Index: head/sys/boot/fdt/dts/arm/armada-380.dtsi =================================================================== --- head/sys/boot/fdt/dts/arm/armada-380.dtsi (revision 319706) +++ head/sys/boot/fdt/dts/arm/armada-380.dtsi (revision 319707) @@ -1,154 +1,163 @@ /* * Device Tree Include file for Marvell Armada 380 SoC. * * Copyright (C) 2014 Marvell * * Lior Amsalem * Gregory CLEMENT * Thomas Petazzoni * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This file is distributed in the hope that it will be useful * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Or, alternatively * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * $FreeBSD$ */ #include "armada-38x.dtsi" / { model = "Marvell Armada 380 family SoC"; compatible = "marvell,armada380"; cpus { #address-cells = <1>; #size-cells = <0>; enable-method = "marvell,armada-380-smp"; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; }; }; soc { internal-regs { pinctrl@18000 { compatible = "marvell,mv88f6810-pinctrl"; }; }; pcie-controller { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci"; #address-cells = <3>; #size-cells = <2>; msi-parent = <&mpic>; bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>; + 0x82000000 0x0 0xf1200000 MBUS_ID(0x08, 0xe8) 0xf1200000 0 0x00100000 /* Port 0 MEM */ + 0x81000000 0x0 0xf1300000 MBUS_ID(0x08, 0xe0) 0xf1300000 0 0x00100000 /* Port 0 IO */ + 0x82000000 0x0 0xf1400000 MBUS_ID(0x04, 0xe8) 0xf1400000 0 0x00100000 /* Port 1 MEM */ + 0x81000000 0x0 0xf1500000 MBUS_ID(0x04, 0xe0) 0xf1500000 0 0x00100000 /* Port 1 IO */ + 0x82000000 0x0 0xf1600000 MBUS_ID(0x04, 0xd8) 0xf1600000 0 0x00100000 /* Port 2 MEM */ + 0x81000000 0x0 0xf1700000 MBUS_ID(0x04, 0xd0) 0xf1700000 0 0x00100000 /* Port 2 IO */ + >; /* x1 port */ pcie@1,0 { + compatible = "mrvl,pcie"; device_type = "pci"; assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; - reg = <0x0800 0 0 0 0>; + reg = <0x0 0x0 0x80000 0x0 0x2000>; #address-cells = <3>; #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; + #interrupt-cells = <3>; + bus-range = <0 255>; + ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1200000 0x0 0x00100000 + 0x81000000 0x0 0x0 0x81000000 0x0 0xf1300000 0x0 0x00100000>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 8>; status = "disabled"; }; /* x1 port */ pcie@2,0 { + compatible = "mrvl,pcie"; device_type = "pci"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x1000 0 0 0 0>; + reg = <0x0 0x0 0x40000 0x0 0x2000>; #address-cells = <3>; #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; + #interrupt-cells = <3>; + bus-range = <0 255>; + ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1400000 0x0 0x00100000 + 0x81000000 0x0 0x0 0x81000000 0x0 0xf1500000 0x0 0x00100000>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; }; /* x1 port */ pcie@3,0 { + compatible = "mrvl,pcie"; device_type = "pci"; assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; - reg = <0x1800 0 0 0 0>; + reg = <0x0 0x0 0x44000 0x0 0x2000>; #address-cells = <3>; #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; + #interrupt-cells = <3>; + bus-range = <0 255>; + ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1600000 0x0 0x00100000 + 0x81000000 0x0 0x0 0x81000000 0x0 0xf1700000 0x0 0x00100000>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; clocks = <&gateclk 6>; status = "disabled"; }; }; }; }; Index: head/sys/boot/fdt/dts/arm/armada-385.dtsi =================================================================== --- head/sys/boot/fdt/dts/arm/armada-385.dtsi (revision 319706) +++ head/sys/boot/fdt/dts/arm/armada-385.dtsi (revision 319707) @@ -1,81 +1,200 @@ /* * Device Tree Include file for Marvell Armada 385 SoC. * * Copyright (C) 2014 Marvell * * Lior Amsalem * Gregory CLEMENT * Thomas Petazzoni * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This file is distributed in the hope that it will be useful * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Or, alternatively * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * $FreeBSD$ */ #include "armada-38x.dtsi" / { model = "Marvell Armada 385 family SoC"; compatible = "marvell,armada385", "marvell,armada380"; cpus { #address-cells = <1>; #size-cells = <0>; enable-method = "marvell,armada-380-smp"; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; }; }; soc { internal-regs { pinctrl@18000 { compatible = "marvell,mv88f6820-pinctrl"; }; }; + + pcie-controller { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 + 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 + 0x82000000 0x0 0xf1200000 MBUS_ID(0x08, 0xe8) 0xf1200000 0 0x00100000 /* Port 0 MEM */ + 0x81000000 0x0 0xf1300000 MBUS_ID(0x08, 0xe0) 0xf1300000 0 0x00100000 /* Port 0 IO */ + 0x82000000 0x0 0xf1400000 MBUS_ID(0x04, 0xe8) 0xf1400000 0 0x00100000 /* Port 1 MEM */ + 0x81000000 0x0 0xf1500000 MBUS_ID(0x04, 0xe0) 0xf1500000 0 0x00100000 /* Port 1 IO */ + 0x82000000 0x0 0xf1600000 MBUS_ID(0x04, 0xd8) 0xf1600000 0 0x00100000 /* Port 2 MEM */ + 0x81000000 0x0 0xf1700000 MBUS_ID(0x04, 0xd0) 0xf1700000 0 0x00100000 /* Port 2 IO */ + 0x82000000 0x0 0xf1800000 MBUS_ID(0x04, 0xb8) 0xf1800000 0 0x00100000 /* Port 3 MEM */ + 0x81000000 0x0 0xf1900000 MBUS_ID(0x04, 0xb0) 0xf1900000 0 0x00100000 /* Port 3 IO */ + >; + + /* + * This port can be either x4 or x1. When + * configured in x4 by the bootloader, then + * pcie@4,0 is not available. + */ + pcie@1,0 { + compatible = "mrvl,pcie"; + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; + reg = <0x0 0x0 0x80000 0x0 0x2000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <3>; + bus-range = <0 255>; + ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1200000 0x0 0x00100000 + 0x81000000 0x0 0x0 0x81000000 0x0 0xf1300000 0x0 0x00100000>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + /* x1 port */ + pcie@2,0 { + compatible = "mrvl,pcie"; + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0 0x0 0x40000 0x0 0x2000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <3>; + bus-range = <0 255>; + ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1400000 0x0 0x00100000 + 0x81000000 0x0 0x0 0x81000000 0x0 0xf1500000 0x0 0x00100000>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + /* x1 port */ + pcie@3,0 { + compatible = "mrvl,pcie"; + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + reg = <0x0 0x0 0x44000 0x0 0x2000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <3>; + bus-range = <0 255>; + ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1600000 0x0 0x00100000 + 0x81000000 0x0 0x0 0x81000000 0x0 0xf1700000 0x0 0x00100000>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + + /* + * x1 port only available when pcie@1,0 is + * configured as a x1 port + */ + pcie@4,0 { + compatible = "mrvl,pcie"; + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; + reg = <0x0 0x0 0x48000 0x0 0x2000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <3>; + bus-range = <0 255>; + ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1800000 0x0 0x00100000 + 0x81000000 0x0 0x0 0x81000000 0x0 0xf1900000 0x0 0x00100000>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + marvell,pcie-port = <3>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 7>; + status = "disabled"; + }; + }; }; + }; Index: head/sys/boot/fdt/dts/arm/armada-388-gp.dts =================================================================== --- head/sys/boot/fdt/dts/arm/armada-388-gp.dts (revision 319706) +++ head/sys/boot/fdt/dts/arm/armada-388-gp.dts (revision 319707) @@ -1,400 +1,421 @@ /* * Device Tree file for Marvell Armada 385 development board * (RD-88F6820-GP) * * Copyright (C) 2014 Marvell * * Gregory CLEMENT * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without * any warranty of any kind, whether express or implied. * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * $FreeBSD$ */ /dts-v1/; #include "armada-388.dtsi" #include / { model = "Marvell Armada 385 GP"; compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380"; chosen { stdout-path = "serial0:115200n8"; }; memory { device_type = "memory"; reg = <0x00000000 0x80000000>; /* 2 GB */ }; soc { ranges = ; internal-regs { crypto@90000 { status = "okay"; }; crypto@92000 { status = "okay"; }; spi@10600 { pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; status = "okay"; spi-flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p128", "jedec,spi-nor"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <50000000>; m25p,fast-read; }; }; i2c@11000 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; status = "okay"; clock-frequency = <100000>; /* * The EEPROM located at adresse 54 is needed * for the boot - DO NOT ERASE IT - */ expander0: pca9555@20 { compatible = "nxp,pca9555"; pinctrl-names = "default"; pinctrl-0 = <&pca0_pins>; interrupt-parent = <&gpio0>; interrupts = <18 IRQ_TYPE_EDGE_FALLING>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x20>; }; expander1: pca9555@21 { compatible = "nxp,pca9555"; pinctrl-names = "default"; interrupt-parent = <&gpio0>; interrupts = <18 IRQ_TYPE_EDGE_FALLING>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x21>; }; }; serial@12000 { /* * Exported on the micro USB connector CON16 * through an FTDI */ pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; }; /* GE1 CON15 */ ethernet@30000 { pinctrl-names = "default"; pinctrl-0 = <&ge1_rgmii_pins>; status = "okay"; phy = <&phy1>; phy-mode = "rgmii-id"; }; /* CON4 */ usb@58000 { vcc-supply = <®_usb2_0_vbus>; status = "okay"; }; /* GE0 CON1 */ ethernet@70000 { pinctrl-names = "default"; /* * The Reference Clock 0 is used to provide a * clock to the PHY */ pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; status = "okay"; phy = <&phy0>; phy-mode = "rgmii-id"; }; mdio@72004 { pinctrl-names = "default"; pinctrl-0 = <&mdio_pins>; phy0: ethernet-phy@1 { reg = <1>; }; phy1: ethernet-phy@0 { reg = <0>; }; }; sata@a8000 { pinctrl-names = "default"; pinctrl-0 = <&sata0_pins>, <&sata1_pins>; status = "okay"; #address-cells = <1>; #size-cells = <0>; sata0: sata-port@0 { reg = <0>; target-supply = <®_5v_sata0>; }; sata1: sata-port@1 { reg = <1>; target-supply = <®_5v_sata1>; }; }; sata@e0000 { pinctrl-names = "default"; pinctrl-0 = <&sata2_pins>, <&sata3_pins>; status = "okay"; #address-cells = <1>; #size-cells = <0>; sata2: sata-port@0 { reg = <0>; target-supply = <®_5v_sata2>; }; sata3: sata-port@1 { reg = <1>; target-supply = <®_5v_sata3>; }; }; sdhci@d8000 { pinctrl-names = "default"; pinctrl-0 = <&sdhci_pins>; cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>; no-1-8-v; wp-inverted; bus-width = <8>; status = "okay"; }; /* CON5 */ usb3@f0000 { vcc-supply = <®_usb2_1_vbus>; status = "okay"; }; /* CON7 */ usb3@f8000 { vcc-supply = <®_usb3_vbus>; status = "okay"; }; }; gpio-fan { compatible = "gpio-fan"; gpios = <&expander1 3 GPIO_ACTIVE_HIGH>; gpio-fan,speed-map = < 0 0 3000 1>; }; - }; + pcie-controller { + status = "okay"; + /* + * One PCIe units is accessible through + * standard PCIe slot on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; - pci0: pcie@f1080000 { - status = "okay"; + /* + * The two other PCIe units are accessible + * through mini PCIe slot on the board. + */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + pcie@3,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + }; }; + reg_usb3_vbus: usb3-vbus { compatible = "regulator-fixed"; regulator-name = "usb3-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; regulator-always-on; gpio = <&expander1 15 GPIO_ACTIVE_HIGH>; }; reg_usb2_0_vbus: v5-vbus0 { compatible = "regulator-fixed"; regulator-name = "v5.0-vbus0"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; regulator-always-on; gpio = <&expander1 14 GPIO_ACTIVE_HIGH>; }; reg_usb2_1_vbus: v5-vbus1 { compatible = "regulator-fixed"; regulator-name = "v5.0-vbus1"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; regulator-always-on; gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; }; reg_usb2_1_vbus: v5-vbus1 { compatible = "regulator-fixed"; regulator-name = "v5.0-vbus1"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; regulator-always-on; gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; }; reg_sata0: pwr-sata0 { compatible = "regulator-fixed"; regulator-name = "pwr_en_sata0"; enable-active-high; regulator-always-on; }; reg_5v_sata0: v5-sata0 { compatible = "regulator-fixed"; regulator-name = "v5.0-sata0"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; vin-supply = <®_sata0>; }; reg_12v_sata0: v12-sata0 { compatible = "regulator-fixed"; regulator-name = "v12.0-sata0"; regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; regulator-always-on; vin-supply = <®_sata0>; }; reg_sata1: pwr-sata1 { regulator-name = "pwr_en_sata1"; compatible = "regulator-fixed"; regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; enable-active-high; regulator-always-on; gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; }; reg_5v_sata1: v5-sata1 { compatible = "regulator-fixed"; regulator-name = "v5.0-sata1"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; vin-supply = <®_sata1>; }; reg_12v_sata1: v12-sata1 { compatible = "regulator-fixed"; regulator-name = "v12.0-sata1"; regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; regulator-always-on; vin-supply = <®_sata1>; }; reg_sata2: pwr-sata2 { compatible = "regulator-fixed"; regulator-name = "pwr_en_sata2"; enable-active-high; regulator-always-on; gpio = <&expander0 11 GPIO_ACTIVE_HIGH>; }; reg_5v_sata2: v5-sata2 { compatible = "regulator-fixed"; regulator-name = "v5.0-sata2"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; vin-supply = <®_sata2>; }; reg_12v_sata2: v12-sata2 { compatible = "regulator-fixed"; regulator-name = "v12.0-sata2"; regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; regulator-always-on; vin-supply = <®_sata2>; }; reg_sata3: pwr-sata3 { compatible = "regulator-fixed"; regulator-name = "pwr_en_sata3"; enable-active-high; regulator-always-on; gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; }; reg_5v_sata3: v5-sata3 { compatible = "regulator-fixed"; regulator-name = "v5.0-sata3"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; vin-supply = <®_sata3>; }; reg_12v_sata3: v12-sata3 { compatible = "regulator-fixed"; regulator-name = "v12.0-sata3"; regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; regulator-always-on; vin-supply = <®_sata3>; }; }; &pinctrl { pca0_pins: pca0_pins { marvell,pins = "mpp18"; marvell,function = "gpio"; }; }; Index: head/sys/boot/fdt/dts/arm/armada-38x.dtsi =================================================================== --- head/sys/boot/fdt/dts/arm/armada-38x.dtsi (revision 319706) +++ head/sys/boot/fdt/dts/arm/armada-38x.dtsi (revision 319707) @@ -1,681 +1,662 @@ /* * Device Tree Include file for Marvell Armada 38x family of SoCs. * * Copyright (C) 2014 Marvell * * Lior Amsalem * Gregory CLEMENT * Thomas Petazzoni * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This file is distributed in the hope that it will be useful * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Or, alternatively * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * $FreeBSD$ */ #include "skeleton.dtsi" #include #include #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) / { model = "Marvell Armada 38x family SoC"; compatible = "marvell,armada380"; aliases { gpio0 = &gpio0; gpio1 = &gpio1; serial0 = &uart0; serial1 = &uart1; sram0 = &SRAM0; sram1 = &SRAM1; }; pmu { compatible = "arm,cortex-a9-pmu"; interrupts-extended = <&mpic 3>; }; SRAM0: sram@f1100000 { compatible = "mrvl,cesa-sram"; reg = <0xf1100000 0x0010000>; }; SRAM1: sram@f1110000 { compatible = "mrvl,cesa-sram"; reg = <0xf1110000 0x0010000>; }; soc { compatible = "marvell,armada380-mbus", "simple-bus"; #address-cells = <2>; #size-cells = <1>; controller = <&mbusc>; interrupt-parent = <&gic>; pcie-mem-aperture = <0xe0000000 0x8000000>; pcie-io-aperture = <0xe8000000 0x100000>; bootrom { compatible = "marvell,bootrom"; reg = ; }; devbus-bootcs { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; #address-cells = <1>; #size-cells = <1>; clocks = <&coreclk 0>; status = "disabled"; }; devbus-cs0 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; #address-cells = <1>; #size-cells = <1>; clocks = <&coreclk 0>; status = "disabled"; }; devbus-cs1 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; #address-cells = <1>; #size-cells = <1>; clocks = <&coreclk 0>; status = "disabled"; }; devbus-cs2 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; #address-cells = <1>; #size-cells = <1>; clocks = <&coreclk 0>; status = "disabled"; }; devbus-cs3 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; #address-cells = <1>; #size-cells = <1>; clocks = <&coreclk 0>; status = "disabled"; }; internal-regs { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; crypto@90000 { compatible = "mrvl,cesa"; reg = <0x90000 0x1000 /* tdma base reg chan 0 */ 0x9D000 0x1000>; /* cesa base reg chan 0 */ interrupts = ; interrupt-parent = <&gic>; sram-handle = <&SRAM0>; status = "disabled"; }; crypto@92000 { compatible = "mrvl,cesa"; reg = <0x92000 0x1000 /* tdma base reg chan 1 */ 0x9F000 0x1000>; /* cesa base reg chan 1 */ interrupts = ; interrupt-parent = <&gic>; sram-handle = <&SRAM1>; status = "disabled"; }; L2: cache-controller@8000 { compatible = "arm,pl310-cache"; reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; }; scu@c000 { compatible = "arm,cortex-a9-scu"; reg = <0xc000 0x58>; }; timer@c200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xc200 0x20>; interrupts = ; clock-frequency = <800000000>; clocks = <&coreclk 2>; }; timer@c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xc600 0x20>; interrupts = ; clock-frequency = <800000000>; clocks = <&coreclk 2>; }; gic: interrupt-controller@d000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; #size-cells = <0>; interrupt-controller; reg = <0xd000 0x1000>, <0xc100 0x100>; }; spi0: spi@10600 { compatible = "marvell,armada-380-spi", "marvell,orion-spi"; reg = <0x10600 0x50>; #address-cells = <1>; #size-cells = <0>; cell-index = <0>; interrupts = ; clocks = <&coreclk 0>; status = "disabled"; }; spi1: spi@10680 { compatible = "marvell,armada-380-spi", "marvell,orion-spi"; reg = <0x10680 0x50>; #address-cells = <1>; #size-cells = <0>; cell-index = <1>; interrupts = ; clocks = <&coreclk 0>; status = "disabled"; }; i2c0: i2c@11000 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11000 0x20>; #address-cells = <1>; #size-cells = <0>; interrupts = ; timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; i2c1: i2c@11100 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11100 0x20>; #address-cells = <1>; #size-cells = <0>; interrupts = ; timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; uart0: serial@12000 { compatible = "snps,dw-apb-uart"; reg = <0x12000 0x100>; reg-shift = <2>; interrupts = ; reg-io-width = <1>; clocks = <&coreclk 0>; status = "disabled"; }; uart1: serial@12100 { compatible = "snps,dw-apb-uart"; reg = <0x12100 0x100>; reg-shift = <2>; interrupts = ; reg-io-width = <1>; clocks = <&coreclk 0>; status = "disabled"; }; pinctrl: pinctrl@18000 { reg = <0x18000 0x20>; ge0_rgmii_pins: ge-rgmii-pins-0 { marvell,pins = "mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp11", "mpp12", "mpp13", "mpp14", "mpp15", "mpp16", "mpp17"; marvell,function = "ge0"; }; ge1_rgmii_pins: ge-rgmii-pins-1 { marvell,pins = "mpp21", "mpp27", "mpp28", "mpp29", "mpp30", "mpp31", "mpp32", "mpp37", "mpp38", "mpp39", "mpp40", "mpp41"; marvell,function = "ge1"; }; i2c0_pins: i2c-pins-0 { marvell,pins = "mpp2", "mpp3"; marvell,function = "i2c0"; }; mdio_pins: mdio-pins { marvell,pins = "mpp4", "mpp5"; marvell,function = "ge"; }; ref_clk0_pins: ref-clk-pins-0 { marvell,pins = "mpp45"; marvell,function = "ref"; }; ref_clk1_pins: ref-clk-pins-1 { marvell,pins = "mpp46"; marvell,function = "ref"; }; spi0_pins: spi-pins-0 { marvell,pins = "mpp22", "mpp23", "mpp24", "mpp25"; marvell,function = "spi0"; }; spi1_pins: spi-pins-1 { marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59"; marvell,function = "spi1"; }; uart0_pins: uart-pins-0 { marvell,pins = "mpp0", "mpp1"; marvell,function = "ua0"; }; uart1_pins: uart-pins-1 { marvell,pins = "mpp19", "mpp20"; marvell,function = "ua1"; }; sdhci_pins: sdhci-pins { marvell,pins = "mpp48", "mpp49", "mpp50", "mpp52", "mpp53", "mpp54", "mpp55", "mpp57", "mpp58", "mpp59"; marvell,function = "sd0"; }; sata0_pins: sata-pins-0 { marvell,pins = "mpp20"; marvell,function = "sata0"; }; sata1_pins: sata-pins-1 { marvell,pins = "mpp19"; marvell,function = "sata1"; }; sata2_pins: sata-pins-2 { marvell,pins = "mpp47"; marvell,function = "sata2"; }; sata3_pins: sata-pins-3 { marvell,pins = "mpp44"; marvell,function = "sata3"; }; }; gpio0: gpio@18100 { compatible = "marvell,orion-gpio"; reg = <0x18100 0x40>; ngpios = <32>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = , , , ; }; gpio1: gpio@18140 { compatible = "marvell,orion-gpio"; reg = <0x18140 0x40>; ngpios = <28>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = , , , ; }; system-controller@18200 { compatible = "marvell,armada-380-system-controller", "marvell,armada-370-xp-system-controller"; reg = <0x18200 0x100>; }; gateclk: clock-gating-control@18220 { compatible = "marvell,armada-380-gating-clock"; reg = <0x18220 0x4>; clocks = <&coreclk 0>; #clock-cells = <1>; }; coreclk: mvebu-sar@18600 { compatible = "marvell,armada-380-core-clock"; reg = <0x18600 0x04>; #clock-cells = <1>; }; mbusc: mbus-controller@20000 { compatible = "marvell,mbus-controller"; reg = <0x20000 0x100>, <0x20180 0x20>; }; mpic: interrupt-controller@20a00 { compatible = "marvell,mpic"; reg = <0x20a00 0x2d0>, <0x21870 0x58>; #interrupt-cells = <1>; #size-cells = <1>; interrupt-controller; msi-controller; interrupts = ; }; timer@20300 { compatible = "marvell,armada-380-timer", "marvell,armada-xp-timer"; reg = <0x20300 0x30>, <0x21040 0x30>; interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <&mpic 5>, <&mpic 6>; clocks = <&coreclk 2>, <&refclk>; clock-names = "nbclk", "fixed"; }; watchdog@20300 { compatible = "marvell,armada-380-wdt"; reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; clocks = <&coreclk 2>, <&refclk>; clock-names = "nbclk", "fixed"; }; cpurst@20800 { compatible = "marvell,armada-370-cpu-reset"; reg = <0x20800 0x10>; }; mpcore-soc-ctrl@20d20 { compatible = "marvell,armada-380-mpcore-soc-ctrl"; reg = <0x20d20 0x6c>; }; coherency-fabric@21010 { compatible = "marvell,armada-380-coherency-fabric"; reg = <0x21010 0x1c>; }; pmsu@22000 { compatible = "marvell,armada-380-pmsu"; reg = <0x22000 0x1000>; }; eth1: ethernet@30000 { compatible = "marvell,armada-370-neta"; reg = <0x30000 0x4000>; interrupts-extended = <&mpic 10>; clocks = <&gateclk 3>; status = "disabled"; }; eth2: ethernet@34000 { compatible = "marvell,armada-370-neta"; reg = <0x34000 0x4000>; interrupts-extended = <&mpic 12>; clocks = <&gateclk 2>; status = "disabled"; }; usb@58000 { compatible = "marvell,orion-ehci"; reg = <0x58000 0x500>; interrupts = ; clocks = <&gateclk 18>; status = "disabled"; }; xor@60800 { compatible = "marvell,orion-xor"; reg = <0x60800 0x100 0x60a00 0x100>; clocks = <&gateclk 22>; status = "okay"; xor00 { interrupts = ; dmacap,memcpy; dmacap,xor; }; xor01 { interrupts = ; dmacap,memcpy; dmacap,xor; dmacap,memset; }; }; xor@60900 { compatible = "marvell,orion-xor"; reg = <0x60900 0x100 0x60b00 0x100>; clocks = <&gateclk 28>; status = "okay"; xor10 { interrupts = ; dmacap,memcpy; dmacap,xor; }; xor11 { interrupts = ; dmacap,memcpy; dmacap,xor; dmacap,memset; }; }; eth0: ethernet@70000 { compatible = "marvell,armada-370-neta"; reg = <0x70000 0x4000>; interrupts-extended = <&mpic 8>; clocks = <&gateclk 4>; status = "disabled"; }; mdio: mdio@72004 { #address-cells = <1>; #size-cells = <0>; compatible = "marvell,orion-mdio"; reg = <0x72004 0x4>; clocks = <&gateclk 4>; }; rtc@a3800 { compatible = "marvell,armada-380-rtc"; reg = <0xa3800 0x20>, <0x184a0 0x0c>; reg-names = "rtc", "rtc-soc"; interrupts = ; }; sata@a8000 { compatible = "marvell,armada-380-ahci"; reg = <0xa8000 0x2000>; interrupts = ; clocks = <&gateclk 15>; status = "disabled"; }; bm: bm@c8000 { compatible = "marvell,armada-380-neta-bm"; reg = <0xc8000 0xac>; clocks = <&gateclk 13>; internal-mem = <&bm_bppi>; status = "disabled"; }; sata@e0000 { compatible = "marvell,armada-380-ahci"; reg = <0xe0000 0x2000>; interrupts = ; clocks = <&gateclk 30>; status = "disabled"; }; coredivclk: clock@e4250 { compatible = "marvell,armada-380-corediv-clock"; reg = <0xe4250 0xc>; #clock-cells = <1>; clocks = <&mainpll>; clock-output-names = "nand"; }; thermal@e8078 { compatible = "marvell,armada380-thermal"; reg = <0xe4078 0x4>, <0xe4074 0x4>; status = "okay"; }; flash@d0000 { compatible = "marvell,armada370-nand"; reg = <0xd0000 0x54>; #address-cells = <1>; #size-cells = <1>; interrupts = ; clocks = <&coredivclk 0>; status = "disabled"; }; sdhci@d8000 { compatible = "marvell,armada-380-sdhci"; reg-names = "sdhci", "mbus", "conf-sdio3"; reg = <0xd8000 0x1000>, <0xdc000 0x100>, <0x18454 0x4>; interrupts = ; clocks = <&gateclk 17>; mrvl,clk-delay-cycles = <0x1F>; status = "disabled"; }; usb3@f0000 { compatible = "marvell,armada-380-xhci"; reg = <0xf0000 0x4000>,<0xf4000 0x4000>; interrupts = ; clocks = <&gateclk 9>; status = "disabled"; }; usb3@f8000 { compatible = "marvell,armada-380-xhci"; reg = <0xf8000 0x4000>,<0xfc000 0x4000>; interrupts = ; clocks = <&gateclk 10>; status = "disabled"; }; }; bm_bppi: bm-bppi { compatible = "mmio-sram"; reg = ; ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; #address-cells = <1>; #size-cells = <1>; clocks = <&gateclk 13>; no-memory-wc; status = "disabled"; }; }; - pci0: pcie@f1080000 { - compatible = "mrvl,pcie"; - status = "disabled"; - device_type = "pci"; - #interrupt-cells = <3>; - #size-cells = <2>; - #address-cells = <3>; - reg = <0xf1080000 0x2000>; - bus-range = <0 255>; - ranges = <0x42000000 0x0 0xf1200000 0xf1200000 0x0 0x00100000 - 0x41000000 0x0 0x00000000 0xf1300000 0x0 0x00100000>; - interrupt-parent = <&gic>; - interrupts = ; - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; - interrupt-map = < - 0x0000 0x0 0x0 0x1 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH - >; - }; - clocks { /* 2 GHz fixed main PLL */ mainpll: mainpll { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000000>; }; /* 25 MHz reference crystal */ refclk: oscillator { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; }; };