Index: stable/11/sys/arm/arm/identcpu.c =================================================================== --- stable/11/sys/arm/arm/identcpu.c (revision 314524) +++ stable/11/sys/arm/arm/identcpu.c (nonexistent) @@ -1,534 +0,0 @@ -/* $NetBSD: cpu.c,v 1.55 2004/02/13 11:36:10 wiz Exp $ */ - -/*- - * Copyright (c) 1995 Mark Brinicombe. - * Copyright (c) 1995 Brini. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Brini. - * 4. The name of the company nor the name of the author may be used to - * endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * RiscBSD kernel project - * - * cpu.c - * - * Probing and configuration for the master CPU - * - * Created : 10/10/95 - */ - -#include -__FBSDID("$FreeBSD$"); -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -char machine[] = "arm"; - -SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, - machine, 0, "Machine class"); - -static const char * const generic_steppings[16] = { - "rev 0", "rev 1", "rev 2", "rev 3", - "rev 4", "rev 5", "rev 6", "rev 7", - "rev 8", "rev 9", "rev 10", "rev 11", - "rev 12", "rev 13", "rev 14", "rev 15", -}; - -static const char * const xscale_steppings[16] = { - "step A-0", "step A-1", "step B-0", "step C-0", - "step D-0", "rev 5", "rev 6", "rev 7", - "rev 8", "rev 9", "rev 10", "rev 11", - "rev 12", "rev 13", "rev 14", "rev 15", -}; - -static const char * const i80219_steppings[16] = { - "step A-0", "rev 1", "rev 2", "rev 3", - "rev 4", "rev 5", "rev 6", "rev 7", - "rev 8", "rev 9", "rev 10", "rev 11", - "rev 12", "rev 13", "rev 14", "rev 15", -}; - -static const char * const i80321_steppings[16] = { - "step A-0", "step B-0", "rev 2", "rev 3", - "rev 4", "rev 5", "rev 6", "rev 7", - "rev 8", "rev 9", "rev 10", "rev 11", - "rev 12", "rev 13", "rev 14", "rev 15", -}; - -static const char * const i81342_steppings[16] = { - "step A-0", "rev 1", "rev 2", "rev 3", - "rev 4", "rev 5", "rev 6", "rev 7", - "rev 8", "rev 9", "rev 10", "rev 11", - "rev 12", "rev 13", "rev 14", "rev 15", -}; - -/* Steppings for PXA2[15]0 */ -static const char * const pxa2x0_steppings[16] = { - "step A-0", "step A-1", "step B-0", "step B-1", - "step B-2", "step C-0", "rev 6", "rev 7", - "rev 8", "rev 9", "rev 10", "rev 11", - "rev 12", "rev 13", "rev 14", "rev 15", -}; - -/* Steppings for PXA255/26x. - * rev 5: PXA26x B0, rev 6: PXA255 A0 - */ -static const char * const pxa255_steppings[16] = { - "rev 0", "rev 1", "rev 2", "step A-0", - "rev 4", "step B-0", "step A-0", "rev 7", - "rev 8", "rev 9", "rev 10", "rev 11", - "rev 12", "rev 13", "rev 14", "rev 15", -}; - -/* Stepping for PXA27x */ -static const char * const pxa27x_steppings[16] = { - "step A-0", "step A-1", "step B-0", "step B-1", - "step C-0", "rev 5", "rev 6", "rev 7", - "rev 8", "rev 9", "rev 10", "rev 11", - "rev 12", "rev 13", "rev 14", "rev 15", -}; - -static const char * const ixp425_steppings[16] = { - "step 0 (A0)", "rev 1 (ARMv5TE)", "rev 2", "rev 3", - "rev 4", "rev 5", "rev 6", "rev 7", - "rev 8", "rev 9", "rev 10", "rev 11", - "rev 12", "rev 13", "rev 14", "rev 15", -}; - -struct cpuidtab { - u_int32_t cpuid; - enum cpu_class cpu_class; - const char *cpu_name; - const char * const *cpu_steppings; -}; - -const struct cpuidtab cpuids[] = { - { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", - generic_steppings }, - { CPU_ID_ARM920T_ALT, CPU_CLASS_ARM9TDMI, "ARM920T", - generic_steppings }, - { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", - generic_steppings }, - { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S", - generic_steppings }, - { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", - generic_steppings }, - { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", - generic_steppings }, - { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", - generic_steppings }, - { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", - generic_steppings }, - { CPU_ID_FA526, CPU_CLASS_ARM9TDMI, "FA526", - generic_steppings }, - { CPU_ID_FA626TE, CPU_CLASS_ARM9ES, "FA626TE", - generic_steppings }, - - { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T", - generic_steppings }, - - { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E", - generic_steppings }, - { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S", - generic_steppings }, - { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S", - generic_steppings }, - - { CPU_ID_CORTEXA5, CPU_CLASS_CORTEXA, "Cortex A5", - generic_steppings }, - { CPU_ID_CORTEXA7, CPU_CLASS_CORTEXA, "Cortex A7", - generic_steppings }, - { CPU_ID_CORTEXA8R1, CPU_CLASS_CORTEXA, "Cortex A8-r1", - generic_steppings }, - { CPU_ID_CORTEXA8R2, CPU_CLASS_CORTEXA, "Cortex A8-r2", - generic_steppings }, - { CPU_ID_CORTEXA8R3, CPU_CLASS_CORTEXA, "Cortex A8-r3", - generic_steppings }, - { CPU_ID_CORTEXA9R1, CPU_CLASS_CORTEXA, "Cortex A9-r1", - generic_steppings }, - { CPU_ID_CORTEXA9R2, CPU_CLASS_CORTEXA, "Cortex A9-r2", - generic_steppings }, - { CPU_ID_CORTEXA9R3, CPU_CLASS_CORTEXA, "Cortex A9-r3", - generic_steppings }, - { CPU_ID_CORTEXA9R4, CPU_CLASS_CORTEXA, "Cortex A9-r4", - generic_steppings }, - { CPU_ID_CORTEXA12R0, CPU_CLASS_CORTEXA, "Cortex A12-r0", - generic_steppings }, - { CPU_ID_CORTEXA15R0, CPU_CLASS_CORTEXA, "Cortex A15-r0", - generic_steppings }, - { CPU_ID_CORTEXA15R1, CPU_CLASS_CORTEXA, "Cortex A15-r1", - generic_steppings }, - { CPU_ID_CORTEXA15R2, CPU_CLASS_CORTEXA, "Cortex A15-r2", - generic_steppings }, - { CPU_ID_CORTEXA15R3, CPU_CLASS_CORTEXA, "Cortex A15-r3", - generic_steppings }, - { CPU_ID_KRAIT300R0, CPU_CLASS_KRAIT, "Krait 300-r0", - generic_steppings }, - { CPU_ID_KRAIT300R1, CPU_CLASS_KRAIT, "Krait 300-r1", - generic_steppings }, - - { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", - xscale_steppings }, - - { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", - i80321_steppings }, - { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", - i80321_steppings }, - { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", - i80321_steppings }, - { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", - i80321_steppings }, - - { CPU_ID_81342, CPU_CLASS_XSCALE, "i81342", - i81342_steppings }, - - { CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz", - i80219_steppings }, - { CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz", - i80219_steppings }, - - { CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x", - pxa27x_steppings }, - { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", - pxa2x0_steppings }, - { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", - pxa2x0_steppings }, - { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250", - pxa2x0_steppings }, - { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210", - pxa2x0_steppings }, - { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA255", - pxa255_steppings }, - { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", - pxa2x0_steppings }, - - { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz", - ixp425_steppings }, - { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz", - ixp425_steppings }, - { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", - ixp425_steppings }, - - /* XXX ixp435 steppings? */ - { CPU_ID_IXP435, CPU_CLASS_XSCALE, "IXP435", - ixp425_steppings }, - - { CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S", - generic_steppings }, - { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S R1", - generic_steppings }, - { CPU_ID_ARM1176JZS, CPU_CLASS_ARM11J, "ARM1176JZ-S", - generic_steppings }, - - { CPU_ID_MV88FR131, CPU_CLASS_MARVELL, "Feroceon 88FR131", - generic_steppings }, - - { CPU_ID_MV88FR571_VD, CPU_CLASS_MARVELL, "Feroceon 88FR571-VD", - generic_steppings }, - { CPU_ID_MV88SV581X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV581x", - generic_steppings }, - { CPU_ID_ARM_88SV581X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV581x", - generic_steppings }, - { CPU_ID_MV88SV584X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV584x", - generic_steppings }, - - { 0, CPU_CLASS_NONE, NULL, NULL } -}; - -struct cpu_classtab { - const char *class_name; - const char *class_option; -}; - -const struct cpu_classtab cpu_classes[] = { - { "unknown", NULL }, /* CPU_CLASS_NONE */ - { "ARM9TDMI", "CPU_ARM9TDMI" }, /* CPU_CLASS_ARM9TDMI */ - { "ARM9E-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9ES */ - { "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */ - { "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */ - { "ARM10EJ", "CPU_ARM10" }, /* CPU_CLASS_ARM10EJ */ - { "Cortex-A", "CPU_CORTEXA" }, /* CPU_CLASS_CORTEXA */ - { "Krait", "CPU_KRAIT" }, /* CPU_CLASS_KRAIT */ - { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ - { "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */ - { "Marvell", "CPU_MARVELL" }, /* CPU_CLASS_MARVELL */ -}; - -/* - * Report the type of the specified arm processor. This uses the generic and - * arm specific information in the cpu structure to identify the processor. - * The remaining fields in the cpu structure are filled in appropriately. - */ - -static const char * const wtnames[] = { - "write-through", - "write-back", - "write-back", - "**unknown 3**", - "**unknown 4**", - "write-back-locking", /* XXX XScale-specific? */ - "write-back-locking-A", - "write-back-locking-B", - "**unknown 8**", - "**unknown 9**", - "**unknown 10**", - "**unknown 11**", - "**unknown 12**", - "**unknown 13**", - "write-back-locking-C", - "**unknown 15**", -}; - -static void -print_enadis(int enadis, char *s) -{ - - printf(" %s %sabled", s, (enadis == 0) ? "dis" : "en"); -} - -enum cpu_class cpu_class = CPU_CLASS_NONE; - -u_int cpu_pfr(int num) -{ - u_int feat; - - switch (num) { - case 0: - __asm __volatile("mrc p15, 0, %0, c0, c1, 0" - : "=r" (feat)); - break; - case 1: - __asm __volatile("mrc p15, 0, %0, c0, c1, 1" - : "=r" (feat)); - break; - default: - panic("Processor Feature Register %d not implemented", num); - break; - } - - return (feat); -} - -static -void identify_armv7(void) -{ - u_int feature; - - printf("Supported features:"); - /* Get Processor Feature Register 0 */ - feature = cpu_pfr(0); - - if (feature & ARM_PFR0_ARM_ISA_MASK) - printf(" ARM_ISA"); - - if (feature & ARM_PFR0_THUMB2) - printf(" THUMB2"); - else if (feature & ARM_PFR0_THUMB) - printf(" THUMB"); - - if (feature & ARM_PFR0_JAZELLE_MASK) - printf(" JAZELLE"); - - if (feature & ARM_PFR0_THUMBEE_MASK) - printf(" THUMBEE"); - - - /* Get Processor Feature Register 1 */ - feature = cpu_pfr(1); - - if (feature & ARM_PFR1_ARMV4_MASK) - printf(" ARMv4"); - - if (feature & ARM_PFR1_SEC_EXT_MASK) - printf(" Security_Ext"); - - if (feature & ARM_PFR1_MICROCTRL_MASK) - printf(" M_profile"); - - printf("\n"); -} - -void -identify_arm_cpu(void) -{ - u_int cpuid, reg, size, sets, ways; - u_int8_t type, linesize, ctrl; - int i; - - ctrl = cpu_get_control(); - cpuid = cpu_ident(); - - if (cpuid == 0) { - printf("Processor failed probe - no CPU ID\n"); - return; - } - - for (i = 0; cpuids[i].cpuid != 0; i++) - if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { - cpu_class = cpuids[i].cpu_class; - printf("CPU: %s %s (%s core)\n", - cpuids[i].cpu_name, - cpuids[i].cpu_steppings[cpuid & - CPU_ID_REVISION_MASK], - cpu_classes[cpu_class].class_name); - break; - } - if (cpuids[i].cpuid == 0) - printf("unknown CPU (ID = 0x%x)\n", cpuid); - - printf(" "); - - if ((cpuid & CPU_ID_ARCH_MASK) == CPU_ID_CPUID_SCHEME) { - identify_armv7(); - } else { - if (ctrl & CPU_CONTROL_BEND_ENABLE) - printf(" Big-endian"); - else - printf(" Little-endian"); - - switch (cpu_class) { - case CPU_CLASS_ARM9TDMI: - case CPU_CLASS_ARM9ES: - case CPU_CLASS_ARM9EJS: - case CPU_CLASS_ARM10E: - case CPU_CLASS_ARM10EJ: - case CPU_CLASS_XSCALE: - case CPU_CLASS_ARM11J: - case CPU_CLASS_MARVELL: - print_enadis(ctrl & CPU_CONTROL_DC_ENABLE, "DC"); - print_enadis(ctrl & CPU_CONTROL_IC_ENABLE, "IC"); -#ifdef CPU_XSCALE_81342 - print_enadis(ctrl & CPU_CONTROL_L2_ENABLE, "L2"); -#endif -#if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) - i = sheeva_control_ext(0, 0); - print_enadis(i & MV_WA_ENABLE, "WA"); - print_enadis(i & MV_DC_STREAM_ENABLE, "DC streaming"); - printf("\n "); - print_enadis((i & MV_BTB_DISABLE) == 0, "BTB"); - print_enadis(i & MV_L2_ENABLE, "L2"); - print_enadis((i & MV_L2_PREFETCH_DISABLE) == 0, - "L2 prefetch"); - printf("\n "); -#endif - break; - default: - break; - } - } - - print_enadis(ctrl & CPU_CONTROL_WBUF_ENABLE, "WB"); - if (ctrl & CPU_CONTROL_LABT_ENABLE) - printf(" LABT"); - else - printf(" EABT"); - - print_enadis(ctrl & CPU_CONTROL_BPRD_ENABLE, "branch prediction"); - printf("\n"); - - if (arm_cache_level) { - printf("LoUU:%d LoC:%d LoUIS:%d \n", CPU_CLIDR_LOUU(arm_cache_level) + 1, - arm_cache_loc + 1, CPU_CLIDR_LOUIS(arm_cache_level) + 1); - i = 0; - while (((type = CPU_CLIDR_CTYPE(arm_cache_level, i)) != 0) && i < 7) { - printf("Cache level %d: \n", i + 1); - if (type == CACHE_DCACHE || type == CACHE_UNI_CACHE || - type == CACHE_SEP_CACHE) { - reg = arm_cache_type[2 * i]; - ways = CPUV7_CT_xSIZE_ASSOC(reg) + 1; - sets = CPUV7_CT_xSIZE_SET(reg) + 1; - linesize = 1 << (CPUV7_CT_xSIZE_LEN(reg) + 4); - size = (ways * sets * linesize) / 1024; - - if (type == CACHE_UNI_CACHE) - printf(" %dKB/%dB %d-way unified cache", size, linesize,ways); - else - printf(" %dKB/%dB %d-way data cache", size, linesize, ways); - if (reg & CPUV7_CT_CTYPE_WT) - printf(" WT"); - if (reg & CPUV7_CT_CTYPE_WB) - printf(" WB"); - if (reg & CPUV7_CT_CTYPE_RA) - printf(" Read-Alloc"); - if (reg & CPUV7_CT_CTYPE_WA) - printf(" Write-Alloc"); - printf("\n"); - } - - if (type == CACHE_ICACHE || type == CACHE_SEP_CACHE) { - reg = arm_cache_type[(2 * i) + 1]; - - ways = CPUV7_CT_xSIZE_ASSOC(reg) + 1; - sets = CPUV7_CT_xSIZE_SET(reg) + 1; - linesize = 1 << (CPUV7_CT_xSIZE_LEN(reg) + 4); - size = (ways * sets * linesize) / 1024; - - printf(" %dKB/%dB %d-way instruction cache", size, linesize, ways); - if (reg & CPUV7_CT_CTYPE_WT) - printf(" WT"); - if (reg & CPUV7_CT_CTYPE_WB) - printf(" WB"); - if (reg & CPUV7_CT_CTYPE_RA) - printf(" Read-Alloc"); - if (reg & CPUV7_CT_CTYPE_WA) - printf(" Write-Alloc"); - printf("\n"); - } - i++; - } - } else { - /* Print cache info. */ - if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) - return; - - if (arm_pcache_unified) { - printf(" %dKB/%dB %d-way %s unified cache\n", - arm_pdcache_size / 1024, - arm_pdcache_line_size, arm_pdcache_ways, - wtnames[arm_pcache_type]); - } else { - printf(" %dKB/%dB %d-way instruction cache\n", - arm_picache_size / 1024, - arm_picache_line_size, arm_picache_ways); - printf(" %dKB/%dB %d-way %s data cache\n", - arm_pdcache_size / 1024, - arm_pdcache_line_size, arm_pdcache_ways, - wtnames[arm_pcache_type]); - } - } -} Property changes on: stable/11/sys/arm/arm/identcpu.c ___________________________________________________________________ Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Index: stable/11/sys/arm/arm/cpuinfo.c =================================================================== --- stable/11/sys/arm/arm/cpuinfo.c (revision 314524) +++ stable/11/sys/arm/arm/cpuinfo.c (revision 314525) @@ -1,233 +1,238 @@ /*- * Copyright 2014 Svatopluk Kraus * Copyright 2014 Michal Meloun * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include struct cpuinfo cpuinfo = { /* Use safe defaults for start */ .dcache_line_size = 32, .dcache_line_mask = 31, .icache_line_size = 32, .icache_line_mask = 31, }; /* Read and parse CPU id scheme */ void cpuinfo_init(void) { cpuinfo.midr = cp15_midr_get(); /* Test old version id schemes first */ if ((cpuinfo.midr & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD) { if (CPU_ID_ISOLD(cpuinfo.midr)) { /* obsolete ARMv2 or ARMv3 CPU */ cpuinfo.midr = 0; return; } if (CPU_ID_IS7(cpuinfo.midr)) { if ((cpuinfo.midr & (1 << 23)) == 0) { /* obsolete ARMv3 CPU */ cpuinfo.midr = 0; return; } /* ARMv4T CPU */ cpuinfo.architecture = 1; cpuinfo.revision = (cpuinfo.midr >> 16) & 0x7F; } else { /* ARM new id scheme */ cpuinfo.architecture = (cpuinfo.midr >> 16) & 0x0F; cpuinfo.revision = (cpuinfo.midr >> 20) & 0x0F; } } else { /* non ARM -> must be new id scheme */ cpuinfo.architecture = (cpuinfo.midr >> 16) & 0x0F; cpuinfo.revision = (cpuinfo.midr >> 20) & 0x0F; } /* Parse rest of MIDR */ cpuinfo.implementer = (cpuinfo.midr >> 24) & 0xFF; cpuinfo.part_number = (cpuinfo.midr >> 4) & 0xFFF; cpuinfo.patch = cpuinfo.midr & 0x0F; /* CP15 c0,c0 regs 0-7 exist on all CPUs (although aliased with MIDR) */ cpuinfo.ctr = cp15_ctr_get(); cpuinfo.tcmtr = cp15_tcmtr_get(); #if __ARM_ARCH >= 6 cpuinfo.tlbtr = cp15_tlbtr_get(); cpuinfo.mpidr = cp15_mpidr_get(); cpuinfo.revidr = cp15_revidr_get(); #endif /* if CPU is not v7 cpu id scheme */ if (cpuinfo.architecture != 0xF) return; #if __ARM_ARCH >= 6 cpuinfo.id_pfr0 = cp15_id_pfr0_get(); cpuinfo.id_pfr1 = cp15_id_pfr1_get(); cpuinfo.id_dfr0 = cp15_id_dfr0_get(); cpuinfo.id_afr0 = cp15_id_afr0_get(); cpuinfo.id_mmfr0 = cp15_id_mmfr0_get(); cpuinfo.id_mmfr1 = cp15_id_mmfr1_get(); cpuinfo.id_mmfr2 = cp15_id_mmfr2_get(); cpuinfo.id_mmfr3 = cp15_id_mmfr3_get(); cpuinfo.id_isar0 = cp15_id_isar0_get(); cpuinfo.id_isar1 = cp15_id_isar1_get(); cpuinfo.id_isar2 = cp15_id_isar2_get(); cpuinfo.id_isar3 = cp15_id_isar3_get(); cpuinfo.id_isar4 = cp15_id_isar4_get(); cpuinfo.id_isar5 = cp15_id_isar5_get(); /* Not yet - CBAR only exist on ARM SMP Cortex A CPUs cpuinfo.cbar = cp15_cbar_get(); */ + if (CPU_CT_FORMAT(cpuinfo.ctr) == CPU_CT_ARMV7) { + cpuinfo.ccsidr = cp15_ccsidr_get(); + cpuinfo.clidr = cp15_clidr_get(); + } /* Test if revidr is implemented */ if (cpuinfo.revidr == cpuinfo.midr) cpuinfo.revidr = 0; /* parsed bits of above registers */ /* id_mmfr0 */ cpuinfo.outermost_shareability = (cpuinfo.id_mmfr0 >> 8) & 0xF; cpuinfo.shareability_levels = (cpuinfo.id_mmfr0 >> 12) & 0xF; cpuinfo.auxiliary_registers = (cpuinfo.id_mmfr0 >> 20) & 0xF; cpuinfo.innermost_shareability = (cpuinfo.id_mmfr0 >> 28) & 0xF; /* id_mmfr2 */ cpuinfo.mem_barrier = (cpuinfo.id_mmfr2 >> 20) & 0xF; /* id_mmfr3 */ cpuinfo.coherent_walk = (cpuinfo.id_mmfr3 >> 20) & 0xF; cpuinfo.maintenance_broadcast =(cpuinfo.id_mmfr3 >> 12) & 0xF; /* id_pfr1 */ cpuinfo.generic_timer_ext = (cpuinfo.id_pfr1 >> 16) & 0xF; cpuinfo.virtualization_ext = (cpuinfo.id_pfr1 >> 12) & 0xF; cpuinfo.security_ext = (cpuinfo.id_pfr1 >> 4) & 0xF; /* L1 Cache sizes */ if (CPU_CT_FORMAT(cpuinfo.ctr) == CPU_CT_ARMV7) { cpuinfo.dcache_line_size = 1 << (CPU_CT_DMINLINE(cpuinfo.ctr) + 2); cpuinfo.icache_line_size = 1 << (CPU_CT_IMINLINE(cpuinfo.ctr) + 2); } else { cpuinfo.dcache_line_size = 1 << (CPU_CT_xSIZE_LEN(CPU_CT_DSIZE(cpuinfo.ctr)) + 3); cpuinfo.icache_line_size = 1 << (CPU_CT_xSIZE_LEN(CPU_CT_ISIZE(cpuinfo.ctr)) + 3); } cpuinfo.dcache_line_mask = cpuinfo.dcache_line_size - 1; cpuinfo.icache_line_mask = cpuinfo.icache_line_size - 1; #endif } /* * Get bits that must be set or cleared in ACLR register. * Note: Bits in ACLR register are IMPLEMENTATION DEFINED. * Its expected that SCU is in operational state before this * function is called. */ void cpuinfo_get_actlr_modifier(uint32_t *actlr_mask, uint32_t *actlr_set) { *actlr_mask = 0; *actlr_set = 0; if (cpuinfo.implementer == CPU_IMPLEMENTER_ARM) { switch (cpuinfo.part_number) { + case CPU_ARCH_CORTEX_A73: case CPU_ARCH_CORTEX_A72: case CPU_ARCH_CORTEX_A57: case CPU_ARCH_CORTEX_A53: /* Nothing to do for AArch32 */ break; case CPU_ARCH_CORTEX_A17: case CPU_ARCH_CORTEX_A12: /* A12 is merged to A17 */ /* * Enable SMP mode */ *actlr_mask = (1 << 6); *actlr_set = (1 << 6); break; case CPU_ARCH_CORTEX_A15: /* * Enable snoop-delayed exclusive handling * Enable SMP mode */ *actlr_mask = (1U << 31) |(1 << 6); *actlr_set = (1U << 31) |(1 << 6); break; case CPU_ARCH_CORTEX_A9: /* * Disable exclusive L1/L2 cache control * Enable SMP mode * Enable Cache and TLB maintenance broadcast */ *actlr_mask = (1 << 7) | (1 << 6) | (1 << 0); *actlr_set = (1 << 6) | (1 << 0); break; case CPU_ARCH_CORTEX_A8: /* * Enable L2 cache * Enable L1 data cache hardware alias checks */ *actlr_mask = (1 << 1) | (1 << 0); *actlr_set = (1 << 1); break; case CPU_ARCH_CORTEX_A7: /* * Enable SMP mode */ *actlr_mask = (1 << 6); *actlr_set = (1 << 6); break; case CPU_ARCH_CORTEX_A5: /* * Disable exclusive L1/L2 cache control * Enable SMP mode * Enable Cache and TLB maintenance broadcast */ *actlr_mask = (1 << 7) | (1 << 6) | (1 << 0); *actlr_set = (1 << 6) | (1 << 0); break; case CPU_ARCH_ARM1176: /* * Restrict cache size to 16KB * Enable the return stack * Enable dynamic branch prediction * Enable static branch prediction */ *actlr_mask = (1 << 6) | (1 << 2) | (1 << 1) | (1 << 0); *actlr_set = (1 << 6) | (1 << 2) | (1 << 1) | (1 << 0); break; } return; } } Index: stable/11/sys/arm/arm/identcpu-v4.c =================================================================== --- stable/11/sys/arm/arm/identcpu-v4.c (nonexistent) +++ stable/11/sys/arm/arm/identcpu-v4.c (revision 314525) @@ -0,0 +1,386 @@ +/* $NetBSD: cpu.c,v 1.55 2004/02/13 11:36:10 wiz Exp $ */ + +/*- + * Copyright (c) 1995 Mark Brinicombe. + * Copyright (c) 1995 Brini. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * RiscBSD kernel project + * + * cpu.c + * + * Probing and configuration for the master CPU + * + * Created : 10/10/95 + */ + +#include +__FBSDID("$FreeBSD$"); +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +char machine[] = "arm"; + +SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, + machine, 0, "Machine class"); + +static const char * const generic_steppings[16] = { + "rev 0", "rev 1", "rev 2", "rev 3", + "rev 4", "rev 5", "rev 6", "rev 7", + "rev 8", "rev 9", "rev 10", "rev 11", + "rev 12", "rev 13", "rev 14", "rev 15", +}; + +static const char * const xscale_steppings[16] = { + "step A-0", "step A-1", "step B-0", "step C-0", + "step D-0", "rev 5", "rev 6", "rev 7", + "rev 8", "rev 9", "rev 10", "rev 11", + "rev 12", "rev 13", "rev 14", "rev 15", +}; + +static const char * const i80219_steppings[16] = { + "step A-0", "rev 1", "rev 2", "rev 3", + "rev 4", "rev 5", "rev 6", "rev 7", + "rev 8", "rev 9", "rev 10", "rev 11", + "rev 12", "rev 13", "rev 14", "rev 15", +}; + +static const char * const i80321_steppings[16] = { + "step A-0", "step B-0", "rev 2", "rev 3", + "rev 4", "rev 5", "rev 6", "rev 7", + "rev 8", "rev 9", "rev 10", "rev 11", + "rev 12", "rev 13", "rev 14", "rev 15", +}; + +static const char * const i81342_steppings[16] = { + "step A-0", "rev 1", "rev 2", "rev 3", + "rev 4", "rev 5", "rev 6", "rev 7", + "rev 8", "rev 9", "rev 10", "rev 11", + "rev 12", "rev 13", "rev 14", "rev 15", +}; + +/* Steppings for PXA2[15]0 */ +static const char * const pxa2x0_steppings[16] = { + "step A-0", "step A-1", "step B-0", "step B-1", + "step B-2", "step C-0", "rev 6", "rev 7", + "rev 8", "rev 9", "rev 10", "rev 11", + "rev 12", "rev 13", "rev 14", "rev 15", +}; + +/* Steppings for PXA255/26x. + * rev 5: PXA26x B0, rev 6: PXA255 A0 + */ +static const char * const pxa255_steppings[16] = { + "rev 0", "rev 1", "rev 2", "step A-0", + "rev 4", "step B-0", "step A-0", "rev 7", + "rev 8", "rev 9", "rev 10", "rev 11", + "rev 12", "rev 13", "rev 14", "rev 15", +}; + +/* Stepping for PXA27x */ +static const char * const pxa27x_steppings[16] = { + "step A-0", "step A-1", "step B-0", "step B-1", + "step C-0", "rev 5", "rev 6", "rev 7", + "rev 8", "rev 9", "rev 10", "rev 11", + "rev 12", "rev 13", "rev 14", "rev 15", +}; + +static const char * const ixp425_steppings[16] = { + "step 0 (A0)", "rev 1 (ARMv5TE)", "rev 2", "rev 3", + "rev 4", "rev 5", "rev 6", "rev 7", + "rev 8", "rev 9", "rev 10", "rev 11", + "rev 12", "rev 13", "rev 14", "rev 15", +}; + +struct cpuidtab { + u_int32_t cpuid; + enum cpu_class cpu_class; + const char *cpu_name; + const char * const *cpu_steppings; +}; + +const struct cpuidtab cpuids[] = { + { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", + generic_steppings }, + { CPU_ID_ARM920T_ALT, CPU_CLASS_ARM9TDMI, "ARM920T", + generic_steppings }, + { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", + generic_steppings }, + { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S", + generic_steppings }, + { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", + generic_steppings }, + { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", + generic_steppings }, + { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", + generic_steppings }, + { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", + generic_steppings }, + { CPU_ID_FA526, CPU_CLASS_ARM9TDMI, "FA526", + generic_steppings }, + { CPU_ID_FA626TE, CPU_CLASS_ARM9ES, "FA626TE", + generic_steppings }, + + { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T", + generic_steppings }, + + { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E", + generic_steppings }, + { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S", + generic_steppings }, + { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S", + generic_steppings }, + + { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", + xscale_steppings }, + + { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", + i80321_steppings }, + { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", + i80321_steppings }, + { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", + i80321_steppings }, + { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", + i80321_steppings }, + + { CPU_ID_81342, CPU_CLASS_XSCALE, "i81342", + i81342_steppings }, + + { CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz", + i80219_steppings }, + { CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz", + i80219_steppings }, + + { CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x", + pxa27x_steppings }, + { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", + pxa2x0_steppings }, + { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", + pxa2x0_steppings }, + { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250", + pxa2x0_steppings }, + { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210", + pxa2x0_steppings }, + { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA255", + pxa255_steppings }, + { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", + pxa2x0_steppings }, + + { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz", + ixp425_steppings }, + { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz", + ixp425_steppings }, + { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", + ixp425_steppings }, + + /* XXX ixp435 steppings? */ + { CPU_ID_IXP435, CPU_CLASS_XSCALE, "IXP435", + ixp425_steppings }, + + { CPU_ID_MV88FR131, CPU_CLASS_MARVELL, "Feroceon 88FR131", + generic_steppings }, + + { CPU_ID_MV88FR571_VD, CPU_CLASS_MARVELL, "Feroceon 88FR571-VD", + generic_steppings }, + + { 0, CPU_CLASS_NONE, NULL, NULL } +}; + +struct cpu_classtab { + const char *class_name; + const char *class_option; +}; + +const struct cpu_classtab cpu_classes[] = { + { "unknown", NULL }, /* CPU_CLASS_NONE */ + { "ARM9TDMI", "CPU_ARM9TDMI" }, /* CPU_CLASS_ARM9TDMI */ + { "ARM9E-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9ES */ + { "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */ + { "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */ + { "ARM10EJ", "CPU_ARM10" }, /* CPU_CLASS_ARM10EJ */ + { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ + { "Marvell", "CPU_MARVELL" }, /* CPU_CLASS_MARVELL */ +}; + +/* + * Report the type of the specified arm processor. This uses the generic and + * arm specific information in the cpu structure to identify the processor. + * The remaining fields in the cpu structure are filled in appropriately. + */ + +static const char * const wtnames[] = { + "write-through", + "write-back", + "write-back", + "**unknown 3**", + "**unknown 4**", + "write-back-locking", /* XXX XScale-specific? */ + "write-back-locking-A", + "write-back-locking-B", + "**unknown 8**", + "**unknown 9**", + "**unknown 10**", + "**unknown 11**", + "**unknown 12**", + "**unknown 13**", + "write-back-locking-C", + "**unknown 15**", +}; + +static void +print_enadis(int enadis, char *s) +{ + + printf(" %s %sabled", s, (enadis == 0) ? "dis" : "en"); +} + +enum cpu_class cpu_class = CPU_CLASS_NONE; + +u_int cpu_pfr(int num) +{ + u_int feat; + + switch (num) { + case 0: + __asm __volatile("mrc p15, 0, %0, c0, c1, 0" + : "=r" (feat)); + break; + case 1: + __asm __volatile("mrc p15, 0, %0, c0, c1, 1" + : "=r" (feat)); + break; + default: + panic("Processor Feature Register %d not implemented", num); + break; + } + + return (feat); +} + +void +identify_arm_cpu(void) +{ + u_int cpuid; + u_int8_t ctrl; + int i; + + ctrl = cpu_get_control(); + cpuid = cpu_ident(); + + if (cpuid == 0) { + printf("Processor failed probe - no CPU ID\n"); + return; + } + + for (i = 0; cpuids[i].cpuid != 0; i++) + if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { + cpu_class = cpuids[i].cpu_class; + printf("CPU: %s %s (%s core)\n", + cpuids[i].cpu_name, + cpuids[i].cpu_steppings[cpuid & + CPU_ID_REVISION_MASK], + cpu_classes[cpu_class].class_name); + break; + } + if (cpuids[i].cpuid == 0) + printf("unknown CPU (ID = 0x%x)\n", cpuid); + + printf(" "); + + if (ctrl & CPU_CONTROL_BEND_ENABLE) + printf(" Big-endian"); + else + printf(" Little-endian"); + + switch (cpu_class) { + case CPU_CLASS_ARM9TDMI: + case CPU_CLASS_ARM9ES: + case CPU_CLASS_ARM9EJS: + case CPU_CLASS_ARM10E: + case CPU_CLASS_ARM10EJ: + case CPU_CLASS_XSCALE: + case CPU_CLASS_MARVELL: + print_enadis(ctrl & CPU_CONTROL_DC_ENABLE, "DC"); + print_enadis(ctrl & CPU_CONTROL_IC_ENABLE, "IC"); +#ifdef CPU_XSCALE_81342 + print_enadis(ctrl & CPU_CONTROL_L2_ENABLE, "L2"); +#endif +#if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) + i = sheeva_control_ext(0, 0); + print_enadis(i & MV_WA_ENABLE, "WA"); + print_enadis(i & MV_DC_STREAM_ENABLE, "DC streaming"); + printf("\n "); + print_enadis((i & MV_BTB_DISABLE) == 0, "BTB"); + print_enadis(i & MV_L2_ENABLE, "L2"); + print_enadis((i & MV_L2_PREFETCH_DISABLE) == 0, + "L2 prefetch"); + printf("\n "); +#endif + break; + default: + break; + } + + print_enadis(ctrl & CPU_CONTROL_WBUF_ENABLE, "WB"); + if (ctrl & CPU_CONTROL_LABT_ENABLE) + printf(" LABT"); + else + printf(" EABT"); + + print_enadis(ctrl & CPU_CONTROL_BPRD_ENABLE, "branch prediction"); + printf("\n"); + + /* Print cache info. */ + if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) + return; + + if (arm_pcache_unified) { + printf(" %dKB/%dB %d-way %s unified cache\n", + arm_pdcache_size / 1024, + arm_pdcache_line_size, arm_pdcache_ways, + wtnames[arm_pcache_type]); + } else { + printf(" %dKB/%dB %d-way instruction cache\n", + arm_picache_size / 1024, + arm_picache_line_size, arm_picache_ways); + printf(" %dKB/%dB %d-way %s data cache\n", + arm_pdcache_size / 1024, + arm_pdcache_line_size, arm_pdcache_ways, + wtnames[arm_pcache_type]); + } +} Property changes on: stable/11/sys/arm/arm/identcpu-v4.c ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: stable/11/sys/arm/arm/identcpu-v6.c =================================================================== --- stable/11/sys/arm/arm/identcpu-v6.c (nonexistent) +++ stable/11/sys/arm/arm/identcpu-v6.c (revision 314525) @@ -0,0 +1,360 @@ +/* $NetBSD: cpu.c,v 1.55 2004/02/13 11:36:10 wiz Exp $ */ + +/*- + * Copyright (c) 1995 Mark Brinicombe. + * Copyright (c) 1995 Brini. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * RiscBSD kernel project + * + * cpu.c + * + * Probing and configuration for the master CPU + * + * Created : 10/10/95 + */ + +#include +__FBSDID("$FreeBSD$"); +#include +#include +#include +#include +#include +#include +#include + +char machine[] = "arm"; + +SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, + machine, 0, "Machine class"); + +static char hw_buf[81]; +static int hw_buf_idx; +static bool hw_buf_newline; + +static struct { + int implementer; + int part_number; + char *impl_name; + char *core_name; +} cpu_names[] = { + {CPU_IMPLEMENTER_ARM, CPU_ARCH_ARM1176, "ARM", "ARM1176"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A5 , "ARM", "Cortex-A5"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A7 , "ARM", "Cortex-A7"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A8 , "ARM", "Cortex-A8"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A9 , "ARM", "Cortex-A9"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A12, "ARM", "Cortex-A12"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A15, "ARM", "Cortex-A15"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A17, "ARM", "Cortex-A17"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A53, "ARM", "Cortex-A53"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A57, "ARM", "Cortex-A57"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A72, "ARM", "Cortex-A72"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A73, "ARM", "Cortex-A73"}, + + {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_581, "Marwell", "PJ4 v7"}, + {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_584, "Marwell", "PJ4MP v7"}, + + {CPU_IMPLEMENTER_QCOM, CPU_ARCH_KRAIT_300, "Qualcomm", "Krait 300"}, +}; + + +static void +print_v5_cache(void) +{ + uint32_t isize, dsize; + uint32_t multiplier; + int pcache_type; + int pcache_unified; + int picache_size; + int picache_line_size; + int picache_ways; + int pdcache_size; + int pdcache_line_size; + int pdcache_ways; + + pcache_unified = 0; + picache_size = 0 ; + picache_line_size = 0 ; + picache_ways = 0 ; + pdcache_size = 0; + pdcache_line_size = 0; + pdcache_ways = 0; + + if ((cpuinfo.ctr & CPU_CT_S) == 0) + pcache_unified = 1; + + /* + * If you want to know how this code works, go read the ARM ARM. + */ + pcache_type = CPU_CT_CTYPE(cpuinfo.ctr); + + if (pcache_unified == 0) { + isize = CPU_CT_ISIZE(cpuinfo.ctr); + multiplier = (isize & CPU_CT_xSIZE_M) ? 3 : 2; + picache_line_size = 1U << (CPU_CT_xSIZE_LEN(isize) + 3); + if (CPU_CT_xSIZE_ASSOC(isize) == 0) { + if (isize & CPU_CT_xSIZE_M) + picache_line_size = 0; /* not present */ + else + picache_ways = 1; + } else { + picache_ways = multiplier << + (CPU_CT_xSIZE_ASSOC(isize) - 1); + } + picache_size = multiplier << (CPU_CT_xSIZE_SIZE(isize) + 8); + } + + dsize = CPU_CT_DSIZE(cpuinfo.ctr); + multiplier = (dsize & CPU_CT_xSIZE_M) ? 3 : 2; + pdcache_line_size = 1U << (CPU_CT_xSIZE_LEN(dsize) + 3); + if (CPU_CT_xSIZE_ASSOC(dsize) == 0) { + if (dsize & CPU_CT_xSIZE_M) + pdcache_line_size = 0; /* not present */ + else + pdcache_ways = 1; + } else { + pdcache_ways = multiplier << + (CPU_CT_xSIZE_ASSOC(dsize) - 1); + } + pdcache_size = multiplier << (CPU_CT_xSIZE_SIZE(dsize) + 8); + + + /* Print cache info. */ + if (picache_line_size == 0 && pdcache_line_size == 0) + return; + + if (pcache_unified) { + printf(" %dKB/%dB %d-way %s unified cache\n", + pdcache_size / 1024, + pdcache_line_size, pdcache_ways, + pcache_type == 0 ? "WT" : "WB"); + } else { + printf(" %dKB/%dB %d-way instruction cache\n", + picache_size / 1024, + picache_line_size, picache_ways); + printf(" %dKB/%dB %d-way %s data cache\n", + pdcache_size / 1024, + pdcache_line_size, pdcache_ways, + pcache_type == 0 ? "WT" : "WB"); + } +} + +static void +print_v7_cache(void ) +{ + uint32_t type, val, size, sets, ways, linesize; + int i; + + printf("LoUU:%d LoC:%d LoUIS:%d \n", + CPU_CLIDR_LOUU(cpuinfo.clidr) + 1, + CPU_CLIDR_LOC(cpuinfo.clidr) + 1, + CPU_CLIDR_LOUIS(cpuinfo.clidr) + 1); + + for (i = 0; i < 7; i++) { + type = CPU_CLIDR_CTYPE(cpuinfo.clidr, i); + if (type == 0) + break; + printf("Cache level %d:\n", i + 1); + if (type == CACHE_DCACHE || type == CACHE_UNI_CACHE || + type == CACHE_SEP_CACHE) { + cp15_csselr_set(i << 1); + val = cp15_ccsidr_get(); + ways = CPUV7_CT_xSIZE_ASSOC(val) + 1; + sets = CPUV7_CT_xSIZE_SET(val) + 1; + linesize = 1 << (CPUV7_CT_xSIZE_LEN(val) + 4); + size = (ways * sets * linesize) / 1024; + + if (type == CACHE_UNI_CACHE) + printf(" %dKB/%dB %d-way unified cache", + size, linesize,ways); + else + printf(" %dKB/%dB %d-way data cache", + size, linesize, ways); + if (val & CPUV7_CT_CTYPE_WT) + printf(" WT"); + if (val & CPUV7_CT_CTYPE_WB) + printf(" WB"); + if (val & CPUV7_CT_CTYPE_RA) + printf(" Read-Alloc"); + if (val & CPUV7_CT_CTYPE_WA) + printf(" Write-Alloc"); + printf("\n"); + } + + if (type == CACHE_ICACHE || type == CACHE_SEP_CACHE) { + cp15_csselr_set(i << 1 | 1); + val = cp15_ccsidr_get(); + ways = CPUV7_CT_xSIZE_ASSOC(val) + 1; + sets = CPUV7_CT_xSIZE_SET(val) + 1; + linesize = 1 << (CPUV7_CT_xSIZE_LEN(val) + 4); + size = (ways * sets * linesize) / 1024; + printf(" %dKB/%dB %d-way instruction cache", + size, linesize, ways); + if (val & CPUV7_CT_CTYPE_WT) + printf(" WT"); + if (val & CPUV7_CT_CTYPE_WB) + printf(" WB"); + if (val & CPUV7_CT_CTYPE_RA) + printf(" Read-Alloc"); + if (val & CPUV7_CT_CTYPE_WA) + printf(" Write-Alloc"); + printf("\n"); + } + } + cp15_csselr_set(0); +} + +static void +add_cap(char *cap) +{ + int len; + + len = strlen(cap); + + if ((hw_buf_idx + len + 2) >= 79) { + printf("%s,\n", hw_buf); + hw_buf_idx = 0; + hw_buf_newline = true; + } + if (hw_buf_newline) + hw_buf_idx += sprintf(hw_buf + hw_buf_idx, " "); + else + hw_buf_idx += sprintf(hw_buf + hw_buf_idx, ", "); + hw_buf_newline = false; + + + hw_buf_idx += sprintf(hw_buf + hw_buf_idx, "%s", cap); +} + +void +identify_arm_cpu(void) +{ + int i; + u_int val; + + /* + * CPU + */ + for(i = 0; i < nitems(cpu_names); i++) { + if (cpu_names[i].implementer == cpuinfo.implementer && + cpu_names[i].part_number == cpuinfo.part_number) { + printf("CPU: %s %s r%dp%d (ECO: 0x%08X)\n", + cpu_names[i].impl_name, cpu_names[i].core_name, + cpuinfo.revision, cpuinfo.patch, + cpuinfo.midr != cpuinfo.revidr ? + cpuinfo.revidr : 0); + break; + } + + } + if (i >= nitems(cpu_names)) + printf("unknown CPU (ID = 0x%x)\n", cpuinfo.midr); + + printf("CPU Features: \n"); + hw_buf_idx = 0; + hw_buf_newline = true; + + val = (cpuinfo.mpidr >> 4)& 0xF; + if (cpuinfo.mpidr & (1 << 31U)) + add_cap("Multiprocessing"); + val = (cpuinfo.id_pfr0 >> 4)& 0xF; + if (val == 1) + add_cap("Thumb"); + else if (val == 3) + add_cap("Thumb2"); + + val = (cpuinfo.id_pfr1 >> 4)& 0xF; + if (val == 1 || val == 2) + add_cap("Security"); + + val = (cpuinfo.id_pfr1 >> 12)& 0xF; + if (val == 1) + add_cap("Virtualization"); + + val = (cpuinfo.id_pfr1 >> 16)& 0xF; + if (val == 1) + add_cap("Generic Timer"); + + val = (cpuinfo.id_mmfr0 >> 0)& 0xF; + if (val == 2) { + add_cap("VMSAv6"); + } else if (val >= 3) { + add_cap("VMSAv7"); + if (val >= 4) + add_cap("PXN"); + if (val >= 5) + add_cap("LPAE"); + } + + val = (cpuinfo.id_mmfr3 >> 20)& 0xF; + if (val == 1) + add_cap("Coherent Walk"); + + if (hw_buf_idx != 0) + printf("%s\n", hw_buf); + + printf("Optional instructions: \n"); + hw_buf_idx = 0; + hw_buf_newline = true; + val = (cpuinfo.id_isar0 >> 24)& 0xF; + if (val == 1) + add_cap("SDIV/UDIV (Thumb)"); + else if (val == 2) + add_cap("SDIV/UDIV"); + + val = (cpuinfo.id_isar2 >> 20)& 0xF; + if (val == 1 || val == 2) + add_cap("UMULL"); + + val = (cpuinfo.id_isar2 >> 16)& 0xF; + if (val == 1 || val == 2 || val == 3) + add_cap("SMULL"); + + val = (cpuinfo.id_isar2 >> 12)& 0xF; + if (val == 1) + add_cap("MLA"); + + val = (cpuinfo.id_isar3 >> 4)& 0xF; + if (val == 1) + add_cap("SIMD"); + else if (val == 3) + add_cap("SIMD(ext)"); + if (hw_buf_idx != 0) + printf("%s\n", hw_buf); + + /* + * Cache + */ + if (CPU_CT_FORMAT(cpuinfo.ctr) == CPU_CT_ARMV7) + print_v7_cache(); + else + print_v5_cache(); +} Property changes on: stable/11/sys/arm/arm/identcpu-v6.c ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: stable/11/sys/arm/include/cpuinfo.h =================================================================== --- stable/11/sys/arm/include/cpuinfo.h (revision 314524) +++ stable/11/sys/arm/include/cpuinfo.h (revision 314525) @@ -1,122 +1,125 @@ /*- * Copyright 2014 Svatopluk Kraus * Copyright 2014 Michal Meloun * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _MACHINE_CPUINFO_H_ #define _MACHINE_CPUINFO_H_ #include #define CPU_IMPLEMENTER_ARM 0x41 #define CPU_IMPLEMENTER_QCOM 0x51 #define CPU_IMPLEMENTER_MRVL 0x56 /* ARM */ #define CPU_ARCH_ARM1176 0xB76 #define CPU_ARCH_CORTEX_A5 0xC05 #define CPU_ARCH_CORTEX_A7 0xC07 #define CPU_ARCH_CORTEX_A8 0xC08 #define CPU_ARCH_CORTEX_A9 0xC09 #define CPU_ARCH_CORTEX_A12 0xC0D #define CPU_ARCH_CORTEX_A15 0xC0F #define CPU_ARCH_CORTEX_A17 0xC11 #define CPU_ARCH_CORTEX_A53 0xD03 #define CPU_ARCH_CORTEX_A57 0xD07 #define CPU_ARCH_CORTEX_A72 0xD08 +#define CPU_ARCH_CORTEX_A73 0xD09 /* QCOM */ #define CPU_ARCH_KRAIT_300 0x06F /* MRVL */ -#define CPU_ARCH_SHEEVA_851 0x581 /* PJ4/PJ4B */ +#define CPU_ARCH_SHEEVA_581 0x581 /* PJ4/PJ4B */ #define CPU_ARCH_SHEEVA_584 0x584 /* PJ4B-MP/PJ4C */ struct cpuinfo { /* raw id registers */ uint32_t midr; uint32_t ctr; uint32_t tcmtr; uint32_t tlbtr; uint32_t mpidr; uint32_t revidr; uint32_t id_pfr0; uint32_t id_pfr1; uint32_t id_dfr0; uint32_t id_afr0; uint32_t id_mmfr0; uint32_t id_mmfr1; uint32_t id_mmfr2; uint32_t id_mmfr3; uint32_t id_isar0; uint32_t id_isar1; uint32_t id_isar2; uint32_t id_isar3; uint32_t id_isar4; uint32_t id_isar5; uint32_t cbar; + uint32_t ccsidr; + uint32_t clidr; - /* Parsed bits of above registers... */ + /* Parsed bits of above registers... */ /* midr */ int implementer; int revision; int architecture; int part_number; int patch; /* id_mmfr0 */ int outermost_shareability; int shareability_levels; int auxiliary_registers; int innermost_shareability; /* id_mmfr1 */ int mem_barrier; /* id_mmfr3 */ int coherent_walk; int maintenance_broadcast; /* id_pfr1 */ int generic_timer_ext; int virtualization_ext; int security_ext; /* L1 cache info */ int dcache_line_size; int dcache_line_mask; int icache_line_size; int icache_line_mask; }; extern struct cpuinfo cpuinfo; void cpuinfo_init(void); void cpuinfo_get_actlr_modifier(uint32_t *actlr_mask, uint32_t *actlr_set); #endif /* _MACHINE_CPUINFO_H_ */ Index: stable/11/sys/conf/files.arm =================================================================== --- stable/11/sys/conf/files.arm (revision 314524) +++ stable/11/sys/conf/files.arm (revision 314525) @@ -1,157 +1,158 @@ # $FreeBSD$ cloudabi32_vdso.o optional compat_cloudabi32 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_armv6.S" \ compile-with "${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_armv6.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi32_vdso.o" # cloudabi32_vdso_blob.o optional compat_cloudabi32 \ dependency "cloudabi32_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf32-littlearm --binary-architecture arm cloudabi32_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi32_vdso_blob.o" # arm/arm/autoconf.c standard arm/arm/bcopy_page.S standard arm/arm/bcopyinout.S standard arm/arm/blockio.S standard arm/arm/bus_space_asm_generic.S standard arm/arm/bus_space_base.c optional fdt arm/arm/bus_space_generic.c standard arm/arm/busdma_machdep-v4.c optional !armv6 arm/arm/busdma_machdep-v6.c optional armv6 arm/arm/copystr.S standard arm/arm/cpufunc.c standard arm/arm/cpufunc_asm.S standard arm/arm/cpufunc_asm_arm9.S optional cpu_arm9 | cpu_arm9e arm/arm/cpufunc_asm_arm11.S optional cpu_arm1176 arm/arm/cpufunc_asm_arm11x6.S optional cpu_arm1176 arm/arm/cpufunc_asm_armv4.S optional cpu_arm9 | cpu_arm9e | cpu_fa526 | cpu_xscale_pxa2x0 | cpu_xscale_ixp425 | cpu_xscale_81342 arm/arm/cpufunc_asm_armv5_ec.S optional cpu_arm9e arm/arm/cpufunc_asm_armv6.S optional cpu_arm1176 arm/arm/cpufunc_asm_armv7.S optional cpu_cortexa | cpu_krait | cpu_mv_pj4b arm/arm/cpufunc_asm_fa526.S optional cpu_fa526 arm/arm/cpufunc_asm_pj4b.S optional cpu_mv_pj4b arm/arm/cpufunc_asm_sheeva.S optional cpu_arm9e arm/arm/cpufunc_asm_xscale.S optional cpu_xscale_pxa2x0 | cpu_xscale_ixp425 | cpu_xscale_81342 arm/arm/cpufunc_asm_xscale_c3.S optional cpu_xscale_81342 arm/arm/cpuinfo.c standard arm/arm/cpu_asm-v6.S optional armv6 arm/arm/db_disasm.c optional ddb arm/arm/db_interface.c optional ddb arm/arm/db_trace.c optional ddb arm/arm/debug_monitor.c optional ddb armv6 arm/arm/disassem.c optional ddb arm/arm/dump_machdep.c standard arm/arm/elf_machdep.c standard arm/arm/elf_note.S standard arm/arm/exception.S standard arm/arm/fiq.c standard arm/arm/fiq_subr.S standard arm/arm/fusu.S standard arm/arm/gdb_machdep.c optional gdb arm/arm/generic_timer.c optional generic_timer arm/arm/gic.c optional gic arm/arm/hdmi_if.m optional hdmi -arm/arm/identcpu.c standard +arm/arm/identcpu-v4.c optional !armv6 +arm/arm/identcpu-v6.c optional armv6 arm/arm/in_cksum.c optional inet | inet6 arm/arm/in_cksum_arm.S optional inet | inet6 arm/arm/intr.c optional !intrng kern/subr_intr.c optional intrng arm/arm/locore.S standard no-obj arm/arm/machdep.c standard arm/arm/machdep_intr.c standard arm/arm/mem.c optional mem arm/arm/minidump_machdep.c optional mem arm/arm/mp_machdep.c optional smp arm/arm/mpcore_timer.c optional mpcore_timer arm/arm/nexus.c standard arm/arm/ofw_machdep.c optional fdt arm/arm/physmem.c standard arm/arm/pl190.c optional pl190 arm/arm/pl310.c optional pl310 arm/arm/platform.c optional platform arm/arm/platform_if.m optional platform arm/arm/pmap-v4.c optional !armv6 arm/arm/pmap-v6.c optional armv6 arm/arm/pmu.c optional pmu | fdt hwpmc arm/arm/sc_machdep.c optional sc arm/arm/setcpsr.S standard arm/arm/setstack.s standard arm/arm/stack_machdep.c optional ddb | stack arm/arm/stdatomic.c standard \ compile-with "${NORMAL_C:N-Wmissing-prototypes}" arm/arm/support.S standard arm/arm/swtch.S standard arm/arm/swtch-v4.S optional !armv6 arm/arm/swtch-v6.S optional armv6 arm/arm/sys_machdep.c standard arm/arm/syscall.c standard arm/arm/trap-v4.c optional !armv6 arm/arm/trap-v6.c optional armv6 arm/arm/uio_machdep.c standard arm/arm/undefined.c standard arm/arm/unwind.c optional ddb | kdtrace_hooks arm/arm/vm_machdep.c standard arm/arm/vfp.c standard arm/cloudabi32/cloudabi32_sysvec.c optional compat_cloudabi32 board_id.h standard \ dependency "$S/arm/conf/genboardid.awk $S/arm/conf/mach-types" \ compile-with "${AWK} -f $S/arm/conf/genboardid.awk $S/arm/conf/mach-types > board_id.h" \ no-obj no-implicit-rule before-depend \ clean "board_id.h" cddl/compat/opensolaris/kern/opensolaris_atomic.c optional zfs | dtrace compile-with "${CDDL_C}" cddl/dev/dtrace/arm/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/arm/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/arm/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" crypto/blowfish/bf_enc.c optional crypto | ipsec crypto/des/des_enc.c optional crypto | ipsec | netsmb dev/dwc/if_dwc.c optional dwc dev/dwc/if_dwc_if.m optional dwc dev/fb/fb.c optional sc dev/fdt/fdt_arm_platform.c optional platform fdt dev/hwpmc/hwpmc_arm.c optional hwpmc dev/hwpmc/hwpmc_armv7.c optional hwpmc armv6 dev/iicbus/twsi/twsi.c optional twsi dev/ofw/ofw_cpu.c optional fdt dev/ofw/ofwpci.c optional fdt pci dev/pci/pci_host_generic.c optional pci_host_generic pci fdt dev/psci/psci.c optional psci dev/psci/psci_arm.S optional psci dev/syscons/scgfbrndr.c optional sc dev/syscons/scterm-teken.c optional sc dev/syscons/scvtb.c optional sc dev/uart/uart_cpu_fdt.c optional uart fdt font.h optional sc \ compile-with "uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x16.fnt && file2c 'u_char dflt_font_16[16*256] = {' '};' < ${SC_DFLT_FONT}-8x16 > font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x14.fnt && file2c 'u_char dflt_font_14[14*256] = {' '};' < ${SC_DFLT_FONT}-8x14 >> font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x8.fnt && file2c 'u_char dflt_font_8[8*256] = {' '};' < ${SC_DFLT_FONT}-8x8 >> font.h" \ no-obj no-implicit-rule before-depend \ clean "font.h ${SC_DFLT_FONT}-8x14 ${SC_DFLT_FONT}-8x16 ${SC_DFLT_FONT}-8x8" kern/msi_if.m optional intrng kern/pic_if.m optional intrng kern/subr_busdma_bufalloc.c standard kern/subr_devmap.c standard kern/subr_sfbuf.c standard libkern/arm/aeabi_unwind.c standard libkern/arm/divsi3.S standard libkern/arm/ffs.S standard libkern/arm/ldivmod.S standard libkern/arm/ldivmod_helper.c standard libkern/arm/memclr.S standard libkern/arm/memcpy.S standard libkern/arm/memset.S standard libkern/arm/muldi3.c standard libkern/ashldi3.c standard libkern/ashrdi3.c standard libkern/divdi3.c standard libkern/ffsl.c standard libkern/ffsll.c standard libkern/fls.c standard libkern/flsl.c standard libkern/flsll.c standard libkern/lshrdi3.c standard libkern/moddi3.c standard libkern/qdivrem.c standard libkern/ucmpdi2.c standard libkern/udivdi3.c standard libkern/umoddi3.c standard Index: stable/11 =================================================================== --- stable/11 (revision 314524) +++ stable/11 (revision 314525) Property changes on: stable/11 ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head:r306901