No OneTemporary
Actions

Size

53 KB

Referenced Files

None

Subscribers

None

View Options

	Index: projects/clang400-import/contrib/compiler-rt
	===================================================================
	--- projects/clang400-import/contrib/compiler-rt (revision 314417)
	+++ projects/clang400-import/contrib/compiler-rt (revision 314418)

	Property changes on: projects/clang400-import/contrib/compiler-rt
	___________________________________________________________________
	Modified: svn:mergeinfo
	## -0,0 +0,1 ##
	Merged /vendor/compiler-rt/dist:r314269-314417
	Index: projects/clang400-import/contrib/libc++
	===================================================================
	--- projects/clang400-import/contrib/libc++ (revision 314417)
	+++ projects/clang400-import/contrib/libc++ (revision 314418)

	Property changes on: projects/clang400-import/contrib/libc++
	___________________________________________________________________
	Modified: svn:mergeinfo
	## -0,0 +0,1 ##
	Merged /vendor/libc++/dist:r314269-314417
	Index: projects/clang400-import/contrib/llvm/lib/CodeGen/ExecutionDepsFix.cpp
	===================================================================
	--- projects/clang400-import/contrib/llvm/lib/CodeGen/ExecutionDepsFix.cpp (revision 314417)
	+++ projects/clang400-import/contrib/llvm/lib/CodeGen/ExecutionDepsFix.cpp (revision 314418)
	@@ -1,867 +1,861 @@
	//===- ExecutionDepsFix.cpp - Fix execution dependecy issues ----- C++ --===//
	//
	// The LLVM Compiler Infrastructure
	//
	// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.
	//
	//===----------------------------------------------------------------------===//
	//
	// This file contains the execution dependency fix pass.
	//
	// Some X86 SSE instructions like mov, and, or, xor are available in different
	// variants for different operand types. These variant instructions are
	// equivalent, but on Nehalem and newer cpus there is extra latency
	// transferring data between integer and floating point domains. ARM cores
	// have similar issues when they are configured with both VFP and NEON
	// pipelines.
	//
	// This pass changes the variant instructions to minimize domain crossings.
	//
	//===----------------------------------------------------------------------===//

	#include "llvm/CodeGen/Passes.h"
	#include "llvm/ADT/PostOrderIterator.h"
	#include "llvm/ADT/iterator_range.h"
	#include "llvm/CodeGen/LivePhysRegs.h"
	#include "llvm/CodeGen/MachineFunctionPass.h"
	#include "llvm/CodeGen/MachineRegisterInfo.h"
	#include "llvm/CodeGen/RegisterClassInfo.h"
	#include "llvm/Support/Allocator.h"
	#include "llvm/Support/Debug.h"
	#include "llvm/Support/raw_ostream.h"
	#include "llvm/Target/TargetInstrInfo.h"
	#include "llvm/Target/TargetSubtargetInfo.h"

	using namespace llvm;

	#define DEBUG_TYPE "execution-fix"

	/// A DomainValue is a bit like LiveIntervals' ValNo, but it also keeps track
	/// of execution domains.
	///
	/// An open DomainValue represents a set of instructions that can still switch
	/// execution domain. Multiple registers may refer to the same open
	/// DomainValue - they will eventually be collapsed to the same execution
	/// domain.
	///
	/// A collapsed DomainValue represents a single register that has been forced
	/// into one of more execution domains. There is a separate collapsed
	/// DomainValue for each register, but it may contain multiple execution
	/// domains. A register value is initially created in a single execution
	/// domain, but if we were forced to pay the penalty of a domain crossing, we
	/// keep track of the fact that the register is now available in multiple
	/// domains.
	namespace {
	struct DomainValue {
	// Basic reference counting.
	unsigned Refs;

	// Bitmask of available domains. For an open DomainValue, it is the still
	// possible domains for collapsing. For a collapsed DomainValue it is the
	// domains where the register is available for free.
	unsigned AvailableDomains;

	// Pointer to the next DomainValue in a chain. When two DomainValues are
	// merged, Victim.Next is set to point to Victor, so old DomainValue
	// references can be updated by following the chain.
	DomainValue *Next;

	// Twiddleable instructions using or defining these registers.
	SmallVector<MachineInstr*, 8> Instrs;

	// A collapsed DomainValue has no instructions to twiddle - it simply keeps
	// track of the domains where the registers are already available.
	bool isCollapsed() const { return Instrs.empty(); }

	// Is domain available?
	bool hasDomain(unsigned domain) const {
	assert(domain <
	static_cast<unsigned>(std::numeric_limits<unsigned>::digits) &&
	"undefined behavior");
	return AvailableDomains & (1u << domain);
	}

	// Mark domain as available.
	void addDomain(unsigned domain) {
	AvailableDomains \|= 1u << domain;
	}

	// Restrict to a single domain available.
	void setSingleDomain(unsigned domain) {
	AvailableDomains = 1u << domain;
	}

	// Return bitmask of domains that are available and in mask.
	unsigned getCommonDomains(unsigned mask) const {
	return AvailableDomains & mask;
	}

	// First domain available.
	unsigned getFirstDomain() const {
	return countTrailingZeros(AvailableDomains);
	}

	DomainValue() : Refs(0) { clear(); }

	// Clear this DomainValue and point to next which has all its data.
	void clear() {
	AvailableDomains = 0;
	Next = nullptr;
	Instrs.clear();
	}
	};
	}

	namespace {
	/// Information about a live register.
	struct LiveReg {
	/// Value currently in this register, or NULL when no value is being tracked.
	/// This counts as a DomainValue reference.
	DomainValue *Value;

	/// Instruction that defined this register, relative to the beginning of the
	/// current basic block. When a LiveReg is used to represent a live-out
	/// register, this value is relative to the end of the basic block, so it
	/// will be a negative number.
	int Def;
	};
	} // anonymous namespace

	namespace {
	class ExeDepsFix : public MachineFunctionPass {
	static char ID;
	SpecificBumpPtrAllocator<DomainValue> Allocator;
	SmallVector<DomainValue*,16> Avail;

	const TargetRegisterClass *const RC;
	MachineFunction *MF;
	const TargetInstrInfo *TII;
	const TargetRegisterInfo *TRI;
	RegisterClassInfo RegClassInfo;
	std::vector<SmallVector<int, 1>> AliasMap;
	const unsigned NumRegs;
	LiveReg *LiveRegs;
	typedef DenseMap<MachineBasicBlock, LiveReg> LiveOutMap;
	LiveOutMap LiveOuts;

	/// List of undefined register reads in this block in forward order.
	std::vector<std::pair<MachineInstr*, unsigned> > UndefReads;

	/// Storage for register unit liveness.
	LivePhysRegs LiveRegSet;

	/// Current instruction number.
	/// The first instruction in each basic block is 0.
	int CurInstr;

	/// True when the current block has a predecessor that hasn't been visited
	/// yet.
	bool SeenUnknownBackEdge;

	public:
	ExeDepsFix(const TargetRegisterClass *rc)
	: MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {}

	void getAnalysisUsage(AnalysisUsage &AU) const override {
	AU.setPreservesAll();
	MachineFunctionPass::getAnalysisUsage(AU);
	}

	bool runOnMachineFunction(MachineFunction &MF) override;

	MachineFunctionProperties getRequiredProperties() const override {
	return MachineFunctionProperties().set(
	MachineFunctionProperties::Property::NoVRegs);
	}

	StringRef getPassName() const override { return "Execution dependency fix"; }

	private:
	iterator_range<SmallVectorImpl<int>::const_iterator>
	regIndices(unsigned Reg) const;

	// DomainValue allocation.
	DomainValue *alloc(int domain = -1);
	DomainValue retain(DomainValue DV) {
	if (DV) ++DV->Refs;
	return DV;
	}
	void release(DomainValue*);
	DomainValue resolve(DomainValue&);

	// LiveRegs manipulations.
	void setLiveReg(int rx, DomainValue *DV);
	void kill(int rx);
	void force(int rx, unsigned domain);
	void collapse(DomainValue *dv, unsigned domain);
	bool merge(DomainValue A, DomainValue B);

	void enterBasicBlock(MachineBasicBlock*);
	void leaveBasicBlock(MachineBasicBlock*);
	void visitInstr(MachineInstr*);
	void processDefs(MachineInstr*, bool Kill);
	void visitSoftInstr(MachineInstr*, unsigned mask);
	void visitHardInstr(MachineInstr*, unsigned domain);
	void pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
	unsigned Pref);
	bool shouldBreakDependence(MachineInstr*, unsigned OpIdx, unsigned Pref);
	void processUndefReads(MachineBasicBlock*);
	};
	}

	char ExeDepsFix::ID = 0;

	/// Translate TRI register number to a list of indices into our smaller tables
	/// of interesting registers.
	iterator_range<SmallVectorImpl<int>::const_iterator>
	ExeDepsFix::regIndices(unsigned Reg) const {
	assert(Reg < AliasMap.size() && "Invalid register");
	const auto &Entry = AliasMap[Reg];
	return make_range(Entry.begin(), Entry.end());
	}

	DomainValue *ExeDepsFix::alloc(int domain) {
	DomainValue *dv = Avail.empty() ?
	new(Allocator.Allocate()) DomainValue :
	Avail.pop_back_val();
	if (domain >= 0)
	dv->addDomain(domain);
	assert(dv->Refs == 0 && "Reference count wasn't cleared");
	assert(!dv->Next && "Chained DomainValue shouldn't have been recycled");
	return dv;
	}

	/// Release a reference to DV. When the last reference is released,
	/// collapse if needed.
	void ExeDepsFix::release(DomainValue *DV) {
	while (DV) {
	assert(DV->Refs && "Bad DomainValue");
	if (--DV->Refs)
	return;

	// There are no more DV references. Collapse any contained instructions.
	if (DV->AvailableDomains && !DV->isCollapsed())
	collapse(DV, DV->getFirstDomain());

	DomainValue *Next = DV->Next;
	DV->clear();
	Avail.push_back(DV);
	// Also release the next DomainValue in the chain.
	DV = Next;
	}
	}

	/// Follow the chain of dead DomainValues until a live DomainValue is reached.
	/// Update the referenced pointer when necessary.
	DomainValue ExeDepsFix::resolve(DomainValue &DVRef) {
	DomainValue *DV = DVRef;
	if (!DV \|\| !DV->Next)
	return DV;

	// DV has a chain. Find the end.
	do DV = DV->Next;
	while (DV->Next);

	// Update DVRef to point to DV.
	retain(DV);
	release(DVRef);
	DVRef = DV;
	return DV;
	}

	/// Set LiveRegs[rx] = dv, updating reference counts.
	void ExeDepsFix::setLiveReg(int rx, DomainValue *dv) {
	assert(unsigned(rx) < NumRegs && "Invalid index");
	assert(LiveRegs && "Must enter basic block first.");

	if (LiveRegs[rx].Value == dv)
	return;
	if (LiveRegs[rx].Value)
	release(LiveRegs[rx].Value);
	LiveRegs[rx].Value = retain(dv);
	}

	// Kill register rx, recycle or collapse any DomainValue.
	void ExeDepsFix::kill(int rx) {
	assert(unsigned(rx) < NumRegs && "Invalid index");
	assert(LiveRegs && "Must enter basic block first.");
	if (!LiveRegs[rx].Value)
	return;

	release(LiveRegs[rx].Value);
	LiveRegs[rx].Value = nullptr;
	}

	/// Force register rx into domain.
	void ExeDepsFix::force(int rx, unsigned domain) {
	assert(unsigned(rx) < NumRegs && "Invalid index");
	assert(LiveRegs && "Must enter basic block first.");
	if (DomainValue *dv = LiveRegs[rx].Value) {
	if (dv->isCollapsed())
	dv->addDomain(domain);
	else if (dv->hasDomain(domain))
	collapse(dv, domain);
	else {
	// This is an incompatible open DomainValue. Collapse it to whatever and
	// force the new value into domain. This costs a domain crossing.
	collapse(dv, dv->getFirstDomain());
	assert(LiveRegs[rx].Value && "Not live after collapse?");
	LiveRegs[rx].Value->addDomain(domain);
	}
	} else {
	// Set up basic collapsed DomainValue.
	setLiveReg(rx, alloc(domain));
	}
	}

	/// Collapse open DomainValue into given domain. If there are multiple
	/// registers using dv, they each get a unique collapsed DomainValue.
	void ExeDepsFix::collapse(DomainValue *dv, unsigned domain) {
	assert(dv->hasDomain(domain) && "Cannot collapse");

	// Collapse all the instructions.
	while (!dv->Instrs.empty())
	TII->setExecutionDomain(*dv->Instrs.pop_back_val(), domain);
	dv->setSingleDomain(domain);

	// If there are multiple users, give them new, unique DomainValues.
	if (LiveRegs && dv->Refs > 1)
	for (unsigned rx = 0; rx != NumRegs; ++rx)
	if (LiveRegs[rx].Value == dv)
	setLiveReg(rx, alloc(domain));
	}

	/// All instructions and registers in B are moved to A, and B is released.
	bool ExeDepsFix::merge(DomainValue A, DomainValue B) {
	assert(!A->isCollapsed() && "Cannot merge into collapsed");
	assert(!B->isCollapsed() && "Cannot merge from collapsed");
	if (A == B)
	return true;
	// Restrict to the domains that A and B have in common.
	unsigned common = A->getCommonDomains(B->AvailableDomains);
	if (!common)
	return false;
	A->AvailableDomains = common;
	A->Instrs.append(B->Instrs.begin(), B->Instrs.end());

	// Clear the old DomainValue so we won't try to swizzle instructions twice.
	B->clear();
	// All uses of B are referred to A.
	B->Next = retain(A);

	for (unsigned rx = 0; rx != NumRegs; ++rx) {
	assert(LiveRegs && "no space allocated for live registers");
	if (LiveRegs[rx].Value == B)
	setLiveReg(rx, A);
	}
	return true;
	}

	/// Set up LiveRegs by merging predecessor live-out values.
	void ExeDepsFix::enterBasicBlock(MachineBasicBlock *MBB) {
	// Detect back-edges from predecessors we haven't processed yet.
	SeenUnknownBackEdge = false;

	// Reset instruction counter in each basic block.
	CurInstr = 0;

	// Set up UndefReads to track undefined register reads.
	UndefReads.clear();
	LiveRegSet.clear();

	// Set up LiveRegs to represent registers entering MBB.
	if (!LiveRegs)
	LiveRegs = new LiveReg[NumRegs];

	// Default values are 'nothing happened a long time ago'.
	for (unsigned rx = 0; rx != NumRegs; ++rx) {
	LiveRegs[rx].Value = nullptr;
	LiveRegs[rx].Def = -(1 << 20);
	}

	// This is the entry block.
	if (MBB->pred_empty()) {
	for (const auto &LI : MBB->liveins()) {
	for (int rx : regIndices(LI.PhysReg)) {
	// Treat function live-ins as if they were defined just before the first
	// instruction. Usually, function arguments are set up immediately
	// before the call.
	LiveRegs[rx].Def = -1;
	}
	}
	DEBUG(dbgs() << "BB#" << MBB->getNumber() << ": entry\n");
	return;
	}

	// Try to coalesce live-out registers from predecessors.
	for (MachineBasicBlock::const_pred_iterator pi = MBB->pred_begin(),
	pe = MBB->pred_end(); pi != pe; ++pi) {
	LiveOutMap::const_iterator fi = LiveOuts.find(*pi);
	if (fi == LiveOuts.end()) {
	SeenUnknownBackEdge = true;
	continue;
	}
	assert(fi->second && "Can't have NULL entries");

	for (unsigned rx = 0; rx != NumRegs; ++rx) {
	// Use the most recent predecessor def for each register.
	LiveRegs[rx].Def = std::max(LiveRegs[rx].Def, fi->second[rx].Def);

	DomainValue *pdv = resolve(fi->second[rx].Value);
	if (!pdv)
	continue;
	if (!LiveRegs[rx].Value) {
	setLiveReg(rx, pdv);
	continue;
	}

	// We have a live DomainValue from more than one predecessor.
	if (LiveRegs[rx].Value->isCollapsed()) {
	// We are already collapsed, but predecessor is not. Force it.
	unsigned Domain = LiveRegs[rx].Value->getFirstDomain();
	if (!pdv->isCollapsed() && pdv->hasDomain(Domain))
	collapse(pdv, Domain);
	continue;
	}

	// Currently open, merge in predecessor.
	if (!pdv->isCollapsed())
	merge(LiveRegs[rx].Value, pdv);
	else
	force(rx, pdv->getFirstDomain());
	}
	}
	DEBUG(dbgs() << "BB#" << MBB->getNumber()
	<< (SeenUnknownBackEdge ? ": incomplete\n" : ": all preds known\n"));
	}

	void ExeDepsFix::leaveBasicBlock(MachineBasicBlock *MBB) {
	assert(LiveRegs && "Must enter basic block first.");
	// Save live registers at end of MBB - used by enterBasicBlock().
	// Also use LiveOuts as a visited set to detect back-edges.
	bool First = LiveOuts.insert(std::make_pair(MBB, LiveRegs)).second;

	if (First) {
	// LiveRegs was inserted in LiveOuts. Adjust all defs to be relative to
	// the end of this block instead of the beginning.
	for (unsigned i = 0, e = NumRegs; i != e; ++i)
	LiveRegs[i].Def -= CurInstr;
	} else {
	// Insertion failed, this must be the second pass.
	// Release all the DomainValues instead of keeping them.
	for (unsigned i = 0, e = NumRegs; i != e; ++i)
	release(LiveRegs[i].Value);
	delete[] LiveRegs;
	}
	LiveRegs = nullptr;
	}

	void ExeDepsFix::visitInstr(MachineInstr *MI) {
	if (MI->isDebugValue())
	return;

	// Update instructions with explicit execution domains.
	std::pair<uint16_t, uint16_t> DomP = TII->getExecutionDomain(*MI);
	if (DomP.first) {
	if (DomP.second)
	visitSoftInstr(MI, DomP.second);
	else
	visitHardInstr(MI, DomP.first);
	}

	// Process defs to track register ages, and kill values clobbered by generic
	// instructions.
	processDefs(MI, !DomP.first);
	}

	/// \brief Helps avoid false dependencies on undef registers by updating the
	/// machine instructions' undef operand to use a register that the instruction
	/// is truly dependent on, or use a register with clearance higher than Pref.
	void ExeDepsFix::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
	unsigned Pref) {
	MachineOperand &MO = MI->getOperand(OpIdx);
	assert(MO.isUndef() && "Expected undef machine operand");

	unsigned OriginalReg = MO.getReg();

	// Update only undef operands that are mapped to one register.
	if (AliasMap[OriginalReg].size() != 1)
	return;

	// Get the undef operand's register class
	const TargetRegisterClass *OpRC =
	TII->getRegClass(MI->getDesc(), OpIdx, TRI, *MF);

	// If the instruction has a true dependency, we can hide the false depdency
	// behind it.
	for (MachineOperand &CurrMO : MI->operands()) {
	if (!CurrMO.isReg() \|\| CurrMO.isDef() \|\| CurrMO.isUndef() \|\|
	!OpRC->contains(CurrMO.getReg()))
	continue;
	// We found a true dependency - replace the undef register with the true
	// dependency.
	MO.setReg(CurrMO.getReg());
	return;
	}

	// Go over all registers in the register class and find the register with
	// max clearance or clearance higher than Pref.
	unsigned MaxClearance = 0;
	unsigned MaxClearanceReg = OriginalReg;
	ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC);
	for (auto Reg : Order) {
	assert(AliasMap[Reg].size() == 1 &&
	"Reg is expected to be mapped to a single index");
	int RCrx = *regIndices(Reg).begin();
	unsigned Clearance = CurInstr - LiveRegs[RCrx].Def;
	if (Clearance <= MaxClearance)
	continue;
	MaxClearance = Clearance;
	MaxClearanceReg = Reg;

	if (MaxClearance > Pref)
	break;
	}

	// Update the operand if we found a register with better clearance.
	if (MaxClearanceReg != OriginalReg)
	MO.setReg(MaxClearanceReg);
	}

	/// \brief Return true to if it makes sense to break dependence on a partial def
	/// or undef use.
	bool ExeDepsFix::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx,
	unsigned Pref) {
	unsigned reg = MI->getOperand(OpIdx).getReg();
	for (int rx : regIndices(reg)) {
	unsigned Clearance = CurInstr - LiveRegs[rx].Def;
	DEBUG(dbgs() << "Clearance: " << Clearance << ", want " << Pref);

	if (Pref > Clearance) {
	DEBUG(dbgs() << ": Break dependency.\n");
	continue;
	}
	// The current clearance seems OK, but we may be ignoring a def from a
	// back-edge.
	if (!SeenUnknownBackEdge \|\| Pref <= unsigned(CurInstr)) {
	DEBUG(dbgs() << ": OK .\n");
	return false;
	}
	// A def from an unprocessed back-edge may make us break this dependency.
	DEBUG(dbgs() << ": Wait for back-edge to resolve.\n");
	return false;
	}
	return true;
	}

	// Update def-ages for registers defined by MI.
	// If Kill is set, also kill off DomainValues clobbered by the defs.
	//
	// Also break dependencies on partial defs and undef uses.
	void ExeDepsFix::processDefs(MachineInstr *MI, bool Kill) {
	assert(!MI->isDebugValue() && "Won't process debug values");

	// Break dependence on undef uses. Do this before updating LiveRegs below.
	unsigned OpNum;
	unsigned Pref = TII->getUndefRegClearance(*MI, OpNum, TRI);
	if (Pref) {
	pickBestRegisterForUndef(MI, OpNum, Pref);
	if (shouldBreakDependence(MI, OpNum, Pref))
	UndefReads.push_back(std::make_pair(MI, OpNum));
	}
	const MCInstrDesc &MCID = MI->getDesc();
	for (unsigned i = 0,
	e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
	i != e; ++i) {
	MachineOperand &MO = MI->getOperand(i);
	if (!MO.isReg())
	continue;
	if (MO.isUse())
	continue;
	for (int rx : regIndices(MO.getReg())) {
	// This instruction explicitly defines rx.
	DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr
	<< '\t' << *MI);

	// Check clearance before partial register updates.
	// Call breakDependence before setting LiveRegs[rx].Def.
	unsigned Pref = TII->getPartialRegUpdateClearance(*MI, i, TRI);
	if (Pref && shouldBreakDependence(MI, i, Pref))
	TII->breakPartialRegDependency(*MI, i, TRI);

	// How many instructions since rx was last written?
	LiveRegs[rx].Def = CurInstr;

	// Kill off domains redefined by generic instructions.
	if (Kill)
	kill(rx);
	}
	}
	++CurInstr;
	}

	/// \break Break false dependencies on undefined register reads.
	///
	/// Walk the block backward computing precise liveness. This is expensive, so we
	/// only do it on demand. Note that the occurrence of undefined register reads
	/// that should be broken is very rare, but when they occur we may have many in
	/// a single block.
	void ExeDepsFix::processUndefReads(MachineBasicBlock *MBB) {
	if (UndefReads.empty())
	return;

	// Collect this block's live out register units.
	LiveRegSet.init(*TRI);
	// We do not need to care about pristine registers as they are just preserved
	// but not actually used in the function.
	LiveRegSet.addLiveOutsNoPristines(*MBB);

	MachineInstr *UndefMI = UndefReads.back().first;
	unsigned OpIdx = UndefReads.back().second;

	for (MachineInstr &I : make_range(MBB->rbegin(), MBB->rend())) {
	// Update liveness, including the current instruction's defs.
	LiveRegSet.stepBackward(I);

	if (UndefMI == &I) {
	if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg()))
	TII->breakPartialRegDependency(*UndefMI, OpIdx, TRI);

	UndefReads.pop_back();
	if (UndefReads.empty())
	return;

	UndefMI = UndefReads.back().first;
	OpIdx = UndefReads.back().second;
	}
	}
	}

	// A hard instruction only works in one domain. All input registers will be
	// forced into that domain.
	void ExeDepsFix::visitHardInstr(MachineInstr *mi, unsigned domain) {
	// Collapse all uses.
	for (unsigned i = mi->getDesc().getNumDefs(),
	e = mi->getDesc().getNumOperands(); i != e; ++i) {
	MachineOperand &mo = mi->getOperand(i);
	if (!mo.isReg()) continue;
	for (int rx : regIndices(mo.getReg())) {
	force(rx, domain);
	}
	}

	// Kill all defs and force them.
	for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) {
	MachineOperand &mo = mi->getOperand(i);
	if (!mo.isReg()) continue;
	for (int rx : regIndices(mo.getReg())) {
	kill(rx);
	force(rx, domain);
	}
	}
	}

	// A soft instruction can be changed to work in other domains given by mask.
	void ExeDepsFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
	// Bitmask of available domains for this instruction after taking collapsed
	// operands into account.
	unsigned available = mask;

	// Scan the explicit use operands for incoming domains.
	SmallVector<int, 4> used;
	if (LiveRegs)
	for (unsigned i = mi->getDesc().getNumDefs(),
	e = mi->getDesc().getNumOperands(); i != e; ++i) {
	MachineOperand &mo = mi->getOperand(i);
	if (!mo.isReg()) continue;
	for (int rx : regIndices(mo.getReg())) {
	DomainValue *dv = LiveRegs[rx].Value;
	if (dv == nullptr)
	continue;
	// Bitmask of domains that dv and available have in common.
	unsigned common = dv->getCommonDomains(available);
	// Is it possible to use this collapsed register for free?
	if (dv->isCollapsed()) {
	// Restrict available domains to the ones in common with the operand.
	// If there are no common domains, we must pay the cross-domain
	// penalty for this operand.
	if (common) available = common;
	} else if (common)
	// Open DomainValue is compatible, save it for merging.
	used.push_back(rx);
	else
	// Open DomainValue is not compatible with instruction. It is useless
	// now.
	kill(rx);
	}
	}

	// If the collapsed operands force a single domain, propagate the collapse.
	if (isPowerOf2_32(available)) {
	unsigned domain = countTrailingZeros(available);
	TII->setExecutionDomain(*mi, domain);
	visitHardInstr(mi, domain);
	return;
	}

	// Kill off any remaining uses that don't match available, and build a list of
	// incoming DomainValues that we want to merge.
	- SmallVector<LiveReg, 4> Regs;
	- for (SmallVectorImpl<int>::iterator i=used.begin(), e=used.end(); i!=e; ++i) {
	- int rx = *i;
	+ SmallVector<const LiveReg *, 4> Regs;
	+ for (int rx : used) {
	assert(LiveRegs && "no space allocated for live registers");
	const LiveReg &LR = LiveRegs[rx];
	// This useless DomainValue could have been missed above.
	if (!LR.Value->getCommonDomains(available)) {
	kill(rx);
	continue;
	}
	// Sorted insertion.
	- bool Inserted = false;
	- for (SmallVectorImpl<LiveReg>::iterator i = Regs.begin(), e = Regs.end();
	- i != e && !Inserted; ++i) {
	- if (LR.Def < i->Def) {
	- Inserted = true;
	- Regs.insert(i, LR);
	- }
	- }
	- if (!Inserted)
	- Regs.push_back(LR);
	+ auto I = std::upper_bound(Regs.begin(), Regs.end(), &LR,
	+ [](const LiveReg LHS, const LiveReg RHS) {
	+ return LHS->Def < RHS->Def;
	+ });
	+ Regs.insert(I, &LR);
	}

	// doms are now sorted in order of appearance. Try to merge them all, giving
	// priority to the latest ones.
	DomainValue *dv = nullptr;
	while (!Regs.empty()) {
	if (!dv) {
	- dv = Regs.pop_back_val().Value;
	+ dv = Regs.pop_back_val()->Value;
	// Force the first dv to match the current instruction.
	dv->AvailableDomains = dv->getCommonDomains(available);
	assert(dv->AvailableDomains && "Domain should have been filtered");
	continue;
	}

	- DomainValue *Latest = Regs.pop_back_val().Value;
	+ DomainValue *Latest = Regs.pop_back_val()->Value;
	// Skip already merged values.
	if (Latest == dv \|\| Latest->Next)
	continue;
	if (merge(dv, Latest))
	continue;

	// If latest didn't merge, it is useless now. Kill all registers using it.
	for (int i : used) {
	assert(LiveRegs && "no space allocated for live registers");
	if (LiveRegs[i].Value == Latest)
	kill(i);
	}
	}

	// dv is the DomainValue we are going to use for this instruction.
	if (!dv) {
	dv = alloc();
	dv->AvailableDomains = available;
	}
	dv->Instrs.push_back(mi);

	// Finally set all defs and non-collapsed uses to dv. We must iterate through
	// all the operators, including imp-def ones.
	for (MachineInstr::mop_iterator ii = mi->operands_begin(),
	ee = mi->operands_end();
	ii != ee; ++ii) {
	MachineOperand &mo = *ii;
	if (!mo.isReg()) continue;
	for (int rx : regIndices(mo.getReg())) {
	if (!LiveRegs[rx].Value \|\| (mo.isDef() && LiveRegs[rx].Value != dv)) {
	kill(rx);
	setLiveReg(rx, dv);
	}
	}
	}
	}

	bool ExeDepsFix::runOnMachineFunction(MachineFunction &mf) {
	if (skipFunction(*mf.getFunction()))
	return false;
	MF = &mf;
	TII = MF->getSubtarget().getInstrInfo();
	TRI = MF->getSubtarget().getRegisterInfo();
	RegClassInfo.runOnMachineFunction(mf);
	LiveRegs = nullptr;
	assert(NumRegs == RC->getNumRegs() && "Bad regclass");

	DEBUG(dbgs() << "********** FIX EXECUTION DEPENDENCIES: "
	<< TRI->getRegClassName(RC) << " **********\n");

	// If no relevant registers are used in the function, we can skip it
	// completely.
	bool anyregs = false;
	const MachineRegisterInfo &MRI = mf.getRegInfo();
	for (unsigned Reg : *RC) {
	if (MRI.isPhysRegUsed(Reg)) {
	anyregs = true;
	break;
	}
	}
	if (!anyregs) return false;

	// Initialize the AliasMap on the first use.
	if (AliasMap.empty()) {
	// Given a PhysReg, AliasMap[PhysReg] returns a list of indices into RC and
	// therefore the LiveRegs array.
	AliasMap.resize(TRI->getNumRegs());
	for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i)
	for (MCRegAliasIterator AI(RC->getRegister(i), TRI, true);
	AI.isValid(); ++AI)
	AliasMap[*AI].push_back(i);
	}

	MachineBasicBlock Entry = &MF->begin();
	ReversePostOrderTraversal<MachineBasicBlock*> RPOT(Entry);
	SmallVector<MachineBasicBlock*, 16> Loops;
	for (ReversePostOrderTraversal<MachineBasicBlock*>::rpo_iterator
	MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) {
	MachineBasicBlock MBB = MBBI;
	enterBasicBlock(MBB);
	if (SeenUnknownBackEdge)
	Loops.push_back(MBB);
	for (MachineInstr &MI : *MBB)
	visitInstr(&MI);
	processUndefReads(MBB);
	leaveBasicBlock(MBB);
	}

	// Visit all the loop blocks again in order to merge DomainValues from
	// back-edges.
	for (MachineBasicBlock *MBB : Loops) {
	enterBasicBlock(MBB);
	for (MachineInstr &MI : *MBB)
	if (!MI.isDebugValue())
	processDefs(&MI, false);
	processUndefReads(MBB);
	leaveBasicBlock(MBB);
	}

	// Clear the LiveOuts vectors and collapse any remaining DomainValues.
	for (ReversePostOrderTraversal<MachineBasicBlock*>::rpo_iterator
	MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) {
	LiveOutMap::const_iterator FI = LiveOuts.find(*MBBI);
	if (FI == LiveOuts.end() \|\| !FI->second)
	continue;
	for (unsigned i = 0, e = NumRegs; i != e; ++i)
	if (FI->second[i].Value)
	release(FI->second[i].Value);
	delete[] FI->second;
	}
	LiveOuts.clear();
	UndefReads.clear();
	Avail.clear();
	Allocator.DestroyAll();

	return false;
	}

	FunctionPass *
	llvm::createExecutionDependencyFixPass(const TargetRegisterClass *RC) {
	return new ExeDepsFix(RC);
	}
	Index: projects/clang400-import/contrib/llvm/tools/clang
	===================================================================
	--- projects/clang400-import/contrib/llvm/tools/clang (revision 314417)
	+++ projects/clang400-import/contrib/llvm/tools/clang (revision 314418)

	Property changes on: projects/clang400-import/contrib/llvm/tools/clang
	___________________________________________________________________
	Modified: svn:mergeinfo
	## -0,0 +0,1 ##
	Merged /vendor/clang/dist:r314268-314417
	Index: projects/clang400-import/contrib/llvm/tools/lld
	===================================================================
	--- projects/clang400-import/contrib/llvm/tools/lld (revision 314417)
	+++ projects/clang400-import/contrib/llvm/tools/lld (revision 314418)

	Property changes on: projects/clang400-import/contrib/llvm/tools/lld
	___________________________________________________________________
	Modified: svn:mergeinfo
	## -0,0 +0,1 ##
	Merged /vendor/lld/dist:r314269-314417
	Index: projects/clang400-import/contrib/llvm/tools/lldb
	===================================================================
	--- projects/clang400-import/contrib/llvm/tools/lldb (revision 314417)
	+++ projects/clang400-import/contrib/llvm/tools/lldb (revision 314418)

	Property changes on: projects/clang400-import/contrib/llvm/tools/lldb
	___________________________________________________________________
	Modified: svn:mergeinfo
	## -0,0 +0,1 ##
	Merged /vendor/lldb/dist:r314269-314417
	Index: projects/clang400-import/contrib/llvm/tools/llvm-xray/xray-converter.cc
	===================================================================
	--- projects/clang400-import/contrib/llvm/tools/llvm-xray/xray-converter.cc (revision 314417)
	+++ projects/clang400-import/contrib/llvm/tools/llvm-xray/xray-converter.cc (revision 314418)
	@@ -1,202 +1,202 @@
	//===- xray-converter.cc - XRay Trace Conversion --------------------------===//
	//
	// The LLVM Compiler Infrastructure
	//
	// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.
	//
	//===----------------------------------------------------------------------===//
	//
	// Implements the trace conversion functions.
	//
	//===----------------------------------------------------------------------===//
	#include "xray-converter.h"

	#include "xray-extract.h"
	#include "xray-registry.h"
	#include "llvm/DebugInfo/Symbolize/Symbolize.h"
	#include "llvm/Support/EndianStream.h"
	#include "llvm/Support/FileSystem.h"
	#include "llvm/Support/YAMLTraits.h"
	#include "llvm/Support/raw_ostream.h"
	#include "llvm/XRay/Trace.h"
	#include "llvm/XRay/YAMLXRayRecord.h"

	using namespace llvm;
	using namespace xray;

	// llvm-xray convert
	// ----------------------------------------------------------------------------
	static cl::SubCommand Convert("convert", "Trace Format Conversion");
	static cl::opt<std::string> ConvertInput(cl::Positional,
	cl::desc("<xray log file>"),
	cl::Required, cl::sub(Convert));
	enum class ConvertFormats { BINARY, YAML };
	static cl::opt<ConvertFormats> ConvertOutputFormat(
	"output-format", cl::desc("output format"),
	cl::values(clEnumValN(ConvertFormats::BINARY, "raw", "output in binary"),
	clEnumValN(ConvertFormats::YAML, "yaml", "output in yaml")),
	cl::sub(Convert));
	static cl::alias ConvertOutputFormat2("f", cl::aliasopt(ConvertOutputFormat),
	cl::desc("Alias for -output-format"),
	cl::sub(Convert));
	static cl::opt<std::string>
	ConvertOutput("output", cl::value_desc("output file"), cl::init("-"),
	cl::desc("output file; use '-' for stdout"),
	cl::sub(Convert));
	static cl::alias ConvertOutput2("o", cl::aliasopt(ConvertOutput),
	cl::desc("Alias for -output"),
	cl::sub(Convert));

	static cl::opt<bool>
	ConvertSymbolize("symbolize",
	cl::desc("symbolize function ids from the input log"),
	cl::init(false), cl::sub(Convert));
	static cl::alias ConvertSymbolize2("y", cl::aliasopt(ConvertSymbolize),
	cl::desc("Alias for -symbolize"),
	cl::sub(Convert));

	static cl::opt<std::string>
	ConvertInstrMap("instr_map",
	cl::desc("binary with the instrumentation map, or "
	"a separate instrumentation map"),
	cl::value_desc("binary with xray_instr_map"),
	cl::sub(Convert), cl::init(""));
	static cl::alias ConvertInstrMap2("m", cl::aliasopt(ConvertInstrMap),
	cl::desc("Alias for -instr_map"),
	cl::sub(Convert));
	static cl::opt<bool> ConvertSortInput(
	"sort",
	cl::desc("determines whether to sort input log records by timestamp"),
	cl::sub(Convert), cl::init(true));
	static cl::alias ConvertSortInput2("s", cl::aliasopt(ConvertSortInput),
	cl::desc("Alias for -sort"),
	cl::sub(Convert));
	static cl::opt<InstrumentationMapExtractor::InputFormats> InstrMapFormat(
	"instr-map-format", cl::desc("format of instrumentation map"),
	cl::values(clEnumValN(InstrumentationMapExtractor::InputFormats::ELF, "elf",
	"instrumentation map in an ELF header"),
	clEnumValN(InstrumentationMapExtractor::InputFormats::YAML,
	"yaml", "instrumentation map in YAML")),
	cl::sub(Convert), cl::init(InstrumentationMapExtractor::InputFormats::ELF));
	static cl::alias InstrMapFormat2("t", cl::aliasopt(InstrMapFormat),
	cl::desc("Alias for -instr-map-format"),
	cl::sub(Convert));

	using llvm::yaml::IO;
	using llvm::yaml::Output;

	void TraceConverter::exportAsYAML(const Trace &Records, raw_ostream &OS) {
	YAMLXRayTrace Trace;
	const auto &FH = Records.getFileHeader();
	Trace.Header = {FH.Version, FH.Type, FH.ConstantTSC, FH.NonstopTSC,
	FH.CycleFrequency};
	Trace.Records.reserve(Records.size());
	for (const auto &R : Records) {
	Trace.Records.push_back({R.RecordType, R.CPU, R.Type, R.FuncId,
	Symbolize ? FuncIdHelper.SymbolOrNumber(R.FuncId)
	: std::to_string(R.FuncId),
	R.TSC, R.TId});
	}
	- Output Out(OS);
	+ Output Out(OS, nullptr, 0);
	Out << Trace;
	}

	void TraceConverter::exportAsRAWv1(const Trace &Records, raw_ostream &OS) {
	// First write out the file header, in the correct endian-appropriate format
	// (XRay assumes currently little endian).
	support::endian::Writer<support::endianness::little> Writer(OS);
	const auto &FH = Records.getFileHeader();
	Writer.write(FH.Version);
	Writer.write(FH.Type);
	uint32_t Bitfield{0};
	if (FH.ConstantTSC)
	Bitfield \|= 1uL;
	if (FH.NonstopTSC)
	Bitfield \|= 1uL << 1;
	Writer.write(Bitfield);
	Writer.write(FH.CycleFrequency);

	// There's 16 bytes of padding at the end of the file header.
	static constexpr uint32_t Padding4B = 0;
	Writer.write(Padding4B);
	Writer.write(Padding4B);
	Writer.write(Padding4B);
	Writer.write(Padding4B);

	// Then write out the rest of the records, still in an endian-appropriate
	// format.
	for (const auto &R : Records) {
	Writer.write(R.RecordType);
	Writer.write(R.CPU);
	switch (R.Type) {
	case RecordTypes::ENTER:
	Writer.write(uint8_t{0});
	break;
	case RecordTypes::EXIT:
	Writer.write(uint8_t{1});
	break;
	}
	Writer.write(R.FuncId);
	Writer.write(R.TSC);
	Writer.write(R.TId);
	Writer.write(Padding4B);
	Writer.write(Padding4B);
	Writer.write(Padding4B);
	}
	}

	namespace llvm {
	namespace xray {

	static CommandRegistration Unused(&Convert, []() -> Error {
	// FIXME: Support conversion to BINARY when upgrading XRay trace versions.
	int Fd;
	auto EC = sys::fs::openFileForRead(ConvertInput, Fd);
	if (EC)
	return make_error<StringError>(
	Twine("Cannot open file '") + ConvertInput + "'", EC);

	Error Err = Error::success();
	xray::InstrumentationMapExtractor Extractor(ConvertInstrMap, InstrMapFormat,
	Err);
	handleAllErrors(std::move(Err),
	[&](const ErrorInfoBase &E) { E.log(errs()); });

	const auto &FunctionAddresses = Extractor.getFunctionAddresses();
	symbolize::LLVMSymbolizer::Options Opts(
	symbolize::FunctionNameKind::LinkageName, true, true, false, "");
	symbolize::LLVMSymbolizer Symbolizer(Opts);
	llvm::xray::FuncIdConversionHelper FuncIdHelper(ConvertInstrMap, Symbolizer,
	FunctionAddresses);
	llvm::xray::TraceConverter TC(FuncIdHelper, ConvertSymbolize);
	raw_fd_ostream OS(ConvertOutput, EC,
	ConvertOutputFormat == ConvertFormats::BINARY
	? sys::fs::OpenFlags::F_None
	: sys::fs::OpenFlags::F_Text);
	if (EC)
	return make_error<StringError>(
	Twine("Cannot open file '") + ConvertOutput + "' for writing.", EC);

	if (auto TraceOrErr = loadTraceFile(ConvertInput, ConvertSortInput)) {
	auto &T = *TraceOrErr;
	switch (ConvertOutputFormat) {
	case ConvertFormats::YAML:
	TC.exportAsYAML(T, OS);
	break;
	case ConvertFormats::BINARY:
	TC.exportAsRAWv1(T, OS);
	break;
	}
	} else {
	return joinErrors(
	make_error<StringError>(
	Twine("Failed loading input file '") + ConvertInput + "'.",
	std::make_error_code(std::errc::executable_format_error)),
	TraceOrErr.takeError());
	}
	return Error::success();
	});

	} // namespace xray
	} // namespace llvm
	Index: projects/clang400-import/contrib/llvm/tools/llvm-xray/xray-extract.cc
	===================================================================
	--- projects/clang400-import/contrib/llvm/tools/llvm-xray/xray-extract.cc (revision 314417)
	+++ projects/clang400-import/contrib/llvm/tools/llvm-xray/xray-extract.cc (revision 314418)
	@@ -1,291 +1,291 @@
	//===- xray-extract.cc - XRay Instrumentation Map Extraction --------------===//
	//
	// The LLVM Compiler Infrastructure
	//
	// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.
	//
	//===----------------------------------------------------------------------===//
	//
	// Implementation of the xray-extract.h interface.
	//
	// FIXME: Support other XRay-instrumented binary formats other than ELF.
	//
	//===----------------------------------------------------------------------===//

	#include <type_traits>
	#include <utility>

	#include "xray-extract.h"

	#include "xray-registry.h"
	#include "xray-sleds.h"
	#include "llvm/Object/ELF.h"
	#include "llvm/Object/ObjectFile.h"
	#include "llvm/Support/CommandLine.h"
	#include "llvm/Support/DataExtractor.h"
	#include "llvm/Support/ELF.h"
	#include "llvm/Support/Error.h"
	#include "llvm/Support/FileSystem.h"
	#include "llvm/Support/Format.h"
	#include "llvm/Support/YAMLTraits.h"
	#include "llvm/Support/raw_ostream.h"

	using namespace llvm;
	using namespace llvm::xray;
	using namespace llvm::yaml;

	// llvm-xray extract
	// ----------------------------------------------------------------------------
	static cl::SubCommand Extract("extract", "Extract instrumentation maps");
	static cl::opt<std::string> ExtractInput(cl::Positional,
	cl::desc("<input file>"), cl::Required,
	cl::sub(Extract));
	static cl::opt<std::string>
	ExtractOutput("output", cl::value_desc("output file"), cl::init("-"),
	cl::desc("output file; use '-' for stdout"),
	cl::sub(Extract));
	static cl::alias ExtractOutput2("o", cl::aliasopt(ExtractOutput),
	cl::desc("Alias for -output"),
	cl::sub(Extract));

	struct YAMLXRaySledEntry {
	int32_t FuncId;
	Hex64 Address;
	Hex64 Function;
	SledEntry::FunctionKinds Kind;
	bool AlwaysInstrument;
	};

	namespace llvm {
	namespace yaml {

	template <> struct ScalarEnumerationTraits<SledEntry::FunctionKinds> {
	static void enumeration(IO &IO, SledEntry::FunctionKinds &Kind) {
	IO.enumCase(Kind, "function-enter", SledEntry::FunctionKinds::ENTRY);
	IO.enumCase(Kind, "function-exit", SledEntry::FunctionKinds::EXIT);
	IO.enumCase(Kind, "tail-exit", SledEntry::FunctionKinds::TAIL);
	}
	};

	template <> struct MappingTraits<YAMLXRaySledEntry> {
	static void mapping(IO &IO, YAMLXRaySledEntry &Entry) {
	IO.mapRequired("id", Entry.FuncId);
	IO.mapRequired("address", Entry.Address);
	IO.mapRequired("function", Entry.Function);
	IO.mapRequired("kind", Entry.Kind);
	IO.mapRequired("always-instrument", Entry.AlwaysInstrument);
	}

	static constexpr bool flow = true;
	};
	}
	}

	LLVM_YAML_IS_SEQUENCE_VECTOR(YAMLXRaySledEntry)

	namespace {

	llvm::Error LoadBinaryInstrELF(
	StringRef Filename, std::deque<SledEntry> &OutputSleds,
	InstrumentationMapExtractor::FunctionAddressMap &InstrMap,
	InstrumentationMapExtractor::FunctionAddressReverseMap &FunctionIds) {
	auto ObjectFile = object::ObjectFile::createObjectFile(Filename);

	if (!ObjectFile)
	return ObjectFile.takeError();

	// FIXME: Maybe support other ELF formats. For now, 64-bit Little Endian only.
	if (!ObjectFile->getBinary()->isELF())
	return make_error<StringError>(
	"File format not supported (only does ELF).",
	std::make_error_code(std::errc::not_supported));
	if (ObjectFile->getBinary()->getArch() != Triple::x86_64)
	return make_error<StringError>(
	"File format not supported (only does ELF little endian 64-bit).",
	std::make_error_code(std::errc::not_supported));

	// Find the section named "xray_instr_map".
	StringRef Contents = "";
	const auto &Sections = ObjectFile->getBinary()->sections();
	auto I = find_if(Sections, [&](object::SectionRef Section) {
	StringRef Name = "";
	if (Section.getName(Name))
	return false;
	return Name == "xray_instr_map";
	});
	if (I == Sections.end())
	return make_error<StringError>(
	"Failed to find XRay instrumentation map.",
	std::make_error_code(std::errc::not_supported));
	if (I->getContents(Contents))
	return make_error<StringError>(
	"Failed to get contents of 'xray_instr_map' section.",
	std::make_error_code(std::errc::executable_format_error));

	// Copy the instrumentation map data into the Sleds data structure.
	auto C = Contents.bytes_begin();
	static constexpr size_t ELF64SledEntrySize = 32;

	if ((C - Contents.bytes_end()) % ELF64SledEntrySize != 0)
	return make_error<StringError>(
	"Instrumentation map entries not evenly divisible by size of an XRay "
	"sled entry in ELF64.",
	std::make_error_code(std::errc::executable_format_error));

	int32_t FuncId = 1;
	uint64_t CurFn = 0;
	std::deque<SledEntry> Sleds;
	for (; C != Contents.bytes_end(); C += ELF64SledEntrySize) {
	DataExtractor Extractor(
	StringRef(reinterpret_cast<const char *>(C), ELF64SledEntrySize), true,
	8);
	Sleds.push_back({});
	auto &Entry = Sleds.back();
	uint32_t OffsetPtr = 0;
	Entry.Address = Extractor.getU64(&OffsetPtr);
	Entry.Function = Extractor.getU64(&OffsetPtr);
	auto Kind = Extractor.getU8(&OffsetPtr);
	switch (Kind) {
	case 0: // ENTRY
	Entry.Kind = SledEntry::FunctionKinds::ENTRY;
	break;
	case 1: // EXIT
	Entry.Kind = SledEntry::FunctionKinds::EXIT;
	break;
	case 2: // TAIL
	Entry.Kind = SledEntry::FunctionKinds::TAIL;
	break;
	default:
	return make_error<StringError>(
	Twine("Encountered unknown sled type ") + "'" + Twine(int32_t{Kind}) +
	"'.",
	std::make_error_code(std::errc::executable_format_error));
	}
	Entry.AlwaysInstrument = Extractor.getU8(&OffsetPtr) != 0;

	// We replicate the function id generation scheme implemented in the runtime
	// here. Ideally we should be able to break it out, or output this map from
	// the runtime, but that's a design point we can discuss later on. For now,
	// we replicate the logic and move on.
	if (CurFn == 0) {
	CurFn = Entry.Function;
	InstrMap[FuncId] = Entry.Function;
	FunctionIds[Entry.Function] = FuncId;
	}
	if (Entry.Function != CurFn) {
	++FuncId;
	CurFn = Entry.Function;
	InstrMap[FuncId] = Entry.Function;
	FunctionIds[Entry.Function] = FuncId;
	}
	}
	OutputSleds = std::move(Sleds);
	return llvm::Error::success();
	}

	Error LoadYAMLInstrMap(
	StringRef Filename, std::deque<SledEntry> &Sleds,
	InstrumentationMapExtractor::FunctionAddressMap &InstrMap,
	InstrumentationMapExtractor::FunctionAddressReverseMap &FunctionIds) {
	int Fd;
	if (auto EC = sys::fs::openFileForRead(Filename, Fd))
	return make_error<StringError>(
	Twine("Failed opening file '") + Filename + "' for reading.", EC);

	uint64_t FileSize;
	if (auto EC = sys::fs::file_size(Filename, FileSize))
	return make_error<StringError>(
	Twine("Failed getting size of file '") + Filename + "'.", EC);

	std::error_code EC;
	sys::fs::mapped_file_region MappedFile(
	Fd, sys::fs::mapped_file_region::mapmode::readonly, FileSize, 0, EC);
	if (EC)
	return make_error<StringError>(
	Twine("Failed memory-mapping file '") + Filename + "'.", EC);

	std::vector<YAMLXRaySledEntry> YAMLSleds;
	Input In(StringRef(MappedFile.data(), MappedFile.size()));
	In >> YAMLSleds;
	if (In.error())
	return make_error<StringError>(
	Twine("Failed loading YAML document from '") + Filename + "'.",
	In.error());

	for (const auto &Y : YAMLSleds) {
	InstrMap[Y.FuncId] = Y.Function;
	FunctionIds[Y.Function] = Y.FuncId;
	Sleds.push_back(
	SledEntry{Y.Address, Y.Function, Y.Kind, Y.AlwaysInstrument});
	}
	return Error::success();
	}

	} // namespace

	InstrumentationMapExtractor::InstrumentationMapExtractor(std::string Filename,
	InputFormats Format,
	Error &EC) {
	ErrorAsOutParameter ErrAsOutputParam(&EC);
	if (Filename.empty()) {
	EC = Error::success();
	return;
	}
	switch (Format) {
	case InputFormats::ELF: {
	EC = handleErrors(
	LoadBinaryInstrELF(Filename, Sleds, FunctionAddresses, FunctionIds),
	[&](std::unique_ptr<ErrorInfoBase> E) {
	return joinErrors(
	make_error<StringError>(
	Twine("Cannot extract instrumentation map from '") +
	Filename + "'.",
	std::make_error_code(std::errc::executable_format_error)),
	std::move(E));
	});
	break;
	}
	case InputFormats::YAML: {
	EC = handleErrors(
	LoadYAMLInstrMap(Filename, Sleds, FunctionAddresses, FunctionIds),
	[&](std::unique_ptr<ErrorInfoBase> E) {
	return joinErrors(
	make_error<StringError>(
	Twine("Cannot load YAML instrumentation map from '") +
	Filename + "'.",
	std::make_error_code(std::errc::executable_format_error)),
	std::move(E));
	});
	break;
	}
	}
	}

	void InstrumentationMapExtractor::exportAsYAML(raw_ostream &OS) {
	// First we translate the sleds into the YAMLXRaySledEntry objects in a deque.
	std::vector<YAMLXRaySledEntry> YAMLSleds;
	YAMLSleds.reserve(Sleds.size());
	for (const auto &Sled : Sleds) {
	YAMLSleds.push_back({FunctionIds[Sled.Function], Sled.Address,
	Sled.Function, Sled.Kind, Sled.AlwaysInstrument});
	}
	- Output Out(OS);
	+ Output Out(OS, nullptr, 0);
	Out << YAMLSleds;
	}

	static CommandRegistration Unused(&Extract, []() -> Error {
	Error Err = Error::success();
	xray::InstrumentationMapExtractor Extractor(
	ExtractInput, InstrumentationMapExtractor::InputFormats::ELF, Err);
	if (Err)
	return Err;

	std::error_code EC;
	raw_fd_ostream OS(ExtractOutput, EC, sys::fs::OpenFlags::F_Text);
	if (EC)
	return make_error<StringError>(
	Twine("Cannot open file '") + ExtractOutput + "' for writing.", EC);
	Extractor.exportAsYAML(OS);
	return Error::success();
	});
	Index: projects/clang400-import/contrib/llvm
	===================================================================
	--- projects/clang400-import/contrib/llvm (revision 314417)
	+++ projects/clang400-import/contrib/llvm (revision 314418)

	Property changes on: projects/clang400-import/contrib/llvm
	___________________________________________________________________
	Modified: svn:mergeinfo
	## -0,0 +0,1 ##
	Merged /vendor/llvm/dist:r314268-314417
	Index: projects/clang400-import/lib/clang/include/clang/Basic/Version.inc
	===================================================================
	--- projects/clang400-import/lib/clang/include/clang/Basic/Version.inc (revision 314417)
	+++ projects/clang400-import/lib/clang/include/clang/Basic/Version.inc (revision 314418)
	@@ -1,11 +1,11 @@
	/* $FreeBSD$ */

	#define CLANG_VERSION 4.0.0
	#define CLANG_VERSION_STRING "4.0.0"
	#define CLANG_VERSION_MAJOR 4
	#define CLANG_VERSION_MINOR 0
	#define CLANG_VERSION_PATCHLEVEL 0

	#define CLANG_VENDOR "FreeBSD "

	-#define SVN_REVISION "296202"
	+#define SVN_REVISION "296509"
	Index: projects/clang400-import/lib/clang/include/lld/Config/Version.inc
	===================================================================
	--- projects/clang400-import/lib/clang/include/lld/Config/Version.inc (revision 314417)
	+++ projects/clang400-import/lib/clang/include/lld/Config/Version.inc (revision 314418)
	@@ -1,8 +1,8 @@
	// $FreeBSD$

	#define LLD_VERSION 4.0.0
	#define LLD_VERSION_STRING "4.0.0"
	#define LLD_VERSION_MAJOR 4
	#define LLD_VERSION_MINOR 0
	-#define LLD_REVISION_STRING "296202"
	+#define LLD_REVISION_STRING "296509"
	#define LLD_REPOSITORY_STRING "FreeBSD"

File Metadata

Mime Type: text/x-c++
Expires: Tue, May 7, 4:32 AM (2 d)
Storage Engine: blob
Storage Format: Raw Data
Storage Handle: 9276585
Default Alt Text: (53 KB)

No OneTemporaryActions

View Options

File Metadata

Event Timeline

No OneTemporary
Actions