Index: head/sys/arm/altera/socfpga/socfpga_machdep.c =================================================================== --- head/sys/arm/altera/socfpga/socfpga_machdep.c (revision 314394) +++ head/sys/arm/altera/socfpga/socfpga_machdep.c (revision 314395) @@ -1,164 +1,176 @@ /*- * Copyright (c) 2014-2017 Ruslan Bukin * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "platform_if.h" +#if defined(SOC_ALTERA_CYCLONE5) static int socfpga_devmap_init(platform_t plat) { /* UART */ devmap_add_entry(0xffc00000, 0x100000); /* * USB OTG * * We use static device map for USB due to some bug in the Altera * which throws Translation Fault (P) exception on high load. * It might be caused due to some power save options being turned * on or something else. */ devmap_add_entry(0xffb00000, 0x100000); /* dwmmc */ devmap_add_entry(0xff700000, 0x100000); /* scu */ devmap_add_entry(0xfff00000, 0x100000); /* FPGA memory window, 256MB */ devmap_add_entry(0xd0000000, 0x10000000); return (0); } +#endif +#if defined(SOC_ALTERA_ARRIA10) static int socfpga_a10_devmap_init(platform_t plat) { /* UART */ devmap_add_entry(0xffc00000, 0x100000); /* USB OTG */ devmap_add_entry(0xffb00000, 0x100000); /* dwmmc */ devmap_add_entry(0xff800000, 0x100000); /* scu */ devmap_add_entry(0xfff00000, 0x100000); return (0); } +#endif static void -_socfpga_cpu_reset(platform_t plat, uint32_t reg) +_socfpga_cpu_reset(bus_size_t reg) { uint32_t paddr; bus_addr_t vaddr; phandle_t node; if (rstmgr_warmreset(reg) == 0) goto end; node = OF_finddevice("/soc/rstmgr"); if (node == -1) goto end; if ((OF_getencprop(node, "reg", &paddr, sizeof(paddr))) > 0) { if (bus_space_map(fdtbus_bs_tag, paddr, 0x8, 0, &vaddr) == 0) { bus_space_write_4(fdtbus_bs_tag, vaddr, reg, CTRL_SWWARMRSTREQ); } } end: while (1); } +#if defined(SOC_ALTERA_CYCLONE5) static void socfpga_cpu_reset(platform_t plat) { - _socfpga_cpu_reset(plat, RSTMGR_CTRL); + _socfpga_cpu_reset(RSTMGR_CTRL); } +#endif +#if defined(SOC_ALTERA_ARRIA10) static void socfpga_a10_cpu_reset(platform_t plat) { - _socfpga_cpu_reset(plat, RSTMGR_A10_CTRL); + _socfpga_cpu_reset(RSTMGR_A10_CTRL); } +#endif +#if defined(SOC_ALTERA_CYCLONE5) static platform_method_t socfpga_methods[] = { PLATFORMMETHOD(platform_devmap_init, socfpga_devmap_init), PLATFORMMETHOD(platform_cpu_reset, socfpga_cpu_reset), #ifdef SMP PLATFORMMETHOD(platform_mp_setmaxid, socfpga_mp_setmaxid), PLATFORMMETHOD(platform_mp_start_ap, socfpga_mp_start_ap), #endif PLATFORMMETHOD_END, }; FDT_PLATFORM_DEF(socfpga, "socfpga", 0, "altr,socfpga-cyclone5", 200); +#endif +#if defined(SOC_ALTERA_ARRIA10) static platform_method_t socfpga_a10_methods[] = { PLATFORMMETHOD(platform_devmap_init, socfpga_a10_devmap_init), PLATFORMMETHOD(platform_cpu_reset, socfpga_a10_cpu_reset), #ifdef SMP PLATFORMMETHOD(platform_mp_setmaxid, socfpga_mp_setmaxid), PLATFORMMETHOD(platform_mp_start_ap, socfpga_a10_mp_start_ap), #endif PLATFORMMETHOD_END, }; FDT_PLATFORM_DEF(socfpga_a10, "socfpga", 0, "altr,socfpga-arria10", 200); +#endif Index: head/sys/arm/altera/socfpga/socfpga_mp.c =================================================================== --- head/sys/arm/altera/socfpga/socfpga_mp.c (revision 314394) +++ head/sys/arm/altera/socfpga/socfpga_mp.c (revision 314395) @@ -1,202 +1,232 @@ /*- * Copyright (c) 2014-2017 Ruslan Bukin * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define SCU_PHYSBASE 0xFFFEC000 #define SCU_PHYSBASE_A10 0xFFFFC000 #define SCU_SIZE 0x100 #define SCU_CONTROL_REG 0x00 #define SCU_CONTROL_ENABLE (1 << 0) #define SCU_CONFIG_REG 0x04 #define SCU_CONFIG_REG_NCPU_MASK 0x03 #define SCU_CPUPOWER_REG 0x08 #define SCU_INV_TAGS_REG 0x0c #define SCU_DIAG_CONTROL 0x30 #define SCU_DIAG_DISABLE_MIGBIT (1 << 0) #define SCU_FILTER_START_REG 0x40 #define SCU_FILTER_END_REG 0x44 #define SCU_SECURE_ACCESS_REG 0x50 #define SCU_NONSECURE_ACCESS_REG 0x54 #define RSTMGR_PHYSBASE 0xFFD05000 #define RSTMGR_SIZE 0x100 #define RAM_PHYSBASE 0x0 #define RAM_SIZE 0x1000 -#define SOCFPGA_SOCKIT 1 -#define SOCFPGA_SOCDK 2 +#define SOCFPGA_ARRIA10 1 +#define SOCFPGA_CYCLONE5 2 extern char *mpentry_addr; static void socfpga_trampoline(void); static void socfpga_trampoline(void) { __asm __volatile( "ldr pc, 1f\n" ".globl mpentry_addr\n" "mpentry_addr:\n" "1: .space 4\n"); } void socfpga_mp_setmaxid(platform_t plat) { int hwcpu, ncpu; /* If we've already set this don't bother to do it again. */ if (mp_ncpus != 0) return; hwcpu = 2; ncpu = hwcpu; TUNABLE_INT_FETCH("hw.ncpu", &ncpu); if (ncpu < 1 || ncpu > hwcpu) ncpu = hwcpu; mp_ncpus = ncpu; mp_maxid = ncpu - 1; } - static void -_socfpga_mp_start_ap(platform_t plat, uint32_t platid) +_socfpga_mp_start_ap(uint32_t platid) { bus_space_handle_t scu, rst, ram; int reg; - if (platid == SOCFPGA_SOCDK) { + switch (platid) { +#if defined(SOC_ALTERA_ARRIA10) + case SOCFPGA_ARRIA10: if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE_A10, SCU_SIZE, 0, &scu) != 0) - panic("Couldn't map the SCU\n"); - } else { + panic("Couldn't map the SCU\n"); + break; +#endif +#if defined(SOC_ALTERA_CYCLONE5) + case SOCFPGA_CYCLONE5: if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0) - panic("Couldn't map the SCU\n"); + panic("Couldn't map the SCU\n"); + break; +#endif + default: + panic("Unknown platform id %d\n", platid); } + if (bus_space_map(fdtbus_bs_tag, RSTMGR_PHYSBASE, RSTMGR_SIZE, 0, &rst) != 0) panic("Couldn't map the reset manager (RSTMGR)\n"); if (bus_space_map(fdtbus_bs_tag, RAM_PHYSBASE, RAM_SIZE, 0, &ram) != 0) panic("Couldn't map the first physram page\n"); /* Invalidate SCU cache tags */ bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000ffff); /* * Erratum ARM/MP: 764369 (problems with cache maintenance). * Setting the "disable-migratory bit" in the undocumented SCU * Diagnostic Control Register helps work around the problem. */ reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL); reg |= (SCU_DIAG_DISABLE_MIGBIT); bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, reg); /* Put CPU1 to reset state */ - if (platid == SOCFPGA_SOCDK) { + switch (platid) { +#if defined(SOC_ALTERA_ARRIA10) + case SOCFPGA_ARRIA10: bus_space_write_4(fdtbus_bs_tag, rst, RSTMGR_A10_MPUMODRST, MPUMODRST_CPU1); - } else { + break; +#endif +#if defined(SOC_ALTERA_CYCLONE5) + case SOCFPGA_CYCLONE5: bus_space_write_4(fdtbus_bs_tag, rst, RSTMGR_MPUMODRST, MPUMODRST_CPU1); + break; +#endif + default: + panic("Unknown platform id %d\n", platid); } /* Enable the SCU, then clean the cache on this core */ reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG); reg |= (SCU_CONTROL_ENABLE); bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG, reg); /* Set up trampoline code */ mpentry_addr = (char *)pmap_kextract((vm_offset_t)mpentry); bus_space_write_region_4(fdtbus_bs_tag, ram, 0, (uint32_t *)&socfpga_trampoline, 8); dcache_wbinv_poc_all(); /* Put CPU1 out from reset */ - if (platid == SOCFPGA_SOCDK) { + switch (platid) { +#if defined(SOC_ALTERA_ARRIA10) + case SOCFPGA_ARRIA10: bus_space_write_4(fdtbus_bs_tag, rst, RSTMGR_A10_MPUMODRST, 0); - } else { + break; +#endif +#if defined(SOC_ALTERA_CYCLONE5) + case SOCFPGA_CYCLONE5: bus_space_write_4(fdtbus_bs_tag, rst, RSTMGR_MPUMODRST, 0); + break; +#endif + default: + panic("Unknown platform id %d\n", platid); } dsb(); sev(); bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE); bus_space_unmap(fdtbus_bs_tag, rst, RSTMGR_SIZE); bus_space_unmap(fdtbus_bs_tag, ram, RAM_SIZE); } +#if defined(SOC_ALTERA_ARRIA10) void socfpga_a10_mp_start_ap(platform_t plat) { - _socfpga_mp_start_ap(plat, SOCFPGA_SOCDK); + _socfpga_mp_start_ap(SOCFPGA_ARRIA10); } +#endif +#if defined(SOC_ALTERA_CYCLONE5) void socfpga_mp_start_ap(platform_t plat) { - _socfpga_mp_start_ap(plat, SOCFPGA_SOCKIT); + _socfpga_mp_start_ap(SOCFPGA_CYCLONE5); } - +#endif Index: head/sys/arm/conf/SOCFPGA =================================================================== --- head/sys/arm/conf/SOCFPGA (revision 314394) +++ head/sys/arm/conf/SOCFPGA (revision 314395) @@ -1,97 +1,100 @@ # # Kernel configuration for Altera SOCFPGA development kits. # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ ident SOCFPGA include "std.armv6" include "../altera/socfpga/std.socfpga" makeoptions MODULES_OVERRIDE="" makeoptions WERROR="-Werror" options SCHED_ULE # ULE scheduler options PLATFORM # Platform based SoC options PLATFORM_SMP options SMP # Enable multiple cores options MULTIDELAY +options SOC_ALTERA_ARRIA10 +options SOC_ALTERA_CYCLONE5 + # NFS root from boopt/dhcp #options BOOTP #options BOOTP_NFSROOT #options BOOTP_COMPAT #options BOOTP_NFSV3 #options BOOTP_WIRED_TO=ue0 # Interrupt controller device gic options INTRNG # ARM MPCore timer device mpcore_timer # MMC/SD/SDIO Card slot support device mmc # mmc/sd bus device mmcsd # mmc/sd flash cards device dwmmc # Pseudo devices device loop device random device pty device md device gpio # USB support options USB_HOST_ALIGN=64 # Align usb buffers to cache line size. device usb device dwcotg device umass device scbus # SCSI bus (required for ATA/SCSI) device da # Direct Access (disks) device pass # Serial ports device uart device uart_snps # I2C (TWSI) device iic device iicbus # SPI device spibus # Ethernet device ether device mii device smsc device smscphy device dwc device micphy # USB ethernet support, requires miibus device miibus device axe # ASIX Electronics USB Ethernet device bpf # Berkeley packet filter # Flattened Device Tree options FDT # Configure using FDT/DTB data Index: head/sys/conf/options.arm =================================================================== --- head/sys/conf/options.arm (revision 314394) +++ head/sys/conf/options.arm (revision 314395) @@ -1,84 +1,86 @@ #$FreeBSD$ ARMV6 opt_global.h ARM_CACHE_LOCK_ENABLE opt_global.h ARM_KERN_DIRECTMAP opt_vm.h ARM_L2_PIPT opt_global.h ARM_MANY_BOARD opt_global.h NKPT2PG opt_pmap.h ARM_WANT_TP_ADDRESS opt_global.h COUNTS_PER_SEC opt_timer.h CPSW_ETHERSWITCH opt_cpsw.h CPU_ARM9 opt_global.h CPU_ARM9E opt_global.h CPU_ARM1176 opt_global.h CPU_CORTEXA opt_global.h CPU_KRAIT opt_global.h CPU_FA526 opt_global.h CPU_MV_PJ4B opt_global.h CPU_XSCALE_81342 opt_global.h CPU_XSCALE_IXP425 opt_global.h CPU_XSCALE_IXP435 opt_global.h CPU_XSCALE_PXA2X0 opt_global.h SMP_ON_UP opt_global.h # Runtime detection of MP extensions DEV_GIC opt_global.h DEV_PMU opt_global.h EFI opt_platform.h FLASHADDR opt_global.h GIC_DEFAULT_ICFGR_INIT opt_global.h INTRNG opt_global.h IPI_IRQ_START opt_smp.h IPI_IRQ_END opt_smp.h FREEBSD_BOOT_LOADER opt_global.h IXP4XX_FLASH_SIZE opt_global.h KERNBASE opt_global.h KERNVIRTADDR opt_global.h LINUX_BOOT_ABI opt_global.h LOADERRAMADDR opt_global.h MULTIDELAY opt_global.h PHYSADDR opt_global.h PLATFORM opt_global.h PLATFORM_SMP opt_global.h SOCDEV_PA opt_global.h SOCDEV_VA opt_global.h PV_STATS opt_pmap.h QEMU_WORKAROUNDS opt_global.h SOC_ALLWINNER_A10 opt_global.h SOC_ALLWINNER_A13 opt_global.h SOC_ALLWINNER_A20 opt_global.h SOC_ALLWINNER_A31 opt_global.h SOC_ALLWINNER_A31S opt_global.h SOC_ALLWINNER_A33 opt_global.h SOC_ALLWINNER_A83T opt_global.h SOC_ALLWINNER_H3 opt_global.h +SOC_ALTERA_ARRIA10 opt_global.h +SOC_ALTERA_CYCLONE5 opt_global.h SOC_BCM2835 opt_global.h SOC_BCM2836 opt_global.h SOC_IMX51 opt_global.h SOC_IMX53 opt_global.h SOC_IMX6 opt_global.h SOC_MV_ARMADAXP opt_global.h SOC_MV_ARMADA38X opt_global.h SOC_MV_DISCOVERY opt_global.h SOC_MV_DOVE opt_global.h SOC_MV_FREY opt_global.h SOC_MV_KIRKWOOD opt_global.h SOC_MV_LOKIPLUS opt_global.h SOC_MV_ORION opt_global.h SOC_OMAP3 opt_global.h SOC_OMAP4 opt_global.h SOC_ROCKCHIP_RK3188 opt_global.h SOC_TI_AM335X opt_global.h SOC_TEGRA2 opt_global.h XSCALE_CACHE_READ_WRITE_ALLOCATE opt_global.h XSACLE_DISABLE_CCNT opt_timer.h VERBOSE_INIT_ARM opt_global.h VM_MAXUSER_ADDRESS opt_global.h AT91_ATE_USE_RMII opt_at91.h AT91_MACB_USE_RMII opt_at91.h AT91_MCI_ALLOW_OVERCLOCK opt_at91.h AT91_MCI_HAS_4WIRE opt_at91.h AT91_MCI_SLOT_B opt_at91.h GFB_DEBUG opt_gfb.h GFB_NO_FONT_LOADING opt_gfb.h GFB_NO_MODE_CHANGE opt_gfb.h AT91C_MAIN_CLOCK opt_at91.h VFP opt_global.h