Index: head/sys/arm/altera/socfpga/socfpga_machdep.c =================================================================== --- head/sys/arm/altera/socfpga/socfpga_machdep.c (revision 314388) +++ head/sys/arm/altera/socfpga/socfpga_machdep.c (revision 314389) @@ -1,123 +1,164 @@ /*- - * Copyright (c) 2014 Ruslan Bukin + * Copyright (c) 2014-2017 Ruslan Bukin * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "platform_if.h" static int socfpga_devmap_init(platform_t plat) { /* UART */ devmap_add_entry(0xffc00000, 0x100000); /* * USB OTG * * We use static device map for USB due to some bug in the Altera * which throws Translation Fault (P) exception on high load. * It might be caused due to some power save options being turned * on or something else. */ devmap_add_entry(0xffb00000, 0x100000); /* dwmmc */ devmap_add_entry(0xff700000, 0x100000); /* scu */ devmap_add_entry(0xfff00000, 0x100000); /* FPGA memory window, 256MB */ devmap_add_entry(0xd0000000, 0x10000000); return (0); } +static int +socfpga_a10_devmap_init(platform_t plat) +{ + + /* UART */ + devmap_add_entry(0xffc00000, 0x100000); + + /* USB OTG */ + devmap_add_entry(0xffb00000, 0x100000); + + /* dwmmc */ + devmap_add_entry(0xff800000, 0x100000); + + /* scu */ + devmap_add_entry(0xfff00000, 0x100000); + + return (0); +} + static void -socfpga_cpu_reset(platform_t plat) +_socfpga_cpu_reset(platform_t plat, uint32_t reg) { uint32_t paddr; bus_addr_t vaddr; phandle_t node; - if (rstmgr_warmreset() == 0) + if (rstmgr_warmreset(reg) == 0) goto end; - node = OF_finddevice("rstmgr"); + node = OF_finddevice("/soc/rstmgr"); if (node == -1) goto end; if ((OF_getencprop(node, "reg", &paddr, sizeof(paddr))) > 0) { if (bus_space_map(fdtbus_bs_tag, paddr, 0x8, 0, &vaddr) == 0) { bus_space_write_4(fdtbus_bs_tag, vaddr, - RSTMGR_CTRL, CTRL_SWWARMRSTREQ); + reg, CTRL_SWWARMRSTREQ); } } end: while (1); } +static void +socfpga_cpu_reset(platform_t plat) +{ + + _socfpga_cpu_reset(plat, RSTMGR_CTRL); +} + +static void +socfpga_a10_cpu_reset(platform_t plat) +{ + + _socfpga_cpu_reset(plat, RSTMGR_A10_CTRL); +} + static platform_method_t socfpga_methods[] = { PLATFORMMETHOD(platform_devmap_init, socfpga_devmap_init), PLATFORMMETHOD(platform_cpu_reset, socfpga_cpu_reset), - #ifdef SMP PLATFORMMETHOD(platform_mp_setmaxid, socfpga_mp_setmaxid), PLATFORMMETHOD(platform_mp_start_ap, socfpga_mp_start_ap), #endif - PLATFORMMETHOD_END, }; +FDT_PLATFORM_DEF(socfpga, "socfpga", 0, "altr,socfpga-cyclone5", 200); -FDT_PLATFORM_DEF(socfpga, "socfpga", 0, "altr,socfpga", 0); +static platform_method_t socfpga_a10_methods[] = { + PLATFORMMETHOD(platform_devmap_init, socfpga_a10_devmap_init), + PLATFORMMETHOD(platform_cpu_reset, socfpga_a10_cpu_reset), +#ifdef SMP + PLATFORMMETHOD(platform_mp_setmaxid, socfpga_mp_setmaxid), + PLATFORMMETHOD(platform_mp_start_ap, socfpga_a10_mp_start_ap), +#endif + PLATFORMMETHOD_END, +}; +FDT_PLATFORM_DEF(socfpga_a10, "socfpga", 0, "altr,socfpga-arria10", 200); Index: head/sys/arm/altera/socfpga/socfpga_manager.c =================================================================== --- head/sys/arm/altera/socfpga/socfpga_manager.c (revision 314388) +++ head/sys/arm/altera/socfpga/socfpga_manager.c (revision 314389) @@ -1,431 +1,431 @@ /*- * Copyright (c) 2014 Ruslan Bukin * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Altera FPGA Manager. * Chapter 4, Cyclone V Device Handbook (CV-5V2 2014.07.22) */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* FPGA Manager Module Registers */ #define FPGAMGR_STAT 0x0 /* Status Register */ #define STAT_MSEL_MASK 0x1f #define STAT_MSEL_SHIFT 3 #define STAT_MODE_SHIFT 0 #define STAT_MODE_MASK 0x7 #define FPGAMGR_CTRL 0x4 /* Control Register */ #define CTRL_AXICFGEN (1 << 8) #define CTRL_CDRATIO_MASK 0x3 #define CTRL_CDRATIO_SHIFT 6 #define CTRL_CFGWDTH_MASK 1 #define CTRL_CFGWDTH_SHIFT 9 #define CTRL_NCONFIGPULL (1 << 2) #define CTRL_NCE (1 << 1) #define CTRL_EN (1 << 0) #define FPGAMGR_DCLKCNT 0x8 /* DCLK Count Register */ #define FPGAMGR_DCLKSTAT 0xC /* DCLK Status Register */ #define FPGAMGR_GPO 0x10 /* General-Purpose Output Register */ #define FPGAMGR_GPI 0x14 /* General-Purpose Input Register */ #define FPGAMGR_MISCI 0x18 /* Miscellaneous Input Register */ /* Configuration Monitor (MON) Registers */ #define GPIO_INTEN 0x830 /* Interrupt Enable Register */ #define GPIO_INTMASK 0x834 /* Interrupt Mask Register */ #define GPIO_INTTYPE_LEVEL 0x838 /* Interrupt Level Register */ #define GPIO_INT_POLARITY 0x83C /* Interrupt Polarity Register */ #define GPIO_INTSTATUS 0x840 /* Interrupt Status Register */ #define GPIO_RAW_INTSTATUS 0x844 /* Raw Interrupt Status Register */ #define GPIO_PORTA_EOI 0x84C /* Clear Interrupt Register */ #define PORTA_EOI_NS (1 << 0) #define GPIO_EXT_PORTA 0x850 /* External Port A Register */ #define EXT_PORTA_CDP (1 << 10) /* Configuration done */ #define GPIO_LS_SYNC 0x860 /* Synchronization Level Register */ #define GPIO_VER_ID_CODE 0x86C /* GPIO Version Register */ #define GPIO_CONFIG_REG2 0x870 /* Configuration Register 2 */ #define GPIO_CONFIG_REG1 0x874 /* Configuration Register 1 */ #define MSEL_PP16_FAST_NOAES_NODC 0x0 #define MSEL_PP16_FAST_AES_NODC 0x1 #define MSEL_PP16_FAST_AESOPT_DC 0x2 #define MSEL_PP16_SLOW_NOAES_NODC 0x4 #define MSEL_PP16_SLOW_AES_NODC 0x5 #define MSEL_PP16_SLOW_AESOPT_DC 0x6 #define MSEL_PP32_FAST_NOAES_NODC 0x8 #define MSEL_PP32_FAST_AES_NODC 0x9 #define MSEL_PP32_FAST_AESOPT_DC 0xa #define MSEL_PP32_SLOW_NOAES_NODC 0xc #define MSEL_PP32_SLOW_AES_NODC 0xd #define MSEL_PP32_SLOW_AESOPT_DC 0xe #define CFGWDTH_16 0 #define CFGWDTH_32 1 #define CDRATIO_1 0 #define CDRATIO_2 1 #define CDRATIO_4 2 #define CDRATIO_8 3 #define FPGAMGR_MODE_POWEROFF 0x0 #define FPGAMGR_MODE_RESET 0x1 #define FPGAMGR_MODE_CONFIG 0x2 #define FPGAMGR_MODE_INIT 0x3 #define FPGAMGR_MODE_USER 0x4 struct cfgmgr_mode { int msel; int cfgwdth; int cdratio; }; static struct cfgmgr_mode cfgmgr_modes[] = { { MSEL_PP16_FAST_NOAES_NODC, CFGWDTH_16, CDRATIO_1 }, { MSEL_PP16_FAST_AES_NODC, CFGWDTH_16, CDRATIO_2 }, { MSEL_PP16_FAST_AESOPT_DC, CFGWDTH_16, CDRATIO_4 }, { MSEL_PP16_SLOW_NOAES_NODC, CFGWDTH_16, CDRATIO_1 }, { MSEL_PP16_SLOW_AES_NODC, CFGWDTH_16, CDRATIO_2 }, { MSEL_PP16_SLOW_AESOPT_DC, CFGWDTH_16, CDRATIO_4 }, { MSEL_PP32_FAST_NOAES_NODC, CFGWDTH_32, CDRATIO_1 }, { MSEL_PP32_FAST_AES_NODC, CFGWDTH_32, CDRATIO_4 }, { MSEL_PP32_FAST_AESOPT_DC, CFGWDTH_32, CDRATIO_8 }, { MSEL_PP32_SLOW_NOAES_NODC, CFGWDTH_32, CDRATIO_1 }, { MSEL_PP32_SLOW_AES_NODC, CFGWDTH_32, CDRATIO_4 }, { MSEL_PP32_SLOW_AESOPT_DC, CFGWDTH_32, CDRATIO_8 }, { -1, -1, -1 }, }; struct fpgamgr_softc { struct resource *res[3]; bus_space_tag_t bst_data; bus_space_handle_t bsh_data; struct cdev *mgr_cdev; device_t dev; }; static struct resource_spec fpgamgr_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_MEMORY, 1, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE }, { -1, 0 } }; static int fpgamgr_state_get(struct fpgamgr_softc *sc) { int reg; reg = READ4(sc, FPGAMGR_STAT); reg >>= STAT_MODE_SHIFT; reg &= STAT_MODE_MASK; return reg; } static int fpgamgr_state_wait(struct fpgamgr_softc *sc, int state) { int tout; tout = 1000; while (tout > 0) { if (fpgamgr_state_get(sc) == state) break; tout--; DELAY(10); } if (tout == 0) { return (1); } return (0); } static int fpga_open(struct cdev *dev, int flags __unused, int fmt __unused, struct thread *td __unused) { struct fpgamgr_softc *sc; struct cfgmgr_mode *mode; int msel; int reg; int i; sc = dev->si_drv1; msel = READ4(sc, FPGAMGR_STAT); msel >>= STAT_MSEL_SHIFT; msel &= STAT_MSEL_MASK; mode = NULL; for (i = 0; cfgmgr_modes[i].msel != -1; i++) { if (msel == cfgmgr_modes[i].msel) { mode = &cfgmgr_modes[i]; break; } } if (mode == NULL) { device_printf(sc->dev, "Can't configure: unknown mode\n"); return (ENXIO); } reg = READ4(sc, FPGAMGR_CTRL); reg &= ~(CTRL_CDRATIO_MASK << CTRL_CDRATIO_SHIFT); reg |= (mode->cdratio << CTRL_CDRATIO_SHIFT); reg &= ~(CTRL_CFGWDTH_MASK << CTRL_CFGWDTH_SHIFT); reg |= (mode->cfgwdth << CTRL_CFGWDTH_SHIFT); reg &= ~(CTRL_NCE); WRITE4(sc, FPGAMGR_CTRL, reg); /* Enable configuration */ reg = READ4(sc, FPGAMGR_CTRL); reg |= (CTRL_EN); WRITE4(sc, FPGAMGR_CTRL, reg); /* Reset FPGA */ reg = READ4(sc, FPGAMGR_CTRL); reg |= (CTRL_NCONFIGPULL); WRITE4(sc, FPGAMGR_CTRL, reg); /* Wait reset state */ if (fpgamgr_state_wait(sc, FPGAMGR_MODE_RESET)) { device_printf(sc->dev, "Can't get RESET state\n"); return (ENXIO); } /* Release from reset */ reg = READ4(sc, FPGAMGR_CTRL); reg &= ~(CTRL_NCONFIGPULL); WRITE4(sc, FPGAMGR_CTRL, reg); if (fpgamgr_state_wait(sc, FPGAMGR_MODE_CONFIG)) { device_printf(sc->dev, "Can't get CONFIG state\n"); return (ENXIO); } /* Clear nSTATUS edge interrupt */ WRITE4(sc, GPIO_PORTA_EOI, PORTA_EOI_NS); /* Enter configuration state */ reg = READ4(sc, FPGAMGR_CTRL); reg |= (CTRL_AXICFGEN); WRITE4(sc, FPGAMGR_CTRL, reg); return (0); } static int fpga_wait_dclk_pulses(struct fpgamgr_softc *sc, int npulses) { int tout; /* Clear done bit, if any */ if (READ4(sc, FPGAMGR_DCLKSTAT) != 0) WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1); /* Request DCLK pulses */ WRITE4(sc, FPGAMGR_DCLKCNT, npulses); /* Wait finish */ tout = 1000; while (tout > 0) { if (READ4(sc, FPGAMGR_DCLKSTAT) == 1) { WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1); break; } tout--; DELAY(10); } if (tout == 0) { return (1); } return (0); } static int fpga_close(struct cdev *dev, int flags __unused, int fmt __unused, struct thread *td __unused) { struct fpgamgr_softc *sc; int reg; sc = dev->si_drv1; reg = READ4(sc, GPIO_EXT_PORTA); if ((reg & EXT_PORTA_CDP) == 0) { device_printf(sc->dev, "Err: configuration failed\n"); return (ENXIO); } /* Exit configuration state */ reg = READ4(sc, FPGAMGR_CTRL); reg &= ~(CTRL_AXICFGEN); WRITE4(sc, FPGAMGR_CTRL, reg); /* Wait dclk pulses */ if (fpga_wait_dclk_pulses(sc, 4)) { device_printf(sc->dev, "Can't proceed 4 dclk pulses\n"); return (ENXIO); } if (fpgamgr_state_wait(sc, FPGAMGR_MODE_USER)) { device_printf(sc->dev, "Can't get USER mode\n"); return (ENXIO); } /* Disable configuration */ reg = READ4(sc, FPGAMGR_CTRL); reg &= ~(CTRL_EN); WRITE4(sc, FPGAMGR_CTRL, reg); return (0); } static int fpga_write(struct cdev *dev, struct uio *uio, int ioflag) { struct fpgamgr_softc *sc; int buffer; sc = dev->si_drv1; /* * Device supports 4-byte copy only. * TODO: add padding for <4 bytes. */ while (uio->uio_resid > 0) { uiomove(&buffer, 4, uio); bus_space_write_4(sc->bst_data, sc->bsh_data, 0x0, buffer); } return (0); } static int fpga_ioctl(struct cdev *dev, u_long cmd, caddr_t addr, int flags, struct thread *td) { return (0); } static struct cdevsw fpga_cdevsw = { .d_version = D_VERSION, .d_open = fpga_open, .d_close = fpga_close, .d_write = fpga_write, .d_ioctl = fpga_ioctl, .d_name = "FPGA Manager", }; static int fpgamgr_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); - if (!ofw_bus_is_compatible(dev, "altr,fpga-mgr")) + if (!ofw_bus_is_compatible(dev, "altr,socfpga-fpga-mgr")) return (ENXIO); device_set_desc(dev, "FPGA Manager"); return (BUS_PROBE_DEFAULT); } static int fpgamgr_attach(device_t dev) { struct fpgamgr_softc *sc; sc = device_get_softc(dev); sc->dev = dev; if (bus_alloc_resources(dev, fpgamgr_spec, sc->res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } /* Memory interface */ sc->bst_data = rman_get_bustag(sc->res[1]); sc->bsh_data = rman_get_bushandle(sc->res[1]); sc->mgr_cdev = make_dev(&fpga_cdevsw, 0, UID_ROOT, GID_WHEEL, 0600, "fpga%d", device_get_unit(sc->dev)); if (sc->mgr_cdev == NULL) { device_printf(dev, "Failed to create character device.\n"); return (ENXIO); } sc->mgr_cdev->si_drv1 = sc; return (0); } static device_method_t fpgamgr_methods[] = { DEVMETHOD(device_probe, fpgamgr_probe), DEVMETHOD(device_attach, fpgamgr_attach), { 0, 0 } }; static driver_t fpgamgr_driver = { "fpgamgr", fpgamgr_methods, sizeof(struct fpgamgr_softc), }; static devclass_t fpgamgr_devclass; DRIVER_MODULE(fpgamgr, simplebus, fpgamgr_driver, fpgamgr_devclass, 0, 0); Index: head/sys/arm/altera/socfpga/socfpga_mp.c =================================================================== --- head/sys/arm/altera/socfpga/socfpga_mp.c (revision 314388) +++ head/sys/arm/altera/socfpga/socfpga_mp.c (revision 314389) @@ -1,165 +1,202 @@ /*- - * Copyright (c) 2014 Ruslan Bukin + * Copyright (c) 2014-2017 Ruslan Bukin * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include +#include #define SCU_PHYSBASE 0xFFFEC000 +#define SCU_PHYSBASE_A10 0xFFFFC000 #define SCU_SIZE 0x100 #define SCU_CONTROL_REG 0x00 #define SCU_CONTROL_ENABLE (1 << 0) #define SCU_CONFIG_REG 0x04 #define SCU_CONFIG_REG_NCPU_MASK 0x03 #define SCU_CPUPOWER_REG 0x08 #define SCU_INV_TAGS_REG 0x0c #define SCU_DIAG_CONTROL 0x30 #define SCU_DIAG_DISABLE_MIGBIT (1 << 0) #define SCU_FILTER_START_REG 0x40 #define SCU_FILTER_END_REG 0x44 #define SCU_SECURE_ACCESS_REG 0x50 #define SCU_NONSECURE_ACCESS_REG 0x54 #define RSTMGR_PHYSBASE 0xFFD05000 #define RSTMGR_SIZE 0x100 -#define MPUMODRST 0x10 -#define MPUMODRST_CPU1 (1 << 1) #define RAM_PHYSBASE 0x0 -#define RAM_SIZE 0x1000 +#define RAM_SIZE 0x1000 +#define SOCFPGA_SOCKIT 1 +#define SOCFPGA_SOCDK 2 + extern char *mpentry_addr; static void socfpga_trampoline(void); static void socfpga_trampoline(void) { __asm __volatile( "ldr pc, 1f\n" ".globl mpentry_addr\n" "mpentry_addr:\n" "1: .space 4\n"); } void socfpga_mp_setmaxid(platform_t plat) { int hwcpu, ncpu; /* If we've already set this don't bother to do it again. */ if (mp_ncpus != 0) return; hwcpu = 2; ncpu = hwcpu; TUNABLE_INT_FETCH("hw.ncpu", &ncpu); if (ncpu < 1 || ncpu > hwcpu) ncpu = hwcpu; mp_ncpus = ncpu; mp_maxid = ncpu - 1; } -void -socfpga_mp_start_ap(platform_t plat) + +static void +_socfpga_mp_start_ap(platform_t plat, uint32_t platid) { bus_space_handle_t scu, rst, ram; int reg; - if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, - SCU_SIZE, 0, &scu) != 0) + if (platid == SOCFPGA_SOCDK) { + if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE_A10, + SCU_SIZE, 0, &scu) != 0) panic("Couldn't map the SCU\n"); + } else { + if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, + SCU_SIZE, 0, &scu) != 0) + panic("Couldn't map the SCU\n"); + } if (bus_space_map(fdtbus_bs_tag, RSTMGR_PHYSBASE, RSTMGR_SIZE, 0, &rst) != 0) panic("Couldn't map the reset manager (RSTMGR)\n"); if (bus_space_map(fdtbus_bs_tag, RAM_PHYSBASE, RAM_SIZE, 0, &ram) != 0) panic("Couldn't map the first physram page\n"); /* Invalidate SCU cache tags */ bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000ffff); /* * Erratum ARM/MP: 764369 (problems with cache maintenance). * Setting the "disable-migratory bit" in the undocumented SCU * Diagnostic Control Register helps work around the problem. */ reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL); reg |= (SCU_DIAG_DISABLE_MIGBIT); bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, reg); /* Put CPU1 to reset state */ - bus_space_write_4(fdtbus_bs_tag, rst, MPUMODRST, MPUMODRST_CPU1); + if (platid == SOCFPGA_SOCDK) { + bus_space_write_4(fdtbus_bs_tag, rst, + RSTMGR_A10_MPUMODRST, MPUMODRST_CPU1); + } else { + bus_space_write_4(fdtbus_bs_tag, rst, + RSTMGR_MPUMODRST, MPUMODRST_CPU1); + } /* Enable the SCU, then clean the cache on this core */ reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG); reg |= (SCU_CONTROL_ENABLE); bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG, reg); /* Set up trampoline code */ mpentry_addr = (char *)pmap_kextract((vm_offset_t)mpentry); bus_space_write_region_4(fdtbus_bs_tag, ram, 0, (uint32_t *)&socfpga_trampoline, 8); dcache_wbinv_poc_all(); /* Put CPU1 out from reset */ - bus_space_write_4(fdtbus_bs_tag, rst, MPUMODRST, 0); + if (platid == SOCFPGA_SOCDK) { + bus_space_write_4(fdtbus_bs_tag, rst, + RSTMGR_A10_MPUMODRST, 0); + } else { + bus_space_write_4(fdtbus_bs_tag, rst, + RSTMGR_MPUMODRST, 0); + } dsb(); sev(); bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE); bus_space_unmap(fdtbus_bs_tag, rst, RSTMGR_SIZE); bus_space_unmap(fdtbus_bs_tag, ram, RAM_SIZE); } + +void +socfpga_a10_mp_start_ap(platform_t plat) +{ + + _socfpga_mp_start_ap(plat, SOCFPGA_SOCDK); +} + +void +socfpga_mp_start_ap(platform_t plat) +{ + + _socfpga_mp_start_ap(plat, SOCFPGA_SOCKIT); +} + Index: head/sys/arm/altera/socfpga/socfpga_mp.h =================================================================== --- head/sys/arm/altera/socfpga/socfpga_mp.h (revision 314388) +++ head/sys/arm/altera/socfpga/socfpga_mp.h (revision 314389) @@ -1,34 +1,35 @@ /*- * Copyright (c) 2017 Andrew Turner * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _SOCFPGA_MP_H_ #define _SOCFPGA_MP_H_ void socfpga_mp_setmaxid(platform_t); void socfpga_mp_start_ap(platform_t); +void socfpga_a10_mp_start_ap(platform_t); #endif /* _SOCFPGA_MP_H_ */ Index: head/sys/arm/altera/socfpga/socfpga_rstmgr.c =================================================================== --- head/sys/arm/altera/socfpga/socfpga_rstmgr.c (revision 314388) +++ head/sys/arm/altera/socfpga/socfpga_rstmgr.c (revision 314389) @@ -1,257 +1,257 @@ /*- - * Copyright (c) 2014 Ruslan Bukin + * Copyright (c) 2014-2017 Ruslan Bukin * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * SOCFPGA Reset Manager. * Chapter 3, Cyclone V Device Handbook (CV-5V2 2014.07.22) */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include struct rstmgr_softc { struct resource *res[1]; bus_space_tag_t bst; bus_space_handle_t bsh; device_t dev; }; struct rstmgr_softc *rstmgr_sc; static struct resource_spec rstmgr_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { -1, 0 } }; enum { RSTMGR_SYSCTL_FPGA2HPS, RSTMGR_SYSCTL_LWHPS2FPGA, RSTMGR_SYSCTL_HPS2FPGA }; static int l3remap(struct rstmgr_softc *sc, int remap, int enable) { uint32_t paddr; bus_addr_t vaddr; phandle_t node; int reg; /* * Control whether bridge is visible to L3 masters or not. * Register is write-only. */ reg = REMAP_MPUZERO; if (enable) reg |= (remap); else reg &= ~(remap); node = OF_finddevice("l3regs"); if (node == -1) { device_printf(sc->dev, "Can't find l3regs node\n"); return (1); } if ((OF_getencprop(node, "reg", &paddr, sizeof(paddr))) > 0) { if (bus_space_map(fdtbus_bs_tag, paddr, 0x4, 0, &vaddr) == 0) { bus_space_write_4(fdtbus_bs_tag, vaddr, L3REGS_REMAP, reg); return (0); } } return (1); } static int rstmgr_sysctl(SYSCTL_HANDLER_ARGS) { struct rstmgr_softc *sc; int enable; int remap; int err; int reg; int bit; sc = arg1; switch (arg2) { case RSTMGR_SYSCTL_FPGA2HPS: bit = BRGMODRST_FPGA2HPS; remap = 0; break; case RSTMGR_SYSCTL_LWHPS2FPGA: bit = BRGMODRST_LWHPS2FPGA; remap = REMAP_LWHPS2FPGA; break; case RSTMGR_SYSCTL_HPS2FPGA: bit = BRGMODRST_HPS2FPGA; remap = REMAP_HPS2FPGA; break; default: return (1); } reg = READ4(sc, RSTMGR_BRGMODRST); enable = reg & bit ? 0 : 1; err = sysctl_handle_int(oidp, &enable, 0, req); if (err || !req->newptr) return (err); if (enable == 1) reg &= ~(bit); else if (enable == 0) reg |= (bit); else return (EINVAL); WRITE4(sc, RSTMGR_BRGMODRST, reg); l3remap(sc, remap, enable); return (0); } int -rstmgr_warmreset(void) +rstmgr_warmreset(uint32_t reg) { struct rstmgr_softc *sc; sc = rstmgr_sc; if (sc == NULL) return (1); /* Request warm reset */ - WRITE4(sc, RSTMGR_CTRL, - CTRL_SWWARMRSTREQ); + WRITE4(sc, reg, CTRL_SWWARMRSTREQ); return (0); } static int rstmgr_add_sysctl(struct rstmgr_softc *sc) { struct sysctl_oid_list *children; struct sysctl_ctx_list *ctx; ctx = device_get_sysctl_ctx(sc->dev); children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fpga2hps", CTLTYPE_UINT | CTLFLAG_RW, sc, RSTMGR_SYSCTL_FPGA2HPS, rstmgr_sysctl, "I", "Enable fpga2hps bridge"); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lwhps2fpga", CTLTYPE_UINT | CTLFLAG_RW, sc, RSTMGR_SYSCTL_LWHPS2FPGA, rstmgr_sysctl, "I", "Enable lwhps2fpga bridge"); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hps2fpga", CTLTYPE_UINT | CTLFLAG_RW, sc, RSTMGR_SYSCTL_HPS2FPGA, rstmgr_sysctl, "I", "Enable hps2fpga bridge"); return (0); } static int rstmgr_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "altr,rst-mgr")) return (ENXIO); device_set_desc(dev, "Reset Manager"); + return (BUS_PROBE_DEFAULT); } static int rstmgr_attach(device_t dev) { struct rstmgr_softc *sc; sc = device_get_softc(dev); sc->dev = dev; if (bus_alloc_resources(dev, rstmgr_spec, sc->res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } /* Memory interface */ sc->bst = rman_get_bustag(sc->res[0]); sc->bsh = rman_get_bushandle(sc->res[0]); rstmgr_sc = sc; rstmgr_add_sysctl(sc); return (0); } static device_method_t rstmgr_methods[] = { DEVMETHOD(device_probe, rstmgr_probe), DEVMETHOD(device_attach, rstmgr_attach), { 0, 0 } }; static driver_t rstmgr_driver = { "rstmgr", rstmgr_methods, sizeof(struct rstmgr_softc), }; static devclass_t rstmgr_devclass; DRIVER_MODULE(rstmgr, simplebus, rstmgr_driver, rstmgr_devclass, 0, 0); Index: head/sys/arm/altera/socfpga/socfpga_rstmgr.h =================================================================== --- head/sys/arm/altera/socfpga/socfpga_rstmgr.h (revision 314388) +++ head/sys/arm/altera/socfpga/socfpga_rstmgr.h (revision 314389) @@ -1,46 +1,50 @@ /*- * Copyright (c) 2014 Ruslan Bukin * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #define RSTMGR_STAT 0x0 /* Status */ #define RSTMGR_CTRL 0x4 /* Control */ #define CTRL_SWWARMRSTREQ (1 << 1) /* Trigger warm reset */ #define RSTMGR_COUNTS 0x8 /* Reset Cycles Count */ #define RSTMGR_MPUMODRST 0x10 /* MPU Module Reset */ +#define MPUMODRST_CPU1 (1 << 1) #define RSTMGR_PERMODRST 0x14 /* Peripheral Module Reset */ #define RSTMGR_PER2MODRST 0x18 /* Peripheral 2 Module Reset */ #define RSTMGR_BRGMODRST 0x1C /* Bridge Module Reset */ #define BRGMODRST_FPGA2HPS (1 << 2) #define BRGMODRST_LWHPS2FPGA (1 << 1) #define BRGMODRST_HPS2FPGA (1 << 0) #define RSTMGR_MISCMODRST 0x20 /* Miscellaneous Module Reset */ -int rstmgr_warmreset(void); +#define RSTMGR_A10_CTRL 0xC /* Control */ +#define RSTMGR_A10_MPUMODRST 0x20 /* MPU Module Reset */ + +int rstmgr_warmreset(uint32_t reg); Index: head/sys/arm/conf/SOCKIT.common =================================================================== --- head/sys/arm/conf/SOCKIT.common (revision 314388) +++ head/sys/arm/conf/SOCKIT.common (nonexistent) @@ -1,96 +0,0 @@ -# -# Kernel configuration for Terasic SoCKit (Altera Cyclone V SoC). -# -# For more information on this file, please read the config(5) manual page, -# and/or the handbook section on Kernel Configuration Files: -# -# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html -# -# The handbook is also available locally in /usr/share/doc/handbook -# if you've installed the doc distribution, otherwise always see the -# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the -# latest information. -# -# An exhaustive list of options and more detailed explanations of the -# device lines is also present in the ../../conf/NOTES and NOTES files. -# If you are in doubt as to the purpose or necessity of a line, check first -# in NOTES. -# -# $FreeBSD$ - -include "std.armv6" -include "../altera/socfpga/std.socfpga" - -makeoptions MODULES_OVERRIDE="" - -makeoptions WERROR="-Werror" - -options SCHED_ULE # ULE scheduler -options PLATFORM # Platform based SoC -options PLATFORM_SMP -options SMP # Enable multiple cores - -# NFS root from boopt/dhcp -#options BOOTP -#options BOOTP_NFSROOT -#options BOOTP_COMPAT -#options BOOTP_NFSV3 -#options BOOTP_WIRED_TO=ue0 - -# Interrupt controller -device gic -options INTRNG - -# ARM MPCore timer -device mpcore_timer - -# MMC/SD/SDIO Card slot support -device mmc # mmc/sd bus -device mmcsd # mmc/sd flash cards -device dwmmc - -# Pseudo devices - -device loop -device random -device pty -device md -device gpio - -# USB support -options USB_HOST_ALIGN=64 # Align usb buffers to cache line size. -device usb -#device musb -device dwcotg - -device umass -device scbus # SCSI bus (required for ATA/SCSI) -device da # Direct Access (disks) -device pass - -# Serial ports -device uart -device uart_ns8250 - -# I2C (TWSI) -device iic -device iicbus - -# SPI -device spibus - -# Ethernet -device ether -device mii -device smsc -device smscphy -device dwc -device micphy - -# USB ethernet support, requires miibus -device miibus -device axe # ASIX Electronics USB Ethernet -device bpf # Berkeley packet filter - -# Flattened Device Tree -options FDT # Configure using FDT/DTB data Property changes on: head/sys/arm/conf/SOCKIT.common ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/arm/conf/SOCDK =================================================================== --- head/sys/arm/conf/SOCDK (nonexistent) +++ head/sys/arm/conf/SOCDK (revision 314389) @@ -0,0 +1,30 @@ +# +# Kernel configuration for Altera Arria10 SOC Development Kit. +# +# For more information on this file, please read the config(5) manual page, +# and/or the handbook section on Kernel Configuration Files: +# +# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html +# +# The handbook is also available locally in /usr/share/doc/handbook +# if you've installed the doc distribution, otherwise always see the +# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the +# latest information. +# +# An exhaustive list of options and more detailed explanations of the +# device lines is also present in the ../../conf/NOTES and NOTES files. +# If you are in doubt as to the purpose or necessity of a line, check first +# in NOTES. +# +# $FreeBSD$ + +#NO_UNIVERSE + +include "SOCFPGA" +ident SOCDK + +options ROOTDEVNAME=\"ufs:/dev/mmcsd0s4\" + +# Flattened Device Tree +options FDT_DTB_STATIC +makeoptions FDT_DTS_FILE=socfpga_arria10_socdk_sdmmc.dts Property changes on: head/sys/arm/conf/SOCDK ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/conf/SOCFPGA =================================================================== --- head/sys/arm/conf/SOCFPGA (nonexistent) +++ head/sys/arm/conf/SOCFPGA (revision 314389) @@ -0,0 +1,97 @@ +# +# Kernel configuration for Altera SOCFPGA development kits. +# +# For more information on this file, please read the config(5) manual page, +# and/or the handbook section on Kernel Configuration Files: +# +# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html +# +# The handbook is also available locally in /usr/share/doc/handbook +# if you've installed the doc distribution, otherwise always see the +# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the +# latest information. +# +# An exhaustive list of options and more detailed explanations of the +# device lines is also present in the ../../conf/NOTES and NOTES files. +# If you are in doubt as to the purpose or necessity of a line, check first +# in NOTES. +# +# $FreeBSD$ + +ident SOCFPGA +include "std.armv6" +include "../altera/socfpga/std.socfpga" + +makeoptions MODULES_OVERRIDE="" + +makeoptions WERROR="-Werror" + +options SCHED_ULE # ULE scheduler +options PLATFORM # Platform based SoC +options PLATFORM_SMP +options SMP # Enable multiple cores +options MULTIDELAY + +# NFS root from boopt/dhcp +#options BOOTP +#options BOOTP_NFSROOT +#options BOOTP_COMPAT +#options BOOTP_NFSV3 +#options BOOTP_WIRED_TO=ue0 + +# Interrupt controller +device gic +options INTRNG + +# ARM MPCore timer +device mpcore_timer + +# MMC/SD/SDIO Card slot support +device mmc # mmc/sd bus +device mmcsd # mmc/sd flash cards +device dwmmc + +# Pseudo devices + +device loop +device random +device pty +device md +device gpio + +# USB support +options USB_HOST_ALIGN=64 # Align usb buffers to cache line size. +device usb +device dwcotg + +device umass +device scbus # SCSI bus (required for ATA/SCSI) +device da # Direct Access (disks) +device pass + +# Serial ports +device uart +device uart_snps + +# I2C (TWSI) +device iic +device iicbus + +# SPI +device spibus + +# Ethernet +device ether +device mii +device smsc +device smscphy +device dwc +device micphy + +# USB ethernet support, requires miibus +device miibus +device axe # ASIX Electronics USB Ethernet +device bpf # Berkeley packet filter + +# Flattened Device Tree +options FDT # Configure using FDT/DTB data Property changes on: head/sys/arm/conf/SOCFPGA ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/conf/SOCKIT =================================================================== --- head/sys/arm/conf/SOCKIT (revision 314388) +++ head/sys/arm/conf/SOCKIT (revision 314389) @@ -1,30 +1,30 @@ # # Kernel configuration for Terasic SoCKit (Altera Cyclone V SoC). # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ #NO_UNIVERSE +include "SOCFPGA" ident SOCKIT -include "SOCKIT.common" -options ROOTDEVNAME=\"ufs:/dev/da0\" +options ROOTDEVNAME=\"ufs:/dev/mmcsd0s4\" # Flattened Device Tree options FDT_DTB_STATIC -makeoptions FDT_DTS_FILE=socfpga-sockit.dts +makeoptions FDT_DTS_FILE=socfpga_cyclone5_sockit_sdmmc.dts Index: head/sys/arm/conf/SOCKIT-BERI =================================================================== --- head/sys/arm/conf/SOCKIT-BERI (revision 314388) +++ head/sys/arm/conf/SOCKIT-BERI (revision 314389) @@ -1,35 +1,37 @@ # # Kernel configuration for Terasic SoCKit (Altera Cyclone V SoC). # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ +#NO_UNIVERSE + +include "SOCFPGA" ident SOCKIT-BERI -include "SOCKIT.common" options ROOTDEVNAME=\"ufs:/dev/mmcsd0s4\" # BERI specific device beri_ring device beri_mem device beri_vtblk device vtbe device altera_pio # Flattened Device Tree options FDT_DTB_STATIC -makeoptions FDT_DTS_FILE=socfpga-sockit-beri.dts +makeoptions FDT_DTS_FILE=socfpga_cyclone5_sockit_beri_sdmmc.dts Index: head/sys/boot/fdt/dts/arm/socfpga-sockit-beri.dts =================================================================== --- head/sys/boot/fdt/dts/arm/socfpga-sockit-beri.dts (revision 314388) +++ head/sys/boot/fdt/dts/arm/socfpga-sockit-beri.dts (nonexistent) @@ -1,177 +0,0 @@ -/*- - * Copyright (c) 2014 Ruslan Bukin - * All rights reserved. - * - * This software was developed by SRI International and the University of - * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) - * ("CTSRD"), as part of the DARPA CRASH research programme. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -/dts-v1/; - -/include/ "socfpga.dtsi" - -/ { - model = "Terasic SoCKit"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - - memreserve = < 0x00000000 0x1000 >, /* SMP trampoline */ - < 0x00001000 0x1000 >, /* virtio block */ - < 0x00002000 0x1000 >; /* virtio net */ - - memory { - device_type = "memory"; - reg = < 0x00000000 0x40000000 >; /* 1G RAM */ - }; - - SOC: socfpga { - serial0: serial@ffc02000 { - status = "okay"; - }; - - usb1: usb@ffb40000 { - status = "okay"; - }; - - gmac1: ethernet@ff702000 { - status = "okay"; - - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txen-skew-ps = <0>; - txc-skew-ps = <2600>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; - }; - - mmc: dwmmc@ff704000 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - num-slots = <1>; - supports-highspeed; - broken-cd; - bus-frequency = <25000000>; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; - }; - - beri_mem0: mem@d0000000 { - compatible = "sri-cambridge,beri-mem"; - reg = <0xd0000000 0x10000000>; /* 256mb */ - status = "okay"; - }; - - pio0: pio@c0020000 { - compatible = "altr,pio"; - reg = <0xc0020000 0x1000>; /* recv */ - interrupts = < 76 >; - interrupt-parent = <&GIC>; - status = "okay"; - }; - - pio1: pio@c0021000 { - compatible = "altr,pio"; - reg = <0xc0021000 0x1000>; /* send */ - interrupts = < 82 >; /* not in use on arm side */ - interrupt-parent = <&GIC>; - status = "okay"; - }; - - pio2: pio@c0022000 { - compatible = "altr,pio"; - reg = <0xc0022000 0x1000>; /* recv */ - interrupts = < 77 >; - interrupt-parent = <&GIC>; - status = "okay"; - }; - - pio3: pio@c0023000 { - compatible = "altr,pio"; - reg = <0xc0023000 0x1000>; /* send */ - interrupts = < 83 >; /* not in use on arm side */ - interrupt-parent = <&GIC>; - status = "okay"; - }; - - beri_vtblk: vtblk@00001000 { - compatible = "sri-cambridge,beri-vtblk"; - reg = <0x00001000 0x1000>; - pio-recv = <&pio0>; - pio-send = <&pio1>; - beri-mem = <&beri_mem0>; - status = "okay"; - }; - - beri_vtnet: vtnet@00002000 { - compatible = "sri-cambridge,beri-vtnet"; - reg = <0x00002000 0x1000>; - pio-recv = <&pio2>; - pio-send = <&pio3>; - beri-mem = <&beri_mem0>; - status = "okay"; - }; - - beri_debug: ring@c0000000 { - compatible = "sri-cambridge,beri-ring"; - reg = <0xc0000000 0x3000>; - interrupts = < 72 73 >; - interrupt-parent = <&GIC>; - device_name = "beri_debug"; - data_size = <0x1000>; - data_read = <0x0>; - data_write = <0x1000>; - control_read = <0x2000>; - control_write = <0x2010>; - status = "okay"; - }; - - beri_console: ring@c0004000 { - compatible = "sri-cambridge,beri-ring"; - reg = <0xc0004000 0x3000>; - interrupts = < 74 75 >; - interrupt-parent = <&GIC>; - device_name = "beri_console"; - data_size = <0x1000>; - data_read = <0x0>; - data_write = <0x1000>; - control_read = <0x2000>; - control_write = <0x2010>; - status = "okay"; - }; - }; - - chosen { - bootargs = "-v"; - stdin = "serial0"; - stdout = "serial0"; - }; -}; Property changes on: head/sys/boot/fdt/dts/arm/socfpga-sockit-beri.dts ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/boot/fdt/dts/arm/socfpga-sockit.dts =================================================================== --- head/sys/boot/fdt/dts/arm/socfpga-sockit.dts (revision 314388) +++ head/sys/boot/fdt/dts/arm/socfpga-sockit.dts (nonexistent) @@ -1,90 +0,0 @@ -/*- - * Copyright (c) 2014 Ruslan Bukin - * All rights reserved. - * - * This software was developed by SRI International and the University of - * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) - * ("CTSRD"), as part of the DARPA CRASH research programme. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -/dts-v1/; - -/include/ "socfpga.dtsi" - -/ { - model = "Terasic SoCKit"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - - /* Reserve first page for secondary CPU trampoline code */ - memreserve = < 0x00000000 0x1000 >; - - memory { - device_type = "memory"; - reg = < 0x00000000 0x40000000 >; /* 1G RAM */ - }; - - SOC: socfpga { - serial0: serial@ffc02000 { - status = "okay"; - }; - - usb1: usb@ffb40000 { - status = "okay"; - }; - - gmac1: ethernet@ff702000 { - status = "okay"; - - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txen-skew-ps = <0>; - txc-skew-ps = <2600>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; - }; - - mmc: dwmmc@ff704000 { - status = "okay"; - num-slots = <1>; - supports-highspeed; - broken-cd; - bus-frequency = <25000000>; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; - }; - }; - - chosen { - bootargs = "-v"; - stdin = "serial0"; - stdout = "serial0"; - }; -}; Property changes on: head/sys/boot/fdt/dts/arm/socfpga-sockit.dts ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/boot/fdt/dts/arm/socfpga.dtsi =================================================================== --- head/sys/boot/fdt/dts/arm/socfpga.dtsi (revision 314388) +++ head/sys/boot/fdt/dts/arm/socfpga.dtsi (nonexistent) @@ -1,200 +0,0 @@ -/*- - * Copyright (c) 2014 Ruslan Bukin - * All rights reserved. - * - * This software was developed by SRI International and the University of - * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) - * ("CTSRD"), as part of the DARPA CRASH research programme. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -/ { - compatible = "altr,socfpga"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&GIC>; - - aliases { - soc = &SOC; - rstmgr = &rstmgr; - l3regs = &l3regs; - serial0 = &serial0; - serial1 = &serial1; - }; - - SOC: socfpga { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - bus-frequency = <0>; - - GIC: interrupt-controller@fffed000 { - compatible = "arm,gic"; - reg = < 0xfffed000 0x1000 >, /* Distributor */ - < 0xfffec100 0x100 >; /* CPU Interface */ - interrupt-controller; - #interrupt-cells = <1>; - }; - - mp_tmr@40002100 { - compatible = "arm,mpcore-timers"; - clock-frequency = <200000000>; - #address-cells = <1>; - #size-cells = <0>; - reg = < 0xfffec200 0x100 >, /* Global Timer */ - < 0xfffec600 0x100 >; /* Private Timer */ - interrupts = < 27 29 >; - interrupt-parent = < &GIC >; - }; - - sysmgr: sysmgr@ffd08000 { - compatible = "altr,sys-mgr"; - reg = <0xffd08000 0x1000>; - }; - - clkmgr: clkmgr@ffd04000 { - compatible = "altr,clk-mgr"; - reg = <0xffd04000 0x1000>; - }; - - rstmgr: rstmgr@ffd05000 { - compatible = "altr,rst-mgr"; - reg = <0xffd05000 0x1000>; - }; - - l3regs: l3regs@ff800000 { - compatible = "altr,l3regs"; - reg = <0xff800000 0x1000>; - }; - - fpgamgr: fpgamgr@ff706000 { - compatible = "altr,fpga-mgr"; - reg = <0xff706000 0x1000>, /* FPGAMGRREGS */ - <0xffb90000 0x1000>; /* FPGAMGRDATA */ - interrupts = < 207 >; - interrupt-parent = <&GIC>; - }; - - gpio0: gpio@ff708000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff708000 0x1000>; - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - snps,nr-gpios = <29>; - }; - }; - - gpio1: gpio@ff709000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff709000 0x1000>; - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - snps,nr-gpios = <29>; - }; - }; - - gpio2: gpio@ff70a000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff70a000 0x1000>; - portc: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - snps,nr-gpios = <27>; - }; - }; - - serial0: serial@ffc02000 { - compatible = "ns16550"; - reg = <0xffc02000 0x1000>; - reg-shift = <2>; - interrupts = <194>; - interrupt-parent = <&GIC>; - current-speed = <115200>; - clock-frequency = < 100000000 >; - status = "disabled"; - }; - - serial1: serial@ffc03000 { - compatible = "ns16550"; - reg = <0xffc03000 0x1000>; - reg-shift = <2>; - interrupts = <195>; - interrupt-parent = <&GIC>; - current-speed = <115200>; - clock-frequency = < 100000000 >; - status = "disabled"; - }; - - usb0: usb@ffb00000 { - compatible = "synopsys,designware-hs-otg2"; - reg = <0xffb00000 0xffff>; - interrupts = <157>; - interrupt-parent = <&GIC>; - status = "disabled"; - }; - - usb1: usb@ffb40000 { - compatible = "synopsys,designware-hs-otg2"; - reg = <0xffb40000 0xffff>; - interrupts = <160>; - interrupt-parent = <&GIC>; - dr_mode = "host"; - status = "disabled"; - }; - - gmac0: ethernet@ff700000 { - compatible = "altr,socfpga-stmmac", - "snps,dwmac-3.70a", "snps,dwmac"; - reg = <0xff700000 0x2000>; - interrupts = <147>; - interrupt-parent = <&GIC>; - phy-mode = "rgmii"; - status = "disabled"; - }; - - gmac1: ethernet@ff702000 { - compatible = "altr,socfpga-stmmac", - "snps,dwmac-3.70a", "snps,dwmac"; - reg = <0xff702000 0x2000>; - interrupts = <152>; - interrupt-parent = <&GIC>; - phy-mode = "rgmii"; - status = "disabled"; - }; - - mmc: dwmmc@ff704000 { - compatible = "altr,socfpga-dw-mshc"; - reg = <0xff704000 0x1000>; - interrupts = <171>; - interrupt-parent = <&GIC>; - fifo-depth = <0x400>; - status = "disabled"; - }; - }; -}; Property changes on: head/sys/boot/fdt/dts/arm/socfpga.dtsi ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/boot/fdt/dts/arm/socfpga_arria10_socdk_sdmmc.dts =================================================================== --- head/sys/boot/fdt/dts/arm/socfpga_arria10_socdk_sdmmc.dts (nonexistent) +++ head/sys/boot/fdt/dts/arm/socfpga_arria10_socdk_sdmmc.dts (revision 314389) @@ -0,0 +1,82 @@ +/*- + * Copyright (c) 2017 Ruslan Bukin + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 + * ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/dts-v1/; +#include "socfpga_arria10_socdk.dtsi" + +/ { + model = "Altera SOCFPGA Arria 10"; + compatible = "altr,socfpga-arria10", "altr,socfpga"; + + /* Reserve first page for secondary CPU trampoline code */ + memreserve = < 0x00000000 0x1000 >; + + soc { + /* Local timer */ + timer@ffffc600 { + clock-frequency = <200000000>; + }; + + /* Global timer */ + global_timer: timer@ffffc200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xffffc200 0x20>; + interrupts = <1 11 0x301>; + clock-frequency = <200000000>; + }; + }; + + chosen { + stdin = "serial1"; + stdout = "serial1"; + }; +}; + +&uart1 { + clock-frequency = < 50000000 >; +}; + +&mmc { + status = "okay"; + num-slots = <1>; + cap-sd-highspeed; + broken-cd; + bus-width = <4>; + bus-frequency = <200000000>; +}; + +&i2c1 { + lcd@28 { + compatible = "newhaven,nhd-0216k3z-nsw-bbw"; + reg = <0x28>; + }; +}; Property changes on: head/sys/boot/fdt/dts/arm/socfpga_arria10_socdk_sdmmc.dts ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/boot/fdt/dts/arm/socfpga_cyclone5_sockit_beri_sdmmc.dts =================================================================== --- head/sys/boot/fdt/dts/arm/socfpga_cyclone5_sockit_beri_sdmmc.dts (nonexistent) +++ head/sys/boot/fdt/dts/arm/socfpga_cyclone5_sockit_beri_sdmmc.dts (revision 314389) @@ -0,0 +1,153 @@ +/*- + * Copyright (c) 2017 Ruslan Bukin + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 + * ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* /dts-v1/; */ +#include "socfpga_cyclone5_sockit.dts" + +/ { + model = "Terasic SoCkit"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + memreserve = < 0x00000000 0x1000 >, /* SMP trampoline */ + < 0x00001000 0x1000 >, /* virtio block */ + < 0x00002000 0x1000 >; /* virtio net */ + + soc { + /* Local timer */ + timer@fffec600 { + clock-frequency = <200000000>; + }; + + /* Global timer */ + global_timer: timer@fffec200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xfffec200 0x20>; + interrupts = <1 11 0xf04>; + clock-frequency = <200000000>; + }; + + beri_mem0: mem@d0000000 { + compatible = "sri-cambridge,beri-mem"; + reg = <0xd0000000 0x10000000>; /* 256mb */ + status = "okay"; + }; + + pio0: pio@c0020000 { + compatible = "altr,pio"; + reg = <0xc0020000 0x1000>; /* recv */ + interrupts = < 76 >; + status = "okay"; + }; + + pio1: pio@c0021000 { + compatible = "altr,pio"; + reg = <0xc0021000 0x1000>; /* send */ + interrupts = < 82 >; /* not in use on arm side */ + status = "okay"; + }; + + pio2: pio@c0022000 { + compatible = "altr,pio"; + reg = <0xc0022000 0x1000>; /* recv */ + interrupts = < 77 >; + status = "okay"; + }; + + pio3: pio@c0023000 { + compatible = "altr,pio"; + reg = <0xc0023000 0x1000>; /* send */ + interrupts = < 83 >; /* not in use on arm side */ + status = "okay"; + }; + + beri_vtblk: vtblk@00001000 { + compatible = "sri-cambridge,beri-vtblk"; + reg = <0x00001000 0x1000>; + pio-recv = <&pio0>; + pio-send = <&pio1>; + beri-mem = <&beri_mem0>; + status = "okay"; + }; + + beri_vtnet: vtnet@00002000 { + compatible = "sri-cambridge,beri-vtnet"; + reg = <0x00002000 0x1000>; + pio-recv = <&pio2>; + pio-send = <&pio3>; + beri-mem = <&beri_mem0>; + status = "okay"; + }; + + beri_debug: ring@c0000000 { + compatible = "sri-cambridge,beri-ring"; + reg = <0xc0000000 0x3000>; + interrupts = < 72 73 >; + device_name = "beri_debug"; + data_size = <0x1000>; + data_read = <0x0>; + data_write = <0x1000>; + control_read = <0x2000>; + control_write = <0x2010>; + status = "okay"; + }; + + beri_console: ring@c0004000 { + compatible = "sri-cambridge,beri-ring"; + reg = <0xc0004000 0x3000>; + interrupts = < 74 75 >; + device_name = "beri_console"; + data_size = <0x1000>; + data_read = <0x0>; + data_write = <0x1000>; + control_read = <0x2000>; + control_write = <0x2010>; + status = "okay"; + }; + }; + + chosen { + stdin = "serial0"; + stdout = "serial0"; + }; +}; + +&mmc0 { + bus-frequency = <25000000>; +}; + +&uart0 { + clock-frequency = <100000000>; +}; + +&uart1 { + status = "disabled"; +}; Property changes on: head/sys/boot/fdt/dts/arm/socfpga_cyclone5_sockit_beri_sdmmc.dts ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/boot/fdt/dts/arm/socfpga_cyclone5_sockit_sdmmc.dts =================================================================== --- head/sys/boot/fdt/dts/arm/socfpga_cyclone5_sockit_sdmmc.dts (nonexistent) +++ head/sys/boot/fdt/dts/arm/socfpga_cyclone5_sockit_sdmmc.dts (revision 314389) @@ -0,0 +1,74 @@ +/*- + * Copyright (c) 2017 Ruslan Bukin + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 + * ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* /dts-v1/; */ +#include "socfpga_cyclone5_sockit.dts" + +/ { + model = "Terasic SoCkit"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + /* Reserve first page for secondary CPU trampoline code */ + memreserve = < 0x00000000 0x1000 >; + + soc { + /* Local timer */ + timer@fffec600 { + clock-frequency = <200000000>; + }; + + /* Global timer */ + global_timer: timer@fffec200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xfffec200 0x20>; + interrupts = <1 11 0xf04>; + clock-frequency = <200000000>; + }; + }; + + chosen { + stdin = "serial0"; + stdout = "serial0"; + }; +}; + +&mmc0 { + bus-frequency = <25000000>; +}; + +&uart0 { + clock-frequency = <100000000>; +}; + +&uart1 { + status = "disabled"; +}; Property changes on: head/sys/boot/fdt/dts/arm/socfpga_cyclone5_sockit_sdmmc.dts ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property