Index: head/sys/arm64/conf/GENERIC =================================================================== --- head/sys/arm64/conf/GENERIC (revision 313767) +++ head/sys/arm64/conf/GENERIC (revision 313768) @@ -1,236 +1,237 @@ # # GENERIC -- Generic kernel configuration file for FreeBSD/arm64 # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ cpu ARM64 ident GENERIC makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols makeoptions WITH_CTF=1 # Run ctfconvert(1) for DTrace support options SCHED_ULE # ULE scheduler options PREEMPTION # Enable kernel thread preemption options INET # InterNETworking options INET6 # IPv6 communications protocols options IPSEC # IP (v4/v6) security options TCP_HHOOK # hhook(9) framework for TCP options TCP_OFFLOAD # TCP offload options SCTP # Stream Control Transmission Protocol options FFS # Berkeley Fast Filesystem options SOFTUPDATES # Enable FFS soft updates support options UFS_ACL # Support for access control lists options UFS_DIRHASH # Improve performance on big directories options UFS_GJOURNAL # Enable gjournal-based UFS journaling options QUOTA # Enable disk quotas for UFS options MD_ROOT # MD is a potential root device options NFSCL # Network Filesystem Client options NFSD # Network Filesystem Server options NFSLOCKD # Network Lock Manager options NFS_ROOT # NFS usable as /, requires NFSCL options MSDOSFS # MSDOS Filesystem options CD9660 # ISO 9660 Filesystem options PROCFS # Process filesystem (requires PSEUDOFS) options PSEUDOFS # Pseudo-filesystem framework options GEOM_PART_GPT # GUID Partition Tables. options GEOM_RAID # Soft RAID functionality. options GEOM_LABEL # Provides labelization options SCSI_DELAY=5000 # Delay (in ms) before probing SCSI options KTRACE # ktrace(1) support options STACK # stack(9) support options SYSVSHM # SYSV-style shared memory options SYSVMSG # SYSV-style message queues options SYSVSEM # SYSV-style semaphores options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions options PRINTF_BUFR_SIZE=128 # Prevent printf output being interspersed. options KBD_INSTALL_CDEV # install a CDEV entry in /dev options HWPMC_HOOKS # Necessary kernel hooks for hwpmc(4) options AUDIT # Security event auditing options CAPABILITY_MODE # Capsicum capability mode options CAPABILITIES # Capsicum capabilities options MAC # TrustedBSD MAC Framework options KDTRACE_FRAME # Ensure frames are compiled in options KDTRACE_HOOKS # Kernel DTrace hooks options VFP # Floating-point support options RACCT # Resource accounting framework options RACCT_DEFAULT_TO_DISABLED # Set kern.racct.enable=0 by default options RCTL # Resource limits options SMP options INTRNG # Debugging support. Always need this: options KDB # Enable kernel debugger support. options KDB_TRACE # Print a stack trace for a panic. # For full debugger support use (turn off in stable branch): options DDB # Support DDB. #options GDB # Support remote GDB. options DEADLKRES # Enable the deadlock resolver options INVARIANTS # Enable calls of extra sanity checking options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS options WITNESS # Enable checks to detect deadlocks and cycles options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed options MALLOC_DEBUG_MAXZONES=8 # Separate malloc(9) zones # SoC support options SOC_ALLWINNER_A64 options SOC_CAVM_THUNDERX options SOC_HISI_HI6220 options SOC_BRCM_BCM2837 # Annapurna Alpine drivers device al_ccu # Alpine Cache Coherency Unit device al_nb_service # Alpine North Bridge Service device al_iofic # I/O Fabric Interrupt Controller device al_serdes # Serializer/Deserializer device al_udma # Universal DMA # VirtIO support device virtio device virtio_pci device virtio_mmio device virtio_blk device vtnet # CPU frequency control device cpufreq # Bus drivers device pci device al_pci # Annapurna Alpine PCI-E options PCI_HP # PCI-Express native HotPlug options PCI_IOV # PCI SR-IOV support # Ethernet NICs device mii device miibus # MII bus support device awg # Allwinner EMAC Gigabit Ethernet +device axgbe # AMD Opteron A1100 integrated NIC device em # Intel PRO/1000 Gigabit Ethernet Family device ix # Intel 10Gb Ethernet Family device msk # Marvell/SysKonnect Yukon II Gigabit Ethernet device smc # SMSC LAN91C111 device vnic # Cavium ThunderX NIC device al_eth # Annapurna Alpine Ethernet NIC # Block devices device ahci device scbus device da # ATA/SCSI peripherals device pass # Passthrough device (direct ATA/SCSI access) # MMC/SD/SDIO Card slot support device sdhci device aw_mmc # Allwinner SD/MMC controller device mmc # mmc/sd bus device mmcsd # mmc/sd flash cards device dwmmc # Serial (COM) ports device uart # Generic UART driver device uart_ns8250 # ns8250-type UART driver device uart_snps device pl011 # USB support options USB_DEBUG # enable debug msgs device aw_ehci # Allwinner EHCI USB interface (USB 2.0) device aw_usbphy # Allwinner USB PHY device dwcotg # DWC OTG controller device ohci # OHCI USB interface device ehci # EHCI USB interface (USB 2.0) device xhci # XHCI PCI->USB interface (USB 3.0) device usb # USB Bus (required) device ukbd # Keyboard device umass # Disks/Mass storage - Requires scbus and da # USB ethernet support device smcphy device smsc # GPIO device aw_gpio # Allwinner GPIO controller device gpio device gpioled device fdt_pinctrl # I2C device aw_rsb # Allwinner Reduced Serial Bus device bcm2835_bsc # Broadcom BCM283x I2C bus device iicbus # Clock and reset controllers device aw_ccu # Allwinner clock controller # Interrupt controllers device aw_nmi # Allwinner NMI support # Real-time clock support device aw_rtc # Allwinner Real-time Clock # Watchdog controllers device aw_wdog # Allwinner Watchdog # Power management controllers device axp81x # X-Powers AXP81x PMIC # EFUSE device aw_sid # Allwinner Secure ID EFUSE # Thermal sensors device aw_thermal # Allwinner Thermal Sensor Controller # SPI device spibus device bcm2835_spi # Broadcom BCM283x SPI bus # Console device vt device kbdmux # Pseudo devices. device loop # Network loopback device random # Entropy device device ether # Ethernet support device vlan # 802.1Q VLAN support device tun # Packet tunnel. device md # Memory "disks" device gif # IPv6 and IPv4 tunneling device firmware # firmware assist module device psci # Support for ARM PSCI # EXT_RESOURCES pseudo devices options EXT_RESOURCES device clk device phy device hwreset device regulator # The `bpf' device enables the Berkeley Packet Filter. # Be aware of the administrative consequences of enabling this! # Note that 'bpf' is required for DHCP. device bpf # Berkeley packet filter # Chip-specific errata options THUNDERX_PASS_1_1_ERRATA options FDT device acpi # The crypto framework is required by IPSEC device crypto # Required by IPSEC Index: head/sys/conf/files.arm64 =================================================================== --- head/sys/conf/files.arm64 (revision 313767) +++ head/sys/conf/files.arm64 (revision 313768) @@ -1,192 +1,197 @@ # $FreeBSD$ cloudabi64_vdso.o optional compat_cloudabi64 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_aarch64.S" \ compile-with "${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_aarch64.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi64_vdso.o" # cloudabi64_vdso_blob.o optional compat_cloudabi64 \ dependency "cloudabi64_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi64_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi64_vdso_blob.o" # arm/allwinner/a10_ehci.c optional ehci aw_ehci fdt arm/allwinner/a10_gpio.c optional gpio aw_gpio fdt arm/allwinner/a10_mmc.c optional mmc aw_mmc fdt arm/allwinner/a64/a64_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/a64/a64_r_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/aw_ccu.c optional aw_ccu fdt arm/allwinner/aw_nmi.c optional aw_nmi fdt \ compile-with "${NORMAL_C} -I$S/gnu/dts/include" arm/allwinner/aw_reset.c optional aw_ccu fdt arm/allwinner/aw_rsb.c optional aw_rsb fdt arm/allwinner/aw_rtc.c optional aw_rtc fdt arm/allwinner/aw_sid.c optional aw_sid fdt arm/allwinner/aw_thermal.c optional aw_thermal fdt arm/allwinner/aw_usbphy.c optional ehci aw_usbphy fdt arm/allwinner/aw_wdog.c optional aw_wdog fdt arm/allwinner/axp81x.c optional axp81x fdt arm/allwinner/clk/aw_ahbclk.c optional aw_ccu fdt arm/allwinner/clk/aw_apbclk.c optional aw_ccu fdt arm/allwinner/clk/aw_axiclk.c optional aw_ccu fdt arm/allwinner/clk/aw_cpuclk.c optional aw_ccu fdt arm/allwinner/clk/aw_gate.c optional aw_ccu fdt arm/allwinner/clk/aw_modclk.c optional aw_ccu fdt arm/allwinner/clk/aw_pll.c optional aw_ccu fdt \ compile-with "${NORMAL_C} -I$S/gnu/dts/include" arm/allwinner/clk/aw_thsclk.c optional aw_ccu fdt arm/allwinner/clk/aw_usbclk.c optional aw_ccu fdt arm/allwinner/if_awg.c optional awg fdt arm/annapurna/alpine/alpine_ccu.c optional al_ccu fdt arm/annapurna/alpine/alpine_nb_service.c optional al_nb_service fdt arm/annapurna/alpine/alpine_pci.c optional al_pci fdt arm/annapurna/alpine/alpine_pci_msix.c optional al_pci fdt arm/annapurna/alpine/alpine_serdes.c optional al_serdes fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" arm/arm/generic_timer.c standard arm/arm/gic.c standard arm/arm/gic_fdt.c optional fdt arm/arm/pmu.c standard arm/broadcom/bcm2835/bcm2835_audio.c optional sound vchiq fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_cpufreq.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_dma.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_fbd.c optional vt soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_ft5406.c optional evdev bcm2835_ft5406 soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_intr.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_mbox.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_rng.c optional random soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_sdhci.c optional sdhci soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_vcio.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_wdog.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837 arm64/acpica/acpi_machdep.c optional acpi arm64/acpica/OsdEnvironment.c optional acpi arm64/acpica/acpi_wakeup.c optional acpi arm64/acpica/pci_cfgreg.c optional acpi pci arm64/arm64/autoconf.c standard arm64/arm64/bus_machdep.c standard arm64/arm64/bus_space_asm.S standard arm64/arm64/busdma_bounce.c standard arm64/arm64/busdma_machdep.c standard arm64/arm64/bzero.S standard arm64/arm64/clock.c standard arm64/arm64/copyinout.S standard arm64/arm64/copystr.c standard arm64/arm64/cpufunc_asm.S standard arm64/arm64/db_disasm.c optional ddb arm64/arm64/db_interface.c optional ddb arm64/arm64/db_trace.c optional ddb arm64/arm64/debug_monitor.c optional ddb arm64/arm64/disassem.c optional ddb arm64/arm64/dump_machdep.c standard arm64/arm64/elf_machdep.c standard arm64/arm64/exception.S standard arm64/arm64/gicv3_its.c optional intrng fdt arm64/arm64/gic_v3.c standard arm64/arm64/gic_v3_fdt.c optional fdt arm64/arm64/identcpu.c standard arm64/arm64/in_cksum.c optional inet | inet6 arm64/arm64/locore.S standard no-obj arm64/arm64/machdep.c standard arm64/arm64/mem.c standard arm64/arm64/memcpy.S standard arm64/arm64/memmove.S standard arm64/arm64/minidump_machdep.c standard arm64/arm64/mp_machdep.c optional smp arm64/arm64/nexus.c standard arm64/arm64/ofw_machdep.c optional fdt arm64/arm64/pmap.c standard arm64/arm64/stack_machdep.c optional ddb | stack arm64/arm64/support.S standard arm64/arm64/swtch.S standard arm64/arm64/sys_machdep.c standard arm64/arm64/trap.c standard arm64/arm64/uio_machdep.c standard arm64/arm64/uma_machdep.c standard arm64/arm64/unwind.c optional ddb | kdtrace_hooks | stack arm64/arm64/vfp.c standard arm64/arm64/vm_machdep.c standard arm64/cavium/thunder_pcie_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_pem.c optional soc_cavm_thunderx pci arm64/cavium/thunder_pcie_pem_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_common.c optional soc_cavm_thunderx pci arm64/cloudabi64/cloudabi64_sysvec.c optional compat_cloudabi64 contrib/vchiq/interface/compat/vchi_bsd.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_connected.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_core.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_shim.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_util.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" crypto/armv8/armv8_crypto.c optional armv8crypto armv8_crypto_wrap.o optional armv8crypto \ dependency "$S/crypto/armv8/armv8_crypto_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} ${WERROR} ${NO_WCAST_QUAL} ${PROF} -march=armv8a+crypto ${.IMPSRC}" \ no-implicit-rule \ clean "armv8_crypto_wrap.o" crypto/blowfish/bf_enc.c optional crypto | ipsec | ipsec_support crypto/des/des_enc.c optional crypto | ipsec | ipsec_support | netsmb dev/acpica/acpi_if.m optional acpi dev/ahci/ahci_generic.c optional ahci +dev/axgbe/if_axgbe.c optional axgbe +dev/axgbe/xgbe-desc.c optional axgbe +dev/axgbe/xgbe-dev.c optional axgbe +dev/axgbe/xgbe-drv.c optional axgbe +dev/axgbe/xgbe-mdio.c optional axgbe dev/cpufreq/cpufreq_dt.c optional cpufreq fdt dev/hwpmc/hwpmc_arm64.c optional hwpmc dev/hwpmc/hwpmc_arm64_md.c optional hwpmc dev/mbox/mbox_if.m optional soc_brcm_bcm2837 dev/mmc/host/dwmmc.c optional dwmmc fdt dev/mmc/host/dwmmc_hisi.c optional dwmmc fdt soc_hisi_hi6220 dev/ofw/ofw_cpu.c optional fdt dev/ofw/ofwpci.c optional fdt pci dev/pci/pci_host_generic.c optional pci dev/pci/pci_host_generic_fdt.c optional pci fdt dev/psci/psci.c optional psci dev/psci/psci_arm64.S optional psci dev/uart/uart_cpu_arm64.c optional uart dev/uart/uart_dev_pl011.c optional uart pl011 dev/usb/controller/dwc_otg_hisi.c optional dwcotg fdt soc_hisi_hi6220 dev/usb/controller/generic_ehci.c optional ehci acpi dev/usb/controller/generic_ohci.c optional ohci fdt dev/usb/controller/generic_usb_if.m optional ohci fdt dev/vnic/mrml_bridge.c optional vnic fdt dev/vnic/nic_main.c optional vnic pci dev/vnic/nicvf_main.c optional vnic pci pci_iov dev/vnic/nicvf_queues.c optional vnic pci pci_iov dev/vnic/thunder_bgx_fdt.c optional vnic fdt dev/vnic/thunder_bgx.c optional vnic pci dev/vnic/thunder_mdio_fdt.c optional vnic fdt dev/vnic/thunder_mdio.c optional vnic dev/vnic/lmac_if.m optional inet | inet6 | vnic kern/kern_clocksource.c standard kern/msi_if.m optional intrng kern/pic_if.m optional intrng kern/subr_devmap.c standard kern/subr_intr.c optional intrng libkern/bcmp.c standard libkern/ffs.c standard libkern/ffsl.c standard libkern/ffsll.c standard libkern/fls.c standard libkern/flsl.c standard libkern/flsll.c standard libkern/memset.c standard cddl/contrib/opensolaris/common/atomic/aarch64/opensolaris_atomic.S optional zfs | dtrace compile-with "${CDDL_C}" cddl/dev/dtrace/aarch64/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/aarch64/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" Index: head/sys/dev/axgbe/if_axgbe.c =================================================================== --- head/sys/dev/axgbe/if_axgbe.c (nonexistent) +++ head/sys/dev/axgbe/if_axgbe.c (revision 313768) @@ -0,0 +1,619 @@ +/*- + * Copyright (c) 2016,2017 SoftIron Inc. + * All rights reserved. + * + * This software was developed by Andrew Turner under + * the sponsorship of SoftIron Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "miibus_if.h" + +#include "xgbe.h" +#include "xgbe-common.h" + +static device_probe_t axgbe_probe; +static device_attach_t axgbe_attach; + +struct axgbe_softc { + /* Must be first */ + struct xgbe_prv_data prv; + + uint8_t mac_addr[ETHER_ADDR_LEN]; + struct ifmedia media; +}; + +static struct ofw_compat_data compat_data[] = { + { "amd,xgbe-seattle-v1a", true }, + { NULL, false } +}; + +static struct resource_spec old_phy_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Rx/Tx regs */ + { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* Integration regs */ + { SYS_RES_MEMORY, 2, RF_ACTIVE }, /* Integration regs */ + { SYS_RES_IRQ, 0, RF_ACTIVE }, /* Interrupt */ + { -1, 0 } +}; + +static struct resource_spec old_mac_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* MAC regs */ + { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* PCS regs */ + { SYS_RES_IRQ, 0, RF_ACTIVE }, /* Device interrupt */ + /* Per-channel interrupts */ + { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL }, + { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL }, + { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL }, + { SYS_RES_IRQ, 4, RF_ACTIVE | RF_OPTIONAL }, + { -1, 0 } +}; + +static struct resource_spec mac_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* MAC regs */ + { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* PCS regs */ + { SYS_RES_MEMORY, 2, RF_ACTIVE }, /* Rx/Tx regs */ + { SYS_RES_MEMORY, 3, RF_ACTIVE }, /* Integration regs */ + { SYS_RES_MEMORY, 4, RF_ACTIVE }, /* Integration regs */ + { SYS_RES_IRQ, 0, RF_ACTIVE }, /* Device interrupt */ + /* Per-channel and auto-negotiation interrupts */ + { SYS_RES_IRQ, 1, RF_ACTIVE }, + { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL }, + { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL }, + { SYS_RES_IRQ, 4, RF_ACTIVE | RF_OPTIONAL }, + { SYS_RES_IRQ, 5, RF_ACTIVE | RF_OPTIONAL }, + { -1, 0 } +}; + +MALLOC_DEFINE(M_AXGBE, "axgbe", "axgbe data"); + +static void +axgbe_init(void *p) +{ + struct axgbe_softc *sc; + struct ifnet *ifp; + + sc = p; + ifp = sc->prv.netdev; + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + return; + + ifp->if_drv_flags |= IFF_DRV_RUNNING; +} + +static int +axgbe_ioctl(struct ifnet *ifp, unsigned long command, caddr_t data) +{ + struct axgbe_softc *sc = ifp->if_softc; + struct ifreq *ifr = (struct ifreq *)data; + int error; + + switch(command) { + case SIOCSIFMTU: + if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) + error = EINVAL; + else + error = xgbe_change_mtu(ifp, ifr->ifr_mtu); + break; + case SIOCSIFFLAGS: + error = 0; + break; + case SIOCSIFMEDIA: + case SIOCGIFMEDIA: + error = ifmedia_ioctl(ifp, ifr, &sc->media, command); + break; + default: + error = ether_ioctl(ifp, command, data); + break; + } + + return (error); +} + +static void +axgbe_qflush(struct ifnet *ifp) +{ + + if_qflush(ifp); +} + +static int +axgbe_media_change(struct ifnet *ifp) +{ + struct axgbe_softc *sc; + int cur_media; + + sc = ifp->if_softc; + + sx_xlock(&sc->prv.an_mutex); + cur_media = sc->media.ifm_cur->ifm_media; + + switch (IFM_SUBTYPE(cur_media)) { + case IFM_10G_KR: + sc->prv.phy.speed = SPEED_10000; + sc->prv.phy.autoneg = AUTONEG_DISABLE; + break; + case IFM_2500_KX: + sc->prv.phy.speed = SPEED_2500; + sc->prv.phy.autoneg = AUTONEG_DISABLE; + break; + case IFM_1000_KX: + sc->prv.phy.speed = SPEED_1000; + sc->prv.phy.autoneg = AUTONEG_DISABLE; + break; + case IFM_AUTO: + sc->prv.phy.autoneg = AUTONEG_ENABLE; + break; + } + sx_xunlock(&sc->prv.an_mutex); + + return (-sc->prv.phy_if.phy_config_aneg(&sc->prv)); +} + +static void +axgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) +{ + struct axgbe_softc *sc; + + sc = ifp->if_softc; + + ifmr->ifm_status = IFM_AVALID; + if (!sc->prv.phy.link) + return; + + ifmr->ifm_status |= IFM_ACTIVE; + ifmr->ifm_active = IFM_ETHER; + + if (sc->prv.phy.duplex == DUPLEX_FULL) + ifmr->ifm_active |= IFM_FDX; + else + ifmr->ifm_active |= IFM_HDX; + + switch (sc->prv.phy.speed) { + case SPEED_10000: + ifmr->ifm_active |= IFM_10G_KR; + break; + case SPEED_2500: + ifmr->ifm_active |= IFM_2500_KX; + break; + case SPEED_1000: + ifmr->ifm_active |= IFM_1000_KX; + break; + } +} + +static uint64_t +axgbe_get_counter(struct ifnet *ifp, ift_counter c) +{ + struct xgbe_prv_data *pdata = ifp->if_softc; + struct xgbe_mmc_stats *pstats = &pdata->mmc_stats; + + DBGPR("-->%s\n", __func__); + + pdata->hw_if.read_mmc_stats(pdata); + + switch(c) { + case IFCOUNTER_IPACKETS: + return (pstats->rxframecount_gb); + case IFCOUNTER_IERRORS: + return (pstats->rxframecount_gb - + pstats->rxbroadcastframes_g - + pstats->rxmulticastframes_g - + pstats->rxunicastframes_g); + case IFCOUNTER_OPACKETS: + return (pstats->txframecount_gb); + case IFCOUNTER_OERRORS: + return (pstats->txframecount_gb - pstats->txframecount_g); + case IFCOUNTER_IBYTES: + return (pstats->rxoctetcount_gb); + case IFCOUNTER_OBYTES: + return (pstats->txoctetcount_gb); + default: + return (if_get_counter_default(ifp, c)); + } +} + +static int +axgbe_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) + return (ENXIO); + + device_set_desc(dev, "AMD 10 Gigabit Ethernet"); + return (BUS_PROBE_DEFAULT); +} + +static int +axgbe_get_optional_prop(device_t dev, phandle_t node, const char *name, + int *data, size_t len) +{ + + if (!OF_hasprop(node, name)) + return (-1); + + if (OF_getencprop(node, name, data, len) <= 0) { + device_printf(dev,"%s property is invalid\n", name); + return (ENXIO); + } + + return (0); +} + +static int +axgbe_attach(device_t dev) +{ + struct axgbe_softc *sc; + struct ifnet *ifp; + pcell_t phy_handle; + device_t phydev; + phandle_t node, phy_node; + struct resource *mac_res[11]; + struct resource *phy_res[4]; + ssize_t len; + int error, i, j; + + sc = device_get_softc(dev); + + node = ofw_bus_get_node(dev); + if (OF_getencprop(node, "phy-handle", &phy_handle, + sizeof(phy_handle)) <= 0) { + phy_node = node; + + if (bus_alloc_resources(dev, mac_spec, mac_res)) { + device_printf(dev, + "could not allocate phy resources\n"); + return (ENXIO); + } + + sc->prv.xgmac_res = mac_res[0]; + sc->prv.xpcs_res = mac_res[1]; + sc->prv.rxtx_res = mac_res[2]; + sc->prv.sir0_res = mac_res[3]; + sc->prv.sir1_res = mac_res[4]; + + sc->prv.dev_irq_res = mac_res[5]; + sc->prv.per_channel_irq = OF_hasprop(node, + XGBE_DMA_IRQS_PROPERTY); + for (i = 0, j = 6; j < nitems(mac_res) - 1 && + mac_res[j + 1] != NULL; i++, j++) { + if (sc->prv.per_channel_irq) { + sc->prv.chan_irq_res[i] = mac_res[j]; + } + } + + /* The last entry is the auto-negotiation interrupt */ + sc->prv.an_irq_res = mac_res[j]; + } else { + phydev = OF_device_from_xref(phy_handle); + phy_node = ofw_bus_get_node(phydev); + + if (bus_alloc_resources(phydev, old_phy_spec, phy_res)) { + device_printf(dev, + "could not allocate phy resources\n"); + return (ENXIO); + } + + if (bus_alloc_resources(dev, old_mac_spec, mac_res)) { + device_printf(dev, + "could not allocate mac resources\n"); + return (ENXIO); + } + + sc->prv.rxtx_res = phy_res[0]; + sc->prv.sir0_res = phy_res[1]; + sc->prv.sir1_res = phy_res[2]; + sc->prv.an_irq_res = phy_res[3]; + + sc->prv.xgmac_res = mac_res[0]; + sc->prv.xpcs_res = mac_res[1]; + sc->prv.dev_irq_res = mac_res[2]; + sc->prv.per_channel_irq = OF_hasprop(node, + XGBE_DMA_IRQS_PROPERTY); + if (sc->prv.per_channel_irq) { + for (i = 0, j = 3; i < nitems(sc->prv.chan_irq_res) && + mac_res[j] != NULL; i++, j++) { + sc->prv.chan_irq_res[i] = mac_res[j]; + } + } + } + + if ((len = OF_getproplen(node, "mac-address")) < 0) { + device_printf(dev, "No mac-address property\n"); + return (EINVAL); + } + + if (len != ETHER_ADDR_LEN) + return (EINVAL); + + OF_getprop(node, "mac-address", sc->mac_addr, ETHER_ADDR_LEN); + + sc->prv.netdev = ifp = if_alloc(IFT_ETHER); + if (ifp == NULL) { + device_printf(dev, "Cannot alloc ifnet\n"); + return (ENXIO); + } + + sc->prv.dev = dev; + sc->prv.dmat = bus_get_dma_tag(dev); + sc->prv.phy.advertising = ADVERTISED_10000baseKR_Full | + ADVERTISED_1000baseKX_Full; + + + /* + * Read the needed properties from the phy node. + */ + + /* This is documented as optional, but Linux requires it */ + if (OF_getencprop(phy_node, XGBE_SPEEDSET_PROPERTY, &sc->prv.speed_set, + sizeof(sc->prv.speed_set)) <= 0) { + device_printf(dev, "%s property is missing\n", + XGBE_SPEEDSET_PROPERTY); + return (EINVAL); + } + + error = axgbe_get_optional_prop(dev, phy_node, XGBE_BLWC_PROPERTY, + sc->prv.serdes_blwc, sizeof(sc->prv.serdes_blwc)); + if (error > 0) { + return (error); + } else if (error < 0) { + sc->prv.serdes_blwc[0] = XGBE_SPEED_1000_BLWC; + sc->prv.serdes_blwc[1] = XGBE_SPEED_2500_BLWC; + sc->prv.serdes_blwc[2] = XGBE_SPEED_10000_BLWC; + } + + error = axgbe_get_optional_prop(dev, phy_node, XGBE_CDR_RATE_PROPERTY, + sc->prv.serdes_cdr_rate, sizeof(sc->prv.serdes_cdr_rate)); + if (error > 0) { + return (error); + } else if (error < 0) { + sc->prv.serdes_cdr_rate[0] = XGBE_SPEED_1000_CDR; + sc->prv.serdes_cdr_rate[1] = XGBE_SPEED_2500_CDR; + sc->prv.serdes_cdr_rate[2] = XGBE_SPEED_10000_CDR; + } + + error = axgbe_get_optional_prop(dev, phy_node, XGBE_PQ_SKEW_PROPERTY, + sc->prv.serdes_pq_skew, sizeof(sc->prv.serdes_pq_skew)); + if (error > 0) { + return (error); + } else if (error < 0) { + sc->prv.serdes_pq_skew[0] = XGBE_SPEED_1000_PQ; + sc->prv.serdes_pq_skew[1] = XGBE_SPEED_2500_PQ; + sc->prv.serdes_pq_skew[2] = XGBE_SPEED_10000_PQ; + } + + error = axgbe_get_optional_prop(dev, phy_node, XGBE_TX_AMP_PROPERTY, + sc->prv.serdes_tx_amp, sizeof(sc->prv.serdes_tx_amp)); + if (error > 0) { + return (error); + } else if (error < 0) { + sc->prv.serdes_tx_amp[0] = XGBE_SPEED_1000_TXAMP; + sc->prv.serdes_tx_amp[1] = XGBE_SPEED_2500_TXAMP; + sc->prv.serdes_tx_amp[2] = XGBE_SPEED_10000_TXAMP; + } + + error = axgbe_get_optional_prop(dev, phy_node, XGBE_DFE_CFG_PROPERTY, + sc->prv.serdes_dfe_tap_cfg, sizeof(sc->prv.serdes_dfe_tap_cfg)); + if (error > 0) { + return (error); + } else if (error < 0) { + sc->prv.serdes_dfe_tap_cfg[0] = XGBE_SPEED_1000_DFE_TAP_CONFIG; + sc->prv.serdes_dfe_tap_cfg[1] = XGBE_SPEED_2500_DFE_TAP_CONFIG; + sc->prv.serdes_dfe_tap_cfg[2] = XGBE_SPEED_10000_DFE_TAP_CONFIG; + } + + error = axgbe_get_optional_prop(dev, phy_node, XGBE_DFE_ENA_PROPERTY, + sc->prv.serdes_dfe_tap_ena, sizeof(sc->prv.serdes_dfe_tap_ena)); + if (error > 0) { + return (error); + } else if (error < 0) { + sc->prv.serdes_dfe_tap_ena[0] = XGBE_SPEED_1000_DFE_TAP_ENABLE; + sc->prv.serdes_dfe_tap_ena[1] = XGBE_SPEED_2500_DFE_TAP_ENABLE; + sc->prv.serdes_dfe_tap_ena[2] = XGBE_SPEED_10000_DFE_TAP_ENABLE; + } + + /* Check if the NIC is DMA coherent */ + sc->prv.coherent = OF_hasprop(node, "dma-coherent"); + if (sc->prv.coherent) { + sc->prv.axdomain = XGBE_DMA_OS_AXDOMAIN; + sc->prv.arcache = XGBE_DMA_OS_ARCACHE; + sc->prv.awcache = XGBE_DMA_OS_AWCACHE; + } else { + sc->prv.axdomain = XGBE_DMA_SYS_AXDOMAIN; + sc->prv.arcache = XGBE_DMA_SYS_ARCACHE; + sc->prv.awcache = XGBE_DMA_SYS_AWCACHE; + } + + /* Create the lock & workqueues */ + spin_lock_init(&sc->prv.xpcs_lock); + sc->prv.dev_workqueue = taskqueue_create("axgbe", M_WAITOK, + taskqueue_thread_enqueue, &sc->prv.dev_workqueue); + taskqueue_start_threads(&sc->prv.dev_workqueue, 1, PI_NET, + "axgbe taskq"); + + /* Set the needed pointers */ + xgbe_init_function_ptrs_phy(&sc->prv.phy_if); + xgbe_init_function_ptrs_dev(&sc->prv.hw_if); + xgbe_init_function_ptrs_desc(&sc->prv.desc_if); + + /* Reset the hardware */ + sc->prv.hw_if.exit(&sc->prv); + + /* Read the hardware features */ + xgbe_get_all_hw_features(&sc->prv); + + /* Set default values */ + sc->prv.pblx8 = DMA_PBL_X8_ENABLE; + sc->prv.tx_desc_count = XGBE_TX_DESC_CNT; + sc->prv.tx_sf_mode = MTL_TSF_ENABLE; + sc->prv.tx_threshold = MTL_TX_THRESHOLD_64; + sc->prv.tx_pbl = DMA_PBL_16; + sc->prv.tx_osp_mode = DMA_OSP_ENABLE; + sc->prv.rx_desc_count = XGBE_RX_DESC_CNT; + sc->prv.rx_sf_mode = MTL_RSF_DISABLE; + sc->prv.rx_threshold = MTL_RX_THRESHOLD_64; + sc->prv.rx_pbl = DMA_PBL_16; + sc->prv.pause_autoneg = 1; + sc->prv.tx_pause = 1; + sc->prv.rx_pause = 1; + sc->prv.phy_speed = SPEED_UNKNOWN; + sc->prv.power_down = 0; + + /* TODO: Limit to min(ncpus, hw rings) */ + sc->prv.tx_ring_count = 1; + sc->prv.tx_q_count = 1; + sc->prv.rx_ring_count = 1; + sc->prv.rx_q_count = sc->prv.hw_feat.rx_q_cnt; + + /* Init the PHY */ + sc->prv.phy_if.phy_init(&sc->prv); + + /* Set the coalescing */ + xgbe_init_rx_coalesce(&sc->prv); + xgbe_init_tx_coalesce(&sc->prv); + + if_initname(ifp, device_get_name(dev), device_get_unit(dev)); + ifp->if_init = axgbe_init; + ifp->if_softc = sc; + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_ioctl = axgbe_ioctl; + ifp->if_transmit = xgbe_xmit; + ifp->if_qflush = axgbe_qflush; + ifp->if_get_counter = axgbe_get_counter; + + /* TODO: Support HW offload */ + ifp->if_capabilities = 0; + ifp->if_capenable = 0; + ifp->if_hwassist = 0; + + ether_ifattach(ifp, sc->mac_addr); + + ifmedia_init(&sc->media, IFM_IMASK, axgbe_media_change, + axgbe_media_status); +#ifdef notyet + ifmedia_add(&sc->media, IFM_ETHER | IFM_10G_KR, 0, NULL); +#endif + ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_KX, 0, NULL); + ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); + ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); + + set_bit(XGBE_DOWN, &sc->prv.dev_state); + + if (xgbe_open(ifp) < 0) { + device_printf(dev, "ndo_open failed\n"); + return (ENXIO); + } + + return (0); +} + +static device_method_t axgbe_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, axgbe_probe), + DEVMETHOD(device_attach, axgbe_attach), + + { 0, 0 } +}; + +static devclass_t axgbe_devclass; + +DEFINE_CLASS_0(axgbe, axgbe_driver, axgbe_methods, + sizeof(struct axgbe_softc)); +DRIVER_MODULE(axgbe, simplebus, axgbe_driver, axgbe_devclass, 0, 0); + + +static struct ofw_compat_data phy_compat_data[] = { + { "amd,xgbe-phy-seattle-v1a", true }, + { NULL, false } +}; + +static int +axgbephy_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_search_compatible(dev, phy_compat_data)->ocd_data) + return (ENXIO); + + device_set_desc(dev, "AMD 10 Gigabit Ethernet"); + return (BUS_PROBE_DEFAULT); +} + +static int +axgbephy_attach(device_t dev) +{ + phandle_t node; + + node = ofw_bus_get_node(dev); + OF_device_register_xref(OF_xref_from_node(node), dev); + + return (0); +} + +static device_method_t axgbephy_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, axgbephy_probe), + DEVMETHOD(device_attach, axgbephy_attach), + + { 0, 0 } +}; + +static devclass_t axgbephy_devclass; + +DEFINE_CLASS_0(axgbephy, axgbephy_driver, axgbephy_methods, 0); +EARLY_DRIVER_MODULE(axgbephy, simplebus, axgbephy_driver, axgbephy_devclass, + 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); Property changes on: head/sys/dev/axgbe/if_axgbe.c ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/dev/axgbe/xgbe-common.h =================================================================== --- head/sys/dev/axgbe/xgbe-common.h (revision 313767) +++ head/sys/dev/axgbe/xgbe-common.h (revision 313768) @@ -1,1304 +1,1310 @@ /* * AMD 10Gb Ethernet driver * * This file is available to you under your choice of the following two * licenses: * * License 1: GPLv2 * * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. * * This file is free software; you may copy, redistribute and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 2 of the License, or (at * your option) any later version. * * This file is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see . * * This file incorporates work covered by the following copyright and * permission notice: * The Synopsys DWC ETHER XGMAC Software Driver and documentation * (hereinafter "Software") is an unsupported proprietary work of Synopsys, * Inc. unless otherwise expressly agreed to in writing between Synopsys * and you. * * The Software IS NOT an item of Licensed Software or Licensed Product * under any End User Software License Agreement or Agreement for Licensed * Product with Synopsys or any supplement thereto. Permission is hereby * granted, free of charge, to any person obtaining a copy of this software * annotated with this license and the Software, to deal in the Software * without restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished * to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * * License 2: Modified BSD * * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Advanced Micro Devices, Inc. nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * This file incorporates work covered by the following copyright and * permission notice: * The Synopsys DWC ETHER XGMAC Software Driver and documentation * (hereinafter "Software") is an unsupported proprietary work of Synopsys, * Inc. unless otherwise expressly agreed to in writing between Synopsys * and you. * * The Software IS NOT an item of Licensed Software or Licensed Product * under any End User Software License Agreement or Agreement for Licensed * Product with Synopsys or any supplement thereto. Permission is hereby * granted, free of charge, to any person obtaining a copy of this software * annotated with this license and the Software, to deal in the Software * without restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished * to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ */ #ifndef __XGBE_COMMON_H__ #define __XGBE_COMMON_H__ +#include +#include + /* DMA register offsets */ #define DMA_MR 0x3000 #define DMA_SBMR 0x3004 #define DMA_ISR 0x3008 #define DMA_AXIARCR 0x3010 #define DMA_AXIAWCR 0x3018 #define DMA_DSR0 0x3020 #define DMA_DSR1 0x3024 /* DMA register entry bit positions and sizes */ #define DMA_AXIARCR_DRC_INDEX 0 #define DMA_AXIARCR_DRC_WIDTH 4 #define DMA_AXIARCR_DRD_INDEX 4 #define DMA_AXIARCR_DRD_WIDTH 2 #define DMA_AXIARCR_TEC_INDEX 8 #define DMA_AXIARCR_TEC_WIDTH 4 #define DMA_AXIARCR_TED_INDEX 12 #define DMA_AXIARCR_TED_WIDTH 2 #define DMA_AXIARCR_THC_INDEX 16 #define DMA_AXIARCR_THC_WIDTH 4 #define DMA_AXIARCR_THD_INDEX 20 #define DMA_AXIARCR_THD_WIDTH 2 #define DMA_AXIAWCR_DWC_INDEX 0 #define DMA_AXIAWCR_DWC_WIDTH 4 #define DMA_AXIAWCR_DWD_INDEX 4 #define DMA_AXIAWCR_DWD_WIDTH 2 #define DMA_AXIAWCR_RPC_INDEX 8 #define DMA_AXIAWCR_RPC_WIDTH 4 #define DMA_AXIAWCR_RPD_INDEX 12 #define DMA_AXIAWCR_RPD_WIDTH 2 #define DMA_AXIAWCR_RHC_INDEX 16 #define DMA_AXIAWCR_RHC_WIDTH 4 #define DMA_AXIAWCR_RHD_INDEX 20 #define DMA_AXIAWCR_RHD_WIDTH 2 #define DMA_AXIAWCR_TDC_INDEX 24 #define DMA_AXIAWCR_TDC_WIDTH 4 #define DMA_AXIAWCR_TDD_INDEX 28 #define DMA_AXIAWCR_TDD_WIDTH 2 #define DMA_ISR_MACIS_INDEX 17 #define DMA_ISR_MACIS_WIDTH 1 #define DMA_ISR_MTLIS_INDEX 16 #define DMA_ISR_MTLIS_WIDTH 1 #define DMA_MR_SWR_INDEX 0 #define DMA_MR_SWR_WIDTH 1 #define DMA_SBMR_EAME_INDEX 11 #define DMA_SBMR_EAME_WIDTH 1 #define DMA_SBMR_BLEN_256_INDEX 7 #define DMA_SBMR_BLEN_256_WIDTH 1 #define DMA_SBMR_UNDEF_INDEX 0 #define DMA_SBMR_UNDEF_WIDTH 1 /* DMA register values */ #define DMA_DSR_RPS_WIDTH 4 #define DMA_DSR_TPS_WIDTH 4 #define DMA_DSR_Q_WIDTH (DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH) #define DMA_DSR0_RPS_START 8 #define DMA_DSR0_TPS_START 12 #define DMA_DSRX_FIRST_QUEUE 3 #define DMA_DSRX_INC 4 #define DMA_DSRX_QPR 4 #define DMA_DSRX_RPS_START 0 #define DMA_DSRX_TPS_START 4 #define DMA_TPS_STOPPED 0x00 #define DMA_TPS_SUSPENDED 0x06 /* DMA channel register offsets * Multiple channels can be active. The first channel has registers * that begin at 0x3100. Each subsequent channel has registers that * are accessed using an offset of 0x80 from the previous channel. */ #define DMA_CH_BASE 0x3100 #define DMA_CH_INC 0x80 #define DMA_CH_CR 0x00 #define DMA_CH_TCR 0x04 #define DMA_CH_RCR 0x08 #define DMA_CH_TDLR_HI 0x10 #define DMA_CH_TDLR_LO 0x14 #define DMA_CH_RDLR_HI 0x18 #define DMA_CH_RDLR_LO 0x1c #define DMA_CH_TDTR_LO 0x24 #define DMA_CH_RDTR_LO 0x2c #define DMA_CH_TDRLR 0x30 #define DMA_CH_RDRLR 0x34 #define DMA_CH_IER 0x38 #define DMA_CH_RIWT 0x3c #define DMA_CH_CATDR_LO 0x44 #define DMA_CH_CARDR_LO 0x4c #define DMA_CH_CATBR_HI 0x50 #define DMA_CH_CATBR_LO 0x54 #define DMA_CH_CARBR_HI 0x58 #define DMA_CH_CARBR_LO 0x5c #define DMA_CH_SR 0x60 /* DMA channel register entry bit positions and sizes */ #define DMA_CH_CR_PBLX8_INDEX 16 #define DMA_CH_CR_PBLX8_WIDTH 1 #define DMA_CH_CR_SPH_INDEX 24 #define DMA_CH_CR_SPH_WIDTH 1 #define DMA_CH_IER_AIE_INDEX 15 #define DMA_CH_IER_AIE_WIDTH 1 #define DMA_CH_IER_FBEE_INDEX 12 #define DMA_CH_IER_FBEE_WIDTH 1 #define DMA_CH_IER_NIE_INDEX 16 #define DMA_CH_IER_NIE_WIDTH 1 #define DMA_CH_IER_RBUE_INDEX 7 #define DMA_CH_IER_RBUE_WIDTH 1 #define DMA_CH_IER_RIE_INDEX 6 #define DMA_CH_IER_RIE_WIDTH 1 #define DMA_CH_IER_RSE_INDEX 8 #define DMA_CH_IER_RSE_WIDTH 1 #define DMA_CH_IER_TBUE_INDEX 2 #define DMA_CH_IER_TBUE_WIDTH 1 #define DMA_CH_IER_TIE_INDEX 0 #define DMA_CH_IER_TIE_WIDTH 1 #define DMA_CH_IER_TXSE_INDEX 1 #define DMA_CH_IER_TXSE_WIDTH 1 #define DMA_CH_RCR_PBL_INDEX 16 #define DMA_CH_RCR_PBL_WIDTH 6 #define DMA_CH_RCR_RBSZ_INDEX 1 #define DMA_CH_RCR_RBSZ_WIDTH 14 #define DMA_CH_RCR_SR_INDEX 0 #define DMA_CH_RCR_SR_WIDTH 1 #define DMA_CH_RIWT_RWT_INDEX 0 #define DMA_CH_RIWT_RWT_WIDTH 8 #define DMA_CH_SR_FBE_INDEX 12 #define DMA_CH_SR_FBE_WIDTH 1 #define DMA_CH_SR_RBU_INDEX 7 #define DMA_CH_SR_RBU_WIDTH 1 #define DMA_CH_SR_RI_INDEX 6 #define DMA_CH_SR_RI_WIDTH 1 #define DMA_CH_SR_RPS_INDEX 8 #define DMA_CH_SR_RPS_WIDTH 1 #define DMA_CH_SR_TBU_INDEX 2 #define DMA_CH_SR_TBU_WIDTH 1 #define DMA_CH_SR_TI_INDEX 0 #define DMA_CH_SR_TI_WIDTH 1 #define DMA_CH_SR_TPS_INDEX 1 #define DMA_CH_SR_TPS_WIDTH 1 #define DMA_CH_TCR_OSP_INDEX 4 #define DMA_CH_TCR_OSP_WIDTH 1 #define DMA_CH_TCR_PBL_INDEX 16 #define DMA_CH_TCR_PBL_WIDTH 6 #define DMA_CH_TCR_ST_INDEX 0 #define DMA_CH_TCR_ST_WIDTH 1 #define DMA_CH_TCR_TSE_INDEX 12 #define DMA_CH_TCR_TSE_WIDTH 1 /* DMA channel register values */ #define DMA_OSP_DISABLE 0x00 #define DMA_OSP_ENABLE 0x01 #define DMA_PBL_1 1 #define DMA_PBL_2 2 #define DMA_PBL_4 4 #define DMA_PBL_8 8 #define DMA_PBL_16 16 #define DMA_PBL_32 32 #define DMA_PBL_64 64 /* 8 x 8 */ #define DMA_PBL_128 128 /* 8 x 16 */ #define DMA_PBL_256 256 /* 8 x 32 */ #define DMA_PBL_X8_DISABLE 0x00 #define DMA_PBL_X8_ENABLE 0x01 /* MAC register offsets */ #define MAC_TCR 0x0000 #define MAC_RCR 0x0004 #define MAC_PFR 0x0008 #define MAC_WTR 0x000c #define MAC_HTR0 0x0010 #define MAC_VLANTR 0x0050 #define MAC_VLANHTR 0x0058 #define MAC_VLANIR 0x0060 #define MAC_IVLANIR 0x0064 #define MAC_RETMR 0x006c #define MAC_Q0TFCR 0x0070 #define MAC_RFCR 0x0090 #define MAC_RQC0R 0x00a0 #define MAC_RQC1R 0x00a4 #define MAC_RQC2R 0x00a8 #define MAC_RQC3R 0x00ac #define MAC_ISR 0x00b0 #define MAC_IER 0x00b4 #define MAC_RTSR 0x00b8 #define MAC_PMTCSR 0x00c0 #define MAC_RWKPFR 0x00c4 #define MAC_LPICSR 0x00d0 #define MAC_LPITCR 0x00d4 #define MAC_VR 0x0110 #define MAC_DR 0x0114 #define MAC_HWF0R 0x011c #define MAC_HWF1R 0x0120 #define MAC_HWF2R 0x0124 #define MAC_GPIOCR 0x0278 #define MAC_GPIOSR 0x027c #define MAC_MACA0HR 0x0300 #define MAC_MACA0LR 0x0304 #define MAC_MACA1HR 0x0308 #define MAC_MACA1LR 0x030c #define MAC_RSSCR 0x0c80 #define MAC_RSSAR 0x0c88 #define MAC_RSSDR 0x0c8c #define MAC_TSCR 0x0d00 #define MAC_SSIR 0x0d04 #define MAC_STSR 0x0d08 #define MAC_STNR 0x0d0c #define MAC_STSUR 0x0d10 #define MAC_STNUR 0x0d14 #define MAC_TSAR 0x0d18 #define MAC_TSSR 0x0d20 #define MAC_TXSNR 0x0d30 #define MAC_TXSSR 0x0d34 #define MAC_QTFCR_INC 4 #define MAC_MACA_INC 4 #define MAC_HTR_INC 4 #define MAC_RQC2_INC 4 #define MAC_RQC2_Q_PER_REG 4 /* MAC register entry bit positions and sizes */ #define MAC_HWF0R_ADDMACADRSEL_INDEX 18 #define MAC_HWF0R_ADDMACADRSEL_WIDTH 5 #define MAC_HWF0R_ARPOFFSEL_INDEX 9 #define MAC_HWF0R_ARPOFFSEL_WIDTH 1 #define MAC_HWF0R_EEESEL_INDEX 13 #define MAC_HWF0R_EEESEL_WIDTH 1 #define MAC_HWF0R_GMIISEL_INDEX 1 #define MAC_HWF0R_GMIISEL_WIDTH 1 #define MAC_HWF0R_MGKSEL_INDEX 7 #define MAC_HWF0R_MGKSEL_WIDTH 1 #define MAC_HWF0R_MMCSEL_INDEX 8 #define MAC_HWF0R_MMCSEL_WIDTH 1 #define MAC_HWF0R_RWKSEL_INDEX 6 #define MAC_HWF0R_RWKSEL_WIDTH 1 #define MAC_HWF0R_RXCOESEL_INDEX 16 #define MAC_HWF0R_RXCOESEL_WIDTH 1 #define MAC_HWF0R_SAVLANINS_INDEX 27 #define MAC_HWF0R_SAVLANINS_WIDTH 1 #define MAC_HWF0R_SMASEL_INDEX 5 #define MAC_HWF0R_SMASEL_WIDTH 1 #define MAC_HWF0R_TSSEL_INDEX 12 #define MAC_HWF0R_TSSEL_WIDTH 1 #define MAC_HWF0R_TSSTSSEL_INDEX 25 #define MAC_HWF0R_TSSTSSEL_WIDTH 2 #define MAC_HWF0R_TXCOESEL_INDEX 14 #define MAC_HWF0R_TXCOESEL_WIDTH 1 #define MAC_HWF0R_VLHASH_INDEX 4 #define MAC_HWF0R_VLHASH_WIDTH 1 #define MAC_HWF1R_ADDR64_INDEX 14 #define MAC_HWF1R_ADDR64_WIDTH 2 #define MAC_HWF1R_ADVTHWORD_INDEX 13 #define MAC_HWF1R_ADVTHWORD_WIDTH 1 #define MAC_HWF1R_DBGMEMA_INDEX 19 #define MAC_HWF1R_DBGMEMA_WIDTH 1 #define MAC_HWF1R_DCBEN_INDEX 16 #define MAC_HWF1R_DCBEN_WIDTH 1 #define MAC_HWF1R_HASHTBLSZ_INDEX 24 #define MAC_HWF1R_HASHTBLSZ_WIDTH 3 #define MAC_HWF1R_L3L4FNUM_INDEX 27 #define MAC_HWF1R_L3L4FNUM_WIDTH 4 #define MAC_HWF1R_NUMTC_INDEX 21 #define MAC_HWF1R_NUMTC_WIDTH 3 #define MAC_HWF1R_RSSEN_INDEX 20 #define MAC_HWF1R_RSSEN_WIDTH 1 #define MAC_HWF1R_RXFIFOSIZE_INDEX 0 #define MAC_HWF1R_RXFIFOSIZE_WIDTH 5 #define MAC_HWF1R_SPHEN_INDEX 17 #define MAC_HWF1R_SPHEN_WIDTH 1 #define MAC_HWF1R_TSOEN_INDEX 18 #define MAC_HWF1R_TSOEN_WIDTH 1 #define MAC_HWF1R_TXFIFOSIZE_INDEX 6 #define MAC_HWF1R_TXFIFOSIZE_WIDTH 5 #define MAC_HWF2R_AUXSNAPNUM_INDEX 28 #define MAC_HWF2R_AUXSNAPNUM_WIDTH 3 #define MAC_HWF2R_PPSOUTNUM_INDEX 24 #define MAC_HWF2R_PPSOUTNUM_WIDTH 3 #define MAC_HWF2R_RXCHCNT_INDEX 12 #define MAC_HWF2R_RXCHCNT_WIDTH 4 #define MAC_HWF2R_RXQCNT_INDEX 0 #define MAC_HWF2R_RXQCNT_WIDTH 4 #define MAC_HWF2R_TXCHCNT_INDEX 18 #define MAC_HWF2R_TXCHCNT_WIDTH 4 #define MAC_HWF2R_TXQCNT_INDEX 6 #define MAC_HWF2R_TXQCNT_WIDTH 4 #define MAC_IER_TSIE_INDEX 12 #define MAC_IER_TSIE_WIDTH 1 #define MAC_ISR_MMCRXIS_INDEX 9 #define MAC_ISR_MMCRXIS_WIDTH 1 #define MAC_ISR_MMCTXIS_INDEX 10 #define MAC_ISR_MMCTXIS_WIDTH 1 #define MAC_ISR_PMTIS_INDEX 4 #define MAC_ISR_PMTIS_WIDTH 1 #define MAC_ISR_TSIS_INDEX 12 #define MAC_ISR_TSIS_WIDTH 1 #define MAC_MACA1HR_AE_INDEX 31 #define MAC_MACA1HR_AE_WIDTH 1 #define MAC_PFR_HMC_INDEX 2 #define MAC_PFR_HMC_WIDTH 1 #define MAC_PFR_HPF_INDEX 10 #define MAC_PFR_HPF_WIDTH 1 #define MAC_PFR_HUC_INDEX 1 #define MAC_PFR_HUC_WIDTH 1 #define MAC_PFR_PM_INDEX 4 #define MAC_PFR_PM_WIDTH 1 #define MAC_PFR_PR_INDEX 0 #define MAC_PFR_PR_WIDTH 1 #define MAC_PFR_VTFE_INDEX 16 #define MAC_PFR_VTFE_WIDTH 1 #define MAC_PMTCSR_MGKPKTEN_INDEX 1 #define MAC_PMTCSR_MGKPKTEN_WIDTH 1 #define MAC_PMTCSR_PWRDWN_INDEX 0 #define MAC_PMTCSR_PWRDWN_WIDTH 1 #define MAC_PMTCSR_RWKFILTRST_INDEX 31 #define MAC_PMTCSR_RWKFILTRST_WIDTH 1 #define MAC_PMTCSR_RWKPKTEN_INDEX 2 #define MAC_PMTCSR_RWKPKTEN_WIDTH 1 #define MAC_Q0TFCR_PT_INDEX 16 #define MAC_Q0TFCR_PT_WIDTH 16 #define MAC_Q0TFCR_TFE_INDEX 1 #define MAC_Q0TFCR_TFE_WIDTH 1 #define MAC_RCR_ACS_INDEX 1 #define MAC_RCR_ACS_WIDTH 1 #define MAC_RCR_CST_INDEX 2 #define MAC_RCR_CST_WIDTH 1 #define MAC_RCR_DCRCC_INDEX 3 #define MAC_RCR_DCRCC_WIDTH 1 #define MAC_RCR_HDSMS_INDEX 12 #define MAC_RCR_HDSMS_WIDTH 3 #define MAC_RCR_IPC_INDEX 9 #define MAC_RCR_IPC_WIDTH 1 #define MAC_RCR_JE_INDEX 8 #define MAC_RCR_JE_WIDTH 1 #define MAC_RCR_LM_INDEX 10 #define MAC_RCR_LM_WIDTH 1 #define MAC_RCR_RE_INDEX 0 #define MAC_RCR_RE_WIDTH 1 #define MAC_RFCR_PFCE_INDEX 8 #define MAC_RFCR_PFCE_WIDTH 1 #define MAC_RFCR_RFE_INDEX 0 #define MAC_RFCR_RFE_WIDTH 1 #define MAC_RFCR_UP_INDEX 1 #define MAC_RFCR_UP_WIDTH 1 #define MAC_RQC0R_RXQ0EN_INDEX 0 #define MAC_RQC0R_RXQ0EN_WIDTH 2 #define MAC_RSSAR_ADDRT_INDEX 2 #define MAC_RSSAR_ADDRT_WIDTH 1 #define MAC_RSSAR_CT_INDEX 1 #define MAC_RSSAR_CT_WIDTH 1 #define MAC_RSSAR_OB_INDEX 0 #define MAC_RSSAR_OB_WIDTH 1 #define MAC_RSSAR_RSSIA_INDEX 8 #define MAC_RSSAR_RSSIA_WIDTH 8 #define MAC_RSSCR_IP2TE_INDEX 1 #define MAC_RSSCR_IP2TE_WIDTH 1 #define MAC_RSSCR_RSSE_INDEX 0 #define MAC_RSSCR_RSSE_WIDTH 1 #define MAC_RSSCR_TCP4TE_INDEX 2 #define MAC_RSSCR_TCP4TE_WIDTH 1 #define MAC_RSSCR_UDP4TE_INDEX 3 #define MAC_RSSCR_UDP4TE_WIDTH 1 #define MAC_RSSDR_DMCH_INDEX 0 #define MAC_RSSDR_DMCH_WIDTH 4 #define MAC_SSIR_SNSINC_INDEX 8 #define MAC_SSIR_SNSINC_WIDTH 8 #define MAC_SSIR_SSINC_INDEX 16 #define MAC_SSIR_SSINC_WIDTH 8 #define MAC_TCR_SS_INDEX 29 #define MAC_TCR_SS_WIDTH 2 #define MAC_TCR_TE_INDEX 0 #define MAC_TCR_TE_WIDTH 1 #define MAC_TSCR_AV8021ASMEN_INDEX 28 #define MAC_TSCR_AV8021ASMEN_WIDTH 1 #define MAC_TSCR_SNAPTYPSEL_INDEX 16 #define MAC_TSCR_SNAPTYPSEL_WIDTH 2 #define MAC_TSCR_TSADDREG_INDEX 5 #define MAC_TSCR_TSADDREG_WIDTH 1 #define MAC_TSCR_TSCFUPDT_INDEX 1 #define MAC_TSCR_TSCFUPDT_WIDTH 1 #define MAC_TSCR_TSCTRLSSR_INDEX 9 #define MAC_TSCR_TSCTRLSSR_WIDTH 1 #define MAC_TSCR_TSENA_INDEX 0 #define MAC_TSCR_TSENA_WIDTH 1 #define MAC_TSCR_TSENALL_INDEX 8 #define MAC_TSCR_TSENALL_WIDTH 1 #define MAC_TSCR_TSEVNTENA_INDEX 14 #define MAC_TSCR_TSEVNTENA_WIDTH 1 #define MAC_TSCR_TSINIT_INDEX 2 #define MAC_TSCR_TSINIT_WIDTH 1 #define MAC_TSCR_TSIPENA_INDEX 11 #define MAC_TSCR_TSIPENA_WIDTH 1 #define MAC_TSCR_TSIPV4ENA_INDEX 13 #define MAC_TSCR_TSIPV4ENA_WIDTH 1 #define MAC_TSCR_TSIPV6ENA_INDEX 12 #define MAC_TSCR_TSIPV6ENA_WIDTH 1 #define MAC_TSCR_TSMSTRENA_INDEX 15 #define MAC_TSCR_TSMSTRENA_WIDTH 1 #define MAC_TSCR_TSVER2ENA_INDEX 10 #define MAC_TSCR_TSVER2ENA_WIDTH 1 #define MAC_TSCR_TXTSSTSM_INDEX 24 #define MAC_TSCR_TXTSSTSM_WIDTH 1 #define MAC_TSSR_TXTSC_INDEX 15 #define MAC_TSSR_TXTSC_WIDTH 1 #define MAC_TXSNR_TXTSSTSMIS_INDEX 31 #define MAC_TXSNR_TXTSSTSMIS_WIDTH 1 #define MAC_VLANHTR_VLHT_INDEX 0 #define MAC_VLANHTR_VLHT_WIDTH 16 #define MAC_VLANIR_VLTI_INDEX 20 #define MAC_VLANIR_VLTI_WIDTH 1 #define MAC_VLANIR_CSVL_INDEX 19 #define MAC_VLANIR_CSVL_WIDTH 1 #define MAC_VLANTR_DOVLTC_INDEX 20 #define MAC_VLANTR_DOVLTC_WIDTH 1 #define MAC_VLANTR_ERSVLM_INDEX 19 #define MAC_VLANTR_ERSVLM_WIDTH 1 #define MAC_VLANTR_ESVL_INDEX 18 #define MAC_VLANTR_ESVL_WIDTH 1 #define MAC_VLANTR_ETV_INDEX 16 #define MAC_VLANTR_ETV_WIDTH 1 #define MAC_VLANTR_EVLS_INDEX 21 #define MAC_VLANTR_EVLS_WIDTH 2 #define MAC_VLANTR_EVLRXS_INDEX 24 #define MAC_VLANTR_EVLRXS_WIDTH 1 #define MAC_VLANTR_VL_INDEX 0 #define MAC_VLANTR_VL_WIDTH 16 #define MAC_VLANTR_VTHM_INDEX 25 #define MAC_VLANTR_VTHM_WIDTH 1 #define MAC_VLANTR_VTIM_INDEX 17 #define MAC_VLANTR_VTIM_WIDTH 1 #define MAC_VR_DEVID_INDEX 8 #define MAC_VR_DEVID_WIDTH 8 #define MAC_VR_SNPSVER_INDEX 0 #define MAC_VR_SNPSVER_WIDTH 8 #define MAC_VR_USERVER_INDEX 16 #define MAC_VR_USERVER_WIDTH 8 /* MMC register offsets */ #define MMC_CR 0x0800 #define MMC_RISR 0x0804 #define MMC_TISR 0x0808 #define MMC_RIER 0x080c #define MMC_TIER 0x0810 #define MMC_TXOCTETCOUNT_GB_LO 0x0814 #define MMC_TXOCTETCOUNT_GB_HI 0x0818 #define MMC_TXFRAMECOUNT_GB_LO 0x081c #define MMC_TXFRAMECOUNT_GB_HI 0x0820 #define MMC_TXBROADCASTFRAMES_G_LO 0x0824 #define MMC_TXBROADCASTFRAMES_G_HI 0x0828 #define MMC_TXMULTICASTFRAMES_G_LO 0x082c #define MMC_TXMULTICASTFRAMES_G_HI 0x0830 #define MMC_TX64OCTETS_GB_LO 0x0834 #define MMC_TX64OCTETS_GB_HI 0x0838 #define MMC_TX65TO127OCTETS_GB_LO 0x083c #define MMC_TX65TO127OCTETS_GB_HI 0x0840 #define MMC_TX128TO255OCTETS_GB_LO 0x0844 #define MMC_TX128TO255OCTETS_GB_HI 0x0848 #define MMC_TX256TO511OCTETS_GB_LO 0x084c #define MMC_TX256TO511OCTETS_GB_HI 0x0850 #define MMC_TX512TO1023OCTETS_GB_LO 0x0854 #define MMC_TX512TO1023OCTETS_GB_HI 0x0858 #define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c #define MMC_TX1024TOMAXOCTETS_GB_HI 0x0860 #define MMC_TXUNICASTFRAMES_GB_LO 0x0864 #define MMC_TXUNICASTFRAMES_GB_HI 0x0868 #define MMC_TXMULTICASTFRAMES_GB_LO 0x086c #define MMC_TXMULTICASTFRAMES_GB_HI 0x0870 #define MMC_TXBROADCASTFRAMES_GB_LO 0x0874 #define MMC_TXBROADCASTFRAMES_GB_HI 0x0878 #define MMC_TXUNDERFLOWERROR_LO 0x087c #define MMC_TXUNDERFLOWERROR_HI 0x0880 #define MMC_TXOCTETCOUNT_G_LO 0x0884 #define MMC_TXOCTETCOUNT_G_HI 0x0888 #define MMC_TXFRAMECOUNT_G_LO 0x088c #define MMC_TXFRAMECOUNT_G_HI 0x0890 #define MMC_TXPAUSEFRAMES_LO 0x0894 #define MMC_TXPAUSEFRAMES_HI 0x0898 #define MMC_TXVLANFRAMES_G_LO 0x089c #define MMC_TXVLANFRAMES_G_HI 0x08a0 #define MMC_RXFRAMECOUNT_GB_LO 0x0900 #define MMC_RXFRAMECOUNT_GB_HI 0x0904 #define MMC_RXOCTETCOUNT_GB_LO 0x0908 #define MMC_RXOCTETCOUNT_GB_HI 0x090c #define MMC_RXOCTETCOUNT_G_LO 0x0910 #define MMC_RXOCTETCOUNT_G_HI 0x0914 #define MMC_RXBROADCASTFRAMES_G_LO 0x0918 #define MMC_RXBROADCASTFRAMES_G_HI 0x091c #define MMC_RXMULTICASTFRAMES_G_LO 0x0920 #define MMC_RXMULTICASTFRAMES_G_HI 0x0924 #define MMC_RXCRCERROR_LO 0x0928 #define MMC_RXCRCERROR_HI 0x092c #define MMC_RXRUNTERROR 0x0930 #define MMC_RXJABBERERROR 0x0934 #define MMC_RXUNDERSIZE_G 0x0938 #define MMC_RXOVERSIZE_G 0x093c #define MMC_RX64OCTETS_GB_LO 0x0940 #define MMC_RX64OCTETS_GB_HI 0x0944 #define MMC_RX65TO127OCTETS_GB_LO 0x0948 #define MMC_RX65TO127OCTETS_GB_HI 0x094c #define MMC_RX128TO255OCTETS_GB_LO 0x0950 #define MMC_RX128TO255OCTETS_GB_HI 0x0954 #define MMC_RX256TO511OCTETS_GB_LO 0x0958 #define MMC_RX256TO511OCTETS_GB_HI 0x095c #define MMC_RX512TO1023OCTETS_GB_LO 0x0960 #define MMC_RX512TO1023OCTETS_GB_HI 0x0964 #define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968 #define MMC_RX1024TOMAXOCTETS_GB_HI 0x096c #define MMC_RXUNICASTFRAMES_G_LO 0x0970 #define MMC_RXUNICASTFRAMES_G_HI 0x0974 #define MMC_RXLENGTHERROR_LO 0x0978 #define MMC_RXLENGTHERROR_HI 0x097c #define MMC_RXOUTOFRANGETYPE_LO 0x0980 #define MMC_RXOUTOFRANGETYPE_HI 0x0984 #define MMC_RXPAUSEFRAMES_LO 0x0988 #define MMC_RXPAUSEFRAMES_HI 0x098c #define MMC_RXFIFOOVERFLOW_LO 0x0990 #define MMC_RXFIFOOVERFLOW_HI 0x0994 #define MMC_RXVLANFRAMES_GB_LO 0x0998 #define MMC_RXVLANFRAMES_GB_HI 0x099c #define MMC_RXWATCHDOGERROR 0x09a0 /* MMC register entry bit positions and sizes */ #define MMC_CR_CR_INDEX 0 #define MMC_CR_CR_WIDTH 1 #define MMC_CR_CSR_INDEX 1 #define MMC_CR_CSR_WIDTH 1 #define MMC_CR_ROR_INDEX 2 #define MMC_CR_ROR_WIDTH 1 #define MMC_CR_MCF_INDEX 3 #define MMC_CR_MCF_WIDTH 1 #define MMC_CR_MCT_INDEX 4 #define MMC_CR_MCT_WIDTH 2 #define MMC_RIER_ALL_INTERRUPTS_INDEX 0 #define MMC_RIER_ALL_INTERRUPTS_WIDTH 23 #define MMC_RISR_RXFRAMECOUNT_GB_INDEX 0 #define MMC_RISR_RXFRAMECOUNT_GB_WIDTH 1 #define MMC_RISR_RXOCTETCOUNT_GB_INDEX 1 #define MMC_RISR_RXOCTETCOUNT_GB_WIDTH 1 #define MMC_RISR_RXOCTETCOUNT_G_INDEX 2 #define MMC_RISR_RXOCTETCOUNT_G_WIDTH 1 #define MMC_RISR_RXBROADCASTFRAMES_G_INDEX 3 #define MMC_RISR_RXBROADCASTFRAMES_G_WIDTH 1 #define MMC_RISR_RXMULTICASTFRAMES_G_INDEX 4 #define MMC_RISR_RXMULTICASTFRAMES_G_WIDTH 1 #define MMC_RISR_RXCRCERROR_INDEX 5 #define MMC_RISR_RXCRCERROR_WIDTH 1 #define MMC_RISR_RXRUNTERROR_INDEX 6 #define MMC_RISR_RXRUNTERROR_WIDTH 1 #define MMC_RISR_RXJABBERERROR_INDEX 7 #define MMC_RISR_RXJABBERERROR_WIDTH 1 #define MMC_RISR_RXUNDERSIZE_G_INDEX 8 #define MMC_RISR_RXUNDERSIZE_G_WIDTH 1 #define MMC_RISR_RXOVERSIZE_G_INDEX 9 #define MMC_RISR_RXOVERSIZE_G_WIDTH 1 #define MMC_RISR_RX64OCTETS_GB_INDEX 10 #define MMC_RISR_RX64OCTETS_GB_WIDTH 1 #define MMC_RISR_RX65TO127OCTETS_GB_INDEX 11 #define MMC_RISR_RX65TO127OCTETS_GB_WIDTH 1 #define MMC_RISR_RX128TO255OCTETS_GB_INDEX 12 #define MMC_RISR_RX128TO255OCTETS_GB_WIDTH 1 #define MMC_RISR_RX256TO511OCTETS_GB_INDEX 13 #define MMC_RISR_RX256TO511OCTETS_GB_WIDTH 1 #define MMC_RISR_RX512TO1023OCTETS_GB_INDEX 14 #define MMC_RISR_RX512TO1023OCTETS_GB_WIDTH 1 #define MMC_RISR_RX1024TOMAXOCTETS_GB_INDEX 15 #define MMC_RISR_RX1024TOMAXOCTETS_GB_WIDTH 1 #define MMC_RISR_RXUNICASTFRAMES_G_INDEX 16 #define MMC_RISR_RXUNICASTFRAMES_G_WIDTH 1 #define MMC_RISR_RXLENGTHERROR_INDEX 17 #define MMC_RISR_RXLENGTHERROR_WIDTH 1 #define MMC_RISR_RXOUTOFRANGETYPE_INDEX 18 #define MMC_RISR_RXOUTOFRANGETYPE_WIDTH 1 #define MMC_RISR_RXPAUSEFRAMES_INDEX 19 #define MMC_RISR_RXPAUSEFRAMES_WIDTH 1 #define MMC_RISR_RXFIFOOVERFLOW_INDEX 20 #define MMC_RISR_RXFIFOOVERFLOW_WIDTH 1 #define MMC_RISR_RXVLANFRAMES_GB_INDEX 21 #define MMC_RISR_RXVLANFRAMES_GB_WIDTH 1 #define MMC_RISR_RXWATCHDOGERROR_INDEX 22 #define MMC_RISR_RXWATCHDOGERROR_WIDTH 1 #define MMC_TIER_ALL_INTERRUPTS_INDEX 0 #define MMC_TIER_ALL_INTERRUPTS_WIDTH 18 #define MMC_TISR_TXOCTETCOUNT_GB_INDEX 0 #define MMC_TISR_TXOCTETCOUNT_GB_WIDTH 1 #define MMC_TISR_TXFRAMECOUNT_GB_INDEX 1 #define MMC_TISR_TXFRAMECOUNT_GB_WIDTH 1 #define MMC_TISR_TXBROADCASTFRAMES_G_INDEX 2 #define MMC_TISR_TXBROADCASTFRAMES_G_WIDTH 1 #define MMC_TISR_TXMULTICASTFRAMES_G_INDEX 3 #define MMC_TISR_TXMULTICASTFRAMES_G_WIDTH 1 #define MMC_TISR_TX64OCTETS_GB_INDEX 4 #define MMC_TISR_TX64OCTETS_GB_WIDTH 1 #define MMC_TISR_TX65TO127OCTETS_GB_INDEX 5 #define MMC_TISR_TX65TO127OCTETS_GB_WIDTH 1 #define MMC_TISR_TX128TO255OCTETS_GB_INDEX 6 #define MMC_TISR_TX128TO255OCTETS_GB_WIDTH 1 #define MMC_TISR_TX256TO511OCTETS_GB_INDEX 7 #define MMC_TISR_TX256TO511OCTETS_GB_WIDTH 1 #define MMC_TISR_TX512TO1023OCTETS_GB_INDEX 8 #define MMC_TISR_TX512TO1023OCTETS_GB_WIDTH 1 #define MMC_TISR_TX1024TOMAXOCTETS_GB_INDEX 9 #define MMC_TISR_TX1024TOMAXOCTETS_GB_WIDTH 1 #define MMC_TISR_TXUNICASTFRAMES_GB_INDEX 10 #define MMC_TISR_TXUNICASTFRAMES_GB_WIDTH 1 #define MMC_TISR_TXMULTICASTFRAMES_GB_INDEX 11 #define MMC_TISR_TXMULTICASTFRAMES_GB_WIDTH 1 #define MMC_TISR_TXBROADCASTFRAMES_GB_INDEX 12 #define MMC_TISR_TXBROADCASTFRAMES_GB_WIDTH 1 #define MMC_TISR_TXUNDERFLOWERROR_INDEX 13 #define MMC_TISR_TXUNDERFLOWERROR_WIDTH 1 #define MMC_TISR_TXOCTETCOUNT_G_INDEX 14 #define MMC_TISR_TXOCTETCOUNT_G_WIDTH 1 #define MMC_TISR_TXFRAMECOUNT_G_INDEX 15 #define MMC_TISR_TXFRAMECOUNT_G_WIDTH 1 #define MMC_TISR_TXPAUSEFRAMES_INDEX 16 #define MMC_TISR_TXPAUSEFRAMES_WIDTH 1 #define MMC_TISR_TXVLANFRAMES_G_INDEX 17 #define MMC_TISR_TXVLANFRAMES_G_WIDTH 1 /* MTL register offsets */ #define MTL_OMR 0x1000 #define MTL_FDCR 0x1008 #define MTL_FDSR 0x100c #define MTL_FDDR 0x1010 #define MTL_ISR 0x1020 #define MTL_RQDCM0R 0x1030 #define MTL_TCPM0R 0x1040 #define MTL_TCPM1R 0x1044 #define MTL_RQDCM_INC 4 #define MTL_RQDCM_Q_PER_REG 4 #define MTL_TCPM_INC 4 #define MTL_TCPM_TC_PER_REG 4 /* MTL register entry bit positions and sizes */ #define MTL_OMR_ETSALG_INDEX 5 #define MTL_OMR_ETSALG_WIDTH 2 #define MTL_OMR_RAA_INDEX 2 #define MTL_OMR_RAA_WIDTH 1 /* MTL queue register offsets * Multiple queues can be active. The first queue has registers * that begin at 0x1100. Each subsequent queue has registers that * are accessed using an offset of 0x80 from the previous queue. */ #define MTL_Q_BASE 0x1100 #define MTL_Q_INC 0x80 #define MTL_Q_TQOMR 0x00 #define MTL_Q_TQUR 0x04 #define MTL_Q_TQDR 0x08 #define MTL_Q_RQOMR 0x40 #define MTL_Q_RQMPOCR 0x44 #define MTL_Q_RQDR 0x48 #define MTL_Q_RQFCR 0x50 #define MTL_Q_IER 0x70 #define MTL_Q_ISR 0x74 /* MTL queue register entry bit positions and sizes */ #define MTL_Q_RQDR_PRXQ_INDEX 16 #define MTL_Q_RQDR_PRXQ_WIDTH 14 #define MTL_Q_RQDR_RXQSTS_INDEX 4 #define MTL_Q_RQDR_RXQSTS_WIDTH 2 #define MTL_Q_RQFCR_RFA_INDEX 1 #define MTL_Q_RQFCR_RFA_WIDTH 6 #define MTL_Q_RQFCR_RFD_INDEX 17 #define MTL_Q_RQFCR_RFD_WIDTH 6 #define MTL_Q_RQOMR_EHFC_INDEX 7 #define MTL_Q_RQOMR_EHFC_WIDTH 1 #define MTL_Q_RQOMR_RQS_INDEX 16 #define MTL_Q_RQOMR_RQS_WIDTH 9 #define MTL_Q_RQOMR_RSF_INDEX 5 #define MTL_Q_RQOMR_RSF_WIDTH 1 #define MTL_Q_RQOMR_RTC_INDEX 0 #define MTL_Q_RQOMR_RTC_WIDTH 2 #define MTL_Q_TQOMR_FTQ_INDEX 0 #define MTL_Q_TQOMR_FTQ_WIDTH 1 #define MTL_Q_TQOMR_Q2TCMAP_INDEX 8 #define MTL_Q_TQOMR_Q2TCMAP_WIDTH 3 #define MTL_Q_TQOMR_TQS_INDEX 16 #define MTL_Q_TQOMR_TQS_WIDTH 10 #define MTL_Q_TQOMR_TSF_INDEX 1 #define MTL_Q_TQOMR_TSF_WIDTH 1 #define MTL_Q_TQOMR_TTC_INDEX 4 #define MTL_Q_TQOMR_TTC_WIDTH 3 #define MTL_Q_TQOMR_TXQEN_INDEX 2 #define MTL_Q_TQOMR_TXQEN_WIDTH 2 /* MTL queue register value */ #define MTL_RSF_DISABLE 0x00 #define MTL_RSF_ENABLE 0x01 #define MTL_TSF_DISABLE 0x00 #define MTL_TSF_ENABLE 0x01 #define MTL_RX_THRESHOLD_64 0x00 #define MTL_RX_THRESHOLD_96 0x02 #define MTL_RX_THRESHOLD_128 0x03 #define MTL_TX_THRESHOLD_32 0x01 #define MTL_TX_THRESHOLD_64 0x00 #define MTL_TX_THRESHOLD_96 0x02 #define MTL_TX_THRESHOLD_128 0x03 #define MTL_TX_THRESHOLD_192 0x04 #define MTL_TX_THRESHOLD_256 0x05 #define MTL_TX_THRESHOLD_384 0x06 #define MTL_TX_THRESHOLD_512 0x07 #define MTL_ETSALG_WRR 0x00 #define MTL_ETSALG_WFQ 0x01 #define MTL_ETSALG_DWRR 0x02 #define MTL_RAA_SP 0x00 #define MTL_RAA_WSP 0x01 #define MTL_Q_DISABLED 0x00 #define MTL_Q_ENABLED 0x02 /* MTL traffic class register offsets * Multiple traffic classes can be active. The first class has registers * that begin at 0x1100. Each subsequent queue has registers that * are accessed using an offset of 0x80 from the previous queue. */ #define MTL_TC_BASE MTL_Q_BASE #define MTL_TC_INC MTL_Q_INC #define MTL_TC_ETSCR 0x10 #define MTL_TC_ETSSR 0x14 #define MTL_TC_QWR 0x18 /* MTL traffic class register entry bit positions and sizes */ #define MTL_TC_ETSCR_TSA_INDEX 0 #define MTL_TC_ETSCR_TSA_WIDTH 2 #define MTL_TC_QWR_QW_INDEX 0 #define MTL_TC_QWR_QW_WIDTH 21 /* MTL traffic class register value */ #define MTL_TSA_SP 0x00 #define MTL_TSA_ETS 0x02 /* PCS MMD select register offset * The MMD select register is used for accessing PCS registers * when the underlying APB3 interface is using indirect addressing. * Indirect addressing requires accessing registers in two phases, * an address phase and a data phase. The address phases requires * writing an address selection value to the MMD select regiesters. */ #define PCS_MMD_SELECT 0xff /* SerDes integration register offsets */ #define SIR0_KR_RT_1 0x002c #define SIR0_STATUS 0x0040 #define SIR1_SPEED 0x0000 /* SerDes integration register entry bit positions and sizes */ #define SIR0_KR_RT_1_RESET_INDEX 11 #define SIR0_KR_RT_1_RESET_WIDTH 1 #define SIR0_STATUS_RX_READY_INDEX 0 #define SIR0_STATUS_RX_READY_WIDTH 1 #define SIR0_STATUS_TX_READY_INDEX 8 #define SIR0_STATUS_TX_READY_WIDTH 1 #define SIR1_SPEED_CDR_RATE_INDEX 12 #define SIR1_SPEED_CDR_RATE_WIDTH 4 #define SIR1_SPEED_DATARATE_INDEX 4 #define SIR1_SPEED_DATARATE_WIDTH 2 #define SIR1_SPEED_PLLSEL_INDEX 3 #define SIR1_SPEED_PLLSEL_WIDTH 1 #define SIR1_SPEED_RATECHANGE_INDEX 6 #define SIR1_SPEED_RATECHANGE_WIDTH 1 #define SIR1_SPEED_TXAMP_INDEX 8 #define SIR1_SPEED_TXAMP_WIDTH 4 #define SIR1_SPEED_WORDMODE_INDEX 0 #define SIR1_SPEED_WORDMODE_WIDTH 3 /* SerDes RxTx register offsets */ #define RXTX_REG6 0x0018 #define RXTX_REG20 0x0050 #define RXTX_REG22 0x0058 #define RXTX_REG114 0x01c8 #define RXTX_REG129 0x0204 /* SerDes RxTx register entry bit positions and sizes */ #define RXTX_REG6_RESETB_RXD_INDEX 8 #define RXTX_REG6_RESETB_RXD_WIDTH 1 #define RXTX_REG20_BLWC_ENA_INDEX 2 #define RXTX_REG20_BLWC_ENA_WIDTH 1 #define RXTX_REG114_PQ_REG_INDEX 9 #define RXTX_REG114_PQ_REG_WIDTH 7 #define RXTX_REG129_RXDFE_CONFIG_INDEX 14 #define RXTX_REG129_RXDFE_CONFIG_WIDTH 2 /* Descriptor/Packet entry bit positions and sizes */ #define RX_PACKET_ERRORS_CRC_INDEX 2 #define RX_PACKET_ERRORS_CRC_WIDTH 1 #define RX_PACKET_ERRORS_FRAME_INDEX 3 #define RX_PACKET_ERRORS_FRAME_WIDTH 1 #define RX_PACKET_ERRORS_LENGTH_INDEX 0 #define RX_PACKET_ERRORS_LENGTH_WIDTH 1 #define RX_PACKET_ERRORS_OVERRUN_INDEX 1 #define RX_PACKET_ERRORS_OVERRUN_WIDTH 1 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX 0 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH 1 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 1 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1 #define RX_PACKET_ATTRIBUTES_INCOMPLETE_INDEX 2 #define RX_PACKET_ATTRIBUTES_INCOMPLETE_WIDTH 1 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX 3 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH 1 #define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX 4 #define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH 1 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX 5 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH 1 #define RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX 6 #define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH 1 #define RX_NORMAL_DESC0_OVT_INDEX 0 #define RX_NORMAL_DESC0_OVT_WIDTH 16 #define RX_NORMAL_DESC2_HL_INDEX 0 #define RX_NORMAL_DESC2_HL_WIDTH 10 #define RX_NORMAL_DESC3_CDA_INDEX 27 #define RX_NORMAL_DESC3_CDA_WIDTH 1 #define RX_NORMAL_DESC3_CTXT_INDEX 30 #define RX_NORMAL_DESC3_CTXT_WIDTH 1 #define RX_NORMAL_DESC3_ES_INDEX 15 #define RX_NORMAL_DESC3_ES_WIDTH 1 #define RX_NORMAL_DESC3_ETLT_INDEX 16 #define RX_NORMAL_DESC3_ETLT_WIDTH 4 #define RX_NORMAL_DESC3_FD_INDEX 29 #define RX_NORMAL_DESC3_FD_WIDTH 1 #define RX_NORMAL_DESC3_INTE_INDEX 30 #define RX_NORMAL_DESC3_INTE_WIDTH 1 #define RX_NORMAL_DESC3_L34T_INDEX 20 #define RX_NORMAL_DESC3_L34T_WIDTH 4 #define RX_NORMAL_DESC3_LD_INDEX 28 #define RX_NORMAL_DESC3_LD_WIDTH 1 #define RX_NORMAL_DESC3_OWN_INDEX 31 #define RX_NORMAL_DESC3_OWN_WIDTH 1 #define RX_NORMAL_DESC3_PL_INDEX 0 #define RX_NORMAL_DESC3_PL_WIDTH 14 #define RX_NORMAL_DESC3_RSV_INDEX 26 #define RX_NORMAL_DESC3_RSV_WIDTH 1 #define RX_DESC3_L34T_IPV4_TCP 1 #define RX_DESC3_L34T_IPV4_UDP 2 #define RX_DESC3_L34T_IPV4_ICMP 3 #define RX_DESC3_L34T_IPV6_TCP 9 #define RX_DESC3_L34T_IPV6_UDP 10 #define RX_DESC3_L34T_IPV6_ICMP 11 #define RX_CONTEXT_DESC3_TSA_INDEX 4 #define RX_CONTEXT_DESC3_TSA_WIDTH 1 #define RX_CONTEXT_DESC3_TSD_INDEX 6 #define RX_CONTEXT_DESC3_TSD_WIDTH 1 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 1 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX 1 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH 1 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 2 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1 #define TX_PACKET_ATTRIBUTES_PTP_INDEX 3 #define TX_PACKET_ATTRIBUTES_PTP_WIDTH 1 #define TX_CONTEXT_DESC2_MSS_INDEX 0 #define TX_CONTEXT_DESC2_MSS_WIDTH 15 #define TX_CONTEXT_DESC3_CTXT_INDEX 30 #define TX_CONTEXT_DESC3_CTXT_WIDTH 1 #define TX_CONTEXT_DESC3_TCMSSV_INDEX 26 #define TX_CONTEXT_DESC3_TCMSSV_WIDTH 1 #define TX_CONTEXT_DESC3_VLTV_INDEX 16 #define TX_CONTEXT_DESC3_VLTV_WIDTH 1 #define TX_CONTEXT_DESC3_VT_INDEX 0 #define TX_CONTEXT_DESC3_VT_WIDTH 16 #define TX_NORMAL_DESC2_HL_B1L_INDEX 0 #define TX_NORMAL_DESC2_HL_B1L_WIDTH 14 #define TX_NORMAL_DESC2_IC_INDEX 31 #define TX_NORMAL_DESC2_IC_WIDTH 1 #define TX_NORMAL_DESC2_TTSE_INDEX 30 #define TX_NORMAL_DESC2_TTSE_WIDTH 1 #define TX_NORMAL_DESC2_VTIR_INDEX 14 #define TX_NORMAL_DESC2_VTIR_WIDTH 2 #define TX_NORMAL_DESC3_CIC_INDEX 16 #define TX_NORMAL_DESC3_CIC_WIDTH 2 #define TX_NORMAL_DESC3_CPC_INDEX 26 #define TX_NORMAL_DESC3_CPC_WIDTH 2 #define TX_NORMAL_DESC3_CTXT_INDEX 30 #define TX_NORMAL_DESC3_CTXT_WIDTH 1 #define TX_NORMAL_DESC3_FD_INDEX 29 #define TX_NORMAL_DESC3_FD_WIDTH 1 #define TX_NORMAL_DESC3_FL_INDEX 0 #define TX_NORMAL_DESC3_FL_WIDTH 15 #define TX_NORMAL_DESC3_LD_INDEX 28 #define TX_NORMAL_DESC3_LD_WIDTH 1 #define TX_NORMAL_DESC3_OWN_INDEX 31 #define TX_NORMAL_DESC3_OWN_WIDTH 1 #define TX_NORMAL_DESC3_TCPHDRLEN_INDEX 19 #define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH 4 #define TX_NORMAL_DESC3_TCPPL_INDEX 0 #define TX_NORMAL_DESC3_TCPPL_WIDTH 18 #define TX_NORMAL_DESC3_TSE_INDEX 18 #define TX_NORMAL_DESC3_TSE_WIDTH 1 #define TX_NORMAL_DESC2_VLAN_INSERT 0x2 /* MDIO undefined or vendor specific registers */ #ifndef MDIO_PMA_10GBR_PMD_CTRL #define MDIO_PMA_10GBR_PMD_CTRL 0x0096 #endif #ifndef MDIO_PMA_10GBR_FECCTRL #define MDIO_PMA_10GBR_FECCTRL 0x00ab #endif #ifndef MDIO_AN_XNP #define MDIO_AN_XNP 0x0016 #endif #ifndef MDIO_AN_LPX #define MDIO_AN_LPX 0x0019 #endif #ifndef MDIO_AN_COMP_STAT #define MDIO_AN_COMP_STAT 0x0030 #endif #ifndef MDIO_AN_INTMASK #define MDIO_AN_INTMASK 0x8001 #endif #ifndef MDIO_AN_INT #define MDIO_AN_INT 0x8002 #endif #ifndef MDIO_CTRL1_SPEED1G #define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100) #endif /* MDIO mask values */ #define XGBE_XNP_MCF_NULL_MESSAGE 0x001 #define XGBE_XNP_ACK_PROCESSED BIT(12) #define XGBE_XNP_MP_FORMATTED BIT(13) #define XGBE_XNP_NP_EXCHANGE BIT(15) #define XGBE_KR_TRAINING_START BIT(0) #define XGBE_KR_TRAINING_ENABLE BIT(1) /* Bit setting and getting macros * The get macro will extract the current bit field value from within * the variable * * The set macro will clear the current bit field value within the * variable and then set the bit field of the variable to the * specified value */ #define GET_BITS(_var, _index, _width) \ (((_var) >> (_index)) & ((0x1 << (_width)) - 1)) #define SET_BITS(_var, _index, _width, _val) \ do { \ (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \ (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \ } while (0) #define GET_BITS_LE(_var, _index, _width) \ ((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1)) #define SET_BITS_LE(_var, _index, _width, _val) \ do { \ (_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index))); \ (_var) |= cpu_to_le32((((_val) & \ ((0x1 << (_width)) - 1)) << (_index))); \ } while (0) /* Bit setting and getting macros based on register fields * The get macro uses the bit field definitions formed using the input * names to extract the current bit field value from within the * variable * * The set macro uses the bit field definitions formed using the input * names to set the bit field of the variable to the specified value */ #define XGMAC_GET_BITS(_var, _prefix, _field) \ GET_BITS((_var), \ _prefix##_##_field##_INDEX, \ _prefix##_##_field##_WIDTH) #define XGMAC_SET_BITS(_var, _prefix, _field, _val) \ SET_BITS((_var), \ _prefix##_##_field##_INDEX, \ _prefix##_##_field##_WIDTH, (_val)) #define XGMAC_GET_BITS_LE(_var, _prefix, _field) \ GET_BITS_LE((_var), \ _prefix##_##_field##_INDEX, \ _prefix##_##_field##_WIDTH) #define XGMAC_SET_BITS_LE(_var, _prefix, _field, _val) \ SET_BITS_LE((_var), \ _prefix##_##_field##_INDEX, \ _prefix##_##_field##_WIDTH, (_val)) /* Macros for reading or writing registers * The ioread macros will get bit fields or full values using the * register definitions formed using the input names * * The iowrite macros will set bit fields or full values using the * register definitions formed using the input names */ #define XGMAC_IOREAD(_pdata, _reg) \ - ioread32((_pdata)->xgmac_regs + _reg) + bus_read_4((_pdata)->xgmac_res, _reg) #define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \ GET_BITS(XGMAC_IOREAD((_pdata), _reg), \ _reg##_##_field##_INDEX, \ _reg##_##_field##_WIDTH) #define XGMAC_IOWRITE(_pdata, _reg, _val) \ - iowrite32((_val), (_pdata)->xgmac_regs + _reg) + bus_write_4((_pdata)->xgmac_res, _reg, (_val)) #define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \ do { \ u32 reg_val = XGMAC_IOREAD((_pdata), _reg); \ SET_BITS(reg_val, \ _reg##_##_field##_INDEX, \ _reg##_##_field##_WIDTH, (_val)); \ XGMAC_IOWRITE((_pdata), _reg, reg_val); \ } while (0) /* Macros for reading or writing MTL queue or traffic class registers * Similar to the standard read and write macros except that the * base register value is calculated by the queue or traffic class number */ #define XGMAC_MTL_IOREAD(_pdata, _n, _reg) \ - ioread32((_pdata)->xgmac_regs + \ + bus_read_4((_pdata)->xgmac_res, \ MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg) #define XGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \ GET_BITS(XGMAC_MTL_IOREAD((_pdata), (_n), _reg), \ _reg##_##_field##_INDEX, \ _reg##_##_field##_WIDTH) #define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \ - iowrite32((_val), (_pdata)->xgmac_regs + \ - MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg) + bus_write_4((_pdata)->xgmac_res, \ + MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg, (_val)) #define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \ do { \ u32 reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg); \ SET_BITS(reg_val, \ _reg##_##_field##_INDEX, \ _reg##_##_field##_WIDTH, (_val)); \ XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \ } while (0) /* Macros for reading or writing DMA channel registers * Similar to the standard read and write macros except that the * base register value is obtained from the ring */ #define XGMAC_DMA_IOREAD(_channel, _reg) \ - ioread32((_channel)->dma_regs + _reg) + bus_space_read_4((_channel)->dma_tag, (_channel)->dma_handle, _reg) #define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \ GET_BITS(XGMAC_DMA_IOREAD((_channel), _reg), \ _reg##_##_field##_INDEX, \ _reg##_##_field##_WIDTH) #define XGMAC_DMA_IOWRITE(_channel, _reg, _val) \ - iowrite32((_val), (_channel)->dma_regs + _reg) + bus_space_write_4((_channel)->dma_tag, (_channel)->dma_handle, \ + _reg, (_val)) #define XGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \ do { \ u32 reg_val = XGMAC_DMA_IOREAD((_channel), _reg); \ SET_BITS(reg_val, \ _reg##_##_field##_INDEX, \ _reg##_##_field##_WIDTH, (_val)); \ XGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \ } while (0) /* Macros for building, reading or writing register values or bits * within the register values of XPCS registers. */ #define XPCS_IOWRITE(_pdata, _off, _val) \ - iowrite32(_val, (_pdata)->xpcs_regs + (_off)) + bus_write_4((_pdata)->xpcs_res, (_off), _val) #define XPCS_IOREAD(_pdata, _off) \ - ioread32((_pdata)->xpcs_regs + (_off)) + bus_read_4((_pdata)->xpcs_res, (_off)) /* Macros for building, reading or writing register values or bits * within the register values of SerDes integration registers. */ #define XSIR_GET_BITS(_var, _prefix, _field) \ GET_BITS((_var), \ _prefix##_##_field##_INDEX, \ _prefix##_##_field##_WIDTH) #define XSIR_SET_BITS(_var, _prefix, _field, _val) \ SET_BITS((_var), \ _prefix##_##_field##_INDEX, \ _prefix##_##_field##_WIDTH, (_val)) #define XSIR0_IOREAD(_pdata, _reg) \ - ioread16((_pdata)->sir0_regs + _reg) + bus_read_2((_pdata)->sir0_res, _reg) #define XSIR0_IOREAD_BITS(_pdata, _reg, _field) \ GET_BITS(XSIR0_IOREAD((_pdata), _reg), \ _reg##_##_field##_INDEX, \ _reg##_##_field##_WIDTH) #define XSIR0_IOWRITE(_pdata, _reg, _val) \ - iowrite16((_val), (_pdata)->sir0_regs + _reg) + bus_write_2((_pdata)->sir0_res, _reg, (_val)) #define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \ do { \ u16 reg_val = XSIR0_IOREAD((_pdata), _reg); \ SET_BITS(reg_val, \ _reg##_##_field##_INDEX, \ _reg##_##_field##_WIDTH, (_val)); \ XSIR0_IOWRITE((_pdata), _reg, reg_val); \ } while (0) #define XSIR1_IOREAD(_pdata, _reg) \ - ioread16((_pdata)->sir1_regs + _reg) + bus_read_2((_pdata)->sir1_res, _reg) #define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \ GET_BITS(XSIR1_IOREAD((_pdata), _reg), \ _reg##_##_field##_INDEX, \ _reg##_##_field##_WIDTH) #define XSIR1_IOWRITE(_pdata, _reg, _val) \ - iowrite16((_val), (_pdata)->sir1_regs + _reg) + bus_write_2((_pdata)->sir1_res, _reg, (_val)) #define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \ do { \ u16 reg_val = XSIR1_IOREAD((_pdata), _reg); \ SET_BITS(reg_val, \ _reg##_##_field##_INDEX, \ _reg##_##_field##_WIDTH, (_val)); \ XSIR1_IOWRITE((_pdata), _reg, reg_val); \ } while (0) /* Macros for building, reading or writing register values or bits * within the register values of SerDes RxTx registers. */ #define XRXTX_IOREAD(_pdata, _reg) \ - ioread16((_pdata)->rxtx_regs + _reg) + bus_read_2((_pdata)->rxtx_res, _reg) #define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \ GET_BITS(XRXTX_IOREAD((_pdata), _reg), \ _reg##_##_field##_INDEX, \ _reg##_##_field##_WIDTH) #define XRXTX_IOWRITE(_pdata, _reg, _val) \ - iowrite16((_val), (_pdata)->rxtx_regs + _reg) + bus_write_2((_pdata)->rxtx_res, _reg, (_val)) #define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \ do { \ u16 reg_val = XRXTX_IOREAD((_pdata), _reg); \ SET_BITS(reg_val, \ _reg##_##_field##_INDEX, \ _reg##_##_field##_WIDTH, (_val)); \ XRXTX_IOWRITE((_pdata), _reg, reg_val); \ } while (0) /* Macros for building, reading or writing register values or bits * using MDIO. Different from above because of the use of standardized * Linux include values. No shifting is performed with the bit * operations, everything works on mask values. */ #define XMDIO_READ(_pdata, _mmd, _reg) \ ((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \ MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff))) #define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \ (XMDIO_READ((_pdata), _mmd, _reg) & _mask) #define XMDIO_WRITE(_pdata, _mmd, _reg, _val) \ ((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \ MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff), (_val))) #define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \ do { \ u32 mmd_val = XMDIO_READ((_pdata), _mmd, _reg); \ mmd_val &= ~_mask; \ mmd_val |= (_val); \ XMDIO_WRITE((_pdata), _mmd, _reg, mmd_val); \ } while (0) #endif Property changes on: head/sys/dev/axgbe/xgbe-common.h ___________________________________________________________________ Deleted: fbsd:nokeywords ## -1 +0,0 ## -yes \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/dev/axgbe/xgbe-desc.c =================================================================== --- head/sys/dev/axgbe/xgbe-desc.c (revision 313767) +++ head/sys/dev/axgbe/xgbe-desc.c (revision 313768) @@ -1,644 +1,539 @@ /* * AMD 10Gb Ethernet driver * * This file is available to you under your choice of the following two * licenses: * * License 1: GPLv2 * * Copyright (c) 2014 Advanced Micro Devices, Inc. * * This file is free software; you may copy, redistribute and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 2 of the License, or (at * your option) any later version. * * This file is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see . * * This file incorporates work covered by the following copyright and * permission notice: * The Synopsys DWC ETHER XGMAC Software Driver and documentation * (hereinafter "Software") is an unsupported proprietary work of Synopsys, * Inc. unless otherwise expressly agreed to in writing between Synopsys * and you. * * The Software IS NOT an item of Licensed Software or Licensed Product * under any End User Software License Agreement or Agreement for Licensed * Product with Synopsys or any supplement thereto. Permission is hereby * granted, free of charge, to any person obtaining a copy of this software * annotated with this license and the Software, to deal in the Software * without restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished * to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * * License 2: Modified BSD * * Copyright (c) 2014 Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Advanced Micro Devices, Inc. nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * This file incorporates work covered by the following copyright and * permission notice: * The Synopsys DWC ETHER XGMAC Software Driver and documentation * (hereinafter "Software") is an unsupported proprietary work of Synopsys, * Inc. unless otherwise expressly agreed to in writing between Synopsys * and you. * * The Software IS NOT an item of Licensed Software or Licensed Product * under any End User Software License Agreement or Agreement for Licensed * Product with Synopsys or any supplement thereto. Permission is hereby * granted, free of charge, to any person obtaining a copy of this software * annotated with this license and the Software, to deal in the Software * without restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished * to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ +#include +__FBSDID("$FreeBSD$"); + #include "xgbe.h" #include "xgbe-common.h" static void xgbe_unmap_rdata(struct xgbe_prv_data *, struct xgbe_ring_data *); static void xgbe_free_ring(struct xgbe_prv_data *pdata, struct xgbe_ring *ring) { struct xgbe_ring_data *rdata; unsigned int i; if (!ring) return; + bus_dmamap_destroy(ring->mbuf_dmat, ring->mbuf_map); + bus_dma_tag_destroy(ring->mbuf_dmat); + + ring->mbuf_map = NULL; + ring->mbuf_dmat = NULL; + if (ring->rdata) { for (i = 0; i < ring->rdesc_count; i++) { rdata = XGBE_GET_DESC_DATA(ring, i); xgbe_unmap_rdata(pdata, rdata); } - kfree(ring->rdata); + free(ring->rdata, M_AXGBE); ring->rdata = NULL; } - if (ring->rx_hdr_pa.pages) { - dma_unmap_page(pdata->dev, ring->rx_hdr_pa.pages_dma, - ring->rx_hdr_pa.pages_len, DMA_FROM_DEVICE); - put_page(ring->rx_hdr_pa.pages); + bus_dmamap_unload(ring->rdesc_dmat, ring->rdesc_map); + bus_dmamem_free(ring->rdesc_dmat, ring->rdesc, ring->rdesc_map); + bus_dma_tag_destroy(ring->rdesc_dmat); - ring->rx_hdr_pa.pages = NULL; - ring->rx_hdr_pa.pages_len = 0; - ring->rx_hdr_pa.pages_offset = 0; - ring->rx_hdr_pa.pages_dma = 0; - } - - if (ring->rx_buf_pa.pages) { - dma_unmap_page(pdata->dev, ring->rx_buf_pa.pages_dma, - ring->rx_buf_pa.pages_len, DMA_FROM_DEVICE); - put_page(ring->rx_buf_pa.pages); - - ring->rx_buf_pa.pages = NULL; - ring->rx_buf_pa.pages_len = 0; - ring->rx_buf_pa.pages_offset = 0; - ring->rx_buf_pa.pages_dma = 0; - } - - if (ring->rdesc) { - dma_free_coherent(pdata->dev, - (sizeof(struct xgbe_ring_desc) * - ring->rdesc_count), - ring->rdesc, ring->rdesc_dma); - ring->rdesc = NULL; - } + ring->rdesc_map = NULL; + ring->rdesc_dmat = NULL; + ring->rdesc = NULL; } static void xgbe_free_ring_resources(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; unsigned int i; DBGPR("-->xgbe_free_ring_resources\n"); channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { xgbe_free_ring(pdata, channel->tx_ring); xgbe_free_ring(pdata, channel->rx_ring); } DBGPR("<--xgbe_free_ring_resources\n"); } +static void xgbe_ring_dmamap_cb(void *arg, bus_dma_segment_t * segs, int nseg, + int error) +{ + if (error) + return; + *(bus_addr_t *) arg = segs->ds_addr; +} + static int xgbe_init_ring(struct xgbe_prv_data *pdata, struct xgbe_ring *ring, unsigned int rdesc_count) { + bus_size_t len; + int err, flags; + DBGPR("-->xgbe_init_ring\n"); if (!ring) return 0; + flags = 0; + if (pdata->coherent) + flags = BUS_DMA_COHERENT; + /* Descriptors */ ring->rdesc_count = rdesc_count; - ring->rdesc = dma_alloc_coherent(pdata->dev, - (sizeof(struct xgbe_ring_desc) * - rdesc_count), &ring->rdesc_dma, - GFP_KERNEL); - if (!ring->rdesc) - return -ENOMEM; + len = sizeof(struct xgbe_ring_desc) * rdesc_count; + err = bus_dma_tag_create(pdata->dmat, 512, 0, BUS_SPACE_MAXADDR, + BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, flags, NULL, NULL, + &ring->rdesc_dmat); + if (err != 0) { + printf("Unable to create the DMA tag: %d\n", err); + return -err; + } + err = bus_dmamem_alloc(ring->rdesc_dmat, (void **)&ring->rdesc, + BUS_DMA_WAITOK | BUS_DMA_COHERENT, &ring->rdesc_map); + if (err != 0) { + bus_dma_tag_destroy(ring->rdesc_dmat); + printf("Unable to allocate DMA memory: %d\n", err); + return -err; + } + err = bus_dmamap_load(ring->rdesc_dmat, ring->rdesc_map, ring->rdesc, + len, xgbe_ring_dmamap_cb, &ring->rdesc_paddr, 0); + if (err != 0) { + bus_dmamem_free(ring->rdesc_dmat, ring->rdesc, ring->rdesc_map); + bus_dma_tag_destroy(ring->rdesc_dmat); + printf("Unable to load DMA memory\n"); + return -err; + } + /* Descriptor information */ - ring->rdata = kcalloc(rdesc_count, sizeof(struct xgbe_ring_data), - GFP_KERNEL); - if (!ring->rdata) - return -ENOMEM; + ring->rdata = malloc(rdesc_count * sizeof(struct xgbe_ring_data), + M_AXGBE, M_WAITOK | M_ZERO); - netif_dbg(pdata, drv, pdata->netdev, - "rdesc=%p, rdesc_dma=%pad, rdata=%p\n", - ring->rdesc, &ring->rdesc_dma, ring->rdata); + /* Create the space DMA tag for mbufs */ + err = bus_dma_tag_create(pdata->dmat, 1, 0, BUS_SPACE_MAXADDR, + BUS_SPACE_MAXADDR, NULL, NULL, XGBE_TX_MAX_BUF_SIZE * rdesc_count, + rdesc_count, XGBE_TX_MAX_BUF_SIZE, flags, NULL, NULL, + &ring->mbuf_dmat); + if (err != 0) + return -err; + err = bus_dmamap_create(ring->mbuf_dmat, 0, &ring->mbuf_map); + if (err != 0) + return -err; + DBGPR("<--xgbe_init_ring\n"); return 0; } static int xgbe_alloc_ring_resources(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; unsigned int i; int ret; DBGPR("-->xgbe_alloc_ring_resources\n"); channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { - netif_dbg(pdata, drv, pdata->netdev, "%s - Tx ring:\n", - channel->name); - ret = xgbe_init_ring(pdata, channel->tx_ring, pdata->tx_desc_count); if (ret) { - netdev_alert(pdata->netdev, - "error initializing Tx ring\n"); + printf("error initializing Tx ring\n"); goto err_ring; } - netif_dbg(pdata, drv, pdata->netdev, "%s - Rx ring:\n", - channel->name); - ret = xgbe_init_ring(pdata, channel->rx_ring, pdata->rx_desc_count); if (ret) { - netdev_alert(pdata->netdev, - "error initializing Rx ring\n"); + printf("error initializing Rx ring\n"); goto err_ring; } } DBGPR("<--xgbe_alloc_ring_resources\n"); return 0; err_ring: xgbe_free_ring_resources(pdata); return ret; } -static int xgbe_alloc_pages(struct xgbe_prv_data *pdata, - struct xgbe_page_alloc *pa, gfp_t gfp, int order) +static int xgbe_map_rx_buffer(struct xgbe_prv_data *pdata, + struct xgbe_ring *ring, + struct xgbe_ring_data *rdata) { - struct page *pages = NULL; - dma_addr_t pages_dma; - int ret; + bus_dmamap_t mbuf_map; + bus_dma_segment_t segs[2]; + struct mbuf *m0, *m1; + int err, nsegs; - /* Try to obtain pages, decreasing order if necessary */ - gfp |= __GFP_COLD | __GFP_COMP | __GFP_NOWARN; - while (order >= 0) { - pages = alloc_pages(gfp, order); - if (pages) - break; + m0 = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MCLBYTES); + if (m0 == NULL) + return (-ENOBUFS); - order--; + m1 = m_getjcl(M_NOWAIT, MT_DATA, 0, MCLBYTES); + if (m1 == NULL) { + m_freem(m0); + return (-ENOBUFS); } - if (!pages) - return -ENOMEM; - /* Map the pages */ - pages_dma = dma_map_page(pdata->dev, pages, 0, - PAGE_SIZE << order, DMA_FROM_DEVICE); - ret = dma_mapping_error(pdata->dev, pages_dma); - if (ret) { - put_page(pages); - return ret; - } + m0->m_next = m1; + m0->m_flags |= M_PKTHDR; + m0->m_len = MHLEN; + m0->m_pkthdr.len = MHLEN + MCLBYTES; - pa->pages = pages; - pa->pages_len = PAGE_SIZE << order; - pa->pages_offset = 0; - pa->pages_dma = pages_dma; + m1->m_len = MCLBYTES; + m1->m_next = NULL; + m1->m_pkthdr.len = MCLBYTES; - return 0; -} - -static void xgbe_set_buffer_data(struct xgbe_buffer_data *bd, - struct xgbe_page_alloc *pa, - unsigned int len) -{ - get_page(pa->pages); - bd->pa = *pa; - - bd->dma_base = pa->pages_dma; - bd->dma_off = pa->pages_offset; - bd->dma_len = len; - - pa->pages_offset += len; - if ((pa->pages_offset + len) > pa->pages_len) { - /* This data descriptor is responsible for unmapping page(s) */ - bd->pa_unmap = *pa; - - /* Get a new allocation next time */ - pa->pages = NULL; - pa->pages_len = 0; - pa->pages_offset = 0; - pa->pages_dma = 0; + err = bus_dmamap_create(ring->mbuf_dmat, 0, &mbuf_map); + if (err != 0) { + m_freem(m0); + return (-err); } -} -static int xgbe_map_rx_buffer(struct xgbe_prv_data *pdata, - struct xgbe_ring *ring, - struct xgbe_ring_data *rdata) -{ - int order, ret; - - if (!ring->rx_hdr_pa.pages) { - ret = xgbe_alloc_pages(pdata, &ring->rx_hdr_pa, GFP_ATOMIC, 0); - if (ret) - return ret; + err = bus_dmamap_load_mbuf_sg(ring->mbuf_dmat, mbuf_map, m0, segs, + &nsegs, BUS_DMA_NOWAIT); + if (err != 0) { + m_freem(m0); + bus_dmamap_destroy(ring->mbuf_dmat, mbuf_map); + return (-err); } - if (!ring->rx_buf_pa.pages) { - order = max_t(int, PAGE_ALLOC_COSTLY_ORDER - 1, 0); - ret = xgbe_alloc_pages(pdata, &ring->rx_buf_pa, GFP_ATOMIC, - order); - if (ret) - return ret; - } + KASSERT(nsegs == 2, + ("xgbe_map_rx_buffer: Unable to handle multiple segments %d", + nsegs)); - /* Set up the header page info */ - xgbe_set_buffer_data(&rdata->rx.hdr, &ring->rx_hdr_pa, - XGBE_SKB_ALLOC_SIZE); + rdata->mb = m0; + rdata->mbuf_free = 0; + rdata->mbuf_dmat = ring->mbuf_dmat; + rdata->mbuf_map = mbuf_map; + rdata->mbuf_hdr_paddr = segs[0].ds_addr; + rdata->mbuf_data_paddr = segs[1].ds_addr; - /* Set up the buffer page info */ - xgbe_set_buffer_data(&rdata->rx.buf, &ring->rx_buf_pa, - pdata->rx_buf_size); - return 0; } static void xgbe_wrapper_tx_descriptor_init(struct xgbe_prv_data *pdata) { struct xgbe_hw_if *hw_if = &pdata->hw_if; struct xgbe_channel *channel; struct xgbe_ring *ring; struct xgbe_ring_data *rdata; struct xgbe_ring_desc *rdesc; - dma_addr_t rdesc_dma; + bus_addr_t rdesc_paddr; unsigned int i, j; DBGPR("-->xgbe_wrapper_tx_descriptor_init\n"); channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { ring = channel->tx_ring; if (!ring) break; rdesc = ring->rdesc; - rdesc_dma = ring->rdesc_dma; + rdesc_paddr = ring->rdesc_paddr; for (j = 0; j < ring->rdesc_count; j++) { rdata = XGBE_GET_DESC_DATA(ring, j); rdata->rdesc = rdesc; - rdata->rdesc_dma = rdesc_dma; + rdata->rdata_paddr = rdesc_paddr; rdesc++; - rdesc_dma += sizeof(struct xgbe_ring_desc); + rdesc_paddr += sizeof(struct xgbe_ring_desc); } ring->cur = 0; ring->dirty = 0; memset(&ring->tx, 0, sizeof(ring->tx)); hw_if->tx_desc_init(channel); } DBGPR("<--xgbe_wrapper_tx_descriptor_init\n"); } static void xgbe_wrapper_rx_descriptor_init(struct xgbe_prv_data *pdata) { struct xgbe_hw_if *hw_if = &pdata->hw_if; struct xgbe_channel *channel; struct xgbe_ring *ring; struct xgbe_ring_desc *rdesc; struct xgbe_ring_data *rdata; - dma_addr_t rdesc_dma; + bus_addr_t rdesc_paddr; unsigned int i, j; DBGPR("-->xgbe_wrapper_rx_descriptor_init\n"); channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { ring = channel->rx_ring; if (!ring) break; rdesc = ring->rdesc; - rdesc_dma = ring->rdesc_dma; + rdesc_paddr = ring->rdesc_paddr; for (j = 0; j < ring->rdesc_count; j++) { rdata = XGBE_GET_DESC_DATA(ring, j); rdata->rdesc = rdesc; - rdata->rdesc_dma = rdesc_dma; + rdata->rdata_paddr = rdesc_paddr; if (xgbe_map_rx_buffer(pdata, ring, rdata)) break; rdesc++; - rdesc_dma += sizeof(struct xgbe_ring_desc); + rdesc_paddr += sizeof(struct xgbe_ring_desc); } ring->cur = 0; ring->dirty = 0; hw_if->rx_desc_init(channel); } - - DBGPR("<--xgbe_wrapper_rx_descriptor_init\n"); } static void xgbe_unmap_rdata(struct xgbe_prv_data *pdata, struct xgbe_ring_data *rdata) { - if (rdata->skb_dma) { - if (rdata->mapped_as_page) { - dma_unmap_page(pdata->dev, rdata->skb_dma, - rdata->skb_dma_len, DMA_TO_DEVICE); - } else { - dma_unmap_single(pdata->dev, rdata->skb_dma, - rdata->skb_dma_len, DMA_TO_DEVICE); - } - rdata->skb_dma = 0; - rdata->skb_dma_len = 0; - } - if (rdata->skb) { - dev_kfree_skb_any(rdata->skb); - rdata->skb = NULL; - } + if (rdata->mbuf_map != NULL) + bus_dmamap_destroy(rdata->mbuf_dmat, rdata->mbuf_map); - if (rdata->rx.hdr.pa.pages) - put_page(rdata->rx.hdr.pa.pages); + if (rdata->mbuf_free) + m_freem(rdata->mb); - if (rdata->rx.hdr.pa_unmap.pages) { - dma_unmap_page(pdata->dev, rdata->rx.hdr.pa_unmap.pages_dma, - rdata->rx.hdr.pa_unmap.pages_len, - DMA_FROM_DEVICE); - put_page(rdata->rx.hdr.pa_unmap.pages); - } + rdata->mb = NULL; + rdata->mbuf_free = 0; + rdata->mbuf_hdr_paddr = 0; + rdata->mbuf_data_paddr = 0; + rdata->mbuf_len = 0; - if (rdata->rx.buf.pa.pages) - put_page(rdata->rx.buf.pa.pages); - - if (rdata->rx.buf.pa_unmap.pages) { - dma_unmap_page(pdata->dev, rdata->rx.buf.pa_unmap.pages_dma, - rdata->rx.buf.pa_unmap.pages_len, - DMA_FROM_DEVICE); - put_page(rdata->rx.buf.pa_unmap.pages); - } - memset(&rdata->tx, 0, sizeof(rdata->tx)); memset(&rdata->rx, 0, sizeof(rdata->rx)); +} - rdata->mapped_as_page = 0; +struct xgbe_map_tx_skb_data { + struct xgbe_ring *ring; + struct xgbe_packet_data *packet; + unsigned int cur_index; +}; - if (rdata->state_saved) { - rdata->state_saved = 0; - rdata->state.skb = NULL; - rdata->state.len = 0; - rdata->state.error = 0; +static void xgbe_map_tx_skb_cb(void *callback_arg, bus_dma_segment_t *segs, + int nseg, bus_size_t mapsize, int error) +{ + struct xgbe_map_tx_skb_data *data; + struct xgbe_ring_data *rdata; + struct xgbe_ring *ring; + int i; + + if (error != 0) + return; + + data = callback_arg; + ring = data->ring; + + for (i = 0; i < nseg; i++) { + rdata = XGBE_GET_DESC_DATA(ring, data->cur_index); + + KASSERT(segs[i].ds_len <= XGBE_TX_MAX_BUF_SIZE, + ("%s: Segment size is too large %ld > %d", __func__, + segs[i].ds_len, XGBE_TX_MAX_BUF_SIZE)); + + if (i == 0) { + rdata->mbuf_dmat = ring->mbuf_dmat; + bus_dmamap_create(ring->mbuf_dmat, 0, &ring->mbuf_map); + } + + rdata->mbuf_hdr_paddr = 0; + rdata->mbuf_data_paddr = segs[i].ds_addr; + rdata->mbuf_len = segs[i].ds_len; + + data->packet->length += rdata->mbuf_len; + + data->cur_index++; } } -static int xgbe_map_tx_skb(struct xgbe_channel *channel, struct sk_buff *skb) +static int xgbe_map_tx_skb(struct xgbe_channel *channel, struct mbuf *m) { - struct xgbe_prv_data *pdata = channel->pdata; struct xgbe_ring *ring = channel->tx_ring; + struct xgbe_map_tx_skb_data cbdata; struct xgbe_ring_data *rdata; struct xgbe_packet_data *packet; - struct skb_frag_struct *frag; - dma_addr_t skb_dma; unsigned int start_index, cur_index; - unsigned int offset, tso, vlan, datalen, len; - unsigned int i; + int err; DBGPR("-->xgbe_map_tx_skb: cur = %d\n", ring->cur); - offset = 0; start_index = ring->cur; cur_index = ring->cur; packet = &ring->packet_data; packet->rdesc_count = 0; packet->length = 0; - tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, - TSO_ENABLE); - vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, - VLAN_CTAG); + cbdata.ring = ring; + cbdata.packet = packet; + cbdata.cur_index = cur_index; - /* Save space for a context descriptor if needed */ - if ((tso && (packet->mss != ring->tx.cur_mss)) || - (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag))) - cur_index++; - rdata = XGBE_GET_DESC_DATA(ring, cur_index); + err = bus_dmamap_load_mbuf(ring->mbuf_dmat, ring->mbuf_map, m, + xgbe_map_tx_skb_cb, &cbdata, BUS_DMA_NOWAIT); + if (err != 0) /* TODO: Undo the mapping */ + return (-err); - if (tso) { - /* Map the TSO header */ - skb_dma = dma_map_single(pdata->dev, skb->data, - packet->header_len, DMA_TO_DEVICE); - if (dma_mapping_error(pdata->dev, skb_dma)) { - netdev_alert(pdata->netdev, "dma_map_single failed\n"); - goto err_out; - } - rdata->skb_dma = skb_dma; - rdata->skb_dma_len = packet->header_len; - netif_dbg(pdata, tx_queued, pdata->netdev, - "skb header: index=%u, dma=%pad, len=%u\n", - cur_index, &skb_dma, packet->header_len); + cur_index = cbdata.cur_index; - offset = packet->header_len; - - packet->length += packet->header_len; - - cur_index++; - rdata = XGBE_GET_DESC_DATA(ring, cur_index); - } - - /* Map the (remainder of the) packet */ - for (datalen = skb_headlen(skb) - offset; datalen; ) { - len = min_t(unsigned int, datalen, XGBE_TX_MAX_BUF_SIZE); - - skb_dma = dma_map_single(pdata->dev, skb->data + offset, len, - DMA_TO_DEVICE); - if (dma_mapping_error(pdata->dev, skb_dma)) { - netdev_alert(pdata->netdev, "dma_map_single failed\n"); - goto err_out; - } - rdata->skb_dma = skb_dma; - rdata->skb_dma_len = len; - netif_dbg(pdata, tx_queued, pdata->netdev, - "skb data: index=%u, dma=%pad, len=%u\n", - cur_index, &skb_dma, len); - - datalen -= len; - offset += len; - - packet->length += len; - - cur_index++; - rdata = XGBE_GET_DESC_DATA(ring, cur_index); - } - - for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { - netif_dbg(pdata, tx_queued, pdata->netdev, - "mapping frag %u\n", i); - - frag = &skb_shinfo(skb)->frags[i]; - offset = 0; - - for (datalen = skb_frag_size(frag); datalen; ) { - len = min_t(unsigned int, datalen, - XGBE_TX_MAX_BUF_SIZE); - - skb_dma = skb_frag_dma_map(pdata->dev, frag, offset, - len, DMA_TO_DEVICE); - if (dma_mapping_error(pdata->dev, skb_dma)) { - netdev_alert(pdata->netdev, - "skb_frag_dma_map failed\n"); - goto err_out; - } - rdata->skb_dma = skb_dma; - rdata->skb_dma_len = len; - rdata->mapped_as_page = 1; - netif_dbg(pdata, tx_queued, pdata->netdev, - "skb frag: index=%u, dma=%pad, len=%u\n", - cur_index, &skb_dma, len); - - datalen -= len; - offset += len; - - packet->length += len; - - cur_index++; - rdata = XGBE_GET_DESC_DATA(ring, cur_index); - } - } - - /* Save the skb address in the last entry. We always have some data + /* Save the mbuf address in the last entry. We always have some data * that has been mapped so rdata is always advanced past the last * piece of mapped data - use the entry pointed to by cur_index - 1. */ rdata = XGBE_GET_DESC_DATA(ring, cur_index - 1); - rdata->skb = skb; + rdata->mb = m; + rdata->mbuf_free = 1; /* Save the number of descriptor entries used */ packet->rdesc_count = cur_index - start_index; DBGPR("<--xgbe_map_tx_skb: count=%u\n", packet->rdesc_count); return packet->rdesc_count; - -err_out: - while (start_index < cur_index) { - rdata = XGBE_GET_DESC_DATA(ring, start_index++); - xgbe_unmap_rdata(pdata, rdata); - } - - DBGPR("<--xgbe_map_tx_skb: count=0\n"); - - return 0; } void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *desc_if) { DBGPR("-->xgbe_init_function_ptrs_desc\n"); desc_if->alloc_ring_resources = xgbe_alloc_ring_resources; desc_if->free_ring_resources = xgbe_free_ring_resources; desc_if->map_tx_skb = xgbe_map_tx_skb; desc_if->map_rx_buffer = xgbe_map_rx_buffer; desc_if->unmap_rdata = xgbe_unmap_rdata; desc_if->wrapper_tx_desc_init = xgbe_wrapper_tx_descriptor_init; desc_if->wrapper_rx_desc_init = xgbe_wrapper_rx_descriptor_init; DBGPR("<--xgbe_init_function_ptrs_desc\n"); } Property changes on: head/sys/dev/axgbe/xgbe-desc.c ___________________________________________________________________ Deleted: fbsd:nokeywords ## -1 +0,0 ## -yes \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/dev/axgbe/xgbe-dev.c =================================================================== --- head/sys/dev/axgbe/xgbe-dev.c (revision 313767) +++ head/sys/dev/axgbe/xgbe-dev.c (revision 313768) @@ -1,2988 +1,2307 @@ /* * AMD 10Gb Ethernet driver * * This file is available to you under your choice of the following two * licenses: * * License 1: GPLv2 * * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. * * This file is free software; you may copy, redistribute and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 2 of the License, or (at * your option) any later version. * * This file is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see . * * This file incorporates work covered by the following copyright and * permission notice: * The Synopsys DWC ETHER XGMAC Software Driver and documentation * (hereinafter "Software") is an unsupported proprietary work of Synopsys, * Inc. unless otherwise expressly agreed to in writing between Synopsys * and you. * * The Software IS NOT an item of Licensed Software or Licensed Product * under any End User Software License Agreement or Agreement for Licensed * Product with Synopsys or any supplement thereto. Permission is hereby * granted, free of charge, to any person obtaining a copy of this software * annotated with this license and the Software, to deal in the Software * without restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished * to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * * License 2: Modified BSD * * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Advanced Micro Devices, Inc. nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * This file incorporates work covered by the following copyright and * permission notice: * The Synopsys DWC ETHER XGMAC Software Driver and documentation * (hereinafter "Software") is an unsupported proprietary work of Synopsys, * Inc. unless otherwise expressly agreed to in writing between Synopsys * and you. * * The Software IS NOT an item of Licensed Software or Licensed Product * under any End User Software License Agreement or Agreement for Licensed * Product with Synopsys or any supplement thereto. Permission is hereby * granted, free of charge, to any person obtaining a copy of this software * annotated with this license and the Software, to deal in the Software * without restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished * to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ -#include -#include -#include -#include -#include +#include +__FBSDID("$FreeBSD$"); +#include +#include + #include "xgbe.h" #include "xgbe-common.h" +#include +#include + static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata, unsigned int usec) { unsigned long rate; unsigned int ret; DBGPR("-->xgbe_usec_to_riwt\n"); rate = pdata->sysclk_rate; /* * Convert the input usec value to the watchdog timer value. Each * watchdog timer value is equivalent to 256 clock cycles. * Calculate the required value as: * ( usec * ( system_clock_mhz / 10^6 ) / 256 */ ret = (usec * (rate / 1000000)) / 256; DBGPR("<--xgbe_usec_to_riwt\n"); return ret; } static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata, unsigned int riwt) { unsigned long rate; unsigned int ret; DBGPR("-->xgbe_riwt_to_usec\n"); rate = pdata->sysclk_rate; /* * Convert the input watchdog timer value to the usec value. Each * watchdog timer value is equivalent to 256 clock cycles. * Calculate the required value as: * ( riwt * 256 ) / ( system_clock_mhz / 10^6 ) */ ret = (riwt * 256) / (rate / 1000000); DBGPR("<--xgbe_riwt_to_usec\n"); return ret; } static int xgbe_config_pblx8(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; unsigned int i; channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, PBLX8, pdata->pblx8); return 0; } static int xgbe_get_tx_pbl_val(struct xgbe_prv_data *pdata) { return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_TCR, PBL); } static int xgbe_config_tx_pbl_val(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; unsigned int i; channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { if (!channel->tx_ring) break; XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, PBL, pdata->tx_pbl); } return 0; } static int xgbe_get_rx_pbl_val(struct xgbe_prv_data *pdata) { return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_RCR, PBL); } static int xgbe_config_rx_pbl_val(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; unsigned int i; channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { if (!channel->rx_ring) break; XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, PBL, pdata->rx_pbl); } return 0; } static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; unsigned int i; channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { if (!channel->tx_ring) break; XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, OSP, pdata->tx_osp_mode); } return 0; } static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val) { unsigned int i; for (i = 0; i < pdata->rx_q_count; i++) XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val); return 0; } static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val) { unsigned int i; for (i = 0; i < pdata->tx_q_count; i++) XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val); return 0; } static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata, unsigned int val) { unsigned int i; for (i = 0; i < pdata->rx_q_count; i++) XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val); return 0; } static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata, unsigned int val) { unsigned int i; for (i = 0; i < pdata->tx_q_count; i++) XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val); return 0; } static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; unsigned int i; channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { if (!channel->rx_ring) break; XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RIWT, RWT, pdata->rx_riwt); } return 0; } static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata) { return 0; } static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; unsigned int i; channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { if (!channel->rx_ring) break; XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, RBSZ, pdata->rx_buf_size); } } static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; unsigned int i; channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { if (!channel->tx_ring) break; XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, TSE, 1); } } static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; unsigned int i; channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { if (!channel->rx_ring) break; XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, SPH, 1); } XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE); } -static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type, - unsigned int index, unsigned int val) -{ - unsigned int wait; - int ret = 0; - - mutex_lock(&pdata->rss_mutex); - - if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) { - ret = -EBUSY; - goto unlock; - } - - XGMAC_IOWRITE(pdata, MAC_RSSDR, val); - - XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index); - XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type); - XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0); - XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1); - - wait = 1000; - while (wait--) { - if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) - goto unlock; - - usleep_range(1000, 1500); - } - - ret = -EBUSY; - -unlock: - mutex_unlock(&pdata->rss_mutex); - - return ret; -} - -static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata) -{ - unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32); - unsigned int *key = (unsigned int *)&pdata->rss_key; - int ret; - - while (key_regs--) { - ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE, - key_regs, *key++); - if (ret) - return ret; - } - - return 0; -} - -static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata) -{ - unsigned int i; - int ret; - - for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) { - ret = xgbe_write_rss_reg(pdata, - XGBE_RSS_LOOKUP_TABLE_TYPE, i, - pdata->rss_table[i]); - if (ret) - return ret; - } - - return 0; -} - -static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key) -{ - memcpy(pdata->rss_key, key, sizeof(pdata->rss_key)); - - return xgbe_write_rss_hash_key(pdata); -} - -static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata, - const u32 *table) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) - XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]); - - return xgbe_write_rss_lookup_table(pdata); -} - -static int xgbe_enable_rss(struct xgbe_prv_data *pdata) -{ - int ret; - - if (!pdata->hw_feat.rss) - return -EOPNOTSUPP; - - /* Program the hash key */ - ret = xgbe_write_rss_hash_key(pdata); - if (ret) - return ret; - - /* Program the lookup table */ - ret = xgbe_write_rss_lookup_table(pdata); - if (ret) - return ret; - - /* Set the RSS options */ - XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); - - /* Enable RSS */ - XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1); - - return 0; -} - static int xgbe_disable_rss(struct xgbe_prv_data *pdata) { if (!pdata->hw_feat.rss) return -EOPNOTSUPP; XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0); return 0; } static void xgbe_config_rss(struct xgbe_prv_data *pdata) { - int ret; if (!pdata->hw_feat.rss) return; - if (pdata->netdev->features & NETIF_F_RXHASH) - ret = xgbe_enable_rss(pdata); - else - ret = xgbe_disable_rss(pdata); - - if (ret) - netdev_err(pdata->netdev, - "error configuring RSS, RSS disabled\n"); + xgbe_disable_rss(pdata); } static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata) { unsigned int max_q_count, q_count; unsigned int reg, reg_val; unsigned int i; /* Clear MTL flow control */ for (i = 0; i < pdata->rx_q_count; i++) XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0); /* Clear MAC flow control */ max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); reg = MAC_Q0TFCR; for (i = 0; i < q_count; i++) { reg_val = XGMAC_IOREAD(pdata, reg); XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0); XGMAC_IOWRITE(pdata, reg, reg_val); reg += MAC_QTFCR_INC; } return 0; } static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata) { - struct ieee_pfc *pfc = pdata->pfc; - struct ieee_ets *ets = pdata->ets; unsigned int max_q_count, q_count; unsigned int reg, reg_val; unsigned int i; /* Set MTL flow control */ for (i = 0; i < pdata->rx_q_count; i++) { - unsigned int ehfc = 0; - - if (pfc && ets) { - unsigned int prio; - - for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) { - unsigned int tc; - - /* Does this queue handle the priority? */ - if (pdata->prio2q_map[prio] != i) - continue; - - /* Get the Traffic Class for this priority */ - tc = ets->prio_tc[prio]; - - /* Check if flow control should be enabled */ - if (pfc->pfc_en & (1 << tc)) { - ehfc = 1; - break; - } - } - } else { - ehfc = 1; - } - - XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc); - - netif_dbg(pdata, drv, pdata->netdev, - "flow control %s for RXq%u\n", - ehfc ? "enabled" : "disabled", i); + XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 1); } /* Set MAC flow control */ max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); reg = MAC_Q0TFCR; for (i = 0; i < q_count; i++) { reg_val = XGMAC_IOREAD(pdata, reg); /* Enable transmit flow control */ XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1); /* Set pause time */ XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff); XGMAC_IOWRITE(pdata, reg, reg_val); reg += MAC_QTFCR_INC; } return 0; } static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata) { XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0); return 0; } static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata) { XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1); return 0; } static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata) { - struct ieee_pfc *pfc = pdata->pfc; - if (pdata->tx_pause || (pfc && pfc->pfc_en)) + if (pdata->tx_pause) xgbe_enable_tx_flow_control(pdata); else xgbe_disable_tx_flow_control(pdata); return 0; } static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata) { - struct ieee_pfc *pfc = pdata->pfc; - if (pdata->rx_pause || (pfc && pfc->pfc_en)) + if (pdata->rx_pause) xgbe_enable_rx_flow_control(pdata); else xgbe_disable_rx_flow_control(pdata); return 0; } static void xgbe_config_flow_control(struct xgbe_prv_data *pdata) { - struct ieee_pfc *pfc = pdata->pfc; xgbe_config_tx_flow_control(pdata); xgbe_config_rx_flow_control(pdata); - XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, - (pfc && pfc->pfc_en) ? 1 : 0); + XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); } static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; unsigned int dma_ch_isr, dma_ch_ier; unsigned int i; channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { /* Clear all the interrupts which are set */ dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR); XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr); /* Clear all interrupt enable bits */ dma_ch_ier = 0; /* Enable following interrupts * NIE - Normal Interrupt Summary Enable * AIE - Abnormal Interrupt Summary Enable * FBEE - Fatal Bus Error Enable */ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, NIE, 1); XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, AIE, 1); XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1); if (channel->tx_ring) { /* Enable the following Tx interrupts * TIE - Transmit Interrupt Enable (unless using * per channel interrupts) */ if (!pdata->per_channel_irq) XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1); } if (channel->rx_ring) { /* Enable following Rx interrupts * RBUE - Receive Buffer Unavailable Enable * RIE - Receive Interrupt Enable (unless using * per channel interrupts) */ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1); if (!pdata->per_channel_irq) XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1); } XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier); } } static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata) { unsigned int mtl_q_isr; unsigned int q_count, i; q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt); for (i = 0; i < q_count; i++) { /* Clear all the interrupts which are set */ mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR); XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr); /* No MTL interrupts to be enabled */ XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0); } } static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata) { unsigned int mac_ier = 0; /* Enable Timestamp interrupt */ XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1); XGMAC_IOWRITE(pdata, MAC_IER, mac_ier); /* Enable all counter interrupts */ XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff); XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff); } static int xgbe_set_gmii_speed(struct xgbe_prv_data *pdata) { if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0x3) return 0; XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x3); return 0; } static int xgbe_set_gmii_2500_speed(struct xgbe_prv_data *pdata) { if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0x2) return 0; XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x2); return 0; } static int xgbe_set_xgmii_speed(struct xgbe_prv_data *pdata) { if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0) return 0; XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0); return 0; } static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata) { /* Put the VLAN tag in the Rx descriptor */ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1); /* Don't check the VLAN type */ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1); /* Check only C-TAG (0x8100) packets */ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0); /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0); /* Enable VLAN tag stripping */ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3); return 0; } static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata) { XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0); return 0; } static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata) { /* Enable VLAN filtering */ XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1); /* Enable VLAN Hash Table filtering */ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1); /* Disable VLAN tag inverse matching */ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0); /* Only filter on the lower 12-bits of the VLAN tag */ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1); /* In order for the VLAN Hash Table filtering to be effective, * the VLAN tag identifier in the VLAN Tag Register must not * be zero. Set the VLAN tag identifier to "1" to enable the * VLAN Hash Table filtering. This implies that a VLAN tag of * 1 will always pass filtering. */ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1); return 0; } static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata) { /* Disable VLAN filtering */ XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0); return 0; } -static u32 xgbe_vid_crc32_le(__le16 vid_le) -{ - u32 poly = 0xedb88320; /* CRCPOLY_LE */ - u32 crc = ~0; - u32 temp = 0; - unsigned char *data = (unsigned char *)&vid_le; - unsigned char data_byte = 0; - int i, bits; - - bits = get_bitmask_order(VLAN_VID_MASK); - for (i = 0; i < bits; i++) { - if ((i % 8) == 0) - data_byte = data[i / 8]; - - temp = ((crc & 1) ^ data_byte) & 1; - crc >>= 1; - data_byte >>= 1; - - if (temp) - crc ^= poly; - } - - return crc; -} - static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata) { - u32 crc; - u16 vid; - __le16 vid_le; u16 vlan_hash_table = 0; - /* Generate the VLAN Hash Table value */ - for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) { - /* Get the CRC32 value of the VLAN ID */ - vid_le = cpu_to_le16(vid); - crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28; - - vlan_hash_table |= (1 << crc); - } - /* Set the VLAN Hash Table filtering register */ XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table); return 0; } static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata, unsigned int enable) { unsigned int val = enable ? 1 : 0; if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val) return 0; - netif_dbg(pdata, drv, pdata->netdev, "%s promiscuous mode\n", - enable ? "entering" : "leaving"); XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val); /* Hardware will still perform VLAN filtering in promiscuous mode */ - if (enable) { - xgbe_disable_rx_vlan_filtering(pdata); - } else { - if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) - xgbe_enable_rx_vlan_filtering(pdata); - } + xgbe_disable_rx_vlan_filtering(pdata); return 0; } static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata, unsigned int enable) { unsigned int val = enable ? 1 : 0; if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val) return 0; - netif_dbg(pdata, drv, pdata->netdev, "%s allmulti mode\n", - enable ? "entering" : "leaving"); XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val); return 0; } static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata, - struct netdev_hw_addr *ha, unsigned int *mac_reg) + char *addr, unsigned int *mac_reg) { unsigned int mac_addr_hi, mac_addr_lo; u8 *mac_addr; mac_addr_lo = 0; mac_addr_hi = 0; - if (ha) { + if (addr) { mac_addr = (u8 *)&mac_addr_lo; - mac_addr[0] = ha->addr[0]; - mac_addr[1] = ha->addr[1]; - mac_addr[2] = ha->addr[2]; - mac_addr[3] = ha->addr[3]; + mac_addr[0] = addr[0]; + mac_addr[1] = addr[1]; + mac_addr[2] = addr[2]; + mac_addr[3] = addr[3]; mac_addr = (u8 *)&mac_addr_hi; - mac_addr[0] = ha->addr[4]; - mac_addr[1] = ha->addr[5]; + mac_addr[0] = addr[4]; + mac_addr[1] = addr[5]; - netif_dbg(pdata, drv, pdata->netdev, - "adding mac address %pM at %#x\n", - ha->addr, *mac_reg); - XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1); } XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi); *mac_reg += MAC_MACA_INC; XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo); *mac_reg += MAC_MACA_INC; } static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata) { - struct net_device *netdev = pdata->netdev; - struct netdev_hw_addr *ha; unsigned int mac_reg; unsigned int addn_macs; mac_reg = MAC_MACA1HR; addn_macs = pdata->hw_feat.addn_mac; - if (netdev_uc_count(netdev) > addn_macs) { - xgbe_set_promiscuous_mode(pdata, 1); - } else { - netdev_for_each_uc_addr(ha, netdev) { - xgbe_set_mac_reg(pdata, ha, &mac_reg); - addn_macs--; - } + xgbe_set_mac_reg(pdata, pdata->mac_addr, &mac_reg); + addn_macs--; - if (netdev_mc_count(netdev) > addn_macs) { - xgbe_set_all_multicast_mode(pdata, 1); - } else { - netdev_for_each_mc_addr(ha, netdev) { - xgbe_set_mac_reg(pdata, ha, &mac_reg); - addn_macs--; - } - } - } - /* Clear remaining additional MAC address entries */ while (addn_macs--) xgbe_set_mac_reg(pdata, NULL, &mac_reg); } -static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata) -{ - struct net_device *netdev = pdata->netdev; - struct netdev_hw_addr *ha; - unsigned int hash_reg; - unsigned int hash_table_shift, hash_table_count; - u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE]; - u32 crc; - unsigned int i; - - hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7); - hash_table_count = pdata->hw_feat.hash_table_size / 32; - memset(hash_table, 0, sizeof(hash_table)); - - /* Build the MAC Hash Table register values */ - netdev_for_each_uc_addr(ha, netdev) { - crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); - crc >>= hash_table_shift; - hash_table[crc >> 5] |= (1 << (crc & 0x1f)); - } - - netdev_for_each_mc_addr(ha, netdev) { - crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); - crc >>= hash_table_shift; - hash_table[crc >> 5] |= (1 << (crc & 0x1f)); - } - - /* Set the MAC Hash Table registers */ - hash_reg = MAC_HTR0; - for (i = 0; i < hash_table_count; i++) { - XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]); - hash_reg += MAC_HTR_INC; - } -} - static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata) { - if (pdata->hw_feat.hash_table_size) - xgbe_set_mac_hash_table(pdata); - else - xgbe_set_mac_addn_addrs(pdata); + xgbe_set_mac_addn_addrs(pdata); return 0; } static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, u8 *addr) { unsigned int mac_addr_hi, mac_addr_lo; mac_addr_hi = (addr[5] << 8) | (addr[4] << 0); mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | (addr[0] << 0); XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi); XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo); return 0; } static int xgbe_config_rx_mode(struct xgbe_prv_data *pdata) { - struct net_device *netdev = pdata->netdev; unsigned int pr_mode, am_mode; - pr_mode = ((netdev->flags & IFF_PROMISC) != 0); - am_mode = ((netdev->flags & IFF_ALLMULTI) != 0); + /* XXX */ + pr_mode = 0; + am_mode = 0; xgbe_set_promiscuous_mode(pdata, pr_mode); xgbe_set_all_multicast_mode(pdata, am_mode); xgbe_add_mac_addresses(pdata); return 0; } static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad, int mmd_reg) { unsigned long flags; unsigned int mmd_address; int mmd_data; if (mmd_reg & MII_ADDR_C45) mmd_address = mmd_reg & ~MII_ADDR_C45; else mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); /* The PCS registers are accessed using mmio. The underlying APB3 * management interface uses indirect addressing to access the MMD * register sets. This requires accessing of the PCS register in two * phases, an address phase and a data phase. * * The mmio interface is based on 32-bit offsets and values. All * register offsets must therefore be adjusted by left shifting the * offset 2 bits and reading 32 bits of data. */ spin_lock_irqsave(&pdata->xpcs_lock, flags); XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8); mmd_data = XPCS_IOREAD(pdata, (mmd_address & 0xff) << 2); spin_unlock_irqrestore(&pdata->xpcs_lock, flags); return mmd_data; } static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, int mmd_reg, int mmd_data) { unsigned int mmd_address; unsigned long flags; if (mmd_reg & MII_ADDR_C45) mmd_address = mmd_reg & ~MII_ADDR_C45; else mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); /* The PCS registers are accessed using mmio. The underlying APB3 * management interface uses indirect addressing to access the MMD * register sets. This requires accessing of the PCS register in two * phases, an address phase and a data phase. * * The mmio interface is based on 32-bit offsets and values. All * register offsets must therefore be adjusted by left shifting the * offset 2 bits and reading 32 bits of data. */ spin_lock_irqsave(&pdata->xpcs_lock, flags); XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8); XPCS_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data); spin_unlock_irqrestore(&pdata->xpcs_lock, flags); } static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc) { return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN); } static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata) { XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0); return 0; } static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata) { XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1); return 0; } static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata) { struct xgbe_ring_desc *rdesc = rdata->rdesc; /* Reset the Tx descriptor * Set buffer 1 (lo) address to zero * Set buffer 1 (hi) address to zero * Reset all other control bits (IC, TTSE, B2L & B1L) * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc) */ rdesc->desc0 = 0; rdesc->desc1 = 0; rdesc->desc2 = 0; rdesc->desc3 = 0; - /* Make sure ownership is written to the descriptor */ - dma_wmb(); + dsb(sy); } static void xgbe_tx_desc_init(struct xgbe_channel *channel) { struct xgbe_ring *ring = channel->tx_ring; struct xgbe_ring_data *rdata; int i; int start_index = ring->cur; DBGPR("-->tx_desc_init\n"); /* Initialze all descriptors */ for (i = 0; i < ring->rdesc_count; i++) { rdata = XGBE_GET_DESC_DATA(ring, i); /* Initialize Tx descriptor */ xgbe_tx_desc_reset(rdata); } /* Update the total number of Tx descriptors */ XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1); /* Update the starting address of descriptor ring */ rdata = XGBE_GET_DESC_DATA(ring, start_index); XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI, - upper_32_bits(rdata->rdesc_dma)); + upper_32_bits(rdata->rdata_paddr)); XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO, - lower_32_bits(rdata->rdesc_dma)); + lower_32_bits(rdata->rdata_paddr)); DBGPR("<--tx_desc_init\n"); } static void xgbe_rx_desc_reset(struct xgbe_prv_data *pdata, struct xgbe_ring_data *rdata, unsigned int index) { struct xgbe_ring_desc *rdesc = rdata->rdesc; - unsigned int rx_usecs = pdata->rx_usecs; - unsigned int rx_frames = pdata->rx_frames; unsigned int inte; - dma_addr_t hdr_dma, buf_dma; - if (!rx_usecs && !rx_frames) { - /* No coalescing, interrupt for every descriptor */ - inte = 1; - } else { - /* Set interrupt based on Rx frame coalescing setting */ - if (rx_frames && !((index + 1) % rx_frames)) - inte = 1; - else - inte = 0; - } + inte = 1; /* Reset the Rx descriptor * Set buffer 1 (lo) address to header dma address (lo) * Set buffer 1 (hi) address to header dma address (hi) * Set buffer 2 (lo) address to buffer dma address (lo) * Set buffer 2 (hi) address to buffer dma address (hi) and * set control bits OWN and INTE */ - hdr_dma = rdata->rx.hdr.dma_base + rdata->rx.hdr.dma_off; - buf_dma = rdata->rx.buf.dma_base + rdata->rx.buf.dma_off; - rdesc->desc0 = cpu_to_le32(lower_32_bits(hdr_dma)); - rdesc->desc1 = cpu_to_le32(upper_32_bits(hdr_dma)); - rdesc->desc2 = cpu_to_le32(lower_32_bits(buf_dma)); - rdesc->desc3 = cpu_to_le32(upper_32_bits(buf_dma)); + rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->mbuf_hdr_paddr)); + rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->mbuf_hdr_paddr)); + rdesc->desc2 = cpu_to_le32(lower_32_bits(rdata->mbuf_data_paddr)); + rdesc->desc3 = cpu_to_le32(upper_32_bits(rdata->mbuf_data_paddr)); XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, inte); - /* Since the Rx DMA engine is likely running, make sure everything - * is written to the descriptor(s) before setting the OWN bit - * for the descriptor - */ - dma_wmb(); + dsb(sy); XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1); - /* Make sure ownership is written to the descriptor */ - dma_wmb(); + dsb(sy); } static void xgbe_rx_desc_init(struct xgbe_channel *channel) { struct xgbe_prv_data *pdata = channel->pdata; struct xgbe_ring *ring = channel->rx_ring; struct xgbe_ring_data *rdata; unsigned int start_index = ring->cur; unsigned int i; DBGPR("-->rx_desc_init\n"); /* Initialize all descriptors */ for (i = 0; i < ring->rdesc_count; i++) { rdata = XGBE_GET_DESC_DATA(ring, i); /* Initialize Rx descriptor */ xgbe_rx_desc_reset(pdata, rdata, i); } + bus_dmamap_sync(ring->rdesc_dmat, ring->rdesc_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + /* Update the total number of Rx descriptors */ XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1); /* Update the starting address of descriptor ring */ rdata = XGBE_GET_DESC_DATA(ring, start_index); XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI, - upper_32_bits(rdata->rdesc_dma)); + upper_32_bits(rdata->rdata_paddr)); XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO, - lower_32_bits(rdata->rdesc_dma)); + lower_32_bits(rdata->rdata_paddr)); /* Update the Rx Descriptor Tail Pointer */ rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1); XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO, - lower_32_bits(rdata->rdesc_dma)); + lower_32_bits(rdata->rdata_paddr)); DBGPR("<--rx_desc_init\n"); } -static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata, - unsigned int addend) -{ - /* Set the addend register value and tell the device */ - XGMAC_IOWRITE(pdata, MAC_TSAR, addend); - XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); - - /* Wait for addend update to complete */ - while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) - udelay(5); -} - -static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec, - unsigned int nsec) -{ - /* Set the time values and tell the device */ - XGMAC_IOWRITE(pdata, MAC_STSUR, sec); - XGMAC_IOWRITE(pdata, MAC_STNUR, nsec); - XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); - - /* Wait for time update to complete */ - while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) - udelay(5); -} - -static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata) -{ - u64 nsec; - - nsec = XGMAC_IOREAD(pdata, MAC_STSR); - nsec *= NSEC_PER_SEC; - nsec += XGMAC_IOREAD(pdata, MAC_STNR); - - return nsec; -} - -static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata) -{ - unsigned int tx_snr; - u64 nsec; - - tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR); - if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) - return 0; - - nsec = XGMAC_IOREAD(pdata, MAC_TXSSR); - nsec *= NSEC_PER_SEC; - nsec += tx_snr; - - return nsec; -} - -static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet, - struct xgbe_ring_desc *rdesc) -{ - u64 nsec; - - if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) && - !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) { - nsec = le32_to_cpu(rdesc->desc1); - nsec <<= 32; - nsec |= le32_to_cpu(rdesc->desc0); - if (nsec != 0xffffffffffffffffULL) { - packet->rx_tstamp = nsec; - XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, - RX_TSTAMP, 1); - } - } -} - -static int xgbe_config_tstamp(struct xgbe_prv_data *pdata, - unsigned int mac_tscr) -{ - /* Set one nano-second accuracy */ - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1); - - /* Set fine timestamp update */ - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1); - - /* Overwrite earlier timestamps */ - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1); - - XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); - - /* Exit if timestamping is not enabled */ - if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) - return 0; - - /* Initialize time registers */ - XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC); - XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC); - xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); - xgbe_set_tstamp_time(pdata, 0, 0); - - /* Initialize the timecounter */ - timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc, - ktime_to_ns(ktime_get_real())); - - return 0; -} - -static void xgbe_config_tc(struct xgbe_prv_data *pdata) -{ - unsigned int offset, queue, prio; - u8 i; - - netdev_reset_tc(pdata->netdev); - if (!pdata->num_tcs) - return; - - netdev_set_num_tc(pdata->netdev, pdata->num_tcs); - - for (i = 0, queue = 0, offset = 0; i < pdata->num_tcs; i++) { - while ((queue < pdata->tx_q_count) && - (pdata->q2tc_map[queue] == i)) - queue++; - - netif_dbg(pdata, drv, pdata->netdev, "TC%u using TXq%u-%u\n", - i, offset, queue - 1); - netdev_set_tc_queue(pdata->netdev, i, queue - offset, offset); - offset = queue; - } - - if (!pdata->ets) - return; - - for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) - netdev_set_prio_tc_map(pdata->netdev, prio, - pdata->ets->prio_tc[prio]); -} - -static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata) -{ - struct ieee_ets *ets = pdata->ets; - unsigned int total_weight, min_weight, weight; - unsigned int mask, reg, reg_val; - unsigned int i, prio; - - if (!ets) - return; - - /* Set Tx to deficit weighted round robin scheduling algorithm (when - * traffic class is using ETS algorithm) - */ - XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR); - - /* Set Traffic Class algorithms */ - total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt; - min_weight = total_weight / 100; - if (!min_weight) - min_weight = 1; - - for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { - /* Map the priorities to the traffic class */ - mask = 0; - for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) { - if (ets->prio_tc[prio] == i) - mask |= (1 << prio); - } - mask &= 0xff; - - netif_dbg(pdata, drv, pdata->netdev, "TC%u PRIO mask=%#x\n", - i, mask); - reg = MTL_TCPM0R + (MTL_TCPM_INC * (i / MTL_TCPM_TC_PER_REG)); - reg_val = XGMAC_IOREAD(pdata, reg); - - reg_val &= ~(0xff << ((i % MTL_TCPM_TC_PER_REG) << 3)); - reg_val |= (mask << ((i % MTL_TCPM_TC_PER_REG) << 3)); - - XGMAC_IOWRITE(pdata, reg, reg_val); - - /* Set the traffic class algorithm */ - switch (ets->tc_tsa[i]) { - case IEEE_8021QAZ_TSA_STRICT: - netif_dbg(pdata, drv, pdata->netdev, - "TC%u using SP\n", i); - XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, - MTL_TSA_SP); - break; - case IEEE_8021QAZ_TSA_ETS: - weight = total_weight * ets->tc_tx_bw[i] / 100; - weight = clamp(weight, min_weight, total_weight); - - netif_dbg(pdata, drv, pdata->netdev, - "TC%u using DWRR (weight %u)\n", i, weight); - XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, - MTL_TSA_ETS); - XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, - weight); - break; - } - } - - xgbe_config_tc(pdata); -} - -static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata) -{ - xgbe_config_flow_control(pdata); -} - static void xgbe_tx_start_xmit(struct xgbe_channel *channel, struct xgbe_ring *ring) { - struct xgbe_prv_data *pdata = channel->pdata; struct xgbe_ring_data *rdata; - /* Make sure everything is written before the register write */ - wmb(); - /* Issue a poll command to Tx DMA by writing address * of next immediate free descriptor */ rdata = XGBE_GET_DESC_DATA(ring, ring->cur); XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO, - lower_32_bits(rdata->rdesc_dma)); + lower_32_bits(rdata->rdata_paddr)); - /* Start the Tx timer */ - if (pdata->tx_usecs && !channel->tx_timer_active) { - channel->tx_timer_active = 1; - mod_timer(&channel->tx_timer, - jiffies + usecs_to_jiffies(pdata->tx_usecs)); - } - ring->tx.xmit_more = 0; } static void xgbe_dev_xmit(struct xgbe_channel *channel) { struct xgbe_prv_data *pdata = channel->pdata; struct xgbe_ring *ring = channel->tx_ring; struct xgbe_ring_data *rdata; struct xgbe_ring_desc *rdesc; struct xgbe_packet_data *packet = &ring->packet_data; - unsigned int csum, tso, vlan; - unsigned int tso_context, vlan_context; unsigned int tx_set_ic; int start_index = ring->cur; int cur_index = ring->cur; int i; DBGPR("-->xgbe_dev_xmit\n"); - csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, - CSUM_ENABLE); - tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, - TSO_ENABLE); - vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, - VLAN_CTAG); - - if (tso && (packet->mss != ring->tx.cur_mss)) - tso_context = 1; - else - tso_context = 0; - - if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag)) - vlan_context = 1; - else - vlan_context = 0; - /* Determine if an interrupt should be generated for this Tx: * Interrupt: * - Tx frame count exceeds the frame count setting * - Addition of Tx frame count to the frame count since the * last interrupt was set exceeds the frame count setting * No interrupt: * - No frame count setting specified (ethtool -C ethX tx-frames 0) * - Addition of Tx frame count to the frame count since the * last interrupt was set does not exceed the frame count setting */ ring->coalesce_count += packet->tx_packets; if (!pdata->tx_frames) tx_set_ic = 0; else if (packet->tx_packets > pdata->tx_frames) tx_set_ic = 1; else if ((ring->coalesce_count % pdata->tx_frames) < packet->tx_packets) tx_set_ic = 1; else tx_set_ic = 0; + tx_set_ic = 1; rdata = XGBE_GET_DESC_DATA(ring, cur_index); rdesc = rdata->rdesc; - /* Create a context descriptor if this is a TSO packet */ - if (tso_context || vlan_context) { - if (tso_context) { - netif_dbg(pdata, tx_queued, pdata->netdev, - "TSO context descriptor, mss=%u\n", - packet->mss); - - /* Set the MSS size */ - XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2, - MSS, packet->mss); - - /* Mark it as a CONTEXT descriptor */ - XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, - CTXT, 1); - - /* Indicate this descriptor contains the MSS */ - XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, - TCMSSV, 1); - - ring->tx.cur_mss = packet->mss; - } - - if (vlan_context) { - netif_dbg(pdata, tx_queued, pdata->netdev, - "VLAN context descriptor, ctag=%u\n", - packet->vlan_ctag); - - /* Mark it as a CONTEXT descriptor */ - XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, - CTXT, 1); - - /* Set the VLAN tag */ - XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, - VT, packet->vlan_ctag); - - /* Indicate this descriptor contains the VLAN tag */ - XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, - VLTV, 1); - - ring->tx.cur_vlan_ctag = packet->vlan_ctag; - } - - cur_index++; - rdata = XGBE_GET_DESC_DATA(ring, cur_index); - rdesc = rdata->rdesc; - } - /* Update buffer address (for TSO this is the header) */ - rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); - rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); + rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->mbuf_data_paddr)); + rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->mbuf_data_paddr)); /* Update the buffer length */ XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, - rdata->skb_dma_len); + rdata->mbuf_len); - /* VLAN tag insertion check */ - if (vlan) - XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR, - TX_NORMAL_DESC2_VLAN_INSERT); - /* Timestamp enablement check */ if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1); /* Mark it as First Descriptor */ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1); /* Mark it as a NORMAL descriptor */ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); /* Set OWN bit if not the first descriptor */ if (cur_index != start_index) XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); - if (tso) { - /* Enable TSO */ - XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1); - XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL, - packet->tcp_payload_len); - XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN, - packet->tcp_header_len / 4); + /* Enable CRC and Pad Insertion */ + XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0); - pdata->ext_stats.tx_tso_packets++; - } else { - /* Enable CRC and Pad Insertion */ - XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0); + /* Set the total length to be transmitted */ + XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL, + packet->length); - /* Enable HW CSUM */ - if (csum) - XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, - CIC, 0x3); - - /* Set the total length to be transmitted */ - XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL, - packet->length); - } - for (i = cur_index - start_index + 1; i < packet->rdesc_count; i++) { cur_index++; rdata = XGBE_GET_DESC_DATA(ring, cur_index); rdesc = rdata->rdesc; /* Update buffer address */ - rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); - rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); + rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->mbuf_data_paddr)); + rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->mbuf_data_paddr)); /* Update the buffer length */ XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, - rdata->skb_dma_len); + rdata->mbuf_len); /* Set OWN bit */ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); /* Mark it as NORMAL descriptor */ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); - - /* Enable HW CSUM */ - if (csum) - XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, - CIC, 0x3); } /* Set LAST bit for the last descriptor */ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1); /* Set IC bit based on Tx coalescing settings */ if (tx_set_ic) XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1); /* Save the Tx info to report back during cleanup */ rdata->tx.packets = packet->tx_packets; rdata->tx.bytes = packet->tx_bytes; + /* Sync the DMA buffers */ + bus_dmamap_sync(ring->rdesc_dmat, ring->rdesc_map, + BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(ring->mbuf_dmat, ring->mbuf_map, + BUS_DMASYNC_PREWRITE); + /* In case the Tx DMA engine is running, make sure everything * is written to the descriptor(s) before setting the OWN bit * for the first descriptor */ - dma_wmb(); /* Set OWN bit for the first descriptor */ rdata = XGBE_GET_DESC_DATA(ring, start_index); rdesc = rdata->rdesc; XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); - if (netif_msg_tx_queued(pdata)) - xgbe_dump_tx_desc(pdata, ring, start_index, - packet->rdesc_count, 1); + /* Sync to ensure the OWN bit was seen */ + bus_dmamap_sync(ring->rdesc_dmat, ring->rdesc_map, + BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); - /* Make sure ownership is written to the descriptor */ - smp_wmb(); - ring->cur = cur_index + 1; - if (!packet->skb->xmit_more || - netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev, - channel->queue_index))) - xgbe_tx_start_xmit(channel, ring); - else - ring->tx.xmit_more = 1; + xgbe_tx_start_xmit(channel, ring); DBGPR(" %s: descriptors %u to %u written\n", channel->name, start_index & (ring->rdesc_count - 1), (ring->cur - 1) & (ring->rdesc_count - 1)); DBGPR("<--xgbe_dev_xmit\n"); } static int xgbe_dev_read(struct xgbe_channel *channel) { - struct xgbe_prv_data *pdata = channel->pdata; struct xgbe_ring *ring = channel->rx_ring; struct xgbe_ring_data *rdata; struct xgbe_ring_desc *rdesc; struct xgbe_packet_data *packet = &ring->packet_data; - struct net_device *netdev = pdata->netdev; - unsigned int err, etlt, l34t; + unsigned int err, etlt; DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur); rdata = XGBE_GET_DESC_DATA(ring, ring->cur); rdesc = rdata->rdesc; + bus_dmamap_sync(ring->rdesc_dmat, ring->rdesc_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + + dsb(sy); + /* Check for data availability */ if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN)) return 1; - /* Make sure descriptor fields are read after reading the OWN bit */ - dma_rmb(); + dsb(sy); - if (netif_msg_rx_status(pdata)) - xgbe_dump_rx_desc(pdata, ring, ring->cur); - - if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) { - /* Timestamp Context Descriptor */ - xgbe_get_rx_tstamp(packet, rdesc); - - XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, - CONTEXT, 1); - XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, - CONTEXT_NEXT, 0); - return 0; - } - /* Normal Descriptor, be sure Context Descriptor bit is off */ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0); /* Indicate if a Context Descriptor is next */ if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA)) XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT_NEXT, 1); /* Get the header length */ if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) { rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2, RX_NORMAL_DESC2, HL); - if (rdata->rx.hdr_len) - pdata->ext_stats.rx_split_header_packets++; } - /* Get the RSS hash */ - if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) { - XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, - RSS_HASH, 1); - - packet->rss_hash = le32_to_cpu(rdesc->desc1); - - l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T); - switch (l34t) { - case RX_DESC3_L34T_IPV4_TCP: - case RX_DESC3_L34T_IPV4_UDP: - case RX_DESC3_L34T_IPV6_TCP: - case RX_DESC3_L34T_IPV6_UDP: - packet->rss_hash_type = PKT_HASH_TYPE_L4; - break; - default: - packet->rss_hash_type = PKT_HASH_TYPE_L3; - } - } - /* Get the packet length */ rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL); if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) { /* Not all the data has been transferred for this packet */ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, INCOMPLETE, 1); return 0; } /* This is the last of the data for this packet */ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, INCOMPLETE, 0); - /* Set checksum done indicator as appropriate */ - if (netdev->features & NETIF_F_RXCSUM) - XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, - CSUM_DONE, 1); - /* Check for errors (only valid in last descriptor) */ err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES); etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT); - netif_dbg(pdata, rx_status, netdev, "err=%u, etlt=%#x\n", err, etlt); - if (!err || !etlt) { - /* No error if err is 0 or etlt is 0 */ - if ((etlt == 0x09) && - (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) { - XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, - VLAN_CTAG, 1); - packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0, - RX_NORMAL_DESC0, - OVT); - netif_dbg(pdata, rx_status, netdev, "vlan-ctag=%#06x\n", - packet->vlan_ctag); - } - } else { + if (err && etlt) { if ((etlt == 0x05) || (etlt == 0x06)) XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CSUM_DONE, 0); else XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS, FRAME, 1); } + bus_dmamap_sync(ring->mbuf_dmat, rdata->mbuf_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name, ring->cur & (ring->rdesc_count - 1), ring->cur); return 0; } static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc) { /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */ return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT); } static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc) { /* Rx and Tx share LD bit, so check TDES3.LD bit */ return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD); } static int xgbe_enable_int(struct xgbe_channel *channel, enum xgbe_int int_id) { unsigned int dma_ch_ier; dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER); switch (int_id) { case XGMAC_INT_DMA_CH_SR_TI: XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1); break; case XGMAC_INT_DMA_CH_SR_TPS: XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 1); break; case XGMAC_INT_DMA_CH_SR_TBU: XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 1); break; case XGMAC_INT_DMA_CH_SR_RI: XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1); break; case XGMAC_INT_DMA_CH_SR_RBU: XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1); break; case XGMAC_INT_DMA_CH_SR_RPS: XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 1); break; case XGMAC_INT_DMA_CH_SR_TI_RI: XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1); XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1); break; case XGMAC_INT_DMA_CH_SR_FBE: XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1); break; case XGMAC_INT_DMA_ALL: dma_ch_ier |= channel->saved_ier; break; default: return -1; } XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier); return 0; } static int xgbe_disable_int(struct xgbe_channel *channel, enum xgbe_int int_id) { unsigned int dma_ch_ier; dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER); switch (int_id) { case XGMAC_INT_DMA_CH_SR_TI: XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0); break; case XGMAC_INT_DMA_CH_SR_TPS: XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 0); break; case XGMAC_INT_DMA_CH_SR_TBU: XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 0); break; case XGMAC_INT_DMA_CH_SR_RI: XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0); break; case XGMAC_INT_DMA_CH_SR_RBU: XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 0); break; case XGMAC_INT_DMA_CH_SR_RPS: XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 0); break; case XGMAC_INT_DMA_CH_SR_TI_RI: XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0); XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0); break; case XGMAC_INT_DMA_CH_SR_FBE: XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 0); break; case XGMAC_INT_DMA_ALL: channel->saved_ier = dma_ch_ier & XGBE_DMA_INTERRUPT_MASK; dma_ch_ier &= ~XGBE_DMA_INTERRUPT_MASK; break; default: return -1; } XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier); return 0; } static int xgbe_exit(struct xgbe_prv_data *pdata) { unsigned int count = 2000; DBGPR("-->xgbe_exit\n"); /* Issue a software reset */ XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1); - usleep_range(10, 15); + DELAY(10); /* Poll Until Poll Condition */ while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) - usleep_range(500, 600); + DELAY(500); if (!count) return -EBUSY; DBGPR("<--xgbe_exit\n"); return 0; } static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata) { unsigned int i, count; if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21) return 0; for (i = 0; i < pdata->tx_q_count; i++) XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1); /* Poll Until Poll Condition */ for (i = 0; i < pdata->tx_q_count; i++) { count = 2000; while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i, MTL_Q_TQOMR, FTQ)) - usleep_range(500, 600); + DELAY(500); if (!count) return -EBUSY; } return 0; } static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata) { /* Set enhanced addressing mode */ XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, EAME, 1); /* Set the System Bus mode */ XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, UNDEF, 1); XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN_256, 1); } static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata) { unsigned int arcache, awcache; arcache = 0; XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, pdata->arcache); XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, pdata->axdomain); XGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, pdata->arcache); XGMAC_SET_BITS(arcache, DMA_AXIARCR, TED, pdata->axdomain); XGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, pdata->arcache); XGMAC_SET_BITS(arcache, DMA_AXIARCR, THD, pdata->axdomain); XGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache); awcache = 0; XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, pdata->awcache); XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWD, pdata->axdomain); XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, pdata->awcache); XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, pdata->axdomain); XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, pdata->awcache); XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, pdata->axdomain); XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDC, pdata->awcache); XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDD, pdata->axdomain); XGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache); } static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata) { unsigned int i; /* Set Tx to weighted round robin scheduling algorithm */ XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR); /* Set Tx traffic classes to use WRR algorithm with equal weights */ for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, MTL_TSA_ETS); XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1); } /* Set Rx to strict priority algorithm */ XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP); } static unsigned int xgbe_calculate_per_queue_fifo(unsigned int fifo_size, unsigned int queue_count) { unsigned int q_fifo_size; unsigned int p_fifo; /* Calculate the configured fifo size */ q_fifo_size = 1 << (fifo_size + 7); /* The configured value may not be the actual amount of fifo RAM */ q_fifo_size = min_t(unsigned int, XGBE_FIFO_MAX, q_fifo_size); q_fifo_size = q_fifo_size / queue_count; /* Each increment in the queue fifo size represents 256 bytes of * fifo, with 0 representing 256 bytes. Distribute the fifo equally * between the queues. */ p_fifo = q_fifo_size / 256; if (p_fifo) p_fifo--; return p_fifo; } static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata) { unsigned int fifo_size; unsigned int i; fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.tx_fifo_size, pdata->tx_q_count); for (i = 0; i < pdata->tx_q_count; i++) XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo_size); - - netif_info(pdata, drv, pdata->netdev, - "%d Tx hardware queues, %d byte fifo per queue\n", - pdata->tx_q_count, ((fifo_size + 1) * 256)); } static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata) { unsigned int fifo_size; unsigned int i; fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.rx_fifo_size, pdata->rx_q_count); for (i = 0; i < pdata->rx_q_count; i++) XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo_size); - - netif_info(pdata, drv, pdata->netdev, - "%d Rx hardware queues, %d byte fifo per queue\n", - pdata->rx_q_count, ((fifo_size + 1) * 256)); } static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata) { unsigned int qptc, qptc_extra, queue; unsigned int prio_queues; unsigned int ppq, ppq_extra, prio; unsigned int mask; unsigned int i, j, reg, reg_val; /* Map the MTL Tx Queues to Traffic Classes * Note: Tx Queues >= Traffic Classes */ qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt; qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt; for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) { for (j = 0; j < qptc; j++) { - netif_dbg(pdata, drv, pdata->netdev, - "TXq%u mapped to TC%u\n", queue, i); XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, Q2TCMAP, i); pdata->q2tc_map[queue++] = i; } if (i < qptc_extra) { - netif_dbg(pdata, drv, pdata->netdev, - "TXq%u mapped to TC%u\n", queue, i); XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, Q2TCMAP, i); pdata->q2tc_map[queue++] = i; } } /* Map the 8 VLAN priority values to available MTL Rx queues */ prio_queues = min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, pdata->rx_q_count); ppq = IEEE_8021QAZ_MAX_TCS / prio_queues; ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues; reg = MAC_RQC2R; reg_val = 0; for (i = 0, prio = 0; i < prio_queues;) { mask = 0; for (j = 0; j < ppq; j++) { - netif_dbg(pdata, drv, pdata->netdev, - "PRIO%u mapped to RXq%u\n", prio, i); mask |= (1 << prio); pdata->prio2q_map[prio++] = i; } if (i < ppq_extra) { - netif_dbg(pdata, drv, pdata->netdev, - "PRIO%u mapped to RXq%u\n", prio, i); mask |= (1 << prio); pdata->prio2q_map[prio++] = i; } reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3)); if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues)) continue; XGMAC_IOWRITE(pdata, reg, reg_val); reg += MAC_RQC2_INC; reg_val = 0; } /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */ reg = MTL_RQDCM0R; reg_val = 0; for (i = 0; i < pdata->rx_q_count;) { reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3)); if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count)) continue; XGMAC_IOWRITE(pdata, reg, reg_val); reg += MTL_RQDCM_INC; reg_val = 0; } } static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata) { unsigned int i; for (i = 0; i < pdata->rx_q_count; i++) { /* Activate flow control when less than 4k left in fifo */ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, 2); /* De-activate flow control when more than 6k left in fifo */ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, 4); } } static void xgbe_config_mac_address(struct xgbe_prv_data *pdata) { - xgbe_set_mac_address(pdata, pdata->netdev->dev_addr); - /* Filtering is done using perfect filtering and hash filtering */ - if (pdata->hw_feat.hash_table_size) { - XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); - XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); - XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1); - } + xgbe_set_mac_address(pdata, IF_LLADDR(pdata->netdev)); } static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata) { unsigned int val; - val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0; + val = (if_getmtu(pdata->netdev) > XGMAC_STD_PACKET_MTU) ? 1 : 0; XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); } static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata) { switch (pdata->phy_speed) { case SPEED_10000: xgbe_set_xgmii_speed(pdata); break; case SPEED_2500: xgbe_set_gmii_2500_speed(pdata); break; case SPEED_1000: xgbe_set_gmii_speed(pdata); break; + case SPEED_UNKNOWN: + break; + default: + panic("TODO %s:%d\n", __FILE__, __LINE__); } } static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata) { - if (pdata->netdev->features & NETIF_F_RXCSUM) + if ((if_getcapenable(pdata->netdev) & IFCAP_RXCSUM) != 0) xgbe_enable_rx_csum(pdata); else xgbe_disable_rx_csum(pdata); } static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata) { /* Indicate that VLAN Tx CTAGs come from context descriptors */ XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); /* Set the current VLAN Hash Table register value */ xgbe_update_vlan_hash_table(pdata); - if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) - xgbe_enable_rx_vlan_filtering(pdata); - else - xgbe_disable_rx_vlan_filtering(pdata); - - if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) - xgbe_enable_rx_vlan_stripping(pdata); - else - xgbe_disable_rx_vlan_stripping(pdata); + xgbe_disable_rx_vlan_filtering(pdata); + xgbe_disable_rx_vlan_stripping(pdata); } static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo) { bool read_hi; u64 val; switch (reg_lo) { /* These registers are always 64 bit */ case MMC_TXOCTETCOUNT_GB_LO: case MMC_TXOCTETCOUNT_G_LO: case MMC_RXOCTETCOUNT_GB_LO: case MMC_RXOCTETCOUNT_G_LO: read_hi = true; break; default: read_hi = false; } val = XGMAC_IOREAD(pdata, reg_lo); if (read_hi) val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32); return val; } static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata) { struct xgbe_mmc_stats *stats = &pdata->mmc_stats; unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR); if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB)) stats->txoctetcount_gb += xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB)) stats->txframecount_gb += xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G)) stats->txbroadcastframes_g += xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G)) stats->txmulticastframes_g += xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB)) stats->tx64octets_gb += xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB)) stats->tx65to127octets_gb += xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB)) stats->tx128to255octets_gb += xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB)) stats->tx256to511octets_gb += xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB)) stats->tx512to1023octets_gb += xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB)) stats->tx1024tomaxoctets_gb += xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB)) stats->txunicastframes_gb += xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB)) stats->txmulticastframes_gb += xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB)) stats->txbroadcastframes_g += xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR)) stats->txunderflowerror += xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G)) stats->txoctetcount_g += xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G)) stats->txframecount_g += xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES)) stats->txpauseframes += xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G)) stats->txvlanframes_g += xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); } static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata) { struct xgbe_mmc_stats *stats = &pdata->mmc_stats; unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB)) stats->rxframecount_gb += xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB)) stats->rxoctetcount_gb += xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G)) stats->rxoctetcount_g += xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G)) stats->rxbroadcastframes_g += xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G)) stats->rxmulticastframes_g += xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR)) stats->rxcrcerror += xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR)) stats->rxrunterror += xgbe_mmc_read(pdata, MMC_RXRUNTERROR); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR)) stats->rxjabbererror += xgbe_mmc_read(pdata, MMC_RXJABBERERROR); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G)) stats->rxundersize_g += xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G)) stats->rxoversize_g += xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB)) stats->rx64octets_gb += xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB)) stats->rx65to127octets_gb += xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB)) stats->rx128to255octets_gb += xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB)) stats->rx256to511octets_gb += xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB)) stats->rx512to1023octets_gb += xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB)) stats->rx1024tomaxoctets_gb += xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G)) stats->rxunicastframes_g += xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR)) stats->rxlengtherror += xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE)) stats->rxoutofrangetype += xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES)) stats->rxpauseframes += xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW)) stats->rxfifooverflow += xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB)) stats->rxvlanframes_gb += xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR)) stats->rxwatchdogerror += xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); } static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata) { struct xgbe_mmc_stats *stats = &pdata->mmc_stats; /* Freeze counters */ XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); stats->txoctetcount_gb += xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); stats->txframecount_gb += xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); stats->txbroadcastframes_g += xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); stats->txmulticastframes_g += xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); stats->tx64octets_gb += xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); stats->tx65to127octets_gb += xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); stats->tx128to255octets_gb += xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); stats->tx256to511octets_gb += xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); stats->tx512to1023octets_gb += xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); stats->tx1024tomaxoctets_gb += xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); stats->txunicastframes_gb += xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); stats->txmulticastframes_gb += xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); stats->txbroadcastframes_g += xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); stats->txunderflowerror += xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); stats->txoctetcount_g += xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); stats->txframecount_g += xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); stats->txpauseframes += xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); stats->txvlanframes_g += xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); stats->rxframecount_gb += xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); stats->rxoctetcount_gb += xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); stats->rxoctetcount_g += xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); stats->rxbroadcastframes_g += xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); stats->rxmulticastframes_g += xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); stats->rxcrcerror += xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); stats->rxrunterror += xgbe_mmc_read(pdata, MMC_RXRUNTERROR); stats->rxjabbererror += xgbe_mmc_read(pdata, MMC_RXJABBERERROR); stats->rxundersize_g += xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); stats->rxoversize_g += xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); stats->rx64octets_gb += xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); stats->rx65to127octets_gb += xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); stats->rx128to255octets_gb += xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); stats->rx256to511octets_gb += xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); stats->rx512to1023octets_gb += xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); stats->rx1024tomaxoctets_gb += xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); stats->rxunicastframes_g += xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); stats->rxlengtherror += xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); stats->rxoutofrangetype += xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); stats->rxpauseframes += xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); stats->rxfifooverflow += xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); stats->rxvlanframes_gb += xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); stats->rxwatchdogerror += xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); /* Un-freeze counters */ XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); } static void xgbe_config_mmc(struct xgbe_prv_data *pdata) { /* Set counters to reset on read */ XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); /* Reset the counters */ XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1); } static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata, struct xgbe_channel *channel) { unsigned int tx_dsr, tx_pos, tx_qidx; unsigned int tx_status; unsigned long tx_timeout; /* Calculate the status register to read and the position within */ if (channel->queue_index < DMA_DSRX_FIRST_QUEUE) { tx_dsr = DMA_DSR0; tx_pos = (channel->queue_index * DMA_DSR_Q_WIDTH) + DMA_DSR0_TPS_START; } else { tx_qidx = channel->queue_index - DMA_DSRX_FIRST_QUEUE; tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC); tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) + DMA_DSRX_TPS_START; } /* The Tx engine cannot be stopped if it is actively processing * descriptors. Wait for the Tx engine to enter the stopped or * suspended state. Don't wait forever though... */ - tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ); - while (time_before(jiffies, tx_timeout)) { + tx_timeout = ticks + (XGBE_DMA_STOP_TIMEOUT * hz); + while (ticks < tx_timeout) { tx_status = XGMAC_IOREAD(pdata, tx_dsr); tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH); if ((tx_status == DMA_TPS_STOPPED) || (tx_status == DMA_TPS_SUSPENDED)) break; - usleep_range(500, 1000); + DELAY(500); } - - if (!time_before(jiffies, tx_timeout)) - netdev_info(pdata->netdev, - "timed out waiting for Tx DMA channel %u to stop\n", - channel->queue_index); } static void xgbe_enable_tx(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; unsigned int i; /* Enable each Tx DMA channel */ channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { if (!channel->tx_ring) break; XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1); } /* Enable each Tx queue */ for (i = 0; i < pdata->tx_q_count; i++) XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, MTL_Q_ENABLED); /* Enable MAC Tx */ XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); } static void xgbe_disable_tx(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; unsigned int i; /* Prepare for Tx DMA channel stop */ channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { if (!channel->tx_ring) break; xgbe_prepare_tx_stop(pdata, channel); } /* Disable MAC Tx */ XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); /* Disable each Tx queue */ for (i = 0; i < pdata->tx_q_count; i++) XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0); /* Disable each Tx DMA channel */ channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { if (!channel->tx_ring) break; XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0); } } static void xgbe_prepare_rx_stop(struct xgbe_prv_data *pdata, unsigned int queue) { unsigned int rx_status; unsigned long rx_timeout; /* The Rx engine cannot be stopped if it is actively processing * packets. Wait for the Rx queue to empty the Rx fifo. Don't * wait forever though... */ - rx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ); - while (time_before(jiffies, rx_timeout)) { + rx_timeout = ticks + (XGBE_DMA_STOP_TIMEOUT * hz); + while (ticks < rx_timeout) { rx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR); if ((XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, PRXQ) == 0) && (XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, RXQSTS) == 0)) break; - usleep_range(500, 1000); + DELAY(500); } - - if (!time_before(jiffies, rx_timeout)) - netdev_info(pdata->netdev, - "timed out waiting for Rx queue %u to empty\n", - queue); } static void xgbe_enable_rx(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; unsigned int reg_val, i; /* Enable each Rx DMA channel */ channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { if (!channel->rx_ring) break; XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1); } /* Enable each Rx queue */ reg_val = 0; for (i = 0; i < pdata->rx_q_count; i++) reg_val |= (0x02 << (i << 1)); XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); /* Enable MAC Rx */ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1); XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1); XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1); XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1); } static void xgbe_disable_rx(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; unsigned int i; /* Disable MAC Rx */ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0); XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0); XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0); XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0); /* Prepare for Rx DMA channel stop */ for (i = 0; i < pdata->rx_q_count; i++) xgbe_prepare_rx_stop(pdata, i); /* Disable each Rx queue */ XGMAC_IOWRITE(pdata, MAC_RQC0R, 0); /* Disable each Rx DMA channel */ channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { if (!channel->rx_ring) break; XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0); } } static void xgbe_powerup_tx(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; unsigned int i; /* Enable each Tx DMA channel */ channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { if (!channel->tx_ring) break; XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1); } /* Enable MAC Tx */ XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); } static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; unsigned int i; /* Prepare for Tx DMA channel stop */ channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { if (!channel->tx_ring) break; xgbe_prepare_tx_stop(pdata, channel); } /* Disable MAC Tx */ XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); /* Disable each Tx DMA channel */ channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { if (!channel->tx_ring) break; XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0); } } static void xgbe_powerup_rx(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; unsigned int i; /* Enable each Rx DMA channel */ channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { if (!channel->rx_ring) break; XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1); } } static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; unsigned int i; /* Disable each Rx DMA channel */ channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { if (!channel->rx_ring) break; XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0); } } static int xgbe_init(struct xgbe_prv_data *pdata) { struct xgbe_desc_if *desc_if = &pdata->desc_if; int ret; DBGPR("-->xgbe_init\n"); /* Flush Tx queues */ ret = xgbe_flush_tx_queues(pdata); if (ret) return ret; /* * Initialize DMA related features */ xgbe_config_dma_bus(pdata); xgbe_config_dma_cache(pdata); xgbe_config_osp_mode(pdata); xgbe_config_pblx8(pdata); xgbe_config_tx_pbl_val(pdata); xgbe_config_rx_pbl_val(pdata); xgbe_config_rx_coalesce(pdata); xgbe_config_tx_coalesce(pdata); xgbe_config_rx_buffer_size(pdata); xgbe_config_tso_mode(pdata); xgbe_config_sph_mode(pdata); xgbe_config_rss(pdata); desc_if->wrapper_tx_desc_init(pdata); desc_if->wrapper_rx_desc_init(pdata); xgbe_enable_dma_interrupts(pdata); /* * Initialize MTL related features */ xgbe_config_mtl_mode(pdata); xgbe_config_queue_mapping(pdata); xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode); xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode); xgbe_config_tx_threshold(pdata, pdata->tx_threshold); xgbe_config_rx_threshold(pdata, pdata->rx_threshold); xgbe_config_tx_fifo_size(pdata); xgbe_config_rx_fifo_size(pdata); xgbe_config_flow_control_threshold(pdata); /*TODO: Error Packet and undersized good Packet forwarding enable (FEP and FUP) */ - xgbe_config_dcb_tc(pdata); - xgbe_config_dcb_pfc(pdata); xgbe_enable_mtl_interrupts(pdata); /* * Initialize MAC related features */ xgbe_config_mac_address(pdata); xgbe_config_rx_mode(pdata); xgbe_config_jumbo_enable(pdata); xgbe_config_flow_control(pdata); xgbe_config_mac_speed(pdata); xgbe_config_checksum_offload(pdata); xgbe_config_vlan_support(pdata); xgbe_config_mmc(pdata); xgbe_enable_mac_interrupts(pdata); DBGPR("<--xgbe_init\n"); return 0; } void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if) { DBGPR("-->xgbe_init_function_ptrs\n"); hw_if->tx_complete = xgbe_tx_complete; hw_if->set_mac_address = xgbe_set_mac_address; hw_if->config_rx_mode = xgbe_config_rx_mode; hw_if->enable_rx_csum = xgbe_enable_rx_csum; hw_if->disable_rx_csum = xgbe_disable_rx_csum; hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping; hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping; hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering; hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering; hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table; hw_if->read_mmd_regs = xgbe_read_mmd_regs; hw_if->write_mmd_regs = xgbe_write_mmd_regs; hw_if->set_gmii_speed = xgbe_set_gmii_speed; hw_if->set_gmii_2500_speed = xgbe_set_gmii_2500_speed; hw_if->set_xgmii_speed = xgbe_set_xgmii_speed; hw_if->enable_tx = xgbe_enable_tx; hw_if->disable_tx = xgbe_disable_tx; hw_if->enable_rx = xgbe_enable_rx; hw_if->disable_rx = xgbe_disable_rx; hw_if->powerup_tx = xgbe_powerup_tx; hw_if->powerdown_tx = xgbe_powerdown_tx; hw_if->powerup_rx = xgbe_powerup_rx; hw_if->powerdown_rx = xgbe_powerdown_rx; hw_if->dev_xmit = xgbe_dev_xmit; hw_if->dev_read = xgbe_dev_read; hw_if->enable_int = xgbe_enable_int; hw_if->disable_int = xgbe_disable_int; hw_if->init = xgbe_init; hw_if->exit = xgbe_exit; /* Descriptor related Sequences have to be initialized here */ hw_if->tx_desc_init = xgbe_tx_desc_init; hw_if->rx_desc_init = xgbe_rx_desc_init; hw_if->tx_desc_reset = xgbe_tx_desc_reset; hw_if->rx_desc_reset = xgbe_rx_desc_reset; hw_if->is_last_desc = xgbe_is_last_desc; hw_if->is_context_desc = xgbe_is_context_desc; hw_if->tx_start_xmit = xgbe_tx_start_xmit; /* For FLOW ctrl */ hw_if->config_tx_flow_control = xgbe_config_tx_flow_control; hw_if->config_rx_flow_control = xgbe_config_rx_flow_control; /* For RX coalescing */ hw_if->config_rx_coalesce = xgbe_config_rx_coalesce; hw_if->config_tx_coalesce = xgbe_config_tx_coalesce; hw_if->usec_to_riwt = xgbe_usec_to_riwt; hw_if->riwt_to_usec = xgbe_riwt_to_usec; /* For RX and TX threshold config */ hw_if->config_rx_threshold = xgbe_config_rx_threshold; hw_if->config_tx_threshold = xgbe_config_tx_threshold; /* For RX and TX Store and Forward Mode config */ hw_if->config_rsf_mode = xgbe_config_rsf_mode; hw_if->config_tsf_mode = xgbe_config_tsf_mode; /* For TX DMA Operating on Second Frame config */ hw_if->config_osp_mode = xgbe_config_osp_mode; /* For RX and TX PBL config */ hw_if->config_rx_pbl_val = xgbe_config_rx_pbl_val; hw_if->get_rx_pbl_val = xgbe_get_rx_pbl_val; hw_if->config_tx_pbl_val = xgbe_config_tx_pbl_val; hw_if->get_tx_pbl_val = xgbe_get_tx_pbl_val; hw_if->config_pblx8 = xgbe_config_pblx8; /* For MMC statistics support */ hw_if->tx_mmc_int = xgbe_tx_mmc_int; hw_if->rx_mmc_int = xgbe_rx_mmc_int; hw_if->read_mmc_stats = xgbe_read_mmc_stats; - /* For PTP config */ - hw_if->config_tstamp = xgbe_config_tstamp; - hw_if->update_tstamp_addend = xgbe_update_tstamp_addend; - hw_if->set_tstamp_time = xgbe_set_tstamp_time; - hw_if->get_tstamp_time = xgbe_get_tstamp_time; - hw_if->get_tx_tstamp = xgbe_get_tx_tstamp; - - /* For Data Center Bridging config */ - hw_if->config_tc = xgbe_config_tc; - hw_if->config_dcb_tc = xgbe_config_dcb_tc; - hw_if->config_dcb_pfc = xgbe_config_dcb_pfc; - /* For Receive Side Scaling */ - hw_if->enable_rss = xgbe_enable_rss; hw_if->disable_rss = xgbe_disable_rss; - hw_if->set_rss_hash_key = xgbe_set_rss_hash_key; - hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table; DBGPR("<--xgbe_init_function_ptrs\n"); } Property changes on: head/sys/dev/axgbe/xgbe-dev.c ___________________________________________________________________ Deleted: fbsd:nokeywords ## -1 +0,0 ## -yes \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/dev/axgbe/xgbe-drv.c =================================================================== --- head/sys/dev/axgbe/xgbe-drv.c (revision 313767) +++ head/sys/dev/axgbe/xgbe-drv.c (revision 313768) @@ -1,2178 +1,1079 @@ /* * AMD 10Gb Ethernet driver * * This file is available to you under your choice of the following two * licenses: * * License 1: GPLv2 * * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. * * This file is free software; you may copy, redistribute and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 2 of the License, or (at * your option) any later version. * * This file is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see . * * This file incorporates work covered by the following copyright and * permission notice: * The Synopsys DWC ETHER XGMAC Software Driver and documentation * (hereinafter "Software") is an unsupported proprietary work of Synopsys, * Inc. unless otherwise expressly agreed to in writing between Synopsys * and you. * * The Software IS NOT an item of Licensed Software or Licensed Product * under any End User Software License Agreement or Agreement for Licensed * Product with Synopsys or any supplement thereto. Permission is hereby * granted, free of charge, to any person obtaining a copy of this software * annotated with this license and the Software, to deal in the Software * without restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished * to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * * License 2: Modified BSD * * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Advanced Micro Devices, Inc. nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * This file incorporates work covered by the following copyright and * permission notice: * The Synopsys DWC ETHER XGMAC Software Driver and documentation * (hereinafter "Software") is an unsupported proprietary work of Synopsys, * Inc. unless otherwise expressly agreed to in writing between Synopsys * and you. * * The Software IS NOT an item of Licensed Software or Licensed Product * under any End User Software License Agreement or Agreement for Licensed * Product with Synopsys or any supplement thereto. Permission is hereby * granted, free of charge, to any person obtaining a copy of this software * annotated with this license and the Software, to deal in the Software * without restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished * to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include +__FBSDID("$FreeBSD$"); +#include +#include + #include "xgbe.h" #include "xgbe-common.h" -static int xgbe_one_poll(struct napi_struct *, int); -static int xgbe_all_poll(struct napi_struct *, int); +static int xgbe_one_poll(struct xgbe_channel *channel, int budget); +static int xgbe_all_poll(struct xgbe_prv_data *pdata, int budget); static int xgbe_alloc_channels(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel_mem, *channel; struct xgbe_ring *tx_ring, *rx_ring; unsigned int count, i; int ret = -ENOMEM; count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count); - channel_mem = kcalloc(count, sizeof(struct xgbe_channel), GFP_KERNEL); - if (!channel_mem) - goto err_channel; + channel_mem = malloc(count * sizeof(struct xgbe_channel), M_AXGBE, + M_WAITOK | M_ZERO); + tx_ring = malloc(pdata->tx_ring_count * sizeof(struct xgbe_ring), + M_AXGBE, M_WAITOK | M_ZERO); + rx_ring = malloc(pdata->rx_ring_count * sizeof(struct xgbe_ring), + M_AXGBE, M_WAITOK | M_ZERO); - tx_ring = kcalloc(pdata->tx_ring_count, sizeof(struct xgbe_ring), - GFP_KERNEL); - if (!tx_ring) - goto err_tx_ring; - - rx_ring = kcalloc(pdata->rx_ring_count, sizeof(struct xgbe_ring), - GFP_KERNEL); - if (!rx_ring) - goto err_rx_ring; - for (i = 0, channel = channel_mem; i < count; i++, channel++) { snprintf(channel->name, sizeof(channel->name), "channel-%d", i); channel->pdata = pdata; channel->queue_index = i; - channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE + - (DMA_CH_INC * i); + channel->dma_tag = rman_get_bustag(pdata->xgmac_res); + bus_space_subregion(channel->dma_tag, + rman_get_bushandle(pdata->xgmac_res), + DMA_CH_BASE + (DMA_CH_INC * i), DMA_CH_INC, + &channel->dma_handle); if (pdata->per_channel_irq) { - /* Get the DMA interrupt (offset 1) */ - ret = platform_get_irq(pdata->pdev, i + 1); - if (ret < 0) { - netdev_err(pdata->netdev, - "platform_get_irq %u failed\n", - i + 1); + if (pdata->chan_irq_res[i] == NULL) goto err_irq; - } - channel->dma_irq = ret; + channel->dma_irq_res = pdata->chan_irq_res[i]; } if (i < pdata->tx_ring_count) { spin_lock_init(&tx_ring->lock); channel->tx_ring = tx_ring++; } if (i < pdata->rx_ring_count) { spin_lock_init(&rx_ring->lock); channel->rx_ring = rx_ring++; } - - netif_dbg(pdata, drv, pdata->netdev, - "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n", - channel->name, channel->dma_regs, channel->dma_irq, - channel->tx_ring, channel->rx_ring); } pdata->channel = channel_mem; pdata->channel_count = count; return 0; err_irq: - kfree(rx_ring); + free(rx_ring, M_AXGBE); + free(tx_ring, M_AXGBE); + free(channel_mem, M_AXGBE); -err_rx_ring: - kfree(tx_ring); - -err_tx_ring: - kfree(channel_mem); - -err_channel: return ret; } static void xgbe_free_channels(struct xgbe_prv_data *pdata) { if (!pdata->channel) return; - kfree(pdata->channel->rx_ring); - kfree(pdata->channel->tx_ring); - kfree(pdata->channel); + free(pdata->channel->rx_ring, M_AXGBE); + free(pdata->channel->tx_ring, M_AXGBE); + free(pdata->channel, M_AXGBE); pdata->channel = NULL; pdata->channel_count = 0; } static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring) { return (ring->rdesc_count - (ring->cur - ring->dirty)); } static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring) { return (ring->cur - ring->dirty); } static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel, struct xgbe_ring *ring, unsigned int count) { struct xgbe_prv_data *pdata = channel->pdata; if (count > xgbe_tx_avail_desc(ring)) { - netif_info(pdata, drv, pdata->netdev, - "Tx queue stopped, not enough descriptors available\n"); - netif_stop_subqueue(pdata->netdev, channel->queue_index); - ring->tx.queue_stopped = 1; - /* If we haven't notified the hardware because of xmit_more * support, tell it now */ if (ring->tx.xmit_more) pdata->hw_if.tx_start_xmit(channel, ring); - return NETDEV_TX_BUSY; + return EFBIG; } return 0; } -static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu) +static int xgbe_calc_rx_buf_size(struct ifnet *netdev, unsigned int mtu) { unsigned int rx_buf_size; if (mtu > XGMAC_JUMBO_PACKET_MTU) { - netdev_alert(netdev, "MTU exceeds maximum supported value\n"); return -EINVAL; } rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; - rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE); + rx_buf_size = MIN(XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE); rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) & ~(XGBE_RX_BUF_ALIGN - 1); return rx_buf_size; } static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata) { struct xgbe_hw_if *hw_if = &pdata->hw_if; struct xgbe_channel *channel; enum xgbe_int int_id; unsigned int i; channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { if (channel->tx_ring && channel->rx_ring) int_id = XGMAC_INT_DMA_CH_SR_TI_RI; else if (channel->tx_ring) int_id = XGMAC_INT_DMA_CH_SR_TI; else if (channel->rx_ring) int_id = XGMAC_INT_DMA_CH_SR_RI; else continue; hw_if->enable_int(channel, int_id); } } -static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata) +static void xgbe_isr(void *data) { - struct xgbe_hw_if *hw_if = &pdata->hw_if; - struct xgbe_channel *channel; - enum xgbe_int int_id; - unsigned int i; - - channel = pdata->channel; - for (i = 0; i < pdata->channel_count; i++, channel++) { - if (channel->tx_ring && channel->rx_ring) - int_id = XGMAC_INT_DMA_CH_SR_TI_RI; - else if (channel->tx_ring) - int_id = XGMAC_INT_DMA_CH_SR_TI; - else if (channel->rx_ring) - int_id = XGMAC_INT_DMA_CH_SR_RI; - else - continue; - - hw_if->disable_int(channel, int_id); - } -} - -static irqreturn_t xgbe_isr(int irq, void *data) -{ struct xgbe_prv_data *pdata = data; struct xgbe_hw_if *hw_if = &pdata->hw_if; struct xgbe_channel *channel; unsigned int dma_isr, dma_ch_isr; - unsigned int mac_isr, mac_tssr; + unsigned int mac_isr; unsigned int i; /* The DMA interrupt status register also reports MAC and MTL * interrupts. So for polling mode, we just need to check for * this register to be non-zero */ dma_isr = XGMAC_IOREAD(pdata, DMA_ISR); if (!dma_isr) - goto isr_done; + return; - netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr); - for (i = 0; i < pdata->channel_count; i++) { if (!(dma_isr & (1 << i))) continue; channel = pdata->channel + i; dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR); - netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n", - i, dma_ch_isr); /* The TI or RI interrupt bits may still be set even if using * per channel DMA interrupts. Check to be sure those are not * enabled before using the private data napi structure. */ if (!pdata->per_channel_irq && (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) || XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) { - if (napi_schedule_prep(&pdata->napi)) { - /* Disable Tx and Rx interrupts */ - xgbe_disable_rx_tx_ints(pdata); - - /* Turn on polling */ - __napi_schedule_irqoff(&pdata->napi); - } + xgbe_all_poll(pdata, 16); } if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU)) pdata->ext_stats.rx_buffer_unavailable++; /* Restart the device on a Fatal Bus Error */ if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE)) - schedule_work(&pdata->restart_work); + taskqueue_enqueue(taskqueue_thread, + &pdata->restart_work); /* Clear all interrupt signals */ XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr); } if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) { mac_isr = XGMAC_IOREAD(pdata, MAC_ISR); if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS)) hw_if->tx_mmc_int(pdata); if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS)) hw_if->rx_mmc_int(pdata); - - if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) { - mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR); - - if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) { - /* Read Tx Timestamp to clear interrupt */ - pdata->tx_tstamp = - hw_if->get_tx_tstamp(pdata); - queue_work(pdata->dev_workqueue, - &pdata->tx_tstamp_work); - } - } } - -isr_done: - return IRQ_HANDLED; } -static irqreturn_t xgbe_dma_isr(int irq, void *data) +static void xgbe_dma_isr(void *data) { struct xgbe_channel *channel = data; - /* Per channel DMA interrupts are enabled, so we use the per - * channel napi structure and not the private data napi structure - */ - if (napi_schedule_prep(&channel->napi)) { - /* Disable Tx and Rx interrupts */ - disable_irq_nosync(channel->dma_irq); - - /* Turn on polling */ - __napi_schedule_irqoff(&channel->napi); - } - - return IRQ_HANDLED; + xgbe_one_poll(channel, 16); } -static void xgbe_tx_timer(unsigned long data) +static void xgbe_service(void *ctx, int pending) { - struct xgbe_channel *channel = (struct xgbe_channel *)data; - struct xgbe_prv_data *pdata = channel->pdata; - struct napi_struct *napi; + struct xgbe_prv_data *pdata = ctx; - DBGPR("-->xgbe_tx_timer\n"); - - napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi; - - if (napi_schedule_prep(napi)) { - /* Disable Tx and Rx interrupts */ - if (pdata->per_channel_irq) - disable_irq_nosync(channel->dma_irq); - else - xgbe_disable_rx_tx_ints(pdata); - - /* Turn on polling */ - __napi_schedule(napi); - } - - channel->tx_timer_active = 0; - - DBGPR("<--xgbe_tx_timer\n"); -} - -static void xgbe_service(struct work_struct *work) -{ - struct xgbe_prv_data *pdata = container_of(work, - struct xgbe_prv_data, - service_work); - pdata->phy_if.phy_status(pdata); } -static void xgbe_service_timer(unsigned long data) +static void xgbe_service_timer(void *data) { - struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data; + struct xgbe_prv_data *pdata = data; - queue_work(pdata->dev_workqueue, &pdata->service_work); + DBGPR("--> xgbe_service_timer\n"); + taskqueue_enqueue(pdata->dev_workqueue, &pdata->service_work); - mod_timer(&pdata->service_timer, jiffies + HZ); + callout_reset(&pdata->service_timer, hz, xgbe_service_timer, pdata); + DBGPR("<-- xgbe_service_timer\n"); } static void xgbe_init_timers(struct xgbe_prv_data *pdata) { - struct xgbe_channel *channel; - unsigned int i; - setup_timer(&pdata->service_timer, xgbe_service_timer, - (unsigned long)pdata); - - channel = pdata->channel; - for (i = 0; i < pdata->channel_count; i++, channel++) { - if (!channel->tx_ring) - break; - - setup_timer(&channel->tx_timer, xgbe_tx_timer, - (unsigned long)channel); - } + callout_init(&pdata->service_timer, 1); } static void xgbe_start_timers(struct xgbe_prv_data *pdata) { - mod_timer(&pdata->service_timer, jiffies + HZ); + callout_reset(&pdata->service_timer, hz, xgbe_service_timer, pdata); } static void xgbe_stop_timers(struct xgbe_prv_data *pdata) { - struct xgbe_channel *channel; - unsigned int i; - del_timer_sync(&pdata->service_timer); - - channel = pdata->channel; - for (i = 0; i < pdata->channel_count; i++, channel++) { - if (!channel->tx_ring) - break; - - del_timer_sync(&channel->tx_timer); - } + callout_drain(&pdata->service_timer); } void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata) { unsigned int mac_hfr0, mac_hfr1, mac_hfr2; struct xgbe_hw_features *hw_feat = &pdata->hw_feat; DBGPR("-->xgbe_get_all_hw_features\n"); mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R); mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R); mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R); memset(hw_feat, 0, sizeof(*hw_feat)); hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR); /* Hardware feature register 0 */ hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL); hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH); hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL); hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL); hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL); hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL); hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL); hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL); hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL); hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL); hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL); hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ADDMACADRSEL); hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL); hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS); /* Hardware feature register 1 */ hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RXFIFOSIZE); hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TXFIFOSIZE); hw_feat->adv_ts_hi = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD); hw_feat->dma_width = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64); hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN); hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN); hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN); hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA); hw_feat->rss = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN); hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC); hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, HASHTBLSZ); hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, L3L4FNUM); /* Hardware feature register 2 */ hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT); hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT); hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT); hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT); hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM); hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM); /* Translate the Hash Table size into actual number */ switch (hw_feat->hash_table_size) { case 0: break; case 1: hw_feat->hash_table_size = 64; break; case 2: hw_feat->hash_table_size = 128; break; case 3: hw_feat->hash_table_size = 256; break; } /* Translate the address width setting into actual number */ switch (hw_feat->dma_width) { case 0: hw_feat->dma_width = 32; break; case 1: hw_feat->dma_width = 40; break; case 2: hw_feat->dma_width = 48; break; default: hw_feat->dma_width = 32; } /* The Queue, Channel and TC counts are zero based so increment them * to get the actual number */ hw_feat->rx_q_cnt++; hw_feat->tx_q_cnt++; hw_feat->rx_ch_cnt++; hw_feat->tx_ch_cnt++; hw_feat->tc_cnt++; DBGPR("<--xgbe_get_all_hw_features\n"); } -static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add) -{ - struct xgbe_channel *channel; - unsigned int i; - - if (pdata->per_channel_irq) { - channel = pdata->channel; - for (i = 0; i < pdata->channel_count; i++, channel++) { - if (add) - netif_napi_add(pdata->netdev, &channel->napi, - xgbe_one_poll, NAPI_POLL_WEIGHT); - - napi_enable(&channel->napi); - } - } else { - if (add) - netif_napi_add(pdata->netdev, &pdata->napi, - xgbe_all_poll, NAPI_POLL_WEIGHT); - - napi_enable(&pdata->napi); - } -} - -static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del) -{ - struct xgbe_channel *channel; - unsigned int i; - - if (pdata->per_channel_irq) { - channel = pdata->channel; - for (i = 0; i < pdata->channel_count; i++, channel++) { - napi_disable(&channel->napi); - - if (del) - netif_napi_del(&channel->napi); - } - } else { - napi_disable(&pdata->napi); - - if (del) - netif_napi_del(&pdata->napi); - } -} - static int xgbe_request_irqs(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; - struct net_device *netdev = pdata->netdev; unsigned int i; int ret; - ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0, - netdev->name, pdata); + ret = bus_setup_intr(pdata->dev, pdata->dev_irq_res, + INTR_MPSAFE | INTR_TYPE_NET, NULL, xgbe_isr, pdata, + &pdata->dev_irq_tag); if (ret) { - netdev_alert(netdev, "error requesting irq %d\n", - pdata->dev_irq); return ret; } if (!pdata->per_channel_irq) return 0; channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { - snprintf(channel->dma_irq_name, - sizeof(channel->dma_irq_name) - 1, - "%s-TxRx-%u", netdev_name(netdev), - channel->queue_index); - - ret = devm_request_irq(pdata->dev, channel->dma_irq, - xgbe_dma_isr, 0, - channel->dma_irq_name, channel); - if (ret) { - netdev_alert(netdev, "error requesting irq %d\n", - channel->dma_irq); + ret = bus_setup_intr(pdata->dev, channel->dma_irq_res, + INTR_MPSAFE | INTR_TYPE_NET, NULL, xgbe_dma_isr, channel, + &channel->dma_irq_tag); + if (ret != 0) { goto err_irq; } } return 0; err_irq: /* Using an unsigned int, 'i' will go to UINT_MAX and exit */ for (i--, channel--; i < pdata->channel_count; i--, channel--) - devm_free_irq(pdata->dev, channel->dma_irq, channel); + bus_teardown_intr(pdata->dev, channel->dma_irq_res, + channel->dma_irq_tag); - devm_free_irq(pdata->dev, pdata->dev_irq, pdata); + bus_teardown_intr(pdata->dev, pdata->dev_irq_res, pdata->dev_irq_tag); - return ret; + return -ret; } static void xgbe_free_irqs(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; unsigned int i; - devm_free_irq(pdata->dev, pdata->dev_irq, pdata); + bus_teardown_intr(pdata->dev, pdata->dev_irq_res, pdata->dev_irq_tag); if (!pdata->per_channel_irq) return; channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) - devm_free_irq(pdata->dev, channel->dma_irq, channel); + bus_teardown_intr(pdata->dev, channel->dma_irq_res, + channel->dma_irq_tag); } void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata) { struct xgbe_hw_if *hw_if = &pdata->hw_if; DBGPR("-->xgbe_init_tx_coalesce\n"); pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS; pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES; hw_if->config_tx_coalesce(pdata); DBGPR("<--xgbe_init_tx_coalesce\n"); } void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata) { struct xgbe_hw_if *hw_if = &pdata->hw_if; DBGPR("-->xgbe_init_rx_coalesce\n"); pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS); pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS; pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES; hw_if->config_rx_coalesce(pdata); DBGPR("<--xgbe_init_rx_coalesce\n"); } static void xgbe_free_tx_data(struct xgbe_prv_data *pdata) { struct xgbe_desc_if *desc_if = &pdata->desc_if; struct xgbe_channel *channel; struct xgbe_ring *ring; struct xgbe_ring_data *rdata; unsigned int i, j; DBGPR("-->xgbe_free_tx_data\n"); channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { ring = channel->tx_ring; if (!ring) break; for (j = 0; j < ring->rdesc_count; j++) { rdata = XGBE_GET_DESC_DATA(ring, j); desc_if->unmap_rdata(pdata, rdata); } } DBGPR("<--xgbe_free_tx_data\n"); } static void xgbe_free_rx_data(struct xgbe_prv_data *pdata) { struct xgbe_desc_if *desc_if = &pdata->desc_if; struct xgbe_channel *channel; struct xgbe_ring *ring; struct xgbe_ring_data *rdata; unsigned int i, j; DBGPR("-->xgbe_free_rx_data\n"); channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { ring = channel->rx_ring; if (!ring) break; for (j = 0; j < ring->rdesc_count; j++) { rdata = XGBE_GET_DESC_DATA(ring, j); desc_if->unmap_rdata(pdata, rdata); } } DBGPR("<--xgbe_free_rx_data\n"); } static int xgbe_phy_init(struct xgbe_prv_data *pdata) { pdata->phy_link = -1; pdata->phy_speed = SPEED_UNKNOWN; return pdata->phy_if.phy_reset(pdata); } -int xgbe_powerdown(struct net_device *netdev, unsigned int caller) -{ - struct xgbe_prv_data *pdata = netdev_priv(netdev); - struct xgbe_hw_if *hw_if = &pdata->hw_if; - unsigned long flags; - - DBGPR("-->xgbe_powerdown\n"); - - if (!netif_running(netdev) || - (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) { - netdev_alert(netdev, "Device is already powered down\n"); - DBGPR("<--xgbe_powerdown\n"); - return -EINVAL; - } - - spin_lock_irqsave(&pdata->lock, flags); - - if (caller == XGMAC_DRIVER_CONTEXT) - netif_device_detach(netdev); - - netif_tx_stop_all_queues(netdev); - - xgbe_stop_timers(pdata); - flush_workqueue(pdata->dev_workqueue); - - hw_if->powerdown_tx(pdata); - hw_if->powerdown_rx(pdata); - - xgbe_napi_disable(pdata, 0); - - pdata->power_down = 1; - - spin_unlock_irqrestore(&pdata->lock, flags); - - DBGPR("<--xgbe_powerdown\n"); - - return 0; -} - -int xgbe_powerup(struct net_device *netdev, unsigned int caller) -{ - struct xgbe_prv_data *pdata = netdev_priv(netdev); - struct xgbe_hw_if *hw_if = &pdata->hw_if; - unsigned long flags; - - DBGPR("-->xgbe_powerup\n"); - - if (!netif_running(netdev) || - (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) { - netdev_alert(netdev, "Device is already powered up\n"); - DBGPR("<--xgbe_powerup\n"); - return -EINVAL; - } - - spin_lock_irqsave(&pdata->lock, flags); - - pdata->power_down = 0; - - xgbe_napi_enable(pdata, 0); - - hw_if->powerup_tx(pdata); - hw_if->powerup_rx(pdata); - - if (caller == XGMAC_DRIVER_CONTEXT) - netif_device_attach(netdev); - - netif_tx_start_all_queues(netdev); - - xgbe_start_timers(pdata); - - spin_unlock_irqrestore(&pdata->lock, flags); - - DBGPR("<--xgbe_powerup\n"); - - return 0; -} - static int xgbe_start(struct xgbe_prv_data *pdata) { struct xgbe_hw_if *hw_if = &pdata->hw_if; struct xgbe_phy_if *phy_if = &pdata->phy_if; - struct net_device *netdev = pdata->netdev; int ret; DBGPR("-->xgbe_start\n"); hw_if->init(pdata); ret = phy_if->phy_start(pdata); if (ret) goto err_phy; - xgbe_napi_enable(pdata, 1); - ret = xgbe_request_irqs(pdata); if (ret) goto err_napi; hw_if->enable_tx(pdata); hw_if->enable_rx(pdata); - netif_tx_start_all_queues(netdev); + xgbe_enable_rx_tx_ints(pdata); xgbe_start_timers(pdata); - queue_work(pdata->dev_workqueue, &pdata->service_work); + taskqueue_enqueue(pdata->dev_workqueue, &pdata->service_work); DBGPR("<--xgbe_start\n"); return 0; err_napi: - xgbe_napi_disable(pdata, 1); - phy_if->phy_stop(pdata); err_phy: hw_if->exit(pdata); return ret; } static void xgbe_stop(struct xgbe_prv_data *pdata) { struct xgbe_hw_if *hw_if = &pdata->hw_if; struct xgbe_phy_if *phy_if = &pdata->phy_if; - struct xgbe_channel *channel; - struct net_device *netdev = pdata->netdev; - struct netdev_queue *txq; - unsigned int i; DBGPR("-->xgbe_stop\n"); - netif_tx_stop_all_queues(netdev); - xgbe_stop_timers(pdata); - flush_workqueue(pdata->dev_workqueue); + taskqueue_drain_all(pdata->dev_workqueue); hw_if->disable_tx(pdata); hw_if->disable_rx(pdata); xgbe_free_irqs(pdata); - xgbe_napi_disable(pdata, 1); - phy_if->phy_stop(pdata); hw_if->exit(pdata); - channel = pdata->channel; - for (i = 0; i < pdata->channel_count; i++, channel++) { - if (!channel->tx_ring) - continue; - - txq = netdev_get_tx_queue(netdev, channel->queue_index); - netdev_tx_reset_queue(txq); - } - DBGPR("<--xgbe_stop\n"); } static void xgbe_restart_dev(struct xgbe_prv_data *pdata) { DBGPR("-->xgbe_restart_dev\n"); /* If not running, "restart" will happen on open */ - if (!netif_running(pdata->netdev)) + if ((pdata->netdev->if_drv_flags & IFF_DRV_RUNNING) == 0) return; xgbe_stop(pdata); xgbe_free_tx_data(pdata); xgbe_free_rx_data(pdata); xgbe_start(pdata); DBGPR("<--xgbe_restart_dev\n"); } -static void xgbe_restart(struct work_struct *work) +static void xgbe_restart(void *ctx, int pending) { - struct xgbe_prv_data *pdata = container_of(work, - struct xgbe_prv_data, - restart_work); + struct xgbe_prv_data *pdata = ctx; - rtnl_lock(); - xgbe_restart_dev(pdata); - - rtnl_unlock(); } -static void xgbe_tx_tstamp(struct work_struct *work) -{ - struct xgbe_prv_data *pdata = container_of(work, - struct xgbe_prv_data, - tx_tstamp_work); - struct skb_shared_hwtstamps hwtstamps; - u64 nsec; - unsigned long flags; - - if (pdata->tx_tstamp) { - nsec = timecounter_cyc2time(&pdata->tstamp_tc, - pdata->tx_tstamp); - - memset(&hwtstamps, 0, sizeof(hwtstamps)); - hwtstamps.hwtstamp = ns_to_ktime(nsec); - skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps); - } - - dev_kfree_skb_any(pdata->tx_tstamp_skb); - - spin_lock_irqsave(&pdata->tstamp_lock, flags); - pdata->tx_tstamp_skb = NULL; - spin_unlock_irqrestore(&pdata->tstamp_lock, flags); -} - -static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata, - struct ifreq *ifreq) -{ - if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config, - sizeof(pdata->tstamp_config))) - return -EFAULT; - - return 0; -} - -static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata, - struct ifreq *ifreq) -{ - struct hwtstamp_config config; - unsigned int mac_tscr; - - if (copy_from_user(&config, ifreq->ifr_data, sizeof(config))) - return -EFAULT; - - if (config.flags) - return -EINVAL; - - mac_tscr = 0; - - switch (config.tx_type) { - case HWTSTAMP_TX_OFF: - break; - - case HWTSTAMP_TX_ON: - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); - break; - - default: - return -ERANGE; - } - - switch (config.rx_filter) { - case HWTSTAMP_FILTER_NONE: - break; - - case HWTSTAMP_FILTER_ALL: - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); - break; - - /* PTP v2, UDP, any kind of event packet */ - case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); - /* PTP v1, UDP, any kind of event packet */ - case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); - break; - - /* PTP v2, UDP, Sync packet */ - case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); - /* PTP v1, UDP, Sync packet */ - case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); - break; - - /* PTP v2, UDP, Delay_req packet */ - case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); - /* PTP v1, UDP, Delay_req packet */ - case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); - break; - - /* 802.AS1, Ethernet, any kind of event packet */ - case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); - break; - - /* 802.AS1, Ethernet, Sync packet */ - case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); - break; - - /* 802.AS1, Ethernet, Delay_req packet */ - case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); - break; - - /* PTP v2/802.AS1, any layer, any kind of event packet */ - case HWTSTAMP_FILTER_PTP_V2_EVENT: - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); - break; - - /* PTP v2/802.AS1, any layer, Sync packet */ - case HWTSTAMP_FILTER_PTP_V2_SYNC: - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); - break; - - /* PTP v2/802.AS1, any layer, Delay_req packet */ - case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); - XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); - break; - - default: - return -ERANGE; - } - - pdata->hw_if.config_tstamp(pdata, mac_tscr); - - memcpy(&pdata->tstamp_config, &config, sizeof(config)); - - return 0; -} - -static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata, - struct sk_buff *skb, - struct xgbe_packet_data *packet) -{ - unsigned long flags; - - if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) { - spin_lock_irqsave(&pdata->tstamp_lock, flags); - if (pdata->tx_tstamp_skb) { - /* Another timestamp in progress, ignore this one */ - XGMAC_SET_BITS(packet->attributes, - TX_PACKET_ATTRIBUTES, PTP, 0); - } else { - pdata->tx_tstamp_skb = skb_get(skb); - skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; - } - spin_unlock_irqrestore(&pdata->tstamp_lock, flags); - } - - if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) - skb_tx_timestamp(skb); -} - -static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet) -{ - if (skb_vlan_tag_present(skb)) - packet->vlan_ctag = skb_vlan_tag_get(skb); -} - -static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet) -{ - int ret; - - if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, - TSO_ENABLE)) - return 0; - - ret = skb_cow_head(skb, 0); - if (ret) - return ret; - - packet->header_len = skb_transport_offset(skb) + tcp_hdrlen(skb); - packet->tcp_header_len = tcp_hdrlen(skb); - packet->tcp_payload_len = skb->len - packet->header_len; - packet->mss = skb_shinfo(skb)->gso_size; - DBGPR(" packet->header_len=%u\n", packet->header_len); - DBGPR(" packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n", - packet->tcp_header_len, packet->tcp_payload_len); - DBGPR(" packet->mss=%u\n", packet->mss); - - /* Update the number of packets that will ultimately be transmitted - * along with the extra bytes for each extra packet - */ - packet->tx_packets = skb_shinfo(skb)->gso_segs; - packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len; - - return 0; -} - -static int xgbe_is_tso(struct sk_buff *skb) -{ - if (skb->ip_summed != CHECKSUM_PARTIAL) - return 0; - - if (!skb_is_gso(skb)) - return 0; - - DBGPR(" TSO packet to be processed\n"); - - return 1; -} - static void xgbe_packet_info(struct xgbe_prv_data *pdata, - struct xgbe_ring *ring, struct sk_buff *skb, + struct xgbe_ring *ring, struct mbuf *m0, struct xgbe_packet_data *packet) { - struct skb_frag_struct *frag; - unsigned int context_desc; + struct mbuf *m; unsigned int len; - unsigned int i; - packet->skb = skb; + packet->m = m0; - context_desc = 0; packet->rdesc_count = 0; packet->tx_packets = 1; - packet->tx_bytes = skb->len; + packet->tx_bytes = m_length(m0, NULL); - if (xgbe_is_tso(skb)) { - /* TSO requires an extra descriptor if mss is different */ - if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) { - context_desc = 1; + for (m = m0; m != NULL; m = m->m_next) { + for (len = m->m_len; len != 0;) { packet->rdesc_count++; + len -= MIN(len, XGBE_TX_MAX_BUF_SIZE); } - - /* TSO requires an extra descriptor for TSO header */ - packet->rdesc_count++; - - XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, - TSO_ENABLE, 1); - XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, - CSUM_ENABLE, 1); - } else if (skb->ip_summed == CHECKSUM_PARTIAL) - XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, - CSUM_ENABLE, 1); - - if (skb_vlan_tag_present(skb)) { - /* VLAN requires an extra descriptor if tag is different */ - if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag) - /* We can share with the TSO context descriptor */ - if (!context_desc) { - context_desc = 1; - packet->rdesc_count++; - } - - XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, - VLAN_CTAG, 1); } - - if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && - (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON)) - XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, - PTP, 1); - - for (len = skb_headlen(skb); len;) { - packet->rdesc_count++; - len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE); - } - - for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { - frag = &skb_shinfo(skb)->frags[i]; - for (len = skb_frag_size(frag); len; ) { - packet->rdesc_count++; - len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE); - } - } } -static int xgbe_open(struct net_device *netdev) +int xgbe_open(struct ifnet *netdev) { - struct xgbe_prv_data *pdata = netdev_priv(netdev); + struct xgbe_prv_data *pdata = netdev->if_softc; struct xgbe_desc_if *desc_if = &pdata->desc_if; int ret; DBGPR("-->xgbe_open\n"); /* Initialize the phy */ ret = xgbe_phy_init(pdata); if (ret) return ret; - /* Enable the clocks */ - ret = clk_prepare_enable(pdata->sysclk); - if (ret) { - netdev_alert(netdev, "dma clk_prepare_enable failed\n"); - return ret; - } - - ret = clk_prepare_enable(pdata->ptpclk); - if (ret) { - netdev_alert(netdev, "ptp clk_prepare_enable failed\n"); - goto err_sysclk; - } - /* Calculate the Rx buffer size before allocating rings */ - ret = xgbe_calc_rx_buf_size(netdev, netdev->mtu); - if (ret < 0) + ret = xgbe_calc_rx_buf_size(netdev, if_getmtu(netdev)); + if (ret < 0) { goto err_ptpclk; + } pdata->rx_buf_size = ret; /* Allocate the channel and ring structures */ ret = xgbe_alloc_channels(pdata); - if (ret) + if (ret) { + printf("xgbe_alloc_channels failed\n"); goto err_ptpclk; + } /* Allocate the ring descriptors and buffers */ ret = desc_if->alloc_ring_resources(pdata); - if (ret) + if (ret) { + printf("desc_if->alloc_ring_resources failed\n"); goto err_channels; + } - INIT_WORK(&pdata->service_work, xgbe_service); - INIT_WORK(&pdata->restart_work, xgbe_restart); - INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp); + TASK_INIT(&pdata->service_work, 0, xgbe_service, pdata); + TASK_INIT(&pdata->restart_work, 0, xgbe_restart, pdata); xgbe_init_timers(pdata); ret = xgbe_start(pdata); if (ret) goto err_rings; clear_bit(XGBE_DOWN, &pdata->dev_state); DBGPR("<--xgbe_open\n"); return 0; err_rings: desc_if->free_ring_resources(pdata); err_channels: xgbe_free_channels(pdata); err_ptpclk: - clk_disable_unprepare(pdata->ptpclk); -err_sysclk: - clk_disable_unprepare(pdata->sysclk); - return ret; } -static int xgbe_close(struct net_device *netdev) +int xgbe_close(struct ifnet *netdev) { - struct xgbe_prv_data *pdata = netdev_priv(netdev); + struct xgbe_prv_data *pdata = netdev->if_softc; struct xgbe_desc_if *desc_if = &pdata->desc_if; DBGPR("-->xgbe_close\n"); /* Stop the device */ xgbe_stop(pdata); /* Free the ring descriptors and buffers */ desc_if->free_ring_resources(pdata); /* Free the channel and ring structures */ xgbe_free_channels(pdata); - /* Disable the clocks */ - clk_disable_unprepare(pdata->ptpclk); - clk_disable_unprepare(pdata->sysclk); - set_bit(XGBE_DOWN, &pdata->dev_state); DBGPR("<--xgbe_close\n"); return 0; } -static int xgbe_xmit(struct sk_buff *skb, struct net_device *netdev) +int xgbe_xmit(struct ifnet *ifp, struct mbuf *m) { - struct xgbe_prv_data *pdata = netdev_priv(netdev); + struct xgbe_prv_data *pdata = ifp->if_softc; struct xgbe_hw_if *hw_if = &pdata->hw_if; struct xgbe_desc_if *desc_if = &pdata->desc_if; struct xgbe_channel *channel; struct xgbe_ring *ring; struct xgbe_packet_data *packet; - struct netdev_queue *txq; int ret; - DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len); + M_ASSERTPKTHDR(m); + MPASS(m->m_nextpkt == NULL); - channel = pdata->channel + skb->queue_mapping; - txq = netdev_get_tx_queue(netdev, channel->queue_index); + if (__predict_false(test_bit(XGBE_DOWN, &pdata->dev_state) || + !pdata->phy.link)) { + m_freem(m); + return (ENETDOWN); + } + + channel = pdata->channel; ring = channel->tx_ring; packet = &ring->packet_data; - ret = NETDEV_TX_OK; - - if (skb->len == 0) { - netif_err(pdata, tx_err, netdev, - "empty skb received from stack\n"); - dev_kfree_skb_any(skb); - goto tx_netdev_return; - } - /* Calculate preliminary packet info */ memset(packet, 0, sizeof(*packet)); - xgbe_packet_info(pdata, ring, skb, packet); + xgbe_packet_info(pdata, ring, m, packet); /* Check that there are enough descriptors available */ ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count); if (ret) goto tx_netdev_return; - ret = xgbe_prep_tso(skb, packet); - if (ret) { - netif_err(pdata, tx_err, netdev, - "error processing TSO packet\n"); - dev_kfree_skb_any(skb); + if (!desc_if->map_tx_skb(channel, m)) { goto tx_netdev_return; } - xgbe_prep_vlan(skb, packet); - if (!desc_if->map_tx_skb(channel, skb)) { - dev_kfree_skb_any(skb); - goto tx_netdev_return; - } - - xgbe_prep_tx_tstamp(pdata, skb, packet); - - /* Report on the actual number of bytes (to be) sent */ - netdev_tx_sent_queue(txq, packet->tx_bytes); - /* Configure required descriptor fields for transmission */ hw_if->dev_xmit(channel); - if (netif_msg_pktdata(pdata)) - xgbe_print_pkt(netdev, skb, true); + return 0; - /* Stop the queue in advance if there may not be enough descriptors */ - xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS); - - ret = NETDEV_TX_OK; - tx_netdev_return: - return ret; -} + m_free(m); -static void xgbe_set_rx_mode(struct net_device *netdev) -{ - struct xgbe_prv_data *pdata = netdev_priv(netdev); - struct xgbe_hw_if *hw_if = &pdata->hw_if; - - DBGPR("-->xgbe_set_rx_mode\n"); - - hw_if->config_rx_mode(pdata); - - DBGPR("<--xgbe_set_rx_mode\n"); -} - -static int xgbe_set_mac_address(struct net_device *netdev, void *addr) -{ - struct xgbe_prv_data *pdata = netdev_priv(netdev); - struct xgbe_hw_if *hw_if = &pdata->hw_if; - struct sockaddr *saddr = addr; - - DBGPR("-->xgbe_set_mac_address\n"); - - if (!is_valid_ether_addr(saddr->sa_data)) - return -EADDRNOTAVAIL; - - memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len); - - hw_if->set_mac_address(pdata, netdev->dev_addr); - - DBGPR("<--xgbe_set_mac_address\n"); - return 0; } -static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd) +int xgbe_change_mtu(struct ifnet *netdev, int mtu) { - struct xgbe_prv_data *pdata = netdev_priv(netdev); + struct xgbe_prv_data *pdata = netdev->if_softc; int ret; - switch (cmd) { - case SIOCGHWTSTAMP: - ret = xgbe_get_hwtstamp_settings(pdata, ifreq); - break; - - case SIOCSHWTSTAMP: - ret = xgbe_set_hwtstamp_settings(pdata, ifreq); - break; - - default: - ret = -EOPNOTSUPP; - } - - return ret; -} - -static int xgbe_change_mtu(struct net_device *netdev, int mtu) -{ - struct xgbe_prv_data *pdata = netdev_priv(netdev); - int ret; - DBGPR("-->xgbe_change_mtu\n"); ret = xgbe_calc_rx_buf_size(netdev, mtu); if (ret < 0) - return ret; + return -ret; pdata->rx_buf_size = ret; - netdev->mtu = mtu; + netdev->if_mtu = mtu; xgbe_restart_dev(pdata); DBGPR("<--xgbe_change_mtu\n"); return 0; } -static void xgbe_tx_timeout(struct net_device *netdev) -{ - struct xgbe_prv_data *pdata = netdev_priv(netdev); - - netdev_warn(netdev, "tx timeout, device restarting\n"); - schedule_work(&pdata->restart_work); -} - -static struct rtnl_link_stats64 *xgbe_get_stats64(struct net_device *netdev, - struct rtnl_link_stats64 *s) -{ - struct xgbe_prv_data *pdata = netdev_priv(netdev); - struct xgbe_mmc_stats *pstats = &pdata->mmc_stats; - - DBGPR("-->%s\n", __func__); - - pdata->hw_if.read_mmc_stats(pdata); - - s->rx_packets = pstats->rxframecount_gb; - s->rx_bytes = pstats->rxoctetcount_gb; - s->rx_errors = pstats->rxframecount_gb - - pstats->rxbroadcastframes_g - - pstats->rxmulticastframes_g - - pstats->rxunicastframes_g; - s->multicast = pstats->rxmulticastframes_g; - s->rx_length_errors = pstats->rxlengtherror; - s->rx_crc_errors = pstats->rxcrcerror; - s->rx_fifo_errors = pstats->rxfifooverflow; - - s->tx_packets = pstats->txframecount_gb; - s->tx_bytes = pstats->txoctetcount_gb; - s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g; - s->tx_dropped = netdev->stats.tx_dropped; - - DBGPR("<--%s\n", __func__); - - return s; -} - -static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, - u16 vid) -{ - struct xgbe_prv_data *pdata = netdev_priv(netdev); - struct xgbe_hw_if *hw_if = &pdata->hw_if; - - DBGPR("-->%s\n", __func__); - - set_bit(vid, pdata->active_vlans); - hw_if->update_vlan_hash_table(pdata); - - DBGPR("<--%s\n", __func__); - - return 0; -} - -static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, - u16 vid) -{ - struct xgbe_prv_data *pdata = netdev_priv(netdev); - struct xgbe_hw_if *hw_if = &pdata->hw_if; - - DBGPR("-->%s\n", __func__); - - clear_bit(vid, pdata->active_vlans); - hw_if->update_vlan_hash_table(pdata); - - DBGPR("<--%s\n", __func__); - - return 0; -} - -#ifdef CONFIG_NET_POLL_CONTROLLER -static void xgbe_poll_controller(struct net_device *netdev) -{ - struct xgbe_prv_data *pdata = netdev_priv(netdev); - struct xgbe_channel *channel; - unsigned int i; - - DBGPR("-->xgbe_poll_controller\n"); - - if (pdata->per_channel_irq) { - channel = pdata->channel; - for (i = 0; i < pdata->channel_count; i++, channel++) - xgbe_dma_isr(channel->dma_irq, channel); - } else { - disable_irq(pdata->dev_irq); - xgbe_isr(pdata->dev_irq, pdata); - enable_irq(pdata->dev_irq); - } - - DBGPR("<--xgbe_poll_controller\n"); -} -#endif /* End CONFIG_NET_POLL_CONTROLLER */ - -static int xgbe_setup_tc(struct net_device *netdev, u32 handle, __be16 proto, - struct tc_to_netdev *tc_to_netdev) -{ - struct xgbe_prv_data *pdata = netdev_priv(netdev); - u8 tc; - - if (tc_to_netdev->type != TC_SETUP_MQPRIO) - return -EINVAL; - - tc = tc_to_netdev->tc; - - if (tc > pdata->hw_feat.tc_cnt) - return -EINVAL; - - pdata->num_tcs = tc; - pdata->hw_if.config_tc(pdata); - - return 0; -} - -static int xgbe_set_features(struct net_device *netdev, - netdev_features_t features) -{ - struct xgbe_prv_data *pdata = netdev_priv(netdev); - struct xgbe_hw_if *hw_if = &pdata->hw_if; - netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter; - int ret = 0; - - rxhash = pdata->netdev_features & NETIF_F_RXHASH; - rxcsum = pdata->netdev_features & NETIF_F_RXCSUM; - rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX; - rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER; - - if ((features & NETIF_F_RXHASH) && !rxhash) - ret = hw_if->enable_rss(pdata); - else if (!(features & NETIF_F_RXHASH) && rxhash) - ret = hw_if->disable_rss(pdata); - if (ret) - return ret; - - if ((features & NETIF_F_RXCSUM) && !rxcsum) - hw_if->enable_rx_csum(pdata); - else if (!(features & NETIF_F_RXCSUM) && rxcsum) - hw_if->disable_rx_csum(pdata); - - if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan) - hw_if->enable_rx_vlan_stripping(pdata); - else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan) - hw_if->disable_rx_vlan_stripping(pdata); - - if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter) - hw_if->enable_rx_vlan_filtering(pdata); - else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter) - hw_if->disable_rx_vlan_filtering(pdata); - - pdata->netdev_features = features; - - DBGPR("<--xgbe_set_features\n"); - - return 0; -} - -static const struct net_device_ops xgbe_netdev_ops = { - .ndo_open = xgbe_open, - .ndo_stop = xgbe_close, - .ndo_start_xmit = xgbe_xmit, - .ndo_set_rx_mode = xgbe_set_rx_mode, - .ndo_set_mac_address = xgbe_set_mac_address, - .ndo_validate_addr = eth_validate_addr, - .ndo_do_ioctl = xgbe_ioctl, - .ndo_change_mtu = xgbe_change_mtu, - .ndo_tx_timeout = xgbe_tx_timeout, - .ndo_get_stats64 = xgbe_get_stats64, - .ndo_vlan_rx_add_vid = xgbe_vlan_rx_add_vid, - .ndo_vlan_rx_kill_vid = xgbe_vlan_rx_kill_vid, -#ifdef CONFIG_NET_POLL_CONTROLLER - .ndo_poll_controller = xgbe_poll_controller, -#endif - .ndo_setup_tc = xgbe_setup_tc, - .ndo_set_features = xgbe_set_features, -}; - -struct net_device_ops *xgbe_get_netdev_ops(void) -{ - return (struct net_device_ops *)&xgbe_netdev_ops; -} - static void xgbe_rx_refresh(struct xgbe_channel *channel) { struct xgbe_prv_data *pdata = channel->pdata; struct xgbe_hw_if *hw_if = &pdata->hw_if; struct xgbe_desc_if *desc_if = &pdata->desc_if; struct xgbe_ring *ring = channel->rx_ring; struct xgbe_ring_data *rdata; while (ring->dirty != ring->cur) { rdata = XGBE_GET_DESC_DATA(ring, ring->dirty); /* Reset rdata values */ desc_if->unmap_rdata(pdata, rdata); if (desc_if->map_rx_buffer(pdata, ring, rdata)) break; hw_if->rx_desc_reset(pdata, rdata, ring->dirty); ring->dirty++; } /* Make sure everything is written before the register write */ - wmb(); + dsb(sy); /* Update the Rx Tail Pointer Register with address of * the last cleaned entry */ rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1); XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO, - lower_32_bits(rdata->rdesc_dma)); + lower_32_bits(rdata->rdata_paddr)); } -static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata, - struct napi_struct *napi, - struct xgbe_ring_data *rdata, - unsigned int len) -{ - struct sk_buff *skb; - u8 *packet; - unsigned int copy_len; - - skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len); - if (!skb) - return NULL; - - /* Start with the header buffer which may contain just the header - * or the header plus data - */ - dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base, - rdata->rx.hdr.dma_off, - rdata->rx.hdr.dma_len, DMA_FROM_DEVICE); - - packet = page_address(rdata->rx.hdr.pa.pages) + - rdata->rx.hdr.pa.pages_offset; - copy_len = (rdata->rx.hdr_len) ? rdata->rx.hdr_len : len; - copy_len = min(rdata->rx.hdr.dma_len, copy_len); - skb_copy_to_linear_data(skb, packet, copy_len); - skb_put(skb, copy_len); - - len -= copy_len; - if (len) { - /* Add the remaining data as a frag */ - dma_sync_single_range_for_cpu(pdata->dev, - rdata->rx.buf.dma_base, - rdata->rx.buf.dma_off, - rdata->rx.buf.dma_len, - DMA_FROM_DEVICE); - - skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, - rdata->rx.buf.pa.pages, - rdata->rx.buf.pa.pages_offset, - len, rdata->rx.buf.dma_len); - rdata->rx.buf.pa.pages = NULL; - } - - return skb; -} - static int xgbe_tx_poll(struct xgbe_channel *channel) { struct xgbe_prv_data *pdata = channel->pdata; struct xgbe_hw_if *hw_if = &pdata->hw_if; struct xgbe_desc_if *desc_if = &pdata->desc_if; struct xgbe_ring *ring = channel->tx_ring; struct xgbe_ring_data *rdata; struct xgbe_ring_desc *rdesc; - struct net_device *netdev = pdata->netdev; - struct netdev_queue *txq; int processed = 0; - unsigned int tx_packets = 0, tx_bytes = 0; unsigned int cur; DBGPR("-->xgbe_tx_poll\n"); /* Nothing to do if there isn't a Tx ring for this channel */ if (!ring) return 0; cur = ring->cur; /* Be sure we get ring->cur before accessing descriptor data */ - smp_rmb(); + dsb(sy); - txq = netdev_get_tx_queue(netdev, channel->queue_index); - while ((processed < XGBE_TX_DESC_MAX_PROC) && (ring->dirty != cur)) { rdata = XGBE_GET_DESC_DATA(ring, ring->dirty); rdesc = rdata->rdesc; if (!hw_if->tx_complete(rdesc)) break; /* Make sure descriptor fields are read after reading the OWN * bit */ - dma_rmb(); + dsb(sy); - if (netif_msg_tx_done(pdata)) - xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0); - - if (hw_if->is_last_desc(rdesc)) { - tx_packets += rdata->tx.packets; - tx_bytes += rdata->tx.bytes; - } - /* Free the SKB and reset the descriptor for re-use */ desc_if->unmap_rdata(pdata, rdata); hw_if->tx_desc_reset(rdata); processed++; ring->dirty++; } if (!processed) return 0; - netdev_tx_completed_queue(txq, tx_packets, tx_bytes); - - if ((ring->tx.queue_stopped == 1) && - (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) { - ring->tx.queue_stopped = 0; - netif_tx_wake_queue(txq); - } - DBGPR("<--xgbe_tx_poll: processed=%d\n", processed); return processed; } static int xgbe_rx_poll(struct xgbe_channel *channel, int budget) { struct xgbe_prv_data *pdata = channel->pdata; struct xgbe_hw_if *hw_if = &pdata->hw_if; struct xgbe_ring *ring = channel->rx_ring; struct xgbe_ring_data *rdata; struct xgbe_packet_data *packet; - struct net_device *netdev = pdata->netdev; - struct napi_struct *napi; - struct sk_buff *skb; - struct skb_shared_hwtstamps *hwtstamps; - unsigned int incomplete, error, context_next, context; - unsigned int len, rdesc_len, max_len; + struct ifnet *ifp = pdata->netdev; + struct mbuf *m; + unsigned int incomplete, context_next, context; unsigned int received = 0; int packet_count = 0; DBGPR("-->xgbe_rx_poll: budget=%d\n", budget); /* Nothing to do if there isn't a Rx ring for this channel */ if (!ring) return 0; incomplete = 0; context_next = 0; - napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi; - rdata = XGBE_GET_DESC_DATA(ring, ring->cur); packet = &ring->packet_data; while (packet_count < budget) { DBGPR(" cur = %d\n", ring->cur); - /* First time in loop see if we need to restore state */ - if (!received && rdata->state_saved) { - skb = rdata->state.skb; - error = rdata->state.error; - len = rdata->state.len; - } else { - memset(packet, 0, sizeof(*packet)); - skb = NULL; - error = 0; - len = 0; - } - read_again: rdata = XGBE_GET_DESC_DATA(ring, ring->cur); if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3)) xgbe_rx_refresh(channel); if (hw_if->dev_read(channel)) break; + m = rdata->mb; + received++; ring->cur++; incomplete = XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, INCOMPLETE); context_next = XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT_NEXT); context = XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT); /* Earlier error, just drain the remaining data */ - if ((incomplete || context_next) && error) + if (incomplete || context_next) { goto read_again; - - if (error || packet->errors) { - if (packet->errors) - netif_err(pdata, rx_err, netdev, - "error in received packet\n"); - dev_kfree_skb(skb); - goto next_packet; } - if (!context) { - /* Length is cumulative, get this descriptor's length */ - rdesc_len = rdata->rx.len - len; - len += rdesc_len; - - if (rdesc_len && !skb) { - skb = xgbe_create_skb(pdata, napi, rdata, - rdesc_len); - if (!skb) - error = 1; - } else if (rdesc_len) { - dma_sync_single_range_for_cpu(pdata->dev, - rdata->rx.buf.dma_base, - rdata->rx.buf.dma_off, - rdata->rx.buf.dma_len, - DMA_FROM_DEVICE); - - skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, - rdata->rx.buf.pa.pages, - rdata->rx.buf.pa.pages_offset, - rdesc_len, - rdata->rx.buf.dma_len); - rdata->rx.buf.pa.pages = NULL; - } - } - - if (incomplete || context_next) - goto read_again; - - if (!skb) + if (packet->errors) { + rdata->mbuf_free = 1; goto next_packet; - - /* Be sure we don't exceed the configured MTU */ - max_len = netdev->mtu + ETH_HLEN; - if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && - (skb->protocol == htons(ETH_P_8021Q))) - max_len += VLAN_HLEN; - - if (skb->len > max_len) { - netif_err(pdata, rx_err, netdev, - "packet length exceeds configured MTU\n"); - dev_kfree_skb(skb); - goto next_packet; } + rdata->mb = NULL; - if (netif_msg_pktdata(pdata)) - xgbe_print_pkt(netdev, skb, false); - - skb_checksum_none_assert(skb); - if (XGMAC_GET_BITS(packet->attributes, - RX_PACKET_ATTRIBUTES, CSUM_DONE)) - skb->ip_summed = CHECKSUM_UNNECESSARY; - - if (XGMAC_GET_BITS(packet->attributes, - RX_PACKET_ATTRIBUTES, VLAN_CTAG)) - __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), - packet->vlan_ctag); - - if (XGMAC_GET_BITS(packet->attributes, - RX_PACKET_ATTRIBUTES, RX_TSTAMP)) { - u64 nsec; - - nsec = timecounter_cyc2time(&pdata->tstamp_tc, - packet->rx_tstamp); - hwtstamps = skb_hwtstamps(skb); - hwtstamps->hwtstamp = ns_to_ktime(nsec); + m->m_pkthdr.len = rdata->rx.hdr_len + rdata->rx.len; + if (rdata->rx.hdr_len != 0) { + m->m_len = rdata->rx.hdr_len; + m->m_next->m_len = rdata->rx.len; + } else { + m->m_len = rdata->rx.len; + m_freem(m->m_next); + m->m_next = NULL; } + if_setrcvif(m, ifp); + if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); - if (XGMAC_GET_BITS(packet->attributes, - RX_PACKET_ATTRIBUTES, RSS_HASH)) - skb_set_hash(skb, packet->rss_hash, - packet->rss_hash_type); + ifp->if_input(ifp, m); - skb->dev = netdev; - skb->protocol = eth_type_trans(skb, netdev); - skb_record_rx_queue(skb, channel->queue_index); - - napi_gro_receive(napi, skb); - next_packet: packet_count++; } - /* Check if we need to save state before leaving */ - if (received && (incomplete || context_next)) { - rdata = XGBE_GET_DESC_DATA(ring, ring->cur); - rdata->state_saved = 1; - rdata->state.skb = skb; - rdata->state.len = len; - rdata->state.error = error; - } - DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count); return packet_count; } -static int xgbe_one_poll(struct napi_struct *napi, int budget) +static int xgbe_one_poll(struct xgbe_channel *channel, int budget) { - struct xgbe_channel *channel = container_of(napi, struct xgbe_channel, - napi); int processed = 0; DBGPR("-->xgbe_one_poll: budget=%d\n", budget); /* Cleanup Tx ring first */ xgbe_tx_poll(channel); /* Process Rx ring next */ processed = xgbe_rx_poll(channel, budget); - /* If we processed everything, we are done */ - if (processed < budget) { - /* Turn off polling */ - napi_complete_done(napi, processed); - - /* Enable Tx and Rx interrupts */ - enable_irq(channel->dma_irq); - } - DBGPR("<--xgbe_one_poll: received = %d\n", processed); return processed; } -static int xgbe_all_poll(struct napi_struct *napi, int budget) +static int xgbe_all_poll(struct xgbe_prv_data *pdata, int budget) { - struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data, - napi); struct xgbe_channel *channel; int ring_budget; int processed, last_processed; unsigned int i; DBGPR("-->xgbe_all_poll: budget=%d\n", budget); processed = 0; ring_budget = budget / pdata->rx_ring_count; do { last_processed = processed; channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { /* Cleanup Tx ring first */ xgbe_tx_poll(channel); /* Process Rx ring next */ if (ring_budget > (budget - processed)) ring_budget = budget - processed; processed += xgbe_rx_poll(channel, ring_budget); } } while ((processed < budget) && (processed != last_processed)); - /* If we processed everything, we are done */ - if (processed < budget) { - /* Turn off polling */ - napi_complete_done(napi, processed); - - /* Enable Tx and Rx interrupts */ - xgbe_enable_rx_tx_ints(pdata); - } - DBGPR("<--xgbe_all_poll: received = %d\n", processed); return processed; -} - -void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring, - unsigned int idx, unsigned int count, unsigned int flag) -{ - struct xgbe_ring_data *rdata; - struct xgbe_ring_desc *rdesc; - - while (count--) { - rdata = XGBE_GET_DESC_DATA(ring, idx); - rdesc = rdata->rdesc; - netdev_dbg(pdata->netdev, - "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx, - (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE", - le32_to_cpu(rdesc->desc0), - le32_to_cpu(rdesc->desc1), - le32_to_cpu(rdesc->desc2), - le32_to_cpu(rdesc->desc3)); - idx++; - } -} - -void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring, - unsigned int idx) -{ - struct xgbe_ring_data *rdata; - struct xgbe_ring_desc *rdesc; - - rdata = XGBE_GET_DESC_DATA(ring, idx); - rdesc = rdata->rdesc; - netdev_dbg(pdata->netdev, - "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n", - idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1), - le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3)); -} - -void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx) -{ - struct ethhdr *eth = (struct ethhdr *)skb->data; - unsigned char *buf = skb->data; - unsigned char buffer[128]; - unsigned int i, j; - - netdev_dbg(netdev, "\n************** SKB dump ****************\n"); - - netdev_dbg(netdev, "%s packet of %d bytes\n", - (tx_rx ? "TX" : "RX"), skb->len); - - netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest); - netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source); - netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto)); - - for (i = 0, j = 0; i < skb->len;) { - j += snprintf(buffer + j, sizeof(buffer) - j, "%02hhx", - buf[i++]); - - if ((i % 32) == 0) { - netdev_dbg(netdev, " %#06x: %s\n", i - 32, buffer); - j = 0; - } else if ((i % 16) == 0) { - buffer[j++] = ' '; - buffer[j++] = ' '; - } else if ((i % 4) == 0) { - buffer[j++] = ' '; - } - } - if (i % 32) - netdev_dbg(netdev, " %#06x: %s\n", i - (i % 32), buffer); - - netdev_dbg(netdev, "\n************** SKB dump ****************\n"); } Property changes on: head/sys/dev/axgbe/xgbe-drv.c ___________________________________________________________________ Deleted: fbsd:nokeywords ## -1 +0,0 ## -yes \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/dev/axgbe/xgbe-mdio.c =================================================================== --- head/sys/dev/axgbe/xgbe-mdio.c (revision 313767) +++ head/sys/dev/axgbe/xgbe-mdio.c (revision 313768) @@ -1,1361 +1,1180 @@ /* * AMD 10Gb Ethernet driver * * This file is available to you under your choice of the following two * licenses: * * License 1: GPLv2 * * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. * * This file is free software; you may copy, redistribute and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 2 of the License, or (at * your option) any later version. * * This file is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see . * * This file incorporates work covered by the following copyright and * permission notice: * The Synopsys DWC ETHER XGMAC Software Driver and documentation * (hereinafter "Software") is an unsupported proprietary work of Synopsys, * Inc. unless otherwise expressly agreed to in writing between Synopsys * and you. * * The Software IS NOT an item of Licensed Software or Licensed Product * under any End User Software License Agreement or Agreement for Licensed * Product with Synopsys or any supplement thereto. Permission is hereby * granted, free of charge, to any person obtaining a copy of this software * annotated with this license and the Software, to deal in the Software * without restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished * to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * * License 2: Modified BSD * * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Advanced Micro Devices, Inc. nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * This file incorporates work covered by the following copyright and * permission notice: * The Synopsys DWC ETHER XGMAC Software Driver and documentation * (hereinafter "Software") is an unsupported proprietary work of Synopsys, * Inc. unless otherwise expressly agreed to in writing between Synopsys * and you. * * The Software IS NOT an item of Licensed Software or Licensed Product * under any End User Software License Agreement or Agreement for Licensed * Product with Synopsys or any supplement thereto. Permission is hereby * granted, free of charge, to any person obtaining a copy of this software * annotated with this license and the Software, to deal in the Software * without restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished * to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ -#include -#include -#include -#include -#include -#include -#include +#include +__FBSDID("$FreeBSD$"); +#include +#include + #include "xgbe.h" #include "xgbe-common.h" +static void xgbe_an_state_machine(struct xgbe_prv_data *pdata); + static void xgbe_an_enable_kr_training(struct xgbe_prv_data *pdata) { unsigned int reg; reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); reg |= XGBE_KR_TRAINING_ENABLE; XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); } static void xgbe_an_disable_kr_training(struct xgbe_prv_data *pdata) { unsigned int reg; reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); reg &= ~XGBE_KR_TRAINING_ENABLE; XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); } static void xgbe_pcs_power_cycle(struct xgbe_prv_data *pdata) { unsigned int reg; reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); reg |= MDIO_CTRL1_LPOWER; XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); - usleep_range(75, 100); + DELAY(75); reg &= ~MDIO_CTRL1_LPOWER; XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); } static void xgbe_serdes_start_ratechange(struct xgbe_prv_data *pdata) { /* Assert Rx and Tx ratechange */ XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 1); } static void xgbe_serdes_complete_ratechange(struct xgbe_prv_data *pdata) { unsigned int wait; u16 status; /* Release Rx and Tx ratechange */ XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 0); /* Wait for Rx and Tx ready */ wait = XGBE_RATECHANGE_COUNT; while (wait--) { - usleep_range(50, 75); + DELAY(50); status = XSIR0_IOREAD(pdata, SIR0_STATUS); if (XSIR_GET_BITS(status, SIR0_STATUS, RX_READY) && XSIR_GET_BITS(status, SIR0_STATUS, TX_READY)) goto rx_reset; } - netif_dbg(pdata, link, pdata->netdev, "SerDes rx/tx not ready (%#hx)\n", - status); - rx_reset: /* Perform Rx reset for the DFE changes */ XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 0); XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 1); } static void xgbe_xgmii_mode(struct xgbe_prv_data *pdata) { unsigned int reg; /* Enable KR training */ xgbe_an_enable_kr_training(pdata); /* Set MAC to 10G speed */ pdata->hw_if.set_xgmii_speed(pdata); /* Set PCS to KR/10G speed */ reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); reg &= ~MDIO_PCS_CTRL2_TYPE; reg |= MDIO_PCS_CTRL2_10GBR; XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg); reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); reg &= ~MDIO_CTRL1_SPEEDSEL; reg |= MDIO_CTRL1_SPEED10G; XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); xgbe_pcs_power_cycle(pdata); /* Set SerDes to 10G speed */ xgbe_serdes_start_ratechange(pdata); XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_10000_RATE); XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_10000_WORD); XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_10000_PLL); XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE, pdata->serdes_cdr_rate[XGBE_SPEED_10000]); XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP, pdata->serdes_tx_amp[XGBE_SPEED_10000]); XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA, pdata->serdes_blwc[XGBE_SPEED_10000]); XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG, pdata->serdes_pq_skew[XGBE_SPEED_10000]); XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG, pdata->serdes_dfe_tap_cfg[XGBE_SPEED_10000]); XRXTX_IOWRITE(pdata, RXTX_REG22, pdata->serdes_dfe_tap_ena[XGBE_SPEED_10000]); xgbe_serdes_complete_ratechange(pdata); - - netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n"); } static void xgbe_gmii_2500_mode(struct xgbe_prv_data *pdata) { unsigned int reg; /* Disable KR training */ xgbe_an_disable_kr_training(pdata); /* Set MAC to 2.5G speed */ pdata->hw_if.set_gmii_2500_speed(pdata); /* Set PCS to KX/1G speed */ reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); reg &= ~MDIO_PCS_CTRL2_TYPE; reg |= MDIO_PCS_CTRL2_10GBX; XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg); reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); reg &= ~MDIO_CTRL1_SPEEDSEL; reg |= MDIO_CTRL1_SPEED1G; XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); xgbe_pcs_power_cycle(pdata); /* Set SerDes to 2.5G speed */ xgbe_serdes_start_ratechange(pdata); XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_2500_RATE); XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_2500_WORD); XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_2500_PLL); XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE, pdata->serdes_cdr_rate[XGBE_SPEED_2500]); XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP, pdata->serdes_tx_amp[XGBE_SPEED_2500]); XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA, pdata->serdes_blwc[XGBE_SPEED_2500]); XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG, pdata->serdes_pq_skew[XGBE_SPEED_2500]); XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG, pdata->serdes_dfe_tap_cfg[XGBE_SPEED_2500]); XRXTX_IOWRITE(pdata, RXTX_REG22, pdata->serdes_dfe_tap_ena[XGBE_SPEED_2500]); xgbe_serdes_complete_ratechange(pdata); - - netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n"); } static void xgbe_gmii_mode(struct xgbe_prv_data *pdata) { unsigned int reg; /* Disable KR training */ xgbe_an_disable_kr_training(pdata); /* Set MAC to 1G speed */ pdata->hw_if.set_gmii_speed(pdata); /* Set PCS to KX/1G speed */ reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); reg &= ~MDIO_PCS_CTRL2_TYPE; reg |= MDIO_PCS_CTRL2_10GBX; XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg); reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); reg &= ~MDIO_CTRL1_SPEEDSEL; reg |= MDIO_CTRL1_SPEED1G; XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); xgbe_pcs_power_cycle(pdata); /* Set SerDes to 1G speed */ xgbe_serdes_start_ratechange(pdata); XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_1000_RATE); XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_1000_WORD); XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_1000_PLL); XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE, pdata->serdes_cdr_rate[XGBE_SPEED_1000]); XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP, pdata->serdes_tx_amp[XGBE_SPEED_1000]); XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA, pdata->serdes_blwc[XGBE_SPEED_1000]); XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG, pdata->serdes_pq_skew[XGBE_SPEED_1000]); XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG, pdata->serdes_dfe_tap_cfg[XGBE_SPEED_1000]); XRXTX_IOWRITE(pdata, RXTX_REG22, pdata->serdes_dfe_tap_ena[XGBE_SPEED_1000]); xgbe_serdes_complete_ratechange(pdata); - - netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n"); } static void xgbe_cur_mode(struct xgbe_prv_data *pdata, enum xgbe_mode *mode) { unsigned int reg; reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); if ((reg & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR) *mode = XGBE_MODE_KR; else *mode = XGBE_MODE_KX; } static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata) { enum xgbe_mode mode; xgbe_cur_mode(pdata, &mode); return (mode == XGBE_MODE_KR); } static void xgbe_switch_mode(struct xgbe_prv_data *pdata) { /* If we are in KR switch to KX, and vice-versa */ if (xgbe_in_kr_mode(pdata)) { if (pdata->speed_set == XGBE_SPEEDSET_1000_10000) xgbe_gmii_mode(pdata); else xgbe_gmii_2500_mode(pdata); } else { xgbe_xgmii_mode(pdata); } } static void xgbe_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) { enum xgbe_mode cur_mode; xgbe_cur_mode(pdata, &cur_mode); if (mode != cur_mode) xgbe_switch_mode(pdata); } static bool xgbe_use_xgmii_mode(struct xgbe_prv_data *pdata) { if (pdata->phy.autoneg == AUTONEG_ENABLE) { if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full) return true; } else { if (pdata->phy.speed == SPEED_10000) return true; } return false; } static bool xgbe_use_gmii_2500_mode(struct xgbe_prv_data *pdata) { if (pdata->phy.autoneg == AUTONEG_ENABLE) { if (pdata->phy.advertising & ADVERTISED_2500baseX_Full) return true; } else { if (pdata->phy.speed == SPEED_2500) return true; } return false; } static bool xgbe_use_gmii_mode(struct xgbe_prv_data *pdata) { if (pdata->phy.autoneg == AUTONEG_ENABLE) { if (pdata->phy.advertising & ADVERTISED_1000baseKX_Full) return true; } else { if (pdata->phy.speed == SPEED_1000) return true; } return false; } static void xgbe_set_an(struct xgbe_prv_data *pdata, bool enable, bool restart) { unsigned int reg; reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1); reg &= ~MDIO_AN_CTRL1_ENABLE; if (enable) reg |= MDIO_AN_CTRL1_ENABLE; if (restart) reg |= MDIO_AN_CTRL1_RESTART; XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg); } static void xgbe_restart_an(struct xgbe_prv_data *pdata) { xgbe_set_an(pdata, true, true); - - netif_dbg(pdata, link, pdata->netdev, "AN enabled/restarted\n"); } static void xgbe_disable_an(struct xgbe_prv_data *pdata) { xgbe_set_an(pdata, false, false); - - netif_dbg(pdata, link, pdata->netdev, "AN disabled\n"); } static enum xgbe_an xgbe_an_tx_training(struct xgbe_prv_data *pdata, enum xgbe_rx *state) { unsigned int ad_reg, lp_reg, reg; *state = XGBE_RX_COMPLETE; /* If we're not in KR mode then we're done */ if (!xgbe_in_kr_mode(pdata)) return XGBE_AN_PAGE_RECEIVED; /* Enable/Disable FEC */ ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL); reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE); if ((ad_reg & 0xc000) && (lp_reg & 0xc000)) reg |= pdata->fec_ability; XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg); /* Start KR training */ reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); if (reg & XGBE_KR_TRAINING_ENABLE) { XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 1); reg |= XGBE_KR_TRAINING_START; XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 0); - - netif_dbg(pdata, link, pdata->netdev, - "KR training initiated\n"); } return XGBE_AN_PAGE_RECEIVED; } static enum xgbe_an xgbe_an_tx_xnp(struct xgbe_prv_data *pdata, enum xgbe_rx *state) { u16 msg; *state = XGBE_RX_XNP; msg = XGBE_XNP_MCF_NULL_MESSAGE; msg |= XGBE_XNP_MP_FORMATTED; XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0); XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0); XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg); return XGBE_AN_PAGE_RECEIVED; } static enum xgbe_an xgbe_an_rx_bpa(struct xgbe_prv_data *pdata, enum xgbe_rx *state) { unsigned int link_support; unsigned int reg, ad_reg, lp_reg; /* Read Base Ability register 2 first */ reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); /* Check for a supported mode, otherwise restart in a different one */ link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20; if (!(reg & link_support)) return XGBE_AN_INCOMPAT_LINK; /* Check Extended Next Page support */ ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); return ((ad_reg & XGBE_XNP_NP_EXCHANGE) || (lp_reg & XGBE_XNP_NP_EXCHANGE)) ? xgbe_an_tx_xnp(pdata, state) : xgbe_an_tx_training(pdata, state); } static enum xgbe_an xgbe_an_rx_xnp(struct xgbe_prv_data *pdata, enum xgbe_rx *state) { unsigned int ad_reg, lp_reg; /* Check Extended Next Page support */ ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP); lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX); return ((ad_reg & XGBE_XNP_NP_EXCHANGE) || (lp_reg & XGBE_XNP_NP_EXCHANGE)) ? xgbe_an_tx_xnp(pdata, state) : xgbe_an_tx_training(pdata, state); } static enum xgbe_an xgbe_an_page_received(struct xgbe_prv_data *pdata) { enum xgbe_rx *state; unsigned long an_timeout; enum xgbe_an ret; if (!pdata->an_start) { - pdata->an_start = jiffies; + pdata->an_start = ticks; } else { an_timeout = pdata->an_start + - msecs_to_jiffies(XGBE_AN_MS_TIMEOUT); - if (time_after(jiffies, an_timeout)) { + ((uint64_t)XGBE_AN_MS_TIMEOUT * (uint64_t)hz) / 1000ull; + if ((int)(ticks - an_timeout) > 0) { /* Auto-negotiation timed out, reset state */ pdata->kr_state = XGBE_RX_BPA; pdata->kx_state = XGBE_RX_BPA; - pdata->an_start = jiffies; - - netif_dbg(pdata, link, pdata->netdev, - "AN timed out, resetting state\n"); + pdata->an_start = ticks; } } state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state : &pdata->kx_state; switch (*state) { case XGBE_RX_BPA: ret = xgbe_an_rx_bpa(pdata, state); break; case XGBE_RX_XNP: ret = xgbe_an_rx_xnp(pdata, state); break; default: ret = XGBE_AN_ERROR; } return ret; } static enum xgbe_an xgbe_an_incompat_link(struct xgbe_prv_data *pdata) { /* Be sure we aren't looping trying to negotiate */ if (xgbe_in_kr_mode(pdata)) { pdata->kr_state = XGBE_RX_ERROR; if (!(pdata->phy.advertising & ADVERTISED_1000baseKX_Full) && !(pdata->phy.advertising & ADVERTISED_2500baseX_Full)) return XGBE_AN_NO_LINK; if (pdata->kx_state != XGBE_RX_BPA) return XGBE_AN_NO_LINK; } else { pdata->kx_state = XGBE_RX_ERROR; if (!(pdata->phy.advertising & ADVERTISED_10000baseKR_Full)) return XGBE_AN_NO_LINK; if (pdata->kr_state != XGBE_RX_BPA) return XGBE_AN_NO_LINK; } xgbe_disable_an(pdata); xgbe_switch_mode(pdata); xgbe_restart_an(pdata); return XGBE_AN_INCOMPAT_LINK; } -static irqreturn_t xgbe_an_isr(int irq, void *data) +static void xgbe_an_isr(void *data) { struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data; - netif_dbg(pdata, intr, pdata->netdev, "AN interrupt received\n"); - /* Disable AN interrupts */ XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0); /* Save the interrupt(s) that fired */ pdata->an_int = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT); if (pdata->an_int) { /* Clear the interrupt(s) that fired and process them */ XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, ~pdata->an_int); - queue_work(pdata->an_workqueue, &pdata->an_irq_work); + xgbe_an_state_machine(pdata); } else { /* Enable AN interrupts */ XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_INT_MASK); } - - return IRQ_HANDLED; } -static void xgbe_an_irq_work(struct work_struct *work) +static void xgbe_an_state_machine(struct xgbe_prv_data *pdata) { - struct xgbe_prv_data *pdata = container_of(work, - struct xgbe_prv_data, - an_irq_work); - - /* Avoid a race between enabling the IRQ and exiting the work by - * waiting for the work to finish and then queueing it - */ - flush_work(&pdata->an_work); - queue_work(pdata->an_workqueue, &pdata->an_work); -} - -static const char *xgbe_state_as_string(enum xgbe_an state) -{ - switch (state) { - case XGBE_AN_READY: - return "Ready"; - case XGBE_AN_PAGE_RECEIVED: - return "Page-Received"; - case XGBE_AN_INCOMPAT_LINK: - return "Incompatible-Link"; - case XGBE_AN_COMPLETE: - return "Complete"; - case XGBE_AN_NO_LINK: - return "No-Link"; - case XGBE_AN_ERROR: - return "Error"; - default: - return "Undefined"; - } -} - -static void xgbe_an_state_machine(struct work_struct *work) -{ - struct xgbe_prv_data *pdata = container_of(work, - struct xgbe_prv_data, - an_work); enum xgbe_an cur_state = pdata->an_state; - mutex_lock(&pdata->an_mutex); + sx_xlock(&pdata->an_mutex); if (!pdata->an_int) goto out; next_int: if (pdata->an_int & XGBE_AN_PG_RCV) { pdata->an_state = XGBE_AN_PAGE_RECEIVED; pdata->an_int &= ~XGBE_AN_PG_RCV; } else if (pdata->an_int & XGBE_AN_INC_LINK) { pdata->an_state = XGBE_AN_INCOMPAT_LINK; pdata->an_int &= ~XGBE_AN_INC_LINK; } else if (pdata->an_int & XGBE_AN_INT_CMPLT) { pdata->an_state = XGBE_AN_COMPLETE; pdata->an_int &= ~XGBE_AN_INT_CMPLT; } else { pdata->an_state = XGBE_AN_ERROR; } pdata->an_result = pdata->an_state; again: - netif_dbg(pdata, link, pdata->netdev, "AN %s\n", - xgbe_state_as_string(pdata->an_state)); - cur_state = pdata->an_state; switch (pdata->an_state) { case XGBE_AN_READY: pdata->an_supported = 0; break; case XGBE_AN_PAGE_RECEIVED: pdata->an_state = xgbe_an_page_received(pdata); pdata->an_supported++; break; case XGBE_AN_INCOMPAT_LINK: pdata->an_supported = 0; pdata->parallel_detect = 0; pdata->an_state = xgbe_an_incompat_link(pdata); break; case XGBE_AN_COMPLETE: pdata->parallel_detect = pdata->an_supported ? 0 : 1; - netif_dbg(pdata, link, pdata->netdev, "%s successful\n", - pdata->an_supported ? "Auto negotiation" - : "Parallel detection"); break; case XGBE_AN_NO_LINK: break; default: pdata->an_state = XGBE_AN_ERROR; } if (pdata->an_state == XGBE_AN_NO_LINK) { pdata->an_int = 0; XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); } else if (pdata->an_state == XGBE_AN_ERROR) { - netdev_err(pdata->netdev, - "error during auto-negotiation, state=%u\n", - cur_state); - pdata->an_int = 0; XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); } if (pdata->an_state >= XGBE_AN_COMPLETE) { pdata->an_result = pdata->an_state; pdata->an_state = XGBE_AN_READY; pdata->kr_state = XGBE_RX_BPA; pdata->kx_state = XGBE_RX_BPA; pdata->an_start = 0; - - netif_dbg(pdata, link, pdata->netdev, "AN result: %s\n", - xgbe_state_as_string(pdata->an_result)); } if (cur_state != pdata->an_state) goto again; if (pdata->an_int) goto next_int; out: /* Enable AN interrupts on the way out */ XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_INT_MASK); - mutex_unlock(&pdata->an_mutex); + sx_xunlock(&pdata->an_mutex); } static void xgbe_an_init(struct xgbe_prv_data *pdata) { unsigned int reg; /* Set up Advertisement register 3 first */ reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); - if (pdata->phy.advertising & ADVERTISED_10000baseR_FEC) - reg |= 0xc000; - else - reg &= ~0xc000; + reg &= ~0xc000; XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg); /* Set up Advertisement register 2 next */ reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full) reg |= 0x80; else reg &= ~0x80; if ((pdata->phy.advertising & ADVERTISED_1000baseKX_Full) || (pdata->phy.advertising & ADVERTISED_2500baseX_Full)) reg |= 0x20; else reg &= ~0x20; XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg); /* Set up Advertisement register 1 last */ reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); if (pdata->phy.advertising & ADVERTISED_Pause) reg |= 0x400; else reg &= ~0x400; if (pdata->phy.advertising & ADVERTISED_Asym_Pause) reg |= 0x800; else reg &= ~0x800; /* We don't intend to perform XNP */ reg &= ~XGBE_XNP_NP_EXCHANGE; XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg); - - netif_dbg(pdata, link, pdata->netdev, "AN initialized\n"); } -static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata) -{ - if (pdata->tx_pause && pdata->rx_pause) - return "rx/tx"; - else if (pdata->rx_pause) - return "rx"; - else if (pdata->tx_pause) - return "tx"; - else - return "off"; -} - -static const char *xgbe_phy_speed_string(int speed) -{ - switch (speed) { - case SPEED_1000: - return "1Gbps"; - case SPEED_2500: - return "2.5Gbps"; - case SPEED_10000: - return "10Gbps"; - case SPEED_UNKNOWN: - return "Unknown"; - default: - return "Unsupported"; - } -} - -static void xgbe_phy_print_status(struct xgbe_prv_data *pdata) -{ - if (pdata->phy.link) - netdev_info(pdata->netdev, - "Link is Up - %s/%s - flow control %s\n", - xgbe_phy_speed_string(pdata->phy.speed), - pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half", - xgbe_phy_fc_string(pdata)); - else - netdev_info(pdata->netdev, "Link is Down\n"); -} - static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata) { int new_state = 0; if (pdata->phy.link) { /* Flow control support */ pdata->pause_autoneg = pdata->phy.pause_autoneg; if (pdata->tx_pause != pdata->phy.tx_pause) { new_state = 1; pdata->hw_if.config_tx_flow_control(pdata); pdata->tx_pause = pdata->phy.tx_pause; } if (pdata->rx_pause != pdata->phy.rx_pause) { new_state = 1; pdata->hw_if.config_rx_flow_control(pdata); pdata->rx_pause = pdata->phy.rx_pause; } /* Speed support */ if (pdata->phy_speed != pdata->phy.speed) { new_state = 1; pdata->phy_speed = pdata->phy.speed; } if (pdata->phy_link != pdata->phy.link) { new_state = 1; pdata->phy_link = pdata->phy.link; } } else if (pdata->phy_link) { new_state = 1; pdata->phy_link = 0; pdata->phy_speed = SPEED_UNKNOWN; } - - if (new_state && netif_msg_link(pdata)) - xgbe_phy_print_status(pdata); } static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata) { - netif_dbg(pdata, link, pdata->netdev, "fixed PHY configuration\n"); /* Disable auto-negotiation */ xgbe_disable_an(pdata); /* Validate/Set specified speed */ switch (pdata->phy.speed) { case SPEED_10000: xgbe_set_mode(pdata, XGBE_MODE_KR); break; case SPEED_2500: case SPEED_1000: xgbe_set_mode(pdata, XGBE_MODE_KX); break; default: return -EINVAL; } /* Validate duplex mode */ if (pdata->phy.duplex != DUPLEX_FULL) return -EINVAL; return 0; } static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata) { set_bit(XGBE_LINK_INIT, &pdata->dev_state); - pdata->link_check = jiffies; + pdata->link_check = ticks; if (pdata->phy.autoneg != AUTONEG_ENABLE) return xgbe_phy_config_fixed(pdata); - netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n"); - /* Disable auto-negotiation interrupt */ - disable_irq(pdata->an_irq); + XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0); + /* Clear any auto-negotitation interrupts */ + XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); + /* Start auto-negotiation in a supported mode */ if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full) { xgbe_set_mode(pdata, XGBE_MODE_KR); } else if ((pdata->phy.advertising & ADVERTISED_1000baseKX_Full) || (pdata->phy.advertising & ADVERTISED_2500baseX_Full)) { xgbe_set_mode(pdata, XGBE_MODE_KX); } else { - enable_irq(pdata->an_irq); + XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0x07); return -EINVAL; } /* Disable and stop any in progress auto-negotiation */ xgbe_disable_an(pdata); /* Clear any auto-negotitation interrupts */ XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); pdata->an_result = XGBE_AN_READY; pdata->an_state = XGBE_AN_READY; pdata->kr_state = XGBE_RX_BPA; pdata->kx_state = XGBE_RX_BPA; /* Re-enable auto-negotiation interrupt */ - enable_irq(pdata->an_irq); + XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0x07); /* Set up advertisement registers based on current settings */ xgbe_an_init(pdata); /* Enable and start auto-negotiation */ xgbe_restart_an(pdata); return 0; } static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata) { int ret; - mutex_lock(&pdata->an_mutex); + sx_xlock(&pdata->an_mutex); ret = __xgbe_phy_config_aneg(pdata); if (ret) set_bit(XGBE_LINK_ERR, &pdata->dev_state); else clear_bit(XGBE_LINK_ERR, &pdata->dev_state); - mutex_unlock(&pdata->an_mutex); + sx_unlock(&pdata->an_mutex); return ret; } static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata) { return (pdata->an_result == XGBE_AN_COMPLETE); } static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata) { unsigned long link_timeout; - link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ); - if (time_after(jiffies, link_timeout)) { - netif_dbg(pdata, link, pdata->netdev, "AN link timeout\n"); + link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * hz); + if ((int)(ticks - link_timeout) >= 0) { xgbe_phy_config_aneg(pdata); } } static void xgbe_phy_status_force(struct xgbe_prv_data *pdata) { if (xgbe_in_kr_mode(pdata)) { pdata->phy.speed = SPEED_10000; } else { switch (pdata->speed_set) { case XGBE_SPEEDSET_1000_10000: pdata->phy.speed = SPEED_1000; break; case XGBE_SPEEDSET_2500_10000: pdata->phy.speed = SPEED_2500; break; } } pdata->phy.duplex = DUPLEX_FULL; } static void xgbe_phy_status_aneg(struct xgbe_prv_data *pdata) { unsigned int ad_reg, lp_reg; pdata->phy.lp_advertising = 0; if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect) return xgbe_phy_status_force(pdata); pdata->phy.lp_advertising |= ADVERTISED_Autoneg; pdata->phy.lp_advertising |= ADVERTISED_Backplane; /* Compare Advertisement and Link Partner register 1 */ ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); if (lp_reg & 0x400) pdata->phy.lp_advertising |= ADVERTISED_Pause; if (lp_reg & 0x800) pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause; if (pdata->phy.pause_autoneg) { /* Set flow control based on auto-negotiation result */ pdata->phy.tx_pause = 0; pdata->phy.rx_pause = 0; if (ad_reg & lp_reg & 0x400) { pdata->phy.tx_pause = 1; pdata->phy.rx_pause = 1; } else if (ad_reg & lp_reg & 0x800) { if (ad_reg & 0x400) pdata->phy.rx_pause = 1; else if (lp_reg & 0x400) pdata->phy.tx_pause = 1; } } /* Compare Advertisement and Link Partner register 2 */ ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); if (lp_reg & 0x80) pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; if (lp_reg & 0x20) { switch (pdata->speed_set) { case XGBE_SPEEDSET_1000_10000: pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; break; case XGBE_SPEEDSET_2500_10000: pdata->phy.lp_advertising |= ADVERTISED_2500baseX_Full; break; } } ad_reg &= lp_reg; if (ad_reg & 0x80) { pdata->phy.speed = SPEED_10000; xgbe_set_mode(pdata, XGBE_MODE_KR); } else if (ad_reg & 0x20) { switch (pdata->speed_set) { case XGBE_SPEEDSET_1000_10000: pdata->phy.speed = SPEED_1000; break; case XGBE_SPEEDSET_2500_10000: pdata->phy.speed = SPEED_2500; break; } xgbe_set_mode(pdata, XGBE_MODE_KX); } else { pdata->phy.speed = SPEED_UNKNOWN; } /* Compare Advertisement and Link Partner register 3 */ ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); - if (lp_reg & 0xc000) - pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; - - pdata->phy.duplex = DUPLEX_FULL; } static void xgbe_phy_status(struct xgbe_prv_data *pdata) { unsigned int reg, link_aneg; if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) { - netif_carrier_off(pdata->netdev); - pdata->phy.link = 0; goto adjust_link; } link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE); /* Get the link status. Link status is latched low, so read * once to clear and then read again to get current state */ reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); pdata->phy.link = (reg & MDIO_STAT1_LSTATUS) ? 1 : 0; if (pdata->phy.link) { if (link_aneg && !xgbe_phy_aneg_done(pdata)) { xgbe_check_link_timeout(pdata); return; } xgbe_phy_status_aneg(pdata); if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) clear_bit(XGBE_LINK_INIT, &pdata->dev_state); - - netif_carrier_on(pdata->netdev); } else { if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) { xgbe_check_link_timeout(pdata); if (link_aneg) return; } xgbe_phy_status_aneg(pdata); - - netif_carrier_off(pdata->netdev); } adjust_link: xgbe_phy_adjust_link(pdata); } static void xgbe_phy_stop(struct xgbe_prv_data *pdata) { - netif_dbg(pdata, link, pdata->netdev, "stopping PHY\n"); /* Disable auto-negotiation */ xgbe_disable_an(pdata); /* Disable auto-negotiation interrupts */ XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0); - devm_free_irq(pdata->dev, pdata->an_irq, pdata); + bus_teardown_intr(pdata->dev, pdata->an_irq_res, pdata->an_irq_tag); pdata->phy.link = 0; - netif_carrier_off(pdata->netdev); xgbe_phy_adjust_link(pdata); } static int xgbe_phy_start(struct xgbe_prv_data *pdata) { - struct net_device *netdev = pdata->netdev; int ret; - netif_dbg(pdata, link, pdata->netdev, "starting PHY\n"); - - ret = devm_request_irq(pdata->dev, pdata->an_irq, - xgbe_an_isr, 0, pdata->an_name, - pdata); + ret = bus_setup_intr(pdata->dev, pdata->an_irq_res, + INTR_MPSAFE | INTR_TYPE_NET, NULL, xgbe_an_isr, pdata, + &pdata->an_irq_tag); if (ret) { - netdev_err(netdev, "phy irq request failed\n"); - return ret; + return -ret; } /* Set initial mode - call the mode setting routines * directly to insure we are properly configured */ if (xgbe_use_xgmii_mode(pdata)) { xgbe_xgmii_mode(pdata); } else if (xgbe_use_gmii_mode(pdata)) { xgbe_gmii_mode(pdata); } else if (xgbe_use_gmii_2500_mode(pdata)) { xgbe_gmii_2500_mode(pdata); } else { ret = -EINVAL; goto err_irq; } /* Set up advertisement registers based on current settings */ xgbe_an_init(pdata); /* Enable auto-negotiation interrupts */ XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0x07); return xgbe_phy_config_aneg(pdata); err_irq: - devm_free_irq(pdata->dev, pdata->an_irq, pdata); + bus_teardown_intr(pdata->dev, pdata->an_irq_res, pdata->an_irq_tag); return ret; } static int xgbe_phy_reset(struct xgbe_prv_data *pdata) { unsigned int count, reg; reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); reg |= MDIO_CTRL1_RESET; XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); count = 50; do { - msleep(20); + DELAY(20); reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); } while ((reg & MDIO_CTRL1_RESET) && --count); if (reg & MDIO_CTRL1_RESET) return -ETIMEDOUT; /* Disable auto-negotiation for now */ xgbe_disable_an(pdata); /* Clear auto-negotiation interrupts */ XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); return 0; } -static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata) -{ - struct device *dev = pdata->dev; - - dev_dbg(dev, "\n************* PHY Reg dump **********************\n"); - - dev_dbg(dev, "PCS Control Reg (%#04x) = %#04x\n", MDIO_CTRL1, - XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1)); - dev_dbg(dev, "PCS Status Reg (%#04x) = %#04x\n", MDIO_STAT1, - XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1)); - dev_dbg(dev, "Phy Id (PHYS ID 1 %#04x)= %#04x\n", MDIO_DEVID1, - XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1)); - dev_dbg(dev, "Phy Id (PHYS ID 2 %#04x)= %#04x\n", MDIO_DEVID2, - XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2)); - dev_dbg(dev, "Devices in Package (%#04x)= %#04x\n", MDIO_DEVS1, - XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1)); - dev_dbg(dev, "Devices in Package (%#04x)= %#04x\n", MDIO_DEVS2, - XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2)); - - dev_dbg(dev, "Auto-Neg Control Reg (%#04x) = %#04x\n", MDIO_CTRL1, - XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1)); - dev_dbg(dev, "Auto-Neg Status Reg (%#04x) = %#04x\n", MDIO_STAT1, - XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1)); - dev_dbg(dev, "Auto-Neg Ad Reg 1 (%#04x) = %#04x\n", - MDIO_AN_ADVERTISE, - XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE)); - dev_dbg(dev, "Auto-Neg Ad Reg 2 (%#04x) = %#04x\n", - MDIO_AN_ADVERTISE + 1, - XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1)); - dev_dbg(dev, "Auto-Neg Ad Reg 3 (%#04x) = %#04x\n", - MDIO_AN_ADVERTISE + 2, - XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2)); - dev_dbg(dev, "Auto-Neg Completion Reg (%#04x) = %#04x\n", - MDIO_AN_COMP_STAT, - XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT)); - - dev_dbg(dev, "\n*************************************************\n"); -} - static void xgbe_phy_init(struct xgbe_prv_data *pdata) { - mutex_init(&pdata->an_mutex); - INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work); - INIT_WORK(&pdata->an_work, xgbe_an_state_machine); + sx_init(&pdata->an_mutex, "axgbe AN lock"); pdata->mdio_mmd = MDIO_MMD_PCS; /* Initialize supported features */ pdata->phy.supported = SUPPORTED_Autoneg; pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; pdata->phy.supported |= SUPPORTED_Backplane; pdata->phy.supported |= SUPPORTED_10000baseKR_Full; switch (pdata->speed_set) { case XGBE_SPEEDSET_1000_10000: pdata->phy.supported |= SUPPORTED_1000baseKX_Full; break; case XGBE_SPEEDSET_2500_10000: pdata->phy.supported |= SUPPORTED_2500baseX_Full; break; } pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECABLE); pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE); if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) pdata->phy.supported |= SUPPORTED_10000baseR_FEC; pdata->phy.advertising = pdata->phy.supported; pdata->phy.address = 0; pdata->phy.autoneg = AUTONEG_ENABLE; pdata->phy.speed = SPEED_UNKNOWN; pdata->phy.duplex = DUPLEX_UNKNOWN; pdata->phy.link = 0; pdata->phy.pause_autoneg = pdata->pause_autoneg; pdata->phy.tx_pause = pdata->tx_pause; pdata->phy.rx_pause = pdata->rx_pause; /* Fix up Flow Control advertising */ pdata->phy.advertising &= ~ADVERTISED_Pause; pdata->phy.advertising &= ~ADVERTISED_Asym_Pause; if (pdata->rx_pause) { pdata->phy.advertising |= ADVERTISED_Pause; pdata->phy.advertising |= ADVERTISED_Asym_Pause; } if (pdata->tx_pause) pdata->phy.advertising ^= ADVERTISED_Asym_Pause; - - if (netif_msg_drv(pdata)) - xgbe_dump_phy_registers(pdata); } void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if) { phy_if->phy_init = xgbe_phy_init; phy_if->phy_reset = xgbe_phy_reset; phy_if->phy_start = xgbe_phy_start; phy_if->phy_stop = xgbe_phy_stop; phy_if->phy_status = xgbe_phy_status; phy_if->phy_config_aneg = xgbe_phy_config_aneg; } Property changes on: head/sys/dev/axgbe/xgbe-mdio.c ___________________________________________________________________ Deleted: fbsd:nokeywords ## -1 +0,0 ## -yes \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/dev/axgbe/xgbe.h =================================================================== --- head/sys/dev/axgbe/xgbe.h (revision 313767) +++ head/sys/dev/axgbe/xgbe.h (revision 313768) @@ -1,1005 +1,889 @@ /* * AMD 10Gb Ethernet driver * * This file is available to you under your choice of the following two * licenses: * * License 1: GPLv2 * * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. * * This file is free software; you may copy, redistribute and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 2 of the License, or (at * your option) any later version. * * This file is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see . * * This file incorporates work covered by the following copyright and * permission notice: * The Synopsys DWC ETHER XGMAC Software Driver and documentation * (hereinafter "Software") is an unsupported proprietary work of Synopsys, * Inc. unless otherwise expressly agreed to in writing between Synopsys * and you. * * The Software IS NOT an item of Licensed Software or Licensed Product * under any End User Software License Agreement or Agreement for Licensed * Product with Synopsys or any supplement thereto. Permission is hereby * granted, free of charge, to any person obtaining a copy of this software * annotated with this license and the Software, to deal in the Software * without restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished * to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * * License 2: Modified BSD * * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Advanced Micro Devices, Inc. nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * This file incorporates work covered by the following copyright and * permission notice: * The Synopsys DWC ETHER XGMAC Software Driver and documentation * (hereinafter "Software") is an unsupported proprietary work of Synopsys, * Inc. unless otherwise expressly agreed to in writing between Synopsys * and you. * * The Software IS NOT an item of Licensed Software or Licensed Product * under any End User Software License Agreement or Agreement for Licensed * Product with Synopsys or any supplement thereto. Permission is hereby * granted, free of charge, to any person obtaining a copy of this software * annotated with this license and the Software, to deal in the Software * without restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished * to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ */ #ifndef __XGBE_H__ #define __XGBE_H__ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include "xgbe_osdep.h" +/* From linux/dcbnl.h */ +#define IEEE_8021QAZ_MAX_TCS 8 + #define XGBE_DRV_NAME "amd-xgbe" #define XGBE_DRV_VERSION "1.0.2" #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver" /* Descriptor related defines */ #define XGBE_TX_DESC_CNT 512 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3) #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1) #define XGBE_RX_DESC_CNT 512 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) /* Descriptors required for maximum contiguous TSO/GSO packet */ #define XGBE_TX_MAX_SPLIT ((GSO_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1) /* Maximum possible descriptors needed for an SKB: * - Maximum number of SKB frags * - Maximum descriptors for contiguous TSO/GSO packet * - Possible context descriptor * - Possible TSO header descriptor */ #define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2) -#define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) +#define XGBE_RX_MIN_BUF_SIZE 1522 #define XGBE_RX_BUF_ALIGN 64 #define XGBE_SKB_ALLOC_SIZE 256 #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */ #define XGBE_MAX_DMA_CHANNELS 16 #define XGBE_MAX_QUEUES 16 #define XGBE_DMA_STOP_TIMEOUT 5 /* DMA cache settings - Outer sharable, write-back, write-allocate */ #define XGBE_DMA_OS_AXDOMAIN 0x2 #define XGBE_DMA_OS_ARCACHE 0xb #define XGBE_DMA_OS_AWCACHE 0xf /* DMA cache settings - System, no caches used */ #define XGBE_DMA_SYS_AXDOMAIN 0x3 #define XGBE_DMA_SYS_ARCACHE 0x0 #define XGBE_DMA_SYS_AWCACHE 0x0 #define XGBE_DMA_INTERRUPT_MASK 0x31c7 #define XGMAC_MIN_PACKET 60 #define XGMAC_STD_PACKET_MTU 1500 #define XGMAC_MAX_STD_PACKET 1518 #define XGMAC_JUMBO_PACKET_MTU 9000 #define XGMAC_MAX_JUMBO_PACKET 9018 /* Common property names */ #define XGBE_MAC_ADDR_PROPERTY "mac-address" #define XGBE_PHY_MODE_PROPERTY "phy-mode" #define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt" #define XGBE_SPEEDSET_PROPERTY "amd,speed-set" #define XGBE_BLWC_PROPERTY "amd,serdes-blwc" #define XGBE_CDR_RATE_PROPERTY "amd,serdes-cdr-rate" #define XGBE_PQ_SKEW_PROPERTY "amd,serdes-pq-skew" #define XGBE_TX_AMP_PROPERTY "amd,serdes-tx-amp" #define XGBE_DFE_CFG_PROPERTY "amd,serdes-dfe-tap-config" #define XGBE_DFE_ENA_PROPERTY "amd,serdes-dfe-tap-enable" /* Device-tree clock names */ #define XGBE_DMA_CLOCK "dma_clk" #define XGBE_PTP_CLOCK "ptp_clk" /* ACPI property names */ #define XGBE_ACPI_DMA_FREQ "amd,dma-freq" #define XGBE_ACPI_PTP_FREQ "amd,ptp-freq" /* Timestamp support - values based on 50MHz PTP clock * 50MHz => 20 nsec */ #define XGBE_TSTAMP_SSINC 20 #define XGBE_TSTAMP_SNSINC 0 /* Driver PMT macros */ #define XGMAC_DRIVER_CONTEXT 1 #define XGMAC_IOCTL_CONTEXT 2 #define XGBE_FIFO_MAX 81920 #define XGBE_TC_MIN_QUANTUM 10 /* Helper macro for descriptor handling * Always use XGBE_GET_DESC_DATA to access the descriptor data * since the index is free-running and needs to be and-ed * with the descriptor count value of the ring to index to * the proper descriptor data. */ #define XGBE_GET_DESC_DATA(_ring, _idx) \ ((_ring)->rdata + \ ((_idx) & ((_ring)->rdesc_count - 1))) /* Default coalescing parameters */ #define XGMAC_INIT_DMA_TX_USECS 1000 #define XGMAC_INIT_DMA_TX_FRAMES 25 #define XGMAC_MAX_DMA_RIWT 0xff #define XGMAC_INIT_DMA_RX_USECS 30 #define XGMAC_INIT_DMA_RX_FRAMES 25 /* Flow control queue count */ #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8 /* Maximum MAC address hash table size (256 bits = 8 bytes) */ #define XGBE_MAC_HASH_TABLE_SIZE 8 /* Receive Side Scaling */ #define XGBE_RSS_HASH_KEY_SIZE 40 #define XGBE_RSS_MAX_TABLE_SIZE 256 #define XGBE_RSS_LOOKUP_TABLE_TYPE 0 #define XGBE_RSS_HASH_KEY_TYPE 1 /* Auto-negotiation */ #define XGBE_AN_MS_TIMEOUT 500 #define XGBE_LINK_TIMEOUT 10 #define XGBE_AN_INT_CMPLT 0x01 #define XGBE_AN_INC_LINK 0x02 #define XGBE_AN_PG_RCV 0x04 #define XGBE_AN_INT_MASK 0x07 /* Rate-change complete wait/retry count */ #define XGBE_RATECHANGE_COUNT 500 /* Default SerDes settings */ #define XGBE_SPEED_10000_BLWC 0 #define XGBE_SPEED_10000_CDR 0x7 #define XGBE_SPEED_10000_PLL 0x1 #define XGBE_SPEED_10000_PQ 0x12 #define XGBE_SPEED_10000_RATE 0x0 #define XGBE_SPEED_10000_TXAMP 0xa #define XGBE_SPEED_10000_WORD 0x7 #define XGBE_SPEED_10000_DFE_TAP_CONFIG 0x1 #define XGBE_SPEED_10000_DFE_TAP_ENABLE 0x7f #define XGBE_SPEED_2500_BLWC 1 #define XGBE_SPEED_2500_CDR 0x2 #define XGBE_SPEED_2500_PLL 0x0 #define XGBE_SPEED_2500_PQ 0xa #define XGBE_SPEED_2500_RATE 0x1 #define XGBE_SPEED_2500_TXAMP 0xf #define XGBE_SPEED_2500_WORD 0x1 #define XGBE_SPEED_2500_DFE_TAP_CONFIG 0x3 #define XGBE_SPEED_2500_DFE_TAP_ENABLE 0x0 #define XGBE_SPEED_1000_BLWC 1 #define XGBE_SPEED_1000_CDR 0x2 #define XGBE_SPEED_1000_PLL 0x0 #define XGBE_SPEED_1000_PQ 0xa #define XGBE_SPEED_1000_RATE 0x3 #define XGBE_SPEED_1000_TXAMP 0xf #define XGBE_SPEED_1000_WORD 0x1 #define XGBE_SPEED_1000_DFE_TAP_CONFIG 0x3 #define XGBE_SPEED_1000_DFE_TAP_ENABLE 0x0 struct xgbe_prv_data; struct xgbe_packet_data { - struct sk_buff *skb; + struct mbuf *m; unsigned int attributes; unsigned int errors; unsigned int rdesc_count; unsigned int length; - unsigned int header_len; - unsigned int tcp_header_len; - unsigned int tcp_payload_len; - unsigned short mss; - - unsigned short vlan_ctag; - u64 rx_tstamp; - u32 rss_hash; - enum pkt_hash_types rss_hash_type; - unsigned int tx_packets; unsigned int tx_bytes; }; /* Common Rx and Tx descriptor mapping */ struct xgbe_ring_desc { __le32 desc0; __le32 desc1; __le32 desc2; __le32 desc3; }; -/* Page allocation related values */ -struct xgbe_page_alloc { - struct page *pages; - unsigned int pages_len; - unsigned int pages_offset; - - dma_addr_t pages_dma; -}; - -/* Ring entry buffer data */ -struct xgbe_buffer_data { - struct xgbe_page_alloc pa; - struct xgbe_page_alloc pa_unmap; - - dma_addr_t dma_base; - unsigned long dma_off; - unsigned int dma_len; -}; - /* Tx-related ring data */ struct xgbe_tx_ring_data { unsigned int packets; /* BQL packet count */ unsigned int bytes; /* BQL byte count */ }; /* Rx-related ring data */ struct xgbe_rx_ring_data { - struct xgbe_buffer_data hdr; /* Header locations */ - struct xgbe_buffer_data buf; /* Payload locations */ - unsigned short hdr_len; /* Length of received header */ unsigned short len; /* Length of received packet */ }; /* Structure used to hold information related to the descriptor * and the packet associated with the descriptor (always use * use the XGBE_GET_DESC_DATA macro to access this data from the ring) */ struct xgbe_ring_data { struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */ - dma_addr_t rdesc_dma; /* DMA address of descriptor */ + bus_addr_t rdata_paddr; - struct sk_buff *skb; /* Virtual address of SKB */ - dma_addr_t skb_dma; /* DMA address of SKB data */ - unsigned int skb_dma_len; /* Length of SKB DMA area */ + bus_dma_tag_t mbuf_dmat; + bus_dmamap_t mbuf_map; + bus_addr_t mbuf_hdr_paddr; + bus_addr_t mbuf_data_paddr; + bus_size_t mbuf_len; + int mbuf_free; + struct mbuf *mb; + struct xgbe_tx_ring_data tx; /* Tx-related data */ struct xgbe_rx_ring_data rx; /* Rx-related data */ - - unsigned int mapped_as_page; - - /* Incomplete receive save location. If the budget is exhausted - * or the last descriptor (last normal descriptor or a following - * context descriptor) has not been DMA'd yet the current state - * of the receive processing needs to be saved. - */ - unsigned int state_saved; - struct { - struct sk_buff *skb; - unsigned int len; - unsigned int error; - } state; }; struct xgbe_ring { /* Ring lock - used just for TX rings at the moment */ spinlock_t lock; /* Per packet related information */ struct xgbe_packet_data packet_data; /* Virtual/DMA addresses and count of allocated descriptor memory */ struct xgbe_ring_desc *rdesc; - dma_addr_t rdesc_dma; + bus_dmamap_t rdesc_map; + bus_dma_tag_t rdesc_dmat; + bus_addr_t rdesc_paddr; unsigned int rdesc_count; + bus_dma_tag_t mbuf_dmat; + bus_dmamap_t mbuf_map; + /* Array of descriptor data corresponding the descriptor memory * (always use the XGBE_GET_DESC_DATA macro to access this data) */ struct xgbe_ring_data *rdata; - /* Page allocation for RX buffers */ - struct xgbe_page_alloc rx_hdr_pa; - struct xgbe_page_alloc rx_buf_pa; - /* Ring index values * cur - Tx: index of descriptor to be used for current transfer * Rx: index of descriptor to check for packet availability * dirty - Tx: index of descriptor to check for transfer complete * Rx: index of descriptor to check for buffer reallocation */ unsigned int cur; unsigned int dirty; /* Coalesce frame count used for interrupt bit setting */ unsigned int coalesce_count; union { struct { unsigned int queue_stopped; unsigned int xmit_more; unsigned short cur_mss; unsigned short cur_vlan_ctag; } tx; }; -} ____cacheline_aligned; +} __aligned(CACHE_LINE_SIZE); /* Structure used to describe the descriptor rings associated with * a DMA channel. */ struct xgbe_channel { char name[16]; /* Address of private data area for device */ struct xgbe_prv_data *pdata; /* Queue index and base address of queue's DMA registers */ unsigned int queue_index; - void __iomem *dma_regs; + bus_space_tag_t dma_tag; + bus_space_handle_t dma_handle; /* Per channel interrupt irq number */ - int dma_irq; - char dma_irq_name[IFNAMSIZ + 32]; + struct resource *dma_irq_res; + void *dma_irq_tag; - /* Netdev related settings */ - struct napi_struct napi; - unsigned int saved_ier; - unsigned int tx_timer_active; - struct timer_list tx_timer; - struct xgbe_ring *tx_ring; struct xgbe_ring *rx_ring; -} ____cacheline_aligned; +} __aligned(CACHE_LINE_SIZE); enum xgbe_state { XGBE_DOWN, XGBE_LINK_INIT, XGBE_LINK_ERR, }; enum xgbe_int { XGMAC_INT_DMA_CH_SR_TI, XGMAC_INT_DMA_CH_SR_TPS, XGMAC_INT_DMA_CH_SR_TBU, XGMAC_INT_DMA_CH_SR_RI, XGMAC_INT_DMA_CH_SR_RBU, XGMAC_INT_DMA_CH_SR_RPS, XGMAC_INT_DMA_CH_SR_TI_RI, XGMAC_INT_DMA_CH_SR_FBE, XGMAC_INT_DMA_ALL, }; enum xgbe_int_state { XGMAC_INT_STATE_SAVE, XGMAC_INT_STATE_RESTORE, }; enum xgbe_speed { XGBE_SPEED_1000 = 0, XGBE_SPEED_2500, XGBE_SPEED_10000, XGBE_SPEEDS, }; enum xgbe_an { XGBE_AN_READY = 0, XGBE_AN_PAGE_RECEIVED, XGBE_AN_INCOMPAT_LINK, XGBE_AN_COMPLETE, XGBE_AN_NO_LINK, XGBE_AN_ERROR, }; enum xgbe_rx { XGBE_RX_BPA = 0, XGBE_RX_XNP, XGBE_RX_COMPLETE, XGBE_RX_ERROR, }; enum xgbe_mode { XGBE_MODE_KR = 0, XGBE_MODE_KX, }; enum xgbe_speedset { XGBE_SPEEDSET_1000_10000 = 0, XGBE_SPEEDSET_2500_10000, }; struct xgbe_phy { u32 supported; u32 advertising; u32 lp_advertising; int address; int autoneg; int speed; int duplex; int link; int pause_autoneg; int tx_pause; int rx_pause; }; struct xgbe_mmc_stats { /* Tx Stats */ u64 txoctetcount_gb; u64 txframecount_gb; u64 txbroadcastframes_g; u64 txmulticastframes_g; u64 tx64octets_gb; u64 tx65to127octets_gb; u64 tx128to255octets_gb; u64 tx256to511octets_gb; u64 tx512to1023octets_gb; u64 tx1024tomaxoctets_gb; u64 txunicastframes_gb; u64 txmulticastframes_gb; u64 txbroadcastframes_gb; u64 txunderflowerror; u64 txoctetcount_g; u64 txframecount_g; u64 txpauseframes; u64 txvlanframes_g; /* Rx Stats */ u64 rxframecount_gb; u64 rxoctetcount_gb; u64 rxoctetcount_g; u64 rxbroadcastframes_g; u64 rxmulticastframes_g; u64 rxcrcerror; u64 rxrunterror; u64 rxjabbererror; u64 rxundersize_g; u64 rxoversize_g; u64 rx64octets_gb; u64 rx65to127octets_gb; u64 rx128to255octets_gb; u64 rx256to511octets_gb; u64 rx512to1023octets_gb; u64 rx1024tomaxoctets_gb; u64 rxunicastframes_g; u64 rxlengtherror; u64 rxoutofrangetype; u64 rxpauseframes; u64 rxfifooverflow; u64 rxvlanframes_gb; u64 rxwatchdogerror; }; struct xgbe_ext_stats { u64 tx_tso_packets; u64 rx_split_header_packets; u64 rx_buffer_unavailable; }; struct xgbe_hw_if { int (*tx_complete)(struct xgbe_ring_desc *); int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr); int (*config_rx_mode)(struct xgbe_prv_data *); int (*enable_rx_csum)(struct xgbe_prv_data *); int (*disable_rx_csum)(struct xgbe_prv_data *); int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *); int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *); int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *); int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *); int (*update_vlan_hash_table)(struct xgbe_prv_data *); int (*read_mmd_regs)(struct xgbe_prv_data *, int, int); void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int); int (*set_gmii_speed)(struct xgbe_prv_data *); int (*set_gmii_2500_speed)(struct xgbe_prv_data *); int (*set_xgmii_speed)(struct xgbe_prv_data *); void (*enable_tx)(struct xgbe_prv_data *); void (*disable_tx)(struct xgbe_prv_data *); void (*enable_rx)(struct xgbe_prv_data *); void (*disable_rx)(struct xgbe_prv_data *); void (*powerup_tx)(struct xgbe_prv_data *); void (*powerdown_tx)(struct xgbe_prv_data *); void (*powerup_rx)(struct xgbe_prv_data *); void (*powerdown_rx)(struct xgbe_prv_data *); int (*init)(struct xgbe_prv_data *); int (*exit)(struct xgbe_prv_data *); int (*enable_int)(struct xgbe_channel *, enum xgbe_int); int (*disable_int)(struct xgbe_channel *, enum xgbe_int); void (*dev_xmit)(struct xgbe_channel *); int (*dev_read)(struct xgbe_channel *); void (*tx_desc_init)(struct xgbe_channel *); void (*rx_desc_init)(struct xgbe_channel *); void (*tx_desc_reset)(struct xgbe_ring_data *); void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *, unsigned int); int (*is_last_desc)(struct xgbe_ring_desc *); int (*is_context_desc)(struct xgbe_ring_desc *); void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *); /* For FLOW ctrl */ int (*config_tx_flow_control)(struct xgbe_prv_data *); int (*config_rx_flow_control)(struct xgbe_prv_data *); /* For RX coalescing */ int (*config_rx_coalesce)(struct xgbe_prv_data *); int (*config_tx_coalesce)(struct xgbe_prv_data *); unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int); unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int); /* For RX and TX threshold config */ int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int); int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int); /* For RX and TX Store and Forward Mode config */ int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int); int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int); /* For TX DMA Operate on Second Frame config */ int (*config_osp_mode)(struct xgbe_prv_data *); /* For RX and TX PBL config */ int (*config_rx_pbl_val)(struct xgbe_prv_data *); int (*get_rx_pbl_val)(struct xgbe_prv_data *); int (*config_tx_pbl_val)(struct xgbe_prv_data *); int (*get_tx_pbl_val)(struct xgbe_prv_data *); int (*config_pblx8)(struct xgbe_prv_data *); /* For MMC statistics */ void (*rx_mmc_int)(struct xgbe_prv_data *); void (*tx_mmc_int)(struct xgbe_prv_data *); void (*read_mmc_stats)(struct xgbe_prv_data *); - /* For Timestamp config */ - int (*config_tstamp)(struct xgbe_prv_data *, unsigned int); - void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int); - void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec, - unsigned int nsec); - u64 (*get_tstamp_time)(struct xgbe_prv_data *); - u64 (*get_tx_tstamp)(struct xgbe_prv_data *); - - /* For Data Center Bridging config */ - void (*config_tc)(struct xgbe_prv_data *); - void (*config_dcb_tc)(struct xgbe_prv_data *); - void (*config_dcb_pfc)(struct xgbe_prv_data *); - /* For Receive Side Scaling */ - int (*enable_rss)(struct xgbe_prv_data *); int (*disable_rss)(struct xgbe_prv_data *); - int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *); - int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *); }; struct xgbe_phy_if { /* For initial PHY setup */ void (*phy_init)(struct xgbe_prv_data *); /* For PHY support when setting device up/down */ int (*phy_reset)(struct xgbe_prv_data *); int (*phy_start)(struct xgbe_prv_data *); void (*phy_stop)(struct xgbe_prv_data *); /* For PHY support while device is up */ void (*phy_status)(struct xgbe_prv_data *); int (*phy_config_aneg)(struct xgbe_prv_data *); }; struct xgbe_desc_if { int (*alloc_ring_resources)(struct xgbe_prv_data *); void (*free_ring_resources)(struct xgbe_prv_data *); - int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *); + int (*map_tx_skb)(struct xgbe_channel *, struct mbuf *); int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *, struct xgbe_ring_data *); void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *); void (*wrapper_tx_desc_init)(struct xgbe_prv_data *); void (*wrapper_rx_desc_init)(struct xgbe_prv_data *); }; /* This structure contains flags that indicate what hardware features * or configurations are present in the device. */ struct xgbe_hw_features { /* HW Version */ unsigned int version; /* HW Feature Register0 */ unsigned int gmii; /* 1000 Mbps support */ unsigned int vlhash; /* VLAN Hash Filter */ unsigned int sma; /* SMA(MDIO) Interface */ unsigned int rwk; /* PMT remote wake-up packet */ unsigned int mgk; /* PMT magic packet */ unsigned int mmc; /* RMON module */ unsigned int aoe; /* ARP Offload */ unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */ unsigned int eee; /* Energy Efficient Ethernet */ unsigned int tx_coe; /* Tx Checksum Offload */ unsigned int rx_coe; /* Rx Checksum Offload */ unsigned int addn_mac; /* Additional MAC Addresses */ unsigned int ts_src; /* Timestamp Source */ unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ /* HW Feature Register1 */ unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ unsigned int adv_ts_hi; /* Advance Timestamping High Word */ unsigned int dma_width; /* DMA width */ unsigned int dcb; /* DCB Feature */ unsigned int sph; /* Split Header Feature */ unsigned int tso; /* TCP Segmentation Offload */ unsigned int dma_debug; /* DMA Debug Registers */ unsigned int rss; /* Receive Side Scaling */ unsigned int tc_cnt; /* Number of Traffic Classes */ unsigned int hash_table_size; /* Hash Table Size */ unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ /* HW Feature Register2 */ unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ unsigned int pps_out_num; /* Number of PPS outputs */ unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ }; struct xgbe_prv_data { - struct net_device *netdev; + struct ifnet *netdev; struct platform_device *pdev; struct acpi_device *adev; - struct device *dev; + device_t dev; /* ACPI or DT flag */ unsigned int use_acpi; /* XGMAC/XPCS related mmio registers */ - void __iomem *xgmac_regs; /* XGMAC CSRs */ - void __iomem *xpcs_regs; /* XPCS MMD registers */ - void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */ - void __iomem *sir0_regs; /* SerDes integration registers (1/2) */ - void __iomem *sir1_regs; /* SerDes integration registers (2/2) */ + struct resource *xgmac_res; /* XGMAC CSRs */ + struct resource *xpcs_res; /* XPCS MMD registers */ + struct resource *rxtx_res; /* SerDes Rx/Tx CSRs */ + struct resource *sir0_res; /* SerDes integration registers (1/2) */ + struct resource *sir1_res; /* SerDes integration registers (2/2) */ - /* Overall device lock */ - spinlock_t lock; + /* DMA tag */ + bus_dma_tag_t dmat; /* XPCS indirect addressing lock */ spinlock_t xpcs_lock; - /* RSS addressing mutex */ - struct mutex rss_mutex; - /* Flags representing xgbe_state */ unsigned long dev_state; - int dev_irq; + struct resource *dev_irq_res; + struct resource *chan_irq_res[4]; + void *dev_irq_tag; unsigned int per_channel_irq; struct xgbe_hw_if hw_if; struct xgbe_phy_if phy_if; struct xgbe_desc_if desc_if; /* AXI DMA settings */ unsigned int coherent; unsigned int axdomain; unsigned int arcache; unsigned int awcache; /* Service routine support */ - struct workqueue_struct *dev_workqueue; - struct work_struct service_work; - struct timer_list service_timer; + struct taskqueue *dev_workqueue; + struct task service_work; + struct callout service_timer; /* Rings for Tx/Rx on a DMA channel */ struct xgbe_channel *channel; unsigned int channel_count; unsigned int tx_ring_count; unsigned int tx_desc_count; unsigned int rx_ring_count; unsigned int rx_desc_count; unsigned int tx_q_count; unsigned int rx_q_count; /* Tx/Rx common settings */ unsigned int pblx8; /* Tx settings */ unsigned int tx_sf_mode; unsigned int tx_threshold; unsigned int tx_pbl; unsigned int tx_osp_mode; /* Rx settings */ unsigned int rx_sf_mode; unsigned int rx_threshold; unsigned int rx_pbl; /* Tx coalescing settings */ unsigned int tx_usecs; unsigned int tx_frames; /* Rx coalescing settings */ unsigned int rx_riwt; unsigned int rx_usecs; unsigned int rx_frames; /* Current Rx buffer size */ unsigned int rx_buf_size; /* Flow control settings */ unsigned int pause_autoneg; unsigned int tx_pause; unsigned int rx_pause; /* Receive Side Scaling settings */ u8 rss_key[XGBE_RSS_HASH_KEY_SIZE]; u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE]; u32 rss_options; /* Netdev related settings */ unsigned char mac_addr[ETH_ALEN]; - netdev_features_t netdev_features; - struct napi_struct napi; struct xgbe_mmc_stats mmc_stats; struct xgbe_ext_stats ext_stats; - /* Filtering support */ - unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; - /* Device clocks */ struct clk *sysclk; unsigned long sysclk_rate; struct clk *ptpclk; unsigned long ptpclk_rate; - /* Timestamp support */ - spinlock_t tstamp_lock; - struct ptp_clock_info ptp_clock_info; - struct ptp_clock *ptp_clock; - struct hwtstamp_config tstamp_config; - struct cyclecounter tstamp_cc; - struct timecounter tstamp_tc; - unsigned int tstamp_addend; - struct work_struct tx_tstamp_work; - struct sk_buff *tx_tstamp_skb; - u64 tx_tstamp; - /* DCB support */ - struct ieee_ets *ets; - struct ieee_pfc *pfc; unsigned int q2tc_map[XGBE_MAX_QUEUES]; unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS]; u8 num_tcs; /* Hardware features of the device */ struct xgbe_hw_features hw_feat; /* Device restart work structure */ - struct work_struct restart_work; + struct task restart_work; /* Keeps track of power mode */ unsigned int power_down; /* Network interface message level setting */ u32 msg_enable; /* Current PHY settings */ - phy_interface_t phy_mode; int phy_link; int phy_speed; /* MDIO/PHY related settings */ struct xgbe_phy phy; int mdio_mmd; unsigned long link_check; char an_name[IFNAMSIZ + 32]; - struct workqueue_struct *an_workqueue; - int an_irq; - struct work_struct an_irq_work; + struct resource *an_irq_res; + void *an_irq_tag; unsigned int speed_set; /* SerDes UEFI configurable settings. * Switching between modes/speeds requires new values for some * SerDes settings. The values can be supplied as device * properties in array format. The first array entry is for * 1GbE, second for 2.5GbE and third for 10GbE */ u32 serdes_blwc[XGBE_SPEEDS]; u32 serdes_cdr_rate[XGBE_SPEEDS]; u32 serdes_pq_skew[XGBE_SPEEDS]; u32 serdes_tx_amp[XGBE_SPEEDS]; u32 serdes_dfe_tap_cfg[XGBE_SPEEDS]; u32 serdes_dfe_tap_ena[XGBE_SPEEDS]; /* Auto-negotiation state machine support */ unsigned int an_int; - struct mutex an_mutex; + struct sx an_mutex; enum xgbe_an an_result; enum xgbe_an an_state; enum xgbe_rx kr_state; enum xgbe_rx kx_state; - struct work_struct an_work; unsigned int an_supported; unsigned int parallel_detect; unsigned int fec_ability; unsigned long an_start; unsigned int lpm_ctrl; /* CTRL1 for resume */ - -#ifdef CONFIG_DEBUG_FS - struct dentry *xgbe_debugfs; - - unsigned int debugfs_xgmac_reg; - - unsigned int debugfs_xpcs_mmd; - unsigned int debugfs_xpcs_reg; -#endif }; /* Function prototypes*/ +int xgbe_open(struct ifnet *); +int xgbe_close(struct ifnet *); +int xgbe_xmit(struct ifnet *, struct mbuf *); +int xgbe_change_mtu(struct ifnet *, int); void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *); void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *); void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *); -struct net_device_ops *xgbe_get_netdev_ops(void); -struct ethtool_ops *xgbe_get_ethtool_ops(void); -#ifdef CONFIG_AMD_XGBE_DCB -const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void); -#endif - -void xgbe_ptp_register(struct xgbe_prv_data *); -void xgbe_ptp_unregister(struct xgbe_prv_data *); -void xgbe_dump_tx_desc(struct xgbe_prv_data *, struct xgbe_ring *, - unsigned int, unsigned int, unsigned int); -void xgbe_dump_rx_desc(struct xgbe_prv_data *, struct xgbe_ring *, - unsigned int); -void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool); void xgbe_get_all_hw_features(struct xgbe_prv_data *); -int xgbe_powerup(struct net_device *, unsigned int); -int xgbe_powerdown(struct net_device *, unsigned int); void xgbe_init_rx_coalesce(struct xgbe_prv_data *); void xgbe_init_tx_coalesce(struct xgbe_prv_data *); -#ifdef CONFIG_DEBUG_FS -void xgbe_debugfs_init(struct xgbe_prv_data *); -void xgbe_debugfs_exit(struct xgbe_prv_data *); -#else -static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {} -static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {} -#endif /* CONFIG_DEBUG_FS */ - /* NOTE: Uncomment for function trace log messages in KERNEL LOG */ #if 0 #define YDEBUG #define YDEBUG_MDIO #endif /* For debug prints */ #ifdef YDEBUG -#define DBGPR(x...) pr_alert(x) +#define DBGPR(x...) printf(x) #else #define DBGPR(x...) do { } while (0) #endif #ifdef YDEBUG_MDIO -#define DBGPR_MDIO(x...) pr_alert(x) +#define DBGPR_MDIO(x...) printf(x) #else #define DBGPR_MDIO(x...) do { } while (0) #endif #endif Property changes on: head/sys/dev/axgbe/xgbe.h ___________________________________________________________________ Deleted: fbsd:nokeywords ## -1 +0,0 ## -yes \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/dev/axgbe/xgbe_osdep.h =================================================================== --- head/sys/dev/axgbe/xgbe_osdep.h (nonexistent) +++ head/sys/dev/axgbe/xgbe_osdep.h (revision 313768) @@ -0,0 +1,188 @@ +/*- + * Copyright (c) 2016,2017 SoftIron Inc. + * All rights reserved. + * + * This software was developed by Andrew Turner under + * the sponsorship of SoftIron Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _XGBE_OSDEP_H_ +#define _XGBE_OSDEP_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t __le32; +typedef uint32_t u32; +typedef uint64_t u64; + +typedef struct { + struct mtx lock; +} spinlock_t; + +static inline void +spin_lock_init(spinlock_t *spinlock) +{ + + mtx_init(&spinlock->lock, "axgbe_spin", NULL, MTX_DEF); +} + +#define spin_lock_irqsave(spinlock, flags) \ +do { \ + (flags) = intr_disable(); \ + mtx_lock(&(spinlock)->lock); \ +} while (0) + +#define spin_unlock_irqrestore(spinlock, flags) \ +do { \ + mtx_unlock(&(spinlock)->lock); \ + intr_restore(flags); \ +} while (0) + +#define BIT(pos) (1ul << pos) + +static inline void +clear_bit(int pos, unsigned long *p) +{ + + atomic_clear_long(p, 1ul << pos); +} + +static inline int +test_bit(int pos, unsigned long *p) +{ + unsigned long val; + + val = *p; + return ((val & 1ul << pos) != 0); +} + +static inline void +set_bit(int pos, unsigned long *p) +{ + + atomic_set_long(p, 1ul << pos); +} + +#define lower_32_bits(x) ((x) & 0xffffffffu) +#define upper_32_bits(x) (((x) >> 32) & 0xffffffffu) +#define cpu_to_le32(x) le32toh(x) +#define le32_to_cpu(x) htole32(x) + +MALLOC_DECLARE(M_AXGBE); + +#define ADVERTISED_Pause 0x01 +#define ADVERTISED_Asym_Pause 0x02 +#define ADVERTISED_Autoneg 0x04 +#define ADVERTISED_Backplane 0x08 +#define ADVERTISED_10000baseKR_Full 0x10 +#define ADVERTISED_2500baseX_Full 0x20 +#define ADVERTISED_1000baseKX_Full 0x40 + +#define AUTONEG_DISABLE 0 +#define AUTONEG_ENABLE 1 + +#define DUPLEX_UNKNOWN 1 +#define DUPLEX_FULL 2 + +#define SPEED_UNKNOWN 1 +#define SPEED_10000 2 +#define SPEED_2500 3 +#define SPEED_1000 4 + +#define SUPPORTED_Autoneg 0x01 +#define SUPPORTED_Pause 0x02 +#define SUPPORTED_Asym_Pause 0x04 +#define SUPPORTED_Backplane 0x08 +#define SUPPORTED_10000baseKR_Full 0x10 +#define SUPPORTED_1000baseKX_Full 0x20 +#define SUPPORTED_2500baseX_Full 0x40 +#define SUPPORTED_10000baseR_FEC 0x80 + +#define BMCR_SPEED100 0x2000 + +#define MDIO_MMD_PMAPMD 1 +#define MDIO_MMD_PCS 3 +#define MDIO_MMD_AN 7 +#define MDIO_PMA_10GBR_FECABLE 170 +#define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 +#define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 +#define MII_ADDR_C45 (1<<30) + +#define MDIO_CTRL1 0x00 /* MII_BMCR */ +#define MDIO_CTRL1_RESET 0x8000 /* BMCR_RESET */ +#define MDIO_CTRL1_SPEEDSELEXT 0x2040 /* BMCR_SPEED1000|BMCR_SPEED100*/ +#define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x3c) +#define MDIO_AN_CTRL1_ENABLE 0x1000 /* BMCR_AUTOEN */ +#define MDIO_CTRL1_LPOWER 0x0800 /* BMCR_PDOWN */ +#define MDIO_AN_CTRL1_RESTART 0x0200 /* BMCR_STARTNEG */ + +#define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00) + +#define MDIO_STAT1 1 /* MII_BMSR */ +#define MDIO_STAT1_LSTATUS 0x0004 /* BMSR_LINK */ + +#define MDIO_CTRL2 0x07 +#define MDIO_PCS_CTRL2_10GBR 0x0000 +#define MDIO_PCS_CTRL2_10GBX 0x0001 +#define MDIO_PCS_CTRL2_TYPE 0x0003 + +#define MDIO_AN_ADVERTISE 16 + +#define MDIO_AN_LPA 19 + +#define ETH_ALEN ETHER_ADDR_LEN +#define ETH_HLEN ETHER_HDR_LEN +#define ETH_FCS_LEN 4 +#define VLAN_HLEN ETHER_VLAN_ENCAP_LEN + +#define ARRAY_SIZE(x) nitems(x) + +#define BITS_PER_LONG (sizeof(long) * CHAR_BIT) +#define BITS_TO_LONGS(n) howmany((n), BITS_PER_LONG) + +#define NSEC_PER_SEC 1000000000ul + +#define min_t(t, a, b) MIN((t)(a), (t)(b)) +#define max_t(t, a, b) MAX((t)(a), (t)(b)) + +#endif /* _XGBE_OSDEP_H_ */ Property changes on: head/sys/dev/axgbe/xgbe_osdep.h ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property