Index: head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300.h =================================================================== --- head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300.h (revision 313090) +++ head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300.h (revision 313091) @@ -1,1726 +1,1727 @@ /* * Copyright (c) 2013 Qualcomm Atheros, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ #ifndef _ATH_AR9300_H_ #define _ATH_AR9300_H_ #include "ar9300_freebsd_inc.h" #define AH_BIG_ENDIAN 4321 #define AH_LITTLE_ENDIAN 1234 #if _BYTE_ORDER == _BIG_ENDIAN #define AH_BYTE_ORDER AH_BIG_ENDIAN #else #define AH_BYTE_ORDER AH_LITTLE_ENDIAN #endif /* XXX doesn't belong here */ #define AR_EEPROM_MODAL_SPURS 5 /* * (a) this should be N(a), * (b) FreeBSD does define nitems, * (c) it doesn't have an AH_ prefix, sigh. */ #define ARRAY_LENGTH(a) (sizeof(a) / sizeof((a)[0])) #include "ah_internal.h" #include "ah_eeprom.h" #include "ah_devid.h" #include "ar9300eep.h" /* For Eeprom definitions */ #define AR9300_MAGIC 0x19741014 /* MAC register values */ #define INIT_CONFIG_STATUS 0x00000000 #define INIT_RSSI_THR 0x7 /* Missed beacon counter initialized to 0x7 (max is 0xff) */ #define INIT_RSSI_BEACON_WEIGHT 8 /* ave beacon rssi weight (0-16) */ /* * Various fifo fill before Tx start, in 64-byte units * i.e. put the frame in the air while still DMAing */ #define MIN_TX_FIFO_THRESHOLD 0x1 #define MAX_TX_FIFO_THRESHOLD (( 4096 / 64) - 1) #define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD #define CHANSEL_DIV 15 #define FCLK 40 #define COEFF ((FCLK * 5) / 2) #define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV) #define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV) #define CHANSEL_5G_DOT5MHZ 2188 /* * Receive Queue Fifo depth. */ enum RX_FIFO_DEPTH { HAL_HP_RXFIFO_DEPTH = 16, HAL_LP_RXFIFO_DEPTH = 128, }; /* * Gain support. */ #define NUM_CORNER_FIX_BITS_2133 7 #define CCK_OFDM_GAIN_DELTA 15 enum GAIN_PARAMS { GP_TXCLIP, GP_PD90, GP_PD84, GP_GSEL }; enum GAIN_PARAMS_2133 { GP_MIXGAIN_OVR, GP_PWD_138, GP_PWD_137, GP_PWD_136, GP_PWD_132, GP_PWD_131, GP_PWD_130, }; enum { HAL_RESET_POWER_ON, HAL_RESET_WARM, HAL_RESET_COLD, }; typedef struct _gain_opt_step { int16_t paramVal[NUM_CORNER_FIX_BITS_2133]; int32_t stepGain; int8_t stepName[16]; } GAIN_OPTIMIZATION_STEP; typedef struct { u_int32_t numStepsInLadder; u_int32_t defaultStepNum; GAIN_OPTIMIZATION_STEP optStep[10]; } GAIN_OPTIMIZATION_LADDER; typedef struct { u_int32_t currStepNum; u_int32_t currGain; u_int32_t targetGain; u_int32_t loTrig; u_int32_t hiTrig; u_int32_t gainFCorrection; u_int32_t active; GAIN_OPTIMIZATION_STEP *curr_step; } GAIN_VALUES; typedef struct { u_int16_t synth_center; u_int16_t ctl_center; u_int16_t ext_center; } CHAN_CENTERS; /* RF HAL structures */ typedef struct rf_hal_funcs { HAL_BOOL (*set_channel)(struct ath_hal *, struct ieee80211_channel *); HAL_BOOL (*get_chip_power_lim)(struct ath_hal *ah, struct ieee80211_channel *chan); } RF_HAL_FUNCS; struct ar9300_ani_default { u_int16_t m1_thresh_low; u_int16_t m2_thresh_low; u_int16_t m1_thresh; u_int16_t m2_thresh; u_int16_t m2_count_thr; u_int16_t m2_count_thr_low; u_int16_t m1_thresh_low_ext; u_int16_t m2_thresh_low_ext; u_int16_t m1_thresh_ext; u_int16_t m2_thresh_ext; u_int16_t firstep; u_int16_t firstep_low; u_int16_t cycpwr_thr1; u_int16_t cycpwr_thr1_ext; }; /* * Per-channel ANI state private to the driver. */ struct ar9300_ani_state { struct ieee80211_channel c; /* XXX ew? */ HAL_BOOL must_restore; HAL_BOOL ofdms_turn; u_int8_t ofdm_noise_immunity_level; u_int8_t cck_noise_immunity_level; u_int8_t spur_immunity_level; u_int8_t firstep_level; u_int8_t ofdm_weak_sig_detect_off; u_int8_t mrc_cck_off; /* Thresholds */ u_int32_t listen_time; u_int32_t ofdm_trig_high; u_int32_t ofdm_trig_low; int32_t cck_trig_high; int32_t cck_trig_low; int32_t rssi_thr_low; int32_t rssi_thr_high; int32_t rssi; /* The current RSSI */ u_int32_t tx_frame_count; /* Last tx_frame_count */ u_int32_t rx_frame_count; /* Last rx Frame count */ u_int32_t rx_busy_count; /* Last rx busy count */ u_int32_t rx_ext_busy_count; /* Last rx busy count; extension channel */ u_int32_t cycle_count; /* Last cycle_count (can detect wrap-around) */ u_int32_t ofdm_phy_err_count;/* OFDM err count since last reset */ u_int32_t cck_phy_err_count; /* CCK err count since last reset */ struct ar9300_ani_default ini_def; /* INI default values for ANI registers */ HAL_BOOL phy_noise_spur; /* based on OFDM/CCK Phy errors */ }; #define AR9300_ANI_POLLINTERVAL 1000 /* 1000 milliseconds between ANI poll */ #define AR9300_CHANNEL_SWITCH_TIME_USEC 1000 /* 1 millisecond needed to change channels */ #define HAL_PROCESS_ANI 0x00000001 /* ANI state setup */ #define HAL_RADAR_EN 0x80000000 /* Radar detect is capable */ #define HAL_AR_EN 0x40000000 /* AR detect is capable */ #define DO_ANI(ah) \ ((AH9300(ah)->ah_proc_phy_err & HAL_PROCESS_ANI)) #if 0 struct ar9300_stats { u_int32_t ast_ani_niup; /* ANI increased noise immunity */ u_int32_t ast_ani_nidown; /* ANI decreased noise immunity */ u_int32_t ast_ani_spurup; /* ANI increased spur immunity */ u_int32_t ast_ani_spurdown;/* ANI descreased spur immunity */ u_int32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ u_int32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ u_int32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ u_int32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ u_int32_t ast_ani_stepup; /* ANI increased first step level */ u_int32_t ast_ani_stepdown;/* ANI decreased first step level */ u_int32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ u_int32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ u_int32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ u_int32_t ast_ani_lzero; /* ANI listen time forced to zero */ u_int32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ }; #endif struct ar9300_rad_reader { u_int16_t rd_index; u_int16_t rd_expSeq; u_int32_t rd_resetVal; u_int8_t rd_start; }; struct ar9300_rad_writer { u_int16_t wr_index; u_int16_t wr_seq; }; struct ar9300_radar_event { u_int32_t re_ts; /* 32 bit time stamp */ u_int8_t re_rssi; /* rssi of radar event */ u_int8_t re_dur; /* duration of radar pulse */ u_int8_t re_chanIndex; /* Channel of event */ }; struct ar9300_radar_q_elem { u_int32_t rq_seqNum; u_int32_t rq_busy; /* 32 bit to insure atomic read/write */ struct ar9300_radar_event rq_event; /* Radar event */ }; struct ar9300_radar_q_info { u_int16_t ri_qsize; /* q size */ u_int16_t ri_seqSize; /* Size of sequence ring */ struct ar9300_rad_reader ri_reader; /* State for the q reader */ struct ar9300_rad_writer ri_writer; /* state for the q writer */ }; #define HAL_MAX_ACK_RADAR_DUR 511 #define HAL_MAX_NUM_PEAKS 3 #define HAL_ARQ_SIZE 4096 /* 8K AR events for buffer size */ #define HAL_ARQ_SEQSIZE 4097 /* Sequence counter wrap for AR */ #define HAL_RADARQ_SIZE 1024 /* 1K radar events for buffer size */ #define HAL_RADARQ_SEQSIZE 1025 /* Sequence counter wrap for radar */ #define HAL_NUMRADAR_STATES 64 /* Number of radar channels we keep state for */ struct ar9300_ar_state { u_int16_t ar_prev_time_stamp; u_int32_t ar_prev_width; u_int32_t ar_phy_err_count[HAL_MAX_ACK_RADAR_DUR]; u_int32_t ar_ack_sum; u_int16_t ar_peak_list[HAL_MAX_NUM_PEAKS]; u_int32_t ar_packet_threshold; /* Thresh to determine traffic load */ u_int32_t ar_par_threshold; /* Thresh to determine peak */ u_int32_t ar_radar_rssi; /* Rssi threshold for AR event */ }; struct ar9300_radar_state { struct ieee80211_channel *rs_chan; /* Channel info */ u_int8_t rs_chan_index; /* Channel index in radar structure */ u_int32_t rs_num_radar_events; /* Number of radar events */ int32_t rs_firpwr; /* Thresh to check radar sig is gone */ u_int32_t rs_radar_rssi; /* Thresh to start radar det (dB) */ u_int32_t rs_height; /* Thresh for pulse height (dB)*/ u_int32_t rs_pulse_rssi; /* Thresh to check if pulse is gone (dB) */ u_int32_t rs_inband; /* Thresh to check if pusle is inband (0.5 dB) */ }; typedef struct { u_int8_t uc_receiver_errors; u_int8_t uc_bad_tlp_errors; u_int8_t uc_bad_dllp_errors; u_int8_t uc_replay_timeout_errors; u_int8_t uc_replay_number_rollover_errors; } ar_pcie_error_moniter_counters; #define AR9300_OPFLAGS_11A 0x01 /* if set, allow 11a */ #define AR9300_OPFLAGS_11G 0x02 /* if set, allow 11g */ #define AR9300_OPFLAGS_N_5G_HT40 0x04 /* if set, disable 5G HT40 */ #define AR9300_OPFLAGS_N_2G_HT40 0x08 /* if set, disable 2G HT40 */ #define AR9300_OPFLAGS_N_5G_HT20 0x10 /* if set, disable 5G HT20 */ #define AR9300_OPFLAGS_N_2G_HT20 0x20 /* if set, disable 2G HT20 */ /* * For Kite and later chipsets, the following bits are not being programmed in EEPROM * and so need to be enabled always. * Bit 0: en_fcc_mid, Bit 1: en_jap_mid, Bit 2: en_fcc_dfs_ht40 * Bit 3: en_jap_ht40, Bit 4: en_jap_dfs_ht40 */ #define AR9300_RDEXT_DEFAULT 0x1F #define AR9300_MAX_CHAINS 3 #define AR9300_NUM_CHAINS(chainmask) \ (((chainmask >> 2) & 1) + ((chainmask >> 1) & 1) + (chainmask & 1)) #define AR9300_CHAIN0_MASK 0x1 #define AR9300_CHAIN1_MASK 0x2 #define AR9300_CHAIN2_MASK 0x4 /* Support for multiple INIs */ struct ar9300_ini_array { const u_int32_t *ia_array; u_int32_t ia_rows; u_int32_t ia_columns; }; #define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \ (iniarray)->ia_array = (const u_int32_t *)(array); \ (iniarray)->ia_rows = (rows); \ (iniarray)->ia_columns = (columns); \ } while (0) #define INI_RA(iniarray, row, column) (((iniarray)->ia_array)[(row) * ((iniarray)->ia_columns) + (column)]) #define INIT_CAL(_perCal) \ (_perCal)->cal_state = CAL_WAITING; \ (_perCal)->cal_next = AH_NULL; #define INSERT_CAL(_ahp, _perCal) \ do { \ if ((_ahp)->ah_cal_list_last == AH_NULL) { \ (_ahp)->ah_cal_list = (_ahp)->ah_cal_list_last = (_perCal); \ ((_ahp)->ah_cal_list_last)->cal_next = (_perCal); \ } else { \ ((_ahp)->ah_cal_list_last)->cal_next = (_perCal); \ (_ahp)->ah_cal_list_last = (_perCal); \ (_perCal)->cal_next = (_ahp)->ah_cal_list; \ } \ } while (0) typedef enum cal_types { IQ_MISMATCH_CAL = 0x1, TEMP_COMP_CAL = 0x2, } HAL_CAL_TYPES; typedef enum cal_state { CAL_INACTIVE, CAL_WAITING, CAL_RUNNING, CAL_DONE } HAL_CAL_STATE; /* Calibrate state */ #define MIN_CAL_SAMPLES 1 #define MAX_CAL_SAMPLES 64 #define INIT_LOG_COUNT 5 #define PER_MIN_LOG_COUNT 2 #define PER_MAX_LOG_COUNT 10 #define AR9300_NUM_BT_WEIGHTS 4 #define AR9300_NUM_WLAN_WEIGHTS 4 /* Per Calibration data structure */ typedef struct per_cal_data { HAL_CAL_TYPES cal_type; // Type of calibration u_int32_t cal_num_samples; // Number of SW samples to collect u_int32_t cal_count_max; // Number of HW samples to collect void (*cal_collect)(struct ath_hal *, u_int8_t); // Accumulator func void (*cal_post_proc)(struct ath_hal *, u_int8_t); // Post-processing func } HAL_PERCAL_DATA; /* List structure for calibration data */ typedef struct cal_list { const HAL_PERCAL_DATA *cal_data; HAL_CAL_STATE cal_state; struct cal_list *cal_next; } HAL_CAL_LIST; #define AR9300_NUM_CAL_TYPES 2 #define AR9300_PAPRD_TABLE_SZ 24 #define AR9300_PAPRD_GAIN_TABLE_SZ 32 #define AR9382_MAX_GPIO_PIN_NUM (16) #define AR9382_GPIO_PIN_8_RESERVED (8) #define AR9382_GPIO_9_INPUT_ONLY (9) #define AR9382_MAX_GPIO_INPUT_PIN_NUM (13) #define AR9382_GPIO_PIN_11_RESERVED (11) #define AR9382_MAX_JTAG_GPIO_PIN_NUM (3) /* Paprd tx power adjust data structure */ struct ar9300_paprd_pwr_adjust { u_int32_t target_rate; // rate index u_int32_t reg_addr; // register offset u_int32_t reg_mask; // mask of register u_int32_t reg_mask_offset; // mask offset of register u_int32_t sub_db; // offset value unit of dB }; struct ar9300NfLimits { int16_t max; int16_t min; int16_t nominal; }; #define AR9300_MAX_RATES 36 /* legacy(4) + ofdm(8) + HTSS(8) + HTDS(8) + HTTS(8)*/ struct ath_hal_9300 { struct ath_hal_private ah_priv; /* base class */ /* * Information retrieved from EEPROM. */ ar9300_eeprom_t ah_eeprom; GAIN_VALUES ah_gain_values; u_int8_t ah_macaddr[IEEE80211_ADDR_LEN]; u_int8_t ah_bssid[IEEE80211_ADDR_LEN]; u_int8_t ah_bssid_mask[IEEE80211_ADDR_LEN]; u_int16_t ah_assoc_id; /* * Runtime state. */ u_int32_t ah_mask_reg; /* copy of AR_IMR */ u_int32_t ah_mask2Reg; /* copy of AR_IMR_S2 */ u_int32_t ah_msi_reg; /* copy of AR_PCIE_MSI */ os_atomic_t ah_ier_ref_count; /* reference count for enabling interrupts */ HAL_ANI_STATS ah_stats; /* various statistics */ RF_HAL_FUNCS ah_rf_hal; u_int32_t ah_tx_desc_mask; /* mask for TXDESC */ u_int32_t ah_tx_ok_interrupt_mask; u_int32_t ah_tx_err_interrupt_mask; u_int32_t ah_tx_desc_interrupt_mask; u_int32_t ah_tx_eol_interrupt_mask; u_int32_t ah_tx_urn_interrupt_mask; HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; HAL_SMPS_MODE ah_sm_power_mode; HAL_BOOL ah_chip_full_sleep; u_int32_t ah_atim_window; HAL_ANT_SETTING ah_diversity_control; /* antenna setting */ u_int16_t ah_antenna_switch_swap; /* Controls mapping of OID request */ u_int8_t ah_tx_chainmask_cfg; /* chain mask config */ u_int8_t ah_rx_chainmask_cfg; u_int32_t ah_beacon_rssi_threshold; /* cache beacon rssi threshold */ /* Calibration related fields */ HAL_CAL_TYPES ah_supp_cals; HAL_CAL_LIST ah_iq_cal_data; /* IQ Cal Data */ HAL_CAL_LIST ah_temp_comp_cal_data; /* Temperature Compensation Cal Data */ HAL_CAL_LIST *ah_cal_list; /* ptr to first cal in list */ HAL_CAL_LIST *ah_cal_list_last; /* ptr to last cal in list */ HAL_CAL_LIST *ah_cal_list_curr; /* ptr to current cal */ // IQ Cal aliases #define ah_total_power_meas_i ah_meas0.unsign #define ah_total_power_meas_q ah_meas1.unsign #define ah_total_iq_corr_meas ah_meas2.sign union { u_int32_t unsign[AR9300_MAX_CHAINS]; int32_t sign[AR9300_MAX_CHAINS]; } ah_meas0; union { u_int32_t unsign[AR9300_MAX_CHAINS]; int32_t sign[AR9300_MAX_CHAINS]; } ah_meas1; union { u_int32_t unsign[AR9300_MAX_CHAINS]; int32_t sign[AR9300_MAX_CHAINS]; } ah_meas2; union { u_int32_t unsign[AR9300_MAX_CHAINS]; int32_t sign[AR9300_MAX_CHAINS]; } ah_meas3; u_int16_t ah_cal_samples; /* end - Calibration related fields */ u_int32_t ah_tx6_power_in_half_dbm; /* power output for 6Mb tx */ u_int32_t ah_sta_id1_defaults; /* STA_ID1 default settings */ u_int32_t ah_misc_mode; /* MISC_MODE settings */ HAL_BOOL ah_get_plcp_hdr; /* setting about MISC_SEL_EVM */ enum { AUTO_32KHZ, /* use it if 32kHz crystal present */ USE_32KHZ, /* do it regardless */ DONT_USE_32KHZ, /* don't use it regardless */ } ah_enable32k_hz_clock; /* whether to sleep at 32kHz */ u_int32_t ah_ofdm_tx_power; int16_t ah_tx_power_index_offset; u_int ah_slot_time; /* user-specified slot time */ u_int ah_ack_timeout; /* user-specified ack timeout */ /* * XXX * 11g-specific stuff; belongs in the driver. */ u_int8_t ah_g_beacon_rate; /* fixed rate for G beacons */ u_int32_t ah_gpio_mask; /* copy of enabled GPIO mask */ u_int32_t ah_gpio_cause; /* copy of GPIO cause (sync and async) */ /* * RF Silent handling; setup according to the EEPROM. */ u_int32_t ah_gpio_select; /* GPIO pin to use */ u_int32_t ah_polarity; /* polarity to disable RF */ u_int32_t ah_gpio_bit; /* after init, prev value */ HAL_BOOL ah_eep_enabled; /* EEPROM bit for capability */ #ifdef ATH_BT_COEX /* * Bluetooth coexistence static setup according to the registry */ HAL_BT_MODULE ah_bt_module; /* Bluetooth module identifier */ u_int8_t ah_bt_coex_config_type; /* BT coex configuration */ u_int8_t ah_bt_active_gpio_select; /* GPIO pin for BT_ACTIVE */ u_int8_t ah_bt_priority_gpio_select; /* GPIO pin for BT_PRIORITY */ u_int8_t ah_wlan_active_gpio_select; /* GPIO pin for WLAN_ACTIVE */ u_int8_t ah_bt_active_polarity; /* Polarity of BT_ACTIVE */ HAL_BOOL ah_bt_coex_single_ant; /* Single or dual antenna configuration */ u_int8_t ah_bt_wlan_isolation; /* Isolation between BT and WLAN in dB */ /* * Bluetooth coexistence runtime settings */ HAL_BOOL ah_bt_coex_enabled; /* If Bluetooth coexistence is enabled */ u_int32_t ah_bt_coex_mode; /* Register setting for AR_BT_COEX_MODE */ u_int32_t ah_bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS]; /* Register setting for AR_BT_COEX_WEIGHT */ u_int32_t ah_bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS]; /* Register setting for AR_BT_COEX_WEIGHT */ u_int32_t ah_bt_coex_mode2; /* Register setting for AR_BT_COEX_MODE2 */ u_int32_t ah_bt_coex_flag; /* Special tuning flags for BT coex */ #endif /* * Generic timer support */ u_int32_t ah_avail_gen_timers; /* mask of available timers */ u_int32_t ah_intr_gen_timer_trigger; /* generic timer trigger interrupt state */ u_int32_t ah_intr_gen_timer_thresh; /* generic timer trigger interrupt state */ HAL_BOOL ah_enable_tsf2; /* enable TSF2 for gen timer 8-15. */ /* * ANI & Radar support. */ u_int32_t ah_proc_phy_err; /* Process Phy errs */ u_int32_t ah_ani_period; /* ani update list period */ struct ar9300_ani_state *ah_curani; /* cached last reference */ struct ar9300_ani_state ah_ani[255]; /* per-channel state */ struct ar9300_radar_state ah_radar[HAL_NUMRADAR_STATES]; /* Per-Channel Radar detector state */ struct ar9300_radar_q_elem *ah_radarq; /* radar event queue */ struct ar9300_radar_q_info ah_radarq_info; /* radar event q read/write state */ struct ar9300_ar_state ah_ar; /* AR detector state */ struct ar9300_radar_q_elem *ah_arq; /* AR event queue */ struct ar9300_radar_q_info ah_arq_info; /* AR event q read/write state */ /* * Transmit power state. Note these are maintained * here so they can be retrieved by diagnostic tools. */ u_int16_t ah_rates_array[16]; /* * Tx queue interrupt state. */ u_int32_t ah_intr_txqs; HAL_BOOL ah_intr_mitigation_rx; /* rx Interrupt Mitigation Settings */ HAL_BOOL ah_intr_mitigation_tx; /* tx Interrupt Mitigation Settings */ /* * Extension Channel Rx Clear State */ u_int32_t ah_cycle_count; u_int32_t ah_ctl_busy; u_int32_t ah_ext_busy; /* HT CWM state */ HAL_HT_EXTPROTSPACING ah_ext_prot_spacing; u_int8_t ah_tx_chainmask; /* tx chain mask */ u_int8_t ah_rx_chainmask; /* rx chain mask */ /* optional tx chainmask */ u_int8_t ah_tx_chainmaskopt; u_int8_t ah_tx_cal_chainmask; /* tx cal chain mask */ u_int8_t ah_rx_cal_chainmask; /* rx cal chain mask */ int ah_hwp; void *ah_cal_mem; HAL_BOOL ah_emu_eeprom; HAL_ANI_CMD ah_ani_function; HAL_BOOL ah_rifs_enabled; u_int32_t ah_rifs_reg[11]; u_int32_t ah_rifs_sec_cnt; /* open-loop power control */ u_int32_t original_gain[22]; int32_t init_pdadc; int32_t pdadc_delta; /* cycle counts for beacon stuck diagnostics */ u_int32_t ah_cycles; u_int32_t ah_rx_clear; u_int32_t ah_rx_frame; u_int32_t ah_tx_frame; #define BB_HANG_SIG1 0 #define BB_HANG_SIG2 1 #define BB_HANG_SIG3 2 #define BB_HANG_SIG4 3 #define MAC_HANG_SIG1 4 #define MAC_HANG_SIG2 5 /* bb hang detection */ int ah_hang[6]; hal_hw_hangs_t ah_hang_wars; /* * Keytable type table */ #define AR_KEYTABLE_SIZE 128 /* XXX! */ uint8_t ah_keytype[AR_KEYTABLE_SIZE]; #undef AR_KEYTABLE_SIZE /* * Support for ar9300 multiple INIs */ struct ar9300_ini_array ah_ini_pcie_serdes; struct ar9300_ini_array ah_ini_pcie_serdes_low_power; struct ar9300_ini_array ah_ini_modes_additional; struct ar9300_ini_array ah_ini_modes_additional_40mhz; struct ar9300_ini_array ah_ini_modes_rxgain; struct ar9300_ini_array ah_ini_modes_rxgain_bounds; struct ar9300_ini_array ah_ini_modes_txgain; struct ar9300_ini_array ah_ini_japan2484; struct ar9300_ini_array ah_ini_radio_post_sys2ant; struct ar9300_ini_array ah_ini_BTCOEX_MAX_TXPWR; struct ar9300_ini_array ah_ini_modes_rxgain_xlna; struct ar9300_ini_array ah_ini_modes_rxgain_bb_core; struct ar9300_ini_array ah_ini_modes_rxgain_bb_postamble; /* * New INI format starting with Osprey 2.0 INI. * Pre, core, post arrays for each sub-system (mac, bb, radio, soc) */ #define ATH_INI_PRE 0 #define ATH_INI_CORE 1 #define ATH_INI_POST 2 #define ATH_INI_NUM_SPLIT (ATH_INI_POST + 1) struct ar9300_ini_array ah_ini_mac[ATH_INI_NUM_SPLIT]; /* New INI format */ struct ar9300_ini_array ah_ini_bb[ATH_INI_NUM_SPLIT]; /* New INI format */ struct ar9300_ini_array ah_ini_radio[ATH_INI_NUM_SPLIT]; /* New INI format */ struct ar9300_ini_array ah_ini_soc[ATH_INI_NUM_SPLIT]; /* New INI format */ /* * Added to support DFS postamble array in INI that we need to apply * in DFS channels */ struct ar9300_ini_array ah_ini_dfs; #if ATH_WOW struct ar9300_ini_array ah_ini_pcie_serdes_wow; /* SerDes values during WOW sleep */ #endif /* To indicate EEPROM mapping used */ u_int32_t ah_immunity_vals[6]; HAL_BOOL ah_immunity_on; /* * snap shot of counter register for debug purposes */ #ifdef AH_DEBUG u_int32_t last_tf; u_int32_t last_rf; u_int32_t last_rc; u_int32_t last_cc; #endif HAL_BOOL ah_dma_stuck; /* Set to AH_TRUE when RX/TX DMA failed to stop. */ u_int32_t nf_tsf32; /* timestamp for NF calibration duration */ u_int32_t reg_dmn; /* Regulatory Domain */ int16_t twice_antenna_gain; /* Antenna Gain */ u_int16_t twice_antenna_reduction; /* Antenna Gain Allowed */ /* * Upper limit after factoring in the regulatory max, antenna gain and * multichain factor. No TxBF, CDD or STBC gain factored */ int16_t upper_limit[AR9300_MAX_CHAINS]; /* adjusted power for descriptor-based TPC for 1, 2, or 3 chains */ int16_t txpower[AR9300_MAX_RATES][AR9300_MAX_CHAINS]; /* adjusted power for descriptor-based TPC for 1, 2, or 3 chains with STBC*/ int16_t txpower_stbc[AR9300_MAX_RATES][AR9300_MAX_CHAINS]; /* Transmit Status ring support */ struct ar9300_txs *ts_ring; u_int16_t ts_tail; u_int16_t ts_size; u_int32_t ts_paddr_start; u_int32_t ts_paddr_end; /* Receive Buffer size */ #define HAL_RXBUFSIZE_DEFAULT 0xfff u_int16_t rx_buf_size; u_int32_t ah_wa_reg_val; // Store the permanent value of Reg 0x4004 so we dont have to R/M/W. (We should not be reading this register when in sleep states). /* Indicate the PLL source clock rate is 25Mhz or not. * clk_25mhz = 0 by default. */ u_int8_t clk_25mhz; /* For PAPRD uses */ u_int16_t small_signal_gain[AH_MAX_CHAINS]; u_int32_t pa_table[AH_MAX_CHAINS][AR9300_PAPRD_TABLE_SZ]; u_int32_t paprd_gain_table_entries[AR9300_PAPRD_GAIN_TABLE_SZ]; u_int32_t paprd_gain_table_index[AR9300_PAPRD_GAIN_TABLE_SZ]; u_int32_t ah_2g_paprd_rate_mask_ht20; /* Copy of eep->modal_header_2g.paprd_rate_mask_ht20 */ u_int32_t ah_2g_paprd_rate_mask_ht40; /* Copy of eep->modal_header_2g.paprd_rate_mask_ht40 */ u_int32_t ah_5g_paprd_rate_mask_ht20; /* Copy of eep->modal_header_5g.paprd_rate_mask_ht20 */ u_int32_t ah_5g_paprd_rate_mask_ht40; /* Copy of eep->modal_header_5g.paprd_rate_mask_ht40 */ u_int32_t paprd_training_power; /* For GreenTx use to store the default tx power */ u_int8_t ah_default_tx_power[ar9300_rate_size]; HAL_BOOL ah_paprd_broken; /* To store offsets of host interface registers */ struct { u_int32_t AR_RC; u_int32_t AR_WA; u_int32_t AR_PM_STATE; u_int32_t AR_H_INFOL; u_int32_t AR_H_INFOH; u_int32_t AR_PCIE_PM_CTRL; u_int32_t AR_HOST_TIMEOUT; u_int32_t AR_EEPROM; u_int32_t AR_SREV; u_int32_t AR_INTR_SYNC_CAUSE; u_int32_t AR_INTR_SYNC_CAUSE_CLR; u_int32_t AR_INTR_SYNC_ENABLE; u_int32_t AR_INTR_ASYNC_MASK; u_int32_t AR_INTR_SYNC_MASK; u_int32_t AR_INTR_ASYNC_CAUSE_CLR; u_int32_t AR_INTR_ASYNC_CAUSE; u_int32_t AR_INTR_ASYNC_ENABLE; u_int32_t AR_PCIE_SERDES; u_int32_t AR_PCIE_SERDES2; u_int32_t AR_GPIO_OUT; u_int32_t AR_GPIO_IN; u_int32_t AR_GPIO_OE_OUT; u_int32_t AR_GPIO_OE1_OUT; u_int32_t AR_GPIO_INTR_POL; u_int32_t AR_GPIO_INPUT_EN_VAL; u_int32_t AR_GPIO_INPUT_MUX1; u_int32_t AR_GPIO_INPUT_MUX2; u_int32_t AR_GPIO_OUTPUT_MUX1; u_int32_t AR_GPIO_OUTPUT_MUX2; u_int32_t AR_GPIO_OUTPUT_MUX3; u_int32_t AR_INPUT_STATE; u_int32_t AR_SPARE; u_int32_t AR_PCIE_CORE_RESET_EN; u_int32_t AR_CLKRUN; u_int32_t AR_EEPROM_STATUS_DATA; u_int32_t AR_OBS; u_int32_t AR_RFSILENT; u_int32_t AR_GPIO_PDPU; u_int32_t AR_GPIO_DS; u_int32_t AR_MISC; u_int32_t AR_PCIE_MSI; u_int32_t AR_TSF_SNAPSHOT_BT_ACTIVE; u_int32_t AR_TSF_SNAPSHOT_BT_PRIORITY; u_int32_t AR_TSF_SNAPSHOT_BT_CNTL; u_int32_t AR_PCIE_PHY_LATENCY_NFTS_ADJ; u_int32_t AR_TDMA_CCA_CNTL; u_int32_t AR_TXAPSYNC; u_int32_t AR_TXSYNC_INIT_SYNC_TMR; u_int32_t AR_INTR_PRIO_SYNC_CAUSE; u_int32_t AR_INTR_PRIO_SYNC_ENABLE; u_int32_t AR_INTR_PRIO_ASYNC_MASK; u_int32_t AR_INTR_PRIO_SYNC_MASK; u_int32_t AR_INTR_PRIO_ASYNC_CAUSE; u_int32_t AR_INTR_PRIO_ASYNC_ENABLE; } ah_hostifregs; u_int32_t ah_enterprise_mode; u_int32_t ah_radar1; u_int32_t ah_dc_offset; HAL_BOOL ah_hw_green_tx_enable; /* 1:enalbe H/W Green Tx */ HAL_BOOL ah_smartantenna_enable; /* 1:enalbe H/W */ u_int32_t ah_disable_cck; HAL_BOOL ah_lna_div_use_bt_ant_enable; /* 1:enable Rx(LNA) Diversity */ /* * Different types of memory where the calibration data might be stored. * All types are searched in Ar9300EepromRestore() in the order flash, eeprom, otp. * To disable searching a type, set its parameter to 0. */ int try_dram; int try_flash; int try_eeprom; int try_otp; #ifdef ATH_CAL_NAND_FLASH int try_nand; #endif /* * This is where we found the calibration data. */ int calibration_data_source; int calibration_data_source_address; /* * This is where we look for the calibration data. must be set before ath_attach() is called */ int calibration_data_try; int calibration_data_try_address; u_int8_t tx_iq_cal_enable : 1, tx_iq_cal_during_agc_cal : 1, tx_cl_cal_enable : 1; #if ATH_SUPPORT_MCI /* For MCI */ HAL_BOOL ah_mci_ready; u_int32_t ah_mci_int_raw; u_int32_t ah_mci_int_rx_msg; u_int32_t ah_mci_rx_status; u_int32_t ah_mci_cont_status; u_int8_t ah_mci_bt_state; u_int32_t ah_mci_gpm_addr; u_int8_t *ah_mci_gpm_buf; u_int32_t ah_mci_gpm_len; u_int32_t ah_mci_gpm_idx; u_int32_t ah_mci_sched_addr; u_int8_t *ah_mci_sched_buf; u_int8_t ah_mci_coex_major_version_wlan; u_int8_t ah_mci_coex_minor_version_wlan; u_int8_t ah_mci_coex_major_version_bt; u_int8_t ah_mci_coex_minor_version_bt; HAL_BOOL ah_mci_coex_bt_version_known; HAL_BOOL ah_mci_coex_wlan_channels_update; u_int32_t ah_mci_coex_wlan_channels[4]; HAL_BOOL ah_mci_coex_2g5g_update; HAL_BOOL ah_mci_coex_is_2g; HAL_BOOL ah_mci_query_bt; HAL_BOOL ah_mci_unhalt_bt_gpm; /* need send UNHALT */ HAL_BOOL ah_mci_halted_bt_gpm; /* HALT sent */ HAL_BOOL ah_mci_need_flush_btinfo; HAL_BOOL ah_mci_concur_tx_en; u_int8_t ah_mci_stomp_low_tx_pri; u_int8_t ah_mci_stomp_all_tx_pri; u_int8_t ah_mci_stomp_none_tx_pri; u_int32_t ah_mci_wlan_cal_seq; u_int32_t ah_mci_wlan_cal_done; #if ATH_SUPPORT_AIC HAL_BOOL ah_aic_enabled; u_int32_t ah_aic_sram[ATH_AIC_MAX_BT_CHANNEL]; #endif #endif /* ATH_SUPPORT_MCI */ u_int8_t ah_cac_quiet_enabled; #if ATH_WOW_OFFLOAD u_int32_t ah_mcast_filter_l32_set; u_int32_t ah_mcast_filter_u32_set; #endif HAL_BOOL ah_reduced_self_gen_mask; HAL_BOOL ah_chip_reset_done; HAL_BOOL ah_abort_txdma_norx; /* store previous passive RX Cal info */ HAL_BOOL ah_skip_rx_iq_cal; HAL_BOOL ah_rx_cal_complete; /* previous rx cal completed or not */ u_int32_t ah_rx_cal_chan; /* chan on which rx cal is done */ u_int32_t ah_rx_cal_chan_flag; u_int32_t ah_rx_cal_corr[AR9300_MAX_CHAINS]; /* Local additions for FreeBSD */ /* * These fields are in the top level HAL in the atheros * codebase; here we place them in the AR9300 HAL and * access them via accessor methods if the driver requires them. */ u_int32_t ah_ob_db1[3]; u_int32_t ah_db2[3]; u_int32_t ah_bb_panic_timeout_ms; u_int32_t ah_bb_panic_last_status; u_int32_t ah_tx_trig_level; u_int16_t ath_hal_spur_chans[AR_EEPROM_MODAL_SPURS][2]; int16_t nf_cw_int_delta; /* diff btwn nominal NF and CW interf threshold */ int ah_phyrestart_disabled; HAL_RSSI_TX_POWER green_tx_status; int green_ap_ps_on; int ah_enable_keysearch_always; int ah_fccaifs; int ah_reset_reason; int ah_dcs_enable; HAL_ANI_STATE ext_ani_state; /* FreeBSD; external facing ANI state */ struct ar9300NfLimits nf_2GHz; struct ar9300NfLimits nf_5GHz; struct ar9300NfLimits *nfp; uint32_t ah_beaconInterval; }; #define AH9300(_ah) ((struct ath_hal_9300 *)(_ah)) #define IS_9300_EMU(ah) \ (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_EMU_PCIE) #define ar9300_eep_data_in_flash(_ah) \ (!(AH_PRIVATE(_ah)->ah_flags & AH_USE_EEPROM)) #ifdef notyet // Need these additional conditions for IS_5GHZ_FAST_CLOCK_EN when we have valid eeprom contents. && \ ((ar9300_eeprom_get(AH9300(_ah), EEP_MINOR_REV) <= AR9300_EEP_MINOR_VER_16) || \ (ar9300_eeprom_get(AH9300(_ah), EEP_FSTCLK_5G)))) #endif /* * WAR for bug 6773. OS_DELAY() does a PIO READ on the PCI bus which allows * other cards' DMA reads to complete in the middle of our reset. */ #define WAR_6773(x) do { \ if ((++(x) % 64) == 0) \ OS_DELAY(1); \ } while (0) #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \ int r; \ for (r = 0; r < ((iniarray)->ia_rows); r++) { \ OS_REG_WRITE(ah, INI_RA((iniarray), (r), 0), INI_RA((iniarray), r, (column)));\ WAR_6773(regWr); \ } \ } while (0) #define UPPER_5G_SUB_BANDSTART 5700 #define MID_5G_SUB_BANDSTART 5400 #define TRAINPOWER_DB_OFFSET 6 #define AH_PAPRD_GET_SCALE_FACTOR(_scale, _eep, _is2G, _channel) do{ if(_is2G) { _scale = (_eep->modal_header_2g.paprd_rate_mask_ht20>>25)&0x7; \ } else { \ if(_channel >= UPPER_5G_SUB_BANDSTART){ _scale = (_eep->modal_header_5g.paprd_rate_mask_ht20>>25)&0x7;} \ else if((UPPER_5G_SUB_BANDSTART < _channel) && (_channel >= MID_5G_SUB_BANDSTART)) \ { _scale = (_eep->modal_header_5g.paprd_rate_mask_ht40>>28)&0x7;} \ else { _scale = (_eep->modal_header_5g.paprd_rate_mask_ht40>>25)&0x7;} } }while(0) #ifdef AH_ASSERT #define ar9300FeatureNotSupported(feature, ah, func) \ ath_hal_printf(ah, # feature \ " not supported but called from %s\n", (func)), \ hal_assert(0) #else #define ar9300FeatureNotSupported(feature, ah, func) \ ath_hal_printf(ah, # feature \ " not supported but called from %s\n", (func)) #endif /* AH_ASSERT */ /* * Green Tx, Based on different RSSI of Received Beacon thresholds, * using different tx power by modified register tx power related values. * The thresholds are decided by system team. */ #define WB225_SW_GREEN_TX_THRES1_DB 56 /* in dB */ #define WB225_SW_GREEN_TX_THRES2_DB 41 /* in dB */ #define WB225_OB_CALIBRATION_VALUE 5 /* For Green Tx OLPC Delta Calibration Offset */ #define WB225_OB_GREEN_TX_SHORT_VALUE 1 /* For Green Tx OB value in short distance*/ #define WB225_OB_GREEN_TX_MIDDLE_VALUE 3 /* For Green Tx OB value in middle distance */ #define WB225_OB_GREEN_TX_LONG_VALUE 5 /* For Green Tx OB value in long distance */ #define WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE 0x06060606 /* For SwGreen Tx BB_powertx_rate9 reg value in short distance */ #define WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE 0x0E0E0E0E /* For SwGreen Tx BB_powertx_rate9 reg value in middle distance */ /* Tx power for short distacnce in SwGreenTx.*/ static const u_int8_t wb225_sw_gtx_tp_distance_short[ar9300_rate_size] = { 6, /*ALL_TARGET_LEGACY_6_24*/ 6, /*ALL_TARGET_LEGACY_36*/ 6, /*ALL_TARGET_LEGACY_48*/ 4, /*ALL_TARGET_LEGACY_54*/ 6, /*ALL_TARGET_LEGACY_1L_5L*/ 6, /*ALL_TARGET_LEGACY_5S*/ 6, /*ALL_TARGET_LEGACY_11L*/ 6, /*ALL_TARGET_LEGACY_11S*/ 6, /*ALL_TARGET_HT20_0_8_16*/ 6, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 4, /*ALL_TARGET_HT20_4*/ 4, /*ALL_TARGET_HT20_5*/ 4, /*ALL_TARGET_HT20_6*/ 2, /*ALL_TARGET_HT20_7*/ 0, /*ALL_TARGET_HT20_12*/ 0, /*ALL_TARGET_HT20_13*/ 0, /*ALL_TARGET_HT20_14*/ 0, /*ALL_TARGET_HT20_15*/ 0, /*ALL_TARGET_HT20_20*/ 0, /*ALL_TARGET_HT20_21*/ 0, /*ALL_TARGET_HT20_22*/ 0, /*ALL_TARGET_HT20_23*/ 6, /*ALL_TARGET_HT40_0_8_16*/ 6, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 4, /*ALL_TARGET_HT40_4*/ 4, /*ALL_TARGET_HT40_5*/ 4, /*ALL_TARGET_HT40_6*/ 2, /*ALL_TARGET_HT40_7*/ 0, /*ALL_TARGET_HT40_12*/ 0, /*ALL_TARGET_HT40_13*/ 0, /*ALL_TARGET_HT40_14*/ 0, /*ALL_TARGET_HT40_15*/ 0, /*ALL_TARGET_HT40_20*/ 0, /*ALL_TARGET_HT40_21*/ 0, /*ALL_TARGET_HT40_22*/ 0 /*ALL_TARGET_HT40_23*/ }; /* Tx power for middle distacnce in SwGreenTx.*/ static const u_int8_t wb225_sw_gtx_tp_distance_middle[ar9300_rate_size] = { 14, /*ALL_TARGET_LEGACY_6_24*/ 14, /*ALL_TARGET_LEGACY_36*/ 14, /*ALL_TARGET_LEGACY_48*/ 12, /*ALL_TARGET_LEGACY_54*/ 14, /*ALL_TARGET_LEGACY_1L_5L*/ 14, /*ALL_TARGET_LEGACY_5S*/ 14, /*ALL_TARGET_LEGACY_11L*/ 14, /*ALL_TARGET_LEGACY_11S*/ 14, /*ALL_TARGET_HT20_0_8_16*/ 14, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 14, /*ALL_TARGET_HT20_4*/ 14, /*ALL_TARGET_HT20_5*/ 12, /*ALL_TARGET_HT20_6*/ 10, /*ALL_TARGET_HT20_7*/ 0, /*ALL_TARGET_HT20_12*/ 0, /*ALL_TARGET_HT20_13*/ 0, /*ALL_TARGET_HT20_14*/ 0, /*ALL_TARGET_HT20_15*/ 0, /*ALL_TARGET_HT20_20*/ 0, /*ALL_TARGET_HT20_21*/ 0, /*ALL_TARGET_HT20_22*/ 0, /*ALL_TARGET_HT20_23*/ 14, /*ALL_TARGET_HT40_0_8_16*/ 14, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 14, /*ALL_TARGET_HT40_4*/ 14, /*ALL_TARGET_HT40_5*/ 12, /*ALL_TARGET_HT40_6*/ 10, /*ALL_TARGET_HT40_7*/ 0, /*ALL_TARGET_HT40_12*/ 0, /*ALL_TARGET_HT40_13*/ 0, /*ALL_TARGET_HT40_14*/ 0, /*ALL_TARGET_HT40_15*/ 0, /*ALL_TARGET_HT40_20*/ 0, /*ALL_TARGET_HT40_21*/ 0, /*ALL_TARGET_HT40_22*/ 0 /*ALL_TARGET_HT40_23*/ }; /* OLPC DeltaCalibration Offset unit in half dB.*/ static const u_int8_t wb225_gtx_olpc_cal_offset[6] = { 0, /* OB0*/ 16, /* OB1*/ 9, /* OB2*/ 5, /* OB3*/ 2, /* OB4*/ 0, /* OB5*/ }; /* * Definitions for HwGreenTx */ #define AR9485_HW_GREEN_TX_THRES1_DB 56 /* in dB */ #define AR9485_HW_GREEN_TX_THRES2_DB 41 /* in dB */ #define AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE 0x0C0C0A0A /* For HwGreen Tx BB_powertx_rate9 reg value in short distance */ #define AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE 0x10100E0E /* For HwGreenTx BB_powertx_rate9 reg value in middle distance */ /* Tx power for short distacnce in HwGreenTx.*/ static const u_int8_t ar9485_hw_gtx_tp_distance_short[ar9300_rate_size] = { 14, /*ALL_TARGET_LEGACY_6_24*/ 14, /*ALL_TARGET_LEGACY_36*/ 8, /*ALL_TARGET_LEGACY_48*/ 2, /*ALL_TARGET_LEGACY_54*/ 14, /*ALL_TARGET_LEGACY_1L_5L*/ 14, /*ALL_TARGET_LEGACY_5S*/ 14, /*ALL_TARGET_LEGACY_11L*/ 14, /*ALL_TARGET_LEGACY_11S*/ 12, /*ALL_TARGET_HT20_0_8_16*/ 12, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 12, /*ALL_TARGET_HT20_4*/ 12, /*ALL_TARGET_HT20_5*/ 8, /*ALL_TARGET_HT20_6*/ 2, /*ALL_TARGET_HT20_7*/ 0, /*ALL_TARGET_HT20_12*/ 0, /*ALL_TARGET_HT20_13*/ 0, /*ALL_TARGET_HT20_14*/ 0, /*ALL_TARGET_HT20_15*/ 0, /*ALL_TARGET_HT20_20*/ 0, /*ALL_TARGET_HT20_21*/ 0, /*ALL_TARGET_HT20_22*/ 0, /*ALL_TARGET_HT20_23*/ 10, /*ALL_TARGET_HT40_0_8_16*/ 10, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 10, /*ALL_TARGET_HT40_4*/ 10, /*ALL_TARGET_HT40_5*/ 6, /*ALL_TARGET_HT40_6*/ 2, /*ALL_TARGET_HT40_7*/ 0, /*ALL_TARGET_HT40_12*/ 0, /*ALL_TARGET_HT40_13*/ 0, /*ALL_TARGET_HT40_14*/ 0, /*ALL_TARGET_HT40_15*/ 0, /*ALL_TARGET_HT40_20*/ 0, /*ALL_TARGET_HT40_21*/ 0, /*ALL_TARGET_HT40_22*/ 0 /*ALL_TARGET_HT40_23*/ }; /* Tx power for middle distacnce in HwGreenTx.*/ static const u_int8_t ar9485_hw_gtx_tp_distance_middle[ar9300_rate_size] = { 18, /*ALL_TARGET_LEGACY_6_24*/ 18, /*ALL_TARGET_LEGACY_36*/ 14, /*ALL_TARGET_LEGACY_48*/ 12, /*ALL_TARGET_LEGACY_54*/ 18, /*ALL_TARGET_LEGACY_1L_5L*/ 18, /*ALL_TARGET_LEGACY_5S*/ 18, /*ALL_TARGET_LEGACY_11L*/ 18, /*ALL_TARGET_LEGACY_11S*/ 16, /*ALL_TARGET_HT20_0_8_16*/ 16, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 16, /*ALL_TARGET_HT20_4*/ 16, /*ALL_TARGET_HT20_5*/ 14, /*ALL_TARGET_HT20_6*/ 12, /*ALL_TARGET_HT20_7*/ 0, /*ALL_TARGET_HT20_12*/ 0, /*ALL_TARGET_HT20_13*/ 0, /*ALL_TARGET_HT20_14*/ 0, /*ALL_TARGET_HT20_15*/ 0, /*ALL_TARGET_HT20_20*/ 0, /*ALL_TARGET_HT20_21*/ 0, /*ALL_TARGET_HT20_22*/ 0, /*ALL_TARGET_HT20_23*/ 14, /*ALL_TARGET_HT40_0_8_16*/ 14, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 14, /*ALL_TARGET_HT40_4*/ 14, /*ALL_TARGET_HT40_5*/ 14, /*ALL_TARGET_HT40_6*/ 12, /*ALL_TARGET_HT40_7*/ 0, /*ALL_TARGET_HT40_12*/ 0, /*ALL_TARGET_HT40_13*/ 0, /*ALL_TARGET_HT40_14*/ 0, /*ALL_TARGET_HT40_15*/ 0, /*ALL_TARGET_HT40_20*/ 0, /*ALL_TARGET_HT40_21*/ 0, /*ALL_TARGET_HT40_22*/ 0 /*ALL_TARGET_HT40_23*/ }; /* MIMO Modes used in TPC calculations */ typedef enum { AR9300_DEF_MODE = 0, /* Could be CDD or Direct */ AR9300_TXBF_MODE, AR9300_STBC_MODE } AR9300_TXMODES; typedef enum { POSEIDON_STORED_REG_OBDB = 0, /* default OB/DB setting from ini */ POSEIDON_STORED_REG_TPC = 1, /* default txpower value in TPC reg */ POSEIDON_STORED_REG_BB_PWRTX_RATE9 = 2, /* default txpower value in * BB_powertx_rate9 reg */ POSEIDON_STORED_REG_SZ /* Can not add anymore */ } POSEIDON_STORED_REGS; typedef enum { POSEIDON_STORED_REG_G2_OLPC_OFFSET = 0,/* default OB/DB setting from ini */ POSEIDON_STORED_REG_G2_SZ /* should not exceed 3 */ } POSEIDON_STORED_REGS_G2; #if AH_NEED_TX_DATA_SWAP #if AH_NEED_RX_DATA_SWAP #define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB | AR_CFG_SWRB,0) #else #define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB,0) #endif #elif AH_NEED_RX_DATA_SWAP #define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWRB,0) #else #define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD,0) #endif extern HAL_BOOL ar9300_rf_attach(struct ath_hal *, HAL_STATUS *); struct ath_hal; extern struct ath_hal_9300 * ar9300_new_state(u_int16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, HAL_OPS_CONFIG *ah_config, HAL_STATUS *status); extern struct ath_hal * ar9300_attach(u_int16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, HAL_OPS_CONFIG *ah_config, HAL_STATUS *status); extern void ar9300_detach(struct ath_hal *ah); extern void ar9300_read_revisions(struct ath_hal *ah); extern HAL_BOOL ar9300_chip_test(struct ath_hal *ah); extern HAL_BOOL ar9300_get_channel_edges(struct ath_hal *ah, u_int16_t flags, u_int16_t *low, u_int16_t *high); extern HAL_BOOL ar9300_fill_capability_info(struct ath_hal *ah); extern void ar9300_beacon_init(struct ath_hal *ah, u_int32_t next_beacon, u_int32_t beacon_period, u_int32_t beacon_period_fraction, HAL_OPMODE opmode); extern void ar9300_set_sta_beacon_timers(struct ath_hal *ah, const HAL_BEACON_STATE *); extern HAL_BOOL ar9300_is_interrupt_pending(struct ath_hal *ah); extern HAL_BOOL ar9300_get_pending_interrupts(struct ath_hal *ah, HAL_INT *, HAL_INT_TYPE, u_int8_t, HAL_BOOL); extern HAL_INT ar9300_get_interrupts(struct ath_hal *ah); extern HAL_INT ar9300_set_interrupts(struct ath_hal *ah, HAL_INT ints, HAL_BOOL); extern void ar9300_set_intr_mitigation_timer(struct ath_hal* ah, HAL_INT_MITIGATION reg, u_int32_t value); extern u_int32_t ar9300_get_intr_mitigation_timer(struct ath_hal* ah, HAL_INT_MITIGATION reg); extern u_int32_t ar9300_get_key_cache_size(struct ath_hal *); extern HAL_BOOL ar9300_is_key_cache_entry_valid(struct ath_hal *, u_int16_t entry); extern HAL_BOOL ar9300_reset_key_cache_entry(struct ath_hal *ah, u_int16_t entry); extern HAL_CHANNEL_INTERNAL * ar9300_check_chan(struct ath_hal *ah, const struct ieee80211_channel *chan); extern HAL_BOOL ar9300_set_key_cache_entry_mac(struct ath_hal *, u_int16_t entry, const u_int8_t *mac); extern HAL_BOOL ar9300_set_key_cache_entry(struct ath_hal *ah, u_int16_t entry, const HAL_KEYVAL *k, const u_int8_t *mac, int xor_key); extern HAL_BOOL ar9300_print_keycache(struct ath_hal *ah); #if ATH_SUPPORT_KEYPLUMB_WAR extern HAL_BOOL ar9300_check_key_cache_entry(struct ath_hal *ah, u_int16_t entry, const HAL_KEYVAL *k, int xorKey); #endif extern void ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac); extern HAL_BOOL ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *); extern void ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mac); extern HAL_BOOL ar9300_set_bss_id_mask(struct ath_hal *, const u_int8_t *); extern HAL_STATUS ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg); #if 0 extern u_int32_t ar9300_ant_ctrl_common_get(struct ath_hal *ah, HAL_BOOL is_2ghz); #endif extern HAL_BOOL ar9300_ant_swcom_sel(struct ath_hal *ah, u_int8_t ops, u_int32_t *common_tbl1, u_int32_t *common_tbl2); extern HAL_BOOL ar9300_set_regulatory_domain(struct ath_hal *ah, u_int16_t reg_domain, HAL_STATUS *stats); extern u_int ar9300_get_wireless_modes(struct ath_hal *ah); extern void ar9300_enable_rf_kill(struct ath_hal *); extern HAL_BOOL ar9300_gpio_cfg_output(struct ath_hal *, u_int32_t gpio, HAL_GPIO_MUX_TYPE signalType); extern HAL_BOOL ar9300_gpio_cfg_output_led_off(struct ath_hal *, u_int32_t gpio, HAL_GPIO_MUX_TYPE signalType); extern HAL_BOOL ar9300_gpio_cfg_input(struct ath_hal *, u_int32_t gpio); extern HAL_BOOL ar9300_gpio_set(struct ath_hal *, u_int32_t gpio, u_int32_t val); extern u_int32_t ar9300_gpio_get(struct ath_hal *ah, u_int32_t gpio); extern u_int32_t ar9300_gpio_get_intr(struct ath_hal *ah); extern void ar9300_gpio_set_intr(struct ath_hal *ah, u_int, u_int32_t ilevel); extern u_int32_t ar9300_gpio_get_polarity(struct ath_hal *ah); extern void ar9300_gpio_set_polarity(struct ath_hal *ah, u_int32_t, u_int32_t); extern u_int32_t ar9300_gpio_get_mask(struct ath_hal *ah); extern int ar9300_gpio_set_mask(struct ath_hal *ah, u_int32_t mask, u_int32_t pol_map); extern void ar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state); extern void ar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enable); extern void ar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enable); extern void ar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid, u_int16_t assoc_id); extern u_int32_t ar9300_ppm_get_rssi_dump(struct ath_hal *); extern u_int32_t ar9300_ppm_arm_trigger(struct ath_hal *); extern int ar9300_ppm_get_trigger(struct ath_hal *); extern u_int32_t ar9300_ppm_force(struct ath_hal *); extern void ar9300_ppm_un_force(struct ath_hal *); extern u_int32_t ar9300_ppm_get_force_state(struct ath_hal *); extern void ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t); extern u_int32_t ar9300_get_dcs_mode(struct ath_hal *ah); extern u_int32_t ar9300_get_tsf32(struct ath_hal *ah); extern u_int64_t ar9300_get_tsf64(struct ath_hal *ah); extern u_int32_t ar9300_get_tsf2_32(struct ath_hal *ah); extern void ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf); extern void ar9300_reset_tsf(struct ath_hal *ah); extern void ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *pSet); extern u_int32_t ar9300_get_random_seed(struct ath_hal *ah); extern HAL_BOOL ar9300_detect_card_present(struct ath_hal *ah); extern void ar9300_update_mib_mac_stats(struct ath_hal *ah); extern void ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats); extern HAL_BOOL ar9300_is_japan_channel_spread_supported(struct ath_hal *ah); extern u_int32_t ar9300_get_cur_rssi(struct ath_hal *ah); extern u_int32_t ar9300_get_rssi_chain0(struct ath_hal *ah); extern u_int ar9300_get_def_antenna(struct ath_hal *ah); extern void ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna); extern HAL_BOOL ar9300_set_antenna_switch(struct ath_hal *ah, HAL_ANT_SETTING settings, const struct ieee80211_channel *chan, u_int8_t *, u_int8_t *, u_int8_t *); extern HAL_BOOL ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah); extern HAL_BOOL ar9300_set_slot_time(struct ath_hal *, u_int); extern HAL_BOOL ar9300_set_ack_timeout(struct ath_hal *, u_int); extern u_int ar9300_get_ack_timeout(struct ath_hal *); extern HAL_STATUS ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration, u_int32_t next_start, HAL_QUIET_FLAG flag); extern void ar9300_set_pcu_config(struct ath_hal *); extern HAL_STATUS ar9300_get_capability(struct ath_hal *, HAL_CAPABILITY_TYPE, u_int32_t, u_int32_t *); extern HAL_BOOL ar9300_set_capability(struct ath_hal *, HAL_CAPABILITY_TYPE, u_int32_t, u_int32_t, HAL_STATUS *); extern HAL_BOOL ar9300_get_diag_state(struct ath_hal *ah, int request, const void *args, u_int32_t argsize, void **result, u_int32_t *resultsize); extern void ar9300_get_desc_info(struct ath_hal *ah, HAL_DESC_INFO *desc_info); extern uint32_t ar9300_get_11n_ext_busy(struct ath_hal *ah); extern void ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode); extern HAL_HT_RXCLEAR ar9300_get_11n_rx_clear(struct ath_hal *ah); extern void ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear); extern HAL_BOOL ar9300_set_power_mode(struct ath_hal *ah, HAL_POWER_MODE mode, int set_chip); extern HAL_POWER_MODE ar9300_get_power_mode(struct ath_hal *ah); extern HAL_BOOL ar9300_set_power_mode_awake(struct ath_hal *ah, int set_chip); extern void ar9300_set_sm_power_mode(struct ath_hal *ah, HAL_SMPS_MODE mode); extern void ar9300_config_pci_power_save(struct ath_hal *ah, int restore, int power_off); extern void ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid, u_int16_t assoc_id); #if ATH_WOW extern void ar9300_wow_apply_pattern(struct ath_hal *ah, u_int8_t *p_ath_pattern, u_int8_t *p_ath_mask, int32_t pattern_count, u_int32_t ath_pattern_len); //extern u_int32_t ar9300_wow_wake_up(struct ath_hal *ah,u_int8_t *chipPatternBytes); extern u_int32_t ar9300_wow_wake_up(struct ath_hal *ah, HAL_BOOL offloadEnable); extern bool ar9300_wow_enable(struct ath_hal *ah, u_int32_t pattern_enable, u_int32_t timeout_in_seconds, int clearbssid, HAL_BOOL offloadEnable); #if ATH_WOW_OFFLOAD /* ARP offload */ #define WOW_OFFLOAD_ARP_INFO_MAX 2 struct hal_wow_offload_arp_info { u_int32_t valid; u_int32_t id; u_int32_t Flags; union { u_int8_t u8[4]; u_int32_t u32; } RemoteIPv4Address; union { u_int8_t u8[4]; u_int32_t u32; } HostIPv4Address; union { u_int8_t u8[6]; u_int32_t u32[2]; } MacAddress; }; /* NS offload */ #define WOW_OFFLOAD_NS_INFO_MAX 2 struct hal_wow_offload_ns_info { u_int32_t valid; u_int32_t id; u_int32_t Flags; union { u_int8_t u8[16]; u_int32_t u32[4]; } RemoteIPv6Address; union { u_int8_t u8[16]; u_int32_t u32[4]; } SolicitedNodeIPv6Address; union { u_int8_t u8[6]; u_int32_t u32[2]; } MacAddress; union { u_int8_t u8[16]; u_int32_t u32[4]; } TargetIPv6Addresses[2]; }; extern void ar9300_wowoffload_prep(struct ath_hal *ah); extern void ar9300_wowoffload_post(struct ath_hal *ah); extern u_int32_t ar9300_wowoffload_download_rekey_data(struct ath_hal *ah, u_int32_t *data, u_int32_t size); extern void ar9300_wowoffload_retrieve_data(struct ath_hal *ah, void *buf, u_int32_t param); extern void ar9300_wowoffload_download_acer_magic(struct ath_hal *ah, HAL_BOOL valid, u_int8_t* datap, u_int32_t bytes); extern void ar9300_wowoffload_download_acer_swka(struct ath_hal *ah, u_int32_t id, HAL_BOOL valid, u_int32_t period, u_int32_t size, u_int32_t* datap); extern void ar9300_wowoffload_download_arp_info(struct ath_hal *ah, u_int32_t id, u_int32_t *data); extern void ar9300_wowoffload_download_ns_info(struct ath_hal *ah, u_int32_t id, u_int32_t *data); #endif /* ATH_WOW_OFFLOAD */ #endif extern HAL_BOOL ar9300_reset(struct ath_hal *ah, HAL_OPMODE opmode, struct ieee80211_channel *chan, HAL_HT_MACMODE macmode, u_int8_t txchainmask, u_int8_t rxchainmask, HAL_HT_EXTPROTSPACING extprotspacing, HAL_BOOL b_channel_change, HAL_STATUS *status, int is_scan); extern HAL_BOOL ar9300_lean_channel_change(struct ath_hal *ah, HAL_OPMODE opmode, struct ieee80211_channel *chan, HAL_HT_MACMODE macmode, u_int8_t txchainmask, u_int8_t rxchainmask); extern HAL_BOOL ar9300_set_reset_reg(struct ath_hal *ah, u_int32_t type); extern void ar9300_init_pll(struct ath_hal *ah, struct ieee80211_channel *chan); extern void ar9300_green_ap_ps_on_off( struct ath_hal *ah, u_int16_t rxMask); extern u_int16_t ar9300_is_single_ant_power_save_possible(struct ath_hal *ah); extern void ar9300_set_operating_mode(struct ath_hal *ah, int opmode); extern HAL_BOOL ar9300_phy_disable(struct ath_hal *ah); extern HAL_BOOL ar9300_disable(struct ath_hal *ah); extern HAL_BOOL ar9300_chip_reset(struct ath_hal *ah, struct ieee80211_channel *); extern HAL_BOOL ar9300_calibration(struct ath_hal *ah, struct ieee80211_channel *chan, u_int8_t rxchainmask, HAL_BOOL longcal, HAL_BOOL *isIQdone, int is_scan, u_int32_t *sched_cals); extern void ar9300_reset_cal_valid(struct ath_hal *ah, const struct ieee80211_channel *chan, HAL_BOOL *isIQdone, u_int32_t cal_type); extern void ar9300_iq_cal_collect(struct ath_hal *ah, u_int8_t num_chains); extern void ar9300_iq_calibration(struct ath_hal *ah, u_int8_t num_chains); extern void ar9300_temp_comp_cal_collect(struct ath_hal *ah); extern void ar9300_temp_comp_calibration(struct ath_hal *ah, u_int8_t num_chains); extern int16_t ar9300_get_min_cca_pwr(struct ath_hal *ah); extern void ar9300_upload_noise_floor(struct ath_hal *ah, int is2G, int16_t nfarray[]); extern HAL_BOOL ar9300_set_tx_power_limit(struct ath_hal *ah, u_int32_t limit, u_int16_t extra_txpow, u_int16_t tpc_in_db); extern void ar9300_chain_noise_floor(struct ath_hal *ah, int16_t *nf_buf, struct ieee80211_channel *chan, int is_scan); extern int16_t ar9300_get_nf_from_reg(struct ath_hal *ah, struct ieee80211_channel *chan, int wait_time); extern int ar9300_get_rx_nf_offset(struct ath_hal *ah, struct ieee80211_channel *chan, int8_t *nf_pwr, int8_t *nf_cal); extern HAL_BOOL ar9300_load_nf(struct ath_hal *ah, int16_t nf[]); extern HAL_RFGAIN ar9300_get_rfgain(struct ath_hal *ah); extern const HAL_RATE_TABLE *ar9300_get_rate_table(struct ath_hal *, u_int mode); extern int16_t ar9300_get_rate_txpower(struct ath_hal *ah, u_int mode, u_int8_t rate_index, u_int8_t chainmask, u_int8_t mimo_mode); extern void ar9300_init_rate_txpower(struct ath_hal *ah, u_int mode, const struct ieee80211_channel *chan, u_int8_t powerPerRate[], u_int8_t chainmask); extern void ar9300_adjust_reg_txpower_cdd(struct ath_hal *ah, u_int8_t powerPerRate[]); extern HAL_STATUS ath_hal_get_rate_power_limit_from_eeprom(struct ath_hal *ah, u_int16_t freq, int8_t *max_rate_power, int8_t *min_rate_power); extern void ar9300_reset_tx_status_ring(struct ath_hal *ah); extern void ar9300_enable_mib_counters(struct ath_hal *); extern void ar9300_disable_mib_counters(struct ath_hal *); extern void ar9300_ani_attach(struct ath_hal *); extern void ar9300_ani_detach(struct ath_hal *); extern struct ar9300_ani_state *ar9300_ani_get_current_state(struct ath_hal *); extern HAL_ANI_STATS *ar9300_ani_get_current_stats(struct ath_hal *); extern HAL_BOOL ar9300_ani_control(struct ath_hal *, HAL_ANI_CMD cmd, int param); struct ath_rx_status; extern void ar9300_process_mib_intr(struct ath_hal *, const HAL_NODE_STATS *); extern void ar9300_ani_ar_poll(struct ath_hal *, const HAL_NODE_STATS *, const struct ieee80211_channel *, HAL_ANISTATS *); extern void ar9300_ani_reset(struct ath_hal *, HAL_BOOL is_scanning); extern void ar9300_ani_init_defaults(struct ath_hal *ah, HAL_HT_MACMODE macmode); extern void ar9300_enable_tpc(struct ath_hal *); extern HAL_BOOL ar9300_rf_gain_cap_apply(struct ath_hal *ah, int is2GHz); extern void ar9300_rx_gain_table_apply(struct ath_hal *ah); extern void ar9300_tx_gain_table_apply(struct ath_hal *ah); extern void ar9300_mat_enable(struct ath_hal *ah, int enable); extern void ar9300_dump_keycache(struct ath_hal *ah, int n, u_int32_t *entry); extern HAL_BOOL ar9300_ant_ctrl_set_lna_div_use_bt_ant(struct ath_hal * ah, HAL_BOOL enable, const struct ieee80211_channel * chan); /* BB Panic Watchdog declarations */ #define HAL_BB_PANIC_WD_TMO 25 /* in ms, 0 to disable */ #define HAL_BB_PANIC_WD_TMO_HORNET 85 extern void ar9300_config_bb_panic_watchdog(struct ath_hal *); extern void ar9300_handle_bb_panic(struct ath_hal *); extern int ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic); extern HAL_BOOL ar9300_handle_radar_bb_panic(struct ath_hal *ah); extern void ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason); /* DFS declarations */ extern void ar9300_check_dfs(struct ath_hal *ah, struct ieee80211_channel *chan); extern void ar9300_dfs_found(struct ath_hal *ah, struct ieee80211_channel *chan, u_int64_t nolTime); extern void ar9300_enable_dfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); extern void ar9300_get_dfs_thresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); extern HAL_BOOL ar9300_radar_wait(struct ath_hal *ah, struct ieee80211_channel *chan); extern struct dfs_pulse * ar9300_get_dfs_radars(struct ath_hal *ah, u_int32_t dfsdomain, int *numradars, struct dfs_bin5pulse **bin5pulses, int *numb5radars, HAL_PHYERR_PARAM *pe); +extern HAL_BOOL ar9300_get_default_dfs_thresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); extern void ar9300_adjust_difs(struct ath_hal *ah, u_int32_t val); extern u_int32_t ar9300_dfs_config_fft(struct ath_hal *ah, HAL_BOOL is_enable); extern void ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable); extern void ar9300_dfs_cac_war(struct ath_hal *ah, u_int32_t start); extern struct ieee80211_channel * ar9300_get_extension_channel(struct ath_hal *ah); extern HAL_BOOL ar9300_is_fast_clock_enabled(struct ath_hal *ah); extern void ar9300_mark_phy_inactive(struct ath_hal *ah); /* Spectral scan declarations */ extern void ar9300_configure_spectral_scan(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss); extern void ar9300_set_cca_threshold(struct ath_hal *ah, u_int8_t thresh62); extern void ar9300_get_spectral_params(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss); extern HAL_BOOL ar9300_is_spectral_active(struct ath_hal *ah); extern HAL_BOOL ar9300_is_spectral_enabled(struct ath_hal *ah); extern void ar9300_start_spectral_scan(struct ath_hal *ah); extern void ar9300_stop_spectral_scan(struct ath_hal *ah); extern u_int32_t ar9300_get_spectral_config(struct ath_hal *ah); extern void ar9300_restore_spectral_config(struct ath_hal *ah, u_int32_t restoreval); int16_t ar9300_get_ctl_chan_nf(struct ath_hal *ah); int16_t ar9300_get_ext_chan_nf(struct ath_hal *ah); /* End spectral scan declarations */ /* Raw ADC capture functions */ extern void ar9300_enable_test_addac_mode(struct ath_hal *ah); extern void ar9300_disable_test_addac_mode(struct ath_hal *ah); extern void ar9300_begin_adc_capture(struct ath_hal *ah, int auto_agc_gain); extern HAL_STATUS ar9300_retrieve_capture_data(struct ath_hal *ah, u_int16_t chain_mask, int disable_dc_filter, void *sample_buf, u_int32_t *max_samples); extern HAL_STATUS ar9300_calc_adc_ref_powers(struct ath_hal *ah, int freq_mhz, int16_t *sample_min, int16_t *sample_max, int32_t *chain_ref_pwr, int num_chain_ref_pwr); extern HAL_STATUS ar9300_get_min_agc_gain(struct ath_hal *ah, int freq_mhz, int32_t *chain_gain, int num_chain_gain); extern HAL_BOOL ar9300_reset_11n(struct ath_hal *ah, HAL_OPMODE opmode, struct ieee80211_channel *chan, HAL_BOOL b_channel_change, HAL_STATUS *status); extern void ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now); extern void ar9300_get_channel_centers(struct ath_hal *ah, const struct ieee80211_channel *chan, CHAN_CENTERS *centers); extern u_int16_t ar9300_get_ctl_center(struct ath_hal *ah, const struct ieee80211_channel *chan); extern u_int16_t ar9300_get_ext_center(struct ath_hal *ah, const struct ieee80211_channel *chan); extern u_int32_t ar9300_get_mib_cycle_counts_pct(struct ath_hal *, u_int32_t*, u_int32_t*, u_int32_t*); extern void ar9300_dma_reg_dump(struct ath_hal *); extern HAL_BOOL ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable); extern HAL_BOOL ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable); extern HAL_BOOL ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable); extern HAL_BOOL ar9300_detect_bb_hang(struct ath_hal *ah); extern HAL_BOOL ar9300_detect_mac_hang(struct ath_hal *ah); #ifdef ATH_BT_COEX extern void ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo); extern void ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf); extern void ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum); extern void ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type); extern void ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh); extern void ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type, u_int32_t value); extern void ar9300_bt_coex_disable(struct ath_hal *ah); extern int ar9300_bt_coex_enable(struct ath_hal *ah); extern void ar9300_init_bt_coex(struct ath_hal *ah); extern u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg); extern u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn); #endif extern int ar9300_alloc_generic_timer(struct ath_hal *ah, HAL_GEN_TIMER_DOMAIN tsf); extern void ar9300_free_generic_timer(struct ath_hal *ah, int index); extern void ar9300_start_generic_timer(struct ath_hal *ah, int index, u_int32_t timer_next, u_int32_t timer_period); extern void ar9300_stop_generic_timer(struct ath_hal *ah, int index); extern void ar9300_get_gen_timer_interrupts(struct ath_hal *ah, u_int32_t *trigger, u_int32_t *thresh); extern void ar9300_start_tsf2(struct ath_hal *ah); extern void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi); extern HAL_BOOL ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah); extern void ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah); extern void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value); extern HAL_BOOL ar9300_is_ani_noise_spur(struct ath_hal *ah); extern void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah); extern int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah); extern void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah, u_int32_t rssi_threshold); extern void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah); extern void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on); extern void ar9300_get_vow_stats(struct ath_hal *ah, HAL_VOWSTATS *p_stats, u_int8_t); extern int ar9300_get_spur_info(struct ath_hal * ah, int *enable, int len, u_int16_t *freq); extern int ar9300_set_spur_info(struct ath_hal * ah, int enable, int len, u_int16_t *freq); extern void ar9300_wow_set_gpio_reset_low(struct ath_hal * ah); extern HAL_BOOL ar9300_get_mib_cycle_counts(struct ath_hal *, HAL_SURVEY_SAMPLE *); extern void ar9300_clear_mib_counters(struct ath_hal *ah); /* EEPROM interface functions */ /* Common Interface functions */ extern HAL_STATUS ar9300_eeprom_attach(struct ath_hal *); extern u_int32_t ar9300_eeprom_get(struct ath_hal_9300 *ahp, EEPROM_PARAM param); extern u_int32_t ar9300_ini_fixup(struct ath_hal *ah, ar9300_eeprom_t *p_eep_data, u_int32_t reg, u_int32_t val); extern HAL_STATUS ar9300_eeprom_set_transmit_power(struct ath_hal *ah, ar9300_eeprom_t *p_eep_data, const struct ieee80211_channel *chan, u_int16_t cfg_ctl, u_int16_t twice_antenna_reduction, u_int16_t twice_max_regulatory_power, u_int16_t power_limit); extern void ar9300_eeprom_set_addac(struct ath_hal *, struct ieee80211_channel *); extern HAL_BOOL ar9300_eeprom_set_param(struct ath_hal *ah, EEPROM_PARAM param, u_int32_t value); extern HAL_BOOL ar9300_eeprom_set_board_values(struct ath_hal *, const struct ieee80211_channel *); extern HAL_BOOL ar9300_eeprom_read_word(struct ath_hal *, u_int off, u_int16_t *data); extern HAL_BOOL ar9300_eeprom_read(struct ath_hal *ah, long address, u_int8_t *buffer, int many); extern HAL_BOOL ar9300_otp_read(struct ath_hal *ah, u_int off, u_int32_t *data, HAL_BOOL is_wifi); extern HAL_BOOL ar9300_flash_read(struct ath_hal *, u_int off, u_int16_t *data); extern HAL_BOOL ar9300_flash_write(struct ath_hal *, u_int off, u_int16_t data); extern u_int ar9300_eeprom_dump_support(struct ath_hal *ah, void **pp_e); extern u_int8_t ar9300_eeprom_get_num_ant_config(struct ath_hal_9300 *ahp, HAL_FREQ_BAND freq_band); extern HAL_STATUS ar9300_eeprom_get_ant_cfg(struct ath_hal_9300 *ahp, const struct ieee80211_channel *chan, u_int8_t index, u_int16_t *config); extern u_int8_t* ar9300_eeprom_get_cust_data(struct ath_hal_9300 *ahp); extern u_int8_t *ar9300_eeprom_get_spur_chans_ptr(struct ath_hal *ah, HAL_BOOL is_2ghz); extern HAL_BOOL ar9300_interference_is_present(struct ath_hal *ah); extern HAL_BOOL ar9300_tuning_caps_apply(struct ath_hal *ah); extern void ar9300_disp_tpc_tables(struct ath_hal *ah); extern u_int8_t *ar9300_get_tpc_tables(struct ath_hal *ah); extern u_int8_t ar9300_eeprom_set_tx_gain_cap(struct ath_hal *ah, int *tx_gain_max); extern u_int8_t ar9300_eeprom_tx_gain_table_index_max_apply(struct ath_hal *ah, u_int16_t channel); /* Common EEPROM Help function */ extern void ar9300_set_immunity(struct ath_hal *ah, HAL_BOOL enable); extern void ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs); extern u_int ar9300_mac_to_clks(struct ath_hal *ah, u_int clks); /* tx_bf interface */ #define ar9300_init_txbf(ah) #define ar9300_set_11n_txbf_sounding(ah, ds, series, cec, opt) #define ar9300_set_11n_txbf_cal(ah, ds, cal_pos, code_rate, cec, opt) #define ar9300_txbf_save_cv_from_compress( \ ah, key_idx, mimo_control, compress_rpt) \ false #define ar9300_txbf_save_cv_from_non_compress( \ ah, key_idx, mimo_control, non_compress_rpt) \ false #define ar9300_txbf_rc_update( \ ah, rx_status, local_h, csi_frame, ness_a, ness_b, bw) \ false #define ar9300_fill_csi_frame( \ ah, rx_status, bandwidth, local_h, csi_frame_body) \ 0 #define ar9300_fill_txbf_capabilities(ah) #define ar9300_get_txbf_capabilities(ah) NULL #define ar9300_txbf_set_key( \ ah, entry, rx_staggered_sounding, channel_estimation_cap, mmss) #define ar9300_read_key_cache_mac(ah, entry, mac) false #define ar9300_txbf_get_cv_cache_nr(ah, key_idx, nr) #define ar9300_set_selfgenrate_limit(ah, ts_ratecode) #define ar9300_reset_lowest_txrate(ah) #define ar9300_txbf_set_basic_set(ah) extern void ar9300_crdc_rx_notify(struct ath_hal *ah, struct ath_rx_status *rxs); extern void ar9300_chain_rssi_diff_compensation(struct ath_hal *ah); #if ATH_SUPPORT_MCI extern void ar9300_mci_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type); extern void ar9300_mci_bt_coex_disable(struct ath_hal *ah); extern int ar9300_mci_bt_coex_enable(struct ath_hal *ah); extern void ar9300_mci_setup (struct ath_hal *ah, u_int32_t gpm_addr, void *gpm_buf, u_int16_t len, u_int32_t sched_addr); extern void ar9300_mci_remote_reset(struct ath_hal *ah, HAL_BOOL wait_done); extern void ar9300_mci_send_lna_transfer(struct ath_hal *ah, HAL_BOOL wait_done); extern void ar9300_mci_send_sys_waking(struct ath_hal *ah, HAL_BOOL wait_done); extern HAL_BOOL ar9300_mci_send_message (struct ath_hal *ah, u_int8_t header, u_int32_t flag, u_int32_t *payload, u_int8_t len, HAL_BOOL wait_done, HAL_BOOL check_bt); extern u_int32_t ar9300_mci_get_interrupt (struct ath_hal *ah, u_int32_t *mci_int, u_int32_t *mci_int_rx_msg); extern u_int32_t ar9300_mci_state (struct ath_hal *ah, u_int32_t state_type, u_int32_t *p_data); extern void ar9300_mci_reset (struct ath_hal *ah, HAL_BOOL en_int, HAL_BOOL is_2g, HAL_BOOL is_full_sleep); extern void ar9300_mci_send_coex_halt_bt_gpm(struct ath_hal *ah, HAL_BOOL halt, HAL_BOOL wait_done); extern void ar9300_mci_mute_bt(struct ath_hal *ah); extern u_int32_t ar9300_mci_wait_for_gpm(struct ath_hal *ah, u_int8_t gpm_type, u_int8_t gpm_opcode, int32_t time_out); extern void ar9300_mci_enable_interrupt(struct ath_hal *ah); extern void ar9300_mci_disable_interrupt(struct ath_hal *ah); extern void ar9300_mci_detach (struct ath_hal *ah); extern u_int32_t ar9300_mci_check_int (struct ath_hal *ah, u_int32_t ints); extern void ar9300_mci_sync_bt_state (struct ath_hal *ah); extern void ar9300_mci_2g5g_changed(struct ath_hal *ah, HAL_BOOL is_2g); extern void ar9300_mci_2g5g_switch(struct ath_hal *ah, HAL_BOOL wait_done); #if ATH_SUPPORT_AIC extern u_int32_t ar9300_aic_calibration (struct ath_hal *ah); extern u_int32_t ar9300_aic_start_normal (struct ath_hal *ah); #endif #endif extern HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable); extern HAL_BOOL ar9300_regulatory_domain_override( struct ath_hal *ah, u_int16_t regdmn); #if ATH_ANT_DIV_COMB extern void ar9300_ant_div_comb_get_config(struct ath_hal *ah, HAL_ANT_COMB_CONFIG* div_comb_conf); extern void ar9300_ant_div_comb_set_config(struct ath_hal *ah, HAL_ANT_COMB_CONFIG* div_comb_conf); #endif /* ATH_ANT_DIV_COMB */ extern void ar9300_disable_phy_restart(struct ath_hal *ah, int disable_phy_restart); extern void ar9300_enable_keysearch_always(struct ath_hal *ah, int enable); extern HAL_BOOL ar9300ForceVCS( struct ath_hal *ah); extern HAL_BOOL ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val); extern HAL_BOOL ar9300Get3StreamSignature( struct ath_hal *ah); #ifdef ATH_TX99_DIAG #ifndef ATH_SUPPORT_HTC extern void ar9300_tx99_channel_pwr_update(struct ath_hal *ah, struct ieee80211_channel *c, u_int32_t txpower); extern void ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask); extern void ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, int chtype); extern void ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data); extern void ar9300_tx99_stop(struct ath_hal *ah); #endif /* ATH_SUPPORT_HTC */ #endif /* ATH_TX99_DIAG */ extern HAL_BOOL ar9300_set_ctl_pwr(struct ath_hal *ah, u_int8_t *ctl_array); extern void ar9300_set_txchainmaskopt(struct ath_hal *ah, u_int8_t mask); enum { AR9300_COEFF_TX_TYPE = 0, AR9300_COEFF_RX_TYPE }; #endif /* _ATH_AR9300_H_ */ Index: head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_freebsd.c =================================================================== --- head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_freebsd.c (revision 313090) +++ head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_freebsd.c (revision 313091) @@ -1,816 +1,806 @@ /* * Copyright (c) 2012, 2013 Adrian Chadd . * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #include "opt_ah.h" #include "ah.h" #include "ah_internal.h" #include "ah_devid.h" #include "ah_desc.h" #include "ar9300.h" #include "ar9300reg.h" #include "ar9300phy.h" #include "ar9300desc.h" #include "ar9300_freebsd.h" #include "ar9300_stub.h" #include "ar9300_stub_funcs.h" #define FIX_NOISE_FLOOR 1 #define NEXT_TBTT_NOW 5 static HAL_BOOL ar9300ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix); static HAL_BOOL ar9300SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix); static void ar9300_beacon_set_beacon_timers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt); static void ar9300SetChainMasks(struct ath_hal *ah, uint32_t tx_chainmask, uint32_t rx_chainmask) { AH9300(ah)->ah_tx_chainmask = tx_chainmask & AH_PRIVATE(ah)->ah_caps.halTxChainMask; AH9300(ah)->ah_rx_chainmask = rx_chainmask & AH_PRIVATE(ah)->ah_caps.halRxChainMask; } static u_int ar9300GetSlotTime(struct ath_hal *ah) { u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff; return (ath_hal_mac_usec(ah, clks)); /* convert from system clocks */ } static HAL_BOOL ar9300_freebsd_set_tx_power_limit(struct ath_hal *ah, uint32_t limit) { return (ar9300_set_tx_power_limit(ah, limit, 0, 0)); } static uint64_t ar9300_get_next_tbtt(struct ath_hal *ah) { return (OS_REG_READ(ah, AR_NEXT_TBTT_TIMER)); } /* * TODO: implement the antenna diversity control for AR9485 and * other LNA mixing based NICs. * * For now we'll just go with the HAL default and make these no-ops. */ static HAL_ANT_SETTING ar9300_freebsd_get_antenna_switch(struct ath_hal *ah) { return (HAL_ANT_VARIABLE); } static HAL_BOOL ar9300_freebsd_set_antenna_switch(struct ath_hal *ah, HAL_ANT_SETTING setting) { return (AH_TRUE); } static u_int ar9300_freebsd_get_cts_timeout(struct ath_hal *ah) { u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS); return ath_hal_mac_usec(ah, clks); /* convert from system clocks */ } static void ar9300_freebsd_set_tsf64(struct ath_hal *ah, uint64_t tsf64) { /* * XXX TODO: read ar5416SetTsf64() - we should wait before we do * this. */ OS_REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); OS_REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); } void ar9300_attach_freebsd_ops(struct ath_hal *ah) { /* Global functions */ ah->ah_detach = ar9300_detach; ah->ah_getRateTable = ar9300_get_rate_table; /* Reset functions */ ah->ah_reset = ar9300_reset_freebsd; ah->ah_phyDisable = ar9300_phy_disable; ah->ah_disable = ar9300_disable; ah->ah_configPCIE = ar9300_config_pcie_freebsd; // ah->ah_disablePCIE = ar9300_disable_pcie_phy; ah->ah_setPCUConfig = ar9300_set_pcu_config; // perCalibration ah->ah_perCalibrationN = ar9300_per_calibration_freebsd; ah->ah_resetCalValid = ar9300_reset_cal_valid_freebsd; ah->ah_setTxPowerLimit = ar9300_freebsd_set_tx_power_limit; ah->ah_getChanNoise = ath_hal_getChanNoise; /* Transmit functions */ ah->ah_setupTxQueue = ar9300_setup_tx_queue; ah->ah_setTxQueueProps = ar9300_set_tx_queue_props; ah->ah_getTxQueueProps = ar9300_get_tx_queue_props; ah->ah_releaseTxQueue = ar9300_release_tx_queue; ah->ah_resetTxQueue = ar9300_reset_tx_queue; ah->ah_getTxDP = ar9300_get_tx_dp; ah->ah_setTxDP = ar9300_set_tx_dp; ah->ah_numTxPending = ar9300_num_tx_pending; ah->ah_startTxDma = ar9300_start_tx_dma; ah->ah_stopTxDma = ar9300_stop_tx_dma_freebsd; ah->ah_setupTxDesc = ar9300_freebsd_setup_tx_desc; ah->ah_setupXTxDesc = ar9300_freebsd_setup_x_tx_desc; ah->ah_fillTxDesc = ar9300_freebsd_fill_tx_desc; ah->ah_procTxDesc = ar9300_freebsd_proc_tx_desc; ah->ah_getTxIntrQueue = ar9300_get_tx_intr_queue; // reqTxIntrDesc ah->ah_getTxCompletionRates = ar9300_freebsd_get_tx_completion_rates; ah->ah_setTxDescLink = ar9300_set_desc_link; ah->ah_getTxDescLink = ar9300_freebsd_get_desc_link; ah->ah_getTxDescLinkPtr = ar9300_get_desc_link_ptr; ah->ah_setupTxStatusRing = ar9300_setup_tx_status_ring; ah->ah_getTxRawTxDesc = ar9300_get_raw_tx_desc; ah->ah_updateTxTrigLevel = ar9300_update_tx_trig_level; /* RX functions */ ah->ah_getRxDP = ar9300_get_rx_dp; ah->ah_setRxDP = ar9300_set_rx_dp; ah->ah_enableReceive = ar9300_enable_receive; ah->ah_stopDmaReceive = ar9300_stop_dma_receive_freebsd; ah->ah_startPcuReceive = ar9300_start_pcu_receive_freebsd; ah->ah_stopPcuReceive = ar9300_stop_pcu_receive; ah->ah_setMulticastFilter = ar9300_set_multicast_filter; ah->ah_setMulticastFilterIndex = ar9300SetMulticastFilterIndex; ah->ah_clrMulticastFilterIndex = ar9300ClrMulticastFilterIndex; ah->ah_getRxFilter = ar9300_get_rx_filter; ah->ah_setRxFilter = ar9300_set_rx_filter; /* setupRxDesc */ ah->ah_procRxDesc = ar9300_proc_rx_desc_freebsd; ah->ah_rxMonitor = ar9300_ani_rxmonitor_freebsd; ah->ah_aniPoll = ar9300_ani_poll_freebsd; ah->ah_procMibEvent = ar9300_process_mib_intr; /* Misc functions */ ah->ah_getCapability = ar9300_get_capability; ah->ah_setCapability = ar9300_set_capability; ah->ah_getDiagState = ar9300_get_diag_state; ah->ah_getMacAddress = ar9300_get_mac_address; ah->ah_setMacAddress = ar9300_set_mac_address; ah->ah_getBssIdMask = ar9300_get_bss_id_mask; ah->ah_setBssIdMask = ar9300_set_bss_id_mask; ah->ah_setRegulatoryDomain = ar9300_set_regulatory_domain; ah->ah_setLedState = ar9300_set_led_state; ah->ah_writeAssocid = ar9300_write_associd; ah->ah_gpioCfgInput = ar9300_gpio_cfg_input; ah->ah_gpioCfgOutput = ar9300_gpio_cfg_output; ah->ah_gpioGet = ar9300_gpio_get; ah->ah_gpioSet = ar9300_gpio_set; ah->ah_gpioSetIntr = ar9300_gpio_set_intr; /* polarity */ /* mask */ ah->ah_getTsf32 = ar9300_get_tsf32; ah->ah_getTsf64 = ar9300_get_tsf64; ah->ah_resetTsf = ar9300_reset_tsf; ah->ah_setTsf64 = ar9300_freebsd_set_tsf64; ah->ah_detectCardPresent = ar9300_detect_card_present; // ah->ah_updateMibCounters = ar9300_update_mib_counters; ah->ah_getRfGain = ar9300_get_rfgain; ah->ah_getDefAntenna = ar9300_get_def_antenna; ah->ah_setDefAntenna = ar9300_set_def_antenna; ah->ah_getAntennaSwitch = ar9300_freebsd_get_antenna_switch; ah->ah_setAntennaSwitch = ar9300_freebsd_set_antenna_switch; // ah->ah_setSifsTime = ar9300_set_sifs_time; // ah->ah_getSifsTime = ar9300_get_sifs_time; ah->ah_setSlotTime = ar9300_set_slot_time; ah->ah_getSlotTime = ar9300GetSlotTime; ah->ah_getAckTimeout = ar9300_get_ack_timeout; ah->ah_setAckTimeout = ar9300_set_ack_timeout; // XXX ack/ctsrate // XXX CTS timeout ah->ah_getCTSTimeout = ar9300_freebsd_get_cts_timeout; // XXX decompmask // coverageclass ah->ah_setQuiet = ar9300_set_quiet; ah->ah_getMibCycleCounts = ar9300_freebsd_get_mib_cycle_counts; /* DFS functions */ ah->ah_enableDfs = ar9300_enable_dfs; ah->ah_getDfsThresh = ar9300_get_dfs_thresh; - ah->ah_getDfsDefaultThresh = ar9300_freebsd_get_dfs_default_thresh; + ah->ah_getDfsDefaultThresh = ar9300_get_default_dfs_thresh; // procradarevent ah->ah_isFastClockEnabled = ar9300_is_fast_clock_enabled; ah->ah_get11nExtBusy = ar9300_get_11n_ext_busy; /* Spectral Scan Functions */ ah->ah_spectralConfigure = ar9300_configure_spectral_scan; ah->ah_spectralGetConfig = ar9300_get_spectral_params; ah->ah_spectralStart = ar9300_start_spectral_scan; ah->ah_spectralStop = ar9300_stop_spectral_scan; ah->ah_spectralIsEnabled = ar9300_is_spectral_enabled; ah->ah_spectralIsActive = ar9300_is_spectral_active; /* Key cache functions */ ah->ah_getKeyCacheSize = ar9300_get_key_cache_size; ah->ah_resetKeyCacheEntry = ar9300_reset_key_cache_entry; ah->ah_isKeyCacheEntryValid = ar9300_is_key_cache_entry_valid; ah->ah_setKeyCacheEntry = ar9300_set_key_cache_entry; ah->ah_setKeyCacheEntryMac = ar9300_set_key_cache_entry_mac; /* Power management functions */ ah->ah_setPowerMode = ar9300_set_power_mode; ah->ah_getPowerMode = ar9300_get_power_mode; /* Beacon functions */ /* ah_setBeaconTimers */ ah->ah_beaconInit = ar9300_freebsd_beacon_init; ah->ah_setBeaconTimers = ar9300_beacon_set_beacon_timers; ah->ah_setStationBeaconTimers = ar9300_set_sta_beacon_timers; /* ah_resetStationBeaconTimers */ ah->ah_getNextTBTT = ar9300_get_next_tbtt; /* Interrupt functions */ ah->ah_isInterruptPending = ar9300_is_interrupt_pending; ah->ah_getPendingInterrupts = ar9300_get_pending_interrupts_freebsd; ah->ah_getInterrupts = ar9300_get_interrupts; ah->ah_setInterrupts = ar9300_set_interrupts_freebsd; /* Regulatory/internal functions */ // AH_PRIVATE(ah)->ah_getNfAdjust = ar9300_get_nf_adjust; AH_PRIVATE(ah)->ah_eepromRead = ar9300_eeprom_read_word; // AH_PRIVATE(ah)->ah_getChipPowerLimits = ar9300_get_chip_power_limits; AH_PRIVATE(ah)->ah_getWirelessModes = ar9300_get_wireless_modes; AH_PRIVATE(ah)->ah_getChannelEdges = ar9300_get_channel_edges; AH_PRIVATE(ah)->ah_eepromRead = ar9300_eeprom_read_word; /* XXX ah_eeprom */ /* XXX ah_eeversion */ /* XXX ah_eepromDetach */ /* XXX ah_eepromGet */ AH_PRIVATE(ah)->ah_eepromGet = ar9300_eeprom_get_freebsd; /* XXX ah_eepromSet */ /* XXX ah_getSpurChan */ /* XXX ah_eepromDiag */ /* 802.11n functions */ ah->ah_chainTxDesc = ar9300_freebsd_chain_tx_desc; ah->ah_setupFirstTxDesc= ar9300_freebsd_setup_first_tx_desc; ah->ah_setupLastTxDesc = ar9300_freebsd_setup_last_tx_desc; ah->ah_set11nRateScenario = ar9300_freebsd_set_11n_rate_scenario; ah->ah_set11nTxDesc = ar9300_freebsd_setup_11n_desc; ah->ah_set11nAggrFirst = ar9300_set_11n_aggr_first; ah->ah_set11nAggrMiddle = ar9300_set_11n_aggr_middle; ah->ah_set11nAggrLast = ar9300_set_11n_aggr_last; ah->ah_clr11nAggr = ar9300_clr_11n_aggr; ah->ah_set11nBurstDuration = ar9300_set_11n_burst_duration; /* ah_get11nExtBusy */ ah->ah_set11nMac2040 = ar9300_set_11n_mac2040; ah->ah_setChainMasks = ar9300SetChainMasks; /* ah_get11nRxClear */ /* ah_set11nRxClear */ /* bluetooth coexistence functions */ ah->ah_btCoexSetInfo = ar9300_set_bt_coex_info; ah->ah_btCoexSetConfig = ar9300_bt_coex_config; ah->ah_btCoexSetQcuThresh = ar9300_bt_coex_set_qcu_thresh; ah->ah_btCoexSetWeights = ar9300_bt_coex_set_weights; ah->ah_btCoexSetBmissThresh = ar9300_bt_coex_setup_bmiss_thresh; ah->ah_btCoexSetParameter = ar9300_bt_coex_set_parameter; ah->ah_btCoexDisable = ar9300_bt_coex_disable; ah->ah_btCoexEnable = ar9300_bt_coex_enable; /* MCI bluetooth functions */ if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { /* * Note: these are done in attach too for now, because * at this point we haven't yet setup the mac/bb revision * values, so this code is effectively NULL. * However, I'm leaving this here so people digging * into the code (a) see the MCI bits here, and (b) * are now told they should look elsewhere for * these methods. */ ah->ah_btCoexSetWeights = ar9300_mci_bt_coex_set_weights; ah->ah_btCoexDisable = ar9300_mci_bt_coex_disable; ah->ah_btCoexEnable = ar9300_mci_bt_coex_enable; } ah->ah_btMciSetup = ar9300_mci_setup; ah->ah_btMciSendMessage = ar9300_mci_send_message; ah->ah_btMciGetInterrupt = ar9300_mci_get_interrupt; ah->ah_btMciState = ar9300_mci_state; ah->ah_btMciDetach = ar9300_mci_detach; /* LNA diversity functions */ ah->ah_divLnaConfGet = ar9300_ant_div_comb_get_config; ah->ah_divLnaConfSet = ar9300_ant_div_comb_set_config; } HAL_BOOL ar9300_reset_freebsd(struct ath_hal *ah, HAL_OPMODE opmode, struct ieee80211_channel *chan, HAL_BOOL bChannelChange, HAL_RESET_TYPE resetType, HAL_STATUS *status) { HAL_BOOL r; HAL_HT_MACMODE macmode; struct ath_hal_private *ap = AH_PRIVATE(ah); macmode = IEEE80211_IS_CHAN_HT40(chan) ? HAL_HT_MACMODE_2040 : HAL_HT_MACMODE_20; r = ar9300_reset(ah, opmode, chan, macmode, ap->ah_caps.halTxChainMask, ap->ah_caps.halRxChainMask, HAL_HT_EXTPROTSPACING_20, /* always 20Mhz channel spacing */ bChannelChange, status, AH_FALSE); /* XXX should really extend ath_hal_reset() */ return (r); } void ar9300_config_pcie_freebsd(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL powerOff) { ar9300_config_pci_power_save(ah, restore ? 1 : 0, powerOff ? 1 : 0); } /* * This is a copy from ar9300_eeprom_get(), purely because the FreeBSD * API is very silly and inconsistent. * * The AR93xx HAL doesn't call the eepromGetFlag() function, so this * only occurs for FreeBSD code. * * When I fix this particular API, I'll undo this. */ HAL_STATUS ar9300_eeprom_get_freebsd(struct ath_hal *ah, int param, void *val) { switch (param) { case AR_EEP_FSTCLK_5G: return HAL_OK; default: ath_hal_printf(ah, "%s: called, param=%d\n", __func__, param); return HAL_EIO; } } HAL_BOOL ar9300_stop_tx_dma_freebsd(struct ath_hal *ah, u_int q) { return ar9300_stop_tx_dma(ah, q, 1000); } void ar9300_ani_poll_freebsd(struct ath_hal *ah, const struct ieee80211_channel *chan) { HAL_NODE_STATS stats; HAL_ANISTATS anistats; HAL_SURVEY_SAMPLE survey; OS_MEMZERO(&stats, sizeof(stats)); OS_MEMZERO(&anistats, sizeof(anistats)); OS_MEMZERO(&survey, sizeof(survey)); ar9300_ani_ar_poll(ah, &stats, chan, &anistats); /* * If ANI stats are valid, use them to update the * channel survey. */ if (anistats.valid) { survey.cycle_count = anistats.cyclecnt_diff; survey.chan_busy = anistats.rxclr_cnt; survey.ext_chan_busy = anistats.extrxclr_cnt; survey.tx_busy = anistats.txframecnt_diff; survey.rx_busy = anistats.rxframecnt_diff; ath_hal_survey_add_sample(ah, &survey); } } /* * Setup the configuration parameters in the style the AR9300 HAL * wants. */ void ar9300_config_defaults_freebsd(struct ath_hal *ah, HAL_OPS_CONFIG *ah_config) { /* Until FreeBSD's HAL does this by default - just copy */ OS_MEMCPY(&ah->ah_config, ah_config, sizeof(HAL_OPS_CONFIG)); ah->ah_config.ath_hal_enable_ani = AH_TRUE; } HAL_BOOL ar9300_stop_dma_receive_freebsd(struct ath_hal *ah) { return ar9300_stop_dma_receive(ah, 1000); } HAL_BOOL ar9300_get_pending_interrupts_freebsd(struct ath_hal *ah, HAL_INT *masked) { /* Non-MSI, so no MSI vector; and 'nortc' = 0 */ return ar9300_get_pending_interrupts(ah, masked, HAL_INT_LINE, 0, 0); } HAL_INT ar9300_set_interrupts_freebsd(struct ath_hal *ah, HAL_INT ints) { /* nortc = 0 */ return ar9300_set_interrupts(ah, ints, 0); } HAL_BOOL ar9300_per_calibration_freebsd(struct ath_hal *ah, struct ieee80211_channel *chan, u_int rxchainmask, HAL_BOOL long_cal, HAL_BOOL *isCalDone) { /* XXX fake scheduled calibrations for now */ u_int32_t sched_cals = 0xfffffff; return ar9300_calibration(ah, chan, AH_PRIVATE(ah)->ah_caps.halRxChainMask, long_cal, isCalDone, 0, /* is_scan */ &sched_cals); } HAL_BOOL ar9300_reset_cal_valid_freebsd(struct ath_hal *ah, const struct ieee80211_channel *chan) { HAL_BOOL is_cal_done = AH_TRUE; ar9300_reset_cal_valid(ah, chan, &is_cal_done, 0xffffffff); return (is_cal_done); } void ar9300_start_pcu_receive_freebsd(struct ath_hal *ah) { /* is_scanning flag == NULL */ ar9300_start_pcu_receive(ah, AH_FALSE); } /* * FreeBSD will just pass in the descriptor value as 'pa'. * The Atheros HAL treats 'pa' as the physical address of the RX * descriptor and 'bufaddr' as the physical address of the RX buffer. * I'm not sure why they didn't collapse them - the AR9300 RX descriptor * routine doesn't check 'pa'. */ HAL_STATUS ar9300_proc_rx_desc_freebsd(struct ath_hal *ah, struct ath_desc *ds, uint32_t pa, struct ath_desc *ds_next, uint64_t tsf, struct ath_rx_status *rxs) { return (ar9300_proc_rx_desc_fast(ah, ds, 0, ds_next, rxs, (void *) ds)); } void ar9300_ani_rxmonitor_freebsd(struct ath_hal *ah, const HAL_NODE_STATS *stats, const struct ieee80211_channel *chan) { } void ar9300_freebsd_get_desc_link(struct ath_hal *ah, void *ds, uint32_t *link) { struct ar9300_txc *ads = AR9300TXC(ds); (*link) = ads->ds_link; } /* * TX descriptor field setting wrappers - eek. */ HAL_BOOL ar9300_freebsd_setup_tx_desc(struct ath_hal *ah, struct ath_desc *ds, u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower, u_int txRate0, u_int txTries0, u_int keyIx, u_int antMode, u_int flags, u_int rtsctsRate, u_int rtsCtsDuration, u_int compicvLen, u_int compivLen, u_int comp) { struct ath_hal_9300 *ahp = AH9300(ah); HAL_KEY_TYPE keyType = 0; /* XXX No padding */ if (keyIx != HAL_TXKEYIX_INVALID) keyType = ahp->ah_keytype[keyIx]; /* XXX bounds check keyix */ ar9300_set_11n_tx_desc(ah, ds, pktLen, type, txPower, keyIx, keyType, flags); return AH_TRUE; } HAL_BOOL ar9300_freebsd_setup_x_tx_desc(struct ath_hal *ah, struct ath_desc *ds, u_int txRate1, u_int txTries1, u_int txRate2, u_int txTries2, u_int txRate3, u_int txTries3) { #if 0 ath_hal_printf(ah, "%s: called, 0x%x/%d, 0x%x/%d, 0x%x/%d\n", __func__, txRate1, txTries1, txRate2, txTries2, txRate3, txTries3); #endif /* XXX should only be called during probe */ return (AH_TRUE); } HAL_BOOL ar9300_freebsd_fill_tx_desc(struct ath_hal *ah, struct ath_desc *ds, HAL_DMA_ADDR *bufListPtr, uint32_t *segLenPtr, u_int descId, u_int qid, HAL_BOOL firstSeg, HAL_BOOL lastSeg, const struct ath_desc *ds0) { HAL_KEY_TYPE keyType = 0; const struct ar9300_txc *ads = AR9300TXC_CONST(ds0); /* * FreeBSD's HAL doesn't pass the keytype to fill_tx_desc(); * it's copied as part of the descriptor chaining. * * So, extract it from ds0. */ keyType = MS(ads->ds_ctl17, AR_encr_type); return ar9300_fill_tx_desc(ah, ds, bufListPtr, segLenPtr, descId, qid, keyType, firstSeg, lastSeg, ds0); } HAL_BOOL ar9300_freebsd_get_tx_completion_rates(struct ath_hal *ah, const struct ath_desc *ds0, int *rates, int *tries) { ath_hal_printf(ah, "%s: called\n", __func__); return AH_FALSE; /* XXX for now */ } /* * 802.11n TX descriptor wrappers */ void ar9300_freebsd_set_11n_rate_scenario(struct ath_hal *ah, struct ath_desc *ds, u_int durUpdateEn, u_int rtsctsRate, HAL_11N_RATE_SERIES series[], u_int nseries, u_int flags) { /* lastds=NULL, rtscts_duration is 0, smart antenna is 0 */ ar9300_set_11n_rate_scenario(ah, (void *) ds, (void *)ds, durUpdateEn, rtsctsRate, 0, series, nseries, flags, 0); } /* chaintxdesc */ HAL_BOOL ar9300_freebsd_chain_tx_desc(struct ath_hal *ah, struct ath_desc *ds, HAL_DMA_ADDR *bufLenList, uint32_t *segLenList, u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int keyIx, HAL_CIPHER cipher, uint8_t numDelims, HAL_BOOL firstSeg, HAL_BOOL lastSeg, HAL_BOOL lastAggr) { ath_hal_printf(ah, "%s: called\n", __func__); return AH_FALSE; } /* setupfirsttxdesc */ HAL_BOOL ar9300_freebsd_setup_first_tx_desc(struct ath_hal *ah, struct ath_desc *ds, u_int aggrLen, u_int flags, u_int txPower, u_int txRate0, u_int txTries0, u_int antMode, u_int rtsctsRate, u_int rtsctsDuration) { ath_hal_printf(ah, "%s: called\n", __func__); return AH_FALSE; } /* setuplasttxdesc */ /* * This gets called but for now let's not log anything; * it's only used to update the rate control information. */ HAL_BOOL ar9300_freebsd_setup_last_tx_desc(struct ath_hal *ah, struct ath_desc *ds, const struct ath_desc *ds0) { // ath_hal_printf(ah, "%s: called\n", __func__); return AH_FALSE; } void ar9300_freebsd_setup_11n_desc(struct ath_hal *ah, void *ds, u_int pktLen, HAL_PKT_TYPE type, u_int txPower, u_int keyIx, u_int flags) { ath_hal_printf(ah, "%s: called\n", __func__); #if 0 struct ath_hal_9300 *ahp = AH9300(ah); HAL_KEY_TYPE keyType = 0; /* XXX No padding */ if (keyIx != HAL_TXKEYIX_INVALID) keyType = ahp->ah_keytype[keyIx]; /* XXX bounds check keyix */ ar9300_set_11n_tx_desc(ah, ds, pktLen, type, txPower, keyIx, keyType, flags); #endif } HAL_STATUS ar9300_freebsd_proc_tx_desc(struct ath_hal *ah, struct ath_desc *ds, struct ath_tx_status *ts) { return ar9300_proc_tx_desc(ah, ts); } void ar9300_freebsd_beacon_init(struct ath_hal *ah, uint32_t next_beacon, uint32_t beacon_period) { ar9300_beacon_init(ah, next_beacon, beacon_period, 0, AH_PRIVATE(ah)->ah_opmode); } HAL_BOOL ar9300_freebsd_get_mib_cycle_counts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs) { - - return (AH_FALSE); -} - -HAL_BOOL -ar9300_freebsd_get_dfs_default_thresh(struct ath_hal *ah, - HAL_PHYERR_PARAM *pe) -{ - - /* XXX not yet */ return (AH_FALSE); } /* * Clear multicast filter by index - from FreeBSD ar5212_recv.c */ static HAL_BOOL ar9300ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix) { uint32_t val; if (ix >= 64) return (AH_FALSE); if (ix >= 32) { val = OS_REG_READ(ah, AR_MCAST_FIL1); OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32)))); } else { val = OS_REG_READ(ah, AR_MCAST_FIL0); OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<= 64) return (AH_FALSE); if (ix >= 32) { val = OS_REG_READ(ah, AR_MCAST_FIL1); OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32)))); } else { val = OS_REG_READ(ah, AR_MCAST_FIL0); OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<bt_nexttbtt)); OS_REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, ONE_EIGHTH_TU_TO_USEC(bt->bt_nextdba)); OS_REG_WRITE(ah, AR_NEXT_SWBA, ONE_EIGHTH_TU_TO_USEC(bt->bt_nextswba)); OS_REG_WRITE(ah, AR_NEXT_NDP_TIMER, TU_TO_USEC(bt->bt_nextatim)); bperiod = TU_TO_USEC(bt->bt_intval & HAL_BEACON_PERIOD); AH9300(ah)->ah_beaconInterval = bt->bt_intval & HAL_BEACON_PERIOD; OS_REG_WRITE(ah, AR_BEACON_PERIOD, bperiod); OS_REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bperiod); OS_REG_WRITE(ah, AR_SWBA_PERIOD, bperiod); OS_REG_WRITE(ah, AR_NDP_PERIOD, bperiod); /* * Reset TSF if required. */ if (bt->bt_intval & HAL_BEACON_RESET_TSF) ar9300_reset_tsf(ah); /* enable timers */ /* NB: flags == 0 handled specially for backwards compatibility */ OS_REG_SET_BIT(ah, AR_TIMER_MODE, bt->bt_flags != 0 ? bt->bt_flags : AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN); } /* * RF attach stubs */ static HAL_BOOL rf9330_attach(struct ath_hal *ah, HAL_STATUS *status) { (*status) = HAL_EINVAL; return (AH_FALSE); } static HAL_BOOL rf9330_probe(struct ath_hal *ah) { return (AH_FALSE); } AH_RF(RF9330, rf9330_probe, rf9330_attach); Index: head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_radar.c =================================================================== --- head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_radar.c (revision 313090) +++ head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_radar.c (revision 313091) @@ -1,601 +1,626 @@ /* * Copyright (c) 2013 Qualcomm Atheros, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ #include "opt_ah.h" #include "ah.h" #include "ah_desc.h" #include "ah_internal.h" #include "ar9300/ar9300.h" #include "ar9300/ar9300phy.h" #include "ar9300/ar9300reg.h" /* * Default 5413/9300 radar phy parameters * Values adjusted to fix EV76432/EV76320 */ #define AR9300_DFS_FIRPWR -28 #define AR9300_DFS_RRSSI 0 #define AR9300_DFS_HEIGHT 10 #define AR9300_DFS_PRSSI 6 #define AR9300_DFS_INBAND 8 #define AR9300_DFS_RELPWR 8 #define AR9300_DFS_RELSTEP 12 #define AR9300_DFS_MAXLEN 255 /* * This PRSSI value should be used during CAC. */ #define AR9300_DFS_PRSSI_CAC 10 /* * make sure that value matches value in ar9300_osprey_2p2_mac_core[][2] * for register 0x1040 to 0x104c */ #define AR9300_DEFAULT_DIFS 0x002ffc0f #define AR9300_FCC_RADARS_FCC_OFFSET 4 struct dfs_pulse ar9300_etsi_radars[] = { /* for short pulses, RSSI threshold should be smaller than * Kquick-drop. The chip has only one chance to drop the gain which * will be reported as the estimated RSSI */ /* TYPE staggered pulse */ /* 0.8-2us, 2-3 bursts,300-400 PRF, 10 pulses each */ {30, 2, 300, 400, 2, 30, 3, 0, 5, 15, 0, 0, 1, 31}, /* Type 5*/ /* 0.8-2us, 2-3 bursts, 400-1200 PRF, 15 pulses each */ {30, 2, 400, 1200, 2, 30, 7, 0, 5, 15, 0, 0, 0, 32}, /* Type 6 */ /* constant PRF based */ /* 0.8-5us, 200 300 PRF, 10 pulses */ {10, 5, 200, 400, 0, 24, 5, 0, 8, 15, 0, 0, 2, 33}, /* Type 1 */ {10, 5, 400, 600, 0, 24, 5, 0, 8, 15, 0, 0, 2, 37}, /* Type 1 */ {10, 5, 600, 800, 0, 24, 5, 0, 8, 15, 0, 0, 2, 38}, /* Type 1 */ {10, 5, 800, 1000, 0, 24, 5, 0, 8, 15, 0, 0, 2, 39}, /* Type 1 */ // {10, 5, 200, 1000, 0, 24, 5, 0, 8, 15, 0, 0, 2, 33}, /* 0.8-15us, 200-1600 PRF, 15 pulses */ {15, 15, 200, 1600, 0, 24, 8, 0, 18, 24, 0, 0, 0, 34}, /* Type 2 */ /* 0.8-15us, 2300-4000 PRF, 25 pulses*/ {25, 15, 2300, 4000, 0, 24, 10, 0, 18, 24, 0, 0, 0, 35}, /* Type 3 */ /* 20-30us, 2000-4000 PRF, 20 pulses*/ {20, 30, 2000, 4000, 0, 24, 8, 19, 33, 24, 0, 0, 0, 36}, /* Type 4 */ }; /* The following are for FCC Bin 1-4 pulses */ struct dfs_pulse ar9300_fcc_radars[] = { /* following two filters are specific to Japan/MKK4 */ // {18, 1, 720, 720, 1, 6, 6, 0, 1, 18, 0, 3, 0, 17}, // 1389 +/- 6 us // {18, 4, 250, 250, 1, 10, 5, 1, 6, 18, 0, 3, 0, 18}, // 4000 +/- 6 us // {18, 5, 260, 260, 1, 10, 6, 1, 6, 18, 0, 3, 0, 19}, // 3846 +/- 7 us {18, 1, 720, 720, 0, 6, 6, 0, 1, 18, 0, 3, 0, 17}, // 1389 +/- 6 us {18, 4, 250, 250, 0, 10, 5, 1, 6, 18, 0, 3, 0, 18}, // 4000 +/- 6 us {18, 5, 260, 260, 0, 10, 6, 1, 6, 18, 0, 3, 1, 19}, // 3846 +/- 7 us // {18, 5, 260, 260, 1, 10, 6, 1, 6, 18, 0, 3, 1, 20}, // 3846 +/- 7 us {18, 5, 260, 260, 1, 10, 6, 1, 6, 18, 0, 3, 1, 20}, // 3846 +/- 7 us /* following filters are common to both FCC and JAPAN */ // FCC TYPE 1 // {18, 1, 325, 1930, 0, 6, 7, 0, 1, 18, 0, 3, 0, 0}, // 518 to 3066 {18, 1, 700, 700, 0, 6, 5, 0, 1, 18, 0, 3, 1, 8}, {18, 1, 350, 350, 0, 6, 5, 0, 1, 18, 0, 3, 0, 0}, // FCC TYPE 6 // {9, 1, 3003, 3003, 1, 7, 5, 0, 1, 18, 0, 0, 0, 1}, // 333 +/- 7 us //{9, 1, 3003, 3003, 1, 7, 5, 0, 1, 18, 0, 0, 0, 1}, {9, 1, 3003, 3003, 0, 7, 5, 0, 1, 18, 0, 0, 1, 1}, // FCC TYPE 2 {23, 5, 4347, 6666, 0, 18, 11, 0, 7, 22, 0, 3, 0, 2}, // FCC TYPE 3 {18, 10, 2000, 5000, 0, 23, 8, 6, 13, 22, 0, 3, 0, 5}, // FCC TYPE 4 {16, 15, 2000, 5000, 0, 25, 7, 11, 23, 22, 0, 3, 0, 11}, }; struct dfs_bin5pulse ar9300_bin5pulses[] = { {2, 28, 105, 12, 22, 5}, }; #if 0 /* * Find the internal HAL channel corresponding to the * public HAL channel specified in c */ static HAL_CHANNEL_INTERNAL * getchannel(struct ath_hal *ah, const struct ieee80211_channel *c) { #define CHAN_FLAGS (CHANNEL_ALL | CHANNEL_HALF | CHANNEL_QUARTER) HAL_CHANNEL_INTERNAL *base, *cc; int flags = c->channel_flags & CHAN_FLAGS; int n, lim; /* * Check current channel to avoid the lookup. */ cc = AH_PRIVATE(ah)->ah_curchan; if (cc != AH_NULL && cc->channel == c->channel && (cc->channel_flags & CHAN_FLAGS) == flags) { return cc; } /* binary search based on known sorting order */ base = AH_TABLES(ah)->ah_channels; n = AH_PRIVATE(ah)->ah_nchan; /* binary search based on known sorting order */ for (lim = n; lim != 0; lim >>= 1) { int d; cc = &base[lim >> 1]; d = c->channel - cc->channel; if (d == 0) { if ((cc->channel_flags & CHAN_FLAGS) == flags) { return cc; } d = flags - (cc->channel_flags & CHAN_FLAGS); } HALDEBUG(ah, HAL_DEBUG_DFS, "%s: channel %u/0x%x d %d\n", __func__, cc->channel, cc->channel_flags, d); if (d > 0) { base = cc + 1; lim--; } } HALDEBUG(ah, HAL_DEBUG_DFS, "%s: no match for %u/0x%x\n", __func__, c->channel, c->channel_flags); return AH_NULL; #undef CHAN_FLAGS } /* * Check the internal channel list to see if the desired channel * is ok to release from the NOL. If not, then do nothing. If so, * mark the channel as clear and reset the internal tsf time */ void ar9300_check_dfs(struct ath_hal *ah, struct ieee80211_channel *chan) { HAL_CHANNEL_INTERNAL *ichan = AH_NULL; ichan = getchannel(ah, chan); if (ichan == AH_NULL) { return; } if (!(ichan->priv_flags & CHANNEL_INTERFERENCE)) { return; } ichan->priv_flags &= ~CHANNEL_INTERFERENCE; ichan->dfs_tsf = 0; } /* * This function marks the channel as having found a dfs event * It also marks the end time that the dfs event should be cleared * If the channel is already marked, then tsf end time can only * be increased */ void ar9300_dfs_found(struct ath_hal *ah, struct ieee80211_channel *chan, u_int64_t nol_time) { HAL_CHANNEL_INTERNAL *ichan; ichan = getchannel(ah, chan); if (ichan == AH_NULL) { return; } if (!(ichan->priv_flags & CHANNEL_INTERFERENCE)) { ichan->dfs_tsf = ar9300_get_tsf64(ah); } ichan->dfs_tsf += nol_time; ichan->priv_flags |= CHANNEL_INTERFERENCE; chan->priv_flags |= CHANNEL_INTERFERENCE; } #endif /* * Enable radar detection and set the radar parameters per the * values in pe */ void ar9300_enable_dfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe) { u_int32_t val; struct ath_hal_private *ahp = AH_PRIVATE(ah); const struct ieee80211_channel *chan = ahp->ah_curchan; struct ath_hal_9300 *ah9300 = AH9300(ah); int reg_writes = 0; val = OS_REG_READ(ah, AR_PHY_RADAR_0); - val |= AR_PHY_RADAR_0_FFT_ENA | AR_PHY_RADAR_0_ENA; + val |= AR_PHY_RADAR_0_FFT_ENA; + + + if (pe->pe_enabled != HAL_PHYERR_PARAM_NOVAL) { + val &= ~AR_PHY_RADAR_0_ENA; + val |= SM(pe->pe_enabled, AR_PHY_RADAR_0_ENA); + } + if (pe->pe_firpwr != HAL_PHYERR_PARAM_NOVAL) { val &= ~AR_PHY_RADAR_0_FIRPWR; val |= SM(pe->pe_firpwr, AR_PHY_RADAR_0_FIRPWR); } if (pe->pe_rrssi != HAL_PHYERR_PARAM_NOVAL) { val &= ~AR_PHY_RADAR_0_RRSSI; val |= SM(pe->pe_rrssi, AR_PHY_RADAR_0_RRSSI); } if (pe->pe_height != HAL_PHYERR_PARAM_NOVAL) { val &= ~AR_PHY_RADAR_0_HEIGHT; val |= SM(pe->pe_height, AR_PHY_RADAR_0_HEIGHT); } if (pe->pe_prssi != HAL_PHYERR_PARAM_NOVAL) { val &= ~AR_PHY_RADAR_0_PRSSI; if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { #if 0 if (ah->ah_use_cac_prssi) { val |= SM(AR9300_DFS_PRSSI_CAC, AR_PHY_RADAR_0_PRSSI); } else { #endif val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI); // } } else { val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI); } } if (pe->pe_inband != HAL_PHYERR_PARAM_NOVAL) { val &= ~AR_PHY_RADAR_0_INBAND; val |= SM(pe->pe_inband, AR_PHY_RADAR_0_INBAND); } OS_REG_WRITE(ah, AR_PHY_RADAR_0, val); val = OS_REG_READ(ah, AR_PHY_RADAR_1); val |= AR_PHY_RADAR_1_MAX_RRSSI | AR_PHY_RADAR_1_BLOCK_CHECK; if (pe->pe_maxlen != HAL_PHYERR_PARAM_NOVAL) { val &= ~AR_PHY_RADAR_1_MAXLEN; val |= SM(pe->pe_maxlen, AR_PHY_RADAR_1_MAXLEN); } if (pe->pe_relstep != HAL_PHYERR_PARAM_NOVAL) { val &= ~AR_PHY_RADAR_1_RELSTEP_THRESH; val |= SM(pe->pe_relstep, AR_PHY_RADAR_1_RELSTEP_THRESH); } if (pe->pe_relpwr != HAL_PHYERR_PARAM_NOVAL) { val &= ~AR_PHY_RADAR_1_RELPWR_THRESH; val |= SM(pe->pe_relpwr, AR_PHY_RADAR_1_RELPWR_THRESH); } OS_REG_WRITE(ah, AR_PHY_RADAR_1, val); if (ath_hal_getcapability(ah, HAL_CAP_EXT_CHAN_DFS, 0, 0) == HAL_OK) { val = OS_REG_READ(ah, AR_PHY_RADAR_EXT); if (IEEE80211_IS_CHAN_HT40(chan)) { /* Enable extension channel radar detection */ OS_REG_WRITE(ah, AR_PHY_RADAR_EXT, val | AR_PHY_RADAR_EXT_ENA); } else { /* HT20 mode, disable extension channel radar detect */ OS_REG_WRITE(ah, AR_PHY_RADAR_EXT, val & ~AR_PHY_RADAR_EXT_ENA); } } /* apply DFS postamble array from INI column 0 is register ID, column 1 is HT20 value, colum2 is HT40 value */ if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_OSPREY_22(ah) || AR_SREV_SCORPION(ah)) { REG_WRITE_ARRAY(&ah9300->ah_ini_dfs, IEEE80211_IS_CHAN_HT40(chan)? 2:1, reg_writes); } #ifdef ATH_HAL_DFS_CHIRPING_FIX_APH128 ath_hal_printf(ah, "DFS change the timing value\n"); if (AR_SREV_AR9580(ah) && IEEE80211_IS_CHAN_HT40(chan)) { OS_REG_WRITE(ah, AR_PHY_TIMING6, 0x3140c00a); } #endif } /* * Get the radar parameter values and return them in the pe * structure */ void ar9300_get_dfs_thresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe) { u_int32_t val, temp; val = OS_REG_READ(ah, AR_PHY_RADAR_0); temp = MS(val, AR_PHY_RADAR_0_FIRPWR); temp |= ~(AR_PHY_RADAR_0_FIRPWR >> AR_PHY_RADAR_0_FIRPWR_S); pe->pe_firpwr = temp; pe->pe_rrssi = MS(val, AR_PHY_RADAR_0_RRSSI); pe->pe_height = MS(val, AR_PHY_RADAR_0_HEIGHT); pe->pe_prssi = MS(val, AR_PHY_RADAR_0_PRSSI); pe->pe_inband = MS(val, AR_PHY_RADAR_0_INBAND); + pe->pe_enabled = !! MS(val, AR_PHY_RADAR_0_ENA); val = OS_REG_READ(ah, AR_PHY_RADAR_1); pe->pe_relpwr = MS(val, AR_PHY_RADAR_1_RELPWR_THRESH); pe->pe_enrelpwr = !! (val & AR_PHY_RADAR_1_RELPWR_ENA); pe->pe_relstep = MS(val, AR_PHY_RADAR_1_RELSTEP_THRESH); pe->pe_en_relstep_check = !! (val & AR_PHY_RADAR_1_RELSTEP_CHECK); pe->pe_maxlen = MS(val, AR_PHY_RADAR_1_MAXLEN); } #if 0 HAL_BOOL ar9300_radar_wait(struct ath_hal *ah, struct ieee80211_channel *chan) { struct ath_hal_private *ahp = AH_PRIVATE(ah); if (!ahp->ah_curchan) { return AH_TRUE; } /* * Rely on the upper layers to determine that we have spent * enough time waiting. */ chan->channel = ahp->ah_curchan->channel; chan->channel_flags = ahp->ah_curchan->channel_flags; chan->max_reg_tx_power = ahp->ah_curchan->max_reg_tx_power; ahp->ah_curchan->priv_flags |= CHANNEL_DFS_CLEAR; chan->priv_flags = ahp->ah_curchan->priv_flags; return AH_FALSE; } #endif struct dfs_pulse * ar9300_get_dfs_radars( struct ath_hal *ah, u_int32_t dfsdomain, int *numradars, struct dfs_bin5pulse **bin5pulses, int *numb5radars, HAL_PHYERR_PARAM *pe) { struct dfs_pulse *dfs_radars = AH_NULL; switch (dfsdomain) { case HAL_DFS_FCC_DOMAIN: dfs_radars = &ar9300_fcc_radars[AR9300_FCC_RADARS_FCC_OFFSET]; *numradars = ARRAY_LENGTH(ar9300_fcc_radars) - AR9300_FCC_RADARS_FCC_OFFSET; *bin5pulses = &ar9300_bin5pulses[0]; *numb5radars = ARRAY_LENGTH(ar9300_bin5pulses); HALDEBUG(ah, HAL_DEBUG_DFS, "%s: DFS_FCC_DOMAIN_9300\n", __func__); break; case HAL_DFS_ETSI_DOMAIN: dfs_radars = &ar9300_etsi_radars[0]; *numradars = ARRAY_LENGTH(ar9300_etsi_radars); *bin5pulses = &ar9300_bin5pulses[0]; *numb5radars = ARRAY_LENGTH(ar9300_bin5pulses); HALDEBUG(ah, HAL_DEBUG_DFS, "%s: DFS_ETSI_DOMAIN_9300\n", __func__); break; case HAL_DFS_MKK4_DOMAIN: dfs_radars = &ar9300_fcc_radars[0]; *numradars = ARRAY_LENGTH(ar9300_fcc_radars); *bin5pulses = &ar9300_bin5pulses[0]; *numb5radars = ARRAY_LENGTH(ar9300_bin5pulses); HALDEBUG(ah, HAL_DEBUG_DFS, "%s: DFS_MKK4_DOMAIN_9300\n", __func__); break; default: HALDEBUG(ah, HAL_DEBUG_DFS, "%s: no domain\n", __func__); return AH_NULL; } /* Set the default phy parameters per chip */ pe->pe_firpwr = AR9300_DFS_FIRPWR; pe->pe_rrssi = AR9300_DFS_RRSSI; pe->pe_height = AR9300_DFS_HEIGHT; pe->pe_prssi = AR9300_DFS_PRSSI; /* we have an issue with PRSSI. For normal operation we use AR9300_DFS_PRSSI, which is set to 6. Please refer to EV91563, 94164. However, this causes problem during CAC as no radar is detected during that period with PRSSI=6. Only PRSSI= 10 seems to fix this. We use this flag to keep track of change in PRSSI. */ // ah->ah_use_cac_prssi = 0; pe->pe_inband = AR9300_DFS_INBAND; pe->pe_relpwr = AR9300_DFS_RELPWR; pe->pe_relstep = AR9300_DFS_RELSTEP; pe->pe_maxlen = AR9300_DFS_MAXLEN; return dfs_radars; +} + +HAL_BOOL +ar9300_get_default_dfs_thresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe) +{ + + pe->pe_firpwr = AR9300_DFS_FIRPWR; + pe->pe_rrssi = AR9300_DFS_RRSSI; + pe->pe_height = AR9300_DFS_HEIGHT; + pe->pe_prssi = AR9300_DFS_PRSSI; + /* see prssi comment above */ + + pe->pe_inband = AR9300_DFS_INBAND; + pe->pe_relpwr = AR9300_DFS_RELPWR; + pe->pe_relstep = AR9300_DFS_RELSTEP; + pe->pe_maxlen = AR9300_DFS_MAXLEN; + return (AH_TRUE); } void ar9300_adjust_difs(struct ath_hal *ah, u_int32_t val) { if (val == 0) { /* * EV 116936: * Restore the register values with that of the HAL structure. * Do not assume and overwrite these values to whatever * is in ar9300_osprey22.ini. */ struct ath_hal_9300 *ahp = AH9300(ah); HAL_TX_QUEUE_INFO *qi; int q; AH9300(ah)->ah_fccaifs = 0; HALDEBUG(ah, HAL_DEBUG_DFS, "%s: restore DIFS \n", __func__); for (q = 0; q < 4; q++) { qi = &ahp->ah_txq[q]; OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(qi->tqi_cwmin, AR_D_LCL_IFS_CWMIN) | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); } } else { /* * These are values from George Lai and are specific to * FCC domain. They are yet to be determined for other domains. */ AH9300(ah)->ah_fccaifs = 1; HALDEBUG(ah, HAL_DEBUG_DFS, "%s: set DIFS to default\n", __func__); /*printk("%s: modify DIFS\n", __func__);*/ OS_REG_WRITE(ah, AR_DLCL_IFS(0), 0x05fffc0f); OS_REG_WRITE(ah, AR_DLCL_IFS(1), 0x05f0fc0f); OS_REG_WRITE(ah, AR_DLCL_IFS(2), 0x05f03c07); OS_REG_WRITE(ah, AR_DLCL_IFS(3), 0x05f01c03); } } u_int32_t ar9300_dfs_config_fft(struct ath_hal *ah, HAL_BOOL is_enable) { u_int32_t val; val = OS_REG_READ(ah, AR_PHY_RADAR_0); if (is_enable) { val |= AR_PHY_RADAR_0_FFT_ENA; } else { val &= ~AR_PHY_RADAR_0_FFT_ENA; } OS_REG_WRITE(ah, AR_PHY_RADAR_0, val); val = OS_REG_READ(ah, AR_PHY_RADAR_0); return val; } /* function to adjust PRSSI value for CAC problem */ void ar9300_dfs_cac_war(struct ath_hal *ah, u_int32_t start) { u_int32_t val; if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { val = OS_REG_READ(ah, AR_PHY_RADAR_0); if (start) { val &= ~AR_PHY_RADAR_0_PRSSI; val |= SM(AR9300_DFS_PRSSI_CAC, AR_PHY_RADAR_0_PRSSI); } else { val &= ~AR_PHY_RADAR_0_PRSSI; val |= SM(AR9300_DFS_PRSSI, AR_PHY_RADAR_0_PRSSI); } OS_REG_WRITE(ah, AR_PHY_RADAR_0, val | AR_PHY_RADAR_0_ENA); // ah->ah_use_cac_prssi = start; } } #if 0 struct ieee80211_channel * ar9300_get_extension_channel(struct ath_hal *ah) { struct ath_hal_private *ahp = AH_PRIVATE(ah); struct ath_hal_private_tables *aht = AH_TABLES(ah); int i = 0; HAL_CHANNEL_INTERNAL *ichan = AH_NULL; CHAN_CENTERS centers; ichan = ahp->ah_curchan; ar9300_get_channel_centers(ah, ichan, ¢ers); if (centers.ctl_center == centers.ext_center) { return AH_NULL; } for (i = 0; i < ahp->ah_nchan; i++) { ichan = &aht->ah_channels[i]; if (ichan->channel == centers.ext_center) { return (struct ieee80211_channel*)ichan; } } return AH_NULL; } #endif HAL_BOOL ar9300_is_fast_clock_enabled(struct ath_hal *ah) { struct ath_hal_private *ahp = AH_PRIVATE(ah); if (IS_5GHZ_FAST_CLOCK_EN(ah, ahp->ah_curchan)) { return AH_TRUE; } return AH_FALSE; } /* * This should be enabled and linked into the build once * radar support is enabled. */ #if 0 HAL_BOOL ar9300_handle_radar_bb_panic(struct ath_hal *ah) { u_int32_t status; u_int32_t val; #ifdef AH_DEBUG struct ath_hal_9300 *ahp = AH9300(ah); #endif status = AH_PRIVATE(ah)->ah_bb_panic_last_status; if ( status == 0x04000539 ) { /* recover from this BB panic without reset*/ /* set AR9300_DFS_FIRPWR to -1 */ val = OS_REG_READ(ah, AR_PHY_RADAR_0); val &= (~AR_PHY_RADAR_0_FIRPWR); val |= SM( 0x7f, AR_PHY_RADAR_0_FIRPWR); OS_REG_WRITE(ah, AR_PHY_RADAR_0, val); OS_DELAY(1); /* set AR9300_DFS_FIRPWR to its default value */ val = OS_REG_READ(ah, AR_PHY_RADAR_0); val &= ~AR_PHY_RADAR_0_FIRPWR; val |= SM( AR9300_DFS_FIRPWR, AR_PHY_RADAR_0_FIRPWR); OS_REG_WRITE(ah, AR_PHY_RADAR_0, val); return AH_TRUE; } else if (status == 0x0400000a) { /* EV 92527 : reset required if we see this signature */ HALDEBUG(ah, HAL_DEBUG_DFS, "%s: BB Panic -- 0x0400000a\n", __func__); return AH_FALSE; } else if (status == 0x1300000a) { /* EV92527: we do not need a reset if we see this signature */ HALDEBUG(ah, HAL_DEBUG_DFS, "%s: BB Panic -- 0x1300000a\n", __func__); return AH_TRUE; } else if ((AR_SREV_WASP(ah) || AR_SREV_HONEYBEE(ah)) && (status == 0x04000409)) { return AH_TRUE; } else { if (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK && (status & 0xff00000f) == 0x04000009 && status != 0x04000409 && status != 0x04000b09 && status != 0x04000e09 && (status & 0x0000ff00)) { /* disable RIFS Rx */ #ifdef AH_DEBUG HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: BB status=0x%08x rifs=%d - disable\n", __func__, status, ahp->ah_rifs_enabled); ar9300_set_rifs_delay(ah, AH_FALSE); } return AH_FALSE; } } #endif #endif Index: head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300phy.h =================================================================== --- head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300phy.h (revision 313090) +++ head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300phy.h (revision 313091) @@ -1,1961 +1,1962 @@ /* * Copyright (c) 2013 Qualcomm Atheros, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ /* * Copyright (c) 2002-2005 Atheros Communications, Inc. * All Rights Reserved. * * Copyright (c) 2011 Qualcomm Atheros, Inc. * All Rights Reserved. * Qualcomm Atheros Confidential and Proprietary. * */ #ifndef _ATH_AR9300PHY_H_ #define _ATH_AR9300PHY_H_ #include "osprey_reg_map.h" /* * BB PHY register map */ #define AR_PHY_BASE offsetof(struct bb_reg_map, bb_chn_reg_map) /* base address of phy regs */ #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) /* * Channel Register Map */ #define AR_CHAN_BASE offsetof(struct bb_reg_map, bb_chn_reg_map) #define AR_CHAN_OFFSET(_x) (AR_CHAN_BASE + offsetof(struct chn_reg_map, _x)) #define AR_PHY_TIMING1 AR_CHAN_OFFSET(BB_timing_controls_1) #define AR_PHY_TIMING2 AR_CHAN_OFFSET(BB_timing_controls_2) #define AR_PHY_TIMING3 AR_CHAN_OFFSET(BB_timing_controls_3) #define AR_PHY_TIMING4 AR_CHAN_OFFSET(BB_timing_control_4) #define AR_PHY_TIMING5 AR_CHAN_OFFSET(BB_timing_control_5) #define AR_PHY_TIMING6 AR_CHAN_OFFSET(BB_timing_control_6) #define AR_PHY_TIMING11 AR_CHAN_OFFSET(BB_timing_control_11) #define AR_PHY_SPUR_REG AR_CHAN_OFFSET(BB_spur_mask_controls) #define AR_PHY_RX_IQCAL_CORR_B0 AR_CHAN_OFFSET(BB_rx_iq_corr_b0) #define AR_PHY_TX_IQCAL_CONTROL_3 AR_CHAN_OFFSET(BB_txiqcal_control_3) /* BB_timing_control_11 */ #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000 #define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC_S 30 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR_S 31 /* BB_spur_mask_controls */ #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT_S 26 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */ #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM_S 17 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI_S 8 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL 0x03FC0000 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 /* BB_rx_iq_corr_b0 */ #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN 0x20000000 #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S 29 /* BB_txiqcal_control_3 */ #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN 0x80000000 #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S 31 #if 0 /* enable vit puncture per rate, 8 bits, lsb is low rate */ #define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18) #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */ #define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9) /* use mask1 or mask2, one per rate */ #define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9 #define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 #endif #define AR_PHY_FIND_SIG_LOW AR_CHAN_OFFSET(BB_find_signal_low) #define AR_PHY_SFCORR AR_CHAN_OFFSET(BB_sfcorr) #if 0 #define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F #define AR_PHY_SFCORR_M2COUNT_THR_S 0 #define AR_PHY_SFCORR_M1_THRESH 0x00FE0000 #define AR_PHY_SFCORR_M1_THRESH_S 17 #define AR_PHY_SFCORR_M2_THRESH 0x7F000000 #define AR_PHY_SFCORR_M2_THRESH_S 24 #endif #define AR_PHY_SFCORR_LOW AR_CHAN_OFFSET(BB_self_corr_low) #define AR_PHY_SFCORR_EXT AR_CHAN_OFFSET(BB_ext_chan_scorr_thr) #if 0 #define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F // [06:00] #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 #define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80 // [13:07] #define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000 // [20:14] #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000 // [27:21] #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 #endif #define AR_PHY_EXT_CCA AR_CHAN_OFFSET(BB_ext_chan_pwr_thr_2_b0) #define AR_PHY_RADAR_0 AR_CHAN_OFFSET(BB_radar_detection) /* radar detection settings */ #define AR_PHY_RADAR_1 AR_CHAN_OFFSET(BB_radar_detection_2) #define AR_PHY_RADAR_1_CF_BIN_THRESH 0x07000000 #define AR_PHY_RADAR_1_CF_BIN_THRESH_S 24 #define AR_PHY_RADAR_EXT AR_CHAN_OFFSET(BB_extension_radar) /* extension channel radar settings */ #define AR_PHY_MULTICHAIN_CTRL AR_CHAN_OFFSET(BB_multichain_control) #define AR_PHY_PERCHAIN_CSD AR_CHAN_OFFSET(BB_per_chain_csd) #define AR_PHY_TX_PHASE_RAMP_0 AR_CHAN_OFFSET(BB_tx_phase_ramp_b0) #define AR_PHY_ADC_GAIN_DC_CORR_0 AR_CHAN_OFFSET(BB_adc_gain_dc_corr_b0) #define AR_PHY_IQ_ADC_MEAS_0_B0 AR_CHAN_OFFSET(BB_iq_adc_meas_0_b0) #define AR_PHY_IQ_ADC_MEAS_1_B0 AR_CHAN_OFFSET(BB_iq_adc_meas_1_b0) #define AR_PHY_IQ_ADC_MEAS_2_B0 AR_CHAN_OFFSET(BB_iq_adc_meas_2_b0) #define AR_PHY_IQ_ADC_MEAS_3_B0 AR_CHAN_OFFSET(BB_iq_adc_meas_3_b0) #define AR_PHY_TX_IQ_CORR_0 AR_CHAN_OFFSET(BB_tx_iq_corr_b0) #define AR_PHY_TX_CRC AR_CHAN_OFFSET(BB_tx_crc) #define AR_PHY_TST_DAC_CONST AR_CHAN_OFFSET(BB_tstdac_constant) #define AR_PHY_SPUR_REPORT_0 AR_CHAN_OFFSET(BB_spur_report_b0) #define AR_PHY_CHAN_INFO_TAB_0 AR_CHAN_OFFSET(BB_chan_info_chan_tab_b0) /* * Channel Field Definitions */ /* BB_timing_controls_2 */ #define AR_PHY_TIMING2_USE_FORCE_PPM 0x00001000 #define AR_PHY_TIMING2_FORCE_PPM_VAL 0x00000fff #define AR_PHY_TIMING2_HT_Fine_Timing_EN 0x80000000 #define AR_PHY_TIMING2_DC_OFFSET 0x08000000 #define AR_PHY_TIMING2_DC_OFFSET_S 27 /* BB_timing_controls_3 */ #define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000 #define AR_PHY_TIMING3_DSC_MAN_S 17 #define AR_PHY_TIMING3_DSC_EXP 0x0001E000 #define AR_PHY_TIMING3_DSC_EXP_S 13 /* BB_timing_control_4 */ #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX 0xF000 /* Mask for max number of samples (logarithmic) */ #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S 12 /* Shift for max number of samples */ #define AR_PHY_TIMING4_DO_CAL 0x10000 /* perform calibration */ #define AR_PHY_TIMING4_ENABLE_PILOT_MASK 0x10000000 #define AR_PHY_TIMING4_ENABLE_PILOT_MASK_S 28 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK 0x20000000 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK_S 29 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER_S 30 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI_S 31 /* BB_adc_gain_dc_corr_b0 */ #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000 #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000 /* BB_self_corr_low */ #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21 /* BB_sfcorr */ #define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F #define AR_PHY_SFCORR_M2COUNT_THR_S 0 #define AR_PHY_SFCORR_M1_THRESH 0x00FE0000 #define AR_PHY_SFCORR_M1_THRESH_S 17 #define AR_PHY_SFCORR_M2_THRESH 0x7F000000 #define AR_PHY_SFCORR_M2_THRESH_S 24 /* BB_ext_chan_scorr_thr */ #define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F // [06:00] #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 #define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80 // [13:07] #define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000 // [20:14] #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000 // [27:21] #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD_S 28 #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 /* BB_ext_chan_pwr_thr_2_b0 */ #define AR_PHY_EXT_CCA_THRESH62 0x007F0000 #define AR_PHY_EXT_CCA_THRESH62_S 16 #define AR_PHY_EXT_MINCCA_PWR 0x01FF0000 #define AR_PHY_EXT_MINCCA_PWR_S 16 #define AR_PHY_EXT_CYCPWR_THR1 0x0000FE00L // [15:09] #define AR_PHY_EXT_CYCPWR_THR1_S 9 /* BB_timing_control_5 */ #define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE #define AR_PHY_TIMING5_CYCPWR_THR1_S 1 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S 0 #define AR_PHY_TIMING5_CYCPWR_THR1A 0x007F0000 #define AR_PHY_TIMING5_CYCPWR_THR1A_S 16 #define AR_PHY_TIMING5_RSSI_THR1A (0x7F << 16) #define AR_PHY_TIMING5_RSSI_THR1A_S 16 #define AR_PHY_TIMING5_RSSI_THR1A_ENA (0x1 << 15) /* BB_radar_detection) */ #define AR_PHY_RADAR_0_ENA 0x00000001 /* Enable radar detection */ +#define AR_PHY_RADAR_0_ENA_S 0 #define AR_PHY_RADAR_0_FFT_ENA 0x80000000 /* Enable FFT data */ #define AR_PHY_RADAR_0_INBAND 0x0000003e /* Inband pulse threshold */ #define AR_PHY_RADAR_0_INBAND_S 1 #define AR_PHY_RADAR_0_PRSSI 0x00000FC0 /* Pulse rssi threshold */ #define AR_PHY_RADAR_0_PRSSI_S 6 #define AR_PHY_RADAR_0_HEIGHT 0x0003F000 /* Pulse height threshold */ #define AR_PHY_RADAR_0_HEIGHT_S 12 #define AR_PHY_RADAR_0_RRSSI 0x00FC0000 /* Radar rssi threshold */ #define AR_PHY_RADAR_0_RRSSI_S 18 #define AR_PHY_RADAR_0_FIRPWR 0x7F000000 /* Radar firpwr threshold */ #define AR_PHY_RADAR_0_FIRPWR_S 24 /* BB_radar_detection_2 */ #define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 /* enable to check radar relative power */ #define AR_PHY_RADAR_1_USE_FIR128 0x00400000 /* enable to use the average inband power * measured over 128 cycles */ #define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000 /* relative pwr thresh */ #define AR_PHY_RADAR_1_RELPWR_THRESH_S 16 #define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 /* Enable to block radar check if weak OFDM * sig or pkt is immediately after tx to rx * transition */ #define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 /* Enable to use max rssi */ #define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 /* Enable to use pulse relative step check */ #define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00 /* Pulse relative step threshold */ #define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8 #define AR_PHY_RADAR_1_MAXLEN 0x000000FF /* Max length of radar pulse */ #define AR_PHY_RADAR_1_MAXLEN_S 0 /* BB_extension_radar */ #define AR_PHY_RADAR_EXT_ENA 0x00004000 /* Enable extension channel radar detection */ #define AR_PHY_RADAR_DC_PWR_THRESH 0x007f8000 #define AR_PHY_RADAR_DC_PWR_THRESH_S 15 #define AR_PHY_RADAR_LB_DC_CAP 0x7f800000 #define AR_PHY_RADAR_LB_DC_CAP_S 23 /* per chain csd*/ #define AR_PHY_PERCHAIN_CSD_chn1_2chains 0x0000001f #define AR_PHY_PERCHAIN_CSD_chn1_2chains_S 0 #define AR_PHY_PERCHAIN_CSD_chn1_3chains 0x000003e0 #define AR_PHY_PERCHAIN_CSD_chn1_3chains_S 5 #define AR_PHY_PERCHAIN_CSD_chn2_3chains 0x00007c00 #define AR_PHY_PERCHAIN_CSD_chn2_3chains_S 10 /* BB_find_signal_low */ #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW (0x3f << 6) #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S 6 #define AR_PHY_FIND_SIG_LOW_FIRPWR (0x7f << 12) #define AR_PHY_FIND_SIG_LOW_FIRPWR_S 12 #define AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT 19 #define AR_PHY_FIND_SIG_LOW_RELSTEP 0x1f #define AR_PHY_FIND_SIG_LOW_RELSTEP_S 0 #define AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT 5 /* BB_chan_info_chan_tab_b* */ #define AR_PHY_CHAN_INFO_TAB_S2_READ 0x00000008 #define AR_PHY_CHAN_INFO_TAB_S2_READ_S 3 /* BB_rx_iq_corr_b* */ #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF 0x0000007F /* Mask for kcos_theta-1 for q correction */ #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S 0 /* shift for Q_COFF */ #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF 0x00003F80 /* Mask for sin_theta for i correction */ #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S 7 /* Shift for sin_theta for i correction */ #define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE 0x00004000 /* enable IQ correction */ #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF 0x003f8000 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S 15 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF 0x1fc00000 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S 22 /* * MRC Register Map */ #define AR_MRC_BASE offsetof(struct bb_reg_map, bb_mrc_reg_map) #define AR_MRC_OFFSET(_x) (AR_MRC_BASE + offsetof(struct mrc_reg_map, _x)) #define AR_PHY_TIMING_3A AR_MRC_OFFSET(BB_timing_control_3a) #define AR_PHY_LDPC_CNTL1 AR_MRC_OFFSET(BB_ldpc_cntl1) #define AR_PHY_LDPC_CNTL2 AR_MRC_OFFSET(BB_ldpc_cntl2) #define AR_PHY_PILOT_SPUR_MASK AR_MRC_OFFSET(BB_pilot_spur_mask) #define AR_PHY_CHAN_SPUR_MASK AR_MRC_OFFSET(BB_chan_spur_mask) #define AR_PHY_SGI_DELTA AR_MRC_OFFSET(BB_short_gi_delta_slope) #define AR_PHY_ML_CNTL_1 AR_MRC_OFFSET(BB_ml_cntl1) #define AR_PHY_ML_CNTL_2 AR_MRC_OFFSET(BB_ml_cntl2) #define AR_PHY_TST_ADC AR_MRC_OFFSET(BB_tstadc) /* BB_pilot_spur_mask fields */ #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A 0x00000FE0 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S 5 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A 0x1F #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S 0 /* BB_chan_spur_mask fields */ #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A 0x00000FE0 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S 5 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A 0x1F #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S 0 /* * MRC Feild Definitions */ #define AR_PHY_SGI_DSC_MAN 0x0007FFF0 #define AR_PHY_SGI_DSC_MAN_S 4 #define AR_PHY_SGI_DSC_EXP 0x0000000F #define AR_PHY_SGI_DSC_EXP_S 0 /* * BBB Register Map */ #define AR_BBB_BASE offsetof(struct bb_reg_map, bb_bbb_reg_map) #define AR_BBB_OFFSET(_x) (AR_BBB_BASE + offsetof(struct bbb_reg_map, _x)) #define AR_PHY_BBB_RX_CTRL(_i) AR_BBB_OFFSET(BB_bbb_rx_ctrl_##_i) /* * AGC Register Map */ #define AR_AGC_BASE offsetof(struct bb_reg_map, bb_agc_reg_map) #define AR_AGC_OFFSET(_x) (AR_AGC_BASE + offsetof(struct agc_reg_map, _x)) #define AR_PHY_SETTLING AR_AGC_OFFSET(BB_settling_time) #define AR_PHY_FORCEMAX_GAINS_0 AR_AGC_OFFSET(BB_gain_force_max_gains_b0) #define AR_PHY_GAINS_MINOFF0 AR_AGC_OFFSET(BB_gains_min_offsets_b0) #define AR_PHY_DESIRED_SZ AR_AGC_OFFSET(BB_desired_sigsize) #define AR_PHY_FIND_SIG AR_AGC_OFFSET(BB_find_signal) #define AR_PHY_AGC AR_AGC_OFFSET(BB_agc) #define AR_PHY_EXT_ATTEN_CTL_0 AR_AGC_OFFSET(BB_ext_atten_switch_ctl_b0) #define AR_PHY_CCA_0 AR_AGC_OFFSET(BB_cca_b0) #define AR_PHY_EXT_CCA0 AR_AGC_OFFSET(BB_cca_ctrl_2_b0) #define AR_PHY_RESTART AR_AGC_OFFSET(BB_restart) #define AR_PHY_MC_GAIN_CTRL AR_AGC_OFFSET(BB_multichain_gain_ctrl) #define AR_PHY_EXTCHN_PWRTHR1 AR_AGC_OFFSET(BB_ext_chan_pwr_thr_1) #define AR_PHY_EXT_CHN_WIN AR_AGC_OFFSET(BB_ext_chan_detect_win) #define AR_PHY_20_40_DET_THR AR_AGC_OFFSET(BB_pwr_thr_20_40_det) #define AR_PHY_RIFS_SRCH AR_AGC_OFFSET(BB_rifs_srch) #define AR_PHY_PEAK_DET_CTRL_1 AR_AGC_OFFSET(BB_peak_det_ctrl_1) #define AR_PHY_PEAK_DET_ENABLE 0x00000002 #define AR_PHY_PEAK_DET_CTRL_2 AR_AGC_OFFSET(BB_peak_det_ctrl_2) #define AR_PHY_RX_GAIN_BOUNDS_1 AR_AGC_OFFSET(BB_rx_gain_bounds_1) #define AR_PHY_RX_GAIN_BOUNDS_2 AR_AGC_OFFSET(BB_rx_gain_bounds_2) #define AR_PHY_RSSI_0 AR_AGC_OFFSET(BB_rssi_b0) #define AR_PHY_SPUR_CCK_REP0 AR_AGC_OFFSET(BB_spur_est_cck_report_b0) #define AR_PHY_CCK_DETECT AR_AGC_OFFSET(BB_bbb_sig_detect) #define AR_PHY_DAG_CTRLCCK AR_AGC_OFFSET(BB_bbb_dagc_ctrl) #define AR_PHY_IQCORR_CTRL_CCK AR_AGC_OFFSET(BB_iqcorr_ctrl_cck) #define AR_PHY_DIG_DC_STATUS_I_B0 AR_AGC_OFFSET(BB_agc_dig_dc_status_i_b0) #define AR_PHY_DIG_DC_STATUS_Q_B0 AR_AGC_OFFSET(BB_agc_dig_dc_status_q_b0) #define AR_PHY_DIG_DC_C1_RES 0x000001ff #define AR_PHY_DIG_DC_C1_RES_S 0 #define AR_PHY_DIG_DC_C2_RES 0x0003fe00 #define AR_PHY_DIG_DC_C2_RES_S 9 #define AR_PHY_DIG_DC_C3_RES 0x07fc0000 #define AR_PHY_DIG_DC_C3_RES_S 18 #define AR_PHY_CCK_SPUR_MIT AR_AGC_OFFSET(BB_cck_spur_mit) #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR 0x000001fe #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S 1 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE 0x60000000 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S 29 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT 0x00000001 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S 0 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ 0x1ffffe00 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S 9 #define AR_PHY_MRC_CCK_CTRL AR_AGC_OFFSET(BB_mrc_cck_ctrl) #define AR_PHY_MRC_CCK_ENABLE 0x00000001 #define AR_PHY_MRC_CCK_ENABLE_S 0 #define AR_PHY_MRC_CCK_MUX_REG 0x00000002 #define AR_PHY_MRC_CCK_MUX_REG_S 1 #define AR_PHY_RX_OCGAIN AR_AGC_OFFSET(BB_rx_ocgain) #define AR_PHY_CCA_NOM_VAL_OSPREY_2GHZ -110 #define AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ -115 #define AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ -125 #define AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ -125 #define AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ -95 #define AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ -100 #define AR_PHY_CCA_NOM_VAL_PEACOCK_5GHZ -105 #define AR_PHY_CCA_NOM_VAL_JUPITER_2GHZ -127 #define AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_2GHZ -127 #define AR_PHY_CCA_NOM_VAL_JUPITER_5GHZ -127 #define AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_5GHZ -127 #define AR_PHY_BT_COEX_4 AR_AGC_OFFSET(BB_bt_coex_4) #define AR_PHY_BT_COEX_5 AR_AGC_OFFSET(BB_bt_coex_5) /* * Noise floor readings at least CW_INT_DELTA above the nominal NF * indicate that CW interference is present. */ #define AR_PHY_CCA_CW_INT_DELTA 30 /* * AGC Field Definitions */ /* BB_ext_atten_switch_ctl_b0 */ #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN 0x00FC0000 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S 18 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN 0x00003C00 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S 10 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN 0x0000001F #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S 0 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN 0x003E0000 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S 17 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN 0x0001F000 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S 12 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB 0x00000FC0 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S 6 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB 0x0000003F #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S 0 /* BB_gain_force_max_gains_b0 */ #define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000 #define AR_PHY_RXGAIN_TXRX_ATTEN_S 12 #define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000 #define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18 #define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80 #define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7 #define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000 #define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14 /* BB_settling_time */ #define AR_PHY_SETTLING_SWITCH 0x00003F80 #define AR_PHY_SETTLING_SWITCH_S 7 /* BB_desired_sigsize */ #define AR_PHY_DESIRED_SZ_ADC 0x000000FF #define AR_PHY_DESIRED_SZ_ADC_S 0 #define AR_PHY_DESIRED_SZ_PGA 0x0000FF00 #define AR_PHY_DESIRED_SZ_PGA_S 8 #define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000 #define AR_PHY_DESIRED_SZ_TOT_DES_S 20 /* BB_cca_b0 */ #define AR_PHY_MINCCA_PWR 0x1FF00000 #define AR_PHY_MINCCA_PWR_S 20 #define AR_PHY_CCA_THRESH62 0x0007F000 #define AR_PHY_CCA_THRESH62_S 12 #define AR9280_PHY_MINCCA_PWR 0x1FF00000 #define AR9280_PHY_MINCCA_PWR_S 20 #define AR9280_PHY_CCA_THRESH62 0x000FF000 #define AR9280_PHY_CCA_THRESH62_S 12 /* BB_cca_ctrl_2_b0 */ #define AR_PHY_EXT_CCA0_THRESH62 0x000000FF #define AR_PHY_EXT_CCA0_THRESH62_S 0 /* BB_bbb_sig_detect */ #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 // [12:6] settling time for antenna switch #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13 /* BB_bbb_dagc_ctrl */ #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR_S 9 #define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00 #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10 /* BB_rifs_srch */ #define AR_PHY_RIFS_INIT_DELAY 0x3ff0000 /*B_tpc_7*/ #define AR_PHY_TPC_7_TX_GAIN_TABLE_MAX 0x3f #define AR_PHY_TPC_7_TX_GAIN_TABLE_MAX_S (0) /* BB_agc */ #define AR_PHY_AGC_QUICK_DROP_S (22) #define AR_PHY_AGC_QUICK_DROP (0xf << AR_PHY_AGC_QUICK_DROP_S) #define AR_PHY_AGC_COARSE_LOW 0x00007F80 #define AR_PHY_AGC_COARSE_LOW_S 7 #define AR_PHY_AGC_COARSE_HIGH 0x003F8000 #define AR_PHY_AGC_COARSE_HIGH_S 15 #define AR_PHY_AGC_COARSE_PWR_CONST 0x0000007F #define AR_PHY_AGC_COARSE_PWR_CONST_S 0 /* BB_find_signal */ #define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000 #define AR_PHY_FIND_SIG_FIRSTEP_S 12 #define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000 #define AR_PHY_FIND_SIG_FIRPWR_S 18 #define AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT 25 #define AR_PHY_FIND_SIG_RELPWR (0x1f << 6) #define AR_PHY_FIND_SIG_RELPWR_S 6 #define AR_PHY_FIND_SIG_RELPWR_SIGN_BIT 11 #define AR_PHY_FIND_SIG_RELSTEP 0x1f #define AR_PHY_FIND_SIG_RELSTEP_S 0 #define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT 5 /* BB_restart */ #define AR_PHY_RESTART_DIV_GC 0x001C0000 /* bb_ant_fast_div_gc_limit */ #define AR_PHY_RESTART_DIV_GC_S 18 #define AR_PHY_RESTART_ENA 0x01 /* enable restart */ #define AR_PHY_DC_RESTART_DIS 0x40000000 /* disable DC restart */ #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON 0xFF000000 //Mask BIT[31:24] #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_S 24 #define AR_PHY_TPC_OLPC_GAIN_DELTA 0x00FF0000 //Mask BIT[23:16] #define AR_PHY_TPC_OLPC_GAIN_DELTA_S 16 #define AR_PHY_TPC_6_ERROR_EST_MODE 0x03000000 //Mask BIT[25:24] #define AR_PHY_TPC_6_ERROR_EST_MODE_S 24 /* * SM Register Map */ #define AR_SM_BASE offsetof(struct bb_reg_map, bb_sm_reg_map) #define AR_SM_OFFSET(_x) (AR_SM_BASE + offsetof(struct sm_reg_map, _x)) #define AR_PHY_D2_CHIP_ID AR_SM_OFFSET(BB_D2_chip_id) #define AR_PHY_GEN_CTRL AR_SM_OFFSET(BB_gen_controls) #define AR_PHY_MODE AR_SM_OFFSET(BB_modes_select) #define AR_PHY_ACTIVE AR_SM_OFFSET(BB_active) #define AR_PHY_SPUR_MASK_A AR_SM_OFFSET(BB_vit_spur_mask_A) #define AR_PHY_SPUR_MASK_B AR_SM_OFFSET(BB_vit_spur_mask_B) #define AR_PHY_SPECTRAL_SCAN AR_SM_OFFSET(BB_spectral_scan) #define AR_PHY_RADAR_BW_FILTER AR_SM_OFFSET(BB_radar_bw_filter) #define AR_PHY_SEARCH_START_DELAY AR_SM_OFFSET(BB_search_start_delay) #define AR_PHY_MAX_RX_LEN AR_SM_OFFSET(BB_max_rx_length) #define AR_PHY_FRAME_CTL AR_SM_OFFSET(BB_frame_control) #define AR_PHY_RFBUS_REQ AR_SM_OFFSET(BB_rfbus_request) #define AR_PHY_RFBUS_GRANT AR_SM_OFFSET(BB_rfbus_grant) #define AR_PHY_RIFS AR_SM_OFFSET(BB_rifs) #define AR_PHY_RX_CLR_DELAY AR_SM_OFFSET(BB_rx_clear_delay) #define AR_PHY_RX_DELAY AR_SM_OFFSET(BB_analog_power_on_time) #define AR_PHY_BB_POWERTX_RATE9 AR_SM_OFFSET(BB_powertx_rate9) #define AR_PHY_TPC_7 AR_SM_OFFSET(BB_tpc_7) #define AR_PHY_CL_MAP_0_B0 AR_SM_OFFSET(BB_cl_map_0_b0) #define AR_PHY_CL_MAP_1_B0 AR_SM_OFFSET(BB_cl_map_1_b0) #define AR_PHY_CL_MAP_2_B0 AR_SM_OFFSET(BB_cl_map_2_b0) #define AR_PHY_CL_MAP_3_B0 AR_SM_OFFSET(BB_cl_map_3_b0) #define AR_PHY_RF_CTL(_i) AR_SM_OFFSET(BB_tx_timing_##_i) #define AR_PHY_XPA_TIMING_CTL AR_SM_OFFSET(BB_xpa_timing_control) #define AR_PHY_MISC_PA_CTL AR_SM_OFFSET(BB_misc_pa_control) #define AR_PHY_SWITCH_CHAIN_0 AR_SM_OFFSET(BB_switch_table_chn_b0) #define AR_PHY_SWITCH_COM AR_SM_OFFSET(BB_switch_table_com1) #define AR_PHY_SWITCH_COM_2 AR_SM_OFFSET(BB_switch_table_com2) #define AR_PHY_RX_CHAINMASK AR_SM_OFFSET(BB_multichain_enable) #define AR_PHY_CAL_CHAINMASK AR_SM_OFFSET(BB_cal_chain_mask) #define AR_PHY_AGC_CONTROL AR_SM_OFFSET(BB_agc_control) #define AR_PHY_CALMODE AR_SM_OFFSET(BB_iq_adc_cal_mode) #define AR_PHY_FCAL_1 AR_SM_OFFSET(BB_fcal_1) #define AR_PHY_FCAL_2_0 AR_SM_OFFSET(BB_fcal_2_b0) #define AR_PHY_DFT_TONE_CTL_0 AR_SM_OFFSET(BB_dft_tone_ctrl_b0) #define AR_PHY_CL_CAL_CTL AR_SM_OFFSET(BB_cl_cal_ctrl) #define AR_PHY_BBGAINMAP_0_1_0 AR_SM_OFFSET(BB_cl_bbgain_map_0_1_b0) #define AR_PHY_BBGAINMAP_2_3_0 AR_SM_OFFSET(BB_cl_bbgain_map_2_3_b0) #define AR_PHY_CL_TAB_0 AR_SM_OFFSET(BB_cl_tab_b0) #define AR_PHY_SYNTH_CONTROL AR_SM_OFFSET(BB_synth_control) #define AR_PHY_ADDAC_CLK_SEL AR_SM_OFFSET(BB_addac_clk_select) #define AR_PHY_PLL_CTL AR_SM_OFFSET(BB_pll_cntl) #define AR_PHY_ANALOG_SWAP AR_SM_OFFSET(BB_analog_swap) #define AR_PHY_ADDAC_PARA_CTL AR_SM_OFFSET(BB_addac_parallel_control) #define AR_PHY_XPA_CFG AR_SM_OFFSET(BB_force_analog) #define AR_PHY_AIC_CTRL_0_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_ctrl_0_b0) #define AR_PHY_AIC_CTRL_1_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_ctrl_1_b0) #define AR_PHY_AIC_CTRL_2_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_ctrl_2_b0) #define AR_PHY_AIC_CTRL_3_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_ctrl_3_b0) #define AR_PHY_AIC_STAT_0_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_stat_0_b0) #define AR_PHY_AIC_STAT_1_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_stat_1_b0) #define AR_PHY_AIC_CTRL_0_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_ctrl_0_b0) #define AR_PHY_AIC_CTRL_1_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_ctrl_1_b0) #define AR_PHY_AIC_CTRL_2_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_ctrl_2_b0) #define AR_PHY_AIC_CTRL_3_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_ctrl_3_b0) #define AR_PHY_AIC_CTRL_4_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_ctrl_4_b0) #define AR_PHY_AIC_STAT_0_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_stat_0_b0) #define AR_PHY_AIC_STAT_1_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_stat_1_b0) #define AR_PHY_AIC_STAT_2_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_stat_2_b0) #define AR_PHY_AIC_CTRL_0_B1_10 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_aic_ctrl_0_b1) #define AR_PHY_AIC_CTRL_1_B1_10 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_aic_ctrl_1_b1) #define AR_PHY_AIC_STAT_0_B1_10 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_aic_stat_0_b1) #define AR_PHY_AIC_STAT_1_B1_10 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_aic_stat_1_b1) #define AR_PHY_AIC_CTRL_0_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_ctrl_0_b1) #define AR_PHY_AIC_CTRL_1_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_ctrl_1_b1) #define AR_PHY_AIC_CTRL_4_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_ctrl_4_b1) #define AR_PHY_AIC_STAT_0_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_stat_0_b1) #define AR_PHY_AIC_STAT_1_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_stat_1_b1) #define AR_PHY_AIC_STAT_2_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_stat_2_b1) #define AR_PHY_AIC_SRAM_ADDR_B0 AR_SM_OFFSET(BB_tables_intf_addr_b0) #define AR_PHY_AIC_SRAM_DATA_B0 AR_SM_OFFSET(BB_tables_intf_data_b0) #define AR_PHY_AIC_SRAM_ADDR_B1 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_tables_intf_addr_b1) #define AR_PHY_AIC_SRAM_DATA_B1 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_tables_intf_data_b1) /* AIC fields */ #define AR_PHY_AIC_MON_ENABLE 0x80000000 #define AR_PHY_AIC_MON_ENABLE_S 31 #define AR_PHY_AIC_CAL_MAX_HOP_COUNT 0x7F000000 #define AR_PHY_AIC_CAL_MAX_HOP_COUNT_S 24 #define AR_PHY_AIC_CAL_MIN_VALID_COUNT 0x00FE0000 #define AR_PHY_AIC_CAL_MIN_VALID_COUNT_S 17 #define AR_PHY_AIC_F_WLAN 0x0001FC00 #define AR_PHY_AIC_F_WLAN_S 10 #define AR_PHY_AIC_CAL_CH_VALID_RESET 0x00000200 #define AR_PHY_AIC_CAL_CH_VALID_RESET_S 9 #define AR_PHY_AIC_CAL_ENABLE 0x00000100 #define AR_PHY_AIC_CAL_ENABLE_S 8 #define AR_PHY_AIC_BTTX_PWR_THR 0x000000FE #define AR_PHY_AIC_BTTX_PWR_THR_S 1 #define AR_PHY_AIC_ENABLE 0x00000001 #define AR_PHY_AIC_ENABLE_S 0 #define AR_PHY_AIC_CAL_BT_REF_DELAY 0x78000000 #define AR_PHY_AIC_CAL_BT_REF_DELAY_S 27 #define AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO 0x07000000 #define AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO_S 24 #define AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO 0x00F00000 #define AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO_S 20 #define AR_PHY_AIC_BT_IDLE_CFG 0x00080000 #define AR_PHY_AIC_BT_IDLE_CFG_S 19 #define AR_PHY_AIC_STDBY_COND 0x00060000 #define AR_PHY_AIC_STDBY_COND_S 17 #define AR_PHY_AIC_STDBY_ROT_ATT_DB 0x0001F800 #define AR_PHY_AIC_STDBY_ROT_ATT_DB_S 11 #define AR_PHY_AIC_STDBY_COM_ATT_DB 0x00000700 #define AR_PHY_AIC_STDBY_COM_ATT_DB_S 8 #define AR_PHY_AIC_RSSI_MAX 0x000000F0 #define AR_PHY_AIC_RSSI_MAX_S 4 #define AR_PHY_AIC_RSSI_MIN 0x0000000F #define AR_PHY_AIC_RSSI_MIN_S 0 #define AR_PHY_AIC_RADIO_DELAY 0x7F000000 #define AR_PHY_AIC_RADIO_DELAY_S 24 #define AR_PHY_AIC_CAL_STEP_SIZE_CORR 0x00F00000 #define AR_PHY_AIC_CAL_STEP_SIZE_CORR_S 20 #define AR_PHY_AIC_CAL_ROT_IDX_CORR 0x000F8000 #define AR_PHY_AIC_CAL_ROT_IDX_CORR_S 15 #define AR_PHY_AIC_CAL_CONV_CHECK_FACTOR 0x00006000 #define AR_PHY_AIC_CAL_CONV_CHECK_FACTOR_S 13 #define AR_PHY_AIC_ROT_IDX_COUNT_MAX 0x00001C00 #define AR_PHY_AIC_ROT_IDX_COUNT_MAX_S 10 #define AR_PHY_AIC_CAL_SYNTH_TOGGLE 0x00000200 #define AR_PHY_AIC_CAL_SYNTH_TOGGLE_S 9 #define AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX 0x00000100 #define AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX_S 8 #define AR_PHY_AIC_CAL_SYNTH_SETTLING 0x000000FF #define AR_PHY_AIC_CAL_SYNTH_SETTLING_S 0 #define AR_PHY_AIC_MON_MAX_HOP_COUNT 0x0FE00000 #define AR_PHY_AIC_MON_MAX_HOP_COUNT_S 21 #define AR_PHY_AIC_MON_MIN_STALE_COUNT 0x001FC000 #define AR_PHY_AIC_MON_MIN_STALE_COUNT_S 14 #define AR_PHY_AIC_MON_PWR_EST_LONG 0x00002000 #define AR_PHY_AIC_MON_PWR_EST_LONG_S 13 #define AR_PHY_AIC_MON_PD_TALLY_SCALING 0x00001800 #define AR_PHY_AIC_MON_PD_TALLY_SCALING_S 11 #define AR_PHY_AIC_MON_PERF_THR 0x000007C0 #define AR_PHY_AIC_MON_PERF_THR_S 6 #define AR_PHY_AIC_CAL_COM_ATT_DB_FIXED 0x00000020 #define AR_PHY_AIC_CAL_COM_ATT_DB_FIXED_S 5 #define AR_PHY_AIC_CAL_TARGET_MAG_SETTING 0x00000018 #define AR_PHY_AIC_CAL_TARGET_MAG_SETTING_S 3 #define AR_PHY_AIC_CAL_PERF_CHECK_FACTOR 0x00000006 #define AR_PHY_AIC_CAL_PERF_CHECK_FACTOR_S 1 #define AR_PHY_AIC_CAL_PWR_EST_LONG 0x00000001 #define AR_PHY_AIC_CAL_PWR_EST_LONG_S 0 #define AR_PHY_AIC_MON_DONE 0x80000000 #define AR_PHY_AIC_MON_DONE_S 31 #define AR_PHY_AIC_MON_ACTIVE 0x40000000 #define AR_PHY_AIC_MON_ACTIVE_S 30 #define AR_PHY_AIC_MEAS_COUNT 0x3F000000 #define AR_PHY_AIC_MEAS_COUNT_S 24 #define AR_PHY_AIC_CAL_ANT_ISO_EST 0x00FC0000 #define AR_PHY_AIC_CAL_ANT_ISO_EST_S 18 #define AR_PHY_AIC_CAL_HOP_COUNT 0x0003F800 #define AR_PHY_AIC_CAL_HOP_COUNT_S 11 #define AR_PHY_AIC_CAL_VALID_COUNT 0x000007F0 #define AR_PHY_AIC_CAL_VALID_COUNT_S 4 #define AR_PHY_AIC_CAL_BT_TOO_WEAK_ERR 0x00000008 #define AR_PHY_AIC_CAL_BT_TOO_WEAK_ERR_S 3 #define AR_PHY_AIC_CAL_BT_TOO_STRONG_ERR 0x00000004 #define AR_PHY_AIC_CAL_BT_TOO_STRONG_ERR_S 2 #define AR_PHY_AIC_CAL_DONE 0x00000002 #define AR_PHY_AIC_CAL_DONE_S 1 #define AR_PHY_AIC_CAL_ACTIVE 0x00000001 #define AR_PHY_AIC_CAL_ACTIVE_S 0 #define AR_PHY_AIC_MEAS_MAG_MIN 0xFFC00000 #define AR_PHY_AIC_MEAS_MAG_MIN_S 22 #define AR_PHY_AIC_MON_STALE_COUNT 0x003F8000 #define AR_PHY_AIC_MON_STALE_COUNT_S 15 #define AR_PHY_AIC_MON_HOP_COUNT 0x00007F00 #define AR_PHY_AIC_MON_HOP_COUNT_S 8 #define AR_PHY_AIC_CAL_AIC_SM 0x000000F8 #define AR_PHY_AIC_CAL_AIC_SM_S 3 #define AR_PHY_AIC_SM 0x00000007 #define AR_PHY_AIC_SM_S 0 #define AR_PHY_AIC_SRAM_VALID 0x00000001 #define AR_PHY_AIC_SRAM_VALID_S 0 #define AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB 0x0000007E #define AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB_S 1 #define AR_PHY_AIC_SRAM_VGA_QUAD_SIGN 0x00000080 #define AR_PHY_AIC_SRAM_VGA_QUAD_SIGN_S 7 #define AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB 0x00003F00 #define AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB_S 8 #define AR_PHY_AIC_SRAM_VGA_DIR_SIGN 0x00004000 #define AR_PHY_AIC_SRAM_VGA_DIR_SIGN_S 14 #define AR_PHY_AIC_SRAM_COM_ATT_6DB 0x00038000 #define AR_PHY_AIC_SRAM_COM_ATT_6DB_S 15 #define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW 3 #define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW_S 0 /* BB_cl_tab_bx */ #define AR_PHY_CL_TAB_CARR_LK_DC_ADD_I 0x07FF0000 #define AR_PHY_CL_TAB_CARR_LK_DC_ADD_I_S 16 #define AR_PHY_CL_TAB_CARR_LK_DC_ADD_Q 0x0000FFE0 #define AR_PHY_CL_TAB_CARR_LK_DC_ADD_Q_S 5 #define AR_PHY_CL_TAB_GAIN_MOD 0x0000001F #define AR_PHY_CL_TAB_GAIN_MOD_S 0 /* BB_vit_spur_mask_A fields */ #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A 0x0001FC00 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S 10 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A 0x3FF #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0 /* enable_flt_svd*/ #define AR_PHY_ENABLE_FLT_SVD 0x00001000 #define AR_PHY_ENABLE_FLT_SVD_S 12 #define AR_PHY_TEST AR_SM_OFFSET(BB_test_controls) #define AR_PHY_TEST_BBB_OBS_SEL 0x780000 #define AR_PHY_TEST_BBB_OBS_SEL_S 19 /* bits 19 to 22 are cf_bbb_obs_sel*/ #define AR_PHY_TEST_RX_OBS_SEL_BIT5_S 23 #define AR_PHY_TEST_RX_OBS_SEL_BIT5 (1 << AR_PHY_TEST_RX_OBS_SEL_BIT5_S)// This is bit 5 for cf_rx_obs_sel #define AR_PHY_TEST_CHAIN_SEL 0xC0000000 #define AR_PHY_TEST_CHAIN_SEL_S 30 /*bits 30 and 31 are tstdac_out_sel which selects which chain to drive out*/ #define AR_PHY_TEST_CTL_STATUS AR_SM_OFFSET(BB_test_controls_status) #define AR_PHY_TEST_CTL_TSTDAC_EN 0x1 #define AR_PHY_TEST_CTL_TSTDAC_EN_S 0 /*cf_tstdac_en, driver to tstdac bus, 0=disable, 1=enable*/ #define AR_PHY_TEST_CTL_TX_OBS_SEL 0x1C #define AR_PHY_TEST_CTL_TX_OBS_SEL_S 2 /* cf_tx_obs_sel, bits 2:4*/ #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL 0x60 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S 5 /* cf_tx_obs_sel, bits 5:6, setting to 11 selects ADC*/ #define AR_PHY_TEST_CTL_TSTADC_EN 0x100 #define AR_PHY_TEST_CTL_TSTADC_EN_S 8 /*cf_tstadc_en, driver to tstadc bus, 0=disable, 1=enable*/ #define AR_PHY_TEST_CTL_RX_OBS_SEL 0x3C00 #define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10 /* cf_tx_obs_sel, bits 10:13*/ #define AR_PHY_TEST_CTL_DEBUGPORT_SEL 0xe0000000 #define AR_PHY_TEST_CTL_DEBUGPORT_SEL_S 29 #define AR_PHY_TSTDAC AR_SM_OFFSET(BB_tstdac) #define AR_PHY_CHAN_STATUS AR_SM_OFFSET(BB_channel_status) #define AR_PHY_CHAN_INFO_MEMORY AR_SM_OFFSET(BB_chaninfo_ctrl) #define AR_PHY_CHNINFO_NOISEPWR AR_SM_OFFSET(BB_chan_info_noise_pwr) #define AR_PHY_CHNINFO_GAINDIFF AR_SM_OFFSET(BB_chan_info_gain_diff) #define AR_PHY_CHNINFO_FINETIM AR_SM_OFFSET(BB_chan_info_fine_timing) #define AR_PHY_CHAN_INFO_GAIN_0 AR_SM_OFFSET(BB_chan_info_gain_b0) #define AR_PHY_SCRAMBLER_SEED AR_SM_OFFSET(BB_scrambler_seed) #define AR_PHY_CCK_TX_CTRL AR_SM_OFFSET(BB_bbb_tx_ctrl) #define AR_PHY_TX_FIR(_i) AR_SM_OFFSET(BB_bbb_txfir_##_i) #define AR_PHY_HEAVYCLIP_CTL AR_SM_OFFSET(BB_heavy_clip_ctrl) #define AR_PHY_HEAVYCLIP_20 AR_SM_OFFSET(BB_heavy_clip_20) #define AR_PHY_HEAVYCLIP_40 AR_SM_OFFSET(BB_heavy_clip_40) #define AR_PHY_ILLEGAL_TXRATE AR_SM_OFFSET(BB_illegal_tx_rate) #define AR_PHY_POWER_TX_RATE(_i) AR_SM_OFFSET(BB_powertx_rate##_i) #define AR_PHY_PWRTX_MAX AR_SM_OFFSET(BB_powertx_max) /* TPC register */ #define AR_PHY_PWRTX_MAX_TPC_ENABLE 0x00000040 #define AR_PHY_POWER_TX_SUB AR_SM_OFFSET(BB_powertx_sub) #define AR_PHY_PER_PACKET_POWERTX_MAX 0x00000040 #define AR_PHY_PER_PACKET_POWERTX_MAX_S 6 #define AR_PHY_POWER_TX_SUB_2_DISABLE 0xFFFFFFC0 /* 2 chain */ #define AR_PHY_POWER_TX_SUB_3_DISABLE 0xFFFFF000 /* 3 chain */ #define AR_PHY_TPC(_i) AR_SM_OFFSET(BB_tpc_##_i) /* values 1-3, 7-10 and 12-15 */ #define AR_PHY_TPC_4_B0 AR_SM_OFFSET(BB_tpc_4_b0) #define AR_PHY_TPC_5_B0 AR_SM_OFFSET(BB_tpc_5_b0) #define AR_PHY_TPC_6_B0 AR_SM_OFFSET(BB_tpc_6_b0) #define AR_PHY_TPC_18 AR_SM_OFFSET(BB_tpc_18) #define AR_PHY_TPC_19 AR_SM_OFFSET(BB_tpc_19) #define AR_PHY_TX_FORCED_GAIN AR_SM_OFFSET(BB_tx_forced_gain) #define AR_PHY_PDADC_TAB_0 AR_SM_OFFSET(BB_pdadc_tab_b0) #define AR_PHY_RTT_CTRL AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_rtt_ctrl) #define AR_PHY_RTT_TABLE_SW_INTF_B0 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_rtt_table_sw_intf_b0) #define AR_PHY_RTT_TABLE_SW_INTF_1_B0 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_rtt_table_sw_intf_1_b0) #define AR_PHY_TX_IQCAL_CONTROL_0(_ah) \ (AR_SREV_POSEIDON(_ah) ? \ AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiqcal_control_0) : \ AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiqcal_control_0)) #define AR_PHY_TX_IQCAL_CONTROL_1(_ah) \ (AR_SREV_POSEIDON(_ah) ? \ AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiqcal_control_1) : \ AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiqcal_control_1)) #define AR_PHY_TX_IQCAL_START(_ah) \ (AR_SREV_POSEIDON(_ah) ? \ AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiqcal_control_0) : \ AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiqcal_start)) #define AR_PHY_TX_IQCAL_STATUS_B0(_ah) \ (AR_SREV_POSEIDON(_ah) ? \ AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiqcal_status_b0) : \ AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiqcal_status_b0)) #define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiq_corr_coeff_01_b0) #define AR_PHY_TX_IQCAL_CORR_COEFF_23_B0 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiq_corr_coeff_23_b0) #define AR_PHY_TX_IQCAL_CORR_COEFF_45_B0 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiq_corr_coeff_45_b0) #define AR_PHY_TX_IQCAL_CORR_COEFF_67_B0 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiq_corr_coeff_67_b0) #define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiq_corr_coeff_01_b0) #define AR_PHY_TX_IQCAL_CORR_COEFF_23_B0_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiq_corr_coeff_23_b0) #define AR_PHY_TX_IQCAL_CORR_COEFF_45_B0_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiq_corr_coeff_45_b0) #define AR_PHY_TX_IQCAL_CORR_COEFF_67_B0_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiq_corr_coeff_67_b0) #define AR_PHY_TXGAIN_TAB(_i) AR_SM_OFFSET(BB_tx_gain_tab_##_i) /* values 1-22 */ #define AR_PHY_TXGAIN_TAB_PAL(_i) AR_SM_OFFSET(BB_tx_gain_tab_pal_##_i) /* values 1-22 */ #define AR_PHY_PANIC_WD_STATUS AR_SM_OFFSET(BB_panic_watchdog_status) #define AR_PHY_PANIC_WD_CTL_1 AR_SM_OFFSET(BB_panic_watchdog_ctrl_1) #define AR_PHY_PANIC_WD_CTL_2 AR_SM_OFFSET(BB_panic_watchdog_ctrl_2) #define AR_PHY_BT_CTL AR_SM_OFFSET(BB_bluetooth_cntl) #define AR_PHY_ONLY_WARMRESET AR_SM_OFFSET(BB_phyonly_warm_reset) #define AR_PHY_ONLY_CTL AR_SM_OFFSET(BB_phyonly_control) #define AR_PHY_ECO_CTRL AR_SM_OFFSET(BB_eco_ctrl) #define AR_PHY_BB_THERM_ADC_1 AR_SM_OFFSET(BB_therm_adc_1) #define AR_PHY_BB_THERM_ADC_4 AR_SM_OFFSET(BB_therm_adc_4) #define AR_PHY_65NM(_field) offsetof(struct radio65_reg, _field) #define AR_PHY_65NM_CH0_TXRF1 AR_PHY_65NM(ch0_TXRF1) #define AR_PHY_65NM_CH0_TXRF2 AR_PHY_65NM(ch0_TXRF2) #define AR_PHY_65NM_CH0_TXRF2_DB2G 0x07000000 #define AR_PHY_65NM_CH0_TXRF2_DB2G_S 24 #define AR_PHY_65NM_CH0_TXRF2_OB2G_CCK 0x00E00000 #define AR_PHY_65NM_CH0_TXRF2_OB2G_CCK_S 21 #define AR_PHY_65NM_CH0_TXRF2_OB2G_PSK 0x001C0000 #define AR_PHY_65NM_CH0_TXRF2_OB2G_PSK_S 18 #define AR_PHY_65NM_CH0_TXRF2_OB2G_QAM 0x00038000 #define AR_PHY_65NM_CH0_TXRF2_OB2G_QAM_S 15 #define AR_PHY_65NM_CH0_TXRF3 AR_PHY_65NM(ch0_TXRF3) #define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G 0x0000001E #define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G_S 1 #define AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE 0x00000001 #define AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE_S 0 #define AR_PHY_65NM_CH1_TXRF1 AR_PHY_65NM(ch1_TXRF1) #define AR_PHY_65NM_CH1_TXRF2 AR_PHY_65NM(ch1_TXRF2) #define AR_PHY_65NM_CH1_TXRF3 AR_PHY_65NM(ch1_TXRF3) #define AR_PHY_65NM_CH2_TXRF1 AR_PHY_65NM(ch2_TXRF1) #define AR_PHY_65NM_CH2_TXRF2 AR_PHY_65NM(ch2_TXRF2) #define AR_PHY_65NM_CH2_TXRF3 AR_PHY_65NM(ch2_TXRF3) #define AR_PHY_65NM_CH0_SYNTH4 AR_PHY_65NM(ch0_SYNTH4) #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S 1 #define AR_PHY_65NM_CH0_SYNTH7 AR_PHY_65NM(ch0_SYNTH7) #define AR_PHY_65NM_CH0_BIAS1 AR_PHY_65NM(ch0_BIAS1) #define AR_PHY_65NM_CH0_BIAS2 AR_PHY_65NM(ch0_BIAS2) #define AR_PHY_65NM_CH0_BIAS4 AR_PHY_65NM(ch0_BIAS4) #define AR_PHY_65NM_CH0_RXTX4 AR_PHY_65NM(ch0_RXTX4) #define AR_PHY_65NM_CH0_SYNTH12 AR_PHY_65NM(ch0_SYNTH12) #define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3 0x00780000 #define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3_S 19 #define AR_PHY_65NM_CH1_RXTX4 AR_PHY_65NM(ch1_RXTX4) #define AR_PHY_65NM_CH2_RXTX4 AR_PHY_65NM(ch2_RXTX4) #define AR_PHY_65NM_RXTX4_XLNA_BIAS 0xC0000000 #define AR_PHY_65NM_RXTX4_XLNA_BIAS_S 30 #define AR_PHY_65NM_CH0_TOP AR_PHY_65NM(overlay_0x16180.Osprey.ch0_TOP) #define AR_PHY_65NM_CH0_TOP_JUPITER AR_PHY_65NM(overlay_0x16180.Jupiter.ch0_TOP1) #define AR_PHY_65NM_CH0_TOP_XPABIASLVL 0x00000300 #define AR_PHY_65NM_CH0_TOP_XPABIASLVL_S 8 #define AR_PHY_65NM_CH0_TOP2 AR_PHY_65NM(overlay_0x16180.Osprey.ch0_TOP2) #define AR_OSPREY_CH0_XTAL AR_PHY_65NM(overlay_0x16180.Osprey.ch0_XTAL) #define AR_OSPREY_CHO_XTAL_CAPINDAC 0x7F000000 #define AR_OSPREY_CHO_XTAL_CAPINDAC_S 24 #define AR_OSPREY_CHO_XTAL_CAPOUTDAC 0x00FE0000 #define AR_OSPREY_CHO_XTAL_CAPOUTDAC_S 17 #define AR_PHY_65NM_CH0_THERM AR_PHY_65NM(overlay_0x16180.Osprey.ch0_THERM) #define AR_PHY_65NM_CH0_THERM_JUPITER AR_PHY_65NM(overlay_0x16180.Jupiter.ch0_THERM) #define AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB 0x00000003 #define AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB_S 0 #define AR_PHY_65NM_CH0_THERM_XPASHORT2GND 0x00000004 #define AR_PHY_65NM_CH0_THERM_XPASHORT2GND_S 2 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT 0x0000ff00 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S 8 #define AR_PHY_65NM_CH0_THERM_START 0x20000000 #define AR_PHY_65NM_CH0_THERM_START_S 29 #define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000 #define AR_PHY_65NM_CH0_THERM_LOCAL_S 31 #define AR_PHY_65NM_CH0_RXTX1 AR_PHY_65NM(ch0_RXTX1) #define AR_PHY_65NM_CH0_RXTX2 AR_PHY_65NM(ch0_RXTX2) #define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK 0x00000004 #define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S 2 #define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK 0x00000008 #define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S 3 #define AR_PHY_65NM_CH0_RXTX3 AR_PHY_65NM(ch0_RXTX3) #define AR_PHY_65NM_CH1_RXTX1 AR_PHY_65NM(ch1_RXTX1) #define AR_PHY_65NM_CH1_RXTX2 AR_PHY_65NM(ch1_RXTX2) #define AR_PHY_65NM_CH1_RXTX3 AR_PHY_65NM(ch1_RXTX3) #define AR_PHY_65NM_CH2_RXTX1 AR_PHY_65NM(ch2_RXTX1) #define AR_PHY_65NM_CH2_RXTX2 AR_PHY_65NM(ch2_RXTX2) #define AR_PHY_65NM_CH2_RXTX3 AR_PHY_65NM(ch2_RXTX3) #define AR_PHY_65NM_CH0_BB1 AR_PHY_65NM(ch0_BB1) #define AR_PHY_65NM_CH0_BB2 AR_PHY_65NM(ch0_BB2) #define AR_PHY_65NM_CH0_BB3 AR_PHY_65NM(ch0_BB3) #define AR_PHY_65NM_CH1_BB1 AR_PHY_65NM(ch1_BB1) #define AR_PHY_65NM_CH1_BB2 AR_PHY_65NM(ch1_BB2) #define AR_PHY_65NM_CH1_BB3 AR_PHY_65NM(ch1_BB3) #define AR_PHY_65NM_CH2_BB1 AR_PHY_65NM(ch2_BB1) #define AR_PHY_65NM_CH2_BB2 AR_PHY_65NM(ch2_BB2) #define AR_PHY_CH_BB3_SEL_OFST_READBK 0x00000300 #define AR_PHY_CH_BB3_SEL_OFST_READBK_S 8 #define AR_PHY_CH_BB3_OFSTCORRI2VQ 0x03e00000 #define AR_PHY_CH_BB3_OFSTCORRI2VQ_S 21 #define AR_PHY_CH_BB3_OFSTCORRI2VI 0x7c000000 #define AR_PHY_CH_BB3_OFSTCORRI2VI_S 26 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT 0x00380000 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S 19 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT 0x00c00000 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT_S 22 #define AR_PHY_LNAGAIN_LONG_SHIFT 0xe0000000 #define AR_PHY_LNAGAIN_LONG_SHIFT_S 29 #define AR_PHY_MXRGAIN_LONG_SHIFT 0x03000000 #define AR_PHY_MXRGAIN_LONG_SHIFT_S 24 #define AR_PHY_VGAGAIN_LONG_SHIFT 0x1c000000 #define AR_PHY_VGAGAIN_LONG_SHIFT_S 26 #define AR_PHY_SCFIR_GAIN_LONG_SHIFT 0x00000001 #define AR_PHY_SCFIR_GAIN_LONG_SHIFT_S 0 #define AR_PHY_MANRXGAIN_LONG_SHIFT 0x00000002 #define AR_PHY_MANRXGAIN_LONG_SHIFT_S 1 #define AR_PHY_MANTXGAIN_LONG_SHIFT 0x80000000 #define AR_PHY_MANTXGAIN_LONG_SHIFT_S 31 /* * SM Field Definitions */ /* BB_cl_cal_ctrl - AR_PHY_CL_CAL_CTL */ #define AR_PHY_CL_CAL_ENABLE 0x00000002 /* do carrier leak calibration after agc_calibrate_done */ #define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001 #define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000 #define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22 #define AR_PHY_CL_MAP_HW_GEN 0x80000000 #define AR_PHY_CL_MAP_HW_GEN_S 31 /* BB_addac_parallel_control - AR_PHY_ADDAC_PARA_CTL */ #define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000 /* BB_fcal_2_b0 - AR_PHY_FCAL_2_0 */ #define AR_PHY_FCAL20_CAP_STATUS_0 0x01f00000 #define AR_PHY_FCAL20_CAP_STATUS_0_S 20 /* BB_rfbus_request */ #define AR_PHY_RFBUS_REQ_EN 0x00000001 /* request for RF bus */ /* BB_rfbus_grant */ #define AR_PHY_RFBUS_GRANT_EN 0x00000001 /* RF bus granted */ /* BB_gen_controls */ #define AR_PHY_GC_TURBO_MODE 0x00000001 /* set turbo mode bits */ #define AR_PHY_GC_TURBO_SHORT 0x00000002 /* set short symbols to turbo mode setting */ #define AR_PHY_GC_DYN2040_EN 0x00000004 /* enable dyn 20/40 mode */ #define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */ #define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/ #define AR_PHY_GC_DYN2040_PRI_CH_S 4 #define AR_PHY_GC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */ #define AR_PHY_GC_HT_EN 0x00000040 /* ht enable */ #define AR_PHY_GC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */ #define AR_PHY_GC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */ #define AR_PHY_GC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */ #define AR_PHY_GC_GF_DETECT_EN 0x00000400 /* enable Green Field detection. Only affects rx, not tx */ #define AR_PHY_GC_ENABLE_DAC_FIFO 0x00000800 /* fifo between bb and dac */ #define AR_PHY_MS_HALF_RATE 0x00000020 #define AR_PHY_MS_QUARTER_RATE 0x00000040 /* BB_analog_power_on_time */ #define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */ /* BB_agc_control */ #define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */ #define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calibration */ #define AR_PHY_AGC_CONTROL_OFFSET_CAL 0x00000800 /* allow offset calibration */ #define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 /* enable noise floor calibration to happen */ #define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 /* allow tx filter calibration */ #define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* don't update noise floor automatically */ #define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 /* extend noise floor power measurement */ #define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 /* carrier leak calibration done */ #define AR_PHY_AGC_CONTROL_PKDET_CAL 0x00100000 /* allow peak deteter calibration */ #define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0 #define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6 /* BB_iq_adc_cal_mode */ #define AR_PHY_CALMODE_IQ 0x00000000 #define AR_PHY_CALMODE_ADC_GAIN 0x00000001 #define AR_PHY_CALMODE_ADC_DC_PER 0x00000002 #define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003 /* BB_analog_swap */ #define AR_PHY_SWAP_ALT_CHAIN 0x00000040 /* BB_modes_select */ #define AR_PHY_MODE_OFDM 0x00000000 /* OFDM */ #define AR_PHY_MODE_CCK 0x00000001 /* CCK */ #define AR_PHY_MODE_DYNAMIC 0x00000004 /* dynamic CCK/OFDM mode */ #define AR_PHY_MODE_DYNAMIC_S 2 #define AR_PHY_MODE_HALF 0x00000020 /* enable half rate */ #define AR_PHY_MODE_QUARTER 0x00000040 /* enable quarter rate */ #define AR_PHY_MAC_CLK_MODE 0x00000080 /* MAC runs at 128/141MHz clock */ #define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100 /* Disable dynamic CCK detection */ #define AR_PHY_MODE_SVD_HALF 0x00000200 /* enable svd half rate */ #define AR_PHY_MODE_DISABLE_CCK 0x00000100 #define AR_PHY_MODE_DISABLE_CCK_S 8 /* BB_active */ #define AR_PHY_ACTIVE_EN 0x00000001 /* Activate PHY chips */ #define AR_PHY_ACTIVE_DIS 0x00000000 /* Deactivate PHY chips */ /* BB_force_analog */ #define AR_PHY_FORCE_XPA_CFG 0x000000001 #define AR_PHY_FORCE_XPA_CFG_S 0 /* BB_xpa_timing_control */ #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF 0xFF000000 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S 24 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF 0x00FF0000 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S 16 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON 0x0000FF00 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S 8 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON 0x000000FF #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S 0 /* BB_tx_timing_3 */ #define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000 #define AR_PHY_TX_END_TO_A2_RX_ON_S 16 /* BB_tx_timing_2 */ #define AR_PHY_TX_END_DATA_START 0x000000FF #define AR_PHY_TX_END_DATA_START_S 0 #define AR_PHY_TX_END_PA_ON 0x0000FF00 #define AR_PHY_TX_END_PA_ON_S 8 /* BB_tpc_5_b0 */ /* ar2413 power control */ #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22 /* BB_tpc_1 */ #define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000 #define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14 #define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000 #define AR_PHY_TPCRG1_PD_GAIN_1_S 16 #define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000 #define AR_PHY_TPCRG1_PD_GAIN_2_S 18 #define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000 #define AR_PHY_TPCRG1_PD_GAIN_3_S 20 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN 0x0000003e #define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1 #define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001 /* BB_tx_forced_gain */ #define AR_PHY_TXGAIN_FORCE 0x00000001 #define AR_PHY_TXGAIN_FORCE_S 0 #define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00 #define AR_PHY_TXGAIN_FORCED_PADVGNRA_S 10 #define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000 #define AR_PHY_TXGAIN_FORCED_PADVGNRB_S 14 #define AR_PHY_TXGAIN_FORCED_PADVGNRC 0x003c0000 #define AR_PHY_TXGAIN_FORCED_PADVGNRC_S 18 #define AR_PHY_TXGAIN_FORCED_PADVGNRD 0x00c00000 #define AR_PHY_TXGAIN_FORCED_PADVGNRD_S 22 #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN 0x000003c0 #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN_S 6 #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN 0x0000000e #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S 1 #define AR_PHY_TXGAIN_FORCED_TXBB6DBGAIN 0x00000030 #define AR_PHY_TXGAIN_FORCED_TXBB6DBGAIN_S 4 /* BB_powertx_rate1 */ #define AR_PHY_POWER_TX_RATE1 0x9934 #define AR_PHY_POWER_TX_RATE2 0x9938 #define AR_PHY_POWER_TX_RATE_MAX AR_PHY_PWRTX_MAX #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040 /* BB_test_controls */ #define PHY_AGC_CLR 0x10000000 /* disable AGC to A2 */ #define RFSILENT_BB 0x00002000 /* shush bb */ /* BB_chan_info_gain_diff */ #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK 0xFFF /* PPM value is 12-bit signed integer */ #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT 0x800 /* Sign bit */ #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320 /* Maximum absolute value */ /* BB_chaninfo_ctrl */ #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001 /* BB_search_start_delay */ #define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */ /* BB_bbb_tx_ctrl */ #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010 /* BB_spectral_scan */ #define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001 /* Enable spectral scan */ #define AR_PHY_SPECTRAL_SCAN_ENABLE_S 0 #define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan */ #define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports */ #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4 #define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports */ #define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8 #define AR_PHY_SPECTRAL_SCAN_COUNT 0x0FFF0000 /* Number of reports */ #define AR_PHY_SPECTRAL_SCAN_COUNT_S 16 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x10000000 /* Short repeat */ #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 28 #define AR_PHY_SPECTRAL_SCAN_PRIORITY_HI 0x20000000 /* high priority */ #define AR_PHY_SPECTRAL_SCAN_PRIORITY_HI_S 29 /* BB_channel_status */ #define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004 /* BB_rtt_ctrl */ #define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION 0x00000001 #define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION_S 0 #define AR_PHY_RTT_CTRL_RESTORE_MASK 0x0000007E #define AR_PHY_RTT_CTRL_RESTORE_MASK_S 1 #define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE 0x00000080 #define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE_S 7 /* BB_rtt_table_sw_intf_b0 */ #define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_0 0x00000001 #define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_0_S 0 #define AR_PHY_RTT_SW_RTT_TABLE_WRITE_0 0x00000002 #define AR_PHY_RTT_SW_RTT_TABLE_WRITE_0_S 1 #define AR_PHY_RTT_SW_RTT_TABLE_ADDR_0 0x0000001C #define AR_PHY_RTT_SW_RTT_TABLE_ADDR_0_S 2 /* BB_rtt_table_sw_intf_1_b0 */ #define AR_PHY_RTT_SW_RTT_TABLE_DATA_0 0xFFFFFFF0 #define AR_PHY_RTT_SW_RTT_TABLE_DATA_0_S 4 /* BB_txiqcal_control_0 */ #define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL 0x80000000 #define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL_S 31 /* BB_txiqcal_control_1 */ #define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000 #define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18 /* BB_txiqcal_start */ #define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001 #define AR_PHY_TX_IQCAL_START_DO_CAL_S 0 /* BB_txiqcal_start for Poseidon */ #define AR_PHY_TX_IQCAL_START_DO_CAL_POSEIDON 0x80000000 #define AR_PHY_TX_IQCAL_START_DO_CAL_POSEIDON_S 31 /* Generic B0, B1, B2 IQ Cal bit fields */ /* BB_txiqcal_status_b* */ #define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001 #define AR_PHY_CALIBRATED_GAINS_0_S 1 #define AR_PHY_CALIBRATED_GAINS_0 (0x1f<