Index: head/sys/boot/fdt/dts/arm/h3.dtsi
===================================================================
--- head/sys/boot/fdt/dts/arm/h3.dtsi	(revision 313013)
+++ head/sys/boot/fdt/dts/arm/h3.dtsi	(revision 313014)
@@ -1,179 +1,179 @@
 /*-
  * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
  * $FreeBSD$
  */
 
 #include <dt-bindings/clock/sun4i-a10-pll2.h>
 
 / {
 	cpus {
 		cpu0: cpu@0 {
 			clocks = <&cpu>;
 			clock-latency = <2000000>;
 		};
 	};
 
 	clocks {
 		pll2: clk@01c20008 {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun8i-h3-pll2-clk";
 			reg = <0x01c20008 0x4>;
 			clocks = <&osc24M>;
 			clock-output-names = "pll2-1x", "pll2-2x",
 			"pll2-4x", "pll2-8x";
 		};
 
 		ths_clk: clk@1c20074 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun8i-h3-ths-clk";
 			reg = <0x01c20074 0x4>;
 			clocks = <&osc24M>;
 			clock-output-names = "ths";
 		};
 
 		codec_clk: clk@01c20140 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-codec-clk";
 			reg = <0x01c20140 0x4>;
 			clocks = <&pll2 SUN4I_A10_PLL2_1X>;
 			clock-output-names = "codec";
 		};
 	};
 
 	soc {
 		emac: ethernet@1c30000 {
 			compatible = "allwinner,sun8i-h3-emac";
 			reg = <0x01c30000 0x104>, <0x01c00030 0x4>;
 			reg-names = "emac", "syscon";
 			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&ahb_rst 17>;
-			reset-names = "ahb";
-			clocks = <&bus_gates 17>;
-			clock-names = "ahb";
+			resets = <&ahb_rst 17>, <&ahb_rst 66>;
+			reset-names = "ahb", "ephy";
+			clocks = <&bus_gates 17>, <&bus_gates 128>;
+			clock-names = "ahb", "ephy";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
 		};
 
 		i2c0: i2c@1c2ac00 {
 			compatible = "allwinner,sun6i-a31-i2c";
 			reg = <0x01c2ac00 0x400>;
 			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&bus_gates 96>;
 			resets = <&apb2_rst 0>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
 
 		i2c1: i2c@1c2b000 {
 			compatible = "allwinner,sun6i-a31-i2c";
 			reg = <0x01c2b000 0x400>;
 			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&bus_gates 97>;
 			resets = <&apb2_rst 1>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
 
 		i2c2: i2c@1c2b400 {
 			compatible = "allwinner,sun6i-a31-i2c";
 			reg = <0x01c2b400 0x400>;
 			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&bus_gates 98>;
 			resets = <&apb2_rst 2>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
 
 		r_i2c: i2c@1f02400 {
 			compatible = "allwinner,sun6i-a31-i2c";
 			reg = <0x01f02400 0x400>;
 			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
 
 		sid: eeprom@1c14000 {
 			compatible = "allwinner,sun8i-a83t-sid";
 			reg = <0x01c14000 0x400>;
 		};
 
 		rtp: rtp@1c25000 {
 			compatible = "allwinner,sun8i-h3-ts";
 			reg = <0x01c25000 0x400>;
 			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&bus_gates 72>, <&ths_clk>;
 			clock-names = "ahb", "ths";
 			resets = <&apb1_rst 8>;
 			#thermal-sensor-cells = <0>;
 		};
 
 		dma: dma-controller@01c02000 {
 			compatible = "allwinner,sun8i-h3-dma";
 			reg = <0x01c02000 0x1000>;
 			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&bus_gates 6>;
 			clock-names = "ahb";
 			resets = <&ahb_rst 6>;
 			reset-names = "ahb";
 			#dma-cells = <1>;
 		};
 
 		codec: codec@01c22c00 {
 			compatible = "allwinner,sun8i-h3-codec";
 			reg = <0x01c22c00 0x100>, <0x01f015c0 0x4>;
 			reg-names = "codec", "pr";
 			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&bus_gates 64>, <&codec_clk>;
 			clock-names = "ahb", "codec";
 			resets = <&ahb_rst 128>;
 			reset-names = "ahb";
 			dmas = <&dma 15>, <&dma 15>;
 			dma-names = "rx", "tx";
 			status = "disabled";
 		};
 
 	};
 };
 
 &pll1 {
 	compatible = "allwinner,sun8i-h3-pll1-clk";
 };
 
 &pio {
 	emac_pins_rgmii_a: emac_rgmii@0 {
 		allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
 				 "PD7", "PD8", "PD9", "PD10", "PD12", "PD13",
 				 "PD15", "PD16", "PD17";
 		allwinner,function = "emac";
 		allwinner,drive = <SUN4I_PINCTRL_40_MA>;
 		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 	};
 };