Index: head/sys/arm/at91/at91_spi.c =================================================================== --- head/sys/arm/at91/at91_spi.c (revision 310228) +++ head/sys/arm/at91/at91_spi.c (revision 310229) @@ -1,457 +1,459 @@ /*- * Copyright (c) 2006 M. Warner Losh. * Copyright (c) 2011-2012 Ian Lepore. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef FDT #include #include #endif #include "spibus_if.h" struct at91_spi_softc { device_t dev; /* Myself */ void *intrhand; /* Interrupt handle */ struct resource *irq_res; /* IRQ resource */ struct resource *mem_res; /* Memory resource */ bus_dma_tag_t dmatag; /* bus dma tag for transfers */ bus_dmamap_t map[4]; /* Maps for the transaction */ struct sx xfer_mtx; /* Enforce one transfer at a time */ uint32_t xfer_done; /* interrupt<->mainthread signaling */ }; #define CS_TO_MR(cs) ((~(1 << (cs)) & 0x0f) << 16) static inline uint32_t RD4(struct at91_spi_softc *sc, bus_size_t off) { return (bus_read_4(sc->mem_res, off)); } static inline void WR4(struct at91_spi_softc *sc, bus_size_t off, uint32_t val) { bus_write_4(sc->mem_res, off, val); } /* bus entry points */ static int at91_spi_attach(device_t dev); static int at91_spi_detach(device_t dev); static int at91_spi_probe(device_t dev); static int at91_spi_transfer(device_t dev, device_t child, struct spi_command *cmd); /* helper routines */ static void at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error); static int at91_spi_activate(device_t dev); static void at91_spi_deactivate(device_t dev); static void at91_spi_intr(void *arg); static int at91_spi_probe(device_t dev) { #ifdef FDT if (!ofw_bus_is_compatible(dev, "atmel,at91rm9200-spi")) return (ENXIO); #endif device_set_desc(dev, "AT91 SPI"); return (0); } static int at91_spi_attach(device_t dev) { struct at91_spi_softc *sc; int err; uint32_t csr; sc = device_get_softc(dev); sc->dev = dev; sx_init(&sc->xfer_mtx, device_get_nameunit(dev)); /* * Allocate resources. */ err = at91_spi_activate(dev); if (err) goto out; #ifdef FDT /* * Disable devices need to hold their resources, so return now and not attach * the spibus, setup interrupt handlers, etc. */ if (!ofw_bus_status_okay(dev)) return 0; #endif /* * Set up the hardware. */ WR4(sc, SPI_CR, SPI_CR_SWRST); /* "Software Reset must be Written Twice" erratum */ WR4(sc, SPI_CR, SPI_CR_SWRST); WR4(sc, SPI_IDR, 0xffffffff); WR4(sc, SPI_MR, (0xf << 24) | SPI_MR_MSTR | SPI_MR_MODFDIS | CS_TO_MR(0)); /* * For now, run the bus at the slowest speed possible as otherwise we * may encounter data corruption on transmit as seen with ETHERNUT5 * and AT45DB321D even though both board and slave device can take * more. * This also serves as a work-around for the "NPCSx rises if no data * data is to be transmitted" erratum. The ideal workaround for the * latter is to take the chip select control away from the peripheral * and manage it directly as a GPIO line. The easy solution is to * slow down the bus so dramatically that it just never gets starved * as may be seen when the OCHI controller is running and consuming * memory and APB bandwidth. * Also, currently we lack a way for lettting both the board and the * slave devices take their maximum supported SPI clocks into account. * Also, we hard-wire SPI mode to 3. */ csr = SPI_CSR_CPOL | (4 << 16) | (0xff << 8); WR4(sc, SPI_CSR0, csr); WR4(sc, SPI_CSR1, csr); WR4(sc, SPI_CSR2, csr); WR4(sc, SPI_CSR3, csr); WR4(sc, SPI_CR, SPI_CR_SPIEN); WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS); WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS); WR4(sc, PDC_RNPR, 0); WR4(sc, PDC_RNCR, 0); WR4(sc, PDC_TNPR, 0); WR4(sc, PDC_TNCR, 0); WR4(sc, PDC_RPR, 0); WR4(sc, PDC_RCR, 0); WR4(sc, PDC_TPR, 0); WR4(sc, PDC_TCR, 0); RD4(sc, SPI_RDR); RD4(sc, SPI_SR); device_add_child(dev, "spibus", -1); bus_generic_attach(dev); out: if (err) at91_spi_deactivate(dev); return (err); } static int at91_spi_detach(device_t dev) { return (EBUSY); /* XXX */ } static int at91_spi_activate(device_t dev) { struct at91_spi_softc *sc; int err, i, rid; sc = device_get_softc(dev); err = ENOMEM; rid = 0; sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->mem_res == NULL) goto out; rid = 0; sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (sc->irq_res == NULL) goto out; err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, at91_spi_intr, sc, &sc->intrhand); if (err != 0) goto out; err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2048, 1, 2048, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->dmatag); if (err != 0) goto out; for (i = 0; i < 4; i++) { err = bus_dmamap_create(sc->dmatag, 0, &sc->map[i]); if (err != 0) goto out; } out: if (err != 0) at91_spi_deactivate(dev); return (err); } static void at91_spi_deactivate(device_t dev) { struct at91_spi_softc *sc; int i; sc = device_get_softc(dev); bus_generic_detach(dev); for (i = 0; i < 4; i++) if (sc->map[i]) bus_dmamap_destroy(sc->dmatag, sc->map[i]); if (sc->dmatag) bus_dma_tag_destroy(sc->dmatag); if (sc->intrhand) bus_teardown_intr(dev, sc->irq_res, sc->intrhand); sc->intrhand = NULL; if (sc->irq_res) bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), sc->irq_res); sc->irq_res = NULL; if (sc->mem_res) bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res), sc->mem_res); sc->mem_res = NULL; } static void at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs __unused, int error) { if (error != 0) return; *(bus_addr_t *)arg = segs[0].ds_addr; } static int at91_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct at91_spi_softc *sc; bus_addr_t addr; int err, i, j, mode[4]; uint32_t cs; KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("%s: TX/RX command sizes should be equal", __func__)); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("%s: TX/RX data sizes should be equal", __func__)); /* get the proper chip select */ spibus_get_cs(child, &cs); + cs &= ~SPIBUS_CS_HIGH; + sc = device_get_softc(dev); i = 0; sx_xlock(&sc->xfer_mtx); /* * Disable transfers while we set things up. */ WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS); /* * PSCDEC = 0 has a range of 0..3 for chip select. We * don't support PSCDEC = 1 which has a range of 0..15. */ if (cs > 3) { device_printf(dev, "Invalid chip select %d requested by %s\n", cs, device_get_nameunit(child)); err = EINVAL; goto out; } #ifdef SPI_CHIP_SELECT_HIGH_SUPPORT /* * The AT91RM9200 couldn't do CS high for CS 0. Other chips can, but we * don't support that yet, or other spi modes. */ if (at91_is_rm92() && cs == 0 && (cmd->flags & SPI_CHIP_SELECT_HIGH) != 0) { device_printf(dev, "Invalid chip select high requested by %s for cs 0.\n", device_get_nameunit(child)); err = EINVAL; goto out; } #endif err = (RD4(sc, SPI_MR) & ~0x000f0000) | CS_TO_MR(cs); WR4(sc, SPI_MR, err); /* * Set up the TX side of the transfer. */ if ((err = bus_dmamap_load(sc->dmatag, sc->map[i], cmd->tx_cmd, cmd->tx_cmd_sz, at91_getaddr, &addr, 0)) != 0) goto out; WR4(sc, PDC_TPR, addr); WR4(sc, PDC_TCR, cmd->tx_cmd_sz); bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREWRITE); mode[i++] = BUS_DMASYNC_POSTWRITE; if (cmd->tx_data_sz > 0) { if ((err = bus_dmamap_load(sc->dmatag, sc->map[i], cmd->tx_data, cmd->tx_data_sz, at91_getaddr, &addr, 0)) != 0) goto out; WR4(sc, PDC_TNPR, addr); WR4(sc, PDC_TNCR, cmd->tx_data_sz); bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREWRITE); mode[i++] = BUS_DMASYNC_POSTWRITE; } /* * Set up the RX side of the transfer. */ if ((err = bus_dmamap_load(sc->dmatag, sc->map[i], cmd->rx_cmd, cmd->rx_cmd_sz, at91_getaddr, &addr, 0)) != 0) goto out; WR4(sc, PDC_RPR, addr); WR4(sc, PDC_RCR, cmd->rx_cmd_sz); bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREREAD); mode[i++] = BUS_DMASYNC_POSTREAD; if (cmd->rx_data_sz > 0) { if ((err = bus_dmamap_load(sc->dmatag, sc->map[i], cmd->rx_data, cmd->rx_data_sz, at91_getaddr, &addr, 0)) != 0) goto out; WR4(sc, PDC_RNPR, addr); WR4(sc, PDC_RNCR, cmd->rx_data_sz); bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREREAD); mode[i++] = BUS_DMASYNC_POSTREAD; } /* * Start the transfer, wait for it to complete. */ sc->xfer_done = 0; WR4(sc, SPI_IER, SPI_SR_RXBUFF); WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN | PDC_PTCR_RXTEN); do err = tsleep(&sc->xfer_done, PCATCH | PZERO, "at91_spi", hz); while (sc->xfer_done == 0 && err != EINTR); /* * Stop the transfer and clean things up. */ WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS); if (err == 0) for (j = 0; j < i; j++) bus_dmamap_sync(sc->dmatag, sc->map[j], mode[j]); out: for (j = 0; j < i; j++) bus_dmamap_unload(sc->dmatag, sc->map[j]); sx_xunlock(&sc->xfer_mtx); return (err); } static void at91_spi_intr(void *arg) { struct at91_spi_softc *sc; uint32_t sr; sc = (struct at91_spi_softc*)arg; sr = RD4(sc, SPI_SR) & RD4(sc, SPI_IMR); if ((sr & SPI_SR_RXBUFF) != 0) { sc->xfer_done = 1; WR4(sc, SPI_IDR, SPI_SR_RXBUFF); wakeup(&sc->xfer_done); } if ((sr & ~SPI_SR_RXBUFF) != 0) { device_printf(sc->dev, "Unexpected ISR %#x\n", sr); WR4(sc, SPI_IDR, sr & ~SPI_SR_RXBUFF); } } static devclass_t at91_spi_devclass; static device_method_t at91_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, at91_spi_probe), DEVMETHOD(device_attach, at91_spi_attach), DEVMETHOD(device_detach, at91_spi_detach), /* spibus interface */ DEVMETHOD(spibus_transfer, at91_spi_transfer), DEVMETHOD_END }; static driver_t at91_spi_driver = { "spi", at91_spi_methods, sizeof(struct at91_spi_softc), }; #ifdef FDT DRIVER_MODULE(at91_spi, simplebus, at91_spi_driver, at91_spi_devclass, NULL, NULL); #else DRIVER_MODULE(at91_spi, atmelarm, at91_spi_driver, at91_spi_devclass, NULL, NULL); #endif Index: head/sys/arm/broadcom/bcm2835/bcm2835_spi.c =================================================================== --- head/sys/arm/broadcom/bcm2835/bcm2835_spi.c (revision 310228) +++ head/sys/arm/broadcom/bcm2835/bcm2835_spi.c (revision 310229) @@ -1,525 +1,528 @@ /*- * Copyright (c) 2012 Oleksandr Tymoshenko * Copyright (c) 2013 Luiz Otavio O Souza * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" static struct ofw_compat_data compat_data[] = { {"broadcom,bcm2835-spi", 1}, {"brcm,bcm2835-spi", 1}, {NULL, 0} }; static void bcm_spi_intr(void *); #ifdef BCM_SPI_DEBUG static void bcm_spi_printr(device_t dev) { struct bcm_spi_softc *sc; uint32_t reg; sc = device_get_softc(dev); reg = BCM_SPI_READ(sc, SPI_CS); device_printf(dev, "CS=%b\n", reg, "\20\1CS0\2CS1\3CPHA\4CPOL\7CSPOL" "\10TA\11DMAEN\12INTD\13INTR\14ADCS\15REN\16LEN" "\21DONE\22RXD\23TXD\24RXR\25RXF\26CSPOL0\27CSPOL1" "\30CSPOL2\31DMA_LEN\32LEN_LONG"); reg = BCM_SPI_READ(sc, SPI_CLK) & SPI_CLK_MASK; if (reg % 2) reg--; if (reg == 0) reg = 65536; device_printf(dev, "CLK=%uMhz/%d=%luhz\n", SPI_CORE_CLK / 1000000, reg, SPI_CORE_CLK / reg); reg = BCM_SPI_READ(sc, SPI_DLEN) & SPI_DLEN_MASK; device_printf(dev, "DLEN=%d\n", reg); reg = BCM_SPI_READ(sc, SPI_LTOH) & SPI_LTOH_MASK; device_printf(dev, "LTOH=%d\n", reg); reg = BCM_SPI_READ(sc, SPI_DC); device_printf(dev, "DC=RPANIC=%#x RDREQ=%#x TPANIC=%#x TDREQ=%#x\n", (reg & SPI_DC_RPANIC_MASK) >> SPI_DC_RPANIC_SHIFT, (reg & SPI_DC_RDREQ_MASK) >> SPI_DC_RDREQ_SHIFT, (reg & SPI_DC_TPANIC_MASK) >> SPI_DC_TPANIC_SHIFT, (reg & SPI_DC_TDREQ_MASK) >> SPI_DC_TDREQ_SHIFT); } #endif static void bcm_spi_modifyreg(struct bcm_spi_softc *sc, uint32_t off, uint32_t mask, uint32_t value) { uint32_t reg; mtx_assert(&sc->sc_mtx, MA_OWNED); reg = BCM_SPI_READ(sc, off); reg &= ~mask; reg |= value; BCM_SPI_WRITE(sc, off, reg); } static int bcm_spi_clock_proc(SYSCTL_HANDLER_ARGS) { struct bcm_spi_softc *sc; uint32_t clk; int error; sc = (struct bcm_spi_softc *)arg1; BCM_SPI_LOCK(sc); clk = BCM_SPI_READ(sc, SPI_CLK); BCM_SPI_UNLOCK(sc); clk &= 0xffff; if (clk == 0) clk = 65536; clk = SPI_CORE_CLK / clk; error = sysctl_handle_int(oidp, &clk, sizeof(clk), req); if (error != 0 || req->newptr == NULL) return (error); clk = SPI_CORE_CLK / clk; if (clk <= 1) clk = 2; else if (clk % 2) clk--; if (clk > 0xffff) clk = 0; BCM_SPI_LOCK(sc); BCM_SPI_WRITE(sc, SPI_CLK, clk); BCM_SPI_UNLOCK(sc); return (0); } static int bcm_spi_cs_bit_proc(SYSCTL_HANDLER_ARGS, uint32_t bit) { struct bcm_spi_softc *sc; uint32_t reg; int error; sc = (struct bcm_spi_softc *)arg1; BCM_SPI_LOCK(sc); reg = BCM_SPI_READ(sc, SPI_CS); BCM_SPI_UNLOCK(sc); reg = (reg & bit) ? 1 : 0; error = sysctl_handle_int(oidp, ®, sizeof(reg), req); if (error != 0 || req->newptr == NULL) return (error); if (reg) reg = bit; BCM_SPI_LOCK(sc); bcm_spi_modifyreg(sc, SPI_CS, bit, reg); BCM_SPI_UNLOCK(sc); return (0); } static int bcm_spi_cpol_proc(SYSCTL_HANDLER_ARGS) { return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CPOL)); } static int bcm_spi_cpha_proc(SYSCTL_HANDLER_ARGS) { return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CPHA)); } static int bcm_spi_cspol0_proc(SYSCTL_HANDLER_ARGS) { return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL0)); } static int bcm_spi_cspol1_proc(SYSCTL_HANDLER_ARGS) { return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL1)); } static void bcm_spi_sysctl_init(struct bcm_spi_softc *sc) { struct sysctl_ctx_list *ctx; struct sysctl_oid *tree_node; struct sysctl_oid_list *tree; /* * Add system sysctl tree/handlers. */ ctx = device_get_sysctl_ctx(sc->sc_dev); tree_node = device_get_sysctl_tree(sc->sc_dev); tree = SYSCTL_CHILDREN(tree_node); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_spi_clock_proc, "IU", "SPI BUS clock frequency"); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cpol", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_spi_cpol_proc, "IU", "SPI BUS clock polarity"); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cpha", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_spi_cpha_proc, "IU", "SPI BUS clock phase"); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol0", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_spi_cspol0_proc, "IU", "SPI BUS chip select 0 polarity"); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol1", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_spi_cspol1_proc, "IU", "SPI BUS chip select 1 polarity"); } static int bcm_spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "BCM2708/2835 SPI controller"); return (BUS_PROBE_DEFAULT); } static int bcm_spi_attach(device_t dev) { struct bcm_spi_softc *sc; device_t gpio; int i, rid; if (device_get_unit(dev) != 0) { device_printf(dev, "only one SPI controller supported\n"); return (ENXIO); } sc = device_get_softc(dev); sc->sc_dev = dev; /* Configure the GPIO pins to ALT0 function to enable SPI the pins. */ gpio = devclass_get_device(devclass_find("gpio"), 0); if (!gpio) { device_printf(dev, "cannot find gpio0\n"); return (ENXIO); } for (i = 0; i < nitems(bcm_spi_pins); i++) bcm_gpio_set_alternate(gpio, bcm_spi_pins[i], BCM_GPIO_ALT0); rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "cannot allocate memory window\n"); return (ENXIO); } sc->sc_bst = rman_get_bustag(sc->sc_mem_res); sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); rid = 0; sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (!sc->sc_irq_res) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); device_printf(dev, "cannot allocate interrupt\n"); return (ENXIO); } /* Hook up our interrupt handler. */ if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, bcm_spi_intr, sc, &sc->sc_intrhand)) { bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); device_printf(dev, "cannot setup the interrupt handler\n"); return (ENXIO); } mtx_init(&sc->sc_mtx, "bcm_spi", NULL, MTX_DEF); /* Add sysctl nodes. */ bcm_spi_sysctl_init(sc); #ifdef BCM_SPI_DEBUG bcm_spi_printr(dev); #endif /* * Enable the SPI controller. Clear the rx and tx FIFO. * Defaults to SPI mode 0. */ BCM_SPI_WRITE(sc, SPI_CS, SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO); /* Set the SPI clock to 500Khz. */ BCM_SPI_WRITE(sc, SPI_CLK, SPI_CORE_CLK / 500000); #ifdef BCM_SPI_DEBUG bcm_spi_printr(dev); #endif device_add_child(dev, "spibus", -1); return (bus_generic_attach(dev)); } static int bcm_spi_detach(device_t dev) { struct bcm_spi_softc *sc; bus_generic_detach(dev); sc = device_get_softc(dev); mtx_destroy(&sc->sc_mtx); if (sc->sc_intrhand) bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); if (sc->sc_irq_res) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (0); } static void bcm_spi_fill_fifo(struct bcm_spi_softc *sc) { struct spi_command *cmd; uint32_t cs, written; uint8_t *data; cmd = sc->sc_cmd; cs = BCM_SPI_READ(sc, SPI_CS) & (SPI_CS_TA | SPI_CS_TXD); while (sc->sc_written < sc->sc_len && cs == (SPI_CS_TA | SPI_CS_TXD)) { data = (uint8_t *)cmd->tx_cmd; written = sc->sc_written++; if (written >= cmd->tx_cmd_sz) { data = (uint8_t *)cmd->tx_data; written -= cmd->tx_cmd_sz; } BCM_SPI_WRITE(sc, SPI_FIFO, data[written]); cs = BCM_SPI_READ(sc, SPI_CS) & (SPI_CS_TA | SPI_CS_TXD); } } static void bcm_spi_drain_fifo(struct bcm_spi_softc *sc) { struct spi_command *cmd; uint32_t cs, read; uint8_t *data; cmd = sc->sc_cmd; cs = BCM_SPI_READ(sc, SPI_CS) & SPI_CS_RXD; while (sc->sc_read < sc->sc_len && cs == SPI_CS_RXD) { data = (uint8_t *)cmd->rx_cmd; read = sc->sc_read++; if (read >= cmd->rx_cmd_sz) { data = (uint8_t *)cmd->rx_data; read -= cmd->rx_cmd_sz; } data[read] = BCM_SPI_READ(sc, SPI_FIFO) & 0xff; cs = BCM_SPI_READ(sc, SPI_CS) & SPI_CS_RXD; } } static void bcm_spi_intr(void *arg) { struct bcm_spi_softc *sc; sc = (struct bcm_spi_softc *)arg; BCM_SPI_LOCK(sc); /* Filter stray interrupts. */ if ((sc->sc_flags & BCM_SPI_BUSY) == 0) { BCM_SPI_UNLOCK(sc); return; } /* TX - Fill up the FIFO. */ bcm_spi_fill_fifo(sc); /* RX - Drain the FIFO. */ bcm_spi_drain_fifo(sc); /* Check for end of transfer. */ if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len) { /* Disable interrupts and the SPI engine. */ bcm_spi_modifyreg(sc, SPI_CS, SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 0); wakeup(sc->sc_dev); } BCM_SPI_UNLOCK(sc); } static int bcm_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct bcm_spi_softc *sc; uint32_t cs; int err; sc = device_get_softc(dev); KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("TX/RX command sizes should be equal")); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("TX/RX data sizes should be equal")); /* Get the proper chip select for this child. */ spibus_get_cs(child, &cs); + + cs &= ~SPIBUS_CS_HIGH; + if (cs > 2) { device_printf(dev, "Invalid chip select %d requested by %s\n", cs, device_get_nameunit(child)); return (EINVAL); } BCM_SPI_LOCK(sc); /* If the controller is in use wait until it is available. */ while (sc->sc_flags & BCM_SPI_BUSY) mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_spi", 0); /* Now we have control over SPI controller. */ sc->sc_flags = BCM_SPI_BUSY; /* Clear the FIFO. */ bcm_spi_modifyreg(sc, SPI_CS, SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO, SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO); /* Save a pointer to the SPI command. */ sc->sc_cmd = cmd; sc->sc_read = 0; sc->sc_written = 0; sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz; /* * Set the CS for this transaction, enable interrupts and announce * we're ready to tx. This will kick off the first interrupt. */ bcm_spi_modifyreg(sc, SPI_CS, SPI_CS_MASK | SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, cs | SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD); /* Wait for the transaction to complete. */ err = mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_spi", hz * 2); /* Make sure the SPI engine and interrupts are disabled. */ bcm_spi_modifyreg(sc, SPI_CS, SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 0); /* Release the controller and wakeup the next thread waiting for it. */ sc->sc_flags = 0; wakeup_one(dev); BCM_SPI_UNLOCK(sc); /* * Check for transfer timeout. The SPI controller doesn't * return errors. */ if (err == EWOULDBLOCK) { device_printf(sc->sc_dev, "SPI error\n"); err = EIO; } return (err); } static phandle_t bcm_spi_get_node(device_t bus, device_t dev) { /* We only have one child, the SPI bus, which needs our own node. */ return (ofw_bus_get_node(bus)); } static device_method_t bcm_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, bcm_spi_probe), DEVMETHOD(device_attach, bcm_spi_attach), DEVMETHOD(device_detach, bcm_spi_detach), /* SPI interface */ DEVMETHOD(spibus_transfer, bcm_spi_transfer), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, bcm_spi_get_node), DEVMETHOD_END }; static devclass_t bcm_spi_devclass; static driver_t bcm_spi_driver = { "spi", bcm_spi_methods, sizeof(struct bcm_spi_softc), }; DRIVER_MODULE(bcm2835_spi, simplebus, bcm_spi_driver, bcm_spi_devclass, 0, 0); Index: head/sys/arm/freescale/vybrid/vf_spi.c =================================================================== --- head/sys/arm/freescale/vybrid/vf_spi.c (revision 310228) +++ head/sys/arm/freescale/vybrid/vf_spi.c (revision 310229) @@ -1,291 +1,293 @@ /*- * Copyright (c) 2014 Ruslan Bukin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Vybrid Family Serial Peripheral Interface (SPI) * Chapter 47, Vybrid Reference Manual, Rev. 5, 07/2013 */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" #include #include #include #include #include #include #include #define SPI_FIFO_SIZE 4 #define SPI_MCR 0x00 /* Module Configuration */ #define MCR_MSTR (1 << 31) /* Master/Slave Mode Select */ #define MCR_CONT_SCKE (1 << 30) /* Continuous SCK Enable */ #define MCR_FRZ (1 << 27) /* Freeze */ #define MCR_PCSIS_S 16 /* Peripheral Chip Select */ #define MCR_PCSIS_M 0x3f #define MCR_MDIS (1 << 14) /* Module Disable */ #define MCR_CLR_TXF (1 << 11) /* Clear TX FIFO */ #define MCR_CLR_RXF (1 << 10) /* Clear RX FIFO */ #define MCR_HALT (1 << 0) /* Starts and stops SPI transfers */ #define SPI_TCR 0x08 /* Transfer Count */ #define SPI_CTAR0 0x0C /* Clock and Transfer Attributes */ #define SPI_CTAR0_SLAVE 0x0C /* Clock and Transfer Attributes */ #define SPI_CTAR1 0x10 /* Clock and Transfer Attributes */ #define SPI_CTAR2 0x14 /* Clock and Transfer Attributes */ #define SPI_CTAR3 0x18 /* Clock and Transfer Attributes */ #define CTAR_FMSZ_M 0xf #define CTAR_FMSZ_S 27 /* Frame Size */ #define CTAR_FMSZ_8 0x7 /* 8 bits */ #define CTAR_CPOL (1 << 26) /* Clock Polarity */ #define CTAR_CPHA (1 << 25) /* Clock Phase */ #define CTAR_LSBFE (1 << 24) /* Less significant bit first */ #define CTAR_PCSSCK_M 0x3 #define CTAR_PCSSCK_S 22 /* PCS to SCK Delay Prescaler */ #define CTAR_PBR_M 0x3 #define CTAR_PBR_S 16 /* Baud Rate Prescaler */ #define CTAR_PBR_7 0x3 /* Divide by 7 */ #define CTAR_CSSCK_M 0xf #define CTAR_CSSCK_S 12 /* PCS to SCK Delay Scaler */ #define CTAR_BR_M 0xf #define CTAR_BR_S 0 /* Baud Rate Scaler */ #define SPI_SR 0x2C /* Status Register */ #define SR_TCF (1 << 31) /* Transfer Complete Flag */ #define SR_EOQF (1 << 28) /* End of Queue Flag */ #define SR_TFFF (1 << 25) /* Transmit FIFO Fill Flag */ #define SR_RFDF (1 << 17) /* Receive FIFO Drain Flag */ #define SPI_RSER 0x30 /* DMA/Interrupt Select */ #define RSER_EOQF_RE (1 << 28) /* Finished Request Enable */ #define SPI_PUSHR 0x34 /* PUSH TX FIFO In Master Mode */ #define PUSHR_CONT (1 << 31) /* Continuous Peripheral CS */ #define PUSHR_EOQ (1 << 27) /* End Of Queue */ #define PUSHR_CTCNT (1 << 26) /* Clear Transfer Counter */ #define PUSHR_PCS_M 0x3f #define PUSHR_PCS_S 16 /* Select PCS signals */ #define SPI_PUSHR_SLAVE 0x34 /* PUSH TX FIFO Register In Slave Mode */ #define SPI_POPR 0x38 /* POP RX FIFO Register */ #define SPI_TXFR0 0x3C /* Transmit FIFO Registers */ #define SPI_TXFR1 0x40 #define SPI_TXFR2 0x44 #define SPI_TXFR3 0x48 #define SPI_RXFR0 0x7C /* Receive FIFO Registers */ #define SPI_RXFR1 0x80 #define SPI_RXFR2 0x84 #define SPI_RXFR3 0x88 struct spi_softc { struct resource *res[2]; bus_space_tag_t bst; bus_space_handle_t bsh; void *ih; }; static struct resource_spec spi_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE }, { -1, 0 } }; static int spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "fsl,mvf600-spi")) return (ENXIO); device_set_desc(dev, "Vybrid Family Serial Peripheral Interface"); return (BUS_PROBE_DEFAULT); } static int spi_attach(device_t dev) { struct spi_softc *sc; uint32_t reg; sc = device_get_softc(dev); if (bus_alloc_resources(dev, spi_spec, sc->res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } /* Memory interface */ sc->bst = rman_get_bustag(sc->res[0]); sc->bsh = rman_get_bushandle(sc->res[0]); reg = READ4(sc, SPI_MCR); reg |= MCR_MSTR; reg &= ~(MCR_CONT_SCKE | MCR_MDIS | MCR_FRZ); reg &= ~(MCR_PCSIS_M << MCR_PCSIS_S); reg |= (MCR_PCSIS_M << MCR_PCSIS_S); /* PCS Active low */ reg |= (MCR_CLR_TXF | MCR_CLR_RXF); WRITE4(sc, SPI_MCR, reg); reg = READ4(sc, SPI_RSER); reg |= RSER_EOQF_RE; WRITE4(sc, SPI_RSER, reg); reg = READ4(sc, SPI_MCR); reg &= ~MCR_HALT; WRITE4(sc, SPI_MCR, reg); reg = READ4(sc, SPI_CTAR0); reg &= ~(CTAR_FMSZ_M << CTAR_FMSZ_S); reg |= (CTAR_FMSZ_8 << CTAR_FMSZ_S); /* * TODO: calculate BR * SCK baud rate = ( fsys / PBR ) * (1 + DBR) / BR * * reg &= ~(CTAR_BR_M << CTAR_BR_S); */ reg &= ~CTAR_CPOL; /* Polarity */ reg |= CTAR_CPHA; /* * Set LSB (Less significant bit first) * must be used for some applications, e.g. some LCDs */ reg |= CTAR_LSBFE; WRITE4(sc, SPI_CTAR0, reg); reg = READ4(sc, SPI_CTAR0); reg &= ~(CTAR_PBR_M << CTAR_PBR_S); reg |= (CTAR_PBR_7 << CTAR_PBR_S); WRITE4(sc, SPI_CTAR0, reg); device_add_child(dev, "spibus", 0); return (bus_generic_attach(dev)); } static int spi_txrx(struct spi_softc *sc, uint8_t *out_buf, uint8_t *in_buf, int bufsz, int cs) { uint32_t reg, wreg; uint32_t txcnt; uint32_t i; txcnt = 0; for (i = 0; i < bufsz; i++) { txcnt++; wreg = out_buf[i]; wreg |= PUSHR_CONT; wreg |= (cs << PUSHR_PCS_S); if (i == 0) wreg |= PUSHR_CTCNT; if (i == (bufsz - 1) || txcnt == SPI_FIFO_SIZE) wreg |= PUSHR_EOQ; WRITE4(sc, SPI_PUSHR, wreg); if (i == (bufsz - 1) || txcnt == SPI_FIFO_SIZE) { txcnt = 0; /* Wait last entry in a queue to be transmitted */ while((READ4(sc, SPI_SR) & SR_EOQF) == 0) continue; reg = READ4(sc, SPI_SR); reg |= (SR_TCF | SR_EOQF); WRITE4(sc, SPI_SR, reg); } /* Wait until RX FIFO is empty */ while((READ4(sc, SPI_SR) & SR_RFDF) == 0) continue; in_buf[i] = READ1(sc, SPI_POPR); } return (0); } static int spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct spi_softc *sc; uint32_t cs; sc = device_get_softc(dev); KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("%s: TX/RX command sizes should be equal", __func__)); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("%s: TX/RX data sizes should be equal", __func__)); /* get the proper chip select */ spibus_get_cs(child, &cs); + cs &= ~SPIBUS_CS_HIGH; + /* Command */ spi_txrx(sc, cmd->tx_cmd, cmd->rx_cmd, cmd->tx_cmd_sz, cs); /* Data */ spi_txrx(sc, cmd->tx_data, cmd->rx_data, cmd->tx_data_sz, cs); return (0); } static device_method_t spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, spi_probe), DEVMETHOD(device_attach, spi_attach), /* SPI interface */ DEVMETHOD(spibus_transfer, spi_transfer), { 0, 0 } }; static driver_t spi_driver = { "spi", spi_methods, sizeof(struct spi_softc), }; static devclass_t spi_devclass; DRIVER_MODULE(spi, simplebus, spi_driver, spi_devclass, 0, 0); Index: head/sys/arm/lpc/lpc_spi.c =================================================================== --- head/sys/arm/lpc/lpc_spi.c (revision 310228) +++ head/sys/arm/lpc/lpc_spi.c (revision 310229) @@ -1,198 +1,200 @@ /*- * Copyright (c) 2011 Jakub Wojciech Klama * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" struct lpc_spi_softc { device_t ls_dev; struct resource * ls_mem_res; struct resource * ls_irq_res; bus_space_tag_t ls_bst; bus_space_handle_t ls_bsh; }; static int lpc_spi_probe(device_t); static int lpc_spi_attach(device_t); static int lpc_spi_detach(device_t); static int lpc_spi_transfer(device_t, device_t, struct spi_command *); #define lpc_spi_read_4(_sc, _reg) \ bus_space_read_4(_sc->ls_bst, _sc->ls_bsh, _reg) #define lpc_spi_write_4(_sc, _reg, _val) \ bus_space_write_4(_sc->ls_bst, _sc->ls_bsh, _reg, _val) static int lpc_spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "lpc,spi")) return (ENXIO); device_set_desc(dev, "LPC32x0 PL022 SPI/SSP controller"); return (BUS_PROBE_DEFAULT); } static int lpc_spi_attach(device_t dev) { struct lpc_spi_softc *sc = device_get_softc(dev); int rid; sc->ls_dev = dev; rid = 0; sc->ls_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->ls_mem_res) { device_printf(dev, "cannot allocate memory window\n"); return (ENXIO); } sc->ls_bst = rman_get_bustag(sc->ls_mem_res); sc->ls_bsh = rman_get_bushandle(sc->ls_mem_res); rid = 0; sc->ls_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (!sc->ls_irq_res) { device_printf(dev, "cannot allocate interrupt\n"); return (ENXIO); } bus_space_write_4(sc->ls_bst, 0xd0028100, 0, (1<<12)|(1<<10)|(1<<9)|(1<<8)|(1<<6)|(1<<5)); lpc_pwr_write(dev, LPC_CLKPWR_SSP_CTRL, LPC_CLKPWR_SSP_CTRL_SSP0EN); lpc_spi_write_4(sc, LPC_SSP_CR0, LPC_SSP_CR0_DSS(8)); lpc_spi_write_4(sc, LPC_SSP_CR1, LPC_SSP_CR1_SSE); lpc_spi_write_4(sc, LPC_SSP_CPSR, 128); device_add_child(dev, "spibus", 0); return (bus_generic_attach(dev)); } static int lpc_spi_detach(device_t dev) { return (EBUSY); } static int lpc_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct lpc_spi_softc *sc = device_get_softc(dev); uint32_t cs; uint8_t *in_buf, *out_buf; int i; spibus_get_cs(child, &cs); + cs &= ~SPIBUS_CS_HIGH; + /* Set CS active */ lpc_gpio_set_state(child, cs, 0); /* Wait for FIFO to be ready */ while ((lpc_spi_read_4(sc, LPC_SSP_SR) & LPC_SSP_SR_TNF) == 0); /* Command */ in_buf = cmd->rx_cmd; out_buf = cmd->tx_cmd; for (i = 0; i < cmd->tx_cmd_sz; i++) { lpc_spi_write_4(sc, LPC_SSP_DR, out_buf[i]); in_buf[i] = lpc_spi_read_4(sc, LPC_SSP_DR); } /* Data */ in_buf = cmd->rx_data; out_buf = cmd->tx_data; for (i = 0; i < cmd->tx_data_sz; i++) { lpc_spi_write_4(sc, LPC_SSP_DR, out_buf[i]); in_buf[i] = lpc_spi_read_4(sc, LPC_SSP_DR); } /* Set CS inactive */ lpc_gpio_set_state(child, cs, 1); return (0); } static device_method_t lpc_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, lpc_spi_probe), DEVMETHOD(device_attach, lpc_spi_attach), DEVMETHOD(device_detach, lpc_spi_detach), /* SPI interface */ DEVMETHOD(spibus_transfer, lpc_spi_transfer), { 0, 0 } }; static devclass_t lpc_spi_devclass; static driver_t lpc_spi_driver = { "spi", lpc_spi_methods, sizeof(struct lpc_spi_softc), }; DRIVER_MODULE(lpcspi, simplebus, lpc_spi_driver, lpc_spi_devclass, 0, 0); Index: head/sys/arm/samsung/exynos/exynos5_spi.c =================================================================== --- head/sys/arm/samsung/exynos/exynos5_spi.c (revision 310228) +++ head/sys/arm/samsung/exynos/exynos5_spi.c (revision 310229) @@ -1,234 +1,236 @@ /*- * Copyright (c) 2014 Ruslan Bukin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Exynos 5 Serial Peripheral Interface (SPI) */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" #include #include #include #include #include #include #include #define CH_CFG 0x00 /* SPI configuration */ #define SW_RST (1 << 5) /* Reset */ #define RX_CH_ON (1 << 1) /* SPI Rx Channel On */ #define TX_CH_ON (1 << 0) /* SPI Tx Channel On */ #define MODE_CFG 0x08 /* FIFO control */ #define CS_REG 0x0C /* slave selection control */ #define NSSOUT (1 << 0) #define SPI_INT_EN 0x10 /* interrupt enable */ #define SPI_STATUS 0x14 /* SPI status */ #define TX_FIFO_LVL_S 6 #define TX_FIFO_LVL_M 0x1ff #define RX_FIFO_LVL_S 15 #define RX_FIFO_LVL_M 0x1ff #define SPI_TX_DATA 0x18 /* Tx data */ #define SPI_RX_DATA 0x1C /* Rx data */ #define PACKET_CNT_REG 0x20 /* packet count */ #define PENDING_CLR_REG 0x24 /* interrupt pending clear */ #define SWAP_CFG 0x28 /* swap configuration */ #define FB_CLK_SEL 0x2C /* feedback clock selection */ #define FB_CLK_180 0x2 /* 180 degree phase lagging */ struct spi_softc { struct resource *res[2]; bus_space_tag_t bst; bus_space_handle_t bsh; device_t dev; }; struct spi_softc *spi_sc; static struct resource_spec spi_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE }, { -1, 0 } }; static int spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "samsung,exynos5-spi")) return (ENXIO); device_set_desc(dev, "Exynos 5 Serial Peripheral Interface (SPI)"); return (BUS_PROBE_DEFAULT); } static int spi_attach(device_t dev) { struct spi_softc *sc; int reg; sc = device_get_softc(dev); sc->dev = dev; if (bus_alloc_resources(dev, spi_spec, sc->res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } /* Memory interface */ sc->bst = rman_get_bustag(sc->res[0]); sc->bsh = rman_get_bushandle(sc->res[0]); spi_sc = sc; WRITE4(sc, FB_CLK_SEL, FB_CLK_180); reg = READ4(sc, CH_CFG); reg |= (RX_CH_ON | TX_CH_ON); WRITE4(sc, CH_CFG, reg); device_add_child(dev, "spibus", 0); return (bus_generic_attach(dev)); } static int spi_txrx(struct spi_softc *sc, uint8_t *out_buf, uint8_t *in_buf, int bufsz, int cs) { uint32_t reg; uint32_t i; if (bufsz == 0) { /* Nothing to transfer */ return (0); } /* Reset registers */ reg = READ4(sc, CH_CFG); reg |= SW_RST; WRITE4(sc, CH_CFG, reg); reg &= ~SW_RST; WRITE4(sc, CH_CFG, reg); /* Assert CS */ reg = READ4(sc, CS_REG); reg &= ~NSSOUT; WRITE4(sc, CS_REG, reg); for (i = 0; i < bufsz; i++) { /* TODO: Implement FIFO operation */ /* Wait all the data shifted out */ while (READ4(sc, SPI_STATUS) & \ (TX_FIFO_LVL_M << TX_FIFO_LVL_S)) continue; WRITE1(sc, SPI_TX_DATA, out_buf[i]); /* Wait until no data available */ while ((READ4(sc, SPI_STATUS) & \ (RX_FIFO_LVL_M << RX_FIFO_LVL_S)) == 0) continue; in_buf[i] = READ1(sc, SPI_RX_DATA); } /* Deassert CS */ reg = READ4(sc, CS_REG); reg |= NSSOUT; WRITE4(sc, CS_REG, reg); return (0); } static int spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct spi_softc *sc; uint32_t cs; sc = device_get_softc(dev); KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("%s: TX/RX command sizes should be equal", __func__)); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("%s: TX/RX data sizes should be equal", __func__)); /* get the proper chip select */ spibus_get_cs(child, &cs); + cs &= ~SPIBUS_CS_HIGH; + /* Command */ spi_txrx(sc, cmd->tx_cmd, cmd->rx_cmd, cmd->tx_cmd_sz, cs); /* Data */ spi_txrx(sc, cmd->tx_data, cmd->rx_data, cmd->tx_data_sz, cs); return (0); } static device_method_t spi_methods[] = { DEVMETHOD(device_probe, spi_probe), DEVMETHOD(device_attach, spi_attach), /* SPI interface */ DEVMETHOD(spibus_transfer, spi_transfer), { 0, 0 } }; static driver_t spi_driver = { "spi", spi_methods, sizeof(struct spi_softc), }; static devclass_t spi_devclass; DRIVER_MODULE(spi, simplebus, spi_driver, spi_devclass, 0, 0); Index: head/sys/arm/ti/ti_spi.c =================================================================== --- head/sys/arm/ti/ti_spi.c (revision 310228) +++ head/sys/arm/ti/ti_spi.c (revision 310229) @@ -1,581 +1,584 @@ /*- * Copyright (c) 2016 Rubicon Communications, LLC (Netgate) * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" static void ti_spi_intr(void *); static int ti_spi_detach(device_t); #undef TI_SPI_DEBUG #ifdef TI_SPI_DEBUG #define IRQSTATUSBITS \ "\020\1TX0_EMPTY\2TX0_UNDERFLOW\3RX0_FULL\4RX0_OVERFLOW" \ "\5TX1_EMPTY\6TX1_UNDERFLOW\7RX1_FULL\11TX2_EMPTY" \ "\12TX1_UNDERFLOW\13RX2_FULL\15TX3_EMPTY\16TX3_UNDERFLOW" \ "\17RX3_FULL\22EOW" #define CONFBITS \ "\020\1PHA\2POL\7EPOL\17DMAW\20DMAR\21DPE0\22DPE1\23IS" \ "\24TURBO\25FORCE\30SBE\31SBPOL\34FFEW\35FFER\36CLKG" #define STATBITS \ "\020\1RXS\2TXS\3EOT\4TXFFE\5TXFFF\6RXFFE\7RXFFFF" #define MODULCTRLBITS \ "\020\1SINGLE\2NOSPIEN\3SLAVE\4SYST\10MOA\11FDAA" #define CTRLBITS \ "\020\1ENABLED" static void ti_spi_printr(device_t dev) { int clk, conf, ctrl, div, i, j, wl; struct ti_spi_softc *sc; uint32_t reg; sc = device_get_softc(dev); reg = TI_SPI_READ(sc, MCSPI_SYSCONFIG); device_printf(dev, "SYSCONFIG: %#x\n", reg); reg = TI_SPI_READ(sc, MCSPI_SYSSTATUS); device_printf(dev, "SYSSTATUS: %#x\n", reg); reg = TI_SPI_READ(sc, MCSPI_IRQSTATUS); device_printf(dev, "IRQSTATUS: 0x%b\n", reg, IRQSTATUSBITS); reg = TI_SPI_READ(sc, MCSPI_IRQENABLE); device_printf(dev, "IRQENABLE: 0x%b\n", reg, IRQSTATUSBITS); reg = TI_SPI_READ(sc, MCSPI_MODULCTRL); device_printf(dev, "MODULCTRL: 0x%b\n", reg, MODULCTRLBITS); for (i = 0; i < sc->sc_numcs; i++) { ctrl = TI_SPI_READ(sc, MCSPI_CTRL_CH(i)); conf = TI_SPI_READ(sc, MCSPI_CONF_CH(i)); device_printf(dev, "CH%dCONF: 0x%b\n", i, conf, CONFBITS); if (conf & MCSPI_CONF_CLKG) { div = (conf >> MCSPI_CONF_CLK_SHIFT) & MCSPI_CONF_CLK_MSK; div |= ((ctrl >> MCSPI_CTRL_EXTCLK_SHIFT) & MCSPI_CTRL_EXTCLK_MSK) << 4; } else { div = 1; j = (conf >> MCSPI_CONF_CLK_SHIFT) & MCSPI_CONF_CLK_MSK; while (j-- > 0) div <<= 1; } clk = TI_SPI_GCLK / div; wl = ((conf >> MCSPI_CONF_WL_SHIFT) & MCSPI_CONF_WL_MSK) + 1; device_printf(dev, "wordlen: %-2d clock: %d\n", wl, clk); reg = TI_SPI_READ(sc, MCSPI_STAT_CH(i)); device_printf(dev, "CH%dSTAT: 0x%b\n", i, reg, STATBITS); device_printf(dev, "CH%dCTRL: 0x%b\n", i, ctrl, CTRLBITS); } reg = TI_SPI_READ(sc, MCSPI_XFERLEVEL); device_printf(dev, "XFERLEVEL: %#x\n", reg); } #endif static void ti_spi_set_clock(struct ti_spi_softc *sc, int ch, int freq) { uint32_t clkdiv, conf, div, extclk, reg; clkdiv = TI_SPI_GCLK / freq; if (clkdiv > MCSPI_EXTCLK_MSK) { extclk = 0; clkdiv = 0; div = 1; while (TI_SPI_GCLK / div > freq && clkdiv <= 0xf) { clkdiv++; div <<= 1; } conf = clkdiv << MCSPI_CONF_CLK_SHIFT; } else { extclk = clkdiv >> 4; clkdiv &= MCSPI_CONF_CLK_MSK; conf = MCSPI_CONF_CLKG | clkdiv << MCSPI_CONF_CLK_SHIFT; } reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(ch)); reg &= ~(MCSPI_CTRL_EXTCLK_MSK << MCSPI_CTRL_EXTCLK_SHIFT); reg |= extclk << MCSPI_CTRL_EXTCLK_SHIFT; TI_SPI_WRITE(sc, MCSPI_CTRL_CH(ch), reg); reg = TI_SPI_READ(sc, MCSPI_CONF_CH(ch)); reg &= ~(MCSPI_CONF_CLKG | MCSPI_CONF_CLK_MSK << MCSPI_CONF_CLK_SHIFT); TI_SPI_WRITE(sc, MCSPI_CONF_CH(ch), reg | conf); } static int ti_spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "ti,omap4-mcspi")) return (ENXIO); device_set_desc(dev, "TI McSPI controller"); return (BUS_PROBE_DEFAULT); } static int ti_spi_attach(device_t dev) { int clk_id, err, i, rid, timeout; struct ti_spi_softc *sc; uint32_t rev; sc = device_get_softc(dev); sc->sc_dev = dev; /* * Get the MMCHS device id from FDT. If it's not there use the newbus * unit number (which will work as long as the devices are in order and * none are skipped in the fdt). Note that this is a property we made * up and added in freebsd, it doesn't exist in the published bindings. */ clk_id = ti_hwmods_get_clock(dev); if (clk_id == INVALID_CLK_IDENT) { device_printf(dev, "failed to get clock based on hwmods property\n"); return (EINVAL); } /* Activate the McSPI module. */ err = ti_prcm_clk_enable(clk_id); if (err) { device_printf(dev, "Error: failed to activate source clock\n"); return (err); } /* Get the number of available channels. */ if ((OF_getencprop(ofw_bus_get_node(dev), "ti,spi-num-cs", &sc->sc_numcs, sizeof(sc->sc_numcs))) <= 0) { sc->sc_numcs = 2; } rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "cannot allocate memory window\n"); return (ENXIO); } sc->sc_bst = rman_get_bustag(sc->sc_mem_res); sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); rid = 0; sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (!sc->sc_irq_res) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); device_printf(dev, "cannot allocate interrupt\n"); return (ENXIO); } /* Hook up our interrupt handler. */ if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, ti_spi_intr, sc, &sc->sc_intrhand)) { bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); device_printf(dev, "cannot setup the interrupt handler\n"); return (ENXIO); } mtx_init(&sc->sc_mtx, "ti_spi", NULL, MTX_DEF); /* Issue a softreset to the controller */ TI_SPI_WRITE(sc, MCSPI_SYSCONFIG, MCSPI_SYSCONFIG_SOFTRESET); timeout = 1000; while (!(TI_SPI_READ(sc, MCSPI_SYSSTATUS) & MCSPI_SYSSTATUS_RESETDONE)) { if (--timeout == 0) { device_printf(dev, "Error: Controller reset operation timed out\n"); ti_spi_detach(dev); return (ENXIO); } DELAY(100); } /* Print the McSPI module revision. */ rev = TI_SPI_READ(sc, MCSPI_REVISION); device_printf(dev, "scheme: %#x func: %#x rtl: %d rev: %d.%d custom rev: %d\n", (rev >> MCSPI_REVISION_SCHEME_SHIFT) & MCSPI_REVISION_SCHEME_MSK, (rev >> MCSPI_REVISION_FUNC_SHIFT) & MCSPI_REVISION_FUNC_MSK, (rev >> MCSPI_REVISION_RTL_SHIFT) & MCSPI_REVISION_RTL_MSK, (rev >> MCSPI_REVISION_MAJOR_SHIFT) & MCSPI_REVISION_MAJOR_MSK, (rev >> MCSPI_REVISION_MINOR_SHIFT) & MCSPI_REVISION_MINOR_MSK, (rev >> MCSPI_REVISION_CUSTOM_SHIFT) & MCSPI_REVISION_CUSTOM_MSK); /* Set Master mode, single channel. */ TI_SPI_WRITE(sc, MCSPI_MODULCTRL, MCSPI_MODULCTRL_SINGLE); /* Clear pending interrupts and disable interrupts. */ TI_SPI_WRITE(sc, MCSPI_IRQENABLE, 0x0); TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, 0xffff); for (i = 0; i < sc->sc_numcs; i++) { /* * Default to SPI mode 0, CS active low, 8 bits word length and * 500kHz clock. */ TI_SPI_WRITE(sc, MCSPI_CONF_CH(i), MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL | (8 - 1) << MCSPI_CONF_WL_SHIFT); /* Set initial clock - 500kHz. */ ti_spi_set_clock(sc, i, 500000); } #ifdef TI_SPI_DEBUG ti_spi_printr(dev); #endif device_add_child(dev, "spibus", -1); return (bus_generic_attach(dev)); } static int ti_spi_detach(device_t dev) { struct ti_spi_softc *sc; sc = device_get_softc(dev); /* Clear pending interrupts and disable interrupts. */ TI_SPI_WRITE(sc, MCSPI_IRQENABLE, 0); TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, 0xffff); /* Reset controller. */ TI_SPI_WRITE(sc, MCSPI_SYSCONFIG, MCSPI_SYSCONFIG_SOFTRESET); bus_generic_detach(dev); mtx_destroy(&sc->sc_mtx); if (sc->sc_intrhand) bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); if (sc->sc_irq_res) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (0); } static int ti_spi_fill_fifo(struct ti_spi_softc *sc) { int bytes, timeout; struct spi_command *cmd; uint32_t written; uint8_t *data; cmd = sc->sc_cmd; bytes = min(sc->sc_len - sc->sc_written, sc->sc_fifolvl); while (bytes-- > 0) { data = (uint8_t *)cmd->tx_cmd; written = sc->sc_written++; if (written >= cmd->tx_cmd_sz) { data = (uint8_t *)cmd->tx_data; written -= cmd->tx_cmd_sz; } if (sc->sc_fifolvl == 1) { /* FIFO disabled. */ timeout = 1000; while (--timeout > 0 && (TI_SPI_READ(sc, MCSPI_STAT_CH(sc->sc_cs)) & MCSPI_STAT_TXS) == 0) { DELAY(100); } if (timeout == 0) return (-1); } TI_SPI_WRITE(sc, MCSPI_TX_CH(sc->sc_cs), data[written]); } return (0); } static int ti_spi_drain_fifo(struct ti_spi_softc *sc) { int bytes, timeout; struct spi_command *cmd; uint32_t read; uint8_t *data; cmd = sc->sc_cmd; bytes = min(sc->sc_len - sc->sc_read, sc->sc_fifolvl); while (bytes-- > 0) { data = (uint8_t *)cmd->rx_cmd; read = sc->sc_read++; if (read >= cmd->rx_cmd_sz) { data = (uint8_t *)cmd->rx_data; read -= cmd->rx_cmd_sz; } if (sc->sc_fifolvl == 1) { /* FIFO disabled. */ timeout = 1000; while (--timeout > 0 && (TI_SPI_READ(sc, MCSPI_STAT_CH(sc->sc_cs)) & MCSPI_STAT_RXS) == 0) { DELAY(100); } if (timeout == 0) return (-1); } data[read] = TI_SPI_READ(sc, MCSPI_RX_CH(sc->sc_cs)); } return (0); } static void ti_spi_intr(void *arg) { int eow; struct ti_spi_softc *sc; uint32_t status; eow = 0; sc = (struct ti_spi_softc *)arg; TI_SPI_LOCK(sc); status = TI_SPI_READ(sc, MCSPI_IRQSTATUS); /* * No new TX_empty or RX_full event will be asserted while the CPU has * not performed the number of writes or reads defined by * MCSPI_XFERLEVEL[AEL] and MCSPI_XFERLEVEL[AFL]. It is responsibility * of CPU perform the right number of writes and reads. */ if (status & MCSPI_IRQ_TX0_EMPTY) ti_spi_fill_fifo(sc); if (status & MCSPI_IRQ_RX0_FULL) ti_spi_drain_fifo(sc); if (status & MCSPI_IRQ_EOW) eow = 1; /* Clear interrupt status. */ TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, status); /* Check for end of transfer. */ if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len) { sc->sc_flags |= TI_SPI_DONE; wakeup(sc->sc_dev); } TI_SPI_UNLOCK(sc); } static int ti_spi_pio_transfer(struct ti_spi_softc *sc) { while (sc->sc_len - sc->sc_written > 0) { if (ti_spi_fill_fifo(sc) == -1) return (EIO); if (ti_spi_drain_fifo(sc) == -1) return (EIO); } return (0); } static int ti_spi_gcd(int a, int b) { int m; while ((m = a % b) != 0) { a = b; b = m; } return (b); } static int ti_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { int err; struct ti_spi_softc *sc; uint32_t reg, cs; sc = device_get_softc(dev); KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("TX/RX command sizes should be equal")); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("TX/RX data sizes should be equal")); /* Get the proper chip select for this child. */ spibus_get_cs(child, &cs); + + cs &= ~SPIBUS_CS_HIGH; + if (cs > sc->sc_numcs) { device_printf(dev, "Invalid chip select %d requested by %s\n", cs, device_get_nameunit(child)); return (EINVAL); } TI_SPI_LOCK(sc); /* If the controller is in use wait until it is available. */ while (sc->sc_flags & TI_SPI_BUSY) mtx_sleep(dev, &sc->sc_mtx, 0, "ti_spi", 0); /* Now we have control over SPI controller. */ sc->sc_flags = TI_SPI_BUSY; /* Save the SPI command data. */ sc->sc_cs = cs; sc->sc_cmd = cmd; sc->sc_read = 0; sc->sc_written = 0; sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz; sc->sc_fifolvl = ti_spi_gcd(sc->sc_len, TI_SPI_FIFOSZ); if (sc->sc_fifolvl < 2 || sc->sc_len > 0xffff) sc->sc_fifolvl = 1; /* FIFO disabled. */ /* Disable FIFO for now. */ sc->sc_fifolvl = 1; /* Use a safe clock - 500kHz. */ ti_spi_set_clock(sc, sc->sc_cs, 500000); /* Disable the FIFO. */ TI_SPI_WRITE(sc, MCSPI_XFERLEVEL, 0); /* 8 bits word, d0 miso, d1 mosi, mode 0 and CS active low. */ reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); reg &= ~(MCSPI_CONF_FFER | MCSPI_CONF_FFEW | MCSPI_CONF_SBPOL | MCSPI_CONF_SBE | MCSPI_CONF_TURBO | MCSPI_CONF_IS | MCSPI_CONF_DPE1 | MCSPI_CONF_DPE0 | MCSPI_CONF_DMAR | MCSPI_CONF_DMAW | MCSPI_CONF_EPOL); reg |= MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL | MCSPI_CONF_WL8BITS; TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); #if 0 /* Enable channel interrupts. */ reg = TI_SPI_READ(sc, MCSPI_IRQENABLE); reg |= 0xf; TI_SPI_WRITE(sc, MCSPI_IRQENABLE, reg); #endif /* Start the transfer. */ reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(sc->sc_cs)); TI_SPI_WRITE(sc, MCSPI_CTRL_CH(sc->sc_cs), reg | MCSPI_CTRL_ENABLE); /* Force CS on. */ reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg |= MCSPI_CONF_FORCE); err = 0; if (sc->sc_fifolvl == 1) err = ti_spi_pio_transfer(sc); /* Force CS off. */ reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); reg &= ~MCSPI_CONF_FORCE; TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); /* Disable IRQs. */ reg = TI_SPI_READ(sc, MCSPI_IRQENABLE); reg &= ~0xf; TI_SPI_WRITE(sc, MCSPI_IRQENABLE, reg); TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, 0xf); /* Disable the SPI channel. */ reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(sc->sc_cs)); reg &= ~MCSPI_CTRL_ENABLE; TI_SPI_WRITE(sc, MCSPI_CTRL_CH(sc->sc_cs), reg); /* Disable FIFO. */ reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); reg &= ~(MCSPI_CONF_FFER | MCSPI_CONF_FFEW); TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); /* Release the controller and wakeup the next thread waiting for it. */ sc->sc_flags = 0; wakeup_one(dev); TI_SPI_UNLOCK(sc); return (err); } static phandle_t ti_spi_get_node(device_t bus, device_t dev) { /* Share controller node with spibus. */ return (ofw_bus_get_node(bus)); } static device_method_t ti_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ti_spi_probe), DEVMETHOD(device_attach, ti_spi_attach), DEVMETHOD(device_detach, ti_spi_detach), /* SPI interface */ DEVMETHOD(spibus_transfer, ti_spi_transfer), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, ti_spi_get_node), DEVMETHOD_END }; static devclass_t ti_spi_devclass; static driver_t ti_spi_driver = { "spi", ti_spi_methods, sizeof(struct ti_spi_softc), }; DRIVER_MODULE(ti_spi, simplebus, ti_spi_driver, ti_spi_devclass, 0, 0); Index: head/sys/dev/spibus/ofw_spibus.c =================================================================== --- head/sys/dev/spibus/ofw_spibus.c (revision 310228) +++ head/sys/dev/spibus/ofw_spibus.c (revision 310229) @@ -1,201 +1,221 @@ /*- * Copyright (c) 2009, Nathan Whitehorn * Copyright (c) 2013 The FreeBSD Foundation * All rights reserved. * * Portions of this software were developed by Oleksandr Rybalko * under sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" struct ofw_spibus_devinfo { struct spibus_ivar opd_dinfo; struct ofw_bus_devinfo opd_obdinfo; }; /* Methods */ static device_probe_t ofw_spibus_probe; static device_attach_t ofw_spibus_attach; static device_t ofw_spibus_add_child(device_t dev, u_int order, const char *name, int unit); static const struct ofw_bus_devinfo *ofw_spibus_get_devinfo(device_t bus, device_t dev); static int ofw_spibus_probe(device_t dev) { if (ofw_bus_get_node(dev) == -1) return (ENXIO); device_set_desc(dev, "OFW SPI bus"); return (0); } static int ofw_spibus_attach(device_t dev) { struct spibus_softc *sc = device_get_softc(dev); struct ofw_spibus_devinfo *dinfo; phandle_t child; pcell_t clock, paddr; device_t childdev; + uint32_t mode = SPIBUS_MODE_NONE; sc->dev = dev; bus_generic_probe(dev); bus_enumerate_hinted_children(dev); /* * Attach those children represented in the device tree. */ for (child = OF_child(ofw_bus_get_node(dev)); child != 0; child = OF_peer(child)) { /* * Try to get the CS number first from the spi-chipselect * property, then try the reg property. */ if (OF_getencprop(child, "spi-chipselect", &paddr, sizeof(paddr)) == -1) { if (OF_getencprop(child, "reg", &paddr, sizeof(paddr)) == -1) continue; } /* + * Try to get the cpol/cpha mode + */ + if (OF_hasprop(child, "spi-cpol")) + mode = SPIBUS_MODE_CPOL; + if (OF_hasprop(child, "spi-cpha")) { + if (mode == SPIBUS_MODE_CPOL) + mode = SPIBUS_MODE_CPOL_CPHA; + else + mode = SPIBUS_MODE_CPHA; + } + + /* + * Try to get the CS polarity + */ + if (OF_hasprop(child, "spi-cs-high")) + paddr |= SPIBUS_CS_HIGH; + + /* * Get the maximum clock frequency for device, zero means * use the default bus speed. */ if (OF_getencprop(child, "spi-max-frequency", &clock, sizeof(clock)) == -1) clock = 0; /* * Now set up the SPI and OFW bus layer devinfo and add it * to the bus. */ dinfo = malloc(sizeof(struct ofw_spibus_devinfo), M_DEVBUF, M_NOWAIT | M_ZERO); if (dinfo == NULL) continue; dinfo->opd_dinfo.cs = paddr; dinfo->opd_dinfo.clock = clock; + dinfo->opd_dinfo.mode = mode; if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, child) != 0) { free(dinfo, M_DEVBUF); continue; } childdev = device_add_child(dev, NULL, -1); device_set_ivars(childdev, dinfo); } return (bus_generic_attach(dev)); } static device_t ofw_spibus_add_child(device_t dev, u_int order, const char *name, int unit) { device_t child; struct ofw_spibus_devinfo *devi; child = device_add_child_ordered(dev, order, name, unit); if (child == NULL) return (child); devi = malloc(sizeof(struct ofw_spibus_devinfo), M_DEVBUF, M_NOWAIT | M_ZERO); if (devi == NULL) { device_delete_child(dev, child); return (0); } /* * NULL all the OFW-related parts of the ivars for non-OFW * children. */ devi->opd_obdinfo.obd_node = -1; devi->opd_obdinfo.obd_name = NULL; devi->opd_obdinfo.obd_compat = NULL; devi->opd_obdinfo.obd_type = NULL; devi->opd_obdinfo.obd_model = NULL; device_set_ivars(child, devi); return (child); } static const struct ofw_bus_devinfo * ofw_spibus_get_devinfo(device_t bus, device_t dev) { struct ofw_spibus_devinfo *dinfo; dinfo = device_get_ivars(dev); return (&dinfo->opd_obdinfo); } static device_method_t ofw_spibus_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ofw_spibus_probe), DEVMETHOD(device_attach, ofw_spibus_attach), /* Bus interface */ DEVMETHOD(bus_child_pnpinfo_str, ofw_bus_gen_child_pnpinfo_str), DEVMETHOD(bus_add_child, ofw_spibus_add_child), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_devinfo, ofw_spibus_get_devinfo), DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), DEVMETHOD_END }; static devclass_t ofwspibus_devclass; DEFINE_CLASS_1(spibus, ofw_spibus_driver, ofw_spibus_methods, sizeof(struct spibus_softc), spibus_driver); DRIVER_MODULE(ofw_spibus, spi, ofw_spibus_driver, ofwspibus_devclass, 0, 0); MODULE_VERSION(ofw_spibus, 1); MODULE_DEPEND(ofw_spibus, spibus, 1, 1, 1); Index: head/sys/dev/spibus/spibusvar.h =================================================================== --- head/sys/dev/spibus/spibusvar.h (revision 310228) +++ head/sys/dev/spibus/spibusvar.h (revision 310229) @@ -1,68 +1,70 @@ /*- * Copyright (c) 2006 M. Warner Losh * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #define SPIBUS_IVAR(d) (struct spibus_ivar *) device_get_ivars(d) #define SPIBUS_SOFTC(d) (struct spibus_softc *) device_get_softc(d) struct spibus_softc { device_t dev; }; #define SPIBUS_MODE_NONE 0 #define SPIBUS_MODE_CPHA 1 #define SPIBUS_MODE_CPOL 2 #define SPIBUS_MODE_CPOL_CPHA 3 struct spibus_ivar { uint32_t cs; uint32_t mode; uint32_t clock; }; +#define SPIBUS_CS_HIGH (1U << 31) + enum { SPIBUS_IVAR_CS, /* chip select that we're on */ SPIBUS_IVAR_MODE, /* SPI mode (0-3) */ SPIBUS_IVAR_CLOCK, /* maximum clock freq for device */ }; #define SPIBUS_ACCESSOR(A, B, T) \ static inline int \ spibus_get_ ## A(device_t dev, T *t) \ { \ return BUS_READ_IVAR(device_get_parent(dev), dev, \ SPIBUS_IVAR_ ## B, (uintptr_t *) t); \ } SPIBUS_ACCESSOR(cs, CS, uint32_t) SPIBUS_ACCESSOR(mode, MODE, uint32_t) SPIBUS_ACCESSOR(clock, CLOCK, uint32_t) extern driver_t spibus_driver; extern devclass_t spibus_devclass; Index: head/sys/dev/xilinx/axi_quad_spi.c =================================================================== --- head/sys/dev/xilinx/axi_quad_spi.c (revision 310228) +++ head/sys/dev/xilinx/axi_quad_spi.c (revision 310229) @@ -1,233 +1,235 @@ /*- * Copyright (c) 2016 Ruslan Bukin * All rights reserved. * * Portions of this software were developed by SRI International and the * University of Cambridge Computer Laboratory under DARPA/AFRL contract * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. * * Portions of this software were developed by the University of Cambridge * Computer Laboratory as part of the CTSRD Project, with support from the * UK Higher Education Innovation Fund (HEIF). * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Xilinx AXI_QUAD_SPI */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" #include #include #include #include #include #include #include #define READ4(_sc, _reg) \ bus_space_read_4(_sc->bst, _sc->bsh, _reg) #define WRITE4(_sc, _reg, _val) \ bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val) #define SPI_SRR 0x40 /* Software reset register */ #define SRR_RESET 0x0A /* The only reset value */ #define SPI_CR 0x60 /* Control register */ #define CR_LSB_FIRST (1 << 9) /* LSB first */ #define CR_MASTER_TI (1 << 8) /* Master Transaction Inhibit */ #define CR_MSS (1 << 7) /* Manual Slave Select */ #define CR_RST_RX (1 << 6) /* RX FIFO Reset */ #define CR_RST_TX (1 << 5) /* TX FIFO Reset */ #define CR_CPHA (1 << 4) /* Clock phase */ #define CR_CPOL (1 << 3) /* Clock polarity */ #define CR_MASTER (1 << 2) /* Master (SPI master mode) */ #define CR_SPE (1 << 1) /* SPI system enable */ #define CR_LOOP (1 << 0) /* Local loopback mode */ #define SPI_SR 0x64 /* Status register */ #define SR_TX_FULL (1 << 3) /* Transmit full */ #define SR_TX_EMPTY (1 << 2) /* Transmit empty */ #define SR_RX_FULL (1 << 1) /* Receive full */ #define SR_RX_EMPTY (1 << 0) /* Receive empty */ #define SPI_DTR 0x68 /* Data transmit register */ #define SPI_DRR 0x6C /* Data receive register */ #define SPI_SSR 0x70 /* Slave select register */ #define SPI_TFOR 0x74 /* Transmit FIFO Occupancy Register */ #define SPI_RFOR 0x78 /* Receive FIFO Occupancy Register */ #define SPI_DGIER 0x1C /* Device global interrupt enable register */ #define SPI_IPISR 0x20 /* IP interrupt status register */ #define SPI_IPIER 0x28 /* IP interrupt enable register */ struct spi_softc { struct resource *res[1]; bus_space_tag_t bst; bus_space_handle_t bsh; void *ih; }; static struct resource_spec spi_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { -1, 0 } }; static int spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "xlnx,xps-spi-3.2")) return (ENXIO); device_set_desc(dev, "Xilinx Quad SPI"); return (BUS_PROBE_DEFAULT); } static int spi_attach(device_t dev) { struct spi_softc *sc; uint32_t reg; sc = device_get_softc(dev); if (bus_alloc_resources(dev, spi_spec, sc->res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } /* Memory interface */ sc->bst = rman_get_bustag(sc->res[0]); sc->bsh = rman_get_bushandle(sc->res[0]); /* Reset */ WRITE4(sc, SPI_SRR, SRR_RESET); DELAY(1000); reg = (CR_MASTER | CR_MSS | CR_RST_RX | CR_RST_TX); WRITE4(sc, SPI_CR, reg); WRITE4(sc, SPI_DGIER, 0); /* Disable interrupts */ reg = (CR_MASTER | CR_MSS | CR_SPE); WRITE4(sc, SPI_CR, reg); device_add_child(dev, "spibus", 0); return (bus_generic_attach(dev)); } static int spi_txrx(struct spi_softc *sc, uint8_t *out_buf, uint8_t *in_buf, int bufsz, int cs) { uint32_t data; uint32_t i; for (i = 0; i < bufsz; i++) { WRITE4(sc, SPI_DTR, out_buf[i]); while(!(READ4(sc, SPI_SR) & SR_TX_EMPTY)) continue; data = READ4(sc, SPI_DRR); if (in_buf) in_buf[i] = (data & 0xff); } return (0); } static int spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct spi_softc *sc; uint32_t reg; uint32_t cs; sc = device_get_softc(dev); KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("%s: TX/RX command sizes should be equal", __func__)); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("%s: TX/RX data sizes should be equal", __func__)); /* get the proper chip select */ spibus_get_cs(child, &cs); + cs &= ~SPIBUS_CS_HIGH; + /* Assert CS */ reg = READ4(sc, SPI_SSR); reg &= ~(1 << cs); WRITE4(sc, SPI_SSR, reg); /* Command */ spi_txrx(sc, cmd->tx_cmd, cmd->rx_cmd, cmd->tx_cmd_sz, cs); /* Data */ spi_txrx(sc, cmd->tx_data, cmd->rx_data, cmd->tx_data_sz, cs); /* Deassert CS */ reg = READ4(sc, SPI_SSR); reg |= (1 << cs); WRITE4(sc, SPI_SSR, reg); return (0); } static device_method_t spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, spi_probe), DEVMETHOD(device_attach, spi_attach), /* SPI interface */ DEVMETHOD(spibus_transfer, spi_transfer), DEVMETHOD_END }; static driver_t spi_driver = { "spi", spi_methods, sizeof(struct spi_softc), }; static devclass_t spi_devclass; DRIVER_MODULE(spi, simplebus, spi_driver, spi_devclass, 0, 0); Index: head/sys/mips/atheros/ar531x/ar5315_spi.c =================================================================== --- head/sys/mips/atheros/ar531x/ar5315_spi.c (revision 310228) +++ head/sys/mips/atheros/ar531x/ar5315_spi.c (revision 310229) @@ -1,288 +1,290 @@ /*- * Copyright (c) 2016, Hiroki Mori * Copyright (c) 2009, Oleksandr Tymoshenko * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" #include #include #undef AR531X_SPI_DEBUG #ifdef AR531X_SPI_DEBUG #define dprintf printf #else #define dprintf(x, arg...) #endif /* * register space access macros */ #define SPI_WRITE(sc, reg, val) do { \ bus_write_4(sc->sc_mem_res, (reg), (val)); \ } while (0) #define SPI_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg)) #define SPI_SET_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits)) #define SPI_CLEAR_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits)) struct ar5315_spi_softc { device_t sc_dev; struct resource *sc_mem_res; uint32_t sc_reg_ctrl; uint32_t sc_debug; }; static void ar5315_spi_attach_sysctl(device_t dev) { struct ar5315_spi_softc *sc; struct sysctl_ctx_list *ctx; struct sysctl_oid *tree; sc = device_get_softc(dev); ctx = device_get_sysctl_ctx(dev); tree = device_get_sysctl_tree(dev); SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "debug", CTLFLAG_RW, &sc->sc_debug, 0, "ar5315_spi debugging flags"); } static int ar5315_spi_probe(device_t dev) { device_set_desc(dev, "AR5315 SPI"); return (0); } static int ar5315_spi_attach(device_t dev) { struct ar5315_spi_softc *sc = device_get_softc(dev); int rid; sc->sc_dev = dev; rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "Could not map memory\n"); return (ENXIO); } device_add_child(dev, "spibus", -1); ar5315_spi_attach_sysctl(dev); return (bus_generic_attach(dev)); } static void ar5315_spi_chip_activate(struct ar5315_spi_softc *sc, int cs) { } static void ar5315_spi_chip_deactivate(struct ar5315_spi_softc *sc, int cs) { } static int ar5315_spi_get_block(off_t offset, caddr_t data, off_t count) { int i; for(i = 0; i < count / 4; ++i) { *((uint32_t *)data + i) = ATH_READ_REG(AR5315_MEM1_BASE + offset + i * 4); } // printf("ar5315_spi_get_blockr: %x %x %x\n", // (int)offset, (int)count, *(uint32_t *)data); return (0); } static int ar5315_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct ar5315_spi_softc *sc; uint8_t *buf_in, *buf_out; int lin, lout; uint32_t ctl, cnt, op, rdat, cs; int i, j; sc = device_get_softc(dev); if (sc->sc_debug & 0x8000) printf("ar5315_spi_transfer: CMD "); spibus_get_cs(child, &cs); + cs &= ~SPIBUS_CS_HIGH; + /* Open SPI controller interface */ ar5315_spi_chip_activate(sc, cs); do { ctl = SPI_READ(sc, ARSPI_REG_CTL); } while (ctl & ARSPI_CTL_BUSY); /* * Transfer command */ buf_out = (uint8_t *)cmd->tx_cmd; op = buf_out[0]; if(op == 0x0b) { int offset = buf_out[1] << 16 | buf_out[2] << 8 | buf_out[3]; ar5315_spi_get_block(offset, cmd->rx_data, cmd->rx_data_sz); return (0); } do { ctl = SPI_READ(sc, ARSPI_REG_CTL); } while (ctl & ARSPI_CTL_BUSY); if (sc->sc_debug & 0x8000) { printf("%08x ", op); printf("tx_cmd_sz=%d rx_cmd_sz=%d ", cmd->tx_cmd_sz, cmd->rx_cmd_sz); if(cmd->tx_cmd_sz != 1) { printf("%08x ", *((uint32_t *)cmd->tx_cmd)); printf("%08x ", *((uint32_t *)cmd->tx_cmd + 1)); } } SPI_WRITE(sc, ARSPI_REG_OPCODE, op); /* clear all of the tx and rx bits */ ctl &= ~(ARSPI_CTL_TXCNT_MASK | ARSPI_CTL_RXCNT_MASK); /* now set txcnt */ cnt = 1; ctl |= (cnt << ARSPI_CTL_TXCNT_SHIFT); cnt = 24; /* now set txcnt */ if(cmd->rx_cmd_sz < 24) cnt = cmd->rx_cmd_sz; ctl |= (cnt << ARSPI_CTL_RXCNT_SHIFT); ctl |= ARSPI_CTL_START; SPI_WRITE(sc, ARSPI_REG_CTL, ctl); if(op == 0x0b) SPI_WRITE(sc, ARSPI_REG_DATA, 0); if (sc->sc_debug & 0x8000) printf("\nDATA "); /* * Receive/transmit data (depends on command) */ // buf_out = (uint8_t *)cmd->tx_data; buf_in = (uint8_t *)cmd->rx_cmd; // lout = cmd->tx_data_sz; lin = cmd->rx_cmd_sz; if (sc->sc_debug & 0x8000) printf("t%d r%d ", lout, lin); for(i = 0; i <= (cnt - 1) / 4; ++i) { do { ctl = SPI_READ(sc, ARSPI_REG_CTL); } while (ctl & ARSPI_CTL_BUSY); rdat = SPI_READ(sc, ARSPI_REG_DATA); if (sc->sc_debug & 0x8000) printf("I%08x ", rdat); for(j = 0; j < 4; ++j) { buf_in[i * 4 + j + 1] = 0xff & (rdat >> (8 * j)); if(i * 4 + j + 2 == cnt) break; } } ar5315_spi_chip_deactivate(sc, cs); /* * Close SPI controller interface, restore flash memory mapped access. */ if (sc->sc_debug & 0x8000) printf("\n"); return (0); } static int ar5315_spi_detach(device_t dev) { struct ar5315_spi_softc *sc = device_get_softc(dev); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (0); } static device_method_t ar5315_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ar5315_spi_probe), DEVMETHOD(device_attach, ar5315_spi_attach), DEVMETHOD(device_detach, ar5315_spi_detach), DEVMETHOD(spibus_transfer, ar5315_spi_transfer), // DEVMETHOD(spibus_get_block, ar5315_spi_get_block), DEVMETHOD_END }; static driver_t ar5315_spi_driver = { "spi", ar5315_spi_methods, sizeof(struct ar5315_spi_softc), }; static devclass_t ar5315_spi_devclass; DRIVER_MODULE(ar5315_spi, nexus, ar5315_spi_driver, ar5315_spi_devclass, 0, 0); Index: head/sys/mips/atheros/ar71xx_spi.c =================================================================== --- head/sys/mips/atheros/ar71xx_spi.c (revision 310228) +++ head/sys/mips/atheros/ar71xx_spi.c (revision 310229) @@ -1,293 +1,295 @@ /*- * Copyright (c) 2009, Oleksandr Tymoshenko * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" #include #undef AR71XX_SPI_DEBUG #ifdef AR71XX_SPI_DEBUG #define dprintf printf #else #define dprintf(x, arg...) #endif /* * register space access macros */ #define SPI_BARRIER_WRITE(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \ BUS_SPACE_BARRIER_WRITE) #define SPI_BARRIER_READ(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \ BUS_SPACE_BARRIER_READ) #define SPI_BARRIER_RW(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \ BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) #define SPI_WRITE(sc, reg, val) do { \ bus_write_4(sc->sc_mem_res, (reg), (val)); \ } while (0) #define SPI_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg)) #define SPI_SET_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits)) #define SPI_CLEAR_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits)) struct ar71xx_spi_softc { device_t sc_dev; struct resource *sc_mem_res; uint32_t sc_reg_ctrl; }; static int ar71xx_spi_probe(device_t dev) { device_set_desc(dev, "AR71XX SPI"); return (BUS_PROBE_NOWILDCARD); } static int ar71xx_spi_attach(device_t dev) { struct ar71xx_spi_softc *sc = device_get_softc(dev); int rid; sc->sc_dev = dev; rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "Could not map memory\n"); return (ENXIO); } SPI_WRITE(sc, AR71XX_SPI_FS, 1); /* Flush out read before reading the control register */ SPI_BARRIER_WRITE(sc); sc->sc_reg_ctrl = SPI_READ(sc, AR71XX_SPI_CTRL); /* * XXX TODO: document what the SPI control register does. */ SPI_WRITE(sc, AR71XX_SPI_CTRL, 0x43); /* * Ensure the config register write has gone out before configuring * the chip select mask. */ SPI_BARRIER_WRITE(sc); SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, SPI_IO_CTRL_CSMASK); /* * .. and ensure the write has gone out before continuing. */ SPI_BARRIER_WRITE(sc); device_add_child(dev, "spibus", -1); return (bus_generic_attach(dev)); } static void ar71xx_spi_chip_activate(struct ar71xx_spi_softc *sc, int cs) { uint32_t ioctrl = SPI_IO_CTRL_CSMASK; /* * Put respective CSx to low */ ioctrl &= ~(SPI_IO_CTRL_CS0 << cs); /* * Make sure any other writes have gone out to the * device before changing the chip select line; * then ensure that it has made it out to the device * before continuing. */ SPI_BARRIER_WRITE(sc); SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, ioctrl); SPI_BARRIER_WRITE(sc); } static void ar71xx_spi_chip_deactivate(struct ar71xx_spi_softc *sc, int cs) { /* * Put all CSx to high */ SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, SPI_IO_CTRL_CSMASK); } static uint8_t ar71xx_spi_txrx(struct ar71xx_spi_softc *sc, int cs, uint8_t data) { int bit; /* CS0 */ uint32_t ioctrl = SPI_IO_CTRL_CSMASK; /* * low-level for selected CS */ ioctrl &= ~(SPI_IO_CTRL_CS0 << cs); uint32_t iod, rds; for (bit = 7; bit >=0; bit--) { if (data & (1 << bit)) iod = ioctrl | SPI_IO_CTRL_DO; else iod = ioctrl & ~SPI_IO_CTRL_DO; SPI_BARRIER_WRITE(sc); SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod); SPI_BARRIER_WRITE(sc); SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod | SPI_IO_CTRL_CLK); } /* * Provide falling edge for connected device by clear clock bit. */ SPI_BARRIER_WRITE(sc); SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod); SPI_BARRIER_WRITE(sc); rds = SPI_READ(sc, AR71XX_SPI_RDS); return (rds & 0xff); } static int ar71xx_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct ar71xx_spi_softc *sc; uint32_t cs; uint8_t *buf_in, *buf_out; int i; sc = device_get_softc(dev); spibus_get_cs(child, &cs); + cs &= ~SPIBUS_CS_HIGH; + ar71xx_spi_chip_activate(sc, cs); KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("TX/RX command sizes should be equal")); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("TX/RX data sizes should be equal")); /* * Transfer command */ buf_out = (uint8_t *)cmd->tx_cmd; buf_in = (uint8_t *)cmd->rx_cmd; for (i = 0; i < cmd->tx_cmd_sz; i++) buf_in[i] = ar71xx_spi_txrx(sc, cs, buf_out[i]); /* * Receive/transmit data (depends on command) */ buf_out = (uint8_t *)cmd->tx_data; buf_in = (uint8_t *)cmd->rx_data; for (i = 0; i < cmd->tx_data_sz; i++) buf_in[i] = ar71xx_spi_txrx(sc, cs, buf_out[i]); ar71xx_spi_chip_deactivate(sc, cs); return (0); } static int ar71xx_spi_detach(device_t dev) { struct ar71xx_spi_softc *sc = device_get_softc(dev); /* * Ensure any other writes to the device are finished * before we tear down the SPI device. */ SPI_BARRIER_WRITE(sc); /* * Restore the control register; ensure it has hit the * hardware before continuing. */ SPI_WRITE(sc, AR71XX_SPI_CTRL, sc->sc_reg_ctrl); SPI_BARRIER_WRITE(sc); /* * And now, put the flash back into mapped IO mode and * ensure _that_ has completed before we finish up. */ SPI_WRITE(sc, AR71XX_SPI_FS, 0); SPI_BARRIER_WRITE(sc); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (0); } static device_method_t ar71xx_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ar71xx_spi_probe), DEVMETHOD(device_attach, ar71xx_spi_attach), DEVMETHOD(device_detach, ar71xx_spi_detach), DEVMETHOD(spibus_transfer, ar71xx_spi_transfer), {0, 0} }; static driver_t ar71xx_spi_driver = { "spi", ar71xx_spi_methods, sizeof(struct ar71xx_spi_softc), }; static devclass_t ar71xx_spi_devclass; DRIVER_MODULE(ar71xx_spi, nexus, ar71xx_spi_driver, ar71xx_spi_devclass, 0, 0); Index: head/sys/mips/mediatek/mtk_spi_v1.c =================================================================== --- head/sys/mips/mediatek/mtk_spi_v1.c (revision 310228) +++ head/sys/mips/mediatek/mtk_spi_v1.c (revision 310229) @@ -1,348 +1,350 @@ /*- * Copyright (c) 2009, Oleksandr Tymoshenko * Copyright (c) 2011, Aleksandr Rybalko * Copyright (c) 2013, Alexander A. Mityaev * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" #include "opt_platform.h" #include #include #include #include #include #undef MTK_SPI_DEBUG #ifdef MTK_SPI_DEBUG #define dprintf printf #else #define dprintf(x, arg...) #endif /* * register space access macros */ #define SPI_WRITE(sc, reg, val) do { \ bus_write_4(sc->sc_mem_res, (reg), (val)); \ } while (0) #define SPI_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg)) #define SPI_SET_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits)) #define SPI_CLEAR_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits)) struct mtk_spi_softc { device_t sc_dev; struct resource *sc_mem_res; }; static int mtk_spi_probe(device_t); static int mtk_spi_attach(device_t); static int mtk_spi_detach(device_t); static int mtk_spi_wait(struct mtk_spi_softc *); static void mtk_spi_chip_activate(struct mtk_spi_softc *); static void mtk_spi_chip_deactivate(struct mtk_spi_softc *); static uint8_t mtk_spi_txrx(struct mtk_spi_softc *, uint8_t *, int); static int mtk_spi_transfer(device_t, device_t, struct spi_command *); static phandle_t mtk_spi_get_node(device_t, device_t); static struct ofw_compat_data compat_data[] = { { "ralink,rt2880-spi", 1 }, { "ralink,rt3050-spi", 1 }, { "ralink,rt3352-spi", 1 }, { "ralink,rt3883-spi", 1 }, { "ralink,rt5350-spi", 1 }, { "ralink,mt7620a-spi", 1 }, { NULL, 0 } }; static int mtk_spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return(ENXIO); device_set_desc(dev, "MTK SPI Controller (v1)"); return (0); } static int mtk_spi_attach(device_t dev) { struct mtk_spi_softc *sc = device_get_softc(dev); int rid; sc->sc_dev = dev; rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "Could not map memory\n"); return (ENXIO); } if (mtk_spi_wait(sc)) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (EBUSY); } SPI_WRITE(sc, MTK_SPICFG, MSBFIRST | SPICLKPOL | TX_ON_CLK_FALL | SPI_CLK_DIV8); /* XXX: make it configurable */ /* * W25Q64CV max 104MHz, bus 120-192 MHz, so divide by 2. * Update: divide by 4, DEV2 to fast for flash. */ device_add_child(dev, "spibus", 0); return (bus_generic_attach(dev)); } static int mtk_spi_detach(device_t dev) { struct mtk_spi_softc *sc = device_get_softc(dev); SPI_SET_BITS(sc, MTK_SPICTL, HIZSMOSI | CS_HIGH); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (0); } static void mtk_spi_chip_activate(struct mtk_spi_softc *sc) { mtk_spi_wait(sc); /* * Put all CSx to low */ SPI_CLEAR_BITS(sc, MTK_SPICTL, CS_HIGH | HIZSMOSI); } static void mtk_spi_chip_deactivate(struct mtk_spi_softc *sc) { mtk_spi_wait(sc); /* * Put all CSx to high */ SPI_SET_BITS(sc, MTK_SPICTL, CS_HIGH | HIZSMOSI); } static int mtk_spi_wait(struct mtk_spi_softc *sc) { int i = 1000; while (i--) { if (!SPI_READ(sc, MTK_SPIBUSY)) break; } if (i == 0) { printf("busy\n"); return (1); } return (0); } static uint8_t mtk_spi_txrx(struct mtk_spi_softc *sc, uint8_t *data, int write) { if (mtk_spi_wait(sc)) return (EBUSY); if (write == MTK_SPI_WRITE) { SPI_WRITE(sc, MTK_SPIDATA, *data); SPI_SET_BITS(sc, MTK_SPICTL, START_WRITE); } else {/* MTK_SPI_READ */ SPI_SET_BITS(sc, MTK_SPICTL, START_READ); if (mtk_spi_wait(sc)) return (EBUSY); *data = SPI_READ(sc, MTK_SPIDATA) & 0xff; } return (0); } static int mtk_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct mtk_spi_softc *sc; uint8_t *buf, byte, *tx_buf; uint32_t cs; int i, sz, error = 0, write = 0; sc = device_get_softc(dev); spibus_get_cs(child, &cs); + cs &= ~SPIBUS_CS_HIGH; + if (cs != 0) /* Only 1 CS */ return (ENXIO); /* There is always a command to transfer. */ tx_buf = (uint8_t *)(cmd->tx_cmd); /* Perform some fixup because MTK dont support duplex SPI */ switch(tx_buf[0]) { case CMD_READ_IDENT: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 3; break; case CMD_ENTER_4B_MODE: case CMD_EXIT_4B_MODE: case CMD_WRITE_ENABLE: case CMD_WRITE_DISABLE: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 0; break; case CMD_READ_STATUS: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 1; break; case CMD_READ: case CMD_FAST_READ: cmd->rx_cmd_sz = cmd->tx_data_sz = 0; break; case CMD_SECTOR_ERASE: cmd->rx_cmd_sz = 0; break; case CMD_PAGE_PROGRAM: cmd->rx_cmd_sz = cmd->rx_data_sz = 0; break; } mtk_spi_chip_activate(sc); if (cmd->tx_cmd_sz + cmd->rx_cmd_sz) { buf = (uint8_t *)(cmd->rx_cmd); tx_buf = (uint8_t *)(cmd->tx_cmd); sz = cmd->tx_cmd_sz + cmd->rx_cmd_sz; for (i = 0; i < sz; i++) { if(i < cmd->tx_cmd_sz) { byte = tx_buf[i]; error = mtk_spi_txrx(sc, &byte, MTK_SPI_WRITE); if (error) goto mtk_spi_transfer_fail; continue; } error = mtk_spi_txrx(sc, &byte, MTK_SPI_READ); if (error) goto mtk_spi_transfer_fail; buf[i] = byte; } } /* * Transfer/Receive data */ if (cmd->tx_data_sz + cmd->rx_data_sz) { write = (cmd->tx_data_sz > 0)?1:0; buf = (uint8_t *)(write ? cmd->tx_data : cmd->rx_data); sz = write ? cmd->tx_data_sz : cmd->rx_data_sz; for (i = 0; i < sz; i++) { byte = buf[i]; error = mtk_spi_txrx(sc, &byte, write ? MTK_SPI_WRITE : MTK_SPI_READ); if (error) goto mtk_spi_transfer_fail; buf[i] = byte; } } mtk_spi_transfer_fail: mtk_spi_chip_deactivate(sc); return (error); } static phandle_t mtk_spi_get_node(device_t bus, device_t dev) { /* We only have one child, the SPI bus, which needs our own node. */ return (ofw_bus_get_node(bus)); } static device_method_t mtk_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mtk_spi_probe), DEVMETHOD(device_attach, mtk_spi_attach), DEVMETHOD(device_detach, mtk_spi_detach), DEVMETHOD(spibus_transfer, mtk_spi_transfer), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, mtk_spi_get_node), DEVMETHOD_END }; static driver_t mtk_spi_driver = { .name = "spi", .methods = mtk_spi_methods, .size = sizeof(struct mtk_spi_softc), }; static devclass_t mtk_spi_devclass; DRIVER_MODULE(mtk_spi_v1, simplebus, mtk_spi_driver, mtk_spi_devclass, 0, 0); Index: head/sys/mips/mediatek/mtk_spi_v2.c =================================================================== --- head/sys/mips/mediatek/mtk_spi_v2.c (revision 310228) +++ head/sys/mips/mediatek/mtk_spi_v2.c (revision 310229) @@ -1,353 +1,355 @@ /*- * Copyright (c) 2009, Oleksandr Tymoshenko * Copyright (c) 2011, Aleksandr Rybalko * Copyright (c) 2013, Alexander A. Mityaev * Copyright (c) 2016, Stanislav Galabov * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" #include "opt_platform.h" #include #include #include #include #include #undef MTK_SPI_DEBUG #ifdef MTK_SPI_DEBUG #define dprintf printf #else #define dprintf(x, arg...) #endif /* * register space access macros */ #define SPI_WRITE(sc, reg, val) do { \ bus_write_4(sc->sc_mem_res, (reg), (val)); \ } while (0) #define SPI_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg)) #define SPI_SET_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits)) #define SPI_CLEAR_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits)) struct mtk_spi_softc { device_t sc_dev; struct resource *sc_mem_res; }; static int mtk_spi_probe(device_t); static int mtk_spi_attach(device_t); static int mtk_spi_detach(device_t); static int mtk_spi_wait(struct mtk_spi_softc *); static void mtk_spi_chip_activate(struct mtk_spi_softc *); static void mtk_spi_chip_deactivate(struct mtk_spi_softc *); static uint8_t mtk_spi_txrx(struct mtk_spi_softc *, uint8_t *, int); static int mtk_spi_transfer(device_t, device_t, struct spi_command *); static phandle_t mtk_spi_get_node(device_t, device_t); static struct ofw_compat_data compat_data[] = { { "ralink,mt7621-spi", 1 }, { "ralink,mtk7628an-spi", 1 }, { NULL, 0 } }; static int mtk_spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return(ENXIO); device_set_desc(dev, "MTK SPI Controller (v2)"); return (0); } static int mtk_spi_attach(device_t dev) { struct mtk_spi_softc *sc = device_get_softc(dev); uint32_t val; int rid; sc->sc_dev = dev; rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "Could not map memory\n"); return (ENXIO); } if (mtk_spi_wait(sc)) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (EBUSY); } val = SPI_READ(sc, MTK_SPIMASTER); val &= ~(0xfff << 16); val |= 13 << 16; val |= 7 << 29; val |= 1 << 2; SPI_WRITE(sc, MTK_SPIMASTER, val); /* * W25Q64CV max 104MHz, bus 120-192 MHz, so divide by 2. * Update: divide by 4, DEV2 to fast for flash. */ device_add_child(dev, "spibus", 0); return (bus_generic_attach(dev)); } static int mtk_spi_detach(device_t dev) { struct mtk_spi_softc *sc = device_get_softc(dev); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (0); } static void mtk_spi_chip_activate(struct mtk_spi_softc *sc) { mtk_spi_wait(sc); /* * Put all CSx to low */ SPI_SET_BITS(sc, MTK_SPIPOLAR, 1); } static void mtk_spi_chip_deactivate(struct mtk_spi_softc *sc) { mtk_spi_wait(sc); /* * Put all CSx to high */ SPI_CLEAR_BITS(sc, MTK_SPIPOLAR, 1); } static int mtk_spi_wait(struct mtk_spi_softc *sc) { int i = 1000; while (i--) { if (!(SPI_READ(sc, MTK_SPITRANS) & SPIBUSY)) break; } if (i == 0) { return (1); } return (0); } static uint8_t mtk_spi_txrx(struct mtk_spi_softc *sc, uint8_t *data, int write) { if (mtk_spi_wait(sc)) return (0xff); if (write == MTK_SPI_WRITE) { SPI_WRITE(sc, MTK_SPIOPCODE, (*data)); SPI_WRITE(sc, MTK_SPIMOREBUF, (8<<24)); } else { SPI_WRITE(sc, MTK_SPIMOREBUF, (8<<12)); } SPI_SET_BITS(sc, MTK_SPITRANS, SPISTART); if (mtk_spi_wait(sc)) return (0xff); if (write == MTK_SPI_READ) { *data = SPI_READ(sc, MTK_SPIDATA) & 0xff; } return (0); } static int mtk_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct mtk_spi_softc *sc; uint8_t *buf, byte, *tx_buf; uint32_t cs; int i, sz, error, write = 0; sc = device_get_softc(dev); spibus_get_cs(child, &cs); + cs &= ~SPIBUS_CS_HIGH; + if (cs != 0) /* Only 1 CS */ return (ENXIO); /* There is always a command to transfer. */ tx_buf = (uint8_t *)(cmd->tx_cmd); /* Perform some fixup because MTK dont support duplex SPI */ switch(tx_buf[0]) { case CMD_READ_IDENT: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 3; break; case CMD_ENTER_4B_MODE: case CMD_EXIT_4B_MODE: case CMD_WRITE_ENABLE: case CMD_WRITE_DISABLE: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 0; break; case CMD_READ_STATUS: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 1; break; case CMD_READ: case CMD_FAST_READ: cmd->rx_cmd_sz = cmd->tx_data_sz = 0; break; case CMD_SECTOR_ERASE: cmd->rx_cmd_sz = 0; break; case CMD_PAGE_PROGRAM: cmd->rx_cmd_sz = cmd->rx_data_sz = 0; break; } mtk_spi_chip_activate(sc); if (cmd->tx_cmd_sz + cmd->rx_cmd_sz) { buf = (uint8_t *)(cmd->rx_cmd); tx_buf = (uint8_t *)(cmd->tx_cmd); sz = cmd->tx_cmd_sz + cmd->rx_cmd_sz; for (i = 0; i < sz; i++) { if(i < cmd->tx_cmd_sz) { byte = tx_buf[i]; error = mtk_spi_txrx(sc, &byte, MTK_SPI_WRITE); if (error) goto mtk_spi_transfer_fail; continue; } error = mtk_spi_txrx(sc, &byte, MTK_SPI_READ); if (error) goto mtk_spi_transfer_fail; buf[i] = byte; } } /* * Transfer/Receive data */ if (cmd->tx_data_sz + cmd->rx_data_sz) { write = (cmd->tx_data_sz > 0)?1:0; buf = (uint8_t *)(write ? cmd->tx_data : cmd->rx_data); sz = write ? cmd->tx_data_sz : cmd->rx_data_sz; for (i = 0; i < sz; i++) { byte = buf[i]; error = mtk_spi_txrx(sc, &byte, write ? MTK_SPI_WRITE : MTK_SPI_READ); if (error) goto mtk_spi_transfer_fail; buf[i] = byte; } } mtk_spi_transfer_fail: mtk_spi_chip_deactivate(sc); return (0); } static phandle_t mtk_spi_get_node(device_t bus, device_t dev) { /* We only have one child, the SPI bus, which needs our own node. */ return (ofw_bus_get_node(bus)); } static device_method_t mtk_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mtk_spi_probe), DEVMETHOD(device_attach, mtk_spi_attach), DEVMETHOD(device_detach, mtk_spi_detach), DEVMETHOD(spibus_transfer, mtk_spi_transfer), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, mtk_spi_get_node), DEVMETHOD_END }; static driver_t mtk_spi_driver = { .name = "spi", .methods = mtk_spi_methods, .size = sizeof(struct mtk_spi_softc), }; static devclass_t mtk_spi_devclass; DRIVER_MODULE(mtk_spi_v2, simplebus, mtk_spi_driver, mtk_spi_devclass, 0, 0); Index: head/sys/mips/rt305x/rt305x_spi.c =================================================================== --- head/sys/mips/rt305x/rt305x_spi.c (revision 310228) +++ head/sys/mips/rt305x/rt305x_spi.c (revision 310229) @@ -1,352 +1,354 @@ /*- * Copyright (c) 2009, Oleksandr Tymoshenko * Copyright (c) 2011, Aleksandr Rybalko * Copyright (c) 2013, Alexander A. Mityaev * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include //#include #include #include #include "spibus_if.h" #include "opt_platform.h" #ifdef FDT #include #include #include #endif #include #include #undef RT305X_SPI_DEBUG #ifdef RT305X_SPI_DEBUG #define dprintf printf #else #define dprintf(x, arg...) #endif /* * register space access macros */ #define SPI_WRITE(sc, reg, val) do { \ bus_write_4(sc->sc_mem_res, (reg), (val)); \ } while (0) #define SPI_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg)) #define SPI_SET_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits)) #define SPI_CLEAR_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits)) struct rt305x_spi_softc { device_t sc_dev; struct resource *sc_mem_res; }; static int rt305x_spi_probe(device_t); static int rt305x_spi_attach(device_t); static int rt305x_spi_detach(device_t); static int rt305x_spi_wait(struct rt305x_spi_softc *); static void rt305x_spi_chip_activate(struct rt305x_spi_softc *); static void rt305x_spi_chip_deactivate(struct rt305x_spi_softc *); static uint8_t rt305x_spi_txrx(struct rt305x_spi_softc *, uint8_t *, int); static int rt305x_spi_transfer(device_t, device_t, struct spi_command *); #ifdef FDT static phandle_t rt305x_spi_get_node(device_t, device_t); #endif static int rt305x_spi_probe(device_t dev) { #ifdef FDT if (!ofw_bus_is_compatible(dev, "ralink,rt305x-spi")) return(ENXIO); #endif device_set_desc(dev, "RT305X SPI"); return (0); } static int rt305x_spi_attach(device_t dev) { struct rt305x_spi_softc *sc = device_get_softc(dev); int rid; sc->sc_dev = dev; rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "Could not map memory\n"); return (ENXIO); } if (rt305x_spi_wait(sc)) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (EBUSY); } SPI_WRITE(sc, RT305X_SPICFG, MSBFIRST | SPICLKPOL | TX_ON_CLK_FALL | SPI_CLK_DIV8); /* XXX: make it configurable */ /* * W25Q64CV max 104MHz, bus 120-192 MHz, so divide by 2. * Update: divide by 4, DEV2 to fast for flash. */ device_add_child(dev, "spibus", 0); return (bus_generic_attach(dev)); } static int rt305x_spi_detach(device_t dev) { struct rt305x_spi_softc *sc = device_get_softc(dev); SPI_SET_BITS(sc, RT305X_SPICTL, HIZSMOSI | CS_HIGH); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (0); } static void rt305x_spi_chip_activate(struct rt305x_spi_softc *sc) { // printf("%s\n", __func__); rt305x_spi_wait(sc); /* * Put all CSx to low */ SPI_CLEAR_BITS(sc, RT305X_SPICTL, CS_HIGH | HIZSMOSI); } static void rt305x_spi_chip_deactivate(struct rt305x_spi_softc *sc) { // printf("%s\n", __func__); rt305x_spi_wait(sc); /* * Put all CSx to high */ SPI_SET_BITS(sc, RT305X_SPICTL, CS_HIGH | HIZSMOSI); } static int rt305x_spi_wait(struct rt305x_spi_softc *sc) { int i = 1000; while (i--) { if (!SPI_READ(sc, RT305X_SPIBUSY)) break; } if (i == 0) { printf("busy\n"); return (1); } return (0); } static uint8_t rt305x_spi_txrx(struct rt305x_spi_softc *sc, uint8_t *data, int write) { if (rt305x_spi_wait(sc)) return (EBUSY); if (write == RT305X_SPI_WRITE) { SPI_WRITE(sc, RT305X_SPIDATA, *data); SPI_SET_BITS(sc, RT305X_SPICTL, START_WRITE); //printf("%s(W:%d)\n", __func__, *data); } else {/* RT305X_SPI_READ */ SPI_SET_BITS(sc, RT305X_SPICTL, START_READ); if (rt305x_spi_wait(sc)) return (EBUSY); *data = SPI_READ(sc, RT305X_SPIDATA) & 0xff; //printf("%s(R:%d)\n", __func__, *data); } return (0); } static int rt305x_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct rt305x_spi_softc *sc; uint32_t cs; uint8_t *buf, byte, *tx_buf; int i, sz, error = 0, write = 0; sc = device_get_softc(dev); spibus_get_cs(child, &cs); + cs &= ~SPIBUS_CS_HIGH; + if (cs != 0) /* Only 1 CS */ return (ENXIO); /* There is always a command to transfer. */ tx_buf = (uint8_t *)(cmd->tx_cmd); /* Perform some fixup because RT305X dont support duplex SPI */ switch(tx_buf[0]) { case CMD_READ_IDENT: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 3; break; case CMD_WRITE_ENABLE: case CMD_WRITE_DISABLE: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 0; break; case CMD_READ_STATUS: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 1; break; case CMD_READ: cmd->tx_cmd_sz = 4; case CMD_FAST_READ: cmd->tx_cmd_sz = 5; cmd->rx_cmd_sz = cmd->tx_data_sz = 0; break; case CMD_SECTOR_ERASE: cmd->tx_cmd_sz = 4; cmd->rx_cmd_sz = cmd->tx_data_sz = 0; break; case CMD_PAGE_PROGRAM: cmd->tx_cmd_sz = 4; cmd->rx_cmd_sz = cmd->rx_data_sz = 0; break; } rt305x_spi_chip_activate(sc); if (cmd->tx_cmd_sz + cmd->rx_cmd_sz) { buf = (uint8_t *)(cmd->rx_cmd); tx_buf = (uint8_t *)(cmd->tx_cmd); sz = cmd->tx_cmd_sz + cmd->rx_cmd_sz; for (i = 0; i < sz; i++) { if(i < cmd->tx_cmd_sz) { byte = tx_buf[i]; error = rt305x_spi_txrx(sc, &byte, RT305X_SPI_WRITE); if (error) goto rt305x_spi_transfer_fail; continue; } error = rt305x_spi_txrx(sc, &byte, RT305X_SPI_READ); if (error) goto rt305x_spi_transfer_fail; buf[i] = byte; } } /* * Transfer/Receive data */ if (cmd->tx_data_sz + cmd->rx_data_sz) { write = (cmd->tx_data_sz > 0)?1:0; buf = (uint8_t *)(write ? cmd->tx_data : cmd->rx_data); sz = write ? cmd->tx_data_sz : cmd->rx_data_sz; for (i = 0; i < sz; i++) { byte = buf[i]; error = rt305x_spi_txrx(sc, &byte, write?RT305X_SPI_WRITE:RT305X_SPI_READ); if (error) goto rt305x_spi_transfer_fail; buf[i] = byte; } } rt305x_spi_transfer_fail: rt305x_spi_chip_deactivate(sc); return (error); } #ifdef FDT static phandle_t rt305x_spi_get_node(device_t bus, device_t dev) { /* We only have one child, the SPI bus, which needs our own node. */ return (ofw_bus_get_node(bus)); } #endif static device_method_t rt305x_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, rt305x_spi_probe), DEVMETHOD(device_attach, rt305x_spi_attach), DEVMETHOD(device_detach, rt305x_spi_detach), DEVMETHOD(spibus_transfer, rt305x_spi_transfer), #ifdef FDT /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, rt305x_spi_get_node), #endif DEVMETHOD_END }; static driver_t rt305x_spi_driver = { .name = "spi", .methods = rt305x_spi_methods, .size = sizeof(struct rt305x_spi_softc), }; static devclass_t rt305x_spi_devclass; DRIVER_MODULE(rt305x_spi, obio, rt305x_spi_driver, rt305x_spi_devclass, 0, 0); #ifdef FDT DRIVER_MODULE(rt305x_spi, simplebus, rt305x_spi_driver, rt305x_spi_devclass, 0, 0); #endif