Index: stable/11/sys/arm/lpc/lpc_spi.c =================================================================== --- stable/11/sys/arm/lpc/lpc_spi.c (revision 310157) +++ stable/11/sys/arm/lpc/lpc_spi.c (revision 310158) @@ -1,196 +1,198 @@ /*- * Copyright (c) 2011 Jakub Wojciech Klama * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" struct lpc_spi_softc { device_t ls_dev; struct resource * ls_mem_res; struct resource * ls_irq_res; bus_space_tag_t ls_bst; bus_space_handle_t ls_bsh; }; static int lpc_spi_probe(device_t); static int lpc_spi_attach(device_t); static int lpc_spi_detach(device_t); static int lpc_spi_transfer(device_t, device_t, struct spi_command *); #define lpc_spi_read_4(_sc, _reg) \ bus_space_read_4(_sc->ls_bst, _sc->ls_bsh, _reg) #define lpc_spi_write_4(_sc, _reg, _val) \ bus_space_write_4(_sc->ls_bst, _sc->ls_bsh, _reg, _val) static int lpc_spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "lpc,spi")) return (ENXIO); device_set_desc(dev, "LPC32x0 PL022 SPI/SSP controller"); return (BUS_PROBE_DEFAULT); } static int lpc_spi_attach(device_t dev) { struct lpc_spi_softc *sc = device_get_softc(dev); int rid; sc->ls_dev = dev; rid = 0; sc->ls_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->ls_mem_res) { device_printf(dev, "cannot allocate memory window\n"); return (ENXIO); } sc->ls_bst = rman_get_bustag(sc->ls_mem_res); sc->ls_bsh = rman_get_bushandle(sc->ls_mem_res); rid = 0; sc->ls_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (!sc->ls_irq_res) { device_printf(dev, "cannot allocate interrupt\n"); return (ENXIO); } bus_space_write_4(sc->ls_bst, 0xd0028100, 0, (1<<12)|(1<<10)|(1<<9)|(1<<8)|(1<<6)|(1<<5)); lpc_pwr_write(dev, LPC_CLKPWR_SSP_CTRL, LPC_CLKPWR_SSP_CTRL_SSP0EN); lpc_spi_write_4(sc, LPC_SSP_CR0, LPC_SSP_CR0_DSS(8)); lpc_spi_write_4(sc, LPC_SSP_CR1, LPC_SSP_CR1_SSE); lpc_spi_write_4(sc, LPC_SSP_CPSR, 128); device_add_child(dev, "spibus", 0); return (bus_generic_attach(dev)); } static int lpc_spi_detach(device_t dev) { return (EBUSY); } static int lpc_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct lpc_spi_softc *sc = device_get_softc(dev); - struct spibus_ivar *devi = SPIBUS_IVAR(child); + uint32_t cs; uint8_t *in_buf, *out_buf; int i; + spibus_get_cs(child, &cs); + /* Set CS active */ - lpc_gpio_set_state(child, devi->cs, 0); + lpc_gpio_set_state(child, cs, 0); /* Wait for FIFO to be ready */ while ((lpc_spi_read_4(sc, LPC_SSP_SR) & LPC_SSP_SR_TNF) == 0); /* Command */ in_buf = cmd->rx_cmd; out_buf = cmd->tx_cmd; for (i = 0; i < cmd->tx_cmd_sz; i++) { lpc_spi_write_4(sc, LPC_SSP_DR, out_buf[i]); in_buf[i] = lpc_spi_read_4(sc, LPC_SSP_DR); } /* Data */ in_buf = cmd->rx_data; out_buf = cmd->tx_data; for (i = 0; i < cmd->tx_data_sz; i++) { lpc_spi_write_4(sc, LPC_SSP_DR, out_buf[i]); in_buf[i] = lpc_spi_read_4(sc, LPC_SSP_DR); } /* Set CS inactive */ - lpc_gpio_set_state(child, devi->cs, 1); + lpc_gpio_set_state(child, cs, 1); return (0); } static device_method_t lpc_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, lpc_spi_probe), DEVMETHOD(device_attach, lpc_spi_attach), DEVMETHOD(device_detach, lpc_spi_detach), /* SPI interface */ DEVMETHOD(spibus_transfer, lpc_spi_transfer), { 0, 0 } }; static devclass_t lpc_spi_devclass; static driver_t lpc_spi_driver = { "spi", lpc_spi_methods, sizeof(struct lpc_spi_softc), }; DRIVER_MODULE(lpcspi, simplebus, lpc_spi_driver, lpc_spi_devclass, 0, 0); Index: stable/11/sys/mips/atheros/ar71xx_spi.c =================================================================== --- stable/11/sys/mips/atheros/ar71xx_spi.c (revision 310157) +++ stable/11/sys/mips/atheros/ar71xx_spi.c (revision 310158) @@ -1,291 +1,293 @@ /*- * Copyright (c) 2009, Oleksandr Tymoshenko * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" #include #undef AR71XX_SPI_DEBUG #ifdef AR71XX_SPI_DEBUG #define dprintf printf #else #define dprintf(x, arg...) #endif /* * register space access macros */ #define SPI_BARRIER_WRITE(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \ BUS_SPACE_BARRIER_WRITE) #define SPI_BARRIER_READ(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \ BUS_SPACE_BARRIER_READ) #define SPI_BARRIER_RW(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \ BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) #define SPI_WRITE(sc, reg, val) do { \ bus_write_4(sc->sc_mem_res, (reg), (val)); \ } while (0) #define SPI_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg)) #define SPI_SET_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits)) #define SPI_CLEAR_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits)) struct ar71xx_spi_softc { device_t sc_dev; struct resource *sc_mem_res; uint32_t sc_reg_ctrl; }; static int ar71xx_spi_probe(device_t dev) { device_set_desc(dev, "AR71XX SPI"); return (BUS_PROBE_NOWILDCARD); } static int ar71xx_spi_attach(device_t dev) { struct ar71xx_spi_softc *sc = device_get_softc(dev); int rid; sc->sc_dev = dev; rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "Could not map memory\n"); return (ENXIO); } SPI_WRITE(sc, AR71XX_SPI_FS, 1); /* Flush out read before reading the control register */ SPI_BARRIER_WRITE(sc); sc->sc_reg_ctrl = SPI_READ(sc, AR71XX_SPI_CTRL); /* * XXX TODO: document what the SPI control register does. */ SPI_WRITE(sc, AR71XX_SPI_CTRL, 0x43); /* * Ensure the config register write has gone out before configuring * the chip select mask. */ SPI_BARRIER_WRITE(sc); SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, SPI_IO_CTRL_CSMASK); /* * .. and ensure the write has gone out before continuing. */ SPI_BARRIER_WRITE(sc); device_add_child(dev, "spibus", -1); return (bus_generic_attach(dev)); } static void ar71xx_spi_chip_activate(struct ar71xx_spi_softc *sc, int cs) { uint32_t ioctrl = SPI_IO_CTRL_CSMASK; /* * Put respective CSx to low */ ioctrl &= ~(SPI_IO_CTRL_CS0 << cs); /* * Make sure any other writes have gone out to the * device before changing the chip select line; * then ensure that it has made it out to the device * before continuing. */ SPI_BARRIER_WRITE(sc); SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, ioctrl); SPI_BARRIER_WRITE(sc); } static void ar71xx_spi_chip_deactivate(struct ar71xx_spi_softc *sc, int cs) { /* * Put all CSx to high */ SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, SPI_IO_CTRL_CSMASK); } static uint8_t ar71xx_spi_txrx(struct ar71xx_spi_softc *sc, int cs, uint8_t data) { int bit; /* CS0 */ uint32_t ioctrl = SPI_IO_CTRL_CSMASK; /* * low-level for selected CS */ ioctrl &= ~(SPI_IO_CTRL_CS0 << cs); uint32_t iod, rds; for (bit = 7; bit >=0; bit--) { if (data & (1 << bit)) iod = ioctrl | SPI_IO_CTRL_DO; else iod = ioctrl & ~SPI_IO_CTRL_DO; SPI_BARRIER_WRITE(sc); SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod); SPI_BARRIER_WRITE(sc); SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod | SPI_IO_CTRL_CLK); } /* * Provide falling edge for connected device by clear clock bit. */ SPI_BARRIER_WRITE(sc); SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod); SPI_BARRIER_WRITE(sc); rds = SPI_READ(sc, AR71XX_SPI_RDS); return (rds & 0xff); } static int ar71xx_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct ar71xx_spi_softc *sc; + uint32_t cs; uint8_t *buf_in, *buf_out; - struct spibus_ivar *devi = SPIBUS_IVAR(child); int i; sc = device_get_softc(dev); - ar71xx_spi_chip_activate(sc, devi->cs); + spibus_get_cs(child, &cs); + ar71xx_spi_chip_activate(sc, cs); + KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("TX/RX command sizes should be equal")); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("TX/RX data sizes should be equal")); /* * Transfer command */ buf_out = (uint8_t *)cmd->tx_cmd; buf_in = (uint8_t *)cmd->rx_cmd; for (i = 0; i < cmd->tx_cmd_sz; i++) - buf_in[i] = ar71xx_spi_txrx(sc, devi->cs, buf_out[i]); + buf_in[i] = ar71xx_spi_txrx(sc, cs, buf_out[i]); /* * Receive/transmit data (depends on command) */ buf_out = (uint8_t *)cmd->tx_data; buf_in = (uint8_t *)cmd->rx_data; for (i = 0; i < cmd->tx_data_sz; i++) - buf_in[i] = ar71xx_spi_txrx(sc, devi->cs, buf_out[i]); + buf_in[i] = ar71xx_spi_txrx(sc, cs, buf_out[i]); - ar71xx_spi_chip_deactivate(sc, devi->cs); + ar71xx_spi_chip_deactivate(sc, cs); return (0); } static int ar71xx_spi_detach(device_t dev) { struct ar71xx_spi_softc *sc = device_get_softc(dev); /* * Ensure any other writes to the device are finished * before we tear down the SPI device. */ SPI_BARRIER_WRITE(sc); /* * Restore the control register; ensure it has hit the * hardware before continuing. */ SPI_WRITE(sc, AR71XX_SPI_CTRL, sc->sc_reg_ctrl); SPI_BARRIER_WRITE(sc); /* * And now, put the flash back into mapped IO mode and * ensure _that_ has completed before we finish up. */ SPI_WRITE(sc, AR71XX_SPI_FS, 0); SPI_BARRIER_WRITE(sc); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (0); } static device_method_t ar71xx_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ar71xx_spi_probe), DEVMETHOD(device_attach, ar71xx_spi_attach), DEVMETHOD(device_detach, ar71xx_spi_detach), DEVMETHOD(spibus_transfer, ar71xx_spi_transfer), {0, 0} }; static driver_t ar71xx_spi_driver = { "spi", ar71xx_spi_methods, sizeof(struct ar71xx_spi_softc), }; static devclass_t ar71xx_spi_devclass; DRIVER_MODULE(ar71xx_spi, nexus, ar71xx_spi_driver, ar71xx_spi_devclass, 0, 0); Index: stable/11/sys/mips/mediatek/mtk_spi_v1.c =================================================================== --- stable/11/sys/mips/mediatek/mtk_spi_v1.c (revision 310157) +++ stable/11/sys/mips/mediatek/mtk_spi_v1.c (revision 310158) @@ -1,346 +1,348 @@ /*- * Copyright (c) 2009, Oleksandr Tymoshenko * Copyright (c) 2011, Aleksandr Rybalko * Copyright (c) 2013, Alexander A. Mityaev * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" #include "opt_platform.h" #include #include #include #include #include #undef MTK_SPI_DEBUG #ifdef MTK_SPI_DEBUG #define dprintf printf #else #define dprintf(x, arg...) #endif /* * register space access macros */ #define SPI_WRITE(sc, reg, val) do { \ bus_write_4(sc->sc_mem_res, (reg), (val)); \ } while (0) #define SPI_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg)) #define SPI_SET_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits)) #define SPI_CLEAR_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits)) struct mtk_spi_softc { device_t sc_dev; struct resource *sc_mem_res; }; static int mtk_spi_probe(device_t); static int mtk_spi_attach(device_t); static int mtk_spi_detach(device_t); static int mtk_spi_wait(struct mtk_spi_softc *); static void mtk_spi_chip_activate(struct mtk_spi_softc *); static void mtk_spi_chip_deactivate(struct mtk_spi_softc *); static uint8_t mtk_spi_txrx(struct mtk_spi_softc *, uint8_t *, int); static int mtk_spi_transfer(device_t, device_t, struct spi_command *); static phandle_t mtk_spi_get_node(device_t, device_t); static struct ofw_compat_data compat_data[] = { { "ralink,rt2880-spi", 1 }, { "ralink,rt3050-spi", 1 }, { "ralink,rt3352-spi", 1 }, { "ralink,rt3883-spi", 1 }, { "ralink,rt5350-spi", 1 }, { "ralink,mt7620a-spi", 1 }, { NULL, 0 } }; static int mtk_spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return(ENXIO); device_set_desc(dev, "MTK SPI Controller (v1)"); return (0); } static int mtk_spi_attach(device_t dev) { struct mtk_spi_softc *sc = device_get_softc(dev); int rid; sc->sc_dev = dev; rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "Could not map memory\n"); return (ENXIO); } if (mtk_spi_wait(sc)) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (EBUSY); } SPI_WRITE(sc, MTK_SPICFG, MSBFIRST | SPICLKPOL | TX_ON_CLK_FALL | SPI_CLK_DIV8); /* XXX: make it configurable */ /* * W25Q64CV max 104MHz, bus 120-192 MHz, so divide by 2. * Update: divide by 4, DEV2 to fast for flash. */ device_add_child(dev, "spibus", 0); return (bus_generic_attach(dev)); } static int mtk_spi_detach(device_t dev) { struct mtk_spi_softc *sc = device_get_softc(dev); SPI_SET_BITS(sc, MTK_SPICTL, HIZSMOSI | CS_HIGH); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (0); } static void mtk_spi_chip_activate(struct mtk_spi_softc *sc) { mtk_spi_wait(sc); /* * Put all CSx to low */ SPI_CLEAR_BITS(sc, MTK_SPICTL, CS_HIGH | HIZSMOSI); } static void mtk_spi_chip_deactivate(struct mtk_spi_softc *sc) { mtk_spi_wait(sc); /* * Put all CSx to high */ SPI_SET_BITS(sc, MTK_SPICTL, CS_HIGH | HIZSMOSI); } static int mtk_spi_wait(struct mtk_spi_softc *sc) { int i = 1000; while (i--) { if (!SPI_READ(sc, MTK_SPIBUSY)) break; } if (i == 0) { printf("busy\n"); return (1); } return (0); } static uint8_t mtk_spi_txrx(struct mtk_spi_softc *sc, uint8_t *data, int write) { if (mtk_spi_wait(sc)) return (EBUSY); if (write == MTK_SPI_WRITE) { SPI_WRITE(sc, MTK_SPIDATA, *data); SPI_SET_BITS(sc, MTK_SPICTL, START_WRITE); } else {/* MTK_SPI_READ */ SPI_SET_BITS(sc, MTK_SPICTL, START_READ); if (mtk_spi_wait(sc)) return (EBUSY); *data = SPI_READ(sc, MTK_SPIDATA) & 0xff; } return (0); } static int mtk_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct mtk_spi_softc *sc; uint8_t *buf, byte, *tx_buf; - struct spibus_ivar *devi = SPIBUS_IVAR(child); + uint32_t cs; int i, sz, error = 0, write = 0; sc = device_get_softc(dev); - if (devi->cs != 0) + spibus_get_cs(child, &cs); + + if (cs != 0) /* Only 1 CS */ return (ENXIO); /* There is always a command to transfer. */ tx_buf = (uint8_t *)(cmd->tx_cmd); /* Perform some fixup because MTK dont support duplex SPI */ switch(tx_buf[0]) { case CMD_READ_IDENT: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 3; break; case CMD_ENTER_4B_MODE: case CMD_EXIT_4B_MODE: case CMD_WRITE_ENABLE: case CMD_WRITE_DISABLE: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 0; break; case CMD_READ_STATUS: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 1; break; case CMD_READ: case CMD_FAST_READ: cmd->rx_cmd_sz = cmd->tx_data_sz = 0; break; case CMD_SECTOR_ERASE: cmd->rx_cmd_sz = 0; break; case CMD_PAGE_PROGRAM: cmd->rx_cmd_sz = cmd->rx_data_sz = 0; break; } mtk_spi_chip_activate(sc); if (cmd->tx_cmd_sz + cmd->rx_cmd_sz) { buf = (uint8_t *)(cmd->rx_cmd); tx_buf = (uint8_t *)(cmd->tx_cmd); sz = cmd->tx_cmd_sz + cmd->rx_cmd_sz; for (i = 0; i < sz; i++) { if(i < cmd->tx_cmd_sz) { byte = tx_buf[i]; error = mtk_spi_txrx(sc, &byte, MTK_SPI_WRITE); if (error) goto mtk_spi_transfer_fail; continue; } error = mtk_spi_txrx(sc, &byte, MTK_SPI_READ); if (error) goto mtk_spi_transfer_fail; buf[i] = byte; } } /* * Transfer/Receive data */ if (cmd->tx_data_sz + cmd->rx_data_sz) { write = (cmd->tx_data_sz > 0)?1:0; buf = (uint8_t *)(write ? cmd->tx_data : cmd->rx_data); sz = write ? cmd->tx_data_sz : cmd->rx_data_sz; for (i = 0; i < sz; i++) { byte = buf[i]; error = mtk_spi_txrx(sc, &byte, write ? MTK_SPI_WRITE : MTK_SPI_READ); if (error) goto mtk_spi_transfer_fail; buf[i] = byte; } } mtk_spi_transfer_fail: mtk_spi_chip_deactivate(sc); return (error); } static phandle_t mtk_spi_get_node(device_t bus, device_t dev) { /* We only have one child, the SPI bus, which needs our own node. */ return (ofw_bus_get_node(bus)); } static device_method_t mtk_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mtk_spi_probe), DEVMETHOD(device_attach, mtk_spi_attach), DEVMETHOD(device_detach, mtk_spi_detach), DEVMETHOD(spibus_transfer, mtk_spi_transfer), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, mtk_spi_get_node), DEVMETHOD_END }; static driver_t mtk_spi_driver = { .name = "spi", .methods = mtk_spi_methods, .size = sizeof(struct mtk_spi_softc), }; static devclass_t mtk_spi_devclass; DRIVER_MODULE(mtk_spi_v1, simplebus, mtk_spi_driver, mtk_spi_devclass, 0, 0); Index: stable/11/sys/mips/mediatek/mtk_spi_v2.c =================================================================== --- stable/11/sys/mips/mediatek/mtk_spi_v2.c (revision 310157) +++ stable/11/sys/mips/mediatek/mtk_spi_v2.c (revision 310158) @@ -1,351 +1,353 @@ /*- * Copyright (c) 2009, Oleksandr Tymoshenko * Copyright (c) 2011, Aleksandr Rybalko * Copyright (c) 2013, Alexander A. Mityaev * Copyright (c) 2016, Stanislav Galabov * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" #include "opt_platform.h" #include #include #include #include #include #undef MTK_SPI_DEBUG #ifdef MTK_SPI_DEBUG #define dprintf printf #else #define dprintf(x, arg...) #endif /* * register space access macros */ #define SPI_WRITE(sc, reg, val) do { \ bus_write_4(sc->sc_mem_res, (reg), (val)); \ } while (0) #define SPI_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg)) #define SPI_SET_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits)) #define SPI_CLEAR_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits)) struct mtk_spi_softc { device_t sc_dev; struct resource *sc_mem_res; }; static int mtk_spi_probe(device_t); static int mtk_spi_attach(device_t); static int mtk_spi_detach(device_t); static int mtk_spi_wait(struct mtk_spi_softc *); static void mtk_spi_chip_activate(struct mtk_spi_softc *); static void mtk_spi_chip_deactivate(struct mtk_spi_softc *); static uint8_t mtk_spi_txrx(struct mtk_spi_softc *, uint8_t *, int); static int mtk_spi_transfer(device_t, device_t, struct spi_command *); static phandle_t mtk_spi_get_node(device_t, device_t); static struct ofw_compat_data compat_data[] = { { "ralink,mt7621-spi", 1 }, { "ralink,mtk7628an-spi", 1 }, { NULL, 0 } }; static int mtk_spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return(ENXIO); device_set_desc(dev, "MTK SPI Controller (v2)"); return (0); } static int mtk_spi_attach(device_t dev) { struct mtk_spi_softc *sc = device_get_softc(dev); uint32_t val; int rid; sc->sc_dev = dev; rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "Could not map memory\n"); return (ENXIO); } if (mtk_spi_wait(sc)) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (EBUSY); } val = SPI_READ(sc, MTK_SPIMASTER); val &= ~(0xfff << 16); val |= 13 << 16; val |= 7 << 29; val |= 1 << 2; SPI_WRITE(sc, MTK_SPIMASTER, val); /* * W25Q64CV max 104MHz, bus 120-192 MHz, so divide by 2. * Update: divide by 4, DEV2 to fast for flash. */ device_add_child(dev, "spibus", 0); return (bus_generic_attach(dev)); } static int mtk_spi_detach(device_t dev) { struct mtk_spi_softc *sc = device_get_softc(dev); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (0); } static void mtk_spi_chip_activate(struct mtk_spi_softc *sc) { mtk_spi_wait(sc); /* * Put all CSx to low */ SPI_SET_BITS(sc, MTK_SPIPOLAR, 1); } static void mtk_spi_chip_deactivate(struct mtk_spi_softc *sc) { mtk_spi_wait(sc); /* * Put all CSx to high */ SPI_CLEAR_BITS(sc, MTK_SPIPOLAR, 1); } static int mtk_spi_wait(struct mtk_spi_softc *sc) { int i = 1000; while (i--) { if (!(SPI_READ(sc, MTK_SPITRANS) & SPIBUSY)) break; } if (i == 0) { return (1); } return (0); } static uint8_t mtk_spi_txrx(struct mtk_spi_softc *sc, uint8_t *data, int write) { if (mtk_spi_wait(sc)) return (0xff); if (write == MTK_SPI_WRITE) { SPI_WRITE(sc, MTK_SPIOPCODE, (*data)); SPI_WRITE(sc, MTK_SPIMOREBUF, (8<<24)); } else { SPI_WRITE(sc, MTK_SPIMOREBUF, (8<<12)); } SPI_SET_BITS(sc, MTK_SPITRANS, SPISTART); if (mtk_spi_wait(sc)) return (0xff); if (write == MTK_SPI_READ) { *data = SPI_READ(sc, MTK_SPIDATA) & 0xff; } return (0); } static int mtk_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct mtk_spi_softc *sc; uint8_t *buf, byte, *tx_buf; - struct spibus_ivar *devi = SPIBUS_IVAR(child); + uint32_t cs; int i, sz, error, write = 0; sc = device_get_softc(dev); - if (devi->cs != 0) + spibus_get_cs(child, &cs); + + if (cs != 0) /* Only 1 CS */ return (ENXIO); /* There is always a command to transfer. */ tx_buf = (uint8_t *)(cmd->tx_cmd); /* Perform some fixup because MTK dont support duplex SPI */ switch(tx_buf[0]) { case CMD_READ_IDENT: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 3; break; case CMD_ENTER_4B_MODE: case CMD_EXIT_4B_MODE: case CMD_WRITE_ENABLE: case CMD_WRITE_DISABLE: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 0; break; case CMD_READ_STATUS: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 1; break; case CMD_READ: case CMD_FAST_READ: cmd->rx_cmd_sz = cmd->tx_data_sz = 0; break; case CMD_SECTOR_ERASE: cmd->rx_cmd_sz = 0; break; case CMD_PAGE_PROGRAM: cmd->rx_cmd_sz = cmd->rx_data_sz = 0; break; } mtk_spi_chip_activate(sc); if (cmd->tx_cmd_sz + cmd->rx_cmd_sz) { buf = (uint8_t *)(cmd->rx_cmd); tx_buf = (uint8_t *)(cmd->tx_cmd); sz = cmd->tx_cmd_sz + cmd->rx_cmd_sz; for (i = 0; i < sz; i++) { if(i < cmd->tx_cmd_sz) { byte = tx_buf[i]; error = mtk_spi_txrx(sc, &byte, MTK_SPI_WRITE); if (error) goto mtk_spi_transfer_fail; continue; } error = mtk_spi_txrx(sc, &byte, MTK_SPI_READ); if (error) goto mtk_spi_transfer_fail; buf[i] = byte; } } /* * Transfer/Receive data */ if (cmd->tx_data_sz + cmd->rx_data_sz) { write = (cmd->tx_data_sz > 0)?1:0; buf = (uint8_t *)(write ? cmd->tx_data : cmd->rx_data); sz = write ? cmd->tx_data_sz : cmd->rx_data_sz; for (i = 0; i < sz; i++) { byte = buf[i]; error = mtk_spi_txrx(sc, &byte, write ? MTK_SPI_WRITE : MTK_SPI_READ); if (error) goto mtk_spi_transfer_fail; buf[i] = byte; } } mtk_spi_transfer_fail: mtk_spi_chip_deactivate(sc); return (0); } static phandle_t mtk_spi_get_node(device_t bus, device_t dev) { /* We only have one child, the SPI bus, which needs our own node. */ return (ofw_bus_get_node(bus)); } static device_method_t mtk_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mtk_spi_probe), DEVMETHOD(device_attach, mtk_spi_attach), DEVMETHOD(device_detach, mtk_spi_detach), DEVMETHOD(spibus_transfer, mtk_spi_transfer), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, mtk_spi_get_node), DEVMETHOD_END }; static driver_t mtk_spi_driver = { .name = "spi", .methods = mtk_spi_methods, .size = sizeof(struct mtk_spi_softc), }; static devclass_t mtk_spi_devclass; DRIVER_MODULE(mtk_spi_v2, simplebus, mtk_spi_driver, mtk_spi_devclass, 0, 0); Index: stable/11/sys/mips/rt305x/rt305x_spi.c =================================================================== --- stable/11/sys/mips/rt305x/rt305x_spi.c (revision 310157) +++ stable/11/sys/mips/rt305x/rt305x_spi.c (revision 310158) @@ -1,350 +1,352 @@ /*- * Copyright (c) 2009, Oleksandr Tymoshenko * Copyright (c) 2011, Aleksandr Rybalko * Copyright (c) 2013, Alexander A. Mityaev * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include //#include #include #include #include "spibus_if.h" #include "opt_platform.h" #ifdef FDT #include #include #include #endif #include #include #undef RT305X_SPI_DEBUG #ifdef RT305X_SPI_DEBUG #define dprintf printf #else #define dprintf(x, arg...) #endif /* * register space access macros */ #define SPI_WRITE(sc, reg, val) do { \ bus_write_4(sc->sc_mem_res, (reg), (val)); \ } while (0) #define SPI_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg)) #define SPI_SET_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits)) #define SPI_CLEAR_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits)) struct rt305x_spi_softc { device_t sc_dev; struct resource *sc_mem_res; }; static int rt305x_spi_probe(device_t); static int rt305x_spi_attach(device_t); static int rt305x_spi_detach(device_t); static int rt305x_spi_wait(struct rt305x_spi_softc *); static void rt305x_spi_chip_activate(struct rt305x_spi_softc *); static void rt305x_spi_chip_deactivate(struct rt305x_spi_softc *); static uint8_t rt305x_spi_txrx(struct rt305x_spi_softc *, uint8_t *, int); static int rt305x_spi_transfer(device_t, device_t, struct spi_command *); #ifdef FDT static phandle_t rt305x_spi_get_node(device_t, device_t); #endif static int rt305x_spi_probe(device_t dev) { #ifdef FDT if (!ofw_bus_is_compatible(dev, "ralink,rt305x-spi")) return(ENXIO); #endif device_set_desc(dev, "RT305X SPI"); return (0); } static int rt305x_spi_attach(device_t dev) { struct rt305x_spi_softc *sc = device_get_softc(dev); int rid; sc->sc_dev = dev; rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "Could not map memory\n"); return (ENXIO); } if (rt305x_spi_wait(sc)) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (EBUSY); } SPI_WRITE(sc, RT305X_SPICFG, MSBFIRST | SPICLKPOL | TX_ON_CLK_FALL | SPI_CLK_DIV8); /* XXX: make it configurable */ /* * W25Q64CV max 104MHz, bus 120-192 MHz, so divide by 2. * Update: divide by 4, DEV2 to fast for flash. */ device_add_child(dev, "spibus", 0); return (bus_generic_attach(dev)); } static int rt305x_spi_detach(device_t dev) { struct rt305x_spi_softc *sc = device_get_softc(dev); SPI_SET_BITS(sc, RT305X_SPICTL, HIZSMOSI | CS_HIGH); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (0); } static void rt305x_spi_chip_activate(struct rt305x_spi_softc *sc) { // printf("%s\n", __func__); rt305x_spi_wait(sc); /* * Put all CSx to low */ SPI_CLEAR_BITS(sc, RT305X_SPICTL, CS_HIGH | HIZSMOSI); } static void rt305x_spi_chip_deactivate(struct rt305x_spi_softc *sc) { // printf("%s\n", __func__); rt305x_spi_wait(sc); /* * Put all CSx to high */ SPI_SET_BITS(sc, RT305X_SPICTL, CS_HIGH | HIZSMOSI); } static int rt305x_spi_wait(struct rt305x_spi_softc *sc) { int i = 1000; while (i--) { if (!SPI_READ(sc, RT305X_SPIBUSY)) break; } if (i == 0) { printf("busy\n"); return (1); } return (0); } static uint8_t rt305x_spi_txrx(struct rt305x_spi_softc *sc, uint8_t *data, int write) { if (rt305x_spi_wait(sc)) return (EBUSY); if (write == RT305X_SPI_WRITE) { SPI_WRITE(sc, RT305X_SPIDATA, *data); SPI_SET_BITS(sc, RT305X_SPICTL, START_WRITE); //printf("%s(W:%d)\n", __func__, *data); } else {/* RT305X_SPI_READ */ SPI_SET_BITS(sc, RT305X_SPICTL, START_READ); if (rt305x_spi_wait(sc)) return (EBUSY); *data = SPI_READ(sc, RT305X_SPIDATA) & 0xff; //printf("%s(R:%d)\n", __func__, *data); } return (0); } static int rt305x_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct rt305x_spi_softc *sc; + uint32_t cs; uint8_t *buf, byte, *tx_buf; - struct spibus_ivar *devi = SPIBUS_IVAR(child); int i, sz, error = 0, write = 0; sc = device_get_softc(dev); - if (devi->cs != 0) + spibus_get_cs(child, &cs); + + if (cs != 0) /* Only 1 CS */ return (ENXIO); /* There is always a command to transfer. */ tx_buf = (uint8_t *)(cmd->tx_cmd); /* Perform some fixup because RT305X dont support duplex SPI */ switch(tx_buf[0]) { case CMD_READ_IDENT: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 3; break; case CMD_WRITE_ENABLE: case CMD_WRITE_DISABLE: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 0; break; case CMD_READ_STATUS: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 1; break; case CMD_READ: cmd->tx_cmd_sz = 4; case CMD_FAST_READ: cmd->tx_cmd_sz = 5; cmd->rx_cmd_sz = cmd->tx_data_sz = 0; break; case CMD_SECTOR_ERASE: cmd->tx_cmd_sz = 4; cmd->rx_cmd_sz = cmd->tx_data_sz = 0; break; case CMD_PAGE_PROGRAM: cmd->tx_cmd_sz = 4; cmd->rx_cmd_sz = cmd->rx_data_sz = 0; break; } rt305x_spi_chip_activate(sc); if (cmd->tx_cmd_sz + cmd->rx_cmd_sz) { buf = (uint8_t *)(cmd->rx_cmd); tx_buf = (uint8_t *)(cmd->tx_cmd); sz = cmd->tx_cmd_sz + cmd->rx_cmd_sz; for (i = 0; i < sz; i++) { if(i < cmd->tx_cmd_sz) { byte = tx_buf[i]; error = rt305x_spi_txrx(sc, &byte, RT305X_SPI_WRITE); if (error) goto rt305x_spi_transfer_fail; continue; } error = rt305x_spi_txrx(sc, &byte, RT305X_SPI_READ); if (error) goto rt305x_spi_transfer_fail; buf[i] = byte; } } /* * Transfer/Receive data */ if (cmd->tx_data_sz + cmd->rx_data_sz) { write = (cmd->tx_data_sz > 0)?1:0; buf = (uint8_t *)(write ? cmd->tx_data : cmd->rx_data); sz = write ? cmd->tx_data_sz : cmd->rx_data_sz; for (i = 0; i < sz; i++) { byte = buf[i]; error = rt305x_spi_txrx(sc, &byte, write?RT305X_SPI_WRITE:RT305X_SPI_READ); if (error) goto rt305x_spi_transfer_fail; buf[i] = byte; } } rt305x_spi_transfer_fail: rt305x_spi_chip_deactivate(sc); return (error); } #ifdef FDT static phandle_t rt305x_spi_get_node(device_t bus, device_t dev) { /* We only have one child, the SPI bus, which needs our own node. */ return (ofw_bus_get_node(bus)); } #endif static device_method_t rt305x_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, rt305x_spi_probe), DEVMETHOD(device_attach, rt305x_spi_attach), DEVMETHOD(device_detach, rt305x_spi_detach), DEVMETHOD(spibus_transfer, rt305x_spi_transfer), #ifdef FDT /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, rt305x_spi_get_node), #endif DEVMETHOD_END }; static driver_t rt305x_spi_driver = { .name = "spi", .methods = rt305x_spi_methods, .size = sizeof(struct rt305x_spi_softc), }; static devclass_t rt305x_spi_devclass; DRIVER_MODULE(rt305x_spi, obio, rt305x_spi_driver, rt305x_spi_devclass, 0, 0); #ifdef FDT DRIVER_MODULE(rt305x_spi, simplebus, rt305x_spi_driver, rt305x_spi_devclass, 0, 0); #endif Index: stable/11 =================================================================== --- stable/11 (revision 310157) +++ stable/11 (revision 310158) Property changes on: stable/11 ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head:r309935