Index: stable/11/sys/arm/at91/at91_spi.c =================================================================== --- stable/11/sys/arm/at91/at91_spi.c (revision 310155) +++ stable/11/sys/arm/at91/at91_spi.c (revision 310156) @@ -1,457 +1,458 @@ /*- * Copyright (c) 2006 M. Warner Losh. * Copyright (c) 2011-2012 Ian Lepore. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef FDT #include #include #include #endif #include "spibus_if.h" struct at91_spi_softc { device_t dev; /* Myself */ void *intrhand; /* Interrupt handle */ struct resource *irq_res; /* IRQ resource */ struct resource *mem_res; /* Memory resource */ bus_dma_tag_t dmatag; /* bus dma tag for transfers */ bus_dmamap_t map[4]; /* Maps for the transaction */ struct sx xfer_mtx; /* Enforce one transfer at a time */ uint32_t xfer_done; /* interrupt<->mainthread signaling */ }; #define CS_TO_MR(cs) ((~(1 << (cs)) & 0x0f) << 16) static inline uint32_t RD4(struct at91_spi_softc *sc, bus_size_t off) { return (bus_read_4(sc->mem_res, off)); } static inline void WR4(struct at91_spi_softc *sc, bus_size_t off, uint32_t val) { bus_write_4(sc->mem_res, off, val); } /* bus entry points */ static int at91_spi_attach(device_t dev); static int at91_spi_detach(device_t dev); static int at91_spi_probe(device_t dev); static int at91_spi_transfer(device_t dev, device_t child, struct spi_command *cmd); /* helper routines */ static void at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error); static int at91_spi_activate(device_t dev); static void at91_spi_deactivate(device_t dev); static void at91_spi_intr(void *arg); static int at91_spi_probe(device_t dev) { #ifdef FDT if (!ofw_bus_is_compatible(dev, "atmel,at91rm9200-spi")) return (ENXIO); #endif device_set_desc(dev, "AT91 SPI"); return (0); } static int at91_spi_attach(device_t dev) { struct at91_spi_softc *sc; int err; uint32_t csr; sc = device_get_softc(dev); sc->dev = dev; sx_init(&sc->xfer_mtx, device_get_nameunit(dev)); /* * Allocate resources. */ err = at91_spi_activate(dev); if (err) goto out; #ifdef FDT /* * Disable devices need to hold their resources, so return now and not attach * the spibus, setup interrupt handlers, etc. */ if (!ofw_bus_status_okay(dev)) return 0; #endif /* * Set up the hardware. */ WR4(sc, SPI_CR, SPI_CR_SWRST); /* "Software Reset must be Written Twice" erratum */ WR4(sc, SPI_CR, SPI_CR_SWRST); WR4(sc, SPI_IDR, 0xffffffff); WR4(sc, SPI_MR, (0xf << 24) | SPI_MR_MSTR | SPI_MR_MODFDIS | CS_TO_MR(0)); /* * For now, run the bus at the slowest speed possible as otherwise we * may encounter data corruption on transmit as seen with ETHERNUT5 * and AT45DB321D even though both board and slave device can take * more. * This also serves as a work-around for the "NPCSx rises if no data * data is to be transmitted" erratum. The ideal workaround for the * latter is to take the chip select control away from the peripheral * and manage it directly as a GPIO line. The easy solution is to * slow down the bus so dramatically that it just never gets starved * as may be seen when the OCHI controller is running and consuming * memory and APB bandwidth. * Also, currently we lack a way for lettting both the board and the * slave devices take their maximum supported SPI clocks into account. * Also, we hard-wire SPI mode to 3. */ csr = SPI_CSR_CPOL | (4 << 16) | (0xff << 8); WR4(sc, SPI_CSR0, csr); WR4(sc, SPI_CSR1, csr); WR4(sc, SPI_CSR2, csr); WR4(sc, SPI_CSR3, csr); WR4(sc, SPI_CR, SPI_CR_SPIEN); WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS); WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS); WR4(sc, PDC_RNPR, 0); WR4(sc, PDC_RNCR, 0); WR4(sc, PDC_TNPR, 0); WR4(sc, PDC_TNCR, 0); WR4(sc, PDC_RPR, 0); WR4(sc, PDC_RCR, 0); WR4(sc, PDC_TPR, 0); WR4(sc, PDC_TCR, 0); RD4(sc, SPI_RDR); RD4(sc, SPI_SR); device_add_child(dev, "spibus", -1); bus_generic_attach(dev); out: if (err) at91_spi_deactivate(dev); return (err); } static int at91_spi_detach(device_t dev) { return (EBUSY); /* XXX */ } static int at91_spi_activate(device_t dev) { struct at91_spi_softc *sc; int err, i, rid; sc = device_get_softc(dev); err = ENOMEM; rid = 0; sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->mem_res == NULL) goto out; rid = 0; sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (sc->irq_res == NULL) goto out; err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, at91_spi_intr, sc, &sc->intrhand); if (err != 0) goto out; err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2048, 1, 2048, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->dmatag); if (err != 0) goto out; for (i = 0; i < 4; i++) { err = bus_dmamap_create(sc->dmatag, 0, &sc->map[i]); if (err != 0) goto out; } out: if (err != 0) at91_spi_deactivate(dev); return (err); } static void at91_spi_deactivate(device_t dev) { struct at91_spi_softc *sc; int i; sc = device_get_softc(dev); bus_generic_detach(dev); for (i = 0; i < 4; i++) if (sc->map[i]) bus_dmamap_destroy(sc->dmatag, sc->map[i]); if (sc->dmatag) bus_dma_tag_destroy(sc->dmatag); if (sc->intrhand) bus_teardown_intr(dev, sc->irq_res, sc->intrhand); sc->intrhand = NULL; if (sc->irq_res) bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), sc->irq_res); sc->irq_res = NULL; if (sc->mem_res) bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res), sc->mem_res); sc->mem_res = NULL; } static void at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs __unused, int error) { if (error != 0) return; *(bus_addr_t *)arg = segs[0].ds_addr; } static int at91_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct at91_spi_softc *sc; bus_addr_t addr; - int err, i, j, mode[4], cs; + int err, i, j, mode[4]; + uint32_t cs; KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("%s: TX/RX command sizes should be equal", __func__)); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("%s: TX/RX data sizes should be equal", __func__)); /* get the proper chip select */ spibus_get_cs(child, &cs); sc = device_get_softc(dev); i = 0; sx_xlock(&sc->xfer_mtx); /* * Disable transfers while we set things up. */ WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS); /* * PSCDEC = 0 has a range of 0..3 for chip select. We * don't support PSCDEC = 1 which has a range of 0..15. */ - if (cs < 0 || cs > 3) { + if (cs > 3) { device_printf(dev, "Invalid chip select %d requested by %s\n", cs, device_get_nameunit(child)); err = EINVAL; goto out; } #ifdef SPI_CHIP_SELECT_HIGH_SUPPORT /* * The AT91RM9200 couldn't do CS high for CS 0. Other chips can, but we * don't support that yet, or other spi modes. */ if (at91_is_rm92() && cs == 0 && (cmd->flags & SPI_CHIP_SELECT_HIGH) != 0) { device_printf(dev, "Invalid chip select high requested by %s for cs 0.\n", device_get_nameunit(child)); err = EINVAL; goto out; } #endif err = (RD4(sc, SPI_MR) & ~0x000f0000) | CS_TO_MR(cs); WR4(sc, SPI_MR, err); /* * Set up the TX side of the transfer. */ if ((err = bus_dmamap_load(sc->dmatag, sc->map[i], cmd->tx_cmd, cmd->tx_cmd_sz, at91_getaddr, &addr, 0)) != 0) goto out; WR4(sc, PDC_TPR, addr); WR4(sc, PDC_TCR, cmd->tx_cmd_sz); bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREWRITE); mode[i++] = BUS_DMASYNC_POSTWRITE; if (cmd->tx_data_sz > 0) { if ((err = bus_dmamap_load(sc->dmatag, sc->map[i], cmd->tx_data, cmd->tx_data_sz, at91_getaddr, &addr, 0)) != 0) goto out; WR4(sc, PDC_TNPR, addr); WR4(sc, PDC_TNCR, cmd->tx_data_sz); bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREWRITE); mode[i++] = BUS_DMASYNC_POSTWRITE; } /* * Set up the RX side of the transfer. */ if ((err = bus_dmamap_load(sc->dmatag, sc->map[i], cmd->rx_cmd, cmd->rx_cmd_sz, at91_getaddr, &addr, 0)) != 0) goto out; WR4(sc, PDC_RPR, addr); WR4(sc, PDC_RCR, cmd->rx_cmd_sz); bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREREAD); mode[i++] = BUS_DMASYNC_POSTREAD; if (cmd->rx_data_sz > 0) { if ((err = bus_dmamap_load(sc->dmatag, sc->map[i], cmd->rx_data, cmd->rx_data_sz, at91_getaddr, &addr, 0)) != 0) goto out; WR4(sc, PDC_RNPR, addr); WR4(sc, PDC_RNCR, cmd->rx_data_sz); bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREREAD); mode[i++] = BUS_DMASYNC_POSTREAD; } /* * Start the transfer, wait for it to complete. */ sc->xfer_done = 0; WR4(sc, SPI_IER, SPI_SR_RXBUFF); WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN | PDC_PTCR_RXTEN); do err = tsleep(&sc->xfer_done, PCATCH | PZERO, "at91_spi", hz); while (sc->xfer_done == 0 && err != EINTR); /* * Stop the transfer and clean things up. */ WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS); if (err == 0) for (j = 0; j < i; j++) bus_dmamap_sync(sc->dmatag, sc->map[j], mode[j]); out: for (j = 0; j < i; j++) bus_dmamap_unload(sc->dmatag, sc->map[j]); sx_xunlock(&sc->xfer_mtx); return (err); } static void at91_spi_intr(void *arg) { struct at91_spi_softc *sc; uint32_t sr; sc = (struct at91_spi_softc*)arg; sr = RD4(sc, SPI_SR) & RD4(sc, SPI_IMR); if ((sr & SPI_SR_RXBUFF) != 0) { sc->xfer_done = 1; WR4(sc, SPI_IDR, SPI_SR_RXBUFF); wakeup(&sc->xfer_done); } if ((sr & ~SPI_SR_RXBUFF) != 0) { device_printf(sc->dev, "Unexpected ISR %#x\n", sr); WR4(sc, SPI_IDR, sr & ~SPI_SR_RXBUFF); } } static devclass_t at91_spi_devclass; static device_method_t at91_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, at91_spi_probe), DEVMETHOD(device_attach, at91_spi_attach), DEVMETHOD(device_detach, at91_spi_detach), /* spibus interface */ DEVMETHOD(spibus_transfer, at91_spi_transfer), DEVMETHOD_END }; static driver_t at91_spi_driver = { "spi", at91_spi_methods, sizeof(struct at91_spi_softc), }; #ifdef FDT DRIVER_MODULE(at91_spi, simplebus, at91_spi_driver, at91_spi_devclass, NULL, NULL); #else DRIVER_MODULE(at91_spi, atmelarm, at91_spi_driver, at91_spi_devclass, NULL, NULL); #endif Index: stable/11/sys/arm/broadcom/bcm2835/bcm2835_spi.c =================================================================== --- stable/11/sys/arm/broadcom/bcm2835/bcm2835_spi.c (revision 310155) +++ stable/11/sys/arm/broadcom/bcm2835/bcm2835_spi.c (revision 310156) @@ -1,525 +1,526 @@ /*- * Copyright (c) 2012 Oleksandr Tymoshenko * Copyright (c) 2013 Luiz Otavio O Souza * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" static struct ofw_compat_data compat_data[] = { {"broadcom,bcm2835-spi", 1}, {"brcm,bcm2835-spi", 1}, {NULL, 0} }; static void bcm_spi_intr(void *); #ifdef BCM_SPI_DEBUG static void bcm_spi_printr(device_t dev) { struct bcm_spi_softc *sc; uint32_t reg; sc = device_get_softc(dev); reg = BCM_SPI_READ(sc, SPI_CS); device_printf(dev, "CS=%b\n", reg, "\20\1CS0\2CS1\3CPHA\4CPOL\7CSPOL" "\10TA\11DMAEN\12INTD\13INTR\14ADCS\15REN\16LEN" "\21DONE\22RXD\23TXD\24RXR\25RXF\26CSPOL0\27CSPOL1" "\30CSPOL2\31DMA_LEN\32LEN_LONG"); reg = BCM_SPI_READ(sc, SPI_CLK) & SPI_CLK_MASK; if (reg % 2) reg--; if (reg == 0) reg = 65536; device_printf(dev, "CLK=%uMhz/%d=%luhz\n", SPI_CORE_CLK / 1000000, reg, SPI_CORE_CLK / reg); reg = BCM_SPI_READ(sc, SPI_DLEN) & SPI_DLEN_MASK; device_printf(dev, "DLEN=%d\n", reg); reg = BCM_SPI_READ(sc, SPI_LTOH) & SPI_LTOH_MASK; device_printf(dev, "LTOH=%d\n", reg); reg = BCM_SPI_READ(sc, SPI_DC); device_printf(dev, "DC=RPANIC=%#x RDREQ=%#x TPANIC=%#x TDREQ=%#x\n", (reg & SPI_DC_RPANIC_MASK) >> SPI_DC_RPANIC_SHIFT, (reg & SPI_DC_RDREQ_MASK) >> SPI_DC_RDREQ_SHIFT, (reg & SPI_DC_TPANIC_MASK) >> SPI_DC_TPANIC_SHIFT, (reg & SPI_DC_TDREQ_MASK) >> SPI_DC_TDREQ_SHIFT); } #endif static void bcm_spi_modifyreg(struct bcm_spi_softc *sc, uint32_t off, uint32_t mask, uint32_t value) { uint32_t reg; mtx_assert(&sc->sc_mtx, MA_OWNED); reg = BCM_SPI_READ(sc, off); reg &= ~mask; reg |= value; BCM_SPI_WRITE(sc, off, reg); } static int bcm_spi_clock_proc(SYSCTL_HANDLER_ARGS) { struct bcm_spi_softc *sc; uint32_t clk; int error; sc = (struct bcm_spi_softc *)arg1; BCM_SPI_LOCK(sc); clk = BCM_SPI_READ(sc, SPI_CLK); BCM_SPI_UNLOCK(sc); clk &= 0xffff; if (clk == 0) clk = 65536; clk = SPI_CORE_CLK / clk; error = sysctl_handle_int(oidp, &clk, sizeof(clk), req); if (error != 0 || req->newptr == NULL) return (error); clk = SPI_CORE_CLK / clk; if (clk <= 1) clk = 2; else if (clk % 2) clk--; if (clk > 0xffff) clk = 0; BCM_SPI_LOCK(sc); BCM_SPI_WRITE(sc, SPI_CLK, clk); BCM_SPI_UNLOCK(sc); return (0); } static int bcm_spi_cs_bit_proc(SYSCTL_HANDLER_ARGS, uint32_t bit) { struct bcm_spi_softc *sc; uint32_t reg; int error; sc = (struct bcm_spi_softc *)arg1; BCM_SPI_LOCK(sc); reg = BCM_SPI_READ(sc, SPI_CS); BCM_SPI_UNLOCK(sc); reg = (reg & bit) ? 1 : 0; error = sysctl_handle_int(oidp, ®, sizeof(reg), req); if (error != 0 || req->newptr == NULL) return (error); if (reg) reg = bit; BCM_SPI_LOCK(sc); bcm_spi_modifyreg(sc, SPI_CS, bit, reg); BCM_SPI_UNLOCK(sc); return (0); } static int bcm_spi_cpol_proc(SYSCTL_HANDLER_ARGS) { return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CPOL)); } static int bcm_spi_cpha_proc(SYSCTL_HANDLER_ARGS) { return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CPHA)); } static int bcm_spi_cspol0_proc(SYSCTL_HANDLER_ARGS) { return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL0)); } static int bcm_spi_cspol1_proc(SYSCTL_HANDLER_ARGS) { return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL1)); } static void bcm_spi_sysctl_init(struct bcm_spi_softc *sc) { struct sysctl_ctx_list *ctx; struct sysctl_oid *tree_node; struct sysctl_oid_list *tree; /* * Add system sysctl tree/handlers. */ ctx = device_get_sysctl_ctx(sc->sc_dev); tree_node = device_get_sysctl_tree(sc->sc_dev); tree = SYSCTL_CHILDREN(tree_node); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_spi_clock_proc, "IU", "SPI BUS clock frequency"); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cpol", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_spi_cpol_proc, "IU", "SPI BUS clock polarity"); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cpha", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_spi_cpha_proc, "IU", "SPI BUS clock phase"); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol0", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_spi_cspol0_proc, "IU", "SPI BUS chip select 0 polarity"); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol1", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_spi_cspol1_proc, "IU", "SPI BUS chip select 1 polarity"); } static int bcm_spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "BCM2708/2835 SPI controller"); return (BUS_PROBE_DEFAULT); } static int bcm_spi_attach(device_t dev) { struct bcm_spi_softc *sc; device_t gpio; int i, rid; if (device_get_unit(dev) != 0) { device_printf(dev, "only one SPI controller supported\n"); return (ENXIO); } sc = device_get_softc(dev); sc->sc_dev = dev; /* Configure the GPIO pins to ALT0 function to enable SPI the pins. */ gpio = devclass_get_device(devclass_find("gpio"), 0); if (!gpio) { device_printf(dev, "cannot find gpio0\n"); return (ENXIO); } for (i = 0; i < nitems(bcm_spi_pins); i++) bcm_gpio_set_alternate(gpio, bcm_spi_pins[i], BCM_GPIO_ALT0); rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "cannot allocate memory window\n"); return (ENXIO); } sc->sc_bst = rman_get_bustag(sc->sc_mem_res); sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); rid = 0; sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (!sc->sc_irq_res) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); device_printf(dev, "cannot allocate interrupt\n"); return (ENXIO); } /* Hook up our interrupt handler. */ if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, bcm_spi_intr, sc, &sc->sc_intrhand)) { bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); device_printf(dev, "cannot setup the interrupt handler\n"); return (ENXIO); } mtx_init(&sc->sc_mtx, "bcm_spi", NULL, MTX_DEF); /* Add sysctl nodes. */ bcm_spi_sysctl_init(sc); #ifdef BCM_SPI_DEBUG bcm_spi_printr(dev); #endif /* * Enable the SPI controller. Clear the rx and tx FIFO. * Defaults to SPI mode 0. */ BCM_SPI_WRITE(sc, SPI_CS, SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO); /* Set the SPI clock to 500Khz. */ BCM_SPI_WRITE(sc, SPI_CLK, SPI_CORE_CLK / 500000); #ifdef BCM_SPI_DEBUG bcm_spi_printr(dev); #endif device_add_child(dev, "spibus", -1); return (bus_generic_attach(dev)); } static int bcm_spi_detach(device_t dev) { struct bcm_spi_softc *sc; bus_generic_detach(dev); sc = device_get_softc(dev); mtx_destroy(&sc->sc_mtx); if (sc->sc_intrhand) bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); if (sc->sc_irq_res) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (0); } static void bcm_spi_fill_fifo(struct bcm_spi_softc *sc) { struct spi_command *cmd; uint32_t cs, written; uint8_t *data; cmd = sc->sc_cmd; cs = BCM_SPI_READ(sc, SPI_CS) & (SPI_CS_TA | SPI_CS_TXD); while (sc->sc_written < sc->sc_len && cs == (SPI_CS_TA | SPI_CS_TXD)) { data = (uint8_t *)cmd->tx_cmd; written = sc->sc_written++; if (written >= cmd->tx_cmd_sz) { data = (uint8_t *)cmd->tx_data; written -= cmd->tx_cmd_sz; } BCM_SPI_WRITE(sc, SPI_FIFO, data[written]); cs = BCM_SPI_READ(sc, SPI_CS) & (SPI_CS_TA | SPI_CS_TXD); } } static void bcm_spi_drain_fifo(struct bcm_spi_softc *sc) { struct spi_command *cmd; uint32_t cs, read; uint8_t *data; cmd = sc->sc_cmd; cs = BCM_SPI_READ(sc, SPI_CS) & SPI_CS_RXD; while (sc->sc_read < sc->sc_len && cs == SPI_CS_RXD) { data = (uint8_t *)cmd->rx_cmd; read = sc->sc_read++; if (read >= cmd->rx_cmd_sz) { data = (uint8_t *)cmd->rx_data; read -= cmd->rx_cmd_sz; } data[read] = BCM_SPI_READ(sc, SPI_FIFO) & 0xff; cs = BCM_SPI_READ(sc, SPI_CS) & SPI_CS_RXD; } } static void bcm_spi_intr(void *arg) { struct bcm_spi_softc *sc; sc = (struct bcm_spi_softc *)arg; BCM_SPI_LOCK(sc); /* Filter stray interrupts. */ if ((sc->sc_flags & BCM_SPI_BUSY) == 0) { BCM_SPI_UNLOCK(sc); return; } /* TX - Fill up the FIFO. */ bcm_spi_fill_fifo(sc); /* RX - Drain the FIFO. */ bcm_spi_drain_fifo(sc); /* Check for end of transfer. */ if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len) { /* Disable interrupts and the SPI engine. */ bcm_spi_modifyreg(sc, SPI_CS, SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 0); wakeup(sc->sc_dev); } BCM_SPI_UNLOCK(sc); } static int bcm_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct bcm_spi_softc *sc; - int cs, err; + uint32_t cs; + int err; sc = device_get_softc(dev); KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("TX/RX command sizes should be equal")); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("TX/RX data sizes should be equal")); /* Get the proper chip select for this child. */ spibus_get_cs(child, &cs); - if (cs < 0 || cs > 2) { + if (cs > 2) { device_printf(dev, "Invalid chip select %d requested by %s\n", cs, device_get_nameunit(child)); return (EINVAL); } BCM_SPI_LOCK(sc); /* If the controller is in use wait until it is available. */ while (sc->sc_flags & BCM_SPI_BUSY) mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_spi", 0); /* Now we have control over SPI controller. */ sc->sc_flags = BCM_SPI_BUSY; /* Clear the FIFO. */ bcm_spi_modifyreg(sc, SPI_CS, SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO, SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO); /* Save a pointer to the SPI command. */ sc->sc_cmd = cmd; sc->sc_read = 0; sc->sc_written = 0; sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz; /* * Set the CS for this transaction, enable interrupts and announce * we're ready to tx. This will kick off the first interrupt. */ bcm_spi_modifyreg(sc, SPI_CS, SPI_CS_MASK | SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, cs | SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD); /* Wait for the transaction to complete. */ err = mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_spi", hz * 2); /* Make sure the SPI engine and interrupts are disabled. */ bcm_spi_modifyreg(sc, SPI_CS, SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 0); /* Release the controller and wakeup the next thread waiting for it. */ sc->sc_flags = 0; wakeup_one(dev); BCM_SPI_UNLOCK(sc); /* * Check for transfer timeout. The SPI controller doesn't * return errors. */ if (err == EWOULDBLOCK) { device_printf(sc->sc_dev, "SPI error\n"); err = EIO; } return (err); } static phandle_t bcm_spi_get_node(device_t bus, device_t dev) { /* We only have one child, the SPI bus, which needs our own node. */ return (ofw_bus_get_node(bus)); } static device_method_t bcm_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, bcm_spi_probe), DEVMETHOD(device_attach, bcm_spi_attach), DEVMETHOD(device_detach, bcm_spi_detach), /* SPI interface */ DEVMETHOD(spibus_transfer, bcm_spi_transfer), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, bcm_spi_get_node), DEVMETHOD_END }; static devclass_t bcm_spi_devclass; static driver_t bcm_spi_driver = { "spi", bcm_spi_methods, sizeof(struct bcm_spi_softc), }; DRIVER_MODULE(bcm2835_spi, simplebus, bcm_spi_driver, bcm_spi_devclass, 0, 0); Index: stable/11/sys/arm/ti/ti_spi.c =================================================================== --- stable/11/sys/arm/ti/ti_spi.c (revision 310155) +++ stable/11/sys/arm/ti/ti_spi.c (revision 310156) @@ -1,582 +1,582 @@ /*- * Copyright (c) 2016 Rubicon Communications, LLC (Netgate) * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" static void ti_spi_intr(void *); static int ti_spi_detach(device_t); #undef TI_SPI_DEBUG #ifdef TI_SPI_DEBUG #define IRQSTATUSBITS \ "\020\1TX0_EMPTY\2TX0_UNDERFLOW\3RX0_FULL\4RX0_OVERFLOW" \ "\5TX1_EMPTY\6TX1_UNDERFLOW\7RX1_FULL\11TX2_EMPTY" \ "\12TX1_UNDERFLOW\13RX2_FULL\15TX3_EMPTY\16TX3_UNDERFLOW" \ "\17RX3_FULL\22EOW" #define CONFBITS \ "\020\1PHA\2POL\7EPOL\17DMAW\20DMAR\21DPE0\22DPE1\23IS" \ "\24TURBO\25FORCE\30SBE\31SBPOL\34FFEW\35FFER\36CLKG" #define STATBITS \ "\020\1RXS\2TXS\3EOT\4TXFFE\5TXFFF\6RXFFE\7RXFFFF" #define MODULCTRLBITS \ "\020\1SINGLE\2NOSPIEN\3SLAVE\4SYST\10MOA\11FDAA" #define CTRLBITS \ "\020\1ENABLED" static void ti_spi_printr(device_t dev) { int clk, conf, ctrl, div, i, j, wl; struct ti_spi_softc *sc; uint32_t reg; sc = device_get_softc(dev); reg = TI_SPI_READ(sc, MCSPI_SYSCONFIG); device_printf(dev, "SYSCONFIG: %#x\n", reg); reg = TI_SPI_READ(sc, MCSPI_SYSSTATUS); device_printf(dev, "SYSSTATUS: %#x\n", reg); reg = TI_SPI_READ(sc, MCSPI_IRQSTATUS); device_printf(dev, "IRQSTATUS: 0x%b\n", reg, IRQSTATUSBITS); reg = TI_SPI_READ(sc, MCSPI_IRQENABLE); device_printf(dev, "IRQENABLE: 0x%b\n", reg, IRQSTATUSBITS); reg = TI_SPI_READ(sc, MCSPI_MODULCTRL); device_printf(dev, "MODULCTRL: 0x%b\n", reg, MODULCTRLBITS); for (i = 0; i < sc->sc_numcs; i++) { ctrl = TI_SPI_READ(sc, MCSPI_CTRL_CH(i)); conf = TI_SPI_READ(sc, MCSPI_CONF_CH(i)); device_printf(dev, "CH%dCONF: 0x%b\n", i, conf, CONFBITS); if (conf & MCSPI_CONF_CLKG) { div = (conf >> MCSPI_CONF_CLK_SHIFT) & MCSPI_CONF_CLK_MSK; div |= ((ctrl >> MCSPI_CTRL_EXTCLK_SHIFT) & MCSPI_CTRL_EXTCLK_MSK) << 4; } else { div = 1; j = (conf >> MCSPI_CONF_CLK_SHIFT) & MCSPI_CONF_CLK_MSK; while (j-- > 0) div <<= 1; } clk = TI_SPI_GCLK / div; wl = ((conf >> MCSPI_CONF_WL_SHIFT) & MCSPI_CONF_WL_MSK) + 1; device_printf(dev, "wordlen: %-2d clock: %d\n", wl, clk); reg = TI_SPI_READ(sc, MCSPI_STAT_CH(i)); device_printf(dev, "CH%dSTAT: 0x%b\n", i, reg, STATBITS); device_printf(dev, "CH%dCTRL: 0x%b\n", i, ctrl, CTRLBITS); } reg = TI_SPI_READ(sc, MCSPI_XFERLEVEL); device_printf(dev, "XFERLEVEL: %#x\n", reg); } #endif static void ti_spi_set_clock(struct ti_spi_softc *sc, int ch, int freq) { uint32_t clkdiv, conf, div, extclk, reg; clkdiv = TI_SPI_GCLK / freq; if (clkdiv > MCSPI_EXTCLK_MSK) { extclk = 0; clkdiv = 0; div = 1; while (TI_SPI_GCLK / div > freq && clkdiv <= 0xf) { clkdiv++; div <<= 1; } conf = clkdiv << MCSPI_CONF_CLK_SHIFT; } else { extclk = clkdiv >> 4; clkdiv &= MCSPI_CONF_CLK_MSK; conf = MCSPI_CONF_CLKG | clkdiv << MCSPI_CONF_CLK_SHIFT; } reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(ch)); reg &= ~(MCSPI_CTRL_EXTCLK_MSK << MCSPI_CTRL_EXTCLK_SHIFT); reg |= extclk << MCSPI_CTRL_EXTCLK_SHIFT; TI_SPI_WRITE(sc, MCSPI_CTRL_CH(ch), reg); reg = TI_SPI_READ(sc, MCSPI_CONF_CH(ch)); reg &= ~(MCSPI_CONF_CLKG | MCSPI_CONF_CLK_MSK << MCSPI_CONF_CLK_SHIFT); TI_SPI_WRITE(sc, MCSPI_CONF_CH(ch), reg | conf); } static int ti_spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "ti,omap4-mcspi")) return (ENXIO); device_set_desc(dev, "TI McSPI controller"); return (BUS_PROBE_DEFAULT); } static int ti_spi_attach(device_t dev) { int clk_id, err, i, rid, timeout; struct ti_spi_softc *sc; uint32_t rev; sc = device_get_softc(dev); sc->sc_dev = dev; /* * Get the MMCHS device id from FDT. If it's not there use the newbus * unit number (which will work as long as the devices are in order and * none are skipped in the fdt). Note that this is a property we made * up and added in freebsd, it doesn't exist in the published bindings. */ clk_id = ti_hwmods_get_clock(dev); if (clk_id == INVALID_CLK_IDENT) { device_printf(dev, "failed to get clock based on hwmods property\n"); return (EINVAL); } /* Activate the McSPI module. */ err = ti_prcm_clk_enable(clk_id); if (err) { device_printf(dev, "Error: failed to activate source clock\n"); return (err); } /* Get the number of available channels. */ if ((OF_getencprop(ofw_bus_get_node(dev), "ti,spi-num-cs", &sc->sc_numcs, sizeof(sc->sc_numcs))) <= 0) { sc->sc_numcs = 2; } rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "cannot allocate memory window\n"); return (ENXIO); } sc->sc_bst = rman_get_bustag(sc->sc_mem_res); sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); rid = 0; sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (!sc->sc_irq_res) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); device_printf(dev, "cannot allocate interrupt\n"); return (ENXIO); } /* Hook up our interrupt handler. */ if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, ti_spi_intr, sc, &sc->sc_intrhand)) { bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); device_printf(dev, "cannot setup the interrupt handler\n"); return (ENXIO); } mtx_init(&sc->sc_mtx, "ti_spi", NULL, MTX_DEF); /* Issue a softreset to the controller */ TI_SPI_WRITE(sc, MCSPI_SYSCONFIG, MCSPI_SYSCONFIG_SOFTRESET); timeout = 1000; while (!(TI_SPI_READ(sc, MCSPI_SYSSTATUS) & MCSPI_SYSSTATUS_RESETDONE)) { if (--timeout == 0) { device_printf(dev, "Error: Controller reset operation timed out\n"); ti_spi_detach(dev); return (ENXIO); } DELAY(100); } /* Print the McSPI module revision. */ rev = TI_SPI_READ(sc, MCSPI_REVISION); device_printf(dev, "scheme: %#x func: %#x rtl: %d rev: %d.%d custom rev: %d\n", (rev >> MCSPI_REVISION_SCHEME_SHIFT) & MCSPI_REVISION_SCHEME_MSK, (rev >> MCSPI_REVISION_FUNC_SHIFT) & MCSPI_REVISION_FUNC_MSK, (rev >> MCSPI_REVISION_RTL_SHIFT) & MCSPI_REVISION_RTL_MSK, (rev >> MCSPI_REVISION_MAJOR_SHIFT) & MCSPI_REVISION_MAJOR_MSK, (rev >> MCSPI_REVISION_MINOR_SHIFT) & MCSPI_REVISION_MINOR_MSK, (rev >> MCSPI_REVISION_CUSTOM_SHIFT) & MCSPI_REVISION_CUSTOM_MSK); /* Set Master mode, single channel. */ TI_SPI_WRITE(sc, MCSPI_MODULCTRL, MCSPI_MODULCTRL_SINGLE); /* Clear pending interrupts and disable interrupts. */ TI_SPI_WRITE(sc, MCSPI_IRQENABLE, 0x0); TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, 0xffff); for (i = 0; i < sc->sc_numcs; i++) { /* * Default to SPI mode 0, CS active low, 8 bits word length and * 500kHz clock. */ TI_SPI_WRITE(sc, MCSPI_CONF_CH(i), MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL | (8 - 1) << MCSPI_CONF_WL_SHIFT); /* Set initial clock - 500kHz. */ ti_spi_set_clock(sc, i, 500000); } #ifdef TI_SPI_DEBUG ti_spi_printr(dev); #endif device_add_child(dev, "spibus", -1); return (bus_generic_attach(dev)); } static int ti_spi_detach(device_t dev) { struct ti_spi_softc *sc; sc = device_get_softc(dev); /* Clear pending interrupts and disable interrupts. */ TI_SPI_WRITE(sc, MCSPI_IRQENABLE, 0); TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, 0xffff); /* Reset controller. */ TI_SPI_WRITE(sc, MCSPI_SYSCONFIG, MCSPI_SYSCONFIG_SOFTRESET); bus_generic_detach(dev); mtx_destroy(&sc->sc_mtx); if (sc->sc_intrhand) bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); if (sc->sc_irq_res) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (0); } static int ti_spi_fill_fifo(struct ti_spi_softc *sc) { int bytes, timeout; struct spi_command *cmd; uint32_t written; uint8_t *data; cmd = sc->sc_cmd; bytes = min(sc->sc_len - sc->sc_written, sc->sc_fifolvl); while (bytes-- > 0) { data = (uint8_t *)cmd->tx_cmd; written = sc->sc_written++; if (written >= cmd->tx_cmd_sz) { data = (uint8_t *)cmd->tx_data; written -= cmd->tx_cmd_sz; } if (sc->sc_fifolvl == 1) { /* FIFO disabled. */ timeout = 1000; while (--timeout > 0 && (TI_SPI_READ(sc, MCSPI_STAT_CH(sc->sc_cs)) & MCSPI_STAT_TXS) == 0) { DELAY(100); } if (timeout == 0) return (-1); } TI_SPI_WRITE(sc, MCSPI_TX_CH(sc->sc_cs), data[written]); } return (0); } static int ti_spi_drain_fifo(struct ti_spi_softc *sc) { int bytes, timeout; struct spi_command *cmd; uint32_t read; uint8_t *data; cmd = sc->sc_cmd; bytes = min(sc->sc_len - sc->sc_read, sc->sc_fifolvl); while (bytes-- > 0) { data = (uint8_t *)cmd->rx_cmd; read = sc->sc_read++; if (read >= cmd->rx_cmd_sz) { data = (uint8_t *)cmd->rx_data; read -= cmd->rx_cmd_sz; } if (sc->sc_fifolvl == 1) { /* FIFO disabled. */ timeout = 1000; while (--timeout > 0 && (TI_SPI_READ(sc, MCSPI_STAT_CH(sc->sc_cs)) & MCSPI_STAT_RXS) == 0) { DELAY(100); } if (timeout == 0) return (-1); } data[read] = TI_SPI_READ(sc, MCSPI_RX_CH(sc->sc_cs)); } return (0); } static void ti_spi_intr(void *arg) { int eow; struct ti_spi_softc *sc; uint32_t status; eow = 0; sc = (struct ti_spi_softc *)arg; TI_SPI_LOCK(sc); status = TI_SPI_READ(sc, MCSPI_IRQSTATUS); /* * No new TX_empty or RX_full event will be asserted while the CPU has * not performed the number of writes or reads defined by * MCSPI_XFERLEVEL[AEL] and MCSPI_XFERLEVEL[AFL]. It is responsibility * of CPU perform the right number of writes and reads. */ if (status & MCSPI_IRQ_TX0_EMPTY) ti_spi_fill_fifo(sc); if (status & MCSPI_IRQ_RX0_FULL) ti_spi_drain_fifo(sc); if (status & MCSPI_IRQ_EOW) eow = 1; /* Clear interrupt status. */ TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, status); /* Check for end of transfer. */ if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len) { sc->sc_flags |= TI_SPI_DONE; wakeup(sc->sc_dev); } TI_SPI_UNLOCK(sc); } static int ti_spi_pio_transfer(struct ti_spi_softc *sc) { while (sc->sc_len - sc->sc_written > 0) { if (ti_spi_fill_fifo(sc) == -1) return (EIO); if (ti_spi_drain_fifo(sc) == -1) return (EIO); } return (0); } static int ti_spi_gcd(int a, int b) { int m; while ((m = a % b) != 0) { a = b; b = m; } return (b); } static int ti_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { - int cs, err; + int err; struct ti_spi_softc *sc; - uint32_t reg; + uint32_t reg, cs; sc = device_get_softc(dev); KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("TX/RX command sizes should be equal")); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("TX/RX data sizes should be equal")); /* Get the proper chip select for this child. */ spibus_get_cs(child, &cs); - if (cs < 0 || cs > sc->sc_numcs) { + if (cs > sc->sc_numcs) { device_printf(dev, "Invalid chip select %d requested by %s\n", cs, device_get_nameunit(child)); return (EINVAL); } TI_SPI_LOCK(sc); /* If the controller is in use wait until it is available. */ while (sc->sc_flags & TI_SPI_BUSY) mtx_sleep(dev, &sc->sc_mtx, 0, "ti_spi", 0); /* Now we have control over SPI controller. */ sc->sc_flags = TI_SPI_BUSY; /* Save the SPI command data. */ sc->sc_cs = cs; sc->sc_cmd = cmd; sc->sc_read = 0; sc->sc_written = 0; sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz; sc->sc_fifolvl = ti_spi_gcd(sc->sc_len, TI_SPI_FIFOSZ); if (sc->sc_fifolvl < 2 || sc->sc_len > 0xffff) sc->sc_fifolvl = 1; /* FIFO disabled. */ /* Disable FIFO for now. */ sc->sc_fifolvl = 1; /* Use a safe clock - 500kHz. */ ti_spi_set_clock(sc, sc->sc_cs, 500000); /* Disable the FIFO. */ TI_SPI_WRITE(sc, MCSPI_XFERLEVEL, 0); /* 8 bits word, d0 miso, d1 mosi, mode 0 and CS active low. */ reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); reg &= ~(MCSPI_CONF_FFER | MCSPI_CONF_FFEW | MCSPI_CONF_SBPOL | MCSPI_CONF_SBE | MCSPI_CONF_TURBO | MCSPI_CONF_IS | MCSPI_CONF_DPE1 | MCSPI_CONF_DPE0 | MCSPI_CONF_DMAR | MCSPI_CONF_DMAW | MCSPI_CONF_EPOL); reg |= MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL | MCSPI_CONF_WL8BITS; TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); #if 0 /* Enable channel interrupts. */ reg = TI_SPI_READ(sc, MCSPI_IRQENABLE); reg |= 0xf; TI_SPI_WRITE(sc, MCSPI_IRQENABLE, reg); #endif /* Start the transfer. */ reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(sc->sc_cs)); TI_SPI_WRITE(sc, MCSPI_CTRL_CH(sc->sc_cs), reg | MCSPI_CTRL_ENABLE); /* Force CS on. */ reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg |= MCSPI_CONF_FORCE); err = 0; if (sc->sc_fifolvl == 1) err = ti_spi_pio_transfer(sc); /* Force CS off. */ reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); reg &= ~MCSPI_CONF_FORCE; TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); /* Disable IRQs. */ reg = TI_SPI_READ(sc, MCSPI_IRQENABLE); reg &= ~0xf; TI_SPI_WRITE(sc, MCSPI_IRQENABLE, reg); TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, 0xf); /* Disable the SPI channel. */ reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(sc->sc_cs)); reg &= ~MCSPI_CTRL_ENABLE; TI_SPI_WRITE(sc, MCSPI_CTRL_CH(sc->sc_cs), reg); /* Disable FIFO. */ reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); reg &= ~(MCSPI_CONF_FFER | MCSPI_CONF_FFEW); TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); /* Release the controller and wakeup the next thread waiting for it. */ sc->sc_flags = 0; wakeup_one(dev); TI_SPI_UNLOCK(sc); return (err); } static phandle_t ti_spi_get_node(device_t bus, device_t dev) { /* Share controller node with spibus. */ return (ofw_bus_get_node(bus)); } static device_method_t ti_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ti_spi_probe), DEVMETHOD(device_attach, ti_spi_attach), DEVMETHOD(device_detach, ti_spi_detach), /* SPI interface */ DEVMETHOD(spibus_transfer, ti_spi_transfer), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, ti_spi_get_node), DEVMETHOD_END }; static devclass_t ti_spi_devclass; static driver_t ti_spi_driver = { "spi", ti_spi_methods, sizeof(struct ti_spi_softc), }; DRIVER_MODULE(ti_spi, simplebus, ti_spi_driver, ti_spi_devclass, 0, 0); Index: stable/11 =================================================================== --- stable/11 (revision 310155) +++ stable/11 (revision 310156) Property changes on: stable/11 ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head:r309912