Index: head/sys/mips/ingenic/jz4780_aic.h =================================================================== --- head/sys/mips/ingenic/jz4780_aic.h (nonexistent) +++ head/sys/mips/ingenic/jz4780_aic.h (revision 309739) @@ -0,0 +1,74 @@ +/*- + * Copyright (c) 2016 Ruslan Bukin + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 + * ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#define AICFR 0x00 /* AIC Configuration Register */ +#define AICFR_TFTH_S 16 /* Transmit FIFO threshold for interrupt or DMA request. */ +#define AICFR_TFTH_M (0x1f << AICFR_TFTH_S) +#define AICFR_TFTH(x) ((x) << AICFR_TFTH_S) +#define AICFR_RFTH_S 24 /* Receive FIFO threshold for interrupt or DMA request. */ +#define AICFR_RFTH_M (0x0f << AICFR_RFTH_S) +#define AICFR_RFTH(x) ((x) << AICFR_RFTH_S) +#define AICFR_ICDC (1 << 5) /* Internal CODEC used. */ +#define AICFR_AUSEL (1 << 4) /* Audio Unit Select */ +#define AICFR_RST (1 << 3) /* Reset AIC. */ +#define AICFR_BCKD (1 << 2) /* BIT_CLK Direction. */ +#define AICFR_SYNCD (1 << 1) /* SYNC is generated internally and driven out to the CODEC. */ +#define AICFR_ENB (1 << 0) /* Enable AIC Controller. */ +#define AICCR 0x04 /* AIC Common Control Register */ +#define AICCR_TFLUSH (1 << 8) /* Transmit FIFO Flush. */ +#define AICCR_RFLUSH (1 << 7) /* Receive FIFO Flush. */ +#define AICCR_CHANNEL_S 24 +#define AICCR_CHANNEL_M (0x7 << AICCR_CHANNEL_S) +#define AICCR_CHANNEL_2 (0x1 << AICCR_CHANNEL_S) /* 2 channels, stereo */ +#define AICCR_ISS_S 16 /* Input Sample Size. */ +#define AICCR_ISS_M (0x7 << AICCR_ISS_S) +#define AICCR_ISS_16 (0x1 << AICCR_ISS_S) +#define AICCR_OSS_S 19 /* Output Sample Size. */ +#define AICCR_OSS_M (0x7 << AICCR_OSS_S) +#define AICCR_OSS_16 (0x1 << AICCR_OSS_S) +#define AICCR_RDMS (1 << 15) /* Receive DMA enable. */ +#define AICCR_TDMS (1 << 14) /* Transmit DMA enable. */ +#define AICCR_ENLBF (1 << 2) /* Enable AIC Loop Back Function. */ +#define AICCR_ERPL (1 << 1) /* Enable Playing Back function. */ +#define I2SCR 0x10 /* AIC I2S/MSB-justified Control */ +#define I2SCR_ESCLK (1 << 4) /* Enable SYSCLK output. */ +#define I2SCR_AMSL (1 << 0) /* Select MSB-Justified Operation Mode. */ +#define AICSR 0x14 /* AIC FIFO Status Register Register */ +#define I2SSR 0x1C /* AIC I2S/MSB-justified Status Register */ +#define I2SDIV 0x30 /* AIC I2S/MSB-justified Clock Divider Register */ +#define AICDR 0x34 /* AIC FIFO Data Port Register */ +#define SPENA 0x80 /* SPDIF Enable Register */ +#define SPCTRL 0x84 /* SPDIF Control Register */ +#define SPSTATE 0x88 /* SPDIF Status Register */ +#define SPCFG1 0x8C /* SPDIF Configure 1 Register */ +#define SPCFG2 0x90 /* SPDIF Configure 2 Register */ +#define SPFIFO 0x94 /* SPDIF FIFO Register */ Property changes on: head/sys/mips/ingenic/jz4780_aic.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/mips/ingenic/jz4780_pdma.h =================================================================== --- head/sys/mips/ingenic/jz4780_pdma.h (revision 309738) +++ head/sys/mips/ingenic/jz4780_pdma.h (revision 309739) @@ -1,68 +1,107 @@ /*- * Copyright (c) 2016 Ruslan Bukin * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* DMA Channel Registers */ #define PDMA_DSA(n) (0x00 + 0x20 * n) /* Channel n Source Address */ #define PDMA_DTA(n) (0x04 + 0x20 * n) /* Channel n Target Address */ #define PDMA_DTC(n) (0x08 + 0x20 * n) /* Channel n Transfer Count */ #define PDMA_DRT(n) (0x0C + 0x20 * n) /* Channel n Request Source */ +#define DRT_AUTO (1 << 3) /* Auto-request. */ #define PDMA_DCS(n) (0x10 + 0x20 * n) /* Channel n Control/Status */ +#define DCS_DES8 (1 << 30) /* Descriptor 8 Word. */ +#define DCS_AR (1 << 4) /* Address Error. */ +#define DCS_TT (1 << 3) /* Transfer Terminate. */ +#define DCS_HLT (1 << 2) /* DMA halt. */ +#define DCS_CTE (1 << 0) /* Channel transfer enable. */ #define PDMA_DCM(n) (0x14 + 0x20 * n) /* Channel n Command */ +#define DCM_SAI (1 << 23) /* Source Address Increment. */ +#define DCM_DAI (1 << 22) /* Destination Address Increment. */ + +#define DCM_SP_S 14 /* Source port width. */ +#define DCM_SP_M (0x3 << DCM_SP_S) +#define DCM_SP_1 (0x1 << DCM_SP_S) /* 1 byte */ +#define DCM_SP_2 (0x2 << DCM_SP_S) /* 2 bytes */ +#define DCM_SP_4 (0x0 << DCM_SP_S) /* 4 bytes */ + +#define DCM_DP_S 12 /* Destination port width. */ +#define DCM_DP_M (0x3 << DCM_DP_S) +#define DCM_DP_1 (0x1 << DCM_DP_S) /* 1 byte */ +#define DCM_DP_2 (0x2 << DCM_DP_S) /* 2 bytes */ +#define DCM_DP_4 (0x0 << DCM_DP_S) /* 4 bytes */ + +#define DCM_TSZ_S 8 /* Transfer Data Size of a data unit. */ +#define DCM_TSZ_M (0x7 << DCM_TSZ_S) +#define DCM_TSZ_1 (0x1 << DCM_TSZ_S) +#define DCM_TSZ_2 (0x2 << DCM_TSZ_S) +#define DCM_TSZ_4 (0x0 << DCM_TSZ_S) +#define DCM_TSZ_16 (0x3 << DCM_TSZ_S) +#define DCM_TSZ_32 (0x4 << DCM_TSZ_S) +#define DCM_TSZ_64 (0x5 << DCM_TSZ_S) +#define DCM_TSZ_128 (0x6 << DCM_TSZ_S) +#define DCM_TIE (1 << 1) /* Transfer Interrupt Enable (TIE). */ +#define DCM_LINK (1 << 0) /* Descriptor Link Enable. */ #define PDMA_DDA(n) (0x18 + 0x20 * n) /* Channel n Descriptor Address */ #define PDMA_DSD(n) (0x1C + 0x20 * n) /* Channel n Stride Difference */ /* Global Control Registers */ #define PDMA_DMAC 0x1000 /* DMA Control */ +#define DMAC_FMSC (1 << 31) +#define DMAC_INTCC_S 17 +#define DMAC_INTCC_M (0x1f << DMAC_INTCC_S) +#define DMAC_INTCE (1 << 16) /* Permit INTC_IRQ to be bound to one of programmable channel. */ +#define DMAC_HLT (1 << 3) /* Global halt status */ +#define DMAC_AR (1 << 2) /* Global address error status */ +#define DMAC_DMAE (1 << 0) /* Enable DMA. */ #define PDMA_DIRQP 0x1004 /* DMA Interrupt Pending */ #define PDMA_DDB 0x1008 /* DMA Doorbell */ #define PDMA_DDS 0x100C /* DMA Doorbell Set */ #define PDMA_DIP 0x1010 /* Descriptor Interrupt Pending */ #define PDMA_DIC 0x1014 /* Descriptor Interrupt Clear */ #define PDMA_DMACP 0x101C /* DMA Channel Programmable */ #define PDMA_DSIRQP 0x1020 /* Channel soft IRQ to MCU */ #define PDMA_DSIRQM 0x1024 /* Channel soft IRQ mask */ #define PDMA_DCIRQP 0x1028 /* Channel IRQ to MCU */ #define PDMA_DCIRQM 0x102C /* Channel IRQ to MCU mask */ #define PDMA_DMCS 0x1030 /* MCU Control and Status */ #define PDMA_DMNMB 0x1034 /* MCU Normal Mailbox */ #define PDMA_DMSMB 0x1038 /* MCU Security Mailbox */ #define PDMA_DMINT 0x103C /* MCU Interrupt */ struct pdma_hwdesc { uint32_t dcm; /* DMA Channel Command */ uint32_t dsa; /* DMA Source Address */ uint32_t dta; /* DMA Target Address */ uint32_t dtc; /* DMA Transfer Counter */ uint32_t sd; /* Stride Address */ uint32_t drt; /* DMA Request Type */ uint32_t reserved[2]; };