Index: head/sys/arm/annapurna/alpine/alpine_pci.c =================================================================== --- head/sys/arm/annapurna/alpine/alpine_pci.c (revision 308930) +++ head/sys/arm/annapurna/alpine/alpine_pci.c (revision 308931) @@ -1,158 +1,159 @@ /*- * Copyright (c) 2015,2016 Annapurna Labs Ltd. and affiliates * All rights reserved. * * Developed by Semihalf. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Alpine PCI/PCI-Express controller driver. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include +#include #include #include #include "pcib_if.h" #include "contrib/alpine-hal/al_hal_unit_adapter_regs.h" #include "contrib/alpine-hal/al_hal_pcie.h" #include "contrib/alpine-hal/al_hal_pcie_axi_reg.h" #define ANNAPURNA_VENDOR_ID 0x1c36 /* Forward prototypes */ static int al_pcib_probe(device_t); static int al_pcib_attach(device_t); static void al_pcib_fixup(device_t); static struct ofw_compat_data compat_data[] = { {"annapurna-labs,al-internal-pcie", true}, {"annapurna-labs,alpine-internal-pcie", true}, {NULL, false} }; /* * Bus interface definitions. */ static device_method_t al_pcib_methods[] = { /* Device interface */ DEVMETHOD(device_probe, al_pcib_probe), DEVMETHOD(device_attach, al_pcib_attach), DEVMETHOD_END }; DEFINE_CLASS_1(pcib, al_pcib_driver, al_pcib_methods, - sizeof(struct generic_pcie_softc), generic_pcie_driver); + sizeof(struct generic_pcie_fdt_softc), generic_pcie_fdt_driver); static devclass_t anpa_pcib_devclass; DRIVER_MODULE(alpine_pcib, simplebus, al_pcib_driver, anpa_pcib_devclass, 0, 0); DRIVER_MODULE(alpine_pcib, ofwbus, al_pcib_driver, anpa_pcib_devclass, 0, 0); static int al_pcib_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) return (ENXIO); device_set_desc(dev, "Annapurna-Labs Integrated Internal PCI-E Controller"); return (BUS_PROBE_DEFAULT); } static int al_pcib_attach(device_t dev) { int rv; rv = pci_host_generic_attach(dev); /* Annapurna quirk: configure vendor-specific registers */ if (rv == 0) al_pcib_fixup(dev); return (rv); } static void al_pcib_fixup(device_t dev) { uint32_t val; uint16_t vid; uint8_t hdrtype; int bus, slot, func, maxfunc; /* Fixup is only needed on bus 0 */ bus = 0; for (slot = 0; slot <= PCI_SLOTMAX; slot++) { maxfunc = 0; for (func = 0; func <= maxfunc; func++) { hdrtype = PCIB_READ_CONFIG(dev, bus, slot, func, PCIR_HDRTYPE, 1); if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) continue; if (func == 0 && (hdrtype & PCIM_MFDEV) != 0) maxfunc = PCI_FUNCMAX; vid = PCIB_READ_CONFIG(dev, bus, slot, func, PCIR_VENDOR, 2); if (vid == ANNAPURNA_VENDOR_ID) { val = PCIB_READ_CONFIG(dev, bus, slot, func, AL_PCI_AXI_CFG_AND_CTR_0, 4); val |= PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_OVRD_FROM_AXUSER_MASK; PCIB_WRITE_CONFIG(dev, bus, slot, func, AL_PCI_AXI_CFG_AND_CTR_0, val, 4); val = PCIB_READ_CONFIG(dev, bus, slot, func, AL_PCI_APP_CONTROL, 4); val &= ~0xffff; val |= PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_SEL_TGTID_MASK; PCIB_WRITE_CONFIG(dev, bus, slot, func, AL_PCI_APP_CONTROL, val, 4); } } } } Index: head/sys/arm64/cavium/thunder_pcie_common.c =================================================================== --- head/sys/arm64/cavium/thunder_pcie_common.c (revision 308930) +++ head/sys/arm64/cavium/thunder_pcie_common.c (revision 308931) @@ -1,207 +1,210 @@ /*- * Copyright (c) 2015 The FreeBSD Foundation * All rights reserved. * * This software was developed by Semihalf under * the sponsorship of the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* Common PCIe functions for Cavium Thunder SOC */ #include __FBSDID("$FreeBSD$"); #include "opt_platform.h" #include #include #include #include #include #include #include #include #include #ifdef FDT #include #include #include #include #endif #include #include #include #include #include #include +#ifdef FDT +#include +#endif #include "thunder_pcie_common.h" MALLOC_DEFINE(M_THUNDER_PCIE, "Thunder PCIe driver", "Thunder PCIe driver memory"); #define THUNDER_CFG_BASE_TO_ECAM(x) ((((x) >> 36UL) & 0x3) | (((x) >> 42UL) & 0x4)) uint32_t range_addr_is_pci(struct pcie_range *ranges, uint64_t addr, uint64_t size) { struct pcie_range *r; int tuple; for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { r = &ranges[tuple]; if (addr >= r->pci_base && addr < (r->pci_base + r->size) && size < r->size) { /* Address is within PCI range */ return (1); } } /* Address is outside PCI range */ return (0); } uint32_t range_addr_is_phys(struct pcie_range *ranges, uint64_t addr, uint64_t size) { struct pcie_range *r; int tuple; for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { r = &ranges[tuple]; if (addr >= r->phys_base && addr < (r->phys_base + r->size) && size < r->size) { /* Address is within Physical range */ return (1); } } /* Address is outside Physical range */ return (0); } uint64_t range_addr_phys_to_pci(struct pcie_range *ranges, uint64_t phys_addr) { struct pcie_range *r; uint64_t offset; int tuple; /* Find physical address corresponding to given bus address */ for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { r = &ranges[tuple]; if (phys_addr >= r->phys_base && phys_addr < (r->phys_base + r->size)) { /* Given phys addr is in this range. * Translate phys addr to bus addr. */ offset = phys_addr - r->phys_base; return (r->pci_base + offset); } } return (0); } uint64_t range_addr_pci_to_phys(struct pcie_range *ranges, uint64_t pci_addr) { struct pcie_range *r; uint64_t offset; int tuple; /* Find physical address corresponding to given bus address */ for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { r = &ranges[tuple]; if (pci_addr >= r->pci_base && pci_addr < (r->pci_base + r->size)) { /* Given pci addr is in this range. * Translate bus addr to phys addr. */ offset = pci_addr - r->pci_base; return (r->phys_base + offset); } } return (0); } int thunder_pcie_identify_ecam(device_t dev, int *ecam) { rman_res_t start; /* Check if we're running on Cavium ThunderX */ if (!CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK, CPU_IMPL_CAVIUM, CPU_PART_THUNDER, 0, 0)) return (EINVAL); start = bus_get_resource_start(dev, SYS_RES_MEMORY, 0); *ecam = THUNDER_CFG_BASE_TO_ECAM(start); device_printf(dev, "ThunderX quirk, setting ECAM to %d\n", *ecam); return (0); } #ifdef THUNDERX_PASS_1_1_ERRATA struct resource * thunder_pcie_alloc_resource(device_t dev, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) { pci_addr_t map, testval; /* * If Enhanced Allocation is not used, we can't allocate any random * range. All internal devices have hardcoded place where they can * be located within PCI address space. Fortunately, we can read * this value from BAR. */ if (((type == SYS_RES_IOPORT) || (type == SYS_RES_MEMORY)) && RMAN_IS_DEFAULT_RANGE(start, end)) { /* Read BAR manually to get resource address and size */ pci_read_bar(child, *rid, &map, &testval, NULL); /* Mask the information bits */ if (PCI_BAR_MEM(map)) map &= PCIM_BAR_MEM_BASE; else map &= PCIM_BAR_IO_BASE; if (PCI_BAR_MEM(testval)) testval &= PCIM_BAR_MEM_BASE; else testval &= PCIM_BAR_IO_BASE; start = map; end = start + count - 1; } return (pci_host_generic_alloc_resource(dev, child, type, rid, start, end, count, flags)); } #endif Index: head/sys/arm64/cavium/thunder_pcie_fdt.c =================================================================== --- head/sys/arm64/cavium/thunder_pcie_fdt.c (revision 308930) +++ head/sys/arm64/cavium/thunder_pcie_fdt.c (revision 308931) @@ -1,160 +1,161 @@ /* * Copyright (C) 2016 Cavium Inc. * All rights reserved. * * Developed by Semihalf. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include +#include #include #include "thunder_pcie_common.h" #include "pcib_if.h" #ifdef THUNDERX_PASS_1_1_ERRATA static struct resource * thunder_pcie_fdt_alloc_resource(device_t, device_t, int, int *, rman_res_t, rman_res_t, rman_res_t, u_int); #endif static int thunder_pcie_fdt_attach(device_t); static int thunder_pcie_fdt_probe(device_t); static int thunder_pcie_fdt_get_id(device_t, device_t, enum pci_id_type, uintptr_t *); static device_method_t thunder_pcie_fdt_methods[] = { /* Device interface */ DEVMETHOD(device_probe, thunder_pcie_fdt_probe), DEVMETHOD(device_attach, thunder_pcie_fdt_attach), #ifdef THUNDERX_PASS_1_1_ERRATA DEVMETHOD(bus_alloc_resource, thunder_pcie_fdt_alloc_resource), #endif /* pcib interface */ DEVMETHOD(pcib_get_id, thunder_pcie_fdt_get_id), /* End */ DEVMETHOD_END }; DEFINE_CLASS_1(pcib, thunder_pcie_fdt_driver, thunder_pcie_fdt_methods, - sizeof(struct generic_pcie_softc), generic_pcie_driver); + sizeof(struct generic_pcie_fdt_softc), generic_pcie_fdt_driver); static devclass_t thunder_pcie_fdt_devclass; DRIVER_MODULE(thunder_pcib, simplebus, thunder_pcie_fdt_driver, thunder_pcie_fdt_devclass, 0, 0); DRIVER_MODULE(thunder_pcib, ofwbus, thunder_pcie_fdt_driver, thunder_pcie_fdt_devclass, 0, 0); static int thunder_pcie_fdt_probe(device_t dev) { /* Check if we're running on Cavium ThunderX */ if (!CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK, CPU_IMPL_CAVIUM, CPU_PART_THUNDER, 0, 0)) return (ENXIO); if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic") || ofw_bus_is_compatible(dev, "cavium,thunder-pcie") || ofw_bus_is_compatible(dev, "cavium,pci-host-thunder-ecam")) { device_set_desc(dev, "Cavium Integrated PCI/PCI-E Controller"); return (BUS_PROBE_DEFAULT); } return (ENXIO); } static int thunder_pcie_fdt_attach(device_t dev) { - struct generic_pcie_softc *sc; + struct generic_pcie_fdt_softc *sc; sc = device_get_softc(dev); - thunder_pcie_identify_ecam(dev, &sc->ecam); - sc->coherent = 1; + thunder_pcie_identify_ecam(dev, &sc->base.ecam); + sc->base.coherent = 1; return (pci_host_generic_attach(dev)); } static int thunder_pcie_fdt_get_id(device_t pci, device_t child, enum pci_id_type type, uintptr_t *id) { phandle_t node; int bsf; if (type != PCI_ID_MSI) return (pcib_get_id(pci, child, type, id)); node = ofw_bus_get_node(pci); if (OF_hasprop(node, "msi-map")) return (generic_pcie_get_id(pci, child, type, id)); bsf = pci_get_rid(child); *id = (pci_get_domain(child) << PCI_RID_DOMAIN_SHIFT) | bsf; return (0); } #ifdef THUNDERX_PASS_1_1_ERRATA static struct resource * thunder_pcie_fdt_alloc_resource(device_t dev, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) { if ((int)ofw_bus_get_node(child) > 0) return (pci_host_generic_alloc_resource(dev, child, type, rid, start, end, count, flags)); return (thunder_pcie_alloc_resource(dev, child, type, rid, start, end, count, flags)); } #endif Index: head/sys/conf/files.arm =================================================================== --- head/sys/conf/files.arm (revision 308930) +++ head/sys/conf/files.arm (revision 308931) @@ -1,166 +1,167 @@ # $FreeBSD$ cloudabi32_vdso.o optional compat_cloudabi32 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_armv6.S" \ compile-with "${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_armv6.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi32_vdso.o" # cloudabi32_vdso_blob.o optional compat_cloudabi32 \ dependency "cloudabi32_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf32-littlearm --binary-architecture arm cloudabi32_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi32_vdso_blob.o" # arm/annapurna/alpine/alpine_ccu.c optional al_ccu fdt arm/annapurna/alpine/alpine_nb_service.c optional al_nb_service fdt arm/annapurna/alpine/alpine_pci.c optional al_pci fdt arm/annapurna/alpine/alpine_pci_msix.c optional al_pci fdt arm/annapurna/alpine/alpine_serdes.c optional al_serdes fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" arm/arm/autoconf.c standard arm/arm/bcopy_page.S standard arm/arm/bcopyinout.S standard arm/arm/blockio.S standard arm/arm/bus_space_asm_generic.S standard arm/arm/bus_space_base.c optional fdt arm/arm/bus_space_generic.c standard arm/arm/busdma_machdep-v4.c optional !armv6 arm/arm/busdma_machdep-v6.c optional armv6 arm/arm/copystr.S standard arm/arm/cpufunc.c standard arm/arm/cpufunc_asm.S standard arm/arm/cpufunc_asm_arm9.S optional cpu_arm9 | cpu_arm9e arm/arm/cpufunc_asm_arm11.S optional cpu_arm1176 arm/arm/cpufunc_asm_arm11x6.S optional cpu_arm1176 arm/arm/cpufunc_asm_armv4.S optional cpu_arm9 | cpu_arm9e | cpu_fa526 | cpu_xscale_pxa2x0 | cpu_xscale_ixp425 | cpu_xscale_81342 arm/arm/cpufunc_asm_armv5_ec.S optional cpu_arm9e arm/arm/cpufunc_asm_armv6.S optional cpu_arm1176 arm/arm/cpufunc_asm_armv7.S optional cpu_cortexa8 | cpu_cortexa_mp | cpu_krait | cpu_mv_pj4b arm/arm/cpufunc_asm_fa526.S optional cpu_fa526 arm/arm/cpufunc_asm_pj4b.S optional cpu_mv_pj4b arm/arm/cpufunc_asm_sheeva.S optional cpu_arm9e arm/arm/cpufunc_asm_xscale.S optional cpu_xscale_pxa2x0 | cpu_xscale_ixp425 | cpu_xscale_81342 arm/arm/cpufunc_asm_xscale_c3.S optional cpu_xscale_81342 arm/arm/cpuinfo.c standard arm/arm/cpu_asm-v6.S optional armv6 arm/arm/db_disasm.c optional ddb arm/arm/db_interface.c optional ddb arm/arm/db_trace.c optional ddb arm/arm/debug_monitor.c optional ddb armv6 arm/arm/disassem.c optional ddb arm/arm/dump_machdep.c standard arm/arm/elf_machdep.c standard arm/arm/elf_note.S standard arm/arm/exception.S standard arm/arm/fiq.c standard arm/arm/fiq_subr.S standard arm/arm/fusu.S standard arm/arm/gdb_machdep.c optional gdb arm/arm/generic_timer.c optional generic_timer arm/arm/gic.c optional gic arm/arm/gic_fdt.c optional gic fdt arm/arm/hdmi_if.m optional hdmi arm/arm/identcpu-v4.c optional !armv6 arm/arm/identcpu-v6.c optional armv6 arm/arm/in_cksum.c optional inet | inet6 arm/arm/in_cksum_arm.S optional inet | inet6 arm/arm/intr.c optional !intrng kern/subr_intr.c optional intrng arm/arm/locore.S standard no-obj arm/arm/machdep.c standard arm/arm/machdep_intr.c standard arm/arm/mem.c optional mem arm/arm/minidump_machdep.c optional mem arm/arm/mp_machdep.c optional smp arm/arm/mpcore_timer.c optional mpcore_timer arm/arm/nexus.c standard arm/arm/ofw_machdep.c optional fdt arm/arm/physmem.c standard arm/arm/pl190.c optional pl190 arm/arm/pl310.c optional pl310 arm/arm/platform.c optional platform arm/arm/platform_if.m optional platform arm/arm/pmap-v4.c optional !armv6 arm/arm/pmap-v6.c optional armv6 arm/arm/pmu.c optional pmu | fdt hwpmc arm/arm/sc_machdep.c optional sc arm/arm/setcpsr.S standard arm/arm/setstack.s standard arm/arm/stack_machdep.c optional ddb | stack arm/arm/stdatomic.c standard \ compile-with "${NORMAL_C:N-Wmissing-prototypes}" arm/arm/support.S standard arm/arm/swtch.S standard arm/arm/swtch-v4.S optional !armv6 arm/arm/swtch-v6.S optional armv6 arm/arm/sys_machdep.c standard arm/arm/syscall.c standard arm/arm/trap-v4.c optional !armv6 arm/arm/trap-v6.c optional armv6 arm/arm/uio_machdep.c standard arm/arm/undefined.c standard arm/arm/unwind.c optional ddb | kdtrace_hooks arm/arm/vm_machdep.c standard arm/arm/vfp.c standard arm/cloudabi32/cloudabi32_sysvec.c optional compat_cloudabi32 board_id.h standard \ dependency "$S/arm/conf/genboardid.awk $S/arm/conf/mach-types" \ compile-with "${AWK} -f $S/arm/conf/genboardid.awk $S/arm/conf/mach-types > board_id.h" \ no-obj no-implicit-rule before-depend \ clean "board_id.h" cddl/compat/opensolaris/kern/opensolaris_atomic.c optional zfs | dtrace compile-with "${CDDL_C}" cddl/dev/dtrace/arm/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/arm/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/arm/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" crypto/blowfish/bf_enc.c optional crypto | ipsec crypto/des/des_enc.c optional crypto | ipsec | netsmb dev/cpufreq/cpufreq_dt.c optional cpufreq fdt dev/dwc/if_dwc.c optional dwc dev/dwc/if_dwc_if.m optional dwc dev/fb/fb.c optional sc dev/fdt/fdt_arm_platform.c optional platform fdt dev/hwpmc/hwpmc_arm.c optional hwpmc dev/hwpmc/hwpmc_armv7.c optional hwpmc armv6 dev/iicbus/twsi/twsi.c optional twsi dev/ofw/ofwpci.c optional fdt pci -dev/pci/pci_host_generic.c optional pci_host_generic pci fdt +dev/pci/pci_host_generic.c optional pci_host_generic pci +dev/pci/pci_host_generic_fdt.c optional pci_host_generic pci fdt dev/psci/psci.c optional psci dev/psci/psci_arm.S optional psci dev/syscons/scgfbrndr.c optional sc dev/syscons/scterm-teken.c optional sc dev/syscons/scvtb.c optional sc dev/uart/uart_cpu_fdt.c optional uart fdt font.h optional sc \ compile-with "uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x16.fnt && file2c 'u_char dflt_font_16[16*256] = {' '};' < ${SC_DFLT_FONT}-8x16 > font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x14.fnt && file2c 'u_char dflt_font_14[14*256] = {' '};' < ${SC_DFLT_FONT}-8x14 >> font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x8.fnt && file2c 'u_char dflt_font_8[8*256] = {' '};' < ${SC_DFLT_FONT}-8x8 >> font.h" \ no-obj no-implicit-rule before-depend \ clean "font.h ${SC_DFLT_FONT}-8x14 ${SC_DFLT_FONT}-8x16 ${SC_DFLT_FONT}-8x8" kern/msi_if.m optional intrng kern/pic_if.m optional intrng kern/subr_busdma_bufalloc.c standard kern/subr_devmap.c standard kern/subr_sfbuf.c standard libkern/arm/aeabi_unwind.c standard libkern/arm/divsi3.S standard libkern/arm/ffs.S standard libkern/arm/ldivmod.S standard libkern/arm/ldivmod_helper.c standard libkern/arm/memclr.S standard libkern/arm/memcpy.S standard libkern/arm/memset.S standard libkern/arm/muldi3.c standard libkern/ashldi3.c standard libkern/ashrdi3.c standard libkern/divdi3.c standard libkern/ffsl.c standard libkern/ffsll.c standard libkern/fls.c standard libkern/flsl.c standard libkern/flsll.c standard libkern/lshrdi3.c standard libkern/moddi3.c standard libkern/qdivrem.c standard libkern/ucmpdi2.c standard libkern/udivdi3.c standard libkern/umoddi3.c standard Index: head/sys/conf/files.arm64 =================================================================== --- head/sys/conf/files.arm64 (revision 308930) +++ head/sys/conf/files.arm64 (revision 308931) @@ -1,191 +1,192 @@ # $FreeBSD$ cloudabi64_vdso.o optional compat_cloudabi64 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_aarch64.S" \ compile-with "${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_aarch64.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi64_vdso.o" # cloudabi64_vdso_blob.o optional compat_cloudabi64 \ dependency "cloudabi64_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi64_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi64_vdso_blob.o" # arm/allwinner/a10_ehci.c optional ehci aw_ehci arm/allwinner/a10_gpio.c optional gpio aw_gpio arm/allwinner/a10_mmc.c optional mmc aw_mmc arm/allwinner/a64/a64_padconf.c optional soc_allwinner_a64 arm/allwinner/a64/a64_r_padconf.c optional soc_allwinner_a64 arm/allwinner/aw_ccu.c optional aw_ccu arm/allwinner/aw_nmi.c optional aw_nmi \ compile-with "${NORMAL_C} -I$S/gnu/dts/include" arm/allwinner/aw_reset.c optional aw_ccu arm/allwinner/aw_rsb.c optional aw_rsb arm/allwinner/aw_rtc.c optional aw_rtc arm/allwinner/aw_sid.c optional aw_sid arm/allwinner/aw_thermal.c optional aw_thermal arm/allwinner/aw_usbphy.c optional ehci aw_usbphy arm/allwinner/aw_wdog.c optional aw_wdog arm/allwinner/axp81x.c optional axp81x arm/allwinner/clk/aw_ahbclk.c optional aw_ccu arm/allwinner/clk/aw_apbclk.c optional aw_ccu arm/allwinner/clk/aw_axiclk.c optional aw_ccu arm/allwinner/clk/aw_cpuclk.c optional aw_ccu arm/allwinner/clk/aw_gate.c optional aw_ccu arm/allwinner/clk/aw_modclk.c optional aw_ccu arm/allwinner/clk/aw_pll.c optional aw_ccu \ compile-with "${NORMAL_C} -I$S/gnu/dts/include" arm/allwinner/clk/aw_thsclk.c optional aw_ccu arm/allwinner/clk/aw_usbclk.c optional aw_ccu arm/allwinner/if_awg.c optional awg arm/annapurna/alpine/alpine_ccu.c optional al_ccu fdt arm/annapurna/alpine/alpine_nb_service.c optional al_nb_service fdt arm/annapurna/alpine/alpine_pci.c optional al_pci fdt arm/annapurna/alpine/alpine_pci_msix.c optional al_pci fdt arm/annapurna/alpine/alpine_serdes.c optional al_serdes fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" arm/arm/generic_timer.c standard arm/arm/gic.c standard arm/arm/gic_fdt.c optional fdt arm/arm/pmu.c standard arm/broadcom/bcm2835/bcm2835_audio.c optional sound vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc soc_brcm_bcm2837 arm/broadcom/bcm2835/bcm2835_cpufreq.c optional soc_brcm_bcm2837 arm/broadcom/bcm2835/bcm2835_dma.c optional soc_brcm_bcm2837 arm/broadcom/bcm2835/bcm2835_fbd.c optional vt soc_brcm_bcm2837 arm/broadcom/bcm2835/bcm2835_ft5406.c optional evdev bcm2835_ft5406 soc_brcm_bcm2837 arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio soc_brcm_bcm2837 arm/broadcom/bcm2835/bcm2835_intr.c optional soc_brcm_bcm2837 arm/broadcom/bcm2835/bcm2835_mbox.c optional soc_brcm_bcm2837 arm/broadcom/bcm2835/bcm2835_rng.c optional random soc_brcm_bcm2837 arm/broadcom/bcm2835/bcm2835_sdhci.c optional sdhci soc_brcm_bcm2837 arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi soc_brcm_bcm2837 arm/broadcom/bcm2835/bcm2835_vcio.c optional soc_brcm_bcm2837 arm/broadcom/bcm2835/bcm2835_wdog.c optional soc_brcm_bcm2837 arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837 arm64/acpica/acpi_machdep.c optional acpi arm64/acpica/OsdEnvironment.c optional acpi arm64/acpica/acpi_wakeup.c optional acpi arm64/acpica/pci_cfgreg.c optional acpi pci arm64/arm64/autoconf.c standard arm64/arm64/bus_machdep.c standard arm64/arm64/bus_space_asm.S standard arm64/arm64/busdma_bounce.c standard arm64/arm64/busdma_machdep.c standard arm64/arm64/bzero.S standard arm64/arm64/clock.c standard arm64/arm64/copyinout.S standard arm64/arm64/copystr.c standard arm64/arm64/cpufunc_asm.S standard arm64/arm64/db_disasm.c optional ddb arm64/arm64/db_interface.c optional ddb arm64/arm64/db_trace.c optional ddb arm64/arm64/debug_monitor.c optional ddb arm64/arm64/disassem.c optional ddb arm64/arm64/dump_machdep.c standard arm64/arm64/elf_machdep.c standard arm64/arm64/exception.S standard arm64/arm64/gicv3_its.c optional intrng arm64/arm64/gic_v3.c standard arm64/arm64/gic_v3_fdt.c optional fdt arm64/arm64/identcpu.c standard arm64/arm64/in_cksum.c optional inet | inet6 arm64/arm64/locore.S standard no-obj arm64/arm64/machdep.c standard arm64/arm64/mem.c standard arm64/arm64/memcpy.S standard arm64/arm64/memmove.S standard arm64/arm64/minidump_machdep.c standard arm64/arm64/mp_machdep.c optional smp arm64/arm64/nexus.c standard arm64/arm64/ofw_machdep.c optional fdt arm64/arm64/pmap.c standard arm64/arm64/stack_machdep.c optional ddb | stack arm64/arm64/support.S standard arm64/arm64/swtch.S standard arm64/arm64/sys_machdep.c standard arm64/arm64/trap.c standard arm64/arm64/uio_machdep.c standard arm64/arm64/uma_machdep.c standard arm64/arm64/unwind.c optional ddb | kdtrace_hooks | stack arm64/arm64/vfp.c standard arm64/arm64/vm_machdep.c standard arm64/cavium/thunder_pcie_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_pem.c optional soc_cavm_thunderx pci arm64/cavium/thunder_pcie_pem_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_common.c optional soc_cavm_thunderx pci arm64/cloudabi64/cloudabi64_sysvec.c optional compat_cloudabi64 contrib/vchiq/interface/compat/vchi_bsd.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_connected.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_core.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_shim.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_util.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" crypto/armv8/armv8_crypto.c optional armv8crypto armv8_crypto_wrap.o optional armv8crypto \ dependency "$S/crypto/armv8/armv8_crypto_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} ${WERROR} ${NO_WCAST_QUAL} ${PROF} -march=armv8a+crypto ${.IMPSRC}" \ no-implicit-rule \ clean "armv8_crypto_wrap.o" crypto/blowfish/bf_enc.c optional crypto | ipsec crypto/des/des_enc.c optional crypto | ipsec | netsmb dev/acpica/acpi_if.m optional acpi dev/ahci/ahci_generic.c optional ahci fdt dev/cpufreq/cpufreq_dt.c optional cpufreq fdt dev/hwpmc/hwpmc_arm64.c optional hwpmc dev/hwpmc/hwpmc_arm64_md.c optional hwpmc dev/mbox/mbox_if.m optional soc_brcm_bcm2837 dev/mmc/host/dwmmc.c optional dwmmc fdt dev/mmc/host/dwmmc_hisi.c optional dwmmc fdt soc_hisi_hi6220 dev/ofw/ofw_cpu.c optional fdt dev/ofw/ofwpci.c optional fdt pci -dev/pci/pci_host_generic.c optional pci fdt -dev/psci/psci.c optional psci +dev/pci/pci_host_generic.c optional pci +dev/pci/pci_host_generic_fdt.c optional pci fdt +dev/psci/psci.c optional psci fdt dev/psci/psci_arm64.S optional psci dev/uart/uart_cpu_arm64.c optional uart dev/uart/uart_dev_pl011.c optional uart pl011 dev/usb/controller/dwc_otg_hisi.c optional dwcotg fdt soc_hisi_hi6220 dev/usb/controller/generic_ehci.c optional ehci acpi dev/usb/controller/generic_ohci.c optional ohci fdt dev/usb/controller/generic_usb_if.m optional ohci fdt dev/vnic/mrml_bridge.c optional vnic fdt dev/vnic/nic_main.c optional vnic pci dev/vnic/nicvf_main.c optional vnic pci pci_iov dev/vnic/nicvf_queues.c optional vnic pci pci_iov dev/vnic/thunder_bgx_fdt.c optional vnic fdt dev/vnic/thunder_bgx.c optional vnic pci dev/vnic/thunder_mdio_fdt.c optional vnic fdt dev/vnic/thunder_mdio.c optional vnic dev/vnic/lmac_if.m optional inet | inet6 | vnic kern/kern_clocksource.c standard kern/msi_if.m optional intrng kern/pic_if.m optional intrng kern/subr_devmap.c standard kern/subr_intr.c optional intrng libkern/bcmp.c standard libkern/ffs.c standard libkern/ffsl.c standard libkern/ffsll.c standard libkern/fls.c standard libkern/flsl.c standard libkern/flsll.c standard libkern/memset.c standard cddl/contrib/opensolaris/common/atomic/aarch64/opensolaris_atomic.S optional zfs | dtrace compile-with "${CDDL_C}" cddl/dev/dtrace/aarch64/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/aarch64/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" Index: head/sys/dev/pci/pci_host_generic.c =================================================================== --- head/sys/dev/pci/pci_host_generic.c (revision 308930) +++ head/sys/dev/pci/pci_host_generic.c (revision 308931) @@ -1,969 +1,394 @@ /*- * Copyright (c) 2015 Ruslan Bukin * Copyright (c) 2014 The FreeBSD Foundation * All rights reserved. * * This software was developed by Semihalf under * the sponsorship of the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* Generic ECAM PCIe driver */ #include __FBSDID("$FreeBSD$"); #include "opt_platform.h" #include #include #include #include #include #include #include #include -#include -#include -#if defined(INTRNG) -#include -#endif - -#include -#include -#include -#include #include #include #include #include -#include #include #include -#include #include "pcib_if.h" /* Assembling ECAM Configuration Address */ #define PCIE_BUS_SHIFT 20 #define PCIE_SLOT_SHIFT 15 #define PCIE_FUNC_SHIFT 12 #define PCIE_BUS_MASK 0xFF #define PCIE_SLOT_MASK 0x1F #define PCIE_FUNC_MASK 0x07 #define PCIE_REG_MASK 0xFFF #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \ ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \ (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \ (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \ ((reg) & PCIE_REG_MASK)) -#define PCI_IO_WINDOW_OFFSET 0x1000 - -#define SPACE_CODE_SHIFT 24 -#define SPACE_CODE_MASK 0x3 -#define SPACE_CODE_IO_SPACE 0x1 -#define PROPS_CELL_SIZE 1 -#define PCI_ADDR_CELL_SIZE 2 - -/* OFW bus interface */ -struct generic_pcie_ofw_devinfo { - struct ofw_bus_devinfo di_dinfo; - struct resource_list di_rl; -}; - /* Forward prototypes */ -static int generic_pcie_probe(device_t dev); -static int parse_pci_mem_ranges(struct generic_pcie_softc *sc); static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, int bytes); static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, uint32_t val, int bytes); static int generic_pcie_maxslots(device_t dev); static int generic_pcie_read_ivar(device_t dev, device_t child, int index, uintptr_t *result); static int generic_pcie_write_ivar(device_t dev, device_t child, int index, uintptr_t value); -static struct resource *generic_pcie_alloc_resource_ofw(device_t, device_t, - int, int *, rman_res_t, rman_res_t, rman_res_t, u_int); -static struct resource *generic_pcie_alloc_resource_pcie(device_t dev, - device_t child, int type, int *rid, rman_res_t start, rman_res_t end, - rman_res_t count, u_int flags); -static int generic_pcie_release_resource(device_t dev, device_t child, - int type, int rid, struct resource *res); -static int generic_pcie_release_resource_ofw(device_t, device_t, int, int, - struct resource *); -static int generic_pcie_release_resource_pcie(device_t, device_t, int, int, - struct resource *); -static int generic_pcie_ofw_bus_attach(device_t); -static const struct ofw_bus_devinfo *generic_pcie_ofw_get_devinfo(device_t, - device_t); -static __inline void -get_addr_size_cells(phandle_t node, pcell_t *addr_cells, pcell_t *size_cells) -{ - - *addr_cells = 2; - /* Find address cells if present */ - OF_getencprop(node, "#address-cells", addr_cells, sizeof(*addr_cells)); - - *size_cells = 2; - /* Find size cells if present */ - OF_getencprop(node, "#size-cells", size_cells, sizeof(*size_cells)); -} - -static int -generic_pcie_probe(device_t dev) -{ - - if (!ofw_bus_status_okay(dev)) - return (ENXIO); - - if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic")) { - device_set_desc(dev, "Generic PCI host controller"); - return (BUS_PROBE_GENERIC); - } - if (ofw_bus_is_compatible(dev, "arm,gem5_pcie")) { - device_set_desc(dev, "GEM5 PCIe host controller"); - return (BUS_PROBE_DEFAULT); - } - - return (ENXIO); -} - int -pci_host_generic_attach(device_t dev) +pci_host_generic_core_attach(device_t dev) { - struct generic_pcie_softc *sc; - uint64_t phys_base; - uint64_t pci_base; - uint64_t size; - phandle_t node; + struct generic_pcie_core_softc *sc; int error; - int tuple; int rid; sc = device_get_softc(dev); sc->dev = dev; - /* Retrieve 'ranges' property from FDT */ - if (bootverbose) - device_printf(dev, "parsing FDT for ECAM%d:\n", - sc->ecam); - if (parse_pci_mem_ranges(sc)) - return (ENXIO); - - /* Attach OFW bus */ - if (generic_pcie_ofw_bus_attach(dev) != 0) - return (ENXIO); - - node = ofw_bus_get_node(dev); - if (sc->coherent == 0) { - sc->coherent = OF_hasprop(node, "dma-coherent"); - } - if (bootverbose) - device_printf(dev, "Bus is%s cache-coherent\n", - sc->coherent ? "" : " not"); - /* Create the parent DMA tag to pass down the coherent flag */ error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1, 0, /* alignment, bounds */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ BUS_SPACE_MAXSIZE, /* maxsize */ BUS_SPACE_UNRESTRICTED, /* nsegments */ BUS_SPACE_MAXSIZE, /* maxsegsize */ sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->dmat); if (error != 0) return (error); rid = 0; sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->res == NULL) { device_printf(dev, "could not map memory.\n"); return (ENXIO); } sc->bst = rman_get_bustag(sc->res); sc->bsh = rman_get_bushandle(sc->res); sc->mem_rman.rm_type = RMAN_ARRAY; sc->mem_rman.rm_descr = "PCIe Memory"; sc->io_rman.rm_type = RMAN_ARRAY; sc->io_rman.rm_descr = "PCIe IO window"; /* Initialize rman and allocate memory regions */ error = rman_init(&sc->mem_rman); if (error) { device_printf(dev, "rman_init() failed. error = %d\n", error); return (error); } error = rman_init(&sc->io_rman); if (error) { device_printf(dev, "rman_init() failed. error = %d\n", error); return (error); } - for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { - phys_base = sc->ranges[tuple].phys_base; - pci_base = sc->ranges[tuple].pci_base; - size = sc->ranges[tuple].size; - if (phys_base == 0 || size == 0) - continue; /* empty range element */ - if (sc->ranges[tuple].flags & FLAG_MEM) { - error = rman_manage_region(&sc->mem_rman, - phys_base, phys_base + size - 1); - } else if (sc->ranges[tuple].flags & FLAG_IO) { - error = rman_manage_region(&sc->io_rman, - pci_base + PCI_IO_WINDOW_OFFSET, - pci_base + PCI_IO_WINDOW_OFFSET + size - 1); - } else - continue; - if (error) { - device_printf(dev, "rman_manage_region() failed." - "error = %d\n", error); - rman_fini(&sc->mem_rman); - return (error); - } - } - - ofw_bus_setup_iinfo(node, &sc->pci_iinfo, sizeof(cell_t)); - - device_add_child(dev, "pci", -1); - return (bus_generic_attach(dev)); -} - -static int -parse_pci_mem_ranges(struct generic_pcie_softc *sc) -{ - pcell_t pci_addr_cells, parent_addr_cells; - pcell_t attributes, size_cells; - cell_t *base_ranges; - int nbase_ranges; - phandle_t node; - int i, j, k; - int tuple; - - node = ofw_bus_get_node(sc->dev); - - OF_getencprop(node, "#address-cells", &pci_addr_cells, - sizeof(pci_addr_cells)); - OF_getencprop(node, "#size-cells", &size_cells, - sizeof(size_cells)); - OF_getencprop(OF_parent(node), "#address-cells", &parent_addr_cells, - sizeof(parent_addr_cells)); - - if (parent_addr_cells > 2 || pci_addr_cells != 3 || size_cells > 2) { - device_printf(sc->dev, - "Unexpected number of address or size cells in FDT\n"); - return (ENXIO); - } - - nbase_ranges = OF_getproplen(node, "ranges"); - sc->nranges = nbase_ranges / sizeof(cell_t) / - (parent_addr_cells + pci_addr_cells + size_cells); - base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK); - OF_getencprop(node, "ranges", base_ranges, nbase_ranges); - - for (i = 0, j = 0; i < sc->nranges; i++) { - attributes = (base_ranges[j++] >> SPACE_CODE_SHIFT) & \ - SPACE_CODE_MASK; - if (attributes == SPACE_CODE_IO_SPACE) { - sc->ranges[i].flags |= FLAG_IO; - } else { - sc->ranges[i].flags |= FLAG_MEM; - } - - sc->ranges[i].pci_base = 0; - for (k = 0; k < (pci_addr_cells - 1); k++) { - sc->ranges[i].pci_base <<= 32; - sc->ranges[i].pci_base |= base_ranges[j++]; - } - sc->ranges[i].phys_base = 0; - for (k = 0; k < parent_addr_cells; k++) { - sc->ranges[i].phys_base <<= 32; - sc->ranges[i].phys_base |= base_ranges[j++]; - } - sc->ranges[i].size = 0; - for (k = 0; k < size_cells; k++) { - sc->ranges[i].size <<= 32; - sc->ranges[i].size |= base_ranges[j++]; - } - } - - for (; i < MAX_RANGES_TUPLES; i++) { - /* zero-fill remaining tuples to mark empty elements in array */ - sc->ranges[i].pci_base = 0; - sc->ranges[i].phys_base = 0; - sc->ranges[i].size = 0; - } - - if (bootverbose) { - for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { - device_printf(sc->dev, - "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx\n", - sc->ranges[tuple].pci_base, - sc->ranges[tuple].phys_base, - sc->ranges[tuple].size); - } - } - - free(base_ranges, M_DEVBUF); return (0); } static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, int bytes) { - struct generic_pcie_softc *sc; + struct generic_pcie_core_softc *sc; bus_space_handle_t h; bus_space_tag_t t; uint64_t offset; uint32_t data; if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) return (~0U); sc = device_get_softc(dev); offset = PCIE_ADDR_OFFSET(bus, slot, func, reg); t = sc->bst; h = sc->bsh; switch (bytes) { case 1: data = bus_space_read_1(t, h, offset); break; case 2: data = le16toh(bus_space_read_2(t, h, offset)); break; case 4: data = le32toh(bus_space_read_4(t, h, offset)); break; default: return (~0U); } return (data); } static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, uint32_t val, int bytes) { - struct generic_pcie_softc *sc; + struct generic_pcie_core_softc *sc; bus_space_handle_t h; bus_space_tag_t t; uint64_t offset; if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) return; sc = device_get_softc(dev); offset = PCIE_ADDR_OFFSET(bus, slot, func, reg); t = sc->bst; h = sc->bsh; switch (bytes) { case 1: bus_space_write_1(t, h, offset, val); break; case 2: bus_space_write_2(t, h, offset, htole16(val)); break; case 4: bus_space_write_4(t, h, offset, htole32(val)); break; default: return; } } static int generic_pcie_maxslots(device_t dev) { return (31); /* max slots per bus acc. to standard */ } static int -generic_pcie_route_interrupt(device_t bus, device_t dev, int pin) -{ - struct generic_pcie_softc *sc; - struct ofw_pci_register reg; - uint32_t pintr, mintr[2]; - phandle_t iparent; - int intrcells; - - sc = device_get_softc(bus); - pintr = pin; - - bzero(®, sizeof(reg)); - reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | - (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | - (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); - - intrcells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), - &sc->pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr), - mintr, sizeof(mintr), &iparent); - if (intrcells) { - pintr = ofw_bus_map_intr(dev, iparent, intrcells, mintr); - return (pintr); - } - - device_printf(bus, "could not route pin %d for device %d.%d\n", - pin, pci_get_slot(dev), pci_get_function(dev)); - return (PCI_INVALID_IRQ); -} - - -static int generic_pcie_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) { - struct generic_pcie_softc *sc; + struct generic_pcie_core_softc *sc; int secondary_bus; sc = device_get_softc(dev); if (index == PCIB_IVAR_BUS) { /* this pcib adds only pci bus 0 as child */ secondary_bus = 0; *result = secondary_bus; return (0); } if (index == PCIB_IVAR_DOMAIN) { *result = sc->ecam; return (0); } if (bootverbose) device_printf(dev, "ERROR: Unknown index %d.\n", index); return (ENOENT); } static int generic_pcie_write_ivar(device_t dev, device_t child, int index, uintptr_t value) { return (ENOENT); } static struct rman * -generic_pcie_rman(struct generic_pcie_softc *sc, int type) +generic_pcie_rman(struct generic_pcie_core_softc *sc, int type) { switch (type) { case SYS_RES_IOPORT: return (&sc->io_rman); case SYS_RES_MEMORY: return (&sc->mem_rman); default: break; } return (NULL); } -static int -generic_pcie_release_resource_pcie(device_t dev, device_t child, int type, +int +pci_host_generic_core_release_resource(device_t dev, device_t child, int type, int rid, struct resource *res) { - struct generic_pcie_softc *sc; + struct generic_pcie_core_softc *sc; struct rman *rm; sc = device_get_softc(dev); +#if defined(NEW_PCIB) && defined(PCI_RES_BUS) + if (type == PCI_RES_BUS) { + return (pci_domain_release_bus(sc->ecam, child, rid, res)); + } +#endif + rm = generic_pcie_rman(sc, type); if (rm != NULL) { KASSERT(rman_is_region_manager(res, rm), ("rman mismatch")); rman_release_resource(res); } return (bus_generic_release_resource(dev, child, type, rid, res)); } -static int -generic_pcie_release_resource(device_t dev, device_t child, int type, - int rid, struct resource *res) +struct resource * +pci_host_generic_core_alloc_resource(device_t dev, device_t child, int type, + int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) { -#if defined(NEW_PCIB) && defined(PCI_RES_BUS) - struct generic_pcie_softc *sc; + struct generic_pcie_core_softc *sc; + struct resource *res; + struct rman *rm; - if (type == PCI_RES_BUS) { - sc = device_get_softc(dev); - return (pci_domain_release_bus(sc->ecam, child, rid, res)); - } -#endif - /* For PCIe devices that do not have FDT nodes, use PCIB method */ - if ((int)ofw_bus_get_node(child) <= 0) { - return (generic_pcie_release_resource_pcie(dev, - child, type, rid, res)); - } + sc = device_get_softc(dev); - /* For other devices use OFW method */ - return (generic_pcie_release_resource_ofw(dev, - child, type, rid, res)); -} - -struct resource * -pci_host_generic_alloc_resource(device_t dev, device_t child, int type, int *rid, - rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) -{ #if defined(NEW_PCIB) && defined(PCI_RES_BUS) - struct generic_pcie_softc *sc; - if (type == PCI_RES_BUS) { - sc = device_get_softc(dev); return (pci_domain_alloc_bus(sc->ecam, child, rid, start, end, count, flags)); } #endif - /* For PCIe devices that do not have FDT nodes, use PCIB method */ - if ((int)ofw_bus_get_node(child) <= 0) - return (generic_pcie_alloc_resource_pcie(dev, child, type, rid, - start, end, count, flags)); - /* For other devices use OFW method */ - return (generic_pcie_alloc_resource_ofw(dev, child, type, rid, - start, end, count, flags)); -} - -static struct resource * -generic_pcie_alloc_resource_pcie(device_t dev, device_t child, int type, int *rid, - rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) -{ - struct generic_pcie_softc *sc; - struct resource *res; - struct rman *rm; - - sc = device_get_softc(dev); - rm = generic_pcie_rman(sc, type); if (rm == NULL) return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, type, rid, start, end, count, flags)); if (bootverbose) { device_printf(dev, "rman_reserve_resource: start=%#jx, end=%#jx, count=%#jx\n", start, end, count); } res = rman_reserve_resource(rm, start, end, count, flags, child); if (res == NULL) goto fail; rman_set_rid(res, *rid); if (flags & RF_ACTIVE) if (bus_activate_resource(child, type, *rid, res)) { rman_release_resource(res); goto fail; } return (res); fail: device_printf(dev, "%s FAIL: type=%d, rid=%d, " "start=%016jx, end=%016jx, count=%016jx, flags=%x\n", __func__, type, *rid, start, end, count, flags); return (NULL); } static int generic_pcie_adjust_resource(device_t dev, device_t child, int type, struct resource *res, rman_res_t start, rman_res_t end) { - struct generic_pcie_softc *sc; + struct generic_pcie_core_softc *sc; struct rman *rm; sc = device_get_softc(dev); #if defined(NEW_PCIB) && defined(PCI_RES_BUS) if (type == PCI_RES_BUS) return (pci_domain_adjust_bus(sc->ecam, child, res, start, end)); #endif rm = generic_pcie_rman(sc, type); if (rm != NULL) return (rman_adjust_resource(res, start, end)); return (bus_generic_adjust_resource(dev, child, type, res, start, end)); } -static int -generic_pcie_activate_resource(device_t dev, device_t child, int type, int rid, - struct resource *r) -{ - struct generic_pcie_softc *sc; - uint64_t phys_base; - uint64_t pci_base; - uint64_t size; - int found; - int res; - int i; - - sc = device_get_softc(dev); - - if ((res = rman_activate_resource(r)) != 0) - return (res); - - switch(type) { - case SYS_RES_IOPORT: - found = 0; - for (i = 0; i < MAX_RANGES_TUPLES; i++) { - pci_base = sc->ranges[i].pci_base; - phys_base = sc->ranges[i].phys_base; - size = sc->ranges[i].size; - - if ((rid > pci_base) && (rid < (pci_base + size))) { - found = 1; - break; - } - } - if (found) { - rman_set_start(r, rman_get_start(r) + phys_base); - rman_set_end(r, rman_get_end(r) + phys_base); - BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child, - type, rid, r); - } else { - device_printf(dev, "Failed to activate IOPORT resource\n"); - res = 0; - } - break; - case SYS_RES_MEMORY: - BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child, type, rid, r); - break; - default: - break; - } - - return (res); -} - -static int -generic_pcie_deactivate_resource(device_t dev, device_t child, int type, int rid, - struct resource *r) -{ - struct generic_pcie_softc *sc; - vm_offset_t vaddr; - int res; - - sc = device_get_softc(dev); - - if ((res = rman_deactivate_resource(r)) != 0) - return (res); - - switch(type) { - case SYS_RES_IOPORT: - case SYS_RES_MEMORY: - vaddr = (vm_offset_t)rman_get_virtual(r); - pmap_unmapdev(vaddr, rman_get_size(r)); - break; - default: - break; - } - - return (res); -} - static bus_dma_tag_t generic_pcie_get_dma_tag(device_t dev, device_t child) { - struct generic_pcie_softc *sc; + struct generic_pcie_core_softc *sc; sc = device_get_softc(dev); return (sc->dmat); } -static int -generic_pcie_alloc_msi(device_t pci, device_t child, int count, int maxcount, - int *irqs) -{ -#if defined(INTRNG) - phandle_t msi_parent; - - ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, - NULL); - return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, - irqs)); -#else - return (ENXIO); -#endif -} - -static int -generic_pcie_release_msi(device_t pci, device_t child, int count, int *irqs) -{ -#if defined(INTRNG) - phandle_t msi_parent; - - ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, - NULL); - return (intr_release_msi(pci, child, msi_parent, count, irqs)); -#else - return (ENXIO); -#endif -} - -static int -generic_pcie_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, - uint32_t *data) -{ -#if defined(INTRNG) - phandle_t msi_parent; - - ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, - NULL); - return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); -#else - return (ENXIO); -#endif -} - -static int -generic_pcie_alloc_msix(device_t pci, device_t child, int *irq) -{ -#if defined(INTRNG) - phandle_t msi_parent; - - ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, - NULL); - return (intr_alloc_msix(pci, child, msi_parent, irq)); -#else - return (ENXIO); -#endif -} - -static int -generic_pcie_release_msix(device_t pci, device_t child, int irq) -{ -#if defined(INTRNG) - phandle_t msi_parent; - - ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, - NULL); - return (intr_release_msix(pci, child, msi_parent, irq)); -#else - return (ENXIO); -#endif -} - -int -generic_pcie_get_id(device_t pci, device_t child, enum pci_id_type type, - uintptr_t *id) -{ - phandle_t node; - uint32_t rid; - uint16_t pci_rid; - - if (type != PCI_ID_MSI) - return (pcib_get_id(pci, child, type, id)); - - node = ofw_bus_get_node(pci); - pci_rid = pci_get_rid(child); - - ofw_bus_msimap(node, pci_rid, NULL, &rid); - *id = rid; - - return (0); -} - static device_method_t generic_pcie_methods[] = { - DEVMETHOD(device_probe, generic_pcie_probe), - DEVMETHOD(device_attach, pci_host_generic_attach), + DEVMETHOD(device_attach, pci_host_generic_core_attach), DEVMETHOD(bus_read_ivar, generic_pcie_read_ivar), DEVMETHOD(bus_write_ivar, generic_pcie_write_ivar), - DEVMETHOD(bus_alloc_resource, pci_host_generic_alloc_resource), + DEVMETHOD(bus_alloc_resource, pci_host_generic_core_alloc_resource), DEVMETHOD(bus_adjust_resource, generic_pcie_adjust_resource), - DEVMETHOD(bus_release_resource, generic_pcie_release_resource), - DEVMETHOD(bus_activate_resource, generic_pcie_activate_resource), - DEVMETHOD(bus_deactivate_resource, generic_pcie_deactivate_resource), + DEVMETHOD(bus_release_resource, pci_host_generic_core_release_resource), DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), DEVMETHOD(bus_get_dma_tag, generic_pcie_get_dma_tag), /* pcib interface */ DEVMETHOD(pcib_maxslots, generic_pcie_maxslots), - DEVMETHOD(pcib_route_interrupt, generic_pcie_route_interrupt), DEVMETHOD(pcib_read_config, generic_pcie_read_config), DEVMETHOD(pcib_write_config, generic_pcie_write_config), - DEVMETHOD(pcib_alloc_msi, generic_pcie_alloc_msi), - DEVMETHOD(pcib_release_msi, generic_pcie_release_msi), - DEVMETHOD(pcib_alloc_msix, generic_pcie_alloc_msix), - DEVMETHOD(pcib_release_msix, generic_pcie_release_msix), - DEVMETHOD(pcib_map_msi, generic_pcie_map_msi), - DEVMETHOD(pcib_get_id, generic_pcie_get_id), - /* ofw_bus interface */ - DEVMETHOD(ofw_bus_get_devinfo, generic_pcie_ofw_get_devinfo), - DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), - DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), - DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), - DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), - DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), - DEVMETHOD_END }; -static const struct ofw_bus_devinfo * -generic_pcie_ofw_get_devinfo(device_t bus __unused, device_t child) -{ - struct generic_pcie_ofw_devinfo *di; - - di = device_get_ivars(child); - return (&di->di_dinfo); -} - -static struct resource * -generic_pcie_alloc_resource_ofw(device_t bus, device_t child, int type, int *rid, - rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) -{ - struct generic_pcie_softc *sc; - struct generic_pcie_ofw_devinfo *di; - struct resource_list_entry *rle; - int i; - - sc = device_get_softc(bus); - - if (RMAN_IS_DEFAULT_RANGE(start, end)) { - if ((di = device_get_ivars(child)) == NULL) - return (NULL); - if (type == SYS_RES_IOPORT) - type = SYS_RES_MEMORY; - - /* Find defaults for this rid */ - rle = resource_list_find(&di->di_rl, type, *rid); - if (rle == NULL) - return (NULL); - - start = rle->start; - end = rle->end; - count = rle->count; - } - - if (type == SYS_RES_MEMORY) { - /* Remap through ranges property */ - for (i = 0; i < MAX_RANGES_TUPLES; i++) { - if (start >= sc->ranges[i].phys_base && end < - sc->ranges[i].pci_base + sc->ranges[i].size) { - start -= sc->ranges[i].phys_base; - start += sc->ranges[i].pci_base; - end -= sc->ranges[i].phys_base; - end += sc->ranges[i].pci_base; - break; - } - } - - if (i == MAX_RANGES_TUPLES) { - device_printf(bus, "Could not map resource " - "%#jx-%#jx\n", start, end); - return (NULL); - } - } - - return (bus_generic_alloc_resource(bus, child, type, rid, start, end, - count, flags)); -} - -static int -generic_pcie_release_resource_ofw(device_t bus, device_t child, int type, int rid, - struct resource *res) -{ - - return (bus_generic_release_resource(bus, child, type, rid, res)); -} - -/* Helper functions */ - -static int -generic_pcie_ofw_bus_attach(device_t dev) -{ - struct generic_pcie_ofw_devinfo *di; - device_t child; - phandle_t parent, node; - pcell_t addr_cells, size_cells; - - parent = ofw_bus_get_node(dev); - if (parent > 0) { - get_addr_size_cells(parent, &addr_cells, &size_cells); - /* Iterate through all bus subordinates */ - for (node = OF_child(parent); node > 0; node = OF_peer(node)) { - - /* Allocate and populate devinfo. */ - di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO); - if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) { - free(di, M_DEVBUF); - continue; - } - - /* Initialize and populate resource list. */ - resource_list_init(&di->di_rl); - ofw_bus_reg_to_rl(dev, node, addr_cells, size_cells, - &di->di_rl); - ofw_bus_intr_to_rl(dev, node, &di->di_rl, NULL); - - /* Add newbus device for this FDT node */ - child = device_add_child(dev, NULL, -1); - if (child == NULL) { - resource_list_free(&di->di_rl); - ofw_bus_gen_destroy_devinfo(&di->di_dinfo); - free(di, M_DEVBUF); - continue; - } - - device_set_ivars(child, di); - } - } - - return (0); -} - -DEFINE_CLASS_0(pcib, generic_pcie_driver, - generic_pcie_methods, sizeof(struct generic_pcie_softc)); - -devclass_t generic_pcie_devclass; - -DRIVER_MODULE(pcib, simplebus, generic_pcie_driver, - generic_pcie_devclass, 0, 0); -DRIVER_MODULE(pcib, ofwbus, generic_pcie_driver, - generic_pcie_devclass, 0, 0); - +DEFINE_CLASS_0(pcib, generic_pcie_core_driver, + generic_pcie_methods, sizeof(struct generic_pcie_core_softc)); Index: head/sys/dev/pci/pci_host_generic.h =================================================================== --- head/sys/dev/pci/pci_host_generic.h (revision 308930) +++ head/sys/dev/pci/pci_host_generic.h (revision 308931) @@ -1,78 +1,77 @@ /* * Copyright (c) 2015 Ruslan Bukin * Copyright (c) 2015 The FreeBSD Foundation * All rights reserved. * * This software was developed by Semihalf. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * * $FreeBSD$ * */ #ifndef __PCI_HOST_GENERIC_H_ #define __PCI_HOST_GENERIC_H_ #include "pci_if.h" #define MAX_RANGES_TUPLES 16 #define MIN_RANGES_TUPLES 2 struct pcie_range { uint64_t pci_base; uint64_t phys_base; uint64_t size; uint64_t flags; #define FLAG_IO (1 << 0) #define FLAG_MEM (1 << 1) }; -struct generic_pcie_softc { +struct generic_pcie_core_softc { struct pcie_range ranges[MAX_RANGES_TUPLES]; int nranges; int coherent; struct rman mem_rman; struct rman io_rman; struct resource *res; struct resource *res1; int ecam; bus_space_tag_t bst; bus_space_handle_t bsh; device_t dev; bus_space_handle_t ioh; bus_dma_tag_t dmat; -#ifdef FDT - struct ofw_bus_iinfo pci_iinfo; -#endif }; -extern devclass_t generic_pcie_devclass; -DECLARE_CLASS(generic_pcie_driver); +DECLARE_CLASS(generic_pcie_core_driver); -struct resource *pci_host_generic_alloc_resource(device_t, +struct resource *pci_host_generic_core_alloc_resource(device_t, device_t, int, int *, rman_res_t, rman_res_t, rman_res_t, u_int); -int pci_host_generic_attach(device_t); -int generic_pcie_get_id(device_t, device_t, enum pci_id_type, uintptr_t *); +int pci_host_generic_core_attach(device_t); +struct resource *pci_host_generic_core_alloc_resource(device_t, device_t, int, + int *, rman_res_t, rman_res_t, rman_res_t, u_int); +int pci_host_generic_core_release_resource(device_t, device_t, int, int, + struct resource *); #endif /* __PCI_HOST_GENERIC_H_ */ Index: head/sys/dev/pci/pci_host_generic_fdt.c =================================================================== --- head/sys/dev/pci/pci_host_generic_fdt.c (nonexistent) +++ head/sys/dev/pci/pci_host_generic_fdt.c (revision 308931) @@ -0,0 +1,641 @@ +/*- + * Copyright (c) 2015 Ruslan Bukin + * Copyright (c) 2014,2016 The FreeBSD Foundation + * All rights reserved. + * + * This software was developed by Andrew Turner under + * the sponsorship of the FreeBSD Foundation. + * + * This software was developed by Semihalf under + * the sponsorship of the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* Generic ECAM PCIe driver FDT attachment */ + +#include +__FBSDID("$FreeBSD$"); + +#include "opt_platform.h" + +#include +#include +#include +#include +#include +#include +#include + +#if defined(INTRNG) +#include +#endif + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "pcib_if.h" + +#define PCI_IO_WINDOW_OFFSET 0x1000 + +#define SPACE_CODE_SHIFT 24 +#define SPACE_CODE_MASK 0x3 +#define SPACE_CODE_IO_SPACE 0x1 +#define PROPS_CELL_SIZE 1 +#define PCI_ADDR_CELL_SIZE 2 + +/* OFW bus interface */ +struct generic_pcie_ofw_devinfo { + struct ofw_bus_devinfo di_dinfo; + struct resource_list di_rl; +}; + +/* Forward prototypes */ + +static int generic_pcie_fdt_probe(device_t dev); +static int parse_pci_mem_ranges(device_t, struct generic_pcie_core_softc *); +static int generic_pcie_fdt_release_resource(device_t dev, device_t child, + int type, int rid, struct resource *res); +static int generic_pcie_ofw_bus_attach(device_t); +static const struct ofw_bus_devinfo *generic_pcie_ofw_get_devinfo(device_t, + device_t); + +static __inline void +get_addr_size_cells(phandle_t node, pcell_t *addr_cells, pcell_t *size_cells) +{ + + *addr_cells = 2; + /* Find address cells if present */ + OF_getencprop(node, "#address-cells", addr_cells, sizeof(*addr_cells)); + + *size_cells = 2; + /* Find size cells if present */ + OF_getencprop(node, "#size-cells", size_cells, sizeof(*size_cells)); +} + +static int +generic_pcie_fdt_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic")) { + device_set_desc(dev, "Generic PCI host controller"); + return (BUS_PROBE_GENERIC); + } + if (ofw_bus_is_compatible(dev, "arm,gem5_pcie")) { + device_set_desc(dev, "GEM5 PCIe host controller"); + return (BUS_PROBE_DEFAULT); + } + + return (ENXIO); +} + +int +pci_host_generic_attach(device_t dev) +{ + struct generic_pcie_fdt_softc *sc; + uint64_t phys_base; + uint64_t pci_base; + uint64_t size; + phandle_t node; + int error; + int tuple; + + sc = device_get_softc(dev); + + /* Retrieve 'ranges' property from FDT */ + if (bootverbose) + device_printf(dev, "parsing FDT for ECAM%d:\n", sc->base.ecam); + if (parse_pci_mem_ranges(dev, &sc->base)) + return (ENXIO); + + /* Attach OFW bus */ + if (generic_pcie_ofw_bus_attach(dev) != 0) + return (ENXIO); + + node = ofw_bus_get_node(dev); + if (sc->base.coherent == 0) { + sc->base.coherent = OF_hasprop(node, "dma-coherent"); + } + if (bootverbose) + device_printf(dev, "Bus is%s cache-coherent\n", + sc->base.coherent ? "" : " not"); + + error = pci_host_generic_attach(dev); + if (error != 0) + return (error); + + for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { + phys_base = sc->base.ranges[tuple].phys_base; + pci_base = sc->base.ranges[tuple].pci_base; + size = sc->base.ranges[tuple].size; + if (phys_base == 0 || size == 0) + continue; /* empty range element */ + if (sc->base.ranges[tuple].flags & FLAG_MEM) { + error = rman_manage_region(&sc->base.mem_rman, + phys_base, phys_base + size - 1); + } else if (sc->base.ranges[tuple].flags & FLAG_IO) { + error = rman_manage_region(&sc->base.io_rman, + pci_base + PCI_IO_WINDOW_OFFSET, + pci_base + PCI_IO_WINDOW_OFFSET + size - 1); + } else + continue; + if (error) { + device_printf(dev, "rman_manage_region() failed." + "error = %d\n", error); + rman_fini(&sc->base.mem_rman); + return (error); + } + } + + ofw_bus_setup_iinfo(node, &sc->pci_iinfo, sizeof(cell_t)); + + device_add_child(dev, "pci", -1); + return (bus_generic_attach(dev)); +} + +static int +parse_pci_mem_ranges(device_t dev, struct generic_pcie_core_softc *sc) +{ + pcell_t pci_addr_cells, parent_addr_cells; + pcell_t attributes, size_cells; + cell_t *base_ranges; + int nbase_ranges; + phandle_t node; + int i, j, k; + int tuple; + + node = ofw_bus_get_node(dev); + + OF_getencprop(node, "#address-cells", &pci_addr_cells, + sizeof(pci_addr_cells)); + OF_getencprop(node, "#size-cells", &size_cells, + sizeof(size_cells)); + OF_getencprop(OF_parent(node), "#address-cells", &parent_addr_cells, + sizeof(parent_addr_cells)); + + if (parent_addr_cells > 2 || pci_addr_cells != 3 || size_cells > 2) { + device_printf(dev, + "Unexpected number of address or size cells in FDT\n"); + return (ENXIO); + } + + nbase_ranges = OF_getproplen(node, "ranges"); + sc->nranges = nbase_ranges / sizeof(cell_t) / + (parent_addr_cells + pci_addr_cells + size_cells); + base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK); + OF_getencprop(node, "ranges", base_ranges, nbase_ranges); + + for (i = 0, j = 0; i < sc->nranges; i++) { + attributes = (base_ranges[j++] >> SPACE_CODE_SHIFT) & \ + SPACE_CODE_MASK; + if (attributes == SPACE_CODE_IO_SPACE) { + sc->ranges[i].flags |= FLAG_IO; + } else { + sc->ranges[i].flags |= FLAG_MEM; + } + + sc->ranges[i].pci_base = 0; + for (k = 0; k < (pci_addr_cells - 1); k++) { + sc->ranges[i].pci_base <<= 32; + sc->ranges[i].pci_base |= base_ranges[j++]; + } + sc->ranges[i].phys_base = 0; + for (k = 0; k < parent_addr_cells; k++) { + sc->ranges[i].phys_base <<= 32; + sc->ranges[i].phys_base |= base_ranges[j++]; + } + sc->ranges[i].size = 0; + for (k = 0; k < size_cells; k++) { + sc->ranges[i].size <<= 32; + sc->ranges[i].size |= base_ranges[j++]; + } + } + + for (; i < MAX_RANGES_TUPLES; i++) { + /* zero-fill remaining tuples to mark empty elements in array */ + sc->ranges[i].pci_base = 0; + sc->ranges[i].phys_base = 0; + sc->ranges[i].size = 0; + } + + if (bootverbose) { + for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { + device_printf(dev, + "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx\n", + sc->ranges[tuple].pci_base, + sc->ranges[tuple].phys_base, + sc->ranges[tuple].size); + } + } + + free(base_ranges, M_DEVBUF); + return (0); +} + +static int +generic_pcie_fdt_route_interrupt(device_t bus, device_t dev, int pin) +{ + struct generic_pcie_fdt_softc *sc; + struct ofw_pci_register reg; + uint32_t pintr, mintr[2]; + phandle_t iparent; + int intrcells; + + sc = device_get_softc(bus); + pintr = pin; + + bzero(®, sizeof(reg)); + reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | + (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | + (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); + + intrcells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), + &sc->pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr), + mintr, sizeof(mintr), &iparent); + if (intrcells) { + pintr = ofw_bus_map_intr(dev, iparent, intrcells, mintr); + return (pintr); + } + + device_printf(bus, "could not route pin %d for device %d.%d\n", + pin, pci_get_slot(dev), pci_get_function(dev)); + return (PCI_INVALID_IRQ); +} + +static int +generic_pcie_fdt_release_resource(device_t dev, device_t child, int type, + int rid, struct resource *res) +{ + +#if defined(NEW_PCIB) && defined(PCI_RES_BUS) + if (type == PCI_RES_BUS) { + return (pci_host_generic_core_release_resource(dev, child, type, + rid, res)); + } +#endif + + /* For PCIe devices that do not have FDT nodes, use PCIB method */ + if ((int)ofw_bus_get_node(child) <= 0) { + return (pci_host_generic_core_release_resource(dev, child, type, + rid, res)); + } + + /* For other devices use OFW method */ + return (bus_generic_release_resource(dev, child, type, rid, res)); +} + +struct resource * +pci_host_generic_alloc_resource(device_t dev, device_t child, int type, + int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) +{ + struct generic_pcie_fdt_softc *sc; + struct generic_pcie_ofw_devinfo *di; + struct resource_list_entry *rle; + int i; + +#if defined(NEW_PCIB) && defined(PCI_RES_BUS) + if (type == PCI_RES_BUS) { + return (pci_host_generic_alloc_resource(dev, child, type, rid, + start, end, count, flags)); + } +#endif + + /* For PCIe devices that do not have FDT nodes, use PCIB method */ + if ((int)ofw_bus_get_node(child) <= 0) + return (pci_host_generic_alloc_resource(dev, child, type, rid, + start, end, count, flags)); + + /* For other devices use OFW method */ + sc = device_get_softc(dev); + + if (RMAN_IS_DEFAULT_RANGE(start, end)) { + if ((di = device_get_ivars(child)) == NULL) + return (NULL); + if (type == SYS_RES_IOPORT) + type = SYS_RES_MEMORY; + + /* Find defaults for this rid */ + rle = resource_list_find(&di->di_rl, type, *rid); + if (rle == NULL) + return (NULL); + + start = rle->start; + end = rle->end; + count = rle->count; + } + + if (type == SYS_RES_MEMORY) { + /* Remap through ranges property */ + for (i = 0; i < MAX_RANGES_TUPLES; i++) { + if (start >= sc->base.ranges[i].phys_base && + end < (sc->base.ranges[i].pci_base + + sc->base.ranges[i].size)) { + start -= sc->base.ranges[i].phys_base; + start += sc->base.ranges[i].pci_base; + end -= sc->base.ranges[i].phys_base; + end += sc->base.ranges[i].pci_base; + break; + } + } + + if (i == MAX_RANGES_TUPLES) { + device_printf(dev, "Could not map resource " + "%#jx-%#jx\n", start, end); + return (NULL); + } + } + + return (bus_generic_alloc_resource(dev, child, type, rid, start, end, + count, flags)); +} + +static int +generic_pcie_fdt_activate_resource(device_t dev, device_t child, int type, + int rid, struct resource *r) +{ + struct generic_pcie_fdt_softc *sc; + uint64_t phys_base; + uint64_t pci_base; + uint64_t size; + int found; + int res; + int i; + + sc = device_get_softc(dev); + + if ((res = rman_activate_resource(r)) != 0) + return (res); + + switch(type) { + case SYS_RES_IOPORT: + found = 0; + for (i = 0; i < MAX_RANGES_TUPLES; i++) { + pci_base = sc->base.ranges[i].pci_base; + phys_base = sc->base.ranges[i].phys_base; + size = sc->base.ranges[i].size; + + if ((rid > pci_base) && (rid < (pci_base + size))) { + found = 1; + break; + } + } + if (found) { + rman_set_start(r, rman_get_start(r) + phys_base); + rman_set_end(r, rman_get_end(r) + phys_base); + res = BUS_ACTIVATE_RESOURCE(device_get_parent(dev), + child, type, rid, r); + } else { + device_printf(dev, + "Failed to activate IOPORT resource\n"); + res = 0; + } + break; + case SYS_RES_MEMORY: + res = BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child, + type, rid, r); + break; + default: + break; + } + + return (res); +} + +static int +generic_pcie_fdt_deactivate_resource(device_t dev, device_t child, int type, + int rid, struct resource *r) +{ + int res; + + if ((res = rman_deactivate_resource(r)) != 0) + return (res); + + switch(type) { + case SYS_RES_IOPORT: + case SYS_RES_MEMORY: + res = BUS_DEACTIVATE_RESOURCE(device_get_parent(dev), child, + type, rid, r); + break; + default: + break; + } + + return (res); +} + +static int +generic_pcie_fdt_alloc_msi(device_t pci, device_t child, int count, + int maxcount, int *irqs) +{ +#if defined(INTRNG) + phandle_t msi_parent; + + ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, + NULL); + return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, + irqs)); +#else + return (ENXIO); +#endif +} + +static int +generic_pcie_fdt_release_msi(device_t pci, device_t child, int count, int *irqs) +{ +#if defined(INTRNG) + phandle_t msi_parent; + + ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, + NULL); + return (intr_release_msi(pci, child, msi_parent, count, irqs)); +#else + return (ENXIO); +#endif +} + +static int +generic_pcie_fdt_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, + uint32_t *data) +{ +#if defined(INTRNG) + phandle_t msi_parent; + + ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, + NULL); + return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); +#else + return (ENXIO); +#endif +} + +static int +generic_pcie_fdt_alloc_msix(device_t pci, device_t child, int *irq) +{ +#if defined(INTRNG) + phandle_t msi_parent; + + ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, + NULL); + return (intr_alloc_msix(pci, child, msi_parent, irq)); +#else + return (ENXIO); +#endif +} + +static int +generic_pcie_fdt_release_msix(device_t pci, device_t child, int irq) +{ +#if defined(INTRNG) + phandle_t msi_parent; + + ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, + NULL); + return (intr_release_msix(pci, child, msi_parent, irq)); +#else + return (ENXIO); +#endif +} + +int +generic_pcie_get_id(device_t pci, device_t child, enum pci_id_type type, + uintptr_t *id) +{ + phandle_t node; + uint32_t rid; + uint16_t pci_rid; + + if (type != PCI_ID_MSI) + return (pcib_get_id(pci, child, type, id)); + + node = ofw_bus_get_node(pci); + pci_rid = pci_get_rid(child); + + ofw_bus_msimap(node, pci_rid, NULL, &rid); + *id = rid; + + return (0); +} + +static const struct ofw_bus_devinfo * +generic_pcie_ofw_get_devinfo(device_t bus __unused, device_t child) +{ + struct generic_pcie_ofw_devinfo *di; + + di = device_get_ivars(child); + return (&di->di_dinfo); +} + +/* Helper functions */ + +static int +generic_pcie_ofw_bus_attach(device_t dev) +{ + struct generic_pcie_ofw_devinfo *di; + device_t child; + phandle_t parent, node; + pcell_t addr_cells, size_cells; + + parent = ofw_bus_get_node(dev); + if (parent > 0) { + get_addr_size_cells(parent, &addr_cells, &size_cells); + /* Iterate through all bus subordinates */ + for (node = OF_child(parent); node > 0; node = OF_peer(node)) { + + /* Allocate and populate devinfo. */ + di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO); + if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) { + free(di, M_DEVBUF); + continue; + } + + /* Initialize and populate resource list. */ + resource_list_init(&di->di_rl); + ofw_bus_reg_to_rl(dev, node, addr_cells, size_cells, + &di->di_rl); + ofw_bus_intr_to_rl(dev, node, &di->di_rl, NULL); + + /* Add newbus device for this FDT node */ + child = device_add_child(dev, NULL, -1); + if (child == NULL) { + resource_list_free(&di->di_rl); + ofw_bus_gen_destroy_devinfo(&di->di_dinfo); + free(di, M_DEVBUF); + continue; + } + + device_set_ivars(child, di); + } + } + + return (0); +} + +static device_method_t generic_pcie_fdt_methods[] = { + DEVMETHOD(device_probe, generic_pcie_fdt_probe), + DEVMETHOD(device_attach, pci_host_generic_attach), + DEVMETHOD(bus_alloc_resource, pci_host_generic_alloc_resource), + DEVMETHOD(bus_release_resource, generic_pcie_fdt_release_resource), + DEVMETHOD(bus_activate_resource, generic_pcie_fdt_activate_resource), + DEVMETHOD(bus_deactivate_resource,generic_pcie_fdt_deactivate_resource), + + /* pcib interface */ + DEVMETHOD(pcib_route_interrupt, generic_pcie_fdt_route_interrupt), + DEVMETHOD(pcib_alloc_msi, generic_pcie_fdt_alloc_msi), + DEVMETHOD(pcib_release_msi, generic_pcie_fdt_release_msi), + DEVMETHOD(pcib_alloc_msix, generic_pcie_fdt_alloc_msix), + DEVMETHOD(pcib_release_msix, generic_pcie_fdt_release_msix), + DEVMETHOD(pcib_map_msi, generic_pcie_fdt_map_msi), + DEVMETHOD(pcib_get_id, generic_pcie_get_id), + + /* ofw_bus interface */ + DEVMETHOD(ofw_bus_get_devinfo, generic_pcie_ofw_get_devinfo), + DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), + DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), + DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), + DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), + DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), + + DEVMETHOD_END +}; + +DEFINE_CLASS_1(pcib, generic_pcie_fdt_driver, generic_pcie_fdt_methods, + sizeof(struct generic_pcie_fdt_softc), generic_pcie_core_driver); + +static devclass_t generic_pcie_fdt_devclass; + +DRIVER_MODULE(pcib, simplebus, generic_pcie_fdt_driver, + generic_pcie_fdt_devclass, 0, 0); +DRIVER_MODULE(pcib, ofwbus, generic_pcie_fdt_driver, generic_pcie_fdt_devclass, + 0, 0); Property changes on: head/sys/dev/pci/pci_host_generic_fdt.c ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/dev/pci/pci_host_generic_fdt.h =================================================================== --- head/sys/dev/pci/pci_host_generic_fdt.h (nonexistent) +++ head/sys/dev/pci/pci_host_generic_fdt.h (revision 308931) @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2015 Ruslan Bukin + * Copyright (c) 2015 The FreeBSD Foundation + * All rights reserved. + * + * This software was developed by Semihalf. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + * $FreeBSD$ + * + */ + +#ifndef __PCI_HOST_GENERIC_FDT_H_ +#define __PCI_HOST_GENERIC_FDT_H_ + +struct generic_pcie_fdt_softc { + struct generic_pcie_core_softc base; + struct ofw_bus_iinfo pci_iinfo; +}; + +DECLARE_CLASS(generic_pcie_fdt_driver); + +struct resource *pci_host_generic_alloc_resource(device_t, + device_t, int, int *, rman_res_t, rman_res_t, rman_res_t, u_int); +int pci_host_generic_attach(device_t); +int generic_pcie_get_id(device_t, device_t, enum pci_id_type, uintptr_t *); + +#endif /* __PCI_HOST_GENERIC_FDT_H_ */ Property changes on: head/sys/dev/pci/pci_host_generic_fdt.h ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property