Index: head/lib/libcompiler_rt/Makefile.inc =================================================================== --- head/lib/libcompiler_rt/Makefile.inc (revision 308250) +++ head/lib/libcompiler_rt/Makefile.inc (revision 308251) @@ -1,216 +1,219 @@ # $FreeBSD$ CRTARCH= ${MACHINE_CPUARCH:C/amd64/x86_64/} CRTSRC= ${SRCTOP}/contrib/compiler-rt/lib/builtins .PATH: ${CRTSRC}/${CRTARCH} .PATH: ${CRTSRC} SRCF+= absvdi2 SRCF+= absvsi2 SRCF+= absvti2 SRCF+= addvdi3 SRCF+= addvsi3 SRCF+= addvti3 SRCF+= apple_versioning SRCF+= ashldi3 SRCF+= ashlti3 SRCF+= ashrdi3 SRCF+= ashrti3 SRCF+= clear_cache SRCF+= clzdi2 SRCF+= clzsi2 SRCF+= clzti2 SRCF+= cmpdi2 SRCF+= cmpti2 SRCF+= ctzdi2 SRCF+= ctzsi2 SRCF+= ctzti2 SRCF+= divdc3 SRCF+= divdi3 SRCF+= divmoddi4 SRCF+= divmodsi4 SRCF+= divsc3 SRCF+= divtc3 SRCF+= divti3 SRCF+= divxc3 SRCF+= enable_execute_stack SRCF+= eprintf SRCF+= extendhfsf2 SRCF+= ffsdi2 SRCF+= ffsti2 SRCF+= fixdfdi SRCF+= fixdfti SRCF+= fixsfdi SRCF+= fixsfti SRCF+= fixunsdfdi SRCF+= fixunsdfsi SRCF+= fixunsdfti SRCF+= fixunssfdi SRCF+= fixunssfsi SRCF+= fixunssfti SRCF+= fixunsxfdi SRCF+= fixunsxfsi SRCF+= fixunsxfti SRCF+= fixxfdi SRCF+= fixxfti SRCF+= floatdidf SRCF+= floatdisf SRCF+= floatditf SRCF+= floatdixf SRCF+= floatsitf SRCF+= floattidf SRCF+= floattisf SRCF+= floattixf SRCF+= floatundidf SRCF+= floatundisf SRCF+= floatunditf SRCF+= floatundixf SRCF+= floatunsidf SRCF+= floatunsisf SRCF+= floatuntidf SRCF+= floatuntisf SRCF+= floatuntixf SRCF+= gcc_personality_v0 SRCF+= int_util SRCF+= lshrdi3 SRCF+= lshrti3 SRCF+= moddi3 SRCF+= modti3 SRCF+= muldc3 SRCF+= muldi3 SRCF+= mulodi4 SRCF+= mulosi4 SRCF+= muloti4 SRCF+= mulsc3 SRCF+= multi3 SRCF+= mulvdi3 SRCF+= mulvsi3 SRCF+= mulvti3 SRCF+= multc3 SRCF+= mulxc3 SRCF+= negdf2 SRCF+= negdi2 SRCF+= negsf2 SRCF+= negti2 SRCF+= negvdi2 SRCF+= negvsi2 SRCF+= negvti2 SRCF+= paritydi2 SRCF+= paritysi2 SRCF+= parityti2 SRCF+= popcountdi2 SRCF+= popcountsi2 SRCF+= popcountti2 SRCF+= powidf2 SRCF+= powisf2 SRCF+= powitf2 SRCF+= powixf2 SRCF+= subvdi3 SRCF+= subvsi3 SRCF+= subvti3 SRCF+= trampoline_setup SRCF+= truncdfhf2 SRCF+= truncsfhf2 SRCF+= ucmpdi2 SRCF+= ucmpti2 SRCF+= udivdi3 SRCF+= udivmoddi4 SRCF+= udivmodsi4 SRCF+= udivmodti4 SRCF+= udivti3 SRCF+= umoddi3 SRCF+= umodti3 -# 128-bit quad precision long double support, only used on arm64 -.if ${MACHINE_CPUARCH} == "aarch64" +# +# 128-bit quad precision long double support, +# only used on arm64 and riscv. +# +.if ${MACHINE_CPUARCH} == "aarch64" || ${MACHINE_CPUARCH} == "riscv" SRCF+= addtf3 SRCF+= comparetf2 SRCF+= divtf3 SRCF+= extenddftf2 SRCF+= extendsftf2 SRCF+= fixtfdi SRCF+= fixtfsi SRCF+= fixtfti SRCF+= fixunstfdi SRCF+= fixunstfsi SRCF+= fixunstfti SRCF+= floatunsitf SRCF+= multf3 SRCF+= subtf3 SRCF+= trunctfdf2 SRCF+= trunctfsf2 .endif # These are already shipped by libc.a on arm and mips .if ${MACHINE_CPUARCH} != "arm" && ${MACHINE_CPUARCH} != "mips" SRCF+= adddf3 SRCF+= addsf3 SRCF+= divdf3 SRCF+= divsf3 SRCF+= extendsfdf2 SRCF+= fixdfsi SRCF+= fixsfsi SRCF+= floatsidf SRCF+= floatsisf SRCF+= muldf3 SRCF+= mulsf3 SRCF+= subdf3 SRCF+= subsf3 SRCF+= truncdfsf2 .endif .if ${MACHINE_CPUARCH} != "arm" SRCF+= comparedf2 SRCF+= comparesf2 .endif .if ${MACHINE_CPUARCH} != "mips" SRCF+= divsi3 SRCF+= modsi3 SRCF+= udivsi3 SRCF+= umodsi3 .endif # FreeBSD-specific atomic intrinsics. .if ${MACHINE_CPUARCH} == "arm" || ${MACHINE_CPUARCH} == "armv6" .PATH: ${SRCTOP}/sys/arm/arm SRCF+= stdatomic CFLAGS+= -DEMIT_SYNC_ATOMICS .elif ${MACHINE_CPUARCH} == "mips" .PATH: ${SRCTOP}/sys/mips/mips SRCF+= stdatomic .endif .for file in ${SRCF} .if ${MACHINE_ARCH:Marmv6*} && (!defined(CPUTYPE) || ${CPUTYPE:M*soft*} == "") \ && exists(${CRTSRC}/${CRTARCH}/${file}vfp.S) SRCS+= ${file}vfp.S . elif exists(${CRTSRC}/${CRTARCH}/${file}.S) SRCS+= ${file}.S . else SRCS+= ${file}.c . endif .endfor .if ${MACHINE_CPUARCH} == "arm" SRCS+= aeabi_div0.c SRCS+= aeabi_idivmod.S SRCS+= aeabi_ldivmod.S SRCS+= aeabi_memcmp.S SRCS+= aeabi_memcpy.S SRCS+= aeabi_memmove.S SRCS+= aeabi_memset.S SRCS+= aeabi_uidivmod.S SRCS+= aeabi_uldivmod.S SRCS+= bswapdi2.S SRCS+= bswapsi2.S SRCS+= switch16.S SRCS+= switch32.S SRCS+= switch8.S SRCS+= switchu8.S SRCS+= sync_synchronize.S .endif Index: head/lib/msun/riscv/Makefile.inc =================================================================== --- head/lib/msun/riscv/Makefile.inc (revision 308250) +++ head/lib/msun/riscv/Makefile.inc (revision 308251) @@ -1,6 +1,3 @@ # $FreeBSD$ -# RISCVTODO: should be 113 -# compilation problems: gcc generates bltuz instruction, which is not exists - -LDBL_PREC = 53 +LDBL_PREC = 113 Index: head/share/man/man7/arch.7 =================================================================== --- head/share/man/man7/arch.7 (revision 308250) +++ head/share/man/man7/arch.7 (revision 308251) @@ -1,193 +1,193 @@ .\" Copyright (c) 2016 The FreeBSD Foundation. All rights reserved. .\" .\" This documentation was created by Ed Maste under sponsorship of .\" The FreeBSD Foundation. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" .Dd October 20, 2016 .Dt ARCH 7 .Os .Sh NAME .Nm arch .Nd Architecture-specific details .Sh DESCRIPTION Differences between CPU architectures and platforms supported by .Fx . .Pp .Ss Type sizes On all supported architectures, .Bl -column -offset -indent "long long" "Size" .It Sy Type Ta Sy Size .It short Ta 2 .It int Ta 4 .It long Ta sizeof(void*) .It long long Ta 8 .It float Ta 4 .It double Ta 8 .El .Bl -column -offset indent "Sy Architecture" "Sy sizeof(void *)" "Sy sizeof(long double)" .It Sy Architecture Ta Sy sizeof(void *) Ta Sy sizeof(long double) .It amd64 Ta 8 Ta 16 .It arm Ta 4 Ta 8 .It armeb Ta 4 Ta 8 .It armv6 Ta 4 Ta 8 .It arm64 Ta 8 Ta 16 .It i386 Ta 4 Ta 12 .It mips Ta 4 Ta 8 .It mipsel Ta 4 Ta 8 .It mipselhf Ta 4 Ta 8 .It mipshf Ta 4 Ta 8 .It mipsn32 Ta 4 Ta 8 .It mips64 Ta 8 Ta 8 .It mips64el Ta 8 Ta 8 .It mips64elhf Ta 8 Ta 8 .It mips64hf Ta 8 Ta 8 .It powerpc Ta 4 Ta 8 .It powerpc64 Ta 8 Ta 8 -.It riscv Ta 8 Ta +.It riscv Ta 8 Ta 16 .It sparc64 Ta 8 Ta 16 .El .Ss Endianness and Char Signedness .Bl -column -offset indent "Sy Architecture" "Sy Endianness" "Sy char Signedness" .It Sy Architecture Ta Sy Endianness Ta Sy char Signedness .It amd64 Ta little Ta signed .It arm Ta little Ta unsigned .It armeb Ta big Ta unsigned .It armv6 Ta little Ta unsigned .It arm64 Ta little Ta unsigned .It i386 Ta little Ta signed .It mips Ta big Ta signed .It mipsel Ta little Ta signed .It mipselhf Ta little Ta signed .It mipshf Ta big Ta signed .It mipsn32 Ta big Ta signed .It mips64 Ta big Ta signed .It mips64el Ta little Ta signed .It mips64elhf Ta little Ta signed .It mips64hf Ta big Ta signed .It powerpc Ta big Ta unsigned .It powerpc64 Ta big Ta unsigned .It riscv Ta little Ta signed .It sparc64 Ta big Ta signed .El .Ss Page Size .Bl -column -offset indent "Sy Architecture" "Sy Page Sizes" .It Sy Architecture Ta Sy Page Sizes .It amd64 Ta 4K, 2M, 1G .It arm Ta 4K .It armeb Ta 4K .It armv6 Ta 4K, 1M .It arm64 Ta 4K, 2M, 1G .It i386 Ta 4K, 2M (PAE), 4M .It mips Ta 4K .It mipsel Ta 4K .It mipselhf Ta 4K .It mipshf Ta 4K .It mipsn32 Ta 4K .It mips64 Ta 4K .It mips64el Ta 4K .It mips64elhf Ta 4K .It mips64hf Ta 4K .It powerpc Ta 4K .It powerpc64 Ta 4K .It riscv Ta 4K .It sparc64 Ta 8K .El .Ss Floating Point .Bl -column -offset indent "Sy Architecture" "Sy float, double" "Sy long double" .It Sy Architecture Ta Sy float, double Ta Sy long double .It amd64 Ta hard Ta hard, 80 bit .It arm Ta soft Ta soft, double precision .It armeb Ta soft Ta soft, double precision .It armv6 Ta hard Ta hard, double precision .It arm64 Ta hard Ta soft, quad precision .It i386 Ta hard Ta hard, 80 bit .It mips Ta soft Ta identical to double .It mipsel Ta soft Ta identical to double .It mipselhf Ta hard Ta identical to double .It mipshf Ta hard Ta identical to double .It mipsn32 Ta soft Ta identical to double .It mips64 Ta soft Ta identical to double .It mips64el Ta soft Ta identical to double .It mips64elhf Ta hard Ta identical to double .It mips64hf Ta hard Ta identical to double .It powerpc Ta hard Ta hard, double precision .It powerpc64 Ta hard Ta hard, double precision .It riscv Ta .It sparc64 Ta hard Ta hard, quad precision .El .Ss Predefined Macros The compiler provides a number of predefined macros. Some of these provide architecture-specific details and are explained below. Other macros, including those required by the language standard, are not included here. .Pp The full set of predefined macros can be obtained with this command: .Bd -literal -offset indent cc -x c -dM -E /dev/null .Ed .Pp Common type size and endianness macros: .Bl -column -offset indent "BYTE_ORDER" "Sy Meaning" .It Sy Macro Ta Sy Meaning .It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int .It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer .It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN . .Dv PDP11_ENDIAN is not used on .Fx . .El .Pp Architecture-specific macros: .Bl -column -offset indent "Sy Architecture" "Sy Predefined macros" .It Sy Architecture Ta Sy Predefined macros .It amd64 Ta Dv __amd64__, Dv __x86_64__ .It arm Ta Dv __arm__ .It armeb Ta Dv __arm__ .It armv6 Ta Dv __arm__, Dv __ARM_ARCH >= 6 .It arm64 Ta Dv __aarch64__ .It i386 Ta Dv __i386__ .It mips Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32 .It mipsel Ta Dv __mips__, Dv __mips_o32 .It mipselhf Ta Dv __mips__, Dv __mips_o32 .It mipshf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32 .It mipsn32 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n32 .It mips64 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64 .It mips64el Ta Dv __mips__, Dv __mips_n64 .It mips64elhf Ta Dv __mips__, Dv __mips_n64 .It mips64hf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64 .It powerpc Ta Dv __powerpc__ .It powerpc64 Ta Dv __powerpc__, Dv __powerpc64__ .It riscv Ta Dv __riscv__, Dv __riscv64 .It sparc64 Ta Dv __sparc64__ .El .Sh SEE ALSO .Xr src.conf 5 , .Xr build 7 .Sh HISTORY An .Nm manual page appeared in .Fx 12 . Index: head/share/mk/bsd.cpu.mk =================================================================== --- head/share/mk/bsd.cpu.mk (revision 308250) +++ head/share/mk/bsd.cpu.mk (revision 308251) @@ -1,374 +1,374 @@ # $FreeBSD$ # Set default CPU compile flags and baseline CPUTYPE for each arch. The # compile flags must support the minimum CPU type for each architecture but # may tune support for more advanced processors. .if !defined(CPUTYPE) || empty(CPUTYPE) _CPUCFLAGS = . if ${MACHINE_CPUARCH} == "aarch64" MACHINE_CPU = arm64 . elif ${MACHINE_CPUARCH} == "amd64" MACHINE_CPU = amd64 sse2 sse mmx . elif ${MACHINE_CPUARCH} == "arm" MACHINE_CPU = arm . elif ${MACHINE_CPUARCH} == "i386" MACHINE_CPU = i486 . elif ${MACHINE_CPUARCH} == "mips" MACHINE_CPU = mips . elif ${MACHINE_CPUARCH} == "powerpc" MACHINE_CPU = aim . elif ${MACHINE_CPUARCH} == "riscv" MACHINE_CPU = riscv . elif ${MACHINE_CPUARCH} == "sparc64" MACHINE_CPU = ultrasparc . endif .else # Handle aliases (not documented in make.conf to avoid user confusion # between e.g. i586 and pentium) . if ${MACHINE_CPUARCH} == "amd64" || ${MACHINE_CPUARCH} == "i386" . if ${CPUTYPE} == "barcelona" CPUTYPE = amdfam10 . elif ${CPUTYPE} == "core-avx2" CPUTYPE = haswell . elif ${CPUTYPE} == "core-avx-i" CPUTYPE = ivybridge . elif ${CPUTYPE} == "corei7-avx" CPUTYPE = sandybridge . elif ${CPUTYPE} == "corei7" CPUTYPE = nehalem . elif ${CPUTYPE} == "slm" CPUTYPE = silvermont . elif ${CPUTYPE} == "atom" CPUTYPE = bonnell . elif ${CPUTYPE} == "core" CPUTYPE = prescott . endif . if ${MACHINE_CPUARCH} == "amd64" . if ${CPUTYPE} == "prescott" CPUTYPE = nocona . endif . else . if ${CPUTYPE} == "k7" CPUTYPE = athlon . elif ${CPUTYPE} == "p4" CPUTYPE = pentium4 . elif ${CPUTYPE} == "p4m" CPUTYPE = pentium4m . elif ${CPUTYPE} == "p3" CPUTYPE = pentium3 . elif ${CPUTYPE} == "p3m" CPUTYPE = pentium3m . elif ${CPUTYPE} == "p-m" CPUTYPE = pentium-m . elif ${CPUTYPE} == "p2" CPUTYPE = pentium2 . elif ${CPUTYPE} == "i686" CPUTYPE = pentiumpro . elif ${CPUTYPE} == "i586/mmx" CPUTYPE = pentium-mmx . elif ${CPUTYPE} == "i586" CPUTYPE = pentium . endif . endif . elif ${MACHINE_ARCH} == "sparc64" . if ${CPUTYPE} == "us" CPUTYPE = ultrasparc . elif ${CPUTYPE} == "us3" CPUTYPE = ultrasparc3 . endif . endif ############################################################################### # Logic to set up correct gcc optimization flag. This must be included # after /etc/make.conf so it can react to the local value of CPUTYPE # defined therein. Consult: # http://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html # http://gcc.gnu.org/onlinedocs/gcc/RS-6000-and-PowerPC-Options.html # http://gcc.gnu.org/onlinedocs/gcc/MIPS-Options.html # http://gcc.gnu.org/onlinedocs/gcc/SPARC-Options.html # http://gcc.gnu.org/onlinedocs/gcc/i386-and-x86_002d64-Options.html . if ${MACHINE_CPUARCH} == "i386" . if ${CPUTYPE} == "crusoe" _CPUCFLAGS = -march=i686 -falign-functions=0 -falign-jumps=0 -falign-loops=0 . elif ${CPUTYPE} == "k5" _CPUCFLAGS = -march=pentium . elif ${CPUTYPE} == "c7" _CPUCFLAGS = -march=c3-2 . else _CPUCFLAGS = -march=${CPUTYPE} . endif . elif ${MACHINE_CPUARCH} == "amd64" _CPUCFLAGS = -march=${CPUTYPE} . elif ${MACHINE_CPUARCH} == "arm" . if ${CPUTYPE} == "xscale" #XXX: gcc doesn't seem to like -mcpu=xscale, and dies while rebuilding itself #_CPUCFLAGS = -mcpu=xscale _CPUCFLAGS = -march=armv5te -D__XSCALE__ . elif ${CPUTYPE:M*soft*} != "" _CPUCFLAGS = -mfloat-abi=softfp . elif ${CPUTYPE} == "armv6" # Not sure we still need ARM_ARCH_6=1 here. _CPUCFLAGS = -march=${CPUTYPE} -DARM_ARCH_6=1 . elif ${CPUTYPE} == "cortexa" _CPUCFLAGS = -march=armv7 -DARM_ARCH_6=1 -mfpu=vfp . elif ${CPUTYPE:Marmv[4567]*} != "" # Handle all the armvX types that FreeBSD runs: # armv4, armv4t, armv5, armv5te, armv6, armv6t2, armv7, armv7-a, armv7ve # they require -march=. All the others require -mcpu=. _CPUCFLAGS = -march=${CPUTYPE} . else # Common values for FreeBSD # arm: (any arm v4 or v5 processor you are targeting) # arm920t, arm926ej-s, marvell-pj4, fa526, fa626, # fa606te, fa626te, fa726te # armv6: (any arm v7 or v8 processor you are targeting and the arm1176jzf-s) # arm1176jzf-s, generic-armv7-a, cortex-a5, cortex-a7, cortex-a8, # cortex-a9, cortex-a12, cortex-a15, cortex-a17, cortex-a53, cortex-a57, # cortex-a72, exynos-m1 _CPUCFLAGS = -mcpu=${CPUTYPE} . endif . elif ${MACHINE_ARCH} == "powerpc" . if ${CPUTYPE} == "e500" _CPUCFLAGS = -Wa,-me500 -msoft-float . else _CPUCFLAGS = -mcpu=${CPUTYPE} -mno-powerpc64 . endif . elif ${MACHINE_ARCH} == "powerpcspe" _CPUCFLAGS = -Wa,-me500 -mspe=yes -mabi=spe -mfloat-gprs=double . elif ${MACHINE_ARCH} == "powerpc64" _CPUCFLAGS = -mcpu=${CPUTYPE} . elif ${MACHINE_CPUARCH} == "mips" # mips[1234], mips32, mips64, and all later releases need to have mips # preserved (releases later than r2 require external toolchain) . if ${CPUTYPE:Mmips32*} != "" || ${CPUTYPE:Mmips64*} != "" || \ ${CPUTYPE:Mmips[1234]} != "" _CPUCFLAGS = -march=${CPUTYPE} . else # Default -march to the CPUTYPE passed in, with mips stripped off so we # accept either mips4kc or 4kc, mostly for historical reasons # Typical values for cores: # 4kc, 24kc, 34kc, 74kc, 1004kc, octeon, octeon+, octeon2, octeon3, # sb1, xlp, xlr _CPUCFLAGS = -march=${CPUTYPE:S/^mips//} . endif . elif ${MACHINE_CPUARCH} == "riscv" -_CPUCFLAGS = -msoft-float # -march="RV64I" # RISCVTODO +_CPUCFLAGS = -mno-float -march="IMAFD" . elif ${MACHINE_ARCH} == "sparc64" . if ${CPUTYPE} == "v9" _CPUCFLAGS = -mcpu=v9 . elif ${CPUTYPE} == "ultrasparc" _CPUCFLAGS = -mcpu=ultrasparc . elif ${CPUTYPE} == "ultrasparc3" _CPUCFLAGS = -mcpu=ultrasparc3 . endif . elif ${MACHINE_CPUARCH} == "aarch64" _CPUCFLAGS = -mcpu=${CPUTYPE} . endif # Set up the list of CPU features based on the CPU type. This is an # unordered list to make it easy for client makefiles to test for the # presence of a CPU feature. ########## i386 . if ${MACHINE_CPUARCH} == "i386" . if ${CPUTYPE} == "bdver4" MACHINE_CPU = xop avx2 avx sse42 sse41 ssse3 sse4a sse3 sse2 sse mmx k6 k5 i586 . elif ${CPUTYPE} == "bdver3" || ${CPUTYPE} == "bdver2" || \ ${CPUTYPE} == "bdver1" MACHINE_CPU = xop avx sse42 sse41 ssse3 sse4a sse3 sse2 sse mmx k6 k5 i586 . elif ${CPUTYPE} == "btver2" MACHINE_CPU = avx sse42 sse41 ssse3 sse4a sse3 sse2 sse mmx k6 k5 i586 . elif ${CPUTYPE} == "btver1" MACHINE_CPU = ssse3 sse4a sse3 sse2 sse mmx k6 k5 i586 . elif ${CPUTYPE} == "amdfam10" MACHINE_CPU = athlon-xp athlon k7 3dnow sse4a sse3 sse2 sse mmx k6 k5 i586 . elif ${CPUTYPE} == "opteron-sse3" || ${CPUTYPE} == "athlon64-sse3" MACHINE_CPU = athlon-xp athlon k7 3dnow sse3 sse2 sse mmx k6 k5 i586 . elif ${CPUTYPE} == "opteron" || ${CPUTYPE} == "athlon64" || \ ${CPUTYPE} == "athlon-fx" MACHINE_CPU = athlon-xp athlon k7 3dnow sse2 sse mmx k6 k5 i586 . elif ${CPUTYPE} == "athlon-mp" || ${CPUTYPE} == "athlon-xp" || \ ${CPUTYPE} == "athlon-4" MACHINE_CPU = athlon-xp athlon k7 3dnow sse mmx k6 k5 i586 . elif ${CPUTYPE} == "athlon" || ${CPUTYPE} == "athlon-tbird" MACHINE_CPU = athlon k7 3dnow mmx k6 k5 i586 . elif ${CPUTYPE} == "k6-3" || ${CPUTYPE} == "k6-2" || ${CPUTYPE} == "geode" MACHINE_CPU = 3dnow mmx k6 k5 i586 . elif ${CPUTYPE} == "k6" MACHINE_CPU = mmx k6 k5 i586 . elif ${CPUTYPE} == "k5" MACHINE_CPU = k5 i586 . elif ${CPUTYPE} == "skylake" || ${CPUTYPE} == "knl" MACHINE_CPU = avx512 avx2 avx sse42 sse41 ssse3 sse3 sse2 sse i686 mmx i586 . elif ${CPUTYPE} == "broadwell" || ${CPUTYPE} == "haswell" MACHINE_CPU = avx2 avx sse42 sse41 ssse3 sse3 sse2 sse i686 mmx i586 . elif ${CPUTYPE} == "ivybridge" || ${CPUTYPE} == "sandybridge" MACHINE_CPU = avx sse42 sse41 ssse3 sse3 sse2 sse i686 mmx i586 . elif ${CPUTYPE} == "westmere" || ${CPUTYPE} == "nehalem" || \ ${CPUTYPE} == "silvermont" MACHINE_CPU = sse42 sse41 ssse3 sse3 sse2 sse i686 mmx i586 . elif ${CPUTYPE} == "penryn" MACHINE_CPU = sse41 ssse3 sse3 sse2 sse i686 mmx i586 . elif ${CPUTYPE} == "core2" || ${CPUTYPE} == "bonnell" MACHINE_CPU = ssse3 sse3 sse2 sse i686 mmx i586 . elif ${CPUTYPE} == "yonah" || ${CPUTYPE} == "prescott" MACHINE_CPU = sse3 sse2 sse i686 mmx i586 . elif ${CPUTYPE} == "pentium4" || ${CPUTYPE} == "pentium4m" || \ ${CPUTYPE} == "pentium-m" MACHINE_CPU = sse2 sse i686 mmx i586 . elif ${CPUTYPE} == "pentium3" || ${CPUTYPE} == "pentium3m" MACHINE_CPU = sse i686 mmx i586 . elif ${CPUTYPE} == "pentium2" MACHINE_CPU = i686 mmx i586 . elif ${CPUTYPE} == "pentiumpro" MACHINE_CPU = i686 i586 . elif ${CPUTYPE} == "pentium-mmx" MACHINE_CPU = mmx i586 . elif ${CPUTYPE} == "pentium" MACHINE_CPU = i586 . elif ${CPUTYPE} == "c7" MACHINE_CPU = sse3 sse2 sse i686 mmx i586 . elif ${CPUTYPE} == "c3-2" MACHINE_CPU = sse i686 mmx i586 . elif ${CPUTYPE} == "c3" MACHINE_CPU = 3dnow mmx i586 . elif ${CPUTYPE} == "winchip2" MACHINE_CPU = 3dnow mmx . elif ${CPUTYPE} == "winchip-c6" MACHINE_CPU = mmx . endif MACHINE_CPU += i486 ########## amd64 . elif ${MACHINE_CPUARCH} == "amd64" . if ${CPUTYPE} == "bdver4" MACHINE_CPU = xop avx2 avx sse42 sse41 ssse3 sse4a sse3 . elif ${CPUTYPE} == "bdver3" || ${CPUTYPE} == "bdver2" || \ ${CPUTYPE} == "bdver1" MACHINE_CPU = xop avx sse42 sse41 ssse3 sse4a sse3 . elif ${CPUTYPE} == "btver2" MACHINE_CPU = avx sse42 sse41 ssse3 sse4a sse3 . elif ${CPUTYPE} == "btver1" MACHINE_CPU = ssse3 sse4a sse3 . elif ${CPUTYPE} == "amdfam10" MACHINE_CPU = k8 3dnow sse4a sse3 . elif ${CPUTYPE} == "opteron-sse3" || ${CPUTYPE} == "athlon64-sse3" || \ ${CPUTYPE} == "k8-sse3" MACHINE_CPU = k8 3dnow sse3 . elif ${CPUTYPE} == "opteron" || ${CPUTYPE} == "athlon64" || \ ${CPUTYPE} == "athlon-fx" || ${CPUTYPE} == "k8" MACHINE_CPU = k8 3dnow . elif ${CPUTYPE} == "skylake" || ${CPUTYPE} == "knl" MACHINE_CPU = avx512 avx2 avx sse42 sse41 ssse3 sse3 . elif ${CPUTYPE} == "broadwell" || ${CPUTYPE} == "haswell" MACHINE_CPU = avx2 avx sse42 sse41 ssse3 sse3 . elif ${CPUTYPE} == "ivybridge" || ${CPUTYPE} == "sandybridge" MACHINE_CPU = avx sse42 sse41 ssse3 sse3 . elif ${CPUTYPE} == "westmere" || ${CPUTYPE} == "nehalem" || \ ${CPUTYPE} == "silvermont" MACHINE_CPU = sse42 sse41 ssse3 sse3 . elif ${CPUTYPE} == "penryn" MACHINE_CPU = sse41 ssse3 sse3 . elif ${CPUTYPE} == "core2" || ${CPUTYPE} == "bonnell" MACHINE_CPU = ssse3 sse3 . elif ${CPUTYPE} == "nocona" MACHINE_CPU = sse3 . endif MACHINE_CPU += amd64 sse2 sse mmx ########## Mips . elif ${MACHINE_CPUARCH} == "mips" MACHINE_CPU = mips ########## powerpc . elif ${MACHINE_ARCH} == "powerpc" . if ${CPUTYPE} == "e500" MACHINE_CPU = booke softfp . endif ########## riscv . elif ${MACHINE_CPUARCH} == "riscv" MACHINE_CPU = riscv ########## sparc64 . elif ${MACHINE_ARCH} == "sparc64" . if ${CPUTYPE} == "v9" MACHINE_CPU = v9 . elif ${CPUTYPE} == "ultrasparc" MACHINE_CPU = v9 ultrasparc . elif ${CPUTYPE} == "ultrasparc3" MACHINE_CPU = v9 ultrasparc ultrasparc3 . endif . endif .endif .if ${MACHINE_CPUARCH} == "mips" CFLAGS += -G0 .if ${TARGET_ARCH:Mmips*hf} CFLAGS += -mhard-float .endif .endif ########## arm .if ${MACHINE_CPUARCH} == "arm" MACHINE_CPU += arm . if ${MACHINE_ARCH:Marmv6*} != "" MACHINE_CPU += armv6 . endif # armv6 is a hybrid. It can use the softfp ABI, but doesn't emulate # floating point in the general case, so don't define softfp for # it at this time. arm and armeb are pure softfp, so define it # for them. . if ${MACHINE_ARCH:Marmv6*} == "" MACHINE_CPU += softfp . endif # Normally armv6 is hard float ABI from FreeBSD 11 onwards. However # when CPUTYPE has 'soft' in it, we use the soft-float ABI to allow # building of soft-float ABI libraries. In this case, we have to # add the -mfloat-abi=softfp to force that. .if ${MACHINE_ARCH:Marmv6*} && defined(CPUTYPE) && ${CPUTYPE:M*soft*} != "" # Needs to be CFLAGS not _CPUCFLAGS because it's needed for the ABI # not a nice optimization. CFLAGS += -mfloat-abi=softfp .endif .endif .if ${MACHINE_ARCH} == "powerpcspe" CFLAGS += -mcpu=8540 -Wa,-me500 -mspe=yes -mabi=spe -mfloat-gprs=double .endif .if ${MACHINE_CPUARCH} == "riscv" -CFLAGS += -msoft-float -ACFLAGS += -msoft-float +CFLAGS += -mno-float +ACFLAGS += -mno-float .endif # NB: COPTFLAGS is handled in /usr/src/sys/conf/kern.pre.mk .if !defined(NO_CPU_CFLAGS) CFLAGS += ${_CPUCFLAGS} .endif # # Prohibit the compiler from emitting SIMD instructions. # These flags are added to CFLAGS in areas where the extra context-switch # cost outweighs the advantages of SIMD instructions. # # gcc: # Setting -mno-mmx implies -mno-3dnow # Setting -mno-sse implies -mno-sse2, -mno-sse3, -mno-ssse3 and -mfpmath=387 # # clang: # Setting -mno-mmx implies -mno-3dnow and -mno-3dnowa # Setting -mno-sse implies -mno-sse2, -mno-sse3, -mno-ssse3, -mno-sse41 and # -mno-sse42 # (-mfpmath= is not supported) # .if ${MACHINE_CPUARCH} == "i386" || ${MACHINE_CPUARCH} == "amd64" CFLAGS_NO_SIMD.clang= -mno-avx CFLAGS_NO_SIMD= -mno-mmx -mno-sse .endif CFLAGS_NO_SIMD += ${CFLAGS_NO_SIMD.${COMPILER_TYPE}} # Add in any architecture-specific CFLAGS. # These come from make.conf or the command line or the environment. CFLAGS += ${CFLAGS.${MACHINE_ARCH}} CXXFLAGS += ${CXXFLAGS.${MACHINE_ARCH}} Index: head/share/mk/bsd.stand.mk =================================================================== --- head/share/mk/bsd.stand.mk (revision 308250) +++ head/share/mk/bsd.stand.mk (revision 308251) @@ -1,24 +1,29 @@ # $FreeBSD$ # # Common definitons for programs building in the stand-alone environment # and/or using libstand. # CFLAGS+= -ffreestanding -Wformat -CFLAGS+= ${CFLAGS_NO_SIMD} -msoft-float -D_STANDALONE +CFLAGS+= ${CFLAGS_NO_SIMD} -D_STANDALONE +.if ${MACHINE_CPUARCH} == "riscv" +CFLAGS+= -mno-float +.else +CFLAGS+= -msoft-float +.endif .if ${MACHINE_CPUARCH} == "i386" CFLAGS.gcc+= -mpreferred-stack-boundary=2 .endif .if ${MACHINE_CPUARCH} == "amd64" CFLAGS+= -fPIC -mno-red-zone .endif .if ${MACHINE} == "pc98" CFLAGS+= -Os .endif .if ${MACHINE_CPUARCH} == "aarch64" CFLAGS+= -mgeneral-regs-only .endif .if ${MACHINE_CPUARCH} == "mips" CFLAGS+= -G0 -fno-pic -mno-abicalls .endif Index: head/sys/modules/dtrace/dtrace/Makefile =================================================================== --- head/sys/modules/dtrace/dtrace/Makefile (revision 308250) +++ head/sys/modules/dtrace/dtrace/Makefile (revision 308251) @@ -1,73 +1,73 @@ # $FreeBSD$ SYSDIR?= ${.CURDIR}/../../.. ARCHDIR= ${MACHINE_CPUARCH} .PATH: ${SYSDIR}/cddl/contrib/opensolaris/uts/common/dtrace .PATH: ${SYSDIR}/cddl/compat/opensolaris/kern .PATH: ${SYSDIR}/cddl/kern .PATH: ${SYSDIR}/cddl/dev/dtrace .PATH: ${SYSDIR}/cddl/dev/dtrace/${ARCHDIR} KMOD= dtrace SRCS= dtrace.c \ dtrace_asm.S \ dtrace_subr.c .if ${MACHINE_CPUARCH} == "amd64" || ${MACHINE_CPUARCH} == "i386" .PATH: ${SYSDIR}/cddl/dev/dtrace/x86 SRCS+= dis_tables.c \ instr_size.c CFLAGS+= -I${SYSDIR}/cddl/contrib/opensolaris/uts/intel \ -I${SYSDIR}/cddl/dev/dtrace/x86 .endif SRCS+= bus_if.h device_if.h vnode_if.h # Needed for dtrace_asm.S SRCS+= assym.s # These are needed for assym.s SRCS+= opt_compat.h opt_kstack_pages.h opt_nfs.h opt_hwpmc_hooks.h #This is needed for dtrace.c SRCS += opensolaris_taskq.c .if ${MACHINE_CPUARCH} == "i386" SRCS+= opt_apic.h .endif CFLAGS+= -I${SYSDIR}/cddl/compat/opensolaris \ -I${SYSDIR}/cddl/dev/dtrace \ -I${SYSDIR}/cddl/dev/dtrace/${ARCHDIR} \ -I${SYSDIR}/cddl/contrib/opensolaris/uts/common \ -I${SYSDIR}/cddl/contrib/opensolaris/common/util \ -I${SYSDIR} -DDIS_MEM CFLAGS+= -DSMP EXPORT_SYMS= dtrace_register \ dtrace_unregister \ dtrace_probe_lookup dtrace_asm.o: assym.s .if ${MACHINE_CPUARCH} == "arm" assym.o: assym.s ${AS} -meabi=5 -o assym.o assym.s .endif .if ${MACHINE_CPUARCH} == "riscv" assym.o: assym.s - ${AS} -msoft-float -o assym.o assym.s + ${AS} -mfloat-abi=soft -o assym.o assym.s .endif .include CFLAGS+= -include ${SYSDIR}/cddl/compat/opensolaris/sys/debug_compat.h CWARNFLAGS+= -Wno-parentheses CWARNFLAGS+= -Wno-uninitialized CWARNFLAGS+= -Wno-cast-qual CWARNFLAGS+= -Wno-unused Index: head/sys/riscv/include/asm.h =================================================================== --- head/sys/riscv/include/asm.h (revision 308250) +++ head/sys/riscv/include/asm.h (revision 308251) @@ -1,66 +1,66 @@ /*- * Copyright (c) 2015 Ruslan Bukin * All rights reserved. * * Portions of this software were developed by SRI International and the * University of Cambridge Computer Laboratory under DARPA/AFRL contract * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. * * Portions of this software were developed by the University of Cambridge * Computer Laboratory as part of the CTSRD Project, with support from the * UK Higher Education Innovation Fund (HEIF). * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _MACHINE_ASM_H_ #define _MACHINE_ASM_H_ #undef __FBSDID #if !defined(lint) && !defined(STRIP_FBSDID) #define __FBSDID(s) .ident s #else #define __FBSDID(s) /* nothing */ #endif /* not lint and not STRIP_FBSDID */ #define _C_LABEL(x) x #define ENTRY(sym) \ - .text; .globl sym; .type sym,@function; .align 2; sym: + .text; .globl sym; .type sym,@function; .align 4; sym: #define END(sym) .size sym, . - sym #define EENTRY(sym) \ .globl sym; sym: #define EEND(sym) #define WEAK_REFERENCE(sym, alias) \ .weak alias; \ .set alias,sym #define SET_FAULT_HANDLER(handler, tmp) \ ld tmp, PC_CURTHREAD(gp); \ ld tmp, TD_PCB(tmp); /* Load the pcb */ \ sd handler, PCB_ONFAULT(tmp) /* Set the handler */ #endif /* _MACHINE_ASM_H_ */ Index: head/sys/riscv/include/float.h =================================================================== --- head/sys/riscv/include/float.h (revision 308250) +++ head/sys/riscv/include/float.h (revision 308251) @@ -1,111 +1,94 @@ /*- * Copyright (c) 1989 Regents of the University of California. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)float.h 7.1 (Berkeley) 5/8/90 * $FreeBSD$ */ #ifndef _MACHINE_FLOAT_H_ #define _MACHINE_FLOAT_H_ #include __BEGIN_DECLS extern int __flt_rounds(void); __END_DECLS #define FLT_RADIX 2 /* b */ #define FLT_ROUNDS __flt_rounds() #if __ISO_C_VISIBLE >= 1999 #define FLT_EVAL_METHOD 0 #define DECIMAL_DIG 17 /* max precision in decimal digits */ #endif #define FLT_MANT_DIG 24 /* p */ #define FLT_EPSILON 1.19209290E-07F /* b**(1-p) */ #define FLT_DIG 6 /* floor((p-1)*log10(b))+(b == 10) */ #define FLT_MIN_EXP (-125) /* emin */ #define FLT_MIN 1.17549435E-38F /* b**(emin-1) */ #define FLT_MIN_10_EXP (-37) /* ceil(log10(b**(emin-1))) */ #define FLT_MAX_EXP 128 /* emax */ #define FLT_MAX 3.40282347E+38F /* (1-b**(-p))*b**emax */ #define FLT_MAX_10_EXP 38 /* floor(log10((1-b**(-p))*b**emax)) */ #if __ISO_C_VISIBLE >= 2011 #define FLT_TRUE_MIN 1.40129846E-45F /* b**(emin-p) */ #define FLT_DECIMAL_DIG 9 /* ceil(1+p*log10(b)) */ #define FLT_HAS_SUBNORM 1 #endif /* __ISO_C_VISIBLE >= 2011 */ #define DBL_MANT_DIG 53 #define DBL_EPSILON 2.2204460492503131E-16 #define DBL_DIG 15 #define DBL_MIN_EXP (-1021) #define DBL_MIN 2.2250738585072014E-308 #define DBL_MIN_10_EXP (-307) #define DBL_MAX_EXP 1024 #define DBL_MAX 1.7976931348623157E+308 #define DBL_MAX_10_EXP 308 #if __ISO_C_VISIBLE >= 2011 #define DBL_TRUE_MIN 4.9406564584124654E-324 #define DBL_DECIMAL_DIG 17 #define DBL_HAS_SUBNORM 1 #endif /* __ISO_C_VISIBLE >= 2011 */ -#define LDBL_MANT_DIG DBL_MANT_DIG -#define LDBL_EPSILON ((long double)DBL_EPSILON) -#define LDBL_DIG DBL_DIG -#define LDBL_MIN_EXP DBL_MIN_EXP -#define LDBL_MIN ((long double)DBL_MIN) -#define LDBL_MIN_10_EXP DBL_MIN_10_EXP -#define LDBL_MAX_EXP DBL_MAX_EXP -#define LDBL_MAX ((long double)DBL_MAX) -#define LDBL_MAX_10_EXP DBL_MAX_10_EXP -#if __ISO_C_VISIBLE >= 2011 -#define LDBL_TRUE_MIN ((long double)DBL_TRUE_MIN) -#define LDBL_DECIMAL_DIG DBL_DECIMAL_DIG -#define LDBL_HAS_SUBNORM DBL_HAS_SUBNORM -#endif /* __ISO_C_VISIBLE >= 2011 */ - -#if 0 /* RISCVTODO */ #define LDBL_MANT_DIG 113 #define LDBL_EPSILON 1.925929944387235853055977942584927319E-34L #define LDBL_DIG 33 #define LDBL_MIN_EXP (-16381) #define LDBL_MIN 3.362103143112093506262677817321752603E-4932L #define LDBL_MIN_10_EXP (-4931) #define LDBL_MAX_EXP (+16384) #define LDBL_MAX 1.189731495357231765085759326628007016E+4932L #define LDBL_MAX_10_EXP (+4932) #if __ISO_C_VISIBLE >= 2011 #define LDBL_TRUE_MIN 6.475175119438025110924438958227646552E-4966L #define LDBL_DECIMAL_DIG 36 #define LDBL_HAS_SUBNORM 1 #endif /* __ISO_C_VISIBLE >= 2011 */ -#endif #endif /* _MACHINE_FLOAT_H_ */