Index: head/sys/arm/arm/cpufunc_asm_arm11.S =================================================================== --- head/sys/arm/arm/cpufunc_asm_arm11.S (revision 306644) +++ head/sys/arm/arm/cpufunc_asm_arm11.S (revision 306645) @@ -1,102 +1,46 @@ /* $NetBSD: cpufunc_asm_arm11.S,v 1.2 2005/12/11 12:16:41 christos Exp $ */ /* * Copyright (c) 2002, 2005 ARM Limited * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the company may not be used to endorse or promote * products derived from this software without specific prior written * permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * ARM11 assembly functions for CPU / MMU / TLB specific operations * * XXX We make no attempt at present to take advantage of the v6 memory * architecture or physically tagged cache. */ #include __FBSDID("$FreeBSD$"); /* - * TLB functions - */ -ENTRY(arm11_tlb_flushID_SE) - mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ - mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ - RET -END(arm11_tlb_flushID_SE) - -/* - * Context switch. - * - * These is the CPU-specific parts of the context switcher cpu_switch() - * These functions actually perform the TTB reload. - * - * NOTE: Special calling convention - * r1, r4-r13 must be preserved - */ -ENTRY(arm11_context_switch) - /* - * We can assume that the caches will only contain kernel addresses - * at this point. So no need to flush them again. - */ - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */ - mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */ - - /* Paranoia -- make sure the pipeline is empty. */ - nop - nop - nop - RET -END(arm11_context_switch) - -/* - * TLB functions - */ -ENTRY(arm11_tlb_flushID) - mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */ - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ - mov pc, lr -END(arm11_tlb_flushID) - -ENTRY(arm11_tlb_flushD) - mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */ - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ - mov pc, lr -END(arm11_tlb_flushD) - -ENTRY(arm11_tlb_flushD_SE) - mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ - mov pc, lr -END(arm11_tlb_flushD_SE) - -/* * Other functions */ ENTRY(arm11_drain_writebuf) mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ mov pc, lr END(arm11_drain_writebuf) Index: head/sys/arm/arm/cpufunc_asm_arm11x6.S =================================================================== --- head/sys/arm/arm/cpufunc_asm_arm11x6.S (revision 306644) +++ head/sys/arm/arm/cpufunc_asm_arm11x6.S (revision 306645) @@ -1,211 +1,96 @@ /* $NetBSD: cpufunc_asm_arm11x6.S,v 1.1 2012/07/21 12:19:15 skrll Exp $ */ /* * Copyright (c) 2007 Microsoft * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Microsoft * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation * by Eben Upton * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); .cpu arm1176jz-s -#if 0 -#define Invalidate_I_cache(Rtmp1, Rtmp2) \ - mcr p15, 0, Rtmp1, c7, c5, 0 /* Invalidate Entire I cache */ -#else -/* - * Workaround for - * - * Erratum 411920 in ARM1136 (fixed in r1p4) - * Erratum 415045 in ARM1176 (fixed in r0p5?) - * - * - value of arg 'reg' Should Be Zero - */ -#define Invalidate_I_cache(Rtmp1, Rtmp2) \ - mov Rtmp1, #0; /* SBZ */ \ - mrs Rtmp2, cpsr; \ - cpsid ifa; \ - mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \ - mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \ - mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \ - mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \ - msr cpsr_cx, Rtmp2; \ - nop; \ - nop; \ - nop; \ - nop; \ - nop; \ - nop; \ - nop; \ - nop; \ - nop; \ - nop; \ - nop; -#endif - -#if 1 -#define Flush_D_cache(reg) \ - mov reg, #0; /* SBZ */ \ - mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \ - mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */ -#else -#define Flush_D_cache(reg) \ -1: mov reg, #0; /* SBZ */ \ - mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \ - mrc p15, 0, reg, C7, C10, 6;/* Read Cache Dirty Status Register */ \ - ands reg, reg, #01; /* Check if it is clean */ \ - bne 1b; /* loop if not */ \ - mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */ -#endif - ENTRY(arm11x6_setttb) mov r1, #0 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLBs */ mcr p15, 0, r1, c7, c10, 4 /* drain write buffer */ RET END(arm11x6_setttb) -ENTRY_NP(arm11x6_idcache_wbinv_all) - Flush_D_cache(r0) - Invalidate_I_cache(r0, r1) - RET -END(arm11x6_idcache_wbinv_all) - -ENTRY_NP(arm11x6_dcache_wbinv_all) - Flush_D_cache(r0) - RET -END(arm11x6_dcache_wbinv_all) - -ENTRY_NP(arm11x6_icache_sync_range) - add r1, r1, r0 - sub r1, r1, #1 - /* Erratum ARM1136 371025, workaround #2 */ - /* Erratum ARM1176 371367 */ - mrs r2, cpsr /* save the CPSR */ - cpsid ifa /* disable interrupts (irq,fiq,abort) */ - mov r3, #0 - mcr p15, 0, r3, c13, c0, 0 /* write FCSE (uTLB invalidate) */ - mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */ - add r3, pc, #0x24 - mcr p15, 0, r3, c7, c13, 1 /* prefetch I-cache line */ - mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range */ - msr cpsr_cx, r2 /* local_irq_restore */ - nop - nop - nop - nop - nop - nop - nop - - mcrr p15, 0, r1, r0, c12 /* clean and invalidate D cache range */ /* XXXNH */ - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(arm11x6_icache_sync_range) - -ENTRY_NP(arm11x6_idcache_wbinv_range) - add r1, r1, r0 - sub r1, r1, #1 - /* Erratum ARM1136 371025, workaround #2 */ - /* Erratum ARM1176 371367 */ - mrs r2, cpsr /* save the CPSR */ - cpsid ifa /* disable interrupts (irq,fiq,abort) */ - mov r3, #0 - mcr p15, 0, r3, c13, c0, 0 /* write FCSE (uTLB invalidate) */ - mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */ - add r3, pc, #0x24 - mcr p15, 0, r3, c7, c13, 1 /* prefetch I-cache line */ - mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range */ - msr cpsr_cx, r2 /* local_irq_restore */ - nop - nop - nop - nop - nop - nop - nop - - mcrr p15, 0, r1, r0, c14 /* clean and invalidate D cache range */ - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(arm11x6_idcache_wbinv_range) - /* * Preload the cache before issuing the WFI by conditionally disabling the * mcr intstructions the first time around the loop. Ensure the function is * cacheline aligned. */ .arch armv6 .p2align 5 ENTRY_NP(arm11x6_sleep) mov r0, #0 mov r1, #2 1: subs r1, #1 nop mcreq p15, 0, r0, c7, c10, 4 /* data sync barrier */ mcreq p15, 0, r0, c7, c0, 4 /* wait for interrupt */ nop nop nop bne 1b RET END(arm11x6_sleep) - Index: head/sys/arm/arm/cpufunc_asm_armv6.S =================================================================== --- head/sys/arm/arm/cpufunc_asm_armv6.S (revision 306644) +++ head/sys/arm/arm/cpufunc_asm_armv6.S (revision 306645) @@ -1,116 +1,64 @@ /* $NetBSD: cpufunc_asm_armv6.S,v 1.4 2010/12/10 02:06:22 bsh Exp $ */ /* * Copyright (c) 2002, 2005 ARM Limited * Portions Copyright (c) 2007 Microsoft * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the company may not be used to endorse or promote * products derived from this software without specific prior written * permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * ARMv6 assembly functions for manipulating caches. * These routines can be used by any core that supports the mcrr address * range operations. */ /* * $FreeBSD$ */ #include .arch armv6 /* - * Functions to set the MMU Translation Table Base register - * - * We need to clean and flush the cache as it uses virtual - * addresses that are about to change. - */ -ENTRY(armv6_setttb) - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - - mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ - - mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ - RET -END(armv6_setttb) - -/* * Cache operations. */ -/* LINTSTUB: void armv6_dcache_wb_range(vaddr_t, vsize_t); */ -ENTRY(armv6_dcache_wb_range) - add r1, r1, r0 - sub r1, r1, #1 - mcrr p15, 0, r1, r0, c12 /* clean D cache range */ - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(armv6_dcache_wb_range) - -/* LINTSTUB: void armv6_dcache_wbinv_range(vaddr_t, vsize_t); */ -ENTRY(armv6_dcache_wbinv_range) - add r1, r1, r0 - sub r1, r1, #1 - mcrr p15, 0, r1, r0, c14 /* clean and invaliate D cache range */ - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(armv6_dcache_wbinv_range) - -/* - * Note, we must not invalidate everything. If the range is too big we - * must use wb-inv of the entire cache. - * - * LINTSTUB: void armv6_dcache_inv_range(vaddr_t, vsize_t); - */ -ENTRY(armv6_dcache_inv_range) - add r1, r1, r0 - sub r1, r1, #1 - mcrr p15, 0, r1, r0, c6 /* invaliate D cache range */ - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(armv6_dcache_inv_range) - +#ifdef ELF_TRAMPOLINE /* LINTSTUB: void armv6_idcache_wbinv_all(void); */ ENTRY_NP(armv6_idcache_wbinv_all) /* * We assume that the code here can never be out of sync with the * dcache, so that we can safely flush the Icache and fall through * into the Dcache purging code. */ mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ /* Purge Dcache. */ mcr p15, 0, r0, c7, c14, 0 /* clean & invalidate D cache */ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ RET END(armv6_idcache_wbinv_all) - -ENTRY(armv6_idcache_inv_all) - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* invalidate all I+D cache */ - RET -END(armv6_idcache_inv_all) - +#endif /* ELF_TRAMPOLINE */ Index: head/sys/arm/arm/cpufunc_asm_armv7.S =================================================================== --- head/sys/arm/arm/cpufunc_asm_armv7.S (revision 306644) +++ head/sys/arm/arm/cpufunc_asm_armv7.S (revision 306645) @@ -1,358 +1,174 @@ /*- * Copyright (c) 2010 Per Odlund * Copyright (C) 2011 MARVELL INTERNATIONAL LTD. * All rights reserved. * * Developed by Semihalf. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of MARVELL nor the names of contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include .cpu cortex-a8 .Lcoherency_level: .word _C_LABEL(arm_cache_loc) .Lcache_type: .word _C_LABEL(arm_cache_type) .Larmv7_dcache_line_size: .word _C_LABEL(arm_dcache_min_line_size) .Larmv7_icache_line_size: .word _C_LABEL(arm_icache_min_line_size) .Larmv7_idcache_line_size: .word _C_LABEL(arm_idcache_min_line_size) .Lway_mask: .word 0x3ff .Lmax_index: .word 0x7fff .Lpage_mask: .word 0xfff #define PT_NOS (1 << 5) #define PT_S (1 << 1) #define PT_INNER_NC 0 #define PT_INNER_WT (1 << 0) #define PT_INNER_WB ((1 << 0) | (1 << 6)) #define PT_INNER_WBWA (1 << 6) #define PT_OUTER_NC 0 #define PT_OUTER_WT (2 << 3) #define PT_OUTER_WB (3 << 3) #define PT_OUTER_WBWA (1 << 3) #ifdef SMP #define PT_ATTR (PT_S|PT_INNER_WBWA|PT_OUTER_WBWA|PT_NOS) #else #define PT_ATTR (PT_INNER_WBWA|PT_OUTER_WBWA) #endif ENTRY(armv7_setttb) dsb orr r0, r0, #PT_ATTR mcr CP15_TTBR0(r0) isb #ifdef SMP mcr CP15_TLBIALLIS #else mcr CP15_TLBIALL #endif dsb isb RET END(armv7_setttb) -ENTRY(armv7_tlb_flushID) - dsb -#ifdef SMP - mcr CP15_TLBIALLIS - mcr CP15_BPIALLIS -#else - mcr CP15_TLBIALL - mcr CP15_BPIALL -#endif - dsb - isb - mov pc, lr -END(armv7_tlb_flushID) - -ENTRY(armv7_tlb_flushID_SE) - ldr r1, .Lpage_mask - bic r0, r0, r1 -#ifdef SMP - mcr CP15_TLBIMVAAIS(r0) - mcr CP15_BPIALLIS -#else - mcr CP15_TLBIMVA(r0) - mcr CP15_BPIALL -#endif - dsb - isb - mov pc, lr -END(armv7_tlb_flushID_SE) - +#ifdef ELF_TRAMPOLINE /* Based on algorithm from ARM Architecture Reference Manual */ ENTRY(armv7_dcache_wbinv_all) stmdb sp!, {r4, r5, r6, r7, r8, r9} /* Get cache level */ ldr r0, .Lcoherency_level ldr r3, [r0] cmp r3, #0 beq Finished /* For each cache level */ mov r8, #0 Loop1: /* Get cache type for given level */ mov r2, r8, lsl #2 add r2, r2, r2 ldr r0, .Lcache_type ldr r1, [r0, r2] /* Get line size */ and r2, r1, #7 add r2, r2, #4 /* Get number of ways */ ldr r4, .Lway_mask ands r4, r4, r1, lsr #3 clz r5, r4 /* Get max index */ ldr r7, .Lmax_index ands r7, r7, r1, lsr #13 Loop2: mov r9, r4 Loop3: mov r6, r8, lsl #1 orr r6, r6, r9, lsl r5 orr r6, r6, r7, lsl r2 /* Clean and invalidate data cache by way/index */ mcr CP15_DCCISW(r6) subs r9, r9, #1 bge Loop3 subs r7, r7, #1 bge Loop2 Skip: add r8, r8, #1 cmp r3, r8 bne Loop1 Finished: dsb ldmia sp!, {r4, r5, r6, r7, r8, r9} RET END(armv7_dcache_wbinv_all) ENTRY(armv7_idcache_wbinv_all) stmdb sp!, {lr} bl armv7_dcache_wbinv_all #ifdef SMP mcr CP15_ICIALLUIS #else mcr CP15_ICIALLU #endif dsb isb ldmia sp!, {lr} RET END(armv7_idcache_wbinv_all) +#endif -ENTRY(armv7_dcache_wb_range) - ldr ip, .Larmv7_dcache_line_size - ldr ip, [ip] - sub r3, ip, #1 - and r2, r0, r3 - add r1, r1, r2 - bic r0, r0, r3 -.Larmv7_wb_next: - mcr CP15_DCCMVAC(r0) - add r0, r0, ip - subs r1, r1, ip - bhi .Larmv7_wb_next - dsb /* data synchronization barrier */ - RET -END(armv7_dcache_wb_range) - -ENTRY(armv7_dcache_wbinv_range) - ldr ip, .Larmv7_dcache_line_size - ldr ip, [ip] - sub r3, ip, #1 - and r2, r0, r3 - add r1, r1, r2 - bic r0, r0, r3 -.Larmv7_wbinv_next: - mcr CP15_DCCIMVAC(r0) - add r0, r0, ip - subs r1, r1, ip - bhi .Larmv7_wbinv_next - dsb /* data synchronization barrier */ - RET -END(armv7_dcache_wbinv_range) - -/* - * Note, we must not invalidate everything. If the range is too big we - * must use wb-inv of the entire cache. - */ -ENTRY(armv7_dcache_inv_range) - ldr ip, .Larmv7_dcache_line_size - ldr ip, [ip] - sub r3, ip, #1 - and r2, r0, r3 - add r1, r1, r2 - bic r0, r0, r3 -.Larmv7_inv_next: - mcr CP15_DCIMVAC(r0) - add r0, r0, ip - subs r1, r1, ip - bhi .Larmv7_inv_next - dsb /* data synchronization barrier */ - RET -END(armv7_dcache_inv_range) - -ENTRY(armv7_idcache_wbinv_range) - ldr ip, .Larmv7_idcache_line_size - ldr ip, [ip] - sub r3, ip, #1 - and r2, r0, r3 - add r1, r1, r2 - bic r0, r0, r3 -.Larmv7_id_wbinv_next: - mcr CP15_ICIMVAU(r0) - mcr CP15_DCCIMVAC(r0) - add r0, r0, ip - subs r1, r1, ip - bhi .Larmv7_id_wbinv_next - dsb /* data synchronization barrier */ - isb /* instruction synchronization barrier */ - RET -END(armv7_idcache_wbinv_range) - - -ENTRY_NP(armv7_icache_sync_range) - ldr ip, .Larmv7_icache_line_size - ldr ip, [ip] - sub r3, ip, #1 /* Address need not be aligned, but */ - and r2, r0, r3 /* round length up if op spans line */ - add r1, r1, r2 /* boundary: len += addr & linemask; */ -.Larmv7_sync_next: - mcr CP15_DCCMVAC(r0) - mcr CP15_ICIMVAU(r0) - add r0, r0, ip - subs r1, r1, ip - bhi .Larmv7_sync_next - dsb /* data synchronization barrier */ - isb /* instruction synchronization barrier */ - RET -END(armv7_icache_sync_range) - ENTRY(armv7_cpu_sleep) dsb /* data synchronization barrier */ wfi /* wait for interrupt */ RET END(armv7_cpu_sleep) -ENTRY(armv7_context_switch) - dsb - orr r0, r0, #PT_ATTR - - mcr CP15_TTBR0(r0) - isb -#ifdef SMP - mcr CP15_TLBIALLIS -#else - mcr CP15_TLBIALL -#endif - dsb - isb - RET -END(armv7_context_switch) - ENTRY(armv7_drain_writebuf) dsb RET END(armv7_drain_writebuf) ENTRY(armv7_sev) dsb sev nop RET END(armv7_sev) - -ENTRY(armv7_auxctrl) - mrc CP15_ACTLR(r2) - bic r3, r2, r0 /* Clear bits */ - eor r3, r3, r1 /* XOR bits */ - - teq r2, r3 - mcrne CP15_ACTLR(r3) - mov r0, r2 - RET -END(armv7_auxctrl) - -/* - * Invalidate all I+D+branch cache. Used by startup code, which counts - * on the fact that only r0-r3,ip are modified and no stack space is used. - */ -ENTRY(armv7_idcache_inv_all) - mov r0, #0 - mcr CP15_CSSELR(r0) @ set cache level to L1 - mrc CP15_CCSIDR(r0) - - ubfx r2, r0, #13, #15 @ get num sets - 1 from CCSIDR - ubfx r3, r0, #3, #10 @ get numways - 1 from CCSIDR - clz r1, r3 @ number of bits to MSB of way - lsl r3, r3, r1 @ shift into position - mov ip, #1 @ - lsl ip, ip, r1 @ ip now contains the way decr - - ubfx r0, r0, #0, #3 @ get linesize from CCSIDR - add r0, r0, #4 @ apply bias - lsl r2, r2, r0 @ shift sets by log2(linesize) - add r3, r3, r2 @ merge numsets - 1 with numways - 1 - sub ip, ip, r2 @ subtract numsets - 1 from way decr - mov r1, #1 - lsl r1, r1, r0 @ r1 now contains the set decr - mov r2, ip @ r2 now contains set way decr - - /* r3 = ways/sets, r2 = way decr, r1 = set decr, r0 and ip are free */ -1: mcr CP15_DCISW(r3) @ invalidate line - movs r0, r3 @ get current way/set - beq 2f @ at 0 means we are done. - movs r0, r0, lsl #10 @ clear way bits leaving only set bits - subne r3, r3, r1 @ non-zero?, decrement set # - subeq r3, r3, r2 @ zero?, decrement way # and restore set count - b 1b - -2: dsb @ wait for stores to finish - mov r0, #0 @ and ... - mcr CP15_ICIALLU @ invalidate instruction+branch cache - isb @ instruction sync barrier - bx lr @ return -END(armv7_idcache_inv_all) - Index: head/sys/arm/include/cpufunc.h =================================================================== --- head/sys/arm/include/cpufunc.h (revision 306644) +++ head/sys/arm/include/cpufunc.h (revision 306645) @@ -1,534 +1,506 @@ /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ /*- * Copyright (c) 1997 Mark Brinicombe. * Copyright (c) 1997 Causality Limited * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Causality Limited. * 4. The name of Causality Limited may not be used to endorse or promote * products derived from this software without specific prior written * permission. * * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * RiscBSD kernel project * * cpufunc.h * * Prototypes for cpu, mmu and tlb related functions. * * $FreeBSD$ */ #ifndef _MACHINE_CPUFUNC_H_ #define _MACHINE_CPUFUNC_H_ #ifdef _KERNEL #include #include #include static __inline void breakpoint(void) { __asm(".word 0xe7ffffff"); } struct cpu_functions { /* CPU functions */ #if __ARM_ARCH < 6 void (*cf_cpwait) (void); #endif /* MMU functions */ u_int (*cf_control) (u_int bic, u_int eor); void (*cf_setttb) (u_int ttb); #if __ARM_ARCH < 6 /* TLB functions */ void (*cf_tlb_flushID) (void); void (*cf_tlb_flushID_SE) (u_int va); void (*cf_tlb_flushD) (void); void (*cf_tlb_flushD_SE) (u_int va); /* * Cache operations: * * We define the following primitives: * * icache_sync_range Synchronize I-cache range * * dcache_wbinv_all Write-back and Invalidate D-cache * dcache_wbinv_range Write-back and Invalidate D-cache range * dcache_inv_range Invalidate D-cache range * dcache_wb_range Write-back D-cache range * * idcache_wbinv_all Write-back and Invalidate D-cache, * Invalidate I-cache * idcache_wbinv_range Write-back and Invalidate D-cache, * Invalidate I-cache range * * Note that the ARM term for "write-back" is "clean". We use * the term "write-back" since it's a more common way to describe * the operation. * * There are some rules that must be followed: * * ID-cache Invalidate All: * Unlike other functions, this one must never write back. * It is used to intialize the MMU when it is in an unknown * state (such as when it may have lines tagged as valid * that belong to a previous set of mappings). * * I-cache Sync range: * The goal is to synchronize the instruction stream, * so you may beed to write-back dirty D-cache blocks * first. If a range is requested, and you can't * synchronize just a range, you have to hit the whole * thing. * * D-cache Write-Back and Invalidate range: * If you can't WB-Inv a range, you must WB-Inv the * entire D-cache. * * D-cache Invalidate: * If you can't Inv the D-cache, you must Write-Back * and Invalidate. Code that uses this operation * MUST NOT assume that the D-cache will not be written * back to memory. * * D-cache Write-Back: * If you can't Write-back without doing an Inv, * that's fine. Then treat this as a WB-Inv. * Skipping the invalidate is merely an optimization. * * All operations: * Valid virtual addresses must be passed to each * cache operation. */ void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); void (*cf_dcache_wbinv_all) (void); void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); void (*cf_idcache_inv_all) (void); void (*cf_idcache_wbinv_all) (void); void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); #endif void (*cf_l2cache_wbinv_all) (void); void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); void (*cf_l2cache_drain_writebuf) (void); /* Other functions */ void (*cf_drain_writebuf) (void); void (*cf_sleep) (int mode); #if __ARM_ARCH < 6 /* Soft functions */ void (*cf_context_switch) (void); #endif void (*cf_setup) (void); }; extern struct cpu_functions cpufuncs; extern u_int cputype; #if __ARM_ARCH < 6 #define cpu_cpwait() cpufuncs.cf_cpwait() #endif #define cpu_control(c, e) cpufuncs.cf_control(c, e) #if __ARM_ARCH < 6 #define cpu_setttb(t) cpufuncs.cf_setttb(t) #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) #define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all() #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) #endif #define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() #define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) #define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) #define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) #define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf() #if __ARM_ARCH < 6 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() #endif #define cpu_sleep(m) cpufuncs.cf_sleep(m) #define cpu_setup() cpufuncs.cf_setup() int set_cpufuncs (void); #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ void cpufunc_nullop (void); u_int cpu_ident (void); u_int cpufunc_control (u_int clear, u_int bic); void cpu_domains (u_int domains); u_int cpu_faultstatus (void); u_int cpu_faultaddress (void); u_int cpu_get_control (void); u_int cpu_pfr (int); #if defined(CPU_FA526) void fa526_setup (void); void fa526_setttb (u_int ttb); void fa526_context_switch (void); void fa526_cpu_sleep (int); void fa526_tlb_flushID_SE (u_int); void fa526_icache_sync_range(vm_offset_t start, vm_size_t end); void fa526_dcache_wbinv_all (void); void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end); void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end); void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end); void fa526_idcache_wbinv_all(void); void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end); #endif #if defined(CPU_ARM9) || defined(CPU_ARM9E) void arm9_setttb (u_int); void arm9_tlb_flushID_SE (u_int va); void arm9_context_switch (void); #endif #if defined(CPU_ARM9) void arm9_icache_sync_range (vm_offset_t, vm_size_t); void arm9_dcache_wbinv_all (void); void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t); void arm9_dcache_inv_range (vm_offset_t, vm_size_t); void arm9_dcache_wb_range (vm_offset_t, vm_size_t); void arm9_idcache_wbinv_all (void); void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t); void arm9_setup (void); extern unsigned arm9_dcache_sets_max; extern unsigned arm9_dcache_sets_inc; extern unsigned arm9_dcache_index_max; extern unsigned arm9_dcache_index_inc; #endif #if defined(CPU_ARM9E) void arm10_setup (void); u_int sheeva_control_ext (u_int, u_int); void sheeva_cpu_sleep (int); void sheeva_setttb (u_int); void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t); void sheeva_dcache_inv_range (vm_offset_t, vm_size_t); void sheeva_dcache_wb_range (vm_offset_t, vm_size_t); void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t); void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t); void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t); void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); void sheeva_l2cache_wbinv_all (void); #endif #if defined(CPU_MV_PJ4B) void armv6_idcache_wbinv_all (void); #endif #if defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT) void armv7_setttb (u_int); -void armv7_tlb_flushID (void); -void armv7_tlb_flushID_SE (u_int); -void armv7_icache_sync_range (vm_offset_t, vm_size_t); -void armv7_idcache_wbinv_range (vm_offset_t, vm_size_t); -void armv7_idcache_inv_all (void); -void armv7_dcache_wbinv_all (void); void armv7_idcache_wbinv_all (void); -void armv7_dcache_wbinv_range (vm_offset_t, vm_size_t); -void armv7_dcache_inv_range (vm_offset_t, vm_size_t); -void armv7_dcache_wb_range (vm_offset_t, vm_size_t); void armv7_cpu_sleep (int); void armv7_setup (void); -void armv7_context_switch (void); void armv7_drain_writebuf (void); void armv7_sev (void); -u_int armv7_auxctrl (u_int, u_int); void armadaxp_idcache_wbinv_all (void); void cortexa_setup (void); #endif #if defined(CPU_MV_PJ4B) void pj4b_config (void); void pj4bv7_setup (void); #endif #if defined(CPU_ARM1176) -void arm11_tlb_flushID (void); -void arm11_tlb_flushID_SE (u_int); -void arm11_tlb_flushD (void); -void arm11_tlb_flushD_SE (u_int va); - -void arm11_context_switch (void); - void arm11_drain_writebuf (void); -void armv6_dcache_wbinv_range (vm_offset_t, vm_size_t); -void armv6_dcache_inv_range (vm_offset_t, vm_size_t); -void armv6_dcache_wb_range (vm_offset_t, vm_size_t); - -void armv6_idcache_inv_all (void); - void arm11x6_setttb (u_int); -void arm11x6_idcache_wbinv_all (void); -void arm11x6_dcache_wbinv_all (void); -void arm11x6_icache_sync_range (vm_offset_t, vm_size_t); -void arm11x6_idcache_wbinv_range (vm_offset_t, vm_size_t); void arm11x6_setup (void); void arm11x6_sleep (int); /* no ref. for errata */ #endif #if defined(CPU_ARM9E) void armv5_ec_setttb(u_int); void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t); void armv5_ec_dcache_wbinv_all(void); void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t); void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t); void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t); void armv5_ec_idcache_wbinv_all(void); void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); #endif #if defined(CPU_ARM9) || defined(CPU_ARM9E) || \ defined(CPU_FA526) || \ defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ defined(CPU_XSCALE_81342) void armv4_tlb_flushID (void); void armv4_tlb_flushD (void); void armv4_tlb_flushD_SE (u_int va); void armv4_drain_writebuf (void); void armv4_idcache_inv_all (void); #endif #if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ defined(CPU_XSCALE_81342) void xscale_cpwait (void); void xscale_cpu_sleep (int mode); u_int xscale_control (u_int clear, u_int bic); void xscale_setttb (u_int ttb); void xscale_tlb_flushID_SE (u_int va); void xscale_cache_flushID (void); void xscale_cache_flushI (void); void xscale_cache_flushD (void); void xscale_cache_flushD_SE (u_int entry); void xscale_cache_cleanID (void); void xscale_cache_cleanD (void); void xscale_cache_cleanD_E (u_int entry); void xscale_cache_clean_minidata (void); void xscale_cache_purgeID (void); void xscale_cache_purgeID_E (u_int entry); void xscale_cache_purgeD (void); void xscale_cache_purgeD_E (u_int entry); void xscale_cache_syncI (void); void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end); void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end); void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end); void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end); void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end); void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end); void xscale_context_switch (void); void xscale_setup (void); #endif /* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ #ifdef CPU_XSCALE_81342 void xscalec3_l2cache_purge (void); void xscalec3_cache_purgeID (void); void xscalec3_cache_purgeD (void); void xscalec3_cache_cleanID (void); void xscalec3_cache_cleanD (void); void xscalec3_cache_syncI (void); void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end); void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end); void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end); void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end); void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end); void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t); void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end); void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end); void xscalec3_setttb (u_int ttb); void xscalec3_context_switch (void); #endif /* CPU_XSCALE_81342 */ /* * Macros for manipulating CPU interrupts */ #if __ARM_ARCH < 6 #define __ARM_INTR_BITS (PSR_I | PSR_F) #else #define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A) #endif static __inline uint32_t __set_cpsr(uint32_t bic, uint32_t eor) { uint32_t tmp, ret; __asm __volatile( "mrs %0, cpsr\n" /* Get the CPSR */ "bic %1, %0, %2\n" /* Clear bits */ "eor %1, %1, %3\n" /* XOR bits */ "msr cpsr_xc, %1\n" /* Set the CPSR */ : "=&r" (ret), "=&r" (tmp) : "r" (bic), "r" (eor) : "memory"); return ret; } static __inline uint32_t disable_interrupts(uint32_t mask) { return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS)); } static __inline uint32_t enable_interrupts(uint32_t mask) { return (__set_cpsr(mask & __ARM_INTR_BITS, 0)); } static __inline uint32_t restore_interrupts(uint32_t old_cpsr) { return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS)); } static __inline register_t intr_disable(void) { return (disable_interrupts(PSR_I | PSR_F)); } static __inline void intr_restore(register_t s) { restore_interrupts(s); } #undef __ARM_INTR_BITS /* * Functions to manipulate cpu r13 * (in arm/arm32/setstack.S) */ void set_stackptr (u_int mode, u_int address); u_int get_stackptr (u_int mode); /* * Miscellany */ int get_pc_str_offset (void); /* * CPU functions from locore.S */ void cpu_reset (void) __attribute__((__noreturn__)); /* * Cache info variables. */ /* PRIMARY CACHE VARIABLES */ extern int arm_picache_size; extern int arm_picache_line_size; extern int arm_picache_ways; extern int arm_pdcache_size; /* and unified */ extern int arm_pdcache_line_size; extern int arm_pdcache_ways; extern int arm_pcache_type; extern int arm_pcache_unified; extern int arm_dcache_align; extern int arm_dcache_align_mask; extern u_int arm_cache_level; extern u_int arm_cache_loc; extern u_int arm_cache_type[14]; #endif /* _KERNEL */ #endif /* _MACHINE_CPUFUNC_H_ */ /* End of cpufunc.h */ Index: head/sys/conf/Makefile.arm =================================================================== --- head/sys/conf/Makefile.arm (revision 306644) +++ head/sys/conf/Makefile.arm (revision 306645) @@ -1,167 +1,169 @@ # Makefile.arm -- with config changes. # Copyright 1990 W. Jolitz # from: @(#)Makefile.i386 7.1 5/10/91 # $FreeBSD$ # # Makefile for FreeBSD # # This makefile is constructed from a machine description: # config machineid # Most changes should be made in the machine description # /sys/arm/conf/``machineid'' # after which you should do # config machineid # Generic makefile changes should be made in # /sys/conf/Makefile.arm # after which config should be rerun for all machines. # # Which version of config(8) is required. %VERSREQ= 600013 STD8X16FONT?= iso .if !defined(S) .if exists(./@/.) S= ./@ .else S= ../../.. .endif .endif .include "$S/conf/kern.pre.mk" INCLUDES+= -I$S/contrib/libfdt -I$S/gnu/dts/include SYSTEM_LD:= ${SYSTEM_LD:$S/conf/ldscript.$M=ldscript.$M} SYSTEM_DEP:= ${SYSTEM_DEP:$S/conf/ldscript.$M=ldscript.$M} .if !defined(DEBUG) && !defined(PROFLEVEL) STRIP_FLAGS = -S .endif # We don't support gcc's thump interwork stuff, so disable it CFLAGS.gcc += -mno-thumb-interwork # We generally don't want fpu instructions in the kernel. CFLAGS.clang += -mfpu=none .if !empty(DDB_ENABLED) CFLAGS += -funwind-tables .if ${COMPILER_TYPE} == "clang" && ${COMPILER_VERSION} < 30500 # clang < 3.5.0 requires us to tell it to emit assembly with unwind information CFLAGS += -mllvm -arm-enable-ehabi .endif .endif # hack because genassym.c includes sys/bus.h which includes these. genassym.o: bus_if.h device_if.h SYSTEM_LD_ = ${LD} -Bdynamic -T ldscript.$M.noheader ${_LDFLAGS} \ -warn-common -export-dynamic -dynamic-linker /red/herring -o \ ${FULLKERNEL}.noheader -X ${SYSTEM_OBJS} vers.o SYSTEM_LD_TAIL +=;sed s/" + SIZEOF_HEADERS"// ldscript.$M\ >ldscript.$M.noheader; \ ${SYSTEM_LD_}; \ ${OBJCOPY} -S -O binary ${FULLKERNEL}.noheader \ ${KERNEL_KO}.bin; \ rm ${FULLKERNEL}.noheader FILES_CPU_FUNC = \ $S/$M/$M/cpufunc_asm_arm9.S \ $S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \ $S/$M/$M/cpufunc_asm_xscale_c3.S $S/$M/$M/cpufunc_asm_armv5_ec.S \ $S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S \ $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv6.S \ $S/$M/$M/cpufunc_asm_armv7.S .if defined(KERNPHYSADDR) KERNEL_EXTRA=trampoline KERNEL_EXTRA_INSTALL=kernel.gz.tramp trampoline: ${KERNEL_KO}.tramp ${KERNEL_KO}.tramp: ${KERNEL_KO} $S/$M/$M/inckern.S $S/$M/$M/elf_trampoline.c echo "#define KERNNAME \"${KERNEL_KO}.tmp\"" >opt_kernname.h sed s/${KERNVIRTADDR}/${KERNPHYSADDR}/ ldscript.$M > ldscript.$M.tramp sed s/" + SIZEOF_HEADERS"// ldscript.$M.tramp > \ ldscript.$M.tramp.noheader echo "#include " >tmphack.S echo "ENTRY(_start)" >>tmphack.S echo "bl _startC" >>tmphack.S ${OBJCOPY} --strip-symbol '$$d' --strip-symbol '$$a' \ -g --strip-symbol '$$t' ${FULLKERNEL} ${KERNEL_KO}.tmp eval $$(stat -s ${KERNEL_KO}.tmp) && \ echo "#define KERNSIZE $$st_size" >>opt_kernname.h ${CC} -O -nostdlib -I. -I$S \ -Xlinker -T -Xlinker ldscript.$M.tramp \ + -DELF_TRAMPOLINE \ tmphack.S \ $S/$M/$M/elf_trampoline.c \ $S/$M/$M/inckern.S \ ${FILES_CPU_FUNC} \ -o ${KERNEL_KO}.tramp ${CC} -O -nostdlib -I. -I$S \ -Xlinker -T -Xlinker ldscript.$M.tramp.noheader \ + -DELF_TRAMPOLINE \ tmphack.S \ $S/$M/$M/elf_trampoline.c \ $S/$M/$M/inckern.S \ ${FILES_CPU_FUNC} \ -o ${KERNEL_KO}.tramp.noheader ${OBJCOPY} -S -O binary ${KERNEL_KO}.tramp.noheader \ ${KERNEL_KO}.tramp.bin ${OBJCOPY} ${STRIP_FLAGS} ${KERNEL_KO}.tmp echo "#define KERNNAME \"${KERNEL_KO}.tmp.gz\"" >opt_kernname.h eval $$(stat -s ${KERNEL_KO}.tmp) && \ echo "#define KERNSIZE $$st_size" >>opt_kernname.h gzip -f9 ${KERNEL_KO}.tmp eval $$(stat -s ${KERNEL_KO}.tmp.gz) && \ echo "#define KERNCOMPSIZE $$st_size" >>opt_kernname.h ${CC} -O2 -ffreestanding -I. -I$S -c \ - -DKZIP \ + -DKZIP -DELF_TRAMPOLINE \ $S/kern/inflate.c \ -o inflate-tramp.o ${CC} -O -nostdlib -I. -I$S \ -Xlinker -T -Xlinker ldscript.$M.tramp \ - -DKZIP \ + -DKZIP -DELF_TRAMPOLINE \ tmphack.S \ $S/$M/$M/elf_trampoline.c \ inflate-tramp.o \ $S/$M/$M/inckern.S \ ${FILES_CPU_FUNC} \ -o ${KERNEL_KO}.gz.tramp ${CC} -O -nostdlib -I. -I$S \ -Xlinker -T -Xlinker ldscript.$M.tramp.noheader \ - -DKZIP \ + -DKZIP -DELF_TRAMPOLINE \ tmphack.S \ $S/$M/$M/elf_trampoline.c \ inflate-tramp.o \ $S/$M/$M/inckern.S \ ${FILES_CPU_FUNC} \ -o ${KERNEL_KO}.tramp.noheader ${OBJCOPY} -S -O binary ${KERNEL_KO}.tramp.noheader \ ${KERNEL_KO}.gz.tramp.bin rm ${KERNEL_KO}.tmp.gz ${KERNEL_KO}.tramp.noheader opt_kernname.h \ inflate-tramp.o tmphack.S .endif %BEFORE_DEPEND %OBJS %FILES.c %FILES.s %FILES.m %CLEAN CLEAN+= ldscript.$M ${KERNEL_KO}.bin ldscript.$M.noheader CLEAN+= ${KERNEL_KO}.tramp ${KERNEL_KO}.tramp.bin ldscript.$M.tramp \ ldscript.$M.tramp.noheader ${KERNEL_KO}.gz.tramp \ ${KERNEL_KO}.gz.tramp.bin ldscript.$M: $S/conf/ldscript.$M cat $S/conf/ldscript.$M|sed s/KERNPHYSADDR/${KERNPHYSADDR}/g| \ sed s/KERNVIRTADDR/${KERNVIRTADDR}/g > ldscript.$M %RULES .include "$S/conf/kern.post.mk"