Index: head/sys/conf/files.powerpc =================================================================== --- head/sys/conf/files.powerpc (revision 306357) +++ head/sys/conf/files.powerpc (revision 306358) @@ -1,256 +1,257 @@ # This file tells config what files go into building a kernel, # files marked standard are always included. # # $FreeBSD$ # # The long compile-with and dependency lines are required because of # limitations in config: backslash-newline doesn't work in strings, and # dependency lines other than the first are silently ignored. # # font.h optional sc \ compile-with "uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x16.fnt && file2c 'u_char dflt_font_16[16*256] = {' '};' < ${SC_DFLT_FONT}-8x16 > font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x14.fnt && file2c 'u_char dflt_font_14[14*256] = {' '};' < ${SC_DFLT_FONT}-8x14 >> font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x8.fnt && file2c 'u_char dflt_font_8[8*256] = {' '};' < ${SC_DFLT_FONT}-8x8 >> font.h" \ no-obj no-implicit-rule before-depend \ clean "font.h ${SC_DFLT_FONT}-8x14 ${SC_DFLT_FONT}-8x16 ${SC_DFLT_FONT}-8x8" # # There is only an asm version on ppc64. cddl/compat/opensolaris/kern/opensolaris_atomic.c optional zfs powerpc | dtrace powerpc compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/atomic/powerpc64/opensolaris_atomic.S optional zfs powerpc64 | dtrace powerpc64 compile-with "${ZFS_S}" cddl/dev/dtrace/powerpc/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/powerpc/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/powerpc/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" crypto/blowfish/bf_enc.c optional crypto | ipsec crypto/des/des_enc.c optional crypto | ipsec | netsmb dev/bm/if_bm.c optional bm powermac dev/adb/adb_bus.c optional adb dev/adb/adb_kbd.c optional adb dev/adb/adb_mouse.c optional adb dev/adb/adb_hb_if.m optional adb dev/adb/adb_if.m optional adb dev/adb/adb_buttons.c optional adb dev/agp/agp_apple.c optional agp powermac dev/fb/fb.c optional sc dev/fdt/fdt_powerpc.c optional fdt # ofwbus depends on simplebus. dev/fdt/simplebus.c optional aim | fdt dev/hwpmc/hwpmc_e500.c optional hwpmc dev/hwpmc/hwpmc_mpc7xxx.c optional hwpmc dev/hwpmc/hwpmc_powerpc.c optional hwpmc dev/hwpmc/hwpmc_ppc970.c optional hwpmc dev/iicbus/ad7417.c optional ad7417 powermac dev/iicbus/adm1030.c optional powermac windtunnel | adm1030 powermac dev/iicbus/adt746x.c optional adt746x powermac dev/iicbus/ds1631.c optional ds1631 powermac dev/iicbus/ds1775.c optional ds1775 powermac dev/iicbus/max6690.c optional max6690 powermac dev/iicbus/ofw_iicbus.c optional iicbus aim dev/nand/nfc_fsl.c optional nand mpc85xx dev/nand/nfc_rb.c optional nand mpc85xx # ofw can be either aim or fdt: fdt case handled in files. aim only powerpc specific. dev/ofw/openfirm.c optional aim dev/ofw/openfirmio.c optional aim dev/ofw/ofw_bus_if.m optional aim dev/ofw/ofw_cpu.c optional aim dev/ofw/ofw_if.m optional aim dev/ofw/ofw_bus_subr.c optional aim dev/ofw/ofw_console.c optional aim dev/ofw/ofw_disk.c optional ofwd aim dev/ofw/ofwbus.c optional aim | fdt dev/ofw/ofwpci.c optional pci dev/ofw/ofw_standard.c optional aim powerpc dev/ofw/ofw_subr.c optional aim powerpc dev/powermac_nvram/powermac_nvram.c optional powermac_nvram powermac dev/quicc/quicc_bfe_fdt.c optional quicc mpc85xx dev/scc/scc_bfe_macio.c optional scc powermac dev/sec/sec.c optional sec mpc85xx dev/sound/macio/aoa.c optional snd_davbus | snd_ai2s powermac dev/sound/macio/davbus.c optional snd_davbus powermac dev/sound/macio/i2s.c optional snd_ai2s powermac dev/sound/macio/onyx.c optional snd_ai2s iicbus powermac dev/sound/macio/snapper.c optional snd_ai2s iicbus powermac dev/sound/macio/tumbler.c optional snd_ai2s iicbus powermac dev/syscons/scgfbrndr.c optional sc dev/syscons/scterm-teken.c optional sc dev/syscons/scvtb.c optional sc dev/tsec/if_tsec.c optional tsec dev/tsec/if_tsec_fdt.c optional tsec fdt dev/uart/uart_cpu_powerpc.c optional uart dev/usb/controller/ehci_fsl.c optional ehci mpc85xx dev/vt/hw/ofwfb/ofwfb.c optional vt aim kern/kern_clocksource.c standard kern/subr_dummy_vdso_tc.c standard kern/syscalls.c optional ktr kern/subr_sfbuf.c standard libkern/ashldi3.c optional powerpc libkern/ashrdi3.c optional powerpc libkern/bcmp.c standard libkern/cmpdi2.c optional powerpc libkern/divdi3.c optional powerpc libkern/ffs.c standard libkern/ffsl.c standard libkern/ffsll.c standard libkern/fls.c standard libkern/flsl.c standard libkern/flsll.c standard libkern/lshrdi3.c optional powerpc libkern/memmove.c standard libkern/memset.c standard libkern/moddi3.c optional powerpc libkern/qdivrem.c optional powerpc libkern/ucmpdi2.c optional powerpc libkern/udivdi3.c optional powerpc libkern/umoddi3.c optional powerpc powerpc/aim/locore.S optional aim no-obj powerpc/aim/aim_machdep.c optional aim powerpc/aim/mmu_oea.c optional aim powerpc powerpc/aim/mmu_oea64.c optional aim powerpc/aim/moea64_if.m optional aim powerpc/aim/moea64_native.c optional aim powerpc/aim/mp_cpudep.c optional aim powerpc/aim/slb.c optional aim powerpc64 powerpc/booke/locore.S optional booke no-obj powerpc/booke/booke_machdep.c optional booke powerpc/booke/machdep_e500.c optional booke_e500 powerpc/booke/mp_cpudep.c optional booke smp powerpc/booke/platform_bare.c optional booke powerpc/booke/pmap.c optional booke powerpc/cpufreq/dfs.c optional cpufreq powerpc/cpufreq/pcr.c optional cpufreq aim powerpc/cpufreq/pmufreq.c optional cpufreq aim pmu powerpc/fpu/fpu_add.c optional fpu_emu powerpc/fpu/fpu_compare.c optional fpu_emu powerpc/fpu/fpu_div.c optional fpu_emu powerpc/fpu/fpu_emu.c optional fpu_emu powerpc/fpu/fpu_explode.c optional fpu_emu powerpc/fpu/fpu_implode.c optional fpu_emu powerpc/fpu/fpu_mul.c optional fpu_emu powerpc/fpu/fpu_sqrt.c optional fpu_emu powerpc/fpu/fpu_subr.c optional fpu_emu powerpc/mambo/mambocall.S optional mambo powerpc/mambo/mambo.c optional mambo powerpc/mambo/mambo_console.c optional mambo powerpc/mambo/mambo_disk.c optional mambo powerpc/mikrotik/platform_rb.c optional mikrotik powerpc/mpc85xx/atpic.c optional mpc85xx isa powerpc/mpc85xx/ds1553_bus_fdt.c optional ds1553 fdt powerpc/mpc85xx/ds1553_core.c optional ds1553 +powerpc/mpc85xx/fsl_diu.c optional mpc85xx diu powerpc/mpc85xx/fsl_sdhc.c optional mpc85xx sdhc powerpc/mpc85xx/i2c.c optional iicbus fdt powerpc/mpc85xx/isa.c optional mpc85xx isa powerpc/mpc85xx/lbc.c optional mpc85xx powerpc/mpc85xx/mpc85xx.c optional mpc85xx powerpc/mpc85xx/mpc85xx_gpio.c optional mpc85xx gpio powerpc/mpc85xx/platform_mpc85xx.c optional mpc85xx powerpc/mpc85xx/pci_mpc85xx.c optional pci mpc85xx powerpc/mpc85xx/pci_mpc85xx_pcib.c optional pci mpc85xx powerpc/mpc85xx/qoriq_gpio.c optional mpc85xx gpio powerpc/ofw/ofw_machdep.c standard powerpc/ofw/ofw_pcibus.c optional pci powerpc/ofw/ofw_pcib_pci.c optional pci powerpc/ofw/ofw_real.c optional aim powerpc/ofw/ofw_syscons.c optional sc aim powerpc/ofw/ofwcall32.S optional aim powerpc powerpc/ofw/ofwcall64.S optional aim powerpc64 powerpc/ofw/ofwmagic.S optional aim powerpc/ofw/openpic_ofw.c optional aim | fdt powerpc/ofw/rtas.c optional aim powerpc/powermac/ata_kauai.c optional powermac ata | powermac atamacio powerpc/powermac/ata_macio.c optional powermac ata | powermac atamacio powerpc/powermac/ata_dbdma.c optional powermac ata | powermac atamacio powerpc/powermac/atibl.c optional powermac atibl powerpc/powermac/cuda.c optional powermac cuda powerpc/powermac/cpcht.c optional powermac pci powerpc/powermac/dbdma.c optional powermac pci powerpc/powermac/fcu.c optional powermac fcu powerpc/powermac/grackle.c optional powermac pci powerpc/powermac/hrowpic.c optional powermac pci powerpc/powermac/kiic.c optional powermac kiic powerpc/powermac/macgpio.c optional powermac pci powerpc/powermac/macio.c optional powermac pci powerpc/powermac/nvbl.c optional powermac nvbl powerpc/powermac/platform_powermac.c optional powermac powerpc/powermac/powermac_thermal.c optional powermac powerpc/powermac/pswitch.c optional powermac pswitch powerpc/powermac/pmu.c optional powermac pmu powerpc/powermac/smu.c optional powermac smu powerpc/powermac/smusat.c optional powermac smu powerpc/powermac/uninorth.c optional powermac powerpc/powermac/uninorthpci.c optional powermac pci powerpc/powermac/vcoregpio.c optional powermac powerpc/powerpc/altivec.c standard powerpc/powerpc/autoconf.c standard powerpc/powerpc/bcopy.c standard powerpc/powerpc/bus_machdep.c standard powerpc/powerpc/busdma_machdep.c standard powerpc/powerpc/clock.c standard powerpc/powerpc/copyinout.c standard powerpc/powerpc/copystr.c standard powerpc/powerpc/cpu.c standard powerpc/powerpc/db_disasm.c optional ddb powerpc/powerpc/db_hwwatch.c optional ddb powerpc/powerpc/db_interface.c optional ddb powerpc/powerpc/db_trace.c optional ddb powerpc/powerpc/dump_machdep.c standard powerpc/powerpc/elf32_machdep.c optional powerpc | compat_freebsd32 powerpc/powerpc/elf64_machdep.c optional powerpc64 powerpc/powerpc/exec_machdep.c standard powerpc/powerpc/fpu.c standard powerpc/powerpc/fuswintr.c standard powerpc/powerpc/gdb_machdep.c optional gdb powerpc/powerpc/in_cksum.c optional inet | inet6 powerpc/powerpc/interrupt.c standard powerpc/powerpc/intr_machdep.c standard powerpc/powerpc/iommu_if.m standard powerpc/powerpc/machdep.c standard powerpc/powerpc/mem.c optional mem powerpc/powerpc/mmu_if.m standard powerpc/powerpc/mp_machdep.c optional smp powerpc/powerpc/nexus.c standard powerpc/powerpc/openpic.c standard powerpc/powerpc/pic_if.m standard powerpc/powerpc/pmap_dispatch.c standard powerpc/powerpc/platform.c standard powerpc/powerpc/platform_if.m standard powerpc/powerpc/ptrace_machdep.c standard powerpc/powerpc/sc_machdep.c optional sc powerpc/powerpc/setjmp.S standard powerpc/powerpc/sigcode32.S optional powerpc | compat_freebsd32 powerpc/powerpc/sigcode64.S optional powerpc64 powerpc/powerpc/swtch32.S optional powerpc powerpc/powerpc/swtch64.S optional powerpc64 powerpc/powerpc/stack_machdep.c optional ddb | stack powerpc/powerpc/suswintr.c standard powerpc/powerpc/syncicache.c standard powerpc/powerpc/sys_machdep.c standard powerpc/powerpc/trap.c standard powerpc/powerpc/uio_machdep.c standard powerpc/powerpc/uma_machdep.c standard powerpc/powerpc/vm_machdep.c standard powerpc/ps3/ehci_ps3.c optional ps3 ehci powerpc/ps3/ohci_ps3.c optional ps3 ohci powerpc/ps3/if_glc.c optional ps3 glc powerpc/ps3/mmu_ps3.c optional ps3 powerpc/ps3/platform_ps3.c optional ps3 powerpc/ps3/ps3bus.c optional ps3 powerpc/ps3/ps3cdrom.c optional ps3 scbus powerpc/ps3/ps3disk.c optional ps3 powerpc/ps3/ps3pic.c optional ps3 powerpc/ps3/ps3_syscons.c optional ps3 vt powerpc/ps3/ps3-hvcall.S optional ps3 powerpc/pseries/phyp-hvcall.S optional pseries powerpc64 powerpc/pseries/mmu_phyp.c optional pseries powerpc64 powerpc/pseries/phyp_console.c optional pseries powerpc64 uart powerpc/pseries/phyp_llan.c optional llan powerpc/pseries/phyp_vscsi.c optional pseries powerpc64 scbus powerpc/pseries/platform_chrp.c optional pseries powerpc/pseries/plpar_iommu.c optional pseries powerpc64 powerpc/pseries/plpar_pcibus.c optional pseries powerpc64 pci powerpc/pseries/rtas_dev.c optional pseries powerpc/pseries/rtas_pci.c optional pseries pci powerpc/pseries/vdevice.c optional pseries powerpc64 powerpc/pseries/xics.c optional pseries powerpc64 powerpc/psim/iobus.c optional psim powerpc/psim/ata_iobus.c optional ata psim powerpc/psim/openpic_iobus.c optional psim powerpc/psim/uart_iobus.c optional uart psim Index: head/sys/powerpc/conf/MPC85XX =================================================================== --- head/sys/powerpc/conf/MPC85XX (revision 306357) +++ head/sys/powerpc/conf/MPC85XX (revision 306358) @@ -1,95 +1,99 @@ # # Custom kernel for Freescale MPC85XX development boards like the CDS etc. # # $FreeBSD$ # cpu BOOKE cpu BOOKE_E500 ident MPC85XX machine powerpc powerpc include "dpaa/config.dpaa" makeoptions DEBUG="-Wa,-me500 -g" makeoptions WERROR="-Werror -Wno-format -Wno-redundant-decls" makeoptions NO_MODULES=yes options FPU_EMU options _KPOSIX_PRIORITY_SCHEDULING options ALT_BREAK_TO_DEBUGGER options BREAK_TO_DEBUGGER options BOOTP options BOOTP_NFSROOT #options BOOTP_NFSV3 options CD9660 options COMPAT_43 options DDB #options DEADLKRES options DEVICE_POLLING #options DIAGNOSTIC options FDT #makeoptions FDT_DTS_FILE=mpc8555cds.dts options FFS options GDB options GEOM_PART_GPT options INET options INET6 options INVARIANTS options INVARIANT_SUPPORT options KDB options KTRACE options MD_ROOT options MPC85XX options MSDOSFS options NFS_ROOT options NFSCL options NFSLOCKD options PROCFS options PSEUDOFS options SCHED_ULE options CAPABILITIES options CAPABILITY_MODE options SMP options SYSVMSG options SYSVSEM options SYSVSHM options WITNESS options WITNESS_SKIPSPIN device ata device bpf device cfi device crypto device cryptodev device da device ds1553 device em device alc device ether device fxp device gpio device iic device iicbus #device isa device loop device md device miibus device pass device pci device quicc device random #device rl device scbus device scc device sec device tsec device tun device uart options USB_DEBUG # enable debug msgs #device uhci device ehci device umass device usb device vlan + +# P1022 DIU +device diu +device videomode Index: head/sys/powerpc/mpc85xx/fsl_diu.c =================================================================== --- head/sys/powerpc/mpc85xx/fsl_diu.c (nonexistent) +++ head/sys/powerpc/mpc85xx/fsl_diu.c (revision 306358) @@ -0,0 +1,479 @@ +/*- + * Copyright (c) 2015 Justin Hibbits + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include + +#include "gpio_if.h" + +#include +#include + +#include "fb_if.h" + +#define DIU_DESC_1 0x000 /* Plane1 Area Descriptor Pointer Register */ +#define DIU_DESC_2 0x004 /* Plane2 Area Descriptor Pointer Register */ +#define DIU_DESC_3 0x008 /* Plane3 Area Descriptor Pointer Register */ +#define DIU_GAMMA 0x00C /* Gamma Register */ +#define DIU_PALETTE 0x010 /* Palette Register */ +#define DIU_CURSOR 0x014 /* Cursor Register */ +#define DIU_CURS_POS 0x018 /* Cursor Position Register */ +#define CURSOR_Y_SHIFT 16 +#define CURSOR_X_SHIFT 0 +#define DIU_DIU_MODE 0x01C /* DIU4 Mode */ +#define DIU_MODE_M 0x7 +#define DIU_MODE_S 0 +#define DIU_MODE_NORMAL 0x1 +#define DIU_MODE_2 0x2 +#define DIU_MODE_3 0x3 +#define DIU_MODE_COLBAR 0x4 +#define DIU_BGND 0x020 /* Background */ +#define DIU_BGND_WB 0x024 /* Background Color in write back Mode Register */ +#define DIU_DISP_SIZE 0x028 /* Display Size */ +#define DELTA_Y_S 16 +#define DELTA_X_S 0 +#define DIU_WB_SIZE 0x02C /* Write back Plane Size Register */ +#define DELTA_Y_WB_S 16 +#define DELTA_X_WB_S 0 +#define DIU_WB_MEM_ADDR 0x030 /* Address to Store the write back Plane Register */ +#define DIU_HSYN_PARA 0x034 /* Horizontal Sync Parameter */ +#define BP_H_SHIFT 22 +#define PW_H_SHIFT 11 +#define FP_H_SHIFT 0 +#define DIU_VSYN_PARA 0x038 /* Vertical Sync Parameter */ +#define BP_V_SHIFT 22 +#define PW_V_SHIFT 11 +#define FP_V_SHIFT 0 +#define DIU_SYNPOL 0x03C /* Synchronize Polarity */ +#define BP_VS (1 << 4) +#define BP_HS (1 << 3) +#define INV_CS (1 << 2) +#define INV_VS (1 << 1) +#define INV_HS (1 << 0) +#define INV_PDI_VS (1 << 8) /* Polarity of PDI input VSYNC. */ +#define INV_PDI_HS (1 << 9) /* Polarity of PDI input HSYNC. */ +#define INV_PDI_DE (1 << 10) /* Polarity of PDI input DE. */ +#define DIU_THRESHOLD 0x040 /* Threshold */ +#define LS_BF_VS_SHIFT 16 +#define OUT_BUF_LOW_SHIFT 0 +#define DIU_INT_STATUS 0x044 /* Interrupt Status */ +#define DIU_INT_MASK 0x048 /* Interrupt Mask */ +#define DIU_COLBAR_1 0x04C /* COLBAR_1 */ +#define DIU_COLORBARn_R(x) ((x & 0xff) << 16) +#define DIU_COLORBARn_G(x) ((x & 0xff) << 8) +#define DIU_COLORBARn_B(x) ((x & 0xff) << 0) +#define DIU_COLBAR_2 0x050 /* COLBAR_2 */ +#define DIU_COLBAR_3 0x054 /* COLBAR_3 */ +#define DIU_COLBAR_4 0x058 /* COLBAR_4 */ +#define DIU_COLBAR_5 0x05c /* COLBAR_5 */ +#define DIU_COLBAR_6 0x060 /* COLBAR_6 */ +#define DIU_COLBAR_7 0x064 /* COLBAR_7 */ +#define DIU_COLBAR_8 0x068 /* COLBAR_8 */ +#define DIU_FILLING 0x06C /* Filling Register */ +#define DIU_PLUT 0x070 /* Priority Look Up Table Register */ + +/* Control Descriptor */ +#define DIU_CTRLDESCL(n, m) 0x200 + (0x40 * n) + 0x4 * (m - 1) +#define DIU_CTRLDESCLn_1(n) DIU_CTRLDESCL(n, 1) +#define DIU_CTRLDESCLn_2(n) DIU_CTRLDESCL(n, 2) +#define DIU_CTRLDESCLn_3(n) DIU_CTRLDESCL(n, 3) +#define TRANS_SHIFT 20 +#define DIU_CTRLDESCLn_4(n) DIU_CTRLDESCL(n, 4) +#define BPP_MASK 0xf /* Bit per pixel Mask */ +#define BPP_SHIFT 16 /* Bit per pixel Shift */ +#define BPP24 0x5 +#define EN_LAYER (1 << 31) /* Enable the layer */ +#define DIU_CTRLDESCLn_5(n) DIU_CTRLDESCL(n, 5) +#define DIU_CTRLDESCLn_6(n) DIU_CTRLDESCL(n, 6) +#define DIU_CTRLDESCLn_7(n) DIU_CTRLDESCL(n, 7) +#define DIU_CTRLDESCLn_8(n) DIU_CTRLDESCL(n, 8) +#define DIU_CTRLDESCLn_9(n) DIU_CTRLDESCL(n, 9) + +#define NUM_LAYERS 1 + +struct panel_info { + uint32_t panel_width; + uint32_t panel_height; + uint32_t panel_hbp; + uint32_t panel_hpw; + uint32_t panel_hfp; + uint32_t panel_vbp; + uint32_t panel_vpw; + uint32_t panel_vfp; + uint32_t panel_freq; + uint32_t clk_div; +}; + +struct diu_area_descriptor { + uint32_t pixel_format; + uint32_t bitmap_address; + uint32_t source_size; + uint32_t aoi_size; + uint32_t aoi_offset; + uint32_t display_offset; + uint32_t chroma_key_max; + uint32_t chroma_key_min; + uint32_t next_ad_addr; +} __aligned(32); + +struct diu_softc { + struct resource *res[2]; + void *ih; + device_t sc_dev; + device_t sc_fbd; /* fbd child */ + struct fb_info sc_info; + struct panel_info sc_panel; + struct diu_area_descriptor *sc_planes[3]; + uint8_t *sc_gamma; + uint8_t *sc_cursor; +}; + +static struct resource_spec diu_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { SYS_RES_IRQ, 0, RF_ACTIVE }, + { -1, 0 } +}; + +static int +diu_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_is_compatible(dev, "fsl,diu")) + return (ENXIO); + + device_set_desc(dev, "Freescale Display Interface Unit"); + return (BUS_PROBE_DEFAULT); +} + +static void +diu_intr(void *arg) +{ + struct diu_softc *sc; + int reg; + + sc = arg; + + /* Ack interrupts */ + reg = bus_read_4(sc->res[0], DIU_INT_STATUS); + bus_write_4(sc->res[0], DIU_INT_STATUS, reg); + + /* TODO interrupt handler */ +} + +static int +diu_set_pxclk(device_t dev, unsigned int freq) +{ + phandle_t node; + unsigned long bus_freq; + uint32_t pxclk_set; + uint32_t clkdvd; + int res; + + node = ofw_bus_get_node(device_get_parent(dev)); + if ((res = OF_getencprop(node, "bus-frequency", + (pcell_t *)&bus_freq, sizeof(bus_freq)) <= 0)) { + device_printf(dev, "Unable to get bus frequency\n"); + return (ENXIO); + } + + /* freq is in kHz */ + freq *= 1000; + /* adding freq/2 to round-to-closest */ + pxclk_set = min(max((bus_freq + freq/2) / freq, 2), 255) << 16; + pxclk_set |= OCP85XX_CLKDVDR_PXCKEN; + clkdvd = ccsr_read4(OCP85XX_CLKDVDR); + clkdvd &= ~(OCP85XX_CLKDVDR_PXCKEN | OCP85XX_CLKDVDR_PXCKINV | + OCP85XX_CLKDVDR_PXCLK_MASK); + ccsr_write4(OCP85XX_CLKDVDR, clkdvd); + ccsr_write4(OCP85XX_CLKDVDR, clkdvd | pxclk_set); + + return (0); +} + +static int +diu_init(struct diu_softc *sc) +{ + struct panel_info *panel; + int reg; + + panel = &sc->sc_panel; + + /* Temporarily disable the DIU while configuring */ + reg = bus_read_4(sc->res[0], DIU_DIU_MODE); + reg &= ~(DIU_MODE_M << DIU_MODE_S); + bus_write_4(sc->res[0], DIU_DIU_MODE, reg); + + if (diu_set_pxclk(sc->sc_dev, panel->panel_freq) < 0) { + return (ENXIO); + } + + /* Configure DIU */ + /* Need to set these somehow later... */ + bus_write_4(sc->res[0], DIU_GAMMA, vtophys(sc->sc_gamma)); + bus_write_4(sc->res[0], DIU_CURSOR, vtophys(sc->sc_cursor)); + bus_write_4(sc->res[0], DIU_CURS_POS, 0); + + reg = ((sc->sc_info.fb_height) << DELTA_Y_S); + reg |= sc->sc_info.fb_width; + bus_write_4(sc->res[0], DIU_DISP_SIZE, reg); + + reg = (panel->panel_hbp << BP_H_SHIFT); + reg |= (panel->panel_hpw << PW_H_SHIFT); + reg |= (panel->panel_hfp << FP_H_SHIFT); + bus_write_4(sc->res[0], DIU_HSYN_PARA, reg); + + reg = (panel->panel_vbp << BP_V_SHIFT); + reg |= (panel->panel_vpw << PW_V_SHIFT); + reg |= (panel->panel_vfp << FP_V_SHIFT); + bus_write_4(sc->res[0], DIU_VSYN_PARA, reg); + + bus_write_4(sc->res[0], DIU_BGND, 0); + + /* Mask all the interrupts */ + bus_write_4(sc->res[0], DIU_INT_MASK, 0x3f); + + /* Reset all layers */ + sc->sc_planes[0] = contigmalloc(sizeof(struct diu_area_descriptor), + M_DEVBUF, M_ZERO, 0, BUS_SPACE_MAXADDR_32BIT, 32, 0); + bus_write_4(sc->res[0], DIU_DESC_1, vtophys(sc->sc_planes[0])); + bus_write_4(sc->res[0], DIU_DESC_2, 0); + bus_write_4(sc->res[0], DIU_DESC_3, 0); + + /* Setup first plane */ + /* Area descriptor fields are little endian, so byte swap. */ + /* Word 0: Pixel format */ + /* Set to 8:8:8:8 ARGB, 4 bytes per pixel, no flip. */ +#define MAKE_PXLFMT(as,rs,gs,bs,a,r,g,b,f,s) \ + htole32((as << (4 * a)) | (rs << 4 * r) | \ + (gs << 4 * g) | (bs << 4 * b) | \ + (f << 28) | (s << 16) | \ + (a << 25) | (r << 19) | \ + (g << 21) | (b << 24)) + reg = MAKE_PXLFMT(8, 8, 8, 8, 3, 2, 1, 0, 1, 3); + sc->sc_planes[0]->pixel_format = reg; + /* Word 1: Bitmap address */ + sc->sc_planes[0]->bitmap_address = htole32(sc->sc_info.fb_pbase); + /* Word 2: Source size/global alpha */ + reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 12)); + sc->sc_planes[0]->source_size = htole32(reg); + /* Word 3: AOI Size */ + reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 16)); + sc->sc_planes[0]->aoi_size = htole32(reg); + /* Word 4: AOI Offset */ + sc->sc_planes[0]->aoi_offset = 0; + /* Word 5: Display offset */ + sc->sc_planes[0]->display_offset = 0; + /* Word 6: Chroma key max */ + sc->sc_planes[0]->chroma_key_max = 0; + /* Word 7: Chroma key min */ + reg = 255 << 16 | 255 << 8 | 255; + sc->sc_planes[0]->chroma_key_min = htole32(reg); + /* Word 8: Next AD */ + sc->sc_planes[0]->next_ad_addr = 0; + + /* TODO: derive this from the panel size */ + bus_write_4(sc->res[0], DIU_PLUT, 0x1f5f666); + + /* Enable DIU in normal mode */ + reg = bus_read_4(sc->res[0], DIU_DIU_MODE); + reg &= ~(DIU_MODE_M << DIU_MODE_S); + reg |= (DIU_MODE_NORMAL << DIU_MODE_S); + bus_write_4(sc->res[0], DIU_DIU_MODE, reg); + + return (0); +} + +static int +diu_attach(device_t dev) +{ + struct edid_info *edid; + struct diu_softc *sc; + const struct videomode *videomode; + void *edid_cells; + const char *vm_name; + phandle_t node; + int h, r, w; + int err, i; + + sc = device_get_softc(dev); + sc->sc_dev = dev; + + if (bus_alloc_resources(dev, diu_spec, sc->res)) { + device_printf(dev, "could not allocate resources\n"); + return (ENXIO); + } + + node = ofw_bus_get_node(dev); + /* Setup interrupt handler */ + err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE, + NULL, diu_intr, sc, &sc->ih); + if (err) { + device_printf(dev, "Unable to alloc interrupt resource.\n"); + return (ENXIO); + } + + /* TODO: Eventually, allow EDID to be dynamically provided. */ + if (OF_getprop_alloc(node, "edid", 1, &edid_cells) <= 0) { + /* + * u-boot uses the environment variable name 'video-mode', so + * just use the same name here. Should allow another variable + * that better fits our design model, but this is fine. + */ + if ((vm_name = kern_getenv("video-mode")) == NULL) { + device_printf(dev, + "No EDID data and no video-mode env set\n"); + return (ENXIO); + } + } + if (edid_cells != NULL) { + if (edid_parse(edid_cells, edid) != 0) { + device_printf(dev, "Error parsing EDID\n"); + OF_prop_free(edid_cells); + return (ENXIO); + } + videomode = edid->edid_preferred_mode; + } else { + /* Parse video-mode kenv variable. */ + if ((err = sscanf(vm_name, "fslfb:%dx%d@%d", &w, &h, &r)) != 3) { + device_printf(dev, + "Cannot parse video mode: %s\n", vm_name); + return (ENXIO); + } + videomode = pick_mode_by_ref(w, h, r); + if (videomode == NULL) { + device_printf(dev, + "Cannot find mode for %dx%d@%d", w, h, r); + return (ENXIO); + } + } + + sc->sc_panel.panel_width = videomode->hdisplay; + sc->sc_panel.panel_height = videomode->vdisplay; + sc->sc_panel.panel_hbp = videomode->hsync_start - videomode->hdisplay; + sc->sc_panel.panel_hfp = videomode->htotal - videomode->hsync_end; + sc->sc_panel.panel_hpw = videomode->hsync_end - videomode->hsync_start; + sc->sc_panel.panel_vbp = videomode->vsync_start - videomode->vdisplay; + sc->sc_panel.panel_vfp = videomode->vtotal - videomode->vsync_end; + sc->sc_panel.panel_vpw = videomode->vsync_end - videomode->vsync_start; + sc->sc_panel.panel_freq = videomode->dot_clock; + + sc->sc_info.fb_width = sc->sc_panel.panel_width; + sc->sc_info.fb_height = sc->sc_panel.panel_height; + sc->sc_info.fb_stride = sc->sc_info.fb_width * 4; + sc->sc_info.fb_bpp = sc->sc_info.fb_depth = 32; + sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride; + sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size, + M_DEVBUF, M_ZERO, 0, BUS_SPACE_MAXADDR_32BIT, PAGE_SIZE, 0); + sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase); + + /* Gamma table is 3 consecutive segments of 256 bytes. */ + sc->sc_gamma = contigmalloc(3 * 256, M_DEVBUF, 0, 0, + BUS_SPACE_MAXADDR_32BIT, PAGE_SIZE, 0); + /* Initialize gamma to default */ + for (i = 0; i < 3 * 256; i++) + sc->sc_gamma[i] = (i % 256); + + /* Cursor format is 32x32x16bpp */ + sc->sc_cursor = contigmalloc(32 * 32 * 2, M_DEVBUF, M_ZERO, 0, + BUS_SPACE_MAXADDR_32BIT, PAGE_SIZE, 0); + + diu_init(sc); + + sc->sc_info.fb_name = device_get_nameunit(dev); + + /* Ask newbus to attach framebuffer device to me. */ + sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev)); + if (sc->sc_fbd == NULL) + device_printf(dev, "Can't attach fbd device\n"); + + if ((err = device_probe_and_attach(sc->sc_fbd)) != 0) { + device_printf(dev, "Failed to attach fbd device: %d\n", err); + } + + return (0); +} + +static struct fb_info * +diu_fb_getinfo(device_t dev) +{ + struct diu_softc *sc = device_get_softc(dev); + + return (&sc->sc_info); +} + +static device_method_t diu_methods[] = { + DEVMETHOD(device_probe, diu_probe), + DEVMETHOD(device_attach, diu_attach), + + /* Framebuffer service methods */ + DEVMETHOD(fb_getinfo, diu_fb_getinfo), + { 0, 0 } +}; + +static driver_t diu_driver = { + "fb", + diu_methods, + sizeof(struct diu_softc), +}; + +static devclass_t diu_devclass; + +DRIVER_MODULE(fb, simplebus, diu_driver, diu_devclass, 0, 0); Property changes on: head/sys/powerpc/mpc85xx/fsl_diu.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/powerpc/mpc85xx/mpc85xx.h =================================================================== --- head/sys/powerpc/mpc85xx/mpc85xx.h (revision 306357) +++ head/sys/powerpc/mpc85xx/mpc85xx.h (revision 306358) @@ -1,166 +1,173 @@ /*- * Copyright (C) 2008 Semihalf, Rafal Jaworowski * Copyright 2006 by Juniper Networks. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _MPC85XX_H_ #define _MPC85XX_H_ #include /* * Configuration control and status registers */ extern vm_offset_t ccsrbar_va; #define CCSRBAR_VA ccsrbar_va #define OCP85XX_CCSRBAR (CCSRBAR_VA + 0x0) #define OCP85XX_BPTR (CCSRBAR_VA + 0x20) #define OCP85XX_BSTRH (CCSRBAR_VA + 0x20) #define OCP85XX_BSTRL (CCSRBAR_VA + 0x24) #define OCP85XX_BSTAR (CCSRBAR_VA + 0x28) #define OCP85XX_COREDISR (CCSRBAR_VA + 0xE0094) #define OCP85XX_BRR (CCSRBAR_VA + 0xE00E4) /* * Run Control and Power Management registers */ #define CCSR_CTBENR (CCSRBAR_VA + 0xE2084) #define CCSR_CTBCKSELR (CCSRBAR_VA + 0xE208C) #define CCSR_CTBCHLTCR (CCSRBAR_VA + 0xE2094) /* * DDR Memory controller. */ #define OCP85XX_DDR1_CS0_CONFIG (CCSRBAR_VA + 0x8080) /* * E500 Coherency Module registers */ #define OCP85XX_EEBPCR (CCSRBAR_VA + 0x1010) /* * Local access registers */ /* Write order: OCP_LAWBARH -> OCP_LAWBARL -> OCP_LAWSR */ #define OCP85XX_LAWBARH(n) (CCSRBAR_VA + 0xc00 + 0x10 * (n)) #define OCP85XX_LAWBARL(n) (CCSRBAR_VA + 0xc04 + 0x10 * (n)) #define OCP85XX_LAWSR_QORIQ(n) (CCSRBAR_VA + 0xc08 + 0x10 * (n)) #define OCP85XX_LAWBAR(n) (CCSRBAR_VA + 0xc08 + 0x10 * (n)) #define OCP85XX_LAWSR_85XX(n) (CCSRBAR_VA + 0xc10 + 0x10 * (n)) #define OCP85XX_LAWSR(n) (mpc85xx_is_qoriq() ? OCP85XX_LAWSR_QORIQ(n) : \ OCP85XX_LAWSR_85XX(n)) /* Attribute register */ #define OCP85XX_ENA_MASK 0x80000000 #define OCP85XX_DIS_MASK 0x7fffffff #define OCP85XX_TGTIF_LBC_QORIQ 0x1f #define OCP85XX_TGTIF_RAM_INTL_QORIQ 0x14 #define OCP85XX_TGTIF_RAM1_QORIQ 0x10 #define OCP85XX_TGTIF_RAM2_QORIQ 0x11 #define OCP85XX_TGTIF_BMAN 0x18 #define OCP85XX_TGTIF_DCSR 0x1D #define OCP85XX_TGTIF_QMAN 0x3C #define OCP85XX_TRGT_SHIFT_QORIQ 20 #define OCP85XX_TGTIF_LBC_85XX 0x04 #define OCP85XX_TGTIF_RAM_INTL_85XX 0x0b #define OCP85XX_TGTIF_RIO_85XX 0x0c #define OCP85XX_TGTIF_RAM1_85XX 0x0f #define OCP85XX_TGTIF_RAM2_85XX 0x16 #define OCP85XX_TGTIF_LBC \ (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_LBC_QORIQ : OCP85XX_TGTIF_LBC_85XX) #define OCP85XX_TGTIF_RAM_INTL \ (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM_INTL_QORIQ : OCP85XX_TGTIF_RAM_INTL_85XX) #define OCP85XX_TGTIF_RIO \ (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RIO_QORIQ : OCP85XX_TGTIF_RIO_85XX) #define OCP85XX_TGTIF_RAM1 \ (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM1_QORIQ : OCP85XX_TGTIF_RAM1_85XX) #define OCP85XX_TGTIF_RAM2 \ (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM2_QORIQ : OCP85XX_TGTIF_RAM2_85XX) /* * L2 cache registers */ #define OCP85XX_L2CTL (CCSRBAR_VA + 0x20000) /* * L3 CoreNet platform cache (CPC) registers */ #define OCP85XX_CPC_CSR0 (CCSRBAR_VA + 0x10000) #define OCP85XX_CPC_CSR0_CE 0x80000000 #define OCP85XX_CPC_CSR0_PE 0x40000000 #define OCP85XX_CPC_CSR0_FI 0x00200000 #define OCP85XX_CPC_CSR0_WT 0x00080000 #define OCP85XX_CPC_CSR0_FL 0x00000800 #define OCP85XX_CPC_CSR0_LFC 0x00000400 #define OCP85XX_CPC_CFG0 (CCSRBAR_VA + 0x10008) #define OCP85XX_CPC_CFG_SZ_MASK 0x00003fff #define OCP85XX_CPC_CFG0_SZ_K(x) (((x) & OCP85XX_CPC_CFG_SZ_MASK) << 6) /* * Power-On Reset configuration */ #define OCP85XX_PORDEVSR (CCSRBAR_VA + 0xe000c) #define OCP85XX_PORDEVSR_IO_SEL 0x00780000 #define OCP85XX_PORDEVSR_IO_SEL_SHIFT 19 #define OCP85XX_PORDEVSR2 (CCSRBAR_VA + 0xe0014) /* * Status Registers. */ #define OCP85XX_RSTCR (CCSRBAR_VA + 0xe00b0) +#define OCP85XX_CLKDVDR (CCSRBAR_VA + 0xe0800) +#define OCP85XX_CLKDVDR_PXCKEN 0x80000000 +#define OCP85XX_CLKDVDR_SSICKEN 0x20000000 +#define OCP85XX_CLKDVDR_PXCKINV 0x10000000 +#define OCP85XX_CLKDVDR_PXCLK_MASK 0x00FF0000 +#define OCP85XX_CLKDVDR_SSICLK_MASK 0x000000FF + /* * Run Control/Power Management Registers. */ #define OCP85XX_RCPM_CDOZSR (CCSRBAR_VA + 0xe2004) #define OCP85XX_RCPM_CDOZCR (CCSRBAR_VA + 0xe200c) /* * Prototypes. */ uint32_t ccsr_read4(uintptr_t addr); void ccsr_write4(uintptr_t addr, uint32_t val); int law_enable(int trgt, uint64_t bar, uint32_t size); int law_disable(int trgt, uint64_t bar, uint32_t size); int law_getmax(void); int law_pci_target(struct resource *, int *, int *); DECLARE_CLASS(mpc85xx_platform); int mpc85xx_attach(platform_t); void mpc85xx_enable_l3_cache(void); void mpc85xx_fix_errata(vm_offset_t); void dataloss_erratum_access(vm_offset_t, uint32_t); int mpc85xx_is_qoriq(void); #endif /* _MPC85XX_H_ */