Index: head/sys/dev/bhnd/bhnd_core.h =================================================================== --- head/sys/dev/bhnd/bhnd_core.h (revision 306286) +++ head/sys/dev/bhnd/bhnd_core.h (nonexistent) @@ -1,49 +0,0 @@ -/*- - * Copyright (c) 2015 Landon Fuller - * Copyright (c) 2010 Broadcom Corporation - * - * This file is derived from the hndsoc.h header distributed with - * Broadcom's initial brcm80211 Linux driver release, as - * contributed to the Linux staging repository. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * $FreeBSD$ - */ - -#ifndef _BHND_BHND_CORE_H_ -#define _BHND_BHND_CORE_H_ - -/* Common core control flags */ -#define BHND_CF 0x0408 -#define BHND_CF_BIST_EN 0x8000 /**< built-in self test */ -#define BHND_CF_PME_EN 0x4000 /**< ??? */ -#define BHND_CF_CORE_BITS 0x3ffc /**< core specific flag mask */ -#define BHND_CF_FGC 0x0002 /**< force clock gating */ -#define BHND_CF_CLOCK_EN 0x0001 /**< enable clock */ - -/* Common core status flags */ -#define BHND_SF 0x0500 -#define BHND_SF_BIST_DONE 0x8000 /**< ??? */ -#define BHND_SF_BIST_ERROR 0x4000 /**< ??? */ -#define BHND_SF_GATED_CLK 0x2000 /**< clock gated */ -#define BHND_SF_DMA64 0x1000 /**< supports 64-bit DMA */ -#define BHND_SF_CORE_BITS 0x0fff /**< core-specific status mask */ - -/*Reset core control flags */ -#define BHND_RESET_CF 0x0800 -#define BHND_RESET_CF_ENABLE 0x0001 - -#define BHND_RESET_SF 0x0804 - -#endif /* _BHND_BHND_CORE_H_ */ Property changes on: head/sys/dev/bhnd/bhnd_core.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/dev/bhnd/bcma/bcma.c =================================================================== --- head/sys/dev/bhnd/bcma/bcma.c (revision 306286) +++ head/sys/dev/bhnd/bcma/bcma.c (revision 306287) @@ -1,635 +1,800 @@ /*- * Copyright (c) 2015 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include -#include "bcmavar.h" +#include #include "bcma_dmp.h" #include "bcma_eromreg.h" #include "bcma_eromvar.h" -#include +#include "bcmavar.h" /* RID used when allocating EROM table */ #define BCMA_EROM_RID 0 static bhnd_erom_class_t * bcma_get_erom_class(driver_t *driver) { return (&bcma_erom_parser); } int bcma_probe(device_t dev) { device_set_desc(dev, "BCMA BHND bus"); return (BUS_PROBE_DEFAULT); } /** * Default bcma(4) bus driver implementation of DEVICE_ATTACH(). * * This implementation initializes internal bcma(4) state and performs * bus enumeration, and must be called by subclassing drivers in * DEVICE_ATTACH() before any other bus methods. */ int bcma_attach(device_t dev) { int error; /* Enumerate children */ if ((error = bcma_add_children(dev))) { device_delete_children(dev); return (error); } return (0); } int bcma_detach(device_t dev) { return (bhnd_generic_detach(dev)); } +static device_t +bcma_add_child(device_t dev, u_int order, const char *name, int unit) +{ + struct bcma_devinfo *dinfo; + device_t child; + + child = device_add_child_ordered(dev, order, name, unit); + if (child == NULL) + return (NULL); + + if ((dinfo = bcma_alloc_dinfo(dev)) == NULL) { + device_delete_child(dev, child); + return (NULL); + } + + device_set_ivars(child, dinfo); + + return (child); +} + +static void +bcma_child_deleted(device_t dev, device_t child) +{ + struct bhnd_softc *sc; + struct bcma_devinfo *dinfo; + + sc = device_get_softc(dev); + + /* Call required bhnd(4) implementation */ + bhnd_generic_child_deleted(dev, child); + + /* Free bcma device info */ + if ((dinfo = device_get_ivars(child)) != NULL) + bcma_free_dinfo(dev, dinfo); + + device_set_ivars(child, NULL); +} + static int bcma_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) { const struct bcma_devinfo *dinfo; const struct bhnd_core_info *ci; dinfo = device_get_ivars(child); ci = &dinfo->corecfg->core_info; switch (index) { case BHND_IVAR_VENDOR: *result = ci->vendor; return (0); case BHND_IVAR_DEVICE: *result = ci->device; return (0); case BHND_IVAR_HWREV: *result = ci->hwrev; return (0); case BHND_IVAR_DEVICE_CLASS: *result = bhnd_core_class(ci); return (0); case BHND_IVAR_VENDOR_NAME: *result = (uintptr_t) bhnd_vendor_name(ci->vendor); return (0); case BHND_IVAR_DEVICE_NAME: *result = (uintptr_t) bhnd_core_name(ci); return (0); case BHND_IVAR_CORE_INDEX: *result = ci->core_idx; return (0); case BHND_IVAR_CORE_UNIT: *result = ci->unit; return (0); + case BHND_IVAR_PMU_INFO: + *result = (uintptr_t) dinfo->pmu_info; + return (0); default: return (ENOENT); } } static int bcma_write_ivar(device_t dev, device_t child, int index, uintptr_t value) { + struct bcma_devinfo *dinfo; + + dinfo = device_get_ivars(child); + switch (index) { case BHND_IVAR_VENDOR: case BHND_IVAR_DEVICE: case BHND_IVAR_HWREV: case BHND_IVAR_DEVICE_CLASS: case BHND_IVAR_VENDOR_NAME: case BHND_IVAR_DEVICE_NAME: case BHND_IVAR_CORE_INDEX: case BHND_IVAR_CORE_UNIT: return (EINVAL); + case BHND_IVAR_PMU_INFO: + dinfo->pmu_info = (struct bhnd_core_pmu_info *) value; + return (0); default: return (ENOENT); } } static struct resource_list * bcma_get_resource_list(device_t dev, device_t child) { struct bcma_devinfo *dinfo = device_get_ivars(child); return (&dinfo->resources); } static int -bcma_reset_core(device_t dev, device_t child, uint16_t flags) +bcma_read_iost(device_t dev, device_t child, uint16_t *iost) { - struct bcma_devinfo *dinfo; + uint32_t value; + int error; + if ((error = bhnd_read_config(child, BCMA_DMP_IOSTATUS, &value, 4))) + return (error); + + /* Return only the bottom 16 bits */ + *iost = (value & BCMA_DMP_IOST_MASK); + return (0); +} + +static int +bcma_read_ioctl(device_t dev, device_t child, uint16_t *ioctl) +{ + uint32_t value; + int error; + + if ((error = bhnd_read_config(child, BCMA_DMP_IOCTRL, &value, 4))) + return (error); + + /* Return only the bottom 16 bits */ + *ioctl = (value & BCMA_DMP_IOCTRL_MASK); + return (0); +} + +static int +bcma_write_ioctl(device_t dev, device_t child, uint16_t value, uint16_t mask) +{ + struct bcma_devinfo *dinfo; + struct bhnd_resource *r; + uint32_t ioctl; + if (device_get_parent(child) != dev) - BHND_BUS_RESET_CORE(device_get_parent(dev), child, flags); + return (EINVAL); dinfo = device_get_ivars(child); - - /* Can't reset the core without access to the agent registers */ - if (dinfo->res_agent == NULL) + if ((r = dinfo->res_agent) == NULL) return (ENODEV); - /* Start reset */ - bhnd_bus_write_4(dinfo->res_agent, BHND_RESET_CF, BHND_RESET_CF_ENABLE); - bhnd_bus_read_4(dinfo->res_agent, BHND_RESET_CF); - DELAY(10); + /* Write new value */ + ioctl = bhnd_bus_read_4(r, BCMA_DMP_IOCTRL); + ioctl &= ~(BCMA_DMP_IOCTRL_MASK & mask); + ioctl |= (value & mask); - /* Disable clock */ - bhnd_bus_write_4(dinfo->res_agent, BHND_CF, flags); - bhnd_bus_read_4(dinfo->res_agent, BHND_CF); - DELAY(10); + bhnd_bus_write_4(r, BCMA_DMP_IOCTRL, ioctl); - /* Enable clocks & force clock gating */ - bhnd_bus_write_4(dinfo->res_agent, BHND_CF, BHND_CF_CLOCK_EN | - BHND_CF_FGC | flags); - bhnd_bus_read_4(dinfo->res_agent, BHND_CF); + /* Perform read-back and wait for completion */ + bhnd_bus_read_4(r, BCMA_DMP_IOCTRL); DELAY(10); - /* Complete reset */ - bhnd_bus_write_4(dinfo->res_agent, BHND_RESET_CF, 0); - bhnd_bus_read_4(dinfo->res_agent, BHND_RESET_CF); - DELAY(10); + return (0); +} - /* Release force clock gating */ - bhnd_bus_write_4(dinfo->res_agent, BHND_CF, BHND_CF_CLOCK_EN | flags); - bhnd_bus_read_4(dinfo->res_agent, BHND_CF); - DELAY(10); +static bool +bcma_is_hw_suspended(device_t dev, device_t child) +{ + uint32_t rst; + uint16_t ioctl; + int error; + /* Is core held in RESET? */ + error = bhnd_read_config(child, BCMA_DMP_RESETCTRL, &rst, 4); + if (error) { + device_printf(child, "error reading HW reset state: %d\n", + error); + return (true); + } + + if (rst & BMCA_DMP_RC_RESET) + return (true); + + /* Is core clocked? */ + error = bhnd_read_ioctl(child, &ioctl); + if (error) { + device_printf(child, "error reading HW ioctl register: %d\n", + error); + return (true); + } + + if (!(ioctl & BHND_IOCTL_CLK_EN)) + return (true); + + return (false); +} + +static int +bcma_reset_hw(device_t dev, device_t child, uint16_t ioctl) +{ + struct bcma_devinfo *dinfo; + struct bhnd_core_pmu_info *pm; + struct bhnd_resource *r; + int error; + + if (device_get_parent(child) != dev) + return (EINVAL); + + dinfo = device_get_ivars(child); + pm = dinfo->pmu_info; + + /* We require exclusive control over BHND_IOCTL_CLK_EN and + * BHND_IOCTL_CLK_FORCE. */ + if (ioctl & (BHND_IOCTL_CLK_EN | BHND_IOCTL_CLK_FORCE)) + return (EINVAL); + + /* Can't suspend the core without access to the agent registers */ + if ((r = dinfo->res_agent) == NULL) + return (ENODEV); + + /* Place core into known RESET state */ + if ((error = BHND_BUS_SUSPEND_HW(dev, child))) + return (error); + + /* + * Leaving the core in reset: + * - Set the caller's IOCTL flags + * - Enable clocks + * - Force clock distribution to ensure propagation throughout the + * core. + */ + error = bhnd_write_ioctl(child, + ioctl | BHND_IOCTL_CLK_EN | BHND_IOCTL_CLK_FORCE, UINT16_MAX); + if (error) + return (error); + + /* Bring the core out of reset */ + if ((error = bcma_dmp_write_reset(child, dinfo, 0x0))) + return (error); + + /* Disable forced clock gating (leaving clock enabled) */ + error = bhnd_write_ioctl(child, 0x0, BHND_IOCTL_CLK_FORCE); + if (error) + return (error); + return (0); } static int -bcma_suspend_core(device_t dev, device_t child) +bcma_suspend_hw(device_t dev, device_t child) { - struct bcma_devinfo *dinfo; + struct bcma_devinfo *dinfo; + struct bhnd_core_pmu_info *pm; + struct bhnd_resource *r; + uint32_t rst; + int error; if (device_get_parent(child) != dev) - BHND_BUS_SUSPEND_CORE(device_get_parent(dev), child); + return (EINVAL); dinfo = device_get_ivars(child); + pm = dinfo->pmu_info; /* Can't suspend the core without access to the agent registers */ - if (dinfo->res_agent == NULL) + if ((r = dinfo->res_agent) == NULL) return (ENODEV); - // TODO - perform suspend + /* Wait for any pending reset operations to clear */ + if ((error = bcma_dmp_wait_reset(child, dinfo))) + return (error); - return (ENXIO); + /* Already in reset? */ + rst = bhnd_bus_read_4(r, BCMA_DMP_RESETCTRL); + if (rst & BMCA_DMP_RC_RESET) + return (0); + + /* Put core into reset */ + if ((error = bcma_dmp_write_reset(child, dinfo, BMCA_DMP_RC_RESET))) + return (error); + + /* Clear core flags */ + if ((error = bhnd_write_ioctl(child, 0x0, UINT16_MAX))) + return (error); + + /* Inform PMU that all outstanding request state should be discarded */ + if (pm != NULL) { + if ((error = BHND_PMU_CORE_RELEASE(pm->pm_pmu, pm))) + return (error); + } + + return (0); } -static uint32_t -bcma_read_config(device_t dev, device_t child, bus_size_t offset, u_int width) +static int +bcma_read_config(device_t dev, device_t child, bus_size_t offset, void *value, + u_int width) { struct bcma_devinfo *dinfo; struct bhnd_resource *r; /* Must be a directly attached child core */ if (device_get_parent(child) != dev) - return (UINT32_MAX); + return (EINVAL); /* Fetch the agent registers */ dinfo = device_get_ivars(child); if ((r = dinfo->res_agent) == NULL) - return (UINT32_MAX); + return (ENODEV); /* Verify bounds */ if (offset > rman_get_size(r->res)) - return (UINT32_MAX); + return (EFAULT); if (rman_get_size(r->res) - offset < width) - return (UINT32_MAX); + return (EFAULT); switch (width) { case 1: - return (bhnd_bus_read_1(r, offset)); + *((uint8_t *)value) = bhnd_bus_read_1(r, offset); + return (0); case 2: - return (bhnd_bus_read_2(r, offset)); + *((uint16_t *)value) = bhnd_bus_read_2(r, offset); + return (0); case 4: - return (bhnd_bus_read_4(r, offset)); + *((uint32_t *)value) = bhnd_bus_read_4(r, offset); + return (0); default: - return (UINT32_MAX); + return (EINVAL); } } -static void -bcma_write_config(device_t dev, device_t child, bus_size_t offset, uint32_t val, - u_int width) +static int +bcma_write_config(device_t dev, device_t child, bus_size_t offset, + const void *value, u_int width) { struct bcma_devinfo *dinfo; struct bhnd_resource *r; /* Must be a directly attached child core */ if (device_get_parent(child) != dev) - return; + return (EINVAL); /* Fetch the agent registers */ dinfo = device_get_ivars(child); if ((r = dinfo->res_agent) == NULL) - return; + return (ENODEV); /* Verify bounds */ if (offset > rman_get_size(r->res)) - return; + return (EFAULT); if (rman_get_size(r->res) - offset < width) - return; + return (EFAULT); switch (width) { case 1: - bhnd_bus_write_1(r, offset, val); - break; + bhnd_bus_write_1(r, offset, *(const uint8_t *)value); + return (0); case 2: - bhnd_bus_write_2(r, offset, val); - break; + bhnd_bus_write_2(r, offset, *(const uint16_t *)value); + return (0); case 4: - bhnd_bus_write_4(r, offset, val); - break; + bhnd_bus_write_4(r, offset, *(const uint32_t *)value); + return (0); default: - break; + return (EINVAL); } } static u_int bcma_get_port_count(device_t dev, device_t child, bhnd_port_type type) { struct bcma_devinfo *dinfo; /* delegate non-bus-attached devices to our parent */ if (device_get_parent(child) != dev) return (BHND_BUS_GET_PORT_COUNT(device_get_parent(dev), child, type)); dinfo = device_get_ivars(child); switch (type) { case BHND_PORT_DEVICE: return (dinfo->corecfg->num_dev_ports); case BHND_PORT_BRIDGE: return (dinfo->corecfg->num_bridge_ports); case BHND_PORT_AGENT: return (dinfo->corecfg->num_wrapper_ports); default: device_printf(dev, "%s: unknown type (%d)\n", __func__, type); return (0); } } static u_int bcma_get_region_count(device_t dev, device_t child, bhnd_port_type type, u_int port_num) { struct bcma_devinfo *dinfo; struct bcma_sport_list *ports; struct bcma_sport *port; /* delegate non-bus-attached devices to our parent */ if (device_get_parent(child) != dev) return (BHND_BUS_GET_REGION_COUNT(device_get_parent(dev), child, type, port_num)); dinfo = device_get_ivars(child); ports = bcma_corecfg_get_port_list(dinfo->corecfg, type); STAILQ_FOREACH(port, ports, sp_link) { if (port->sp_num == port_num) return (port->sp_num_maps); } /* not found */ return (0); } static int bcma_get_port_rid(device_t dev, device_t child, bhnd_port_type port_type, u_int port_num, u_int region_num) { struct bcma_devinfo *dinfo; struct bcma_map *map; struct bcma_sport_list *ports; struct bcma_sport *port; dinfo = device_get_ivars(child); ports = bcma_corecfg_get_port_list(dinfo->corecfg, port_type); STAILQ_FOREACH(port, ports, sp_link) { if (port->sp_num != port_num) continue; STAILQ_FOREACH(map, &port->sp_maps, m_link) if (map->m_region_num == region_num) return map->m_rid; } return -1; } static int bcma_decode_port_rid(device_t dev, device_t child, int type, int rid, bhnd_port_type *port_type, u_int *port_num, u_int *region_num) { struct bcma_devinfo *dinfo; struct bcma_map *map; struct bcma_sport_list *ports; struct bcma_sport *port; dinfo = device_get_ivars(child); /* Ports are always memory mapped */ if (type != SYS_RES_MEMORY) return (EINVAL); /* Starting with the most likely device list, search all three port * lists */ bhnd_port_type types[] = { BHND_PORT_DEVICE, BHND_PORT_AGENT, BHND_PORT_BRIDGE }; for (int i = 0; i < nitems(types); i++) { ports = bcma_corecfg_get_port_list(dinfo->corecfg, types[i]); STAILQ_FOREACH(port, ports, sp_link) { STAILQ_FOREACH(map, &port->sp_maps, m_link) { if (map->m_rid != rid) continue; *port_type = port->sp_type; *port_num = port->sp_num; *region_num = map->m_region_num; return (0); } } } return (ENOENT); } static int bcma_get_region_addr(device_t dev, device_t child, bhnd_port_type port_type, u_int port_num, u_int region_num, bhnd_addr_t *addr, bhnd_size_t *size) { struct bcma_devinfo *dinfo; struct bcma_map *map; struct bcma_sport_list *ports; struct bcma_sport *port; dinfo = device_get_ivars(child); ports = bcma_corecfg_get_port_list(dinfo->corecfg, port_type); /* Search the port list */ STAILQ_FOREACH(port, ports, sp_link) { if (port->sp_num != port_num) continue; STAILQ_FOREACH(map, &port->sp_maps, m_link) { if (map->m_region_num != region_num) continue; /* Found! */ *addr = map->m_base; *size = map->m_size; return (0); } } return (ENOENT); } /** * Default bcma(4) bus driver implementation of BHND_BUS_GET_INTR_COUNT(). * * This implementation consults @p child's agent register block, * returning the number of interrupt output lines routed to @p child. */ int bcma_get_intr_count(device_t dev, device_t child) { struct bcma_devinfo *dinfo; uint32_t dmpcfg, oobw; dinfo = device_get_ivars(child); /* Agent block must be mapped */ if (dinfo->res_agent == NULL) return (0); /* Agent must support OOB */ dmpcfg = bhnd_bus_read_4(dinfo->res_agent, BCMA_DMP_CONFIG); if (!BCMA_DMP_GET_FLAG(dmpcfg, BCMA_DMP_CFG_OOB)) return (0); /* Return OOB width as interrupt count */ oobw = bhnd_bus_read_4(dinfo->res_agent, BCMA_DMP_OOB_OUTWIDTH(BCMA_OOB_BANK_INTR)); if (oobw > BCMA_OOB_NUM_SEL) { device_printf(dev, "ignoring invalid OOBOUTWIDTH for core %u: " "%#x\n", BCMA_DINFO_COREIDX(dinfo), oobw); return (0); } return (oobw); } /** * Default bcma(4) bus driver implementation of BHND_BUS_GET_CORE_IVEC(). * * This implementation consults @p child's agent register block, * returning the interrupt output line routed to @p child, at OOB selector * @p intr. */ int bcma_get_core_ivec(device_t dev, device_t child, u_int intr, uint32_t *ivec) { struct bcma_devinfo *dinfo; uint32_t oobsel; dinfo = device_get_ivars(child); /* Interrupt ID must be valid. */ if (intr >= bcma_get_intr_count(dev, child)) return (ENXIO); /* Fetch OOBSEL busline value */ KASSERT(dinfo->res_agent != NULL, ("missing agent registers")); oobsel = bhnd_bus_read_4(dinfo->res_agent, BCMA_DMP_OOBSELOUT( BCMA_OOB_BANK_INTR, intr)); *ivec = (oobsel >> BCMA_DMP_OOBSEL_SHIFT(intr)) & BCMA_DMP_OOBSEL_BUSLINE_MASK; return (0); } -static struct bhnd_devinfo * -bcma_alloc_bhnd_dinfo(device_t dev) -{ - struct bcma_devinfo *dinfo = bcma_alloc_dinfo(dev); - return ((struct bhnd_devinfo *)dinfo); -} - -static void -bcma_free_bhnd_dinfo(device_t dev, struct bhnd_devinfo *dinfo) -{ - bcma_free_dinfo(dev, (struct bcma_devinfo *)dinfo); -} - /** * Scan the device enumeration ROM table, adding all valid discovered cores to * the bus. * * @param bus The bcma bus. */ int bcma_add_children(device_t bus) { bhnd_erom_t *erom; struct bcma_erom *bcma_erom; const struct bhnd_chipid *cid; struct bcma_corecfg *corecfg; struct bcma_devinfo *dinfo; device_t child; int error; cid = BHND_BUS_GET_CHIPID(bus, bus); corecfg = NULL; /* Allocate our EROM parser */ erom = bhnd_erom_alloc(&bcma_erom_parser, cid, bus, BCMA_EROM_RID); if (erom == NULL) return (ENODEV); /* Add all cores. */ bcma_erom = (struct bcma_erom *)erom; while ((error = bcma_erom_next_corecfg(bcma_erom, &corecfg)) == 0) { int nintr; /* Add the child device */ child = BUS_ADD_CHILD(bus, 0, NULL, -1); if (child == NULL) { error = ENXIO; goto cleanup; } /* Initialize device ivars */ dinfo = device_get_ivars(child); if ((error = bcma_init_dinfo(bus, dinfo, corecfg))) goto cleanup; /* The dinfo instance now owns the corecfg value */ corecfg = NULL; /* Allocate device's agent registers, if any */ if ((error = bcma_dinfo_alloc_agent(bus, child, dinfo))) goto cleanup; /* Assign interrupts */ nintr = bhnd_get_intr_count(child); for (int rid = 0; rid < nintr; rid++) { error = BHND_BUS_ASSIGN_INTR(bus, child, rid); if (error) { device_printf(bus, "failed to assign interrupt " "%d to core %u: %d\n", rid, BCMA_DINFO_COREIDX(dinfo), error); } } /* If pins are floating or the hardware is otherwise * unpopulated, the device shouldn't be used. */ if (bhnd_is_hw_disabled(child)) device_disable(child); /* Issue bus callback for fully initialized child. */ BHND_BUS_CHILD_ADDED(bus, child); } /* EOF while parsing cores is expected */ if (error == ENOENT) error = 0; cleanup: bhnd_erom_free(erom); if (corecfg != NULL) bcma_free_corecfg(corecfg); if (error) device_delete_children(bus); return (error); } static device_method_t bcma_methods[] = { /* Device interface */ DEVMETHOD(device_probe, bcma_probe), DEVMETHOD(device_attach, bcma_attach), DEVMETHOD(device_detach, bcma_detach), /* Bus interface */ + DEVMETHOD(bus_add_child, bcma_add_child), + DEVMETHOD(bus_child_deleted, bcma_child_deleted), DEVMETHOD(bus_read_ivar, bcma_read_ivar), DEVMETHOD(bus_write_ivar, bcma_write_ivar), DEVMETHOD(bus_get_resource_list, bcma_get_resource_list), /* BHND interface */ DEVMETHOD(bhnd_bus_get_erom_class, bcma_get_erom_class), - DEVMETHOD(bhnd_bus_alloc_devinfo, bcma_alloc_bhnd_dinfo), - DEVMETHOD(bhnd_bus_free_devinfo, bcma_free_bhnd_dinfo), - DEVMETHOD(bhnd_bus_reset_core, bcma_reset_core), - DEVMETHOD(bhnd_bus_suspend_core, bcma_suspend_core), + DEVMETHOD(bhnd_bus_read_ioctl, bcma_read_ioctl), + DEVMETHOD(bhnd_bus_write_ioctl, bcma_write_ioctl), + DEVMETHOD(bhnd_bus_read_iost, bcma_read_iost), + DEVMETHOD(bhnd_bus_is_hw_suspended, bcma_is_hw_suspended), + DEVMETHOD(bhnd_bus_reset_hw, bcma_reset_hw), + DEVMETHOD(bhnd_bus_suspend_hw, bcma_suspend_hw), DEVMETHOD(bhnd_bus_read_config, bcma_read_config), DEVMETHOD(bhnd_bus_write_config, bcma_write_config), DEVMETHOD(bhnd_bus_get_port_count, bcma_get_port_count), DEVMETHOD(bhnd_bus_get_region_count, bcma_get_region_count), DEVMETHOD(bhnd_bus_get_port_rid, bcma_get_port_rid), DEVMETHOD(bhnd_bus_decode_port_rid, bcma_decode_port_rid), DEVMETHOD(bhnd_bus_get_region_addr, bcma_get_region_addr), DEVMETHOD(bhnd_bus_get_intr_count, bcma_get_intr_count), DEVMETHOD(bhnd_bus_get_core_ivec, bcma_get_core_ivec), DEVMETHOD_END }; DEFINE_CLASS_1(bhnd, bcma_driver, bcma_methods, sizeof(struct bcma_softc), bhnd_driver); MODULE_VERSION(bcma, 1); MODULE_DEPEND(bcma, bhnd, 1, 1, 1); Index: head/sys/dev/bhnd/bcma/bcma_dmp.h =================================================================== --- head/sys/dev/bhnd/bcma/bcma_dmp.h (revision 306286) +++ head/sys/dev/bhnd/bcma/bcma_dmp.h (revision 306287) @@ -1,259 +1,265 @@ /*- * Copyright (c) 2015 Landon Fuller * Copyright (c) 2010 Broadcom Corporation * * Portions of this file were derived from the aidmp.h header * distributed with Broadcom's initial brcm80211 Linux driver release, as * contributed to the Linux staging repository. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ #ifndef _BCMA_BCMA_DMP_H_ #define _BCMA_BCMA_DMP_H_ /* * PL-368 Device Management Plugin (DMP) Registers & Constants * * The "DMP" core used in Broadcom HND devices has been described * by Broadcom engineers (and in published header files) as being * ARM's PL-368 "Device Management Plugin" system IP, included with * the CoreLink AMBA Designer tooling. * * Documentation for the PL-368 is not publicly available, however, * and the only public reference by ARM to its existence appears to be * in the proprietary "NIC-301 Interconnect Device Management (PL368)" * errata publication, available to licensees as part of ARM's * CoreLink Controllers and Peripherals Engineering Errata. * * As such, the exact interpretation of these register definitions is * unconfirmed, and may be incorrect. */ #define BCMA_DMP_GET_FLAG(_value, _flag) \ (((_value) & _flag) != 0) #define BCMA_DMP_GET_BITS(_value, _field) \ ((_value & _field ## _MASK) >> _field ## _SHIFT) #define BHND_DMP_SET_BITS(_value, _field) \ (((_value) << _field ## _SHIFT) & _field ## _MASK) /* Out-of-band Router registers */ #define BCMA_OOB_BUSCONFIG 0x020 #define BCMA_OOB_STATUSA 0x100 #define BCMA_OOB_STATUSB 0x104 #define BCMA_OOB_STATUSC 0x108 #define BCMA_OOB_STATUSD 0x10c #define BCMA_OOB_ENABLEA0 0x200 #define BCMA_OOB_ENABLEA1 0x204 #define BCMA_OOB_ENABLEA2 0x208 #define BCMA_OOB_ENABLEA3 0x20c #define BCMA_OOB_ENABLEB0 0x280 #define BCMA_OOB_ENABLEB1 0x284 #define BCMA_OOB_ENABLEB2 0x288 #define BCMA_OOB_ENABLEB3 0x28c #define BCMA_OOB_ENABLEC0 0x300 #define BCMA_OOB_ENABLEC1 0x304 #define BCMA_OOB_ENABLEC2 0x308 #define BCMA_OOB_ENABLEC3 0x30c #define BCMA_OOB_ENABLED0 0x380 #define BCMA_OOB_ENABLED1 0x384 #define BCMA_OOB_ENABLED2 0x388 #define BCMA_OOB_ENABLED3 0x38c #define BCMA_OOB_ITCR 0xf00 #define BCMA_OOB_ITIPOOBA 0xf10 #define BCMA_OOB_ITIPOOBB 0xf14 #define BCMA_OOB_ITIPOOBC 0xf18 #define BCMA_OOB_ITIPOOBD 0xf1c #define BCMA_OOB_ITOPOOBA 0xf30 #define BCMA_OOB_ITOPOOBB 0xf34 #define BCMA_OOB_ITOPOOBC 0xf38 #define BCMA_OOB_ITOPOOBD 0xf3c /* Common definitions */ #define BCMA_OOB_NUM_BANKS 4 /**< number of OOB banks (A, B, C, D) */ #define BCMA_OOB_NUM_SEL 8 /**< number of OOB selectors per bank */ #define BCMA_OOB_NUM_BUSLINES 32 /**< number of bus lines managed by OOB core */ #define BCMA_OOB_BANKA 0 /**< bank A index */ #define BCMA_OOB_BANKB 1 /**< bank B index */ #define BCMA_OOB_BANKC 2 /**< bank C index */ #define BCMA_OOB_BANKD 3 /**< bank D index */ /** OOB bank used for interrupt lines */ #define BCMA_OOB_BANK_INTR BCMA_OOB_BANKA /* DMP agent registers */ #define BCMA_DMP_OOBSELINA30 0x000 /**< A0-A3 input selectors */ #define BCMA_DMP_OOBSELINA74 0x004 /**< A4-A7 input selectors */ #define BCMA_DMP_OOBSELINB30 0x020 /**< B0-B3 input selectors */ #define BCMA_DMP_OOBSELINB74 0x024 /**< B4-B7 input selectors */ #define BCMA_DMP_OOBSELINC30 0x040 /**< C0-C3 input selectors */ #define BCMA_DMP_OOBSELINC74 0x044 /**< C4-C7 input selectors */ #define BCMA_DMP_OOBSELIND30 0x060 /**< D0-D3 input selectors */ #define BCMA_DMP_OOBSELIND74 0x064 /**< D4-D7 input selectors */ #define BCMA_DMP_OOBSELOUTA30 0x100 /**< A0-A3 output selectors */ #define BCMA_DMP_OOBSELOUTA74 0x104 /**< A4-A7 output selectors */ #define BCMA_DMP_OOBSELOUTB30 0x120 /**< B0-B3 output selectors */ #define BCMA_DMP_OOBSELOUTB74 0x124 /**< B4-B7 output selectors */ #define BCMA_DMP_OOBSELOUTC30 0x140 /**< C0-C3 output selectors */ #define BCMA_DMP_OOBSELOUTC74 0x144 /**< C4-C7 output selectors */ #define BCMA_DMP_OOBSELOUTD30 0x160 /**< D0-D3 output selectors */ #define BCMA_DMP_OOBSELOUTD74 0x164 /**< D4-D7 output selectors */ #define BCMA_DMP_OOBSYNCA 0x200 #define BCMA_DMP_OOBSELOUTAEN 0x204 #define BCMA_DMP_OOBSYNCB 0x220 #define BCMA_DMP_OOBSELOUTBEN 0x224 #define BCMA_DMP_OOBSYNCC 0x240 #define BCMA_DMP_OOBSELOUTCEN 0x244 #define BCMA_DMP_OOBSYNCD 0x260 #define BCMA_DMP_OOBSELOUTDEN 0x264 #define BCMA_DMP_OOBAEXTWIDTH 0x300 #define BCMA_DMP_OOBAINWIDTH 0x304 #define BCMA_DMP_OOBAOUTWIDTH 0x308 #define BCMA_DMP_OOBBEXTWIDTH 0x320 #define BCMA_DMP_OOBBINWIDTH 0x324 #define BCMA_DMP_OOBBOUTWIDTH 0x328 #define BCMA_DMP_OOBCEXTWIDTH 0x340 #define BCMA_DMP_OOBCINWIDTH 0x344 #define BCMA_DMP_OOBCOUTWIDTH 0x348 #define BCMA_DMP_OOBDEXTWIDTH 0x360 #define BCMA_DMP_OOBDINWIDTH 0x364 #define BCMA_DMP_OOBDOUTWIDTH 0x368 #define BCMA_DMP_OOBSEL(_base, _bank, _sel) \ (_base + (_bank * 8) + (_sel >= 4 ? 4 : 0)) #define BCMA_DMP_OOBSELIN(_bank, _sel) \ BCMA_DMP_OOBSEL(BCMA_DMP_OOBSELINA30, _bank, _sel) #define BCMA_DMP_OOBSELOUT(_bank, _sel) \ BCMA_DMP_OOBSEL(BCMA_DMP_OOBSELOUTA30, _bank, _sel) #define BCMA_DMP_OOBSYNC(_bank) (BCMA_DMP_OOBSYNCA + (_bank * 8)) #define BCMA_DMP_OOBSELOUT_EN(_bank) (BCMA_DMP_OOBSELOUTAEN + (_bank * 8)) #define BCMA_DMP_OOB_EXTWIDTH(_bank) (BCMA_DMP_OOBAEXTWIDTH + (_bank * 12)) #define BCMA_DMP_OOB_INWIDTH(_bank) (BCMA_DMP_OOBAINWIDTH + (_bank * 12)) #define BCMA_DMP_OOB_OUTWIDTH(_bank) (BCMA_DMP_OOBAOUTWIDTH + (_bank * 12)) // This was inherited from Broadcom's aidmp.h header // Is it required for any of our use-cases? #if 0 /* defined(IL_BIGENDIAN) && defined(BCMHND74K) */ /* Selective swapped defines for those registers we need in * big-endian code. */ #define BCMA_DMP_IOCTRLSET 0x404 #define BCMA_DMP_IOCTRLCLEAR 0x400 #define BCMA_DMP_IOCTRL 0x40c #define BCMA_DMP_IOSTATUS 0x504 #define BCMA_DMP_RESETCTRL 0x804 #define BCMA_DMP_RESETSTATUS 0x800 #else /* !IL_BIGENDIAN || !BCMHND74K */ #define BCMA_DMP_IOCTRLSET 0x400 #define BCMA_DMP_IOCTRLCLEAR 0x404 #define BCMA_DMP_IOCTRL 0x408 #define BCMA_DMP_IOSTATUS 0x500 #define BCMA_DMP_RESETCTRL 0x800 #define BCMA_DMP_RESETSTATUS 0x804 #endif /* IL_BIGENDIAN && BCMHND74K */ #define BCMA_DMP_IOCTRLWIDTH 0x700 #define BCMA_DMP_IOSTATUSWIDTH 0x704 #define BCMA_DMP_RESETREADID 0x808 #define BCMA_DMP_RESETWRITEID 0x80c #define BCMA_DMP_ERRLOGCTRL 0xa00 #define BCMA_DMP_ERRLOGDONE 0xa04 #define BCMA_DMP_ERRLOGSTATUS 0xa08 #define BCMA_DMP_ERRLOGADDRLO 0xa0c #define BCMA_DMP_ERRLOGADDRHI 0xa10 #define BCMA_DMP_ERRLOGID 0xa14 #define BCMA_DMP_ERRLOGUSER 0xa18 #define BCMA_DMP_ERRLOGFLAGS 0xa1c #define BCMA_DMP_INTSTATUS 0xa00 #define BCMA_DMP_CONFIG 0xe00 #define BCMA_DMP_ITCR 0xf00 #define BCMA_DMP_ITIPOOBA 0xf10 #define BCMA_DMP_ITIPOOBB 0xf14 #define BCMA_DMP_ITIPOOBC 0xf18 #define BCMA_DMP_ITIPOOBD 0xf1c #define BCMA_DMP_ITIPOOBAOUT 0xf30 #define BCMA_DMP_ITIPOOBBOUT 0xf34 #define BCMA_DMP_ITIPOOBCOUT 0xf38 #define BCMA_DMP_ITIPOOBDOUT 0xf3c #define BCMA_DMP_ITOPOOBA 0xf50 #define BCMA_DMP_ITOPOOBB 0xf54 #define BCMA_DMP_ITOPOOBC 0xf58 #define BCMA_DMP_ITOPOOBD 0xf5c #define BCMA_DMP_ITOPOOBAIN 0xf70 #define BCMA_DMP_ITOPOOBBIN 0xf74 #define BCMA_DMP_ITOPOOBCIN 0xf78 #define BCMA_DMP_ITOPOOBDIN 0xf7c #define BCMA_DMP_ITOPRESET 0xf90 #define BCMA_DMP_PERIPHERIALID4 0xfd0 #define BCMA_DMP_PERIPHERIALID5 0xfd4 #define BCMA_DMP_PERIPHERIALID6 0xfd8 #define BCMA_DMP_PERIPHERIALID7 0xfdc #define BCMA_DMP_PERIPHERIALID0 0xfe0 #define BCMA_DMP_PERIPHERIALID1 0xfe4 #define BCMA_DMP_PERIPHERIALID2 0xfe8 #define BCMA_DMP_PERIPHERIALID3 0xfec #define BCMA_DMP_COMPONENTID0 0xff0 #define BCMA_DMP_COMPONENTID1 0xff4 #define BCMA_DMP_COMPONENTID2 0xff8 #define BCMA_DMP_COMPONENTID3 0xffc /* OOBSEL(IN|OUT) */ #define BCMA_DMP_OOBSEL_MASK 0xFF /**< OOB selector mask */ #define BCMA_DMP_OOBSEL_EN (1<<7) /**< OOB selector enable bit */ #define BCMA_DMP_OOBSEL_SHIFT(_sel) ((_sel % BCMA_OOB_NUM_SEL) * 8) #define BCMA_DMP_OOBSEL_BUSLINE_MASK 0x7F /**< OOB selector bus line mask */ #define BCMA_DMP_OOBSEL_BUSLINE_SHIFT 0 #define BCMA_DMP_OOBSEL_0_MASK BCMA_DMP_OOBSEL_MASK #define BCMA_DMP_OOBSEL_1_MASK BCMA_DMP_OOBSEL_MASK #define BCMA_DMP_OOBSEL_2_MASK BCMA_DMP_OOBSEL_MASK #define BCMA_DMP_OOBSEL_3_MASK BCMA_DMP_OOBSEL_MASK #define BCMA_DMP_OOBSEL_4_MASK BCMA_DMP_OOBSEL_MASK #define BCMA_DMP_OOBSEL_5_MASK BCMA_DMP_OOBSEL_MASK #define BCMA_DMP_OOBSEL_6_MASK BCMA_DMP_OOBSEL_MASK #define BCMA_DMP_OOBSEL_7_MASK BCMA_DMP_OOBSEL_MASK #define BCMA_DMP_OOBSEL_0_SHIFT BCMA_DMP_OOBSEL_SHIFT(0) #define BCMA_DMP_OOBSEL_1_SHIFT BCMA_DMP_OOBSEL_SHIFT(1) #define BCMA_DMP_OOBSEL_2_SHIFT BCMA_DMP_OOBSEL_SHIFT(2) #define BCMA_DMP_OOBSEL_3_SHIFT BCMA_DMP_OOBSEL_SHIFT(3) #define BCMA_DMP_OOBSEL_4_SHIFT BCMA_DMP_OOBSEL_0_SHIFT #define BCMA_DMP_OOBSEL_5_SHIFT BCMA_DMP_OOBSEL_1_SHIFT #define BCMA_DMP_OOBSEL_6_SHIFT BCMA_DMP_OOBSEL_2_SHIFT #define BCMA_DMP_OOBSEL_7_SHIFT BCMA_DMP_OOBSEL_3_SHIFT +/* ioctrl */ +#define BCMA_DMP_IOCTRL_MASK 0x0000FFFF + +/* iostatus */ +#define BCMA_DMP_IOST_MASK 0x0000FFFF + /* resetctrl */ -#define BMCA_DMP_RC_RESET 1 +#define BMCA_DMP_RC_RESET 0x00000001 /* config */ #define BCMA_DMP_CFG_OOB 0x00000020 #define BCMA_DMP_CFG_IOS 0x00000010 #define BCMA_DMP_CFGIOC 0x00000008 #define BCMA_DMP_CFGTO 0x00000004 #define BCMA_DMP_CFGERRL 0x00000002 #define BCMA_DMP_CFGRST 0x00000001 #endif /* _BCMA_BCMA_DMP_H_ */ Index: head/sys/dev/bhnd/bcma/bcma_subr.c =================================================================== --- head/sys/dev/bhnd/bcma/bcma_subr.c (revision 306286) +++ head/sys/dev/bhnd/bcma/bcma_subr.c (revision 306287) @@ -1,370 +1,431 @@ /*- * Copyright (c) 2015 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include +#include "bcma_dmp.h" + #include "bcmavar.h" /* Return the resource ID for a device's agent register allocation */ #define BCMA_AGENT_RID(_dinfo) \ (BCMA_AGENT_RID_BASE + BCMA_DINFO_COREIDX(_dinfo)) /** * Allocate and initialize new core config structure. * * @param core_index Core index on the bus. * @param core_unit Core unit number. * @param vendor Core designer. * @param device Core identifier (e.g. part number). * @param hwrev Core revision. */ struct bcma_corecfg * bcma_alloc_corecfg(u_int core_index, int core_unit, uint16_t vendor, uint16_t device, uint8_t hwrev) { struct bcma_corecfg *cfg; cfg = malloc(sizeof(*cfg), M_BHND, M_NOWAIT); if (cfg == NULL) return NULL; cfg->core_info = (struct bhnd_core_info) { .vendor = vendor, .device = device, .hwrev = hwrev, .core_idx = core_index, .unit = core_unit }; STAILQ_INIT(&cfg->master_ports); cfg->num_master_ports = 0; STAILQ_INIT(&cfg->dev_ports); cfg->num_dev_ports = 0; STAILQ_INIT(&cfg->bridge_ports); cfg->num_bridge_ports = 0; STAILQ_INIT(&cfg->wrapper_ports); cfg->num_wrapper_ports = 0; return (cfg); } /** * Deallocate the given core config and any associated resources. * * @param corecfg Core info to be deallocated. */ void bcma_free_corecfg(struct bcma_corecfg *corecfg) { struct bcma_mport *mport, *mnext; struct bcma_sport *sport, *snext; STAILQ_FOREACH_SAFE(mport, &corecfg->master_ports, mp_link, mnext) { free(mport, M_BHND); } STAILQ_FOREACH_SAFE(sport, &corecfg->dev_ports, sp_link, snext) { bcma_free_sport(sport); } STAILQ_FOREACH_SAFE(sport, &corecfg->bridge_ports, sp_link, snext) { bcma_free_sport(sport); } STAILQ_FOREACH_SAFE(sport, &corecfg->wrapper_ports, sp_link, snext) { bcma_free_sport(sport); } free(corecfg, M_BHND); } /** * Return the @p cfg port list for @p type. * * @param cfg The core configuration. * @param type The requested port type. */ struct bcma_sport_list * bcma_corecfg_get_port_list(struct bcma_corecfg *cfg, bhnd_port_type type) { switch (type) { case BHND_PORT_DEVICE: return (&cfg->dev_ports); break; case BHND_PORT_BRIDGE: return (&cfg->bridge_ports); break; case BHND_PORT_AGENT: return (&cfg->wrapper_ports); break; default: return (NULL); } } /** * Populate the resource list and bcma_map RIDs using the maps defined on * @p ports. * * @param bus The requesting bus device. * @param dinfo The device info instance to be initialized. * @param ports The set of ports to be enumerated */ static void bcma_dinfo_init_resource_info(device_t bus, struct bcma_devinfo *dinfo, struct bcma_sport_list *ports) { struct bcma_map *map; struct bcma_sport *port; bhnd_addr_t end; STAILQ_FOREACH(port, ports, sp_link) { STAILQ_FOREACH(map, &port->sp_maps, m_link) { /* * Create the corresponding device resource list entry. * * We necessarily skip registration if the region's * device memory range is not representable via * rman_res_t. * * When rman_res_t is migrated to uintmax_t, any * range should be representable. */ end = map->m_base + map->m_size; if (map->m_base <= RM_MAX_END && end <= RM_MAX_END) { map->m_rid = resource_list_add_next( &dinfo->resources, SYS_RES_MEMORY, map->m_base, end, map->m_size); } else if (bootverbose) { device_printf(bus, "core%u %s%u.%u: region %llx-%llx extends " "beyond supported addressable range\n", dinfo->corecfg->core_info.core_idx, bhnd_port_type_name(port->sp_type), port->sp_num, map->m_region_num, (unsigned long long) map->m_base, (unsigned long long) end); } } } } /** * Allocate and return a new empty device info structure. * * @param bus The requesting bus device. * * @retval NULL if allocation failed. */ struct bcma_devinfo * bcma_alloc_dinfo(device_t bus) { struct bcma_devinfo *dinfo; dinfo = malloc(sizeof(struct bcma_devinfo), M_BHND, M_NOWAIT|M_ZERO); if (dinfo == NULL) return (NULL); dinfo->corecfg = NULL; dinfo->res_agent = NULL; dinfo->rid_agent = -1; resource_list_init(&dinfo->resources); return (dinfo); } /** * Initialize a device info structure previously allocated via * bcma_alloc_dinfo, assuming ownership of the provided core * configuration. * * @param bus The requesting bus device. * @param dinfo The device info instance. * @param corecfg Device core configuration; ownership of this value * will be assumed by @p dinfo. * * @retval 0 success * @retval non-zero initialization failed. */ int bcma_init_dinfo(device_t bus, struct bcma_devinfo *dinfo, struct bcma_corecfg *corecfg) { KASSERT(dinfo->corecfg == NULL, ("dinfo previously initialized")); /* Save core configuration value */ dinfo->corecfg = corecfg; /* The device ports must always be initialized first to ensure that * rid 0 maps to the first device port */ bcma_dinfo_init_resource_info(bus, dinfo, &corecfg->dev_ports); bcma_dinfo_init_resource_info(bus, dinfo, &corecfg->bridge_ports); bcma_dinfo_init_resource_info(bus, dinfo, &corecfg->wrapper_ports); return (0); } /** * Allocate the per-core agent register block for a device info structure * previous initialized via bcma_init_dinfo(). * * If an agent0.0 region is not defined on @p dinfo, the device info * agent resource is set to NULL and 0 is returned. * * @param bus The requesting bus device. * @param child The bcma child device. * @param dinfo The device info associated with @p child * * @retval 0 success * @retval non-zero resource allocation failed. */ int bcma_dinfo_alloc_agent(device_t bus, device_t child, struct bcma_devinfo *dinfo) { bhnd_addr_t addr; bhnd_size_t size; rman_res_t r_start, r_count, r_end; int error; KASSERT(dinfo->res_agent == NULL, ("double allocation of agent")); /* Verify that the agent register block exists and is * mappable */ if (bhnd_get_port_rid(child, BHND_PORT_AGENT, 0, 0) == -1) return (0); /* nothing to do */ /* Fetch the address of the agent register block */ error = bhnd_get_region_addr(child, BHND_PORT_AGENT, 0, 0, &addr, &size); if (error) { device_printf(bus, "failed fetching agent register block " "address for core %u\n", BCMA_DINFO_COREIDX(dinfo)); return (error); } /* Allocate the resource */ r_start = addr; r_count = size; r_end = r_start + r_count - 1; dinfo->rid_agent = BCMA_AGENT_RID(dinfo); dinfo->res_agent = BHND_BUS_ALLOC_RESOURCE(bus, bus, SYS_RES_MEMORY, &dinfo->rid_agent, r_start, r_end, r_count, RF_ACTIVE); if (dinfo->res_agent == NULL) { device_printf(bus, "failed allocating agent register block for " "core %u\n", BCMA_DINFO_COREIDX(dinfo)); return (ENXIO); } return (0); } /** * Deallocate the given device info structure and any associated resources. * * @param bus The requesting bus device. * @param dinfo Device info to be deallocated. */ void bcma_free_dinfo(device_t bus, struct bcma_devinfo *dinfo) { resource_list_free(&dinfo->resources); if (dinfo->corecfg != NULL) bcma_free_corecfg(dinfo->corecfg); /* Release agent resource, if any */ if (dinfo->res_agent != NULL) { bhnd_release_resource(bus, SYS_RES_MEMORY, dinfo->rid_agent, dinfo->res_agent); } free(dinfo, M_BHND); } /** * Allocate and initialize new slave port descriptor. * * @param port_num Per-core port number. * @param port_type Port type. */ struct bcma_sport * bcma_alloc_sport(bcma_pid_t port_num, bhnd_port_type port_type) { struct bcma_sport *sport; sport = malloc(sizeof(struct bcma_sport), M_BHND, M_NOWAIT); if (sport == NULL) return NULL; sport->sp_num = port_num; sport->sp_type = port_type; sport->sp_num_maps = 0; STAILQ_INIT(&sport->sp_maps); return sport; } /** * Deallocate all resources associated with the given port descriptor. * * @param sport Port descriptor to be deallocated. */ void bcma_free_sport(struct bcma_sport *sport) { struct bcma_map *map, *mapnext; STAILQ_FOREACH_SAFE(map, &sport->sp_maps, m_link, mapnext) { free(map, M_BHND); } free(sport, M_BHND); } + +/** + * Given a bcma(4) child's device info, spin waiting for the device's DMP + * resetstatus register to clear. + * + * @param child The bcma(4) child device. + * @param dinfo The @p child device info. + * + * @retval 0 success + * @retval ENODEV if @p dinfo does not map an agent register resource. + * @retval ETIMEDOUT if timeout occurs + */ +int +bcma_dmp_wait_reset(device_t child, struct bcma_devinfo *dinfo) +{ + uint32_t rst; + + if (dinfo->res_agent == NULL) + return (ENODEV); + + /* 300us should be long enough, but there are references to this + * requiring up to 10ms when performing reset of an 80211 core + * after a MAC PSM microcode watchdog event. */ + for (int i = 0; i < 10000; i += 10) { + rst = bhnd_bus_read_4(dinfo->res_agent, BCMA_DMP_RESETSTATUS); + if (rst == 0) + return (0); + + DELAY(10); + } + + device_printf(child, "BCMA_DMP_RESETSTATUS timeout\n"); + return (ETIMEDOUT); +} + +/** + * Set the bcma(4) child's DMP resetctrl register value, and then wait + * for all backplane operations to complete. + * + * @param child The bcma(4) child device. + * @param dinfo The @p child device info. + * @param value The new ioctrl value to set. + * + * @retval 0 success + * @retval ENODEV if @p dinfo does not map an agent register resource. + * @retval ETIMEDOUT if timeout occurs waiting for reset completion + */ +int +bcma_dmp_write_reset(device_t child, struct bcma_devinfo *dinfo, uint32_t value) +{ + if (dinfo->res_agent == NULL) + return (ENODEV); + + bhnd_bus_write_4(dinfo->res_agent, BCMA_DMP_RESETCTRL, value); + bhnd_bus_read_4(dinfo->res_agent, BCMA_DMP_RESETCTRL); /* read-back */ + DELAY(10); + + return (bcma_dmp_wait_reset(child, dinfo)); +} Index: head/sys/dev/bhnd/bcma/bcmavar.h =================================================================== --- head/sys/dev/bhnd/bcma/bcmavar.h (revision 306286) +++ head/sys/dev/bhnd/bcma/bcmavar.h (revision 306287) @@ -1,169 +1,174 @@ /*- * Copyright (c) 2015 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. * * $FreeBSD$ */ #ifndef _BCMA_BCMAVAR_H_ #define _BCMA_BCMAVAR_H_ #include #include #include #include #include #include "bcma.h" /* * Internal definitions shared by bcma(4) driver implementations. */ /** Base resource ID for per-core agent register allocations */ #define BCMA_AGENT_RID_BASE 100 /** * Return the device's core index. * * @param _dinfo The bcma_devinfo instance to query. */ #define BCMA_DINFO_COREIDX(_dinfo) \ ((_dinfo)->corecfg->core_info.core_idx) /** BCMA port identifier. */ typedef u_int bcma_pid_t; #define BCMA_PID_MAX UINT_MAX /**< Maximum bcma_pid_t value */ /** BCMA per-port region map identifier. */ typedef u_int bcma_rmid_t; #define BCMA_RMID_MAX UINT_MAX /**< Maximum bcma_rmid_t value */ struct bcma_devinfo; struct bcma_corecfg; struct bcma_map; struct bcma_mport; struct bcma_sport; int bcma_probe(device_t dev); int bcma_attach(device_t dev); int bcma_detach(device_t dev); int bcma_get_intr_count(device_t dev, device_t child); int bcma_get_core_ivec(device_t dev, device_t child, u_int intr, uint32_t *ivec); int bcma_add_children(device_t bus); struct bcma_sport_list *bcma_corecfg_get_port_list(struct bcma_corecfg *cfg, bhnd_port_type type); struct bcma_devinfo *bcma_alloc_dinfo(device_t bus); int bcma_init_dinfo(device_t bus, struct bcma_devinfo *dinfo, struct bcma_corecfg *corecfg); int bcma_dinfo_alloc_agent(device_t bus, device_t child, struct bcma_devinfo *dinfo); void bcma_free_dinfo(device_t bus, struct bcma_devinfo *dinfo); struct bcma_corecfg *bcma_alloc_corecfg(u_int core_index, int core_unit, uint16_t vendor, uint16_t device, uint8_t hwrev); void bcma_free_corecfg(struct bcma_corecfg *corecfg); struct bcma_sport *bcma_alloc_sport(bcma_pid_t port_num, bhnd_port_type port_type); void bcma_free_sport(struct bcma_sport *sport); +int bcma_dmp_wait_reset(device_t child, + struct bcma_devinfo *dinfo); +int bcma_dmp_write_reset(device_t child, + struct bcma_devinfo *dinfo, uint32_t value); + /** BCMA master port descriptor */ struct bcma_mport { bcma_pid_t mp_num; /**< AXI port identifier (bus-unique) */ bcma_pid_t mp_vid; /**< AXI master virtual ID (core-unique) */ STAILQ_ENTRY(bcma_mport) mp_link; }; /** BCMA memory region descriptor */ struct bcma_map { bcma_rmid_t m_region_num; /**< region identifier (port-unique). */ bhnd_addr_t m_base; /**< base address */ bhnd_size_t m_size; /**< size */ int m_rid; /**< bus resource id, or -1. */ STAILQ_ENTRY(bcma_map) m_link; }; /** BCMA slave port descriptor */ struct bcma_sport { bcma_pid_t sp_num; /**< slave port number (core-unique) */ bhnd_port_type sp_type; /**< port type */ u_long sp_num_maps; /**< number of regions mapped to this port */ STAILQ_HEAD(, bcma_map) sp_maps; STAILQ_ENTRY(bcma_sport) sp_link; }; STAILQ_HEAD(bcma_mport_list, bcma_mport); STAILQ_HEAD(bcma_sport_list, bcma_sport); /** BCMA IP core/block configuration */ struct bcma_corecfg { struct bhnd_core_info core_info; /**< standard core info */ u_long num_master_ports; /**< number of master port descriptors. */ struct bcma_mport_list master_ports; /**< master port descriptors */ u_long num_dev_ports; /**< number of device slave port descriptors. */ struct bcma_sport_list dev_ports; /**< device port descriptors */ u_long num_bridge_ports; /**< number of bridge slave port descriptors. */ struct bcma_sport_list bridge_ports; /**< bridge port descriptors */ u_long num_wrapper_ports; /**< number of wrapper slave port descriptors. */ struct bcma_sport_list wrapper_ports; /**< wrapper port descriptors */ }; /** * BCMA per-device info */ struct bcma_devinfo { - struct bhnd_devinfo bhnd_dinfo; /**< superclass device info. */ + struct resource_list resources; /**< Slave port memory regions. */ + struct bcma_corecfg *corecfg; /**< IP core/block config */ - struct resource_list resources; /**< Slave port memory regions. */ - struct bcma_corecfg *corecfg; /**< IP core/block config */ + struct bhnd_resource *res_agent; /**< Agent (wrapper) resource, or NULL. Not + * all bcma(4) cores have or require an agent. */ + int rid_agent; /**< Agent resource ID, or -1 */ - struct bhnd_resource *res_agent; /**< Agent (wrapper) resource, or NULL. Not - * all bcma(4) cores have or require an agent. */ - int rid_agent; /**< Agent resource ID, or -1 */ + struct bhnd_core_pmu_info *pmu_info; /**< Bus-managed PMU state, or NULL */ }; /** BMCA per-instance state */ struct bcma_softc { struct bhnd_softc bhnd_sc; /**< bhnd state */ }; #endif /* _BCMA_BCMAVAR_H_ */ Index: head/sys/dev/bhnd/bhnd.c =================================================================== --- head/sys/dev/bhnd/bhnd.c (revision 306286) +++ head/sys/dev/bhnd/bhnd.c (revision 306287) @@ -1,1337 +1,1284 @@ /*- * Copyright (c) 2015-2016 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); /* * Broadcom Home Networking Division (HND) Bus Driver. * * The Broadcom HND family of devices consists of both SoCs and host-connected * networking chipsets containing a common family of Broadcom IP cores, * including an integrated MIPS and/or ARM cores. * * HND devices expose a nearly identical interface whether accessible over a * native SoC interconnect, or when connected via a host interface such as * PCIe. As a result, the majority of hardware support code should be re-usable * across host drivers for HND networking chipsets, as well as FreeBSD support * for Broadcom MIPS/ARM HND SoCs. * * Earlier HND models used the siba(4) on-chip interconnect, while later models * use bcma(4); the programming model is almost entirely independent * of the actual underlying interconect. */ #include #include #include #include #include #include #include #include #include #include #include #include "bhnd_chipc_if.h" #include "bhnd_nvram_if.h" #include "bhnd.h" #include "bhndvar.h" MALLOC_DEFINE(M_BHND, "bhnd", "bhnd bus data structures"); /* Bus pass at which all bus-required children must be available, and * attachment may be finalized. */ #define BHND_FINISH_ATTACH_PASS BUS_PASS_DEFAULT /** * bhnd_generic_probe_nomatch() reporting configuration. */ static const struct bhnd_nomatch { uint16_t vendor; /**< core designer */ uint16_t device; /**< core id */ bool if_verbose; /**< print when bootverbose is set. */ } bhnd_nomatch_table[] = { { BHND_MFGID_ARM, BHND_COREID_OOB_ROUTER, true }, { BHND_MFGID_ARM, BHND_COREID_EROM, true }, { BHND_MFGID_ARM, BHND_COREID_PL301, true }, { BHND_MFGID_ARM, BHND_COREID_APB_BRIDGE, true }, { BHND_MFGID_ARM, BHND_COREID_AXI_UNMAPPED, false }, { BHND_MFGID_INVALID, BHND_COREID_INVALID, false } }; static int bhnd_delete_children(struct bhnd_softc *sc); static int bhnd_finish_attach(struct bhnd_softc *sc); static device_t bhnd_find_chipc(struct bhnd_softc *sc); static struct chipc_caps *bhnd_find_chipc_caps(struct bhnd_softc *sc); static device_t bhnd_find_platform_dev(struct bhnd_softc *sc, const char *classname); static device_t bhnd_find_pmu(struct bhnd_softc *sc); static device_t bhnd_find_nvram(struct bhnd_softc *sc); static int compare_ascending_probe_order(const void *lhs, const void *rhs); static int compare_descending_probe_order(const void *lhs, const void *rhs); /** * Default bhnd(4) bus driver implementation of DEVICE_ATTACH(). * * This implementation calls device_probe_and_attach() for each of the device's * children, in bhnd probe order. */ int bhnd_generic_attach(device_t dev) { struct bhnd_softc *sc; device_t *devs; int ndevs; int error; if (device_is_attached(dev)) return (EBUSY); sc = device_get_softc(dev); sc->dev = dev; if ((error = device_get_children(dev, &devs, &ndevs))) return (error); /* Probe and attach all children */ qsort(devs, ndevs, sizeof(*devs), compare_ascending_probe_order); for (int i = 0; i < ndevs; i++) { device_t child = devs[i]; device_probe_and_attach(child); } /* Try to finalize attachment */ if (bus_current_pass >= BHND_FINISH_ATTACH_PASS) { if ((error = bhnd_finish_attach(sc))) goto cleanup; } cleanup: free(devs, M_TEMP); if (error) bhnd_delete_children(sc); return (error); } /** * Detach and delete all children, in reverse of their attach order. */ static int bhnd_delete_children(struct bhnd_softc *sc) { device_t *devs; int ndevs; int error; if ((error = device_get_children(sc->dev, &devs, &ndevs))) return (error); /* Detach in the reverse of attach order */ qsort(devs, ndevs, sizeof(*devs), compare_descending_probe_order); for (int i = 0; i < ndevs; i++) { device_t child = devs[i]; /* Terminate on first error */ if ((error = device_delete_child(sc->dev, child))) goto cleanup; } cleanup: free(devs, M_TEMP); return (error); } /** * Default bhnd(4) bus driver implementation of DEVICE_DETACH(). * * This implementation calls device_detach() for each of the device's * children, in reverse bhnd probe order, terminating if any call to * device_detach() fails. */ int bhnd_generic_detach(device_t dev) { struct bhnd_softc *sc; if (!device_is_attached(dev)) return (EBUSY); sc = device_get_softc(dev); return (bhnd_delete_children(sc)); } /** * Default bhnd(4) bus driver implementation of DEVICE_SHUTDOWN(). * * This implementation calls device_shutdown() for each of the device's * children, in reverse bhnd probe order, terminating if any call to * device_shutdown() fails. */ int bhnd_generic_shutdown(device_t dev) { device_t *devs; int ndevs; int error; if (!device_is_attached(dev)) return (EBUSY); if ((error = device_get_children(dev, &devs, &ndevs))) return (error); /* Shutdown in the reverse of attach order */ qsort(devs, ndevs, sizeof(*devs), compare_descending_probe_order); for (int i = 0; i < ndevs; i++) { device_t child = devs[i]; /* Terminate on first error */ if ((error = device_shutdown(child))) goto cleanup; } cleanup: free(devs, M_TEMP); return (error); } /** * Default bhnd(4) bus driver implementation of DEVICE_RESUME(). * * This implementation calls BUS_RESUME_CHILD() for each of the device's * children in bhnd probe order, terminating if any call to BUS_RESUME_CHILD() * fails. */ int bhnd_generic_resume(device_t dev) { device_t *devs; int ndevs; int error; if (!device_is_attached(dev)) return (EBUSY); if ((error = device_get_children(dev, &devs, &ndevs))) return (error); qsort(devs, ndevs, sizeof(*devs), compare_ascending_probe_order); for (int i = 0; i < ndevs; i++) { device_t child = devs[i]; /* Terminate on first error */ if ((error = BUS_RESUME_CHILD(device_get_parent(child), child))) goto cleanup; } cleanup: free(devs, M_TEMP); return (error); } /** * Default bhnd(4) bus driver implementation of DEVICE_SUSPEND(). * * This implementation calls BUS_SUSPEND_CHILD() for each of the device's * children in reverse bhnd probe order. If any call to BUS_SUSPEND_CHILD() * fails, the suspend operation is terminated and any devices that were * suspended are resumed immediately by calling their BUS_RESUME_CHILD() * methods. */ int bhnd_generic_suspend(device_t dev) { device_t *devs; int ndevs; int error; if (!device_is_attached(dev)) return (EBUSY); if ((error = device_get_children(dev, &devs, &ndevs))) return (error); /* Suspend in the reverse of attach order */ qsort(devs, ndevs, sizeof(*devs), compare_descending_probe_order); for (int i = 0; i < ndevs; i++) { device_t child = devs[i]; error = BUS_SUSPEND_CHILD(device_get_parent(child), child); /* On error, resume suspended devices and then terminate */ if (error) { for (int j = 0; j < i; j++) { BUS_RESUME_CHILD(device_get_parent(devs[j]), devs[j]); } goto cleanup; } } cleanup: free(devs, M_TEMP); return (error); } static void bhnd_new_pass(device_t dev) { struct bhnd_softc *sc; int error; sc = device_get_softc(dev); /* Attach any permissible children */ bus_generic_new_pass(dev); /* Finalize attachment */ if (!sc->attach_done && bus_current_pass >= BHND_FINISH_ATTACH_PASS) { if ((error = bhnd_finish_attach(sc))) { panic("bhnd_finish_attach() failed: %d", error); } } } /* * Finish any pending bus attachment operations. * * When attached as a SoC bus (as opposed to a bridged WiFi device), our * platform devices may not be attached until later bus passes, necessitating * delayed initialization on our part. */ static int bhnd_finish_attach(struct bhnd_softc *sc) { struct chipc_caps *ccaps; GIANT_REQUIRED; /* for newbus */ KASSERT(bus_current_pass >= BHND_FINISH_ATTACH_PASS, ("bhnd_finish_attach() called in pass %d", bus_current_pass)); KASSERT(!sc->attach_done, ("duplicate call to bhnd_finish_attach()")); /* Locate chipc device */ if ((sc->chipc_dev = bhnd_find_chipc(sc)) == NULL) { device_printf(sc->dev, "error: ChipCommon device not found\n"); return (ENXIO); } ccaps = BHND_CHIPC_GET_CAPS(sc->chipc_dev); /* Look for NVRAM device */ if (ccaps->nvram_src != BHND_NVRAM_SRC_UNKNOWN) { if ((sc->nvram_dev = bhnd_find_nvram(sc)) == NULL) { device_printf(sc->dev, "warning: NVRAM %s device not found\n", bhnd_nvram_src_name(ccaps->nvram_src)); } } /* Look for a PMU */ if (ccaps->pmu || ccaps->pwr_ctrl) { if ((sc->pmu_dev = bhnd_find_pmu(sc)) == NULL) { device_printf(sc->dev, "attach failed: supported PMU not found\n"); return (ENXIO); } } /* Mark attach as completed */ sc->attach_done = true; return (0); } /* Locate the ChipCommon core. */ static device_t bhnd_find_chipc(struct bhnd_softc *sc) { device_t chipc; /* Make sure we're holding Giant for newbus */ GIANT_REQUIRED; /* chipc_dev is initialized during attachment */ if (sc->attach_done) { if ((chipc = sc->chipc_dev) == NULL) return (NULL); goto found; } /* Locate chipc core with a core unit of 0 */ chipc = bhnd_find_child(sc->dev, BHND_DEVCLASS_CC, 0); if (chipc == NULL) return (NULL); found: if (device_get_state(chipc) < DS_ATTACHING) { device_printf(sc->dev, "chipc found, but did not attach\n"); return (NULL); } return (chipc); } /* Locate the ChipCommon core and return the device capabilities */ static struct chipc_caps * bhnd_find_chipc_caps(struct bhnd_softc *sc) { device_t chipc; if ((chipc = bhnd_find_chipc(sc)) == NULL) { device_printf(sc->dev, "chipc unavailable; cannot fetch capabilities\n"); return (NULL); } return (BHND_CHIPC_GET_CAPS(chipc)); } /** * Find an attached platform device on @p dev, searching first for cores * matching @p classname, and if not found, searching the children of the first * bhnd_chipc device on the bus. * * @param sc Driver state. * @param chipc Attached ChipCommon device. * @param classname Device class to search for. * * @retval device_t A matching device. * @retval NULL If no matching device is found. */ static device_t bhnd_find_platform_dev(struct bhnd_softc *sc, const char *classname) { device_t chipc, child; /* Make sure we're holding Giant for newbus */ GIANT_REQUIRED; /* Look for a directly-attached child */ child = device_find_child(sc->dev, classname, -1); if (child != NULL) goto found; /* Look for the first matching ChipCommon child */ if ((chipc = bhnd_find_chipc(sc)) == NULL) { device_printf(sc->dev, "chipc unavailable; cannot locate %s\n", classname); return (NULL); } child = device_find_child(chipc, classname, -1); if (child != NULL) goto found; /* Look for a parent-attached device (e.g. nexus0 -> bhnd_nvram) */ child = device_find_child(device_get_parent(sc->dev), classname, -1); if (child == NULL) return (NULL); found: if (device_get_state(child) < DS_ATTACHING) return (NULL); return (child); } /* Locate the PMU device, if any */ static device_t bhnd_find_pmu(struct bhnd_softc *sc) { /* Make sure we're holding Giant for newbus */ GIANT_REQUIRED; /* pmu_dev is initialized during attachment */ if (sc->attach_done) { if (sc->pmu_dev == NULL) return (NULL); if (device_get_state(sc->pmu_dev) < DS_ATTACHING) return (NULL); return (sc->pmu_dev); } return (bhnd_find_platform_dev(sc, "bhnd_pmu")); } /* Locate the NVRAM device, if any */ static device_t bhnd_find_nvram(struct bhnd_softc *sc) { struct chipc_caps *ccaps; /* Make sure we're holding Giant for newbus */ GIANT_REQUIRED; /* nvram_dev is initialized during attachment */ if (sc->attach_done) { if (sc->nvram_dev == NULL) return (NULL); if (device_get_state(sc->nvram_dev) < DS_ATTACHING) return (NULL); return (sc->nvram_dev); } if ((ccaps = bhnd_find_chipc_caps(sc)) == NULL) return (NULL); if (ccaps->nvram_src == BHND_NVRAM_SRC_UNKNOWN) return (NULL); return (bhnd_find_platform_dev(sc, "bhnd_nvram")); } /* * Ascending comparison of bhnd device's probe order. */ static int compare_ascending_probe_order(const void *lhs, const void *rhs) { device_t ldev, rdev; int lorder, rorder; ldev = (*(const device_t *) lhs); rdev = (*(const device_t *) rhs); lorder = BHND_BUS_GET_PROBE_ORDER(device_get_parent(ldev), ldev); rorder = BHND_BUS_GET_PROBE_ORDER(device_get_parent(rdev), rdev); if (lorder < rorder) { return (-1); } else if (lorder > rorder) { return (1); } else { return (0); } } /* * Descending comparison of bhnd device's probe order. */ static int compare_descending_probe_order(const void *lhs, const void *rhs) { return (compare_ascending_probe_order(rhs, lhs)); } /** * Default bhnd(4) bus driver implementation of BHND_BUS_GET_PROBE_ORDER(). * * This implementation determines probe ordering based on the device's class * and other properties, including whether the device is serving as a host * bridge. */ int bhnd_generic_get_probe_order(device_t dev, device_t child) { switch (bhnd_get_class(child)) { case BHND_DEVCLASS_CC: /* Must be early enough to provide NVRAM access to the * host bridge */ return (BHND_PROBE_ROOT + BHND_PROBE_ORDER_FIRST); case BHND_DEVCLASS_CC_B: /* fall through */ case BHND_DEVCLASS_PMU: return (BHND_PROBE_BUS + BHND_PROBE_ORDER_EARLY); case BHND_DEVCLASS_SOC_ROUTER: return (BHND_PROBE_BUS + BHND_PROBE_ORDER_LATE); case BHND_DEVCLASS_SOC_BRIDGE: return (BHND_PROBE_BUS + BHND_PROBE_ORDER_LAST); case BHND_DEVCLASS_CPU: return (BHND_PROBE_CPU + BHND_PROBE_ORDER_FIRST); case BHND_DEVCLASS_RAM: /* fall through */ case BHND_DEVCLASS_MEMC: return (BHND_PROBE_CPU + BHND_PROBE_ORDER_EARLY); case BHND_DEVCLASS_NVRAM: return (BHND_PROBE_RESOURCE + BHND_PROBE_ORDER_EARLY); case BHND_DEVCLASS_PCI: case BHND_DEVCLASS_PCIE: case BHND_DEVCLASS_PCCARD: case BHND_DEVCLASS_ENET: case BHND_DEVCLASS_ENET_MAC: case BHND_DEVCLASS_ENET_PHY: case BHND_DEVCLASS_WLAN: case BHND_DEVCLASS_WLAN_MAC: case BHND_DEVCLASS_WLAN_PHY: case BHND_DEVCLASS_EROM: case BHND_DEVCLASS_OTHER: case BHND_DEVCLASS_INVALID: if (bhnd_find_hostb_device(dev) == child) return (BHND_PROBE_ROOT + BHND_PROBE_ORDER_EARLY); return (BHND_PROBE_DEFAULT); default: return (BHND_PROBE_DEFAULT); } } /** * Default bhnd(4) bus driver implementation of BHND_BUS_ALLOC_PMU(). */ int bhnd_generic_alloc_pmu(device_t dev, device_t child) { struct bhnd_softc *sc; struct bhnd_resource *br; struct chipc_caps *ccaps; - struct bhnd_devinfo *dinfo; struct bhnd_core_pmu_info *pm; struct resource_list *rl; struct resource_list_entry *rle; device_t pmu_dev; bhnd_addr_t r_addr; bhnd_size_t r_size; bus_size_t pmu_regs; int error; GIANT_REQUIRED; /* for newbus */ sc = device_get_softc(dev); - dinfo = device_get_ivars(child); + pm = bhnd_get_pmu_info(child); pmu_regs = BHND_CLK_CTL_ST; if ((ccaps = bhnd_find_chipc_caps(sc)) == NULL) { device_printf(sc->dev, "alloc_pmu failed: chipc " "capabilities unavailable\n"); return (ENXIO); } if ((pmu_dev = bhnd_find_pmu(sc)) == NULL) { device_printf(sc->dev, "pmu unavailable; cannot allocate request state\n"); return (ENXIO); } /* already allocated? */ - if (dinfo->pmu_info != NULL) { + if (pm != NULL) { panic("duplicate PMU allocation for %s", device_get_nameunit(child)); } /* Determine address+size of the core's PMU register block */ error = bhnd_get_region_addr(child, BHND_PORT_DEVICE, 0, 0, &r_addr, &r_size); if (error) { device_printf(sc->dev, "error fetching register block info for " "%s: %d\n", device_get_nameunit(child), error); return (error); } if (r_size < (pmu_regs + sizeof(uint32_t))) { device_printf(sc->dev, "pmu offset %#jx would overrun %s " "register block\n", (uintmax_t)pmu_regs, device_get_nameunit(child)); return (ENODEV); } /* Locate actual resource containing the core's register block */ if ((rl = BUS_GET_RESOURCE_LIST(dev, child)) == NULL) { device_printf(dev, "NULL resource list returned for %s\n", device_get_nameunit(child)); return (ENXIO); } if ((rle = resource_list_find(rl, SYS_RES_MEMORY, 0)) == NULL) { device_printf(dev, "cannot locate core register resource " "for %s\n", device_get_nameunit(child)); return (ENXIO); } if (rle->res == NULL) { device_printf(dev, "core register resource unallocated for " "%s\n", device_get_nameunit(child)); return (ENXIO); } if (r_addr+pmu_regs < rman_get_start(rle->res) || r_addr+pmu_regs >= rman_get_end(rle->res)) { device_printf(dev, "core register resource does not map PMU " "registers at %#jx\n for %s\n", r_addr+pmu_regs, device_get_nameunit(child)); return (ENXIO); } /* Adjust PMU register offset relative to the actual start address * of the core's register block allocation. * * XXX: The saved offset will be invalid if bus_adjust_resource is * used to modify the resource's start address. */ if (rman_get_start(rle->res) > r_addr) pmu_regs -= rman_get_start(rle->res) - r_addr; else pmu_regs -= r_addr - rman_get_start(rle->res); /* Allocate and initialize PMU info */ br = malloc(sizeof(struct bhnd_resource), M_BHND, M_NOWAIT); if (br == NULL) return (ENOMEM); br->res = rle->res; br->direct = ((rman_get_flags(rle->res) & RF_ACTIVE) != 0); - pm = malloc(sizeof(*dinfo->pmu_info), M_BHND, M_NOWAIT); + pm = malloc(sizeof(*pm), M_BHND, M_NOWAIT); if (pm == NULL) { free(br, M_BHND); return (ENOMEM); } pm->pm_dev = child; pm->pm_pmu = pmu_dev; pm->pm_res = br; pm->pm_regs = pmu_regs; - dinfo->pmu_info = pm; + bhnd_set_pmu_info(child, pm); return (0); } /** * Default bhnd(4) bus driver implementation of BHND_BUS_RELEASE_PMU(). */ int bhnd_generic_release_pmu(device_t dev, device_t child) { struct bhnd_softc *sc; - struct bhnd_devinfo *dinfo; + struct bhnd_core_pmu_info *pm; device_t pmu; int error; GIANT_REQUIRED; /* for newbus */ sc = device_get_softc(dev); - dinfo = device_get_ivars(child); if ((pmu = bhnd_find_pmu(sc)) == NULL) { device_printf(sc->dev, "pmu unavailable; cannot release request state\n"); return (ENXIO); } /* dispatch release request */ - if (dinfo->pmu_info == NULL) + pm = bhnd_get_pmu_info(child); + if (pm == NULL) panic("pmu over-release for %s", device_get_nameunit(child)); - if ((error = BHND_PMU_CORE_RELEASE(pmu, dinfo->pmu_info))) + if ((error = BHND_PMU_CORE_RELEASE(pmu, pm))) return (error); /* free PMU info */ - free(dinfo->pmu_info->pm_res, M_BHND); - free(dinfo->pmu_info, M_BHND); - dinfo->pmu_info = NULL; + bhnd_set_pmu_info(child, NULL); + free(pm->pm_res, M_BHND); + free(pm, M_BHND); return (0); } /** * Default bhnd(4) bus driver implementation of BHND_BUS_REQUEST_CLOCK(). */ int bhnd_generic_request_clock(device_t dev, device_t child, bhnd_clock clock) { struct bhnd_softc *sc; - struct bhnd_devinfo *dinfo; struct bhnd_core_pmu_info *pm; sc = device_get_softc(dev); - dinfo = device_get_ivars(child); - if ((pm = dinfo->pmu_info) == NULL) + if ((pm = bhnd_get_pmu_info(child)) == NULL) panic("no active PMU request state"); /* dispatch request to PMU */ return (BHND_PMU_CORE_REQ_CLOCK(pm->pm_pmu, pm, clock)); } /** * Default bhnd(4) bus driver implementation of BHND_BUS_ENABLE_CLOCKS(). */ int bhnd_generic_enable_clocks(device_t dev, device_t child, uint32_t clocks) { struct bhnd_softc *sc; - struct bhnd_devinfo *dinfo; struct bhnd_core_pmu_info *pm; sc = device_get_softc(dev); - dinfo = device_get_ivars(child); - if ((pm = dinfo->pmu_info) == NULL) + if ((pm = bhnd_get_pmu_info(child)) == NULL) panic("no active PMU request state"); /* dispatch request to PMU */ return (BHND_PMU_CORE_EN_CLOCKS(pm->pm_pmu, pm, clocks)); } /** * Default bhnd(4) bus driver implementation of BHND_BUS_REQUEST_EXT_RSRC(). */ int bhnd_generic_request_ext_rsrc(device_t dev, device_t child, u_int rsrc) { struct bhnd_softc *sc; - struct bhnd_devinfo *dinfo; struct bhnd_core_pmu_info *pm; sc = device_get_softc(dev); - dinfo = device_get_ivars(child); - if ((pm = dinfo->pmu_info) == NULL) + if ((pm = bhnd_get_pmu_info(child)) == NULL) panic("no active PMU request state"); /* dispatch request to PMU */ return (BHND_PMU_CORE_REQ_EXT_RSRC(pm->pm_pmu, pm, rsrc)); } /** * Default bhnd(4) bus driver implementation of BHND_BUS_RELEASE_EXT_RSRC(). */ int bhnd_generic_release_ext_rsrc(device_t dev, device_t child, u_int rsrc) { struct bhnd_softc *sc; - struct bhnd_devinfo *dinfo; struct bhnd_core_pmu_info *pm; sc = device_get_softc(dev); - dinfo = device_get_ivars(child); - if ((pm = dinfo->pmu_info) == NULL) + if ((pm = bhnd_get_pmu_info(child)) == NULL) panic("no active PMU request state"); /* dispatch request to PMU */ return (BHND_PMU_CORE_RELEASE_EXT_RSRC(pm->pm_pmu, pm, rsrc)); } /** * Default bhnd(4) bus driver implementation of BHND_BUS_IS_REGION_VALID(). * * This implementation assumes that port and region numbers are 0-indexed and * are allocated non-sparsely, using BHND_BUS_GET_PORT_COUNT() and * BHND_BUS_GET_REGION_COUNT() to determine if @p port and @p region fall * within the defined range. */ static bool bhnd_generic_is_region_valid(device_t dev, device_t child, bhnd_port_type type, u_int port, u_int region) { if (port >= bhnd_get_port_count(child, type)) return (false); if (region >= bhnd_get_region_count(child, type, port)) return (false); return (true); } /** * Default bhnd(4) bus driver implementation of BHND_BUS_GET_NVRAM_VAR(). * * This implementation searches @p dev for a usable NVRAM child device. * * If no usable child device is found on @p dev, the request is delegated to * the BHND_BUS_GET_NVRAM_VAR() method on the parent of @p dev. */ int bhnd_generic_get_nvram_var(device_t dev, device_t child, const char *name, void *buf, size_t *size, bhnd_nvram_type type) { struct bhnd_softc *sc; device_t nvram, parent; sc = device_get_softc(dev); /* If a NVRAM device is available, consult it first */ if ((nvram = bhnd_find_nvram(sc)) != NULL) return BHND_NVRAM_GETVAR(nvram, name, buf, size, type); /* Otherwise, try to delegate to parent */ if ((parent = device_get_parent(dev)) == NULL) return (ENODEV); return (BHND_BUS_GET_NVRAM_VAR(device_get_parent(dev), child, name, buf, size, type)); } /** * Default bhnd(4) bus driver implementation of BUS_PRINT_CHILD(). * * This implementation requests the device's struct resource_list via * BUS_GET_RESOURCE_LIST. */ int bhnd_generic_print_child(device_t dev, device_t child) { struct resource_list *rl; int retval = 0; retval += bus_print_child_header(dev, child); rl = BUS_GET_RESOURCE_LIST(dev, child); if (rl != NULL) { retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%#jd"); } retval += printf(" at core %u", bhnd_get_core_index(child)); retval += bus_print_child_domain(dev, child); retval += bus_print_child_footer(dev, child); return (retval); } /** * Default bhnd(4) bus driver implementation of BUS_PROBE_NOMATCH(). * * This implementation requests the device's struct resource_list via * BUS_GET_RESOURCE_LIST. */ void bhnd_generic_probe_nomatch(device_t dev, device_t child) { struct resource_list *rl; const struct bhnd_nomatch *nm; bool report; /* Fetch reporting configuration for this device */ report = true; for (nm = bhnd_nomatch_table; nm->device != BHND_COREID_INVALID; nm++) { if (nm->vendor != bhnd_get_vendor(child)) continue; if (nm->device != bhnd_get_device(child)) continue; report = false; if (bootverbose && nm->if_verbose) report = true; break; } if (!report) return; /* Print the non-matched device info */ device_printf(dev, "<%s %s>", bhnd_get_vendor_name(child), bhnd_get_device_name(child)); rl = BUS_GET_RESOURCE_LIST(dev, child); if (rl != NULL) { resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%#jd"); } printf(" at core %u (no driver attached)\n", bhnd_get_core_index(child)); } /** * Default implementation of BUS_CHILD_PNPINFO_STR(). */ static int bhnd_child_pnpinfo_str(device_t dev, device_t child, char *buf, size_t buflen) { if (device_get_parent(child) != dev) { return (BUS_CHILD_PNPINFO_STR(device_get_parent(dev), child, buf, buflen)); } snprintf(buf, buflen, "vendor=0x%hx device=0x%hx rev=0x%hhx", bhnd_get_vendor(child), bhnd_get_device(child), bhnd_get_hwrev(child)); return (0); } /** * Default implementation of BUS_CHILD_LOCATION_STR(). */ static int bhnd_child_location_str(device_t dev, device_t child, char *buf, size_t buflen) { bhnd_addr_t addr; bhnd_size_t size; if (device_get_parent(child) != dev) { return (BUS_CHILD_LOCATION_STR(device_get_parent(dev), child, buf, buflen)); } if (bhnd_get_region_addr(child, BHND_PORT_DEVICE, 0, 0, &addr, &size)) { /* No device default port/region */ if (buflen > 0) *buf = '\0'; return (0); } snprintf(buf, buflen, "port0.0=0x%llx", (unsigned long long) addr); return (0); } /** - * Default bhnd(4) bus driver implementation of BUS_ADD_CHILD(). - * - * This implementation manages internal bhnd(4) state, and must be called - * by subclassing drivers. - */ -device_t -bhnd_generic_add_child(device_t dev, u_int order, const char *name, int unit) -{ - struct bhnd_devinfo *dinfo; - device_t child; - - child = device_add_child_ordered(dev, order, name, unit); - if (child == NULL) - return (NULL); - - if ((dinfo = BHND_BUS_ALLOC_DEVINFO(dev)) == NULL) { - device_delete_child(dev, child); - return (NULL); - } - - device_set_ivars(child, dinfo); - - return (child); -} - -/** - * Default bhnd(4) bus driver implementation of BHND_BUS_CHILD_ADDED(). - * - * This implementation manages internal bhnd(4) state, and must be called - * by subclassing drivers. - */ -void -bhnd_generic_child_added(device_t dev, device_t child) -{ -} - -/** * Default bhnd(4) bus driver implementation of BUS_CHILD_DELETED(). * * This implementation manages internal bhnd(4) state, and must be called * by subclassing drivers. */ void bhnd_generic_child_deleted(device_t dev, device_t child) { struct bhnd_softc *sc; - struct bhnd_devinfo *dinfo; sc = device_get_softc(dev); /* Free device info */ - if ((dinfo = device_get_ivars(child)) != NULL) { - if (dinfo->pmu_info != NULL) { - /* Releasing PMU requests automatically would be nice, - * but we can't reference per-core PMU register - * resource after driver detach */ - panic("%s leaked device pmu state\n", - device_get_nameunit(child)); - } - - BHND_BUS_FREE_DEVINFO(dev, dinfo); + if (bhnd_get_pmu_info(child) != NULL) { + /* Releasing PMU requests automatically would be nice, + * but we can't reference per-core PMU register + * resource after driver detach */ + panic("%s leaked device pmu state\n", + device_get_nameunit(child)); } /* Clean up platform device references */ if (sc->chipc_dev == child) { sc->chipc_dev = NULL; } else if (sc->nvram_dev == child) { sc->nvram_dev = NULL; } else if (sc->pmu_dev == child) { sc->pmu_dev = NULL; } } /** * Helper function for implementing BUS_SUSPEND_CHILD(). * * TODO: Power management * * If @p child is not a direct child of @p dev, suspension is delegated to * the @p dev parent. */ int bhnd_generic_suspend_child(device_t dev, device_t child) { if (device_get_parent(child) != dev) BUS_SUSPEND_CHILD(device_get_parent(dev), child); return bus_generic_suspend_child(dev, child); } /** * Helper function for implementing BUS_RESUME_CHILD(). * * TODO: Power management * * If @p child is not a direct child of @p dev, suspension is delegated to * the @p dev parent. */ int bhnd_generic_resume_child(device_t dev, device_t child) { if (device_get_parent(child) != dev) BUS_RESUME_CHILD(device_get_parent(dev), child); return bus_generic_resume_child(dev, child); } /* * Delegate all indirect I/O to the parent device. When inherited by * non-bridged bus implementations, resources will never be marked as * indirect, and these methods will never be called. */ #define BHND_IO_READ(_type, _name, _method) \ static _type \ bhnd_read_ ## _name (device_t dev, device_t child, \ struct bhnd_resource *r, bus_size_t offset) \ { \ return (BHND_BUS_READ_ ## _method( \ device_get_parent(dev), child, r, offset)); \ } #define BHND_IO_WRITE(_type, _name, _method) \ static void \ bhnd_write_ ## _name (device_t dev, device_t child, \ struct bhnd_resource *r, bus_size_t offset, _type value) \ { \ return (BHND_BUS_WRITE_ ## _method( \ device_get_parent(dev), child, r, offset, \ value)); \ } #define BHND_IO_MISC(_type, _op, _method) \ static void \ bhnd_ ## _op (device_t dev, device_t child, \ struct bhnd_resource *r, bus_size_t offset, _type datap, \ bus_size_t count) \ { \ BHND_BUS_ ## _method(device_get_parent(dev), child, r, \ offset, datap, count); \ } #define BHND_IO_METHODS(_type, _size) \ BHND_IO_READ(_type, _size, _size) \ BHND_IO_WRITE(_type, _size, _size) \ \ BHND_IO_READ(_type, stream_ ## _size, STREAM_ ## _size) \ BHND_IO_WRITE(_type, stream_ ## _size, STREAM_ ## _size) \ \ BHND_IO_MISC(_type*, read_multi_ ## _size, \ READ_MULTI_ ## _size) \ BHND_IO_MISC(_type*, write_multi_ ## _size, \ WRITE_MULTI_ ## _size) \ \ BHND_IO_MISC(_type*, read_multi_stream_ ## _size, \ READ_MULTI_STREAM_ ## _size) \ BHND_IO_MISC(_type*, write_multi_stream_ ## _size, \ WRITE_MULTI_STREAM_ ## _size) \ \ BHND_IO_MISC(_type, set_multi_ ## _size, SET_MULTI_ ## _size) \ BHND_IO_MISC(_type, set_region_ ## _size, SET_REGION_ ## _size) \ \ BHND_IO_MISC(_type*, read_region_ ## _size, \ READ_REGION_ ## _size) \ BHND_IO_MISC(_type*, write_region_ ## _size, \ WRITE_REGION_ ## _size) \ \ BHND_IO_MISC(_type*, read_region_stream_ ## _size, \ READ_REGION_STREAM_ ## _size) \ BHND_IO_MISC(_type*, write_region_stream_ ## _size, \ WRITE_REGION_STREAM_ ## _size) \ BHND_IO_METHODS(uint8_t, 1); BHND_IO_METHODS(uint16_t, 2); BHND_IO_METHODS(uint32_t, 4); static void bhnd_barrier(device_t dev, device_t child, struct bhnd_resource *r, bus_size_t offset, bus_size_t length, int flags) { BHND_BUS_BARRIER(device_get_parent(dev), child, r, offset, length, flags); } static device_method_t bhnd_methods[] = { /* Device interface */ \ DEVMETHOD(device_attach, bhnd_generic_attach), DEVMETHOD(device_detach, bhnd_generic_detach), DEVMETHOD(device_shutdown, bhnd_generic_shutdown), DEVMETHOD(device_suspend, bhnd_generic_suspend), DEVMETHOD(device_resume, bhnd_generic_resume), /* Bus interface */ DEVMETHOD(bus_new_pass, bhnd_new_pass), - DEVMETHOD(bus_add_child, bhnd_generic_add_child), DEVMETHOD(bus_child_deleted, bhnd_generic_child_deleted), DEVMETHOD(bus_probe_nomatch, bhnd_generic_probe_nomatch), DEVMETHOD(bus_print_child, bhnd_generic_print_child), DEVMETHOD(bus_child_pnpinfo_str, bhnd_child_pnpinfo_str), DEVMETHOD(bus_child_location_str, bhnd_child_location_str), DEVMETHOD(bus_suspend_child, bhnd_generic_suspend_child), DEVMETHOD(bus_resume_child, bhnd_generic_resume_child), DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), DEVMETHOD(bus_config_intr, bus_generic_config_intr), DEVMETHOD(bus_bind_intr, bus_generic_bind_intr), DEVMETHOD(bus_describe_intr, bus_generic_describe_intr), DEVMETHOD(bus_get_dma_tag, bus_generic_get_dma_tag), /* BHND interface */ DEVMETHOD(bhnd_bus_get_chipid, bhnd_bus_generic_get_chipid), DEVMETHOD(bhnd_bus_is_hw_disabled, bhnd_bus_generic_is_hw_disabled), DEVMETHOD(bhnd_bus_read_board_info, bhnd_bus_generic_read_board_info), DEVMETHOD(bhnd_bus_get_probe_order, bhnd_generic_get_probe_order), DEVMETHOD(bhnd_bus_alloc_pmu, bhnd_generic_alloc_pmu), DEVMETHOD(bhnd_bus_release_pmu, bhnd_generic_release_pmu), DEVMETHOD(bhnd_bus_request_clock, bhnd_generic_request_clock), DEVMETHOD(bhnd_bus_enable_clocks, bhnd_generic_enable_clocks), DEVMETHOD(bhnd_bus_request_ext_rsrc, bhnd_generic_request_ext_rsrc), DEVMETHOD(bhnd_bus_release_ext_rsrc, bhnd_generic_release_ext_rsrc), - DEVMETHOD(bhnd_bus_child_added, bhnd_generic_child_added), DEVMETHOD(bhnd_bus_is_region_valid, bhnd_generic_is_region_valid), DEVMETHOD(bhnd_bus_get_nvram_var, bhnd_generic_get_nvram_var), /* BHND interface (bus I/O) */ DEVMETHOD(bhnd_bus_read_1, bhnd_read_1), DEVMETHOD(bhnd_bus_read_2, bhnd_read_2), DEVMETHOD(bhnd_bus_read_4, bhnd_read_4), DEVMETHOD(bhnd_bus_write_1, bhnd_write_1), DEVMETHOD(bhnd_bus_write_2, bhnd_write_2), DEVMETHOD(bhnd_bus_write_4, bhnd_write_4), DEVMETHOD(bhnd_bus_read_stream_1, bhnd_read_stream_1), DEVMETHOD(bhnd_bus_read_stream_2, bhnd_read_stream_2), DEVMETHOD(bhnd_bus_read_stream_4, bhnd_read_stream_4), DEVMETHOD(bhnd_bus_write_stream_1, bhnd_write_stream_1), DEVMETHOD(bhnd_bus_write_stream_2, bhnd_write_stream_2), DEVMETHOD(bhnd_bus_write_stream_4, bhnd_write_stream_4), DEVMETHOD(bhnd_bus_read_multi_1, bhnd_read_multi_1), DEVMETHOD(bhnd_bus_read_multi_2, bhnd_read_multi_2), DEVMETHOD(bhnd_bus_read_multi_4, bhnd_read_multi_4), DEVMETHOD(bhnd_bus_write_multi_1, bhnd_write_multi_1), DEVMETHOD(bhnd_bus_write_multi_2, bhnd_write_multi_2), DEVMETHOD(bhnd_bus_write_multi_4, bhnd_write_multi_4), DEVMETHOD(bhnd_bus_read_multi_stream_1, bhnd_read_multi_stream_1), DEVMETHOD(bhnd_bus_read_multi_stream_2, bhnd_read_multi_stream_2), DEVMETHOD(bhnd_bus_read_multi_stream_4, bhnd_read_multi_stream_4), DEVMETHOD(bhnd_bus_write_multi_stream_1,bhnd_write_multi_stream_1), DEVMETHOD(bhnd_bus_write_multi_stream_2,bhnd_write_multi_stream_2), DEVMETHOD(bhnd_bus_write_multi_stream_4,bhnd_write_multi_stream_4), DEVMETHOD(bhnd_bus_set_multi_1, bhnd_set_multi_1), DEVMETHOD(bhnd_bus_set_multi_2, bhnd_set_multi_2), DEVMETHOD(bhnd_bus_set_multi_4, bhnd_set_multi_4), DEVMETHOD(bhnd_bus_set_region_1, bhnd_set_region_1), DEVMETHOD(bhnd_bus_set_region_2, bhnd_set_region_2), DEVMETHOD(bhnd_bus_set_region_4, bhnd_set_region_4), DEVMETHOD(bhnd_bus_read_region_1, bhnd_read_region_1), DEVMETHOD(bhnd_bus_read_region_2, bhnd_read_region_2), DEVMETHOD(bhnd_bus_read_region_4, bhnd_read_region_4), DEVMETHOD(bhnd_bus_write_region_1, bhnd_write_region_1), DEVMETHOD(bhnd_bus_write_region_2, bhnd_write_region_2), DEVMETHOD(bhnd_bus_write_region_4, bhnd_write_region_4), DEVMETHOD(bhnd_bus_read_region_stream_1,bhnd_read_region_stream_1), DEVMETHOD(bhnd_bus_read_region_stream_2,bhnd_read_region_stream_2), DEVMETHOD(bhnd_bus_read_region_stream_4,bhnd_read_region_stream_4), DEVMETHOD(bhnd_bus_write_region_stream_1, bhnd_write_region_stream_1), DEVMETHOD(bhnd_bus_write_region_stream_2, bhnd_write_region_stream_2), DEVMETHOD(bhnd_bus_write_region_stream_4, bhnd_write_region_stream_4), DEVMETHOD(bhnd_bus_barrier, bhnd_barrier), DEVMETHOD_END }; devclass_t bhnd_devclass; /**< bhnd bus. */ devclass_t bhnd_hostb_devclass; /**< bhnd bus host bridge. */ devclass_t bhnd_nvram_devclass; /**< bhnd NVRAM device */ DEFINE_CLASS_0(bhnd, bhnd_driver, bhnd_methods, sizeof(struct bhnd_softc)); MODULE_VERSION(bhnd, 1); Index: head/sys/dev/bhnd/bhnd.h =================================================================== --- head/sys/dev/bhnd/bhnd.h (revision 306286) +++ head/sys/dev/bhnd/bhnd.h (revision 306287) @@ -1,1265 +1,1438 @@ /*- * Copyright (c) 2015 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. * * $FreeBSD$ */ #ifndef _BHND_BHND_H_ #define _BHND_BHND_H_ #include #include #include #include "bhnd_ids.h" #include "bhnd_types.h" #include "bhnd_erom_types.h" #include "bhnd_debug.h" #include "bhnd_bus_if.h" #include "bhnd_match.h" #include "nvram/bhnd_nvram.h" +struct bhnd_core_pmu_info; + extern devclass_t bhnd_devclass; extern devclass_t bhnd_hostb_devclass; extern devclass_t bhnd_nvram_devclass; #define BHND_CHIPID_MAX_NAMELEN 32 /**< maximum buffer required for a bhnd_format_chip_id() */ /** * bhnd child instance variables */ enum bhnd_device_vars { BHND_IVAR_VENDOR, /**< Designer's JEP-106 manufacturer ID. */ BHND_IVAR_DEVICE, /**< Part number */ BHND_IVAR_HWREV, /**< Core revision */ BHND_IVAR_DEVICE_CLASS, /**< Core class (@sa bhnd_devclass_t) */ BHND_IVAR_VENDOR_NAME, /**< Core vendor name */ BHND_IVAR_DEVICE_NAME, /**< Core name */ BHND_IVAR_CORE_INDEX, /**< Bus-assigned core number */ BHND_IVAR_CORE_UNIT, /**< Bus-assigned core unit number, assigned sequentially (starting at 0) for each vendor/device pair. */ + BHND_IVAR_PMU_INFO, /**< Internal bus-managed PMU state */ }; /** * bhnd device probe priority bands. */ enum { BHND_PROBE_ROOT = 0, /**< Nexus or host bridge */ BHND_PROBE_BUS = 1000, /**< Busses and bridges */ BHND_PROBE_CPU = 2000, /**< CPU devices */ BHND_PROBE_INTERRUPT = 3000, /**< Interrupt controllers. */ BHND_PROBE_TIMER = 4000, /**< Timers and clocks. */ BHND_PROBE_RESOURCE = 5000, /**< Resource discovery (including NVRAM/SPROM) */ BHND_PROBE_DEFAULT = 6000, /**< Default device priority */ }; /** * Constants defining fine grained ordering within a BHND_PROBE_* priority band. * * Example: * @code * BHND_PROBE_BUS + BHND_PROBE_ORDER_FIRST * @endcode */ enum { BHND_PROBE_ORDER_FIRST = 0, BHND_PROBE_ORDER_EARLY = 25, BHND_PROBE_ORDER_MIDDLE = 50, BHND_PROBE_ORDER_LATE = 75, BHND_PROBE_ORDER_LAST = 100 }; + +/** + * Per-core IOCTL flags common to all bhnd(4) cores. + */ +enum { + BHND_IOCTL_BIST = 0x8000, /**< Initiate a built-in self-test (BIST). Must be cleared + after BIST results are read via BHND_IOST_BIST_* */ + BHND_IOCTL_PME = 0x4000, /**< Enable posting of power management events by the core. */ + BHND_IOCTL_CFLAGS = 0x3FFC, /**< Reserved for core-specific ioctl flags. */ + BHND_IOCTL_CLK_FORCE = 0x0002, /**< Force disable of clock gating, resulting in all clocks + being distributed within the core. Should be set when + asserting/deasserting reset to ensure the reset signal + fully propagates to the entire core. */ + BHND_IOCTL_CLK_EN = 0x0001, /**< If cleared, the core clock will be disabled. Should be + set during normal operation, and cleared when the core is + held in reset. */ +}; + +/** + * Per-core IOST flags common to all bhnd(4) cores. + */ +enum { + BHND_IOST_BIST_DONE = 0x8000, /**< Set upon BIST completion (see BHND_IOCTL_BIST), and cleared + if 0 is written to BHND_IOCTL_BIST. */ + BHND_IOST_BIST_FAIL = 0x4000, /**< Set upon detection of a BIST error; the value is unspecified + if BIST has not completed and BHND_IOST_BIST_DONE is not set. */ + BHND_IOST_CLK = 0x2000, /**< Set if the core has requested that gated clocks be enabled, or + cleared otherwise. The value is undefined if a core does not + support clock gating. */ + BHND_IOST_DMA64 = 0x1000, /**< Set if this core supports 64-bit DMA */ + BHND_IOST_CFLAGS = 0x0FFC, /**< Reserved for core-specific status flags. */ +}; + /* * Simplified accessors for bhnd device ivars */ #define BHND_ACCESSOR(var, ivar, type) \ __BUS_ACCESSOR(bhnd, var, BHND, ivar, type) BHND_ACCESSOR(vendor, VENDOR, uint16_t); BHND_ACCESSOR(device, DEVICE, uint16_t); BHND_ACCESSOR(hwrev, HWREV, uint8_t); BHND_ACCESSOR(class, DEVICE_CLASS, bhnd_devclass_t); BHND_ACCESSOR(vendor_name, VENDOR_NAME, const char *); BHND_ACCESSOR(device_name, DEVICE_NAME, const char *); BHND_ACCESSOR(core_index, CORE_INDEX, u_int); BHND_ACCESSOR(core_unit, CORE_UNIT, int); +BHND_ACCESSOR(pmu_info, PMU_INFO, struct bhnd_core_pmu_info *); #undef BHND_ACCESSOR /** * A bhnd(4) board descriptor. */ struct bhnd_board_info { uint16_t board_vendor; /**< PCI-SIG vendor ID (even on non-PCI * devices). * * On PCI devices, this will generally * be the subsystem vendor ID, but the * value may be overridden in device * NVRAM. */ uint16_t board_type; /**< Board type (See BHND_BOARD_*) * * On PCI devices, this will generally * be the subsystem device ID, but the * value may be overridden in device * NVRAM. */ uint16_t board_rev; /**< Board revision. */ uint8_t board_srom_rev; /**< Board SROM format revision */ uint32_t board_flags; /**< Board flags (see BHND_BFL_*) */ uint32_t board_flags2; /**< Board flags 2 (see BHND_BFL2_*) */ uint32_t board_flags3; /**< Board flags 3 (see BHND_BFL3_*) */ }; /** * Chip Identification * * This is read from the ChipCommon ID register; on earlier bhnd(4) devices * where ChipCommon is unavailable, known values must be supplied. */ struct bhnd_chipid { uint16_t chip_id; /**< chip id (BHND_CHIPID_*) */ uint8_t chip_rev; /**< chip revision */ uint8_t chip_pkg; /**< chip package (BHND_PKGID_*) */ uint8_t chip_type; /**< chip type (BHND_CHIPTYPE_*) */ bhnd_addr_t enum_addr; /**< chip_type-specific enumeration * address; either the siba(4) base * core register block, or the bcma(4) * EROM core address. */ uint8_t ncores; /**< number of cores, if known. 0 if * not available. */ }; /** * A bhnd(4) core descriptor. */ struct bhnd_core_info { uint16_t vendor; /**< JEP-106 vendor (BHND_MFGID_*) */ uint16_t device; /**< device */ uint16_t hwrev; /**< hardware revision */ u_int core_idx; /**< bus-assigned core index */ int unit; /**< bus-assigned core unit */ }; /** * A bhnd(4) bus resource. * * This provides an abstract interface to per-core resources that may require * bus-level remapping of address windows prior to access. */ struct bhnd_resource { struct resource *res; /**< the system resource. */ bool direct; /**< false if the resource requires * bus window remapping before it * is MMIO accessible. */ }; /** Wrap the active resource @p _r in a bhnd_resource structure */ #define BHND_DIRECT_RESOURCE(_r) ((struct bhnd_resource) { \ .res = (_r), \ .direct = true, \ }) /** * Device quirk table descriptor. */ struct bhnd_device_quirk { struct bhnd_device_match desc; /**< device match descriptor */ uint32_t quirks; /**< quirk flags */ }; #define BHND_CORE_QUIRK(_rev, _flags) \ {{ BHND_MATCH_CORE_REV(_rev) }, (_flags) } #define BHND_CHIP_QUIRK(_chip, _rev, _flags) \ {{ BHND_CHIP_IR(BCM ## _chip, _rev) }, (_flags) } #define BHND_PKG_QUIRK(_chip, _pkg, _flags) \ {{ BHND_CHIP_IP(BCM ## _chip, BCM ## _chip ## _pkg) }, (_flags) } #define BHND_BOARD_QUIRK(_board, _flags) \ {{ BHND_MATCH_BOARD_TYPE(_board) }, \ (_flags) } #define BHND_DEVICE_QUIRK_END { { BHND_MATCH_ANY }, 0 } #define BHND_DEVICE_QUIRK_IS_END(_q) \ (((_q)->desc.m.match_flags == 0) && (_q)->quirks == 0) enum { BHND_DF_ANY = 0, BHND_DF_HOSTB = (1<<0), /**< core is serving as the bus' host * bridge. implies BHND_DF_ADAPTER */ BHND_DF_SOC = (1<<1), /**< core is attached to a native bus (BHND_ATTACH_NATIVE) */ BHND_DF_ADAPTER = (1<<2), /**< core is attached to a bridged * adapter (BHND_ATTACH_ADAPTER) */ }; /** Device probe table descriptor */ struct bhnd_device { const struct bhnd_device_match core; /**< core match descriptor */ const char *desc; /**< device description, or NULL. */ const struct bhnd_device_quirk *quirks_table; /**< quirks table for this device, or NULL */ uint32_t device_flags; /**< required BHND_DF_* flags */ }; #define _BHND_DEVICE(_vendor, _device, _desc, _quirks, \ _flags, ...) \ { { BHND_MATCH_CORE(BHND_MFGID_ ## _vendor, \ BHND_COREID_ ## _device) }, _desc, _quirks, \ _flags } #define BHND_DEVICE(_vendor, _device, _desc, _quirks, ...) \ _BHND_DEVICE(_vendor, _device, _desc, _quirks, \ ## __VA_ARGS__, 0) #define BHND_DEVICE_END { { BHND_MATCH_ANY }, NULL, NULL, 0 } #define BHND_DEVICE_IS_END(_d) \ (BHND_MATCH_IS_ANY(&(_d)->core) && (_d)->desc == NULL) const char *bhnd_vendor_name(uint16_t vendor); const char *bhnd_port_type_name(bhnd_port_type port_type); const char *bhnd_nvram_src_name(bhnd_nvram_src nvram_src); const char *bhnd_find_core_name(uint16_t vendor, uint16_t device); bhnd_devclass_t bhnd_find_core_class(uint16_t vendor, uint16_t device); const char *bhnd_core_name(const struct bhnd_core_info *ci); bhnd_devclass_t bhnd_core_class(const struct bhnd_core_info *ci); int bhnd_format_chip_id(char *buffer, size_t size, uint16_t chip_id); device_t bhnd_match_child(device_t dev, const struct bhnd_core_match *desc); device_t bhnd_find_child(device_t dev, bhnd_devclass_t class, int unit); device_t bhnd_find_bridge_root(device_t dev, devclass_t bus_class); const struct bhnd_core_info *bhnd_match_core( const struct bhnd_core_info *cores, u_int num_cores, const struct bhnd_core_match *desc); const struct bhnd_core_info *bhnd_find_core( const struct bhnd_core_info *cores, u_int num_cores, bhnd_devclass_t class); struct bhnd_core_match bhnd_core_get_match_desc( const struct bhnd_core_info *core); bool bhnd_cores_equal( const struct bhnd_core_info *lhs, const struct bhnd_core_info *rhs); bool bhnd_core_matches( const struct bhnd_core_info *core, const struct bhnd_core_match *desc); bool bhnd_chip_matches( const struct bhnd_chipid *chipid, const struct bhnd_chip_match *desc); bool bhnd_board_matches( const struct bhnd_board_info *info, const struct bhnd_board_match *desc); bool bhnd_hwrev_matches(uint16_t hwrev, const struct bhnd_hwrev_match *desc); bool bhnd_device_matches(device_t dev, const struct bhnd_device_match *desc); const struct bhnd_device *bhnd_device_lookup(device_t dev, const struct bhnd_device *table, size_t entry_size); uint32_t bhnd_device_quirks(device_t dev, const struct bhnd_device *table, size_t entry_size); struct bhnd_core_info bhnd_get_core_info(device_t dev); int bhnd_alloc_resources(device_t dev, struct resource_spec *rs, struct bhnd_resource **res); void bhnd_release_resources(device_t dev, const struct resource_spec *rs, struct bhnd_resource **res); struct bhnd_chipid bhnd_parse_chipid(uint32_t idreg, bhnd_addr_t enum_addr); int bhnd_chipid_fixed_ncores( const struct bhnd_chipid *cid, uint16_t chipc_hwrev, uint8_t *ncores); int bhnd_read_chipid(device_t dev, struct resource_spec *rs, bus_size_t chipc_offset, struct bhnd_chipid *result); void bhnd_set_custom_core_desc(device_t dev, const char *name); void bhnd_set_default_core_desc(device_t dev); void bhnd_set_default_bus_desc(device_t dev, const struct bhnd_chipid *chip_id); int bhnd_nvram_getvar_str(device_t dev, const char *name, char *buf, size_t len, size_t *rlen); int bhnd_nvram_getvar_uint(device_t dev, const char *name, void *value, int width); int bhnd_nvram_getvar_uint8(device_t dev, const char *name, uint8_t *value); int bhnd_nvram_getvar_uint16(device_t dev, const char *name, uint16_t *value); int bhnd_nvram_getvar_uint32(device_t dev, const char *name, uint32_t *value); int bhnd_nvram_getvar_int(device_t dev, const char *name, void *value, int width); int bhnd_nvram_getvar_int8(device_t dev, const char *name, int8_t *value); int bhnd_nvram_getvar_int16(device_t dev, const char *name, int16_t *value); int bhnd_nvram_getvar_int32(device_t dev, const char *name, int32_t *value); int bhnd_nvram_getvar_array(device_t dev, const char *name, void *buf, size_t count, bhnd_nvram_type type); bool bhnd_bus_generic_is_hw_disabled(device_t dev, device_t child); bool bhnd_bus_generic_is_region_valid(device_t dev, device_t child, bhnd_port_type type, u_int port, u_int region); int bhnd_bus_generic_get_nvram_var(device_t dev, device_t child, const char *name, void *buf, size_t *size, bhnd_nvram_type type); const struct bhnd_chipid *bhnd_bus_generic_get_chipid(device_t dev, device_t child); int bhnd_bus_generic_read_board_info(device_t dev, device_t child, struct bhnd_board_info *info); struct bhnd_resource *bhnd_bus_generic_alloc_resource (device_t dev, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags); int bhnd_bus_generic_release_resource (device_t dev, device_t child, int type, int rid, struct bhnd_resource *r); int bhnd_bus_generic_activate_resource (device_t dev, device_t child, int type, int rid, struct bhnd_resource *r); int bhnd_bus_generic_deactivate_resource (device_t dev, device_t child, int type, int rid, struct bhnd_resource *r); bhnd_attach_type bhnd_bus_generic_get_attach_type(device_t dev, device_t child); /** * Return the bhnd(4) bus driver's device enumeration parser class * * @param driver A bhnd bus driver instance. */ static inline bhnd_erom_class_t * bhnd_driver_get_erom_class(driver_t *driver) { return (BHND_BUS_GET_EROM_CLASS(driver)); } /** * Return the active host bridge core for the bhnd bus, if any, or NULL if * not found. * * @param dev A bhnd bus device. */ static inline device_t bhnd_find_hostb_device(device_t dev) { return (BHND_BUS_FIND_HOSTB_DEVICE(dev)); } /** * Return true if the hardware components required by @p dev are known to be * unpopulated or otherwise unusable. * * In some cases, enumerated devices may have pins that are left floating, or * the hardware may otherwise be non-functional; this method allows a parent * device to explicitly specify if a successfully enumerated @p dev should * be disabled. * * @param dev A bhnd bus child device. */ static inline bool bhnd_is_hw_disabled(device_t dev) { return (BHND_BUS_IS_HW_DISABLED(device_get_parent(dev), dev)); } /** * Return the BHND chip identification info for the bhnd bus. * * @param dev A bhnd bus child device. */ static inline const struct bhnd_chipid * bhnd_get_chipid(device_t dev) { return (BHND_BUS_GET_CHIPID(device_get_parent(dev), dev)); }; + /** + * Read the current value of a bhnd(4) device's per-core I/O control register. + * + * @param dev The bhnd bus child device to be queried. + * @param[out] ioctl On success, the I/O control register value. + * + * @retval 0 success + * @retval EINVAL If @p child is not a direct child of @p dev. + * @retval ENODEV If agent/config space for @p child is unavailable. + * @retval non-zero If reading the IOCTL register otherwise fails, a regular + * unix error code will be returned. + */ +static inline int +bhnd_read_ioctl(device_t dev, uint16_t *ioctl) +{ + return (BHND_BUS_READ_IOCTL(device_get_parent(dev), dev, ioctl)); +} + +/** + * Write @p value and @p mask to a bhnd(4) device's per-core I/O control + * register. + * + * @param dev The bhnd bus child device for which the IOCTL register will be + * written. + * @param value The value to be written (see BHND_IOCTL_*). + * @param mask Only the bits defined by @p mask will be updated from @p value. + * + * @retval 0 success + * @retval EINVAL If @p child is not a direct child of @p dev. + * @retval ENODEV If agent/config space for @p child is unavailable. + * @retval non-zero If writing the IOCTL register otherwise fails, a regular + * unix error code will be returned. + */ +static inline int +bhnd_write_ioctl(device_t dev, uint16_t value, uint16_t mask) +{ + return (BHND_BUS_WRITE_IOCTL(device_get_parent(dev), dev, value, mask)); +} + +/** + * Read the current value of a bhnd(4) device's per-core I/O status register. + * + * @param dev The bhnd bus child device to be queried. + * @param[out] iost On success, the I/O status register value. + * + * @retval 0 success + * @retval EINVAL If @p child is not a direct child of @p dev. + * @retval ENODEV If agent/config space for @p child is unavailable. + * @retval non-zero If reading the IOST register otherwise fails, a regular + * unix error code will be returned. + */ +static inline int +bhnd_read_iost(device_t dev, uint16_t *iost) +{ + return (BHND_BUS_READ_IOST(device_get_parent(dev), dev, iost)); +} + +/** + * Return true if the given bhnd device's hardware is currently held + * in a RESET state or otherwise not clocked (BHND_IOCTL_CLK_EN). + * + * @param dev The device to query. + * + * @retval true If @p dev is held in RESET or not clocked (BHND_IOCTL_CLK_EN), + * or an error occured determining @p dev's hardware state. + * @retval false If @p dev is clocked and is not held in RESET. + */ +static inline bool +bhnd_is_hw_suspended(device_t dev) +{ + return (BHND_BUS_IS_HW_SUSPENDED(device_get_parent(dev), dev)); +} + +/** + * Place the bhnd(4) device's hardware into a reset state, and then bring the + * hardware out of reset with BHND_IOCTL_CLK_EN and @p ioctl flags set. + * + * Any clock or resource PMU requests previously made by @p dev will be + * invalidated. + * + * @param dev The device to be reset. + * @param ioctl Device-specific core ioctl flags to be supplied on reset + * (see BHND_IOCTL_*). + * + * @retval 0 success + * @retval non-zero error + */ +static inline int +bhnd_reset_hw(device_t dev, uint16_t ioctl) +{ + return (BHND_BUS_RESET_HW(device_get_parent(dev), dev, ioctl)); +} + +/** + * Suspend @p child's hardware in a low-power reset state. + * + * Any clock or resource PMU requests previously made by @p dev will be + * invalidated. + * + * The hardware may be brought out of reset via bhnd_reset_hw(). + * + * @param dev The device to be suspended. + * + * @retval 0 success + * @retval non-zero error + */ +static inline int +bhnd_suspend_hw(device_t dev) +{ + return (BHND_BUS_SUSPEND_HW(device_get_parent(dev), dev)); +} + +/** * If supported by the chipset, return the clock source for the given clock. * * This function is only supported on early PWRCTL-equipped chipsets * that expose clock management via their host bridge interface. Currently, * this includes PCI (not PCIe) devices, with ChipCommon core revisions 0-9. * * @param dev A bhnd bus child device. * @param clock The clock for which a clock source will be returned. * * @retval bhnd_clksrc The clock source for @p clock. * @retval BHND_CLKSRC_UNKNOWN If @p clock is unsupported, or its * clock source is not known to the bus. */ static inline bhnd_clksrc bhnd_pwrctl_get_clksrc(device_t dev, bhnd_clock clock) { return (BHND_BUS_PWRCTL_GET_CLKSRC(device_get_parent(dev), dev, clock)); } /** * If supported by the chipset, gate @p clock * * This function is only supported on early PWRCTL-equipped chipsets * that expose clock management via their host bridge interface. Currently, * this includes PCI (not PCIe) devices, with ChipCommon core revisions 0-9. * * @param dev A bhnd bus child device. * @param clock The clock to be disabled. * * @retval 0 success * @retval ENODEV If bus-level clock source management is not supported. * @retval ENXIO If bus-level management of @p clock is not supported. */ static inline int bhnd_pwrctl_gate_clock(device_t dev, bhnd_clock clock) { return (BHND_BUS_PWRCTL_GATE_CLOCK(device_get_parent(dev), dev, clock)); } /** * If supported by the chipset, ungate @p clock * * This function is only supported on early PWRCTL-equipped chipsets * that expose clock management via their host bridge interface. Currently, * this includes PCI (not PCIe) devices, with ChipCommon core revisions 0-9. * * @param dev A bhnd bus child device. * @param clock The clock to be enabled. * * @retval 0 success * @retval ENODEV If bus-level clock source management is not supported. * @retval ENXIO If bus-level management of @p clock is not supported. */ static inline int bhnd_pwrctl_ungate_clock(device_t dev, bhnd_clock clock) { return (BHND_BUS_PWRCTL_UNGATE_CLOCK(device_get_parent(dev), dev, clock)); } /** * Return the BHND attachment type of the parent bhnd bus. * * @param dev A bhnd bus child device. * * @retval BHND_ATTACH_ADAPTER if the bus is resident on a bridged adapter, * such as a WiFi chipset. * @retval BHND_ATTACH_NATIVE if the bus provides hardware services (clock, * CPU, etc) to a directly attached native host. */ static inline bhnd_attach_type bhnd_get_attach_type (device_t dev) { return (BHND_BUS_GET_ATTACH_TYPE(device_get_parent(dev), dev)); } /** * Attempt to read the BHND board identification from the bhnd bus. * * This relies on NVRAM access, and will fail if a valid NVRAM device cannot * be found, or is not yet attached. * * @param dev The parent of @p child. * @param child The bhnd device requesting board info. * @param[out] info On success, will be populated with the bhnd(4) device's * board information. * * @retval 0 success * @retval ENODEV No valid NVRAM source could be found. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ static inline int bhnd_read_board_info(device_t dev, struct bhnd_board_info *info) { return (BHND_BUS_READ_BOARD_INFO(device_get_parent(dev), dev, info)); } /** * Return the number of interrupts to be assigned to @p child via * BHND_BUS_ASSIGN_INTR(). * * @param dev A bhnd bus child device. */ static inline int bhnd_get_intr_count(device_t dev) { return (BHND_BUS_GET_INTR_COUNT(device_get_parent(dev), dev)); } /** * Return the backplane interrupt vector corresponding to @p dev's given * @p intr number. * * @param dev A bhnd bus child device. * @param intr The interrupt number being queried. This is equivalent to the * bus resource ID for the interrupt. * @param[out] ivec On success, the assigned hardware interrupt vector be * written to this pointer. * * On bcma(4) devices, this returns the OOB bus line assigned to the * interrupt. * * On siba(4) devices, this returns the target OCP slave flag number assigned * to the interrupt. * * @retval 0 success * @retval ENXIO If @p intr exceeds the number of interrupts available * to @p child. */ static inline int bhnd_get_core_ivec(device_t dev, u_int intr, uint32_t *ivec) { return (BHND_BUS_GET_CORE_IVEC(device_get_parent(dev), dev, intr, ivec)); } /** * Allocate and enable per-core PMU request handling for @p child. * * The region containing the core's PMU register block (if any) must be * allocated via bus_alloc_resource(9) (or bhnd_alloc_resource) before * calling bhnd_alloc_pmu(), and must not be released until after * calling bhnd_release_pmu(). * * @param dev The parent of @p child. * @param child The requesting bhnd device. * * @retval 0 success * @retval non-zero If allocating PMU request state otherwise fails, a * regular unix error code will be returned. */ static inline int bhnd_alloc_pmu(device_t dev) { return (BHND_BUS_ALLOC_PMU(device_get_parent(dev), dev)); } /** * Release any per-core PMU resources allocated for @p child. Any outstanding * PMU requests are are discarded. * * @param dev The parent of @p child. * @param child The requesting bhnd device. * * @retval 0 success * @retval non-zero If releasing PMU request state otherwise fails, a * regular unix error code will be returned, and * the core state will be left unmodified. */ static inline int bhnd_release_pmu(device_t dev) { return (BHND_BUS_RELEASE_PMU(device_get_parent(dev), dev)); } /** * Request that @p clock (or faster) be routed to @p dev. * - * A driver must ask the bhnd bus to allocate clock request state + * @note A driver must ask the bhnd bus to allocate clock request state * via bhnd_alloc_pmu() before it can request clock resources. * - * Request multiplexing is managed by the bus. + * @note Any outstanding PMU clock requests will be discarded upon calling + * BHND_BUS_RESET_HW() or BHND_BUS_SUSPEND_HW(). * * @param dev The bhnd(4) device to which @p clock should be routed. * @param clock The requested clock source. * * @retval 0 success * @retval ENODEV If an unsupported clock was requested. - * @retval ENXIO If the PMU has not been initialized or is otherwise unvailable. + * @retval ENXIO If the PMU has not been initialized or is otherwise unvailable, */ static inline int bhnd_request_clock(device_t dev, bhnd_clock clock) { return (BHND_BUS_REQUEST_CLOCK(device_get_parent(dev), dev, clock)); } /** * Request that @p clocks be powered on behalf of @p dev. * * This will power any clock sources (e.g. XTAL, PLL, etc) required for * @p clocks and wait until they are ready, discarding any previous * requests by @p dev. - * - * Request multiplexing is managed by the bus. * - * A driver must ask the bhnd bus to allocate clock request state + * @note A driver must ask the bhnd bus to allocate clock request state * via bhnd_alloc_pmu() before it can request clock resources. - * + * + * @note Any outstanding PMU clock requests will be discarded upon calling + * BHND_BUS_RESET_HW() or BHND_BUS_SUSPEND_HW(). + * * @param dev The requesting bhnd(4) device. * @param clocks The clock(s) to be enabled. * * @retval 0 success * @retval ENODEV If an unsupported clock was requested. * @retval ENXIO If the PMU has not been initialized or is otherwise unvailable. */ static inline int bhnd_enable_clocks(device_t dev, uint32_t clocks) { return (BHND_BUS_ENABLE_CLOCKS(device_get_parent(dev), dev, clocks)); } /** * Power up an external PMU-managed resource assigned to @p dev. * - * A driver must ask the bhnd bus to allocate PMU request state + * @note A driver must ask the bhnd bus to allocate PMU request state * via bhnd_alloc_pmu() before it can request PMU resources. * + * @note Any outstanding PMU resource requests will be released upon calling + * bhnd_reset_hw() or bhnd_suspend_hw(). + * * @param dev The requesting bhnd(4) device. * @param rsrc The core-specific external resource identifier. * * @retval 0 success * @retval ENODEV If the PMU does not support @p rsrc. * @retval ENXIO If the PMU has not been initialized or is otherwise unvailable. */ static inline int bhnd_request_ext_rsrc(device_t dev, u_int rsrc) { return (BHND_BUS_REQUEST_EXT_RSRC(device_get_parent(dev), dev, rsrc)); } /** * Power down an external PMU-managed resource assigned to @p dev. * * A driver must ask the bhnd bus to allocate PMU request state * via bhnd_alloc_pmu() before it can request PMU resources. * * @param dev The requesting bhnd(4) device. * @param rsrc The core-specific external resource identifier. * * @retval 0 success * @retval ENODEV If the PMU does not support @p rsrc. * @retval ENXIO If the PMU has not been initialized or is otherwise unvailable. */ static inline int bhnd_release_ext_rsrc(device_t dev, u_int rsrc) { return (BHND_BUS_RELEASE_EXT_RSRC(device_get_parent(dev), dev, rsrc)); } - /** * Read @p width bytes at @p offset from the bus-specific agent/config * space of @p dev. * * @param dev The bhnd device for which @p offset should be read. * @param offset The offset to be read. + * @param[out] value On success, the will be set to the @p width value read + * at @p offset. * @param width The size of the access. Must be 1, 2 or 4 bytes. * * The exact behavior of this method is bus-specific. In the case of * bcma(4), this method provides access to the first agent port of @p child. * * @note Device drivers should only use this API for functionality * that is not available via another bhnd(4) function. + * + * @retval 0 success + * @retval EINVAL If @p child is not a direct child of @p dev. + * @retval EINVAL If @p width is not one of 1, 2, or 4 bytes. + * @retval ENODEV If accessing agent/config space for @p child is unsupported. + * @retval EFAULT If reading @p width at @p offset exceeds the bounds of + * the mapped agent/config space for @p child. */ static inline uint32_t -bhnd_read_config(device_t dev, bus_size_t offset, u_int width) +bhnd_read_config(device_t dev, bus_size_t offset, void *value, u_int width) { return (BHND_BUS_READ_CONFIG(device_get_parent(dev), dev, offset, - width)); + value, width)); } /** - * Read @p width bytes at @p offset from the bus-specific agent/config + * Write @p width bytes at @p offset to the bus-specific agent/config * space of @p dev. * * @param dev The bhnd device for which @p offset should be read. * @param offset The offset to be written. - * @param width The size of the access. Must be 1, 2 or 4 bytes. + * @param value A pointer to the value to be written. + * @param width The size of @p value. Must be 1, 2 or 4 bytes. * * The exact behavior of this method is bus-specific. In the case of * bcma(4), this method provides access to the first agent port of @p child. * * @note Device drivers should only use this API for functionality * that is not available via another bhnd(4) function. + * + * @retval 0 success + * @retval EINVAL If @p child is not a direct child of @p dev. + * @retval EINVAL If @p width is not one of 1, 2, or 4 bytes. + * @retval ENODEV If accessing agent/config space for @p child is unsupported. + * @retval EFAULT If reading @p width at @p offset exceeds the bounds of + * the mapped agent/config space for @p child. */ -static inline void -bhnd_write_config(device_t dev, bus_size_t offset, uint32_t val, u_int width) +static inline int +bhnd_write_config(device_t dev, bus_size_t offset, const void *value, + u_int width) { - BHND_BUS_WRITE_CONFIG(device_get_parent(dev), dev, offset, val, width); + return (BHND_BUS_WRITE_CONFIG(device_get_parent(dev), dev, offset, + value, width)); } /** * Read an NVRAM variable, coerced to the requested @p type. * * @param dev A bhnd bus child device. * @param name The NVRAM variable name. * @param[out] buf A buffer large enough to hold @p len bytes. On * success, the requested value will be written to * this buffer. This argment may be NULL if * the value is not desired. * @param[in,out] len The maximum capacity of @p buf. On success, * will be set to the actual size of the requested * value. * @param type The desired data representation to be written * to @p buf. * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENODEV No valid NVRAM source could be found. * @retval ENOMEM If a buffer of @p size is too small to hold the * requested value. * @retval EOPNOTSUPP If the value cannot be coerced to @p type. * @retval ERANGE If value coercion would overflow @p type. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ static inline int bhnd_nvram_getvar(device_t dev, const char *name, void *buf, size_t *len, bhnd_nvram_type type) { return (BHND_BUS_GET_NVRAM_VAR(device_get_parent(dev), dev, name, buf, len, type)); } /** * Allocate a resource from a device's parent bhnd(4) bus. * * @param dev The device requesting resource ownership. * @param type The type of resource to allocate. This may be any type supported * by the standard bus APIs. * @param rid The bus-specific handle identifying the resource being allocated. * @param start The start address of the resource. * @param end The end address of the resource. * @param count The size of the resource. * @param flags The flags for the resource to be allocated. These may be any * values supported by the standard bus APIs. * * To request the resource's default addresses, pass @p start and * @p end values of @c 0 and @c ~0, respectively, and * a @p count of @c 1. * * @retval NULL The resource could not be allocated. * @retval resource The allocated resource. */ static inline struct bhnd_resource * bhnd_alloc_resource(device_t dev, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) { return BHND_BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, type, rid, start, end, count, flags); } /** * Allocate a resource from a device's parent bhnd(4) bus, using the * resource's default start, end, and count values. * * @param dev The device requesting resource ownership. * @param type The type of resource to allocate. This may be any type supported * by the standard bus APIs. * @param rid The bus-specific handle identifying the resource being allocated. * @param flags The flags for the resource to be allocated. These may be any * values supported by the standard bus APIs. * * @retval NULL The resource could not be allocated. * @retval resource The allocated resource. */ static inline struct bhnd_resource * bhnd_alloc_resource_any(device_t dev, int type, int *rid, u_int flags) { return bhnd_alloc_resource(dev, type, rid, 0, ~0, 1, flags); } /** * Activate a previously allocated bhnd resource. * * @param dev The device holding ownership of the allocated resource. * @param type The type of the resource. * @param rid The bus-specific handle identifying the resource. * @param r A pointer to the resource returned by bhnd_alloc_resource or * BHND_BUS_ALLOC_RESOURCE. * * @retval 0 success * @retval non-zero an error occurred while activating the resource. */ static inline int bhnd_activate_resource(device_t dev, int type, int rid, struct bhnd_resource *r) { return BHND_BUS_ACTIVATE_RESOURCE(device_get_parent(dev), dev, type, rid, r); } /** * Deactivate a previously activated bhnd resource. * * @param dev The device holding ownership of the activated resource. * @param type The type of the resource. * @param rid The bus-specific handle identifying the resource. * @param r A pointer to the resource returned by bhnd_alloc_resource or * BHND_BUS_ALLOC_RESOURCE. * * @retval 0 success * @retval non-zero an error occurred while activating the resource. */ static inline int bhnd_deactivate_resource(device_t dev, int type, int rid, struct bhnd_resource *r) { return BHND_BUS_DEACTIVATE_RESOURCE(device_get_parent(dev), dev, type, rid, r); } /** * Free a resource allocated by bhnd_alloc_resource(). * * @param dev The device holding ownership of the resource. * @param type The type of the resource. * @param rid The bus-specific handle identifying the resource. * @param r A pointer to the resource returned by bhnd_alloc_resource or * BHND_ALLOC_RESOURCE. * * @retval 0 success * @retval non-zero an error occurred while activating the resource. */ static inline int bhnd_release_resource(device_t dev, int type, int rid, struct bhnd_resource *r) { return BHND_BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, type, rid, r); } /** * Return true if @p region_num is a valid region on @p port_num of * @p type attached to @p dev. * * @param dev A bhnd bus child device. * @param type The port type being queried. * @param port_num The port number being queried. * @param region_num The region number being queried. */ static inline bool bhnd_is_region_valid(device_t dev, bhnd_port_type type, u_int port_num, u_int region_num) { return (BHND_BUS_IS_REGION_VALID(device_get_parent(dev), dev, type, port_num, region_num)); } /** * Return the number of ports of type @p type attached to @p def. * * @param dev A bhnd bus child device. * @param type The port type being queried. */ static inline u_int bhnd_get_port_count(device_t dev, bhnd_port_type type) { return (BHND_BUS_GET_PORT_COUNT(device_get_parent(dev), dev, type)); } /** * Return the number of memory regions mapped to @p child @p port of * type @p type. * * @param dev A bhnd bus child device. * @param port The port number being queried. * @param type The port type being queried. */ static inline u_int bhnd_get_region_count(device_t dev, bhnd_port_type type, u_int port) { return (BHND_BUS_GET_REGION_COUNT(device_get_parent(dev), dev, type, port)); } /** * Return the resource-ID for a memory region on the given device port. * * @param dev A bhnd bus child device. * @param type The port type. * @param port The port identifier. * @param region The identifier of the memory region on @p port. * * @retval int The RID for the given @p port and @p region on @p device. * @retval -1 No such port/region found. */ static inline int bhnd_get_port_rid(device_t dev, bhnd_port_type type, u_int port, u_int region) { return BHND_BUS_GET_PORT_RID(device_get_parent(dev), dev, type, port, region); } /** * Decode a port / region pair on @p dev defined by @p rid. * * @param dev A bhnd bus child device. * @param type The resource type. * @param rid The resource identifier. * @param[out] port_type The decoded port type. * @param[out] port The decoded port identifier. * @param[out] region The decoded region identifier. * * @retval 0 success * @retval non-zero No matching port/region found. */ static inline int bhnd_decode_port_rid(device_t dev, int type, int rid, bhnd_port_type *port_type, u_int *port, u_int *region) { return BHND_BUS_DECODE_PORT_RID(device_get_parent(dev), dev, type, rid, port_type, port, region); } /** * Get the address and size of @p region on @p port. * * @param dev A bhnd bus child device. * @param port_type The port type. * @param port The port identifier. * @param region The identifier of the memory region on @p port. * @param[out] region_addr The region's base address. * @param[out] region_size The region's size. * * @retval 0 success * @retval non-zero No matching port/region found. */ static inline int bhnd_get_region_addr(device_t dev, bhnd_port_type port_type, u_int port, u_int region, bhnd_addr_t *region_addr, bhnd_size_t *region_size) { return BHND_BUS_GET_REGION_ADDR(device_get_parent(dev), dev, port_type, port, region, region_addr, region_size); } /* * bhnd bus-level equivalents of the bus_(read|write|set|barrier|...) * macros (compatible with bhnd_resource). * * Generated with bhnd/tools/bus_macro.sh */ #define bhnd_bus_barrier(r, o, l, f) \ ((r)->direct) ? \ bus_barrier((r)->res, (o), (l), (f)) : \ BHND_BUS_BARRIER( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (l), (f)) #define bhnd_bus_read_1(r, o) \ ((r)->direct) ? \ bus_read_1((r)->res, (o)) : \ BHND_BUS_READ_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o)) #define bhnd_bus_read_multi_1(r, o, d, c) \ ((r)->direct) ? \ bus_read_multi_1((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_MULTI_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_read_region_1(r, o, d, c) \ ((r)->direct) ? \ bus_read_region_1((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_REGION_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_1(r, o, v) \ ((r)->direct) ? \ bus_write_1((r)->res, (o), (v)) : \ BHND_BUS_WRITE_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v)) #define bhnd_bus_write_multi_1(r, o, d, c) \ ((r)->direct) ? \ bus_write_multi_1((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_MULTI_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_region_1(r, o, d, c) \ ((r)->direct) ? \ bus_write_region_1((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_REGION_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_read_stream_1(r, o) \ ((r)->direct) ? \ bus_read_stream_1((r)->res, (o)) : \ BHND_BUS_READ_STREAM_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o)) #define bhnd_bus_read_multi_stream_1(r, o, d, c) \ ((r)->direct) ? \ bus_read_multi_stream_1((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_MULTI_STREAM_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_read_region_stream_1(r, o, d, c) \ ((r)->direct) ? \ bus_read_region_stream_1((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_REGION_STREAM_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_stream_1(r, o, v) \ ((r)->direct) ? \ bus_write_stream_1((r)->res, (o), (v)) : \ BHND_BUS_WRITE_STREAM_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v)) #define bhnd_bus_write_multi_stream_1(r, o, d, c) \ ((r)->direct) ? \ bus_write_multi_stream_1((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_MULTI_STREAM_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_region_stream_1(r, o, d, c) \ ((r)->direct) ? \ bus_write_region_stream_1((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_REGION_STREAM_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_set_multi_1(r, o, v, c) \ ((r)->direct) ? \ bus_set_multi_1((r)->res, (o), (v), (c)) : \ BHND_BUS_SET_MULTI_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v), (c)) #define bhnd_bus_set_region_1(r, o, v, c) \ ((r)->direct) ? \ bus_set_region_1((r)->res, (o), (v), (c)) : \ BHND_BUS_SET_REGION_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v), (c)) #define bhnd_bus_read_2(r, o) \ ((r)->direct) ? \ bus_read_2((r)->res, (o)) : \ BHND_BUS_READ_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o)) #define bhnd_bus_read_multi_2(r, o, d, c) \ ((r)->direct) ? \ bus_read_multi_2((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_MULTI_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_read_region_2(r, o, d, c) \ ((r)->direct) ? \ bus_read_region_2((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_REGION_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_2(r, o, v) \ ((r)->direct) ? \ bus_write_2((r)->res, (o), (v)) : \ BHND_BUS_WRITE_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v)) #define bhnd_bus_write_multi_2(r, o, d, c) \ ((r)->direct) ? \ bus_write_multi_2((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_MULTI_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_region_2(r, o, d, c) \ ((r)->direct) ? \ bus_write_region_2((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_REGION_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_read_stream_2(r, o) \ ((r)->direct) ? \ bus_read_stream_2((r)->res, (o)) : \ BHND_BUS_READ_STREAM_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o)) #define bhnd_bus_read_multi_stream_2(r, o, d, c) \ ((r)->direct) ? \ bus_read_multi_stream_2((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_MULTI_STREAM_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_read_region_stream_2(r, o, d, c) \ ((r)->direct) ? \ bus_read_region_stream_2((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_REGION_STREAM_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_stream_2(r, o, v) \ ((r)->direct) ? \ bus_write_stream_2((r)->res, (o), (v)) : \ BHND_BUS_WRITE_STREAM_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v)) #define bhnd_bus_write_multi_stream_2(r, o, d, c) \ ((r)->direct) ? \ bus_write_multi_stream_2((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_MULTI_STREAM_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_region_stream_2(r, o, d, c) \ ((r)->direct) ? \ bus_write_region_stream_2((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_REGION_STREAM_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_set_multi_2(r, o, v, c) \ ((r)->direct) ? \ bus_set_multi_2((r)->res, (o), (v), (c)) : \ BHND_BUS_SET_MULTI_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v), (c)) #define bhnd_bus_set_region_2(r, o, v, c) \ ((r)->direct) ? \ bus_set_region_2((r)->res, (o), (v), (c)) : \ BHND_BUS_SET_REGION_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v), (c)) #define bhnd_bus_read_4(r, o) \ ((r)->direct) ? \ bus_read_4((r)->res, (o)) : \ BHND_BUS_READ_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o)) #define bhnd_bus_read_multi_4(r, o, d, c) \ ((r)->direct) ? \ bus_read_multi_4((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_MULTI_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_read_region_4(r, o, d, c) \ ((r)->direct) ? \ bus_read_region_4((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_REGION_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_4(r, o, v) \ ((r)->direct) ? \ bus_write_4((r)->res, (o), (v)) : \ BHND_BUS_WRITE_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v)) #define bhnd_bus_write_multi_4(r, o, d, c) \ ((r)->direct) ? \ bus_write_multi_4((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_MULTI_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_region_4(r, o, d, c) \ ((r)->direct) ? \ bus_write_region_4((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_REGION_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_read_stream_4(r, o) \ ((r)->direct) ? \ bus_read_stream_4((r)->res, (o)) : \ BHND_BUS_READ_STREAM_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o)) #define bhnd_bus_read_multi_stream_4(r, o, d, c) \ ((r)->direct) ? \ bus_read_multi_stream_4((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_MULTI_STREAM_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_read_region_stream_4(r, o, d, c) \ ((r)->direct) ? \ bus_read_region_stream_4((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_REGION_STREAM_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_stream_4(r, o, v) \ ((r)->direct) ? \ bus_write_stream_4((r)->res, (o), (v)) : \ BHND_BUS_WRITE_STREAM_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v)) #define bhnd_bus_write_multi_stream_4(r, o, d, c) \ ((r)->direct) ? \ bus_write_multi_stream_4((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_MULTI_STREAM_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_region_stream_4(r, o, d, c) \ ((r)->direct) ? \ bus_write_region_stream_4((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_REGION_STREAM_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_set_multi_4(r, o, v, c) \ ((r)->direct) ? \ bus_set_multi_4((r)->res, (o), (v), (c)) : \ BHND_BUS_SET_MULTI_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v), (c)) #define bhnd_bus_set_region_4(r, o, v, c) \ ((r)->direct) ? \ bus_set_region_4((r)->res, (o), (v), (c)) : \ BHND_BUS_SET_REGION_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v), (c)) #endif /* _BHND_BHND_H_ */ Index: head/sys/dev/bhnd/bhnd_bus_if.m =================================================================== --- head/sys/dev/bhnd/bhnd_bus_if.m (revision 306286) +++ head/sys/dev/bhnd/bhnd_bus_if.m (revision 306287) @@ -1,1345 +1,1470 @@ #- # Copyright (c) 2015-2016 Landon Fuller # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions # are met: # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. # IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, # INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # $FreeBSD$ #include #include #include #include #include INTERFACE bhnd_bus; # # bhnd(4) bus interface # HEADER { /* forward declarations */ struct bhnd_board_info; struct bhnd_core_info; struct bhnd_chipid; struct bhnd_devinfo; struct bhnd_resource; } CODE { #include #include static bhnd_erom_class_t * bhnd_bus_null_get_erom_class(driver_t *driver) { return (NULL); } static struct bhnd_chipid * bhnd_bus_null_get_chipid(device_t dev, device_t child) { panic("bhnd_bus_get_chipid unimplemented"); } + static int + bhnd_bus_null_read_ioctl(device_t dev, device_t child, uint16_t *ioctl) + { + panic("bhnd_bus_read_ioctl unimplemented"); + } + + + static int + bhnd_bus_null_write_ioctl(device_t dev, device_t child, uint16_t value, + uint16_t mask) + { + panic("bhnd_bus_write_ioctl unimplemented"); + } + + + static int + bhnd_bus_null_read_iost(device_t dev, device_t child, uint16_t *iost) + { + panic("bhnd_bus_read_iost unimplemented"); + } + + static bool + bhnd_bus_null_is_hw_suspended(device_t dev, device_t child) + { + panic("bhnd_bus_is_hw_suspended unimplemented"); + } + + static int + bhnd_bus_null_reset_hw(device_t dev, device_t child, uint16_t ioctl) + { + panic("bhnd_bus_reset_hw unimplemented"); + } + + + static int + bhnd_bus_null_suspend_hw(device_t dev, device_t child) + { + panic("bhnd_bus_suspend_hw unimplemented"); + } + static bhnd_attach_type bhnd_bus_null_get_attach_type(device_t dev, device_t child) { panic("bhnd_bus_get_attach_type unimplemented"); } static bhnd_clksrc bhnd_bus_null_pwrctl_get_clksrc(device_t dev, device_t child, bhnd_clock clock) { return (BHND_CLKSRC_UNKNOWN); } static int bhnd_bus_null_pwrctl_gate_clock(device_t dev, device_t child, bhnd_clock clock) { return (ENODEV); } static int bhnd_bus_null_pwrctl_ungate_clock(device_t dev, device_t child, bhnd_clock clock) { return (ENODEV); } static int bhnd_bus_null_read_board_info(device_t dev, device_t child, struct bhnd_board_info *info) { panic("bhnd_bus_read_boardinfo unimplemented"); } static int bhnd_bus_null_get_intr_count(device_t dev, device_t child) { panic("bhnd_bus_get_intr_count unimplemented"); } static int bhnd_bus_null_assign_intr(device_t dev, device_t child, int rid) { panic("bhnd_bus_assign_intr unimplemented"); } static int bhnd_bus_null_get_core_ivec(device_t dev, device_t child, u_int intr, uint32_t *ivec) { panic("bhnd_bus_get_core_ivec unimplemented"); } static void bhnd_bus_null_child_added(device_t dev, device_t child) { } static int bhnd_bus_null_alloc_pmu(device_t dev, device_t child) { panic("bhnd_bus_alloc_pmu unimplemented"); } static int bhnd_bus_null_release_pmu(device_t dev, device_t child) { panic("bhnd_bus_release_pmu unimplemented"); } static int bhnd_bus_null_request_clock(device_t dev, device_t child, bhnd_clock clock) { panic("bhnd_bus_request_clock unimplemented"); } static int bhnd_bus_null_enable_clocks(device_t dev, device_t child, uint32_t clocks) { panic("bhnd_bus_enable_clocks unimplemented"); } static int bhnd_bus_null_request_ext_rsrc(device_t dev, device_t child, u_int rsrc) { panic("bhnd_bus_request_ext_rsrc unimplemented"); } static int bhnd_bus_null_release_ext_rsrc(device_t dev, device_t child, u_int rsrc) { panic("bhnd_bus_release_ext_rsrc unimplemented"); } - static uint32_t + static int bhnd_bus_null_read_config(device_t dev, device_t child, - bus_size_t offset, u_int width) + bus_size_t offset, void *value, u_int width) { panic("bhnd_bus_null_read_config unimplemented"); } static void bhnd_bus_null_write_config(device_t dev, device_t child, - bus_size_t offset, uint32_t val, u_int width) + bus_size_t offset, void *value, u_int width) { panic("bhnd_bus_null_write_config unimplemented"); } static device_t bhnd_bus_null_find_hostb_device(device_t dev) { return (NULL); } static bool bhnd_bus_null_is_hw_disabled(device_t dev, device_t child) { panic("bhnd_bus_is_hw_disabled unimplemented"); } static int bhnd_bus_null_get_probe_order(device_t dev, device_t child) { panic("bhnd_bus_get_probe_order unimplemented"); } static int bhnd_bus_null_get_port_rid(device_t dev, device_t child, bhnd_port_type port_type, u_int port, u_int region) { return (-1); } static int bhnd_bus_null_decode_port_rid(device_t dev, device_t child, int type, int rid, bhnd_port_type *port_type, u_int *port, u_int *region) { return (ENOENT); } static int bhnd_bus_null_get_region_addr(device_t dev, device_t child, bhnd_port_type type, u_int port, u_int region, bhnd_addr_t *addr, bhnd_size_t *size) { return (ENOENT); } static int bhnd_bus_null_get_nvram_var(device_t dev, device_t child, const char *name, void *buf, size_t *size, bhnd_nvram_type type) { return (ENODEV); } } /** * Return the bhnd(4) bus driver's device enumeration parser class. * * @param driver The bhnd bus driver instance. */ STATICMETHOD bhnd_erom_class_t * get_erom_class { driver_t *driver; } DEFAULT bhnd_bus_null_get_erom_class; /** * Return the active host bridge core for the bhnd bus, if any. * * @param dev The bhnd bus device. * * @retval device_t if a hostb device exists * @retval NULL if no hostb device is found. */ METHOD device_t find_hostb_device { device_t dev; } DEFAULT bhnd_bus_null_find_hostb_device; /** * Return true if the hardware components required by @p child are unpopulated * or otherwise unusable. * * In some cases, enumerated devices may have pins that are left floating, or * the hardware may otherwise be non-functional; this method allows a parent * device to explicitly specify if a successfully enumerated @p child should * be disabled. * * @param dev The device whose child is being examined. * @param child The child device. */ METHOD bool is_hw_disabled { device_t dev; device_t child; } DEFAULT bhnd_bus_null_is_hw_disabled; /** * Return the probe (and attach) order for @p child. * * All devices on the bhnd(4) bus will be probed, attached, or resumed in * ascending order; they will be suspended, shutdown, and detached in * descending order. * * The following device methods will be dispatched in ascending probe order * by the bus: * * - DEVICE_PROBE() * - DEVICE_ATTACH() * - DEVICE_RESUME() * * The following device methods will be dispatched in descending probe order * by the bus: * * - DEVICE_SHUTDOWN() * - DEVICE_DETACH() * - DEVICE_SUSPEND() * * @param dev The device whose child is being examined. * @param child The child device. * * Refer to BHND_PROBE_* and BHND_PROBE_ORDER_* for the standard set of * priorities. */ METHOD int get_probe_order { device_t dev; device_t child; } DEFAULT bhnd_bus_null_get_probe_order; /** * Return the BHND chip identification for the parent bus. * * @param dev The device whose child is being examined. * @param child The child device. */ METHOD const struct bhnd_chipid * get_chipid { device_t dev; device_t child; } DEFAULT bhnd_bus_null_get_chipid; /** * Return the BHND attachment type of the parent bus. * * @param dev The device whose child is being examined. * @param child The child device. * * @retval BHND_ATTACH_ADAPTER if the bus is resident on a bridged adapter, * such as a WiFi chipset. * @retval BHND_ATTACH_NATIVE if the bus provides hardware services (clock, * CPU, etc) to a directly attached native host. */ METHOD bhnd_attach_type get_attach_type { device_t dev; device_t child; } DEFAULT bhnd_bus_null_get_attach_type; /** * Attempt to read the BHND board identification from the parent bus. * * This relies on NVRAM access, and will fail if a valid NVRAM device cannot * be found, or is not yet attached. * * @param dev The parent of @p child. * @param child The bhnd device requesting board info. * @param[out] info On success, will be populated with the bhnd(4) device's * board information. * * @retval 0 success * @retval ENODEV No valid NVRAM source could be found. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ METHOD int read_board_info { device_t dev; device_t child; struct bhnd_board_info *info; } DEFAULT bhnd_bus_null_read_board_info; /** - * Allocate and zero-initialize a buffer suitably sized and aligned for a - * bhnd_devinfo structure. - * - * @param dev The bhnd bus device. - * - * @retval non-NULL success - * @retval NULL allocation failed - */ -METHOD struct bhnd_devinfo * alloc_devinfo { - device_t dev; -}; - -/** - * Release memory previously allocated for @p devinfo. - * - * @param dev The bhnd bus device. - * @param dinfo A devinfo buffer previously allocated via - * BHND_BUS_ALLOC_DEVINFO(). - */ -METHOD void free_devinfo { - device_t dev; - struct bhnd_devinfo *dinfo; -}; - - -/** * Return the number of interrupts to be assigned to @p child via * BHND_BUS_ASSIGN_INTR(). * * @param dev The bhnd bus parent of @p child. * @param child The bhnd device for which a count should be returned. * * @retval 0 If no interrupts should be assigned. * @retval non-zero The count of interrupt resource IDs to be * assigned, starting at rid 0. */ METHOD int get_intr_count { device_t dev; device_t child; } DEFAULT bhnd_bus_null_get_intr_count; /** * Assign an interrupt to @p child via bus_set_resource(). * * The default bus implementation of this method should assign backplane * interrupt values to @p child. * * Bridge-attached bus implementations may instead override standard * interconnect IRQ assignment, providing IRQs inherited from the parent bus. * * TODO: Once we can depend on INTRNG, investigate replacing this with a * bridge-level interrupt controller. * * @param dev The bhnd bus parent of @p child. * @param child The bhnd device to which an interrupt should be assigned. * @param rid The interrupt resource ID to be assigned. * * @retval 0 If an interrupt was assigned. * @retval non-zero If assigning an interrupt otherwise fails, a regular * unix error code will be returned. */ METHOD int assign_intr { device_t dev; device_t child; int rid; } DEFAULT bhnd_bus_null_assign_intr; /** * Return the backplane interrupt vector corresponding to @p child's given * @p intr number. * * @param dev The bhnd bus parent of @p child. * @param child The bhnd device for which the assigned interrupt vector should * be queried. * @param intr The interrupt number being queried. This is equivalent to the * bus resource ID for the interrupt. * @param[out] ivec On success, the assigned hardware interrupt vector be * written to this pointer. * * On bcma(4) devices, this returns the OOB bus line assigned to the * interrupt. * * On siba(4) devices, this returns the target OCP slave flag number assigned * to the interrupt. * * @retval 0 success * @retval ENXIO If @p intr exceeds the number of interrupts available * to @p child. */ METHOD int get_core_ivec { device_t dev; device_t child; u_int intr; uint32_t *ivec; } DEFAULT bhnd_bus_null_get_core_ivec; /** * Notify a bhnd bus that a child was added. * * This method must be called by concrete bhnd(4) driver impementations * after @p child's bus state is fully initialized. * * @param dev The bhnd bus whose child is being added. * @param child The child added to @p dev. */ METHOD void child_added { device_t dev; device_t child; } DEFAULT bhnd_bus_null_child_added; /** - * Reset the device's hardware core. + * Read the current value of @p child's I/O control register. * - * @param dev The parent of @p child. + * @param dev The bhnd bus parent of @p child. + * @param child The bhnd device for which the I/O control register should be + * read. + * @param[out] ioctl On success, the I/O control register value. + * + * @retval 0 success + * @retval EINVAL If @p child is not a direct child of @p dev. + * @retval ENODEV If agent/config space for @p child is unavailable. + * @retval non-zero If reading the IOCTL register otherwise fails, a regular + * unix error code will be returned. + */ +METHOD int read_ioctl { + device_t dev; + device_t child; + uint16_t *ioctl; +} DEFAULT bhnd_bus_null_read_ioctl; + +/** + * Write @p value with @p mask to @p child's I/O control register. + * + * @param dev The bhnd bus parent of @p child. + * @param child The bhnd device for which the I/O control register should + * be updated. + * @param value The value to be written (see also BHND_IOCTL_*). + * @param mask Only the bits defined by @p mask will be updated from @p value. + * + * @retval 0 success + * @retval EINVAL If @p child is not a direct child of @p dev. + * @retval ENODEV If agent/config space for @p child is unavailable. + * @retval non-zero If writing the IOCTL register otherwise fails, a regular + * unix error code will be returned. + */ +METHOD int write_ioctl { + device_t dev; + device_t child; + uint16_t value; + uint16_t mask; +} DEFAULT bhnd_bus_null_write_ioctl; + +/** + * Read the current value of @p child's I/O status register. + * + * @param dev The bhnd bus parent of @p child. + * @param child The bhnd device for which the I/O status register should be + * read. + * @param[out] iost On success, the I/O status register value. + * + * @retval 0 success + * @retval EINVAL If @p child is not a direct child of @p dev. + * @retval ENODEV If agent/config space for @p child is unavailable. + * @retval non-zero If reading the IOST register otherwise fails, a regular + * unix error code will be returned. + */ +METHOD int read_iost { + device_t dev; + device_t child; + uint16_t *iost; +} DEFAULT bhnd_bus_null_read_iost; + + +/** + * Return true if the given bhnd device's hardware is currently held + * in a RESET state or otherwise not clocked (BHND_IOCTL_CLK_EN). + * + * @param dev The bhnd bus parent of @p child. + * @param child The device to query. + * + * @retval true If @p child is held in RESET or not clocked (BHND_IOCTL_CLK_EN), + * or an error occured determining @p child's hardware state. + * @retval false If @p child is clocked and is not held in RESET. + */ +METHOD bool is_hw_suspended { + device_t dev; + device_t child; +} DEFAULT bhnd_bus_null_is_hw_suspended; + +/** + * Place the bhnd(4) device's hardware into a reset state, and then bring the + * hardware out of reset with BHND_IOCTL_CLK_EN and @p ioctl flags set. + * + * Any clock or resource PMU requests previously made by @p child will be + * invalidated. + * + * @param dev The bhnd bus parent of @p child. * @param child The device to be reset. - * @param flags Device-specific core flags to be supplied on reset. + * @param ioctl Device-specific core ioctl flags to be supplied on reset + * (see BHND_IOCTL_*). * * @retval 0 success * @retval non-zero error */ -METHOD int reset_core { +METHOD int reset_hw { device_t dev; device_t child; - uint16_t flags; -} + uint16_t ioctl; +} DEFAULT bhnd_bus_null_reset_hw; /** - * Suspend a device hardware core. + * Suspend @p child's hardware in a low-power reset state. * - * @param dev The parent of @p child. - * @param child The device to be reset. + * Any clock or resource PMU requests previously made by @p dev will be + * invalidated. * + * The hardware may be brought out of reset via bhnd_reset_hw(). + * + * @param dev The bhnd bus parent of @P child. + * @param dev The device to be suspended. + * * @retval 0 success * @retval non-zero error */ -METHOD int suspend_core { +METHOD int suspend_hw { device_t dev; device_t child; -} +} DEFAULT bhnd_bus_null_suspend_hw; /** * If supported by the chipset, return the clock source for the given clock. * * This function is only supported on early PWRCTL-equipped chipsets * that expose clock management via their host bridge interface. Currently, * this includes PCI (not PCIe) devices, with ChipCommon core revisions 0-9. * * @param dev The parent of @p child. * @param child The bhnd device requesting a clock source. * @param clock The clock for which a clock source will be returned. * * @retval bhnd_clksrc The clock source for @p clock. * @retval BHND_CLKSRC_UNKNOWN If @p clock is unsupported, or its * clock source is not known to the bus. */ METHOD bhnd_clksrc pwrctl_get_clksrc { device_t dev; device_t child; bhnd_clock clock; } DEFAULT bhnd_bus_null_pwrctl_get_clksrc; /** * If supported by the chipset, gate the clock source for @p clock * * This function is only supported on early PWRCTL-equipped chipsets * that expose clock management via their host bridge interface. Currently, * this includes PCI (not PCIe) devices, with ChipCommon core revisions 0-9. * * @param dev The parent of @p child. * @param child The bhnd device requesting clock gating. * @param clock The clock to be disabled. * * @retval 0 success * @retval ENODEV If bus-level clock source management is not supported. * @retval ENXIO If bus-level management of @p clock is not supported. */ METHOD int pwrctl_gate_clock { device_t dev; device_t child; bhnd_clock clock; } DEFAULT bhnd_bus_null_pwrctl_gate_clock; /** * If supported by the chipset, ungate the clock source for @p clock * * This function is only supported on early PWRCTL-equipped chipsets * that expose clock management via their host bridge interface. Currently, * this includes PCI (not PCIe) devices, with ChipCommon core revisions 0-9. * * @param dev The parent of @p child. * @param child The bhnd device requesting clock gating. * @param clock The clock to be enabled. * * @retval 0 success * @retval ENODEV If bus-level clock source management is not supported. * @retval ENXIO If bus-level management of @p clock is not supported. */ METHOD int pwrctl_ungate_clock { device_t dev; device_t child; bhnd_clock clock; } DEFAULT bhnd_bus_null_pwrctl_ungate_clock; /** * Allocate and enable per-core PMU request handling for @p child. * * The region containing the core's PMU register block (if any) must be * allocated via bus_alloc_resource(9) (or bhnd_alloc_resource) before * calling BHND_BUS_ALLOC_PMU(), and must not be released until after * calling BHND_BUS_RELEASE_PMU(). * * @param dev The parent of @p child. * @param child The requesting bhnd device. */ METHOD int alloc_pmu { device_t dev; device_t child; } DEFAULT bhnd_bus_null_alloc_pmu; /** * Release per-core PMU resources allocated for @p child. Any * outstanding PMU requests are discarded. * * @param dev The parent of @p child. * @param child The requesting bhnd device. */ METHOD int release_pmu { device_t dev; device_t child; } DEFAULT bhnd_bus_null_release_pmu; /** * Request that @p clock (or faster) be routed to @p child. * - * A driver must ask the bhnd bus to allocate PMU request state + * @note A driver must ask the bhnd bus to allocate PMU request state * via BHND_BUS_ALLOC_PMU() before it can request clock resources. - * - * Request multiplexing is managed by the bus. * + * @note Any outstanding PMU clock requests will be discarded upon calling + * BHND_BUS_RESET_HW() or BHND_BUS_SUSPEND_HW(). + * * @param dev The parent of @p child. * @param child The bhnd device requesting @p clock. * @param clock The requested clock source. * * @retval 0 success * @retval ENODEV If an unsupported clock was requested. * @retval ENXIO If the PMU has not been initialized or is otherwise unvailable. */ METHOD int request_clock { device_t dev; device_t child; bhnd_clock clock; } DEFAULT bhnd_bus_null_request_clock; /** * Request that @p clocks be powered on behalf of @p child. * * This will power on clock sources (e.g. XTAL, PLL, etc) required for * @p clocks and wait until they are ready, discarding any previous * requests by @p child. * - * Request multiplexing is managed by the bus. - * - * A driver must ask the bhnd bus to allocate PMU request state + * @note A driver must ask the bhnd bus to allocate PMU request state * via BHND_BUS_ALLOC_PMU() before it can request clock resources. * + * @note Any outstanding PMU clock requests will be discarded upon calling + * BHND_BUS_RESET_HW() or BHND_BUS_SUSPEND_HW(). + * * @param dev The parent of @p child. * @param child The bhnd device requesting @p clock. * @param clock The requested clock source. * * @retval 0 success * @retval ENODEV If an unsupported clock was requested. * @retval ENXIO If the PMU has not been initialized or is otherwise unvailable. */ METHOD int enable_clocks { device_t dev; device_t child; uint32_t clocks; } DEFAULT bhnd_bus_null_enable_clocks; /** * Power up an external PMU-managed resource assigned to @p child. * - * A driver must ask the bhnd bus to allocate PMU request state + * @note A driver must ask the bhnd bus to allocate PMU request state * via BHND_BUS_ALLOC_PMU() before it can request PMU resources. * + * @note Any outstanding PMU resource requests will be released upon calling + * BHND_BUS_RESET_HW() or BHND_BUS_SUSPEND_HW(). + * * @param dev The parent of @p child. * @param child The bhnd device requesting @p rsrc. * @param rsrc The core-specific external resource identifier. * * @retval 0 success * @retval ENODEV If the PMU does not support @p rsrc. * @retval ENXIO If the PMU has not been initialized or is otherwise unvailable. */ METHOD int request_ext_rsrc { device_t dev; device_t child; u_int rsrc; } DEFAULT bhnd_bus_null_request_ext_rsrc; /** * Power down an external PMU-managed resource assigned to @p child. * - * A driver must ask the bhnd bus to allocate PMU request state + * @note A driver must ask the bhnd bus to allocate PMU request state * via BHND_BUS_ALLOC_PMU() before it can request PMU resources. * * @param dev The parent of @p child. * @param child The bhnd device requesting @p rsrc. * @param rsrc The core-specific external resource number. * * @retval 0 success * @retval ENODEV If the PMU does not support @p rsrc. * @retval ENXIO If the PMU has not been initialized or is otherwise unvailable. */ METHOD int release_ext_rsrc { device_t dev; device_t child; u_int rsrc; } DEFAULT bhnd_bus_null_release_ext_rsrc; /** * Read @p width bytes at @p offset from the bus-specific agent/config * space of @p child. * * @param dev The parent of @p child. * @param child The bhnd device for which @p offset should be read. * @param offset The offset to be read. + * @param[out] value On success, the bytes read at @p offset. * @param width The size of the access. Must be 1, 2 or 4 bytes. * * The exact behavior of this method is bus-specific. On a bcma(4) bus, this * method provides access to the first agent port of @p child; on a siba(4) bus, * this method provides access to the core's CFG0 register block. * * @note Device drivers should only use this API for functionality * that is not available via another bhnd(4) function. + * + * @retval 0 success + * @retval EINVAL If @p child is not a direct child of @p dev. + * @retval EINVAL If @p width is not one of 1, 2, or 4 bytes. + * @retval ENODEV If accessing agent/config space for @p child is unsupported. + * @retval EFAULT If reading @p width at @p offset exceeds the bounds of + * the mapped agent/config space for @p child. */ -METHOD uint32_t read_config { +METHOD int read_config { device_t dev; device_t child; bus_size_t offset; + void *value; u_int width; } DEFAULT bhnd_bus_null_read_config; /** * Read @p width bytes at @p offset from the bus-specific agent/config * space of @p child. * * @param dev The parent of @p child. * @param child The bhnd device for which @p offset should be read. * @param offset The offset to be written. - * @param width The size of the access. Must be 1, 2 or 4 bytes. + * @param value A pointer to the value to be written. + * @param width The size of @p value. Must be 1, 2 or 4 bytes. * * The exact behavior of this method is bus-specific. In the case of * bcma(4), this method provides access to the first agent port of @p child. * * @note Device drivers should only use this API for functionality * that is not available via another bhnd(4) function. + * + * @retval 0 success + * @retval EINVAL If @p child is not a direct child of @p dev. + * @retval EINVAL If @p width is not one of 1, 2, or 4 bytes. + * @retval ENODEV If accessing agent/config space for @p child is unsupported. + * @retval EFAULT If reading @p width at @p offset exceeds the bounds of + * the mapped agent/config space for @p child. */ -METHOD void write_config { +METHOD int write_config { device_t dev; device_t child; bus_size_t offset; - uint32_t val; + const void *value; u_int width; } DEFAULT bhnd_bus_null_write_config; /** * Allocate a bhnd resource. * * This method's semantics are functionally identical to the bus API of the same * name; refer to BUS_ALLOC_RESOURCE for complete documentation. */ METHOD struct bhnd_resource * alloc_resource { device_t dev; device_t child; int type; int *rid; rman_res_t start; rman_res_t end; rman_res_t count; u_int flags; } DEFAULT bhnd_bus_generic_alloc_resource; /** * Release a bhnd resource. * * This method's semantics are functionally identical to the bus API of the same * name; refer to BUS_RELEASE_RESOURCE for complete documentation. */ METHOD int release_resource { device_t dev; device_t child; int type; int rid; struct bhnd_resource *res; } DEFAULT bhnd_bus_generic_release_resource; /** * Activate a bhnd resource. * * This method's semantics are functionally identical to the bus API of the same * name; refer to BUS_ACTIVATE_RESOURCE for complete documentation. */ METHOD int activate_resource { device_t dev; device_t child; int type; int rid; struct bhnd_resource *r; } DEFAULT bhnd_bus_generic_activate_resource; /** * Deactivate a bhnd resource. * * This method's semantics are functionally identical to the bus API of the same * name; refer to BUS_DEACTIVATE_RESOURCE for complete documentation. */ METHOD int deactivate_resource { device_t dev; device_t child; int type; int rid; struct bhnd_resource *r; } DEFAULT bhnd_bus_generic_deactivate_resource; /** * Return true if @p region_num is a valid region on @p port_num of * @p type attached to @p child. * * @param dev The device whose child is being examined. * @param child The child device. * @param type The port type being queried. * @param port_num The port number being queried. * @param region_num The region number being queried. */ METHOD bool is_region_valid { device_t dev; device_t child; bhnd_port_type type; u_int port_num; u_int region_num; }; /** * Return the number of ports of type @p type attached to @p child. * * @param dev The device whose child is being examined. * @param child The child device. * @param type The port type being queried. */ METHOD u_int get_port_count { device_t dev; device_t child; bhnd_port_type type; }; /** * Return the number of memory regions mapped to @p child @p port of * type @p type. * * @param dev The device whose child is being examined. * @param child The child device. * @param port The port number being queried. * @param type The port type being queried. */ METHOD u_int get_region_count { device_t dev; device_t child; bhnd_port_type type; u_int port; }; /** * Return the SYS_RES_MEMORY resource-ID for a port/region pair attached to * @p child. * * @param dev The bus device. * @param child The bhnd child. * @param port_type The port type. * @param port_num The index of the child interconnect port. * @param region_num The index of the port-mapped address region. * * @retval -1 No such port/region found. */ METHOD int get_port_rid { device_t dev; device_t child; bhnd_port_type port_type; u_int port_num; u_int region_num; } DEFAULT bhnd_bus_null_get_port_rid; /** * Decode a port / region pair on @p child defined by @p type and @p rid. * * @param dev The bus device. * @param child The bhnd child. * @param type The resource type. * @param rid The resource ID. * @param[out] port_type The port's type. * @param[out] port The port identifier. * @param[out] region The identifier of the memory region on @p port. * * @retval 0 success * @retval non-zero No matching type/rid found. */ METHOD int decode_port_rid { device_t dev; device_t child; int type; int rid; bhnd_port_type *port_type; u_int *port; u_int *region; } DEFAULT bhnd_bus_null_decode_port_rid; /** * Get the address and size of @p region on @p port. * * @param dev The bus device. * @param child The bhnd child. * @param port_type The port type. * @param port The port identifier. * @param region The identifier of the memory region on @p port. * @param[out] region_addr The region's base address. * @param[out] region_size The region's size. * * @retval 0 success * @retval non-zero No matching port/region found. */ METHOD int get_region_addr { device_t dev; device_t child; bhnd_port_type port_type; u_int port; u_int region; bhnd_addr_t *region_addr; bhnd_size_t *region_size; } DEFAULT bhnd_bus_null_get_region_addr; /** * Read an NVRAM variable. * * It is the responsibility of the bus to delegate this request to * the appropriate NVRAM child device, or to a parent bus implementation. * * @param dev The bus device. * @param child The requesting device. * @param name The NVRAM variable name. * @param[out] buf On success, the requested value will be written * to this buffer. This argment may be NULL if * the value is not desired. * @param[in,out] size The capacity of @p buf. On success, will be set * to the actual size of the requested value. * @param type The data type to be written to @p buf. * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENOMEM If @p buf is non-NULL and a buffer of @p size is too * small to hold the requested value. * @retval ENODEV No valid NVRAM source could be found. * @retval EFTYPE If the @p name's data type cannot be coerced to @p type. * @retval ERANGE If value coercion would overflow @p type. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ METHOD int get_nvram_var { device_t dev; device_t child; const char *name; void *buf; size_t *size; bhnd_nvram_type type; } DEFAULT bhnd_bus_null_get_nvram_var; /** An implementation of bus_read_1() compatible with bhnd_resource */ METHOD uint8_t read_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; } /** An implementation of bus_read_2() compatible with bhnd_resource */ METHOD uint16_t read_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; } /** An implementation of bus_read_4() compatible with bhnd_resource */ METHOD uint32_t read_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; } /** An implementation of bus_write_1() compatible with bhnd_resource */ METHOD void write_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t value; } /** An implementation of bus_write_2() compatible with bhnd_resource */ METHOD void write_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t value; } /** An implementation of bus_write_4() compatible with bhnd_resource */ METHOD void write_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t value; } /** An implementation of bus_read_stream_1() compatible with bhnd_resource */ METHOD uint8_t read_stream_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; } /** An implementation of bus_read_stream_2() compatible with bhnd_resource */ METHOD uint16_t read_stream_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; } /** An implementation of bus_read_stream_4() compatible with bhnd_resource */ METHOD uint32_t read_stream_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; } /** An implementation of bus_write_stream_1() compatible with bhnd_resource */ METHOD void write_stream_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t value; } /** An implementation of bus_write_stream_2() compatible with bhnd_resource */ METHOD void write_stream_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t value; } /** An implementation of bus_write_stream_4() compatible with bhnd_resource */ METHOD void write_stream_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t value; } /** An implementation of bus_read_multi_1() compatible with bhnd_resource */ METHOD void read_multi_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_read_multi_2() compatible with bhnd_resource */ METHOD void read_multi_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_read_multi_4() compatible with bhnd_resource */ METHOD void read_multi_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_write_multi_1() compatible with bhnd_resource */ METHOD void write_multi_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_write_multi_2() compatible with bhnd_resource */ METHOD void write_multi_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_write_multi_4() compatible with bhnd_resource */ METHOD void write_multi_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_read_multi_stream_1() compatible * bhnd_resource */ METHOD void read_multi_stream_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_read_multi_stream_2() compatible * bhnd_resource */ METHOD void read_multi_stream_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_read_multi_stream_4() compatible * bhnd_resource */ METHOD void read_multi_stream_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_write_multi_stream_1() compatible * bhnd_resource */ METHOD void write_multi_stream_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_write_multi_stream_2() compatible with * bhnd_resource */ METHOD void write_multi_stream_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_write_multi_stream_4() compatible with * bhnd_resource */ METHOD void write_multi_stream_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_set_multi_1() compatible with bhnd_resource */ METHOD void set_multi_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t value; bus_size_t count; } /** An implementation of bus_set_multi_2() compatible with bhnd_resource */ METHOD void set_multi_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t value; bus_size_t count; } /** An implementation of bus_set_multi_4() compatible with bhnd_resource */ METHOD void set_multi_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t value; bus_size_t count; } /** An implementation of bus_set_region_1() compatible with bhnd_resource */ METHOD void set_region_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t value; bus_size_t count; } /** An implementation of bus_set_region_2() compatible with bhnd_resource */ METHOD void set_region_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t value; bus_size_t count; } /** An implementation of bus_set_region_4() compatible with bhnd_resource */ METHOD void set_region_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t value; bus_size_t count; } /** An implementation of bus_read_region_1() compatible with bhnd_resource */ METHOD void read_region_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_read_region_2() compatible with bhnd_resource */ METHOD void read_region_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_read_region_4() compatible with bhnd_resource */ METHOD void read_region_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_read_region_stream_1() compatible with * bhnd_resource */ METHOD void read_region_stream_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_read_region_stream_2() compatible with * bhnd_resource */ METHOD void read_region_stream_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_read_region_stream_4() compatible with * bhnd_resource */ METHOD void read_region_stream_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_write_region_1() compatible with bhnd_resource */ METHOD void write_region_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_write_region_2() compatible with bhnd_resource */ METHOD void write_region_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_write_region_4() compatible with bhnd_resource */ METHOD void write_region_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_write_region_stream_1() compatible with * bhnd_resource */ METHOD void write_region_stream_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_write_region_stream_2() compatible with * bhnd_resource */ METHOD void write_region_stream_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_write_region_stream_4() compatible with * bhnd_resource */ METHOD void write_region_stream_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_barrier() compatible with bhnd_resource */ METHOD void barrier { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; bus_size_t length; int flags; } Index: head/sys/dev/bhnd/bhndvar.h =================================================================== --- head/sys/dev/bhnd/bhndvar.h (revision 306286) +++ head/sys/dev/bhnd/bhndvar.h (revision 306287) @@ -1,115 +1,101 @@ /*- * Copyright (c) 2015-2016 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. * * $FreeBSD$ */ #ifndef _BHND_BHNDVAR_H_ #define _BHND_BHNDVAR_H_ #include #include #include #include "bhnd.h" /* * Definitions shared by bhnd(4) bus and bhndb(4) bridge driver implementations. */ MALLOC_DECLARE(M_BHND); DECLARE_CLASS(bhnd_driver); -struct bhnd_core_pmu_info; - int bhnd_generic_attach(device_t dev); int bhnd_generic_detach(device_t dev); int bhnd_generic_shutdown(device_t dev); int bhnd_generic_resume(device_t dev); int bhnd_generic_suspend(device_t dev); int bhnd_generic_get_probe_order(device_t dev, device_t child); int bhnd_generic_alloc_pmu(device_t dev, device_t child); int bhnd_generic_release_pmu(device_t dev, device_t child); int bhnd_generic_request_clock(device_t dev, device_t child, bhnd_clock clock); int bhnd_generic_enable_clocks(device_t dev, device_t child, uint32_t clocks); int bhnd_generic_request_ext_rsrc(device_t dev, device_t child, u_int rsrc); int bhnd_generic_release_ext_rsrc(device_t dev, device_t child, u_int rsrc); int bhnd_generic_print_child(device_t dev, device_t child); void bhnd_generic_probe_nomatch(device_t dev, device_t child); -device_t bhnd_generic_add_child(device_t dev, u_int order, - const char *name, int unit); -void bhnd_generic_child_added(device_t dev, device_t child); void bhnd_generic_child_deleted(device_t dev, device_t child); int bhnd_generic_suspend_child(device_t dev, device_t child); int bhnd_generic_resume_child(device_t dev, device_t child); int bhnd_generic_get_nvram_var(device_t dev, device_t child, const char *name, void *buf, size_t *size, bhnd_nvram_type type); - - -/** - * bhnd per-device info. Must be first member of all subclass - * devinfo structures. - */ -struct bhnd_devinfo { - struct bhnd_core_pmu_info *pmu_info; /**< PMU info, or NULL */ -}; /** * bhnd driver instance state. Must be first member of all subclass * softc structures. */ struct bhnd_softc { device_t dev; /**< bus device */ bool attach_done; /**< true if initialization of * all platform devices has * been completed */ device_t chipc_dev; /**< bhnd_chipc device */ device_t nvram_dev; /**< bhnd_nvram device, if any */ device_t pmu_dev; /**< bhnd_pmu device, if any */ }; #endif /* _BHND_BHNDVAR_H_ */ Index: head/sys/dev/bhnd/cores/pmu/bhnd_pmu.c =================================================================== --- head/sys/dev/bhnd/cores/pmu/bhnd_pmu.c (revision 306286) +++ head/sys/dev/bhnd/cores/pmu/bhnd_pmu.c (revision 306287) @@ -1,508 +1,525 @@ /*- * Copyright (c) 2015-2016 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include "bhnd_nvram_map.h" #include "bhnd_pmureg.h" #include "bhnd_pmuvar.h" #include "bhnd_pmu_private.h" /* * Broadcom PMU driver. * * On modern BHND chipsets, the PMU, GCI, and SRENG (Save/Restore Engine?) * register blocks are found within a dedicated PMU core (attached via * the AHB 'always on bus'). * * On earlier chipsets, these register blocks are found at the same * offsets within the ChipCommon core. */ devclass_t bhnd_pmu_devclass; /**< bhnd(4) PMU device class */ static int bhnd_pmu_sysctl_bus_freq(SYSCTL_HANDLER_ARGS); static int bhnd_pmu_sysctl_cpu_freq(SYSCTL_HANDLER_ARGS); static int bhnd_pmu_sysctl_mem_freq(SYSCTL_HANDLER_ARGS); static uint32_t bhnd_pmu_read_4(bus_size_t reg, void *ctx); static void bhnd_pmu_write_4(bus_size_t reg, uint32_t val, void *ctx); static uint32_t bhnd_pmu_read_chipst(void *ctx); static const struct bhnd_pmu_io bhnd_pmu_res_io = { .rd4 = bhnd_pmu_read_4, .wr4 = bhnd_pmu_write_4, .rd_chipst = bhnd_pmu_read_chipst }; +#define BPMU_ASSERT_CLKCTL_AVAIL(_pinfo) \ + KASSERT(!bhnd_is_hw_suspended((_pinfo)->pm_dev), \ + ("reading clkctl on suspended core will trigger system livelock")) + #define BPMU_CLKCTL_READ_4(_pinfo) \ bhnd_bus_read_4((_pinfo)->pm_res, (_pinfo)->pm_regs) #define BPMU_CLKCTL_WRITE_4(_pinfo, _val) \ bhnd_bus_write_4((_pinfo)->pm_res, (_pinfo)->pm_regs, (_val)) #define BPMU_CLKCTL_SET_4(_pinfo, _val, _mask) \ BPMU_CLKCTL_WRITE_4((_pinfo), \ ((_val) & (_mask)) | (BPMU_CLKCTL_READ_4(_pinfo) & ~(_mask))) /** * Default bhnd_pmu driver implementation of DEVICE_PROBE(). */ int bhnd_pmu_probe(device_t dev) { return (BUS_PROBE_DEFAULT); } /** * Default bhnd_pmu driver implementation of DEVICE_ATTACH(). * * @param dev PMU device. * @param res The PMU device registers. The driver will maintain a borrowed * reference to this resource for the lifetime of the device. */ int bhnd_pmu_attach(device_t dev, struct bhnd_resource *res) { struct bhnd_pmu_softc *sc; struct sysctl_ctx_list *ctx; struct sysctl_oid *tree; devclass_t bhnd_class; device_t core, bus; int error; sc = device_get_softc(dev); sc->dev = dev; sc->quirks = 0; sc->res = res; /* Fetch capability flags */ sc->caps = bhnd_bus_read_4(sc->res, BHND_PMU_CAP); /* Find the bus-attached core */ bhnd_class = devclass_find("bhnd"); core = sc->dev; while ((bus = device_get_parent(core)) != NULL) { if (device_get_devclass(bus) == bhnd_class) break; core = bus; } if (core == NULL) { device_printf(sc->dev, "bhnd bus not found\n"); return (ENXIO); } /* Fetch chip and board info */ sc->cid = *bhnd_get_chipid(core); if ((error = bhnd_read_board_info(core, &sc->board))) { device_printf(sc->dev, "error fetching board info: %d\n", error); return (ENXIO); } /* Locate ChipCommon device */ sc->chipc_dev = bhnd_find_child(bus, BHND_DEVCLASS_CC, 0); if (sc->chipc_dev == NULL) { device_printf(sc->dev, "chipcommon device not found\n"); return (ENXIO); } /* Initialize query state */ error = bhnd_pmu_query_init(&sc->query, dev, sc->cid, &bhnd_pmu_res_io, sc); if (error) return (error); sc->io = sc->query.io; sc->io_ctx = sc->query.io_ctx; BPMU_LOCK_INIT(sc); /* Set quirk flags */ switch (sc->cid.chip_id) { case BHND_CHIPID_BCM4328: case BHND_CHIPID_BCM5354: /* HTAVAIL/ALPAVAIL are bitswapped in CLKCTL */ sc->quirks |= BPMU_QUIRK_CLKCTL_CCS0; break; default: break; } /* Initialize PMU */ if ((error = bhnd_pmu_init(sc))) { device_printf(sc->dev, "PMU init failed: %d\n", error); goto failed; } /* Set up sysctl nodes */ ctx = device_get_sysctl_ctx(dev); tree = device_get_sysctl_tree(dev); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "bus_freq", CTLTYPE_UINT | CTLFLAG_RD, sc, 0, bhnd_pmu_sysctl_bus_freq, "IU", "Bus clock frequency"); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "cpu_freq", CTLTYPE_UINT | CTLFLAG_RD, sc, 0, bhnd_pmu_sysctl_cpu_freq, "IU", "CPU clock frequency"); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "mem_freq", CTLTYPE_UINT | CTLFLAG_RD, sc, 0, bhnd_pmu_sysctl_mem_freq, "IU", "Memory clock frequency"); return (0); failed: BPMU_LOCK_DESTROY(sc); bhnd_pmu_query_fini(&sc->query); return (error); } /** * Default bhnd_pmu driver implementation of DEVICE_DETACH(). */ int bhnd_pmu_detach(device_t dev) { struct bhnd_pmu_softc *sc; sc = device_get_softc(dev); BPMU_LOCK_DESTROY(sc); bhnd_pmu_query_fini(&sc->query); return (0); } /** * Default bhnd_pmu driver implementation of DEVICE_SUSPEND(). */ int bhnd_pmu_suspend(device_t dev) { return (0); } /** * Default bhnd_pmu driver implementation of DEVICE_RESUME(). */ int bhnd_pmu_resume(device_t dev) { struct bhnd_pmu_softc *sc; int error; sc = device_get_softc(dev); /* Re-initialize PMU */ if ((error = bhnd_pmu_init(sc))) { device_printf(sc->dev, "PMU init failed: %d\n", error); return (error); } return (0); } static int bhnd_pmu_sysctl_bus_freq(SYSCTL_HANDLER_ARGS) { struct bhnd_pmu_softc *sc; uint32_t freq; sc = arg1; BPMU_LOCK(sc); freq = bhnd_pmu_si_clock(&sc->query); BPMU_UNLOCK(sc); return (sysctl_handle_32(oidp, NULL, freq, req)); } static int bhnd_pmu_sysctl_cpu_freq(SYSCTL_HANDLER_ARGS) { struct bhnd_pmu_softc *sc; uint32_t freq; sc = arg1; BPMU_LOCK(sc); freq = bhnd_pmu_cpu_clock(&sc->query); BPMU_UNLOCK(sc); return (sysctl_handle_32(oidp, NULL, freq, req)); } static int bhnd_pmu_sysctl_mem_freq(SYSCTL_HANDLER_ARGS) { struct bhnd_pmu_softc *sc; uint32_t freq; sc = arg1; BPMU_LOCK(sc); freq = bhnd_pmu_mem_clock(&sc->query); BPMU_UNLOCK(sc); return (sysctl_handle_32(oidp, NULL, freq, req)); } static int bhnd_pmu_core_req_clock(device_t dev, struct bhnd_core_pmu_info *pinfo, bhnd_clock clock) { struct bhnd_pmu_softc *sc; uint32_t avail; uint32_t req; + BPMU_ASSERT_CLKCTL_AVAIL(pinfo); + sc = device_get_softc(dev); avail = 0x0; req = 0x0; switch (clock) { case BHND_CLOCK_DYN: break; case BHND_CLOCK_ILP: req |= BHND_CCS_FORCEILP; break; case BHND_CLOCK_ALP: req |= BHND_CCS_FORCEALP; avail |= BHND_CCS_ALPAVAIL; break; case BHND_CLOCK_HT: req |= BHND_CCS_FORCEHT; avail |= BHND_CCS_HTAVAIL; break; default: device_printf(dev, "%s requested unknown clock: %#x\n", device_get_nameunit(pinfo->pm_dev), clock); return (ENODEV); } BPMU_LOCK(sc); /* Issue request */ BPMU_CLKCTL_SET_4(pinfo, req, BHND_CCS_FORCE_MASK); /* Wait for clock availability */ bhnd_pmu_wait_clkst(sc, pinfo->pm_dev, pinfo->pm_res, pinfo->pm_regs, avail, avail); BPMU_UNLOCK(sc); return (0); } static int bhnd_pmu_core_en_clocks(device_t dev, struct bhnd_core_pmu_info *pinfo, uint32_t clocks) { struct bhnd_pmu_softc *sc; uint32_t avail; uint32_t req; + BPMU_ASSERT_CLKCTL_AVAIL(pinfo); + sc = device_get_softc(dev); avail = 0x0; req = 0x0; /* Build clock request flags */ if (clocks & BHND_CLOCK_DYN) /* nothing to enable */ clocks &= ~BHND_CLOCK_DYN; if (clocks & BHND_CLOCK_ILP) /* nothing to enable */ clocks &= ~BHND_CLOCK_ILP; if (clocks & BHND_CLOCK_ALP) { req |= BHND_CCS_ALPAREQ; avail |= BHND_CCS_ALPAVAIL; clocks &= ~BHND_CLOCK_ALP; } if (clocks & BHND_CLOCK_HT) { req |= BHND_CCS_HTAREQ; avail |= BHND_CCS_HTAVAIL; clocks &= ~BHND_CLOCK_HT; } /* Check for unknown clock values */ if (clocks != 0x0) { device_printf(dev, "%s requested unknown clocks: %#x\n", device_get_nameunit(pinfo->pm_dev), clocks); return (ENODEV); } BPMU_LOCK(sc); /* Issue request */ BPMU_CLKCTL_SET_4(pinfo, req, BHND_CCS_AREQ_MASK); /* Wait for clock availability */ bhnd_pmu_wait_clkst(sc, pinfo->pm_dev, pinfo->pm_res, pinfo->pm_regs, avail, avail); BPMU_UNLOCK(sc); return (0); } static int bhnd_pmu_core_req_ext_rsrc(device_t dev, struct bhnd_core_pmu_info *pinfo, u_int rsrc) { struct bhnd_pmu_softc *sc; uint32_t req; uint32_t avail; + BPMU_ASSERT_CLKCTL_AVAIL(pinfo); + sc = device_get_softc(dev); if (rsrc > BHND_CCS_ERSRC_MAX) return (EINVAL); req = BHND_PMU_SET_BITS((1<pm_dev, pinfo->pm_res, pinfo->pm_regs, avail, avail); BPMU_UNLOCK(sc); return (0); } static int bhnd_pmu_core_release_ext_rsrc(device_t dev, struct bhnd_core_pmu_info *pinfo, u_int rsrc) { struct bhnd_pmu_softc *sc; uint32_t mask; + BPMU_ASSERT_CLKCTL_AVAIL(pinfo); + sc = device_get_softc(dev); if (rsrc > BHND_CCS_ERSRC_MAX) return (EINVAL); mask = BHND_PMU_SET_BITS((1<pm_dev)) + return (0); BPMU_LOCK(sc); /* Clear all FORCE, AREQ, and ERSRC flags */ BPMU_CLKCTL_SET_4(pinfo, 0x0, BHND_CCS_FORCE_MASK | BHND_CCS_AREQ_MASK | BHND_CCS_ERSRC_REQ_MASK); BPMU_UNLOCK(sc); return (0); } static uint32_t bhnd_pmu_read_4(bus_size_t reg, void *ctx) { struct bhnd_pmu_softc *sc = ctx; return (bhnd_bus_read_4(sc->res, reg)); } static void bhnd_pmu_write_4(bus_size_t reg, uint32_t val, void *ctx) { struct bhnd_pmu_softc *sc = ctx; return (bhnd_bus_write_4(sc->res, reg, val)); } static uint32_t bhnd_pmu_read_chipst(void *ctx) { struct bhnd_pmu_softc *sc = ctx; return (BHND_CHIPC_READ_CHIPST(sc->chipc_dev)); } static device_method_t bhnd_pmu_methods[] = { /* Device interface */ DEVMETHOD(device_probe, bhnd_pmu_probe), DEVMETHOD(device_detach, bhnd_pmu_detach), DEVMETHOD(device_suspend, bhnd_pmu_suspend), DEVMETHOD(device_resume, bhnd_pmu_resume), /* BHND PMU interface */ DEVMETHOD(bhnd_pmu_core_req_clock, bhnd_pmu_core_req_clock), DEVMETHOD(bhnd_pmu_core_en_clocks, bhnd_pmu_core_en_clocks), DEVMETHOD(bhnd_pmu_core_req_ext_rsrc, bhnd_pmu_core_req_ext_rsrc), DEVMETHOD(bhnd_pmu_core_release_ext_rsrc, bhnd_pmu_core_release_ext_rsrc), DEVMETHOD(bhnd_pmu_core_release, bhnd_pmu_core_release), DEVMETHOD_END }; DEFINE_CLASS_0(bhnd_pmu, bhnd_pmu_driver, bhnd_pmu_methods, sizeof(struct bhnd_pmu_softc)); MODULE_VERSION(bhnd_pmu, 1); Index: head/sys/dev/bhnd/cores/pmu/bhnd_pmu.h =================================================================== --- head/sys/dev/bhnd/cores/pmu/bhnd_pmu.h (revision 306286) +++ head/sys/dev/bhnd/cores/pmu/bhnd_pmu.h (revision 306287) @@ -1,52 +1,54 @@ /*- * Copyright (c) 2016 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. * * $FreeBSD$ */ #ifndef _BHND_CORES_PMU_BHND_PMU_H_ #define _BHND_CORES_PMU_BHND_PMU_H_ #include +#include + #include "bhnd_pmu_if.h" /** * Per-core PMU register information. */ struct bhnd_core_pmu_info { device_t pm_dev; /**< core device */ device_t pm_pmu; /**< PMU device */ struct bhnd_resource *pm_res; /**< Resource containing PMU register block for this device (if any). */ bus_size_t pm_regs; /**< Offset to PMU register * block in @p pm_res */ }; #endif /* _BHND_CORES_PMU_BHND_PMU_H_ */ Index: head/sys/dev/bhnd/cores/pmu/bhnd_pmu_private.h =================================================================== --- head/sys/dev/bhnd/cores/pmu/bhnd_pmu_private.h (revision 306286) +++ head/sys/dev/bhnd/cores/pmu/bhnd_pmu_private.h (revision 306287) @@ -1,138 +1,138 @@ /*- * Copyright (c) 2016 Landon Fuller * Copyright (C) 2010, Broadcom Corporation. * All rights reserved. * * This file is derived from the hndpmu.h header contributed by Broadcom * to to the Linux staging repository, as well as later revisions of hndpmu.h * distributed with the Asus RT-N16 firmware source code release. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ #ifndef _BHND_CORES_PMU_BHND_PMU_PRIVATE_H_ #define _BHND_CORES_PMU_BHND_PMU_PRIVATE_H_ #include #include "bhnd_pmuvar.h" /* Register I/O */ #define BHND_PMU_READ_4(_sc, _reg) (_sc)->io->rd4((_reg), (_sc)->io_ctx) #define BHND_PMU_WRITE_4(_sc, _reg, _val) \ (_sc)->io->wr4((_reg), (_val), (_sc)->io_ctx) #define BHND_PMU_AND_4(_sc, _reg, _val) \ BHND_PMU_WRITE_4((_sc), (_reg), \ BHND_PMU_READ_4((_sc), (_reg)) & (_val)) #define BHND_PMU_OR_4(_sc, _reg, _val) \ BHND_PMU_WRITE_4((_sc), (_reg), \ BHND_PMU_READ_4((_sc), (_reg)) | (_val)) /* Indirect register support */ #define BHND_PMU_IND_READ(_sc, _src, _reg) \ bhnd_pmu_ind_read((_sc)->io, (_sc)->io_ctx, \ BHND_PMU_ ## _src ## _ADDR, BHND_PMU_ ## _src ## _DATA, (_reg)) #define BHND_PMU_IND_WRITE(_sc, _src, _reg, _val, _mask) \ bhnd_pmu_ind_write((_sc)->io, (_sc)->io_ctx, \ BHND_PMU_ ## _src ## _ADDR, \ BHND_PMU_ ## _src ## _DATA, (_reg), (_val), (_mask)) /* Chip Control indirect registers */ #define BHND_PMU_CCTRL_READ(_sc, _reg) \ BHND_PMU_IND_READ((_sc), CHIPCTL, (_reg)) #define BHND_PMU_CCTRL_WRITE(_sc, _reg, _val, _mask) \ BHND_PMU_IND_WRITE((_sc), CHIPCTL, (_reg), (_val), (_mask)) /* Register Control indirect registers */ #define BHND_PMU_REGCTRL_READ(_sc, _reg) \ BHND_PMU_IND_READ((_sc), REG_CONTROL, (_reg)) #define BHND_PMU_REGCTRL_WRITE(_sc, _reg, _val, _mask) \ BHND_PMU_IND_WRITE((_sc), REG_CONTROL, (_reg), (_val), (_mask)) /* PLL Control indirect registers */ #define BHND_PMU_PLL_READ(_sc, _reg) \ BHND_PMU_IND_READ((_sc), PLL_CONTROL, (_reg)) #define BHND_PMU_PLL_WRITE(_sc, _reg, _val, _mask) \ BHND_PMU_IND_WRITE((_sc), PLL_CONTROL, (_reg), (_val), (_mask)) /** FVCO frequencies, in Hz */ enum { FVCO_880 = 880 * 1000, /**< 880MHz */ FVCO_1760 = 1760 * 1000, /**< 1760MHz */ FVCO_1440 = 1440 * 1000, /**< 1440MHz */ FVCO_960 = 960 * 1000, /**< 960MHz */ }; /** LDO voltage tunables */ enum { SET_LDO_VOLTAGE_LDO1 = 1, SET_LDO_VOLTAGE_LDO2 = 2, SET_LDO_VOLTAGE_LDO3 = 3, SET_LDO_VOLTAGE_PAREF = 4, SET_LDO_VOLTAGE_CLDO_PWM = 5, SET_LDO_VOLTAGE_CLDO_BURST = 6, SET_LDO_VOLTAGE_CBUCK_PWM = 7, SET_LDO_VOLTAGE_CBUCK_BURST = 8, SET_LDO_VOLTAGE_LNLDO1 = 9, SET_LDO_VOLTAGE_LNLDO2_SEL = 10, }; uint32_t bhnd_pmu_ind_read(const struct bhnd_pmu_io *io, void *io_ctx, bus_size_t addr, bus_size_t data, uint32_t reg); void bhnd_pmu_ind_write(const struct bhnd_pmu_io *io, void *io_ctx, bus_size_t addr, bus_size_t data, uint32_t reg, uint32_t val, uint32_t mask); bool bhnd_pmu_wait_clkst(struct bhnd_pmu_softc *sc, device_t dev, struct bhnd_resource *r, bus_size_t clkst_reg, uint32_t value, uint32_t mask); int bhnd_pmu_init(struct bhnd_pmu_softc *sc); void bhnd_pmu_pll_init(struct bhnd_pmu_softc *sc, uint32_t xtalfreq); int bhnd_pmu_res_init(struct bhnd_pmu_softc *sc); void bhnd_pmu_swreg_init(struct bhnd_pmu_softc *sc); uint32_t bhnd_pmu_force_ilp(struct bhnd_pmu_softc *sc, bool force); void bhnd_pmu_set_switcher_voltage(struct bhnd_pmu_softc *sc, uint8_t bb_voltage, uint8_t rf_voltage); void bhnd_pmu_set_ldo_voltage(struct bhnd_pmu_softc *sc, uint8_t ldo, uint8_t voltage); int bhnd_pmu_fast_pwrup_delay(struct bhnd_pmu_softc *sc, uint16_t *pwrup_delay); void bhnd_pmu_rcal(struct bhnd_pmu_softc *sc); void bhnd_pmu_spuravoid(struct bhnd_pmu_softc *sc, uint8_t spuravoid); bool bhnd_pmu_is_otp_powered(struct bhnd_pmu_softc *sc); uint32_t bhnd_pmu_measure_alpclk(struct bhnd_pmu_softc *sc); -void bhnd_pmu_radio_enable(struct bhnd_pmu_softc *sc, +int bhnd_pmu_radio_enable(struct bhnd_pmu_softc *sc, device_t d11core, bool enable); uint32_t bhnd_pmu_waitforclk_on_backplane(struct bhnd_pmu_softc *sc, uint32_t clk, uint32_t delay); int bhnd_pmu_otp_power(struct bhnd_pmu_softc *sc, bool on); void bhnd_pmu_sdiod_drive_strength_init(struct bhnd_pmu_softc *sc, uint32_t drivestrength); void bhnd_pmu_paref_ldo_enable(struct bhnd_pmu_softc *sc, bool enable); #endif /* _BHND_CORES_PMU_BHND_PMU_PRIVATE_H_ */ Index: head/sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c =================================================================== --- head/sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c (revision 306286) +++ head/sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c (revision 306287) @@ -1,3508 +1,3518 @@ /*- * Copyright (c) 2016 Landon Fuller * Copyright (C) 2010, Broadcom Corporation. * All rights reserved. * * This file is derived from the hndpmu.c source contributed by Broadcom * to to the Linux staging repository, as well as later revisions of hndpmu.c * distributed with the Asus RT-N16 firmware source code release. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include "bhnd_nvram_map.h" #include "bhnd_pmureg.h" #include "bhnd_pmuvar.h" #include "bhnd_pmu_private.h" #define PMU_LOG(_sc, _fmt, ...) do { \ if (_sc->dev != NULL) \ device_printf(_sc->dev, _fmt, ##__VA_ARGS__); \ else \ printf(_fmt, ##__VA_ARGS__); \ } while (0) #ifdef BCMDBG #define PMU_DEBUG(_sc, _fmt, ...) PMU_LOG(_sc, _fmt, ##__VA_ARGS__) #else #define PMU_DEBUG(_sc, _fmt, ...) #endif typedef struct pmu0_xtaltab0 pmu0_xtaltab0_t; typedef struct pmu1_xtaltab0 pmu1_xtaltab0_t; /* PLL controls/clocks */ static const pmu1_xtaltab0_t *bhnd_pmu1_xtaltab0(struct bhnd_pmu_query *sc); static const pmu1_xtaltab0_t *bhnd_pmu1_xtaldef0(struct bhnd_pmu_query *sc); static void bhnd_pmu0_pllinit0(struct bhnd_pmu_softc *sc, uint32_t xtal); static uint32_t bhnd_pmu0_cpuclk0(struct bhnd_pmu_query *sc); static uint32_t bhnd_pmu0_alpclk0(struct bhnd_pmu_query *sc); static void bhnd_pmu1_pllinit0(struct bhnd_pmu_softc *sc, uint32_t xtal); static uint32_t bhnd_pmu1_pllfvco0(struct bhnd_pmu_query *sc); static uint32_t bhnd_pmu1_cpuclk0(struct bhnd_pmu_query *sc); static uint32_t bhnd_pmu1_alpclk0(struct bhnd_pmu_query *sc); static uint32_t bhnd_pmu5_clock(struct bhnd_pmu_query *sc, u_int pll0, u_int m); /* PMU resources */ static bool bhnd_pmu_res_depfltr_bb(struct bhnd_pmu_softc *sc); static bool bhnd_pmu_res_depfltr_ncb(struct bhnd_pmu_softc *sc); static bool bhnd_pmu_res_depfltr_paldo(struct bhnd_pmu_softc *sc); static bool bhnd_pmu_res_depfltr_npaldo(struct bhnd_pmu_softc *sc); static uint32_t bhnd_pmu_res_deps(struct bhnd_pmu_softc *sc, uint32_t rsrcs, bool all); static int bhnd_pmu_res_uptime(struct bhnd_pmu_softc *sc, uint8_t rsrc, uint32_t *uptime); static int bhnd_pmu_res_masks(struct bhnd_pmu_softc *sc, uint32_t *pmin, uint32_t *pmax); static void bhnd_pmu_spuravoid_pllupdate(struct bhnd_pmu_softc *sc, uint8_t spuravoid); static void bhnd_pmu_set_4330_plldivs(struct bhnd_pmu_softc *sc); #define BHND_PMU_REV(_sc) \ ((uint8_t)BHND_PMU_GET_BITS((_sc)->caps, BHND_PMU_CAP_REV)) #define PMU_WAIT_CLKST(_sc, _val, _mask) \ bhnd_pmu_wait_clkst((_sc), (_sc)->dev, (_sc)->res, \ BHND_CLK_CTL_ST, (_val), (_mask)) #define PMURES_BIT(_bit) \ (1 << (BHND_PMU_ ## _bit)) #define PMU_CST4330_SDIOD_CHIPMODE(_sc) \ CHIPC_CST4330_CHIPMODE_SDIOD((_sc)->io->rd_chipst((_sc)->io_ctx)) /** * Initialize @p query state. * * @param[out] query On success, will be populated with a valid query instance * state. * @param dev The device owning @p query, or NULL. * @param id The bhnd chip identification. * @param io I/O callback functions. * @param ctx I/O callback context. * * @retval 0 success * @retval non-zero if the query state could not be initialized. */ int bhnd_pmu_query_init(struct bhnd_pmu_query *query, device_t dev, struct bhnd_chipid id, const struct bhnd_pmu_io *io, void *ctx) { query->dev = dev; query->io = io; query->io_ctx = ctx; query->cid = id; query->caps = BHND_PMU_READ_4(query, BHND_PMU_CAP); return (0); } /** * Release any resources held by @p query. * * @param query A query instance previously initialized via * bhnd_pmu_query_init(). */ void bhnd_pmu_query_fini(struct bhnd_pmu_query *query) { /* nothing to do */ } /** * Perform an indirect register read. * * @param addr Offset of the address register. * @param data Offset of the data register. * @param reg Indirect register to be read. */ uint32_t bhnd_pmu_ind_read(const struct bhnd_pmu_io *io, void *io_ctx, bus_size_t addr, bus_size_t data, uint32_t reg) { io->wr4(addr, reg, io_ctx); return (io->rd4(data, io_ctx)); } /** * Perform an indirect register write. * * @param addr Offset of the address register. * @param data Offset of the data register. * @param reg Indirect register to be written. * @param val Value to be written to @p reg. * @param mask Only the bits defined by @p mask will be updated from @p val. */ void bhnd_pmu_ind_write(const struct bhnd_pmu_io *io, void *io_ctx, bus_size_t addr, bus_size_t data, uint32_t reg, uint32_t val, uint32_t mask) { uint32_t rval; io->wr4(addr, reg, io_ctx); if (mask != UINT32_MAX) { rval = io->rd4(data, io_ctx); rval &= ~mask | (val & mask); } else { rval = val; } io->wr4(data, rval, io_ctx); } /** * Wait for up to BHND_PMU_MAX_TRANSITION_DLY microseconds for the per-core * clock status to be equal to @p value after applying @p mask. * * @param sc PMU driver state. * @param dev Requesting device. * @param r An active resource mapping the clock status register. * @param clkst_reg Offset to the CLK_CTL_ST register. * @param value Value to wait for. * @param mask Mask to apply prior to value comparison. */ bool bhnd_pmu_wait_clkst(struct bhnd_pmu_softc *sc, device_t dev, struct bhnd_resource *r, bus_size_t clkst_reg, uint32_t value, uint32_t mask) { uint32_t clkst; /* Bitswapped HTAVAIL/ALPAVAIL work-around */ if (sc->quirks & BPMU_QUIRK_CLKCTL_CCS0) { uint32_t fmask, fval; fmask = mask & ~(BHND_CCS_HTAVAIL | BHND_CCS_ALPAVAIL); fval = value & ~(BHND_CCS_HTAVAIL | BHND_CCS_ALPAVAIL); if (mask & BHND_CCS_HTAVAIL) fmask |= BHND_CCS0_HTAVAIL; if (value & BHND_CCS_HTAVAIL) fval |= BHND_CCS0_HTAVAIL; if (mask & BHND_CCS_ALPAVAIL) fmask |= BHND_CCS0_ALPAVAIL; if (value & BHND_CCS_ALPAVAIL) fval |= BHND_CCS0_ALPAVAIL; mask = fmask; value = fval; } for (uint32_t i = 0; i < BHND_PMU_MAX_TRANSITION_DLY; i += 10) { clkst = bhnd_bus_read_4(r, clkst_reg); if ((clkst & mask) == (value & mask)) return (true); DELAY(10); } device_printf(dev, "clkst wait timeout (value=%#x, " "mask=%#x)\n", value, mask); return (false); } /* Setup switcher voltage */ void bhnd_pmu_set_switcher_voltage(struct bhnd_pmu_softc *sc, uint8_t bb_voltage, uint8_t rf_voltage) { BHND_PMU_REGCTRL_WRITE(sc, 0x01, (bb_voltage & 0x1f) << 22, ~0); BHND_PMU_REGCTRL_WRITE(sc, 0x00, (rf_voltage & 0x1f) << 14, ~0); } void bhnd_pmu_set_ldo_voltage(struct bhnd_pmu_softc *sc, uint8_t ldo, uint8_t voltage) { uint32_t chipst; uint32_t regctrl; uint8_t shift; uint8_t mask; uint8_t addr; switch (sc->cid.chip_id) { case BHND_CHIPID_BCM4328: case BHND_CHIPID_BCM5354: switch (ldo) { case SET_LDO_VOLTAGE_LDO1: addr = 2; shift = 17 + 8; mask = 0xf; break; case SET_LDO_VOLTAGE_LDO2: addr = 3; shift = 1; mask = 0xf; break; case SET_LDO_VOLTAGE_LDO3: addr = 3; shift = 9; mask = 0xf; break; case SET_LDO_VOLTAGE_PAREF: addr = 3; shift = 17; mask = 0x3f; break; default: panic("unknown BCM4328/BCM5354 LDO %hhu\n", ldo); } break; case BHND_CHIPID_BCM4312: switch (ldo) { case SET_LDO_VOLTAGE_PAREF: addr = 0; shift = 21; mask = 0x3f; break; default: panic("unknown BCM4312 LDO %hhu\n", ldo); } break; case BHND_CHIPID_BCM4325: switch (ldo) { case SET_LDO_VOLTAGE_CLDO_PWM: addr = 5; shift = 9; mask = 0xf; break; case SET_LDO_VOLTAGE_CLDO_BURST: addr = 5; shift = 13; mask = 0xf; break; case SET_LDO_VOLTAGE_CBUCK_PWM: addr = 3; shift = 20; mask = 0x1f; /* Bit 116 & 119 are inverted in CLB for opt 2b */ chipst = BHND_CHIPC_READ_CHIPST(sc->chipc_dev); if (BHND_PMU_GET_BITS(chipst, CHIPC_CST4325_PMUTOP_2B)) voltage ^= 0x9; break; case SET_LDO_VOLTAGE_CBUCK_BURST: addr = 3; shift = 25; mask = 0x1f; /* Bit 121 & 124 are inverted in CLB for opt 2b */ chipst = BHND_CHIPC_READ_CHIPST(sc->chipc_dev); if (BHND_PMU_GET_BITS(chipst, CHIPC_CST4325_PMUTOP_2B)) voltage ^= 0x9; break; case SET_LDO_VOLTAGE_LNLDO1: addr = 5; shift = 17; mask = 0x1f; break; case SET_LDO_VOLTAGE_LNLDO2_SEL: addr = 6; shift = 0; mask = 0x1; break; default: panic("unknown BCM4325 LDO %hhu\n", ldo); } break; case BHND_CHIPID_BCM4336: switch (ldo) { case SET_LDO_VOLTAGE_CLDO_PWM: addr = 4; shift = 1; mask = 0xf; break; case SET_LDO_VOLTAGE_CLDO_BURST: addr = 4; shift = 5; mask = 0xf; break; case SET_LDO_VOLTAGE_LNLDO1: addr = 4; shift = 17; mask = 0xf; break; default: panic("unknown BCM4336 LDO %hhu\n", ldo); } break; case BHND_CHIPID_BCM4330: switch (ldo) { case SET_LDO_VOLTAGE_CBUCK_PWM: addr = 3; shift = 0; mask = 0x1f; break; default: panic("unknown BCM4330 LDO %hhu\n", ldo); } break; case BHND_CHIPID_BCM4331: switch (ldo) { case SET_LDO_VOLTAGE_PAREF: addr = 1; shift = 0; mask = 0xf; break; default: panic("unknown BCM4331 LDO %hhu\n", ldo); } break; default: panic("cannot set LDO voltage on unsupported chip %hu\n", sc->cid.chip_id); return; } regctrl = (voltage & mask) << shift; BHND_PMU_REGCTRL_WRITE(sc, addr, regctrl, mask << shift); } /* d11 slow to fast clock transition time in slow clock cycles */ #define D11SCC_SLOW2FAST_TRANSITION 2 int bhnd_pmu_fast_pwrup_delay(struct bhnd_pmu_softc *sc, uint16_t *pwrup_delay) { uint32_t ilp; uint32_t uptime; u_int delay; int error; switch (sc->cid.chip_id) { case BHND_CHIPID_BCM43224: case BHND_CHIPID_BCM43225: case BHND_CHIPID_BCM43421: case BHND_CHIPID_BCM43235: case BHND_CHIPID_BCM43236: case BHND_CHIPID_BCM43238: case BHND_CHIPID_BCM4331: case BHND_CHIPID_BCM6362: case BHND_CHIPID_BCM4313: delay = 3700; break; case BHND_CHIPID_BCM4325: error = bhnd_pmu_res_uptime(sc, BHND_PMU_RES4325_HT_AVAIL, &uptime); if (error) return (error); ilp = bhnd_pmu_ilp_clock(&sc->query); delay = (uptime + D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp - 1) / ilp); delay = (11 * delay) / 10; break; case BHND_CHIPID_BCM4329: error = bhnd_pmu_res_uptime(sc, BHND_PMU_RES4329_HT_AVAIL, &uptime); if (error) return (error); ilp = bhnd_pmu_ilp_clock(&sc->query); delay = (uptime + D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp - 1) / ilp); delay = (11 * delay) / 10; break; case BHND_CHIPID_BCM4319: delay = 3700; break; case BHND_CHIPID_BCM4336: error = bhnd_pmu_res_uptime(sc, BHND_PMU_RES4336_HT_AVAIL, &uptime); if (error) return (error); ilp = bhnd_pmu_ilp_clock(&sc->query); delay = (uptime + D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp - 1) / ilp); delay = (11 * delay) / 10; break; case BHND_CHIPID_BCM4330: error = bhnd_pmu_res_uptime(sc, BHND_PMU_RES4330_HT_AVAIL, &uptime); if (error) return (error); ilp = bhnd_pmu_ilp_clock(&sc->query); delay = (uptime + D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp - 1) / ilp); delay = (11 * delay) / 10; break; default: delay = BHND_PMU_MAX_TRANSITION_DLY; break; } *pwrup_delay = (uint16_t)delay; return (0); } uint32_t bhnd_pmu_force_ilp(struct bhnd_pmu_softc *sc, bool force) { uint32_t orig; uint32_t pctrl; pctrl = BHND_PMU_READ_4(sc, BHND_PMU_CTRL); orig = pctrl; if (force) pctrl &= ~(BHND_PMU_CTRL_HT_REQ_EN | BHND_PMU_CTRL_ALP_REQ_EN); else pctrl |= (BHND_PMU_CTRL_HT_REQ_EN | BHND_PMU_CTRL_ALP_REQ_EN); BHND_PMU_WRITE_4(sc, BHND_PMU_CTRL, pctrl); return (orig); } /* Setup resource up/down timers */ typedef struct { uint8_t resnum; uint16_t updown; } pmu_res_updown_t; typedef bool (*pmu_res_filter) (struct bhnd_pmu_softc *sc); /* Change resource dependencies masks */ typedef struct { uint32_t res_mask; /* resources (chip specific) */ int8_t action; /* action */ uint32_t depend_mask; /* changes to the dependencies mask */ pmu_res_filter filter; /* action is taken when filter is NULL or returns true */ } pmu_res_depend_t; /* Resource dependencies mask change action */ #define RES_DEPEND_SET 0 /* Override the dependencies mask */ #define RES_DEPEND_ADD 1 /* Add to the dependencies mask */ #define RES_DEPEND_REMOVE -1 /* Remove from the dependencies mask */ static const pmu_res_updown_t bcm4328a0_res_updown[] = { { BHND_PMU_RES4328_EXT_SWITCHER_PWM, 0x0101}, { BHND_PMU_RES4328_BB_SWITCHER_PWM, 0x1f01}, { BHND_PMU_RES4328_BB_SWITCHER_BURST, 0x010f}, { BHND_PMU_RES4328_BB_EXT_SWITCHER_BURST, 0x0101}, { BHND_PMU_RES4328_ILP_REQUEST, 0x0202}, { BHND_PMU_RES4328_RADIO_SWITCHER_PWM, 0x0f01}, { BHND_PMU_RES4328_RADIO_SWITCHER_BURST, 0x0f01}, { BHND_PMU_RES4328_ROM_SWITCH, 0x0101}, { BHND_PMU_RES4328_PA_REF_LDO, 0x0f01}, { BHND_PMU_RES4328_RADIO_LDO, 0x0f01}, { BHND_PMU_RES4328_AFE_LDO, 0x0f01}, { BHND_PMU_RES4328_PLL_LDO, 0x0f01}, { BHND_PMU_RES4328_BG_FILTBYP, 0x0101}, { BHND_PMU_RES4328_TX_FILTBYP, 0x0101}, { BHND_PMU_RES4328_RX_FILTBYP, 0x0101}, { BHND_PMU_RES4328_XTAL_PU, 0x0101}, { BHND_PMU_RES4328_XTAL_EN, 0xa001}, { BHND_PMU_RES4328_BB_PLL_FILTBYP, 0x0101}, { BHND_PMU_RES4328_RF_PLL_FILTBYP, 0x0101}, { BHND_PMU_RES4328_BB_PLL_PU, 0x0701} }; static const pmu_res_depend_t bcm4328a0_res_depend[] = { /* Adjust ILP request resource not to force ext/BB switchers into burst mode */ { PMURES_BIT(RES4328_ILP_REQUEST), RES_DEPEND_SET, PMURES_BIT(RES4328_EXT_SWITCHER_PWM) | PMURES_BIT(RES4328_BB_SWITCHER_PWM), NULL} }; static const pmu_res_updown_t bcm4325a0_res_updown[] = { { BHND_PMU_RES4325_XTAL_PU, 0x1501} }; static const pmu_res_depend_t bcm4325a0_res_depend[] = { /* Adjust OTP PU resource dependencies - remove BB BURST */ { PMURES_BIT(RES4325_OTP_PU), RES_DEPEND_REMOVE, PMURES_BIT(RES4325_BUCK_BOOST_BURST), NULL}, /* Adjust ALP/HT Avail resource dependencies - bring up BB along if it is used. */ { PMURES_BIT(RES4325_ALP_AVAIL) | PMURES_BIT(RES4325_HT_AVAIL), RES_DEPEND_ADD, PMURES_BIT(RES4325_BUCK_BOOST_BURST) | PMURES_BIT(RES4325_BUCK_BOOST_PWM), bhnd_pmu_res_depfltr_bb}, /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */ { PMURES_BIT(RES4325_HT_AVAIL), RES_DEPEND_ADD, PMURES_BIT(RES4325_RX_PWRSW_PU) | PMURES_BIT(RES4325_TX_PWRSW_PU) | PMURES_BIT(RES4325_LOGEN_PWRSW_PU) | PMURES_BIT(RES4325_AFE_PWRSW_PU), NULL}, /* Adjust ALL resource dependencies - remove CBUCK dependencies if it is not used. */ { PMURES_BIT(RES4325_ILP_REQUEST) | PMURES_BIT(RES4325_ABUCK_BURST) | PMURES_BIT(RES4325_ABUCK_PWM) | PMURES_BIT(RES4325_LNLDO1_PU) | PMURES_BIT(RES4325C1_LNLDO2_PU) | PMURES_BIT(RES4325_XTAL_PU) | PMURES_BIT(RES4325_ALP_AVAIL) | PMURES_BIT(RES4325_RX_PWRSW_PU) | PMURES_BIT(RES4325_TX_PWRSW_PU) | PMURES_BIT(RES4325_RFPLL_PWRSW_PU) | PMURES_BIT(RES4325_LOGEN_PWRSW_PU) | PMURES_BIT(RES4325_AFE_PWRSW_PU) | PMURES_BIT(RES4325_BBPLL_PWRSW_PU) | PMURES_BIT(RES4325_HT_AVAIL), RES_DEPEND_REMOVE, PMURES_BIT(RES4325B0_CBUCK_LPOM) | PMURES_BIT(RES4325B0_CBUCK_BURST) | PMURES_BIT(RES4325B0_CBUCK_PWM), bhnd_pmu_res_depfltr_ncb} }; static const pmu_res_updown_t bcm4315a0_res_updown[] = { { BHND_PMU_RES4315_XTAL_PU, 0x2501} }; static const pmu_res_depend_t bcm4315a0_res_depend[] = { /* Adjust OTP PU resource dependencies - not need PALDO unless write */ { PMURES_BIT(RES4315_OTP_PU), RES_DEPEND_REMOVE, PMURES_BIT(RES4315_PALDO_PU), bhnd_pmu_res_depfltr_npaldo}, /* Adjust ALP/HT Avail resource dependencies - bring up PALDO along if it is used. */ { PMURES_BIT(RES4315_ALP_AVAIL) | PMURES_BIT(RES4315_HT_AVAIL), RES_DEPEND_ADD, PMURES_BIT(RES4315_PALDO_PU), bhnd_pmu_res_depfltr_paldo}, /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */ { PMURES_BIT(RES4315_HT_AVAIL), RES_DEPEND_ADD, PMURES_BIT(RES4315_RX_PWRSW_PU) | PMURES_BIT(RES4315_TX_PWRSW_PU) | PMURES_BIT(RES4315_LOGEN_PWRSW_PU) | PMURES_BIT(RES4315_AFE_PWRSW_PU), NULL}, /* Adjust ALL resource dependencies - remove CBUCK dependencies if it is not used. */ { PMURES_BIT(RES4315_CLDO_PU) | PMURES_BIT(RES4315_ILP_REQUEST) | PMURES_BIT(RES4315_LNLDO1_PU) | PMURES_BIT(RES4315_OTP_PU) | PMURES_BIT(RES4315_LNLDO2_PU) | PMURES_BIT(RES4315_XTAL_PU) | PMURES_BIT(RES4315_ALP_AVAIL) | PMURES_BIT(RES4315_RX_PWRSW_PU) | PMURES_BIT(RES4315_TX_PWRSW_PU) | PMURES_BIT(RES4315_RFPLL_PWRSW_PU) | PMURES_BIT(RES4315_LOGEN_PWRSW_PU) | PMURES_BIT(RES4315_AFE_PWRSW_PU) | PMURES_BIT(RES4315_BBPLL_PWRSW_PU) | PMURES_BIT(RES4315_HT_AVAIL), RES_DEPEND_REMOVE, PMURES_BIT(RES4315_CBUCK_LPOM) | PMURES_BIT(RES4315_CBUCK_BURST) | PMURES_BIT(RES4315_CBUCK_PWM), bhnd_pmu_res_depfltr_ncb} }; /* 4329 specific. needs to come back this issue later */ static const pmu_res_updown_t bcm4329_res_updown[] = { { BHND_PMU_RES4329_XTAL_PU, 0x1501} }; static const pmu_res_depend_t bcm4329_res_depend[] = { /* Adjust HT Avail resource dependencies */ { PMURES_BIT(RES4329_HT_AVAIL), RES_DEPEND_ADD, PMURES_BIT(RES4329_CBUCK_LPOM) | PMURES_BIT(RES4329_CBUCK_BURST) | PMURES_BIT(RES4329_CBUCK_PWM) | PMURES_BIT(RES4329_CLDO_PU) | PMURES_BIT(RES4329_PALDO_PU) | PMURES_BIT(RES4329_LNLDO1_PU) | PMURES_BIT(RES4329_XTAL_PU) | PMURES_BIT(RES4329_ALP_AVAIL) | PMURES_BIT(RES4329_RX_PWRSW_PU) | PMURES_BIT(RES4329_TX_PWRSW_PU) | PMURES_BIT(RES4329_RFPLL_PWRSW_PU) | PMURES_BIT(RES4329_LOGEN_PWRSW_PU) | PMURES_BIT(RES4329_AFE_PWRSW_PU) | PMURES_BIT(RES4329_BBPLL_PWRSW_PU), NULL} }; static const pmu_res_updown_t bcm4319a0_res_updown[] = { { BHND_PMU_RES4319_XTAL_PU, 0x3f01} }; static const pmu_res_depend_t bcm4319a0_res_depend[] = { /* Adjust OTP PU resource dependencies - not need PALDO unless write */ { PMURES_BIT(RES4319_OTP_PU), RES_DEPEND_REMOVE, PMURES_BIT(RES4319_PALDO_PU), bhnd_pmu_res_depfltr_npaldo}, /* Adjust HT Avail resource dependencies - bring up PALDO along if it is used. */ { PMURES_BIT(RES4319_HT_AVAIL), RES_DEPEND_ADD, PMURES_BIT(RES4319_PALDO_PU), bhnd_pmu_res_depfltr_paldo}, /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */ { PMURES_BIT(RES4319_HT_AVAIL), RES_DEPEND_ADD, PMURES_BIT(RES4319_RX_PWRSW_PU) | PMURES_BIT(RES4319_TX_PWRSW_PU) | PMURES_BIT(RES4319_RFPLL_PWRSW_PU) | PMURES_BIT(RES4319_LOGEN_PWRSW_PU) | PMURES_BIT(RES4319_AFE_PWRSW_PU), NULL} }; static const pmu_res_updown_t bcm4336a0_res_updown[] = { { BHND_PMU_RES4336_HT_AVAIL, 0x0D01} }; static const pmu_res_depend_t bcm4336a0_res_depend[] = { /* Just a dummy entry for now */ { PMURES_BIT(RES4336_RSVD), RES_DEPEND_ADD, 0, NULL} }; static const pmu_res_updown_t bcm4330a0_res_updown[] = { { BHND_PMU_RES4330_HT_AVAIL, 0x0e02} }; static const pmu_res_depend_t bcm4330a0_res_depend[] = { /* Just a dummy entry for now */ { PMURES_BIT(RES4330_HT_AVAIL), RES_DEPEND_ADD, 0, NULL} }; /* true if the power topology uses the buck boost to provide 3.3V to VDDIO_RF * and WLAN PA */ static bool bhnd_pmu_res_depfltr_bb(struct bhnd_pmu_softc *sc) { return (BHND_PMU_GET_FLAG(sc->board.board_flags, BHND_BFL_BUCKBOOST)); } /* true if the power topology doesn't use the cbuck. Key on chiprev also if * the chip is BCM4325. */ static bool bhnd_pmu_res_depfltr_ncb(struct bhnd_pmu_softc *sc) { if (sc->cid.chip_id == BHND_CHIPID_BCM4325 && sc->cid.chip_rev <= 1) return (false); return (BHND_PMU_GET_FLAG(sc->board.board_flags, BHND_BFL_NOCBUCK)); } /* true if the power topology uses the PALDO */ static bool bhnd_pmu_res_depfltr_paldo(struct bhnd_pmu_softc *sc) { return (BHND_PMU_GET_FLAG(sc->board.board_flags, BHND_BFL_PALDO)); } /* true if the power topology doesn't use the PALDO */ static bool bhnd_pmu_res_depfltr_npaldo(struct bhnd_pmu_softc *sc) { return (!BHND_PMU_GET_FLAG(sc->board.board_flags, BHND_BFL_PALDO)); } /* Determine min/max rsrc masks. Value 0 leaves hardware at default. */ static int bhnd_pmu_res_masks(struct bhnd_pmu_softc *sc, uint32_t *pmin, uint32_t *pmax) { uint32_t max_mask, min_mask; uint32_t chipst, otpsel; uint32_t nval; uint8_t rsrcs; int error; max_mask = 0; min_mask = 0; /* # resources */ rsrcs = BHND_PMU_GET_BITS(sc->caps, BHND_PMU_CAP_RC); /* determine min/max rsrc masks */ switch (sc->cid.chip_id) { case BHND_CHIPID_BCM4325: /* If used by this device, enable the CBUCK */ if (!bhnd_pmu_res_depfltr_ncb(sc)) min_mask |= PMURES_BIT(RES4325B0_CBUCK_LPOM); chipst = BHND_CHIPC_READ_CHIPST(sc->chipc_dev); if (BHND_PMU_GET_BITS(chipst, CHIPC_CST4325_PMUTOP_2B)) min_mask |= PMURES_BIT(RES4325B0_CLDO_PU); /* Is OTP required? */ otpsel = BHND_PMU_GET_BITS(chipst, CHIPC_CST4325_SPROM_OTP_SEL); if (otpsel != CHIPC_CST_OTP_PWRDN) min_mask |= PMURES_BIT(RES4325_OTP_PU); /* Leave buck boost on in burst mode for certain boards */ if (sc->board.board_flags & BHND_BFL_BUCKBOOST) { switch (sc->board.board_type) { case BHND_BOARD_BCM94325DEVBU: case BHND_BOARD_BCM94325BGABU: min_mask |= PMURES_BIT( RES4325_BUCK_BOOST_BURST); break; } } /* Allow all resources to be turned on upon requests */ max_mask = ~(~0 << rsrcs); break; case BHND_CHIPID_BCM4312: /* default min_mask = 0x80000cbb is wrong */ min_mask = 0xcbb; /* * max_mask = 0x7fff; * pmu_res_updown_table_sz = 0; * pmu_res_depend_table_sz = 0; */ break; case BHND_CHIPID_BCM4322: case BHND_CHIPID_BCM43221: case BHND_CHIPID_BCM43231: case BHND_CHIPID_BCM4342: if (sc->cid.chip_rev >= 2) break; /* request ALP(can skip for A1) */ min_mask = PMURES_BIT(RES4322_RF_LDO) | PMURES_BIT(RES4322_XTAL_PU) | PMURES_BIT(RES4322_ALP_AVAIL); if (bhnd_get_attach_type(sc->chipc_dev) == BHND_ATTACH_NATIVE) { min_mask |= PMURES_BIT(RES4322_SI_PLL_ON) | PMURES_BIT(RES4322_HT_SI_AVAIL) | PMURES_BIT(RES4322_PHY_PLL_ON) | PMURES_BIT(RES4322_OTP_PU) | PMURES_BIT(RES4322_HT_PHY_AVAIL); max_mask = 0x1ff; } break; case BHND_CHIPID_BCM43222: case BHND_CHIPID_BCM43111: case BHND_CHIPID_BCM43112: case BHND_CHIPID_BCM43224: case BHND_CHIPID_BCM43225: case BHND_CHIPID_BCM43421: case BHND_CHIPID_BCM43226: case BHND_CHIPID_BCM43420: case BHND_CHIPID_BCM43235: case BHND_CHIPID_BCM43236: case BHND_CHIPID_BCM43238: case BHND_CHIPID_BCM43234: case BHND_CHIPID_BCM43237: case BHND_CHIPID_BCM4331: case BHND_CHIPID_BCM43431: case BHND_CHIPID_BCM6362: /* use chip default */ break; case BHND_CHIPID_BCM4328: min_mask = PMURES_BIT(RES4328_BB_SWITCHER_PWM) | PMURES_BIT(RES4328_EXT_SWITCHER_PWM) | PMURES_BIT(RES4328_XTAL_EN); max_mask = 0xfffffff; break; case BHND_CHIPID_BCM5354: /* Allow (but don't require) PLL to turn on */ max_mask = 0xfffffff; break; case BHND_CHIPID_BCM4329: /* Down to save the power. */ if (sc->cid.chip_rev >= 0x2) { min_mask = PMURES_BIT(RES4329_CBUCK_LPOM) | PMURES_BIT(RES4329_LNLDO1_PU) | PMURES_BIT(RES4329_CLDO_PU); } else { min_mask = PMURES_BIT(RES4329_CBUCK_LPOM) | PMURES_BIT(RES4329_CLDO_PU); } /* Is OTP required? */ chipst = BHND_CHIPC_READ_CHIPST(sc->chipc_dev); otpsel = BHND_PMU_GET_BITS(chipst, CHIPC_CST4329_SPROM_OTP_SEL); if (otpsel != CHIPC_CST_OTP_PWRDN) min_mask |= PMURES_BIT(RES4329_OTP_PU); /* Allow (but don't require) PLL to turn on */ max_mask = 0x3ff63e; break; case BHND_CHIPID_BCM4319: /* We only need a few resources to be kept on all the time */ min_mask = PMURES_BIT(RES4319_CBUCK_LPOM) | PMURES_BIT(RES4319_CLDO_PU); /* Allow everything else to be turned on upon requests */ max_mask = ~(~0 << rsrcs); break; case BHND_CHIPID_BCM4336: /* Down to save the power. */ min_mask = PMURES_BIT(RES4336_CBUCK_LPOM) | PMURES_BIT(RES4336_CLDO_PU) | PMURES_BIT(RES4336_LDO3P3_PU) | PMURES_BIT(RES4336_OTP_PU) | PMURES_BIT(RES4336_DIS_INT_RESET_PD); /* Allow (but don't require) PLL to turn on */ max_mask = 0x1ffffff; break; case BHND_CHIPID_BCM4330: /* Down to save the power. */ min_mask = PMURES_BIT(RES4330_CBUCK_LPOM) | PMURES_BIT(RES4330_CLDO_PU) | PMURES_BIT(RES4330_DIS_INT_RESET_PD) | PMURES_BIT(RES4330_LDO3P3_PU) | PMURES_BIT(RES4330_OTP_PU); /* Allow (but don't require) PLL to turn on */ max_mask = 0xfffffff; break; case BHND_CHIPID_BCM4313: min_mask = PMURES_BIT(RES4313_BB_PU_RSRC) | PMURES_BIT(RES4313_XTAL_PU_RSRC) | PMURES_BIT(RES4313_ALP_AVAIL_RSRC) | PMURES_BIT(RES4313_BB_PLL_PWRSW_RSRC); max_mask = 0xffff; break; default: break; } /* Apply nvram override to min mask */ error = bhnd_nvram_getvar_uint32(sc->chipc_dev, BHND_NVAR_RMIN, &nval); if (error && error != ENOENT) { PMU_LOG(sc, "NVRAM error reading %s: %d\n", BHND_NVAR_RMIN, error); return (error); } else if (!error) { PMU_DEBUG(sc, "Applying rmin=%#x to min_mask\n", nval); min_mask = nval; } /* Apply nvram override to max mask */ error = bhnd_nvram_getvar_uint32(sc->chipc_dev, BHND_NVAR_RMAX, &nval); if (error && error != ENOENT) { PMU_LOG(sc, "NVRAM error reading %s: %d\n", BHND_NVAR_RMAX, error); return (error); } else if (!error) { PMU_DEBUG(sc, "Applying rmax=%#x to max_mask\n", nval); min_mask = nval; } if (pmin != NULL) *pmin = min_mask; if (pmax != NULL) *pmax = max_mask; return (0); } /* initialize PMU resources */ int bhnd_pmu_res_init(struct bhnd_pmu_softc *sc) { const pmu_res_updown_t *pmu_res_updown_table; const pmu_res_depend_t *pmu_res_depend_table; size_t pmu_res_updown_table_sz; size_t pmu_res_depend_table_sz; uint32_t max_mask, min_mask; uint8_t rsrcs; int error; pmu_res_depend_table = NULL; pmu_res_depend_table_sz = 0; pmu_res_updown_table = NULL; pmu_res_updown_table_sz = 0; switch (sc->cid.chip_id) { case BHND_CHIPID_BCM4315: /* Optimize resources up/down timers */ pmu_res_updown_table = bcm4315a0_res_updown; pmu_res_updown_table_sz = nitems(bcm4315a0_res_updown); /* Optimize resources dependencies */ pmu_res_depend_table = bcm4315a0_res_depend; pmu_res_depend_table_sz = nitems(bcm4315a0_res_depend); break; case BHND_CHIPID_BCM4325: /* Optimize resources up/down timers */ pmu_res_updown_table = bcm4325a0_res_updown; pmu_res_updown_table_sz = nitems(bcm4325a0_res_updown); /* Optimize resources dependencies */ pmu_res_depend_table = bcm4325a0_res_depend; pmu_res_depend_table_sz = nitems(bcm4325a0_res_depend); break; case BHND_CHIPID_BCM4328: /* Optimize resources up/down timers */ pmu_res_updown_table = bcm4328a0_res_updown; pmu_res_updown_table_sz = nitems(bcm4328a0_res_updown); /* Optimize resources dependencies */ pmu_res_depend_table = bcm4328a0_res_depend; pmu_res_depend_table_sz = nitems(bcm4328a0_res_depend); break; case BHND_CHIPID_BCM4329: /* Optimize resources up/down timers */ pmu_res_updown_table = bcm4329_res_updown; pmu_res_updown_table_sz = nitems(bcm4329_res_updown); /* Optimize resources dependencies */ pmu_res_depend_table = bcm4329_res_depend; pmu_res_depend_table_sz = nitems(bcm4329_res_depend); break; case BHND_CHIPID_BCM4319: /* Optimize resources up/down timers */ pmu_res_updown_table = bcm4319a0_res_updown; pmu_res_updown_table_sz = nitems(bcm4319a0_res_updown); /* Optimize resources dependencies masks */ pmu_res_depend_table = bcm4319a0_res_depend; pmu_res_depend_table_sz = nitems(bcm4319a0_res_depend); break; case BHND_CHIPID_BCM4336: /* Optimize resources up/down timers */ pmu_res_updown_table = bcm4336a0_res_updown; pmu_res_updown_table_sz = nitems(bcm4336a0_res_updown); /* Optimize resources dependencies masks */ pmu_res_depend_table = bcm4336a0_res_depend; pmu_res_depend_table_sz = nitems(bcm4336a0_res_depend); break; case BHND_CHIPID_BCM4330: /* Optimize resources up/down timers */ pmu_res_updown_table = bcm4330a0_res_updown; pmu_res_updown_table_sz = nitems(bcm4330a0_res_updown); /* Optimize resources dependencies masks */ pmu_res_depend_table = bcm4330a0_res_depend; pmu_res_depend_table_sz = nitems(bcm4330a0_res_depend); break; default: break; } /* # resources */ rsrcs = BHND_PMU_GET_BITS(sc->caps, BHND_PMU_CAP_RC); /* Program up/down timers */ for (size_t i = 0; i < pmu_res_updown_table_sz; i++) { const pmu_res_updown_t *updt; KASSERT(pmu_res_updown_table != NULL, ("no updown tables")); updt = &pmu_res_updown_table[pmu_res_updown_table_sz - i - 1]; PMU_DEBUG(sc, "Changing rsrc %d res_updn_timer to %#x\n", updt->resnum, updt->updown); BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, updt->resnum); BHND_PMU_WRITE_4(sc, BHND_PMU_RES_UPDN_TIMER, updt->updown); } /* Apply nvram overrides to up/down timers */ for (uint8_t i = 0; i < rsrcs; i++) { char name[6]; uint32_t val; snprintf(name, sizeof(name), "r%dt", i); error = bhnd_nvram_getvar_uint32(sc->chipc_dev, name, &val); if (error == ENOENT) { continue; } else if (error) { PMU_LOG(sc, "NVRAM error reading %s: %d\n", name, error); return (error); } PMU_DEBUG(sc, "Applying %s=%s to rsrc %d res_updn_timer\n", name, val, i); BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, i); BHND_PMU_WRITE_4(sc, BHND_PMU_RES_UPDN_TIMER, val); } /* Program resource dependencies table */ for (size_t i = 0; i < pmu_res_depend_table_sz; i++) { const pmu_res_depend_t *rdep; pmu_res_filter filter; uint32_t depend_mask; KASSERT(pmu_res_depend_table != NULL, ("no depend tables")); rdep = &pmu_res_depend_table[pmu_res_depend_table_sz - i - 1]; filter = rdep->filter; if (filter != NULL && !filter(sc)) continue; for (uint8_t i = 0; i < rsrcs; i++) { if ((rdep->res_mask & BHND_PMURES_BIT(i)) == 0) continue; BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, i); depend_mask = BHND_PMU_READ_4(sc, BHND_PMU_RES_DEP_MASK); switch (rdep->action) { case RES_DEPEND_SET: PMU_DEBUG(sc, "Changing rsrc %hhu res_dep_mask to " "%#x\n", i, table->depend_mask); depend_mask = rdep->depend_mask; break; case RES_DEPEND_ADD: PMU_DEBUG(sc, "Adding %#x to rsrc %hhu " "res_dep_mask\n", table->depend_mask, i); depend_mask |= rdep->depend_mask; break; case RES_DEPEND_REMOVE: PMU_DEBUG(sc, "Removing %#x from rsrc %hhu " "res_dep_mask\n", table->depend_mask, i); depend_mask &= ~(rdep->depend_mask); break; default: panic("unknown RES_DEPEND action: %d\n", rdep->action); break; } } } /* Apply nvram overrides to dependencies masks */ for (uint8_t i = 0; i < rsrcs; i++) { char name[6]; uint32_t val; snprintf(name, sizeof(name), "r%dd", i); error = bhnd_nvram_getvar_uint32(sc->chipc_dev, name, &val); if (error == ENOENT) { continue; } else if (error) { PMU_LOG(sc, "NVRAM error reading %s: %d\n", name, error); return (error); } PMU_DEBUG(sc, "Applying %s=%s to rsrc %d res_dep_mask\n", name, val, i); BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, i); BHND_PMU_WRITE_4(sc, BHND_PMU_RES_DEP_MASK, val); } /* Determine min/max rsrc masks */ if ((error = bhnd_pmu_res_masks(sc, &min_mask, &max_mask))) return (error); /* It is required to program max_mask first and then min_mask */ /* Program max resource mask */ if (max_mask != 0) { PMU_DEBUG(sc, "Changing max_res_mask to 0x%x\n", max_mask); BHND_PMU_WRITE_4(sc, BHND_PMU_MAX_RES_MASK, max_mask); } /* Program min resource mask */ if (min_mask != 0) { PMU_DEBUG(sc, "Changing min_res_mask to 0x%x\n", min_mask); BHND_PMU_WRITE_4(sc, BHND_PMU_MIN_RES_MASK, min_mask); } /* Add some delay; allow resources to come up and settle. */ DELAY(2000); return (0); } /* setup pll and query clock speed */ struct pmu0_xtaltab0 { uint16_t freq; uint8_t xf; uint8_t wbint; uint32_t wbfrac; }; /* the following table is based on 880Mhz fvco */ static const pmu0_xtaltab0_t pmu0_xtaltab0[] = { { 12000, 1, 73, 349525}, { 13000, 2, 67, 725937}, { 14400, 3, 61, 116508}, { 15360, 4, 57, 305834}, { 16200, 5, 54, 336579}, { 16800, 6, 52, 399457}, { 19200, 7, 45, 873813}, { 19800, 8, 44, 466033}, { 20000, 9, 44, 0}, { 25000, 10, 70, 419430}, { 26000, 11, 67, 725937}, { 30000, 12, 58, 699050}, { 38400, 13, 45, 873813}, { 40000, 14, 45, 0}, { 0, 0, 0, 0} }; #define PMU0_XTAL0_DEFAULT 8 /* setup pll and query clock speed */ struct pmu1_xtaltab0 { uint16_t fref; uint8_t xf; uint8_t p1div; uint8_t p2div; uint8_t ndiv_int; uint32_t ndiv_frac; }; static const pmu1_xtaltab0_t pmu1_xtaltab0_880_4329[] = { { 12000, 1, 3, 22, 0x9, 0xFFFFEF}, { 13000, 2, 1, 6, 0xb, 0x483483}, { 14400, 3, 1, 10, 0xa, 0x1C71C7}, { 15360, 4, 1, 5, 0xb, 0x755555}, { 16200, 5, 1, 10, 0x5, 0x6E9E06}, { 16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, { 19200, 7, 1, 4, 0xb, 0x755555}, { 19800, 8, 1, 11, 0x4, 0xA57EB}, { 20000, 9, 1, 11, 0x4, 0x0}, { 24000, 10, 3, 11, 0xa, 0x0}, { 25000, 11, 5, 16, 0xb, 0x0}, { 26000, 12, 1, 1, 0x21, 0xD89D89}, { 30000, 13, 3, 8, 0xb, 0x0}, { 37400, 14, 3, 1, 0x46, 0x969696}, { 38400, 15, 1, 1, 0x16, 0xEAAAAA}, { 40000, 16, 1, 2, 0xb, 0}, { 0, 0, 0, 0, 0, 0} }; /* the following table is based on 880Mhz fvco */ static const pmu1_xtaltab0_t pmu1_xtaltab0_880[] = { { 12000, 1, 3, 22, 0x9, 0xFFFFEF}, { 13000, 2, 1, 6, 0xb, 0x483483}, { 14400, 3, 1, 10, 0xa, 0x1C71C7}, { 15360, 4, 1, 5, 0xb, 0x755555}, { 16200, 5, 1, 10, 0x5, 0x6E9E06}, { 16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, { 19200, 7, 1, 4, 0xb, 0x755555}, { 19800, 8, 1, 11, 0x4, 0xA57EB}, { 20000, 9, 1, 11, 0x4, 0x0}, { 24000, 10, 3, 11, 0xa, 0x0}, { 25000, 11, 5, 16, 0xb, 0x0}, { 26000, 12, 1, 2, 0x10, 0xEC4EC4}, { 30000, 13, 3, 8, 0xb, 0x0}, { 33600, 14, 1, 2, 0xd, 0x186186}, { 38400, 15, 1, 2, 0xb, 0x755555}, { 40000, 16, 1, 2, 0xb, 0}, { 0, 0, 0, 0, 0, 0} }; #define PMU1_XTALTAB0_880_12000K 0 #define PMU1_XTALTAB0_880_13000K 1 #define PMU1_XTALTAB0_880_14400K 2 #define PMU1_XTALTAB0_880_15360K 3 #define PMU1_XTALTAB0_880_16200K 4 #define PMU1_XTALTAB0_880_16800K 5 #define PMU1_XTALTAB0_880_19200K 6 #define PMU1_XTALTAB0_880_19800K 7 #define PMU1_XTALTAB0_880_20000K 8 #define PMU1_XTALTAB0_880_24000K 9 #define PMU1_XTALTAB0_880_25000K 10 #define PMU1_XTALTAB0_880_26000K 11 #define PMU1_XTALTAB0_880_30000K 12 #define PMU1_XTALTAB0_880_37400K 13 #define PMU1_XTALTAB0_880_38400K 14 #define PMU1_XTALTAB0_880_40000K 15 /* the following table is based on 1760Mhz fvco */ static const pmu1_xtaltab0_t pmu1_xtaltab0_1760[] = { { 12000, 1, 3, 44, 0x9, 0xFFFFEF}, { 13000, 2, 1, 12, 0xb, 0x483483}, { 14400, 3, 1, 20, 0xa, 0x1C71C7}, { 15360, 4, 1, 10, 0xb, 0x755555}, { 16200, 5, 1, 20, 0x5, 0x6E9E06}, { 16800, 6, 1, 20, 0x5, 0x3Cf3Cf}, { 19200, 7, 1, 18, 0x5, 0x17B425}, { 19800, 8, 1, 22, 0x4, 0xA57EB}, { 20000, 9, 1, 22, 0x4, 0x0}, { 24000, 10, 3, 22, 0xa, 0x0}, { 25000, 11, 5, 32, 0xb, 0x0}, { 26000, 12, 1, 4, 0x10, 0xEC4EC4}, { 30000, 13, 3, 16, 0xb, 0x0}, { 38400, 14, 1, 10, 0x4, 0x955555}, { 40000, 15, 1, 4, 0xb, 0}, { 0, 0, 0, 0, 0, 0} }; /* table index */ #define PMU1_XTALTAB0_1760_12000K 0 #define PMU1_XTALTAB0_1760_13000K 1 #define PMU1_XTALTAB0_1760_14400K 2 #define PMU1_XTALTAB0_1760_15360K 3 #define PMU1_XTALTAB0_1760_16200K 4 #define PMU1_XTALTAB0_1760_16800K 5 #define PMU1_XTALTAB0_1760_19200K 6 #define PMU1_XTALTAB0_1760_19800K 7 #define PMU1_XTALTAB0_1760_20000K 8 #define PMU1_XTALTAB0_1760_24000K 9 #define PMU1_XTALTAB0_1760_25000K 10 #define PMU1_XTALTAB0_1760_26000K 11 #define PMU1_XTALTAB0_1760_30000K 12 #define PMU1_XTALTAB0_1760_38400K 13 #define PMU1_XTALTAB0_1760_40000K 14 /* the following table is based on 1440Mhz fvco */ static const pmu1_xtaltab0_t pmu1_xtaltab0_1440[] = { { 12000, 1, 1, 1, 0x78, 0x0}, { 13000, 2, 1, 1, 0x6E, 0xC4EC4E}, { 14400, 3, 1, 1, 0x64, 0x0}, { 15360, 4, 1, 1, 0x5D, 0xC00000}, { 16200, 5, 1, 1, 0x58, 0xE38E38}, { 16800, 6, 1, 1, 0x55, 0xB6DB6D}, { 19200, 7, 1, 1, 0x4B, 0}, { 19800, 8, 1, 1, 0x48, 0xBA2E8B}, { 20000, 9, 1, 1, 0x48, 0x0}, { 25000, 10, 1, 1, 0x39, 0x999999}, { 26000, 11, 1, 1, 0x37, 0x627627}, { 30000, 12, 1, 1, 0x30, 0x0}, { 37400, 13, 2, 1, 0x4D, 0x15E76}, { 38400, 13, 2, 1, 0x4B, 0x0}, { 40000, 14, 2, 1, 0x48, 0x0}, { 48000, 15, 2, 1, 0x3c, 0x0}, { 0, 0, 0, 0, 0, 0} }; /* table index */ #define PMU1_XTALTAB0_1440_12000K 0 #define PMU1_XTALTAB0_1440_13000K 1 #define PMU1_XTALTAB0_1440_14400K 2 #define PMU1_XTALTAB0_1440_15360K 3 #define PMU1_XTALTAB0_1440_16200K 4 #define PMU1_XTALTAB0_1440_16800K 5 #define PMU1_XTALTAB0_1440_19200K 6 #define PMU1_XTALTAB0_1440_19800K 7 #define PMU1_XTALTAB0_1440_20000K 8 #define PMU1_XTALTAB0_1440_25000K 9 #define PMU1_XTALTAB0_1440_26000K 10 #define PMU1_XTALTAB0_1440_30000K 11 #define PMU1_XTALTAB0_1440_37400K 12 #define PMU1_XTALTAB0_1440_38400K 13 #define PMU1_XTALTAB0_1440_40000K 14 #define PMU1_XTALTAB0_1440_48000K 15 #define XTAL_FREQ_24000MHZ 24000 #define XTAL_FREQ_30000MHZ 30000 #define XTAL_FREQ_37400MHZ 37400 #define XTAL_FREQ_48000MHZ 48000 static const pmu1_xtaltab0_t pmu1_xtaltab0_960[] = { { 12000, 1, 1, 1, 0x50, 0x0}, { 13000, 2, 1, 1, 0x49, 0xD89D89}, { 14400, 3, 1, 1, 0x42, 0xAAAAAA}, { 15360, 4, 1, 1, 0x3E, 0x800000}, { 16200, 5, 1, 1, 0x39, 0x425ED0}, { 16800, 6, 1, 1, 0x39, 0x249249}, { 19200, 7, 1, 1, 0x32, 0x0}, { 19800, 8, 1, 1, 0x30, 0x7C1F07}, { 20000, 9, 1, 1, 0x30, 0x0}, { 25000, 10, 1, 1, 0x26, 0x666666}, { 26000, 11, 1, 1, 0x24, 0xEC4EC4}, { 30000, 12, 1, 1, 0x20, 0x0}, { 37400, 13, 2, 1, 0x33, 0x563EF9}, { 38400, 14, 2, 1, 0x32, 0x0}, { 40000, 15, 2, 1, 0x30, 0x0}, { 48000, 16, 2, 1, 0x28, 0x0}, { 0, 0, 0, 0, 0, 0} }; /* table index */ #define PMU1_XTALTAB0_960_12000K 0 #define PMU1_XTALTAB0_960_13000K 1 #define PMU1_XTALTAB0_960_14400K 2 #define PMU1_XTALTAB0_960_15360K 3 #define PMU1_XTALTAB0_960_16200K 4 #define PMU1_XTALTAB0_960_16800K 5 #define PMU1_XTALTAB0_960_19200K 6 #define PMU1_XTALTAB0_960_19800K 7 #define PMU1_XTALTAB0_960_20000K 8 #define PMU1_XTALTAB0_960_25000K 9 #define PMU1_XTALTAB0_960_26000K 10 #define PMU1_XTALTAB0_960_30000K 11 #define PMU1_XTALTAB0_960_37400K 12 #define PMU1_XTALTAB0_960_38400K 13 #define PMU1_XTALTAB0_960_40000K 14 #define PMU1_XTALTAB0_960_48000K 15 /* select xtal table for each chip */ static const pmu1_xtaltab0_t * bhnd_pmu1_xtaltab0(struct bhnd_pmu_query *sc) { switch (sc->cid.chip_id) { case BHND_CHIPID_BCM4315: return (pmu1_xtaltab0_1760); case BHND_CHIPID_BCM4319: return (pmu1_xtaltab0_1440); case BHND_CHIPID_BCM4325: return (pmu1_xtaltab0_880); case BHND_CHIPID_BCM4329: return (pmu1_xtaltab0_880_4329); case BHND_CHIPID_BCM4336: return (pmu1_xtaltab0_960); case BHND_CHIPID_BCM4330: if (PMU_CST4330_SDIOD_CHIPMODE(sc)) return (pmu1_xtaltab0_960); else return (pmu1_xtaltab0_1440); default: PMU_DEBUG(sc, "bhnd_pmu1_xtaltab0: Unknown chipid %#hx\n", sc->cid.chip_id); return (NULL); } } /* select default xtal frequency for each chip */ static const pmu1_xtaltab0_t * bhnd_pmu1_xtaldef0(struct bhnd_pmu_query *sc) { switch (sc->cid.chip_id) { case BHND_CHIPID_BCM4315: /* Default to 26000Khz */ return (&pmu1_xtaltab0_1760[PMU1_XTALTAB0_1760_26000K]); case BHND_CHIPID_BCM4319: /* Default to 30000Khz */ return (&pmu1_xtaltab0_1440[PMU1_XTALTAB0_1440_30000K]); case BHND_CHIPID_BCM4325: /* Default to 26000Khz */ return (&pmu1_xtaltab0_880[PMU1_XTALTAB0_880_26000K]); case BHND_CHIPID_BCM4329: /* Default to 38400Khz */ return (&pmu1_xtaltab0_880_4329[PMU1_XTALTAB0_880_38400K]); case BHND_CHIPID_BCM4336: /* Default to 26000Khz */ return (&pmu1_xtaltab0_960[PMU1_XTALTAB0_960_26000K]); case BHND_CHIPID_BCM4330: /* Default to 37400Khz */ if (PMU_CST4330_SDIOD_CHIPMODE(sc)) return (&pmu1_xtaltab0_960[PMU1_XTALTAB0_960_37400K]); else return (&pmu1_xtaltab0_1440[PMU1_XTALTAB0_1440_37400K]); default: PMU_DEBUG(sc, "bhnd_pmu1_xtaldef0: Unknown chipid %#hx\n", sc->cid.chip_id); return (NULL); } } /* select default pll fvco for each chip */ static uint32_t bhnd_pmu1_pllfvco0(struct bhnd_pmu_query *sc) { switch (sc->cid.chip_id) { case BHND_CHIPID_BCM4329: return (FVCO_880); case BHND_CHIPID_BCM4319: return (FVCO_1440); case BHND_CHIPID_BCM4336: return (FVCO_960); case BHND_CHIPID_BCM4330: if (PMU_CST4330_SDIOD_CHIPMODE(sc)) return (FVCO_960); else return (FVCO_1440); default: PMU_DEBUG(sc, "bhnd_pmu1_pllfvco0: Unknown chipid %#hx\n", sc->cid.chip_id); return (0); } } /* query alp/xtal clock frequency */ static uint32_t bhnd_pmu1_alpclk0(struct bhnd_pmu_query *sc) { const pmu1_xtaltab0_t *xt; uint32_t xf; /* Find the frequency in the table */ xf = BHND_PMU_READ_4(sc, BHND_PMU_CTRL); xf = BHND_PMU_GET_BITS(xf, BHND_PMU_CTRL_XTALFREQ); for (xt = bhnd_pmu1_xtaltab0(sc); xt != NULL && xt->fref != 0; xt++) { if (xt->xf == xf) break; } /* Could not find it so assign a default value */ if (xt == NULL || xt->fref == 0) xt = bhnd_pmu1_xtaldef0(sc); if (xt == NULL || xt->fref == 0) { PMU_LOG(sc, "no matching ALP/XTAL frequency found\n"); return (0); } return (xt->fref * 1000); } /* Set up PLL registers in the PMU as per the crystal speed. */ static void bhnd_pmu0_pllinit0(struct bhnd_pmu_softc *sc, uint32_t xtal) { const pmu0_xtaltab0_t *xt; uint32_t pll_data, pll_mask; uint32_t pll_res; uint32_t pmu_ctrl; uint32_t xf; /* Use h/w default PLL config */ if (xtal == 0) { PMU_DEBUG(sc, "Unspecified xtal frequency, skipping PLL " "configuration\n"); return; } /* Find the frequency in the table */ for (xt = pmu0_xtaltab0; xt->freq; xt ++) { if (xt->freq == xtal) break; } if (xt->freq == 0) xt = &pmu0_xtaltab0[PMU0_XTAL0_DEFAULT]; PMU_DEBUG(sc, "XTAL %d.%d MHz (%d)\n", xtal / 1000, xtal % 1000, xt->xf); /* Check current PLL state */ pmu_ctrl = BHND_PMU_READ_4(sc, BHND_PMU_CTRL); xf = BHND_PMU_GET_BITS(pmu_ctrl, BHND_PMU_CTRL_XTALFREQ); if (xf == xt->xf) { #ifdef BCMUSBDEV if (sc->cid.chip_id == BHND_CHIPID_BCM4328) { bhnd_pmu0_sbclk4328(sc, BHND_PMU0_PLL0_PC0_DIV_ARM_88MHZ); return; } #endif /* BCMUSBDEV */ PMU_DEBUG(sc, "PLL already programmed for %d.%d MHz\n", xt->freq / 1000, xt->freq % 1000); return; } if (xf != 0) { PMU_DEBUG(sc, "Reprogramming PLL for %d.%d MHz (was %d.%dMHz)\n", xt->freq / 1000, xt->freq % 1000, pmu0_xtaltab0[tmp-1].freq / 1000, pmu0_xtaltab0[tmp-1].freq % 1000); } else { PMU_DEBUG(sc, "Programming PLL for %d.%d MHz\n", xt->freq / 1000, xt->freq % 1000); } /* Make sure the PLL is off */ switch (sc->cid.chip_id) { case BHND_CHIPID_BCM4328: pll_res = PMURES_BIT(RES4328_BB_PLL_PU); break; case BHND_CHIPID_BCM5354: pll_res = PMURES_BIT(RES5354_BB_PLL_PU); break; default: panic("unsupported chipid %#hx\n", sc->cid.chip_id); } BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, ~pll_res); BHND_PMU_AND_4(sc, BHND_PMU_MAX_RES_MASK, ~pll_res); /* Wait for HT clock to shutdown. */ PMU_WAIT_CLKST(sc, 0, BHND_CCS_HTAVAIL); PMU_DEBUG(sc, "Done masking\n"); /* Write PDIV in pllcontrol[0] */ if (xt->freq >= BHND_PMU0_PLL0_PC0_PDIV_FREQ) { BHND_PMU_PLL_WRITE(sc, BHND_PMU0_PLL0_PLLCTL0, BHND_PMU0_PLL0_PC0_PDIV_MASK, BHND_PMU0_PLL0_PC0_PDIV_MASK); } else { BHND_PMU_PLL_WRITE(sc, BHND_PMU0_PLL0_PLLCTL0, 0, BHND_PMU0_PLL0_PC0_PDIV_MASK); } /* Write WILD in pllcontrol[1] */ pll_data = BHND_PMU_SET_BITS(xt->wbint, BHND_PMU0_PLL0_PC1_WILD_INT) | BHND_PMU_SET_BITS(xt->wbfrac, BHND_PMU0_PLL0_PC1_WILD_FRAC); if (xt->wbfrac == 0) { pll_data |= BHND_PMU0_PLL0_PC1_STOP_MOD; } else { pll_data &= ~BHND_PMU0_PLL0_PC1_STOP_MOD; } pll_mask = BHND_PMU0_PLL0_PC1_WILD_INT_MASK | BHND_PMU0_PLL0_PC1_WILD_FRAC_MASK; BHND_PMU_PLL_WRITE(sc, BHND_PMU0_PLL0_PLLCTL1, pll_data, pll_mask); /* Write WILD in pllcontrol[2] */ pll_data = BHND_PMU_SET_BITS(xt->wbint, BHND_PMU0_PLL0_PC2_WILD_INT); pll_mask = BHND_PMU0_PLL0_PC2_WILD_INT_MASK; BHND_PMU_PLL_WRITE(sc, BHND_PMU0_PLL0_PLLCTL2, pll_data, pll_mask); PMU_DEBUG(sc, "Done pll\n"); /* Write XtalFreq. Set the divisor also. */ pmu_ctrl = BHND_PMU_READ_4(sc, BHND_PMU_CTRL); pmu_ctrl &= ~(BHND_PMU_CTRL_ILP_DIV_MASK|BHND_PMU_CTRL_XTALFREQ_MASK); pmu_ctrl |= BHND_PMU_SET_BITS(((xt->freq + 127) / 128) - 1, BHND_PMU_CTRL_ILP_DIV); pmu_ctrl |= BHND_PMU_SET_BITS(xt->xf, BHND_PMU_CTRL_XTALFREQ); BHND_PMU_WRITE_4(sc, BHND_PMU_CTRL, pmu_ctrl); } /* query alp/xtal clock frequency */ static uint32_t bhnd_pmu0_alpclk0(struct bhnd_pmu_query *sc) { const pmu0_xtaltab0_t *xt; uint32_t xf; /* Find the frequency in the table */ xf = BHND_PMU_READ_4(sc, BHND_PMU_CTRL); xf = BHND_PMU_GET_BITS(xf, BHND_PMU_CTRL_XTALFREQ); for (xt = pmu0_xtaltab0; xt->freq; xt++) if (xt->xf == xf) break; /* PLL must be configured before */ if (xt == NULL || xt->freq == 0) panic("unsupported frequency: %u", xf); return (xt->freq * 1000); } /* query CPU clock frequency */ static uint32_t bhnd_pmu0_cpuclk0(struct bhnd_pmu_query *sc) { uint32_t tmp, divarm; uint32_t FVCO; #ifdef BCMDBG uint32_t pdiv, wbint, wbfrac, fvco; uint32_t freq; #endif FVCO = FVCO_880; /* Read divarm from pllcontrol[0] */ tmp = BHND_PMU_PLL_READ(sc, BHND_PMU0_PLL0_PLLCTL0); divarm = BHND_PMU_GET_BITS(tmp, BHND_PMU0_PLL0_PC0_DIV_ARM); #ifdef BCMDBG /* Calculate fvco based on xtal freq, pdiv, and wild */ pdiv = tmp & BHND_PMU0_PLL0_PC0_PDIV_MASK; tmp = BHND_PMU_PLL_READ(sc, BHND_PMU0_PLL0_PLLCTL1); wbfrac = BHND_PMU_GET_BITS(tmp, BHND_PMU0_PLL0_PC1_WILD_FRAC); wbint = BHND_PMU_GET_BITS(tmp, PMU0_PLL0_PC1_WILD_INT); tmp = BHND_PMU_PLL_READ(sc, BHND_PMU0_PLL0_PLLCTL2); wbint += BHND_PMU_GET_BITS(tmp, BHND_PMU0_PLL0_PC2_WILD_INT); freq = bhnd_pmu0_alpclk0(sih, osh, cc) / 1000; fvco = (freq * wbint) << 8; fvco += (freq * (wbfrac >> 10)) >> 2; fvco += (freq * (wbfrac & 0x3ff)) >> 10; fvco >>= 8; fvco >>= pdiv; fvco /= 1000; fvco *= 1000; PMU_DEBUG(sc, "bhnd_pmu0_cpuclk0: wbint %u wbfrac %u fvco %u\n", wbint, wbfrac, fvco); FVCO = fvco; #endif /* BCMDBG */ /* Return ARM/SB clock */ return FVCO / (divarm + BHND_PMU0_PLL0_PC0_DIV_ARM_BASE) * 1000; } /* Set up PLL registers in the PMU as per the crystal speed. */ static void bhnd_pmu1_pllinit0(struct bhnd_pmu_softc *sc, uint32_t xtal) { const pmu1_xtaltab0_t *xt; uint32_t buf_strength; uint32_t plladdr, plldata, pllmask; uint32_t pmuctrl; uint32_t FVCO; uint8_t ndiv_mode; FVCO = bhnd_pmu1_pllfvco0(&sc->query) / 1000; buf_strength = 0; ndiv_mode = 1; /* Use h/w default PLL config */ if (xtal == 0) { PMU_DEBUG(sc, "Unspecified xtal frequency, skipping PLL " "configuration\n"); return; } /* Find the frequency in the table */ for (xt = bhnd_pmu1_xtaltab0(&sc->query); xt != NULL && xt->fref != 0; xt++) { if (xt->fref == xtal) break; } /* Check current PLL state, bail out if it has been programmed or * we don't know how to program it. */ if (xt == NULL || xt->fref == 0) { PMU_LOG(sc, "Unsupported XTAL frequency %d.%dMHz, skipping PLL " "configuration\n", xtal / 1000, xtal % 1000); return; } /* For 4319 bootloader already programs the PLL but bootloader does not * program the PLL4 and PLL5. So Skip this check for 4319. */ pmuctrl = BHND_PMU_READ_4(sc, BHND_PMU_CTRL); if (BHND_PMU_GET_BITS(pmuctrl, BHND_PMU_CTRL_XTALFREQ) == xt->xf && sc->cid.chip_id != BHND_CHIPID_BCM4319 && sc->cid.chip_id != BHND_CHIPID_BCM4330) { PMU_DEBUG(sc, "PLL already programmed for %d.%dMHz\n", xt->fref / 1000, xt->fref % 1000); return; } PMU_DEBUG(sc, "XTAL %d.%dMHz (%d)\n", xtal / 1000, xtal % 1000, xt->xf); PMU_DEBUG(sc, "Programming PLL for %d.%dMHz\n", xt->fref / 1000, xt->fref % 1000); switch (sc->cid.chip_id) { case BHND_CHIPID_BCM4325: /* Change the BBPLL drive strength to 2 for all channels */ buf_strength = 0x222222; BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, ~(PMURES_BIT(RES4325_BBPLL_PWRSW_PU) | PMURES_BIT(RES4325_HT_AVAIL))); BHND_PMU_AND_4(sc, BHND_PMU_MAX_RES_MASK, ~(PMURES_BIT(RES4325_BBPLL_PWRSW_PU) | PMURES_BIT(RES4325_HT_AVAIL))); /* Wait for HT clock to shutdown. */ PMU_WAIT_CLKST(sc, 0, BHND_CCS_HTAVAIL); break; case BHND_CHIPID_BCM4329: /* Change the BBPLL drive strength to 8 for all channels */ buf_strength = 0x888888; BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, ~(PMURES_BIT(RES4329_BBPLL_PWRSW_PU) | PMURES_BIT(RES4329_HT_AVAIL))); BHND_PMU_AND_4(sc, BHND_PMU_MAX_RES_MASK, ~(PMURES_BIT(RES4329_BBPLL_PWRSW_PU) | PMURES_BIT(RES4329_HT_AVAIL))); /* Wait for HT clock to shutdown. */ PMU_WAIT_CLKST(sc, 0, BHND_CCS_HTAVAIL); /* Initialize PLL4 */ plladdr = BHND_PMU1_PLL0_PLLCTL4; if (xt->fref == 38400) plldata = 0x200024C0; else if (xt->fref == 37400) plldata = 0x20004500; else if (xt->fref == 26000) plldata = 0x200024C0; else plldata = 0x200005C0; /* Chip Dflt Settings */ BHND_PMU_PLL_WRITE(sc, plladdr, plldata, ~0); /* Initialize PLL5 */ plladdr = BHND_PMU1_PLL0_PLLCTL5; plldata = BHND_PMU_PLL_READ(sc, plladdr); plldata &= BHND_PMU1_PLL0_PC5_CLK_DRV_MASK; if (xt->fref == 38400 || xt->fref == 37400 || xt->fref == 26000) { plldata |= 0x15; } else { plldata |= 0x25; /* Chip Dflt Settings */ } BHND_PMU_PLL_WRITE(sc, plladdr, plldata, ~0); break; case BHND_CHIPID_BCM4319: /* Change the BBPLL drive strength to 2 for all channels */ buf_strength = 0x222222; /* Make sure the PLL is off */ /* WAR65104: Disable the HT_AVAIL resource first and then * after a delay (more than downtime for HT_AVAIL) remove the * BBPLL resource; backplane clock moves to ALP from HT. */ BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, ~(PMURES_BIT(RES4319_HT_AVAIL))); BHND_PMU_AND_4(sc, BHND_PMU_MAX_RES_MASK, ~(PMURES_BIT(RES4319_HT_AVAIL))); DELAY(100); BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU))); BHND_PMU_AND_4(sc, BHND_PMU_MAX_RES_MASK, ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU))); DELAY(100); /* Wait for HT clock to shutdown. */ PMU_WAIT_CLKST(sc, 0, BHND_CCS_HTAVAIL); plldata = 0x200005c0; BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL4, plldata, ~0); break; case BHND_CHIPID_BCM4336: BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, ~(PMURES_BIT(RES4336_HT_AVAIL) | PMURES_BIT(RES4336_MACPHY_CLKAVAIL))); BHND_PMU_AND_4(sc, BHND_PMU_MAX_RES_MASK, ~(PMURES_BIT(RES4336_HT_AVAIL) | PMURES_BIT(RES4336_MACPHY_CLKAVAIL))); DELAY(100); /* Wait for HT clock to shutdown. */ PMU_WAIT_CLKST(sc, 0, BHND_CCS_HTAVAIL); break; case BHND_CHIPID_BCM4330: BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, ~(PMURES_BIT(RES4330_HT_AVAIL) | PMURES_BIT(RES4330_MACPHY_CLKAVAIL))); BHND_PMU_AND_4(sc, BHND_PMU_MAX_RES_MASK, ~(PMURES_BIT(RES4330_HT_AVAIL) | PMURES_BIT(RES4330_MACPHY_CLKAVAIL))); DELAY(100); /* Wait for HT clock to shutdown. */ PMU_WAIT_CLKST(sc, 0, BHND_CCS_HTAVAIL); break; default: panic("unsupported chipid %#hx\n", sc->cid.chip_id); } PMU_DEBUG(sc, "Done masking\n"); /* Write p1div and p2div to pllcontrol[0] */ plldata = BHND_PMU_SET_BITS(xt->p1div, BHND_PMU1_PLL0_PC0_P1DIV) | BHND_PMU_SET_BITS(xt->p2div, BHND_PMU1_PLL0_PC0_P2DIV); pllmask = BHND_PMU1_PLL0_PC0_P1DIV_MASK|BHND_PMU1_PLL0_PC0_P2DIV_MASK; if (sc->cid.chip_id == BHND_CHIPID_BCM4319) { plldata &= ~(BHND_PMU1_PLL0_PC0_BYPASS_SDMOD_MASK); pllmask |= BHND_PMU1_PLL0_PC0_BYPASS_SDMOD_MASK; if (!xt->ndiv_frac) { plldata |= BHND_PMU_SET_BITS(1, BHND_PMU1_PLL0_PC0_BYPASS_SDMOD); } } BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, plldata, pllmask); if (sc->cid.chip_id == BHND_CHIPID_BCM4330) bhnd_pmu_set_4330_plldivs(sc); if (sc->cid.chip_id == BHND_CHIPID_BCM4329 && sc->cid.chip_rev == 0) { BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, BHND_PMU_DOT11MAC_880MHZ_CLK_DIVISOR_VAL, BHND_PMU_DOT11MAC_880MHZ_CLK_DIVISOR_MASK); } /* Write ndiv_int and ndiv_mode to pllcontrol[2] */ if (sc->cid.chip_id == BHND_CHIPID_BCM4336 || sc->cid.chip_id == BHND_CHIPID_BCM4330) { ndiv_mode = BHND_PMU1_PLL0_PC2_NDIV_MODE_MFB; } else if (sc->cid.chip_id == BHND_CHIPID_BCM4319) { if (!(xt->ndiv_frac)) ndiv_mode = BHND_PMU1_PLL0_PC2_NDIV_MODE_INT; else ndiv_mode = BHND_PMU1_PLL0_PC2_NDIV_MODE_MFB; } else { ndiv_mode = BHND_PMU1_PLL0_PC2_NDIV_MODE_MASH; } BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, BHND_PMU_SET_BITS(xt->ndiv_int, BHND_PMU1_PLL0_PC2_NDIV_INT) | BHND_PMU_SET_BITS(ndiv_mode, BHND_PMU1_PLL0_PC2_NDIV_MODE), BHND_PMU1_PLL0_PC2_NDIV_INT_MASK | BHND_PMU1_PLL0_PC2_NDIV_MODE_MASK); /* Write ndiv_frac to pllcontrol[3] */ BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL3, BHND_PMU_SET_BITS(xt->ndiv_frac, BHND_PMU1_PLL0_PC3_NDIV_FRAC), BHND_PMU1_PLL0_PC3_NDIV_FRAC_MASK); /* Writing to pllcontrol[4] */ if (sc->cid.chip_id == BHND_CHIPID_BCM4319) { uint8_t xs; if (!xt->ndiv_frac) plldata = 0x200005c0; else plldata = 0x202C2820; if (FVCO < 1600) xs = 4; else xs = 7; plldata &= ~(BHND_PMU1_PLL0_PC4_KVCO_XS_MASK); plldata |= BHND_PMU_SET_BITS(xs, BHND_PMU1_PLL0_PC4_KVCO_XS); BHND_PMU_WRITE_4(sc, BHND_PMU1_PLL0_PLLCTL4, plldata); } /* Write clock driving strength to pllcontrol[5] */ if (buf_strength) { PMU_DEBUG(sc, "Adjusting PLL buffer drive strength: %x\n", buf_strength); plldata = BHND_PMU_SET_BITS(buf_strength, BHND_PMU1_PLL0_PC5_CLK_DRV); pllmask = BHND_PMU1_PLL0_PC5_CLK_DRV_MASK; if (sc->cid.chip_id == BHND_CHIPID_BCM4319) { pllmask |= BHND_PMU1_PLL0_PC5_VCO_RNG_MASK | BHND_PMU1_PLL0_PC5_PLL_CTRL_37_32_MASK; if (!xt->ndiv_frac) { plldata |= BHND_PMU_SET_BITS(0x25, BHND_PMU1_PLL0_PC5_PLL_CTRL_37_32); } else { plldata |= BHND_PMU_SET_BITS(0x15, BHND_PMU1_PLL0_PC5_PLL_CTRL_37_32); } if (FVCO >= 1600) { plldata |= BHND_PMU_SET_BITS(0x1, BHND_PMU1_PLL0_PC5_VCO_RNG); } } BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL5, plldata, pllmask); } PMU_DEBUG(sc, "Done pll\n"); /* to operate the 4319 usb in 24MHz/48MHz; chipcontrol[2][84:83] needs * to be updated. */ if (sc->cid.chip_id == BHND_CHIPID_BCM4319 && xt->fref != XTAL_FREQ_30000MHZ) { uint32_t pll_sel; switch (xt->fref) { case XTAL_FREQ_24000MHZ: pll_sel = BHND_PMU_CCTL_4319USB_24MHZ_PLL_SEL; break; case XTAL_FREQ_48000MHZ: pll_sel = BHND_PMU_CCTL_4319USB_48MHZ_PLL_SEL; break; default: panic("unsupported 4319USB XTAL frequency: %hu\n", xt->fref); } BHND_PMU_CCTRL_WRITE(sc, BHND_PMU1_PLL0_CHIPCTL2, BHND_PMU_SET_BITS(pll_sel, BHND_PMU_CCTL_4319USB_XTAL_SEL), BHND_PMU_CCTL_4319USB_XTAL_SEL_MASK); } /* Flush deferred pll control registers writes */ if (BHND_PMU_REV(sc) >= 2) BHND_PMU_OR_4(sc, BHND_PMU_CTRL, BHND_PMU_CTRL_PLL_PLLCTL_UPD); /* Write XtalFreq. Set the divisor also. */ pmuctrl = BHND_PMU_READ_4(sc, BHND_PMU_CTRL); pmuctrl = ~(BHND_PMU_CTRL_ILP_DIV_MASK | BHND_PMU_CTRL_XTALFREQ_MASK); pmuctrl |= BHND_PMU_SET_BITS(((xt->fref + 127) / 128) - 1, BHND_PMU_CTRL_ILP_DIV); pmuctrl |= BHND_PMU_SET_BITS(xt->xf, BHND_PMU_CTRL_XTALFREQ); if (sc->cid.chip_id == BHND_CHIPID_BCM4329 && sc->cid.chip_rev == 0) { /* clear the htstretch before clearing HTReqEn */ BHND_PMU_AND_4(sc, BHND_PMU_CLKSTRETCH, ~BHND_PMU_CLKSTRETCH); pmuctrl &= ~BHND_PMU_CTRL_HT_REQ_EN; } BHND_PMU_WRITE_4(sc, BHND_PMU_CTRL, pmuctrl); } /* query the CPU clock frequency */ static uint32_t bhnd_pmu1_cpuclk0(struct bhnd_pmu_query *sc) { uint32_t tmp, m1div; #ifdef BCMDBG uint32_t ndiv_int, ndiv_frac, p2div, p1div, fvco; uint32_t fref; #endif uint32_t FVCO = bhnd_pmu1_pllfvco0(sc); /* Read m1div from pllcontrol[1] */ tmp = BHND_PMU_PLL_READ(sc, BHND_PMU1_PLL0_PLLCTL1); m1div = BHND_PMU_GET_BITS(tmp, BHND_PMU1_PLL0_PC1_M1DIV); #ifdef BCMDBG /* Read p2div/p1div from pllcontrol[0] */ tmp = BHND_PMU_PLL_READ(sc, BHND_PMU1_PLL0_PLLCTL0); p2div = BHND_PMU_GET_BITS(tmp, BHND_PMU1_PLL0_PC0_P2DIV); p1div = BHND_PMU_GET_BITS(tmp, BHND_PMU1_PLL0_PC0_P1DIV); /* Calculate fvco based on xtal freq and ndiv and pdiv */ tmp = BHND_PMU_PLL_READ(sc, BHND_PMU1_PLL0_PLLCTL2); ndiv_int = BHND_PMU_GET_BITS(tmp, BHND_PMU1_PLL0_PC2_NDIV_INT); tmp = BHND_PMU_PLL_READ(sc, BHND_PMU1_PLL0_PLLCTL3); ndiv_frac = BHND_PMU_GET_BITS(tmp, BHND_PMU1_PLL0_PC3_NDIV_FRAC); fref = bhnd_pmu1_alpclk0(sc) / 1000; fvco = (fref * ndiv_int) << 8; fvco += (fref * (ndiv_frac >> 12)) >> 4; fvco += (fref * (ndiv_frac & 0xfff)) >> 12; fvco >>= 8; fvco *= p2div; fvco /= p1div; fvco /= 1000; fvco *= 1000; PMU_DEBUG(sc, "bhnd_pmu1_cpuclk0: ndiv_int %u ndiv_frac %u p2div %u " "p1div %u fvco %u\n", ndiv_int, ndiv_frac, p2div, p1div, fvco); FVCO = fvco; #endif /* BCMDBG */ /* Return ARM/SB clock */ return (FVCO / m1div * 1000); } /* initialize PLL */ void bhnd_pmu_pll_init(struct bhnd_pmu_softc *sc, u_int xtalfreq) { uint32_t max_mask, min_mask; uint32_t res_ht, res_pll; switch (sc->cid.chip_id) { case BHND_CHIPID_BCM4312: /* assume default works */ break; case BHND_CHIPID_BCM4322: case BHND_CHIPID_BCM43221: case BHND_CHIPID_BCM43231: case BHND_CHIPID_BCM4342: if (sc->cid.chip_rev != 0) break; min_mask = BHND_PMU_READ_4(sc, BHND_PMU_MIN_RES_MASK); max_mask = BHND_PMU_READ_4(sc, BHND_PMU_MIN_RES_MASK); res_ht = PMURES_BIT(RES4322_HT_SI_AVAIL); res_pll = PMURES_BIT(RES4322_SI_PLL_ON); /* Have to remove HT Avail request before powering off PLL */ BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, ~res_ht); BHND_PMU_AND_4(sc, BHND_PMU_MAX_RES_MASK, ~res_ht); PMU_WAIT_CLKST(sc, 0, BHND_CCS_HTAVAIL); /* Make sure the PLL is off */ BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, ~res_pll); BHND_PMU_AND_4(sc, BHND_PMU_MAX_RES_MASK, ~res_pll); PMU_WAIT_CLKST(sc, 0, BHND_CCS_HTAVAIL); DELAY(1000); BHND_PMU_PLL_WRITE(sc, BHND_PMU2_SI_PLL_PLLCTL, 0x380005c0, ~0); DELAY(100); BHND_PMU_WRITE_4(sc, BHND_PMU_MAX_RES_MASK, max_mask); DELAY(100); BHND_PMU_WRITE_4(sc, BHND_PMU_MIN_RES_MASK, min_mask); DELAY(100); break; case BHND_CHIPID_BCM4325: bhnd_pmu1_pllinit0(sc, xtalfreq); break; case BHND_CHIPID_BCM4328: bhnd_pmu0_pllinit0(sc, xtalfreq); break; case BHND_CHIPID_BCM5354: if (xtalfreq == 0) xtalfreq = 25000; bhnd_pmu0_pllinit0(sc, xtalfreq); break; case BHND_CHIPID_BCM4329: if (xtalfreq == 0) xtalfreq = 38400; bhnd_pmu1_pllinit0(sc, xtalfreq); break; case BHND_CHIPID_BCM4313: case BHND_CHIPID_BCM43222: case BHND_CHIPID_BCM43111: case BHND_CHIPID_BCM43112: case BHND_CHIPID_BCM43224: case BHND_CHIPID_BCM43225: case BHND_CHIPID_BCM43420: case BHND_CHIPID_BCM43421: case BHND_CHIPID_BCM43226: case BHND_CHIPID_BCM43235: case BHND_CHIPID_BCM43236: case BHND_CHIPID_BCM43238: case BHND_CHIPID_BCM43234: case BHND_CHIPID_BCM43237: case BHND_CHIPID_BCM4331: case BHND_CHIPID_BCM43431: case BHND_CHIPID_BCM43131: case BHND_CHIPID_BCM43227: case BHND_CHIPID_BCM43228: case BHND_CHIPID_BCM43428: case BHND_CHIPID_BCM6362: /* assume default works */ break; case BHND_CHIPID_BCM4315: case BHND_CHIPID_BCM4319: case BHND_CHIPID_BCM4336: case BHND_CHIPID_BCM4330: bhnd_pmu1_pllinit0(sc, xtalfreq); break; default: PMU_DEBUG("No PLL init done for chip %#hx rev %d pmurev %d\n", sc->cid.chip_id, sc->cid.chip_rev, BHND_PMU_REV(sc)); break; } } /** * Return the ALP/XTAL clock frequency, in Hz. * * @param sc PMU query instance. */ uint32_t bhnd_pmu_alp_clock(struct bhnd_pmu_query *sc) { uint32_t clock; clock = BHND_PMU_ALP_CLOCK; switch (sc->cid.chip_id) { case BHND_CHIPID_BCM4328: case BHND_CHIPID_BCM5354: clock = bhnd_pmu0_alpclk0(sc); break; case BHND_CHIPID_BCM4315: case BHND_CHIPID_BCM4319: case BHND_CHIPID_BCM4325: case BHND_CHIPID_BCM4329: case BHND_CHIPID_BCM4330: case BHND_CHIPID_BCM4336: clock = bhnd_pmu1_alpclk0(sc); break; case BHND_CHIPID_BCM4312: case BHND_CHIPID_BCM4322: case BHND_CHIPID_BCM43221: case BHND_CHIPID_BCM43231: case BHND_CHIPID_BCM43222: case BHND_CHIPID_BCM43111: case BHND_CHIPID_BCM43112: case BHND_CHIPID_BCM43224: case BHND_CHIPID_BCM43225: case BHND_CHIPID_BCM43420: case BHND_CHIPID_BCM43421: case BHND_CHIPID_BCM43226: case BHND_CHIPID_BCM43235: case BHND_CHIPID_BCM43236: case BHND_CHIPID_BCM43238: case BHND_CHIPID_BCM43234: case BHND_CHIPID_BCM43237: case BHND_CHIPID_BCM4331: case BHND_CHIPID_BCM43431: case BHND_CHIPID_BCM43131: case BHND_CHIPID_BCM43227: case BHND_CHIPID_BCM43228: case BHND_CHIPID_BCM43428: case BHND_CHIPID_BCM6362: case BHND_CHIPID_BCM4342: case BHND_CHIPID_BCM4716: case BHND_CHIPID_BCM4748: case BHND_CHIPID_BCM47162: case BHND_CHIPID_BCM4313: case BHND_CHIPID_BCM5357: case BHND_CHIPID_BCM4749: case BHND_CHIPID_BCM53572: /* always 20Mhz */ clock = 20000 * 1000; break; case BHND_CHIPID_BCM5356: case BHND_CHIPID_BCM4706: /* always 25Mhz */ clock = 25000 * 1000; break; default: PMU_DEBUG("No ALP clock specified " "for chip %s rev %d pmurev %d, using default %d Hz\n", bcm_chipname(sih->chip, chn, 8), sih->chiprev, sih->pmurev, clock); break; } return (clock); } /* Find the output of the "m" pll divider given pll controls that start with * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc. */ static uint32_t bhnd_pmu5_clock(struct bhnd_pmu_query *sc, u_int pll0, u_int m) { uint32_t div; uint32_t fc; uint32_t ndiv; uint32_t p1, p2; uint32_t tmp; if ((pll0 & 3) || (pll0 > BHND_PMU4716_MAINPLL_PLL0)) { PMU_LOG(sc, "%s: Bad pll0: %d", __func__, pll0); return (0); } /* Strictly there is an m5 divider, but I'm not sure we use it */ if ((m == 0) || (m > 4)) { PMU_LOG(sc, "%s: Bad m divider: %d", __func__, m); return (0); } if (sc->cid.chip_id == BHND_CHIPID_BCM5357 || sc->cid.chip_id == BHND_CHIPID_BCM4749) { /* Detect failure in clock setting */ tmp = sc->io->rd_chipst(sc->io_ctx); if ((tmp & 0x40000) != 0) return (133 * 1000000); } /* Fetch p1 and p2 */ BHND_PMU_WRITE_4(sc, BHND_PMU_PLL_CONTROL_ADDR, pll0 + BHND_PMU5_PLL_P1P2_OFF); BHND_PMU_READ_4(sc, BHND_PMU_PLL_CONTROL_ADDR); tmp = BHND_PMU_READ_4(sc, BHND_PMU_PLL_CONTROL_DATA); p1 = BHND_PMU_GET_BITS(tmp, BHND_PMU5_PLL_P1); p2 = BHND_PMU_GET_BITS(tmp, BHND_PMU5_PLL_P2); /* Fetch div */ BHND_PMU_WRITE_4(sc, BHND_PMU_PLL_CONTROL_ADDR, pll0 + BHND_PMU5_PLL_M14_OFF); BHND_PMU_READ_4(sc, BHND_PMU_PLL_CONTROL_ADDR); tmp = BHND_PMU_READ_4(sc, BHND_PMU_PLL_CONTROL_DATA); div = (tmp >> ((m - 1) * BHND_PMU5_PLL_MDIV_WIDTH)); div &= BHND_PMU5_PLL_MDIV_MASK; /* Fetch ndiv */ BHND_PMU_WRITE_4(sc, BHND_PMU_PLL_CONTROL_ADDR, pll0 + BHND_PMU5_PLL_NM5_OFF); BHND_PMU_READ_4(sc, BHND_PMU_PLL_CONTROL_ADDR); tmp = BHND_PMU_READ_4(sc, BHND_PMU_PLL_CONTROL_DATA); ndiv = BHND_PMU_GET_BITS(tmp, BHND_PMU5_PLL_NDIV); /* Do calculation in Mhz */ fc = bhnd_pmu_alp_clock(sc) / 1000000; fc = (p1 * ndiv * fc) / p2; PMU_DEBUG(sc, "%s: p1=%d, p2=%d, ndiv=%d(0x%x), m%d=%d; fc=%d, " "clock=%d\n", __func__, p1, p2, ndiv, ndiv, m, div, fc, fc / div); /* Return clock in Hertz */ return ((fc / div) * 1000000); } /** * Return the backplane clock frequency, in Hz. * * On designs that feed the same clock to both backplane * and CPU, this returns the CPU clock speed. * * @param sc PMU query instance. */ uint32_t bhnd_pmu_si_clock(struct bhnd_pmu_query *sc) { uint32_t chipst; uint32_t clock; clock = BHND_PMU_HT_CLOCK; switch (sc->cid.chip_id) { case BHND_CHIPID_BCM4322: case BHND_CHIPID_BCM43221: case BHND_CHIPID_BCM43231: case BHND_CHIPID_BCM43222: case BHND_CHIPID_BCM43111: case BHND_CHIPID_BCM43112: case BHND_CHIPID_BCM43224: case BHND_CHIPID_BCM43420: case BHND_CHIPID_BCM43225: case BHND_CHIPID_BCM43421: case BHND_CHIPID_BCM43226: case BHND_CHIPID_BCM4331: case BHND_CHIPID_BCM43431: case BHND_CHIPID_BCM6362: case BHND_CHIPID_BCM4342: /* 96MHz backplane clock */ clock = 96000 * 1000; break; case BHND_CHIPID_BCM4716: case BHND_CHIPID_BCM4748: case BHND_CHIPID_BCM47162: clock = bhnd_pmu5_clock(sc, BHND_PMU4716_MAINPLL_PLL0, BHND_PMU5_MAINPLL_SI); break; case BHND_CHIPID_BCM4325: clock = bhnd_pmu1_cpuclk0(sc); break; case BHND_CHIPID_BCM4328: clock = bhnd_pmu0_cpuclk0(sc); break; case BHND_CHIPID_BCM4329: if (sc->cid.chip_rev == 0) clock = 38400 * 1000; else clock = bhnd_pmu1_cpuclk0(sc); break; case BHND_CHIPID_BCM4315: case BHND_CHIPID_BCM4319: case BHND_CHIPID_BCM4336: case BHND_CHIPID_BCM4330: clock = bhnd_pmu1_cpuclk0(sc); break; case BHND_CHIPID_BCM4313: /* 80MHz backplane clock */ clock = 80000 * 1000; break; case BHND_CHIPID_BCM43234: case BHND_CHIPID_BCM43235: case BHND_CHIPID_BCM43236: case BHND_CHIPID_BCM43238: chipst = sc->io->rd_chipst(sc->io_ctx); if (chipst & CHIPC_CST43236_BP_CLK) clock = 120000 * 1000; else clock = 96000 * 1000; break; case BHND_CHIPID_BCM43237: chipst = sc->io->rd_chipst(sc->io_ctx); if (chipst & CHIPC_CST43237_BP_CLK) clock = 96000 * 1000; else clock = 80000 * 1000; break; case BHND_CHIPID_BCM5356: clock = bhnd_pmu5_clock(sc, BHND_PMU5356_MAINPLL_PLL0, BHND_PMU5_MAINPLL_SI); break; case BHND_CHIPID_BCM5357: case BHND_CHIPID_BCM4749: clock = bhnd_pmu5_clock(sc, BHND_PMU5357_MAINPLL_PLL0, BHND_PMU5_MAINPLL_SI); break; case BHND_CHIPID_BCM53572: clock = 75000000; break; default: PMU_LOG(sc, "No backplane clock specified for chip %#hx rev " "%hhd pmurev %hhd, using default %dHz\n", sc->cid.chip_id, sc->cid.chip_rev, BHND_PMU_REV(sc), clock); break; } return (clock); } /** * Return the CPU clock frequency, in Hz. * * @param sc PMU query instance. */ uint32_t bhnd_pmu_cpu_clock(struct bhnd_pmu_query *sc) { uint32_t clock; /* 5354 chip uses a non programmable PLL of frequency 240MHz */ if (sc->cid.chip_id == BHND_CHIPID_BCM5354) return (240 * 1000 * 1000); /* 240MHz */ if (sc->cid.chip_id == BHND_CHIPID_BCM53572) return (300000000); if (BHND_PMU_REV(sc) >= 5 && sc->cid.chip_id != BHND_CHIPID_BCM4329 && sc->cid.chip_id != BHND_CHIPID_BCM4319 && sc->cid.chip_id != BHND_CHIPID_BCM43234 && sc->cid.chip_id != BHND_CHIPID_BCM43235 && sc->cid.chip_id != BHND_CHIPID_BCM43236 && sc->cid.chip_id != BHND_CHIPID_BCM43237 && sc->cid.chip_id != BHND_CHIPID_BCM43238 && sc->cid.chip_id != BHND_CHIPID_BCM4336 && sc->cid.chip_id != BHND_CHIPID_BCM4330) { u_int pll; switch (sc->cid.chip_id) { case BHND_CHIPID_BCM5356: pll = BHND_PMU5356_MAINPLL_PLL0; break; case BHND_CHIPID_BCM5357: case BHND_CHIPID_BCM4749: pll = BHND_PMU5357_MAINPLL_PLL0; break; default: pll = BHND_PMU4716_MAINPLL_PLL0; break; } clock = bhnd_pmu5_clock(sc, pll, BHND_PMU5_MAINPLL_CPU); } else { clock = bhnd_pmu_si_clock(sc); } return (clock); } /** * Return the memory clock frequency, in Hz. * * @param sc PMU query instance. */ uint32_t bhnd_pmu_mem_clock(struct bhnd_pmu_query *sc) { uint32_t clock; if (BHND_PMU_REV(sc) >= 5 && sc->cid.chip_id != BHND_CHIPID_BCM4329 && sc->cid.chip_id != BHND_CHIPID_BCM4319 && sc->cid.chip_id != BHND_CHIPID_BCM43234 && sc->cid.chip_id != BHND_CHIPID_BCM43235 && sc->cid.chip_id != BHND_CHIPID_BCM43236 && sc->cid.chip_id != BHND_CHIPID_BCM43237 && sc->cid.chip_id != BHND_CHIPID_BCM43238 && sc->cid.chip_id != BHND_CHIPID_BCM4336 && sc->cid.chip_id != BHND_CHIPID_BCM4330) { u_int pll; switch (sc->cid.chip_id) { case BHND_CHIPID_BCM5356: pll = BHND_PMU5356_MAINPLL_PLL0; break; case BHND_CHIPID_BCM5357: case BHND_CHIPID_BCM4749: pll = BHND_PMU5357_MAINPLL_PLL0; break; default: pll = BHND_PMU4716_MAINPLL_PLL0; break; } clock = bhnd_pmu5_clock(sc, pll, BHND_PMU5_MAINPLL_MEM); } else { clock = bhnd_pmu_si_clock(sc); } return (clock); } /* Measure ILP clock frequency */ #define ILP_CALC_DUR 10 /* ms, make sure 1000 can be divided by it. */ /** * Measure and return the ILP clock frequency, in Hz. * * @param sc PMU query instance. */ uint32_t bhnd_pmu_ilp_clock(struct bhnd_pmu_query *sc) { uint32_t start, end, delta; if (sc->ilp_cps == 0) { start = BHND_PMU_READ_4(sc, BHND_PMU_TIMER); DELAY(ILP_CALC_DUR); end = BHND_PMU_READ_4(sc, BHND_PMU_TIMER); delta = end - start; sc->ilp_cps = delta * (1000 / ILP_CALC_DUR); } return (sc->ilp_cps); } /* SDIO Pad drive strength to select value mappings */ typedef struct { uint8_t strength; /* Pad Drive Strength in mA */ uint8_t sel; /* Chip-specific select value */ } sdiod_drive_str_t; /* SDIO Drive Strength to sel value table for PMU Rev 1 */ static const sdiod_drive_str_t sdiod_drive_strength_tab1[] = { { 4, 0x2}, { 2, 0x3}, { 1, 0x0}, { 0, 0x0} }; /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */ static const sdiod_drive_str_t sdiod_drive_strength_tab2[] = { { 12, 0x7}, { 10, 0x6}, { 8, 0x5}, { 6, 0x4}, { 4, 0x2}, { 2, 0x1}, { 0, 0x0} }; /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */ static const sdiod_drive_str_t sdiod_drive_strength_tab3[] = { { 32, 0x7}, { 26, 0x6}, { 22, 0x5}, { 16, 0x4}, { 12, 0x3}, { 8, 0x2}, { 4, 0x1}, { 0, 0x0} }; #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu)) void bhnd_pmu_sdiod_drive_strength_init(struct bhnd_pmu_softc *sc, uint32_t drivestrength) { const sdiod_drive_str_t *str_tab; uint32_t str_mask; uint32_t str_shift; u_int intr_val; str_tab = NULL; str_mask = 0; str_shift = 0; intr_val = 0; switch (SDIOD_DRVSTR_KEY(sc->cid.chip_id, BHND_PMU_REV(sc))) { case SDIOD_DRVSTR_KEY(BHND_CHIPID_BCM4325, 1): str_tab = sdiod_drive_strength_tab1; str_mask = 0x30000000; str_shift = 28; break; case SDIOD_DRVSTR_KEY(BHND_CHIPID_BCM4325, 2): case SDIOD_DRVSTR_KEY(BHND_CHIPID_BCM4325, 3): case SDIOD_DRVSTR_KEY(BHND_CHIPID_BCM4315, 4): case SDIOD_DRVSTR_KEY(BHND_CHIPID_BCM4319, 7): str_tab = sdiod_drive_strength_tab2; str_mask = 0x00003800; str_shift = 11; break; case SDIOD_DRVSTR_KEY(BHND_CHIPID_BCM4336, 8): str_tab = sdiod_drive_strength_tab3; str_mask = 0x00003800; str_shift = 11; break; default: PMU_LOG(sc, "No SDIO Drive strength init done for chip %#x " "rev %hhd pmurev %hhd\n", sc->cid.chip_id, sc->cid.chip_rev, BHND_PMU_REV(sc)); break; } if (str_tab != NULL) { uint32_t drivestrength_sel = 0; uint32_t cc_data_temp; for (u_int i = 0; str_tab[i].strength != 0; i++) { if (drivestrength >= str_tab[i].strength) { drivestrength_sel = str_tab[i].sel; break; } } cc_data_temp = BHND_PMU_CCTRL_READ(sc, 1); cc_data_temp &= ~str_mask; drivestrength_sel <<= str_shift; cc_data_temp |= drivestrength_sel; BHND_PMU_CCTRL_WRITE(sc, 1, cc_data_temp, ~0); PMU_DEBUG(sc, "SDIO: %dmA drive strength selected, set to " "0x%08x\n", drivestrength, cc_data_temp); } } /** * Initialize the PMU. */ int bhnd_pmu_init(struct bhnd_pmu_softc *sc) { uint32_t xtalfreq; int error; if (BHND_PMU_REV(sc) == 1) { BHND_PMU_AND_4(sc, BHND_PMU_CTRL, ~BHND_PMU_CTRL_NOILP_ON_WAIT); } else if (BHND_PMU_REV(sc) >= 2) { BHND_PMU_OR_4(sc, BHND_PMU_CTRL, BHND_PMU_CTRL_NOILP_ON_WAIT); } if (sc->cid.chip_id == BHND_CHIPID_BCM4329 && sc->cid.chip_rev == 2) { /* Fix for 4329b0 bad LPOM state. */ BHND_PMU_REGCTRL_WRITE(sc, 2, 0x100, ~0); BHND_PMU_REGCTRL_WRITE(sc, 3, 0x4, ~0); } if (sc->cid.chip_id == BHND_CHIPID_BCM4319) { /* Limiting the PALDO spike during init time */ BHND_PMU_REGCTRL_WRITE(sc, 2, 0x00000005, 0x00000007); } /* Fetch target xtalfreq, in KHz */ error = bhnd_nvram_getvar_uint32(sc->chipc_dev, BHND_NVAR_XTALFREQ, &xtalfreq); /* If not available, log any real errors, and then try to measure it */ if (error) { if (error != ENOENT) PMU_LOG(sc, "error fetching xtalfreq: %d\n", error); xtalfreq = bhnd_pmu_measure_alpclk(sc); } /* Perform PLL initialization */ bhnd_pmu_pll_init(sc, xtalfreq); if ((error = bhnd_pmu_res_init(sc))) return (error); bhnd_pmu_swreg_init(sc); return (0); } /* Return up time in ILP cycles for the given resource. */ static int bhnd_pmu_res_uptime(struct bhnd_pmu_softc *sc, uint8_t rsrc, uint32_t *uptime) { uint32_t deps; uint32_t up, dup, dmax; uint32_t min_mask; int error; /* uptime of resource 'rsrc' */ BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, rsrc); up = BHND_PMU_READ_4(sc, BHND_PMU_RES_UPDN_TIMER); up = BHND_PMU_GET_BITS(up, BHND_PMU_RES_UPDN_UPTME); /* Find direct dependencies of resource 'rsrc' */ deps = bhnd_pmu_res_deps(sc, BHND_PMURES_BIT(rsrc), false); for (uint8_t i = 0; i <= BHND_PMU_RESNUM_MAX; i++) { if (!(deps & BHND_PMURES_BIT(i))) continue; deps &= ~bhnd_pmu_res_deps(sc, BHND_PMURES_BIT(i), true); } /* Exclude the minimum resource set */ if ((error = bhnd_pmu_res_masks(sc, &min_mask, NULL))) return (error); deps &= ~min_mask; /* max uptime of direct dependencies */ dmax = 0; for (uint8_t i = 0; i <= BHND_PMU_RESNUM_MAX; i++) { if (!(deps & BHND_PMURES_BIT(i))) continue; if ((error = bhnd_pmu_res_uptime(sc, i, &dup))) return (error); if (dmax < dup) dmax = dup; } PMU_DEBUG(sc, "bhnd_pmu_res_uptime: rsrc %hhu uptime %u(deps 0x%08x " "uptime %u)\n", rsrc, up, deps, dmax); *uptime = (up + dmax + BHND_PMURES_UP_TRANSITION); return (0); } /* Return dependencies (direct or all/indirect) for the given resources */ static uint32_t bhnd_pmu_res_deps(struct bhnd_pmu_softc *sc, uint32_t rsrcs, bool all) { uint32_t deps; deps = 0; for (uint8_t i = 0; i <= BHND_PMU_RESNUM_MAX; i++) { if (!(rsrcs & BHND_PMURES_BIT(i))) continue; BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, i); deps |= BHND_PMU_READ_4(sc, BHND_PMU_RES_DEP_MASK); } /* None found? */ if (deps == 0) return (0); /* Recurse dependencies */ if (all) deps |= bhnd_pmu_res_deps(sc, deps, true); return (deps); } /* power up/down OTP through PMU resources */ int bhnd_pmu_otp_power(struct bhnd_pmu_softc *sc, bool on) { uint32_t deps; uint32_t min_mask; uint32_t rsrcs; int error; /* Determine rsrcs to turn on/off OTP power */ switch (sc->cid.chip_id) { case BHND_CHIPID_BCM4322: case BHND_CHIPID_BCM43221: case BHND_CHIPID_BCM43231: case BHND_CHIPID_BCM4342: rsrcs = PMURES_BIT(RES4322_OTP_PU); break; case BHND_CHIPID_BCM4315: rsrcs = PMURES_BIT(RES4315_OTP_PU); break; case BHND_CHIPID_BCM4325: rsrcs = PMURES_BIT(RES4325_OTP_PU); break; case BHND_CHIPID_BCM4329: rsrcs = PMURES_BIT(RES4329_OTP_PU); break; case BHND_CHIPID_BCM4319: rsrcs = PMURES_BIT(RES4319_OTP_PU); break; case BHND_CHIPID_BCM4336: rsrcs = PMURES_BIT(RES4336_OTP_PU); break; case BHND_CHIPID_BCM4330: rsrcs = PMURES_BIT(RES4330_OTP_PU); break; default: /* Not required? */ return (0); } /* Fetch all dependencies */ deps = bhnd_pmu_res_deps(sc, rsrcs, true); /* Exclude the minimum resource set */ if ((error = bhnd_pmu_res_masks(sc, &min_mask, NULL))) return (error); deps &= ~min_mask; /* Turn on/off the power */ if (on) { uint32_t state; PMU_DEBUG(sc, "Adding rsrc 0x%x to min_res_mask\n", rsrcs | deps); BHND_PMU_OR_4(sc, BHND_PMU_MIN_RES_MASK, (rsrcs|deps)); /* Wait for all resources to become available */ for (int i = 0; i < BHND_PMU_MAX_TRANSITION_DLY; i += 10) { state = BHND_PMU_READ_4(sc, BHND_PMU_RES_STATE); if ((state & rsrcs) == rsrcs) break; DELAY(10); } if ((state & rsrcs) != rsrcs) { PMU_LOG(sc, "timeout waiting for OTP resource " "enable\n"); return (ENXIO); } } else { PMU_DEBUG(sc, "Removing rsrc 0x%x from min_res_mask\n", rsrcs | deps); BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, ~(rsrcs|deps)); } return (0); } void bhnd_pmu_rcal(struct bhnd_pmu_softc *sc) { uint32_t chipst; uint32_t val; uint8_t rcal_code; bool bluetooth_rcal; bluetooth_rcal = false; switch (sc->cid.chip_id) { case BHND_CHIPID_BCM4325: case BHND_CHIPID_BCM4329: /* Kick RCal */ BHND_PMU_WRITE_4(sc, BHND_PMU_CHIPCTL_ADDR, 1); /* Power Down RCAL Block */ BHND_PMU_AND_4(sc, BHND_PMU_CHIPCTL_DATA, ~0x04); if (sc->cid.chip_id == BHND_CHIPID_BCM4325) { chipst = BHND_CHIPC_READ_CHIPST(sc->chipc_dev); if (BHND_PMU_GET_BITS(chipst, CHIPC_CST4325_RCAL_VALID)) bluetooth_rcal = true; } /* Power Up RCAL block */ BHND_PMU_AND_4(sc, BHND_PMU_CHIPCTL_DATA, 0x04); /* Wait for completion */ for (int i = 0; i < (10 * 1000 * 1000); i++) { chipst = BHND_CHIPC_READ_CHIPST(sc->chipc_dev); if (chipst & 0x08) break; DELAY(10); } KASSERT((chipst & 0x08) != 0, ("rcal completion timeout")); if (bluetooth_rcal) { rcal_code = 0x6; } else { /* Drop LSB to convert from 5 bit code to 4 bit code */ rcal_code = (uint8_t) (chipst >> 5) & 0x0f; } PMU_DEBUG("RCal completed, status 0x%x, code 0x%x\n", R_REG(&cc->chipstatus), rcal_code); /* Write RCal code into pmu_vreg_ctrl[32:29] */ BHND_PMU_WRITE_4(sc, BHND_PMU_REG_CONTROL_ADDR, 0); val = BHND_PMU_READ_4(sc, BHND_PMU_REG_CONTROL_DATA); val &= ~((uint32_t) 0x07 << 29); val |= (uint32_t) (rcal_code & 0x07) << 29; BHND_PMU_WRITE_4(sc, BHND_PMU_REG_CONTROL_DATA, val); BHND_PMU_WRITE_4(sc, BHND_PMU_REG_CONTROL_ADDR, 1); val = BHND_PMU_READ_4(sc, BHND_PMU_REG_CONTROL_DATA); val &= ~(uint32_t) 0x01; val |= (uint32_t) ((rcal_code >> 3) & 0x01); BHND_PMU_WRITE_4(sc, BHND_PMU_REG_CONTROL_DATA, val); /* Write RCal code into pmu_chip_ctrl[33:30] */ BHND_PMU_WRITE_4(sc, BHND_PMU_CHIPCTL_ADDR, 0); val = BHND_PMU_READ_4(sc, BHND_PMU_CHIPCTL_DATA); val &= ~((uint32_t) 0x03 << 30); val |= (uint32_t) (rcal_code & 0x03) << 30; BHND_PMU_WRITE_4(sc, BHND_PMU_CHIPCTL_DATA, val); BHND_PMU_WRITE_4(sc, BHND_PMU_CHIPCTL_ADDR, 1); val = BHND_PMU_READ_4(sc, BHND_PMU_CHIPCTL_DATA); val &= ~(uint32_t) 0x03; val |= (uint32_t) ((rcal_code >> 2) & 0x03); BHND_PMU_WRITE_4(sc, BHND_PMU_CHIPCTL_DATA, val); /* Set override in pmu_chip_ctrl[29] */ BHND_PMU_WRITE_4(sc, BHND_PMU_CHIPCTL_ADDR, 0); BHND_PMU_OR_4(sc, BHND_PMU_CHIPCTL_DATA, (0x01 << 29)); /* Power off RCal block */ BHND_PMU_WRITE_4(sc, BHND_PMU_CHIPCTL_ADDR, 1); BHND_PMU_AND_4(sc, BHND_PMU_CHIPCTL_DATA, ~0x04); break; default: break; } } void bhnd_pmu_spuravoid(struct bhnd_pmu_softc *sc, uint8_t spuravoid) { /* force the HT off */ if (sc->cid.chip_id == BHND_CHIPID_BCM4336) { BHND_PMU_AND_4(sc, BHND_PMU_MAX_RES_MASK, ~BHND_PMU_RES4336_HT_AVAIL); /* wait for the ht to really go away */ PMU_WAIT_CLKST(sc, 0, BHND_CCS_HTAVAIL); } /* update the pll changes */ bhnd_pmu_spuravoid_pllupdate(sc, spuravoid); /* enable HT back on */ if (sc->cid.chip_id == BHND_CHIPID_BCM4336) { BHND_PMU_OR_4(sc, BHND_PMU_MAX_RES_MASK, BHND_PMU_RES4336_HT_AVAIL); } } static void bhnd_pmu_spuravoid_pllupdate(struct bhnd_pmu_softc *sc, uint8_t spuravoid) { uint16_t chip_id; uint32_t tmp; uint32_t pmuctrl; uint8_t phypll_offset; uint8_t bcm5357_bcm43236_p1div[] = { 0x1, 0x5, 0x5 }; uint8_t bcm5357_bcm43236_ndiv[] = { 0x30, 0xf6, 0xfc }; /* 6362a0 has same clks as 4322[4-6] */ chip_id = sc->cid.chip_id; if (chip_id == BHND_CHIPID_BCM6362 && sc->cid.chip_rev == 0) { chip_id = BHND_CHIPID_BCM43224; } switch (chip_id) { case BHND_CHIPID_BCM6362: KASSERT(sc->cid.chip_rev != 0, ("invalid clock config")); /* fallthrough */ case BHND_CHIPID_BCM5357: case BHND_CHIPID_BCM4749: case BHND_CHIPID_BCM43235: case BHND_CHIPID_BCM43236: case BHND_CHIPID_BCM43238: case BHND_CHIPID_BCM43234: case BHND_CHIPID_BCM43237: case BHND_CHIPID_BCM53572: KASSERT(spuravoid < nitems(bcm5357_bcm43236_p1div), ("spuravoid %hhu outside p1div table\n", spuravoid)); KASSERT(spuravoid < nitems(bcm5357_bcm43236_ndiv), ("spuravoid %hhu outside ndiv table\n", spuravoid)); /* BCM5357 needs to touch PLL1_PLLCTL[02], so offset * PLL0_PLLCTL[02] by 6 */ phypll_offset = 0; if (sc->cid.chip_id == BHND_CHIPID_BCM5357) phypll_offset = 6; /* RMW only the P1 divider */ tmp = BHND_PMU_SET_BITS(bcm5357_bcm43236_p1div[spuravoid], BHND_PMU1_PLL0_PC0_P1DIV); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0 + phypll_offset, tmp, BHND_PMU1_PLL0_PC0_P1DIV_MASK); /* RMW only the int feedback divider */ tmp = BHND_PMU_SET_BITS(bcm5357_bcm43236_ndiv[spuravoid], BHND_PMU1_PLL0_PC2_NDIV_INT); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2 + phypll_offset, tmp, BHND_PMU1_PLL0_PC0_P1DIV_MASK); pmuctrl = BHND_PMU_CTRL_PLL_PLLCTL_UPD; break; case BHND_CHIPID_BCM4331: if (spuravoid == 2) { BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, 0x11500014, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, 0x0FC00a08, ~0); } else if (spuravoid == 1) { BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, 0x11500014, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, 0x0F600a08, ~0); } else { BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, 0x11100014, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, 0x03000a08, ~0); } pmuctrl = BHND_PMU_CTRL_PLL_PLLCTL_UPD; break; case BHND_CHIPID_BCM43224: case BHND_CHIPID_BCM43225: case BHND_CHIPID_BCM43226: case BHND_CHIPID_BCM43421: if (spuravoid == 1) { BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, 0x11500010, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, 0x000C0C06, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, 0x0F600a08, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL3, 0x00000000, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL4, 0x2001E920, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL5, 0x88888815, ~0); } else { BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, 0x11100010, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, 0x000c0c06, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, 0x03000a08, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL3, 0x00000000, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL4, 0x200005c0, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL5, 0x88888815, ~0); } pmuctrl = BHND_PMU_CTRL_PLL_PLLCTL_UPD; break; case BHND_CHIPID_BCM43111: case BHND_CHIPID_BCM43112: case BHND_CHIPID_BCM43222: case BHND_CHIPID_BCM43420: if (spuravoid == 1) { BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, 0x11500008, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, 0x0c000c06, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, 0x0f600a08, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL3, 0x00000000, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL4, 0x2001e920, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL5, 0x88888815, ~0); } else { BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, 0x11100008, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, 0x0c000c06, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, 0x03000a08, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL3, 0x00000000, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL4, 0x200005c0, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL5, 0x88888855, ~0); } pmuctrl = BHND_PMU_CTRL_PLL_PLLCTL_UPD; break; case BHND_CHIPID_BCM4716: case BHND_CHIPID_BCM4748: case BHND_CHIPID_BCM47162: if (spuravoid == 1) { BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, 0x11500060, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, 0x080C0C06, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, 0x0F600000, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL3, 0x00000000, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL4, 0x2001E924, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL5, 0x88888815, ~0); } else { BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, 0x11100060, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, 0x080c0c06, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, 0x03000000, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL3, 0x00000000, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL4, 0x200005c0, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL5, 0x88888815, ~0); } pmuctrl = BHND_PMU_CTRL_NOILP_ON_WAIT | BHND_PMU_CTRL_PLL_PLLCTL_UPD; break; case BHND_CHIPID_BCM4319: pmuctrl = 0; break; case BHND_CHIPID_BCM4322: case BHND_CHIPID_BCM43221: case BHND_CHIPID_BCM43231: case BHND_CHIPID_BCM4342: BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, 0x11100070, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, 0x1014140a, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL5, 0x88888854, ~0); if (spuravoid == 1) { /* spur_avoid ON, enable 41/82/164Mhz clock mode */ BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, 0x05201828, ~0); } else { /* enable 40/80/160Mhz clock mode */ BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, 0x05001828, ~0); } pmuctrl = BHND_PMU_CTRL_PLL_PLLCTL_UPD; break; case BHND_CHIPID_BCM4336: /* Looks like these are only for default xtal freq 26MHz */ BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, 0x02100020, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, 0x0C0C0C0C, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, 0x01240C0C, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL4, 0x202C2820, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL5, 0x88888825, ~0); if (spuravoid == 1) { tmp = 0x00EC4EC4; } else { tmp = 0x00762762; } BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL3, tmp, ~0); pmuctrl = BHND_PMU_CTRL_PLL_PLLCTL_UPD; break; case BHND_CHIPID_BCM43131: case BHND_CHIPID_BCM43227: case BHND_CHIPID_BCM43228: case BHND_CHIPID_BCM43428: /* LCNXN */ /* PLL Settings for spur avoidance on/off mode, no on2 support * for 43228A0 */ if (spuravoid == 1) { BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, 0x01100014, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, 0x040C0C06, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, 0x03140A08, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL3, 0x00333333, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL4, 0x202C2820, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL5, 0x88888815, ~0); } else { BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, 0x11100014, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, 0x040c0c06, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, 0x03000a08, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL3, 0x00000000, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL4, 0x200005c0, ~0); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL5, 0x88888815, ~0); } pmuctrl = BHND_PMU_CTRL_PLL_PLLCTL_UPD; break; default: PMU_LOG(sc, "%s: unknown spuravoidance settings for chip %#hx, " "not changing PLL", __func__, sc->cid.chip_id); pmuctrl = 0; break; } if (pmuctrl != 0) BHND_PMU_OR_4(sc, BHND_PMU_CTRL, pmuctrl); } bool bhnd_pmu_is_otp_powered(struct bhnd_pmu_softc *sc) { uint32_t otp_res; /* Determine per-chip OTP resource */ switch (sc->cid.chip_id) { case BHND_CHIPID_BCM4329: otp_res = PMURES_BIT(RES4329_OTP_PU); break; case BHND_CHIPID_BCM4319: otp_res = PMURES_BIT(RES4319_OTP_PU); break; case BHND_CHIPID_BCM4336: otp_res = PMURES_BIT(RES4336_OTP_PU); break; case BHND_CHIPID_BCM4330: otp_res = PMURES_BIT(RES4330_OTP_PU); break; /* These chips don't use PMU bit to power up/down OTP. OTP always on. * Use OTP_INIT command to reset/refresh state. */ case BHND_CHIPID_BCM43224: case BHND_CHIPID_BCM43225: case BHND_CHIPID_BCM43421: case BHND_CHIPID_BCM43236: case BHND_CHIPID_BCM43235: case BHND_CHIPID_BCM43238: return (true); default: return (true); } /* Check resource state */ if ((BHND_PMU_READ_4(sc, BHND_PMU_RES_STATE) & otp_res) == 0) return (false); return (true); } void bhnd_pmu_paref_ldo_enable(struct bhnd_pmu_softc *sc, bool enable) { uint32_t ldo; switch (sc->cid.chip_id) { case BHND_CHIPID_BCM4328: ldo = PMURES_BIT(RES4328_PA_REF_LDO); break; case BHND_CHIPID_BCM5354: ldo = PMURES_BIT(RES5354_PA_REF_LDO); break; case BHND_CHIPID_BCM4312: ldo = PMURES_BIT(RES4312_PA_REF_LDO); break; default: return; } if (enable) { BHND_PMU_OR_4(sc, BHND_PMU_MIN_RES_MASK, ldo); } else { BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, ~ldo); } } /* initialize PMU switch/regulators */ void bhnd_pmu_swreg_init(struct bhnd_pmu_softc *sc) { uint32_t chipst; switch (sc->cid.chip_id) { case BHND_CHIPID_BCM4325: if (sc->cid.chip_rev <= 2) break; chipst = BHND_CHIPC_READ_CHIPST(sc->chipc_dev); if (BHND_PMU_GET_BITS(chipst, CHIPC_CST4325_PMUTOP_2B)) { bhnd_pmu_set_ldo_voltage(sc, SET_LDO_VOLTAGE_CLDO_PWM, 0xf); bhnd_pmu_set_ldo_voltage(sc, SET_LDO_VOLTAGE_CLDO_BURST, 0xf); } bhnd_pmu_set_ldo_voltage(sc, SET_LDO_VOLTAGE_CBUCK_PWM, 0xb); bhnd_pmu_set_ldo_voltage(sc, SET_LDO_VOLTAGE_CBUCK_BURST, 0xb); bhnd_pmu_set_ldo_voltage(sc, SET_LDO_VOLTAGE_LNLDO1, 0x1); if (sc->board.board_flags & BHND_BFL_LNLDO2_2P5) { bhnd_pmu_set_ldo_voltage(sc, SET_LDO_VOLTAGE_LNLDO2_SEL, 0x1); } break; case BHND_CHIPID_BCM4336: /* Reduce CLDO PWM output voltage to 1.2V */ bhnd_pmu_set_ldo_voltage(sc, SET_LDO_VOLTAGE_CLDO_PWM, 0xe); /* Reduce CLDO BURST output voltage to 1.2V */ bhnd_pmu_set_ldo_voltage(sc, SET_LDO_VOLTAGE_CLDO_BURST, 0xe); /* Reduce LNLDO1 output voltage to 1.2V */ bhnd_pmu_set_ldo_voltage(sc, SET_LDO_VOLTAGE_LNLDO1, 0xe); if (sc->cid.chip_rev == 0) BHND_PMU_REGCTRL_WRITE(sc, 2, 0x400000, 0x400000); break; case BHND_CHIPID_BCM4330: /* CBUCK Voltage is 1.8 by default and set that to 1.5 */ bhnd_pmu_set_ldo_voltage(sc, SET_LDO_VOLTAGE_CBUCK_PWM, 0); break; default: break; } } -void +int bhnd_pmu_radio_enable(struct bhnd_pmu_softc *sc, device_t d11core, bool enable) { - uint32_t oobsel; - uint32_t rsrcs; + uint32_t oobsel; + uint32_t rsrcs; + int error; - if (bhnd_get_device(d11core) != BHND_COREID_D11) - panic("bhnd_pmu_radio_enable() called on non-D11 core"); + if (bhnd_get_device(d11core) != BHND_COREID_D11) { + device_printf(sc->dev, + "bhnd_pmu_radio_enable() called on non-D11 core"); + return (EINVAL); + } switch (sc->cid.chip_id) { case BHND_CHIPID_BCM4325: if (sc->board.board_flags & BHND_BFL_FASTPWR) break; if ((sc->board.board_flags & BHND_BFL_BUCKBOOST) == 0) break; rsrcs = PMURES_BIT(RES4325_BUCK_BOOST_BURST); if (enable) { BHND_PMU_OR_4(sc, BHND_PMU_MIN_RES_MASK, rsrcs); DELAY(100 * 1000); /* 100ms */ } else { BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, ~rsrcs); } - break; + return (0); + case BHND_CHIPID_BCM4319: - oobsel = bhnd_read_config(d11core, BCMA_DMP_OOBSELOUTB74, 4); + error = bhnd_read_config(d11core, BCMA_DMP_OOBSELOUTB74, + &oobsel, 4); + if (error) + return (error); if (enable) { oobsel |= BHND_PMU_SET_BITS(BCMA_DMP_OOBSEL_EN, BCMA_DMP_OOBSEL_5); oobsel |= BHND_PMU_SET_BITS(BCMA_DMP_OOBSEL_EN, BCMA_DMP_OOBSEL_6); } else { oobsel &= ~BHND_PMU_SET_BITS(BCMA_DMP_OOBSEL_EN, BCMA_DMP_OOBSEL_5); oobsel &= ~BHND_PMU_SET_BITS(BCMA_DMP_OOBSEL_EN, BCMA_DMP_OOBSEL_6); } - bhnd_write_config(d11core, BCMA_DMP_OOBSELOUTB74, oobsel, 4); - break; + return (bhnd_write_config(d11core, BCMA_DMP_OOBSELOUTB74, + &oobsel, 4)); } + + return (0); } /* Wait for a particular clock level to be on the backplane */ uint32_t bhnd_pmu_waitforclk_on_backplane(struct bhnd_pmu_softc *sc, uint32_t clk, uint32_t delay) { uint32_t pmu_st; for (uint32_t i = 0; i < delay; i += 10) { pmu_st = BHND_PMU_READ_4(sc, BHND_PMU_ST); if ((pmu_st & clk) == clk) return (clk); DELAY(10); } pmu_st = BHND_PMU_READ_4(sc, BHND_PMU_ST); return (pmu_st & clk); } /* * Measures the ALP clock frequency in KHz. Returns 0 if not possible. * Possible only if PMU rev >= 10 and there is an external LPO 32768Hz crystal. */ #define EXT_ILP_HZ 32768 uint32_t bhnd_pmu_measure_alpclk(struct bhnd_pmu_softc *sc) { uint32_t alp_khz; uint32_t pmu_st; if (BHND_PMU_REV(sc) < 10) return (0); pmu_st = BHND_PMU_READ_4(sc, BHND_PMU_ST); if (pmu_st & BHND_PMU_ST_EXTLPOAVAIL) { uint32_t alp_hz, ilp_ctr; /* Enable frequency measurement */ BHND_PMU_WRITE_4(sc, BHND_PMU_XTALFREQ, 1U << BHND_PMU_XTALFREQ_REG_MEASURE_SHIFT); /* Delay for well over 4 ILP clocks */ DELAY(1000); /* Read the latched number of ALP ticks per 4 ILP ticks */ ilp_ctr = BHND_PMU_READ_4(sc, BHND_PMU_XTALFREQ); ilp_ctr = BHND_PMU_GET_BITS(ilp_ctr, BHND_PMU_XTALFREQ_REG_ILPCTR); /* Turn off PMU_XTALFREQ_REG_MEASURE to save power */ BHND_PMU_WRITE_4(sc, BHND_PMU_XTALFREQ, 0); /* Calculate ALP frequency */ alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4; /* Round to nearest 100KHz and convert to KHz */ alp_khz = (alp_hz + 50000) / 100000 * 100; } else { alp_khz = 0; } return (alp_khz); } static void bhnd_pmu_set_4330_plldivs(struct bhnd_pmu_softc *sc) { uint32_t FVCO = bhnd_pmu1_pllfvco0(&sc->query) / 1000; uint32_t m1div, m2div, m3div, m4div, m5div, m6div; uint32_t pllc1, pllc2; m2div = m3div = m4div = m6div = FVCO / 80; m5div = FVCO / 160; if (PMU_CST4330_SDIOD_CHIPMODE(sc)) m1div = FVCO / 80; else m1div = FVCO / 90; pllc1 = 0; pllc1 |= BHND_PMU_SET_BITS(m1div, BHND_PMU1_PLL0_PC1_M1DIV); pllc1 |= BHND_PMU_SET_BITS(m2div, BHND_PMU1_PLL0_PC1_M2DIV); pllc1 |= BHND_PMU_SET_BITS(m3div, BHND_PMU1_PLL0_PC1_M3DIV); pllc1 |= BHND_PMU_SET_BITS(m4div, BHND_PMU1_PLL0_PC1_M4DIV); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, pllc1, ~0); pllc2 = 0; pllc2 |= BHND_PMU_SET_BITS(m5div, BHND_PMU1_PLL0_PC2_M5DIV); pllc2 |= BHND_PMU_SET_BITS(m6div, BHND_PMU1_PLL0_PC2_M6DIV); BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, pllc2, BHND_PMU1_PLL0_PC2_M5DIV_MASK | BHND_PMU1_PLL0_PC2_M6DIV_MASK); } Index: head/sys/dev/bhnd/cores/usb/bhnd_usb.c =================================================================== --- head/sys/dev/bhnd/cores/usb/bhnd_usb.c (revision 306286) +++ head/sys/dev/bhnd/cores/usb/bhnd_usb.c (revision 306287) @@ -1,487 +1,486 @@ /*- * Copyright (c) 2010, Aleksandr Rybalko * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * Ported version of BroadCom USB core driver from ZRouter project */ #include #include #include #include #include #include #include #include #include #include #include -#include #include #include "bhnd_usbvar.h" /****************************** Variables ************************************/ static const struct bhnd_device bhnd_usb_devs[] = { BHND_DEVICE(BCM, USB, "USB1.1 Host/Device core", NULL), BHND_DEVICE(BCM, USB20H, "USB2.0 Host core", NULL), BHND_DEVICE(BCM, USB20D, "USB2.0 Device core", NULL), BHND_DEVICE(BCM, USB11H, "USB1.1 Host core", NULL), BHND_DEVICE(BCM, USB11D, "USB1.1 Device core", NULL), BHND_DEVICE_END }; /****************************** Prototypes ***********************************/ static int bhnd_usb_attach(device_t); static int bhnd_usb_probe(device_t); static device_t bhnd_usb_add_child(device_t dev, u_int order, const char *name, int unit); static int bhnd_usb_print_all_resources(device_t dev); static int bhnd_usb_print_child(device_t bus, device_t child); static struct resource * bhnd_usb_alloc_resource(device_t bus, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags); static int bhnd_usb_release_resource(device_t dev, device_t child, int type, int rid, struct resource *r); static struct resource_list * bhnd_usb_get_reslist(device_t dev, device_t child); static int bhnd_usb_probe(device_t dev) { const struct bhnd_device *id; id = bhnd_device_lookup(dev, bhnd_usb_devs, sizeof(bhnd_usb_devs[0])); if (id == NULL) return (ENXIO); device_set_desc(dev, id->desc); return (BUS_PROBE_DEFAULT); } static int bhnd_usb_attach(device_t dev) { struct bhnd_usb_softc *sc; int rid; uint32_t tmp; int tries, err; sc = device_get_softc(dev); - BHND_BUS_RESET_CORE(device_get_parent(dev), dev, 0); + bhnd_reset_hw(dev, 0); /* * Allocate the resources which the parent bus has already * determined for us. * XXX: There are few windows (usually 2), RID should be chip-specific */ rid = 0; sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->sc_mem == NULL) { BHND_ERROR_DEV(dev, "unable to allocate memory"); return (ENXIO); } sc->sc_bt = rman_get_bustag(sc->sc_mem); sc->sc_bh = rman_get_bushandle(sc->sc_mem); sc->sc_maddr = rman_get_start(sc->sc_mem); sc->sc_msize = rman_get_size(sc->sc_mem); rid = 0; sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); if (sc->sc_irq == NULL) { BHND_ERROR_DEV(dev, "unable to allocate IRQ"); return (ENXIO); } sc->sc_irqn = rman_get_start(sc->sc_irq); sc->mem_rman.rm_start = sc->sc_maddr; sc->mem_rman.rm_end = sc->sc_maddr + sc->sc_msize - 1; sc->mem_rman.rm_type = RMAN_ARRAY; sc->mem_rman.rm_descr = "BHND USB core I/O memory addresses"; if (rman_init(&sc->mem_rman) != 0 || rman_manage_region(&sc->mem_rman, sc->mem_rman.rm_start, sc->mem_rman.rm_end) != 0) { panic("%s: sc->mem_rman", __func__); } sc->irq_rman.rm_start = sc->sc_irqn; sc->irq_rman.rm_end = sc->sc_irqn; sc->irq_rman.rm_type = RMAN_ARRAY; sc->irq_rman.rm_descr = "BHND USB core IRQ"; /* * BHND USB share same IRQ between OHCI and EHCI */ if (rman_init(&sc->irq_rman) != 0 || rman_manage_region(&sc->irq_rman, sc->irq_rman.rm_start, sc->irq_rman.rm_end) != 0) panic("%s: failed to set up IRQ rman", __func__); /* TODO: macros for registers */ bus_write_4(sc->sc_mem, 0x200, 0x7ff); DELAY(100); #define OHCI_CONTROL 0x04 bus_write_4(sc->sc_mem, OHCI_CONTROL, 0); if ( bhnd_get_device(dev) == BHND_COREID_USB20H) { uint32_t rev; BHND_INFO_DEV(dev, "USB HOST 2.0 setup for rev %d", rev); rev = bhnd_get_hwrev(dev); if (rev == 1/* ? == 2 */) { /* SiBa code */ /* Change Flush control reg */ tmp = bus_read_4(sc->sc_mem, 0x400) & ~0x8; bus_write_4(sc->sc_mem, 0x400, tmp); tmp = bus_read_4(sc->sc_mem, 0x400); BHND_DEBUG_DEV(dev, "USB20H fcr: 0x%x", tmp); /* Change Shim control reg */ tmp = bus_read_4(sc->sc_mem, 0x304) & ~0x100; bus_write_4(sc->sc_mem, 0x304, tmp); tmp = bus_read_4(sc->sc_mem, 0x304); BHND_DEBUG_DEV(dev, "USB20H shim: 0x%x", tmp); } else if (rev >= 5) { /* BCMA code */ err = bhnd_alloc_pmu(dev); if(err) { BHND_ERROR_DEV(dev, "can't alloc pmu: %d", err); return (err); } err = bhnd_request_ext_rsrc(dev, 1); if(err) { BHND_ERROR_DEV(dev, "can't req ext: %d", err); return (err); } /* Take out of resets */ bus_write_4(sc->sc_mem, 0x200, 0x4ff); DELAY(25); bus_write_4(sc->sc_mem, 0x200, 0x6ff); DELAY(25); /* Make sure digital and AFE are locked in USB PHY */ bus_write_4(sc->sc_mem, 0x524, 0x6b); DELAY(50); bus_read_4(sc->sc_mem, 0x524); DELAY(50); bus_write_4(sc->sc_mem, 0x524, 0xab); DELAY(50); bus_read_4(sc->sc_mem, 0x524); DELAY(50); bus_write_4(sc->sc_mem, 0x524, 0x2b); DELAY(50); bus_read_4(sc->sc_mem, 0x524); DELAY(50); bus_write_4(sc->sc_mem, 0x524, 0x10ab); DELAY(50); bus_read_4(sc->sc_mem, 0x524); tries = 10000; for (;;) { DELAY(10); tmp = bus_read_4(sc->sc_mem, 0x528); if (tmp & 0xc000) break; if (--tries != 0) continue; tmp = bus_read_4(sc->sc_mem, 0x528); BHND_ERROR_DEV(dev, "USB20H mdio_rddata 0x%08x", tmp); } /* XXX: Puzzle code */ bus_write_4(sc->sc_mem, 0x528, 0x80000000); bus_read_4(sc->sc_mem, 0x314); DELAY(265); bus_write_4(sc->sc_mem, 0x200, 0x7ff); DELAY(10); /* Take USB and HSIC out of non-driving modes */ bus_write_4(sc->sc_mem, 0x510, 0); } } bus_generic_probe(dev); if (bhnd_get_device(dev) == BHND_COREID_USB20H && ( bhnd_get_hwrev(dev) > 0)) bhnd_usb_add_child(dev, 0, "ehci", -1); bhnd_usb_add_child(dev, 1, "ohci", -1); bus_generic_attach(dev); return (0); } static struct resource * bhnd_usb_alloc_resource(device_t bus, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) { struct resource *rv; struct resource_list *rl; struct resource_list_entry *rle; int isdefault, needactivate; struct bhnd_usb_softc *sc = device_get_softc(bus); isdefault = RMAN_IS_DEFAULT_RANGE(start,end); needactivate = flags & RF_ACTIVE; rl = BUS_GET_RESOURCE_LIST(bus, child); rle = NULL; if (isdefault) { BHND_INFO_DEV(bus, "trying allocate def %d - %d for %s", type, *rid, device_get_nameunit(child) ); rle = resource_list_find(rl, type, *rid); if (rle == NULL) return (NULL); if (rle->res != NULL) panic("%s: resource entry is busy", __func__); start = rle->start; end = rle->end; count = rle->count; } else { BHND_INFO_DEV(bus, "trying allocate %d - %d (%jx-%jx) for %s", type, *rid, start, end, device_get_nameunit(child) ); } /* * If the request is for a resource which we manage, * attempt to satisfy the allocation ourselves. */ if (type == SYS_RES_MEMORY) { rv = rman_reserve_resource(&sc->mem_rman, start, end, count, flags, child); if (rv == 0) { BHND_ERROR_DEV(bus, "could not reserve resource"); return (0); } rman_set_rid(rv, *rid); if (needactivate && bus_activate_resource(child, type, *rid, rv)) { BHND_ERROR_DEV(bus, "could not activate resource"); rman_release_resource(rv); return (0); } return (rv); } if (type == SYS_RES_IRQ) { rv = rman_reserve_resource(&sc->irq_rman, start, end, count, flags, child); if (rv == 0) { BHND_ERROR_DEV(bus, "could not reserve resource"); return (0); } rman_set_rid(rv, *rid); if (needactivate && bus_activate_resource(child, type, *rid, rv)) { BHND_ERROR_DEV(bus, "could not activate resource"); rman_release_resource(rv); return (0); } return (rv); } /* * Pass the request to the parent. */ return (resource_list_alloc(rl, bus, child, type, rid, start, end, count, flags)); } static struct resource_list * bhnd_usb_get_reslist(device_t dev, device_t child) { struct bhnd_usb_devinfo *sdi; sdi = device_get_ivars(child); return (&sdi->sdi_rl); } static int bhnd_usb_release_resource(device_t dev, device_t child, int type, int rid, struct resource *r) { struct resource_list *rl; struct resource_list_entry *rle; rl = bhnd_usb_get_reslist(dev, child); if (rl == NULL) return (EINVAL); rle = resource_list_find(rl, type, rid); if (rle == NULL) return (EINVAL); rman_release_resource(r); rle->res = NULL; return (0); } static int bhnd_usb_print_all_resources(device_t dev) { struct bhnd_usb_devinfo *sdi; struct resource_list *rl; int retval; retval = 0; sdi = device_get_ivars(dev); rl = &sdi->sdi_rl; if (STAILQ_FIRST(rl)) retval += printf(" at"); retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%jx"); retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); return (retval); } static int bhnd_usb_print_child(device_t bus, device_t child) { int retval = 0; retval += bus_print_child_header(bus, child); retval += bhnd_usb_print_all_resources(child); if (device_get_flags(child)) retval += printf(" flags %#x", device_get_flags(child)); retval += printf(" on %s\n", device_get_nameunit(bus)); return (retval); } static device_t bhnd_usb_add_child(device_t dev, u_int order, const char *name, int unit) { struct bhnd_usb_softc *sc; struct bhnd_usb_devinfo *sdi; device_t child; sc = device_get_softc(dev); child = device_add_child_ordered(dev, order, name, unit); if (child == NULL) return (NULL); sdi = malloc(sizeof(struct bhnd_usb_devinfo), M_DEVBUF, M_NOWAIT|M_ZERO); if (sdi == NULL) return (NULL); if (strncmp(name, "ohci", 4) == 0) { sdi->sdi_maddr = sc->sc_maddr + 0x000; sdi->sdi_msize = 0x200; sdi->sdi_irq = sc->sc_irqn; BHND_INFO_DEV(dev, "ohci: irq=%d maddr=0x%jx", sdi->sdi_irq, sdi->sdi_maddr); } else if (strncmp(name, "ehci", 4) == 0) { sdi->sdi_maddr = sc->sc_maddr + 0x000; sdi->sdi_msize = 0x1000; sdi->sdi_irq = sc->sc_irqn; BHND_INFO_DEV(dev, "ehci: irq=%d maddr=0x%jx", sdi->sdi_irq, sdi->sdi_maddr); } else { panic("Unknown subdevice"); /* Unknown subdevice */ sdi->sdi_maddr = 1; sdi->sdi_msize = 1; sdi->sdi_irq = 1; } resource_list_init(&sdi->sdi_rl); /* * Determine memory window on bus and irq if one is needed. */ resource_list_add(&sdi->sdi_rl, SYS_RES_MEMORY, 0, sdi->sdi_maddr, sdi->sdi_maddr + sdi->sdi_msize - 1, sdi->sdi_msize); resource_list_add(&sdi->sdi_rl, SYS_RES_IRQ, 0, sdi->sdi_irq, sdi->sdi_irq, 1); device_set_ivars(child, sdi); return (child); } static device_method_t bhnd_usb_methods[] = { /* Device interface */ DEVMETHOD(device_attach, bhnd_usb_attach), DEVMETHOD(device_probe, bhnd_usb_probe), /* Bus interface */ DEVMETHOD(bus_add_child, bhnd_usb_add_child), DEVMETHOD(bus_alloc_resource, bhnd_usb_alloc_resource), DEVMETHOD(bus_get_resource_list, bhnd_usb_get_reslist), DEVMETHOD(bus_print_child, bhnd_usb_print_child), DEVMETHOD(bus_release_resource, bhnd_usb_release_resource), /* Bus interface: generic part */ DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), DEVMETHOD_END }; static devclass_t bhnd_usb_devclass; DEFINE_CLASS_0(bhnd_usb, bhnd_usb_driver, bhnd_usb_methods, sizeof(struct bhnd_usb_softc)); DRIVER_MODULE(bhnd_usb, bhnd, bhnd_usb_driver, bhnd_usb_devclass, 0, 0); MODULE_VERSION(bhnd_usb, 1); Index: head/sys/dev/bhnd/siba/siba.c =================================================================== --- head/sys/dev/bhnd/siba/siba.c (revision 306286) +++ head/sys/dev/bhnd/siba/siba.c (revision 306287) @@ -1,716 +1,971 @@ /*- * Copyright (c) 2015 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include +#include #include "sibareg.h" #include "sibavar.h" static bhnd_erom_class_t * siba_get_erom_class(driver_t *driver) { return (&siba_erom_parser); } int siba_probe(device_t dev) { device_set_desc(dev, "SIBA BHND bus"); return (BUS_PROBE_DEFAULT); } /** * Default siba(4) bus driver implementation of DEVICE_ATTACH(). * * This implementation initializes internal siba(4) state and performs * bus enumeration, and must be called by subclassing drivers in * DEVICE_ATTACH() before any other bus methods. */ int siba_attach(device_t dev) { struct siba_softc *sc; int error; sc = device_get_softc(dev); sc->dev = dev; /* Enumerate children */ if ((error = siba_add_children(dev))) { device_delete_children(dev); return (error); } return (0); } int siba_detach(device_t dev) { return (bhnd_generic_detach(dev)); } int siba_resume(device_t dev) { return (bhnd_generic_resume(dev)); } int siba_suspend(device_t dev) { return (bhnd_generic_suspend(dev)); } static int siba_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) { const struct siba_devinfo *dinfo; const struct bhnd_core_info *cfg; dinfo = device_get_ivars(child); cfg = &dinfo->core_id.core_info; switch (index) { case BHND_IVAR_VENDOR: *result = cfg->vendor; return (0); case BHND_IVAR_DEVICE: *result = cfg->device; return (0); case BHND_IVAR_HWREV: *result = cfg->hwrev; return (0); case BHND_IVAR_DEVICE_CLASS: *result = bhnd_core_class(cfg); return (0); case BHND_IVAR_VENDOR_NAME: *result = (uintptr_t) bhnd_vendor_name(cfg->vendor); return (0); case BHND_IVAR_DEVICE_NAME: *result = (uintptr_t) bhnd_core_name(cfg); return (0); case BHND_IVAR_CORE_INDEX: *result = cfg->core_idx; return (0); case BHND_IVAR_CORE_UNIT: *result = cfg->unit; return (0); + case BHND_IVAR_PMU_INFO: + *result = (uintptr_t) dinfo->pmu_info; + return (0); default: return (ENOENT); } } static int siba_write_ivar(device_t dev, device_t child, int index, uintptr_t value) { + struct siba_devinfo *dinfo; + + dinfo = device_get_ivars(child); + switch (index) { case BHND_IVAR_VENDOR: case BHND_IVAR_DEVICE: case BHND_IVAR_HWREV: case BHND_IVAR_DEVICE_CLASS: case BHND_IVAR_VENDOR_NAME: case BHND_IVAR_DEVICE_NAME: case BHND_IVAR_CORE_INDEX: case BHND_IVAR_CORE_UNIT: return (EINVAL); + case BHND_IVAR_PMU_INFO: + dinfo->pmu_info = (struct bhnd_core_pmu_info *) value; + return (0); default: return (ENOENT); } } static struct resource_list * siba_get_resource_list(device_t dev, device_t child) { struct siba_devinfo *dinfo = device_get_ivars(child); return (&dinfo->resources); } static int -siba_reset_core(device_t dev, device_t child, uint16_t flags) +siba_read_iost(device_t dev, device_t child, uint16_t *iost) { - struct siba_devinfo *dinfo; + uint32_t tmhigh; + int error; + error = bhnd_read_config(child, SIBA_CFG0_TMSTATEHIGH, &tmhigh, 4); + if (error) + return (error); + + *iost = (SIBA_REG_GET(tmhigh, TMH_SISF)); + return (0); +} + +static int +siba_read_ioctl(device_t dev, device_t child, uint16_t *ioctl) +{ + uint32_t ts_low; + int error; + + if ((error = bhnd_read_config(child, SIBA_CFG0_TMSTATELOW, &ts_low, 4))) + return (error); + + *ioctl = (SIBA_REG_GET(ts_low, TML_SICF)); + return (0); +} + +static int +siba_write_ioctl(device_t dev, device_t child, uint16_t value, uint16_t mask) +{ + struct siba_devinfo *dinfo; + struct bhnd_resource *r; + uint32_t ts_low, ts_mask; + if (device_get_parent(child) != dev) - BHND_BUS_RESET_CORE(device_get_parent(dev), child, flags); + return (EINVAL); + /* Fetch CFG0 mapping */ dinfo = device_get_ivars(child); + if ((r = dinfo->cfg[0]) == NULL) + return (ENODEV); - /* Can't reset the core without access to the CFG0 registers */ - if (dinfo->cfg[0] == NULL) + /* Mask and set TMSTATELOW core flag bits */ + ts_mask = (mask << SIBA_TML_SICF_SHIFT) & SIBA_TML_SICF_MASK; + ts_low = (value << SIBA_TML_SICF_SHIFT) & ts_mask; + + return (siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATELOW, + ts_low, ts_mask)); +} + +static bool +siba_is_hw_suspended(device_t dev, device_t child) +{ + uint32_t ts_low; + uint16_t ioctl; + int error; + + /* Fetch target state */ + error = bhnd_read_config(child, SIBA_CFG0_TMSTATELOW, &ts_low, 4); + if (error) { + device_printf(child, "error reading HW reset state: %d\n", + error); + return (true); + } + + /* Is core held in RESET? */ + if (ts_low & SIBA_TML_RESET) + return (true); + + /* Is core clocked? */ + ioctl = SIBA_REG_GET(ts_low, TML_SICF); + if (!(ioctl & BHND_IOCTL_CLK_EN)) + return (true); + + return (false); +} + +static int +siba_reset_hw(device_t dev, device_t child, uint16_t ioctl) +{ + struct siba_devinfo *dinfo; + struct bhnd_resource *r; + uint32_t ts_low, imstate; + int error; + + if (device_get_parent(child) != dev) + return (EINVAL); + + dinfo = device_get_ivars(child); + + /* Can't suspend the core without access to the CFG0 registers */ + if ((r = dinfo->cfg[0]) == NULL) return (ENODEV); - // TODO - perform reset + /* We require exclusive control over BHND_IOCTL_CLK_EN and + * BHND_IOCTL_CLK_FORCE. */ + if (ioctl & (BHND_IOCTL_CLK_EN | BHND_IOCTL_CLK_FORCE)) + return (EINVAL); - return (ENXIO); + /* Place core into known RESET state */ + if ((error = BHND_BUS_SUSPEND_HW(dev, child))) + return (error); + + /* Leaving the core in reset, set the caller's IOCTL flags and + * enable the core's clocks. */ + ts_low = (ioctl | BHND_IOCTL_CLK_EN | BHND_IOCTL_CLK_FORCE) << + SIBA_TML_SICF_SHIFT; + error = siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATELOW, + ts_low, SIBA_TML_SICF_MASK); + if (error) + return (error); + + /* Clear any target errors */ + if (bhnd_bus_read_4(r, SIBA_CFG0_TMSTATEHIGH) & SIBA_TMH_SERR) { + error = siba_write_target_state(child, dinfo, + SIBA_CFG0_TMSTATEHIGH, 0, SIBA_TMH_SERR); + if (error) + return (error); + } + + /* Clear any initiator errors */ + imstate = bhnd_bus_read_4(r, SIBA_CFG0_IMSTATE); + if (imstate & (SIBA_IM_IBE|SIBA_IM_TO)) { + error = siba_write_target_state(child, dinfo, SIBA_CFG0_IMSTATE, + 0, SIBA_IM_IBE|SIBA_IM_TO); + if (error) + return (error); + } + + /* Release from RESET while leaving clocks forced, ensuring the + * signal propagates throughout the core */ + error = siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATELOW, + 0x0, SIBA_TML_RESET); + if (error) + return (error); + + /* The core should now be active; we can clear the BHND_IOCTL_CLK_FORCE + * bit and allow the core to manage clock gating. */ + error = siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATELOW, + 0x0, (BHND_IOCTL_CLK_FORCE << SIBA_TML_SICF_SHIFT)); + if (error) + return (error); + + return (0); } static int -siba_suspend_core(device_t dev, device_t child) +siba_suspend_hw(device_t dev, device_t child) { - struct siba_devinfo *dinfo; + struct siba_devinfo *dinfo; + struct bhnd_core_pmu_info *pm; + struct bhnd_resource *r; + uint32_t idl, ts_low; + uint16_t ioctl; + int error; if (device_get_parent(child) != dev) - BHND_BUS_SUSPEND_CORE(device_get_parent(dev), child); + return (EINVAL); dinfo = device_get_ivars(child); + pm = dinfo->pmu_info; /* Can't suspend the core without access to the CFG0 registers */ - if (dinfo->cfg[0] == NULL) + if ((r = dinfo->cfg[0]) == NULL) return (ENODEV); - // TODO - perform suspend + /* Already in RESET? */ + ts_low = bhnd_bus_read_4(r, SIBA_CFG0_TMSTATELOW); + if (ts_low & SIBA_TML_RESET) { + /* Clear IOCTL flags, ensuring the clock is disabled */ + return (siba_write_target_state(child, dinfo, + SIBA_CFG0_TMSTATELOW, 0x0, SIBA_TML_SICF_MASK)); - return (ENXIO); + return (0); + } + + /* If clocks are already disabled, we can put the core directly + * into RESET */ + ioctl = SIBA_REG_GET(ts_low, TML_SICF); + if (!(ioctl & BHND_IOCTL_CLK_EN)) { + /* Set RESET and clear IOCTL flags */ + return (siba_write_target_state(child, dinfo, + SIBA_CFG0_TMSTATELOW, + SIBA_TML_RESET, + SIBA_TML_RESET | SIBA_TML_SICF_MASK)); + } + + /* Reject any further target backplane transactions */ + error = siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATELOW, + SIBA_TML_REJ, SIBA_TML_REJ); + if (error) + return (error); + + /* If this is an initiator core, we need to reject initiator + * transactions too. */ + idl = bhnd_bus_read_4(r, SIBA_CFG0_IDLOW); + if (idl & SIBA_IDL_INIT) { + error = siba_write_target_state(child, dinfo, SIBA_CFG0_IMSTATE, + SIBA_IM_RJ, SIBA_IM_RJ); + if (error) + return (error); + } + + /* Put the core into RESET|REJECT, forcing clocks to ensure the RESET + * signal propagates throughout the core, leaving REJECT asserted. */ + ts_low = SIBA_TML_RESET; + ts_low |= (BHND_IOCTL_CLK_EN | BHND_IOCTL_CLK_FORCE) << + SIBA_TML_SICF_SHIFT; + + error = siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATELOW, + ts_low, ts_low); + if (error) + return (error); + + /* Give RESET ample time */ + DELAY(10); + + /* Leaving core in reset, disable all clocks, clear REJ flags and + * IOCTL state */ + error = siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATELOW, + SIBA_TML_RESET, + SIBA_TML_RESET | SIBA_TML_REJ | SIBA_TML_SICF_MASK); + if (error) + return (error); + + /* Clear previously asserted initiator reject */ + if (idl & SIBA_IDL_INIT) { + error = siba_write_target_state(child, dinfo, SIBA_CFG0_IMSTATE, + 0, SIBA_IM_RJ); + if (error) + return (error); + } + + /* Core is now in RESET, with clocks disabled and REJ not asserted. + * + * We lastly need to inform the PMU, releasing any outstanding per-core + * PMU requests */ + if (pm != NULL) { + if ((error = BHND_PMU_CORE_RELEASE(pm->pm_pmu, pm))) + return (error); + } + + return (0); } -static uint32_t -siba_read_config(device_t dev, device_t child, bus_size_t offset, u_int width) +static int +siba_read_config(device_t dev, device_t child, bus_size_t offset, void *value, + u_int width) { struct siba_devinfo *dinfo; rman_res_t r_size; /* Must be directly attached */ if (device_get_parent(child) != dev) - return (UINT32_MAX); + return (EINVAL); /* CFG0 registers must be available */ dinfo = device_get_ivars(child); if (dinfo->cfg[0] == NULL) - return (UINT32_MAX); + return (ENODEV); /* Offset must fall within CFG0 */ r_size = rman_get_size(dinfo->cfg[0]->res); if (r_size < offset || r_size - offset < width) - return (UINT32_MAX); + return (EFAULT); switch (width) { case 1: - return (bhnd_bus_read_1(dinfo->cfg[0], offset)); + *((uint8_t *)value) = bhnd_bus_read_1(dinfo->cfg[0], offset); + return (0); case 2: - return (bhnd_bus_read_2(dinfo->cfg[0], offset)); + *((uint16_t *)value) = bhnd_bus_read_2(dinfo->cfg[0], offset); + return (0); case 4: - return (bhnd_bus_read_4(dinfo->cfg[0], offset)); + *((uint32_t *)value) = bhnd_bus_read_4(dinfo->cfg[0], offset); + return (0); + default: + return (EINVAL); } - - /* Unsuported */ - return (UINT32_MAX); } -static void -siba_write_config(device_t dev, device_t child, bus_size_t offset, uint32_t val, - u_int width) +static int +siba_write_config(device_t dev, device_t child, bus_size_t offset, + const void *value, u_int width) { struct siba_devinfo *dinfo; + struct bhnd_resource *r; rman_res_t r_size; /* Must be directly attached */ if (device_get_parent(child) != dev) - return; + return (EINVAL); /* CFG0 registers must be available */ dinfo = device_get_ivars(child); - if (dinfo->cfg[0] == NULL) - return; + if ((r = dinfo->cfg[0]) == NULL) + return (ENODEV); /* Offset must fall within CFG0 */ - r_size = rman_get_size(dinfo->cfg[0]->res); + r_size = rman_get_size(r->res); if (r_size < offset || r_size - offset < width) - return; + return (EFAULT); switch (width) { case 1: - bhnd_bus_write_1(dinfo->cfg[0], offset, val); + bhnd_bus_write_1(r, offset, *(const uint8_t *)value); + return (0); case 2: - bhnd_bus_write_2(dinfo->cfg[0], offset, val); + bhnd_bus_write_2(r, offset, *(const uint8_t *)value); + return (0); case 4: - bhnd_bus_write_4(dinfo->cfg[0], offset, val); + bhnd_bus_write_4(r, offset, *(const uint8_t *)value); + return (0); + default: + return (EINVAL); } } static u_int siba_get_port_count(device_t dev, device_t child, bhnd_port_type type) { struct siba_devinfo *dinfo; /* delegate non-bus-attached devices to our parent */ if (device_get_parent(child) != dev) return (BHND_BUS_GET_PORT_COUNT(device_get_parent(dev), child, type)); dinfo = device_get_ivars(child); return (siba_addrspace_port_count(dinfo->core_id.num_addrspace)); } static u_int siba_get_region_count(device_t dev, device_t child, bhnd_port_type type, u_int port) { struct siba_devinfo *dinfo; /* delegate non-bus-attached devices to our parent */ if (device_get_parent(child) != dev) return (BHND_BUS_GET_REGION_COUNT(device_get_parent(dev), child, type, port)); dinfo = device_get_ivars(child); if (!siba_is_port_valid(dinfo->core_id.num_addrspace, type, port)) return (0); return (siba_addrspace_region_count(dinfo->core_id.num_addrspace, port)); } static int siba_get_port_rid(device_t dev, device_t child, bhnd_port_type port_type, u_int port_num, u_int region_num) { struct siba_devinfo *dinfo; struct siba_addrspace *addrspace; /* delegate non-bus-attached devices to our parent */ if (device_get_parent(child) != dev) return (BHND_BUS_GET_PORT_RID(device_get_parent(dev), child, port_type, port_num, region_num)); dinfo = device_get_ivars(child); addrspace = siba_find_addrspace(dinfo, port_type, port_num, region_num); if (addrspace == NULL) return (-1); return (addrspace->sa_rid); } static int siba_decode_port_rid(device_t dev, device_t child, int type, int rid, bhnd_port_type *port_type, u_int *port_num, u_int *region_num) { struct siba_devinfo *dinfo; /* delegate non-bus-attached devices to our parent */ if (device_get_parent(child) != dev) return (BHND_BUS_DECODE_PORT_RID(device_get_parent(dev), child, type, rid, port_type, port_num, region_num)); dinfo = device_get_ivars(child); /* Ports are always memory mapped */ if (type != SYS_RES_MEMORY) return (EINVAL); for (int i = 0; i < dinfo->core_id.num_addrspace; i++) { if (dinfo->addrspace[i].sa_rid != rid) continue; *port_type = BHND_PORT_DEVICE; *port_num = siba_addrspace_port(i); *region_num = siba_addrspace_region(i); return (0); } /* Not found */ return (ENOENT); } static int siba_get_region_addr(device_t dev, device_t child, bhnd_port_type port_type, u_int port_num, u_int region_num, bhnd_addr_t *addr, bhnd_size_t *size) { struct siba_devinfo *dinfo; struct siba_addrspace *addrspace; /* delegate non-bus-attached devices to our parent */ if (device_get_parent(child) != dev) { return (BHND_BUS_GET_REGION_ADDR(device_get_parent(dev), child, port_type, port_num, region_num, addr, size)); } dinfo = device_get_ivars(child); addrspace = siba_find_addrspace(dinfo, port_type, port_num, region_num); if (addrspace == NULL) return (ENOENT); *addr = addrspace->sa_base; *size = addrspace->sa_size - addrspace->sa_bus_reserved; return (0); } /** * Default siba(4) bus driver implementation of BHND_BUS_GET_INTR_COUNT(). * * This implementation consults @p child's configuration block mapping, * returning SIBA_CORE_NUM_INTR if a valid CFG0 block is mapped. */ int siba_get_intr_count(device_t dev, device_t child) { struct siba_devinfo *dinfo; /* delegate non-bus-attached devices to our parent */ if (device_get_parent(child) != dev) return (BHND_BUS_GET_INTR_COUNT(device_get_parent(dev), child)); dinfo = device_get_ivars(child); /* We can get/set interrupt sbflags on any core with a valid cfg0 * block; whether the core actually makes use of it is another matter * entirely */ if (dinfo->cfg[0] == NULL) return (0); return (SIBA_CORE_NUM_INTR); } /** * Default siba(4) bus driver implementation of BHND_BUS_GET_CORE_IVEC(). * * This implementation consults @p child's CFG0 register block, * returning the interrupt flag assigned to @p child. */ int siba_get_core_ivec(device_t dev, device_t child, u_int intr, uint32_t *ivec) { struct siba_devinfo *dinfo; uint32_t tpsflag; /* delegate non-bus-attached devices to our parent */ if (device_get_parent(child) != dev) return (BHND_BUS_GET_CORE_IVEC(device_get_parent(dev), child, intr, ivec)); /* Must be a valid interrupt ID */ if (intr >= siba_get_intr_count(dev, child)) return (ENXIO); /* Fetch sbflag number */ dinfo = device_get_ivars(child); tpsflag = bhnd_bus_read_4(dinfo->cfg[0], SIBA_CFG0_TPSFLAG); *ivec = SIBA_REG_GET(tpsflag, TPS_NUM0); return (0); } /** * Register all address space mappings for @p di. * * @param dev The siba bus device. * @param di The device info instance on which to register all address * space entries. * @param r A resource mapping the enumeration table block for @p di. */ static int siba_register_addrspaces(device_t dev, struct siba_devinfo *di, struct bhnd_resource *r) { struct siba_core_id *cid; uint32_t addr; uint32_t size; int error; cid = &di->core_id; /* Register the device address space entries */ for (uint8_t i = 0; i < di->core_id.num_addrspace; i++) { uint32_t adm; u_int adm_offset; uint32_t bus_reserved; /* Determine the register offset */ adm_offset = siba_admatch_offset(i); if (adm_offset == 0) { device_printf(dev, "addrspace %hhu is unsupported", i); return (ENODEV); } /* Fetch the address match register value */ adm = bhnd_bus_read_4(r, adm_offset); /* Parse the value */ if ((error = siba_parse_admatch(adm, &addr, &size))) { device_printf(dev, "failed to decode address " " match register value 0x%x\n", adm); return (error); } /* If this is the device's core/enumeration addrespace, * reserve the Sonics configuration register blocks for the * use of our bus. */ bus_reserved = 0; if (i == SIBA_CORE_ADDRSPACE) bus_reserved = cid->num_cfg_blocks * SIBA_CFG_SIZE; /* Append the region info */ error = siba_append_dinfo_region(di, i, addr, size, bus_reserved); if (error) return (error); } return (0); } /** * Map per-core configuration blocks for @p dinfo. * * @param dev The siba bus device. * @param dinfo The device info instance on which to map all per-core * configuration blocks. */ static int siba_map_cfg_resources(device_t dev, struct siba_devinfo *dinfo) { struct siba_addrspace *addrspace; rman_res_t r_start, r_count, r_end; uint8_t num_cfg; num_cfg = dinfo->core_id.num_cfg_blocks; if (num_cfg > SIBA_MAX_CFG) { device_printf(dev, "config block count %hhu out of range\n", num_cfg); return (ENXIO); } /* Fetch the core register address space */ addrspace = siba_find_addrspace(dinfo, BHND_PORT_DEVICE, 0, 0); if (addrspace == NULL) { device_printf(dev, "missing device registers\n"); return (ENXIO); } /* * Map the per-core configuration blocks */ for (uint8_t i = 0; i < num_cfg; i++) { /* Determine the config block's address range; configuration * blocks are allocated starting at SIBA_CFG0_OFFSET, * growing downwards. */ r_start = addrspace->sa_base + SIBA_CFG0_OFFSET; r_start -= i * SIBA_CFG_SIZE; r_count = SIBA_CFG_SIZE; r_end = r_start + r_count - 1; /* Allocate the config resource */ dinfo->cfg_rid[i] = SIBA_CFG_RID(dinfo, i); dinfo->cfg[i] = BHND_BUS_ALLOC_RESOURCE(dev, dev, SYS_RES_MEMORY, &dinfo->cfg_rid[i], r_start, r_end, r_count, RF_ACTIVE); if (dinfo->cfg[i] == NULL) { device_printf(dev, "failed to allocate SIBA_CFG%hhu\n", i); return (ENXIO); } } return (0); } - -static struct bhnd_devinfo * -siba_alloc_bhnd_dinfo(device_t dev) +static device_t +siba_add_child(device_t dev, u_int order, const char *name, int unit) { - struct siba_devinfo *dinfo = siba_alloc_dinfo(dev); - return ((struct bhnd_devinfo *)dinfo); + struct siba_devinfo *dinfo; + device_t child; + + child = device_add_child_ordered(dev, order, name, unit); + if (child == NULL) + return (NULL); + + if ((dinfo = siba_alloc_dinfo(dev)) == NULL) { + device_delete_child(dev, child); + return (NULL); + } + + device_set_ivars(child, dinfo); + + return (child); } static void -siba_free_bhnd_dinfo(device_t dev, struct bhnd_devinfo *dinfo) +siba_child_deleted(device_t dev, device_t child) { - siba_free_dinfo(dev, (struct siba_devinfo *)dinfo); + struct bhnd_softc *sc; + struct siba_devinfo *dinfo; + + sc = device_get_softc(dev); + + /* Call required bhnd(4) implementation */ + bhnd_generic_child_deleted(dev, child); + + /* Free siba device info */ + if ((dinfo = device_get_ivars(child)) != NULL) + siba_free_dinfo(dev, dinfo); + + device_set_ivars(child, NULL); } /** * Scan the core table and add all valid discovered cores to * the bus. * * @param dev The siba bus device. */ int siba_add_children(device_t dev) { const struct bhnd_chipid *chipid; struct bhnd_core_info *cores; struct siba_devinfo *dinfo; struct bhnd_resource *r; int rid; int error; dinfo = NULL; cores = NULL; r = NULL; chipid = BHND_BUS_GET_CHIPID(dev, dev); /* Allocate our temporary core table and enumerate all cores */ cores = malloc(sizeof(*cores) * chipid->ncores, M_BHND, M_NOWAIT); if (cores == NULL) return (ENOMEM); /* Add all cores. */ for (u_int i = 0; i < chipid->ncores; i++) { struct siba_core_id cid; device_t child; uint32_t idhigh, idlow; rman_res_t r_count, r_end, r_start; int nintr; /* Map the core's register block */ rid = 0; r_start = SIBA_CORE_ADDR(i); r_count = SIBA_CORE_SIZE; r_end = r_start + SIBA_CORE_SIZE - 1; r = bhnd_alloc_resource(dev, SYS_RES_MEMORY, &rid, r_start, r_end, r_count, RF_ACTIVE); if (r == NULL) { error = ENXIO; goto cleanup; } /* Add the child device */ child = BUS_ADD_CHILD(dev, 0, NULL, -1); if (child == NULL) { error = ENXIO; goto cleanup; } /* Read the core info */ idhigh = bhnd_bus_read_4(r, SB0_REG_ABS(SIBA_CFG0_IDHIGH)); idlow = bhnd_bus_read_4(r, SB0_REG_ABS(SIBA_CFG0_IDLOW)); cid = siba_parse_core_id(idhigh, idlow, i, 0); cores[i] = cid.core_info; /* Determine unit number */ for (u_int j = 0; j < i; j++) { if (cores[j].vendor == cores[i].vendor && cores[j].device == cores[i].device) cores[i].unit++; } /* Initialize per-device bus info */ if ((dinfo = device_get_ivars(child)) == NULL) { error = ENXIO; goto cleanup; } if ((error = siba_init_dinfo(dev, dinfo, &cid))) goto cleanup; /* Register the core's address space(s). */ if ((error = siba_register_addrspaces(dev, dinfo, r))) goto cleanup; /* Release our resource covering the register blocks * we're about to map */ bhnd_release_resource(dev, SYS_RES_MEMORY, rid, r); r = NULL; /* Map the core's config blocks */ if ((error = siba_map_cfg_resources(dev, dinfo))) goto cleanup; /* Assign interrupts */ nintr = bhnd_get_intr_count(child); for (int rid = 0; rid < nintr; rid++) { error = BHND_BUS_ASSIGN_INTR(dev, child, rid); if (error) { device_printf(dev, "failed to assign interrupt " "%d to core %u: %d\n", rid, i, error); } } /* If pins are floating or the hardware is otherwise * unpopulated, the device shouldn't be used. */ if (bhnd_is_hw_disabled(child)) device_disable(child); /* Issue bus callback for fully initialized child. */ BHND_BUS_CHILD_ADDED(dev, child); } cleanup: if (cores != NULL) free(cores, M_BHND); if (r != NULL) bhnd_release_resource(dev, SYS_RES_MEMORY, rid, r); return (error); } static device_method_t siba_methods[] = { /* Device interface */ DEVMETHOD(device_probe, siba_probe), DEVMETHOD(device_attach, siba_attach), DEVMETHOD(device_detach, siba_detach), DEVMETHOD(device_resume, siba_resume), DEVMETHOD(device_suspend, siba_suspend), /* Bus interface */ + DEVMETHOD(bus_add_child, siba_add_child), + DEVMETHOD(bus_child_deleted, siba_child_deleted), DEVMETHOD(bus_read_ivar, siba_read_ivar), DEVMETHOD(bus_write_ivar, siba_write_ivar), DEVMETHOD(bus_get_resource_list, siba_get_resource_list), /* BHND interface */ DEVMETHOD(bhnd_bus_get_erom_class, siba_get_erom_class), - DEVMETHOD(bhnd_bus_alloc_devinfo, siba_alloc_bhnd_dinfo), - DEVMETHOD(bhnd_bus_free_devinfo, siba_free_bhnd_dinfo), - DEVMETHOD(bhnd_bus_reset_core, siba_reset_core), - DEVMETHOD(bhnd_bus_suspend_core, siba_suspend_core), + DEVMETHOD(bhnd_bus_read_ioctl, siba_read_ioctl), + DEVMETHOD(bhnd_bus_write_ioctl, siba_write_ioctl), + DEVMETHOD(bhnd_bus_read_iost, siba_read_iost), + DEVMETHOD(bhnd_bus_is_hw_suspended, siba_is_hw_suspended), + DEVMETHOD(bhnd_bus_reset_hw, siba_reset_hw), + DEVMETHOD(bhnd_bus_suspend_hw, siba_suspend_hw), DEVMETHOD(bhnd_bus_read_config, siba_read_config), DEVMETHOD(bhnd_bus_write_config, siba_write_config), DEVMETHOD(bhnd_bus_get_port_count, siba_get_port_count), DEVMETHOD(bhnd_bus_get_region_count, siba_get_region_count), DEVMETHOD(bhnd_bus_get_port_rid, siba_get_port_rid), DEVMETHOD(bhnd_bus_decode_port_rid, siba_decode_port_rid), DEVMETHOD(bhnd_bus_get_region_addr, siba_get_region_addr), DEVMETHOD(bhnd_bus_get_intr_count, siba_get_intr_count), DEVMETHOD(bhnd_bus_get_core_ivec, siba_get_core_ivec), DEVMETHOD_END }; DEFINE_CLASS_1(bhnd, siba_driver, siba_methods, sizeof(struct siba_softc), bhnd_driver); MODULE_VERSION(siba, 1); MODULE_DEPEND(siba, bhnd, 1, 1, 1); Index: head/sys/dev/bhnd/siba/siba_subr.c =================================================================== --- head/sys/dev/bhnd/siba/siba_subr.c (revision 306286) +++ head/sys/dev/bhnd/siba/siba_subr.c (revision 306287) @@ -1,469 +1,551 @@ /*- * Copyright (c) 2015 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include "sibareg.h" #include "sibavar.h" /** * Map a siba(4) OCP vendor code to its corresponding JEDEC JEP-106 vendor * code. * * @param ocp_vendor An OCP vendor code. * @return The BHND_MFGID constant corresponding to @p ocp_vendor, or * BHND_MFGID_INVALID if the OCP vendor is unknown. */ uint16_t siba_get_bhnd_mfgid(uint16_t ocp_vendor) { switch (ocp_vendor) { case OCP_VENDOR_BCM: return (BHND_MFGID_BCM); default: return (BHND_MFGID_INVALID); } } /** * Parse the SIBA_IDH_* fields from the per-core identification * registers, returning a siba_core_id representation. * * @param idhigh The SIBA_R0_IDHIGH register. * @param idlow The SIBA_R0_IDLOW register. * @param core_id The core id (index) to include in the result. * @param unit The unit number to include in the result. */ struct siba_core_id siba_parse_core_id(uint32_t idhigh, uint32_t idlow, u_int core_idx, int unit) { uint16_t ocp_vendor; uint8_t sonics_rev; uint8_t num_addrspace; uint8_t num_cfg; ocp_vendor = SIBA_REG_GET(idhigh, IDH_VENDOR); sonics_rev = SIBA_REG_GET(idlow, IDL_SBREV); num_addrspace = SIBA_REG_GET(idlow, IDL_NRADDR) + 1 /* + enum block */; /* Determine the number of sonics config register blocks */ num_cfg = SIBA_CFG_NUM_2_2; if (sonics_rev >= SIBA_IDL_SBREV_2_3) num_cfg = SIBA_CFG_NUM_2_3; return (struct siba_core_id) { .core_info = { .vendor = siba_get_bhnd_mfgid(ocp_vendor), .device = SIBA_REG_GET(idhigh, IDH_DEVICE), .hwrev = SIBA_IDH_CORE_REV(idhigh), .core_idx = core_idx, .unit = unit }, .sonics_vendor = ocp_vendor, .sonics_rev = sonics_rev, .num_addrspace = num_addrspace, .num_cfg_blocks = num_cfg }; } /** * Allocate and return a new empty device info structure. * * @param bus The requesting bus device. * * @retval NULL if allocation failed. */ struct siba_devinfo * siba_alloc_dinfo(device_t bus) { struct siba_devinfo *dinfo; dinfo = malloc(sizeof(struct siba_devinfo), M_BHND, M_NOWAIT|M_ZERO); if (dinfo == NULL) return NULL; for (u_int i = 0; i < nitems(dinfo->cfg); i++) { dinfo->cfg[i] = NULL; dinfo->cfg_rid[i] = -1; } resource_list_init(&dinfo->resources); return dinfo; } /** * Initialize a device info structure previously allocated via * siba_alloc_dinfo, copying the provided core id. * * @param dev The requesting bus device. * @param dinfo The device info instance. * @param core Device core info. * * @retval 0 success * @retval non-zero initialization failed. */ int siba_init_dinfo(device_t dev, struct siba_devinfo *dinfo, const struct siba_core_id *core_id) { dinfo->core_id = *core_id; return (0); } /** * Map an addrspace index to its corresponding bhnd(4) port number. * * @param addrspace Address space index. */ u_int siba_addrspace_port(u_int addrspace) { /* The first addrspace is always mapped to device0; the remainder * are mapped to device1 */ if (addrspace == 0) return (0); else return (1); } /** * Map an addrspace index to its corresponding bhnd(4) region number. * * @param addrspace Address space index. */ u_int siba_addrspace_region(u_int addrspace) { /* The first addrspace is always mapped to device0.0; the remainder * are mapped to device1.0 + (n - 1) */ if (addrspace == 0) return (0); else return (addrspace - 1); } /** * Return the number of bhnd(4) ports to advertise for the given * @p num_addrspace. * * @param num_addrspace The number of siba address spaces. */ u_int siba_addrspace_port_count(u_int num_addrspace) { /* 0, 1, or 2 ports */ return min(num_addrspace, 2); } /** * Return the number of bhnd(4) regions to advertise on @p port * given the provided @p num_addrspace address space count. * * @param num_addrspace The number of core-mapped siba(4) Sonics/OCP address * spaces. */ u_int siba_addrspace_region_count(u_int num_addrspace, u_int port) { /* The first address space, if any, is mapped to device0.0 */ if (port == 0) return (min(num_addrspace, 1)); /* All remaining address spaces are mapped to device0.(n - 1) */ if (port == 1 && num_addrspace >= 2) return (num_addrspace - 1); /* No region mapping */ return (0); } /** * Return true if @p port is defined given an address space count * of @p num_addrspace, false otherwise. * * Refer to the siba_find_addrspace() function for information on siba's * mapping of bhnd(4) port and region identifiers. * * @param num_addrspace The number of address spaces to verify the port against. * @param type The bhnd(4) port type. * @param port The bhnd(4) port number. */ bool siba_is_port_valid(u_int num_addrspace, bhnd_port_type type, u_int port) { /* Only device ports are supported */ if (type != BHND_PORT_DEVICE) return (false); /* Verify the index against the port count */ if (siba_addrspace_port_count(num_addrspace) <= port) return (false); return (true); } /** * Map a bhnd(4) type/port/region triplet to its associated address space * index, if any. * * For compatibility with bcma(4), we map address spaces to port/region * identifiers as follows: * * [port] [addrspace] * device0.0 0 * device1.0 1 * device1.1 2 * device1.2 3 * * The only supported port type is BHND_PORT_DEVICE. * * @param num_addrspace The number of available siba address spaces. * @param type The bhnd(4) port type. * @param port The bhnd(4) port number. * @param region The bhnd(4) port region. * @param addridx On success, the corresponding addrspace index. * * @retval 0 success * @retval ENOENT if the given type/port/region cannot be mapped to a * siba address space. */ int siba_addrspace_index(u_int num_addrspace, bhnd_port_type type, u_int port, u_int region, u_int *addridx) { u_int idx; if (!siba_is_port_valid(num_addrspace, type, port)) return (ENOENT); if (port == 0) idx = region; else if (port == 1) idx = region + 1; else return (ENOENT); if (idx >= num_addrspace) return (ENOENT); /* Found */ *addridx = idx; return (0); } /** * Map an bhnd(4) type/port/region triplet to its associated address space * entry, if any. * * The only supported port type is BHND_PORT_DEVICE. * * @param dinfo The device info to search for a matching address space. * @param type The bhnd(4) port type. * @param port The bhnd(4) port number. * @param region The bhnd(4) port region. */ struct siba_addrspace * siba_find_addrspace(struct siba_devinfo *dinfo, bhnd_port_type type, u_int port, u_int region) { u_int addridx; int error; /* Map to addrspace index */ error = siba_addrspace_index(dinfo->core_id.num_addrspace, type, port, region, &addridx); if (error) return (NULL); /* Found */ if (addridx >= SIBA_MAX_ADDRSPACE) return (NULL); return (&dinfo->addrspace[addridx]); } /** * Append an address space entry to @p dinfo. * * @param dinfo The device info entry to update. * @param addridx The address space index. * @param base The mapping's base address. * @param size The mapping size. * @param bus_reserved Number of bytes to reserve in @p size for bus use * when registering the resource list entry. This is used to reserve bus * access to the core's SIBA_CFG* register blocks. * * @retval 0 success * @retval non-zero An error occurred appending the entry. */ int siba_append_dinfo_region(struct siba_devinfo *dinfo, uint8_t addridx, uint32_t base, uint32_t size, uint32_t bus_reserved) { struct siba_addrspace *sa; rman_res_t r_size; /* Verify that base + size will not overflow */ if (size > 0 && UINT32_MAX - (size - 1) < base) return (ERANGE); /* Verify that size - bus_reserved will not underflow */ if (size < bus_reserved) return (ERANGE); /* Must not be 0-length */ if (size == 0) return (EINVAL); /* Must not exceed addrspace array size */ if (addridx >= nitems(dinfo->addrspace)) return (EINVAL); /* Initialize new addrspace entry */ sa = &dinfo->addrspace[addridx]; sa->sa_base = base; sa->sa_size = size; sa->sa_bus_reserved = bus_reserved; /* Populate the resource list */ r_size = size - bus_reserved; sa->sa_rid = resource_list_add_next(&dinfo->resources, SYS_RES_MEMORY, base, base + (r_size - 1), r_size); return (0); } /** * Deallocate the given device info structure and any associated resources. * * @param dev The requesting bus device. * @param dinfo Device info to be deallocated. */ void siba_free_dinfo(device_t dev, struct siba_devinfo *dinfo) { resource_list_free(&dinfo->resources); /* Free all mapped configuration blocks */ for (u_int i = 0; i < nitems(dinfo->cfg); i++) { if (dinfo->cfg[i] == NULL) continue; bhnd_release_resource(dev, SYS_RES_MEMORY, dinfo->cfg_rid[i], dinfo->cfg[i]); dinfo->cfg[i] = NULL; dinfo->cfg_rid[i] = -1; } free(dinfo, M_BHND); } /** * Return the core-enumeration-relative offset for the @p addrspace * SIBA_R0_ADMATCH* register. * * @param addrspace The address space index. * * @retval non-zero success * @retval 0 the given @p addrspace index is not supported. */ u_int siba_admatch_offset(uint8_t addrspace) { switch (addrspace) { case 0: return SB0_REG_ABS(SIBA_CFG0_ADMATCH0); case 1: return SB0_REG_ABS(SIBA_CFG0_ADMATCH1); case 2: return SB0_REG_ABS(SIBA_CFG0_ADMATCH2); case 3: return SB0_REG_ABS(SIBA_CFG0_ADMATCH3); default: return (0); } } /** * Parse a SIBA_R0_ADMATCH* register. * * @param addrspace The address space index. * @param am The address match register value to be parsed. * @param[out] addr The parsed address. * @param[out] size The parsed size. * * @retval 0 success * @retval non-zero a parse error occurred. */ int siba_parse_admatch(uint32_t am, uint32_t *addr, uint32_t *size) { u_int am_type; /* Negative encoding is not supported. This is not used on any * currently known devices*/ if (am & SIBA_AM_ADNEG) return (EINVAL); /* Extract the base address and size */ am_type = SIBA_REG_GET(am, AM_TYPE); switch (am_type) { case 0: *addr = am & SIBA_AM_BASE0_MASK; *size = 1 << (SIBA_REG_GET(am, AM_ADINT0) + 1); break; case 1: *addr = am & SIBA_AM_BASE1_MASK; *size = 1 << (SIBA_REG_GET(am, AM_ADINT1) + 1); break; case 2: *addr = am & SIBA_AM_BASE2_MASK; *size = 1 << (SIBA_REG_GET(am, AM_ADINT2) + 1); break; default: return (EINVAL); } return (0); } + +/** + * Write @p value to @p dev's CFG0 target/initiator state register and + * wait for completion. + * + * @param dev The siba(4) child device. + * @param reg The state register to write (e.g. SIBA_CFG0_TMSTATELOW, + * SIBA_CFG0_IMSTATE) + * @param value The value to write to @p reg. + * @param mask The mask of bits to be included from @p value. + * + * @retval 0 success. + * @retval ENODEV if SIBA_CFG0 is not mapped by @p dinfo. + * @retval ETIMEDOUT if a timeout occurs prior to SIBA_TMH_BUSY clearing. + */ +int +siba_write_target_state(device_t dev, struct siba_devinfo *dinfo, + bus_size_t reg, uint32_t value, uint32_t mask) +{ + struct bhnd_resource *r; + uint32_t rval; + + /* Must have a CFG0 block */ + if ((r = dinfo->cfg[0]) == NULL) + return (ENODEV); + + /* Verify the register offset falls within CFG register block */ + if (reg > SIBA_CFG_SIZE-4) + return (EFAULT); + + for (int i = 0; i < 300; i += 10) { + rval = bhnd_bus_read_4(r, reg); + rval &= ~mask; + rval |= (value & mask); + + bhnd_bus_write_4(r, reg, rval); + bhnd_bus_read_4(r, reg); /* read-back */ + DELAY(1); + + /* If the write has completed, wait for target busy state + * to clear */ + rval = bhnd_bus_read_4(r, reg); + if ((rval & mask) == (value & mask)) + return (siba_wait_target_busy(dev, dinfo, 100000)); + + DELAY(10); + } + + return (ETIMEDOUT); +} + +/** + * Spin for up to @p usec waiting for SIBA_TMH_BUSY to clear in + * @p dev's SIBA_CFG0_TMSTATEHIGH register. + * + * @param dev The siba(4) child device to wait on. + * @param dinfo The @p dev's device info + * + * @retval 0 if SIBA_TMH_BUSY is cleared prior to the @p usec timeout. + * @retval ENODEV if SIBA_CFG0 is not mapped by @p dinfo. + * @retval ETIMEDOUT if a timeout occurs prior to SIBA_TMH_BUSY clearing. + */ +int +siba_wait_target_busy(device_t dev, struct siba_devinfo *dinfo, int usec) +{ + struct bhnd_resource *r; + uint32_t ts_high; + + if ((r = dinfo->cfg[0]) == NULL) + return (ENODEV); + + for (int i = 0; i < usec; i += 10) { + ts_high = bhnd_bus_read_4(r, SIBA_CFG0_TMSTATEHIGH); + if (!(ts_high & SIBA_TMH_BUSY)) + return (0); + + DELAY(10); + } + + device_printf(dev, "SIBA_TMH_BUSY wait timeout\n"); + return (ETIMEDOUT); +} Index: head/sys/dev/bhnd/siba/sibareg.h =================================================================== --- head/sys/dev/bhnd/siba/sibareg.h (revision 306286) +++ head/sys/dev/bhnd/siba/sibareg.h (revision 306287) @@ -1,267 +1,267 @@ /*- * Copyright (c) 2015 Landon Fuller * Copyright (c) 2010 Broadcom Corporation * * This file was derived from the sbconfig.h header distributed with * Broadcom's initial brcm80211 Linux driver release, as * contributed to the Linux staging repository. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ #ifndef _BHND_SIBA_SIBAREG_ #define _BHND_SIBA_SIBAREG_ #include /* * Broadcom SIBA Configuration Space Registers. * * Backplane configuration registers common to siba(4) core register * blocks. */ /** * Extract a config attribute by applying _MASK and _SHIFT defines. * * @param _reg The register value containing the desired attribute * @param _attr The BCMA EROM attribute name (e.g. ENTRY_ISVALID), to be * concatenated with the `SB` prefix and `_MASK`/`_SHIFT` suffixes. */ #define SIBA_REG_GET(_entry, _attr) \ ((_entry & SIBA_ ## _attr ## _MASK) \ >> SIBA_ ## _attr ## _SHIFT) #define SIBA_ENUM_ADDR BHND_DEFAULT_CHIPC_ADDR /**< enumeration space */ #define SIBA_ENUM_SIZE 0x00100000 /**< size of the enumeration space */ #define SIBA_CORE_SIZE BHND_DEFAULT_CORE_SIZE /**< per-core register block size */ #define SIBA_CORE_NUM_INTR 1 /**< number of per-core interrupt lines */ #define SIBA_MAX_CORES \ (SIBA_ENUM_SIZE/SIBA_CORE_SIZE) /**< Maximum number of cores */ /** Evaluates to the bus address offset of the @p idx core register block */ #define SIBA_CORE_OFFSET(idx) ((idx) * SIBA_CORE_SIZE) /** Evaluates to the bus address of the @p idx core register block */ #define SIBA_CORE_ADDR(idx) (SIBA_ENUM_ADDR + SIBA_CORE_OFFSET(idx)) /* * Sonics configuration registers are mapped to each core's enumeration * space, at the end of the 4kb device register block, in reverse * order: * * [0x0000-0x0dff] core registers * [0x0e00-0x0eff] SIBA_R1 registers (sonics >= 2.3) * [0x0f00-0x0fff] SIBA_R0 registers */ #define SIBA_CFG0_OFFSET 0xf00 /**< first configuration block */ #define SIBA_CFG1_OFFSET 0xe00 /**< second configuration block (sonics >= 2.3) */ #define SIBA_CFG_SIZE 0x100 /**< cfg register block size */ /* Return the SIBA_CORE_ADDR-relative offset for a SIBA_CFG* register. */ #define SB0_REG_ABS(off) ((off) + SIBA_CFG0_OFFSET) #define SB1_REG_ABS(off) ((off) + SIBA_CFG1_OFFSET) /* SIBA_CFG0 registers */ #define SIBA_CFG0_IPSFLAG 0x08 /**< initiator port ocp slave flag */ #define SIBA_CFG0_TPSFLAG 0x18 /**< target port ocp slave flag */ #define SIBA_CFG0_TMERRLOGA 0x48 /**< sonics >= 2.3 */ #define SIBA_CFG0_TMERRLOG 0x50 /**< sonics >= 2.3 */ #define SIBA_CFG0_ADMATCH3 0x60 /**< address match3 */ #define SIBA_CFG0_ADMATCH2 0x68 /**< address match2 */ #define SIBA_CFG0_ADMATCH1 0x70 /**< address match1 */ #define SIBA_CFG0_IMSTATE 0x90 /**< initiator agent state */ #define SIBA_CFG0_INTVEC 0x94 /**< interrupt mask */ #define SIBA_CFG0_TMSTATELOW 0x98 /**< target state */ #define SIBA_CFG0_TMSTATEHIGH 0x9c /**< target state */ #define SIBA_CFG0_BWA0 0xa0 /**< bandwidth allocation table0 */ #define SIBA_CFG0_IMCONFIGLOW 0xa8 /**< initiator configuration */ #define SIBA_CFG0_IMCONFIGHIGH 0xac /**< initiator configuration */ #define SIBA_CFG0_ADMATCH0 0xb0 /**< address match0 */ #define SIBA_CFG0_TMCONFIGLOW 0xb8 /**< target configuration */ #define SIBA_CFG0_TMCONFIGHIGH 0xbc /**< target configuration */ #define SIBA_CFG0_BCONFIG 0xc0 /**< broadcast configuration */ #define SIBA_CFG0_BSTATE 0xc8 /**< broadcast state */ #define SIBA_CFG0_ACTCNFG 0xd8 /**< activate configuration */ #define SIBA_CFG0_FLAGST 0xe8 /**< current sbflags */ #define SIBA_CFG0_IDLOW 0xf8 /**< identification */ #define SIBA_CFG0_IDHIGH 0xfc /**< identification */ /* SIBA_CFG1 registers (sonics >= 2.3) */ #define SIBA_CFG1_IMERRLOGA 0xa8 /**< (sonics >= 2.3) */ #define SIBA_CFG1_IMERRLOG 0xb0 /**< sbtmerrlog (sonics >= 2.3) */ #define SIBA_CFG1_TMPORTCONNID0 0xd8 /**< sonics >= 2.3 */ #define SIBA_CFG1_TMPORTLOCK0 0xf8 /**< sonics >= 2.3 */ /* sbipsflag */ #define SIBA_IPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */ #define SIBA_IPS_INT1_SHIFT 0 #define SIBA_IPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */ #define SIBA_IPS_INT2_SHIFT 8 #define SIBA_IPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */ #define SIBA_IPS_INT3_SHIFT 16 #define SIBA_IPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */ #define SIBA_IPS_INT4_SHIFT 24 /* sbtpsflag */ #define SIBA_TPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */ #define SIBA_TPS_NUM0_SHIFT 0 #define SIBA_TPS_F0EN0 0x40 /* interrupt is always sent on the backplane */ /* sbtmerrlog */ #define SIBA_TMEL_CM 0x00000007 /* command */ #define SIBA_TMEL_CI 0x0000ff00 /* connection id */ #define SIBA_TMEL_EC 0x0f000000 /* error code */ #define SIBA_TMEL_ME 0x80000000 /* multiple error */ /* sbimstate */ #define SIBA_IM_PC 0xf /* pipecount */ #define SIBA_IM_AP_MASK 0x30 /* arbitration policy */ #define SIBA_IM_AP_BOTH 0x00 /* use both timeslaces and token */ #define SIBA_IM_AP_TS 0x10 /* use timesliaces only */ #define SIBA_IM_AP_TK 0x20 /* use token only */ #define SIBA_IM_AP_RSV 0x30 /* reserved */ #define SIBA_IM_IBE 0x20000 /* inbanderror */ #define SIBA_IM_TO 0x40000 /* timeout */ #define SIBA_IM_BY 0x01800000 /* busy (sonics >= 2.3) */ #define SIBA_IM_RJ 0x02000000 /* reject (sonics >= 2.3) */ /* sbtmstatelow */ #define SIBA_TML_RESET 0x0001 /* reset */ #define SIBA_TML_REJ_MASK 0x0006 /* reject field */ #define SIBA_TML_REJ 0x0002 /* reject */ #define SIBA_TML_TMPREJ 0x0004 /* temporary reject, for error recovery */ +#define SIBA_TML_SICF_MASK 0xFFFF0000 /* core IOCTL flags */ +#define SIBA_TML_SICF_SHIFT 16 -#define SIBA_TML_SICF_SHIFT 16 /* Shift to locate the SI control flags in sbtml */ - /* sbtmstatehigh */ #define SIBA_TMH_SERR 0x0001 /* serror */ #define SIBA_TMH_INT 0x0002 /* interrupt */ #define SIBA_TMH_BUSY 0x0004 /* busy */ #define SIBA_TMH_TO 0x0020 /* timeout (sonics >= 2.3) */ - -#define SIBA_TMH_SISF_SHIFT 16 /* Shift to locate the SI status flags in sbtmh */ +#define SIBA_TMH_SISF_MASK 0xFFFF0000 /* core IOST flags */ +#define SIBA_TMH_SISF_SHIFT 16 /* sbbwa0 */ #define SIBA_BWA_TAB0_MASK 0xffff /* lookup table 0 */ #define SIBA_BWA_TAB1_MASK 0xffff /* lookup table 1 */ #define SIBA_BWA_TAB1_SHIFT 16 /* sbimconfiglow */ #define SIBA_IMCL_STO_MASK 0x7 /* service timeout */ #define SIBA_IMCL_RTO_MASK 0x70 /* request timeout */ #define SIBA_IMCL_RTO_SHIFT 4 #define SIBA_IMCL_CID_MASK 0xff0000 /* connection id */ #define SIBA_IMCL_CID_SHIFT 16 /* sbimconfighigh */ #define SIBA_IMCH_IEM_MASK 0xc /* inband error mode */ #define SIBA_IMCH_TEM_MASK 0x30 /* timeout error mode */ #define SIBA_IMCH_TEM_SHIFT 4 #define SIBA_IMCH_BEM_MASK 0xc0 /* bus error mode */ #define SIBA_IMCH_BEM_SHIFT 6 /* sbadmatch0-4 */ #define SIBA_AM_TYPE_MASK 0x3 /* address type */ #define SIBA_AM_TYPE_SHIFT 0x0 #define SIBA_AM_AD64 0x4 /* reserved */ #define SIBA_AM_ADINT0_MASK 0xf8 /* type0 size */ #define SIBA_AM_ADINT0_SHIFT 3 #define SIBA_AM_ADINT1_MASK 0x1f8 /* type1 size */ #define SIBA_AM_ADINT1_SHIFT 3 #define SIBA_AM_ADINT2_MASK 0x1f8 /* type2 size */ #define SIBA_AM_ADINT2_SHIFT 3 #define SIBA_AM_ADEN 0x400 /* enable */ #define SIBA_AM_ADNEG 0x800 /* negative decode */ #define SIBA_AM_BASE0_MASK 0xffffff00 /* type0 base address */ #define SIBA_AM_BASE0_SHIFT 8 #define SIBA_AM_BASE1_MASK 0xfffff000 /* type1 base address for the core */ #define SIBA_AM_BASE1_SHIFT 12 #define SIBA_AM_BASE2_MASK 0xffff0000 /* type2 base address for the core */ #define SIBA_AM_BASE2_SHIFT 16 /* sbtmconfiglow */ #define SIBA_TMCL_CD_MASK 0xff /* clock divide */ #define SIBA_TMCL_CO_MASK 0xf800 /* clock offset */ #define SIBA_TMCL_CO_SHIFT 11 #define SIBA_TMCL_IF_MASK 0xfc0000 /* interrupt flags */ #define SIBA_TMCL_IF_SHIFT 18 #define SIBA_TMCL_IM_MASK 0x3000000 /* interrupt mode */ #define SIBA_TMCL_IM_SHIFT 24 /* sbtmconfighigh */ #define SIBA_TMCH_BM_MASK 0x3 /* busy mode */ #define SIBA_TMCH_RM_MASK 0x3 /* retry mode */ #define SIBA_TMCH_RM_SHIFT 2 #define SIBA_TMCH_SM_MASK 0x30 /* stop mode */ #define SIBA_TMCH_SM_SHIFT 4 #define SIBA_TMCH_EM_MASK 0x300 /* sb error mode */ #define SIBA_TMCH_EM_SHIFT 8 #define SIBA_TMCH_IM_MASK 0xc00 /* int mode */ #define SIBA_TMCH_IM_SHIFT 10 /* sbbconfig */ #define SIBA_BC_LAT_MASK 0x3 /* sb latency */ #define SIBA_BC_MAX0_MASK 0xf0000 /* maxccntr0 */ #define SIBA_BC_MAX0_SHIFT 16 #define SIBA_BC_MAX1_MASK 0xf00000 /* maxccntr1 */ #define SIBA_BC_MAX1_SHIFT 20 /* sbbstate */ #define SIBA_BS_SRD 0x1 /* st reg disable */ #define SIBA_BS_HRD 0x2 /* hold reg disable */ /* sbidlow */ #define SIBA_IDL_CS_MASK 0x3 /* config space */ #define SIBA_IDL_CS_SHIFT 0 #define SIBA_IDL_NRADDR_MASK 0x38 /* # address ranges supported */ #define SIBA_IDL_NRADDR_SHIFT 3 #define SIBA_IDL_SYNCH 0x40 /* sync */ #define SIBA_IDL_INIT 0x80 /* initiator */ #define SIBA_IDL_MINLAT_MASK 0xf00 /* minimum backplane latency */ #define SIBA_IDL_MINLAT_SHIFT 8 #define SIBA_IDL_MAXLAT_MASK 0xf000 /* maximum backplane latency */ #define SIBA_IDL_MAXLAT_SHIFT 12 #define SIBA_IDL_FIRST_MASK 0x10000 /* this initiator is first */ #define SIBA_IDL_FIRST_SHIFT 16 #define SIBA_IDL_CW_MASK 0xc0000 /* cycle counter width */ #define SIBA_IDL_CW_SHIFT 18 #define SIBA_IDL_TP_MASK 0xf00000 /* target ports */ #define SIBA_IDL_TP_SHIFT 20 #define SIBA_IDL_IP_MASK 0xf000000 /* initiator ports */ #define SIBA_IDL_IP_SHIFT 24 #define SIBA_IDL_SBREV_MASK 0xf0000000 /* sonics backplane revision code */ #define SIBA_IDL_SBREV_SHIFT 28 #define SIBA_IDL_SBREV_2_2 0x0 /* version 2.2 or earlier */ #define SIBA_IDL_SBREV_2_3 0x1 /* version 2.3 */ /* sbidhigh */ #define SIBA_IDH_RC_MASK 0x000f /* revision code */ #define SIBA_IDH_RCE_MASK 0x7000 /* revision code extension field */ #define SIBA_IDH_RCE_SHIFT 8 #define SIBA_IDH_DEVICE_MASK 0x8ff0 /* core code */ #define SIBA_IDH_DEVICE_SHIFT 4 #define SIBA_IDH_VENDOR_MASK 0xffff0000 /* vendor code */ #define SIBA_IDH_VENDOR_SHIFT 16 #define SIBA_IDH_CORE_REV(sbidh) \ (SIBA_REG_GET((sbidh), IDH_RCE) | ((sbidh) & SIBA_IDH_RC_MASK)) #define SIBA_COMMIT 0xfd8 /* update buffered registers value */ #endif /* _BHND_SIBA_SIBAREG_ */ Index: head/sys/dev/bhnd/siba/sibavar.h =================================================================== --- head/sys/dev/bhnd/siba/sibavar.h (revision 306286) +++ head/sys/dev/bhnd/siba/sibavar.h (revision 306287) @@ -1,167 +1,172 @@ /*- * Copyright (c) 2015 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. * * $FreeBSD$ */ #ifndef _SIBA_SIBAVAR_H_ #define _SIBA_SIBAVAR_H_ #include #include #include #include #include #include "siba.h" /* * Internal definitions shared by siba(4) driver implementations. */ struct siba_addrspace; struct siba_devinfo; struct siba_core_id; int siba_probe(device_t dev); int siba_attach(device_t dev); int siba_detach(device_t dev); int siba_resume(device_t dev); int siba_suspend(device_t dev); int siba_get_intr_count(device_t dev, device_t child); int siba_get_core_ivec(device_t dev, device_t child, u_int intr, uint32_t *ivec); uint16_t siba_get_bhnd_mfgid(uint16_t ocp_vendor); struct siba_core_id siba_parse_core_id(uint32_t idhigh, uint32_t idlow, u_int core_idx, int unit); int siba_add_children(device_t bus); struct siba_devinfo *siba_alloc_dinfo(device_t dev); int siba_init_dinfo(device_t dev, struct siba_devinfo *dinfo, const struct siba_core_id *core_id); void siba_free_dinfo(device_t dev, struct siba_devinfo *dinfo); u_int siba_addrspace_port_count(u_int num_addrspace); u_int siba_addrspace_region_count(u_int num_addrspace, u_int port); u_int siba_addrspace_port(u_int addrspace); u_int siba_addrspace_region(u_int addrspace); int siba_addrspace_index(u_int num_addrspace, bhnd_port_type type, u_int port, u_int region, u_int *addridx); bool siba_is_port_valid(u_int num_addrspace, bhnd_port_type type, u_int port); struct siba_addrspace *siba_find_addrspace(struct siba_devinfo *dinfo, bhnd_port_type type, u_int port, u_int region); int siba_append_dinfo_region(struct siba_devinfo *dinfo, uint8_t sid, uint32_t base, uint32_t size, uint32_t bus_reserved); u_int siba_admatch_offset(uint8_t addrspace); int siba_parse_admatch(uint32_t am, uint32_t *addr, uint32_t *size); +int siba_write_target_state(device_t dev, + struct siba_devinfo *dinfo, bus_size_t reg, + uint32_t value, uint32_t mask); +int siba_wait_target_busy(device_t child, + struct siba_devinfo *dinfo, int usec); + /* Sonics configuration register blocks */ #define SIBA_CFG_NUM_2_2 1 /**< sonics <= 2.2 maps SIBA_CFG0. */ #define SIBA_CFG_NUM_2_3 2 /**< sonics <= 2.3 maps SIBA_CFG0 and SIBA_CFG1 */ #define SIBA_MAX_CFG SIBA_CFG_NUM_2_3 /**< maximum number of supported config register blocks */ #define SIBA_CFG_RID_BASE 100 /**< base resource ID for SIBA_CFG* register allocations */ #define SIBA_CFG_RID(_dinfo, _cfg) \ (SIBA_CFG_RID_BASE + (_cfg) + \ (_dinfo->core_id.core_info.core_idx * SIBA_MAX_CFG)) /* Sonics/OCP address space mappings */ #define SIBA_CORE_ADDRSPACE 0 /**< Address space mapping the primary device registers */ #define SIBA_MAX_ADDRSPACE 4 /**< Maximum number of Sonics/OCP * address space mappings for a * single core. */ /* bhnd(4) (port,region) representation of siba address space mappings */ #define SIBA_MAX_PORT 2 /**< maximum number of advertised * bhnd(4) ports */ /** siba(4) address space descriptor */ struct siba_addrspace { uint32_t sa_base; /**< base address */ uint32_t sa_size; /**< size */ int sa_rid; /**< bus resource id */ uint32_t sa_bus_reserved;/**< number of bytes at high end of * address space reserved for the bus */ }; /** * siba(4) per-core identification info. */ struct siba_core_id { struct bhnd_core_info core_info; /**< standard bhnd(4) core info */ uint16_t sonics_vendor; /**< OCP vendor identifier used to generate * the JEDEC-106 bhnd(4) vendor identifier. */ uint8_t sonics_rev; /**< sonics backplane revision code */ uint8_t num_addrspace; /**< number of address ranges mapped to this core. */ uint8_t num_cfg_blocks; /**< number of Sonics configuration register blocks mapped to the core's enumeration space */ }; /** * siba(4) per-device info */ struct siba_devinfo { - struct bhnd_devinfo bhnd_dinfo; /**< superclass device info. */ + struct resource_list resources; /**< per-core memory regions. */ + struct siba_core_id core_id; /**< core identification info */ + struct siba_addrspace addrspace[SIBA_MAX_ADDRSPACE]; /**< memory map descriptors */ - struct resource_list resources; /**< per-core memory regions. */ - struct siba_core_id core_id; /**< core identification info */ - struct siba_addrspace addrspace[SIBA_MAX_ADDRSPACE]; /**< memory map descriptors */ - - struct bhnd_resource *cfg[SIBA_MAX_CFG]; /**< SIBA_CFG_* registers */ - int cfg_rid[SIBA_MAX_CFG]; /**< SIBA_CFG_* resource IDs */ + struct bhnd_resource *cfg[SIBA_MAX_CFG]; /**< SIBA_CFG_* registers */ + int cfg_rid[SIBA_MAX_CFG]; /**< SIBA_CFG_* resource IDs */ + struct bhnd_core_pmu_info *pmu_info; /**< Bus-managed PMU state, or NULL */ }; /** siba(4) per-instance state */ struct siba_softc { struct bhnd_softc bhnd_sc; /**< bhnd state */ device_t dev; /**< siba device */ }; #endif /* _SIBA_SIBAVAR_H_ */ Index: head/sys/modules/bhnd/bcma/Makefile =================================================================== --- head/sys/modules/bhnd/bcma/Makefile (revision 306286) +++ head/sys/modules/bhnd/bcma/Makefile (revision 306287) @@ -1,11 +1,11 @@ # $FreeBSD$ .PATH: ${.CURDIR}/../../../dev/bhnd/bcma KMOD= bcma SRCS= bcma.c bcma_subr.c bcma_erom.c SRCS+= device_if.h bus_if.h -SRCS+= bhnd_bus_if.h bhnd_erom_if.h +SRCS+= bhnd_bus_if.h bhnd_erom_if.h bhnd_pmu_if.h .include Index: head/sys/modules/bhnd/siba/Makefile =================================================================== --- head/sys/modules/bhnd/siba/Makefile (revision 306286) +++ head/sys/modules/bhnd/siba/Makefile (revision 306287) @@ -1,12 +1,12 @@ # $FreeBSD$ .PATH: ${.CURDIR}/../../../dev/bhnd/siba KMOD= siba SRCS= siba.c siba_subr.c \ siba_erom.c SRCS+= device_if.h bus_if.h -SRCS+= bhnd_bus_if.h bhnd_erom_if.h +SRCS+= bhnd_bus_if.h bhnd_erom_if.h bhnd_pmu_if.h .include