Index: head/share/man/man4/intpm.4 =================================================================== --- head/share/man/man4/intpm.4 (revision 306217) +++ head/share/man/man4/intpm.4 (revision 306218) @@ -1,84 +1,86 @@ .\" Copyright (c) 1999 Takanori Watanabe .\" All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" -.Dd July 20, 2016 +.Dd September 22, 2016 .Dt INTPM 4 .Os .Sh NAME .Nm intpm .Nd Intel PIIX4 Power Management controller driver .Sh SYNOPSIS .Cd device pci .Cd device smbus .Cd device smb .Cd device intpm .Sh DESCRIPTION The .Nm driver provides access to .Tn Intel PIIX4 compatible Power Management controllers. Currently, only .Xr smbus 4 controller function is implemented. .Sh HARDWARE The .Nm driver supports the following chipsets: .Pp .Bl -bullet -compact .It Intel 82371AB/82443MX .It ATI IXP400 .It AMD SB600/7x0/8x0/9x0 southbridges .It AMD Axx/Hudson/Bolton FCHs .It -AMD FCH integrated into Family 16h Models 00h-0Fh Processors +AMD FCH integrated into Family 15h Models 60h-6Fh, 70h-7Fh Processors +.It +AMD FCH integrated into Family 16h Models 00h-0Fh, 30h-3Fh Processors .El .Sh SEE ALSO .Xr amdpm 4 , .Xr amdsmb 4 , .Xr ichsmb 4 , .Xr smb 4 , .Xr smbus 4 .Sh HISTORY The .Nm driver first appeared in .Fx 3.4 . .Sh AUTHORS This manual page was written by .An Takanori Watanabe Aq Mt takawata@shidahara1.planet.sci.kobe-u.ac.jp . .Sh BUGS This device requires IRQ 9 exclusively. To use this, you should enable ACPI function in BIOS configuration, or PnP mechanism assigns conflicted IRQ for PnP ISA card. And do not use IRQ 9 for Non-PnP ISA cards. Index: head/sys/dev/amdsbwd/amd_chipset.h =================================================================== --- head/sys/dev/amdsbwd/amd_chipset.h (nonexistent) +++ head/sys/dev/amdsbwd/amd_chipset.h (revision 306218) @@ -0,0 +1,139 @@ +/*- + * Copyright (c) 2016 Andriy Gapon + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * The following registers, bits and magic values are defined in Register + * Reference Guide documents for SB600, SB7x0, SB8x0, SB9x0 southbridges and + * various versions of Fusion Controller Hubs (FCHs). FCHs integrated into + * CPUs are documented in BIOS and Kernel Development Guide documents for + * the corresponding processor families. + * + * At present there are three classes of supported chipsets: + * - SB600 and S7x0 southbridges where the SMBus controller device has + * a PCI Device ID of 0x43851002 and a revision less than 0x40 + * - SB8x0, SB9x0 southbridges and FCHs where the SMBus controller device has + * a PCI Device ID of 0x43851002 and a revision greater than or equal to 0x40 + * or the controller has an ID of 0x780b1022 and a revision less than 0x41 + * - FCHs where the SMBus controller device has a PCI Device ID of 0x780b1022 + * and a revision greater than or equal to 0x41 + * The register definitions are compatible within the classes and may be + * incompatible accross them. + * So far there is no public documentation for "KERNCZ" FCH where the SMBus + * controller has a PCI ID of 0x790b1022. Based on some code in Linux it is + * assumed that revisions less than 0x49 are compatible with the SB8x0 class + * and revisions greater than or equal to 0x49 are compatible with the class + * of FCHs with 0x41+ revisions. + */ + +/* + * IO registers for accessing the PMIO space. + * See SB7xx RRG 2.3.3.1.1, for instance. + */ +#define AMDSB_PMIO_INDEX 0xcd6 +#define AMDSB_PMIO_DATA (PMIO_INDEX + 1) +#define AMDSB_PMIO_WIDTH 2 + +/* + * SB7x0 and compatible registers in the PMIO space. + * See SB7xx RRG 2.3.3.2. + */ +#define AMDSB_PM_RESET_STATUS0 0x44 +#define AMDSB_PM_RESET_STATUS1 0x45 +#define AMDSB_WD_RST_STS 0x02 +#define AMDSB_PM_WDT_CTRL 0x69 +#define AMDSB_WDT_DISABLE 0x01 +#define AMDSB_WDT_RES_MASK (0x02 | 0x04) +#define AMDSB_WDT_RES_32US 0x00 +#define AMDSB_WDT_RES_10MS 0x02 +#define AMDSB_WDT_RES_100MS 0x04 +#define AMDSB_WDT_RES_1S 0x06 +#define AMDSB_PM_WDT_BASE_LSB 0x6c +#define AMDSB_PM_WDT_BASE_MSB 0x6f + +/* + * SB8x0 and compatible registers in the PMIO space. + * See SB8xx RRG 2.3.3, for instance. + */ +#define AMDSB8_PM_SMBUS_EN 0x2c +#define AMDSB8_SMBUS_EN 0x01 +#define AMDSB8_SMBUS_ADDR_MASK 0xffe0u +#define AMDSB8_PM_WDT_EN 0x48 +#define AMDSB8_WDT_DEC_EN 0x01 +#define AMDSB8_WDT_DISABLE 0x02 +#define AMDSB8_PM_WDT_CTRL 0x4c +#define AMDSB8_WDT_32KHZ 0x00 +#define AMDSB8_WDT_1HZ 0x03 +#define AMDSB8_WDT_RES_MASK 0x03 +#define AMDSB8_PM_RESET_STATUS0 0xc0 +#define AMDSB8_PM_RESET_STATUS1 0xc1 +#define AMDSB8_WD_RST_STS 0x20 + +/* + * Newer FCH registers in the PMIO space. + * See BKDG for Family 16h Models 30h-3Fh 3.26.13 PMx00 and PMx04. + */ +#define AMDFCH41_PM_DECODE_EN0 0x00 +#define AMDFCH41_SMBUS_EN 0x10 +#define AMDFCH41_WDT_EN 0x80 +#define AMDFCH41_PM_DECODE_EN1 0x01 +#define AMDFCH41_PM_DECODE_EN3 0x03 +#define AMDFCH41_WDT_RES_MASK 0x03 +#define AMDFCH41_WDT_RES_32US 0x00 +#define AMDFCH41_WDT_RES_10MS 0x01 +#define AMDFCH41_WDT_RES_100MS 0x02 +#define AMDFCH41_WDT_RES_1S 0x03 +#define AMDFCH41_WDT_EN_MASK 0x0c +#define AMDFCH41_WDT_ENABLE 0x00 +#define AMDFCH41_PM_ISA_CTRL 0x04 +#define AMDFCH41_MMIO_EN 0x02 + +/* + * Fixed MMIO addresses for accessing Watchdog and SMBus registers. + * See BKDG for Family 16h Models 30h-3Fh 3.26.13 PMx00 and PMx04. + */ +#define AMDFCH41_WDT_FIXED_ADDR 0xfeb00000u +#define AMDFCH41_MMIO_ADDR 0xfed80000u +#define AMDFCH41_MMIO_SMBUS_OFF 0x0a00 +#define AMDFCH41_MMIO_WDT_OFF 0x0b00 + +/* + * PCI Device IDs and revisions. + * SB600 RRG 2.3.1.1, + * SB7xx RRG 2.3.1.1, + * SB8xx RRG 2.3.1, + * BKDG for Family 16h Models 00h-0Fh 3.26.7.1, + * BKDG for Family 16h Models 30h-3Fh 3.26.7.1. + * Also, see i2c-piix4 aka piix4_smbus Linux driver. + */ +#define AMDSB_SMBUS_DEVID 0x43851002 +#define AMDSB8_SMBUS_REVID 0x40 +#define AMDFCH_SMBUS_DEVID 0x780b1022 +#define AMDFCH41_SMBUS_REVID 0x41 +#define AMDCZ_SMBUS_DEVID 0x790b1022 +#define AMDCZ49_SMBUS_REVID 0x49 + Property changes on: head/sys/dev/amdsbwd/amd_chipset.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/amdsbwd/amdsbwd.c =================================================================== --- head/sys/dev/amdsbwd/amdsbwd.c (revision 306217) +++ head/sys/dev/amdsbwd/amdsbwd.c (revision 306218) @@ -1,588 +1,542 @@ /*- * Copyright (c) 2009 Andriy Gapon * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * This is a driver for watchdog timer present in AMD SB600/SB7xx/SB8xx * southbridges. * Please see the following specifications for the descriptions of the * registers and flags: * - AMD SB600 Register Reference Guide, Public Version, Rev. 3.03 (SB600 RRG) * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/46155_sb600_rrg_pub_3.03.pdf * - AMD SB700/710/750 Register Reference Guide (RRG) * http://developer.amd.com/assets/43009_sb7xx_rrg_pub_1.00.pdf * - AMD SB700/710/750 Register Programming Requirements (RPR) * http://developer.amd.com/assets/42413_sb7xx_rpr_pub_1.00.pdf * - AMD SB800-Series Southbridges Register Reference Guide (RRG) * http://support.amd.com/us/Embedded_TechDocs/45482.pdf * Please see the following for Watchdog Resource Table specification: * - Watchdog Timer Hardware Requirements for Windows Server 2003 (WDRT) * http://www.microsoft.com/whdc/system/sysinternals/watchdog.mspx * AMD SB600/SB7xx/SB8xx watchdog hardware seems to conform to the above * specifications, but the table hasn't been spotted in the wild yet. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include +#include #include -/* SB7xx RRG 2.3.3.1.1. */ -#define AMDSB_PMIO_INDEX 0xcd6 -#define AMDSB_PMIO_DATA (PMIO_INDEX + 1) -#define AMDSB_PMIO_WIDTH 2 -/* SB7xx RRG 2.3.3.2. */ -#define AMDSB_PM_RESET_STATUS0 0x44 -#define AMDSB_PM_RESET_STATUS1 0x45 -#define AMDSB_WD_RST_STS 0x02 -/* SB7xx RRG 2.3.3.2, RPR 2.36. */ -#define AMDSB_PM_WDT_CTRL 0x69 -#define AMDSB_WDT_DISABLE 0x01 -#define AMDSB_WDT_RES_MASK (0x02 | 0x04) -#define AMDSB_WDT_RES_32US 0x00 -#define AMDSB_WDT_RES_10MS 0x02 -#define AMDSB_WDT_RES_100MS 0x04 -#define AMDSB_WDT_RES_1S 0x06 -#define AMDSB_PM_WDT_BASE_LSB 0x6c -#define AMDSB_PM_WDT_BASE_MSB 0x6f -/* SB8xx RRG 2.3.3. */ -#define AMDSB8_PM_WDT_EN 0x48 -#define AMDSB8_WDT_DEC_EN 0x01 -#define AMDSB8_WDT_DISABLE 0x02 -#define AMDSB8_PM_WDT_CTRL 0x4c -#define AMDSB8_WDT_32KHZ 0x00 -#define AMDSB8_WDT_1HZ 0x03 -#define AMDSB8_WDT_RES_MASK 0x03 -#define AMDSB8_PM_RESET_STATUS0 0xC0 -#define AMDSB8_PM_RESET_STATUS1 0xC1 -#define AMDSB8_WD_RST_STS 0x20 -/* SB7xx RRG 2.3.4, WDRT. */ +/* + * Registers in the Watchdog IO space. + * See SB7xx RRG 2.3.4, WDRT. + */ #define AMDSB_WD_CTRL 0x00 #define AMDSB_WD_RUN 0x01 #define AMDSB_WD_FIRED 0x02 #define AMDSB_WD_SHUTDOWN 0x04 #define AMDSB_WD_DISABLE 0x08 #define AMDSB_WD_RESERVED 0x70 #define AMDSB_WD_RELOAD 0x80 #define AMDSB_WD_COUNT 0x04 #define AMDSB_WD_COUNT_MASK 0xffff #define AMDSB_WDIO_REG_WIDTH 4 -/* WDRT */ -#define MAXCOUNT_MIN_VALUE 511 -/* SB7xx RRG 2.3.1.1, SB600 RRG 2.3.1.1, SB8xx RRG 2.3.1. */ -#define AMDSB_SMBUS_DEVID 0x43851002 -#define AMDSB8_SMBUS_REVID 0x40 -#define AMDHUDSON_SMBUS_DEVID 0x780b1022 -#define AMDKERNCZ_SMBUS_DEVID 0x790b1022 -/* BKDG Family 16h Models 30h - 3Fh */ -#define AMDFCH16H3XH_PM_WDT_EN 0x00 -#define AMDFCH_WDT_DEC_EN 0x80 -#define AMDFCH16H3XH_PM_WDT_CTRL 0x03 -#define AMDFCH_WDT_RES_MASK 0x03 -#define AMDFCH_WDT_RES_32US 0x00 -#define AMDFCH_WDT_RES_10MS 0x01 -#define AMDFCH_WDT_RES_100MS 0x02 -#define AMDFCH_WDT_RES_1S 0x03 -#define AMDFCH_WDT_ENABLE_MASK 0x0c -#define AMDFCH_WDT_ENABLE 0x00 -#define AMDFCH16H3XH_PM_MMIO_CTRL 0x04 -#define AMDFCH_WDT_MMIO_EN 0x02 -#define AMDFCH16H3XH_WDT_ADDR1 0xfed80b00u -#define AMDFCH16H3XH_WDT_ADDR2 0xfeb00000u #define amdsbwd_verbose_printf(dev, ...) \ do { \ if (bootverbose) \ device_printf(dev, __VA_ARGS__);\ } while (0) struct amdsbwd_softc { device_t dev; eventhandler_tag ev_tag; struct resource *res_ctrl; struct resource *res_count; int rid_ctrl; int rid_count; int ms_per_tick; int max_ticks; int active; unsigned int timeout; }; static void amdsbwd_identify(driver_t *driver, device_t parent); static int amdsbwd_probe(device_t dev); static int amdsbwd_attach(device_t dev); static int amdsbwd_detach(device_t dev); static device_method_t amdsbwd_methods[] = { DEVMETHOD(device_identify, amdsbwd_identify), DEVMETHOD(device_probe, amdsbwd_probe), DEVMETHOD(device_attach, amdsbwd_attach), DEVMETHOD(device_detach, amdsbwd_detach), #if 0 DEVMETHOD(device_shutdown, amdsbwd_detach), #endif DEVMETHOD_END }; static devclass_t amdsbwd_devclass; static driver_t amdsbwd_driver = { "amdsbwd", amdsbwd_methods, sizeof(struct amdsbwd_softc) }; DRIVER_MODULE(amdsbwd, isa, amdsbwd_driver, amdsbwd_devclass, NULL, NULL); static uint8_t pmio_read(struct resource *res, uint8_t reg) { bus_write_1(res, 0, reg); /* Index */ return (bus_read_1(res, 1)); /* Data */ } static void pmio_write(struct resource *res, uint8_t reg, uint8_t val) { bus_write_1(res, 0, reg); /* Index */ bus_write_1(res, 1, val); /* Data */ } static uint32_t wdctrl_read(struct amdsbwd_softc *sc) { return (bus_read_4(sc->res_ctrl, 0)); } static void wdctrl_write(struct amdsbwd_softc *sc, uint32_t val) { bus_write_4(sc->res_ctrl, 0, val); } static __unused uint32_t wdcount_read(struct amdsbwd_softc *sc) { return (bus_read_4(sc->res_count, 0)); } static void wdcount_write(struct amdsbwd_softc *sc, uint32_t val) { bus_write_4(sc->res_count, 0, val); } static void amdsbwd_tmr_enable(struct amdsbwd_softc *sc) { uint32_t val; val = wdctrl_read(sc); val |= AMDSB_WD_RUN; wdctrl_write(sc, val); sc->active = 1; amdsbwd_verbose_printf(sc->dev, "timer enabled\n"); } static void amdsbwd_tmr_disable(struct amdsbwd_softc *sc) { uint32_t val; val = wdctrl_read(sc); val &= ~AMDSB_WD_RUN; wdctrl_write(sc, val); sc->active = 0; amdsbwd_verbose_printf(sc->dev, "timer disabled\n"); } static void amdsbwd_tmr_reload(struct amdsbwd_softc *sc) { uint32_t val; val = wdctrl_read(sc); val |= AMDSB_WD_RELOAD; wdctrl_write(sc, val); } static void amdsbwd_tmr_set(struct amdsbwd_softc *sc, uint16_t timeout) { timeout &= AMDSB_WD_COUNT_MASK; wdcount_write(sc, timeout); sc->timeout = timeout; amdsbwd_verbose_printf(sc->dev, "timeout set to %u ticks\n", timeout); } static void amdsbwd_event(void *arg, unsigned int cmd, int *error) { struct amdsbwd_softc *sc = arg; unsigned int timeout; /* convert from power-of-two-ns to WDT ticks */ cmd &= WD_INTERVAL; if (cmd < WD_TO_1SEC) cmd = 0; if (cmd) { timeout = ((uint64_t)1 << (cmd - WD_TO_1MS)) / sc->ms_per_tick; if (timeout > sc->max_ticks) timeout = sc->max_ticks; if (timeout != sc->timeout) { amdsbwd_tmr_set(sc, timeout); if (!sc->active) amdsbwd_tmr_enable(sc); } amdsbwd_tmr_reload(sc); *error = 0; } else { if (sc->active) amdsbwd_tmr_disable(sc); } } static void amdsbwd_identify(driver_t *driver, device_t parent) { device_t child; device_t smb_dev; if (resource_disabled("amdsbwd", 0)) return; if (device_find_child(parent, "amdsbwd", -1) != NULL) return; /* * Try to identify SB600/SB7xx by PCI Device ID of SMBus device * that should be present at bus 0, device 20, function 0. */ smb_dev = pci_find_bsf(0, 20, 0); if (smb_dev == NULL) return; if (pci_get_devid(smb_dev) != AMDSB_SMBUS_DEVID && - pci_get_devid(smb_dev) != AMDHUDSON_SMBUS_DEVID && - pci_get_devid(smb_dev) != AMDKERNCZ_SMBUS_DEVID) + pci_get_devid(smb_dev) != AMDFCH_SMBUS_DEVID && + pci_get_devid(smb_dev) != AMDCZ_SMBUS_DEVID) return; child = BUS_ADD_CHILD(parent, ISA_ORDER_SPECULATIVE, "amdsbwd", -1); if (child == NULL) device_printf(parent, "add amdsbwd child failed\n"); } static void amdsbwd_probe_sb7xx(device_t dev, struct resource *pmres, uint32_t *addr) { uint8_t val; int i; /* Report cause of previous reset for user's convenience. */ val = pmio_read(pmres, AMDSB_PM_RESET_STATUS0); if (val != 0) amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val); val = pmio_read(pmres, AMDSB_PM_RESET_STATUS1); if (val != 0) amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val); if ((val & AMDSB_WD_RST_STS) != 0) device_printf(dev, "Previous Reset was caused by Watchdog\n"); /* Find base address of memory mapped WDT registers. */ for (*addr = 0, i = 0; i < 4; i++) { *addr <<= 8; *addr |= pmio_read(pmres, AMDSB_PM_WDT_BASE_MSB - i); } *addr &= ~0x07u; /* Set watchdog timer tick to 1s. */ val = pmio_read(pmres, AMDSB_PM_WDT_CTRL); val &= ~AMDSB_WDT_RES_MASK; val |= AMDSB_WDT_RES_1S; pmio_write(pmres, AMDSB_PM_WDT_CTRL, val); /* Enable watchdog device (in stopped state). */ val = pmio_read(pmres, AMDSB_PM_WDT_CTRL); val &= ~AMDSB_WDT_DISABLE; pmio_write(pmres, AMDSB_PM_WDT_CTRL, val); /* * XXX TODO: Ensure that watchdog decode is enabled * (register 0x41, bit 3). */ device_set_desc(dev, "AMD SB600/SB7xx Watchdog Timer"); } static void amdsbwd_probe_sb8xx(device_t dev, struct resource *pmres, uint32_t *addr) { uint8_t val; int i; /* Report cause of previous reset for user's convenience. */ val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS0); if (val != 0) amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val); val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS1); if (val != 0) amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val); if ((val & AMDSB8_WD_RST_STS) != 0) device_printf(dev, "Previous Reset was caused by Watchdog\n"); /* Find base address of memory mapped WDT registers. */ for (*addr = 0, i = 0; i < 4; i++) { *addr <<= 8; *addr |= pmio_read(pmres, AMDSB8_PM_WDT_EN + 3 - i); } *addr &= ~0x07u; /* Set watchdog timer tick to 1s. */ val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL); val &= ~AMDSB8_WDT_RES_MASK; val |= AMDSB8_WDT_1HZ; pmio_write(pmres, AMDSB8_PM_WDT_CTRL, val); #ifdef AMDSBWD_DEBUG val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL); amdsbwd_verbose_printf(dev, "AMDSB8_PM_WDT_CTRL value = %#04x\n", val); #endif /* * Enable watchdog device (in stopped state) * and decoding of its address. */ val = pmio_read(pmres, AMDSB8_PM_WDT_EN); val &= ~AMDSB8_WDT_DISABLE; val |= AMDSB8_WDT_DEC_EN; pmio_write(pmres, AMDSB8_PM_WDT_EN, val); #ifdef AMDSBWD_DEBUG val = pmio_read(pmres, AMDSB8_PM_WDT_EN); device_printf(dev, "AMDSB8_PM_WDT_EN value = %#04x\n", val); #endif device_set_desc(dev, "AMD SB8xx/SB9xx/Axx Watchdog Timer"); } static void -amdsbwd_probe_fch_16h_3xh(device_t dev, struct resource *pmres, uint32_t *addr) +amdsbwd_probe_fch41(device_t dev, struct resource *pmres, uint32_t *addr) { uint8_t val; - val = pmio_read(pmres, AMDFCH16H3XH_PM_MMIO_CTRL); - if ((val & AMDFCH_WDT_MMIO_EN) != 0) { + val = pmio_read(pmres, AMDFCH41_PM_ISA_CTRL); + if ((val & AMDFCH41_MMIO_EN) != 0) { /* Fixed offset for the watchdog within ACPI MMIO range. */ amdsbwd_verbose_printf(dev, "ACPI MMIO range is enabled\n"); - *addr = AMDFCH16H3XH_WDT_ADDR1; + *addr = AMDFCH41_MMIO_ADDR + AMDFCH41_MMIO_WDT_OFF; } else { /* * Enable decoding of watchdog MMIO address. */ - val = pmio_read(pmres, AMDFCH16H3XH_PM_WDT_EN); - val |= AMDFCH_WDT_DEC_EN; - pmio_write(pmres, AMDFCH16H3XH_PM_WDT_EN, val); + val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0); + val |= AMDFCH41_WDT_EN; + pmio_write(pmres, AMDFCH41_PM_DECODE_EN0, val); #ifdef AMDSBWD_DEBUG - val = pmio_read(pmres, AMDFCH16H3XH_PM_WDT_EN); - device_printf(dev, "AMDFCH16H3XH_PM_WDT_EN value = %#04x\n", + val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0); + device_printf(dev, "AMDFCH41_PM_DECODE_EN0 value = %#04x\n", val); #endif /* Special fixed MMIO range for the watchdog. */ - *addr = AMDFCH16H3XH_WDT_ADDR2; + *addr = AMDFCH41_WDT_FIXED_ADDR; } /* * Set watchdog timer tick to 1s and * enable the watchdog device (in stopped state). */ - val = pmio_read(pmres, AMDFCH16H3XH_PM_WDT_CTRL); - val &= ~AMDFCH_WDT_RES_MASK; - val |= AMDFCH_WDT_RES_1S; - val &= ~AMDFCH_WDT_ENABLE_MASK; - val |= AMDFCH_WDT_ENABLE; - pmio_write(pmres, AMDFCH16H3XH_PM_WDT_CTRL, val); + val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3); + val &= ~AMDFCH41_WDT_RES_MASK; + val |= AMDFCH41_WDT_RES_1S; + val &= ~AMDFCH41_WDT_EN_MASK; + val |= AMDFCH41_WDT_ENABLE; + pmio_write(pmres, AMDFCH41_PM_DECODE_EN3, val); #ifdef AMDSBWD_DEBUG - val = pmio_read(pmres, AMDFCH16H3XH_PM_WDT_CTRL); - amdsbwd_verbose_printf(dev, "AMDFCH16H3XH_PM_WDT_CTRL value = %#04x\n", + val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3); + amdsbwd_verbose_printf(dev, "AMDFCH41_PM_DECODE_EN3 value = %#04x\n", val); #endif - device_set_desc(dev, "AMD FCH Rev 42h+ Watchdog Timer"); + device_set_desc(dev, "AMD FCH Rev 41h+ Watchdog Timer"); } static int amdsbwd_probe(device_t dev) { struct resource *res; device_t smb_dev; uint32_t addr; int rid; int rc; uint32_t devid; uint8_t revid; /* Do not claim some ISA PnP device by accident. */ if (isa_get_logicalid(dev) != 0) return (ENXIO); rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, AMDSB_PMIO_INDEX, AMDSB_PMIO_WIDTH); if (rc != 0) { device_printf(dev, "bus_set_resource for IO failed\n"); return (ENXIO); } rid = 0; res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, RF_ACTIVE | RF_SHAREABLE); if (res == NULL) { device_printf(dev, "bus_alloc_resource for IO failed\n"); return (ENXIO); } smb_dev = pci_find_bsf(0, 20, 0); KASSERT(smb_dev != NULL, ("can't find SMBus PCI device\n")); devid = pci_get_devid(smb_dev); revid = pci_get_revid(smb_dev); if (devid == AMDSB_SMBUS_DEVID && revid < AMDSB8_SMBUS_REVID) amdsbwd_probe_sb7xx(dev, res, &addr); - else if (devid == AMDSB_SMBUS_DEVID || devid == AMDKERNCZ_SMBUS_DEVID || - (devid == AMDHUDSON_SMBUS_DEVID && revid < 0x42)) + else if (devid == AMDSB_SMBUS_DEVID || + (devid == AMDFCH_SMBUS_DEVID && revid < AMDFCH41_SMBUS_REVID) || + (devid == AMDCZ_SMBUS_DEVID && revid < AMDCZ49_SMBUS_REVID)) amdsbwd_probe_sb8xx(dev, res, &addr); else - amdsbwd_probe_fch_16h_3xh(dev, res, &addr); + amdsbwd_probe_fch41(dev, res, &addr); bus_release_resource(dev, SYS_RES_IOPORT, rid, res); bus_delete_resource(dev, SYS_RES_IOPORT, rid); amdsbwd_verbose_printf(dev, "memory base address = %#010x\n", addr); rc = bus_set_resource(dev, SYS_RES_MEMORY, 0, addr + AMDSB_WD_CTRL, AMDSB_WDIO_REG_WIDTH); if (rc != 0) { device_printf(dev, "bus_set_resource for control failed\n"); return (ENXIO); } rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, addr + AMDSB_WD_COUNT, AMDSB_WDIO_REG_WIDTH); if (rc != 0) { device_printf(dev, "bus_set_resource for count failed\n"); return (ENXIO); } return (0); } static int amdsbwd_attach_sb(device_t dev, struct amdsbwd_softc *sc) { sc->max_ticks = UINT16_MAX; sc->rid_ctrl = 0; sc->rid_count = 1; sc->ms_per_tick = 1000; sc->res_ctrl = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid_ctrl, RF_ACTIVE); if (sc->res_ctrl == NULL) { device_printf(dev, "bus_alloc_resource for ctrl failed\n"); return (ENXIO); } sc->res_count = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid_count, RF_ACTIVE); if (sc->res_count == NULL) { device_printf(dev, "bus_alloc_resource for count failed\n"); return (ENXIO); } return (0); } static int amdsbwd_attach(device_t dev) { struct amdsbwd_softc *sc; int rc; sc = device_get_softc(dev); sc->dev = dev; rc = amdsbwd_attach_sb(dev, sc); if (rc != 0) goto fail; #ifdef AMDSBWD_DEBUG device_printf(dev, "wd ctrl = %#04x\n", wdctrl_read(sc)); device_printf(dev, "wd count = %#04x\n", wdcount_read(sc)); #endif /* Setup initial state of Watchdog Control. */ wdctrl_write(sc, AMDSB_WD_FIRED); if (wdctrl_read(sc) & AMDSB_WD_DISABLE) { device_printf(dev, "watchdog hardware is disabled\n"); goto fail; } sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, amdsbwd_event, sc, EVENTHANDLER_PRI_ANY); return (0); fail: amdsbwd_detach(dev); return (ENXIO); } static int amdsbwd_detach(device_t dev) { struct amdsbwd_softc *sc; sc = device_get_softc(dev); if (sc->ev_tag != NULL) EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); if (sc->active) amdsbwd_tmr_disable(sc); if (sc->res_ctrl != NULL) bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ctrl, sc->res_ctrl); if (sc->res_count != NULL) bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_count, sc->res_count); return (0); } Index: head/sys/dev/intpm/intpm.c =================================================================== --- head/sys/dev/intpm/intpm.c (revision 306217) +++ head/sys/dev/intpm/intpm.c (revision 306218) @@ -1,931 +1,928 @@ /*- * Copyright (c) 1998, 1999 Takanori Watanabe * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include "smbus_if.h" #include #include #include +#include #include "opt_intpm.h" struct intsmb_softc { device_t dev; struct resource *io_res; struct resource *irq_res; void *irq_hand; device_t smbus; int io_rid; int isbusy; int cfg_irq9; int sb8xx; int poll; struct mtx lock; }; #define INTSMB_LOCK(sc) mtx_lock(&(sc)->lock) #define INTSMB_UNLOCK(sc) mtx_unlock(&(sc)->lock) #define INTSMB_LOCK_ASSERT(sc) mtx_assert(&(sc)->lock, MA_OWNED) static int intsmb_probe(device_t); static int intsmb_attach(device_t); static int intsmb_detach(device_t); static int intsmb_intr(struct intsmb_softc *sc); static int intsmb_slvintr(struct intsmb_softc *sc); static void intsmb_alrintr(struct intsmb_softc *sc); static int intsmb_callback(device_t dev, int index, void *data); static int intsmb_quick(device_t dev, u_char slave, int how); static int intsmb_sendb(device_t dev, u_char slave, char byte); static int intsmb_recvb(device_t dev, u_char slave, char *byte); static int intsmb_writeb(device_t dev, u_char slave, char cmd, char byte); static int intsmb_writew(device_t dev, u_char slave, char cmd, short word); static int intsmb_readb(device_t dev, u_char slave, char cmd, char *byte); static int intsmb_readw(device_t dev, u_char slave, char cmd, short *word); static int intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata); static int intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf); static int intsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf); static void intsmb_start(struct intsmb_softc *sc, u_char cmd, int nointr); static int intsmb_stop(struct intsmb_softc *sc); static int intsmb_stop_poll(struct intsmb_softc *sc); static int intsmb_free(struct intsmb_softc *sc); static void intsmb_rawintr(void *arg); static int intsmb_probe(device_t dev) { switch (pci_get_devid(dev)) { case 0x71138086: /* Intel 82371AB */ case 0x719b8086: /* Intel 82443MX */ #if 0 /* Not a good idea yet, this stops isab0 functioning */ case 0x02001166: /* ServerWorks OSB4 */ #endif device_set_desc(dev, "Intel PIIX4 SMBUS Interface"); break; case 0x43721002: device_set_desc(dev, "ATI IXP400 SMBus Controller"); break; - case 0x43851002: + case AMDSB_SMBUS_DEVID: device_set_desc(dev, "AMD SB600/7xx/8xx/9xx SMBus Controller"); break; - case 0x780b1022: /* AMD FCH */ - if (pci_get_revid(dev) < 0x40) - return (ENXIO); + case AMDFCH_SMBUS_DEVID: /* AMD FCH */ + case AMDCZ_SMBUS_DEVID: /* AMD Carizzo FCH */ device_set_desc(dev, "AMD FCH SMBus Controller"); break; default: return (ENXIO); } return (BUS_PROBE_DEFAULT); } static uint8_t -sb8xx_pmio_read(struct resource *res, uint8_t reg) +amd_pmio_read(struct resource *res, uint8_t reg) { bus_write_1(res, 0, reg); /* Index */ return (bus_read_1(res, 1)); /* Data */ } static int sb8xx_attach(device_t dev) { - static const int AMDSB_PMIO_INDEX = 0xcd6; - static const int AMDSB_PMIO_WIDTH = 2; - static const int AMDSB8_SMBUS_ADDR = 0x2c; - static const int AMDSB8_SMBUS_EN = 0x01; - static const int AMDSB8_SMBUS_ADDR_MASK = ~0x1fu; static const int AMDSB_SMBIO_WIDTH = 0x14; - static const int AMDSB_SMBUS_CFG = 0x10; - static const int AMDSB_SMBUS_IRQ = 0x01; - static const int AMDSB_SMBUS_REV_MASK = ~0x0fu; - static const int AMDSB_SMBUS_REV_SHIFT = 4; - static const int AMDSB_IO_RID = 0; - struct intsmb_softc *sc; struct resource *res; + uint32_t devid; + uint8_t revid; uint16_t addr; - uint8_t cfg; int rid; int rc; + bool enabled; sc = device_get_softc(dev); - rid = AMDSB_IO_RID; + rid = 0; rc = bus_set_resource(dev, SYS_RES_IOPORT, rid, AMDSB_PMIO_INDEX, AMDSB_PMIO_WIDTH); if (rc != 0) { device_printf(dev, "bus_set_resource for PM IO failed\n"); return (ENXIO); } res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, - RF_ACTIVE | RF_SHAREABLE); + RF_ACTIVE); if (res == NULL) { device_printf(dev, "bus_alloc_resource for PM IO failed\n"); return (ENXIO); } - addr = sb8xx_pmio_read(res, AMDSB8_SMBUS_ADDR + 1); - addr <<= 8; - addr |= sb8xx_pmio_read(res, AMDSB8_SMBUS_ADDR); + devid = pci_get_devid(dev); + revid = pci_get_revid(dev); + if (devid == AMDSB_SMBUS_DEVID || + (devid == AMDFCH_SMBUS_DEVID && revid < AMDFCH41_SMBUS_REVID) || + (devid == AMDCZ_SMBUS_DEVID && revid < AMDCZ49_SMBUS_REVID)) { + addr = amd_pmio_read(res, AMDSB8_PM_SMBUS_EN + 1); + addr <<= 8; + addr |= amd_pmio_read(res, AMDSB8_PM_SMBUS_EN); + enabled = (addr & AMDSB8_SMBUS_EN) != 0; + addr &= AMDSB8_SMBUS_ADDR_MASK; + } else { + addr = amd_pmio_read(res, AMDFCH41_PM_DECODE_EN0); + enabled = (addr & AMDFCH41_SMBUS_EN) != 0; + addr = amd_pmio_read(res, AMDFCH41_PM_DECODE_EN1); + addr <<= 8; + } bus_release_resource(dev, SYS_RES_IOPORT, rid, res); bus_delete_resource(dev, SYS_RES_IOPORT, rid); - if ((addr & AMDSB8_SMBUS_EN) == 0) { - device_printf(dev, "SB8xx SMBus not enabled\n"); + if (!enabled) { + device_printf(dev, "SB8xx/SB9xx/FCH SMBus not enabled\n"); return (ENXIO); } - addr &= AMDSB8_SMBUS_ADDR_MASK; - sc->io_rid = AMDSB_IO_RID; + sc->io_rid = 0; rc = bus_set_resource(dev, SYS_RES_IOPORT, sc->io_rid, addr, AMDSB_SMBIO_WIDTH); if (rc != 0) { device_printf(dev, "bus_set_resource for SMBus IO failed\n"); return (ENXIO); } if (res == NULL) { device_printf(dev, "bus_alloc_resource for SMBus IO failed\n"); return (ENXIO); } sc->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->io_rid, - RF_ACTIVE | RF_SHAREABLE); - cfg = bus_read_1(sc->io_res, AMDSB_SMBUS_CFG); - + RF_ACTIVE); sc->poll = 1; - device_printf(dev, "intr %s disabled ", - (cfg & AMDSB_SMBUS_IRQ) != 0 ? "IRQ" : "SMI"); - printf("revision %d\n", - (cfg & AMDSB_SMBUS_REV_MASK) >> AMDSB_SMBUS_REV_SHIFT); - return (0); } static void intsmb_release_resources(device_t dev) { struct intsmb_softc *sc = device_get_softc(dev); if (sc->smbus) device_delete_child(dev, sc->smbus); if (sc->irq_hand) bus_teardown_intr(dev, sc->irq_res, sc->irq_hand); if (sc->irq_res) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); if (sc->io_res) bus_release_resource(dev, SYS_RES_IOPORT, sc->io_rid, sc->io_res); mtx_destroy(&sc->lock); } static int intsmb_attach(device_t dev) { struct intsmb_softc *sc = device_get_softc(dev); int error, rid, value; int intr; char *str; sc->dev = dev; mtx_init(&sc->lock, device_get_nameunit(dev), "intsmb", MTX_DEF); sc->cfg_irq9 = 0; switch (pci_get_devid(dev)) { #ifndef NO_CHANGE_PCICONF case 0x71138086: /* Intel 82371AB */ case 0x719b8086: /* Intel 82443MX */ /* Changing configuration is allowed. */ sc->cfg_irq9 = 1; break; #endif - case 0x43851002: - if (pci_get_revid(dev) >= 0x40) + case AMDSB_SMBUS_DEVID: + if (pci_get_revid(dev) >= AMDSB8_SMBUS_REVID) sc->sb8xx = 1; break; - case 0x780b1022: + case AMDFCH_SMBUS_DEVID: + case AMDCZ_SMBUS_DEVID: sc->sb8xx = 1; break; } if (sc->sb8xx) { error = sb8xx_attach(dev); if (error != 0) goto fail; else goto no_intr; } sc->io_rid = PCI_BASE_ADDR_SMB; sc->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->io_rid, RF_ACTIVE); if (sc->io_res == NULL) { device_printf(dev, "Could not allocate I/O space\n"); error = ENXIO; goto fail; } if (sc->cfg_irq9) { pci_write_config(dev, PCIR_INTLINE, 0x9, 1); pci_write_config(dev, PCI_HST_CFG_SMB, PCI_INTR_SMB_IRQ9 | PCI_INTR_SMB_ENABLE, 1); } value = pci_read_config(dev, PCI_HST_CFG_SMB, 1); sc->poll = (value & PCI_INTR_SMB_ENABLE) == 0; intr = value & PCI_INTR_SMB_MASK; switch (intr) { case PCI_INTR_SMB_SMI: str = "SMI"; break; case PCI_INTR_SMB_IRQ9: str = "IRQ 9"; break; case PCI_INTR_SMB_IRQ_PCI: str = "PCI IRQ"; break; default: str = "BOGUS"; } device_printf(dev, "intr %s %s ", str, sc->poll == 0 ? "enabled" : "disabled"); printf("revision %d\n", pci_read_config(dev, PCI_REVID_SMB, 1)); if (!sc->poll && intr == PCI_INTR_SMB_SMI) { device_printf(dev, "using polling mode when configured interrupt is SMI\n"); sc->poll = 1; } if (sc->poll) goto no_intr; if (intr != PCI_INTR_SMB_IRQ9 && intr != PCI_INTR_SMB_IRQ_PCI) { device_printf(dev, "Unsupported interrupt mode\n"); error = ENXIO; goto fail; } /* Force IRQ 9. */ rid = 0; if (sc->cfg_irq9) bus_set_resource(dev, SYS_RES_IRQ, rid, 9, 1); sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); if (sc->irq_res == NULL) { device_printf(dev, "Could not allocate irq\n"); error = ENXIO; goto fail; } error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, intsmb_rawintr, sc, &sc->irq_hand); if (error) { device_printf(dev, "Failed to map intr\n"); goto fail; } no_intr: sc->isbusy = 0; sc->smbus = device_add_child(dev, "smbus", -1); if (sc->smbus == NULL) { device_printf(dev, "failed to add smbus child\n"); error = ENXIO; goto fail; } error = device_probe_and_attach(sc->smbus); if (error) { device_printf(dev, "failed to probe+attach smbus child\n"); goto fail; } #ifdef ENABLE_ALART /* Enable Arart */ bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN); #endif return (0); fail: intsmb_release_resources(dev); return (error); } static int intsmb_detach(device_t dev) { int error; error = bus_generic_detach(dev); if (error) { device_printf(dev, "bus detach failed\n"); return (error); } intsmb_release_resources(dev); return (0); } static void intsmb_rawintr(void *arg) { struct intsmb_softc *sc = arg; INTSMB_LOCK(sc); intsmb_intr(sc); intsmb_slvintr(sc); INTSMB_UNLOCK(sc); } static int intsmb_callback(device_t dev, int index, void *data) { int error = 0; switch (index) { case SMB_REQUEST_BUS: break; case SMB_RELEASE_BUS: break; default: error = SMB_EINVAL; } return (error); } /* Counterpart of smbtx_smb_free(). */ static int intsmb_free(struct intsmb_softc *sc) { INTSMB_LOCK_ASSERT(sc); if ((bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) & PIIX4_SMBHSTSTAT_BUSY) || #ifdef ENABLE_ALART (bus_read_1(sc->io_res, PIIX4_SMBSLVSTS) & PIIX4_SMBSLVSTS_BUSY) || #endif sc->isbusy) return (SMB_EBUSY); sc->isbusy = 1; /* Disable Interrupt in slave part. */ #ifndef ENABLE_ALART bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, 0); #endif /* Reset INTR Flag to prepare INTR. */ bus_write_1(sc->io_res, PIIX4_SMBHSTSTS, PIIX4_SMBHSTSTAT_INTR | PIIX4_SMBHSTSTAT_ERR | PIIX4_SMBHSTSTAT_BUSC | PIIX4_SMBHSTSTAT_FAIL); return (0); } static int intsmb_intr(struct intsmb_softc *sc) { int status, tmp; status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS); if (status & PIIX4_SMBHSTSTAT_BUSY) return (1); if (status & (PIIX4_SMBHSTSTAT_INTR | PIIX4_SMBHSTSTAT_ERR | PIIX4_SMBHSTSTAT_BUSC | PIIX4_SMBHSTSTAT_FAIL)) { tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT); bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp & ~PIIX4_SMBHSTCNT_INTREN); if (sc->isbusy) { sc->isbusy = 0; wakeup(sc); } return (0); } return (1); /* Not Completed */ } static int intsmb_slvintr(struct intsmb_softc *sc) { int status; status = bus_read_1(sc->io_res, PIIX4_SMBSLVSTS); if (status & PIIX4_SMBSLVSTS_BUSY) return (1); if (status & PIIX4_SMBSLVSTS_ALART) intsmb_alrintr(sc); else if (status & ~(PIIX4_SMBSLVSTS_ALART | PIIX4_SMBSLVSTS_SDW2 | PIIX4_SMBSLVSTS_SDW1)) { } /* Reset Status Register */ bus_write_1(sc->io_res, PIIX4_SMBSLVSTS, PIIX4_SMBSLVSTS_ALART | PIIX4_SMBSLVSTS_SDW2 | PIIX4_SMBSLVSTS_SDW1 | PIIX4_SMBSLVSTS_SLV); return (0); } static void intsmb_alrintr(struct intsmb_softc *sc) { int slvcnt; #ifdef ENABLE_ALART int error; uint8_t addr; #endif /* Stop generating INTR from ALART. */ slvcnt = bus_read_1(sc->io_res, PIIX4_SMBSLVCNT); #ifdef ENABLE_ALART bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, slvcnt & ~PIIX4_SMBSLVCNT_ALTEN); #endif DELAY(5); /* Ask bus who asserted it and then ask it what's the matter. */ #ifdef ENABLE_ALART error = intsmb_free(sc); if (error) return; bus_write_1(sc->io_res, PIIX4_SMBHSTADD, SMBALTRESP | LSB); intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 1); error = intsmb_stop_poll(sc); if (error) device_printf(sc->dev, "ALART: ERROR\n"); else { addr = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0); device_printf(sc->dev, "ALART_RESPONSE: 0x%x\n", addr); } /* Re-enable INTR from ALART. */ bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, slvcnt | PIIX4_SMBSLVCNT_ALTEN); DELAY(5); #endif } static void intsmb_start(struct intsmb_softc *sc, unsigned char cmd, int nointr) { unsigned char tmp; INTSMB_LOCK_ASSERT(sc); tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT); tmp &= 0xe0; tmp |= cmd; tmp |= PIIX4_SMBHSTCNT_START; /* While not in autoconfiguration enable interrupts. */ if (!sc->poll && !cold && !nointr) tmp |= PIIX4_SMBHSTCNT_INTREN; bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp); } static int intsmb_error(device_t dev, int status) { int error = 0; if (status & PIIX4_SMBHSTSTAT_ERR) error |= SMB_EBUSERR; if (status & PIIX4_SMBHSTSTAT_BUSC) error |= SMB_ECOLLI; if (status & PIIX4_SMBHSTSTAT_FAIL) error |= SMB_ENOACK; if (error != 0 && bootverbose) device_printf(dev, "error = %d, status = %#x\n", error, status); return (error); } /* * Polling Code. * * Polling is not encouraged because it requires waiting for the * device if it is busy. * (29063505.pdf from Intel) But during boot, interrupt cannot be used, so use * polling code then. */ static int intsmb_stop_poll(struct intsmb_softc *sc) { int error, i, status, tmp; INTSMB_LOCK_ASSERT(sc); /* First, wait for busy to be set. */ for (i = 0; i < 0x7fff; i++) if (bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) & PIIX4_SMBHSTSTAT_BUSY) break; /* Wait for busy to clear. */ for (i = 0; i < 0x7fff; i++) { status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS); if (!(status & PIIX4_SMBHSTSTAT_BUSY)) { sc->isbusy = 0; error = intsmb_error(sc->dev, status); return (error); } } /* Timed out waiting for busy to clear. */ sc->isbusy = 0; tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT); bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp & ~PIIX4_SMBHSTCNT_INTREN); return (SMB_ETIMEOUT); } /* * Wait for completion and return result. */ static int intsmb_stop(struct intsmb_softc *sc) { int error, status; INTSMB_LOCK_ASSERT(sc); if (sc->poll || cold) /* So that it can use device during device probe on SMBus. */ return (intsmb_stop_poll(sc)); error = msleep(sc, &sc->lock, PWAIT | PCATCH, "SMBWAI", hz / 8); if (error == 0) { status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS); if (!(status & PIIX4_SMBHSTSTAT_BUSY)) { error = intsmb_error(sc->dev, status); if (error == 0 && !(status & PIIX4_SMBHSTSTAT_INTR)) device_printf(sc->dev, "unknown cause why?\n"); #ifdef ENABLE_ALART bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN); #endif return (error); } } /* Timeout Procedure. */ sc->isbusy = 0; /* Re-enable suppressed interrupt from slave part. */ bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN); if (error == EWOULDBLOCK) return (SMB_ETIMEOUT); else return (SMB_EABORT); } static int intsmb_quick(device_t dev, u_char slave, int how) { struct intsmb_softc *sc = device_get_softc(dev); int error; u_char data; data = slave; /* Quick command is part of Address, I think. */ switch(how) { case SMB_QWRITE: data &= ~LSB; break; case SMB_QREAD: data |= LSB; break; default: return (SMB_EINVAL); } INTSMB_LOCK(sc); error = intsmb_free(sc); if (error) { INTSMB_UNLOCK(sc); return (error); } bus_write_1(sc->io_res, PIIX4_SMBHSTADD, data); intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_QUICK, 0); error = intsmb_stop(sc); INTSMB_UNLOCK(sc); return (error); } static int intsmb_sendb(device_t dev, u_char slave, char byte) { struct intsmb_softc *sc = device_get_softc(dev); int error; INTSMB_LOCK(sc); error = intsmb_free(sc); if (error) { INTSMB_UNLOCK(sc); return (error); } bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB); bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, byte); intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 0); error = intsmb_stop(sc); INTSMB_UNLOCK(sc); return (error); } static int intsmb_recvb(device_t dev, u_char slave, char *byte) { struct intsmb_softc *sc = device_get_softc(dev); int error; INTSMB_LOCK(sc); error = intsmb_free(sc); if (error) { INTSMB_UNLOCK(sc); return (error); } bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB); intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 0); error = intsmb_stop(sc); if (error == 0) { #ifdef RECV_IS_IN_CMD /* * Linux SMBus stuff also troubles * Because Intel's datasheet does not make clear. */ *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTCMD); #else *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0); #endif } INTSMB_UNLOCK(sc); return (error); } static int intsmb_writeb(device_t dev, u_char slave, char cmd, char byte) { struct intsmb_softc *sc = device_get_softc(dev); int error; INTSMB_LOCK(sc); error = intsmb_free(sc); if (error) { INTSMB_UNLOCK(sc); return (error); } bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB); bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd); bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, byte); intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BDATA, 0); error = intsmb_stop(sc); INTSMB_UNLOCK(sc); return (error); } static int intsmb_writew(device_t dev, u_char slave, char cmd, short word) { struct intsmb_softc *sc = device_get_softc(dev); int error; INTSMB_LOCK(sc); error = intsmb_free(sc); if (error) { INTSMB_UNLOCK(sc); return (error); } bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB); bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd); bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, word & 0xff); bus_write_1(sc->io_res, PIIX4_SMBHSTDAT1, (word >> 8) & 0xff); intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0); error = intsmb_stop(sc); INTSMB_UNLOCK(sc); return (error); } static int intsmb_readb(device_t dev, u_char slave, char cmd, char *byte) { struct intsmb_softc *sc = device_get_softc(dev); int error; INTSMB_LOCK(sc); error = intsmb_free(sc); if (error) { INTSMB_UNLOCK(sc); return (error); } bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB); bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd); intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BDATA, 0); error = intsmb_stop(sc); if (error == 0) *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0); INTSMB_UNLOCK(sc); return (error); } static int intsmb_readw(device_t dev, u_char slave, char cmd, short *word) { struct intsmb_softc *sc = device_get_softc(dev); int error; INTSMB_LOCK(sc); error = intsmb_free(sc); if (error) { INTSMB_UNLOCK(sc); return (error); } bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB); bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd); intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0); error = intsmb_stop(sc); if (error == 0) { *word = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0); *word |= bus_read_1(sc->io_res, PIIX4_SMBHSTDAT1) << 8; } INTSMB_UNLOCK(sc); return (error); } /* * Data sheet claims that it implements all function, but also claims * that it implements 7 function and not mention PCALL. So I don't know * whether it will work. */ static int intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata) { #ifdef PROCCALL_TEST struct intsmb_softc *sc = device_get_softc(dev); int error; INTSMB_LOCK(sc); error = intsmb_free(sc); if (error) { INTSMB_UNLOCK(sc); return (error); } bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB); bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd); bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, sdata & 0xff); bus_write_1(sc->io_res, PIIX4_SMBHSTDAT1, (sdata & 0xff) >> 8); intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0); error = intsmb_stop(sc); if (error == 0) { *rdata = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0); *rdata |= bus_read_1(sc->io_res, PIIX4_SMBHSTDAT1) << 8; } INTSMB_UNLOCK(sc); return (error); #else return (SMB_ENOTSUPP); #endif } static int intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf) { struct intsmb_softc *sc = device_get_softc(dev); int error, i; if (count > SMBBLOCKTRANS_MAX || count == 0) return (SMB_EINVAL); INTSMB_LOCK(sc); error = intsmb_free(sc); if (error) { INTSMB_UNLOCK(sc); return (error); } /* Reset internal array index. */ bus_read_1(sc->io_res, PIIX4_SMBHSTCNT); bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB); bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd); for (i = 0; i < count; i++) bus_write_1(sc->io_res, PIIX4_SMBBLKDAT, buf[i]); bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, count); intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BLOCK, 0); error = intsmb_stop(sc); INTSMB_UNLOCK(sc); return (error); } static int intsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf) { struct intsmb_softc *sc = device_get_softc(dev); int error, i; u_char data, nread; if (*count > SMBBLOCKTRANS_MAX || *count == 0) return (SMB_EINVAL); INTSMB_LOCK(sc); error = intsmb_free(sc); if (error) { INTSMB_UNLOCK(sc); return (error); } /* Reset internal array index. */ bus_read_1(sc->io_res, PIIX4_SMBHSTCNT); bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB); bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd); bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, *count); intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BLOCK, 0); error = intsmb_stop(sc); if (error == 0) { nread = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0); if (nread != 0 && nread <= SMBBLOCKTRANS_MAX) { for (i = 0; i < nread; i++) { data = bus_read_1(sc->io_res, PIIX4_SMBBLKDAT); if (i < *count) buf[i] = data; } *count = nread; } else error = SMB_EBUSERR; } INTSMB_UNLOCK(sc); return (error); } static devclass_t intsmb_devclass; static device_method_t intsmb_methods[] = { /* Device interface */ DEVMETHOD(device_probe, intsmb_probe), DEVMETHOD(device_attach, intsmb_attach), DEVMETHOD(device_detach, intsmb_detach), /* SMBus interface */ DEVMETHOD(smbus_callback, intsmb_callback), DEVMETHOD(smbus_quick, intsmb_quick), DEVMETHOD(smbus_sendb, intsmb_sendb), DEVMETHOD(smbus_recvb, intsmb_recvb), DEVMETHOD(smbus_writeb, intsmb_writeb), DEVMETHOD(smbus_writew, intsmb_writew), DEVMETHOD(smbus_readb, intsmb_readb), DEVMETHOD(smbus_readw, intsmb_readw), DEVMETHOD(smbus_pcall, intsmb_pcall), DEVMETHOD(smbus_bwrite, intsmb_bwrite), DEVMETHOD(smbus_bread, intsmb_bread), DEVMETHOD_END }; static driver_t intsmb_driver = { "intsmb", intsmb_methods, sizeof(struct intsmb_softc), }; DRIVER_MODULE_ORDERED(intsmb, pci, intsmb_driver, intsmb_devclass, 0, 0, SI_ORDER_ANY); DRIVER_MODULE(smbus, intsmb, smbus_driver, smbus_devclass, 0, 0); MODULE_DEPEND(intsmb, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER); MODULE_VERSION(intsmb, 1);