Index: head/sys/conf/files =================================================================== --- head/sys/conf/files (revision 304869) +++ head/sys/conf/files (revision 304870) @@ -1,4389 +1,4396 @@ # $FreeBSD$ # # The long compile-with and dependency lines are required because of # limitations in config: backslash-newline doesn't work in strings, and # dependency lines other than the first are silently ignored. # acpi_quirks.h optional acpi \ dependency "$S/tools/acpi_quirks2h.awk $S/dev/acpica/acpi_quirks" \ compile-with "${AWK} -f $S/tools/acpi_quirks2h.awk $S/dev/acpica/acpi_quirks" \ no-obj no-implicit-rule before-depend \ clean "acpi_quirks.h" bhnd_nvram_map.h optional bhnd \ dependency "$S/dev/bhnd/tools/nvram_map_gen.sh $S/dev/bhnd/tools/nvram_map_gen.awk $S/dev/bhnd/nvram/nvram_map" \ compile-with "sh $S/dev/bhnd/tools/nvram_map_gen.sh $S/dev/bhnd/nvram/nvram_map -h" \ no-obj no-implicit-rule before-depend \ clean "bhnd_nvram_map.h" bhnd_nvram_map_data.h optional bhnd \ dependency "$S/dev/bhnd/tools/nvram_map_gen.sh $S/dev/bhnd/tools/nvram_map_gen.awk $S/dev/bhnd/nvram/nvram_map" \ compile-with "sh $S/dev/bhnd/tools/nvram_map_gen.sh $S/dev/bhnd/nvram/nvram_map -d" \ no-obj no-implicit-rule before-depend \ clean "bhnd_nvram_map_data.h" # # The 'fdt_dtb_file' target covers an actual DTB file name, which is derived # from the specified source (DTS) file: .dts -> .dtb # fdt_dtb_file optional fdt fdt_dtb_static \ compile-with "sh -c 'MACHINE=${MACHINE} $S/tools/fdt/make_dtb.sh $S ${FDT_DTS_FILE} ${.CURDIR}'" \ no-obj no-implicit-rule before-depend \ clean "${FDT_DTS_FILE:R}.dtb" fdt_static_dtb.h optional fdt fdt_dtb_static \ compile-with "sh -c 'MACHINE=${MACHINE} $S/tools/fdt/make_dtbh.sh ${FDT_DTS_FILE} ${.CURDIR}'" \ dependency "fdt_dtb_file" \ no-obj no-implicit-rule before-depend \ clean "fdt_static_dtb.h" feeder_eq_gen.h optional sound \ dependency "$S/tools/sound/feeder_eq_mkfilter.awk" \ compile-with "${AWK} -f $S/tools/sound/feeder_eq_mkfilter.awk -- ${FEEDER_EQ_PRESETS} > feeder_eq_gen.h" \ no-obj no-implicit-rule before-depend \ clean "feeder_eq_gen.h" feeder_rate_gen.h optional sound \ dependency "$S/tools/sound/feeder_rate_mkfilter.awk" \ compile-with "${AWK} -f $S/tools/sound/feeder_rate_mkfilter.awk -- ${FEEDER_RATE_PRESETS} > feeder_rate_gen.h" \ no-obj no-implicit-rule before-depend \ clean "feeder_rate_gen.h" snd_fxdiv_gen.h optional sound \ dependency "$S/tools/sound/snd_fxdiv_gen.awk" \ compile-with "${AWK} -f $S/tools/sound/snd_fxdiv_gen.awk -- > snd_fxdiv_gen.h" \ no-obj no-implicit-rule before-depend \ clean "snd_fxdiv_gen.h" miidevs.h optional miibus | mii \ dependency "$S/tools/miidevs2h.awk $S/dev/mii/miidevs" \ compile-with "${AWK} -f $S/tools/miidevs2h.awk $S/dev/mii/miidevs" \ no-obj no-implicit-rule before-depend \ clean "miidevs.h" pccarddevs.h standard \ dependency "$S/tools/pccarddevs2h.awk $S/dev/pccard/pccarddevs" \ compile-with "${AWK} -f $S/tools/pccarddevs2h.awk $S/dev/pccard/pccarddevs" \ no-obj no-implicit-rule before-depend \ clean "pccarddevs.h" kbdmuxmap.h optional kbdmux_dflt_keymap \ compile-with "kbdcontrol -P ${S:S/sys$/share/}/vt/keymaps -P ${S:S/sys$/share/}/syscons/keymaps -L ${KBDMUX_DFLT_KEYMAP} | sed -e 's/^static keymap_t.* = /static keymap_t key_map = /' -e 's/^static accentmap_t.* = /static accentmap_t accent_map = /' > kbdmuxmap.h" \ no-obj no-implicit-rule before-depend \ clean "kbdmuxmap.h" teken_state.h optional sc | vt \ dependency "$S/teken/gensequences $S/teken/sequences" \ compile-with "${AWK} -f $S/teken/gensequences $S/teken/sequences > teken_state.h" \ no-obj no-implicit-rule before-depend \ clean "teken_state.h" usbdevs.h optional usb \ dependency "$S/tools/usbdevs2h.awk $S/dev/usb/usbdevs" \ compile-with "${AWK} -f $S/tools/usbdevs2h.awk $S/dev/usb/usbdevs -h" \ no-obj no-implicit-rule before-depend \ clean "usbdevs.h" usbdevs_data.h optional usb \ dependency "$S/tools/usbdevs2h.awk $S/dev/usb/usbdevs" \ compile-with "${AWK} -f $S/tools/usbdevs2h.awk $S/dev/usb/usbdevs -d" \ no-obj no-implicit-rule before-depend \ clean "usbdevs_data.h" cam/cam.c optional scbus cam/cam_compat.c optional scbus cam/cam_iosched.c optional scbus cam/cam_periph.c optional scbus cam/cam_queue.c optional scbus cam/cam_sim.c optional scbus cam/cam_xpt.c optional scbus cam/ata/ata_all.c optional scbus cam/ata/ata_xpt.c optional scbus cam/ata/ata_pmp.c optional scbus cam/nvme/nvme_all.c optional scbus nvme !nvd cam/nvme/nvme_da.c optional scbus nvme da !nvd cam/nvme/nvme_xpt.c optional scbus nvme !nvd cam/scsi/scsi_xpt.c optional scbus cam/scsi/scsi_all.c optional scbus cam/scsi/scsi_cd.c optional cd cam/scsi/scsi_ch.c optional ch cam/ata/ata_da.c optional ada | da cam/ctl/ctl.c optional ctl cam/ctl/ctl_backend.c optional ctl cam/ctl/ctl_backend_block.c optional ctl cam/ctl/ctl_backend_ramdisk.c optional ctl cam/ctl/ctl_cmd_table.c optional ctl cam/ctl/ctl_frontend.c optional ctl cam/ctl/ctl_frontend_cam_sim.c optional ctl cam/ctl/ctl_frontend_ioctl.c optional ctl cam/ctl/ctl_frontend_iscsi.c optional ctl cam/ctl/ctl_ha.c optional ctl cam/ctl/ctl_scsi_all.c optional ctl cam/ctl/ctl_tpc.c optional ctl cam/ctl/ctl_tpc_local.c optional ctl cam/ctl/ctl_error.c optional ctl cam/ctl/ctl_util.c optional ctl cam/ctl/scsi_ctl.c optional ctl cam/scsi/scsi_da.c optional da cam/scsi/scsi_low.c optional ct | ncv | nsp | stg cam/scsi/scsi_pass.c optional pass cam/scsi/scsi_pt.c optional pt cam/scsi/scsi_sa.c optional sa cam/scsi/scsi_enc.c optional ses cam/scsi/scsi_enc_ses.c optional ses cam/scsi/scsi_enc_safte.c optional ses cam/scsi/scsi_sg.c optional sg cam/scsi/scsi_targ_bh.c optional targbh cam/scsi/scsi_target.c optional targ cam/scsi/smp_all.c optional scbus # shared between zfs and dtrace cddl/compat/opensolaris/kern/opensolaris.c optional zfs | dtrace compile-with "${CDDL_C}" cddl/compat/opensolaris/kern/opensolaris_cmn_err.c optional zfs | dtrace compile-with "${CDDL_C}" cddl/compat/opensolaris/kern/opensolaris_kmem.c optional zfs | dtrace compile-with "${CDDL_C}" cddl/compat/opensolaris/kern/opensolaris_misc.c optional zfs | dtrace compile-with "${CDDL_C}" cddl/compat/opensolaris/kern/opensolaris_sunddi.c optional zfs | dtrace compile-with "${CDDL_C}" cddl/compat/opensolaris/kern/opensolaris_taskq.c optional zfs | dtrace compile-with "${CDDL_C}" # zfs specific cddl/compat/opensolaris/kern/opensolaris_acl.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_dtrace.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_kobj.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_kstat.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_lookup.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_policy.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_string.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_sysevent.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_uio.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_vfs.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_vm.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_zone.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/acl/acl_common.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/avl/avl.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/nvpair/opensolaris_fnvpair.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/nvpair/opensolaris_nvpair.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/nvpair/opensolaris_nvpair_alloc_fixed.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/unicode/u8_textprep.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zfeature_common.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zfs_comutil.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zfs_deleg.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zfs_fletcher.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zfs_ioctl_compat.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zfs_namecheck.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zfs_prop.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zpool_prop.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zprop_common.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/gfs.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/vnode.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/blkptr.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/bplist.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/bpobj.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/bptree.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/bqueue.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dbuf.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/ddt.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/ddt_zap.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_diff.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_object.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_objset.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_send.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_traverse.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_tx.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_zfetch.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dnode.c optional zfs compile-with "${ZFS_C}" \ warning "kernel contains CDDL licensed ZFS filesystem" cddl/contrib/opensolaris/uts/common/fs/zfs/dnode_sync.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_bookmark.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_dataset.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_deadlist.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_deleg.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_destroy.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_dir.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_pool.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_prop.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_scan.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_userhold.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_synctask.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/gzip.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lz4.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lzjb.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/metaslab.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/multilist.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/range_tree.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/refcount.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/rrwlock.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/sa.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/sha256.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/skein_zfs.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/spa.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/spa_config.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/spa_errlog.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/spa_history.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/spa_misc.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/space_map.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/space_reftree.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/trim_map.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/txg.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/uberblock.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/unique.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_cache.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_file.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_geom.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_label.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_mirror.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_missing.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_queue.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_raidz.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_root.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zap.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zap_leaf.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zap_micro.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfeature.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_acl.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_byteswap.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ctldir.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_debug.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_dir.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_fm.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_fuid.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_log.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_onexit.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_replay.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_rlock.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_sa.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vfsops.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_znode.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zil.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zio.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zio_checksum.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zio_compress.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zio_inject.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zle.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zrlock.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zvol.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/os/callb.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/os/fm.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/os/list.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/os/nvpair_alloc_system.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/adler32.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/deflate.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/inffast.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/inflate.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/inftrees.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/opensolaris_crc32.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/trees.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/zmod.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/zmod_subr.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/zutil.c optional zfs compile-with "${ZFS_C}" # dtrace specific cddl/contrib/opensolaris/uts/common/dtrace/dtrace.c optional dtrace compile-with "${DTRACE_C}" \ warning "kernel contains CDDL licensed DTRACE" cddl/dev/dtmalloc/dtmalloc.c optional dtmalloc | dtraceall compile-with "${CDDL_C}" cddl/dev/profile/profile.c optional dtrace_profile | dtraceall compile-with "${CDDL_C}" cddl/dev/sdt/sdt.c optional dtrace_sdt | dtraceall compile-with "${CDDL_C}" cddl/dev/fbt/fbt.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" cddl/dev/systrace/systrace.c optional dtrace_systrace | dtraceall compile-with "${CDDL_C}" cddl/dev/prototype.c optional dtrace_prototype | dtraceall compile-with "${CDDL_C}" fs/nfsclient/nfs_clkdtrace.c optional dtnfscl nfscl | dtraceall nfscl compile-with "${CDDL_C}" compat/cloudabi/cloudabi_clock.c optional compat_cloudabi32 | compat_cloudabi64 compat/cloudabi/cloudabi_errno.c optional compat_cloudabi32 | compat_cloudabi64 compat/cloudabi/cloudabi_fd.c optional compat_cloudabi32 | compat_cloudabi64 compat/cloudabi/cloudabi_file.c optional compat_cloudabi32 | compat_cloudabi64 compat/cloudabi/cloudabi_futex.c optional compat_cloudabi32 | compat_cloudabi64 compat/cloudabi/cloudabi_mem.c optional compat_cloudabi32 | compat_cloudabi64 compat/cloudabi/cloudabi_proc.c optional compat_cloudabi32 | compat_cloudabi64 compat/cloudabi/cloudabi_random.c optional compat_cloudabi32 | compat_cloudabi64 compat/cloudabi/cloudabi_sock.c optional compat_cloudabi32 | compat_cloudabi64 compat/cloudabi/cloudabi_thread.c optional compat_cloudabi32 | compat_cloudabi64 compat/cloudabi/cloudabi_vdso.c optional compat_cloudabi32 | compat_cloudabi64 compat/cloudabi32/cloudabi32_fd.c optional compat_cloudabi32 compat/cloudabi32/cloudabi32_module.c optional compat_cloudabi32 compat/cloudabi32/cloudabi32_poll.c optional compat_cloudabi32 compat/cloudabi32/cloudabi32_sock.c optional compat_cloudabi32 compat/cloudabi32/cloudabi32_syscalls.c optional compat_cloudabi32 compat/cloudabi32/cloudabi32_sysent.c optional compat_cloudabi32 compat/cloudabi32/cloudabi32_thread.c optional compat_cloudabi32 compat/cloudabi64/cloudabi64_fd.c optional compat_cloudabi64 compat/cloudabi64/cloudabi64_module.c optional compat_cloudabi64 compat/cloudabi64/cloudabi64_poll.c optional compat_cloudabi64 compat/cloudabi64/cloudabi64_sock.c optional compat_cloudabi64 compat/cloudabi64/cloudabi64_syscalls.c optional compat_cloudabi64 compat/cloudabi64/cloudabi64_sysent.c optional compat_cloudabi64 compat/cloudabi64/cloudabi64_thread.c optional compat_cloudabi64 compat/freebsd32/freebsd32_capability.c optional compat_freebsd32 compat/freebsd32/freebsd32_ioctl.c optional compat_freebsd32 compat/freebsd32/freebsd32_misc.c optional compat_freebsd32 compat/freebsd32/freebsd32_syscalls.c optional compat_freebsd32 compat/freebsd32/freebsd32_sysent.c optional compat_freebsd32 contrib/dev/acpica/common/ahids.c optional acpi acpi_debug contrib/dev/acpica/common/ahuuids.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbcmds.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbconvert.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbdisply.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbexec.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbhistry.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbinput.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbmethod.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbnames.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbobject.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbstats.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbtest.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbutils.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbxface.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmbuffer.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmcstyle.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmdeferred.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmnames.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmopcode.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmresrc.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmresrcl.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmresrcl2.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmresrcs.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmutils.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmwalk.c optional acpi acpi_debug contrib/dev/acpica/components/dispatcher/dsargs.c optional acpi contrib/dev/acpica/components/dispatcher/dscontrol.c optional acpi contrib/dev/acpica/components/dispatcher/dsdebug.c optional acpi contrib/dev/acpica/components/dispatcher/dsfield.c optional acpi contrib/dev/acpica/components/dispatcher/dsinit.c optional acpi contrib/dev/acpica/components/dispatcher/dsmethod.c optional acpi contrib/dev/acpica/components/dispatcher/dsmthdat.c optional acpi contrib/dev/acpica/components/dispatcher/dsobject.c optional acpi contrib/dev/acpica/components/dispatcher/dsopcode.c optional acpi contrib/dev/acpica/components/dispatcher/dsutils.c optional acpi contrib/dev/acpica/components/dispatcher/dswexec.c optional acpi contrib/dev/acpica/components/dispatcher/dswload.c optional acpi contrib/dev/acpica/components/dispatcher/dswload2.c optional acpi contrib/dev/acpica/components/dispatcher/dswscope.c optional acpi contrib/dev/acpica/components/dispatcher/dswstate.c optional acpi contrib/dev/acpica/components/events/evevent.c optional acpi contrib/dev/acpica/components/events/evglock.c optional acpi contrib/dev/acpica/components/events/evgpe.c optional acpi contrib/dev/acpica/components/events/evgpeblk.c optional acpi contrib/dev/acpica/components/events/evgpeinit.c optional acpi contrib/dev/acpica/components/events/evgpeutil.c optional acpi contrib/dev/acpica/components/events/evhandler.c optional acpi contrib/dev/acpica/components/events/evmisc.c optional acpi contrib/dev/acpica/components/events/evregion.c optional acpi contrib/dev/acpica/components/events/evrgnini.c optional acpi contrib/dev/acpica/components/events/evsci.c optional acpi contrib/dev/acpica/components/events/evxface.c optional acpi contrib/dev/acpica/components/events/evxfevnt.c optional acpi contrib/dev/acpica/components/events/evxfgpe.c optional acpi contrib/dev/acpica/components/events/evxfregn.c optional acpi contrib/dev/acpica/components/executer/exconcat.c optional acpi contrib/dev/acpica/components/executer/exconfig.c optional acpi contrib/dev/acpica/components/executer/exconvrt.c optional acpi contrib/dev/acpica/components/executer/excreate.c optional acpi contrib/dev/acpica/components/executer/exdebug.c optional acpi contrib/dev/acpica/components/executer/exdump.c optional acpi contrib/dev/acpica/components/executer/exfield.c optional acpi contrib/dev/acpica/components/executer/exfldio.c optional acpi contrib/dev/acpica/components/executer/exmisc.c optional acpi contrib/dev/acpica/components/executer/exmutex.c optional acpi contrib/dev/acpica/components/executer/exnames.c optional acpi contrib/dev/acpica/components/executer/exoparg1.c optional acpi contrib/dev/acpica/components/executer/exoparg2.c optional acpi contrib/dev/acpica/components/executer/exoparg3.c optional acpi contrib/dev/acpica/components/executer/exoparg6.c optional acpi contrib/dev/acpica/components/executer/exprep.c optional acpi contrib/dev/acpica/components/executer/exregion.c optional acpi contrib/dev/acpica/components/executer/exresnte.c optional acpi contrib/dev/acpica/components/executer/exresolv.c optional acpi contrib/dev/acpica/components/executer/exresop.c optional acpi contrib/dev/acpica/components/executer/exstore.c optional acpi contrib/dev/acpica/components/executer/exstoren.c optional acpi contrib/dev/acpica/components/executer/exstorob.c optional acpi contrib/dev/acpica/components/executer/exsystem.c optional acpi contrib/dev/acpica/components/executer/extrace.c optional acpi contrib/dev/acpica/components/executer/exutils.c optional acpi contrib/dev/acpica/components/hardware/hwacpi.c optional acpi contrib/dev/acpica/components/hardware/hwesleep.c optional acpi contrib/dev/acpica/components/hardware/hwgpe.c optional acpi contrib/dev/acpica/components/hardware/hwpci.c optional acpi contrib/dev/acpica/components/hardware/hwregs.c optional acpi contrib/dev/acpica/components/hardware/hwsleep.c optional acpi contrib/dev/acpica/components/hardware/hwtimer.c optional acpi contrib/dev/acpica/components/hardware/hwvalid.c optional acpi contrib/dev/acpica/components/hardware/hwxface.c optional acpi contrib/dev/acpica/components/hardware/hwxfsleep.c optional acpi contrib/dev/acpica/components/namespace/nsaccess.c optional acpi contrib/dev/acpica/components/namespace/nsalloc.c optional acpi contrib/dev/acpica/components/namespace/nsarguments.c optional acpi contrib/dev/acpica/components/namespace/nsconvert.c optional acpi contrib/dev/acpica/components/namespace/nsdump.c optional acpi contrib/dev/acpica/components/namespace/nseval.c optional acpi contrib/dev/acpica/components/namespace/nsinit.c optional acpi contrib/dev/acpica/components/namespace/nsload.c optional acpi contrib/dev/acpica/components/namespace/nsnames.c optional acpi contrib/dev/acpica/components/namespace/nsobject.c optional acpi contrib/dev/acpica/components/namespace/nsparse.c optional acpi contrib/dev/acpica/components/namespace/nspredef.c optional acpi contrib/dev/acpica/components/namespace/nsprepkg.c optional acpi contrib/dev/acpica/components/namespace/nsrepair.c optional acpi contrib/dev/acpica/components/namespace/nsrepair2.c optional acpi contrib/dev/acpica/components/namespace/nssearch.c optional acpi contrib/dev/acpica/components/namespace/nsutils.c optional acpi contrib/dev/acpica/components/namespace/nswalk.c optional acpi contrib/dev/acpica/components/namespace/nsxfeval.c optional acpi contrib/dev/acpica/components/namespace/nsxfname.c optional acpi contrib/dev/acpica/components/namespace/nsxfobj.c optional acpi contrib/dev/acpica/components/parser/psargs.c optional acpi contrib/dev/acpica/components/parser/psloop.c optional acpi contrib/dev/acpica/components/parser/psobject.c optional acpi contrib/dev/acpica/components/parser/psopcode.c optional acpi contrib/dev/acpica/components/parser/psopinfo.c optional acpi contrib/dev/acpica/components/parser/psparse.c optional acpi contrib/dev/acpica/components/parser/psscope.c optional acpi contrib/dev/acpica/components/parser/pstree.c optional acpi contrib/dev/acpica/components/parser/psutils.c optional acpi contrib/dev/acpica/components/parser/pswalk.c optional acpi contrib/dev/acpica/components/parser/psxface.c optional acpi contrib/dev/acpica/components/resources/rsaddr.c optional acpi contrib/dev/acpica/components/resources/rscalc.c optional acpi contrib/dev/acpica/components/resources/rscreate.c optional acpi contrib/dev/acpica/components/resources/rsdump.c optional acpi acpi_debug contrib/dev/acpica/components/resources/rsdumpinfo.c optional acpi contrib/dev/acpica/components/resources/rsinfo.c optional acpi contrib/dev/acpica/components/resources/rsio.c optional acpi contrib/dev/acpica/components/resources/rsirq.c optional acpi contrib/dev/acpica/components/resources/rslist.c optional acpi contrib/dev/acpica/components/resources/rsmemory.c optional acpi contrib/dev/acpica/components/resources/rsmisc.c optional acpi contrib/dev/acpica/components/resources/rsserial.c optional acpi contrib/dev/acpica/components/resources/rsutils.c optional acpi contrib/dev/acpica/components/resources/rsxface.c optional acpi contrib/dev/acpica/components/tables/tbdata.c optional acpi contrib/dev/acpica/components/tables/tbfadt.c optional acpi contrib/dev/acpica/components/tables/tbfind.c optional acpi contrib/dev/acpica/components/tables/tbinstal.c optional acpi contrib/dev/acpica/components/tables/tbprint.c optional acpi contrib/dev/acpica/components/tables/tbutils.c optional acpi contrib/dev/acpica/components/tables/tbxface.c optional acpi contrib/dev/acpica/components/tables/tbxfload.c optional acpi contrib/dev/acpica/components/tables/tbxfroot.c optional acpi contrib/dev/acpica/components/utilities/utaddress.c optional acpi contrib/dev/acpica/components/utilities/utalloc.c optional acpi contrib/dev/acpica/components/utilities/utascii.c optional acpi contrib/dev/acpica/components/utilities/utbuffer.c optional acpi contrib/dev/acpica/components/utilities/utcache.c optional acpi contrib/dev/acpica/components/utilities/utcopy.c optional acpi contrib/dev/acpica/components/utilities/utdebug.c optional acpi contrib/dev/acpica/components/utilities/utdecode.c optional acpi contrib/dev/acpica/components/utilities/utdelete.c optional acpi contrib/dev/acpica/components/utilities/uterror.c optional acpi contrib/dev/acpica/components/utilities/uteval.c optional acpi contrib/dev/acpica/components/utilities/utexcep.c optional acpi contrib/dev/acpica/components/utilities/utglobal.c optional acpi contrib/dev/acpica/components/utilities/uthex.c optional acpi contrib/dev/acpica/components/utilities/utids.c optional acpi contrib/dev/acpica/components/utilities/utinit.c optional acpi contrib/dev/acpica/components/utilities/utlock.c optional acpi contrib/dev/acpica/components/utilities/utmath.c optional acpi contrib/dev/acpica/components/utilities/utmisc.c optional acpi contrib/dev/acpica/components/utilities/utmutex.c optional acpi contrib/dev/acpica/components/utilities/utnonansi.c optional acpi contrib/dev/acpica/components/utilities/utobject.c optional acpi contrib/dev/acpica/components/utilities/utosi.c optional acpi contrib/dev/acpica/components/utilities/utownerid.c optional acpi contrib/dev/acpica/components/utilities/utpredef.c optional acpi contrib/dev/acpica/components/utilities/utresrc.c optional acpi contrib/dev/acpica/components/utilities/utstate.c optional acpi contrib/dev/acpica/components/utilities/utstring.c optional acpi contrib/dev/acpica/components/utilities/utuuid.c optional acpi acpi_debug contrib/dev/acpica/components/utilities/utxface.c optional acpi contrib/dev/acpica/components/utilities/utxferror.c optional acpi contrib/dev/acpica/components/utilities/utxfinit.c optional acpi #contrib/dev/acpica/components/utilities/utxfmutex.c optional acpi contrib/ipfilter/netinet/fil.c optional ipfilter inet \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_auth.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_fil_freebsd.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_frag.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_log.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_nat.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_proxy.c optional ipfilter inet \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_state.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_lookup.c optional ipfilter inet \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN} -Wno-unused -Wno-error -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_pool.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_htable.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_sync.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/mlfk_ipl.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_nat6.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_rules.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_scan.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_dstlist.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/radix_ipf.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/libfdt/fdt.c optional fdt contrib/libfdt/fdt_ro.c optional fdt contrib/libfdt/fdt_rw.c optional fdt contrib/libfdt/fdt_strerror.c optional fdt contrib/libfdt/fdt_sw.c optional fdt contrib/libfdt/fdt_wip.c optional fdt contrib/libnv/dnvlist.c standard contrib/libnv/nvlist.c standard contrib/libnv/nvpair.c standard contrib/ngatm/netnatm/api/cc_conn.c optional ngatm_ccatm \ compile-with "${NORMAL_C_NOWERROR} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/cc_data.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/cc_dump.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/cc_port.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/cc_sig.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/cc_user.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/unisap.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/misc/straddr.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/misc/unimsg_common.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/msg/traffic.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/msg/uni_ie.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/msg/uni_msg.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/saal/saal_sscfu.c optional ngatm_sscfu \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/saal/saal_sscop.c optional ngatm_sscop \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_call.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_coord.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_party.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_print.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_reset.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_uni.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_unimsgcpy.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_verify.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" crypto/blowfish/bf_ecb.c optional ipsec crypto/blowfish/bf_skey.c optional crypto | ipsec crypto/camellia/camellia.c optional crypto | ipsec crypto/camellia/camellia-api.c optional crypto | ipsec crypto/des/des_ecb.c optional crypto | ipsec | netsmb crypto/des/des_setkey.c optional crypto | ipsec | netsmb crypto/rc4/rc4.c optional netgraph_mppc_encryption | kgssapi crypto/rijndael/rijndael-alg-fst.c optional crypto | geom_bde | \ ipsec | random !random_loadable | wlan_ccmp crypto/rijndael/rijndael-api-fst.c optional geom_bde | random !random_loadable crypto/rijndael/rijndael-api.c optional crypto | ipsec | wlan_ccmp crypto/sha1.c optional carp | crypto | ipsec | \ netgraph_mppc_encryption | sctp crypto/sha2/sha256c.c optional crypto | geom_bde | ipsec | random !random_loadable | \ sctp | zfs crypto/sha2/sha512c.c optional crypto | geom_bde | ipsec | zfs crypto/skein/skein.c optional crypto | zfs crypto/skein/skein_block.c optional crypto | zfs crypto/siphash/siphash.c optional inet | inet6 crypto/siphash/siphash_test.c optional inet | inet6 ddb/db_access.c optional ddb ddb/db_break.c optional ddb ddb/db_capture.c optional ddb ddb/db_command.c optional ddb ddb/db_examine.c optional ddb ddb/db_expr.c optional ddb ddb/db_input.c optional ddb ddb/db_lex.c optional ddb ddb/db_main.c optional ddb ddb/db_output.c optional ddb ddb/db_print.c optional ddb ddb/db_ps.c optional ddb ddb/db_run.c optional ddb ddb/db_script.c optional ddb ddb/db_sym.c optional ddb ddb/db_thread.c optional ddb ddb/db_textdump.c optional ddb ddb/db_variables.c optional ddb ddb/db_watch.c optional ddb ddb/db_write_cmd.c optional ddb dev/aac/aac.c optional aac dev/aac/aac_cam.c optional aacp aac dev/aac/aac_debug.c optional aac dev/aac/aac_disk.c optional aac dev/aac/aac_linux.c optional aac compat_linux dev/aac/aac_pci.c optional aac pci dev/aacraid/aacraid.c optional aacraid dev/aacraid/aacraid_cam.c optional aacraid scbus dev/aacraid/aacraid_debug.c optional aacraid dev/aacraid/aacraid_linux.c optional aacraid compat_linux dev/aacraid/aacraid_pci.c optional aacraid pci dev/acpi_support/acpi_wmi.c optional acpi_wmi acpi dev/acpi_support/acpi_asus.c optional acpi_asus acpi dev/acpi_support/acpi_asus_wmi.c optional acpi_asus_wmi acpi dev/acpi_support/acpi_fujitsu.c optional acpi_fujitsu acpi dev/acpi_support/acpi_hp.c optional acpi_hp acpi dev/acpi_support/acpi_ibm.c optional acpi_ibm acpi dev/acpi_support/acpi_panasonic.c optional acpi_panasonic acpi dev/acpi_support/acpi_sony.c optional acpi_sony acpi dev/acpi_support/acpi_toshiba.c optional acpi_toshiba acpi dev/acpi_support/atk0110.c optional aibs acpi dev/acpica/Osd/OsdDebug.c optional acpi dev/acpica/Osd/OsdHardware.c optional acpi dev/acpica/Osd/OsdInterrupt.c optional acpi dev/acpica/Osd/OsdMemory.c optional acpi dev/acpica/Osd/OsdSchedule.c optional acpi dev/acpica/Osd/OsdStream.c optional acpi dev/acpica/Osd/OsdSynch.c optional acpi dev/acpica/Osd/OsdTable.c optional acpi dev/acpica/acpi.c optional acpi dev/acpica/acpi_acad.c optional acpi dev/acpica/acpi_battery.c optional acpi dev/acpica/acpi_button.c optional acpi dev/acpica/acpi_cmbat.c optional acpi dev/acpica/acpi_cpu.c optional acpi dev/acpica/acpi_ec.c optional acpi dev/acpica/acpi_isab.c optional acpi isa dev/acpica/acpi_lid.c optional acpi dev/acpica/acpi_package.c optional acpi dev/acpica/acpi_pci.c optional acpi pci dev/acpica/acpi_pci_link.c optional acpi pci dev/acpica/acpi_pcib.c optional acpi pci dev/acpica/acpi_pcib_acpi.c optional acpi pci dev/acpica/acpi_pcib_pci.c optional acpi pci dev/acpica/acpi_perf.c optional acpi dev/acpica/acpi_powerres.c optional acpi dev/acpica/acpi_quirk.c optional acpi dev/acpica/acpi_resource.c optional acpi dev/acpica/acpi_smbat.c optional acpi dev/acpica/acpi_thermal.c optional acpi dev/acpica/acpi_throttle.c optional acpi dev/acpica/acpi_timer.c optional acpi dev/acpica/acpi_video.c optional acpi_video acpi dev/acpica/acpi_dock.c optional acpi_dock acpi dev/adlink/adlink.c optional adlink dev/advansys/adv_eisa.c optional adv eisa dev/advansys/adv_pci.c optional adv pci dev/advansys/advansys.c optional adv dev/advansys/advlib.c optional adv dev/advansys/advmcode.c optional adv dev/advansys/adw_pci.c optional adw pci dev/advansys/adwcam.c optional adw dev/advansys/adwlib.c optional adw dev/advansys/adwmcode.c optional adw dev/ae/if_ae.c optional ae pci dev/age/if_age.c optional age pci dev/agp/agp.c optional agp pci dev/agp/agp_if.m optional agp pci dev/aha/aha.c optional aha dev/aha/aha_isa.c optional aha isa dev/aha/aha_mca.c optional aha mca dev/ahb/ahb.c optional ahb eisa dev/ahci/ahci.c optional ahci dev/ahci/ahciem.c optional ahci dev/ahci/ahci_pci.c optional ahci pci dev/aic/aic.c optional aic dev/aic/aic_pccard.c optional aic pccard dev/aic7xxx/ahc_eisa.c optional ahc eisa dev/aic7xxx/ahc_isa.c optional ahc isa dev/aic7xxx/ahc_pci.c optional ahc pci \ compile-with "${NORMAL_C} ${NO_WCONSTANT_CONVERSION}" dev/aic7xxx/ahd_pci.c optional ahd pci \ compile-with "${NORMAL_C} ${NO_WCONSTANT_CONVERSION}" dev/aic7xxx/aic7770.c optional ahc dev/aic7xxx/aic79xx.c optional ahd pci dev/aic7xxx/aic79xx_osm.c optional ahd pci dev/aic7xxx/aic79xx_pci.c optional ahd pci dev/aic7xxx/aic79xx_reg_print.c optional ahd pci ahd_reg_pretty_print dev/aic7xxx/aic7xxx.c optional ahc dev/aic7xxx/aic7xxx_93cx6.c optional ahc dev/aic7xxx/aic7xxx_osm.c optional ahc dev/aic7xxx/aic7xxx_pci.c optional ahc pci dev/aic7xxx/aic7xxx_reg_print.c optional ahc ahc_reg_pretty_print dev/alc/if_alc.c optional alc pci dev/ale/if_ale.c optional ale pci dev/alpm/alpm.c optional alpm pci dev/altera/avgen/altera_avgen.c optional altera_avgen dev/altera/avgen/altera_avgen_fdt.c optional altera_avgen fdt dev/altera/avgen/altera_avgen_nexus.c optional altera_avgen dev/altera/sdcard/altera_sdcard.c optional altera_sdcard dev/altera/sdcard/altera_sdcard_disk.c optional altera_sdcard dev/altera/sdcard/altera_sdcard_io.c optional altera_sdcard dev/altera/sdcard/altera_sdcard_fdt.c optional altera_sdcard fdt dev/altera/sdcard/altera_sdcard_nexus.c optional altera_sdcard dev/altera/pio/pio.c optional altera_pio dev/altera/pio/pio_if.m optional altera_pio dev/amdpm/amdpm.c optional amdpm pci | nfpm pci dev/amdsmb/amdsmb.c optional amdsmb pci dev/amr/amr.c optional amr dev/amr/amr_cam.c optional amrp amr dev/amr/amr_disk.c optional amr dev/amr/amr_linux.c optional amr compat_linux dev/amr/amr_pci.c optional amr pci dev/an/if_an.c optional an dev/an/if_an_isa.c optional an isa dev/an/if_an_pccard.c optional an pccard dev/an/if_an_pci.c optional an pci # dev/ata/ata_if.m optional ata | atacore dev/ata/ata-all.c optional ata | atacore dev/ata/ata-dma.c optional ata | atacore dev/ata/ata-lowlevel.c optional ata | atacore dev/ata/ata-sata.c optional ata | atacore dev/ata/ata-card.c optional ata pccard | atapccard dev/ata/ata-cbus.c optional ata pc98 | atapc98 dev/ata/ata-isa.c optional ata isa | ataisa dev/ata/ata-pci.c optional ata pci | atapci dev/ata/chipsets/ata-acard.c optional ata pci | ataacard dev/ata/chipsets/ata-acerlabs.c optional ata pci | ataacerlabs dev/ata/chipsets/ata-amd.c optional ata pci | ataamd dev/ata/chipsets/ata-ati.c optional ata pci | ataati dev/ata/chipsets/ata-cenatek.c optional ata pci | atacenatek dev/ata/chipsets/ata-cypress.c optional ata pci | atacypress dev/ata/chipsets/ata-cyrix.c optional ata pci | atacyrix dev/ata/chipsets/ata-highpoint.c optional ata pci | atahighpoint dev/ata/chipsets/ata-intel.c optional ata pci | ataintel dev/ata/chipsets/ata-ite.c optional ata pci | ataite dev/ata/chipsets/ata-jmicron.c optional ata pci | atajmicron dev/ata/chipsets/ata-marvell.c optional ata pci | atamarvell dev/ata/chipsets/ata-micron.c optional ata pci | atamicron dev/ata/chipsets/ata-national.c optional ata pci | atanational dev/ata/chipsets/ata-netcell.c optional ata pci | atanetcell dev/ata/chipsets/ata-nvidia.c optional ata pci | atanvidia dev/ata/chipsets/ata-promise.c optional ata pci | atapromise dev/ata/chipsets/ata-serverworks.c optional ata pci | ataserverworks dev/ata/chipsets/ata-siliconimage.c optional ata pci | atasiliconimage | ataati dev/ata/chipsets/ata-sis.c optional ata pci | atasis dev/ata/chipsets/ata-via.c optional ata pci | atavia # dev/ath/if_ath_pci.c optional ath_pci pci \ compile-with "${NORMAL_C} -I$S/dev/ath" # dev/ath/if_ath_ahb.c optional ath_ahb \ compile-with "${NORMAL_C} -I$S/dev/ath" # dev/ath/if_ath.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_alq.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_beacon.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_btcoex.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_btcoex_mci.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_debug.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_descdma.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_keycache.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_ioctl.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_led.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_lna_div.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_tx.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_tx_edma.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_tx_ht.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_tdma.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_sysctl.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_rx.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_rx_edma.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_spectral.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ah_osdep.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" # dev/ath/ath_hal/ah.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_eeprom_v1.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_eeprom_v3.c optional ath_hal | ath_ar5211 | ath_ar5212 \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_eeprom_v14.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_eeprom_v4k.c \ optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_eeprom_9287.c \ optional ath_hal | ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_regdomain.c optional ath \ compile-with "${NORMAL_C} ${NO_WSHIFT_COUNT_NEGATIVE} ${NO_WSHIFT_COUNT_OVERFLOW} -I$S/dev/ath" # ar5210 dev/ath/ath_hal/ar5210/ar5210_attach.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_beacon.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_interrupts.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_keycache.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_misc.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_phy.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_power.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_recv.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_reset.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_xmit.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar5211 dev/ath/ath_hal/ar5211/ar5211_attach.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_beacon.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_interrupts.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_keycache.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_misc.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_phy.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_power.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_recv.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_reset.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_xmit.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar5212 dev/ath/ath_hal/ar5212/ar5212_ani.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_attach.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_beacon.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_eeprom.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_gpio.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_interrupts.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_keycache.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_misc.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_phy.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_power.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_recv.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_reset.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_rfgain.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_xmit.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar5416 (depends on ar5212) dev/ath/ath_hal/ar5416/ar5416_ani.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_attach.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_beacon.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_btcoex.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_cal.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_cal_iq.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_eeprom.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_gpio.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_interrupts.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_keycache.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_misc.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_phy.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_power.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_radar.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_recv.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_reset.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_spectral.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_xmit.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar9130 (depends upon ar5416) - also requires AH_SUPPORT_AR9130 # # Since this is an embedded MAC SoC, there's no need to compile it into the # default HAL. dev/ath/ath_hal/ar9001/ar9130_attach.c optional ath_ar9130 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9001/ar9130_phy.c optional ath_ar9130 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9001/ar9130_eeprom.c optional ath_ar9130 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar9160 (depends on ar5416) dev/ath/ath_hal/ar9001/ar9160_attach.c optional ath_hal | ath_ar9160 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar9280 (depends on ar5416) dev/ath/ath_hal/ar9002/ar9280_attach.c optional ath_hal | ath_ar9280 | \ ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9280_olc.c optional ath_hal | ath_ar9280 | \ ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar9285 (depends on ar5416 and ar9280) dev/ath/ath_hal/ar9002/ar9285_attach.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9285_btcoex.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9285_reset.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9285_cal.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9285_phy.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9285_diversity.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar9287 (depends on ar5416) dev/ath/ath_hal/ar9002/ar9287_attach.c optional ath_hal | ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9287_reset.c optional ath_hal | ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9287_cal.c optional ath_hal | ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9287_olc.c optional ath_hal | ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar9300 contrib/dev/ath/ath_hal/ar9300/ar9300_ani.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_attach.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_beacon.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_eeprom.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal ${NO_WCONSTANT_CONVERSION}" contrib/dev/ath/ath_hal/ar9300/ar9300_freebsd.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_gpio.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_interrupts.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_keycache.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_mci.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_misc.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_paprd.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_phy.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_power.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_radar.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_radio.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_recv.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_recv_ds.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_reset.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal ${NO_WSOMETIMES_UNINITIALIZED} -Wno-unused-function" contrib/dev/ath/ath_hal/ar9300/ar9300_stub.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_stub_funcs.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_spectral.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_timer.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_xmit.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_xmit_ds.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" # rf backends dev/ath/ath_hal/ar5212/ar2316.c optional ath_rf2316 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar2317.c optional ath_rf2317 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar2413.c optional ath_hal | ath_rf2413 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar2425.c optional ath_hal | ath_rf2425 | ath_rf2417 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5111.c optional ath_hal | ath_rf5111 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5112.c optional ath_hal | ath_rf5112 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5413.c optional ath_hal | ath_rf5413 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar2133.c optional ath_hal | ath_ar5416 | \ ath_ar9130 | ath_ar9160 | ath_ar9280 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9280.c optional ath_hal | ath_ar9280 | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9285.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9287.c optional ath_hal | ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ath rate control algorithms dev/ath/ath_rate/amrr/amrr.c optional ath_rate_amrr \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_rate/onoe/onoe.c optional ath_rate_onoe \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_rate/sample/sample.c optional ath_rate_sample \ compile-with "${NORMAL_C} -I$S/dev/ath" # ath DFS modules dev/ath/ath_dfs/null/dfs_null.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" # dev/bce/if_bce.c optional bce dev/bfe/if_bfe.c optional bfe dev/bge/if_bge.c optional bge dev/bhnd/bhnd.c optional bhnd dev/bhnd/bhnd_nexus.c optional bhnd siba_nexus | \ bhnd bcma_nexus dev/bhnd/bhnd_subr.c optional bhnd dev/bhnd/bhnd_bus_if.m optional bhnd dev/bhnd/bhndb/bhnd_bhndb.c optional bhndb bhnd dev/bhnd/bhndb/bhndb.c optional bhndb bhnd dev/bhnd/bhndb/bhndb_bus_if.m optional bhndb bhnd dev/bhnd/bhndb/bhndb_hwdata.c optional bhndb bhnd dev/bhnd/bhndb/bhndb_if.m optional bhndb bhnd dev/bhnd/bhndb/bhndb_pci.c optional bhndb bhnd pci dev/bhnd/bhndb/bhndb_pci_hwdata.c optional bhndb bhnd pci dev/bhnd/bhndb/bhndb_pci_sprom.c optional bhndb bhnd pci dev/bhnd/bhndb/bhndb_subr.c optional bhndb bhnd dev/bhnd/bcma/bcma.c optional bcma bhnd dev/bhnd/bcma/bcma_bhndb.c optional bcma bhnd bhndb dev/bhnd/bcma/bcma_erom.c optional bcma bhnd dev/bhnd/bcma/bcma_nexus.c optional bcma_nexus bcma bhnd dev/bhnd/bcma/bcma_subr.c optional bcma bhnd +dev/bhnd/cores/chipc/bhnd_chipc_if.m optional bhnd +dev/bhnd/cores/chipc/bhnd_sprom_chipc.c optional bhnd +dev/bhnd/cores/chipc/bhnd_pmu_chipc.c optional bhnd dev/bhnd/cores/chipc/chipc.c optional bhnd dev/bhnd/cores/chipc/chipc_cfi.c optional bhnd cfi dev/bhnd/cores/chipc/chipc_slicer.c optional bhnd cfi | bhnd spibus dev/bhnd/cores/chipc/chipc_spi.c optional bhnd spibus dev/bhnd/cores/chipc/chipc_subr.c optional bhnd -dev/bhnd/cores/chipc/bhnd_chipc_if.m optional bhnd -dev/bhnd/cores/chipc/bhnd_sprom_chipc.c optional bhnd +dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl.c optional bhnd +dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c optional bhnd dev/bhnd/cores/pci/bhnd_pci.c optional bhnd pci dev/bhnd/cores/pci/bhnd_pci_hostb.c optional bhndb bhnd pci dev/bhnd/cores/pci/bhnd_pcib.c optional bhnd_pcib bhnd pci dev/bhnd/cores/pcie2/bhnd_pcie2.c optional bhnd pci dev/bhnd/cores/pcie2/bhnd_pcie2_hostb.c optional bhndb bhnd pci dev/bhnd/cores/pcie2/bhnd_pcie2b.c optional bhnd_pcie2b bhnd pci +dev/bhnd/cores/pmu/bhnd_pmu.c optional bhnd +dev/bhnd/cores/pmu/bhnd_pmu_core.c optional bhnd +dev/bhnd/cores/pmu/bhnd_pmu_if.m optional bhnd +dev/bhnd/cores/pmu/bhnd_pmu_subr.c optional bhnd dev/bhnd/nvram/bhnd_nvram.c optional bhnd dev/bhnd/nvram/bhnd_nvram_common.c optional bhnd dev/bhnd/nvram/bhnd_nvram_cfe.c optional bhnd siba_nexus cfe | \ bhnd bcma_nexus cfe dev/bhnd/nvram/bhnd_nvram_if.m optional bhnd dev/bhnd/nvram/bhnd_nvram_parser.c optional bhnd dev/bhnd/nvram/bhnd_sprom.c optional bhnd dev/bhnd/nvram/bhnd_sprom_parser.c optional bhnd dev/bhnd/siba/siba.c optional siba bhnd dev/bhnd/siba/siba_bhndb.c optional siba bhnd bhndb dev/bhnd/siba/siba_nexus.c optional siba_nexus siba bhnd dev/bhnd/siba/siba_subr.c optional siba bhnd # dev/bktr/bktr_audio.c optional bktr pci dev/bktr/bktr_card.c optional bktr pci dev/bktr/bktr_core.c optional bktr pci dev/bktr/bktr_i2c.c optional bktr pci smbus dev/bktr/bktr_os.c optional bktr pci dev/bktr/bktr_tuner.c optional bktr pci dev/bktr/msp34xx.c optional bktr pci dev/buslogic/bt.c optional bt dev/buslogic/bt_eisa.c optional bt eisa dev/buslogic/bt_isa.c optional bt isa dev/buslogic/bt_mca.c optional bt mca dev/buslogic/bt_pci.c optional bt pci dev/bwi/bwimac.c optional bwi dev/bwi/bwiphy.c optional bwi dev/bwi/bwirf.c optional bwi dev/bwi/if_bwi.c optional bwi dev/bwi/if_bwi_pci.c optional bwi pci # XXX Work around clang warning, until maintainer approves fix. dev/bwn/if_bwn.c optional bwn siba_bwn \ compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}" dev/bwn/if_bwn_pci.c optional bwn pci bhnd dev/bwn/if_bwn_phy_common.c optional bwn siba_bwn dev/bwn/if_bwn_phy_g.c optional bwn siba_bwn \ compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}" dev/bwn/if_bwn_phy_lp.c optional bwn siba_bwn \ compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}" dev/bwn/if_bwn_phy_n.c optional bwn siba_bwn dev/bwn/if_bwn_util.c optional bwn siba_bwn dev/bwn/bwn_mac.c optional bwn bhnd dev/cardbus/cardbus.c optional cardbus dev/cardbus/cardbus_cis.c optional cardbus dev/cardbus/cardbus_device.c optional cardbus dev/cas/if_cas.c optional cas dev/cfi/cfi_bus_fdt.c optional cfi fdt dev/cfi/cfi_bus_nexus.c optional cfi dev/cfi/cfi_core.c optional cfi dev/cfi/cfi_dev.c optional cfi dev/cfi/cfi_disk.c optional cfid dev/ciss/ciss.c optional ciss dev/cm/smc90cx6.c optional cm dev/cmx/cmx.c optional cmx dev/cmx/cmx_pccard.c optional cmx pccard dev/cpufreq/ichss.c optional cpufreq dev/cs/if_cs.c optional cs dev/cs/if_cs_isa.c optional cs isa dev/cs/if_cs_pccard.c optional cs pccard dev/cxgb/cxgb_main.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/cxgb_sge.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_mc5.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_vsc7323.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_vsc8211.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_ael1002.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_aq100x.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_mv88e1xxx.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_xgmac.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_t3_hw.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_tn1010.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/sys/uipc_mvec.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/cxgb_t3fw.c optional cxgb cxgb_t3fw \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgbe/t4_if.m optional cxgbe pci dev/cxgbe/t4_iov.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/t4_mp_ring.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/t4_main.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/t4_netmap.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/t4_sge.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/t4_l2t.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/t4_tracer.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/common/t4_hw.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" t4fw_cfg.c optional cxgbe \ compile-with "${AWK} -f $S/tools/fw_stub.awk t4fw_cfg.fw:t4fw_cfg t4fw_cfg_uwire.fw:t4fw_cfg_uwire t4fw.fw:t4fw -mt4fw_cfg -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "t4fw_cfg.c" t4fw_cfg.fwo optional cxgbe \ dependency "t4fw_cfg.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "t4fw_cfg.fwo" t4fw_cfg.fw optional cxgbe \ dependency "$S/dev/cxgbe/firmware/t4fw_cfg.txt" \ compile-with "${CP} ${.ALLSRC} ${.TARGET}" \ no-obj no-implicit-rule \ clean "t4fw_cfg.fw" t4fw_cfg_uwire.fwo optional cxgbe \ dependency "t4fw_cfg_uwire.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "t4fw_cfg_uwire.fwo" t4fw_cfg_uwire.fw optional cxgbe \ dependency "$S/dev/cxgbe/firmware/t4fw_cfg_uwire.txt" \ compile-with "${CP} ${.ALLSRC} ${.TARGET}" \ no-obj no-implicit-rule \ clean "t4fw_cfg_uwire.fw" t4fw.fwo optional cxgbe \ dependency "t4fw.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "t4fw.fwo" t4fw.fw optional cxgbe \ dependency "$S/dev/cxgbe/firmware/t4fw-1.15.37.0.bin.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "t4fw.fw" t5fw_cfg.c optional cxgbe \ compile-with "${AWK} -f $S/tools/fw_stub.awk t5fw_cfg.fw:t5fw_cfg t5fw.fw:t5fw -mt5fw_cfg -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "t5fw_cfg.c" t5fw_cfg.fwo optional cxgbe \ dependency "t5fw_cfg.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "t5fw_cfg.fwo" t5fw_cfg.fw optional cxgbe \ dependency "$S/dev/cxgbe/firmware/t5fw_cfg.txt" \ compile-with "${CP} ${.ALLSRC} ${.TARGET}" \ no-obj no-implicit-rule \ clean "t5fw_cfg.fw" t5fw.fwo optional cxgbe \ dependency "t5fw.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "t5fw.fwo" t5fw.fw optional cxgbe \ dependency "$S/dev/cxgbe/firmware/t5fw-1.15.37.0.bin.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "t5fw.fw" dev/cy/cy.c optional cy dev/cy/cy_isa.c optional cy isa dev/cy/cy_pci.c optional cy pci dev/cyapa/cyapa.c optional cyapa smbus dev/dc/if_dc.c optional dc pci dev/dc/dcphy.c optional dc pci dev/dc/pnphy.c optional dc pci dev/dcons/dcons.c optional dcons dev/dcons/dcons_crom.c optional dcons_crom dev/dcons/dcons_os.c optional dcons dev/de/if_de.c optional de pci dev/digi/CX.c optional digi_CX dev/digi/CX_PCI.c optional digi_CX_PCI dev/digi/EPCX.c optional digi_EPCX dev/digi/EPCX_PCI.c optional digi_EPCX_PCI dev/digi/Xe.c optional digi_Xe dev/digi/Xem.c optional digi_Xem dev/digi/Xr.c optional digi_Xr dev/digi/digi.c optional digi dev/digi/digi_isa.c optional digi isa dev/digi/digi_pci.c optional digi pci dev/dpt/dpt_eisa.c optional dpt eisa dev/dpt/dpt_pci.c optional dpt pci dev/dpt/dpt_scsi.c optional dpt dev/drm/ati_pcigart.c optional drm dev/drm/drm_agpsupport.c optional drm dev/drm/drm_auth.c optional drm dev/drm/drm_bufs.c optional drm dev/drm/drm_context.c optional drm dev/drm/drm_dma.c optional drm dev/drm/drm_drawable.c optional drm dev/drm/drm_drv.c optional drm dev/drm/drm_fops.c optional drm dev/drm/drm_hashtab.c optional drm dev/drm/drm_ioctl.c optional drm dev/drm/drm_irq.c optional drm dev/drm/drm_lock.c optional drm dev/drm/drm_memory.c optional drm dev/drm/drm_mm.c optional drm dev/drm/drm_pci.c optional drm dev/drm/drm_scatter.c optional drm dev/drm/drm_sman.c optional drm dev/drm/drm_sysctl.c optional drm dev/drm/drm_vm.c optional drm dev/drm/i915_dma.c optional i915drm dev/drm/i915_drv.c optional i915drm dev/drm/i915_irq.c optional i915drm dev/drm/i915_mem.c optional i915drm dev/drm/i915_suspend.c optional i915drm dev/drm/mach64_dma.c optional mach64drm dev/drm/mach64_drv.c optional mach64drm dev/drm/mach64_irq.c optional mach64drm dev/drm/mach64_state.c optional mach64drm dev/drm/mga_dma.c optional mgadrm dev/drm/mga_drv.c optional mgadrm dev/drm/mga_irq.c optional mgadrm dev/drm/mga_state.c optional mgadrm dev/drm/mga_warp.c optional mgadrm dev/drm/r128_cce.c optional r128drm \ compile-with "${NORMAL_C} ${NO_WCONSTANT_CONVERSION}" dev/drm/r128_drv.c optional r128drm dev/drm/r128_irq.c optional r128drm dev/drm/r128_state.c optional r128drm dev/drm/r300_cmdbuf.c optional radeondrm dev/drm/r600_blit.c optional radeondrm dev/drm/r600_cp.c optional radeondrm \ compile-with "${NORMAL_C} ${NO_WCONSTANT_CONVERSION}" dev/drm/radeon_cp.c optional radeondrm \ compile-with "${NORMAL_C} ${NO_WCONSTANT_CONVERSION}" dev/drm/radeon_cs.c optional radeondrm dev/drm/radeon_drv.c optional radeondrm dev/drm/radeon_irq.c optional radeondrm dev/drm/radeon_mem.c optional radeondrm dev/drm/radeon_state.c optional radeondrm dev/drm/savage_bci.c optional savagedrm dev/drm/savage_drv.c optional savagedrm dev/drm/savage_state.c optional savagedrm dev/drm/sis_drv.c optional sisdrm dev/drm/sis_ds.c optional sisdrm dev/drm/sis_mm.c optional sisdrm dev/drm/tdfx_drv.c optional tdfxdrm dev/drm/via_dma.c optional viadrm dev/drm/via_dmablit.c optional viadrm dev/drm/via_drv.c optional viadrm dev/drm/via_irq.c optional viadrm dev/drm/via_map.c optional viadrm dev/drm/via_mm.c optional viadrm dev/drm/via_verifier.c optional viadrm dev/drm/via_video.c optional viadrm dev/ed/if_ed.c optional ed dev/ed/if_ed_novell.c optional ed dev/ed/if_ed_rtl80x9.c optional ed dev/ed/if_ed_pccard.c optional ed pccard dev/ed/if_ed_pci.c optional ed pci dev/eisa/eisa_if.m standard dev/eisa/eisaconf.c optional eisa dev/e1000/if_em.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/if_lem.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/if_igb.c optional igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_80003es2lan.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82540.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82541.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82542.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82543.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82571.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82575.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_ich8lan.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_i210.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_api.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_mac.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_manage.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_nvm.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_phy.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_vf.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_mbx.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_osdep.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/et/if_et.c optional et dev/en/if_en_pci.c optional en pci dev/en/midway.c optional en dev/ep/if_ep.c optional ep dev/ep/if_ep_eisa.c optional ep eisa dev/ep/if_ep_isa.c optional ep isa dev/ep/if_ep_mca.c optional ep mca dev/ep/if_ep_pccard.c optional ep pccard dev/esp/esp_pci.c optional esp pci dev/esp/ncr53c9x.c optional esp dev/etherswitch/arswitch/arswitch.c optional arswitch dev/etherswitch/arswitch/arswitch_reg.c optional arswitch dev/etherswitch/arswitch/arswitch_phy.c optional arswitch dev/etherswitch/arswitch/arswitch_8216.c optional arswitch dev/etherswitch/arswitch/arswitch_8226.c optional arswitch dev/etherswitch/arswitch/arswitch_8316.c optional arswitch dev/etherswitch/arswitch/arswitch_8327.c optional arswitch dev/etherswitch/arswitch/arswitch_7240.c optional arswitch dev/etherswitch/arswitch/arswitch_9340.c optional arswitch dev/etherswitch/arswitch/arswitch_vlans.c optional arswitch dev/etherswitch/etherswitch.c optional etherswitch dev/etherswitch/etherswitch_if.m optional etherswitch dev/etherswitch/ip17x/ip17x.c optional ip17x dev/etherswitch/ip17x/ip175c.c optional ip17x dev/etherswitch/ip17x/ip175d.c optional ip17x dev/etherswitch/ip17x/ip17x_phy.c optional ip17x dev/etherswitch/ip17x/ip17x_vlans.c optional ip17x dev/etherswitch/miiproxy.c optional miiproxy dev/etherswitch/rtl8366/rtl8366rb.c optional rtl8366rb dev/etherswitch/ukswitch/ukswitch.c optional ukswitch dev/ex/if_ex.c optional ex dev/ex/if_ex_isa.c optional ex isa dev/ex/if_ex_pccard.c optional ex pccard dev/exca/exca.c optional cbb dev/extres/clk/clk.c optional ext_resources clk dev/extres/clk/clkdev_if.m optional ext_resources clk dev/extres/clk/clknode_if.m optional ext_resources clk dev/extres/clk/clk_bus.c optional ext_resources clk fdt dev/extres/clk/clk_div.c optional ext_resources clk dev/extres/clk/clk_fixed.c optional ext_resources clk dev/extres/clk/clk_gate.c optional ext_resources clk dev/extres/clk/clk_mux.c optional ext_resources clk dev/extres/phy/phy.c optional ext_resources phy dev/extres/phy/phy_if.m optional ext_resources phy dev/extres/hwreset/hwreset.c optional ext_resources hwreset dev/extres/hwreset/hwreset_if.m optional ext_resources hwreset dev/extres/regulator/regdev_if.m optional ext_resources regulator dev/extres/regulator/regnode_if.m optional ext_resources regulator dev/extres/regulator/regulator.c optional ext_resources regulator dev/extres/regulator/regulator_bus.c optional ext_resources regulator fdt dev/extres/regulator/regulator_fixed.c optional ext_resources regulator dev/fatm/if_fatm.c optional fatm pci dev/fb/fbd.c optional fbd | vt dev/fb/fb_if.m standard dev/fb/splash.c optional sc splash dev/fdt/fdt_clock.c optional fdt fdt_clock dev/fdt/fdt_clock_if.m optional fdt fdt_clock dev/fdt/fdt_common.c optional fdt dev/fdt/fdt_pinctrl.c optional fdt fdt_pinctrl dev/fdt/fdt_pinctrl_if.m optional fdt fdt_pinctrl dev/fdt/fdt_slicer.c optional fdt cfi | fdt nand | fdt mx25l dev/fdt/fdt_static_dtb.S optional fdt fdt_dtb_static \ dependency "fdt_dtb_file" dev/fdt/simplebus.c optional fdt dev/fe/if_fe.c optional fe dev/fe/if_fe_pccard.c optional fe pccard dev/filemon/filemon.c optional filemon dev/firewire/firewire.c optional firewire dev/firewire/fwcrom.c optional firewire dev/firewire/fwdev.c optional firewire dev/firewire/fwdma.c optional firewire dev/firewire/fwmem.c optional firewire dev/firewire/fwohci.c optional firewire dev/firewire/fwohci_pci.c optional firewire pci dev/firewire/if_fwe.c optional fwe dev/firewire/if_fwip.c optional fwip dev/firewire/sbp.c optional sbp dev/firewire/sbp_targ.c optional sbp_targ dev/flash/at45d.c optional at45d dev/flash/mx25l.c optional mx25l dev/fxp/if_fxp.c optional fxp dev/fxp/inphy.c optional fxp dev/gem/if_gem.c optional gem dev/gem/if_gem_pci.c optional gem pci dev/gem/if_gem_sbus.c optional gem sbus dev/gpio/gpiobacklight.c optional gpiobacklight fdt dev/gpio/gpiokeys.c optional gpiokeys fdt dev/gpio/gpiokeys_codes.c optional gpiokeys fdt dev/gpio/gpiobus.c optional gpio \ dependency "gpiobus_if.h" dev/gpio/gpioc.c optional gpio \ dependency "gpio_if.h" dev/gpio/gpioiic.c optional gpioiic dev/gpio/gpioled.c optional gpioled dev/gpio/gpiospi.c optional gpiospi dev/gpio/gpio_if.m optional gpio dev/gpio/gpiobus_if.m optional gpio dev/gpio/gpiopps.c optional gpiopps dev/gpio/ofw_gpiobus.c optional fdt gpio dev/hatm/if_hatm.c optional hatm pci dev/hatm/if_hatm_intr.c optional hatm pci dev/hatm/if_hatm_ioctl.c optional hatm pci dev/hatm/if_hatm_rx.c optional hatm pci dev/hatm/if_hatm_tx.c optional hatm pci dev/hifn/hifn7751.c optional hifn dev/hme/if_hme.c optional hme dev/hme/if_hme_pci.c optional hme pci dev/hme/if_hme_sbus.c optional hme sbus dev/hptiop/hptiop.c optional hptiop scbus dev/hwpmc/hwpmc_logging.c optional hwpmc dev/hwpmc/hwpmc_mod.c optional hwpmc dev/hwpmc/hwpmc_soft.c optional hwpmc dev/ichiic/ig4_iic.c optional ig4 smbus dev/ichiic/ig4_pci.c optional ig4 pci smbus dev/ichsmb/ichsmb.c optional ichsmb dev/ichsmb/ichsmb_pci.c optional ichsmb pci dev/ida/ida.c optional ida dev/ida/ida_disk.c optional ida dev/ida/ida_eisa.c optional ida eisa dev/ida/ida_pci.c optional ida pci dev/iicbus/ad7418.c optional ad7418 dev/iicbus/ds1307.c optional ds1307 dev/iicbus/ds133x.c optional ds133x dev/iicbus/ds1374.c optional ds1374 dev/iicbus/ds1672.c optional ds1672 dev/iicbus/ds3231.c optional ds3231 dev/iicbus/icee.c optional icee dev/iicbus/if_ic.c optional ic dev/iicbus/iic.c optional iic dev/iicbus/iicbb.c optional iicbb dev/iicbus/iicbb_if.m optional iicbb dev/iicbus/iicbus.c optional iicbus dev/iicbus/iicbus_if.m optional iicbus dev/iicbus/iiconf.c optional iicbus dev/iicbus/iicsmb.c optional iicsmb \ dependency "iicbus_if.h" dev/iicbus/iicoc.c optional iicoc dev/iicbus/lm75.c optional lm75 dev/iicbus/ofw_iicbus.c optional fdt iicbus dev/iicbus/pcf8563.c optional pcf8563 dev/iicbus/s35390a.c optional s35390a dev/iir/iir.c optional iir dev/iir/iir_ctrl.c optional iir dev/iir/iir_pci.c optional iir pci dev/intpm/intpm.c optional intpm pci # XXX Work around clang warning, until maintainer approves fix. dev/ips/ips.c optional ips \ compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}" dev/ips/ips_commands.c optional ips dev/ips/ips_disk.c optional ips dev/ips/ips_ioctl.c optional ips dev/ips/ips_pci.c optional ips pci dev/ipw/if_ipw.c optional ipw ipwbssfw.c optional ipwbssfw | ipwfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk ipw_bss.fw:ipw_bss:130 -lintel_ipw -mipw_bss -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "ipwbssfw.c" ipw_bss.fwo optional ipwbssfw | ipwfw \ dependency "ipw_bss.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "ipw_bss.fwo" ipw_bss.fw optional ipwbssfw | ipwfw \ dependency "$S/contrib/dev/ipw/ipw2100-1.3.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "ipw_bss.fw" ipwibssfw.c optional ipwibssfw | ipwfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk ipw_ibss.fw:ipw_ibss:130 -lintel_ipw -mipw_ibss -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "ipwibssfw.c" ipw_ibss.fwo optional ipwibssfw | ipwfw \ dependency "ipw_ibss.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "ipw_ibss.fwo" ipw_ibss.fw optional ipwibssfw | ipwfw \ dependency "$S/contrib/dev/ipw/ipw2100-1.3-i.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "ipw_ibss.fw" ipwmonitorfw.c optional ipwmonitorfw | ipwfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk ipw_monitor.fw:ipw_monitor:130 -lintel_ipw -mipw_monitor -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "ipwmonitorfw.c" ipw_monitor.fwo optional ipwmonitorfw | ipwfw \ dependency "ipw_monitor.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "ipw_monitor.fwo" ipw_monitor.fw optional ipwmonitorfw | ipwfw \ dependency "$S/contrib/dev/ipw/ipw2100-1.3-p.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "ipw_monitor.fw" dev/iscsi/icl.c optional iscsi | ctl dev/iscsi/icl_conn_if.m optional iscsi | ctl dev/iscsi/icl_soft.c optional iscsi | ctl dev/iscsi/icl_soft_proxy.c optional iscsi | ctl dev/iscsi/iscsi.c optional iscsi scbus dev/iscsi_initiator/iscsi.c optional iscsi_initiator scbus dev/iscsi_initiator/iscsi_subr.c optional iscsi_initiator scbus dev/iscsi_initiator/isc_cam.c optional iscsi_initiator scbus dev/iscsi_initiator/isc_soc.c optional iscsi_initiator scbus dev/iscsi_initiator/isc_sm.c optional iscsi_initiator scbus dev/iscsi_initiator/isc_subr.c optional iscsi_initiator scbus dev/ismt/ismt.c optional ismt dev/isl/isl.c optional isl smbus dev/isp/isp.c optional isp dev/isp/isp_freebsd.c optional isp dev/isp/isp_library.c optional isp dev/isp/isp_pci.c optional isp pci dev/isp/isp_sbus.c optional isp sbus dev/isp/isp_target.c optional isp dev/ispfw/ispfw.c optional ispfw dev/iwi/if_iwi.c optional iwi iwibssfw.c optional iwibssfw | iwifw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwi_bss.fw:iwi_bss:300 -lintel_iwi -miwi_bss -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwibssfw.c" iwi_bss.fwo optional iwibssfw | iwifw \ dependency "iwi_bss.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwi_bss.fwo" iwi_bss.fw optional iwibssfw | iwifw \ dependency "$S/contrib/dev/iwi/ipw2200-bss.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwi_bss.fw" iwiibssfw.c optional iwiibssfw | iwifw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwi_ibss.fw:iwi_ibss:300 -lintel_iwi -miwi_ibss -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwiibssfw.c" iwi_ibss.fwo optional iwiibssfw | iwifw \ dependency "iwi_ibss.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwi_ibss.fwo" iwi_ibss.fw optional iwiibssfw | iwifw \ dependency "$S/contrib/dev/iwi/ipw2200-ibss.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwi_ibss.fw" iwimonitorfw.c optional iwimonitorfw | iwifw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwi_monitor.fw:iwi_monitor:300 -lintel_iwi -miwi_monitor -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwimonitorfw.c" iwi_monitor.fwo optional iwimonitorfw | iwifw \ dependency "iwi_monitor.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwi_monitor.fwo" iwi_monitor.fw optional iwimonitorfw | iwifw \ dependency "$S/contrib/dev/iwi/ipw2200-sniffer.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwi_monitor.fw" dev/iwm/if_iwm.c optional iwm dev/iwm/if_iwm_binding.c optional iwm dev/iwm/if_iwm_led.c optional iwm dev/iwm/if_iwm_mac_ctxt.c optional iwm dev/iwm/if_iwm_pcie_trans.c optional iwm dev/iwm/if_iwm_phy_ctxt.c optional iwm dev/iwm/if_iwm_phy_db.c optional iwm dev/iwm/if_iwm_power.c optional iwm dev/iwm/if_iwm_scan.c optional iwm dev/iwm/if_iwm_time_event.c optional iwm dev/iwm/if_iwm_util.c optional iwm iwm3160fw.c optional iwm3160fw | iwmfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwm3160.fw:iwm3160fw -miwm3160fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwm3160fw.c" iwm3160fw.fwo optional iwm3160fw | iwmfw \ dependency "iwm3160.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwm3160fw.fwo" iwm3160.fw optional iwm3160fw | iwmfw \ dependency "$S/contrib/dev/iwm/iwm-3160-16.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwm3160.fw" iwm7260fw.c optional iwm7260fw | iwmfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwm7260.fw:iwm7260fw -miwm7260fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwm7260fw.c" iwm7260fw.fwo optional iwm7260fw | iwmfw \ dependency "iwm7260.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwm7260fw.fwo" iwm7260.fw optional iwm7260fw | iwmfw \ dependency "$S/contrib/dev/iwm/iwm-7260-16.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwm7260.fw" iwm7265fw.c optional iwm7265fw | iwmfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwm7265.fw:iwm7265fw -miwm7265fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwm7265fw.c" iwm7265fw.fwo optional iwm7265fw | iwmfw \ dependency "iwm7265.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwm7265fw.fwo" iwm7265.fw optional iwm7265fw | iwmfw \ dependency "$S/contrib/dev/iwm/iwm-7265-16.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwm7265.fw" iwm8000Cfw.c optional iwm8000Cfw | iwmfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwm8000C.fw:iwm8000Cfw -miwm8000Cfw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwm8000Cfw.c" iwm8000Cfw.fwo optional iwm8000Cfw | iwmfw \ dependency "iwm8000C.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwm8000Cfw.fwo" iwm8000C.fw optional iwm8000Cfw | iwmfw \ dependency "$S/contrib/dev/iwm/iwm-8000C-16.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwm8000C.fw" dev/iwn/if_iwn.c optional iwn iwn1000fw.c optional iwn1000fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn1000.fw:iwn1000fw -miwn1000fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn1000fw.c" iwn1000fw.fwo optional iwn1000fw | iwnfw \ dependency "iwn1000.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn1000fw.fwo" iwn1000.fw optional iwn1000fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-1000-39.31.5.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn1000.fw" iwn100fw.c optional iwn100fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn100.fw:iwn100fw -miwn100fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn100fw.c" iwn100fw.fwo optional iwn100fw | iwnfw \ dependency "iwn100.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn100fw.fwo" iwn100.fw optional iwn100fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-100-39.31.5.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn100.fw" iwn105fw.c optional iwn105fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn105.fw:iwn105fw -miwn105fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn105fw.c" iwn105fw.fwo optional iwn105fw | iwnfw \ dependency "iwn105.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn105fw.fwo" iwn105.fw optional iwn105fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-105-6-18.168.6.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn105.fw" iwn135fw.c optional iwn135fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn135.fw:iwn135fw -miwn135fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn135fw.c" iwn135fw.fwo optional iwn135fw | iwnfw \ dependency "iwn135.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn135fw.fwo" iwn135.fw optional iwn135fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-135-6-18.168.6.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn135.fw" iwn2000fw.c optional iwn2000fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn2000.fw:iwn2000fw -miwn2000fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn2000fw.c" iwn2000fw.fwo optional iwn2000fw | iwnfw \ dependency "iwn2000.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn2000fw.fwo" iwn2000.fw optional iwn2000fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-2000-18.168.6.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn2000.fw" iwn2030fw.c optional iwn2030fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn2030.fw:iwn2030fw -miwn2030fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn2030fw.c" iwn2030fw.fwo optional iwn2030fw | iwnfw \ dependency "iwn2030.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn2030fw.fwo" iwn2030.fw optional iwn2030fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwnwifi-2030-18.168.6.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn2030.fw" iwn4965fw.c optional iwn4965fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn4965.fw:iwn4965fw -miwn4965fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn4965fw.c" iwn4965fw.fwo optional iwn4965fw | iwnfw \ dependency "iwn4965.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn4965fw.fwo" iwn4965.fw optional iwn4965fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-4965-228.61.2.24.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn4965.fw" iwn5000fw.c optional iwn5000fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn5000.fw:iwn5000fw -miwn5000fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn5000fw.c" iwn5000fw.fwo optional iwn5000fw | iwnfw \ dependency "iwn5000.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn5000fw.fwo" iwn5000.fw optional iwn5000fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-5000-8.83.5.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn5000.fw" iwn5150fw.c optional iwn5150fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn5150.fw:iwn5150fw -miwn5150fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn5150fw.c" iwn5150fw.fwo optional iwn5150fw | iwnfw \ dependency "iwn5150.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn5150fw.fwo" iwn5150.fw optional iwn5150fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-5150-8.24.2.2.fw.uu"\ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn5150.fw" iwn6000fw.c optional iwn6000fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn6000.fw:iwn6000fw -miwn6000fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn6000fw.c" iwn6000fw.fwo optional iwn6000fw | iwnfw \ dependency "iwn6000.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn6000fw.fwo" iwn6000.fw optional iwn6000fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-6000-9.221.4.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn6000.fw" iwn6000g2afw.c optional iwn6000g2afw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn6000g2a.fw:iwn6000g2afw -miwn6000g2afw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn6000g2afw.c" iwn6000g2afw.fwo optional iwn6000g2afw | iwnfw \ dependency "iwn6000g2a.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn6000g2afw.fwo" iwn6000g2a.fw optional iwn6000g2afw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-6000g2a-18.168.6.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn6000g2a.fw" iwn6000g2bfw.c optional iwn6000g2bfw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn6000g2b.fw:iwn6000g2bfw -miwn6000g2bfw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn6000g2bfw.c" iwn6000g2bfw.fwo optional iwn6000g2bfw | iwnfw \ dependency "iwn6000g2b.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn6000g2bfw.fwo" iwn6000g2b.fw optional iwn6000g2bfw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-6000g2b-18.168.6.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn6000g2b.fw" iwn6050fw.c optional iwn6050fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn6050.fw:iwn6050fw -miwn6050fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn6050fw.c" iwn6050fw.fwo optional iwn6050fw | iwnfw \ dependency "iwn6050.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn6050fw.fwo" iwn6050.fw optional iwn6050fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-6050-41.28.5.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn6050.fw" dev/ixgb/if_ixgb.c optional ixgb dev/ixgb/ixgb_ee.c optional ixgb dev/ixgb/ixgb_hw.c optional ixgb dev/ixgbe/if_ix.c optional ix inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe -DSMP" dev/ixgbe/if_ixv.c optional ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe -DSMP" dev/ixgbe/ix_txrx.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_osdep.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_phy.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_api.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_common.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_mbx.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_vf.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_82598.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_82599.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_x540.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_x550.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_dcb.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_dcb_82598.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_dcb_82599.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/jme/if_jme.c optional jme pci dev/joy/joy.c optional joy dev/joy/joy_isa.c optional joy isa dev/kbd/kbd.c optional atkbd | pckbd | sc | ukbd | vt dev/kbdmux/kbdmux.c optional kbdmux dev/ksyms/ksyms.c optional ksyms dev/le/am7990.c optional le dev/le/am79900.c optional le dev/le/if_le_pci.c optional le pci dev/le/lance.c optional le dev/led/led.c standard dev/lge/if_lge.c optional lge dev/lmc/if_lmc.c optional lmc dev/malo/if_malo.c optional malo dev/malo/if_malohal.c optional malo dev/malo/if_malo_pci.c optional malo pci dev/mc146818/mc146818.c optional mc146818 dev/mca/mca_bus.c optional mca dev/md/md.c optional md dev/mdio/mdio_if.m optional miiproxy | mdio dev/mdio/mdio.c optional miiproxy | mdio dev/mem/memdev.c optional mem dev/mem/memutil.c optional mem dev/mfi/mfi.c optional mfi dev/mfi/mfi_debug.c optional mfi dev/mfi/mfi_pci.c optional mfi pci dev/mfi/mfi_disk.c optional mfi dev/mfi/mfi_syspd.c optional mfi dev/mfi/mfi_tbolt.c optional mfi dev/mfi/mfi_linux.c optional mfi compat_linux dev/mfi/mfi_cam.c optional mfip scbus dev/mii/acphy.c optional miibus | acphy dev/mii/amphy.c optional miibus | amphy dev/mii/atphy.c optional miibus | atphy dev/mii/axphy.c optional miibus | axphy dev/mii/bmtphy.c optional miibus | bmtphy dev/mii/brgphy.c optional miibus | brgphy dev/mii/ciphy.c optional miibus | ciphy dev/mii/e1000phy.c optional miibus | e1000phy dev/mii/gentbi.c optional miibus | gentbi dev/mii/icsphy.c optional miibus | icsphy dev/mii/ip1000phy.c optional miibus | ip1000phy dev/mii/jmphy.c optional miibus | jmphy dev/mii/lxtphy.c optional miibus | lxtphy dev/mii/micphy.c optional miibus fdt | micphy fdt dev/mii/mii.c optional miibus | mii dev/mii/mii_bitbang.c optional miibus | mii_bitbang dev/mii/mii_physubr.c optional miibus | mii dev/mii/miibus_if.m optional miibus | mii dev/mii/mlphy.c optional miibus | mlphy dev/mii/nsgphy.c optional miibus | nsgphy dev/mii/nsphy.c optional miibus | nsphy dev/mii/nsphyter.c optional miibus | nsphyter dev/mii/pnaphy.c optional miibus | pnaphy dev/mii/qsphy.c optional miibus | qsphy dev/mii/rdcphy.c optional miibus | rdcphy dev/mii/rgephy.c optional miibus | rgephy dev/mii/rlphy.c optional miibus | rlphy dev/mii/rlswitch.c optional rlswitch dev/mii/smcphy.c optional miibus | smcphy dev/mii/smscphy.c optional miibus | smscphy dev/mii/tdkphy.c optional miibus | tdkphy dev/mii/tlphy.c optional miibus | tlphy dev/mii/truephy.c optional miibus | truephy dev/mii/ukphy.c optional miibus | mii dev/mii/ukphy_subr.c optional miibus | mii dev/mii/xmphy.c optional miibus | xmphy dev/mk48txx/mk48txx.c optional mk48txx dev/mlx/mlx.c optional mlx dev/mlx/mlx_disk.c optional mlx dev/mlx/mlx_pci.c optional mlx pci dev/mly/mly.c optional mly dev/mmc/mmc.c optional mmc dev/mmc/mmcbr_if.m standard dev/mmc/mmcbus_if.m standard dev/mmc/mmcsd.c optional mmcsd dev/mn/if_mn.c optional mn pci dev/mpr/mpr.c optional mpr dev/mpr/mpr_config.c optional mpr # XXX Work around clang warning, until maintainer approves fix. dev/mpr/mpr_mapping.c optional mpr \ compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}" dev/mpr/mpr_pci.c optional mpr pci dev/mpr/mpr_sas.c optional mpr \ compile-with "${NORMAL_C} ${NO_WUNNEEDED_INTERNAL_DECL}" dev/mpr/mpr_sas_lsi.c optional mpr dev/mpr/mpr_table.c optional mpr dev/mpr/mpr_user.c optional mpr dev/mps/mps.c optional mps dev/mps/mps_config.c optional mps # XXX Work around clang warning, until maintainer approves fix. dev/mps/mps_mapping.c optional mps \ compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}" dev/mps/mps_pci.c optional mps pci dev/mps/mps_sas.c optional mps \ compile-with "${NORMAL_C} ${NO_WUNNEEDED_INTERNAL_DECL}" dev/mps/mps_sas_lsi.c optional mps dev/mps/mps_table.c optional mps dev/mps/mps_user.c optional mps dev/mpt/mpt.c optional mpt dev/mpt/mpt_cam.c optional mpt dev/mpt/mpt_debug.c optional mpt dev/mpt/mpt_pci.c optional mpt pci dev/mpt/mpt_raid.c optional mpt dev/mpt/mpt_user.c optional mpt dev/mrsas/mrsas.c optional mrsas dev/mrsas/mrsas_cam.c optional mrsas dev/mrsas/mrsas_ioctl.c optional mrsas dev/mrsas/mrsas_fp.c optional mrsas dev/msk/if_msk.c optional msk dev/mvs/mvs.c optional mvs dev/mvs/mvs_if.m optional mvs dev/mvs/mvs_pci.c optional mvs pci dev/mwl/if_mwl.c optional mwl dev/mwl/if_mwl_pci.c optional mwl pci dev/mwl/mwlhal.c optional mwl mwlfw.c optional mwlfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk mw88W8363.fw:mw88W8363fw mwlboot.fw:mwlboot -mmwl -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "mwlfw.c" mw88W8363.fwo optional mwlfw \ dependency "mw88W8363.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "mw88W8363.fwo" mw88W8363.fw optional mwlfw \ dependency "$S/contrib/dev/mwl/mw88W8363.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "mw88W8363.fw" mwlboot.fwo optional mwlfw \ dependency "mwlboot.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "mwlboot.fwo" mwlboot.fw optional mwlfw \ dependency "$S/contrib/dev/mwl/mwlboot.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "mwlboot.fw" dev/mxge/if_mxge.c optional mxge pci dev/mxge/mxge_eth_z8e.c optional mxge pci dev/mxge/mxge_ethp_z8e.c optional mxge pci dev/mxge/mxge_rss_eth_z8e.c optional mxge pci dev/mxge/mxge_rss_ethp_z8e.c optional mxge pci dev/my/if_my.c optional my dev/nand/nand.c optional nand dev/nand/nand_bbt.c optional nand dev/nand/nand_cdev.c optional nand dev/nand/nand_generic.c optional nand dev/nand/nand_geom.c optional nand dev/nand/nand_id.c optional nand dev/nand/nandbus.c optional nand dev/nand/nandbus_if.m optional nand dev/nand/nand_if.m optional nand dev/nand/nandsim.c optional nandsim nand dev/nand/nandsim_chip.c optional nandsim nand dev/nand/nandsim_ctrl.c optional nandsim nand dev/nand/nandsim_log.c optional nandsim nand dev/nand/nandsim_swap.c optional nandsim nand dev/nand/nfc_if.m optional nand dev/ncr/ncr.c optional ncr pci dev/ncv/ncr53c500.c optional ncv dev/ncv/ncr53c500_pccard.c optional ncv pccard dev/netmap/netmap.c optional netmap dev/netmap/netmap_freebsd.c optional netmap dev/netmap/netmap_generic.c optional netmap dev/netmap/netmap_mbq.c optional netmap dev/netmap/netmap_mem2.c optional netmap dev/netmap/netmap_monitor.c optional netmap dev/netmap/netmap_offloadings.c optional netmap dev/netmap/netmap_pipe.c optional netmap dev/netmap/netmap_vale.c optional netmap # compile-with "${NORMAL_C} -Wconversion -Wextra" dev/nfsmb/nfsmb.c optional nfsmb pci dev/nge/if_nge.c optional nge dev/nxge/if_nxge.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nxge/xgehal/xgehal-device.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nxge/xgehal/xgehal-mm.c optional nxge dev/nxge/xgehal/xge-queue.c optional nxge dev/nxge/xgehal/xgehal-driver.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nxge/xgehal/xgehal-ring.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nxge/xgehal/xgehal-channel.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nxge/xgehal/xgehal-fifo.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nxge/xgehal/xgehal-stats.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nxge/xgehal/xgehal-config.c optional nxge dev/nxge/xgehal/xgehal-mgmt.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nmdm/nmdm.c optional nmdm dev/nsp/nsp.c optional nsp dev/nsp/nsp_pccard.c optional nsp pccard dev/null/null.c standard dev/oce/oce_hw.c optional oce pci dev/oce/oce_if.c optional oce pci dev/oce/oce_mbox.c optional oce pci dev/oce/oce_queue.c optional oce pci dev/oce/oce_sysctl.c optional oce pci dev/oce/oce_util.c optional oce pci dev/ofw/ofw_bus_if.m optional fdt dev/ofw/ofw_bus_subr.c optional fdt dev/ofw/ofw_fdt.c optional fdt dev/ofw/ofw_if.m optional fdt dev/ofw/ofw_subr.c optional fdt dev/ofw/ofwbus.c optional fdt dev/ofw/openfirm.c optional fdt dev/ofw/openfirmio.c optional fdt dev/ow/ow.c optional ow \ dependency "owll_if.h" \ dependency "own_if.h" dev/ow/owll_if.m optional ow dev/ow/own_if.m optional ow dev/ow/ow_temp.c optional ow_temp dev/ow/owc_gpiobus.c optional owc gpio dev/patm/if_patm.c optional patm pci dev/patm/if_patm_attach.c optional patm pci dev/patm/if_patm_intr.c optional patm pci dev/patm/if_patm_ioctl.c optional patm pci dev/patm/if_patm_rtables.c optional patm pci dev/patm/if_patm_rx.c optional patm pci dev/patm/if_patm_tx.c optional patm pci dev/pbio/pbio.c optional pbio isa dev/pccard/card_if.m standard dev/pccard/pccard.c optional pccard dev/pccard/pccard_cis.c optional pccard dev/pccard/pccard_cis_quirks.c optional pccard dev/pccard/pccard_device.c optional pccard dev/pccard/power_if.m standard dev/pccbb/pccbb.c optional cbb dev/pccbb/pccbb_isa.c optional cbb isa dev/pccbb/pccbb_pci.c optional cbb pci dev/pcf/pcf.c optional pcf dev/pci/eisa_pci.c optional pci eisa dev/pci/fixup_pci.c optional pci dev/pci/hostb_pci.c optional pci dev/pci/ignore_pci.c optional pci dev/pci/isa_pci.c optional pci isa dev/pci/pci.c optional pci dev/pci/pci_if.m standard dev/pci/pci_iov.c optional pci pci_iov dev/pci/pci_iov_if.m standard dev/pci/pci_iov_schema.c optional pci pci_iov dev/pci/pci_pci.c optional pci dev/pci/pci_subr.c optional pci dev/pci/pci_user.c optional pci dev/pci/pcib_if.m standard dev/pci/pcib_support.c standard dev/pci/vga_pci.c optional pci dev/pcn/if_pcn.c optional pcn pci dev/pdq/if_fea.c optional fea eisa dev/pdq/if_fpa.c optional fpa pci dev/pdq/pdq.c optional nowerror fea eisa | fpa pci dev/pdq/pdq_ifsubr.c optional nowerror fea eisa | fpa pci dev/pms/freebsd/driver/ini/src/agtiapi.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/sadisc.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/mpi.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/saframe.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/sahw.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/sainit.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/saint.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/sampicmd.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/sampirsp.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/saphy.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/saport.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/sasata.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/sasmp.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/sassp.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/satimer.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/sautil.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/saioctlcmd.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/mpidebug.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/discovery/dm/dminit.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/discovery/dm/dmsmp.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/discovery/dm/dmdisc.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/discovery/dm/dmport.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/discovery/dm/dmtimer.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/discovery/dm/dmmisc.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sat/src/sminit.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sat/src/smmisc.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sat/src/smsat.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sat/src/smsatcb.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sat/src/smsathw.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sat/src/smtimer.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/common/tdinit.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/common/tdmisc.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/common/tdesgl.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/common/tdport.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/common/tdint.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/common/tdioctl.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/common/tdhw.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/common/ossacmnapi.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/common/tddmcmnapi.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/common/tdsmcmnapi.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/common/tdtimers.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/sas/ini/itdio.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/sas/ini/itdcb.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/sas/ini/itdinit.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/sas/ini/itddisc.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/sata/host/sat.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/sata/host/ossasat.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/sata/host/sathw.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/ppbus/if_plip.c optional plip dev/ppbus/immio.c optional vpo dev/ppbus/lpbb.c optional lpbb dev/ppbus/lpt.c optional lpt dev/ppbus/pcfclock.c optional pcfclock dev/ppbus/ppb_1284.c optional ppbus dev/ppbus/ppb_base.c optional ppbus dev/ppbus/ppb_msq.c optional ppbus dev/ppbus/ppbconf.c optional ppbus dev/ppbus/ppbus_if.m optional ppbus dev/ppbus/ppi.c optional ppi dev/ppbus/pps.c optional pps dev/ppbus/vpo.c optional vpo dev/ppbus/vpoio.c optional vpo dev/ppc/ppc.c optional ppc dev/ppc/ppc_acpi.c optional ppc acpi dev/ppc/ppc_isa.c optional ppc isa dev/ppc/ppc_pci.c optional ppc pci dev/ppc/ppc_puc.c optional ppc puc dev/proto/proto_bus_isa.c optional proto acpi | proto isa dev/proto/proto_bus_pci.c optional proto pci dev/proto/proto_busdma.c optional proto dev/proto/proto_core.c optional proto dev/pst/pst-iop.c optional pst dev/pst/pst-pci.c optional pst pci dev/pst/pst-raid.c optional pst dev/pty/pty.c optional pty dev/puc/puc.c optional puc dev/puc/puc_cfg.c optional puc dev/puc/puc_pccard.c optional puc pccard dev/puc/puc_pci.c optional puc pci dev/puc/pucdata.c optional puc pci dev/quicc/quicc_core.c optional quicc dev/ral/rt2560.c optional ral dev/ral/rt2661.c optional ral dev/ral/rt2860.c optional ral dev/ral/if_ral_pci.c optional ral pci rt2561fw.c optional rt2561fw | ralfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rt2561.fw:rt2561fw -mrt2561 -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rt2561fw.c" rt2561fw.fwo optional rt2561fw | ralfw \ dependency "rt2561.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rt2561fw.fwo" rt2561.fw optional rt2561fw | ralfw \ dependency "$S/contrib/dev/ral/rt2561.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rt2561.fw" rt2561sfw.c optional rt2561sfw | ralfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rt2561s.fw:rt2561sfw -mrt2561s -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rt2561sfw.c" rt2561sfw.fwo optional rt2561sfw | ralfw \ dependency "rt2561s.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rt2561sfw.fwo" rt2561s.fw optional rt2561sfw | ralfw \ dependency "$S/contrib/dev/ral/rt2561s.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rt2561s.fw" rt2661fw.c optional rt2661fw | ralfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rt2661.fw:rt2661fw -mrt2661 -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rt2661fw.c" rt2661fw.fwo optional rt2661fw | ralfw \ dependency "rt2661.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rt2661fw.fwo" rt2661.fw optional rt2661fw | ralfw \ dependency "$S/contrib/dev/ral/rt2661.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rt2661.fw" rt2860fw.c optional rt2860fw | ralfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rt2860.fw:rt2860fw -mrt2860 -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rt2860fw.c" rt2860fw.fwo optional rt2860fw | ralfw \ dependency "rt2860.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rt2860fw.fwo" rt2860.fw optional rt2860fw | ralfw \ dependency "$S/contrib/dev/ral/rt2860.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rt2860.fw" dev/random/random_infra.c optional random dev/random/random_harvestq.c optional random dev/random/randomdev.c optional random random_yarrow | \ random !random_yarrow !random_loadable dev/random/yarrow.c optional random random_yarrow dev/random/fortuna.c optional random !random_yarrow !random_loadable dev/random/hash.c optional random random_yarrow | \ random !random_yarrow !random_loadable dev/rc/rc.c optional rc dev/rccgpio/rccgpio.c optional rccgpio gpio dev/re/if_re.c optional re dev/rl/if_rl.c optional rl pci dev/rndtest/rndtest.c optional rndtest dev/rp/rp.c optional rp dev/rp/rp_isa.c optional rp isa dev/rp/rp_pci.c optional rp pci dev/rtwn/if_rtwn.c optional rtwn rtwn-rtl8192cfwU.c optional rtwn-rtl8192cfwU | rtwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rtwn-rtl8192cfwU.fw:rtwn-rtl8192cfwU:111 -mrtwn-rtl8192cfwU -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rtwn-rtl8192cfwU.c" rtwn-rtl8192cfwU.fwo optional rtwn-rtl8192cfwU | rtwnfw \ dependency "rtwn-rtl8192cfwU.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rtwn-rtl8192cfwU.fwo" rtwn-rtl8192cfwU.fw optional rtwn-rtl8192cfwU | rtwnfw \ dependency "$S/contrib/dev/rtwn/rtwn-rtl8192cfwU.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rtwn-rtl8192cfwU.fw" rtwn-rtl8192cfwU_B.c optional rtwn-rtl8192cfwU_B | rtwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rtwn-rtl8192cfwU_B.fw:rtwn-rtl8192cfwU_B:111 -mrtwn-rtl8192cfwU_B -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rtwn-rtl8192cfwU_B.c" rtwn-rtl8192cfwU_B.fwo optional rtwn-rtl8192cfwU_B | rtwnfw \ dependency "rtwn-rtl8192cfwU_B.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rtwn-rtl8192cfwU_B.fwo" rtwn-rtl8192cfwU_B.fw optional rtwn-rtl8192cfwU_B | rtwnfw \ dependency "$S/contrib/dev/rtwn/rtwn-rtl8192cfwU_B.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rtwn-rtl8192cfwU_B.fw" dev/safe/safe.c optional safe dev/scc/scc_if.m optional scc dev/scc/scc_bfe_ebus.c optional scc ebus dev/scc/scc_bfe_quicc.c optional scc quicc dev/scc/scc_bfe_sbus.c optional scc fhc | scc sbus dev/scc/scc_core.c optional scc dev/scc/scc_dev_quicc.c optional scc quicc dev/scc/scc_dev_sab82532.c optional scc dev/scc/scc_dev_z8530.c optional scc dev/sdhci/sdhci.c optional sdhci dev/sdhci/sdhci_if.m optional sdhci dev/sdhci/sdhci_pci.c optional sdhci pci dev/sf/if_sf.c optional sf pci dev/sge/if_sge.c optional sge pci dev/siba/siba_bwn.c optional siba_bwn pci dev/siba/siba_core.c optional siba_bwn pci dev/siis/siis.c optional siis pci dev/sis/if_sis.c optional sis pci dev/sk/if_sk.c optional sk pci dev/smbus/smb.c optional smb dev/smbus/smbconf.c optional smbus dev/smbus/smbus.c optional smbus dev/smbus/smbus_if.m optional smbus dev/smc/if_smc.c optional smc dev/smc/if_smc_fdt.c optional smc fdt dev/sn/if_sn.c optional sn dev/sn/if_sn_isa.c optional sn isa dev/sn/if_sn_pccard.c optional sn pccard dev/snp/snp.c optional snp dev/sound/clone.c optional sound dev/sound/unit.c optional sound dev/sound/isa/ad1816.c optional snd_ad1816 isa dev/sound/isa/ess.c optional snd_ess isa dev/sound/isa/gusc.c optional snd_gusc isa dev/sound/isa/mss.c optional snd_mss isa dev/sound/isa/sb16.c optional snd_sb16 isa dev/sound/isa/sb8.c optional snd_sb8 isa dev/sound/isa/sbc.c optional snd_sbc isa dev/sound/isa/sndbuf_dma.c optional sound isa dev/sound/pci/als4000.c optional snd_als4000 pci dev/sound/pci/atiixp.c optional snd_atiixp pci dev/sound/pci/cmi.c optional snd_cmi pci dev/sound/pci/cs4281.c optional snd_cs4281 pci dev/sound/pci/csa.c optional snd_csa pci dev/sound/pci/csapcm.c optional snd_csa pci dev/sound/pci/ds1.c optional snd_ds1 pci dev/sound/pci/emu10k1.c optional snd_emu10k1 pci dev/sound/pci/emu10kx.c optional snd_emu10kx pci dev/sound/pci/emu10kx-pcm.c optional snd_emu10kx pci dev/sound/pci/emu10kx-midi.c optional snd_emu10kx pci dev/sound/pci/envy24.c optional snd_envy24 pci dev/sound/pci/envy24ht.c optional snd_envy24ht pci dev/sound/pci/es137x.c optional snd_es137x pci dev/sound/pci/fm801.c optional snd_fm801 pci dev/sound/pci/ich.c optional snd_ich pci dev/sound/pci/maestro.c optional snd_maestro pci dev/sound/pci/maestro3.c optional snd_maestro3 pci dev/sound/pci/neomagic.c optional snd_neomagic pci dev/sound/pci/solo.c optional snd_solo pci dev/sound/pci/spicds.c optional snd_spicds pci dev/sound/pci/t4dwave.c optional snd_t4dwave pci dev/sound/pci/via8233.c optional snd_via8233 pci dev/sound/pci/via82c686.c optional snd_via82c686 pci dev/sound/pci/vibes.c optional snd_vibes pci dev/sound/pci/hda/hdaa.c optional snd_hda pci dev/sound/pci/hda/hdaa_patches.c optional snd_hda pci dev/sound/pci/hda/hdac.c optional snd_hda pci dev/sound/pci/hda/hdac_if.m optional snd_hda pci dev/sound/pci/hda/hdacc.c optional snd_hda pci dev/sound/pci/hdspe.c optional snd_hdspe pci dev/sound/pci/hdspe-pcm.c optional snd_hdspe pci dev/sound/pcm/ac97.c optional sound dev/sound/pcm/ac97_if.m optional sound dev/sound/pcm/ac97_patch.c optional sound dev/sound/pcm/buffer.c optional sound \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/channel.c optional sound dev/sound/pcm/channel_if.m optional sound dev/sound/pcm/dsp.c optional sound dev/sound/pcm/feeder.c optional sound dev/sound/pcm/feeder_chain.c optional sound dev/sound/pcm/feeder_eq.c optional sound \ dependency "feeder_eq_gen.h" \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/feeder_if.m optional sound dev/sound/pcm/feeder_format.c optional sound \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/feeder_matrix.c optional sound \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/feeder_mixer.c optional sound \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/feeder_rate.c optional sound \ dependency "feeder_rate_gen.h" \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/feeder_volume.c optional sound \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/mixer.c optional sound dev/sound/pcm/mixer_if.m optional sound dev/sound/pcm/sndstat.c optional sound dev/sound/pcm/sound.c optional sound dev/sound/pcm/vchan.c optional sound dev/sound/usb/uaudio.c optional snd_uaudio usb dev/sound/usb/uaudio_pcm.c optional snd_uaudio usb dev/sound/midi/midi.c optional sound dev/sound/midi/mpu401.c optional sound dev/sound/midi/mpu_if.m optional sound dev/sound/midi/mpufoi_if.m optional sound dev/sound/midi/sequencer.c optional sound dev/sound/midi/synth_if.m optional sound dev/spibus/ofw_spibus.c optional fdt spibus dev/spibus/spibus.c optional spibus \ dependency "spibus_if.h" dev/spibus/spigen.c optional spigen dev/spibus/spibus_if.m optional spibus dev/ste/if_ste.c optional ste pci dev/stg/tmc18c30.c optional stg dev/stg/tmc18c30_isa.c optional stg isa dev/stg/tmc18c30_pccard.c optional stg pccard dev/stg/tmc18c30_pci.c optional stg pci dev/stg/tmc18c30_subr.c optional stg dev/stge/if_stge.c optional stge dev/streams/streams.c optional streams dev/sym/sym_hipd.c optional sym \ dependency "$S/dev/sym/sym_{conf,defs}.h" dev/syscons/blank/blank_saver.c optional blank_saver dev/syscons/daemon/daemon_saver.c optional daemon_saver dev/syscons/dragon/dragon_saver.c optional dragon_saver dev/syscons/fade/fade_saver.c optional fade_saver dev/syscons/fire/fire_saver.c optional fire_saver dev/syscons/green/green_saver.c optional green_saver dev/syscons/logo/logo.c optional logo_saver dev/syscons/logo/logo_saver.c optional logo_saver dev/syscons/rain/rain_saver.c optional rain_saver dev/syscons/schistory.c optional sc dev/syscons/scmouse.c optional sc dev/syscons/scterm.c optional sc dev/syscons/scvidctl.c optional sc dev/syscons/snake/snake_saver.c optional snake_saver dev/syscons/star/star_saver.c optional star_saver dev/syscons/syscons.c optional sc dev/syscons/sysmouse.c optional sc dev/syscons/warp/warp_saver.c optional warp_saver dev/tdfx/tdfx_linux.c optional tdfx_linux tdfx compat_linux dev/tdfx/tdfx_pci.c optional tdfx pci dev/ti/if_ti.c optional ti pci dev/tl/if_tl.c optional tl pci dev/trm/trm.c optional trm dev/twa/tw_cl_init.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twa/tw_cl_intr.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twa/tw_cl_io.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twa/tw_cl_misc.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twa/tw_osl_cam.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twa/tw_osl_freebsd.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twe/twe.c optional twe dev/twe/twe_freebsd.c optional twe dev/tws/tws.c optional tws dev/tws/tws_cam.c optional tws dev/tws/tws_hdm.c optional tws dev/tws/tws_services.c optional tws dev/tws/tws_user.c optional tws dev/tx/if_tx.c optional tx dev/txp/if_txp.c optional txp dev/uart/uart_bus_acpi.c optional uart acpi dev/uart/uart_bus_ebus.c optional uart ebus dev/uart/uart_bus_fdt.c optional uart fdt dev/uart/uart_bus_isa.c optional uart isa dev/uart/uart_bus_pccard.c optional uart pccard dev/uart/uart_bus_pci.c optional uart pci dev/uart/uart_bus_puc.c optional uart puc dev/uart/uart_bus_scc.c optional uart scc dev/uart/uart_core.c optional uart dev/uart/uart_dbg.c optional uart gdb dev/uart/uart_dev_ns8250.c optional uart uart_ns8250 | uart uart_snps dev/uart/uart_dev_pl011.c optional uart pl011 dev/uart/uart_dev_quicc.c optional uart quicc dev/uart/uart_dev_sab82532.c optional uart uart_sab82532 dev/uart/uart_dev_sab82532.c optional uart scc dev/uart/uart_dev_snps.c optional uart uart_snps dev/uart/uart_dev_z8530.c optional uart uart_z8530 dev/uart/uart_dev_z8530.c optional uart scc dev/uart/uart_if.m optional uart dev/uart/uart_subr.c optional uart dev/uart/uart_tty.c optional uart dev/ubsec/ubsec.c optional ubsec # # USB controller drivers # dev/usb/controller/at91dci.c optional at91dci dev/usb/controller/at91dci_atmelarm.c optional at91dci at91rm9200 dev/usb/controller/musb_otg.c optional musb dev/usb/controller/musb_otg_atmelarm.c optional musb at91rm9200 dev/usb/controller/dwc_otg.c optional dwcotg dev/usb/controller/dwc_otg_fdt.c optional dwcotg fdt dev/usb/controller/ehci.c optional ehci dev/usb/controller/ehci_pci.c optional ehci pci dev/usb/controller/ohci.c optional ohci dev/usb/controller/ohci_pci.c optional ohci pci dev/usb/controller/uhci.c optional uhci dev/usb/controller/uhci_pci.c optional uhci pci dev/usb/controller/xhci.c optional xhci dev/usb/controller/xhci_pci.c optional xhci pci dev/usb/controller/saf1761_otg.c optional saf1761otg dev/usb/controller/saf1761_otg_fdt.c optional saf1761otg fdt dev/usb/controller/uss820dci.c optional uss820dci dev/usb/controller/uss820dci_atmelarm.c optional uss820dci at91rm9200 dev/usb/controller/usb_controller.c optional usb # # USB storage drivers # dev/usb/storage/umass.c optional umass dev/usb/storage/urio.c optional urio dev/usb/storage/ustorage_fs.c optional usfs # # USB core # dev/usb/usb_busdma.c optional usb dev/usb/usb_core.c optional usb dev/usb/usb_debug.c optional usb dev/usb/usb_dev.c optional usb dev/usb/usb_device.c optional usb dev/usb/usb_dynamic.c optional usb dev/usb/usb_error.c optional usb dev/usb/usb_generic.c optional usb dev/usb/usb_handle_request.c optional usb dev/usb/usb_hid.c optional usb dev/usb/usb_hub.c optional usb dev/usb/usb_if.m optional usb dev/usb/usb_lookup.c optional usb dev/usb/usb_mbuf.c optional usb dev/usb/usb_msctest.c optional usb dev/usb/usb_parse.c optional usb dev/usb/usb_pf.c optional usb dev/usb/usb_process.c optional usb dev/usb/usb_request.c optional usb dev/usb/usb_transfer.c optional usb dev/usb/usb_util.c optional usb # # USB network drivers # dev/usb/net/if_aue.c optional aue dev/usb/net/if_axe.c optional axe dev/usb/net/if_axge.c optional axge dev/usb/net/if_cdce.c optional cdce dev/usb/net/if_cue.c optional cue dev/usb/net/if_ipheth.c optional ipheth dev/usb/net/if_kue.c optional kue dev/usb/net/if_mos.c optional mos dev/usb/net/if_rue.c optional rue dev/usb/net/if_smsc.c optional smsc dev/usb/net/if_udav.c optional udav dev/usb/net/if_ure.c optional ure dev/usb/net/if_usie.c optional usie dev/usb/net/if_urndis.c optional urndis dev/usb/net/ruephy.c optional rue dev/usb/net/usb_ethernet.c optional uether | aue | axe | axge | cdce | \ cue | ipheth | kue | mos | rue | \ smsc | udav | ure | urndis dev/usb/net/uhso.c optional uhso # # USB WLAN drivers # dev/usb/wlan/if_rsu.c optional rsu rsu-rtl8712fw.c optional rsu-rtl8712fw | rsufw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rsu-rtl8712fw.fw:rsu-rtl8712fw:120 -mrsu-rtl8712fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rsu-rtl8712fw.c" rsu-rtl8712fw.fwo optional rsu-rtl8712fw | rsufw \ dependency "rsu-rtl8712fw.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rsu-rtl8712fw.fwo" rsu-rtl8712fw.fw optional rsu-rtl8712.fw | rsufw \ dependency "$S/contrib/dev/rsu/rsu-rtl8712fw.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rsu-rtl8712fw.fw" dev/usb/wlan/if_rum.c optional rum dev/usb/wlan/if_run.c optional run runfw.c optional runfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk run.fw:runfw -mrunfw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "runfw.c" runfw.fwo optional runfw \ dependency "run.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "runfw.fwo" run.fw optional runfw \ dependency "$S/contrib/dev/run/rt2870.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "run.fw" dev/usb/wlan/if_uath.c optional uath dev/usb/wlan/if_upgt.c optional upgt dev/usb/wlan/if_ural.c optional ural dev/usb/wlan/if_urtw.c optional urtw dev/usb/wlan/if_zyd.c optional zyd # # USB serial and parallel port drivers # dev/usb/serial/u3g.c optional u3g dev/usb/serial/uark.c optional uark dev/usb/serial/ubsa.c optional ubsa dev/usb/serial/ubser.c optional ubser dev/usb/serial/uchcom.c optional uchcom dev/usb/serial/ucycom.c optional ucycom dev/usb/serial/ufoma.c optional ufoma dev/usb/serial/uftdi.c optional uftdi dev/usb/serial/ugensa.c optional ugensa dev/usb/serial/uipaq.c optional uipaq dev/usb/serial/ulpt.c optional ulpt dev/usb/serial/umcs.c optional umcs dev/usb/serial/umct.c optional umct dev/usb/serial/umodem.c optional umodem dev/usb/serial/umoscom.c optional umoscom dev/usb/serial/uplcom.c optional uplcom dev/usb/serial/uslcom.c optional uslcom dev/usb/serial/uvisor.c optional uvisor dev/usb/serial/uvscom.c optional uvscom dev/usb/serial/usb_serial.c optional ucom | u3g | uark | ubsa | ubser | \ uchcom | ucycom | ufoma | uftdi | \ ugensa | uipaq | umcs | umct | \ umodem | umoscom | uplcom | usie | \ uslcom | uvisor | uvscom # # USB misc drivers # dev/usb/misc/ufm.c optional ufm dev/usb/misc/udbp.c optional udbp dev/usb/misc/ugold.c optional ugold dev/usb/misc/uled.c optional uled # # USB input drivers # dev/usb/input/atp.c optional atp dev/usb/input/uep.c optional uep dev/usb/input/uhid.c optional uhid dev/usb/input/ukbd.c optional ukbd dev/usb/input/ums.c optional ums dev/usb/input/wsp.c optional wsp # # USB quirks # dev/usb/quirk/usb_quirk.c optional usb # # USB templates # dev/usb/template/usb_template.c optional usb_template dev/usb/template/usb_template_audio.c optional usb_template dev/usb/template/usb_template_cdce.c optional usb_template dev/usb/template/usb_template_kbd.c optional usb_template dev/usb/template/usb_template_modem.c optional usb_template dev/usb/template/usb_template_mouse.c optional usb_template dev/usb/template/usb_template_msc.c optional usb_template dev/usb/template/usb_template_mtp.c optional usb_template dev/usb/template/usb_template_phone.c optional usb_template dev/usb/template/usb_template_serialnet.c optional usb_template dev/usb/template/usb_template_midi.c optional usb_template # # USB video drivers # dev/usb/video/udl.c optional udl # # USB END # dev/videomode/videomode.c optional videomode dev/videomode/edid.c optional videomode dev/videomode/pickmode.c optional videomode dev/videomode/vesagtf.c optional videomode dev/utopia/idtphy.c optional utopia dev/utopia/suni.c optional utopia dev/utopia/utopia.c optional utopia dev/vge/if_vge.c optional vge dev/viapm/viapm.c optional viapm pci dev/virtio/virtio.c optional virtio dev/virtio/virtqueue.c optional virtio dev/virtio/virtio_bus_if.m optional virtio dev/virtio/virtio_if.m optional virtio dev/virtio/pci/virtio_pci.c optional virtio_pci dev/virtio/mmio/virtio_mmio.c optional virtio_mmio dev/virtio/mmio/virtio_mmio_if.m optional virtio_mmio dev/virtio/network/if_vtnet.c optional vtnet dev/virtio/block/virtio_blk.c optional virtio_blk dev/virtio/balloon/virtio_balloon.c optional virtio_balloon dev/virtio/scsi/virtio_scsi.c optional virtio_scsi dev/virtio/random/virtio_random.c optional virtio_random dev/virtio/console/virtio_console.c optional virtio_console dev/vkbd/vkbd.c optional vkbd dev/vr/if_vr.c optional vr pci dev/vt/colors/vt_termcolors.c optional vt dev/vt/font/vt_font_default.c optional vt dev/vt/font/vt_mouse_cursor.c optional vt dev/vt/hw/efifb/efifb.c optional vt_efifb dev/vt/hw/fb/vt_fb.c optional vt dev/vt/hw/vga/vt_vga.c optional vt vt_vga dev/vt/logo/logo_freebsd.c optional vt splash dev/vt/logo/logo_beastie.c optional vt splash dev/vt/vt_buf.c optional vt dev/vt/vt_consolectl.c optional vt dev/vt/vt_core.c optional vt dev/vt/vt_cpulogos.c optional vt splash dev/vt/vt_font.c optional vt dev/vt/vt_sysmouse.c optional vt dev/vte/if_vte.c optional vte pci dev/vx/if_vx.c optional vx dev/vx/if_vx_eisa.c optional vx eisa dev/vx/if_vx_pci.c optional vx pci dev/vxge/vxge.c optional vxge dev/vxge/vxgehal/vxgehal-ifmsg.c optional vxge dev/vxge/vxgehal/vxgehal-mrpcim.c optional vxge dev/vxge/vxgehal/vxge-queue.c optional vxge dev/vxge/vxgehal/vxgehal-ring.c optional vxge dev/vxge/vxgehal/vxgehal-swapper.c optional vxge dev/vxge/vxgehal/vxgehal-mgmt.c optional vxge dev/vxge/vxgehal/vxgehal-srpcim.c optional vxge dev/vxge/vxgehal/vxgehal-config.c optional vxge dev/vxge/vxgehal/vxgehal-blockpool.c optional vxge dev/vxge/vxgehal/vxgehal-doorbells.c optional vxge dev/vxge/vxgehal/vxgehal-mgmtaux.c optional vxge dev/vxge/vxgehal/vxgehal-device.c optional vxge dev/vxge/vxgehal/vxgehal-mm.c optional vxge dev/vxge/vxgehal/vxgehal-driver.c optional vxge dev/vxge/vxgehal/vxgehal-virtualpath.c optional vxge dev/vxge/vxgehal/vxgehal-channel.c optional vxge dev/vxge/vxgehal/vxgehal-fifo.c optional vxge dev/watchdog/watchdog.c standard dev/wb/if_wb.c optional wb pci dev/wi/if_wi.c optional wi dev/wi/if_wi_pccard.c optional wi pccard dev/wi/if_wi_pci.c optional wi pci dev/wpi/if_wpi.c optional wpi pci wpifw.c optional wpifw \ compile-with "${AWK} -f $S/tools/fw_stub.awk wpi.fw:wpifw:153229 -mwpi -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "wpifw.c" wpifw.fwo optional wpifw \ dependency "wpi.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "wpifw.fwo" wpi.fw optional wpifw \ dependency "$S/contrib/dev/wpi/iwlwifi-3945-15.32.2.9.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "wpi.fw" dev/xe/if_xe.c optional xe dev/xe/if_xe_pccard.c optional xe pccard dev/xen/balloon/balloon.c optional xenhvm dev/xen/blkfront/blkfront.c optional xenhvm dev/xen/blkback/blkback.c optional xenhvm dev/xen/console/xen_console.c optional xenhvm dev/xen/control/control.c optional xenhvm dev/xen/grant_table/grant_table.c optional xenhvm dev/xen/netback/netback.c optional xenhvm dev/xen/netfront/netfront.c optional xenhvm dev/xen/xenpci/xenpci.c optional xenpci dev/xen/timer/timer.c optional xenhvm dev/xen/pvcpu/pvcpu.c optional xenhvm dev/xen/xenstore/xenstore.c optional xenhvm dev/xen/xenstore/xenstore_dev.c optional xenhvm dev/xen/xenstore/xenstored_dev.c optional xenhvm dev/xen/evtchn/evtchn_dev.c optional xenhvm dev/xen/privcmd/privcmd.c optional xenhvm dev/xen/debug/debug.c optional xenhvm dev/xl/if_xl.c optional xl pci dev/xl/xlphy.c optional xl pci fs/autofs/autofs.c optional autofs fs/autofs/autofs_vfsops.c optional autofs fs/autofs/autofs_vnops.c optional autofs fs/deadfs/dead_vnops.c standard fs/devfs/devfs_devs.c standard fs/devfs/devfs_dir.c standard fs/devfs/devfs_rule.c standard fs/devfs/devfs_vfsops.c standard fs/devfs/devfs_vnops.c standard fs/fdescfs/fdesc_vfsops.c optional fdescfs fs/fdescfs/fdesc_vnops.c optional fdescfs fs/fifofs/fifo_vnops.c standard fs/cuse/cuse.c optional cuse fs/fuse/fuse_device.c optional fuse fs/fuse/fuse_file.c optional fuse fs/fuse/fuse_internal.c optional fuse fs/fuse/fuse_io.c optional fuse fs/fuse/fuse_ipc.c optional fuse fs/fuse/fuse_main.c optional fuse fs/fuse/fuse_node.c optional fuse fs/fuse/fuse_vfsops.c optional fuse fs/fuse/fuse_vnops.c optional fuse fs/msdosfs/msdosfs_conv.c optional msdosfs fs/msdosfs/msdosfs_denode.c optional msdosfs fs/msdosfs/msdosfs_fat.c optional msdosfs fs/msdosfs/msdosfs_fileno.c optional msdosfs fs/msdosfs/msdosfs_iconv.c optional msdosfs_iconv fs/msdosfs/msdosfs_lookup.c optional msdosfs fs/msdosfs/msdosfs_vfsops.c optional msdosfs fs/msdosfs/msdosfs_vnops.c optional msdosfs fs/nandfs/bmap.c optional nandfs fs/nandfs/nandfs_alloc.c optional nandfs fs/nandfs/nandfs_bmap.c optional nandfs fs/nandfs/nandfs_buffer.c optional nandfs fs/nandfs/nandfs_cleaner.c optional nandfs fs/nandfs/nandfs_cpfile.c optional nandfs fs/nandfs/nandfs_dat.c optional nandfs fs/nandfs/nandfs_dir.c optional nandfs fs/nandfs/nandfs_ifile.c optional nandfs fs/nandfs/nandfs_segment.c optional nandfs fs/nandfs/nandfs_subr.c optional nandfs fs/nandfs/nandfs_sufile.c optional nandfs fs/nandfs/nandfs_vfsops.c optional nandfs fs/nandfs/nandfs_vnops.c optional nandfs fs/nfs/nfs_commonkrpc.c optional nfscl | nfsd fs/nfs/nfs_commonsubs.c optional nfscl | nfsd fs/nfs/nfs_commonport.c optional nfscl | nfsd fs/nfs/nfs_commonacl.c optional nfscl | nfsd fs/nfsclient/nfs_clcomsubs.c optional nfscl fs/nfsclient/nfs_clsubs.c optional nfscl fs/nfsclient/nfs_clstate.c optional nfscl fs/nfsclient/nfs_clkrpc.c optional nfscl fs/nfsclient/nfs_clrpcops.c optional nfscl fs/nfsclient/nfs_clvnops.c optional nfscl fs/nfsclient/nfs_clnode.c optional nfscl fs/nfsclient/nfs_clvfsops.c optional nfscl fs/nfsclient/nfs_clport.c optional nfscl fs/nfsclient/nfs_clbio.c optional nfscl fs/nfsclient/nfs_clnfsiod.c optional nfscl fs/nfsserver/nfs_fha_new.c optional nfsd inet fs/nfsserver/nfs_nfsdsocket.c optional nfsd inet fs/nfsserver/nfs_nfsdsubs.c optional nfsd inet fs/nfsserver/nfs_nfsdstate.c optional nfsd inet fs/nfsserver/nfs_nfsdkrpc.c optional nfsd inet fs/nfsserver/nfs_nfsdserv.c optional nfsd inet fs/nfsserver/nfs_nfsdport.c optional nfsd inet fs/nfsserver/nfs_nfsdcache.c optional nfsd inet fs/nullfs/null_subr.c optional nullfs fs/nullfs/null_vfsops.c optional nullfs fs/nullfs/null_vnops.c optional nullfs fs/procfs/procfs.c optional procfs fs/procfs/procfs_ctl.c optional procfs fs/procfs/procfs_dbregs.c optional procfs fs/procfs/procfs_fpregs.c optional procfs fs/procfs/procfs_ioctl.c optional procfs fs/procfs/procfs_map.c optional procfs fs/procfs/procfs_mem.c optional procfs fs/procfs/procfs_note.c optional procfs fs/procfs/procfs_osrel.c optional procfs fs/procfs/procfs_regs.c optional procfs fs/procfs/procfs_rlimit.c optional procfs fs/procfs/procfs_status.c optional procfs fs/procfs/procfs_type.c optional procfs fs/pseudofs/pseudofs.c optional pseudofs fs/pseudofs/pseudofs_fileno.c optional pseudofs fs/pseudofs/pseudofs_vncache.c optional pseudofs fs/pseudofs/pseudofs_vnops.c optional pseudofs fs/smbfs/smbfs_io.c optional smbfs fs/smbfs/smbfs_node.c optional smbfs fs/smbfs/smbfs_smb.c optional smbfs fs/smbfs/smbfs_subr.c optional smbfs fs/smbfs/smbfs_vfsops.c optional smbfs fs/smbfs/smbfs_vnops.c optional smbfs fs/udf/osta.c optional udf fs/udf/udf_iconv.c optional udf_iconv fs/udf/udf_vfsops.c optional udf fs/udf/udf_vnops.c optional udf fs/unionfs/union_subr.c optional unionfs fs/unionfs/union_vfsops.c optional unionfs fs/unionfs/union_vnops.c optional unionfs fs/tmpfs/tmpfs_vnops.c optional tmpfs fs/tmpfs/tmpfs_fifoops.c optional tmpfs fs/tmpfs/tmpfs_vfsops.c optional tmpfs fs/tmpfs/tmpfs_subr.c optional tmpfs gdb/gdb_cons.c optional gdb gdb/gdb_main.c optional gdb gdb/gdb_packet.c optional gdb geom/bde/g_bde.c optional geom_bde geom/bde/g_bde_crypt.c optional geom_bde geom/bde/g_bde_lock.c optional geom_bde geom/bde/g_bde_work.c optional geom_bde geom/cache/g_cache.c optional geom_cache geom/concat/g_concat.c optional geom_concat geom/eli/g_eli.c optional geom_eli geom/eli/g_eli_crypto.c optional geom_eli geom/eli/g_eli_ctl.c optional geom_eli geom/eli/g_eli_hmac.c optional geom_eli geom/eli/g_eli_integrity.c optional geom_eli geom/eli/g_eli_key.c optional geom_eli geom/eli/g_eli_key_cache.c optional geom_eli geom/eli/g_eli_privacy.c optional geom_eli geom/eli/pkcs5v2.c optional geom_eli geom/gate/g_gate.c optional geom_gate geom/geom_aes.c optional geom_aes geom/geom_bsd.c optional geom_bsd geom/geom_bsd_enc.c optional geom_bsd | geom_part_bsd geom/geom_ccd.c optional ccd | geom_ccd geom/geom_ctl.c standard geom/geom_dev.c standard geom/geom_disk.c standard geom/geom_dump.c standard geom/geom_event.c standard geom/geom_fox.c optional geom_fox geom/geom_flashmap.c optional fdt cfi | fdt nand | fdt mx25l geom/geom_io.c standard geom/geom_kern.c standard geom/geom_map.c optional geom_map geom/geom_mbr.c optional geom_mbr geom/geom_mbr_enc.c optional geom_mbr geom/geom_pc98.c optional geom_pc98 geom/geom_pc98_enc.c optional geom_pc98 geom/geom_redboot.c optional geom_redboot geom/geom_slice.c standard geom/geom_subr.c standard geom/geom_sunlabel.c optional geom_sunlabel geom/geom_sunlabel_enc.c optional geom_sunlabel geom/geom_vfs.c standard geom/geom_vol_ffs.c optional geom_vol geom/journal/g_journal.c optional geom_journal geom/journal/g_journal_ufs.c optional geom_journal geom/label/g_label.c optional geom_label | geom_label_gpt geom/label/g_label_ext2fs.c optional geom_label geom/label/g_label_iso9660.c optional geom_label geom/label/g_label_msdosfs.c optional geom_label geom/label/g_label_ntfs.c optional geom_label geom/label/g_label_reiserfs.c optional geom_label geom/label/g_label_ufs.c optional geom_label geom/label/g_label_gpt.c optional geom_label | geom_label_gpt geom/label/g_label_disk_ident.c optional geom_label geom/linux_lvm/g_linux_lvm.c optional geom_linux_lvm geom/mirror/g_mirror.c optional geom_mirror geom/mirror/g_mirror_ctl.c optional geom_mirror geom/mountver/g_mountver.c optional geom_mountver geom/multipath/g_multipath.c optional geom_multipath geom/nop/g_nop.c optional geom_nop geom/part/g_part.c standard geom/part/g_part_if.m standard geom/part/g_part_apm.c optional geom_part_apm geom/part/g_part_bsd.c optional geom_part_bsd geom/part/g_part_bsd64.c optional geom_part_bsd64 geom/part/g_part_ebr.c optional geom_part_ebr geom/part/g_part_gpt.c optional geom_part_gpt geom/part/g_part_ldm.c optional geom_part_ldm geom/part/g_part_mbr.c optional geom_part_mbr geom/part/g_part_pc98.c optional geom_part_pc98 geom/part/g_part_vtoc8.c optional geom_part_vtoc8 geom/raid/g_raid.c optional geom_raid geom/raid/g_raid_ctl.c optional geom_raid geom/raid/g_raid_md_if.m optional geom_raid geom/raid/g_raid_tr_if.m optional geom_raid geom/raid/md_ddf.c optional geom_raid geom/raid/md_intel.c optional geom_raid geom/raid/md_jmicron.c optional geom_raid geom/raid/md_nvidia.c optional geom_raid geom/raid/md_promise.c optional geom_raid geom/raid/md_sii.c optional geom_raid geom/raid/tr_concat.c optional geom_raid geom/raid/tr_raid0.c optional geom_raid geom/raid/tr_raid1.c optional geom_raid geom/raid/tr_raid1e.c optional geom_raid geom/raid/tr_raid5.c optional geom_raid geom/raid3/g_raid3.c optional geom_raid3 geom/raid3/g_raid3_ctl.c optional geom_raid3 geom/shsec/g_shsec.c optional geom_shsec geom/stripe/g_stripe.c optional geom_stripe contrib/xz-embedded/freebsd/xz_malloc.c \ optional xz_embedded | geom_uzip \ compile-with "${NORMAL_C} -I$S/contrib/xz-embedded/freebsd/ -I$S/contrib/xz-embedded/linux/lib/xz/ -I$S/contrib/xz-embedded/linux/include/linux/" contrib/xz-embedded/linux/lib/xz/xz_crc32.c \ optional xz_embedded | geom_uzip \ compile-with "${NORMAL_C} -I$S/contrib/xz-embedded/freebsd/ -I$S/contrib/xz-embedded/linux/lib/xz/ -I$S/contrib/xz-embedded/linux/include/linux/" contrib/xz-embedded/linux/lib/xz/xz_dec_bcj.c \ optional xz_embedded | geom_uzip \ compile-with "${NORMAL_C} -I$S/contrib/xz-embedded/freebsd/ -I$S/contrib/xz-embedded/linux/lib/xz/ -I$S/contrib/xz-embedded/linux/include/linux/" contrib/xz-embedded/linux/lib/xz/xz_dec_lzma2.c \ optional xz_embedded | geom_uzip \ compile-with "${NORMAL_C} -I$S/contrib/xz-embedded/freebsd/ -I$S/contrib/xz-embedded/linux/lib/xz/ -I$S/contrib/xz-embedded/linux/include/linux/" contrib/xz-embedded/linux/lib/xz/xz_dec_stream.c \ optional xz_embedded | geom_uzip \ compile-with "${NORMAL_C} -I$S/contrib/xz-embedded/freebsd/ -I$S/contrib/xz-embedded/linux/lib/xz/ -I$S/contrib/xz-embedded/linux/include/linux/" geom/uzip/g_uzip.c optional geom_uzip geom/uzip/g_uzip_lzma.c optional geom_uzip geom/uzip/g_uzip_wrkthr.c optional geom_uzip geom/uzip/g_uzip_zlib.c optional geom_uzip geom/vinum/geom_vinum.c optional geom_vinum geom/vinum/geom_vinum_create.c optional geom_vinum geom/vinum/geom_vinum_drive.c optional geom_vinum geom/vinum/geom_vinum_plex.c optional geom_vinum geom/vinum/geom_vinum_volume.c optional geom_vinum geom/vinum/geom_vinum_subr.c optional geom_vinum geom/vinum/geom_vinum_raid5.c optional geom_vinum geom/vinum/geom_vinum_share.c optional geom_vinum geom/vinum/geom_vinum_list.c optional geom_vinum geom/vinum/geom_vinum_rm.c optional geom_vinum geom/vinum/geom_vinum_init.c optional geom_vinum geom/vinum/geom_vinum_state.c optional geom_vinum geom/vinum/geom_vinum_rename.c optional geom_vinum geom/vinum/geom_vinum_move.c optional geom_vinum geom/vinum/geom_vinum_events.c optional geom_vinum geom/virstor/binstream.c optional geom_virstor geom/virstor/g_virstor.c optional geom_virstor geom/virstor/g_virstor_md.c optional geom_virstor geom/zero/g_zero.c optional geom_zero fs/ext2fs/ext2_alloc.c optional ext2fs fs/ext2fs/ext2_balloc.c optional ext2fs fs/ext2fs/ext2_bmap.c optional ext2fs fs/ext2fs/ext2_extents.c optional ext2fs fs/ext2fs/ext2_inode.c optional ext2fs fs/ext2fs/ext2_inode_cnv.c optional ext2fs fs/ext2fs/ext2_hash.c optional ext2fs fs/ext2fs/ext2_htree.c optional ext2fs fs/ext2fs/ext2_lookup.c optional ext2fs fs/ext2fs/ext2_subr.c optional ext2fs fs/ext2fs/ext2_vfsops.c optional ext2fs fs/ext2fs/ext2_vnops.c optional ext2fs # isa/isa_if.m standard isa/isa_common.c optional isa isa/isahint.c optional isa isa/pnp.c optional isa isapnp isa/pnpparse.c optional isa isapnp fs/cd9660/cd9660_bmap.c optional cd9660 fs/cd9660/cd9660_lookup.c optional cd9660 fs/cd9660/cd9660_node.c optional cd9660 fs/cd9660/cd9660_rrip.c optional cd9660 fs/cd9660/cd9660_util.c optional cd9660 fs/cd9660/cd9660_vfsops.c optional cd9660 fs/cd9660/cd9660_vnops.c optional cd9660 fs/cd9660/cd9660_iconv.c optional cd9660_iconv kern/bus_if.m standard kern/clock_if.m standard kern/cpufreq_if.m standard kern/device_if.m standard kern/imgact_binmisc.c optional imagact_binmisc kern/imgact_elf.c standard kern/imgact_elf32.c optional compat_freebsd32 kern/imgact_shell.c standard kern/inflate.c optional gzip kern/init_main.c standard kern/init_sysent.c standard kern/ksched.c optional _kposix_priority_scheduling kern/kern_acct.c standard kern/kern_alq.c optional alq kern/kern_clock.c standard kern/kern_condvar.c standard kern/kern_conf.c standard kern/kern_cons.c standard kern/kern_cpu.c standard kern/kern_cpuset.c standard kern/kern_context.c standard kern/kern_descrip.c standard kern/kern_dtrace.c optional kdtrace_hooks kern/kern_dump.c standard kern/kern_environment.c standard kern/kern_et.c standard kern/kern_event.c standard kern/kern_exec.c standard kern/kern_exit.c standard kern/kern_fail.c standard kern/kern_ffclock.c standard kern/kern_fork.c standard kern/kern_gzio.c optional gzio kern/kern_hhook.c standard kern/kern_idle.c standard kern/kern_intr.c standard kern/kern_jail.c standard kern/kern_khelp.c standard kern/kern_kthread.c standard kern/kern_ktr.c optional ktr kern/kern_ktrace.c standard kern/kern_linker.c standard kern/kern_lock.c standard kern/kern_lockf.c standard kern/kern_lockstat.c optional kdtrace_hooks kern/kern_loginclass.c standard kern/kern_malloc.c standard kern/kern_mbuf.c standard kern/kern_mib.c standard kern/kern_module.c standard kern/kern_mtxpool.c standard kern/kern_mutex.c standard kern/kern_ntptime.c standard kern/kern_numa.c standard kern/kern_osd.c standard kern/kern_physio.c standard kern/kern_pmc.c standard kern/kern_poll.c optional device_polling kern/kern_priv.c standard kern/kern_proc.c standard kern/kern_procctl.c standard kern/kern_prot.c standard kern/kern_racct.c standard kern/kern_rangelock.c standard kern/kern_rctl.c standard kern/kern_resource.c standard kern/kern_rmlock.c standard kern/kern_rwlock.c standard kern/kern_sdt.c optional kdtrace_hooks kern/kern_sema.c standard kern/kern_sendfile.c standard kern/kern_sharedpage.c standard kern/kern_shutdown.c standard kern/kern_sig.c standard kern/kern_switch.c standard kern/kern_sx.c standard kern/kern_synch.c standard kern/kern_syscalls.c standard kern/kern_sysctl.c standard kern/kern_tc.c standard kern/kern_thr.c standard kern/kern_thread.c standard kern/kern_time.c standard kern/kern_timeout.c standard kern/kern_umtx.c standard kern/kern_uuid.c standard kern/kern_xxx.c standard kern/link_elf.c standard kern/linker_if.m standard kern/md4c.c optional netsmb kern/md5c.c standard kern/p1003_1b.c standard kern/posix4_mib.c standard kern/sched_4bsd.c optional sched_4bsd kern/sched_ule.c optional sched_ule kern/serdev_if.m standard kern/stack_protector.c standard \ compile-with "${NORMAL_C:N-fstack-protector*}" kern/subr_acl_nfs4.c optional ufs_acl | zfs kern/subr_acl_posix1e.c optional ufs_acl kern/subr_autoconf.c standard kern/subr_blist.c standard kern/subr_bus.c standard kern/subr_bus_dma.c standard kern/subr_bufring.c standard kern/subr_capability.c standard kern/subr_clock.c standard kern/subr_counter.c standard kern/subr_devstat.c standard kern/subr_disk.c standard kern/subr_eventhandler.c standard kern/subr_fattime.c standard kern/subr_firmware.c optional firmware kern/subr_gtaskqueue.c standard kern/subr_hash.c standard kern/subr_hints.c standard kern/subr_kdb.c standard kern/subr_kobj.c standard kern/subr_lock.c standard kern/subr_log.c standard kern/subr_mbpool.c optional libmbpool kern/subr_mchain.c optional libmchain kern/subr_module.c standard kern/subr_msgbuf.c standard kern/subr_param.c standard kern/subr_pcpu.c standard kern/subr_pctrie.c standard kern/subr_power.c standard kern/subr_prf.c standard kern/subr_prof.c standard kern/subr_rman.c standard kern/subr_rtc.c standard kern/subr_sbuf.c standard kern/subr_scanf.c standard kern/subr_sglist.c standard kern/subr_sleepqueue.c standard kern/subr_smp.c standard kern/subr_stack.c optional ddb | stack | ktr kern/subr_taskqueue.c standard kern/subr_terminal.c optional vt kern/subr_trap.c standard kern/subr_turnstile.c standard kern/subr_uio.c standard kern/subr_unit.c standard kern/subr_vmem.c standard kern/subr_witness.c optional witness kern/sys_capability.c standard kern/sys_generic.c standard kern/sys_pipe.c standard kern/sys_procdesc.c standard kern/sys_process.c standard kern/sys_socket.c standard kern/syscalls.c standard kern/sysv_ipc.c standard kern/sysv_msg.c optional sysvmsg kern/sysv_sem.c optional sysvsem kern/sysv_shm.c optional sysvshm kern/tty.c standard kern/tty_compat.c optional compat_43tty kern/tty_info.c standard kern/tty_inq.c standard kern/tty_outq.c standard kern/tty_pts.c standard kern/tty_tty.c standard kern/tty_ttydisc.c standard kern/uipc_accf.c standard kern/uipc_debug.c optional ddb kern/uipc_domain.c standard kern/uipc_mbuf.c standard kern/uipc_mbuf2.c standard kern/uipc_mbufhash.c standard kern/uipc_mqueue.c optional p1003_1b_mqueue kern/uipc_sem.c optional p1003_1b_semaphores kern/uipc_shm.c standard kern/uipc_sockbuf.c standard kern/uipc_socket.c standard kern/uipc_syscalls.c standard kern/uipc_usrreq.c standard kern/vfs_acl.c standard kern/vfs_aio.c standard kern/vfs_bio.c standard kern/vfs_cache.c standard kern/vfs_cluster.c standard kern/vfs_default.c standard kern/vfs_export.c standard kern/vfs_extattr.c standard kern/vfs_hash.c standard kern/vfs_init.c standard kern/vfs_lookup.c standard kern/vfs_mount.c standard kern/vfs_mountroot.c standard kern/vfs_subr.c standard kern/vfs_syscalls.c standard kern/vfs_vnops.c standard # # Kernel GSS-API # gssd.h optional kgssapi \ dependency "$S/kgssapi/gssd.x" \ compile-with "RPCGEN_CPP='${CPP}' rpcgen -hM $S/kgssapi/gssd.x | grep -v pthread.h > gssd.h" \ no-obj no-implicit-rule before-depend local \ clean "gssd.h" gssd_xdr.c optional kgssapi \ dependency "$S/kgssapi/gssd.x gssd.h" \ compile-with "RPCGEN_CPP='${CPP}' rpcgen -c $S/kgssapi/gssd.x -o gssd_xdr.c" \ no-implicit-rule before-depend local \ clean "gssd_xdr.c" gssd_clnt.c optional kgssapi \ dependency "$S/kgssapi/gssd.x gssd.h" \ compile-with "RPCGEN_CPP='${CPP}' rpcgen -lM $S/kgssapi/gssd.x | grep -v string.h > gssd_clnt.c" \ no-implicit-rule before-depend local \ clean "gssd_clnt.c" kgssapi/gss_accept_sec_context.c optional kgssapi kgssapi/gss_add_oid_set_member.c optional kgssapi kgssapi/gss_acquire_cred.c optional kgssapi kgssapi/gss_canonicalize_name.c optional kgssapi kgssapi/gss_create_empty_oid_set.c optional kgssapi kgssapi/gss_delete_sec_context.c optional kgssapi kgssapi/gss_display_status.c optional kgssapi kgssapi/gss_export_name.c optional kgssapi kgssapi/gss_get_mic.c optional kgssapi kgssapi/gss_init_sec_context.c optional kgssapi kgssapi/gss_impl.c optional kgssapi kgssapi/gss_import_name.c optional kgssapi kgssapi/gss_names.c optional kgssapi kgssapi/gss_pname_to_uid.c optional kgssapi kgssapi/gss_release_buffer.c optional kgssapi kgssapi/gss_release_cred.c optional kgssapi kgssapi/gss_release_name.c optional kgssapi kgssapi/gss_release_oid_set.c optional kgssapi kgssapi/gss_set_cred_option.c optional kgssapi kgssapi/gss_test_oid_set_member.c optional kgssapi kgssapi/gss_unwrap.c optional kgssapi kgssapi/gss_verify_mic.c optional kgssapi kgssapi/gss_wrap.c optional kgssapi kgssapi/gss_wrap_size_limit.c optional kgssapi kgssapi/gssd_prot.c optional kgssapi kgssapi/krb5/krb5_mech.c optional kgssapi kgssapi/krb5/kcrypto.c optional kgssapi kgssapi/krb5/kcrypto_aes.c optional kgssapi kgssapi/krb5/kcrypto_arcfour.c optional kgssapi kgssapi/krb5/kcrypto_des.c optional kgssapi kgssapi/krb5/kcrypto_des3.c optional kgssapi kgssapi/kgss_if.m optional kgssapi kgssapi/gsstest.c optional kgssapi_debug # These files in libkern/ are those needed by all architectures. Some # of the files in libkern/ are only needed on some architectures, e.g., # libkern/divdi3.c is needed by i386 but not alpha. Also, some of these # routines may be optimized for a particular platform. In either case, # the file should be moved to conf/files. from here. # libkern/arc4random.c standard libkern/asprintf.c standard libkern/bcd.c standard libkern/bsearch.c standard libkern/crc32.c standard libkern/explicit_bzero.c standard libkern/fnmatch.c standard libkern/iconv.c optional libiconv libkern/iconv_converter_if.m optional libiconv libkern/iconv_ucs.c optional libiconv libkern/iconv_xlat.c optional libiconv libkern/iconv_xlat16.c optional libiconv libkern/inet_aton.c standard libkern/inet_ntoa.c standard libkern/inet_ntop.c standard libkern/inet_pton.c standard libkern/jenkins_hash.c standard libkern/murmur3_32.c standard libkern/mcount.c optional profiling-routine libkern/memcchr.c standard libkern/memchr.c standard libkern/memcmp.c standard libkern/memmem.c optional gdb libkern/qsort.c standard libkern/qsort_r.c standard libkern/random.c standard libkern/scanc.c standard libkern/strcasecmp.c standard libkern/strcat.c standard libkern/strchr.c standard libkern/strcmp.c standard libkern/strcpy.c standard libkern/strcspn.c standard libkern/strdup.c standard libkern/strndup.c standard libkern/strlcat.c standard libkern/strlcpy.c standard libkern/strlen.c standard libkern/strncat.c standard libkern/strncmp.c standard libkern/strncpy.c standard libkern/strnlen.c standard libkern/strrchr.c standard libkern/strsep.c standard libkern/strspn.c standard libkern/strstr.c standard libkern/strtol.c standard libkern/strtoq.c standard libkern/strtoul.c standard libkern/strtouq.c standard libkern/strvalid.c standard libkern/timingsafe_bcmp.c standard libkern/zlib.c optional crypto | geom_uzip | ipsec | \ mxge | netgraph_deflate | \ ddb_ctf | gzio net/altq/altq_cbq.c optional altq net/altq/altq_cdnr.c optional altq net/altq/altq_codel.c optional altq net/altq/altq_hfsc.c optional altq net/altq/altq_fairq.c optional altq net/altq/altq_priq.c optional altq net/altq/altq_red.c optional altq net/altq/altq_rio.c optional altq net/altq/altq_rmclass.c optional altq net/altq/altq_subr.c optional altq net/bpf.c standard net/bpf_buffer.c optional bpf net/bpf_jitter.c optional bpf_jitter net/bpf_filter.c optional bpf | netgraph_bpf net/bpf_zerocopy.c optional bpf net/bridgestp.c optional bridge | if_bridge net/flowtable.c optional flowtable inet | flowtable inet6 net/ieee8023ad_lacp.c optional lagg net/if.c standard net/if_arcsubr.c optional arcnet net/if_atmsubr.c optional atm net/if_bridge.c optional bridge inet | if_bridge inet net/if_clone.c standard net/if_dead.c standard net/if_debug.c optional ddb net/if_disc.c optional disc net/if_edsc.c optional edsc net/if_enc.c optional enc inet | enc inet6 net/if_epair.c optional epair net/if_ethersubr.c optional ether net/if_fddisubr.c optional fddi net/if_fwsubr.c optional fwip net/if_gif.c optional gif inet | gif inet6 | \ netgraph_gif inet | netgraph_gif inet6 net/if_gre.c optional gre inet | gre inet6 net/if_iso88025subr.c optional token net/if_lagg.c optional lagg net/if_loop.c optional loop net/if_llatbl.c standard net/if_me.c optional me inet net/if_media.c standard net/if_mib.c standard net/if_spppfr.c optional sppp | netgraph_sppp net/if_spppsubr.c optional sppp | netgraph_sppp net/if_stf.c optional stf inet inet6 net/if_tun.c optional tun net/if_tap.c optional tap net/if_vlan.c optional vlan net/if_vxlan.c optional vxlan inet | vxlan inet6 net/ifdi_if.m optional ether pci net/iflib.c optional ether pci net/mp_ring.c optional ether net/mppcc.c optional netgraph_mppc_compression net/mppcd.c optional netgraph_mppc_compression net/netisr.c standard net/pfil.c optional ether | inet net/radix.c standard net/radix_mpath.c standard net/raw_cb.c standard net/raw_usrreq.c standard net/route.c standard net/rss_config.c optional inet rss | inet6 rss net/rtsock.c standard net/slcompress.c optional netgraph_vjc | sppp | \ netgraph_sppp net/toeplitz.c optional inet rss | inet6 rss net/vnet.c optional vimage net80211/ieee80211.c optional wlan net80211/ieee80211_acl.c optional wlan wlan_acl net80211/ieee80211_action.c optional wlan net80211/ieee80211_ageq.c optional wlan net80211/ieee80211_adhoc.c optional wlan \ compile-with "${NORMAL_C} -Wno-unused-function" net80211/ieee80211_ageq.c optional wlan net80211/ieee80211_amrr.c optional wlan | wlan_amrr net80211/ieee80211_crypto.c optional wlan \ compile-with "${NORMAL_C} -Wno-unused-function" net80211/ieee80211_crypto_ccmp.c optional wlan wlan_ccmp net80211/ieee80211_crypto_none.c optional wlan net80211/ieee80211_crypto_tkip.c optional wlan wlan_tkip net80211/ieee80211_crypto_wep.c optional wlan wlan_wep net80211/ieee80211_ddb.c optional wlan ddb net80211/ieee80211_dfs.c optional wlan net80211/ieee80211_freebsd.c optional wlan net80211/ieee80211_hostap.c optional wlan \ compile-with "${NORMAL_C} -Wno-unused-function" net80211/ieee80211_ht.c optional wlan net80211/ieee80211_hwmp.c optional wlan ieee80211_support_mesh net80211/ieee80211_input.c optional wlan net80211/ieee80211_ioctl.c optional wlan net80211/ieee80211_mesh.c optional wlan ieee80211_support_mesh \ compile-with "${NORMAL_C} -Wno-unused-function" net80211/ieee80211_monitor.c optional wlan net80211/ieee80211_node.c optional wlan net80211/ieee80211_output.c optional wlan net80211/ieee80211_phy.c optional wlan net80211/ieee80211_power.c optional wlan net80211/ieee80211_proto.c optional wlan net80211/ieee80211_radiotap.c optional wlan net80211/ieee80211_ratectl.c optional wlan net80211/ieee80211_ratectl_none.c optional wlan net80211/ieee80211_regdomain.c optional wlan net80211/ieee80211_rssadapt.c optional wlan wlan_rssadapt net80211/ieee80211_scan.c optional wlan net80211/ieee80211_scan_sta.c optional wlan net80211/ieee80211_sta.c optional wlan \ compile-with "${NORMAL_C} -Wno-unused-function" net80211/ieee80211_superg.c optional wlan ieee80211_support_superg net80211/ieee80211_scan_sw.c optional wlan net80211/ieee80211_tdma.c optional wlan ieee80211_support_tdma net80211/ieee80211_wds.c optional wlan net80211/ieee80211_xauth.c optional wlan wlan_xauth net80211/ieee80211_alq.c optional wlan ieee80211_alq netgraph/atm/ccatm/ng_ccatm.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" netgraph/atm/ng_atm.c optional ngatm_atm netgraph/atm/ngatmbase.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" netgraph/atm/sscfu/ng_sscfu.c optional ngatm_sscfu \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" netgraph/atm/sscop/ng_sscop.c optional ngatm_sscop \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" netgraph/atm/uni/ng_uni.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" netgraph/bluetooth/common/ng_bluetooth.c optional netgraph_bluetooth netgraph/bluetooth/drivers/bt3c/ng_bt3c_pccard.c optional netgraph_bluetooth_bt3c netgraph/bluetooth/drivers/h4/ng_h4.c optional netgraph_bluetooth_h4 netgraph/bluetooth/drivers/ubt/ng_ubt.c optional netgraph_bluetooth_ubt usb netgraph/bluetooth/drivers/ubtbcmfw/ubtbcmfw.c optional netgraph_bluetooth_ubtbcmfw usb netgraph/bluetooth/hci/ng_hci_cmds.c optional netgraph_bluetooth_hci netgraph/bluetooth/hci/ng_hci_evnt.c optional netgraph_bluetooth_hci netgraph/bluetooth/hci/ng_hci_main.c optional netgraph_bluetooth_hci netgraph/bluetooth/hci/ng_hci_misc.c optional netgraph_bluetooth_hci netgraph/bluetooth/hci/ng_hci_ulpi.c optional netgraph_bluetooth_hci netgraph/bluetooth/l2cap/ng_l2cap_cmds.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/l2cap/ng_l2cap_evnt.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/l2cap/ng_l2cap_llpi.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/l2cap/ng_l2cap_main.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/l2cap/ng_l2cap_misc.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/l2cap/ng_l2cap_ulpi.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/socket/ng_btsocket.c optional netgraph_bluetooth_socket netgraph/bluetooth/socket/ng_btsocket_hci_raw.c optional netgraph_bluetooth_socket netgraph/bluetooth/socket/ng_btsocket_l2cap.c optional netgraph_bluetooth_socket netgraph/bluetooth/socket/ng_btsocket_l2cap_raw.c optional netgraph_bluetooth_socket netgraph/bluetooth/socket/ng_btsocket_rfcomm.c optional netgraph_bluetooth_socket netgraph/bluetooth/socket/ng_btsocket_sco.c optional netgraph_bluetooth_socket netgraph/netflow/netflow.c optional netgraph_netflow netgraph/netflow/netflow_v9.c optional netgraph_netflow netgraph/netflow/ng_netflow.c optional netgraph_netflow netgraph/ng_UI.c optional netgraph_UI netgraph/ng_async.c optional netgraph_async netgraph/ng_atmllc.c optional netgraph_atmllc netgraph/ng_base.c optional netgraph netgraph/ng_bpf.c optional netgraph_bpf netgraph/ng_bridge.c optional netgraph_bridge netgraph/ng_car.c optional netgraph_car netgraph/ng_cisco.c optional netgraph_cisco netgraph/ng_deflate.c optional netgraph_deflate netgraph/ng_device.c optional netgraph_device netgraph/ng_echo.c optional netgraph_echo netgraph/ng_eiface.c optional netgraph_eiface netgraph/ng_ether.c optional netgraph_ether netgraph/ng_ether_echo.c optional netgraph_ether_echo netgraph/ng_frame_relay.c optional netgraph_frame_relay netgraph/ng_gif.c optional netgraph_gif inet6 | netgraph_gif inet netgraph/ng_gif_demux.c optional netgraph_gif_demux netgraph/ng_hole.c optional netgraph_hole netgraph/ng_iface.c optional netgraph_iface netgraph/ng_ip_input.c optional netgraph_ip_input netgraph/ng_ipfw.c optional netgraph_ipfw inet ipfirewall netgraph/ng_ksocket.c optional netgraph_ksocket netgraph/ng_l2tp.c optional netgraph_l2tp netgraph/ng_lmi.c optional netgraph_lmi netgraph/ng_mppc.c optional netgraph_mppc_compression | \ netgraph_mppc_encryption netgraph/ng_nat.c optional netgraph_nat inet libalias netgraph/ng_one2many.c optional netgraph_one2many netgraph/ng_parse.c optional netgraph netgraph/ng_patch.c optional netgraph_patch netgraph/ng_pipe.c optional netgraph_pipe netgraph/ng_ppp.c optional netgraph_ppp netgraph/ng_pppoe.c optional netgraph_pppoe netgraph/ng_pptpgre.c optional netgraph_pptpgre netgraph/ng_pred1.c optional netgraph_pred1 netgraph/ng_rfc1490.c optional netgraph_rfc1490 netgraph/ng_socket.c optional netgraph_socket netgraph/ng_split.c optional netgraph_split netgraph/ng_sppp.c optional netgraph_sppp netgraph/ng_tag.c optional netgraph_tag netgraph/ng_tcpmss.c optional netgraph_tcpmss netgraph/ng_tee.c optional netgraph_tee netgraph/ng_tty.c optional netgraph_tty netgraph/ng_vjc.c optional netgraph_vjc netgraph/ng_vlan.c optional netgraph_vlan netinet/accf_data.c optional accept_filter_data inet netinet/accf_dns.c optional accept_filter_dns inet netinet/accf_http.c optional accept_filter_http inet netinet/if_atm.c optional atm netinet/if_ether.c optional inet ether netinet/igmp.c optional inet netinet/in.c optional inet netinet/in_debug.c optional inet ddb netinet/in_kdtrace.c optional inet | inet6 netinet/ip_carp.c optional inet carp | inet6 carp netinet/in_fib.c optional inet netinet/in_gif.c optional gif inet | netgraph_gif inet netinet/ip_gre.c optional gre inet netinet/ip_id.c optional inet netinet/in_jail.c optional inet netinet/in_mcast.c optional inet netinet/in_pcb.c optional inet | inet6 netinet/in_pcbgroup.c optional inet pcbgroup | inet6 pcbgroup netinet/in_prot.c optional inet | inet6 netinet/in_proto.c optional inet | inet6 netinet/in_rmx.c optional inet netinet/in_rss.c optional inet rss netinet/ip_divert.c optional inet ipdivert ipfirewall netinet/ip_ecn.c optional inet | inet6 netinet/ip_encap.c optional inet | inet6 netinet/ip_fastfwd.c optional inet netinet/ip_icmp.c optional inet | inet6 netinet/ip_input.c optional inet netinet/ip_ipsec.c optional inet ipsec netinet/ip_mroute.c optional mrouting inet netinet/ip_options.c optional inet netinet/ip_output.c optional inet netinet/ip_reass.c optional inet netinet/raw_ip.c optional inet | inet6 netinet/cc/cc.c optional inet | inet6 netinet/cc/cc_newreno.c optional inet | inet6 netinet/sctp_asconf.c optional inet sctp | inet6 sctp netinet/sctp_auth.c optional inet sctp | inet6 sctp netinet/sctp_bsd_addr.c optional inet sctp | inet6 sctp netinet/sctp_cc_functions.c optional inet sctp | inet6 sctp netinet/sctp_crc32.c optional inet sctp | inet6 sctp netinet/sctp_indata.c optional inet sctp | inet6 sctp netinet/sctp_input.c optional inet sctp | inet6 sctp netinet/sctp_output.c optional inet sctp | inet6 sctp netinet/sctp_pcb.c optional inet sctp | inet6 sctp netinet/sctp_peeloff.c optional inet sctp | inet6 sctp netinet/sctp_ss_functions.c optional inet sctp | inet6 sctp netinet/sctp_syscalls.c optional inet sctp | inet6 sctp netinet/sctp_sysctl.c optional inet sctp | inet6 sctp netinet/sctp_timer.c optional inet sctp | inet6 sctp netinet/sctp_usrreq.c optional inet sctp | inet6 sctp netinet/sctputil.c optional inet sctp | inet6 sctp netinet/siftr.c optional inet siftr alq | inet6 siftr alq netinet/tcp_debug.c optional tcpdebug netinet/tcp_fastopen.c optional inet tcp_rfc7413 | inet6 tcp_rfc7413 netinet/tcp_hostcache.c optional inet | inet6 netinet/tcp_input.c optional inet | inet6 netinet/tcp_lro.c optional inet | inet6 netinet/tcp_output.c optional inet | inet6 netinet/tcp_offload.c optional tcp_offload inet | tcp_offload inet6 netinet/tcp_pcap.c optional inet tcppcap | inet6 tcppcap netinet/tcp_reass.c optional inet | inet6 netinet/tcp_sack.c optional inet | inet6 netinet/tcp_subr.c optional inet | inet6 netinet/tcp_syncache.c optional inet | inet6 netinet/tcp_timer.c optional inet | inet6 netinet/tcp_timewait.c optional inet | inet6 netinet/tcp_usrreq.c optional inet | inet6 netinet/udp_usrreq.c optional inet | inet6 netinet/libalias/alias.c optional libalias inet | netgraph_nat inet netinet/libalias/alias_db.c optional libalias inet | netgraph_nat inet netinet/libalias/alias_mod.c optional libalias | netgraph_nat netinet/libalias/alias_proxy.c optional libalias inet | netgraph_nat inet netinet/libalias/alias_util.c optional libalias inet | netgraph_nat inet netinet/libalias/alias_sctp.c optional libalias inet | netgraph_nat inet netinet6/dest6.c optional inet6 netinet6/frag6.c optional inet6 netinet6/icmp6.c optional inet6 netinet6/in6.c optional inet6 netinet6/in6_cksum.c optional inet6 netinet6/in6_fib.c optional inet6 netinet6/in6_gif.c optional gif inet6 | netgraph_gif inet6 netinet6/in6_ifattach.c optional inet6 netinet6/in6_jail.c optional inet6 netinet6/in6_mcast.c optional inet6 netinet6/in6_pcb.c optional inet6 netinet6/in6_pcbgroup.c optional inet6 pcbgroup netinet6/in6_proto.c optional inet6 netinet6/in6_rmx.c optional inet6 netinet6/in6_rss.c optional inet6 rss netinet6/in6_src.c optional inet6 netinet6/ip6_forward.c optional inet6 netinet6/ip6_gre.c optional gre inet6 netinet6/ip6_id.c optional inet6 netinet6/ip6_input.c optional inet6 netinet6/ip6_mroute.c optional mrouting inet6 netinet6/ip6_output.c optional inet6 netinet6/ip6_ipsec.c optional inet6 ipsec netinet6/mld6.c optional inet6 netinet6/nd6.c optional inet6 netinet6/nd6_nbr.c optional inet6 netinet6/nd6_rtr.c optional inet6 netinet6/raw_ip6.c optional inet6 netinet6/route6.c optional inet6 netinet6/scope6.c optional inet6 netinet6/sctp6_usrreq.c optional inet6 sctp netinet6/udp6_usrreq.c optional inet6 netipsec/ipsec.c optional ipsec inet | ipsec inet6 netipsec/ipsec_input.c optional ipsec inet | ipsec inet6 netipsec/ipsec_mbuf.c optional ipsec inet | ipsec inet6 netipsec/ipsec_output.c optional ipsec inet | ipsec inet6 netipsec/key.c optional ipsec inet | ipsec inet6 netipsec/key_debug.c optional ipsec inet | ipsec inet6 netipsec/keysock.c optional ipsec inet | ipsec inet6 netipsec/xform_ah.c optional ipsec inet | ipsec inet6 netipsec/xform_esp.c optional ipsec inet | ipsec inet6 netipsec/xform_ipcomp.c optional ipsec inet | ipsec inet6 netipsec/xform_tcp.c optional ipsec inet tcp_signature | \ ipsec inet6 tcp_signature netnatm/natm.c optional natm netnatm/natm_pcb.c optional natm netnatm/natm_proto.c optional natm netpfil/ipfw/dn_aqm_codel.c optional inet dummynet netpfil/ipfw/dn_aqm_pie.c optional inet dummynet netpfil/ipfw/dn_heap.c optional inet dummynet netpfil/ipfw/dn_sched_fifo.c optional inet dummynet netpfil/ipfw/dn_sched_fq_codel.c optional inet dummynet netpfil/ipfw/dn_sched_fq_pie.c optional inet dummynet netpfil/ipfw/dn_sched_prio.c optional inet dummynet netpfil/ipfw/dn_sched_qfq.c optional inet dummynet netpfil/ipfw/dn_sched_rr.c optional inet dummynet netpfil/ipfw/dn_sched_wf2q.c optional inet dummynet netpfil/ipfw/ip_dummynet.c optional inet dummynet netpfil/ipfw/ip_dn_io.c optional inet dummynet netpfil/ipfw/ip_dn_glue.c optional inet dummynet netpfil/ipfw/ip_fw2.c optional inet ipfirewall netpfil/ipfw/ip_fw_bpf.c optional inet ipfirewall netpfil/ipfw/ip_fw_dynamic.c optional inet ipfirewall netpfil/ipfw/ip_fw_eaction.c optional inet ipfirewall netpfil/ipfw/ip_fw_log.c optional inet ipfirewall netpfil/ipfw/ip_fw_pfil.c optional inet ipfirewall netpfil/ipfw/ip_fw_sockopt.c optional inet ipfirewall netpfil/ipfw/ip_fw_table.c optional inet ipfirewall netpfil/ipfw/ip_fw_table_algo.c optional inet ipfirewall netpfil/ipfw/ip_fw_table_value.c optional inet ipfirewall netpfil/ipfw/ip_fw_iface.c optional inet ipfirewall netpfil/ipfw/ip_fw_nat.c optional inet ipfirewall_nat netpfil/ipfw/nat64/ip_fw_nat64.c optional inet inet6 ipfirewall \ ipfirewall_nat64 netpfil/ipfw/nat64/nat64lsn.c optional inet inet6 ipfirewall \ ipfirewall_nat64 netpfil/ipfw/nat64/nat64lsn_control.c optional inet inet6 ipfirewall \ ipfirewall_nat64 netpfil/ipfw/nat64/nat64stl.c optional inet inet6 ipfirewall \ ipfirewall_nat64 netpfil/ipfw/nat64/nat64stl_control.c optional inet inet6 ipfirewall \ ipfirewall_nat64 netpfil/ipfw/nat64/nat64_translate.c optional inet inet6 ipfirewall \ ipfirewall_nat64 netpfil/ipfw/nptv6/ip_fw_nptv6.c optional inet inet6 ipfirewall \ ipfirewall_nptv6 netpfil/ipfw/nptv6/nptv6.c optional inet inet6 ipfirewall \ ipfirewall_nptv6 netpfil/pf/if_pflog.c optional pflog pf inet netpfil/pf/if_pfsync.c optional pfsync pf inet netpfil/pf/pf.c optional pf inet netpfil/pf/pf_if.c optional pf inet netpfil/pf/pf_ioctl.c optional pf inet netpfil/pf/pf_lb.c optional pf inet netpfil/pf/pf_norm.c optional pf inet netpfil/pf/pf_osfp.c optional pf inet netpfil/pf/pf_ruleset.c optional pf inet netpfil/pf/pf_table.c optional pf inet netpfil/pf/in4_cksum.c optional pf inet netsmb/smb_conn.c optional netsmb netsmb/smb_crypt.c optional netsmb netsmb/smb_dev.c optional netsmb netsmb/smb_iod.c optional netsmb netsmb/smb_rq.c optional netsmb netsmb/smb_smb.c optional netsmb netsmb/smb_subr.c optional netsmb netsmb/smb_trantcp.c optional netsmb netsmb/smb_usr.c optional netsmb nfs/bootp_subr.c optional bootp nfscl nfs/krpc_subr.c optional bootp nfscl nfs/nfs_diskless.c optional nfscl nfs_root nfs/nfs_fha.c optional nfsd nfs/nfs_lock.c optional nfscl | nfslockd | nfsd nfs/nfs_nfssvc.c optional nfscl | nfsd nlm/nlm_advlock.c optional nfslockd | nfsd nlm/nlm_prot_clnt.c optional nfslockd | nfsd nlm/nlm_prot_impl.c optional nfslockd | nfsd nlm/nlm_prot_server.c optional nfslockd | nfsd nlm/nlm_prot_svc.c optional nfslockd | nfsd nlm/nlm_prot_xdr.c optional nfslockd | nfsd nlm/sm_inter_xdr.c optional nfslockd | nfsd # Linux Kernel Programming Interface compat/linuxkpi/common/src/linux_kmod.c optional compat_linuxkpi \ compile-with "${LINUXKPI_C}" compat/linuxkpi/common/src/linux_compat.c optional compat_linuxkpi \ compile-with "${LINUXKPI_C}" compat/linuxkpi/common/src/linux_pci.c optional compat_linuxkpi pci \ compile-with "${LINUXKPI_C}" compat/linuxkpi/common/src/linux_idr.c optional compat_linuxkpi \ compile-with "${LINUXKPI_C}" compat/linuxkpi/common/src/linux_radix.c optional compat_linuxkpi \ compile-with "${LINUXKPI_C}" compat/linuxkpi/common/src/linux_usb.c optional compat_linuxkpi usb \ compile-with "${LINUXKPI_C}" # OpenFabrics Enterprise Distribution (Infiniband) ofed/drivers/infiniband/core/addr.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/agent.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/cache.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" # XXX Mad.c must be ordered before cm.c for sysinit sets to occur in # the correct order. ofed/drivers/infiniband/core/mad.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/cm.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/ -Wno-unused-function" ofed/drivers/infiniband/core/cma.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/device.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/fmr_pool.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/iwcm.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/mad_rmpp.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/multicast.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/packer.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/peer_mem.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/sa_query.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/smi.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/sysfs.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/ucm.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/ucma.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/ud_header.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/umem.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/user_mad.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/uverbs_cmd.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/uverbs_main.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/uverbs_marshall.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/verbs.c optional ofed \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/ulp/ipoib/ipoib_cm.c optional ipoib \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/" #ofed/drivers/infiniband/ulp/ipoib/ipoib_fs.c optional ipoib \ # compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/" ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c optional ipoib \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/" ofed/drivers/infiniband/ulp/ipoib/ipoib_main.c optional ipoib \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/" ofed/drivers/infiniband/ulp/ipoib/ipoib_multicast.c optional ipoib \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/" ofed/drivers/infiniband/ulp/ipoib/ipoib_verbs.c optional ipoib \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/" #ofed/drivers/infiniband/ulp/ipoib/ipoib_vlan.c optional ipoib \ # compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/" ofed/drivers/infiniband/ulp/sdp/sdp_bcopy.c optional sdp inet \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/" ofed/drivers/infiniband/ulp/sdp/sdp_main.c optional sdp inet \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/" ofed/drivers/infiniband/ulp/sdp/sdp_rx.c optional sdp inet \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/" ofed/drivers/infiniband/ulp/sdp/sdp_cma.c optional sdp inet \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/" ofed/drivers/infiniband/ulp/sdp/sdp_tx.c optional sdp inet \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/" ofed/drivers/infiniband/hw/mlx4/alias_GUID.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/mcg.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/sysfs.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/cm.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/ah.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/cq.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/doorbell.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/mad.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/main.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/mlx4_exp.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/mr.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/qp.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/srq.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/wc.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/net/mlx4/alloc.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/catas.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/cmd.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/cq.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/eq.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/fw.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/icm.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/intf.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/main.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/mcg.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/ -Wno-unused" ofed/drivers/net/mlx4/mr.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/pd.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/port.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/profile.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/qp.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/reset.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/sense.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/srq.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/resource_tracker.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/sys_tune.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/en_cq.c optional mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/en_main.c optional mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/en_netdev.c optional mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/en_port.c optional mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/en_resources.c optional mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/en_rx.c optional mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/en_tx.c optional mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" dev/mlx5/mlx5_core/mlx5_alloc.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_cmd.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_cq.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_eq.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_flow_table.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_fw.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_health.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_mad.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_main.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_mcg.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_mr.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_pagealloc.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_pd.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_port.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_qp.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_srq.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_transobj.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_uar.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_vport.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_wq.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_en/mlx5_en_ethtool.c optional mlx5en pci inet inet6 \ compile-with "${OFED_C}" dev/mlx5/mlx5_en/mlx5_en_main.c optional mlx5en pci inet inet6 \ compile-with "${OFED_C}" dev/mlx5/mlx5_en/mlx5_en_tx.c optional mlx5en pci inet inet6 \ compile-with "${OFED_C}" dev/mlx5/mlx5_en/mlx5_en_flow_table.c optional mlx5en pci inet inet6 \ compile-with "${OFED_C}" dev/mlx5/mlx5_en/mlx5_en_rx.c optional mlx5en pci inet inet6 \ compile-with "${OFED_C}" dev/mlx5/mlx5_en/mlx5_en_txrx.c optional mlx5en pci inet inet6 \ compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_allocator.c optional mthca \ compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_av.c optional mthca \ compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_catas.c optional mthca \ compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_cmd.c optional mthca \ compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_cq.c optional mthca \ compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_eq.c optional mthca \ compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_mad.c optional mthca \ compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_main.c optional mthca \ compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_mcg.c optional mthca \ compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_memfree.c optional mthca \ compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_mr.c optional mthca \ compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_pd.c optional mthca \ compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_profile.c optional mthca \ compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_provider.c optional mthca \ compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_qp.c optional mthca \ compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_reset.c optional mthca \ compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_srq.c optional mthca \ compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_uar.c optional mthca \ compile-with "${OFED_C}" # crypto support opencrypto/cast.c optional crypto | ipsec opencrypto/criov.c optional crypto | ipsec opencrypto/crypto.c optional crypto | ipsec opencrypto/cryptodev.c optional cryptodev opencrypto/cryptodev_if.m optional crypto | ipsec opencrypto/cryptosoft.c optional crypto | ipsec opencrypto/cryptodeflate.c optional crypto | ipsec opencrypto/gmac.c optional crypto | ipsec opencrypto/gfmult.c optional crypto | ipsec opencrypto/rmd160.c optional crypto | ipsec opencrypto/skipjack.c optional crypto | ipsec opencrypto/xform.c optional crypto | ipsec rpc/auth_none.c optional krpc | nfslockd | nfscl | nfsd rpc/auth_unix.c optional krpc | nfslockd | nfscl | nfsd rpc/authunix_prot.c optional krpc | nfslockd | nfscl | nfsd rpc/clnt_bck.c optional krpc | nfslockd | nfscl | nfsd rpc/clnt_dg.c optional krpc | nfslockd | nfscl | nfsd rpc/clnt_rc.c optional krpc | nfslockd | nfscl | nfsd rpc/clnt_vc.c optional krpc | nfslockd | nfscl | nfsd rpc/getnetconfig.c optional krpc | nfslockd | nfscl | nfsd rpc/replay.c optional krpc | nfslockd | nfscl | nfsd rpc/rpc_callmsg.c optional krpc | nfslockd | nfscl | nfsd rpc/rpc_generic.c optional krpc | nfslockd | nfscl | nfsd rpc/rpc_prot.c optional krpc | nfslockd | nfscl | nfsd rpc/rpcb_clnt.c optional krpc | nfslockd | nfscl | nfsd rpc/rpcb_prot.c optional krpc | nfslockd | nfscl | nfsd rpc/svc.c optional krpc | nfslockd | nfscl | nfsd rpc/svc_auth.c optional krpc | nfslockd | nfscl | nfsd rpc/svc_auth_unix.c optional krpc | nfslockd | nfscl | nfsd rpc/svc_dg.c optional krpc | nfslockd | nfscl | nfsd rpc/svc_generic.c optional krpc | nfslockd | nfscl | nfsd rpc/svc_vc.c optional krpc | nfslockd | nfscl | nfsd rpc/rpcsec_gss/rpcsec_gss.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi rpc/rpcsec_gss/rpcsec_gss_conf.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi rpc/rpcsec_gss/rpcsec_gss_misc.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi rpc/rpcsec_gss/rpcsec_gss_prot.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi rpc/rpcsec_gss/svc_rpcsec_gss.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi security/audit/audit.c optional audit security/audit/audit_arg.c optional audit security/audit/audit_bsm.c optional audit security/audit/audit_bsm_klib.c optional audit security/audit/audit_pipe.c optional audit security/audit/audit_syscalls.c standard security/audit/audit_trigger.c optional audit security/audit/audit_worker.c optional audit security/audit/bsm_domain.c optional audit security/audit/bsm_errno.c optional audit security/audit/bsm_fcntl.c optional audit security/audit/bsm_socket_type.c optional audit security/audit/bsm_token.c optional audit security/mac/mac_audit.c optional mac audit security/mac/mac_cred.c optional mac security/mac/mac_framework.c optional mac security/mac/mac_inet.c optional mac inet | mac inet6 security/mac/mac_inet6.c optional mac inet6 security/mac/mac_label.c optional mac security/mac/mac_net.c optional mac security/mac/mac_pipe.c optional mac security/mac/mac_posix_sem.c optional mac security/mac/mac_posix_shm.c optional mac security/mac/mac_priv.c optional mac security/mac/mac_process.c optional mac security/mac/mac_socket.c optional mac security/mac/mac_syscalls.c standard security/mac/mac_system.c optional mac security/mac/mac_sysv_msg.c optional mac security/mac/mac_sysv_sem.c optional mac security/mac/mac_sysv_shm.c optional mac security/mac/mac_vfs.c optional mac security/mac_biba/mac_biba.c optional mac_biba security/mac_bsdextended/mac_bsdextended.c optional mac_bsdextended security/mac_bsdextended/ugidfw_system.c optional mac_bsdextended security/mac_bsdextended/ugidfw_vnode.c optional mac_bsdextended security/mac_ifoff/mac_ifoff.c optional mac_ifoff security/mac_lomac/mac_lomac.c optional mac_lomac security/mac_mls/mac_mls.c optional mac_mls security/mac_none/mac_none.c optional mac_none security/mac_partition/mac_partition.c optional mac_partition security/mac_portacl/mac_portacl.c optional mac_portacl security/mac_seeotheruids/mac_seeotheruids.c optional mac_seeotheruids security/mac_stub/mac_stub.c optional mac_stub security/mac_test/mac_test.c optional mac_test teken/teken.c optional sc | vt ufs/ffs/ffs_alloc.c optional ffs ufs/ffs/ffs_balloc.c optional ffs ufs/ffs/ffs_inode.c optional ffs ufs/ffs/ffs_snapshot.c optional ffs ufs/ffs/ffs_softdep.c optional ffs ufs/ffs/ffs_subr.c optional ffs ufs/ffs/ffs_tables.c optional ffs ufs/ffs/ffs_vfsops.c optional ffs ufs/ffs/ffs_vnops.c optional ffs ufs/ffs/ffs_rawread.c optional ffs directio ufs/ffs/ffs_suspend.c optional ffs ufs/ufs/ufs_acl.c optional ffs ufs/ufs/ufs_bmap.c optional ffs ufs/ufs/ufs_dirhash.c optional ffs ufs/ufs/ufs_extattr.c optional ffs ufs/ufs/ufs_gjournal.c optional ffs UFS_GJOURNAL ufs/ufs/ufs_inode.c optional ffs ufs/ufs/ufs_lookup.c optional ffs ufs/ufs/ufs_quota.c optional ffs ufs/ufs/ufs_vfsops.c optional ffs ufs/ufs/ufs_vnops.c optional ffs vm/default_pager.c standard vm/device_pager.c standard vm/phys_pager.c standard vm/redzone.c optional DEBUG_REDZONE vm/sg_pager.c standard vm/swap_pager.c standard vm/uma_core.c standard vm/uma_dbg.c standard vm/memguard.c optional DEBUG_MEMGUARD vm/vm_fault.c standard vm/vm_glue.c standard vm/vm_init.c standard vm/vm_kern.c standard vm/vm_map.c standard vm/vm_meter.c standard vm/vm_mmap.c standard vm/vm_object.c standard vm/vm_page.c standard vm/vm_pageout.c standard vm/vm_pager.c standard vm/vm_phys.c standard vm/vm_radix.c standard vm/vm_reserv.c standard vm/vm_domain.c standard vm/vm_unix.c standard vm/vm_zeroidle.c standard vm/vnode_pager.c standard xen/features.c optional xenhvm xen/xenbus/xenbus_if.m optional xenhvm xen/xenbus/xenbus.c optional xenhvm xen/xenbus/xenbusb_if.m optional xenhvm xen/xenbus/xenbusb.c optional xenhvm xen/xenbus/xenbusb_front.c optional xenhvm xen/xenbus/xenbusb_back.c optional xenhvm xen/xenmem/xenmem_if.m optional xenhvm xdr/xdr.c optional krpc | nfslockd | nfscl | nfsd xdr/xdr_array.c optional krpc | nfslockd | nfscl | nfsd xdr/xdr_mbuf.c optional krpc | nfslockd | nfscl | nfsd xdr/xdr_mem.c optional krpc | nfslockd | nfscl | nfsd xdr/xdr_reference.c optional krpc | nfslockd | nfscl | nfsd xdr/xdr_sizeof.c optional krpc | nfslockd | nfscl | nfsd Index: head/sys/dev/bhnd/bcma/bcma.c =================================================================== --- head/sys/dev/bhnd/bcma/bcma.c (revision 304869) +++ head/sys/dev/bhnd/bcma/bcma.c (revision 304870) @@ -1,518 +1,595 @@ /*- * Copyright (c) 2015 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include "bcmavar.h" #include "bcma_eromreg.h" #include "bcma_eromvar.h" #include int bcma_probe(device_t dev) { device_set_desc(dev, "BCMA BHND bus"); return (BUS_PROBE_DEFAULT); } int bcma_attach(device_t dev) { struct bcma_devinfo *dinfo; device_t *devs, child; int ndevs; int error; if ((error = device_get_children(dev, &devs, &ndevs))) return (error); /* * Map our children's agent register block. */ for (int i = 0; i < ndevs; i++) { bhnd_addr_t addr; bhnd_size_t size; rman_res_t r_start, r_count, r_end; child = devs[i]; dinfo = device_get_ivars(child); KASSERT(!device_is_suspended(child), ("bcma(4) stateful suspend handling requires that devices " "not be suspended before bcma_attach()")); /* Verify that the agent register block exists and is * mappable */ if (bhnd_get_port_rid(child, BHND_PORT_AGENT, 0, 0) == -1) continue; /* Fetch the address of the agent register block */ error = bhnd_get_region_addr(child, BHND_PORT_AGENT, 0, 0, &addr, &size); if (error) { device_printf(dev, "failed fetching agent register " "block address for core %d\n", i); goto cleanup; } /* Allocate the resource */ r_start = addr; r_count = size; r_end = r_start + r_count - 1; dinfo->rid_agent = i + 1; dinfo->res_agent = BHND_BUS_ALLOC_RESOURCE(dev, dev, SYS_RES_MEMORY, &dinfo->rid_agent, r_start, r_end, r_count, RF_ACTIVE); if (dinfo->res_agent == NULL) { device_printf(dev, "failed allocating agent register " "block for core %d\n", i); error = ENXIO; goto cleanup; } } cleanup: free(devs, M_BHND); if (error) return (error); return (bhnd_generic_attach(dev)); } int bcma_detach(device_t dev) { return (bhnd_generic_detach(dev)); } static int bcma_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) { const struct bcma_devinfo *dinfo; const struct bhnd_core_info *ci; dinfo = device_get_ivars(child); ci = &dinfo->corecfg->core_info; switch (index) { case BHND_IVAR_VENDOR: *result = ci->vendor; return (0); case BHND_IVAR_DEVICE: *result = ci->device; return (0); case BHND_IVAR_HWREV: *result = ci->hwrev; return (0); case BHND_IVAR_DEVICE_CLASS: *result = bhnd_core_class(ci); return (0); case BHND_IVAR_VENDOR_NAME: *result = (uintptr_t) bhnd_vendor_name(ci->vendor); return (0); case BHND_IVAR_DEVICE_NAME: *result = (uintptr_t) bhnd_core_name(ci); return (0); case BHND_IVAR_CORE_INDEX: *result = ci->core_idx; return (0); case BHND_IVAR_CORE_UNIT: *result = ci->unit; return (0); default: return (ENOENT); } } static int bcma_write_ivar(device_t dev, device_t child, int index, uintptr_t value) { switch (index) { case BHND_IVAR_VENDOR: case BHND_IVAR_DEVICE: case BHND_IVAR_HWREV: case BHND_IVAR_DEVICE_CLASS: case BHND_IVAR_VENDOR_NAME: case BHND_IVAR_DEVICE_NAME: case BHND_IVAR_CORE_INDEX: case BHND_IVAR_CORE_UNIT: return (EINVAL); default: return (ENOENT); } } static struct resource_list * bcma_get_resource_list(device_t dev, device_t child) { struct bcma_devinfo *dinfo = device_get_ivars(child); return (&dinfo->resources); } static device_t bcma_find_hostb_device(device_t dev) { struct bcma_softc *sc = device_get_softc(dev); /* This is set (or not) by the concrete bcma driver subclass. */ return (sc->hostb_dev); } static int bcma_reset_core(device_t dev, device_t child, uint16_t flags) { struct bcma_devinfo *dinfo; if (device_get_parent(child) != dev) BHND_BUS_RESET_CORE(device_get_parent(dev), child, flags); dinfo = device_get_ivars(child); /* Can't reset the core without access to the agent registers */ if (dinfo->res_agent == NULL) return (ENODEV); /* Start reset */ bhnd_bus_write_4(dinfo->res_agent, BHND_RESET_CF, BHND_RESET_CF_ENABLE); bhnd_bus_read_4(dinfo->res_agent, BHND_RESET_CF); DELAY(10); /* Disable clock */ bhnd_bus_write_4(dinfo->res_agent, BHND_CF, flags); bhnd_bus_read_4(dinfo->res_agent, BHND_CF); DELAY(10); /* Enable clocks & force clock gating */ bhnd_bus_write_4(dinfo->res_agent, BHND_CF, BHND_CF_CLOCK_EN | BHND_CF_FGC | flags); bhnd_bus_read_4(dinfo->res_agent, BHND_CF); DELAY(10); /* Complete reset */ bhnd_bus_write_4(dinfo->res_agent, BHND_RESET_CF, 0); bhnd_bus_read_4(dinfo->res_agent, BHND_RESET_CF); DELAY(10); /* Release force clock gating */ bhnd_bus_write_4(dinfo->res_agent, BHND_CF, BHND_CF_CLOCK_EN | flags); bhnd_bus_read_4(dinfo->res_agent, BHND_CF); DELAY(10); return (0); } static int bcma_suspend_core(device_t dev, device_t child) { struct bcma_devinfo *dinfo; if (device_get_parent(child) != dev) BHND_BUS_SUSPEND_CORE(device_get_parent(dev), child); dinfo = device_get_ivars(child); /* Can't suspend the core without access to the agent registers */ if (dinfo->res_agent == NULL) return (ENODEV); // TODO - perform suspend return (ENXIO); } +static uint32_t +bcma_read_config(device_t dev, device_t child, bus_size_t offset, u_int width) +{ + struct bcma_devinfo *dinfo; + struct bhnd_resource *r; + + /* Must be a directly attached child core */ + if (device_get_parent(child) != dev) + return (UINT32_MAX); + + /* Fetch the agent registers */ + dinfo = device_get_ivars(child); + if ((r = dinfo->res_agent) == NULL) + return (UINT32_MAX); + + /* Verify bounds */ + if (offset > rman_get_size(r->res)) + return (UINT32_MAX); + + if (rman_get_size(r->res) - offset < width) + return (UINT32_MAX); + + switch (width) { + case 1: + return (bhnd_bus_read_1(r, offset)); + case 2: + return (bhnd_bus_read_2(r, offset)); + case 4: + return (bhnd_bus_read_4(r, offset)); + default: + return (UINT32_MAX); + } +} + +static void +bcma_write_config(device_t dev, device_t child, bus_size_t offset, uint32_t val, + u_int width) +{ + struct bcma_devinfo *dinfo; + struct bhnd_resource *r; + + /* Must be a directly attached child core */ + if (device_get_parent(child) != dev) + return; + + /* Fetch the agent registers */ + dinfo = device_get_ivars(child); + if ((r = dinfo->res_agent) == NULL) + return; + + /* Verify bounds */ + if (offset > rman_get_size(r->res)) + return; + + if (rman_get_size(r->res) - offset < width) + return; + + switch (width) { + case 1: + bhnd_bus_write_1(r, offset, val); + break; + case 2: + bhnd_bus_write_2(r, offset, val); + break; + case 4: + bhnd_bus_write_4(r, offset, val); + break; + default: + break; + } +} + static u_int bcma_get_port_count(device_t dev, device_t child, bhnd_port_type type) { struct bcma_devinfo *dinfo; /* delegate non-bus-attached devices to our parent */ if (device_get_parent(child) != dev) return (BHND_BUS_GET_PORT_COUNT(device_get_parent(dev), child, type)); dinfo = device_get_ivars(child); switch (type) { case BHND_PORT_DEVICE: return (dinfo->corecfg->num_dev_ports); case BHND_PORT_BRIDGE: return (dinfo->corecfg->num_bridge_ports); case BHND_PORT_AGENT: return (dinfo->corecfg->num_wrapper_ports); default: device_printf(dev, "%s: unknown type (%d)\n", __func__, type); return (0); } } static u_int bcma_get_region_count(device_t dev, device_t child, bhnd_port_type type, u_int port_num) { struct bcma_devinfo *dinfo; struct bcma_sport_list *ports; struct bcma_sport *port; /* delegate non-bus-attached devices to our parent */ if (device_get_parent(child) != dev) return (BHND_BUS_GET_REGION_COUNT(device_get_parent(dev), child, type, port_num)); dinfo = device_get_ivars(child); ports = bcma_corecfg_get_port_list(dinfo->corecfg, type); STAILQ_FOREACH(port, ports, sp_link) { if (port->sp_num == port_num) return (port->sp_num_maps); } /* not found */ return (0); } static int bcma_get_port_rid(device_t dev, device_t child, bhnd_port_type port_type, u_int port_num, u_int region_num) { struct bcma_devinfo *dinfo; struct bcma_map *map; struct bcma_sport_list *ports; struct bcma_sport *port; dinfo = device_get_ivars(child); ports = bcma_corecfg_get_port_list(dinfo->corecfg, port_type); STAILQ_FOREACH(port, ports, sp_link) { if (port->sp_num != port_num) continue; STAILQ_FOREACH(map, &port->sp_maps, m_link) if (map->m_region_num == region_num) return map->m_rid; } return -1; } static int bcma_decode_port_rid(device_t dev, device_t child, int type, int rid, bhnd_port_type *port_type, u_int *port_num, u_int *region_num) { struct bcma_devinfo *dinfo; struct bcma_map *map; struct bcma_sport_list *ports; struct bcma_sport *port; dinfo = device_get_ivars(child); /* Ports are always memory mapped */ if (type != SYS_RES_MEMORY) return (EINVAL); /* Starting with the most likely device list, search all three port * lists */ bhnd_port_type types[] = { BHND_PORT_DEVICE, BHND_PORT_AGENT, BHND_PORT_BRIDGE }; for (int i = 0; i < nitems(types); i++) { ports = bcma_corecfg_get_port_list(dinfo->corecfg, types[i]); STAILQ_FOREACH(port, ports, sp_link) { STAILQ_FOREACH(map, &port->sp_maps, m_link) { if (map->m_rid != rid) continue; *port_type = port->sp_type; *port_num = port->sp_num; *region_num = map->m_region_num; return (0); } } } return (ENOENT); } static int bcma_get_region_addr(device_t dev, device_t child, bhnd_port_type port_type, u_int port_num, u_int region_num, bhnd_addr_t *addr, bhnd_size_t *size) { struct bcma_devinfo *dinfo; struct bcma_map *map; struct bcma_sport_list *ports; struct bcma_sport *port; dinfo = device_get_ivars(child); ports = bcma_corecfg_get_port_list(dinfo->corecfg, port_type); /* Search the port list */ STAILQ_FOREACH(port, ports, sp_link) { if (port->sp_num != port_num) continue; STAILQ_FOREACH(map, &port->sp_maps, m_link) { if (map->m_region_num != region_num) continue; /* Found! */ *addr = map->m_base; *size = map->m_size; return (0); } } return (ENOENT); } static struct bhnd_devinfo * bcma_alloc_bhnd_dinfo(device_t dev) { struct bcma_devinfo *dinfo = bcma_alloc_dinfo(dev); return ((struct bhnd_devinfo *)dinfo); } static void bcma_free_bhnd_dinfo(device_t dev, struct bhnd_devinfo *dinfo) { bcma_free_dinfo(dev, (struct bcma_devinfo *)dinfo); } /** * Scan a device enumeration ROM table, adding all valid discovered cores to * the bus. * * @param bus The bcma bus. * @param erom_res An active resource mapping the EROM core. * @param erom_offset Base offset of the EROM core's register mapping. */ int bcma_add_children(device_t bus, struct resource *erom_res, bus_size_t erom_offset) { struct bcma_erom erom; struct bcma_corecfg *corecfg; struct bcma_devinfo *dinfo; device_t child; int error; corecfg = NULL; /* Initialize our reader */ error = bcma_erom_open(&erom, erom_res, erom_offset); if (error) return (error); /* Add all cores. */ while (!error) { /* Parse next core */ error = bcma_erom_parse_corecfg(&erom, &corecfg); if (error && error == ENOENT) { return (0); } else if (error) { goto failed; } /* Add the child device */ child = BUS_ADD_CHILD(bus, 0, NULL, -1); if (child == NULL) { error = ENXIO; goto failed; } /* Initialize device ivars */ dinfo = device_get_ivars(child); if ((error = bcma_init_dinfo(bus, dinfo, corecfg))) goto failed; /* The dinfo instance now owns the corecfg value */ corecfg = NULL; /* If pins are floating or the hardware is otherwise * unpopulated, the device shouldn't be used. */ if (bhnd_is_hw_disabled(child)) device_disable(child); + + /* Issue bus callback for fully initialized child. */ + BHND_BUS_CHILD_ADDED(bus, child); } /* Hit EOF parsing cores? */ if (error == ENOENT) return (0); failed: if (corecfg != NULL) bcma_free_corecfg(corecfg); return (error); } static device_method_t bcma_methods[] = { /* Device interface */ DEVMETHOD(device_probe, bcma_probe), DEVMETHOD(device_attach, bcma_attach), DEVMETHOD(device_detach, bcma_detach), /* Bus interface */ DEVMETHOD(bus_read_ivar, bcma_read_ivar), DEVMETHOD(bus_write_ivar, bcma_write_ivar), DEVMETHOD(bus_get_resource_list, bcma_get_resource_list), /* BHND interface */ DEVMETHOD(bhnd_bus_find_hostb_device, bcma_find_hostb_device), DEVMETHOD(bhnd_bus_alloc_devinfo, bcma_alloc_bhnd_dinfo), DEVMETHOD(bhnd_bus_free_devinfo, bcma_free_bhnd_dinfo), DEVMETHOD(bhnd_bus_reset_core, bcma_reset_core), DEVMETHOD(bhnd_bus_suspend_core, bcma_suspend_core), + DEVMETHOD(bhnd_bus_read_config, bcma_read_config), + DEVMETHOD(bhnd_bus_write_config, bcma_write_config), DEVMETHOD(bhnd_bus_get_port_count, bcma_get_port_count), DEVMETHOD(bhnd_bus_get_region_count, bcma_get_region_count), DEVMETHOD(bhnd_bus_get_port_rid, bcma_get_port_rid), DEVMETHOD(bhnd_bus_decode_port_rid, bcma_decode_port_rid), DEVMETHOD(bhnd_bus_get_region_addr, bcma_get_region_addr), DEVMETHOD_END }; DEFINE_CLASS_1(bhnd, bcma_driver, bcma_methods, sizeof(struct bcma_softc), bhnd_driver); MODULE_VERSION(bcma, 1); MODULE_DEPEND(bcma, bhnd, 1, 1, 1); Index: head/sys/dev/bhnd/bcma/bcma_dmp.h =================================================================== --- head/sys/dev/bhnd/bcma/bcma_dmp.h (revision 304869) +++ head/sys/dev/bhnd/bcma/bcma_dmp.h (revision 304870) @@ -1,193 +1,206 @@ /*- * Copyright (c) 2015 Landon Fuller * Copyright (c) 2010 Broadcom Corporation * * Portions of this file were derived from the aidmp.h header * distributed with Broadcom's initial brcm80211 Linux driver release, as * contributed to the Linux staging repository. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ #ifndef _BCMA_BCMA_DMP_H_ #define _BCMA_BCMA_DMP_H_ /* * PL-368 Device Management Plugin (DMP) Registers & Constants * * The "DMP" core used in Broadcom HND devices has been described * by Broadcom engineers (and in published header files) as being * ARM's PL-368 "Device Management Plugin" system IP, included with * the CoreLink AMBA Designer tooling. * * Documentation for the PL-368 is not publicly available, however, * and the only public reference by ARM to its existence appears to be * in the proprietary "NIC-301 Interconnect Device Management (PL368)" * errata publication, available to licensees as part of ARM's * CoreLink Controllers and Peripherals Engineering Errata. */ /* Out-of-band Router registers */ #define BCMA_OOB_BUSCONFIG 0x020 #define BCMA_OOB_STATUSA 0x100 #define BCMA_OOB_STATUSB 0x104 #define BCMA_OOB_STATUSC 0x108 #define BCMA_OOB_STATUSD 0x10c #define BCMA_OOB_ENABLEA0 0x200 #define BCMA_OOB_ENABLEA1 0x204 #define BCMA_OOB_ENABLEA2 0x208 #define BCMA_OOB_ENABLEA3 0x20c #define BCMA_OOB_ENABLEB0 0x280 #define BCMA_OOB_ENABLEB1 0x284 #define BCMA_OOB_ENABLEB2 0x288 #define BCMA_OOB_ENABLEB3 0x28c #define BCMA_OOB_ENABLEC0 0x300 #define BCMA_OOB_ENABLEC1 0x304 #define BCMA_OOB_ENABLEC2 0x308 #define BCMA_OOB_ENABLEC3 0x30c #define BCMA_OOB_ENABLED0 0x380 #define BCMA_OOB_ENABLED1 0x384 #define BCMA_OOB_ENABLED2 0x388 #define BCMA_OOB_ENABLED3 0x38c #define BCMA_OOB_ITCR 0xf00 #define BCMA_OOB_ITIPOOBA 0xf10 #define BCMA_OOB_ITIPOOBB 0xf14 #define BCMA_OOB_ITIPOOBC 0xf18 #define BCMA_OOB_ITIPOOBD 0xf1c #define BCMA_OOB_ITOPOOBA 0xf30 #define BCMA_OOB_ITOPOOBB 0xf34 #define BCMA_OOB_ITOPOOBC 0xf38 #define BCMA_OOB_ITOPOOBD 0xf3c /* DMP wrapper registers */ #define BCMA_DMP_OOBSELINA30 0x000 #define BCMA_DMP_OOBSELINA74 0x004 #define BCMA_DMP_OOBSELINB30 0x020 #define BCMA_DMP_OOBSELINB74 0x024 #define BCMA_DMP_OOBSELINC30 0x040 #define BCMA_DMP_OOBSELINC74 0x044 #define BCMA_DMP_OOBSELIND30 0x060 #define BCMA_DMP_OOBSELIND74 0x064 #define BCMA_DMP_OOBSELOUTA30 0x100 #define BCMA_DMP_OOBSELOUTA74 0x104 #define BCMA_DMP_OOBSELOUTB30 0x120 #define BCMA_DMP_OOBSELOUTB74 0x124 #define BCMA_DMP_OOBSELOUTC30 0x140 #define BCMA_DMP_OOBSELOUTC74 0x144 #define BCMA_DMP_OOBSELOUTD30 0x160 #define BCMA_DMP_OOBSELOUTD74 0x164 #define BCMA_DMP_OOBSYNCA 0x200 #define BCMA_DMP_OOBSELOUTAEN 0x204 #define BCMA_DMP_OOBSYNCB 0x220 #define BCMA_DMP_OOBSELOUTBEN 0x224 #define BCMA_DMP_OOBSYNCC 0x240 #define BCMA_DMP_OOBSELOUTCEN 0x244 #define BCMA_DMP_OOBSYNCD 0x260 #define BCMA_DMP_OOBSELOUTDEN 0x264 #define BCMA_DMP_OOBAEXTWIDTH 0x300 #define BCMA_DMP_OOBAINWIDTH 0x304 #define BCMA_DMP_OOBAOUTWIDTH 0x308 #define BCMA_DMP_OOBBEXTWIDTH 0x320 #define BCMA_DMP_OOBBINWIDTH 0x324 #define BCMA_DMP_OOBBOUTWIDTH 0x328 #define BCMA_DMP_OOBCEXTWIDTH 0x340 #define BCMA_DMP_OOBCINWIDTH 0x344 #define BCMA_DMP_OOBCOUTWIDTH 0x348 #define BCMA_DMP_OOBDEXTWIDTH 0x360 #define BCMA_DMP_OOBDINWIDTH 0x364 #define BCMA_DMP_OOBDOUTWIDTH 0x368 +/* The exact interpretation of these bits is unverified; these + * are our best guesses as to their use */ +#define BCMA_DMP_OOBSEL_MASK 0xFF /**< OOBSEL config mask */ +#define BCMA_DMP_OOBSEL_0_MASK BCMA_DMP_OOBSEL_MASK +#define BCMA_DMP_OOBSEL_1_MASK BCMA_DMP_OOBSEL_MASK +#define BCMA_DMP_OOBSEL_2_MASK BCMA_DMP_OOBSEL_MASK +#define BCMA_DMP_OOBSEL_3_MASK BCMA_DMP_OOBSEL_MASK +#define BCMA_DMP_OOBSEL_0_SHIFT 0 /**< first OOBSEL config */ +#define BCMA_DMP_OOBSEL_1_SHIFT 8 /**< second OOBSEL config */ +#define BCMA_DMP_OOBSEL_2_SHIFT 16 /**< third OOBSEL config */ +#define BCMA_DMP_OOBSEL_3_SHIFT 24 /**< fouth OOBSEL config */ +#define BCMA_DMP_OOBSEL_EN (1 << 7) /**< enable bit */ + // This was inherited from Broadcom's aidmp.h header // Is it required for any of our use-cases? #if 0 /* defined(IL_BIGENDIAN) && defined(BCMHND74K) */ /* Selective swapped defines for those registers we need in * big-endian code. */ #define BCMA_DMP_IOCTRLSET 0x404 #define BCMA_DMP_IOCTRLCLEAR 0x400 #define BCMA_DMP_IOCTRL 0x40c #define BCMA_DMP_IOSTATUS 0x504 #define BCMA_DMP_RESETCTRL 0x804 #define BCMA_DMP_RESETSTATUS 0x800 #else /* !IL_BIGENDIAN || !BCMHND74K */ #define BCMA_DMP_IOCTRLSET 0x400 #define BCMA_DMP_IOCTRLCLEAR 0x404 #define BCMA_DMP_IOCTRL 0x408 #define BCMA_DMP_IOSTATUS 0x500 #define BCMA_DMP_RESETCTRL 0x800 #define BCMA_DMP_RESETSTATUS 0x804 #endif /* IL_BIGENDIAN && BCMHND74K */ #define BCMA_DMP_IOCTRLWIDTH 0x700 #define BCMA_DMP_IOSTATUSWIDTH 0x704 #define BCMA_DMP_RESETREADID 0x808 #define BCMA_DMP_RESETWRITEID 0x80c #define BCMA_DMP_ERRLOGCTRL 0xa00 #define BCMA_DMP_ERRLOGDONE 0xa04 #define BCMA_DMP_ERRLOGSTATUS 0xa08 #define BCMA_DMP_ERRLOGADDRLO 0xa0c #define BCMA_DMP_ERRLOGADDRHI 0xa10 #define BCMA_DMP_ERRLOGID 0xa14 #define BCMA_DMP_ERRLOGUSER 0xa18 #define BCMA_DMP_ERRLOGFLAGS 0xa1c #define BCMA_DMP_INTSTATUS 0xa00 #define BCMA_DMP_CONFIG 0xe00 #define BCMA_DMP_ITCR 0xf00 #define BCMA_DMP_ITIPOOBA 0xf10 #define BCMA_DMP_ITIPOOBB 0xf14 #define BCMA_DMP_ITIPOOBC 0xf18 #define BCMA_DMP_ITIPOOBD 0xf1c #define BCMA_DMP_ITIPOOBAOUT 0xf30 #define BCMA_DMP_ITIPOOBBOUT 0xf34 #define BCMA_DMP_ITIPOOBCOUT 0xf38 #define BCMA_DMP_ITIPOOBDOUT 0xf3c #define BCMA_DMP_ITOPOOBA 0xf50 #define BCMA_DMP_ITOPOOBB 0xf54 #define BCMA_DMP_ITOPOOBC 0xf58 #define BCMA_DMP_ITOPOOBD 0xf5c #define BCMA_DMP_ITOPOOBAIN 0xf70 #define BCMA_DMP_ITOPOOBBIN 0xf74 #define BCMA_DMP_ITOPOOBCIN 0xf78 #define BCMA_DMP_ITOPOOBDIN 0xf7c #define BCMA_DMP_ITOPRESET 0xf90 #define BCMA_DMP_PERIPHERIALID4 0xfd0 #define BCMA_DMP_PERIPHERIALID5 0xfd4 #define BCMA_DMP_PERIPHERIALID6 0xfd8 #define BCMA_DMP_PERIPHERIALID7 0xfdc #define BCMA_DMP_PERIPHERIALID0 0xfe0 #define BCMA_DMP_PERIPHERIALID1 0xfe4 #define BCMA_DMP_PERIPHERIALID2 0xfe8 #define BCMA_DMP_PERIPHERIALID3 0xfec #define BCMA_DMP_COMPONENTID0 0xff0 #define BCMA_DMP_COMPONENTID1 0xff4 #define BCMA_DMP_COMPONENTID2 0xff8 #define BCMA_DMP_COMPONENTID3 0xffc /* resetctrl */ #define BMCA_DMP_RC_RESET 1 /* config */ #define BCMA_DMP_CFG_OOB 0x00000020 #define BCMA_DMP_CFG_IOS 0x00000010 #define BCMA_DMP_CFGIOC 0x00000008 #define BCMA_DMP_CFGTO 0x00000004 #define BCMA_DMP_CFGERRL 0x00000002 #define BCMA_DMP_CFGRST 0x00000001 #endif /* _BCMA_BCMA_DMP_H_ */ Index: head/sys/dev/bhnd/bhnd.c =================================================================== --- head/sys/dev/bhnd/bhnd.c (revision 304869) +++ head/sys/dev/bhnd/bhnd.c (revision 304870) @@ -1,1067 +1,1330 @@ /*- - * Copyright (c) 2015 Landon Fuller + * Copyright (c) 2015-2016 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); /* * Broadcom Home Networking Division (HND) Bus Driver. * * The Broadcom HND family of devices consists of both SoCs and host-connected * networking chipsets containing a common family of Broadcom IP cores, * including an integrated MIPS and/or ARM cores. * * HND devices expose a nearly identical interface whether accessible over a * native SoC interconnect, or when connected via a host interface such as * PCIe. As a result, the majority of hardware support code should be re-usable * across host drivers for HND networking chipsets, as well as FreeBSD support * for Broadcom MIPS/ARM HND SoCs. * * Earlier HND models used the siba(4) on-chip interconnect, while later models * use bcma(4); the programming model is almost entirely independent * of the actual underlying interconect. */ #include #include #include #include #include #include #include #include #include +#include +#include + #include "bhnd_chipc_if.h" #include "bhnd_nvram_if.h" #include "bhnd.h" #include "bhndvar.h" MALLOC_DEFINE(M_BHND, "bhnd", "bhnd bus data structures"); /* Bus pass at which all bus-required children must be available, and * attachment may be finalized. */ #define BHND_FINISH_ATTACH_PASS BUS_PASS_DEFAULT /** * bhnd_generic_probe_nomatch() reporting configuration. */ static const struct bhnd_nomatch { uint16_t vendor; /**< core designer */ uint16_t device; /**< core id */ bool if_verbose; /**< print when bootverbose is set. */ } bhnd_nomatch_table[] = { { BHND_MFGID_ARM, BHND_COREID_OOB_ROUTER, true }, { BHND_MFGID_ARM, BHND_COREID_EROM, true }, { BHND_MFGID_ARM, BHND_COREID_PL301, true }, { BHND_MFGID_ARM, BHND_COREID_APB_BRIDGE, true }, { BHND_MFGID_ARM, BHND_COREID_AXI_UNMAPPED, false }, { BHND_MFGID_INVALID, BHND_COREID_INVALID, false } }; static int bhnd_delete_children(struct bhnd_softc *sc); static int bhnd_finish_attach(struct bhnd_softc *sc); static device_t bhnd_find_chipc(struct bhnd_softc *sc); static struct chipc_caps *bhnd_find_chipc_caps(struct bhnd_softc *sc); static device_t bhnd_find_platform_dev(struct bhnd_softc *sc, const char *classname); static device_t bhnd_find_pmu(struct bhnd_softc *sc); static device_t bhnd_find_nvram(struct bhnd_softc *sc); static int compare_ascending_probe_order(const void *lhs, const void *rhs); static int compare_descending_probe_order(const void *lhs, const void *rhs); /** * Default bhnd(4) bus driver implementation of DEVICE_ATTACH(). * * This implementation calls device_probe_and_attach() for each of the device's * children, in bhnd probe order. */ int bhnd_generic_attach(device_t dev) { struct bhnd_softc *sc; device_t *devs; int ndevs; int error; if (device_is_attached(dev)) return (EBUSY); sc = device_get_softc(dev); sc->dev = dev; if ((error = device_get_children(dev, &devs, &ndevs))) return (error); /* Probe and attach all children */ qsort(devs, ndevs, sizeof(*devs), compare_ascending_probe_order); for (int i = 0; i < ndevs; i++) { device_t child = devs[i]; device_probe_and_attach(child); } /* Try to finalize attachment */ if (bus_current_pass >= BHND_FINISH_ATTACH_PASS) { if ((error = bhnd_finish_attach(sc))) goto cleanup; } cleanup: free(devs, M_TEMP); if (error) bhnd_delete_children(sc); return (error); } /** * Detach and delete all children, in reverse of their attach order. */ static int bhnd_delete_children(struct bhnd_softc *sc) { device_t *devs; int ndevs; int error; if ((error = device_get_children(sc->dev, &devs, &ndevs))) return (error); /* Detach in the reverse of attach order */ qsort(devs, ndevs, sizeof(*devs), compare_descending_probe_order); for (int i = 0; i < ndevs; i++) { device_t child = devs[i]; /* Terminate on first error */ if ((error = device_delete_child(sc->dev, child))) goto cleanup; } cleanup: free(devs, M_TEMP); return (error); } /** * Default bhnd(4) bus driver implementation of DEVICE_DETACH(). * * This implementation calls device_detach() for each of the device's * children, in reverse bhnd probe order, terminating if any call to * device_detach() fails. */ int bhnd_generic_detach(device_t dev) { struct bhnd_softc *sc; if (!device_is_attached(dev)) return (EBUSY); sc = device_get_softc(dev); return (bhnd_delete_children(sc)); } /** * Default bhnd(4) bus driver implementation of DEVICE_SHUTDOWN(). * * This implementation calls device_shutdown() for each of the device's * children, in reverse bhnd probe order, terminating if any call to * device_shutdown() fails. */ int bhnd_generic_shutdown(device_t dev) { device_t *devs; int ndevs; int error; if (!device_is_attached(dev)) return (EBUSY); if ((error = device_get_children(dev, &devs, &ndevs))) return (error); /* Shutdown in the reverse of attach order */ qsort(devs, ndevs, sizeof(*devs), compare_descending_probe_order); for (int i = 0; i < ndevs; i++) { device_t child = devs[i]; /* Terminate on first error */ if ((error = device_shutdown(child))) goto cleanup; } cleanup: free(devs, M_TEMP); return (error); } /** * Default bhnd(4) bus driver implementation of DEVICE_RESUME(). * * This implementation calls BUS_RESUME_CHILD() for each of the device's * children in bhnd probe order, terminating if any call to BUS_RESUME_CHILD() * fails. */ int bhnd_generic_resume(device_t dev) { device_t *devs; int ndevs; int error; if (!device_is_attached(dev)) return (EBUSY); if ((error = device_get_children(dev, &devs, &ndevs))) return (error); qsort(devs, ndevs, sizeof(*devs), compare_ascending_probe_order); for (int i = 0; i < ndevs; i++) { device_t child = devs[i]; /* Terminate on first error */ if ((error = BUS_RESUME_CHILD(device_get_parent(child), child))) goto cleanup; } cleanup: free(devs, M_TEMP); return (error); } /** * Default bhnd(4) bus driver implementation of DEVICE_SUSPEND(). * * This implementation calls BUS_SUSPEND_CHILD() for each of the device's * children in reverse bhnd probe order. If any call to BUS_SUSPEND_CHILD() * fails, the suspend operation is terminated and any devices that were * suspended are resumed immediately by calling their BUS_RESUME_CHILD() * methods. */ int bhnd_generic_suspend(device_t dev) { device_t *devs; int ndevs; int error; if (!device_is_attached(dev)) return (EBUSY); if ((error = device_get_children(dev, &devs, &ndevs))) return (error); /* Suspend in the reverse of attach order */ qsort(devs, ndevs, sizeof(*devs), compare_descending_probe_order); for (int i = 0; i < ndevs; i++) { device_t child = devs[i]; error = BUS_SUSPEND_CHILD(device_get_parent(child), child); /* On error, resume suspended devices and then terminate */ if (error) { for (int j = 0; j < i; j++) { BUS_RESUME_CHILD(device_get_parent(devs[j]), devs[j]); } goto cleanup; } } cleanup: free(devs, M_TEMP); return (error); } static void bhnd_new_pass(device_t dev) { struct bhnd_softc *sc; int error; sc = device_get_softc(dev); /* Attach any permissible children */ bus_generic_new_pass(dev); /* Finalize attachment */ if (!sc->attach_done && bus_current_pass >= BHND_FINISH_ATTACH_PASS) { if ((error = bhnd_finish_attach(sc))) { panic("bhnd_finish_attach() failed: %d", error); } } } /* * Finish any pending bus attachment operations. * * When attached as a SoC bus (as opposed to a bridged WiFi device), our * platform devices may not be attached until later bus passes, necessitating * delayed initialization on our part. */ static int bhnd_finish_attach(struct bhnd_softc *sc) { struct chipc_caps *ccaps; - GIANT_REQUIRED; /* newbus */ + GIANT_REQUIRED; /* for newbus */ KASSERT(bus_current_pass >= BHND_FINISH_ATTACH_PASS, ("bhnd_finish_attach() called in pass %d", bus_current_pass)); KASSERT(!sc->attach_done, ("duplicate call to bhnd_finish_attach()")); /* Locate chipc device */ if ((sc->chipc_dev = bhnd_find_chipc(sc)) == NULL) { device_printf(sc->dev, "error: ChipCommon device not found\n"); return (ENXIO); } ccaps = BHND_CHIPC_GET_CAPS(sc->chipc_dev); /* Look for NVRAM device */ if (ccaps->nvram_src != BHND_NVRAM_SRC_UNKNOWN) { if ((sc->nvram_dev = bhnd_find_nvram(sc)) == NULL) { device_printf(sc->dev, "warning: NVRAM %s device not found\n", bhnd_nvram_src_name(ccaps->nvram_src)); } } /* Look for a PMU */ - if (ccaps->pmu) { + if (ccaps->pmu || ccaps->pwr_ctrl) { if ((sc->pmu_dev = bhnd_find_pmu(sc)) == NULL) { device_printf(sc->dev, - "warning: PMU device not found\n"); + "attach failed: supported PMU not found\n"); + return (ENXIO); } } /* Mark attach as completed */ sc->attach_done = true; return (0); } /* Locate the ChipCommon core. */ static device_t bhnd_find_chipc(struct bhnd_softc *sc) { device_t chipc; /* Make sure we're holding Giant for newbus */ GIANT_REQUIRED; /* chipc_dev is initialized during attachment */ if (sc->attach_done) { if ((chipc = sc->chipc_dev) == NULL) return (NULL); goto found; } /* Locate chipc core with a core unit of 0 */ chipc = bhnd_find_child(sc->dev, BHND_DEVCLASS_CC, 0); if (chipc == NULL) return (NULL); found: if (device_get_state(chipc) < DS_ATTACHING) { device_printf(sc->dev, "chipc found, but did not attach\n"); return (NULL); } return (chipc); } /* Locate the ChipCommon core and return the device capabilities */ static struct chipc_caps * bhnd_find_chipc_caps(struct bhnd_softc *sc) { device_t chipc; if ((chipc = bhnd_find_chipc(sc)) == NULL) { device_printf(sc->dev, "chipc unavailable; cannot fetch capabilities\n"); return (NULL); } return (BHND_CHIPC_GET_CAPS(chipc)); } /** * Find an attached platform device on @p dev, searching first for cores * matching @p classname, and if not found, searching the children of the first * bhnd_chipc device on the bus. * * @param sc Driver state. * @param chipc Attached ChipCommon device. * @param classname Device class to search for. * * @retval device_t A matching device. * @retval NULL If no matching device is found. */ static device_t bhnd_find_platform_dev(struct bhnd_softc *sc, const char *classname) { device_t chipc, child; /* Make sure we're holding Giant for newbus */ GIANT_REQUIRED; /* Look for a directly-attached child */ child = device_find_child(sc->dev, classname, -1); if (child != NULL) goto found; /* Look for the first matching ChipCommon child */ if ((chipc = bhnd_find_chipc(sc)) == NULL) { device_printf(sc->dev, "chipc unavailable; cannot locate %s\n", classname); return (NULL); } child = device_find_child(chipc, classname, -1); if (child != NULL) goto found; /* Look for a parent-attached device (e.g. nexus0 -> bhnd_nvram) */ child = device_find_child(device_get_parent(sc->dev), classname, -1); if (child == NULL) return (NULL); found: if (device_get_state(child) < DS_ATTACHING) return (NULL); return (child); } /* Locate the PMU device, if any */ static device_t bhnd_find_pmu(struct bhnd_softc *sc) { - struct chipc_caps *ccaps; - /* Make sure we're holding Giant for newbus */ GIANT_REQUIRED; /* pmu_dev is initialized during attachment */ if (sc->attach_done) { if (sc->pmu_dev == NULL) return (NULL); if (device_get_state(sc->pmu_dev) < DS_ATTACHING) return (NULL); return (sc->pmu_dev); } - if ((ccaps = bhnd_find_chipc_caps(sc)) == NULL) - return (NULL); - if (!ccaps->pmu) - return (NULL); - return (bhnd_find_platform_dev(sc, "bhnd_pmu")); } /* Locate the NVRAM device, if any */ static device_t bhnd_find_nvram(struct bhnd_softc *sc) { struct chipc_caps *ccaps; /* Make sure we're holding Giant for newbus */ GIANT_REQUIRED; /* nvram_dev is initialized during attachment */ if (sc->attach_done) { if (sc->nvram_dev == NULL) return (NULL); if (device_get_state(sc->nvram_dev) < DS_ATTACHING) return (NULL); return (sc->nvram_dev); } if ((ccaps = bhnd_find_chipc_caps(sc)) == NULL) return (NULL); if (ccaps->nvram_src == BHND_NVRAM_SRC_UNKNOWN) return (NULL); return (bhnd_find_platform_dev(sc, "bhnd_nvram")); } /* * Ascending comparison of bhnd device's probe order. */ static int compare_ascending_probe_order(const void *lhs, const void *rhs) { device_t ldev, rdev; int lorder, rorder; ldev = (*(const device_t *) lhs); rdev = (*(const device_t *) rhs); lorder = BHND_BUS_GET_PROBE_ORDER(device_get_parent(ldev), ldev); rorder = BHND_BUS_GET_PROBE_ORDER(device_get_parent(rdev), rdev); if (lorder < rorder) { return (-1); } else if (lorder > rorder) { return (1); } else { return (0); } } /* * Descending comparison of bhnd device's probe order. */ static int compare_descending_probe_order(const void *lhs, const void *rhs) { return (compare_ascending_probe_order(rhs, lhs)); } /** * Default bhnd(4) bus driver implementation of BHND_BUS_GET_PROBE_ORDER(). * * This implementation determines probe ordering based on the device's class * and other properties, including whether the device is serving as a host * bridge. */ int bhnd_generic_get_probe_order(device_t dev, device_t child) { switch (bhnd_get_class(child)) { case BHND_DEVCLASS_CC: /* Must be early enough to provide NVRAM access to the * host bridge */ return (BHND_PROBE_ROOT + BHND_PROBE_ORDER_FIRST); case BHND_DEVCLASS_CC_B: /* fall through */ case BHND_DEVCLASS_PMU: return (BHND_PROBE_BUS + BHND_PROBE_ORDER_EARLY); case BHND_DEVCLASS_SOC_ROUTER: return (BHND_PROBE_BUS + BHND_PROBE_ORDER_LATE); case BHND_DEVCLASS_SOC_BRIDGE: return (BHND_PROBE_BUS + BHND_PROBE_ORDER_LAST); case BHND_DEVCLASS_CPU: return (BHND_PROBE_CPU + BHND_PROBE_ORDER_FIRST); case BHND_DEVCLASS_RAM: /* fall through */ case BHND_DEVCLASS_MEMC: return (BHND_PROBE_CPU + BHND_PROBE_ORDER_EARLY); case BHND_DEVCLASS_NVRAM: return (BHND_PROBE_RESOURCE + BHND_PROBE_ORDER_EARLY); case BHND_DEVCLASS_PCI: case BHND_DEVCLASS_PCIE: case BHND_DEVCLASS_PCCARD: case BHND_DEVCLASS_ENET: case BHND_DEVCLASS_ENET_MAC: case BHND_DEVCLASS_ENET_PHY: case BHND_DEVCLASS_WLAN: case BHND_DEVCLASS_WLAN_MAC: case BHND_DEVCLASS_WLAN_PHY: case BHND_DEVCLASS_EROM: case BHND_DEVCLASS_OTHER: case BHND_DEVCLASS_INVALID: if (bhnd_find_hostb_device(dev) == child) return (BHND_PROBE_ROOT + BHND_PROBE_ORDER_EARLY); return (BHND_PROBE_DEFAULT); default: return (BHND_PROBE_DEFAULT); } } /** + * Default bhnd(4) bus driver implementation of BHND_BUS_ALLOC_PMU(). + */ +int +bhnd_generic_alloc_pmu(device_t dev, device_t child) +{ + struct bhnd_softc *sc; + struct bhnd_resource *br; + struct chipc_caps *ccaps; + struct bhnd_devinfo *dinfo; + struct bhnd_core_pmu_info *pm; + struct resource_list *rl; + struct resource_list_entry *rle; + device_t pmu_dev; + bhnd_addr_t r_addr; + bhnd_size_t r_size; + bus_size_t pmu_regs; + int error; + + GIANT_REQUIRED; /* for newbus */ + + sc = device_get_softc(dev); + dinfo = device_get_ivars(child); + pmu_regs = BHND_CLK_CTL_ST; + + if ((ccaps = bhnd_find_chipc_caps(sc)) == NULL) { + device_printf(sc->dev, "alloc_pmu failed: chipc " + "capabilities unavailable\n"); + return (ENXIO); + } + + if ((pmu_dev = bhnd_find_pmu(sc)) == NULL) { + device_printf(sc->dev, + "pmu unavailable; cannot allocate request state\n"); + return (ENXIO); + } + + /* already allocated? */ + if (dinfo->pmu_info != NULL) { + panic("duplicate PMU allocation for %s", + device_get_nameunit(child)); + } + + /* Determine address+size of the core's PMU register block */ + error = bhnd_get_region_addr(child, BHND_PORT_DEVICE, 0, 0, &r_addr, + &r_size); + if (error) { + device_printf(sc->dev, "error fetching register block info for " + "%s: %d\n", device_get_nameunit(child), error); + return (error); + } + + if (r_size < (pmu_regs + sizeof(uint32_t))) { + device_printf(sc->dev, "pmu offset %#jx would overrun %s " + "register block\n", (uintmax_t)pmu_regs, + device_get_nameunit(child)); + return (ENODEV); + } + + /* Locate actual resource containing the core's register block */ + if ((rl = BUS_GET_RESOURCE_LIST(dev, child)) == NULL) { + device_printf(dev, "NULL resource list returned for %s\n", + device_get_nameunit(child)); + return (ENXIO); + } + + if ((rle = resource_list_find(rl, SYS_RES_MEMORY, 0)) == NULL) { + device_printf(dev, "cannot locate core register resource " + "for %s\n", device_get_nameunit(child)); + return (ENXIO); + } + + if (rle->res == NULL) { + device_printf(dev, "core register resource unallocated for " + "%s\n", device_get_nameunit(child)); + return (ENXIO); + } + + if (r_addr+pmu_regs < rman_get_start(rle->res) || + r_addr+pmu_regs >= rman_get_end(rle->res)) + { + device_printf(dev, "core register resource does not map PMU " + "registers at %#jx\n for %s\n", r_addr+pmu_regs, + device_get_nameunit(child)); + return (ENXIO); + } + + /* Adjust PMU register offset relative to the actual start address + * of the core's register block allocation. + * + * XXX: The saved offset will be invalid if bus_adjust_resource is + * used to modify the resource's start address. + */ + if (rman_get_start(rle->res) > r_addr) + pmu_regs -= rman_get_start(rle->res) - r_addr; + else + pmu_regs -= r_addr - rman_get_start(rle->res); + + /* Allocate and initialize PMU info */ + br = malloc(sizeof(struct bhnd_resource), M_BHND, M_NOWAIT); + if (br == NULL) + return (ENOMEM); + + br->res = rle->res; + br->direct = ((rman_get_flags(rle->res) & RF_ACTIVE) != 0); + + pm = malloc(sizeof(*dinfo->pmu_info), M_BHND, M_NOWAIT); + if (pm == NULL) { + free(br, M_BHND); + return (ENOMEM); + } + pm->pm_dev = child; + pm->pm_pmu = pmu_dev; + pm->pm_res = br; + pm->pm_regs = pmu_regs; + + dinfo->pmu_info = pm; + return (0); +} + +/** + * Default bhnd(4) bus driver implementation of BHND_BUS_RELEASE_PMU(). + */ +int +bhnd_generic_release_pmu(device_t dev, device_t child) +{ + struct bhnd_softc *sc; + struct bhnd_devinfo *dinfo; + device_t pmu; + int error; + + GIANT_REQUIRED; /* for newbus */ + + sc = device_get_softc(dev); + dinfo = device_get_ivars(child); + + if ((pmu = bhnd_find_pmu(sc)) == NULL) { + device_printf(sc->dev, + "pmu unavailable; cannot release request state\n"); + return (ENXIO); + } + + /* dispatch release request */ + if (dinfo->pmu_info == NULL) + panic("pmu over-release for %s", device_get_nameunit(child)); + + if ((error = BHND_PMU_CORE_RELEASE(pmu, dinfo->pmu_info))) + return (error); + + /* free PMU info */ + free(dinfo->pmu_info->pm_res, M_BHND); + free(dinfo->pmu_info, M_BHND); + dinfo->pmu_info = NULL; + + return (0); +} + +/** + * Default bhnd(4) bus driver implementation of BHND_BUS_REQUEST_CLOCK(). + */ +int +bhnd_generic_request_clock(device_t dev, device_t child, bhnd_clock clock) +{ + struct bhnd_softc *sc; + struct bhnd_devinfo *dinfo; + struct bhnd_core_pmu_info *pm; + + sc = device_get_softc(dev); + dinfo = device_get_ivars(child); + + if ((pm = dinfo->pmu_info) == NULL) + panic("no active PMU request state"); + + /* dispatch request to PMU */ + return (BHND_PMU_CORE_REQ_CLOCK(pm->pm_pmu, pm, clock)); +} + +/** + * Default bhnd(4) bus driver implementation of BHND_BUS_ENABLE_CLOCKS(). + */ +int +bhnd_generic_enable_clocks(device_t dev, device_t child, uint32_t clocks) +{ + struct bhnd_softc *sc; + struct bhnd_devinfo *dinfo; + struct bhnd_core_pmu_info *pm; + + sc = device_get_softc(dev); + dinfo = device_get_ivars(child); + + if ((pm = dinfo->pmu_info) == NULL) + panic("no active PMU request state"); + + /* dispatch request to PMU */ + return (BHND_PMU_CORE_EN_CLOCKS(pm->pm_pmu, pm, clocks)); +} + +/** + * Default bhnd(4) bus driver implementation of BHND_BUS_REQUEST_EXT_RSRC(). + */ +int +bhnd_generic_request_ext_rsrc(device_t dev, device_t child, u_int rsrc) +{ + struct bhnd_softc *sc; + struct bhnd_devinfo *dinfo; + struct bhnd_core_pmu_info *pm; + + sc = device_get_softc(dev); + dinfo = device_get_ivars(child); + + if ((pm = dinfo->pmu_info) == NULL) + panic("no active PMU request state"); + + /* dispatch request to PMU */ + return (BHND_PMU_CORE_REQ_EXT_RSRC(pm->pm_pmu, pm, rsrc)); +} + +/** + * Default bhnd(4) bus driver implementation of BHND_BUS_RELEASE_EXT_RSRC(). + */ +int +bhnd_generic_release_ext_rsrc(device_t dev, device_t child, u_int rsrc) +{ + struct bhnd_softc *sc; + struct bhnd_devinfo *dinfo; + struct bhnd_core_pmu_info *pm; + + sc = device_get_softc(dev); + dinfo = device_get_ivars(child); + + if ((pm = dinfo->pmu_info) == NULL) + panic("no active PMU request state"); + + /* dispatch request to PMU */ + return (BHND_PMU_CORE_RELEASE_EXT_RSRC(pm->pm_pmu, pm, rsrc)); +} + + +/** * Default bhnd(4) bus driver implementation of BHND_BUS_IS_REGION_VALID(). * * This implementation assumes that port and region numbers are 0-indexed and * are allocated non-sparsely, using BHND_BUS_GET_PORT_COUNT() and * BHND_BUS_GET_REGION_COUNT() to determine if @p port and @p region fall * within the defined range. */ static bool bhnd_generic_is_region_valid(device_t dev, device_t child, bhnd_port_type type, u_int port, u_int region) { if (port >= bhnd_get_port_count(child, type)) return (false); if (region >= bhnd_get_region_count(child, type, port)) return (false); return (true); } /** * Default bhnd(4) bus driver implementation of BHND_BUS_GET_NVRAM_VAR(). * * This implementation searches @p dev for a usable NVRAM child device. * * If no usable child device is found on @p dev, the request is delegated to * the BHND_BUS_GET_NVRAM_VAR() method on the parent of @p dev. */ int bhnd_generic_get_nvram_var(device_t dev, device_t child, const char *name, void *buf, size_t *size, bhnd_nvram_type type) { struct bhnd_softc *sc; device_t nvram, parent; sc = device_get_softc(dev); /* If a NVRAM device is available, consult it first */ if ((nvram = bhnd_find_nvram(sc)) != NULL) return BHND_NVRAM_GETVAR(nvram, name, buf, size, type); /* Otherwise, try to delegate to parent */ if ((parent = device_get_parent(dev)) == NULL) return (ENODEV); return (BHND_BUS_GET_NVRAM_VAR(device_get_parent(dev), child, name, buf, size, type)); } /** * Default bhnd(4) bus driver implementation of BUS_PRINT_CHILD(). * * This implementation requests the device's struct resource_list via * BUS_GET_RESOURCE_LIST. */ int bhnd_generic_print_child(device_t dev, device_t child) { struct resource_list *rl; int retval = 0; retval += bus_print_child_header(dev, child); rl = BUS_GET_RESOURCE_LIST(dev, child); if (rl != NULL) { retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); } retval += printf(" at core %u", bhnd_get_core_index(child)); retval += bus_print_child_domain(dev, child); retval += bus_print_child_footer(dev, child); return (retval); } /** * Default bhnd(4) bus driver implementation of BUS_PROBE_NOMATCH(). * * This implementation requests the device's struct resource_list via * BUS_GET_RESOURCE_LIST. */ void bhnd_generic_probe_nomatch(device_t dev, device_t child) { struct resource_list *rl; const struct bhnd_nomatch *nm; bool report; /* Fetch reporting configuration for this device */ report = true; for (nm = bhnd_nomatch_table; nm->device != BHND_COREID_INVALID; nm++) { if (nm->vendor != bhnd_get_vendor(child)) continue; if (nm->device != bhnd_get_device(child)) continue; report = false; if (bootverbose && nm->if_verbose) report = true; break; } if (!report) return; /* Print the non-matched device info */ device_printf(dev, "<%s %s>", bhnd_get_vendor_name(child), bhnd_get_device_name(child)); rl = BUS_GET_RESOURCE_LIST(dev, child); if (rl != NULL) resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); printf(" at core %u (no driver attached)\n", bhnd_get_core_index(child)); } /** * Default implementation of BUS_CHILD_PNPINFO_STR(). */ static int bhnd_child_pnpinfo_str(device_t dev, device_t child, char *buf, size_t buflen) { if (device_get_parent(child) != dev) { return (BUS_CHILD_PNPINFO_STR(device_get_parent(dev), child, buf, buflen)); } snprintf(buf, buflen, "vendor=0x%hx device=0x%hx rev=0x%hhx", bhnd_get_vendor(child), bhnd_get_device(child), bhnd_get_hwrev(child)); return (0); } /** * Default implementation of BUS_CHILD_LOCATION_STR(). */ static int bhnd_child_location_str(device_t dev, device_t child, char *buf, size_t buflen) { bhnd_addr_t addr; bhnd_size_t size; if (device_get_parent(child) != dev) { return (BUS_CHILD_LOCATION_STR(device_get_parent(dev), child, buf, buflen)); } if (bhnd_get_region_addr(child, BHND_PORT_DEVICE, 0, 0, &addr, &size)) { /* No device default port/region */ if (buflen > 0) *buf = '\0'; return (0); } snprintf(buf, buflen, "port0.0=0x%llx", (unsigned long long) addr); return (0); } /** * Default bhnd(4) bus driver implementation of BUS_ADD_CHILD(). * * This implementation manages internal bhnd(4) state, and must be called * by subclassing drivers. */ device_t bhnd_generic_add_child(device_t dev, u_int order, const char *name, int unit) { struct bhnd_devinfo *dinfo; device_t child; child = device_add_child_ordered(dev, order, name, unit); if (child == NULL) return (NULL); if ((dinfo = BHND_BUS_ALLOC_DEVINFO(dev)) == NULL) { device_delete_child(dev, child); return (NULL); } device_set_ivars(child, dinfo); - /* Inform concrete bus driver. */ - BHND_BUS_CHILD_ADDED(dev, child); - return (child); } /** + * Default bhnd(4) bus driver implementation of BHND_BUS_CHILD_ADDED(). + * + * This implementation manages internal bhnd(4) state, and must be called + * by subclassing drivers. + */ +void +bhnd_generic_child_added(device_t dev, device_t child) +{ +} + +/** * Default bhnd(4) bus driver implementation of BUS_CHILD_DELETED(). * * This implementation manages internal bhnd(4) state, and must be called * by subclassing drivers. */ void bhnd_generic_child_deleted(device_t dev, device_t child) { struct bhnd_softc *sc; struct bhnd_devinfo *dinfo; sc = device_get_softc(dev); /* Free device info */ - if ((dinfo = device_get_ivars(child)) != NULL) + if ((dinfo = device_get_ivars(child)) != NULL) { + if (dinfo->pmu_info != NULL) { + /* Releasing PMU requests automatically would be nice, + * but we can't reference per-core PMU register + * resource after driver detach */ + panic("%s leaked device pmu state\n", + device_get_nameunit(child)); + } + BHND_BUS_FREE_DEVINFO(dev, dinfo); + } /* Clean up platform device references */ if (sc->chipc_dev == child) { sc->chipc_dev = NULL; } else if (sc->nvram_dev == child) { sc->nvram_dev = NULL; } else if (sc->pmu_dev == child) { sc->pmu_dev = NULL; } } /** * Helper function for implementing BUS_SUSPEND_CHILD(). * * TODO: Power management * * If @p child is not a direct child of @p dev, suspension is delegated to * the @p dev parent. */ int bhnd_generic_suspend_child(device_t dev, device_t child) { if (device_get_parent(child) != dev) BUS_SUSPEND_CHILD(device_get_parent(dev), child); return bus_generic_suspend_child(dev, child); } /** * Helper function for implementing BUS_RESUME_CHILD(). * * TODO: Power management * * If @p child is not a direct child of @p dev, suspension is delegated to * the @p dev parent. */ int bhnd_generic_resume_child(device_t dev, device_t child) { if (device_get_parent(child) != dev) BUS_RESUME_CHILD(device_get_parent(dev), child); return bus_generic_resume_child(dev, child); } /* * Delegate all indirect I/O to the parent device. When inherited by * non-bridged bus implementations, resources will never be marked as * indirect, and these methods will never be called. */ #define BHND_IO_READ(_type, _name, _method) \ static _type \ bhnd_read_ ## _name (device_t dev, device_t child, \ struct bhnd_resource *r, bus_size_t offset) \ { \ return (BHND_BUS_READ_ ## _method( \ device_get_parent(dev), child, r, offset)); \ } #define BHND_IO_WRITE(_type, _name, _method) \ static void \ bhnd_write_ ## _name (device_t dev, device_t child, \ struct bhnd_resource *r, bus_size_t offset, _type value) \ { \ return (BHND_BUS_WRITE_ ## _method( \ device_get_parent(dev), child, r, offset, \ value)); \ } #define BHND_IO_MISC(_type, _op, _method) \ static void \ bhnd_ ## _op (device_t dev, device_t child, \ struct bhnd_resource *r, bus_size_t offset, _type datap, \ bus_size_t count) \ { \ BHND_BUS_ ## _method(device_get_parent(dev), child, r, \ offset, datap, count); \ } #define BHND_IO_METHODS(_type, _size) \ BHND_IO_READ(_type, _size, _size) \ BHND_IO_WRITE(_type, _size, _size) \ \ BHND_IO_READ(_type, stream_ ## _size, STREAM_ ## _size) \ BHND_IO_WRITE(_type, stream_ ## _size, STREAM_ ## _size) \ \ BHND_IO_MISC(_type*, read_multi_ ## _size, \ READ_MULTI_ ## _size) \ BHND_IO_MISC(_type*, write_multi_ ## _size, \ WRITE_MULTI_ ## _size) \ \ BHND_IO_MISC(_type*, read_multi_stream_ ## _size, \ READ_MULTI_STREAM_ ## _size) \ BHND_IO_MISC(_type*, write_multi_stream_ ## _size, \ WRITE_MULTI_STREAM_ ## _size) \ \ BHND_IO_MISC(_type, set_multi_ ## _size, SET_MULTI_ ## _size) \ BHND_IO_MISC(_type, set_region_ ## _size, SET_REGION_ ## _size) \ \ BHND_IO_MISC(_type*, read_region_ ## _size, \ READ_REGION_ ## _size) \ BHND_IO_MISC(_type*, write_region_ ## _size, \ WRITE_REGION_ ## _size) \ \ BHND_IO_MISC(_type*, read_region_stream_ ## _size, \ READ_REGION_STREAM_ ## _size) \ BHND_IO_MISC(_type*, write_region_stream_ ## _size, \ WRITE_REGION_STREAM_ ## _size) \ BHND_IO_METHODS(uint8_t, 1); BHND_IO_METHODS(uint16_t, 2); BHND_IO_METHODS(uint32_t, 4); static void bhnd_barrier(device_t dev, device_t child, struct bhnd_resource *r, bus_size_t offset, bus_size_t length, int flags) { BHND_BUS_BARRIER(device_get_parent(dev), child, r, offset, length, flags); } static device_method_t bhnd_methods[] = { /* Device interface */ \ DEVMETHOD(device_attach, bhnd_generic_attach), DEVMETHOD(device_detach, bhnd_generic_detach), DEVMETHOD(device_shutdown, bhnd_generic_shutdown), DEVMETHOD(device_suspend, bhnd_generic_suspend), DEVMETHOD(device_resume, bhnd_generic_resume), /* Bus interface */ DEVMETHOD(bus_new_pass, bhnd_new_pass), DEVMETHOD(bus_add_child, bhnd_generic_add_child), DEVMETHOD(bus_child_deleted, bhnd_generic_child_deleted), DEVMETHOD(bus_probe_nomatch, bhnd_generic_probe_nomatch), DEVMETHOD(bus_print_child, bhnd_generic_print_child), DEVMETHOD(bus_child_pnpinfo_str, bhnd_child_pnpinfo_str), DEVMETHOD(bus_child_location_str, bhnd_child_location_str), DEVMETHOD(bus_suspend_child, bhnd_generic_suspend_child), DEVMETHOD(bus_resume_child, bhnd_generic_resume_child), DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), DEVMETHOD(bus_config_intr, bus_generic_config_intr), DEVMETHOD(bus_bind_intr, bus_generic_bind_intr), DEVMETHOD(bus_describe_intr, bus_generic_describe_intr), DEVMETHOD(bus_get_dma_tag, bus_generic_get_dma_tag), /* BHND interface */ DEVMETHOD(bhnd_bus_get_chipid, bhnd_bus_generic_get_chipid), + DEVMETHOD(bhnd_bus_is_hw_disabled, bhnd_bus_generic_is_hw_disabled), + DEVMETHOD(bhnd_bus_read_board_info, bhnd_bus_generic_read_board_info), + DEVMETHOD(bhnd_bus_get_probe_order, bhnd_generic_get_probe_order), + + DEVMETHOD(bhnd_bus_alloc_pmu, bhnd_generic_alloc_pmu), + DEVMETHOD(bhnd_bus_release_pmu, bhnd_generic_release_pmu), + DEVMETHOD(bhnd_bus_request_clock, bhnd_generic_request_clock), + DEVMETHOD(bhnd_bus_enable_clocks, bhnd_generic_enable_clocks), + DEVMETHOD(bhnd_bus_request_ext_rsrc, bhnd_generic_request_ext_rsrc), + DEVMETHOD(bhnd_bus_release_ext_rsrc, bhnd_generic_release_ext_rsrc), + + DEVMETHOD(bhnd_bus_child_added, bhnd_generic_child_added), DEVMETHOD(bhnd_bus_is_region_valid, bhnd_generic_is_region_valid), - DEVMETHOD(bhnd_bus_is_hw_disabled, bhnd_bus_generic_is_hw_disabled), DEVMETHOD(bhnd_bus_get_nvram_var, bhnd_generic_get_nvram_var), /* BHND interface (bus I/O) */ DEVMETHOD(bhnd_bus_read_1, bhnd_read_1), DEVMETHOD(bhnd_bus_read_2, bhnd_read_2), DEVMETHOD(bhnd_bus_read_4, bhnd_read_4), DEVMETHOD(bhnd_bus_write_1, bhnd_write_1), DEVMETHOD(bhnd_bus_write_2, bhnd_write_2), DEVMETHOD(bhnd_bus_write_4, bhnd_write_4), DEVMETHOD(bhnd_bus_read_stream_1, bhnd_read_stream_1), DEVMETHOD(bhnd_bus_read_stream_2, bhnd_read_stream_2), DEVMETHOD(bhnd_bus_read_stream_4, bhnd_read_stream_4), DEVMETHOD(bhnd_bus_write_stream_1, bhnd_write_stream_1), DEVMETHOD(bhnd_bus_write_stream_2, bhnd_write_stream_2), DEVMETHOD(bhnd_bus_write_stream_4, bhnd_write_stream_4), DEVMETHOD(bhnd_bus_read_multi_1, bhnd_read_multi_1), DEVMETHOD(bhnd_bus_read_multi_2, bhnd_read_multi_2), DEVMETHOD(bhnd_bus_read_multi_4, bhnd_read_multi_4), DEVMETHOD(bhnd_bus_write_multi_1, bhnd_write_multi_1), DEVMETHOD(bhnd_bus_write_multi_2, bhnd_write_multi_2), DEVMETHOD(bhnd_bus_write_multi_4, bhnd_write_multi_4), DEVMETHOD(bhnd_bus_read_multi_stream_1, bhnd_read_multi_stream_1), DEVMETHOD(bhnd_bus_read_multi_stream_2, bhnd_read_multi_stream_2), DEVMETHOD(bhnd_bus_read_multi_stream_4, bhnd_read_multi_stream_4), DEVMETHOD(bhnd_bus_write_multi_stream_1,bhnd_write_multi_stream_1), DEVMETHOD(bhnd_bus_write_multi_stream_2,bhnd_write_multi_stream_2), DEVMETHOD(bhnd_bus_write_multi_stream_4,bhnd_write_multi_stream_4), DEVMETHOD(bhnd_bus_set_multi_1, bhnd_set_multi_1), DEVMETHOD(bhnd_bus_set_multi_2, bhnd_set_multi_2), DEVMETHOD(bhnd_bus_set_multi_4, bhnd_set_multi_4), DEVMETHOD(bhnd_bus_set_region_1, bhnd_set_region_1), DEVMETHOD(bhnd_bus_set_region_2, bhnd_set_region_2), DEVMETHOD(bhnd_bus_set_region_4, bhnd_set_region_4), DEVMETHOD(bhnd_bus_read_region_1, bhnd_read_region_1), DEVMETHOD(bhnd_bus_read_region_2, bhnd_read_region_2), DEVMETHOD(bhnd_bus_read_region_4, bhnd_read_region_4), DEVMETHOD(bhnd_bus_write_region_1, bhnd_write_region_1), DEVMETHOD(bhnd_bus_write_region_2, bhnd_write_region_2), DEVMETHOD(bhnd_bus_write_region_4, bhnd_write_region_4), DEVMETHOD(bhnd_bus_read_region_stream_1,bhnd_read_region_stream_1), DEVMETHOD(bhnd_bus_read_region_stream_2,bhnd_read_region_stream_2), DEVMETHOD(bhnd_bus_read_region_stream_4,bhnd_read_region_stream_4), DEVMETHOD(bhnd_bus_write_region_stream_1, bhnd_write_region_stream_1), DEVMETHOD(bhnd_bus_write_region_stream_2, bhnd_write_region_stream_2), DEVMETHOD(bhnd_bus_write_region_stream_4, bhnd_write_region_stream_4), DEVMETHOD(bhnd_bus_barrier, bhnd_barrier), DEVMETHOD_END }; devclass_t bhnd_devclass; /**< bhnd bus. */ devclass_t bhnd_hostb_devclass; /**< bhnd bus host bridge. */ devclass_t bhnd_nvram_devclass; /**< bhnd NVRAM device */ DEFINE_CLASS_0(bhnd, bhnd_driver, bhnd_methods, sizeof(struct bhnd_softc)); MODULE_VERSION(bhnd, 1); Index: head/sys/dev/bhnd/bhnd.h =================================================================== --- head/sys/dev/bhnd/bhnd.h (revision 304869) +++ head/sys/dev/bhnd/bhnd.h (revision 304870) @@ -1,965 +1,1191 @@ /*- * Copyright (c) 2015 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. * * $FreeBSD$ */ #ifndef _BHND_BHND_H_ #define _BHND_BHND_H_ #include #include #include #include "bhnd_ids.h" #include "bhnd_types.h" #include "bhnd_debug.h" #include "bhnd_bus_if.h" #include "bhnd_match.h" #include "nvram/bhnd_nvram.h" extern devclass_t bhnd_devclass; extern devclass_t bhnd_hostb_devclass; extern devclass_t bhnd_nvram_devclass; /** * bhnd child instance variables */ enum bhnd_device_vars { BHND_IVAR_VENDOR, /**< Designer's JEP-106 manufacturer ID. */ BHND_IVAR_DEVICE, /**< Part number */ BHND_IVAR_HWREV, /**< Core revision */ BHND_IVAR_DEVICE_CLASS, /**< Core class (@sa bhnd_devclass_t) */ BHND_IVAR_VENDOR_NAME, /**< Core vendor name */ BHND_IVAR_DEVICE_NAME, /**< Core name */ BHND_IVAR_CORE_INDEX, /**< Bus-assigned core number */ BHND_IVAR_CORE_UNIT, /**< Bus-assigned core unit number, assigned sequentially (starting at 0) for each vendor/device pair. */ }; /** * bhnd device probe priority bands. */ enum { BHND_PROBE_ROOT = 0, /**< Nexus or host bridge */ BHND_PROBE_BUS = 1000, /**< Busses and bridges */ BHND_PROBE_CPU = 2000, /**< CPU devices */ BHND_PROBE_INTERRUPT = 3000, /**< Interrupt controllers. */ BHND_PROBE_TIMER = 4000, /**< Timers and clocks. */ BHND_PROBE_RESOURCE = 5000, /**< Resource discovery (including NVRAM/SPROM) */ BHND_PROBE_DEFAULT = 6000, /**< Default device priority */ }; /** * Constants defining fine grained ordering within a BHND_PROBE_* priority band. * * Example: * @code * BHND_PROBE_BUS + BHND_PROBE_ORDER_FIRST * @endcode */ enum { BHND_PROBE_ORDER_FIRST = 0, BHND_PROBE_ORDER_EARLY = 25, BHND_PROBE_ORDER_MIDDLE = 50, BHND_PROBE_ORDER_LATE = 75, BHND_PROBE_ORDER_LAST = 100 }; /* * Simplified accessors for bhnd device ivars */ #define BHND_ACCESSOR(var, ivar, type) \ __BUS_ACCESSOR(bhnd, var, BHND, ivar, type) BHND_ACCESSOR(vendor, VENDOR, uint16_t); BHND_ACCESSOR(device, DEVICE, uint16_t); BHND_ACCESSOR(hwrev, HWREV, uint8_t); BHND_ACCESSOR(class, DEVICE_CLASS, bhnd_devclass_t); BHND_ACCESSOR(vendor_name, VENDOR_NAME, const char *); BHND_ACCESSOR(device_name, DEVICE_NAME, const char *); BHND_ACCESSOR(core_index, CORE_INDEX, u_int); BHND_ACCESSOR(core_unit, CORE_UNIT, int); #undef BHND_ACCESSOR /** * A bhnd(4) board descriptor. */ struct bhnd_board_info { uint16_t board_vendor; /**< PCI-SIG vendor ID (even on non-PCI * devices). * * On PCI devices, this will generally * be the subsystem vendor ID, but the * value may be overridden in device * NVRAM. */ uint16_t board_type; /**< Board type (See BHND_BOARD_*) * * On PCI devices, this will generally * be the subsystem device ID, but the * value may be overridden in device * NVRAM. */ uint16_t board_rev; /**< Board revision. */ uint8_t board_srom_rev; /**< Board SROM format revision */ uint32_t board_flags; /**< Board flags (see BHND_BFL_*) */ uint32_t board_flags2; /**< Board flags 2 (see BHND_BFL2_*) */ uint32_t board_flags3; /**< Board flags 3 (see BHND_BFL3_*) */ }; /** * Chip Identification * * This is read from the ChipCommon ID register; on earlier bhnd(4) devices * where ChipCommon is unavailable, known values must be supplied. */ struct bhnd_chipid { uint16_t chip_id; /**< chip id (BHND_CHIPID_*) */ uint8_t chip_rev; /**< chip revision */ uint8_t chip_pkg; /**< chip package (BHND_PKGID_*) */ uint8_t chip_type; /**< chip type (BHND_CHIPTYPE_*) */ bhnd_addr_t enum_addr; /**< chip_type-specific enumeration * address; either the siba(4) base * core register block, or the bcma(4) * EROM core address. */ uint8_t ncores; /**< number of cores, if known. 0 if * not available. */ }; /** * A bhnd(4) core descriptor. */ struct bhnd_core_info { uint16_t vendor; /**< JEP-106 vendor (BHND_MFGID_*) */ uint16_t device; /**< device */ uint16_t hwrev; /**< hardware revision */ u_int core_idx; /**< bus-assigned core index */ int unit; /**< bus-assigned core unit */ }; /** * A bhnd(4) bus resource. * * This provides an abstract interface to per-core resources that may require * bus-level remapping of address windows prior to access. */ struct bhnd_resource { struct resource *res; /**< the system resource. */ bool direct; /**< false if the resource requires * bus window remapping before it * is MMIO accessible. */ }; /** * Device quirk table descriptor. */ struct bhnd_device_quirk { struct bhnd_device_match desc; /**< device match descriptor */ uint32_t quirks; /**< quirk flags */ }; #define BHND_CORE_QUIRK(_rev, _flags) \ {{ BHND_MATCH_CORE_REV(_rev) }, (_flags) } #define BHND_CHIP_QUIRK(_chip, _rev, _flags) \ {{ BHND_CHIP_IR(BCM ## _chip, _rev) }, (_flags) } #define BHND_PKG_QUIRK(_chip, _pkg, _flags) \ {{ BHND_CHIP_IP(BCM ## _chip, BCM ## _chip ## _pkg) }, (_flags) } #define BHND_BOARD_QUIRK(_board, _flags) \ {{ BHND_MATCH_BOARD_TYPE(_board) }, \ (_flags) } #define BHND_DEVICE_QUIRK_END { { BHND_MATCH_ANY }, 0 } #define BHND_DEVICE_QUIRK_IS_END(_q) \ (((_q)->desc.m.match_flags == 0) && (_q)->quirks == 0) enum { BHND_DF_ANY = 0, BHND_DF_HOSTB = (1<<0), /**< core is serving as the bus' host * bridge. implies BHND_DF_ADAPTER */ BHND_DF_SOC = (1<<1), /**< core is attached to a native bus (BHND_ATTACH_NATIVE) */ BHND_DF_ADAPTER = (1<<2), /**< core is attached to a bridged * adapter (BHND_ATTACH_ADAPTER) */ }; /** Device probe table descriptor */ struct bhnd_device { const struct bhnd_device_match core; /**< core match descriptor */ const char *desc; /**< device description, or NULL. */ const struct bhnd_device_quirk *quirks_table; /**< quirks table for this device, or NULL */ uint32_t device_flags; /**< required BHND_DF_* flags */ }; #define _BHND_DEVICE(_vendor, _device, _desc, _quirks, \ _flags, ...) \ { { BHND_MATCH_CORE(BHND_MFGID_ ## _vendor, \ BHND_COREID_ ## _device) }, _desc, _quirks, \ _flags } #define BHND_DEVICE(_vendor, _device, _desc, _quirks, ...) \ _BHND_DEVICE(_vendor, _device, _desc, _quirks, \ ## __VA_ARGS__, 0) #define BHND_DEVICE_END { { BHND_MATCH_ANY }, NULL, NULL, 0 } #define BHND_DEVICE_IS_END(_d) \ (BHND_MATCH_IS_ANY(&(_d)->core) && (_d)->desc == NULL) const char *bhnd_vendor_name(uint16_t vendor); const char *bhnd_port_type_name(bhnd_port_type port_type); const char *bhnd_nvram_src_name(bhnd_nvram_src nvram_src); const char *bhnd_find_core_name(uint16_t vendor, uint16_t device); bhnd_devclass_t bhnd_find_core_class(uint16_t vendor, uint16_t device); const char *bhnd_core_name(const struct bhnd_core_info *ci); bhnd_devclass_t bhnd_core_class(const struct bhnd_core_info *ci); device_t bhnd_match_child(device_t dev, const struct bhnd_core_match *desc); device_t bhnd_find_child(device_t dev, bhnd_devclass_t class, int unit); device_t bhnd_find_bridge_root(device_t dev, devclass_t bus_class); const struct bhnd_core_info *bhnd_match_core( const struct bhnd_core_info *cores, u_int num_cores, const struct bhnd_core_match *desc); const struct bhnd_core_info *bhnd_find_core( const struct bhnd_core_info *cores, u_int num_cores, bhnd_devclass_t class); bool bhnd_core_matches( const struct bhnd_core_info *core, const struct bhnd_core_match *desc); bool bhnd_chip_matches( const struct bhnd_chipid *chipid, const struct bhnd_chip_match *desc); bool bhnd_board_matches( const struct bhnd_board_info *info, const struct bhnd_board_match *desc); bool bhnd_hwrev_matches(uint16_t hwrev, const struct bhnd_hwrev_match *desc); bool bhnd_device_matches(device_t dev, const struct bhnd_device_match *desc); const struct bhnd_device *bhnd_device_lookup(device_t dev, const struct bhnd_device *table, size_t entry_size); uint32_t bhnd_device_quirks(device_t dev, const struct bhnd_device *table, size_t entry_size); struct bhnd_core_info bhnd_get_core_info(device_t dev); int bhnd_alloc_resources(device_t dev, struct resource_spec *rs, struct bhnd_resource **res); void bhnd_release_resources(device_t dev, const struct resource_spec *rs, struct bhnd_resource **res); struct bhnd_chipid bhnd_parse_chipid(uint32_t idreg, bhnd_addr_t enum_addr); int bhnd_read_chipid(device_t dev, struct resource_spec *rs, bus_size_t chipc_offset, struct bhnd_chipid *result); void bhnd_set_custom_core_desc(device_t dev, const char *name); void bhnd_set_default_core_desc(device_t dev); int bhnd_nvram_getvar_str(device_t dev, const char *name, char *buf, size_t len, size_t *rlen); int bhnd_nvram_getvar_uint(device_t dev, const char *name, void *value, int width); int bhnd_nvram_getvar_uint8(device_t dev, const char *name, uint8_t *value); int bhnd_nvram_getvar_uint16(device_t dev, const char *name, uint16_t *value); int bhnd_nvram_getvar_uint32(device_t dev, const char *name, uint32_t *value); int bhnd_nvram_getvar_int(device_t dev, const char *name, void *value, int width); int bhnd_nvram_getvar_int8(device_t dev, const char *name, int8_t *value); int bhnd_nvram_getvar_int16(device_t dev, const char *name, int16_t *value); int bhnd_nvram_getvar_int32(device_t dev, const char *name, int32_t *value); int bhnd_nvram_getvar_array(device_t dev, const char *name, void *buf, size_t count, bhnd_nvram_type type); bool bhnd_bus_generic_is_hw_disabled(device_t dev, device_t child); bool bhnd_bus_generic_is_region_valid(device_t dev, device_t child, bhnd_port_type type, u_int port, u_int region); int bhnd_bus_generic_get_nvram_var(device_t dev, device_t child, const char *name, void *buf, size_t *size, bhnd_nvram_type type); const struct bhnd_chipid *bhnd_bus_generic_get_chipid(device_t dev, device_t child); int bhnd_bus_generic_read_board_info(device_t dev, device_t child, struct bhnd_board_info *info); struct bhnd_resource *bhnd_bus_generic_alloc_resource (device_t dev, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags); int bhnd_bus_generic_release_resource (device_t dev, device_t child, int type, int rid, struct bhnd_resource *r); int bhnd_bus_generic_activate_resource (device_t dev, device_t child, int type, int rid, struct bhnd_resource *r); int bhnd_bus_generic_deactivate_resource (device_t dev, device_t child, int type, int rid, struct bhnd_resource *r); bhnd_attach_type bhnd_bus_generic_get_attach_type(device_t dev, device_t child); /** * Return the active host bridge core for the bhnd bus, if any, or NULL if * not found. * * @param dev A bhnd bus device. */ static inline device_t bhnd_find_hostb_device(device_t dev) { return (BHND_BUS_FIND_HOSTB_DEVICE(dev)); } /** * Return true if the hardware components required by @p dev are known to be * unpopulated or otherwise unusable. * * In some cases, enumerated devices may have pins that are left floating, or * the hardware may otherwise be non-functional; this method allows a parent * device to explicitly specify if a successfully enumerated @p dev should * be disabled. * * @param dev A bhnd bus child device. */ static inline bool bhnd_is_hw_disabled(device_t dev) { return (BHND_BUS_IS_HW_DISABLED(device_get_parent(dev), dev)); } /** * Return the BHND chip identification info for the bhnd bus. * * @param dev A bhnd bus child device. */ static inline const struct bhnd_chipid * bhnd_get_chipid(device_t dev) { return (BHND_BUS_GET_CHIPID(device_get_parent(dev), dev)); }; /** + * If supported by the chipset, return the clock source for the given clock. + * + * This function is only supported on early PWRCTL-equipped chipsets + * that expose clock management via their host bridge interface. Currently, + * this includes PCI (not PCIe) devices, with ChipCommon core revisions 0-9. + * + * @param dev A bhnd bus child device. + * @param clock The clock for which a clock source will be returned. + * + * @retval bhnd_clksrc The clock source for @p clock. + * @retval BHND_CLKSRC_UNKNOWN If @p clock is unsupported, or its + * clock source is not known to the bus. + */ +static inline bhnd_clksrc +bhnd_pwrctl_get_clksrc(device_t dev, bhnd_clock clock) +{ + return (BHND_BUS_PWRCTL_GET_CLKSRC(device_get_parent(dev), dev, clock)); +} + +/** + * If supported by the chipset, gate @p clock + * + * This function is only supported on early PWRCTL-equipped chipsets + * that expose clock management via their host bridge interface. Currently, + * this includes PCI (not PCIe) devices, with ChipCommon core revisions 0-9. + * + * @param dev A bhnd bus child device. + * @param clock The clock to be disabled. + * + * @retval 0 success + * @retval ENODEV If bus-level clock source management is not supported. + * @retval ENXIO If bus-level management of @p clock is not supported. + */ +static inline int +bhnd_pwrctl_gate_clock(device_t dev, bhnd_clock clock) +{ + return (BHND_BUS_PWRCTL_GATE_CLOCK(device_get_parent(dev), dev, clock)); +} + +/** + * If supported by the chipset, ungate @p clock + * + * This function is only supported on early PWRCTL-equipped chipsets + * that expose clock management via their host bridge interface. Currently, + * this includes PCI (not PCIe) devices, with ChipCommon core revisions 0-9. + * + * @param dev A bhnd bus child device. + * @param clock The clock to be enabled. + * + * @retval 0 success + * @retval ENODEV If bus-level clock source management is not supported. + * @retval ENXIO If bus-level management of @p clock is not supported. + */ +static inline int +bhnd_pwrctl_ungate_clock(device_t dev, bhnd_clock clock) +{ + return (BHND_BUS_PWRCTL_UNGATE_CLOCK(device_get_parent(dev), dev, + clock)); +} + +/** * Return the BHND attachment type of the parent bhnd bus. * * @param dev A bhnd bus child device. * * @retval BHND_ATTACH_ADAPTER if the bus is resident on a bridged adapter, * such as a WiFi chipset. * @retval BHND_ATTACH_NATIVE if the bus provides hardware services (clock, * CPU, etc) to a directly attached native host. */ static inline bhnd_attach_type bhnd_get_attach_type (device_t dev) { return (BHND_BUS_GET_ATTACH_TYPE(device_get_parent(dev), dev)); } /** * Attempt to read the BHND board identification from the bhnd bus. * * This relies on NVRAM access, and will fail if a valid NVRAM device cannot * be found, or is not yet attached. * * @param dev The parent of @p child. * @param child The bhnd device requesting board info. * @param[out] info On success, will be populated with the bhnd(4) device's * board information. * * @retval 0 success * @retval ENODEV No valid NVRAM source could be found. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ static inline int bhnd_read_board_info(device_t dev, struct bhnd_board_info *info) { return (BHND_BUS_READ_BOARD_INFO(device_get_parent(dev), dev, info)); +} + +/** + * Allocate and enable per-core PMU request handling for @p child. + * + * The region containing the core's PMU register block (if any) must be + * allocated via bus_alloc_resource(9) (or bhnd_alloc_resource) before + * calling bhnd_alloc_pmu(), and must not be released until after + * calling bhnd_release_pmu(). + * + * @param dev The parent of @p child. + * @param child The requesting bhnd device. + * + * @retval 0 success + * @retval non-zero If allocating PMU request state otherwise fails, a + * regular unix error code will be returned. + */ +static inline int +bhnd_alloc_pmu(device_t dev) +{ + return (BHND_BUS_ALLOC_PMU(device_get_parent(dev), dev)); +} + +/** + * Release any per-core PMU resources allocated for @p child. Any outstanding + * PMU requests are are discarded. + * + * @param dev The parent of @p child. + * @param child The requesting bhnd device. + * + * @retval 0 success + * @retval non-zero If releasing PMU request state otherwise fails, a + * regular unix error code will be returned, and + * the core state will be left unmodified. + */ +static inline int +bhnd_release_pmu(device_t dev) +{ + return (BHND_BUS_RELEASE_PMU(device_get_parent(dev), dev)); +} + +/** + * Request that @p clock (or faster) be routed to @p dev. + * + * A driver must ask the bhnd bus to allocate clock request state + * via bhnd_alloc_pmu() before it can request clock resources. + * + * Request multiplexing is managed by the bus. + * + * @param dev The bhnd(4) device to which @p clock should be routed. + * @param clock The requested clock source. + * + * @retval 0 success + * @retval ENODEV If an unsupported clock was requested. + * @retval ENXIO If the PMU has not been initialized or is otherwise unvailable. + */ +static inline int +bhnd_request_clock(device_t dev, bhnd_clock clock) +{ + return (BHND_BUS_REQUEST_CLOCK(device_get_parent(dev), dev, clock)); +} + +/** + * Request that @p clocks be powered on behalf of @p dev. + * + * This will power any clock sources (e.g. XTAL, PLL, etc) required for + * @p clocks and wait until they are ready, discarding any previous + * requests by @p dev. + * + * Request multiplexing is managed by the bus. + * + * A driver must ask the bhnd bus to allocate clock request state + * via bhnd_alloc_pmu() before it can request clock resources. + * + * @param dev The requesting bhnd(4) device. + * @param clocks The clock(s) to be enabled. + * + * @retval 0 success + * @retval ENODEV If an unsupported clock was requested. + * @retval ENXIO If the PMU has not been initialized or is otherwise unvailable. + */ +static inline int +bhnd_enable_clocks(device_t dev, uint32_t clocks) +{ + return (BHND_BUS_ENABLE_CLOCKS(device_get_parent(dev), dev, clocks)); +} + +/** + * Power up an external PMU-managed resource assigned to @p dev. + * + * A driver must ask the bhnd bus to allocate PMU request state + * via bhnd_alloc_pmu() before it can request PMU resources. + * + * @param dev The requesting bhnd(4) device. + * @param rsrc The core-specific external resource identifier. + * + * @retval 0 success + * @retval ENODEV If the PMU does not support @p rsrc. + * @retval ENXIO If the PMU has not been initialized or is otherwise unvailable. + */ +static inline int +bhnd_request_ext_rsrc(device_t dev, u_int rsrc) +{ + return (BHND_BUS_REQUEST_EXT_RSRC(device_get_parent(dev), dev, rsrc)); +} + +/** + * Power down an external PMU-managed resource assigned to @p dev. + * + * A driver must ask the bhnd bus to allocate PMU request state + * via bhnd_alloc_pmu() before it can request PMU resources. + * + * @param dev The requesting bhnd(4) device. + * @param rsrc The core-specific external resource identifier. + * + * @retval 0 success + * @retval ENODEV If the PMU does not support @p rsrc. + * @retval ENXIO If the PMU has not been initialized or is otherwise unvailable. + */ +static inline int +bhnd_release_ext_rsrc(device_t dev, u_int rsrc) +{ + return (BHND_BUS_RELEASE_EXT_RSRC(device_get_parent(dev), dev, rsrc)); +} + + +/** + * Read @p width bytes at @p offset from the bus-specific agent/config + * space of @p dev. + * + * @param dev The bhnd device for which @p offset should be read. + * @param offset The offset to be read. + * @param width The size of the access. Must be 1, 2 or 4 bytes. + * + * The exact behavior of this method is bus-specific. In the case of + * bcma(4), this method provides access to the first agent port of @p child. + * + * @note Device drivers should only use this API for functionality + * that is not available via another bhnd(4) function. + */ +static inline uint32_t +bhnd_read_config(device_t dev, bus_size_t offset, u_int width) +{ + return (BHND_BUS_READ_CONFIG(device_get_parent(dev), dev, offset, + width)); +} + +/** + * Read @p width bytes at @p offset from the bus-specific agent/config + * space of @p dev. + * + * @param dev The bhnd device for which @p offset should be read. + * @param offset The offset to be written. + * @param width The size of the access. Must be 1, 2 or 4 bytes. + * + * The exact behavior of this method is bus-specific. In the case of + * bcma(4), this method provides access to the first agent port of @p child. + * + * @note Device drivers should only use this API for functionality + * that is not available via another bhnd(4) function. + */ +static inline void +bhnd_write_config(device_t dev, bus_size_t offset, uint32_t val, u_int width) +{ + BHND_BUS_WRITE_CONFIG(device_get_parent(dev), dev, offset, val, width); } /** * Read an NVRAM variable, coerced to the requested @p type. * * @param dev A bhnd bus child device. * @param name The NVRAM variable name. * @param[out] buf A buffer large enough to hold @p len bytes. On * success, the requested value will be written to * this buffer. This argment may be NULL if * the value is not desired. * @param[in,out] len The maximum capacity of @p buf. On success, * will be set to the actual size of the requested * value. * @param type The desired data representation to be written * to @p buf. * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENODEV No valid NVRAM source could be found. * @retval ENOMEM If a buffer of @p size is too small to hold the * requested value. * @retval EOPNOTSUPP If the value cannot be coerced to @p type. * @retval ERANGE If value coercion would overflow @p type. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ static inline int bhnd_nvram_getvar(device_t dev, const char *name, void *buf, size_t *len, bhnd_nvram_type type) { return (BHND_BUS_GET_NVRAM_VAR(device_get_parent(dev), dev, name, buf, len, type)); } /** * Allocate a resource from a device's parent bhnd(4) bus. * * @param dev The device requesting resource ownership. * @param type The type of resource to allocate. This may be any type supported * by the standard bus APIs. * @param rid The bus-specific handle identifying the resource being allocated. * @param start The start address of the resource. * @param end The end address of the resource. * @param count The size of the resource. * @param flags The flags for the resource to be allocated. These may be any * values supported by the standard bus APIs. * * To request the resource's default addresses, pass @p start and * @p end values of @c 0 and @c ~0, respectively, and * a @p count of @c 1. * * @retval NULL The resource could not be allocated. * @retval resource The allocated resource. */ static inline struct bhnd_resource * bhnd_alloc_resource(device_t dev, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) { return BHND_BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, type, rid, start, end, count, flags); } /** * Allocate a resource from a device's parent bhnd(4) bus, using the * resource's default start, end, and count values. * * @param dev The device requesting resource ownership. * @param type The type of resource to allocate. This may be any type supported * by the standard bus APIs. * @param rid The bus-specific handle identifying the resource being allocated. * @param flags The flags for the resource to be allocated. These may be any * values supported by the standard bus APIs. * * @retval NULL The resource could not be allocated. * @retval resource The allocated resource. */ static inline struct bhnd_resource * bhnd_alloc_resource_any(device_t dev, int type, int *rid, u_int flags) { return bhnd_alloc_resource(dev, type, rid, 0, ~0, 1, flags); } /** * Activate a previously allocated bhnd resource. * * @param dev The device holding ownership of the allocated resource. * @param type The type of the resource. * @param rid The bus-specific handle identifying the resource. * @param r A pointer to the resource returned by bhnd_alloc_resource or * BHND_BUS_ALLOC_RESOURCE. * * @retval 0 success * @retval non-zero an error occurred while activating the resource. */ static inline int bhnd_activate_resource(device_t dev, int type, int rid, struct bhnd_resource *r) { return BHND_BUS_ACTIVATE_RESOURCE(device_get_parent(dev), dev, type, rid, r); } /** * Deactivate a previously activated bhnd resource. * * @param dev The device holding ownership of the activated resource. * @param type The type of the resource. * @param rid The bus-specific handle identifying the resource. * @param r A pointer to the resource returned by bhnd_alloc_resource or * BHND_BUS_ALLOC_RESOURCE. * * @retval 0 success * @retval non-zero an error occurred while activating the resource. */ static inline int bhnd_deactivate_resource(device_t dev, int type, int rid, struct bhnd_resource *r) { return BHND_BUS_DEACTIVATE_RESOURCE(device_get_parent(dev), dev, type, rid, r); } /** * Free a resource allocated by bhnd_alloc_resource(). * * @param dev The device holding ownership of the resource. * @param type The type of the resource. * @param rid The bus-specific handle identifying the resource. * @param r A pointer to the resource returned by bhnd_alloc_resource or * BHND_ALLOC_RESOURCE. * * @retval 0 success * @retval non-zero an error occurred while activating the resource. */ static inline int bhnd_release_resource(device_t dev, int type, int rid, struct bhnd_resource *r) { return BHND_BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, type, rid, r); } /** * Return true if @p region_num is a valid region on @p port_num of * @p type attached to @p dev. * * @param dev A bhnd bus child device. * @param type The port type being queried. * @param port_num The port number being queried. * @param region_num The region number being queried. */ static inline bool bhnd_is_region_valid(device_t dev, bhnd_port_type type, u_int port_num, u_int region_num) { return (BHND_BUS_IS_REGION_VALID(device_get_parent(dev), dev, type, port_num, region_num)); } /** * Return the number of ports of type @p type attached to @p def. * * @param dev A bhnd bus child device. * @param type The port type being queried. */ static inline u_int bhnd_get_port_count(device_t dev, bhnd_port_type type) { return (BHND_BUS_GET_PORT_COUNT(device_get_parent(dev), dev, type)); } /** * Return the number of memory regions mapped to @p child @p port of * type @p type. * * @param dev A bhnd bus child device. * @param port The port number being queried. * @param type The port type being queried. */ static inline u_int bhnd_get_region_count(device_t dev, bhnd_port_type type, u_int port) { return (BHND_BUS_GET_REGION_COUNT(device_get_parent(dev), dev, type, port)); } /** * Return the resource-ID for a memory region on the given device port. * * @param dev A bhnd bus child device. * @param type The port type. * @param port The port identifier. * @param region The identifier of the memory region on @p port. * * @retval int The RID for the given @p port and @p region on @p device. * @retval -1 No such port/region found. */ static inline int bhnd_get_port_rid(device_t dev, bhnd_port_type type, u_int port, u_int region) { return BHND_BUS_GET_PORT_RID(device_get_parent(dev), dev, type, port, region); } /** * Decode a port / region pair on @p dev defined by @p rid. * * @param dev A bhnd bus child device. * @param type The resource type. * @param rid The resource identifier. * @param[out] port_type The decoded port type. * @param[out] port The decoded port identifier. * @param[out] region The decoded region identifier. * * @retval 0 success * @retval non-zero No matching port/region found. */ static inline int bhnd_decode_port_rid(device_t dev, int type, int rid, bhnd_port_type *port_type, u_int *port, u_int *region) { return BHND_BUS_DECODE_PORT_RID(device_get_parent(dev), dev, type, rid, port_type, port, region); } /** * Get the address and size of @p region on @p port. * * @param dev A bhnd bus child device. * @param port_type The port type. * @param port The port identifier. * @param region The identifier of the memory region on @p port. * @param[out] region_addr The region's base address. * @param[out] region_size The region's size. * * @retval 0 success * @retval non-zero No matching port/region found. */ static inline int bhnd_get_region_addr(device_t dev, bhnd_port_type port_type, u_int port, u_int region, bhnd_addr_t *region_addr, bhnd_size_t *region_size) { return BHND_BUS_GET_REGION_ADDR(device_get_parent(dev), dev, port_type, port, region, region_addr, region_size); } /* * bhnd bus-level equivalents of the bus_(read|write|set|barrier|...) * macros (compatible with bhnd_resource). * * Generated with bhnd/tools/bus_macro.sh */ #define bhnd_bus_barrier(r, o, l, f) \ ((r)->direct) ? \ bus_barrier((r)->res, (o), (l), (f)) : \ BHND_BUS_BARRIER( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (l), (f)) #define bhnd_bus_read_1(r, o) \ ((r)->direct) ? \ bus_read_1((r)->res, (o)) : \ BHND_BUS_READ_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o)) #define bhnd_bus_read_multi_1(r, o, d, c) \ ((r)->direct) ? \ bus_read_multi_1((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_MULTI_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_read_region_1(r, o, d, c) \ ((r)->direct) ? \ bus_read_region_1((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_REGION_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_1(r, o, v) \ ((r)->direct) ? \ bus_write_1((r)->res, (o), (v)) : \ BHND_BUS_WRITE_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v)) #define bhnd_bus_write_multi_1(r, o, d, c) \ ((r)->direct) ? \ bus_write_multi_1((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_MULTI_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_region_1(r, o, d, c) \ ((r)->direct) ? \ bus_write_region_1((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_REGION_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_read_stream_1(r, o) \ ((r)->direct) ? \ bus_read_stream_1((r)->res, (o)) : \ BHND_BUS_READ_STREAM_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o)) #define bhnd_bus_read_multi_stream_1(r, o, d, c) \ ((r)->direct) ? \ bus_read_multi_stream_1((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_MULTI_STREAM_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_read_region_stream_1(r, o, d, c) \ ((r)->direct) ? \ bus_read_region_stream_1((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_REGION_STREAM_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_stream_1(r, o, v) \ ((r)->direct) ? \ bus_write_stream_1((r)->res, (o), (v)) : \ BHND_BUS_WRITE_STREAM_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v)) #define bhnd_bus_write_multi_stream_1(r, o, d, c) \ ((r)->direct) ? \ bus_write_multi_stream_1((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_MULTI_STREAM_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_region_stream_1(r, o, d, c) \ ((r)->direct) ? \ bus_write_region_stream_1((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_REGION_STREAM_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_set_multi_1(r, o, v, c) \ ((r)->direct) ? \ bus_set_multi_1((r)->res, (o), (v), (c)) : \ BHND_BUS_SET_MULTI_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v), (c)) #define bhnd_bus_set_region_1(r, o, v, c) \ ((r)->direct) ? \ bus_set_region_1((r)->res, (o), (v), (c)) : \ BHND_BUS_SET_REGION_1( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v), (c)) #define bhnd_bus_read_2(r, o) \ ((r)->direct) ? \ bus_read_2((r)->res, (o)) : \ BHND_BUS_READ_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o)) #define bhnd_bus_read_multi_2(r, o, d, c) \ ((r)->direct) ? \ bus_read_multi_2((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_MULTI_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_read_region_2(r, o, d, c) \ ((r)->direct) ? \ bus_read_region_2((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_REGION_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_2(r, o, v) \ ((r)->direct) ? \ bus_write_2((r)->res, (o), (v)) : \ BHND_BUS_WRITE_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v)) #define bhnd_bus_write_multi_2(r, o, d, c) \ ((r)->direct) ? \ bus_write_multi_2((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_MULTI_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_region_2(r, o, d, c) \ ((r)->direct) ? \ bus_write_region_2((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_REGION_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_read_stream_2(r, o) \ ((r)->direct) ? \ bus_read_stream_2((r)->res, (o)) : \ BHND_BUS_READ_STREAM_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o)) #define bhnd_bus_read_multi_stream_2(r, o, d, c) \ ((r)->direct) ? \ bus_read_multi_stream_2((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_MULTI_STREAM_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_read_region_stream_2(r, o, d, c) \ ((r)->direct) ? \ bus_read_region_stream_2((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_REGION_STREAM_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_stream_2(r, o, v) \ ((r)->direct) ? \ bus_write_stream_2((r)->res, (o), (v)) : \ BHND_BUS_WRITE_STREAM_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v)) #define bhnd_bus_write_multi_stream_2(r, o, d, c) \ ((r)->direct) ? \ bus_write_multi_stream_2((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_MULTI_STREAM_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_region_stream_2(r, o, d, c) \ ((r)->direct) ? \ bus_write_region_stream_2((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_REGION_STREAM_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_set_multi_2(r, o, v, c) \ ((r)->direct) ? \ bus_set_multi_2((r)->res, (o), (v), (c)) : \ BHND_BUS_SET_MULTI_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v), (c)) #define bhnd_bus_set_region_2(r, o, v, c) \ ((r)->direct) ? \ bus_set_region_2((r)->res, (o), (v), (c)) : \ BHND_BUS_SET_REGION_2( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v), (c)) #define bhnd_bus_read_4(r, o) \ ((r)->direct) ? \ bus_read_4((r)->res, (o)) : \ BHND_BUS_READ_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o)) #define bhnd_bus_read_multi_4(r, o, d, c) \ ((r)->direct) ? \ bus_read_multi_4((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_MULTI_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_read_region_4(r, o, d, c) \ ((r)->direct) ? \ bus_read_region_4((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_REGION_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_4(r, o, v) \ ((r)->direct) ? \ bus_write_4((r)->res, (o), (v)) : \ BHND_BUS_WRITE_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v)) #define bhnd_bus_write_multi_4(r, o, d, c) \ ((r)->direct) ? \ bus_write_multi_4((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_MULTI_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_region_4(r, o, d, c) \ ((r)->direct) ? \ bus_write_region_4((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_REGION_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_read_stream_4(r, o) \ ((r)->direct) ? \ bus_read_stream_4((r)->res, (o)) : \ BHND_BUS_READ_STREAM_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o)) #define bhnd_bus_read_multi_stream_4(r, o, d, c) \ ((r)->direct) ? \ bus_read_multi_stream_4((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_MULTI_STREAM_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_read_region_stream_4(r, o, d, c) \ ((r)->direct) ? \ bus_read_region_stream_4((r)->res, (o), (d), (c)) : \ BHND_BUS_READ_REGION_STREAM_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_stream_4(r, o, v) \ ((r)->direct) ? \ bus_write_stream_4((r)->res, (o), (v)) : \ BHND_BUS_WRITE_STREAM_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v)) #define bhnd_bus_write_multi_stream_4(r, o, d, c) \ ((r)->direct) ? \ bus_write_multi_stream_4((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_MULTI_STREAM_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_write_region_stream_4(r, o, d, c) \ ((r)->direct) ? \ bus_write_region_stream_4((r)->res, (o), (d), (c)) : \ BHND_BUS_WRITE_REGION_STREAM_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (d), (c)) #define bhnd_bus_set_multi_4(r, o, v, c) \ ((r)->direct) ? \ bus_set_multi_4((r)->res, (o), (v), (c)) : \ BHND_BUS_SET_MULTI_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v), (c)) #define bhnd_bus_set_region_4(r, o, v, c) \ ((r)->direct) ? \ bus_set_region_4((r)->res, (o), (v), (c)) : \ BHND_BUS_SET_REGION_4( \ device_get_parent(rman_get_device((r)->res)), \ rman_get_device((r)->res), (r), (o), (v), (c)) #endif /* _BHND_BHND_H_ */ Index: head/sys/dev/bhnd/bhnd_bus_if.m =================================================================== --- head/sys/dev/bhnd/bhnd_bus_if.m (revision 304869) +++ head/sys/dev/bhnd/bhnd_bus_if.m (revision 304870) @@ -1,939 +1,1237 @@ #- # Copyright (c) 2015 Landon Fuller # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions # are met: # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. # IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, # INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # $FreeBSD$ #include #include #include #include INTERFACE bhnd_bus; # # bhnd(4) bus interface # HEADER { /* forward declarations */ struct bhnd_board_info; struct bhnd_core_info; struct bhnd_chipid; struct bhnd_devinfo; struct bhnd_resource; } CODE { #include #include static struct bhnd_chipid * bhnd_bus_null_get_chipid(device_t dev, device_t child) { panic("bhnd_bus_get_chipid unimplemented"); } static bhnd_attach_type bhnd_bus_null_get_attach_type(device_t dev, device_t child) { panic("bhnd_bus_get_attach_type unimplemented"); } + + static bhnd_clksrc + bhnd_bus_null_pwrctl_get_clksrc(device_t dev, device_t child, + bhnd_clock clock) + { + return (BHND_CLKSRC_UNKNOWN); + } static int + bhnd_bus_null_pwrctl_gate_clock(device_t dev, device_t child, + bhnd_clock clock) + { + return (ENODEV); + } + + static int + bhnd_bus_null_pwrctl_ungate_clock(device_t dev, device_t child, + bhnd_clock clock) + { + return (ENODEV); + } + + static int bhnd_bus_null_read_board_info(device_t dev, device_t child, struct bhnd_board_info *info) { panic("bhnd_bus_read_boardinfo unimplemented"); } static void bhnd_bus_null_child_added(device_t dev, device_t child) { } + static int + bhnd_bus_null_alloc_pmu(device_t dev, device_t child) + { + panic("bhnd_bus_alloc_pmu unimplemented"); + } + + static int + bhnd_bus_null_release_pmu(device_t dev, device_t child) + { + panic("bhnd_bus_release_pmu unimplemented"); + } + + static int + bhnd_bus_null_request_clock(device_t dev, device_t child, + bhnd_clock clock) + { + panic("bhnd_bus_request_clock unimplemented"); + } + + static int + bhnd_bus_null_enable_clocks(device_t dev, device_t child, + uint32_t clocks) + { + panic("bhnd_bus_enable_clocks unimplemented"); + } + + static int + bhnd_bus_null_request_ext_rsrc(device_t dev, device_t child, + u_int rsrc) + { + panic("bhnd_bus_request_ext_rsrc unimplemented"); + } + + static int + bhnd_bus_null_release_ext_rsrc(device_t dev, device_t child, + u_int rsrc) + { + panic("bhnd_bus_release_ext_rsrc unimplemented"); + } + + static uint32_t + bhnd_bus_null_read_config(device_t dev, device_t child, + bus_size_t offset, u_int width) + { + panic("bhnd_bus_null_read_config unimplemented"); + } + + static void + bhnd_bus_null_write_config(device_t dev, device_t child, + bus_size_t offset, uint32_t val, u_int width) + { + panic("bhnd_bus_null_write_config unimplemented"); + } + static device_t bhnd_bus_null_find_hostb_device(device_t dev) { panic("bhnd_bus_find_hostb_device unimplemented"); } static bool bhnd_bus_null_is_hw_disabled(device_t dev, device_t child) { panic("bhnd_bus_is_hw_disabled unimplemented"); } static int bhnd_bus_null_get_probe_order(device_t dev, device_t child) { panic("bhnd_bus_get_probe_order unimplemented"); } static int bhnd_bus_null_get_port_rid(device_t dev, device_t child, bhnd_port_type port_type, u_int port, u_int region) { return (-1); } static int bhnd_bus_null_decode_port_rid(device_t dev, device_t child, int type, int rid, bhnd_port_type *port_type, u_int *port, u_int *region) { return (ENOENT); } static int bhnd_bus_null_get_region_addr(device_t dev, device_t child, bhnd_port_type type, u_int port, u_int region, bhnd_addr_t *addr, bhnd_size_t *size) { return (ENOENT); } static int bhnd_bus_null_get_nvram_var(device_t dev, device_t child, const char *name, void *buf, size_t *size, bhnd_nvram_type type) { return (ENODEV); } } /** * Return the active host bridge core for the bhnd bus, if any. * * @param dev The bhnd bus device. * * @retval device_t if a hostb device exists * @retval NULL if no hostb device is found. */ METHOD device_t find_hostb_device { device_t dev; } DEFAULT bhnd_bus_null_find_hostb_device; /** * Return true if the hardware components required by @p child are unpopulated * or otherwise unusable. * * In some cases, enumerated devices may have pins that are left floating, or * the hardware may otherwise be non-functional; this method allows a parent * device to explicitly specify if a successfully enumerated @p child should * be disabled. * * @param dev The device whose child is being examined. * @param child The child device. */ METHOD bool is_hw_disabled { device_t dev; device_t child; } DEFAULT bhnd_bus_null_is_hw_disabled; /** * Return the probe (and attach) order for @p child. * * All devices on the bhnd(4) bus will be probed, attached, or resumed in * ascending order; they will be suspended, shutdown, and detached in * descending order. * * The following device methods will be dispatched in ascending probe order * by the bus: * * - DEVICE_PROBE() * - DEVICE_ATTACH() * - DEVICE_RESUME() * * The following device methods will be dispatched in descending probe order * by the bus: * * - DEVICE_SHUTDOWN() * - DEVICE_DETACH() * - DEVICE_SUSPEND() * * @param dev The device whose child is being examined. * @param child The child device. * * Refer to BHND_PROBE_* and BHND_PROBE_ORDER_* for the standard set of * priorities. */ METHOD int get_probe_order { device_t dev; device_t child; } DEFAULT bhnd_bus_null_get_probe_order; /** * Return the BHND chip identification for the parent bus. * * @param dev The device whose child is being examined. * @param child The child device. */ METHOD const struct bhnd_chipid * get_chipid { device_t dev; device_t child; } DEFAULT bhnd_bus_null_get_chipid; /** * Return the BHND attachment type of the parent bus. * * @param dev The device whose child is being examined. * @param child The child device. * * @retval BHND_ATTACH_ADAPTER if the bus is resident on a bridged adapter, * such as a WiFi chipset. * @retval BHND_ATTACH_NATIVE if the bus provides hardware services (clock, * CPU, etc) to a directly attached native host. */ METHOD bhnd_attach_type get_attach_type { device_t dev; device_t child; } DEFAULT bhnd_bus_null_get_attach_type; /** * Attempt to read the BHND board identification from the parent bus. * * This relies on NVRAM access, and will fail if a valid NVRAM device cannot * be found, or is not yet attached. * * @param dev The parent of @p child. * @param child The bhnd device requesting board info. * @param[out] info On success, will be populated with the bhnd(4) device's * board information. * * @retval 0 success * @retval ENODEV No valid NVRAM source could be found. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ METHOD int read_board_info { device_t dev; device_t child; struct bhnd_board_info *info; } DEFAULT bhnd_bus_null_read_board_info; /** * Allocate and zero-initialize a buffer suitably sized and aligned for a * bhnd_devinfo structure. * * @param dev The bhnd bus device. * * @retval non-NULL success * @retval NULL allocation failed */ METHOD struct bhnd_devinfo * alloc_devinfo { device_t dev; }; /** * Release memory previously allocated for @p devinfo. * * @param dev The bhnd bus device. * @param dinfo A devinfo buffer previously allocated via * BHND_BUS_ALLOC_DEVINFO(). */ METHOD void free_devinfo { device_t dev; struct bhnd_devinfo *dinfo; }; /** * Notify a bhnd bus that a child was added. * - * Called at the end of BUS_ADD_CHILD() to allow the concrete bhnd(4) - * driver instance to initialize any additional driver-specific state for the - * child. + * This method must be called by concrete bhnd(4) driver impementations + * after @p child's bus state is fully initialized. * * @param dev The bhnd bus whose child is being added. * @param child The child added to @p dev. */ METHOD void child_added { device_t dev; device_t child; } DEFAULT bhnd_bus_null_child_added; /** * Reset the device's hardware core. * * @param dev The parent of @p child. * @param child The device to be reset. * @param flags Device-specific core flags to be supplied on reset. * * @retval 0 success * @retval non-zero error */ METHOD int reset_core { device_t dev; device_t child; uint16_t flags; } /** * Suspend a device hardware core. * * @param dev The parent of @p child. * @param child The device to be reset. * * @retval 0 success * @retval non-zero error */ METHOD int suspend_core { device_t dev; device_t child; } + +/** + * If supported by the chipset, return the clock source for the given clock. + * + * This function is only supported on early PWRCTL-equipped chipsets + * that expose clock management via their host bridge interface. Currently, + * this includes PCI (not PCIe) devices, with ChipCommon core revisions 0-9. + * + * @param dev The parent of @p child. + * @param child The bhnd device requesting a clock source. + * @param clock The clock for which a clock source will be returned. + * + * @retval bhnd_clksrc The clock source for @p clock. + * @retval BHND_CLKSRC_UNKNOWN If @p clock is unsupported, or its + * clock source is not known to the bus. + */ +METHOD bhnd_clksrc pwrctl_get_clksrc { + device_t dev; + device_t child; + bhnd_clock clock; +} DEFAULT bhnd_bus_null_pwrctl_get_clksrc; + +/** + * If supported by the chipset, gate the clock source for @p clock + * + * This function is only supported on early PWRCTL-equipped chipsets + * that expose clock management via their host bridge interface. Currently, + * this includes PCI (not PCIe) devices, with ChipCommon core revisions 0-9. + * + * @param dev The parent of @p child. + * @param child The bhnd device requesting clock gating. + * @param clock The clock to be disabled. + * + * @retval 0 success + * @retval ENODEV If bus-level clock source management is not supported. + * @retval ENXIO If bus-level management of @p clock is not supported. + */ +METHOD int pwrctl_gate_clock { + device_t dev; + device_t child; + bhnd_clock clock; +} DEFAULT bhnd_bus_null_pwrctl_gate_clock; + +/** + * If supported by the chipset, ungate the clock source for @p clock + * + * This function is only supported on early PWRCTL-equipped chipsets + * that expose clock management via their host bridge interface. Currently, + * this includes PCI (not PCIe) devices, with ChipCommon core revisions 0-9. + * + * @param dev The parent of @p child. + * @param child The bhnd device requesting clock gating. + * @param clock The clock to be enabled. + * + * @retval 0 success + * @retval ENODEV If bus-level clock source management is not supported. + * @retval ENXIO If bus-level management of @p clock is not supported. + */ +METHOD int pwrctl_ungate_clock { + device_t dev; + device_t child; + bhnd_clock clock; +} DEFAULT bhnd_bus_null_pwrctl_ungate_clock; + +/** + * Allocate and enable per-core PMU request handling for @p child. + * + * The region containing the core's PMU register block (if any) must be + * allocated via bus_alloc_resource(9) (or bhnd_alloc_resource) before + * calling BHND_BUS_ALLOC_PMU(), and must not be released until after + * calling BHND_BUS_RELEASE_PMU(). + * + * @param dev The parent of @p child. + * @param child The requesting bhnd device. + */ +METHOD int alloc_pmu { + device_t dev; + device_t child; +} DEFAULT bhnd_bus_null_alloc_pmu; + +/** + * Release per-core PMU resources allocated for @p child. Any + * outstanding PMU requests are discarded. + * + * @param dev The parent of @p child. + * @param child The requesting bhnd device. + */ +METHOD int release_pmu { + device_t dev; + device_t child; +} DEFAULT bhnd_bus_null_release_pmu; + +/** + * Request that @p clock (or faster) be routed to @p child. + * + * A driver must ask the bhnd bus to allocate PMU request state + * via BHND_BUS_ALLOC_PMU() before it can request clock resources. + * + * Request multiplexing is managed by the bus. + * + * @param dev The parent of @p child. + * @param child The bhnd device requesting @p clock. + * @param clock The requested clock source. + * + * @retval 0 success + * @retval ENODEV If an unsupported clock was requested. + * @retval ENXIO If the PMU has not been initialized or is otherwise unvailable. + */ +METHOD int request_clock { + device_t dev; + device_t child; + bhnd_clock clock; +} DEFAULT bhnd_bus_null_request_clock; + +/** + * Request that @p clocks be powered on behalf of @p child. + * + * This will power on clock sources (e.g. XTAL, PLL, etc) required for + * @p clocks and wait until they are ready, discarding any previous + * requests by @p child. + * + * Request multiplexing is managed by the bus. + * + * A driver must ask the bhnd bus to allocate PMU request state + * via BHND_BUS_ALLOC_PMU() before it can request clock resources. + * + * @param dev The parent of @p child. + * @param child The bhnd device requesting @p clock. + * @param clock The requested clock source. + * + * @retval 0 success + * @retval ENODEV If an unsupported clock was requested. + * @retval ENXIO If the PMU has not been initialized or is otherwise unvailable. + */ +METHOD int enable_clocks { + device_t dev; + device_t child; + uint32_t clocks; +} DEFAULT bhnd_bus_null_enable_clocks; + +/** + * Power up an external PMU-managed resource assigned to @p child. + * + * A driver must ask the bhnd bus to allocate PMU request state + * via BHND_BUS_ALLOC_PMU() before it can request PMU resources. + * + * @param dev The parent of @p child. + * @param child The bhnd device requesting @p rsrc. + * @param rsrc The core-specific external resource identifier. + * + * @retval 0 success + * @retval ENODEV If the PMU does not support @p rsrc. + * @retval ENXIO If the PMU has not been initialized or is otherwise unvailable. + */ +METHOD int request_ext_rsrc { + device_t dev; + device_t child; + u_int rsrc; +} DEFAULT bhnd_bus_null_request_ext_rsrc; + +/** + * Power down an external PMU-managed resource assigned to @p child. + * + * A driver must ask the bhnd bus to allocate PMU request state + * via BHND_BUS_ALLOC_PMU() before it can request PMU resources. + * + * @param dev The parent of @p child. + * @param child The bhnd device requesting @p rsrc. + * @param rsrc The core-specific external resource number. + * + * @retval 0 success + * @retval ENODEV If the PMU does not support @p rsrc. + * @retval ENXIO If the PMU has not been initialized or is otherwise unvailable. + */ +METHOD int release_ext_rsrc { + device_t dev; + device_t child; + u_int rsrc; +} DEFAULT bhnd_bus_null_release_ext_rsrc; + +/** + * Read @p width bytes at @p offset from the bus-specific agent/config + * space of @p child. + * + * @param dev The parent of @p child. + * @param child The bhnd device for which @p offset should be read. + * @param offset The offset to be read. + * @param width The size of the access. Must be 1, 2 or 4 bytes. + * + * The exact behavior of this method is bus-specific. In the case of + * bcma(4), this method provides access to the first agent port of @p child. + * + * @note Device drivers should only use this API for functionality + * that is not available via another bhnd(4) function. + */ +METHOD uint32_t read_config { + device_t dev; + device_t child; + bus_size_t offset; + u_int width; +} DEFAULT bhnd_bus_null_read_config; + +/** + * Read @p width bytes at @p offset from the bus-specific agent/config + * space of @p child. + * + * @param dev The parent of @p child. + * @param child The bhnd device for which @p offset should be read. + * @param offset The offset to be written. + * @param width The size of the access. Must be 1, 2 or 4 bytes. + * + * The exact behavior of this method is bus-specific. In the case of + * bcma(4), this method provides access to the first agent port of @p child. + * + * @note Device drivers should only use this API for functionality + * that is not available via another bhnd(4) function. + */ +METHOD void write_config { + device_t dev; + device_t child; + bus_size_t offset; + uint32_t val; + u_int width; +} DEFAULT bhnd_bus_null_write_config; /** * Allocate a bhnd resource. * * This method's semantics are functionally identical to the bus API of the same * name; refer to BUS_ALLOC_RESOURCE for complete documentation. */ METHOD struct bhnd_resource * alloc_resource { device_t dev; device_t child; int type; int *rid; rman_res_t start; rman_res_t end; rman_res_t count; u_int flags; } DEFAULT bhnd_bus_generic_alloc_resource; /** * Release a bhnd resource. * * This method's semantics are functionally identical to the bus API of the same * name; refer to BUS_RELEASE_RESOURCE for complete documentation. */ METHOD int release_resource { device_t dev; device_t child; int type; int rid; struct bhnd_resource *res; } DEFAULT bhnd_bus_generic_release_resource; /** * Activate a bhnd resource. * * This method's semantics are functionally identical to the bus API of the same * name; refer to BUS_ACTIVATE_RESOURCE for complete documentation. */ METHOD int activate_resource { device_t dev; device_t child; int type; int rid; struct bhnd_resource *r; } DEFAULT bhnd_bus_generic_activate_resource; /** * Deactivate a bhnd resource. * * This method's semantics are functionally identical to the bus API of the same * name; refer to BUS_DEACTIVATE_RESOURCE for complete documentation. */ METHOD int deactivate_resource { device_t dev; device_t child; int type; int rid; struct bhnd_resource *r; } DEFAULT bhnd_bus_generic_deactivate_resource; /** * Return true if @p region_num is a valid region on @p port_num of * @p type attached to @p child. * * @param dev The device whose child is being examined. * @param child The child device. * @param type The port type being queried. * @param port_num The port number being queried. * @param region_num The region number being queried. */ METHOD bool is_region_valid { device_t dev; device_t child; bhnd_port_type type; u_int port_num; u_int region_num; }; /** * Return the number of ports of type @p type attached to @p child. * * @param dev The device whose child is being examined. * @param child The child device. * @param type The port type being queried. */ METHOD u_int get_port_count { device_t dev; device_t child; bhnd_port_type type; }; /** * Return the number of memory regions mapped to @p child @p port of * type @p type. * * @param dev The device whose child is being examined. * @param child The child device. * @param port The port number being queried. * @param type The port type being queried. */ METHOD u_int get_region_count { device_t dev; device_t child; bhnd_port_type type; u_int port; }; /** * Return the SYS_RES_MEMORY resource-ID for a port/region pair attached to * @p child. * * @param dev The bus device. * @param child The bhnd child. * @param port_type The port type. * @param port_num The index of the child interconnect port. * @param region_num The index of the port-mapped address region. * * @retval -1 No such port/region found. */ METHOD int get_port_rid { device_t dev; device_t child; bhnd_port_type port_type; u_int port_num; u_int region_num; } DEFAULT bhnd_bus_null_get_port_rid; /** * Decode a port / region pair on @p child defined by @p type and @p rid. * * @param dev The bus device. * @param child The bhnd child. * @param type The resource type. * @param rid The resource ID. * @param[out] port_type The port's type. * @param[out] port The port identifier. * @param[out] region The identifier of the memory region on @p port. * * @retval 0 success * @retval non-zero No matching type/rid found. */ METHOD int decode_port_rid { device_t dev; device_t child; int type; int rid; bhnd_port_type *port_type; u_int *port; u_int *region; } DEFAULT bhnd_bus_null_decode_port_rid; /** * Get the address and size of @p region on @p port. * * @param dev The bus device. * @param child The bhnd child. * @param port_type The port type. * @param port The port identifier. * @param region The identifier of the memory region on @p port. * @param[out] region_addr The region's base address. * @param[out] region_size The region's size. * * @retval 0 success * @retval non-zero No matching port/region found. */ METHOD int get_region_addr { device_t dev; device_t child; bhnd_port_type port_type; u_int port; u_int region; bhnd_addr_t *region_addr; bhnd_size_t *region_size; } DEFAULT bhnd_bus_null_get_region_addr; /** * Read an NVRAM variable. * * It is the responsibility of the bus to delegate this request to * the appropriate NVRAM child device, or to a parent bus implementation. * * @param dev The bus device. * @param child The requesting device. * @param name The NVRAM variable name. * @param[out] buf On success, the requested value will be written * to this buffer. This argment may be NULL if * the value is not desired. * @param[in,out] size The capacity of @p buf. On success, will be set * to the actual size of the requested value. * @param type The data type to be written to @p buf. * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENOMEM If @p buf is non-NULL and a buffer of @p size is too * small to hold the requested value. * @retval ENODEV No valid NVRAM source could be found. * @retval EFTYPE If the @p name's data type cannot be coerced to @p type. * @retval ERANGE If value coercion would overflow @p type. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ METHOD int get_nvram_var { device_t dev; device_t child; const char *name; void *buf; size_t *size; bhnd_nvram_type type; } DEFAULT bhnd_bus_null_get_nvram_var; /** An implementation of bus_read_1() compatible with bhnd_resource */ METHOD uint8_t read_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; } /** An implementation of bus_read_2() compatible with bhnd_resource */ METHOD uint16_t read_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; } /** An implementation of bus_read_4() compatible with bhnd_resource */ METHOD uint32_t read_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; } /** An implementation of bus_write_1() compatible with bhnd_resource */ METHOD void write_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t value; } /** An implementation of bus_write_2() compatible with bhnd_resource */ METHOD void write_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t value; } /** An implementation of bus_write_4() compatible with bhnd_resource */ METHOD void write_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t value; } /** An implementation of bus_read_stream_1() compatible with bhnd_resource */ METHOD uint8_t read_stream_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; } /** An implementation of bus_read_stream_2() compatible with bhnd_resource */ METHOD uint16_t read_stream_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; } /** An implementation of bus_read_stream_4() compatible with bhnd_resource */ METHOD uint32_t read_stream_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; } /** An implementation of bus_write_stream_1() compatible with bhnd_resource */ METHOD void write_stream_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t value; } /** An implementation of bus_write_stream_2() compatible with bhnd_resource */ METHOD void write_stream_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t value; } /** An implementation of bus_write_stream_4() compatible with bhnd_resource */ METHOD void write_stream_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t value; } /** An implementation of bus_read_multi_1() compatible with bhnd_resource */ METHOD void read_multi_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_read_multi_2() compatible with bhnd_resource */ METHOD void read_multi_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_read_multi_4() compatible with bhnd_resource */ METHOD void read_multi_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_write_multi_1() compatible with bhnd_resource */ METHOD void write_multi_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_write_multi_2() compatible with bhnd_resource */ METHOD void write_multi_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_write_multi_4() compatible with bhnd_resource */ METHOD void write_multi_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_read_multi_stream_1() compatible * bhnd_resource */ METHOD void read_multi_stream_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_read_multi_stream_2() compatible * bhnd_resource */ METHOD void read_multi_stream_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_read_multi_stream_4() compatible * bhnd_resource */ METHOD void read_multi_stream_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_write_multi_stream_1() compatible * bhnd_resource */ METHOD void write_multi_stream_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_write_multi_stream_2() compatible with * bhnd_resource */ METHOD void write_multi_stream_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_write_multi_stream_4() compatible with * bhnd_resource */ METHOD void write_multi_stream_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_set_multi_1() compatible with bhnd_resource */ METHOD void set_multi_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t value; bus_size_t count; } /** An implementation of bus_set_multi_2() compatible with bhnd_resource */ METHOD void set_multi_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t value; bus_size_t count; } /** An implementation of bus_set_multi_4() compatible with bhnd_resource */ METHOD void set_multi_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t value; bus_size_t count; } /** An implementation of bus_set_region_1() compatible with bhnd_resource */ METHOD void set_region_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t value; bus_size_t count; } /** An implementation of bus_set_region_2() compatible with bhnd_resource */ METHOD void set_region_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t value; bus_size_t count; } /** An implementation of bus_set_region_4() compatible with bhnd_resource */ METHOD void set_region_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t value; bus_size_t count; } /** An implementation of bus_read_region_1() compatible with bhnd_resource */ METHOD void read_region_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_read_region_2() compatible with bhnd_resource */ METHOD void read_region_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_read_region_4() compatible with bhnd_resource */ METHOD void read_region_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_read_region_stream_1() compatible with * bhnd_resource */ METHOD void read_region_stream_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_read_region_stream_2() compatible with * bhnd_resource */ METHOD void read_region_stream_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_read_region_stream_4() compatible with * bhnd_resource */ METHOD void read_region_stream_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_write_region_1() compatible with bhnd_resource */ METHOD void write_region_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_write_region_2() compatible with bhnd_resource */ METHOD void write_region_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_write_region_4() compatible with bhnd_resource */ METHOD void write_region_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_write_region_stream_1() compatible with * bhnd_resource */ METHOD void write_region_stream_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_write_region_stream_2() compatible with * bhnd_resource */ METHOD void write_region_stream_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_write_region_stream_4() compatible with * bhnd_resource */ METHOD void write_region_stream_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_barrier() compatible with bhnd_resource */ METHOD void barrier { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; bus_size_t length; int flags; } Index: head/sys/dev/bhnd/bhnd_core.h =================================================================== --- head/sys/dev/bhnd/bhnd_core.h (revision 304869) +++ head/sys/dev/bhnd/bhnd_core.h (revision 304870) @@ -1,85 +1,49 @@ /*- * Copyright (c) 2015 Landon Fuller * Copyright (c) 2010 Broadcom Corporation * * This file is derived from the hndsoc.h header distributed with * Broadcom's initial brcm80211 Linux driver release, as * contributed to the Linux staging repository. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ #ifndef _BHND_BHND_CORE_H_ #define _BHND_BHND_CORE_H_ /* Common core control flags */ #define BHND_CF 0x0408 #define BHND_CF_BIST_EN 0x8000 /**< built-in self test */ #define BHND_CF_PME_EN 0x4000 /**< ??? */ #define BHND_CF_CORE_BITS 0x3ffc /**< core specific flag mask */ #define BHND_CF_FGC 0x0002 /**< force clock gating */ #define BHND_CF_CLOCK_EN 0x0001 /**< enable clock */ /* Common core status flags */ #define BHND_SF 0x0500 #define BHND_SF_BIST_DONE 0x8000 /**< ??? */ #define BHND_SF_BIST_ERROR 0x4000 /**< ??? */ #define BHND_SF_GATED_CLK 0x2000 /**< clock gated */ #define BHND_SF_DMA64 0x1000 /**< supports 64-bit DMA */ #define BHND_SF_CORE_BITS 0x0fff /**< core-specific status mask */ /*Reset core control flags */ #define BHND_RESET_CF 0x0800 #define BHND_RESET_CF_ENABLE 0x0001 #define BHND_RESET_SF 0x0804 -/* - * A register that is common to all cores to - * communicate w/PMU regarding clock control. - * - * TODO: Determine when this register first appeared. - */ -#define BHND_CLK_CTL_ST 0x1e0 /**< clock control and status */ - -/* - * BHND_CLK_CTL_ST register - * - * Clock Mode Name Description - * High Throughput (HT) Full bandwidth, low latency. Generally supplied - * from PLL. - * Active Low Power (ALP) Register access, low speed DMA. - * Idle Low Power (ILP) No interconnect activity, or if long latency - * is permitted. - */ -#define BHND_CCS_FORCEALP 0x00000001 /**< force ALP request */ -#define BHND_CCS_FORCEHT 0x00000002 /**< force HT request */ -#define BHND_CCS_FORCEILP 0x00000004 /**< force ILP request */ -#define BHND_CCS_ALPAREQ 0x00000008 /**< ALP Avail Request */ -#define BHND_CCS_HTAREQ 0x00000010 /**< HT Avail Request */ -#define BHND_CCS_FORCEHWREQOFF 0x00000020 /**< Force HW Clock Request Off */ -#define BHND_CCS_ERSRC_REQ_MASK 0x00000700 /**< external resource requests */ -#define BHND_CCS_ERSRC_REQ_SHIFT 8 -#define BHND_CCS_ALPAVAIL 0x00010000 /**< ALP is available */ -#define BHND_CCS_HTAVAIL 0x00020000 /**< HT is available */ -#define BHND_CCS_BP_ON_APL 0x00040000 /**< RO: Backplane is running on ALP clock */ -#define BHND_CCS_BP_ON_HT 0x00080000 /**< RO: Backplane is running on HT clock */ -#define BHND_CCS_ERSRC_STS_MASK 0x07000000 /**< external resource status */ -#define BHND_CCS_ERSRC_STS_SHIFT 24 - -#define BHND_CCS0_HTAVAIL 0x00010000 /**< HT avail in chipc and pcmcia on 4328a0 */ -#define BHND_CCS0_ALPAVAIL 0x00020000 /**< ALP avail in chipc and pcmcia on 4328a0 */ - #endif /* _BHND_BHND_CORE_H_ */ Index: head/sys/dev/bhnd/bhnd_ids.h =================================================================== --- head/sys/dev/bhnd/bhnd_ids.h (revision 304869) +++ head/sys/dev/bhnd/bhnd_ids.h (revision 304870) @@ -1,1133 +1,1127 @@ /*- * Copyright (c) 2015-2016 Landon Fuller * Copyright (c) 1999-2015, Broadcom Corporation * * This file is derived from the bcmdevs.h header contributed by Broadcom * to Android's bcmdhd driver module, later revisions of bcmdevs.h distributed * with the dd-wrt project, and the hndsoc.h header distributed with Broadcom's * initial brcm80211 Linux driver release as contributed to the Linux staging * repository. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ #ifndef _BHND_BHND_IDS_H_ #define _BHND_BHND_IDS_H_ /* * JEDEC JEP-106 Core Vendor IDs * * These are the JEDEC JEP-106 manufacturer ID representions (with ARM's * non-standard 4-bit continutation code), as used in ARM's PrimeCell * identification registers, bcma(4) EROM core descriptors, etc. * * @note * Bus implementations that predate the adoption of ARM IP * will need to convert bus-specific vendor IDs to their BHND_MFGID * JEP-106 equivalents. * * @par ARM 4-bit Continuation Code * * BHND MFGIDs are encoded using ARM's non-standard 4-bit continuation code * format: * * @code{.unparsed} * [11:8 ][7:0 ] * [cont code][mfg id] * @endcode * * The 4-bit continuation code field specifies the number of JEP-106 * continuation codes that prefix the manufacturer's ID code. In the case of * ARM's JEP-106 ID of `0x7F 0x7F 0x7F 0x7F 0x3B`, the four 0x7F continuations * are encoded as '4' in the 4-bit continuation code field (i.e. 0x43B). */ #define BHND_MFGID_ARM 0x043b /**< arm JEP-106 vendor id */ #define BHND_MFGID_BCM 0x04bf /**< broadcom JEP-106 vendor id */ #define BHND_MFGID_MIPS 0x04a7 /**< mips JEP-106 vendor id */ #define BHND_MFGID_INVALID 0x0000 /**< invalid JEP-106 vendor id */ /* * OCP (Open Core Protocol) Vendor IDs. * * OCP-IP assigned vendor codes are used by siba(4) */ #define OCP_VENDOR_BCM 0x4243 /**< Broadcom OCP vendor id */ /* PCI vendor IDs */ #define PCI_VENDOR_EPIGRAM 0xfeda #define PCI_VENDOR_BROADCOM 0x14e4 #define PCI_VENDOR_3COM 0x10b7 #define PCI_VENDOR_NETGEAR 0x1385 #define PCI_VENDOR_DIAMOND 0x1092 #define PCI_VENDOR_INTEL 0x8086 #define PCI_VENDOR_DELL 0x1028 #define PCI_VENDOR_HP 0x103c #define PCI_VENDOR_HP_COMPAQ 0x0e11 #define PCI_VENDOR_APPLE 0x106b #define PCI_VENDOR_SI_IMAGE 0x1095 /* Silicon Image, used by Arasan SDIO Host */ #define PCI_VENDOR_BUFFALO 0x1154 /* Buffalo vendor id */ #define PCI_VENDOR_TI 0x104c /* Texas Instruments */ #define PCI_VENDOR_RICOH 0x1180 /* Ricoh */ #define PCI_VENDOR_JMICRON 0x197b /* PCMCIA vendor IDs */ #define PCMCIA_VENDOR_BROADCOM 0x02d0 /* SDIO vendor IDs */ #define SDIO_VENDOR_BROADCOM 0x00BF /* USB dongle VID/PIDs */ #define USB_VID_BROADCOM 0x0a5c #define USB_PID_BCM4328 0xbd12 #define USB_PID_BCM4322 0xbd13 #define USB_PID_BCM4319 0xbd16 #define USB_PID_BCM43236 0xbd17 #define USB_PID_BCM4332 0xbd18 #define USB_PID_BCM4330 0xbd19 #define USB_PID_BCM4334 0xbd1a #define USB_PID_BCM43239 0xbd1b #define USB_PID_BCM4324 0xbd1c #define USB_PID_BCM4360 0xbd1d #define USB_PID_BCM43143 0xbd1e #define USB_PID_BCM43242 0xbd1f #define USB_PID_BCM43342 0xbd21 #define USB_PID_BCM4335 0xbd20 #define USB_PID_BCM4350 0xbd23 #define USB_PID_BCM43341 0xbd22 #define USB_PID_BCM_DNGL_BDC 0x0bdc /* BDC USB device controller IP? */ #define USB_PID_BCM_DNGL_JTAG 0x4a44 /* HW USB BLOCK [CPULESS USB] PIDs */ #define USB_PID_CCM_HWUSB_43239 43239 /* PCI Device IDs */ #define PCI_DEVID_BCM4210 0x1072 /* never used */ #define PCI_DEVID_BCM4230 0x1086 /* never used */ #define PCI_DEVID_BCM4401_ENET 0x170c /* 4401b0 production enet cards */ #define PCI_DEVID_BCM3352 0x3352 /* bcm3352 device id */ #define PCI_DEVID_BCM3360 0x3360 /* bcm3360 device id */ #define PCI_DEVID_BCM4211 0x4211 #define PCI_DEVID_BCM4231 0x4231 #define PCI_DEVID_BCM4301 0x4301 /* 4031 802.11b */ #define PCI_DEVID_BCM4303_D11B 0x4303 /* 4303 802.11b */ #define PCI_DEVID_BCM4306 0x4306 /* 4306 802.11b/g */ #define PCI_DEVID_BCM4307 0x4307 /* 4307 802.11b, 10/100 ethernet, V.92 modem */ #define PCI_DEVID_BCM4311_D11G 0x4311 /* 4311 802.11b/g id */ #define PCI_DEVID_BCM4311_D11DUAL 0x4312 /* 4311 802.11a/b/g id */ #define PCI_DEVID_BCM4311_D11A 0x4313 /* 4311 802.11a id */ #define PCI_DEVID_BCM4328_D11DUAL 0x4314 /* 4328/4312 802.11a/g id */ #define PCI_DEVID_BCM4328_D11G 0x4315 /* 4328/4312 802.11g id */ #define PCI_DEVID_BCM4328_D11A 0x4316 /* 4328/4312 802.11a id */ #define PCI_DEVID_BCM4318_D11G 0x4318 /* 4318 802.11b/g id */ #define PCI_DEVID_BCM4318_D11DUAL 0x4319 /* 4318 802.11a/b/g id */ #define PCI_DEVID_BCM4318_D11A 0x431a /* 4318 802.11a id */ #define PCI_DEVID_BCM4325_D11DUAL 0x431b /* 4325 802.11a/g id */ #define PCI_DEVID_BCM4325_D11G 0x431c /* 4325 802.11g id */ #define PCI_DEVID_BCM4325_D11A 0x431d /* 4325 802.11a id */ #define PCI_DEVID_BCM4306_D11G 0x4320 /* 4306 802.11g */ #define PCI_DEVID_BCM4306_D11A 0x4321 /* 4306 802.11a */ #define PCI_DEVID_BCM4306_UART 0x4322 /* 4306 uart */ #define PCI_DEVID_BCM4306_V90 0x4323 /* 4306 v90 codec */ #define PCI_DEVID_BCM4306_D11DUAL 0x4324 /* 4306 dual A+B */ #define PCI_DEVID_BCM4306_D11G_ID2 0x4325 /* BCM4306_D11G; INF w/loose binding war */ #define PCI_DEVID_BCM4321_D11N 0x4328 /* 4321 802.11n dualband id */ #define PCI_DEVID_BCM4321_D11N2G 0x4329 /* 4321 802.11n 2.4Ghz band id */ #define PCI_DEVID_BCM4321_D11N5G 0x432a /* 4321 802.11n 5Ghz band id */ #define PCI_DEVID_BCM4322_D11N 0x432b /* 4322 802.11n dualband device */ #define PCI_DEVID_BCM4322_D11N2G 0x432c /* 4322 802.11n 2.4GHz device */ #define PCI_DEVID_BCM4322_D11N5G 0x432d /* 4322 802.11n 5GHz device */ #define PCI_DEVID_BCM4329_D11N 0x432e /* 4329 802.11n dualband device */ #define PCI_DEVID_BCM4329_D11N2G 0x432f /* 4329 802.11n 2.4G device */ #define PCI_DEVID_BCM4329_D11N5G 0x4330 /* 4329 802.11n 5G device */ #define PCI_DEVID_BCM4315_D11DUAL 0x4334 /* 4315 802.11a/g id */ #define PCI_DEVID_BCM4315_D11G 0x4335 /* 4315 802.11g id */ #define PCI_DEVID_BCM4315_D11A 0x4336 /* 4315 802.11a id */ #define PCI_DEVID_BCM4319_D11N 0x4337 /* 4319 802.11n dualband device */ #define PCI_DEVID_BCM4319_D11N2G 0x4338 /* 4319 802.11n 2.4G device */ #define PCI_DEVID_BCM4319_D11N5G 0x4339 /* 4319 802.11n 5G device */ #define PCI_DEVID_BCM43231_D11N2G 0x4340 /* 43231 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43221_D11N2G 0x4341 /* 43221 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43222_D11N 0x4350 /* 43222 802.11n dualband device */ #define PCI_DEVID_BCM43222_D11N2G 0x4351 /* 43222 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43222_D11N5G 0x4352 /* 43222 802.11n 5GHz device */ #define PCI_DEVID_BCM43224_D11N 0x4353 /* 43224 802.11n dualband device */ #define PCI_DEVID_BCM43224_D11N_ID_VEN1 0x0576 /* Vendor specific 43224 802.11n db device */ #define PCI_DEVID_BCM43226_D11N 0x4354 /* 43226 802.11n dualband device */ #define PCI_DEVID_BCM43236_D11N 0x4346 /* 43236 802.11n dualband device */ #define PCI_DEVID_BCM43236_D11N2G 0x4347 /* 43236 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43236_D11N5G 0x4348 /* 43236 802.11n 5GHz device */ #define PCI_DEVID_BCM43225_D11N2G 0x4357 /* 43225 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43421_D11N 0xA99D /* 43421 802.11n dualband device */ #define PCI_DEVID_BCM4313_D11N2G 0x4727 /* 4313 802.11n 2.4G device */ #define PCI_DEVID_BCM4330_D11N 0x4360 /* 4330 802.11n dualband device */ #define PCI_DEVID_BCM4330_D11N2G 0x4361 /* 4330 802.11n 2.4G device */ #define PCI_DEVID_BCM4330_D11N5G 0x4362 /* 4330 802.11n 5G device */ #define PCI_DEVID_BCM4336_D11N 0x4343 /* 4336 802.11n 2.4GHz device */ #define PCI_DEVID_BCM6362_D11N 0x435f /* 6362 802.11n dualband device */ #define PCI_DEVID_BCM6362_D11N2G 0x433f /* 6362 802.11n 2.4Ghz band id */ #define PCI_DEVID_BCM6362_D11N5G 0x434f /* 6362 802.11n 5Ghz band id */ #define PCI_DEVID_BCM4331_D11N 0x4331 /* 4331 802.11n dualband id */ #define PCI_DEVID_BCM4331_D11N2G 0x4332 /* 4331 802.11n 2.4Ghz band id */ #define PCI_DEVID_BCM4331_D11N5G 0x4333 /* 4331 802.11n 5Ghz band id */ #define PCI_DEVID_BCM43237_D11N 0x4355 /* 43237 802.11n dualband device */ #define PCI_DEVID_BCM43237_D11N5G 0x4356 /* 43237 802.11n 5GHz device */ #define PCI_DEVID_BCM43227_D11N2G 0x4358 /* 43228 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43228_D11N 0x4359 /* 43228 802.11n DualBand device */ #define PCI_DEVID_BCM43228_D11N5G 0x435a /* 43228 802.11n 5GHz device */ #define PCI_DEVID_BCM43362_D11N 0x4363 /* 43362 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43239_D11N 0x4370 /* 43239 802.11n dualband device */ #define PCI_DEVID_BCM4324_D11N 0x4374 /* 4324 802.11n dualband device */ #define PCI_DEVID_BCM43217_D11N2G 0x43a9 /* 43217 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43131_D11N2G 0x43aa /* 43131 802.11n 2.4GHz device */ #define PCI_DEVID_BCM4314_D11N2G 0x4364 /* 4314 802.11n 2.4G device */ #define PCI_DEVID_BCM43142_D11N2G 0x4365 /* 43142 802.11n 2.4G device */ #define PCI_DEVID_BCM43143_D11N2G 0x4366 /* 43143 802.11n 2.4G device */ #define PCI_DEVID_BCM4334_D11N 0x4380 /* 4334 802.11n dualband device */ #define PCI_DEVID_BCM4334_D11N2G 0x4381 /* 4334 802.11n 2.4G device */ #define PCI_DEVID_BCM4334_D11N5G 0x4382 /* 4334 802.11n 5G device */ #define PCI_DEVID_BCM43342_D11N 0x4383 /* 43342 802.11n dualband device */ #define PCI_DEVID_BCM43342_D11N2G 0x4384 /* 43342 802.11n 2.4G device */ #define PCI_DEVID_BCM43342_D11N5G 0x4385 /* 43342 802.11n 5G device */ #define PCI_DEVID_BCM43341_D11N 0x4386 /* 43341 802.11n dualband device */ #define PCI_DEVID_BCM43341_D11N2G 0x4387 /* 43341 802.11n 2.4G device */ #define PCI_DEVID_BCM43341_D11N5G 0x4388 /* 43341 802.11n 5G device */ #define PCI_DEVID_BCM4360_D11AC 0x43a0 #define PCI_DEVID_BCM4360_D11AC2G 0x43a1 #define PCI_DEVID_BCM4360_D11AC5G 0x43a2 #define PCI_DEVID_BCM4335_D11AC 0x43ae #define PCI_DEVID_BCM4335_D11AC2G 0x43af #define PCI_DEVID_BCM4335_D11AC5G 0x43b0 #define PCI_DEVID_BCM4352_D11AC 0x43b1 /* 4352 802.11ac dualband device */ #define PCI_DEVID_BCM4352_D11AC2G 0x43b2 /* 4352 802.11ac 2.4G device */ #define PCI_DEVID_BCM4352_D11AC5G 0x43b3 /* 4352 802.11ac 5G device */ #define PCI_DEVID_PCIXX21_FLASHMEDIA0 0x8033 /* TI PCI xx21 Standard Host Controller */ #define PCI_DEVID_PCIXX21_SDIOH0 0x8034 /* TI PCI xx21 Standard Host Controller */ /* PCI Subsystem Vendor IDs */ #define PCI_SUBVENDOR_BCM943228HMB 0x0607 #define PCI_SUBVENDOR_BCM94313HMGBL 0x0608 #define PCI_SUBVENDOR_BCM94313HMG 0x0609 #define PCI_SUBVENDOR_BCM943142HM 0x0611 /* PCI Subsystem Device IDs */ #define PCI_SUBDEVID_BCM43143_D11N2G 0x4366 /* 43143 802.11n 2.4G device */ #define PCI_SUBDEVID_BCM43242_D11N 0x4367 /* 43242 802.11n dualband device */ #define PCI_SUBDEVID_BCM43242_D11N2G 0x4368 /* 43242 802.11n 2.4G device */ #define PCI_SUBDEVID_BCM43242_D11N5G 0x4369 /* 43242 802.11n 5G device */ #define PCI_SUBDEVID_BCM4350_D11AC 0x43a3 #define PCI_SUBDEVID_BCM4350_D11AC2G 0x43a4 #define PCI_SUBDEVID_BCM4350_D11AC5G 0x43a5 #define PCI_SUBDEVID_BCMGPRS_UART 0x4333 /* Uart id used by 4306/gprs card */ #define PCI_SUBDEVID_BCMGPRS2_UART 0x4344 /* Uart id used by 4306/gprs card */ #define PCI_SUBDEVID_BCM_FPGA_JTAGM 0x43f0 /* FPGA jtagm device id */ #define PCI_SUBDEVID_BCM_JTAGM 0x43f1 /* BCM jtagm device id */ #define PCI_SUBDEVID_BCM_SDIOH_FPGA 0x43f2 /* sdio host fpga */ #define PCI_SUBDEVID_BCM_SDIOH 0x43f3 /* BCM sdio host id */ #define PCI_SUBDEVID_BCM_SDIOD_FPGA 0x43f4 /* sdio device fpga */ #define PCI_SUBDEVID_BCM_SPIH_FPGA 0x43f5 /* PCI SPI Host Controller FPGA */ #define PCI_SUBDEVID_BCM_SPIH 0x43f6 /* Synopsis SPI Host Controller */ #define PCI_SUBDEVID_BCM_MIMO_FPGA 0x43f8 /* FPGA mimo minimacphy device id */ #define PCI_SUBDEVID_BCM_JTAGM2 0x43f9 /* PCI_SUBDEVID_BCM alternate jtagm device id */ #define PCI_SUBDEVID_BCM_SDHCI_FPGA 0x43fa /* Standard SDIO Host Controller FPGA */ #define PCI_SUBDEVID_BCM4402_ENET 0x4402 /* 4402 enet */ #define PCI_SUBDEVID_BCM4402_V90 0x4403 /* 4402 v90 codec */ #define PCI_SUBDEVID_BCM4410 0x4410 /* bcm44xx family pci iline */ #define PCI_SUBDEVID_BCM4412 0x4412 /* bcm44xx family pci enet */ #define PCI_SUBDEVID_BCM4430 0x4430 /* bcm44xx family cardbus iline */ #define PCI_SUBDEVID_BCM4432 0x4432 /* bcm44xx family cardbus enet */ #define PCI_SUBDEVID_BCM4704_ENET 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */ #define PCI_SUBDEVID_BCM4710 0x4710 /* 4710 primary function 0 */ #define PCI_SUBDEVID_BCM47XX_AUDIO 0x4711 /* 47xx audio codec */ #define PCI_SUBDEVID_BCM47XX_V90 0x4712 /* 47xx v90 codec */ #define PCI_SUBDEVID_BCM47XX_ENET 0x4713 /* 47xx enet */ #define PCI_SUBDEVID_BCM47XX_EXT 0x4714 /* 47xx external i/f */ #define PCI_SUBDEVID_BCM47XX_GMAC 0x4715 /* 47xx Unimac based GbE */ #define PCI_SUBDEVID_BCM47XX_USBH 0x4716 /* 47xx usb host */ #define PCI_SUBDEVID_BCM47XX_USBD 0x4717 /* 47xx usb device */ #define PCI_SUBDEVID_BCM47XX_IPSEC 0x4718 /* 47xx ipsec */ #define PCI_SUBDEVID_BCM47XX_ROBO 0x4719 /* 47xx/53xx roboswitch core */ #define PCI_SUBDEVID_BCM47XX_USB20H 0x471a /* 47xx usb 2.0 host */ #define PCI_SUBDEVID_BCM47XX_USB20D 0x471b /* 47xx usb 2.0 device */ #define PCI_SUBDEVID_BCM47XX_ATA100 0x471d /* 47xx parallel ATA */ #define PCI_SUBDEVID_BCM47XX_SATAXOR 0x471e /* 47xx serial ATA & XOR DMA */ #define PCI_SUBDEVID_BCM47XX_GIGETH 0x471f /* 47xx GbE (5700) */ #define PCI_SUBDEVID_BCM4712_MIPS 0x4720 /* 4712 base devid */ #define PCI_SUBDEVID_BCM4716 0x4722 /* 4716 base devid */ #define PCI_SUBDEVID_BCM47XX_USB30H 0x472a /* 47xx usb 3.0 host */ #define PCI_SUBDEVID_BCM47XX_USB30D 0x472b /* 47xx usb 3.0 device */ #define PCI_SUBDEVID_BCM47XX_SMBUS_EMU 0x47fe /* 47xx emulated SMBus device */ #define PCI_SUBDEVID_BCM47XX_XOR_EMU 0x47ff /* 47xx emulated XOR engine */ #define PCI_SUBDEVID_BCM_EPI41210 0xa0fa /* bcm4210 */ #define PCI_SUBDEVID_BCM_EPI41230 0xa10e /* bcm4230 */ #define PCI_SUBDEVID_BCM_JINVANI_SDIOH 0x4743 /* Jinvani SDIO Gold Host */ #define PCI_SUBDEVID_BCM27XX_SDIOH 0x2702 /* PCI_SUBDEVID_BCM27xx Standard SDIO Host */ #define PCI_SUBDEVID_BCM_PCIXX21_FLASHMEDIA 0x803b /* TI PCI xx21 Standard Host Controller */ #define PCI_SUBDEVID_BCM_PCIXX21_SDIOH 0x803c /* TI PCI xx21 Standard Host Controller */ #define PCI_SUBDEVID_BCM_R5C822_SDIOH 0x0822 /* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host */ #define PCI_SUBDEVID_BCM_JMICRON_SDIOH 0x2381 /* JMicron Standard SDIO Host Controller */ /* Broadcom ChipCommon Chip IDs */ #define BHND_CHIPID_BCM4306 0x4306 /* 4306 chipcommon chipid */ #define BHND_CHIPID_BCM4311 0x4311 /* 4311 PCIe 802.11a/b/g */ #define BHND_CHIPID_BCM43111 43111 /* 43111 chipcommon chipid (OTP chipid) */ #define BHND_CHIPID_BCM43112 43112 /* 43112 chipcommon chipid (OTP chipid) */ #define BHND_CHIPID_BCM4312 0x4312 /* 4312 chipcommon chipid */ #define BHND_CHIPID_BCM4313 0x4313 /* 4313 chip id */ #define BHND_CHIPID_BCM43131 43131 /* 43131 chip id (OTP chipid) */ #define BHND_CHIPID_BCM4315 0x4315 /* 4315 chip id */ #define BHND_CHIPID_BCM4318 0x4318 /* 4318 chipcommon chipid */ #define BHND_CHIPID_BCM4319 0x4319 /* 4319 chip id */ #define BHND_CHIPID_BCM4320 0x4320 /* 4320 chipcommon chipid */ #define BHND_CHIPID_BCM4321 0x4321 /* 4321 chipcommon chipid */ #define BHND_CHIPID_BCM43217 43217 /* 43217 chip id (OTP chipid) */ #define BHND_CHIPID_BCM4322 0x4322 /* 4322 chipcommon chipid */ #define BHND_CHIPID_BCM43221 43221 /* 43221 chipcommon chipid (OTP chipid) */ #define BHND_CHIPID_BCM43222 43222 /* 43222 chipcommon chipid */ #define BHND_CHIPID_BCM43224 43224 /* 43224 chipcommon chipid */ #define BHND_CHIPID_BCM43225 43225 /* 43225 chipcommon chipid */ #define BHND_CHIPID_BCM43227 43227 /* 43227 chipcommon chipid */ #define BHND_CHIPID_BCM43228 43228 /* 43228 chipcommon chipid */ #define BHND_CHIPID_BCM43226 43226 /* 43226 chipcommon chipid */ #define BHND_CHIPID_BCM43231 43231 /* 43231 chipcommon chipid (OTP chipid) */ #define BHND_CHIPID_BCM43234 43234 /* 43234 chipcommon chipid */ #define BHND_CHIPID_BCM43235 43235 /* 43235 chipcommon chipid */ #define BHND_CHIPID_BCM43236 43236 /* 43236 chipcommon chipid */ #define BHND_CHIPID_BCM43237 43237 /* 43237 chipcommon chipid */ #define BHND_CHIPID_BCM43238 43238 /* 43238 chipcommon chipid */ #define BHND_CHIPID_BCM43239 43239 /* 43239 chipcommon chipid */ #define BHND_CHIPID_BCM43420 43420 /* 43222 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM43421 43421 /* 43224 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM43428 43428 /* 43228 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM43431 43431 /* 4331 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM43460 43460 /* 4360 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM43462 0xA9C6 /* 43462 chipcommon chipid */ #define BHND_CHIPID_BCM4325 0x4325 /* 4325 chip id */ #define BHND_CHIPID_BCM4328 0x4328 /* 4328 chip id */ #define BHND_CHIPID_BCM4329 0x4329 /* 4329 chipcommon chipid */ #define BHND_CHIPID_BCM4331 0x4331 /* 4331 chipcommon chipid */ #define BHND_CHIPID_BCM4336 0x4336 /* 4336 chipcommon chipid */ #define BHND_CHIPID_BCM43362 43362 /* 43362 chipcommon chipid */ #define BHND_CHIPID_BCM4330 0x4330 /* 4330 chipcommon chipid */ #define BHND_CHIPID_BCM6362 0x6362 /* 6362 chipcommon chipid */ #define BHND_CHIPID_BCM4314 0x4314 /* 4314 chipcommon chipid */ #define BHND_CHIPID_BCM43142 43142 /* 43142 chipcommon chipid */ #define BHND_CHIPID_BCM43143 43143 /* 43143 chipcommon chipid */ #define BHND_CHIPID_BCM4324 0x4324 /* 4324 chipcommon chipid */ #define BHND_CHIPID_BCM43242 43242 /* 43242 chipcommon chipid */ #define BHND_CHIPID_BCM43243 43243 /* 43243 chipcommon chipid */ #define BHND_CHIPID_BCM4334 0x4334 /* 4334 chipcommon chipid */ #define BHND_CHIPID_BCM4335 0x4335 /* 4335 chipcommon chipid */ #define BHND_CHIPID_BCM4360 0x4360 /* 4360 chipcommon chipid */ #define BHND_CHIPID_BCM43602 0xaa52 /* 43602 chipcommon chipid */ #define BHND_CHIPID_BCM4352 0x4352 /* 4352 chipcommon chipid */ #define BHND_CHIPID_BCM43526 0xAA06 #define BHND_CHIPID_BCM43341 43341 /* 43341 chipcommon chipid */ #define BHND_CHIPID_BCM43342 43342 /* 43342 chipcommon chipid */ #define BHND_CHIPID_BCM4335 0x4335 #define BHND_CHIPID_BCM4350 0x4350 /* 4350 chipcommon chipid */ #define BHND_CHIPID_BCM4342 4342 /* 4342 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM4402 0x4402 /* 4402 chipid */ #define BHND_CHIPID_BCM4704 0x4704 /* 4704 chipcommon chipid */ #define BHND_CHIPID_BCM4706 0x5300 /* 4706 chipcommon chipid */ #define BHND_CHIPID_BCM4707 53010 /* 4707 chipcommon chipid */ #define BHND_CHIPID_BCM53018 53018 /* 53018 chipcommon chipid */ #define BHND_CHIPID_IS_BCM4707(chipid) \ (((chipid) == BHND_CHIPID_BCM4707) || \ ((chipid) == BHND_CHIPID_BCM53018)) #define BHND_CHIPID_BCM4710 0x4710 /* 4710 chipid */ #define BHND_CHIPID_BCM4712 0x4712 /* 4712 chipcommon chipid */ #define BHND_CHIPID_BCM4716 0x4716 /* 4716 chipcommon chipid */ #define BHND_CHIPID_BCM47162 47162 /* 47162 chipcommon chipid */ #define BHND_CHIPID_BCM4748 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM4749 0x4749 /* 5357 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM4785 0x4785 /* 4785 chipcommon chipid */ #define BHND_CHIPID_BCM5350 0x5350 /* 5350 chipcommon chipid */ #define BHND_CHIPID_BCM5352 0x5352 /* 5352 chipcommon chipid */ #define BHND_CHIPID_BCM5354 0x5354 /* 5354 chipcommon chipid */ #define BHND_CHIPID_BCM5365 0x5365 /* 5365 chipcommon chipid */ #define BHND_CHIPID_BCM5356 0x5356 /* 5356 chipcommon chipid */ #define BHND_CHIPID_BCM5357 0x5357 /* 5357 chipcommon chipid */ #define BHND_CHIPID_BCM53572 53572 /* 53572 chipcommon chipid */ /* Broadcom ChipCommon Package IDs */ #define BHND_PKGID_BCM4303 2 /* 4303 package id */ #define BHND_PKGID_BCM4309 1 /* 4309 package id */ #define BHND_PKGID_BCM4712LARGE 0 /* 340pin 4712 package id */ #define BHND_PKGID_BCM4712SMALL 1 /* 200pin 4712 package id */ #define BHND_PKGID_BCM4712MID 2 /* 225pin 4712 package id */ #define BHND_PKGID_BCM4328USBD11G 2 /* 4328 802.11g USB package id */ #define BHND_PKGID_BCM4328USBDUAL 3 /* 4328 802.11a/g USB package id */ #define BHND_PKGID_BCM4328SDIOD11G 4 /* 4328 802.11g SDIO package id */ #define BHND_PKGID_BCM4328SDIODUAL 5 /* 4328 802.11a/g SDIO package id */ #define BHND_PKGID_BCM4329_289PIN 0 /* 4329 289-pin package id */ #define BHND_PKGID_BCM4329_182PIN 1 /* 4329N 182-pin package id */ #define BHND_PKGID_BCM5354E 1 /* 5354E package id */ #define BHND_PKGID_BCM4716 8 /* 4716 package id */ #define BHND_PKGID_BCM4717 9 /* 4717 package id */ #define BHND_PKGID_BCM4718 10 /* 4718 package id */ #define BHND_PKGID_BCM5356_NONMODE 1 /* 5356 package without nmode suppport */ #define BHND_PKGID_BCM5358U 8 /* 5358U package id */ #define BHND_PKGID_BCM5358 9 /* 5358 package id */ #define BHND_PKGID_BCM47186 10 /* 47186 package id */ #define BHND_PKGID_BCM5357 11 /* 5357 package id */ #define BHND_PKGID_BCM5356U 12 /* 5356U package id */ #define BHND_PKGID_BCM53572 8 /* 53572 package id */ #define BHND_PKGID_BCM5357C0 8 /* 5357c0 package id (the same as 53572) */ #define BHND_PKGID_BCM47188 9 /* 47188 package id */ #define BHND_PKGID_BCM5358C0 0xa /* 5358c0 package id */ #define BHND_PKGID_BCM5356C0 0xb /* 5356c0 package id */ #define BHND_PKGID_BCM4331TT 8 /* 4331 12x12 package id */ #define BHND_PKGID_BCM4331TN 9 /* 4331 12x9 package id */ #define BHND_PKGID_BCM4331TNA0 0xb /* 4331 12x9 package id */ #define BHND_PKGID_BCM4706L 1 /* 4706L package id */ #define BHND_PKGID_HDLSIM5350 1 /* HDL simulator package id for a 5350 */ #define BHND_PKGID_HDLSIM 14 /* HDL simulator package id */ #define BHND_PKGID_HWSIM 15 /* Hardware simulator package id */ #define BHND_PKGID_BCM43224_FAB_CSM 0x8 /* the chip is manufactured by CSM */ #define BHND_PKGID_BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */ #define BHND_PKGID_BCM4336_WLBGA 0x8 #define BHND_PKGID_BCM4330_WLBGA 0x0 #define BHND_PKGID_BCM4314PCIE_ARM (8 | 0) /* 4314 QFN PCI package id, bit 3 tie high */ #define BHND_PKGID_BCM4314SDIO (8 | 1) /* 4314 QFN SDIO package id */ #define BHND_PKGID_BCM4314PCIE (8 | 2) /* 4314 QFN PCI (ARM-less) package id */ #define BHND_PKGID_BCM4314SDIO_ARM (8 | 3) /* 4314 QFN SDIO (ARM-less) package id */ #define BHND_PKGID_BCM4314SDIO_FPBGA (8 | 4) /* 4314 FpBGA SDIO package id */ #define BHND_PKGID_BCM4314DEV (8 | 6) /* 4314 Development package id */ #define BHND_PKGID_BCM4707 1 /* 4707 package id */ #define BHND_PKGID_BCM4708 2 /* 4708 package id */ #define BHND_PKGID_BCM4709 0 /* 4709 package id */ #define BHND_PKGID_BCM4335_WLCSP (0x0) /* WLCSP Module/Mobile SDIO/HSIC. */ #define BHND_PKGID_BCM4335_FCBGA (0x1) /* FCBGA PC/Embedded/Media PCIE/SDIO */ #define BHND_PKGID_BCM4335_WLBGA (0x2) /* WLBGA COB/Mobile SDIO/HSIC. */ #define BHND_PKGID_BCM4335_FCBGAD (0x3) /* FCBGA Debug Debug/Dev All if's. */ #define BHND_PKGID_PKG_MASK_BCM4335 (0x3) /* Broadcom Core IDs */ #define BHND_COREID_INVALID 0x700 /* Invalid coreid */ #define BHND_COREID_CC 0x800 /* chipcommon core */ #define BHND_COREID_ILINE20 0x801 /* iline20 core */ #define BHND_COREID_SRAM 0x802 /* sram core */ #define BHND_COREID_SDRAM 0x803 /* sdram core */ #define BHND_COREID_PCI 0x804 /* pci core */ #define BHND_COREID_MIPS 0x805 /* mips core */ #define BHND_COREID_ENET 0x806 /* enet mac core */ #define BHND_COREID_CODEC 0x807 /* v90 codec core */ #define BHND_COREID_USB 0x808 /* usb 1.1 host/device core */ #define BHND_COREID_ADSL 0x809 /* ADSL core */ #define BHND_COREID_ILINE100 0x80a /* iline100 core */ #define BHND_COREID_IPSEC 0x80b /* ipsec core */ #define BHND_COREID_UTOPIA 0x80c /* utopia core */ #define BHND_COREID_PCMCIA 0x80d /* pcmcia core */ #define BHND_COREID_SOCRAM 0x80e /* internal memory core */ #define BHND_COREID_MEMC 0x80f /* memc sdram core */ #define BHND_COREID_OFDM 0x810 /* OFDM phy core */ #define BHND_COREID_EXTIF 0x811 /* external interface core */ #define BHND_COREID_D11 0x812 /* 802.11 MAC core */ #define BHND_COREID_APHY 0x813 /* 802.11a phy core */ #define BHND_COREID_BPHY 0x814 /* 802.11b phy core */ #define BHND_COREID_GPHY 0x815 /* 802.11g phy core */ #define BHND_COREID_MIPS33 0x816 /* mips3302 core */ #define BHND_COREID_USB11H 0x817 /* usb 1.1 host core */ #define BHND_COREID_USB11D 0x818 /* usb 1.1 device core */ #define BHND_COREID_USB20H 0x819 /* usb 2.0 host core */ #define BHND_COREID_USB20D 0x81a /* usb 2.0 device core */ #define BHND_COREID_SDIOH 0x81b /* sdio host core */ #define BHND_COREID_ROBO 0x81c /* roboswitch core */ #define BHND_COREID_ATA100 0x81d /* parallel ATA core */ #define BHND_COREID_SATAXOR 0x81e /* serial ATA & XOR DMA core */ #define BHND_COREID_GIGETH 0x81f /* gigabit ethernet core */ #define BHND_COREID_PCIE 0x820 /* pci express core */ #define BHND_COREID_NPHY 0x821 /* 802.11n 2x2 phy core */ #define BHND_COREID_SRAMC 0x822 /* SRAM controller core */ #define BHND_COREID_MINIMAC 0x823 /* MINI MAC/phy core */ #define BHND_COREID_ARM11 0x824 /* ARM 1176 core */ #define BHND_COREID_ARM7S 0x825 /* ARM7tdmi-s core */ #define BHND_COREID_LPPHY 0x826 /* 802.11a/b/g phy core */ #define BHND_COREID_PMU 0x827 /* PMU core */ #define BHND_COREID_SSNPHY 0x828 /* 802.11n single-stream phy core */ #define BHND_COREID_SDIOD 0x829 /* SDIO device core */ #define BHND_COREID_ARMCM3 0x82a /* ARM Cortex M3 core */ #define BHND_COREID_HTPHY 0x82b /* 802.11n 4x4 phy core */ #define BHND_COREID_MIPS74K 0x82c /* mips 74k core */ #define BHND_COREID_GMAC 0x82d /* Gigabit MAC core */ #define BHND_COREID_DMEMC 0x82e /* DDR1/2 memory controller core */ #define BHND_COREID_PCIERC 0x82f /* PCIE Root Complex core */ #define BHND_COREID_OCP 0x830 /* OCP2OCP bridge core */ #define BHND_COREID_SC 0x831 /* shared common core */ #define BHND_COREID_AHB 0x832 /* OCP2AHB bridge core */ #define BHND_COREID_SPIH 0x833 /* SPI host core */ #define BHND_COREID_I2S 0x834 /* I2S core */ #define BHND_COREID_DMEMS 0x835 /* SDR/DDR1 memory controller core */ #define BHND_COREID_UBUS_SHIM 0x837 /* SHIM component in ubus/6362 */ #define BHND_COREID_PCIE2 0x83c /* pci express (gen2) core */ /* ARM/AMBA Core IDs */ #define BHND_COREID_APB_BRIDGE 0x135 /* BP135 AMBA AXI-APB bridge */ #define BHND_COREID_PL301 0x301 /* PL301 AMBA AXI Interconnect */ #define BHND_COREID_EROM 0x366 /* Enumeration ROM */ #define BHND_COREID_OOB_ROUTER 0x367 /* OOB router core ID */ #define BHND_COREID_AXI_UNMAPPED 0xfff /* AXI "Default Slave"; maps all unused address * ranges, returning DECERR on read or write. */ /* Northstar Plus and BCM4706 Core IDs */ #define BHND_COREID_4706_CC 0x500 /* chipcommon core */ #define BHND_COREID_NS_PCIE2 0x501 /* pci express (gen2) core */ #define BHND_COREID_NS_DMA 0x502 /* dma core */ #define BHND_COREID_NS_SDIO 0x503 /* sdio host core */ #define BHND_COREID_NS_USB20H 0x504 /* usb 2.0 host core */ #define BHND_COREID_NS_USB30H 0x505 /* usb 3.0 host core */ #define BHND_COREID_NS_A9JTAG 0x506 /* ARM Cortex A9 JTAG core */ #define BHND_COREID_NS_DDR23_MEMC 0x507 /* DDR2/3 cadence/denali memory controller core () */ #define BHND_COREID_NS_ROM 0x508 /* device ROM core */ #define BHND_COREID_NS_NAND 0x509 /* NAND flash controller core */ #define BHND_COREID_NS_QSPI 0x50a /* QSPI flash controller core */ #define BHND_COREID_NS_CC_B 0x50b /* chipcommon `b' (auxiliary) core */ #define BHND_COREID_4706_SOCRAM 0x50e /* internal memory core */ #define BHND_COREID_IHOST_ARMCA9 0x510 /* ARM Cortex A9 core */ #define BHND_COREID_4706_GMAC_CMN 0x5dc /* Gigabit MAC common core */ #define BHND_COREID_4706_GMAC 0x52d /* Gigabit MAC core */ #define BHND_COREID_AMEMC 0x52e /* DDR1/2 cadence/denali memory controller core */ /* ARM PrimeCell Peripherial IDs. These were derived from inspection of the * PrimeCell-compatible BCM4331 cores, but due to lack of documentation, the * surmised core name/description may be incorrect. */ #define BHND_PRIMEID_EROM 0x364 /* Enumeration ROM's primecell ID */ #define BHND_PRIMEID_SWRAP 0x368 /* PL368 Device Management Interface (Slave) */ #define BHND_PRIMEID_MWRAP 0x369 /* PL369 Device Management Interface (Master) */ /* Core HW Revision Numbers */ #define BHND_HWREV_INVALID 0xFF /* Invalid hardware revision ID */ /* Chip Types */ #define BHND_CHIPTYPE_SIBA 0 /**< siba(4) interconnect */ #define BHND_CHIPTYPE_BCMA 1 /**< bcma(4) interconnect */ #define BHND_CHIPTYPE_UBUS 2 /**< ubus interconnect found in bcm63xx devices */ #define BHND_CHIPTYPE_BCMA_ALT 3 /**< bcma(4) interconnect */ /** Evaluates to true if @p _type uses a BCMA EROM table */ #define BHND_CHIPTYPE_HAS_EROM(_type) \ ((_type) == BHND_CHIPTYPE_BCMA || \ (_type) == BHND_CHIPTYPE_BCMA_ALT || \ (_type) == BHND_CHIPTYPE_UBUS) /* Boardflags */ #define BHND_BFL_BTC2WIRE 0x00000001 /* old 2wire Bluetooth coexistence, OBSOLETE */ #define BHND_BFL_BTCOEX 0x00000001 /* Board supports BTCOEX */ #define BHND_BFL_PACTRL 0x00000002 /* Board has gpio 9 controlling the PA */ #define BHND_BFL_AIRLINEMODE 0x00000004 /* Board implements gpio 13 radio disable indication, UNUSED */ #define BHND_BFL_ADCDIV 0x00000008 /* Board has the rssi ADC divider */ #define BHND_BFL_DIS_256QAM 0x00000008 #define BHND_BFL_ENETROBO 0x00000010 /* Board has robo switch or core */ #define BHND_BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */ #define BHND_BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */ #define BHND_BFL_ENETADM 0x00000080 /* Board has ADMtek switch */ #define BHND_BFL_ENETVLAN 0x00000100 /* Board has VLAN capability */ #define BHND_BFL_LTECOEX 0x00000200 /* Board has LTE coex capability */ #define BHND_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */ #define BHND_BFL_FEM 0x00000800 /* Board supports the Front End Module */ #define BHND_BFL_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */ #define BHND_BFL_HGPA 0x00002000 /* Board has a high gain PA */ #define BHND_BFL_BTC2WIRE_ALTGPIO 0x00004000 /* Board's BTC 2wire is in the alternate gpios OBSLETE */ #define BHND_BFL_ALTIQ 0x00008000 /* Alternate I/Q settings */ #define BHND_BFL_NOPA 0x00010000 /* Board has no PA */ #define BHND_BFL_RSSIINV 0x00020000 /* Board's RSSI uses positive slope(not TSSI) */ #define BHND_BFL_PAREF 0x00040000 /* Board uses the PARef LDO */ #define BHND_BFL_3TSWITCH 0x00080000 /* Board uses a triple throw switch shared with BT */ #define BHND_BFL_PHASESHIFT 0x00100000 /* Board can support phase shifter */ #define BHND_BFL_BUCKBOOST 0x00200000 /* Power topology uses BUCKBOOST */ #define BHND_BFL_FEM_BT 0x00400000 /* Board has FEM and switch to share antenna w/ BT */ #define BHND_BFL_RXCHAIN_OFF_BT 0x00400000 /* one rxchain is to be shut off when BT is active */ #define BHND_BFL_NOCBUCK 0x00800000 /* Power topology doesn't use CBUCK */ #define BHND_BFL_CCKFAVOREVM 0x01000000 /* Favor CCK EVM over spectral mask */ #define BHND_BFL_PALDO 0x02000000 /* Power topology uses PALDO */ #define BHND_BFL_LNLDO2_2P5 0x04000000 /* Select 2.5V as LNLDO2 output voltage */ #define BHND_BFL_FASTPWR 0x08000000 #define BHND_BFL_UCPWRCTL_MININDX 0x08000000 /* Enforce min power index to avoid FEM damage */ #define BHND_BFL_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */ #define BHND_BFL_TRSW_1by2 0x20000000 /* Board has 2 TRSW's in 1by2 designs */ #define BHND_BFL_GAINBOOSTA01 0x20000000 /* 5g Gainboost for core0 and core1 */ #define BHND_BFL_LO_TRSW_R_5GHz 0x40000000 /* In 5G do not throw TRSW to T for clipLO gain */ #define BHND_BFL_ELNA_GAINDEF 0x80000000 /* Backoff InitGain based on elna_2g/5g field * when this flag is set */ #define BHND_BFL_EXTLNA_TX 0x20000000 /* Temp boardflag to indicate to */ /* Boardflags2 */ #define BHND_BFL2_RXBB_INT_REG_DIS 0x00000001 /* Board has an external rxbb regulator */ #define BHND_BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */ #define BHND_BFL2_TXPWRCTRL_EN 0x00000004 /* Board permits enabling TX Power Control */ #define BHND_BFL2_2X4_DIV 0x00000008 /* Board supports the 2X4 diversity switch */ #define BHND_BFL2_5G_PWRGAIN 0x00000010 /* Board supports 5G band power gain */ #define BHND_BFL2_PCIEWAR_OVR 0x00000020 /* Board overrides ASPM and Clkreq settings */ #define BHND_BFL2_CAESERS_BRD 0x00000040 /* Board is Caesers brd (unused by sw) */ #define BHND_BFL2_BTC3WIRE 0x00000080 /* Board support legacy 3 wire or 4 wire */ #define BHND_BFL2_BTCLEGACY 0x00000080 /* Board support legacy 3/4 wire, to replace * BHND_BFL2_BTC3WIRE */ #define BHND_BFL2_SKWRKFEM_BRD 0x00000100 /* 4321mcm93 board uses Skyworks FEM */ #define BHND_BFL2_SPUR_WAR 0x00000200 /* Board has a WAR for clock-harmonic spurs */ #define BHND_BFL2_GPLL_WAR 0x00000400 /* Flag to narrow G-band PLL loop b/w */ #define BHND_BFL2_TRISTATE_LED 0x00000800 /* Tri-state the LED */ #define BHND_BFL2_SINGLEANT_CCK 0x00001000 /* Tx CCK pkts on Ant 0 only */ #define BHND_BFL2_2G_SPUR_WAR 0x00002000 /* WAR to reduce and avoid clock-harmonic spurs in 2G */ #define BHND_BFL2_BPHY_ALL_TXCORES 0x00004000 /* Transmit bphy frames using all tx cores */ #define BHND_BFL2_FCC_BANDEDGE_WAR 0x00008000 /* Activates WAR to improve FCC bandedge performance */ #define BHND_BFL2_GPLL_WAR2 0x00010000 /* Flag to widen G-band PLL loop b/w */ #define BHND_BFL2_IPALVLSHIFT_3P3 0x00020000 #define BHND_BFL2_INTERNDET_TXIQCAL 0x00040000 /* Use internal envelope detector for TX IQCAL */ #define BHND_BFL2_XTALBUFOUTEN 0x00080000 /* Keep the buffered Xtal output from radio on */ /* Most drivers will turn it off without this flag */ /* to save power. */ #define BHND_BFL2_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are controlled by analog PA ctrl lines */ #define BHND_BFL2_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are controlled by analog PA ctrl lines */ #define BHND_BFL2_ELNACTRL_TRSW_2G 0x00400000 /* AZW4329: 2G gmode_elna_gain controls TR Switch */ #define BHND_BFL2_BT_SHARE_ANT0 0x00800000 /* WLAN/BT share antenna 0 */ #define BHND_BFL2_BT_SHARE_BM_BIT0 0x00800000 /* bit 0 of WLAN/BT shared core bitmap */ #define BHND_BFL2_TEMPSENSE_HIGHER 0x01000000 /* The tempsense threshold can sustain higher value * than programmed. The exact delta is decided by * driver per chip/boardtype. This can be used * when tempsense qualification happens after shipment */ #define BHND_BFL2_BTC3WIREONLY 0x02000000 /* standard 3 wire btc only. 4 wire not supported */ #define BHND_BFL2_PWR_NOMINAL 0x04000000 /* 0: power reduction on, 1: no power reduction */ #define BHND_BFL2_EXTLNA_PWRSAVE 0x08000000 /* boardflag to enable ucode to apply power save * ucode control of eLNA during Tx */ #define BHND_BFL2_4313_RADIOREG 0x10000000 /* board rework */ #define BHND_BFL2_DYNAMIC_VMID 0x10000000 /* boardflag to enable dynamic Vmid idle TSSI CAL */ #define BHND_BFL2_SDR_EN 0x20000000 /* SDR enabled or disabled */ #define BHND_BFL2_LNA1BYPFORTR2G 0x40000000 /* acphy, enable lna1 bypass for clip gain, 2g */ #define BHND_BFL2_LNA1BYPFORTR5G 0x80000000 /* acphy, enable lna1 bypass for clip gain, 5g */ /* SROM 11 - 11ac boardflag definitions */ #define BHND_BFL_SROM11_BTCOEX 0x00000001 /* Board supports BTCOEX */ #define BHND_BFL_SROM11_WLAN_BT_SH_XTL 0x00000002 /* bluetooth and wlan share same crystal */ #define BHND_BFL_SROM11_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */ #define BHND_BFL_SROM11_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */ #define BHND_BFL_SROM11_GAINBOOSTA01 0x20000000 /* 5g Gainboost for core0 and core1 */ #define BHND_BFL2_SROM11_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */ #define BHND_BFL2_SROM11_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are ctrl-ed by analog PA ctrl lines */ #define BHND_BFL2_SROM11_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are ctrl-ed by analog PA ctrl lines */ /* Boardflags3 */ #define BHND_BFL3_FEMCTRL_SUB 0x00000007 /* acphy, subrevs of femctrl on top of srom_femctrl */ #define BHND_BFL3_RCAL_WAR 0x00000008 /* acphy, rcal war active on this board (4335a0) */ #define BHND_BFL3_TXGAINTBLID 0x00000070 /* acphy, txgain table id */ #define BHND_BFL3_TXGAINTBLID_SHIFT 0x4 /* acphy, txgain table id shift bit */ #define BHND_BFL3_TSSI_DIV_WAR 0x00000080 /* acphy, Separate paparam for 20/40/80 */ #define BHND_BFL3_TSSI_DIV_WAR_SHIFT 0x7 /* acphy, Separate paparam for 20/40/80 shift bit */ #define BHND_BFL3_FEMTBL_FROM_NVRAM 0x00000100 /* acphy, femctrl table is read from nvram */ #define BHND_BFL3_FEMTBL_FROM_NVRAM_SHIFT 0x8 /* acphy, femctrl table is read from nvram */ #define BHND_BFL3_AGC_CFG_2G 0x00000200 /* acphy, gain control configuration for 2G */ #define BHND_BFL3_AGC_CFG_5G 0x00000400 /* acphy, gain control configuration for 5G */ #define BHND_BFL3_PPR_BIT_EXT 0x00000800 /* acphy, bit position for 1bit extension for ppr */ #define BHND_BFL3_PPR_BIT_EXT_SHIFT 11 /* acphy, bit shift for 1bit extension for ppr */ #define BHND_BFL3_BBPLL_SPR_MODE_DIS 0x00001000 /* acphy, disables bbpll spur modes */ #define BHND_BFL3_RCAL_OTP_VAL_EN 0x00002000 /* acphy, to read rcal_trim value from otp */ #define BHND_BFL3_2GTXGAINTBL_BLANK 0x00004000 /* acphy, blank the first X ticks of 2g gaintbl */ #define BHND_BFL3_2GTXGAINTBL_BLANK_SHIFT 14 /* acphy, blank the first X ticks of 2g gaintbl */ #define BHND_BFL3_5GTXGAINTBL_BLANK 0x00008000 /* acphy, blank the first X ticks of 5g gaintbl */ #define BHND_BFL3_5GTXGAINTBL_BLANK_SHIFT 15 /* acphy, blank the first X ticks of 5g gaintbl */ #define BHND_BFL3_BT_SHARE_BM_BIT1 0x40000000 /* bit 1 of WLAN/BT shared core bitmap */ #define BHND_BFL3_PHASETRACK_MAX_ALPHABETA 0x00010000 /* acphy, to max out alpha,beta to 511 */ #define BHND_BFL3_PHASETRACK_MAX_ALPHABETA_SHIFT 16 /* acphy, to max out alpha,beta to 511 */ #define BHND_BFL3_BT_SHARE_BM_BIT1 0x40000000 /* bit 1 of WLAN/BT shared core bitmap */ #define BHND_BFL3_EN_NONBRCM_TXBF 0x10000000 /* acphy, enable non-brcm TXBF */ #define BHND_BFL3_EN_P2PLINK_TXBF 0x20000000 /* acphy, enable TXBF in p2p links */ /* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */ #define BHND_GPIO_BOARD_BTC3W_IN 0x850 /* bit 4 is RF_ACTIVE, bit 6 is STATUS, bit 11 is PRI */ #define BHND_GPIO_BOARD_BTC3W_OUT 0x020 /* bit 5 is TX_CONF */ #define BHND_GPIO_BOARD_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistence Input */ #define BHND_GPIO_BOARD_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistence Out */ #define BHND_GPIO_BOARD_BTC_IN 0x080 /* bit 7 is BT Coexistence Input */ #define BHND_GPIO_BOARD_BTC_OUT 0x100 /* bit 8 is BT Coexistence Out */ #define BHND_GPIO_BOARD_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */ #define BHND_GPIO_BOARD_12 0x1000 /* gpio 12 */ #define BHND_GPIO_BOARD_13 0x2000 /* gpio 13 */ #define BHND_GPIO_BOARD_BTC4_IN 0x0800 /* gpio 11, coex4, in */ #define BHND_GPIO_BOARD_BTC4_BT 0x2000 /* gpio 12, coex4, bt active */ #define BHND_GPIO_BOARD_BTC4_STAT 0x4000 /* gpio 14, coex4, status */ #define BHND_GPIO_BOARD_BTC4_WLAN 0x8000 /* gpio 15, coex4, wlan active */ #define BHND_GPIO_BOARD_1_WLAN_PWR 0x02 /* throttle WLAN power on X21 board */ #define BHND_GPIO_BOARD_3_WLAN_PWR 0x08 /* throttle WLAN power on X28 board */ #define BHND_GPIO_BOARD_4_WLAN_PWR 0x10 /* throttle WLAN power on X19 board */ #define BHND_GPIO_BTC4W_OUT_4312 0x010 /* bit 4 is BT_IODISABLE */ #define BHND_GPIO_BTC4W_OUT_43224 0x020 /* bit 5 is BT_IODISABLE */ #define BHND_GPIO_BTC4W_OUT_43224_SHARED 0x0e0 /* bit 5 is BT_IODISABLE */ #define BHND_GPIO_BTC4W_OUT_43225 0x0e0 /* bit 5 BT_IODISABLE, bit 6 SW_BT, bit 7 SW_WL */ #define BHND_GPIO_BTC4W_OUT_43421 0x020 /* bit 5 is BT_IODISABLE */ #define BHND_GPIO_BTC4W_OUT_4313 0x060 /* bit 5 SW_BT, bit 6 SW_WL */ #define BHND_GPIO_BTC4W_OUT_4331_SHARED 0x010 /* GPIO 4 */ -/* Power Control Defines */ -#define BHND_CHIPC_PLL_DELAY 150 /* us pll on delay */ -#define BHND_CHIPC_FREF_DELAY 200 /* us fref change delay */ -#define BHND_CHIPC_MIN_SLOW_CLK 32 /* us Slow clock period */ -#define BHND_CHIPC_XTAL_ON_DELAY 1000 /* us crystal power-on delay */ - /* Board Types */ #define BHND_BOARD_BU4710 0x0400 #define BHND_BOARD_VSIM4710 0x0401 #define BHND_BOARD_QT4710 0x0402 #define BHND_BOARD_BU4309 0x040a #define BHND_BOARD_BCM94309CB 0x040b #define BHND_BOARD_BCM94309MP 0x040c #define BHND_BOARD_BCM4309AP 0x040d #define BHND_BOARD_BCM94302MP 0x040e #define BHND_BOARD_BU4306 0x0416 #define BHND_BOARD_BCM94306CB 0x0417 #define BHND_BOARD_BCM94306MP 0x0418 #define BHND_BOARD_BCM94710D 0x041a #define BHND_BOARD_BCM94710R1 0x041b #define BHND_BOARD_BCM94710R4 0x041c #define BHND_BOARD_BCM94710AP 0x041d #define BHND_BOARD_BU2050 0x041f #define BHND_BOARD_BCM94309G 0x0421 #define BHND_BOARD_BU4704 0x0423 #define BHND_BOARD_BU4702 0x0424 #define BHND_BOARD_BCM94306PC 0x0425 /* pcmcia 3.3v 4306 card */ #define BHND_BOARD_BCM94702MN 0x0428 /* BCM4702 1U CompactPCI Board */ #define BHND_BOARD_BCM94702CPCI 0x0429 /* BCM4702 with BCM95380 VLAN Router */ #define BHND_BOARD_BCM95380RR 0x042a /* cb4306 with SiGe PA */ #define BHND_BOARD_BCM94306CBSG 0x042b /* cb4306 with SiGe PA */ #define BHND_BOARD_PCSG94306 0x042d /* bu4704 with sdram */ #define BHND_BOARD_BU4704SD 0x042e /* Dual 11a/11g Router */ #define BHND_BOARD_BCM94704AGR 0x042f /* 11a-only minipci */ #define BHND_BOARD_BCM94308MP 0x0430 #define BHND_BOARD_BU4712 0x0444 #define BHND_BOARD_BU4712SD 0x045d #define BHND_BOARD_BU4712L 0x045f /* BCM4712 boards */ #define BHND_BOARD_BCM94712AP 0x0445 #define BHND_BOARD_BCM94712P 0x0446 /* BCM4318 boards */ #define BHND_BOARD_BU4318 0x0447 #define BHND_BOARD_CB4318 0x0448 #define BHND_BOARD_MPG4318 0x0449 #define BHND_BOARD_MP4318 0x044a #define BHND_BOARD_SD4318 0x044b /* BCM4313 boards */ #define BHND_BOARD_BCM94313BU 0x050f #define BHND_BOARD_BCM94313HM 0x0510 #define BHND_BOARD_BCM94313EPA 0x0511 #define BHND_BOARD_BCM94313HMG 0x051C /* BCM63XX boards */ #define BHND_BOARD_BCM96338 0x6338 #define BHND_BOARD_BCM96348 0x6348 #define BHND_BOARD_BCM96358 0x6358 #define BHND_BOARD_BCM96368 0x6368 /* Another mp4306 with SiGe */ #define BHND_BOARD_BCM94306P 0x044c /* mp4303 */ #define BHND_BOARD_BCM94303MP 0x044e /* mpsgh4306 */ #define BHND_BOARD_BCM94306MPSGH 0x044f /* BRCM 4306 w/ Front End Modules */ #define BHND_BOARD_BCM94306MPM 0x0450 #define BHND_BOARD_BCM94306MPL 0x0453 /* 4712agr */ #define BHND_BOARD_BCM94712AGR 0x0451 /* pcmcia 4303 */ #define BHND_BOARD_PC4303 0x0454 /* 5350K */ #define BHND_BOARD_BCM95350K 0x0455 /* 5350R */ #define BHND_BOARD_BCM95350R 0x0456 /* 4306mplna */ #define BHND_BOARD_BCM94306MPLNA 0x0457 /* 4320 boards */ #define BHND_BOARD_BU4320 0x0458 #define BHND_BOARD_BU4320S 0x0459 #define BHND_BOARD_BCM94320PH 0x045a /* 4306mph */ #define BHND_BOARD_BCM94306MPH 0x045b /* 4306pciv */ #define BHND_BOARD_BCM94306PCIV 0x045c #define BHND_BOARD_BU4712SD 0x045d #define BHND_BOARD_BCM94320PFLSH 0x045e #define BHND_BOARD_BU4712L 0x045f #define BHND_BOARD_BCM94712LGR 0x0460 #define BHND_BOARD_BCM94320R 0x0461 #define BHND_BOARD_BU5352 0x0462 #define BHND_BOARD_BCM94318MPGH 0x0463 #define BHND_BOARD_BU4311 0x0464 #define BHND_BOARD_BCM94311MC 0x0465 #define BHND_BOARD_BCM94311MCAG 0x0466 #define BHND_BOARD_BCM95352GR 0x0467 /* bcm95351agr */ #define BHND_BOARD_BCM95351AGR 0x0470 /* bcm94704mpcb */ #define BHND_BOARD_BCM94704MPCB 0x0472 /* 4785 boards */ #define BHND_BOARD_BU4785 0x0478 /* 4321 boards */ #define BHND_BOARD_BCM4321BU 0x046b #define BHND_BOARD_BCM4321BUE 0x047c #define BHND_BOARD_BCM4321MP 0x046c #define BHND_BOARD_BCM4321CB2 0x046d #define BHND_BOARD_BCM4321CB2_AG 0x0066 #define BHND_BOARD_BCM4321MC 0x046e /* 4328 boards */ #define BHND_BOARD_BU4328 0x0481 #define BHND_BOARD_BCM4328SDG 0x0482 #define BHND_BOARD_BCM4328SDAG 0x0483 #define BHND_BOARD_BCM4328UG 0x0484 #define BHND_BOARD_BCM4328UAG 0x0485 #define BHND_BOARD_BCM4328PC 0x0486 #define BHND_BOARD_BCM4328CF 0x0487 /* 4325 boards */ #define BHND_BOARD_BCM94325DEVBU 0x0490 #define BHND_BOARD_BCM94325BGABU 0x0491 #define BHND_BOARD_BCM94325SDGWB 0x0492 #define BHND_BOARD_BCM94325SDGMDL 0x04aa #define BHND_BOARD_BCM94325SDGMDL2 0x04c6 #define BHND_BOARD_BCM94325SDGMDL3 0x04c9 #define BHND_BOARD_BCM94325SDABGWBA 0x04e1 /* 4322 boards */ #define BHND_BOARD_BCM94322MC 0x04a4 #define BHND_BOARD_BCM94322USB 0x04a8 /* dualband */ #define BHND_BOARD_BCM94322HM 0x04b0 #define BHND_BOARD_BCM94322USB2D 0x04bf /* single band discrete front end */ /* 4312 boards */ #define BHND_BOARD_BCM4312MCGSG 0x04b5 /* 4315 boards */ #define BHND_BOARD_BCM94315DEVBU 0x04c2 #define BHND_BOARD_BCM94315USBGP 0x04c7 #define BHND_BOARD_BCM94315BGABU 0x04ca #define BHND_BOARD_BCM94315USBGP41 0x04cb /* 4319 boards */ #define BHND_BOARD_BCM94319DEVBU 0X04e5 #define BHND_BOARD_BCM94319USB 0X04e6 #define BHND_BOARD_BCM94319SD 0X04e7 /* 4716 boards */ #define BHND_BOARD_BCM94716NR2 0x04cd /* 4319 boards */ #define BHND_BOARD_BCM94319DEVBU 0X04e5 #define BHND_BOARD_BCM94319USBNP4L 0X04e6 #define BHND_BOARD_BCM94319WLUSBN4L 0X04e7 #define BHND_BOARD_BCM94319SDG 0X04ea #define BHND_BOARD_BCM94319LCUSBSDN4L 0X04eb #define BHND_BOARD_BCM94319USBB 0x04ee #define BHND_BOARD_BCM94319LCSDN4L 0X0507 #define BHND_BOARD_BCM94319LSUSBN4L 0X0508 #define BHND_BOARD_BCM94319SDNA4L 0X0517 #define BHND_BOARD_BCM94319SDELNA4L 0X0518 #define BHND_BOARD_BCM94319SDELNA6L 0X0539 #define BHND_BOARD_BCM94319ARCADYAN 0X0546 #define BHND_BOARD_BCM94319WINDSOR 0x0561 #define BHND_BOARD_BCM94319MLAP 0x0562 #define BHND_BOARD_BCM94319SDNA 0x058b #define BHND_BOARD_BCM94319BHEMU3 0x0563 #define BHND_BOARD_BCM94319SDHMB 0x058c #define BHND_BOARD_BCM94319SDBREF 0x05a1 #define BHND_BOARD_BCM94319USBSDB 0x05a2 /* 4329 boards */ #define BHND_BOARD_BCM94329AGB 0X04b9 #define BHND_BOARD_BCM94329TDKMDL1 0X04ba #define BHND_BOARD_BCM94329TDKMDL11 0X04fc #define BHND_BOARD_BCM94329OLYMPICN18 0X04fd #define BHND_BOARD_BCM94329OLYMPICN90 0X04fe #define BHND_BOARD_BCM94329OLYMPICN90U 0X050c #define BHND_BOARD_BCM94329OLYMPICN90M 0X050b #define BHND_BOARD_BCM94329AGBF 0X04ff #define BHND_BOARD_BCM94329OLYMPICX17 0X0504 #define BHND_BOARD_BCM94329OLYMPICX17M 0X050a #define BHND_BOARD_BCM94329OLYMPICX17U 0X0509 #define BHND_BOARD_BCM94329OLYMPICUNO 0X0564 #define BHND_BOARD_BCM94329MOTOROLA 0X0565 #define BHND_BOARD_BCM94329OLYMPICLOCO 0X0568 /* 4336 SDIO board types */ #define BHND_BOARD_BCM94336SD_WLBGABU 0x0511 #define BHND_BOARD_BCM94336SD_WLBGAREF 0x0519 #define BHND_BOARD_BCM94336SDGP 0x0538 #define BHND_BOARD_BCM94336SDG 0x0519 #define BHND_BOARD_BCM94336SDGN 0x0538 #define BHND_BOARD_BCM94336SDGFC 0x056B /* 4330 SDIO board types */ #define BHND_BOARD_BCM94330SDG 0x0528 #define BHND_BOARD_BCM94330SD_FCBGABU 0x052e #define BHND_BOARD_BCM94330SD_WLBGABU 0x052f #define BHND_BOARD_BCM94330SD_FCBGA 0x0530 #define BHND_BOARD_BCM94330FCSDAGB 0x0532 #define BHND_BOARD_BCM94330OLYMPICAMG 0x0549 #define BHND_BOARD_BCM94330OLYMPICAMGEPA 0x054F #define BHND_BOARD_BCM94330OLYMPICUNO3 0x0551 #define BHND_BOARD_BCM94330WLSDAGB 0x0547 #define BHND_BOARD_BCM94330CSPSDAGBB 0x054A /* 43224 boards */ #define BHND_BOARD_BCM943224X21 0x056e #define BHND_BOARD_BCM943224X21_FCC 0x00d1 #define BHND_BOARD_BCM943224X21B 0x00e9 #define BHND_BOARD_BCM943224M93 0x008b #define BHND_BOARD_BCM943224M93A 0x0090 #define BHND_BOARD_BCM943224X16 0x0093 #define BHND_BOARD_BCM94322X9 0x008d #define BHND_BOARD_BCM94322M35e 0x008e /* 43228 Boards */ #define BHND_BOARD_BCM943228BU8 0x0540 #define BHND_BOARD_BCM943228BU9 0x0541 #define BHND_BOARD_BCM943228BU 0x0542 #define BHND_BOARD_BCM943227HM4L 0x0543 #define BHND_BOARD_BCM943227HMB 0x0544 #define BHND_BOARD_BCM943228HM4L 0x0545 #define BHND_BOARD_BCM943228SD 0x0573 /* 43239 Boards */ #define BHND_BOARD_BCM943239MOD 0x05ac #define BHND_BOARD_BCM943239REF 0x05aa /* 4331 boards */ #define BHND_BOARD_BCM94331X19 0x00D6 /* X19B */ #define BHND_BOARD_BCM94331X28 0x00E4 /* X28 */ #define BHND_BOARD_BCM94331X28B 0x010E /* X28B */ #define BHND_BOARD_BCM94331PCIEBT3Ax BCM94331X28 #define BHND_BOARD_BCM94331X12_2G 0x00EC /* X12 2G */ #define BHND_BOARD_BCM94331X12_5G 0x00ED /* X12 5G */ #define BHND_BOARD_BCM94331X29B 0x00EF /* X29B */ #define BHND_BOARD_BCM94331X29D 0x010F /* X29D */ #define BHND_BOARD_BCM94331CSAX BCM94331X29B #define BHND_BOARD_BCM94331X19C 0x00F5 /* X19C */ #define BHND_BOARD_BCM94331X33 0x00F4 /* X33 */ #define BHND_BOARD_BCM94331BU 0x0523 #define BHND_BOARD_BCM94331S9BU 0x0524 #define BHND_BOARD_BCM94331MC 0x0525 #define BHND_BOARD_BCM94331MCI 0x0526 #define BHND_BOARD_BCM94331PCIEBT4 0x0527 #define BHND_BOARD_BCM94331HM 0x0574 #define BHND_BOARD_BCM94331PCIEDUAL 0x059B #define BHND_BOARD_BCM94331MCH5 0x05A9 #define BHND_BOARD_BCM94331CS 0x05C6 #define BHND_BOARD_BCM94331CD 0x05DA /* 4314 Boards */ #define BHND_BOARD_BCM94314BU 0x05b1 /* 53572 Boards */ #define BHND_BOARD_BCM953572BU 0x058D #define BHND_BOARD_BCM953572NR2 0x058E #define BHND_BOARD_BCM947188NR2 0x058F #define BHND_BOARD_BCM953572SDRNR2 0x0590 /* 43236 boards */ #define BHND_BOARD_BCM943236OLYMPICSULLEY 0x594 #define BHND_BOARD_BCM943236PREPROTOBLU2O3 0x5b9 #define BHND_BOARD_BCM943236USBELNA 0x5f8 /* 4314 Boards */ #define BHND_BOARD_BCM94314BUSDIO 0x05c8 #define BHND_BOARD_BCM94314BGABU 0x05c9 #define BHND_BOARD_BCM94314HMEPA 0x05ca #define BHND_BOARD_BCM94314HMEPABK 0x05cb #define BHND_BOARD_BCM94314SUHMEPA 0x05cc #define BHND_BOARD_BCM94314SUHM 0x05cd #define BHND_BOARD_BCM94314HM 0x05d1 /* 4334 Boards */ #define BHND_BOARD_BCM94334FCAGBI 0x05df #define BHND_BOARD_BCM94334WLAGBI 0x05dd /* 4335 Boards */ #define BHND_BOARD_BCM94335X52 0x0114 /* 4345 Boards */ #define BHND_BOARD_BCM94345 0x0687 /* 4360 Boards */ #define BHND_BOARD_BCM94360X52C 0X0117 #define BHND_BOARD_BCM94360X52D 0X0137 #define BHND_BOARD_BCM94360X29C 0X0112 #define BHND_BOARD_BCM94360X29CP2 0X0134 #define BHND_BOARD_BCM94360X51 0x0111 #define BHND_BOARD_BCM94360X51P2 0x0129 #define BHND_BOARD_BCM94360X51A 0x0135 #define BHND_BOARD_BCM94360X51B 0x0136 #define BHND_BOARD_BCM94360CS 0x061B #define BHND_BOARD_BCM94360J28_D11AC2G 0x0c00 #define BHND_BOARD_BCM94360J28_D11AC5G 0x0c01 #define BHND_BOARD_BCM94360USBH5_D11AC5G 0x06aa /* 4350 Boards */ #define BHND_BOARD_BCM94350X52B 0X0116 #define BHND_BOARD_BCM94350X14 0X0131 /* 43217 Boards */ #define BHND_BOARD_BCM943217BU 0x05d5 #define BHND_BOARD_BCM943217HM2L 0x05d6 #define BHND_BOARD_BCM943217HMITR2L 0x05d7 /* 43142 Boards */ #define BHND_BOARD_BCM943142HM 0x05e0 /* 43341 Boards */ #define BHND_BOARD_BCM943341WLABGS 0x062d /* 43342 Boards */ #define BHND_BOARD_BCM943342FCAGBI 0x0641 /* 43602 Boards, unclear yet what boards will be created. */ #define BHND_BOARD_BCM943602RSVD1 0x06a5 #define BHND_BOARD_BCM943602RSVD2 0x06a6 #define BHND_BOARD_BCM943602X87 0X0133 #define BHND_BOARD_BCM943602X238 0X0132 /* 4354 board types */ #define BHND_BOARD_BCM94354WLSAGBI 0x06db #define BHND_BOARD_BCM94354Z 0x0707 /* # of GPIO pins */ #define BHND_BCM43XX_GPIO_NUMPINS 32 /* These values are used by dhd USB host driver. */ #define BHND_USB_RDL_RAM_BASE_4319 0x60000000 #define BHND_USB_RDL_RAM_BASE_4329 0x60000000 #define BHND_USB_RDL_RAM_SIZE_4319 0x48000 #define BHND_USB_RDL_RAM_SIZE_4329 0x48000 #define BHND_USB_RDL_RAM_SIZE_43236 0x70000 #define BHND_USB_RDL_RAM_BASE_43236 0x60000000 #define BHND_USB_RDL_RAM_SIZE_4328 0x60000 #define BHND_USB_RDL_RAM_BASE_4328 0x80000000 #define BHND_USB_RDL_RAM_SIZE_4322 0x60000 #define BHND_USB_RDL_RAM_BASE_4322 0x60000000 #define BHND_USB_RDL_RAM_SIZE_4360 0xA0000 #define BHND_USB_RDL_RAM_BASE_4360 0x60000000 #define BHND_USB_RDL_RAM_SIZE_43242 0x90000 #define BHND_USB_RDL_RAM_BASE_43242 0x60000000 #define BHND_USB_RDL_RAM_SIZE_43143 0x70000 #define BHND_USB_RDL_RAM_BASE_43143 0x60000000 #define BHND_USB_RDL_RAM_SIZE_4350 0xC0000 #define BHND_USB_RDL_RAM_BASE_4350 0x180800 /* generic defs for nvram "muxenab" bits * Note: these differ for 4335a0. refer bcmchipc.h for specific mux options. */ #define BHND_NVRAM_MUXENAB_UART 0x00000001 #define BHND_NVRAM_MUXENAB_GPIO 0x00000002 #define BHND_NVRAM_MUXENAB_ERCX 0x00000004 /* External Radio BT coex */ #define BHND_NVRAM_MUXENAB_JTAG 0x00000008 #define BHND_NVRAM_MUXENAB_HOST_WAKE 0x00000010 /* configure GPIO for SDIO host_wake */ #define BHND_NVRAM_MUXENAB_I2S_EN 0x00000020 #define BHND_NVRAM_MUXENAB_I2S_MASTER 0x00000040 #define BHND_NVRAM_MUXENAB_I2S_FULL 0x00000080 #define BHND_NVRAM_MUXENAB_SFLASH 0x00000100 #define BHND_NVRAM_MUXENAB_RFSWCTRL0 0x00000200 #define BHND_NVRAM_MUXENAB_RFSWCTRL1 0x00000400 #define BHND_NVRAM_MUXENAB_RFSWCTRL2 0x00000800 #define BHND_NVRAM_MUXENAB_SECI 0x00001000 #define BHND_NVRAM_MUXENAB_BT_LEGACY 0x00002000 #define BHND_NVRAM_MUXENAB_HOST_WAKE1 0x00004000 /* configure alternative GPIO for SDIO host_wake */ /* Boot flags */ #define BHND_BOOTFLAG_FLASH_KERNEL_NFLASH 0x00000001 #define BHND_BOOTFLAG_FLASH_BOOT_NFLASH 0x00000002 #endif /* _BHND_BHND_IDS_H_ */ Index: head/sys/dev/bhnd/bhnd_subr.c =================================================================== --- head/sys/dev/bhnd/bhnd_subr.c (revision 304869) +++ head/sys/dev/bhnd/bhnd_subr.c (revision 304870) @@ -1,1460 +1,1462 @@ /*- * Copyright (c) 2015 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include "nvram/bhnd_nvram.h" #include "bhnd_chipc_if.h" #include "bhnd_nvram_if.h" #include "bhnd_nvram_map.h" #include "bhndreg.h" #include "bhndvar.h" /* BHND core device description table. */ static const struct bhnd_core_desc { uint16_t vendor; uint16_t device; bhnd_devclass_t class; const char *desc; } bhnd_core_descs[] = { #define BHND_CDESC(_mfg, _cid, _cls, _desc) \ { BHND_MFGID_ ## _mfg, BHND_COREID_ ## _cid, \ BHND_DEVCLASS_ ## _cls, _desc } BHND_CDESC(BCM, CC, CC, "ChipCommon I/O Controller"), BHND_CDESC(BCM, ILINE20, OTHER, "iLine20 HPNA"), BHND_CDESC(BCM, SRAM, RAM, "SRAM"), BHND_CDESC(BCM, SDRAM, RAM, "SDRAM"), BHND_CDESC(BCM, PCI, PCI, "PCI Bridge"), BHND_CDESC(BCM, MIPS, CPU, "MIPS Core"), BHND_CDESC(BCM, ENET, ENET_MAC, "Fast Ethernet MAC"), BHND_CDESC(BCM, CODEC, OTHER, "V.90 Modem Codec"), BHND_CDESC(BCM, USB, OTHER, "USB 1.1 Device/Host Controller"), BHND_CDESC(BCM, ADSL, OTHER, "ADSL Core"), BHND_CDESC(BCM, ILINE100, OTHER, "iLine100 HPNA"), BHND_CDESC(BCM, IPSEC, OTHER, "IPsec Accelerator"), BHND_CDESC(BCM, UTOPIA, OTHER, "UTOPIA ATM Core"), BHND_CDESC(BCM, PCMCIA, PCCARD, "PCMCIA Bridge"), BHND_CDESC(BCM, SOCRAM, RAM, "Internal Memory"), BHND_CDESC(BCM, MEMC, MEMC, "MEMC SDRAM Controller"), BHND_CDESC(BCM, OFDM, OTHER, "OFDM PHY"), BHND_CDESC(BCM, EXTIF, OTHER, "External Interface"), BHND_CDESC(BCM, D11, WLAN, "802.11 MAC/PHY/Radio"), BHND_CDESC(BCM, APHY, WLAN_PHY, "802.11a PHY"), BHND_CDESC(BCM, BPHY, WLAN_PHY, "802.11b PHY"), BHND_CDESC(BCM, GPHY, WLAN_PHY, "802.11g PHY"), BHND_CDESC(BCM, MIPS33, CPU, "MIPS3302 Core"), BHND_CDESC(BCM, USB11H, OTHER, "USB 1.1 Host Controller"), BHND_CDESC(BCM, USB11D, OTHER, "USB 1.1 Device Core"), BHND_CDESC(BCM, USB20H, OTHER, "USB 2.0 Host Controller"), BHND_CDESC(BCM, USB20D, OTHER, "USB 2.0 Device Core"), BHND_CDESC(BCM, SDIOH, OTHER, "SDIO Host Controller"), BHND_CDESC(BCM, ROBO, OTHER, "RoboSwitch"), BHND_CDESC(BCM, ATA100, OTHER, "Parallel ATA Controller"), BHND_CDESC(BCM, SATAXOR, OTHER, "SATA DMA/XOR Controller"), BHND_CDESC(BCM, GIGETH, ENET_MAC, "Gigabit Ethernet MAC"), BHND_CDESC(BCM, PCIE, PCIE, "PCIe Bridge"), BHND_CDESC(BCM, NPHY, WLAN_PHY, "802.11n 2x2 PHY"), BHND_CDESC(BCM, SRAMC, MEMC, "SRAM Controller"), BHND_CDESC(BCM, MINIMAC, OTHER, "MINI MAC/PHY"), BHND_CDESC(BCM, ARM11, CPU, "ARM1176 CPU"), BHND_CDESC(BCM, ARM7S, CPU, "ARM7TDMI-S CPU"), BHND_CDESC(BCM, LPPHY, WLAN_PHY, "802.11a/b/g PHY"), BHND_CDESC(BCM, PMU, PMU, "PMU"), BHND_CDESC(BCM, SSNPHY, WLAN_PHY, "802.11n Single-Stream PHY"), BHND_CDESC(BCM, SDIOD, OTHER, "SDIO Device Core"), BHND_CDESC(BCM, ARMCM3, CPU, "ARM Cortex-M3 CPU"), BHND_CDESC(BCM, HTPHY, WLAN_PHY, "802.11n 4x4 PHY"), BHND_CDESC(MIPS,MIPS74K, CPU, "MIPS74k CPU"), BHND_CDESC(BCM, GMAC, ENET_MAC, "Gigabit MAC core"), BHND_CDESC(BCM, DMEMC, MEMC, "DDR1/DDR2 Memory Controller"), BHND_CDESC(BCM, PCIERC, OTHER, "PCIe Root Complex"), BHND_CDESC(BCM, OCP, SOC_BRIDGE, "OCP to OCP Bridge"), BHND_CDESC(BCM, SC, OTHER, "Shared Common Core"), BHND_CDESC(BCM, AHB, SOC_BRIDGE, "OCP to AHB Bridge"), BHND_CDESC(BCM, SPIH, OTHER, "SPI Host Controller"), BHND_CDESC(BCM, I2S, OTHER, "I2S Digital Audio Interface"), BHND_CDESC(BCM, DMEMS, MEMC, "SDR/DDR1 Memory Controller"), BHND_CDESC(BCM, UBUS_SHIM, OTHER, "BCM6362/UBUS WLAN SHIM"), BHND_CDESC(BCM, PCIE2, PCIE, "PCIe Bridge (Gen2)"), BHND_CDESC(ARM, APB_BRIDGE, SOC_BRIDGE, "BP135 AMBA3 AXI to APB Bridge"), BHND_CDESC(ARM, PL301, SOC_ROUTER, "PL301 AMBA3 Interconnect"), BHND_CDESC(ARM, EROM, EROM, "PL366 Device Enumeration ROM"), BHND_CDESC(ARM, OOB_ROUTER, OTHER, "PL367 OOB Interrupt Router"), BHND_CDESC(ARM, AXI_UNMAPPED, OTHER, "Unmapped Address Ranges"), BHND_CDESC(BCM, 4706_CC, CC, "ChipCommon I/O Controller"), BHND_CDESC(BCM, NS_PCIE2, PCIE, "PCIe Bridge (Gen2)"), BHND_CDESC(BCM, NS_DMA, OTHER, "DMA engine"), BHND_CDESC(BCM, NS_SDIO, OTHER, "SDIO 3.0 Host Controller"), BHND_CDESC(BCM, NS_USB20H, OTHER, "USB 2.0 Host Controller"), BHND_CDESC(BCM, NS_USB30H, OTHER, "USB 3.0 Host Controller"), BHND_CDESC(BCM, NS_A9JTAG, OTHER, "ARM Cortex A9 JTAG Interface"), BHND_CDESC(BCM, NS_DDR23_MEMC, MEMC, "Denali DDR2/DD3 Memory Controller"), BHND_CDESC(BCM, NS_ROM, NVRAM, "System ROM"), BHND_CDESC(BCM, NS_NAND, NVRAM, "NAND Flash Controller"), BHND_CDESC(BCM, NS_QSPI, NVRAM, "QSPI Flash Controller"), BHND_CDESC(BCM, NS_CC_B, CC_B, "ChipCommon B Auxiliary I/O Controller"), BHND_CDESC(BCM, 4706_SOCRAM, RAM, "Internal Memory"), BHND_CDESC(BCM, IHOST_ARMCA9, CPU, "ARM Cortex A9 CPU"), BHND_CDESC(BCM, 4706_GMAC_CMN, ENET, "Gigabit MAC (Common)"), BHND_CDESC(BCM, 4706_GMAC, ENET_MAC, "Gigabit MAC"), BHND_CDESC(BCM, AMEMC, MEMC, "Denali DDR1/DDR2 Memory Controller"), #undef BHND_CDESC /* Derived from inspection of the BCM4331 cores that provide PrimeCell * IDs. Due to lack of documentation, the surmised device name/purpose * provided here may be incorrect. */ { BHND_MFGID_ARM, BHND_PRIMEID_EROM, BHND_DEVCLASS_OTHER, "PL364 Device Enumeration ROM" }, { BHND_MFGID_ARM, BHND_PRIMEID_SWRAP, BHND_DEVCLASS_OTHER, "PL368 Device Management Interface" }, { BHND_MFGID_ARM, BHND_PRIMEID_MWRAP, BHND_DEVCLASS_OTHER, "PL369 Device Management Interface" }, { 0, 0, 0, NULL } }; /** * Return the name for a given JEP106 manufacturer ID. * * @param vendor A JEP106 Manufacturer ID, including the non-standard ARM 4-bit * JEP106 continuation code. */ const char * bhnd_vendor_name(uint16_t vendor) { switch (vendor) { case BHND_MFGID_ARM: return "ARM"; case BHND_MFGID_BCM: return "Broadcom"; case BHND_MFGID_MIPS: return "MIPS"; default: return "unknown"; } } /** * Return the name of a port type. */ const char * bhnd_port_type_name(bhnd_port_type port_type) { switch (port_type) { case BHND_PORT_DEVICE: return ("device"); case BHND_PORT_BRIDGE: return ("bridge"); case BHND_PORT_AGENT: return ("agent"); default: return "unknown"; } } /** * Return the name of an NVRAM source. */ const char * bhnd_nvram_src_name(bhnd_nvram_src nvram_src) { switch (nvram_src) { case BHND_NVRAM_SRC_FLASH: return ("flash"); case BHND_NVRAM_SRC_OTP: return ("OTP"); case BHND_NVRAM_SRC_SPROM: return ("SPROM"); case BHND_NVRAM_SRC_UNKNOWN: return ("none"); default: return ("unknown"); } } static const struct bhnd_core_desc * bhnd_find_core_desc(uint16_t vendor, uint16_t device) { for (u_int i = 0; bhnd_core_descs[i].desc != NULL; i++) { if (bhnd_core_descs[i].vendor != vendor) continue; if (bhnd_core_descs[i].device != device) continue; return (&bhnd_core_descs[i]); } return (NULL); } /** * Return a human-readable name for a BHND core. * * @param vendor The core designer's JEDEC-106 Manufacturer ID * @param device The core identifier. */ const char * bhnd_find_core_name(uint16_t vendor, uint16_t device) { const struct bhnd_core_desc *desc; if ((desc = bhnd_find_core_desc(vendor, device)) == NULL) return ("unknown"); return desc->desc; } /** * Return the device class for a BHND core. * * @param vendor The core designer's JEDEC-106 Manufacturer ID * @param device The core identifier. */ bhnd_devclass_t bhnd_find_core_class(uint16_t vendor, uint16_t device) { const struct bhnd_core_desc *desc; if ((desc = bhnd_find_core_desc(vendor, device)) == NULL) return (BHND_DEVCLASS_OTHER); return desc->class; } /** * Return a human-readable name for a BHND core. * * @param ci The core's info record. */ const char * bhnd_core_name(const struct bhnd_core_info *ci) { return bhnd_find_core_name(ci->vendor, ci->device); } /** * Return the device class for a BHND core. * * @param ci The core's info record. */ bhnd_devclass_t bhnd_core_class(const struct bhnd_core_info *ci) { return bhnd_find_core_class(ci->vendor, ci->device); } /** * Initialize a core info record with data from from a bhnd-attached @p dev. * * @param dev A bhnd device. * @param core The record to be initialized. */ struct bhnd_core_info bhnd_get_core_info(device_t dev) { return (struct bhnd_core_info) { .vendor = bhnd_get_vendor(dev), .device = bhnd_get_device(dev), .hwrev = bhnd_get_hwrev(dev), .core_idx = bhnd_get_core_index(dev), .unit = bhnd_get_core_unit(dev) }; } /** * Find a @p class child device with @p unit on @p dev. * * @param parent The bhnd-compatible bus to be searched. * @param class The device class to match on. * @param unit The core unit number; specify -1 to return the first match * regardless of unit number. * * @retval device_t if a matching child device is found. * @retval NULL if no matching child device is found. */ device_t bhnd_find_child(device_t dev, bhnd_devclass_t class, int unit) { struct bhnd_core_match md = { BHND_MATCH_CORE_CLASS(class), BHND_MATCH_CORE_UNIT(unit) }; if (unit == -1) md.m.match.core_unit = 0; return bhnd_match_child(dev, &md); } /** * Find the first child device on @p dev that matches @p desc. * * @param parent The bhnd-compatible bus to be searched. * @param desc A match descriptor. * * @retval device_t if a matching child device is found. * @retval NULL if no matching child device is found. */ device_t bhnd_match_child(device_t dev, const struct bhnd_core_match *desc) { device_t *devlistp; device_t match; int devcnt; int error; error = device_get_children(dev, &devlistp, &devcnt); if (error != 0) return (NULL); match = NULL; for (int i = 0; i < devcnt; i++) { struct bhnd_core_info ci = bhnd_get_core_info(devlistp[i]); if (bhnd_core_matches(&ci, desc)) { match = devlistp[i]; goto done; } } done: free(devlistp, M_TEMP); return match; } /** * Walk up the bhnd device hierarchy to locate the root device * to which the bhndb bridge is attached. * * This can be used from within bhnd host bridge drivers to locate the * actual upstream host device. * * @param dev A bhnd device. * @param bus_class The expected bus (e.g. "pci") to which the bridge root * should be attached. * * @retval device_t if a matching parent device is found. * @retval NULL @p dev is not attached via a bhndb bus * @retval NULL no parent device is attached via @p bus_class. */ device_t bhnd_find_bridge_root(device_t dev, devclass_t bus_class) { devclass_t bhndb_class; device_t parent; KASSERT(device_get_devclass(device_get_parent(dev)) == bhnd_devclass, ("%s not a bhnd device", device_get_nameunit(dev))); bhndb_class = devclass_find("bhndb"); /* Walk the device tree until we hit a bridge */ parent = dev; while ((parent = device_get_parent(parent)) != NULL) { if (device_get_devclass(parent) == bhndb_class) break; } /* No bridge? */ if (parent == NULL) return (NULL); /* Search for a parent attached to the expected bus class */ while ((parent = device_get_parent(parent)) != NULL) { device_t bus; bus = device_get_parent(parent); if (bus != NULL && device_get_devclass(bus) == bus_class) return (parent); } /* Not found */ return (NULL); } /** * Find the first core in @p cores that matches @p desc. * * @param cores The table to search. * @param num_cores The length of @p cores. * @param desc A match descriptor. * * @retval bhnd_core_info if a matching core is found. * @retval NULL if no matching core is found. */ const struct bhnd_core_info * bhnd_match_core(const struct bhnd_core_info *cores, u_int num_cores, const struct bhnd_core_match *desc) { for (u_int i = 0; i < num_cores; i++) { if (bhnd_core_matches(&cores[i], desc)) return &cores[i]; } return (NULL); } /** * Find the first core in @p cores with the given @p class. * * @param cores The table to search. * @param num_cores The length of @p cores. * @param desc A match descriptor. * * @retval bhnd_core_info if a matching core is found. * @retval NULL if no matching core is found. */ const struct bhnd_core_info * bhnd_find_core(const struct bhnd_core_info *cores, u_int num_cores, bhnd_devclass_t class) { struct bhnd_core_match md = { BHND_MATCH_CORE_CLASS(class) }; return bhnd_match_core(cores, num_cores, &md); } /** * Return true if the @p core matches @p desc. * * @param core A bhnd core descriptor. * @param desc A match descriptor to compare against @p core. * * @retval true if @p core matches @p match * @retval false if @p core does not match @p match. */ bool bhnd_core_matches(const struct bhnd_core_info *core, const struct bhnd_core_match *desc) { if (desc->m.match.core_vendor && desc->core_vendor != core->vendor) return (false); if (desc->m.match.core_id && desc->core_id != core->device) return (false); if (desc->m.match.core_unit && desc->core_unit != core->unit) return (false); if (desc->m.match.core_rev && !bhnd_hwrev_matches(core->hwrev, &desc->core_rev)) return (false); if (desc->m.match.core_class && desc->core_class != bhnd_core_class(core)) return (false); return true; } /** * Return true if the @p chip matches @p desc. * * @param chip A bhnd chip identifier. * @param desc A match descriptor to compare against @p chip. * * @retval true if @p chip matches @p match * @retval false if @p chip does not match @p match. */ bool bhnd_chip_matches(const struct bhnd_chipid *chip, const struct bhnd_chip_match *desc) { if (desc->m.match.chip_id && chip->chip_id != desc->chip_id) return (false); if (desc->m.match.chip_pkg && chip->chip_pkg != desc->chip_pkg) return (false); if (desc->m.match.chip_rev && !bhnd_hwrev_matches(chip->chip_rev, &desc->chip_rev)) return (false); return (true); } /** * Return true if the @p board matches @p desc. * * @param board The bhnd board info. * @param desc A match descriptor to compare against @p board. * * @retval true if @p chip matches @p match * @retval false if @p chip does not match @p match. */ bool bhnd_board_matches(const struct bhnd_board_info *board, const struct bhnd_board_match *desc) { if (desc->m.match.board_srom_rev && !bhnd_hwrev_matches(board->board_srom_rev, &desc->board_srom_rev)) return (false); if (desc->m.match.board_vendor && board->board_vendor != desc->board_vendor) return (false); if (desc->m.match.board_type && board->board_type != desc->board_type) return (false); if (desc->m.match.board_rev && !bhnd_hwrev_matches(board->board_rev, &desc->board_rev)) return (false); return (true); } /** * Return true if the @p hwrev matches @p desc. * * @param hwrev A bhnd hardware revision. * @param desc A match descriptor to compare against @p core. * * @retval true if @p hwrev matches @p match * @retval false if @p hwrev does not match @p match. */ bool bhnd_hwrev_matches(uint16_t hwrev, const struct bhnd_hwrev_match *desc) { if (desc->start != BHND_HWREV_INVALID && desc->start > hwrev) return false; if (desc->end != BHND_HWREV_INVALID && desc->end < hwrev) return false; return true; } /** * Return true if the @p dev matches @p desc. * * @param dev A bhnd device. * @param desc A match descriptor to compare against @p dev. * * @retval true if @p dev matches @p match * @retval false if @p dev does not match @p match. */ bool bhnd_device_matches(device_t dev, const struct bhnd_device_match *desc) { struct bhnd_core_info core; const struct bhnd_chipid *chip; struct bhnd_board_info board; device_t parent; int error; /* Construct individual match descriptors */ struct bhnd_core_match m_core = { _BHND_CORE_MATCH_COPY(desc) }; struct bhnd_chip_match m_chip = { _BHND_CHIP_MATCH_COPY(desc) }; struct bhnd_board_match m_board = { _BHND_BOARD_MATCH_COPY(desc) }; /* Fetch and match core info */ if (m_core.m.match_flags) { /* Only applicable to bhnd-attached cores */ parent = device_get_parent(dev); if (device_get_devclass(parent) != bhnd_devclass) { device_printf(dev, "attempting to match core " "attributes against non-core device\n"); return (false); } core = bhnd_get_core_info(dev); if (!bhnd_core_matches(&core, &m_core)) return (false); } /* Fetch and match chip info */ if (m_chip.m.match_flags) { chip = bhnd_get_chipid(dev); if (!bhnd_chip_matches(chip, &m_chip)) return (false); } /* Fetch and match board info. * * This is not available until after NVRAM is up; earlier device * matches should not include board requirements */ if (m_board.m.match_flags) { if ((error = bhnd_read_board_info(dev, &board))) { device_printf(dev, "failed to read required board info " "during device matching: %d\n", error); return (false); } if (!bhnd_board_matches(&board, &m_board)) return (false); } /* All matched */ return (true); } /** * Search @p table for an entry matching @p dev. * * @param dev A bhnd device to match against @p table. * @param table The device table to search. * @param entry_size The @p table entry size, in bytes. * * @retval bhnd_device the first matching device, if any. * @retval NULL if no matching device is found in @p table. */ const struct bhnd_device * bhnd_device_lookup(device_t dev, const struct bhnd_device *table, size_t entry_size) { const struct bhnd_device *entry; device_t hostb, parent; bhnd_attach_type attach_type; uint32_t dflags; parent = device_get_parent(dev); hostb = bhnd_find_hostb_device(parent); attach_type = bhnd_get_attach_type(dev); for (entry = table; !BHND_DEVICE_IS_END(entry); entry = (const struct bhnd_device *) ((const char *) entry + entry_size)) { /* match core info */ if (!bhnd_device_matches(dev, &entry->core)) continue; /* match device flags */ dflags = entry->device_flags; /* hostb implies BHND_ATTACH_ADAPTER requirement */ if (dflags & BHND_DF_HOSTB) dflags |= BHND_DF_ADAPTER; if (dflags & BHND_DF_ADAPTER) if (attach_type != BHND_ATTACH_ADAPTER) continue; if (dflags & BHND_DF_HOSTB) if (dev != hostb) continue; if (dflags & BHND_DF_SOC) if (attach_type != BHND_ATTACH_NATIVE) continue; /* device found */ return (entry); } /* not found */ return (NULL); } /** * Scan the device @p table for all quirk flags applicable to @p dev. * * @param dev A bhnd device to match against @p table. * @param table The device table to search. * * @return returns all matching quirk flags. */ uint32_t bhnd_device_quirks(device_t dev, const struct bhnd_device *table, size_t entry_size) { const struct bhnd_device *dent; const struct bhnd_device_quirk *qent, *qtable; uint32_t quirks; /* Locate the device entry */ if ((dent = bhnd_device_lookup(dev, table, entry_size)) == NULL) return (0); /* Quirks table is optional */ qtable = dent->quirks_table; if (qtable == NULL) return (0); /* Collect matching device quirk entries */ quirks = 0; for (qent = qtable; !BHND_DEVICE_QUIRK_IS_END(qent); qent++) { if (bhnd_device_matches(dev, &qent->desc)) quirks |= qent->quirks; } return (quirks); } /** * Allocate bhnd(4) resources defined in @p rs from a parent bus. * * @param dev The device requesting ownership of the resources. * @param rs A standard bus resource specification. This will be updated * with the allocated resource's RIDs. * @param res On success, the allocated bhnd resources. * * @retval 0 success * @retval non-zero if allocation of any non-RF_OPTIONAL resource fails, * all allocated resources will be released and a regular * unix error code will be returned. */ int bhnd_alloc_resources(device_t dev, struct resource_spec *rs, struct bhnd_resource **res) { /* Initialize output array */ for (u_int i = 0; rs[i].type != -1; i++) res[i] = NULL; for (u_int i = 0; rs[i].type != -1; i++) { res[i] = bhnd_alloc_resource_any(dev, rs[i].type, &rs[i].rid, rs[i].flags); /* Clean up all allocations on failure */ if (res[i] == NULL && !(rs[i].flags & RF_OPTIONAL)) { bhnd_release_resources(dev, rs, res); return (ENXIO); } } return (0); }; /** * Release bhnd(4) resources defined in @p rs from a parent bus. * * @param dev The device that owns the resources. * @param rs A standard bus resource specification previously initialized * by @p bhnd_alloc_resources. * @param res The bhnd resources to be released. */ void bhnd_release_resources(device_t dev, const struct resource_spec *rs, struct bhnd_resource **res) { for (u_int i = 0; rs[i].type != -1; i++) { if (res[i] == NULL) continue; bhnd_release_resource(dev, rs[i].type, rs[i].rid, res[i]); res[i] = NULL; } } /** * Parse the CHIPC_ID_* fields from the ChipCommon CHIPC_ID * register, returning its bhnd_chipid representation. * * @param idreg The CHIPC_ID register value. * @param enum_addr The enumeration address to include in the result. * * @warning * On early siba(4) devices, the ChipCommon core does not provide * a valid CHIPC_ID_NUMCORE field. On these ChipCommon revisions * (see CHIPC_NCORES_MIN_HWREV()), this function will parse and return * an invalid `ncores` value. */ struct bhnd_chipid bhnd_parse_chipid(uint32_t idreg, bhnd_addr_t enum_addr) { struct bhnd_chipid result; /* Fetch the basic chip info */ result.chip_id = CHIPC_GET_BITS(idreg, CHIPC_ID_CHIP); result.chip_pkg = CHIPC_GET_BITS(idreg, CHIPC_ID_PKG); result.chip_rev = CHIPC_GET_BITS(idreg, CHIPC_ID_REV); result.chip_type = CHIPC_GET_BITS(idreg, CHIPC_ID_BUS); result.ncores = CHIPC_GET_BITS(idreg, CHIPC_ID_NUMCORE); result.enum_addr = enum_addr; return (result); } /** * Allocate the resource defined by @p rs via @p dev, use it * to read the ChipCommon ID register relative to @p chipc_offset, * then release the resource. * * @param dev The device owning @p rs. * @param rs A resource spec that encompasses the ChipCommon register block. * @param chipc_offset The offset of the ChipCommon registers within @p rs. * @param[out] result the chip identification data. * * @retval 0 success * @retval non-zero if the ChipCommon identification data could not be read. */ int bhnd_read_chipid(device_t dev, struct resource_spec *rs, bus_size_t chipc_offset, struct bhnd_chipid *result) { struct resource *res; bhnd_addr_t enum_addr; uint32_t reg; uint8_t chip_type; int error, rid, rtype; rid = rs->rid; rtype = rs->type; error = 0; /* Allocate the ChipCommon window resource and fetch the chipid data */ res = bus_alloc_resource_any(dev, rtype, &rid, RF_ACTIVE); if (res == NULL) { device_printf(dev, "failed to allocate bhnd chipc resource\n"); return (ENXIO); } /* Fetch the basic chip info */ reg = bus_read_4(res, chipc_offset + CHIPC_ID); chip_type = CHIPC_GET_BITS(reg, CHIPC_ID_BUS); /* Fetch the EROMPTR */ if (BHND_CHIPTYPE_HAS_EROM(chip_type)) { enum_addr = bus_read_4(res, chipc_offset + CHIPC_EROMPTR); } else if (chip_type == BHND_CHIPTYPE_SIBA) { /* siba(4) uses the ChipCommon base address as the enumeration * address */ enum_addr = rman_get_start(res) + chipc_offset; } else { device_printf(dev, "unknown chip type %hhu\n", chip_type); error = ENODEV; goto cleanup; } *result = bhnd_parse_chipid(reg, enum_addr); cleanup: /* Clean up */ bus_release_resource(dev, rtype, rid, res); return (error); } /** * Read an NVRAM variable's NUL-terminated string value. * * @param dev A bhnd bus child device. * @param name The NVRAM variable name. * @param[out] buf A buffer large enough to hold @p len bytes. On * success, the NUL-terminated string value will be * written to this buffer. This argment may be NULL if * the value is not desired. * @param len The maximum capacity of @p buf. * @param[out] rlen On success, will be set to the actual size of * the requested value (including NUL termination). This * argment may be NULL if the size is not desired. * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENODEV No valid NVRAM source could be found. * @retval ENOMEM If @p buf is non-NULL and a buffer of @p len is too * small to hold the requested value. * @retval EFTYPE If the variable data cannot be coerced to a valid * string representation. * @retval ERANGE If value coercion would overflow @p type. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ int bhnd_nvram_getvar_str(device_t dev, const char *name, char *buf, size_t len, size_t *rlen) { size_t larg; int error; larg = len; error = bhnd_nvram_getvar(dev, name, buf, &larg, BHND_NVRAM_TYPE_CSTR); if (rlen != NULL) *rlen = larg; return (error); } /** * Read an NVRAM variable's unsigned integer value. * * @param dev A bhnd bus child device. * @param name The NVRAM variable name. * @param[out] value On success, the requested value will be written * to this pointer. * @param width The output integer type width (1, 2, or * 4 bytes). * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENODEV No valid NVRAM source could be found. * @retval EFTYPE If the variable data cannot be coerced to a * a valid unsigned integer representation. * @retval ERANGE If value coercion would overflow (or underflow) an * unsigned representation of the given @p width. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ int bhnd_nvram_getvar_uint(device_t dev, const char *name, void *value, int width) { bhnd_nvram_type type; size_t len; switch (width) { case 1: type = BHND_NVRAM_TYPE_UINT8; break; case 2: type = BHND_NVRAM_TYPE_UINT16; break; case 4: type = BHND_NVRAM_TYPE_UINT32; break; default: device_printf(dev, "unsupported NVRAM integer width: %d\n", width); return (EINVAL); } len = width; return (bhnd_nvram_getvar(dev, name, value, &len, type)); } /** * Read an NVRAM variable's unsigned 8-bit integer value. * * @param dev A bhnd bus child device. * @param name The NVRAM variable name. * @param[out] value On success, the requested value will be written * to this pointer. * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENODEV No valid NVRAM source could be found. * @retval EFTYPE If the variable data cannot be coerced to a * a valid unsigned integer representation. * @retval ERANGE If value coercion would overflow (or underflow) uint8_t. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ int bhnd_nvram_getvar_uint8(device_t dev, const char *name, uint8_t *value) { return (bhnd_nvram_getvar_uint(dev, name, value, sizeof(*value))); } /** * Read an NVRAM variable's unsigned 16-bit integer value. * * @param dev A bhnd bus child device. * @param name The NVRAM variable name. * @param[out] value On success, the requested value will be written * to this pointer. * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENODEV No valid NVRAM source could be found. * @retval EFTYPE If the variable data cannot be coerced to a * a valid unsigned integer representation. * @retval ERANGE If value coercion would overflow (or underflow) * uint16_t. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ int bhnd_nvram_getvar_uint16(device_t dev, const char *name, uint16_t *value) { return (bhnd_nvram_getvar_uint(dev, name, value, sizeof(*value))); } /** * Read an NVRAM variable's unsigned 32-bit integer value. * * @param dev A bhnd bus child device. * @param name The NVRAM variable name. * @param[out] value On success, the requested value will be written * to this pointer. * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENODEV No valid NVRAM source could be found. * @retval EFTYPE If the variable data cannot be coerced to a * a valid unsigned integer representation. * @retval ERANGE If value coercion would overflow (or underflow) * uint32_t. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ int bhnd_nvram_getvar_uint32(device_t dev, const char *name, uint32_t *value) { return (bhnd_nvram_getvar_uint(dev, name, value, sizeof(*value))); } /** * Read an NVRAM variable's signed integer value. * * @param dev A bhnd bus child device. * @param name The NVRAM variable name. * @param[out] value On success, the requested value will be written * to this pointer. * @param width The output integer type width (1, 2, or * 4 bytes). * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENODEV No valid NVRAM source could be found. * @retval EFTYPE If the variable data cannot be coerced to a * a valid integer representation. * @retval ERANGE If value coercion would overflow (or underflow) an * signed representation of the given @p width. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ int bhnd_nvram_getvar_int(device_t dev, const char *name, void *value, int width) { bhnd_nvram_type type; size_t len; switch (width) { case 1: type = BHND_NVRAM_TYPE_INT8; break; case 2: type = BHND_NVRAM_TYPE_INT16; break; case 4: type = BHND_NVRAM_TYPE_INT32; break; default: device_printf(dev, "unsupported NVRAM integer width: %d\n", width); return (EINVAL); } len = width; return (bhnd_nvram_getvar(dev, name, value, &len, type)); } /** * Read an NVRAM variable's signed 8-bit integer value. * * @param dev A bhnd bus child device. * @param name The NVRAM variable name. * @param[out] value On success, the requested value will be written * to this pointer. * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENODEV No valid NVRAM source could be found. * @retval EFTYPE If the variable data cannot be coerced to a * a valid integer representation. * @retval ERANGE If value coercion would overflow (or underflow) int8_t. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ int bhnd_nvram_getvar_int8(device_t dev, const char *name, int8_t *value) { return (bhnd_nvram_getvar_int(dev, name, value, sizeof(*value))); } /** * Read an NVRAM variable's signed 16-bit integer value. * * @param dev A bhnd bus child device. * @param name The NVRAM variable name. * @param[out] value On success, the requested value will be written * to this pointer. * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENODEV No valid NVRAM source could be found. * @retval EFTYPE If the variable data cannot be coerced to a * a valid integer representation. * @retval ERANGE If value coercion would overflow (or underflow) * int16_t. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ int bhnd_nvram_getvar_int16(device_t dev, const char *name, int16_t *value) { return (bhnd_nvram_getvar_int(dev, name, value, sizeof(*value))); } /** * Read an NVRAM variable's signed 32-bit integer value. * * @param dev A bhnd bus child device. * @param name The NVRAM variable name. * @param[out] value On success, the requested value will be written * to this pointer. * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENODEV No valid NVRAM source could be found. * @retval EFTYPE If the variable data cannot be coerced to a * a valid integer representation. * @retval ERANGE If value coercion would overflow (or underflow) * int32_t. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ int bhnd_nvram_getvar_int32(device_t dev, const char *name, int32_t *value) { return (bhnd_nvram_getvar_int(dev, name, value, sizeof(*value))); } /** * Read an NVRAM variable's array value. * * @param dev A bhnd bus child device. * @param name The NVRAM variable name. * @param[out] buf A buffer large enough to hold @p size bytes. * On success, the requested value will be written * to this buffer. * @param[in,out] size The required number of bytes to write to * @p buf. * @param type The desired array element data representation. * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENODEV No valid NVRAM source could be found. * @retval ENXIO If less than @p size bytes are available. * @retval ENOMEM If a buffer of @p size is too small to hold the * requested value. * @retval EFTYPE If the variable data cannot be coerced to a * a valid instance of @p type. * @retval ERANGE If value coercion would overflow (or underflow) a * representation of @p type. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ int bhnd_nvram_getvar_array(device_t dev, const char *name, void *buf, size_t size, bhnd_nvram_type type) { size_t nbytes; int error; /* Attempt read */ nbytes = size; if ((error = bhnd_nvram_getvar(dev, name, buf, &nbytes, type))) return (error); /* Verify that the expected number of bytes were fetched */ if (nbytes < size) return (ENXIO); return (0); } /** * Using the bhnd(4) bus-level core information and a custom core name, * populate @p dev's device description. * * @param dev A bhnd-bus attached device. * @param dev_name The core's name (e.g. "SDIO Device Core") */ void bhnd_set_custom_core_desc(device_t dev, const char *dev_name) { const char *vendor_name; char *desc; vendor_name = bhnd_get_vendor_name(dev); asprintf(&desc, M_BHND, "%s %s, rev %hhu", vendor_name, dev_name, bhnd_get_hwrev(dev)); if (desc != NULL) { device_set_desc_copy(dev, desc); free(desc, M_BHND); } else { device_set_desc(dev, dev_name); } } /** * Using the bhnd(4) bus-level core information, populate @p dev's device * description. * * @param dev A bhnd-bus attached device. */ void bhnd_set_default_core_desc(device_t dev) { bhnd_set_custom_core_desc(dev, bhnd_get_device_name(dev)); } /** * Helper function for implementing BHND_BUS_IS_HW_DISABLED(). * * If a parent device is available, this implementation delegates the * request to the BHND_BUS_IS_HW_DISABLED() method on the parent of @p dev. * * If no parent device is available (i.e. on a the bus root), the hardware * is assumed to be usable and false is returned. */ bool bhnd_bus_generic_is_hw_disabled(device_t dev, device_t child) { if (device_get_parent(dev) != NULL) return (BHND_BUS_IS_HW_DISABLED(device_get_parent(dev), child)); return (false); } /** * Helper function for implementing BHND_BUS_GET_CHIPID(). * * This implementation delegates the request to the BHND_BUS_GET_CHIPID() * method on the parent of @p dev. If no parent exists, the implementation * will panic. */ const struct bhnd_chipid * bhnd_bus_generic_get_chipid(device_t dev, device_t child) { if (device_get_parent(dev) != NULL) return (BHND_BUS_GET_CHIPID(device_get_parent(dev), child)); panic("missing BHND_BUS_GET_CHIPID()"); } /* nvram board_info population macros for bhnd_bus_generic_read_board_info() */ #define BHND_GV(_dest, _name) \ bhnd_nvram_getvar_uint(child, BHND_NVAR_ ## _name, &_dest, \ sizeof(_dest)) #define REQ_BHND_GV(_dest, _name) do { \ if ((error = BHND_GV(_dest, _name))) { \ device_printf(dev, \ "error reading " __STRING(_name) ": %d\n", error); \ return (error); \ } \ } while(0) #define OPT_BHND_GV(_dest, _name, _default) do { \ if ((error = BHND_GV(_dest, _name))) { \ if (error != ENOENT) { \ device_printf(dev, \ "error reading " \ __STRING(_name) ": %d\n", error); \ return (error); \ } \ _dest = _default; \ } \ } while(0) /** * Helper function for implementing BHND_BUS_READ_BOARDINFO(). * * This implementation populates @p info with information from NVRAM, * defaulting board_vendor and board_type fields to 0 if the * requested variables cannot be found. * * This behavior is correct for most SoCs, but must be overridden on * bridged (PCI, PCMCIA, etc) devices to produce a complete bhnd_board_info * result. */ int bhnd_bus_generic_read_board_info(device_t dev, device_t child, struct bhnd_board_info *info) { int error; OPT_BHND_GV(info->board_vendor, BOARDVENDOR, 0); OPT_BHND_GV(info->board_type, BOARDTYPE, 0); /* srom >= 2 */ REQ_BHND_GV(info->board_rev, BOARDREV); - REQ_BHND_GV(info->board_srom_rev,SROMREV); + OPT_BHND_GV(info->board_srom_rev,SROMREV, 0); /* missing in + some SoC + NVRAM */ REQ_BHND_GV(info->board_flags, BOARDFLAGS); OPT_BHND_GV(info->board_flags2, BOARDFLAGS2, 0); /* srom >= 4 */ OPT_BHND_GV(info->board_flags3, BOARDFLAGS3, 0); /* srom >= 11 */ return (0); } #undef BHND_GV #undef BHND_GV_REQ #undef BHND_GV_OPT /** * Helper function for implementing BHND_BUS_GET_NVRAM_VAR(). * * This implementation searches @p dev for a usable NVRAM child device. * * If no usable child device is found on @p dev, the request is delegated to * the BHND_BUS_GET_NVRAM_VAR() method on the parent of @p dev. */ int bhnd_bus_generic_get_nvram_var(device_t dev, device_t child, const char *name, void *buf, size_t *size, bhnd_nvram_type type) { device_t nvram; device_t parent; /* Make sure we're holding Giant for newbus */ GIANT_REQUIRED; /* Look for a directly-attached NVRAM child */ if ((nvram = device_find_child(dev, "bhnd_nvram", -1)) != NULL) return BHND_NVRAM_GETVAR(nvram, name, buf, size, type); /* Try to delegate to parent */ if ((parent = device_get_parent(dev)) == NULL) return (ENODEV); return (BHND_BUS_GET_NVRAM_VAR(device_get_parent(dev), child, name, buf, size, type)); } /** * Helper function for implementing BHND_BUS_ALLOC_RESOURCE(). * * This implementation of BHND_BUS_ALLOC_RESOURCE() delegates allocation * of the underlying resource to BUS_ALLOC_RESOURCE(), and activation * to @p dev's BHND_BUS_ACTIVATE_RESOURCE(). */ struct bhnd_resource * bhnd_bus_generic_alloc_resource(device_t dev, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) { struct bhnd_resource *br; struct resource *res; int error; br = NULL; res = NULL; /* Allocate the real bus resource (without activating it) */ res = BUS_ALLOC_RESOURCE(dev, child, type, rid, start, end, count, (flags & ~RF_ACTIVE)); if (res == NULL) return (NULL); /* Allocate our bhnd resource wrapper. */ br = malloc(sizeof(struct bhnd_resource), M_BHND, M_NOWAIT); if (br == NULL) goto failed; br->direct = false; br->res = res; /* Attempt activation */ if (flags & RF_ACTIVE) { error = BHND_BUS_ACTIVATE_RESOURCE(dev, child, type, *rid, br); if (error) goto failed; } return (br); failed: if (res != NULL) BUS_RELEASE_RESOURCE(dev, child, type, *rid, res); free(br, M_BHND); return (NULL); } /** * Helper function for implementing BHND_BUS_RELEASE_RESOURCE(). * * This implementation of BHND_BUS_RELEASE_RESOURCE() delegates release of * the backing resource to BUS_RELEASE_RESOURCE(). */ int bhnd_bus_generic_release_resource(device_t dev, device_t child, int type, int rid, struct bhnd_resource *r) { int error; if ((error = BUS_RELEASE_RESOURCE(dev, child, type, rid, r->res))) return (error); free(r, M_BHND); return (0); } /** * Helper function for implementing BHND_BUS_ACTIVATE_RESOURCE(). * * This implementation of BHND_BUS_ACTIVATE_RESOURCE() simply calls the * BHND_BUS_ACTIVATE_RESOURCE() method of the parent of @p dev. */ int bhnd_bus_generic_activate_resource(device_t dev, device_t child, int type, int rid, struct bhnd_resource *r) { /* Try to delegate to the parent */ if (device_get_parent(dev) != NULL) return (BHND_BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child, type, rid, r)); return (EINVAL); }; /** * Helper function for implementing BHND_BUS_DEACTIVATE_RESOURCE(). * * This implementation of BHND_BUS_ACTIVATE_RESOURCE() simply calls the * BHND_BUS_ACTIVATE_RESOURCE() method of the parent of @p dev. */ int bhnd_bus_generic_deactivate_resource(device_t dev, device_t child, int type, int rid, struct bhnd_resource *r) { if (device_get_parent(dev) != NULL) return (BHND_BUS_DEACTIVATE_RESOURCE(device_get_parent(dev), child, type, rid, r)); return (EINVAL); }; Index: head/sys/dev/bhnd/bhnd_types.h =================================================================== --- head/sys/dev/bhnd/bhnd_types.h (revision 304869) +++ head/sys/dev/bhnd/bhnd_types.h (revision 304870) @@ -1,108 +1,168 @@ /*- * Copyright (c) 2015 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. * * $FreeBSD$ */ #ifndef _BHND_BHND_TYPES_H_ #define _BHND_BHND_TYPES_H_ #include #include "nvram/bhnd_nvram.h" /** bhnd(4) device classes. */ typedef enum { BHND_DEVCLASS_CC, /**< chipcommon i/o controller */ BHND_DEVCLASS_CC_B, /**< chipcommon auxiliary controller */ BHND_DEVCLASS_PMU, /**< pmu controller */ BHND_DEVCLASS_PCI, /**< pci host/device bridge */ BHND_DEVCLASS_PCIE, /**< pcie host/device bridge */ BHND_DEVCLASS_PCCARD, /**< pcmcia host/device bridge */ BHND_DEVCLASS_RAM, /**< internal RAM/SRAM */ BHND_DEVCLASS_MEMC, /**< memory controller */ BHND_DEVCLASS_ENET, /**< 802.3 MAC/PHY */ BHND_DEVCLASS_ENET_MAC, /**< 802.3 MAC */ BHND_DEVCLASS_ENET_PHY, /**< 802.3 PHY */ BHND_DEVCLASS_WLAN, /**< 802.11 MAC/PHY/Radio */ BHND_DEVCLASS_WLAN_MAC, /**< 802.11 MAC */ BHND_DEVCLASS_WLAN_PHY, /**< 802.11 PHY */ BHND_DEVCLASS_CPU, /**< cpu core */ BHND_DEVCLASS_SOC_ROUTER, /**< interconnect router */ BHND_DEVCLASS_SOC_BRIDGE, /**< interconnect host bridge */ BHND_DEVCLASS_EROM, /**< bus device enumeration ROM */ BHND_DEVCLASS_NVRAM, /**< nvram/flash controller */ BHND_DEVCLASS_OTHER, /**< other / unknown */ BHND_DEVCLASS_INVALID /**< no/invalid class */ } bhnd_devclass_t; /** * bhnd(4) port types. * * Only BHND_PORT_DEVICE is guaranteed to be supported by all bhnd(4) bus * implementations. */ typedef enum { BHND_PORT_DEVICE = 0, /**< device memory */ BHND_PORT_BRIDGE = 1, /**< bridge memory */ BHND_PORT_AGENT = 2, /**< interconnect agent/wrapper */ } bhnd_port_type; /** * bhnd(4) attachment types. */ typedef enum { BHND_ATTACH_ADAPTER = 0, /**< A bridged card, such as a PCI WiFi chipset */ BHND_ATTACH_NATIVE = 1 /**< A bus resident on the native host, such as * the primary or secondary bus of an embedded * SoC */ } bhnd_attach_type; +/** + * bhnd(4) clock types. + */ +typedef enum { + /** + * Dynamically select an appropriate clock source based on all + * outstanding clock requests. + */ + BHND_CLOCK_DYN = (1 << 0), + + /** + * Idle Low-Power (ILP). + * + * No register access is required, or long request latency is + * acceptable. + */ + BHND_CLOCK_ILP = (1 << 1), + + /** + * Active Low-Power (ALP). + * + * Low-latency register access and low-rate DMA. + */ + BHND_CLOCK_ALP = (1 << 2), + + /** + * High Throughput (HT). + * + * High bus throughput and lowest-latency register access. + */ + BHND_CLOCK_HT = (1 << 3) +} bhnd_clock; + +/** + * Given two clock types, return the type with the highest precedence. + */ +static inline bhnd_clock +bhnd_clock_max(bhnd_clock a, bhnd_clock b) { + return (a > b ? a : b); +} + +/** + * bhnd(4) clock sources. + */ +typedef enum { + /** + * Clock is provided by the PCI bus clock + */ + BHND_CLKSRC_PCI = 0, + + /** Clock is provided by a crystal. */ + BHND_CLKSRC_XTAL = 1, + + /** Clock is provided by a low power oscillator. */ + BHND_CLKSRC_LPO = 2, + + /** Clock source is unknown */ + BHND_CLKSRC_UNKNOWN = 3 +} bhnd_clksrc; + /** Evaluates to true if @p cls is a device class that can be configured * as a host bridge device. */ #define BHND_DEVCLASS_SUPPORTS_HOSTB(cls) \ ((cls) == BHND_DEVCLASS_PCI || (cls) == BHND_DEVCLASS_PCIE || \ (cls) == BHND_DEVCLASS_PCCARD) /** * BHND bus address. * * @note While the interconnect may support 64-bit addressing, not * all bridges and SoC CPUs will. */ typedef uint64_t bhnd_addr_t; #define BHND_ADDR_MAX UINT64_MAX /**< Maximum bhnd_addr_t value */ /** BHND bus size. */ typedef uint64_t bhnd_size_t; #define BHND_SIZE_MAX UINT64_MAX /**< Maximum bhnd_size_t value */ #endif /* _BHND_BHND_TYPES_H_ */ Index: head/sys/dev/bhnd/bhndb/bhnd_bhndb.c =================================================================== --- head/sys/dev/bhnd/bhndb/bhnd_bhndb.c (revision 304869) +++ head/sys/dev/bhnd/bhndb/bhnd_bhndb.c (revision 304870) @@ -1,77 +1,108 @@ /*- * Copyright (c) 2015-2016 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include "bhndbvar.h" /* * bhnd(4) driver mix-in providing a shared common methods for * bhnd devices attached via a bhndb bridge. */ static int bhnd_bhndb_read_board_info(device_t dev, device_t child, struct bhnd_board_info *info) { int error; /* Initialize with NVRAM-derived values */ if ((error = bhnd_bus_generic_read_board_info(dev, child, info))) return (error); /* Let the bridge fill in any additional data */ return (BHNDB_POPULATE_BOARD_INFO(device_get_parent(dev), dev, info)); } static bhnd_attach_type bhnd_bhndb_get_attach_type(device_t dev, device_t child) { /* It's safe to assume that a bridged device is always an adapter */ return (BHND_ATTACH_ADAPTER); } +static bhnd_clksrc +bhnd_bhndb_pwrctl_get_clksrc(device_t dev, device_t child, + bhnd_clock clock) +{ + /* Delegate to parent bridge */ + return (BHND_BUS_PWRCTL_GET_CLKSRC(device_get_parent(dev), child, + clock)); +} + +static int +bhnd_bhndb_pwrctl_gate_clock(device_t dev, device_t child, + bhnd_clock clock) +{ + /* Delegate to parent bridge */ + return (BHND_BUS_PWRCTL_GATE_CLOCK(device_get_parent(dev), child, + clock)); +} + +static int +bhnd_bhndb_pwrctl_ungate_clock(device_t dev, device_t child, + bhnd_clock clock) +{ + /* Delegate to parent bridge */ + return (BHND_BUS_PWRCTL_UNGATE_CLOCK(device_get_parent(dev), child, + clock)); +} + static device_method_t bhnd_bhndb_methods[] = { /* BHND interface */ DEVMETHOD(bhnd_bus_get_attach_type, bhnd_bhndb_get_attach_type), DEVMETHOD(bhnd_bus_read_board_info, bhnd_bhndb_read_board_info), + + DEVMETHOD(bhnd_bus_pwrctl_get_clksrc, bhnd_bhndb_pwrctl_get_clksrc), + DEVMETHOD(bhnd_bus_pwrctl_gate_clock, bhnd_bhndb_pwrctl_gate_clock), + DEVMETHOD(bhnd_bus_pwrctl_ungate_clock, bhnd_bhndb_pwrctl_ungate_clock), DEVMETHOD_END }; DEFINE_CLASS_0(bhnd, bhnd_bhndb_driver, bhnd_bhndb_methods, 0); Index: head/sys/dev/bhnd/bhndb/bhndb.c =================================================================== --- head/sys/dev/bhnd/bhndb/bhndb.c (revision 304869) +++ head/sys/dev/bhnd/bhndb/bhndb.c (revision 304870) @@ -1,2031 +1,2030 @@ /*- * Copyright (c) 2015 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); /* * Abstract BHND Bridge Device Driver * * Provides generic support for bridging from a parent bus (such as PCI) to * a BHND-compatible bus (e.g. bcma or siba). */ #include #include #include #include #include #include #include #include #include #include #include #include #include "bhnd_chipc_if.h" #include "bhnd_nvram_if.h" #include "bhndbvar.h" #include "bhndb_bus_if.h" #include "bhndb_hwdata.h" #include "bhndb_private.h" /* Debugging flags */ static u_long bhndb_debug = 0; TUNABLE_ULONG("hw.bhndb.debug", &bhndb_debug); enum { BHNDB_DEBUG_PRIO = 1 << 0, }; #define BHNDB_DEBUG(_type) (BHNDB_DEBUG_ ## _type & bhndb_debug) static bool bhndb_hw_matches(device_t *devlist, int num_devs, const struct bhndb_hw *hw); static int bhndb_initialize_region_cfg( struct bhndb_softc *sc, device_t *devs, int ndevs, const struct bhndb_hw_priority *table, struct bhndb_resources *r); static int bhndb_find_hwspec(struct bhndb_softc *sc, device_t *devs, int ndevs, const struct bhndb_hw **hw); static int bhndb_read_chipid(struct bhndb_softc *sc, const struct bhndb_hwcfg *cfg, struct bhnd_chipid *result); bhndb_addrspace bhndb_get_addrspace(struct bhndb_softc *sc, device_t child); static struct rman *bhndb_get_rman(struct bhndb_softc *sc, device_t child, int type); static int bhndb_init_child_resource(struct resource *r, struct resource *parent, bhnd_size_t offset, bhnd_size_t size); static int bhndb_activate_static_region( struct bhndb_softc *sc, struct bhndb_region *region, device_t child, int type, int rid, struct resource *r); static int bhndb_try_activate_resource( struct bhndb_softc *sc, device_t child, int type, int rid, struct resource *r, bool *indirect); /** * Default bhndb(4) implementation of DEVICE_PROBE(). * * This function provides the default bhndb implementation of DEVICE_PROBE(), * and is compatible with bhndb(4) bridges attached via bhndb_attach_bridge(). */ int bhndb_generic_probe(device_t dev) { return (BUS_PROBE_NOWILDCARD); } static void bhndb_probe_nomatch(device_t dev, device_t child) { const char *name; name = device_get_name(child); if (name == NULL) name = "unknown device"; device_printf(dev, "<%s> (no driver attached)\n", name); } static int bhndb_print_child(device_t dev, device_t child) { struct bhndb_softc *sc; struct resource_list *rl; int retval = 0; sc = device_get_softc(dev); retval += bus_print_child_header(dev, child); rl = BUS_GET_RESOURCE_LIST(dev, child); if (rl != NULL) { retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); } retval += bus_print_child_domain(dev, child); retval += bus_print_child_footer(dev, child); return (retval); } static int bhndb_child_pnpinfo_str(device_t bus, device_t child, char *buf, size_t buflen) { *buf = '\0'; return (0); } static int bhndb_child_location_str(device_t dev, device_t child, char *buf, size_t buflen) { struct bhndb_softc *sc; sc = device_get_softc(dev); snprintf(buf, buflen, "base=0x%llx", (unsigned long long) sc->chipid.enum_addr); return (0); } /** * Return true if @p devlist matches the @p hw specification. * * @param devlist A device table to match against. * @param num_devs The number of devices in @p devlist. * @param hw The hardware description to be matched against. */ static bool bhndb_hw_matches(device_t *devlist, int num_devs, const struct bhndb_hw *hw) { for (u_int i = 0; i < hw->num_hw_reqs; i++) { const struct bhnd_core_match *match; struct bhnd_core_info ci; bool found; match = &hw->hw_reqs[i]; found = false; for (int d = 0; d < num_devs; d++) { ci = bhnd_get_core_info(devlist[d]); if (!bhnd_core_matches(&ci, match)) continue; found = true; break; } if (!found) return (false); } return (true); } /** * Initialize the region maps and priority configuration in @p r using * the provided priority @p table and the set of devices attached to * the bridged @p bus_dev . * * @param sc The bhndb device state. * @param devs All devices enumerated on the bridged bhnd bus. * @param ndevs The length of @p devs. * @param table Hardware priority table to be used to determine the relative * priorities of per-core port resources. * @param r The resource state to be configured. */ static int bhndb_initialize_region_cfg(struct bhndb_softc *sc, device_t *devs, int ndevs, const struct bhndb_hw_priority *table, struct bhndb_resources *r) { const struct bhndb_hw_priority *hp; bhnd_addr_t addr; bhnd_size_t size; size_t prio_low, prio_default, prio_high; int error; /* The number of port regions per priority band that must be accessible * via dynamic register windows */ prio_low = 0; prio_default = 0; prio_high = 0; /* * Register bridge regions covering all statically mapped ports. */ for (int i = 0; i < ndevs; i++) { const struct bhndb_regwin *regw; device_t child; child = devs[i]; for (regw = r->cfg->register_windows; regw->win_type != BHNDB_REGWIN_T_INVALID; regw++) { /* Only core windows are supported */ if (regw->win_type != BHNDB_REGWIN_T_CORE) continue; /* Skip non-applicable register windows. */ if (!bhndb_regwin_matches_device(regw, child)) continue; /* Fetch the base address of the mapped port. */ error = bhnd_get_region_addr(child, regw->d.core.port_type, regw->d.core.port, regw->d.core.region, &addr, &size); if (error) return (error); /* * Always defer to the register window's size. * * If the port size is smaller than the window size, * this ensures that we fully utilize register windows * larger than the referenced port. * * If the port size is larger than the window size, this * ensures that we do not directly map the allocations * within the region to a too-small window. */ size = regw->win_size; /* * Add to the bus region list. * * The window priority for a statically mapped * region is always HIGH. */ error = bhndb_add_resource_region(r, addr, size, BHNDB_PRIORITY_HIGH, regw); if (error) return (error); } } /* * Perform priority accounting and register bridge regions for all * ports defined in the priority table */ for (int i = 0; i < ndevs; i++) { struct bhndb_region *region; device_t child; child = devs[i]; /* * Skip priority accounting for cores that ... */ /* ... do not require bridge resources */ if (bhnd_is_hw_disabled(child) || !device_is_enabled(child)) continue; /* ... do not have a priority table entry */ hp = bhndb_hw_priority_find_device(table, child); if (hp == NULL) continue; /* ... are explicitly disabled in the priority table. */ if (hp->priority == BHNDB_PRIORITY_NONE) continue; /* Determine the number of dynamic windows required and * register their bus_region entries. */ for (u_int i = 0; i < hp->num_ports; i++) { const struct bhndb_port_priority *pp; pp = &hp->ports[i]; /* Skip ports not defined on this device */ if (!bhnd_is_region_valid(child, pp->type, pp->port, pp->region)) { continue; } /* Fetch the address+size of the mapped port. */ error = bhnd_get_region_addr(child, pp->type, pp->port, pp->region, &addr, &size); if (error) return (error); /* Skip ports with an existing static mapping */ region = bhndb_find_resource_region(r, addr, size); if (region != NULL && region->static_regwin != NULL) continue; /* Define a dynamic region for this port */ error = bhndb_add_resource_region(r, addr, size, pp->priority, NULL); if (error) return (error); /* Update port mapping counts */ switch (pp->priority) { case BHNDB_PRIORITY_NONE: break; case BHNDB_PRIORITY_LOW: prio_low++; break; case BHNDB_PRIORITY_DEFAULT: prio_default++; break; case BHNDB_PRIORITY_HIGH: prio_high++; break; } } } /* Determine the minimum priority at which we'll allocate direct * register windows from our dynamic pool */ size_t prio_total = prio_low + prio_default + prio_high; if (prio_total <= r->dwa_count) { /* low+default+high priority regions get windows */ r->min_prio = BHNDB_PRIORITY_LOW; } else if (prio_default + prio_high <= r->dwa_count) { /* default+high priority regions get windows */ r->min_prio = BHNDB_PRIORITY_DEFAULT; } else { /* high priority regions get windows */ r->min_prio = BHNDB_PRIORITY_HIGH; } if (BHNDB_DEBUG(PRIO)) { struct bhndb_region *region; const char *direct_msg, *type_msg; bhndb_priority_t prio, prio_min; prio_min = r->min_prio; device_printf(sc->dev, "min_prio: %d\n", prio_min); STAILQ_FOREACH(region, &r->bus_regions, link) { prio = region->priority; direct_msg = prio >= prio_min ? "direct" : "indirect"; type_msg = region->static_regwin ? "static" : "dynamic"; device_printf(sc->dev, "region 0x%llx+0x%llx priority " "%u %s/%s\n", (unsigned long long) region->addr, (unsigned long long) region->size, region->priority, direct_msg, type_msg); } } return (0); } /** * Find a hardware specification for @p dev. * * @param sc The bhndb device state. * @param devs All devices enumerated on the bridged bhnd bus. * @param ndevs The length of @p devs. * @param[out] hw On success, the matched hardware specification. * with @p dev. * * @retval 0 success * @retval non-zero if an error occurs fetching device info for comparison. */ static int bhndb_find_hwspec(struct bhndb_softc *sc, device_t *devs, int ndevs, const struct bhndb_hw **hw) { const struct bhndb_hw *next, *hw_table; /* Search for the first matching hardware config. */ hw_table = BHNDB_BUS_GET_HARDWARE_TABLE(sc->parent_dev, sc->dev); for (next = hw_table; next->hw_reqs != NULL; next++) { if (!bhndb_hw_matches(devs, ndevs, next)) continue; /* Found */ *hw = next; return (0); } return (ENOENT); } /** * Read the ChipCommon identification data for this device. * * @param sc bhndb device state. * @param cfg The hardware configuration to use when mapping the ChipCommon * registers. * @param[out] result the chip identification data. * * @retval 0 success * @retval non-zero if the ChipCommon identification data could not be read. */ static int bhndb_read_chipid(struct bhndb_softc *sc, const struct bhndb_hwcfg *cfg, struct bhnd_chipid *result) { const struct bhnd_chipid *parent_cid; const struct bhndb_regwin *cc_win; struct resource_spec rs; int error; /* Let our parent device override the discovery process */ parent_cid = BHNDB_BUS_GET_CHIPID(sc->parent_dev, sc->dev); if (parent_cid != NULL) { *result = *parent_cid; return (0); } /* Find a register window we can use to map the first CHIPC_CHIPID_SIZE * of ChipCommon registers. */ cc_win = bhndb_regwin_find_best(cfg->register_windows, BHND_DEVCLASS_CC, 0, BHND_PORT_DEVICE, 0, 0, CHIPC_CHIPID_SIZE); if (cc_win == NULL) { device_printf(sc->dev, "no chipcommon register window\n"); return (0); } /* We can assume a device without a static ChipCommon window uses the * default ChipCommon address. */ if (cc_win->win_type == BHNDB_REGWIN_T_DYN) { error = BHNDB_SET_WINDOW_ADDR(sc->dev, cc_win, BHND_DEFAULT_CHIPC_ADDR); if (error) { device_printf(sc->dev, "failed to set chipcommon " "register window\n"); return (error); } } /* Let the default bhnd implemenation alloc/release the resource and * perform the read */ rs.type = cc_win->res.type; rs.rid = cc_win->res.rid; rs.flags = RF_ACTIVE; return (bhnd_read_chipid(sc->parent_dev, &rs, cc_win->win_offset, result)); } /** * Helper function that must be called by subclass bhndb(4) drivers * when implementing DEVICE_ATTACH() before calling any bhnd(4) or bhndb(4) * APIs on the bridge device. * * @param dev The bridge device to attach. * @param bridge_devclass The device class of the bridging core. This is used * to automatically detect the bridge core, and to disable additional bridge * cores (e.g. PCMCIA on a PCIe device). */ int bhndb_attach(device_t dev, bhnd_devclass_t bridge_devclass) { struct bhndb_devinfo *dinfo; struct bhndb_softc *sc; const struct bhndb_hwcfg *cfg; int error; sc = device_get_softc(dev); sc->dev = dev; sc->parent_dev = device_get_parent(dev); sc->bridge_class = bridge_devclass; BHNDB_LOCK_INIT(sc); /* Read our chip identification data */ cfg = BHNDB_BUS_GET_GENERIC_HWCFG(sc->parent_dev, sc->dev); if ((error = bhndb_read_chipid(sc, cfg, &sc->chipid))) return (error); /* Populate generic resource allocation state. */ sc->bus_res = bhndb_alloc_resources(dev, sc->parent_dev, cfg); if (sc->bus_res == NULL) { return (ENXIO); } /* Attach our bridged bus device */ sc->bus_dev = BUS_ADD_CHILD(dev, 0, "bhnd", -1); if (sc->bus_dev == NULL) { error = ENXIO; goto failed; } /* Configure address space */ dinfo = device_get_ivars(sc->bus_dev); dinfo->addrspace = BHNDB_ADDRSPACE_BRIDGED; /* Finish attach */ return (bus_generic_attach(dev)); failed: BHNDB_LOCK_DESTROY(sc); if (sc->bus_res != NULL) bhndb_free_resources(sc->bus_res); return (error); } /** * Default bhndb(4) implementation of BHNDB_INIT_FULL_CONFIG(). * * This function provides the default bhndb implementation of * BHNDB_INIT_FULL_CONFIG(), and must be called by any subclass driver * overriding BHNDB_INIT_FULL_CONFIG(). * * As documented by BHNDB_INIT_FULL_CONFIG, this function performs final * bridge configuration based on the hardware information enumerated by the * child bus, and will reset all resource allocation state on the bridge. * * When calling this method: * - Any bus resources previously allocated by @p child must be deallocated. * - The @p child bus must have performed initial enumeration -- but not * probe or attachment -- of its children. */ int bhndb_generic_init_full_config(device_t dev, device_t child, const struct bhndb_hw_priority *hw_prio_table) { struct bhndb_softc *sc; const struct bhndb_hw *hw; struct bhndb_resources *r; device_t *devs; device_t hostb; int ndevs; int error; sc = device_get_softc(dev); hostb = NULL; /* Fetch the full set of bhnd-attached cores */ if ((error = device_get_children(sc->bus_dev, &devs, &ndevs))) { device_printf(sc->dev, "unable to get children\n"); return (error); } /* Find our host bridge device */ hostb = BHNDB_FIND_HOSTB_DEVICE(dev, child); if (hostb == NULL) { device_printf(sc->dev, "no host bridge core found\n"); error = ENODEV; goto cleanup; } /* Find our full register window configuration */ if ((error = bhndb_find_hwspec(sc, devs, ndevs, &hw))) { device_printf(sc->dev, "unable to identify device, " " using generic bridge resource definitions\n"); error = 0; goto cleanup; } if (bootverbose || BHNDB_DEBUG(PRIO)) device_printf(sc->dev, "%s resource configuration\n", hw->name); /* Release existing resource state */ BHNDB_LOCK(sc); bhndb_free_resources(sc->bus_res); sc->bus_res = NULL; BHNDB_UNLOCK(sc); /* Allocate new resource state */ r = bhndb_alloc_resources(dev, sc->parent_dev, hw->cfg); if (r == NULL) { error = ENXIO; goto cleanup; } /* Initialize our resource priority configuration */ error = bhndb_initialize_region_cfg(sc, devs, ndevs, hw_prio_table, r); if (error) { bhndb_free_resources(r); goto cleanup; } /* Update our bridge state */ BHNDB_LOCK(sc); sc->bus_res = r; sc->hostb_dev = hostb; BHNDB_UNLOCK(sc); cleanup: free(devs, M_TEMP); return (error); } /** * Default bhndb(4) implementation of DEVICE_DETACH(). * * This function detaches any child devices, and if successful, releases all * resources held by the bridge device. */ int bhndb_generic_detach(device_t dev) { struct bhndb_softc *sc; int error; sc = device_get_softc(dev); /* Detach children */ if ((error = bus_generic_detach(dev))) return (error); /* Clean up our driver state. */ bhndb_free_resources(sc->bus_res); BHNDB_LOCK_DESTROY(sc); return (0); } /** * Default bhndb(4) implementation of DEVICE_SUSPEND(). * * This function calls bus_generic_suspend() (or implements equivalent * behavior). */ int bhndb_generic_suspend(device_t dev) { return (bus_generic_suspend(dev)); } /** * Default bhndb(4) implementation of DEVICE_RESUME(). * * This function calls bus_generic_resume() (or implements equivalent * behavior). */ int bhndb_generic_resume(device_t dev) { struct bhndb_softc *sc; struct bhndb_resources *bus_res; struct bhndb_dw_alloc *dwa; int error; sc = device_get_softc(dev); bus_res = sc->bus_res; /* Guarantee that all in-use dynamic register windows are mapped to * their previously configured target address. */ BHNDB_LOCK(sc); for (size_t i = 0; i < bus_res->dwa_count; i++) { dwa = &bus_res->dw_alloc[i]; /* Skip regions that were not previously used */ if (bhndb_dw_is_free(bus_res, dwa) && dwa->target == 0x0) continue; /* Otherwise, ensure the register window is correct before * any children attempt MMIO */ error = BHNDB_SET_WINDOW_ADDR(dev, dwa->win, dwa->target); if (error) break; } BHNDB_UNLOCK(sc); /* Error restoring hardware state; children cannot be safely resumed */ if (error) { device_printf(dev, "Unable to restore hardware configuration; " "cannot resume: %d\n", error); return (error); } return (bus_generic_resume(dev)); } /** * Default implementation of BHNDB_SUSPEND_RESOURCE. */ static void bhndb_suspend_resource(device_t dev, device_t child, int type, struct resource *r) { struct bhndb_softc *sc; struct bhndb_dw_alloc *dwa; sc = device_get_softc(dev); // TODO: IRQs? if (type != SYS_RES_MEMORY) return; BHNDB_LOCK(sc); dwa = bhndb_dw_find_resource(sc->bus_res, r); if (dwa == NULL) { BHNDB_UNLOCK(sc); return; } if (BHNDB_DEBUG(PRIO)) device_printf(child, "suspend resource type=%d 0x%jx+0x%jx\n", type, rman_get_start(r), rman_get_size(r)); /* Release the resource's window reference */ bhndb_dw_release(sc->bus_res, dwa, r); BHNDB_UNLOCK(sc); } /** * Default implementation of BHNDB_RESUME_RESOURCE. */ static int bhndb_resume_resource(device_t dev, device_t child, int type, struct resource *r) { struct bhndb_softc *sc; sc = device_get_softc(dev); // TODO: IRQs? if (type != SYS_RES_MEMORY) return (0); /* Inactive resources don't require reallocation of bridge resources */ if (!(rman_get_flags(r) & RF_ACTIVE)) return (0); if (BHNDB_DEBUG(PRIO)) device_printf(child, "resume resource type=%d 0x%jx+0x%jx\n", type, rman_get_start(r), rman_get_size(r)); return (bhndb_try_activate_resource(sc, rman_get_device(r), type, rman_get_rid(r), r, NULL)); } /** * Default bhndb(4) implementation of BUS_READ_IVAR(). */ static int bhndb_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) { return (ENOENT); } /** * Default bhndb(4) implementation of BUS_WRITE_IVAR(). */ static int bhndb_write_ivar(device_t dev, device_t child, int index, uintptr_t value) { return (ENOENT); } /** * Return the address space for the given @p child device. */ bhndb_addrspace bhndb_get_addrspace(struct bhndb_softc *sc, device_t child) { struct bhndb_devinfo *dinfo; device_t imd_dev; /* Find the directly attached parent of the requesting device */ imd_dev = child; while (imd_dev != NULL && device_get_parent(imd_dev) != sc->dev) imd_dev = device_get_parent(imd_dev); if (imd_dev == NULL) panic("bhndb address space request for non-child device %s\n", device_get_nameunit(child)); dinfo = device_get_ivars(imd_dev); return (dinfo->addrspace); } /** * Return the rman instance for a given resource @p type, if any. * * @param sc The bhndb device state. * @param child The requesting child. * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...) */ static struct rman * bhndb_get_rman(struct bhndb_softc *sc, device_t child, int type) { switch (bhndb_get_addrspace(sc, child)) { case BHNDB_ADDRSPACE_NATIVE: switch (type) { case SYS_RES_MEMORY: return (&sc->bus_res->ht_mem_rman); case SYS_RES_IRQ: return (NULL); default: return (NULL); }; case BHNDB_ADDRSPACE_BRIDGED: switch (type) { case SYS_RES_MEMORY: return (&sc->bus_res->br_mem_rman); case SYS_RES_IRQ: // TODO // return &sc->irq_rman; return (NULL); default: return (NULL); }; } /* Quieten gcc */ return (NULL); } /** * Default implementation of BUS_ADD_CHILD() */ static device_t bhndb_add_child(device_t dev, u_int order, const char *name, int unit) { struct bhndb_devinfo *dinfo; device_t child; child = device_add_child_ordered(dev, order, name, unit); if (child == NULL) return (NULL); dinfo = malloc(sizeof(struct bhndb_devinfo), M_BHND, M_NOWAIT); if (dinfo == NULL) { device_delete_child(dev, child); return (NULL); } dinfo->addrspace = BHNDB_ADDRSPACE_NATIVE; resource_list_init(&dinfo->resources); device_set_ivars(child, dinfo); return (child); } /** * Default implementation of BUS_CHILD_DELETED(). */ static void bhndb_child_deleted(device_t dev, device_t child) { struct bhndb_devinfo *dinfo = device_get_ivars(child); if (dinfo != NULL) { resource_list_free(&dinfo->resources); free(dinfo, M_BHND); } device_set_ivars(child, NULL); } /** * Default implementation of BHNDB_GET_CHIPID(). */ static const struct bhnd_chipid * bhndb_get_chipid(device_t dev, device_t child) { struct bhndb_softc *sc = device_get_softc(dev); return (&sc->chipid); } /** * Default implementation of BHNDB_IS_HW_DISABLED(). */ static bool bhndb_is_hw_disabled(device_t dev, device_t child) { struct bhndb_softc *sc; struct bhnd_core_info core; sc = device_get_softc(dev); /* Requestor must be attached to the bhnd bus */ if (device_get_parent(child) != sc->bus_dev) { return (BHND_BUS_IS_HW_DISABLED(device_get_parent(dev), child)); } /* Fetch core info */ core = bhnd_get_core_info(child); /* Try to defer to the bhndb bus parent */ if (BHNDB_BUS_IS_CORE_DISABLED(sc->parent_dev, dev, &core)) return (true); /* Otherwise, we treat bridge-capable cores as unpopulated if they're * not the configured host bridge */ if (BHND_DEVCLASS_SUPPORTS_HOSTB(bhnd_core_class(&core))) return (BHNDB_FIND_HOSTB_DEVICE(dev, sc->bus_dev) != child); /* Otherwise, assume the core is populated */ return (false); } /* ascending core index comparison used by bhndb_find_hostb_device() */ static int compare_core_index(const void *lhs, const void *rhs) { u_int left = bhnd_get_core_index(*(const device_t *) lhs); u_int right = bhnd_get_core_index(*(const device_t *) rhs); if (left < right) return (-1); else if (left > right) return (1); else return (0); } /** * Default bhndb(4) implementation of BHND_BUS_FIND_HOSTB_DEVICE(). * * This function uses a heuristic valid on all known PCI/PCIe/PCMCIA-bridged * bhnd(4) devices to determine the hostb core: * * - The core must have a Broadcom vendor ID. * - The core devclass must match the bridge type. * - The core must be the first device on the bus with the bridged device * class. * * @param dev The bhndb device * @param child The requesting bhnd bus. */ static device_t bhndb_find_hostb_device(device_t dev, device_t child) { struct bhndb_softc *sc; struct bhnd_device_match md; device_t hostb_dev, *devlist; int devcnt, error; sc = device_get_softc(dev); /* Set up a match descriptor for the required device class. */ md = (struct bhnd_device_match) { BHND_MATCH_CORE_CLASS(sc->bridge_class), BHND_MATCH_CORE_UNIT(0) }; /* Must be the absolute first matching device on the bus. */ if ((error = device_get_children(child, &devlist, &devcnt))) return (false); /* Sort by core index value, ascending */ qsort(devlist, devcnt, sizeof(*devlist), compare_core_index); /* Find the hostb device */ hostb_dev = NULL; for (int i = 0; i < devcnt; i++) { if (bhnd_device_matches(devlist[i], &md)) { hostb_dev = devlist[i]; break; } } /* Clean up */ free(devlist, M_TEMP); return (hostb_dev); } /** * Default bhndb(4) implementation of BUS_ALLOC_RESOURCE(). */ static struct resource * bhndb_alloc_resource(device_t dev, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) { struct bhndb_softc *sc; struct resource_list_entry *rle; struct resource *rv; struct rman *rm; int error; bool passthrough, isdefault; sc = device_get_softc(dev); passthrough = (device_get_parent(child) != dev); isdefault = RMAN_IS_DEFAULT_RANGE(start, end); rle = NULL; /* Populate defaults */ if (!passthrough && isdefault) { /* Fetch the resource list entry. */ rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, *rid); if (rle == NULL) { device_printf(dev, "default resource %#x type %d for child %s " "not found\n", *rid, type, device_get_nameunit(child)); return (NULL); } if (rle->res != NULL) { device_printf(dev, "resource entry %#x type %d for child %s is busy\n", *rid, type, device_get_nameunit(child)); return (NULL); } start = rle->start; end = rle->end; count = ulmax(count, rle->count); } /* Validate resource addresses */ if (start > end || count > ((end - start) + 1)) return (NULL); /* Fetch the resource manager */ rm = bhndb_get_rman(sc, child, type); if (rm == NULL) return (NULL); /* Make our reservation */ rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, child); if (rv == NULL) return (NULL); rman_set_rid(rv, *rid); /* Activate */ if (flags & RF_ACTIVE) { error = bus_activate_resource(child, type, *rid, rv); if (error) { device_printf(dev, "failed to activate entry %#x type %d for " "child %s: %d\n", *rid, type, device_get_nameunit(child), error); rman_release_resource(rv); return (NULL); } } /* Update child's resource list entry */ if (rle != NULL) { rle->res = rv; rle->start = rman_get_start(rv); rle->end = rman_get_end(rv); rle->count = rman_get_size(rv); } return (rv); } /** * Default bhndb(4) implementation of BUS_RELEASE_RESOURCE(). */ static int bhndb_release_resource(device_t dev, device_t child, int type, int rid, struct resource *r) { struct resource_list_entry *rle; bool passthrough; int error; passthrough = (device_get_parent(child) != dev); /* Deactivate resources */ if (rman_get_flags(r) & RF_ACTIVE) { error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r); if (error) return (error); } if ((error = rman_release_resource(r))) return (error); if (!passthrough) { /* Clean resource list entry */ rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid); if (rle != NULL) rle->res = NULL; } return (0); } /** * Default bhndb(4) implementation of BUS_ADJUST_RESOURCE(). */ static int bhndb_adjust_resource(device_t dev, device_t child, int type, struct resource *r, rman_res_t start, rman_res_t end) { struct bhndb_softc *sc; struct rman *rm; rman_res_t mstart, mend; int error; sc = device_get_softc(dev); error = 0; /* Verify basic constraints */ if (end <= start) return (EINVAL); /* Fetch resource manager */ rm = bhndb_get_rman(sc, child, type); if (rm == NULL) return (ENXIO); if (!rman_is_region_manager(r, rm)) return (ENXIO); BHNDB_LOCK(sc); /* If not active, allow any range permitted by the resource manager */ if (!(rman_get_flags(r) & RF_ACTIVE)) goto done; /* Otherwise, the range is limited to the existing register window * mapping */ error = bhndb_find_resource_limits(sc->bus_res, r, &mstart, &mend); if (error) goto done; if (start < mstart || end > mend) { error = EINVAL; goto done; } /* Fall through */ done: if (!error) error = rman_adjust_resource(r, start, end); BHNDB_UNLOCK(sc); return (error); } /** * Initialize child resource @p r with a virtual address, tag, and handle * copied from @p parent, adjusted to contain only the range defined by * @p offsize and @p size. * * @param r The register to be initialized. * @param parent The parent bus resource that fully contains the subregion. * @param offset The subregion offset within @p parent. * @param size The subregion size. * @p r. */ static int bhndb_init_child_resource(struct resource *r, struct resource *parent, bhnd_size_t offset, bhnd_size_t size) { bus_space_handle_t bh, child_bh; bus_space_tag_t bt; uintptr_t vaddr; int error; /* Fetch the parent resource's real bus values */ vaddr = (uintptr_t) rman_get_virtual(parent); bt = rman_get_bustag(parent); bh = rman_get_bushandle(parent); /* Configure child resource with window-adjusted real bus values */ vaddr += offset; error = bus_space_subregion(bt, bh, offset, size, &child_bh); if (error) return (error); rman_set_virtual(r, (void *) vaddr); rman_set_bustag(r, bt); rman_set_bushandle(r, child_bh); return (0); } /** * Attempt activation of a fixed register window mapping for @p child. * * @param sc BHNDB device state. * @param region The static region definition capable of mapping @p r. * @param child A child requesting resource activation. * @param type Resource type. * @param rid Resource identifier. * @param r Resource to be activated. * * @retval 0 if @p r was activated successfully * @retval ENOENT if no fixed register window was found. * @retval non-zero if @p r could not be activated. */ static int bhndb_activate_static_region(struct bhndb_softc *sc, struct bhndb_region *region, device_t child, int type, int rid, struct resource *r) { struct resource *bridge_res; const struct bhndb_regwin *win; bhnd_size_t parent_offset; rman_res_t r_start, r_size; int error; win = region->static_regwin; KASSERT(win != NULL && BHNDB_REGWIN_T_IS_STATIC(win->win_type), ("can't activate non-static region")); r_start = rman_get_start(r); r_size = rman_get_size(r); /* Find the corresponding bridge resource */ bridge_res = bhndb_find_regwin_resource(sc->bus_res, win); if (bridge_res == NULL) return (ENXIO); /* Calculate subregion offset within the parent resource */ parent_offset = r_start - region->addr; parent_offset += win->win_offset; /* Configure resource with its real bus values. */ error = bhndb_init_child_resource(r, bridge_res, parent_offset, r_size); if (error) return (error); /* Mark active */ if ((error = rman_activate_resource(r))) return (error); return (0); } /** * Attempt to allocate/retain a dynamic register window for @p r, returning * the retained window. * * @param sc The bhndb driver state. * @param r The resource for which a window will be retained. */ static struct bhndb_dw_alloc * bhndb_retain_dynamic_window(struct bhndb_softc *sc, struct resource *r) { struct bhndb_dw_alloc *dwa; rman_res_t r_start, r_size; int error; BHNDB_LOCK_ASSERT(sc, MA_OWNED); r_start = rman_get_start(r); r_size = rman_get_size(r); /* Look for an existing dynamic window we can reference */ dwa = bhndb_dw_find_mapping(sc->bus_res, r_start, r_size); if (dwa != NULL) { if (bhndb_dw_retain(sc->bus_res, dwa, r) == 0) return (dwa); return (NULL); } /* Otherwise, try to reserve a free window */ dwa = bhndb_dw_next_free(sc->bus_res); if (dwa == NULL) { /* No free windows */ return (NULL); } /* Set the window target */ error = bhndb_dw_set_addr(sc->dev, sc->bus_res, dwa, rman_get_start(r), rman_get_size(r)); if (error) { device_printf(sc->dev, "dynamic window initialization " "for 0x%llx-0x%llx failed: %d\n", (unsigned long long) r_start, (unsigned long long) r_start + r_size - 1, error); return (NULL); } /* Add our reservation */ if (bhndb_dw_retain(sc->bus_res, dwa, r)) return (NULL); return (dwa); } /** * Activate a resource using any viable static or dynamic register window. * * @param sc The bhndb driver state. * @param child The child holding ownership of @p r. * @param type The type of the resource to be activated. * @param rid The resource ID of @p r. * @param r The resource to be activated * @param[out] indirect On error and if not NULL, will be set to 'true' if * the caller should instead use an indirect resource mapping. * * @retval 0 success * @retval non-zero activation failed. */ static int bhndb_try_activate_resource(struct bhndb_softc *sc, device_t child, int type, int rid, struct resource *r, bool *indirect) { struct bhndb_region *region; struct bhndb_dw_alloc *dwa; bhndb_priority_t dw_priority; rman_res_t r_start, r_size; rman_res_t parent_offset; int error; BHNDB_LOCK_ASSERT(sc, MA_NOTOWNED); // TODO - IRQs if (type != SYS_RES_MEMORY) return (ENXIO); if (indirect) *indirect = false; r_start = rman_get_start(r); r_size = rman_get_size(r); /* Activate native addrspace resources using the host address space */ if (bhndb_get_addrspace(sc, child) == BHNDB_ADDRSPACE_NATIVE) { struct resource *parent; /* Find the bridge resource referenced by the child */ parent = bhndb_find_resource_range(sc->bus_res, r_start, r_size); if (parent == NULL) { device_printf(sc->dev, "host resource not found " "for 0x%llx-0x%llx\n", (unsigned long long) r_start, (unsigned long long) r_start + r_size - 1); return (ENOENT); } /* Initialize child resource with the real bus values */ error = bhndb_init_child_resource(r, parent, r_start - rman_get_start(parent), r_size); if (error) return (error); /* Try to activate child resource */ return (rman_activate_resource(r)); } /* Default to low priority */ dw_priority = BHNDB_PRIORITY_LOW; /* Look for a bus region matching the resource's address range */ region = bhndb_find_resource_region(sc->bus_res, r_start, r_size); if (region != NULL) dw_priority = region->priority; /* Prefer static mappings over consuming a dynamic windows. */ if (region && region->static_regwin) { error = bhndb_activate_static_region(sc, region, child, type, rid, r); if (error) device_printf(sc->dev, "static window allocation " "for 0x%llx-0x%llx failed\n", (unsigned long long) r_start, (unsigned long long) r_start + r_size - 1); return (error); } /* A dynamic window will be required; is this resource high enough * priority to be reserved a dynamic window? */ if (dw_priority < sc->bus_res->min_prio) { if (indirect) *indirect = true; return (ENOMEM); } /* Find and retain a usable window */ BHNDB_LOCK(sc); { dwa = bhndb_retain_dynamic_window(sc, r); } BHNDB_UNLOCK(sc); if (dwa == NULL) { if (indirect) *indirect = true; return (ENOMEM); } /* Configure resource with its real bus values. */ parent_offset = dwa->win->win_offset; parent_offset += r_start - dwa->target; error = bhndb_init_child_resource(r, dwa->parent_res, parent_offset, dwa->win->win_size); if (error) goto failed; /* Mark active */ if ((error = rman_activate_resource(r))) goto failed; return (0); failed: /* Release our region allocation. */ BHNDB_LOCK(sc); bhndb_dw_release(sc->bus_res, dwa, r); BHNDB_UNLOCK(sc); return (error); } /** * Default bhndb(4) implementation of BUS_ACTIVATE_RESOURCE(). * * Maps resource activation requests to a viable static or dynamic * register window, if any. */ static int bhndb_activate_resource(device_t dev, device_t child, int type, int rid, struct resource *r) { struct bhndb_softc *sc = device_get_softc(dev); return (bhndb_try_activate_resource(sc, child, type, rid, r, NULL)); } /** * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE(). */ static int bhndb_deactivate_resource(device_t dev, device_t child, int type, int rid, struct resource *r) { struct bhndb_dw_alloc *dwa; struct bhndb_softc *sc; struct rman *rm; int error; sc = device_get_softc(dev); if ((rm = bhndb_get_rman(sc, child, type)) == NULL) return (EINVAL); /* Mark inactive */ if ((error = rman_deactivate_resource(r))) return (error); /* Free any dynamic window allocation. */ if (bhndb_get_addrspace(sc, child) == BHNDB_ADDRSPACE_BRIDGED) { BHNDB_LOCK(sc); dwa = bhndb_dw_find_resource(sc->bus_res, r); if (dwa != NULL) bhndb_dw_release(sc->bus_res, dwa, r); BHNDB_UNLOCK(sc); } return (0); } /** * Default bhndb(4) implementation of BUS_GET_RESOURCE_LIST(). */ static struct resource_list * bhndb_get_resource_list(device_t dev, device_t child) { struct bhndb_devinfo *dinfo = device_get_ivars(child); return (&dinfo->resources); } /** * Default bhndb(4) implementation of BHND_BUS_ACTIVATE_RESOURCE(). * * For BHNDB_ADDRSPACE_NATIVE children, all resources may be assumed to * be activated by the bridge. * * For BHNDB_ADDRSPACE_BRIDGED children, attempts to activate a static register * window, a dynamic register window, or configures @p r as an indirect * resource -- in that order. */ static int bhndb_activate_bhnd_resource(device_t dev, device_t child, int type, int rid, struct bhnd_resource *r) { struct bhndb_softc *sc; struct bhndb_region *region; rman_res_t r_start, r_size; int error; bool indirect; KASSERT(!r->direct, ("direct flag set on inactive resource")); KASSERT(!(rman_get_flags(r->res) & RF_ACTIVE), ("RF_ACTIVE set on inactive resource")); sc = device_get_softc(dev); r_start = rman_get_start(r->res); r_size = rman_get_size(r->res); /* Verify bridged address range's resource priority, and skip direct * allocation if the priority is too low. */ if (bhndb_get_addrspace(sc, child) == BHNDB_ADDRSPACE_BRIDGED) { bhndb_priority_t r_prio; region = bhndb_find_resource_region(sc->bus_res, r_start, r_size); if (region != NULL) r_prio = region->priority; else r_prio = BHNDB_PRIORITY_NONE; /* If less than the minimum dynamic window priority, this * resource should always be indirect. */ if (r_prio < sc->bus_res->min_prio) return (0); } /* Attempt direct activation */ error = bhndb_try_activate_resource(sc, child, type, rid, r->res, &indirect); if (!error) { r->direct = true; } else if (indirect) { /* The request was valid, but no viable register window is * available; indirection must be employed. */ error = 0; r->direct = false; } if (BHNDB_DEBUG(PRIO) && bhndb_get_addrspace(sc, child) == BHNDB_ADDRSPACE_BRIDGED) { device_printf(child, "activated 0x%llx-0x%llx as %s " "resource\n", (unsigned long long) r_start, (unsigned long long) r_start + r_size - 1, r->direct ? "direct" : "indirect"); } return (error); }; /** * Default bhndb(4) implementation of BHND_BUS_DEACTIVATE_RESOURCE(). */ static int bhndb_deactivate_bhnd_resource(device_t dev, device_t child, int type, int rid, struct bhnd_resource *r) { int error; /* Indirect resources don't require activation */ if (!r->direct) return (0); KASSERT(rman_get_flags(r->res) & RF_ACTIVE, ("RF_ACTIVE not set on direct resource")); /* Perform deactivation */ error = bus_deactivate_resource(child, type, rid, r->res); if (!error) r->direct = false; return (error); }; /** * Slow path for bhndb_io_resource(). * * Iterates over the existing allocated dynamic windows looking for a viable * in-use region; the first matching region is returned. */ static struct bhndb_dw_alloc * bhndb_io_resource_slow(struct bhndb_softc *sc, bus_addr_t addr, bus_size_t size, bus_size_t *offset) { struct bhndb_resources *br; struct bhndb_dw_alloc *dwa; BHNDB_LOCK_ASSERT(sc, MA_OWNED); br = sc->bus_res; /* Search for an existing dynamic mapping of this address range. * Static regions are not searched, as a statically mapped * region would never be allocated as an indirect resource. */ for (size_t i = 0; i < br->dwa_count; i++) { const struct bhndb_regwin *win; dwa = &br->dw_alloc[i]; win = dwa->win; KASSERT(win->win_type == BHNDB_REGWIN_T_DYN, ("invalid register window type")); /* Verify the range */ if (addr < dwa->target) continue; if (addr + size > dwa->target + win->win_size) continue; /* Found */ *offset = dwa->win->win_offset; *offset += addr - dwa->target; return (dwa); } /* not found */ return (NULL); } /** * Find the bridge resource to be used for I/O requests. * * @param sc Bridge driver state. * @param addr The I/O target address. * @param size The size of the I/O operation to be performed at @p addr. * @param[out] offset The offset within the returned resource at which * to perform the I/O request. */ static inline struct bhndb_dw_alloc * bhndb_io_resource(struct bhndb_softc *sc, bus_addr_t addr, bus_size_t size, bus_size_t *offset) { struct bhndb_resources *br; struct bhndb_dw_alloc *dwa; int error; BHNDB_LOCK_ASSERT(sc, MA_OWNED); br = sc->bus_res; /* Try to fetch a free window */ dwa = bhndb_dw_next_free(br); /* * If no dynamic windows are available, look for an existing * region that maps the target range. * * If none are found, this is a child driver bug -- our window * over-commit should only fail in the case where a child driver leaks * resources, or perform operations out-of-order. * * Broadcom HND chipsets are designed to not require register window * swapping during execution; as long as the child devices are * attached/detached correctly, using the hardware's required order * of operations, there should always be a window available for the * current operation. */ if (dwa == NULL) { dwa = bhndb_io_resource_slow(sc, addr, size, offset); if (dwa == NULL) { panic("register windows exhausted attempting to map " "0x%llx-0x%llx\n", (unsigned long long) addr, (unsigned long long) addr+size-1); } return (dwa); } /* Adjust the window if the I/O request won't fit in the current * target range. */ if (addr < dwa->target || addr > dwa->target + dwa->win->win_size || (dwa->target + dwa->win->win_size) - addr < size) { error = bhndb_dw_set_addr(sc->dev, sc->bus_res, dwa, addr, size); if (error) { panic("failed to set register window target mapping " "0x%llx-0x%llx\n", (unsigned long long) addr, (unsigned long long) addr+size-1); } } /* Calculate the offset and return */ *offset = (addr - dwa->target) + dwa->win->win_offset; return (dwa); } /* * BHND_BUS_(READ|WRITE_* implementations */ /* bhndb_bus_(read|write) common implementation */ #define BHNDB_IO_COMMON_SETUP(_io_size) \ struct bhndb_softc *sc; \ struct bhndb_dw_alloc *dwa; \ struct resource *io_res; \ bus_size_t io_offset; \ \ sc = device_get_softc(dev); \ \ BHNDB_LOCK(sc); \ dwa = bhndb_io_resource(sc, rman_get_start(r->res) + \ offset, _io_size, &io_offset); \ io_res = dwa->parent_res; \ \ KASSERT(!r->direct, \ ("bhnd_bus slow path used for direct resource")); \ \ KASSERT(rman_get_flags(io_res) & RF_ACTIVE, \ ("i/o resource is not active")); #define BHNDB_IO_COMMON_TEARDOWN() \ BHNDB_UNLOCK(sc); /* Defines a bhndb_bus_read_* method implementation */ #define BHNDB_IO_READ(_type, _name) \ static _type \ bhndb_bus_read_ ## _name (device_t dev, device_t child, \ struct bhnd_resource *r, bus_size_t offset) \ { \ _type v; \ BHNDB_IO_COMMON_SETUP(sizeof(_type)); \ v = bus_read_ ## _name (io_res, io_offset); \ BHNDB_IO_COMMON_TEARDOWN(); \ \ return (v); \ } /* Defines a bhndb_bus_write_* method implementation */ #define BHNDB_IO_WRITE(_type, _name) \ static void \ bhndb_bus_write_ ## _name (device_t dev, device_t child, \ struct bhnd_resource *r, bus_size_t offset, _type value) \ { \ BHNDB_IO_COMMON_SETUP(sizeof(_type)); \ bus_write_ ## _name (io_res, io_offset, value); \ BHNDB_IO_COMMON_TEARDOWN(); \ } /* Defines a bhndb_bus_(read|write|set)_(multi|region)_* method */ #define BHNDB_IO_MISC(_type, _ptr, _op, _size) \ static void \ bhndb_bus_ ## _op ## _ ## _size (device_t dev, \ device_t child, struct bhnd_resource *r, bus_size_t offset, \ _type _ptr datap, bus_size_t count) \ { \ BHNDB_IO_COMMON_SETUP(sizeof(_type) * count); \ bus_ ## _op ## _ ## _size (io_res, io_offset, \ datap, count); \ BHNDB_IO_COMMON_TEARDOWN(); \ } /* Defines a complete set of read/write methods */ #define BHNDB_IO_METHODS(_type, _size) \ BHNDB_IO_READ(_type, _size) \ BHNDB_IO_WRITE(_type, _size) \ \ BHNDB_IO_READ(_type, stream_ ## _size) \ BHNDB_IO_WRITE(_type, stream_ ## _size) \ \ BHNDB_IO_MISC(_type, *, read_multi, _size) \ BHNDB_IO_MISC(_type, *, write_multi, _size) \ \ BHNDB_IO_MISC(_type, *, read_multi_stream, _size) \ BHNDB_IO_MISC(_type, *, write_multi_stream, _size) \ \ BHNDB_IO_MISC(_type, , set_multi, _size) \ BHNDB_IO_MISC(_type, , set_region, _size) \ BHNDB_IO_MISC(_type, *, read_region, _size) \ BHNDB_IO_MISC(_type, *, write_region, _size) \ \ BHNDB_IO_MISC(_type, *, read_region_stream, _size) \ BHNDB_IO_MISC(_type, *, write_region_stream, _size) BHNDB_IO_METHODS(uint8_t, 1); BHNDB_IO_METHODS(uint16_t, 2); BHNDB_IO_METHODS(uint32_t, 4); /** * Default bhndb(4) implementation of BHND_BUS_BARRIER(). */ static void bhndb_bus_barrier(device_t dev, device_t child, struct bhnd_resource *r, bus_size_t offset, bus_size_t length, int flags) { BHNDB_IO_COMMON_SETUP(length); bus_barrier(io_res, io_offset + offset, length, flags); BHNDB_IO_COMMON_TEARDOWN(); } /** * Default bhndb(4) implementation of BUS_SETUP_INTR(). */ static int bhndb_setup_intr(device_t dev, device_t child, struct resource *r, int flags, driver_filter_t filter, driver_intr_t handler, void *arg, void **cookiep) { // TODO return (EOPNOTSUPP); } /** * Default bhndb(4) implementation of BUS_TEARDOWN_INTR(). */ static int bhndb_teardown_intr(device_t dev, device_t child, struct resource *r, void *cookie) { // TODO return (EOPNOTSUPP); } /** * Default bhndb(4) implementation of BUS_CONFIG_INTR(). */ static int bhndb_config_intr(device_t dev, int irq, enum intr_trigger trig, enum intr_polarity pol) { // TODO return (EOPNOTSUPP); } /** * Default bhndb(4) implementation of BUS_BIND_INTR(). */ static int bhndb_bind_intr(device_t dev, device_t child, struct resource *r, int cpu) { // TODO return (EOPNOTSUPP); } /** * Default bhndb(4) implementation of BUS_DESCRIBE_INTR(). */ static int bhndb_describe_intr(device_t dev, device_t child, struct resource *irq, void *cookie, const char *descr) { // TODO return (EOPNOTSUPP); } /** * Default bhndb(4) implementation of BUS_GET_DMA_TAG(). */ static bus_dma_tag_t bhndb_get_dma_tag(device_t dev, device_t child) { // TODO return (NULL); } static device_method_t bhndb_methods[] = { /* Device interface */ \ DEVMETHOD(device_probe, bhndb_generic_probe), DEVMETHOD(device_detach, bhndb_generic_detach), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD(device_suspend, bhndb_generic_suspend), DEVMETHOD(device_resume, bhndb_generic_resume), /* Bus interface */ DEVMETHOD(bus_probe_nomatch, bhndb_probe_nomatch), DEVMETHOD(bus_print_child, bhndb_print_child), DEVMETHOD(bus_child_pnpinfo_str, bhndb_child_pnpinfo_str), DEVMETHOD(bus_child_location_str, bhndb_child_location_str), DEVMETHOD(bus_add_child, bhndb_add_child), DEVMETHOD(bus_child_deleted, bhndb_child_deleted), DEVMETHOD(bus_alloc_resource, bhndb_alloc_resource), DEVMETHOD(bus_release_resource, bhndb_release_resource), DEVMETHOD(bus_activate_resource, bhndb_activate_resource), DEVMETHOD(bus_deactivate_resource, bhndb_deactivate_resource), DEVMETHOD(bus_setup_intr, bhndb_setup_intr), DEVMETHOD(bus_teardown_intr, bhndb_teardown_intr), DEVMETHOD(bus_config_intr, bhndb_config_intr), DEVMETHOD(bus_bind_intr, bhndb_bind_intr), DEVMETHOD(bus_describe_intr, bhndb_describe_intr), DEVMETHOD(bus_get_dma_tag, bhndb_get_dma_tag), DEVMETHOD(bus_adjust_resource, bhndb_adjust_resource), DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), DEVMETHOD(bus_get_resource_list, bhndb_get_resource_list), DEVMETHOD(bus_read_ivar, bhndb_read_ivar), DEVMETHOD(bus_write_ivar, bhndb_write_ivar), /* BHNDB interface */ DEVMETHOD(bhndb_get_chipid, bhndb_get_chipid), DEVMETHOD(bhndb_init_full_config, bhndb_generic_init_full_config), DEVMETHOD(bhndb_find_hostb_device, bhndb_find_hostb_device), DEVMETHOD(bhndb_suspend_resource, bhndb_suspend_resource), DEVMETHOD(bhndb_resume_resource, bhndb_resume_resource), /* BHND interface */ DEVMETHOD(bhnd_bus_is_hw_disabled, bhndb_is_hw_disabled), DEVMETHOD(bhnd_bus_get_chipid, bhndb_get_chipid), DEVMETHOD(bhnd_bus_activate_resource, bhndb_activate_bhnd_resource), DEVMETHOD(bhnd_bus_deactivate_resource, bhndb_deactivate_bhnd_resource), DEVMETHOD(bhnd_bus_get_nvram_var, bhnd_bus_generic_get_nvram_var), DEVMETHOD(bhnd_bus_read_1, bhndb_bus_read_1), DEVMETHOD(bhnd_bus_read_2, bhndb_bus_read_2), DEVMETHOD(bhnd_bus_read_4, bhndb_bus_read_4), DEVMETHOD(bhnd_bus_write_1, bhndb_bus_write_1), DEVMETHOD(bhnd_bus_write_2, bhndb_bus_write_2), DEVMETHOD(bhnd_bus_write_4, bhndb_bus_write_4), DEVMETHOD(bhnd_bus_read_stream_1, bhndb_bus_read_stream_1), DEVMETHOD(bhnd_bus_read_stream_2, bhndb_bus_read_stream_2), DEVMETHOD(bhnd_bus_read_stream_4, bhndb_bus_read_stream_4), DEVMETHOD(bhnd_bus_write_stream_1, bhndb_bus_write_stream_1), DEVMETHOD(bhnd_bus_write_stream_2, bhndb_bus_write_stream_2), DEVMETHOD(bhnd_bus_write_stream_4, bhndb_bus_write_stream_4), DEVMETHOD(bhnd_bus_read_multi_1, bhndb_bus_read_multi_1), DEVMETHOD(bhnd_bus_read_multi_2, bhndb_bus_read_multi_2), DEVMETHOD(bhnd_bus_read_multi_4, bhndb_bus_read_multi_4), DEVMETHOD(bhnd_bus_write_multi_1, bhndb_bus_write_multi_1), DEVMETHOD(bhnd_bus_write_multi_2, bhndb_bus_write_multi_2), DEVMETHOD(bhnd_bus_write_multi_4, bhndb_bus_write_multi_4), DEVMETHOD(bhnd_bus_read_multi_stream_1, bhndb_bus_read_multi_stream_1), DEVMETHOD(bhnd_bus_read_multi_stream_2, bhndb_bus_read_multi_stream_2), DEVMETHOD(bhnd_bus_read_multi_stream_4, bhndb_bus_read_multi_stream_4), DEVMETHOD(bhnd_bus_write_multi_stream_1,bhndb_bus_write_multi_stream_1), DEVMETHOD(bhnd_bus_write_multi_stream_2,bhndb_bus_write_multi_stream_2), DEVMETHOD(bhnd_bus_write_multi_stream_4,bhndb_bus_write_multi_stream_4), DEVMETHOD(bhnd_bus_set_multi_1, bhndb_bus_set_multi_1), DEVMETHOD(bhnd_bus_set_multi_2, bhndb_bus_set_multi_2), DEVMETHOD(bhnd_bus_set_multi_4, bhndb_bus_set_multi_4), DEVMETHOD(bhnd_bus_set_region_1, bhndb_bus_set_region_1), DEVMETHOD(bhnd_bus_set_region_2, bhndb_bus_set_region_2), DEVMETHOD(bhnd_bus_set_region_4, bhndb_bus_set_region_4), DEVMETHOD(bhnd_bus_read_region_1, bhndb_bus_read_region_1), DEVMETHOD(bhnd_bus_read_region_2, bhndb_bus_read_region_2), DEVMETHOD(bhnd_bus_read_region_4, bhndb_bus_read_region_4), DEVMETHOD(bhnd_bus_write_region_1, bhndb_bus_write_region_1), DEVMETHOD(bhnd_bus_write_region_2, bhndb_bus_write_region_2), DEVMETHOD(bhnd_bus_write_region_4, bhndb_bus_write_region_4), DEVMETHOD(bhnd_bus_read_region_stream_1,bhndb_bus_read_region_stream_1), DEVMETHOD(bhnd_bus_read_region_stream_2,bhndb_bus_read_region_stream_2), DEVMETHOD(bhnd_bus_read_region_stream_4,bhndb_bus_read_region_stream_4), DEVMETHOD(bhnd_bus_write_region_stream_1,bhndb_bus_write_region_stream_1), DEVMETHOD(bhnd_bus_write_region_stream_2,bhndb_bus_write_region_stream_2), DEVMETHOD(bhnd_bus_write_region_stream_4,bhndb_bus_write_region_stream_4), DEVMETHOD(bhnd_bus_barrier, bhndb_bus_barrier), DEVMETHOD_END }; devclass_t bhndb_devclass; DEFINE_CLASS_0(bhndb, bhndb_driver, bhndb_methods, sizeof(struct bhndb_softc)); MODULE_VERSION(bhndb, 1); MODULE_DEPEND(bhndb, bhnd, 1, 1, 1); -MODULE_DEPEND(bhndb, bhnd_chipc, 1, 1, 1); Index: head/sys/dev/bhnd/bhndb/bhndb_pci.c =================================================================== --- head/sys/dev/bhnd/bhndb/bhndb_pci.c (revision 304869) +++ head/sys/dev/bhnd/bhndb/bhndb_pci.c (revision 304870) @@ -1,633 +1,695 @@ /*- * Copyright (c) 2015-2016 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); /* * PCI-specific implementation for the BHNDB bridge driver. * * Provides support for bridging from a PCI parent bus to a BHND-compatible * bus (e.g. bcma or siba) via a Broadcom PCI core configured in end-point * mode. * * This driver handles all initial generic host-level PCI interactions with a * PCI/PCIe bridge core operating in endpoint mode. Once the bridged bhnd(4) * bus has been enumerated, this driver works in tandem with a core-specific * bhnd_pci_hostb driver to manage the PCI core. */ #include #include #include #include #include #include #include #include #include #include #include #include "bhndb_pcireg.h" #include "bhndb_pcivar.h" #include "bhndb_private.h" static int bhndb_enable_pci_clocks(struct bhndb_pci_softc *sc); static int bhndb_disable_pci_clocks(struct bhndb_pci_softc *sc); static int bhndb_pci_compat_setregwin(struct bhndb_pci_softc *, const struct bhndb_regwin *, bhnd_addr_t); static int bhndb_pci_fast_setregwin(struct bhndb_pci_softc *, const struct bhndb_regwin *, bhnd_addr_t); static void bhndb_init_sromless_pci_config( struct bhndb_pci_softc *sc); static bus_addr_t bhndb_pci_sprom_addr(struct bhndb_pci_softc *sc); static bus_size_t bhndb_pci_sprom_size(struct bhndb_pci_softc *sc); /** * Default bhndb_pci implementation of device_probe(). * * Verifies that the parent is a PCI/PCIe device. */ static int bhndb_pci_probe(device_t dev) { device_t parent; devclass_t parent_bus; devclass_t pci; /* Our parent must be a PCI/PCIe device. */ pci = devclass_find("pci"); parent = device_get_parent(dev); parent_bus = device_get_devclass(device_get_parent(parent)); if (parent_bus != pci) return (ENXIO); device_set_desc(dev, "PCI-BHND bridge"); return (BUS_PROBE_DEFAULT); } static int bhndb_pci_attach(device_t dev) { struct bhndb_pci_softc *sc; int error, reg; sc = device_get_softc(dev); sc->dev = dev; sc->parent = device_get_parent(dev); /* Enable PCI bus mastering */ pci_enable_busmaster(sc->parent); /* Determine our bridge device class */ sc->pci_devclass = BHND_DEVCLASS_PCI; if (pci_find_cap(sc->parent, PCIY_EXPRESS, ®) == 0) sc->pci_devclass = BHND_DEVCLASS_PCIE; /* Enable clocks (if supported by this hardware) */ if ((error = bhndb_enable_pci_clocks(sc))) return (error); /* Use siba(4)-compatible regwin handling until we know * what kind of bus is attached */ sc->set_regwin = bhndb_pci_compat_setregwin; /* Perform full bridge attach. This should call back into our * bhndb_pci_init_full_config() implementation once the bridged * bhnd(4) bus has been enumerated, but before any devices have been * probed or attached. */ if ((error = bhndb_attach(dev, sc->pci_devclass))) return (error); /* If supported, switch to the faster regwin handling */ if (sc->bhndb.chipid.chip_type != BHND_CHIPTYPE_SIBA) { atomic_store_rel_ptr((volatile void *) &sc->set_regwin, (uintptr_t) &bhndb_pci_fast_setregwin); } return (0); } static int bhndb_pci_init_full_config(device_t dev, device_t child, const struct bhndb_hw_priority *hw_prio_table) { struct bhndb_pci_softc *sc; device_t nv_dev; bus_size_t nv_sz; int error; sc = device_get_softc(dev); /* Let our parent perform standard initialization first */ if ((error = bhndb_generic_init_full_config(dev, child, hw_prio_table))) return (error); /* Fix-up power on defaults for SROM-less devices. */ bhndb_init_sromless_pci_config(sc); /* If SPROM is mapped directly into BAR0, add NVRAM device. */ nv_sz = bhndb_pci_sprom_size(sc); if (nv_sz > 0) { struct bhndb_devinfo *dinfo; const char *dname; if (bootverbose) { device_printf(dev, "found SPROM (%u bytes)\n", (unsigned int) nv_sz); } /* Add sprom device */ dname = "bhnd_nvram"; if ((nv_dev = BUS_ADD_CHILD(dev, 0, dname, -1)) == NULL) { device_printf(dev, "failed to add sprom device\n"); return (ENXIO); } /* Initialize device address space and resource covering the * BAR0 SPROM shadow. */ dinfo = device_get_ivars(nv_dev); dinfo->addrspace = BHNDB_ADDRSPACE_NATIVE; error = bus_set_resource(nv_dev, SYS_RES_MEMORY, 0, bhndb_pci_sprom_addr(sc), nv_sz); if (error) { device_printf(dev, "failed to register sprom resources\n"); return (error); } /* Attach the device */ if ((error = device_probe_and_attach(nv_dev))) { device_printf(dev, "sprom attach failed\n"); return (error); } } return (0); } static const struct bhndb_regwin * bhndb_pci_sprom_regwin(struct bhndb_pci_softc *sc) { struct bhndb_resources *bres; const struct bhndb_hwcfg *cfg; const struct bhndb_regwin *sprom_win; bres = sc->bhndb.bus_res; cfg = bres->cfg; sprom_win = bhndb_regwin_find_type(cfg->register_windows, BHNDB_REGWIN_T_SPROM, BHNDB_PCI_V0_BAR0_SPROM_SIZE); return (sprom_win); } static bus_addr_t bhndb_pci_sprom_addr(struct bhndb_pci_softc *sc) { const struct bhndb_regwin *sprom_win; struct resource *r; /* Fetch the SPROM register window */ sprom_win = bhndb_pci_sprom_regwin(sc); KASSERT(sprom_win != NULL, ("requested sprom address on PCI_V2+")); /* Fetch the associated resource */ r = bhndb_find_regwin_resource(sc->bhndb.bus_res, sprom_win); KASSERT(r != NULL, ("missing resource for sprom window\n")); return (rman_get_start(r) + sprom_win->win_offset); } static bus_size_t bhndb_pci_sprom_size(struct bhndb_pci_softc *sc) { const struct bhndb_regwin *sprom_win; uint32_t sctl; bus_size_t sprom_sz; sprom_win = bhndb_pci_sprom_regwin(sc); /* PCI_V2 and later devices map SPROM/OTP via ChipCommon */ if (sprom_win == NULL) return (0); /* Determine SPROM size */ sctl = pci_read_config(sc->parent, BHNDB_PCI_SPROM_CONTROL, 4); if (sctl & BHNDB_PCI_SPROM_BLANK) return (0); switch (sctl & BHNDB_PCI_SPROM_SZ_MASK) { case BHNDB_PCI_SPROM_SZ_1KB: sprom_sz = (1 * 1024); break; case BHNDB_PCI_SPROM_SZ_4KB: sprom_sz = (4 * 1024); break; case BHNDB_PCI_SPROM_SZ_16KB: sprom_sz = (16 * 1024); break; case BHNDB_PCI_SPROM_SZ_RESERVED: default: device_printf(sc->dev, "invalid PCI sprom size 0x%x\n", sctl); return (0); } if (sprom_sz > sprom_win->win_size) { device_printf(sc->dev, "PCI sprom size (0x%x) overruns defined register window\n", sctl); return (0); } return (sprom_sz); } /* * On devices without a SROM, the PCI(e) cores will be initialized with * their Power-on-Reset defaults; this can leave two of the BAR0 PCI windows * mapped to the wrong core. * * This function updates the SROM shadow to point the BAR0 windows at the * current PCI core. * * Applies to all PCI/PCIe revisions. */ static void bhndb_init_sromless_pci_config(struct bhndb_pci_softc *sc) { struct bhndb_resources *bres; const struct bhndb_hwcfg *cfg; const struct bhndb_regwin *win; struct resource *core_regs; bus_size_t srom_offset; u_int pci_cidx, sprom_cidx; uint16_t val; bres = sc->bhndb.bus_res; cfg = bres->cfg; if (bhnd_get_vendor(sc->bhndb.hostb_dev) != BHND_MFGID_BCM) return; switch (bhnd_get_device(sc->bhndb.hostb_dev)) { case BHND_COREID_PCI: srom_offset = BHND_PCI_SRSH_PI_OFFSET; break; case BHND_COREID_PCIE: srom_offset = BHND_PCIE_SRSH_PI_OFFSET; break; default: device_printf(sc->dev, "unsupported PCI host bridge device\n"); return; } /* Locate the static register window mapping the PCI core */ win = bhndb_regwin_find_core(cfg->register_windows, sc->pci_devclass, 0, BHND_PORT_DEVICE, 0, 0); if (win == NULL) { device_printf(sc->dev, "missing PCI core register window\n"); return; } /* Fetch the resource containing the register window */ core_regs = bhndb_find_regwin_resource(bres, win); if (core_regs == NULL) { device_printf(sc->dev, "missing PCI core register resource\n"); return; } /* Fetch the SPROM's configured core index */ val = bus_read_2(core_regs, win->win_offset + srom_offset); sprom_cidx = (val & BHND_PCI_SRSH_PI_MASK) >> BHND_PCI_SRSH_PI_SHIFT; /* If it doesn't match host bridge's core index, update the index * value */ pci_cidx = bhnd_get_core_index(sc->bhndb.hostb_dev); if (sprom_cidx != pci_cidx) { val &= ~BHND_PCI_SRSH_PI_MASK; val |= (pci_cidx << BHND_PCI_SRSH_PI_SHIFT); bus_write_2(core_regs, win->win_offset + srom_offset, val); } } static int bhndb_pci_resume(device_t dev) { struct bhndb_pci_softc *sc; int error; sc = device_get_softc(dev); /* Enable clocks (if supported by this hardware) */ if ((error = bhndb_enable_pci_clocks(sc))) return (error); /* Perform resume */ return (bhndb_generic_resume(dev)); } static int bhndb_pci_suspend(device_t dev) { struct bhndb_pci_softc *sc; int error; sc = device_get_softc(dev); /* Disable clocks (if supported by this hardware) */ if ((error = bhndb_disable_pci_clocks(sc))) return (error); /* Perform suspend */ return (bhndb_generic_suspend(dev)); } static int bhndb_pci_detach(device_t dev) { struct bhndb_pci_softc *sc; int error; sc = device_get_softc(dev); /* Disable clocks (if supported by this hardware) */ if ((error = bhndb_disable_pci_clocks(sc))) return (error); /* Perform detach */ if ((error = bhndb_generic_detach(dev))) return (error); /* Disable PCI bus mastering */ pci_disable_busmaster(sc->parent); return (0); } static int bhndb_pci_set_window_addr(device_t dev, const struct bhndb_regwin *rw, bhnd_addr_t addr) { struct bhndb_pci_softc *sc = device_get_softc(dev); return (sc->set_regwin(sc, rw, addr)); } /** * A siba(4) and bcma(4)-compatible bhndb_set_window_addr implementation. * * On siba(4) devices, it's possible that writing a PCI window register may * not succeed; it's necessary to immediately read the configuration register * and retry if not set to the desired value. * * This is not necessary on bcma(4) devices, but other than the overhead of * validating the register, there's no harm in performing the verification. */ static int bhndb_pci_compat_setregwin(struct bhndb_pci_softc *sc, const struct bhndb_regwin *rw, bhnd_addr_t addr) { int error; int reg; if (rw->win_type != BHNDB_REGWIN_T_DYN) return (ENODEV); reg = rw->d.dyn.cfg_offset; for (u_int i = 0; i < BHNDB_PCI_BARCTRL_WRITE_RETRY; i++) { if ((error = bhndb_pci_fast_setregwin(sc, rw, addr))) return (error); if (pci_read_config(sc->parent, reg, 4) == addr) return (0); DELAY(10); } /* Unable to set window */ return (ENODEV); } /** * A bcma(4)-only bhndb_set_window_addr implementation. */ static int bhndb_pci_fast_setregwin(struct bhndb_pci_softc *sc, const struct bhndb_regwin *rw, bhnd_addr_t addr) { /* The PCI bridge core only supports 32-bit addressing, regardless * of the bus' support for 64-bit addressing */ if (addr > UINT32_MAX) return (ERANGE); switch (rw->win_type) { case BHNDB_REGWIN_T_DYN: /* Addresses must be page aligned */ if (addr % rw->win_size != 0) return (EINVAL); pci_write_config(sc->parent, rw->d.dyn.cfg_offset, addr, 4); break; default: return (ENODEV); } return (0); } static int bhndb_pci_populate_board_info(device_t dev, device_t child, struct bhnd_board_info *info) { struct bhndb_pci_softc *sc; sc = device_get_softc(dev); /* * On a subset of Apple BCM4360 modules, always prefer the * PCI subdevice to the SPROM-supplied boardtype. * * TODO: * * Broadcom's own drivers implement this override, and then later use * the remapped BCM4360 board type to determine the required * board-specific workarounds. * * Without access to this hardware, it's unclear why this mapping * is done, and we must do the same. If we can survey the hardware * in question, it may be possible to replace this behavior with * explicit references to the SPROM-supplied boardtype(s) in our * quirk definitions. */ if (pci_get_subvendor(sc->parent) == PCI_VENDOR_APPLE) { switch (info->board_type) { case BHND_BOARD_BCM94360X29C: case BHND_BOARD_BCM94360X29CP2: case BHND_BOARD_BCM94360X51: case BHND_BOARD_BCM94360X51P2: info->board_type = 0; /* allow override below */ break; default: break; } } /* If NVRAM did not supply vendor/type info, provide the PCI * subvendor/subdevice values. */ if (info->board_vendor == 0) info->board_vendor = pci_get_subvendor(sc->parent); if (info->board_type == 0) info->board_type = pci_get_subdevice(sc->parent); return (0); } /** * Enable externally managed clocks, if required. * * Some PCI chipsets (BCM4306, possibly others) chips do not support * the idle low-power clock. Clocking must be bootstrapped at * attach/resume by directly adjusting GPIO registers exposed in the * PCI config space, and correspondingly, explicitly shutdown at * detach/suspend. * * @param sc Bridge driver state. */ static int bhndb_enable_pci_clocks(struct bhndb_pci_softc *sc) { uint32_t gpio_in, gpio_out, gpio_en; uint32_t gpio_flags; uint16_t pci_status; /* Only supported and required on PCI devices */ if (sc->pci_devclass != BHND_DEVCLASS_PCI) return (0); /* Read state of XTAL pin */ gpio_in = pci_read_config(sc->parent, BHNDB_PCI_GPIO_IN, 4); if (gpio_in & BHNDB_PCI_GPIO_XTAL_ON) return (0); /* already enabled */ /* Fetch current config */ gpio_out = pci_read_config(sc->parent, BHNDB_PCI_GPIO_OUT, 4); gpio_en = pci_read_config(sc->parent, BHNDB_PCI_GPIO_OUTEN, 4); /* Set PLL_OFF/XTAL_ON pins to HIGH and enable both pins */ gpio_flags = (BHNDB_PCI_GPIO_PLL_OFF|BHNDB_PCI_GPIO_XTAL_ON); gpio_out |= gpio_flags; gpio_en |= gpio_flags; pci_write_config(sc->parent, BHNDB_PCI_GPIO_OUT, gpio_out, 4); pci_write_config(sc->parent, BHNDB_PCI_GPIO_OUTEN, gpio_en, 4); DELAY(1000); /* Reset PLL_OFF */ gpio_out &= ~BHNDB_PCI_GPIO_PLL_OFF; pci_write_config(sc->parent, BHNDB_PCI_GPIO_OUT, gpio_out, 4); DELAY(5000); /* Clear any PCI 'sent target-abort' flag. */ pci_status = pci_read_config(sc->parent, PCIR_STATUS, 2); pci_status &= ~PCIM_STATUS_STABORT; pci_write_config(sc->parent, PCIR_STATUS, pci_status, 2); return (0); } /** * Disable externally managed clocks, if required. * * @param sc Bridge driver state. */ static int bhndb_disable_pci_clocks(struct bhndb_pci_softc *sc) { uint32_t gpio_out, gpio_en; /* Only supported and required on PCI devices */ if (sc->pci_devclass != BHND_DEVCLASS_PCI) return (0); /* Fetch current config */ gpio_out = pci_read_config(sc->parent, BHNDB_PCI_GPIO_OUT, 4); gpio_en = pci_read_config(sc->parent, BHNDB_PCI_GPIO_OUTEN, 4); /* Set PLL_OFF to HIGH, XTAL_ON to LOW. */ gpio_out &= ~BHNDB_PCI_GPIO_XTAL_ON; gpio_out |= BHNDB_PCI_GPIO_PLL_OFF; pci_write_config(sc->parent, BHNDB_PCI_GPIO_OUT, gpio_out, 4); /* Enable both output pins */ gpio_en |= (BHNDB_PCI_GPIO_PLL_OFF|BHNDB_PCI_GPIO_XTAL_ON); pci_write_config(sc->parent, BHNDB_PCI_GPIO_OUTEN, gpio_en, 4); return (0); } +static bhnd_clksrc +bhndb_pci_pwrctl_get_clksrc(device_t dev, device_t child, + bhnd_clock clock) +{ + struct bhndb_pci_softc *sc; + uint32_t gpio_out; + + sc = device_get_softc(dev); + + /* Only supported on PCI devices */ + if (sc->pci_devclass != BHND_DEVCLASS_PCI) + return (ENODEV); + + /* Only ILP is supported */ + if (clock != BHND_CLOCK_ILP) + return (ENXIO); + + gpio_out = pci_read_config(sc->parent, BHNDB_PCI_GPIO_OUT, 4); + if (gpio_out & BHNDB_PCI_GPIO_SCS) + return (BHND_CLKSRC_PCI); + else + return (BHND_CLKSRC_XTAL); +} + +static int +bhndb_pci_pwrctl_gate_clock(device_t dev, device_t child, + bhnd_clock clock) +{ + struct bhndb_pci_softc *sc = device_get_softc(dev); + + /* Only supported on PCI devices */ + if (sc->pci_devclass != BHND_DEVCLASS_PCI) + return (ENODEV); + + /* Only HT is supported */ + if (clock != BHND_CLOCK_HT) + return (ENXIO); + + return (bhndb_disable_pci_clocks(sc)); +} + +static int +bhndb_pci_pwrctl_ungate_clock(device_t dev, device_t child, + bhnd_clock clock) +{ + struct bhndb_pci_softc *sc = device_get_softc(dev); + + /* Only supported on PCI devices */ + if (sc->pci_devclass != BHND_DEVCLASS_PCI) + return (ENODEV); + + /* Only HT is supported */ + if (clock != BHND_CLOCK_HT) + return (ENXIO); + + return (bhndb_enable_pci_clocks(sc)); +} + static device_method_t bhndb_pci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, bhndb_pci_probe), DEVMETHOD(device_attach, bhndb_pci_attach), DEVMETHOD(device_resume, bhndb_pci_resume), DEVMETHOD(device_suspend, bhndb_pci_suspend), DEVMETHOD(device_detach, bhndb_pci_detach), + /* BHND interface */ + DEVMETHOD(bhnd_bus_pwrctl_get_clksrc, bhndb_pci_pwrctl_get_clksrc), + DEVMETHOD(bhnd_bus_pwrctl_gate_clock, bhndb_pci_pwrctl_gate_clock), + DEVMETHOD(bhnd_bus_pwrctl_ungate_clock, bhndb_pci_pwrctl_ungate_clock), + /* BHNDB interface */ DEVMETHOD(bhndb_init_full_config, bhndb_pci_init_full_config), DEVMETHOD(bhndb_set_window_addr, bhndb_pci_set_window_addr), DEVMETHOD(bhndb_populate_board_info, bhndb_pci_populate_board_info), DEVMETHOD_END }; DEFINE_CLASS_1(bhndb, bhndb_pci_driver, bhndb_pci_methods, sizeof(struct bhndb_pci_softc), bhndb_driver); MODULE_VERSION(bhndb_pci, 1); MODULE_DEPEND(bhndb_pci, bhnd_pci_hostb, 1, 1, 1); -MODULE_DEPEND(bhndb_pci, bhnd_pcie2_hostb, 1, 1, 1); MODULE_DEPEND(bhndb_pci, pci, 1, 1, 1); MODULE_DEPEND(bhndb_pci, bhndb, 1, 1, 1); MODULE_DEPEND(bhndb_pci, bhnd, 1, 1, 1); Index: head/sys/dev/bhnd/bhndvar.h =================================================================== --- head/sys/dev/bhnd/bhndvar.h (revision 304869) +++ head/sys/dev/bhnd/bhndvar.h (revision 304870) @@ -1,97 +1,115 @@ /*- - * Copyright (c) 2015 Landon Fuller + * Copyright (c) 2015-2016 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. * * $FreeBSD$ */ #ifndef _BHND_BHNDVAR_H_ #define _BHND_BHNDVAR_H_ #include #include #include #include "bhnd.h" /* * Definitions shared by bhnd(4) bus and bhndb(4) bridge driver implementations. */ MALLOC_DECLARE(M_BHND); DECLARE_CLASS(bhnd_driver); -/** - * bhnd per-device info. Must be first member of all subclass - * devinfo structures. - */ -struct bhnd_devinfo { -}; +struct bhnd_core_pmu_info; -/** - * bhnd driver instance state. Must be first member of all subclass - * softc structures. - */ -struct bhnd_softc { - device_t dev; /**< bus device */ - - bool attach_done; /**< true if initialization of all - * platform devices has been - * completed */ - device_t chipc_dev; /**< bhnd_chipc device */ - device_t nvram_dev; /**< bhnd_nvram device, if any */ - device_t pmu_dev; /**< bhnd_pmu device, if any */ -}; - int bhnd_generic_attach(device_t dev); int bhnd_generic_detach(device_t dev); int bhnd_generic_shutdown(device_t dev); int bhnd_generic_resume(device_t dev); int bhnd_generic_suspend(device_t dev); int bhnd_generic_get_probe_order(device_t dev, device_t child); +int bhnd_generic_alloc_pmu(device_t dev, + device_t child); +int bhnd_generic_release_pmu(device_t dev, + device_t child); +int bhnd_generic_request_clock(device_t dev, + device_t child, bhnd_clock clock); +int bhnd_generic_enable_clocks(device_t dev, + device_t child, uint32_t clocks); +int bhnd_generic_request_ext_rsrc(device_t dev, + device_t child, u_int rsrc); +int bhnd_generic_release_ext_rsrc(device_t dev, + device_t child, u_int rsrc); + int bhnd_generic_print_child(device_t dev, device_t child); void bhnd_generic_probe_nomatch(device_t dev, device_t child); device_t bhnd_generic_add_child(device_t dev, u_int order, const char *name, int unit); +void bhnd_generic_child_added(device_t dev, device_t child); void bhnd_generic_child_deleted(device_t dev, device_t child); int bhnd_generic_suspend_child(device_t dev, device_t child); int bhnd_generic_resume_child(device_t dev, device_t child); int bhnd_generic_get_nvram_var(device_t dev, device_t child, const char *name, void *buf, size_t *size, bhnd_nvram_type type); + + +/** + * bhnd per-device info. Must be first member of all subclass + * devinfo structures. + */ +struct bhnd_devinfo { + struct bhnd_core_pmu_info *pmu_info; /**< PMU info, or NULL */ +}; + +/** + * bhnd driver instance state. Must be first member of all subclass + * softc structures. + */ +struct bhnd_softc { + device_t dev; /**< bus device */ + + bool attach_done; /**< true if initialization of + * all platform devices has + * been completed */ + device_t chipc_dev; /**< bhnd_chipc device */ + device_t nvram_dev; /**< bhnd_nvram device, if any */ + device_t pmu_dev; /**< bhnd_pmu device, if any */ +}; #endif /* _BHND_BHNDVAR_H_ */ Index: head/sys/dev/bhnd/cores/chipc/bhnd_chipc_if.m =================================================================== --- head/sys/dev/bhnd/cores/chipc/bhnd_chipc_if.m (revision 304869) +++ head/sys/dev/bhnd/cores/chipc/bhnd_chipc_if.m (revision 304870) @@ -1,100 +1,116 @@ #- # Copyright (c) 2016 Landon Fuller # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions # are met: # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. # IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, # INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # $FreeBSD$ #include #include #include INTERFACE bhnd_chipc; # # bhnd(4) ChipCommon interface. # HEADER { /* forward declarations */ struct chipc_caps; } CODE { static struct chipc_caps * bhnd_chipc_null_get_caps(device_t dev) { panic("bhnd_chipc_generic_get_caps unimplemented"); } } + +/** + * Return the current value of the chipstatus register. + * + * @param dev A bhnd(4) ChipCommon device. + * + * Drivers should only use function for functionality that is not + * available via another bhnd_chipc() function. + * + * @returns The chipstatus register value, or 0 if undefined by this + * hardware (e.g. if @p dev is an EXTIF core). + */ +METHOD uint32_t read_chipst { + device_t dev; +} + /** * Write @p value with @p mask directly to the chipctrl register. * * @param dev A bhnd(4) ChipCommon device. * @param value The value to write. * @param mask The mask of bits to be written from @p value. * * Drivers should only use function for functionality that is not * available via another bhnd_chipc() function. * * Currently, the only known valid use-case is in implementing a hardware * work-around for the BCM4321 PCIe rev7 core revision. */ METHOD void write_chipctrl { device_t dev; uint32_t value; uint32_t mask; } /** * Return a borrowed reference to ChipCommon's capability * table. * * @param dev A bhnd(4) ChipCommon device */ METHOD struct chipc_caps * get_caps { device_t dev; } DEFAULT bhnd_chipc_null_get_caps; /** * Enable hardware access to the SPROM/OTP source. * * @param sc chipc driver state. * * @retval 0 success * @retval EBUSY If enabling the hardware may conflict with * other active devices. */ METHOD int enable_sprom { device_t dev; } /** * Release hardware access to the SPROM/OTP source. * * @param sc chipc driver state. */ METHOD void disable_sprom { device_t dev; } Index: head/sys/dev/bhnd/cores/chipc/bhnd_pmu_chipc.c =================================================================== --- head/sys/dev/bhnd/cores/chipc/bhnd_pmu_chipc.c (nonexistent) +++ head/sys/dev/bhnd/cores/chipc/bhnd_pmu_chipc.c (revision 304870) @@ -0,0 +1,126 @@ +/*- + * Copyright (c) 2016 Landon Fuller + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + */ + +#include +__FBSDID("$FreeBSD$"); + +/* + * ChipCommon attachment support for the bhnd(4) PMU driver. + * + * Supports non-AOB ("Always-on Bus") devices that map the PMU register blocks + * via the ChipCommon core, rather than vending a distinct PMU core on the + * bhnd bus. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include "bhnd_chipc_if.h" +#include "bhnd_pmu_if.h" + +#include "chipcvar.h" + +static int +bhnd_pmu_chipc_probe(device_t dev) +{ + struct bhnd_pmu_softc *sc; + struct chipc_caps *ccaps; + struct chipc_softc *chipc_sc; + device_t chipc; + char desc[34]; + int error; + uint32_t pcaps; + uint8_t rev; + + sc = device_get_softc(dev); + + /* Look for chipc parent */ + chipc = device_get_parent(dev); + if (device_get_devclass(chipc) != devclass_find("bhnd_chipc")) + return (ENXIO); + + /* Check the chipc PMU capability flag. */ + ccaps = BHND_CHIPC_GET_CAPS(chipc); + if (!ccaps->pmu) + return (ENXIO); + + /* Delegate to common driver implementation */ + if ((error = bhnd_pmu_probe(dev)) > 0) + return (error); + + /* Fetch PMU capability flags */ + chipc_sc = device_get_softc(chipc); + pcaps = bhnd_bus_read_4(chipc_sc->core, BHND_PMU_CAP); + + /* Set description */ + rev = BHND_PMU_GET_BITS(pcaps, BHND_PMU_CAP_REV); + snprintf(desc, sizeof(desc), "Broadcom ChipCommon PMU, rev %hhu", rev); + device_set_desc_copy(dev, desc); + + return (BUS_PROBE_NOWILDCARD); +} + +static int +bhnd_pmu_chipc_attach(device_t dev) +{ + struct chipc_softc *chipc_sc; + struct bhnd_resource *r; + + /* Fetch core registers from ChipCommon parent */ + chipc_sc = device_get_softc(device_get_parent(dev)); + r = chipc_sc->core; + + return (bhnd_pmu_attach(dev, r)); +} + +static device_method_t bhnd_pmu_chipc_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, bhnd_pmu_chipc_probe), + DEVMETHOD(device_attach, bhnd_pmu_chipc_attach), + + DEVMETHOD_END +}; + +DEFINE_CLASS_1(bhnd_pmu, bhnd_pmu_chipc_driver, bhnd_pmu_chipc_methods, + sizeof(struct bhnd_pmu_softc), bhnd_pmu_driver); +EARLY_DRIVER_MODULE(bhnd_pmu_chipc, bhnd_chipc, bhnd_pmu_chipc_driver, + bhnd_pmu_devclass, NULL, NULL, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); + +MODULE_DEPEND(bhnd_pmu_chipc, bhnd, 1, 1, 1); +MODULE_VERSION(bhnd_pmu_chipc, 1); Property changes on: head/sys/dev/bhnd/cores/chipc/bhnd_pmu_chipc.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/bhnd/cores/chipc/bhnd_sprom_chipc.c =================================================================== --- head/sys/dev/bhnd/cores/chipc/bhnd_sprom_chipc.c (revision 304869) +++ head/sys/dev/bhnd/cores/chipc/bhnd_sprom_chipc.c (revision 304870) @@ -1,111 +1,110 @@ /*- * Copyright (c) 2015-2016 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); /* * ChipCommon SPROM driver. */ #include #include #include #include #include #include #include #include #include #include -#include "bhnd_nvram_if.h" +#include -#include "chipcvar.h" -#include "chipc_private.h" +#include "bhnd_nvram_if.h" #define CHIPC_VALID_SPROM_SRC(_src) \ ((_src) == BHND_NVRAM_SRC_SPROM || (_src) == BHND_NVRAM_SRC_OTP) static int chipc_sprom_probe(device_t dev) { struct chipc_caps *caps; device_t chipc; int error; chipc = device_get_parent(dev); caps = BHND_CHIPC_GET_CAPS(chipc); /* Only match on SPROM/OTP devices */ if (!CHIPC_VALID_SPROM_SRC(caps->nvram_src)) return (ENXIO); /* Defer to default driver implementation */ if ((error = bhnd_sprom_probe(dev)) > 0) return (error); return (BUS_PROBE_NOWILDCARD); } static int chipc_sprom_attach(device_t dev) { struct chipc_caps *caps; device_t chipc; int error; chipc = device_get_parent(dev); caps = BHND_CHIPC_GET_CAPS(chipc); /* Request that ChipCommon enable access to SPROM hardware before * delegating attachment (and SPROM parsing) to the common driver */ if ((error = BHND_CHIPC_ENABLE_SPROM(chipc))) return (error); error = bhnd_sprom_attach(dev, caps->sprom_offset); BHND_CHIPC_DISABLE_SPROM(chipc); return (error); } static device_method_t chipc_sprom_methods[] = { /* Device interface */ DEVMETHOD(device_probe, chipc_sprom_probe), DEVMETHOD(device_attach, chipc_sprom_attach), DEVMETHOD_END }; DEFINE_CLASS_1(bhnd_nvram, chipc_sprom_driver, chipc_sprom_methods, sizeof(struct bhnd_sprom_softc), bhnd_sprom_driver); DRIVER_MODULE(bhnd_chipc_sprom, bhnd_chipc, chipc_sprom_driver, bhnd_nvram_devclass, NULL, NULL); MODULE_DEPEND(bhnd_chipc_sprom, bhnd, 1, 1, 1); MODULE_DEPEND(bhnd_chipc_sprom, bhnd_chipc, 1, 1, 1); MODULE_DEPEND(bhnd_chipc_sprom, bhnd_sprom, 1, 1, 1); MODULE_VERSION(bhnd_chipc_sprom, 1); Index: head/sys/dev/bhnd/cores/chipc/chipc.c =================================================================== --- head/sys/dev/bhnd/cores/chipc/chipc.c (revision 304869) +++ head/sys/dev/bhnd/cores/chipc/chipc.c (revision 304870) @@ -1,1332 +1,1372 @@ /*- * Copyright (c) 2015-2016 Landon Fuller * Copyright (c) 2016 Michael Zhilin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); /* * Broadcom ChipCommon driver. * * With the exception of some very early chipsets, the ChipCommon core * has been included in all HND SoCs and chipsets based on the siba(4) * and bcma(4) interconnects, providing a common interface to chipset * identification, bus enumeration, UARTs, clocks, watchdog interrupts, * GPIO, flash, etc. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include "chipcreg.h" #include "chipcvar.h" #include "chipc_private.h" devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */ static struct bhnd_device_quirk chipc_quirks[]; /* Supported device identifiers */ static const struct bhnd_device chipc_devices[] = { BHND_DEVICE(BCM, CC, NULL, chipc_quirks), BHND_DEVICE_END }; /* Device quirks table */ static struct bhnd_device_quirk chipc_quirks[] = { /* HND OTP controller revisions */ BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */ BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */ BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */ /* IPX OTP controller revisions */ BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX), BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX), BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM), BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT), BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE), /* 4706 variant quirks */ BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */ BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH), /* 4331 quirks*/ BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM), BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM), /* 4360 quirks */ BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), BHND_DEVICE_QUIRK_END }; // FIXME: IRQ shouldn't be hard-coded #define CHIPC_MIPS_IRQ 2 -static int chipc_add_children(struct chipc_softc *sc); +static int chipc_add_children(struct chipc_softc *sc); -static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc, - struct chipc_caps *caps); -static int chipc_read_caps(struct chipc_softc *sc, - struct chipc_caps *caps); +static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc, + struct chipc_caps *caps); +static int chipc_read_caps(struct chipc_softc *sc, + struct chipc_caps *caps); -static bool chipc_should_enable_sprom( - struct chipc_softc *sc); +static bool chipc_should_enable_muxed_sprom( + struct chipc_softc *sc); +static int chipc_enable_otp_power(struct chipc_softc *sc); +static void chipc_disable_otp_power(struct chipc_softc *sc); +static int chipc_enable_sprom_pins(struct chipc_softc *sc); +static void chipc_disable_sprom_pins(struct chipc_softc *sc); -static int chipc_try_activate_resource( - struct chipc_softc *sc, device_t child, - int type, int rid, struct resource *r, - bool req_direct); +static int chipc_try_activate_resource(struct chipc_softc *sc, + device_t child, int type, int rid, + struct resource *r, bool req_direct); -static int chipc_init_rman(struct chipc_softc *sc); -static void chipc_free_rman(struct chipc_softc *sc); -static struct rman *chipc_get_rman(struct chipc_softc *sc, - int type); +static int chipc_init_rman(struct chipc_softc *sc); +static void chipc_free_rman(struct chipc_softc *sc); +static struct rman *chipc_get_rman(struct chipc_softc *sc, int type); /* quirk and capability flag convenience macros */ #define CHIPC_QUIRK(_sc, _name) \ ((_sc)->quirks & CHIPC_QUIRK_ ## _name) #define CHIPC_CAP(_sc, _name) \ ((_sc)->caps._name) #define CHIPC_ASSERT_QUIRK(_sc, name) \ KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) #define CHIPC_ASSERT_CAP(_sc, name) \ KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set")) static int chipc_probe(device_t dev) { const struct bhnd_device *id; id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0])); if (id == NULL) return (ENXIO); bhnd_set_default_core_desc(dev); return (BUS_PROBE_DEFAULT); } static int chipc_attach(device_t dev) { struct chipc_softc *sc; int error; sc = device_get_softc(dev); sc->dev = dev; sc->quirks = bhnd_device_quirks(dev, chipc_devices, sizeof(chipc_devices[0])); sc->sprom_refcnt = 0; CHIPC_LOCK_INIT(sc); STAILQ_INIT(&sc->mem_regions); /* Set up resource management */ if ((error = chipc_init_rman(sc))) { device_printf(sc->dev, "failed to initialize chipc resource state: %d\n", error); goto failed; } /* Allocate the region containing the chipc register block */ if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) { error = ENXIO; goto failed; } error = chipc_retain_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); if (error) { sc->core_region = NULL; goto failed; } /* Save a direct reference to our chipc registers */ sc->core = sc->core_region->cr_res; /* Fetch and parse capability register(s) */ if ((error = chipc_read_caps(sc, &sc->caps))) goto failed; if (bootverbose) chipc_print_caps(sc->dev, &sc->caps); /* Attach all supported child devices */ if ((error = chipc_add_children(sc))) goto failed; if ((error = bus_generic_attach(dev))) goto failed; return (0); failed: device_delete_children(sc->dev); if (sc->core_region != NULL) { chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); } chipc_free_rman(sc); CHIPC_LOCK_DESTROY(sc); return (error); } static int chipc_detach(device_t dev) { struct chipc_softc *sc; int error; sc = device_get_softc(dev); if ((error = bus_generic_detach(dev))) return (error); chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); chipc_free_rman(sc); CHIPC_LOCK_DESTROY(sc); return (0); } static int chipc_add_children(struct chipc_softc *sc) { device_t child; const char *flash_bus; int error; /* SPROM/OTP */ if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM || sc->caps.nvram_src == BHND_NVRAM_SRC_OTP) { child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", -1); if (child == NULL) { device_printf(sc->dev, "failed to add nvram device\n"); return (ENXIO); } /* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */ error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, CHIPC_SPROM_OTP, CHIPC_SPROM_OTP_SIZE, 0, 0); if (error) return (error); } -#ifdef notyet /* - * PMU/SLOWCLK/INSTACLK + * PMU/PWR_CTRL * - * On AOB ("Always on Bus") devices, a PMU core (if it exists) is - * enumerated directly by the bhnd(4) bus -- not chipc. - * - * Otherwise, we always add a PMU child device, and let the - * chipc bhnd_pmu drivers probe for it. If the core supports an - * earlier non-PMU clock/power register interface, one of the instaclk, - * powerctl, or null bhnd_pmu drivers will claim the device. + * On AOB ("Always on Bus") devices, the PMU core (if it exists) is + * attached directly to the bhnd(4) bus -- not chipc. */ - if (!sc->caps.aob || (sc->caps.aob && !sc->caps.pmu)) { + if (sc->caps.pwr_ctrl || (sc->caps.pmu && !sc->caps.aob)) { child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", -1); if (child == NULL) { device_printf(sc->dev, "failed to add pmu\n"); return (ENXIO); } - - /* Associate the applicable register block */ - error = 0; - if (sc->caps.pmu) { - error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, - CHIPC_PMU, CHIPC_PMU_SIZE, 0, 0); - } else if (sc->caps.power_control) { - error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, - CHIPC_PWRCTL, CHIPC_PWRCTL_SIZE, 0, 0); - } - - if (error) - return (error); - } -#endif /* notyet */ /* All remaining devices are SoC-only */ if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE) return (0); /* UARTs */ for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) { child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1); if (child == NULL) { device_printf(sc->dev, "failed to add uart%u\n", i); return (ENXIO); } /* Shared IRQ */ error = bus_set_resource(child, SYS_RES_IRQ, 0, CHIPC_MIPS_IRQ, 1); if (error) { device_printf(sc->dev, "failed to set uart%u irq %u\n", i, CHIPC_MIPS_IRQ); return (error); } /* UART registers are mapped sequentially */ error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0); if (error) return (error); } /* Flash */ flash_bus = chipc_flash_bus_name(sc->caps.flash_type); if (flash_bus != NULL) { child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, -1); if (child == NULL) { device_printf(sc->dev, "failed to add %s device\n", flash_bus); return (ENXIO); } /* flash memory mapping */ error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, 0, RM_MAX_END, 1, 1); if (error) return (error); /* flashctrl registers */ error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 1, CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0); if (error) return (error); } return (0); } /** * Determine the NVRAM data source for this device. * * The SPROM, OTP, and flash capability flags must be fully populated in * @p caps. * * @param sc chipc driver state. * @param caps capability flags to be used to derive NVRAM configuration. */ static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps) { uint32_t otp_st, srom_ctrl; /* * We check for hardware presence in order of precedence. For example, * SPROM is is always used in preference to internal OTP if found. */ if (CHIPC_QUIRK(sc, SUPPORTS_SPROM) && caps->sprom) { srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL); if (srom_ctrl & CHIPC_SRC_PRESENT) return (BHND_NVRAM_SRC_SPROM); } /* Check for programmed OTP H/W subregion (contains SROM data) */ if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) { /* TODO: need access to HND-OTP device */ if (!CHIPC_QUIRK(sc, OTP_HND)) { device_printf(sc->dev, "NVRAM unavailable: unsupported OTP controller.\n"); return (BHND_NVRAM_SRC_UNKNOWN); } otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST); if (otp_st & CHIPC_OTPS_GUP_HW) return (BHND_NVRAM_SRC_OTP); } /* Check for flash */ if (caps->flash_type != CHIPC_FLASH_NONE) return (BHND_NVRAM_SRC_FLASH); /* No NVRAM hardware capability declared */ return (BHND_NVRAM_SRC_UNKNOWN); } /* Read and parse chipc capabilities */ static int chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps) { uint32_t cap_reg; uint32_t cap_ext_reg; uint32_t regval; /* Fetch cap registers */ cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES); cap_ext_reg = 0; if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT)) cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT); /* Extract values */ caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART); caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB); caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO); caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL); caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS); - caps->power_control = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL); + caps->pwr_ctrl = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL); caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP); caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL); caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64); caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM); caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU); caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI); caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM); caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE); caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI); caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO); caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB); /* Fetch OTP size for later IPX controller revisions */ if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) { regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE); } /* Determine flash type and parameters */ caps->cfi_width = 0; switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) { case CHIPC_CAP_SFLASH_ST: caps->flash_type = CHIPC_SFLASH_ST; break; case CHIPC_CAP_SFLASH_AT: caps->flash_type = CHIPC_SFLASH_AT; break; case CHIPC_CAP_NFLASH: /* unimplemented */ caps->flash_type = CHIPC_NFLASH; break; case CHIPC_CAP_PFLASH: caps->flash_type = CHIPC_PFLASH_CFI; /* determine cfi width */ regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG); if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS)) caps->cfi_width = 2; else caps->cfi_width = 1; break; case CHIPC_CAP_FLASH_NONE: caps->flash_type = CHIPC_FLASH_NONE; break; } /* Handle 4706_NFLASH fallback */ if (CHIPC_QUIRK(sc, 4706_NFLASH) && CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH)) { caps->flash_type = CHIPC_NFLASH_4706; } /* Determine NVRAM source. Must occur after the SPROM/OTP/flash * capability flags have been populated. */ caps->nvram_src = chipc_find_nvram_src(sc, caps); /* Determine the SPROM offset within OTP (if any). SPROM-formatted * data is placed within the OTP general use region. */ caps->sprom_offset = 0; if (caps->nvram_src == BHND_NVRAM_SRC_OTP) { CHIPC_ASSERT_QUIRK(sc, OTP_IPX); /* Bit offset to GUP HW subregion containing SPROM data */ regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP); /* Convert to bytes */ caps->sprom_offset /= 8; } return (0); } static int chipc_suspend(device_t dev) { return (bus_generic_suspend(dev)); } static int chipc_resume(device_t dev) { return (bus_generic_resume(dev)); } static void chipc_probe_nomatch(device_t dev, device_t child) { struct resource_list *rl; const char *name; name = device_get_name(child); if (name == NULL) name = "unknown device"; device_printf(dev, "<%s> at", name); rl = BUS_GET_RESOURCE_LIST(dev, child); if (rl != NULL) { resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); } printf(" (no driver attached)\n"); } static int chipc_print_child(device_t dev, device_t child) { struct resource_list *rl; int retval = 0; retval += bus_print_child_header(dev, child); rl = BUS_GET_RESOURCE_LIST(dev, child); if (rl != NULL) { retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); } retval += bus_print_child_domain(dev, child); retval += bus_print_child_footer(dev, child); return (retval); } static int chipc_child_pnpinfo_str(device_t dev, device_t child, char *buf, size_t buflen) { if (buflen == 0) return (EOVERFLOW); *buf = '\0'; return (0); } static int chipc_child_location_str(device_t dev, device_t child, char *buf, size_t buflen) { if (buflen == 0) return (EOVERFLOW); *buf = '\0'; return (ENXIO); } static device_t chipc_add_child(device_t dev, u_int order, const char *name, int unit) { struct chipc_softc *sc; struct chipc_devinfo *dinfo; device_t child; sc = device_get_softc(dev); child = device_add_child_ordered(dev, order, name, unit); if (child == NULL) return (NULL); dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT); if (dinfo == NULL) { device_delete_child(dev, child); return (NULL); } resource_list_init(&dinfo->resources); device_set_ivars(child, dinfo); return (child); } static void chipc_child_deleted(device_t dev, device_t child) { struct chipc_devinfo *dinfo = device_get_ivars(child); if (dinfo != NULL) { resource_list_free(&dinfo->resources); free(dinfo, M_BHND); } device_set_ivars(child, NULL); } static struct resource_list * chipc_get_resource_list(device_t dev, device_t child) { struct chipc_devinfo *dinfo = device_get_ivars(child); return (&dinfo->resources); } /* Allocate region records for the given port, and add the port's memory * range to the mem_rman */ static int chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type, u_int port) { struct chipc_region *cr; rman_res_t start, end; u_int num_regions; int error; num_regions = bhnd_get_region_count(sc->dev, type, port); for (u_int region = 0; region < num_regions; region++) { /* Allocate new region record */ cr = chipc_alloc_region(sc, type, port, region); if (cr == NULL) return (ENODEV); /* Can't manage regions that cannot be allocated */ if (cr->cr_rid < 0) { BHND_DEBUG_DEV(sc->dev, "no rid for chipc region " "%s%u.%u", bhnd_port_type_name(type), port, region); chipc_free_region(sc, cr); continue; } /* Add to rman's managed range */ start = cr->cr_addr; end = cr->cr_end; if ((error = rman_manage_region(&sc->mem_rman, start, end))) { chipc_free_region(sc, cr); return (error); } /* Add to region list */ STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link); } return (0); } /* Initialize memory state for all chipc port regions */ static int chipc_init_rman(struct chipc_softc *sc) { u_int num_ports; int error; /* Port types for which we'll register chipc_region mappings */ bhnd_port_type types[] = { BHND_PORT_DEVICE }; /* Initialize resource manager */ sc->mem_rman.rm_start = 0; sc->mem_rman.rm_end = BUS_SPACE_MAXADDR; sc->mem_rman.rm_type = RMAN_ARRAY; sc->mem_rman.rm_descr = "ChipCommon Device Memory"; if ((error = rman_init(&sc->mem_rman))) { device_printf(sc->dev, "could not initialize mem_rman: %d\n", error); return (error); } /* Populate per-port-region state */ for (u_int i = 0; i < nitems(types); i++) { num_ports = bhnd_get_port_count(sc->dev, types[i]); for (u_int port = 0; port < num_ports; port++) { error = chipc_rman_init_regions(sc, types[i], port); if (error) { device_printf(sc->dev, "region init failed for %s%u: %d\n", bhnd_port_type_name(types[i]), port, error); goto failed; } } } return (0); failed: chipc_free_rman(sc); return (error); } /* Free memory management state */ static void chipc_free_rman(struct chipc_softc *sc) { struct chipc_region *cr, *cr_next; STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next) chipc_free_region(sc, cr); rman_fini(&sc->mem_rman); } /** * Return the rman instance for a given resource @p type, if any. * * @param sc The chipc device state. * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...) */ static struct rman * chipc_get_rman(struct chipc_softc *sc, int type) { switch (type) { case SYS_RES_MEMORY: return (&sc->mem_rman); case SYS_RES_IRQ: /* IRQs can be used with RF_SHAREABLE, so we don't perform * any local proxying of resource requests. */ return (NULL); default: return (NULL); }; } static struct resource * chipc_alloc_resource(device_t dev, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) { struct chipc_softc *sc; struct chipc_region *cr; struct resource_list_entry *rle; struct resource *rv; struct rman *rm; int error; bool passthrough, isdefault; sc = device_get_softc(dev); passthrough = (device_get_parent(child) != dev); isdefault = RMAN_IS_DEFAULT_RANGE(start, end); rle = NULL; /* Fetch the resource manager, delegate request if necessary */ rm = chipc_get_rman(sc, type); if (rm == NULL) { /* Requested resource type is delegated to our parent */ rv = bus_generic_rl_alloc_resource(dev, child, type, rid, start, end, count, flags); return (rv); } /* Populate defaults */ if (!passthrough && isdefault) { /* Fetch the resource list entry. */ rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, *rid); if (rle == NULL) { device_printf(dev, "default resource %#x type %d for child %s " "not found\n", *rid, type, device_get_nameunit(child)); return (NULL); } if (rle->res != NULL) { device_printf(dev, "resource entry %#x type %d for child %s is busy " "[%d]\n", *rid, type, device_get_nameunit(child), rman_get_flags(rle->res)); return (NULL); } start = rle->start; end = rle->end; count = ulmax(count, rle->count); } /* Locate a mapping region */ if ((cr = chipc_find_region(sc, start, end)) == NULL) { /* Resource requests outside our shared port regions can be * delegated to our parent. */ rv = bus_generic_rl_alloc_resource(dev, child, type, rid, start, end, count, flags); return (rv); } /* Try to retain a region reference */ if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED))) return (NULL); /* Make our rman reservation */ rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, child); if (rv == NULL) { chipc_release_region(sc, cr, RF_ALLOCATED); return (NULL); } rman_set_rid(rv, *rid); /* Activate */ if (flags & RF_ACTIVE) { error = bus_activate_resource(child, type, *rid, rv); if (error) { device_printf(dev, "failed to activate entry %#x type %d for " "child %s: %d\n", *rid, type, device_get_nameunit(child), error); chipc_release_region(sc, cr, RF_ALLOCATED); rman_release_resource(rv); return (NULL); } } /* Update child's resource list entry */ if (rle != NULL) { rle->res = rv; rle->start = rman_get_start(rv); rle->end = rman_get_end(rv); rle->count = rman_get_size(rv); } return (rv); } static int chipc_release_resource(device_t dev, device_t child, int type, int rid, struct resource *r) { struct chipc_softc *sc; struct chipc_region *cr; struct rman *rm; struct resource_list_entry *rle; int error; sc = device_get_softc(dev); /* Handled by parent bus? */ rm = chipc_get_rman(sc, type); if (rm == NULL || !rman_is_region_manager(r, rm)) { return (bus_generic_rl_release_resource(dev, child, type, rid, r)); } /* Locate the mapping region */ cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); if (cr == NULL) return (EINVAL); /* Deactivate resources */ if (rman_get_flags(r) & RF_ACTIVE) { error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r); if (error) return (error); } if ((error = rman_release_resource(r))) return (error); /* Drop allocation reference */ chipc_release_region(sc, cr, RF_ALLOCATED); /* Clear reference from the resource list entry if exists */ rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid); if (rle != NULL) rle->res = NULL; return (0); } static int chipc_adjust_resource(device_t dev, device_t child, int type, struct resource *r, rman_res_t start, rman_res_t end) { struct chipc_softc *sc; struct chipc_region *cr; struct rman *rm; sc = device_get_softc(dev); /* Handled by parent bus? */ rm = chipc_get_rman(sc, type); if (rm == NULL || !rman_is_region_manager(r, rm)) { return (bus_generic_adjust_resource(dev, child, type, r, start, end)); } /* The range is limited to the existing region mapping */ cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); if (cr == NULL) return (EINVAL); if (end <= start) return (EINVAL); if (start < cr->cr_addr || end > cr->cr_end) return (EINVAL); /* Range falls within the existing region */ return (rman_adjust_resource(r, start, end)); } /** * Retain an RF_ACTIVE reference to the region mapping @p r, and * configure @p r with its subregion values. * * @param sc Driver instance state. * @param child Requesting child device. * @param type resource type of @p r. * @param rid resource id of @p r * @param r resource to be activated. * @param req_direct If true, failure to allocate a direct bhnd resource * will be treated as an error. If false, the resource will not be marked * as RF_ACTIVE if bhnd direct resource allocation fails. */ static int chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type, int rid, struct resource *r, bool req_direct) { struct rman *rm; struct chipc_region *cr; bhnd_size_t cr_offset; rman_res_t r_start, r_end, r_size; int error; rm = chipc_get_rman(sc, type); if (rm == NULL || !rman_is_region_manager(r, rm)) return (EINVAL); r_start = rman_get_start(r); r_end = rman_get_end(r); r_size = rman_get_size(r); /* Find the corresponding chipc region */ cr = chipc_find_region(sc, r_start, r_end); if (cr == NULL) return (EINVAL); /* Calculate subregion offset within the chipc region */ cr_offset = r_start - cr->cr_addr; /* Retain (and activate, if necessary) the chipc region */ if ((error = chipc_retain_region(sc, cr, RF_ACTIVE))) return (error); /* Configure child resource with its subregion values. */ if (cr->cr_res->direct) { error = chipc_init_child_resource(r, cr->cr_res->res, cr_offset, r_size); if (error) goto cleanup; /* Mark active */ if ((error = rman_activate_resource(r))) goto cleanup; } else if (req_direct) { error = ENOMEM; goto cleanup; } return (0); cleanup: chipc_release_region(sc, cr, RF_ACTIVE); return (error); } static int chipc_activate_bhnd_resource(device_t dev, device_t child, int type, int rid, struct bhnd_resource *r) { struct chipc_softc *sc; struct rman *rm; int error; sc = device_get_softc(dev); /* Delegate non-locally managed resources to parent */ rm = chipc_get_rman(sc, type); if (rm == NULL || !rman_is_region_manager(r->res, rm)) { return (bhnd_bus_generic_activate_resource(dev, child, type, rid, r)); } /* Try activating the chipc region resource */ error = chipc_try_activate_resource(sc, child, type, rid, r->res, false); if (error) return (error); /* Mark the child resource as direct according to the returned resource * state */ if (rman_get_flags(r->res) & RF_ACTIVE) r->direct = true; return (0); } static int chipc_activate_resource(device_t dev, device_t child, int type, int rid, struct resource *r) { struct chipc_softc *sc; struct rman *rm; sc = device_get_softc(dev); /* Delegate non-locally managed resources to parent */ rm = chipc_get_rman(sc, type); if (rm == NULL || !rman_is_region_manager(r, rm)) { return (bus_generic_activate_resource(dev, child, type, rid, r)); } /* Try activating the chipc region-based resource */ return (chipc_try_activate_resource(sc, child, type, rid, r, true)); } /** * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE(). */ static int chipc_deactivate_resource(device_t dev, device_t child, int type, int rid, struct resource *r) { struct chipc_softc *sc; struct chipc_region *cr; struct rman *rm; int error; sc = device_get_softc(dev); /* Handled by parent bus? */ rm = chipc_get_rman(sc, type); if (rm == NULL || !rman_is_region_manager(r, rm)) { return (bus_generic_deactivate_resource(dev, child, type, rid, r)); } /* Find the corresponding chipc region */ cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); if (cr == NULL) return (EINVAL); /* Mark inactive */ if ((error = rman_deactivate_resource(r))) return (error); /* Drop associated RF_ACTIVE reference */ chipc_release_region(sc, cr, RF_ACTIVE); return (0); } /** * Examine bus state and make a best effort determination of whether it's * likely safe to enable the muxed SPROM pins. * * On devices that do not use SPROM pin muxing, always returns true. * * @param sc chipc driver state. */ static bool -chipc_should_enable_sprom(struct chipc_softc *sc) +chipc_should_enable_muxed_sprom(struct chipc_softc *sc) { device_t *devs; device_t hostb; device_t parent; int devcount; int error; bool result; - mtx_assert(&Giant, MA_OWNED); /* for newbus */ - /* Nothing to do? */ if (!CHIPC_QUIRK(sc, MUX_SPROM)) return (true); + mtx_lock(&Giant); /* for newbus */ + parent = device_get_parent(sc->dev); hostb = bhnd_find_hostb_device(parent); - if ((error = device_get_children(parent, &devs, &devcount))) + if ((error = device_get_children(parent, &devs, &devcount))) { + mtx_unlock(&Giant); return (false); + } /* Reject any active devices other than ChipCommon, or the * host bridge (if any). */ result = true; for (int i = 0; i < devcount; i++) { if (devs[i] == hostb || devs[i] == sc->dev) continue; if (!device_is_attached(devs[i])) continue; if (device_is_suspended(devs[i])) continue; /* Active device; assume SPROM is busy */ result = false; break; } free(devs, M_TEMP); + mtx_unlock(&Giant); return (result); } +static int +chipc_enable_sprom(device_t dev) +{ + struct chipc_softc *sc; + int error; + + sc = device_get_softc(dev); + CHIPC_LOCK(sc); + + /* Already enabled? */ + if (sc->sprom_refcnt >= 1) { + sc->sprom_refcnt++; + CHIPC_UNLOCK(sc); + + return (0); + } + + switch (sc->caps.nvram_src) { + case BHND_NVRAM_SRC_SPROM: + error = chipc_enable_sprom_pins(sc); + break; + case BHND_NVRAM_SRC_OTP: + error = chipc_enable_otp_power(sc); + break; + default: + error = 0; + break; + } + + /* Bump the reference count */ + if (error == 0) + sc->sprom_refcnt++; + + CHIPC_UNLOCK(sc); + return (error); +} + +static void +chipc_disable_sprom(device_t dev) +{ + struct chipc_softc *sc; + + sc = device_get_softc(dev); + CHIPC_LOCK(sc); + + /* Check reference count, skip disable if in-use. */ + KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease")); + sc->sprom_refcnt--; + if (sc->sprom_refcnt > 0) { + CHIPC_UNLOCK(sc); + return; + } + + switch (sc->caps.nvram_src) { + case BHND_NVRAM_SRC_SPROM: + chipc_disable_sprom_pins(sc); + break; + case BHND_NVRAM_SRC_OTP: + chipc_disable_otp_power(sc); + break; + default: + break; + } + + + CHIPC_UNLOCK(sc); +} + +static int +chipc_enable_otp_power(struct chipc_softc *sc) +{ + // TODO: Enable OTP resource via PMU, and wait up to 100 usec for + // OTPS_READY to be set in `optstatus`. + return (0); +} + +static void +chipc_disable_otp_power(struct chipc_softc *sc) +{ + // TODO: Disable OTP resource via PMU +} + /** * If required by this device, enable access to the SPROM. * * @param sc chipc driver state. */ static int -chipc_enable_sprom_pins(device_t dev) +chipc_enable_sprom_pins(struct chipc_softc *sc) { - struct chipc_softc *sc; uint32_t cctrl; - int error; - sc = device_get_softc(dev); + CHIPC_LOCK_ASSERT(sc, MA_OWNED); + KASSERT(sc->sprom_refcnt == 0, ("sprom pins already enabled")); /* Nothing to do? */ if (!CHIPC_QUIRK(sc, MUX_SPROM)) return (0); - /* Make sure we're holding Giant for newbus */ - mtx_lock(&Giant); - CHIPC_LOCK(sc); - - /* Already enabled? */ - if (sc->sprom_refcnt >= 1) { - error = 0; - goto finished; - } - /* Check whether bus is busy */ - if (!chipc_should_enable_sprom(sc)) { - error = EBUSY; - goto finished; - } + if (!chipc_should_enable_muxed_sprom(sc)) + return (EBUSY); cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); /* 4331 devices */ if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN; if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2; bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); - error = 0; - goto finished; + return (0); } /* 4360 devices */ if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { /* Unimplemented */ } /* Refuse to proceed on unsupported devices with muxed SPROM pins */ device_printf(sc->dev, "muxed sprom lines on unrecognized device\n"); - error = ENXIO; - -finished: - /* Bump the reference count */ - if (error == 0) - sc->sprom_refcnt++; - - CHIPC_UNLOCK(sc); - mtx_unlock(&Giant); - - return (error); + return (ENXIO); } /** * If required by this device, revert any GPIO/pin configuration applied * to allow SPROM access. * * @param sc chipc driver state. */ static void -chipc_disable_sprom_pins(device_t dev) +chipc_disable_sprom_pins(struct chipc_softc *sc) { - struct chipc_softc *sc; uint32_t cctrl; - sc = device_get_softc(dev); - /* Nothing to do? */ if (!CHIPC_QUIRK(sc, MUX_SPROM)) return; - CHIPC_LOCK(sc); + CHIPC_LOCK_ASSERT(sc, MA_OWNED); + KASSERT(sc->sprom_refcnt != 0, ("sprom pins already disabled")); + KASSERT(sc->sprom_refcnt == 1, ("sprom pins in use")); - /* Check reference count, skip disable if in-use. */ - KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease")); - sc->sprom_refcnt--; - if (sc->sprom_refcnt > 0) - goto finished; - cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); /* 4331 devices */ if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { cctrl |= CHIPC_CCTRL4331_EXTPA_EN; if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) cctrl |= CHIPC_CCTRL4331_EXTPA_EN2; bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); - goto finished; + return; } /* 4360 devices */ if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { /* Unimplemented */ } +} -finished: - CHIPC_UNLOCK(sc); +static uint32_t +chipc_read_chipst(device_t dev) +{ + struct chipc_softc *sc = device_get_softc(dev); + return (bhnd_bus_read_4(sc->core, CHIPC_CHIPST)); } static void chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask) { struct chipc_softc *sc; uint32_t cctrl; sc = device_get_softc(dev); CHIPC_LOCK(sc); cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); cctrl = (cctrl & ~mask) | (value | mask); bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); CHIPC_UNLOCK(sc); } static struct chipc_caps * chipc_get_caps(device_t dev) { struct chipc_softc *sc; sc = device_get_softc(dev); return (&sc->caps); } static device_method_t chipc_methods[] = { /* Device interface */ DEVMETHOD(device_probe, chipc_probe), DEVMETHOD(device_attach, chipc_attach), DEVMETHOD(device_detach, chipc_detach), DEVMETHOD(device_suspend, chipc_suspend), DEVMETHOD(device_resume, chipc_resume), /* Bus interface */ DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch), DEVMETHOD(bus_print_child, chipc_print_child), DEVMETHOD(bus_child_pnpinfo_str, chipc_child_pnpinfo_str), DEVMETHOD(bus_child_location_str, chipc_child_location_str), DEVMETHOD(bus_add_child, chipc_add_child), DEVMETHOD(bus_child_deleted, chipc_child_deleted), DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), DEVMETHOD(bus_alloc_resource, chipc_alloc_resource), DEVMETHOD(bus_release_resource, chipc_release_resource), DEVMETHOD(bus_adjust_resource, chipc_adjust_resource), DEVMETHOD(bus_activate_resource, chipc_activate_resource), DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource), DEVMETHOD(bus_get_resource_list, chipc_get_resource_list), DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), DEVMETHOD(bus_config_intr, bus_generic_config_intr), DEVMETHOD(bus_bind_intr, bus_generic_bind_intr), DEVMETHOD(bus_describe_intr, bus_generic_describe_intr), /* BHND bus inteface */ DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource), /* ChipCommon interface */ + DEVMETHOD(bhnd_chipc_read_chipst, chipc_read_chipst), DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl), - DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom_pins), - DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom_pins), + DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom), + DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom), DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps), DEVMETHOD_END }; -DEFINE_CLASS_0(bhnd_chipc, chipc_driver, chipc_methods, sizeof(struct chipc_softc)); -EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, chipc_driver, bhnd_chipc_devclass, 0, 0, +DEFINE_CLASS_0(bhnd_chipc, bhnd_chipc_driver, chipc_methods, sizeof(struct chipc_softc)); +EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, bhnd_chipc_driver, bhnd_chipc_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1); MODULE_VERSION(bhnd_chipc, 1); Index: head/sys/dev/bhnd/cores/chipc/chipc.h =================================================================== --- head/sys/dev/bhnd/cores/chipc/chipc.h (revision 304869) +++ head/sys/dev/bhnd/cores/chipc/chipc.h (revision 304870) @@ -1,40 +1,96 @@ /*- * Copyright (c) 2015-2016 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. * * $FreeBSD$ */ #ifndef _BHND_CORES_CHIPC_CHIPC_H_ #define _BHND_CORES_CHIPC_CHIPC_H_ #include #include #include "bhnd_chipc_if.h" +/** + * Supported ChipCommon flash types. + */ +typedef enum { + CHIPC_FLASH_NONE = 0, /**< No flash, or a type unrecognized + by the ChipCommon driver */ + CHIPC_PFLASH_CFI = 1, /**< CFI-compatible parallel flash */ + CHIPC_SFLASH_ST = 2, /**< ST serial flash */ + CHIPC_SFLASH_AT = 3, /**< Atmel serial flash */ + CHIPC_QSFLASH_ST = 4, /**< ST quad-SPI flash */ + CHIPC_QSFLASH_AT = 5, /**< Atmel quad-SPI flash */ + CHIPC_NFLASH = 6, /**< NAND flash */ + CHIPC_NFLASH_4706 = 7 /**< BCM4706 NAND flash */ +} chipc_flash; + +/** + * ChipCommon capability flags; + */ +struct chipc_caps { + uint8_t num_uarts; /**< Number of attached UARTS (1-3) */ + bool mipseb; /**< MIPS is big-endian */ + uint8_t uart_clock; /**< UART clock source (see CHIPC_CAP_UCLKSEL_*) */ + uint8_t uart_gpio; /**< UARTs own GPIO pins 12-15 */ + + uint8_t extbus_type; /**< ExtBus type (CHIPC_CAP_EXTBUS_*) */ + + chipc_flash flash_type; /**< flash type */ + uint8_t cfi_width; /**< CFI bus width, 0 if unknown or CFI + not present */ + + bhnd_nvram_src nvram_src; /**< identified NVRAM source */ + bus_size_t sprom_offset; /**< Offset to SPROM data within + SPROM/OTP, 0 if unknown or not + present */ + uint8_t otp_size; /**< OTP (row?) size, 0 if not present */ + + uint8_t pll_type; /**< PLL type */ + bool pwr_ctrl; /**< Power/clock control available */ + bool jtag_master; /**< JTAG Master present */ + bool boot_rom; /**< Internal boot ROM is active */ + uint8_t backplane_64; /**< Backplane supports 64-bit addressing. + Note that this does not gaurantee + the CPU itself supports 64-bit + addressing. */ + bool pmu; /**< PMU is present. */ + bool eci; /**< ECI (enhanced coexistence inteface) is present. */ + bool seci; /**< SECI (serial ECI) is present */ + bool sprom; /**< SPROM is present */ + bool gsio; /**< GSIO (SPI/I2C) present */ + bool aob; /**< AOB (always on bus) present. + If set, PMU and GCI registers are + not accessible via ChipCommon, + and are instead accessible via + dedicated cores on the bhnd bus */ +}; + #endif /* _BHND_CORES_CHIPC_CHIPC_H_ */ Index: head/sys/dev/bhnd/cores/chipc/chipc_subr.c =================================================================== --- head/sys/dev/bhnd/cores/chipc/chipc_subr.c (revision 304869) +++ head/sys/dev/bhnd/cores/chipc/chipc_subr.c (revision 304870) @@ -1,525 +1,525 @@ /*- * Copyright (c) 2016 Michael Zhilin * Copyright (c) 2015-2016 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); #include #include #include "chipc_private.h" #include "chipcvar.h" /** * Return a human-readable name for the given flash @p type. */ const char * chipc_flash_name(chipc_flash type) { switch (type) { case CHIPC_PFLASH_CFI: return ("CFI Flash"); case CHIPC_SFLASH_ST: case CHIPC_SFLASH_AT: return ("SPI Flash"); case CHIPC_QSFLASH_ST: case CHIPC_QSFLASH_AT: return ("QSPI Flash"); case CHIPC_NFLASH: case CHIPC_NFLASH_4706: return ("NAND"); case CHIPC_FLASH_NONE: default: return ("unknown"); } } /** * Return the name of the bus device class used by flash @p type, * or NULL if @p type is unsupported. */ const char * chipc_flash_bus_name(chipc_flash type) { switch (type) { case CHIPC_PFLASH_CFI: return ("cfi"); case CHIPC_SFLASH_ST: case CHIPC_SFLASH_AT: return ("spi"); case CHIPC_QSFLASH_ST: case CHIPC_QSFLASH_AT: /* unimplemented; spi? */ return (NULL); case CHIPC_NFLASH: case CHIPC_NFLASH_4706: /* unimplemented; nandbus? */ return (NULL); case CHIPC_FLASH_NONE: default: return (NULL); } } /** * Return the name of the flash device class for SPI flash @p type, * or NULL if @p type does not use SPI, or is unsupported. */ const char * chipc_sflash_device_name(chipc_flash type) { switch (type) { case CHIPC_SFLASH_ST: return ("mx25l"); case CHIPC_SFLASH_AT: return ("at45d"); case CHIPC_QSFLASH_ST: case CHIPC_QSFLASH_AT: /* unimplemented */ return (NULL); case CHIPC_PFLASH_CFI: case CHIPC_NFLASH: case CHIPC_NFLASH_4706: case CHIPC_FLASH_NONE: default: return (NULL); } } /** * Initialize child resource @p r with a virtual address, tag, and handle * copied from @p parent, adjusted to contain only the range defined by * @p offsize and @p size. * * @param r The register to be initialized. * @param parent The parent bus resource that fully contains the subregion. * @param offset The subregion offset within @p parent. * @param size The subregion size. */ int chipc_init_child_resource(struct resource *r, struct resource *parent, bhnd_size_t offset, bhnd_size_t size) { bus_space_handle_t bh, child_bh; bus_space_tag_t bt; uintptr_t vaddr; int error; /* Fetch the parent resource's bus values */ vaddr = (uintptr_t) rman_get_virtual(parent); bt = rman_get_bustag(parent); bh = rman_get_bushandle(parent); /* Configure child resource with offset-adjusted values */ vaddr += offset; error = bus_space_subregion(bt, bh, offset, size, &child_bh); if (error) return (error); rman_set_virtual(r, (void *) vaddr); rman_set_bustag(r, bt); rman_set_bushandle(r, child_bh); return (0); } /** * Associate a resource with a given resource ID, relative to the given * port and region. * * This function behaves identically to bus_set_resource() for all resource * types other than SYS_RES_MEMORY. * * For SYS_RES_MEMORY resources, the specified @p region's address and size * will be fetched from the bhnd(4) bus, and bus_set_resource() will be called * with @p start added the region's actual base address. * * To use the default region values for @p start and @p count, specify * a @p start value of 0ul, and an end value of RMAN_MAX_END * * @param sc chipc driver state. * @param child The device to set the resource on. * @param type The resource type. * @param rid The resource ID. * @param start The resource start address (if SYS_RES_MEMORY, this is * relative to @p region's base address). * @param count The length of the resource. * @param port The mapping port number (ignored if not SYS_RES_MEMORY). * @param region The mapping region number (ignored if not SYS_RES_MEMORY). */ int chipc_set_resource(struct chipc_softc *sc, device_t child, int type, int rid, rman_res_t start, rman_res_t count, u_int port, u_int region) { bhnd_addr_t region_addr; bhnd_size_t region_size; bool isdefault; int error; if (type != SYS_RES_MEMORY) return (bus_set_resource(child, type, rid, start, count)); isdefault = RMAN_IS_DEFAULT_RANGE(start, count); /* Fetch region address and size */ error = bhnd_get_region_addr(sc->dev, BHND_PORT_DEVICE, port, region, ®ion_addr, ®ion_size); if (error) { device_printf(sc->dev, "lookup of %s%u.%u failed: %d\n", bhnd_port_type_name(BHND_PORT_DEVICE), port, region, error); return (error); } /* Populate defaults */ if (isdefault) { start = 0; count = region_size; } /* Verify requested range is mappable */ if (start > region_size || region_size - start < count) { device_printf(sc->dev, "%s%u.%u region cannot map requested range %#jx+%#jx\n", bhnd_port_type_name(BHND_PORT_DEVICE), port, region, start, count); return (ERANGE); } return (bus_set_resource(child, type, rid, region_addr + start, count)); } /* * Print a capability structure. */ void chipc_print_caps(device_t dev, struct chipc_caps *caps) { #define CC_TFS(_flag) (caps->_flag ? "yes" : "no") device_printf(dev, "MIPSEB: %-3s | BP64: %s\n", CC_TFS(mipseb), CC_TFS(backplane_64)); device_printf(dev, "UARTs: %-3hhu | UGPIO: %s\n", caps->num_uarts, CC_TFS(uart_gpio)); // XXX: hitting a kvprintf bug with '%#02x' not prefixing '0x' in // some cases, and not apply the field width in others device_printf(dev, "UARTClk: 0x%02x | Flash: %u\n", caps->uart_clock, caps->flash_type); device_printf(dev, "SPROM: %-3s | OTP: %s\n", CC_TFS(sprom), CC_TFS(otp_size)); device_printf(dev, "CFIsz: 0x%02x | OTPsz: 0x%02x\n", caps->cfi_width, caps->otp_size); - device_printf(dev, "ExtBus: 0x%02x | PwCtl: %s\n", - caps->extbus_type, CC_TFS(power_control)); + device_printf(dev, "ExtBus: 0x%02x | PwrCtrl: %s\n", + caps->extbus_type, CC_TFS(pwr_ctrl)); device_printf(dev, "PLL: 0x%02x | JTAGM: %s\n", caps->pll_type, CC_TFS(jtag_master)); device_printf(dev, "PMU: %-3s | ECI: %s\n", CC_TFS(pmu), CC_TFS(eci)); device_printf(dev, "SECI: %-3s | GSIO: %s\n", CC_TFS(seci), CC_TFS(gsio)); device_printf(dev, "AOB: %-3s | BootROM: %s\n", CC_TFS(aob), CC_TFS(boot_rom)); #undef CC_TFS } /** * Allocate and initialize new region record. * * @param sc Driver instance state. * @param type The port type to query. * @param port The port number to query. * @param region The region number to query. */ struct chipc_region * chipc_alloc_region(struct chipc_softc *sc, bhnd_port_type type, u_int port, u_int region) { struct chipc_region *cr; int error; /* Don't bother allocating a chipc_region if init will fail */ if (!bhnd_is_region_valid(sc->dev, type, port, region)) return (NULL); /* Allocate and initialize region info */ cr = malloc(sizeof(*cr), M_BHND, M_NOWAIT); if (cr == NULL) return (NULL); cr->cr_port_type = type; cr->cr_port_num = port; cr->cr_region_num = region; cr->cr_res = NULL; cr->cr_refs = 0; cr->cr_act_refs = 0; error = bhnd_get_region_addr(sc->dev, type, port, region, &cr->cr_addr, &cr->cr_count); if (error) { device_printf(sc->dev, "fetching chipc region address failed: %d\n", error); goto failed; } cr->cr_end = cr->cr_addr + cr->cr_count - 1; /* Fetch default resource ID for this region. Not all regions have an * assigned rid, in which case this will return -1 */ cr->cr_rid = bhnd_get_port_rid(sc->dev, type, port, region); return (cr); failed: device_printf(sc->dev, "chipc region alloc failed for %s%u.%u\n", bhnd_port_type_name(type), port, region); free(cr, M_BHND); return (NULL); } /** * Deallocate the given region record and its associated resource, if any. * * @param sc Driver instance state. * @param cr Region record to be deallocated. */ void chipc_free_region(struct chipc_softc *sc, struct chipc_region *cr) { KASSERT(cr->cr_refs == 0, ("chipc %s%u.%u region has %u active references", bhnd_port_type_name(cr->cr_port_type), cr->cr_port_num, cr->cr_region_num, cr->cr_refs)); if (cr->cr_res != NULL) { bhnd_release_resource(sc->dev, SYS_RES_MEMORY, cr->cr_res_rid, cr->cr_res); } free(cr, M_BHND); } /** * Locate the region mapping the given range, if any. Returns NULL if no * valid region is found. * * @param sc Driver instance state. * @param start start of address range. * @param end end of address range. */ struct chipc_region * chipc_find_region(struct chipc_softc *sc, rman_res_t start, rman_res_t end) { struct chipc_region *cr; if (start > end) return (NULL); STAILQ_FOREACH(cr, &sc->mem_regions, cr_link) { if (start < cr->cr_addr || end > cr->cr_end) continue; /* Found */ return (cr); } /* Not found */ return (NULL); } /** * Locate a region mapping by its bhnd-assigned resource id (as returned by * bhnd_get_port_rid). * * @param sc Driver instance state. * @param rid Resource ID to query for. */ struct chipc_region * chipc_find_region_by_rid(struct chipc_softc *sc, int rid) { struct chipc_region *cr; int port_rid; STAILQ_FOREACH(cr, &sc->mem_regions, cr_link) { port_rid = bhnd_get_port_rid(sc->dev, cr->cr_port_type, cr->cr_port_num, cr->cr_region_num); if (port_rid == -1 || port_rid != rid) continue; /* Found */ return (cr); } /* Not found */ return (NULL); } /** * Retain a reference to a chipc_region, allocating and activating the * backing resource as required. * * @param sc chipc driver instance state * @param cr region to retain. * @param flags specify RF_ALLOCATED to retain an allocation reference, * RF_ACTIVE to retain an activation reference. */ int chipc_retain_region(struct chipc_softc *sc, struct chipc_region *cr, int flags) { int error; KASSERT(!(flags &~ (RF_ACTIVE|RF_ALLOCATED)), ("unsupported flags")); CHIPC_LOCK(sc); /* Handle allocation */ if (flags & RF_ALLOCATED) { /* If this is the first reference, allocate the resource */ if (cr->cr_refs == 0) { KASSERT(cr->cr_res == NULL, ("non-NULL resource has refcount")); /* Fetch initial resource ID */ if ((cr->cr_res_rid = cr->cr_rid) == -1) { CHIPC_UNLOCK(sc); return (EINVAL); } /* Allocate resource */ cr->cr_res = bhnd_alloc_resource(sc->dev, SYS_RES_MEMORY, &cr->cr_res_rid, cr->cr_addr, cr->cr_end, cr->cr_count, 0); if (cr->cr_res == NULL) { CHIPC_UNLOCK(sc); return (ENXIO); } } /* Increment allocation refcount */ cr->cr_refs++; } /* Handle activation */ if (flags & RF_ACTIVE) { KASSERT(cr->cr_refs > 0, ("cannot activate unallocated resource")); /* If this is the first reference, activate the resource */ if (cr->cr_act_refs == 0) { error = bhnd_activate_resource(sc->dev, SYS_RES_MEMORY, cr->cr_res_rid, cr->cr_res); if (error) { /* Drop any allocation reference acquired * above */ CHIPC_UNLOCK(sc); chipc_release_region(sc, cr, flags &~ RF_ACTIVE); return (error); } } /* Increment activation refcount */ cr->cr_act_refs++; } CHIPC_UNLOCK(sc); return (0); } /** * Release a reference to a chipc_region, deactivating and releasing the * backing resource if the reference count hits zero. * * @param sc chipc driver instance state * @param cr region to retain. * @param flags specify RF_ALLOCATED to release an allocation reference, * RF_ACTIVE to release an activation reference. */ int chipc_release_region(struct chipc_softc *sc, struct chipc_region *cr, int flags) { int error; CHIPC_LOCK(sc); error = 0; KASSERT(cr->cr_res != NULL, ("release on NULL region resource")); if (flags & RF_ACTIVE) { KASSERT(cr->cr_act_refs > 0, ("RF_ACTIVE over-released")); KASSERT(cr->cr_act_refs <= cr->cr_refs, ("RF_ALLOCATED released with RF_ACTIVE held")); /* If this is the last reference, deactivate the resource */ if (cr->cr_act_refs == 1) { error = bhnd_deactivate_resource(sc->dev, SYS_RES_MEMORY, cr->cr_res_rid, cr->cr_res); if (error) goto done; } /* Drop our activation refcount */ cr->cr_act_refs--; } if (flags & RF_ALLOCATED) { KASSERT(cr->cr_refs > 0, ("overrelease of refs")); /* If this is the last reference, release the resource */ if (cr->cr_refs == 1) { error = bhnd_release_resource(sc->dev, SYS_RES_MEMORY, cr->cr_res_rid, cr->cr_res); if (error) goto done; cr->cr_res = NULL; } /* Drop our allocation refcount */ cr->cr_refs--; } done: CHIPC_UNLOCK(sc); return (error); } Index: head/sys/dev/bhnd/cores/chipc/chipcreg.h =================================================================== --- head/sys/dev/bhnd/cores/chipc/chipcreg.h (revision 304869) +++ head/sys/dev/bhnd/cores/chipc/chipcreg.h (revision 304870) @@ -1,1553 +1,962 @@ /*- * Copyright (c) 2015-2016 Landon Fuller * Copyright (c) 2010 Broadcom Corporation * All rights reserved. * * This file is derived from the sbchipc.h header distributed with * Broadcom's initial brcm80211 Linux driver release, as * contributed to the Linux staging repository. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ #ifndef _BHND_CORES_CHIPC_CHIPCREG_H_ #define _BHND_CORES_CHIPC_CHIPCREG_H_ #define CHIPC_CHIPID_SIZE 0x100 /**< size of the register block containing the chip identification registers required during bus enumeration */ /** Evaluates to true if the given ChipCommon core revision provides * the core count via the chip identification register. */ #define CHIPC_NCORES_MIN_HWREV(hwrev) ((hwrev) == 4 || (hwrev) >= 6) /** Evaluates to true if the given ChipCommon core revision supports * the CHIPC_CAPABILITIES_EXT register */ #define CHIPC_HWREV_HAS_CAP_EXT(hwrev) ((hwrev) >= 35) /** Evaluates to true if the chipcommon core (determined from the provided * @p _chipid (CHIPC_ID) register value) provides a pointer to the enumeration * table via CHIPC_EROMPTR */ #define CHIPC_HAS_EROMPTR(_chipid) \ (CHIPC_GET_BITS((_chipid), CHIPC_ID_BUS) != BHND_CHIPTYPE_SIBA) #define CHIPC_GET_FLAG(_value, _flag) (((_value) & _flag) != 0) #define CHIPC_GET_BITS(_value, _field) \ ((_value & _field ## _MASK) >> _field ## _SHIFT) #define CHIPC_ID 0x00 #define CHIPC_CAPABILITIES 0x04 #define CHIPC_CORECTRL 0x08 /* rev >= 1 */ #define CHIPC_BIST 0x0C #define CHIPC_OTPST 0x10 /**< otp status */ #define CHIPC_OTPCTRL 0x14 /**< otp control */ #define CHIPC_OTPPROG 0x18 #define CHIPC_OTPLAYOUT 0x1C /**< otp layout (IPX OTP) */ #define CHIPC_INTST 0x20 /**< interrupt status */ #define CHIPC_INTM 0x24 /**< interrupt mask */ #define CHIPC_CHIPCTRL 0x28 /**< chip control (rev >= 11) */ #define CHIPC_CHIPST 0x2C /**< chip status (rev >= 11) */ #define CHIPC_JTAGCMD 0x30 #define CHIPC_JTAGIR 0x34 #define CHIPC_JTAGDR 0x38 #define CHIPC_JTAGCTRL 0x3c #define CHIPC_SFLASH_BASE 0x40 #define CHIPC_SFLASH_SIZE 12 #define CHIPC_SFLASHCTRL 0x40 #define CHIPC_SFLASHADDR 0x44 #define CHIPC_SFLASHDATA 0x48 /* siba backplane configuration broadcast (siba-only) */ #define CHIPC_SBBCAST_ADDR 0x50 #define CHIPC_SBBCAST_DATA 0x54 #define CHIPC_GPIOPU 0x58 /**< pull-up mask (rev >= 20) */ #define CHIPC_GPIOPD 0x5C /**< pull down mask (rev >= 20) */ #define CHIPC_GPIOIN 0x60 #define CHIPC_GPIOOUT 0x64 #define CHIPC_GPIOOUTEN 0x68 #define CHIPC_GPIOCTRL 0x6C #define CHIPC_GPIOPOL 0x70 #define CHIPC_GPIOINTM 0x74 /**< gpio interrupt mask */ #define CHIPC_GPIOEVENT 0x78 /**< gpio event (rev >= 11) */ #define CHIPC_GPIOEVENT_INTM 0x7C /**< gpio event interrupt mask (rev >= 11) */ #define CHIPC_WATCHDOG 0x80 /**< watchdog timer */ #define CHIPC_GPIOEVENT_INTPOLARITY 0x84 /**< gpio even interrupt polarity (rev >= 11) */ #define CHIPC_GPIOTIMERVAL 0x88 /**< gpio-based LED duty cycle (rev >= 16) */ #define CHIPC_GPIOTIMEROUTMASK 0x8C -/* clock control block */ +/* clock control registers (non-PMU devices) */ #define CHIPC_CLKC_N 0x90 #define CHIPC_CLKC_SB 0x94 /* m0 (backplane) */ #define CHIPC_CLKC_PCI 0x98 /* m1 */ #define CHIPC_CLKC_M2 0x9C /* mii/uart/mipsref */ #define CHIPC_CLKC_M3 0xA0 /* cpu */ #define CHIPC_CLKDIV 0xA4 /* rev >= 3 */ + #define CHIPC_GPIODEBUGSEL 0xA8 /* rev >= 28 */ #define CHIPC_CAPABILITIES_EXT 0xAC -/* pll delay (registers rev >= 4) */ -#define CHIPC_PLL_ON_DELAY 0xB0 -#define CHIPC_PLL_FREFSEL_DELAY 0xB4 -#define CHIPC_PLL_SLOWCLK_CTL 0xB8 /* revs 6-9 */ +/* pll/slowclk clock control registers (rev >= 4) */ +#define CHIPC_PLL_ON_DELAY 0xB0 /* rev >= 4 */ +#define CHIPC_PLL_FREFSEL_DELAY 0xB4 /* rev >= 4 */ +#define CHIPC_PLL_SLOWCLK_CTL 0xB8 /* "slowclock" (rev 6-9) */ + + /* "instaclock" clock control registers */ +#define CHIPC_SYS_CLK_CTL 0xC0 /* "instaclock" (rev >= 10) */ +#define CHIPC_SYS_CLK_ST_STRETCH 0xC4 /* state strech (?) rev >= 10 */ -/* "instaclock" registers */ -#define CHIPC_SYS_CLK_CTL 0xC0 /* rev >= 10 */ -#define CHIPC_SYS_CLKSTATESTRETCH 0xC4 /* rev >= 10 */ - /* indirect backplane access (rev >= 10) */ #define CHIPC_BP_ADDRLOW 0xD0 #define CHIPC_BP_ADDRHIGH 0xD4 #define CHIPC_BP_DATA 0xD8 #define CHIPC_BP_INDACCESS 0xE0 /* SPI/I2C (rev >= 37) */ #define CHIPC_GSIO_CTRL 0xE4 #define CHIPC_GSIO_ADDR 0xE8 #define CHIPC_GSIO_DATA 0xEC /* More clock dividers (corerev >= 32) */ #define CHIPC_CLKDIV2 0xF0 #define CHIPC_EROMPTR 0xFC /**< 32-bit EROM base address * on BCMA devices */ - + /* ExtBus control registers (rev >= 3) */ #define CHIPC_PCMCIA_CFG 0x100 #define CHIPC_PCMCIA_MEMWAIT 0x104 #define CHIPC_PCMCIA_ATTRWAIT 0x108 #define CHIPC_PCMCIA_IOWAIT 0x10C #define CHIPC_IDE_CFG 0x110 #define CHIPC_IDE_MEMWAIT 0x114 #define CHIPC_IDE_ATTRWAIT 0x118 #define CHIPC_IDE_IOWAIT 0x11C #define CHIPC_PROG_CFG 0x120 #define CHIPC_PROG_WAITCOUNT 0x124 #define CHIPC_FLASH_CFG 0x128 #define CHIPC_FLASH_WAITCOUNT 0x12C #define CHIPC_SECI_CFG 0x130 #define CHIPC_SECI_ST 0x134 #define CHIPC_SECI_STM 0x138 #define CHIPC_SECI_RXNBC 0x13C /* Enhanced Coexistence Interface (ECI) registers (rev 21-34) */ #define CHIPC_ECI_OUTPUT 0x140 #define CHIPC_ECI_CTRL 0x144 #define CHIPC_ECI_INPUTLO 0x148 #define CHIPC_ECI_INPUTMI 0x14C #define CHIPC_ECI_INPUTHI 0x150 #define CHIPC_ECI_INPUTINTPOLARITYLO 0x154 #define CHIPC_ECI_INPUTINTPOLARITYMI 0x158 #define CHIPC_ECI_INPUTINTPOLARITYHI 0x15C #define CHIPC_ECI_INTMASKLO 0x160 #define CHIPC_ECI_INTMASKMI 0x164 #define CHIPC_ECI_INTMASKHI 0x168 #define CHIPC_ECI_EVENTLO 0x16C #define CHIPC_ECI_EVENTMI 0x170 #define CHIPC_ECI_EVENTHI 0x174 #define CHIPC_ECI_EVENTMASKLO 0x178 #define CHIPC_ECI_EVENTMASKMI 0x17C #define CHIPC_ECI_EVENTMASKHI 0x180 #define CHIPC_FLASHSTRCFG 0x18C /**< BCM4706 NAND flash config */ #define CHIPC_SPROM_CTRL 0x190 /**< SPROM interface (rev >= 32) */ #define CHIPC_SPROM_ADDR 0x194 #define CHIPC_SPROM_DATA 0x198 /* Clock control and hardware workarounds (corerev >= 20) */ #define CHIPC_CLK_CTL_ST 0x1E0 #define CHIPC_SPROM_HWWAR 0x19 #define CHIPC_UART_BASE 0x300 #define CHIPC_UART_SIZE 0x100 #define CHIPC_UART_MAX 3 /**< max UART blocks */ #define CHIPC_UART(_n) (CHIPC_UART_BASE + (CHIPC_UART_SIZE*_n)) -/* PMU registers (rev >= 20) */ +/* PMU register block (rev >= 20) */ #define CHIPC_PMU_BASE 0x600 #define CHIPC_PMU_SIZE 0x70 -#define CHIPC_PMU_CTRL 0x600 -#define CHIPC_PMU_CAP 0x604 -#define CHIPC_PMU_ST 0x608 -#define CHIPC_PMU_RES_STATE 0x60c -#define CHIPC_PMU_RES_PENDING 0x610 -#define CHIPC_PMU_TIMER 0x614 -#define CHIPC_PMU_MIN_RES_MASK 0x618 -#define CHIPC_PMU_MAX_RES_MASK 0x61c -#define CHIPC_PMU_RES_TABLE_SEL 0x620 -#define CHIPC_PMU_RES_DEP_MASK 0x624 -#define CHIPC_PMU_RES_UPDN_TIMER 0x628 -#define CHIPC_PMU_RES_TIMER 0x62C -#define CHIPC_PMU_CLKSTRETCH 0x630 -#define CHIPC_PMU_WATCHDOG 0x634 -#define CHIPC_PMU_GPIOSEL 0x638 /* pmu rev >= 1 ? */ -#define CHIPC_PMU_GPIOEN 0x63C /* pmu rev >= 1 ? */ -#define CHIPC_PMU_RES_REQ_TIMER_SEL 0x640 -#define CHIPC_PMU_RES_REQ_TIMER 0x644 -#define CHIPC_PMU_RES_REQ_MASK 0x648 -#define CHIPC_CHIPCTL_ADDR 0x650 -#define CHIPC_CHIPCTL_DATA 0x654 -#define CHIPC_PMU_REG_CONTROL_ADDR 0x658 -#define CHIPC_PMU_REG_CONTROL_DATA 0x65C -#define CHIPC_PMU_PLL_CONTROL_ADDR 0x660 -#define CHIPC_PMU_PLL_CONTROL_DATA 0x664 -#define CHIPC_PMU_STRAPOPT 0x668 /* chipc rev >= 28 */ -#define CHIPC_PMU_XTALFREQ 0x66C /* pmu rev >= 10 */ - #define CHIPC_SPROM_OTP 0x800 /* SPROM/OTP address space */ #define CHIPC_SPROM_OTP_SIZE 0x400 /** chipid */ #define CHIPC_ID_CHIP_MASK 0x0000FFFF /**< chip id */ #define CHIPC_ID_CHIP_SHIFT 0 #define CHIPC_ID_REV_MASK 0x000F0000 /**< chip revision */ #define CHIPC_ID_REV_SHIFT 16 #define CHIPC_ID_PKG_MASK 0x00F00000 /**< physical package ID */ #define CHIPC_ID_PKG_SHIFT 20 #define CHIPC_ID_NUMCORE_MASK 0x0F000000 /**< number of cores on chip (rev >= 4) */ #define CHIPC_ID_NUMCORE_SHIFT 24 #define CHIPC_ID_BUS_MASK 0xF0000000 /**< chip/interconnect type (BHND_CHIPTYPE_*) */ #define CHIPC_ID_BUS_SHIFT 28 /* capabilities */ #define CHIPC_CAP_NUM_UART_MASK 0x00000003 /* Number of UARTs (1-3) */ #define CHIPC_CAP_NUM_UART_SHIFT 0 #define CHIPC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */ #define CHIPC_CAP_UCLKSEL_MASK 0x00000018 /* UARTs clock select */ #define CHIPC_CAP_UCLKSEL_SHIFT 3 #define CHIPC_CAP_UCLKSEL_UINTCLK 0x1 /* UARTs are driven by internal divided clock */ #define CHIPC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */ #define CHIPC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */ #define CHIPC_CAP_EXTBUS_SHIFT 6 #define CHIPC_CAP_EXTBUS_NONE 0x0 /* No ExtBus present */ #define CHIPC_CAP_EXTBUS_FULL 0x1 /* ExtBus: PCMCIA, IDE & Prog */ #define CHIPC_CAP_EXTBUS_PROG 0x2 /* ExtBus: ProgIf only */ #define CHIPC_CAP_FLASH_MASK 0x00000700 /* Type of flash */ #define CHIPC_CAP_FLASH_SHIFT 8 #define CHIPC_CAP_FLASH_NONE 0x0 /* No flash */ #define CHIPC_CAP_SFLASH_ST 0x1 /* ST serial flash */ #define CHIPC_CAP_SFLASH_AT 0x2 /* Atmel serial flash */ #define CHIPC_CAP_NFLASH 0x3 /* NAND flash */ #define CHIPC_CAP_PFLASH 0x7 /* Parallel flash */ #define CHIPC_CAP_PLL_MASK 0x00038000 /* Type of PLL */ #define CHIPC_CAP_PLL_SHIFT 15 -#define CHIPC_CAP_PWR_CTL 0x00040000 /* Power control */ +#define CHIPC_CAP_PWR_CTL 0x00040000 /* Power/clock control */ #define CHIPC_CAP_OTP_SIZE_MASK 0x00380000 /* OTP Size (0 = none) */ #define CHIPC_CAP_OTP_SIZE_SHIFT 19 /* OTP Size shift */ #define CHIPC_CAP_OTP_SIZE_BASE 5 /* OTP Size base */ #define CHIPC_CAP_JTAGP 0x00400000 /* JTAG Master Present */ #define CHIPC_CAP_ROM 0x00800000 /* Internal boot rom active */ #define CHIPC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */ #define CHIPC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */ #define CHIPC_CAP_ECI 0x20000000 /* Enhanced Coexistence Interface */ #define CHIPC_CAP_SPROM 0x40000000 /* SPROM Present, rev >= 32 */ #define CHIPC_CAP_4706_NFLASH 0x80000000 /* NAND flash present, BCM4706 or chipc rev38 (BCM5357)? */ #define CHIPC_CAP2_SECI 0x00000001 /* SECI Present, rev >= 36 */ #define CHIPC_CAP2_GSIO 0x00000002 /* GSIO (spi/i2c) present, rev >= 37 */ #define CHIPC_CAP2_GCI 0x00000004 /* GCI present (rev >= ??) */ #define CHIPC_CAP2_AOB 0x00000040 /* Always on Bus present (rev >= 49) * * If set, PMU and GCI registers * are found in dedicated cores. * * This appears to be a lower power * APB bus, bridged via ARM APB IP. */ /* * ChipStatus (Common) */ /** ChipStatus CIS/OTP/SPROM values used to advertise OTP/SPROM availability in * chipcommon revs 11-31. */ enum { CHIPC_CST_DEFCIS_SEL = 0, /**< OTP is powered up, use default CIS, no SPROM */ CHIPC_CST_SPROM_SEL = 1, /**< OTP is powered up, SPROM is present */ CHIPC_CST_OTP_SEL = 2, /**< OTP is powered up, no SPROM */ CHIPC_CST_OTP_PWRDN = 3 /**< OTP is powered down, SPROM is present (rev <= 22 only) */ }; #define CHIPC_CST_SPROM_OTP_SEL_R22_MASK 0x00000003 /**< chipstatus OTP/SPROM SEL value (rev 22) */ #define CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT 0 #define CHIPC_CST_SPROM_OTP_SEL_R23_MASK 0x000000c0 /**< chipstatus OTP/SPROM SEL value (revs 23-31) * * it is unknown whether this is supported on * any CC revs >= 32 that also vend CHIPC_CAP_* * constants for OTP/SPROM/NVRAM availability. */ #define CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT 6 /* PLL type */ -#define CHIPC_PLL_NONE 0x00000000 -#define CHIPC_PLL_TYPE1 0x00010000 /* 48MHz base, 3 dividers */ -#define CHIPC_PLL_TYPE2 0x00020000 /* 48MHz, 4 dividers */ -#define CHIPC_PLL_TYPE3 0x00030000 /* 25MHz, 2 dividers */ -#define CHIPC_PLL_TYPE4 0x00008000 /* 48MHz, 4 dividers */ -#define CHIPC_PLL_TYPE5 0x00018000 /* 25MHz, 4 dividers */ -#define CHIPC_PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */ -#define CHIPC_PLL_TYPE7 0x00038000 /* 25MHz, 4 dividers */ +#define CHIPC_PLL_NONE 0x00 +#define CHIPC_PLL_TYPE1 0x10 /* 48MHz base, 3 dividers */ +#define CHIPC_PLL_TYPE2 0x20 /* 48MHz, 4 dividers */ +#define CHIPC_PLL_TYPE3 0x30 /* 25MHz, 2 dividers */ +#define CHIPC_PLL_TYPE4 0x08 /* 48MHz, 4 dividers */ +#define CHIPC_PLL_TYPE5 0x18 /* 25MHz, 4 dividers */ +#define CHIPC_PLL_TYPE6 0x28 /* 100/200 or 120/240 only */ +#define CHIPC_PLL_TYPE7 0x38 /* 25MHz, 4 dividers */ -/* ILP clock */ -#define CHIPC_ILP_CLOCK 32000 +/* dynamic clock control defines */ +#define CHIPC_LPOMINFREQ 25000 /* low power oscillator min */ +#define CHIPC_LPOMAXFREQ 43000 /* low power oscillator max */ +#define CHIPC_XTALMINFREQ 19800000 /* 20 MHz - 1% */ +#define CHIPC_XTALMAXFREQ 20200000 /* 20 MHz + 1% */ +#define CHIPC_PCIMINFREQ 25000000 /* 25 MHz */ +#define CHIPC_PCIMAXFREQ 34000000 /* 33 MHz + fudge */ -/* ALP clock on pre-PMU chips */ -#define CHIPC_ALP_CLOCK 20000000 +#define CHIPC_ILP_DIV_5MHZ 0 /* ILP = 5 MHz */ +#define CHIPC_ILP_DIV_1MHZ 4 /* ILP = 1 MHz */ -/* HT clock */ -#define CHIPC_HT_CLOCK 80000000 +/* Power Control Defines */ +#define CHIPC_PLL_DELAY 150 /* us pll on delay */ +#define CHIPC_FREF_DELAY 200 /* us fref change delay */ +#define CHIPC_MIN_SLOW_CLK 32 /* us Slow clock period */ +#define CHIPC_XTAL_ON_DELAY 1000 /* us crystal power-on delay */ /* corecontrol */ #define CHIPC_UARTCLKO 0x00000001 /* Drive UART with internal clock */ #define CHIPC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ #define CHIPC_UARTCLKEN 0x00000008 /* enable UART Clock (corerev > = 21 */ /* chipcontrol */ #define CHIPCTRL_4321A0_DEFAULT 0x3a4 #define CHIPCTRL_4321A1_DEFAULT 0x0a4 #define CHIPCTRL_4321_PLL_DOWN 0x800000 /* serdes PLL down override */ /* Fields in the otpstatus register in rev >= 21 */ #define CHIPC_OTPS_OL_MASK 0x000000ff #define CHIPC_OTPS_OL_MFG 0x00000001 /* manuf row is locked */ #define CHIPC_OTPS_OL_OR1 0x00000002 /* otp redundancy row 1 is locked */ #define CHIPC_OTPS_OL_OR2 0x00000004 /* otp redundancy row 2 is locked */ #define CHIPC_OTPS_OL_GU 0x00000008 /* general use region is locked */ #define CHIPC_OTPS_GUP_MASK 0x00000f00 #define CHIPC_OTPS_GUP_SHIFT 8 #define CHIPC_OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */ #define CHIPC_OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */ #define CHIPC_OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */ #define CHIPC_OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */ #define CHIPC_OTPS_READY 0x00001000 #define CHIPC_OTPS_RV(x) (1 << (16 + (x))) /* redundancy entry valid */ #define CHIPC_OTPS_RV_MASK 0x0fff0000 /* IPX OTP fields in the otpcontrol register */ #define CHIPC_OTPC_PROGSEL 0x00000001 #define CHIPC_OTPC_PCOUNT_MASK 0x0000000e #define CHIPC_OTPC_PCOUNT_SHIFT 1 #define CHIPC_OTPC_VSEL_MASK 0x000000f0 #define CHIPC_OTPC_VSEL_SHIFT 4 #define CHIPC_OTPC_TMM_MASK 0x00000700 #define CHIPC_OTPC_TMM_SHIFT 8 #define CHIPC_OTPC_ODM 0x00000800 #define CHIPC_OTPC_PROGEN 0x80000000 /* Fields in otpprog in IPX OTP and HND OTP */ #define CHIPC_OTPP_COL_MASK 0x000000ff #define CHIPC_OTPP_COL_SHIFT 0 #define CHIPC_OTPP_ROW_MASK 0x0000ff00 #define CHIPC_OTPP_ROW_SHIFT 8 #define CHIPC_OTPP_OC_MASK 0x0f000000 #define CHIPC_OTPP_OC_SHIFT 24 #define CHIPC_OTPP_READERR 0x10000000 #define CHIPC_OTPP_VALUE_MASK 0x20000000 #define CHIPC_OTPP_VALUE_SHIFT 29 #define CHIPC_OTPP_START_BUSY 0x80000000 #define CHIPC_OTPP_READ 0x40000000 /* HND OTP */ /* otplayout */ #define CHIPC_OTPL_SIZE_MASK 0x0000f000 /* rev >= 49 */ #define CHIPC_OTPL_SIZE_SHIFT 12 #define CHIPC_OTPL_GUP_MASK 0x00000FFF /* bit offset to general use region */ #define CHIPC_OTPL_GUP_SHIFT 0 #define CHIPC_OTPL_CISFORMAT_NEW 0x80000000 /* rev >= 36 */ /* Opcodes for OTPP_OC field */ #define CHIPC_OTPPOC_READ 0 #define CHIPC_OTPPOC_BIT_PROG 1 #define CHIPC_OTPPOC_VERIFY 3 #define CHIPC_OTPPOC_INIT 4 #define CHIPC_OTPPOC_SET 5 #define CHIPC_OTPPOC_RESET 6 #define CHIPC_OTPPOC_OCST 7 #define CHIPC_OTPPOC_ROW_LOCK 8 #define CHIPC_OTPPOC_PRESCN_TEST 9 /* Jtagm characteristics that appeared at a given corerev */ #define CHIPC_JTAGM_CREV_OLD 10 /* Old command set, 16bit max IR */ #define CHIPC_JTAGM_CREV_IRP 22 /* Able to do pause-ir */ #define CHIPC_JTAGM_CREV_RTI 28 /* Able to do return-to-idle */ /* jtagcmd */ #define CHIPC_JCMD_START 0x80000000 #define CHIPC_JCMD_BUSY 0x80000000 #define CHIPC_JCMD_STATE_MASK 0x60000000 #define CHIPC_JCMD_STATE_TLR 0x00000000 /* Test-logic-reset */ #define CHIPC_JCMD_STATE_PIR 0x20000000 /* Pause IR */ #define CHIPC_JCMD_STATE_PDR 0x40000000 /* Pause DR */ #define CHIPC_JCMD_STATE_RTI 0x60000000 /* Run-test-idle */ #define CHIPC_JCMD0_ACC_MASK 0x0000f000 #define CHIPC_JCMD0_ACC_IRDR 0x00000000 #define CHIPC_JCMD0_ACC_DR 0x00001000 #define CHIPC_JCMD0_ACC_IR 0x00002000 #define CHIPC_JCMD0_ACC_RESET 0x00003000 #define CHIPC_JCMD0_ACC_IRPDR 0x00004000 #define CHIPC_JCMD0_ACC_PDR 0x00005000 #define CHIPC_JCMD0_IRW_MASK 0x00000f00 #define CHIPC_JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */ #define CHIPC_JCMD_ACC_IRDR 0x00000000 #define CHIPC_JCMD_ACC_DR 0x00010000 #define CHIPC_JCMD_ACC_IR 0x00020000 #define CHIPC_JCMD_ACC_RESET 0x00030000 #define CHIPC_JCMD_ACC_IRPDR 0x00040000 #define CHIPC_JCMD_ACC_PDR 0x00050000 #define CHIPC_JCMD_ACC_PIR 0x00060000 #define CHIPC_JCMD_ACC_IRDR_I 0x00070000 /* rev 28: return to run-test-idle */ #define CHIPC_JCMD_ACC_DR_I 0x00080000 /* rev 28: return to run-test-idle */ #define CHIPC_JCMD_IRW_MASK 0x00001f00 #define CHIPC_JCMD_IRW_SHIFT 8 #define CHIPC_JCMD_DRW_MASK 0x0000003f /* jtagctrl */ #define CHIPC_JCTRL_FORCE_CLK 4 /* Force clock */ #define CHIPC_JCTRL_EXT_EN 2 /* Enable external targets */ #define CHIPC_JCTRL_EN 1 /* Enable Jtag master */ /* Fields in clkdiv */ #define CHIPC_CLKD_SFLASH 0x0f000000 #define CHIPC_CLKD_SFLASH_SHIFT 24 #define CHIPC_CLKD_OTP 0x000f0000 #define CHIPC_CLKD_OTP_SHIFT 16 #define CHIPC_CLKD_JTAG 0x00000f00 #define CHIPC_CLKD_JTAG_SHIFT 8 #define CHIPC_CLKD_UART 0x000000ff #define CHIPC_CLKD2_SPROM 0x00000003 /* intstatus/intmask */ #define CHIPC_CI_GPIO 0x00000001 /* gpio intr */ #define CHIPC_CI_EI 0x00000002 /* extif intr (corerev >= 3) */ #define CHIPC_CI_TEMP 0x00000004 /* temp. ctrl intr (corerev >= 15) */ #define CHIPC_CI_SIRQ 0x00000008 /* serial IRQ intr (corerev >= 15) */ #define CHIPC_CI_PMU 0x00000020 /* pmu intr (corerev >= 21) */ #define CHIPC_CI_UART 0x00000040 /* uart intr (corerev >= 21) */ #define CHIPC_CI_WDRESET 0x80000000 /* watchdog reset occurred */ /* slow_clk_ctl */ #define CHIPC_SCC_SS_MASK 0x00000007 /* slow clock source mask */ #define CHIPC_SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */ #define CHIPC_SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */ #define CHIPC_SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */ #define CHIPC_SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */ #define CHIPC_SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, * 0: LPO is enabled */ #define CHIPC_SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, * 0: power logic control */ #define CHIPC_SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors * PLL clock disable requests from core */ #define CHIPC_SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't * disable crystal when appropriate */ #define CHIPC_SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */ #define CHIPC_SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */ #define CHIPC_SCC_CD_SHIFT 16 /* system_clk_ctl */ #define CHIPC_SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */ #define CHIPC_SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */ #define CHIPC_SYCC_FP 0x00000004 /* ForcePLLOn */ #define CHIPC_SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */ #define CHIPC_SYCC_HR 0x00000010 /* Force HT */ #define CHIPC_SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */ #define CHIPC_SYCC_CD_SHIFT 16 /* Indirect backplane access */ #define CHIPC_BPIA_BYTEEN 0x0000000f #define CHIPC_BPIA_SZ1 0x00000001 #define CHIPC_BPIA_SZ2 0x00000003 #define CHIPC_BPIA_SZ4 0x00000007 #define CHIPC_BPIA_SZ8 0x0000000f #define CHIPC_BPIA_WRITE 0x00000100 #define CHIPC_BPIA_START 0x00000200 #define CHIPC_BPIA_BUSY 0x00000200 #define CHIPC_BPIA_ERROR 0x00000400 /* pcmcia/prog/flash_config */ #define CHIPC_CF_EN 0x00000001 /* enable */ #define CHIPC_CF_EM_MASK 0x0000000e /* mode */ #define CHIPC_CF_EM_SHIFT 1 #define CHIPC_CF_EM_FLASH 0 /* flash/asynchronous mode */ #define CHIPC_CF_EM_SYNC 2 /* synchronous mode */ #define CHIPC_CF_EM_PCMCIA 4 /* pcmcia mode */ #define CHIPC_CF_DS 0x00000010 /* destsize: 0=8bit, 1=16bit */ #define CHIPC_CF_BS 0x00000020 /* byteswap */ #define CHIPC_CF_CD_MASK 0x000000c0 /* clock divider */ #define CHIPC_CF_CD_SHIFT 6 #define CHIPC_CF_CD_DIV2 0x00000000 /* backplane/2 */ #define CHIPC_CF_CD_DIV3 0x00000040 /* backplane/3 */ #define CHIPC_CF_CD_DIV4 0x00000080 /* backplane/4 */ #define CHIPC_CF_CE 0x00000100 /* clock enable */ #define CHIPC_CF_SB 0x00000200 /* size/bytestrobe (synch only) */ /* pcmcia_memwait */ #define CHIPC_PM_W0_MASK 0x0000003f /* waitcount0 */ #define CHIPC_PM_W1_MASK 0x00001f00 /* waitcount1 */ #define CHIPC_PM_W1_SHIFT 8 #define CHIPC_PM_W2_MASK 0x001f0000 /* waitcount2 */ #define CHIPC_PM_W2_SHIFT 16 #define CHIPC_PM_W3_MASK 0x1f000000 /* waitcount3 */ #define CHIPC_PM_W3_SHIFT 24 /* pcmcia_attrwait */ #define CHIPC_PA_W0_MASK 0x0000003f /* waitcount0 */ #define CHIPC_PA_W1_MASK 0x00001f00 /* waitcount1 */ #define CHIPC_PA_W1_SHIFT 8 #define CHIPC_PA_W2_MASK 0x001f0000 /* waitcount2 */ #define CHIPC_PA_W2_SHIFT 16 #define CHIPC_PA_W3_MASK 0x1f000000 /* waitcount3 */ #define CHIPC_PA_W3_SHIFT 24 /* pcmcia_iowait */ #define CHIPC_PI_W0_MASK 0x0000003f /* waitcount0 */ #define CHIPC_PI_W1_MASK 0x00001f00 /* waitcount1 */ #define CHIPC_PI_W1_SHIFT 8 #define CHIPC_PI_W2_MASK 0x001f0000 /* waitcount2 */ #define CHIPC_PI_W2_SHIFT 16 #define CHIPC_PI_W3_MASK 0x1f000000 /* waitcount3 */ #define CHIPC_PI_W3_SHIFT 24 /* prog_waitcount */ #define CHIPC_PW_W0_MASK 0x0000001f /* waitcount0 */ #define CHIPC_PW_W1_MASK 0x00001f00 /* waitcount1 */ #define CHIPC_PW_W1_SHIFT 8 #define CHIPC_PW_W2_MASK 0x001f0000 /* waitcount2 */ #define CHIPC_PW_W2_SHIFT 16 #define CHIPC_PW_W3_MASK 0x1f000000 /* waitcount3 */ #define CHIPC_PW_W3_SHIFT 24 #define CHIPC_PW_W0 0x0000000c #define CHIPC_PW_W1 0x00000a00 #define CHIPC_PW_W2 0x00020000 #define CHIPC_PW_W3 0x01000000 /* flash_waitcount */ #define CHIPC_FW_W0_MASK 0x0000003f /* waitcount0 */ #define CHIPC_FW_W1_MASK 0x00001f00 /* waitcount1 */ #define CHIPC_FW_W1_SHIFT 8 #define CHIPC_FW_W2_MASK 0x001f0000 /* waitcount2 */ #define CHIPC_FW_W2_SHIFT 16 #define CHIPC_FW_W3_MASK 0x1f000000 /* waitcount3 */ #define CHIPC_FW_W3_SHIFT 24 /* When SPROM support present, fields in spromcontrol */ #define CHIPC_SRC_START 0x80000000 #define CHIPC_SRC_BUSY 0x80000000 #define CHIPC_SRC_OPCODE 0x60000000 #define CHIPC_SRC_OP_READ 0x00000000 #define CHIPC_SRC_OP_WRITE 0x20000000 #define CHIPC_SRC_OP_WRDIS 0x40000000 #define CHIPC_SRC_OP_WREN 0x60000000 #define CHIPC_SRC_OTPSEL 0x00000010 #define CHIPC_SRC_LOCK 0x00000008 #define CHIPC_SRC_SIZE_MASK 0x00000006 #define CHIPC_SRC_SIZE_1K 0x00000000 #define CHIPC_SRC_SIZE_4K 0x00000002 #define CHIPC_SRC_SIZE_16K 0x00000004 #define CHIPC_SRC_SIZE_SHIFT 1 #define CHIPC_SRC_PRESENT 0x00000001 -/* Fields in pmucontrol */ -#define CHIPC_PCTL_ILP_DIV_MASK 0xffff0000 -#define CHIPC_PCTL_ILP_DIV_SHIFT 16 -#define CHIPC_PCTL_PLL_PLLCTL_UPD 0x00000400 /* rev 2 */ -#define CHIPC_PCTL_NOILP_ON_WAIT 0x00000200 /* rev 1 */ -#define CHIPC_PCTL_HT_REQ_EN 0x00000100 -#define CHIPC_PCTL_ALP_REQ_EN 0x00000080 -#define CHIPC_PCTL_XTALFREQ_MASK 0x0000007c -#define CHIPC_PCTL_XTALFREQ_SHIFT 2 -#define CHIPC_PCTL_ILP_DIV_EN 0x00000002 -#define CHIPC_PCTL_LPO_SEL 0x00000001 - -/* Fields in clkstretch */ -#define CHIPC_CSTRETCH_HT 0xffff0000 -#define CHIPC_CSTRETCH_ALP 0x0000ffff - /* gpiotimerval */ #define CHIPC_GPIO_ONTIME_SHIFT 16 /* clockcontrol_n */ #define CHIPC_CN_N1_MASK 0x3f /* n1 control */ +#define CHIPC_CN_N1_SHIFT 0 #define CHIPC_CN_N2_MASK 0x3f00 /* n2 control */ #define CHIPC_CN_N2_SHIFT 8 #define CHIPC_CN_PLLC_MASK 0xf0000 /* pll control */ #define CHIPC_CN_PLLC_SHIFT 16 /* clockcontrol_sb/pci/uart */ #define CHIPC_M1_MASK 0x3f /* m1 control */ +#define CHIPC_M1_SHIFT 0 #define CHIPC_M2_MASK 0x3f00 /* m2 control */ #define CHIPC_M2_SHIFT 8 #define CHIPC_M3_MASK 0x3f0000 /* m3 control */ #define CHIPC_M3_SHIFT 16 #define CHIPC_MC_MASK 0x1f000000 /* mux control */ #define CHIPC_MC_SHIFT 24 /* N3M Clock control magic field values */ #define CHIPC_F6_2 0x02 /* A factor of 2 in */ #define CHIPC_F6_3 0x03 /* 6-bit fields like */ #define CHIPC_F6_4 0x05 /* N1, M1 or M3 */ #define CHIPC_F6_5 0x09 #define CHIPC_F6_6 0x11 #define CHIPC_F6_7 0x21 #define CHIPC_F5_BIAS 5 /* 5-bit fields get this added */ #define CHIPC_MC_BYPASS 0x08 #define CHIPC_MC_M1 0x04 #define CHIPC_MC_M1M2 0x02 #define CHIPC_MC_M1M2M3 0x01 #define CHIPC_MC_M1M3 0x11 /* Type 2 Clock control magic field values */ #define CHIPC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */ #define CHIPC_T2M2_BIAS 3 /* m2 bias */ #define CHIPC_T2MC_M1BYP 1 #define CHIPC_T2MC_M2BYP 2 #define CHIPC_T2MC_M3BYP 4 /* Type 6 Clock control magic field values */ #define CHIPC_T6_MMASK 1 /* bits of interest in m */ #define CHIPC_T6_M0 120000000 /* sb clock for m = 0 */ #define CHIPC_T6_M1 100000000 /* sb clock for m = 1 */ #define CHIPC_SB2MIPS_T6(sb) (2 * (sb)) /* Common clock base */ #define CHIPC_CLOCK_BASE1 24000000 /* Half the clock freq */ #define CHIPC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLLs */ /* Clock control values for 200MHz in 5350 */ #define CHIPC_CLKC_5350_N 0x0311 #define CHIPC_CLKC_5350_M 0x04020009 /* Bits in the ExtBus config registers */ #define CHIPC_CFG_EN 0x0001 /* Enable */ #define CHIPC_CFG_EM_MASK 0x000e /* Extif Mode */ #define CHIPC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */ #define CHIPC_CFG_EM_SYNC 0x0002 /* Synchronous */ #define CHIPC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */ #define CHIPC_CFG_EM_IDE 0x0006 /* IDE */ #define CHIPC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */ #define CHIPC_FLASH_CFG_CD_MASK 0x00e0 /* Sync: Clock divisor, rev >= 20 */ #define CHIPC_FLASH_CFG_CE 0x0100 /* Sync: Clock enable, rev >= 20 */ #define CHIPC_FLASH_CFG_SB 0x0200 /* Sync: Size/Bytestrobe, rev >= 20 */ #define CHIPC_FLASH_CFG_IS 0x0400 /* Extif Sync Clk Select, rev >= 20 */ /* ExtBus address space */ #define CHIPC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */ #define CHIPC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */ #define CHIPC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */ #define CHIPC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */ #define CHIPC_EB_IDE 0x1a800000 /* IDE memory base */ #define CHIPC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */ #define CHIPC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */ #define CHIPC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */ #define CHIPC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */ /* Start/busy bit in flashcontrol */ #define CHIPC_SFLASH_OPCODE 0x000000ff #define CHIPC_SFLASH_ACTION 0x00000700 #define CHIPC_SFLASH_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */ #define CHIPC_SFLASH_START 0x80000000 #define CHIPC_SFLASH_BUSY SFLASH_START /* flashcontrol action codes */ #define CHIPC_SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */ #define CHIPC_SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */ #define CHIPC_SFLASH_ACT_OP3A 0x0200 /* opcode + 3 addr bytes */ #define CHIPC_SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addr & 1 data bytes */ #define CHIPC_SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addr & 4 data bytes */ #define CHIPC_SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addr, 4 don't care & 4 data bytes */ #define CHIPC_SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addr, 1 don't care & 4 data bytes */ /* flashcontrol action+opcodes for ST flashes */ #define CHIPC_SFLASH_ST_WREN 0x0006 /* Write Enable */ #define CHIPC_SFLASH_ST_WRDIS 0x0004 /* Write Disable */ #define CHIPC_SFLASH_ST_RDSR 0x0105 /* Read Status Register */ #define CHIPC_SFLASH_ST_WRSR 0x0101 /* Write Status Register */ #define CHIPC_SFLASH_ST_READ 0x0303 /* Read Data Bytes */ #define CHIPC_SFLASH_ST_PP 0x0302 /* Page Program */ #define CHIPC_SFLASH_ST_SE 0x02d8 /* Sector Erase */ #define CHIPC_SFLASH_ST_BE 0x00c7 /* Bulk Erase */ #define CHIPC_SFLASH_ST_DP 0x00b9 /* Deep Power-down */ #define CHIPC_SFLASH_ST_RES 0x03ab /* Read Electronic Signature */ #define CHIPC_SFLASH_ST_CSA 0x1000 /* Keep chip select asserted */ #define CHIPC_SFLASH_ST_SSE 0x0220 /* Sub-sector Erase */ /* Status register bits for ST flashes */ #define CHIPC_SFLASH_ST_WIP 0x01 /* Write In Progress */ #define CHIPC_SFLASH_ST_WEL 0x02 /* Write Enable Latch */ #define CHIPC_SFLASH_ST_BP_MASK 0x1c /* Block Protect */ #define CHIPC_SFLASH_ST_BP_SHIFT 2 #define CHIPC_SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */ /* flashcontrol action+opcodes for Atmel flashes */ #define CHIPC_SFLASH_AT_READ 0x07e8 #define CHIPC_SFLASH_AT_PAGE_READ 0x07d2 #define CHIPC_SFLASH_AT_BUF1_READ #define CHIPC_SFLASH_AT_BUF2_READ #define CHIPC_SFLASH_AT_STATUS 0x01d7 #define CHIPC_SFLASH_AT_BUF1_WRITE 0x0384 #define CHIPC_SFLASH_AT_BUF2_WRITE 0x0387 #define CHIPC_SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283 #define CHIPC_SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286 #define CHIPC_SFLASH_AT_BUF1_PROGRAM 0x0288 #define CHIPC_SFLASH_AT_BUF2_PROGRAM 0x0289 #define CHIPC_SFLASH_AT_PAGE_ERASE 0x0281 #define CHIPC_SFLASH_AT_BLOCK_ERASE 0x0250 #define CHIPC_SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382 #define CHIPC_SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385 #define CHIPC_SFLASH_AT_BUF1_LOAD 0x0253 #define CHIPC_SFLASH_AT_BUF2_LOAD 0x0255 #define CHIPC_SFLASH_AT_BUF1_COMPARE 0x0260 #define CHIPC_SFLASH_AT_BUF2_COMPARE 0x0261 #define CHIPC_SFLASH_AT_BUF1_REPROGRAM 0x0258 #define CHIPC_SFLASH_AT_BUF2_REPROGRAM 0x0259 /* Status register bits for Atmel flashes */ #define CHIPC_SFLASH_AT_READY 0x80 #define CHIPC_SFLASH_AT_MISMATCH 0x40 #define CHIPC_SFLASH_AT_ID_MASK 0x38 #define CHIPC_SFLASH_AT_ID_SHIFT 3 /* * These are the UART port assignments, expressed as offsets from the base * register. These assignments should hold for any serial port based on * a 8250, 16450, or 16550(A). */ #define CHIPC_UART_RX 0 /* In: Receive buffer (DLAB=0) */ #define CHIPC_UART_TX 0 /* Out: Transmit buffer (DLAB=0) */ #define CHIPC_UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */ #define CHIPC_UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */ #define CHIPC_UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */ #define CHIPC_UART_IIR 2 /* In: Interrupt Identity Register */ #define CHIPC_UART_FCR 2 /* Out: FIFO Control Register */ #define CHIPC_UART_LCR 3 /* Out: Line Control Register */ #define CHIPC_UART_MCR 4 /* Out: Modem Control Register */ #define CHIPC_UART_LSR 5 /* In: Line Status Register */ #define CHIPC_UART_MSR 6 /* In: Modem Status Register */ #define CHIPC_UART_SCR 7 /* I/O: Scratch Register */ #define CHIPC_UART_LCR_DLAB 0x80 /* Divisor latch access bit */ #define CHIPC_UART_LCR_WLEN8 0x03 /* Word length: 8 bits */ #define CHIPC_UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */ #define CHIPC_UART_MCR_LOOP 0x10 /* Enable loopback test mode */ #define CHIPC_UART_LSR_RX_FIFO 0x80 /* Receive FIFO error */ #define CHIPC_UART_LSR_TDHR 0x40 /* Data-hold-register empty */ #define CHIPC_UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ #define CHIPC_UART_LSR_BREAK 0x10 /* Break interrupt */ #define CHIPC_UART_LSR_FRAMING 0x08 /* Framing error */ #define CHIPC_UART_LSR_PARITY 0x04 /* Parity error */ #define CHIPC_UART_LSR_OVERRUN 0x02 /* Overrun error */ #define CHIPC_UART_LSR_RXRDY 0x01 /* Receiver ready */ #define CHIPC_UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */ /* Interrupt Identity Register (IIR) bits */ #define CHIPC_UART_IIR_FIFO_MASK 0xc0 /* IIR FIFO disable/enabled mask */ #define CHIPC_UART_IIR_INT_MASK 0xf /* IIR interrupt ID source */ #define CHIPC_UART_IIR_MDM_CHG 0x0 /* Modem status changed */ #define CHIPC_UART_IIR_NOINT 0x1 /* No interrupt pending */ #define CHIPC_UART_IIR_THRE 0x2 /* THR empty */ #define CHIPC_UART_IIR_RCVD_DATA 0x4 /* Received data available */ #define CHIPC_UART_IIR_RCVR_STATUS 0x6 /* Receiver status */ #define CHIPC_UART_IIR_CHAR_TIME 0xc /* Character time */ /* Interrupt Enable Register (IER) bits */ #define CHIPC_UART_IER_EDSSI 8 /* enable modem status interrupt */ #define CHIPC_UART_IER_ELSI 4 /* enable receiver line status interrupt */ #define CHIPC_UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */ #define CHIPC_UART_IER_ERBFI 1 /* enable data available interrupt */ -/* pmustatus */ -#define CHIPC_PST_EXTLPOAVAIL 0x0100 -#define CHIPC_PST_WDRESET 0x0080 -#define CHIPC_PST_INTPEND 0x0040 -#define CHIPC_PST_SBCLKST 0x0030 -#define CHIPC_PST_SBCLKST_ILP 0x0010 -#define CHIPC_PST_SBCLKST_ALP 0x0020 -#define CHIPC_PST_SBCLKST_HT 0x0030 -#define CHIPC_PST_ALPAVAIL 0x0008 -#define CHIPC_PST_HTAVAIL 0x0004 -#define CHIPC_PST_RESINIT 0x0003 - -/* pmucapabilities */ -#define CHIPC_PCAP_REV_MASK 0x000000ff -#define CHIPC_PCAP_RC_MASK 0x00001f00 -#define CHIPC_PCAP_RC_SHIFT 8 -#define CHIPC_PCAP_TC_MASK 0x0001e000 -#define CHIPC_PCAP_TC_SHIFT 13 -#define CHIPC_PCAP_PC_MASK 0x001e0000 -#define CHIPC_PCAP_PC_SHIFT 17 -#define CHIPC_PCAP_VC_MASK 0x01e00000 -#define CHIPC_PCAP_VC_SHIFT 21 -#define CHIPC_PCAP_CC_MASK 0x1e000000 -#define CHIPC_PCAP_CC_SHIFT 25 -#define CHIPC_PCAP5_PC_MASK 0x003e0000 /* PMU corerev >= 5 */ -#define CHIPC_PCAP5_PC_SHIFT 17 -#define CHIPC_PCAP5_VC_MASK 0x07c00000 -#define CHIPC_PCAP5_VC_SHIFT 22 -#define CHIPC_PCAP5_CC_MASK 0xf8000000 -#define CHIPC_PCAP5_CC_SHIFT 27 - -/* PMU Resource Request Timer registers */ -/* This is based on PmuRev0 */ -#define CHIPC_PRRT_TIME_MASK 0x03ff -#define CHIPC_PRRT_INTEN 0x0400 -#define CHIPC_PRRT_REQ_ACTIVE 0x0800 -#define CHIPC_PRRT_ALP_REQ 0x1000 -#define CHIPC_PRRT_HT_REQ 0x2000 - -/* PMU resource bit position */ -#define CHIPC_PMURES_BIT(bit) (1 << (bit)) - -/* PMU resource number limit */ -#define CHIPC_PMURES_MAX_RESNUM 30 - -/* PMU chip control0 register */ -#define CHIPC_PMU_CHIPCTL0 0 - -/* PMU chip control1 register */ -#define CHIPC_PMU_CHIPCTL1 1 -#define CHIPC_PMU_CC1_RXC_DLL_BYPASS 0x00010000 - -#define CHIPC_PMU_CC1_IF_TYPE_MASK 0x00000030 -#define CHIPC_PMU_CC1_IF_TYPE_RMII 0x00000000 -#define CHIPC_PMU_CC1_IF_TYPE_MII 0x00000010 -#define CHIPC_PMU_CC1_IF_TYPE_RGMII 0x00000020 - -#define CHIPC_PMU_CC1_SW_TYPE_MASK 0x000000c0 -#define CHIPC_PMU_CC1_SW_TYPE_EPHY 0x00000000 -#define CHIPC_PMU_CC1_SW_TYPE_EPHYMII 0x00000040 -#define CHIPC_PMU_CC1_SW_TYPE_EPHYRMII 0x00000080 -#define CHIPC_PMU_CC1_SW_TYPE_RGMII 0x000000c0 - -/* PMU corerev and chip specific PLL controls. - * PMU_PLL_XX where is PMU corerev and is an arbitrary number - * to differentiate different PLLs controlled by the same PMU rev. - */ -/* pllcontrol registers */ -/* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */ -#define CHIPC_PMU0_PLL0_PLLCTL0 0 -#define CHIPC_PMU0_PLL0_PC0_PDIV_MASK 1 -#define CHIPC_PMU0_PLL0_PC0_PDIV_FREQ 25000 -#define CHIPC_PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038 -#define CHIPC_PMU0_PLL0_PC0_DIV_ARM_SHIFT 3 -#define CHIPC_PMU0_PLL0_PC0_DIV_ARM_BASE 8 - -/* PC0_DIV_ARM for PLLOUT_ARM */ -#define CHIPC_PMU0_PLL0_PC0_DIV_ARM_110MHZ 0 -#define CHIPC_PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1 -#define CHIPC_PMU0_PLL0_PC0_DIV_ARM_88MHZ 2 -#define CHIPC_PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */ -#define CHIPC_PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4 -#define CHIPC_PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5 -#define CHIPC_PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6 -#define CHIPC_PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7 - -/* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */ -#define CHIPC_PMU0_PLL0_PLLCTL1 1 -#define CHIPC_PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000 -#define CHIPC_PMU0_PLL0_PC1_WILD_INT_SHIFT 28 -#define CHIPC_PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00 -#define CHIPC_PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8 -#define CHIPC_PMU0_PLL0_PC1_STOP_MOD 0x00000040 - -/* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */ -#define CHIPC_PMU0_PLL0_PLLCTL2 2 -#define CHIPC_PMU0_PLL0_PC2_WILD_INT_MASK 0xf -#define CHIPC_PMU0_PLL0_PC2_WILD_INT_SHIFT 4 - -/* pllcontrol registers */ -/* ndiv_pwrdn, pwrdn_ch, refcomp_pwrdn, dly_ch, p1div, p2div, _bypass_sdmod */ -#define CHIPC_PMU1_PLL0_PLLCTL0 0 -#define CHIPC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 -#define CHIPC_PMU1_PLL0_PC0_P1DIV_SHIFT 20 -#define CHIPC_PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000 -#define CHIPC_PMU1_PLL0_PC0_P2DIV_SHIFT 24 - -/* mdiv */ -#define CHIPC_PMU1_PLL0_PLLCTL1 1 -#define CHIPC_PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff -#define CHIPC_PMU1_PLL0_PC1_M1DIV_SHIFT 0 -#define CHIPC_PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00 -#define CHIPC_PMU1_PLL0_PC1_M2DIV_SHIFT 8 -#define CHIPC_PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000 -#define CHIPC_PMU1_PLL0_PC1_M3DIV_SHIFT 16 -#define CHIPC_PMU1_PLL0_PC1_M4DIV_MASK 0xff000000 -#define CHIPC_PMU1_PLL0_PC1_M4DIV_SHIFT 24 - -#define CHIPC_DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8 -#define CHIPC_DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) -#define CHIPC_DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) - -/* mdiv, ndiv_dither_mfb, ndiv_mode, ndiv_int */ -#define CHIPC_PMU1_PLL0_PLLCTL2 2 -#define CHIPC_PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff -#define CHIPC_PMU1_PLL0_PC2_M5DIV_SHIFT 0 -#define CHIPC_PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00 -#define CHIPC_PMU1_PLL0_PC2_M6DIV_SHIFT 8 -#define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000 -#define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17 -#define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_MASH 1 -#define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_MFB 2 /* recommended for 4319 */ -#define CHIPC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 -#define CHIPC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 - -/* ndiv_frac */ -#define CHIPC_PMU1_PLL0_PLLCTL3 3 -#define CHIPC_PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff -#define CHIPC_PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0 - -/* pll_ctrl */ -#define CHIPC_PMU1_PLL0_PLLCTL4 4 - -/* pll_ctrl, vco_rng, clkdrive_ch */ -#define CHIPC_PMU1_PLL0_PLLCTL5 5 -#define CHIPC_PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00 -#define CHIPC_PMU1_PLL0_PC5_CLK_DRV_SHIFT 8 - -/* PMU rev 2 control words */ -#define CHIPC_PMU2_PHY_PLL_PLLCTL 4 -#define CHIPC_PMU2_SI_PLL_PLLCTL 10 - -/* PMU rev 2 */ -/* pllcontrol registers */ -/* ndiv_pwrdn, pwrdn_ch, refcomp_pwrdn, dly_ch, p1div, p2div, _bypass_sdmod */ -#define CHIPC_PMU2_PLL_PLLCTL0 0 -#define CHIPC_PMU2_PLL_PC0_P1DIV_MASK 0x00f00000 -#define CHIPC_PMU2_PLL_PC0_P1DIV_SHIFT 20 -#define CHIPC_PMU2_PLL_PC0_P2DIV_MASK 0x0f000000 -#define CHIPC_PMU2_PLL_PC0_P2DIV_SHIFT 24 - -/* mdiv */ -#define CHIPC_PMU2_PLL_PLLCTL1 1 -#define CHIPC_PMU2_PLL_PC1_M1DIV_MASK 0x000000ff -#define CHIPC_PMU2_PLL_PC1_M1DIV_SHIFT 0 -#define CHIPC_PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00 -#define CHIPC_PMU2_PLL_PC1_M2DIV_SHIFT 8 -#define CHIPC_PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000 -#define CHIPC_PMU2_PLL_PC1_M3DIV_SHIFT 16 -#define CHIPC_PMU2_PLL_PC1_M4DIV_MASK 0xff000000 -#define CHIPC_PMU2_PLL_PC1_M4DIV_SHIFT 24 - -/* mdiv, ndiv_dither_mfb, ndiv_mode, ndiv_int */ -#define CHIPC_PMU2_PLL_PLLCTL2 2 -#define CHIPC_PMU2_PLL_PC2_M5DIV_MASK 0x000000ff -#define CHIPC_PMU2_PLL_PC2_M5DIV_SHIFT 0 -#define CHIPC_PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00 -#define CHIPC_PMU2_PLL_PC2_M6DIV_SHIFT 8 -#define CHIPC_PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000 -#define CHIPC_PMU2_PLL_PC2_NDIV_MODE_SHIFT 17 -#define CHIPC_PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000 -#define CHIPC_PMU2_PLL_PC2_NDIV_INT_SHIFT 20 - -/* ndiv_frac */ -#define CHIPC_PMU2_PLL_PLLCTL3 3 -#define CHIPC_PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff -#define CHIPC_PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0 - -/* pll_ctrl */ -#define CHIPC_PMU2_PLL_PLLCTL4 4 - -/* pll_ctrl, vco_rng, clkdrive_ch */ -#define CHIPC_PMU2_PLL_PLLCTL5 5 -#define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00 -#define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8 -#define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000 -#define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12 -#define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000 -#define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16 -#define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000 -#define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20 -#define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000 -#define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24 -#define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000 -#define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28 - -/* PMU rev 5 (& 6) */ -#define CHIPC_PMU5_PLL_P1P2_OFF 0 -#define CHIPC_PMU5_PLL_P1_MASK 0x0f000000 -#define CHIPC_PMU5_PLL_P1_SHIFT 24 -#define CHIPC_PMU5_PLL_P2_MASK 0x00f00000 -#define CHIPC_PMU5_PLL_P2_SHIFT 20 -#define CHIPC_PMU5_PLL_M14_OFF 1 -#define CHIPC_PMU5_PLL_MDIV_MASK 0x000000ff -#define CHIPC_PMU5_PLL_MDIV_WIDTH 8 -#define CHIPC_PMU5_PLL_NM5_OFF 2 -#define CHIPC_PMU5_PLL_NDIV_MASK 0xfff00000 -#define CHIPC_PMU5_PLL_NDIV_SHIFT 20 -#define CHIPC_PMU5_PLL_NDIV_MODE_MASK 0x000e0000 -#define CHIPC_PMU5_PLL_NDIV_MODE_SHIFT 17 -#define CHIPC_PMU5_PLL_FMAB_OFF 3 -#define CHIPC_PMU5_PLL_MRAT_MASK 0xf0000000 -#define CHIPC_PMU5_PLL_MRAT_SHIFT 28 -#define CHIPC_PMU5_PLL_ABRAT_MASK 0x08000000 -#define CHIPC_PMU5_PLL_ABRAT_SHIFT 27 -#define CHIPC_PMU5_PLL_FDIV_MASK 0x07ffffff -#define CHIPC_PMU5_PLL_PLLCTL_OFF 4 -#define CHIPC_PMU5_PLL_PCHI_OFF 5 -#define CHIPC_PMU5_PLL_PCHI_MASK 0x0000003f - -/* pmu XtalFreqRatio */ -#define CHIPC_PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF -#define CHIPC_PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000 -#define CHIPC_PMU_XTALFREQ_REG_MEASURE_SHIFT 31 - -/* Divider allocation in 4716/47162/5356/5357 */ -#define CHIPC_PMU5_MAINPLL_CPU 1 -#define CHIPC_PMU5_MAINPLL_MEM 2 -#define CHIPC_PMU5_MAINPLL_SI 3 - -#define CHIPC_PMU7_PLL_PLLCTL7 7 -#define CHIPC_PMU7_PLL_PLLCTL8 8 -#define CHIPC_PMU7_PLL_PLLCTL11 11 - -/* PLL usage in 4716/47162 */ -#define CHIPC_PMU4716_MAINPLL_PLL0 12 - -/* PLL usage in 5356/5357 */ -#define CHIPC_PMU5356_MAINPLL_PLL0 0 -#define CHIPC_PMU5357_MAINPLL_PLL0 0 - -/* 4716/47162 resources */ -#define CHIPC_RES4716_PROC_PLL_ON 0x00000040 -#define CHIPC_RES4716_PROC_HT_AVAIL 0x00000080 - -/* 4716/4717/4718 Chip specific ChipControl register bits */ -#define CHIPC_CCTRL471X_I2S_PINS_ENABLE 0x0080 /* I2S pins off by default, shared with pflash */ - -/* 5354 resources */ -#define CHIPC_RES5354_EXT_SWITCHER_PWM 0 /* 0x00001 */ -#define CHIPC_RES5354_BB_SWITCHER_PWM 1 /* 0x00002 */ -#define CHIPC_RES5354_BB_SWITCHER_BURST 2 /* 0x00004 */ -#define CHIPC_RES5354_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ -#define CHIPC_RES5354_ILP_REQUEST 4 /* 0x00010 */ -#define CHIPC_RES5354_RADIO_SWITCHER_PWM 5 /* 0x00020 */ -#define CHIPC_RES5354_RADIO_SWITCHER_BURST 6 /* 0x00040 */ -#define CHIPC_RES5354_ROM_SWITCH 7 /* 0x00080 */ -#define CHIPC_RES5354_PA_REF_LDO 8 /* 0x00100 */ -#define CHIPC_RES5354_RADIO_LDO 9 /* 0x00200 */ -#define CHIPC_RES5354_AFE_LDO 10 /* 0x00400 */ -#define CHIPC_RES5354_PLL_LDO 11 /* 0x00800 */ -#define CHIPC_RES5354_BG_FILTBYP 12 /* 0x01000 */ -#define CHIPC_RES5354_TX_FILTBYP 13 /* 0x02000 */ -#define CHIPC_RES5354_RX_FILTBYP 14 /* 0x04000 */ -#define CHIPC_RES5354_XTAL_PU 15 /* 0x08000 */ -#define CHIPC_RES5354_XTAL_EN 16 /* 0x10000 */ -#define CHIPC_RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */ -#define CHIPC_RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */ -#define CHIPC_RES5354_BB_PLL_PU 19 /* 0x80000 */ - -/* 5357 Chip specific ChipControl register bits */ -#define CHIPC_CCTRL5357_EXTPA (1<<14) /* extPA in ChipControl 1, bit 14 */ -#define CHIPC_CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in ChipControl 1, bit 15 */ - -/* 4328 resources */ -#define CHIPC_RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */ -#define CHIPC_RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */ -#define CHIPC_RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */ -#define CHIPC_RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ -#define CHIPC_RES4328_ILP_REQUEST 4 /* 0x00010 */ -#define CHIPC_RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */ -#define CHIPC_RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */ -#define CHIPC_RES4328_ROM_SWITCH 7 /* 0x00080 */ -#define CHIPC_RES4328_PA_REF_LDO 8 /* 0x00100 */ -#define CHIPC_RES4328_RADIO_LDO 9 /* 0x00200 */ -#define CHIPC_RES4328_AFE_LDO 10 /* 0x00400 */ -#define CHIPC_RES4328_PLL_LDO 11 /* 0x00800 */ -#define CHIPC_RES4328_BG_FILTBYP 12 /* 0x01000 */ -#define CHIPC_RES4328_TX_FILTBYP 13 /* 0x02000 */ -#define CHIPC_RES4328_RX_FILTBYP 14 /* 0x04000 */ -#define CHIPC_RES4328_XTAL_PU 15 /* 0x08000 */ -#define CHIPC_RES4328_XTAL_EN 16 /* 0x10000 */ -#define CHIPC_RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */ -#define CHIPC_RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */ -#define CHIPC_RES4328_BB_PLL_PU 19 /* 0x80000 */ - -/* 4325 A0/A1 resources */ -#define CHIPC_RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */ -#define CHIPC_RES4325_CBUCK_BURST 1 /* 0x00000002 */ -#define CHIPC_RES4325_CBUCK_PWM 2 /* 0x00000004 */ -#define CHIPC_RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */ -#define CHIPC_RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */ -#define CHIPC_RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */ -#define CHIPC_RES4325_ILP_REQUEST 6 /* 0x00000040 */ -#define CHIPC_RES4325_ABUCK_BURST 7 /* 0x00000080 */ -#define CHIPC_RES4325_ABUCK_PWM 8 /* 0x00000100 */ -#define CHIPC_RES4325_LNLDO1_PU 9 /* 0x00000200 */ -#define CHIPC_RES4325_OTP_PU 10 /* 0x00000400 */ -#define CHIPC_RES4325_LNLDO3_PU 11 /* 0x00000800 */ -#define CHIPC_RES4325_LNLDO4_PU 12 /* 0x00001000 */ -#define CHIPC_RES4325_XTAL_PU 13 /* 0x00002000 */ -#define CHIPC_RES4325_ALP_AVAIL 14 /* 0x00004000 */ -#define CHIPC_RES4325_RX_PWRSW_PU 15 /* 0x00008000 */ -#define CHIPC_RES4325_TX_PWRSW_PU 16 /* 0x00010000 */ -#define CHIPC_RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */ -#define CHIPC_RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */ -#define CHIPC_RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */ -#define CHIPC_RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */ -#define CHIPC_RES4325_HT_AVAIL 21 /* 0x00200000 */ - -/* 4325 B0/C0 resources */ -#define CHIPC_RES4325B0_CBUCK_LPOM 1 /* 0x00000002 */ -#define CHIPC_RES4325B0_CBUCK_BURST 2 /* 0x00000004 */ -#define CHIPC_RES4325B0_CBUCK_PWM 3 /* 0x00000008 */ -#define CHIPC_RES4325B0_CLDO_PU 4 /* 0x00000010 */ - -/* 4325 C1 resources */ -#define CHIPC_RES4325C1_LNLDO2_PU 12 /* 0x00001000 */ - /* 4325 chip-specific ChipStatus register bits */ #define CHIPC_CST4325_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK #define CHIPC_CST4325_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT #define CHIPC_CST4325_SDIO_USB_MODE_MASK 0x00000004 #define CHIPC_CST4325_SDIO_USB_MODE_SHIFT 2 #define CHIPC_CST4325_RCAL_VALID_MASK 0x00000008 #define CHIPC_CST4325_RCAL_VALID_SHIFT 3 #define CHIPC_CST4325_RCAL_VALUE_MASK 0x000001f0 #define CHIPC_CST4325_RCAL_VALUE_SHIFT 4 #define CHIPC_CST4325_PMUTOP_2B_MASK 0x00000200 /* 1 for 2b, 0 for to 2a */ #define CHIPC_CST4325_PMUTOP_2B_SHIFT 9 -#define CHIPC_RES4329_RESERVED0 0 /* 0x00000001 */ -#define CHIPC_RES4329_CBUCK_LPOM 1 /* 0x00000002 */ -#define CHIPC_RES4329_CBUCK_BURST 2 /* 0x00000004 */ -#define CHIPC_RES4329_CBUCK_PWM 3 /* 0x00000008 */ -#define CHIPC_RES4329_CLDO_PU 4 /* 0x00000010 */ -#define CHIPC_RES4329_PALDO_PU 5 /* 0x00000020 */ -#define CHIPC_RES4329_ILP_REQUEST 6 /* 0x00000040 */ -#define CHIPC_RES4329_RESERVED7 7 /* 0x00000080 */ -#define CHIPC_RES4329_RESERVED8 8 /* 0x00000100 */ -#define CHIPC_RES4329_LNLDO1_PU 9 /* 0x00000200 */ -#define CHIPC_RES4329_OTP_PU 10 /* 0x00000400 */ -#define CHIPC_RES4329_RESERVED11 11 /* 0x00000800 */ -#define CHIPC_RES4329_LNLDO2_PU 12 /* 0x00001000 */ -#define CHIPC_RES4329_XTAL_PU 13 /* 0x00002000 */ -#define CHIPC_RES4329_ALP_AVAIL 14 /* 0x00004000 */ -#define CHIPC_RES4329_RX_PWRSW_PU 15 /* 0x00008000 */ -#define CHIPC_RES4329_TX_PWRSW_PU 16 /* 0x00010000 */ -#define CHIPC_RES4329_RFPLL_PWRSW_PU 17 /* 0x00020000 */ -#define CHIPC_RES4329_LOGEN_PWRSW_PU 18 /* 0x00040000 */ -#define CHIPC_RES4329_AFE_PWRSW_PU 19 /* 0x00080000 */ -#define CHIPC_RES4329_BBPLL_PWRSW_PU 20 /* 0x00100000 */ -#define CHIPC_RES4329_HT_AVAIL 21 /* 0x00200000 */ - /* 4329 chip-specific ChipStatus register bits */ #define CHIPC_CST4329_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK #define CHIPC_CST4329_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT #define CHIPC_CST4329_SPI_SDIO_MODE_MASK 0x00000004 #define CHIPC_CST4329_SPI_SDIO_MODE_SHIFT 2 /* 4312 chip-specific ChipStatus register bits */ #define CHIPC_CST4312_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK #define CHIPC_CST4312_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT -/* 4312 resources (all PMU chips with little memory constraint) */ -#define CHIPC_RES4312_SWITCHER_BURST 0 /* 0x00000001 */ -#define CHIPC_RES4312_SWITCHER_PWM 1 /* 0x00000002 */ -#define CHIPC_RES4312_PA_REF_LDO 2 /* 0x00000004 */ -#define CHIPC_RES4312_CORE_LDO_BURST 3 /* 0x00000008 */ -#define CHIPC_RES4312_CORE_LDO_PWM 4 /* 0x00000010 */ -#define CHIPC_RES4312_RADIO_LDO 5 /* 0x00000020 */ -#define CHIPC_RES4312_ILP_REQUEST 6 /* 0x00000040 */ -#define CHIPC_RES4312_BG_FILTBYP 7 /* 0x00000080 */ -#define CHIPC_RES4312_TX_FILTBYP 8 /* 0x00000100 */ -#define CHIPC_RES4312_RX_FILTBYP 9 /* 0x00000200 */ -#define CHIPC_RES4312_XTAL_PU 10 /* 0x00000400 */ -#define CHIPC_RES4312_ALP_AVAIL 11 /* 0x00000800 */ -#define CHIPC_RES4312_BB_PLL_FILTBYP 12 /* 0x00001000 */ -#define CHIPC_RES4312_RF_PLL_FILTBYP 13 /* 0x00002000 */ -#define CHIPC_RES4312_HT_AVAIL 14 /* 0x00004000 */ -/* 4322 resources */ -#define CHIPC_RES4322_RF_LDO 0 -#define CHIPC_RES4322_ILP_REQUEST 1 -#define CHIPC_RES4322_XTAL_PU 2 -#define CHIPC_RES4322_ALP_AVAIL 3 -#define CHIPC_RES4322_SI_PLL_ON 4 -#define CHIPC_RES4322_HT_SI_AVAIL 5 -#define CHIPC_RES4322_PHY_PLL_ON 6 -#define CHIPC_RES4322_HT_PHY_AVAIL 7 -#define CHIPC_RES4322_OTP_PU 8 - /* 4322 chip-specific ChipStatus register bits */ #define CHIPC_CST4322_XTAL_FREQ_20_40MHZ 0x00000020 #define CHIPC_CST4322_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R23_MASK #define CHIPC_CST4322_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT #define CHIPC_CST4322_PCI_OR_USB 0x00000100 #define CHIPC_CST4322_BOOT_MASK 0x00000600 #define CHIPC_CST4322_BOOT_SHIFT 9 #define CHIPC_CST4322_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ #define CHIPC_CST4322_BOOT_FROM_ROM 1 /* boot from ROM */ #define CHIPC_CST4322_BOOT_FROM_FLASH 2 /* boot from FLASH */ #define CHIPC_CST4322_BOOT_FROM_INVALID 3 #define CHIPC_CST4322_ILP_DIV_EN 0x00000800 #define CHIPC_CST4322_FLASH_TYPE_MASK 0x00001000 #define CHIPC_CST4322_FLASH_TYPE_SHIFT 12 #define CHIPC_CST4322_FLASH_TYPE_SHIFT_ST 0 /* ST serial FLASH */ #define CHIPC_CST4322_FLASH_TYPE_SHIFT_ATMEL 1 /* ATMEL flash */ #define CHIPC_CST4322_ARM_TAP_SEL 0x00002000 #define CHIPC_CST4322_RES_INIT_MODE_MASK 0x0000c000 #define CHIPC_CST4322_RES_INIT_MODE_SHIFT 14 #define CHIPC_CST4322_RES_INIT_MODE_ILPAVAIL 0 /* resinitmode: ILP available */ #define CHIPC_CST4322_RES_INIT_MODE_ILPREQ 1 /* resinitmode: ILP request */ #define CHIPC_CST4322_RES_INIT_MODE_ALPAVAIL 2 /* resinitmode: ALP available */ #define CHIPC_CST4322_RES_INIT_MODE_HTAVAIL 3 /* resinitmode: HT available */ #define CHIPC_CST4322_PCIPLLCLK_GATING 0x00010000 #define CHIPC_CST4322_CLK_SWITCH_PCI_TO_ALP 0x00020000 #define CHIPC_CST4322_PCI_CARDBUS_MODE 0x00040000 -/* 43224 chip-specific ChipControl register bits */ -#define CHIPC_CCTRL43224_GPIO_TOGGLE 0x8000 -#define CHIPC_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */ -#define CHIPC_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */ - -/* 43236 resources */ -#define CHIPC_RES43236_REGULATOR 0 -#define CHIPC_RES43236_ILP_REQUEST 1 -#define CHIPC_RES43236_XTAL_PU 2 -#define CHIPC_RES43236_ALP_AVAIL 3 -#define CHIPC_RES43236_SI_PLL_ON 4 -#define CHIPC_RES43236_HT_SI_AVAIL 5 - -/* 43236 chip-specific ChipControl register bits */ -#define CHIPC_CCTRL43236_BT_COEXIST (1<<0) /* 0 disable */ -#define CHIPC_CCTRL43236_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ -#define CHIPC_CCTRL43236_EXT_LNA (1<<2) /* 0 disable */ -#define CHIPC_CCTRL43236_ANT_MUX_2o3 (1<<3) /* 2o3 mux, chipcontrol bit 3 */ -#define CHIPC_CCTRL43236_GSIO (1<<4) /* 0 disable */ - /* 43236 Chip specific ChipStatus register bits */ #define CHIPC_CST43236_SFLASH_MASK 0x00000040 #define CHIPC_CST43236_OTP_SEL_MASK 0x00000080 #define CHIPC_CST43236_OTP_SEL_SHIFT 7 #define CHIPC_CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */ #define CHIPC_CST43236_BP_CLK 0x00000200 /* 120/96Mbps */ #define CHIPC_CST43236_BOOT_MASK 0x00001800 #define CHIPC_CST43236_BOOT_SHIFT 11 #define CHIPC_CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ #define CHIPC_CST43236_BOOT_FROM_ROM 1 /* boot from ROM */ #define CHIPC_CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */ #define CHIPC_CST43236_BOOT_FROM_INVALID 3 -/* 4331 resources */ -#define CHIPC_RES4331_REGULATOR 0 -#define CHIPC_RES4331_ILP_REQUEST 1 -#define CHIPC_RES4331_XTAL_PU 2 -#define CHIPC_RES4331_ALP_AVAIL 3 -#define CHIPC_RES4331_SI_PLL_ON 4 -#define CHIPC_RES4331_HT_SI_AVAIL 5 +/* 43237 Chip specific ChipStatus register bits */ +#define CHIPC_CST43237_BP_CLK 0x00000200 /* 96/80Mbps */ -/* 4331 chip-specific ChipControl register bits */ +/* 4331 Chip specific ChipStatus register bits */ +#define CHIPC_CST4331_XTAL_FREQ 0x00000001 /* crystal frequency 20/40Mhz */ +#define CHIPC_CST4331_SPROM_PRESENT 0x00000002 +#define CHIPC_CST4331_OTP_PRESENT 0x00000004 +#define CHIPC_CST4331_LDO_RF 0x00000008 +#define CHIPC_CST4331_LDO_PAR 0x00000010 + +/* 4331 chip-specific CHIPCTRL register bits */ #define CHIPC_CCTRL4331_BT_COEXIST (1<<0) /* 0 disable */ #define CHIPC_CCTRL4331_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ #define CHIPC_CCTRL4331_EXT_LNA (1<<2) /* 0 disable */ #define CHIPC_CCTRL4331_SPROM_GPIO13_15 (1<<3) /* sprom/gpio13-15 mux */ #define CHIPC_CCTRL4331_EXTPA_EN (1<<4) /* 0 ext pa disable, 1 ext pa enabled */ #define CHIPC_CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5) /* set drive out GPIO_CLK on sprom_cs pin */ #define CHIPC_CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6) /* use sprom_cs pin as PCIE mdio interface */ #define CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7) /* aband extpa will be at gpio2/5 and sprom_dout */ #define CHIPC_CCTRL4331_OVR_PIPEAUXCLKEN (1<<8) /* override core control on pipe_AuxClkEnable */ #define CHIPC_CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9) /* override core control on pipe_AuxPowerDown */ #define CHIPC_CCTRL4331_PCIE_AUXCLKEN (1<<10) /* pcie_auxclkenable */ #define CHIPC_CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11) /* pcie_pipe_pllpowerdown */ #define CHIPC_CCTRL4331_EXTPA_EN2 (1<<12) /* 0 ext pa2 disable, 1 ext pa2 enabled */ #define CHIPC_CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16) /* enable bt_shd0 at gpio4 */ #define CHIPC_CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17) /* enable bt_shd1 at gpio5 */ -/* 4331 Chip specific ChipStatus register bits */ -#define CHIPC_CST4331_XTAL_FREQ 0x00000001 /* crystal frequency 20/40Mhz */ -#define CHIPC_CST4331_SPROM_PRESENT 0x00000002 -#define CHIPC_CST4331_OTP_PRESENT 0x00000004 -#define CHIPC_CST4331_LDO_RF 0x00000008 -#define CHIPC_CST4331_LDO_PAR 0x00000010 - -/* 4315 resources */ -#define CHIPC_RES4315_CBUCK_LPOM 1 /* 0x00000002 */ -#define CHIPC_RES4315_CBUCK_BURST 2 /* 0x00000004 */ -#define CHIPC_RES4315_CBUCK_PWM 3 /* 0x00000008 */ -#define CHIPC_RES4315_CLDO_PU 4 /* 0x00000010 */ -#define CHIPC_RES4315_PALDO_PU 5 /* 0x00000020 */ -#define CHIPC_RES4315_ILP_REQUEST 6 /* 0x00000040 */ -#define CHIPC_RES4315_LNLDO1_PU 9 /* 0x00000200 */ -#define CHIPC_RES4315_OTP_PU 10 /* 0x00000400 */ -#define CHIPC_RES4315_LNLDO2_PU 12 /* 0x00001000 */ -#define CHIPC_RES4315_XTAL_PU 13 /* 0x00002000 */ -#define CHIPC_RES4315_ALP_AVAIL 14 /* 0x00004000 */ -#define CHIPC_RES4315_RX_PWRSW_PU 15 /* 0x00008000 */ -#define CHIPC_RES4315_TX_PWRSW_PU 16 /* 0x00010000 */ -#define CHIPC_RES4315_RFPLL_PWRSW_PU 17 /* 0x00020000 */ -#define CHIPC_RES4315_LOGEN_PWRSW_PU 18 /* 0x00040000 */ -#define CHIPC_RES4315_AFE_PWRSW_PU 19 /* 0x00080000 */ -#define CHIPC_RES4315_BBPLL_PWRSW_PU 20 /* 0x00100000 */ -#define CHIPC_RES4315_HT_AVAIL 21 /* 0x00200000 */ - /* 4315 chip-specific ChipStatus register bits */ #define CHIPC_CST4315_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK #define CHIPC_CST4315_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT #define CHIPC_CST4315_SDIO_MODE 0x00000004 /* gpio [8], sdio/usb mode */ #define CHIPC_CST4315_RCAL_VALID 0x00000008 #define CHIPC_CST4315_RCAL_VALUE_MASK 0x000001f0 #define CHIPC_CST4315_RCAL_VALUE_SHIFT 4 #define CHIPC_CST4315_PALDO_EXTPNP 0x00000200 /* PALDO is configured with external PNP */ #define CHIPC_CST4315_CBUCK_MODE_MASK 0x00000c00 #define CHIPC_CST4315_CBUCK_MODE_BURST 0x00000400 #define CHIPC_CST4315_CBUCK_MODE_LPBURST 0x00000c00 -/* 4319 resources */ -#define CHIPC_RES4319_CBUCK_LPOM 1 /* 0x00000002 */ -#define CHIPC_RES4319_CBUCK_BURST 2 /* 0x00000004 */ -#define CHIPC_RES4319_CBUCK_PWM 3 /* 0x00000008 */ -#define CHIPC_RES4319_CLDO_PU 4 /* 0x00000010 */ -#define CHIPC_RES4319_PALDO_PU 5 /* 0x00000020 */ -#define CHIPC_RES4319_ILP_REQUEST 6 /* 0x00000040 */ -#define CHIPC_RES4319_LNLDO1_PU 9 /* 0x00000200 */ -#define CHIPC_RES4319_OTP_PU 10 /* 0x00000400 */ -#define CHIPC_RES4319_LNLDO2_PU 12 /* 0x00001000 */ -#define CHIPC_RES4319_XTAL_PU 13 /* 0x00002000 */ -#define CHIPC_RES4319_ALP_AVAIL 14 /* 0x00004000 */ -#define CHIPC_RES4319_RX_PWRSW_PU 15 /* 0x00008000 */ -#define CHIPC_RES4319_TX_PWRSW_PU 16 /* 0x00010000 */ -#define CHIPC_RES4319_RFPLL_PWRSW_PU 17 /* 0x00020000 */ -#define CHIPC_RES4319_LOGEN_PWRSW_PU 18 /* 0x00040000 */ -#define CHIPC_RES4319_AFE_PWRSW_PU 19 /* 0x00080000 */ -#define CHIPC_RES4319_BBPLL_PWRSW_PU 20 /* 0x00100000 */ -#define CHIPC_RES4319_HT_AVAIL 21 /* 0x00200000 */ - /* 4319 chip-specific ChipStatus register bits */ #define CHIPC_CST4319_SPI_CPULESSUSB 0x00000001 #define CHIPC_CST4319_SPI_CLK_POL 0x00000002 #define CHIPC_CST4319_SPI_CLK_PH 0x00000008 #define CHIPC_CST4319_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R23_MASK /* gpio [7:6], SDIO CIS selection */ #define CHIPC_CST4319_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT #define CHIPC_CST4319_SDIO_USB_MODE 0x00000100 /* gpio [8], sdio/usb mode */ #define CHIPC_CST4319_REMAP_SEL_MASK 0x00000600 #define CHIPC_CST4319_ILPDIV_EN 0x00000800 #define CHIPC_CST4319_XTAL_PD_POL 0x00001000 #define CHIPC_CST4319_LPO_SEL 0x00002000 #define CHIPC_CST4319_RES_INIT_MODE 0x0000c000 #define CHIPC_CST4319_PALDO_EXTPNP 0x00010000 /* PALDO is configured with external PNP */ #define CHIPC_CST4319_CBUCK_MODE_MASK 0x00060000 #define CHIPC_CST4319_CBUCK_MODE_BURST 0x00020000 #define CHIPC_CST4319_CBUCK_MODE_LPBURST 0x00060000 #define CHIPC_CST4319_RCAL_VALID 0x01000000 #define CHIPC_CST4319_RCAL_VALUE_MASK 0x3e000000 #define CHIPC_CST4319_RCAL_VALUE_SHIFT 25 -#define CHIPC_PMU1_PLL0_CHIPCTL0 0 -#define CHIPC_PMU1_PLL0_CHIPCTL1 1 -#define CHIPC_PMU1_PLL0_CHIPCTL2 2 -#define CHIPC_CCTL_4319USB_XTAL_SEL_MASK 0x00180000 -#define CHIPC_CCTL_4319USB_XTAL_SEL_SHIFT 19 -#define CHIPC_CCTL_4319USB_48MHZ_PLL_SEL 1 -#define CHIPC_CCTL_4319USB_24MHZ_PLL_SEL 2 - -/* PMU resources for 4336 */ -#define CHIPC_RES4336_CBUCK_LPOM 0 -#define CHIPC_RES4336_CBUCK_BURST 1 -#define CHIPC_RES4336_CBUCK_LP_PWM 2 -#define CHIPC_RES4336_CBUCK_PWM 3 -#define CHIPC_RES4336_CLDO_PU 4 -#define CHIPC_RES4336_DIS_INT_RESET_PD 5 -#define CHIPC_RES4336_ILP_REQUEST 6 -#define CHIPC_RES4336_LNLDO_PU 7 -#define CHIPC_RES4336_LDO3P3_PU 8 -#define CHIPC_RES4336_OTP_PU 9 -#define CHIPC_RES4336_XTAL_PU 10 -#define CHIPC_RES4336_ALP_AVAIL 11 -#define CHIPC_RES4336_RADIO_PU 12 -#define CHIPC_RES4336_BG_PU 13 -#define CHIPC_RES4336_VREG1p4_PU_PU 14 -#define CHIPC_RES4336_AFE_PWRSW_PU 15 -#define CHIPC_RES4336_RX_PWRSW_PU 16 -#define CHIPC_RES4336_TX_PWRSW_PU 17 -#define CHIPC_RES4336_BB_PWRSW_PU 18 -#define CHIPC_RES4336_SYNTH_PWRSW_PU 19 -#define CHIPC_RES4336_MISC_PWRSW_PU 20 -#define CHIPC_RES4336_LOGEN_PWRSW_PU 21 -#define CHIPC_RES4336_BBPLL_PWRSW_PU 22 -#define CHIPC_RES4336_MACPHY_CLKAVAIL 23 -#define CHIPC_RES4336_HT_AVAIL 24 -#define CHIPC_RES4336_RSVD 25 - /* 4336 chip-specific ChipStatus register bits */ #define CHIPC_CST4336_SPI_MODE_MASK 0x00000001 #define CHIPC_CST4336_SPROM_PRESENT 0x00000002 #define CHIPC_CST4336_OTP_PRESENT 0x00000004 #define CHIPC_CST4336_ARMREMAP_0 0x00000008 #define CHIPC_CST4336_ILPDIV_EN_MASK 0x00000010 #define CHIPC_CST4336_ILPDIV_EN_SHIFT 4 #define CHIPC_CST4336_XTAL_PD_POL_MASK 0x00000020 #define CHIPC_CST4336_XTAL_PD_POL_SHIFT 5 #define CHIPC_CST4336_LPO_SEL_MASK 0x00000040 #define CHIPC_CST4336_LPO_SEL_SHIFT 6 #define CHIPC_CST4336_RES_INIT_MODE_MASK 0x00000180 #define CHIPC_CST4336_RES_INIT_MODE_SHIFT 7 #define CHIPC_CST4336_CBUCK_MODE_MASK 0x00000600 #define CHIPC_CST4336_CBUCK_MODE_SHIFT 9 -/* 4330 resources */ -#define CHIPC_RES4330_CBUCK_LPOM 0 -#define CHIPC_RES4330_CBUCK_BURST 1 -#define CHIPC_RES4330_CBUCK_LP_PWM 2 -#define CHIPC_RES4330_CBUCK_PWM 3 -#define CHIPC_RES4330_CLDO_PU 4 -#define CHIPC_RES4330_DIS_INT_RESET_PD 5 -#define CHIPC_RES4330_ILP_REQUEST 6 -#define CHIPC_RES4330_LNLDO_PU 7 -#define CHIPC_RES4330_LDO3P3_PU 8 -#define CHIPC_RES4330_OTP_PU 9 -#define CHIPC_RES4330_XTAL_PU 10 -#define CHIPC_RES4330_ALP_AVAIL 11 -#define CHIPC_RES4330_RADIO_PU 12 -#define CHIPC_RES4330_BG_PU 13 -#define CHIPC_RES4330_VREG1p4_PU_PU 14 -#define CHIPC_RES4330_AFE_PWRSW_PU 15 -#define CHIPC_RES4330_RX_PWRSW_PU 16 -#define CHIPC_RES4330_TX_PWRSW_PU 17 -#define CHIPC_RES4330_BB_PWRSW_PU 18 -#define CHIPC_RES4330_SYNTH_PWRSW_PU 19 -#define CHIPC_RES4330_MISC_PWRSW_PU 20 -#define CHIPC_RES4330_LOGEN_PWRSW_PU 21 -#define CHIPC_RES4330_BBPLL_PWRSW_PU 22 -#define CHIPC_RES4330_MACPHY_CLKAVAIL 23 -#define CHIPC_RES4330_HT_AVAIL 24 -#define CHIPC_RES4330_5gRX_PWRSW_PU 25 -#define CHIPC_RES4330_5gTX_PWRSW_PU 26 -#define CHIPC_RES4330_5g_LOGEN_PWRSW_PU 27 - /* 4330 chip-specific ChipStatus register bits */ #define CHIPC_CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6) /* SDIO || gSPI */ #define CHIPC_CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6) /* USB || USBDA */ #define CHIPC_CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0) /* SDIO */ #define CHIPC_CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4) /* gSPI */ #define CHIPC_CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6) /* USB packet-oriented */ #define CHIPC_CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7) /* USB Direct Access */ #define CHIPC_CST4330_OTP_PRESENT 0x00000010 #define CHIPC_CST4330_LPO_AUTODET_EN 0x00000020 #define CHIPC_CST4330_ARMREMAP_0 0x00000040 #define CHIPC_CST4330_SPROM_PRESENT 0x00000080 /* takes priority over OTP if both set */ #define CHIPC_CST4330_ILPDIV_EN 0x00000100 #define CHIPC_CST4330_LPO_SEL 0x00000200 #define CHIPC_CST4330_RES_INIT_MODE_SHIFT 10 #define CHIPC_CST4330_RES_INIT_MODE_MASK 0x00000c00 #define CHIPC_CST4330_CBUCK_MODE_SHIFT 12 #define CHIPC_CST4330_CBUCK_MODE_MASK 0x00003000 #define CHIPC_CST4330_CBUCK_POWER_OK 0x00004000 #define CHIPC_CST4330_BB_PLL_LOCKED 0x00008000 #define CHIPC_SOCDEVRAM_4330_BP_ADDR 0x1E000000 #define CHIPC_SOCDEVRAM_4330_ARM_ADDR 0x00800000 -/* 4313 resources */ -#define CHIPC_RES4313_BB_PU_RSRC 0 -#define CHIPC_RES4313_ILP_REQ_RSRC 1 -#define CHIPC_RES4313_XTAL_PU_RSRC 2 -#define CHIPC_RES4313_ALP_AVAIL_RSRC 3 -#define CHIPC_RES4313_RADIO_PU_RSRC 4 -#define CHIPC_RES4313_BG_PU_RSRC 5 -#define CHIPC_RES4313_VREG1P4_PU_RSRC 6 -#define CHIPC_RES4313_AFE_PWRSW_RSRC 7 -#define CHIPC_RES4313_RX_PWRSW_RSRC 8 -#define CHIPC_RES4313_TX_PWRSW_RSRC 9 -#define CHIPC_RES4313_BB_PWRSW_RSRC 10 -#define CHIPC_RES4313_SYNTH_PWRSW_RSRC 11 -#define CHIPC_RES4313_MISC_PWRSW_RSRC 12 -#define CHIPC_RES4313_BB_PLL_PWRSW_RSRC 13 -#define CHIPC_RES4313_HT_AVAIL_RSRC 14 -#define CHIPC_RES4313_MACPHY_CLK_AVAIL_RSRC 15 - /* 4313 chip-specific ChipStatus register bits */ #define CHIPC_CST4313_SPROM_PRESENT 1 #define CHIPC_CST4313_OTP_PRESENT 2 #define CHIPC_CST4313_SPROM_OTP_SEL_MASK 0x00000002 #define CHIPC_CST4313_SPROM_OTP_SEL_SHIFT 0 -/* 4313 Chip specific ChipControl register bits */ -#define CHIPC_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ - -/* 43228 resources */ -#define CHIPC_RES43228_NOT_USED 0 -#define CHIPC_RES43228_ILP_REQUEST 1 -#define CHIPC_RES43228_XTAL_PU 2 -#define CHIPC_RES43228_ALP_AVAIL 3 -#define CHIPC_RES43228_PLL_EN 4 -#define CHIPC_RES43228_HT_PHY_AVAIL 5 - /* 43228 chipstatus reg bits */ #define CHIPC_CST43228_ILP_DIV_EN 0x1 #define CHIPC_CST43228_OTP_PRESENT 0x2 #define CHIPC_CST43228_SERDES_REFCLK_PADSEL 0x4 #define CHIPC_CST43228_SDIO_MODE 0x8 #define CHIPC_CST43228_SDIO_OTP_PRESENT 0x10 #define CHIPC_CST43228_SDIO_RESET 0x20 - -/* -* Maximum delay for the PMU state transition in us. -* This is an upper bound intended for spinwaits etc. -*/ -#define CHIPC_PMU_MAX_TRANSITION_DLY 15000 - -/* PMU resource up transition time in ILP cycles */ -#define CHIPC_PMURES_UP_TRANSITION 2 /* * Register eci_inputlo bitfield values. * - BT packet type information bits [7:0] */ /* [3:0] - Task (link) type */ #define CHIPC_BT_ACL 0x00 #define CHIPC_BT_SCO 0x01 #define CHIPC_BT_eSCO 0x02 #define CHIPC_BT_A2DP 0x03 #define CHIPC_BT_SNIFF 0x04 #define CHIPC_BT_PAGE_SCAN 0x05 #define CHIPC_BT_INQUIRY_SCAN 0x06 #define CHIPC_BT_PAGE 0x07 #define CHIPC_BT_INQUIRY 0x08 #define CHIPC_BT_MSS 0x09 #define CHIPC_BT_PARK 0x0a #define CHIPC_BT_RSSISCAN 0x0b #define CHIPC_BT_MD_ACL 0x0c #define CHIPC_BT_MD_eSCO 0x0d #define CHIPC_BT_SCAN_WITH_SCO_LINK 0x0e #define CHIPC_BT_SCAN_WITHOUT_SCO_LINK 0x0f /* [7:4] = packet duration code */ /* [8] - Master / Slave */ #define CHIPC_BT_MASTER 0 #define CHIPC_BT_SLAVE 1 /* [11:9] - multi-level priority */ #define CHIPC_BT_LOWEST_PRIO 0x0 #define CHIPC_BT_HIGHEST_PRIO 0x3 #endif /* _BHND_CORES_CHIPC_CHIPCREG_H_ */ Index: head/sys/dev/bhnd/cores/chipc/chipcvar.h =================================================================== --- head/sys/dev/bhnd/cores/chipc/chipcvar.h (revision 304869) +++ head/sys/dev/bhnd/cores/chipc/chipcvar.h (revision 304870) @@ -1,225 +1,169 @@ /*- * Copyright (c) 2015 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. * * $FreeBSD$ */ #ifndef _BHND_CORES_CHIPC_CHIPCVAR_H_ #define _BHND_CORES_CHIPC_CHIPCVAR_H_ #include #include #include #include "chipc.h" -DECLARE_CLASS(bhnd_chipc); +DECLARE_CLASS(bhnd_chipc_driver); extern devclass_t bhnd_chipc_devclass; struct chipc_region; -/** - * Supported ChipCommon flash types. - */ -typedef enum { - CHIPC_FLASH_NONE = 0, /**< No flash, or a type unrecognized - by the ChipCommon driver */ - CHIPC_PFLASH_CFI = 1, /**< CFI-compatible parallel flash */ - CHIPC_SFLASH_ST = 2, /**< ST serial flash */ - CHIPC_SFLASH_AT = 3, /**< Atmel serial flash */ - CHIPC_QSFLASH_ST = 4, /**< ST quad-SPI flash */ - CHIPC_QSFLASH_AT = 5, /**< Atmel quad-SPI flash */ - CHIPC_NFLASH = 6, /**< NAND flash */ - CHIPC_NFLASH_4706 = 7 /**< BCM4706 NAND flash */ -} chipc_flash; - const char *chipc_flash_name(chipc_flash type); const char *chipc_flash_bus_name(chipc_flash type); const char *chipc_sflash_device_name(chipc_flash type); - -/** - * ChipCommon capability flags; - */ -struct chipc_caps { - uint8_t num_uarts; /**< Number of attached UARTS (1-3) */ - bool mipseb; /**< MIPS is big-endian */ - uint8_t uart_clock; /**< UART clock source (see CHIPC_CAP_UCLKSEL_*) */ - uint8_t uart_gpio; /**< UARTs own GPIO pins 12-15 */ - - uint8_t extbus_type; /**< ExtBus type (CHIPC_CAP_EXTBUS_*) */ - - chipc_flash flash_type; /**< flash type */ - uint8_t cfi_width; /**< CFI bus width, 0 if unknown or CFI - not present */ - - bhnd_nvram_src nvram_src; /**< identified NVRAM source */ - bus_size_t sprom_offset; /**< Offset to SPROM data within - SPROM/OTP, 0 if unknown or not - present */ - uint8_t otp_size; /**< OTP (row?) size, 0 if not present */ - - uint8_t pll_type; /**< PLL type */ - bool power_control; /**< Power control available */ - bool jtag_master; /**< JTAG Master present */ - bool boot_rom; /**< Internal boot ROM is active */ - uint8_t backplane_64; /**< Backplane supports 64-bit addressing. - Note that this does not gaurantee - the CPU itself supports 64-bit - addressing. */ - bool pmu; /**< PMU is present. */ - bool eci; /**< ECI (enhanced coexistence inteface) is present. */ - bool seci; /**< SECI (serial ECI) is present */ - bool sprom; /**< SPROM is present */ - bool gsio; /**< GSIO (SPI/I2C) present */ - bool aob; /**< AOB (always on bus) present. - If set, PMU and GCI registers are - not accessible via ChipCommon, - and are instead accessible via - dedicated cores on the bhnd bus */ -}; /* * ChipCommon device quirks / features */ enum { /** No quirks */ CHIPC_QUIRK_NONE = 0, /** * ChipCommon-controlled SPROM/OTP is supported, along with the * CHIPC_CAP_SPROM capability flag. */ CHIPC_QUIRK_SUPPORTS_SPROM = (1<<1), /** * The BCM4706 NAND flash interface is supported, along with the * CHIPC_CAP_4706_NFLASH capability flag. */ CHIPC_QUIRK_4706_NFLASH = (1<<2), /** * The SPROM is attached via muxed pins. The pins must be switched * to allow reading/writing. */ CHIPC_QUIRK_MUX_SPROM = (1<<3), /** * Access to the SPROM uses pins shared with the 802.11a external PA. * * On modules using these 4331 packages, the CCTRL4331_EXTPA_EN flag * must be cleared to allow SPROM access. */ CHIPC_QUIRK_4331_EXTPA_MUX_SPROM = (1<<4) | CHIPC_QUIRK_MUX_SPROM, /** * Access to the SPROM uses pins shared with the 802.11a external PA. * * On modules using these 4331 chip packages, the external PA is * attached via GPIO 2, 5, and sprom_dout pins. * * When enabling and disabling EXTPA to allow SPROM access, the * CCTRL4331_EXTPA_ON_GPIO2_5 flag must also be set or cleared, * respectively. */ CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM = (1<<5) | CHIPC_QUIRK_4331_EXTPA_MUX_SPROM, /** * Access to the SPROM uses pins shared with two 802.11a external PAs. * * When enabling and disabling EXTPA, the CCTRL4331_EXTPA_EN2 must also * be cleared to allow SPROM access. */ CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM = (1<<6) | CHIPC_QUIRK_4331_EXTPA_MUX_SPROM, /** * SPROM pins are muxed with the FEM control lines on this 4360-family * device. The muxed pins must be switched to allow reading/writing * the SPROM. */ CHIPC_QUIRK_4360_FEM_MUX_SPROM = (1<<5) | CHIPC_QUIRK_MUX_SPROM, /** Supports CHIPC_CAPABILITIES_EXT register */ CHIPC_QUIRK_SUPPORTS_CAP_EXT = (1<<6), /** Supports HND or IPX OTP registers (CHIPC_OTPST, CHIPC_OTPCTRL, * CHIPC_OTPPROG) */ CHIPC_QUIRK_SUPPORTS_OTP = (1<<7), /** Supports HND OTP registers. */ CHIPC_QUIRK_OTP_HND = (1<<8) | CHIPC_QUIRK_SUPPORTS_OTP, /** Supports IPX OTP registers. */ CHIPC_QUIRK_OTP_IPX = (1<<9) | CHIPC_QUIRK_SUPPORTS_OTP, /** OTP size is defined via CHIPC_OTPLAYOUT register in later * ChipCommon revisions using the 'IPX' OTP controller. */ CHIPC_QUIRK_IPX_OTPL_SIZE = (1<<10) }; /** * chipc child device info. */ struct chipc_devinfo { struct resource_list resources; /**< child resources */ }; /** * chipc driver instance state. */ struct chipc_softc { device_t dev; struct bhnd_resource *core; /**< core registers. */ struct chipc_region *core_region; /**< region containing core registers */ uint32_t quirks; /**< chipc quirk flags */ struct chipc_caps caps; /**< chipc capabilities */ struct mtx mtx; /**< state mutex. */ size_t sprom_refcnt; /**< SPROM pin enable refcount */ struct rman mem_rman; /**< port memory manager */ STAILQ_HEAD(, chipc_region) mem_regions;/**< memory allocation records */ }; #define CHIPC_LOCK_INIT(sc) \ mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \ "BHND chipc driver lock", MTX_DEF) #define CHIPC_LOCK(sc) mtx_lock(&(sc)->mtx) #define CHIPC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) #define CHIPC_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what) #define CHIPC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) #endif /* _BHND_CORES_CHIPC_CHIPCVAR_H_ */ Index: head/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl.c =================================================================== --- head/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl.c (nonexistent) +++ head/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl.c (revision 304870) @@ -0,0 +1,479 @@ +/*- + * Copyright (c) 2016 Landon Fuller + * Copyright (c) 2010, Broadcom Corporation. + * All rights reserved. + * + * This file is derived from the siutils.c source distributed with the + * Asus RT-N16 firmware source code release. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id: siutils.c,v 1.821.2.48 2011-02-11 20:59:28 Exp $ + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include + +#include "bhnd_chipc_if.h" + +#include "bhnd_pwrctl_private.h" + +/* + * ChipCommon Power Control. + * + * Provides a bhnd_pmu_if-compatible interface to device clocking and + * power management on non-PMU chipsets. + */ + +typedef enum { + BHND_PWRCTL_WAR_UP, /**< apply attach/resume workarounds */ + BHND_PWRCTL_WAR_RUN, /**< apply running workarounds */ + BHND_PWRCTL_WAR_DOWN, /**< apply detach/suspend workarounds */ +} bhnd_pwrctl_wars; + +static int bhnd_pwrctl_updateclk(struct bhnd_pwrctl_softc *sc, + bhnd_pwrctl_wars wars); + +static struct bhnd_device_quirk pwrctl_quirks[]; + + +/* Supported parent core device identifiers */ +static const struct bhnd_device pwrctl_devices[] = { + BHND_DEVICE(BCM, CC, "ChipCommon Power Control", pwrctl_quirks), + BHND_DEVICE_END +}; + +/* Device quirks table */ +static struct bhnd_device_quirk pwrctl_quirks[] = { + BHND_CORE_QUIRK (HWREV_LTE(5), PWRCTL_QUIRK_PCICLK_CTL), + BHND_CORE_QUIRK (HWREV_RANGE(6, 9), PWRCTL_QUIRK_SLOWCLK_CTL), + BHND_CORE_QUIRK (HWREV_RANGE(10, 19), PWRCTL_QUIRK_INSTACLK_CTL), + + BHND_DEVICE_QUIRK_END +}; + +static int +bhnd_pwrctl_probe(device_t dev) +{ + const struct bhnd_device *id; + struct chipc_caps *ccaps; + device_t chipc; + + /* Look for compatible chipc parent */ + chipc = device_get_parent(dev); + if (device_get_devclass(chipc) != devclass_find("bhnd_chipc")) + return (ENXIO); + + if (device_get_driver(chipc) != &bhnd_chipc_driver) + return (ENXIO); + + /* Verify chipc capability flags */ + ccaps = BHND_CHIPC_GET_CAPS(chipc); + if (ccaps->pmu || !ccaps->pwr_ctrl) + return (ENXIO); + + /* Check for chipc device match */ + id = bhnd_device_lookup(chipc, pwrctl_devices, + sizeof(pwrctl_devices[0])); + if (id == NULL) + return (ENXIO); + + device_set_desc(dev, id->desc); + return (BUS_PROBE_NOWILDCARD); +} + +static int +bhnd_pwrctl_attach(device_t dev) +{ + struct bhnd_pwrctl_softc *sc; + const struct bhnd_chipid *cid; + struct chipc_softc *chipc_sc; + bhnd_devclass_t hostb_class; + device_t hostb_dev; + int error; + + sc = device_get_softc(dev); + + /* TODO: Need further testing on actual PWRCTL hardware */ + device_printf(dev, "WARNING: Using untested PWRCTL support\n"); + + sc->dev = dev; + sc->chipc_dev = device_get_parent(dev); + sc->quirks = bhnd_device_quirks(sc->chipc_dev, pwrctl_devices, + sizeof(pwrctl_devices[0])); + + /* On devices that lack a slow clock source, HT must always be + * enabled. */ + hostb_class = BHND_DEVCLASS_INVALID; + hostb_dev = bhnd_find_hostb_device(device_get_parent(sc->chipc_dev)); + if (hostb_dev != NULL) + hostb_class = bhnd_get_class(hostb_dev); + + cid = bhnd_get_chipid(sc->chipc_dev); + switch (cid->chip_id) { + case BHND_CHIPID_BCM4311: + if (cid->chip_rev <= 1 && hostb_class == BHND_DEVCLASS_PCI) + sc->quirks |= PWRCTL_QUIRK_FORCE_HT; + break; + + case BHND_CHIPID_BCM4321: + if (hostb_class == BHND_DEVCLASS_PCIE || + hostb_class == BHND_DEVCLASS_PCI) + sc->quirks |= PWRCTL_QUIRK_FORCE_HT; + break; + + case BHND_CHIPID_BCM4716: + if (hostb_class == BHND_DEVCLASS_PCIE) + sc->quirks |= PWRCTL_QUIRK_FORCE_HT; + break; + } + + /* Fetch core register block from ChipCommon parent */ + chipc_sc = device_get_softc(sc->chipc_dev); + sc->res = chipc_sc->core; + + PWRCTL_LOCK_INIT(sc); + STAILQ_INIT(&sc->clkres_list); + + /* Initialize power control */ + PWRCTL_LOCK(sc); + + if ((error = bhnd_pwrctl_init(sc))) { + PWRCTL_UNLOCK(sc); + goto cleanup; + } + + /* Apply default clock transitions */ + if ((error = bhnd_pwrctl_updateclk(sc, BHND_PWRCTL_WAR_UP))) { + PWRCTL_UNLOCK(sc); + goto cleanup; + } + + PWRCTL_UNLOCK(sc); + + return (0); + +cleanup: + PWRCTL_LOCK_DESTROY(sc); + return (error); +} + +static int +bhnd_pwrctl_detach(device_t dev) +{ + struct bhnd_pwrctl_softc *sc; + struct bhnd_pwrctl_clkres *clkres, *crnext; + int error; + + sc = device_get_softc(dev); + + if ((error = bhnd_pwrctl_setclk(sc, BHND_CLOCK_DYN))) + return (error); + + STAILQ_FOREACH_SAFE(clkres, &sc->clkres_list, cr_link, crnext) + free(clkres, M_DEVBUF); + + PWRCTL_LOCK_DESTROY(sc); + return (0); +} + +static int +bhnd_pwrctl_suspend(device_t dev) +{ + struct bhnd_pwrctl_softc *sc; + int error; + + sc = device_get_softc(dev); + + /* Update clock state */ + PWRCTL_LOCK(sc); + error = bhnd_pwrctl_updateclk(sc, BHND_PWRCTL_WAR_DOWN); + PWRCTL_UNLOCK(sc); + + return (error); +} + +static int +bhnd_pwrctl_resume(device_t dev) +{ + struct bhnd_pwrctl_softc *sc; + int error; + + sc = device_get_softc(dev); + + PWRCTL_LOCK(sc); + + /* Re-initialize power control registers */ + if ((error = bhnd_pwrctl_init(sc))) { + device_printf(sc->dev, "PWRCTL init failed: %d\n", error); + goto cleanup; + } + + /* Restore clock state */ + if ((error = bhnd_pwrctl_updateclk(sc, BHND_PWRCTL_WAR_UP))) { + device_printf(sc->dev, "clock state restore failed: %d\n", + error); + goto cleanup; + } + +cleanup: + PWRCTL_UNLOCK(sc); + return (error); +} + +/** + * Find the clock reservation associated with @p pinfo, if any. + * + * @param sc Driver instance state. + * @param pinfo PMU info for device. + */ +static struct bhnd_pwrctl_clkres * +bhnd_pwrctl_find_res(struct bhnd_pwrctl_softc *sc, + struct bhnd_core_pmu_info *pinfo) +{ + struct bhnd_pwrctl_clkres *clkres; + + PWRCTL_LOCK_ASSERT(sc, MA_OWNED); + + STAILQ_FOREACH(clkres, &sc->clkres_list, cr_link) { + if (clkres->owner == pinfo->pm_dev) + return (clkres); + } + + /* not found */ + return (NULL); +} + +/** + * Enumerate all active clock requests, compute the minimum required clock, + * and issue any required clock transition. + * + * @param sc Driver instance state. + * @param wars Work-around state. + */ +static int +bhnd_pwrctl_updateclk(struct bhnd_pwrctl_softc *sc, bhnd_pwrctl_wars wars) +{ + struct bhnd_pwrctl_clkres *clkres; + bhnd_clock clock; + + PWRCTL_LOCK_ASSERT(sc, MA_OWNED); + + /* Default clock target */ + clock = BHND_CLOCK_DYN; + + /* Apply quirk-specific overrides to the clock target */ + switch (wars) { + case BHND_PWRCTL_WAR_UP: + /* Force HT clock */ + if (PWRCTL_QUIRK(sc, FORCE_HT)) + clock = BHND_CLOCK_HT; + break; + + case BHND_PWRCTL_WAR_RUN: + /* Cannot transition clock if FORCE_HT */ + if (PWRCTL_QUIRK(sc, FORCE_HT)) + return (0); + break; + + case BHND_PWRCTL_WAR_DOWN: + /* Leave default clock unmodified to permit + * transition back to BHND_CLOCK_DYN on FORCE_HT devices. */ + break; + } + + /* Determine required clock */ + STAILQ_FOREACH(clkres, &sc->clkres_list, cr_link) + clock = bhnd_clock_max(clock, clkres->clock); + + /* Map to supported clock setting */ + switch (clock) { + case BHND_CLOCK_DYN: + case BHND_CLOCK_ILP: + clock = BHND_CLOCK_DYN; + break; + case BHND_CLOCK_ALP: + /* In theory FORCE_ALP is supported by the hardware, but + * there are currently no known use-cases for it; mapping + * to HT is still valid, and allows us to punt on determing + * where FORCE_ALP is supported and functional */ + clock = BHND_CLOCK_HT; + break; + case BHND_CLOCK_HT: + break; + default: + device_printf(sc->dev, "unknown clock: %#x\n", clock); + return (ENODEV); + } + + /* Issue transition */ + return (bhnd_pwrctl_setclk(sc, clock)); +} + +static int +bhnd_pwrctl_core_req_clock(device_t dev, struct bhnd_core_pmu_info *pinfo, + bhnd_clock clock) +{ + struct bhnd_pwrctl_softc *sc; + struct bhnd_pwrctl_clkres *clkres; + int error; + + sc = device_get_softc(dev); + error = 0; + + PWRCTL_LOCK(sc); + + clkres = bhnd_pwrctl_find_res(sc, pinfo); + + /* BHND_CLOCK_DYN discards the clock reservation entirely */ + if (clock == BHND_CLOCK_DYN) { + /* nothing to clean up? */ + if (clkres == NULL) { + PWRCTL_UNLOCK(sc); + return (0); + } + + /* drop reservation and apply clock transition */ + STAILQ_REMOVE(&sc->clkres_list, clkres, + bhnd_pwrctl_clkres, cr_link); + + if ((error = bhnd_pwrctl_updateclk(sc, BHND_PWRCTL_WAR_RUN))) { + device_printf(dev, "clock transition failed: %d\n", + error); + + /* restore reservation */ + STAILQ_INSERT_TAIL(&sc->clkres_list, clkres, cr_link); + + PWRCTL_UNLOCK(sc); + return (error); + } + + /* deallocate orphaned reservation */ + free(clkres, M_DEVBUF); + + PWRCTL_UNLOCK(sc); + return (0); + } + + /* create (or update) reservation */ + if (clkres == NULL) { + clkres = malloc(sizeof(struct bhnd_pwrctl_clkres), M_DEVBUF, + M_NOWAIT); + if (clkres == NULL) + return (ENOMEM); + + clkres->owner = pinfo->pm_dev; + clkres->clock = clock; + + STAILQ_INSERT_TAIL(&sc->clkres_list, clkres, cr_link); + } else { + KASSERT(clkres->owner == pinfo->pm_dev, ("invalid owner")); + clkres->clock = clock; + } + + /* apply clock transition */ + error = bhnd_pwrctl_updateclk(sc, BHND_PWRCTL_WAR_RUN); + if (error) { + STAILQ_REMOVE(&sc->clkres_list, clkres, bhnd_pwrctl_clkres, + cr_link); + free(clkres, M_DEVBUF); + } + + PWRCTL_UNLOCK(sc); + return (error); +} + +static int +bhnd_pwrctl_core_req_ext_rsrc(device_t dev, struct bhnd_core_pmu_info *pinfo, + u_int rsrc) +{ + /* HW does not support per-core external resources */ + return (ENODEV); +} + +static int +bhnd_pwrctl_core_release_ext_rsrc(device_t dev, + struct bhnd_core_pmu_info *pinfo, u_int rsrc) +{ + /* HW does not support per-core external resources */ + return (ENODEV); +} + +static int +bhnd_pwrctl_core_en_clocks(device_t dev, struct bhnd_core_pmu_info *pinfo, + uint32_t clocks) +{ + /* All supported clocks are already enabled by default (?) */ + clocks &= ~(BHND_CLOCK_DYN | + BHND_CLOCK_ILP | + BHND_CLOCK_ALP | + BHND_CLOCK_HT); + + if (clocks != 0) { + device_printf(dev, "%s requested unknown clocks: %#x\n", + device_get_nameunit(pinfo->pm_dev), clocks); + return (ENODEV); + } + + return (0); +} + +static int +bhnd_pwrctl_core_release(device_t dev, struct bhnd_core_pmu_info *pinfo) +{ + /* Requesting BHND_CLOCK_DYN releases any outstanding clock + * reservations */ + return (bhnd_pwrctl_core_req_clock(dev, pinfo, BHND_CLOCK_DYN)); +} + +static device_method_t bhnd_pwrctl_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, bhnd_pwrctl_probe), + DEVMETHOD(device_attach, bhnd_pwrctl_attach), + DEVMETHOD(device_detach, bhnd_pwrctl_detach), + DEVMETHOD(device_suspend, bhnd_pwrctl_suspend), + DEVMETHOD(device_resume, bhnd_pwrctl_resume), + + /* BHND PMU interface */ + DEVMETHOD(bhnd_pmu_core_req_clock, bhnd_pwrctl_core_req_clock), + DEVMETHOD(bhnd_pmu_core_en_clocks, bhnd_pwrctl_core_en_clocks), + DEVMETHOD(bhnd_pmu_core_req_ext_rsrc, bhnd_pwrctl_core_req_ext_rsrc), + DEVMETHOD(bhnd_pmu_core_release_ext_rsrc, bhnd_pwrctl_core_release_ext_rsrc), + DEVMETHOD(bhnd_pmu_core_release, bhnd_pwrctl_core_release), + + DEVMETHOD_END +}; + +DEFINE_CLASS_0(bhnd_pmu, bhnd_pwrctl_driver, bhnd_pwrctl_methods, + sizeof(struct bhnd_pwrctl_softc)); +EARLY_DRIVER_MODULE(bhnd_pwrctl, bhnd_chipc, bhnd_pwrctl_driver, + bhnd_pmu_devclass, NULL, NULL, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); + +MODULE_DEPEND(bhnd_pwrctl, bhnd, 1, 1, 1); +MODULE_VERSION(bhnd_pwrctl, 1); Property changes on: head/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_private.h =================================================================== --- head/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_private.h (nonexistent) +++ head/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_private.h (revision 304870) @@ -0,0 +1,43 @@ +/*- + * Copyright (c) 2016 Landon Fuller + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ + +#ifndef _BHND_PWRCTL_BHND_PWRCTL_PRIVATE_H_ +#define _BHND_PWRCTL_BHND_PWRCTL_PRIVATE_H_ + +#include "bhnd_pwrctlvar.h" + +int bhnd_pwrctl_init(struct bhnd_pwrctl_softc *sc); +int bhnd_pwrctl_setclk(struct bhnd_pwrctl_softc *sc, + bhnd_clock clock); +uint32_t bhnd_pwrctl_getclk_speed(struct bhnd_pwrctl_softc *sc); +uint16_t bhnd_pwrctl_fast_pwrup_delay(struct bhnd_pwrctl_softc *sc); + +#endif /* _BHND_PWRCTL_BHND_PWRCTL_PRIVATE_H_ */ Property changes on: head/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_private.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c =================================================================== --- head/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c (nonexistent) +++ head/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c (revision 304870) @@ -0,0 +1,463 @@ +/*- + * Copyright (c) 2016 Landon Fuller + * Copyright (c) 2010, Broadcom Corporation. + * All rights reserved. + * + * This file is derived from the siutils.c source distributed with the + * Asus RT-N16 firmware source code release. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id: siutils.c,v 1.821.2.48 2011-02-11 20:59:28 Exp $ + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include + +#include "bhnd_chipc_if.h" + +#include "bhnd_pwrctl_private.h" + +static uint32_t bhnd_pwrctl_factor6(uint32_t x); +static uint32_t bhnd_pwrctl_clock_rate(uint32_t pll_type, uint32_t n, + uint32_t m); + +/** + * Return the factor value corresponding to a given N3M clock control magic + * field value (CHIPC_F6_*). + */ +static uint32_t +bhnd_pwrctl_factor6(uint32_t x) +{ + switch (x) { + case CHIPC_F6_2: + return (2); + case CHIPC_F6_3: + return (3); + case CHIPC_F6_4: + return (4); + case CHIPC_F6_5: + return (5); + case CHIPC_F6_6: + return (6); + case CHIPC_F6_7: + return (7); + default: + return (0); + } +} + +/** + * Calculate the clock speed (in Hz) for a given a set of clockcontrol + * values. + * + * @param pll_type PLL type (CHIPC_PLL_TYPE*) + * @param n clock control N register value. + * @param m clock control N register value. + */ +static uint32_t +bhnd_pwrctl_clock_rate(uint32_t pll_type, uint32_t n, uint32_t m) +{ + uint32_t clk_base; + uint32_t n1, n2, clock, m1, m2, m3, mc; + + n1 = CHIPC_GET_BITS(n, CHIPC_CN_N1); + n2 = CHIPC_GET_BITS(n, CHIPC_CN_N2); + + switch (pll_type) { + case CHIPC_PLL_TYPE1: + case CHIPC_PLL_TYPE3: + case CHIPC_PLL_TYPE4: + case CHIPC_PLL_TYPE7: + n1 = bhnd_pwrctl_factor6(n1); + n2 += CHIPC_F5_BIAS; + break; + + case CHIPC_PLL_TYPE2: + n1 += CHIPC_T2_BIAS; + n2 += CHIPC_T2_BIAS; + KASSERT(n1 >= 2 && n1 <= 7, ("invalid n1 value")); + KASSERT(n2 >= 5 && n2 <= 23, ("invalid n2 value")); + break; + + case CHIPC_PLL_TYPE5: + return (100000000); + + case CHIPC_PLL_TYPE6: + if (m & CHIPC_T6_MMASK) + return (CHIPC_T6_M1); + else + return (CHIPC_T6_M0); + + default: + printf("unsupported PLL type %u\n", pll_type); + return (0); + } + + /* PLL types 3 and 7 use BASE2 (25Mhz) */ + if (pll_type == CHIPC_PLL_TYPE3 || pll_type == CHIPC_PLL_TYPE7) { + clk_base = CHIPC_CLOCK_BASE2; + } else { + clk_base = CHIPC_CLOCK_BASE1; + } + + clock = clk_base * n1 * n2; + + if (clock == 0) + return (0); + + m1 = CHIPC_GET_BITS(m, CHIPC_M1); + m2 = CHIPC_GET_BITS(m, CHIPC_M2); + m3 = CHIPC_GET_BITS(m, CHIPC_M3); + mc = CHIPC_GET_BITS(m, CHIPC_MC); + + switch (pll_type) { + case CHIPC_PLL_TYPE1: + case CHIPC_PLL_TYPE3: + case CHIPC_PLL_TYPE4: + case CHIPC_PLL_TYPE7: + m1 = bhnd_pwrctl_factor6(m1); + if (pll_type == CHIPC_PLL_TYPE1 || pll_type == CHIPC_PLL_TYPE3) + m2 += CHIPC_F5_BIAS; + else + m2 = bhnd_pwrctl_factor6(m2); + + m3 = bhnd_pwrctl_factor6(m3); + + switch (mc) { + case CHIPC_MC_BYPASS: + return (clock); + case CHIPC_MC_M1: + return (clock / m1); + case CHIPC_MC_M1M2: + return (clock / (m1 * m2)); + case CHIPC_MC_M1M2M3: + return (clock / (m1 * m2 * m3)); + case CHIPC_MC_M1M3: + return (clock / (m1 * m3)); + default: + printf("unsupported pwrctl mc %#x\n", mc); + return (0); + } + case CHIPC_PLL_TYPE2: + m1 += CHIPC_T2_BIAS; + m2 += CHIPC_T2M2_BIAS; + m3 += CHIPC_T2_BIAS; + KASSERT(m1 >= 2 && m1 <= 7, ("invalid m1 value")); + KASSERT(m2 >= 3 && m2 <= 10, ("invalid m2 value")); + KASSERT(m3 >= 2 && m3 <= 7, ("invalid m3 value")); + + if ((mc & CHIPC_T2MC_M1BYP) == 0) + clock /= m1; + if ((mc & CHIPC_T2MC_M2BYP) == 0) + clock /= m2; + if ((mc & CHIPC_T2MC_M3BYP) == 0) + clock /= m3; + + return (clock); + default: + panic("unhandled PLL type %u\n", pll_type); + } +} + +/** + * Return the backplane clock speed in Hz. + * + * @param sc driver instance state. + */ +uint32_t +bhnd_pwrctl_getclk_speed(struct bhnd_pwrctl_softc *sc) +{ + struct chipc_caps *ccaps; + bus_size_t creg; + uint32_t n, m; + uint32_t rate; + + PWRCTL_LOCK_ASSERT(sc, MA_OWNED); + + ccaps = BHND_CHIPC_GET_CAPS(sc->chipc_dev); + + n = bhnd_bus_read_4(sc->res, CHIPC_CLKC_N); + + switch (ccaps->pll_type) { + case CHIPC_PLL_TYPE6: + creg = CHIPC_CLKC_M3; /* non-extif regster */ + break; + case CHIPC_PLL_TYPE3: + creg = CHIPC_CLKC_M2; + break; + default: + creg = CHIPC_CLKC_SB; + break; + } + + m = bhnd_bus_read_4(sc->res, creg); + + /* calculate rate */ + rate = bhnd_pwrctl_clock_rate(ccaps->pll_type, n, m); + + if (ccaps->pll_type == CHIPC_PLL_TYPE3) + rate /= 2; + + return (rate); +} + +/* return the slow clock source */ +static bhnd_clksrc +bhnd_pwrctl_slowclk_src(struct bhnd_pwrctl_softc *sc) +{ + uint32_t clkreg; + uint32_t clksrc; + + /* Fetch clock source */ + if (PWRCTL_QUIRK(sc, PCICLK_CTL)) { + return (bhnd_pwrctl_get_clksrc(sc->chipc_dev, BHND_CLOCK_ILP)); + } else if (PWRCTL_QUIRK(sc, SLOWCLK_CTL)) { + clkreg = bhnd_bus_read_4(sc->res, CHIPC_PLL_SLOWCLK_CTL); + clksrc = clkreg & CHIPC_SCC_SS_MASK; + } else { + /* Instaclock */ + clksrc = CHIPC_SCC_SS_XTAL; + } + + /* Map to bhnd_clksrc */ + switch (clksrc) { + case CHIPC_SCC_SS_PCI: + return (BHND_CLKSRC_PCI); + case CHIPC_SCC_SS_LPO: + return (BHND_CLKSRC_LPO); + case CHIPC_SCC_SS_XTAL: + return (BHND_CLKSRC_XTAL); + default: + return (BHND_CLKSRC_UNKNOWN); + } +} + +/* return the ILP (slowclock) min or max frequency */ +static uint32_t +bhnd_pwrctl_slowclk_freq(struct bhnd_pwrctl_softc *sc, bool max_freq) +{ + bhnd_clksrc slowclk; + uint32_t div; + uint32_t hz; + + slowclk = bhnd_pwrctl_slowclk_src(sc); + + /* Determine clock divisor */ + if (PWRCTL_QUIRK(sc, PCICLK_CTL)) { + if (slowclk == BHND_CLKSRC_PCI) + div = 64; + else + div = 32; + } else if (PWRCTL_QUIRK(sc, SLOWCLK_CTL)) { + div = bhnd_bus_read_4(sc->res, CHIPC_PLL_SLOWCLK_CTL); + div = CHIPC_GET_BITS(div, CHIPC_SCC_CD); + div *= 4; + } else if (PWRCTL_QUIRK(sc, INSTACLK_CTL)) { + if (max_freq) { + div = 1; + } else { + div = bhnd_bus_read_4(sc->res, CHIPC_SYS_CLK_CTL); + div = CHIPC_GET_BITS(div, CHIPC_SYCC_CD); + div = 4 * (div + 1); + } + } else { + device_printf(sc->dev, "unknown device type\n"); + return (0); + } + + /* Determine clock frequency */ + switch (slowclk) { + case BHND_CLKSRC_LPO: + hz = max_freq ? CHIPC_LPOMAXFREQ : CHIPC_LPOMINFREQ; + break; + case BHND_CLKSRC_XTAL: + hz = max_freq ? CHIPC_XTALMAXFREQ : CHIPC_XTALMINFREQ; + break; + case BHND_CLKSRC_PCI: + hz = max_freq ? CHIPC_PCIMAXFREQ : CHIPC_PCIMINFREQ; + break; + default: + device_printf(sc->dev, "unknown slowclk source %#x\n", slowclk); + return (0); + } + + return (hz / div); +} + +/** + * Initialize power control registers. + */ +int +bhnd_pwrctl_init(struct bhnd_pwrctl_softc *sc) +{ + uint32_t clkctl; + uint32_t pll_delay, slowclk, slowmaxfreq; + uint32_t pll_on_delay, fref_sel_delay; + int error; + + pll_delay = CHIPC_PLL_DELAY; + + /* set all Instaclk chip ILP to 1 MHz */ + if (PWRCTL_QUIRK(sc, INSTACLK_CTL)) { + clkctl = (CHIPC_ILP_DIV_1MHZ << CHIPC_SYCC_CD_SHIFT); + clkctl &= CHIPC_SYCC_CD_MASK; + bhnd_bus_write_4(sc->res, CHIPC_SYS_CLK_CTL, clkctl); + } + + /* + * Initialize PLL/FREF delays. + * + * If the slow clock is not sourced by the xtal, include the + * delay required to bring it up. + */ + slowclk = bhnd_pwrctl_slowclk_src(sc); + if (slowclk != CHIPC_SCC_SS_XTAL) + pll_delay += CHIPC_XTAL_ON_DELAY; + + /* Starting with 4318 it is ILP that is used for the delays */ + if (PWRCTL_QUIRK(sc, INSTACLK_CTL)) + slowmaxfreq = bhnd_pwrctl_slowclk_freq(sc, false); + else + slowmaxfreq = bhnd_pwrctl_slowclk_freq(sc, true); + + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000; + fref_sel_delay = ((slowmaxfreq * CHIPC_FREF_DELAY) + 999999) / 1000000; + + bhnd_bus_write_4(sc->res, CHIPC_PLL_ON_DELAY, pll_on_delay); + bhnd_bus_write_4(sc->res, CHIPC_PLL_FREFSEL_DELAY, fref_sel_delay); + + /* If required, force HT */ + if (PWRCTL_QUIRK(sc, FORCE_HT)) { + if ((error = bhnd_pwrctl_setclk(sc, BHND_CLOCK_HT))) + return (error); + } + + return (0); +} + +/* return the value suitable for writing to the dot11 core + * FAST_PWRUP_DELAY register */ +uint16_t +bhnd_pwrctl_fast_pwrup_delay(struct bhnd_pwrctl_softc *sc) +{ + uint32_t pll_on_delay, slowminfreq; + uint16_t fpdelay; + + fpdelay = 0; + + slowminfreq = bhnd_pwrctl_slowclk_freq(sc, false); + + pll_on_delay = bhnd_bus_read_4(sc->res, CHIPC_PLL_ON_DELAY) + 2; + pll_on_delay *= 1000000; + pll_on_delay += (slowminfreq - 1); + fpdelay = pll_on_delay / slowminfreq; + + return (fpdelay); +} + +/** + * Distribute @p clock on backplane. + * + * @param sc Driver instance state. + * @param clock Clock to enable. + * + * @retval 0 success + * @retval ENODEV If @p clock is unsupported, or if the device does not + * support dynamic clock control. + */ +int +bhnd_pwrctl_setclk(struct bhnd_pwrctl_softc *sc, bhnd_clock clock) +{ + uint32_t scc; + + PWRCTL_LOCK_ASSERT(sc, MA_OWNED); + + /* Is dynamic clock control supported? */ + if (PWRCTL_QUIRK(sc, FIXED_CLK)) + return (ENODEV); + + /* Chips with ccrev 10 are EOL and they don't have SYCC_HR used below */ + if (bhnd_get_hwrev(sc->chipc_dev) == 10) + return (ENODEV); + + scc = bhnd_bus_read_4(sc->res, CHIPC_PLL_SLOWCLK_CTL); + + switch (clock) { + case BHND_CLOCK_HT: + /* fast (pll) clock */ + if (PWRCTL_QUIRK(sc, SLOWCLK_CTL)) { + scc &= ~(CHIPC_SCC_XC | CHIPC_SCC_FS | CHIPC_SCC_IP); + scc |= CHIPC_SCC_IP; + + /* force xtal back on before clearing SCC_DYN_XTAL.. */ + bhnd_pwrctl_ungate_clock(sc->chipc_dev, BHND_CLOCK_HT); + } else if (PWRCTL_QUIRK(sc, INSTACLK_CTL)) { + scc |= CHIPC_SYCC_HR; + } else { + return (ENODEV); + } + + bhnd_bus_write_4(sc->res, CHIPC_PLL_SLOWCLK_CTL, scc); + DELAY(CHIPC_PLL_DELAY); + + break; + + case BHND_CLOCK_DYN: + /* enable dynamic clock control */ + if (PWRCTL_QUIRK(sc, SLOWCLK_CTL)) { + scc &= ~(CHIPC_SCC_FS | CHIPC_SCC_IP | CHIPC_SCC_XC); + if ((scc & CHIPC_SCC_SS_MASK) != CHIPC_SCC_SS_XTAL) + scc |= CHIPC_SCC_XC; + + bhnd_bus_write_4(sc->res, CHIPC_PLL_SLOWCLK_CTL, scc); + + /* for dynamic control, we have to release our xtal_pu + * "force on" */ + if (scc & CHIPC_SCC_XC) { + bhnd_pwrctl_gate_clock(sc->chipc_dev, + BHND_CLOCK_HT); + } + } else if (PWRCTL_QUIRK(sc, INSTACLK_CTL)) { + /* Instaclock */ + scc &= ~CHIPC_SYCC_HR; + bhnd_bus_write_4(sc->res, CHIPC_SYS_CLK_CTL, scc); + } else { + return (ENODEV); + } + + break; + + default: + return (ENODEV); + } + + return (0); +} Property changes on: head/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctlvar.h =================================================================== --- head/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctlvar.h (nonexistent) +++ head/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctlvar.h (revision 304870) @@ -0,0 +1,120 @@ +/*- + * Copyright (c) 2015-2016 Landon Fuller + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ + +#ifndef _BHND_PWRCTL_BHND_PWRCTLVAR_H_ +#define _BHND_PWRCTL_BHND_PWRCTLVAR_H_ + +#include +#include +#include + +/** + * bhnd pwrctl device quirks. + */ +enum { + /** No quirks */ + PWRCTL_QUIRK_NONE = 0, + + /** + * Early ChipCommon revisions do not support dynamic clock control + */ + PWRCTL_QUIRK_FIXED_CLK = (1 << 0), + + /** + * On PCI (not PCIe) devices, early ChipCommon revisions + * (rev <= 5) vend xtal/pll and clock config registers via the PCI + * config space. + * + * Dynamic clock control is not supported on these devices. + */ + PWRCTL_QUIRK_PCICLK_CTL = (1 << 1) | PWRCTL_QUIRK_FIXED_CLK, + + + /** + * On earliy BCM4311, BCM4321, and BCM4716 PCI(e) devices, no ALP + * clock is available, and the HT clock must be enabled. + */ + PWRCTL_QUIRK_FORCE_HT = (1 << 2), + + /** + * ChipCommon revisions 6-9 use the slowclk register layout. + */ + PWRCTL_QUIRK_SLOWCLK_CTL = (1 << 3), + + /** + * ChipCommon revisions 10-19 support the instaclk register layout. + */ + PWRCTL_QUIRK_INSTACLK_CTL = (1 << 4), + +}; + +/** + * device clock reservation. + */ +struct bhnd_pwrctl_clkres { + device_t owner; /**< bhnd(4) device holding this reservation */ + bhnd_clock clock; /**< requested clock */ + STAILQ_ENTRY(bhnd_pwrctl_clkres) cr_link; +}; + + +/** + * bhnd pwrctl driver instance state. + */ +struct bhnd_pwrctl_softc { + device_t dev; + uint32_t quirks; + + device_t chipc_dev; /**< core device */ + struct bhnd_resource *res; /**< core register block. */ + + struct mtx mtx; /**< state mutex */ + + /** active clock reservations */ + STAILQ_HEAD(, bhnd_pwrctl_clkres) clkres_list; +}; + +#define PWRCTL_LOCK_INIT(sc) \ + mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \ + "bhnd pwrctl driver lock", MTX_DEF) +#define PWRCTL_LOCK(sc) mtx_lock(&(sc)->mtx) +#define PWRCTL_UNLOCK(sc) mtx_unlock(&(sc)->mtx) +#define PWRCTL_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what) +#define PWRCTL_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) + +/* quirk convenience macro */ +#define PWRCTL_QUIRK(_sc, _name) \ + ((_sc)->quirks & PWRCTL_QUIRK_ ## _name) + +#define PWRCTL_ASSERT_QUIRK(_sc, name) \ + KASSERT(PWRCTL_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) + +#endif /* _BHND_PWRCTL_BHND_PWRCTLVAR_H_ */ Property changes on: head/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctlvar.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/bhnd/cores/pmu/bhnd_pmu.c =================================================================== --- head/sys/dev/bhnd/cores/pmu/bhnd_pmu.c (nonexistent) +++ head/sys/dev/bhnd/cores/pmu/bhnd_pmu.c (revision 304870) @@ -0,0 +1,466 @@ +/*- + * Copyright (c) 2015-2016 Landon Fuller + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include "bhnd_nvram_map.h" + +#include "bhnd_pmureg.h" +#include "bhnd_pmuvar.h" + +#include "bhnd_pmu_private.h" + +/* + * Broadcom PMU driver. + * + * On modern BHND chipsets, the PMU, GCI, and SRENG (Save/Restore Engine?) + * register blocks are found within a dedicated PMU core (attached via + * the AHB 'always on bus'). + * + * On earlier chipsets, these register blocks are found at the same + * offsets within the ChipCommon core. + */ + +devclass_t bhnd_pmu_devclass; /**< bhnd(4) PMU device class */ + +static int bhnd_pmu_sysctl_bus_freq(SYSCTL_HANDLER_ARGS); +static int bhnd_pmu_sysctl_cpu_freq(SYSCTL_HANDLER_ARGS); +static int bhnd_pmu_sysctl_mem_freq(SYSCTL_HANDLER_ARGS); + +#define BPMU_CLKCTL_READ_4(_pinfo) \ + bhnd_bus_read_4((_pinfo)->pm_res, (_pinfo)->pm_regs) + +#define BPMU_CLKCTL_WRITE_4(_pinfo, _val) \ + bhnd_bus_write_4((_pinfo)->pm_res, (_pinfo)->pm_regs, (_val)) + +#define BPMU_CLKCTL_SET_4(_pinfo, _val, _mask) \ + BPMU_CLKCTL_WRITE_4((_pinfo), \ + ((_val) & (_mask)) | (BPMU_CLKCTL_READ_4(_pinfo) & ~(_mask))) + +/** + * Default bhnd_pmu driver implementation of DEVICE_PROBE(). + */ +int +bhnd_pmu_probe(device_t dev) +{ + return (BUS_PROBE_DEFAULT); +} + +/** + * Default bhnd_pmu driver implementation of DEVICE_ATTACH(). + * + * @param dev PMU device. + * @param res The PMU device registers. The driver will maintain a borrowed + * reference to this resource for the lifetime of the device. + */ +int +bhnd_pmu_attach(device_t dev, struct bhnd_resource *res) +{ + struct bhnd_pmu_softc *sc; + struct sysctl_ctx_list *ctx; + struct sysctl_oid *tree; + devclass_t bhnd_class; + device_t core, bus; + int error; + + sc = device_get_softc(dev); + sc->dev = dev; + sc->quirks = 0; + sc->res = res; + + /* Fetch capability flags */ + sc->caps = bhnd_bus_read_4(sc->res, BHND_PMU_CAP); + + /* Find the bus-attached core */ + bhnd_class = devclass_find("bhnd"); + core = sc->dev; + while ((bus = device_get_parent(core)) != NULL) { + if (device_get_devclass(bus) == bhnd_class) + break; + + core = bus; + } + + if (core == NULL) { + device_printf(sc->dev, "bhnd bus not found\n"); + return (ENXIO); + } + + /* Fetch chip and board info */ + sc->cid = *bhnd_get_chipid(core); + + if ((error = bhnd_read_board_info(core, &sc->board))) { + device_printf(sc->dev, "error fetching board info: %d\n", + error); + return (ENXIO); + } + + /* Locate ChipCommon device */ + sc->chipc_dev = bhnd_find_child(bus, BHND_DEVCLASS_CC, 0); + if (sc->chipc_dev == NULL) { + device_printf(sc->dev, "chipcommon device not found\n"); + return (ENXIO); + } + + BPMU_LOCK_INIT(sc); + + /* Set quirk flags */ + switch (sc->cid.chip_id) { + case BHND_CHIPID_BCM4328: + case BHND_CHIPID_BCM5354: + /* HTAVAIL/ALPAVAIL are bitswapped in CLKCTL */ + sc->quirks |= BPMU_QUIRK_CLKCTL_CCS0; + break; + default: + break; + } + + /* Initialize PMU */ + if ((error = bhnd_pmu_init(sc))) { + device_printf(sc->dev, "PMU init failed: %d\n", error); + goto failed; + } + + /* Set up sysctl nodes */ + ctx = device_get_sysctl_ctx(dev); + tree = device_get_sysctl_tree(dev); + + SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, + "bus_freq", CTLTYPE_UINT | CTLFLAG_RD, sc, 0, + bhnd_pmu_sysctl_bus_freq, "IU", "Bus clock frequency"); + + SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, + "cpu_freq", CTLTYPE_UINT | CTLFLAG_RD, sc, 0, + bhnd_pmu_sysctl_cpu_freq, "IU", "CPU clock frequency"); + + SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, + "mem_freq", CTLTYPE_UINT | CTLFLAG_RD, sc, 0, + bhnd_pmu_sysctl_mem_freq, "IU", "Memory clock frequency"); + + return (0); + +failed: + BPMU_LOCK_DESTROY(sc); + return (error); +} + +/** + * Default bhnd_pmu driver implementation of DEVICE_DETACH(). + */ +int +bhnd_pmu_detach(device_t dev) +{ + struct bhnd_pmu_softc *sc; + + sc = device_get_softc(dev); + + BPMU_LOCK_DESTROY(sc); + + return (0); +} + +/** + * Default bhnd_pmu driver implementation of DEVICE_SUSPEND(). + */ +int +bhnd_pmu_suspend(device_t dev) +{ + return (0); +} + +/** + * Default bhnd_pmu driver implementation of DEVICE_RESUME(). + */ +int +bhnd_pmu_resume(device_t dev) +{ + struct bhnd_pmu_softc *sc; + int error; + + sc = device_get_softc(dev); + + /* Re-initialize PMU */ + if ((error = bhnd_pmu_init(sc))) { + device_printf(sc->dev, "PMU init failed: %d\n", error); + return (error); + } + + return (0); +} + +static int +bhnd_pmu_sysctl_bus_freq(SYSCTL_HANDLER_ARGS) +{ + struct bhnd_pmu_softc *sc; + uint32_t freq; + + sc = arg1; + + BPMU_LOCK(sc); + freq = bhnd_pmu_si_clock(sc); + BPMU_UNLOCK(sc); + + return (sysctl_handle_32(oidp, NULL, freq, req)); +} + +static int +bhnd_pmu_sysctl_cpu_freq(SYSCTL_HANDLER_ARGS) +{ + struct bhnd_pmu_softc *sc; + uint32_t freq; + + sc = arg1; + + BPMU_LOCK(sc); + freq = bhnd_pmu_cpu_clock(sc); + BPMU_UNLOCK(sc); + + return (sysctl_handle_32(oidp, NULL, freq, req)); +} + +static int +bhnd_pmu_sysctl_mem_freq(SYSCTL_HANDLER_ARGS) +{ + struct bhnd_pmu_softc *sc; + uint32_t freq; + + sc = arg1; + + BPMU_LOCK(sc); + freq = bhnd_pmu_mem_clock(sc); + BPMU_UNLOCK(sc); + + return (sysctl_handle_32(oidp, NULL, freq, req)); +} + +static int +bhnd_pmu_core_req_clock(device_t dev, struct bhnd_core_pmu_info *pinfo, + bhnd_clock clock) +{ + struct bhnd_pmu_softc *sc; + uint32_t avail; + uint32_t req; + + sc = device_get_softc(dev); + + avail = 0x0; + req = 0x0; + + switch (clock) { + case BHND_CLOCK_DYN: + break; + case BHND_CLOCK_ILP: + req |= BHND_CCS_FORCEILP; + break; + case BHND_CLOCK_ALP: + req |= BHND_CCS_FORCEALP; + avail |= BHND_CCS_ALPAVAIL; + break; + case BHND_CLOCK_HT: + req |= BHND_CCS_FORCEHT; + avail |= BHND_CCS_HTAVAIL; + break; + default: + device_printf(dev, "%s requested unknown clock: %#x\n", + device_get_nameunit(pinfo->pm_dev), clock); + return (ENODEV); + } + + BPMU_LOCK(sc); + + /* Issue request */ + BPMU_CLKCTL_SET_4(pinfo, req, BHND_CCS_FORCE_MASK); + + /* Wait for clock availability */ + bhnd_pmu_wait_clkst(sc, pinfo->pm_dev, pinfo->pm_res, pinfo->pm_regs, + avail, avail); + + BPMU_UNLOCK(sc); + + return (0); +} + +static int +bhnd_pmu_core_en_clocks(device_t dev, struct bhnd_core_pmu_info *pinfo, + uint32_t clocks) +{ + struct bhnd_pmu_softc *sc; + uint32_t avail; + uint32_t req; + + sc = device_get_softc(dev); + + avail = 0x0; + req = 0x0; + + /* Build clock request flags */ + if (clocks & BHND_CLOCK_DYN) /* nothing to enable */ + clocks &= ~BHND_CLOCK_DYN; + + if (clocks & BHND_CLOCK_ILP) /* nothing to enable */ + clocks &= ~BHND_CLOCK_ILP; + + if (clocks & BHND_CLOCK_ALP) { + req |= BHND_CCS_ALPAREQ; + avail |= BHND_CCS_ALPAVAIL; + clocks &= ~BHND_CLOCK_ALP; + } + + if (clocks & BHND_CLOCK_HT) { + req |= BHND_CCS_HTAREQ; + avail |= BHND_CCS_HTAVAIL; + clocks &= ~BHND_CLOCK_HT; + } + + /* Check for unknown clock values */ + if (clocks != 0x0) { + device_printf(dev, "%s requested unknown clocks: %#x\n", + device_get_nameunit(pinfo->pm_dev), clocks); + return (ENODEV); + } + + BPMU_LOCK(sc); + + /* Issue request */ + BPMU_CLKCTL_SET_4(pinfo, req, BHND_CCS_AREQ_MASK); + + /* Wait for clock availability */ + bhnd_pmu_wait_clkst(sc, pinfo->pm_dev, pinfo->pm_res, pinfo->pm_regs, + avail, avail); + + BPMU_UNLOCK(sc); + + return (0); +} + +static int +bhnd_pmu_core_req_ext_rsrc(device_t dev, struct bhnd_core_pmu_info *pinfo, + u_int rsrc) +{ + struct bhnd_pmu_softc *sc; + uint32_t req; + uint32_t avail; + + sc = device_get_softc(dev); + + if (rsrc > BHND_CCS_ERSRC_MAX) + return (EINVAL); + + req = BHND_PMU_SET_BITS((1<pm_dev, pinfo->pm_res, pinfo->pm_regs, + avail, avail); + + BPMU_UNLOCK(sc); + + return (0); +} + +static int +bhnd_pmu_core_release_ext_rsrc(device_t dev, struct bhnd_core_pmu_info *pinfo, + u_int rsrc) +{ + struct bhnd_pmu_softc *sc; + uint32_t mask; + + sc = device_get_softc(dev); + + if (rsrc > BHND_CCS_ERSRC_MAX) + return (EINVAL); + + mask = BHND_PMU_SET_BITS((1< + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ + +#ifndef _BHND_CORES_PMU_BHND_PMU_H_ +#define _BHND_CORES_PMU_BHND_PMU_H_ + +#include + +#include "bhnd_pmu_if.h" + +/** + * Per-core PMU register information. + */ +struct bhnd_core_pmu_info { + device_t pm_dev; /**< core device */ + device_t pm_pmu; /**< PMU device */ + struct bhnd_resource *pm_res; /**< Resource containing PMU + register block for this + device (if any). */ + bus_size_t pm_regs; /**< Offset to PMU register + * block in @p pm_res */ +}; + +#endif /* _BHND_CORES_PMU_BHND_PMU_H_ */ Property changes on: head/sys/dev/bhnd/cores/pmu/bhnd_pmu.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/bhnd/cores/pmu/bhnd_pmu_core.c =================================================================== --- head/sys/dev/bhnd/cores/pmu/bhnd_pmu_core.c (nonexistent) +++ head/sys/dev/bhnd/cores/pmu/bhnd_pmu_core.c (revision 304870) @@ -0,0 +1,138 @@ +/*- + * Copyright (c) 2015-2016 Landon Fuller + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include "bhnd_pmureg.h" +#include "bhnd_pmuvar.h" + +/* + * PMU core driver. + */ + +/* Supported device identifiers */ +static const struct bhnd_device bhnd_pmucore_devices[] = { + BHND_DEVICE(BCM, PMU, NULL, NULL), + + BHND_DEVICE_END +}; + +static int +bhnd_pmu_core_probe(device_t dev) +{ + const struct bhnd_device *id; + int error; + + id = bhnd_device_lookup(dev, bhnd_pmucore_devices, + sizeof(bhnd_pmucore_devices[0])); + if (id == NULL) + return (ENXIO); + + /* Delegate to common driver implementation */ + if ((error = bhnd_pmu_probe(dev)) > 0) + return (error); + + bhnd_set_default_core_desc(dev); + return (BUS_PROBE_DEFAULT); +} + +static int +bhnd_pmu_core_attach(device_t dev) +{ + struct bhnd_pmu_softc *sc; + struct bhnd_resource *res; + int error; + int rid; + + sc = device_get_softc(dev); + + /* Allocate register block */ + rid = 0; + res = bhnd_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); + if (res == NULL) { + device_printf(dev, "failed to allocate resources\n"); + return (ENXIO); + } + + /* Delegate to common driver implementation */ + if ((error = bhnd_pmu_attach(dev, res))) { + bhnd_release_resource(dev, SYS_RES_MEMORY, rid, res); + return (error); + } + + sc->rid = rid; + return (0); +} + +static int +bhnd_pmu_core_detach(device_t dev) +{ + struct bhnd_pmu_softc *sc; + int error; + + sc = device_get_softc(dev); + + /* Delegate to common driver implementation */ + if ((error = bhnd_pmu_detach(dev))) + return (error); + + bhnd_release_resource(dev, SYS_RES_MEMORY, sc->rid, sc->res); + return (0); +} + +static device_method_t bhnd_pmucore_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, bhnd_pmu_core_probe), + DEVMETHOD(device_attach, bhnd_pmu_core_attach), + DEVMETHOD(device_detach, bhnd_pmu_core_detach), + + DEVMETHOD_END +}; + +DEFINE_CLASS_1(bhnd_pmu, bhnd_pmucore_driver, bhnd_pmucore_methods, + sizeof(struct bhnd_pmu_softc), bhnd_pmu_driver); +EARLY_DRIVER_MODULE(bhnd_pmu, bhnd, bhnd_pmucore_driver, bhnd_pmu_devclass, + NULL, NULL, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); + +MODULE_DEPEND(bhnd_pmu_core, bhnd_pmu, 1, 1, 1); +MODULE_VERSION(bhnd_pmu_core, 1); Property changes on: head/sys/dev/bhnd/cores/pmu/bhnd_pmu_core.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/bhnd/cores/pmu/bhnd_pmu_if.m =================================================================== --- head/sys/dev/bhnd/cores/pmu/bhnd_pmu_if.m (nonexistent) +++ head/sys/dev/bhnd/cores/pmu/bhnd_pmu_if.m (revision 304870) @@ -0,0 +1,130 @@ +#- +# Copyright (c) 2016 Landon Fuller +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# $FreeBSD$ + +#include +#include + +#include + +INTERFACE bhnd_pmu; + +# +# bhnd(4) PMU interface. +# +# Provides a common PMU and clock control interface. +# + +HEADER { + struct bhnd_core_pmu_info; +} + +/** + * Enabling routing of @p clock (or faster) to a requesting core. + * + * @param dev PMU device. + * @param pinfo PMU info for requesting core. + * @param clock Clock requested. + * + * @retval 0 success + * @retval ENODEV If an unsupported clock was requested. + */ +METHOD int core_req_clock { + device_t dev; + struct bhnd_core_pmu_info *pinfo; + bhnd_clock clock; +}; + + +/** + * Request that @p clocks be powered on behalf of a requesting core. + * + * This will power any clock sources (XTAL, PLL, etc,) required by + * @p clocks and wait until they are ready, discarding any previous + * requests from the @p pinfo device. + * + * Requests from multiple devices are aggregated by the PMU. + * + * @param dev PMU device. + * @param pinfo PMU info for requesting core. + * @param clocks Clocks requested. + * + * @retval 0 success + * @retval ENODEV If an unsupported clock was requested. + */ +METHOD int core_en_clocks { + device_t dev; + struct bhnd_core_pmu_info *pinfo; + uint32_t clocks; +}; + +/** + * Power up a core-specific external resource. + * + * @param dev The parent of @p child. + * @param pinfo PMU info for requesting core. + * @param rsrc The core-specific external resource identifier. + * + * @retval 0 success + * @retval ENODEV If @p rsrc is not supported by this PMU driver. + */ +METHOD int core_req_ext_rsrc { + device_t dev; + struct bhnd_core_pmu_info *pinfo; + u_int rsrc; +}; + +/** + * Power down a core-specific external resource. + * + * @param dev The parent of @p child. + * @param pinfo PMU info for requesting core. + * @param rsrc The core-specific external resource identifier. + * + * @retval 0 success + * @retval ENODEV If @p rsrc is not supported by this PMU driver. + */ +METHOD int core_release_ext_rsrc { + device_t dev; + struct bhnd_core_pmu_info *pinfo; + u_int rsrc; +}; + +/** + * Release all outstanding requests (clocks, resources, etc) associated with + * @p pinfo. + * + * @param dev PMU device. + * @param pinfo PMU info for requesting core. + * + * @retval 0 success + * @retval non-zero If releasing PMU request state fails, a + * regular unix error code will be returned, and + * the request state will be left unmodified. + */ +METHOD int core_release { + device_t dev; + struct bhnd_core_pmu_info *pinfo; +}; Property changes on: head/sys/dev/bhnd/cores/pmu/bhnd_pmu_if.m ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/bhnd/cores/pmu/bhnd_pmu_private.h =================================================================== --- head/sys/dev/bhnd/cores/pmu/bhnd_pmu_private.h (nonexistent) +++ head/sys/dev/bhnd/cores/pmu/bhnd_pmu_private.h (revision 304870) @@ -0,0 +1,147 @@ +/*- + * Copyright (c) 2016 Landon Fuller + * Copyright (C) 2010, Broadcom Corporation. + * All rights reserved. + * + * This file is derived from the hndpmu.h header contributed by Broadcom + * to to the Linux staging repository, as well as later revisions of hndpmu.h + * distributed with the Asus RT-N16 firmware source code release. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $FreeBSD$ + */ + +#ifndef _BHND_CORES_PMU_BHND_PMU_PRIVATE_H_ +#define _BHND_CORES_PMU_BHND_PMU_PRIVATE_H_ + +#include + +#include "bhnd_pmuvar.h" + +/* Register I/O */ +#define BHND_PMU_READ_1(_sc, _reg) bhnd_bus_read_1((_sc)->res, (_reg)) +#define BHND_PMU_READ_2(_sc, _reg) bhnd_bus_read_2((_sc)->res, (_reg)) +#define BHND_PMU_READ_4(_sc, _reg) bhnd_bus_read_4((_sc)->res, (_reg)) +#define BHND_PMU_WRITE_1(_sc, _reg, _val) \ + bhnd_bus_write_1((_sc)->res, (_reg), (_val)) +#define BHND_PMU_WRITE_2(_sc, _reg, _val) \ + bhnd_bus_write_2((_sc)->res, (_reg), (_val)) +#define BHND_PMU_WRITE_4(_sc, _reg, _val) \ + bhnd_bus_write_4((_sc)->res, (_reg), (_val)) + +#define BHND_PMU_AND_4(_sc, _reg, _val) \ + BHND_PMU_WRITE_4((_sc), (_reg), \ + BHND_PMU_READ_4((_sc), (_reg)) & (_val)) +#define BHND_PMU_OR_4(_sc, _reg, _val) \ + BHND_PMU_WRITE_4((_sc), (_reg), \ + BHND_PMU_READ_4((_sc), (_reg)) | (_val)) + +/* Indirect register support */ +#define BHND_PMU_IND_READ(_sc, _src, _reg) \ + bhnd_pmu_ind_read((_sc), BHND_PMU_ ## _src ## _ADDR, \ + BHND_PMU_ ## _src ## _DATA, (_reg)) +#define BHND_PMU_IND_WRITE(_sc, _src, _reg, _val, _mask) \ + bhnd_pmu_ind_write(sc, BHND_PMU_ ## _src ## _ADDR, \ + BHND_PMU_ ## _src ## _DATA, (_reg), (_val), (_mask)) + +/* Chip Control indirect registers */ +#define BHND_PMU_CCTRL_READ(_sc, _reg) \ + BHND_PMU_IND_READ((_sc), CHIPCTL, (_reg)) +#define BHND_PMU_CCTRL_WRITE(_sc, _reg, _val, _mask) \ + BHND_PMU_IND_WRITE((_sc), CHIPCTL, (_reg), (_val), (_mask)) + +/* Register Control indirect registers */ +#define BHND_PMU_REGCTRL_READ(_sc, _reg) \ + BHND_PMU_IND_READ((_sc), REG_CONTROL, (_reg)) +#define BHND_PMU_REGCTRL_WRITE(_sc, _reg, _val, _mask) \ + BHND_PMU_IND_WRITE((_sc), REG_CONTROL, (_reg), (_val), (_mask)) + +/* PLL Control indirect registers */ +#define BHND_PMU_PLL_READ(_sc, _reg) \ + BHND_PMU_IND_READ((_sc), PLL_CONTROL, (_reg)) +#define BHND_PMU_PLL_WRITE(_sc, _reg, _val, _mask) \ + BHND_PMU_IND_WRITE((_sc), PLL_CONTROL, (_reg), (_val), (_mask)) + + +/** FVCO frequencies, in Hz */ +enum { + FVCO_880 = 880 * 1000, /**< 880MHz */ + FVCO_1760 = 1760 * 1000, /**< 1760MHz */ + FVCO_1440 = 1440 * 1000, /**< 1440MHz */ + FVCO_960 = 960 * 1000, /**< 960MHz */ +}; + +/** LDO voltage tunables */ +enum { + SET_LDO_VOLTAGE_LDO1 = 1, + SET_LDO_VOLTAGE_LDO2 = 2, + SET_LDO_VOLTAGE_LDO3 = 3, + SET_LDO_VOLTAGE_PAREF = 4, + SET_LDO_VOLTAGE_CLDO_PWM = 5, + SET_LDO_VOLTAGE_CLDO_BURST = 6, + SET_LDO_VOLTAGE_CBUCK_PWM = 7, + SET_LDO_VOLTAGE_CBUCK_BURST = 8, + SET_LDO_VOLTAGE_LNLDO1 = 9, + SET_LDO_VOLTAGE_LNLDO2_SEL = 10, +}; + +uint32_t bhnd_pmu_ind_read(struct bhnd_pmu_softc *sc, bus_size_t addr, + bus_size_t data, uint32_t reg); +void bhnd_pmu_ind_write(struct bhnd_pmu_softc *sc, bus_size_t addr, + bus_size_t data, uint32_t reg, uint32_t val, uint32_t mask); + +bool bhnd_pmu_wait_clkst(struct bhnd_pmu_softc *sc, device_t dev, + struct bhnd_resource *r, bus_size_t clkst_reg, + uint32_t value, uint32_t mask); + +int bhnd_pmu_init(struct bhnd_pmu_softc *sc); +void bhnd_pmu_pll_init(struct bhnd_pmu_softc *sc, uint32_t xtalfreq); +int bhnd_pmu_res_init(struct bhnd_pmu_softc *sc); +void bhnd_pmu_swreg_init(struct bhnd_pmu_softc *sc); + +uint32_t bhnd_pmu_force_ilp(struct bhnd_pmu_softc *sc, bool force); + +uint32_t bhnd_pmu_si_clock(struct bhnd_pmu_softc *sc); +uint32_t bhnd_pmu_cpu_clock(struct bhnd_pmu_softc *sc); +uint32_t bhnd_pmu_mem_clock(struct bhnd_pmu_softc *sc); +uint32_t bhnd_pmu_alp_clock(struct bhnd_pmu_softc *sc); +uint32_t bhnd_pmu_ilp_clock(struct bhnd_pmu_softc *sc); + +void bhnd_pmu_set_switcher_voltage(struct bhnd_pmu_softc *sc, + uint8_t bb_voltage, uint8_t rf_voltage); +void bhnd_pmu_set_ldo_voltage(struct bhnd_pmu_softc *sc, + uint8_t ldo, uint8_t voltage); +int bhnd_pmu_fast_pwrup_delay(struct bhnd_pmu_softc *sc, + uint16_t *pwrup_delay); +void bhnd_pmu_rcal(struct bhnd_pmu_softc *sc); +void bhnd_pmu_spuravoid(struct bhnd_pmu_softc *sc, + uint8_t spuravoid); + +bool bhnd_pmu_is_otp_powered(struct bhnd_pmu_softc *sc); +uint32_t bhnd_pmu_measure_alpclk(struct bhnd_pmu_softc *sc); + +void bhnd_pmu_radio_enable(struct bhnd_pmu_softc *sc, + device_t d11core, bool enable); + +uint32_t bhnd_pmu_waitforclk_on_backplane(struct bhnd_pmu_softc *sc, + uint32_t clk, uint32_t delay); + +int bhnd_pmu_otp_power(struct bhnd_pmu_softc *sc, bool on); +void bhnd_pmu_sdiod_drive_strength_init(struct bhnd_pmu_softc *sc, + uint32_t drivestrength); + +void bhnd_pmu_paref_ldo_enable(struct bhnd_pmu_softc *sc, + bool enable); + +#endif /* _BHND_CORES_PMU_BHND_PMU_PRIVATE_H_ */ Property changes on: head/sys/dev/bhnd/cores/pmu/bhnd_pmu_private.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c =================================================================== --- head/sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c (nonexistent) +++ head/sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c (revision 304870) @@ -0,0 +1,3446 @@ +/*- + * Copyright (c) 2016 Landon Fuller + * Copyright (C) 2010, Broadcom Corporation. + * All rights reserved. + * + * This file is derived from the hndpmu.c source contributed by Broadcom + * to to the Linux staging repository, as well as later revisions of hndpmu.c + * distributed with the Asus RT-N16 firmware source code release. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include + +#include +#include +#include + +#include + +#include "bhnd_nvram_map.h" + +#include "bhnd_pmureg.h" +#include "bhnd_pmuvar.h" + +#include "bhnd_pmu_private.h" + +#ifdef BCMDBG +#define PMU_MSG(args) printf args +#define PMU_ERROR(args) do { \ + panic args; \ +} while (0) +#else +#define PMU_MSG(args) +#define PMU_ERROR(args) printf args +#endif + +typedef struct pmu0_xtaltab0 pmu0_xtaltab0_t; +typedef struct pmu1_xtaltab0 pmu1_xtaltab0_t; + +/* PLL controls/clocks */ +static const pmu1_xtaltab0_t *bhnd_pmu1_xtaltab0(struct bhnd_pmu_softc *sc); +static const pmu1_xtaltab0_t *bhnd_pmu1_xtaldef0(struct bhnd_pmu_softc *sc); + +static void bhnd_pmu0_pllinit0(struct bhnd_pmu_softc *sc, uint32_t xtal); +static uint32_t bhnd_pmu0_cpuclk0(struct bhnd_pmu_softc *sc); +static uint32_t bhnd_pmu0_alpclk0(struct bhnd_pmu_softc *sc); + +static void bhnd_pmu1_pllinit0(struct bhnd_pmu_softc *sc, uint32_t xtal); +static uint32_t bhnd_pmu1_pllfvco0(struct bhnd_pmu_softc *sc); +static uint32_t bhnd_pmu1_cpuclk0(struct bhnd_pmu_softc *sc); +static uint32_t bhnd_pmu1_alpclk0(struct bhnd_pmu_softc *sc); + +static uint32_t bhnd_pmu5_clock(struct bhnd_pmu_softc *sc, u_int pll0, u_int m); + +/* PMU resources */ +static bool bhnd_pmu_res_depfltr_bb(struct bhnd_pmu_softc *sc); +static bool bhnd_pmu_res_depfltr_ncb(struct bhnd_pmu_softc *sc); +static bool bhnd_pmu_res_depfltr_paldo(struct bhnd_pmu_softc *sc); +static bool bhnd_pmu_res_depfltr_npaldo(struct bhnd_pmu_softc *sc); +static uint32_t bhnd_pmu_res_deps(struct bhnd_pmu_softc *sc, uint32_t rsrcs, + bool all); +static int bhnd_pmu_res_uptime(struct bhnd_pmu_softc *sc, uint8_t rsrc, + uint32_t *uptime); +static int bhnd_pmu_res_masks(struct bhnd_pmu_softc *sc, uint32_t *pmin, + uint32_t *pmax); + +static void bhnd_pmu_spuravoid_pllupdate(struct bhnd_pmu_softc *sc, + uint8_t spuravoid); +static void bhnd_pmu_set_4330_plldivs(struct bhnd_pmu_softc *sc); + +#define BHND_PMU_REV(_sc) \ + ((uint8_t)BHND_PMU_GET_BITS((_sc)->caps, BHND_PMU_CAP_REV)) + +#define PMU_WAIT_CLKST(_sc, _val, _mask) \ + bhnd_pmu_wait_clkst((_sc), (_sc)->dev, (_sc)->res, \ + BHND_CLK_CTL_ST, (_val), (_mask)) + +#define PMURES_BIT(_bit) \ + (1 << (BHND_PMU_ ## _bit)) + +#define PMU_CST4330_SDIOD_CHIPMODE(_sc) \ + CHIPC_CST4330_CHIPMODE_SDIOD(BHND_CHIPC_READ_CHIPST((_sc)->chipc_dev)) + +/** + * Perform an indirect register read. + * + * @param addr Offset of the address register. + * @param data Offset of the data register. + * @param reg Indirect register to be read. + */ +uint32_t +bhnd_pmu_ind_read(struct bhnd_pmu_softc *sc, bus_size_t addr, bus_size_t data, + uint32_t reg) +{ + BHND_PMU_WRITE_4(sc, addr, reg); + return (BHND_PMU_READ_4(sc, data)); +} + +/** + * Perform an indirect register write. + * + * @param addr Offset of the address register. + * @param data Offset of the data register. + * @param reg Indirect register to be written. + * @param val Value to be written to @p reg. + * @param mask Only the bits defined by @p mask will be updated from @p val. + */ +void +bhnd_pmu_ind_write(struct bhnd_pmu_softc *sc, bus_size_t addr, + bus_size_t data, uint32_t reg, uint32_t val, uint32_t mask) +{ + uint32_t rval; + + BHND_PMU_WRITE_4(sc, addr, reg); + + if (mask != UINT32_MAX) { + rval = BHND_PMU_READ_4(sc, data); + rval &= ~mask | (val & mask); + } else { + rval = val; + } + + BHND_PMU_WRITE_4(sc, data, rval); +} + +/** + * Wait for up to BHND_PMU_MAX_TRANSITION_DLY microseconds for the per-core + * clock status to be equal to @p value after applying @p mask. + * + * @param sc PMU driver state. + * @param dev Requesting device. + * @param r An active resource mapping the clock status register. + * @param clkst_reg Offset to the CLK_CTL_ST register. + * @param value Value to wait for. + * @param mask Mask to apply prior to value comparison. + */ +bool +bhnd_pmu_wait_clkst(struct bhnd_pmu_softc *sc, device_t dev, + struct bhnd_resource *r, bus_size_t clkst_reg, uint32_t value, + uint32_t mask) +{ + uint32_t clkst; + + /* Bitswapped HTAVAIL/ALPAVAIL work-around */ + if (sc->quirks & BPMU_QUIRK_CLKCTL_CCS0) { + uint32_t fmask, fval; + + fmask = mask & ~(BHND_CCS_HTAVAIL | BHND_CCS_ALPAVAIL); + fval = value & ~(BHND_CCS_HTAVAIL | BHND_CCS_ALPAVAIL); + + if (mask & BHND_CCS_HTAVAIL) + fmask |= BHND_CCS0_HTAVAIL; + if (value & BHND_CCS_HTAVAIL) + fval |= BHND_CCS0_HTAVAIL; + + if (mask & BHND_CCS_ALPAVAIL) + fmask |= BHND_CCS0_ALPAVAIL; + if (value & BHND_CCS_ALPAVAIL) + fval |= BHND_CCS0_ALPAVAIL; + + mask = fmask; + value = fval; + } + + for (uint32_t i = 0; i < BHND_PMU_MAX_TRANSITION_DLY; i += 10) { + clkst = bhnd_bus_read_4(r, clkst_reg); + if ((clkst & mask) == (value & mask)) + return (true); + + DELAY(10); + } + + device_printf(dev, "clkst wait timeout (value=%#x, " + "mask=%#x)\n", value, mask); + + return (false); +} + +/* Setup switcher voltage */ +void +bhnd_pmu_set_switcher_voltage(struct bhnd_pmu_softc *sc, uint8_t bb_voltage, + uint8_t rf_voltage) +{ + BHND_PMU_REGCTRL_WRITE(sc, 0x01, (bb_voltage & 0x1f) << 22, ~0); + BHND_PMU_REGCTRL_WRITE(sc, 0x00, (rf_voltage & 0x1f) << 14, ~0); +} + +void +bhnd_pmu_set_ldo_voltage(struct bhnd_pmu_softc *sc, uint8_t ldo, + uint8_t voltage) +{ + uint32_t chipst; + uint32_t regctrl; + uint8_t shift; + uint8_t mask; + uint8_t addr; + + switch (sc->cid.chip_id) { + case BHND_CHIPID_BCM4328: + case BHND_CHIPID_BCM5354: + switch (ldo) { + case SET_LDO_VOLTAGE_LDO1: + addr = 2; + shift = 17 + 8; + mask = 0xf; + break; + case SET_LDO_VOLTAGE_LDO2: + addr = 3; + shift = 1; + mask = 0xf; + break; + case SET_LDO_VOLTAGE_LDO3: + addr = 3; + shift = 9; + mask = 0xf; + break; + case SET_LDO_VOLTAGE_PAREF: + addr = 3; + shift = 17; + mask = 0x3f; + break; + default: + panic("unknown BCM4328/BCM5354 LDO %hhu\n", ldo); + } + break; + case BHND_CHIPID_BCM4312: + switch (ldo) { + case SET_LDO_VOLTAGE_PAREF: + addr = 0; + shift = 21; + mask = 0x3f; + break; + default: + panic("unknown BCM4312 LDO %hhu\n", ldo); + } + break; + case BHND_CHIPID_BCM4325: + switch (ldo) { + case SET_LDO_VOLTAGE_CLDO_PWM: + addr = 5; + shift = 9; + mask = 0xf; + break; + case SET_LDO_VOLTAGE_CLDO_BURST: + addr = 5; + shift = 13; + mask = 0xf; + break; + case SET_LDO_VOLTAGE_CBUCK_PWM: + addr = 3; + shift = 20; + mask = 0x1f; + /* Bit 116 & 119 are inverted in CLB for opt 2b */ + chipst = BHND_CHIPC_READ_CHIPST(sc->chipc_dev); + if (BHND_PMU_GET_BITS(chipst, CHIPC_CST4325_PMUTOP_2B)) + voltage ^= 0x9; + break; + case SET_LDO_VOLTAGE_CBUCK_BURST: + addr = 3; + shift = 25; + mask = 0x1f; + /* Bit 121 & 124 are inverted in CLB for opt 2b */ + chipst = BHND_CHIPC_READ_CHIPST(sc->chipc_dev); + if (BHND_PMU_GET_BITS(chipst, CHIPC_CST4325_PMUTOP_2B)) + voltage ^= 0x9; + break; + case SET_LDO_VOLTAGE_LNLDO1: + addr = 5; + shift = 17; + mask = 0x1f; + break; + case SET_LDO_VOLTAGE_LNLDO2_SEL: + addr = 6; + shift = 0; + mask = 0x1; + break; + default: + panic("unknown BCM4325 LDO %hhu\n", ldo); + } + break; + case BHND_CHIPID_BCM4336: + switch (ldo) { + case SET_LDO_VOLTAGE_CLDO_PWM: + addr = 4; + shift = 1; + mask = 0xf; + break; + case SET_LDO_VOLTAGE_CLDO_BURST: + addr = 4; + shift = 5; + mask = 0xf; + break; + case SET_LDO_VOLTAGE_LNLDO1: + addr = 4; + shift = 17; + mask = 0xf; + break; + default: + panic("unknown BCM4336 LDO %hhu\n", ldo); + } + break; + case BHND_CHIPID_BCM4330: + switch (ldo) { + case SET_LDO_VOLTAGE_CBUCK_PWM: + addr = 3; + shift = 0; + mask = 0x1f; + break; + default: + panic("unknown BCM4330 LDO %hhu\n", ldo); + } + break; + case BHND_CHIPID_BCM4331: + switch (ldo) { + case SET_LDO_VOLTAGE_PAREF: + addr = 1; + shift = 0; + mask = 0xf; + break; + default: + panic("unknown BCM4331 LDO %hhu\n", ldo); + } + break; + default: + panic("cannot set LDO voltage on unsupported chip %hu\n", + sc->cid.chip_id); + return; + } + + regctrl = (voltage & mask) << shift; + BHND_PMU_REGCTRL_WRITE(sc, addr, regctrl, mask << shift); +} + +/* d11 slow to fast clock transition time in slow clock cycles */ +#define D11SCC_SLOW2FAST_TRANSITION 2 + +int +bhnd_pmu_fast_pwrup_delay(struct bhnd_pmu_softc *sc, uint16_t *pwrup_delay) +{ + uint32_t ilp; + uint32_t uptime; + u_int delay; + int error; + + switch (sc->cid.chip_id) { + case BHND_CHIPID_BCM43224: + case BHND_CHIPID_BCM43225: + case BHND_CHIPID_BCM43421: + case BHND_CHIPID_BCM43235: + case BHND_CHIPID_BCM43236: + case BHND_CHIPID_BCM43238: + case BHND_CHIPID_BCM4331: + case BHND_CHIPID_BCM6362: + case BHND_CHIPID_BCM4313: + delay = 3700; + break; + + case BHND_CHIPID_BCM4325: + error = bhnd_pmu_res_uptime(sc, BHND_PMU_RES4325_HT_AVAIL, + &uptime); + if (error) + return (error); + + ilp = bhnd_pmu_ilp_clock(sc); + delay = (uptime + D11SCC_SLOW2FAST_TRANSITION) * + ((1000000 + ilp - 1) / ilp); + delay = (11 * delay) / 10; + break; + + case BHND_CHIPID_BCM4329: + error = bhnd_pmu_res_uptime(sc, BHND_PMU_RES4329_HT_AVAIL, + &uptime); + if (error) + return (error); + + ilp = bhnd_pmu_ilp_clock(sc); + delay = (uptime + D11SCC_SLOW2FAST_TRANSITION) * + ((1000000 + ilp - 1) / ilp); + delay = (11 * delay) / 10; + break; + + case BHND_CHIPID_BCM4319: + delay = 3700; + break; + + case BHND_CHIPID_BCM4336: + error = bhnd_pmu_res_uptime(sc, BHND_PMU_RES4336_HT_AVAIL, + &uptime); + if (error) + return (error); + + ilp = bhnd_pmu_ilp_clock(sc); + delay = (uptime + D11SCC_SLOW2FAST_TRANSITION) * + ((1000000 + ilp - 1) / ilp); + delay = (11 * delay) / 10; + break; + + case BHND_CHIPID_BCM4330: + error = bhnd_pmu_res_uptime(sc, BHND_PMU_RES4330_HT_AVAIL, + &uptime); + if (error) + return (error); + + ilp = bhnd_pmu_ilp_clock(sc); + delay = (uptime + D11SCC_SLOW2FAST_TRANSITION) * + ((1000000 + ilp - 1) / ilp); + delay = (11 * delay) / 10; + break; + + default: + delay = BHND_PMU_MAX_TRANSITION_DLY; + break; + } + + *pwrup_delay = (uint16_t)delay; + return (0); +} + +uint32_t +bhnd_pmu_force_ilp(struct bhnd_pmu_softc *sc, bool force) +{ + uint32_t orig; + uint32_t pctrl; + + pctrl = BHND_PMU_READ_4(sc, BHND_PMU_CTRL); + orig = pctrl; + + if (force) + pctrl &= ~(BHND_PMU_CTRL_HT_REQ_EN | BHND_PMU_CTRL_ALP_REQ_EN); + else + pctrl |= (BHND_PMU_CTRL_HT_REQ_EN | BHND_PMU_CTRL_ALP_REQ_EN); + + BHND_PMU_WRITE_4(sc, BHND_PMU_CTRL, pctrl); + + return (orig); +} + +/* Setup resource up/down timers */ +typedef struct { + uint8_t resnum; + uint16_t updown; +} pmu_res_updown_t; + +typedef bool (*pmu_res_filter) (struct bhnd_pmu_softc *sc); + +/* Change resource dependencies masks */ +typedef struct { + uint32_t res_mask; /* resources (chip specific) */ + int8_t action; /* action */ + uint32_t depend_mask; /* changes to the dependencies mask */ + pmu_res_filter filter; /* action is taken when filter is NULL or returns true */ +} pmu_res_depend_t; + +/* Resource dependencies mask change action */ +#define RES_DEPEND_SET 0 /* Override the dependencies mask */ +#define RES_DEPEND_ADD 1 /* Add to the dependencies mask */ +#define RES_DEPEND_REMOVE -1 /* Remove from the dependencies mask */ + +static const pmu_res_updown_t bcm4328a0_res_updown[] = { + { + BHND_PMU_RES4328_EXT_SWITCHER_PWM, 0x0101}, { + BHND_PMU_RES4328_BB_SWITCHER_PWM, 0x1f01}, { + BHND_PMU_RES4328_BB_SWITCHER_BURST, 0x010f}, { + BHND_PMU_RES4328_BB_EXT_SWITCHER_BURST, 0x0101}, { + BHND_PMU_RES4328_ILP_REQUEST, 0x0202}, { + BHND_PMU_RES4328_RADIO_SWITCHER_PWM, 0x0f01}, { + BHND_PMU_RES4328_RADIO_SWITCHER_BURST, 0x0f01}, { + BHND_PMU_RES4328_ROM_SWITCH, 0x0101}, { + BHND_PMU_RES4328_PA_REF_LDO, 0x0f01}, { + BHND_PMU_RES4328_RADIO_LDO, 0x0f01}, { + BHND_PMU_RES4328_AFE_LDO, 0x0f01}, { + BHND_PMU_RES4328_PLL_LDO, 0x0f01}, { + BHND_PMU_RES4328_BG_FILTBYP, 0x0101}, { + BHND_PMU_RES4328_TX_FILTBYP, 0x0101}, { + BHND_PMU_RES4328_RX_FILTBYP, 0x0101}, { + BHND_PMU_RES4328_XTAL_PU, 0x0101}, { + BHND_PMU_RES4328_XTAL_EN, 0xa001}, { + BHND_PMU_RES4328_BB_PLL_FILTBYP, 0x0101}, { + BHND_PMU_RES4328_RF_PLL_FILTBYP, 0x0101}, { + BHND_PMU_RES4328_BB_PLL_PU, 0x0701} +}; + +static const pmu_res_depend_t bcm4328a0_res_depend[] = { + /* Adjust ILP request resource not to force ext/BB switchers into burst mode */ + { + PMURES_BIT(RES4328_ILP_REQUEST), + RES_DEPEND_SET, + PMURES_BIT(RES4328_EXT_SWITCHER_PWM) | + PMURES_BIT(RES4328_BB_SWITCHER_PWM), NULL} +}; + +static const pmu_res_updown_t bcm4325a0_res_updown[] = { + { + BHND_PMU_RES4325_XTAL_PU, 0x1501} +}; + +static const pmu_res_depend_t bcm4325a0_res_depend[] = { + /* Adjust OTP PU resource dependencies - remove BB BURST */ + { + PMURES_BIT(RES4325_OTP_PU), + RES_DEPEND_REMOVE, + PMURES_BIT(RES4325_BUCK_BOOST_BURST), NULL}, + /* Adjust ALP/HT Avail resource dependencies - bring up BB along if it is used. */ + { + PMURES_BIT(RES4325_ALP_AVAIL) | PMURES_BIT(RES4325_HT_AVAIL), + RES_DEPEND_ADD, + PMURES_BIT(RES4325_BUCK_BOOST_BURST) | + PMURES_BIT(RES4325_BUCK_BOOST_PWM), bhnd_pmu_res_depfltr_bb}, + /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */ + { + PMURES_BIT(RES4325_HT_AVAIL), + RES_DEPEND_ADD, + PMURES_BIT(RES4325_RX_PWRSW_PU) | + PMURES_BIT(RES4325_TX_PWRSW_PU) | + PMURES_BIT(RES4325_LOGEN_PWRSW_PU) | + PMURES_BIT(RES4325_AFE_PWRSW_PU), NULL}, + /* Adjust ALL resource dependencies - remove CBUCK dependencies if it is not used. */ + { + PMURES_BIT(RES4325_ILP_REQUEST) | + PMURES_BIT(RES4325_ABUCK_BURST) | + PMURES_BIT(RES4325_ABUCK_PWM) | + PMURES_BIT(RES4325_LNLDO1_PU) | + PMURES_BIT(RES4325C1_LNLDO2_PU) | + PMURES_BIT(RES4325_XTAL_PU) | + PMURES_BIT(RES4325_ALP_AVAIL) | + PMURES_BIT(RES4325_RX_PWRSW_PU) | + PMURES_BIT(RES4325_TX_PWRSW_PU) | + PMURES_BIT(RES4325_RFPLL_PWRSW_PU) | + PMURES_BIT(RES4325_LOGEN_PWRSW_PU) | + PMURES_BIT(RES4325_AFE_PWRSW_PU) | + PMURES_BIT(RES4325_BBPLL_PWRSW_PU) | + PMURES_BIT(RES4325_HT_AVAIL), RES_DEPEND_REMOVE, + PMURES_BIT(RES4325B0_CBUCK_LPOM) | + PMURES_BIT(RES4325B0_CBUCK_BURST) | + PMURES_BIT(RES4325B0_CBUCK_PWM), bhnd_pmu_res_depfltr_ncb} +}; + +static const pmu_res_updown_t bcm4315a0_res_updown[] = { + { + BHND_PMU_RES4315_XTAL_PU, 0x2501} +}; + +static const pmu_res_depend_t bcm4315a0_res_depend[] = { + /* Adjust OTP PU resource dependencies - not need PALDO unless write */ + { + PMURES_BIT(RES4315_OTP_PU), + RES_DEPEND_REMOVE, + PMURES_BIT(RES4315_PALDO_PU), bhnd_pmu_res_depfltr_npaldo}, + /* Adjust ALP/HT Avail resource dependencies - bring up PALDO along if it is used. */ + { + PMURES_BIT(RES4315_ALP_AVAIL) | PMURES_BIT(RES4315_HT_AVAIL), + RES_DEPEND_ADD, + PMURES_BIT(RES4315_PALDO_PU), bhnd_pmu_res_depfltr_paldo}, + /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */ + { + PMURES_BIT(RES4315_HT_AVAIL), + RES_DEPEND_ADD, + PMURES_BIT(RES4315_RX_PWRSW_PU) | + PMURES_BIT(RES4315_TX_PWRSW_PU) | + PMURES_BIT(RES4315_LOGEN_PWRSW_PU) | + PMURES_BIT(RES4315_AFE_PWRSW_PU), NULL}, + /* Adjust ALL resource dependencies - remove CBUCK dependencies if it is not used. */ + { + PMURES_BIT(RES4315_CLDO_PU) | PMURES_BIT(RES4315_ILP_REQUEST) | + PMURES_BIT(RES4315_LNLDO1_PU) | + PMURES_BIT(RES4315_OTP_PU) | + PMURES_BIT(RES4315_LNLDO2_PU) | + PMURES_BIT(RES4315_XTAL_PU) | + PMURES_BIT(RES4315_ALP_AVAIL) | + PMURES_BIT(RES4315_RX_PWRSW_PU) | + PMURES_BIT(RES4315_TX_PWRSW_PU) | + PMURES_BIT(RES4315_RFPLL_PWRSW_PU) | + PMURES_BIT(RES4315_LOGEN_PWRSW_PU) | + PMURES_BIT(RES4315_AFE_PWRSW_PU) | + PMURES_BIT(RES4315_BBPLL_PWRSW_PU) | + PMURES_BIT(RES4315_HT_AVAIL), RES_DEPEND_REMOVE, + PMURES_BIT(RES4315_CBUCK_LPOM) | + PMURES_BIT(RES4315_CBUCK_BURST) | + PMURES_BIT(RES4315_CBUCK_PWM), bhnd_pmu_res_depfltr_ncb} +}; + +/* 4329 specific. needs to come back this issue later */ +static const pmu_res_updown_t bcm4329_res_updown[] = { + { + BHND_PMU_RES4329_XTAL_PU, 0x1501} +}; + +static const pmu_res_depend_t bcm4329_res_depend[] = { + /* Adjust HT Avail resource dependencies */ + { + PMURES_BIT(RES4329_HT_AVAIL), + RES_DEPEND_ADD, + PMURES_BIT(RES4329_CBUCK_LPOM) | + PMURES_BIT(RES4329_CBUCK_BURST) | + PMURES_BIT(RES4329_CBUCK_PWM) | + PMURES_BIT(RES4329_CLDO_PU) | + PMURES_BIT(RES4329_PALDO_PU) | + PMURES_BIT(RES4329_LNLDO1_PU) | + PMURES_BIT(RES4329_XTAL_PU) | + PMURES_BIT(RES4329_ALP_AVAIL) | + PMURES_BIT(RES4329_RX_PWRSW_PU) | + PMURES_BIT(RES4329_TX_PWRSW_PU) | + PMURES_BIT(RES4329_RFPLL_PWRSW_PU) | + PMURES_BIT(RES4329_LOGEN_PWRSW_PU) | + PMURES_BIT(RES4329_AFE_PWRSW_PU) | + PMURES_BIT(RES4329_BBPLL_PWRSW_PU), NULL} +}; + +static const pmu_res_updown_t bcm4319a0_res_updown[] = { + { + BHND_PMU_RES4319_XTAL_PU, 0x3f01} +}; + +static const pmu_res_depend_t bcm4319a0_res_depend[] = { + /* Adjust OTP PU resource dependencies - not need PALDO unless write */ + { + PMURES_BIT(RES4319_OTP_PU), + RES_DEPEND_REMOVE, + PMURES_BIT(RES4319_PALDO_PU), bhnd_pmu_res_depfltr_npaldo}, + /* Adjust HT Avail resource dependencies - bring up PALDO along if it is used. */ + { + PMURES_BIT(RES4319_HT_AVAIL), + RES_DEPEND_ADD, + PMURES_BIT(RES4319_PALDO_PU), bhnd_pmu_res_depfltr_paldo}, + /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */ + { + PMURES_BIT(RES4319_HT_AVAIL), + RES_DEPEND_ADD, + PMURES_BIT(RES4319_RX_PWRSW_PU) | + PMURES_BIT(RES4319_TX_PWRSW_PU) | + PMURES_BIT(RES4319_RFPLL_PWRSW_PU) | + PMURES_BIT(RES4319_LOGEN_PWRSW_PU) | + PMURES_BIT(RES4319_AFE_PWRSW_PU), NULL} +}; + +static const pmu_res_updown_t bcm4336a0_res_updown[] = { + { + BHND_PMU_RES4336_HT_AVAIL, 0x0D01} +}; + +static const pmu_res_depend_t bcm4336a0_res_depend[] = { + /* Just a dummy entry for now */ + { + PMURES_BIT(RES4336_RSVD), RES_DEPEND_ADD, 0, NULL} +}; + +static const pmu_res_updown_t bcm4330a0_res_updown[] = { + { + BHND_PMU_RES4330_HT_AVAIL, 0x0e02} +}; + +static const pmu_res_depend_t bcm4330a0_res_depend[] = { + /* Just a dummy entry for now */ + { + PMURES_BIT(RES4330_HT_AVAIL), RES_DEPEND_ADD, 0, NULL} +}; + +/* true if the power topology uses the buck boost to provide 3.3V to VDDIO_RF + * and WLAN PA */ +static bool +bhnd_pmu_res_depfltr_bb(struct bhnd_pmu_softc *sc) +{ + return (BHND_PMU_GET_FLAG(sc->board.board_flags, BHND_BFL_BUCKBOOST)); +} + +/* true if the power topology doesn't use the cbuck. Key on chiprev also if + * the chip is BCM4325. */ +static bool +bhnd_pmu_res_depfltr_ncb(struct bhnd_pmu_softc *sc) +{ + if (sc->cid.chip_id == BHND_CHIPID_BCM4325 && sc->cid.chip_rev <= 1) + return (false); + + return (BHND_PMU_GET_FLAG(sc->board.board_flags, BHND_BFL_NOCBUCK)); +} + +/* true if the power topology uses the PALDO */ +static bool +bhnd_pmu_res_depfltr_paldo(struct bhnd_pmu_softc *sc) +{ + return (BHND_PMU_GET_FLAG(sc->board.board_flags, BHND_BFL_PALDO)); +} + +/* true if the power topology doesn't use the PALDO */ +static bool +bhnd_pmu_res_depfltr_npaldo(struct bhnd_pmu_softc *sc) +{ + return (!BHND_PMU_GET_FLAG(sc->board.board_flags, BHND_BFL_PALDO)); +} + +/* Determine min/max rsrc masks. Value 0 leaves hardware at default. */ +static int +bhnd_pmu_res_masks(struct bhnd_pmu_softc *sc, uint32_t *pmin, uint32_t *pmax) +{ + uint32_t max_mask, min_mask; + uint32_t chipst, otpsel; + uint32_t nval; + uint8_t rsrcs; + int error; + + max_mask = 0; + min_mask = 0; + + /* # resources */ + rsrcs = BHND_PMU_GET_BITS(sc->caps, BHND_PMU_CAP_RC); + + /* determine min/max rsrc masks */ + switch (sc->cid.chip_id) { + case BHND_CHIPID_BCM4325: + /* If used by this device, enable the CBUCK */ + if (!bhnd_pmu_res_depfltr_ncb(sc)) + min_mask |= PMURES_BIT(RES4325B0_CBUCK_LPOM); + + chipst = BHND_CHIPC_READ_CHIPST(sc->chipc_dev); + if (BHND_PMU_GET_BITS(chipst, CHIPC_CST4325_PMUTOP_2B)) + min_mask |= PMURES_BIT(RES4325B0_CLDO_PU); + + /* Is OTP required? */ + otpsel = BHND_PMU_GET_BITS(chipst, CHIPC_CST4325_SPROM_OTP_SEL); + if (otpsel != CHIPC_CST_OTP_PWRDN) + min_mask |= PMURES_BIT(RES4325_OTP_PU); + + /* Leave buck boost on in burst mode for certain boards */ + if (sc->board.board_flags & BHND_BFL_BUCKBOOST) { + switch (sc->board.board_type) { + case BHND_BOARD_BCM94325DEVBU: + case BHND_BOARD_BCM94325BGABU: + min_mask |= PMURES_BIT( + RES4325_BUCK_BOOST_BURST); + break; + } + } + + /* Allow all resources to be turned on upon requests */ + max_mask = ~(~0 << rsrcs); + break; + + case BHND_CHIPID_BCM4312: + /* default min_mask = 0x80000cbb is wrong */ + min_mask = 0xcbb; + /* + * max_mask = 0x7fff; + * pmu_res_updown_table_sz = 0; + * pmu_res_depend_table_sz = 0; + */ + break; + + case BHND_CHIPID_BCM4322: + case BHND_CHIPID_BCM43221: + case BHND_CHIPID_BCM43231: + case BHND_CHIPID_BCM4342: + if (sc->cid.chip_rev >= 2) + break; + + /* request ALP(can skip for A1) */ + min_mask = PMURES_BIT(RES4322_RF_LDO) | + PMURES_BIT(RES4322_XTAL_PU) | + PMURES_BIT(RES4322_ALP_AVAIL); + + if (bhnd_get_attach_type(sc->chipc_dev) == BHND_ATTACH_NATIVE) { + min_mask |= + PMURES_BIT(RES4322_SI_PLL_ON) | + PMURES_BIT(RES4322_HT_SI_AVAIL) | + PMURES_BIT(RES4322_PHY_PLL_ON) | + PMURES_BIT(RES4322_OTP_PU) | + PMURES_BIT(RES4322_HT_PHY_AVAIL); + max_mask = 0x1ff; + } + break; + + case BHND_CHIPID_BCM43222: + case BHND_CHIPID_BCM43111: + case BHND_CHIPID_BCM43112: + case BHND_CHIPID_BCM43224: + case BHND_CHIPID_BCM43225: + case BHND_CHIPID_BCM43421: + case BHND_CHIPID_BCM43226: + case BHND_CHIPID_BCM43420: + case BHND_CHIPID_BCM43235: + case BHND_CHIPID_BCM43236: + case BHND_CHIPID_BCM43238: + case BHND_CHIPID_BCM43234: + case BHND_CHIPID_BCM43237: + case BHND_CHIPID_BCM4331: + case BHND_CHIPID_BCM43431: + case BHND_CHIPID_BCM6362: + /* use chip default */ + break; + + case BHND_CHIPID_BCM4328: + min_mask = + PMURES_BIT(RES4328_BB_SWITCHER_PWM) | + PMURES_BIT(RES4328_EXT_SWITCHER_PWM) | + PMURES_BIT(RES4328_XTAL_EN); + max_mask = 0xfffffff; + break; + + case BHND_CHIPID_BCM5354: + /* Allow (but don't require) PLL to turn on */ + max_mask = 0xfffffff; + break; + + case BHND_CHIPID_BCM4329: + /* Down to save the power. */ + if (sc->cid.chip_rev >= 0x2) { + min_mask = + PMURES_BIT(RES4329_CBUCK_LPOM) | + PMURES_BIT(RES4329_LNLDO1_PU) | + PMURES_BIT(RES4329_CLDO_PU); + } else { + min_mask = + PMURES_BIT(RES4329_CBUCK_LPOM) | + PMURES_BIT(RES4329_CLDO_PU); + } + + /* Is OTP required? */ + chipst = BHND_CHIPC_READ_CHIPST(sc->chipc_dev); + otpsel = BHND_PMU_GET_BITS(chipst, CHIPC_CST4329_SPROM_OTP_SEL); + if (otpsel != CHIPC_CST_OTP_PWRDN) + min_mask |= PMURES_BIT(RES4329_OTP_PU); + + /* Allow (but don't require) PLL to turn on */ + max_mask = 0x3ff63e; + break; + + case BHND_CHIPID_BCM4319: + /* We only need a few resources to be kept on all the time */ + min_mask = PMURES_BIT(RES4319_CBUCK_LPOM) | + PMURES_BIT(RES4319_CLDO_PU); + + /* Allow everything else to be turned on upon requests */ + max_mask = ~(~0 << rsrcs); + break; + + case BHND_CHIPID_BCM4336: + /* Down to save the power. */ + min_mask = + PMURES_BIT(RES4336_CBUCK_LPOM) | + PMURES_BIT(RES4336_CLDO_PU) | + PMURES_BIT(RES4336_LDO3P3_PU) | + PMURES_BIT(RES4336_OTP_PU) | + PMURES_BIT(RES4336_DIS_INT_RESET_PD); + /* Allow (but don't require) PLL to turn on */ + max_mask = 0x1ffffff; + break; + + case BHND_CHIPID_BCM4330: + /* Down to save the power. */ + min_mask = + PMURES_BIT(RES4330_CBUCK_LPOM) | PMURES_BIT(RES4330_CLDO_PU) + | PMURES_BIT(RES4330_DIS_INT_RESET_PD) | + PMURES_BIT(RES4330_LDO3P3_PU) | PMURES_BIT(RES4330_OTP_PU); + /* Allow (but don't require) PLL to turn on */ + max_mask = 0xfffffff; + break; + + case BHND_CHIPID_BCM4313: + min_mask = PMURES_BIT(RES4313_BB_PU_RSRC) | + PMURES_BIT(RES4313_XTAL_PU_RSRC) | + PMURES_BIT(RES4313_ALP_AVAIL_RSRC) | + PMURES_BIT(RES4313_BB_PLL_PWRSW_RSRC); + max_mask = 0xffff; + break; + default: + break; + } + + /* Apply nvram override to min mask */ + error = bhnd_nvram_getvar_uint32(sc->chipc_dev, BHND_NVAR_RMIN, &nval); + if (error && error != ENOENT) { + device_printf(sc->dev, "NVRAM error reading %s: %d\n", + BHND_NVAR_RMIN, error); + return (error); + } else if (!error) { + PMU_MSG(("Applying rmin=%#x to min_mask\n", nval)); + min_mask = nval; + } + + /* Apply nvram override to max mask */ + error = bhnd_nvram_getvar_uint32(sc->chipc_dev, BHND_NVAR_RMAX, &nval); + if (error && error != ENOENT) { + device_printf(sc->dev, "NVRAM error reading %s: %d\n", + BHND_NVAR_RMAX, error); + return (error); + } else if (!error) { + PMU_MSG(("Applying rmax=%#x to max_mask\n", nval)); + min_mask = nval; + } + + if (pmin != NULL) + *pmin = min_mask; + + if (pmax != NULL) + *pmax = max_mask; + + return (0); +} + +/* initialize PMU resources */ +int +bhnd_pmu_res_init(struct bhnd_pmu_softc *sc) +{ + const pmu_res_updown_t *pmu_res_updown_table; + const pmu_res_depend_t *pmu_res_depend_table; + size_t pmu_res_updown_table_sz; + size_t pmu_res_depend_table_sz; + uint32_t max_mask, min_mask; + uint8_t rsrcs; + int error; + + pmu_res_depend_table = NULL; + pmu_res_depend_table_sz = 0; + + pmu_res_updown_table = NULL; + pmu_res_updown_table_sz = 0; + + switch (sc->cid.chip_id) { + case BHND_CHIPID_BCM4315: + /* Optimize resources up/down timers */ + pmu_res_updown_table = bcm4315a0_res_updown; + pmu_res_updown_table_sz = nitems(bcm4315a0_res_updown); + + /* Optimize resources dependencies */ + pmu_res_depend_table = bcm4315a0_res_depend; + pmu_res_depend_table_sz = nitems(bcm4315a0_res_depend); + break; + + case BHND_CHIPID_BCM4325: + /* Optimize resources up/down timers */ + pmu_res_updown_table = bcm4325a0_res_updown; + pmu_res_updown_table_sz = nitems(bcm4325a0_res_updown); + + /* Optimize resources dependencies */ + pmu_res_depend_table = bcm4325a0_res_depend; + pmu_res_depend_table_sz = nitems(bcm4325a0_res_depend); + break; + + case BHND_CHIPID_BCM4328: + /* Optimize resources up/down timers */ + pmu_res_updown_table = bcm4328a0_res_updown; + pmu_res_updown_table_sz = nitems(bcm4328a0_res_updown); + + /* Optimize resources dependencies */ + pmu_res_depend_table = bcm4328a0_res_depend; + pmu_res_depend_table_sz = nitems(bcm4328a0_res_depend); + break; + + case BHND_CHIPID_BCM4329: + /* Optimize resources up/down timers */ + pmu_res_updown_table = bcm4329_res_updown; + pmu_res_updown_table_sz = nitems(bcm4329_res_updown); + + /* Optimize resources dependencies */ + pmu_res_depend_table = bcm4329_res_depend; + pmu_res_depend_table_sz = nitems(bcm4329_res_depend); + break; + + case BHND_CHIPID_BCM4319: + /* Optimize resources up/down timers */ + pmu_res_updown_table = bcm4319a0_res_updown; + pmu_res_updown_table_sz = nitems(bcm4319a0_res_updown); + + /* Optimize resources dependencies masks */ + pmu_res_depend_table = bcm4319a0_res_depend; + pmu_res_depend_table_sz = nitems(bcm4319a0_res_depend); + break; + + case BHND_CHIPID_BCM4336: + /* Optimize resources up/down timers */ + pmu_res_updown_table = bcm4336a0_res_updown; + pmu_res_updown_table_sz = nitems(bcm4336a0_res_updown); + + /* Optimize resources dependencies masks */ + pmu_res_depend_table = bcm4336a0_res_depend; + pmu_res_depend_table_sz = nitems(bcm4336a0_res_depend); + break; + + case BHND_CHIPID_BCM4330: + /* Optimize resources up/down timers */ + pmu_res_updown_table = bcm4330a0_res_updown; + pmu_res_updown_table_sz = nitems(bcm4330a0_res_updown); + + /* Optimize resources dependencies masks */ + pmu_res_depend_table = bcm4330a0_res_depend; + pmu_res_depend_table_sz = nitems(bcm4330a0_res_depend); + break; + default: + break; + } + + /* # resources */ + rsrcs = BHND_PMU_GET_BITS(sc->caps, BHND_PMU_CAP_RC); + + /* Program up/down timers */ + for (size_t i = 0; i < pmu_res_updown_table_sz; i++) { + const pmu_res_updown_t *updt; + + KASSERT(pmu_res_updown_table != NULL, ("no updown tables")); + + updt = &pmu_res_updown_table[pmu_res_updown_table_sz - i - 1]; + + PMU_MSG(("Changing rsrc %d res_updn_timer to %#x\n", + updt->resnum, updt->updown)); + + BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, updt->resnum); + BHND_PMU_WRITE_4(sc, BHND_PMU_RES_UPDN_TIMER, updt->updown); + } + + /* Apply nvram overrides to up/down timers */ + for (uint8_t i = 0; i < rsrcs; i++) { + char name[6]; + uint32_t val; + + snprintf(name, sizeof(name), "r%dt", i); + error = bhnd_nvram_getvar_uint32(sc->chipc_dev, name, &val); + + if (error == ENOENT) { + continue; + } else if (error) { + device_printf(sc->dev, "NVRAM error reading %s: %d\n", + name, error); + return (error); + } + + PMU_MSG(("Applying %s=%s to rsrc %d res_updn_timer\n", name, + val, i)); + + BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, i); + BHND_PMU_WRITE_4(sc, BHND_PMU_RES_UPDN_TIMER, val); + } + + /* Program resource dependencies table */ + for (size_t i = 0; i < pmu_res_depend_table_sz; i++) { + const pmu_res_depend_t *rdep; + pmu_res_filter filter; + uint32_t depend_mask; + + KASSERT(pmu_res_depend_table != NULL, ("no depend tables")); + + rdep = &pmu_res_depend_table[pmu_res_depend_table_sz - i - 1]; + filter = rdep->filter; + + if (filter != NULL && !filter(sc)) + continue; + + for (uint8_t i = 0; i < rsrcs; i++) { + if ((rdep->res_mask & BHND_PMURES_BIT(i)) == 0) + continue; + + BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, i); + depend_mask = BHND_PMU_READ_4(sc, + BHND_PMU_RES_DEP_MASK); + switch (rdep->action) { + case RES_DEPEND_SET: + PMU_MSG(("Changing rsrc %hhu res_dep_mask to " + "%#x\n", i, table->depend_mask)); + depend_mask = rdep->depend_mask; + break; + + case RES_DEPEND_ADD: + PMU_MSG(("Adding %#x to rsrc %hhu " + "res_dep_mask\n", table->depend_mask, i)); + + depend_mask |= rdep->depend_mask; + break; + + case RES_DEPEND_REMOVE: + PMU_MSG(("Removing %#x from rsrc %hhu " + "res_dep_mask\n", table->depend_mask, i)); + + depend_mask &= ~(rdep->depend_mask); + break; + + default: + panic("unknown RES_DEPEND action: %d\n", + rdep->action); + break; + } + + + } + } + + /* Apply nvram overrides to dependencies masks */ + for (uint8_t i = 0; i < rsrcs; i++) { + char name[6]; + uint32_t val; + + snprintf(name, sizeof(name), "r%dd", i); + error = bhnd_nvram_getvar_uint32(sc->chipc_dev, name, &val); + + if (error == ENOENT) { + continue; + } else if (error) { + device_printf(sc->dev, "NVRAM error reading %s: %d\n", + name, error); + return (error); + } + + PMU_MSG(("Applying %s=%s to rsrc %d res_dep_mask\n", name, val, + i)); + + BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, i); + BHND_PMU_WRITE_4(sc, BHND_PMU_RES_DEP_MASK, val); + } + + /* Determine min/max rsrc masks */ + if ((error = bhnd_pmu_res_masks(sc, &min_mask, &max_mask))) + return (error); + + /* It is required to program max_mask first and then min_mask */ + + /* Program max resource mask */ + if (max_mask != 0) { + PMU_MSG(("Changing max_res_mask to 0x%x\n", max_mask)); + BHND_PMU_WRITE_4(sc, BHND_PMU_MAX_RES_MASK, max_mask); + } + + /* Program min resource mask */ + + if (min_mask != 0) { + PMU_MSG(("Changing min_res_mask to 0x%x\n", min_mask)); + BHND_PMU_WRITE_4(sc, BHND_PMU_MIN_RES_MASK, min_mask); + } + + /* Add some delay; allow resources to come up and settle. */ + DELAY(2000); + + return (0); +} + +/* setup pll and query clock speed */ +struct pmu0_xtaltab0 { + uint16_t freq; + uint8_t xf; + uint8_t wbint; + uint32_t wbfrac; +}; + +/* the following table is based on 880Mhz fvco */ +static const pmu0_xtaltab0_t pmu0_xtaltab0[] = { + { + 12000, 1, 73, 349525}, { + 13000, 2, 67, 725937}, { + 14400, 3, 61, 116508}, { + 15360, 4, 57, 305834}, { + 16200, 5, 54, 336579}, { + 16800, 6, 52, 399457}, { + 19200, 7, 45, 873813}, { + 19800, 8, 44, 466033}, { + 20000, 9, 44, 0}, { + 25000, 10, 70, 419430}, { + 26000, 11, 67, 725937}, { + 30000, 12, 58, 699050}, { + 38400, 13, 45, 873813}, { + 40000, 14, 45, 0}, { + 0, 0, 0, 0} +}; + +#define PMU0_XTAL0_DEFAULT 8 + +/* setup pll and query clock speed */ +struct pmu1_xtaltab0 { + uint16_t fref; + uint8_t xf; + uint8_t p1div; + uint8_t p2div; + uint8_t ndiv_int; + uint32_t ndiv_frac; +}; + +static const pmu1_xtaltab0_t pmu1_xtaltab0_880_4329[] = { + { + 12000, 1, 3, 22, 0x9, 0xFFFFEF}, { + 13000, 2, 1, 6, 0xb, 0x483483}, { + 14400, 3, 1, 10, 0xa, 0x1C71C7}, { + 15360, 4, 1, 5, 0xb, 0x755555}, { + 16200, 5, 1, 10, 0x5, 0x6E9E06}, { + 16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, { + 19200, 7, 1, 4, 0xb, 0x755555}, { + 19800, 8, 1, 11, 0x4, 0xA57EB}, { + 20000, 9, 1, 11, 0x4, 0x0}, { + 24000, 10, 3, 11, 0xa, 0x0}, { + 25000, 11, 5, 16, 0xb, 0x0}, { + 26000, 12, 1, 1, 0x21, 0xD89D89}, { + 30000, 13, 3, 8, 0xb, 0x0}, { + 37400, 14, 3, 1, 0x46, 0x969696}, { + 38400, 15, 1, 1, 0x16, 0xEAAAAA}, { + 40000, 16, 1, 2, 0xb, 0}, { + 0, 0, 0, 0, 0, 0} +}; + +/* the following table is based on 880Mhz fvco */ +static const pmu1_xtaltab0_t pmu1_xtaltab0_880[] = { + { + 12000, 1, 3, 22, 0x9, 0xFFFFEF}, { + 13000, 2, 1, 6, 0xb, 0x483483}, { + 14400, 3, 1, 10, 0xa, 0x1C71C7}, { + 15360, 4, 1, 5, 0xb, 0x755555}, { + 16200, 5, 1, 10, 0x5, 0x6E9E06}, { + 16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, { + 19200, 7, 1, 4, 0xb, 0x755555}, { + 19800, 8, 1, 11, 0x4, 0xA57EB}, { + 20000, 9, 1, 11, 0x4, 0x0}, { + 24000, 10, 3, 11, 0xa, 0x0}, { + 25000, 11, 5, 16, 0xb, 0x0}, { + 26000, 12, 1, 2, 0x10, 0xEC4EC4}, { + 30000, 13, 3, 8, 0xb, 0x0}, { + 33600, 14, 1, 2, 0xd, 0x186186}, { + 38400, 15, 1, 2, 0xb, 0x755555}, { + 40000, 16, 1, 2, 0xb, 0}, { + 0, 0, 0, 0, 0, 0} +}; + +#define PMU1_XTALTAB0_880_12000K 0 +#define PMU1_XTALTAB0_880_13000K 1 +#define PMU1_XTALTAB0_880_14400K 2 +#define PMU1_XTALTAB0_880_15360K 3 +#define PMU1_XTALTAB0_880_16200K 4 +#define PMU1_XTALTAB0_880_16800K 5 +#define PMU1_XTALTAB0_880_19200K 6 +#define PMU1_XTALTAB0_880_19800K 7 +#define PMU1_XTALTAB0_880_20000K 8 +#define PMU1_XTALTAB0_880_24000K 9 +#define PMU1_XTALTAB0_880_25000K 10 +#define PMU1_XTALTAB0_880_26000K 11 +#define PMU1_XTALTAB0_880_30000K 12 +#define PMU1_XTALTAB0_880_37400K 13 +#define PMU1_XTALTAB0_880_38400K 14 +#define PMU1_XTALTAB0_880_40000K 15 + +/* the following table is based on 1760Mhz fvco */ +static const pmu1_xtaltab0_t pmu1_xtaltab0_1760[] = { + { + 12000, 1, 3, 44, 0x9, 0xFFFFEF}, { + 13000, 2, 1, 12, 0xb, 0x483483}, { + 14400, 3, 1, 20, 0xa, 0x1C71C7}, { + 15360, 4, 1, 10, 0xb, 0x755555}, { + 16200, 5, 1, 20, 0x5, 0x6E9E06}, { + 16800, 6, 1, 20, 0x5, 0x3Cf3Cf}, { + 19200, 7, 1, 18, 0x5, 0x17B425}, { + 19800, 8, 1, 22, 0x4, 0xA57EB}, { + 20000, 9, 1, 22, 0x4, 0x0}, { + 24000, 10, 3, 22, 0xa, 0x0}, { + 25000, 11, 5, 32, 0xb, 0x0}, { + 26000, 12, 1, 4, 0x10, 0xEC4EC4}, { + 30000, 13, 3, 16, 0xb, 0x0}, { + 38400, 14, 1, 10, 0x4, 0x955555}, { + 40000, 15, 1, 4, 0xb, 0}, { + 0, 0, 0, 0, 0, 0} +}; + +/* table index */ +#define PMU1_XTALTAB0_1760_12000K 0 +#define PMU1_XTALTAB0_1760_13000K 1 +#define PMU1_XTALTAB0_1760_14400K 2 +#define PMU1_XTALTAB0_1760_15360K 3 +#define PMU1_XTALTAB0_1760_16200K 4 +#define PMU1_XTALTAB0_1760_16800K 5 +#define PMU1_XTALTAB0_1760_19200K 6 +#define PMU1_XTALTAB0_1760_19800K 7 +#define PMU1_XTALTAB0_1760_20000K 8 +#define PMU1_XTALTAB0_1760_24000K 9 +#define PMU1_XTALTAB0_1760_25000K 10 +#define PMU1_XTALTAB0_1760_26000K 11 +#define PMU1_XTALTAB0_1760_30000K 12 +#define PMU1_XTALTAB0_1760_38400K 13 +#define PMU1_XTALTAB0_1760_40000K 14 + +/* the following table is based on 1440Mhz fvco */ +static const pmu1_xtaltab0_t pmu1_xtaltab0_1440[] = { + { + 12000, 1, 1, 1, 0x78, 0x0}, { + 13000, 2, 1, 1, 0x6E, 0xC4EC4E}, { + 14400, 3, 1, 1, 0x64, 0x0}, { + 15360, 4, 1, 1, 0x5D, 0xC00000}, { + 16200, 5, 1, 1, 0x58, 0xE38E38}, { + 16800, 6, 1, 1, 0x55, 0xB6DB6D}, { + 19200, 7, 1, 1, 0x4B, 0}, { + 19800, 8, 1, 1, 0x48, 0xBA2E8B}, { + 20000, 9, 1, 1, 0x48, 0x0}, { + 25000, 10, 1, 1, 0x39, 0x999999}, { + 26000, 11, 1, 1, 0x37, 0x627627}, { + 30000, 12, 1, 1, 0x30, 0x0}, { + 37400, 13, 2, 1, 0x4D, 0x15E76}, { + 38400, 13, 2, 1, 0x4B, 0x0}, { + 40000, 14, 2, 1, 0x48, 0x0}, { + 48000, 15, 2, 1, 0x3c, 0x0}, { + 0, 0, 0, 0, 0, 0} +}; + +/* table index */ +#define PMU1_XTALTAB0_1440_12000K 0 +#define PMU1_XTALTAB0_1440_13000K 1 +#define PMU1_XTALTAB0_1440_14400K 2 +#define PMU1_XTALTAB0_1440_15360K 3 +#define PMU1_XTALTAB0_1440_16200K 4 +#define PMU1_XTALTAB0_1440_16800K 5 +#define PMU1_XTALTAB0_1440_19200K 6 +#define PMU1_XTALTAB0_1440_19800K 7 +#define PMU1_XTALTAB0_1440_20000K 8 +#define PMU1_XTALTAB0_1440_25000K 9 +#define PMU1_XTALTAB0_1440_26000K 10 +#define PMU1_XTALTAB0_1440_30000K 11 +#define PMU1_XTALTAB0_1440_37400K 12 +#define PMU1_XTALTAB0_1440_38400K 13 +#define PMU1_XTALTAB0_1440_40000K 14 +#define PMU1_XTALTAB0_1440_48000K 15 + +#define XTAL_FREQ_24000MHZ 24000 +#define XTAL_FREQ_30000MHZ 30000 +#define XTAL_FREQ_37400MHZ 37400 +#define XTAL_FREQ_48000MHZ 48000 + +static const pmu1_xtaltab0_t pmu1_xtaltab0_960[] = { + { + 12000, 1, 1, 1, 0x50, 0x0}, { + 13000, 2, 1, 1, 0x49, 0xD89D89}, { + 14400, 3, 1, 1, 0x42, 0xAAAAAA}, { + 15360, 4, 1, 1, 0x3E, 0x800000}, { + 16200, 5, 1, 1, 0x39, 0x425ED0}, { + 16800, 6, 1, 1, 0x39, 0x249249}, { + 19200, 7, 1, 1, 0x32, 0x0}, { + 19800, 8, 1, 1, 0x30, 0x7C1F07}, { + 20000, 9, 1, 1, 0x30, 0x0}, { + 25000, 10, 1, 1, 0x26, 0x666666}, { + 26000, 11, 1, 1, 0x24, 0xEC4EC4}, { + 30000, 12, 1, 1, 0x20, 0x0}, { + 37400, 13, 2, 1, 0x33, 0x563EF9}, { + 38400, 14, 2, 1, 0x32, 0x0}, { + 40000, 15, 2, 1, 0x30, 0x0}, { + 48000, 16, 2, 1, 0x28, 0x0}, { + 0, 0, 0, 0, 0, 0} +}; + +/* table index */ +#define PMU1_XTALTAB0_960_12000K 0 +#define PMU1_XTALTAB0_960_13000K 1 +#define PMU1_XTALTAB0_960_14400K 2 +#define PMU1_XTALTAB0_960_15360K 3 +#define PMU1_XTALTAB0_960_16200K 4 +#define PMU1_XTALTAB0_960_16800K 5 +#define PMU1_XTALTAB0_960_19200K 6 +#define PMU1_XTALTAB0_960_19800K 7 +#define PMU1_XTALTAB0_960_20000K 8 +#define PMU1_XTALTAB0_960_25000K 9 +#define PMU1_XTALTAB0_960_26000K 10 +#define PMU1_XTALTAB0_960_30000K 11 +#define PMU1_XTALTAB0_960_37400K 12 +#define PMU1_XTALTAB0_960_38400K 13 +#define PMU1_XTALTAB0_960_40000K 14 +#define PMU1_XTALTAB0_960_48000K 15 + +/* select xtal table for each chip */ +static const pmu1_xtaltab0_t * +bhnd_pmu1_xtaltab0(struct bhnd_pmu_softc *sc) +{ + switch (sc->cid.chip_id) { + case BHND_CHIPID_BCM4315: + return (pmu1_xtaltab0_1760); + case BHND_CHIPID_BCM4319: + return (pmu1_xtaltab0_1440); + case BHND_CHIPID_BCM4325: + return (pmu1_xtaltab0_880); + case BHND_CHIPID_BCM4329: + return (pmu1_xtaltab0_880_4329); + case BHND_CHIPID_BCM4336: + return (pmu1_xtaltab0_960); + case BHND_CHIPID_BCM4330: + if (PMU_CST4330_SDIOD_CHIPMODE(sc)) + return (pmu1_xtaltab0_960); + else + return (pmu1_xtaltab0_1440); + default: + PMU_MSG(("bhnd_pmu1_xtaltab0: Unknown chipid %#hx\n", + sc->cid.chip_id)); + return (NULL); + } +} + +/* select default xtal frequency for each chip */ +static const pmu1_xtaltab0_t * +bhnd_pmu1_xtaldef0(struct bhnd_pmu_softc *sc) +{ + switch (sc->cid.chip_id) { + case BHND_CHIPID_BCM4315: + /* Default to 26000Khz */ + return (&pmu1_xtaltab0_1760[PMU1_XTALTAB0_1760_26000K]); + case BHND_CHIPID_BCM4319: + /* Default to 30000Khz */ + return (&pmu1_xtaltab0_1440[PMU1_XTALTAB0_1440_30000K]); + case BHND_CHIPID_BCM4325: + /* Default to 26000Khz */ + return (&pmu1_xtaltab0_880[PMU1_XTALTAB0_880_26000K]); + case BHND_CHIPID_BCM4329: + /* Default to 38400Khz */ + return (&pmu1_xtaltab0_880_4329[PMU1_XTALTAB0_880_38400K]); + case BHND_CHIPID_BCM4336: + /* Default to 26000Khz */ + return (&pmu1_xtaltab0_960[PMU1_XTALTAB0_960_26000K]); + case BHND_CHIPID_BCM4330: + /* Default to 37400Khz */ + if (PMU_CST4330_SDIOD_CHIPMODE(sc)) + return (&pmu1_xtaltab0_960[PMU1_XTALTAB0_960_37400K]); + else + return (&pmu1_xtaltab0_1440[PMU1_XTALTAB0_1440_37400K]); + default: + PMU_MSG(("bhnd_pmu1_xtaldef0: Unknown chipid %#hx\n", + sc->cid.chip_id)); + return (NULL); + } +} + +/* select default pll fvco for each chip */ +static uint32_t +bhnd_pmu1_pllfvco0(struct bhnd_pmu_softc *sc) +{ + switch (sc->cid.chip_id) { + case BHND_CHIPID_BCM4329: + return (FVCO_880); + case BHND_CHIPID_BCM4319: + return (FVCO_1440); + case BHND_CHIPID_BCM4336: + return (FVCO_960); + case BHND_CHIPID_BCM4330: + if (PMU_CST4330_SDIOD_CHIPMODE(sc)) + return (FVCO_960); + else + return (FVCO_1440); + default: + PMU_MSG(("bhnd_pmu1_pllfvco0: Unknown chipid %#hx\n", + sc->cid.chip_id)); + return (0); + } +} + +/* query alp/xtal clock frequency */ +static uint32_t +bhnd_pmu1_alpclk0(struct bhnd_pmu_softc *sc) +{ + const pmu1_xtaltab0_t *xt; + uint32_t xf; + + /* Find the frequency in the table */ + xf = BHND_PMU_READ_4(sc, BHND_PMU_CTRL); + xf = BHND_PMU_GET_BITS(xf, BHND_PMU_CTRL_XTALFREQ); + + for (xt = bhnd_pmu1_xtaltab0(sc); xt != NULL && xt->fref != 0; xt++) { + if (xt->xf == xf) + break; + } + + /* Could not find it so assign a default value */ + if (xt == NULL || xt->fref == 0) + xt = bhnd_pmu1_xtaldef0(sc); + + if (xt == NULL || xt->fref == 0) { + device_printf(sc->dev, + "no matching ALP/XTAL frequency found\n"); + return (0); + } + + return (xt->fref * 1000); +} + +/* Set up PLL registers in the PMU as per the crystal speed. */ +static void +bhnd_pmu0_pllinit0(struct bhnd_pmu_softc *sc, uint32_t xtal) +{ + const pmu0_xtaltab0_t *xt; + uint32_t pll_data, pll_mask; + uint32_t pll_res; + uint32_t pmu_ctrl; + uint32_t xf; + + /* Use h/w default PLL config */ + if (xtal == 0) { + PMU_MSG(("Unspecified xtal frequency, skipping PLL " + "configuration\n")); + return; + } + + /* Find the frequency in the table */ + for (xt = pmu0_xtaltab0; xt->freq; xt ++) { + if (xt->freq == xtal) + break; + } + + if (xt->freq == 0) + xt = &pmu0_xtaltab0[PMU0_XTAL0_DEFAULT]; + + PMU_MSG(("XTAL %d.%d MHz (%d)\n", xtal / 1000, xtal % 1000, xt->xf)); + + /* Check current PLL state */ + pmu_ctrl = BHND_PMU_READ_4(sc, BHND_PMU_CTRL); + xf = BHND_PMU_GET_BITS(pmu_ctrl, BHND_PMU_CTRL_XTALFREQ); + if (xf == xt->xf) { +#ifdef BCMUSBDEV + if (sc->cid.chip_id == BHND_CHIPID_BCM4328) { + bhnd_pmu0_sbclk4328(sc, + BHND_PMU0_PLL0_PC0_DIV_ARM_88MHZ); + return; + } +#endif /* BCMUSBDEV */ + + PMU_MSG(("PLL already programmed for %d.%d MHz\n", + xt->freq / 1000, xt->freq % 1000)); + return; + } + + if (xf != 0) { + PMU_MSG(("Reprogramming PLL for %d.%d MHz (was %d.%dMHz)\n", + xt->freq / 1000, xt->freq % 1000, + pmu0_xtaltab0[tmp-1].freq / 1000, + pmu0_xtaltab0[tmp-1].freq % 1000)); + } else { + PMU_MSG(("Programming PLL for %d.%d MHz\n", + xt->freq / 1000, xt->freq % 1000)); + } + + /* Make sure the PLL is off */ + switch (sc->cid.chip_id) { + case BHND_CHIPID_BCM4328: + pll_res = PMURES_BIT(RES4328_BB_PLL_PU); + break; + case BHND_CHIPID_BCM5354: + pll_res = PMURES_BIT(RES5354_BB_PLL_PU); + break; + default: + panic("unsupported chipid %#hx\n", sc->cid.chip_id); + } + BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, ~pll_res); + BHND_PMU_AND_4(sc, BHND_PMU_MAX_RES_MASK, ~pll_res); + + /* Wait for HT clock to shutdown. */ + PMU_WAIT_CLKST(sc, 0, BHND_CCS_HTAVAIL); + + PMU_MSG(("Done masking\n")); + + /* Write PDIV in pllcontrol[0] */ + if (xt->freq >= BHND_PMU0_PLL0_PC0_PDIV_FREQ) { + BHND_PMU_PLL_WRITE(sc, BHND_PMU0_PLL0_PLLCTL0, + BHND_PMU0_PLL0_PC0_PDIV_MASK, BHND_PMU0_PLL0_PC0_PDIV_MASK); + } else { + BHND_PMU_PLL_WRITE(sc, BHND_PMU0_PLL0_PLLCTL0, 0, + BHND_PMU0_PLL0_PC0_PDIV_MASK); + } + + /* Write WILD in pllcontrol[1] */ + pll_data = + BHND_PMU_SET_BITS(xt->wbint, BHND_PMU0_PLL0_PC1_WILD_INT) | + BHND_PMU_SET_BITS(xt->wbfrac, BHND_PMU0_PLL0_PC1_WILD_FRAC); + + if (xt->wbfrac == 0) { + pll_data |= BHND_PMU0_PLL0_PC1_STOP_MOD; + } else { + pll_data &= ~BHND_PMU0_PLL0_PC1_STOP_MOD; + } + + pll_mask = + BHND_PMU0_PLL0_PC1_WILD_INT_MASK | + BHND_PMU0_PLL0_PC1_WILD_FRAC_MASK; + + BHND_PMU_PLL_WRITE(sc, BHND_PMU0_PLL0_PLLCTL1, pll_data, pll_mask); + + /* Write WILD in pllcontrol[2] */ + pll_data = BHND_PMU_SET_BITS(xt->wbint, BHND_PMU0_PLL0_PC2_WILD_INT); + pll_mask = BHND_PMU0_PLL0_PC2_WILD_INT_MASK; + BHND_PMU_PLL_WRITE(sc, BHND_PMU0_PLL0_PLLCTL2, pll_data, pll_mask); + + PMU_MSG(("Done pll\n")); + + /* Write XtalFreq. Set the divisor also. */ + pmu_ctrl = BHND_PMU_READ_4(sc, BHND_PMU_CTRL); + pmu_ctrl &= ~(BHND_PMU_CTRL_ILP_DIV_MASK|BHND_PMU_CTRL_XTALFREQ_MASK); + + pmu_ctrl |= BHND_PMU_SET_BITS(((xt->freq + 127) / 128) - 1, + BHND_PMU_CTRL_ILP_DIV); + pmu_ctrl |= BHND_PMU_SET_BITS(xt->xf, BHND_PMU_CTRL_XTALFREQ); + + BHND_PMU_WRITE_4(sc, BHND_PMU_CTRL, pmu_ctrl); +} + +/* query alp/xtal clock frequency */ +static uint32_t +bhnd_pmu0_alpclk0(struct bhnd_pmu_softc *sc) +{ + const pmu0_xtaltab0_t *xt; + uint32_t xf; + + /* Find the frequency in the table */ + xf = BHND_PMU_READ_4(sc, BHND_PMU_CTRL); + xf = BHND_PMU_GET_BITS(xf, BHND_PMU_CTRL_XTALFREQ); + for (xt = pmu0_xtaltab0; xt->freq; xt++) + if (xt->xf == xf) + break; + + /* PLL must be configured before */ + if (xt == NULL || xt->freq == 0) + panic("unsupported frequency: %u", xf); + + return (xt->freq * 1000); +} + +/* query CPU clock frequency */ +static uint32_t +bhnd_pmu0_cpuclk0(struct bhnd_pmu_softc *sc) +{ + uint32_t tmp, divarm; + uint32_t FVCO; +#ifdef BCMDBG + uint32_t pdiv, wbint, wbfrac, fvco; + uint32_t freq; +#endif + + FVCO = FVCO_880; + + /* Read divarm from pllcontrol[0] */ + tmp = BHND_PMU_PLL_READ(sc, BHND_PMU0_PLL0_PLLCTL0); + divarm = BHND_PMU_GET_BITS(tmp, BHND_PMU0_PLL0_PC0_DIV_ARM); + +#ifdef BCMDBG + /* Calculate fvco based on xtal freq, pdiv, and wild */ + pdiv = tmp & BHND_PMU0_PLL0_PC0_PDIV_MASK; + + tmp = BHND_PMU_PLL_READ(sc, BHND_PMU0_PLL0_PLLCTL1); + wbfrac = BHND_PMU_GET_BITS(tmp, BHND_PMU0_PLL0_PC1_WILD_FRAC); + wbint = BHND_PMU_GET_BITS(tmp, PMU0_PLL0_PC1_WILD_INT); + + tmp = BHND_PMU_PLL_READ(sc, BHND_PMU0_PLL0_PLLCTL2); + wbint += BHND_PMU_GET_BITS(tmp, BHND_PMU0_PLL0_PC2_WILD_INT); + + freq = bhnd_pmu0_alpclk0(sih, osh, cc) / 1000; + + fvco = (freq * wbint) << 8; + fvco += (freq * (wbfrac >> 10)) >> 2; + fvco += (freq * (wbfrac & 0x3ff)) >> 10; + fvco >>= 8; + fvco >>= pdiv; + fvco /= 1000; + fvco *= 1000; + + PMU_MSG(("bhnd_pmu0_cpuclk0: wbint %u wbfrac %u fvco %u\n", + wbint, wbfrac, fvco)); + + FVCO = fvco; +#endif /* BCMDBG */ + + /* Return ARM/SB clock */ + return FVCO / (divarm + BHND_PMU0_PLL0_PC0_DIV_ARM_BASE) * 1000; +} + + + +/* Set up PLL registers in the PMU as per the crystal speed. */ +static void +bhnd_pmu1_pllinit0(struct bhnd_pmu_softc *sc, uint32_t xtal) +{ + const pmu1_xtaltab0_t *xt; + uint32_t buf_strength; + uint32_t plladdr, plldata, pllmask; + uint32_t pmuctrl; + uint32_t FVCO; + uint8_t ndiv_mode; + + FVCO = bhnd_pmu1_pllfvco0(sc) / 1000; + buf_strength = 0; + ndiv_mode = 1; + + /* Use h/w default PLL config */ + if (xtal == 0) { + PMU_MSG(("Unspecified xtal frequency, skipping PLL " + "configuration\n")); + return; + } + + /* Find the frequency in the table */ + for (xt = bhnd_pmu1_xtaltab0(sc); xt != NULL && xt->fref != 0; xt++) { + if (xt->fref == xtal) + break; + } + + /* Check current PLL state, bail out if it has been programmed or + * we don't know how to program it. + */ + if (xt == NULL || xt->fref == 0) { + device_printf(sc->dev, "Unsupported XTAL frequency %d.%dMHz, " + "skipping PLL configuration\n", xtal / 1000, xtal % 1000); + return; + } + + /* For 4319 bootloader already programs the PLL but bootloader does not + * program the PLL4 and PLL5. So Skip this check for 4319. */ + pmuctrl = BHND_PMU_READ_4(sc, BHND_PMU_CTRL); + if (BHND_PMU_GET_BITS(pmuctrl, BHND_PMU_CTRL_XTALFREQ) == xt->xf && + sc->cid.chip_id != BHND_CHIPID_BCM4319 && + sc->cid.chip_id != BHND_CHIPID_BCM4330) + { + PMU_MSG(("PLL already programmed for %d.%dMHz\n", + xt->fref / 1000, xt->fref % 1000)); + return; + } + + PMU_MSG(("XTAL %d.%dMHz (%d)\n", xtal / 1000, xtal % 1000, xt->xf)); + PMU_MSG(("Programming PLL for %d.%dMHz\n", xt->fref / 1000, + xt->fref % 1000)); + + switch (sc->cid.chip_id) { + case BHND_CHIPID_BCM4325: + /* Change the BBPLL drive strength to 2 for all channels */ + buf_strength = 0x222222; + + BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, + ~(PMURES_BIT(RES4325_BBPLL_PWRSW_PU) | + PMURES_BIT(RES4325_HT_AVAIL))); + BHND_PMU_AND_4(sc, BHND_PMU_MAX_RES_MASK, + ~(PMURES_BIT(RES4325_BBPLL_PWRSW_PU) | + PMURES_BIT(RES4325_HT_AVAIL))); + + /* Wait for HT clock to shutdown. */ + PMU_WAIT_CLKST(sc, 0, BHND_CCS_HTAVAIL); + break; + + case BHND_CHIPID_BCM4329: + /* Change the BBPLL drive strength to 8 for all channels */ + buf_strength = 0x888888; + + BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, + ~(PMURES_BIT(RES4329_BBPLL_PWRSW_PU) | + PMURES_BIT(RES4329_HT_AVAIL))); + BHND_PMU_AND_4(sc, BHND_PMU_MAX_RES_MASK, + ~(PMURES_BIT(RES4329_BBPLL_PWRSW_PU) | + PMURES_BIT(RES4329_HT_AVAIL))); + + /* Wait for HT clock to shutdown. */ + PMU_WAIT_CLKST(sc, 0, BHND_CCS_HTAVAIL); + + /* Initialize PLL4 */ + plladdr = BHND_PMU1_PLL0_PLLCTL4; + if (xt->fref == 38400) + plldata = 0x200024C0; + else if (xt->fref == 37400) + plldata = 0x20004500; + else if (xt->fref == 26000) + plldata = 0x200024C0; + else + plldata = 0x200005C0; /* Chip Dflt Settings */ + + BHND_PMU_PLL_WRITE(sc, plladdr, plldata, ~0); + + /* Initialize PLL5 */ + plladdr = BHND_PMU1_PLL0_PLLCTL5; + + plldata = BHND_PMU_PLL_READ(sc, plladdr); + plldata &= BHND_PMU1_PLL0_PC5_CLK_DRV_MASK; + + if (xt->fref == 38400 || + xt->fref == 37400 || + xt->fref == 26000) { + plldata |= 0x15; + } else { + plldata |= 0x25; /* Chip Dflt Settings */ + } + + BHND_PMU_PLL_WRITE(sc, plladdr, plldata, ~0); + break; + + case BHND_CHIPID_BCM4319: + /* Change the BBPLL drive strength to 2 for all channels */ + buf_strength = 0x222222; + + /* Make sure the PLL is off */ + /* WAR65104: Disable the HT_AVAIL resource first and then + * after a delay (more than downtime for HT_AVAIL) remove the + * BBPLL resource; backplane clock moves to ALP from HT. + */ + BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, + ~(PMURES_BIT(RES4319_HT_AVAIL))); + BHND_PMU_AND_4(sc, BHND_PMU_MAX_RES_MASK, + ~(PMURES_BIT(RES4319_HT_AVAIL))); + + DELAY(100); + BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, + ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU))); + BHND_PMU_AND_4(sc, BHND_PMU_MAX_RES_MASK, + ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU))); + + DELAY(100); + + /* Wait for HT clock to shutdown. */ + PMU_WAIT_CLKST(sc, 0, BHND_CCS_HTAVAIL); + + plldata = 0x200005c0; + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL4, plldata, ~0); + break; + + case BHND_CHIPID_BCM4336: + BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, + ~(PMURES_BIT(RES4336_HT_AVAIL) | + PMURES_BIT(RES4336_MACPHY_CLKAVAIL))); + BHND_PMU_AND_4(sc, BHND_PMU_MAX_RES_MASK, + ~(PMURES_BIT(RES4336_HT_AVAIL) | + PMURES_BIT(RES4336_MACPHY_CLKAVAIL))); + DELAY(100); + + /* Wait for HT clock to shutdown. */ + PMU_WAIT_CLKST(sc, 0, BHND_CCS_HTAVAIL); + + break; + + case BHND_CHIPID_BCM4330: + BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, + ~(PMURES_BIT(RES4330_HT_AVAIL) | + PMURES_BIT(RES4330_MACPHY_CLKAVAIL))); + BHND_PMU_AND_4(sc, BHND_PMU_MAX_RES_MASK, + ~(PMURES_BIT(RES4330_HT_AVAIL) | + PMURES_BIT(RES4330_MACPHY_CLKAVAIL))); + DELAY(100); + + /* Wait for HT clock to shutdown. */ + PMU_WAIT_CLKST(sc, 0, BHND_CCS_HTAVAIL); + + break; + + default: + panic("unsupported chipid %#hx\n", sc->cid.chip_id); + } + + PMU_MSG(("Done masking\n")); + + /* Write p1div and p2div to pllcontrol[0] */ + plldata = + BHND_PMU_SET_BITS(xt->p1div, BHND_PMU1_PLL0_PC0_P1DIV) | + BHND_PMU_SET_BITS(xt->p2div, BHND_PMU1_PLL0_PC0_P2DIV); + pllmask = BHND_PMU1_PLL0_PC0_P1DIV_MASK|BHND_PMU1_PLL0_PC0_P2DIV_MASK; + + if (sc->cid.chip_id == BHND_CHIPID_BCM4319) { + plldata &= ~(BHND_PMU1_PLL0_PC0_BYPASS_SDMOD_MASK); + pllmask |= BHND_PMU1_PLL0_PC0_BYPASS_SDMOD_MASK; + if (!xt->ndiv_frac) { + plldata |= BHND_PMU_SET_BITS(1, + BHND_PMU1_PLL0_PC0_BYPASS_SDMOD); + } + } + + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, plldata, pllmask); + + + if (sc->cid.chip_id == BHND_CHIPID_BCM4330) + bhnd_pmu_set_4330_plldivs(sc); + + if (sc->cid.chip_id == BHND_CHIPID_BCM4329 && sc->cid.chip_rev == 0) { + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, + BHND_PMU_DOT11MAC_880MHZ_CLK_DIVISOR_VAL, + BHND_PMU_DOT11MAC_880MHZ_CLK_DIVISOR_MASK); + } + + /* Write ndiv_int and ndiv_mode to pllcontrol[2] */ + if (sc->cid.chip_id == BHND_CHIPID_BCM4336 || + sc->cid.chip_id == BHND_CHIPID_BCM4330) + { + ndiv_mode = BHND_PMU1_PLL0_PC2_NDIV_MODE_MFB; + } else if (sc->cid.chip_id == BHND_CHIPID_BCM4319) { + if (!(xt->ndiv_frac)) + ndiv_mode = BHND_PMU1_PLL0_PC2_NDIV_MODE_INT; + else + ndiv_mode = BHND_PMU1_PLL0_PC2_NDIV_MODE_MFB; + } else { + ndiv_mode = BHND_PMU1_PLL0_PC2_NDIV_MODE_MASH; + } + + + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, + BHND_PMU_SET_BITS(xt->ndiv_int, BHND_PMU1_PLL0_PC2_NDIV_INT) | + BHND_PMU_SET_BITS(ndiv_mode, BHND_PMU1_PLL0_PC2_NDIV_MODE), + BHND_PMU1_PLL0_PC2_NDIV_INT_MASK | + BHND_PMU1_PLL0_PC2_NDIV_MODE_MASK); + + /* Write ndiv_frac to pllcontrol[3] */ + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL3, + BHND_PMU_SET_BITS(xt->ndiv_frac, BHND_PMU1_PLL0_PC3_NDIV_FRAC), + BHND_PMU1_PLL0_PC3_NDIV_FRAC_MASK); + + /* Writing to pllcontrol[4] */ + if (sc->cid.chip_id == BHND_CHIPID_BCM4319) { + uint8_t xs; + + if (!xt->ndiv_frac) + plldata = 0x200005c0; + else + plldata = 0x202C2820; + + if (FVCO < 1600) + xs = 4; + else + xs = 7; + + plldata &= ~(BHND_PMU1_PLL0_PC4_KVCO_XS_MASK); + plldata |= BHND_PMU_SET_BITS(xs, BHND_PMU1_PLL0_PC4_KVCO_XS); + BHND_PMU_WRITE_4(sc, BHND_PMU1_PLL0_PLLCTL4, plldata); + } + + /* Write clock driving strength to pllcontrol[5] */ + if (buf_strength) { + PMU_MSG(("Adjusting PLL buffer drive strength: %x\n", + buf_strength)); + + plldata = BHND_PMU_SET_BITS(buf_strength, + BHND_PMU1_PLL0_PC5_CLK_DRV); + pllmask = BHND_PMU1_PLL0_PC5_CLK_DRV_MASK; + + if (sc->cid.chip_id == BHND_CHIPID_BCM4319) { + pllmask |= + BHND_PMU1_PLL0_PC5_VCO_RNG_MASK | + BHND_PMU1_PLL0_PC5_PLL_CTRL_37_32_MASK; + + if (!xt->ndiv_frac) { + plldata |= BHND_PMU_SET_BITS(0x25, + BHND_PMU1_PLL0_PC5_PLL_CTRL_37_32); + } else { + plldata |= BHND_PMU_SET_BITS(0x15, + BHND_PMU1_PLL0_PC5_PLL_CTRL_37_32); + } + + if (FVCO >= 1600) { + plldata |= BHND_PMU_SET_BITS(0x1, + BHND_PMU1_PLL0_PC5_VCO_RNG); + } + } + + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL5, plldata, + pllmask); + } + + PMU_MSG(("Done pll\n")); + + /* to operate the 4319 usb in 24MHz/48MHz; chipcontrol[2][84:83] needs + * to be updated. + */ + if (sc->cid.chip_id == BHND_CHIPID_BCM4319 && + xt->fref != XTAL_FREQ_30000MHZ) + { + uint32_t pll_sel; + + switch (xt->fref) { + case XTAL_FREQ_24000MHZ: + pll_sel = BHND_PMU_CCTL_4319USB_24MHZ_PLL_SEL; + break; + case XTAL_FREQ_48000MHZ: + pll_sel = BHND_PMU_CCTL_4319USB_48MHZ_PLL_SEL; + break; + default: + panic("unsupported 4319USB XTAL frequency: %hu\n", + xt->fref); + } + + BHND_PMU_CCTRL_WRITE(sc, BHND_PMU1_PLL0_CHIPCTL2, + BHND_PMU_SET_BITS(pll_sel, BHND_PMU_CCTL_4319USB_XTAL_SEL), + BHND_PMU_CCTL_4319USB_XTAL_SEL_MASK); + } + + /* Flush deferred pll control registers writes */ + if (BHND_PMU_REV(sc) >= 2) + BHND_PMU_OR_4(sc, BHND_PMU_CTRL, BHND_PMU_CTRL_PLL_PLLCTL_UPD); + + /* Write XtalFreq. Set the divisor also. */ + pmuctrl = BHND_PMU_READ_4(sc, BHND_PMU_CTRL); + pmuctrl = ~(BHND_PMU_CTRL_ILP_DIV_MASK | BHND_PMU_CTRL_XTALFREQ_MASK); + pmuctrl |= BHND_PMU_SET_BITS(((xt->fref + 127) / 128) - 1, + BHND_PMU_CTRL_ILP_DIV); + pmuctrl |= BHND_PMU_SET_BITS(xt->xf, BHND_PMU_CTRL_XTALFREQ); + + if (sc->cid.chip_id == BHND_CHIPID_BCM4329 && sc->cid.chip_rev == 0) { + /* clear the htstretch before clearing HTReqEn */ + BHND_PMU_AND_4(sc, BHND_PMU_CLKSTRETCH, ~BHND_PMU_CLKSTRETCH); + pmuctrl &= ~BHND_PMU_CTRL_HT_REQ_EN; + } + + BHND_PMU_WRITE_4(sc, BHND_PMU_CTRL, pmuctrl); +} + +/* query the CPU clock frequency */ +static uint32_t +bhnd_pmu1_cpuclk0(struct bhnd_pmu_softc *sc) +{ + uint32_t tmp, m1div; +#ifdef BCMDBG + uint32_t ndiv_int, ndiv_frac, p2div, p1div, fvco; + uint32_t fref; +#endif + uint32_t FVCO = bhnd_pmu1_pllfvco0(sc); + + /* Read m1div from pllcontrol[1] */ + tmp = BHND_PMU_PLL_READ(sc, BHND_PMU1_PLL0_PLLCTL1); + m1div = BHND_PMU_GET_BITS(tmp, BHND_PMU1_PLL0_PC1_M1DIV); + +#ifdef BCMDBG + /* Read p2div/p1div from pllcontrol[0] */ + tmp = BHND_PMU_PLL_READ(sc, BHND_PMU1_PLL0_PLLCTL0); + p2div = BHND_PMU_GET_BITS(tmp, BHND_PMU1_PLL0_PC0_P2DIV); + p1div = BHND_PMU_GET_BITS(tmp, BHND_PMU1_PLL0_PC0_P1DIV); + + /* Calculate fvco based on xtal freq and ndiv and pdiv */ + tmp = BHND_PMU_PLL_READ(sc, BHND_PMU1_PLL0_PLLCTL2); + ndiv_int = BHND_PMU_GET_BITS(tmp, BHND_PMU1_PLL0_PC2_NDIV_INT); + + tmp = BHND_PMU_PLL_READ(sc, BHND_PMU1_PLL0_PLLCTL3); + ndiv_frac = BHND_PMU_GET_BITS(tmp, BHND_PMU1_PLL0_PC3_NDIV_FRAC); + + fref = bhnd_pmu1_alpclk0(sc) / 1000; + + fvco = (fref * ndiv_int) << 8; + fvco += (fref * (ndiv_frac >> 12)) >> 4; + fvco += (fref * (ndiv_frac & 0xfff)) >> 12; + fvco >>= 8; + fvco *= p2div; + fvco /= p1div; + fvco /= 1000; + fvco *= 1000; + + PMU_MSG(("bhnd_pmu1_cpuclk0: ndiv_int %u ndiv_frac %u p2div %u " + "p1div %u fvco %u\n", ndiv_int, ndiv_frac, p2div, p1div, fvco)); + + FVCO = fvco; +#endif /* BCMDBG */ + + /* Return ARM/SB clock */ + return (FVCO / m1div * 1000); +} + +/* initialize PLL */ +void +bhnd_pmu_pll_init(struct bhnd_pmu_softc *sc, u_int xtalfreq) +{ + uint32_t max_mask, min_mask; + uint32_t res_ht, res_pll; + + switch (sc->cid.chip_id) { + case BHND_CHIPID_BCM4312: + /* assume default works */ + break; + case BHND_CHIPID_BCM4322: + case BHND_CHIPID_BCM43221: + case BHND_CHIPID_BCM43231: + case BHND_CHIPID_BCM4342: + if (sc->cid.chip_rev != 0) + break; + + min_mask = BHND_PMU_READ_4(sc, BHND_PMU_MIN_RES_MASK); + max_mask = BHND_PMU_READ_4(sc, BHND_PMU_MIN_RES_MASK); + res_ht = PMURES_BIT(RES4322_HT_SI_AVAIL); + res_pll = PMURES_BIT(RES4322_SI_PLL_ON); + + /* Have to remove HT Avail request before powering off PLL */ + BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, ~res_ht); + BHND_PMU_AND_4(sc, BHND_PMU_MAX_RES_MASK, ~res_ht); + PMU_WAIT_CLKST(sc, 0, BHND_CCS_HTAVAIL); + + /* Make sure the PLL is off */ + BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, ~res_pll); + BHND_PMU_AND_4(sc, BHND_PMU_MAX_RES_MASK, ~res_pll); + PMU_WAIT_CLKST(sc, 0, BHND_CCS_HTAVAIL); + + DELAY(1000); + + BHND_PMU_PLL_WRITE(sc, BHND_PMU2_SI_PLL_PLLCTL, 0x380005c0, ~0); + DELAY(100); + + BHND_PMU_WRITE_4(sc, BHND_PMU_MAX_RES_MASK, max_mask); + DELAY(100); + BHND_PMU_WRITE_4(sc, BHND_PMU_MIN_RES_MASK, min_mask); + DELAY(100); + + break; + case BHND_CHIPID_BCM4325: + bhnd_pmu1_pllinit0(sc, xtalfreq); + break; + case BHND_CHIPID_BCM4328: + bhnd_pmu0_pllinit0(sc, xtalfreq); + break; + case BHND_CHIPID_BCM5354: + if (xtalfreq == 0) + xtalfreq = 25000; + bhnd_pmu0_pllinit0(sc, xtalfreq); + break; + case BHND_CHIPID_BCM4329: + if (xtalfreq == 0) + xtalfreq = 38400; + bhnd_pmu1_pllinit0(sc, xtalfreq); + break; + + case BHND_CHIPID_BCM4313: + case BHND_CHIPID_BCM43222: + case BHND_CHIPID_BCM43111: + case BHND_CHIPID_BCM43112: + case BHND_CHIPID_BCM43224: + case BHND_CHIPID_BCM43225: + case BHND_CHIPID_BCM43420: + case BHND_CHIPID_BCM43421: + case BHND_CHIPID_BCM43226: + case BHND_CHIPID_BCM43235: + case BHND_CHIPID_BCM43236: + case BHND_CHIPID_BCM43238: + case BHND_CHIPID_BCM43234: + case BHND_CHIPID_BCM43237: + case BHND_CHIPID_BCM4331: + case BHND_CHIPID_BCM43431: + case BHND_CHIPID_BCM43131: + case BHND_CHIPID_BCM43227: + case BHND_CHIPID_BCM43228: + case BHND_CHIPID_BCM43428: + case BHND_CHIPID_BCM6362: + /* assume default works */ + break; + + case BHND_CHIPID_BCM4315: + case BHND_CHIPID_BCM4319: + case BHND_CHIPID_BCM4336: + case BHND_CHIPID_BCM4330: + bhnd_pmu1_pllinit0(sc, xtalfreq); + break; + default: + PMU_MSG(("No PLL init done for chip %#hx rev %d pmurev %d\n", + sc->cid.chip_id, sc->cid.chip_rev, BHND_PMU_REV(sc))); + break; + } +} + +/* query alp/xtal clock frequency */ +uint32_t +bhnd_pmu_alp_clock(struct bhnd_pmu_softc *sc) +{ + uint32_t clock; + + clock = BHND_PMU_ALP_CLOCK; + switch (sc->cid.chip_id) { + case BHND_CHIPID_BCM4328: + case BHND_CHIPID_BCM5354: + clock = bhnd_pmu0_alpclk0(sc); + break; + case BHND_CHIPID_BCM4315: + case BHND_CHIPID_BCM4319: + case BHND_CHIPID_BCM4325: + case BHND_CHIPID_BCM4329: + case BHND_CHIPID_BCM4330: + case BHND_CHIPID_BCM4336: + clock = bhnd_pmu1_alpclk0(sc); + break; + case BHND_CHIPID_BCM4312: + case BHND_CHIPID_BCM4322: + case BHND_CHIPID_BCM43221: + case BHND_CHIPID_BCM43231: + case BHND_CHIPID_BCM43222: + case BHND_CHIPID_BCM43111: + case BHND_CHIPID_BCM43112: + case BHND_CHIPID_BCM43224: + case BHND_CHIPID_BCM43225: + case BHND_CHIPID_BCM43420: + case BHND_CHIPID_BCM43421: + case BHND_CHIPID_BCM43226: + case BHND_CHIPID_BCM43235: + case BHND_CHIPID_BCM43236: + case BHND_CHIPID_BCM43238: + case BHND_CHIPID_BCM43234: + case BHND_CHIPID_BCM43237: + case BHND_CHIPID_BCM4331: + case BHND_CHIPID_BCM43431: + case BHND_CHIPID_BCM43131: + case BHND_CHIPID_BCM43227: + case BHND_CHIPID_BCM43228: + case BHND_CHIPID_BCM43428: + case BHND_CHIPID_BCM6362: + case BHND_CHIPID_BCM4342: + case BHND_CHIPID_BCM4716: + case BHND_CHIPID_BCM4748: + case BHND_CHIPID_BCM47162: + case BHND_CHIPID_BCM4313: + case BHND_CHIPID_BCM5357: + case BHND_CHIPID_BCM4749: + case BHND_CHIPID_BCM53572: + /* always 20Mhz */ + clock = 20000 * 1000; + break; + case BHND_CHIPID_BCM5356: + case BHND_CHIPID_BCM4706: + /* always 25Mhz */ + clock = 25000 * 1000; + break; + default: + PMU_MSG(("No ALP clock specified " + "for chip %s rev %d pmurev %d, using default %d Hz\n", + bcm_chipname(sih->chip, chn, 8), sih->chiprev, + sih->pmurev, clock)); + break; + } + + return (clock); +} + +/* Find the output of the "m" pll divider given pll controls that start with + * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc. + */ +static uint32_t +bhnd_pmu5_clock(struct bhnd_pmu_softc *sc, u_int pll0, u_int m) +{ + uint32_t div; + uint32_t fc; + uint32_t ndiv; + uint32_t p1, p2; + uint32_t tmp; + + if ((pll0 & 3) || (pll0 > BHND_PMU4716_MAINPLL_PLL0)) { + PMU_ERROR(("%s: Bad pll0: %d\n", __func__, pll0)); + return (0); + } + + /* Strictly there is an m5 divider, but I'm not sure we use it */ + if ((m == 0) || (m > 4)) { + PMU_ERROR(("%s: Bad m divider: %d\n", __func__, m)); + return (0); + } + + if (sc->cid.chip_id == BHND_CHIPID_BCM5357 || + sc->cid.chip_id == BHND_CHIPID_BCM4749) + { + /* Detect failure in clock setting */ + tmp = BHND_CHIPC_READ_CHIPST(sc->chipc_dev); + if ((tmp & 0x40000) != 0) + return (133 * 1000000); + } + + + /* Fetch p1 and p2 */ + BHND_PMU_WRITE_4(sc, BHND_PMU_PLL_CONTROL_ADDR, + pll0 + BHND_PMU5_PLL_P1P2_OFF); + BHND_PMU_READ_4(sc, BHND_PMU_PLL_CONTROL_ADDR); + + tmp = BHND_PMU_READ_4(sc, BHND_PMU_PLL_CONTROL_DATA); + p1 = BHND_PMU_GET_BITS(tmp, BHND_PMU5_PLL_P1); + p2 = BHND_PMU_GET_BITS(tmp, BHND_PMU5_PLL_P2); + + /* Fetch div */ + BHND_PMU_WRITE_4(sc, BHND_PMU_PLL_CONTROL_ADDR, + pll0 + BHND_PMU5_PLL_M14_OFF); + BHND_PMU_READ_4(sc, BHND_PMU_PLL_CONTROL_ADDR); + + tmp = BHND_PMU_READ_4(sc, BHND_PMU_PLL_CONTROL_DATA); + div = (tmp >> ((m - 1) * BHND_PMU5_PLL_MDIV_WIDTH)); + div &= BHND_PMU5_PLL_MDIV_MASK; + + /* Fetch ndiv */ + BHND_PMU_WRITE_4(sc, BHND_PMU_PLL_CONTROL_ADDR, + pll0 + BHND_PMU5_PLL_NM5_OFF); + BHND_PMU_READ_4(sc, BHND_PMU_PLL_CONTROL_ADDR); + + tmp = BHND_PMU_READ_4(sc, BHND_PMU_PLL_CONTROL_DATA); + ndiv = BHND_PMU_GET_BITS(tmp, BHND_PMU5_PLL_NDIV); + + /* Do calculation in Mhz */ + fc = bhnd_pmu_alp_clock(sc) / 1000000; + fc = (p1 * ndiv * fc) / p2; + + PMU_MSG(("%s: p1=%d, p2=%d, ndiv=%d(0x%x), m%d=%d; fc=%d, clock=%d\n", + __func__, p1, p2, ndiv, ndiv, m, div, fc, fc / div)); + + /* Return clock in Hertz */ + return ((fc / div) * 1000000); +} + +/* query backplane clock frequency */ +/* For designs that feed the same clock to both backplane + * and CPU just return the CPU clock speed. + */ +uint32_t +bhnd_pmu_si_clock(struct bhnd_pmu_softc *sc) +{ + uint32_t chipst; + uint32_t clock; + + clock = BHND_PMU_HT_CLOCK; + + switch (sc->cid.chip_id) { + case BHND_CHIPID_BCM4322: + case BHND_CHIPID_BCM43221: + case BHND_CHIPID_BCM43231: + case BHND_CHIPID_BCM43222: + case BHND_CHIPID_BCM43111: + case BHND_CHIPID_BCM43112: + case BHND_CHIPID_BCM43224: + case BHND_CHIPID_BCM43420: + case BHND_CHIPID_BCM43225: + case BHND_CHIPID_BCM43421: + case BHND_CHIPID_BCM43226: + case BHND_CHIPID_BCM4331: + case BHND_CHIPID_BCM43431: + case BHND_CHIPID_BCM6362: + case BHND_CHIPID_BCM4342: + /* 96MHz backplane clock */ + clock = 96000 * 1000; + break; + + case BHND_CHIPID_BCM4716: + case BHND_CHIPID_BCM4748: + case BHND_CHIPID_BCM47162: + clock = bhnd_pmu5_clock(sc, BHND_PMU4716_MAINPLL_PLL0, + BHND_PMU5_MAINPLL_SI); + break; + + case BHND_CHIPID_BCM4325: + clock = bhnd_pmu1_cpuclk0(sc); + break; + + case BHND_CHIPID_BCM4328: + clock = bhnd_pmu0_cpuclk0(sc); + break; + + case BHND_CHIPID_BCM4329: + if (sc->cid.chip_rev == 0) + clock = 38400 * 1000; + else + clock = bhnd_pmu1_cpuclk0(sc); + break; + + case BHND_CHIPID_BCM4315: + case BHND_CHIPID_BCM4319: + case BHND_CHIPID_BCM4336: + case BHND_CHIPID_BCM4330: + clock = bhnd_pmu1_cpuclk0(sc); + break; + + case BHND_CHIPID_BCM4313: + /* 80MHz backplane clock */ + clock = 80000 * 1000; + break; + + case BHND_CHIPID_BCM43234: + case BHND_CHIPID_BCM43235: + case BHND_CHIPID_BCM43236: + case BHND_CHIPID_BCM43238: + chipst = BHND_CHIPC_READ_CHIPST(sc->chipc_dev); + if (chipst & CHIPC_CST43236_BP_CLK) + clock = 120000 * 1000; + else + clock = 96000 * 1000; + break; + case BHND_CHIPID_BCM43237: + chipst = BHND_CHIPC_READ_CHIPST(sc->chipc_dev); + if (chipst & CHIPC_CST43237_BP_CLK) + clock = 96000 * 1000; + else + clock = 80000 * 1000; + break; + case BHND_CHIPID_BCM5356: + clock = bhnd_pmu5_clock(sc, BHND_PMU5356_MAINPLL_PLL0, + BHND_PMU5_MAINPLL_SI); + break; + case BHND_CHIPID_BCM5357: + case BHND_CHIPID_BCM4749: + clock = bhnd_pmu5_clock(sc, BHND_PMU5357_MAINPLL_PLL0, + BHND_PMU5_MAINPLL_SI); + break; + case BHND_CHIPID_BCM53572: + clock = 75000000; + break; + default: + device_printf(sc->dev, "No backplane clock specified for chip " + "%#hx rev %hhd pmurev %hhd, using default %dHz\n", + sc->cid.chip_id, sc->cid.chip_rev, BHND_PMU_REV(sc), clock); + break; + } + + return (clock); +} + +/* query CPU clock frequency */ +uint32_t +bhnd_pmu_cpu_clock(struct bhnd_pmu_softc *sc) +{ + uint32_t clock; + + if (sc->cid.chip_id == BHND_CHIPID_BCM5354) + return (240 * 1000 * 1000); /* 240MHz */ + + /* 5354 chip uses a non programmable PLL of frequency 240MHz */ + if (sc->cid.chip_id == BHND_CHIPID_BCM5354) + return (240000000); + + if (sc->cid.chip_id == BHND_CHIPID_BCM53572) + return (300000000); + + if (BHND_PMU_REV(sc) >= 5 && + sc->cid.chip_id != BHND_CHIPID_BCM4329 && + sc->cid.chip_id != BHND_CHIPID_BCM4319 && + sc->cid.chip_id != BHND_CHIPID_BCM43234 && + sc->cid.chip_id != BHND_CHIPID_BCM43235 && + sc->cid.chip_id != BHND_CHIPID_BCM43236 && + sc->cid.chip_id != BHND_CHIPID_BCM43237 && + sc->cid.chip_id != BHND_CHIPID_BCM43238 && + sc->cid.chip_id != BHND_CHIPID_BCM4336 && + sc->cid.chip_id != BHND_CHIPID_BCM4330) + { + u_int pll; + + switch (sc->cid.chip_id) { + case BHND_CHIPID_BCM5356: + pll = BHND_PMU5356_MAINPLL_PLL0; + break; + case BHND_CHIPID_BCM5357: + case BHND_CHIPID_BCM4749: + pll = BHND_PMU5357_MAINPLL_PLL0; + break; + default: + pll = BHND_PMU4716_MAINPLL_PLL0; + break; + } + + clock = bhnd_pmu5_clock(sc, pll, BHND_PMU5_MAINPLL_CPU); + } else { + clock = bhnd_pmu_si_clock(sc); + } + + return (clock); +} + +/* query memory clock frequency */ +uint32_t +bhnd_pmu_mem_clock(struct bhnd_pmu_softc *sc) +{ + uint32_t clock; + + if (BHND_PMU_REV(sc) >= 5 && + sc->cid.chip_id != BHND_CHIPID_BCM4329 && + sc->cid.chip_id != BHND_CHIPID_BCM4319 && + sc->cid.chip_id != BHND_CHIPID_BCM43234 && + sc->cid.chip_id != BHND_CHIPID_BCM43235 && + sc->cid.chip_id != BHND_CHIPID_BCM43236 && + sc->cid.chip_id != BHND_CHIPID_BCM43237 && + sc->cid.chip_id != BHND_CHIPID_BCM43238 && + sc->cid.chip_id != BHND_CHIPID_BCM4336 && + sc->cid.chip_id != BHND_CHIPID_BCM4330) + { + u_int pll; + + switch (sc->cid.chip_id) { + case BHND_CHIPID_BCM5356: + pll = BHND_PMU5356_MAINPLL_PLL0; + break; + case BHND_CHIPID_BCM5357: + case BHND_CHIPID_BCM4749: + pll = BHND_PMU5357_MAINPLL_PLL0; + break; + default: + pll = BHND_PMU4716_MAINPLL_PLL0; + break; + } + + clock = bhnd_pmu5_clock(sc, pll, BHND_PMU5_MAINPLL_MEM); + } else { + clock = bhnd_pmu_si_clock(sc); + } + + return (clock); +} + +/* Measure ILP clock frequency */ +#define ILP_CALC_DUR 10 /* ms, make sure 1000 can be divided by it. */ + +uint32_t +bhnd_pmu_ilp_clock(struct bhnd_pmu_softc *sc) +{ + uint32_t start, end, delta; + + if (sc->ilp_cps == 0) { + start = BHND_PMU_READ_4(sc, BHND_PMU_TIMER); + DELAY(ILP_CALC_DUR); + end = BHND_PMU_READ_4(sc, BHND_PMU_TIMER); + delta = end - start; + sc->ilp_cps = delta * (1000 / ILP_CALC_DUR); + } + + return (sc->ilp_cps); +} + +/* SDIO Pad drive strength to select value mappings */ +typedef struct { + uint8_t strength; /* Pad Drive Strength in mA */ + uint8_t sel; /* Chip-specific select value */ +} sdiod_drive_str_t; + +/* SDIO Drive Strength to sel value table for PMU Rev 1 */ +static const sdiod_drive_str_t sdiod_drive_strength_tab1[] = { + { + 4, 0x2}, { + 2, 0x3}, { + 1, 0x0}, { + 0, 0x0} + }; + +/* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */ +static const sdiod_drive_str_t sdiod_drive_strength_tab2[] = { + { + 12, 0x7}, { + 10, 0x6}, { + 8, 0x5}, { + 6, 0x4}, { + 4, 0x2}, { + 2, 0x1}, { + 0, 0x0} + }; + +/* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */ +static const sdiod_drive_str_t sdiod_drive_strength_tab3[] = { + { + 32, 0x7}, { + 26, 0x6}, { + 22, 0x5}, { + 16, 0x4}, { + 12, 0x3}, { + 8, 0x2}, { + 4, 0x1}, { + 0, 0x0} + }; + +#define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu)) + +void +bhnd_pmu_sdiod_drive_strength_init(struct bhnd_pmu_softc *sc, + uint32_t drivestrength) +{ + const sdiod_drive_str_t *str_tab; + uint32_t str_mask; + uint32_t str_shift; + u_int intr_val; + + str_tab = NULL; + str_mask = 0; + str_shift = 0; + intr_val = 0; + + switch (SDIOD_DRVSTR_KEY(sc->cid.chip_id, BHND_PMU_REV(sc))) { + case SDIOD_DRVSTR_KEY(BHND_CHIPID_BCM4325, 1): + str_tab = sdiod_drive_strength_tab1; + str_mask = 0x30000000; + str_shift = 28; + break; + case SDIOD_DRVSTR_KEY(BHND_CHIPID_BCM4325, 2): + case SDIOD_DRVSTR_KEY(BHND_CHIPID_BCM4325, 3): + case SDIOD_DRVSTR_KEY(BHND_CHIPID_BCM4315, 4): + case SDIOD_DRVSTR_KEY(BHND_CHIPID_BCM4319, 7): + str_tab = sdiod_drive_strength_tab2; + str_mask = 0x00003800; + str_shift = 11; + break; + case SDIOD_DRVSTR_KEY(BHND_CHIPID_BCM4336, 8): + str_tab = sdiod_drive_strength_tab3; + str_mask = 0x00003800; + str_shift = 11; + break; + + default: + device_printf(sc->dev, "No SDIO Drive strength init done for " + "chip %#x rev %hhd pmurev %hhd\n", sc->cid.chip_id, + sc->cid.chip_rev, BHND_PMU_REV(sc)); + break; + } + + if (str_tab != NULL) { + uint32_t drivestrength_sel = 0; + uint32_t cc_data_temp; + + for (u_int i = 0; str_tab[i].strength != 0; i++) { + if (drivestrength >= str_tab[i].strength) { + drivestrength_sel = str_tab[i].sel; + break; + } + } + + cc_data_temp = BHND_PMU_CCTRL_READ(sc, 1); + cc_data_temp &= ~str_mask; + drivestrength_sel <<= str_shift; + cc_data_temp |= drivestrength_sel; + BHND_PMU_CCTRL_WRITE(sc, 1, cc_data_temp, ~0); + + PMU_MSG(("SDIO: %dmA drive strength selected, set to 0x%08x\n", + drivestrength, cc_data_temp)); + } +} + +/** + * Initialize the PMU. + */ +int +bhnd_pmu_init(struct bhnd_pmu_softc *sc) +{ + uint32_t xtalfreq; + int error; + + if (BHND_PMU_REV(sc) == 1) { + BHND_PMU_AND_4(sc, BHND_PMU_CTRL, ~BHND_PMU_CTRL_NOILP_ON_WAIT); + } else if (BHND_PMU_REV(sc) >= 2) { + BHND_PMU_OR_4(sc, BHND_PMU_CTRL, BHND_PMU_CTRL_NOILP_ON_WAIT); + } + + if (sc->cid.chip_id == BHND_CHIPID_BCM4329 && sc->cid.chip_rev == 2) { + /* Fix for 4329b0 bad LPOM state. */ + BHND_PMU_REGCTRL_WRITE(sc, 2, 0x100, ~0); + BHND_PMU_REGCTRL_WRITE(sc, 3, 0x4, ~0); + } + + if (sc->cid.chip_id == BHND_CHIPID_BCM4319) { + /* Limiting the PALDO spike during init time */ + BHND_PMU_REGCTRL_WRITE(sc, 2, 0x00000005, 0x00000007); + } + + + /* Fetch target xtalfreq, in KHz */ + error = bhnd_nvram_getvar_uint32(sc->chipc_dev, BHND_NVAR_XTALFREQ, + &xtalfreq); + + /* If not available, log any real errors, and then try to measure it */ + if (error) { + if (error != ENOENT) { + device_printf(sc->dev, "error fetching xtalfreq: %d\n", + error); + } + + xtalfreq = bhnd_pmu_measure_alpclk(sc); + } + + /* Perform PLL initialization */ + bhnd_pmu_pll_init(sc, xtalfreq); + + if ((error = bhnd_pmu_res_init(sc))) + return (error); + + bhnd_pmu_swreg_init(sc); + + return (0); +} + +/* Return up time in ILP cycles for the given resource. */ +static int +bhnd_pmu_res_uptime(struct bhnd_pmu_softc *sc, uint8_t rsrc, uint32_t *uptime) +{ + uint32_t deps; + uint32_t up, dup, dmax; + uint32_t min_mask; + int error; + + /* uptime of resource 'rsrc' */ + BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, rsrc); + up = BHND_PMU_READ_4(sc, BHND_PMU_RES_UPDN_TIMER); + up = BHND_PMU_GET_BITS(up, BHND_PMU_RES_UPDN_UPTME); + + /* Find direct dependencies of resource 'rsrc' */ + deps = bhnd_pmu_res_deps(sc, BHND_PMURES_BIT(rsrc), false); + for (uint8_t i = 0; i <= BHND_PMU_RESNUM_MAX; i++) { + if (!(deps & BHND_PMURES_BIT(i))) + continue; + deps &= ~bhnd_pmu_res_deps(sc, BHND_PMURES_BIT(i), true); + } + + /* Exclude the minimum resource set */ + if ((error = bhnd_pmu_res_masks(sc, &min_mask, NULL))) + return (error); + + deps &= ~min_mask; + + /* max uptime of direct dependencies */ + dmax = 0; + for (uint8_t i = 0; i <= BHND_PMU_RESNUM_MAX; i++) { + if (!(deps & BHND_PMURES_BIT(i))) + continue; + + if ((error = bhnd_pmu_res_uptime(sc, i, &dup))) + return (error); + + if (dmax < dup) + dmax = dup; + } + + PMU_MSG(("bhnd_pmu_res_uptime: rsrc %hhu uptime %u(deps 0x%08x " + "uptime %u)\n", rsrc, up, deps, dmax)); + + *uptime = (up + dmax + BHND_PMURES_UP_TRANSITION); + return (0); +} + +/* Return dependencies (direct or all/indirect) for the given resources */ +static uint32_t +bhnd_pmu_res_deps(struct bhnd_pmu_softc *sc, uint32_t rsrcs, bool all) +{ + uint32_t deps; + + deps = 0; + for (uint8_t i = 0; i <= BHND_PMU_RESNUM_MAX; i++) { + if (!(rsrcs & BHND_PMURES_BIT(i))) + continue; + + BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, i); + deps |= BHND_PMU_READ_4(sc, BHND_PMU_RES_DEP_MASK); + } + + /* None found? */ + if (deps == 0) + return (0); + + /* Recurse dependencies */ + if (all) + deps |= bhnd_pmu_res_deps(sc, deps, true); + + return (deps); +} + +/* power up/down OTP through PMU resources */ +int +bhnd_pmu_otp_power(struct bhnd_pmu_softc *sc, bool on) +{ + uint32_t deps; + uint32_t min_mask; + uint32_t rsrcs; + int error; + + /* Determine rsrcs to turn on/off OTP power */ + switch (sc->cid.chip_id) { + case BHND_CHIPID_BCM4322: + case BHND_CHIPID_BCM43221: + case BHND_CHIPID_BCM43231: + case BHND_CHIPID_BCM4342: + rsrcs = PMURES_BIT(RES4322_OTP_PU); + break; + case BHND_CHIPID_BCM4315: + rsrcs = PMURES_BIT(RES4315_OTP_PU); + break; + case BHND_CHIPID_BCM4325: + rsrcs = PMURES_BIT(RES4325_OTP_PU); + break; + case BHND_CHIPID_BCM4329: + rsrcs = PMURES_BIT(RES4329_OTP_PU); + break; + case BHND_CHIPID_BCM4319: + rsrcs = PMURES_BIT(RES4319_OTP_PU); + break; + case BHND_CHIPID_BCM4336: + rsrcs = PMURES_BIT(RES4336_OTP_PU); + break; + case BHND_CHIPID_BCM4330: + rsrcs = PMURES_BIT(RES4330_OTP_PU); + break; + default: + /* Not required? */ + return (0); + } + + /* Fetch all dependencies */ + deps = bhnd_pmu_res_deps(sc, rsrcs, true); + + /* Exclude the minimum resource set */ + if ((error = bhnd_pmu_res_masks(sc, &min_mask, NULL))) + return (error); + + deps &= ~min_mask; + + /* Turn on/off the power */ + if (on) { + uint32_t state; + + PMU_MSG(("Adding rsrc 0x%x to min_res_mask\n", + rsrcs | deps)); + BHND_PMU_OR_4(sc, BHND_PMU_MIN_RES_MASK, (rsrcs|deps)); + + /* Wait for all resources to become available */ + for (int i = 0; i < BHND_PMU_MAX_TRANSITION_DLY; i += 10) { + state = BHND_PMU_READ_4(sc, BHND_PMU_RES_STATE); + if ((state & rsrcs) == rsrcs) + break; + + DELAY(10); + } + + if ((state & rsrcs) != rsrcs) { + device_printf(sc->dev, "timeout waiting for OTP " + "resource enable\n"); + return (ENXIO); + } + } else { + PMU_MSG(("Removing rsrc 0x%x from min_res_mask\n", + rsrcs | deps)); + BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, ~(rsrcs|deps)); + } + + return (0); +} + +void +bhnd_pmu_rcal(struct bhnd_pmu_softc *sc) +{ + uint32_t chipst; + uint32_t val; + uint8_t rcal_code; + bool bluetooth_rcal; + + + bluetooth_rcal = false; + + switch (sc->cid.chip_id) { + case BHND_CHIPID_BCM4325: + case BHND_CHIPID_BCM4329: + /* Kick RCal */ + BHND_PMU_WRITE_4(sc, BHND_PMU_CHIPCTL_ADDR, 1); + + /* Power Down RCAL Block */ + BHND_PMU_AND_4(sc, BHND_PMU_CHIPCTL_DATA, ~0x04); + + if (sc->cid.chip_id == BHND_CHIPID_BCM4325) { + chipst = BHND_CHIPC_READ_CHIPST(sc->chipc_dev); + if (BHND_PMU_GET_BITS(chipst, CHIPC_CST4325_RCAL_VALID)) + bluetooth_rcal = true; + } + + /* Power Up RCAL block */ + BHND_PMU_AND_4(sc, BHND_PMU_CHIPCTL_DATA, 0x04); + + /* Wait for completion */ + for (int i = 0; i < (10 * 1000 * 1000); i++) { + chipst = BHND_CHIPC_READ_CHIPST(sc->chipc_dev); + + if (chipst & 0x08) + break; + + DELAY(10); + } + KASSERT((chipst & 0x08) != 0, ("rcal completion timeout")); + + if (bluetooth_rcal) { + rcal_code = 0x6; + } else { + /* Drop LSB to convert from 5 bit code to 4 bit code */ + rcal_code = (uint8_t) (chipst >> 5) & 0x0f; + } + + PMU_MSG(("RCal completed, status 0x%x, code 0x%x\n", + R_REG(&cc->chipstatus), rcal_code)); + + /* Write RCal code into pmu_vreg_ctrl[32:29] */ + BHND_PMU_WRITE_4(sc, BHND_PMU_REG_CONTROL_ADDR, 0); + val = BHND_PMU_READ_4(sc, BHND_PMU_REG_CONTROL_DATA); + val &= ~((uint32_t) 0x07 << 29); + val |= (uint32_t) (rcal_code & 0x07) << 29; + BHND_PMU_WRITE_4(sc, BHND_PMU_REG_CONTROL_DATA, val); + + BHND_PMU_WRITE_4(sc, BHND_PMU_REG_CONTROL_ADDR, 1); + val = BHND_PMU_READ_4(sc, BHND_PMU_REG_CONTROL_DATA); + val &= ~(uint32_t) 0x01; + val |= (uint32_t) ((rcal_code >> 3) & 0x01); + BHND_PMU_WRITE_4(sc, BHND_PMU_REG_CONTROL_DATA, val); + + /* Write RCal code into pmu_chip_ctrl[33:30] */ + BHND_PMU_WRITE_4(sc, BHND_PMU_CHIPCTL_ADDR, 0); + val = BHND_PMU_READ_4(sc, BHND_PMU_CHIPCTL_DATA); + val &= ~((uint32_t) 0x03 << 30); + val |= (uint32_t) (rcal_code & 0x03) << 30; + BHND_PMU_WRITE_4(sc, BHND_PMU_CHIPCTL_DATA, val); + + BHND_PMU_WRITE_4(sc, BHND_PMU_CHIPCTL_ADDR, 1); + val = BHND_PMU_READ_4(sc, BHND_PMU_CHIPCTL_DATA); + val &= ~(uint32_t) 0x03; + val |= (uint32_t) ((rcal_code >> 2) & 0x03); + BHND_PMU_WRITE_4(sc, BHND_PMU_CHIPCTL_DATA, val); + + /* Set override in pmu_chip_ctrl[29] */ + BHND_PMU_WRITE_4(sc, BHND_PMU_CHIPCTL_ADDR, 0); + BHND_PMU_OR_4(sc, BHND_PMU_CHIPCTL_DATA, (0x01 << 29)); + + /* Power off RCal block */ + BHND_PMU_WRITE_4(sc, BHND_PMU_CHIPCTL_ADDR, 1); + BHND_PMU_AND_4(sc, BHND_PMU_CHIPCTL_DATA, ~0x04); + break; + default: + break; + } +} + +void +bhnd_pmu_spuravoid(struct bhnd_pmu_softc *sc, uint8_t spuravoid) +{ + /* force the HT off */ + if (sc->cid.chip_id == BHND_CHIPID_BCM4336) { + BHND_PMU_AND_4(sc, BHND_PMU_MAX_RES_MASK, + ~BHND_PMU_RES4336_HT_AVAIL); + + /* wait for the ht to really go away */ + PMU_WAIT_CLKST(sc, 0, BHND_CCS_HTAVAIL); + } + + /* update the pll changes */ + bhnd_pmu_spuravoid_pllupdate(sc, spuravoid); + + /* enable HT back on */ + if (sc->cid.chip_id == BHND_CHIPID_BCM4336) { + BHND_PMU_OR_4(sc, BHND_PMU_MAX_RES_MASK, + BHND_PMU_RES4336_HT_AVAIL); + } +} + +static void +bhnd_pmu_spuravoid_pllupdate(struct bhnd_pmu_softc *sc, uint8_t spuravoid) +{ + uint16_t chip_id; + uint32_t tmp; + uint32_t pmuctrl; + uint8_t phypll_offset; + + uint8_t bcm5357_bcm43236_p1div[] = { 0x1, 0x5, 0x5 }; + uint8_t bcm5357_bcm43236_ndiv[] = { 0x30, 0xf6, 0xfc }; + + /* 6362a0 has same clks as 4322[4-6] */ + chip_id = sc->cid.chip_id; + if (chip_id == BHND_CHIPID_BCM6362 && sc->cid.chip_rev == 0) { + chip_id = BHND_CHIPID_BCM43224; + } + + switch (chip_id) { + case BHND_CHIPID_BCM6362: + KASSERT(sc->cid.chip_rev != 0, ("invalid clock config")); + /* fallthrough */ + case BHND_CHIPID_BCM5357: + case BHND_CHIPID_BCM4749: + case BHND_CHIPID_BCM43235: + case BHND_CHIPID_BCM43236: + case BHND_CHIPID_BCM43238: + case BHND_CHIPID_BCM43234: + case BHND_CHIPID_BCM43237: + case BHND_CHIPID_BCM53572: + KASSERT(spuravoid < nitems(bcm5357_bcm43236_p1div), + ("spuravoid %hhu outside p1div table\n", spuravoid)); + + KASSERT(spuravoid < nitems(bcm5357_bcm43236_ndiv), + ("spuravoid %hhu outside ndiv table\n", spuravoid)); + + /* BCM5357 needs to touch PLL1_PLLCTL[02], so offset + * PLL0_PLLCTL[02] by 6 */ + phypll_offset = 0; + if (sc->cid.chip_id == BHND_CHIPID_BCM5357) + phypll_offset = 6; + + /* RMW only the P1 divider */ + tmp = BHND_PMU_SET_BITS(bcm5357_bcm43236_p1div[spuravoid], + BHND_PMU1_PLL0_PC0_P1DIV); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0 + phypll_offset, + tmp, BHND_PMU1_PLL0_PC0_P1DIV_MASK); + + /* RMW only the int feedback divider */ + tmp = BHND_PMU_SET_BITS(bcm5357_bcm43236_ndiv[spuravoid], + BHND_PMU1_PLL0_PC2_NDIV_INT); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2 + phypll_offset, + tmp, BHND_PMU1_PLL0_PC0_P1DIV_MASK); + + pmuctrl = BHND_PMU_CTRL_PLL_PLLCTL_UPD; + break; + + case BHND_CHIPID_BCM4331: + if (spuravoid == 2) { + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, + 0x11500014, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, + 0x0FC00a08, ~0); + } else if (spuravoid == 1) { + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, + 0x11500014, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, + 0x0F600a08, ~0); + } else { + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, + 0x11100014, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, + 0x03000a08, ~0); + } + pmuctrl = BHND_PMU_CTRL_PLL_PLLCTL_UPD; + break; + + case BHND_CHIPID_BCM43224: + case BHND_CHIPID_BCM43225: + case BHND_CHIPID_BCM43226: + case BHND_CHIPID_BCM43421: + if (spuravoid == 1) { + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, + 0x11500010, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, + 0x000C0C06, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, + 0x0F600a08, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL3, + 0x00000000, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL4, + 0x2001E920, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL5, + 0x88888815, ~0); + } else { + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, + 0x11100010, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, + 0x000c0c06, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, + 0x03000a08, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL3, + 0x00000000, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL4, + 0x200005c0, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL5, + 0x88888815, ~0); + } + pmuctrl = BHND_PMU_CTRL_PLL_PLLCTL_UPD; + break; + + case BHND_CHIPID_BCM43111: + case BHND_CHIPID_BCM43112: + case BHND_CHIPID_BCM43222: + case BHND_CHIPID_BCM43420: + if (spuravoid == 1) { + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, + 0x11500008, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, + 0x0c000c06, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, + 0x0f600a08, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL3, + 0x00000000, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL4, + 0x2001e920, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL5, + 0x88888815, ~0); + } else { + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, + 0x11100008, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, + 0x0c000c06, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, + 0x03000a08, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL3, + 0x00000000, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL4, + 0x200005c0, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL5, + 0x88888855, ~0); + } + + pmuctrl = BHND_PMU_CTRL_PLL_PLLCTL_UPD; + break; + + case BHND_CHIPID_BCM4716: + case BHND_CHIPID_BCM4748: + case BHND_CHIPID_BCM47162: + if (spuravoid == 1) { + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, + 0x11500060, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, + 0x080C0C06, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, + 0x0F600000, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL3, + 0x00000000, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL4, + 0x2001E924, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL5, + 0x88888815, ~0); + } else { + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, + 0x11100060, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, + 0x080c0c06, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, + 0x03000000, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL3, + 0x00000000, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL4, + 0x200005c0, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL5, + 0x88888815, ~0); + } + + pmuctrl = BHND_PMU_CTRL_NOILP_ON_WAIT | + BHND_PMU_CTRL_PLL_PLLCTL_UPD; + break; + + case BHND_CHIPID_BCM4319: + break; + + case BHND_CHIPID_BCM4322: + case BHND_CHIPID_BCM43221: + case BHND_CHIPID_BCM43231: + case BHND_CHIPID_BCM4342: + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, 0x11100070, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, 0x1014140a, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL5, 0x88888854, ~0); + + if (spuravoid == 1) { + /* spur_avoid ON, enable 41/82/164Mhz clock mode */ + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, + 0x05201828, ~0); + } else { + /* enable 40/80/160Mhz clock mode */ + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, + 0x05001828, ~0); + } + + pmuctrl = BHND_PMU_CTRL_PLL_PLLCTL_UPD; + break; + + case BHND_CHIPID_BCM4336: + /* Looks like these are only for default xtal freq 26MHz */ + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, 0x02100020, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, 0x0C0C0C0C, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, 0x01240C0C, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL4, 0x202C2820, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL5, 0x88888825, ~0); + + if (spuravoid == 1) { + tmp = 0x00EC4EC4; + } else { + tmp = 0x00762762; + } + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL3, tmp, ~0); + + + pmuctrl = BHND_PMU_CTRL_PLL_PLLCTL_UPD; + break; + case BHND_CHIPID_BCM43131: + case BHND_CHIPID_BCM43227: + case BHND_CHIPID_BCM43228: + case BHND_CHIPID_BCM43428: + /* LCNXN */ + /* PLL Settings for spur avoidance on/off mode, no on2 support + * for 43228A0 */ + if (spuravoid == 1) { + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, + 0x01100014, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, + 0x040C0C06, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, + 0x03140A08, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL3, + 0x00333333, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL4, + 0x202C2820, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL5, + 0x88888815, ~0); + } else { + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, + 0x11100014, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, + 0x040c0c06, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, + 0x03000a08, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL3, + 0x00000000, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL4, + 0x200005c0, ~0); + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL5, + 0x88888815, ~0); + } + pmuctrl = BHND_PMU_CTRL_PLL_PLLCTL_UPD; + break; + default: + PMU_ERROR(("%s: unknown spuravoidance settings for chip %#hx, " + "not changing PLL\n", __func__, sc->cid.chip_id)); + break; + } + + BHND_PMU_OR_4(sc, BHND_PMU_CTRL, pmuctrl); +} + +bool +bhnd_pmu_is_otp_powered(struct bhnd_pmu_softc *sc) +{ + uint32_t otp_res; + + /* Determine per-chip OTP resource */ + switch (sc->cid.chip_id) { + case BHND_CHIPID_BCM4329: + otp_res = PMURES_BIT(RES4329_OTP_PU); + break; + case BHND_CHIPID_BCM4319: + otp_res = PMURES_BIT(RES4319_OTP_PU); + break; + case BHND_CHIPID_BCM4336: + otp_res = PMURES_BIT(RES4336_OTP_PU); + break; + case BHND_CHIPID_BCM4330: + otp_res = PMURES_BIT(RES4330_OTP_PU); + break; + + /* These chips don't use PMU bit to power up/down OTP. OTP always on. + * Use OTP_INIT command to reset/refresh state. + */ + case BHND_CHIPID_BCM43224: + case BHND_CHIPID_BCM43225: + case BHND_CHIPID_BCM43421: + case BHND_CHIPID_BCM43236: + case BHND_CHIPID_BCM43235: + case BHND_CHIPID_BCM43238: + return (true); + + default: + return (true); + } + + /* Check resource state */ + if ((BHND_PMU_READ_4(sc, BHND_PMU_RES_STATE) & otp_res) == 0) + return (false); + + return (true); +} + +void +bhnd_pmu_paref_ldo_enable(struct bhnd_pmu_softc *sc, bool enable) +{ + uint32_t ldo; + + switch (sc->cid.chip_id) { + case BHND_CHIPID_BCM4328: + ldo = PMURES_BIT(RES4328_PA_REF_LDO); + break; + case BHND_CHIPID_BCM5354: + ldo = PMURES_BIT(RES5354_PA_REF_LDO); + break; + case BHND_CHIPID_BCM4312: + ldo = PMURES_BIT(RES4312_PA_REF_LDO); + break; + default: + return; + } + + if (enable) { + BHND_PMU_OR_4(sc, BHND_PMU_MIN_RES_MASK, ldo); + } else { + BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, ~ldo); + } +} + +/* initialize PMU switch/regulators */ +void +bhnd_pmu_swreg_init(struct bhnd_pmu_softc *sc) +{ + uint32_t chipst; + + switch (sc->cid.chip_id) { + case BHND_CHIPID_BCM4325: + if (sc->cid.chip_rev <= 2) + break; + + chipst = BHND_CHIPC_READ_CHIPST(sc->chipc_dev); + if (BHND_PMU_GET_BITS(chipst, CHIPC_CST4325_PMUTOP_2B)) { + bhnd_pmu_set_ldo_voltage(sc, SET_LDO_VOLTAGE_CLDO_PWM, + 0xf); + bhnd_pmu_set_ldo_voltage(sc, SET_LDO_VOLTAGE_CLDO_BURST, + 0xf); + } + + bhnd_pmu_set_ldo_voltage(sc, SET_LDO_VOLTAGE_CBUCK_PWM, 0xb); + bhnd_pmu_set_ldo_voltage(sc, SET_LDO_VOLTAGE_CBUCK_BURST, 0xb); + + bhnd_pmu_set_ldo_voltage(sc, SET_LDO_VOLTAGE_LNLDO1, 0x1); + if (sc->board.board_flags & BHND_BFL_LNLDO2_2P5) { + bhnd_pmu_set_ldo_voltage(sc, SET_LDO_VOLTAGE_LNLDO2_SEL, + 0x1); + } + + break; + case BHND_CHIPID_BCM4336: + /* Reduce CLDO PWM output voltage to 1.2V */ + bhnd_pmu_set_ldo_voltage(sc, SET_LDO_VOLTAGE_CLDO_PWM, 0xe); + /* Reduce CLDO BURST output voltage to 1.2V */ + bhnd_pmu_set_ldo_voltage(sc, SET_LDO_VOLTAGE_CLDO_BURST, 0xe); + /* Reduce LNLDO1 output voltage to 1.2V */ + bhnd_pmu_set_ldo_voltage(sc, SET_LDO_VOLTAGE_LNLDO1, 0xe); + if (sc->cid.chip_rev == 0) + BHND_PMU_REGCTRL_WRITE(sc, 2, 0x400000, 0x400000); + break; + + case BHND_CHIPID_BCM4330: + /* CBUCK Voltage is 1.8 by default and set that to 1.5 */ + bhnd_pmu_set_ldo_voltage(sc, SET_LDO_VOLTAGE_CBUCK_PWM, 0); + break; + default: + break; + } +} + +void +bhnd_pmu_radio_enable(struct bhnd_pmu_softc *sc, device_t d11core, bool enable) +{ + uint32_t oobsel; + uint32_t rsrcs; + + if (bhnd_get_device(d11core) != BHND_COREID_D11) + panic("bhnd_pmu_radio_enable() called on non-D11 core"); + + switch (sc->cid.chip_id) { + case BHND_CHIPID_BCM4325: + if (sc->board.board_flags & BHND_BFL_FASTPWR) + break; + + if ((sc->board.board_flags & BHND_BFL_BUCKBOOST) == 0) + break; + + rsrcs = PMURES_BIT(RES4325_BUCK_BOOST_BURST); + + if (enable) { + BHND_PMU_OR_4(sc, BHND_PMU_MIN_RES_MASK, rsrcs); + DELAY(100 * 1000); /* 100ms */ + } else { + BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, ~rsrcs); + } + + break; + case BHND_CHIPID_BCM4319: + oobsel = bhnd_read_config(d11core, BCMA_DMP_OOBSELOUTB74, 4); + + if (enable) { + oobsel |= BHND_PMU_SET_BITS(BCMA_DMP_OOBSEL_EN, + BCMA_DMP_OOBSEL_1); + oobsel |= BHND_PMU_SET_BITS(BCMA_DMP_OOBSEL_EN, + BCMA_DMP_OOBSEL_2); + } else { + oobsel &= ~BHND_PMU_SET_BITS(BCMA_DMP_OOBSEL_EN, + BCMA_DMP_OOBSEL_1); + oobsel &= ~BHND_PMU_SET_BITS(BCMA_DMP_OOBSEL_EN, + BCMA_DMP_OOBSEL_2); + } + + bhnd_write_config(d11core, BCMA_DMP_OOBSELOUTB74, oobsel, 4); + break; + } +} + +/* Wait for a particular clock level to be on the backplane */ +uint32_t +bhnd_pmu_waitforclk_on_backplane(struct bhnd_pmu_softc *sc, uint32_t clk, + uint32_t delay) +{ + uint32_t pmu_st; + + for (uint32_t i = 0; i < delay; i += 10) { + pmu_st = BHND_PMU_READ_4(sc, BHND_PMU_ST); + if ((pmu_st & clk) == clk) + return (clk); + + DELAY(10); + } + + pmu_st = BHND_PMU_READ_4(sc, BHND_PMU_ST); + return (pmu_st & clk); +} + +/* + * Measures the ALP clock frequency in KHz. Returns 0 if not possible. + * Possible only if PMU rev >= 10 and there is an external LPO 32768Hz crystal. + */ + +#define EXT_ILP_HZ 32768 + +uint32_t +bhnd_pmu_measure_alpclk(struct bhnd_pmu_softc *sc) +{ + uint32_t alp_khz; + uint32_t pmu_st; + + if (BHND_PMU_REV(sc) < 10) + return (0); + + pmu_st = BHND_PMU_READ_4(sc, BHND_PMU_ST); + if (pmu_st & BHND_PMU_ST_EXTLPOAVAIL) { + uint32_t alp_hz, ilp_ctr; + + /* Enable frequency measurement */ + BHND_PMU_WRITE_4(sc, BHND_PMU_XTALFREQ, 1U << + BHND_PMU_XTALFREQ_REG_MEASURE_SHIFT); + + /* Delay for well over 4 ILP clocks */ + DELAY(1000); + + /* Read the latched number of ALP ticks per 4 ILP ticks */ + ilp_ctr = BHND_PMU_READ_4(sc, BHND_PMU_XTALFREQ); + ilp_ctr = BHND_PMU_GET_BITS(ilp_ctr, + BHND_PMU_XTALFREQ_REG_ILPCTR); + + /* Turn off PMU_XTALFREQ_REG_MEASURE to save power */ + BHND_PMU_WRITE_4(sc, BHND_PMU_XTALFREQ, 0); + + /* Calculate ALP frequency */ + alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4; + + /* Round to nearest 100KHz and convert to KHz */ + alp_khz = (alp_hz + 50000) / 100000 * 100; + } else { + alp_khz = 0; + } + + return (alp_khz); +} + +static void +bhnd_pmu_set_4330_plldivs(struct bhnd_pmu_softc *sc) +{ + uint32_t FVCO = bhnd_pmu1_pllfvco0(sc) / 1000; + uint32_t m1div, m2div, m3div, m4div, m5div, m6div; + uint32_t pllc1, pllc2; + + m2div = m3div = m4div = m6div = FVCO / 80; + m5div = FVCO / 160; + + if (PMU_CST4330_SDIOD_CHIPMODE(sc)) + m1div = FVCO / 80; + else + m1div = FVCO / 90; + + pllc1 = 0; + pllc1 |= BHND_PMU_SET_BITS(m1div, BHND_PMU1_PLL0_PC1_M1DIV); + pllc1 |= BHND_PMU_SET_BITS(m2div, BHND_PMU1_PLL0_PC1_M2DIV); + pllc1 |= BHND_PMU_SET_BITS(m3div, BHND_PMU1_PLL0_PC1_M3DIV); + pllc1 |= BHND_PMU_SET_BITS(m4div, BHND_PMU1_PLL0_PC1_M4DIV); + + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL1, pllc1, ~0); + + pllc2 = 0; + pllc2 |= BHND_PMU_SET_BITS(m5div, BHND_PMU1_PLL0_PC2_M5DIV); + pllc2 |= BHND_PMU_SET_BITS(m6div, BHND_PMU1_PLL0_PC2_M6DIV); + + BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, pllc2, + BHND_PMU1_PLL0_PC2_M5DIV_MASK | BHND_PMU1_PLL0_PC2_M6DIV_MASK); +} Property changes on: head/sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/bhnd/cores/pmu/bhnd_pmureg.h =================================================================== --- head/sys/dev/bhnd/cores/pmu/bhnd_pmureg.h (nonexistent) +++ head/sys/dev/bhnd/cores/pmu/bhnd_pmureg.h (revision 304870) @@ -0,0 +1,712 @@ +/*- + * Copyright (c) 2015-2016 Landon Fuller + * Copyright (c) 2010 Broadcom Corporation + * All rights reserved. + * + * This file is derived from the sbchipc.h header contributed by Broadcom + * to to the Linux staging repository, as well as later revisions of sbchipc.h + * distributed with the Asus RT-N16 firmware source code release. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $FreeBSD$ + */ + +#ifndef _BHND_CORES_PMU_BHND_PMUREG_H_ +#define _BHND_CORES_PMU_BHND_PMUREG_H_ + +#define BHND_PMU_GET_FLAG(_value, _flag) \ + (((_value) & _flag) != 0) +#define BHND_PMU_GET_BITS(_value, _field) \ + (((_value) & _field ## _MASK) >> _field ## _SHIFT) +#define BHND_PMU_SET_BITS(_value, _field) \ + (((_value) & _field ## _MASK) >> _field ## _SHIFT) + +#define BHND_PMU_ILP_CLOCK 32000 /**< default ILP freq */ +#define BHND_PMU_ALP_CLOCK 20000000 /**< default ALP freq */ +#define BHND_PMU_HT_CLOCK 80000000 /**< default HT freq */ + +/** + * Common per-core clock control/status register available on PMU-equipped + * devices. + */ +#define BHND_CLK_CTL_ST 0x1e0 /**< clock control and status */ + +/* + * BHND_CLK_CTL_ST register + * + * Clock Mode Name Description + * High Throughput (HT) Full bandwidth, low latency. Generally supplied + * from PLL. + * Active Low Power (ALP) Register access, low speed DMA. + * Idle Low Power (ILP) No interconnect activity, or if long latency + * is permitted. + */ +#define BHND_CCS_FORCEALP 0x00000001 /**< force ALP request */ +#define BHND_CCS_FORCEHT 0x00000002 /**< force HT request */ +#define BHND_CCS_FORCEILP 0x00000004 /**< force ILP request */ +#define BHND_CCS_FORCE_MASK 0x0000000F + +#define BHND_CCS_ALPAREQ 0x00000008 /**< ALP Avail Request */ +#define BHND_CCS_HTAREQ 0x00000010 /**< HT Avail Request */ +#define BHND_CCS_AREQ_MASK 0x00000018 + +#define BHND_CCS_FORCEHWREQOFF 0x00000020 /**< Force HW Clock Request Off */ + +#define BHND_CCS_ERSRC_REQ_MASK 0x00000700 /**< external resource requests */ +#define BHND_CCS_ERSRC_REQ_SHIFT 8 +#define BHND_CCS_ERSRC_MAX 2 /**< maximum ERSRC value (corresponding to bits 0-2) */ + +#define BHND_CCS_ALPAVAIL 0x00010000 /**< ALP is available */ +#define BHND_CCS_HTAVAIL 0x00020000 /**< HT is available */ +#define BHND_CCS_AVAIL_MASK 0x00030000 + +#define BHND_CCS_BP_ON_APL 0x00040000 /**< RO: Backplane is running on ALP clock */ +#define BHND_CCS_BP_ON_HT 0x00080000 /**< RO: Backplane is running on HT clock */ +#define BHND_CCS_ERSRC_STS_MASK 0x07000000 /**< external resource status */ +#define BHND_CCS_ERSRC_STS_SHIFT 24 + +#define BHND_CCS0_HTAVAIL 0x00010000 /**< HT avail in chipc and pcmcia on 4328a0 */ +#define BHND_CCS0_ALPAVAIL 0x00020000 /**< ALP avail in chipc and pcmcia on 4328a0 */ + +/* PMU registers */ +#define BHND_PMU_CTRL 0x600 +#define BHND_PMU_CTRL_ILP_DIV_MASK 0xffff0000 +#define BHND_PMU_CTRL_ILP_DIV_SHIFT 16 +#define BHND_PMU_CTRL_PLL_PLLCTL_UPD 0x00000400 /* rev 2 */ +#define BHND_PMU_CTRL_NOILP_ON_WAIT 0x00000200 /* rev 1 */ +#define BHND_PMU_CTRL_HT_REQ_EN 0x00000100 +#define BHND_PMU_CTRL_ALP_REQ_EN 0x00000080 +#define BHND_PMU_CTRL_XTALFREQ_MASK 0x0000007c +#define BHND_PMU_CTRL_XTALFREQ_SHIFT 2 +#define BHND_PMU_CTRL_ILP_DIV_EN 0x00000002 +#define BHND_PMU_CTRL_LPO_SEL 0x00000001 +#define BHND_PMU_CAP 0x604 +#define BHND_PMU_CAP_REV_MASK 0x000000ff +#define BHND_PMU_CAP_REV_SHIFT 0 +#define BHND_PMU_CAP_RC_MASK 0x00001f00 +#define BHND_PMU_CAP_RC_SHIFT 8 +#define BHND_PMU_CAP_RC_MAX \ + (BHND_PMU_CAP_RC_MASK >> BHND_PMU_CAP_RC_SHIFT) +#define BHND_PMU_CAP_TC_MASK 0x0001e000 +#define BHND_PMU_CAP_TC_SHIFT 13 +#define BHND_PMU_CAP_PC_MASK 0x001e0000 +#define BHND_PMU_CAP_PC_SHIFT 17 +#define BHND_PMU_CAP_VC_MASK 0x01e00000 +#define BHND_PMU_CAP_VC_SHIFT 21 +#define BHND_PMU_CAP_CC_MASK 0x1e000000 +#define BHND_PMU_CAP_CC_SHIFT 25 +#define BHND_PMU_CAP5_PC_MASK 0x003e0000 /* PMU corerev >= 5 */ +#define BHND_PMU_CAP5_PC_SHIFT 17 +#define BHND_PMU_CAP5_VC_MASK 0x07c00000 +#define BHND_PMU_CAP5_VC_SHIFT 22 +#define BHND_PMU_CAP5_CC_MASK 0xf8000000 +#define BHND_PMU_CAP5_CC_SHIFT 27 +#define BHND_PMU_ST 0x608 +#define BHND_PMU_ST_EXTLPOAVAIL 0x0100 +#define BHND_PMU_ST_WDRESET 0x0080 +#define BHND_PMU_ST_INTPEND 0x0040 +#define BHND_PMU_ST_SBCLKST 0x0030 +#define BHND_PMU_ST_SBCLKST_ILP 0x0010 +#define BHND_PMU_ST_SBCLKST_ALP 0x0020 +#define BHND_PMU_ST_SBCLKST_HT 0x0030 +#define BHND_PMU_ST_ALPAVAIL 0x0008 +#define BHND_PMU_ST_HTAVAIL 0x0004 +#define BHND_PMU_ST_RESINIT 0x0003 +#define BHND_PMU_RES_STATE 0x60c +#define BHND_PMU_RES_PENDING 0x610 +#define BHND_PMU_TIMER 0x614 +#define BHND_PMU_MIN_RES_MASK 0x618 +#define BHND_PMU_MAX_RES_MASK 0x61c +#define BHND_PMU_RES_TABLE_SEL 0x620 +#define BHND_PMU_RES_DEP_MASK 0x624 +#define BHND_PMU_RES_UPDN_TIMER 0x628 +#define BHND_PMU_RES_UPDN_UPTME_MASK 0xFF +#define BHND_PMU_RES_UPDN_UPTME_SHIFT 8 +#define BHND_PMU_RES_TIMER 0x62C +#define BHND_PMU_CLKSTRETCH 0x630 +#define BHND_PMU_CSTRETCH_HT 0xffff0000 +#define BHND_PMU_CSTRETCH_ALP 0x0000ffff +#define BHND_PMU_WATCHDOG 0x634 +#define BHND_PMU_GPIOSEL 0x638 /* pmu rev >= 1 ? */ +#define BHND_PMU_GPIOEN 0x63C /* pmu rev >= 1 ? */ +#define BHND_PMU_RES_REQ_TIMER_SEL 0x640 +#define BHND_PMU_RES_REQ_TIMER 0x644 +#define BHND_PMU_RRQT_TIME_MASK 0x03ff +#define BHND_PMU_RRQT_INTEN 0x0400 +#define BHND_PMU_RRQT_REQ_ACTIVE 0x0800 +#define BHND_PMU_RRQT_ALP_REQ 0x1000 +#define BHND_PMU_RRQT_HT_REQ 0x2000 +#define BHND_PMU_RES_REQ_MASK 0x648 +#define BHND_PMU_CHIPCTL_ADDR 0x650 +#define BHND_PMU_CHIPCTL_DATA 0x654 +#define BHND_PMU_REG_CONTROL_ADDR 0x658 +#define BHND_PMU_REG_CONTROL_DATA 0x65C +#define BHND_PMU_PLL_CONTROL_ADDR 0x660 +#define BHND_PMU_PLL_CONTROL_DATA 0x664 +#define BHND_PMU_STRAPOPT 0x668 /* chipc rev >= 28 */ +#define BHND_PMU_XTALFREQ 0x66C /* pmu rev >= 10 */ + +/* PMU resource bit position */ +#define BHND_PMURES_BIT(bit) (1 << (bit)) + +/* PMU resource number limit */ +#define BHND_PMU_RESNUM_MAX 30 + +/* PMU chip control0 register */ +#define BHND_PMU_CHIPCTL0 0 + +/* PMU chip control1 register */ +#define BHND_PMU_CHIPCTL1 1 +#define BHND_PMU_CC1_RXC_DLL_BYPASS 0x00010000 + +#define BHND_PMU_CC1_IF_TYPE_MASK 0x00000030 +#define BHND_PMU_CC1_IF_TYPE_RMII 0x00000000 +#define BHND_PMU_CC1_IF_TYPE_MII 0x00000010 +#define BHND_PMU_CC1_IF_TYPE_RGMII 0x00000020 + +#define BHND_PMU_CC1_SW_TYPE_MASK 0x000000c0 +#define BHND_PMU_CC1_SW_TYPE_EPHY 0x00000000 +#define BHND_PMU_CC1_SW_TYPE_EPHYMII 0x00000040 +#define BHND_PMU_CC1_SW_TYPE_EPHYRMII 0x00000080 +#define BHND_PMU_CC1_SW_TYPE_RGMII 0x000000c0 + +/* PMU corerev and chip specific PLL controls. + * PMU_PLL_XX where is PMU corerev and is an arbitrary number + * to differentiate different PLLs controlled by the same PMU rev. + */ + +/* pllcontrol registers */ +/* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */ +#define BHND_PMU0_PLL0_PLLCTL0 0 +#define BHND_PMU0_PLL0_PC0_PDIV_MASK 1 +#define BHND_PMU0_PLL0_PC0_PDIV_FREQ 25000 +#define BHND_PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038 +#define BHND_PMU0_PLL0_PC0_DIV_ARM_SHIFT 3 +#define BHND_PMU0_PLL0_PC0_DIV_ARM_BASE 8 + +/* PC0_DIV_ARM for PLLOUT_ARM */ +#define BHND_PMU0_PLL0_PC0_DIV_ARM_110MHZ 0 +#define BHND_PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1 +#define BHND_PMU0_PLL0_PC0_DIV_ARM_88MHZ 2 +#define BHND_PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */ +#define BHND_PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4 +#define BHND_PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5 +#define BHND_PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6 +#define BHND_PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7 + +/* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */ +#define BHND_PMU0_PLL0_PLLCTL1 1 +#define BHND_PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000 +#define BHND_PMU0_PLL0_PC1_WILD_INT_SHIFT 28 +#define BHND_PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00 +#define BHND_PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8 +#define BHND_PMU0_PLL0_PC1_STOP_MOD 0x00000040 + +/* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */ +#define BHND_PMU0_PLL0_PLLCTL2 2 +#define BHND_PMU0_PLL0_PC2_WILD_INT_MASK 0xf +#define BHND_PMU0_PLL0_PC2_WILD_INT_SHIFT 4 + +/* pllcontrol registers */ +/* ndiv_pwrdn, pwrdn_ch, refcomp_pwrdn, dly_ch, p1div, p2div, _bypass_sdmod */ +#define BHND_PMU1_PLL0_PLLCTL0 0 +#define BHND_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 +#define BHND_PMU1_PLL0_PC0_P1DIV_SHIFT 20 +#define BHND_PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000 +#define BHND_PMU1_PLL0_PC0_P2DIV_SHIFT 24 +#define BHND_PMU1_PLL0_PC0_BYPASS_SDMOD_MASK 0x10000000 +#define BHND_PMU1_PLL0_PC0_BYPASS_SDMOD_SHIFT 28 + +/* mdiv */ +#define BHND_PMU1_PLL0_PLLCTL1 1 +#define BHND_PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff +#define BHND_PMU1_PLL0_PC1_M1DIV_SHIFT 0 +#define BHND_PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00 +#define BHND_PMU1_PLL0_PC1_M2DIV_SHIFT 8 +#define BHND_PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000 +#define BHND_PMU1_PLL0_PC1_M3DIV_SHIFT 16 +#define BHND_PMU1_PLL0_PC1_M4DIV_MASK 0xff000000 +#define BHND_PMU1_PLL0_PC1_M4DIV_SHIFT 24 + +#define BHND_PMU_DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8 +#define BHND_PMU_DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << BHND_PMU_DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) +#define BHND_PMU_DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << BHND_PMU_DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) + +/* mdiv, ndiv_dither_mfb, ndiv_mode, ndiv_int */ +#define BHND_PMU1_PLL0_PLLCTL2 2 +#define BHND_PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff +#define BHND_PMU1_PLL0_PC2_M5DIV_SHIFT 0 +#define BHND_PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00 +#define BHND_PMU1_PLL0_PC2_M6DIV_SHIFT 8 +#define BHND_PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000 +#define BHND_PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17 +#define BHND_PMU1_PLL0_PC2_NDIV_MODE_INT 0 +#define BHND_PMU1_PLL0_PC2_NDIV_MODE_MASH 1 +#define BHND_PMU1_PLL0_PC2_NDIV_MODE_MFB 2 /* recommended for 4319 */ +#define BHND_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 +#define BHND_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 + +/* ndiv_frac */ +#define BHND_PMU1_PLL0_PLLCTL3 3 +#define BHND_PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff +#define BHND_PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0 + +/* pll_ctrl */ +#define BHND_PMU1_PLL0_PLLCTL4 4 +#define BHND_PMU1_PLL0_PC4_KVCO_XS_MASK 0x38000000 +#define BHND_PMU1_PLL0_PC4_KVCO_XS_SHIFT 27 + +/* pll_ctrl, vco_rng, clkdrive_ch */ +#define BHND_PMU1_PLL0_PLLCTL5 5 +#define BHND_PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00 +#define BHND_PMU1_PLL0_PC5_CLK_DRV_SHIFT 8 +#define BHND_PMU1_PLL0_PC5_PLL_CTRL_37_32_MASK 0x0000003f +#define BHND_PMU1_PLL0_PC5_PLL_CTRL_37_32_SHIFT 0 +#define BHND_PMU1_PLL0_PC5_VCO_RNG_MASK 0x000000C0 +#define BHND_PMU1_PLL0_PC5_VCO_RNG_SHIFT 6 + +/* PMU rev 2 control words */ +#define BHND_PMU2_PHY_PLL_PLLCTL 4 +#define BHND_PMU2_SI_PLL_PLLCTL 10 + +/* PMU rev 2 */ +/* pllcontrol registers */ +/* ndiv_pwrdn, pwrdn_ch, refcomp_pwrdn, dly_ch, p1div, p2div, _bypass_sdmod */ +#define BHND_PMU2_PLL_PLLCTL0 0 +#define BHND_PMU2_PLL_PC0_P1DIV_MASK 0x00f00000 +#define BHND_PMU2_PLL_PC0_P1DIV_SHIFT 20 +#define BHND_PMU2_PLL_PC0_P2DIV_MASK 0x0f000000 +#define BHND_PMU2_PLL_PC0_P2DIV_SHIFT 24 + +/* mdiv */ +#define BHND_PMU2_PLL_PLLCTL1 1 +#define BHND_PMU2_PLL_PC1_M1DIV_MASK 0x000000ff +#define BHND_PMU2_PLL_PC1_M1DIV_SHIFT 0 +#define BHND_PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00 +#define BHND_PMU2_PLL_PC1_M2DIV_SHIFT 8 +#define BHND_PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000 +#define BHND_PMU2_PLL_PC1_M3DIV_SHIFT 16 +#define BHND_PMU2_PLL_PC1_M4DIV_MASK 0xff000000 +#define BHND_PMU2_PLL_PC1_M4DIV_SHIFT 24 + +/* mdiv, ndiv_dither_mfb, ndiv_mode, ndiv_int */ +#define BHND_PMU2_PLL_PLLCTL2 2 +#define BHND_PMU2_PLL_PC2_M5DIV_MASK 0x000000ff +#define BHND_PMU2_PLL_PC2_M5DIV_SHIFT 0 +#define BHND_PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00 +#define BHND_PMU2_PLL_PC2_M6DIV_SHIFT 8 +#define BHND_PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000 +#define BHND_PMU2_PLL_PC2_NDIV_MODE_SHIFT 17 +#define BHND_PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000 +#define BHND_PMU2_PLL_PC2_NDIV_INT_SHIFT 20 + +/* ndiv_frac */ +#define BHND_PMU2_PLL_PLLCTL3 3 +#define BHND_PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff +#define BHND_PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0 + +/* pll_ctrl */ +#define BHND_PMU2_PLL_PLLCTL4 4 + +/* pll_ctrl, vco_rng, clkdrive_ch */ +#define BHND_PMU2_PLL_PLLCTL5 5 +#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00 +#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8 +#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000 +#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12 +#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000 +#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16 +#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000 +#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20 +#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000 +#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24 +#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000 +#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28 + +/* PMU rev 5 (& 6) */ +#define BHND_PMU5_PLL_P1P2_OFF 0 +#define BHND_PMU5_PLL_P1_MASK 0x0f000000 +#define BHND_PMU5_PLL_P1_SHIFT 24 +#define BHND_PMU5_PLL_P2_MASK 0x00f00000 +#define BHND_PMU5_PLL_P2_SHIFT 20 +#define BHND_PMU5_PLL_M14_OFF 1 +#define BHND_PMU5_PLL_MDIV_MASK 0x000000ff +#define BHND_PMU5_PLL_MDIV_WIDTH 8 +#define BHND_PMU5_PLL_NM5_OFF 2 +#define BHND_PMU5_PLL_NDIV_MASK 0xfff00000 +#define BHND_PMU5_PLL_NDIV_SHIFT 20 +#define BHND_PMU5_PLL_NDIV_MODE_MASK 0x000e0000 +#define BHND_PMU5_PLL_NDIV_MODE_SHIFT 17 +#define BHND_PMU5_PLL_FMAB_OFF 3 +#define BHND_PMU5_PLL_MRAT_MASK 0xf0000000 +#define BHND_PMU5_PLL_MRAT_SHIFT 28 +#define BHND_PMU5_PLL_ABRAT_MASK 0x08000000 +#define BHND_PMU5_PLL_ABRAT_SHIFT 27 +#define BHND_PMU5_PLL_FDIV_MASK 0x07ffffff +#define BHND_PMU5_PLL_PLLCTL_OFF 4 +#define BHND_PMU5_PLL_PCHI_OFF 5 +#define BHND_PMU5_PLL_PCHI_MASK 0x0000003f + +/* pmu XtalFreqRatio */ +#define BHND_PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF +#define BHND_PMU_XTALFREQ_REG_ILPCTR_SHIFT 0 +#define BHND_PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000 +#define BHND_PMU_XTALFREQ_REG_MEASURE_SHIFT 31 + + +/* Divider allocation in 4716/47162/5356/5357 */ +#define BHND_PMU5_MAINPLL_CPU 1 +#define BHND_PMU5_MAINPLL_MEM 2 +#define BHND_PMU5_MAINPLL_SI 3 + +#define BHND_PMU7_PLL_PLLCTL7 7 +#define BHND_PMU7_PLL_PLLCTL8 8 +#define BHND_PMU7_PLL_PLLCTL11 11 + + +/* PLL usage in 4716/47162 */ +#define BHND_PMU4716_MAINPLL_PLL0 12 + + +/* PLL usage in 5356/5357 */ +#define BHND_PMU5356_MAINPLL_PLL0 0 +#define BHND_PMU5357_MAINPLL_PLL0 0 + + +/* 4716/47162 PMU resources */ +#define BHND_PMU_RES4716_PROC_PLL_ON 0x00000040 +#define BHND_PMU_RES4716_PROC_HT_AVAIL 0x00000080 + +/* 4716/4717/4718 chip-specific CHIPCTRL PMU register bits */ +#define BHND_PMU_CCTRL471X_I2S_PINS_ENABLE 0x0080 /* I2S pins off by default, shared with pflash */ + + +/* 5354 PMU resources */ +#define BHND_PMU_RES5354_EXT_SWITCHER_PWM 0 /* 0x00001 */ +#define BHND_PMU_RES5354_BB_SWITCHER_PWM 1 /* 0x00002 */ +#define BHND_PMU_RES5354_BB_SWITCHER_BURST 2 /* 0x00004 */ +#define BHND_PMU_RES5354_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ +#define BHND_PMU_RES5354_ILP_REQUEST 4 /* 0x00010 */ +#define BHND_PMU_RES5354_RADIO_SWITCHER_PWM 5 /* 0x00020 */ +#define BHND_PMU_RES5354_RADIO_SWITCHER_BURST 6 /* 0x00040 */ +#define BHND_PMU_RES5354_ROM_SWITCH 7 /* 0x00080 */ +#define BHND_PMU_RES5354_PA_REF_LDO 8 /* 0x00100 */ +#define BHND_PMU_RES5354_RADIO_LDO 9 /* 0x00200 */ +#define BHND_PMU_RES5354_AFE_LDO 10 /* 0x00400 */ +#define BHND_PMU_RES5354_PLL_LDO 11 /* 0x00800 */ +#define BHND_PMU_RES5354_BG_FILTBYP 12 /* 0x01000 */ +#define BHND_PMU_RES5354_TX_FILTBYP 13 /* 0x02000 */ +#define BHND_PMU_RES5354_RX_FILTBYP 14 /* 0x04000 */ +#define BHND_PMU_RES5354_XTAL_PU 15 /* 0x08000 */ +#define BHND_PMU_RES5354_XTAL_EN 16 /* 0x10000 */ +#define BHND_PMU_RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */ +#define BHND_PMU_RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */ +#define BHND_PMU_RES5354_BB_PLL_PU 19 /* 0x80000 */ + + +/* 5357 chip-specific CHIPCTRL register bits */ +#define BHND_PMU_CCTRL5357_EXTPA (1<<14) /* extPA in CHIPCTL1, bit 14 */ +#define BHND_PMU_CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in CHIPCTL1, bit 15 */ + + +/* 4328 PMU resources */ +#define BHND_PMU_RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */ +#define BHND_PMU_RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */ +#define BHND_PMU_RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */ +#define BHND_PMU_RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ +#define BHND_PMU_RES4328_ILP_REQUEST 4 /* 0x00010 */ +#define BHND_PMU_RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */ +#define BHND_PMU_RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */ +#define BHND_PMU_RES4328_ROM_SWITCH 7 /* 0x00080 */ +#define BHND_PMU_RES4328_PA_REF_LDO 8 /* 0x00100 */ +#define BHND_PMU_RES4328_RADIO_LDO 9 /* 0x00200 */ +#define BHND_PMU_RES4328_AFE_LDO 10 /* 0x00400 */ +#define BHND_PMU_RES4328_PLL_LDO 11 /* 0x00800 */ +#define BHND_PMU_RES4328_BG_FILTBYP 12 /* 0x01000 */ +#define BHND_PMU_RES4328_TX_FILTBYP 13 /* 0x02000 */ +#define BHND_PMU_RES4328_RX_FILTBYP 14 /* 0x04000 */ +#define BHND_PMU_RES4328_XTAL_PU 15 /* 0x08000 */ +#define BHND_PMU_RES4328_XTAL_EN 16 /* 0x10000 */ +#define BHND_PMU_RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */ +#define BHND_PMU_RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */ +#define BHND_PMU_RES4328_BB_PLL_PU 19 /* 0x80000 */ + + +/* 4325 A0/A1 PMU resources */ +#define BHND_PMU_RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */ +#define BHND_PMU_RES4325_CBUCK_BURST 1 /* 0x00000002 */ +#define BHND_PMU_RES4325_CBUCK_PWM 2 /* 0x00000004 */ +#define BHND_PMU_RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */ +#define BHND_PMU_RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */ +#define BHND_PMU_RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */ +#define BHND_PMU_RES4325_ILP_REQUEST 6 /* 0x00000040 */ +#define BHND_PMU_RES4325_ABUCK_BURST 7 /* 0x00000080 */ +#define BHND_PMU_RES4325_ABUCK_PWM 8 /* 0x00000100 */ +#define BHND_PMU_RES4325_LNLDO1_PU 9 /* 0x00000200 */ +#define BHND_PMU_RES4325_OTP_PU 10 /* 0x00000400 */ +#define BHND_PMU_RES4325_LNLDO3_PU 11 /* 0x00000800 */ +#define BHND_PMU_RES4325_LNLDO4_PU 12 /* 0x00001000 */ +#define BHND_PMU_RES4325_XTAL_PU 13 /* 0x00002000 */ +#define BHND_PMU_RES4325_ALP_AVAIL 14 /* 0x00004000 */ +#define BHND_PMU_RES4325_RX_PWRSW_PU 15 /* 0x00008000 */ +#define BHND_PMU_RES4325_TX_PWRSW_PU 16 /* 0x00010000 */ +#define BHND_PMU_RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */ +#define BHND_PMU_RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */ +#define BHND_PMU_RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */ +#define BHND_PMU_RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */ +#define BHND_PMU_RES4325_HT_AVAIL 21 /* 0x00200000 */ + + +/* 4325 B0/C0 PMU resources */ +#define BHND_PMU_RES4325B0_CBUCK_LPOM 1 /* 0x00000002 */ +#define BHND_PMU_RES4325B0_CBUCK_BURST 2 /* 0x00000004 */ +#define BHND_PMU_RES4325B0_CBUCK_PWM 3 /* 0x00000008 */ +#define BHND_PMU_RES4325B0_CLDO_PU 4 /* 0x00000010 */ + + +/* 4325 C1 PMU resources */ +#define BHND_PMU_RES4325C1_LNLDO2_PU 12 /* 0x00001000 */ + + +/* 4325 PMU resources */ +#define BHND_PMU_RES4329_RESERVED0 0 /* 0x00000001 */ +#define BHND_PMU_RES4329_CBUCK_LPOM 1 /* 0x00000002 */ +#define BHND_PMU_RES4329_CBUCK_BURST 2 /* 0x00000004 */ +#define BHND_PMU_RES4329_CBUCK_PWM 3 /* 0x00000008 */ +#define BHND_PMU_RES4329_CLDO_PU 4 /* 0x00000010 */ +#define BHND_PMU_RES4329_PALDO_PU 5 /* 0x00000020 */ +#define BHND_PMU_RES4329_ILP_REQUEST 6 /* 0x00000040 */ +#define BHND_PMU_RES4329_RESERVED7 7 /* 0x00000080 */ +#define BHND_PMU_RES4329_RESERVED8 8 /* 0x00000100 */ +#define BHND_PMU_RES4329_LNLDO1_PU 9 /* 0x00000200 */ +#define BHND_PMU_RES4329_OTP_PU 10 /* 0x00000400 */ +#define BHND_PMU_RES4329_RESERVED11 11 /* 0x00000800 */ +#define BHND_PMU_RES4329_LNLDO2_PU 12 /* 0x00001000 */ +#define BHND_PMU_RES4329_XTAL_PU 13 /* 0x00002000 */ +#define BHND_PMU_RES4329_ALP_AVAIL 14 /* 0x00004000 */ +#define BHND_PMU_RES4329_RX_PWRSW_PU 15 /* 0x00008000 */ +#define BHND_PMU_RES4329_TX_PWRSW_PU 16 /* 0x00010000 */ +#define BHND_PMU_RES4329_RFPLL_PWRSW_PU 17 /* 0x00020000 */ +#define BHND_PMU_RES4329_LOGEN_PWRSW_PU 18 /* 0x00040000 */ +#define BHND_PMU_RES4329_AFE_PWRSW_PU 19 /* 0x00080000 */ +#define BHND_PMU_RES4329_BBPLL_PWRSW_PU 20 /* 0x00100000 */ +#define BHND_PMU_RES4329_HT_AVAIL 21 /* 0x00200000 */ + + +/* 4312 PMU resources (all PMU chips with little memory constraint) */ +#define BHND_PMU_RES4312_SWITCHER_BURST 0 /* 0x00000001 */ +#define BHND_PMU_RES4312_SWITCHER_PWM 1 /* 0x00000002 */ +#define BHND_PMU_RES4312_PA_REF_LDO 2 /* 0x00000004 */ +#define BHND_PMU_RES4312_CORE_LDO_BURST 3 /* 0x00000008 */ +#define BHND_PMU_RES4312_CORE_LDO_PWM 4 /* 0x00000010 */ +#define BHND_PMU_RES4312_RADIO_LDO 5 /* 0x00000020 */ +#define BHND_PMU_RES4312_ILP_REQUEST 6 /* 0x00000040 */ +#define BHND_PMU_RES4312_BG_FILTBYP 7 /* 0x00000080 */ +#define BHND_PMU_RES4312_TX_FILTBYP 8 /* 0x00000100 */ +#define BHND_PMU_RES4312_RX_FILTBYP 9 /* 0x00000200 */ +#define BHND_PMU_RES4312_XTAL_PU 10 /* 0x00000400 */ +#define BHND_PMU_RES4312_ALP_AVAIL 11 /* 0x00000800 */ +#define BHND_PMU_RES4312_BB_PLL_FILTBYP 12 /* 0x00001000 */ +#define BHND_PMU_RES4312_RF_PLL_FILTBYP 13 /* 0x00002000 */ +#define BHND_PMU_RES4312_HT_AVAIL 14 /* 0x00004000 */ + + +/* 4322 PMU resources */ +#define BHND_PMU_RES4322_RF_LDO 0 +#define BHND_PMU_RES4322_ILP_REQUEST 1 +#define BHND_PMU_RES4322_XTAL_PU 2 +#define BHND_PMU_RES4322_ALP_AVAIL 3 +#define BHND_PMU_RES4322_SI_PLL_ON 4 +#define BHND_PMU_RES4322_HT_SI_AVAIL 5 +#define BHND_PMU_RES4322_PHY_PLL_ON 6 +#define BHND_PMU_RES4322_HT_PHY_AVAIL 7 +#define BHND_PMU_RES4322_OTP_PU 8 + + +/* 43224 chip-specific CHIPCTRL register bits */ +#define BHND_PMU_CCTRL_43224_GPIO_TOGGLE 0x8000 +#define BHND_PMU_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */ +#define BHND_PMU_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */ + + +/* 43236 PMU resources */ +#define BHND_PMU_RES43236_REGULATOR 0 +#define BHND_PMU_RES43236_ILP_REQUEST 1 +#define BHND_PMU_RES43236_XTAL_PU 2 +#define BHND_PMU_RES43236_ALP_AVAIL 3 +#define BHND_PMU_RES43236_SI_PLL_ON 4 +#define BHND_PMU_RES43236_HT_SI_AVAIL 5 + +/* 43236 chip-specific CHIPCTRL register bits */ +#define BHND_PMU_CCTRL43236_BT_COEXIST (1<<0) /* 0 disable */ +#define BHND_PMU_CCTRL43236_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ +#define BHND_PMU_CCTRL43236_EXT_LNA (1<<2) /* 0 disable */ +#define BHND_PMU_CCTRL43236_ANT_MUX_2o3 (1<<3) /* 2o3 mux, chipcontrol bit 3 */ +#define BHND_PMU_CCTRL43236_GSIO (1<<4) /* 0 disable */ + + +/* 4331 PMU resources */ +#define BHND_PMU_RES4331_REGULATOR 0 +#define BHND_PMU_RES4331_ILP_REQUEST 1 +#define BHND_PMU_RES4331_XTAL_PU 2 +#define BHND_PMU_RES4331_ALP_AVAIL 3 +#define BHND_PMU_RES4331_SI_PLL_ON 4 +#define BHND_PMU_RES4331_HT_SI_AVAIL 5 + +/* 4315 PMU resources */ +#define BHND_PMU_RES4315_CBUCK_LPOM 1 /* 0x00000002 */ +#define BHND_PMU_RES4315_CBUCK_BURST 2 /* 0x00000004 */ +#define BHND_PMU_RES4315_CBUCK_PWM 3 /* 0x00000008 */ +#define BHND_PMU_RES4315_CLDO_PU 4 /* 0x00000010 */ +#define BHND_PMU_RES4315_PALDO_PU 5 /* 0x00000020 */ +#define BHND_PMU_RES4315_ILP_REQUEST 6 /* 0x00000040 */ +#define BHND_PMU_RES4315_LNLDO1_PU 9 /* 0x00000200 */ +#define BHND_PMU_RES4315_OTP_PU 10 /* 0x00000400 */ +#define BHND_PMU_RES4315_LNLDO2_PU 12 /* 0x00001000 */ +#define BHND_PMU_RES4315_XTAL_PU 13 /* 0x00002000 */ +#define BHND_PMU_RES4315_ALP_AVAIL 14 /* 0x00004000 */ +#define BHND_PMU_RES4315_RX_PWRSW_PU 15 /* 0x00008000 */ +#define BHND_PMU_RES4315_TX_PWRSW_PU 16 /* 0x00010000 */ +#define BHND_PMU_RES4315_RFPLL_PWRSW_PU 17 /* 0x00020000 */ +#define BHND_PMU_RES4315_LOGEN_PWRSW_PU 18 /* 0x00040000 */ +#define BHND_PMU_RES4315_AFE_PWRSW_PU 19 /* 0x00080000 */ +#define BHND_PMU_RES4315_BBPLL_PWRSW_PU 20 /* 0x00100000 */ +#define BHND_PMU_RES4315_HT_AVAIL 21 /* 0x00200000 */ + +/* 4319 PMU resources */ +#define BHND_PMU_RES4319_CBUCK_LPOM 1 /* 0x00000002 */ +#define BHND_PMU_RES4319_CBUCK_BURST 2 /* 0x00000004 */ +#define BHND_PMU_RES4319_CBUCK_PWM 3 /* 0x00000008 */ +#define BHND_PMU_RES4319_CLDO_PU 4 /* 0x00000010 */ +#define BHND_PMU_RES4319_PALDO_PU 5 /* 0x00000020 */ +#define BHND_PMU_RES4319_ILP_REQUEST 6 /* 0x00000040 */ +#define BHND_PMU_RES4319_LNLDO1_PU 9 /* 0x00000200 */ +#define BHND_PMU_RES4319_OTP_PU 10 /* 0x00000400 */ +#define BHND_PMU_RES4319_LNLDO2_PU 12 /* 0x00001000 */ +#define BHND_PMU_RES4319_XTAL_PU 13 /* 0x00002000 */ +#define BHND_PMU_RES4319_ALP_AVAIL 14 /* 0x00004000 */ +#define BHND_PMU_RES4319_RX_PWRSW_PU 15 /* 0x00008000 */ +#define BHND_PMU_RES4319_TX_PWRSW_PU 16 /* 0x00010000 */ +#define BHND_PMU_RES4319_RFPLL_PWRSW_PU 17 /* 0x00020000 */ +#define BHND_PMU_RES4319_LOGEN_PWRSW_PU 18 /* 0x00040000 */ +#define BHND_PMU_RES4319_AFE_PWRSW_PU 19 /* 0x00080000 */ +#define BHND_PMU_RES4319_BBPLL_PWRSW_PU 20 /* 0x00100000 */ +#define BHND_PMU_RES4319_HT_AVAIL 21 /* 0x00200000 */ + +/* 4319 chip-specific CHIPCTL register bits */ +#define BHND_PMU1_PLL0_CHIPCTL0 0 +#define BHND_PMU1_PLL0_CHIPCTL1 1 +#define BHND_PMU1_PLL0_CHIPCTL2 2 +#define BHND_PMU_CCTL_4319USB_XTAL_SEL_MASK 0x00180000 +#define BHND_PMU_CCTL_4319USB_XTAL_SEL_SHIFT 19 +#define BHND_PMU_CCTL_4319USB_48MHZ_PLL_SEL 1 +#define BHND_PMU_CCTL_4319USB_24MHZ_PLL_SEL 2 + +/* 4336 PMU resources */ +#define BHND_PMU_RES4336_CBUCK_LPOM 0 +#define BHND_PMU_RES4336_CBUCK_BURST 1 +#define BHND_PMU_RES4336_CBUCK_LP_PWM 2 +#define BHND_PMU_RES4336_CBUCK_PWM 3 +#define BHND_PMU_RES4336_CLDO_PU 4 +#define BHND_PMU_RES4336_DIS_INT_RESET_PD 5 +#define BHND_PMU_RES4336_ILP_REQUEST 6 +#define BHND_PMU_RES4336_LNLDO_PU 7 +#define BHND_PMU_RES4336_LDO3P3_PU 8 +#define BHND_PMU_RES4336_OTP_PU 9 +#define BHND_PMU_RES4336_XTAL_PU 10 +#define BHND_PMU_RES4336_ALP_AVAIL 11 +#define BHND_PMU_RES4336_RADIO_PU 12 +#define BHND_PMU_RES4336_BG_PU 13 +#define BHND_PMU_RES4336_VREG1p4_PU_PU 14 +#define BHND_PMU_RES4336_AFE_PWRSW_PU 15 +#define BHND_PMU_RES4336_RX_PWRSW_PU 16 +#define BHND_PMU_RES4336_TX_PWRSW_PU 17 +#define BHND_PMU_RES4336_BB_PWRSW_PU 18 +#define BHND_PMU_RES4336_SYNTH_PWRSW_PU 19 +#define BHND_PMU_RES4336_MISC_PWRSW_PU 20 +#define BHND_PMU_RES4336_LOGEN_PWRSW_PU 21 +#define BHND_PMU_RES4336_BBPLL_PWRSW_PU 22 +#define BHND_PMU_RES4336_MACPHY_CLKAVAIL 23 +#define BHND_PMU_RES4336_HT_AVAIL 24 +#define BHND_PMU_RES4336_RSVD 25 + +/* 4330 resources */ +#define BHND_PMU_RES4330_CBUCK_LPOM 0 +#define BHND_PMU_RES4330_CBUCK_BURST 1 +#define BHND_PMU_RES4330_CBUCK_LP_PWM 2 +#define BHND_PMU_RES4330_CBUCK_PWM 3 +#define BHND_PMU_RES4330_CLDO_PU 4 +#define BHND_PMU_RES4330_DIS_INT_RESET_PD 5 +#define BHND_PMU_RES4330_ILP_REQUEST 6 +#define BHND_PMU_RES4330_LNLDO_PU 7 +#define BHND_PMU_RES4330_LDO3P3_PU 8 +#define BHND_PMU_RES4330_OTP_PU 9 +#define BHND_PMU_RES4330_XTAL_PU 10 +#define BHND_PMU_RES4330_ALP_AVAIL 11 +#define BHND_PMU_RES4330_RADIO_PU 12 +#define BHND_PMU_RES4330_BG_PU 13 +#define BHND_PMU_RES4330_VREG1p4_PU_PU 14 +#define BHND_PMU_RES4330_AFE_PWRSW_PU 15 +#define BHND_PMU_RES4330_RX_PWRSW_PU 16 +#define BHND_PMU_RES4330_TX_PWRSW_PU 17 +#define BHND_PMU_RES4330_BB_PWRSW_PU 18 +#define BHND_PMU_RES4330_SYNTH_PWRSW_PU 19 +#define BHND_PMU_RES4330_MISC_PWRSW_PU 20 +#define BHND_PMU_RES4330_LOGEN_PWRSW_PU 21 +#define BHND_PMU_RES4330_BBPLL_PWRSW_PU 22 +#define BHND_PMU_RES4330_MACPHY_CLKAVAIL 23 +#define BHND_PMU_RES4330_HT_AVAIL 24 +#define BHND_PMU_RES4330_5gRX_PWRSW_PU 25 +#define BHND_PMU_RES4330_5gTX_PWRSW_PU 26 +#define BHND_PMU_RES4330_5g_LOGEN_PWRSW_PU 27 + +/* 4313 resources */ +#define BHND_PMU_RES4313_BB_PU_RSRC 0 +#define BHND_PMU_RES4313_ILP_REQ_RSRC 1 +#define BHND_PMU_RES4313_XTAL_PU_RSRC 2 +#define BHND_PMU_RES4313_ALP_AVAIL_RSRC 3 +#define BHND_PMU_RES4313_RADIO_PU_RSRC 4 +#define BHND_PMU_RES4313_BG_PU_RSRC 5 +#define BHND_PMU_RES4313_VREG1P4_PU_RSRC 6 +#define BHND_PMU_RES4313_AFE_PWRSW_RSRC 7 +#define BHND_PMU_RES4313_RX_PWRSW_RSRC 8 +#define BHND_PMU_RES4313_TX_PWRSW_RSRC 9 +#define BHND_PMU_RES4313_BB_PWRSW_RSRC 10 +#define BHND_PMU_RES4313_SYNTH_PWRSW_RSRC 11 +#define BHND_PMU_RES4313_MISC_PWRSW_RSRC 12 +#define BHND_PMU_RES4313_BB_PLL_PWRSW_RSRC 13 +#define BHND_PMU_RES4313_HT_AVAIL_RSRC 14 +#define BHND_PMU_RES4313_MACPHY_CLK_AVAIL_RSRC 15 + +/* 4313 chip-specific CHIPCTRL register bits */ +#define BHND_PMU_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ + +/* 43228 resources */ +#define BHND_PMU_RES43228_NOT_USED 0 +#define BHND_PMU_RES43228_ILP_REQUEST 1 +#define BHND_PMU_RES43228_XTAL_PU 2 +#define BHND_PMU_RES43228_ALP_AVAIL 3 +#define BHND_PMU_RES43228_PLL_EN 4 +#define BHND_PMU_RES43228_HT_PHY_AVAIL 5 + +/* +* Maximum delay for the PMU state transition in us. +* This is an upper bound intended for spinwaits etc. +*/ +#define BHND_PMU_MAX_TRANSITION_DLY 15000 + +/* PMU resource up transition time in ILP cycles */ +#define BHND_PMURES_UP_TRANSITION 2 + +#endif /* _BHND_CORES_PMU_BHND_PMUREG_H_ */ Property changes on: head/sys/dev/bhnd/cores/pmu/bhnd_pmureg.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/bhnd/cores/pmu/bhnd_pmuvar.h =================================================================== --- head/sys/dev/bhnd/cores/pmu/bhnd_pmuvar.h (nonexistent) +++ head/sys/dev/bhnd/cores/pmu/bhnd_pmuvar.h (revision 304870) @@ -0,0 +1,92 @@ +/*- + * Copyright (c) 2015 Landon Fuller + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ + +#ifndef _BHND_CORES_PMU_BHND_PMUVAR_H_ +#define _BHND_CORES_PMU_BHND_PMUVAR_H_ + +#include +#include + +#include "bhnd_pmu.h" + +DECLARE_CLASS(bhnd_pmu_driver); +extern devclass_t bhnd_pmu_devclass; + +int bhnd_pmu_probe(device_t dev); + +int bhnd_pmu_attach(device_t dev, struct bhnd_resource *res); +int bhnd_pmu_detach(device_t dev); +int bhnd_pmu_suspend(device_t dev); +int bhnd_pmu_resume(device_t dev); + +/* + * BHND PMU device quirks / features + */ +enum { + /** No quirks */ + BPMU_QUIRK_NONE = 0, + + /** On BCM4328-derived chipsets, the CLK_CTL_ST register CCS_HTAVAIL + * and CCS_ALPAVAIL bits are swapped; the BHND_CCS0_* constants should + * be used. */ + BPMU_QUIRK_CLKCTL_CCS0 = 1 +}; + +/** + * bhnd_pmu driver instance state. + */ +struct bhnd_pmu_softc { + device_t dev; + uint32_t quirks; /**< device quirk flags */ + uint32_t caps; /**< pmu capability flags. */ + + struct bhnd_chipid cid; /**< chip identification */ + struct bhnd_board_info board; /**< board identification */ + device_t chipc_dev; /**< chipcommon device */ + + struct bhnd_resource *res; /**< pmu register block. */ + int rid; /**< pmu register RID */ + + struct mtx mtx; /**< state mutex */ + + uint32_t ilp_cps; /**< measured ILP cycles per + second, or 0 */ +}; + +#define BPMU_LOCK_INIT(sc) \ + mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \ + "BHND chipc driver lock", MTX_DEF) +#define BPMU_LOCK(sc) mtx_lock(&(sc)->mtx) +#define BPMU_UNLOCK(sc) mtx_unlock(&(sc)->mtx) +#define BPMU_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what) +#define BPMU_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) + +#endif /* _BHND_CORES_PMU_BHND_PMUVAR_H_ */ Property changes on: head/sys/dev/bhnd/cores/pmu/bhnd_pmuvar.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/bhnd/nvram/nvram_map =================================================================== --- head/sys/dev/bhnd/nvram/nvram_map (revision 304869) +++ head/sys/dev/bhnd/nvram/nvram_map (revision 304870) @@ -1,1450 +1,1465 @@ #- # Copyright (c) 2015-2016 Landon Fuller # Copyright (C) 2008-2015, Broadcom Corporation. # All Rights Reserved. # # The contents of this file (variable names, descriptions, and offsets) were # extracted or derived from Broadcom's ISC-licensed sources. # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY # SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION # OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN # CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. # # $FreeBSD$ # # NVRAM variable definitions and revision-specific SPROM offsets. # # Processed by nvram_map_gen.awk to produce bhnd_nvram_map.h # # NOTE: file was originally generated automatically by using libclang # to analyze and extract format information and descriptions from Broadcom's # available ISC-licensed CIS and SROM code and associated headers. # # Board Info # u16 boardvendor {} # PCI vendor ID (SoC NVRAM-only) u16 subvid { srom >= 2 0x6 } # PCI subvendor ID u16 devid { srom >= 8 0x60 } # PCI device ID u32 boardflags { srom 1 u16 0x72 srom 2 u16 0x72 | u16 0x38 (<<16) srom 3 u16 0x72 | u16 0x7A (<<16) srom 4 0x44 srom 5-7 0x4A srom >= 8 0x84 } u32 boardflags2 { srom 4 0x48 srom 5-7 0x4E srom >= 8 0x88 } u32 boardflags3 { srom >= 11 0x8C } # Board serial number, independent of mac addr u16 boardnum { srom 1-2 0x4C srom 3 0x4E srom 4 0x50 srom 5-7 0x56 srom 8-10 0x90 srom >= 11 0x94 } # Board revision u16 boardrev { srom 1-3 u8 0x5D srom 4-7 0x42 srom >= 8 0x82 } # Board type u16 boardtype { srom >= 2 0x4 } # SROM revision u8 sromrev { srom 1-3 0x74 srom 4-9 0x1B6 srom 10 0x1CA srom 11 0x1D2 } + +# PMU Info +# + +# PMU min resource mask (embedded-only). +u32 rmin { + sfmt decimal +} + +# PMU min resource max (embedded-only). +u32 rmax { + sfmt decimal +} + + # Antennas available u8 aa2g { srom 1-3 0x5C (&0x30, >>4) srom 4-7 0x5D srom 8-10 0x9D srom >= 11 0xA1 } u8 aa5g { srom 1-3 0x5C (&0xC0, >>6) srom 4-7 0x5C srom 8-10 0x9C srom >= 11 0xA0 } # ACPHY PA trimming parameters: 40 u16[12] pa5gbw40a0 { srom >= 11 0x110 } # ACPHY PA trimming parameters: 80 u16[12] pa5gbw80a0 { srom >= 11 0x138 } # ACPHY PA trimming parameters: 40/80 u16[12] pa5gbw4080a0 { srom >= 11 0x138 } u16[12] pa5gbw4080a1 { srom >= 11 u16 0xB6, u16 0xBC, u16 0xCE, u16 0xD4, u16[8] 0x128 } # ACPHY PA trimming parameters: CCK u16[3] pa2gccka0 { srom >= 11 0x102 } # ACPHY Power-per-rate 2gpo u16 dot11agofdmhrbw202gpo { srom >= 11 0x15C } u16 ofdmlrbw202gpo { srom >= 11 0x15E } # ACPHY Power-per-rate 5gpo u32 mcsbw805glpo { srom >= 11 0x168 } u32 mcsbw805gmpo { srom >= 11 0x178 } u32 mcsbw805ghpo { srom >= 11 0x188 } u16 mcslr5glpo { srom >= 11 0x190 (&0xFFF) } u16 mcslr5gmpo { srom >= 11 0x192 } u16 mcslr5ghpo { srom >= 11 0x194 } # ACPHY Power-per-rate sbpo u16 sb20in40hrpo { srom >= 11 0x196 } u16 sb20in80and160hr5glpo { srom >= 11 0x198 } u16 sb40and80hr5glpo { srom >= 11 0x19A } u16 sb20in80and160hr5gmpo { srom >= 11 0x19C } u16 sb40and80hr5gmpo { srom >= 11 0x19E } u16 sb20in80and160hr5ghpo { srom >= 11 0x1A0 } u16 sb40and80hr5ghpo { srom >= 11 0x1A2 } u16 sb20in40lrpo { srom >= 11 0x1A4 } u16 sb20in80and160lr5glpo { srom >= 11 0x1A6 } u16 sb40and80lr5glpo { srom >= 11 0x1A8 } u16 sb20in80and160lr5gmpo { srom >= 11 0x1AA } u16 sb40and80lr5gmpo { srom >= 11 0x1AC } u16 sb20in80and160lr5ghpo { srom >= 11 0x1AE } u16 sb40and80lr5ghpo { srom >= 11 0x1B0 } u16 dot11agduphrpo { srom >= 11 0x1B2 } u16 dot11agduplrpo { srom >= 11 0x1B4 } # Antenna gain u8 ag0 { srom 1-3 0x75 srom 4-7 0x5F srom 8-10 0x9F } u8 ag1 { srom 1-3 0x74 srom 4-7 0x5E srom 8-10 0x9E } u8 ag2 { srom 4-7 0x61 srom 8-10 0xA1 } u8 ag3 { srom 4-7 0x60 srom 8-10 0xA0 } u8 agbg0 { srom >= 11 0xA2 } u8 agbg1 { srom >= 11 0xA3 } u8 agbg2 { srom >= 11 0xA4 } u8 aga0 { srom >= 11 0xA5 } u8 aga1 { srom >= 11 0xA6 } u8 aga2 { srom >= 11 0xA7 } # Default country code (sromrev == 1) u8 cc { srom 1 0x5C (&0xF) } # 2 bytes each # CCK Power offsets for 20 MHz rates (11, 5.5, 2, 1Mbps) # cckbw202gpo cckbw20ul2gpo # u16 cckbw202gpo { srom 9-10 0x140 srom >= 11 0x150 } u16 cckbw20ul2gpo { srom 9-10 0x142 srom >= 11 0x152 } # Country code (2 bytes ascii + 1 byte cctl) # in rev 2 # char[2] ccode { sfmt ccode srom 0-3 0x76 srom 4 0x52 srom 5-7 0x44 srom 8-10 0x92 srom >= 11 0x96 } # 2 byte; txchain, rxchain u8 txchain { all1 ignore srom 4-7 0x7B (&0xF) srom 8-10 0xA3 (&0xF) srom >= 11 0xA9 (&0xF) } u8 rxchain { all1 ignore srom 4-7 0x7B (&0xF0, >>4) srom 8-10 0xA3 (&0xF0, >>4) srom >= 11 0xA9 (&0xF0, >>4) } u16 antswitch { all1 ignore srom 4-7 u8 0x7A srom 8-10 u8 0xA2 srom >= 11 u8 0xA8 } u8 elna2g { srom 8-10 0xBB } u8 elna5g { srom 8-10 0xBA } # 11n front-end specification u8 antswctl2g { srom 8-10 0xAE (&0xF8, >>3) } u8 triso2g { srom 8-10 0xAE (&0x7) } u8 pdetrange2g { srom 8-10 0xAF (&0xF8, >>3) } u8 extpagain2g { srom 8-10 0xAF (&0x6, >>1) } u8 tssipos2g { srom 8-10 0xAF (&0x1) } u8 antswctl5g { srom 8-10 0xB0 (&0xF8, >>3) } u8 triso5g { srom 8-10 0xB0 (&0x7) } u8 pdetrange5g { srom 8-10 0xB1 (&0xF8, >>3) } u8 extpagain5g { srom 8-10 0xB1 (&0x6, >>1) } u8 tssipos5g { srom 8-10 0xB1 (&0x1) } # FEM config u8 femctrl { sfmt decimal srom >= 11 0xAA (&0xF8, >>3) } u8 papdcap2g { sfmt decimal srom >= 11 0xAA (&0x4, >>2) } u8 tworangetssi2g { sfmt decimal srom >= 11 0xAA (&0x2, >>1) } u8 pdgain2g { sfmt decimal srom >= 11 u16 0xAA (&0x1F0, >>4) } u8 epagain2g { sfmt decimal srom >= 11 0xAB (&0xE, >>1) } u8 tssiposslope2g { sfmt decimal srom >= 11 0xAB (&0x1) } u8 gainctrlsph { sfmt decimal srom >= 11 0xAC (&0xF8, >>3) } u8 papdcap5g { sfmt decimal srom >= 11 0xAC (&0x4, >>2) } u8 tworangetssi5g { sfmt decimal srom >= 11 0xAC (&0x2, >>1) } u8 pdgain5g { sfmt decimal srom >= 11 u16 0xAC (&0x1F0, >>4) } u8 epagain5g { sfmt decimal srom >= 11 0xAD (&0xE, >>1) } u8 tssiposslope5g { sfmt decimal srom >= 11 0xAD (&0x1) } # LED duty cycle u8[2] leddc { sfmt led_dc all1 ignore srom 3 0x7C srom 4 0x5A srom 5-7 0x5A srom 8-10 0x9A srom >= 11 0x9E } # LED set u8 ledbh0 { all1 ignore srom 1-3 0x65 srom 4 0x57 srom 5-7 0x77 srom 8-10 0x97 srom >= 11 0x9B } u8 ledbh1 { all1 ignore srom 1-3 0x64 srom 4 0x56 srom 5-7 0x76 srom 8-10 0x96 srom >= 11 0x9A } u8 ledbh2 { all1 ignore srom 1-3 0x67 srom 4 0x59 srom 5-7 0x79 srom 8-10 0x99 srom >= 11 0x9D } u8 ledbh3 { all1 ignore srom 1-3 0x66 srom 4 0x58 srom 5-7 0x78 srom 8-10 0x98 srom >= 11 0x9C } # 2 bytes total # Additional power offset for Legacy Dup40 transmissions. # Applied in addition to legofdmbw20ulXpo, X=2g, 5gl, 5gm, or 5gh. # LSB nibble: 2G band, MSB nibble: 5G band high subband. # leg40dup5ghpo, leg40dup5gmpo, leg40dup5glpo, leg40dup2gpo # u16 legofdm40duppo { srom 9-10 0x196 } # 4 bytes each # OFDM power offsets for 20 MHz Legacy rates # (54, 48, 36, 24, 18, 12, 9, 6 Mbps) # legofdmbw202gpo legofdmbw20ul2gpo # u32 legofdmbw202gpo { srom 9-10 0x144 } u32 legofdmbw20ul2gpo { srom 9-10 0x148 } # 4 bytes each # 5G band: OFDM power offsets for 20 MHz Legacy rates # (54, 48, 36, 24, 18, 12, 9, 6 Mbps) # low subband : legofdmbw205glpo legofdmbw20ul2glpo # mid subband :legofdmbw205gmpo legofdmbw20ul2gmpo # high subband :legofdmbw205ghpo legofdmbw20ul2ghpo # u32 legofdmbw205glpo { srom 9-10 0x14C } u32 legofdmbw20ul5glpo { srom 9-10 0x150 } u32 legofdmbw205gmpo { srom 9-10 0x154 } u32 legofdmbw20ul5gmpo { srom 9-10 0x158 } u32 legofdmbw205ghpo { srom 9-10 0x15C } u32 legofdmbw20ul5ghpo { srom 9-10 0x160 } # mac addr override for the standard CIS LAN_NID u8[6] macaddr { sfmt macaddr srom 3 u8 0x4B, u8 0x4A, u8 0x4D, u8 0x4C, u8 0x4F, u8 0x4E srom 4 u8 0x4D, u8 0x4C, u8 0x4F, u8 0x4E, u8 0x51, u8 0x50 srom 5-7 u8 0x53, u8 0x52, u8 0x55, u8 0x54, u8 0x57, u8 0x56 srom 8-10 u8 0x8D, u8 0x8C, u8 0x8F, u8 0x8E, u8 0x91, u8 0x90 srom >= 11 u8 0x91, u8 0x90, u8 0x93, u8 0x92, u8 0x95, u8 0x94 } # 4 bytes each # mcs 0-7 power-offset. LSB nibble: m0, MSB nibble: m7 # mcsbw202gpo mcsbw20ul2gpo mcsbw402gpo # u32 mcsbw202gpo { srom 9-10 0x164 srom >= 11 0x154 } u32 mcsbw20ul2gpo { srom 9-10 0x168 } u32 mcsbw402gpo { srom 9-10 0x16C srom >= 11 0x158 } # 4 bytes each # 5G high subband mcs 0-7 power-offset. # LSB nibble: m0, MSB nibble: m7 # mcsbw205ghpo mcsbw20ul5ghpo mcsbw405ghpo # u32 mcsbw205ghpo { srom 9-10 0x188 srom >= 11 0x180 } u32 mcsbw20ul5ghpo { srom 9-10 0x18C } u32 mcsbw405ghpo { srom 9-10 0x190 srom >= 11 0x184 } # 4 bytes each # 5G low subband mcs 0-7 power-offset. # LSB nibble: m0, MSB nibble: m7 # mcsbw205glpo mcsbw20ul5glpo mcsbw405glpo # u32 mcsbw205glpo { srom 9-10 0x170 srom >= 11 0x160 } u32 mcsbw20ul5glpo { srom 9-10 0x174 } u32 mcsbw405glpo { srom 9-10 0x178 srom >= 11 0x164 } # 4 bytes each # 5G mid subband mcs 0-7 power-offset. # LSB nibble: m0, MSB nibble: m7 # mcsbw205gmpo mcsbw20ul5gmpo mcsbw405gmpo # u32 mcsbw205gmpo { srom 9-10 0x17C srom >= 11 0x170 } u32 mcsbw20ul5gmpo { srom 9-10 0x180 } u32 mcsbw405gmpo { srom 9-10 0x184 srom >= 11 0x174 } # 2 bytes total # mcs-32 power offset for each band/subband. # LSB nibble: 2G band, MSB nibble: # mcs322ghpo, mcs325gmpo, mcs325glpo, mcs322gpo # u16 mcs32po { srom 9-10 0x194 } u8 measpower { srom 8-10 0xB4 (&0xFE, >>1) srom >= 11 0xB0 (&0xFE, >>1) } u8 measpower1 { srom 8-10 0xBF (&0x7F) srom >= 11 0xBB (&0x7F) } u8 measpower2 { srom 8-10 u16 0xBE (&0x3F80, >>7) srom >= 11 u16 0xBA (&0x3F80, >>7) } u16 rawtempsense { srom 8-10 0xB4 (&0x1FF) srom >= 11 0xB0 (&0x1FF) } u8 noiselvl2ga0 { sfmt decimal srom 8-10 0x1AB (&0x1F) srom >= 11 0x1BD (&0x1F) } u8 noiselvl2ga1 { sfmt decimal srom 8-10 u16 0x1AA (&0x3E0, >>5) srom >= 11 u16 0x1BC (&0x3E0, >>5) } u8 noiselvl2ga2 { sfmt decimal srom 8-10 0x1AA (&0x7C, >>2) srom >= 11 0x1BC (&0x7C, >>2) } u8[4] noiselvl5ga0 { sfmt decimal srom >= 11 u8 0x1BF (&0x1F), u8 0x1C1 (&0x1F), u8 0x1C3 (&0x1F), u8 0x1C5 (&0x1F) } u8[4] noiselvl5ga1 { sfmt decimal srom >= 11 u16[4] 0x1BE (&0x3E0, >>5) } u8[4] noiselvl5ga2 { sfmt decimal srom >= 11 u8 0x1BE (&0x7C, >>2), u8 0x1C0 (&0x7C, >>2), u8 0x1C2 (&0x7C, >>2), u8 0x1C4 (&0x7C, >>2) } # paparambwver u8 paparambwver { sfmt decimal srom >= 11 0x190 (&0xF0, >>4) } # PA parameters: 8 (sromrev == 1) # or 9 (sromrev > 1) bytes # u16 pa0b0 { sfmt decimal srom 1-3 0x5E srom 8-10 0xC2 } u16 pa0b1 { sfmt decimal srom 1-3 0x60 srom 8-10 0xC4 } u16 pa0b2 { sfmt decimal srom 1-3 0x62 srom 8-10 0xC6 } u8 pa0itssit { sfmt decimal srom 1-3 0x71 srom 8-10 0xC0 } u8 pa0maxpwr { sfmt decimal srom 1-3 0x69 srom 8-10 0xC1 } u8 opo { srom 2-3 0x79 srom 8-10 0x143 } # 5G PA params u16 pa1b0 { sfmt decimal srom 1-3 0x6A srom 8-10 0xCC } u16 pa1b1 { sfmt decimal srom 1-3 0x6C srom 8-10 0xCE } u16 pa1b2 { sfmt decimal srom 1-3 0x6E srom 8-10 0xD0 } u16 pa1lob0 { sfmt decimal srom 2-3 0x3C srom 8-10 0xD2 } u16 pa1lob1 { sfmt decimal srom 2-3 0x3E srom 8-10 0xD4 } u16 pa1lob2 { sfmt decimal srom 2-3 0x40 srom 8-10 0xD6 } u16 pa1hib0 { sfmt decimal srom 2-3 0x42 srom 8-10 0xD8 } u16 pa1hib1 { sfmt decimal srom 2-3 0x44 srom 8-10 0xDA } u16 pa1hib2 { sfmt decimal srom 2-3 0x46 srom 8-10 0xDC } u8 pa1itssit { sfmt decimal srom 1-3 0x70 srom 8-10 0xC8 } u8 pa1maxpwr { sfmt decimal srom 1-3 0x68 srom 8-10 0xC9 } u8 pa1lomaxpwr { sfmt decimal srom 2-3 0x3A srom 8-10 0xCA } u8 pa1himaxpwr { sfmt decimal srom 2-3 0x3B srom 8-10 0xCB } u16 pdoffset40ma0 { srom >= 11 0xCA } u16 pdoffset40ma1 { srom >= 11 0xCC } u16 pdoffset40ma2 { srom >= 11 0xCE } u16 pdoffset80ma0 { srom >= 11 0xD0 } u16 pdoffset80ma1 { srom >= 11 0xD2 } u16 pdoffset80ma2 { srom >= 11 0xD4 } u8 pdoffset2g40ma0 { srom >= 11 0xC9 (&0xF) } u8 pdoffset2g40ma1 { srom >= 11 0xC9 (&0xF0, >>4) } u8 pdoffset2g40ma2 { srom >= 11 0xC8 (&0xF) } u8 pdoffset2g40mvalid { srom >= 11 0xC8 (&0x80, >>7) } # 40Mhz channel 2g/5g power offset u16 bw40po { srom 4-7 0x18E srom 8 0x196 } # 40Mhz channel dup 2g/5g power offset u16 bwduppo { srom 4-7 0x190 srom 8 0x198 } # cck2g/ofdm2g/ofdm5g power offset u16 cck2gpo { srom 4-7 0x138 srom 8 0x140 } u32 ofdm2gpo { srom 4-7 0x13A srom 8 0x142 } u32 ofdm5gpo { srom 4-7 0x13E srom 8 0x146 } u32 ofdm5glpo { srom 4-7 0x142 srom 8 0x14A } u32 ofdm5ghpo { srom 4-7 0x146 srom 8 0x14E } # cdd2g/5g power offset u16 cddpo { srom 4-7 0x18A srom 8 0x192 } # mcs2g power offset u16 mcs2gpo0 { srom 4-7 0x14A srom 8 0x152 } u16 mcs2gpo1 { srom 4-7 0x14C srom 8 0x154 } u16 mcs2gpo2 { srom 4-7 0x14E srom 8 0x156 } u16 mcs2gpo3 { srom 4-7 0x150 srom 8 0x158 } u16 mcs2gpo4 { srom 4-7 0x152 srom 8 0x15A } u16 mcs2gpo5 { srom 4-7 0x154 srom 8 0x15C } u16 mcs2gpo6 { srom 4-7 0x156 srom 8 0x15E } u16 mcs2gpo7 { srom 4-7 0x158 srom 8 0x160 } # mcs5g low-high band power offset u16 mcs5glpo0 { srom 4-7 0x16A srom 8 0x172 } u16 mcs5glpo1 { srom 4-7 0x16C srom 8 0x174 } u16 mcs5glpo2 { srom 4-7 0x16E srom 8 0x176 } u16 mcs5glpo3 { srom 4-7 0x170 srom 8 0x178 } u16 mcs5glpo4 { srom 4-7 0x172 srom 8 0x17A } u16 mcs5glpo5 { srom 4-7 0x174 srom 8 0x17C } u16 mcs5glpo6 { srom 4-7 0x176 srom 8 0x17E } u16 mcs5glpo7 { srom 4-7 0x178 srom 8 0x180 } u16 mcs5ghpo0 { srom 4-7 0x17A srom 8 0x182 } u16 mcs5ghpo1 { srom 4-7 0x17C srom 8 0x184 } u16 mcs5ghpo2 { srom 4-7 0x17E srom 8 0x186 } u16 mcs5ghpo3 { srom 4-7 0x180 srom 8 0x188 } u16 mcs5ghpo4 { srom 4-7 0x182 srom 8 0x18A } u16 mcs5ghpo5 { srom 4-7 0x184 srom 8 0x18C } u16 mcs5ghpo6 { srom 4-7 0x186 srom 8 0x18E } u16 mcs5ghpo7 { srom 4-7 0x188 srom 8 0x190 } # mcs5g mid band power offset u16 mcs5gpo0 { srom 4-7 0x15A srom 8 0x162 } u16 mcs5gpo1 { srom 4-7 0x15C srom 8 0x164 } u16 mcs5gpo2 { srom 4-7 0x15E srom 8 0x166 } u16 mcs5gpo3 { srom 4-7 0x160 srom 8 0x168 } u16 mcs5gpo4 { srom 4-7 0x162 srom 8 0x16A } u16 mcs5gpo5 { srom 4-7 0x164 srom 8 0x16C } u16 mcs5gpo6 { srom 4-7 0x166 srom 8 0x16E } u16 mcs5gpo7 { srom 4-7 0x168 srom 8 0x170 } # stbc2g/5g power offset u16 stbcpo { srom 4-7 0x18C srom 8 0x194 } u8 regrev { srom 3 0x78 srom 4 0x55 srom 5-7 0x47 srom 8-10 0x95 srom >= 11 0x99 } # 4328 2G RSSI mid pt sel & board switch arch, # 2 bytes, rev 3. # u8 rssismf2g { srom 3 0x51 (&0xF) srom 8-10 0xA5 (&0xF) } u8 rssismc2g { srom 3 0x51 (&0xF0, >>4) srom 8-10 0xA5 (&0xF0, >>4) } u8 rssisav2g { srom 3 0x50 (&0x7) srom 8-10 0xA4 (&0x7) } u8 bxa2g { srom 3 0x50 (&0x18, >>3) srom 8-10 0xA4 (&0x18, >>3) } # 4328 5G RSSI mid pt sel & board switch arch, # 2 bytes, rev 3. # u8 rssismf5g { srom 3 0x53 (&0xF) srom 8-10 0xA7 (&0xF) } u8 rssismc5g { srom 3 0x53 (&0xF0, >>4) srom 8-10 0xA7 (&0xF0, >>4) } u8 rssisav5g { srom 3 0x52 (&0x7) srom 8-10 0xA6 (&0x7) } u8 bxa5g { srom 3 0x52 (&0x18, >>3) srom 8-10 0xA6 (&0x18, >>3) } u8 rxgainerr2ga0 { srom 8-10 0x19B (&0x3F) srom >= 11 0x1C7 (&0x3F) } u8 rxgainerr2ga1 { srom 8-10 u16 0x19A (&0x7C0, >>6) srom >= 11 u16 0x1C6 (&0x7C0, >>6) } u8 rxgainerr2ga2 { srom 8-10 0x19A (&0xF8, >>3) srom >= 11 0x1C6 (&0xF8, >>3) } u8[4] rxgainerr5ga0 { srom >= 11 u8 0x1C9 (&0x3F), u8 0x1CB (&0x3F), u8 0x1CD (&0x3F), u8 0x1CF (&0x3F) } u8[4] rxgainerr5ga1 { srom >= 11 u16[4] 0x1C8 (&0x7C0, >>6) } u8[4] rxgainerr5ga2 { srom >= 11 u8 0x1C8 (&0xF8, >>3), u8 0x1CA (&0xF8, >>3), u8 0x1CC (&0xF8, >>3), u8 0x1CE (&0xF8, >>3) } u8 rxgainerr5gha0 { srom 8-10 0x1A1 (&0x3F) } u8 rxgainerr5gha1 { srom 8-10 u16 0x1A0 (&0x7C0, >>6) } u8 rxgainerr5gha2 { srom 8-10 0x1A0 (&0xF8, >>3) } u8 rxgainerr5gla0 { srom 8-10 0x19D (&0x3F) } u8 rxgainerr5gla1 { srom 8-10 u16 0x19C (&0x7C0, >>6) } u8 rxgainerr5gla2 { srom 8-10 0x19C (&0xF8, >>3) } u8 rxgainerr5gma0 { srom 8-10 0x19F (&0x3F) } u8 rxgainerr5gma1 { srom 8-10 u16 0x19E (&0x7C0, >>6) } u8 rxgainerr5gma2 { srom 8-10 0x19E (&0xF8, >>3) } u8 rxgainerr5gua0 { srom 8-10 0x1A3 (&0x3F) } u8 rxgainerr5gua1 { srom 8-10 u16 0x1A2 (&0x7C0, >>6) } u8 rxgainerr5gua2 { srom 8-10 0x1A2 (&0xF8, >>3) } # 4328 2G RX power offset i8 rxpo2g { sfmt decimal srom 3 0x5B srom 8-10 0xAD } # 4328 5G RX power offset i8 rxpo5g { sfmt decimal srom 3 0x5A srom 8-10 0xAC } u16 subband5gver { srom 8-10 u8 0x1A5 (&0x7) srom >= 11 0xD6 } # 2 bytes # byte1 tempthresh # byte2 period(msb 4 bits) | hysterisis(lsb 4 bits) # u8 tempthresh { srom 8-10 0xB2 srom >= 11 0xAE } u8 temps_period { sfmt decimal srom 8-10 0xBC (&0xF) srom >= 11 0xB8 (&0xF) } u8 temps_hysteresis { sfmt decimal srom 8-10 0xBC (&0xF0, >>4) srom >= 11 0xB8 (&0xF0, >>4) } u8 tempoffset { sfmt decimal srom 8-10 0xB3 srom >= 11 0xAF } u8 tempsense_slope { srom 8-10 0xB7 srom >= 11 0xB3 } u8 tempcorrx { srom 8-10 0xB6 (&0xFC, >>2) srom >= 11 0xB2 (&0xFC, >>2) } u8 tempsense_option { srom 8-10 0xB6 (&0x3) srom >= 11 0xB2 (&0x3) } u8 phycal_tempdelta { sfmt decimal srom 8-10 0xBD srom >= 11 0xB9 } # 4328 2G TR isolation, 1 byte u8 tri2g { srom 3 0x55 srom 8-10 0xA9 } # 4328 5G TR isolation, 3 bytes u8 tri5gl { srom 3 0x57 srom 8-10 0xAB } u8 tri5g { srom 3 0x54 srom 8-10 0xA8 } u8 tri5gh { srom 3 0x56 srom 8-10 0xAA } # phy txbf rpcalvars u16 rpcal2g { srom >= 11 0x16C } u16 rpcal5gb0 { srom >= 11 0x16E } u16 rpcal5gb1 { srom >= 11 0x17C } u16 rpcal5gb2 { srom >= 11 0x17E } u16 rpcal5gb3 { srom >= 11 0x18C } # Crystal frequency in kilohertz u32 xtalfreq { sfmt decimal srom >= 11 u16 0xB4 } # N-PHY tx power workaround u8 txpid2ga0 { srom 4-7 0x63 } u8 txpid2ga1 { srom 4-7 0x62 } u8 txpid2ga2 { srom 4-7 0x65 } u8 txpid2ga3 { srom 4-7 0x64 } u8 txpid5ga0 { srom 4-7 0x67 } u8 txpid5ga1 { srom 4-7 0x66 } u8 txpid5ga2 { srom 4-7 0x69 } u8 txpid5ga3 { srom 4-7 0x68 } u8 txpid5gha0 { srom 4-7 0x6F } u8 txpid5gha1 { srom 4-7 0x6E } u8 txpid5gha2 { srom 4-7 0x71 } u8 txpid5gha3 { srom 4-7 0x70 } u8 txpid5gla0 { srom 4-7 0x6B } u8 txpid5gla1 { srom 4-7 0x6A } u8 txpid5gla2 { srom 4-7 0x6D } u8 txpid5gla3 { srom 4-7 0x6C } u16 cckPwrOffset { srom 10 0x1B4 } u8[6] et1macaddr { sfmt macaddr srom 0-2 u8 0x55, u8 0x54, u8 0x57, u8 0x56, u8 0x59, u8 0x58 } u8 eu_edthresh2g { srom 8 0x1A9 srom 9 0x199 srom 10 0x199 srom 11 0x1D1 } u8 eu_edthresh5g { srom 8 0x1A8 srom 9 0x198 srom 10 0x198 srom 11 0x1D0 } u8 freqoffset_corr { srom 8-10 0xB9 (&0xF) } u8 hw_iqcal_en { srom 8-10 0xB9 (&0x20, >>5) } u8[6] il0macaddr { sfmt macaddr srom 0-2 u8 0x49, u8 0x48, u8 0x51, u8 0x50, u8 0x53, u8 0x52 } u8 iqcal_swp_dis { srom 8-10 0xB9 (&0x10, >>4) } u8 noisecaloffset { srom 8-9 0x1B5 } u8 noisecaloffset5g { srom 8-9 0x1B4 } u8 noiselvl5gha0 { srom 8-10 0x1B1 (&0x1F) } u8 noiselvl5gha1 { srom 8-10 u16 0x1B0 (&0x3E0, >>5) } u8 noiselvl5gha2 { srom 8-10 0x1B0 (&0x7C, >>2) } u8 noiselvl5gla0 { srom 8-10 0x1AD (&0x1F) } u8 noiselvl5gla1 { srom 8-10 u16 0x1AC (&0x3E0, >>5) } u8 noiselvl5gla2 { srom 8-10 0x1AC (&0x7C, >>2) } u8 noiselvl5gma0 { srom 8-10 0x1AF (&0x1F) } u8 noiselvl5gma1 { srom 8-10 u16 0x1AE (&0x3E0, >>5) } u8 noiselvl5gma2 { srom 8-10 0x1AE (&0x7C, >>2) } u8 noiselvl5gua0 { srom 8-10 0x1B3 (&0x1F) } u8 noiselvl5gua1 { srom 8-10 u16 0x1B2 (&0x3E0, >>5) } u8 noiselvl5gua2 { srom 8-10 0x1B2 (&0x7C, >>2) } u8 pcieingress_war { srom 8-10 0x1A7 (&0xF) } u8 pdoffsetcckma0 { srom >= 11 0x18F (&0xF) } u8 pdoffsetcckma1 { srom >= 11 0x18F (&0xF0, >>4) } u8 pdoffsetcckma2 { srom >= 11 0x18E (&0xF) } u8 sar2g { srom 9-10 0x1A9 srom >= 11 0x1BB } u8 sar5g { srom 9-10 0x1A8 srom >= 11 0x1BA } u32[5] swctrlmap_2g { srom 10 u32[4] 0x1B8, u16 0x1C8 } u16 tssifloor2g { srom >= 11 0xBE (&0x3FF) } u16[4] tssifloor5g { srom >= 11 0xC0 (&0x3FF) } u8 txidxcap2g { srom >= 11 u16 0x1A8 (&0xFF0, >>4) } u8 txidxcap5g { srom >= 11 u16 0x1AC (&0xFF0, >>4) } # # Any variables defined within a `struct` block will be interpreted relative to # the provided array of SPROM base addresses; this is used to define # a common layout defined at the given base addresses. # # To produce SPROM variable names matching those used in the Broadcom HND # ASCII 'key=value\0' NVRAM, the index number of the variable's # struct instance will be appended (e.g., given a variable of noiselvl5ga, the # generated variable instances will be named noiselvl5ga0, noiselvl5ga1, # noiselvl5ga2, noiselvl5ga3 ...) # # PHY chain[0-4] parameters struct phy_chains[] { srom 4-7 [0x080, 0x0AE, 0x0DC, 0x10A] srom 8-10 [0x0C0, 0x0E0, 0x100, 0x120] srom >= 11 [0x0D8, 0x100, 0x128] # AC-PHY PA parameters u8[4] maxp5ga { srom 4-7 u8 0xB srom 8-10 u8 0x9 srom >= 11 u8 0xD, u8 0xC, u8 0xF, u8 0xE } u16[3] pa2ga { srom >= 11 0x2 } u8 maxp2ga { srom 4-7 0x1 srom 8-10 0x1 srom >= 11 0x1 } u16[12] pa5ga { srom >= 11 0x10 } # AC-PHY rxgains u8 rxgains5ghtrelnabypa { srom >= 11 0x8 (&0x80, >>7) } u8 rxgains5ghelnagaina { srom >= 11 0x8 (&0x7) } u8 rxgains5gelnagaina { srom >= 11 0xA (&0x7) } u8 rxgains5gmtrelnabypa { srom >= 11 0x9 (&0x80, >>7) } u8 rxgains2gtrelnabypa { srom >= 11 0xB (&0x80, >>7) } u8 rxgains5gmtrisoa { srom >= 11 0x9 (&0x78, >>3) } u8 rxgains5gmelnagaina { srom >= 11 0x9 (&0x7) } u8 rxgains2gelnagaina { srom >= 11 0xB (&0x7) } u8 rxgains5gtrisoa { srom >= 11 0xA (&0x78, >>3) } u8 rxgains5gtrelnabypa { srom >= 11 0xA (&0x80, >>7) } u8 rxgains2gtrisoa { srom >= 11 0xB (&0x78, >>3) } u8 rxgains5ghtrisoa { srom >= 11 0x8 (&0x78, >>3) } # 11n PA parameters u16 pa5gw2a { srom 4-7 0x12 srom 8-10 0x10 } u16 pa5ghw1a { srom 4-7 0x20 srom 8-10 0x1A } u16 pa5glw3a { srom 4-7 0x1C } u16 pa5glw1a { srom 4-7 0x18 srom 8-10 0x14 } u16 pa5gw1a { srom 4-7 0x10 srom 8-10 0xE } u16 pa5glw0a { srom 4-7 0x16 srom 8-10 0x12 } u16 pa5gw3a { srom 4-7 0x14 } u16 pa5glw2a { srom 4-7 0x1A srom 8-10 0x16 } u16 pa5ghw3a { srom 4-7 0x24 } u16 pa5gw0a { srom 4-7 0xE srom 8-10 0xC } u8 maxp5gha { srom 4-7 0xD srom 8-10 0xB } u16 pa5ghw2a { srom 4-7 0x22 srom 8-10 0x1C } u16 pa5ghw0a { srom 4-7 0x1E srom 8-10 0x18 } u16 pa2gw3a { srom 4-7 0x8 } u16 pa2gw2a { srom 4-7 0x6 srom 8-10 0x6 } u16 pa2gw1a { srom 4-7 0x4 srom 8-10 0x4 } u16 pa2gw0a { srom 4-7 0x2 srom 8-10 0x2 } u8 maxp5gla { srom 4-7 0xC srom 8-10 0xA } u8 itt5ga { srom 4-7 0xA srom 8-10 0x8 } u8 itt2ga { srom 4-7 0x0 srom 8-10 0x0 } } Index: head/sys/dev/bhnd/siba/siba.c =================================================================== --- head/sys/dev/bhnd/siba/siba.c (revision 304869) +++ head/sys/dev/bhnd/siba/siba.c (revision 304870) @@ -1,649 +1,668 @@ /*- * Copyright (c) 2015 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include "sibareg.h" #include "sibavar.h" int siba_probe(device_t dev) { device_set_desc(dev, "SIBA BHND bus"); return (BUS_PROBE_DEFAULT); } int siba_attach(device_t dev) { struct siba_devinfo *dinfo; struct siba_softc *sc; device_t *devs; int ndevs; int error; sc = device_get_softc(dev); sc->dev = dev; /* Fetch references to the siba SIBA_CFG* blocks for all * registered devices */ if ((error = device_get_children(dev, &devs, &ndevs))) return (error); for (int i = 0; i < ndevs; i++) { struct siba_addrspace *addrspace; dinfo = device_get_ivars(devs[i]); KASSERT(!device_is_suspended(devs[i]), ("siba(4) stateful suspend handling requires that devices " "not be suspended before siba_attach()")); /* Fetch the core register address space */ addrspace = siba_find_addrspace(dinfo, BHND_PORT_DEVICE, 0, 0); if (addrspace == NULL) { device_printf(dev, "missing device registers for core %d\n", i); error = ENXIO; goto cleanup; } /* * Map the per-core configuration blocks */ KASSERT(dinfo->core_id.num_cfg_blocks <= SIBA_MAX_CFG, ("config block count %u out of range", dinfo->core_id.num_cfg_blocks)); for (u_int cfgidx = 0; cfgidx < dinfo->core_id.num_cfg_blocks; cfgidx++) { rman_res_t r_start, r_count, r_end; /* Determine the config block's address range; configuration * blocks are allocated starting at SIBA_CFG0_OFFSET, * growing downwards. */ r_start = addrspace->sa_base + SIBA_CFG0_OFFSET; r_start -= cfgidx * SIBA_CFG_SIZE; r_count = SIBA_CFG_SIZE; r_end = r_start + r_count - 1; /* Allocate the config resource */ dinfo->cfg_rid[cfgidx] = 0; dinfo->cfg[cfgidx] = BHND_BUS_ALLOC_RESOURCE(dev, dev, SYS_RES_MEMORY, &dinfo->cfg_rid[cfgidx], r_start, r_end, r_count, RF_ACTIVE); if (dinfo->cfg[cfgidx] == NULL) { device_printf(dev, "failed allocating CFG_%u for " "core %d\n", cfgidx, i); error = ENXIO; goto cleanup; } } } cleanup: free(devs, M_BHND); if (error) return (error); /* Delegate remainder to standard bhnd method implementation */ return (bhnd_generic_attach(dev)); } int siba_detach(device_t dev) { return (bhnd_generic_detach(dev)); } int siba_resume(device_t dev) { return (bhnd_generic_resume(dev)); } int siba_suspend(device_t dev) { return (bhnd_generic_suspend(dev)); } static int siba_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) { const struct siba_devinfo *dinfo; const struct bhnd_core_info *cfg; dinfo = device_get_ivars(child); cfg = &dinfo->core_id.core_info; switch (index) { case BHND_IVAR_VENDOR: *result = cfg->vendor; return (0); case BHND_IVAR_DEVICE: *result = cfg->device; return (0); case BHND_IVAR_HWREV: *result = cfg->hwrev; return (0); case BHND_IVAR_DEVICE_CLASS: *result = bhnd_core_class(cfg); return (0); case BHND_IVAR_VENDOR_NAME: *result = (uintptr_t) bhnd_vendor_name(cfg->vendor); return (0); case BHND_IVAR_DEVICE_NAME: *result = (uintptr_t) bhnd_core_name(cfg); return (0); case BHND_IVAR_CORE_INDEX: *result = cfg->core_idx; return (0); case BHND_IVAR_CORE_UNIT: *result = cfg->unit; return (0); default: return (ENOENT); } } static int siba_write_ivar(device_t dev, device_t child, int index, uintptr_t value) { switch (index) { case BHND_IVAR_VENDOR: case BHND_IVAR_DEVICE: case BHND_IVAR_HWREV: case BHND_IVAR_DEVICE_CLASS: case BHND_IVAR_VENDOR_NAME: case BHND_IVAR_DEVICE_NAME: case BHND_IVAR_CORE_INDEX: case BHND_IVAR_CORE_UNIT: return (EINVAL); default: return (ENOENT); } } static struct resource_list * siba_get_resource_list(device_t dev, device_t child) { struct siba_devinfo *dinfo = device_get_ivars(child); return (&dinfo->resources); } static device_t siba_find_hostb_device(device_t dev) { struct siba_softc *sc = device_get_softc(dev); /* This is set (or not) by the concrete siba driver subclass. */ return (sc->hostb_dev); } static int siba_reset_core(device_t dev, device_t child, uint16_t flags) { struct siba_devinfo *dinfo; if (device_get_parent(child) != dev) BHND_BUS_RESET_CORE(device_get_parent(dev), child, flags); dinfo = device_get_ivars(child); /* Can't reset the core without access to the CFG0 registers */ if (dinfo->cfg[0] == NULL) return (ENODEV); // TODO - perform reset return (ENXIO); } static int siba_suspend_core(device_t dev, device_t child) { struct siba_devinfo *dinfo; if (device_get_parent(child) != dev) BHND_BUS_SUSPEND_CORE(device_get_parent(dev), child); dinfo = device_get_ivars(child); /* Can't suspend the core without access to the CFG0 registers */ if (dinfo->cfg[0] == NULL) return (ENODEV); // TODO - perform suspend return (ENXIO); } +static uint32_t +siba_read_config(device_t dev, device_t child, bus_size_t offset, u_int width) +{ + /* Unsuported */ + return (UINT32_MAX); +} +static void +siba_write_config(device_t dev, device_t child, bus_size_t offset, uint32_t val, + u_int width) +{ + /* Unsuported */ + return; +} + static u_int siba_get_port_count(device_t dev, device_t child, bhnd_port_type type) { struct siba_devinfo *dinfo; /* delegate non-bus-attached devices to our parent */ if (device_get_parent(child) != dev) return (BHND_BUS_GET_PORT_COUNT(device_get_parent(dev), child, type)); dinfo = device_get_ivars(child); return (siba_addrspace_port_count(dinfo)); } static u_int siba_get_region_count(device_t dev, device_t child, bhnd_port_type type, u_int port) { struct siba_devinfo *dinfo; /* delegate non-bus-attached devices to our parent */ if (device_get_parent(child) != dev) return (BHND_BUS_GET_REGION_COUNT(device_get_parent(dev), child, type, port)); dinfo = device_get_ivars(child); if (!siba_is_port_valid(dinfo, type, port)) return (0); return (siba_addrspace_region_count(dinfo, port)); } static int siba_get_port_rid(device_t dev, device_t child, bhnd_port_type port_type, u_int port_num, u_int region_num) { struct siba_devinfo *dinfo; struct siba_addrspace *addrspace; /* delegate non-bus-attached devices to our parent */ if (device_get_parent(child) != dev) return (BHND_BUS_GET_PORT_RID(device_get_parent(dev), child, port_type, port_num, region_num)); dinfo = device_get_ivars(child); addrspace = siba_find_addrspace(dinfo, port_type, port_num, region_num); if (addrspace == NULL) return (-1); return (addrspace->sa_rid); } static int siba_decode_port_rid(device_t dev, device_t child, int type, int rid, bhnd_port_type *port_type, u_int *port_num, u_int *region_num) { struct siba_devinfo *dinfo; /* delegate non-bus-attached devices to our parent */ if (device_get_parent(child) != dev) return (BHND_BUS_DECODE_PORT_RID(device_get_parent(dev), child, type, rid, port_type, port_num, region_num)); dinfo = device_get_ivars(child); /* Ports are always memory mapped */ if (type != SYS_RES_MEMORY) return (EINVAL); for (int i = 0; i < dinfo->core_id.num_addrspace; i++) { if (dinfo->addrspace[i].sa_rid != rid) continue; *port_type = BHND_PORT_DEVICE; *port_num = siba_addrspace_port(i); *region_num = siba_addrspace_region(i); return (0); } /* Not found */ return (ENOENT); } static int siba_get_region_addr(device_t dev, device_t child, bhnd_port_type port_type, u_int port_num, u_int region_num, bhnd_addr_t *addr, bhnd_size_t *size) { struct siba_devinfo *dinfo; struct siba_addrspace *addrspace; /* delegate non-bus-attached devices to our parent */ if (device_get_parent(child) != dev) { return (BHND_BUS_GET_REGION_ADDR(device_get_parent(dev), child, port_type, port_num, region_num, addr, size)); } dinfo = device_get_ivars(child); addrspace = siba_find_addrspace(dinfo, port_type, port_num, region_num); if (addrspace == NULL) return (ENOENT); *addr = addrspace->sa_base; *size = addrspace->sa_size - addrspace->sa_bus_reserved; return (0); } /** * Register all address space mappings for @p di. * * @param dev The siba bus device. * @param di The device info instance on which to register all address * space entries. * @param r A resource mapping the enumeration table block for @p di. */ static int siba_register_addrspaces(device_t dev, struct siba_devinfo *di, struct resource *r) { struct siba_core_id *cid; uint32_t addr; uint32_t size; int error; cid = &di->core_id; /* Register the device address space entries */ for (uint8_t i = 0; i < di->core_id.num_addrspace; i++) { uint32_t adm; u_int adm_offset; uint32_t bus_reserved; /* Determine the register offset */ adm_offset = siba_admatch_offset(i); if (adm_offset == 0) { device_printf(dev, "addrspace %hhu is unsupported", i); return (ENODEV); } /* Fetch the address match register value */ adm = bus_read_4(r, adm_offset); /* Parse the value */ if ((error = siba_parse_admatch(adm, &addr, &size))) { device_printf(dev, "failed to decode address " " match register value 0x%x\n", adm); return (error); } /* If this is the device's core/enumeration addrespace, * reserve the Sonics configuration register blocks for the * use of our bus. */ bus_reserved = 0; if (i == SIBA_CORE_ADDRSPACE) bus_reserved = cid->num_cfg_blocks * SIBA_CFG_SIZE; /* Append the region info */ error = siba_append_dinfo_region(di, i, addr, size, bus_reserved); if (error) return (error); } return (0); } static struct bhnd_devinfo * siba_alloc_bhnd_dinfo(device_t dev) { struct siba_devinfo *dinfo = siba_alloc_dinfo(dev); return ((struct bhnd_devinfo *)dinfo); } static void siba_free_bhnd_dinfo(device_t dev, struct bhnd_devinfo *dinfo) { siba_free_dinfo(dev, (struct siba_devinfo *)dinfo); } /** * Scan the core table and add all valid discovered cores to * the bus. * * @param dev The siba bus device. * @param chipid The chip identifier, if the device does not provide a * ChipCommon core. Should o NULL otherwise. */ int siba_add_children(device_t dev, const struct bhnd_chipid *chipid) { struct bhnd_chipid ccid; struct bhnd_core_info *cores; struct siba_devinfo *dinfo; struct resource *r; int rid; int error; dinfo = NULL; cores = NULL; r = NULL; /* * Try to determine the number of device cores via the ChipCommon * identification registers. * * A small number of very early devices do not include a ChipCommon * core, in which case our caller must supply the chip identification * information via a non-NULL chipid parameter. */ if (chipid == NULL) { uint32_t idhigh, ccreg; uint16_t vendor, device; uint8_t ccrev; /* Map the first core's register block. If the ChipCommon core * exists, it will always be the first core. */ rid = 0; r = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, SIBA_CORE_ADDR(0), SIBA_CORE_SIZE, SIBA_CORE_ADDR(0) + SIBA_CORE_SIZE - 1, RF_ACTIVE); /* Identify the core */ idhigh = bus_read_4(r, SB0_REG_ABS(SIBA_CFG0_IDHIGH)); vendor = SIBA_REG_GET(idhigh, IDH_VENDOR); device = SIBA_REG_GET(idhigh, IDH_DEVICE); ccrev = SIBA_IDH_CORE_REV(idhigh); if (vendor != OCP_VENDOR_BCM || device != BHND_COREID_CC) { device_printf(dev, "cannot identify device: no chipcommon core " "found\n"); error = ENXIO; goto cleanup; } /* Identify the chipset */ ccreg = bus_read_4(r, CHIPC_ID); ccid = bhnd_parse_chipid(ccreg, SIBA_ENUM_ADDR); if (!CHIPC_NCORES_MIN_HWREV(ccrev)) { switch (ccid.chip_id) { case BHND_CHIPID_BCM4306: ccid.ncores = 6; break; case BHND_CHIPID_BCM4704: ccid.ncores = 9; break; case BHND_CHIPID_BCM5365: /* * BCM5365 does support ID_NUMCORE in at least * some of its revisions, but for unknown * reasons, Broadcom's drivers always exclude * the ChipCommon revision (0x5) used by BCM5365 * from the set of revisions supporting * ID_NUMCORE, and instead supply a fixed value. * * Presumably, at least some of these devices * shipped with a broken ID_NUMCORE value. */ ccid.ncores = 7; break; default: device_printf(dev, "unable to determine core " "count for unrecognized chipset 0x%hx\n", ccid.chip_id); error = ENXIO; goto cleanup; } } chipid = &ccid; bus_release_resource(dev, SYS_RES_MEMORY, rid, r); } /* Allocate our temporary core table and enumerate all cores */ cores = malloc(sizeof(*cores) * chipid->ncores, M_BHND, M_NOWAIT); if (cores == NULL) return (ENOMEM); /* Add all cores. */ for (u_int i = 0; i < chipid->ncores; i++) { struct siba_core_id cid; device_t child; uint32_t idhigh, idlow; rman_res_t r_count, r_end, r_start; /* Map the core's register block */ rid = 0; r_start = SIBA_CORE_ADDR(i); r_count = SIBA_CORE_SIZE; r_end = r_start + SIBA_CORE_SIZE - 1; r = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, r_start, r_end, r_count, RF_ACTIVE); if (r == NULL) { error = ENXIO; goto cleanup; } /* Add the child device */ child = BUS_ADD_CHILD(dev, 0, NULL, -1); if (child == NULL) { error = ENXIO; goto cleanup; } /* Read the core info */ idhigh = bus_read_4(r, SB0_REG_ABS(SIBA_CFG0_IDHIGH)); idlow = bus_read_4(r, SB0_REG_ABS(SIBA_CFG0_IDLOW)); cid = siba_parse_core_id(idhigh, idlow, i, 0); cores[i] = cid.core_info; /* Determine unit number */ for (u_int j = 0; j < i; j++) { if (cores[j].vendor == cores[i].vendor && cores[j].device == cores[i].device) cores[i].unit++; } /* Initialize per-device bus info */ if ((dinfo = device_get_ivars(child)) == NULL) { error = ENXIO; goto cleanup; } if ((error = siba_init_dinfo(dev, dinfo, &cid))) goto cleanup; /* Register the core's address space(s). */ if ((error = siba_register_addrspaces(dev, dinfo, r))) goto cleanup; /* If pins are floating or the hardware is otherwise * unpopulated, the device shouldn't be used. */ if (bhnd_is_hw_disabled(child)) device_disable(child); /* Release our resource */ bus_release_resource(dev, SYS_RES_MEMORY, rid, r); r = NULL; + + /* Issue bus callback for fully initialized child. */ + BHND_BUS_CHILD_ADDED(dev, child); } cleanup: if (cores != NULL) free(cores, M_BHND); if (r != NULL) bus_release_resource(dev, SYS_RES_MEMORY, rid, r); return (error); } static device_method_t siba_methods[] = { /* Device interface */ DEVMETHOD(device_probe, siba_probe), DEVMETHOD(device_attach, siba_attach), DEVMETHOD(device_detach, siba_detach), DEVMETHOD(device_resume, siba_resume), DEVMETHOD(device_suspend, siba_suspend), /* Bus interface */ DEVMETHOD(bus_read_ivar, siba_read_ivar), DEVMETHOD(bus_write_ivar, siba_write_ivar), DEVMETHOD(bus_get_resource_list, siba_get_resource_list), /* BHND interface */ DEVMETHOD(bhnd_bus_find_hostb_device, siba_find_hostb_device), DEVMETHOD(bhnd_bus_alloc_devinfo, siba_alloc_bhnd_dinfo), DEVMETHOD(bhnd_bus_free_devinfo, siba_free_bhnd_dinfo), DEVMETHOD(bhnd_bus_reset_core, siba_reset_core), DEVMETHOD(bhnd_bus_suspend_core, siba_suspend_core), + DEVMETHOD(bhnd_bus_read_config, siba_read_config), + DEVMETHOD(bhnd_bus_write_config, siba_write_config), DEVMETHOD(bhnd_bus_get_port_count, siba_get_port_count), DEVMETHOD(bhnd_bus_get_region_count, siba_get_region_count), DEVMETHOD(bhnd_bus_get_port_rid, siba_get_port_rid), DEVMETHOD(bhnd_bus_decode_port_rid, siba_decode_port_rid), DEVMETHOD(bhnd_bus_get_region_addr, siba_get_region_addr), DEVMETHOD_END }; DEFINE_CLASS_1(bhnd, siba_driver, siba_methods, sizeof(struct siba_softc), bhnd_driver); MODULE_VERSION(siba, 1); MODULE_DEPEND(siba, bhnd, 1, 1, 1); Index: head/sys/mips/broadcom/bcm_machdep.c =================================================================== --- head/sys/mips/broadcom/bcm_machdep.c (revision 304869) +++ head/sys/mips/broadcom/bcm_machdep.c (revision 304870) @@ -1,436 +1,437 @@ /*- * Copyright (c) 2007 Bruce M. Simpson. * Copyright (c) 2016 Michael Zhilin * Copyright (c) 2016 Landon Fuller * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_ddb.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include +#include #include "bcm_machdep.h" #include "bcm_mips_exts.h" #include "bcm_socinfo.h" #ifdef CFE #include #endif #if 0 #define BCM_TRACE(_fmt, ...) printf(_fmt, ##__VA_ARGS__) #else #define BCM_TRACE(_fmt, ...) #endif static int bcm_find_core(struct bhnd_chipid *chipid, bhnd_devclass_t devclass, int unit, struct bhnd_core_info *info, uintptr_t *addr); static int bcm_init_platform_data(struct bcm_platform *pdata); /* Allow bus-specific implementations to override bcm_find_core_(bcma|siba) * symbols, if included in the kernel build */ __weak_reference(bcm_find_core_default, bcm_find_core_bcma); __weak_reference(bcm_find_core_default, bcm_find_core_siba); extern int *edata; extern int *end; static struct bcm_platform bcm_platform_data; static bool bcm_platform_data_avail = false; struct bcm_platform * bcm_get_platform(void) { if (!bcm_platform_data_avail) panic("platform data not available"); return (&bcm_platform_data); } /* Default (no-op) bcm_find_core() implementation. */ int bcm_find_core_default(struct bhnd_chipid *chipid, bhnd_devclass_t devclass, int unit, struct bhnd_core_info *info, uintptr_t *addr) { return (ENODEV); } /** * Search @p chipid's enumeration table for a core with @p devclass and * @p unit. * * @param chipid Chip identification data, including the address * of the enumeration table to be searched. * @param devclass Search for a core matching this device class. * @param unit The core's required unit number. * @param[out] info On success, will be populated with the core * info. */ static int bcm_find_core(struct bhnd_chipid *chipid, bhnd_devclass_t devclass, int unit, struct bhnd_core_info *info, uintptr_t *addr) { switch (chipid->chip_type) { case BHND_CHIPTYPE_SIBA: return (bcm_find_core_siba(chipid, devclass, unit, info, addr)); break; default: if (!BHND_CHIPTYPE_HAS_EROM(chipid->chip_type)) { printf("%s: unsupported chip type: %d\n", __FUNCTION__, chipid->chip_type); return (ENXIO); } return (bcm_find_core_bcma(chipid, devclass, unit, info, addr)); } } /** * Populate platform configuration data. */ static int bcm_init_platform_data(struct bcm_platform *pdata) { uint32_t reg; bhnd_addr_t enum_addr; long maddr; uint8_t chip_type; bool aob, pmu; int error; /* Fetch CFE console handle (if any). Must be initialized before * any calls to printf/early_putc. */ #ifdef CFE if ((pdata->cfe_console = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE)) < 0) pdata->cfe_console = -1; #endif /* Fetch bhnd/chipc address */ if (resource_long_value("bhnd", 0, "maddr", &maddr) == 0) pdata->cc_addr = (u_long)maddr; else pdata->cc_addr = BHND_DEFAULT_CHIPC_ADDR; /* Read chip identifier from ChipCommon */ reg = BCM_SOC_READ_4(pdata->cc_addr, CHIPC_ID); chip_type = CHIPC_GET_BITS(reg, CHIPC_ID_BUS); if (BHND_CHIPTYPE_HAS_EROM(chip_type)) enum_addr = BCM_SOC_READ_4(pdata->cc_addr, CHIPC_EROMPTR); else enum_addr = pdata->cc_addr; pdata->id = bhnd_parse_chipid(reg, enum_addr); /* Fetch chipc core info and capabilities */ pdata->cc_caps = BCM_SOC_READ_4(pdata->cc_addr, CHIPC_CAPABILITIES); error = bcm_find_core(&pdata->id, BHND_DEVCLASS_CC, 0, &pdata->cc_id, NULL); if (error) { printf("%s: error locating chipc core: %d", __FUNCTION__, error); return (error); } if (CHIPC_HWREV_HAS_CAP_EXT(pdata->cc_id.hwrev)) { pdata->cc_caps_ext = BCM_SOC_READ_4(pdata->cc_addr, CHIPC_CAPABILITIES_EXT); } else { pdata->cc_caps_ext = 0x0; } /* Fetch PMU info */ pmu = CHIPC_GET_FLAG(pdata->cc_caps, CHIPC_CAP_PMU); aob = CHIPC_GET_FLAG(pdata->cc_caps_ext, CHIPC_CAP2_AOB); if (pmu && aob) { /* PMU block mapped to a PMU core on the Always-on-Bus (aob) */ error = bcm_find_core(&pdata->id, BHND_DEVCLASS_PMU, 0, &pdata->pmu_id, &pdata->pmu_addr); if (error) { printf("%s: error locating pmu core: %d", __FUNCTION__, error); return (error); } } else if (pmu) { /* PMU block mapped to chipc */ pdata->pmu_addr = pdata->cc_addr; pdata->pmu_id = pdata->cc_id; } else { /* No PMU */ pdata->pmu_addr = 0x0; memset(&pdata->pmu_id, 0, sizeof(pdata->pmu_id)); } bcm_platform_data_avail = true; return (0); } void platform_cpu_init() { /* Nothing special */ } static void mips_init(void) { int i, j; printf("entry: mips_init()\n"); #ifdef CFE /* * Query DRAM memory map from CFE. */ physmem = 0; for (i = 0; i < 10; i += 2) { int result; uint64_t addr, len, type; result = cfe_enummem(i / 2, 0, &addr, &len, &type); if (result < 0) { BCM_TRACE("There is no phys memory for: %d\n", i); phys_avail[i] = phys_avail[i + 1] = 0; break; } if (type != CFE_MI_AVAILABLE) { BCM_TRACE("phys memory is not available: %d\n", i); continue; } phys_avail[i] = addr; if (i == 0 && addr == 0) { /* * If this is the first physical memory segment probed * from CFE, omit the region at the start of physical * memory where the kernel has been loaded. */ phys_avail[i] += MIPS_KSEG0_TO_PHYS(kernel_kseg0_end); } BCM_TRACE("phys memory is available for: %d\n", i); BCM_TRACE(" => addr = %jx\n", addr); BCM_TRACE(" => len = %jd\n", len); phys_avail[i + 1] = addr + len; physmem += len; } BCM_TRACE("Total phys memory is : %ld\n", physmem); realmem = btoc(physmem); #endif for (j = 0; j < i; j++) dump_avail[j] = phys_avail[j]; physmem = realmem; init_param1(); init_param2(physmem); mips_cpu_init(); pmap_bootstrap(); mips_proc0_init(); mutex_init(); kdb_init(); #ifdef KDB if (boothowto & RB_KDB) kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); #endif } void platform_reset(void) { bool bcm4785war; printf("bcm::platform_reset()\n"); intr_disable(); #ifdef CFE /* Fall back on CFE if reset requested during platform * data initialization */ if (!bcm_platform_data_avail) { cfe_exit(0, 0); while (1); } #endif /* Handle BCM4785-specific behavior */ bcm4785war = false; if (bcm_get_platform()->id.chip_id == BHND_CHIPID_BCM4785) { bcm4785war = true; /* Switch to async mode */ bcm_mips_wr_pllcfg3(MIPS_BCMCFG_PLLCFG3_SM); } /* Set watchdog (PMU or ChipCommon) */ if (bcm_get_platform()->pmu_addr != 0x0) { - BCM_CHIPC_WRITE_4(CHIPC_PMU_WATCHDOG, 1); + BCM_CHIPC_WRITE_4(BHND_PMU_WATCHDOG, 1); } else BCM_CHIPC_WRITE_4(CHIPC_WATCHDOG, 1); /* BCM4785 */ if (bcm4785war) { mips_sync(); __asm __volatile("wait"); } while (1); } void platform_start(__register_t a0, __register_t a1, __register_t a2, __register_t a3) { vm_offset_t kernend; uint64_t platform_counter_freq; struct bcm_socinfo *socinfo; int error; /* clear the BSS and SBSS segments */ kernend = (vm_offset_t)&end; memset(&edata, 0, kernend - (vm_offset_t)(&edata)); mips_postboot_fixup(); /* Initialize pcpu stuff */ mips_pcpu0_init(); #ifdef CFE /* * Initialize CFE firmware trampolines. This must be done * before any CFE APIs are called, including writing * to the CFE console. * * CFE passes the following values in registers: * a0: firmware handle * a2: firmware entry point * a3: entry point seal */ if (a3 == CFE_EPTSEAL) cfe_init(a0, a2); #endif /* Init BCM platform data */ if ((error = bcm_init_platform_data(&bcm_platform_data))) panic("bcm_init_platform_data() failed: %d", error); socinfo = bcm_get_socinfo(); platform_counter_freq = socinfo->cpurate * 1000 * 1000; /* BCM4718 is 480MHz */ mips_timer_early_init(platform_counter_freq); cninit(); mips_init(); mips_timer_init_params(platform_counter_freq, socinfo->double_count); } /* * CFE-based EARLY_PRINTF support. To use, add the following to the kernel * config: * option EARLY_PRINTF * option CFE * device cfe */ #if defined(EARLY_PRINTF) && defined(CFE) static void bcm_cfe_eputc(int c) { unsigned char ch; int handle; ch = (unsigned char) c; /* bcm_get_platform() cannot be used here, as we may be called * from bcm_init_platform_data(). */ if ((handle = bcm_platform_data.cfe_console) < 0) return; if (ch == '\n') early_putc('\r'); while ((cfe_write(handle, &ch, 1)) == 0) continue; } early_putc_t *early_putc = bcm_cfe_eputc; #endif /* EARLY_PRINTF */ Index: head/sys/modules/bhnd/Makefile =================================================================== --- head/sys/modules/bhnd/Makefile (revision 304869) +++ head/sys/modules/bhnd/Makefile (revision 304870) @@ -1,32 +1,46 @@ # $FreeBSD$ .PATH: ${.CURDIR}/../../dev/bhnd +.PATH: ${.CURDIR}/../../dev/bhnd/cores/chipc +.PATH: ${.CURDIR}/../../dev/bhnd/cores/chipc/pwrctl +.PATH: ${.CURDIR}/../../dev/bhnd/cores/pmu .PATH: ${.CURDIR}/../../dev/bhnd/nvram KMOD= bhnd -SRCS= bhnd.c \ - bhnd_subr.c +SRCS= bhnd.c bhnd_subr.c +SRCS+= bhnd_bus_if.c bhnd_bus_if.h +# ChipCommon +SRCS+= chipc.c chipc_subr.c +SRCS+= bhnd_sprom_chipc.c \ + bhnd_pmu_chipc.c \ + bhnd_pwrctl.c bhnd_pwrctl_subr.c +SRCS+= bhnd_chipc_if.c bhnd_chipc_if.h + +# PMU +SRCS+= bhnd_pmu.c \ + bhnd_pmu_core.c \ + bhnd_pmu_subr.c +SRCS+= bhnd_pmu_if.c bhnd_pmu_if.h + +# NVRAM/SPROM SRCS+= bhnd_nvram.c \ bhnd_nvram_parser.c \ bhnd_sprom.c \ bhnd_sprom_parser.c SRCS+= bhnd_nvram_common.c SRCS+= bhnd_nvram_map.h bhnd_nvram_map_data.h - -SRCS+= bhnd_bus_if.c bhnd_bus_if.h \ - bhnd_chipc_if.c bhnd_chipc_if.h \ - bhnd_nvram_if.c bhnd_nvram_if.h +SRCS+= bhnd_nvram_if.c bhnd_nvram_if.h SRCS+= device_if.h bus_if.h SUBDIR= bcma \ bcma_bhndb \ bhndb \ bhndb_pci \ cores \ siba \ siba_bhndb .include .include Index: head/sys/modules/bhnd/cores/bhnd_chipc/Makefile =================================================================== --- head/sys/modules/bhnd/cores/bhnd_chipc/Makefile (revision 304869) +++ head/sys/modules/bhnd/cores/bhnd_chipc/Makefile (nonexistent) @@ -1,11 +0,0 @@ -# $FreeBSD$ - -.PATH: ${.CURDIR}/../../../../dev/bhnd/cores/chipc - -KMOD= bhnd_chipc -SRCS= chipc.c chipc_subr.c \ - bhnd_sprom_chipc.c -SRCS+= device_if.h bus_if.h bhnd_bus_if.h \ - bhnd_chipc_if.h bhnd_nvram_if.h - -.include Property changes on: head/sys/modules/bhnd/cores/bhnd_chipc/Makefile ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/modules/bhnd/cores/Makefile =================================================================== --- head/sys/modules/bhnd/cores/Makefile (revision 304869) +++ head/sys/modules/bhnd/cores/Makefile (revision 304870) @@ -1,8 +1,7 @@ # $FreeBSD$ -SUBDIR= bhnd_chipc \ - bhnd_pci \ +SUBDIR= bhnd_pci \ bhnd_pci_hostb \ bhnd_pcib .include