Index: head/sys/dev/bhnd/bcma/bcma_erom.c =================================================================== --- head/sys/dev/bhnd/bcma/bcma_erom.c (revision 304858) +++ head/sys/dev/bhnd/bcma/bcma_erom.c (revision 304859) @@ -1,916 +1,1142 @@ /*- * Copyright (c) 2015 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include "bcma_eromreg.h" #include "bcma_eromvar.h" /* * BCMA Enumeration ROM (EROM) Table * * Provides auto-discovery of BCMA cores on Broadcom's HND SoC. * * The EROM core address can be found at BCMA_CC_EROM_ADDR within the * ChipCommon registers. The table itself is comprised of 32-bit * type-tagged entries, organized into an array of variable-length * core descriptor records. * * The final core descriptor is followed by a 32-bit BCMA_EROM_TABLE_EOF (0xF) * marker. */ static const char *erom_entry_type_name (uint8_t entry); static int erom_read32(struct bcma_erom *erom, uint32_t *entry); static int erom_skip32(struct bcma_erom *erom); static int erom_skip_core(struct bcma_erom *erom); static int erom_skip_mport(struct bcma_erom *erom); static int erom_skip_sport_region(struct bcma_erom *erom); static int erom_seek_next(struct bcma_erom *erom, uint8_t etype); +static int erom_region_to_port_type(struct bcma_erom *erom, + uint8_t region_type, bhnd_port_type *port_type); -#define EROM_LOG(erom, fmt, ...) \ - device_printf(erom->dev, "erom[0x%llx]: " fmt, \ - (unsigned long long) (erom->offset), ##__VA_ARGS__); +#define EROM_LOG(erom, fmt, ...) do { \ + if (erom->dev != NULL) { \ + device_printf(erom->dev, "erom[0x%llx]: " fmt, \ + (unsigned long long) (erom->offset), ##__VA_ARGS__);\ + } else { \ + printf("erom[0x%llx]: " fmt, \ + (unsigned long long) (erom->offset), ##__VA_ARGS__);\ + } \ +} while(0) /** * Open an EROM table for reading. * * @param[out] erom On success, will be populated with a valid EROM * read state. * @param r An active resource mapping the EROM core. * @param offset Offset of the EROM core within @p resource. * * @retval 0 success * @retval non-zero if the erom table could not be opened. */ int -bcma_erom_open(struct bcma_erom *erom, struct resource *r, bus_size_t offset) +bcma_erom_open(struct bcma_erom *erom, struct resource *r, + bus_size_t offset) { + return (bhnd_erom_bus_space_open(erom, rman_get_device(r), + rman_get_bustag(r), rman_get_bushandle(r), offset)); + + return (0); +} + +/** + * Open an EROM table for reading using the provided bus space tag and + * handle. + * + * @param[out] erom On success, will be populated with a valid EROM + * read state. + * @param dev The owning device, or NULL if none. + * @param bst EROM table bus space tag. + * @param bsh EROM table bus space handle. + * @param offset Offset of the EROM core from @p resource. + * + * @retval 0 success + * @retval non-zero if the erom table could not be opened. + */ +int +bhnd_erom_bus_space_open(struct bcma_erom *erom, device_t dev, + bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t offset) +{ /* Initialize the EROM reader */ - erom->dev = rman_get_device(r); - erom->r = r; + erom->dev = dev; + erom->bst = bst; + erom->bsh = bsh; erom->start = offset + BCMA_EROM_TABLE_START; erom->offset = 0; return (0); } /** Return the type name for an EROM entry */ static const char * erom_entry_type_name (uint8_t entry) { switch (BCMA_EROM_GET_ATTR(entry, ENTRY_TYPE)) { case BCMA_EROM_ENTRY_TYPE_CORE: return "core"; case BCMA_EROM_ENTRY_TYPE_MPORT: return "mport"; case BCMA_EROM_ENTRY_TYPE_REGION: return "region"; default: return "unknown"; } } /** * Return the current read position. */ bus_size_t bcma_erom_tell(struct bcma_erom *erom) { return (erom->offset); } /** * Seek to an absolute read position. */ void bcma_erom_seek(struct bcma_erom *erom, bus_size_t offset) { erom->offset = offset; } /** * Read a 32-bit entry value from the EROM table without advancing the * read position. * * @param erom EROM read state. * @param entry Will contain the read result on success. * @retval 0 success * @retval ENOENT The end of the EROM table was reached. * @retval non-zero The read could not be completed. */ int bcma_erom_peek32(struct bcma_erom *erom, uint32_t *entry) { if (erom->offset >= BCMA_EROM_TABLE_SIZE) { EROM_LOG(erom, "BCMA EROM table missing terminating EOF\n"); return (EINVAL); } - *entry = bus_read_4(erom->r, erom->start + erom->offset); + *entry = bus_space_read_4(erom->bst, erom->bsh, + erom->start + erom->offset); return (0); } /** * Read a 32-bit entry value from the EROM table. * * @param erom EROM read state. * @param entry Will contain the read result on success. * @retval 0 success * @retval ENOENT The end of the EROM table was reached. * @retval non-zero The read could not be completed. */ static int erom_read32(struct bcma_erom *erom, uint32_t *entry) { int error; if ((error = bcma_erom_peek32(erom, entry)) == 0) erom->offset += 4; return (error); } /** * Read and discard 32-bit entry value from the EROM table. * * @param erom EROM read state. * @retval 0 success * @retval ENOENT The end of the EROM table was reached. * @retval non-zero The read could not be completed. */ static int erom_skip32(struct bcma_erom *erom) { uint32_t entry; return erom_read32(erom, &entry); } /** * Read and discard a core descriptor from the EROM table. * * @param erom EROM read state. * @retval 0 success * @retval ENOENT The end of the EROM table was reached. * @retval non-zero The read could not be completed. */ static int erom_skip_core(struct bcma_erom *erom) { struct bcma_erom_core core; return (bcma_erom_parse_core(erom, &core)); } /** * Read and discard a master port descriptor from the EROM table. * * @param erom EROM read state. * @retval 0 success * @retval ENOENT The end of the EROM table was reached. * @retval non-zero The read could not be completed. */ static int erom_skip_mport(struct bcma_erom *erom) { struct bcma_erom_mport mp; return (bcma_erom_parse_mport(erom, &mp)); } /** * Read and discard a port region descriptor from the EROM table. * * @param erom EROM read state. * @retval 0 success * @retval ENOENT The end of the EROM table was reached. * @retval non-zero The read could not be completed. */ static int erom_skip_sport_region(struct bcma_erom *erom) { struct bcma_erom_sport_region r; return (bcma_erom_parse_sport_region(erom, &r)); } /** * Seek to the next entry matching the given EROM entry type. * * @param erom EROM read state. * @param etype One of BCMA_EROM_ENTRY_TYPE_CORE, * BCMA_EROM_ENTRY_TYPE_MPORT, or BCMA_EROM_ENTRY_TYPE_REGION. * @retval 0 success * @retval ENOENT The end of the EROM table was reached. * @retval non-zero Reading or parsing the descriptor failed. */ static int erom_seek_next(struct bcma_erom *erom, uint8_t etype) { uint32_t entry; int error; /* Iterate until we hit an entry matching the requested type. */ while (!(error = bcma_erom_peek32(erom, &entry))) { /* Handle EOF */ if (entry == BCMA_EROM_TABLE_EOF) return (ENOENT); /* Invalid entry */ if (!BCMA_EROM_GET_ATTR(entry, ENTRY_ISVALID)) return (EINVAL); /* Entry type matches? */ if (BCMA_EROM_GET_ATTR(entry, ENTRY_TYPE) == etype) return (0); /* Skip non-matching entry types. */ switch (BCMA_EROM_GET_ATTR(entry, ENTRY_TYPE)) { case BCMA_EROM_ENTRY_TYPE_CORE: if ((error = erom_skip_core(erom))) return (error); break; case BCMA_EROM_ENTRY_TYPE_MPORT: if ((error = erom_skip_mport(erom))) return (error); break; case BCMA_EROM_ENTRY_TYPE_REGION: if ((error = erom_skip_sport_region(erom))) return (error); break; default: /* Unknown entry type! */ return (EINVAL); } } return (error); } /** * Return the read position to the start of the EROM table. * * @param erom EROM read state. */ void bcma_erom_reset(struct bcma_erom *erom) { erom->offset = 0; } /** + * Seek to the next core entry. + * + * @param erom EROM read state. + * @retval 0 success + * @retval ENOENT The end of the EROM table was reached. + * @retval non-zero Reading or parsing failed. + */ +int +bcma_erom_seek_next_core(struct bcma_erom *erom) +{ + return (erom_seek_next(erom, BCMA_EROM_ENTRY_TYPE_CORE)); +} + +/** * Seek to the requested core entry. * * @param erom EROM read state. * @param core_index Index of the core to seek to. * @retval 0 success * @retval ENOENT The end of the EROM table was reached before @p index was * found. * @retval non-zero Reading or parsing failed. */ int bcma_erom_seek_core_index(struct bcma_erom *erom, u_int core_index) { int error; /* Start search at top of EROM */ bcma_erom_reset(erom); /* Skip core descriptors till we hit the requested entry */ for (u_int i = 0; i < core_index; i++) { struct bcma_erom_core core; /* Read past the core descriptor */ if ((error = bcma_erom_parse_core(erom, &core))) return (error); /* Seek to the next readable core entry */ error = erom_seek_next(erom, BCMA_EROM_ENTRY_TYPE_CORE); if (error) return (error); } return (0); } /** * Read the next core descriptor from the EROM table. * * @param erom EROM read state. * @param[out] core On success, will be populated with the parsed core * descriptor data. * @retval 0 success * @retval ENOENT The end of the EROM table was reached. * @retval non-zero Reading or parsing the core descriptor failed. */ int bcma_erom_parse_core(struct bcma_erom *erom, struct bcma_erom_core *core) { uint32_t entry; int error; /* Parse CoreDescA */ if ((error = erom_read32(erom, &entry))) return (error); /* Handle EOF */ if (entry == BCMA_EROM_TABLE_EOF) return (ENOENT); if (!BCMA_EROM_ENTRY_IS(entry, CORE)) { EROM_LOG(erom, "Unexpected EROM entry 0x%x (type=%s)\n", entry, erom_entry_type_name(entry)); return (EINVAL); } core->vendor = BCMA_EROM_GET_ATTR(entry, COREA_DESIGNER); core->device = BCMA_EROM_GET_ATTR(entry, COREA_ID); /* Parse CoreDescB */ if ((error = erom_read32(erom, &entry))) return (error); if (!BCMA_EROM_ENTRY_IS(entry, CORE)) { return (EINVAL); } core->rev = BCMA_EROM_GET_ATTR(entry, COREB_REV); core->num_mport = BCMA_EROM_GET_ATTR(entry, COREB_NUM_MP); core->num_dport = BCMA_EROM_GET_ATTR(entry, COREB_NUM_DP); core->num_mwrap = BCMA_EROM_GET_ATTR(entry, COREB_NUM_WMP); core->num_swrap = BCMA_EROM_GET_ATTR(entry, COREB_NUM_WSP); return (0); } /** + * Seek to a region record associated with @p core_index. + * + * @param erom EROM read state. + * @param core_index The index of the core record to be searched. + * @param port_type The port type to search for. + * @param port_num The port number to search for. + * @param region_num The region number to search for. + * @retval 0 success + * @retval ENOENT The requested region was not found. + * @retval non-zero Reading or parsing failed. + */ +int +bcma_erom_seek_core_sport_region(struct bcma_erom *erom, u_int core_index, + bhnd_port_type port_type, u_int port_num, u_int region_num) +{ + struct bcma_erom_core core; + uint32_t entry; + uint8_t region_port, region_type; + bool found; + int error; + + if ((error = bcma_erom_seek_core_index(erom, core_index))) + return (error); + + if ((error = bcma_erom_parse_core(erom, &core))) + return (error); + + /* Skip master ports */ + for (u_long i = 0; i < core.num_mport; i++) { + if ((error = erom_skip_mport(erom))) + return (error); + } + + /* Seek to the region block for the given port type */ + found = false; + while (1) { + bhnd_port_type p_type; + uint8_t r_type; + + if ((error = bcma_erom_peek32(erom, &entry))) + return (error); + + if (!BCMA_EROM_ENTRY_IS(entry, REGION)) + return (ENOENT); + + /* Expected region type? */ + r_type = BCMA_EROM_GET_ATTR(entry, REGION_TYPE); + if ((error = erom_region_to_port_type(erom, r_type, &p_type))) + return (error); + + if (p_type == port_type) { + found = true; + break; + } + + /* Skip to next entry */ + if ((error = erom_skip_sport_region(erom))) + return (error); + } + + if (!found) + return (ENOENT); + + /* Found the appropriate port type block; now find the region records + * for the given port number */ + found = false; + for (u_int i = 0; i <= port_num; i++) { + bhnd_port_type p_type; + + if ((error = bcma_erom_peek32(erom, &entry))) + return (error); + + if (!BCMA_EROM_ENTRY_IS(entry, REGION)) + return (ENOENT); + + /* Fetch the type/port of the first region entry */ + region_type = BCMA_EROM_GET_ATTR(entry, REGION_TYPE); + region_port = BCMA_EROM_GET_ATTR(entry, REGION_PORT); + + /* Have we found the region entries for the desired port? */ + if (i == port_num) { + error = erom_region_to_port_type(erom, region_type, + &p_type); + if (error) + return (error); + + if (p_type == port_type) + found = true; + + break; + } + + /* Otherwise, seek to next block of region records */ + while (1) { + uint8_t next_type, next_port; + + if ((error = erom_skip_sport_region(erom))) + return (error); + + if ((error = bcma_erom_peek32(erom, &entry))) + return (error); + + if (!BCMA_EROM_ENTRY_IS(entry, REGION)) + return (ENOENT); + + next_type = BCMA_EROM_GET_ATTR(entry, REGION_TYPE); + next_port = BCMA_EROM_GET_ATTR(entry, REGION_PORT); + + if (next_type != region_type || + next_port != region_port) + break; + } + } + + if (!found) + return (ENOENT); + + /* Finally, search for the requested region number */ + for (u_int i = 0; i <= region_num; i++) { + uint8_t next_port, next_type; + + if ((error = bcma_erom_peek32(erom, &entry))) + return (error); + + if (!BCMA_EROM_ENTRY_IS(entry, REGION)) + return (ENOENT); + + /* Check for the end of the region block */ + next_type = BCMA_EROM_GET_ATTR(entry, REGION_TYPE); + next_port = BCMA_EROM_GET_ATTR(entry, REGION_PORT); + + if (next_type != region_type || + next_port != region_port) + break; + + if (i == region_num) + return (0); + + if ((error = erom_skip_sport_region(erom))) + return (error); + } + + /* Not found */ + return (ENOENT); +} + +/** * Read the next master port descriptor from the EROM table. * * @param erom EROM read state. * @param[out] mport On success, will be populated with the parsed * descriptor data. * @retval 0 success * @retval non-zero Reading or parsing the descriptor failed. */ int bcma_erom_parse_mport(struct bcma_erom *erom, struct bcma_erom_mport *mport) { uint32_t entry; int error; /* Parse the master port descriptor */ if ((error = erom_read32(erom, &entry))) return (error); if (!BCMA_EROM_ENTRY_IS(entry, MPORT)) return (EINVAL); mport->port_vid = BCMA_EROM_GET_ATTR(entry, MPORT_ID); mport->port_num = BCMA_EROM_GET_ATTR(entry, MPORT_NUM); return (0); } /** * Read the next slave port region descriptor from the EROM table. * * @param erom EROM read state. * @param[out] mport On success, will be populated with the parsed * descriptor data. * @retval 0 success * @retval ENOENT The end of the region descriptor table was reached. * @retval non-zero Reading or parsing the descriptor failed. */ int bcma_erom_parse_sport_region(struct bcma_erom *erom, struct bcma_erom_sport_region *region) { uint32_t entry; uint8_t size_type; int error; /* Peek at the region descriptor */ if (bcma_erom_peek32(erom, &entry)) return (EINVAL); /* A non-region entry signals the end of the region table */ if (!BCMA_EROM_ENTRY_IS(entry, REGION)) { return (ENOENT); } else { erom_skip32(erom); } region->base_addr = BCMA_EROM_GET_ATTR(entry, REGION_BASE); region->region_type = BCMA_EROM_GET_ATTR(entry, REGION_TYPE); region->region_port = BCMA_EROM_GET_ATTR(entry, REGION_PORT); size_type = BCMA_EROM_GET_ATTR(entry, REGION_SIZE); /* If region address is 64-bit, fetch the high bits. */ if (BCMA_EROM_GET_ATTR(entry, REGION_64BIT)) { if ((error = erom_read32(erom, &entry))) return (error); region->base_addr |= ((bhnd_addr_t) entry << 32); } /* Parse the region size; it's either encoded as the binary logarithm * of the number of 4K pages (i.e. log2 n), or its encoded as a * 32-bit/64-bit literal value directly following the current entry. */ if (size_type == BCMA_EROM_REGION_SIZE_OTHER) { if ((error = erom_read32(erom, &entry))) return (error); region->size = BCMA_EROM_GET_ATTR(entry, RSIZE_VAL); if (BCMA_EROM_GET_ATTR(entry, RSIZE_64BIT)) { if ((error = erom_read32(erom, &entry))) return (error); region->size |= ((bhnd_size_t) entry << 32); } } else { region->size = BCMA_EROM_REGION_SIZE_BASE << size_type; } /* Verify that addr+size does not overflow. */ if (region->size != 0 && BHND_ADDR_MAX - (region->size - 1) < region->base_addr) { EROM_LOG(erom, "%s%u: invalid address map %llx:%llx\n", erom_entry_type_name(region->region_type), region->region_port, (unsigned long long) region->base_addr, (unsigned long long) region->size); return (EINVAL); } return (0); } /** + * Convert a bcma_erom_core record to its bhnd_core_info representation. + * + * @param core EROM core record to convert. + * @param core_idx The core index of @p core. + * @param core_unit The core unit of @p core. + * @param[out] info The populated bhnd_core_info representation. + */ +void +bcma_erom_to_core_info(const struct bcma_erom_core *core, u_int core_idx, + int core_unit, struct bhnd_core_info *info) +{ + info->vendor = core->vendor; + info->device = core->device; + info->hwrev = core->rev; + info->core_idx = core_idx; + info->unit = core_unit; +} + +/** * Parse all cores descriptors from @p erom and return the array * in @p cores and the count in @p num_cores. The current EROM read position * is left unmodified. * * The memory allocated for the table should be freed using * `free(*cores, M_BHND)`. @p cores and @p num_cores are not changed * when an error is returned. * * @param erom EROM read state. * @param[out] cores the table of parsed core descriptors. * @param[out] num_cores the number of core records in @p cores. */ int bcma_erom_get_core_info(struct bcma_erom *erom, struct bhnd_core_info **cores, u_int *num_cores) { struct bhnd_core_info *buffer; bus_size_t initial_offset; u_int count; int error; buffer = NULL; initial_offset = bcma_erom_tell(erom); /* Determine the core count */ bcma_erom_reset(erom); for (count = 0, error = 0; !error; count++) { struct bcma_erom_core core; /* Seek to the first readable core entry */ error = erom_seek_next(erom, BCMA_EROM_ENTRY_TYPE_CORE); if (error == ENOENT) break; else if (error) goto cleanup; /* Read past the core descriptor */ if ((error = bcma_erom_parse_core(erom, &core))) goto cleanup; } /* Allocate our output buffer */ buffer = malloc(sizeof(struct bhnd_core_info) * count, M_BHND, M_NOWAIT); if (buffer == NULL) { error = ENOMEM; goto cleanup; } /* Parse all core descriptors */ bcma_erom_reset(erom); for (u_int i = 0; i < count; i++) { - struct bcma_erom_core core; + struct bcma_erom_core core; + int unit; /* Parse the core */ error = erom_seek_next(erom, BCMA_EROM_ENTRY_TYPE_CORE); if (error) goto cleanup; error = bcma_erom_parse_core(erom, &core); if (error) goto cleanup; - - /* Convert to a bhnd info record */ - buffer[i].vendor = core.vendor; - buffer[i].device = core.device; - buffer[i].hwrev = core.rev; - buffer[i].core_idx = i; - buffer[i].unit = 0; /* Determine the unit number */ + unit = 0; for (u_int j = 0; j < i; j++) { if (buffer[i].vendor == buffer[j].vendor && buffer[i].device == buffer[j].device) - buffer[i].unit++; + unit++; } + + /* Convert to a bhnd info record */ + bcma_erom_to_core_info(&core, i, unit, &buffer[i]); } cleanup: if (!error) { *cores = buffer; *num_cores = count; } else { if (buffer != NULL) free(buffer, M_BHND); } /* Restore the initial position */ bcma_erom_seek(erom, initial_offset); return (error); } +/** + * Map an EROM region type to its corresponding port type. + * + * @param region_type Region type value. + * @param[out] port_type On success, the corresponding port type. + */ +static int +erom_region_to_port_type(struct bcma_erom *erom, uint8_t region_type, + bhnd_port_type *port_type) +{ + switch (region_type) { + case BCMA_EROM_REGION_TYPE_DEVICE: + *port_type = BHND_PORT_DEVICE; + return (0); + case BCMA_EROM_REGION_TYPE_BRIDGE: + *port_type = BHND_PORT_BRIDGE; + return (0); + case BCMA_EROM_REGION_TYPE_MWRAP: + case BCMA_EROM_REGION_TYPE_SWRAP: + *port_type = BHND_PORT_AGENT; + return (0); + default: + EROM_LOG(erom, "unsupported region type %hhx\n", + region_type); + return (EINVAL); + } +} /** * Register all MMIO region descriptors for the given slave port. * * @param erom EROM read state. * @param corecfg Core info to be populated with the scanned port regions. * @param port_num Port index for which regions will be parsed. * @param region_type The region type to be parsed. * @param[out] offset The offset at which to perform parsing. On success, this * will be updated to point to the next EROM table entry. */ static int erom_corecfg_fill_port_regions(struct bcma_erom *erom, struct bcma_corecfg *corecfg, bcma_pid_t port_num, uint8_t region_type) { struct bcma_sport *sport; struct bcma_sport_list *sports; bus_size_t entry_offset; int error; bhnd_port_type port_type; error = 0; - + /* Determine the port type for this region type. */ - switch (region_type) { - case BCMA_EROM_REGION_TYPE_DEVICE: - port_type = BHND_PORT_DEVICE; - break; - case BCMA_EROM_REGION_TYPE_BRIDGE: - port_type = BHND_PORT_BRIDGE; - break; - case BCMA_EROM_REGION_TYPE_MWRAP: - case BCMA_EROM_REGION_TYPE_SWRAP: - port_type = BHND_PORT_AGENT; - break; - default: - EROM_LOG(erom, "unsupported region type %hhx\n", - region_type); - return (EINVAL); - } + if ((error = erom_region_to_port_type(erom, region_type, &port_type))) + return (error); /* Fetch the list to be populated */ sports = bcma_corecfg_get_port_list(corecfg, port_type); /* Allocate a new port descriptor */ sport = bcma_alloc_sport(port_num, port_type); if (sport == NULL) return (ENOMEM); /* Read all address regions defined for this port */ for (bcma_rmid_t region_num = 0;; region_num++) { struct bcma_map *map; struct bcma_erom_sport_region spr; /* No valid port definition should come anywhere near * BCMA_RMID_MAX. */ if (region_num == BCMA_RMID_MAX) { EROM_LOG(erom, "core%u %s%u: region count reached " "upper limit of %u\n", corecfg->core_info.core_idx, bhnd_port_type_name(port_type), port_num, BCMA_RMID_MAX); error = EINVAL; goto cleanup; } /* Parse the next region entry. */ entry_offset = bcma_erom_tell(erom); error = bcma_erom_parse_sport_region(erom, &spr); if (error && error != ENOENT) { EROM_LOG(erom, "core%u %s%u.%u: invalid slave port " "address region\n", corecfg->core_info.core_idx, bhnd_port_type_name(port_type), port_num, region_num); goto cleanup; } /* ENOENT signals no further region entries */ if (error == ENOENT) { /* No further entries */ error = 0; break; } /* A region or type mismatch also signals no further region * entries */ if (spr.region_port != port_num || spr.region_type != region_type) { /* We don't want to consume this entry */ bcma_erom_seek(erom, entry_offset); error = 0; goto cleanup; } /* * Create the map entry. */ map = malloc(sizeof(struct bcma_map), M_BHND, M_NOWAIT); if (map == NULL) { error = ENOMEM; goto cleanup; } map->m_region_num = region_num; map->m_base = spr.base_addr; map->m_size = spr.size; map->m_rid = -1; /* Add the region map to the port */ STAILQ_INSERT_TAIL(&sport->sp_maps, map, m_link); sport->sp_num_maps++; } cleanup: /* Append the new port descriptor on success, or deallocate the * partially parsed descriptor on failure. */ if (error == 0) { STAILQ_INSERT_TAIL(sports, sport, sp_link); } else if (sport != NULL) { bcma_free_sport(sport); } return error; } /** * Parse the next core entry from the EROM table and produce a bcma_corecfg * to be owned by the caller. * * @param erom EROM read state. * @param[out] result On success, the core's device info. The caller inherits * ownership of this allocation. * * @return If successful, returns 0. If the end of the EROM table is hit, * ENOENT will be returned. On error, returns a non-zero error value. */ int bcma_erom_parse_corecfg(struct bcma_erom *erom, struct bcma_corecfg **result) { struct bcma_corecfg *cfg; struct bcma_erom_core core; uint8_t first_region_type; bus_size_t initial_offset; u_int core_index; int core_unit; int error; cfg = NULL; initial_offset = bcma_erom_tell(erom); /* Parse the next core entry */ if ((error = bcma_erom_parse_core(erom, &core))) return (error); /* Determine the core's index and unit numbers */ bcma_erom_reset(erom); core_unit = 0; core_index = 0; for (; bcma_erom_tell(erom) != initial_offset; core_index++) { struct bcma_erom_core prev_core; /* Parse next core */ if ((error = erom_seek_next(erom, BCMA_EROM_ENTRY_TYPE_CORE))) return (error); if ((error = bcma_erom_parse_core(erom, &prev_core))) return (error); /* Is earlier unit? */ if (core.vendor == prev_core.vendor && core.device == prev_core.device) { core_unit++; } /* Seek to next core */ if ((error = erom_seek_next(erom, BCMA_EROM_ENTRY_TYPE_CORE))) return (error); } /* We already parsed the core descriptor */ if ((error = erom_skip_core(erom))) return (error); /* Allocate our corecfg */ cfg = bcma_alloc_corecfg(core_index, core_unit, core.vendor, core.device, core.rev); if (cfg == NULL) return (ENOMEM); /* These are 5-bit values in the EROM table, and should never be able * to overflow BCMA_PID_MAX. */ KASSERT(core.num_mport <= BCMA_PID_MAX, ("unsupported mport count")); KASSERT(core.num_dport <= BCMA_PID_MAX, ("unsupported dport count")); KASSERT(core.num_mwrap + core.num_swrap <= BCMA_PID_MAX, ("unsupported wport count")); if (bootverbose) { EROM_LOG(erom, "core%u: %s %s (cid=%hx, rev=%hu, unit=%d)\n", core_index, bhnd_vendor_name(core.vendor), bhnd_find_core_name(core.vendor, core.device), core.device, core.rev, core_unit); } cfg->num_master_ports = core.num_mport; cfg->num_dev_ports = 0; /* determined below */ cfg->num_bridge_ports = 0; /* determined blow */ cfg->num_wrapper_ports = core.num_mwrap + core.num_swrap; /* Parse Master Port Descriptors */ for (uint8_t i = 0; i < core.num_mport; i++) { struct bcma_mport *mport; struct bcma_erom_mport mpd; /* Parse the master port descriptor */ error = bcma_erom_parse_mport(erom, &mpd); if (error) goto failed; /* Initialize a new bus mport structure */ mport = malloc(sizeof(struct bcma_mport), M_BHND, M_NOWAIT); if (mport == NULL) { error = ENOMEM; goto failed; } mport->mp_vid = mpd.port_vid; mport->mp_num = mpd.port_num; /* Update dinfo */ STAILQ_INSERT_TAIL(&cfg->master_ports, mport, mp_link); } /* * Determine whether this is a bridge device; if so, we can * expect the first sequence of address region descriptors to * be of EROM_REGION_TYPE_BRIDGE instead of * BCMA_EROM_REGION_TYPE_DEVICE. * * It's unclear whether this is the correct mechanism by which we * should detect/handle bridge devices, but this approach matches * that of (some of) Broadcom's published drivers. */ if (core.num_dport > 0) { uint32_t entry; if ((error = bcma_erom_peek32(erom, &entry))) goto failed; if (BCMA_EROM_ENTRY_IS(entry, REGION) && BCMA_EROM_GET_ATTR(entry, REGION_TYPE) == BCMA_EROM_REGION_TYPE_BRIDGE) { first_region_type = BCMA_EROM_REGION_TYPE_BRIDGE; cfg->num_dev_ports = 0; cfg->num_bridge_ports = core.num_dport; } else { first_region_type = BCMA_EROM_REGION_TYPE_DEVICE; cfg->num_dev_ports = core.num_dport; cfg->num_bridge_ports = 0; } } /* Device/bridge port descriptors */ for (uint8_t sp_num = 0; sp_num < core.num_dport; sp_num++) { error = erom_corecfg_fill_port_regions(erom, cfg, sp_num, first_region_type); if (error) goto failed; } /* Wrapper (aka device management) descriptors (for master ports). */ for (uint8_t sp_num = 0; sp_num < core.num_mwrap; sp_num++) { error = erom_corecfg_fill_port_regions(erom, cfg, sp_num, BCMA_EROM_REGION_TYPE_MWRAP); if (error) goto failed; } /* Wrapper (aka device management) descriptors (for slave ports). */ for (uint8_t i = 0; i < core.num_swrap; i++) { /* Slave wrapper ports are not numbered distinctly from master * wrapper ports. */ /* * Broadcom DDR1/DDR2 Memory Controller * (cid=82e, rev=1, unit=0, d/mw/sw = 2/0/1 ) -> * bhnd0: erom[0xdc]: core6 agent0.0: mismatch got: 0x1 (0x2) * * ARM BP135 AMBA3 AXI to APB Bridge * (cid=135, rev=0, unit=0, d/mw/sw = 1/0/1 ) -> * bhnd0: erom[0x124]: core9 agent1.0: mismatch got: 0x0 (0x2) * * core.num_mwrap * ===> * (core.num_mwrap > 0) ? * core.num_mwrap : * ((core.vendor == BHND_MFGID_BCM) ? 1 : 0) */ uint8_t sp_num; sp_num = (core.num_mwrap > 0) ? core.num_mwrap : ((core.vendor == BHND_MFGID_BCM) ? 1 : 0) + i; error = erom_corecfg_fill_port_regions(erom, cfg, sp_num, BCMA_EROM_REGION_TYPE_SWRAP); if (error) goto failed; } *result = cfg; return (0); failed: if (cfg != NULL) bcma_free_corecfg(cfg); return error; } Index: head/sys/dev/bhnd/bcma/bcma_eromvar.h =================================================================== --- head/sys/dev/bhnd/bcma/bcma_eromvar.h (revision 304858) +++ head/sys/dev/bhnd/bcma/bcma_eromvar.h (revision 304859) @@ -1,104 +1,117 @@ /*- * Copyright (c) 2015 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. * * $FreeBSD$ */ #ifndef _BCMA_BCMA_EROMVAR_H_ #define _BCMA_BCMA_EROMVAR_H_ #include #include "bcmavar.h" /** * EROM read context. */ struct bcma_erom { - device_t dev; /**< EROM parent device */ - struct resource *r; /**< EROM table resource. */ - bus_size_t start; /**< EROM table offset */ - bus_size_t offset; /**< current read offset */ + device_t dev; /**< EROM parent device */ + bus_space_tag_t bst; /**< EROM table bus space */ + bus_space_handle_t bsh; /**< EROM table bus handle */ + bus_size_t start; /**< EROM table offset */ + bus_size_t offset; /**< current read offset */ }; /** EROM core descriptor. */ struct bcma_erom_core { uint16_t vendor; /**< core's designer */ uint16_t device; /**< core's device identifier */ uint16_t rev; /**< core's hardware revision */ u_long num_mport; /**< number of master port descriptors */ u_long num_dport; /**< number of slave port descriptors */ u_long num_mwrap; /**< number of master wrapper slave port descriptors */ u_long num_swrap; /**< number of slave wrapper slave port descriptors */ }; /** EROM master port descriptor. */ struct bcma_erom_mport { uint8_t port_num; /**< the port number (bus-unique) */ uint8_t port_vid; /**< the port VID. A single physical master port may have multiple VIDs; the canonical port address is composed of the port number + the port VID */ }; /** EROM slave port region descriptor. */ struct bcma_erom_sport_region { uint8_t region_port; /**< the slave port mapping this region */ uint8_t region_type; /**< the mapping port's type */ bhnd_addr_t base_addr; /**< region base address */ bhnd_addr_t size; /**< region size */ }; int bcma_erom_open(struct bcma_erom *erom, struct resource *r, bus_size_t offset); +int bhnd_erom_bus_space_open(struct bcma_erom *erom, device_t owner, + bus_space_tag_t bst, bus_space_handle_t bsh, + bus_size_t offset); + int bcma_erom_peek32(struct bcma_erom *erom, uint32_t *entry); bus_size_t bcma_erom_tell(struct bcma_erom *erom); void bcma_erom_seek(struct bcma_erom *erom, bus_size_t offset); void bcma_erom_reset(struct bcma_erom *erom); +int bcma_erom_seek_next_core(struct bcma_erom *erom); int bcma_erom_seek_core_index(struct bcma_erom *erom, u_int core_index); int bcma_erom_parse_core(struct bcma_erom *erom, struct bcma_erom_core *core); +int bcma_erom_seek_core_sport_region(struct bcma_erom *erom, + u_int core_index, bhnd_port_type port_type, u_int port_num, + u_int region_num); + int bcma_erom_parse_mport(struct bcma_erom *erom, struct bcma_erom_mport *mport); int bcma_erom_parse_sport_region(struct bcma_erom *erom, struct bcma_erom_sport_region *region); + +void bcma_erom_to_core_info(const struct bcma_erom_core *core, + u_int core_idx, int core_unit, struct bhnd_core_info *info); int bcma_erom_get_core_info(struct bcma_erom *erom, struct bhnd_core_info **cores, u_int *num_cores); int bcma_erom_parse_corecfg(struct bcma_erom *erom, struct bcma_corecfg **result); #endif /* _BCMA_BCMA_EROMVAR_H_ */ Index: head/sys/dev/bhnd/bhnd_ids.h =================================================================== --- head/sys/dev/bhnd/bhnd_ids.h (revision 304858) +++ head/sys/dev/bhnd/bhnd_ids.h (revision 304859) @@ -1,1127 +1,1133 @@ /*- * Copyright (c) 2015-2016 Landon Fuller * Copyright (c) 1999-2015, Broadcom Corporation * * This file is derived from the bcmdevs.h header contributed by Broadcom * to Android's bcmdhd driver module, later revisions of bcmdevs.h distributed * with the dd-wrt project, and the hndsoc.h header distributed with Broadcom's * initial brcm80211 Linux driver release as contributed to the Linux staging * repository. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ #ifndef _BHND_BHND_IDS_H_ #define _BHND_BHND_IDS_H_ /* * JEDEC JEP-106 Core Vendor IDs * * These are the JEDEC JEP-106 manufacturer ID representions (with ARM's * non-standard 4-bit continutation code), as used in ARM's PrimeCell * identification registers, bcma(4) EROM core descriptors, etc. * * @note * Bus implementations that predate the adoption of ARM IP * will need to convert bus-specific vendor IDs to their BHND_MFGID * JEP-106 equivalents. * * @par ARM 4-bit Continuation Code * * BHND MFGIDs are encoded using ARM's non-standard 4-bit continuation code * format: * * @code{.unparsed} * [11:8 ][7:0 ] * [cont code][mfg id] * @endcode * * The 4-bit continuation code field specifies the number of JEP-106 * continuation codes that prefix the manufacturer's ID code. In the case of * ARM's JEP-106 ID of `0x7F 0x7F 0x7F 0x7F 0x3B`, the four 0x7F continuations * are encoded as '4' in the 4-bit continuation code field (i.e. 0x43B). */ #define BHND_MFGID_ARM 0x043b /**< arm JEP-106 vendor id */ #define BHND_MFGID_BCM 0x04bf /**< broadcom JEP-106 vendor id */ #define BHND_MFGID_MIPS 0x04a7 /**< mips JEP-106 vendor id */ #define BHND_MFGID_INVALID 0x0000 /**< invalid JEP-106 vendor id */ /* * OCP (Open Core Protocol) Vendor IDs. * * OCP-IP assigned vendor codes are used by siba(4) */ #define OCP_VENDOR_BCM 0x4243 /**< Broadcom OCP vendor id */ /* PCI vendor IDs */ #define PCI_VENDOR_EPIGRAM 0xfeda #define PCI_VENDOR_BROADCOM 0x14e4 #define PCI_VENDOR_3COM 0x10b7 #define PCI_VENDOR_NETGEAR 0x1385 #define PCI_VENDOR_DIAMOND 0x1092 #define PCI_VENDOR_INTEL 0x8086 #define PCI_VENDOR_DELL 0x1028 #define PCI_VENDOR_HP 0x103c #define PCI_VENDOR_HP_COMPAQ 0x0e11 #define PCI_VENDOR_APPLE 0x106b #define PCI_VENDOR_SI_IMAGE 0x1095 /* Silicon Image, used by Arasan SDIO Host */ #define PCI_VENDOR_BUFFALO 0x1154 /* Buffalo vendor id */ #define PCI_VENDOR_TI 0x104c /* Texas Instruments */ #define PCI_VENDOR_RICOH 0x1180 /* Ricoh */ #define PCI_VENDOR_JMICRON 0x197b /* PCMCIA vendor IDs */ #define PCMCIA_VENDOR_BROADCOM 0x02d0 /* SDIO vendor IDs */ #define SDIO_VENDOR_BROADCOM 0x00BF /* USB dongle VID/PIDs */ #define USB_VID_BROADCOM 0x0a5c #define USB_PID_BCM4328 0xbd12 #define USB_PID_BCM4322 0xbd13 #define USB_PID_BCM4319 0xbd16 #define USB_PID_BCM43236 0xbd17 #define USB_PID_BCM4332 0xbd18 #define USB_PID_BCM4330 0xbd19 #define USB_PID_BCM4334 0xbd1a #define USB_PID_BCM43239 0xbd1b #define USB_PID_BCM4324 0xbd1c #define USB_PID_BCM4360 0xbd1d #define USB_PID_BCM43143 0xbd1e #define USB_PID_BCM43242 0xbd1f #define USB_PID_BCM43342 0xbd21 #define USB_PID_BCM4335 0xbd20 #define USB_PID_BCM4350 0xbd23 #define USB_PID_BCM43341 0xbd22 #define USB_PID_BCM_DNGL_BDC 0x0bdc /* BDC USB device controller IP? */ #define USB_PID_BCM_DNGL_JTAG 0x4a44 /* HW USB BLOCK [CPULESS USB] PIDs */ #define USB_PID_CCM_HWUSB_43239 43239 /* PCI Device IDs */ #define PCI_DEVID_BCM4210 0x1072 /* never used */ #define PCI_DEVID_BCM4230 0x1086 /* never used */ #define PCI_DEVID_BCM4401_ENET 0x170c /* 4401b0 production enet cards */ #define PCI_DEVID_BCM3352 0x3352 /* bcm3352 device id */ #define PCI_DEVID_BCM3360 0x3360 /* bcm3360 device id */ #define PCI_DEVID_BCM4211 0x4211 #define PCI_DEVID_BCM4231 0x4231 #define PCI_DEVID_BCM4301 0x4301 /* 4031 802.11b */ #define PCI_DEVID_BCM4303_D11B 0x4303 /* 4303 802.11b */ #define PCI_DEVID_BCM4306 0x4306 /* 4306 802.11b/g */ #define PCI_DEVID_BCM4307 0x4307 /* 4307 802.11b, 10/100 ethernet, V.92 modem */ #define PCI_DEVID_BCM4311_D11G 0x4311 /* 4311 802.11b/g id */ #define PCI_DEVID_BCM4311_D11DUAL 0x4312 /* 4311 802.11a/b/g id */ #define PCI_DEVID_BCM4311_D11A 0x4313 /* 4311 802.11a id */ #define PCI_DEVID_BCM4328_D11DUAL 0x4314 /* 4328/4312 802.11a/g id */ #define PCI_DEVID_BCM4328_D11G 0x4315 /* 4328/4312 802.11g id */ #define PCI_DEVID_BCM4328_D11A 0x4316 /* 4328/4312 802.11a id */ #define PCI_DEVID_BCM4318_D11G 0x4318 /* 4318 802.11b/g id */ #define PCI_DEVID_BCM4318_D11DUAL 0x4319 /* 4318 802.11a/b/g id */ #define PCI_DEVID_BCM4318_D11A 0x431a /* 4318 802.11a id */ #define PCI_DEVID_BCM4325_D11DUAL 0x431b /* 4325 802.11a/g id */ #define PCI_DEVID_BCM4325_D11G 0x431c /* 4325 802.11g id */ #define PCI_DEVID_BCM4325_D11A 0x431d /* 4325 802.11a id */ #define PCI_DEVID_BCM4306_D11G 0x4320 /* 4306 802.11g */ #define PCI_DEVID_BCM4306_D11A 0x4321 /* 4306 802.11a */ #define PCI_DEVID_BCM4306_UART 0x4322 /* 4306 uart */ #define PCI_DEVID_BCM4306_V90 0x4323 /* 4306 v90 codec */ #define PCI_DEVID_BCM4306_D11DUAL 0x4324 /* 4306 dual A+B */ #define PCI_DEVID_BCM4306_D11G_ID2 0x4325 /* BCM4306_D11G; INF w/loose binding war */ #define PCI_DEVID_BCM4321_D11N 0x4328 /* 4321 802.11n dualband id */ #define PCI_DEVID_BCM4321_D11N2G 0x4329 /* 4321 802.11n 2.4Ghz band id */ #define PCI_DEVID_BCM4321_D11N5G 0x432a /* 4321 802.11n 5Ghz band id */ #define PCI_DEVID_BCM4322_D11N 0x432b /* 4322 802.11n dualband device */ #define PCI_DEVID_BCM4322_D11N2G 0x432c /* 4322 802.11n 2.4GHz device */ #define PCI_DEVID_BCM4322_D11N5G 0x432d /* 4322 802.11n 5GHz device */ #define PCI_DEVID_BCM4329_D11N 0x432e /* 4329 802.11n dualband device */ #define PCI_DEVID_BCM4329_D11N2G 0x432f /* 4329 802.11n 2.4G device */ #define PCI_DEVID_BCM4329_D11N5G 0x4330 /* 4329 802.11n 5G device */ #define PCI_DEVID_BCM4315_D11DUAL 0x4334 /* 4315 802.11a/g id */ #define PCI_DEVID_BCM4315_D11G 0x4335 /* 4315 802.11g id */ #define PCI_DEVID_BCM4315_D11A 0x4336 /* 4315 802.11a id */ #define PCI_DEVID_BCM4319_D11N 0x4337 /* 4319 802.11n dualband device */ #define PCI_DEVID_BCM4319_D11N2G 0x4338 /* 4319 802.11n 2.4G device */ #define PCI_DEVID_BCM4319_D11N5G 0x4339 /* 4319 802.11n 5G device */ #define PCI_DEVID_BCM43231_D11N2G 0x4340 /* 43231 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43221_D11N2G 0x4341 /* 43221 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43222_D11N 0x4350 /* 43222 802.11n dualband device */ #define PCI_DEVID_BCM43222_D11N2G 0x4351 /* 43222 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43222_D11N5G 0x4352 /* 43222 802.11n 5GHz device */ #define PCI_DEVID_BCM43224_D11N 0x4353 /* 43224 802.11n dualband device */ #define PCI_DEVID_BCM43224_D11N_ID_VEN1 0x0576 /* Vendor specific 43224 802.11n db device */ #define PCI_DEVID_BCM43226_D11N 0x4354 /* 43226 802.11n dualband device */ #define PCI_DEVID_BCM43236_D11N 0x4346 /* 43236 802.11n dualband device */ #define PCI_DEVID_BCM43236_D11N2G 0x4347 /* 43236 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43236_D11N5G 0x4348 /* 43236 802.11n 5GHz device */ #define PCI_DEVID_BCM43225_D11N2G 0x4357 /* 43225 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43421_D11N 0xA99D /* 43421 802.11n dualband device */ #define PCI_DEVID_BCM4313_D11N2G 0x4727 /* 4313 802.11n 2.4G device */ #define PCI_DEVID_BCM4330_D11N 0x4360 /* 4330 802.11n dualband device */ #define PCI_DEVID_BCM4330_D11N2G 0x4361 /* 4330 802.11n 2.4G device */ #define PCI_DEVID_BCM4330_D11N5G 0x4362 /* 4330 802.11n 5G device */ #define PCI_DEVID_BCM4336_D11N 0x4343 /* 4336 802.11n 2.4GHz device */ #define PCI_DEVID_BCM6362_D11N 0x435f /* 6362 802.11n dualband device */ #define PCI_DEVID_BCM6362_D11N2G 0x433f /* 6362 802.11n 2.4Ghz band id */ #define PCI_DEVID_BCM6362_D11N5G 0x434f /* 6362 802.11n 5Ghz band id */ #define PCI_DEVID_BCM4331_D11N 0x4331 /* 4331 802.11n dualband id */ #define PCI_DEVID_BCM4331_D11N2G 0x4332 /* 4331 802.11n 2.4Ghz band id */ #define PCI_DEVID_BCM4331_D11N5G 0x4333 /* 4331 802.11n 5Ghz band id */ #define PCI_DEVID_BCM43237_D11N 0x4355 /* 43237 802.11n dualband device */ #define PCI_DEVID_BCM43237_D11N5G 0x4356 /* 43237 802.11n 5GHz device */ #define PCI_DEVID_BCM43227_D11N2G 0x4358 /* 43228 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43228_D11N 0x4359 /* 43228 802.11n DualBand device */ #define PCI_DEVID_BCM43228_D11N5G 0x435a /* 43228 802.11n 5GHz device */ #define PCI_DEVID_BCM43362_D11N 0x4363 /* 43362 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43239_D11N 0x4370 /* 43239 802.11n dualband device */ #define PCI_DEVID_BCM4324_D11N 0x4374 /* 4324 802.11n dualband device */ #define PCI_DEVID_BCM43217_D11N2G 0x43a9 /* 43217 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43131_D11N2G 0x43aa /* 43131 802.11n 2.4GHz device */ #define PCI_DEVID_BCM4314_D11N2G 0x4364 /* 4314 802.11n 2.4G device */ #define PCI_DEVID_BCM43142_D11N2G 0x4365 /* 43142 802.11n 2.4G device */ #define PCI_DEVID_BCM43143_D11N2G 0x4366 /* 43143 802.11n 2.4G device */ #define PCI_DEVID_BCM4334_D11N 0x4380 /* 4334 802.11n dualband device */ #define PCI_DEVID_BCM4334_D11N2G 0x4381 /* 4334 802.11n 2.4G device */ #define PCI_DEVID_BCM4334_D11N5G 0x4382 /* 4334 802.11n 5G device */ #define PCI_DEVID_BCM43342_D11N 0x4383 /* 43342 802.11n dualband device */ #define PCI_DEVID_BCM43342_D11N2G 0x4384 /* 43342 802.11n 2.4G device */ #define PCI_DEVID_BCM43342_D11N5G 0x4385 /* 43342 802.11n 5G device */ #define PCI_DEVID_BCM43341_D11N 0x4386 /* 43341 802.11n dualband device */ #define PCI_DEVID_BCM43341_D11N2G 0x4387 /* 43341 802.11n 2.4G device */ #define PCI_DEVID_BCM43341_D11N5G 0x4388 /* 43341 802.11n 5G device */ #define PCI_DEVID_BCM4360_D11AC 0x43a0 #define PCI_DEVID_BCM4360_D11AC2G 0x43a1 #define PCI_DEVID_BCM4360_D11AC5G 0x43a2 #define PCI_DEVID_BCM4335_D11AC 0x43ae #define PCI_DEVID_BCM4335_D11AC2G 0x43af #define PCI_DEVID_BCM4335_D11AC5G 0x43b0 #define PCI_DEVID_BCM4352_D11AC 0x43b1 /* 4352 802.11ac dualband device */ #define PCI_DEVID_BCM4352_D11AC2G 0x43b2 /* 4352 802.11ac 2.4G device */ #define PCI_DEVID_BCM4352_D11AC5G 0x43b3 /* 4352 802.11ac 5G device */ #define PCI_DEVID_PCIXX21_FLASHMEDIA0 0x8033 /* TI PCI xx21 Standard Host Controller */ #define PCI_DEVID_PCIXX21_SDIOH0 0x8034 /* TI PCI xx21 Standard Host Controller */ /* PCI Subsystem Vendor IDs */ #define PCI_SUBVENDOR_BCM943228HMB 0x0607 #define PCI_SUBVENDOR_BCM94313HMGBL 0x0608 #define PCI_SUBVENDOR_BCM94313HMG 0x0609 #define PCI_SUBVENDOR_BCM943142HM 0x0611 /* PCI Subsystem Device IDs */ #define PCI_SUBDEVID_BCM43143_D11N2G 0x4366 /* 43143 802.11n 2.4G device */ #define PCI_SUBDEVID_BCM43242_D11N 0x4367 /* 43242 802.11n dualband device */ #define PCI_SUBDEVID_BCM43242_D11N2G 0x4368 /* 43242 802.11n 2.4G device */ #define PCI_SUBDEVID_BCM43242_D11N5G 0x4369 /* 43242 802.11n 5G device */ #define PCI_SUBDEVID_BCM4350_D11AC 0x43a3 #define PCI_SUBDEVID_BCM4350_D11AC2G 0x43a4 #define PCI_SUBDEVID_BCM4350_D11AC5G 0x43a5 #define PCI_SUBDEVID_BCMGPRS_UART 0x4333 /* Uart id used by 4306/gprs card */ #define PCI_SUBDEVID_BCMGPRS2_UART 0x4344 /* Uart id used by 4306/gprs card */ #define PCI_SUBDEVID_BCM_FPGA_JTAGM 0x43f0 /* FPGA jtagm device id */ #define PCI_SUBDEVID_BCM_JTAGM 0x43f1 /* BCM jtagm device id */ #define PCI_SUBDEVID_BCM_SDIOH_FPGA 0x43f2 /* sdio host fpga */ #define PCI_SUBDEVID_BCM_SDIOH 0x43f3 /* BCM sdio host id */ #define PCI_SUBDEVID_BCM_SDIOD_FPGA 0x43f4 /* sdio device fpga */ #define PCI_SUBDEVID_BCM_SPIH_FPGA 0x43f5 /* PCI SPI Host Controller FPGA */ #define PCI_SUBDEVID_BCM_SPIH 0x43f6 /* Synopsis SPI Host Controller */ #define PCI_SUBDEVID_BCM_MIMO_FPGA 0x43f8 /* FPGA mimo minimacphy device id */ #define PCI_SUBDEVID_BCM_JTAGM2 0x43f9 /* PCI_SUBDEVID_BCM alternate jtagm device id */ #define PCI_SUBDEVID_BCM_SDHCI_FPGA 0x43fa /* Standard SDIO Host Controller FPGA */ #define PCI_SUBDEVID_BCM4402_ENET 0x4402 /* 4402 enet */ #define PCI_SUBDEVID_BCM4402_V90 0x4403 /* 4402 v90 codec */ #define PCI_SUBDEVID_BCM4410 0x4410 /* bcm44xx family pci iline */ #define PCI_SUBDEVID_BCM4412 0x4412 /* bcm44xx family pci enet */ #define PCI_SUBDEVID_BCM4430 0x4430 /* bcm44xx family cardbus iline */ #define PCI_SUBDEVID_BCM4432 0x4432 /* bcm44xx family cardbus enet */ #define PCI_SUBDEVID_BCM4704_ENET 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */ #define PCI_SUBDEVID_BCM4710 0x4710 /* 4710 primary function 0 */ #define PCI_SUBDEVID_BCM47XX_AUDIO 0x4711 /* 47xx audio codec */ #define PCI_SUBDEVID_BCM47XX_V90 0x4712 /* 47xx v90 codec */ #define PCI_SUBDEVID_BCM47XX_ENET 0x4713 /* 47xx enet */ #define PCI_SUBDEVID_BCM47XX_EXT 0x4714 /* 47xx external i/f */ #define PCI_SUBDEVID_BCM47XX_GMAC 0x4715 /* 47xx Unimac based GbE */ #define PCI_SUBDEVID_BCM47XX_USBH 0x4716 /* 47xx usb host */ #define PCI_SUBDEVID_BCM47XX_USBD 0x4717 /* 47xx usb device */ #define PCI_SUBDEVID_BCM47XX_IPSEC 0x4718 /* 47xx ipsec */ #define PCI_SUBDEVID_BCM47XX_ROBO 0x4719 /* 47xx/53xx roboswitch core */ #define PCI_SUBDEVID_BCM47XX_USB20H 0x471a /* 47xx usb 2.0 host */ #define PCI_SUBDEVID_BCM47XX_USB20D 0x471b /* 47xx usb 2.0 device */ #define PCI_SUBDEVID_BCM47XX_ATA100 0x471d /* 47xx parallel ATA */ #define PCI_SUBDEVID_BCM47XX_SATAXOR 0x471e /* 47xx serial ATA & XOR DMA */ #define PCI_SUBDEVID_BCM47XX_GIGETH 0x471f /* 47xx GbE (5700) */ #define PCI_SUBDEVID_BCM4712_MIPS 0x4720 /* 4712 base devid */ #define PCI_SUBDEVID_BCM4716 0x4722 /* 4716 base devid */ #define PCI_SUBDEVID_BCM47XX_USB30H 0x472a /* 47xx usb 3.0 host */ #define PCI_SUBDEVID_BCM47XX_USB30D 0x472b /* 47xx usb 3.0 device */ #define PCI_SUBDEVID_BCM47XX_SMBUS_EMU 0x47fe /* 47xx emulated SMBus device */ #define PCI_SUBDEVID_BCM47XX_XOR_EMU 0x47ff /* 47xx emulated XOR engine */ #define PCI_SUBDEVID_BCM_EPI41210 0xa0fa /* bcm4210 */ #define PCI_SUBDEVID_BCM_EPI41230 0xa10e /* bcm4230 */ #define PCI_SUBDEVID_BCM_JINVANI_SDIOH 0x4743 /* Jinvani SDIO Gold Host */ #define PCI_SUBDEVID_BCM27XX_SDIOH 0x2702 /* PCI_SUBDEVID_BCM27xx Standard SDIO Host */ #define PCI_SUBDEVID_BCM_PCIXX21_FLASHMEDIA 0x803b /* TI PCI xx21 Standard Host Controller */ #define PCI_SUBDEVID_BCM_PCIXX21_SDIOH 0x803c /* TI PCI xx21 Standard Host Controller */ #define PCI_SUBDEVID_BCM_R5C822_SDIOH 0x0822 /* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host */ #define PCI_SUBDEVID_BCM_JMICRON_SDIOH 0x2381 /* JMicron Standard SDIO Host Controller */ /* Broadcom ChipCommon Chip IDs */ #define BHND_CHIPID_BCM4306 0x4306 /* 4306 chipcommon chipid */ #define BHND_CHIPID_BCM4311 0x4311 /* 4311 PCIe 802.11a/b/g */ #define BHND_CHIPID_BCM43111 43111 /* 43111 chipcommon chipid (OTP chipid) */ #define BHND_CHIPID_BCM43112 43112 /* 43112 chipcommon chipid (OTP chipid) */ #define BHND_CHIPID_BCM4312 0x4312 /* 4312 chipcommon chipid */ #define BHND_CHIPID_BCM4313 0x4313 /* 4313 chip id */ #define BHND_CHIPID_BCM43131 43131 /* 43131 chip id (OTP chipid) */ #define BHND_CHIPID_BCM4315 0x4315 /* 4315 chip id */ #define BHND_CHIPID_BCM4318 0x4318 /* 4318 chipcommon chipid */ #define BHND_CHIPID_BCM4319 0x4319 /* 4319 chip id */ #define BHND_CHIPID_BCM4320 0x4320 /* 4320 chipcommon chipid */ #define BHND_CHIPID_BCM4321 0x4321 /* 4321 chipcommon chipid */ #define BHND_CHIPID_BCM43217 43217 /* 43217 chip id (OTP chipid) */ #define BHND_CHIPID_BCM4322 0x4322 /* 4322 chipcommon chipid */ #define BHND_CHIPID_BCM43221 43221 /* 43221 chipcommon chipid (OTP chipid) */ #define BHND_CHIPID_BCM43222 43222 /* 43222 chipcommon chipid */ #define BHND_CHIPID_BCM43224 43224 /* 43224 chipcommon chipid */ #define BHND_CHIPID_BCM43225 43225 /* 43225 chipcommon chipid */ #define BHND_CHIPID_BCM43227 43227 /* 43227 chipcommon chipid */ #define BHND_CHIPID_BCM43228 43228 /* 43228 chipcommon chipid */ #define BHND_CHIPID_BCM43226 43226 /* 43226 chipcommon chipid */ #define BHND_CHIPID_BCM43231 43231 /* 43231 chipcommon chipid (OTP chipid) */ #define BHND_CHIPID_BCM43234 43234 /* 43234 chipcommon chipid */ #define BHND_CHIPID_BCM43235 43235 /* 43235 chipcommon chipid */ #define BHND_CHIPID_BCM43236 43236 /* 43236 chipcommon chipid */ #define BHND_CHIPID_BCM43237 43237 /* 43237 chipcommon chipid */ #define BHND_CHIPID_BCM43238 43238 /* 43238 chipcommon chipid */ #define BHND_CHIPID_BCM43239 43239 /* 43239 chipcommon chipid */ #define BHND_CHIPID_BCM43420 43420 /* 43222 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM43421 43421 /* 43224 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM43428 43428 /* 43228 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM43431 43431 /* 4331 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM43460 43460 /* 4360 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM43462 0xA9C6 /* 43462 chipcommon chipid */ #define BHND_CHIPID_BCM4325 0x4325 /* 4325 chip id */ #define BHND_CHIPID_BCM4328 0x4328 /* 4328 chip id */ #define BHND_CHIPID_BCM4329 0x4329 /* 4329 chipcommon chipid */ #define BHND_CHIPID_BCM4331 0x4331 /* 4331 chipcommon chipid */ #define BHND_CHIPID_BCM4336 0x4336 /* 4336 chipcommon chipid */ #define BHND_CHIPID_BCM43362 43362 /* 43362 chipcommon chipid */ #define BHND_CHIPID_BCM4330 0x4330 /* 4330 chipcommon chipid */ #define BHND_CHIPID_BCM6362 0x6362 /* 6362 chipcommon chipid */ #define BHND_CHIPID_BCM4314 0x4314 /* 4314 chipcommon chipid */ #define BHND_CHIPID_BCM43142 43142 /* 43142 chipcommon chipid */ #define BHND_CHIPID_BCM43143 43143 /* 43143 chipcommon chipid */ #define BHND_CHIPID_BCM4324 0x4324 /* 4324 chipcommon chipid */ #define BHND_CHIPID_BCM43242 43242 /* 43242 chipcommon chipid */ #define BHND_CHIPID_BCM43243 43243 /* 43243 chipcommon chipid */ #define BHND_CHIPID_BCM4334 0x4334 /* 4334 chipcommon chipid */ #define BHND_CHIPID_BCM4335 0x4335 /* 4335 chipcommon chipid */ #define BHND_CHIPID_BCM4360 0x4360 /* 4360 chipcommon chipid */ #define BHND_CHIPID_BCM43602 0xaa52 /* 43602 chipcommon chipid */ #define BHND_CHIPID_BCM4352 0x4352 /* 4352 chipcommon chipid */ #define BHND_CHIPID_BCM43526 0xAA06 #define BHND_CHIPID_BCM43341 43341 /* 43341 chipcommon chipid */ #define BHND_CHIPID_BCM43342 43342 /* 43342 chipcommon chipid */ #define BHND_CHIPID_BCM4335 0x4335 #define BHND_CHIPID_BCM4350 0x4350 /* 4350 chipcommon chipid */ #define BHND_CHIPID_BCM4342 4342 /* 4342 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM4402 0x4402 /* 4402 chipid */ #define BHND_CHIPID_BCM4704 0x4704 /* 4704 chipcommon chipid */ #define BHND_CHIPID_BCM4706 0x5300 /* 4706 chipcommon chipid */ #define BHND_CHIPID_BCM4707 53010 /* 4707 chipcommon chipid */ #define BHND_CHIPID_BCM53018 53018 /* 53018 chipcommon chipid */ #define BHND_CHIPID_IS_BCM4707(chipid) \ (((chipid) == BHND_CHIPID_BCM4707) || \ ((chipid) == BHND_CHIPID_BCM53018)) #define BHND_CHIPID_BCM4710 0x4710 /* 4710 chipid */ #define BHND_CHIPID_BCM4712 0x4712 /* 4712 chipcommon chipid */ #define BHND_CHIPID_BCM4716 0x4716 /* 4716 chipcommon chipid */ #define BHND_CHIPID_BCM47162 47162 /* 47162 chipcommon chipid */ #define BHND_CHIPID_BCM4748 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM4749 0x4749 /* 5357 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM4785 0x4785 /* 4785 chipcommon chipid */ #define BHND_CHIPID_BCM5350 0x5350 /* 5350 chipcommon chipid */ #define BHND_CHIPID_BCM5352 0x5352 /* 5352 chipcommon chipid */ #define BHND_CHIPID_BCM5354 0x5354 /* 5354 chipcommon chipid */ #define BHND_CHIPID_BCM5365 0x5365 /* 5365 chipcommon chipid */ #define BHND_CHIPID_BCM5356 0x5356 /* 5356 chipcommon chipid */ #define BHND_CHIPID_BCM5357 0x5357 /* 5357 chipcommon chipid */ #define BHND_CHIPID_BCM53572 53572 /* 53572 chipcommon chipid */ /* Broadcom ChipCommon Package IDs */ #define BHND_PKGID_BCM4303 2 /* 4303 package id */ #define BHND_PKGID_BCM4309 1 /* 4309 package id */ #define BHND_PKGID_BCM4712LARGE 0 /* 340pin 4712 package id */ #define BHND_PKGID_BCM4712SMALL 1 /* 200pin 4712 package id */ #define BHND_PKGID_BCM4712MID 2 /* 225pin 4712 package id */ #define BHND_PKGID_BCM4328USBD11G 2 /* 4328 802.11g USB package id */ #define BHND_PKGID_BCM4328USBDUAL 3 /* 4328 802.11a/g USB package id */ #define BHND_PKGID_BCM4328SDIOD11G 4 /* 4328 802.11g SDIO package id */ #define BHND_PKGID_BCM4328SDIODUAL 5 /* 4328 802.11a/g SDIO package id */ #define BHND_PKGID_BCM4329_289PIN 0 /* 4329 289-pin package id */ #define BHND_PKGID_BCM4329_182PIN 1 /* 4329N 182-pin package id */ #define BHND_PKGID_BCM5354E 1 /* 5354E package id */ #define BHND_PKGID_BCM4716 8 /* 4716 package id */ #define BHND_PKGID_BCM4717 9 /* 4717 package id */ #define BHND_PKGID_BCM4718 10 /* 4718 package id */ #define BHND_PKGID_BCM5356_NONMODE 1 /* 5356 package without nmode suppport */ #define BHND_PKGID_BCM5358U 8 /* 5358U package id */ #define BHND_PKGID_BCM5358 9 /* 5358 package id */ #define BHND_PKGID_BCM47186 10 /* 47186 package id */ #define BHND_PKGID_BCM5357 11 /* 5357 package id */ #define BHND_PKGID_BCM5356U 12 /* 5356U package id */ #define BHND_PKGID_BCM53572 8 /* 53572 package id */ #define BHND_PKGID_BCM5357C0 8 /* 5357c0 package id (the same as 53572) */ #define BHND_PKGID_BCM47188 9 /* 47188 package id */ #define BHND_PKGID_BCM5358C0 0xa /* 5358c0 package id */ #define BHND_PKGID_BCM5356C0 0xb /* 5356c0 package id */ #define BHND_PKGID_BCM4331TT 8 /* 4331 12x12 package id */ #define BHND_PKGID_BCM4331TN 9 /* 4331 12x9 package id */ #define BHND_PKGID_BCM4331TNA0 0xb /* 4331 12x9 package id */ #define BHND_PKGID_BCM4706L 1 /* 4706L package id */ #define BHND_PKGID_HDLSIM5350 1 /* HDL simulator package id for a 5350 */ #define BHND_PKGID_HDLSIM 14 /* HDL simulator package id */ #define BHND_PKGID_HWSIM 15 /* Hardware simulator package id */ #define BHND_PKGID_BCM43224_FAB_CSM 0x8 /* the chip is manufactured by CSM */ #define BHND_PKGID_BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */ #define BHND_PKGID_BCM4336_WLBGA 0x8 #define BHND_PKGID_BCM4330_WLBGA 0x0 #define BHND_PKGID_BCM4314PCIE_ARM (8 | 0) /* 4314 QFN PCI package id, bit 3 tie high */ #define BHND_PKGID_BCM4314SDIO (8 | 1) /* 4314 QFN SDIO package id */ #define BHND_PKGID_BCM4314PCIE (8 | 2) /* 4314 QFN PCI (ARM-less) package id */ #define BHND_PKGID_BCM4314SDIO_ARM (8 | 3) /* 4314 QFN SDIO (ARM-less) package id */ #define BHND_PKGID_BCM4314SDIO_FPBGA (8 | 4) /* 4314 FpBGA SDIO package id */ #define BHND_PKGID_BCM4314DEV (8 | 6) /* 4314 Development package id */ #define BHND_PKGID_BCM4707 1 /* 4707 package id */ #define BHND_PKGID_BCM4708 2 /* 4708 package id */ #define BHND_PKGID_BCM4709 0 /* 4709 package id */ #define BHND_PKGID_BCM4335_WLCSP (0x0) /* WLCSP Module/Mobile SDIO/HSIC. */ #define BHND_PKGID_BCM4335_FCBGA (0x1) /* FCBGA PC/Embedded/Media PCIE/SDIO */ #define BHND_PKGID_BCM4335_WLBGA (0x2) /* WLBGA COB/Mobile SDIO/HSIC. */ #define BHND_PKGID_BCM4335_FCBGAD (0x3) /* FCBGA Debug Debug/Dev All if's. */ #define BHND_PKGID_PKG_MASK_BCM4335 (0x3) /* Broadcom Core IDs */ #define BHND_COREID_INVALID 0x700 /* Invalid coreid */ #define BHND_COREID_CC 0x800 /* chipcommon core */ #define BHND_COREID_ILINE20 0x801 /* iline20 core */ #define BHND_COREID_SRAM 0x802 /* sram core */ #define BHND_COREID_SDRAM 0x803 /* sdram core */ #define BHND_COREID_PCI 0x804 /* pci core */ #define BHND_COREID_MIPS 0x805 /* mips core */ #define BHND_COREID_ENET 0x806 /* enet mac core */ #define BHND_COREID_CODEC 0x807 /* v90 codec core */ #define BHND_COREID_USB 0x808 /* usb 1.1 host/device core */ #define BHND_COREID_ADSL 0x809 /* ADSL core */ #define BHND_COREID_ILINE100 0x80a /* iline100 core */ #define BHND_COREID_IPSEC 0x80b /* ipsec core */ #define BHND_COREID_UTOPIA 0x80c /* utopia core */ #define BHND_COREID_PCMCIA 0x80d /* pcmcia core */ #define BHND_COREID_SOCRAM 0x80e /* internal memory core */ #define BHND_COREID_MEMC 0x80f /* memc sdram core */ #define BHND_COREID_OFDM 0x810 /* OFDM phy core */ #define BHND_COREID_EXTIF 0x811 /* external interface core */ #define BHND_COREID_D11 0x812 /* 802.11 MAC core */ #define BHND_COREID_APHY 0x813 /* 802.11a phy core */ #define BHND_COREID_BPHY 0x814 /* 802.11b phy core */ #define BHND_COREID_GPHY 0x815 /* 802.11g phy core */ #define BHND_COREID_MIPS33 0x816 /* mips3302 core */ #define BHND_COREID_USB11H 0x817 /* usb 1.1 host core */ #define BHND_COREID_USB11D 0x818 /* usb 1.1 device core */ #define BHND_COREID_USB20H 0x819 /* usb 2.0 host core */ #define BHND_COREID_USB20D 0x81a /* usb 2.0 device core */ #define BHND_COREID_SDIOH 0x81b /* sdio host core */ #define BHND_COREID_ROBO 0x81c /* roboswitch core */ #define BHND_COREID_ATA100 0x81d /* parallel ATA core */ #define BHND_COREID_SATAXOR 0x81e /* serial ATA & XOR DMA core */ #define BHND_COREID_GIGETH 0x81f /* gigabit ethernet core */ #define BHND_COREID_PCIE 0x820 /* pci express core */ #define BHND_COREID_NPHY 0x821 /* 802.11n 2x2 phy core */ #define BHND_COREID_SRAMC 0x822 /* SRAM controller core */ #define BHND_COREID_MINIMAC 0x823 /* MINI MAC/phy core */ #define BHND_COREID_ARM11 0x824 /* ARM 1176 core */ #define BHND_COREID_ARM7S 0x825 /* ARM7tdmi-s core */ #define BHND_COREID_LPPHY 0x826 /* 802.11a/b/g phy core */ #define BHND_COREID_PMU 0x827 /* PMU core */ #define BHND_COREID_SSNPHY 0x828 /* 802.11n single-stream phy core */ #define BHND_COREID_SDIOD 0x829 /* SDIO device core */ #define BHND_COREID_ARMCM3 0x82a /* ARM Cortex M3 core */ #define BHND_COREID_HTPHY 0x82b /* 802.11n 4x4 phy core */ #define BHND_COREID_MIPS74K 0x82c /* mips 74k core */ #define BHND_COREID_GMAC 0x82d /* Gigabit MAC core */ #define BHND_COREID_DMEMC 0x82e /* DDR1/2 memory controller core */ #define BHND_COREID_PCIERC 0x82f /* PCIE Root Complex core */ #define BHND_COREID_OCP 0x830 /* OCP2OCP bridge core */ #define BHND_COREID_SC 0x831 /* shared common core */ #define BHND_COREID_AHB 0x832 /* OCP2AHB bridge core */ #define BHND_COREID_SPIH 0x833 /* SPI host core */ #define BHND_COREID_I2S 0x834 /* I2S core */ #define BHND_COREID_DMEMS 0x835 /* SDR/DDR1 memory controller core */ #define BHND_COREID_UBUS_SHIM 0x837 /* SHIM component in ubus/6362 */ #define BHND_COREID_PCIE2 0x83c /* pci express (gen2) core */ /* ARM/AMBA Core IDs */ #define BHND_COREID_APB_BRIDGE 0x135 /* BP135 AMBA AXI-APB bridge */ #define BHND_COREID_PL301 0x301 /* PL301 AMBA AXI Interconnect */ #define BHND_COREID_EROM 0x366 /* Enumeration ROM */ #define BHND_COREID_OOB_ROUTER 0x367 /* OOB router core ID */ #define BHND_COREID_AXI_UNMAPPED 0xfff /* AXI "Default Slave"; maps all unused address * ranges, returning DECERR on read or write. */ /* Northstar Plus and BCM4706 Core IDs */ #define BHND_COREID_4706_CC 0x500 /* chipcommon core */ #define BHND_COREID_NS_PCIE2 0x501 /* pci express (gen2) core */ #define BHND_COREID_NS_DMA 0x502 /* dma core */ #define BHND_COREID_NS_SDIO 0x503 /* sdio host core */ #define BHND_COREID_NS_USB20H 0x504 /* usb 2.0 host core */ #define BHND_COREID_NS_USB30H 0x505 /* usb 3.0 host core */ #define BHND_COREID_NS_A9JTAG 0x506 /* ARM Cortex A9 JTAG core */ #define BHND_COREID_NS_DDR23_MEMC 0x507 /* DDR2/3 cadence/denali memory controller core () */ #define BHND_COREID_NS_ROM 0x508 /* device ROM core */ #define BHND_COREID_NS_NAND 0x509 /* NAND flash controller core */ #define BHND_COREID_NS_QSPI 0x50a /* QSPI flash controller core */ #define BHND_COREID_NS_CC_B 0x50b /* chipcommon `b' (auxiliary) core */ #define BHND_COREID_4706_SOCRAM 0x50e /* internal memory core */ #define BHND_COREID_IHOST_ARMCA9 0x510 /* ARM Cortex A9 core */ #define BHND_COREID_4706_GMAC_CMN 0x5dc /* Gigabit MAC common core */ #define BHND_COREID_4706_GMAC 0x52d /* Gigabit MAC core */ #define BHND_COREID_AMEMC 0x52e /* DDR1/2 cadence/denali memory controller core */ /* ARM PrimeCell Peripherial IDs. These were derived from inspection of the * PrimeCell-compatible BCM4331 cores, but due to lack of documentation, the * surmised core name/description may be incorrect. */ #define BHND_PRIMEID_EROM 0x364 /* Enumeration ROM's primecell ID */ #define BHND_PRIMEID_SWRAP 0x368 /* PL368 Device Management Interface (Slave) */ #define BHND_PRIMEID_MWRAP 0x369 /* PL369 Device Management Interface (Master) */ /* Core HW Revision Numbers */ #define BHND_HWREV_INVALID 0xFF /* Invalid hardware revision ID */ /* Chip Types */ #define BHND_CHIPTYPE_SIBA 0 /**< siba(4) interconnect */ #define BHND_CHIPTYPE_BCMA 1 /**< bcma(4) interconnect */ #define BHND_CHIPTYPE_UBUS 2 /**< ubus interconnect found in bcm63xx devices */ #define BHND_CHIPTYPE_BCMA_ALT 3 /**< bcma(4) interconnect */ +/** Evaluates to true if @p _type uses a BCMA EROM table */ +#define BHND_CHIPTYPE_HAS_EROM(_type) \ + ((_type) == BHND_CHIPTYPE_BCMA || \ + (_type) == BHND_CHIPTYPE_BCMA_ALT || \ + (_type) == BHND_CHIPTYPE_UBUS) + /* Boardflags */ #define BHND_BFL_BTC2WIRE 0x00000001 /* old 2wire Bluetooth coexistence, OBSOLETE */ #define BHND_BFL_BTCOEX 0x00000001 /* Board supports BTCOEX */ #define BHND_BFL_PACTRL 0x00000002 /* Board has gpio 9 controlling the PA */ #define BHND_BFL_AIRLINEMODE 0x00000004 /* Board implements gpio 13 radio disable indication, UNUSED */ #define BHND_BFL_ADCDIV 0x00000008 /* Board has the rssi ADC divider */ #define BHND_BFL_DIS_256QAM 0x00000008 #define BHND_BFL_ENETROBO 0x00000010 /* Board has robo switch or core */ #define BHND_BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */ #define BHND_BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */ #define BHND_BFL_ENETADM 0x00000080 /* Board has ADMtek switch */ #define BHND_BFL_ENETVLAN 0x00000100 /* Board has VLAN capability */ #define BHND_BFL_LTECOEX 0x00000200 /* Board has LTE coex capability */ #define BHND_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */ #define BHND_BFL_FEM 0x00000800 /* Board supports the Front End Module */ #define BHND_BFL_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */ #define BHND_BFL_HGPA 0x00002000 /* Board has a high gain PA */ #define BHND_BFL_BTC2WIRE_ALTGPIO 0x00004000 /* Board's BTC 2wire is in the alternate gpios OBSLETE */ #define BHND_BFL_ALTIQ 0x00008000 /* Alternate I/Q settings */ #define BHND_BFL_NOPA 0x00010000 /* Board has no PA */ #define BHND_BFL_RSSIINV 0x00020000 /* Board's RSSI uses positive slope(not TSSI) */ #define BHND_BFL_PAREF 0x00040000 /* Board uses the PARef LDO */ #define BHND_BFL_3TSWITCH 0x00080000 /* Board uses a triple throw switch shared with BT */ #define BHND_BFL_PHASESHIFT 0x00100000 /* Board can support phase shifter */ #define BHND_BFL_BUCKBOOST 0x00200000 /* Power topology uses BUCKBOOST */ #define BHND_BFL_FEM_BT 0x00400000 /* Board has FEM and switch to share antenna w/ BT */ #define BHND_BFL_RXCHAIN_OFF_BT 0x00400000 /* one rxchain is to be shut off when BT is active */ #define BHND_BFL_NOCBUCK 0x00800000 /* Power topology doesn't use CBUCK */ #define BHND_BFL_CCKFAVOREVM 0x01000000 /* Favor CCK EVM over spectral mask */ #define BHND_BFL_PALDO 0x02000000 /* Power topology uses PALDO */ #define BHND_BFL_LNLDO2_2P5 0x04000000 /* Select 2.5V as LNLDO2 output voltage */ #define BHND_BFL_FASTPWR 0x08000000 #define BHND_BFL_UCPWRCTL_MININDX 0x08000000 /* Enforce min power index to avoid FEM damage */ #define BHND_BFL_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */ #define BHND_BFL_TRSW_1by2 0x20000000 /* Board has 2 TRSW's in 1by2 designs */ #define BHND_BFL_GAINBOOSTA01 0x20000000 /* 5g Gainboost for core0 and core1 */ #define BHND_BFL_LO_TRSW_R_5GHz 0x40000000 /* In 5G do not throw TRSW to T for clipLO gain */ #define BHND_BFL_ELNA_GAINDEF 0x80000000 /* Backoff InitGain based on elna_2g/5g field * when this flag is set */ #define BHND_BFL_EXTLNA_TX 0x20000000 /* Temp boardflag to indicate to */ /* Boardflags2 */ #define BHND_BFL2_RXBB_INT_REG_DIS 0x00000001 /* Board has an external rxbb regulator */ #define BHND_BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */ #define BHND_BFL2_TXPWRCTRL_EN 0x00000004 /* Board permits enabling TX Power Control */ #define BHND_BFL2_2X4_DIV 0x00000008 /* Board supports the 2X4 diversity switch */ #define BHND_BFL2_5G_PWRGAIN 0x00000010 /* Board supports 5G band power gain */ #define BHND_BFL2_PCIEWAR_OVR 0x00000020 /* Board overrides ASPM and Clkreq settings */ #define BHND_BFL2_CAESERS_BRD 0x00000040 /* Board is Caesers brd (unused by sw) */ #define BHND_BFL2_BTC3WIRE 0x00000080 /* Board support legacy 3 wire or 4 wire */ #define BHND_BFL2_BTCLEGACY 0x00000080 /* Board support legacy 3/4 wire, to replace * BHND_BFL2_BTC3WIRE */ #define BHND_BFL2_SKWRKFEM_BRD 0x00000100 /* 4321mcm93 board uses Skyworks FEM */ #define BHND_BFL2_SPUR_WAR 0x00000200 /* Board has a WAR for clock-harmonic spurs */ #define BHND_BFL2_GPLL_WAR 0x00000400 /* Flag to narrow G-band PLL loop b/w */ #define BHND_BFL2_TRISTATE_LED 0x00000800 /* Tri-state the LED */ #define BHND_BFL2_SINGLEANT_CCK 0x00001000 /* Tx CCK pkts on Ant 0 only */ #define BHND_BFL2_2G_SPUR_WAR 0x00002000 /* WAR to reduce and avoid clock-harmonic spurs in 2G */ #define BHND_BFL2_BPHY_ALL_TXCORES 0x00004000 /* Transmit bphy frames using all tx cores */ #define BHND_BFL2_FCC_BANDEDGE_WAR 0x00008000 /* Activates WAR to improve FCC bandedge performance */ #define BHND_BFL2_GPLL_WAR2 0x00010000 /* Flag to widen G-band PLL loop b/w */ #define BHND_BFL2_IPALVLSHIFT_3P3 0x00020000 #define BHND_BFL2_INTERNDET_TXIQCAL 0x00040000 /* Use internal envelope detector for TX IQCAL */ #define BHND_BFL2_XTALBUFOUTEN 0x00080000 /* Keep the buffered Xtal output from radio on */ /* Most drivers will turn it off without this flag */ /* to save power. */ #define BHND_BFL2_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are controlled by analog PA ctrl lines */ #define BHND_BFL2_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are controlled by analog PA ctrl lines */ #define BHND_BFL2_ELNACTRL_TRSW_2G 0x00400000 /* AZW4329: 2G gmode_elna_gain controls TR Switch */ #define BHND_BFL2_BT_SHARE_ANT0 0x00800000 /* WLAN/BT share antenna 0 */ #define BHND_BFL2_BT_SHARE_BM_BIT0 0x00800000 /* bit 0 of WLAN/BT shared core bitmap */ #define BHND_BFL2_TEMPSENSE_HIGHER 0x01000000 /* The tempsense threshold can sustain higher value * than programmed. The exact delta is decided by * driver per chip/boardtype. This can be used * when tempsense qualification happens after shipment */ #define BHND_BFL2_BTC3WIREONLY 0x02000000 /* standard 3 wire btc only. 4 wire not supported */ #define BHND_BFL2_PWR_NOMINAL 0x04000000 /* 0: power reduction on, 1: no power reduction */ #define BHND_BFL2_EXTLNA_PWRSAVE 0x08000000 /* boardflag to enable ucode to apply power save * ucode control of eLNA during Tx */ #define BHND_BFL2_4313_RADIOREG 0x10000000 /* board rework */ #define BHND_BFL2_DYNAMIC_VMID 0x10000000 /* boardflag to enable dynamic Vmid idle TSSI CAL */ #define BHND_BFL2_SDR_EN 0x20000000 /* SDR enabled or disabled */ #define BHND_BFL2_LNA1BYPFORTR2G 0x40000000 /* acphy, enable lna1 bypass for clip gain, 2g */ #define BHND_BFL2_LNA1BYPFORTR5G 0x80000000 /* acphy, enable lna1 bypass for clip gain, 5g */ /* SROM 11 - 11ac boardflag definitions */ #define BHND_BFL_SROM11_BTCOEX 0x00000001 /* Board supports BTCOEX */ #define BHND_BFL_SROM11_WLAN_BT_SH_XTL 0x00000002 /* bluetooth and wlan share same crystal */ #define BHND_BFL_SROM11_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */ #define BHND_BFL_SROM11_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */ #define BHND_BFL_SROM11_GAINBOOSTA01 0x20000000 /* 5g Gainboost for core0 and core1 */ #define BHND_BFL2_SROM11_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */ #define BHND_BFL2_SROM11_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are ctrl-ed by analog PA ctrl lines */ #define BHND_BFL2_SROM11_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are ctrl-ed by analog PA ctrl lines */ /* Boardflags3 */ #define BHND_BFL3_FEMCTRL_SUB 0x00000007 /* acphy, subrevs of femctrl on top of srom_femctrl */ #define BHND_BFL3_RCAL_WAR 0x00000008 /* acphy, rcal war active on this board (4335a0) */ #define BHND_BFL3_TXGAINTBLID 0x00000070 /* acphy, txgain table id */ #define BHND_BFL3_TXGAINTBLID_SHIFT 0x4 /* acphy, txgain table id shift bit */ #define BHND_BFL3_TSSI_DIV_WAR 0x00000080 /* acphy, Separate paparam for 20/40/80 */ #define BHND_BFL3_TSSI_DIV_WAR_SHIFT 0x7 /* acphy, Separate paparam for 20/40/80 shift bit */ #define BHND_BFL3_FEMTBL_FROM_NVRAM 0x00000100 /* acphy, femctrl table is read from nvram */ #define BHND_BFL3_FEMTBL_FROM_NVRAM_SHIFT 0x8 /* acphy, femctrl table is read from nvram */ #define BHND_BFL3_AGC_CFG_2G 0x00000200 /* acphy, gain control configuration for 2G */ #define BHND_BFL3_AGC_CFG_5G 0x00000400 /* acphy, gain control configuration for 5G */ #define BHND_BFL3_PPR_BIT_EXT 0x00000800 /* acphy, bit position for 1bit extension for ppr */ #define BHND_BFL3_PPR_BIT_EXT_SHIFT 11 /* acphy, bit shift for 1bit extension for ppr */ #define BHND_BFL3_BBPLL_SPR_MODE_DIS 0x00001000 /* acphy, disables bbpll spur modes */ #define BHND_BFL3_RCAL_OTP_VAL_EN 0x00002000 /* acphy, to read rcal_trim value from otp */ #define BHND_BFL3_2GTXGAINTBL_BLANK 0x00004000 /* acphy, blank the first X ticks of 2g gaintbl */ #define BHND_BFL3_2GTXGAINTBL_BLANK_SHIFT 14 /* acphy, blank the first X ticks of 2g gaintbl */ #define BHND_BFL3_5GTXGAINTBL_BLANK 0x00008000 /* acphy, blank the first X ticks of 5g gaintbl */ #define BHND_BFL3_5GTXGAINTBL_BLANK_SHIFT 15 /* acphy, blank the first X ticks of 5g gaintbl */ #define BHND_BFL3_BT_SHARE_BM_BIT1 0x40000000 /* bit 1 of WLAN/BT shared core bitmap */ #define BHND_BFL3_PHASETRACK_MAX_ALPHABETA 0x00010000 /* acphy, to max out alpha,beta to 511 */ #define BHND_BFL3_PHASETRACK_MAX_ALPHABETA_SHIFT 16 /* acphy, to max out alpha,beta to 511 */ #define BHND_BFL3_BT_SHARE_BM_BIT1 0x40000000 /* bit 1 of WLAN/BT shared core bitmap */ #define BHND_BFL3_EN_NONBRCM_TXBF 0x10000000 /* acphy, enable non-brcm TXBF */ #define BHND_BFL3_EN_P2PLINK_TXBF 0x20000000 /* acphy, enable TXBF in p2p links */ /* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */ #define BHND_GPIO_BOARD_BTC3W_IN 0x850 /* bit 4 is RF_ACTIVE, bit 6 is STATUS, bit 11 is PRI */ #define BHND_GPIO_BOARD_BTC3W_OUT 0x020 /* bit 5 is TX_CONF */ #define BHND_GPIO_BOARD_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistence Input */ #define BHND_GPIO_BOARD_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistence Out */ #define BHND_GPIO_BOARD_BTC_IN 0x080 /* bit 7 is BT Coexistence Input */ #define BHND_GPIO_BOARD_BTC_OUT 0x100 /* bit 8 is BT Coexistence Out */ #define BHND_GPIO_BOARD_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */ #define BHND_GPIO_BOARD_12 0x1000 /* gpio 12 */ #define BHND_GPIO_BOARD_13 0x2000 /* gpio 13 */ #define BHND_GPIO_BOARD_BTC4_IN 0x0800 /* gpio 11, coex4, in */ #define BHND_GPIO_BOARD_BTC4_BT 0x2000 /* gpio 12, coex4, bt active */ #define BHND_GPIO_BOARD_BTC4_STAT 0x4000 /* gpio 14, coex4, status */ #define BHND_GPIO_BOARD_BTC4_WLAN 0x8000 /* gpio 15, coex4, wlan active */ #define BHND_GPIO_BOARD_1_WLAN_PWR 0x02 /* throttle WLAN power on X21 board */ #define BHND_GPIO_BOARD_3_WLAN_PWR 0x08 /* throttle WLAN power on X28 board */ #define BHND_GPIO_BOARD_4_WLAN_PWR 0x10 /* throttle WLAN power on X19 board */ #define BHND_GPIO_BTC4W_OUT_4312 0x010 /* bit 4 is BT_IODISABLE */ #define BHND_GPIO_BTC4W_OUT_43224 0x020 /* bit 5 is BT_IODISABLE */ #define BHND_GPIO_BTC4W_OUT_43224_SHARED 0x0e0 /* bit 5 is BT_IODISABLE */ #define BHND_GPIO_BTC4W_OUT_43225 0x0e0 /* bit 5 BT_IODISABLE, bit 6 SW_BT, bit 7 SW_WL */ #define BHND_GPIO_BTC4W_OUT_43421 0x020 /* bit 5 is BT_IODISABLE */ #define BHND_GPIO_BTC4W_OUT_4313 0x060 /* bit 5 SW_BT, bit 6 SW_WL */ #define BHND_GPIO_BTC4W_OUT_4331_SHARED 0x010 /* GPIO 4 */ /* Power Control Defines */ #define BHND_CHIPC_PLL_DELAY 150 /* us pll on delay */ #define BHND_CHIPC_FREF_DELAY 200 /* us fref change delay */ #define BHND_CHIPC_MIN_SLOW_CLK 32 /* us Slow clock period */ #define BHND_CHIPC_XTAL_ON_DELAY 1000 /* us crystal power-on delay */ /* Board Types */ #define BHND_BOARD_BU4710 0x0400 #define BHND_BOARD_VSIM4710 0x0401 #define BHND_BOARD_QT4710 0x0402 #define BHND_BOARD_BU4309 0x040a #define BHND_BOARD_BCM94309CB 0x040b #define BHND_BOARD_BCM94309MP 0x040c #define BHND_BOARD_BCM4309AP 0x040d #define BHND_BOARD_BCM94302MP 0x040e #define BHND_BOARD_BU4306 0x0416 #define BHND_BOARD_BCM94306CB 0x0417 #define BHND_BOARD_BCM94306MP 0x0418 #define BHND_BOARD_BCM94710D 0x041a #define BHND_BOARD_BCM94710R1 0x041b #define BHND_BOARD_BCM94710R4 0x041c #define BHND_BOARD_BCM94710AP 0x041d #define BHND_BOARD_BU2050 0x041f #define BHND_BOARD_BCM94309G 0x0421 #define BHND_BOARD_BU4704 0x0423 #define BHND_BOARD_BU4702 0x0424 #define BHND_BOARD_BCM94306PC 0x0425 /* pcmcia 3.3v 4306 card */ #define BHND_BOARD_BCM94702MN 0x0428 /* BCM4702 1U CompactPCI Board */ #define BHND_BOARD_BCM94702CPCI 0x0429 /* BCM4702 with BCM95380 VLAN Router */ #define BHND_BOARD_BCM95380RR 0x042a /* cb4306 with SiGe PA */ #define BHND_BOARD_BCM94306CBSG 0x042b /* cb4306 with SiGe PA */ #define BHND_BOARD_PCSG94306 0x042d /* bu4704 with sdram */ #define BHND_BOARD_BU4704SD 0x042e /* Dual 11a/11g Router */ #define BHND_BOARD_BCM94704AGR 0x042f /* 11a-only minipci */ #define BHND_BOARD_BCM94308MP 0x0430 #define BHND_BOARD_BU4712 0x0444 #define BHND_BOARD_BU4712SD 0x045d #define BHND_BOARD_BU4712L 0x045f /* BCM4712 boards */ #define BHND_BOARD_BCM94712AP 0x0445 #define BHND_BOARD_BCM94712P 0x0446 /* BCM4318 boards */ #define BHND_BOARD_BU4318 0x0447 #define BHND_BOARD_CB4318 0x0448 #define BHND_BOARD_MPG4318 0x0449 #define BHND_BOARD_MP4318 0x044a #define BHND_BOARD_SD4318 0x044b /* BCM4313 boards */ #define BHND_BOARD_BCM94313BU 0x050f #define BHND_BOARD_BCM94313HM 0x0510 #define BHND_BOARD_BCM94313EPA 0x0511 #define BHND_BOARD_BCM94313HMG 0x051C /* BCM63XX boards */ #define BHND_BOARD_BCM96338 0x6338 #define BHND_BOARD_BCM96348 0x6348 #define BHND_BOARD_BCM96358 0x6358 #define BHND_BOARD_BCM96368 0x6368 /* Another mp4306 with SiGe */ #define BHND_BOARD_BCM94306P 0x044c /* mp4303 */ #define BHND_BOARD_BCM94303MP 0x044e /* mpsgh4306 */ #define BHND_BOARD_BCM94306MPSGH 0x044f /* BRCM 4306 w/ Front End Modules */ #define BHND_BOARD_BCM94306MPM 0x0450 #define BHND_BOARD_BCM94306MPL 0x0453 /* 4712agr */ #define BHND_BOARD_BCM94712AGR 0x0451 /* pcmcia 4303 */ #define BHND_BOARD_PC4303 0x0454 /* 5350K */ #define BHND_BOARD_BCM95350K 0x0455 /* 5350R */ #define BHND_BOARD_BCM95350R 0x0456 /* 4306mplna */ #define BHND_BOARD_BCM94306MPLNA 0x0457 /* 4320 boards */ #define BHND_BOARD_BU4320 0x0458 #define BHND_BOARD_BU4320S 0x0459 #define BHND_BOARD_BCM94320PH 0x045a /* 4306mph */ #define BHND_BOARD_BCM94306MPH 0x045b /* 4306pciv */ #define BHND_BOARD_BCM94306PCIV 0x045c #define BHND_BOARD_BU4712SD 0x045d #define BHND_BOARD_BCM94320PFLSH 0x045e #define BHND_BOARD_BU4712L 0x045f #define BHND_BOARD_BCM94712LGR 0x0460 #define BHND_BOARD_BCM94320R 0x0461 #define BHND_BOARD_BU5352 0x0462 #define BHND_BOARD_BCM94318MPGH 0x0463 #define BHND_BOARD_BU4311 0x0464 #define BHND_BOARD_BCM94311MC 0x0465 #define BHND_BOARD_BCM94311MCAG 0x0466 #define BHND_BOARD_BCM95352GR 0x0467 /* bcm95351agr */ #define BHND_BOARD_BCM95351AGR 0x0470 /* bcm94704mpcb */ #define BHND_BOARD_BCM94704MPCB 0x0472 /* 4785 boards */ #define BHND_BOARD_BU4785 0x0478 /* 4321 boards */ #define BHND_BOARD_BCM4321BU 0x046b #define BHND_BOARD_BCM4321BUE 0x047c #define BHND_BOARD_BCM4321MP 0x046c #define BHND_BOARD_BCM4321CB2 0x046d #define BHND_BOARD_BCM4321CB2_AG 0x0066 #define BHND_BOARD_BCM4321MC 0x046e /* 4328 boards */ #define BHND_BOARD_BU4328 0x0481 #define BHND_BOARD_BCM4328SDG 0x0482 #define BHND_BOARD_BCM4328SDAG 0x0483 #define BHND_BOARD_BCM4328UG 0x0484 #define BHND_BOARD_BCM4328UAG 0x0485 #define BHND_BOARD_BCM4328PC 0x0486 #define BHND_BOARD_BCM4328CF 0x0487 /* 4325 boards */ #define BHND_BOARD_BCM94325DEVBU 0x0490 #define BHND_BOARD_BCM94325BGABU 0x0491 #define BHND_BOARD_BCM94325SDGWB 0x0492 #define BHND_BOARD_BCM94325SDGMDL 0x04aa #define BHND_BOARD_BCM94325SDGMDL2 0x04c6 #define BHND_BOARD_BCM94325SDGMDL3 0x04c9 #define BHND_BOARD_BCM94325SDABGWBA 0x04e1 /* 4322 boards */ #define BHND_BOARD_BCM94322MC 0x04a4 #define BHND_BOARD_BCM94322USB 0x04a8 /* dualband */ #define BHND_BOARD_BCM94322HM 0x04b0 #define BHND_BOARD_BCM94322USB2D 0x04bf /* single band discrete front end */ /* 4312 boards */ #define BHND_BOARD_BCM4312MCGSG 0x04b5 /* 4315 boards */ #define BHND_BOARD_BCM94315DEVBU 0x04c2 #define BHND_BOARD_BCM94315USBGP 0x04c7 #define BHND_BOARD_BCM94315BGABU 0x04ca #define BHND_BOARD_BCM94315USBGP41 0x04cb /* 4319 boards */ #define BHND_BOARD_BCM94319DEVBU 0X04e5 #define BHND_BOARD_BCM94319USB 0X04e6 #define BHND_BOARD_BCM94319SD 0X04e7 /* 4716 boards */ #define BHND_BOARD_BCM94716NR2 0x04cd /* 4319 boards */ #define BHND_BOARD_BCM94319DEVBU 0X04e5 #define BHND_BOARD_BCM94319USBNP4L 0X04e6 #define BHND_BOARD_BCM94319WLUSBN4L 0X04e7 #define BHND_BOARD_BCM94319SDG 0X04ea #define BHND_BOARD_BCM94319LCUSBSDN4L 0X04eb #define BHND_BOARD_BCM94319USBB 0x04ee #define BHND_BOARD_BCM94319LCSDN4L 0X0507 #define BHND_BOARD_BCM94319LSUSBN4L 0X0508 #define BHND_BOARD_BCM94319SDNA4L 0X0517 #define BHND_BOARD_BCM94319SDELNA4L 0X0518 #define BHND_BOARD_BCM94319SDELNA6L 0X0539 #define BHND_BOARD_BCM94319ARCADYAN 0X0546 #define BHND_BOARD_BCM94319WINDSOR 0x0561 #define BHND_BOARD_BCM94319MLAP 0x0562 #define BHND_BOARD_BCM94319SDNA 0x058b #define BHND_BOARD_BCM94319BHEMU3 0x0563 #define BHND_BOARD_BCM94319SDHMB 0x058c #define BHND_BOARD_BCM94319SDBREF 0x05a1 #define BHND_BOARD_BCM94319USBSDB 0x05a2 /* 4329 boards */ #define BHND_BOARD_BCM94329AGB 0X04b9 #define BHND_BOARD_BCM94329TDKMDL1 0X04ba #define BHND_BOARD_BCM94329TDKMDL11 0X04fc #define BHND_BOARD_BCM94329OLYMPICN18 0X04fd #define BHND_BOARD_BCM94329OLYMPICN90 0X04fe #define BHND_BOARD_BCM94329OLYMPICN90U 0X050c #define BHND_BOARD_BCM94329OLYMPICN90M 0X050b #define BHND_BOARD_BCM94329AGBF 0X04ff #define BHND_BOARD_BCM94329OLYMPICX17 0X0504 #define BHND_BOARD_BCM94329OLYMPICX17M 0X050a #define BHND_BOARD_BCM94329OLYMPICX17U 0X0509 #define BHND_BOARD_BCM94329OLYMPICUNO 0X0564 #define BHND_BOARD_BCM94329MOTOROLA 0X0565 #define BHND_BOARD_BCM94329OLYMPICLOCO 0X0568 /* 4336 SDIO board types */ #define BHND_BOARD_BCM94336SD_WLBGABU 0x0511 #define BHND_BOARD_BCM94336SD_WLBGAREF 0x0519 #define BHND_BOARD_BCM94336SDGP 0x0538 #define BHND_BOARD_BCM94336SDG 0x0519 #define BHND_BOARD_BCM94336SDGN 0x0538 #define BHND_BOARD_BCM94336SDGFC 0x056B /* 4330 SDIO board types */ #define BHND_BOARD_BCM94330SDG 0x0528 #define BHND_BOARD_BCM94330SD_FCBGABU 0x052e #define BHND_BOARD_BCM94330SD_WLBGABU 0x052f #define BHND_BOARD_BCM94330SD_FCBGA 0x0530 #define BHND_BOARD_BCM94330FCSDAGB 0x0532 #define BHND_BOARD_BCM94330OLYMPICAMG 0x0549 #define BHND_BOARD_BCM94330OLYMPICAMGEPA 0x054F #define BHND_BOARD_BCM94330OLYMPICUNO3 0x0551 #define BHND_BOARD_BCM94330WLSDAGB 0x0547 #define BHND_BOARD_BCM94330CSPSDAGBB 0x054A /* 43224 boards */ #define BHND_BOARD_BCM943224X21 0x056e #define BHND_BOARD_BCM943224X21_FCC 0x00d1 #define BHND_BOARD_BCM943224X21B 0x00e9 #define BHND_BOARD_BCM943224M93 0x008b #define BHND_BOARD_BCM943224M93A 0x0090 #define BHND_BOARD_BCM943224X16 0x0093 #define BHND_BOARD_BCM94322X9 0x008d #define BHND_BOARD_BCM94322M35e 0x008e /* 43228 Boards */ #define BHND_BOARD_BCM943228BU8 0x0540 #define BHND_BOARD_BCM943228BU9 0x0541 #define BHND_BOARD_BCM943228BU 0x0542 #define BHND_BOARD_BCM943227HM4L 0x0543 #define BHND_BOARD_BCM943227HMB 0x0544 #define BHND_BOARD_BCM943228HM4L 0x0545 #define BHND_BOARD_BCM943228SD 0x0573 /* 43239 Boards */ #define BHND_BOARD_BCM943239MOD 0x05ac #define BHND_BOARD_BCM943239REF 0x05aa /* 4331 boards */ #define BHND_BOARD_BCM94331X19 0x00D6 /* X19B */ #define BHND_BOARD_BCM94331X28 0x00E4 /* X28 */ #define BHND_BOARD_BCM94331X28B 0x010E /* X28B */ #define BHND_BOARD_BCM94331PCIEBT3Ax BCM94331X28 #define BHND_BOARD_BCM94331X12_2G 0x00EC /* X12 2G */ #define BHND_BOARD_BCM94331X12_5G 0x00ED /* X12 5G */ #define BHND_BOARD_BCM94331X29B 0x00EF /* X29B */ #define BHND_BOARD_BCM94331X29D 0x010F /* X29D */ #define BHND_BOARD_BCM94331CSAX BCM94331X29B #define BHND_BOARD_BCM94331X19C 0x00F5 /* X19C */ #define BHND_BOARD_BCM94331X33 0x00F4 /* X33 */ #define BHND_BOARD_BCM94331BU 0x0523 #define BHND_BOARD_BCM94331S9BU 0x0524 #define BHND_BOARD_BCM94331MC 0x0525 #define BHND_BOARD_BCM94331MCI 0x0526 #define BHND_BOARD_BCM94331PCIEBT4 0x0527 #define BHND_BOARD_BCM94331HM 0x0574 #define BHND_BOARD_BCM94331PCIEDUAL 0x059B #define BHND_BOARD_BCM94331MCH5 0x05A9 #define BHND_BOARD_BCM94331CS 0x05C6 #define BHND_BOARD_BCM94331CD 0x05DA /* 4314 Boards */ #define BHND_BOARD_BCM94314BU 0x05b1 /* 53572 Boards */ #define BHND_BOARD_BCM953572BU 0x058D #define BHND_BOARD_BCM953572NR2 0x058E #define BHND_BOARD_BCM947188NR2 0x058F #define BHND_BOARD_BCM953572SDRNR2 0x0590 /* 43236 boards */ #define BHND_BOARD_BCM943236OLYMPICSULLEY 0x594 #define BHND_BOARD_BCM943236PREPROTOBLU2O3 0x5b9 #define BHND_BOARD_BCM943236USBELNA 0x5f8 /* 4314 Boards */ #define BHND_BOARD_BCM94314BUSDIO 0x05c8 #define BHND_BOARD_BCM94314BGABU 0x05c9 #define BHND_BOARD_BCM94314HMEPA 0x05ca #define BHND_BOARD_BCM94314HMEPABK 0x05cb #define BHND_BOARD_BCM94314SUHMEPA 0x05cc #define BHND_BOARD_BCM94314SUHM 0x05cd #define BHND_BOARD_BCM94314HM 0x05d1 /* 4334 Boards */ #define BHND_BOARD_BCM94334FCAGBI 0x05df #define BHND_BOARD_BCM94334WLAGBI 0x05dd /* 4335 Boards */ #define BHND_BOARD_BCM94335X52 0x0114 /* 4345 Boards */ #define BHND_BOARD_BCM94345 0x0687 /* 4360 Boards */ #define BHND_BOARD_BCM94360X52C 0X0117 #define BHND_BOARD_BCM94360X52D 0X0137 #define BHND_BOARD_BCM94360X29C 0X0112 #define BHND_BOARD_BCM94360X29CP2 0X0134 #define BHND_BOARD_BCM94360X51 0x0111 #define BHND_BOARD_BCM94360X51P2 0x0129 #define BHND_BOARD_BCM94360X51A 0x0135 #define BHND_BOARD_BCM94360X51B 0x0136 #define BHND_BOARD_BCM94360CS 0x061B #define BHND_BOARD_BCM94360J28_D11AC2G 0x0c00 #define BHND_BOARD_BCM94360J28_D11AC5G 0x0c01 #define BHND_BOARD_BCM94360USBH5_D11AC5G 0x06aa /* 4350 Boards */ #define BHND_BOARD_BCM94350X52B 0X0116 #define BHND_BOARD_BCM94350X14 0X0131 /* 43217 Boards */ #define BHND_BOARD_BCM943217BU 0x05d5 #define BHND_BOARD_BCM943217HM2L 0x05d6 #define BHND_BOARD_BCM943217HMITR2L 0x05d7 /* 43142 Boards */ #define BHND_BOARD_BCM943142HM 0x05e0 /* 43341 Boards */ #define BHND_BOARD_BCM943341WLABGS 0x062d /* 43342 Boards */ #define BHND_BOARD_BCM943342FCAGBI 0x0641 /* 43602 Boards, unclear yet what boards will be created. */ #define BHND_BOARD_BCM943602RSVD1 0x06a5 #define BHND_BOARD_BCM943602RSVD2 0x06a6 #define BHND_BOARD_BCM943602X87 0X0133 #define BHND_BOARD_BCM943602X238 0X0132 /* 4354 board types */ #define BHND_BOARD_BCM94354WLSAGBI 0x06db #define BHND_BOARD_BCM94354Z 0x0707 /* # of GPIO pins */ #define BHND_BCM43XX_GPIO_NUMPINS 32 /* These values are used by dhd USB host driver. */ #define BHND_USB_RDL_RAM_BASE_4319 0x60000000 #define BHND_USB_RDL_RAM_BASE_4329 0x60000000 #define BHND_USB_RDL_RAM_SIZE_4319 0x48000 #define BHND_USB_RDL_RAM_SIZE_4329 0x48000 #define BHND_USB_RDL_RAM_SIZE_43236 0x70000 #define BHND_USB_RDL_RAM_BASE_43236 0x60000000 #define BHND_USB_RDL_RAM_SIZE_4328 0x60000 #define BHND_USB_RDL_RAM_BASE_4328 0x80000000 #define BHND_USB_RDL_RAM_SIZE_4322 0x60000 #define BHND_USB_RDL_RAM_BASE_4322 0x60000000 #define BHND_USB_RDL_RAM_SIZE_4360 0xA0000 #define BHND_USB_RDL_RAM_BASE_4360 0x60000000 #define BHND_USB_RDL_RAM_SIZE_43242 0x90000 #define BHND_USB_RDL_RAM_BASE_43242 0x60000000 #define BHND_USB_RDL_RAM_SIZE_43143 0x70000 #define BHND_USB_RDL_RAM_BASE_43143 0x60000000 #define BHND_USB_RDL_RAM_SIZE_4350 0xC0000 #define BHND_USB_RDL_RAM_BASE_4350 0x180800 /* generic defs for nvram "muxenab" bits * Note: these differ for 4335a0. refer bcmchipc.h for specific mux options. */ #define BHND_NVRAM_MUXENAB_UART 0x00000001 #define BHND_NVRAM_MUXENAB_GPIO 0x00000002 #define BHND_NVRAM_MUXENAB_ERCX 0x00000004 /* External Radio BT coex */ #define BHND_NVRAM_MUXENAB_JTAG 0x00000008 #define BHND_NVRAM_MUXENAB_HOST_WAKE 0x00000010 /* configure GPIO for SDIO host_wake */ #define BHND_NVRAM_MUXENAB_I2S_EN 0x00000020 #define BHND_NVRAM_MUXENAB_I2S_MASTER 0x00000040 #define BHND_NVRAM_MUXENAB_I2S_FULL 0x00000080 #define BHND_NVRAM_MUXENAB_SFLASH 0x00000100 #define BHND_NVRAM_MUXENAB_RFSWCTRL0 0x00000200 #define BHND_NVRAM_MUXENAB_RFSWCTRL1 0x00000400 #define BHND_NVRAM_MUXENAB_RFSWCTRL2 0x00000800 #define BHND_NVRAM_MUXENAB_SECI 0x00001000 #define BHND_NVRAM_MUXENAB_BT_LEGACY 0x00002000 #define BHND_NVRAM_MUXENAB_HOST_WAKE1 0x00004000 /* configure alternative GPIO for SDIO host_wake */ /* Boot flags */ #define BHND_BOOTFLAG_FLASH_KERNEL_NFLASH 0x00000001 #define BHND_BOOTFLAG_FLASH_BOOT_NFLASH 0x00000002 #endif /* _BHND_BHND_IDS_H_ */ Index: head/sys/dev/bhnd/bhnd_subr.c =================================================================== --- head/sys/dev/bhnd/bhnd_subr.c (revision 304858) +++ head/sys/dev/bhnd/bhnd_subr.c (revision 304859) @@ -1,1463 +1,1460 @@ /*- * Copyright (c) 2015 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include "nvram/bhnd_nvram.h" #include "bhnd_chipc_if.h" #include "bhnd_nvram_if.h" #include "bhnd_nvram_map.h" #include "bhndreg.h" #include "bhndvar.h" /* BHND core device description table. */ static const struct bhnd_core_desc { uint16_t vendor; uint16_t device; bhnd_devclass_t class; const char *desc; } bhnd_core_descs[] = { #define BHND_CDESC(_mfg, _cid, _cls, _desc) \ { BHND_MFGID_ ## _mfg, BHND_COREID_ ## _cid, \ BHND_DEVCLASS_ ## _cls, _desc } BHND_CDESC(BCM, CC, CC, "ChipCommon I/O Controller"), BHND_CDESC(BCM, ILINE20, OTHER, "iLine20 HPNA"), BHND_CDESC(BCM, SRAM, RAM, "SRAM"), BHND_CDESC(BCM, SDRAM, RAM, "SDRAM"), BHND_CDESC(BCM, PCI, PCI, "PCI Bridge"), BHND_CDESC(BCM, MIPS, CPU, "MIPS Core"), BHND_CDESC(BCM, ENET, ENET_MAC, "Fast Ethernet MAC"), BHND_CDESC(BCM, CODEC, OTHER, "V.90 Modem Codec"), BHND_CDESC(BCM, USB, OTHER, "USB 1.1 Device/Host Controller"), BHND_CDESC(BCM, ADSL, OTHER, "ADSL Core"), BHND_CDESC(BCM, ILINE100, OTHER, "iLine100 HPNA"), BHND_CDESC(BCM, IPSEC, OTHER, "IPsec Accelerator"), BHND_CDESC(BCM, UTOPIA, OTHER, "UTOPIA ATM Core"), BHND_CDESC(BCM, PCMCIA, PCCARD, "PCMCIA Bridge"), BHND_CDESC(BCM, SOCRAM, RAM, "Internal Memory"), BHND_CDESC(BCM, MEMC, MEMC, "MEMC SDRAM Controller"), BHND_CDESC(BCM, OFDM, OTHER, "OFDM PHY"), BHND_CDESC(BCM, EXTIF, OTHER, "External Interface"), BHND_CDESC(BCM, D11, WLAN, "802.11 MAC/PHY/Radio"), BHND_CDESC(BCM, APHY, WLAN_PHY, "802.11a PHY"), BHND_CDESC(BCM, BPHY, WLAN_PHY, "802.11b PHY"), BHND_CDESC(BCM, GPHY, WLAN_PHY, "802.11g PHY"), BHND_CDESC(BCM, MIPS33, CPU, "MIPS3302 Core"), BHND_CDESC(BCM, USB11H, OTHER, "USB 1.1 Host Controller"), BHND_CDESC(BCM, USB11D, OTHER, "USB 1.1 Device Core"), BHND_CDESC(BCM, USB20H, OTHER, "USB 2.0 Host Controller"), BHND_CDESC(BCM, USB20D, OTHER, "USB 2.0 Device Core"), BHND_CDESC(BCM, SDIOH, OTHER, "SDIO Host Controller"), BHND_CDESC(BCM, ROBO, OTHER, "RoboSwitch"), BHND_CDESC(BCM, ATA100, OTHER, "Parallel ATA Controller"), BHND_CDESC(BCM, SATAXOR, OTHER, "SATA DMA/XOR Controller"), BHND_CDESC(BCM, GIGETH, ENET_MAC, "Gigabit Ethernet MAC"), BHND_CDESC(BCM, PCIE, PCIE, "PCIe Bridge"), BHND_CDESC(BCM, NPHY, WLAN_PHY, "802.11n 2x2 PHY"), BHND_CDESC(BCM, SRAMC, MEMC, "SRAM Controller"), BHND_CDESC(BCM, MINIMAC, OTHER, "MINI MAC/PHY"), BHND_CDESC(BCM, ARM11, CPU, "ARM1176 CPU"), BHND_CDESC(BCM, ARM7S, CPU, "ARM7TDMI-S CPU"), BHND_CDESC(BCM, LPPHY, WLAN_PHY, "802.11a/b/g PHY"), BHND_CDESC(BCM, PMU, PMU, "PMU"), BHND_CDESC(BCM, SSNPHY, WLAN_PHY, "802.11n Single-Stream PHY"), BHND_CDESC(BCM, SDIOD, OTHER, "SDIO Device Core"), BHND_CDESC(BCM, ARMCM3, CPU, "ARM Cortex-M3 CPU"), BHND_CDESC(BCM, HTPHY, WLAN_PHY, "802.11n 4x4 PHY"), BHND_CDESC(MIPS,MIPS74K, CPU, "MIPS74k CPU"), BHND_CDESC(BCM, GMAC, ENET_MAC, "Gigabit MAC core"), BHND_CDESC(BCM, DMEMC, MEMC, "DDR1/DDR2 Memory Controller"), BHND_CDESC(BCM, PCIERC, OTHER, "PCIe Root Complex"), BHND_CDESC(BCM, OCP, SOC_BRIDGE, "OCP to OCP Bridge"), BHND_CDESC(BCM, SC, OTHER, "Shared Common Core"), BHND_CDESC(BCM, AHB, SOC_BRIDGE, "OCP to AHB Bridge"), BHND_CDESC(BCM, SPIH, OTHER, "SPI Host Controller"), BHND_CDESC(BCM, I2S, OTHER, "I2S Digital Audio Interface"), BHND_CDESC(BCM, DMEMS, MEMC, "SDR/DDR1 Memory Controller"), BHND_CDESC(BCM, UBUS_SHIM, OTHER, "BCM6362/UBUS WLAN SHIM"), BHND_CDESC(BCM, PCIE2, PCIE, "PCIe Bridge (Gen2)"), BHND_CDESC(ARM, APB_BRIDGE, SOC_BRIDGE, "BP135 AMBA3 AXI to APB Bridge"), BHND_CDESC(ARM, PL301, SOC_ROUTER, "PL301 AMBA3 Interconnect"), BHND_CDESC(ARM, EROM, EROM, "PL366 Device Enumeration ROM"), BHND_CDESC(ARM, OOB_ROUTER, OTHER, "PL367 OOB Interrupt Router"), BHND_CDESC(ARM, AXI_UNMAPPED, OTHER, "Unmapped Address Ranges"), BHND_CDESC(BCM, 4706_CC, CC, "ChipCommon I/O Controller"), BHND_CDESC(BCM, NS_PCIE2, PCIE, "PCIe Bridge (Gen2)"), BHND_CDESC(BCM, NS_DMA, OTHER, "DMA engine"), BHND_CDESC(BCM, NS_SDIO, OTHER, "SDIO 3.0 Host Controller"), BHND_CDESC(BCM, NS_USB20H, OTHER, "USB 2.0 Host Controller"), BHND_CDESC(BCM, NS_USB30H, OTHER, "USB 3.0 Host Controller"), BHND_CDESC(BCM, NS_A9JTAG, OTHER, "ARM Cortex A9 JTAG Interface"), BHND_CDESC(BCM, NS_DDR23_MEMC, MEMC, "Denali DDR2/DD3 Memory Controller"), BHND_CDESC(BCM, NS_ROM, NVRAM, "System ROM"), BHND_CDESC(BCM, NS_NAND, NVRAM, "NAND Flash Controller"), BHND_CDESC(BCM, NS_QSPI, NVRAM, "QSPI Flash Controller"), BHND_CDESC(BCM, NS_CC_B, CC_B, "ChipCommon B Auxiliary I/O Controller"), BHND_CDESC(BCM, 4706_SOCRAM, RAM, "Internal Memory"), BHND_CDESC(BCM, IHOST_ARMCA9, CPU, "ARM Cortex A9 CPU"), BHND_CDESC(BCM, 4706_GMAC_CMN, ENET, "Gigabit MAC (Common)"), BHND_CDESC(BCM, 4706_GMAC, ENET_MAC, "Gigabit MAC"), BHND_CDESC(BCM, AMEMC, MEMC, "Denali DDR1/DDR2 Memory Controller"), #undef BHND_CDESC /* Derived from inspection of the BCM4331 cores that provide PrimeCell * IDs. Due to lack of documentation, the surmised device name/purpose * provided here may be incorrect. */ { BHND_MFGID_ARM, BHND_PRIMEID_EROM, BHND_DEVCLASS_OTHER, "PL364 Device Enumeration ROM" }, { BHND_MFGID_ARM, BHND_PRIMEID_SWRAP, BHND_DEVCLASS_OTHER, "PL368 Device Management Interface" }, { BHND_MFGID_ARM, BHND_PRIMEID_MWRAP, BHND_DEVCLASS_OTHER, "PL369 Device Management Interface" }, { 0, 0, 0, NULL } }; /** * Return the name for a given JEP106 manufacturer ID. * * @param vendor A JEP106 Manufacturer ID, including the non-standard ARM 4-bit * JEP106 continuation code. */ const char * bhnd_vendor_name(uint16_t vendor) { switch (vendor) { case BHND_MFGID_ARM: return "ARM"; case BHND_MFGID_BCM: return "Broadcom"; case BHND_MFGID_MIPS: return "MIPS"; default: return "unknown"; } } /** * Return the name of a port type. */ const char * bhnd_port_type_name(bhnd_port_type port_type) { switch (port_type) { case BHND_PORT_DEVICE: return ("device"); case BHND_PORT_BRIDGE: return ("bridge"); case BHND_PORT_AGENT: return ("agent"); default: return "unknown"; } } /** * Return the name of an NVRAM source. */ const char * bhnd_nvram_src_name(bhnd_nvram_src nvram_src) { switch (nvram_src) { case BHND_NVRAM_SRC_FLASH: return ("flash"); case BHND_NVRAM_SRC_OTP: return ("OTP"); case BHND_NVRAM_SRC_SPROM: return ("SPROM"); case BHND_NVRAM_SRC_UNKNOWN: return ("none"); default: return ("unknown"); } } static const struct bhnd_core_desc * bhnd_find_core_desc(uint16_t vendor, uint16_t device) { for (u_int i = 0; bhnd_core_descs[i].desc != NULL; i++) { if (bhnd_core_descs[i].vendor != vendor) continue; if (bhnd_core_descs[i].device != device) continue; return (&bhnd_core_descs[i]); } return (NULL); } /** * Return a human-readable name for a BHND core. * * @param vendor The core designer's JEDEC-106 Manufacturer ID * @param device The core identifier. */ const char * bhnd_find_core_name(uint16_t vendor, uint16_t device) { const struct bhnd_core_desc *desc; if ((desc = bhnd_find_core_desc(vendor, device)) == NULL) return ("unknown"); return desc->desc; } /** * Return the device class for a BHND core. * * @param vendor The core designer's JEDEC-106 Manufacturer ID * @param device The core identifier. */ bhnd_devclass_t bhnd_find_core_class(uint16_t vendor, uint16_t device) { const struct bhnd_core_desc *desc; if ((desc = bhnd_find_core_desc(vendor, device)) == NULL) return (BHND_DEVCLASS_OTHER); return desc->class; } /** * Return a human-readable name for a BHND core. * * @param ci The core's info record. */ const char * bhnd_core_name(const struct bhnd_core_info *ci) { return bhnd_find_core_name(ci->vendor, ci->device); } /** * Return the device class for a BHND core. * * @param ci The core's info record. */ bhnd_devclass_t bhnd_core_class(const struct bhnd_core_info *ci) { return bhnd_find_core_class(ci->vendor, ci->device); } /** * Initialize a core info record with data from from a bhnd-attached @p dev. * * @param dev A bhnd device. * @param core The record to be initialized. */ struct bhnd_core_info bhnd_get_core_info(device_t dev) { return (struct bhnd_core_info) { .vendor = bhnd_get_vendor(dev), .device = bhnd_get_device(dev), .hwrev = bhnd_get_hwrev(dev), .core_idx = bhnd_get_core_index(dev), .unit = bhnd_get_core_unit(dev) }; } /** * Find a @p class child device with @p unit on @p dev. * * @param parent The bhnd-compatible bus to be searched. * @param class The device class to match on. * @param unit The core unit number; specify -1 to return the first match * regardless of unit number. * * @retval device_t if a matching child device is found. * @retval NULL if no matching child device is found. */ device_t bhnd_find_child(device_t dev, bhnd_devclass_t class, int unit) { struct bhnd_core_match md = { BHND_MATCH_CORE_CLASS(class), BHND_MATCH_CORE_UNIT(unit) }; if (unit == -1) md.m.match.core_unit = 0; return bhnd_match_child(dev, &md); } /** * Find the first child device on @p dev that matches @p desc. * * @param parent The bhnd-compatible bus to be searched. * @param desc A match descriptor. * * @retval device_t if a matching child device is found. * @retval NULL if no matching child device is found. */ device_t bhnd_match_child(device_t dev, const struct bhnd_core_match *desc) { device_t *devlistp; device_t match; int devcnt; int error; error = device_get_children(dev, &devlistp, &devcnt); if (error != 0) return (NULL); match = NULL; for (int i = 0; i < devcnt; i++) { struct bhnd_core_info ci = bhnd_get_core_info(devlistp[i]); if (bhnd_core_matches(&ci, desc)) { match = devlistp[i]; goto done; } } done: free(devlistp, M_TEMP); return match; } /** * Walk up the bhnd device hierarchy to locate the root device * to which the bhndb bridge is attached. * * This can be used from within bhnd host bridge drivers to locate the * actual upstream host device. * * @param dev A bhnd device. * @param bus_class The expected bus (e.g. "pci") to which the bridge root * should be attached. * * @retval device_t if a matching parent device is found. * @retval NULL @p dev is not attached via a bhndb bus * @retval NULL no parent device is attached via @p bus_class. */ device_t bhnd_find_bridge_root(device_t dev, devclass_t bus_class) { devclass_t bhndb_class; device_t parent; KASSERT(device_get_devclass(device_get_parent(dev)) == bhnd_devclass, ("%s not a bhnd device", device_get_nameunit(dev))); bhndb_class = devclass_find("bhndb"); /* Walk the device tree until we hit a bridge */ parent = dev; while ((parent = device_get_parent(parent)) != NULL) { if (device_get_devclass(parent) == bhndb_class) break; } /* No bridge? */ if (parent == NULL) return (NULL); /* Search for a parent attached to the expected bus class */ while ((parent = device_get_parent(parent)) != NULL) { device_t bus; bus = device_get_parent(parent); if (bus != NULL && device_get_devclass(bus) == bus_class) return (parent); } /* Not found */ return (NULL); } /** * Find the first core in @p cores that matches @p desc. * * @param cores The table to search. * @param num_cores The length of @p cores. * @param desc A match descriptor. * * @retval bhnd_core_info if a matching core is found. * @retval NULL if no matching core is found. */ const struct bhnd_core_info * bhnd_match_core(const struct bhnd_core_info *cores, u_int num_cores, const struct bhnd_core_match *desc) { for (u_int i = 0; i < num_cores; i++) { if (bhnd_core_matches(&cores[i], desc)) return &cores[i]; } return (NULL); } /** * Find the first core in @p cores with the given @p class. * * @param cores The table to search. * @param num_cores The length of @p cores. * @param desc A match descriptor. * * @retval bhnd_core_info if a matching core is found. * @retval NULL if no matching core is found. */ const struct bhnd_core_info * bhnd_find_core(const struct bhnd_core_info *cores, u_int num_cores, bhnd_devclass_t class) { struct bhnd_core_match md = { BHND_MATCH_CORE_CLASS(class) }; return bhnd_match_core(cores, num_cores, &md); } /** * Return true if the @p core matches @p desc. * * @param core A bhnd core descriptor. * @param desc A match descriptor to compare against @p core. * * @retval true if @p core matches @p match * @retval false if @p core does not match @p match. */ bool bhnd_core_matches(const struct bhnd_core_info *core, const struct bhnd_core_match *desc) { if (desc->m.match.core_vendor && desc->core_vendor != core->vendor) return (false); if (desc->m.match.core_id && desc->core_id != core->device) return (false); if (desc->m.match.core_unit && desc->core_unit != core->unit) return (false); if (desc->m.match.core_rev && !bhnd_hwrev_matches(core->hwrev, &desc->core_rev)) return (false); if (desc->m.match.core_class && desc->core_class != bhnd_core_class(core)) return (false); return true; } /** * Return true if the @p chip matches @p desc. * * @param chip A bhnd chip identifier. * @param desc A match descriptor to compare against @p chip. * * @retval true if @p chip matches @p match * @retval false if @p chip does not match @p match. */ bool bhnd_chip_matches(const struct bhnd_chipid *chip, const struct bhnd_chip_match *desc) { if (desc->m.match.chip_id && chip->chip_id != desc->chip_id) return (false); if (desc->m.match.chip_pkg && chip->chip_pkg != desc->chip_pkg) return (false); if (desc->m.match.chip_rev && !bhnd_hwrev_matches(chip->chip_rev, &desc->chip_rev)) return (false); return (true); } /** * Return true if the @p board matches @p desc. * * @param board The bhnd board info. * @param desc A match descriptor to compare against @p board. * * @retval true if @p chip matches @p match * @retval false if @p chip does not match @p match. */ bool bhnd_board_matches(const struct bhnd_board_info *board, const struct bhnd_board_match *desc) { if (desc->m.match.board_srom_rev && !bhnd_hwrev_matches(board->board_srom_rev, &desc->board_srom_rev)) return (false); if (desc->m.match.board_vendor && board->board_vendor != desc->board_vendor) return (false); if (desc->m.match.board_type && board->board_type != desc->board_type) return (false); if (desc->m.match.board_rev && !bhnd_hwrev_matches(board->board_rev, &desc->board_rev)) return (false); return (true); } /** * Return true if the @p hwrev matches @p desc. * * @param hwrev A bhnd hardware revision. * @param desc A match descriptor to compare against @p core. * * @retval true if @p hwrev matches @p match * @retval false if @p hwrev does not match @p match. */ bool bhnd_hwrev_matches(uint16_t hwrev, const struct bhnd_hwrev_match *desc) { if (desc->start != BHND_HWREV_INVALID && desc->start > hwrev) return false; if (desc->end != BHND_HWREV_INVALID && desc->end < hwrev) return false; return true; } /** * Return true if the @p dev matches @p desc. * * @param dev A bhnd device. * @param desc A match descriptor to compare against @p dev. * * @retval true if @p dev matches @p match * @retval false if @p dev does not match @p match. */ bool bhnd_device_matches(device_t dev, const struct bhnd_device_match *desc) { struct bhnd_core_info core; const struct bhnd_chipid *chip; struct bhnd_board_info board; device_t parent; int error; /* Construct individual match descriptors */ struct bhnd_core_match m_core = { _BHND_CORE_MATCH_COPY(desc) }; struct bhnd_chip_match m_chip = { _BHND_CHIP_MATCH_COPY(desc) }; struct bhnd_board_match m_board = { _BHND_BOARD_MATCH_COPY(desc) }; /* Fetch and match core info */ if (m_core.m.match_flags) { /* Only applicable to bhnd-attached cores */ parent = device_get_parent(dev); if (device_get_devclass(parent) != bhnd_devclass) { device_printf(dev, "attempting to match core " "attributes against non-core device\n"); return (false); } core = bhnd_get_core_info(dev); if (!bhnd_core_matches(&core, &m_core)) return (false); } /* Fetch and match chip info */ if (m_chip.m.match_flags) { chip = bhnd_get_chipid(dev); if (!bhnd_chip_matches(chip, &m_chip)) return (false); } /* Fetch and match board info. * * This is not available until after NVRAM is up; earlier device * matches should not include board requirements */ if (m_board.m.match_flags) { if ((error = bhnd_read_board_info(dev, &board))) { device_printf(dev, "failed to read required board info " "during device matching: %d\n", error); return (false); } if (!bhnd_board_matches(&board, &m_board)) return (false); } /* All matched */ return (true); } /** * Search @p table for an entry matching @p dev. * * @param dev A bhnd device to match against @p table. * @param table The device table to search. * @param entry_size The @p table entry size, in bytes. * * @retval bhnd_device the first matching device, if any. * @retval NULL if no matching device is found in @p table. */ const struct bhnd_device * bhnd_device_lookup(device_t dev, const struct bhnd_device *table, size_t entry_size) { const struct bhnd_device *entry; device_t hostb, parent; bhnd_attach_type attach_type; uint32_t dflags; parent = device_get_parent(dev); hostb = bhnd_find_hostb_device(parent); attach_type = bhnd_get_attach_type(dev); for (entry = table; !BHND_DEVICE_IS_END(entry); entry = (const struct bhnd_device *) ((const char *) entry + entry_size)) { /* match core info */ if (!bhnd_device_matches(dev, &entry->core)) continue; /* match device flags */ dflags = entry->device_flags; /* hostb implies BHND_ATTACH_ADAPTER requirement */ if (dflags & BHND_DF_HOSTB) dflags |= BHND_DF_ADAPTER; if (dflags & BHND_DF_ADAPTER) if (attach_type != BHND_ATTACH_ADAPTER) continue; if (dflags & BHND_DF_HOSTB) if (dev != hostb) continue; if (dflags & BHND_DF_SOC) if (attach_type != BHND_ATTACH_NATIVE) continue; /* device found */ return (entry); } /* not found */ return (NULL); } /** * Scan the device @p table for all quirk flags applicable to @p dev. * * @param dev A bhnd device to match against @p table. * @param table The device table to search. * * @return returns all matching quirk flags. */ uint32_t bhnd_device_quirks(device_t dev, const struct bhnd_device *table, size_t entry_size) { const struct bhnd_device *dent; const struct bhnd_device_quirk *qent, *qtable; uint32_t quirks; /* Locate the device entry */ if ((dent = bhnd_device_lookup(dev, table, entry_size)) == NULL) return (0); /* Quirks table is optional */ qtable = dent->quirks_table; if (qtable == NULL) return (0); /* Collect matching device quirk entries */ quirks = 0; for (qent = qtable; !BHND_DEVICE_QUIRK_IS_END(qent); qent++) { if (bhnd_device_matches(dev, &qent->desc)) quirks |= qent->quirks; } return (quirks); } /** * Allocate bhnd(4) resources defined in @p rs from a parent bus. * * @param dev The device requesting ownership of the resources. * @param rs A standard bus resource specification. This will be updated * with the allocated resource's RIDs. * @param res On success, the allocated bhnd resources. * * @retval 0 success * @retval non-zero if allocation of any non-RF_OPTIONAL resource fails, * all allocated resources will be released and a regular * unix error code will be returned. */ int bhnd_alloc_resources(device_t dev, struct resource_spec *rs, struct bhnd_resource **res) { /* Initialize output array */ for (u_int i = 0; rs[i].type != -1; i++) res[i] = NULL; for (u_int i = 0; rs[i].type != -1; i++) { res[i] = bhnd_alloc_resource_any(dev, rs[i].type, &rs[i].rid, rs[i].flags); /* Clean up all allocations on failure */ if (res[i] == NULL && !(rs[i].flags & RF_OPTIONAL)) { bhnd_release_resources(dev, rs, res); return (ENXIO); } } return (0); }; /** * Release bhnd(4) resources defined in @p rs from a parent bus. * * @param dev The device that owns the resources. * @param rs A standard bus resource specification previously initialized * by @p bhnd_alloc_resources. * @param res The bhnd resources to be released. */ void bhnd_release_resources(device_t dev, const struct resource_spec *rs, struct bhnd_resource **res) { for (u_int i = 0; rs[i].type != -1; i++) { if (res[i] == NULL) continue; bhnd_release_resource(dev, rs[i].type, rs[i].rid, res[i]); res[i] = NULL; } } /** * Parse the CHIPC_ID_* fields from the ChipCommon CHIPC_ID * register, returning its bhnd_chipid representation. * * @param idreg The CHIPC_ID register value. * @param enum_addr The enumeration address to include in the result. * * @warning * On early siba(4) devices, the ChipCommon core does not provide * a valid CHIPC_ID_NUMCORE field. On these ChipCommon revisions * (see CHIPC_NCORES_MIN_HWREV()), this function will parse and return * an invalid `ncores` value. */ struct bhnd_chipid bhnd_parse_chipid(uint32_t idreg, bhnd_addr_t enum_addr) { struct bhnd_chipid result; /* Fetch the basic chip info */ result.chip_id = CHIPC_GET_BITS(idreg, CHIPC_ID_CHIP); result.chip_pkg = CHIPC_GET_BITS(idreg, CHIPC_ID_PKG); result.chip_rev = CHIPC_GET_BITS(idreg, CHIPC_ID_REV); result.chip_type = CHIPC_GET_BITS(idreg, CHIPC_ID_BUS); result.ncores = CHIPC_GET_BITS(idreg, CHIPC_ID_NUMCORE); result.enum_addr = enum_addr; return (result); } /** * Allocate the resource defined by @p rs via @p dev, use it * to read the ChipCommon ID register relative to @p chipc_offset, * then release the resource. * * @param dev The device owning @p rs. * @param rs A resource spec that encompasses the ChipCommon register block. * @param chipc_offset The offset of the ChipCommon registers within @p rs. * @param[out] result the chip identification data. * * @retval 0 success * @retval non-zero if the ChipCommon identification data could not be read. */ int bhnd_read_chipid(device_t dev, struct resource_spec *rs, bus_size_t chipc_offset, struct bhnd_chipid *result) { struct resource *res; + bhnd_addr_t enum_addr; uint32_t reg; + uint8_t chip_type; int error, rid, rtype; - /* Allocate the ChipCommon window resource and fetch the chipid data */ rid = rs->rid; rtype = rs->type; + error = 0; + + /* Allocate the ChipCommon window resource and fetch the chipid data */ res = bus_alloc_resource_any(dev, rtype, &rid, RF_ACTIVE); if (res == NULL) { device_printf(dev, "failed to allocate bhnd chipc resource\n"); return (ENXIO); } /* Fetch the basic chip info */ reg = bus_read_4(res, chipc_offset + CHIPC_ID); - *result = bhnd_parse_chipid(reg, 0x0); + chip_type = CHIPC_GET_BITS(reg, CHIPC_ID_BUS); - /* Fetch the enum base address */ - error = 0; - switch (result->chip_type) { - case BHND_CHIPTYPE_SIBA: - result->enum_addr = BHND_DEFAULT_CHIPC_ADDR; - break; - case BHND_CHIPTYPE_BCMA: - case BHND_CHIPTYPE_BCMA_ALT: - result->enum_addr = bus_read_4(res, chipc_offset + - CHIPC_EROMPTR); - break; - case BHND_CHIPTYPE_UBUS: - device_printf(dev, "unsupported ubus/bcm63xx chip type"); + /* Fetch the EROMPTR */ + if (BHND_CHIPTYPE_HAS_EROM(chip_type)) { + enum_addr = bus_read_4(res, chipc_offset + CHIPC_EROMPTR); + } else if (chip_type == BHND_CHIPTYPE_SIBA) { + /* siba(4) uses the ChipCommon base address as the enumeration + * address */ + enum_addr = rman_get_start(res) + chipc_offset; + } else { + device_printf(dev, "unknown chip type %hhu\n", chip_type); error = ENODEV; goto cleanup; - default: - device_printf(dev, "unknown chip type %hhu\n", - result->chip_type); - error = ENODEV; - goto cleanup; } + + *result = bhnd_parse_chipid(reg, enum_addr); cleanup: /* Clean up */ bus_release_resource(dev, rtype, rid, res); return (error); } /** * Read an NVRAM variable's NUL-terminated string value. * * @param dev A bhnd bus child device. * @param name The NVRAM variable name. * @param[out] buf A buffer large enough to hold @p len bytes. On * success, the NUL-terminated string value will be * written to this buffer. This argment may be NULL if * the value is not desired. * @param len The maximum capacity of @p buf. * @param[out] rlen On success, will be set to the actual size of * the requested value (including NUL termination). This * argment may be NULL if the size is not desired. * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENODEV No valid NVRAM source could be found. * @retval ENOMEM If @p buf is non-NULL and a buffer of @p len is too * small to hold the requested value. * @retval EFTYPE If the variable data cannot be coerced to a valid * string representation. * @retval ERANGE If value coercion would overflow @p type. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ int bhnd_nvram_getvar_str(device_t dev, const char *name, char *buf, size_t len, size_t *rlen) { size_t larg; int error; larg = len; error = bhnd_nvram_getvar(dev, name, buf, &larg, BHND_NVRAM_TYPE_CSTR); if (rlen != NULL) *rlen = larg; return (error); } /** * Read an NVRAM variable's unsigned integer value. * * @param dev A bhnd bus child device. * @param name The NVRAM variable name. * @param[out] value On success, the requested value will be written * to this pointer. * @param width The output integer type width (1, 2, or * 4 bytes). * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENODEV No valid NVRAM source could be found. * @retval EFTYPE If the variable data cannot be coerced to a * a valid unsigned integer representation. * @retval ERANGE If value coercion would overflow (or underflow) an * unsigned representation of the given @p width. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ int bhnd_nvram_getvar_uint(device_t dev, const char *name, void *value, int width) { bhnd_nvram_type type; size_t len; switch (width) { case 1: type = BHND_NVRAM_TYPE_UINT8; break; case 2: type = BHND_NVRAM_TYPE_UINT16; break; case 4: type = BHND_NVRAM_TYPE_UINT32; break; default: device_printf(dev, "unsupported NVRAM integer width: %d\n", width); return (EINVAL); } len = width; return (bhnd_nvram_getvar(dev, name, value, &len, type)); } /** * Read an NVRAM variable's unsigned 8-bit integer value. * * @param dev A bhnd bus child device. * @param name The NVRAM variable name. * @param[out] value On success, the requested value will be written * to this pointer. * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENODEV No valid NVRAM source could be found. * @retval EFTYPE If the variable data cannot be coerced to a * a valid unsigned integer representation. * @retval ERANGE If value coercion would overflow (or underflow) uint8_t. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ int bhnd_nvram_getvar_uint8(device_t dev, const char *name, uint8_t *value) { return (bhnd_nvram_getvar_uint(dev, name, value, sizeof(*value))); } /** * Read an NVRAM variable's unsigned 16-bit integer value. * * @param dev A bhnd bus child device. * @param name The NVRAM variable name. * @param[out] value On success, the requested value will be written * to this pointer. * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENODEV No valid NVRAM source could be found. * @retval EFTYPE If the variable data cannot be coerced to a * a valid unsigned integer representation. * @retval ERANGE If value coercion would overflow (or underflow) * uint16_t. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ int bhnd_nvram_getvar_uint16(device_t dev, const char *name, uint16_t *value) { return (bhnd_nvram_getvar_uint(dev, name, value, sizeof(*value))); } /** * Read an NVRAM variable's unsigned 32-bit integer value. * * @param dev A bhnd bus child device. * @param name The NVRAM variable name. * @param[out] value On success, the requested value will be written * to this pointer. * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENODEV No valid NVRAM source could be found. * @retval EFTYPE If the variable data cannot be coerced to a * a valid unsigned integer representation. * @retval ERANGE If value coercion would overflow (or underflow) * uint32_t. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ int bhnd_nvram_getvar_uint32(device_t dev, const char *name, uint32_t *value) { return (bhnd_nvram_getvar_uint(dev, name, value, sizeof(*value))); } /** * Read an NVRAM variable's signed integer value. * * @param dev A bhnd bus child device. * @param name The NVRAM variable name. * @param[out] value On success, the requested value will be written * to this pointer. * @param width The output integer type width (1, 2, or * 4 bytes). * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENODEV No valid NVRAM source could be found. * @retval EFTYPE If the variable data cannot be coerced to a * a valid integer representation. * @retval ERANGE If value coercion would overflow (or underflow) an * signed representation of the given @p width. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ int bhnd_nvram_getvar_int(device_t dev, const char *name, void *value, int width) { bhnd_nvram_type type; size_t len; switch (width) { case 1: type = BHND_NVRAM_TYPE_INT8; break; case 2: type = BHND_NVRAM_TYPE_INT16; break; case 4: type = BHND_NVRAM_TYPE_INT32; break; default: device_printf(dev, "unsupported NVRAM integer width: %d\n", width); return (EINVAL); } len = width; return (bhnd_nvram_getvar(dev, name, value, &len, type)); } /** * Read an NVRAM variable's signed 8-bit integer value. * * @param dev A bhnd bus child device. * @param name The NVRAM variable name. * @param[out] value On success, the requested value will be written * to this pointer. * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENODEV No valid NVRAM source could be found. * @retval EFTYPE If the variable data cannot be coerced to a * a valid integer representation. * @retval ERANGE If value coercion would overflow (or underflow) int8_t. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ int bhnd_nvram_getvar_int8(device_t dev, const char *name, int8_t *value) { return (bhnd_nvram_getvar_int(dev, name, value, sizeof(*value))); } /** * Read an NVRAM variable's signed 16-bit integer value. * * @param dev A bhnd bus child device. * @param name The NVRAM variable name. * @param[out] value On success, the requested value will be written * to this pointer. * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENODEV No valid NVRAM source could be found. * @retval EFTYPE If the variable data cannot be coerced to a * a valid integer representation. * @retval ERANGE If value coercion would overflow (or underflow) * int16_t. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ int bhnd_nvram_getvar_int16(device_t dev, const char *name, int16_t *value) { return (bhnd_nvram_getvar_int(dev, name, value, sizeof(*value))); } /** * Read an NVRAM variable's signed 32-bit integer value. * * @param dev A bhnd bus child device. * @param name The NVRAM variable name. * @param[out] value On success, the requested value will be written * to this pointer. * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENODEV No valid NVRAM source could be found. * @retval EFTYPE If the variable data cannot be coerced to a * a valid integer representation. * @retval ERANGE If value coercion would overflow (or underflow) * int32_t. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ int bhnd_nvram_getvar_int32(device_t dev, const char *name, int32_t *value) { return (bhnd_nvram_getvar_int(dev, name, value, sizeof(*value))); } /** * Read an NVRAM variable's array value. * * @param dev A bhnd bus child device. * @param name The NVRAM variable name. * @param[out] buf A buffer large enough to hold @p size bytes. * On success, the requested value will be written * to this buffer. * @param[in,out] size The required number of bytes to write to * @p buf. * @param type The desired array element data representation. * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENODEV No valid NVRAM source could be found. * @retval ENXIO If less than @p size bytes are available. * @retval ENOMEM If a buffer of @p size is too small to hold the * requested value. * @retval EFTYPE If the variable data cannot be coerced to a * a valid instance of @p type. * @retval ERANGE If value coercion would overflow (or underflow) a * representation of @p type. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ int bhnd_nvram_getvar_array(device_t dev, const char *name, void *buf, size_t size, bhnd_nvram_type type) { size_t nbytes; int error; /* Attempt read */ nbytes = size; if ((error = bhnd_nvram_getvar(dev, name, buf, &nbytes, type))) return (error); /* Verify that the expected number of bytes were fetched */ if (nbytes < size) return (ENXIO); return (0); } /** * Using the bhnd(4) bus-level core information and a custom core name, * populate @p dev's device description. * * @param dev A bhnd-bus attached device. * @param dev_name The core's name (e.g. "SDIO Device Core") */ void bhnd_set_custom_core_desc(device_t dev, const char *dev_name) { const char *vendor_name; char *desc; vendor_name = bhnd_get_vendor_name(dev); asprintf(&desc, M_BHND, "%s %s, rev %hhu", vendor_name, dev_name, bhnd_get_hwrev(dev)); if (desc != NULL) { device_set_desc_copy(dev, desc); free(desc, M_BHND); } else { device_set_desc(dev, dev_name); } } /** * Using the bhnd(4) bus-level core information, populate @p dev's device * description. * * @param dev A bhnd-bus attached device. */ void bhnd_set_default_core_desc(device_t dev) { bhnd_set_custom_core_desc(dev, bhnd_get_device_name(dev)); } /** * Helper function for implementing BHND_BUS_IS_HW_DISABLED(). * * If a parent device is available, this implementation delegates the * request to the BHND_BUS_IS_HW_DISABLED() method on the parent of @p dev. * * If no parent device is available (i.e. on a the bus root), the hardware * is assumed to be usable and false is returned. */ bool bhnd_bus_generic_is_hw_disabled(device_t dev, device_t child) { if (device_get_parent(dev) != NULL) return (BHND_BUS_IS_HW_DISABLED(device_get_parent(dev), child)); return (false); } /** * Helper function for implementing BHND_BUS_GET_CHIPID(). * * This implementation delegates the request to the BHND_BUS_GET_CHIPID() * method on the parent of @p dev. If no parent exists, the implementation * will panic. */ const struct bhnd_chipid * bhnd_bus_generic_get_chipid(device_t dev, device_t child) { if (device_get_parent(dev) != NULL) return (BHND_BUS_GET_CHIPID(device_get_parent(dev), child)); panic("missing BHND_BUS_GET_CHIPID()"); } /* nvram board_info population macros for bhnd_bus_generic_read_board_info() */ #define BHND_GV(_dest, _name) \ bhnd_nvram_getvar_uint(child, BHND_NVAR_ ## _name, &_dest, \ sizeof(_dest)) #define REQ_BHND_GV(_dest, _name) do { \ if ((error = BHND_GV(_dest, _name))) { \ device_printf(dev, \ "error reading " __STRING(_name) ": %d\n", error); \ return (error); \ } \ } while(0) #define OPT_BHND_GV(_dest, _name, _default) do { \ if ((error = BHND_GV(_dest, _name))) { \ if (error != ENOENT) { \ device_printf(dev, \ "error reading " \ __STRING(_name) ": %d\n", error); \ return (error); \ } \ _dest = _default; \ } \ } while(0) /** * Helper function for implementing BHND_BUS_READ_BOARDINFO(). * * This implementation populates @p info with information from NVRAM, * defaulting board_vendor and board_type fields to 0 if the * requested variables cannot be found. * * This behavior is correct for most SoCs, but must be overridden on * bridged (PCI, PCMCIA, etc) devices to produce a complete bhnd_board_info * result. */ int bhnd_bus_generic_read_board_info(device_t dev, device_t child, struct bhnd_board_info *info) { int error; OPT_BHND_GV(info->board_vendor, BOARDVENDOR, 0); OPT_BHND_GV(info->board_type, BOARDTYPE, 0); /* srom >= 2 */ REQ_BHND_GV(info->board_rev, BOARDREV); REQ_BHND_GV(info->board_srom_rev,SROMREV); REQ_BHND_GV(info->board_flags, BOARDFLAGS); OPT_BHND_GV(info->board_flags2, BOARDFLAGS2, 0); /* srom >= 4 */ OPT_BHND_GV(info->board_flags3, BOARDFLAGS3, 0); /* srom >= 11 */ return (0); } #undef BHND_GV #undef BHND_GV_REQ #undef BHND_GV_OPT /** * Helper function for implementing BHND_BUS_GET_NVRAM_VAR(). * * This implementation searches @p dev for a usable NVRAM child device. * * If no usable child device is found on @p dev, the request is delegated to * the BHND_BUS_GET_NVRAM_VAR() method on the parent of @p dev. */ int bhnd_bus_generic_get_nvram_var(device_t dev, device_t child, const char *name, void *buf, size_t *size, bhnd_nvram_type type) { device_t nvram; device_t parent; /* Make sure we're holding Giant for newbus */ GIANT_REQUIRED; /* Look for a directly-attached NVRAM child */ if ((nvram = device_find_child(dev, "bhnd_nvram", -1)) != NULL) return BHND_NVRAM_GETVAR(nvram, name, buf, size, type); /* Try to delegate to parent */ if ((parent = device_get_parent(dev)) == NULL) return (ENODEV); return (BHND_BUS_GET_NVRAM_VAR(device_get_parent(dev), child, name, buf, size, type)); } /** * Helper function for implementing BHND_BUS_ALLOC_RESOURCE(). * * This implementation of BHND_BUS_ALLOC_RESOURCE() delegates allocation * of the underlying resource to BUS_ALLOC_RESOURCE(), and activation * to @p dev's BHND_BUS_ACTIVATE_RESOURCE(). */ struct bhnd_resource * bhnd_bus_generic_alloc_resource(device_t dev, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) { struct bhnd_resource *br; struct resource *res; int error; br = NULL; res = NULL; /* Allocate the real bus resource (without activating it) */ res = BUS_ALLOC_RESOURCE(dev, child, type, rid, start, end, count, (flags & ~RF_ACTIVE)); if (res == NULL) return (NULL); /* Allocate our bhnd resource wrapper. */ br = malloc(sizeof(struct bhnd_resource), M_BHND, M_NOWAIT); if (br == NULL) goto failed; br->direct = false; br->res = res; /* Attempt activation */ if (flags & RF_ACTIVE) { error = BHND_BUS_ACTIVATE_RESOURCE(dev, child, type, *rid, br); if (error) goto failed; } return (br); failed: if (res != NULL) BUS_RELEASE_RESOURCE(dev, child, type, *rid, res); free(br, M_BHND); return (NULL); } /** * Helper function for implementing BHND_BUS_RELEASE_RESOURCE(). * * This implementation of BHND_BUS_RELEASE_RESOURCE() delegates release of * the backing resource to BUS_RELEASE_RESOURCE(). */ int bhnd_bus_generic_release_resource(device_t dev, device_t child, int type, int rid, struct bhnd_resource *r) { int error; if ((error = BUS_RELEASE_RESOURCE(dev, child, type, rid, r->res))) return (error); free(r, M_BHND); return (0); } /** * Helper function for implementing BHND_BUS_ACTIVATE_RESOURCE(). * * This implementation of BHND_BUS_ACTIVATE_RESOURCE() simply calls the * BHND_BUS_ACTIVATE_RESOURCE() method of the parent of @p dev. */ int bhnd_bus_generic_activate_resource(device_t dev, device_t child, int type, int rid, struct bhnd_resource *r) { /* Try to delegate to the parent */ if (device_get_parent(dev) != NULL) return (BHND_BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child, type, rid, r)); return (EINVAL); }; /** * Helper function for implementing BHND_BUS_DEACTIVATE_RESOURCE(). * * This implementation of BHND_BUS_ACTIVATE_RESOURCE() simply calls the * BHND_BUS_ACTIVATE_RESOURCE() method of the parent of @p dev. */ int bhnd_bus_generic_deactivate_resource(device_t dev, device_t child, int type, int rid, struct bhnd_resource *r) { if (device_get_parent(dev) != NULL) return (BHND_BUS_DEACTIVATE_RESOURCE(device_get_parent(dev), child, type, rid, r)); return (EINVAL); }; Index: head/sys/dev/bhnd/cores/chipc/chipcreg.h =================================================================== --- head/sys/dev/bhnd/cores/chipc/chipcreg.h (revision 304858) +++ head/sys/dev/bhnd/cores/chipc/chipcreg.h (revision 304859) @@ -1,1543 +1,1553 @@ /*- * Copyright (c) 2015-2016 Landon Fuller * Copyright (c) 2010 Broadcom Corporation * All rights reserved. * * This file is derived from the sbchipc.h header distributed with * Broadcom's initial brcm80211 Linux driver release, as * contributed to the Linux staging repository. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ #ifndef _BHND_CORES_CHIPC_CHIPCREG_H_ #define _BHND_CORES_CHIPC_CHIPCREG_H_ #define CHIPC_CHIPID_SIZE 0x100 /**< size of the register block containing the chip identification registers required during bus enumeration */ /** Evaluates to true if the given ChipCommon core revision provides * the core count via the chip identification register. */ #define CHIPC_NCORES_MIN_HWREV(hwrev) ((hwrev) == 4 || (hwrev) >= 6) +/** Evaluates to true if the given ChipCommon core revision supports + * the CHIPC_CAPABILITIES_EXT register */ +#define CHIPC_HWREV_HAS_CAP_EXT(hwrev) ((hwrev) >= 35) + +/** Evaluates to true if the chipcommon core (determined from the provided + * @p _chipid (CHIPC_ID) register value) provides a pointer to the enumeration + * table via CHIPC_EROMPTR */ +#define CHIPC_HAS_EROMPTR(_chipid) \ + (CHIPC_GET_BITS((_chipid), CHIPC_ID_BUS) != BHND_CHIPTYPE_SIBA) + #define CHIPC_GET_FLAG(_value, _flag) (((_value) & _flag) != 0) #define CHIPC_GET_BITS(_value, _field) \ ((_value & _field ## _MASK) >> _field ## _SHIFT) #define CHIPC_ID 0x00 #define CHIPC_CAPABILITIES 0x04 #define CHIPC_CORECTRL 0x08 /* rev >= 1 */ #define CHIPC_BIST 0x0C #define CHIPC_OTPST 0x10 /**< otp status */ #define CHIPC_OTPCTRL 0x14 /**< otp control */ #define CHIPC_OTPPROG 0x18 #define CHIPC_OTPLAYOUT 0x1C /**< otp layout (IPX OTP) */ #define CHIPC_INTST 0x20 /**< interrupt status */ #define CHIPC_INTM 0x24 /**< interrupt mask */ #define CHIPC_CHIPCTRL 0x28 /**< chip control (rev >= 11) */ #define CHIPC_CHIPST 0x2C /**< chip status (rev >= 11) */ #define CHIPC_JTAGCMD 0x30 #define CHIPC_JTAGIR 0x34 #define CHIPC_JTAGDR 0x38 #define CHIPC_JTAGCTRL 0x3c #define CHIPC_SFLASH_BASE 0x40 #define CHIPC_SFLASH_SIZE 12 #define CHIPC_SFLASHCTRL 0x40 #define CHIPC_SFLASHADDR 0x44 #define CHIPC_SFLASHDATA 0x48 /* siba backplane configuration broadcast (siba-only) */ #define CHIPC_SBBCAST_ADDR 0x50 #define CHIPC_SBBCAST_DATA 0x54 #define CHIPC_GPIOPU 0x58 /**< pull-up mask (rev >= 20) */ #define CHIPC_GPIOPD 0x5C /**< pull down mask (rev >= 20) */ #define CHIPC_GPIOIN 0x60 #define CHIPC_GPIOOUT 0x64 #define CHIPC_GPIOOUTEN 0x68 #define CHIPC_GPIOCTRL 0x6C #define CHIPC_GPIOPOL 0x70 #define CHIPC_GPIOINTM 0x74 /**< gpio interrupt mask */ #define CHIPC_GPIOEVENT 0x78 /**< gpio event (rev >= 11) */ #define CHIPC_GPIOEVENT_INTM 0x7C /**< gpio event interrupt mask (rev >= 11) */ #define CHIPC_WATCHDOG 0x80 /**< watchdog timer */ #define CHIPC_GPIOEVENT_INTPOLARITY 0x84 /**< gpio even interrupt polarity (rev >= 11) */ #define CHIPC_GPIOTIMERVAL 0x88 /**< gpio-based LED duty cycle (rev >= 16) */ #define CHIPC_GPIOTIMEROUTMASK 0x8C /* clock control block */ #define CHIPC_CLKC_N 0x90 #define CHIPC_CLKC_SB 0x94 /* m0 (backplane) */ #define CHIPC_CLKC_PCI 0x98 /* m1 */ #define CHIPC_CLKC_M2 0x9C /* mii/uart/mipsref */ #define CHIPC_CLKC_M3 0xA0 /* cpu */ #define CHIPC_CLKDIV 0xA4 /* rev >= 3 */ #define CHIPC_GPIODEBUGSEL 0xA8 /* rev >= 28 */ #define CHIPC_CAPABILITIES_EXT 0xAC /* pll delay (registers rev >= 4) */ #define CHIPC_PLL_ON_DELAY 0xB0 #define CHIPC_PLL_FREFSEL_DELAY 0xB4 #define CHIPC_PLL_SLOWCLK_CTL 0xB8 /* revs 6-9 */ /* "instaclock" registers */ #define CHIPC_SYS_CLK_CTL 0xC0 /* rev >= 10 */ #define CHIPC_SYS_CLKSTATESTRETCH 0xC4 /* rev >= 10 */ /* indirect backplane access (rev >= 10) */ #define CHIPC_BP_ADDRLOW 0xD0 #define CHIPC_BP_ADDRHIGH 0xD4 #define CHIPC_BP_DATA 0xD8 #define CHIPC_BP_INDACCESS 0xE0 /* SPI/I2C (rev >= 37) */ #define CHIPC_GSIO_CTRL 0xE4 #define CHIPC_GSIO_ADDR 0xE8 #define CHIPC_GSIO_DATA 0xEC /* More clock dividers (corerev >= 32) */ #define CHIPC_CLKDIV2 0xF0 #define CHIPC_EROMPTR 0xFC /**< 32-bit EROM base address * on BCMA devices */ /* ExtBus control registers (rev >= 3) */ #define CHIPC_PCMCIA_CFG 0x100 #define CHIPC_PCMCIA_MEMWAIT 0x104 #define CHIPC_PCMCIA_ATTRWAIT 0x108 #define CHIPC_PCMCIA_IOWAIT 0x10C #define CHIPC_IDE_CFG 0x110 #define CHIPC_IDE_MEMWAIT 0x114 #define CHIPC_IDE_ATTRWAIT 0x118 #define CHIPC_IDE_IOWAIT 0x11C #define CHIPC_PROG_CFG 0x120 #define CHIPC_PROG_WAITCOUNT 0x124 #define CHIPC_FLASH_CFG 0x128 #define CHIPC_FLASH_WAITCOUNT 0x12C #define CHIPC_SECI_CFG 0x130 #define CHIPC_SECI_ST 0x134 #define CHIPC_SECI_STM 0x138 #define CHIPC_SECI_RXNBC 0x13C /* Enhanced Coexistence Interface (ECI) registers (rev 21-34) */ #define CHIPC_ECI_OUTPUT 0x140 #define CHIPC_ECI_CTRL 0x144 #define CHIPC_ECI_INPUTLO 0x148 #define CHIPC_ECI_INPUTMI 0x14C #define CHIPC_ECI_INPUTHI 0x150 #define CHIPC_ECI_INPUTINTPOLARITYLO 0x154 #define CHIPC_ECI_INPUTINTPOLARITYMI 0x158 #define CHIPC_ECI_INPUTINTPOLARITYHI 0x15C #define CHIPC_ECI_INTMASKLO 0x160 #define CHIPC_ECI_INTMASKMI 0x164 #define CHIPC_ECI_INTMASKHI 0x168 #define CHIPC_ECI_EVENTLO 0x16C #define CHIPC_ECI_EVENTMI 0x170 #define CHIPC_ECI_EVENTHI 0x174 #define CHIPC_ECI_EVENTMASKLO 0x178 #define CHIPC_ECI_EVENTMASKMI 0x17C #define CHIPC_ECI_EVENTMASKHI 0x180 #define CHIPC_FLASHSTRCFG 0x18C /**< BCM4706 NAND flash config */ #define CHIPC_SPROM_CTRL 0x190 /**< SPROM interface (rev >= 32) */ #define CHIPC_SPROM_ADDR 0x194 #define CHIPC_SPROM_DATA 0x198 /* Clock control and hardware workarounds (corerev >= 20) */ #define CHIPC_CLK_CTL_ST 0x1E0 #define CHIPC_SPROM_HWWAR 0x19 #define CHIPC_UART_BASE 0x300 #define CHIPC_UART_SIZE 0x100 #define CHIPC_UART_MAX 3 /**< max UART blocks */ #define CHIPC_UART(_n) (CHIPC_UART_BASE + (CHIPC_UART_SIZE*_n)) /* PMU registers (rev >= 20) */ #define CHIPC_PMU_BASE 0x600 #define CHIPC_PMU_SIZE 0x70 #define CHIPC_PMU_CTRL 0x600 #define CHIPC_PMU_CAP 0x604 #define CHIPC_PMU_ST 0x608 #define CHIPC_PMU_RES_STATE 0x60c #define CHIPC_PMU_RES_PENDING 0x610 #define CHIPC_PMU_TIMER 0x614 #define CHIPC_PMU_MIN_RES_MASK 0x618 #define CHIPC_PMU_MAX_RES_MASK 0x61c #define CHIPC_PMU_RES_TABLE_SEL 0x620 #define CHIPC_PMU_RES_DEP_MASK 0x624 #define CHIPC_PMU_RES_UPDN_TIMER 0x628 #define CHIPC_PMU_RES_TIMER 0x62C #define CHIPC_PMU_CLKSTRETCH 0x630 #define CHIPC_PMU_WATCHDOG 0x634 #define CHIPC_PMU_GPIOSEL 0x638 /* pmu rev >= 1 ? */ #define CHIPC_PMU_GPIOEN 0x63C /* pmu rev >= 1 ? */ #define CHIPC_PMU_RES_REQ_TIMER_SEL 0x640 #define CHIPC_PMU_RES_REQ_TIMER 0x644 #define CHIPC_PMU_RES_REQ_MASK 0x648 #define CHIPC_CHIPCTL_ADDR 0x650 #define CHIPC_CHIPCTL_DATA 0x654 #define CHIPC_PMU_REG_CONTROL_ADDR 0x658 #define CHIPC_PMU_REG_CONTROL_DATA 0x65C #define CHIPC_PMU_PLL_CONTROL_ADDR 0x660 #define CHIPC_PMU_PLL_CONTROL_DATA 0x664 #define CHIPC_PMU_STRAPOPT 0x668 /* chipc rev >= 28 */ #define CHIPC_PMU_XTALFREQ 0x66C /* pmu rev >= 10 */ #define CHIPC_SPROM_OTP 0x800 /* SPROM/OTP address space */ #define CHIPC_SPROM_OTP_SIZE 0x400 /** chipid */ #define CHIPC_ID_CHIP_MASK 0x0000FFFF /**< chip id */ #define CHIPC_ID_CHIP_SHIFT 0 #define CHIPC_ID_REV_MASK 0x000F0000 /**< chip revision */ #define CHIPC_ID_REV_SHIFT 16 #define CHIPC_ID_PKG_MASK 0x00F00000 /**< physical package ID */ #define CHIPC_ID_PKG_SHIFT 20 #define CHIPC_ID_NUMCORE_MASK 0x0F000000 /**< number of cores on chip (rev >= 4) */ #define CHIPC_ID_NUMCORE_SHIFT 24 #define CHIPC_ID_BUS_MASK 0xF0000000 /**< chip/interconnect type (BHND_CHIPTYPE_*) */ #define CHIPC_ID_BUS_SHIFT 28 /* capabilities */ #define CHIPC_CAP_NUM_UART_MASK 0x00000003 /* Number of UARTs (1-3) */ #define CHIPC_CAP_NUM_UART_SHIFT 0 #define CHIPC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */ #define CHIPC_CAP_UCLKSEL_MASK 0x00000018 /* UARTs clock select */ #define CHIPC_CAP_UCLKSEL_SHIFT 3 #define CHIPC_CAP_UCLKSEL_UINTCLK 0x1 /* UARTs are driven by internal divided clock */ #define CHIPC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */ #define CHIPC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */ #define CHIPC_CAP_EXTBUS_SHIFT 6 #define CHIPC_CAP_EXTBUS_NONE 0x0 /* No ExtBus present */ #define CHIPC_CAP_EXTBUS_FULL 0x1 /* ExtBus: PCMCIA, IDE & Prog */ #define CHIPC_CAP_EXTBUS_PROG 0x2 /* ExtBus: ProgIf only */ #define CHIPC_CAP_FLASH_MASK 0x00000700 /* Type of flash */ #define CHIPC_CAP_FLASH_SHIFT 8 #define CHIPC_CAP_FLASH_NONE 0x0 /* No flash */ #define CHIPC_CAP_SFLASH_ST 0x1 /* ST serial flash */ #define CHIPC_CAP_SFLASH_AT 0x2 /* Atmel serial flash */ #define CHIPC_CAP_NFLASH 0x3 /* NAND flash */ #define CHIPC_CAP_PFLASH 0x7 /* Parallel flash */ #define CHIPC_CAP_PLL_MASK 0x00038000 /* Type of PLL */ #define CHIPC_CAP_PLL_SHIFT 15 #define CHIPC_CAP_PWR_CTL 0x00040000 /* Power control */ #define CHIPC_CAP_OTP_SIZE_MASK 0x00380000 /* OTP Size (0 = none) */ #define CHIPC_CAP_OTP_SIZE_SHIFT 19 /* OTP Size shift */ #define CHIPC_CAP_OTP_SIZE_BASE 5 /* OTP Size base */ #define CHIPC_CAP_JTAGP 0x00400000 /* JTAG Master Present */ #define CHIPC_CAP_ROM 0x00800000 /* Internal boot rom active */ #define CHIPC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */ #define CHIPC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */ #define CHIPC_CAP_ECI 0x20000000 /* Enhanced Coexistence Interface */ #define CHIPC_CAP_SPROM 0x40000000 /* SPROM Present, rev >= 32 */ #define CHIPC_CAP_4706_NFLASH 0x80000000 /* NAND flash present, BCM4706 or chipc rev38 (BCM5357)? */ #define CHIPC_CAP2_SECI 0x00000001 /* SECI Present, rev >= 36 */ #define CHIPC_CAP2_GSIO 0x00000002 /* GSIO (spi/i2c) present, rev >= 37 */ #define CHIPC_CAP2_GCI 0x00000004 /* GCI present (rev >= ??) */ #define CHIPC_CAP2_AOB 0x00000040 /* Always on Bus present (rev >= 49) * * If set, PMU and GCI registers * are found in dedicated cores. * * This appears to be a lower power * APB bus, bridged via ARM APB IP. */ /* * ChipStatus (Common) */ /** ChipStatus CIS/OTP/SPROM values used to advertise OTP/SPROM availability in * chipcommon revs 11-31. */ enum { CHIPC_CST_DEFCIS_SEL = 0, /**< OTP is powered up, use default CIS, no SPROM */ CHIPC_CST_SPROM_SEL = 1, /**< OTP is powered up, SPROM is present */ CHIPC_CST_OTP_SEL = 2, /**< OTP is powered up, no SPROM */ CHIPC_CST_OTP_PWRDN = 3 /**< OTP is powered down, SPROM is present (rev <= 22 only) */ }; #define CHIPC_CST_SPROM_OTP_SEL_R22_MASK 0x00000003 /**< chipstatus OTP/SPROM SEL value (rev 22) */ #define CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT 0 #define CHIPC_CST_SPROM_OTP_SEL_R23_MASK 0x000000c0 /**< chipstatus OTP/SPROM SEL value (revs 23-31) * * it is unknown whether this is supported on * any CC revs >= 32 that also vend CHIPC_CAP_* * constants for OTP/SPROM/NVRAM availability. */ #define CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT 6 /* PLL type */ #define CHIPC_PLL_NONE 0x00000000 #define CHIPC_PLL_TYPE1 0x00010000 /* 48MHz base, 3 dividers */ #define CHIPC_PLL_TYPE2 0x00020000 /* 48MHz, 4 dividers */ #define CHIPC_PLL_TYPE3 0x00030000 /* 25MHz, 2 dividers */ #define CHIPC_PLL_TYPE4 0x00008000 /* 48MHz, 4 dividers */ #define CHIPC_PLL_TYPE5 0x00018000 /* 25MHz, 4 dividers */ #define CHIPC_PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */ #define CHIPC_PLL_TYPE7 0x00038000 /* 25MHz, 4 dividers */ /* ILP clock */ #define CHIPC_ILP_CLOCK 32000 /* ALP clock on pre-PMU chips */ #define CHIPC_ALP_CLOCK 20000000 /* HT clock */ #define CHIPC_HT_CLOCK 80000000 /* corecontrol */ #define CHIPC_UARTCLKO 0x00000001 /* Drive UART with internal clock */ #define CHIPC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ #define CHIPC_UARTCLKEN 0x00000008 /* enable UART Clock (corerev > = 21 */ /* chipcontrol */ #define CHIPCTRL_4321A0_DEFAULT 0x3a4 #define CHIPCTRL_4321A1_DEFAULT 0x0a4 #define CHIPCTRL_4321_PLL_DOWN 0x800000 /* serdes PLL down override */ /* Fields in the otpstatus register in rev >= 21 */ #define CHIPC_OTPS_OL_MASK 0x000000ff #define CHIPC_OTPS_OL_MFG 0x00000001 /* manuf row is locked */ #define CHIPC_OTPS_OL_OR1 0x00000002 /* otp redundancy row 1 is locked */ #define CHIPC_OTPS_OL_OR2 0x00000004 /* otp redundancy row 2 is locked */ #define CHIPC_OTPS_OL_GU 0x00000008 /* general use region is locked */ #define CHIPC_OTPS_GUP_MASK 0x00000f00 #define CHIPC_OTPS_GUP_SHIFT 8 #define CHIPC_OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */ #define CHIPC_OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */ #define CHIPC_OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */ #define CHIPC_OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */ #define CHIPC_OTPS_READY 0x00001000 #define CHIPC_OTPS_RV(x) (1 << (16 + (x))) /* redundancy entry valid */ #define CHIPC_OTPS_RV_MASK 0x0fff0000 /* IPX OTP fields in the otpcontrol register */ #define CHIPC_OTPC_PROGSEL 0x00000001 #define CHIPC_OTPC_PCOUNT_MASK 0x0000000e #define CHIPC_OTPC_PCOUNT_SHIFT 1 #define CHIPC_OTPC_VSEL_MASK 0x000000f0 #define CHIPC_OTPC_VSEL_SHIFT 4 #define CHIPC_OTPC_TMM_MASK 0x00000700 #define CHIPC_OTPC_TMM_SHIFT 8 #define CHIPC_OTPC_ODM 0x00000800 #define CHIPC_OTPC_PROGEN 0x80000000 /* Fields in otpprog in IPX OTP and HND OTP */ #define CHIPC_OTPP_COL_MASK 0x000000ff #define CHIPC_OTPP_COL_SHIFT 0 #define CHIPC_OTPP_ROW_MASK 0x0000ff00 #define CHIPC_OTPP_ROW_SHIFT 8 #define CHIPC_OTPP_OC_MASK 0x0f000000 #define CHIPC_OTPP_OC_SHIFT 24 #define CHIPC_OTPP_READERR 0x10000000 #define CHIPC_OTPP_VALUE_MASK 0x20000000 #define CHIPC_OTPP_VALUE_SHIFT 29 #define CHIPC_OTPP_START_BUSY 0x80000000 #define CHIPC_OTPP_READ 0x40000000 /* HND OTP */ /* otplayout */ #define CHIPC_OTPL_SIZE_MASK 0x0000f000 /* rev >= 49 */ #define CHIPC_OTPL_SIZE_SHIFT 12 #define CHIPC_OTPL_GUP_MASK 0x00000FFF /* bit offset to general use region */ #define CHIPC_OTPL_GUP_SHIFT 0 #define CHIPC_OTPL_CISFORMAT_NEW 0x80000000 /* rev >= 36 */ /* Opcodes for OTPP_OC field */ #define CHIPC_OTPPOC_READ 0 #define CHIPC_OTPPOC_BIT_PROG 1 #define CHIPC_OTPPOC_VERIFY 3 #define CHIPC_OTPPOC_INIT 4 #define CHIPC_OTPPOC_SET 5 #define CHIPC_OTPPOC_RESET 6 #define CHIPC_OTPPOC_OCST 7 #define CHIPC_OTPPOC_ROW_LOCK 8 #define CHIPC_OTPPOC_PRESCN_TEST 9 /* Jtagm characteristics that appeared at a given corerev */ #define CHIPC_JTAGM_CREV_OLD 10 /* Old command set, 16bit max IR */ #define CHIPC_JTAGM_CREV_IRP 22 /* Able to do pause-ir */ #define CHIPC_JTAGM_CREV_RTI 28 /* Able to do return-to-idle */ /* jtagcmd */ #define CHIPC_JCMD_START 0x80000000 #define CHIPC_JCMD_BUSY 0x80000000 #define CHIPC_JCMD_STATE_MASK 0x60000000 #define CHIPC_JCMD_STATE_TLR 0x00000000 /* Test-logic-reset */ #define CHIPC_JCMD_STATE_PIR 0x20000000 /* Pause IR */ #define CHIPC_JCMD_STATE_PDR 0x40000000 /* Pause DR */ #define CHIPC_JCMD_STATE_RTI 0x60000000 /* Run-test-idle */ #define CHIPC_JCMD0_ACC_MASK 0x0000f000 #define CHIPC_JCMD0_ACC_IRDR 0x00000000 #define CHIPC_JCMD0_ACC_DR 0x00001000 #define CHIPC_JCMD0_ACC_IR 0x00002000 #define CHIPC_JCMD0_ACC_RESET 0x00003000 #define CHIPC_JCMD0_ACC_IRPDR 0x00004000 #define CHIPC_JCMD0_ACC_PDR 0x00005000 #define CHIPC_JCMD0_IRW_MASK 0x00000f00 #define CHIPC_JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */ #define CHIPC_JCMD_ACC_IRDR 0x00000000 #define CHIPC_JCMD_ACC_DR 0x00010000 #define CHIPC_JCMD_ACC_IR 0x00020000 #define CHIPC_JCMD_ACC_RESET 0x00030000 #define CHIPC_JCMD_ACC_IRPDR 0x00040000 #define CHIPC_JCMD_ACC_PDR 0x00050000 #define CHIPC_JCMD_ACC_PIR 0x00060000 #define CHIPC_JCMD_ACC_IRDR_I 0x00070000 /* rev 28: return to run-test-idle */ #define CHIPC_JCMD_ACC_DR_I 0x00080000 /* rev 28: return to run-test-idle */ #define CHIPC_JCMD_IRW_MASK 0x00001f00 #define CHIPC_JCMD_IRW_SHIFT 8 #define CHIPC_JCMD_DRW_MASK 0x0000003f /* jtagctrl */ #define CHIPC_JCTRL_FORCE_CLK 4 /* Force clock */ #define CHIPC_JCTRL_EXT_EN 2 /* Enable external targets */ #define CHIPC_JCTRL_EN 1 /* Enable Jtag master */ /* Fields in clkdiv */ #define CHIPC_CLKD_SFLASH 0x0f000000 #define CHIPC_CLKD_SFLASH_SHIFT 24 #define CHIPC_CLKD_OTP 0x000f0000 #define CHIPC_CLKD_OTP_SHIFT 16 #define CHIPC_CLKD_JTAG 0x00000f00 #define CHIPC_CLKD_JTAG_SHIFT 8 #define CHIPC_CLKD_UART 0x000000ff #define CHIPC_CLKD2_SPROM 0x00000003 /* intstatus/intmask */ #define CHIPC_CI_GPIO 0x00000001 /* gpio intr */ #define CHIPC_CI_EI 0x00000002 /* extif intr (corerev >= 3) */ #define CHIPC_CI_TEMP 0x00000004 /* temp. ctrl intr (corerev >= 15) */ #define CHIPC_CI_SIRQ 0x00000008 /* serial IRQ intr (corerev >= 15) */ #define CHIPC_CI_PMU 0x00000020 /* pmu intr (corerev >= 21) */ #define CHIPC_CI_UART 0x00000040 /* uart intr (corerev >= 21) */ #define CHIPC_CI_WDRESET 0x80000000 /* watchdog reset occurred */ /* slow_clk_ctl */ #define CHIPC_SCC_SS_MASK 0x00000007 /* slow clock source mask */ #define CHIPC_SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */ #define CHIPC_SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */ #define CHIPC_SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */ #define CHIPC_SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */ #define CHIPC_SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, * 0: LPO is enabled */ #define CHIPC_SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, * 0: power logic control */ #define CHIPC_SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors * PLL clock disable requests from core */ #define CHIPC_SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't * disable crystal when appropriate */ #define CHIPC_SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */ #define CHIPC_SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */ #define CHIPC_SCC_CD_SHIFT 16 /* system_clk_ctl */ #define CHIPC_SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */ #define CHIPC_SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */ #define CHIPC_SYCC_FP 0x00000004 /* ForcePLLOn */ #define CHIPC_SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */ #define CHIPC_SYCC_HR 0x00000010 /* Force HT */ #define CHIPC_SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */ #define CHIPC_SYCC_CD_SHIFT 16 /* Indirect backplane access */ #define CHIPC_BPIA_BYTEEN 0x0000000f #define CHIPC_BPIA_SZ1 0x00000001 #define CHIPC_BPIA_SZ2 0x00000003 #define CHIPC_BPIA_SZ4 0x00000007 #define CHIPC_BPIA_SZ8 0x0000000f #define CHIPC_BPIA_WRITE 0x00000100 #define CHIPC_BPIA_START 0x00000200 #define CHIPC_BPIA_BUSY 0x00000200 #define CHIPC_BPIA_ERROR 0x00000400 /* pcmcia/prog/flash_config */ #define CHIPC_CF_EN 0x00000001 /* enable */ #define CHIPC_CF_EM_MASK 0x0000000e /* mode */ #define CHIPC_CF_EM_SHIFT 1 #define CHIPC_CF_EM_FLASH 0 /* flash/asynchronous mode */ #define CHIPC_CF_EM_SYNC 2 /* synchronous mode */ #define CHIPC_CF_EM_PCMCIA 4 /* pcmcia mode */ #define CHIPC_CF_DS 0x00000010 /* destsize: 0=8bit, 1=16bit */ #define CHIPC_CF_BS 0x00000020 /* byteswap */ #define CHIPC_CF_CD_MASK 0x000000c0 /* clock divider */ #define CHIPC_CF_CD_SHIFT 6 #define CHIPC_CF_CD_DIV2 0x00000000 /* backplane/2 */ #define CHIPC_CF_CD_DIV3 0x00000040 /* backplane/3 */ #define CHIPC_CF_CD_DIV4 0x00000080 /* backplane/4 */ #define CHIPC_CF_CE 0x00000100 /* clock enable */ #define CHIPC_CF_SB 0x00000200 /* size/bytestrobe (synch only) */ /* pcmcia_memwait */ #define CHIPC_PM_W0_MASK 0x0000003f /* waitcount0 */ #define CHIPC_PM_W1_MASK 0x00001f00 /* waitcount1 */ #define CHIPC_PM_W1_SHIFT 8 #define CHIPC_PM_W2_MASK 0x001f0000 /* waitcount2 */ #define CHIPC_PM_W2_SHIFT 16 #define CHIPC_PM_W3_MASK 0x1f000000 /* waitcount3 */ #define CHIPC_PM_W3_SHIFT 24 /* pcmcia_attrwait */ #define CHIPC_PA_W0_MASK 0x0000003f /* waitcount0 */ #define CHIPC_PA_W1_MASK 0x00001f00 /* waitcount1 */ #define CHIPC_PA_W1_SHIFT 8 #define CHIPC_PA_W2_MASK 0x001f0000 /* waitcount2 */ #define CHIPC_PA_W2_SHIFT 16 #define CHIPC_PA_W3_MASK 0x1f000000 /* waitcount3 */ #define CHIPC_PA_W3_SHIFT 24 /* pcmcia_iowait */ #define CHIPC_PI_W0_MASK 0x0000003f /* waitcount0 */ #define CHIPC_PI_W1_MASK 0x00001f00 /* waitcount1 */ #define CHIPC_PI_W1_SHIFT 8 #define CHIPC_PI_W2_MASK 0x001f0000 /* waitcount2 */ #define CHIPC_PI_W2_SHIFT 16 #define CHIPC_PI_W3_MASK 0x1f000000 /* waitcount3 */ #define CHIPC_PI_W3_SHIFT 24 /* prog_waitcount */ #define CHIPC_PW_W0_MASK 0x0000001f /* waitcount0 */ #define CHIPC_PW_W1_MASK 0x00001f00 /* waitcount1 */ #define CHIPC_PW_W1_SHIFT 8 #define CHIPC_PW_W2_MASK 0x001f0000 /* waitcount2 */ #define CHIPC_PW_W2_SHIFT 16 #define CHIPC_PW_W3_MASK 0x1f000000 /* waitcount3 */ #define CHIPC_PW_W3_SHIFT 24 #define CHIPC_PW_W0 0x0000000c #define CHIPC_PW_W1 0x00000a00 #define CHIPC_PW_W2 0x00020000 #define CHIPC_PW_W3 0x01000000 /* flash_waitcount */ #define CHIPC_FW_W0_MASK 0x0000003f /* waitcount0 */ #define CHIPC_FW_W1_MASK 0x00001f00 /* waitcount1 */ #define CHIPC_FW_W1_SHIFT 8 #define CHIPC_FW_W2_MASK 0x001f0000 /* waitcount2 */ #define CHIPC_FW_W2_SHIFT 16 #define CHIPC_FW_W3_MASK 0x1f000000 /* waitcount3 */ #define CHIPC_FW_W3_SHIFT 24 /* When SPROM support present, fields in spromcontrol */ #define CHIPC_SRC_START 0x80000000 #define CHIPC_SRC_BUSY 0x80000000 #define CHIPC_SRC_OPCODE 0x60000000 #define CHIPC_SRC_OP_READ 0x00000000 #define CHIPC_SRC_OP_WRITE 0x20000000 #define CHIPC_SRC_OP_WRDIS 0x40000000 #define CHIPC_SRC_OP_WREN 0x60000000 #define CHIPC_SRC_OTPSEL 0x00000010 #define CHIPC_SRC_LOCK 0x00000008 #define CHIPC_SRC_SIZE_MASK 0x00000006 #define CHIPC_SRC_SIZE_1K 0x00000000 #define CHIPC_SRC_SIZE_4K 0x00000002 #define CHIPC_SRC_SIZE_16K 0x00000004 #define CHIPC_SRC_SIZE_SHIFT 1 #define CHIPC_SRC_PRESENT 0x00000001 /* Fields in pmucontrol */ #define CHIPC_PCTL_ILP_DIV_MASK 0xffff0000 #define CHIPC_PCTL_ILP_DIV_SHIFT 16 #define CHIPC_PCTL_PLL_PLLCTL_UPD 0x00000400 /* rev 2 */ #define CHIPC_PCTL_NOILP_ON_WAIT 0x00000200 /* rev 1 */ #define CHIPC_PCTL_HT_REQ_EN 0x00000100 #define CHIPC_PCTL_ALP_REQ_EN 0x00000080 #define CHIPC_PCTL_XTALFREQ_MASK 0x0000007c #define CHIPC_PCTL_XTALFREQ_SHIFT 2 #define CHIPC_PCTL_ILP_DIV_EN 0x00000002 #define CHIPC_PCTL_LPO_SEL 0x00000001 /* Fields in clkstretch */ #define CHIPC_CSTRETCH_HT 0xffff0000 #define CHIPC_CSTRETCH_ALP 0x0000ffff /* gpiotimerval */ #define CHIPC_GPIO_ONTIME_SHIFT 16 /* clockcontrol_n */ #define CHIPC_CN_N1_MASK 0x3f /* n1 control */ #define CHIPC_CN_N2_MASK 0x3f00 /* n2 control */ #define CHIPC_CN_N2_SHIFT 8 #define CHIPC_CN_PLLC_MASK 0xf0000 /* pll control */ #define CHIPC_CN_PLLC_SHIFT 16 /* clockcontrol_sb/pci/uart */ #define CHIPC_M1_MASK 0x3f /* m1 control */ #define CHIPC_M2_MASK 0x3f00 /* m2 control */ #define CHIPC_M2_SHIFT 8 #define CHIPC_M3_MASK 0x3f0000 /* m3 control */ #define CHIPC_M3_SHIFT 16 #define CHIPC_MC_MASK 0x1f000000 /* mux control */ #define CHIPC_MC_SHIFT 24 /* N3M Clock control magic field values */ #define CHIPC_F6_2 0x02 /* A factor of 2 in */ #define CHIPC_F6_3 0x03 /* 6-bit fields like */ #define CHIPC_F6_4 0x05 /* N1, M1 or M3 */ #define CHIPC_F6_5 0x09 #define CHIPC_F6_6 0x11 #define CHIPC_F6_7 0x21 #define CHIPC_F5_BIAS 5 /* 5-bit fields get this added */ #define CHIPC_MC_BYPASS 0x08 #define CHIPC_MC_M1 0x04 #define CHIPC_MC_M1M2 0x02 #define CHIPC_MC_M1M2M3 0x01 #define CHIPC_MC_M1M3 0x11 /* Type 2 Clock control magic field values */ #define CHIPC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */ #define CHIPC_T2M2_BIAS 3 /* m2 bias */ #define CHIPC_T2MC_M1BYP 1 #define CHIPC_T2MC_M2BYP 2 #define CHIPC_T2MC_M3BYP 4 /* Type 6 Clock control magic field values */ #define CHIPC_T6_MMASK 1 /* bits of interest in m */ #define CHIPC_T6_M0 120000000 /* sb clock for m = 0 */ #define CHIPC_T6_M1 100000000 /* sb clock for m = 1 */ #define CHIPC_SB2MIPS_T6(sb) (2 * (sb)) /* Common clock base */ #define CHIPC_CLOCK_BASE1 24000000 /* Half the clock freq */ #define CHIPC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLLs */ /* Clock control values for 200MHz in 5350 */ #define CHIPC_CLKC_5350_N 0x0311 #define CHIPC_CLKC_5350_M 0x04020009 /* Bits in the ExtBus config registers */ #define CHIPC_CFG_EN 0x0001 /* Enable */ #define CHIPC_CFG_EM_MASK 0x000e /* Extif Mode */ #define CHIPC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */ #define CHIPC_CFG_EM_SYNC 0x0002 /* Synchronous */ #define CHIPC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */ #define CHIPC_CFG_EM_IDE 0x0006 /* IDE */ #define CHIPC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */ #define CHIPC_FLASH_CFG_CD_MASK 0x00e0 /* Sync: Clock divisor, rev >= 20 */ #define CHIPC_FLASH_CFG_CE 0x0100 /* Sync: Clock enable, rev >= 20 */ #define CHIPC_FLASH_CFG_SB 0x0200 /* Sync: Size/Bytestrobe, rev >= 20 */ #define CHIPC_FLASH_CFG_IS 0x0400 /* Extif Sync Clk Select, rev >= 20 */ /* ExtBus address space */ #define CHIPC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */ #define CHIPC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */ #define CHIPC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */ #define CHIPC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */ #define CHIPC_EB_IDE 0x1a800000 /* IDE memory base */ #define CHIPC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */ #define CHIPC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */ #define CHIPC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */ #define CHIPC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */ /* Start/busy bit in flashcontrol */ #define CHIPC_SFLASH_OPCODE 0x000000ff #define CHIPC_SFLASH_ACTION 0x00000700 #define CHIPC_SFLASH_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */ #define CHIPC_SFLASH_START 0x80000000 #define CHIPC_SFLASH_BUSY SFLASH_START /* flashcontrol action codes */ #define CHIPC_SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */ #define CHIPC_SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */ #define CHIPC_SFLASH_ACT_OP3A 0x0200 /* opcode + 3 addr bytes */ #define CHIPC_SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addr & 1 data bytes */ #define CHIPC_SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addr & 4 data bytes */ #define CHIPC_SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addr, 4 don't care & 4 data bytes */ #define CHIPC_SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addr, 1 don't care & 4 data bytes */ /* flashcontrol action+opcodes for ST flashes */ #define CHIPC_SFLASH_ST_WREN 0x0006 /* Write Enable */ #define CHIPC_SFLASH_ST_WRDIS 0x0004 /* Write Disable */ #define CHIPC_SFLASH_ST_RDSR 0x0105 /* Read Status Register */ #define CHIPC_SFLASH_ST_WRSR 0x0101 /* Write Status Register */ #define CHIPC_SFLASH_ST_READ 0x0303 /* Read Data Bytes */ #define CHIPC_SFLASH_ST_PP 0x0302 /* Page Program */ #define CHIPC_SFLASH_ST_SE 0x02d8 /* Sector Erase */ #define CHIPC_SFLASH_ST_BE 0x00c7 /* Bulk Erase */ #define CHIPC_SFLASH_ST_DP 0x00b9 /* Deep Power-down */ #define CHIPC_SFLASH_ST_RES 0x03ab /* Read Electronic Signature */ #define CHIPC_SFLASH_ST_CSA 0x1000 /* Keep chip select asserted */ #define CHIPC_SFLASH_ST_SSE 0x0220 /* Sub-sector Erase */ /* Status register bits for ST flashes */ #define CHIPC_SFLASH_ST_WIP 0x01 /* Write In Progress */ #define CHIPC_SFLASH_ST_WEL 0x02 /* Write Enable Latch */ #define CHIPC_SFLASH_ST_BP_MASK 0x1c /* Block Protect */ #define CHIPC_SFLASH_ST_BP_SHIFT 2 #define CHIPC_SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */ /* flashcontrol action+opcodes for Atmel flashes */ #define CHIPC_SFLASH_AT_READ 0x07e8 #define CHIPC_SFLASH_AT_PAGE_READ 0x07d2 #define CHIPC_SFLASH_AT_BUF1_READ #define CHIPC_SFLASH_AT_BUF2_READ #define CHIPC_SFLASH_AT_STATUS 0x01d7 #define CHIPC_SFLASH_AT_BUF1_WRITE 0x0384 #define CHIPC_SFLASH_AT_BUF2_WRITE 0x0387 #define CHIPC_SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283 #define CHIPC_SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286 #define CHIPC_SFLASH_AT_BUF1_PROGRAM 0x0288 #define CHIPC_SFLASH_AT_BUF2_PROGRAM 0x0289 #define CHIPC_SFLASH_AT_PAGE_ERASE 0x0281 #define CHIPC_SFLASH_AT_BLOCK_ERASE 0x0250 #define CHIPC_SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382 #define CHIPC_SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385 #define CHIPC_SFLASH_AT_BUF1_LOAD 0x0253 #define CHIPC_SFLASH_AT_BUF2_LOAD 0x0255 #define CHIPC_SFLASH_AT_BUF1_COMPARE 0x0260 #define CHIPC_SFLASH_AT_BUF2_COMPARE 0x0261 #define CHIPC_SFLASH_AT_BUF1_REPROGRAM 0x0258 #define CHIPC_SFLASH_AT_BUF2_REPROGRAM 0x0259 /* Status register bits for Atmel flashes */ #define CHIPC_SFLASH_AT_READY 0x80 #define CHIPC_SFLASH_AT_MISMATCH 0x40 #define CHIPC_SFLASH_AT_ID_MASK 0x38 #define CHIPC_SFLASH_AT_ID_SHIFT 3 /* * These are the UART port assignments, expressed as offsets from the base * register. These assignments should hold for any serial port based on * a 8250, 16450, or 16550(A). */ #define CHIPC_UART_RX 0 /* In: Receive buffer (DLAB=0) */ #define CHIPC_UART_TX 0 /* Out: Transmit buffer (DLAB=0) */ #define CHIPC_UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */ #define CHIPC_UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */ #define CHIPC_UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */ #define CHIPC_UART_IIR 2 /* In: Interrupt Identity Register */ #define CHIPC_UART_FCR 2 /* Out: FIFO Control Register */ #define CHIPC_UART_LCR 3 /* Out: Line Control Register */ #define CHIPC_UART_MCR 4 /* Out: Modem Control Register */ #define CHIPC_UART_LSR 5 /* In: Line Status Register */ #define CHIPC_UART_MSR 6 /* In: Modem Status Register */ #define CHIPC_UART_SCR 7 /* I/O: Scratch Register */ #define CHIPC_UART_LCR_DLAB 0x80 /* Divisor latch access bit */ #define CHIPC_UART_LCR_WLEN8 0x03 /* Word length: 8 bits */ #define CHIPC_UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */ #define CHIPC_UART_MCR_LOOP 0x10 /* Enable loopback test mode */ #define CHIPC_UART_LSR_RX_FIFO 0x80 /* Receive FIFO error */ #define CHIPC_UART_LSR_TDHR 0x40 /* Data-hold-register empty */ #define CHIPC_UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ #define CHIPC_UART_LSR_BREAK 0x10 /* Break interrupt */ #define CHIPC_UART_LSR_FRAMING 0x08 /* Framing error */ #define CHIPC_UART_LSR_PARITY 0x04 /* Parity error */ #define CHIPC_UART_LSR_OVERRUN 0x02 /* Overrun error */ #define CHIPC_UART_LSR_RXRDY 0x01 /* Receiver ready */ #define CHIPC_UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */ /* Interrupt Identity Register (IIR) bits */ #define CHIPC_UART_IIR_FIFO_MASK 0xc0 /* IIR FIFO disable/enabled mask */ #define CHIPC_UART_IIR_INT_MASK 0xf /* IIR interrupt ID source */ #define CHIPC_UART_IIR_MDM_CHG 0x0 /* Modem status changed */ #define CHIPC_UART_IIR_NOINT 0x1 /* No interrupt pending */ #define CHIPC_UART_IIR_THRE 0x2 /* THR empty */ #define CHIPC_UART_IIR_RCVD_DATA 0x4 /* Received data available */ #define CHIPC_UART_IIR_RCVR_STATUS 0x6 /* Receiver status */ #define CHIPC_UART_IIR_CHAR_TIME 0xc /* Character time */ /* Interrupt Enable Register (IER) bits */ #define CHIPC_UART_IER_EDSSI 8 /* enable modem status interrupt */ #define CHIPC_UART_IER_ELSI 4 /* enable receiver line status interrupt */ #define CHIPC_UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */ #define CHIPC_UART_IER_ERBFI 1 /* enable data available interrupt */ /* pmustatus */ #define CHIPC_PST_EXTLPOAVAIL 0x0100 #define CHIPC_PST_WDRESET 0x0080 #define CHIPC_PST_INTPEND 0x0040 #define CHIPC_PST_SBCLKST 0x0030 #define CHIPC_PST_SBCLKST_ILP 0x0010 #define CHIPC_PST_SBCLKST_ALP 0x0020 #define CHIPC_PST_SBCLKST_HT 0x0030 #define CHIPC_PST_ALPAVAIL 0x0008 #define CHIPC_PST_HTAVAIL 0x0004 #define CHIPC_PST_RESINIT 0x0003 /* pmucapabilities */ #define CHIPC_PCAP_REV_MASK 0x000000ff #define CHIPC_PCAP_RC_MASK 0x00001f00 #define CHIPC_PCAP_RC_SHIFT 8 #define CHIPC_PCAP_TC_MASK 0x0001e000 #define CHIPC_PCAP_TC_SHIFT 13 #define CHIPC_PCAP_PC_MASK 0x001e0000 #define CHIPC_PCAP_PC_SHIFT 17 #define CHIPC_PCAP_VC_MASK 0x01e00000 #define CHIPC_PCAP_VC_SHIFT 21 #define CHIPC_PCAP_CC_MASK 0x1e000000 #define CHIPC_PCAP_CC_SHIFT 25 #define CHIPC_PCAP5_PC_MASK 0x003e0000 /* PMU corerev >= 5 */ #define CHIPC_PCAP5_PC_SHIFT 17 #define CHIPC_PCAP5_VC_MASK 0x07c00000 #define CHIPC_PCAP5_VC_SHIFT 22 #define CHIPC_PCAP5_CC_MASK 0xf8000000 #define CHIPC_PCAP5_CC_SHIFT 27 /* PMU Resource Request Timer registers */ /* This is based on PmuRev0 */ #define CHIPC_PRRT_TIME_MASK 0x03ff #define CHIPC_PRRT_INTEN 0x0400 #define CHIPC_PRRT_REQ_ACTIVE 0x0800 #define CHIPC_PRRT_ALP_REQ 0x1000 #define CHIPC_PRRT_HT_REQ 0x2000 /* PMU resource bit position */ #define CHIPC_PMURES_BIT(bit) (1 << (bit)) /* PMU resource number limit */ #define CHIPC_PMURES_MAX_RESNUM 30 /* PMU chip control0 register */ #define CHIPC_PMU_CHIPCTL0 0 /* PMU chip control1 register */ #define CHIPC_PMU_CHIPCTL1 1 #define CHIPC_PMU_CC1_RXC_DLL_BYPASS 0x00010000 #define CHIPC_PMU_CC1_IF_TYPE_MASK 0x00000030 #define CHIPC_PMU_CC1_IF_TYPE_RMII 0x00000000 #define CHIPC_PMU_CC1_IF_TYPE_MII 0x00000010 #define CHIPC_PMU_CC1_IF_TYPE_RGMII 0x00000020 #define CHIPC_PMU_CC1_SW_TYPE_MASK 0x000000c0 #define CHIPC_PMU_CC1_SW_TYPE_EPHY 0x00000000 #define CHIPC_PMU_CC1_SW_TYPE_EPHYMII 0x00000040 #define CHIPC_PMU_CC1_SW_TYPE_EPHYRMII 0x00000080 #define CHIPC_PMU_CC1_SW_TYPE_RGMII 0x000000c0 /* PMU corerev and chip specific PLL controls. * PMU_PLL_XX where is PMU corerev and is an arbitrary number * to differentiate different PLLs controlled by the same PMU rev. */ /* pllcontrol registers */ /* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */ #define CHIPC_PMU0_PLL0_PLLCTL0 0 #define CHIPC_PMU0_PLL0_PC0_PDIV_MASK 1 #define CHIPC_PMU0_PLL0_PC0_PDIV_FREQ 25000 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_SHIFT 3 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_BASE 8 /* PC0_DIV_ARM for PLLOUT_ARM */ #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_110MHZ 0 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_88MHZ 2 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */ #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7 /* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */ #define CHIPC_PMU0_PLL0_PLLCTL1 1 #define CHIPC_PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000 #define CHIPC_PMU0_PLL0_PC1_WILD_INT_SHIFT 28 #define CHIPC_PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00 #define CHIPC_PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8 #define CHIPC_PMU0_PLL0_PC1_STOP_MOD 0x00000040 /* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */ #define CHIPC_PMU0_PLL0_PLLCTL2 2 #define CHIPC_PMU0_PLL0_PC2_WILD_INT_MASK 0xf #define CHIPC_PMU0_PLL0_PC2_WILD_INT_SHIFT 4 /* pllcontrol registers */ /* ndiv_pwrdn, pwrdn_ch, refcomp_pwrdn, dly_ch, p1div, p2div, _bypass_sdmod */ #define CHIPC_PMU1_PLL0_PLLCTL0 0 #define CHIPC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 #define CHIPC_PMU1_PLL0_PC0_P1DIV_SHIFT 20 #define CHIPC_PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000 #define CHIPC_PMU1_PLL0_PC0_P2DIV_SHIFT 24 /* mdiv */ #define CHIPC_PMU1_PLL0_PLLCTL1 1 #define CHIPC_PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff #define CHIPC_PMU1_PLL0_PC1_M1DIV_SHIFT 0 #define CHIPC_PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00 #define CHIPC_PMU1_PLL0_PC1_M2DIV_SHIFT 8 #define CHIPC_PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000 #define CHIPC_PMU1_PLL0_PC1_M3DIV_SHIFT 16 #define CHIPC_PMU1_PLL0_PC1_M4DIV_MASK 0xff000000 #define CHIPC_PMU1_PLL0_PC1_M4DIV_SHIFT 24 #define CHIPC_DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8 #define CHIPC_DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) #define CHIPC_DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) /* mdiv, ndiv_dither_mfb, ndiv_mode, ndiv_int */ #define CHIPC_PMU1_PLL0_PLLCTL2 2 #define CHIPC_PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff #define CHIPC_PMU1_PLL0_PC2_M5DIV_SHIFT 0 #define CHIPC_PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00 #define CHIPC_PMU1_PLL0_PC2_M6DIV_SHIFT 8 #define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000 #define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17 #define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_MASH 1 #define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_MFB 2 /* recommended for 4319 */ #define CHIPC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 #define CHIPC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 /* ndiv_frac */ #define CHIPC_PMU1_PLL0_PLLCTL3 3 #define CHIPC_PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff #define CHIPC_PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0 /* pll_ctrl */ #define CHIPC_PMU1_PLL0_PLLCTL4 4 /* pll_ctrl, vco_rng, clkdrive_ch */ #define CHIPC_PMU1_PLL0_PLLCTL5 5 #define CHIPC_PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00 #define CHIPC_PMU1_PLL0_PC5_CLK_DRV_SHIFT 8 /* PMU rev 2 control words */ #define CHIPC_PMU2_PHY_PLL_PLLCTL 4 #define CHIPC_PMU2_SI_PLL_PLLCTL 10 /* PMU rev 2 */ /* pllcontrol registers */ /* ndiv_pwrdn, pwrdn_ch, refcomp_pwrdn, dly_ch, p1div, p2div, _bypass_sdmod */ #define CHIPC_PMU2_PLL_PLLCTL0 0 #define CHIPC_PMU2_PLL_PC0_P1DIV_MASK 0x00f00000 #define CHIPC_PMU2_PLL_PC0_P1DIV_SHIFT 20 #define CHIPC_PMU2_PLL_PC0_P2DIV_MASK 0x0f000000 #define CHIPC_PMU2_PLL_PC0_P2DIV_SHIFT 24 /* mdiv */ #define CHIPC_PMU2_PLL_PLLCTL1 1 #define CHIPC_PMU2_PLL_PC1_M1DIV_MASK 0x000000ff #define CHIPC_PMU2_PLL_PC1_M1DIV_SHIFT 0 #define CHIPC_PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00 #define CHIPC_PMU2_PLL_PC1_M2DIV_SHIFT 8 #define CHIPC_PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000 #define CHIPC_PMU2_PLL_PC1_M3DIV_SHIFT 16 #define CHIPC_PMU2_PLL_PC1_M4DIV_MASK 0xff000000 #define CHIPC_PMU2_PLL_PC1_M4DIV_SHIFT 24 /* mdiv, ndiv_dither_mfb, ndiv_mode, ndiv_int */ #define CHIPC_PMU2_PLL_PLLCTL2 2 #define CHIPC_PMU2_PLL_PC2_M5DIV_MASK 0x000000ff #define CHIPC_PMU2_PLL_PC2_M5DIV_SHIFT 0 #define CHIPC_PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00 #define CHIPC_PMU2_PLL_PC2_M6DIV_SHIFT 8 #define CHIPC_PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000 #define CHIPC_PMU2_PLL_PC2_NDIV_MODE_SHIFT 17 #define CHIPC_PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000 #define CHIPC_PMU2_PLL_PC2_NDIV_INT_SHIFT 20 /* ndiv_frac */ #define CHIPC_PMU2_PLL_PLLCTL3 3 #define CHIPC_PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff #define CHIPC_PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0 /* pll_ctrl */ #define CHIPC_PMU2_PLL_PLLCTL4 4 /* pll_ctrl, vco_rng, clkdrive_ch */ #define CHIPC_PMU2_PLL_PLLCTL5 5 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28 /* PMU rev 5 (& 6) */ #define CHIPC_PMU5_PLL_P1P2_OFF 0 #define CHIPC_PMU5_PLL_P1_MASK 0x0f000000 #define CHIPC_PMU5_PLL_P1_SHIFT 24 #define CHIPC_PMU5_PLL_P2_MASK 0x00f00000 #define CHIPC_PMU5_PLL_P2_SHIFT 20 #define CHIPC_PMU5_PLL_M14_OFF 1 #define CHIPC_PMU5_PLL_MDIV_MASK 0x000000ff #define CHIPC_PMU5_PLL_MDIV_WIDTH 8 #define CHIPC_PMU5_PLL_NM5_OFF 2 #define CHIPC_PMU5_PLL_NDIV_MASK 0xfff00000 #define CHIPC_PMU5_PLL_NDIV_SHIFT 20 #define CHIPC_PMU5_PLL_NDIV_MODE_MASK 0x000e0000 #define CHIPC_PMU5_PLL_NDIV_MODE_SHIFT 17 #define CHIPC_PMU5_PLL_FMAB_OFF 3 #define CHIPC_PMU5_PLL_MRAT_MASK 0xf0000000 #define CHIPC_PMU5_PLL_MRAT_SHIFT 28 #define CHIPC_PMU5_PLL_ABRAT_MASK 0x08000000 #define CHIPC_PMU5_PLL_ABRAT_SHIFT 27 #define CHIPC_PMU5_PLL_FDIV_MASK 0x07ffffff #define CHIPC_PMU5_PLL_PLLCTL_OFF 4 #define CHIPC_PMU5_PLL_PCHI_OFF 5 #define CHIPC_PMU5_PLL_PCHI_MASK 0x0000003f /* pmu XtalFreqRatio */ #define CHIPC_PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF #define CHIPC_PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000 #define CHIPC_PMU_XTALFREQ_REG_MEASURE_SHIFT 31 /* Divider allocation in 4716/47162/5356/5357 */ #define CHIPC_PMU5_MAINPLL_CPU 1 #define CHIPC_PMU5_MAINPLL_MEM 2 #define CHIPC_PMU5_MAINPLL_SI 3 #define CHIPC_PMU7_PLL_PLLCTL7 7 #define CHIPC_PMU7_PLL_PLLCTL8 8 #define CHIPC_PMU7_PLL_PLLCTL11 11 /* PLL usage in 4716/47162 */ #define CHIPC_PMU4716_MAINPLL_PLL0 12 /* PLL usage in 5356/5357 */ #define CHIPC_PMU5356_MAINPLL_PLL0 0 #define CHIPC_PMU5357_MAINPLL_PLL0 0 /* 4716/47162 resources */ #define CHIPC_RES4716_PROC_PLL_ON 0x00000040 #define CHIPC_RES4716_PROC_HT_AVAIL 0x00000080 /* 4716/4717/4718 Chip specific ChipControl register bits */ #define CHIPC_CCTRL471X_I2S_PINS_ENABLE 0x0080 /* I2S pins off by default, shared with pflash */ /* 5354 resources */ #define CHIPC_RES5354_EXT_SWITCHER_PWM 0 /* 0x00001 */ #define CHIPC_RES5354_BB_SWITCHER_PWM 1 /* 0x00002 */ #define CHIPC_RES5354_BB_SWITCHER_BURST 2 /* 0x00004 */ #define CHIPC_RES5354_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ #define CHIPC_RES5354_ILP_REQUEST 4 /* 0x00010 */ #define CHIPC_RES5354_RADIO_SWITCHER_PWM 5 /* 0x00020 */ #define CHIPC_RES5354_RADIO_SWITCHER_BURST 6 /* 0x00040 */ #define CHIPC_RES5354_ROM_SWITCH 7 /* 0x00080 */ #define CHIPC_RES5354_PA_REF_LDO 8 /* 0x00100 */ #define CHIPC_RES5354_RADIO_LDO 9 /* 0x00200 */ #define CHIPC_RES5354_AFE_LDO 10 /* 0x00400 */ #define CHIPC_RES5354_PLL_LDO 11 /* 0x00800 */ #define CHIPC_RES5354_BG_FILTBYP 12 /* 0x01000 */ #define CHIPC_RES5354_TX_FILTBYP 13 /* 0x02000 */ #define CHIPC_RES5354_RX_FILTBYP 14 /* 0x04000 */ #define CHIPC_RES5354_XTAL_PU 15 /* 0x08000 */ #define CHIPC_RES5354_XTAL_EN 16 /* 0x10000 */ #define CHIPC_RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */ #define CHIPC_RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */ #define CHIPC_RES5354_BB_PLL_PU 19 /* 0x80000 */ /* 5357 Chip specific ChipControl register bits */ #define CHIPC_CCTRL5357_EXTPA (1<<14) /* extPA in ChipControl 1, bit 14 */ #define CHIPC_CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in ChipControl 1, bit 15 */ /* 4328 resources */ #define CHIPC_RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */ #define CHIPC_RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */ #define CHIPC_RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */ #define CHIPC_RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ #define CHIPC_RES4328_ILP_REQUEST 4 /* 0x00010 */ #define CHIPC_RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */ #define CHIPC_RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */ #define CHIPC_RES4328_ROM_SWITCH 7 /* 0x00080 */ #define CHIPC_RES4328_PA_REF_LDO 8 /* 0x00100 */ #define CHIPC_RES4328_RADIO_LDO 9 /* 0x00200 */ #define CHIPC_RES4328_AFE_LDO 10 /* 0x00400 */ #define CHIPC_RES4328_PLL_LDO 11 /* 0x00800 */ #define CHIPC_RES4328_BG_FILTBYP 12 /* 0x01000 */ #define CHIPC_RES4328_TX_FILTBYP 13 /* 0x02000 */ #define CHIPC_RES4328_RX_FILTBYP 14 /* 0x04000 */ #define CHIPC_RES4328_XTAL_PU 15 /* 0x08000 */ #define CHIPC_RES4328_XTAL_EN 16 /* 0x10000 */ #define CHIPC_RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */ #define CHIPC_RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */ #define CHIPC_RES4328_BB_PLL_PU 19 /* 0x80000 */ /* 4325 A0/A1 resources */ #define CHIPC_RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */ #define CHIPC_RES4325_CBUCK_BURST 1 /* 0x00000002 */ #define CHIPC_RES4325_CBUCK_PWM 2 /* 0x00000004 */ #define CHIPC_RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */ #define CHIPC_RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */ #define CHIPC_RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */ #define CHIPC_RES4325_ILP_REQUEST 6 /* 0x00000040 */ #define CHIPC_RES4325_ABUCK_BURST 7 /* 0x00000080 */ #define CHIPC_RES4325_ABUCK_PWM 8 /* 0x00000100 */ #define CHIPC_RES4325_LNLDO1_PU 9 /* 0x00000200 */ #define CHIPC_RES4325_OTP_PU 10 /* 0x00000400 */ #define CHIPC_RES4325_LNLDO3_PU 11 /* 0x00000800 */ #define CHIPC_RES4325_LNLDO4_PU 12 /* 0x00001000 */ #define CHIPC_RES4325_XTAL_PU 13 /* 0x00002000 */ #define CHIPC_RES4325_ALP_AVAIL 14 /* 0x00004000 */ #define CHIPC_RES4325_RX_PWRSW_PU 15 /* 0x00008000 */ #define CHIPC_RES4325_TX_PWRSW_PU 16 /* 0x00010000 */ #define CHIPC_RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */ #define CHIPC_RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */ #define CHIPC_RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */ #define CHIPC_RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */ #define CHIPC_RES4325_HT_AVAIL 21 /* 0x00200000 */ /* 4325 B0/C0 resources */ #define CHIPC_RES4325B0_CBUCK_LPOM 1 /* 0x00000002 */ #define CHIPC_RES4325B0_CBUCK_BURST 2 /* 0x00000004 */ #define CHIPC_RES4325B0_CBUCK_PWM 3 /* 0x00000008 */ #define CHIPC_RES4325B0_CLDO_PU 4 /* 0x00000010 */ /* 4325 C1 resources */ #define CHIPC_RES4325C1_LNLDO2_PU 12 /* 0x00001000 */ /* 4325 chip-specific ChipStatus register bits */ #define CHIPC_CST4325_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK #define CHIPC_CST4325_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT #define CHIPC_CST4325_SDIO_USB_MODE_MASK 0x00000004 #define CHIPC_CST4325_SDIO_USB_MODE_SHIFT 2 #define CHIPC_CST4325_RCAL_VALID_MASK 0x00000008 #define CHIPC_CST4325_RCAL_VALID_SHIFT 3 #define CHIPC_CST4325_RCAL_VALUE_MASK 0x000001f0 #define CHIPC_CST4325_RCAL_VALUE_SHIFT 4 #define CHIPC_CST4325_PMUTOP_2B_MASK 0x00000200 /* 1 for 2b, 0 for to 2a */ #define CHIPC_CST4325_PMUTOP_2B_SHIFT 9 #define CHIPC_RES4329_RESERVED0 0 /* 0x00000001 */ #define CHIPC_RES4329_CBUCK_LPOM 1 /* 0x00000002 */ #define CHIPC_RES4329_CBUCK_BURST 2 /* 0x00000004 */ #define CHIPC_RES4329_CBUCK_PWM 3 /* 0x00000008 */ #define CHIPC_RES4329_CLDO_PU 4 /* 0x00000010 */ #define CHIPC_RES4329_PALDO_PU 5 /* 0x00000020 */ #define CHIPC_RES4329_ILP_REQUEST 6 /* 0x00000040 */ #define CHIPC_RES4329_RESERVED7 7 /* 0x00000080 */ #define CHIPC_RES4329_RESERVED8 8 /* 0x00000100 */ #define CHIPC_RES4329_LNLDO1_PU 9 /* 0x00000200 */ #define CHIPC_RES4329_OTP_PU 10 /* 0x00000400 */ #define CHIPC_RES4329_RESERVED11 11 /* 0x00000800 */ #define CHIPC_RES4329_LNLDO2_PU 12 /* 0x00001000 */ #define CHIPC_RES4329_XTAL_PU 13 /* 0x00002000 */ #define CHIPC_RES4329_ALP_AVAIL 14 /* 0x00004000 */ #define CHIPC_RES4329_RX_PWRSW_PU 15 /* 0x00008000 */ #define CHIPC_RES4329_TX_PWRSW_PU 16 /* 0x00010000 */ #define CHIPC_RES4329_RFPLL_PWRSW_PU 17 /* 0x00020000 */ #define CHIPC_RES4329_LOGEN_PWRSW_PU 18 /* 0x00040000 */ #define CHIPC_RES4329_AFE_PWRSW_PU 19 /* 0x00080000 */ #define CHIPC_RES4329_BBPLL_PWRSW_PU 20 /* 0x00100000 */ #define CHIPC_RES4329_HT_AVAIL 21 /* 0x00200000 */ /* 4329 chip-specific ChipStatus register bits */ #define CHIPC_CST4329_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK #define CHIPC_CST4329_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT #define CHIPC_CST4329_SPI_SDIO_MODE_MASK 0x00000004 #define CHIPC_CST4329_SPI_SDIO_MODE_SHIFT 2 /* 4312 chip-specific ChipStatus register bits */ #define CHIPC_CST4312_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK #define CHIPC_CST4312_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT /* 4312 resources (all PMU chips with little memory constraint) */ #define CHIPC_RES4312_SWITCHER_BURST 0 /* 0x00000001 */ #define CHIPC_RES4312_SWITCHER_PWM 1 /* 0x00000002 */ #define CHIPC_RES4312_PA_REF_LDO 2 /* 0x00000004 */ #define CHIPC_RES4312_CORE_LDO_BURST 3 /* 0x00000008 */ #define CHIPC_RES4312_CORE_LDO_PWM 4 /* 0x00000010 */ #define CHIPC_RES4312_RADIO_LDO 5 /* 0x00000020 */ #define CHIPC_RES4312_ILP_REQUEST 6 /* 0x00000040 */ #define CHIPC_RES4312_BG_FILTBYP 7 /* 0x00000080 */ #define CHIPC_RES4312_TX_FILTBYP 8 /* 0x00000100 */ #define CHIPC_RES4312_RX_FILTBYP 9 /* 0x00000200 */ #define CHIPC_RES4312_XTAL_PU 10 /* 0x00000400 */ #define CHIPC_RES4312_ALP_AVAIL 11 /* 0x00000800 */ #define CHIPC_RES4312_BB_PLL_FILTBYP 12 /* 0x00001000 */ #define CHIPC_RES4312_RF_PLL_FILTBYP 13 /* 0x00002000 */ #define CHIPC_RES4312_HT_AVAIL 14 /* 0x00004000 */ /* 4322 resources */ #define CHIPC_RES4322_RF_LDO 0 #define CHIPC_RES4322_ILP_REQUEST 1 #define CHIPC_RES4322_XTAL_PU 2 #define CHIPC_RES4322_ALP_AVAIL 3 #define CHIPC_RES4322_SI_PLL_ON 4 #define CHIPC_RES4322_HT_SI_AVAIL 5 #define CHIPC_RES4322_PHY_PLL_ON 6 #define CHIPC_RES4322_HT_PHY_AVAIL 7 #define CHIPC_RES4322_OTP_PU 8 /* 4322 chip-specific ChipStatus register bits */ #define CHIPC_CST4322_XTAL_FREQ_20_40MHZ 0x00000020 #define CHIPC_CST4322_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R23_MASK #define CHIPC_CST4322_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT #define CHIPC_CST4322_PCI_OR_USB 0x00000100 #define CHIPC_CST4322_BOOT_MASK 0x00000600 #define CHIPC_CST4322_BOOT_SHIFT 9 #define CHIPC_CST4322_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ #define CHIPC_CST4322_BOOT_FROM_ROM 1 /* boot from ROM */ #define CHIPC_CST4322_BOOT_FROM_FLASH 2 /* boot from FLASH */ #define CHIPC_CST4322_BOOT_FROM_INVALID 3 #define CHIPC_CST4322_ILP_DIV_EN 0x00000800 #define CHIPC_CST4322_FLASH_TYPE_MASK 0x00001000 #define CHIPC_CST4322_FLASH_TYPE_SHIFT 12 #define CHIPC_CST4322_FLASH_TYPE_SHIFT_ST 0 /* ST serial FLASH */ #define CHIPC_CST4322_FLASH_TYPE_SHIFT_ATMEL 1 /* ATMEL flash */ #define CHIPC_CST4322_ARM_TAP_SEL 0x00002000 #define CHIPC_CST4322_RES_INIT_MODE_MASK 0x0000c000 #define CHIPC_CST4322_RES_INIT_MODE_SHIFT 14 #define CHIPC_CST4322_RES_INIT_MODE_ILPAVAIL 0 /* resinitmode: ILP available */ #define CHIPC_CST4322_RES_INIT_MODE_ILPREQ 1 /* resinitmode: ILP request */ #define CHIPC_CST4322_RES_INIT_MODE_ALPAVAIL 2 /* resinitmode: ALP available */ #define CHIPC_CST4322_RES_INIT_MODE_HTAVAIL 3 /* resinitmode: HT available */ #define CHIPC_CST4322_PCIPLLCLK_GATING 0x00010000 #define CHIPC_CST4322_CLK_SWITCH_PCI_TO_ALP 0x00020000 #define CHIPC_CST4322_PCI_CARDBUS_MODE 0x00040000 /* 43224 chip-specific ChipControl register bits */ #define CHIPC_CCTRL43224_GPIO_TOGGLE 0x8000 #define CHIPC_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */ #define CHIPC_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */ /* 43236 resources */ #define CHIPC_RES43236_REGULATOR 0 #define CHIPC_RES43236_ILP_REQUEST 1 #define CHIPC_RES43236_XTAL_PU 2 #define CHIPC_RES43236_ALP_AVAIL 3 #define CHIPC_RES43236_SI_PLL_ON 4 #define CHIPC_RES43236_HT_SI_AVAIL 5 /* 43236 chip-specific ChipControl register bits */ #define CHIPC_CCTRL43236_BT_COEXIST (1<<0) /* 0 disable */ #define CHIPC_CCTRL43236_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ #define CHIPC_CCTRL43236_EXT_LNA (1<<2) /* 0 disable */ #define CHIPC_CCTRL43236_ANT_MUX_2o3 (1<<3) /* 2o3 mux, chipcontrol bit 3 */ #define CHIPC_CCTRL43236_GSIO (1<<4) /* 0 disable */ /* 43236 Chip specific ChipStatus register bits */ #define CHIPC_CST43236_SFLASH_MASK 0x00000040 #define CHIPC_CST43236_OTP_SEL_MASK 0x00000080 #define CHIPC_CST43236_OTP_SEL_SHIFT 7 #define CHIPC_CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */ #define CHIPC_CST43236_BP_CLK 0x00000200 /* 120/96Mbps */ #define CHIPC_CST43236_BOOT_MASK 0x00001800 #define CHIPC_CST43236_BOOT_SHIFT 11 #define CHIPC_CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ #define CHIPC_CST43236_BOOT_FROM_ROM 1 /* boot from ROM */ #define CHIPC_CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */ #define CHIPC_CST43236_BOOT_FROM_INVALID 3 /* 4331 resources */ #define CHIPC_RES4331_REGULATOR 0 #define CHIPC_RES4331_ILP_REQUEST 1 #define CHIPC_RES4331_XTAL_PU 2 #define CHIPC_RES4331_ALP_AVAIL 3 #define CHIPC_RES4331_SI_PLL_ON 4 #define CHIPC_RES4331_HT_SI_AVAIL 5 /* 4331 chip-specific ChipControl register bits */ #define CHIPC_CCTRL4331_BT_COEXIST (1<<0) /* 0 disable */ #define CHIPC_CCTRL4331_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ #define CHIPC_CCTRL4331_EXT_LNA (1<<2) /* 0 disable */ #define CHIPC_CCTRL4331_SPROM_GPIO13_15 (1<<3) /* sprom/gpio13-15 mux */ #define CHIPC_CCTRL4331_EXTPA_EN (1<<4) /* 0 ext pa disable, 1 ext pa enabled */ #define CHIPC_CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5) /* set drive out GPIO_CLK on sprom_cs pin */ #define CHIPC_CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6) /* use sprom_cs pin as PCIE mdio interface */ #define CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7) /* aband extpa will be at gpio2/5 and sprom_dout */ #define CHIPC_CCTRL4331_OVR_PIPEAUXCLKEN (1<<8) /* override core control on pipe_AuxClkEnable */ #define CHIPC_CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9) /* override core control on pipe_AuxPowerDown */ #define CHIPC_CCTRL4331_PCIE_AUXCLKEN (1<<10) /* pcie_auxclkenable */ #define CHIPC_CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11) /* pcie_pipe_pllpowerdown */ #define CHIPC_CCTRL4331_EXTPA_EN2 (1<<12) /* 0 ext pa2 disable, 1 ext pa2 enabled */ #define CHIPC_CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16) /* enable bt_shd0 at gpio4 */ #define CHIPC_CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17) /* enable bt_shd1 at gpio5 */ /* 4331 Chip specific ChipStatus register bits */ #define CHIPC_CST4331_XTAL_FREQ 0x00000001 /* crystal frequency 20/40Mhz */ #define CHIPC_CST4331_SPROM_PRESENT 0x00000002 #define CHIPC_CST4331_OTP_PRESENT 0x00000004 #define CHIPC_CST4331_LDO_RF 0x00000008 #define CHIPC_CST4331_LDO_PAR 0x00000010 /* 4315 resources */ #define CHIPC_RES4315_CBUCK_LPOM 1 /* 0x00000002 */ #define CHIPC_RES4315_CBUCK_BURST 2 /* 0x00000004 */ #define CHIPC_RES4315_CBUCK_PWM 3 /* 0x00000008 */ #define CHIPC_RES4315_CLDO_PU 4 /* 0x00000010 */ #define CHIPC_RES4315_PALDO_PU 5 /* 0x00000020 */ #define CHIPC_RES4315_ILP_REQUEST 6 /* 0x00000040 */ #define CHIPC_RES4315_LNLDO1_PU 9 /* 0x00000200 */ #define CHIPC_RES4315_OTP_PU 10 /* 0x00000400 */ #define CHIPC_RES4315_LNLDO2_PU 12 /* 0x00001000 */ #define CHIPC_RES4315_XTAL_PU 13 /* 0x00002000 */ #define CHIPC_RES4315_ALP_AVAIL 14 /* 0x00004000 */ #define CHIPC_RES4315_RX_PWRSW_PU 15 /* 0x00008000 */ #define CHIPC_RES4315_TX_PWRSW_PU 16 /* 0x00010000 */ #define CHIPC_RES4315_RFPLL_PWRSW_PU 17 /* 0x00020000 */ #define CHIPC_RES4315_LOGEN_PWRSW_PU 18 /* 0x00040000 */ #define CHIPC_RES4315_AFE_PWRSW_PU 19 /* 0x00080000 */ #define CHIPC_RES4315_BBPLL_PWRSW_PU 20 /* 0x00100000 */ #define CHIPC_RES4315_HT_AVAIL 21 /* 0x00200000 */ /* 4315 chip-specific ChipStatus register bits */ #define CHIPC_CST4315_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK #define CHIPC_CST4315_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT #define CHIPC_CST4315_SDIO_MODE 0x00000004 /* gpio [8], sdio/usb mode */ #define CHIPC_CST4315_RCAL_VALID 0x00000008 #define CHIPC_CST4315_RCAL_VALUE_MASK 0x000001f0 #define CHIPC_CST4315_RCAL_VALUE_SHIFT 4 #define CHIPC_CST4315_PALDO_EXTPNP 0x00000200 /* PALDO is configured with external PNP */ #define CHIPC_CST4315_CBUCK_MODE_MASK 0x00000c00 #define CHIPC_CST4315_CBUCK_MODE_BURST 0x00000400 #define CHIPC_CST4315_CBUCK_MODE_LPBURST 0x00000c00 /* 4319 resources */ #define CHIPC_RES4319_CBUCK_LPOM 1 /* 0x00000002 */ #define CHIPC_RES4319_CBUCK_BURST 2 /* 0x00000004 */ #define CHIPC_RES4319_CBUCK_PWM 3 /* 0x00000008 */ #define CHIPC_RES4319_CLDO_PU 4 /* 0x00000010 */ #define CHIPC_RES4319_PALDO_PU 5 /* 0x00000020 */ #define CHIPC_RES4319_ILP_REQUEST 6 /* 0x00000040 */ #define CHIPC_RES4319_LNLDO1_PU 9 /* 0x00000200 */ #define CHIPC_RES4319_OTP_PU 10 /* 0x00000400 */ #define CHIPC_RES4319_LNLDO2_PU 12 /* 0x00001000 */ #define CHIPC_RES4319_XTAL_PU 13 /* 0x00002000 */ #define CHIPC_RES4319_ALP_AVAIL 14 /* 0x00004000 */ #define CHIPC_RES4319_RX_PWRSW_PU 15 /* 0x00008000 */ #define CHIPC_RES4319_TX_PWRSW_PU 16 /* 0x00010000 */ #define CHIPC_RES4319_RFPLL_PWRSW_PU 17 /* 0x00020000 */ #define CHIPC_RES4319_LOGEN_PWRSW_PU 18 /* 0x00040000 */ #define CHIPC_RES4319_AFE_PWRSW_PU 19 /* 0x00080000 */ #define CHIPC_RES4319_BBPLL_PWRSW_PU 20 /* 0x00100000 */ #define CHIPC_RES4319_HT_AVAIL 21 /* 0x00200000 */ /* 4319 chip-specific ChipStatus register bits */ #define CHIPC_CST4319_SPI_CPULESSUSB 0x00000001 #define CHIPC_CST4319_SPI_CLK_POL 0x00000002 #define CHIPC_CST4319_SPI_CLK_PH 0x00000008 #define CHIPC_CST4319_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R23_MASK /* gpio [7:6], SDIO CIS selection */ #define CHIPC_CST4319_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT #define CHIPC_CST4319_SDIO_USB_MODE 0x00000100 /* gpio [8], sdio/usb mode */ #define CHIPC_CST4319_REMAP_SEL_MASK 0x00000600 #define CHIPC_CST4319_ILPDIV_EN 0x00000800 #define CHIPC_CST4319_XTAL_PD_POL 0x00001000 #define CHIPC_CST4319_LPO_SEL 0x00002000 #define CHIPC_CST4319_RES_INIT_MODE 0x0000c000 #define CHIPC_CST4319_PALDO_EXTPNP 0x00010000 /* PALDO is configured with external PNP */ #define CHIPC_CST4319_CBUCK_MODE_MASK 0x00060000 #define CHIPC_CST4319_CBUCK_MODE_BURST 0x00020000 #define CHIPC_CST4319_CBUCK_MODE_LPBURST 0x00060000 #define CHIPC_CST4319_RCAL_VALID 0x01000000 #define CHIPC_CST4319_RCAL_VALUE_MASK 0x3e000000 #define CHIPC_CST4319_RCAL_VALUE_SHIFT 25 #define CHIPC_PMU1_PLL0_CHIPCTL0 0 #define CHIPC_PMU1_PLL0_CHIPCTL1 1 #define CHIPC_PMU1_PLL0_CHIPCTL2 2 #define CHIPC_CCTL_4319USB_XTAL_SEL_MASK 0x00180000 #define CHIPC_CCTL_4319USB_XTAL_SEL_SHIFT 19 #define CHIPC_CCTL_4319USB_48MHZ_PLL_SEL 1 #define CHIPC_CCTL_4319USB_24MHZ_PLL_SEL 2 /* PMU resources for 4336 */ #define CHIPC_RES4336_CBUCK_LPOM 0 #define CHIPC_RES4336_CBUCK_BURST 1 #define CHIPC_RES4336_CBUCK_LP_PWM 2 #define CHIPC_RES4336_CBUCK_PWM 3 #define CHIPC_RES4336_CLDO_PU 4 #define CHIPC_RES4336_DIS_INT_RESET_PD 5 #define CHIPC_RES4336_ILP_REQUEST 6 #define CHIPC_RES4336_LNLDO_PU 7 #define CHIPC_RES4336_LDO3P3_PU 8 #define CHIPC_RES4336_OTP_PU 9 #define CHIPC_RES4336_XTAL_PU 10 #define CHIPC_RES4336_ALP_AVAIL 11 #define CHIPC_RES4336_RADIO_PU 12 #define CHIPC_RES4336_BG_PU 13 #define CHIPC_RES4336_VREG1p4_PU_PU 14 #define CHIPC_RES4336_AFE_PWRSW_PU 15 #define CHIPC_RES4336_RX_PWRSW_PU 16 #define CHIPC_RES4336_TX_PWRSW_PU 17 #define CHIPC_RES4336_BB_PWRSW_PU 18 #define CHIPC_RES4336_SYNTH_PWRSW_PU 19 #define CHIPC_RES4336_MISC_PWRSW_PU 20 #define CHIPC_RES4336_LOGEN_PWRSW_PU 21 #define CHIPC_RES4336_BBPLL_PWRSW_PU 22 #define CHIPC_RES4336_MACPHY_CLKAVAIL 23 #define CHIPC_RES4336_HT_AVAIL 24 #define CHIPC_RES4336_RSVD 25 /* 4336 chip-specific ChipStatus register bits */ #define CHIPC_CST4336_SPI_MODE_MASK 0x00000001 #define CHIPC_CST4336_SPROM_PRESENT 0x00000002 #define CHIPC_CST4336_OTP_PRESENT 0x00000004 #define CHIPC_CST4336_ARMREMAP_0 0x00000008 #define CHIPC_CST4336_ILPDIV_EN_MASK 0x00000010 #define CHIPC_CST4336_ILPDIV_EN_SHIFT 4 #define CHIPC_CST4336_XTAL_PD_POL_MASK 0x00000020 #define CHIPC_CST4336_XTAL_PD_POL_SHIFT 5 #define CHIPC_CST4336_LPO_SEL_MASK 0x00000040 #define CHIPC_CST4336_LPO_SEL_SHIFT 6 #define CHIPC_CST4336_RES_INIT_MODE_MASK 0x00000180 #define CHIPC_CST4336_RES_INIT_MODE_SHIFT 7 #define CHIPC_CST4336_CBUCK_MODE_MASK 0x00000600 #define CHIPC_CST4336_CBUCK_MODE_SHIFT 9 /* 4330 resources */ #define CHIPC_RES4330_CBUCK_LPOM 0 #define CHIPC_RES4330_CBUCK_BURST 1 #define CHIPC_RES4330_CBUCK_LP_PWM 2 #define CHIPC_RES4330_CBUCK_PWM 3 #define CHIPC_RES4330_CLDO_PU 4 #define CHIPC_RES4330_DIS_INT_RESET_PD 5 #define CHIPC_RES4330_ILP_REQUEST 6 #define CHIPC_RES4330_LNLDO_PU 7 #define CHIPC_RES4330_LDO3P3_PU 8 #define CHIPC_RES4330_OTP_PU 9 #define CHIPC_RES4330_XTAL_PU 10 #define CHIPC_RES4330_ALP_AVAIL 11 #define CHIPC_RES4330_RADIO_PU 12 #define CHIPC_RES4330_BG_PU 13 #define CHIPC_RES4330_VREG1p4_PU_PU 14 #define CHIPC_RES4330_AFE_PWRSW_PU 15 #define CHIPC_RES4330_RX_PWRSW_PU 16 #define CHIPC_RES4330_TX_PWRSW_PU 17 #define CHIPC_RES4330_BB_PWRSW_PU 18 #define CHIPC_RES4330_SYNTH_PWRSW_PU 19 #define CHIPC_RES4330_MISC_PWRSW_PU 20 #define CHIPC_RES4330_LOGEN_PWRSW_PU 21 #define CHIPC_RES4330_BBPLL_PWRSW_PU 22 #define CHIPC_RES4330_MACPHY_CLKAVAIL 23 #define CHIPC_RES4330_HT_AVAIL 24 #define CHIPC_RES4330_5gRX_PWRSW_PU 25 #define CHIPC_RES4330_5gTX_PWRSW_PU 26 #define CHIPC_RES4330_5g_LOGEN_PWRSW_PU 27 /* 4330 chip-specific ChipStatus register bits */ #define CHIPC_CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6) /* SDIO || gSPI */ #define CHIPC_CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6) /* USB || USBDA */ #define CHIPC_CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0) /* SDIO */ #define CHIPC_CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4) /* gSPI */ #define CHIPC_CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6) /* USB packet-oriented */ #define CHIPC_CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7) /* USB Direct Access */ #define CHIPC_CST4330_OTP_PRESENT 0x00000010 #define CHIPC_CST4330_LPO_AUTODET_EN 0x00000020 #define CHIPC_CST4330_ARMREMAP_0 0x00000040 #define CHIPC_CST4330_SPROM_PRESENT 0x00000080 /* takes priority over OTP if both set */ #define CHIPC_CST4330_ILPDIV_EN 0x00000100 #define CHIPC_CST4330_LPO_SEL 0x00000200 #define CHIPC_CST4330_RES_INIT_MODE_SHIFT 10 #define CHIPC_CST4330_RES_INIT_MODE_MASK 0x00000c00 #define CHIPC_CST4330_CBUCK_MODE_SHIFT 12 #define CHIPC_CST4330_CBUCK_MODE_MASK 0x00003000 #define CHIPC_CST4330_CBUCK_POWER_OK 0x00004000 #define CHIPC_CST4330_BB_PLL_LOCKED 0x00008000 #define CHIPC_SOCDEVRAM_4330_BP_ADDR 0x1E000000 #define CHIPC_SOCDEVRAM_4330_ARM_ADDR 0x00800000 /* 4313 resources */ #define CHIPC_RES4313_BB_PU_RSRC 0 #define CHIPC_RES4313_ILP_REQ_RSRC 1 #define CHIPC_RES4313_XTAL_PU_RSRC 2 #define CHIPC_RES4313_ALP_AVAIL_RSRC 3 #define CHIPC_RES4313_RADIO_PU_RSRC 4 #define CHIPC_RES4313_BG_PU_RSRC 5 #define CHIPC_RES4313_VREG1P4_PU_RSRC 6 #define CHIPC_RES4313_AFE_PWRSW_RSRC 7 #define CHIPC_RES4313_RX_PWRSW_RSRC 8 #define CHIPC_RES4313_TX_PWRSW_RSRC 9 #define CHIPC_RES4313_BB_PWRSW_RSRC 10 #define CHIPC_RES4313_SYNTH_PWRSW_RSRC 11 #define CHIPC_RES4313_MISC_PWRSW_RSRC 12 #define CHIPC_RES4313_BB_PLL_PWRSW_RSRC 13 #define CHIPC_RES4313_HT_AVAIL_RSRC 14 #define CHIPC_RES4313_MACPHY_CLK_AVAIL_RSRC 15 /* 4313 chip-specific ChipStatus register bits */ #define CHIPC_CST4313_SPROM_PRESENT 1 #define CHIPC_CST4313_OTP_PRESENT 2 #define CHIPC_CST4313_SPROM_OTP_SEL_MASK 0x00000002 #define CHIPC_CST4313_SPROM_OTP_SEL_SHIFT 0 /* 4313 Chip specific ChipControl register bits */ #define CHIPC_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ /* 43228 resources */ #define CHIPC_RES43228_NOT_USED 0 #define CHIPC_RES43228_ILP_REQUEST 1 #define CHIPC_RES43228_XTAL_PU 2 #define CHIPC_RES43228_ALP_AVAIL 3 #define CHIPC_RES43228_PLL_EN 4 #define CHIPC_RES43228_HT_PHY_AVAIL 5 /* 43228 chipstatus reg bits */ #define CHIPC_CST43228_ILP_DIV_EN 0x1 #define CHIPC_CST43228_OTP_PRESENT 0x2 #define CHIPC_CST43228_SERDES_REFCLK_PADSEL 0x4 #define CHIPC_CST43228_SDIO_MODE 0x8 #define CHIPC_CST43228_SDIO_OTP_PRESENT 0x10 #define CHIPC_CST43228_SDIO_RESET 0x20 /* * Maximum delay for the PMU state transition in us. * This is an upper bound intended for spinwaits etc. */ #define CHIPC_PMU_MAX_TRANSITION_DLY 15000 /* PMU resource up transition time in ILP cycles */ #define CHIPC_PMURES_UP_TRANSITION 2 /* * Register eci_inputlo bitfield values. * - BT packet type information bits [7:0] */ /* [3:0] - Task (link) type */ #define CHIPC_BT_ACL 0x00 #define CHIPC_BT_SCO 0x01 #define CHIPC_BT_eSCO 0x02 #define CHIPC_BT_A2DP 0x03 #define CHIPC_BT_SNIFF 0x04 #define CHIPC_BT_PAGE_SCAN 0x05 #define CHIPC_BT_INQUIRY_SCAN 0x06 #define CHIPC_BT_PAGE 0x07 #define CHIPC_BT_INQUIRY 0x08 #define CHIPC_BT_MSS 0x09 #define CHIPC_BT_PARK 0x0a #define CHIPC_BT_RSSISCAN 0x0b #define CHIPC_BT_MD_ACL 0x0c #define CHIPC_BT_MD_eSCO 0x0d #define CHIPC_BT_SCAN_WITH_SCO_LINK 0x0e #define CHIPC_BT_SCAN_WITHOUT_SCO_LINK 0x0f /* [7:4] = packet duration code */ /* [8] - Master / Slave */ #define CHIPC_BT_MASTER 0 #define CHIPC_BT_SLAVE 1 /* [11:9] - multi-level priority */ #define CHIPC_BT_LOWEST_PRIO 0x0 #define CHIPC_BT_HIGHEST_PRIO 0x3 #endif /* _BHND_CORES_CHIPC_CHIPCREG_H_ */ Index: head/sys/mips/broadcom/bcm_bcma.c =================================================================== --- head/sys/mips/broadcom/bcm_bcma.c (nonexistent) +++ head/sys/mips/broadcom/bcm_bcma.c (revision 304859) @@ -0,0 +1,100 @@ +/*- + * Copyright (c) 2016 Landon Fuller + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include + +#include + +#include +#include + +#include "bcm_machdep.h" + +#define BCMFC_ERR(fmt, ...) printf("%s: " fmt, __FUNCTION__, ##__VA_ARGS__) + +int +bcm_find_core_bcma(struct bhnd_chipid *chipid, bhnd_devclass_t devclass, + int unit, struct bhnd_core_info *info, uintptr_t *addr) +{ + struct bcma_erom erom; + struct bcma_erom_core core; + struct bcma_erom_sport_region region; + bhnd_devclass_t core_class; + int error; + + error = bhnd_erom_bus_space_open(&erom, NULL, mips_bus_space_generic, + (bus_space_handle_t) BCM_SOC_ADDR(chipid->enum_addr, 0), 0); + if (error) { + BCMFC_ERR("erom open failed: %d\n", error); + return (error); + } + + for (u_long core_index = 0; core_index < ULONG_MAX; core_index++) { + /* Fetch next core record */ + if ((error = bcma_erom_seek_next_core(&erom))) + return (error); + + if ((error = bcma_erom_parse_core(&erom, &core))) { + BCMFC_ERR("core parse failed: %d\n", error); + return (error); + } + + /* Check for match */ + core_class = bhnd_find_core_class(core.vendor, + core.device); + if (core_class != devclass) + continue; + + /* Provide the basic core info */ + if (info != NULL) + bcma_erom_to_core_info(&core, core_index, 0, info); + + /* Provide the core's device0.0 port address */ + error = bcma_erom_seek_core_sport_region(&erom, core_index, + BHND_PORT_DEVICE, 0, 0); + if (error) { + BCMFC_ERR("sport not found: %d\n", error); + return (error); + } + + if ((error = bcma_erom_parse_sport_region(&erom, ®ion))) { + BCMFC_ERR("sport parse failed: %d\n", error); + return (error); + } + + if (addr != NULL) + *addr = region.base_addr; + + return (0); + } + + /* Not found */ + return (ENOENT); +} Property changes on: head/sys/mips/broadcom/bcm_bcma.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/mips/broadcom/bcm_machdep.c =================================================================== --- head/sys/mips/broadcom/bcm_machdep.c (revision 304858) +++ head/sys/mips/broadcom/bcm_machdep.c (revision 304859) @@ -1,288 +1,436 @@ /*- * Copyright (c) 2007 Bruce M. Simpson. * Copyright (c) 2016 Michael Zhilin + * Copyright (c) 2016 Landon Fuller * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_ddb.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include +#include +#include + +#include + +#include +#include + +#include + +#include "bcm_machdep.h" +#include "bcm_mips_exts.h" #include "bcm_socinfo.h" #ifdef CFE #include #endif #if 0 #define BCM_TRACE(_fmt, ...) printf(_fmt, ##__VA_ARGS__) #else #define BCM_TRACE(_fmt, ...) #endif -extern int *edata; -extern int *end; +static int bcm_find_core(struct bhnd_chipid *chipid, + bhnd_devclass_t devclass, int unit, + struct bhnd_core_info *info, uintptr_t *addr); +static int bcm_init_platform_data(struct bcm_platform *pdata); +/* Allow bus-specific implementations to override bcm_find_core_(bcma|siba) + * symbols, if included in the kernel build */ +__weak_reference(bcm_find_core_default, bcm_find_core_bcma); +__weak_reference(bcm_find_core_default, bcm_find_core_siba); + +extern int *edata; +extern int *end; + +static struct bcm_platform bcm_platform_data; +static bool bcm_platform_data_avail = false; + +struct bcm_platform * +bcm_get_platform(void) +{ + if (!bcm_platform_data_avail) + panic("platform data not available"); + + return (&bcm_platform_data); +} + +/* Default (no-op) bcm_find_core() implementation. */ +int +bcm_find_core_default(struct bhnd_chipid *chipid, bhnd_devclass_t devclass, + int unit, struct bhnd_core_info *info, uintptr_t *addr) +{ + return (ENODEV); +} + +/** + * Search @p chipid's enumeration table for a core with @p devclass and + * @p unit. + * + * @param chipid Chip identification data, including the address + * of the enumeration table to be searched. + * @param devclass Search for a core matching this device class. + * @param unit The core's required unit number. + * @param[out] info On success, will be populated with the core + * info. + */ +static int +bcm_find_core(struct bhnd_chipid *chipid, bhnd_devclass_t devclass, int unit, + struct bhnd_core_info *info, uintptr_t *addr) +{ + switch (chipid->chip_type) { + case BHND_CHIPTYPE_SIBA: + return (bcm_find_core_siba(chipid, devclass, unit, info, addr)); + break; + default: + if (!BHND_CHIPTYPE_HAS_EROM(chipid->chip_type)) { + printf("%s: unsupported chip type: %d\n", __FUNCTION__, + chipid->chip_type); + return (ENXIO); + } + return (bcm_find_core_bcma(chipid, devclass, unit, info, addr)); + } +} + +/** + * Populate platform configuration data. + */ +static int +bcm_init_platform_data(struct bcm_platform *pdata) +{ + uint32_t reg; + bhnd_addr_t enum_addr; + long maddr; + uint8_t chip_type; + bool aob, pmu; + int error; + + /* Fetch CFE console handle (if any). Must be initialized before + * any calls to printf/early_putc. */ +#ifdef CFE + if ((pdata->cfe_console = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE)) < 0) + pdata->cfe_console = -1; +#endif + + /* Fetch bhnd/chipc address */ + if (resource_long_value("bhnd", 0, "maddr", &maddr) == 0) + pdata->cc_addr = (u_long)maddr; + else + pdata->cc_addr = BHND_DEFAULT_CHIPC_ADDR; + + /* Read chip identifier from ChipCommon */ + reg = BCM_SOC_READ_4(pdata->cc_addr, CHIPC_ID); + chip_type = CHIPC_GET_BITS(reg, CHIPC_ID_BUS); + + if (BHND_CHIPTYPE_HAS_EROM(chip_type)) + enum_addr = BCM_SOC_READ_4(pdata->cc_addr, CHIPC_EROMPTR); + else + enum_addr = pdata->cc_addr; + + pdata->id = bhnd_parse_chipid(reg, enum_addr); + + /* Fetch chipc core info and capabilities */ + pdata->cc_caps = BCM_SOC_READ_4(pdata->cc_addr, CHIPC_CAPABILITIES); + + error = bcm_find_core(&pdata->id, BHND_DEVCLASS_CC, 0, &pdata->cc_id, + NULL); + if (error) { + printf("%s: error locating chipc core: %d", __FUNCTION__, + error); + return (error); + } + + if (CHIPC_HWREV_HAS_CAP_EXT(pdata->cc_id.hwrev)) { + pdata->cc_caps_ext = BCM_SOC_READ_4(pdata->cc_addr, + CHIPC_CAPABILITIES_EXT); + } else { + pdata->cc_caps_ext = 0x0; + } + + /* Fetch PMU info */ + pmu = CHIPC_GET_FLAG(pdata->cc_caps, CHIPC_CAP_PMU); + aob = CHIPC_GET_FLAG(pdata->cc_caps_ext, CHIPC_CAP2_AOB); + + if (pmu && aob) { + /* PMU block mapped to a PMU core on the Always-on-Bus (aob) */ + error = bcm_find_core(&pdata->id, BHND_DEVCLASS_PMU, 0, + &pdata->pmu_id, &pdata->pmu_addr); + + if (error) { + printf("%s: error locating pmu core: %d", __FUNCTION__, + error); + return (error); + } + } else if (pmu) { + /* PMU block mapped to chipc */ + pdata->pmu_addr = pdata->cc_addr; + pdata->pmu_id = pdata->cc_id; + } else { + /* No PMU */ + pdata->pmu_addr = 0x0; + memset(&pdata->pmu_id, 0, sizeof(pdata->pmu_id)); + } + + bcm_platform_data_avail = true; + return (0); +} + void platform_cpu_init() { /* Nothing special */ } static void mips_init(void) { int i, j; printf("entry: mips_init()\n"); #ifdef CFE /* * Query DRAM memory map from CFE. */ physmem = 0; for (i = 0; i < 10; i += 2) { int result; uint64_t addr, len, type; result = cfe_enummem(i / 2, 0, &addr, &len, &type); if (result < 0) { BCM_TRACE("There is no phys memory for: %d\n", i); phys_avail[i] = phys_avail[i + 1] = 0; break; } if (type != CFE_MI_AVAILABLE) { BCM_TRACE("phys memory is not available: %d\n", i); continue; } phys_avail[i] = addr; if (i == 0 && addr == 0) { /* * If this is the first physical memory segment probed * from CFE, omit the region at the start of physical * memory where the kernel has been loaded. */ phys_avail[i] += MIPS_KSEG0_TO_PHYS(kernel_kseg0_end); } BCM_TRACE("phys memory is available for: %d\n", i); BCM_TRACE(" => addr = %jx\n", addr); BCM_TRACE(" => len = %jd\n", len); phys_avail[i + 1] = addr + len; physmem += len; } BCM_TRACE("Total phys memory is : %ld\n", physmem); realmem = btoc(physmem); #endif for (j = 0; j < i; j++) dump_avail[j] = phys_avail[j]; physmem = realmem; init_param1(); init_param2(physmem); mips_cpu_init(); pmap_bootstrap(); mips_proc0_init(); mutex_init(); kdb_init(); #ifdef KDB if (boothowto & RB_KDB) kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); #endif } void platform_reset(void) { + bool bcm4785war; + printf("bcm::platform_reset()\n"); intr_disable(); -#if defined(CFE) - cfe_exit(0, 0); -#else - /* PMU watchdog reset */ - BCM_WRITE_REG32(BCM_REG_CHIPC_PMUWD_OFFS, 2); /* PMU watchdog */ +#ifdef CFE + /* Fall back on CFE if reset requested during platform + * data initialization */ + if (!bcm_platform_data_avail) { + cfe_exit(0, 0); + while (1); + } #endif -#if 0 - /* Non-PMU reset - * XXX: Need chipc capability flags */ - *((volatile uint8_t *)MIPS_PHYS_TO_KSEG1(SENTRY5_EXTIFADR)) = 0x80; -#endif - - for (;;); + /* Handle BCM4785-specific behavior */ + bcm4785war = false; + if (bcm_get_platform()->id.chip_id == BHND_CHIPID_BCM4785) { + bcm4785war = true; + + /* Switch to async mode */ + bcm_mips_wr_pllcfg3(MIPS_BCMCFG_PLLCFG3_SM); + } + + /* Set watchdog (PMU or ChipCommon) */ + if (bcm_get_platform()->pmu_addr != 0x0) { + BCM_CHIPC_WRITE_4(CHIPC_PMU_WATCHDOG, 1); + } else + BCM_CHIPC_WRITE_4(CHIPC_WATCHDOG, 1); + + /* BCM4785 */ + if (bcm4785war) { + mips_sync(); + __asm __volatile("wait"); + } + + while (1); } void platform_start(__register_t a0, __register_t a1, __register_t a2, __register_t a3) { vm_offset_t kernend; uint64_t platform_counter_freq; struct bcm_socinfo *socinfo; + int error; /* clear the BSS and SBSS segments */ kernend = (vm_offset_t)&end; memset(&edata, 0, kernend - (vm_offset_t)(&edata)); mips_postboot_fixup(); /* Initialize pcpu stuff */ mips_pcpu0_init(); #ifdef CFE /* * Initialize CFE firmware trampolines. This must be done * before any CFE APIs are called, including writing * to the CFE console. * * CFE passes the following values in registers: * a0: firmware handle * a2: firmware entry point * a3: entry point seal */ if (a3 == CFE_EPTSEAL) cfe_init(a0, a2); #endif -#if 0 - /* - * Probe the Broadcom on-chip PLL clock registers - * and discover the CPU pipeline clock and bus clock - * multipliers from this. - * XXX: Wrong place. You have to ask the ChipCommon - * or External Interface cores on the SiBa. - */ - uint32_t busmult, cpumult, refclock, clkcfg1; -#define S5_CLKCFG1_REFCLOCK_MASK 0x0000001F -#define S5_CLKCFG1_BUSMULT_MASK 0x000003E0 -#define S5_CLKCFG1_BUSMULT_SHIFT 5 -#define S5_CLKCFG1_CPUMULT_MASK 0xFFFFFC00 -#define S5_CLKCFG1_CPUMULT_SHIFT 10 + /* Init BCM platform data */ + if ((error = bcm_init_platform_data(&bcm_platform_data))) + panic("bcm_init_platform_data() failed: %d", error); - counter_freq = 100000000; /* XXX */ - - clkcfg1 = s5_rd_clkcfg1(); - printf("clkcfg1 = 0x%08x\n", clkcfg1); - - refclock = clkcfg1 & 0x1F; - busmult = ((clkcfg1 & 0x000003E0) >> 5) + 1; - cpumult = ((clkcfg1 & 0xFFFFFC00) >> 10) + 1; - - printf("refclock = %u\n", refclock); - printf("busmult = %u\n", busmult); - printf("cpumult = %u\n", cpumult); - - counter_freq = cpumult * refclock; -#endif - socinfo = bcm_get_socinfo(); platform_counter_freq = socinfo->cpurate * 1000 * 1000; /* BCM4718 is 480MHz */ mips_timer_early_init(platform_counter_freq); cninit(); mips_init(); mips_timer_init_params(platform_counter_freq, socinfo->double_count); } /* * CFE-based EARLY_PRINTF support. To use, add the following to the kernel * config: * option EARLY_PRINTF * option CFE * device cfe */ #if defined(EARLY_PRINTF) && defined(CFE) static void bcm_cfe_eputc(int c) { - static int fd = -1; unsigned char ch; + int handle; ch = (unsigned char) c; - if (fd == -1) { - if ((fd = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE)) < 0) - return; - } + /* bcm_get_platform() cannot be used here, as we may be called + * from bcm_init_platform_data(). */ + if ((handle = bcm_platform_data.cfe_console) < 0) + return; if (ch == '\n') early_putc('\r'); - while ((cfe_write(fd, &ch, 1)) == 0) + while ((cfe_write(handle, &ch, 1)) == 0) continue; } early_putc_t *early_putc = bcm_cfe_eputc; #endif /* EARLY_PRINTF */ Index: head/sys/mips/broadcom/bcm_machdep.h =================================================================== --- head/sys/mips/broadcom/bcm_machdep.h (nonexistent) +++ head/sys/mips/broadcom/bcm_machdep.h (revision 304859) @@ -0,0 +1,93 @@ +/*- + * Copyright (c) 2016 Landon Fuller + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ + +#ifndef _MIPS_BROADCOM_BCM_MACHDEP_H_ +#define _MIPS_BROADCOM_BCM_MACHDEP_H_ + +#include +#include + +#include + +struct bcm_platform { + struct bhnd_chipid id; /**< chip id */ + struct bhnd_core_info cc_id; /**< chipc core info */ + uintptr_t cc_addr; /**< chipc core phys address */ + uint32_t cc_caps; /**< chipc capabilities */ + uint32_t cc_caps_ext; /**< chipc extended capabilies */ + + /* On non-AOB devices, the PMU register block is mapped to chipc; + * the pmu_id and pmu_addr values will be copied from cc_id + * and cc_addr. */ + struct bhnd_core_info pmu_id; /**< PMU core info */ + uintptr_t pmu_addr; /**< PMU core phys address. */ + +#ifdef CFE + int cfe_console; /**< Console handle, or -1 */ +#endif +}; + + +typedef int (bcm_bus_find_core)(struct bhnd_chipid *chipid, + bhnd_devclass_t devclass, int unit, struct bhnd_core_info *info, + uintptr_t *addr); + +struct bcm_platform *bcm_get_platform(void); + +bcm_bus_find_core bcm_find_core_default; +bcm_bus_find_core bcm_find_core_bcma; +bcm_bus_find_core bcm_find_core_siba; + +#define BCM_SOC_ADDR(_addr, _offset) \ + MIPS_PHYS_TO_KSEG1((_addr) + (_offset)) + +#define BCM_SOC_READ_4(_addr, _offset) \ + readl(BCM_SOC_ADDR((_addr), (_offset))) +#define BCM_SOC_WRITE_4(_addr, _reg, _val) \ + writel(BCM_SOC_ADDR((_addr), (_offset)), (_val)) + +#define BCM_CORE_ADDR(_name, _reg) \ + BCM_SOC_ADDR(bcm_get_platform()->_name, (_reg)) + +#define BCM_CORE_READ_4(_name, _reg) \ + readl(BCM_CORE_ADDR(_name, (_reg))) +#define BCM_CORE_WRITE_4(_name, _reg, _val) \ + writel(BCM_CORE_ADDR(_name, (_reg)), (_val)) + +#define BCM_CHIPC_READ_4(_reg) BCM_CORE_READ_4(cc_addr, (_reg)) +#define BCM_CHIPC_WRITE_4(_reg, _val) \ + BCM_CORE_WRITE_4(cc_addr, (_reg), (_val)) + +#define BCM_PMU_READ_4(_reg) BCM_CORE_READ_4(pmu_addr, (_reg)) +#define BCM_PMU_WRITE_4(_reg, _val) \ + BCM_CORE_WRITE_4(pmu_addr, (_reg), (_val)) + +#endif /* _MIPS_BROADCOM_BCM_MACHDEP_H_ */ Property changes on: head/sys/mips/broadcom/bcm_machdep.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/mips/broadcom/bcm_mips_exts.h =================================================================== --- head/sys/mips/broadcom/bcm_mips_exts.h (nonexistent) +++ head/sys/mips/broadcom/bcm_mips_exts.h (revision 304859) @@ -0,0 +1,190 @@ +/*- + * Copyright 2000,2001,2002,2003 Broadcom Corporation. + * All rights reserved. + * + * This file is derived from the sbmips32.h header distributed + * by Broadcom with the CFE 1.4.2 sources. + * + * This software is furnished under license and may be used and + * copied only in accordance with the following terms and + * conditions. Subject to these conditions, you may download, + * copy, install, use, modify and distribute modified or unmodified + * copies of this software in source and/or binary form. No title + * or ownership is transferred hereby. + * + * 1) Any source code used, modified or distributed must reproduce + * and retain this copyright notice and list of conditions + * as they appear in the source file. + * + * 2) No right is granted to use any trade name, trademark, or + * logo of Broadcom Corporation. The "Broadcom Corporation" + * name may not be used to endorse or promote products derived + * from this software without the prior written permission of + * Broadcom Corporation. + * + * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED + * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR + * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT + * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN + * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + + +/* ********************************************************************* + * Broadcom Common Firmware Environment (CFE) + * + * MIPS32 CPU definitions File: sbmips32.h + * + * This module contains constants and macros specific to the + * Broadcom MIPS32 core. In addition to generic MIPS32, it + * includes definitions for the MIP32-01 and MIPS3302 OCP cores + * for the Silicon Backplane. + * + *********************************************************************/ + +#ifndef _MIPS_BROADCOM_BCM_MIPS_EXTS_H_ +#define _MIPS_BROADCOM_BCM_MIPS_EXTS_H_ + +#include + +/* + * The following Broadcom Custom CP0 Registers appear in the Broadcom + * BMIPS330x MIPS32 core. + */ + +#define MIPS_COP_0_BCMCFG 22 + +/* + * Custom CP0 Accessors + */ + +#define BCM_MIPS_RW32_COP0_SEL(n,r,s) \ +static __inline uint32_t \ +bcm_mips_rd_ ## n(void) \ +{ \ + int v0; \ + __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \ + : [v0] "=&r"(v0)); \ + mips_barrier(); \ + return (v0); \ +} \ +static __inline void \ +bcm_mips_wr_ ## n(uint32_t a0) \ +{ \ + __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \ + __XSTRING(COP0_SYNC)";" \ + "nop;" \ + "nop;" \ + : \ + : [a0] "r"(a0)); \ + mips_barrier(); \ +} struct __hack + +BCM_MIPS_RW32_COP0_SEL(pllcfg1, MIPS_COP_0_CONFIG, 1); +BCM_MIPS_RW32_COP0_SEL(pllcfg2, MIPS_COP_0_CONFIG, 2); +BCM_MIPS_RW32_COP0_SEL(clksync, MIPS_COP_0_CONFIG, 3); +BCM_MIPS_RW32_COP0_SEL(pllcfg3, MIPS_COP_0_CONFIG, 4); +BCM_MIPS_RW32_COP0_SEL(rstcfg, MIPS_COP_0_CONFIG, 5); + +/* + * Broadcom PLLConfig1 Register (22, select 1) + */ + +/* SoftMIPSPLLCfg */ +#define MIPS_BCMCFG_PLLCFG1_MC_SHIFT 10 +#define MIPS_BCMCFG_PLLCFG1_MC_MASK 0xFFFFFC00 + +/* SoftISBPLLCfg */ +#define MIPS_BCMCFG_PLLCFG1_BC_SHIFT 5 +#define MIPS_BCMCFG_PLLCFG1_BC_MASK 0x000003E0 + +/* SoftRefPLLCfg */ +#define MIPS_BCMCFG_PLLCFG1_PC_SHIFT 0 +#define MIPS_BCMCFG_PLLCFG1_PC_MASK 0x0000001F + +/* + * Broadcom PLLConfig2 Register (22, select 2) + */ + +/* Soft1to1ClkRatio */ +#define MIPS_BCMCFG_PLLCFG2_CR (1<<23) + +/* SoftUSBxPLLCfg */ +#define MIPS_BCMCFG_PLLCFG2_UC_SHIFT 15 +#define MIPS_BCMCFG_PLLCFG2_UC_MASK 0x007F8000 + +/* SoftIDExPLLCfg */ +#define MIPS_BCMCFG_PLLCFG2_IC_SHIFT 7 +#define MIPS_BCMCFG_PLLCFG2_IC_MASK 0x00007F80 + +#define MIPS_BCMCFG_PLLCFG2_BE (1<<6) /* ISBxSoftCfgEnable */ +#define MIPS_BCMCFG_PLLCFG2_UE (1<<5) /* USBxSoftCfgEnable */ +#define MIPS_BCMCFG_PLLCFG2_IE (1<<4) /* IDExSoftCfgEnable */ +#define MIPS_BCMCFG_PLLCFG2_CA (1<<3) /* CfgActive */ +#define MIPS_BCMCFG_PLLCFG2_CF (1<<2) /* RefSoftCfgEnable */ +#define MIPS_BCMCFG_PLLCFG2_CI (1<<1) /* ISBSoftCfgEnable */ +#define MIPS_BCMCFG_PLLCFG2_CC (1<<0) /* MIPSSoftCfgEnable */ + +/* + * Broadcom ClkSync Register (22, select 3) + */ +/* SoftClkCfgHigh */ +#define MIPS_BCMCFG_CLKSYNC_CH_SHIFT 16 +#define MIPS_BCMCFG_CLKSYNC_CH_MASK 0xFFFF0000 + +/* SoftClkCfgLow */ +#define MIPS_BCMCFG_CLKSYNC_CL_SHIFT 0 +#define MIPS_BCMCFG_CLKSYNC_CL_MASK 0x0000FFFF + +/* + * Broadcom ISBxPLLConfig3 Register (22, select 4) + */ + +/* AsyncClkRatio */ +#define MIPS_BCMCFG_PLLCFG3_AR_SHIFT 23 +#define MIPS_BCMCFG_PLLCFG3_AR_MASK 0x01800000 + +#define MIPS_BCMCFG_PLLCFG3_SM (1<<22) /* SyncMode */ + +/* SoftISBxPLLCfg */ +#define MIPS_BCMCFG_PLLCFG3_IC_SHIFT 0 +#define MIPS_BCMCFG_PLLCFG3_IC_MASK 0x003FFFFF + +/* + * Broadcom BRCMRstConfig Register (22, select 5) + */ + +#define MIPS_BCMCFG_RSTCFG_SR (1<<18) /* SSMR */ +#define MIPS_BCMCFG_RSTCFG_DT (1<<16) /* BHTD */ + +/* RStSt */ +#define MIPS_BCMCFG_RSTCFG_RS_SHIFT 8 +#define MIPS_BCMCFG_RSTCFG_RS_MASK 0x00001F00 +#define MIPS_BCMCFG_RST_OTHER 0x00 +#define MIPS_BCMCFG_RST_SH 0x01 +#define MIPS_BCMCFG_RST_SS 0x02 +#define MIPS_BCMCFG_RST_EJTAG 0x04 +#define MIPS_BCMCFG_RST_WDOG 0x08 +#define MIPS_BCMCFG_RST_CRC 0x10 + +#define MIPS_BCMCFG_RSTCFG_CR (1<<7) /* RStCr */ + +/* WBMD */ +#define MIPS_BCMCFG_RSTCFG_WD_SHIFT 3 +#define MIPS_BCMCFG_RSTCFG_WD_MASK 0x00000078 + +#define MIPS_BCMCFG_RSTCFG_SS (1<<2) /* SSR */ +#define MIPS_BCMCFG_RSTCFG_SH (1<<1) /* SHR */ +#define MIPS_BCMCFG_RSTCFG_BR (1<<0) /* BdR */ + +#endif /* _MIPS_BROADCOM_BCM_MIPS_EXTS_H_ */ Property changes on: head/sys/mips/broadcom/bcm_mips_exts.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/mips/broadcom/bcm_siba.c =================================================================== --- head/sys/mips/broadcom/bcm_siba.c (nonexistent) +++ head/sys/mips/broadcom/bcm_siba.c (revision 304859) @@ -0,0 +1,64 @@ +/*- + * Copyright (c) 2016 Landon Fuller + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include + +#include +#include + +#include "bcm_machdep.h" + +int +bcm_find_core_siba(struct bhnd_chipid *chipid, bhnd_devclass_t devclass, + int unit, struct bhnd_core_info *info, uintptr_t *addr) +{ + struct siba_core_id scid; + uintptr_t cc_addr; + uint32_t idhigh, idlow; + + /* No other cores are required during early boot on siba(4) devices */ + if (devclass != BHND_DEVCLASS_CC || unit != 0) + return (ENOENT); + + cc_addr = chipid->enum_addr; + idhigh = BCM_SOC_READ_4(cc_addr, SB0_REG_ABS(SIBA_CFG0_IDHIGH)); + idlow = BCM_SOC_READ_4(cc_addr, SB0_REG_ABS(SIBA_CFG0_IDHIGH)); + + scid = siba_parse_core_id(idhigh, idlow, 0, 0); + + if (info != NULL) + *info = scid.core_info; + + if (addr != NULL) + *addr = cc_addr; + + return (0); +} Property changes on: head/sys/mips/broadcom/bcm_siba.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/mips/broadcom/bcm_socinfo.c =================================================================== --- head/sys/mips/broadcom/bcm_socinfo.c (revision 304858) +++ head/sys/mips/broadcom/bcm_socinfo.c (revision 304859) @@ -1,91 +1,95 @@ /*- * Copyright (c) 2016 Michael Zhilin * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include + +#include + +#include "bcm_machdep.h" #include "bcm_socinfo.h" /* found on https://wireless.wiki.kernel.org/en/users/drivers/b43/soc */ struct bcm_socinfo bcm_socinfos[] = { {0x00005300, 600, 25000000, 1}, /* BCM4706 to check */ {0x0022B83A, 300, 20000000, 1}, /* BCM4716B0 ASUS RT-N12 */ {0x00914716, 354, 20000000, 1}, /* BCM4717A1 to check */ {0x00A14716, 480, 20000000, 1}, /* BCM4718A1 ASUS RT-N16 */ {0x00435356, 300, 25000000, 1}, /* BCM5356A1 (RT-N10, WNR1000v3) */ {0x00825357, 500, 20000000, 1}, /* BCM5358UB0 ASUS RT-N53A1 */ {0x00845357, 300, 20000000, 1}, /* BCM5357B0 to check */ {0x00945357, 500, 20000000, 1}, /* BCM5358 */ {0x00A45357, 500, 20000000, 1}, /* BCM47186B0 Tenda N60 */ {0x0085D144, 300, 20000000, 1}, /* BCM5356C0 */ {0x00B5D144, 300, 20000000, 1}, /* BCM5357C0 */ {0x00015365, 200, 0, 1}, /* BCM5365 */ {0,0,0} }; /* Most popular BCM SoC info */ struct bcm_socinfo BCM_DEFAULT_SOCINFO = {0x0, 300, 20000000, 0}; struct bcm_socinfo* bcm_get_socinfo_by_socid(uint32_t key) { struct bcm_socinfo* start; if(!key) return (NULL); for(start = bcm_socinfos; start->id > 0; start++) if(start->id == key) return (start); return (NULL); } struct bcm_socinfo* bcm_get_socinfo(void) { uint32_t socid; struct bcm_socinfo *socinfo; /* * We need Chip ID + Revision + Package * -------------------------------------------------------------- * | Mask | Usage | * -------------------------------------------------------------- * | 0x0000FFFF | Chip ID | * | 0x000F0000 | Chip Revision | * | 0x00F00000 | Package Options | * | 0x0F000000 | Number of Cores (ChipCommon Rev. >= 4)| * | 0xF0000000 | Chip Type | * -------------------------------------------------------------- */ - socid = BCM_READ_REG32(BCM_REG_CHIPC_ID) & 0x00FFFFFF; + socid = BCM_CHIPC_READ_4(CHIPC_ID) & 0x00FFFFFF; socinfo = bcm_get_socinfo_by_socid(socid); return (socinfo != NULL) ? socinfo : &BCM_DEFAULT_SOCINFO; } Index: head/sys/mips/broadcom/bcm_socinfo.h =================================================================== --- head/sys/mips/broadcom/bcm_socinfo.h (revision 304858) +++ head/sys/mips/broadcom/bcm_socinfo.h (revision 304859) @@ -1,60 +1,47 @@ /*- * Copyright (c) 2016 Michael Zhilin * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * $FreeBSD$ */ #ifndef _MIPS_BROADCOM_BCM_SOCINFO_H_ #define _MIPS_BROADCOM_BCM_SOCINFO_H_ #include struct bcm_socinfo { uint32_t id; uint32_t cpurate; /* in MHz */ uint32_t uartrate; /* in Hz */ int double_count; }; struct bcm_socinfo* bcm_get_socinfo_by_socid(uint32_t key); struct bcm_socinfo* bcm_get_socinfo(void); -#define BCM_SOCADDR 0x18000000 -#define BCM_REG_CHIPC_ID 0x0 -#define BCM_REG_CHIPC_UART 0x300 -#define BCM_REG_CHIPC_PMUWD_OFFS 0x634 -#define BCM_SOCREG(reg) \ - MIPS_PHYS_TO_KSEG1((BCM_SOCADDR + (reg))) -#define BCM_READ_REG32(reg) \ - *((volatile uint32_t *)BCM_SOCREG(reg)) -#define BCM_WRITE_REG32(reg, value) \ - do { \ - writel((void*)BCM_SOCREG((reg)),value); \ - } while (0); - #endif /* _MIPS_BROADCOM_BCM_SOCINFO_H_ */ Index: head/sys/mips/broadcom/files.broadcom =================================================================== --- head/sys/mips/broadcom/files.broadcom (revision 304858) +++ head/sys/mips/broadcom/files.broadcom (revision 304859) @@ -1,21 +1,23 @@ # $FreeBSD$ # TODO: Add attachment elsewhere in the tree # for USB 1.1 OHCI, Ethernet and IPSEC cores # which are believed to be devices we have drivers for # which just need to be tweaked for attachment to an BHND system bus. +mips/broadcom/bcm_bcma.c optional bcma_nexus bcma mips/broadcom/bcm_machdep.c standard +mips/broadcom/bcm_siba.c optional siba_nexus siba mips/mips/tick.c standard mips/mips/mips_pic.c standard kern/subr_intr.c standard kern/pic_if.m standard kern/msi_if.m optional intrng mips/broadcom/uart_cpu_chipc.c optional uart mips/broadcom/uart_bus_chipc.c optional uart mips/broadcom/bcm_socinfo.c standard mips/broadcom/bcm_mipscore.c standard # TODO: Replace with BCM47xx/57xx/etc-aware geom_map geom/geom_flashmap.c standard Index: head/sys/mips/broadcom/uart_cpu_chipc.c =================================================================== --- head/sys/mips/broadcom/uart_cpu_chipc.c (revision 304858) +++ head/sys/mips/broadcom/uart_cpu_chipc.c (revision 304859) @@ -1,173 +1,175 @@ /*- * Copyright (c) 2016 Michael Zhilin * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_uart.h" #include #include #include #include #include #include #include #include #include #include #include -#include "bcm_socinfo.h" - #ifdef CFE #include #include #include #endif +#include "bcm_machdep.h" +#include "bcm_socinfo.h" + bus_space_tag_t uart_bus_space_io; bus_space_tag_t uart_bus_space_mem; static struct uart_class *chipc_uart_class = &uart_ns8250_class; #define CHIPC_UART_BAUDRATE 115200 int uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2) { return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0); } static int uart_cpu_init(struct uart_devinfo *di, u_int uart, int baudrate) { struct bcm_socinfo *socinfo; if (uart >= CHIPC_UART_MAX) return (EINVAL); socinfo = bcm_get_socinfo(); di->ops = uart_getops(chipc_uart_class); di->bas.chan = 0; di->bas.bst = uart_bus_space_mem; - di->bas.bsh = (bus_space_handle_t) BCM_SOCREG(CHIPC_UART(uart)); + di->bas.bsh = (bus_space_handle_t) BCM_CORE_ADDR(cc_addr, + CHIPC_UART(uart)); di->bas.regshft = 0; di->bas.rclk = socinfo->uartrate; /* in Hz */ di->baudrate = baudrate; di->databits = 8; di->stopbits = 1; di->parity = UART_PARITY_NONE; return (0); } #ifdef CFE static int uart_getenv_cfe(int devtype, struct uart_devinfo *di) { char device[sizeof("uartXX")]; int baud, fd, len; int ret; u_int uart; /* CFE only vends console configuration */ if (devtype != UART_DEV_CONSOLE) return (ENODEV); /* Fetch console device */ ret = cfe_getenv("BOOT_CONSOLE", device, sizeof(device)); if (ret != CFE_OK) return (ENXIO); /* Parse serial console unit. Fails on non-uart devices. */ if (sscanf(device, "uart%u", &uart) != 1) return (ENXIO); /* Fetch device handle */ - fd = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE); + fd = bcm_get_platform()->cfe_console; if (fd < 0) return (ENXIO); /* Fetch serial configuration */ ret = cfe_ioctl(fd, IOCTL_SERIAL_GETSPEED, (unsigned char *)&baud, sizeof(baud), &len, 0); if (ret != CFE_OK) baud = CHIPC_UART_BAUDRATE; /* Initialize device info */ return (uart_cpu_init(di, uart, baud)); } #endif /* CFE */ int uart_cpu_getdev(int devtype, struct uart_devinfo *di) { int ivar; uart_bus_space_io = NULL; uart_bus_space_mem = mips_bus_space_generic; #ifdef CFE /* Check the CFE environment */ if (uart_getenv_cfe(devtype, di) == 0) return (0); #endif /* CFE */ /* Check the kernel environment. */ if (uart_getenv(devtype, di, chipc_uart_class) == 0) return (0); /* Scan the device hints for the first matching device */ for (u_int i = 0; i < CHIPC_UART_MAX; i++) { if (resource_int_value("uart", i, "flags", &ivar)) continue; /* Check usability */ if (devtype == UART_DEV_CONSOLE && !UART_FLAGS_CONSOLE(ivar)) continue; if (devtype == UART_DEV_DBGPORT && !UART_FLAGS_DBGPORT(ivar)) continue; if (resource_int_value("uart", i, "disabled", &ivar) == 0 && ivar == 0) continue; /* Found */ if (resource_int_value("uart", i, "baud", &ivar) != 0) ivar = CHIPC_UART_BAUDRATE; return (uart_cpu_init(di, i, ivar)); } /* Default to uart0/115200 */ return (uart_cpu_init(di, 0, CHIPC_UART_BAUDRATE)); }