Index: head/sys/dev/etherswitch/arswitch/arswitch.c =================================================================== --- head/sys/dev/etherswitch/arswitch/arswitch.c (revision 303809) +++ head/sys/dev/etherswitch/arswitch/arswitch.c (revision 303810) @@ -1,989 +1,1006 @@ /*- * Copyright (c) 2011-2012 Stefan Bethke. * Copyright (c) 2012 Adrian Chadd. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "mdio_if.h" #include "miibus_if.h" #include "etherswitch_if.h" -#if defined(DEBUG) -static SYSCTL_NODE(_debug, OID_AUTO, arswitch, CTLFLAG_RD, 0, "arswitch"); -#endif - /* Map ETHERSWITCH_PORT_LED_* to Atheros pattern codes */ static int led_pattern_table[] = { [ETHERSWITCH_PORT_LED_DEFAULT] = 0x3, [ETHERSWITCH_PORT_LED_ON] = 0x2, [ETHERSWITCH_PORT_LED_OFF] = 0x0, [ETHERSWITCH_PORT_LED_BLINK] = 0x1 }; static inline int arswitch_portforphy(int phy); static void arswitch_tick(void *arg); static int arswitch_ifmedia_upd(struct ifnet *); static void arswitch_ifmedia_sts(struct ifnet *, struct ifmediareq *); static int ar8xxx_port_vlan_setup(struct arswitch_softc *sc, etherswitch_port_t *p); static int ar8xxx_port_vlan_get(struct arswitch_softc *sc, etherswitch_port_t *p); static int arswitch_setled(struct arswitch_softc *sc, int phy, int led, int style); static int arswitch_probe(device_t dev) { struct arswitch_softc *sc; uint32_t id; char *chipname, desc[256]; sc = device_get_softc(dev); bzero(sc, sizeof(*sc)); sc->page = -1; /* AR7240 probe */ if (ar7240_probe(dev) == 0) { chipname = "AR7240"; sc->sc_switchtype = AR8X16_SWITCH_AR7240; sc->is_internal_switch = 1; id = 0; goto done; } /* AR9340 probe */ if (ar9340_probe(dev) == 0) { chipname = "AR9340"; sc->sc_switchtype = AR8X16_SWITCH_AR9340; sc->is_internal_switch = 1; id = 0; goto done; } /* AR8xxx probe */ id = arswitch_readreg(dev, AR8X16_REG_MASK_CTRL); sc->chip_rev = (id & AR8X16_MASK_CTRL_REV_MASK); sc->chip_ver = (id & AR8X16_MASK_CTRL_VER_MASK) > AR8X16_MASK_CTRL_VER_SHIFT; switch (id & (AR8X16_MASK_CTRL_VER_MASK | AR8X16_MASK_CTRL_REV_MASK)) { case 0x0101: chipname = "AR8216"; sc->sc_switchtype = AR8X16_SWITCH_AR8216; break; case 0x0201: chipname = "AR8226"; sc->sc_switchtype = AR8X16_SWITCH_AR8226; break; /* 0x0301 - AR8236 */ case 0x1000: case 0x1001: chipname = "AR8316"; sc->sc_switchtype = AR8X16_SWITCH_AR8316; break; case 0x1202: case 0x1204: chipname = "AR8327"; sc->sc_switchtype = AR8X16_SWITCH_AR8327; sc->mii_lo_first = 1; break; default: chipname = NULL; } done: - DPRINTF(dev, "chipname=%s, id=%08x\n", chipname, id); + DPRINTF(sc, ARSWITCH_DBG_ANY, "chipname=%s, id=%08x\n", chipname, id); if (chipname != NULL) { snprintf(desc, sizeof(desc), "Atheros %s Ethernet Switch (ver %d rev %d)", chipname, sc->chip_ver, sc->chip_rev); device_set_desc_copy(dev, desc); return (BUS_PROBE_DEFAULT); } return (ENXIO); } static int arswitch_attach_phys(struct arswitch_softc *sc) { int phy, err = 0; char name[IFNAMSIZ]; /* PHYs need an interface, so we generate a dummy one */ snprintf(name, IFNAMSIZ, "%sport", device_get_nameunit(sc->sc_dev)); for (phy = 0; phy < sc->numphys; phy++) { sc->ifp[phy] = if_alloc(IFT_ETHER); sc->ifp[phy]->if_softc = sc; sc->ifp[phy]->if_flags |= IFF_UP | IFF_BROADCAST | IFF_DRV_RUNNING | IFF_SIMPLEX; sc->ifname[phy] = malloc(strlen(name)+1, M_DEVBUF, M_WAITOK); bcopy(name, sc->ifname[phy], strlen(name)+1); if_initname(sc->ifp[phy], sc->ifname[phy], arswitch_portforphy(phy)); err = mii_attach(sc->sc_dev, &sc->miibus[phy], sc->ifp[phy], arswitch_ifmedia_upd, arswitch_ifmedia_sts, \ BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); #if 0 DPRINTF(sc->sc_dev, "%s attached to pseudo interface %s\n", device_get_nameunit(sc->miibus[phy]), sc->ifp[phy]->if_xname); #endif if (err != 0) { device_printf(sc->sc_dev, "attaching PHY %d failed\n", phy); return (err); } if (AR8X16_IS_SWITCH(sc, AR8327)) { int led; char ledname[IFNAMSIZ+4]; for (led = 0; led < 3; led++) { sprintf(ledname, "%s%dled%d", name, arswitch_portforphy(phy), led+1); sc->dev_led[phy][led].sc = sc; sc->dev_led[phy][led].phy = phy; sc->dev_led[phy][led].lednum = led; } } } return (0); } static int arswitch_reset(device_t dev) { arswitch_writereg(dev, AR8X16_REG_MASK_CTRL, AR8X16_MASK_CTRL_SOFT_RESET); DELAY(1000); if (arswitch_readreg(dev, AR8X16_REG_MASK_CTRL) & AR8X16_MASK_CTRL_SOFT_RESET) { device_printf(dev, "unable to reset switch\n"); return (-1); } return (0); } static int arswitch_set_vlan_mode(struct arswitch_softc *sc, uint32_t mode) { /* Check for invalid modes. */ if ((mode & sc->info.es_vlan_caps) != mode) return (EINVAL); switch (mode) { case ETHERSWITCH_VLAN_DOT1Q: sc->vlan_mode = ETHERSWITCH_VLAN_DOT1Q; break; case ETHERSWITCH_VLAN_PORT: sc->vlan_mode = ETHERSWITCH_VLAN_PORT; break; default: sc->vlan_mode = 0; } /* Reset VLANs. */ sc->hal.arswitch_vlan_init_hw(sc); return (0); } static void ar8xxx_port_init(struct arswitch_softc *sc, int port) { /* Port0 - CPU */ if (port == AR8X16_PORT_CPU) { arswitch_writereg(sc->sc_dev, AR8X16_REG_PORT_STS(0), (AR8X16_IS_SWITCH(sc, AR8216) ? AR8X16_PORT_STS_SPEED_100 : AR8X16_PORT_STS_SPEED_1000) | (AR8X16_IS_SWITCH(sc, AR8216) ? 0 : AR8X16_PORT_STS_RXFLOW) | (AR8X16_IS_SWITCH(sc, AR8216) ? 0 : AR8X16_PORT_STS_TXFLOW) | AR8X16_PORT_STS_RXMAC | AR8X16_PORT_STS_TXMAC | AR8X16_PORT_STS_DUPLEX); arswitch_writereg(sc->sc_dev, AR8X16_REG_PORT_CTRL(0), arswitch_readreg(sc->sc_dev, AR8X16_REG_PORT_CTRL(0)) & ~AR8X16_PORT_CTRL_HEADER); } else { /* Set ports to auto negotiation. */ arswitch_writereg(sc->sc_dev, AR8X16_REG_PORT_STS(port), AR8X16_PORT_STS_LINK_AUTO); arswitch_writereg(sc->sc_dev, AR8X16_REG_PORT_CTRL(port), arswitch_readreg(sc->sc_dev, AR8X16_REG_PORT_CTRL(port)) & ~AR8X16_PORT_CTRL_HEADER); } } static int ar8xxx_atu_flush(struct arswitch_softc *sc) { int ret; ret = arswitch_waitreg(sc->sc_dev, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0, 1000); if (ret) device_printf(sc->sc_dev, "%s: waitreg failed\n", __func__); if (!ret) arswitch_writereg(sc->sc_dev, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH); return (ret); } static int arswitch_attach(device_t dev) { - struct arswitch_softc *sc; + struct arswitch_softc *sc = device_get_softc(dev); + struct sysctl_ctx_list *ctx; + struct sysctl_oid *tree; int err = 0; int port; - sc = device_get_softc(dev); - /* sc->sc_switchtype is already decided in arswitch_probe() */ sc->sc_dev = dev; mtx_init(&sc->sc_mtx, "arswitch", NULL, MTX_DEF); sc->page = -1; strlcpy(sc->info.es_name, device_get_desc(dev), sizeof(sc->info.es_name)); + /* Debugging */ + ctx = device_get_sysctl_ctx(sc->sc_dev); + tree = device_get_sysctl_tree(sc->sc_dev); + SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, + "debug", CTLFLAG_RW, &sc->sc_debug, 0, + "control debugging printfs"); + /* Default HAL methods */ sc->hal.arswitch_port_init = ar8xxx_port_init; sc->hal.arswitch_port_vlan_setup = ar8xxx_port_vlan_setup; sc->hal.arswitch_port_vlan_get = ar8xxx_port_vlan_get; sc->hal.arswitch_vlan_init_hw = ar8xxx_reset_vlans; sc->hal.arswitch_vlan_getvgroup = ar8xxx_getvgroup; sc->hal.arswitch_vlan_setvgroup = ar8xxx_setvgroup; sc->hal.arswitch_vlan_get_pvid = ar8xxx_get_pvid; sc->hal.arswitch_vlan_set_pvid = ar8xxx_set_pvid; sc->hal.arswitch_get_dot1q_vlan = ar8xxx_get_dot1q_vlan; sc->hal.arswitch_set_dot1q_vlan = ar8xxx_set_dot1q_vlan; sc->hal.arswitch_flush_dot1q_vlan = ar8xxx_flush_dot1q_vlan; sc->hal.arswitch_purge_dot1q_vlan = ar8xxx_purge_dot1q_vlan; sc->hal.arswitch_get_port_vlan = ar8xxx_get_port_vlan; sc->hal.arswitch_set_port_vlan = ar8xxx_set_port_vlan; sc->hal.arswitch_atu_flush = ar8xxx_atu_flush; sc->hal.arswitch_phy_read = arswitch_readphy_internal; sc->hal.arswitch_phy_write = arswitch_writephy_internal; /* * Attach switch related functions */ if (AR8X16_IS_SWITCH(sc, AR7240)) ar7240_attach(sc); else if (AR8X16_IS_SWITCH(sc, AR9340)) ar9340_attach(sc); else if (AR8X16_IS_SWITCH(sc, AR8216)) ar8216_attach(sc); else if (AR8X16_IS_SWITCH(sc, AR8226)) ar8226_attach(sc); else if (AR8X16_IS_SWITCH(sc, AR8316)) ar8316_attach(sc); else if (AR8X16_IS_SWITCH(sc, AR8327)) ar8327_attach(sc); else { - DPRINTF(dev, "%s: unknown switch (%d)?\n", __func__, sc->sc_switchtype); + DPRINTF(sc, ARSWITCH_DBG_ANY, + "%s: unknown switch (%d)?\n", __func__, sc->sc_switchtype); return (ENXIO); } /* Common defaults. */ sc->info.es_nports = 5; /* XXX technically 6, but 6th not used */ /* XXX Defaults for externally connected AR8316 */ sc->numphys = 4; sc->phy4cpu = 1; sc->is_rgmii = 1; sc->is_gmii = 0; sc->is_mii = 0; (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "numphys", &sc->numphys); (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "phy4cpu", &sc->phy4cpu); (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "is_rgmii", &sc->is_rgmii); (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "is_gmii", &sc->is_gmii); (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "is_mii", &sc->is_mii); if (sc->numphys > AR8X16_NUM_PHYS) sc->numphys = AR8X16_NUM_PHYS; /* Reset the switch. */ if (arswitch_reset(dev)) { - DPRINTF(dev, "%s: arswitch_reset: failed\n", __func__); + DPRINTF(sc, ARSWITCH_DBG_ANY, + "%s: arswitch_reset: failed\n", __func__); return (ENXIO); } err = sc->hal.arswitch_hw_setup(sc); - DPRINTF(dev, "%s: hw_setup: err=%d\n", __func__, err); - if (err != 0) + if (err != 0) { + DPRINTF(sc, ARSWITCH_DBG_ANY, + "%s: hw_setup: err=%d\n", __func__, err); return (err); + } err = sc->hal.arswitch_hw_global_setup(sc); - DPRINTF(dev, "%s: hw_global_setup: err=%d\n", __func__, err); - if (err != 0) + if (err != 0) { + DPRINTF(sc, ARSWITCH_DBG_ANY, + "%s: hw_global_setup: err=%d\n", __func__, err); return (err); + } /* Initialize the switch ports. */ for (port = 0; port <= sc->numphys; port++) { sc->hal.arswitch_port_init(sc, port); } /* * Attach the PHYs and complete the bus enumeration. */ err = arswitch_attach_phys(sc); - DPRINTF(dev, "%s: attach_phys: err=%d\n", __func__, err); - if (err != 0) + if (err != 0) { + DPRINTF(sc, ARSWITCH_DBG_ANY, + "%s: attach_phys: err=%d\n", __func__, err); return (err); + } /* Default to ingress filters off. */ err = arswitch_set_vlan_mode(sc, 0); - DPRINTF(dev, "%s: set_vlan_mode: err=%d\n", __func__, err); - if (err != 0) + if (err != 0) { + DPRINTF(sc, ARSWITCH_DBG_ANY, + "%s: set_vlan_mode: err=%d\n", __func__, err); return (err); + } bus_generic_probe(dev); bus_enumerate_hinted_children(dev); err = bus_generic_attach(dev); - DPRINTF(dev, "%s: bus_generic_attach: err=%d\n", __func__, err); - if (err != 0) + if (err != 0) { + DPRINTF(sc, ARSWITCH_DBG_ANY, + "%s: bus_generic_attach: err=%d\n", __func__, err); return (err); + } callout_init_mtx(&sc->callout_tick, &sc->sc_mtx, 0); ARSWITCH_LOCK(sc); arswitch_tick(sc); ARSWITCH_UNLOCK(sc); return (err); } static int arswitch_detach(device_t dev) { struct arswitch_softc *sc = device_get_softc(dev); int i; callout_drain(&sc->callout_tick); for (i=0; i < sc->numphys; i++) { if (sc->miibus[i] != NULL) device_delete_child(dev, sc->miibus[i]); if (sc->ifp[i] != NULL) if_free(sc->ifp[i]); free(sc->ifname[i], M_DEVBUF); } bus_generic_detach(dev); mtx_destroy(&sc->sc_mtx); return (0); } /* * Convert PHY number to port number. PHY0 is connected to port 1, PHY1 to * port 2, etc. */ static inline int arswitch_portforphy(int phy) { return (phy+1); } static inline struct mii_data * arswitch_miiforport(struct arswitch_softc *sc, int port) { int phy = port-1; if (phy < 0 || phy >= sc->numphys) return (NULL); return (device_get_softc(sc->miibus[phy])); } static inline struct ifnet * arswitch_ifpforport(struct arswitch_softc *sc, int port) { int phy = port-1; if (phy < 0 || phy >= sc->numphys) return (NULL); return (sc->ifp[phy]); } /* * Convert port status to ifmedia. */ static void arswitch_update_ifmedia(int portstatus, u_int *media_status, u_int *media_active) { *media_active = IFM_ETHER; *media_status = IFM_AVALID; if ((portstatus & AR8X16_PORT_STS_LINK_UP) != 0) *media_status |= IFM_ACTIVE; else { *media_active |= IFM_NONE; return; } switch (portstatus & AR8X16_PORT_STS_SPEED_MASK) { case AR8X16_PORT_STS_SPEED_10: *media_active |= IFM_10_T; break; case AR8X16_PORT_STS_SPEED_100: *media_active |= IFM_100_TX; break; case AR8X16_PORT_STS_SPEED_1000: *media_active |= IFM_1000_T; break; } if ((portstatus & AR8X16_PORT_STS_DUPLEX) == 0) *media_active |= IFM_FDX; else *media_active |= IFM_HDX; if ((portstatus & AR8X16_PORT_STS_TXFLOW) != 0) *media_active |= IFM_ETH_TXPAUSE; if ((portstatus & AR8X16_PORT_STS_RXFLOW) != 0) *media_active |= IFM_ETH_RXPAUSE; } /* * Poll the status for all PHYs. We're using the switch port status because * thats a lot quicker to read than talking to all the PHYs. Care must be * taken that the resulting ifmedia_active is identical to what the PHY will * compute, or gratuitous link status changes will occur whenever the PHYs * update function is called. */ static void arswitch_miipollstat(struct arswitch_softc *sc) { int i; struct mii_data *mii; struct mii_softc *miisc; int portstatus; int port_flap = 0; ARSWITCH_LOCK_ASSERT(sc, MA_OWNED); for (i = 0; i < sc->numphys; i++) { if (sc->miibus[i] == NULL) continue; mii = device_get_softc(sc->miibus[i]); /* XXX This would be nice to have abstracted out to be per-chip */ /* AR8327/AR8337 has a different register base */ if (AR8X16_IS_SWITCH(sc, AR8327)) portstatus = arswitch_readreg(sc->sc_dev, AR8327_REG_PORT_STATUS(arswitch_portforphy(i))); else portstatus = arswitch_readreg(sc->sc_dev, AR8X16_REG_PORT_STS(arswitch_portforphy(i))); -#if 0 - DPRINTF(sc->sc_dev, "p[%d]=%b\n", +#if 1 + DPRINTF(sc, ARSWITCH_DBG_POLL, "p[%d]=0x%08x (%b)\n", i, portstatus, + portstatus, "\20\3TXMAC\4RXMAC\5TXFLOW\6RXFLOW\7" "DUPLEX\11LINK_UP\12LINK_AUTO\13LINK_PAUSE"); #endif /* * If the current status is down, but we have a link * status showing up, we need to do an ATU flush. */ if ((mii->mii_media_status & IFM_ACTIVE) == 0 && (portstatus & AR8X16_PORT_STS_LINK_UP) != 0) { device_printf(sc->sc_dev, "%s: port %d: port -> UP\n", __func__, i); port_flap = 1; } /* * and maybe if a port goes up->down? */ if ((mii->mii_media_status & IFM_ACTIVE) != 0 && (portstatus & AR8X16_PORT_STS_LINK_UP) == 0) { device_printf(sc->sc_dev, "%s: port %d: port -> DOWN\n", __func__, i); port_flap = 1; } arswitch_update_ifmedia(portstatus, &mii->mii_media_status, &mii->mii_media_active); LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { if (IFM_INST(mii->mii_media.ifm_cur->ifm_media) != miisc->mii_inst) continue; mii_phy_update(miisc, MII_POLLSTAT); } } /* If a port went from down->up, flush the ATU */ if (port_flap) sc->hal.arswitch_atu_flush(sc); } static void arswitch_tick(void *arg) { struct arswitch_softc *sc = arg; arswitch_miipollstat(sc); callout_reset(&sc->callout_tick, hz, arswitch_tick, sc); } static void arswitch_lock(device_t dev) { struct arswitch_softc *sc = device_get_softc(dev); ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED); ARSWITCH_LOCK(sc); } static void arswitch_unlock(device_t dev) { struct arswitch_softc *sc = device_get_softc(dev); ARSWITCH_LOCK_ASSERT(sc, MA_OWNED); ARSWITCH_UNLOCK(sc); } static etherswitch_info_t * arswitch_getinfo(device_t dev) { struct arswitch_softc *sc = device_get_softc(dev); return (&sc->info); } static int ar8xxx_port_vlan_get(struct arswitch_softc *sc, etherswitch_port_t *p) { uint32_t reg; ARSWITCH_LOCK(sc); /* Retrieve the PVID. */ sc->hal.arswitch_vlan_get_pvid(sc, p->es_port, &p->es_pvid); /* Port flags. */ reg = arswitch_readreg(sc->sc_dev, AR8X16_REG_PORT_CTRL(p->es_port)); if (reg & AR8X16_PORT_CTRL_DOUBLE_TAG) p->es_flags |= ETHERSWITCH_PORT_DOUBLE_TAG; reg >>= AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_SHIFT; if ((reg & 0x3) == AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_ADD) p->es_flags |= ETHERSWITCH_PORT_ADDTAG; if ((reg & 0x3) == AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_STRIP) p->es_flags |= ETHERSWITCH_PORT_STRIPTAG; ARSWITCH_UNLOCK(sc); return (0); } static int arswitch_is_cpuport(struct arswitch_softc *sc, int port) { return ((port == AR8X16_PORT_CPU) || ((AR8X16_IS_SWITCH(sc, AR8327) && port == AR8327_PORT_GMAC6))); } static int arswitch_getport(device_t dev, etherswitch_port_t *p) { struct arswitch_softc *sc; struct mii_data *mii; struct ifmediareq *ifmr; int err; sc = device_get_softc(dev); /* XXX +1 is for AR8327; should make this configurable! */ if (p->es_port < 0 || p->es_port > sc->info.es_nports) return (ENXIO); err = sc->hal.arswitch_port_vlan_get(sc, p); if (err != 0) return (err); mii = arswitch_miiforport(sc, p->es_port); if (arswitch_is_cpuport(sc, p->es_port)) { /* fill in fixed values for CPU port */ /* XXX is this valid in all cases? */ p->es_flags |= ETHERSWITCH_PORT_CPU; ifmr = &p->es_ifmr; ifmr->ifm_count = 0; ifmr->ifm_current = ifmr->ifm_active = IFM_ETHER | IFM_1000_T | IFM_FDX; ifmr->ifm_mask = 0; ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID; } else if (mii != NULL) { err = ifmedia_ioctl(mii->mii_ifp, &p->es_ifr, &mii->mii_media, SIOCGIFMEDIA); if (err) return (err); } else { return (ENXIO); } if (!arswitch_is_cpuport(sc, p->es_port) && AR8X16_IS_SWITCH(sc, AR8327)) { int led; p->es_nleds = 3; for (led = 0; led < p->es_nleds; led++) { int style; uint32_t val; /* Find the right style enum for our pattern */ val = arswitch_readreg(dev, ar8327_led_mapping[p->es_port-1][led].reg); val = (val>>ar8327_led_mapping[p->es_port-1][led].shift)&0x03; for (style = 0; style < ETHERSWITCH_PORT_LED_MAX; style++) { if (led_pattern_table[style] == val) break; } /* can't happen */ if (style == ETHERSWITCH_PORT_LED_MAX) style = ETHERSWITCH_PORT_LED_DEFAULT; p->es_led[led] = style; } } else { p->es_nleds = 0; } return (0); } static int ar8xxx_port_vlan_setup(struct arswitch_softc *sc, etherswitch_port_t *p) { uint32_t reg; int err; ARSWITCH_LOCK(sc); /* Set the PVID. */ if (p->es_pvid != 0) sc->hal.arswitch_vlan_set_pvid(sc, p->es_port, p->es_pvid); /* Mutually exclusive. */ if (p->es_flags & ETHERSWITCH_PORT_ADDTAG && p->es_flags & ETHERSWITCH_PORT_STRIPTAG) { ARSWITCH_UNLOCK(sc); return (EINVAL); } reg = 0; if (p->es_flags & ETHERSWITCH_PORT_DOUBLE_TAG) reg |= AR8X16_PORT_CTRL_DOUBLE_TAG; if (p->es_flags & ETHERSWITCH_PORT_ADDTAG) reg |= AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_ADD << AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_SHIFT; if (p->es_flags & ETHERSWITCH_PORT_STRIPTAG) reg |= AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_STRIP << AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_SHIFT; err = arswitch_modifyreg(sc->sc_dev, AR8X16_REG_PORT_CTRL(p->es_port), 0x3 << AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_SHIFT | AR8X16_PORT_CTRL_DOUBLE_TAG, reg); ARSWITCH_UNLOCK(sc); return (err); } static int arswitch_setport(device_t dev, etherswitch_port_t *p) { int err, i; struct arswitch_softc *sc; struct ifmedia *ifm; struct mii_data *mii; struct ifnet *ifp; sc = device_get_softc(dev); if (p->es_port < 0 || p->es_port > sc->info.es_nports) return (ENXIO); /* Port flags. */ if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { err = sc->hal.arswitch_port_vlan_setup(sc, p); if (err) return (err); } /* Do not allow media or led changes on CPU port. */ if (arswitch_is_cpuport(sc, p->es_port)) return (0); if (AR8X16_IS_SWITCH(sc, AR8327)) { for (i = 0; i < 3; i++) { int err; err = arswitch_setled(sc, p->es_port-1, i, p->es_led[i]); if (err) return (err); } } mii = arswitch_miiforport(sc, p->es_port); if (mii == NULL) return (ENXIO); ifp = arswitch_ifpforport(sc, p->es_port); ifm = &mii->mii_media; return (ifmedia_ioctl(ifp, &p->es_ifr, ifm, SIOCSIFMEDIA)); } static int arswitch_setled(struct arswitch_softc *sc, int phy, int led, int style) { int shift; if (phy < 0 || phy > sc->numphys) return EINVAL; if (style < 0 || style > ETHERSWITCH_PORT_LED_MAX) return (EINVAL); shift = ar8327_led_mapping[phy][led].shift; return (arswitch_modifyreg(sc->sc_dev, ar8327_led_mapping[phy][led].reg, 0x03 << shift, led_pattern_table[style] << shift)); } static void arswitch_statchg(device_t dev) { + struct arswitch_softc *sc = device_get_softc(dev); - DPRINTF(dev, "%s\n", __func__); + DPRINTF(sc, ARSWITCH_DBG_POLL, "%s\n", __func__); } static int arswitch_ifmedia_upd(struct ifnet *ifp) { struct arswitch_softc *sc = ifp->if_softc; struct mii_data *mii = arswitch_miiforport(sc, ifp->if_dunit); if (mii == NULL) return (ENXIO); mii_mediachg(mii); return (0); } static void arswitch_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) { struct arswitch_softc *sc = ifp->if_softc; struct mii_data *mii = arswitch_miiforport(sc, ifp->if_dunit); - DPRINTF(sc->sc_dev, "%s\n", __func__); + DPRINTF(sc, ARSWITCH_DBG_POLL, "%s\n", __func__); if (mii == NULL) return; mii_pollstat(mii); ifmr->ifm_active = mii->mii_media_active; ifmr->ifm_status = mii->mii_media_status; } static int arswitch_getconf(device_t dev, etherswitch_conf_t *conf) { struct arswitch_softc *sc; sc = device_get_softc(dev); /* Return the VLAN mode. */ conf->cmd = ETHERSWITCH_CONF_VLAN_MODE; conf->vlan_mode = sc->vlan_mode; return (0); } static int arswitch_setconf(device_t dev, etherswitch_conf_t *conf) { struct arswitch_softc *sc; int err; sc = device_get_softc(dev); /* Set the VLAN mode. */ if (conf->cmd & ETHERSWITCH_CONF_VLAN_MODE) { err = arswitch_set_vlan_mode(sc, conf->vlan_mode); if (err != 0) return (err); } return (0); } static int arswitch_getvgroup(device_t dev, etherswitch_vlangroup_t *e) { struct arswitch_softc *sc = device_get_softc(dev); return (sc->hal.arswitch_vlan_getvgroup(sc, e)); } static int arswitch_setvgroup(device_t dev, etherswitch_vlangroup_t *e) { struct arswitch_softc *sc = device_get_softc(dev); return (sc->hal.arswitch_vlan_setvgroup(sc, e)); } static int arswitch_readphy(device_t dev, int phy, int reg) { struct arswitch_softc *sc = device_get_softc(dev); return (sc->hal.arswitch_phy_read(dev, phy, reg)); } static int arswitch_writephy(device_t dev, int phy, int reg, int val) { struct arswitch_softc *sc = device_get_softc(dev); return (sc->hal.arswitch_phy_write(dev, phy, reg, val)); } static device_method_t arswitch_methods[] = { /* Device interface */ DEVMETHOD(device_probe, arswitch_probe), DEVMETHOD(device_attach, arswitch_attach), DEVMETHOD(device_detach, arswitch_detach), /* bus interface */ DEVMETHOD(bus_add_child, device_add_child_ordered), /* MII interface */ DEVMETHOD(miibus_readreg, arswitch_readphy), DEVMETHOD(miibus_writereg, arswitch_writephy), DEVMETHOD(miibus_statchg, arswitch_statchg), /* MDIO interface */ DEVMETHOD(mdio_readreg, arswitch_readphy), DEVMETHOD(mdio_writereg, arswitch_writephy), /* etherswitch interface */ DEVMETHOD(etherswitch_lock, arswitch_lock), DEVMETHOD(etherswitch_unlock, arswitch_unlock), DEVMETHOD(etherswitch_getinfo, arswitch_getinfo), DEVMETHOD(etherswitch_readreg, arswitch_readreg), DEVMETHOD(etherswitch_writereg, arswitch_writereg), DEVMETHOD(etherswitch_readphyreg, arswitch_readphy), DEVMETHOD(etherswitch_writephyreg, arswitch_writephy), DEVMETHOD(etherswitch_getport, arswitch_getport), DEVMETHOD(etherswitch_setport, arswitch_setport), DEVMETHOD(etherswitch_getvgroup, arswitch_getvgroup), DEVMETHOD(etherswitch_setvgroup, arswitch_setvgroup), DEVMETHOD(etherswitch_getconf, arswitch_getconf), DEVMETHOD(etherswitch_setconf, arswitch_setconf), DEVMETHOD_END }; DEFINE_CLASS_0(arswitch, arswitch_driver, arswitch_methods, sizeof(struct arswitch_softc)); static devclass_t arswitch_devclass; DRIVER_MODULE(arswitch, mdio, arswitch_driver, arswitch_devclass, 0, 0); DRIVER_MODULE(miibus, arswitch, miibus_driver, miibus_devclass, 0, 0); DRIVER_MODULE(mdio, arswitch, mdio_driver, mdio_devclass, 0, 0); DRIVER_MODULE(etherswitch, arswitch, etherswitch_driver, etherswitch_devclass, 0, 0); MODULE_VERSION(arswitch, 1); MODULE_DEPEND(arswitch, miibus, 1, 1, 1); /* XXX which versions? */ MODULE_DEPEND(arswitch, etherswitch, 1, 1, 1); /* XXX which versions? */ Index: head/sys/dev/etherswitch/arswitch/arswitch_8327.c =================================================================== --- head/sys/dev/etherswitch/arswitch/arswitch_8327.c (revision 303809) +++ head/sys/dev/etherswitch/arswitch/arswitch_8327.c (revision 303810) @@ -1,1190 +1,1190 @@ /*- * Copyright (c) 2011-2012 Stefan Bethke. * Copyright (c) 2014 Adrian Chadd. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "mdio_if.h" #include "miibus_if.h" #include "etherswitch_if.h" /* * AR8327 TODO: * * There should be a default hardware setup hint set for the default * switch config. Otherwise the default is "all ports in one vlangroup", * which means both CPU ports can see each other and that will quickly * lead to traffic storms/loops. */ /* Map port+led to register+shift */ struct ar8327_led_mapping ar8327_led_mapping[AR8327_NUM_PHYS][ETHERSWITCH_PORT_MAX_LEDS] = { { /* PHY0 */ {AR8327_REG_LED_CTRL0, 14 }, {AR8327_REG_LED_CTRL1, 14 }, {AR8327_REG_LED_CTRL2, 14 } }, { /* PHY1 */ {AR8327_REG_LED_CTRL3, 8 }, {AR8327_REG_LED_CTRL3, 10 }, {AR8327_REG_LED_CTRL3, 12 } }, { /* PHY2 */ {AR8327_REG_LED_CTRL3, 14 }, {AR8327_REG_LED_CTRL3, 16 }, {AR8327_REG_LED_CTRL3, 18 } }, { /* PHY3 */ {AR8327_REG_LED_CTRL3, 20 }, {AR8327_REG_LED_CTRL3, 22 }, {AR8327_REG_LED_CTRL3, 24 } }, { /* PHY4 */ {AR8327_REG_LED_CTRL0, 30 }, {AR8327_REG_LED_CTRL1, 30 }, {AR8327_REG_LED_CTRL2, 30 } } }; static int ar8327_vlan_op(struct arswitch_softc *sc, uint32_t op, uint32_t vid, uint32_t data) { int err; /* * Wait for the "done" bit to finish. */ if (arswitch_waitreg(sc->sc_dev, AR8327_REG_VTU_FUNC1, AR8327_VTU_FUNC1_BUSY, 0, 5)) return (EBUSY); /* * If it's a "load" operation, then ensure 'data' is loaded * in first. */ if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD) { err = arswitch_writereg(sc->sc_dev, AR8327_REG_VTU_FUNC0, data); if (err) return (err); } /* * Set the VID. */ op |= ((vid & 0xfff) << AR8327_VTU_FUNC1_VID_S); /* * Set busy bit to start loading in the command. */ op |= AR8327_VTU_FUNC1_BUSY; arswitch_writereg(sc->sc_dev, AR8327_REG_VTU_FUNC1, op); /* * Finally - wait for it to load. */ if (arswitch_waitreg(sc->sc_dev, AR8327_REG_VTU_FUNC1, AR8327_VTU_FUNC1_BUSY, 0, 5)) return (EBUSY); return (0); } static void ar8327_phy_fixup(struct arswitch_softc *sc, int phy) { if (bootverbose) device_printf(sc->sc_dev, "%s: called; phy=%d; chiprev=%d\n", __func__, phy, sc->chip_rev); switch (sc->chip_rev) { case 1: /* For 100M waveform */ arswitch_writedbg(sc->sc_dev, phy, 0, 0x02ea); /* Turn on Gigabit clock */ arswitch_writedbg(sc->sc_dev, phy, 0x3d, 0x68a0); break; case 2: arswitch_writemmd(sc->sc_dev, phy, 0x7, 0x3c); arswitch_writemmd(sc->sc_dev, phy, 0x4007, 0x0); /* fallthrough */ case 4: arswitch_writemmd(sc->sc_dev, phy, 0x3, 0x800d); arswitch_writemmd(sc->sc_dev, phy, 0x4003, 0x803f); arswitch_writedbg(sc->sc_dev, phy, 0x3d, 0x6860); arswitch_writedbg(sc->sc_dev, phy, 0x5, 0x2c46); arswitch_writedbg(sc->sc_dev, phy, 0x3c, 0x6000); break; } } static uint32_t ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg) { uint32_t t; if (!cfg) return (0); t = 0; switch (cfg->mode) { case AR8327_PAD_NC: break; case AR8327_PAD_MAC2MAC_MII: t = AR8327_PAD_MAC_MII_EN; if (cfg->rxclk_sel) t |= AR8327_PAD_MAC_MII_RXCLK_SEL; if (cfg->txclk_sel) t |= AR8327_PAD_MAC_MII_TXCLK_SEL; break; case AR8327_PAD_MAC2MAC_GMII: t = AR8327_PAD_MAC_GMII_EN; if (cfg->rxclk_sel) t |= AR8327_PAD_MAC_GMII_RXCLK_SEL; if (cfg->txclk_sel) t |= AR8327_PAD_MAC_GMII_TXCLK_SEL; break; case AR8327_PAD_MAC_SGMII: t = AR8327_PAD_SGMII_EN; /* * WAR for the Qualcomm Atheros AP136 board. * It seems that RGMII TX/RX delay settings needs to be * applied for SGMII mode as well, The ethernet is not * reliable without this. */ t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S; t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S; if (cfg->rxclk_delay_en) t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN; if (cfg->txclk_delay_en) t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN; if (cfg->sgmii_delay_en) t |= AR8327_PAD_SGMII_DELAY_EN; break; case AR8327_PAD_MAC2PHY_MII: t = AR8327_PAD_PHY_MII_EN; if (cfg->rxclk_sel) t |= AR8327_PAD_PHY_MII_RXCLK_SEL; if (cfg->txclk_sel) t |= AR8327_PAD_PHY_MII_TXCLK_SEL; break; case AR8327_PAD_MAC2PHY_GMII: t = AR8327_PAD_PHY_GMII_EN; if (cfg->pipe_rxclk_sel) t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL; if (cfg->rxclk_sel) t |= AR8327_PAD_PHY_GMII_RXCLK_SEL; if (cfg->txclk_sel) t |= AR8327_PAD_PHY_GMII_TXCLK_SEL; break; case AR8327_PAD_MAC_RGMII: t = AR8327_PAD_RGMII_EN; t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S; t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S; if (cfg->rxclk_delay_en) t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN; if (cfg->txclk_delay_en) t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN; break; case AR8327_PAD_PHY_GMII: t = AR8327_PAD_PHYX_GMII_EN; break; case AR8327_PAD_PHY_RGMII: t = AR8327_PAD_PHYX_RGMII_EN; break; case AR8327_PAD_PHY_MII: t = AR8327_PAD_PHYX_MII_EN; break; } return (t); } /* * Map the hard-coded port config from the switch setup to * the chipset port config (status, duplex, flow, etc.) */ static uint32_t ar8327_get_port_init_status(struct ar8327_port_cfg *cfg) { uint32_t t; if (!cfg->force_link) return (AR8X16_PORT_STS_LINK_AUTO); t = AR8X16_PORT_STS_TXMAC | AR8X16_PORT_STS_RXMAC; t |= cfg->duplex ? AR8X16_PORT_STS_DUPLEX : 0; t |= cfg->rxpause ? AR8X16_PORT_STS_RXFLOW : 0; t |= cfg->txpause ? AR8X16_PORT_STS_TXFLOW : 0; switch (cfg->speed) { case AR8327_PORT_SPEED_10: t |= AR8X16_PORT_STS_SPEED_10; break; case AR8327_PORT_SPEED_100: t |= AR8X16_PORT_STS_SPEED_100; break; case AR8327_PORT_SPEED_1000: t |= AR8X16_PORT_STS_SPEED_1000; break; } return (t); } /* * Fetch the port data for the given port. * * This goes and does dirty things with the hints space * to determine what the configuration parameters should be. * * Returns 1 if the structure was successfully parsed and * the contents are valid; 0 otherwise. */ static int ar8327_fetch_pdata_port(struct arswitch_softc *sc, struct ar8327_port_cfg *pcfg, int port) { int val; char sbuf[128]; /* Check if force_link exists */ val = 0; snprintf(sbuf, 128, "port.%d.force_link", port); (void) resource_int_value(device_get_name(sc->sc_dev), device_get_unit(sc->sc_dev), sbuf, &val); if (val != 1) return (0); pcfg->force_link = 1; /* force_link is set; let's parse the rest of the fields */ snprintf(sbuf, 128, "port.%d.speed", port); if (resource_int_value(device_get_name(sc->sc_dev), device_get_unit(sc->sc_dev), sbuf, &val) == 0) { switch (val) { case 10: pcfg->speed = AR8327_PORT_SPEED_10; break; case 100: pcfg->speed = AR8327_PORT_SPEED_100; break; case 1000: pcfg->speed = AR8327_PORT_SPEED_1000; break; default: device_printf(sc->sc_dev, "%s: invalid port %d duplex value (%d)\n", __func__, port, val); return (0); } } snprintf(sbuf, 128, "port.%d.duplex", port); if (resource_int_value(device_get_name(sc->sc_dev), device_get_unit(sc->sc_dev), sbuf, &val) == 0) pcfg->duplex = val; snprintf(sbuf, 128, "port.%d.txpause", port); if (resource_int_value(device_get_name(sc->sc_dev), device_get_unit(sc->sc_dev), sbuf, &val) == 0) pcfg->txpause = val; snprintf(sbuf, 128, "port.%d.rxpause", port); if (resource_int_value(device_get_name(sc->sc_dev), device_get_unit(sc->sc_dev), sbuf, &val) == 0) pcfg->rxpause = val; #if 1 device_printf(sc->sc_dev, "%s: port %d: speed=%d, duplex=%d, txpause=%d, rxpause=%d\n", __func__, port, pcfg->speed, pcfg->duplex, pcfg->txpause, pcfg->rxpause); #endif return (1); } /* * Parse the pad configuration from the boot hints. * * The (mostly optional) fields are: * * uint32_t mode; * uint32_t rxclk_sel; * uint32_t txclk_sel; * uint32_t txclk_delay_sel; * uint32_t rxclk_delay_sel; * uint32_t txclk_delay_en; * uint32_t rxclk_delay_en; * uint32_t sgmii_delay_en; * uint32_t pipe_rxclk_sel; * * If mode isn't in the hints, 0 is returned. * Else the structure is fleshed out and 1 is returned. */ static int ar8327_fetch_pdata_pad(struct arswitch_softc *sc, struct ar8327_pad_cfg *pc, int pad) { int val; char sbuf[128]; /* Check if mode exists */ val = 0; snprintf(sbuf, 128, "pad.%d.mode", pad); if (resource_int_value(device_get_name(sc->sc_dev), device_get_unit(sc->sc_dev), sbuf, &val) != 0) return (0); /* assume that 'mode' exists and was found */ pc->mode = val; snprintf(sbuf, 128, "pad.%d.rxclk_sel", pad); if (resource_int_value(device_get_name(sc->sc_dev), device_get_unit(sc->sc_dev), sbuf, &val) == 0) pc->rxclk_sel = val; snprintf(sbuf, 128, "pad.%d.txclk_sel", pad); if (resource_int_value(device_get_name(sc->sc_dev), device_get_unit(sc->sc_dev), sbuf, &val) == 0) pc->txclk_sel = val; snprintf(sbuf, 128, "pad.%d.txclk_delay_sel", pad); if (resource_int_value(device_get_name(sc->sc_dev), device_get_unit(sc->sc_dev), sbuf, &val) == 0) pc->txclk_delay_sel = val; snprintf(sbuf, 128, "pad.%d.rxclk_delay_sel", pad); if (resource_int_value(device_get_name(sc->sc_dev), device_get_unit(sc->sc_dev), sbuf, &val) == 0) pc->rxclk_delay_sel = val; snprintf(sbuf, 128, "pad.%d.txclk_delay_en", pad); if (resource_int_value(device_get_name(sc->sc_dev), device_get_unit(sc->sc_dev), sbuf, &val) == 0) pc->txclk_delay_en = val; snprintf(sbuf, 128, "pad.%d.rxclk_delay_en", pad); if (resource_int_value(device_get_name(sc->sc_dev), device_get_unit(sc->sc_dev), sbuf, &val) == 0) pc->rxclk_delay_en = val; snprintf(sbuf, 128, "pad.%d.sgmii_delay_en", pad); if (resource_int_value(device_get_name(sc->sc_dev), device_get_unit(sc->sc_dev), sbuf, &val) == 0) pc->sgmii_delay_en = val; snprintf(sbuf, 128, "pad.%d.pipe_rxclk_sel", pad); if (resource_int_value(device_get_name(sc->sc_dev), device_get_unit(sc->sc_dev), sbuf, &val) == 0) pc->pipe_rxclk_sel = val; if (bootverbose) { device_printf(sc->sc_dev, "%s: pad %d: mode=%d, rxclk_sel=%d, txclk_sel=%d, " "txclk_delay_sel=%d, rxclk_delay_sel=%d, txclk_delay_en=%d, " "rxclk_enable_en=%d, sgmii_delay_en=%d, pipe_rxclk_sel=%d\n", __func__, pad, pc->mode, pc->rxclk_sel, pc->txclk_sel, pc->txclk_delay_sel, pc->rxclk_delay_sel, pc->txclk_delay_en, pc->rxclk_delay_en, pc->sgmii_delay_en, pc->pipe_rxclk_sel); } return (1); } /* * Fetch the SGMII configuration block from the boot hints. */ static int ar8327_fetch_pdata_sgmii(struct arswitch_softc *sc, struct ar8327_sgmii_cfg *scfg) { int val; /* sgmii_ctrl */ val = 0; if (resource_int_value(device_get_name(sc->sc_dev), device_get_unit(sc->sc_dev), "sgmii.ctrl", &val) != 0) return (0); scfg->sgmii_ctrl = val; /* serdes_aen */ val = 0; if (resource_int_value(device_get_name(sc->sc_dev), device_get_unit(sc->sc_dev), "sgmii.serdes_aen", &val) != 0) return (0); scfg->serdes_aen = val; return (1); } /* * Fetch the LED configuration from the boot hints. */ static int ar8327_fetch_pdata_led(struct arswitch_softc *sc, struct ar8327_led_cfg *lcfg) { int val; val = 0; if (resource_int_value(device_get_name(sc->sc_dev), device_get_unit(sc->sc_dev), "led.ctrl0", &val) != 0) return (0); lcfg->led_ctrl0 = val; val = 0; if (resource_int_value(device_get_name(sc->sc_dev), device_get_unit(sc->sc_dev), "led.ctrl1", &val) != 0) return (0); lcfg->led_ctrl1 = val; val = 0; if (resource_int_value(device_get_name(sc->sc_dev), device_get_unit(sc->sc_dev), "led.ctrl2", &val) != 0) return (0); lcfg->led_ctrl2 = val; val = 0; if (resource_int_value(device_get_name(sc->sc_dev), device_get_unit(sc->sc_dev), "led.ctrl3", &val) != 0) return (0); lcfg->led_ctrl3 = val; val = 0; if (resource_int_value(device_get_name(sc->sc_dev), device_get_unit(sc->sc_dev), "led.open_drain", &val) != 0) return (0); lcfg->open_drain = val; return (1); } /* * Initialise the ar8327 specific hardware features from * the hints provided in the boot environment. */ static int ar8327_init_pdata(struct arswitch_softc *sc) { struct ar8327_pad_cfg pc; struct ar8327_port_cfg port_cfg; struct ar8327_sgmii_cfg scfg; struct ar8327_led_cfg lcfg; uint32_t t, new_pos, pos; /* Port 0 */ bzero(&port_cfg, sizeof(port_cfg)); sc->ar8327.port0_status = 0; if (ar8327_fetch_pdata_port(sc, &port_cfg, 0)) sc->ar8327.port0_status = ar8327_get_port_init_status(&port_cfg); /* Port 6 */ bzero(&port_cfg, sizeof(port_cfg)); sc->ar8327.port6_status = 0; if (ar8327_fetch_pdata_port(sc, &port_cfg, 6)) sc->ar8327.port6_status = ar8327_get_port_init_status(&port_cfg); /* Pad 0 */ bzero(&pc, sizeof(pc)); t = 0; if (ar8327_fetch_pdata_pad(sc, &pc, 0)) t = ar8327_get_pad_cfg(&pc); #if 0 if (AR8X16_IS_SWITCH(sc, AR8337)) t |= AR8337_PAD_MAC06_EXCHANGE_EN; #endif arswitch_writereg(sc->sc_dev, AR8327_REG_PAD0_MODE, t); /* Pad 5 */ bzero(&pc, sizeof(pc)); t = 0; if (ar8327_fetch_pdata_pad(sc, &pc, 5)) t = ar8327_get_pad_cfg(&pc); arswitch_writereg(sc->sc_dev, AR8327_REG_PAD5_MODE, t); /* Pad 6 */ bzero(&pc, sizeof(pc)); t = 0; if (ar8327_fetch_pdata_pad(sc, &pc, 6)) t = ar8327_get_pad_cfg(&pc); arswitch_writereg(sc->sc_dev, AR8327_REG_PAD6_MODE, t); pos = arswitch_readreg(sc->sc_dev, AR8327_REG_POWER_ON_STRIP); new_pos = pos; /* XXX LED config */ bzero(&lcfg, sizeof(lcfg)); if (ar8327_fetch_pdata_led(sc, &lcfg)) { if (lcfg.open_drain) new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN; else new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN; arswitch_writereg(sc->sc_dev, AR8327_REG_LED_CTRL0, lcfg.led_ctrl0); arswitch_writereg(sc->sc_dev, AR8327_REG_LED_CTRL1, lcfg.led_ctrl1); arswitch_writereg(sc->sc_dev, AR8327_REG_LED_CTRL2, lcfg.led_ctrl2); arswitch_writereg(sc->sc_dev, AR8327_REG_LED_CTRL3, lcfg.led_ctrl3); if (new_pos != pos) new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL; } /* SGMII config */ bzero(&scfg, sizeof(scfg)); if (ar8327_fetch_pdata_sgmii(sc, &scfg)) { device_printf(sc->sc_dev, "%s: SGMII cfg?\n", __func__); t = scfg.sgmii_ctrl; if (sc->chip_rev == 1) t |= AR8327_SGMII_CTRL_EN_PLL | AR8327_SGMII_CTRL_EN_RX | AR8327_SGMII_CTRL_EN_TX; else t &= ~(AR8327_SGMII_CTRL_EN_PLL | AR8327_SGMII_CTRL_EN_RX | AR8327_SGMII_CTRL_EN_TX); arswitch_writereg(sc->sc_dev, AR8327_REG_SGMII_CTRL, t); if (scfg.serdes_aen) new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN; else new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN; } arswitch_writereg(sc->sc_dev, AR8327_REG_POWER_ON_STRIP, new_pos); return (0); } static int ar8327_hw_setup(struct arswitch_softc *sc) { int i; int err; /* pdata fetch and setup */ err = ar8327_init_pdata(sc); if (err != 0) return (err); /* XXX init leds */ for (i = 0; i < AR8327_NUM_PHYS; i++) { /* phy fixup */ ar8327_phy_fixup(sc, i); /* start PHY autonegotiation? */ /* XXX is this done as part of the normal PHY setup? */ } /* Let things settle */ DELAY(1000); return (0); } /* * Initialise other global values, for the AR8327. */ static int ar8327_hw_global_setup(struct arswitch_softc *sc) { uint32_t t; /* enable CPU port and disable mirror port */ t = AR8327_FWD_CTRL0_CPU_PORT_EN | AR8327_FWD_CTRL0_MIRROR_PORT; arswitch_writereg(sc->sc_dev, AR8327_REG_FWD_CTRL0, t); /* forward multicast and broadcast frames to CPU */ t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) | (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) | (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S); arswitch_writereg(sc->sc_dev, AR8327_REG_FWD_CTRL1, t); /* enable jumbo frames */ /* XXX need to macro-shift the value! */ arswitch_modifyreg(sc->sc_dev, AR8327_REG_MAX_FRAME_SIZE, AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2); /* Enable MIB counters */ arswitch_modifyreg(sc->sc_dev, AR8327_REG_MODULE_EN, AR8327_MODULE_EN_MIB, AR8327_MODULE_EN_MIB); /* Disable EEE on all ports due to stability issues */ t = arswitch_readreg(sc->sc_dev, AR8327_REG_EEE_CTRL); t |= AR8327_EEE_CTRL_DISABLE_PHY(0) | AR8327_EEE_CTRL_DISABLE_PHY(1) | AR8327_EEE_CTRL_DISABLE_PHY(2) | AR8327_EEE_CTRL_DISABLE_PHY(3) | AR8327_EEE_CTRL_DISABLE_PHY(4); arswitch_writereg(sc->sc_dev, AR8327_REG_EEE_CTRL, t); /* Set the right number of ports */ /* GMAC0 (CPU), GMAC1..5 (PHYs), GMAC6 (CPU) */ sc->info.es_nports = 7; return (0); } /* * Port setup. Called at attach time. */ static void ar8327_port_init(struct arswitch_softc *sc, int port) { uint32_t t; int ports; /* For now, port can see all other ports */ ports = 0x7f; if (port == AR8X16_PORT_CPU) t = sc->ar8327.port0_status; else if (port == 6) t = sc->ar8327.port6_status; else t = AR8X16_PORT_STS_LINK_AUTO; arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_STATUS(port), t); arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_HEADER(port), 0); /* * Default to 1 port group. */ t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S; t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S; arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN0(port), t); t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S; arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN1(port), t); /* * This doesn't configure any ports which this port can "see". * bits 0-6 control which ports a frame coming into this port * can be sent out to. * * So by doing this, we're making it impossible to send frames out * to that port. */ t = AR8327_PORT_LOOKUP_LEARN; t |= AR8X16_PORT_CTRL_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S; /* So this allows traffic to any port except ourselves */ t |= (ports & ~(1 << port)); arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(port), t); } static int ar8327_port_vlan_setup(struct arswitch_softc *sc, etherswitch_port_t *p) { /* Check: ADDTAG/STRIPTAG - exclusive */ ARSWITCH_LOCK(sc); /* Set the PVID. */ if (p->es_pvid != 0) sc->hal.arswitch_vlan_set_pvid(sc, p->es_port, p->es_pvid); /* * DOUBLE_TAG * VLAN_MODE_ADD * VLAN_MODE_STRIP */ ARSWITCH_UNLOCK(sc); return (0); } /* * Get the port VLAN configuration. */ static int ar8327_port_vlan_get(struct arswitch_softc *sc, etherswitch_port_t *p) { ARSWITCH_LOCK(sc); /* Retrieve the PVID */ sc->hal.arswitch_vlan_get_pvid(sc, p->es_port, &p->es_pvid); /* Retrieve the current port configuration from the VTU */ /* * DOUBLE_TAG * VLAN_MODE_ADD * VLAN_MODE_STRIP */ ARSWITCH_UNLOCK(sc); return (0); } static void ar8327_port_disable_mirror(struct arswitch_softc *sc, int port) { arswitch_modifyreg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(port), AR8327_PORT_LOOKUP_ING_MIRROR_EN, 0); arswitch_modifyreg(sc->sc_dev, AR8327_REG_PORT_HOL_CTRL1(port), AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN, 0); } static void ar8327_reset_vlans(struct arswitch_softc *sc) { int i; uint32_t t; int ports; ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED); ARSWITCH_LOCK(sc); /* Clear the existing VLAN configuration */ memset(sc->vid, 0, sizeof(sc->vid)); /* * Disable mirroring. */ arswitch_modifyreg(sc->sc_dev, AR8327_REG_FWD_CTRL0, AR8327_FWD_CTRL0_MIRROR_PORT, (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S)); /* * XXX TODO: disable any Q-in-Q port configuration, * tagging, egress filters, etc. */ /* * For now, let's default to one portgroup, just so traffic * flows. All ports can see other ports. There are two CPU GMACs * (GMAC0, GMAC6), GMAC1..GMAC5 are external PHYs. * * (ETHERSWITCH_VLAN_PORT) */ ports = 0x7f; /* * XXX TODO: set things up correctly for vlans! */ for (i = 0; i < AR8327_NUM_PORTS; i++) { int egress, ingress; if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) { sc->vid[i] = i | ETHERSWITCH_VID_VALID; /* set egress == out_keep */ ingress = AR8X16_PORT_VLAN_MODE_PORT_ONLY; /* in_port_only, forward */ egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH; } else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { ingress = AR8X16_PORT_VLAN_MODE_SECURE; egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD; } else { /* set egress == out_keep */ ingress = AR8X16_PORT_VLAN_MODE_PORT_ONLY; /* in_port_only, forward */ egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH; } /* set pvid = 1; there's only one vlangroup to start with */ t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S; t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S; arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN0(i), t); t = AR8327_PORT_VLAN1_PORT_VLAN_PROP; t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S; arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN1(i), t); /* Ports can see other ports */ /* XXX not entirely true for dot1q? */ t = (ports & ~(1 << i)); /* all ports besides us */ t |= AR8327_PORT_LOOKUP_LEARN; t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S; t |= AR8X16_PORT_CTRL_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S; arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(i), t); } /* * Disable port mirroring entirely. */ for (i = 0; i < AR8327_NUM_PORTS; i++) { ar8327_port_disable_mirror(sc, i); } /* * If dot1q - set pvid; dot1q, etc. */ if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { sc->vid[0] = 1; for (i = 0; i < AR8327_NUM_PORTS; i++) { /* Each port - pvid 1 */ sc->hal.arswitch_vlan_set_pvid(sc, i, sc->vid[0]); } /* Initialise vlan1 - all ports, untagged */ sc->hal.arswitch_set_dot1q_vlan(sc, ports, ports, sc->vid[0]); sc->vid[0] |= ETHERSWITCH_VID_VALID; } ARSWITCH_UNLOCK(sc); } static int ar8327_vlan_get_port(struct arswitch_softc *sc, uint32_t *ports, int vid) { int port; uint32_t reg; ARSWITCH_LOCK_ASSERT(sc, MA_OWNED); /* For port based vlans the vlanid is the same as the port index. */ port = vid & ETHERSWITCH_VID_MASK; reg = arswitch_readreg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(port)); *ports = reg & 0x7f; return (0); } static int ar8327_vlan_set_port(struct arswitch_softc *sc, uint32_t ports, int vid) { int err, port; ARSWITCH_LOCK_ASSERT(sc, MA_OWNED); /* For port based vlans the vlanid is the same as the port index. */ port = vid & ETHERSWITCH_VID_MASK; err = arswitch_modifyreg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(port), 0x7f, /* vlan membership mask */ (ports & 0x7f)); if (err) return (err); return (0); } static int ar8327_vlan_getvgroup(struct arswitch_softc *sc, etherswitch_vlangroup_t *vg) { return (ar8xxx_getvgroup(sc, vg)); } static int ar8327_vlan_setvgroup(struct arswitch_softc *sc, etherswitch_vlangroup_t *vg) { return (ar8xxx_setvgroup(sc, vg)); } static int ar8327_get_pvid(struct arswitch_softc *sc, int port, int *pvid) { uint32_t reg; ARSWITCH_LOCK_ASSERT(sc, MA_OWNED); /* * XXX for now, assuming it's CVID; likely very wrong! */ port = port & ETHERSWITCH_VID_MASK; reg = arswitch_readreg(sc->sc_dev, AR8327_REG_PORT_VLAN0(port)); reg = reg >> AR8327_PORT_VLAN0_DEF_CVID_S; reg = reg & 0xfff; *pvid = reg; return (0); } static int ar8327_set_pvid(struct arswitch_softc *sc, int port, int pvid) { uint32_t t; /* Limit pvid to valid values */ pvid &= 0x7f; t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S; t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S; arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN0(port), t); return (0); } static int ar8327_atu_flush(struct arswitch_softc *sc) { int ret; ret = arswitch_waitreg(sc->sc_dev, AR8327_REG_ATU_FUNC, AR8327_ATU_FUNC_BUSY, 0, 1000); if (ret) device_printf(sc->sc_dev, "%s: waitreg failed\n", __func__); if (!ret) arswitch_writereg(sc->sc_dev, AR8327_REG_ATU_FUNC, AR8327_ATU_FUNC_OP_FLUSH); return (ret); } static int ar8327_flush_dot1q_vlan(struct arswitch_softc *sc) { return (ar8327_vlan_op(sc, AR8327_VTU_FUNC1_OP_FLUSH, 0, 0)); } static int ar8327_purge_dot1q_vlan(struct arswitch_softc *sc, int vid) { return (ar8327_vlan_op(sc, AR8327_VTU_FUNC1_OP_PURGE, vid, 0)); } static int ar8327_get_dot1q_vlan(struct arswitch_softc *sc, uint32_t *ports, uint32_t *untagged_ports, int vid) { int i, r; uint32_t op, reg, val; op = AR8327_VTU_FUNC1_OP_GET_ONE; /* Filter out the vid flags; only grab the VLAN ID */ vid &= 0xfff; /* XXX TODO: the VTU here stores egress mode - keep, tag, untagged, none */ r = ar8327_vlan_op(sc, op, vid, 0); if (r != 0) { device_printf(sc->sc_dev, "%s: %d: op failed\n", __func__, vid); } reg = arswitch_readreg(sc->sc_dev, AR8327_REG_VTU_FUNC0); - DPRINTF(sc->sc_dev, "%s: %d: reg=0x%08x\n", __func__, vid, reg); + DPRINTF(sc, ARSWITCH_DBG_REGIO, "%s: %d: reg=0x%08x\n", __func__, vid, reg); /* * If any of the bits are set, update the port mask. * Worry about the port config itself when getport() is called. */ *ports = 0; for (i = 0; i < AR8327_NUM_PORTS; i++) { val = reg >> AR8327_VTU_FUNC0_EG_MODE_S(i); val = val & 0x3; /* XXX KEEP (unmodified?) */ if (val == AR8327_VTU_FUNC0_EG_MODE_TAG) { *ports |= (1 << i); } else if (val == AR8327_VTU_FUNC0_EG_MODE_UNTAG) { *ports |= (1 << i); *untagged_ports |= (1 << i); } } return (0); } static int ar8327_set_dot1q_vlan(struct arswitch_softc *sc, uint32_t ports, uint32_t untagged_ports, int vid) { int i; uint32_t op, val, mode; op = AR8327_VTU_FUNC1_OP_LOAD; vid &= 0xfff; - DPRINTF(sc->sc_dev, + DPRINTF(sc, ARSWITCH_DBG_VLAN, "%s: vid: %d, ports=0x%08x, untagged_ports=0x%08x\n", __func__, vid, ports, untagged_ports); /* * Mark it as valid; and that it should use per-VLAN MAC table, * not VID=0 when doing MAC lookups */ val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL; for (i = 0; i < AR8327_NUM_PORTS; i++) { if ((ports & BIT(i)) == 0) mode = AR8327_VTU_FUNC0_EG_MODE_NOT; else if (untagged_ports & BIT(i)) mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG; else mode = AR8327_VTU_FUNC0_EG_MODE_TAG; val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i); } return (ar8327_vlan_op(sc, op, vid, val)); } void ar8327_attach(struct arswitch_softc *sc) { sc->hal.arswitch_hw_setup = ar8327_hw_setup; sc->hal.arswitch_hw_global_setup = ar8327_hw_global_setup; sc->hal.arswitch_port_init = ar8327_port_init; sc->hal.arswitch_vlan_getvgroup = ar8327_vlan_getvgroup; sc->hal.arswitch_vlan_setvgroup = ar8327_vlan_setvgroup; sc->hal.arswitch_port_vlan_setup = ar8327_port_vlan_setup; sc->hal.arswitch_port_vlan_get = ar8327_port_vlan_get; sc->hal.arswitch_flush_dot1q_vlan = ar8327_flush_dot1q_vlan; sc->hal.arswitch_purge_dot1q_vlan = ar8327_purge_dot1q_vlan; sc->hal.arswitch_set_dot1q_vlan = ar8327_set_dot1q_vlan; sc->hal.arswitch_get_dot1q_vlan = ar8327_get_dot1q_vlan; sc->hal.arswitch_vlan_init_hw = ar8327_reset_vlans; sc->hal.arswitch_vlan_get_pvid = ar8327_get_pvid; sc->hal.arswitch_vlan_set_pvid = ar8327_set_pvid; sc->hal.arswitch_get_port_vlan = ar8327_vlan_get_port; sc->hal.arswitch_set_port_vlan = ar8327_vlan_set_port; sc->hal.arswitch_atu_flush = ar8327_atu_flush; /* * Reading the PHY via the MDIO interface currently doesn't * work correctly. * * So for now, just go direct to the PHY registers themselves. * This has always worked on external devices, but not internal * devices (AR934x, AR724x, AR933x.) */ sc->hal.arswitch_phy_read = arswitch_readphy_external; sc->hal.arswitch_phy_write = arswitch_writephy_external; /* Set the switch vlan capabilities. */ sc->info.es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q | ETHERSWITCH_VLAN_PORT | ETHERSWITCH_VLAN_DOUBLE_TAG; sc->info.es_nvlangroups = AR8X16_MAX_VLANS; } Index: head/sys/dev/etherswitch/arswitch/arswitch_phy.c =================================================================== --- head/sys/dev/etherswitch/arswitch/arswitch_phy.c (revision 303809) +++ head/sys/dev/etherswitch/arswitch/arswitch_phy.c (revision 303810) @@ -1,197 +1,201 @@ /*- * Copyright (c) 2011-2012 Stefan Bethke. * Copyright (c) 2012 Adrian Chadd. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "mdio_if.h" #include "miibus_if.h" #include "etherswitch_if.h" -#if defined(DEBUG) -static SYSCTL_NODE(_debug, OID_AUTO, arswitch, CTLFLAG_RD, 0, "arswitch"); -#endif - /* * Access PHYs integrated into the switch by going direct * to the PHY space itself, rather than through the switch * MDIO register. */ int arswitch_readphy_external(device_t dev, int phy, int reg) { int ret; struct arswitch_softc *sc; sc = device_get_softc(dev); ARSWITCH_LOCK(sc); ret = (MDIO_READREG(device_get_parent(dev), phy, reg)); + DPRINTF(sc, ARSWITCH_DBG_PHYIO, + "%s: phy=0x%08x, reg=0x%08x, ret=0x%08x\n", + __func__, phy, reg, ret); ARSWITCH_UNLOCK(sc); return (ret); } int arswitch_writephy_external(device_t dev, int phy, int reg, int data) { struct arswitch_softc *sc; sc = device_get_softc(dev); ARSWITCH_LOCK(sc); (void) MDIO_WRITEREG(device_get_parent(dev), phy, reg, data); + DPRINTF(sc, ARSWITCH_DBG_PHYIO, + "%s: phy=0x%08x, reg=0x%08x, data=0x%08x\n", + __func__, phy, reg, data); ARSWITCH_UNLOCK(sc); return (0); } /* * Access PHYs integrated into the switch chip through the switch's MDIO * control register. */ int arswitch_readphy_internal(device_t dev, int phy, int reg) { struct arswitch_softc *sc; uint32_t data = 0, ctrl; int err, timeout; uint32_t a; sc = device_get_softc(dev); ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED); if (phy < 0 || phy >= 32) return (ENXIO); if (reg < 0 || reg >= 32) return (ENXIO); if (AR8X16_IS_SWITCH(sc, AR8327)) a = AR8327_REG_MDIO_CTRL; else a = AR8X16_REG_MDIO_CTRL; ARSWITCH_LOCK(sc); err = arswitch_writereg_msb(dev, a, AR8X16_MDIO_CTRL_BUSY | AR8X16_MDIO_CTRL_MASTER_EN | AR8X16_MDIO_CTRL_CMD_READ | (phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) | (reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT)); DEVERR(dev, err, "arswitch_readphy()=%d: phy=%d.%02x\n", phy, reg); if (err != 0) goto fail; for (timeout = 100; timeout--; ) { ctrl = arswitch_readreg_msb(dev, a); if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0) break; } if (timeout < 0) { - DPRINTF(dev, "arswitch_readphy(): phy=%d.%02x; timeout=%d\n", phy, reg, timeout); + DPRINTF(sc, ARSWITCH_DBG_ANY, + "arswitch_readphy(): phy=%d.%02x; timeout=%d\n", + phy, reg, timeout); goto fail; } data = arswitch_readreg_lsb(dev, a) & AR8X16_MDIO_CTRL_DATA_MASK; ARSWITCH_UNLOCK(sc); return (data); fail: ARSWITCH_UNLOCK(sc); return (-1); } int arswitch_writephy_internal(device_t dev, int phy, int reg, int data) { struct arswitch_softc *sc; uint32_t ctrl; int err, timeout; uint32_t a; sc = device_get_softc(dev); ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED); if (reg < 0 || reg >= 32) return (ENXIO); if (AR8X16_IS_SWITCH(sc, AR8327)) a = AR8327_REG_MDIO_CTRL; else a = AR8X16_REG_MDIO_CTRL; ARSWITCH_LOCK(sc); err = arswitch_writereg(dev, a, AR8X16_MDIO_CTRL_BUSY | AR8X16_MDIO_CTRL_MASTER_EN | AR8X16_MDIO_CTRL_CMD_WRITE | (phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) | (reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT) | (data & AR8X16_MDIO_CTRL_DATA_MASK)); if (err != 0) goto out; for (timeout = 100; timeout--; ) { ctrl = arswitch_readreg(dev, a); if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0) break; } if (timeout < 0) err = EIO; out: DEVERR(dev, err, "arswitch_writephy()=%d: phy=%d.%02x\n", phy, reg); ARSWITCH_UNLOCK(sc); return (err); } Index: head/sys/dev/etherswitch/arswitch/arswitch_reg.c =================================================================== --- head/sys/dev/etherswitch/arswitch/arswitch_reg.c (revision 303809) +++ head/sys/dev/etherswitch/arswitch/arswitch_reg.c (revision 303810) @@ -1,265 +1,275 @@ /*- * Copyright (c) 2011-2012 Stefan Bethke. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "mdio_if.h" #include "miibus_if.h" #include "etherswitch_if.h" static inline void arswitch_split_setpage(device_t dev, uint32_t addr, uint16_t *phy, uint16_t *reg) { struct arswitch_softc *sc = device_get_softc(dev); uint16_t page; page = (addr >> 9) & 0x1ff; *phy = (addr >> 6) & 0x7; *reg = (addr >> 1) & 0x1f; if (sc->page != page) { MDIO_WRITEREG(device_get_parent(dev), 0x18, 0, page); DELAY(2000); sc->page = page; } } /* * Read half a register. Some of the registers define control bits, and * the sequence of half-word accesses matters. The register addresses * are word-even (mod 4). */ static inline int arswitch_readreg16(device_t dev, int addr) { uint16_t phy, reg; arswitch_split_setpage(dev, addr, &phy, ®); return (MDIO_READREG(device_get_parent(dev), 0x10 | phy, reg)); } /* * Write half a register. See above! */ static inline int arswitch_writereg16(device_t dev, int addr, int data) { uint16_t phy, reg; arswitch_split_setpage(dev, addr, &phy, ®); return (MDIO_WRITEREG(device_get_parent(dev), 0x10 | phy, reg, data)); } /* * XXX NOTE: * * This may not work for AR7240 series embedded switches - * the per-PHY register space doesn't seem to be exposed. * * In that instance, it may be required to speak via * the internal switch PHY MDIO bus indirection. */ void arswitch_writedbg(device_t dev, int phy, uint16_t dbg_addr, uint16_t dbg_data) { (void) MDIO_WRITEREG(device_get_parent(dev), phy, MII_ATH_DBG_ADDR, dbg_addr); (void) MDIO_WRITEREG(device_get_parent(dev), phy, MII_ATH_DBG_DATA, dbg_data); } void arswitch_writemmd(device_t dev, int phy, uint16_t dbg_addr, uint16_t dbg_data) { (void) MDIO_WRITEREG(device_get_parent(dev), phy, MII_ATH_MMD_ADDR, dbg_addr); (void) MDIO_WRITEREG(device_get_parent(dev), phy, MII_ATH_MMD_DATA, dbg_data); } static uint32_t arswitch_reg_read32(device_t dev, int phy, int reg) { uint16_t lo, hi; lo = MDIO_READREG(device_get_parent(dev), phy, reg); hi = MDIO_READREG(device_get_parent(dev), phy, reg + 1); return (hi << 16) | lo; } static int arswitch_reg_write32(device_t dev, int phy, int reg, uint32_t value) { struct arswitch_softc *sc; int r; uint16_t lo, hi; sc = device_get_softc(dev); lo = value & 0xffff; hi = (uint16_t) (value >> 16); if (sc->mii_lo_first) { r = MDIO_WRITEREG(device_get_parent(dev), phy, reg, lo); r |= MDIO_WRITEREG(device_get_parent(dev), phy, reg + 1, hi); } else { r = MDIO_WRITEREG(device_get_parent(dev), phy, reg + 1, hi); r |= MDIO_WRITEREG(device_get_parent(dev), phy, reg, lo); } return r; } int arswitch_readreg(device_t dev, int addr) { uint16_t phy, reg; arswitch_split_setpage(dev, addr, &phy, ®); return arswitch_reg_read32(dev, 0x10 | phy, reg); } int arswitch_writereg(device_t dev, int addr, int value) { struct arswitch_softc *sc; uint16_t phy, reg; sc = device_get_softc(dev); arswitch_split_setpage(dev, addr, &phy, ®); return (arswitch_reg_write32(dev, 0x10 | phy, reg, value)); } /* * Read/write 16 bit values in the switch register space. * * Some of the registers are control registers (eg the MDIO * data versus control space) and so need to be treated * differently. */ int arswitch_readreg_lsb(device_t dev, int addr) { return (arswitch_readreg16(dev, addr)); } int arswitch_readreg_msb(device_t dev, int addr) { return (arswitch_readreg16(dev, addr + 2) << 16); } int arswitch_writereg_lsb(device_t dev, int addr, int data) { return (arswitch_writereg16(dev, addr, data & 0xffff)); } int arswitch_writereg_msb(device_t dev, int addr, int data) { return (arswitch_writereg16(dev, addr + 2, (data >> 16) & 0xffff)); } int arswitch_modifyreg(device_t dev, int addr, int mask, int set) { int value; uint16_t phy, reg; + ARSWITCH_LOCK_ASSERT(sc, MA_OWNED); + arswitch_split_setpage(dev, addr, &phy, ®); value = arswitch_reg_read32(dev, 0x10 | phy, reg); value &= ~mask; value |= set; return (arswitch_reg_write32(dev, 0x10 | phy, reg, value)); } int arswitch_waitreg(device_t dev, int addr, int mask, int val, int timeout) { + struct arswitch_softc *sc = device_get_softc(dev); int err, v; uint16_t phy, reg; + ARSWITCH_LOCK_ASSERT(sc, MA_OWNED); + arswitch_split_setpage(dev, addr, &phy, ®); err = -1; while (1) { v = arswitch_reg_read32(dev, 0x10 | phy, reg); v &= mask; if (v == val) { err = 0; break; } if (!timeout) break; DELAY(1); timeout--; + } + if (err != 0) { + DPRINTF(sc, ARSWITCH_DBG_ANY, + "%s: waitreg failed; addr=0x%08x, mask=0x%08x, val=0x%08x\n", + __func__, addr, mask, val); } return (err); } Index: head/sys/dev/etherswitch/arswitch/arswitchvar.h =================================================================== --- head/sys/dev/etherswitch/arswitch/arswitchvar.h (revision 303809) +++ head/sys/dev/etherswitch/arswitch/arswitchvar.h (revision 303810) @@ -1,160 +1,171 @@ /*- * Copyright (c) 2011-2012 Stefan Bethke. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef __ARSWITCHVAR_H__ #define __ARSWITCHVAR_H__ typedef enum { AR8X16_SWITCH_NONE, AR8X16_SWITCH_AR7240, AR8X16_SWITCH_AR8216, AR8X16_SWITCH_AR8226, AR8X16_SWITCH_AR8316, AR8X16_SWITCH_AR9340, AR8X16_SWITCH_AR8327, AR8X16_SWITCH_AR8337, } ar8x16_switch_type; /* * XXX TODO: start using this where required */ #define AR8X16_IS_SWITCH(_sc, _type) \ (!!((_sc)->sc_switchtype == AR8X16_SWITCH_ ## _type)) #define ARSWITCH_NUM_PORTS MAX(AR8327_NUM_PORTS, AR8X16_NUM_PORTS) #define ARSWITCH_NUM_PHYS MAX(AR8327_NUM_PHYS, AR8X16_NUM_PHYS) #define ARSWITCH_NUM_LEDS 3 struct arswitch_dev_led { struct arswitch_softc *sc; struct cdev *led; int phy; int lednum; }; struct arswitch_softc { struct mtx sc_mtx; /* serialize access to softc */ device_t sc_dev; int phy4cpu; /* PHY4 is connected to the CPU */ int numphys; /* PHYs we manage */ int is_rgmii; /* PHY mode is RGMII (XXX which PHY?) */ int is_gmii; /* PHY mode is GMII (XXX which PHY?) */ int is_mii; /* PHY mode is MII (XXX which PHY?) */ int page; int is_internal_switch; int chip_ver; int chip_rev; int mii_lo_first; /* Send low data DWORD before high */ ar8x16_switch_type sc_switchtype; /* should be the max of both pre-AR8327 and AR8327 ports */ char *ifname[ARSWITCH_NUM_PHYS]; device_t miibus[ARSWITCH_NUM_PHYS]; struct ifnet *ifp[ARSWITCH_NUM_PHYS]; struct arswitch_dev_led dev_led[ARSWITCH_NUM_PHYS][ARSWITCH_NUM_LEDS]; struct callout callout_tick; etherswitch_info_t info; + uint32_t sc_debug; + /* VLANs support */ int vid[AR8X16_MAX_VLANS]; uint32_t vlan_mode; struct { /* Global setup */ int (* arswitch_hw_setup) (struct arswitch_softc *); int (* arswitch_hw_global_setup) (struct arswitch_softc *); /* Port functions */ void (* arswitch_port_init) (struct arswitch_softc *, int); /* ATU functions */ int (* arswitch_atu_flush) (struct arswitch_softc *); /* VLAN functions */ int (* arswitch_port_vlan_setup) (struct arswitch_softc *, etherswitch_port_t *); int (* arswitch_port_vlan_get) (struct arswitch_softc *, etherswitch_port_t *); void (* arswitch_vlan_init_hw) (struct arswitch_softc *); int (* arswitch_vlan_getvgroup) (struct arswitch_softc *, etherswitch_vlangroup_t *); int (* arswitch_vlan_setvgroup) (struct arswitch_softc *, etherswitch_vlangroup_t *); int (* arswitch_vlan_get_pvid) (struct arswitch_softc *, int, int *); int (* arswitch_vlan_set_pvid) (struct arswitch_softc *, int, int); int (* arswitch_flush_dot1q_vlan) (struct arswitch_softc *sc); int (* arswitch_purge_dot1q_vlan) (struct arswitch_softc *sc, int vid); int (* arswitch_get_dot1q_vlan) (struct arswitch_softc *, uint32_t *ports, uint32_t *untagged_ports, int vid); int (* arswitch_set_dot1q_vlan) (struct arswitch_softc *sc, uint32_t ports, uint32_t untagged_ports, int vid); int (* arswitch_get_port_vlan) (struct arswitch_softc *sc, uint32_t *ports, int vid); int (* arswitch_set_port_vlan) (struct arswitch_softc *sc, uint32_t ports, int vid); /* PHY functions */ int (* arswitch_phy_read) (device_t, int, int); int (* arswitch_phy_write) (device_t, int, int, int); } hal; struct { uint32_t port0_status; uint32_t port5_status; uint32_t port6_status; } ar8327; }; #define ARSWITCH_LOCK(_sc) \ mtx_lock(&(_sc)->sc_mtx) #define ARSWITCH_UNLOCK(_sc) \ mtx_unlock(&(_sc)->sc_mtx) #define ARSWITCH_LOCK_ASSERT(_sc, _what) \ mtx_assert(&(_sc)->sc_mtx, (_what)) #define ARSWITCH_TRYLOCK(_sc) \ mtx_trylock(&(_sc)->sc_mtx) -#if defined(DEBUG) -#define DPRINTF(dev, args...) device_printf(dev, args) +#define ARSWITCH_DBG_RESET 0x00000001 +#define ARSWITCH_DBG_REGIO 0x00000002 +#define ARSWITCH_DBG_PHYIO 0x00000004 +#define ARSWITCH_DBG_POLL 0x00000008 +#define ARSWITCH_DBG_VLAN 0x00000010 +#define ARSWITCH_DBG_ANY 0xffffffff + +#if 1 +#define DPRINTF(sc, dbg, args...) \ + do { \ + if (((sc)->sc_debug & (dbg)) || \ + ((sc)->sc_debug == ARSWITCH_DBG_ANY)) { \ + device_printf((sc)->sc_dev, args); \ + } \ + } while (0) #define DEVERR(dev, err, fmt, args...) do { \ if (err != 0) device_printf(dev, fmt, err, args); \ } while (0) -#define DEBUG_INCRVAR(var) do { \ - var++; \ - } while (0) #else -#define DPRINTF(dev, args...) +#define DPRINTF(dev, dbg, args...) #define DEVERR(dev, err, fmt, args...) -#define DEBUG_INCRVAR(var) #endif #endif /* __ARSWITCHVAR_H__ */