Index: head/sys/arm/broadcom/bcm2835/bcm2835_rng.c =================================================================== --- head/sys/arm/broadcom/bcm2835/bcm2835_rng.c (nonexistent) +++ head/sys/arm/broadcom/bcm2835/bcm2835_rng.c (revision 303035) @@ -0,0 +1,534 @@ +/* + * Copyright (c) 2015, 2016, Stephen J. Kiernan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include + +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include + +#if !defined(BCM2835_RNG_USE_CALLOUT) +#define BCM2835_RNG_USE_INTERRUPT +#endif + +static device_attach_t bcm2835_rng_attach; +static device_detach_t bcm2835_rng_detach; +static device_probe_t bcm2835_rng_probe; + +#define RNG_CTRL 0x00 /* RNG Control Register */ +#define RNG_COMBLK1_OSC 0x003f0000 /* Combiner Blk 1 Oscillator */ +#define RNG_COMBLK1_OSC_SHIFT 16 +#define RNG_COMBLK2_OSC 0x0fc00000 /* Combiner Blk 2 Oscillator */ +#define RNG_COMBLK2_OSC_SHIFT 22 +#define RNG_JCLK_BYP_DIV_CNT 0x0000ff00 /* Jitter clk bypass divider + count */ +#define RNG_JCLK_BYP_DIV_CNT_SHIFT 8 +#define RNG_JCLK_BYP_SRC 0x00000020 /* Jitter clk bypass source */ +#define RNG_JCLK_BYP_SEL 0x00000010 /* Jitter clk bypass select */ +#define RNG_RBG2X 0x00000002 /* RBG 2X SPEED */ +#define RNG_RBGEN_BIT 0x00000001 /* Enable RNG bit */ + +#define RNG_STATUS 0x04 /* RNG status register */ +#define RND_VAL_SHIFT 24 /* Shift for valid words */ +#define RND_VAL_MASK 0x000000ff /* Number valid words mask */ +#define RND_VAL_WARM_CNT 0x40000 /* RNG Warm Up count */ +#define RND_WARM_CNT 0xfffff /* RNG Warm Up Count mask */ + +#define RNG_DATA 0x08 /* RNG Data Register */ +#define RNG_FF_THRES 0x0c +#define RNG_FF_THRES_MASK 0x0000001f + +#define RNG_INT_MASK 0x10 +#define RNG_INT_OFF_BIT 0x00000001 + +#define RNG_FF_DEFAULT 0x10 /* FIFO threshold default */ + +#define RNG_FIFO_WORDS (RNG_FF_DEFAULT / sizeof(uint32_t)) + +#define RNG_NUM_OSCILLATORS 6 +#define RNG_STALL_COUNT_DEFAULT 10 + +struct bcm2835_rng_softc { + device_t sc_dev; + struct resource * sc_mem_res; + struct resource * sc_irq_res; + void * sc_intr_hdl; +#if defined(BCM2835_RNG_USE_CALLOUT) || defined(BCM2835_RNG_USE_INTERRUPT) + uint32_t sc_buf[RNG_FIFO_WORDS]; +#endif +#if defined(BCM2835_RNG_USE_CALLOUT) + struct callout sc_rngto; + int sc_rnghz; +#endif + int sc_stall_count; + int sc_rbg2x; + long sc_underrun; +}; + +static __inline void +bcm2835_rng_stat_inc_underrun(struct bcm2835_rng_softc *sc) +{ + + atomic_add_long(&sc->sc_underrun, 1); +} + +static __inline uint32_t +bcm2835_rng_read4(struct bcm2835_rng_softc *sc, bus_size_t off) +{ + + return bus_read_4(sc->sc_mem_res, off); +} + +static __inline void +bcm2835_rng_read_multi4(struct bcm2835_rng_softc *sc, bus_size_t off, + uint32_t *datap, bus_size_t count) +{ + + bus_read_multi_4(sc->sc_mem_res, off, datap, count); +} + +static __inline void +bcm2835_rng_write4(struct bcm2835_rng_softc *sc, bus_size_t off, uint32_t val) +{ + + bus_write_4(sc->sc_mem_res, off, val); +} + +static void +bcm2835_rng_dump_registers(struct bcm2835_rng_softc *sc, struct sbuf *sbp) +{ + uint32_t comblk2_osc, comblk1_osc, jclk_byp_div, val; + int i; + + /* Display RNG control register contents */ + val = bcm2835_rng_read4(sc, RNG_CTRL); + sbuf_printf(sbp, "RNG_CTRL (%08x)\n", val); + + comblk2_osc = (val & RNG_COMBLK2_OSC) >> RNG_COMBLK2_OSC_SHIFT; + sbuf_printf(sbp, " RNG_COMBLK2_OSC (%02x)\n", comblk2_osc); + for (i = 0; i < RNG_NUM_OSCILLATORS; i++) + if ((comblk2_osc & (1 << i)) == 0) + sbuf_printf(sbp, " Oscillator %d enabled\n", i + 1); + + comblk1_osc = (val & RNG_COMBLK1_OSC) >> RNG_COMBLK1_OSC_SHIFT; + sbuf_printf(sbp, " RNG_COMBLK1_OSC (%02x)\n", comblk1_osc); + for (i = 0; i < RNG_NUM_OSCILLATORS; i++) + if ((comblk1_osc & (1 << i)) == 0) + sbuf_printf(sbp, " Oscillator %d enabled\n", i + 1); + + jclk_byp_div = (val & RNG_JCLK_BYP_DIV_CNT) >> + RNG_JCLK_BYP_DIV_CNT_SHIFT; + sbuf_printf(sbp, + " RNG_JCLK_BYP_DIV_CNT (%02x)\n APB clock frequency / %d\n", + jclk_byp_div, 2 * (jclk_byp_div + 1)); + + sbuf_printf(sbp, " RNG_JCLK_BYP_SRC:\n %s\n", + (val & RNG_JCLK_BYP_SRC) ? "Use divided down APB clock" : + "Use RNG clock (APB clock)"); + + sbuf_printf(sbp, " RNG_JCLK_BYP_SEL:\n %s\n", + (val & RNG_JCLK_BYP_SEL) ? "Bypass internal jitter clock" : + "Use internal jitter clock"); + + if ((val & RNG_RBG2X) != 0) + sbuf_cat(sbp, " RNG_RBG2X: RNG 2X SPEED enabled\n"); + + if ((val & RNG_RBGEN_BIT) != 0) + sbuf_cat(sbp, " RNG_RBGEN_BIT: RBG enabled\n"); + + /* Display RNG status register contents */ + val = bcm2835_rng_read4(sc, RNG_STATUS); + sbuf_printf(sbp, "RNG_CTRL (%08x)\n", val); + sbuf_printf(sbp, " RND_VAL: %02x\n", + (val >> RND_VAL_SHIFT) & RND_VAL_MASK); + sbuf_printf(sbp, " RND_WARM_CNT: %05x\n", val & RND_WARM_CNT); + + /* Display FIFO threshold register contents */ + val = bcm2835_rng_read4(sc, RNG_FF_THRES); + sbuf_printf(sbp, "RNG_FF_THRES: %05x\n", val & RNG_FF_THRES_MASK); + + /* Display interrupt mask register contents */ + val = bcm2835_rng_read4(sc, RNG_INT_MASK); + sbuf_printf(sbp, "RNG_INT_MASK: interrupt %s\n", + ((val & RNG_INT_OFF_BIT) != 0) ? "disabled" : "enabled"); +} + +static void +bcm2835_rng_disable_intr(struct bcm2835_rng_softc *sc) +{ + uint32_t mask; + + /* Set the interrupt off bit in the interrupt mask register */ + mask = bcm2835_rng_read4(sc, RNG_INT_MASK); + mask |= RNG_INT_OFF_BIT; + bcm2835_rng_write4(sc, RNG_INT_MASK, mask); +} + +#if defined(BCM2835_RNG_USE_INTERRUPT) +static void +bcm2835_rng_enable_intr(struct bcm2835_rng_softc *sc) +{ + uint32_t mask; + + /* Clear the interrupt off bit in the interrupt mask register */ + mask = bcm2835_rng_read4(sc, RNG_INT_MASK); + mask &= ~RNG_INT_OFF_BIT; + bcm2835_rng_write4(sc, RNG_INT_MASK, mask); +} +#endif + +static void +bcm2835_rng_start(struct bcm2835_rng_softc *sc) +{ + uint32_t ctrl; + + /* Disable the interrupt */ + bcm2835_rng_disable_intr(sc); + + /* Set the warmup count */ + bcm2835_rng_write4(sc, RNG_STATUS, RND_VAL_WARM_CNT); + + /* Enable the RNG */ + ctrl = bcm2835_rng_read4(sc, RNG_CTRL); + ctrl |= RNG_RBGEN_BIT; + if (sc->sc_rbg2x) + ctrl |= RNG_RBG2X; + bcm2835_rng_write4(sc, RNG_CTRL, ctrl); + +#if defined(BCM2835_RNG_USE_INTERRUPT) + /* Enable the interrupt */ + bcm2835_rng_enable_intr(sc); +#endif +} + +static void +bcm2835_rng_stop(struct bcm2835_rng_softc *sc) +{ + uint32_t ctrl; + + /* Disable the RNG */ + ctrl = bcm2835_rng_read4(sc, RNG_CTRL); + ctrl &= ~RNG_RBGEN_BIT; + bcm2835_rng_write4(sc, RNG_CTRL, ctrl); +} + +static void +bcm2835_rng_harvest(struct bcm2835_rng_softc *sc) +{ + uint32_t *dest; + uint32_t status; + u_int cnt, nread, num_avail, num_words; + int seen_underrun, num_stalls; + + dest = sc->sc_buf; + nread = num_words = 0; + seen_underrun = num_stalls = 0; + for (cnt = sizeof(sc->sc_buf) / sizeof(uint32_t); cnt > 0; + cnt -= num_words) { + /* Read status register to find out how many words available */ + status = bcm2835_rng_read4(sc, RNG_STATUS); + num_avail = (status >> RND_VAL_SHIFT) & RND_VAL_MASK; + + /* If we have none... */ + if (num_avail == 0) { + bcm2835_rng_stat_inc_underrun(sc); + if (++seen_underrun >= sc->sc_stall_count) { + if (num_stalls++ > 0) { + device_printf(sc->sc_dev, + "RNG stalled, disabling device\n"); + bcm2835_rng_stop(sc); + break; + } else { + device_printf(sc->sc_dev, + "Too many underruns, resetting\n"); + bcm2835_rng_stop(sc); + bcm2835_rng_start(sc); + seen_underrun = 0; + } + } + /* Try again */ + continue; + } + + CTR2(KTR_DEV, "%s: %d words available in RNG FIFO", + device_get_nameunit(sc->sc_dev), num_avail); + + /* Pull MIN(num_avail, cnt) words from the FIFO */ + num_words = (num_avail > cnt) ? cnt : num_avail; + bcm2835_rng_read_multi4(sc, RNG_DATA, dest, + num_words); + dest += num_words; + nread += num_words; + } + + cnt = nread * sizeof(uint32_t); + if (cnt > 0) + random_harvest_queue(sc->sc_buf, cnt, cnt * NBBY / 2, + RANDOM_PURE_BROADCOM); + +#if defined(BCM2835_RNG_USE_CALLOUT) + callout_reset(&sc->sc_rngto, sc->sc_rnghz, bcm2835_rng_harvest, sc); +#endif +} + +static int +sysctl_bcm2835_rng_2xspeed(SYSCTL_HANDLER_ARGS) +{ + struct bcm2835_rng_softc *sc = arg1; + int error, rbg2x; + + rbg2x = sc->sc_rbg2x; + error = sysctl_handle_int(oidp, &rbg2x, 0, req); + if (error) + return (error); + if (req->newptr == NULL) + return (error); + if (rbg2x == sc->sc_rbg2x) + return (0); + + /* Reset the RNG */ + bcm2835_rng_stop(sc); + sc->sc_rbg2x = rbg2x; + bcm2835_rng_start(sc); + + return (0); +} + +#ifdef BCM2835_RNG_DEBUG_REGISTERS +static int +sysctl_bcm2835_rng_dump(SYSCTL_HANDLER_ARGS) +{ + struct sbuf sb; + struct bcm2835_rng_softc *sc = arg1; + int error; + + error = sysctl_wire_old_buffer(req, 0); + if (error != 0) + return (error); + sbuf_new_for_sysctl(&sb, NULL, 128, req); + bcm2835_rng_dump_registers(sc, &sb); + error = sbuf_finish(&sb); + sbuf_delete(&sb); + return (error); +} +#endif + +static int +bcm2835_rng_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-rng")) + return (ENXIO); + + device_set_desc(dev, "Broadcom BCM2835 RNG"); + + return (BUS_PROBE_DEFAULT); +} + +static int +bcm2835_rng_attach(device_t dev) +{ + struct bcm2835_rng_softc *sc; + struct sysctl_ctx_list *sysctl_ctx; + struct sysctl_oid *sysctl_tree; + int error, rid; + + error = 0; + sc = device_get_softc(dev); + sc->sc_dev = dev; + sc->sc_stall_count = RNG_STALL_COUNT_DEFAULT; +#ifdef BCM2835_RNG_USE_CALLOUT + /* Initialize callout */ + callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); +#endif + TUNABLE_INT_FETCH("bcmrng.2xspeed", &sc->sc_rbg2x); + TUNABLE_INT_FETCH("bcmrng.stall_count", &sc->sc_stall_count); + + /* Allocate memory resources */ + rid = 0; + sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (sc->sc_mem_res == NULL) { + bcm2835_rng_detach(dev); + return (ENXIO); + } + +#if defined(BCM2835_RNG_USE_INTERRUPT) + /* Allocate interrupt resource */ + rid = 0; + sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_SHAREABLE | RF_ACTIVE); + if (sc->sc_irq_res == NULL) { + bcm2835_rng_detach(dev); + return (ENXIO); + } + + /* Set up the interrupt handler */ + error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, + NULL, (driver_intr_t *)bcm2835_rng_harvest, sc, &sc->sc_intr_hdl); + if (error) { + device_printf(dev, "Failed to set up IRQ\n"); + sc->sc_intr_hdl = NULL; + bcm2835_rng_detach(dev); + return (error); + } +#endif + + /* Start the RNG */ + bcm2835_rng_start(sc); + + /* Dump the registers if booting verbose */ + if (bootverbose) { + struct sbuf sb; + + (void) sbuf_new(&sb, NULL, 256, + SBUF_AUTOEXTEND | SBUF_INCLUDENUL); + bcm2835_rng_dump_registers(sc, &sb); + sbuf_trim(&sb); + error = sbuf_finish(&sb); + if (error == 0) + device_printf(dev, "%s", sbuf_data(&sb)); + sbuf_delete(&sb); + } + + sysctl_ctx = device_get_sysctl_ctx(dev); + sysctl_tree = device_get_sysctl_tree(dev); + SYSCTL_ADD_LONG(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO, + "underrun", CTLFLAG_RD, &sc->sc_underrun, + "Number of FIFO underruns"); + SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO, + "2xspeed", CTLTYPE_INT | CTLFLAG_RW, sc, 0, + sysctl_bcm2835_rng_2xspeed, "I", "Enable RBG 2X SPEED"); + SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO, + "stall_count", CTLFLAG_RW, &sc->sc_stall_count, + RNG_STALL_COUNT_DEFAULT, "Number of underruns to assume RNG stall"); +#ifdef BCM2835_RNG_DEBUG_REGISTERS + SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO, + "dumpregs", CTLTYPE_STRING | CTLFLAG_RD, sc, 0, + sysctl_bcm2835_rng_dump, "S", "Dump RNG registers"); +#endif + +#if defined(BCM2835_RNG_USE_CALLOUT) + /* Reset callout */ + if (hz >= 100) + sc->sc_rnghz = hz / 100; + else + sc->sc_rnghz = 1; + callout_reset(&sc->sc_rngto, sc->sc_rnghz, bcm2835_rng_harvest, sc); +#endif + + return (0); +} + +static int +bcm2835_rng_detach(device_t dev) +{ + struct bcm2835_rng_softc *sc; +#if defined(BCM2835_RNG_USE_INTERRUPT) + int error; +#endif + + sc = device_get_softc(dev); + + /* Stop the RNG */ + bcm2835_rng_stop(sc); + + /* Drain the callout it */ +#if defined(BCM2835_RNG_USE_CALLOUT) + callout_drain(&sc->sc_rngto); +#endif + +#if defined(BCM2835_RNG_USE_INTERRUPT) + /* Tear down the interrupt */ + if (sc->sc_irq_res && sc->sc_intr_hdl) { + error = bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intr_hdl); + if (error != 0) { + device_printf(dev, "could not tear down IRQ\n"); + return (error); + } + sc->sc_intr_hdl = NULL; + } + + /* Release interrupt resource */ + if (sc->sc_irq_res) { + bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); + sc->sc_irq_res = NULL; + } +#endif + + /* Release memory resource */ + if (sc->sc_mem_res != NULL) + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); + + return (0); +} + +static device_method_t bcm2835_rng_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, bcm2835_rng_probe), + DEVMETHOD(device_attach, bcm2835_rng_attach), + DEVMETHOD(device_detach, bcm2835_rng_detach), + + DEVMETHOD_END +}; + +static driver_t bcm2835_rng_driver = { + "bcmrng", + bcm2835_rng_methods, + sizeof(struct bcm2835_rng_softc) +}; +static devclass_t bcm2835_rng_devclass; + +DRIVER_MODULE(bcm2835_rng, simplebus, bcm2835_rng_driver, + bcm2835_rng_devclass, 0, 0); +DRIVER_MODULE(bcm2835_rng, ofwbus, bcm2835_rng_driver, bcm2835_rng_devclass, 0, + 0); +MODULE_VERSION(bcm2835_rng, 1); +MODULE_DEPEND(bcm2835_rng, randomdev, 1, 1, 1); Property changes on: head/sys/arm/broadcom/bcm2835/bcm2835_rng.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/broadcom/bcm2835/files.bcm283x =================================================================== --- head/sys/arm/broadcom/bcm2835/files.bcm283x (revision 303034) +++ head/sys/arm/broadcom/bcm2835/files.bcm283x (revision 303035) @@ -1,44 +1,45 @@ # $FreeBSD$ arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc arm/broadcom/bcm2835/bcm2835_common.c optional fdt arm/broadcom/bcm2835/bcm2835_cpufreq.c standard arm/broadcom/bcm2835/bcm2835_dma.c standard arm/broadcom/bcm2835/bcm2835_fb.c optional sc arm/broadcom/bcm2835/bcm2835_fbd.c optional vt arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio arm/broadcom/bcm2835/bcm2835_intr.c standard arm/broadcom/bcm2835/bcm2835_machdep.c standard arm/broadcom/bcm2835/bcm2835_mbox.c standard +arm/broadcom/bcm2835/bcm2835_rng.c optional random arm/broadcom/bcm2835/bcm2835_sdhci.c optional sdhci arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi arm/broadcom/bcm2835/bcm2835_vcio.c standard arm/broadcom/bcm2835/bcm2835_wdog.c standard arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt kern/kern_clocksource.c standard dev/mbox/mbox_if.m standard arm/broadcom/bcm2835/bcm2835_audio.c optional sound vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" # VideoCore driver contrib/vchiq/interface/compat/vchi_bsd.c optional vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c optional vchiq \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_arm.c optional vchiq \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_connected.c optional vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_core.c optional vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c optional vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c optional vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_shim.c optional vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_util.c optional vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" Index: head/sys/boot/fdt/dts/arm/bcm2835.dtsi =================================================================== --- head/sys/boot/fdt/dts/arm/bcm2835.dtsi (revision 303034) +++ head/sys/boot/fdt/dts/arm/bcm2835.dtsi (revision 303035) @@ -1,497 +1,505 @@ /* * Copyright (c) 2012 Oleksandr Tymoshenko * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ / { #address-cells = <1>; #size-cells = <1>; cpus { cpu@0 { compatible = "arm,1176jzf-s"; }; }; SOC: axi { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x20000000 0x01000000>; ranges = <0 0x20000000 0x01000000>; intc: interrupt-controller { compatible = "broadcom,bcm2835-armctrl-ic", "broadcom,bcm2708-armctrl-ic"; reg = <0xB200 0x200>; interrupt-controller; #interrupt-cells = <1>; /* Bank 0 * 0: ARM_TIMER * 1: ARM_MAILBOX * 2: ARM_DOORBELL_0 * 3: ARM_DOORBELL_1 * 4: VPU0_HALTED * 5: VPU1_HALTED * 6: ILLEGAL_TYPE0 * 7: ILLEGAL_TYPE1 */ /* Bank 1 * 0: TIMER0 16: DMA0 * 1: TIMER1 17: DMA1 * 2: TIMER2 18: VC_DMA2 * 3: TIMER3 19: VC_DMA3 * 4: CODEC0 20: DMA4 * 5: CODEC1 21: DMA5 * 6: CODEC2 22: DMA6 * 7: VC_JPEG 23: DMA7 * 8: ISP 24: DMA8 * 9: VC_USB 25: DMA9 * 10: VC_3D 26: DMA10 * 11: TRANSPOSER 27: DMA11 * 12: MULTICORESYNC0 28: DMA12 * 13: MULTICORESYNC1 29: AUX * 14: MULTICORESYNC2 30: ARM * 15: MULTICORESYNC3 31: VPUDMA */ /* Bank 2 * 0: HOSTPORT 16: SMI * 1: VIDEOSCALER 17: GPIO0 * 2: CCP2TX 18: GPIO1 * 3: SDC 19: GPIO2 * 4: DSI0 20: GPIO3 * 5: AVE 21: VC_I2C * 6: CAM0 22: VC_SPI * 7: CAM1 23: VC_I2SPCM * 8: HDMI0 24: VC_SDIO * 9: HDMI1 25: VC_UART * 10: PIXELVALVE1 26: SLIMBUS * 11: I2CSPISLV 27: VEC * 12: DSI1 28: CPG * 13: PWA0 29: RNG * 14: PWA1 30: VC_ARASANSDIO * 15: CPR 31: AVSPMON */ }; timer { compatible = "broadcom,bcm2835-system-timer", "broadcom,bcm2708-system-timer"; reg = <0x3000 0x1000>; interrupts = <8 9 10 11>; interrupt-parent = <&intc>; clock-frequency = <1000000>; }; armtimer { /* Not AMBA compatible */ compatible = "broadcom,bcm2835-sp804", "arm,sp804"; reg = <0xB400 0x24>; interrupts = <0>; interrupt-parent = <&intc>; }; watchdog0 { compatible = "broadcom,bcm2835-wdt", "broadcom,bcm2708-wdt"; reg = <0x10001c 0x0c>; /* 0x1c, 0x20, 0x24 */ }; gpio: gpio { compatible = "broadcom,bcm2835-gpio", "broadcom,bcm2708-gpio"; reg = <0x200000 0xb0>; /* Unusual arrangement of interrupts * (determined by testing) * 17: Bank 0 (GPIOs 0-31) * 19: Bank 1 (GPIOs 32-53) * 18: Bank 2 * 20: All banks (GPIOs 0-53) */ interrupts = <57 59 58 60>; interrupt-parent = <&intc>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pins_reserved>; /* Pins that can short 3.3V to GND in output mode: 46-47 * Pins used by VideoCore: 48-53 */ broadcom,read-only = <46>, <47>, <48>, <49>, <50>, <51>, <52>, <53>; /* BSC0 */ pins_bsc0_a: bsc0_a { broadcom,pins = <0>, <1>; }; pins_bsc0_b: bsc0_b { broadcom,pins = <28>, <29>; }; pins_bsc0_c: bsc0_c { broadcom,pins = <44>, <45>; }; /* BSC1 */ pins_bsc1_a: bsc1_a { broadcom,pins = <2>, <3>; }; pins_bsc1_b: bsc1_b { broadcom,pins = <44>, <45>; }; /* GPCLK0 */ pins_gpclk0_a: gpclk0_a { broadcom,pins = <4>; }; pins_gpclk0_b: gpclk0_b { broadcom,pins = <20>; }; pins_gpclk0_c: gpclk0_c { broadcom,pins = <32>; }; pins_gpclk0_d: gpclk0_d { broadcom,pins = <34>; }; /* GPCLK1 */ pins_gpclk1_a: gpclk1_a { broadcom,pins = <5>; }; pins_gpclk1_b: gpclk1_b { broadcom,pins = <21>; }; pins_gpclk1_c: gpclk1_c { broadcom,pins = <42>; }; pins_gpclk1_d: gpclk1_d { broadcom,pins = <44>; }; /* GPCLK2 */ pins_gpclk2_a: gpclk2_a { broadcom,pins = <6>; }; pins_gpclk2_b: gpclk2_b { broadcom,pins = <43>; }; /* SPI0 */ pins_spi0_a: spi0_a { broadcom,pins = <7>, <8>, <9>, <10>, <11>; }; pins_spi0_b: spi0_b { broadcom,pins = <35>, <36>, <37>, <38>, <39>; }; /* PWM */ pins_pwm0_a: pwm0_a { broadcom,pins = <12>; }; pins_pwm0_b: pwm0_b { broadcom,pins = <18>; }; pins_pwm0_c: pwm0_c { broadcom,pins = <40>; }; pins_pwm1_a: pwm1_a { broadcom,pins = <13>; }; pins_pwm1_b: pwm1_b { broadcom,pins = <19>; }; pins_pwm1_c: pwm1_c { broadcom,pins = <41>; }; pins_pwm1_d: pwm1_d { broadcom,pins = <45>; }; /* UART0 */ pins_uart0_a: uart0_a { broadcom,pins = <14>, <15>; }; pins_uart0_b: uart0_b { broadcom,pins = <32>, <33>; }; pins_uart0_c: uart0_c { broadcom,pins = <36>, <37>; }; pins_uart0_fc_a: uart0_fc_a { broadcom,pins = <16>, <17>; }; pins_uart0_fc_b: uart0_fc_b { broadcom,pins = <30>, <31>; }; pins_uart0_fc_c: uart0_fc_c { broadcom,pins = <39>, <38>; }; /* PCM */ pins_pcm_a: pcm_a { broadcom,pins = <18>, <19>, <20>, <21>; }; pins_pcm_b: pcm_b { broadcom,pins = <28>, <29>, <30>, <31>; }; /* Secondary Address Bus */ pins_sm_addr_a: sm_addr_a { broadcom,pins = <5>, <4>, <3>, <2>, <1>, <0>; }; pins_sm_addr_b: sm_addr_b { broadcom,pins = <33>, <32>, <31>, <30>, <29>, <28>; }; pins_sm_ctl_a: sm_ctl_a { broadcom,pins = <6>, <7>; }; pins_sm_ctl_b: sm_ctl_b { broadcom,pins = <34>, <35>; }; pins_sm_data_8bit_a: sm_data_8bit_a { broadcom,pins = <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>; }; pins_sm_data_8bit_b: sm_data_8bit_b { broadcom,pins = <36>, <37>, <38>, <39>, <40>, <41>, <42>, <43>; }; pins_sm_data_16bit: sm_data_16bit { broadcom,pins = <16>, <17>, <18>, <19>, <20>, <21>, <22>, <23>; }; pins_sm_data_18bit: sm_data_18bit { broadcom,pins = <24>, <25>; }; /* BSCSL */ pins_bscsl: bscsl { broadcom,pins = <18>, <19>; }; /* SPISL */ pins_spisl: spisl { broadcom,pins = <18>, <19>, <20>, <21>; }; /* SPI1 */ pins_spi1: spi1 { broadcom,pins = <16>, <17>, <18>, <19>, <20>, <21>; }; /* UART1 */ pins_uart1_a: uart1_a { broadcom,pins = <14>, <15>; }; pins_uart1_b: uart1_b { broadcom,pins = <32>, <33>; }; pins_uart1_c: uart1_c { broadcom,pins = <40>, <41>; }; pins_uart1_fc_a: uart1_fc_a { broadcom,pins = <16>, <17>; }; pins_uart1_fc_b: uart1_fc_b { broadcom,pins = <30>, <31>; }; pins_uart1_fc_c: uart1_fc_c { broadcom,pins = <43>, <42>; }; /* SPI2 */ pins_spi2: spi2 { broadcom,pins = <40>, <41>, <42>, <43>, <44>, <45>; }; /* ARM JTAG */ pins_arm_jtag_trst: arm_jtag_trst { broadcom,pins = <22>; }; pins_arm_jtag_a: arm_jtag_a { broadcom,pins = <4>, <5>, <6>, <12>, <13>; }; pins_arm_jtag_b: arm_jtag_b { broadcom,pins = <23>, <24>, <25>, <26>, <27>; }; /* Reserved */ pins_reserved: reserved { broadcom,pins = <48>, <49>, <50>, <51>, <52>, <53>; }; }; + rng { + compatible = "broadcom,bcm2835-rng", + "broadcom,bcm2708-rng"; + reg = <0x104000 0x20>; + interrupts = <69>; + interrupt-parent = <&intc>; + }; + bsc0 { #address-cells = <1>; #size-cells = <0>; compatible = "broadcom,bcm2835-bsc", "broadcom,bcm2708-bsc"; reg = <0x205000 0x20>; interrupts = <61>; interrupt-parent = <&intc>; }; bsc1 { #address-cells = <1>; #size-cells = <0>; compatible = "broadcom,bcm2835-bsc", "broadcom,bcm2708-bsc"; reg = <0x804000 0x20>; interrupts = <61>; interrupt-parent = <&intc>; }; spi0 { compatible = "broadcom,bcm2835-spi", "broadcom,bcm2708-spi"; reg = <0x204000 0x20>; interrupts = <62>; interrupt-parent = <&intc>; }; dma: dma { compatible = "broadcom,bcm2835-dma", "broadcom,bcm2708-dma"; reg = <0x7000 0x1000>, <0xE05000 0x1000>; interrupts = <24 25 26 27 28 29 30 31 32 33 34 35 36>; interrupt-parent = <&intc>; broadcom,channels = <0>; /* Set by VideoCore */ }; vc_mbox: mbox { compatible = "broadcom,bcm2835-mbox", "broadcom,bcm2708-mbox"; reg = <0xB880 0x40>; interrupts = <1>; interrupt-parent = <&intc>; /* Channels * 0: Power * 1: Frame buffer * 2: Virtual UART * 3: VCHIQ * 4: LEDs * 5: Buttons * 6: Touch screen */ }; sdhci { compatible = "broadcom,bcm2835-sdhci", "broadcom,bcm2708-sdhci"; reg = <0x300000 0x100>; interrupts = <70>; interrupt-parent = <&intc>; clock-frequency = <50000000>; /* Set by VideoCore */ }; uart0: uart0 { compatible = "broadcom,bcm2835-uart", "broadcom,bcm2708-uart", "arm,pl011", "arm,primecell"; reg = <0x201000 0x1000>; interrupts = <65>; interrupt-parent = <&intc>; clock-frequency = <3000000>; /* Set by VideoCore */ reg-shift = <2>; }; vchiq: vchiq { compatible = "broadcom,bcm2835-vchiq"; reg = <0xB800 0x50>; interrupts = <2>; interrupt-parent = <&intc>; cache-line-size = <32>; }; usb { compatible = "broadcom,bcm2835-usb", "broadcom,bcm2708-usb", "synopsys,designware-hs-otg2"; reg = <0x980000 0x20000>; interrupts = <17>; interrupt-parent = <&intc>; #address-cells = <1>; #size-cells = <0>; }; }; }; Index: head/sys/boot/fdt/dts/arm/bcm2836.dtsi =================================================================== --- head/sys/boot/fdt/dts/arm/bcm2836.dtsi (revision 303034) +++ head/sys/boot/fdt/dts/arm/bcm2836.dtsi (revision 303035) @@ -1,490 +1,498 @@ /* * Copyright (c) 2012 Oleksandr Tymoshenko * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ / { #address-cells = <1>; #size-cells = <1>; timer { compatible = "arm,armv7-timer"; clock-frequency = <19200000>; interrupts = <0 1 3 2>; interrupt-parent = <&local_intc>; }; SOC: axi { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x3f000000 0x01000000>; ranges = <0 0x3f000000 0x01000000>, <0x40000000 0x40000000 0x00001000>; local_intc: local_intc { compatible = "brcm,bcm2836-l1-intc"; reg = <0x40000000 0x100>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&local_intc>; }; intc: interrupt-controller { compatible = "broadcom,bcm2835-armctrl-ic", "broadcom,bcm2708-armctrl-ic"; reg = <0xB200 0x200>; interrupt-parent = <&local_intc>; interrupts = <8>; interrupt-controller; #interrupt-cells = <1>; /* Bank 0 * 0: ARM_TIMER * 1: ARM_MAILBOX * 2: ARM_DOORBELL_0 * 3: ARM_DOORBELL_1 * 4: VPU0_HALTED * 5: VPU1_HALTED * 6: ILLEGAL_TYPE0 * 7: ILLEGAL_TYPE1 */ /* Bank 1 * 0: TIMER0 16: DMA0 * 1: TIMER1 17: DMA1 * 2: TIMER2 18: VC_DMA2 * 3: TIMER3 19: VC_DMA3 * 4: CODEC0 20: DMA4 * 5: CODEC1 21: DMA5 * 6: CODEC2 22: DMA6 * 7: VC_JPEG 23: DMA7 * 8: ISP 24: DMA8 * 9: VC_USB 25: DMA9 * 10: VC_3D 26: DMA10 * 11: TRANSPOSER 27: DMA11 * 12: MULTICORESYNC0 28: DMA12 * 13: MULTICORESYNC1 29: AUX * 14: MULTICORESYNC2 30: ARM * 15: MULTICORESYNC3 31: VPUDMA */ /* Bank 2 * 0: HOSTPORT 16: SMI * 1: VIDEOSCALER 17: GPIO0 * 2: CCP2TX 18: GPIO1 * 3: SDC 19: GPIO2 * 4: DSI0 20: GPIO3 * 5: AVE 21: VC_I2C * 6: CAM0 22: VC_SPI * 7: CAM1 23: VC_I2SPCM * 8: HDMI0 24: VC_SDIO * 9: HDMI1 25: VC_UART * 10: PIXELVALVE1 26: SLIMBUS * 11: I2CSPISLV 27: VEC * 12: DSI1 28: CPG * 13: PWA0 29: RNG * 14: PWA1 30: VC_ARASANSDIO * 15: CPR 31: AVSPMON */ }; watchdog0 { compatible = "broadcom,bcm2835-wdt", "broadcom,bcm2708-wdt"; reg = <0x10001c 0x0c>; /* 0x1c, 0x20, 0x24 */ }; gpio: gpio { compatible = "broadcom,bcm2835-gpio", "broadcom,bcm2708-gpio"; reg = <0x200000 0xb0>; /* Unusual arrangement of interrupts * (determined by testing) * 17: Bank 0 (GPIOs 0-31) * 19: Bank 1 (GPIOs 32-53) * 18: Bank 2 * 20: All banks (GPIOs 0-53) */ interrupts = <57 59 58 60>; interrupt-parent = <&intc>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pins_reserved>; /* Pins that can short 3.3V to GND in output mode: 46 * Pins used by VideoCore: 48-53 */ broadcom,read-only = <46>, <48>, <49>, <50>, <51>, <52>, <53>; /* BSC0 */ pins_bsc0_a: bsc0_a { broadcom,pins = <0>, <1>; }; pins_bsc0_b: bsc0_b { broadcom,pins = <28>, <29>; }; pins_bsc0_c: bsc0_c { broadcom,pins = <44>, <45>; }; /* BSC1 */ pins_bsc1_a: bsc1_a { broadcom,pins = <2>, <3>; }; pins_bsc1_b: bsc1_b { broadcom,pins = <44>, <45>; }; /* GPCLK0 */ pins_gpclk0_a: gpclk0_a { broadcom,pins = <4>; }; pins_gpclk0_b: gpclk0_b { broadcom,pins = <20>; }; pins_gpclk0_c: gpclk0_c { broadcom,pins = <32>; }; pins_gpclk0_d: gpclk0_d { broadcom,pins = <34>; }; /* GPCLK1 */ pins_gpclk1_a: gpclk1_a { broadcom,pins = <5>; }; pins_gpclk1_b: gpclk1_b { broadcom,pins = <21>; }; pins_gpclk1_c: gpclk1_c { broadcom,pins = <42>; }; pins_gpclk1_d: gpclk1_d { broadcom,pins = <44>; }; /* GPCLK2 */ pins_gpclk2_a: gpclk2_a { broadcom,pins = <6>; }; pins_gpclk2_b: gpclk2_b { broadcom,pins = <43>; }; /* SPI0 */ pins_spi0_a: spi0_a { broadcom,pins = <7>, <8>, <9>, <10>, <11>; }; pins_spi0_b: spi0_b { broadcom,pins = <35>, <36>, <37>, <38>, <39>; }; /* PWM */ pins_pwm0_a: pwm0_a { broadcom,pins = <12>; }; pins_pwm0_b: pwm0_b { broadcom,pins = <18>; }; pins_pwm0_c: pwm0_c { broadcom,pins = <40>; }; pins_pwm1_a: pwm1_a { broadcom,pins = <13>; }; pins_pwm1_b: pwm1_b { broadcom,pins = <19>; }; pins_pwm1_c: pwm1_c { broadcom,pins = <41>; }; pins_pwm1_d: pwm1_d { broadcom,pins = <45>; }; /* UART0 */ pins_uart0_a: uart0_a { broadcom,pins = <14>, <15>; }; pins_uart0_b: uart0_b { broadcom,pins = <32>, <33>; }; pins_uart0_c: uart0_c { broadcom,pins = <36>, <37>; }; pins_uart0_fc_a: uart0_fc_a { broadcom,pins = <16>, <17>; }; pins_uart0_fc_b: uart0_fc_b { broadcom,pins = <30>, <31>; }; pins_uart0_fc_c: uart0_fc_c { broadcom,pins = <39>, <38>; }; /* PCM */ pins_pcm_a: pcm_a { broadcom,pins = <18>, <19>, <20>, <21>; }; pins_pcm_b: pcm_b { broadcom,pins = <28>, <29>, <30>, <31>; }; /* Secondary Address Bus */ pins_sm_addr_a: sm_addr_a { broadcom,pins = <5>, <4>, <3>, <2>, <1>, <0>; }; pins_sm_addr_b: sm_addr_b { broadcom,pins = <33>, <32>, <31>, <30>, <29>, <28>; }; pins_sm_ctl_a: sm_ctl_a { broadcom,pins = <6>, <7>; }; pins_sm_ctl_b: sm_ctl_b { broadcom,pins = <34>, <35>; }; pins_sm_data_8bit_a: sm_data_8bit_a { broadcom,pins = <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>; }; pins_sm_data_8bit_b: sm_data_8bit_b { broadcom,pins = <36>, <37>, <38>, <39>, <40>, <41>, <42>, <43>; }; pins_sm_data_16bit: sm_data_16bit { broadcom,pins = <16>, <17>, <18>, <19>, <20>, <21>, <22>, <23>; }; pins_sm_data_18bit: sm_data_18bit { broadcom,pins = <24>, <25>; }; /* BSCSL */ pins_bscsl: bscsl { broadcom,pins = <18>, <19>; }; /* SPISL */ pins_spisl: spisl { broadcom,pins = <18>, <19>, <20>, <21>; }; /* SPI1 */ pins_spi1: spi1 { broadcom,pins = <16>, <17>, <18>, <19>, <20>, <21>; }; /* UART1 */ pins_uart1_a: uart1_a { broadcom,pins = <14>, <15>; }; pins_uart1_b: uart1_b { broadcom,pins = <32>, <33>; }; pins_uart1_c: uart1_c { broadcom,pins = <40>, <41>; }; pins_uart1_fc_a: uart1_fc_a { broadcom,pins = <16>, <17>; }; pins_uart1_fc_b: uart1_fc_b { broadcom,pins = <30>, <31>; }; pins_uart1_fc_c: uart1_fc_c { broadcom,pins = <43>, <42>; }; /* SPI2 */ pins_spi2: spi2 { broadcom,pins = <40>, <41>, <42>, <43>, <44>, <45>; }; /* ARM JTAG */ pins_arm_jtag_trst: arm_jtag_trst { broadcom,pins = <22>; }; pins_arm_jtag_a: arm_jtag_a { broadcom,pins = <4>, <5>, <6>, <12>, <13>; }; pins_arm_jtag_b: arm_jtag_b { broadcom,pins = <23>, <24>, <25>, <26>, <27>; }; /* Reserved */ pins_reserved: reserved { broadcom,pins = <48>, <49>, <50>, <51>, <52>, <53>; }; }; + rng { + compatible = "broadcom,bcm2835-rng", + "broadcom,bcm2708-rng"; + reg = <0x104000 0x20>; + interrupts = <69>; + interrupt-parent = <&intc>; + }; + bsc0 { #address-cells = <1>; #size-cells = <0>; compatible = "broadcom,bcm2835-bsc", "broadcom,bcm2708-bsc"; reg = <0x205000 0x20>; interrupts = <61>; interrupt-parent = <&intc>; }; bsc1 { #address-cells = <1>; #size-cells = <0>; compatible = "broadcom,bcm2835-bsc", "broadcom,bcm2708-bsc"; reg = <0x804000 0x20>; interrupts = <61>; interrupt-parent = <&intc>; }; spi0 { compatible = "broadcom,bcm2835-spi", "broadcom,bcm2708-spi"; reg = <0x204000 0x20>; interrupts = <62>; interrupt-parent = <&intc>; }; dma: dma { compatible = "broadcom,bcm2835-dma", "broadcom,bcm2708-dma"; reg = <0x7000 0x1000>, <0xE05000 0x1000>; interrupts = <24 25 26 27 28 29 30 31 32 33 34 35 36>; interrupt-parent = <&intc>; broadcom,channels = <0>; /* Set by VideoCore */ }; vc_mbox: mbox { compatible = "broadcom,bcm2835-mbox", "broadcom,bcm2708-mbox"; reg = <0xB880 0x40>; interrupts = <1>; interrupt-parent = <&intc>; /* Channels * 0: Power * 1: Frame buffer * 2: Virtual UART * 3: VCHIQ * 4: LEDs * 5: Buttons * 6: Touch screen */ }; sdhci { compatible = "broadcom,bcm2835-sdhci", "broadcom,bcm2708-sdhci"; reg = <0x300000 0x100>; interrupts = <70>; interrupt-parent = <&intc>; clock-frequency = <250000000>; /* Set by VideoCore */ }; uart0: uart0 { compatible = "broadcom,bcm2835-uart", "broadcom,bcm2708-uart", "arm,pl011", "arm,primecell"; reg = <0x201000 0x1000>; interrupts = <65>; interrupt-parent = <&intc>; clock-frequency = <3000000>; /* Set by VideoCore */ reg-shift = <2>; }; vchiq: vchiq { compatible = "broadcom,bcm2835-vchiq"; reg = <0xB800 0x50>; interrupts = <2>; interrupt-parent = <&intc>; cache-line-size = <32>; }; usb { compatible = "broadcom,bcm2835-usb", "broadcom,bcm2708-usb", "synopsys,designware-hs-otg2"; reg = <0x980000 0x20000>; interrupts = <17>; interrupt-parent = <&intc>; #address-cells = <1>; #size-cells = <0>; }; }; }; Index: head/sys/sys/random.h =================================================================== --- head/sys/sys/random.h (revision 303034) +++ head/sys/sys/random.h (revision 303035) @@ -1,116 +1,117 @@ /*- * Copyright (c) 2000-2015 Mark R. V. Murray * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer * in this position and unchanged. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _SYS_RANDOM_H_ #define _SYS_RANDOM_H_ #ifdef _KERNEL #include #if !defined(KLD_MODULE) #if defined(RANDOM_LOADABLE) && defined(RANDOM_YARROW) #error "Cannot define both RANDOM_LOADABLE and RANDOM_YARROW" #endif #endif struct uio; #if defined(DEV_RANDOM) u_int read_random(void *, u_int); int read_random_uio(struct uio *, bool); #else static __inline int read_random_uio(void *a __unused, u_int b __unused) { return (0); } static __inline u_int read_random(void *a __unused, u_int b __unused) { return (0); } #endif /* * Note: if you add or remove members of random_entropy_source, remember to also update the * KASSERT regarding what valid members are in random_harvest_internal(), and remember the * strings in the static array random_source_descr[] in random_harvestq.c. * * NOTE: complain loudly to markm@ or on the lists if this enum gets more than 32 * distinct values (0-31)! ENTROPYSOURCE may be == 32, but not > 32. */ enum random_entropy_source { RANDOM_START = 0, RANDOM_CACHED = 0, /* Environmental sources */ RANDOM_ATTACH, RANDOM_KEYBOARD, RANDOM_MOUSE, RANDOM_NET_TUN, RANDOM_NET_ETHER, RANDOM_NET_NG, RANDOM_INTERRUPT, RANDOM_SWI, RANDOM_FS_ATIME, RANDOM_UMA, /* Special!! UMA/SLAB Allocator */ RANDOM_ENVIRONMENTAL_END = RANDOM_UMA, /* Fast hardware random-number sources from here on. */ RANDOM_PURE_OCTEON, RANDOM_PURE_SAFE, RANDOM_PURE_GLXSB, RANDOM_PURE_UBSEC, RANDOM_PURE_HIFN, RANDOM_PURE_RDRAND, RANDOM_PURE_NEHEMIAH, RANDOM_PURE_RNDTEST, RANDOM_PURE_VIRTIO, + RANDOM_PURE_BROADCOM, ENTROPYSOURCE }; #define RANDOM_HARVEST_EVERYTHING_MASK ((1 << (RANDOM_ENVIRONMENTAL_END + 1)) - 1) #if defined(DEV_RANDOM) void random_harvest_queue(const void *, u_int, u_int, enum random_entropy_source); void random_harvest_fast(const void *, u_int, u_int, enum random_entropy_source); void random_harvest_direct(const void *, u_int, u_int, enum random_entropy_source); #else #define random_harvest_queue(a, b, c, d) do {} while (0) #define random_harvest_fast(a, b, c, d) do {} while (0) #define random_harvest_direct(a, b, c, d) do {} while (0) #endif #if defined(RANDOM_ENABLE_UMA) #define random_harvest_fast_uma(a, b, c, d) random_harvest_fast(a, b, c, d) #else /* !defined(RANDOM_ENABLE_UMA) */ #define random_harvest_fast_uma(a, b, c, d) do {} while (0) #endif /* defined(RANDOM_ENABLE_UMA) */ #endif /* _KERNEL */ #endif /* _SYS_RANDOM_H_ */