Index: head/sys/mips/atheros/ar71xx_chip.c =================================================================== --- head/sys/mips/atheros/ar71xx_chip.c (revision 302189) +++ head/sys/mips/atheros/ar71xx_chip.c (revision 302190) @@ -1,339 +1,337 @@ /*- * Copyright (c) 2010 Adrian Chadd * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_ddb.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include -#include - /* XXX these should replace the current definitions in ar71xxreg.h */ /* XXX perhaps an ar71xx_chip.h header file? */ #define AR71XX_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00 #define AR71XX_PLL_REG_SEC_CONFIG AR71XX_PLL_CPU_BASE + 0x04 #define AR71XX_PLL_REG_ETH0_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x10 #define AR71XX_PLL_REG_ETH1_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x14 #define AR71XX_PLL_DIV_SHIFT 3 #define AR71XX_PLL_DIV_MASK 0x1f #define AR71XX_CPU_DIV_SHIFT 16 #define AR71XX_CPU_DIV_MASK 0x3 #define AR71XX_DDR_DIV_SHIFT 18 #define AR71XX_DDR_DIV_MASK 0x3 #define AR71XX_AHB_DIV_SHIFT 20 #define AR71XX_AHB_DIV_MASK 0x7 /* XXX these shouldn't be in here - this file is a per-chip file */ /* XXX these should be in the top-level ar71xx type, not ar71xx -chip */ uint32_t u_ar71xx_cpu_freq; uint32_t u_ar71xx_ahb_freq; uint32_t u_ar71xx_ddr_freq; uint32_t u_ar71xx_uart_freq; uint32_t u_ar71xx_wdt_freq; uint32_t u_ar71xx_refclk; uint32_t u_ar71xx_mdio_freq; static void ar71xx_chip_detect_mem_size(void) { } static void ar71xx_chip_detect_sys_frequency(void) { uint32_t pll; uint32_t freq; uint32_t div; u_ar71xx_mdio_freq = u_ar71xx_refclk = AR71XX_BASE_FREQ; pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG); div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; freq = div * AR71XX_BASE_FREQ; div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; u_ar71xx_cpu_freq = freq / div; div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; u_ar71xx_ddr_freq = freq / div; div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div; u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div; u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div; } /* * This does not lock the CPU whilst doing the work! */ static void ar71xx_chip_device_stop(uint32_t mask) { uint32_t reg; reg = ATH_READ_REG(AR71XX_RST_RESET); ATH_WRITE_REG(AR71XX_RST_RESET, reg | mask); } static void ar71xx_chip_device_start(uint32_t mask) { uint32_t reg; reg = ATH_READ_REG(AR71XX_RST_RESET); ATH_WRITE_REG(AR71XX_RST_RESET, reg & ~mask); } static int ar71xx_chip_device_stopped(uint32_t mask) { uint32_t reg; reg = ATH_READ_REG(AR71XX_RST_RESET); return ((reg & mask) == mask); } void ar71xx_chip_set_mii_speed(uint32_t unit, uint32_t speed) { uint32_t val, reg, ctrl; switch (unit) { case 0: reg = AR71XX_MII0_CTRL; break; case 1: reg = AR71XX_MII1_CTRL; break; default: printf("%s: invalid MII unit set for arge unit: %d\n", __func__, unit); return; } switch (speed) { case 10: ctrl = MII_CTRL_SPEED_10; break; case 100: ctrl = MII_CTRL_SPEED_100; break; case 1000: ctrl = MII_CTRL_SPEED_1000; break; default: printf("%s: invalid MII speed (%d) set for arge unit: %d\n", __func__, speed, unit); return; } val = ATH_READ_REG(reg); val &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT); val |= (ctrl & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT; ATH_WRITE_REG(reg, val); } void ar71xx_chip_set_mii_if(uint32_t unit, uint32_t mii_mode) { uint32_t val, reg, mii_if; switch (unit) { case 0: reg = AR71XX_MII0_CTRL; if (mii_mode == AR71XX_MII_MODE_GMII) mii_if = MII0_CTRL_IF_GMII; else if (mii_mode == AR71XX_MII_MODE_MII) mii_if = MII0_CTRL_IF_MII; else if (mii_mode == AR71XX_MII_MODE_RGMII) mii_if = MII0_CTRL_IF_RGMII; else if (mii_mode == AR71XX_MII_MODE_RMII) mii_if = MII0_CTRL_IF_RMII; else { printf("%s: invalid MII mode (%d) for unit %d\n", __func__, mii_mode, unit); return; } break; case 1: reg = AR71XX_MII1_CTRL; if (mii_mode == AR71XX_MII_MODE_RGMII) mii_if = MII1_CTRL_IF_RGMII; else if (mii_mode == AR71XX_MII_MODE_RMII) mii_if = MII1_CTRL_IF_RMII; else { printf("%s: invalid MII mode (%d) for unit %d\n", __func__, mii_mode, unit); return; } break; default: printf("%s: invalid MII unit set for arge unit: %d\n", __func__, unit); return; } val = ATH_READ_REG(reg); val &= ~(MII_CTRL_IF_MASK << MII_CTRL_IF_SHIFT); val |= (mii_if & MII_CTRL_IF_MASK) << MII_CTRL_IF_SHIFT; ATH_WRITE_REG(reg, val); } /* Speed is either 10, 100 or 1000 */ static void ar71xx_chip_set_pll_ge(int unit, int speed, uint32_t pll) { switch (unit) { case 0: ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, AR71XX_PLL_ETH_INT0_CLK, pll, AR71XX_PLL_ETH0_SHIFT); break; case 1: ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, AR71XX_PLL_ETH_INT1_CLK, pll, AR71XX_PLL_ETH1_SHIFT); break; default: printf("%s: invalid PLL set for arge unit: %d\n", __func__, unit); return; } } static void ar71xx_chip_ddr_flush(ar71xx_flush_ddr_id_t id) { switch (id) { case AR71XX_CPU_DDR_FLUSH_GE0: ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE0); break; case AR71XX_CPU_DDR_FLUSH_GE1: ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE1); break; case AR71XX_CPU_DDR_FLUSH_USB: ar71xx_ddr_flush(AR71XX_WB_FLUSH_USB); break; case AR71XX_CPU_DDR_FLUSH_PCIE: ar71xx_ddr_flush(AR71XX_WB_FLUSH_PCI); break; default: printf("%s: invalid DDR flush id (%d)\n", __func__, id); break; } } static uint32_t ar71xx_chip_get_eth_pll(unsigned int mac, int speed) { uint32_t pll; switch (speed) { case 10: pll = PLL_ETH_INT_CLK_10; break; case 100: pll = PLL_ETH_INT_CLK_100; break; case 1000: pll = PLL_ETH_INT_CLK_1000; break; default: printf("%s%d: invalid speed %d\n", __func__, mac, speed); pll = 0; } return (pll); } static void ar71xx_chip_init_usb_peripheral(void) { ar71xx_device_stop(RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST | RST_RESET_USB_PHY); DELAY(1000); ar71xx_device_start(RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST | RST_RESET_USB_PHY); DELAY(1000); ATH_WRITE_REG(AR71XX_USB_CTRL_CONFIG, USB_CTRL_CONFIG_OHCI_DES_SWAP | USB_CTRL_CONFIG_OHCI_BUF_SWAP | USB_CTRL_CONFIG_EHCI_DES_SWAP | USB_CTRL_CONFIG_EHCI_BUF_SWAP); ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ, (32 << USB_CTRL_FLADJ_HOST_SHIFT) | (3 << USB_CTRL_FLADJ_A5_SHIFT)); DELAY(1000); } struct ar71xx_cpu_def ar71xx_chip_def = { &ar71xx_chip_detect_mem_size, &ar71xx_chip_detect_sys_frequency, &ar71xx_chip_device_stop, &ar71xx_chip_device_start, &ar71xx_chip_device_stopped, &ar71xx_chip_set_pll_ge, &ar71xx_chip_set_mii_speed, &ar71xx_chip_set_mii_if, &ar71xx_chip_get_eth_pll, &ar71xx_chip_ddr_flush, &ar71xx_chip_init_usb_peripheral, }; Index: head/sys/mips/atheros/ar71xx_machdep.c =================================================================== --- head/sys/mips/atheros/ar71xx_machdep.c (revision 302189) +++ head/sys/mips/atheros/ar71xx_machdep.c (revision 302190) @@ -1,484 +1,482 @@ /*- * Copyright (c) 2009 Oleksandr Tymoshenko * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_ddb.h" #include "opt_ar71xx.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include -#include - extern char edata[], end[]; /* 4KB static data aread to keep a copy of the bootload env until the dynamic kenv is setup */ char boot1_env[4096]; /* * We get a string in from Redboot with the all the arguments together, * "foo=bar bar=baz". Split them up and save in kenv. */ static void parse_argv(char *str) { char *n, *v; while ((v = strsep(&str, " ")) != NULL) { if (*v == '\0') continue; if (*v == '-') { while (*v != '\0') { v++; switch (*v) { case 'a': boothowto |= RB_ASKNAME; break; case 'd': boothowto |= RB_KDB; break; case 'g': boothowto |= RB_GDB; break; case 's': boothowto |= RB_SINGLE; break; case 'v': boothowto |= RB_VERBOSE; break; } } } else { n = strsep(&v, "="); if (v == NULL) kern_setenv(n, "1"); else kern_setenv(n, v); } } } void platform_cpu_init() { /* Nothing special */ } void platform_reset(void) { ar71xx_device_stop(RST_RESET_FULL_CHIP); /* Wait for reset */ while(1) ; } /* * Obtain the MAC address via the Redboot environment. */ static int ar71xx_redboot_get_macaddr(void) { char *var; int count = 0, i; uint32_t macaddr[ETHER_ADDR_LEN]; uint8_t tmpmac[ETHER_ADDR_LEN]; /* * "ethaddr" is passed via envp on RedBoot platforms * "kmac" is passed via argv on RouterBOOT platforms */ if ((var = kern_getenv("ethaddr")) != NULL || (var = kern_getenv("kmac")) != NULL) { count = sscanf(var, "%x%*c%x%*c%x%*c%x%*c%x%*c%x", &macaddr[0], &macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4], &macaddr[5]); if (count < 6) { memset(macaddr, 0, sizeof(macaddr)); } else { for (i = 0; i < ETHER_ADDR_LEN; i++) tmpmac[i] = macaddr[i] & 0xff; (void) ar71xx_mac_addr_init(ar71xx_board_mac_addr, tmpmac, 0, /* offset */ 0); /* is_local */ } freeenv(var); return (0); } return (-1); } #ifdef AR71XX_ENV_ROUTERBOOT /* * RouterBoot gives us the board memory in a command line argument. */ static int ar71xx_routerboot_get_mem(int argc, char **argv) { int i, board_mem; /* * Protect ourselves from garbage in registers. */ if (!MIPS_IS_VALID_PTR(argv)) return (0); for (i = 0; i < argc; i++) { if (argv[i] == NULL) continue; if (strncmp(argv[i], "mem=", 4) == 0) { if (sscanf(argv[i] + 4, "%dM", &board_mem) == 1) return (btoc(board_mem * 1024 * 1024)); } } return (0); } #endif /* * Handle initialising the MAC address from a specific EEPROM * offset. * * This is done during (very) early boot. * * hint.ar71xx.0.eeprom_mac_addr=
* hint.ar71xx.0.eeprom_mac_isascii=<0|1> */ static int ar71xx_platform_read_eeprom_mac(void) { long eeprom_mac_addr = 0; const char *mac; int i, readascii = 0; uint8_t macaddr[ETHER_ADDR_LEN]; if (resource_long_value("ar71xx", 0, "eeprom_mac_addr", &eeprom_mac_addr) != 0) return (-1); /* get a pointer to the EEPROM MAC address */ mac = (const char *) MIPS_PHYS_TO_KSEG1(eeprom_mac_addr); /* Check if it's ASCII or not */ if (resource_int_value("ar71xx", 0, "eeprom_mac_isascii", &readascii) == 0 && readascii == 1) { printf("ar71xx: Overriding MAC from EEPROM (ascii)\n"); for (i = 0; i < 6; i++) { macaddr[i] = strtol(&(mac[i*3]), NULL, 16); } } else { printf("ar71xx: Overriding MAC from EEPROM\n"); for (i = 0; i < 6; i++) { macaddr[i] = mac[i]; } } /* Set the default board MAC */ (void) ar71xx_mac_addr_init(ar71xx_board_mac_addr, macaddr, 0, /* offset */ 0); /* is_local */ printf("ar71xx: Board MAC: %6D\n", ar71xx_board_mac_addr, ":"); return (0); } /* * Populate a kenv hint for the given device based on the given * MAC address and offset. * * Returns 0 if ok, < 0 on error. */ static int ar71xx_platform_set_mac_hint(const char *dev, int unit, const uint8_t *macaddr, int offset, int islocal) { char macstr[32]; uint8_t lclmac[ETHER_ADDR_LEN]; char devstr[32]; /* Initialise the MAC address, plus/minus the offset */ if (ar71xx_mac_addr_init(lclmac, macaddr, offset, islocal) != 0) { return (-1); } /* Turn it into a string */ snprintf(macstr, 32, "%6D", lclmac, ":"); snprintf(devstr, 32, "hint.%s.%d.macaddr", dev, unit); printf(" %s => %s\n", devstr, macstr); /* Call setenv */ if (kern_setenv(devstr, macstr) != 0) { printf("%s: failed to set hint (%s => %s)\n", __func__, devstr, macstr); return (-1); } return (0); } /* * Iterate through the list of boot time hints that populate * a device MAC address hint based on the "board" MAC address. * * ar71xx_mac_map.X.devid= * ar71xx_mac_map.X.unitid= * ar71xx_mac_map.X.offset= * ar71xx_mac_map.X.is_local=<1 or 0> */ static int ar71xx_platform_check_mac_hints(void) { int i; const char *devid; int offset, is_local, unitid; for (i = 0; i < 8; i++) { if (resource_string_value("ar71xx_mac_map", i, "devid", &devid) != 0) break; if (resource_int_value("ar71xx_mac_map", i, "unitid", &unitid) != 0) break; if (resource_int_value("ar71xx_mac_map", i, "offset", &offset) != 0) break; if (resource_int_value("ar71xx_mac_map", i, "is_local", &is_local) != 0) break; printf("ar71xx: devid '%s.%d', MAC offset '%d'\n", devid, unitid, offset); (void) ar71xx_platform_set_mac_hint(devid, unitid, ar71xx_board_mac_addr, offset, is_local); } return (0); } extern char cpu_model[]; void platform_start(__register_t a0 __unused, __register_t a1 __unused, __register_t a2 __unused, __register_t a3 __unused) { uint64_t platform_counter_freq; int argc = 0, i; char **argv = NULL, **envp = NULL; vm_offset_t kernend; /* * clear the BSS and SBSS segments, this should be first call in * the function */ kernend = (vm_offset_t)&end; memset(&edata, 0, kernend - (vm_offset_t)(&edata)); mips_postboot_fixup(); /* Initialize pcpu stuff */ mips_pcpu0_init(); /* * Until some more sensible abstractions for uboot/redboot * environment handling, we have to make this a compile-time * hack. The existing code handles the uboot environment * very incorrectly so we should just ignore initialising * the relevant pointers. */ #ifndef AR71XX_ENV_UBOOT argc = a0; argv = (char**)a1; envp = (char**)a2; #endif /* * Protect ourselves from garbage in registers */ if (MIPS_IS_VALID_PTR(envp)) { for (i = 0; envp[i]; i += 2) { if (strcmp(envp[i], "memsize") == 0) realmem = btoc(strtoul(envp[i+1], NULL, 16)); else if (strcmp(envp[i], "bootverbose") == 0) bootverbose = btoc(strtoul(envp[i+1], NULL, 10)); } } bootverbose = 1; #ifdef AR71XX_ENV_ROUTERBOOT /* * RouterBoot informs the board memory as a command line argument. */ if (realmem == 0) realmem = ar71xx_routerboot_get_mem(argc, argv); #endif /* * Just wild guess. RedBoot let us down and didn't reported * memory size */ if (realmem == 0) realmem = btoc(32*1024*1024); /* * Allow build-time override in case Redboot lies * or in other situations (eg where there's u-boot) * where there isn't (yet) a convienent method of * being told how much RAM is available. * * This happens on at least the Ubiquiti LS-SR71A * board, where redboot says there's 16mb of RAM * but in fact there's 32mb. */ #if defined(AR71XX_REALMEM) realmem = btoc(AR71XX_REALMEM); #endif /* phys_avail regions are in bytes */ phys_avail[0] = MIPS_KSEG0_TO_PHYS(kernel_kseg0_end); phys_avail[1] = ctob(realmem); dump_avail[0] = phys_avail[0]; dump_avail[1] = phys_avail[1] - phys_avail[0]; physmem = realmem; /* * ns8250 uart code uses DELAY so ticker should be inititalized * before cninit. And tick_init_params refers to hz, so * init_param1 * should be called first. */ init_param1(); /* Detect the system type - this is needed for subsequent chipset-specific calls */ ar71xx_detect_sys_type(); ar71xx_detect_sys_frequency(); platform_counter_freq = ar71xx_cpu_freq(); mips_timer_init_params(platform_counter_freq, 1); cninit(); init_static_kenv(boot1_env, sizeof(boot1_env)); printf("CPU platform: %s\n", ar71xx_get_system_type()); printf("CPU Frequency=%d MHz\n", u_ar71xx_cpu_freq / 1000000); printf("CPU DDR Frequency=%d MHz\n", u_ar71xx_ddr_freq / 1000000); printf("CPU AHB Frequency=%d MHz\n", u_ar71xx_ahb_freq / 1000000); printf("platform frequency: %lld MHz\n", platform_counter_freq / 1000000); printf("CPU reference clock: %d MHz\n", u_ar71xx_refclk / 1000000); printf("CPU MDIO clock: %d MHz\n", u_ar71xx_mdio_freq / 1000000); printf("arguments: \n"); printf(" a0 = %08x\n", a0); printf(" a1 = %08x\n", a1); printf(" a2 = %08x\n", a2); printf(" a3 = %08x\n", a3); strcpy(cpu_model, ar71xx_get_system_type()); /* * XXX this code is very redboot specific. */ printf("Cmd line:"); if (MIPS_IS_VALID_PTR(argv)) { for (i = 0; i < argc; i++) { printf(" %s", argv[i]); parse_argv(argv[i]); } } else printf ("argv is invalid"); printf("\n"); printf("Environment:\n"); if (MIPS_IS_VALID_PTR(envp)) { for (i = 0; envp[i]; i+=2) { printf(" %s = %s\n", envp[i], envp[i+1]); kern_setenv(envp[i], envp[i+1]); } } else printf ("envp is invalid\n"); /* Platform setup */ init_param2(physmem); mips_cpu_init(); pmap_bootstrap(); mips_proc0_init(); mutex_init(); /* * Reset USB devices */ ar71xx_init_usb_peripheral(); /* * Reset internal ethernet switch, if one exists */ ar71xx_reset_ethernet_switch(); /* * Initialise the gmac driver. */ ar71xx_init_gmac(); /* Redboot if_arge MAC address is in the environment */ (void) ar71xx_redboot_get_macaddr(); /* Various other boards need things to come out of EEPROM */ (void) ar71xx_platform_read_eeprom_mac(); /* Initialise the MAC address hint map */ ar71xx_platform_check_mac_hints(); kdb_init(); #ifdef KDB if (boothowto & RB_KDB) kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); #endif } Index: head/sys/mips/atheros/ar724x_chip.c =================================================================== --- head/sys/mips/atheros/ar724x_chip.c (revision 302189) +++ head/sys/mips/atheros/ar724x_chip.c (revision 302190) @@ -1,246 +1,244 @@ /*- * Copyright (c) 2010 Adrian Chadd * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_ddb.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include -#include - static void ar724x_chip_detect_mem_size(void) { } static void ar724x_chip_detect_sys_frequency(void) { uint32_t pll; uint32_t freq; uint32_t div; u_ar71xx_mdio_freq = u_ar71xx_refclk = AR724X_BASE_FREQ; pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG); div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); freq = div * AR724X_BASE_FREQ; div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); freq *= div; u_ar71xx_cpu_freq = freq; div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; u_ar71xx_ddr_freq = freq / div; div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div; u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div; u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div; } static void ar724x_chip_device_stop(uint32_t mask) { uint32_t mask_inv, reg; mask_inv = mask & AR724X_RESET_MODULE_USB_OHCI_DLL; reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE); reg |= mask; reg &= ~mask_inv; ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg); } static void ar724x_chip_device_start(uint32_t mask) { uint32_t mask_inv, reg; mask_inv = mask & AR724X_RESET_MODULE_USB_OHCI_DLL; reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE); reg &= ~mask; reg |= mask_inv; ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg); } static int ar724x_chip_device_stopped(uint32_t mask) { uint32_t reg; reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE); return ((reg & mask) == mask); } static void ar724x_chip_set_mii_speed(uint32_t unit, uint32_t speed) { /* XXX TODO */ return; } /* * XXX TODO: set the PLL for arge0 only on AR7242. * The PLL/clock requirements are different. * * Otherwise, it's a NULL function for AR7240, AR7241 and * AR7242 arge1. */ static void ar724x_chip_set_pll_ge(int unit, int speed, uint32_t pll) { switch (unit) { case 0: /* XXX TODO */ break; case 1: /* XXX TODO */ break; default: printf("%s: invalid PLL set for arge unit: %d\n", __func__, unit); return; } } static void ar724x_chip_ddr_flush(ar71xx_flush_ddr_id_t id) { switch (id) { case AR71XX_CPU_DDR_FLUSH_GE0: ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0); break; case AR71XX_CPU_DDR_FLUSH_GE1: ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1); break; case AR71XX_CPU_DDR_FLUSH_USB: ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_USB); break; case AR71XX_CPU_DDR_FLUSH_PCIE: ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_PCIE); break; default: printf("%s: invalid DDR flush id (%d)\n", __func__, id); break; } } static uint32_t ar724x_chip_get_eth_pll(unsigned int mac, int speed) { return (0); } static void ar724x_chip_init_usb_peripheral(void) { switch (ar71xx_soc) { case AR71XX_SOC_AR7240: ar71xx_device_stop(AR724X_RESET_MODULE_USB_OHCI_DLL | AR724X_RESET_USB_HOST); DELAY(1000); ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL | AR724X_RESET_USB_HOST); DELAY(1000); /* * WAR for HW bug. Here it adjusts the duration * between two SOFS. */ ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ, (3 << USB_CTRL_FLADJ_A0_SHIFT)); break; case AR71XX_SOC_AR7241: case AR71XX_SOC_AR7242: ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL); DELAY(100); ar71xx_device_start(AR724X_RESET_USB_HOST); DELAY(100); ar71xx_device_start(AR724X_RESET_USB_PHY); DELAY(100); break; default: break; } } struct ar71xx_cpu_def ar724x_chip_def = { &ar724x_chip_detect_mem_size, &ar724x_chip_detect_sys_frequency, &ar724x_chip_device_stop, &ar724x_chip_device_start, &ar724x_chip_device_stopped, &ar724x_chip_set_pll_ge, &ar724x_chip_set_mii_speed, &ar71xx_chip_set_mii_if, &ar724x_chip_get_eth_pll, &ar724x_chip_ddr_flush, &ar724x_chip_init_usb_peripheral }; Index: head/sys/mips/atheros/ar91xx_chip.c =================================================================== --- head/sys/mips/atheros/ar91xx_chip.c (revision 302189) +++ head/sys/mips/atheros/ar91xx_chip.c (revision 302190) @@ -1,219 +1,217 @@ /*- * Copyright (c) 2010 Adrian Chadd * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_ddb.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include -#include - static void ar91xx_chip_detect_mem_size(void) { } static void ar91xx_chip_detect_sys_frequency(void) { uint32_t pll; uint32_t freq; uint32_t div; u_ar71xx_mdio_freq = u_ar71xx_refclk = AR91XX_BASE_FREQ; pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG); div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK); freq = div * AR91XX_BASE_FREQ; u_ar71xx_cpu_freq = freq; div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1; u_ar71xx_ddr_freq = freq / div; div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2; u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div; u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div; u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div; } static void ar91xx_chip_device_stop(uint32_t mask) { uint32_t reg; reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE); ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg | mask); } static void ar91xx_chip_device_start(uint32_t mask) { uint32_t reg; reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE); ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg & ~mask); } static int ar91xx_chip_device_stopped(uint32_t mask) { uint32_t reg; reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE); return ((reg & mask) == mask); } static void ar91xx_chip_set_pll_ge(int unit, int speed, uint32_t pll) { switch (unit) { case 0: ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK, pll, AR91XX_ETH0_PLL_SHIFT); break; case 1: ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK, pll, AR91XX_ETH1_PLL_SHIFT); break; default: printf("%s: invalid PLL set for arge unit: %d\n", __func__, unit); return; } } static void ar91xx_chip_ddr_flush(ar71xx_flush_ddr_id_t id) { switch (id) { case AR71XX_CPU_DDR_FLUSH_GE0: ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0); break; case AR71XX_CPU_DDR_FLUSH_GE1: ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1); break; case AR71XX_CPU_DDR_FLUSH_USB: ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_USB); break; case AR71XX_CPU_DDR_FLUSH_WMAC: ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC); break; default: printf("%s: invalid DDR flush id (%d)\n", __func__, id); break; } } static uint32_t ar91xx_chip_get_eth_pll(unsigned int mac, int speed) { uint32_t pll; switch(speed) { case 10: pll = AR91XX_PLL_VAL_10; break; case 100: pll = AR91XX_PLL_VAL_100; break; case 1000: pll = AR91XX_PLL_VAL_1000; break; default: printf("%s%d: invalid speed %d\n", __func__, mac, speed); pll = 0; } return (pll); } static void ar91xx_chip_init_usb_peripheral(void) { ar71xx_device_stop(AR91XX_RST_RESET_MODULE_USBSUS_OVERRIDE); DELAY(100); ar71xx_device_start(RST_RESET_USB_HOST); DELAY(100); ar71xx_device_start(RST_RESET_USB_PHY); DELAY(100); /* Wireless */ ar71xx_device_stop(AR91XX_RST_RESET_MODULE_AMBA2WMAC); DELAY(1000); ar71xx_device_start(AR91XX_RST_RESET_MODULE_AMBA2WMAC); DELAY(1000); } struct ar71xx_cpu_def ar91xx_chip_def = { &ar91xx_chip_detect_mem_size, &ar91xx_chip_detect_sys_frequency, &ar91xx_chip_device_stop, &ar91xx_chip_device_start, &ar91xx_chip_device_stopped, &ar91xx_chip_set_pll_ge, &ar71xx_chip_set_mii_speed, &ar71xx_chip_set_mii_if, &ar91xx_chip_get_eth_pll, &ar91xx_chip_ddr_flush, &ar91xx_chip_init_usb_peripheral, }; Index: head/sys/mips/broadcom/bcm_machdep.c =================================================================== --- head/sys/mips/broadcom/bcm_machdep.c (revision 302189) +++ head/sys/mips/broadcom/bcm_machdep.c (revision 302190) @@ -1,221 +1,256 @@ /*- * Copyright (c) 2007 Bruce M. Simpson. * Copyright (c) 2016 Michael Zhilin * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_ddb.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include -#include #include "bcm_socinfo.h" #ifdef CFE #include #endif #if 0 -#define BROADCOM_TRACE 0 +#define BCM_TRACE(_fmt, ...) printf(_fmt, ##__VA_ARGS__) +#else +#define BCM_TRACE(_fmt, ...) #endif extern int *edata; extern int *end; void platform_cpu_init() { /* Nothing special */ } static void mips_init(void) { int i, j; printf("entry: mips_init()\n"); #ifdef CFE /* * Query DRAM memory map from CFE. */ physmem = 0; for (i = 0; i < 10; i += 2) { int result; uint64_t addr, len, type; result = cfe_enummem(i / 2, 0, &addr, &len, &type); if (result < 0) { -#ifdef BROADCOM_TRACE - printf("There is no phys memory for: %d\n", i); -#endif + BCM_TRACE("There is no phys memory for: %d\n", i); phys_avail[i] = phys_avail[i + 1] = 0; break; } - if (type != CFE_MI_AVAILABLE){ -#ifdef BROADCOM_TRACE - printf("phys memory is not available: %d\n", i); -#endif + if (type != CFE_MI_AVAILABLE) { + BCM_TRACE("phys memory is not available: %d\n", i); continue; } phys_avail[i] = addr; if (i == 0 && addr == 0) { /* * If this is the first physical memory segment probed * from CFE, omit the region at the start of physical * memory where the kernel has been loaded. */ phys_avail[i] += MIPS_KSEG0_TO_PHYS(kernel_kseg0_end); } -#ifdef BROADCOM_TRACE - printf("phys memory is available for: %d\n", i); - printf(" => addr = %jx\n", addr); - printf(" => len = %jd\n", len); -#endif + + BCM_TRACE("phys memory is available for: %d\n", i); + BCM_TRACE(" => addr = %jx\n", addr); + BCM_TRACE(" => len = %jd\n", len); + phys_avail[i + 1] = addr + len; physmem += len; } -#ifdef BROADCOM_TRACE - printf("Total phys memory is : %ld\n", physmem); -#endif - + BCM_TRACE("Total phys memory is : %ld\n", physmem); realmem = btoc(physmem); #endif for (j = 0; j < i; j++) dump_avail[j] = phys_avail[j]; physmem = realmem; init_param1(); init_param2(physmem); mips_cpu_init(); pmap_bootstrap(); mips_proc0_init(); mutex_init(); kdb_init(); #ifdef KDB if (boothowto & RB_KDB) kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); #endif } -#define BCM_REG_CHIPC 0x18000000 - - void platform_reset(void) { printf("bcm::platform_reset()\n"); intr_disable(); + +#if defined(CFE) + cfe_exit(0, 0); +#else + /* PMU watchdog reset */ BCM_WRITE_REG32(BCM_REG_CHIPC_PMUWD_OFFS, 2); /* PMU watchdog */ +#endif + +#if 0 + /* Non-PMU reset + * XXX: Need chipc capability flags */ + *((volatile uint8_t *)MIPS_PHYS_TO_KSEG1(SENTRY5_EXTIFADR)) = 0x80; +#endif + for (;;); } void platform_start(__register_t a0, __register_t a1, __register_t a2, __register_t a3) { vm_offset_t kernend; uint64_t platform_counter_freq; struct bcm_socinfo *socinfo; /* clear the BSS and SBSS segments */ kernend = (vm_offset_t)&end; memset(&edata, 0, kernend - (vm_offset_t)(&edata)); mips_postboot_fixup(); /* Initialize pcpu stuff */ mips_pcpu0_init(); +#if 0 + /* + * Probe the Broadcom on-chip PLL clock registers + * and discover the CPU pipeline clock and bus clock + * multipliers from this. + * XXX: Wrong place. You have to ask the ChipCommon + * or External Interface cores on the SiBa. + */ + uint32_t busmult, cpumult, refclock, clkcfg1; +#define S5_CLKCFG1_REFCLOCK_MASK 0x0000001F +#define S5_CLKCFG1_BUSMULT_MASK 0x000003E0 +#define S5_CLKCFG1_BUSMULT_SHIFT 5 +#define S5_CLKCFG1_CPUMULT_MASK 0xFFFFFC00 +#define S5_CLKCFG1_CPUMULT_SHIFT 10 + + counter_freq = 100000000; /* XXX */ + + clkcfg1 = s5_rd_clkcfg1(); + printf("clkcfg1 = 0x%08x\n", clkcfg1); + + refclock = clkcfg1 & 0x1F; + busmult = ((clkcfg1 & 0x000003E0) >> 5) + 1; + cpumult = ((clkcfg1 & 0xFFFFFC00) >> 10) + 1; + + printf("refclock = %u\n", refclock); + printf("busmult = %u\n", busmult); + printf("cpumult = %u\n", cpumult); + + counter_freq = cpumult * refclock; +#endif + socinfo = bcm_get_socinfo(); platform_counter_freq = socinfo->cpurate * 1000 * 1000; /* BCM4718 is 480MHz */ mips_timer_early_init(platform_counter_freq); #ifdef CFE /* * Initialize CFE firmware trampolines before * we initialize the low-level console. * * CFE passes the following values in registers: * a0: firmware handle * a2: firmware entry point * a3: entry point seal */ if (a3 == CFE_EPTSEAL) cfe_init(a0, a2); #endif + cninit(); mips_init(); - /* BCM471x timer is 1/2 of Clk */ - mips_timer_init_params(platform_counter_freq, 1); + mips_timer_init_params(platform_counter_freq, socinfo->double_count); } Index: head/sys/mips/broadcom/bcm_socinfo.c =================================================================== --- head/sys/mips/broadcom/bcm_socinfo.c (revision 302189) +++ head/sys/mips/broadcom/bcm_socinfo.c (revision 302190) @@ -1,90 +1,91 @@ /*- * Copyright (c) 2016 Michael Zhilin * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include "bcm_socinfo.h" /* found on https://wireless.wiki.kernel.org/en/users/drivers/b43/soc */ struct bcm_socinfo bcm_socinfos[] = { - {0x00005300, 600, 25000000}, /* BCM4706 to check */ - {0x0022B83A, 300, 20000000}, /* BCM4716B0 ASUS RT-N12 */ - {0x00914716, 354, 20000000}, /* BCM4717A1 to check */ - {0x00A14716, 480, 20000000}, /* BCM4718A1 ASUS RT-N16 */ - {0x00435356, 300, 25000000}, /* BCM5356A1 (RT-N10, WNR1000v3) */ - {0x00825357, 500, 20000000}, /* BCM5358UB0 ASUS RT-N53A1 */ - {0x00845357, 300, 20000000}, /* BCM5357B0 to check */ - {0x00945357, 500, 20000000}, /* BCM5358 */ - {0x00A45357, 500, 20000000}, /* BCM47186B0 Tenda N60 */ - {0x0085D144, 300, 20000000}, /* BCM5356C0 */ - {0x00B5D144, 300, 20000000}, /* BCM5357C0 */ + {0x00005300, 600, 25000000, 1}, /* BCM4706 to check */ + {0x0022B83A, 300, 20000000, 1}, /* BCM4716B0 ASUS RT-N12 */ + {0x00914716, 354, 20000000, 1}, /* BCM4717A1 to check */ + {0x00A14716, 480, 20000000, 1}, /* BCM4718A1 ASUS RT-N16 */ + {0x00435356, 300, 25000000, 1}, /* BCM5356A1 (RT-N10, WNR1000v3) */ + {0x00825357, 500, 20000000, 1}, /* BCM5358UB0 ASUS RT-N53A1 */ + {0x00845357, 300, 20000000, 1}, /* BCM5357B0 to check */ + {0x00945357, 500, 20000000, 1}, /* BCM5358 */ + {0x00A45357, 500, 20000000, 1}, /* BCM47186B0 Tenda N60 */ + {0x0085D144, 300, 20000000, 1}, /* BCM5356C0 */ + {0x00B5D144, 300, 20000000, 1}, /* BCM5357C0 */ + {0x00015365, 200, 0, 1}, /* BCM5365 */ {0,0,0} }; /* Most popular BCM SoC info */ -struct bcm_socinfo BCM_DEFAULT_SOCINFO = {0x0, 300, 20000000}; +struct bcm_socinfo BCM_DEFAULT_SOCINFO = {0x0, 300, 20000000, 0}; struct bcm_socinfo* bcm_get_socinfo_by_socid(uint32_t key) { struct bcm_socinfo* start; if(!key) return (NULL); for(start = bcm_socinfos; start->id > 0; start++) if(start->id == key) return (start); return (NULL); } struct bcm_socinfo* bcm_get_socinfo(void) { uint32_t socid; struct bcm_socinfo *socinfo; /* * We need Chip ID + Revision + Package * -------------------------------------------------------------- * | Mask | Usage | * -------------------------------------------------------------- * | 0x0000FFFF | Chip ID | * | 0x000F0000 | Chip Revision | * | 0x00F00000 | Package Options | * | 0x0F000000 | Number of Cores (ChipCommon Rev. >= 4)| * | 0xF0000000 | Chip Type | * -------------------------------------------------------------- */ socid = BCM_READ_REG32(BCM_REG_CHIPC_ID) & 0x00FFFFFF; socinfo = bcm_get_socinfo_by_socid(socid); return (socinfo != NULL) ? socinfo : &BCM_DEFAULT_SOCINFO; } Index: head/sys/mips/broadcom/bcm_socinfo.h =================================================================== --- head/sys/mips/broadcom/bcm_socinfo.h (revision 302189) +++ head/sys/mips/broadcom/bcm_socinfo.h (revision 302190) @@ -1,59 +1,60 @@ /*- * Copyright (c) 2016 Michael Zhilin * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * $FreeBSD$ */ #ifndef _MIPS_BROADCOM_BCM_SOCINFO_H_ #define _MIPS_BROADCOM_BCM_SOCINFO_H_ #include struct bcm_socinfo { - uint32_t id; - uint32_t cpurate; /* in MHz */ - uint32_t uartrate; /* in Hz */ + uint32_t id; + uint32_t cpurate; /* in MHz */ + uint32_t uartrate; /* in Hz */ + int double_count; }; struct bcm_socinfo* bcm_get_socinfo_by_socid(uint32_t key); struct bcm_socinfo* bcm_get_socinfo(void); #define BCM_SOCADDR 0x18000000 #define BCM_REG_CHIPC_ID 0x0 #define BCM_REG_CHIPC_UART 0x300 #define BCM_REG_CHIPC_PMUWD_OFFS 0x634 #define BCM_SOCREG(reg) \ MIPS_PHYS_TO_KSEG1((BCM_SOCADDR + (reg))) #define BCM_READ_REG32(reg) \ *((volatile uint32_t *)BCM_SOCREG(reg)) #define BCM_WRITE_REG32(reg, value) \ do { \ writel((void*)BCM_SOCREG((reg)),value); \ } while (0); #endif /* _MIPS_BROADCOM_BCM_SOCINFO_H_ */ Index: head/sys/mips/broadcom/std.broadcom =================================================================== --- head/sys/mips/broadcom/std.broadcom (revision 302189) +++ head/sys/mips/broadcom/std.broadcom (revision 302190) @@ -1,7 +1,9 @@ # $FreeBSD$ # machine mips mipsel -cpu CPU_MIPS74K +makeoptions INTRNG +options INTRNG + files "../broadcom/files.broadcom" Index: head/sys/mips/broadcom/uart_cpu_chipc.c =================================================================== --- head/sys/mips/broadcom/uart_cpu_chipc.c (revision 302189) +++ head/sys/mips/broadcom/uart_cpu_chipc.c (revision 302190) @@ -1,78 +1,123 @@ /*- * Copyright (c) 2016 Michael Zhilin * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_uart.h" #include #include #include #include #include #include #include +#include + #include #include #include #include "bcm_socinfo.h" bus_space_tag_t uart_bus_space_io; bus_space_tag_t uart_bus_space_mem; +static struct uart_class *chipc_uart_class = &uart_ns8250_class; + +#define CHIPC_UART_BAUDRATE 115200 + int uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2) { return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0); } -int -uart_cpu_getdev(int devtype, struct uart_devinfo *di) +static int +uart_cpu_init(struct uart_devinfo *di, int uart, int baudrate) { - struct uart_class *class; struct bcm_socinfo *socinfo; + if (uart >= CHIPC_UART_MAX) + return (EINVAL); + socinfo = bcm_get_socinfo(); - class = &uart_ns8250_class; - di->ops = uart_getops(class); + di->ops = uart_getops(chipc_uart_class); di->bas.chan = 0; - di->bas.bst = mips_bus_space_generic; - di->bas.bsh = (bus_space_handle_t)BCM_SOCREG(BCM_REG_CHIPC_UART); + di->bas.bst = uart_bus_space_mem; + di->bas.bsh = (bus_space_handle_t) BCM_SOCREG(CHIPC_UART(uart)); di->bas.regshft = 0; di->bas.rclk = socinfo->uartrate; /* in Hz */ - di->baudrate = 115200; + di->baudrate = baudrate; di->databits = 8; di->stopbits = 1; di->parity = UART_PARITY_NONE; + + return (0); +} + +int +uart_cpu_getdev(int devtype, struct uart_devinfo *di) +{ + int ivar; + uart_bus_space_io = NULL; uart_bus_space_mem = mips_bus_space_generic; - return (0); + + /* Check the environment. */ + if (uart_getenv(devtype, di, chipc_uart_class) == 0) + return (0); + + /* Scan the device hints for the first matching device */ + for (int i = 0; i < CHIPC_UART_MAX; i++) { + if (resource_int_value("uart", i, "flags", &ivar)) + continue; + + /* Check usability */ + if (devtype == UART_DEV_CONSOLE && !UART_FLAGS_CONSOLE(ivar)) + continue; + + if (devtype == UART_DEV_DBGPORT && !UART_FLAGS_DBGPORT(ivar)) + continue; + + if (resource_int_value("uart", i, "disabled", &ivar) == 0 && + ivar == 0) + continue; + + /* Found */ + if (resource_int_value("uart", i, "baud", &ivar) != 0) + ivar = CHIPC_UART_BAUDRATE; + + return (uart_cpu_init(di, i, ivar)); + } + + /* Default to uart0/115200 */ + return (uart_cpu_init(di, 0, CHIPC_UART_BAUDRATE)); } Index: head/sys/mips/conf/BCM =================================================================== --- head/sys/mips/conf/BCM (revision 302189) +++ head/sys/mips/conf/BCM (revision 302190) @@ -1,100 +1,98 @@ # # $FreeBSD$ # # The Broadcom 470x/471x/535x series of processors and boards is very commonly # used in COTS hardware including the ASUS RT-N12, RT-N16, RT-N53. # ident BCM +cpu CPU_MIPS74K hints "BCM.hints" include "../broadcom/std.broadcom" # ships with cfe firmware options CFE options ALT_BREAK_TO_DEBUGGER options BREAK_TO_DEBUGGER options BOOTVERBOSE=0 - -makeoptions INTRNG -options INTRNG makeoptions TRAMPLOADADDR=0x80800000 makeoptions DEBUG="-g3" #Build kernel with gdb(1) debug symbols makeoptions MODULES_OVERRIDE="" options DDB options KDB options SCHED_4BSD #4BSD scheduler options INET #InterNETworking options NFSCL #Network Filesystem Client #options NFS_ROOT #NFS usable as /, requires NFSCL options PSEUDOFS #Pseudo-filesystem framework options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions options FFS #Berkeley Fast Filesystem options SOFTUPDATES #Enable FFS soft updates support options UFS_ACL #Support for access control lists options UFS_DIRHASH #Improve performance on big directories device geom_uzip options GEOM_UZIP options GEOM_LABEL # Providers labelization. options ROOTDEVNAME=\"ufs:ufs/FBSD\" # assumes FW built by # freebsd-build-wifi # Debugging for use in -current #options DEADLKRES options INVARIANTS options INVARIANT_SUPPORT #options BHND_LOGLEVEL=BHND_DEBUG_LEVEL #options BUS_DEBUG #makeoptions BUS_DEBUG #options VERBOSE_SYSINIT #makeoptions VERBOSE_SYSINIT # bhnd(4) device bhnd device bcma # bcma backplane device bcma_nexus device pci device bhnd_pcib # PCIe-G1 core #device bgmac # Broadcom GMAC - not yet device mdio #Flash device spibus device mx25l # Serial Flash device cfi # Parallel Flash device cfid #UART device uart #Base device loop device ether device random device md #Performance #options HWPMC_HOOKS #device hwpmc #device hwpmc_mips74k #Ethernet # device bfe # XXX will build both pci and siba device miibus # attachments # pci devices # USB is not yet ready #options USB_DEBUG # enable debug msgs #device usb # USB Bus (required) #device uhci # UHCI PCI->USB interface #device ehci # EHCI PCI->USB interface (USB 2.0) Index: head/sys/mips/conf/BCM.hints =================================================================== --- head/sys/mips/conf/BCM.hints (revision 302189) +++ head/sys/mips/conf/BCM.hints (revision 302190) @@ -1,5 +1,4 @@ # $FreeBSD$ hint.bhnd.0.at="nexus0" hint.bhnd.0.maddr="0x18000000" hint.bhnd.0.msize="0x00100000" - Index: head/sys/mips/conf/SENTRY5 =================================================================== --- head/sys/mips/conf/SENTRY5 (revision 302189) +++ head/sys/mips/conf/SENTRY5 (revision 302190) @@ -1,89 +1,88 @@ # # $FreeBSD$ # # The Broadcom Sentry5 series of processors and boards is very commonly # used in COTS hardware including the Netgear WGT634U. # # Some tweaks are needed for use with this platform: # # * CFE firmware's ELF loader expects an ELF kernel which is linked so as # not to contain offsets in PT_LOAD which point behind the actual offset # of that PT header. FreeBSD normally links the first PT_LOAD header to # begin at offset 0. # # * Broadcom's support package for the internal bus, the Sonics # SiliconBackplane, needs to be integrated to detect and probe hardware # correctly. # # * The clock needs to be calibrated correctly, so that DELAY() may work. # One problem with this is that the low-level printf() routine calls DELAY(), # which currently causes divide-by-zero trap # # * The Broadcom CPUs have no FPU. Attempting to detect one by reading CP1's # status register causes an unhandled boot-time exception. An FPU emulator # will be necessary to support multi-user boot. # ident SENTRY5 +cpu CPU_MIPS4KC +makeoptions TRAMPLOADADDR=0x807963c0 -# XXX only siba should be hardwired for now; we will use -# bus enumeration there hints "SENTRY5.hints" -include "../sentry5/std.sentry5" +include "../broadcom/std.broadcom" # sentry5 normally ships with cfe firmware; use the console for now options CFE options CFE_CONSOLE options ALT_BREAK_TO_DEBUGGER makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols makeoptions MODULES_OVERRIDE="" options DDB options KDB options SCHED_4BSD #4BSD scheduler options INET #InterNETworking options NFSCL #Network Filesystem Client options NFS_ROOT #NFS usable as /, requires NFSCL options PSEUDOFS #Pseudo-filesystem framework options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions # Debugging for use in -current #options DEADLKRES options INVARIANTS options INVARIANT_SUPPORT #options BUS_DEBUG #makeoptions BUS_DEBUG device bhnd device siba device siba_nexus device bhnd_pcib device pci # bhnd_pcib # device bfe # XXX will build both pci and siba # device miibus # attachments # pci devices # notyet: #device ath # in pci slot #device ath_pci # Atheros pci/cardbus glue #device ath_hal # pci chip support #options AH_SUPPORT_AR5416 # enable AR5416 tx/rx descriptors options USB_DEBUG # enable debug msgs device usb # USB Bus (required) device uhci # UHCI PCI->USB interface device ehci # EHCI PCI->USB interface (USB 2.0) -# need to teach the code to ignore the bridge.... +device cfi # parallel flash +device cfid - -# XXX notyet; need to be auto probed children of siba_cc. -#device uart +device uart device loop device ether device md Index: head/sys/mips/conf/SENTRY5.hints =================================================================== --- head/sys/mips/conf/SENTRY5.hints (revision 302189) +++ head/sys/mips/conf/SENTRY5.hints (revision 302190) @@ -1,5 +1,7 @@ # $FreeBSD$ hint.bhnd.0.at="nexus0" -hint.bhnd.0.maddr="0x18000000" -hint.bhnd.0.msize="0x1000" -# XXX irq? +hint.bhnd.0.maddr="0x18000000" +hint.bhnd.0.msize="0x00100000" + +# console on uart1 +hint.uart.1.flags="0x10" Index: head/sys/mips/sentry5/uart_cpu_sbusart.c =================================================================== --- head/sys/mips/sentry5/uart_cpu_sbusart.c (revision 302189) +++ head/sys/mips/sentry5/uart_cpu_sbusart.c (nonexistent) @@ -1,82 +0,0 @@ -/*- - * Copyright (c) 2006 Wojciech A. Koszek - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $Id$ - */ -/* - * Skeleton of this file was based on respective code for ARM - * code written by Olivier Houchard. - */ -/* - * XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is - * experimental and was written for MIPS32 port. - */ -#include "opt_uart.h" - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include - -#include - -#include -#include - -#include - -bus_space_tag_t uart_bus_space_io; -bus_space_tag_t uart_bus_space_mem; - -extern struct uart_ops malta_usart_ops; -extern struct bus_space malta_bs_tag; - -int -uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2) -{ - return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0); -} - -int -uart_cpu_getdev(int devtype, struct uart_devinfo *di) -{ - di->ops = uart_getops(&uart_ns8250_class); - di->bas.chan = 0; - di->bas.bst = 0; - di->bas.regshft = 0; - di->bas.rclk = 0; - di->baudrate = 115200; - di->databits = 8; - di->stopbits = 1; - di->parity = UART_PARITY_NONE; - - uart_bus_space_io = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR); - uart_bus_space_mem = mips_bus_space_generic; - di->bas.bsh = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR); - return (0); -} Property changes on: head/sys/mips/sentry5/uart_cpu_sbusart.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/sentry5/s5_machdep.c =================================================================== --- head/sys/mips/sentry5/s5_machdep.c (revision 302189) +++ head/sys/mips/sentry5/s5_machdep.c (nonexistent) @@ -1,223 +0,0 @@ -/*- - * Copyright (c) 2007 Bruce M. Simpson. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include "opt_ddb.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#ifdef CFE -#include -#endif - -extern int *edata; -extern int *end; - -void -platform_cpu_init() -{ - /* Nothing special */ -} - -static void -mips_init(void) -{ - int i, j; - - printf("entry: mips_init()\n"); - -#ifdef CFE - /* - * Query DRAM memory map from CFE. - */ - physmem = 0; - for (i = 0; i < 10; i += 2) { - int result; - uint64_t addr, len, type; - - result = cfe_enummem(i, 0, &addr, &len, &type); - if (result < 0) { - phys_avail[i] = phys_avail[i + 1] = 0; - break; - } - if (type != CFE_MI_AVAILABLE) - continue; - - phys_avail[i] = addr; - if (i == 0 && addr == 0) { - /* - * If this is the first physical memory segment probed - * from CFE, omit the region at the start of physical - * memory where the kernel has been loaded. - */ - phys_avail[i] += MIPS_KSEG0_TO_PHYS(kernel_kseg0_end); - } - phys_avail[i + 1] = addr + len; - physmem += len; - } - - realmem = btoc(physmem); -#endif - - for (j = 0; j < i; j++) - dump_avail[j] = phys_avail[j]; - - physmem = realmem; - - init_param1(); - init_param2(physmem); - mips_cpu_init(); - pmap_bootstrap(); - mips_proc0_init(); - mutex_init(); - kdb_init(); -#ifdef KDB - if (boothowto & RB_KDB) - kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); -#endif -} - -void -platform_reset(void) -{ - -#if defined(CFE) - cfe_exit(0, 0); -#else - *((volatile uint8_t *)MIPS_PHYS_TO_KSEG1(SENTRY5_EXTIFADR)) = 0x80; -#endif -} - -void -platform_start(__register_t a0, __register_t a1, __register_t a2, - __register_t a3) -{ - vm_offset_t kernend; - uint64_t platform_counter_freq; - - /* clear the BSS and SBSS segments */ - kernend = (vm_offset_t)&end; - memset(&edata, 0, kernend - (vm_offset_t)(&edata)); - - mips_postboot_fixup(); - - /* Initialize pcpu stuff */ - mips_pcpu0_init(); - -#ifdef CFE - /* - * Initialize CFE firmware trampolines before - * we initialize the low-level console. - * - * CFE passes the following values in registers: - * a0: firmware handle - * a2: firmware entry point - * a3: entry point seal - */ - if (a3 == CFE_EPTSEAL) - cfe_init(a0, a2); -#endif - cninit(); - - mips_init(); - -# if 0 - /* - * Probe the Broadcom Sentry5's on-chip PLL clock registers - * and discover the CPU pipeline clock and bus clock - * multipliers from this. - * XXX: Wrong place. You have to ask the ChipCommon - * or External Interface cores on the SiBa. - */ - uint32_t busmult, cpumult, refclock, clkcfg1; -#define S5_CLKCFG1_REFCLOCK_MASK 0x0000001F -#define S5_CLKCFG1_BUSMULT_MASK 0x000003E0 -#define S5_CLKCFG1_BUSMULT_SHIFT 5 -#define S5_CLKCFG1_CPUMULT_MASK 0xFFFFFC00 -#define S5_CLKCFG1_CPUMULT_SHIFT 10 - - counter_freq = 100000000; /* XXX */ - - clkcfg1 = s5_rd_clkcfg1(); - printf("clkcfg1 = 0x%08x\n", clkcfg1); - - refclock = clkcfg1 & 0x1F; - busmult = ((clkcfg1 & 0x000003E0) >> 5) + 1; - cpumult = ((clkcfg1 & 0xFFFFFC00) >> 10) + 1; - - printf("refclock = %u\n", refclock); - printf("busmult = %u\n", busmult); - printf("cpumult = %u\n", cpumult); - - counter_freq = cpumult * refclock; -# else - platform_counter_freq = 200 * 1000 * 1000; /* Sentry5 is 200MHz */ -# endif - - mips_timer_init_params(platform_counter_freq, 0); -} Property changes on: head/sys/mips/sentry5/s5_machdep.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/sentry5/files.sentry5 =================================================================== --- head/sys/mips/sentry5/files.sentry5 (revision 302189) +++ head/sys/mips/sentry5/files.sentry5 (nonexistent) @@ -1,9 +0,0 @@ -# $FreeBSD$ - -# TODO: Add attachment elsehwere in the tree -# for USB 1.1 OHCI, Ethernet and IPSEC cores -# which are believed to be devices we have drivers for -# which just need to be tweaked for attachment to an SSB system bus. -mips/sentry5/s5_machdep.c standard -mips/mips/intr_machdep.c standard -mips/mips/tick.c standard Property changes on: head/sys/mips/sentry5/files.sentry5 ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/sentry5/obio.c =================================================================== --- head/sys/mips/sentry5/obio.c (revision 302189) +++ head/sys/mips/sentry5/obio.c (nonexistent) @@ -1,183 +0,0 @@ -/* $NetBSD: obio.c,v 1.11 2003/07/15 00:25:05 lukem Exp $ */ - -/*- - * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Jason R. Thorpe for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * On-board device autoconfiguration support for Broadcom Sentry5 - * based boards. - * XXX This is totally bogus and is just enough to get the console hopefully - * running on the sentry5. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include - -int obio_probe(device_t); -int obio_attach(device_t); - -/* - * A bit tricky and hackish. Since we need OBIO to rely - * on PCI we make it pseudo-pci device. But there should - * be only one such device, so we use this static flag - * to prevent false positives on every realPCI device probe. - */ -static int have_one = 0; - -int -obio_probe(device_t dev) -{ - if (!have_one) { - have_one = 1; - return 0; - } - return (ENXIO); -} - -int -obio_attach(device_t dev) -{ - struct obio_softc *sc = device_get_softc(dev); - - sc->oba_st = MIPS_BUS_SPACE_IO; - sc->oba_addr = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR); - sc->oba_size = 0x03FFFFFF; /* XXX sb pci bus 0 aperture size? */ - sc->oba_rman.rm_type = RMAN_ARRAY; - sc->oba_rman.rm_descr = "OBIO I/O"; - if (rman_init(&sc->oba_rman) != 0 || - rman_manage_region(&sc->oba_rman, - sc->oba_addr, sc->oba_addr + sc->oba_size) != 0) - panic("obio_attach: failed to set up I/O rman"); - sc->oba_irq_rman.rm_type = RMAN_ARRAY; - sc->oba_irq_rman.rm_descr = "OBIO IRQ"; - - /* - * This module is intended for UART purposes only and - * it's IRQ is 4 - */ - if (rman_init(&sc->oba_irq_rman) != 0 || - rman_manage_region(&sc->oba_irq_rman, 4, 4) != 0) - panic("obio_attach: failed to set up IRQ rman"); - - device_add_child(dev, "uart", 0); - bus_generic_probe(dev); - bus_generic_attach(dev); - - return (0); -} - -static struct resource * -obio_alloc_resource(device_t bus, device_t child, int type, int *rid, - rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) -{ - struct resource *rv; - struct rman *rm; - bus_space_handle_t bh = 0; - struct obio_softc *sc = device_get_softc(bus); - - switch (type) { - case SYS_RES_IRQ: - rm = &sc->oba_irq_rman; - break; - case SYS_RES_MEMORY: - return (NULL); - case SYS_RES_IOPORT: - rm = &sc->oba_rman; - bh = sc->oba_addr; - start = bh; - break; - default: - return (NULL); - } - - - rv = rman_reserve_resource(rm, start, end, count, flags, child); - if (rv == NULL) - return (NULL); - if (type == SYS_RES_IRQ) - return (rv); - rman_set_rid(rv, *rid); - rman_set_bustag(rv, mips_bus_space_generic); - rman_set_bushandle(rv, bh); - - if (0) { - if (bus_activate_resource(child, type, *rid, rv)) { - rman_release_resource(rv); - return (NULL); - } - } - return (rv); - -} - -static int -obio_activate_resource(device_t bus, device_t child, int type, int rid, - struct resource *r) -{ - return (0); -} -static device_method_t obio_methods[] = { - DEVMETHOD(device_probe, obio_probe), - DEVMETHOD(device_attach, obio_attach), - - DEVMETHOD(bus_alloc_resource, obio_alloc_resource), - DEVMETHOD(bus_activate_resource, obio_activate_resource), - DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), - DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), - - {0, 0}, -}; - -static driver_t obio_driver = { - "obio", - obio_methods, - sizeof(struct obio_softc), -}; -static devclass_t obio_devclass; - -DRIVER_MODULE(obio, pci, obio_driver, obio_devclass, 0, 0); Property changes on: head/sys/mips/sentry5/obio.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/sentry5/uart_bus_sbusart.c =================================================================== --- head/sys/mips/sentry5/uart_bus_sbusart.c (revision 302189) +++ head/sys/mips/sentry5/uart_bus_sbusart.c (nonexistent) @@ -1,95 +0,0 @@ -/*- - * Copyright (c) 2007 Bruce M. Simpson. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * $Id$ - */ -/* - * Skeleton of this file was based on respective code for ARM - * code written by Olivier Houchard. - */ - -/* - * XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is - * experimental and was written for MIPS32 port. - */ -#include "opt_uart.h" - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include - -#include "uart_if.h" - -static int uart_malta_probe(device_t dev); - -extern struct uart_class malta_uart_class; - -static device_method_t uart_malta_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, uart_malta_probe), - DEVMETHOD(device_attach, uart_bus_attach), - DEVMETHOD(device_detach, uart_bus_detach), - { 0, 0 } -}; - -static driver_t uart_malta_driver = { - uart_driver_name, - uart_malta_methods, - sizeof(struct uart_softc), -}; - -extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; -static int -uart_malta_probe(device_t dev) -{ - struct uart_softc *sc; - - sc = device_get_softc(dev); - sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs); - sc->sc_class = &uart_ns8250_class; - bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas)); - sc->sc_sysdev->bas.bst = mips_bus_space_generic; - sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR); - sc->sc_bas.bst = mips_bus_space_generic; - sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR); - return(uart_bus_probe(dev, 0, 0, 0, 0)); -} - -DRIVER_MODULE(uart, obio, uart_malta_driver, uart_devclass, 0, 0); Property changes on: head/sys/mips/sentry5/uart_bus_sbusart.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/sentry5/s5reg.h =================================================================== --- head/sys/mips/sentry5/s5reg.h (revision 302189) +++ head/sys/mips/sentry5/s5reg.h (nonexistent) @@ -1,58 +0,0 @@ -/* $FreeBSD$ */ - -#ifndef _MIPS32_SENTRY5_SENTRY5REG_H_ -#define _MIPS32_SENTRY5_SENTRY5REG_H_ - -#define SENTRY5_UART0ADR 0x18000300 -#define SENTRY5_UART1ADR 0x18000400 - -/* Reset register implemented here in a PLD device. */ -#define SENTRY5_EXTIFADR 0x1F000000 -#define SENTRY5_DORESET 0x80 - -/* - * Custom CP0 register macros. - * XXX: This really needs the mips cpuregs.h file for the barrier. - */ -#define S5_RDRW32_C0P0_CUST22(n,r) \ -static __inline u_int32_t \ -s5_rd_ ## n (void) \ -{ \ - int v0; \ - __asm __volatile ("mfc0 %[v0], $22, "__XSTRING(r)" ;" \ - : [v0] "=&r"(v0)); \ - /*mips_barrier();*/ \ - return (v0); \ -} \ -static __inline void \ -s5_wr_ ## n (u_int32_t a0) \ -{ \ - __asm __volatile ("mtc0 %[a0], $22, "__XSTRING(r)" ;" \ - __XSTRING(COP0_SYNC)";" \ - "nop;" \ - "nop;" \ - : \ - : [a0] "r"(a0)); \ - /*mips_barrier();*/ \ -} struct __hack - -/* - * All 5 of these sub-registers are used by Linux. - * There is a further custom register at 25 which is not used. - */ -#define S5_CP0_DIAG 0 -#define S5_CP0_CLKCFG1 1 -#define S5_CP0_CLKCFG2 2 -#define S5_CP0_SYNC 3 -#define S5_CP0_CLKCFG3 4 -#define S5_CP0_RESET 5 - -/* s5_[rd|wr]_xxx() */ -S5_RDRW32_C0P0_CUST22(diag, S5_CP0_DIAG); -S5_RDRW32_C0P0_CUST22(clkcfg1, S5_CP0_CLKCFG1); -S5_RDRW32_C0P0_CUST22(clkcfg2, S5_CP0_CLKCFG2); -S5_RDRW32_C0P0_CUST22(sync, S5_CP0_SYNC); -S5_RDRW32_C0P0_CUST22(clkcfg3, S5_CP0_CLKCFG3); -S5_RDRW32_C0P0_CUST22(reset, S5_CP0_RESET); - -#endif /* _MIPS32_SENTRY5_SENTRY5REG_H_ */ Property changes on: head/sys/mips/sentry5/s5reg.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/sentry5/obiovar.h =================================================================== --- head/sys/mips/sentry5/obiovar.h (revision 302189) +++ head/sys/mips/sentry5/obiovar.h (nonexistent) @@ -1,58 +0,0 @@ -/* $NetBSD: obiovar.h,v 1.4 2003/06/16 17:40:53 thorpej Exp $ */ - -/*- - * Copyright (c) 2002, 2003 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Jason R. Thorpe for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - * - */ - -#ifndef _SENTRY5_OBIOVAR_H_ -#define _SENTRY5_OBIOVAR_H_ - -#include - -struct obio_softc { - bus_space_tag_t oba_st; /* bus space tag */ - bus_addr_t oba_addr; /* address of device */ - bus_size_t oba_size; /* size of device */ - int oba_width; /* bus width */ - int oba_irq; /* XINT interrupt bit # */ - struct rman oba_rman; - struct rman oba_irq_rman; - -}; -extern struct bus_space obio_bs_tag; - -#endif /* _SENTRY5_OBIOVAR_H_ */ Property changes on: head/sys/mips/sentry5/obiovar.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/sentry5/std.sentry5 =================================================================== --- head/sys/mips/sentry5/std.sentry5 (revision 302189) +++ head/sys/mips/sentry5/std.sentry5 (nonexistent) @@ -1,10 +0,0 @@ -# $FreeBSD$ -# - -machine mips mipsel - -cpu CPU_MIPS4KC -options CPU_SENTRY5 # XXX should this be a - # sub-cpu option? -files "../sentry5/files.sentry5" - Property changes on: head/sys/mips/sentry5/std.sentry5 ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property