Index: head/sys/dev/bhnd/bhnd_bus_if.m =================================================================== --- head/sys/dev/bhnd/bhnd_bus_if.m (revision 302188) +++ head/sys/dev/bhnd/bhnd_bus_if.m (revision 302189) @@ -1,883 +1,889 @@ #- # Copyright (c) 2015 Landon Fuller # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions # are met: # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. # IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, # INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # $FreeBSD$ #include #include #include #include INTERFACE bhnd_bus; # # bhnd(4) bus interface # HEADER { /* forward declarations */ struct bhnd_board_info; struct bhnd_core_info; struct bhnd_chipid; struct bhnd_resource; } CODE { #include #include static struct bhnd_chipid * bhnd_bus_null_get_chipid(device_t dev, device_t child) { panic("bhnd_bus_get_chipid unimplemented"); } + static bhnd_attach_type + bhnd_bus_null_get_attach_type(device_t dev, device_t child) + { + panic("bhnd_bus_get_attach_type unimplemented"); + } + static int bhnd_bus_null_read_board_info(device_t dev, device_t child, struct bhnd_board_info *info) { panic("bhnd_bus_read_boardinfo unimplemented"); } static device_t bhnd_bus_null_find_hostb_device(device_t dev) { panic("bhnd_bus_find_hostb_device unimplemented"); } static bool bhnd_bus_null_is_hw_disabled(device_t dev, device_t child) { panic("bhnd_bus_is_hw_disabled unimplemented"); } static int bhnd_bus_null_get_probe_order(device_t dev, device_t child) { panic("bhnd_bus_get_probe_order unimplemented"); } static int bhnd_bus_null_get_port_rid(device_t dev, device_t child, bhnd_port_type port_type, u_int port, u_int region) { return (-1); } static int bhnd_bus_null_decode_port_rid(device_t dev, device_t child, int type, int rid, bhnd_port_type *port_type, u_int *port, u_int *region) { return (ENOENT); } static int bhnd_bus_null_get_region_addr(device_t dev, device_t child, bhnd_port_type type, u_int port, u_int region, bhnd_addr_t *addr, bhnd_size_t *size) { return (ENOENT); } static int bhnd_bus_null_get_nvram_var(device_t dev, device_t child, const char *name, void *buf, size_t *size) { return (ENODEV); } } /** * Return the active host bridge core for the bhnd bus, if any. * * @param dev The bhnd bus device. * * @retval device_t if a hostb device exists * @retval NULL if no hostb device is found. */ METHOD device_t find_hostb_device { device_t dev; } DEFAULT bhnd_bus_null_find_hostb_device; /** * Return true if the hardware components required by @p child are unpopulated * or otherwise unusable. * * In some cases, enumerated devices may have pins that are left floating, or * the hardware may otherwise be non-functional; this method allows a parent * device to explicitly specify if a successfully enumerated @p child should * be disabled. * * @param dev The device whose child is being examined. * @param child The child device. */ METHOD bool is_hw_disabled { device_t dev; device_t child; } DEFAULT bhnd_bus_null_is_hw_disabled; /** * Return the probe (and attach) order for @p child. * * All devices on the bhnd(4) bus will be probed, attached, or resumed in * ascending order; they will be suspended, shutdown, and detached in * descending order. * * The following device methods will be dispatched in ascending probe order * by the bus: * * - DEVICE_PROBE() * - DEVICE_ATTACH() * - DEVICE_RESUME() * * The following device methods will be dispatched in descending probe order * by the bus: * * - DEVICE_SHUTDOWN() * - DEVICE_DETACH() * - DEVICE_SUSPEND() * * @param dev The device whose child is being examined. * @param child The child device. * * Refer to BHND_PROBE_* and BHND_PROBE_ORDER_* for the standard set of * priorities. */ METHOD int get_probe_order { device_t dev; device_t child; } DEFAULT bhnd_bus_null_get_probe_order; /** * Return the BHND chip identification for the parent bus. * * @param dev The device whose child is being examined. * @param child The child device. */ METHOD const struct bhnd_chipid * get_chipid { device_t dev; device_t child; } DEFAULT bhnd_bus_null_get_chipid; /** * Return the BHND attachment type of the parent bus. * * @param dev The device whose child is being examined. * @param child The child device. * * @retval BHND_ATTACH_ADAPTER if the bus is resident on a bridged adapter, * such as a WiFi chipset. * @retval BHND_ATTACH_NATIVE if the bus provides hardware services (clock, * CPU, etc) to a directly attached native host. */ METHOD bhnd_attach_type get_attach_type { device_t dev; device_t child; -} DEFAULT bhnd_bus_generic_get_attach_type; +} DEFAULT bhnd_bus_null_get_attach_type; /** * Attempt to read the BHND board identification from the parent bus. * * This relies on NVRAM access, and will fail if a valid NVRAM device cannot * be found, or is not yet attached. * * @param dev The parent of @p child. * @param child The bhnd device requesting board info. * @param[out] info On success, will be populated with the bhnd(4) device's * board information. * * @retval 0 success * @retval ENODEV No valid NVRAM source could be found. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ METHOD int read_board_info { device_t dev; device_t child; struct bhnd_board_info *info; } DEFAULT bhnd_bus_null_read_board_info; /** * Reset the device's hardware core. * * @param dev The parent of @p child. * @param child The device to be reset. * @param flags Device-specific core flags to be supplied on reset. * * @retval 0 success * @retval non-zero error */ METHOD int reset_core { device_t dev; device_t child; uint16_t flags; } /** * Suspend a device hardware core. * * @param dev The parent of @p child. * @param child The device to be reset. * * @retval 0 success * @retval non-zero error */ METHOD int suspend_core { device_t dev; device_t child; } /** * Allocate a bhnd resource. * * This method's semantics are functionally identical to the bus API of the same * name; refer to BUS_ALLOC_RESOURCE for complete documentation. */ METHOD struct bhnd_resource * alloc_resource { device_t dev; device_t child; int type; int *rid; rman_res_t start; rman_res_t end; rman_res_t count; u_int flags; } DEFAULT bhnd_bus_generic_alloc_resource; /** * Release a bhnd resource. * * This method's semantics are functionally identical to the bus API of the same * name; refer to BUS_RELEASE_RESOURCE for complete documentation. */ METHOD int release_resource { device_t dev; device_t child; int type; int rid; struct bhnd_resource *res; } DEFAULT bhnd_bus_generic_release_resource; /** * Activate a bhnd resource. * * This method's semantics are functionally identical to the bus API of the same * name; refer to BUS_ACTIVATE_RESOURCE for complete documentation. */ METHOD int activate_resource { device_t dev; device_t child; int type; int rid; struct bhnd_resource *r; } DEFAULT bhnd_bus_generic_activate_resource; /** * Deactivate a bhnd resource. * * This method's semantics are functionally identical to the bus API of the same * name; refer to BUS_DEACTIVATE_RESOURCE for complete documentation. */ METHOD int deactivate_resource { device_t dev; device_t child; int type; int rid; struct bhnd_resource *r; } DEFAULT bhnd_bus_generic_deactivate_resource; /** * Return true if @p region_num is a valid region on @p port_num of * @p type attached to @p child. * * @param dev The device whose child is being examined. * @param child The child device. * @param type The port type being queried. * @param port_num The port number being queried. * @param region_num The region number being queried. */ METHOD bool is_region_valid { device_t dev; device_t child; bhnd_port_type type; u_int port_num; u_int region_num; }; /** * Return the number of ports of type @p type attached to @p child. * * @param dev The device whose child is being examined. * @param child The child device. * @param type The port type being queried. */ METHOD u_int get_port_count { device_t dev; device_t child; bhnd_port_type type; }; /** * Return the number of memory regions mapped to @p child @p port of * type @p type. * * @param dev The device whose child is being examined. * @param child The child device. * @param port The port number being queried. * @param type The port type being queried. */ METHOD u_int get_region_count { device_t dev; device_t child; bhnd_port_type type; u_int port; }; /** * Return the SYS_RES_MEMORY resource-ID for a port/region pair attached to * @p child. * * @param dev The bus device. * @param child The bhnd child. * @param port_type The port type. * @param port_num The index of the child interconnect port. * @param region_num The index of the port-mapped address region. * * @retval -1 No such port/region found. */ METHOD int get_port_rid { device_t dev; device_t child; bhnd_port_type port_type; u_int port_num; u_int region_num; } DEFAULT bhnd_bus_null_get_port_rid; /** * Decode a port / region pair on @p child defined by @p type and @p rid. * * @param dev The bus device. * @param child The bhnd child. * @param type The resource type. * @param rid The resource ID. * @param[out] port_type The port's type. * @param[out] port The port identifier. * @param[out] region The identifier of the memory region on @p port. * * @retval 0 success * @retval non-zero No matching type/rid found. */ METHOD int decode_port_rid { device_t dev; device_t child; int type; int rid; bhnd_port_type *port_type; u_int *port; u_int *region; } DEFAULT bhnd_bus_null_decode_port_rid; /** * Get the address and size of @p region on @p port. * * @param dev The bus device. * @param child The bhnd child. * @param port_type The port type. * @param port The port identifier. * @param region The identifier of the memory region on @p port. * @param[out] region_addr The region's base address. * @param[out] region_size The region's size. * * @retval 0 success * @retval non-zero No matching port/region found. */ METHOD int get_region_addr { device_t dev; device_t child; bhnd_port_type port_type; u_int port; u_int region; bhnd_addr_t *region_addr; bhnd_size_t *region_size; } DEFAULT bhnd_bus_null_get_region_addr; /** * Read an NVRAM variable. * * It is the responsibility of the bus to delegate this request to * the appropriate NVRAM child device, or to a parent bus implementation. * * @param dev The bus device. * @param child The requesting device. * @param name The NVRAM variable name. * @param[out] buf On success, the requested value will be written * to this buffer. This argment may be NULL if * the value is not desired. * @param[in,out] size The capacity of @p buf. On success, will be set * to the actual size of the requested value. * * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval ENOMEM If @p buf is non-NULL and a buffer of @p size is too * small to hold the requested value. * @retval ENODEV No valid NVRAM source could be found. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ METHOD int get_nvram_var { device_t dev; device_t child; const char *name; void *buf; size_t *size; } DEFAULT bhnd_bus_null_get_nvram_var; /** An implementation of bus_read_1() compatible with bhnd_resource */ METHOD uint8_t read_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; } /** An implementation of bus_read_2() compatible with bhnd_resource */ METHOD uint16_t read_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; } /** An implementation of bus_read_4() compatible with bhnd_resource */ METHOD uint32_t read_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; } /** An implementation of bus_write_1() compatible with bhnd_resource */ METHOD void write_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t value; } /** An implementation of bus_write_2() compatible with bhnd_resource */ METHOD void write_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t value; } /** An implementation of bus_write_4() compatible with bhnd_resource */ METHOD void write_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t value; } /** An implementation of bus_read_stream_1() compatible with bhnd_resource */ METHOD uint8_t read_stream_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; } /** An implementation of bus_read_stream_2() compatible with bhnd_resource */ METHOD uint16_t read_stream_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; } /** An implementation of bus_read_stream_4() compatible with bhnd_resource */ METHOD uint32_t read_stream_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; } /** An implementation of bus_write_stream_1() compatible with bhnd_resource */ METHOD void write_stream_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t value; } /** An implementation of bus_write_stream_2() compatible with bhnd_resource */ METHOD void write_stream_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t value; } /** An implementation of bus_write_stream_4() compatible with bhnd_resource */ METHOD void write_stream_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t value; } /** An implementation of bus_read_multi_1() compatible with bhnd_resource */ METHOD void read_multi_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_read_multi_2() compatible with bhnd_resource */ METHOD void read_multi_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_read_multi_4() compatible with bhnd_resource */ METHOD void read_multi_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_write_multi_1() compatible with bhnd_resource */ METHOD void write_multi_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_write_multi_2() compatible with bhnd_resource */ METHOD void write_multi_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_write_multi_4() compatible with bhnd_resource */ METHOD void write_multi_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_read_multi_stream_1() compatible * bhnd_resource */ METHOD void read_multi_stream_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_read_multi_stream_2() compatible * bhnd_resource */ METHOD void read_multi_stream_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_read_multi_stream_4() compatible * bhnd_resource */ METHOD void read_multi_stream_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_write_multi_stream_1() compatible * bhnd_resource */ METHOD void write_multi_stream_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_write_multi_stream_2() compatible with * bhnd_resource */ METHOD void write_multi_stream_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_write_multi_stream_4() compatible with * bhnd_resource */ METHOD void write_multi_stream_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_set_multi_1() compatible with bhnd_resource */ METHOD void set_multi_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t value; bus_size_t count; } /** An implementation of bus_set_multi_2() compatible with bhnd_resource */ METHOD void set_multi_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t value; bus_size_t count; } /** An implementation of bus_set_multi_4() compatible with bhnd_resource */ METHOD void set_multi_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t value; bus_size_t count; } /** An implementation of bus_set_region_1() compatible with bhnd_resource */ METHOD void set_region_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t value; bus_size_t count; } /** An implementation of bus_set_region_2() compatible with bhnd_resource */ METHOD void set_region_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t value; bus_size_t count; } /** An implementation of bus_set_region_4() compatible with bhnd_resource */ METHOD void set_region_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t value; bus_size_t count; } /** An implementation of bus_read_region_1() compatible with bhnd_resource */ METHOD void read_region_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_read_region_2() compatible with bhnd_resource */ METHOD void read_region_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_read_region_4() compatible with bhnd_resource */ METHOD void read_region_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_read_region_stream_1() compatible with * bhnd_resource */ METHOD void read_region_stream_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_read_region_stream_2() compatible with * bhnd_resource */ METHOD void read_region_stream_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_read_region_stream_4() compatible with * bhnd_resource */ METHOD void read_region_stream_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_write_region_1() compatible with bhnd_resource */ METHOD void write_region_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_write_region_2() compatible with bhnd_resource */ METHOD void write_region_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_write_region_4() compatible with bhnd_resource */ METHOD void write_region_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_write_region_stream_1() compatible with * bhnd_resource */ METHOD void write_region_stream_1 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint8_t *datap; bus_size_t count; } /** An implementation of bus_write_region_stream_2() compatible with * bhnd_resource */ METHOD void write_region_stream_2 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint16_t *datap; bus_size_t count; } /** An implementation of bus_write_region_stream_4() compatible with * bhnd_resource */ METHOD void write_region_stream_4 { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; uint32_t *datap; bus_size_t count; } /** An implementation of bus_barrier() compatible with bhnd_resource */ METHOD void barrier { device_t dev; device_t child; struct bhnd_resource *r; bus_size_t offset; bus_size_t length; int flags; } Index: head/sys/dev/bhnd/bhnd_subr.c =================================================================== --- head/sys/dev/bhnd/bhnd_subr.c (revision 302188) +++ head/sys/dev/bhnd/bhnd_subr.c (revision 302189) @@ -1,1179 +1,1161 @@ /*- * Copyright (c) 2015 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include "nvram/bhnd_nvram.h" #include "bhnd_chipc_if.h" #include "bhnd_nvram_if.h" #include "bhnd_nvram_map.h" #include "bhndreg.h" #include "bhndvar.h" static device_t find_nvram_child(device_t dev); /* BHND core device description table. */ static const struct bhnd_core_desc { uint16_t vendor; uint16_t device; bhnd_devclass_t class; const char *desc; } bhnd_core_descs[] = { #define BHND_CDESC(_mfg, _cid, _cls, _desc) \ { BHND_MFGID_ ## _mfg, BHND_COREID_ ## _cid, \ BHND_DEVCLASS_ ## _cls, _desc } BHND_CDESC(BCM, CC, CC, "ChipCommon I/O Controller"), BHND_CDESC(BCM, ILINE20, OTHER, "iLine20 HPNA"), BHND_CDESC(BCM, SRAM, RAM, "SRAM"), BHND_CDESC(BCM, SDRAM, RAM, "SDRAM"), BHND_CDESC(BCM, PCI, PCI, "PCI Bridge"), BHND_CDESC(BCM, MIPS, CPU, "MIPS Core"), BHND_CDESC(BCM, ENET, ENET_MAC, "Fast Ethernet MAC"), BHND_CDESC(BCM, CODEC, OTHER, "V.90 Modem Codec"), BHND_CDESC(BCM, USB, OTHER, "USB 1.1 Device/Host Controller"), BHND_CDESC(BCM, ADSL, OTHER, "ADSL Core"), BHND_CDESC(BCM, ILINE100, OTHER, "iLine100 HPNA"), BHND_CDESC(BCM, IPSEC, OTHER, "IPsec Accelerator"), BHND_CDESC(BCM, UTOPIA, OTHER, "UTOPIA ATM Core"), BHND_CDESC(BCM, PCMCIA, PCCARD, "PCMCIA Bridge"), BHND_CDESC(BCM, SOCRAM, RAM, "Internal Memory"), BHND_CDESC(BCM, MEMC, MEMC, "MEMC SDRAM Controller"), BHND_CDESC(BCM, OFDM, OTHER, "OFDM PHY"), BHND_CDESC(BCM, EXTIF, OTHER, "External Interface"), BHND_CDESC(BCM, D11, WLAN, "802.11 MAC/PHY/Radio"), BHND_CDESC(BCM, APHY, WLAN_PHY, "802.11a PHY"), BHND_CDESC(BCM, BPHY, WLAN_PHY, "802.11b PHY"), BHND_CDESC(BCM, GPHY, WLAN_PHY, "802.11g PHY"), BHND_CDESC(BCM, MIPS33, CPU, "MIPS3302 Core"), BHND_CDESC(BCM, USB11H, OTHER, "USB 1.1 Host Controller"), BHND_CDESC(BCM, USB11D, OTHER, "USB 1.1 Device Core"), BHND_CDESC(BCM, USB20H, OTHER, "USB 2.0 Host Controller"), BHND_CDESC(BCM, USB20D, OTHER, "USB 2.0 Device Core"), BHND_CDESC(BCM, SDIOH, OTHER, "SDIO Host Controller"), BHND_CDESC(BCM, ROBO, OTHER, "RoboSwitch"), BHND_CDESC(BCM, ATA100, OTHER, "Parallel ATA Controller"), BHND_CDESC(BCM, SATAXOR, OTHER, "SATA DMA/XOR Controller"), BHND_CDESC(BCM, GIGETH, ENET_MAC, "Gigabit Ethernet MAC"), BHND_CDESC(BCM, PCIE, PCIE, "PCIe Bridge"), BHND_CDESC(BCM, NPHY, WLAN_PHY, "802.11n 2x2 PHY"), BHND_CDESC(BCM, SRAMC, MEMC, "SRAM Controller"), BHND_CDESC(BCM, MINIMAC, OTHER, "MINI MAC/PHY"), BHND_CDESC(BCM, ARM11, CPU, "ARM1176 CPU"), BHND_CDESC(BCM, ARM7S, CPU, "ARM7TDMI-S CPU"), BHND_CDESC(BCM, LPPHY, WLAN_PHY, "802.11a/b/g PHY"), BHND_CDESC(BCM, PMU, PMU, "PMU"), BHND_CDESC(BCM, SSNPHY, WLAN_PHY, "802.11n Single-Stream PHY"), BHND_CDESC(BCM, SDIOD, OTHER, "SDIO Device Core"), BHND_CDESC(BCM, ARMCM3, CPU, "ARM Cortex-M3 CPU"), BHND_CDESC(BCM, HTPHY, WLAN_PHY, "802.11n 4x4 PHY"), BHND_CDESC(MIPS,MIPS74K, CPU, "MIPS74k CPU"), BHND_CDESC(BCM, GMAC, ENET_MAC, "Gigabit MAC core"), BHND_CDESC(BCM, DMEMC, MEMC, "DDR1/DDR2 Memory Controller"), BHND_CDESC(BCM, PCIERC, OTHER, "PCIe Root Complex"), BHND_CDESC(BCM, OCP, SOC_BRIDGE, "OCP to OCP Bridge"), BHND_CDESC(BCM, SC, OTHER, "Shared Common Core"), BHND_CDESC(BCM, AHB, SOC_BRIDGE, "OCP to AHB Bridge"), BHND_CDESC(BCM, SPIH, OTHER, "SPI Host Controller"), BHND_CDESC(BCM, I2S, OTHER, "I2S Digital Audio Interface"), BHND_CDESC(BCM, DMEMS, MEMC, "SDR/DDR1 Memory Controller"), BHND_CDESC(BCM, UBUS_SHIM, OTHER, "BCM6362/UBUS WLAN SHIM"), BHND_CDESC(BCM, PCIE2, PCIE, "PCIe Bridge (Gen2)"), BHND_CDESC(ARM, APB_BRIDGE, SOC_BRIDGE, "BP135 AMBA3 AXI to APB Bridge"), BHND_CDESC(ARM, PL301, SOC_ROUTER, "PL301 AMBA3 Interconnect"), BHND_CDESC(ARM, EROM, EROM, "PL366 Device Enumeration ROM"), BHND_CDESC(ARM, OOB_ROUTER, OTHER, "PL367 OOB Interrupt Router"), BHND_CDESC(ARM, AXI_UNMAPPED, OTHER, "Unmapped Address Ranges"), BHND_CDESC(BCM, 4706_CC, CC, "ChipCommon I/O Controller"), BHND_CDESC(BCM, NS_PCIE2, PCIE, "PCIe Bridge (Gen2)"), BHND_CDESC(BCM, NS_DMA, OTHER, "DMA engine"), BHND_CDESC(BCM, NS_SDIO, OTHER, "SDIO 3.0 Host Controller"), BHND_CDESC(BCM, NS_USB20H, OTHER, "USB 2.0 Host Controller"), BHND_CDESC(BCM, NS_USB30H, OTHER, "USB 3.0 Host Controller"), BHND_CDESC(BCM, NS_A9JTAG, OTHER, "ARM Cortex A9 JTAG Interface"), BHND_CDESC(BCM, NS_DDR23_MEMC, MEMC, "Denali DDR2/DD3 Memory Controller"), BHND_CDESC(BCM, NS_ROM, NVRAM, "System ROM"), BHND_CDESC(BCM, NS_NAND, NVRAM, "NAND Flash Controller"), BHND_CDESC(BCM, NS_QSPI, NVRAM, "QSPI Flash Controller"), BHND_CDESC(BCM, NS_CC_B, CC_B, "ChipCommon B Auxiliary I/O Controller"), BHND_CDESC(BCM, 4706_SOCRAM, RAM, "Internal Memory"), BHND_CDESC(BCM, IHOST_ARMCA9, CPU, "ARM Cortex A9 CPU"), BHND_CDESC(BCM, 4706_GMAC_CMN, ENET, "Gigabit MAC (Common)"), BHND_CDESC(BCM, 4706_GMAC, ENET_MAC, "Gigabit MAC"), BHND_CDESC(BCM, AMEMC, MEMC, "Denali DDR1/DDR2 Memory Controller"), #undef BHND_CDESC /* Derived from inspection of the BCM4331 cores that provide PrimeCell * IDs. Due to lack of documentation, the surmised device name/purpose * provided here may be incorrect. */ { BHND_MFGID_ARM, BHND_PRIMEID_EROM, BHND_DEVCLASS_OTHER, "PL364 Device Enumeration ROM" }, { BHND_MFGID_ARM, BHND_PRIMEID_SWRAP, BHND_DEVCLASS_OTHER, "PL368 Device Management Interface" }, { BHND_MFGID_ARM, BHND_PRIMEID_MWRAP, BHND_DEVCLASS_OTHER, "PL369 Device Management Interface" }, { 0, 0, 0, NULL } }; /** * Return the name for a given JEP106 manufacturer ID. * * @param vendor A JEP106 Manufacturer ID, including the non-standard ARM 4-bit * JEP106 continuation code. */ const char * bhnd_vendor_name(uint16_t vendor) { switch (vendor) { case BHND_MFGID_ARM: return "ARM"; case BHND_MFGID_BCM: return "Broadcom"; case BHND_MFGID_MIPS: return "MIPS"; default: return "unknown"; } } /** * Return the name of a port type. */ const char * bhnd_port_type_name(bhnd_port_type port_type) { switch (port_type) { case BHND_PORT_DEVICE: return ("device"); case BHND_PORT_BRIDGE: return ("bridge"); case BHND_PORT_AGENT: return ("agent"); default: return "unknown"; } } static const struct bhnd_core_desc * bhnd_find_core_desc(uint16_t vendor, uint16_t device) { for (u_int i = 0; bhnd_core_descs[i].desc != NULL; i++) { if (bhnd_core_descs[i].vendor != vendor) continue; if (bhnd_core_descs[i].device != device) continue; return (&bhnd_core_descs[i]); } return (NULL); } /** * Return a human-readable name for a BHND core. * * @param vendor The core designer's JEDEC-106 Manufacturer ID * @param device The core identifier. */ const char * bhnd_find_core_name(uint16_t vendor, uint16_t device) { const struct bhnd_core_desc *desc; if ((desc = bhnd_find_core_desc(vendor, device)) == NULL) return ("unknown"); return desc->desc; } /** * Return the device class for a BHND core. * * @param vendor The core designer's JEDEC-106 Manufacturer ID * @param device The core identifier. */ bhnd_devclass_t bhnd_find_core_class(uint16_t vendor, uint16_t device) { const struct bhnd_core_desc *desc; if ((desc = bhnd_find_core_desc(vendor, device)) == NULL) return (BHND_DEVCLASS_OTHER); return desc->class; } /** * Return a human-readable name for a BHND core. * * @param ci The core's info record. */ const char * bhnd_core_name(const struct bhnd_core_info *ci) { return bhnd_find_core_name(ci->vendor, ci->device); } /** * Return the device class for a BHND core. * * @param ci The core's info record. */ bhnd_devclass_t bhnd_core_class(const struct bhnd_core_info *ci) { return bhnd_find_core_class(ci->vendor, ci->device); } /** * Initialize a core info record with data from from a bhnd-attached @p dev. * * @param dev A bhnd device. * @param core The record to be initialized. */ struct bhnd_core_info bhnd_get_core_info(device_t dev) { return (struct bhnd_core_info) { .vendor = bhnd_get_vendor(dev), .device = bhnd_get_device(dev), .hwrev = bhnd_get_hwrev(dev), .core_idx = bhnd_get_core_index(dev), .unit = bhnd_get_core_unit(dev) }; } /** * Find a @p class child device with @p unit on @p dev. * * @param parent The bhnd-compatible bus to be searched. * @param class The device class to match on. * @param unit The device unit number; specify -1 to return the first match * regardless of unit number. * * @retval device_t if a matching child device is found. * @retval NULL if no matching child device is found. */ device_t bhnd_find_child(device_t dev, bhnd_devclass_t class, int unit) { struct bhnd_core_match md = { BHND_MATCH_CORE_CLASS(class), BHND_MATCH_CORE_UNIT(unit) }; if (unit == -1) md.m.match.core_unit = 0; return bhnd_match_child(dev, &md); } /** * Find the first child device on @p dev that matches @p desc. * * @param parent The bhnd-compatible bus to be searched. * @param desc A match descriptor. * * @retval device_t if a matching child device is found. * @retval NULL if no matching child device is found. */ device_t bhnd_match_child(device_t dev, const struct bhnd_core_match *desc) { device_t *devlistp; device_t match; int devcnt; int error; error = device_get_children(dev, &devlistp, &devcnt); if (error != 0) return (NULL); match = NULL; for (int i = 0; i < devcnt; i++) { struct bhnd_core_info ci = bhnd_get_core_info(devlistp[i]); if (bhnd_core_matches(&ci, desc)) { match = devlistp[i]; goto done; } } done: free(devlistp, M_TEMP); return match; } /** * Walk up the bhnd device hierarchy to locate the root device * to which the bhndb bridge is attached. * * This can be used from within bhnd host bridge drivers to locate the * actual upstream host device. * * @param dev A bhnd device. * @param bus_class The expected bus (e.g. "pci") to which the bridge root * should be attached. * * @retval device_t if a matching parent device is found. * @retval NULL @p dev is not attached via a bhndb bus * @retval NULL no parent device is attached via @p bus_class. */ device_t bhnd_find_bridge_root(device_t dev, devclass_t bus_class) { devclass_t bhndb_class; device_t parent; KASSERT(device_get_devclass(device_get_parent(dev)) == bhnd_devclass, ("%s not a bhnd device", device_get_nameunit(dev))); bhndb_class = devclass_find("bhndb"); /* Walk the device tree until we hit a bridge */ parent = dev; while ((parent = device_get_parent(parent)) != NULL) { if (device_get_devclass(parent) == bhndb_class) break; } /* No bridge? */ if (parent == NULL) return (NULL); /* Search for a parent attached to the expected bus class */ while ((parent = device_get_parent(parent)) != NULL) { device_t bus; bus = device_get_parent(parent); if (bus != NULL && device_get_devclass(bus) == bus_class) return (parent); } /* Not found */ return (NULL); } /** * Find the first core in @p cores that matches @p desc. * * @param cores The table to search. * @param num_cores The length of @p cores. * @param desc A match descriptor. * * @retval bhnd_core_info if a matching core is found. * @retval NULL if no matching core is found. */ const struct bhnd_core_info * bhnd_match_core(const struct bhnd_core_info *cores, u_int num_cores, const struct bhnd_core_match *desc) { for (u_int i = 0; i < num_cores; i++) { if (bhnd_core_matches(&cores[i], desc)) return &cores[i]; } return (NULL); } /** * Find the first core in @p cores with the given @p class. * * @param cores The table to search. * @param num_cores The length of @p cores. * @param desc A match descriptor. * * @retval bhnd_core_info if a matching core is found. * @retval NULL if no matching core is found. */ const struct bhnd_core_info * bhnd_find_core(const struct bhnd_core_info *cores, u_int num_cores, bhnd_devclass_t class) { struct bhnd_core_match md = { BHND_MATCH_CORE_CLASS(class) }; return bhnd_match_core(cores, num_cores, &md); } /** * Return true if the @p core matches @p desc. * * @param core A bhnd core descriptor. * @param desc A match descriptor to compare against @p core. * * @retval true if @p core matches @p match * @retval false if @p core does not match @p match. */ bool bhnd_core_matches(const struct bhnd_core_info *core, const struct bhnd_core_match *desc) { if (desc->m.match.core_vendor && desc->core_vendor != core->vendor) return (false); if (desc->m.match.core_id && desc->core_id != core->device) return (false); if (desc->m.match.core_unit && desc->core_unit != core->unit) return (false); if (desc->m.match.core_rev && !bhnd_hwrev_matches(core->hwrev, &desc->core_rev)) return (false); if (desc->m.match.core_class && desc->core_class != bhnd_core_class(core)) return (false); return true; } /** * Return true if the @p chip matches @p desc. * * @param chip A bhnd chip identifier. * @param desc A match descriptor to compare against @p chip. * * @retval true if @p chip matches @p match * @retval false if @p chip does not match @p match. */ bool bhnd_chip_matches(const struct bhnd_chipid *chip, const struct bhnd_chip_match *desc) { if (desc->m.match.chip_id && chip->chip_id != desc->chip_id) return (false); if (desc->m.match.chip_pkg && chip->chip_pkg != desc->chip_pkg) return (false); if (desc->m.match.chip_rev && !bhnd_hwrev_matches(chip->chip_rev, &desc->chip_rev)) return (false); return (true); } /** * Return true if the @p board matches @p desc. * * @param board The bhnd board info. * @param desc A match descriptor to compare against @p board. * * @retval true if @p chip matches @p match * @retval false if @p chip does not match @p match. */ bool bhnd_board_matches(const struct bhnd_board_info *board, const struct bhnd_board_match *desc) { if (desc->m.match.board_srom_rev && !bhnd_hwrev_matches(board->board_srom_rev, &desc->board_srom_rev)) return (false); if (desc->m.match.board_vendor && board->board_vendor != desc->board_vendor) return (false); if (desc->m.match.board_type && board->board_type != desc->board_type) return (false); if (desc->m.match.board_rev && !bhnd_hwrev_matches(board->board_rev, &desc->board_rev)) return (false); return (true); } /** * Return true if the @p hwrev matches @p desc. * * @param hwrev A bhnd hardware revision. * @param desc A match descriptor to compare against @p core. * * @retval true if @p hwrev matches @p match * @retval false if @p hwrev does not match @p match. */ bool bhnd_hwrev_matches(uint16_t hwrev, const struct bhnd_hwrev_match *desc) { if (desc->start != BHND_HWREV_INVALID && desc->start > hwrev) return false; if (desc->end != BHND_HWREV_INVALID && desc->end < hwrev) return false; return true; } /** * Return true if the @p dev matches @p desc. * * @param dev A bhnd device. * @param desc A match descriptor to compare against @p dev. * * @retval true if @p dev matches @p match * @retval false if @p dev does not match @p match. */ bool bhnd_device_matches(device_t dev, const struct bhnd_device_match *desc) { struct bhnd_core_info core; const struct bhnd_chipid *chip; struct bhnd_board_info board; device_t parent; int error; /* Construct individual match descriptors */ struct bhnd_core_match m_core = { _BHND_CORE_MATCH_COPY(desc) }; struct bhnd_chip_match m_chip = { _BHND_CHIP_MATCH_COPY(desc) }; struct bhnd_board_match m_board = { _BHND_BOARD_MATCH_COPY(desc) }; /* Fetch and match core info */ if (m_core.m.match_flags) { /* Only applicable to bhnd-attached cores */ parent = device_get_parent(dev); if (device_get_devclass(parent) != bhnd_devclass) { device_printf(dev, "attempting to match core " "attributes against non-core device\n"); return (false); } core = bhnd_get_core_info(dev); if (!bhnd_core_matches(&core, &m_core)) return (false); } /* Fetch and match chip info */ if (m_chip.m.match_flags) { chip = bhnd_get_chipid(dev); if (!bhnd_chip_matches(chip, &m_chip)) return (false); } /* Fetch and match board info. * * This is not available until after NVRAM is up; earlier device * matches should not include board requirements */ if (m_board.m.match_flags) { if ((error = bhnd_read_board_info(dev, &board))) { device_printf(dev, "failed to read required board info " "during device matching: %d\n", error); return (false); } if (!bhnd_board_matches(&board, &m_board)) return (false); } /* All matched */ return (true); } /** * Search @p table for an entry matching @p dev. * * @param dev A bhnd device to match against @p table. * @param table The device table to search. * @param entry_size The @p table entry size, in bytes. * * @retval bhnd_device the first matching device, if any. * @retval NULL if no matching device is found in @p table. */ const struct bhnd_device * bhnd_device_lookup(device_t dev, const struct bhnd_device *table, size_t entry_size) { const struct bhnd_device *entry; device_t hostb, parent; bhnd_attach_type attach_type; uint32_t dflags; parent = device_get_parent(dev); hostb = bhnd_find_hostb_device(parent); attach_type = bhnd_get_attach_type(dev); for (entry = table; !BHND_DEVICE_IS_END(entry); entry = (const struct bhnd_device *) ((const char *) entry + entry_size)) { /* match core info */ if (!bhnd_device_matches(dev, &entry->core)) continue; /* match device flags */ dflags = entry->device_flags; /* hostb implies BHND_ATTACH_ADAPTER requirement */ if (dflags & BHND_DF_HOSTB) dflags |= BHND_DF_ADAPTER; if (dflags & BHND_DF_ADAPTER) if (attach_type != BHND_ATTACH_ADAPTER) continue; if (dflags & BHND_DF_HOSTB) if (dev != hostb) continue; if (dflags & BHND_DF_SOC) if (attach_type != BHND_ATTACH_NATIVE) continue; /* device found */ return (entry); } /* not found */ return (NULL); } /** * Scan the device @p table for all quirk flags applicable to @p dev. * * @param dev A bhnd device to match against @p table. * @param table The device table to search. * * @return returns all matching quirk flags. */ uint32_t bhnd_device_quirks(device_t dev, const struct bhnd_device *table, size_t entry_size) { const struct bhnd_device *dent; const struct bhnd_device_quirk *qent, *qtable; uint32_t quirks; /* Locate the device entry */ if ((dent = bhnd_device_lookup(dev, table, entry_size)) == NULL) return (0); /* Quirks table is optional */ qtable = dent->quirks_table; if (qtable == NULL) return (0); /* Collect matching device quirk entries */ quirks = 0; for (qent = qtable; !BHND_DEVICE_QUIRK_IS_END(qent); qent++) { if (bhnd_device_matches(dev, &qent->desc)) quirks |= qent->quirks; } return (quirks); } /** * Allocate bhnd(4) resources defined in @p rs from a parent bus. * * @param dev The device requesting ownership of the resources. * @param rs A standard bus resource specification. This will be updated * with the allocated resource's RIDs. * @param res On success, the allocated bhnd resources. * * @retval 0 success * @retval non-zero if allocation of any non-RF_OPTIONAL resource fails, * all allocated resources will be released and a regular * unix error code will be returned. */ int bhnd_alloc_resources(device_t dev, struct resource_spec *rs, struct bhnd_resource **res) { /* Initialize output array */ for (u_int i = 0; rs[i].type != -1; i++) res[i] = NULL; for (u_int i = 0; rs[i].type != -1; i++) { res[i] = bhnd_alloc_resource_any(dev, rs[i].type, &rs[i].rid, rs[i].flags); /* Clean up all allocations on failure */ if (res[i] == NULL && !(rs[i].flags & RF_OPTIONAL)) { bhnd_release_resources(dev, rs, res); return (ENXIO); } } return (0); }; /** * Release bhnd(4) resources defined in @p rs from a parent bus. * * @param dev The device that owns the resources. * @param rs A standard bus resource specification previously initialized * by @p bhnd_alloc_resources. * @param res The bhnd resources to be released. */ void bhnd_release_resources(device_t dev, const struct resource_spec *rs, struct bhnd_resource **res) { for (u_int i = 0; rs[i].type != -1; i++) { if (res[i] == NULL) continue; bhnd_release_resource(dev, rs[i].type, rs[i].rid, res[i]); res[i] = NULL; } } /** * Parse the CHIPC_ID_* fields from the ChipCommon CHIPC_ID * register, returning its bhnd_chipid representation. * * @param idreg The CHIPC_ID register value. * @param enum_addr The enumeration address to include in the result. * * @warning * On early siba(4) devices, the ChipCommon core does not provide * a valid CHIPC_ID_NUMCORE field. On these ChipCommon revisions * (see CHIPC_NCORES_MIN_HWREV()), this function will parse and return * an invalid `ncores` value. */ struct bhnd_chipid bhnd_parse_chipid(uint32_t idreg, bhnd_addr_t enum_addr) { struct bhnd_chipid result; /* Fetch the basic chip info */ result.chip_id = CHIPC_GET_BITS(idreg, CHIPC_ID_CHIP); result.chip_pkg = CHIPC_GET_BITS(idreg, CHIPC_ID_PKG); result.chip_rev = CHIPC_GET_BITS(idreg, CHIPC_ID_REV); result.chip_type = CHIPC_GET_BITS(idreg, CHIPC_ID_BUS); result.ncores = CHIPC_GET_BITS(idreg, CHIPC_ID_NUMCORE); result.enum_addr = enum_addr; return (result); } /** * Allocate the resource defined by @p rs via @p dev, use it * to read the ChipCommon ID register relative to @p chipc_offset, * then release the resource. * * @param dev The device owning @p rs. * @param rs A resource spec that encompasses the ChipCommon register block. * @param chipc_offset The offset of the ChipCommon registers within @p rs. * @param[out] result the chip identification data. * * @retval 0 success * @retval non-zero if the ChipCommon identification data could not be read. */ int bhnd_read_chipid(device_t dev, struct resource_spec *rs, bus_size_t chipc_offset, struct bhnd_chipid *result) { struct resource *res; uint32_t reg; int error, rid, rtype; /* Allocate the ChipCommon window resource and fetch the chipid data */ rid = rs->rid; rtype = rs->type; res = bus_alloc_resource_any(dev, rtype, &rid, RF_ACTIVE); if (res == NULL) { device_printf(dev, "failed to allocate bhnd chipc resource\n"); return (ENXIO); } /* Fetch the basic chip info */ reg = bus_read_4(res, chipc_offset + CHIPC_ID); *result = bhnd_parse_chipid(reg, 0x0); /* Fetch the enum base address */ error = 0; switch (result->chip_type) { case BHND_CHIPTYPE_SIBA: result->enum_addr = BHND_DEFAULT_CHIPC_ADDR; break; case BHND_CHIPTYPE_BCMA: case BHND_CHIPTYPE_BCMA_ALT: result->enum_addr = bus_read_4(res, chipc_offset + CHIPC_EROMPTR); break; case BHND_CHIPTYPE_UBUS: device_printf(dev, "unsupported ubus/bcm63xx chip type"); error = ENODEV; goto cleanup; default: device_printf(dev, "unknown chip type %hhu\n", result->chip_type); error = ENODEV; goto cleanup; } cleanup: /* Clean up */ bus_release_resource(dev, rtype, rid, res); return (error); } /** * Using the bhnd(4) bus-level core information and a custom core name, * populate @p dev's device description. * * @param dev A bhnd-bus attached device. * @param dev_name The core's name (e.g. "SDIO Device Core") */ void bhnd_set_custom_core_desc(device_t dev, const char *dev_name) { const char *vendor_name; char *desc; vendor_name = bhnd_get_vendor_name(dev); asprintf(&desc, M_BHND, "%s %s, rev %hhu", vendor_name, dev_name, bhnd_get_hwrev(dev)); if (desc != NULL) { device_set_desc_copy(dev, desc); free(desc, M_BHND); } else { device_set_desc(dev, dev_name); } } /** * Using the bhnd(4) bus-level core information, populate @p dev's device * description. * * @param dev A bhnd-bus attached device. */ void bhnd_set_default_core_desc(device_t dev) { bhnd_set_custom_core_desc(dev, bhnd_get_device_name(dev)); } /** * Helper function for implementing BHND_BUS_IS_HW_DISABLED(). * * If a parent device is available, this implementation delegates the * request to the BHND_BUS_IS_HW_DISABLED() method on the parent of @p dev. * * If no parent device is available (i.e. on a the bus root), the hardware * is assumed to be usable and false is returned. */ bool bhnd_bus_generic_is_hw_disabled(device_t dev, device_t child) { if (device_get_parent(dev) != NULL) return (BHND_BUS_IS_HW_DISABLED(device_get_parent(dev), child)); return (false); } /** * Helper function for implementing BHND_BUS_GET_CHIPID(). * * This implementation delegates the request to the BHND_BUS_GET_CHIPID() * method on the parent of @p dev. If no parent exists, the implementation * will panic. */ const struct bhnd_chipid * bhnd_bus_generic_get_chipid(device_t dev, device_t child) { if (device_get_parent(dev) != NULL) return (BHND_BUS_GET_CHIPID(device_get_parent(dev), child)); panic("missing BHND_BUS_GET_CHIPID()"); } /* nvram board_info population macros for bhnd_bus_generic_read_board_info() */ #define BHND_GV(_dest, _name) \ bhnd_nvram_getvar(child, BHND_NVAR_ ## _name, &_dest, sizeof(_dest)) #define REQ_BHND_GV(_dest, _name) do { \ if ((error = BHND_GV(_dest, _name))) { \ device_printf(dev, \ "error reading " __STRING(_name) ": %d\n", error); \ return (error); \ } \ } while(0) #define OPT_BHND_GV(_dest, _name, _default) do { \ if ((error = BHND_GV(_dest, _name))) { \ if (error != ENOENT) { \ device_printf(dev, \ "error reading " \ __STRING(_name) ": %d\n", error); \ return (error); \ } \ _dest = _default; \ } \ } while(0) /** * Helper function for implementing BHND_BUS_READ_BOARDINFO(). * * This implementation populates @p info with information from NVRAM, * defaulting board_vendor and board_type fields to 0 if the * requested variables cannot be found. * * This behavior is correct for most SoCs, but must be overridden on * bridged (PCI, PCMCIA, etc) devices to produce a complete bhnd_board_info * result. */ int bhnd_bus_generic_read_board_info(device_t dev, device_t child, struct bhnd_board_info *info) { int error; OPT_BHND_GV(info->board_vendor, BOARDVENDOR, 0); OPT_BHND_GV(info->board_type, BOARDTYPE, 0); /* srom >= 2 */ REQ_BHND_GV(info->board_rev, BOARDREV); REQ_BHND_GV(info->board_srom_rev,SROMREV); REQ_BHND_GV(info->board_flags, BOARDFLAGS); OPT_BHND_GV(info->board_flags2, BOARDFLAGS2, 0); /* srom >= 4 */ OPT_BHND_GV(info->board_flags3, BOARDFLAGS3, 0); /* srom >= 11 */ return (0); } #undef BHND_GV #undef BHND_GV_REQ #undef BHND_GV_OPT /** * Find an NVRAM child device on @p dev, if any. * * @retval device_t An NVRAM device. * @retval NULL If no NVRAM device is found. */ static device_t find_nvram_child(device_t dev) { device_t chipc, nvram; /* Look for a directly-attached NVRAM child */ nvram = device_find_child(dev, "bhnd_nvram", 0); if (nvram != NULL) return (nvram); /* Remaining checks are only applicable when searching a bhnd(4) * bus. */ if (device_get_devclass(dev) != bhnd_devclass) return (NULL); /* Look for a ChipCommon-attached NVRAM device */ if ((chipc = bhnd_find_child(dev, BHND_DEVCLASS_CC, -1)) != NULL) { nvram = device_find_child(chipc, "bhnd_nvram", 0); if (nvram != NULL) return (nvram); } /* Not found */ return (NULL); } /** * Helper function for implementing BHND_BUS_GET_NVRAM_VAR(). * * This implementation searches @p dev for a usable NVRAM child device: * - The first child device implementing the bhnd_nvram devclass is * returned, otherwise * - If @p dev is a bhnd(4) bus, a ChipCommon core that advertises an * attached NVRAM source. * * If no usable child device is found on @p dev, the request is delegated to * the BHND_BUS_GET_NVRAM_VAR() method on the parent of @p dev. */ int bhnd_bus_generic_get_nvram_var(device_t dev, device_t child, const char *name, void *buf, size_t *size) { device_t nvram; device_t parent; /* Try to find an NVRAM device applicable to @p child */ if ((nvram = find_nvram_child(dev)) != NULL) return BHND_NVRAM_GETVAR(nvram, name, buf, size); /* Try to delegate to parent */ if ((parent = device_get_parent(dev)) == NULL) return (ENODEV); return (BHND_BUS_GET_NVRAM_VAR(device_get_parent(dev), child, name, buf, size)); } /** * Helper function for implementing BHND_BUS_ALLOC_RESOURCE(). * * This implementation of BHND_BUS_ALLOC_RESOURCE() delegates allocation * of the underlying resource to BUS_ALLOC_RESOURCE(), and activation * to @p dev's BHND_BUS_ACTIVATE_RESOURCE(). */ struct bhnd_resource * bhnd_bus_generic_alloc_resource(device_t dev, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) { struct bhnd_resource *br; struct resource *res; int error; br = NULL; res = NULL; /* Allocate the real bus resource (without activating it) */ res = BUS_ALLOC_RESOURCE(dev, child, type, rid, start, end, count, (flags & ~RF_ACTIVE)); if (res == NULL) return (NULL); /* Allocate our bhnd resource wrapper. */ br = malloc(sizeof(struct bhnd_resource), M_BHND, M_NOWAIT); if (br == NULL) goto failed; br->direct = false; br->res = res; /* Attempt activation */ if (flags & RF_ACTIVE) { error = BHND_BUS_ACTIVATE_RESOURCE(dev, child, type, *rid, br); if (error) goto failed; } return (br); failed: if (res != NULL) BUS_RELEASE_RESOURCE(dev, child, type, *rid, res); free(br, M_BHND); return (NULL); } /** * Helper function for implementing BHND_BUS_RELEASE_RESOURCE(). * * This implementation of BHND_BUS_RELEASE_RESOURCE() delegates release of * the backing resource to BUS_RELEASE_RESOURCE(). */ int bhnd_bus_generic_release_resource(device_t dev, device_t child, int type, int rid, struct bhnd_resource *r) { int error; if ((error = BUS_RELEASE_RESOURCE(dev, child, type, rid, r->res))) return (error); free(r, M_BHND); return (0); } /** * Helper function for implementing BHND_BUS_ACTIVATE_RESOURCE(). * * This implementation of BHND_BUS_ACTIVATE_RESOURCE() simply calls the * BHND_BUS_ACTIVATE_RESOURCE() method of the parent of @p dev. */ int bhnd_bus_generic_activate_resource(device_t dev, device_t child, int type, int rid, struct bhnd_resource *r) { /* Try to delegate to the parent */ if (device_get_parent(dev) != NULL) return (BHND_BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child, type, rid, r)); return (EINVAL); }; /** * Helper function for implementing BHND_BUS_DEACTIVATE_RESOURCE(). * * This implementation of BHND_BUS_ACTIVATE_RESOURCE() simply calls the * BHND_BUS_ACTIVATE_RESOURCE() method of the parent of @p dev. */ int bhnd_bus_generic_deactivate_resource(device_t dev, device_t child, int type, int rid, struct bhnd_resource *r) { if (device_get_parent(dev) != NULL) return (BHND_BUS_DEACTIVATE_RESOURCE(device_get_parent(dev), child, type, rid, r)); return (EINVAL); }; -/** - * Helper function for implementing BHND_BUS_GET_ATTACH_TYPE(). - * - * This implementation of BHND_BUS_GET_ATTACH_TYPE() simply calls the - * BHND_BUS_GET_ATTACH_TYPE() method of the parent of @p dev. - */ -bhnd_attach_type -bhnd_bus_generic_get_attach_type(device_t dev, device_t child) -{ - /* iterate from cores via bhnd to bridge or SoC */ - if (device_get_parent(dev) != NULL) - return (BHND_BUS_GET_ATTACH_TYPE(device_get_parent(dev), - child)); - - panic("bhnd_bus_get_attach_type unimplemented"); - /* Unreachable */ - return (BHND_ATTACH_ADAPTER); -} Index: head/sys/dev/bhnd/cores/chipc/bhnd_chipc_if.m =================================================================== --- head/sys/dev/bhnd/cores/chipc/bhnd_chipc_if.m (revision 302188) +++ head/sys/dev/bhnd/cores/chipc/bhnd_chipc_if.m (revision 302189) @@ -1,125 +1,100 @@ #- # Copyright (c) 2016 Landon Fuller # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions # are met: # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. # IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, # INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # $FreeBSD$ #include #include #include INTERFACE bhnd_chipc; # # bhnd(4) ChipCommon interface. # HEADER { - #include /* forward declarations */ struct chipc_caps; - struct chipc_caps *bhnd_chipc_generic_get_caps(device_t dev); } CODE { - - /** - * Helper function for implementing BHND_CHIPC_GET_CAPS(). - * - * This implementation of BHND_CHIPC_GET_CAPS() simply calls the - * BHND_CHIPC_GET_CAPS() method of the parent of @p dev. - */ - struct chipc_caps* - bhnd_chipc_generic_get_caps(device_t dev) + static struct chipc_caps * + bhnd_chipc_null_get_caps(device_t dev) { - - if (device_get_parent(dev) != NULL) - return (BHND_CHIPC_GET_CAPS(device_get_parent(dev))); - panic("bhnd_chipc_generic_get_caps unimplemented"); - /* Unreachable */ - return (NULL); } - } /** * Write @p value with @p mask directly to the chipctrl register. * * @param dev A bhnd(4) ChipCommon device. * @param value The value to write. * @param mask The mask of bits to be written from @p value. * * Drivers should only use function for functionality that is not * available via another bhnd_chipc() function. * * Currently, the only known valid use-case is in implementing a hardware * work-around for the BCM4321 PCIe rev7 core revision. */ METHOD void write_chipctrl { device_t dev; uint32_t value; uint32_t mask; } /** * Return a borrowed reference to ChipCommon's capability * table. * * @param dev A bhnd(4) ChipCommon device */ METHOD struct chipc_caps * get_caps { device_t dev; -} DEFAULT bhnd_chipc_generic_get_caps; +} DEFAULT bhnd_chipc_null_get_caps; /** * Enable hardware access to the SPROM/OTP source. * * @param sc chipc driver state. * * @retval 0 success * @retval EBUSY If enabling the hardware may conflict with * other active devices. */ METHOD int enable_sprom { device_t dev; } /** * Release hardware access to the SPROM/OTP source. * * @param sc chipc driver state. */ METHOD void disable_sprom { - device_t dev; -} - -/** - * Return the flash configuration register value - * - * @param dev A bhnd(4) ChipCommon device - */ -METHOD uint32_t get_flash_cfg { device_t dev; } Index: head/sys/dev/bhnd/cores/chipc/bhnd_sprom_chipc.c =================================================================== --- head/sys/dev/bhnd/cores/chipc/bhnd_sprom_chipc.c (revision 302188) +++ head/sys/dev/bhnd/cores/chipc/bhnd_sprom_chipc.c (revision 302189) @@ -1,128 +1,111 @@ /*- * Copyright (c) 2015-2016 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); /* * ChipCommon SPROM driver. */ #include #include #include #include #include #include #include #include #include #include #include "bhnd_nvram_if.h" #include "chipcvar.h" #include "chipc_private.h" #define CHIPC_VALID_SPROM_SRC(_src) \ ((_src) == BHND_NVRAM_SRC_SPROM || (_src) == BHND_NVRAM_SRC_OTP) -static void -chipc_sprom_identify(driver_t *driver, device_t parent) -{ - struct chipc_caps *caps; - - caps = BHND_CHIPC_GET_CAPS(parent); - if (!CHIPC_VALID_SPROM_SRC(caps->nvram_src)) - return; - - if (device_find_child(parent, "bhnd_nvram", 0) != NULL) - return; - - if (BUS_ADD_CHILD(parent, 0, "bhnd_nvram", 0) == NULL) - device_printf(parent, "add bhnd_nvram failed\n"); -} - static int chipc_sprom_probe(device_t dev) { struct chipc_caps *caps; device_t chipc; int error; chipc = device_get_parent(dev); caps = BHND_CHIPC_GET_CAPS(chipc); /* Only match on SPROM/OTP devices */ if (!CHIPC_VALID_SPROM_SRC(caps->nvram_src)) return (ENXIO); /* Defer to default driver implementation */ if ((error = bhnd_sprom_probe(dev)) > 0) return (error); return (BUS_PROBE_NOWILDCARD); } static int chipc_sprom_attach(device_t dev) { struct chipc_caps *caps; device_t chipc; int error; chipc = device_get_parent(dev); caps = BHND_CHIPC_GET_CAPS(chipc); /* Request that ChipCommon enable access to SPROM hardware before * delegating attachment (and SPROM parsing) to the common driver */ if ((error = BHND_CHIPC_ENABLE_SPROM(chipc))) return (error); error = bhnd_sprom_attach(dev, caps->sprom_offset); BHND_CHIPC_DISABLE_SPROM(chipc); return (error); } static device_method_t chipc_sprom_methods[] = { /* Device interface */ - DEVMETHOD(device_identify, chipc_sprom_identify), DEVMETHOD(device_probe, chipc_sprom_probe), DEVMETHOD(device_attach, chipc_sprom_attach), DEVMETHOD_END }; DEFINE_CLASS_1(bhnd_nvram, chipc_sprom_driver, chipc_sprom_methods, sizeof(struct bhnd_sprom_softc), bhnd_sprom_driver); DRIVER_MODULE(bhnd_chipc_sprom, bhnd_chipc, chipc_sprom_driver, bhnd_nvram_devclass, NULL, NULL); MODULE_DEPEND(bhnd_chipc_sprom, bhnd, 1, 1, 1); MODULE_DEPEND(bhnd_chipc_sprom, bhnd_chipc, 1, 1, 1); MODULE_DEPEND(bhnd_chipc_sprom, bhnd_sprom, 1, 1, 1); MODULE_VERSION(bhnd_chipc_sprom, 1); Index: head/sys/dev/bhnd/cores/chipc/chipc.c =================================================================== --- head/sys/dev/bhnd/cores/chipc/chipc.c (revision 302188) +++ head/sys/dev/bhnd/cores/chipc/chipc.c (revision 302189) @@ -1,1411 +1,1340 @@ /*- * Copyright (c) 2015-2016 Landon Fuller * Copyright (c) 2016 Michael Zhilin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); /* * Broadcom ChipCommon driver. * * With the exception of some very early chipsets, the ChipCommon core * has been included in all HND SoCs and chipsets based on the siba(4) * and bcma(4) interconnects, providing a common interface to chipset - * identification, bus enumeration, UARTs, clocks, watchdog interrupts, GPIO, - * flash, etc. - * - * The purpose of this driver is memory resource management for ChipCommon drivers - * like UART, PMU, flash. ChipCommon core has several memory regions. - * - * ChipCommon driver has memory resource manager. Driver - * gets information about BHND core ports/regions and map them - * into drivers' resources. - * - * Here is overview of mapping: - * - * ------------------------------------------------------ - * | Port.Region| Purpose | - * ------------------------------------------------------ - * | 0.0 | PMU, SPI(0x40), UART(0x300) | - * | 1.0 | ? | - * | 1.1 | MMIO flash (SPI & CFI) | - * ------------------------------------------------------ + * identification, bus enumeration, UARTs, clocks, watchdog interrupts, + * GPIO, flash, etc. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include "chipcreg.h" #include "chipcvar.h" + #include "chipc_private.h" devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */ static struct bhnd_device_quirk chipc_quirks[]; /* Supported device identifiers */ static const struct bhnd_device chipc_devices[] = { BHND_DEVICE(BCM, CC, NULL, chipc_quirks), BHND_DEVICE_END }; /* Device quirks table */ static struct bhnd_device_quirk chipc_quirks[] = { /* HND OTP controller revisions */ BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */ BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */ BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */ /* IPX OTP controller revisions */ BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX), BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX), BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM), BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT), BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE), /* 4706 variant quirks */ BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */ BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH), /* 4331 quirks*/ BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM), BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM), /* 4360 quirks */ BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), BHND_DEVICE_QUIRK_END }; +// FIXME: IRQ shouldn't be hard-coded +#define CHIPC_MIPS_IRQ 2 -/* - * Here is resource configuration hints for child devices - * - * [Flash] There are 2 flash resources: - * - resource ID (rid) = 0: memory-mapped flash memory - * - resource ID (rid) = 1: memory-mapped flash registers (i.e for SPI) - * - * [UART] Uses IRQ and memory resources: - * - resource ID (rid) = 0: memory-mapped registers - * - IRQ resource ID (rid) = 0: shared IRQ line for Tx/Rx. - */ +static int chipc_add_children(struct chipc_softc *sc); -static const struct chipc_hint { - const char *name; - int unit; - int type; - int rid; - rman_res_t base; /* relative to parent resource */ - rman_res_t size; - u_int port; /* ignored if SYS_RES_IRQ */ - u_int region; -} chipc_hints[] = { - // FIXME: cfg/spi port1.1 mapping on siba(4) SoCs - // FIXME: IRQ shouldn't be hardcoded - /* device unit type rid base size port,region */ - { "bhnd_nvram", 0, SYS_RES_MEMORY, 0, CHIPC_SPROM_OTP, CHIPC_SPROM_OTP_SIZE, 0,0 }, - { "uart", 0, SYS_RES_MEMORY, 0, CHIPC_UART0_BASE, CHIPC_UART_SIZE, 0,0 }, - { "uart", 0, SYS_RES_IRQ, 0, 2, 1 }, - { "uart", 1, SYS_RES_MEMORY, 0, CHIPC_UART1_BASE, CHIPC_UART_SIZE, 0,0 }, - { "uart", 1, SYS_RES_IRQ, 0, 2, 1 }, - { "spi", 0, SYS_RES_MEMORY, 0, 0, RM_MAX_END, 1,1 }, - { "spi", 0, SYS_RES_MEMORY, 1, CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0,0 }, - { "cfi", 0, SYS_RES_MEMORY, 0, 0, RM_MAX_END, 1,1}, - { "cfi", 0, SYS_RES_MEMORY, 1, CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0,0 }, - { NULL } -}; - - -static int chipc_try_activate_resource( - struct chipc_softc *sc, device_t child, - int type, int rid, struct resource *r, - bool req_direct); - static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps); static int chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps); static bool chipc_should_enable_sprom( struct chipc_softc *sc); +static int chipc_try_activate_resource( + struct chipc_softc *sc, device_t child, + int type, int rid, struct resource *r, + bool req_direct); + static int chipc_init_rman(struct chipc_softc *sc); static void chipc_free_rman(struct chipc_softc *sc); static struct rman *chipc_get_rman(struct chipc_softc *sc, int type); /* quirk and capability flag convenience macros */ #define CHIPC_QUIRK(_sc, _name) \ ((_sc)->quirks & CHIPC_QUIRK_ ## _name) #define CHIPC_CAP(_sc, _name) \ ((_sc)->caps._name) #define CHIPC_ASSERT_QUIRK(_sc, name) \ KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) #define CHIPC_ASSERT_CAP(_sc, name) \ KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set")) static int chipc_probe(device_t dev) { const struct bhnd_device *id; id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0])); if (id == NULL) return (ENXIO); bhnd_set_default_core_desc(dev); return (BUS_PROBE_DEFAULT); } static int chipc_attach(device_t dev) { struct chipc_softc *sc; - bhnd_addr_t enum_addr; - uint32_t ccid_reg; - uint8_t chip_type; int error; sc = device_get_softc(dev); sc->dev = dev; sc->quirks = bhnd_device_quirks(dev, chipc_devices, sizeof(chipc_devices[0])); sc->sprom_refcnt = 0; CHIPC_LOCK_INIT(sc); STAILQ_INIT(&sc->mem_regions); /* Set up resource management */ if ((error = chipc_init_rman(sc))) { device_printf(sc->dev, "failed to initialize chipc resource state: %d\n", error); goto failed; } - /* Allocate the region containing our core registers */ + /* Allocate the region containing the chipc register block */ if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) { error = ENXIO; goto failed; } error = chipc_retain_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); if (error) { sc->core_region = NULL; goto failed; - } else { - sc->core = sc->core_region->cr_res; } - /* Fetch our chipset identification data */ - ccid_reg = bhnd_bus_read_4(sc->core, CHIPC_ID); - chip_type = CHIPC_GET_BITS(ccid_reg, CHIPC_ID_BUS); + /* Save a direct reference to our chipc registers */ + sc->core = sc->core_region->cr_res; - switch (chip_type) { - case BHND_CHIPTYPE_SIBA: - /* enumeration space starts at the ChipCommon register base. */ - enum_addr = rman_get_start(sc->core->res); - break; - case BHND_CHIPTYPE_BCMA: - case BHND_CHIPTYPE_BCMA_ALT: - enum_addr = bhnd_bus_read_4(sc->core, CHIPC_EROMPTR); - break; - default: - device_printf(dev, "unsupported chip type %hhu\n", chip_type); - error = ENODEV; - goto failed; - } - - sc->ccid = bhnd_parse_chipid(ccid_reg, enum_addr); - /* Fetch and parse capability register(s) */ if ((error = chipc_read_caps(sc, &sc->caps))) goto failed; if (bootverbose) chipc_print_caps(sc->dev, &sc->caps); - /* Probe and attach children */ - bus_generic_probe(dev); + /* Attach all supported child devices */ + if ((error = chipc_add_children(sc))) + goto failed; + if ((error = bus_generic_attach(dev))) goto failed; return (0); failed: device_delete_children(sc->dev); if (sc->core_region != NULL) { chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); } chipc_free_rman(sc); CHIPC_LOCK_DESTROY(sc); return (error); } static int chipc_detach(device_t dev) { struct chipc_softc *sc; int error; sc = device_get_softc(dev); if ((error = bus_generic_detach(dev))) return (error); chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); chipc_free_rman(sc); CHIPC_LOCK_DESTROY(sc); return (0); } +static int +chipc_add_children(struct chipc_softc *sc) +{ + device_t child; + const char *flash_bus; + int error; + + /* SPROM/OTP */ + if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM || + sc->caps.nvram_src == BHND_NVRAM_SRC_OTP) + { + child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", -1); + if (child == NULL) { + device_printf(sc->dev, "failed to add nvram device\n"); + return (ENXIO); + } + + /* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */ + error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, + CHIPC_SPROM_OTP, CHIPC_SPROM_OTP_SIZE, 0, 0); + if (error) + return (error); + } + +#ifdef notyet + /* + * PMU/SLOWCLK/INSTACLK + * + * On AOB ("Always on Bus") devices, a PMU core (if it exists) is + * enumerated directly by the bhnd(4) bus -- not chipc. + * + * Otherwise, we always add a PMU child device, and let the + * chipc bhnd_pmu drivers probe for it. If the core supports an + * earlier non-PMU clock/power register interface, one of the instaclk, + * powerctl, or null bhnd_pmu drivers will claim the device. + */ + if (!sc->caps.aob || (sc->caps.aob && !sc->caps.pmu)) { + child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", -1); + if (child == NULL) { + device_printf(sc->dev, "failed to add pmu\n"); + return (ENXIO); + } + + /* Associate the applicable register block */ + error = 0; + if (sc->caps.pmu) { + error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, + CHIPC_PMU, CHIPC_PMU_SIZE, 0, 0); + } else if (sc->caps.power_control) { + error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, + CHIPC_PWRCTL, CHIPC_PWRCTL_SIZE, 0, 0); + } + + if (error) + return (error); + + } +#endif /* notyet */ + + /* All remaining devices are SoC-only */ + if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE) + return (0); + + /* UARTs */ + for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) { + child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1); + if (child == NULL) { + device_printf(sc->dev, "failed to add uart%u\n", i); + return (ENXIO); + } + + /* Shared IRQ */ + error = bus_set_resource(child, SYS_RES_IRQ, 0, CHIPC_MIPS_IRQ, + 1); + if (error) { + device_printf(sc->dev, "failed to set uart%u irq %u\n", + i, CHIPC_MIPS_IRQ); + return (error); + } + + /* UART registers are mapped sequentially */ + error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, + CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0); + if (error) + return (error); + } + + /* Flash */ + flash_bus = chipc_flash_bus_name(sc->caps.flash_type); + if (flash_bus != NULL) { + child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, -1); + if (child == NULL) { + device_printf(sc->dev, "failed to add %s device\n", + flash_bus); + return (ENXIO); + } + + /* flash memory mapping */ + error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, + 0, RM_MAX_END, 1, 1); + if (error) + return (error); + + /* flashctrl registers */ + error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 1, + CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0); + if (error) + return (error); + } + + return (0); +} + /** * Determine the NVRAM data source for this device. * * The SPROM, OTP, and flash capability flags must be fully populated in * @p caps. * * @param sc chipc driver state. * @param caps capability flags to be used to derive NVRAM configuration. */ static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps) { uint32_t otp_st, srom_ctrl; /* Very early devices vend SPROM/OTP/CIS (if at all) via the * host bridge interface instead of ChipCommon. */ if (!CHIPC_QUIRK(sc, SUPPORTS_SPROM)) return (BHND_NVRAM_SRC_UNKNOWN); /* * Later chipset revisions standardized the SPROM capability flags and * register interfaces. * * We check for hardware presence in order of precedence. For example, * SPROM is is always used in preference to internal OTP if found. */ if (caps->sprom) { srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL); if (srom_ctrl & CHIPC_SRC_PRESENT) return (BHND_NVRAM_SRC_SPROM); } /* Check for programmed OTP H/W subregion (contains SROM data) */ if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) { /* TODO: need access to HND-OTP device */ if (!CHIPC_QUIRK(sc, OTP_HND)) { device_printf(sc->dev, "NVRAM unavailable: unsupported OTP controller.\n"); return (BHND_NVRAM_SRC_UNKNOWN); } otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST); if (otp_st & CHIPC_OTPS_GUP_HW) return (BHND_NVRAM_SRC_OTP); } /* Check for flash */ if (caps->flash_type != CHIPC_FLASH_NONE) return (BHND_NVRAM_SRC_FLASH); /* No NVRAM hardware capability declared */ return (BHND_NVRAM_SRC_UNKNOWN); } /* Read and parse chipc capabilities */ static int chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps) { uint32_t cap_reg; uint32_t cap_ext_reg; uint32_t regval; /* Fetch cap registers */ cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES); cap_ext_reg = 0; if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT)) cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT); /* Extract values */ caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART); caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB); caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO); caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL); caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS); caps->power_control = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL); caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP); caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL); caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64); caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM); caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU); caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI); caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM); caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE); caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI); caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO); caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB); /* Fetch OTP size for later IPX controller revisions */ if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) { regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE); } /* Determine flash type and parameters */ caps->cfi_width = 0; - switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) { case CHIPC_CAP_SFLASH_ST: caps->flash_type = CHIPC_SFLASH_ST; break; case CHIPC_CAP_SFLASH_AT: caps->flash_type = CHIPC_SFLASH_AT; break; case CHIPC_CAP_NFLASH: + /* unimplemented */ caps->flash_type = CHIPC_NFLASH; break; case CHIPC_CAP_PFLASH: caps->flash_type = CHIPC_PFLASH_CFI; /* determine cfi width */ regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG); if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS)) caps->cfi_width = 2; else caps->cfi_width = 1; break; case CHIPC_CAP_FLASH_NONE: caps->flash_type = CHIPC_FLASH_NONE; break; } /* Handle 4706_NFLASH fallback */ if (CHIPC_QUIRK(sc, 4706_NFLASH) && CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH)) { caps->flash_type = CHIPC_NFLASH_4706; } /* Determine NVRAM source. Must occur after the SPROM/OTP/flash * capability flags have been populated. */ caps->nvram_src = chipc_find_nvram_src(sc, caps); /* Determine the SPROM offset within OTP (if any). SPROM-formatted * data is placed within the OTP general use region. */ caps->sprom_offset = 0; if (caps->nvram_src == BHND_NVRAM_SRC_OTP) { CHIPC_ASSERT_QUIRK(sc, OTP_IPX); /* Bit offset to GUP HW subregion containing SPROM data */ regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP); /* Convert to bytes */ caps->sprom_offset /= 8; } return (0); } static int chipc_suspend(device_t dev) { return (bus_generic_suspend(dev)); } static int chipc_resume(device_t dev) { return (bus_generic_resume(dev)); } static void chipc_probe_nomatch(device_t dev, device_t child) { struct resource_list *rl; const char *name; name = device_get_name(child); if (name == NULL) name = "unknown device"; device_printf(dev, "<%s> at", name); rl = BUS_GET_RESOURCE_LIST(dev, child); if (rl != NULL) { resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); } printf(" (no driver attached)\n"); } static int chipc_print_child(device_t dev, device_t child) { struct resource_list *rl; int retval = 0; retval += bus_print_child_header(dev, child); rl = BUS_GET_RESOURCE_LIST(dev, child); if (rl != NULL) { retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); } retval += bus_print_child_domain(dev, child); retval += bus_print_child_footer(dev, child); return (retval); } static int chipc_child_pnpinfo_str(device_t dev, device_t child, char *buf, size_t buflen) { if (buflen == 0) return (EOVERFLOW); *buf = '\0'; return (0); } static int chipc_child_location_str(device_t dev, device_t child, char *buf, size_t buflen) { if (buflen == 0) return (EOVERFLOW); *buf = '\0'; return (ENXIO); } static device_t chipc_add_child(device_t dev, u_int order, const char *name, int unit) { + struct chipc_softc *sc; struct chipc_devinfo *dinfo; - const struct chipc_hint *hint; device_t child; - devclass_t child_dc; - int error; - int busrel_unit; + sc = device_get_softc(dev); + child = device_add_child_ordered(dev, order, name, unit); if (child == NULL) return (NULL); - /* system-wide device unit */ - unit = device_get_unit(child); - child_dc = device_get_devclass(child); - - busrel_unit = 0; - for (int i = 0; i < unit; i++) { - device_t tmp; - - tmp = devclass_get_device(child_dc, i); - if (tmp != NULL && (device_get_parent(tmp) == dev)) - busrel_unit++; - } - - /* bus-wide device unit (override unit for further hint matching) */ - unit = busrel_unit; - dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT); if (dinfo == NULL) { device_delete_child(dev, child); return (NULL); } resource_list_init(&dinfo->resources); device_set_ivars(child, dinfo); - /* Hint matching requires a device name */ - if (name == NULL) - return (child); - - /* Use hint table to set child resources */ - for (hint = chipc_hints; hint->name != NULL; hint++) { - bhnd_addr_t region_addr; - bhnd_size_t region_size; - - /* Check device name */ - if (strcmp(hint->name, name) != 0) - continue; - - /* Check device unit */ - if (hint->unit >= 0 && unit != hint->unit) - continue; - - switch (hint->type) { - case SYS_RES_IRQ: - /* Add child resource */ - error = bus_set_resource(child, hint->type, hint->rid, - hint->base, hint->size); - if (error) { - device_printf(dev, - "bus_set_resource() failed for %s: %d\n", - device_get_nameunit(child), error); - goto failed; - } - break; - - case SYS_RES_MEMORY: - /* Fetch region address and size */ - error = bhnd_get_region_addr(dev, BHND_PORT_DEVICE, - hint->port, hint->region, ®ion_addr, - ®ion_size); - if (error) { - device_printf(dev, - "lookup of %s%u.%u failed: %d\n", - bhnd_port_type_name(BHND_PORT_DEVICE), - hint->port, hint->region, error); - goto failed; - } - - /* Verify requested range is mappable */ - if (hint->base > region_size || - (hint->size != RM_MAX_END && - (hint->size > region_size || - region_size - hint->base < hint->size ))) - { - device_printf(dev, - "%s%u.%u region cannot map requested range " - "%#jx+%#jx\n", - bhnd_port_type_name(BHND_PORT_DEVICE), - hint->port, hint->region, hint->base, - hint->size); - } - - /* - * Add child resource. If hint doesn't define the end - * of resource window (RX_MAX_END), use end of region. - */ - - error = bus_set_resource(child, - hint->type, - hint->rid, region_addr + hint->base, - (hint->size == RM_MAX_END) ? - region_size - hint->base : - hint->size); - if (error) { - device_printf(dev, - "bus_set_resource() failed for %s: %d\n", - device_get_nameunit(child), error); - goto failed; - } - break; - default: - device_printf(child, "unknown hint resource type: %d\n", - hint->type); - break; - } - } - return (child); - -failed: - device_delete_child(dev, child); - return (NULL); } static void chipc_child_deleted(device_t dev, device_t child) { struct chipc_devinfo *dinfo = device_get_ivars(child); if (dinfo != NULL) { resource_list_free(&dinfo->resources); free(dinfo, M_BHND); } device_set_ivars(child, NULL); } static struct resource_list * chipc_get_resource_list(device_t dev, device_t child) { struct chipc_devinfo *dinfo = device_get_ivars(child); return (&dinfo->resources); } /* Allocate region records for the given port, and add the port's memory * range to the mem_rman */ static int chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type, u_int port) { struct chipc_region *cr; rman_res_t start, end; u_int num_regions; int error; - num_regions = bhnd_get_region_count(sc->dev, port, port); + num_regions = bhnd_get_region_count(sc->dev, type, port); for (u_int region = 0; region < num_regions; region++) { /* Allocate new region record */ cr = chipc_alloc_region(sc, type, port, region); if (cr == NULL) return (ENODEV); /* Can't manage regions that cannot be allocated */ if (cr->cr_rid < 0) { BHND_DEBUG_DEV(sc->dev, "no rid for chipc region " "%s%u.%u", bhnd_port_type_name(type), port, region); chipc_free_region(sc, cr); continue; } /* Add to rman's managed range */ start = cr->cr_addr; end = cr->cr_end; if ((error = rman_manage_region(&sc->mem_rman, start, end))) { chipc_free_region(sc, cr); return (error); } /* Add to region list */ STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link); } return (0); } /* Initialize memory state for all chipc port regions */ static int chipc_init_rman(struct chipc_softc *sc) { u_int num_ports; int error; /* Port types for which we'll register chipc_region mappings */ bhnd_port_type types[] = { BHND_PORT_DEVICE }; /* Initialize resource manager */ sc->mem_rman.rm_start = 0; sc->mem_rman.rm_end = BUS_SPACE_MAXADDR; sc->mem_rman.rm_type = RMAN_ARRAY; sc->mem_rman.rm_descr = "ChipCommon Device Memory"; if ((error = rman_init(&sc->mem_rman))) { device_printf(sc->dev, "could not initialize mem_rman: %d\n", error); return (error); } /* Populate per-port-region state */ for (u_int i = 0; i < nitems(types); i++) { num_ports = bhnd_get_port_count(sc->dev, types[i]); for (u_int port = 0; port < num_ports; port++) { error = chipc_rman_init_regions(sc, types[i], port); if (error) { device_printf(sc->dev, "region init failed for %s%u: %d\n", bhnd_port_type_name(types[i]), port, error); goto failed; } } } return (0); failed: chipc_free_rman(sc); return (error); } /* Free memory management state */ static void chipc_free_rman(struct chipc_softc *sc) { struct chipc_region *cr, *cr_next; STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next) chipc_free_region(sc, cr); rman_fini(&sc->mem_rman); } /** * Return the rman instance for a given resource @p type, if any. * * @param sc The chipc device state. * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...) */ static struct rman * chipc_get_rman(struct chipc_softc *sc, int type) { switch (type) { case SYS_RES_MEMORY: return (&sc->mem_rman); case SYS_RES_IRQ: /* IRQs can be used with RF_SHAREABLE, so we don't perform * any local proxying of resource requests. */ return (NULL); default: return (NULL); }; } static struct resource * chipc_alloc_resource(device_t dev, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) { struct chipc_softc *sc; struct chipc_region *cr; struct resource_list_entry *rle; struct resource *rv; struct rman *rm; int error; bool passthrough, isdefault; sc = device_get_softc(dev); passthrough = (device_get_parent(child) != dev); isdefault = RMAN_IS_DEFAULT_RANGE(start, end); rle = NULL; /* Fetch the resource manager, delegate request if necessary */ rm = chipc_get_rman(sc, type); if (rm == NULL) { /* Requested resource type is delegated to our parent */ rv = bus_generic_rl_alloc_resource(dev, child, type, rid, start, end, count, flags); return (rv); } /* Populate defaults */ if (!passthrough && isdefault) { /* Fetch the resource list entry. */ rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, *rid); if (rle == NULL) { device_printf(dev, "default resource %#x type %d for child %s " "not found\n", *rid, type, device_get_nameunit(child)); return (NULL); } if (rle->res != NULL) { device_printf(dev, "resource entry %#x type %d for child %s is busy " "[%d]\n", *rid, type, device_get_nameunit(child), rman_get_flags(rle->res)); return (NULL); } start = rle->start; end = rle->end; count = ulmax(count, rle->count); } /* Locate a mapping region */ if ((cr = chipc_find_region(sc, start, end)) == NULL) { /* Resource requests outside our shared port regions can be * delegated to our parent. */ rv = bus_generic_rl_alloc_resource(dev, child, type, rid, start, end, count, flags); return (rv); } /* Try to retain a region reference */ if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED))) return (NULL); /* Make our rman reservation */ rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, child); if (rv == NULL) { chipc_release_region(sc, cr, RF_ALLOCATED); return (NULL); } rman_set_rid(rv, *rid); /* Activate */ if (flags & RF_ACTIVE) { error = bus_activate_resource(child, type, *rid, rv); if (error) { device_printf(dev, "failed to activate entry %#x type %d for " "child %s: %d\n", *rid, type, device_get_nameunit(child), error); chipc_release_region(sc, cr, RF_ALLOCATED); rman_release_resource(rv); return (NULL); } } /* Update child's resource list entry */ if (rle != NULL) { rle->res = rv; rle->start = rman_get_start(rv); rle->end = rman_get_end(rv); rle->count = rman_get_size(rv); } return (rv); } static int chipc_release_resource(device_t dev, device_t child, int type, int rid, struct resource *r) { struct chipc_softc *sc; struct chipc_region *cr; struct rman *rm; struct resource_list_entry *rle; int error; sc = device_get_softc(dev); /* Handled by parent bus? */ rm = chipc_get_rman(sc, type); if (rm == NULL || !rman_is_region_manager(r, rm)) { return (bus_generic_rl_release_resource(dev, child, type, rid, r)); } /* Locate the mapping region */ cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); if (cr == NULL) return (EINVAL); /* Deactivate resources */ if (rman_get_flags(r) & RF_ACTIVE) { error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r); if (error) return (error); } if ((error = rman_release_resource(r))) return (error); /* Drop allocation reference */ chipc_release_region(sc, cr, RF_ALLOCATED); /* Clear reference from the resource list entry if exists */ rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid); if (rle != NULL) rle->res = NULL; return (0); } static int chipc_adjust_resource(device_t dev, device_t child, int type, struct resource *r, rman_res_t start, rman_res_t end) { struct chipc_softc *sc; struct chipc_region *cr; struct rman *rm; sc = device_get_softc(dev); /* Handled by parent bus? */ rm = chipc_get_rman(sc, type); if (rm == NULL || !rman_is_region_manager(r, rm)) { return (bus_generic_adjust_resource(dev, child, type, r, start, end)); } /* The range is limited to the existing region mapping */ cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); if (cr == NULL) return (EINVAL); if (end <= start) return (EINVAL); if (start < cr->cr_addr || end > cr->cr_end) return (EINVAL); /* Range falls within the existing region */ return (rman_adjust_resource(r, start, end)); } /** * Retain an RF_ACTIVE reference to the region mapping @p r, and * configure @p r with its subregion values. * * @param sc Driver instance state. * @param child Requesting child device. * @param type resource type of @p r. * @param rid resource id of @p r * @param r resource to be activated. * @param req_direct If true, failure to allocate a direct bhnd resource * will be treated as an error. If false, the resource will not be marked * as RF_ACTIVE if bhnd direct resource allocation fails. */ static int chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type, int rid, struct resource *r, bool req_direct) { struct rman *rm; struct chipc_region *cr; bhnd_size_t cr_offset; rman_res_t r_start, r_end, r_size; int error; rm = chipc_get_rman(sc, type); if (rm == NULL || !rman_is_region_manager(r, rm)) return (EINVAL); r_start = rman_get_start(r); r_end = rman_get_end(r); r_size = rman_get_size(r); /* Find the corresponding chipc region */ cr = chipc_find_region(sc, r_start, r_end); if (cr == NULL) return (EINVAL); /* Calculate subregion offset within the chipc region */ cr_offset = r_start - cr->cr_addr; /* Retain (and activate, if necessary) the chipc region */ if ((error = chipc_retain_region(sc, cr, RF_ACTIVE))) return (error); /* Configure child resource with its subregion values. */ if (cr->cr_res->direct) { error = chipc_init_child_resource(r, cr->cr_res->res, cr_offset, r_size); if (error) goto cleanup; /* Mark active */ if ((error = rman_activate_resource(r))) goto cleanup; } else if (req_direct) { error = ENOMEM; goto cleanup; } return (0); cleanup: chipc_release_region(sc, cr, RF_ACTIVE); return (error); } static int chipc_activate_bhnd_resource(device_t dev, device_t child, int type, int rid, struct bhnd_resource *r) { struct chipc_softc *sc; struct rman *rm; int error; sc = device_get_softc(dev); /* Delegate non-locally managed resources to parent */ rm = chipc_get_rman(sc, type); if (rm == NULL || !rman_is_region_manager(r->res, rm)) { return (bhnd_bus_generic_activate_resource(dev, child, type, rid, r)); } /* Try activating the chipc region resource */ error = chipc_try_activate_resource(sc, child, type, rid, r->res, false); if (error) return (error); /* Mark the child resource as direct according to the returned resource * state */ if (rman_get_flags(r->res) & RF_ACTIVE) r->direct = true; return (0); } static int chipc_activate_resource(device_t dev, device_t child, int type, int rid, struct resource *r) { struct chipc_softc *sc; struct rman *rm; sc = device_get_softc(dev); /* Delegate non-locally managed resources to parent */ rm = chipc_get_rman(sc, type); if (rm == NULL || !rman_is_region_manager(r, rm)) { return (bus_generic_activate_resource(dev, child, type, rid, r)); } /* Try activating the chipc region-based resource */ return (chipc_try_activate_resource(sc, child, type, rid, r, true)); } /** * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE(). */ static int chipc_deactivate_resource(device_t dev, device_t child, int type, int rid, struct resource *r) { struct chipc_softc *sc; struct chipc_region *cr; struct rman *rm; int error; sc = device_get_softc(dev); /* Handled by parent bus? */ rm = chipc_get_rman(sc, type); if (rm == NULL || !rman_is_region_manager(r, rm)) { return (bus_generic_deactivate_resource(dev, child, type, rid, r)); } /* Find the corresponding chipc region */ cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); if (cr == NULL) return (EINVAL); /* Mark inactive */ if ((error = rman_deactivate_resource(r))) return (error); /* Drop associated RF_ACTIVE reference */ chipc_release_region(sc, cr, RF_ACTIVE); return (0); } /** * Examine bus state and make a best effort determination of whether it's * likely safe to enable the muxed SPROM pins. * * On devices that do not use SPROM pin muxing, always returns true. * * @param sc chipc driver state. */ static bool chipc_should_enable_sprom(struct chipc_softc *sc) { device_t *devs; device_t hostb; device_t parent; int devcount; int error; bool result; mtx_assert(&Giant, MA_OWNED); /* for newbus */ /* Nothing to do? */ if (!CHIPC_QUIRK(sc, MUX_SPROM)) return (true); parent = device_get_parent(sc->dev); hostb = bhnd_find_hostb_device(parent); if ((error = device_get_children(parent, &devs, &devcount))) return (false); /* Reject any active devices other than ChipCommon, or the * host bridge (if any). */ result = true; for (int i = 0; i < devcount; i++) { if (devs[i] == hostb || devs[i] == sc->dev) continue; if (!device_is_attached(devs[i])) continue; if (device_is_suspended(devs[i])) continue; /* Active device; assume SPROM is busy */ result = false; break; } free(devs, M_TEMP); return (result); } /** * If required by this device, enable access to the SPROM. * * @param sc chipc driver state. */ static int chipc_enable_sprom_pins(device_t dev) { struct chipc_softc *sc; uint32_t cctrl; int error; sc = device_get_softc(dev); /* Nothing to do? */ if (!CHIPC_QUIRK(sc, MUX_SPROM)) return (0); /* Make sure we're holding Giant for newbus */ mtx_lock(&Giant); CHIPC_LOCK(sc); /* Already enabled? */ if (sc->sprom_refcnt >= 1) { error = 0; goto finished; } /* Check whether bus is busy */ if (!chipc_should_enable_sprom(sc)) { error = EBUSY; goto finished; } cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); /* 4331 devices */ if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN; if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2; bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); error = 0; goto finished; } /* 4360 devices */ if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { /* Unimplemented */ } /* Refuse to proceed on unsupported devices with muxed SPROM pins */ device_printf(sc->dev, "muxed sprom lines on unrecognized device\n"); error = ENXIO; finished: /* Bump the reference count */ if (error == 0) sc->sprom_refcnt++; CHIPC_UNLOCK(sc); mtx_unlock(&Giant); return (error); } /** * If required by this device, revert any GPIO/pin configuration applied * to allow SPROM access. * * @param sc chipc driver state. */ static void chipc_disable_sprom_pins(device_t dev) { struct chipc_softc *sc; uint32_t cctrl; sc = device_get_softc(dev); /* Nothing to do? */ if (!CHIPC_QUIRK(sc, MUX_SPROM)) return; CHIPC_LOCK(sc); /* Check reference count, skip disable if in-use. */ KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease")); sc->sprom_refcnt--; if (sc->sprom_refcnt > 0) goto finished; cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); /* 4331 devices */ if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { cctrl |= CHIPC_CCTRL4331_EXTPA_EN; if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) cctrl |= CHIPC_CCTRL4331_EXTPA_EN2; bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); goto finished; } /* 4360 devices */ if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { /* Unimplemented */ } finished: CHIPC_UNLOCK(sc); } static void chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask) { struct chipc_softc *sc; uint32_t cctrl; sc = device_get_softc(dev); CHIPC_LOCK(sc); cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); cctrl = (cctrl & ~mask) | (value | mask); bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); CHIPC_UNLOCK(sc); } static struct chipc_caps * chipc_get_caps(device_t dev) { struct chipc_softc *sc; sc = device_get_softc(dev); return (&sc->caps); } -static uint32_t -chipc_get_flash_cfg(device_t dev) -{ - struct chipc_softc *sc; - - sc = device_get_softc(dev); - return (bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG)); -} - static device_method_t chipc_methods[] = { /* Device interface */ DEVMETHOD(device_probe, chipc_probe), DEVMETHOD(device_attach, chipc_attach), DEVMETHOD(device_detach, chipc_detach), DEVMETHOD(device_suspend, chipc_suspend), DEVMETHOD(device_resume, chipc_resume), /* Bus interface */ DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch), DEVMETHOD(bus_print_child, chipc_print_child), DEVMETHOD(bus_child_pnpinfo_str, chipc_child_pnpinfo_str), DEVMETHOD(bus_child_location_str, chipc_child_location_str), DEVMETHOD(bus_add_child, chipc_add_child), DEVMETHOD(bus_child_deleted, chipc_child_deleted), DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), DEVMETHOD(bus_alloc_resource, chipc_alloc_resource), DEVMETHOD(bus_release_resource, chipc_release_resource), DEVMETHOD(bus_adjust_resource, chipc_adjust_resource), DEVMETHOD(bus_activate_resource, chipc_activate_resource), DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource), DEVMETHOD(bus_get_resource_list, chipc_get_resource_list), DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), DEVMETHOD(bus_config_intr, bus_generic_config_intr), DEVMETHOD(bus_bind_intr, bus_generic_bind_intr), DEVMETHOD(bus_describe_intr, bus_generic_describe_intr), /* BHND bus inteface */ DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource), /* ChipCommon interface */ DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl), DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom_pins), DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom_pins), DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps), - DEVMETHOD(bhnd_chipc_get_flash_cfg, chipc_get_flash_cfg), DEVMETHOD_END }; DEFINE_CLASS_0(bhnd_chipc, chipc_driver, chipc_methods, sizeof(struct chipc_softc)); EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, chipc_driver, bhnd_chipc_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1); MODULE_VERSION(bhnd_chipc, 1); Index: head/sys/dev/bhnd/cores/chipc/chipc_cfi.c =================================================================== --- head/sys/dev/bhnd/cores/chipc/chipc_cfi.c (revision 302188) +++ head/sys/dev/bhnd/cores/chipc/chipc_cfi.c (revision 302189) @@ -1,141 +1,89 @@ /*- * Copyright (c) 2016 Michael Zhilin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include -#include #include #include "bhnd_chipc_if.h" -#include "chipc_slicer.h" + #include "chipcreg.h" #include "chipcvar.h" +#include "chipc_slicer.h" -/* - * **************************** PROTOTYPES **************************** - */ - -static void chipc_cfi_identify(driver_t *driver, device_t parent); -static int chipc_cfi_probe(device_t dev); -static int chipc_cfi_attach(device_t dev); - -/* - * **************************** IMPLEMENTATION ************************ - */ - -static void -chipc_cfi_identify(driver_t *driver, device_t parent) -{ - struct chipc_caps *caps; - - if (device_find_child(parent, cfi_driver_name, -1) != NULL) - return; - - caps = BHND_CHIPC_GET_CAPS(parent); - if (caps == NULL) - return; - - if (caps->flash_type != CHIPC_PFLASH_CFI) - return; - - BUS_ADD_CHILD(parent, 0, cfi_driver_name, -1); - return; -} - static int chipc_cfi_probe(device_t dev) { - int error; - int enabled; - int byteswap; - uint32_t flash_config; struct cfi_softc *sc; + int error; sc = device_get_softc(dev); - flash_config = BHND_CHIPC_GET_FLASH_CFG(device_get_parent(dev)); - - enabled = (flash_config & CHIPC_CF_EN); - byteswap = (flash_config & CHIPC_CF_BS); - - if (enabled == 0) - device_disable(dev); - - BHND_DEBUG_DEV(dev, "trying attach flash enabled=%d swapbytes=%d", - enabled, byteswap); - sc->sc_width = 0; - error = cfi_probe(dev); - if (error == 0) - device_set_desc(dev, "ChipCommon CFI"); + if ((error = cfi_probe(dev)) > 0) + return (error); + + device_set_desc(dev, "Broadcom ChipCommon CFI"); return (error); } static int chipc_cfi_attach(device_t dev) { - int error; - - error = cfi_attach(dev); - if (error) - return (error); - - flash_register_slicer(chipc_slicer_cfi); - return (0); + chipc_register_slicer(CHIPC_PFLASH_CFI); + return (cfi_attach(dev)); } static device_method_t chipc_cfi_methods[] = { /* device interface */ - DEVMETHOD(device_identify, chipc_cfi_identify), DEVMETHOD(device_probe, chipc_cfi_probe), DEVMETHOD(device_attach, chipc_cfi_attach), DEVMETHOD(device_detach, cfi_detach), {0, 0} }; static driver_t chipc_cfi_driver = { cfi_driver_name, chipc_cfi_methods, sizeof(struct cfi_softc), }; DRIVER_MODULE(cfi, bhnd_chipc, chipc_cfi_driver, cfi_devclass, 0, 0); - Index: head/sys/dev/bhnd/cores/chipc/chipc_private.h =================================================================== --- head/sys/dev/bhnd/cores/chipc/chipc_private.h (revision 302188) +++ head/sys/dev/bhnd/cores/chipc/chipc_private.h (revision 302189) @@ -1,100 +1,105 @@ /*- * Copyright (c) 2015-2016 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. * * $FreeBSD$ */ #ifndef _BHND_CORES_CHIPC_CHIPC_PRIVATE_H_ #define _BHND_CORES_CHIPC_CHIPC_PRIVATE_H_ #include #include #include #include #include #include #include #include /* * Private bhnd_chipc(4) driver definitions. */ struct chipc_caps; struct chipc_region; struct chipc_softc; int chipc_init_child_resource(struct resource *r, struct resource *parent, bhnd_size_t offset, bhnd_size_t size); +int chipc_set_resource(struct chipc_softc *sc, + device_t child, int type, int rid, + rman_res_t start, rman_res_t count, u_int port, + u_int region); + struct chipc_region *chipc_alloc_region(struct chipc_softc *sc, bhnd_port_type type, u_int port, u_int region); void chipc_free_region(struct chipc_softc *sc, struct chipc_region *cr); struct chipc_region *chipc_find_region(struct chipc_softc *sc, rman_res_t start, rman_res_t end); struct chipc_region *chipc_find_region_by_rid(struct chipc_softc *sc, int rid); int chipc_retain_region(struct chipc_softc *sc, struct chipc_region *cr, int flags); int chipc_release_region(struct chipc_softc *sc, struct chipc_region *cr, int flags); void chipc_print_caps(device_t dev, struct chipc_caps *caps); /** * chipc SYS_RES_MEMORY region allocation record. */ struct chipc_region { bhnd_port_type cr_port_type; /**< bhnd port type */ u_int cr_port_num; /**< bhnd port number */ u_int cr_region_num; /**< bhnd region number */ bhnd_addr_t cr_addr; /**< region base address */ bhnd_addr_t cr_end; /**< region end address */ bhnd_size_t cr_count; /**< region count */ int cr_rid; /**< rid to use when performing resource allocation, or -1 if region has no assigned resource ID */ struct bhnd_resource *cr_res; /**< bus resource, or NULL */ int cr_res_rid; /**< cr_res RID, if any. */ u_int cr_refs; /**< RF_ALLOCATED refcount */ u_int cr_act_refs; /**< RF_ACTIVE refcount */ STAILQ_ENTRY(chipc_region) cr_link; }; #endif /* _BHND_CORES_CHIPC_CHIPC_PRIVATE_H_ */ Index: head/sys/dev/bhnd/cores/chipc/chipc_slicer.c =================================================================== --- head/sys/dev/bhnd/cores/chipc/chipc_slicer.c (revision 302188) +++ head/sys/dev/bhnd/cores/chipc/chipc_slicer.c (revision 302189) @@ -1,172 +1,202 @@ /*- * Copyright (c) 2016 Michael Zhilin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); /* * Slicer is required to split firmware images into pieces. * The first supported FW is TRX-based used by Asus routers * TODO: add NetGear FW (CHK) */ #include #include #include #include #include #include #include #include #include #include #include "chipc_slicer.h" #include #include "chipc_spi.h" -static int chipc_slicer_walk(device_t dev, struct resource* res, +static int chipc_slicer_walk(device_t dev, struct resource *res, struct flash_slice *slices, int *nslices); +void +chipc_register_slicer(chipc_flash flash_type) +{ + switch (flash_type) { + case CHIPC_SFLASH_AT: + case CHIPC_SFLASH_ST: + flash_register_slicer(chipc_slicer_spi); + break; + case CHIPC_PFLASH_CFI: + flash_register_slicer(chipc_slicer_cfi); + break; + default: + /* Unsupported */ + break; + } +} + int chipc_slicer_cfi(device_t dev, struct flash_slice *slices, int *nslices) { struct cfi_softc *sc; + device_t parent; - if (strcmp("cfi", device_get_name(dev)) != 0) - return (0); + /* must be CFI flash */ + if (device_get_devclass(dev) != devclass_find("cfi")) + return (ENXIO); - sc = device_get_softc(dev); + /* must be attached to chipc */ + if ((parent = device_get_parent(dev)) == NULL) { + BHND_ERROR_DEV(dev, "no found ChipCommon device"); + return (ENXIO); + } + if (device_get_devclass(parent) != devclass_find("bhnd_chipc")) { + BHND_ERROR_DEV(dev, "no found ChipCommon device"); + return (ENXIO); + } + + sc = device_get_softc(dev); return (chipc_slicer_walk(dev, sc->sc_res, slices, nslices)); } int chipc_slicer_spi(device_t dev, struct flash_slice *slices, int *nslices) { - /* flash(mx25l) <- spibus <- chipc_spi */ - device_t spibus; - device_t chipc_spi; struct chipc_spi_softc *sc; + device_t chipc, spi, spibus; BHND_DEBUG_DEV(dev, "initting SPI slicer: %s", device_get_name(dev)); - if (strcmp("mx25l", device_get_name(dev)) != 0) - return (EINVAL); - + /* must be SPI-attached flash */ spibus = device_get_parent(dev); if (spibus == NULL) { BHND_ERROR_DEV(dev, "no found ChipCommon SPI BUS device"); - return (EINVAL); + return (ENXIO); } - chipc_spi = device_get_parent(spibus); - if (chipc_spi == NULL) { - BHND_ERROR_DEV(spibus, "no found ChipCommon SPI device"); - return (EINVAL); + spi = device_get_parent(spibus); + if (spi == NULL) { + BHND_ERROR_DEV(dev, "no found ChipCommon SPI device"); + return (ENXIO); } - sc = device_get_softc(chipc_spi); + chipc = device_get_parent(spi); + if (device_get_devclass(chipc) != devclass_find("bhnd_chipc")) { + BHND_ERROR_DEV(dev, "no found ChipCommon device"); + return (ENXIO); + } - return (chipc_slicer_walk(dev, sc->sc_res, slices, nslices)); + sc = device_get_softc(spi); + return (chipc_slicer_walk(dev, sc->sc_flash_res, slices, nslices)); } /* * Main processing part */ static int -chipc_slicer_walk(device_t dev, struct resource* res, - struct flash_slice *slices, int *nslices) +chipc_slicer_walk(device_t dev, struct resource *res, + struct flash_slice *slices, int *nslices) { uint32_t fw_len; uint32_t fs_ofs; uint32_t val; uint32_t ofs_trx; int flash_size; *nslices = 0; flash_size = rman_get_size(res); ofs_trx = flash_size; BHND_TRACE_DEV(dev, "slicer: scanning memory [%x bytes] for headers...", flash_size); /* Find FW header in flash memory with step=128Kb (0x1000) */ for(uint32_t ofs = 0; ofs < flash_size; ofs+= 0x1000){ val = bus_read_4(res, ofs); switch (val) { case TRX_MAGIC: /* check for second TRX */ if (ofs_trx < ofs) { BHND_TRACE_DEV(dev, "stop on 2nd TRX: %x", ofs); break; } BHND_TRACE("TRX found: %x", ofs); ofs_trx = ofs; /* read last offset of TRX header */ fs_ofs = bus_read_4(res, ofs + 24); BHND_TRACE("FS offset: %x", fs_ofs); /* * GEOM IO will panic if offset is not aligned * on sector size, i.e. 512 bytes */ if (fs_ofs % 0x200 != 0) { BHND_WARN("WARNING! filesystem offset should be" " aligned on sector size (%d bytes)", 0x200); BHND_WARN("ignoring TRX firmware image"); break; } slices[*nslices].base = ofs + fs_ofs; //XXX: fully sized? any other partition? fw_len = bus_read_4(res, ofs + 4); slices[*nslices].size = fw_len - fs_ofs; slices[*nslices].label = "rootfs"; *nslices += 1; break; case CFE_MAGIC: BHND_TRACE("CFE found: %x", ofs); break; case NVRAM_MAGIC: BHND_TRACE("NVRAM found: %x", ofs); break; default: break; } } BHND_TRACE("slicer: done"); return (0); } Index: head/sys/dev/bhnd/cores/chipc/chipc_slicer.h =================================================================== --- head/sys/dev/bhnd/cores/chipc/chipc_slicer.h (revision 302188) +++ head/sys/dev/bhnd/cores/chipc/chipc_slicer.h (revision 302189) @@ -1,46 +1,49 @@ /*- * Copyright (c) 2016 Michael Zhilin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. * * $FreeBSD$ */ #ifndef _BHND_CORES_CHIPC_CHIPC_SLICER_H_ #define _BHND_CORES_CHIPC_CHIPC_SLICER_H_ #include +#include "chipcvar.h" + #define TRX_MAGIC 0x30524448 #define CFE_MAGIC 0x43464531 #define NVRAM_MAGIC 0x48534C46 +void chipc_register_slicer(chipc_flash flash_type); int chipc_slicer_spi(device_t dev, struct flash_slice *slices, int *nslices); int chipc_slicer_cfi(device_t dev, struct flash_slice *slices, int *nslices); #endif /* _BHND_CORES_CHIPC_CHIPC_SLICER_H_ */ Index: head/sys/dev/bhnd/cores/chipc/chipc_spi.c =================================================================== --- head/sys/dev/bhnd/cores/chipc/chipc_spi.c (revision 302188) +++ head/sys/dev/bhnd/cores/chipc/chipc_spi.c (revision 302189) @@ -1,280 +1,278 @@ /*- * Copyright (c) 2016 Michael Zhilin + * Copyright (c) 2016 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include -/* - * SPI BUS interface - */ + #include +#include "bhnd_chipc_if.h" + #include "spibus_if.h" #include "chipcreg.h" #include "chipcvar.h" -#include "chipc_spi.h" -#include "bhnd_chipc_if.h" - -/* - * Flash slicer - */ #include "chipc_slicer.h" -/* - * **************************** PROTOTYPES **************************** - */ +#include "chipc_spi.h" -static void chipc_spi_identify(driver_t *driver, device_t parent); static int chipc_spi_probe(device_t dev); static int chipc_spi_attach(device_t dev); +static int chipc_spi_detach(device_t dev); static int chipc_spi_transfer(device_t dev, device_t child, struct spi_command *cmd); static int chipc_spi_txrx(struct chipc_spi_softc *sc, uint8_t in, uint8_t* out); static int chipc_spi_wait(struct chipc_spi_softc *sc); -/* - * **************************** IMPLEMENTATION ************************ - */ +static int +chipc_spi_probe(device_t dev) +{ + device_set_desc(dev, "Broadcom ChipCommon SPI"); + return (BUS_PROBE_NOWILDCARD); +} -static void -chipc_spi_identify(driver_t *driver, device_t parent) +static int +chipc_spi_attach(device_t dev) { - struct chipc_caps *caps; - device_t spidev; - device_t spibus; - device_t flash; - char* flash_name; - int err; + struct chipc_spi_softc *sc; + struct chipc_caps *ccaps; + device_t flash_dev; + device_t spibus; + const char *flash_name; + int error; - flash_name = NULL; + sc = device_get_softc(dev); - if (device_find_child(parent, "spi", -1) != NULL) - return; - - caps = BHND_CHIPC_GET_CAPS(parent); - if (caps == NULL) { - BHND_ERROR_DEV(parent, "can't retrieve ChipCommon capabilities"); - return; + /* Allocate SPI controller registers */ + sc->sc_rid = 1; + sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, + RF_ACTIVE); + if (sc->sc_res == NULL) { + device_printf(dev, "failed to allocate device registers\n"); + return (ENXIO); } - switch (caps->flash_type) { - case CHIPC_SFLASH_AT: - flash_name = "at45d"; - break; - case CHIPC_SFLASH_ST: - flash_name = "mx25l"; - break; - default: - return; + /* Allocate flash shadow region */ + sc->sc_flash_rid = 0; + sc->sc_flash_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, + &sc->sc_flash_rid, RF_ACTIVE); + if (sc->sc_flash_res == NULL) { + device_printf(dev, "failed to allocate flash region\n"); + error = ENXIO; + goto failed; } - spidev = BUS_ADD_CHILD(parent, 0, "spi", -1); - if (spidev == NULL) { - BHND_ERROR_DEV(parent, "can't add chipc_spi to ChipCommon"); - return; + /* + * Add flash device + * + * XXX: This should be replaced with a DEVICE_IDENTIFY implementation + * in chipc-specific subclasses of the mx25l and at45d drivers. + */ + if ((spibus = device_add_child(dev, "spibus", -1)) == NULL) { + device_printf(dev, "failed to add spibus\n"); + error = ENXIO; + goto failed; } - err = device_probe_and_attach(spidev); - if (err) { - BHND_ERROR_DEV(spidev, "failed attach chipc_spi: %d", err); - return; - } + /* Let spibus perform full attach before we try to call + * BUS_ADD_CHILD() */ + if ((error = bus_generic_attach(dev))) + goto failed; - spibus = device_find_child(spidev, "spibus", -1); - if (spibus == NULL) { - BHND_ERROR_DEV(spidev, "can't find spibus under chipc_spi"); - return; - } + /* Determine flash type and add the flash child */ + ccaps = BHND_CHIPC_GET_CAPS(device_get_parent(dev)); + flash_name = chipc_sflash_device_name(ccaps->flash_type); + if (flash_name != NULL) { + flash_dev = BUS_ADD_CHILD(spibus, 0, flash_name, -1); + if (flash_dev == NULL) { + device_printf(dev, "failed to add %s\n", flash_name); + error = ENXIO; + goto failed; + } - flash = BUS_ADD_CHILD(spibus, 0, flash_name, -1); - if (flash == NULL) { - BHND_ERROR_DEV(spibus, "can't add %s to spibus", flash_name); - return; + chipc_register_slicer(ccaps->flash_type); + + if ((error = device_probe_and_attach(flash_dev))) { + device_printf(dev, "failed to attach %s: %d\n", + flash_name, error); + goto failed; + } } - err = device_probe_and_attach(flash); - if (err) - BHND_ERROR_DEV(flash, "failed attach flash %s: %d", flash_name, - err); + return (0); - return; -} +failed: + device_delete_children(dev); -static int -chipc_spi_probe(device_t dev) -{ - device_set_desc(dev, "ChipCommon SPI"); - return (BUS_PROBE_DEFAULT); -} + if (sc->sc_res != NULL) + bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, + sc->sc_res); -struct resource_spec spec_mem[] = { - {SYS_RES_MEMORY, 0, RF_ACTIVE}, - {SYS_RES_MEMORY, 1, RF_ACTIVE}, - { -1, -1, 0 } - }; + if (sc->sc_flash_res != NULL) + bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_flash_rid, + sc->sc_flash_res); + return (error); +} + static int -chipc_spi_attach(device_t dev) +chipc_spi_detach(device_t dev) { - int err; struct chipc_spi_softc *sc; - struct resource *mem[2]; + int error; sc = device_get_softc(dev); - err = bus_alloc_resources(dev, spec_mem, mem); - if (err != 0) - return (ENXIO); - sc->sc_res = mem[0]; - sc->sc_mem_res = mem[1]; + if ((error = bus_generic_detach(dev))) + return (error); - flash_register_slicer(chipc_slicer_spi); - device_add_child(dev, "spibus", 0); - return (bus_generic_attach(dev)); + bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_res); + bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_flash_rid, + sc->sc_flash_res); + return (0); } static int chipc_spi_wait(struct chipc_spi_softc *sc) { int i; for (i = CHIPC_SPI_MAXTRIES; i > 0; i--) if (!(SPI_READ(sc, CHIPC_SPI_FLASHCTL) & CHIPC_SPI_FLASHCTL_START)) break; if (i > 0) return (0); - BHND_DEBUG_DEV(sc->dev, "busy"); + BHND_DEBUG_DEV(sc->sc_dev, "busy"); return (-1); } static int chipc_spi_txrx(struct chipc_spi_softc *sc, uint8_t out, uint8_t* in) { uint32_t ctl; ctl = CHIPC_SPI_FLASHCTL_START | CHIPC_SPI_FLASHCTL_CSACTIVE | out; SPI_BARRIER_WRITE(sc); SPI_WRITE(sc, CHIPC_SPI_FLASHCTL, ctl); SPI_BARRIER_WRITE(sc); if (chipc_spi_wait(sc)) return (-1); *in = SPI_READ(sc, CHIPC_SPI_FLASHDATA) & 0xff; return (0); } static int chipc_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct chipc_spi_softc *sc; uint8_t *buf_in; uint8_t *buf_out; int i; sc = device_get_softc(dev); KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("TX/RX command sizes should be equal")); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("TX/RX data sizes should be equal")); if (cmd->tx_cmd_sz == 0) { BHND_DEBUG_DEV(child, "size of command is ZERO"); return (EIO); } SPI_BARRIER_WRITE(sc); SPI_WRITE(sc, CHIPC_SPI_FLASHADDR, 0); SPI_BARRIER_WRITE(sc); /* * Transfer command */ buf_out = (uint8_t *)cmd->tx_cmd; buf_in = (uint8_t *)cmd->rx_cmd; for (i = 0; i < cmd->tx_cmd_sz; i++) if (chipc_spi_txrx(sc, buf_out[i], &(buf_in[i]))) return (EIO); /* * Receive/transmit data */ buf_out = (uint8_t *)cmd->tx_data; buf_in = (uint8_t *)cmd->rx_data; for (i = 0; i < cmd->tx_data_sz; i++) if (chipc_spi_txrx(sc, buf_out[i], &(buf_in[i]))) return (EIO); /* * Clear CS bit and whole control register */ SPI_BARRIER_WRITE(sc); SPI_WRITE(sc, CHIPC_SPI_FLASHCTL, 0); SPI_BARRIER_WRITE(sc); return (0); } -/* - * **************************** METADATA ************************ - */ static device_method_t chipc_spi_methods[] = { - DEVMETHOD(device_identify, chipc_spi_identify), DEVMETHOD(device_probe, chipc_spi_probe), DEVMETHOD(device_attach, chipc_spi_attach), + DEVMETHOD(device_detach, chipc_spi_detach), + /* SPI */ DEVMETHOD(spibus_transfer, chipc_spi_transfer), DEVMETHOD_END }; static driver_t chipc_spi_driver = { "spi", chipc_spi_methods, sizeof(struct chipc_spi_softc), }; static devclass_t chipc_spi_devclass; DRIVER_MODULE(chipc_spi, bhnd_chipc, chipc_spi_driver, chipc_spi_devclass, - 0, 0); + 0, 0); Index: head/sys/dev/bhnd/cores/chipc/chipc_spi.h =================================================================== --- head/sys/dev/bhnd/cores/chipc/chipc_spi.h (revision 302188) +++ head/sys/dev/bhnd/cores/chipc/chipc_spi.h (revision 302189) @@ -1,94 +1,92 @@ /*- * Copyright (c) 2016 Michael Zhilin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ /* * $FreeBSD$ */ #ifndef _BHND_CORES_CHIPC_CHIPC_SPI_H_ #define _BHND_CORES_CHIPC_CHIPC_SPI_H_ #define CHIPC_SPI_MAXTRIES 1000 #define CHIPC_SPI_ACTION_INPUT 1 #define CHIPC_SPI_ACTION_OUTPUT 2 #define CHIPC_SPI_FLASHCTL 0x00 #define CHIPC_SPI_FLASHCTL_OPCODE 0x000000ff #define CHIPC_SPI_FLASHCTL_ACTION 0x00000700 // /* * We don't use action at all. Experimentaly found, that * action 0 - read current MISO byte to data register (interactive mode) * action 1 = read 2nd byte to data register * action 2 = read 4th byte to data register (surprise! see action 6) * action 3 = read 5th byte to data register * action 4 = read bytes 5-8 to data register in swapped order * action 5 = read bytes 9-12 to data register in swapped order * action 6 = read 3rd byte to data register * action 7 = read bytes 6-9 to data register in swapped order * It may be wrong if CS bit is 1. * If CS bit is 1, you should write cmd / data to opcode byte-to-byte. */ #define CHIPC_SPI_FLASHCTL_CSACTIVE 0x00001000 #define CHIPC_SPI_FLASHCTL_START 0x80000000 //same as BUSY #define CHIPC_SPI_FLASHCTL_BUSY 0x80000000 //same as BUSY #define CHIPC_SPI_FLASHADDR 0x04 #define CHIPC_SPI_FLASHDATA 0x08 struct chipc_spi_softc { - device_t dev; + device_t sc_dev; + struct resource *sc_res; /**< SPI registers */ + int sc_rid; - /* SPI registers */ - struct resource *sc_mem_res; - - /* MMIO flash */ - struct resource *sc_res; + struct resource *sc_flash_res; /**< flash shadow */ + int sc_flash_rid; }; /* register space access macros */ -#define SPI_BARRIER_WRITE(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \ +#define SPI_BARRIER_WRITE(sc) bus_barrier((sc)->sc_res, 0, 0, \ BUS_SPACE_BARRIER_WRITE) -#define SPI_BARRIER_READ(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \ +#define SPI_BARRIER_READ(sc) bus_barrier((sc)->sc_res, 0, 0, \ BUS_SPACE_BARRIER_READ) -#define SPI_BARRIER_RW(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \ - BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) +#define SPI_BARRIER_RW(sc) bus_barrier((sc)->sc_res, 0, 0, \ + BUS_SPACE_BARRIER_READ | \ + BUS_SPACE_BARRIER_WRITE) -#define SPI_WRITE(sc, reg, val) do { \ - bus_write_4(sc->sc_mem_res, (reg), (val)); \ - } while (0) +#define SPI_WRITE(sc, reg, val) bus_write_4(sc->sc_res, (reg), (val)); -#define SPI_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg)) +#define SPI_READ(sc, reg) bus_read_4(sc->sc_res, (reg)) #define SPI_SET_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits)) #define SPI_CLEAR_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits)) #endif /* _BHND_CORES_CHIPC_CHIPC_SPI_H_ */ Index: head/sys/dev/bhnd/cores/chipc/chipc_subr.c =================================================================== --- head/sys/dev/bhnd/cores/chipc/chipc_subr.c (revision 302188) +++ head/sys/dev/bhnd/cores/chipc/chipc_subr.c (revision 302189) @@ -1,372 +1,525 @@ /*- * Copyright (c) 2016 Michael Zhilin * Copyright (c) 2015-2016 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); #include #include #include "chipc_private.h" #include "chipcvar.h" /** + * Return a human-readable name for the given flash @p type. + */ +const char * +chipc_flash_name(chipc_flash type) +{ + switch (type) { + case CHIPC_PFLASH_CFI: + return ("CFI Flash"); + + case CHIPC_SFLASH_ST: + case CHIPC_SFLASH_AT: + return ("SPI Flash"); + + case CHIPC_QSFLASH_ST: + case CHIPC_QSFLASH_AT: + return ("QSPI Flash"); + + case CHIPC_NFLASH: + case CHIPC_NFLASH_4706: + return ("NAND"); + + case CHIPC_FLASH_NONE: + default: + return ("unknown"); + } +} + +/** + * Return the name of the bus device class used by flash @p type, + * or NULL if @p type is unsupported. + */ +const char * +chipc_flash_bus_name(chipc_flash type) +{ + switch (type) { + case CHIPC_PFLASH_CFI: + return ("cfi"); + + case CHIPC_SFLASH_ST: + case CHIPC_SFLASH_AT: + return ("spi"); + + case CHIPC_QSFLASH_ST: + case CHIPC_QSFLASH_AT: + /* unimplemented; spi? */ + return (NULL); + + case CHIPC_NFLASH: + case CHIPC_NFLASH_4706: + /* unimplemented; nandbus? */ + return (NULL); + + case CHIPC_FLASH_NONE: + default: + return (NULL); + } +} + +/** + * Return the name of the flash device class for SPI flash @p type, + * or NULL if @p type does not use SPI, or is unsupported. + */ +const char * +chipc_sflash_device_name(chipc_flash type) +{ + switch (type) { + case CHIPC_SFLASH_ST: + return ("mx25l"); + + case CHIPC_SFLASH_AT: + return ("at45d"); + + case CHIPC_QSFLASH_ST: + case CHIPC_QSFLASH_AT: + /* unimplemented */ + return (NULL); + + case CHIPC_PFLASH_CFI: + case CHIPC_NFLASH: + case CHIPC_NFLASH_4706: + case CHIPC_FLASH_NONE: + default: + return (NULL); + } +} + +/** * Initialize child resource @p r with a virtual address, tag, and handle * copied from @p parent, adjusted to contain only the range defined by * @p offsize and @p size. * * @param r The register to be initialized. * @param parent The parent bus resource that fully contains the subregion. * @param offset The subregion offset within @p parent. * @param size The subregion size. */ int chipc_init_child_resource(struct resource *r, struct resource *parent, bhnd_size_t offset, bhnd_size_t size) { bus_space_handle_t bh, child_bh; bus_space_tag_t bt; uintptr_t vaddr; int error; /* Fetch the parent resource's bus values */ vaddr = (uintptr_t) rman_get_virtual(parent); bt = rman_get_bustag(parent); bh = rman_get_bushandle(parent); /* Configure child resource with offset-adjusted values */ vaddr += offset; error = bus_space_subregion(bt, bh, offset, size, &child_bh); if (error) return (error); rman_set_virtual(r, (void *) vaddr); rman_set_bustag(r, bt); rman_set_bushandle(r, child_bh); return (0); +} + +/** + * Associate a resource with a given resource ID, relative to the given + * port and region. + * + * This function behaves identically to bus_set_resource() for all resource + * types other than SYS_RES_MEMORY. + * + * For SYS_RES_MEMORY resources, the specified @p region's address and size + * will be fetched from the bhnd(4) bus, and bus_set_resource() will be called + * with @p start added the region's actual base address. + * + * To use the default region values for @p start and @p count, specify + * a @p start value of 0ul, and an end value of RMAN_MAX_END + * + * @param sc chipc driver state. + * @param child The device to set the resource on. + * @param type The resource type. + * @param rid The resource ID. + * @param start The resource start address (if SYS_RES_MEMORY, this is + * relative to @p region's base address). + * @param count The length of the resource. + * @param port The mapping port number (ignored if not SYS_RES_MEMORY). + * @param region The mapping region number (ignored if not SYS_RES_MEMORY). + */ +int +chipc_set_resource(struct chipc_softc *sc, device_t child, int type, int rid, + rman_res_t start, rman_res_t count, u_int port, u_int region) +{ + bhnd_addr_t region_addr; + bhnd_size_t region_size; + bool isdefault; + int error; + + if (type != SYS_RES_MEMORY) + return (bus_set_resource(child, type, rid, start, count)); + + isdefault = RMAN_IS_DEFAULT_RANGE(start, count); + + /* Fetch region address and size */ + error = bhnd_get_region_addr(sc->dev, BHND_PORT_DEVICE, port, + region, ®ion_addr, ®ion_size); + if (error) { + device_printf(sc->dev, + "lookup of %s%u.%u failed: %d\n", + bhnd_port_type_name(BHND_PORT_DEVICE), port, region, error); + return (error); + } + + /* Populate defaults */ + if (isdefault) { + start = 0; + count = region_size; + } + + /* Verify requested range is mappable */ + if (start > region_size || region_size - start < count) { + device_printf(sc->dev, + "%s%u.%u region cannot map requested range %#jx+%#jx\n", + bhnd_port_type_name(BHND_PORT_DEVICE), port, region, start, + count); + return (ERANGE); + } + + return (bus_set_resource(child, type, rid, region_addr + start, count)); } /* * Print a capability structure. */ void chipc_print_caps(device_t dev, struct chipc_caps *caps) { #define CC_TFS(_flag) (caps->_flag ? "yes" : "no") device_printf(dev, "MIPSEB: %-3s | BP64: %s\n", CC_TFS(mipseb), CC_TFS(backplane_64)); device_printf(dev, "UARTs: %-3hhu | UGPIO: %s\n", caps->num_uarts, CC_TFS(uart_gpio)); // XXX: hitting a kvprintf bug with '%#02x' not prefixing '0x' in // some cases, and not apply the field width in others device_printf(dev, "UARTClk: 0x%02x | Flash: %u\n", caps->uart_clock, caps->flash_type); device_printf(dev, "SPROM: %-3s | OTP: %s\n", CC_TFS(sprom), CC_TFS(otp_size)); device_printf(dev, "CFIsz: 0x%02x | OTPsz: 0x%02x\n", caps->cfi_width, caps->otp_size); device_printf(dev, "ExtBus: 0x%02x | PwCtl: %s\n", caps->extbus_type, CC_TFS(power_control)); device_printf(dev, "PLL: 0x%02x | JTAGM: %s\n", caps->pll_type, CC_TFS(jtag_master)); device_printf(dev, "PMU: %-3s | ECI: %s\n", CC_TFS(pmu), CC_TFS(eci)); device_printf(dev, "SECI: %-3s | GSIO: %s\n", CC_TFS(seci), CC_TFS(gsio)); device_printf(dev, "AOB: %-3s | BootROM: %s\n", CC_TFS(aob), CC_TFS(boot_rom)); #undef CC_TFS } /** * Allocate and initialize new region record. * * @param sc Driver instance state. * @param type The port type to query. * @param port The port number to query. * @param region The region number to query. */ struct chipc_region * chipc_alloc_region(struct chipc_softc *sc, bhnd_port_type type, u_int port, u_int region) { struct chipc_region *cr; int error; /* Don't bother allocating a chipc_region if init will fail */ if (!bhnd_is_region_valid(sc->dev, type, port, region)) return (NULL); /* Allocate and initialize region info */ cr = malloc(sizeof(*cr), M_BHND, M_NOWAIT); if (cr == NULL) return (NULL); cr->cr_port_type = type; cr->cr_port_num = port; cr->cr_region_num = region; cr->cr_res = NULL; cr->cr_refs = 0; cr->cr_act_refs = 0; error = bhnd_get_region_addr(sc->dev, type, port, region, &cr->cr_addr, &cr->cr_count); if (error) { device_printf(sc->dev, "fetching chipc region address failed: %d\n", error); goto failed; } cr->cr_end = cr->cr_addr + cr->cr_count - 1; /* Fetch default resource ID for this region. Not all regions have an * assigned rid, in which case this will return -1 */ cr->cr_rid = bhnd_get_port_rid(sc->dev, type, port, region); return (cr); failed: device_printf(sc->dev, "chipc region alloc failed for %s%u.%u\n", bhnd_port_type_name(type), port, region); free(cr, M_BHND); return (NULL); } /** * Deallocate the given region record and its associated resource, if any. * * @param sc Driver instance state. * @param cr Region record to be deallocated. */ void chipc_free_region(struct chipc_softc *sc, struct chipc_region *cr) { KASSERT(cr->cr_refs == 0, ("chipc %s%u.%u region has %u active references", bhnd_port_type_name(cr->cr_port_type), cr->cr_port_num, cr->cr_region_num, cr->cr_refs)); if (cr->cr_res != NULL) { bhnd_release_resource(sc->dev, SYS_RES_MEMORY, cr->cr_res_rid, cr->cr_res); } free(cr, M_BHND); } /** * Locate the region mapping the given range, if any. Returns NULL if no * valid region is found. * * @param sc Driver instance state. * @param start start of address range. * @param end end of address range. */ struct chipc_region * chipc_find_region(struct chipc_softc *sc, rman_res_t start, rman_res_t end) { struct chipc_region *cr; if (start > end) return (NULL); STAILQ_FOREACH(cr, &sc->mem_regions, cr_link) { if (start < cr->cr_addr || end > cr->cr_end) continue; /* Found */ return (cr); } /* Not found */ return (NULL); } /** * Locate a region mapping by its bhnd-assigned resource id (as returned by * bhnd_get_port_rid). * * @param sc Driver instance state. * @param rid Resource ID to query for. */ struct chipc_region * chipc_find_region_by_rid(struct chipc_softc *sc, int rid) { struct chipc_region *cr; int port_rid; STAILQ_FOREACH(cr, &sc->mem_regions, cr_link) { port_rid = bhnd_get_port_rid(sc->dev, cr->cr_port_type, cr->cr_port_num, cr->cr_region_num); if (port_rid == -1 || port_rid != rid) continue; /* Found */ return (cr); } /* Not found */ return (NULL); } /** * Retain a reference to a chipc_region, allocating and activating the * backing resource as required. * * @param sc chipc driver instance state * @param cr region to retain. * @param flags specify RF_ALLOCATED to retain an allocation reference, * RF_ACTIVE to retain an activation reference. */ int chipc_retain_region(struct chipc_softc *sc, struct chipc_region *cr, int flags) { int error; KASSERT(!(flags &~ (RF_ACTIVE|RF_ALLOCATED)), ("unsupported flags")); CHIPC_LOCK(sc); /* Handle allocation */ if (flags & RF_ALLOCATED) { /* If this is the first reference, allocate the resource */ if (cr->cr_refs == 0) { KASSERT(cr->cr_res == NULL, ("non-NULL resource has refcount")); /* Fetch initial resource ID */ if ((cr->cr_res_rid = cr->cr_rid) == -1) { CHIPC_UNLOCK(sc); return (EINVAL); } /* Allocate resource */ cr->cr_res = bhnd_alloc_resource(sc->dev, SYS_RES_MEMORY, &cr->cr_res_rid, cr->cr_addr, cr->cr_end, cr->cr_count, 0); if (cr->cr_res == NULL) { CHIPC_UNLOCK(sc); return (ENXIO); } } /* Increment allocation refcount */ cr->cr_refs++; } /* Handle activation */ if (flags & RF_ACTIVE) { KASSERT(cr->cr_refs > 0, ("cannot activate unallocated resource")); /* If this is the first reference, activate the resource */ if (cr->cr_act_refs == 0) { error = bhnd_activate_resource(sc->dev, SYS_RES_MEMORY, cr->cr_res_rid, cr->cr_res); if (error) { /* Drop any allocation reference acquired * above */ CHIPC_UNLOCK(sc); chipc_release_region(sc, cr, flags &~ RF_ACTIVE); return (error); } } /* Increment activation refcount */ cr->cr_act_refs++; } CHIPC_UNLOCK(sc); return (0); } /** * Release a reference to a chipc_region, deactivating and releasing the * backing resource if the reference count hits zero. * * @param sc chipc driver instance state * @param cr region to retain. * @param flags specify RF_ALLOCATED to release an allocation reference, * RF_ACTIVE to release an activation reference. */ int chipc_release_region(struct chipc_softc *sc, struct chipc_region *cr, int flags) { int error; CHIPC_LOCK(sc); error = 0; KASSERT(cr->cr_res != NULL, ("release on NULL region resource")); if (flags & RF_ACTIVE) { KASSERT(cr->cr_act_refs > 0, ("RF_ACTIVE over-released")); KASSERT(cr->cr_act_refs <= cr->cr_refs, ("RF_ALLOCATED released with RF_ACTIVE held")); /* If this is the last reference, deactivate the resource */ if (cr->cr_act_refs == 1) { error = bhnd_deactivate_resource(sc->dev, SYS_RES_MEMORY, cr->cr_res_rid, cr->cr_res); if (error) goto done; } /* Drop our activation refcount */ cr->cr_act_refs--; } if (flags & RF_ALLOCATED) { KASSERT(cr->cr_refs > 0, ("overrelease of refs")); /* If this is the last reference, release the resource */ if (cr->cr_refs == 1) { error = bhnd_release_resource(sc->dev, SYS_RES_MEMORY, cr->cr_res_rid, cr->cr_res); if (error) goto done; cr->cr_res = NULL; } /* Drop our allocation refcount */ cr->cr_refs--; } done: CHIPC_UNLOCK(sc); return (error); } Index: head/sys/dev/bhnd/cores/chipc/chipcreg.h =================================================================== --- head/sys/dev/bhnd/cores/chipc/chipcreg.h (revision 302188) +++ head/sys/dev/bhnd/cores/chipc/chipcreg.h (revision 302189) @@ -1,1543 +1,1543 @@ /*- * Copyright (c) 2015-2016 Landon Fuller * Copyright (c) 2010 Broadcom Corporation * All rights reserved. * * This file is derived from the sbchipc.h header distributed with * Broadcom's initial brcm80211 Linux driver release, as * contributed to the Linux staging repository. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ #ifndef _BHND_CORES_CHIPC_CHIPCREG_H_ #define _BHND_CORES_CHIPC_CHIPCREG_H_ #define CHIPC_CHIPID_SIZE 0x100 /**< size of the register block containing the chip identification registers required during bus enumeration */ /** Evaluates to true if the given ChipCommon core revision provides * the core count via the chip identification register. */ #define CHIPC_NCORES_MIN_HWREV(hwrev) ((hwrev) == 4 || (hwrev) >= 6) #define CHIPC_GET_FLAG(_value, _flag) (((_value) & _flag) != 0) #define CHIPC_GET_BITS(_value, _field) \ ((_value & _field ## _MASK) >> _field ## _SHIFT) #define CHIPC_ID 0x00 #define CHIPC_CAPABILITIES 0x04 #define CHIPC_CORECTRL 0x08 /* rev >= 1 */ #define CHIPC_BIST 0x0C #define CHIPC_OTPST 0x10 /**< otp status */ #define CHIPC_OTPCTRL 0x14 /**< otp control */ #define CHIPC_OTPPROG 0x18 #define CHIPC_OTPLAYOUT 0x1C /**< otp layout (IPX OTP) */ #define CHIPC_INTST 0x20 /**< interrupt status */ #define CHIPC_INTM 0x24 /**< interrupt mask */ #define CHIPC_CHIPCTRL 0x28 /**< chip control (rev >= 11) */ #define CHIPC_CHIPST 0x2C /**< chip status (rev >= 11) */ #define CHIPC_JTAGCMD 0x30 #define CHIPC_JTAGIR 0x34 #define CHIPC_JTAGDR 0x38 #define CHIPC_JTAGCTRL 0x3c #define CHIPC_SFLASH_BASE 0x40 #define CHIPC_SFLASH_SIZE 12 #define CHIPC_SFLASHCTRL 0x40 #define CHIPC_SFLASHADDR 0x44 #define CHIPC_SFLASHDATA 0x48 /* siba backplane configuration broadcast (siba-only) */ #define CHIPC_SBBCAST_ADDR 0x50 #define CHIPC_SBBCAST_DATA 0x54 #define CHIPC_GPIOPU 0x58 /**< pull-up mask (rev >= 20) */ #define CHIPC_GPIOPD 0x5C /**< pull down mask (rev >= 20) */ #define CHIPC_GPIOIN 0x60 #define CHIPC_GPIOOUT 0x64 #define CHIPC_GPIOOUTEN 0x68 #define CHIPC_GPIOCTRL 0x6C #define CHIPC_GPIOPOL 0x70 #define CHIPC_GPIOINTM 0x74 /**< gpio interrupt mask */ #define CHIPC_GPIOEVENT 0x78 /**< gpio event (rev >= 11) */ #define CHIPC_GPIOEVENT_INTM 0x7C /**< gpio event interrupt mask (rev >= 11) */ #define CHIPC_WATCHDOG 0x80 /**< watchdog timer */ #define CHIPC_GPIOEVENT_INTPOLARITY 0x84 /**< gpio even interrupt polarity (rev >= 11) */ #define CHIPC_GPIOTIMERVAL 0x88 /**< gpio-based LED duty cycle (rev >= 16) */ #define CHIPC_GPIOTIMEROUTMASK 0x8C /* clock control block */ #define CHIPC_CLKC_N 0x90 #define CHIPC_CLKC_SB 0x94 /* m0 (backplane) */ #define CHIPC_CLKC_PCI 0x98 /* m1 */ #define CHIPC_CLKC_M2 0x9C /* mii/uart/mipsref */ #define CHIPC_CLKC_M3 0xA0 /* cpu */ #define CHIPC_CLKDIV 0xA4 /* rev >= 3 */ #define CHIPC_GPIODEBUGSEL 0xA8 /* rev >= 28 */ #define CHIPC_CAPABILITIES_EXT 0xAC /* pll delay (registers rev >= 4) */ #define CHIPC_PLL_ON_DELAY 0xB0 #define CHIPC_PLL_FREFSEL_DELAY 0xB4 #define CHIPC_PLL_SLOWCLK_CTL 0xB8 /* revs 6-9 */ /* "instaclock" registers */ #define CHIPC_SYS_CLK_CTL 0xC0 /* rev >= 10 */ #define CHIPC_SYS_CLKSTATESTRETCH 0xC4 /* rev >= 10 */ /* indirect backplane access (rev >= 10) */ #define CHIPC_BP_ADDRLOW 0xD0 #define CHIPC_BP_ADDRHIGH 0xD4 #define CHIPC_BP_DATA 0xD8 #define CHIPC_BP_INDACCESS 0xE0 /* SPI/I2C (rev >= 37) */ #define CHIPC_GSIO_CTRL 0xE4 #define CHIPC_GSIO_ADDR 0xE8 #define CHIPC_GSIO_DATA 0xEC /* More clock dividers (corerev >= 32) */ #define CHIPC_CLKDIV2 0xF0 #define CHIPC_EROMPTR 0xFC /**< 32-bit EROM base address * on BCMA devices */ /* ExtBus control registers (rev >= 3) */ #define CHIPC_PCMCIA_CFG 0x100 #define CHIPC_PCMCIA_MEMWAIT 0x104 #define CHIPC_PCMCIA_ATTRWAIT 0x108 #define CHIPC_PCMCIA_IOWAIT 0x10C #define CHIPC_IDE_CFG 0x110 #define CHIPC_IDE_MEMWAIT 0x114 #define CHIPC_IDE_ATTRWAIT 0x118 #define CHIPC_IDE_IOWAIT 0x11C #define CHIPC_PROG_CFG 0x120 #define CHIPC_PROG_WAITCOUNT 0x124 #define CHIPC_FLASH_CFG 0x128 #define CHIPC_FLASH_WAITCOUNT 0x12C #define CHIPC_SECI_CFG 0x130 #define CHIPC_SECI_ST 0x134 #define CHIPC_SECI_STM 0x138 #define CHIPC_SECI_RXNBC 0x13C /* Enhanced Coexistence Interface (ECI) registers (rev 21-34) */ #define CHIPC_ECI_OUTPUT 0x140 #define CHIPC_ECI_CTRL 0x144 #define CHIPC_ECI_INPUTLO 0x148 #define CHIPC_ECI_INPUTMI 0x14C #define CHIPC_ECI_INPUTHI 0x150 #define CHIPC_ECI_INPUTINTPOLARITYLO 0x154 #define CHIPC_ECI_INPUTINTPOLARITYMI 0x158 #define CHIPC_ECI_INPUTINTPOLARITYHI 0x15C #define CHIPC_ECI_INTMASKLO 0x160 #define CHIPC_ECI_INTMASKMI 0x164 #define CHIPC_ECI_INTMASKHI 0x168 #define CHIPC_ECI_EVENTLO 0x16C #define CHIPC_ECI_EVENTMI 0x170 #define CHIPC_ECI_EVENTHI 0x174 #define CHIPC_ECI_EVENTMASKLO 0x178 #define CHIPC_ECI_EVENTMASKMI 0x17C #define CHIPC_ECI_EVENTMASKHI 0x180 #define CHIPC_FLASHSTRCFG 0x18C /**< BCM4706 NAND flash config */ #define CHIPC_SPROM_CTRL 0x190 /**< SPROM interface (rev >= 32) */ #define CHIPC_SPROM_ADDR 0x194 #define CHIPC_SPROM_DATA 0x198 /* Clock control and hardware workarounds (corerev >= 20) */ #define CHIPC_CLK_CTL_ST 0x1E0 #define CHIPC_SPROM_HWWAR 0x19 #define CHIPC_UART_BASE 0x300 #define CHIPC_UART_SIZE 0x100 -#define CHIPC_UART0_BASE CHIPC_UART_BASE -#define CHIPC_UART1_BASE (CHIPC_UART_BASE + CHIPC_UART_SIZE) +#define CHIPC_UART_MAX 3 /**< max UART blocks */ +#define CHIPC_UART(_n) (CHIPC_UART_BASE + (CHIPC_UART_SIZE*_n)) /* PMU registers (rev >= 20) */ #define CHIPC_PMU_BASE 0x600 #define CHIPC_PMU_SIZE 0x70 #define CHIPC_PMU_CTRL 0x600 #define CHIPC_PMU_CAP 0x604 #define CHIPC_PMU_ST 0x608 #define CHIPC_PMU_RES_STATE 0x60c #define CHIPC_PMU_RES_PENDING 0x610 #define CHIPC_PMU_TIMER 0x614 #define CHIPC_PMU_MIN_RES_MASK 0x618 #define CHIPC_PMU_MAX_RES_MASK 0x61c #define CHIPC_PMU_RES_TABLE_SEL 0x620 #define CHIPC_PMU_RES_DEP_MASK 0x624 #define CHIPC_PMU_RES_UPDN_TIMER 0x628 #define CHIPC_PMU_RES_TIMER 0x62C #define CHIPC_PMU_CLKSTRETCH 0x630 #define CHIPC_PMU_WATCHDOG 0x634 #define CHIPC_PMU_GPIOSEL 0x638 /* pmu rev >= 1 ? */ #define CHIPC_PMU_GPIOEN 0x63C /* pmu rev >= 1 ? */ #define CHIPC_PMU_RES_REQ_TIMER_SEL 0x640 #define CHIPC_PMU_RES_REQ_TIMER 0x644 #define CHIPC_PMU_RES_REQ_MASK 0x648 #define CHIPC_CHIPCTL_ADDR 0x650 #define CHIPC_CHIPCTL_DATA 0x654 #define CHIPC_PMU_REG_CONTROL_ADDR 0x658 #define CHIPC_PMU_REG_CONTROL_DATA 0x65C #define CHIPC_PMU_PLL_CONTROL_ADDR 0x660 #define CHIPC_PMU_PLL_CONTROL_DATA 0x664 #define CHIPC_PMU_STRAPOPT 0x668 /* chipc rev >= 28 */ #define CHIPC_PMU_XTALFREQ 0x66C /* pmu rev >= 10 */ #define CHIPC_SPROM_OTP 0x800 /* SPROM/OTP address space */ #define CHIPC_SPROM_OTP_SIZE 0x400 /** chipid */ #define CHIPC_ID_CHIP_MASK 0x0000FFFF /**< chip id */ #define CHIPC_ID_CHIP_SHIFT 0 #define CHIPC_ID_REV_MASK 0x000F0000 /**< chip revision */ #define CHIPC_ID_REV_SHIFT 16 #define CHIPC_ID_PKG_MASK 0x00F00000 /**< physical package ID */ #define CHIPC_ID_PKG_SHIFT 20 #define CHIPC_ID_NUMCORE_MASK 0x0F000000 /**< number of cores on chip (rev >= 4) */ #define CHIPC_ID_NUMCORE_SHIFT 24 #define CHIPC_ID_BUS_MASK 0xF0000000 /**< chip/interconnect type (BHND_CHIPTYPE_*) */ #define CHIPC_ID_BUS_SHIFT 28 /* capabilities */ #define CHIPC_CAP_NUM_UART_MASK 0x00000003 /* Number of UARTs (1-3) */ #define CHIPC_CAP_NUM_UART_SHIFT 0 #define CHIPC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */ #define CHIPC_CAP_UCLKSEL_MASK 0x00000018 /* UARTs clock select */ #define CHIPC_CAP_UCLKSEL_SHIFT 3 #define CHIPC_CAP_UCLKSEL_UINTCLK 0x1 /* UARTs are driven by internal divided clock */ #define CHIPC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */ #define CHIPC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */ #define CHIPC_CAP_EXTBUS_SHIFT 6 #define CHIPC_CAP_EXTBUS_NONE 0x0 /* No ExtBus present */ #define CHIPC_CAP_EXTBUS_FULL 0x1 /* ExtBus: PCMCIA, IDE & Prog */ #define CHIPC_CAP_EXTBUS_PROG 0x2 /* ExtBus: ProgIf only */ #define CHIPC_CAP_FLASH_MASK 0x00000700 /* Type of flash */ #define CHIPC_CAP_FLASH_SHIFT 8 #define CHIPC_CAP_FLASH_NONE 0x0 /* No flash */ #define CHIPC_CAP_SFLASH_ST 0x1 /* ST serial flash */ #define CHIPC_CAP_SFLASH_AT 0x2 /* Atmel serial flash */ #define CHIPC_CAP_NFLASH 0x3 /* NAND flash */ #define CHIPC_CAP_PFLASH 0x7 /* Parallel flash */ #define CHIPC_CAP_PLL_MASK 0x00038000 /* Type of PLL */ #define CHIPC_CAP_PLL_SHIFT 15 #define CHIPC_CAP_PWR_CTL 0x00040000 /* Power control */ #define CHIPC_CAP_OTP_SIZE_MASK 0x00380000 /* OTP Size (0 = none) */ #define CHIPC_CAP_OTP_SIZE_SHIFT 19 /* OTP Size shift */ #define CHIPC_CAP_OTP_SIZE_BASE 5 /* OTP Size base */ #define CHIPC_CAP_JTAGP 0x00400000 /* JTAG Master Present */ #define CHIPC_CAP_ROM 0x00800000 /* Internal boot rom active */ #define CHIPC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */ #define CHIPC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */ #define CHIPC_CAP_ECI 0x20000000 /* Enhanced Coexistence Interface */ #define CHIPC_CAP_SPROM 0x40000000 /* SPROM Present, rev >= 32 */ #define CHIPC_CAP_4706_NFLASH 0x80000000 /* NAND flash present, BCM4706 or chipc rev38 (BCM5357)? */ #define CHIPC_CAP2_SECI 0x00000001 /* SECI Present, rev >= 36 */ #define CHIPC_CAP2_GSIO 0x00000002 /* GSIO (spi/i2c) present, rev >= 37 */ #define CHIPC_CAP2_GCI 0x00000004 /* GCI present (rev >= ??) */ #define CHIPC_CAP2_AOB 0x00000040 /* Always on Bus present (rev >= 49) * * If set, PMU and GCI registers * are found in dedicated cores. * * This appears to be a lower power * APB bus, bridged via ARM APB IP. */ /* * ChipStatus (Common) */ /** ChipStatus CIS/OTP/SPROM values used to advertise OTP/SPROM availability in * chipcommon revs 11-31. */ enum { CHIPC_CST_DEFCIS_SEL = 0, /**< OTP is powered up, use default CIS, no SPROM */ CHIPC_CST_SPROM_SEL = 1, /**< OTP is powered up, SPROM is present */ CHIPC_CST_OTP_SEL = 2, /**< OTP is powered up, no SPROM */ CHIPC_CST_OTP_PWRDN = 3 /**< OTP is powered down, SPROM is present (rev <= 22 only) */ }; #define CHIPC_CST_SPROM_OTP_SEL_R22_MASK 0x00000003 /**< chipstatus OTP/SPROM SEL value (rev 22) */ #define CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT 0 #define CHIPC_CST_SPROM_OTP_SEL_R23_MASK 0x000000c0 /**< chipstatus OTP/SPROM SEL value (revs 23-31) * * it is unknown whether this is supported on * any CC revs >= 32 that also vend CHIPC_CAP_* * constants for OTP/SPROM/NVRAM availability. */ #define CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT 6 /* PLL type */ #define CHIPC_PLL_NONE 0x00000000 #define CHIPC_PLL_TYPE1 0x00010000 /* 48MHz base, 3 dividers */ #define CHIPC_PLL_TYPE2 0x00020000 /* 48MHz, 4 dividers */ #define CHIPC_PLL_TYPE3 0x00030000 /* 25MHz, 2 dividers */ #define CHIPC_PLL_TYPE4 0x00008000 /* 48MHz, 4 dividers */ #define CHIPC_PLL_TYPE5 0x00018000 /* 25MHz, 4 dividers */ #define CHIPC_PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */ #define CHIPC_PLL_TYPE7 0x00038000 /* 25MHz, 4 dividers */ /* ILP clock */ #define CHIPC_ILP_CLOCK 32000 /* ALP clock on pre-PMU chips */ #define CHIPC_ALP_CLOCK 20000000 /* HT clock */ #define CHIPC_HT_CLOCK 80000000 /* corecontrol */ #define CHIPC_UARTCLKO 0x00000001 /* Drive UART with internal clock */ #define CHIPC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ #define CHIPC_UARTCLKEN 0x00000008 /* enable UART Clock (corerev > = 21 */ /* chipcontrol */ #define CHIPCTRL_4321A0_DEFAULT 0x3a4 #define CHIPCTRL_4321A1_DEFAULT 0x0a4 #define CHIPCTRL_4321_PLL_DOWN 0x800000 /* serdes PLL down override */ /* Fields in the otpstatus register in rev >= 21 */ #define CHIPC_OTPS_OL_MASK 0x000000ff #define CHIPC_OTPS_OL_MFG 0x00000001 /* manuf row is locked */ #define CHIPC_OTPS_OL_OR1 0x00000002 /* otp redundancy row 1 is locked */ #define CHIPC_OTPS_OL_OR2 0x00000004 /* otp redundancy row 2 is locked */ #define CHIPC_OTPS_OL_GU 0x00000008 /* general use region is locked */ #define CHIPC_OTPS_GUP_MASK 0x00000f00 #define CHIPC_OTPS_GUP_SHIFT 8 #define CHIPC_OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */ #define CHIPC_OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */ #define CHIPC_OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */ #define CHIPC_OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */ #define CHIPC_OTPS_READY 0x00001000 #define CHIPC_OTPS_RV(x) (1 << (16 + (x))) /* redundancy entry valid */ #define CHIPC_OTPS_RV_MASK 0x0fff0000 /* IPX OTP fields in the otpcontrol register */ #define CHIPC_OTPC_PROGSEL 0x00000001 #define CHIPC_OTPC_PCOUNT_MASK 0x0000000e #define CHIPC_OTPC_PCOUNT_SHIFT 1 #define CHIPC_OTPC_VSEL_MASK 0x000000f0 #define CHIPC_OTPC_VSEL_SHIFT 4 #define CHIPC_OTPC_TMM_MASK 0x00000700 #define CHIPC_OTPC_TMM_SHIFT 8 #define CHIPC_OTPC_ODM 0x00000800 #define CHIPC_OTPC_PROGEN 0x80000000 /* Fields in otpprog in IPX OTP and HND OTP */ #define CHIPC_OTPP_COL_MASK 0x000000ff #define CHIPC_OTPP_COL_SHIFT 0 #define CHIPC_OTPP_ROW_MASK 0x0000ff00 #define CHIPC_OTPP_ROW_SHIFT 8 #define CHIPC_OTPP_OC_MASK 0x0f000000 #define CHIPC_OTPP_OC_SHIFT 24 #define CHIPC_OTPP_READERR 0x10000000 #define CHIPC_OTPP_VALUE_MASK 0x20000000 #define CHIPC_OTPP_VALUE_SHIFT 29 #define CHIPC_OTPP_START_BUSY 0x80000000 #define CHIPC_OTPP_READ 0x40000000 /* HND OTP */ /* otplayout */ #define CHIPC_OTPL_SIZE_MASK 0x0000f000 /* rev >= 49 */ #define CHIPC_OTPL_SIZE_SHIFT 12 #define CHIPC_OTPL_GUP_MASK 0x00000FFF /* bit offset to general use region */ #define CHIPC_OTPL_GUP_SHIFT 0 #define CHIPC_OTPL_CISFORMAT_NEW 0x80000000 /* rev >= 36 */ /* Opcodes for OTPP_OC field */ #define CHIPC_OTPPOC_READ 0 #define CHIPC_OTPPOC_BIT_PROG 1 #define CHIPC_OTPPOC_VERIFY 3 #define CHIPC_OTPPOC_INIT 4 #define CHIPC_OTPPOC_SET 5 #define CHIPC_OTPPOC_RESET 6 #define CHIPC_OTPPOC_OCST 7 #define CHIPC_OTPPOC_ROW_LOCK 8 #define CHIPC_OTPPOC_PRESCN_TEST 9 /* Jtagm characteristics that appeared at a given corerev */ #define CHIPC_JTAGM_CREV_OLD 10 /* Old command set, 16bit max IR */ #define CHIPC_JTAGM_CREV_IRP 22 /* Able to do pause-ir */ #define CHIPC_JTAGM_CREV_RTI 28 /* Able to do return-to-idle */ /* jtagcmd */ #define CHIPC_JCMD_START 0x80000000 #define CHIPC_JCMD_BUSY 0x80000000 #define CHIPC_JCMD_STATE_MASK 0x60000000 #define CHIPC_JCMD_STATE_TLR 0x00000000 /* Test-logic-reset */ #define CHIPC_JCMD_STATE_PIR 0x20000000 /* Pause IR */ #define CHIPC_JCMD_STATE_PDR 0x40000000 /* Pause DR */ #define CHIPC_JCMD_STATE_RTI 0x60000000 /* Run-test-idle */ #define CHIPC_JCMD0_ACC_MASK 0x0000f000 #define CHIPC_JCMD0_ACC_IRDR 0x00000000 #define CHIPC_JCMD0_ACC_DR 0x00001000 #define CHIPC_JCMD0_ACC_IR 0x00002000 #define CHIPC_JCMD0_ACC_RESET 0x00003000 #define CHIPC_JCMD0_ACC_IRPDR 0x00004000 #define CHIPC_JCMD0_ACC_PDR 0x00005000 #define CHIPC_JCMD0_IRW_MASK 0x00000f00 #define CHIPC_JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */ #define CHIPC_JCMD_ACC_IRDR 0x00000000 #define CHIPC_JCMD_ACC_DR 0x00010000 #define CHIPC_JCMD_ACC_IR 0x00020000 #define CHIPC_JCMD_ACC_RESET 0x00030000 #define CHIPC_JCMD_ACC_IRPDR 0x00040000 #define CHIPC_JCMD_ACC_PDR 0x00050000 #define CHIPC_JCMD_ACC_PIR 0x00060000 #define CHIPC_JCMD_ACC_IRDR_I 0x00070000 /* rev 28: return to run-test-idle */ #define CHIPC_JCMD_ACC_DR_I 0x00080000 /* rev 28: return to run-test-idle */ #define CHIPC_JCMD_IRW_MASK 0x00001f00 #define CHIPC_JCMD_IRW_SHIFT 8 #define CHIPC_JCMD_DRW_MASK 0x0000003f /* jtagctrl */ #define CHIPC_JCTRL_FORCE_CLK 4 /* Force clock */ #define CHIPC_JCTRL_EXT_EN 2 /* Enable external targets */ #define CHIPC_JCTRL_EN 1 /* Enable Jtag master */ /* Fields in clkdiv */ #define CHIPC_CLKD_SFLASH 0x0f000000 #define CHIPC_CLKD_SFLASH_SHIFT 24 #define CHIPC_CLKD_OTP 0x000f0000 #define CHIPC_CLKD_OTP_SHIFT 16 #define CHIPC_CLKD_JTAG 0x00000f00 #define CHIPC_CLKD_JTAG_SHIFT 8 #define CHIPC_CLKD_UART 0x000000ff #define CHIPC_CLKD2_SPROM 0x00000003 /* intstatus/intmask */ #define CHIPC_CI_GPIO 0x00000001 /* gpio intr */ #define CHIPC_CI_EI 0x00000002 /* extif intr (corerev >= 3) */ #define CHIPC_CI_TEMP 0x00000004 /* temp. ctrl intr (corerev >= 15) */ #define CHIPC_CI_SIRQ 0x00000008 /* serial IRQ intr (corerev >= 15) */ #define CHIPC_CI_PMU 0x00000020 /* pmu intr (corerev >= 21) */ #define CHIPC_CI_UART 0x00000040 /* uart intr (corerev >= 21) */ #define CHIPC_CI_WDRESET 0x80000000 /* watchdog reset occurred */ /* slow_clk_ctl */ #define CHIPC_SCC_SS_MASK 0x00000007 /* slow clock source mask */ #define CHIPC_SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */ #define CHIPC_SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */ #define CHIPC_SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */ #define CHIPC_SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */ #define CHIPC_SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, * 0: LPO is enabled */ #define CHIPC_SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, * 0: power logic control */ #define CHIPC_SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors * PLL clock disable requests from core */ #define CHIPC_SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't * disable crystal when appropriate */ #define CHIPC_SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */ #define CHIPC_SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */ #define CHIPC_SCC_CD_SHIFT 16 /* system_clk_ctl */ #define CHIPC_SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */ #define CHIPC_SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */ #define CHIPC_SYCC_FP 0x00000004 /* ForcePLLOn */ #define CHIPC_SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */ #define CHIPC_SYCC_HR 0x00000010 /* Force HT */ #define CHIPC_SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */ #define CHIPC_SYCC_CD_SHIFT 16 /* Indirect backplane access */ #define CHIPC_BPIA_BYTEEN 0x0000000f #define CHIPC_BPIA_SZ1 0x00000001 #define CHIPC_BPIA_SZ2 0x00000003 #define CHIPC_BPIA_SZ4 0x00000007 #define CHIPC_BPIA_SZ8 0x0000000f #define CHIPC_BPIA_WRITE 0x00000100 #define CHIPC_BPIA_START 0x00000200 #define CHIPC_BPIA_BUSY 0x00000200 #define CHIPC_BPIA_ERROR 0x00000400 /* pcmcia/prog/flash_config */ #define CHIPC_CF_EN 0x00000001 /* enable */ #define CHIPC_CF_EM_MASK 0x0000000e /* mode */ #define CHIPC_CF_EM_SHIFT 1 #define CHIPC_CF_EM_FLASH 0 /* flash/asynchronous mode */ #define CHIPC_CF_EM_SYNC 2 /* synchronous mode */ #define CHIPC_CF_EM_PCMCIA 4 /* pcmcia mode */ #define CHIPC_CF_DS 0x00000010 /* destsize: 0=8bit, 1=16bit */ #define CHIPC_CF_BS 0x00000020 /* byteswap */ #define CHIPC_CF_CD_MASK 0x000000c0 /* clock divider */ #define CHIPC_CF_CD_SHIFT 6 #define CHIPC_CF_CD_DIV2 0x00000000 /* backplane/2 */ #define CHIPC_CF_CD_DIV3 0x00000040 /* backplane/3 */ #define CHIPC_CF_CD_DIV4 0x00000080 /* backplane/4 */ #define CHIPC_CF_CE 0x00000100 /* clock enable */ #define CHIPC_CF_SB 0x00000200 /* size/bytestrobe (synch only) */ /* pcmcia_memwait */ #define CHIPC_PM_W0_MASK 0x0000003f /* waitcount0 */ #define CHIPC_PM_W1_MASK 0x00001f00 /* waitcount1 */ #define CHIPC_PM_W1_SHIFT 8 #define CHIPC_PM_W2_MASK 0x001f0000 /* waitcount2 */ #define CHIPC_PM_W2_SHIFT 16 #define CHIPC_PM_W3_MASK 0x1f000000 /* waitcount3 */ #define CHIPC_PM_W3_SHIFT 24 /* pcmcia_attrwait */ #define CHIPC_PA_W0_MASK 0x0000003f /* waitcount0 */ #define CHIPC_PA_W1_MASK 0x00001f00 /* waitcount1 */ #define CHIPC_PA_W1_SHIFT 8 #define CHIPC_PA_W2_MASK 0x001f0000 /* waitcount2 */ #define CHIPC_PA_W2_SHIFT 16 #define CHIPC_PA_W3_MASK 0x1f000000 /* waitcount3 */ #define CHIPC_PA_W3_SHIFT 24 /* pcmcia_iowait */ #define CHIPC_PI_W0_MASK 0x0000003f /* waitcount0 */ #define CHIPC_PI_W1_MASK 0x00001f00 /* waitcount1 */ #define CHIPC_PI_W1_SHIFT 8 #define CHIPC_PI_W2_MASK 0x001f0000 /* waitcount2 */ #define CHIPC_PI_W2_SHIFT 16 #define CHIPC_PI_W3_MASK 0x1f000000 /* waitcount3 */ #define CHIPC_PI_W3_SHIFT 24 /* prog_waitcount */ #define CHIPC_PW_W0_MASK 0x0000001f /* waitcount0 */ #define CHIPC_PW_W1_MASK 0x00001f00 /* waitcount1 */ #define CHIPC_PW_W1_SHIFT 8 #define CHIPC_PW_W2_MASK 0x001f0000 /* waitcount2 */ #define CHIPC_PW_W2_SHIFT 16 #define CHIPC_PW_W3_MASK 0x1f000000 /* waitcount3 */ #define CHIPC_PW_W3_SHIFT 24 #define CHIPC_PW_W0 0x0000000c #define CHIPC_PW_W1 0x00000a00 #define CHIPC_PW_W2 0x00020000 #define CHIPC_PW_W3 0x01000000 /* flash_waitcount */ #define CHIPC_FW_W0_MASK 0x0000003f /* waitcount0 */ #define CHIPC_FW_W1_MASK 0x00001f00 /* waitcount1 */ #define CHIPC_FW_W1_SHIFT 8 #define CHIPC_FW_W2_MASK 0x001f0000 /* waitcount2 */ #define CHIPC_FW_W2_SHIFT 16 #define CHIPC_FW_W3_MASK 0x1f000000 /* waitcount3 */ #define CHIPC_FW_W3_SHIFT 24 /* When SPROM support present, fields in spromcontrol */ #define CHIPC_SRC_START 0x80000000 #define CHIPC_SRC_BUSY 0x80000000 #define CHIPC_SRC_OPCODE 0x60000000 #define CHIPC_SRC_OP_READ 0x00000000 #define CHIPC_SRC_OP_WRITE 0x20000000 #define CHIPC_SRC_OP_WRDIS 0x40000000 #define CHIPC_SRC_OP_WREN 0x60000000 #define CHIPC_SRC_OTPSEL 0x00000010 #define CHIPC_SRC_LOCK 0x00000008 #define CHIPC_SRC_SIZE_MASK 0x00000006 #define CHIPC_SRC_SIZE_1K 0x00000000 #define CHIPC_SRC_SIZE_4K 0x00000002 #define CHIPC_SRC_SIZE_16K 0x00000004 #define CHIPC_SRC_SIZE_SHIFT 1 #define CHIPC_SRC_PRESENT 0x00000001 /* Fields in pmucontrol */ #define CHIPC_PCTL_ILP_DIV_MASK 0xffff0000 #define CHIPC_PCTL_ILP_DIV_SHIFT 16 #define CHIPC_PCTL_PLL_PLLCTL_UPD 0x00000400 /* rev 2 */ #define CHIPC_PCTL_NOILP_ON_WAIT 0x00000200 /* rev 1 */ #define CHIPC_PCTL_HT_REQ_EN 0x00000100 #define CHIPC_PCTL_ALP_REQ_EN 0x00000080 #define CHIPC_PCTL_XTALFREQ_MASK 0x0000007c #define CHIPC_PCTL_XTALFREQ_SHIFT 2 #define CHIPC_PCTL_ILP_DIV_EN 0x00000002 #define CHIPC_PCTL_LPO_SEL 0x00000001 /* Fields in clkstretch */ #define CHIPC_CSTRETCH_HT 0xffff0000 #define CHIPC_CSTRETCH_ALP 0x0000ffff /* gpiotimerval */ #define CHIPC_GPIO_ONTIME_SHIFT 16 /* clockcontrol_n */ #define CHIPC_CN_N1_MASK 0x3f /* n1 control */ #define CHIPC_CN_N2_MASK 0x3f00 /* n2 control */ #define CHIPC_CN_N2_SHIFT 8 #define CHIPC_CN_PLLC_MASK 0xf0000 /* pll control */ #define CHIPC_CN_PLLC_SHIFT 16 /* clockcontrol_sb/pci/uart */ #define CHIPC_M1_MASK 0x3f /* m1 control */ #define CHIPC_M2_MASK 0x3f00 /* m2 control */ #define CHIPC_M2_SHIFT 8 #define CHIPC_M3_MASK 0x3f0000 /* m3 control */ #define CHIPC_M3_SHIFT 16 #define CHIPC_MC_MASK 0x1f000000 /* mux control */ #define CHIPC_MC_SHIFT 24 /* N3M Clock control magic field values */ #define CHIPC_F6_2 0x02 /* A factor of 2 in */ #define CHIPC_F6_3 0x03 /* 6-bit fields like */ #define CHIPC_F6_4 0x05 /* N1, M1 or M3 */ #define CHIPC_F6_5 0x09 #define CHIPC_F6_6 0x11 #define CHIPC_F6_7 0x21 #define CHIPC_F5_BIAS 5 /* 5-bit fields get this added */ #define CHIPC_MC_BYPASS 0x08 #define CHIPC_MC_M1 0x04 #define CHIPC_MC_M1M2 0x02 #define CHIPC_MC_M1M2M3 0x01 #define CHIPC_MC_M1M3 0x11 /* Type 2 Clock control magic field values */ #define CHIPC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */ #define CHIPC_T2M2_BIAS 3 /* m2 bias */ #define CHIPC_T2MC_M1BYP 1 #define CHIPC_T2MC_M2BYP 2 #define CHIPC_T2MC_M3BYP 4 /* Type 6 Clock control magic field values */ #define CHIPC_T6_MMASK 1 /* bits of interest in m */ #define CHIPC_T6_M0 120000000 /* sb clock for m = 0 */ #define CHIPC_T6_M1 100000000 /* sb clock for m = 1 */ #define CHIPC_SB2MIPS_T6(sb) (2 * (sb)) /* Common clock base */ #define CHIPC_CLOCK_BASE1 24000000 /* Half the clock freq */ #define CHIPC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLLs */ /* Clock control values for 200MHz in 5350 */ #define CHIPC_CLKC_5350_N 0x0311 #define CHIPC_CLKC_5350_M 0x04020009 /* Bits in the ExtBus config registers */ #define CHIPC_CFG_EN 0x0001 /* Enable */ #define CHIPC_CFG_EM_MASK 0x000e /* Extif Mode */ #define CHIPC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */ #define CHIPC_CFG_EM_SYNC 0x0002 /* Synchronous */ #define CHIPC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */ #define CHIPC_CFG_EM_IDE 0x0006 /* IDE */ #define CHIPC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */ #define CHIPC_FLASH_CFG_CD_MASK 0x00e0 /* Sync: Clock divisor, rev >= 20 */ #define CHIPC_FLASH_CFG_CE 0x0100 /* Sync: Clock enable, rev >= 20 */ #define CHIPC_FLASH_CFG_SB 0x0200 /* Sync: Size/Bytestrobe, rev >= 20 */ #define CHIPC_FLASH_CFG_IS 0x0400 /* Extif Sync Clk Select, rev >= 20 */ /* ExtBus address space */ #define CHIPC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */ #define CHIPC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */ #define CHIPC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */ #define CHIPC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */ #define CHIPC_EB_IDE 0x1a800000 /* IDE memory base */ #define CHIPC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */ #define CHIPC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */ #define CHIPC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */ #define CHIPC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */ /* Start/busy bit in flashcontrol */ #define CHIPC_SFLASH_OPCODE 0x000000ff #define CHIPC_SFLASH_ACTION 0x00000700 #define CHIPC_SFLASH_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */ #define CHIPC_SFLASH_START 0x80000000 #define CHIPC_SFLASH_BUSY SFLASH_START /* flashcontrol action codes */ #define CHIPC_SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */ #define CHIPC_SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */ #define CHIPC_SFLASH_ACT_OP3A 0x0200 /* opcode + 3 addr bytes */ #define CHIPC_SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addr & 1 data bytes */ #define CHIPC_SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addr & 4 data bytes */ #define CHIPC_SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addr, 4 don't care & 4 data bytes */ #define CHIPC_SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addr, 1 don't care & 4 data bytes */ /* flashcontrol action+opcodes for ST flashes */ #define CHIPC_SFLASH_ST_WREN 0x0006 /* Write Enable */ #define CHIPC_SFLASH_ST_WRDIS 0x0004 /* Write Disable */ #define CHIPC_SFLASH_ST_RDSR 0x0105 /* Read Status Register */ #define CHIPC_SFLASH_ST_WRSR 0x0101 /* Write Status Register */ #define CHIPC_SFLASH_ST_READ 0x0303 /* Read Data Bytes */ #define CHIPC_SFLASH_ST_PP 0x0302 /* Page Program */ #define CHIPC_SFLASH_ST_SE 0x02d8 /* Sector Erase */ #define CHIPC_SFLASH_ST_BE 0x00c7 /* Bulk Erase */ #define CHIPC_SFLASH_ST_DP 0x00b9 /* Deep Power-down */ #define CHIPC_SFLASH_ST_RES 0x03ab /* Read Electronic Signature */ #define CHIPC_SFLASH_ST_CSA 0x1000 /* Keep chip select asserted */ #define CHIPC_SFLASH_ST_SSE 0x0220 /* Sub-sector Erase */ /* Status register bits for ST flashes */ #define CHIPC_SFLASH_ST_WIP 0x01 /* Write In Progress */ #define CHIPC_SFLASH_ST_WEL 0x02 /* Write Enable Latch */ #define CHIPC_SFLASH_ST_BP_MASK 0x1c /* Block Protect */ #define CHIPC_SFLASH_ST_BP_SHIFT 2 #define CHIPC_SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */ /* flashcontrol action+opcodes for Atmel flashes */ #define CHIPC_SFLASH_AT_READ 0x07e8 #define CHIPC_SFLASH_AT_PAGE_READ 0x07d2 #define CHIPC_SFLASH_AT_BUF1_READ #define CHIPC_SFLASH_AT_BUF2_READ #define CHIPC_SFLASH_AT_STATUS 0x01d7 #define CHIPC_SFLASH_AT_BUF1_WRITE 0x0384 #define CHIPC_SFLASH_AT_BUF2_WRITE 0x0387 #define CHIPC_SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283 #define CHIPC_SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286 #define CHIPC_SFLASH_AT_BUF1_PROGRAM 0x0288 #define CHIPC_SFLASH_AT_BUF2_PROGRAM 0x0289 #define CHIPC_SFLASH_AT_PAGE_ERASE 0x0281 #define CHIPC_SFLASH_AT_BLOCK_ERASE 0x0250 #define CHIPC_SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382 #define CHIPC_SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385 #define CHIPC_SFLASH_AT_BUF1_LOAD 0x0253 #define CHIPC_SFLASH_AT_BUF2_LOAD 0x0255 #define CHIPC_SFLASH_AT_BUF1_COMPARE 0x0260 #define CHIPC_SFLASH_AT_BUF2_COMPARE 0x0261 #define CHIPC_SFLASH_AT_BUF1_REPROGRAM 0x0258 #define CHIPC_SFLASH_AT_BUF2_REPROGRAM 0x0259 /* Status register bits for Atmel flashes */ #define CHIPC_SFLASH_AT_READY 0x80 #define CHIPC_SFLASH_AT_MISMATCH 0x40 #define CHIPC_SFLASH_AT_ID_MASK 0x38 #define CHIPC_SFLASH_AT_ID_SHIFT 3 /* * These are the UART port assignments, expressed as offsets from the base * register. These assignments should hold for any serial port based on * a 8250, 16450, or 16550(A). */ #define CHIPC_UART_RX 0 /* In: Receive buffer (DLAB=0) */ #define CHIPC_UART_TX 0 /* Out: Transmit buffer (DLAB=0) */ #define CHIPC_UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */ #define CHIPC_UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */ #define CHIPC_UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */ #define CHIPC_UART_IIR 2 /* In: Interrupt Identity Register */ #define CHIPC_UART_FCR 2 /* Out: FIFO Control Register */ #define CHIPC_UART_LCR 3 /* Out: Line Control Register */ #define CHIPC_UART_MCR 4 /* Out: Modem Control Register */ #define CHIPC_UART_LSR 5 /* In: Line Status Register */ #define CHIPC_UART_MSR 6 /* In: Modem Status Register */ #define CHIPC_UART_SCR 7 /* I/O: Scratch Register */ #define CHIPC_UART_LCR_DLAB 0x80 /* Divisor latch access bit */ #define CHIPC_UART_LCR_WLEN8 0x03 /* Word length: 8 bits */ #define CHIPC_UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */ #define CHIPC_UART_MCR_LOOP 0x10 /* Enable loopback test mode */ #define CHIPC_UART_LSR_RX_FIFO 0x80 /* Receive FIFO error */ #define CHIPC_UART_LSR_TDHR 0x40 /* Data-hold-register empty */ #define CHIPC_UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ #define CHIPC_UART_LSR_BREAK 0x10 /* Break interrupt */ #define CHIPC_UART_LSR_FRAMING 0x08 /* Framing error */ #define CHIPC_UART_LSR_PARITY 0x04 /* Parity error */ #define CHIPC_UART_LSR_OVERRUN 0x02 /* Overrun error */ #define CHIPC_UART_LSR_RXRDY 0x01 /* Receiver ready */ #define CHIPC_UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */ /* Interrupt Identity Register (IIR) bits */ #define CHIPC_UART_IIR_FIFO_MASK 0xc0 /* IIR FIFO disable/enabled mask */ #define CHIPC_UART_IIR_INT_MASK 0xf /* IIR interrupt ID source */ #define CHIPC_UART_IIR_MDM_CHG 0x0 /* Modem status changed */ #define CHIPC_UART_IIR_NOINT 0x1 /* No interrupt pending */ #define CHIPC_UART_IIR_THRE 0x2 /* THR empty */ #define CHIPC_UART_IIR_RCVD_DATA 0x4 /* Received data available */ #define CHIPC_UART_IIR_RCVR_STATUS 0x6 /* Receiver status */ #define CHIPC_UART_IIR_CHAR_TIME 0xc /* Character time */ /* Interrupt Enable Register (IER) bits */ #define CHIPC_UART_IER_EDSSI 8 /* enable modem status interrupt */ #define CHIPC_UART_IER_ELSI 4 /* enable receiver line status interrupt */ #define CHIPC_UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */ #define CHIPC_UART_IER_ERBFI 1 /* enable data available interrupt */ /* pmustatus */ #define CHIPC_PST_EXTLPOAVAIL 0x0100 #define CHIPC_PST_WDRESET 0x0080 #define CHIPC_PST_INTPEND 0x0040 #define CHIPC_PST_SBCLKST 0x0030 #define CHIPC_PST_SBCLKST_ILP 0x0010 #define CHIPC_PST_SBCLKST_ALP 0x0020 #define CHIPC_PST_SBCLKST_HT 0x0030 #define CHIPC_PST_ALPAVAIL 0x0008 #define CHIPC_PST_HTAVAIL 0x0004 #define CHIPC_PST_RESINIT 0x0003 /* pmucapabilities */ #define CHIPC_PCAP_REV_MASK 0x000000ff #define CHIPC_PCAP_RC_MASK 0x00001f00 #define CHIPC_PCAP_RC_SHIFT 8 #define CHIPC_PCAP_TC_MASK 0x0001e000 #define CHIPC_PCAP_TC_SHIFT 13 #define CHIPC_PCAP_PC_MASK 0x001e0000 #define CHIPC_PCAP_PC_SHIFT 17 #define CHIPC_PCAP_VC_MASK 0x01e00000 #define CHIPC_PCAP_VC_SHIFT 21 #define CHIPC_PCAP_CC_MASK 0x1e000000 #define CHIPC_PCAP_CC_SHIFT 25 #define CHIPC_PCAP5_PC_MASK 0x003e0000 /* PMU corerev >= 5 */ #define CHIPC_PCAP5_PC_SHIFT 17 #define CHIPC_PCAP5_VC_MASK 0x07c00000 #define CHIPC_PCAP5_VC_SHIFT 22 #define CHIPC_PCAP5_CC_MASK 0xf8000000 #define CHIPC_PCAP5_CC_SHIFT 27 /* PMU Resource Request Timer registers */ /* This is based on PmuRev0 */ #define CHIPC_PRRT_TIME_MASK 0x03ff #define CHIPC_PRRT_INTEN 0x0400 #define CHIPC_PRRT_REQ_ACTIVE 0x0800 #define CHIPC_PRRT_ALP_REQ 0x1000 #define CHIPC_PRRT_HT_REQ 0x2000 /* PMU resource bit position */ #define CHIPC_PMURES_BIT(bit) (1 << (bit)) /* PMU resource number limit */ #define CHIPC_PMURES_MAX_RESNUM 30 /* PMU chip control0 register */ #define CHIPC_PMU_CHIPCTL0 0 /* PMU chip control1 register */ #define CHIPC_PMU_CHIPCTL1 1 #define CHIPC_PMU_CC1_RXC_DLL_BYPASS 0x00010000 #define CHIPC_PMU_CC1_IF_TYPE_MASK 0x00000030 #define CHIPC_PMU_CC1_IF_TYPE_RMII 0x00000000 #define CHIPC_PMU_CC1_IF_TYPE_MII 0x00000010 #define CHIPC_PMU_CC1_IF_TYPE_RGMII 0x00000020 #define CHIPC_PMU_CC1_SW_TYPE_MASK 0x000000c0 #define CHIPC_PMU_CC1_SW_TYPE_EPHY 0x00000000 #define CHIPC_PMU_CC1_SW_TYPE_EPHYMII 0x00000040 #define CHIPC_PMU_CC1_SW_TYPE_EPHYRMII 0x00000080 #define CHIPC_PMU_CC1_SW_TYPE_RGMII 0x000000c0 /* PMU corerev and chip specific PLL controls. * PMU_PLL_XX where is PMU corerev and is an arbitrary number * to differentiate different PLLs controlled by the same PMU rev. */ /* pllcontrol registers */ /* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */ #define CHIPC_PMU0_PLL0_PLLCTL0 0 #define CHIPC_PMU0_PLL0_PC0_PDIV_MASK 1 #define CHIPC_PMU0_PLL0_PC0_PDIV_FREQ 25000 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_SHIFT 3 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_BASE 8 /* PC0_DIV_ARM for PLLOUT_ARM */ #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_110MHZ 0 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_88MHZ 2 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */ #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7 /* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */ #define CHIPC_PMU0_PLL0_PLLCTL1 1 #define CHIPC_PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000 #define CHIPC_PMU0_PLL0_PC1_WILD_INT_SHIFT 28 #define CHIPC_PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00 #define CHIPC_PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8 #define CHIPC_PMU0_PLL0_PC1_STOP_MOD 0x00000040 /* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */ #define CHIPC_PMU0_PLL0_PLLCTL2 2 #define CHIPC_PMU0_PLL0_PC2_WILD_INT_MASK 0xf #define CHIPC_PMU0_PLL0_PC2_WILD_INT_SHIFT 4 /* pllcontrol registers */ /* ndiv_pwrdn, pwrdn_ch, refcomp_pwrdn, dly_ch, p1div, p2div, _bypass_sdmod */ #define CHIPC_PMU1_PLL0_PLLCTL0 0 #define CHIPC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 #define CHIPC_PMU1_PLL0_PC0_P1DIV_SHIFT 20 #define CHIPC_PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000 #define CHIPC_PMU1_PLL0_PC0_P2DIV_SHIFT 24 /* mdiv */ #define CHIPC_PMU1_PLL0_PLLCTL1 1 #define CHIPC_PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff #define CHIPC_PMU1_PLL0_PC1_M1DIV_SHIFT 0 #define CHIPC_PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00 #define CHIPC_PMU1_PLL0_PC1_M2DIV_SHIFT 8 #define CHIPC_PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000 #define CHIPC_PMU1_PLL0_PC1_M3DIV_SHIFT 16 #define CHIPC_PMU1_PLL0_PC1_M4DIV_MASK 0xff000000 #define CHIPC_PMU1_PLL0_PC1_M4DIV_SHIFT 24 #define CHIPC_DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8 #define CHIPC_DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) #define CHIPC_DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) /* mdiv, ndiv_dither_mfb, ndiv_mode, ndiv_int */ #define CHIPC_PMU1_PLL0_PLLCTL2 2 #define CHIPC_PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff #define CHIPC_PMU1_PLL0_PC2_M5DIV_SHIFT 0 #define CHIPC_PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00 #define CHIPC_PMU1_PLL0_PC2_M6DIV_SHIFT 8 #define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000 #define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17 #define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_MASH 1 #define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_MFB 2 /* recommended for 4319 */ #define CHIPC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 #define CHIPC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 /* ndiv_frac */ #define CHIPC_PMU1_PLL0_PLLCTL3 3 #define CHIPC_PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff #define CHIPC_PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0 /* pll_ctrl */ #define CHIPC_PMU1_PLL0_PLLCTL4 4 /* pll_ctrl, vco_rng, clkdrive_ch */ #define CHIPC_PMU1_PLL0_PLLCTL5 5 #define CHIPC_PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00 #define CHIPC_PMU1_PLL0_PC5_CLK_DRV_SHIFT 8 /* PMU rev 2 control words */ #define CHIPC_PMU2_PHY_PLL_PLLCTL 4 #define CHIPC_PMU2_SI_PLL_PLLCTL 10 /* PMU rev 2 */ /* pllcontrol registers */ /* ndiv_pwrdn, pwrdn_ch, refcomp_pwrdn, dly_ch, p1div, p2div, _bypass_sdmod */ #define CHIPC_PMU2_PLL_PLLCTL0 0 #define CHIPC_PMU2_PLL_PC0_P1DIV_MASK 0x00f00000 #define CHIPC_PMU2_PLL_PC0_P1DIV_SHIFT 20 #define CHIPC_PMU2_PLL_PC0_P2DIV_MASK 0x0f000000 #define CHIPC_PMU2_PLL_PC0_P2DIV_SHIFT 24 /* mdiv */ #define CHIPC_PMU2_PLL_PLLCTL1 1 #define CHIPC_PMU2_PLL_PC1_M1DIV_MASK 0x000000ff #define CHIPC_PMU2_PLL_PC1_M1DIV_SHIFT 0 #define CHIPC_PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00 #define CHIPC_PMU2_PLL_PC1_M2DIV_SHIFT 8 #define CHIPC_PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000 #define CHIPC_PMU2_PLL_PC1_M3DIV_SHIFT 16 #define CHIPC_PMU2_PLL_PC1_M4DIV_MASK 0xff000000 #define CHIPC_PMU2_PLL_PC1_M4DIV_SHIFT 24 /* mdiv, ndiv_dither_mfb, ndiv_mode, ndiv_int */ #define CHIPC_PMU2_PLL_PLLCTL2 2 #define CHIPC_PMU2_PLL_PC2_M5DIV_MASK 0x000000ff #define CHIPC_PMU2_PLL_PC2_M5DIV_SHIFT 0 #define CHIPC_PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00 #define CHIPC_PMU2_PLL_PC2_M6DIV_SHIFT 8 #define CHIPC_PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000 #define CHIPC_PMU2_PLL_PC2_NDIV_MODE_SHIFT 17 #define CHIPC_PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000 #define CHIPC_PMU2_PLL_PC2_NDIV_INT_SHIFT 20 /* ndiv_frac */ #define CHIPC_PMU2_PLL_PLLCTL3 3 #define CHIPC_PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff #define CHIPC_PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0 /* pll_ctrl */ #define CHIPC_PMU2_PLL_PLLCTL4 4 /* pll_ctrl, vco_rng, clkdrive_ch */ #define CHIPC_PMU2_PLL_PLLCTL5 5 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28 /* PMU rev 5 (& 6) */ #define CHIPC_PMU5_PLL_P1P2_OFF 0 #define CHIPC_PMU5_PLL_P1_MASK 0x0f000000 #define CHIPC_PMU5_PLL_P1_SHIFT 24 #define CHIPC_PMU5_PLL_P2_MASK 0x00f00000 #define CHIPC_PMU5_PLL_P2_SHIFT 20 #define CHIPC_PMU5_PLL_M14_OFF 1 #define CHIPC_PMU5_PLL_MDIV_MASK 0x000000ff #define CHIPC_PMU5_PLL_MDIV_WIDTH 8 #define CHIPC_PMU5_PLL_NM5_OFF 2 #define CHIPC_PMU5_PLL_NDIV_MASK 0xfff00000 #define CHIPC_PMU5_PLL_NDIV_SHIFT 20 #define CHIPC_PMU5_PLL_NDIV_MODE_MASK 0x000e0000 #define CHIPC_PMU5_PLL_NDIV_MODE_SHIFT 17 #define CHIPC_PMU5_PLL_FMAB_OFF 3 #define CHIPC_PMU5_PLL_MRAT_MASK 0xf0000000 #define CHIPC_PMU5_PLL_MRAT_SHIFT 28 #define CHIPC_PMU5_PLL_ABRAT_MASK 0x08000000 #define CHIPC_PMU5_PLL_ABRAT_SHIFT 27 #define CHIPC_PMU5_PLL_FDIV_MASK 0x07ffffff #define CHIPC_PMU5_PLL_PLLCTL_OFF 4 #define CHIPC_PMU5_PLL_PCHI_OFF 5 #define CHIPC_PMU5_PLL_PCHI_MASK 0x0000003f /* pmu XtalFreqRatio */ #define CHIPC_PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF #define CHIPC_PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000 #define CHIPC_PMU_XTALFREQ_REG_MEASURE_SHIFT 31 /* Divider allocation in 4716/47162/5356/5357 */ #define CHIPC_PMU5_MAINPLL_CPU 1 #define CHIPC_PMU5_MAINPLL_MEM 2 #define CHIPC_PMU5_MAINPLL_SI 3 #define CHIPC_PMU7_PLL_PLLCTL7 7 #define CHIPC_PMU7_PLL_PLLCTL8 8 #define CHIPC_PMU7_PLL_PLLCTL11 11 /* PLL usage in 4716/47162 */ #define CHIPC_PMU4716_MAINPLL_PLL0 12 /* PLL usage in 5356/5357 */ #define CHIPC_PMU5356_MAINPLL_PLL0 0 #define CHIPC_PMU5357_MAINPLL_PLL0 0 /* 4716/47162 resources */ #define CHIPC_RES4716_PROC_PLL_ON 0x00000040 #define CHIPC_RES4716_PROC_HT_AVAIL 0x00000080 /* 4716/4717/4718 Chip specific ChipControl register bits */ #define CHIPC_CCTRL471X_I2S_PINS_ENABLE 0x0080 /* I2S pins off by default, shared with pflash */ /* 5354 resources */ #define CHIPC_RES5354_EXT_SWITCHER_PWM 0 /* 0x00001 */ #define CHIPC_RES5354_BB_SWITCHER_PWM 1 /* 0x00002 */ #define CHIPC_RES5354_BB_SWITCHER_BURST 2 /* 0x00004 */ #define CHIPC_RES5354_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ #define CHIPC_RES5354_ILP_REQUEST 4 /* 0x00010 */ #define CHIPC_RES5354_RADIO_SWITCHER_PWM 5 /* 0x00020 */ #define CHIPC_RES5354_RADIO_SWITCHER_BURST 6 /* 0x00040 */ #define CHIPC_RES5354_ROM_SWITCH 7 /* 0x00080 */ #define CHIPC_RES5354_PA_REF_LDO 8 /* 0x00100 */ #define CHIPC_RES5354_RADIO_LDO 9 /* 0x00200 */ #define CHIPC_RES5354_AFE_LDO 10 /* 0x00400 */ #define CHIPC_RES5354_PLL_LDO 11 /* 0x00800 */ #define CHIPC_RES5354_BG_FILTBYP 12 /* 0x01000 */ #define CHIPC_RES5354_TX_FILTBYP 13 /* 0x02000 */ #define CHIPC_RES5354_RX_FILTBYP 14 /* 0x04000 */ #define CHIPC_RES5354_XTAL_PU 15 /* 0x08000 */ #define CHIPC_RES5354_XTAL_EN 16 /* 0x10000 */ #define CHIPC_RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */ #define CHIPC_RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */ #define CHIPC_RES5354_BB_PLL_PU 19 /* 0x80000 */ /* 5357 Chip specific ChipControl register bits */ #define CHIPC_CCTRL5357_EXTPA (1<<14) /* extPA in ChipControl 1, bit 14 */ #define CHIPC_CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in ChipControl 1, bit 15 */ /* 4328 resources */ #define CHIPC_RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */ #define CHIPC_RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */ #define CHIPC_RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */ #define CHIPC_RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ #define CHIPC_RES4328_ILP_REQUEST 4 /* 0x00010 */ #define CHIPC_RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */ #define CHIPC_RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */ #define CHIPC_RES4328_ROM_SWITCH 7 /* 0x00080 */ #define CHIPC_RES4328_PA_REF_LDO 8 /* 0x00100 */ #define CHIPC_RES4328_RADIO_LDO 9 /* 0x00200 */ #define CHIPC_RES4328_AFE_LDO 10 /* 0x00400 */ #define CHIPC_RES4328_PLL_LDO 11 /* 0x00800 */ #define CHIPC_RES4328_BG_FILTBYP 12 /* 0x01000 */ #define CHIPC_RES4328_TX_FILTBYP 13 /* 0x02000 */ #define CHIPC_RES4328_RX_FILTBYP 14 /* 0x04000 */ #define CHIPC_RES4328_XTAL_PU 15 /* 0x08000 */ #define CHIPC_RES4328_XTAL_EN 16 /* 0x10000 */ #define CHIPC_RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */ #define CHIPC_RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */ #define CHIPC_RES4328_BB_PLL_PU 19 /* 0x80000 */ /* 4325 A0/A1 resources */ #define CHIPC_RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */ #define CHIPC_RES4325_CBUCK_BURST 1 /* 0x00000002 */ #define CHIPC_RES4325_CBUCK_PWM 2 /* 0x00000004 */ #define CHIPC_RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */ #define CHIPC_RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */ #define CHIPC_RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */ #define CHIPC_RES4325_ILP_REQUEST 6 /* 0x00000040 */ #define CHIPC_RES4325_ABUCK_BURST 7 /* 0x00000080 */ #define CHIPC_RES4325_ABUCK_PWM 8 /* 0x00000100 */ #define CHIPC_RES4325_LNLDO1_PU 9 /* 0x00000200 */ #define CHIPC_RES4325_OTP_PU 10 /* 0x00000400 */ #define CHIPC_RES4325_LNLDO3_PU 11 /* 0x00000800 */ #define CHIPC_RES4325_LNLDO4_PU 12 /* 0x00001000 */ #define CHIPC_RES4325_XTAL_PU 13 /* 0x00002000 */ #define CHIPC_RES4325_ALP_AVAIL 14 /* 0x00004000 */ #define CHIPC_RES4325_RX_PWRSW_PU 15 /* 0x00008000 */ #define CHIPC_RES4325_TX_PWRSW_PU 16 /* 0x00010000 */ #define CHIPC_RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */ #define CHIPC_RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */ #define CHIPC_RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */ #define CHIPC_RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */ #define CHIPC_RES4325_HT_AVAIL 21 /* 0x00200000 */ /* 4325 B0/C0 resources */ #define CHIPC_RES4325B0_CBUCK_LPOM 1 /* 0x00000002 */ #define CHIPC_RES4325B0_CBUCK_BURST 2 /* 0x00000004 */ #define CHIPC_RES4325B0_CBUCK_PWM 3 /* 0x00000008 */ #define CHIPC_RES4325B0_CLDO_PU 4 /* 0x00000010 */ /* 4325 C1 resources */ #define CHIPC_RES4325C1_LNLDO2_PU 12 /* 0x00001000 */ /* 4325 chip-specific ChipStatus register bits */ #define CHIPC_CST4325_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK #define CHIPC_CST4325_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT #define CHIPC_CST4325_SDIO_USB_MODE_MASK 0x00000004 #define CHIPC_CST4325_SDIO_USB_MODE_SHIFT 2 #define CHIPC_CST4325_RCAL_VALID_MASK 0x00000008 #define CHIPC_CST4325_RCAL_VALID_SHIFT 3 #define CHIPC_CST4325_RCAL_VALUE_MASK 0x000001f0 #define CHIPC_CST4325_RCAL_VALUE_SHIFT 4 #define CHIPC_CST4325_PMUTOP_2B_MASK 0x00000200 /* 1 for 2b, 0 for to 2a */ #define CHIPC_CST4325_PMUTOP_2B_SHIFT 9 #define CHIPC_RES4329_RESERVED0 0 /* 0x00000001 */ #define CHIPC_RES4329_CBUCK_LPOM 1 /* 0x00000002 */ #define CHIPC_RES4329_CBUCK_BURST 2 /* 0x00000004 */ #define CHIPC_RES4329_CBUCK_PWM 3 /* 0x00000008 */ #define CHIPC_RES4329_CLDO_PU 4 /* 0x00000010 */ #define CHIPC_RES4329_PALDO_PU 5 /* 0x00000020 */ #define CHIPC_RES4329_ILP_REQUEST 6 /* 0x00000040 */ #define CHIPC_RES4329_RESERVED7 7 /* 0x00000080 */ #define CHIPC_RES4329_RESERVED8 8 /* 0x00000100 */ #define CHIPC_RES4329_LNLDO1_PU 9 /* 0x00000200 */ #define CHIPC_RES4329_OTP_PU 10 /* 0x00000400 */ #define CHIPC_RES4329_RESERVED11 11 /* 0x00000800 */ #define CHIPC_RES4329_LNLDO2_PU 12 /* 0x00001000 */ #define CHIPC_RES4329_XTAL_PU 13 /* 0x00002000 */ #define CHIPC_RES4329_ALP_AVAIL 14 /* 0x00004000 */ #define CHIPC_RES4329_RX_PWRSW_PU 15 /* 0x00008000 */ #define CHIPC_RES4329_TX_PWRSW_PU 16 /* 0x00010000 */ #define CHIPC_RES4329_RFPLL_PWRSW_PU 17 /* 0x00020000 */ #define CHIPC_RES4329_LOGEN_PWRSW_PU 18 /* 0x00040000 */ #define CHIPC_RES4329_AFE_PWRSW_PU 19 /* 0x00080000 */ #define CHIPC_RES4329_BBPLL_PWRSW_PU 20 /* 0x00100000 */ #define CHIPC_RES4329_HT_AVAIL 21 /* 0x00200000 */ /* 4329 chip-specific ChipStatus register bits */ #define CHIPC_CST4329_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK #define CHIPC_CST4329_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT #define CHIPC_CST4329_SPI_SDIO_MODE_MASK 0x00000004 #define CHIPC_CST4329_SPI_SDIO_MODE_SHIFT 2 /* 4312 chip-specific ChipStatus register bits */ #define CHIPC_CST4312_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK #define CHIPC_CST4312_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT /* 4312 resources (all PMU chips with little memory constraint) */ #define CHIPC_RES4312_SWITCHER_BURST 0 /* 0x00000001 */ #define CHIPC_RES4312_SWITCHER_PWM 1 /* 0x00000002 */ #define CHIPC_RES4312_PA_REF_LDO 2 /* 0x00000004 */ #define CHIPC_RES4312_CORE_LDO_BURST 3 /* 0x00000008 */ #define CHIPC_RES4312_CORE_LDO_PWM 4 /* 0x00000010 */ #define CHIPC_RES4312_RADIO_LDO 5 /* 0x00000020 */ #define CHIPC_RES4312_ILP_REQUEST 6 /* 0x00000040 */ #define CHIPC_RES4312_BG_FILTBYP 7 /* 0x00000080 */ #define CHIPC_RES4312_TX_FILTBYP 8 /* 0x00000100 */ #define CHIPC_RES4312_RX_FILTBYP 9 /* 0x00000200 */ #define CHIPC_RES4312_XTAL_PU 10 /* 0x00000400 */ #define CHIPC_RES4312_ALP_AVAIL 11 /* 0x00000800 */ #define CHIPC_RES4312_BB_PLL_FILTBYP 12 /* 0x00001000 */ #define CHIPC_RES4312_RF_PLL_FILTBYP 13 /* 0x00002000 */ #define CHIPC_RES4312_HT_AVAIL 14 /* 0x00004000 */ /* 4322 resources */ #define CHIPC_RES4322_RF_LDO 0 #define CHIPC_RES4322_ILP_REQUEST 1 #define CHIPC_RES4322_XTAL_PU 2 #define CHIPC_RES4322_ALP_AVAIL 3 #define CHIPC_RES4322_SI_PLL_ON 4 #define CHIPC_RES4322_HT_SI_AVAIL 5 #define CHIPC_RES4322_PHY_PLL_ON 6 #define CHIPC_RES4322_HT_PHY_AVAIL 7 #define CHIPC_RES4322_OTP_PU 8 /* 4322 chip-specific ChipStatus register bits */ #define CHIPC_CST4322_XTAL_FREQ_20_40MHZ 0x00000020 #define CHIPC_CST4322_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R23_MASK #define CHIPC_CST4322_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT #define CHIPC_CST4322_PCI_OR_USB 0x00000100 #define CHIPC_CST4322_BOOT_MASK 0x00000600 #define CHIPC_CST4322_BOOT_SHIFT 9 #define CHIPC_CST4322_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ #define CHIPC_CST4322_BOOT_FROM_ROM 1 /* boot from ROM */ #define CHIPC_CST4322_BOOT_FROM_FLASH 2 /* boot from FLASH */ #define CHIPC_CST4322_BOOT_FROM_INVALID 3 #define CHIPC_CST4322_ILP_DIV_EN 0x00000800 #define CHIPC_CST4322_FLASH_TYPE_MASK 0x00001000 #define CHIPC_CST4322_FLASH_TYPE_SHIFT 12 #define CHIPC_CST4322_FLASH_TYPE_SHIFT_ST 0 /* ST serial FLASH */ #define CHIPC_CST4322_FLASH_TYPE_SHIFT_ATMEL 1 /* ATMEL flash */ #define CHIPC_CST4322_ARM_TAP_SEL 0x00002000 #define CHIPC_CST4322_RES_INIT_MODE_MASK 0x0000c000 #define CHIPC_CST4322_RES_INIT_MODE_SHIFT 14 #define CHIPC_CST4322_RES_INIT_MODE_ILPAVAIL 0 /* resinitmode: ILP available */ #define CHIPC_CST4322_RES_INIT_MODE_ILPREQ 1 /* resinitmode: ILP request */ #define CHIPC_CST4322_RES_INIT_MODE_ALPAVAIL 2 /* resinitmode: ALP available */ #define CHIPC_CST4322_RES_INIT_MODE_HTAVAIL 3 /* resinitmode: HT available */ #define CHIPC_CST4322_PCIPLLCLK_GATING 0x00010000 #define CHIPC_CST4322_CLK_SWITCH_PCI_TO_ALP 0x00020000 #define CHIPC_CST4322_PCI_CARDBUS_MODE 0x00040000 /* 43224 chip-specific ChipControl register bits */ #define CHIPC_CCTRL43224_GPIO_TOGGLE 0x8000 #define CHIPC_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */ #define CHIPC_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */ /* 43236 resources */ #define CHIPC_RES43236_REGULATOR 0 #define CHIPC_RES43236_ILP_REQUEST 1 #define CHIPC_RES43236_XTAL_PU 2 #define CHIPC_RES43236_ALP_AVAIL 3 #define CHIPC_RES43236_SI_PLL_ON 4 #define CHIPC_RES43236_HT_SI_AVAIL 5 /* 43236 chip-specific ChipControl register bits */ #define CHIPC_CCTRL43236_BT_COEXIST (1<<0) /* 0 disable */ #define CHIPC_CCTRL43236_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ #define CHIPC_CCTRL43236_EXT_LNA (1<<2) /* 0 disable */ #define CHIPC_CCTRL43236_ANT_MUX_2o3 (1<<3) /* 2o3 mux, chipcontrol bit 3 */ #define CHIPC_CCTRL43236_GSIO (1<<4) /* 0 disable */ /* 43236 Chip specific ChipStatus register bits */ #define CHIPC_CST43236_SFLASH_MASK 0x00000040 #define CHIPC_CST43236_OTP_SEL_MASK 0x00000080 #define CHIPC_CST43236_OTP_SEL_SHIFT 7 #define CHIPC_CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */ #define CHIPC_CST43236_BP_CLK 0x00000200 /* 120/96Mbps */ #define CHIPC_CST43236_BOOT_MASK 0x00001800 #define CHIPC_CST43236_BOOT_SHIFT 11 #define CHIPC_CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ #define CHIPC_CST43236_BOOT_FROM_ROM 1 /* boot from ROM */ #define CHIPC_CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */ #define CHIPC_CST43236_BOOT_FROM_INVALID 3 /* 4331 resources */ #define CHIPC_RES4331_REGULATOR 0 #define CHIPC_RES4331_ILP_REQUEST 1 #define CHIPC_RES4331_XTAL_PU 2 #define CHIPC_RES4331_ALP_AVAIL 3 #define CHIPC_RES4331_SI_PLL_ON 4 #define CHIPC_RES4331_HT_SI_AVAIL 5 /* 4331 chip-specific ChipControl register bits */ #define CHIPC_CCTRL4331_BT_COEXIST (1<<0) /* 0 disable */ #define CHIPC_CCTRL4331_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ #define CHIPC_CCTRL4331_EXT_LNA (1<<2) /* 0 disable */ #define CHIPC_CCTRL4331_SPROM_GPIO13_15 (1<<3) /* sprom/gpio13-15 mux */ #define CHIPC_CCTRL4331_EXTPA_EN (1<<4) /* 0 ext pa disable, 1 ext pa enabled */ #define CHIPC_CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5) /* set drive out GPIO_CLK on sprom_cs pin */ #define CHIPC_CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6) /* use sprom_cs pin as PCIE mdio interface */ #define CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7) /* aband extpa will be at gpio2/5 and sprom_dout */ #define CHIPC_CCTRL4331_OVR_PIPEAUXCLKEN (1<<8) /* override core control on pipe_AuxClkEnable */ #define CHIPC_CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9) /* override core control on pipe_AuxPowerDown */ #define CHIPC_CCTRL4331_PCIE_AUXCLKEN (1<<10) /* pcie_auxclkenable */ #define CHIPC_CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11) /* pcie_pipe_pllpowerdown */ #define CHIPC_CCTRL4331_EXTPA_EN2 (1<<12) /* 0 ext pa2 disable, 1 ext pa2 enabled */ #define CHIPC_CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16) /* enable bt_shd0 at gpio4 */ #define CHIPC_CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17) /* enable bt_shd1 at gpio5 */ /* 4331 Chip specific ChipStatus register bits */ #define CHIPC_CST4331_XTAL_FREQ 0x00000001 /* crystal frequency 20/40Mhz */ #define CHIPC_CST4331_SPROM_PRESENT 0x00000002 #define CHIPC_CST4331_OTP_PRESENT 0x00000004 #define CHIPC_CST4331_LDO_RF 0x00000008 #define CHIPC_CST4331_LDO_PAR 0x00000010 /* 4315 resources */ #define CHIPC_RES4315_CBUCK_LPOM 1 /* 0x00000002 */ #define CHIPC_RES4315_CBUCK_BURST 2 /* 0x00000004 */ #define CHIPC_RES4315_CBUCK_PWM 3 /* 0x00000008 */ #define CHIPC_RES4315_CLDO_PU 4 /* 0x00000010 */ #define CHIPC_RES4315_PALDO_PU 5 /* 0x00000020 */ #define CHIPC_RES4315_ILP_REQUEST 6 /* 0x00000040 */ #define CHIPC_RES4315_LNLDO1_PU 9 /* 0x00000200 */ #define CHIPC_RES4315_OTP_PU 10 /* 0x00000400 */ #define CHIPC_RES4315_LNLDO2_PU 12 /* 0x00001000 */ #define CHIPC_RES4315_XTAL_PU 13 /* 0x00002000 */ #define CHIPC_RES4315_ALP_AVAIL 14 /* 0x00004000 */ #define CHIPC_RES4315_RX_PWRSW_PU 15 /* 0x00008000 */ #define CHIPC_RES4315_TX_PWRSW_PU 16 /* 0x00010000 */ #define CHIPC_RES4315_RFPLL_PWRSW_PU 17 /* 0x00020000 */ #define CHIPC_RES4315_LOGEN_PWRSW_PU 18 /* 0x00040000 */ #define CHIPC_RES4315_AFE_PWRSW_PU 19 /* 0x00080000 */ #define CHIPC_RES4315_BBPLL_PWRSW_PU 20 /* 0x00100000 */ #define CHIPC_RES4315_HT_AVAIL 21 /* 0x00200000 */ /* 4315 chip-specific ChipStatus register bits */ #define CHIPC_CST4315_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK #define CHIPC_CST4315_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT #define CHIPC_CST4315_SDIO_MODE 0x00000004 /* gpio [8], sdio/usb mode */ #define CHIPC_CST4315_RCAL_VALID 0x00000008 #define CHIPC_CST4315_RCAL_VALUE_MASK 0x000001f0 #define CHIPC_CST4315_RCAL_VALUE_SHIFT 4 #define CHIPC_CST4315_PALDO_EXTPNP 0x00000200 /* PALDO is configured with external PNP */ #define CHIPC_CST4315_CBUCK_MODE_MASK 0x00000c00 #define CHIPC_CST4315_CBUCK_MODE_BURST 0x00000400 #define CHIPC_CST4315_CBUCK_MODE_LPBURST 0x00000c00 /* 4319 resources */ #define CHIPC_RES4319_CBUCK_LPOM 1 /* 0x00000002 */ #define CHIPC_RES4319_CBUCK_BURST 2 /* 0x00000004 */ #define CHIPC_RES4319_CBUCK_PWM 3 /* 0x00000008 */ #define CHIPC_RES4319_CLDO_PU 4 /* 0x00000010 */ #define CHIPC_RES4319_PALDO_PU 5 /* 0x00000020 */ #define CHIPC_RES4319_ILP_REQUEST 6 /* 0x00000040 */ #define CHIPC_RES4319_LNLDO1_PU 9 /* 0x00000200 */ #define CHIPC_RES4319_OTP_PU 10 /* 0x00000400 */ #define CHIPC_RES4319_LNLDO2_PU 12 /* 0x00001000 */ #define CHIPC_RES4319_XTAL_PU 13 /* 0x00002000 */ #define CHIPC_RES4319_ALP_AVAIL 14 /* 0x00004000 */ #define CHIPC_RES4319_RX_PWRSW_PU 15 /* 0x00008000 */ #define CHIPC_RES4319_TX_PWRSW_PU 16 /* 0x00010000 */ #define CHIPC_RES4319_RFPLL_PWRSW_PU 17 /* 0x00020000 */ #define CHIPC_RES4319_LOGEN_PWRSW_PU 18 /* 0x00040000 */ #define CHIPC_RES4319_AFE_PWRSW_PU 19 /* 0x00080000 */ #define CHIPC_RES4319_BBPLL_PWRSW_PU 20 /* 0x00100000 */ #define CHIPC_RES4319_HT_AVAIL 21 /* 0x00200000 */ /* 4319 chip-specific ChipStatus register bits */ #define CHIPC_CST4319_SPI_CPULESSUSB 0x00000001 #define CHIPC_CST4319_SPI_CLK_POL 0x00000002 #define CHIPC_CST4319_SPI_CLK_PH 0x00000008 #define CHIPC_CST4319_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R23_MASK /* gpio [7:6], SDIO CIS selection */ #define CHIPC_CST4319_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT #define CHIPC_CST4319_SDIO_USB_MODE 0x00000100 /* gpio [8], sdio/usb mode */ #define CHIPC_CST4319_REMAP_SEL_MASK 0x00000600 #define CHIPC_CST4319_ILPDIV_EN 0x00000800 #define CHIPC_CST4319_XTAL_PD_POL 0x00001000 #define CHIPC_CST4319_LPO_SEL 0x00002000 #define CHIPC_CST4319_RES_INIT_MODE 0x0000c000 #define CHIPC_CST4319_PALDO_EXTPNP 0x00010000 /* PALDO is configured with external PNP */ #define CHIPC_CST4319_CBUCK_MODE_MASK 0x00060000 #define CHIPC_CST4319_CBUCK_MODE_BURST 0x00020000 #define CHIPC_CST4319_CBUCK_MODE_LPBURST 0x00060000 #define CHIPC_CST4319_RCAL_VALID 0x01000000 #define CHIPC_CST4319_RCAL_VALUE_MASK 0x3e000000 #define CHIPC_CST4319_RCAL_VALUE_SHIFT 25 #define CHIPC_PMU1_PLL0_CHIPCTL0 0 #define CHIPC_PMU1_PLL0_CHIPCTL1 1 #define CHIPC_PMU1_PLL0_CHIPCTL2 2 #define CHIPC_CCTL_4319USB_XTAL_SEL_MASK 0x00180000 #define CHIPC_CCTL_4319USB_XTAL_SEL_SHIFT 19 #define CHIPC_CCTL_4319USB_48MHZ_PLL_SEL 1 #define CHIPC_CCTL_4319USB_24MHZ_PLL_SEL 2 /* PMU resources for 4336 */ #define CHIPC_RES4336_CBUCK_LPOM 0 #define CHIPC_RES4336_CBUCK_BURST 1 #define CHIPC_RES4336_CBUCK_LP_PWM 2 #define CHIPC_RES4336_CBUCK_PWM 3 #define CHIPC_RES4336_CLDO_PU 4 #define CHIPC_RES4336_DIS_INT_RESET_PD 5 #define CHIPC_RES4336_ILP_REQUEST 6 #define CHIPC_RES4336_LNLDO_PU 7 #define CHIPC_RES4336_LDO3P3_PU 8 #define CHIPC_RES4336_OTP_PU 9 #define CHIPC_RES4336_XTAL_PU 10 #define CHIPC_RES4336_ALP_AVAIL 11 #define CHIPC_RES4336_RADIO_PU 12 #define CHIPC_RES4336_BG_PU 13 #define CHIPC_RES4336_VREG1p4_PU_PU 14 #define CHIPC_RES4336_AFE_PWRSW_PU 15 #define CHIPC_RES4336_RX_PWRSW_PU 16 #define CHIPC_RES4336_TX_PWRSW_PU 17 #define CHIPC_RES4336_BB_PWRSW_PU 18 #define CHIPC_RES4336_SYNTH_PWRSW_PU 19 #define CHIPC_RES4336_MISC_PWRSW_PU 20 #define CHIPC_RES4336_LOGEN_PWRSW_PU 21 #define CHIPC_RES4336_BBPLL_PWRSW_PU 22 #define CHIPC_RES4336_MACPHY_CLKAVAIL 23 #define CHIPC_RES4336_HT_AVAIL 24 #define CHIPC_RES4336_RSVD 25 /* 4336 chip-specific ChipStatus register bits */ #define CHIPC_CST4336_SPI_MODE_MASK 0x00000001 #define CHIPC_CST4336_SPROM_PRESENT 0x00000002 #define CHIPC_CST4336_OTP_PRESENT 0x00000004 #define CHIPC_CST4336_ARMREMAP_0 0x00000008 #define CHIPC_CST4336_ILPDIV_EN_MASK 0x00000010 #define CHIPC_CST4336_ILPDIV_EN_SHIFT 4 #define CHIPC_CST4336_XTAL_PD_POL_MASK 0x00000020 #define CHIPC_CST4336_XTAL_PD_POL_SHIFT 5 #define CHIPC_CST4336_LPO_SEL_MASK 0x00000040 #define CHIPC_CST4336_LPO_SEL_SHIFT 6 #define CHIPC_CST4336_RES_INIT_MODE_MASK 0x00000180 #define CHIPC_CST4336_RES_INIT_MODE_SHIFT 7 #define CHIPC_CST4336_CBUCK_MODE_MASK 0x00000600 #define CHIPC_CST4336_CBUCK_MODE_SHIFT 9 /* 4330 resources */ #define CHIPC_RES4330_CBUCK_LPOM 0 #define CHIPC_RES4330_CBUCK_BURST 1 #define CHIPC_RES4330_CBUCK_LP_PWM 2 #define CHIPC_RES4330_CBUCK_PWM 3 #define CHIPC_RES4330_CLDO_PU 4 #define CHIPC_RES4330_DIS_INT_RESET_PD 5 #define CHIPC_RES4330_ILP_REQUEST 6 #define CHIPC_RES4330_LNLDO_PU 7 #define CHIPC_RES4330_LDO3P3_PU 8 #define CHIPC_RES4330_OTP_PU 9 #define CHIPC_RES4330_XTAL_PU 10 #define CHIPC_RES4330_ALP_AVAIL 11 #define CHIPC_RES4330_RADIO_PU 12 #define CHIPC_RES4330_BG_PU 13 #define CHIPC_RES4330_VREG1p4_PU_PU 14 #define CHIPC_RES4330_AFE_PWRSW_PU 15 #define CHIPC_RES4330_RX_PWRSW_PU 16 #define CHIPC_RES4330_TX_PWRSW_PU 17 #define CHIPC_RES4330_BB_PWRSW_PU 18 #define CHIPC_RES4330_SYNTH_PWRSW_PU 19 #define CHIPC_RES4330_MISC_PWRSW_PU 20 #define CHIPC_RES4330_LOGEN_PWRSW_PU 21 #define CHIPC_RES4330_BBPLL_PWRSW_PU 22 #define CHIPC_RES4330_MACPHY_CLKAVAIL 23 #define CHIPC_RES4330_HT_AVAIL 24 #define CHIPC_RES4330_5gRX_PWRSW_PU 25 #define CHIPC_RES4330_5gTX_PWRSW_PU 26 #define CHIPC_RES4330_5g_LOGEN_PWRSW_PU 27 /* 4330 chip-specific ChipStatus register bits */ #define CHIPC_CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6) /* SDIO || gSPI */ #define CHIPC_CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6) /* USB || USBDA */ #define CHIPC_CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0) /* SDIO */ #define CHIPC_CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4) /* gSPI */ #define CHIPC_CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6) /* USB packet-oriented */ #define CHIPC_CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7) /* USB Direct Access */ #define CHIPC_CST4330_OTP_PRESENT 0x00000010 #define CHIPC_CST4330_LPO_AUTODET_EN 0x00000020 #define CHIPC_CST4330_ARMREMAP_0 0x00000040 #define CHIPC_CST4330_SPROM_PRESENT 0x00000080 /* takes priority over OTP if both set */ #define CHIPC_CST4330_ILPDIV_EN 0x00000100 #define CHIPC_CST4330_LPO_SEL 0x00000200 #define CHIPC_CST4330_RES_INIT_MODE_SHIFT 10 #define CHIPC_CST4330_RES_INIT_MODE_MASK 0x00000c00 #define CHIPC_CST4330_CBUCK_MODE_SHIFT 12 #define CHIPC_CST4330_CBUCK_MODE_MASK 0x00003000 #define CHIPC_CST4330_CBUCK_POWER_OK 0x00004000 #define CHIPC_CST4330_BB_PLL_LOCKED 0x00008000 #define CHIPC_SOCDEVRAM_4330_BP_ADDR 0x1E000000 #define CHIPC_SOCDEVRAM_4330_ARM_ADDR 0x00800000 /* 4313 resources */ #define CHIPC_RES4313_BB_PU_RSRC 0 #define CHIPC_RES4313_ILP_REQ_RSRC 1 #define CHIPC_RES4313_XTAL_PU_RSRC 2 #define CHIPC_RES4313_ALP_AVAIL_RSRC 3 #define CHIPC_RES4313_RADIO_PU_RSRC 4 #define CHIPC_RES4313_BG_PU_RSRC 5 #define CHIPC_RES4313_VREG1P4_PU_RSRC 6 #define CHIPC_RES4313_AFE_PWRSW_RSRC 7 #define CHIPC_RES4313_RX_PWRSW_RSRC 8 #define CHIPC_RES4313_TX_PWRSW_RSRC 9 #define CHIPC_RES4313_BB_PWRSW_RSRC 10 #define CHIPC_RES4313_SYNTH_PWRSW_RSRC 11 #define CHIPC_RES4313_MISC_PWRSW_RSRC 12 #define CHIPC_RES4313_BB_PLL_PWRSW_RSRC 13 #define CHIPC_RES4313_HT_AVAIL_RSRC 14 #define CHIPC_RES4313_MACPHY_CLK_AVAIL_RSRC 15 /* 4313 chip-specific ChipStatus register bits */ #define CHIPC_CST4313_SPROM_PRESENT 1 #define CHIPC_CST4313_OTP_PRESENT 2 #define CHIPC_CST4313_SPROM_OTP_SEL_MASK 0x00000002 #define CHIPC_CST4313_SPROM_OTP_SEL_SHIFT 0 /* 4313 Chip specific ChipControl register bits */ #define CHIPC_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ /* 43228 resources */ #define CHIPC_RES43228_NOT_USED 0 #define CHIPC_RES43228_ILP_REQUEST 1 #define CHIPC_RES43228_XTAL_PU 2 #define CHIPC_RES43228_ALP_AVAIL 3 #define CHIPC_RES43228_PLL_EN 4 #define CHIPC_RES43228_HT_PHY_AVAIL 5 /* 43228 chipstatus reg bits */ #define CHIPC_CST43228_ILP_DIV_EN 0x1 #define CHIPC_CST43228_OTP_PRESENT 0x2 #define CHIPC_CST43228_SERDES_REFCLK_PADSEL 0x4 #define CHIPC_CST43228_SDIO_MODE 0x8 #define CHIPC_CST43228_SDIO_OTP_PRESENT 0x10 #define CHIPC_CST43228_SDIO_RESET 0x20 /* * Maximum delay for the PMU state transition in us. * This is an upper bound intended for spinwaits etc. */ #define CHIPC_PMU_MAX_TRANSITION_DLY 15000 /* PMU resource up transition time in ILP cycles */ #define CHIPC_PMURES_UP_TRANSITION 2 /* * Register eci_inputlo bitfield values. * - BT packet type information bits [7:0] */ /* [3:0] - Task (link) type */ #define CHIPC_BT_ACL 0x00 #define CHIPC_BT_SCO 0x01 #define CHIPC_BT_eSCO 0x02 #define CHIPC_BT_A2DP 0x03 #define CHIPC_BT_SNIFF 0x04 #define CHIPC_BT_PAGE_SCAN 0x05 #define CHIPC_BT_INQUIRY_SCAN 0x06 #define CHIPC_BT_PAGE 0x07 #define CHIPC_BT_INQUIRY 0x08 #define CHIPC_BT_MSS 0x09 #define CHIPC_BT_PARK 0x0a #define CHIPC_BT_RSSISCAN 0x0b #define CHIPC_BT_MD_ACL 0x0c #define CHIPC_BT_MD_eSCO 0x0d #define CHIPC_BT_SCAN_WITH_SCO_LINK 0x0e #define CHIPC_BT_SCAN_WITHOUT_SCO_LINK 0x0f /* [7:4] = packet duration code */ /* [8] - Master / Slave */ #define CHIPC_BT_MASTER 0 #define CHIPC_BT_SLAVE 1 /* [11:9] - multi-level priority */ #define CHIPC_BT_LOWEST_PRIO 0x0 #define CHIPC_BT_HIGHEST_PRIO 0x3 #endif /* _BHND_CORES_CHIPC_CHIPCREG_H_ */ Index: head/sys/dev/bhnd/cores/chipc/chipcvar.h =================================================================== --- head/sys/dev/bhnd/cores/chipc/chipcvar.h (revision 302188) +++ head/sys/dev/bhnd/cores/chipc/chipcvar.h (revision 302189) @@ -1,221 +1,225 @@ /*- * Copyright (c) 2015 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. * * $FreeBSD$ */ #ifndef _BHND_CORES_CHIPC_CHIPCVAR_H_ #define _BHND_CORES_CHIPC_CHIPCVAR_H_ #include #include #include #include "chipc.h" DECLARE_CLASS(bhnd_chipc); extern devclass_t bhnd_chipc_devclass; struct chipc_region; /** * Supported ChipCommon flash types. */ typedef enum { CHIPC_FLASH_NONE = 0, /**< No flash, or a type unrecognized by the ChipCommon driver */ CHIPC_PFLASH_CFI = 1, /**< CFI-compatible parallel flash */ CHIPC_SFLASH_ST = 2, /**< ST serial flash */ CHIPC_SFLASH_AT = 3, /**< Atmel serial flash */ CHIPC_QSFLASH_ST = 4, /**< ST quad-SPI flash */ CHIPC_QSFLASH_AT = 5, /**< Atmel quad-SPI flash */ CHIPC_NFLASH = 6, /**< NAND flash */ CHIPC_NFLASH_4706 = 7 /**< BCM4706 NAND flash */ } chipc_flash; +const char *chipc_flash_name(chipc_flash type); +const char *chipc_flash_bus_name(chipc_flash type); +const char *chipc_sflash_device_name(chipc_flash type); + /** * ChipCommon capability flags; */ struct chipc_caps { uint8_t num_uarts; /**< Number of attached UARTS (1-3) */ bool mipseb; /**< MIPS is big-endian */ uint8_t uart_clock; /**< UART clock source (see CHIPC_CAP_UCLKSEL_*) */ uint8_t uart_gpio; /**< UARTs own GPIO pins 12-15 */ uint8_t extbus_type; /**< ExtBus type (CHIPC_CAP_EXTBUS_*) */ - chipc_flash flash_type; /**< Flash type */ - bhnd_nvram_src nvram_src; /**< identified NVRAM source */ + chipc_flash flash_type; /**< flash type */ + uint8_t cfi_width; /**< CFI bus width, 0 if unknown or CFI + not present */ + + bhnd_nvram_src nvram_src; /**< identified NVRAM source */ bus_size_t sprom_offset; /**< Offset to SPROM data within SPROM/OTP, 0 if unknown or not present */ uint8_t otp_size; /**< OTP (row?) size, 0 if not present */ - uint8_t cfi_width; /**< CFI bus width, 0 if unknown or CFI - not present */ uint8_t pll_type; /**< PLL type */ bool power_control; /**< Power control available */ bool jtag_master; /**< JTAG Master present */ bool boot_rom; /**< Internal boot ROM is active */ uint8_t backplane_64; /**< Backplane supports 64-bit addressing. Note that this does not gaurantee the CPU itself supports 64-bit addressing. */ bool pmu; /**< PMU is present. */ bool eci; /**< ECI (enhanced coexistence inteface) is present. */ bool seci; /**< SECI (serial ECI) is present */ bool sprom; /**< SPROM is present */ bool gsio; /**< GSIO (SPI/I2C) present */ bool aob; /**< AOB (always on bus) present. If set, PMU and GCI registers are not accessible via ChipCommon, and are instead accessible via dedicated cores on the bhnd bus */ }; /* * ChipCommon device quirks / features */ enum { /** No quirks */ CHIPC_QUIRK_NONE = 0, /** * ChipCommon-controlled SPROM/OTP is supported, along with the * CHIPC_CAP_SPROM capability flag. */ CHIPC_QUIRK_SUPPORTS_SPROM = (1<<1), /** * The BCM4706 NAND flash interface is supported, along with the * CHIPC_CAP_4706_NFLASH capability flag. */ CHIPC_QUIRK_4706_NFLASH = (1<<2), /** * The SPROM is attached via muxed pins. The pins must be switched * to allow reading/writing. */ CHIPC_QUIRK_MUX_SPROM = (1<<3), /** * Access to the SPROM uses pins shared with the 802.11a external PA. * * On modules using these 4331 packages, the CCTRL4331_EXTPA_EN flag * must be cleared to allow SPROM access. */ CHIPC_QUIRK_4331_EXTPA_MUX_SPROM = (1<<4) | CHIPC_QUIRK_MUX_SPROM, /** * Access to the SPROM uses pins shared with the 802.11a external PA. * * On modules using these 4331 chip packages, the external PA is * attached via GPIO 2, 5, and sprom_dout pins. * * When enabling and disabling EXTPA to allow SPROM access, the * CCTRL4331_EXTPA_ON_GPIO2_5 flag must also be set or cleared, * respectively. */ CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM = (1<<5) | CHIPC_QUIRK_4331_EXTPA_MUX_SPROM, /** * Access to the SPROM uses pins shared with two 802.11a external PAs. * * When enabling and disabling EXTPA, the CCTRL4331_EXTPA_EN2 must also * be cleared to allow SPROM access. */ CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM = (1<<6) | CHIPC_QUIRK_4331_EXTPA_MUX_SPROM, /** * SPROM pins are muxed with the FEM control lines on this 4360-family * device. The muxed pins must be switched to allow reading/writing * the SPROM. */ CHIPC_QUIRK_4360_FEM_MUX_SPROM = (1<<5) | CHIPC_QUIRK_MUX_SPROM, /** Supports CHIPC_CAPABILITIES_EXT register */ CHIPC_QUIRK_SUPPORTS_CAP_EXT = (1<<6), /** Supports HND or IPX OTP registers (CHIPC_OTPST, CHIPC_OTPCTRL, * CHIPC_OTPPROG) */ CHIPC_QUIRK_SUPPORTS_OTP = (1<<7), /** Supports HND OTP registers. */ CHIPC_QUIRK_OTP_HND = (1<<8) | CHIPC_QUIRK_SUPPORTS_OTP, /** Supports IPX OTP registers. */ CHIPC_QUIRK_OTP_IPX = (1<<9) | CHIPC_QUIRK_SUPPORTS_OTP, /** OTP size is defined via CHIPC_OTPLAYOUT register in later * ChipCommon revisions using the 'IPX' OTP controller. */ CHIPC_QUIRK_IPX_OTPL_SIZE = (1<<10) }; /** * chipc child device info. */ struct chipc_devinfo { struct resource_list resources; /**< child resources */ }; /** * chipc driver instance state. */ struct chipc_softc { device_t dev; struct bhnd_resource *core; /**< core registers. */ struct chipc_region *core_region; /**< region containing core registers */ - struct bhnd_chipid ccid; /**< chip identification */ uint32_t quirks; /**< chipc quirk flags */ struct chipc_caps caps; /**< chipc capabilities */ struct mtx mtx; /**< state mutex. */ size_t sprom_refcnt; /**< SPROM pin enable refcount */ struct rman mem_rman; /**< port memory manager */ STAILQ_HEAD(, chipc_region) mem_regions;/**< memory allocation records */ }; #define CHIPC_LOCK_INIT(sc) \ mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \ "BHND chipc driver lock", MTX_DEF) #define CHIPC_LOCK(sc) mtx_lock(&(sc)->mtx) #define CHIPC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) #define CHIPC_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what) #define CHIPC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) #endif /* _BHND_CORES_CHIPC_CHIPCVAR_H_ */ Index: head/sys/mips/broadcom/uart_bus_chipc.c =================================================================== --- head/sys/mips/broadcom/uart_bus_chipc.c (revision 302188) +++ head/sys/mips/broadcom/uart_bus_chipc.c (revision 302189) @@ -1,138 +1,83 @@ /*- * Copyright (c) 2016 Michael Zhilin * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_uart.h" #include #include #include #include #include #include #include #include #include #include #include #include -#include - #include "uart_if.h" #include "bhnd_chipc_if.h" +#include "bcm_socinfo.h" -static int uart_chipc_probe(device_t dev); -extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; - -static void -uart_chipc_identify(driver_t *driver, device_t parent) -{ - struct chipc_caps *caps; - - if (device_find_child(parent, "uart", -1) != NULL) - return; - - caps = BHND_CHIPC_GET_CAPS(parent); - - if (caps == NULL) { - device_printf(parent, "error: can't retrieve ChipCommon " - "capabilities\n"); - return; - } - - if (caps->num_uarts == 0) - return; - - /* - * TODO: add more than one UART - */ - BUS_ADD_CHILD(parent, 0, "uart", -1); -} - static int uart_chipc_probe(device_t dev) { struct uart_softc *sc; - struct resource *res; - int rid; - int err; + struct bcm_socinfo *socinfo; - rid = 0; - res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); - if (res == NULL) { - device_printf(dev, "can't allocate main resource\n"); - return (ENXIO); - } - sc = device_get_softc(dev); sc->sc_class = &uart_ns8250_class; - sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs); - if (sc->sc_sysdev == NULL) { - device_printf(dev, "missing sysdev\n"); - return (EINVAL); - } - bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas)); - - sc->sc_sysdev->bas.bst = rman_get_bustag(res); - sc->sc_sysdev->bas.bsh = rman_get_bushandle(res); - sc->sc_bas.bst = sc->sc_sysdev->bas.bst; - sc->sc_bas.bsh = sc->sc_sysdev->bas.bsh; - - err = bus_release_resource(dev, SYS_RES_MEMORY, rid, res); - if (err) { - device_printf(dev, "can't release resource [%d]\n", rid); - return (ENXIO); - } - - /* We use internal SoC clock generator with non-standart freq MHz */ - return (uart_bus_probe(dev, 0, sc->sc_sysdev->bas.rclk, 0, 0)); + /* TODO: UART rate should be calculated from CPU clock speed + * as fetched from bhnd bus */ + socinfo = bcm_get_socinfo(); + return (uart_bus_probe(dev, 0, socinfo->uartrate, 0, 0)); } static device_method_t uart_chipc_methods[] = { /* Device interface */ - DEVMETHOD(device_identify, uart_chipc_identify), DEVMETHOD(device_probe, uart_chipc_probe), DEVMETHOD(device_attach, uart_bus_attach), DEVMETHOD(device_detach, uart_bus_detach), { 0, 0 } }; static driver_t uart_chipc_driver = { uart_driver_name, uart_chipc_methods, sizeof(struct uart_softc), }; DRIVER_MODULE(uart, bhnd_chipc, uart_chipc_driver, uart_devclass, 0, 0);