Index: stable/10/sys/conf/files.i386 =================================================================== --- stable/10/sys/conf/files.i386 (revision 300372) +++ stable/10/sys/conf/files.i386 (revision 300373) @@ -1,622 +1,624 @@ # This file tells config what files go into building a kernel, # files marked standard are always included. # # $FreeBSD$ # # The long compile-with and dependency lines are required because of # limitations in config: backslash-newline doesn't work in strings, and # dependency lines other than the first are silently ignored. # linux_genassym.o optional compat_linux \ dependency "$S/i386/linux/linux_genassym.c" \ compile-with "${CC} ${CFLAGS:N-fno-common} -c ${.IMPSRC}" \ no-obj no-implicit-rule \ clean "linux_genassym.o" # linux_assym.h optional compat_linux \ dependency "$S/kern/genassym.sh linux_genassym.o" \ compile-with "sh $S/kern/genassym.sh linux_genassym.o > ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "linux_assym.h" # linux_locore.o optional compat_linux \ dependency "linux_assym.h $S/i386/linux/linux_locore.s" \ compile-with "${CC} -x assembler-with-cpp -DLOCORE -shared -s -pipe -I. -I$S -Werror -Wall -fno-common -nostdinc -nostdlib -Wl,-T$S/i386/linux/linux_vdso.lds.s -Wl,-soname=linux_vdso.so,--eh-frame-hdr,-fPIC,-warn-common ${.IMPSRC} -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "linux_locore.o" # linux_vdso.so optional compat_linux \ dependency "linux_locore.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf32-i386-freebsd --binary-architecture i386 linux_locore.o ${.TARGET}" \ no-implicit-rule \ clean "linux_vdso.so" # svr4_genassym.o optional compat_svr4 \ dependency "$S/i386/svr4/svr4_genassym.c" \ compile-with "${CC} ${CFLAGS:N-fno-common} -c ${.IMPSRC}" \ no-obj no-implicit-rule \ clean "svr4_genassym.o" # svr4_assym.h optional compat_svr4 \ dependency "$S/kern/genassym.sh svr4_genassym.o" \ compile-with "sh $S/kern/genassym.sh svr4_genassym.o > ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "svr4_assym.h" # font.h optional sc_dflt_font \ compile-with "uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x16.fnt && file2c 'static u_char dflt_font_16[16*256] = {' '};' < ${SC_DFLT_FONT}-8x16 > font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x14.fnt && file2c 'static u_char dflt_font_14[14*256] = {' '};' < ${SC_DFLT_FONT}-8x14 >> font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x8.fnt && file2c 'static u_char dflt_font_8[8*256] = {' '};' < ${SC_DFLT_FONT}-8x8 >> font.h" \ no-obj no-implicit-rule before-depend \ clean "font.h ${SC_DFLT_FONT}-8x14 ${SC_DFLT_FONT}-8x16 ${SC_DFLT_FONT}-8x8" # atkbdmap.h optional atkbd_dflt_keymap \ compile-with "kbdcontrol -P ${S:S/sys$/share/}/vt/keymaps -P ${S:S/sys$/share/}/syscons/keymaps -L ${ATKBD_DFLT_KEYMAP} | sed -e 's/^static keymap_t.* = /static keymap_t key_map = /' -e 's/^static accentmap_t.* = /static accentmap_t accent_map = /' > atkbdmap.h" \ no-obj no-implicit-rule before-depend \ clean "atkbdmap.h" # ukbdmap.h optional ukbd_dflt_keymap \ compile-with "kbdcontrol -P ${S:S/sys$/share/}/vt/keymaps -P ${S:S/sys$/share/}/syscons/keymaps -L ${UKBD_DFLT_KEYMAP} | sed -e 's/^static keymap_t.* = /static keymap_t key_map = /' -e 's/^static accentmap_t.* = /static accentmap_t accent_map = /' > ukbdmap.h" \ no-obj no-implicit-rule before-depend \ clean "ukbdmap.h" # nvenetlib.o optional nve pci \ dependency "$S/contrib/dev/nve/i386/nvenetlib.o.bz2.uu" \ compile-with "uudecode $S/contrib/dev/nve/i386/nvenetlib.o.bz2.uu ; bzip2 -df nvenetlib.o.bz2" \ no-implicit-rule # os+%DIKED-nve.h optional nve pci \ dependency "$S/contrib/dev/nve/os.h" \ compile-with "sed -e 's/^.*#include.*phy\.h.*$$//' $S/contrib/dev/nve/os.h > os+%DIKED-nve.h" \ no-implicit-rule no-obj before-depend \ clean "os+%DIKED-nve.h" # hpt27xx_lib.o optional hpt27xx \ dependency "$S/dev/hpt27xx/i386-elf.hpt27xx_lib.o.uu" \ compile-with "uudecode < $S/dev/hpt27xx/i386-elf.hpt27xx_lib.o.uu" \ no-implicit-rule # hptmvraid.o optional hptmv \ dependency "$S/dev/hptmv/i386-elf.raid.o.uu" \ compile-with "uudecode < $S/dev/hptmv/i386-elf.raid.o.uu" \ no-implicit-rule # hptnr_lib.o optional hptnr \ dependency "$S/dev/hptnr/i386-elf.hptnr_lib.o.uu" \ compile-with "uudecode < $S/dev/hptnr/i386-elf.hptnr_lib.o.uu" \ no-implicit-rule # hptrr_lib.o optional hptrr \ dependency "$S/dev/hptrr/i386-elf.hptrr_lib.o.uu" \ compile-with "uudecode < $S/dev/hptrr/i386-elf.hptrr_lib.o.uu" \ no-implicit-rule # cddl/contrib/opensolaris/common/atomic/i386/opensolaris_atomic.S optional zfs compile-with "${ZFS_S}" compat/linprocfs/linprocfs.c optional linprocfs compat/linsysfs/linsysfs.c optional linsysfs compat/linux/linux_event.c optional compat_linux compat/linux/linux_emul.c optional compat_linux compat/linux/linux_file.c optional compat_linux compat/linux/linux_fork.c optional compat_linux compat/linux/linux_futex.c optional compat_linux compat/linux/linux_getcwd.c optional compat_linux compat/linux/linux_ioctl.c optional compat_linux compat/linux/linux_ipc.c optional compat_linux compat/linux/linux_mib.c optional compat_linux compat/linux/linux_misc.c optional compat_linux compat/linux/linux_signal.c optional compat_linux compat/linux/linux_socket.c optional compat_linux compat/linux/linux_stats.c optional compat_linux compat/linux/linux_sysctl.c optional compat_linux compat/linux/linux_time.c optional compat_linux compat/linux/linux_timer.c optional compat_linux compat/linux/linux_uid16.c optional compat_linux compat/linux/linux_util.c optional compat_linux compat/linux/linux_vdso.c optional compat_linux compat/linux/linux.c optional compat_linux compat/ndis/kern_ndis.c optional ndisapi pci compat/ndis/kern_windrv.c optional ndisapi pci compat/ndis/subr_hal.c optional ndisapi pci compat/ndis/subr_ndis.c optional ndisapi pci compat/ndis/subr_ntoskrnl.c optional ndisapi pci compat/ndis/subr_pe.c optional ndisapi pci compat/ndis/subr_usbd.c optional ndisapi pci compat/ndis/winx32_wrap.S optional ndisapi pci compat/svr4/imgact_svr4.c optional compat_svr4 compat/svr4/svr4_fcntl.c optional compat_svr4 compat/svr4/svr4_filio.c optional compat_svr4 compat/svr4/svr4_ioctl.c optional compat_svr4 compat/svr4/svr4_ipc.c optional compat_svr4 compat/svr4/svr4_misc.c optional compat_svr4 compat/svr4/svr4_resource.c optional compat_svr4 compat/svr4/svr4_signal.c optional compat_svr4 compat/svr4/svr4_socket.c optional compat_svr4 compat/svr4/svr4_sockio.c optional compat_svr4 compat/svr4/svr4_stat.c optional compat_svr4 compat/svr4/svr4_stream.c optional compat_svr4 compat/svr4/svr4_syscallnames.c optional compat_svr4 compat/svr4/svr4_sysent.c optional compat_svr4 compat/svr4/svr4_sysvec.c optional compat_svr4 compat/svr4/svr4_termios.c optional compat_svr4 bf_enc.o optional crypto | ipsec \ dependency "$S/crypto/blowfish/arch/i386/bf_enc.S $S/crypto/blowfish/arch/i386/bf_enc_586.S $S/crypto/blowfish/arch/i386/bf_enc_686.S" \ compile-with "${CC} -c -I$S/crypto/blowfish/arch/i386 ${ASM_CFLAGS} ${WERROR} ${.IMPSRC}" \ no-implicit-rule crypto/aesni/aeskeys_i386.S optional aesni crypto/aesni/aesni.c optional aesni aesni_wrap.o optional aesni \ dependency "$S/crypto/aesni/aesni_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc} ${WERROR} ${PROF} -mmmx -msse -maes ${.IMPSRC}" \ no-implicit-rule \ clean "aesni_wrap.o" crypto/des/arch/i386/des_enc.S optional crypto | ipsec | netsmb crypto/via/padlock.c optional padlock crypto/via/padlock_cipher.c optional padlock crypto/via/padlock_hash.c optional padlock dev/advansys/adv_isa.c optional adv isa dev/agp/agp_ali.c optional agp dev/agp/agp_amd.c optional agp dev/agp/agp_amd64.c optional agp dev/agp/agp_ati.c optional agp dev/agp/agp_i810.c optional agp dev/agp/agp_intel.c optional agp dev/agp/agp_nvidia.c optional agp dev/agp/agp_sis.c optional agp dev/agp/agp_via.c optional agp dev/aic/aic_isa.c optional aic isa dev/amdsbwd/amdsbwd.c optional amdsbwd dev/amdtemp/amdtemp.c optional amdtemp dev/arcmsr/arcmsr.c optional arcmsr pci dev/asmc/asmc.c optional asmc isa dev/atkbdc/atkbd.c optional atkbd atkbdc dev/atkbdc/atkbd_atkbdc.c optional atkbd atkbdc dev/atkbdc/atkbdc.c optional atkbdc dev/atkbdc/atkbdc_isa.c optional atkbdc isa dev/atkbdc/atkbdc_subr.c optional atkbdc dev/atkbdc/psm.c optional psm atkbdc dev/bxe/bxe.c optional bxe pci dev/bxe/bxe_stats.c optional bxe pci dev/bxe/bxe_debug.c optional bxe pci dev/bxe/ecore_sp.c optional bxe pci dev/bxe/bxe_elink.c optional bxe pci dev/bxe/57710_init_values.c optional bxe pci dev/bxe/57711_init_values.c optional bxe pci dev/bxe/57712_init_values.c optional bxe pci dev/ce/ceddk.c optional ce dev/ce/if_ce.c optional ce dev/ce/tau32-ddk.c optional ce \ compile-with "${NORMAL_C} ${NO_WCONSTANT_CONVERSION}" dev/cm/if_cm_isa.c optional cm isa dev/coretemp/coretemp.c optional coretemp dev/cp/cpddk.c optional cp dev/cp/if_cp.c optional cp dev/cpuctl/cpuctl.c optional cpuctl dev/ctau/ctau.c optional ctau dev/ctau/ctddk.c optional ctau dev/ctau/if_ct.c optional ctau dev/cx/csigma.c optional cx dev/cx/cxddk.c optional cx dev/cx/if_cx.c optional cx dev/dpms/dpms.c optional dpms dev/ed/if_ed_3c503.c optional ed isa ed_3c503 dev/ed/if_ed_isa.c optional ed isa dev/ed/if_ed_wd80x3.c optional ed isa dev/ed/if_ed_hpp.c optional ed isa ed_hpp dev/ed/if_ed_sic.c optional ed isa ed_sic dev/fb/fb.c optional fb | vga dev/fb/s3_pci.c optional s3pci dev/fb/vesa.c optional vga vesa dev/fb/vga.c optional vga dev/fdc/fdc.c optional fdc dev/fdc/fdc_acpi.c optional fdc dev/fdc/fdc_isa.c optional fdc isa dev/fdc/fdc_pccard.c optional fdc pccard dev/fdt/fdt_x86.c optional fdt dev/fe/if_fe_isa.c optional fe isa dev/glxiic/glxiic.c optional glxiic dev/glxsb/glxsb.c optional glxsb dev/glxsb/glxsb_hash.c optional glxsb dev/hpt27xx/hpt27xx_os_bsd.c optional hpt27xx dev/hpt27xx/hpt27xx_osm_bsd.c optional hpt27xx dev/hpt27xx/hpt27xx_config.c optional hpt27xx dev/hptmv/entry.c optional hptmv dev/hptmv/mv.c optional hptmv dev/hptmv/gui_lib.c optional hptmv dev/hptmv/hptproc.c optional hptmv dev/hptmv/ioctl.c optional hptmv dev/hptnr/hptnr_os_bsd.c optional hptnr dev/hptnr/hptnr_osm_bsd.c optional hptnr dev/hptnr/hptnr_config.c optional hptnr dev/hptrr/hptrr_os_bsd.c optional hptrr dev/hptrr/hptrr_osm_bsd.c optional hptrr dev/hptrr/hptrr_config.c optional hptrr dev/hwpmc/hwpmc_amd.c optional hwpmc dev/hwpmc/hwpmc_intel.c optional hwpmc dev/hwpmc/hwpmc_core.c optional hwpmc dev/hwpmc/hwpmc_uncore.c optional hwpmc dev/hwpmc/hwpmc_pentium.c optional hwpmc dev/hwpmc/hwpmc_piv.c optional hwpmc dev/hwpmc/hwpmc_ppro.c optional hwpmc dev/hwpmc/hwpmc_tsc.c optional hwpmc dev/hwpmc/hwpmc_x86.c optional hwpmc dev/hyperv/netvsc/hv_net_vsc.c optional hyperv dev/hyperv/netvsc/hv_netvsc_drv_freebsd.c optional hyperv dev/hyperv/netvsc/hv_rndis_filter.c optional hyperv dev/hyperv/stordisengage/hv_ata_pci_disengage.c optional hyperv dev/hyperv/storvsc/hv_storvsc_drv_freebsd.c optional hyperv dev/hyperv/utilities/hv_kvp.c optional hyperv dev/hyperv/utilities/hv_util.c optional hyperv dev/hyperv/vmbus/hv_channel.c optional hyperv dev/hyperv/vmbus/hv_channel_mgmt.c optional hyperv dev/hyperv/vmbus/hv_connection.c optional hyperv dev/hyperv/vmbus/hv_hv.c optional hyperv dev/hyperv/vmbus/hv_et.c optional hyperv dev/hyperv/vmbus/hv_ring_buffer.c optional hyperv dev/hyperv/vmbus/hv_vmbus_drv_freebsd.c optional hyperv dev/ichwd/ichwd.c optional ichwd dev/if_ndis/if_ndis.c optional ndis dev/if_ndis/if_ndis_pccard.c optional ndis pccard dev/if_ndis/if_ndis_pci.c optional ndis cardbus | ndis pci dev/if_ndis/if_ndis_usb.c optional ndis usb dev/io/iodev.c optional io dev/ipmi/ipmi.c optional ipmi dev/ipmi/ipmi_acpi.c optional ipmi acpi dev/ipmi/ipmi_isa.c optional ipmi isa dev/ipmi/ipmi_kcs.c optional ipmi dev/ipmi/ipmi_smic.c optional ipmi dev/ipmi/ipmi_smbus.c optional ipmi smbus dev/ipmi/ipmi_smbios.c optional ipmi dev/ipmi/ipmi_ssif.c optional ipmi smbus dev/ipmi/ipmi_pci.c optional ipmi pci dev/ipmi/ipmi_linux.c optional ipmi compat_linux dev/kbd/kbd.c optional atkbd | sc | ukbd | vt dev/le/if_le_isa.c optional le isa dev/lindev/full.c optional lindev dev/lindev/lindev.c optional lindev dev/mse/mse.c optional mse dev/mse/mse_isa.c optional mse isa dev/nfe/if_nfe.c optional nfe pci +dev/ntb/if_ntb/if_ntb.c optional if_ntb +dev/ntb/ntb_hw/ntb_hw.c optional if_ntb | ntb_hw dev/nvd/nvd.c optional nvd nvme dev/nve/if_nve.c optional nve pci dev/nvme/nvme.c optional nvme dev/nvme/nvme_ctrlr.c optional nvme dev/nvme/nvme_ctrlr_cmd.c optional nvme dev/nvme/nvme_ns.c optional nvme dev/nvme/nvme_ns_cmd.c optional nvme dev/nvme/nvme_qpair.c optional nvme dev/nvme/nvme_sysctl.c optional nvme dev/nvme/nvme_test.c optional nvme dev/nvme/nvme_util.c optional nvme dev/nvram/nvram.c optional nvram isa dev/pcf/pcf_isa.c optional pcf dev/random/ivy.c optional rdrand_rng dev/random/nehemiah.c optional padlock_rng dev/sbni/if_sbni.c optional sbni dev/sbni/if_sbni_isa.c optional sbni isa dev/sbni/if_sbni_pci.c optional sbni pci dev/sio/sio.c optional sio dev/sio/sio_isa.c optional sio isa dev/sio/sio_pccard.c optional sio pccard dev/sio/sio_pci.c optional sio pci dev/sio/sio_puc.c optional sio puc dev/speaker/spkr.c optional speaker dev/syscons/apm/apm_saver.c optional apm_saver apm dev/syscons/scterm-teken.c optional sc dev/syscons/scvesactl.c optional sc vga vesa dev/syscons/scvgarndr.c optional sc vga dev/syscons/scvtb.c optional sc dev/tpm/tpm.c optional tpm dev/tpm/tpm_acpi.c optional tpm acpi dev/tpm/tpm_isa.c optional tpm isa dev/uart/uart_cpu_x86.c optional uart dev/viawd/viawd.c optional viawd dev/vmware/vmxnet3/if_vmx.c optional vmx dev/acpica/acpi_if.m standard dev/acpi_support/acpi_wmi_if.m standard dev/wbwd/wbwd.c optional wbwd dev/wpi/if_wpi.c optional wpi dev/isci/isci.c optional isci dev/isci/isci_controller.c optional isci dev/isci/isci_domain.c optional isci dev/isci/isci_interrupt.c optional isci dev/isci/isci_io_request.c optional isci dev/isci/isci_logger.c optional isci dev/isci/isci_oem_parameters.c optional isci dev/isci/isci_remote_device.c optional isci dev/isci/isci_sysctl.c optional isci dev/isci/isci_task_request.c optional isci dev/isci/isci_timer.c optional isci dev/isci/scil/sati.c optional isci dev/isci/scil/sati_abort_task_set.c optional isci dev/isci/scil/sati_atapi.c optional isci dev/isci/scil/sati_device.c optional isci dev/isci/scil/sati_inquiry.c optional isci dev/isci/scil/sati_log_sense.c optional isci dev/isci/scil/sati_lun_reset.c optional isci dev/isci/scil/sati_mode_pages.c optional isci dev/isci/scil/sati_mode_select.c optional isci dev/isci/scil/sati_mode_sense.c optional isci dev/isci/scil/sati_mode_sense_10.c optional isci dev/isci/scil/sati_mode_sense_6.c optional isci dev/isci/scil/sati_move.c optional isci dev/isci/scil/sati_passthrough.c optional isci dev/isci/scil/sati_read.c optional isci dev/isci/scil/sati_read_buffer.c optional isci dev/isci/scil/sati_read_capacity.c optional isci dev/isci/scil/sati_reassign_blocks.c optional isci dev/isci/scil/sati_report_luns.c optional isci dev/isci/scil/sati_request_sense.c optional isci dev/isci/scil/sati_start_stop_unit.c optional isci dev/isci/scil/sati_synchronize_cache.c optional isci dev/isci/scil/sati_test_unit_ready.c optional isci dev/isci/scil/sati_unmap.c optional isci dev/isci/scil/sati_util.c optional isci dev/isci/scil/sati_verify.c optional isci dev/isci/scil/sati_write.c optional isci dev/isci/scil/sati_write_and_verify.c optional isci dev/isci/scil/sati_write_buffer.c optional isci dev/isci/scil/sati_write_long.c optional isci dev/isci/scil/sci_abstract_list.c optional isci dev/isci/scil/sci_base_controller.c optional isci dev/isci/scil/sci_base_domain.c optional isci dev/isci/scil/sci_base_iterator.c optional isci dev/isci/scil/sci_base_library.c optional isci dev/isci/scil/sci_base_logger.c optional isci dev/isci/scil/sci_base_memory_descriptor_list.c optional isci dev/isci/scil/sci_base_memory_descriptor_list_decorator.c optional isci dev/isci/scil/sci_base_object.c optional isci dev/isci/scil/sci_base_observer.c optional isci dev/isci/scil/sci_base_phy.c optional isci dev/isci/scil/sci_base_port.c optional isci dev/isci/scil/sci_base_remote_device.c optional isci dev/isci/scil/sci_base_request.c optional isci dev/isci/scil/sci_base_state_machine.c optional isci dev/isci/scil/sci_base_state_machine_logger.c optional isci dev/isci/scil/sci_base_state_machine_observer.c optional isci dev/isci/scil/sci_base_subject.c optional isci dev/isci/scil/sci_util.c optional isci dev/isci/scil/scic_sds_controller.c optional isci dev/isci/scil/scic_sds_library.c optional isci dev/isci/scil/scic_sds_pci.c optional isci dev/isci/scil/scic_sds_phy.c optional isci dev/isci/scil/scic_sds_port.c optional isci dev/isci/scil/scic_sds_port_configuration_agent.c optional isci dev/isci/scil/scic_sds_remote_device.c optional isci dev/isci/scil/scic_sds_remote_node_context.c optional isci dev/isci/scil/scic_sds_remote_node_table.c optional isci dev/isci/scil/scic_sds_request.c optional isci dev/isci/scil/scic_sds_sgpio.c optional isci dev/isci/scil/scic_sds_smp_remote_device.c optional isci dev/isci/scil/scic_sds_smp_request.c optional isci dev/isci/scil/scic_sds_ssp_request.c optional isci dev/isci/scil/scic_sds_stp_packet_request.c optional isci dev/isci/scil/scic_sds_stp_remote_device.c optional isci dev/isci/scil/scic_sds_stp_request.c optional isci dev/isci/scil/scic_sds_unsolicited_frame_control.c optional isci dev/isci/scil/scif_sas_controller.c optional isci dev/isci/scil/scif_sas_controller_state_handlers.c optional isci dev/isci/scil/scif_sas_controller_states.c optional isci dev/isci/scil/scif_sas_domain.c optional isci dev/isci/scil/scif_sas_domain_state_handlers.c optional isci dev/isci/scil/scif_sas_domain_states.c optional isci dev/isci/scil/scif_sas_high_priority_request_queue.c optional isci dev/isci/scil/scif_sas_internal_io_request.c optional isci dev/isci/scil/scif_sas_io_request.c optional isci dev/isci/scil/scif_sas_io_request_state_handlers.c optional isci dev/isci/scil/scif_sas_io_request_states.c optional isci dev/isci/scil/scif_sas_library.c optional isci dev/isci/scil/scif_sas_remote_device.c optional isci dev/isci/scil/scif_sas_remote_device_ready_substate_handlers.c optional isci dev/isci/scil/scif_sas_remote_device_ready_substates.c optional isci dev/isci/scil/scif_sas_remote_device_starting_substate_handlers.c optional isci dev/isci/scil/scif_sas_remote_device_starting_substates.c optional isci dev/isci/scil/scif_sas_remote_device_state_handlers.c optional isci dev/isci/scil/scif_sas_remote_device_states.c optional isci dev/isci/scil/scif_sas_request.c optional isci dev/isci/scil/scif_sas_smp_activity_clear_affiliation.c optional isci dev/isci/scil/scif_sas_smp_io_request.c optional isci dev/isci/scil/scif_sas_smp_phy.c optional isci dev/isci/scil/scif_sas_smp_remote_device.c optional isci dev/isci/scil/scif_sas_stp_io_request.c optional isci dev/isci/scil/scif_sas_stp_remote_device.c optional isci dev/isci/scil/scif_sas_stp_task_request.c optional isci dev/isci/scil/scif_sas_task_request.c optional isci dev/isci/scil/scif_sas_task_request_state_handlers.c optional isci dev/isci/scil/scif_sas_task_request_states.c optional isci dev/isci/scil/scif_sas_timer.c optional isci dev/virtio/virtio.c optional virtio dev/virtio/virtqueue.c optional virtio dev/virtio/virtio_bus_if.m optional virtio dev/virtio/virtio_if.m optional virtio dev/virtio/pci/virtio_pci.c optional virtio_pci dev/virtio/network/if_vtnet.c optional vtnet dev/virtio/block/virtio_blk.c optional virtio_blk dev/virtio/balloon/virtio_balloon.c optional virtio_balloon dev/virtio/scsi/virtio_scsi.c optional virtio_scsi dev/virtio/random/virtio_random.c optional virtio_random dev/virtio/console/virtio_console.c optional virtio_console i386/acpica/acpi_machdep.c optional acpi acpi_wakecode.o optional acpi \ dependency "$S/i386/acpica/acpi_wakecode.S assym.s" \ compile-with "${NORMAL_S}" \ no-obj no-implicit-rule before-depend \ clean "acpi_wakecode.o" acpi_wakecode.bin optional acpi \ dependency "acpi_wakecode.o" \ compile-with "${OBJCOPY} -S -O binary acpi_wakecode.o ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "acpi_wakecode.bin" acpi_wakecode.h optional acpi \ dependency "acpi_wakecode.bin" \ compile-with "file2c -sx 'static char wakecode[] = {' '};' < acpi_wakecode.bin > ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "acpi_wakecode.h" acpi_wakedata.h optional acpi \ dependency "acpi_wakecode.o" \ compile-with '${NM} -n --defined-only acpi_wakecode.o | while read offset dummy what; do echo "#define $${what} 0x$${offset}"; done > ${.TARGET}' \ no-obj no-implicit-rule before-depend \ clean "acpi_wakedata.h" # i386/bios/apm.c optional apm i386/bios/mca_machdep.c optional mca i386/bios/smapi.c optional smapi i386/bios/smapi_bios.S optional smapi #i386/i386/apic_vector.s optional apic i386/i386/atomic.c standard \ compile-with "${CC} -c ${CFLAGS} ${DEFINED_PROF:S/^$/-fomit-frame-pointer/} ${.IMPSRC}" i386/i386/autoconf.c standard i386/i386/bios.c optional native i386/i386/bioscall.s optional native i386/i386/bpf_jit_machdep.c optional bpf_jitter i386/i386/db_disasm.c optional ddb i386/i386/db_interface.c optional ddb i386/i386/db_trace.c optional ddb i386/i386/elan-mmcr.c optional cpu_elan | cpu_soekris i386/i386/elf_machdep.c standard i386/i386/exception.s optional native i386/xen/exception.s optional xen i386/i386/gdb_machdep.c optional gdb i386/i386/geode.c optional cpu_geode i386/i386/i686_mem.c optional mem i386/i386/in_cksum.c optional inet | inet6 i386/i386/initcpu.c standard i386/i386/io.c optional io i386/i386/k6_mem.c optional mem i386/i386/locore.s optional native no-obj i386/xen/locore.s optional xen no-obj i386/i386/longrun.c optional cpu_enable_longrun i386/i386/machdep.c standard i386/xen/xen_machdep.c optional xen i386/i386/mem.c optional mem i386/i386/minidump_machdep.c standard i386/i386/mp_clock.c optional smp i386/i386/mp_machdep.c optional native smp i386/xen/mp_machdep.c optional xen smp i386/i386/mp_watchdog.c optional mp_watchdog smp i386/i386/mpboot.s optional smp native i386/xen/mptable.c optional apic xen i386/i386/perfmon.c optional perfmon i386/i386/pmap.c optional native i386/xen/pmap.c optional xen i386/i386/ptrace_machdep.c standard i386/i386/stack_machdep.c optional ddb | stack i386/i386/support.s standard i386/i386/swtch.s standard i386/i386/sys_machdep.c standard i386/i386/trap.c standard i386/i386/uio_machdep.c standard i386/i386/vm86.c standard i386/i386/vm_machdep.c standard i386/ibcs2/ibcs2_errno.c optional ibcs2 i386/ibcs2/ibcs2_fcntl.c optional ibcs2 i386/ibcs2/ibcs2_ioctl.c optional ibcs2 i386/ibcs2/ibcs2_ipc.c optional ibcs2 i386/ibcs2/ibcs2_isc.c optional ibcs2 i386/ibcs2/ibcs2_isc_sysent.c optional ibcs2 i386/ibcs2/ibcs2_misc.c optional ibcs2 i386/ibcs2/ibcs2_msg.c optional ibcs2 i386/ibcs2/ibcs2_other.c optional ibcs2 i386/ibcs2/ibcs2_signal.c optional ibcs2 i386/ibcs2/ibcs2_socksys.c optional ibcs2 i386/ibcs2/ibcs2_stat.c optional ibcs2 i386/ibcs2/ibcs2_sysent.c optional ibcs2 i386/ibcs2/ibcs2_sysi86.c optional ibcs2 i386/ibcs2/ibcs2_sysvec.c optional ibcs2 i386/ibcs2/ibcs2_util.c optional ibcs2 i386/ibcs2/ibcs2_xenix.c optional ibcs2 i386/ibcs2/ibcs2_xenix_sysent.c optional ibcs2 i386/ibcs2/imgact_coff.c optional ibcs2 i386/xen/clock.c optional xen i386/isa/elink.c optional ep | ie i386/isa/npx.c optional npx i386/isa/pmtimer.c optional pmtimer i386/isa/prof_machdep.c optional profiling-routine i386/isa/spic.c optional spic i386/linux/imgact_linux.c optional compat_linux i386/linux/linux_dummy.c optional compat_linux i386/linux/linux_machdep.c optional compat_linux i386/linux/linux_ptrace.c optional compat_linux i386/linux/linux_support.s optional compat_linux \ dependency "linux_assym.h" i386/linux/linux_sysent.c optional compat_linux i386/linux/linux_sysvec.c optional compat_linux i386/pci/pci_cfgreg.c optional pci i386/pci/pci_pir.c optional pci i386/svr4/svr4_locore.s optional compat_svr4 \ dependency "svr4_assym.h" \ warning "COMPAT_SVR4 is broken and should be avoided" i386/svr4/svr4_machdep.c optional compat_svr4 # isa/syscons_isa.c optional sc isa/vga_isa.c optional vga kern/kern_clocksource.c standard kern/imgact_aout.c optional compat_aout kern/imgact_binmisc.c optional imagact_binmisc kern/imgact_gzip.c optional gzip libkern/divdi3.c standard libkern/flsll.c standard libkern/memmove.c standard libkern/memset.c standard libkern/moddi3.c standard libkern/qdivrem.c standard libkern/ucmpdi2.c standard libkern/udivdi3.c standard libkern/umoddi3.c standard i386/xbox/xbox.c optional xbox i386/xbox/xboxfb.c optional xboxfb dev/fb/boot_font.c optional xboxfb i386/xbox/pic16l.s optional xbox # # x86 real mode BIOS support, required by dpms/vesa # compat/x86bios/x86bios.c optional x86bios | dpms | vesa # # x86 shared code between IA32, AMD64 and PC98 architectures # x86/acpica/OsdEnvironment.c optional acpi x86/acpica/acpi_apm.c optional acpi x86/acpica/acpi_wakeup.c optional acpi x86/acpica/madt.c optional acpi apic x86/acpica/srat.c optional acpi x86/bios/smbios.c optional smbios x86/bios/vpd.c optional vpd x86/cpufreq/est.c optional cpufreq x86/cpufreq/hwpstate.c optional cpufreq x86/cpufreq/p4tcc.c optional cpufreq x86/cpufreq/powernow.c optional cpufreq x86/cpufreq/smist.c optional cpufreq x86/iommu/busdma_dmar.c optional acpi acpi_dmar pci x86/iommu/intel_ctx.c optional acpi acpi_dmar pci x86/iommu/intel_drv.c optional acpi acpi_dmar pci x86/iommu/intel_fault.c optional acpi acpi_dmar pci x86/iommu/intel_gas.c optional acpi acpi_dmar pci x86/iommu/intel_idpgtbl.c optional acpi acpi_dmar pci x86/iommu/intel_qi.c optional acpi acpi_dmar pci x86/iommu/intel_quirks.c optional acpi acpi_dmar pci x86/iommu/intel_utils.c optional acpi acpi_dmar pci x86/isa/atpic.c optional atpic x86/isa/atrtc.c optional native x86/isa/clock.c optional native x86/isa/elcr.c optional atpic | apic native x86/isa/isa.c optional isa x86/isa/isa_dma.c optional isa x86/isa/nmi.c standard x86/isa/orm.c optional isa x86/pci/pci_bus.c optional pci x86/pci/qpi.c optional pci x86/x86/bus_machdep.c standard x86/x86/busdma_bounce.c standard x86/x86/busdma_machdep.c standard x86/x86/dump_machdep.c standard x86/x86/fdt_machdep.c optional fdt x86/x86/identcpu.c standard x86/x86/intr_machdep.c standard x86/x86/io_apic.c optional apic x86/x86/legacy.c optional native x86/x86/local_apic.c optional apic x86/x86/mca.c standard x86/x86/mptable.c optional apic native x86/x86/mptable_pci.c optional apic native pci x86/x86/msi.c optional apic pci x86/x86/nexus.c standard x86/x86/tsc.c standard x86/xen/hvm.c optional xenhvm x86/xen/xen_intr.c optional xen | xenhvm Index: stable/10/sys/dev/ntb/if_ntb/if_ntb.c =================================================================== --- stable/10/sys/dev/ntb/if_ntb/if_ntb.c (revision 300372) +++ stable/10/sys/dev/ntb/if_ntb/if_ntb.c (revision 300373) @@ -1,1384 +1,1711 @@ /*- * Copyright (C) 2013 Intel Corporation + * Copyright (C) 2015 EMC Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include +#include #include #include +#include #include #include #include #include #include #include #include +#include #include + #include #include #include #include #include #include + #include #include + #include #include #include +#include +#include + #include "../ntb_hw/ntb_hw.h" /* * The Non-Transparent Bridge (NTB) is a device on some Intel processors that * allows you to connect two systems using a PCI-e link. * * This module contains a protocol for sending and receiving messages, and * exposes that protocol through a simulated ethernet device called ntb. * * NOTE: Much of the code in this module is shared with Linux. Any patches may * be picked up and redistributed in Linux with a dual GPL/BSD license. */ -/* TODO: These functions should really be part of the kernel */ -#define test_bit(pos, bitmap_addr) (*(bitmap_addr) & 1UL << (pos)) -#define set_bit(pos, bitmap_addr) *(bitmap_addr) |= 1UL << (pos) -#define clear_bit(pos, bitmap_addr) *(bitmap_addr) &= ~(1UL << (pos)) +#define QP_SETSIZE 64 +BITSET_DEFINE(_qpset, QP_SETSIZE); +#define test_bit(pos, addr) BIT_ISSET(QP_SETSIZE, (pos), (addr)) +#define set_bit(pos, addr) BIT_SET(QP_SETSIZE, (pos), (addr)) +#define clear_bit(pos, addr) BIT_CLR(QP_SETSIZE, (pos), (addr)) +#define ffs_bit(addr) BIT_FFS(QP_SETSIZE, (addr)) #define KTR_NTB KTR_SPARE3 -#define NTB_TRANSPORT_VERSION 3 +#define NTB_TRANSPORT_VERSION 4 #define NTB_RX_MAX_PKTS 64 #define NTB_RXQ_SIZE 300 -static unsigned int transport_mtu = 0x4000 + ETHER_HDR_LEN + ETHER_CRC_LEN; -static unsigned int max_num_clients = 1; +enum ntb_link_event { + NTB_LINK_DOWN = 0, + NTB_LINK_UP, +}; +static SYSCTL_NODE(_hw, OID_AUTO, if_ntb, CTLFLAG_RW, 0, "if_ntb"); + +static unsigned g_if_ntb_debug_level; +SYSCTL_UINT(_hw_if_ntb, OID_AUTO, debug_level, CTLFLAG_RWTUN, + &g_if_ntb_debug_level, 0, "if_ntb log level -- higher is more verbose"); +#define ntb_printf(lvl, ...) do { \ + if ((lvl) <= g_if_ntb_debug_level) { \ + if_printf(nt->ifp, __VA_ARGS__); \ + } \ +} while (0) + +static unsigned transport_mtu = IP_MAXPACKET + ETHER_HDR_LEN + ETHER_CRC_LEN; + +static uint64_t max_mw_size; +SYSCTL_UQUAD(_hw_if_ntb, OID_AUTO, max_mw_size, CTLFLAG_RDTUN, &max_mw_size, 0, + "If enabled (non-zero), limit the size of large memory windows. " + "Both sides of the NTB MUST set the same value here."); + +static unsigned max_num_clients; +SYSCTL_UINT(_hw_if_ntb, OID_AUTO, max_num_clients, CTLFLAG_RDTUN, + &max_num_clients, 0, "Maximum number of NTB transport clients. " + "0 (default) - use all available NTB memory windows; " + "positive integer N - Limit to N memory windows."); + +static unsigned enable_xeon_watchdog; +SYSCTL_UINT(_hw_if_ntb, OID_AUTO, enable_xeon_watchdog, CTLFLAG_RDTUN, + &enable_xeon_watchdog, 0, "If non-zero, write a register every second to " + "keep a watchdog from tearing down the NTB link"); + STAILQ_HEAD(ntb_queue_list, ntb_queue_entry); +typedef uint32_t ntb_q_idx_t; + struct ntb_queue_entry { /* ntb_queue list reference */ STAILQ_ENTRY(ntb_queue_entry) entry; - /* info on data to be transfered */ + /* info on data to be transferred */ void *cb_data; void *buf; - uint64_t len; - uint64_t flags; + uint32_t len; + uint32_t flags; + + struct ntb_transport_qp *qp; + struct ntb_payload_header *x_hdr; + ntb_q_idx_t index; }; struct ntb_rx_info { - unsigned int entry; + ntb_q_idx_t entry; }; struct ntb_transport_qp { - struct ntb_netdev *transport; + struct ntb_transport_ctx *transport; struct ntb_softc *ntb; void *cb_data; bool client_ready; - bool qp_link; + volatile bool link_is_up; uint8_t qp_num; /* Only 64 QPs are allowed. 0-63 */ struct ntb_rx_info *rx_info; struct ntb_rx_info *remote_rx_info; - void (*tx_handler) (struct ntb_transport_qp *qp, void *qp_data, + void (*tx_handler)(struct ntb_transport_qp *qp, void *qp_data, void *data, int len); struct ntb_queue_list tx_free_q; struct mtx ntb_tx_free_q_lock; - void *tx_mw; - uint64_t tx_index; - uint64_t tx_max_entry; + caddr_t tx_mw; + bus_addr_t tx_mw_phys; + ntb_q_idx_t tx_index; + ntb_q_idx_t tx_max_entry; uint64_t tx_max_frame; - void (*rx_handler) (struct ntb_transport_qp *qp, void *qp_data, + void (*rx_handler)(struct ntb_transport_qp *qp, void *qp_data, void *data, int len); + struct ntb_queue_list rx_post_q; struct ntb_queue_list rx_pend_q; - struct ntb_queue_list rx_free_q; - struct mtx ntb_rx_pend_q_lock; - struct mtx ntb_rx_free_q_lock; + /* ntb_rx_q_lock: synchronize access to rx_XXXX_q */ + struct mtx ntb_rx_q_lock; struct task rx_completion_task; - void *rx_buff; - uint64_t rx_index; - uint64_t rx_max_entry; + struct task rxc_db_work; + caddr_t rx_buff; + ntb_q_idx_t rx_index; + ntb_q_idx_t rx_max_entry; uint64_t rx_max_frame; - void (*event_handler) (void *data, int status); + void (*event_handler)(void *data, enum ntb_link_event status); struct callout link_work; struct callout queue_full; struct callout rx_full; uint64_t last_rx_no_buf; /* Stats */ uint64_t rx_bytes; uint64_t rx_pkts; uint64_t rx_ring_empty; uint64_t rx_err_no_buf; uint64_t rx_err_oflow; uint64_t rx_err_ver; uint64_t tx_bytes; uint64_t tx_pkts; uint64_t tx_ring_full; + uint64_t tx_err_no_buf; }; struct ntb_queue_handlers { - void (*rx_handler) (struct ntb_transport_qp *qp, void *qp_data, + void (*rx_handler)(struct ntb_transport_qp *qp, void *qp_data, void *data, int len); - void (*tx_handler) (struct ntb_transport_qp *qp, void *qp_data, + void (*tx_handler)(struct ntb_transport_qp *qp, void *qp_data, void *data, int len); - void (*event_handler) (void *data, int status); + void (*event_handler)(void *data, enum ntb_link_event status); }; - struct ntb_transport_mw { - size_t size; - void *virt_addr; - vm_paddr_t dma_addr; + vm_paddr_t phys_addr; + size_t phys_size; + size_t xlat_align; + size_t xlat_align_size; + bus_addr_t addr_limit; + /* Tx buff is off vbase / phys_addr */ + caddr_t vbase; + size_t xlat_size; + size_t buff_size; + /* Rx buff is off virt_addr / dma_addr */ + caddr_t virt_addr; + bus_addr_t dma_addr; }; -struct ntb_netdev { +struct ntb_transport_ctx { struct ntb_softc *ntb; struct ifnet *ifp; - struct ntb_transport_mw mw[NTB_NUM_MW]; - struct ntb_transport_qp *qps; - uint64_t max_qps; - uint64_t qp_bitmap; - bool transport_link; + struct ntb_transport_mw mw_vec[NTB_MAX_NUM_MW]; + struct ntb_transport_qp *qp_vec; + struct _qpset qp_bitmap; + struct _qpset qp_bitmap_free; + unsigned mw_count; + unsigned qp_count; + volatile bool link_is_up; struct callout link_work; - struct ntb_transport_qp *qp; + struct callout link_watchdog; + struct task link_cleanup; uint64_t bufsize; u_char eaddr[ETHER_ADDR_LEN]; struct mtx tx_lock; struct mtx rx_lock; + + /* The hardcoded single queuepair in ntb_setup_interface() */ + struct ntb_transport_qp *qp; }; -static struct ntb_netdev net_softc; +static struct ntb_transport_ctx net_softc; enum { IF_NTB_DESC_DONE_FLAG = 1 << 0, IF_NTB_LINK_DOWN_FLAG = 1 << 1, }; struct ntb_payload_header { - uint64_t ver; - uint64_t len; - uint64_t flags; + ntb_q_idx_t ver; + uint32_t len; + uint32_t flags; }; enum { + /* + * The order of this enum is part of the if_ntb remote protocol. Do + * not reorder without bumping protocol version (and it's probably best + * to keep the protocol in lock-step with the Linux NTB driver. + */ IF_NTB_VERSION = 0, - IF_NTB_MW0_SZ, - IF_NTB_MW1_SZ, - IF_NTB_NUM_QPS, IF_NTB_QP_LINKS, + IF_NTB_NUM_QPS, + IF_NTB_NUM_MWS, + /* + * N.B.: transport_link_work assumes MW1 enums = MW0 + 2. + */ + IF_NTB_MW0_SZ_HIGH, + IF_NTB_MW0_SZ_LOW, + IF_NTB_MW1_SZ_HIGH, + IF_NTB_MW1_SZ_LOW, IF_NTB_MAX_SPAD, + + /* + * Some NTB-using hardware have a watchdog to work around NTB hangs; if + * a register or doorbell isn't written every few seconds, the link is + * torn down. Write an otherwise unused register every few seconds to + * work around this watchdog. + */ + IF_NTB_WATCHDOG_SPAD = 15 }; +CTASSERT(IF_NTB_WATCHDOG_SPAD < XEON_SPAD_COUNT && + IF_NTB_WATCHDOG_SPAD < ATOM_SPAD_COUNT); -#define QP_TO_MW(qp) ((qp) % NTB_NUM_MW) +#define QP_TO_MW(nt, qp) ((qp) % nt->mw_count) #define NTB_QP_DEF_NUM_ENTRIES 100 #define NTB_LINK_DOWN_TIMEOUT 10 static int ntb_handle_module_events(struct module *m, int what, void *arg); static int ntb_setup_interface(void); static int ntb_teardown_interface(void); static void ntb_net_init(void *arg); static int ntb_ioctl(struct ifnet *ifp, u_long command, caddr_t data); static void ntb_start(struct ifnet *ifp); static void ntb_net_tx_handler(struct ntb_transport_qp *qp, void *qp_data, void *data, int len); static void ntb_net_rx_handler(struct ntb_transport_qp *qp, void *qp_data, void *data, int len); -static void ntb_net_event_handler(void *data, int status); -static int ntb_transport_init(struct ntb_softc *ntb); -static void ntb_transport_free(void *transport); -static void ntb_transport_init_queue(struct ntb_netdev *nt, +static void ntb_net_event_handler(void *data, enum ntb_link_event status); +static int ntb_transport_probe(struct ntb_softc *ntb); +static void ntb_transport_free(struct ntb_transport_ctx *); +static void ntb_transport_init_queue(struct ntb_transport_ctx *nt, unsigned int qp_num); static void ntb_transport_free_queue(struct ntb_transport_qp *qp); -static struct ntb_transport_qp * ntb_transport_create_queue(void *data, +static struct ntb_transport_qp *ntb_transport_create_queue(void *data, struct ntb_softc *pdev, const struct ntb_queue_handlers *handlers); static void ntb_transport_link_up(struct ntb_transport_qp *qp); static int ntb_transport_tx_enqueue(struct ntb_transport_qp *qp, void *cb, void *data, unsigned int len); static int ntb_process_tx(struct ntb_transport_qp *qp, struct ntb_queue_entry *entry); -static void ntb_tx_copy_task(struct ntb_transport_qp *qp, +static void ntb_memcpy_tx(struct ntb_transport_qp *qp, struct ntb_queue_entry *entry, void *offset); static void ntb_qp_full(void *arg); -static void ntb_transport_rxc_db(void *data, int db_num); -static void ntb_rx_pendq_full(void *arg); -static void ntb_transport_rx(struct ntb_transport_qp *qp); +static void ntb_transport_rxc_db(void *arg, int pending); static int ntb_process_rxc(struct ntb_transport_qp *qp); -static void ntb_rx_copy_task(struct ntb_transport_qp *qp, +static void ntb_memcpy_rx(struct ntb_transport_qp *qp, struct ntb_queue_entry *entry, void *offset); -static void ntb_rx_completion_task(void *arg, int pending); -static void ntb_transport_event_callback(void *data, enum ntb_hw_event event); +static inline void ntb_rx_copy_callback(struct ntb_transport_qp *qp, + void *data); +static void ntb_complete_rxc(void *arg, int pending); +static void ntb_transport_doorbell_callback(void *data, uint32_t vector); +static void ntb_transport_event_callback(void *data); static void ntb_transport_link_work(void *arg); -static int ntb_set_mw(struct ntb_netdev *nt, int num_mw, unsigned int size); -static void ntb_transport_setup_qp_mw(struct ntb_netdev *nt, +static int ntb_set_mw(struct ntb_transport_ctx *, int num_mw, size_t size); +static void ntb_free_mw(struct ntb_transport_ctx *nt, int num_mw); +static int ntb_transport_setup_qp_mw(struct ntb_transport_ctx *nt, unsigned int qp_num); static void ntb_qp_link_work(void *arg); -static void ntb_transport_link_cleanup(struct ntb_netdev *nt); +static void ntb_transport_link_cleanup(struct ntb_transport_ctx *nt); +static void ntb_transport_link_cleanup_work(void *, int); static void ntb_qp_link_down(struct ntb_transport_qp *qp); +static void ntb_qp_link_down_reset(struct ntb_transport_qp *qp); static void ntb_qp_link_cleanup(struct ntb_transport_qp *qp); static void ntb_transport_link_down(struct ntb_transport_qp *qp); static void ntb_send_link_down(struct ntb_transport_qp *qp); static void ntb_list_add(struct mtx *lock, struct ntb_queue_entry *entry, struct ntb_queue_list *list); static struct ntb_queue_entry *ntb_list_rm(struct mtx *lock, struct ntb_queue_list *list); +static struct ntb_queue_entry *ntb_list_mv(struct mtx *lock, + struct ntb_queue_list *from, struct ntb_queue_list *to); static void create_random_local_eui48(u_char *eaddr); static unsigned int ntb_transport_max_size(struct ntb_transport_qp *qp); +static void xeon_link_watchdog_hb(void *); +static const struct ntb_ctx_ops ntb_transport_ops = { + .link_event = ntb_transport_event_callback, + .db_event = ntb_transport_doorbell_callback, +}; + MALLOC_DEFINE(M_NTB_IF, "if_ntb", "ntb network driver"); +static inline void +iowrite32(uint32_t val, void *addr) +{ + + bus_space_write_4(X86_BUS_SPACE_MEM, 0/* HACK */, (uintptr_t)addr, + val); +} + /* Module setup and teardown */ static int ntb_handle_module_events(struct module *m, int what, void *arg) { int err = 0; switch (what) { case MOD_LOAD: err = ntb_setup_interface(); break; case MOD_UNLOAD: err = ntb_teardown_interface(); break; default: err = EOPNOTSUPP; break; } return (err); } static moduledata_t if_ntb_mod = { "if_ntb", ntb_handle_module_events, NULL }; DECLARE_MODULE(if_ntb, if_ntb_mod, SI_SUB_KLD, SI_ORDER_ANY); MODULE_DEPEND(if_ntb, ntb_hw, 1, 1, 1); static int -ntb_setup_interface() +ntb_setup_interface(void) { struct ifnet *ifp; struct ntb_queue_handlers handlers = { ntb_net_rx_handler, ntb_net_tx_handler, ntb_net_event_handler }; + int rc; net_softc.ntb = devclass_get_softc(devclass_find("ntb_hw"), 0); if (net_softc.ntb == NULL) { printf("ntb: Cannot find devclass\n"); return (ENXIO); } - ntb_transport_init(net_softc.ntb); - ifp = net_softc.ifp = if_alloc(IFT_ETHER); if (ifp == NULL) { - printf("ntb: cannot allocate ifnet structure\n"); + ntb_transport_free(&net_softc); + printf("ntb: Cannot allocate ifnet structure\n"); return (ENOMEM); } + if_initname(ifp, "ntb", 0); + rc = ntb_transport_probe(net_softc.ntb); + if (rc != 0) { + printf("ntb: Cannot init transport: %d\n", rc); + if_free(net_softc.ifp); + return (rc); + } + net_softc.qp = ntb_transport_create_queue(ifp, net_softc.ntb, &handlers); - if_initname(ifp, "ntb", 0); ifp->if_init = ntb_net_init; ifp->if_softc = &net_softc; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX; ifp->if_ioctl = ntb_ioctl; ifp->if_start = ntb_start; IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; IFQ_SET_READY(&ifp->if_snd); create_random_local_eui48(net_softc.eaddr); ether_ifattach(ifp, net_softc.eaddr); ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_JUMBO_MTU; ifp->if_capenable = ifp->if_capabilities; + ifp->if_mtu = ntb_transport_max_size(net_softc.qp) - ETHER_HDR_LEN - + ETHER_CRC_LEN; ntb_transport_link_up(net_softc.qp); net_softc.bufsize = ntb_transport_max_size(net_softc.qp) + sizeof(struct ether_header); return (0); } static int -ntb_teardown_interface() +ntb_teardown_interface(void) { - if (net_softc.qp != NULL) + if (net_softc.qp != NULL) { ntb_transport_link_down(net_softc.qp); + ntb_transport_free_queue(net_softc.qp); + ntb_transport_free(&net_softc); + } + if (net_softc.ifp != NULL) { ether_ifdetach(net_softc.ifp); if_free(net_softc.ifp); + net_softc.ifp = NULL; } - if (net_softc.qp != NULL) { - ntb_transport_free_queue(net_softc.qp); - ntb_transport_free(&net_softc); - } - return (0); } /* Network device interface */ static void ntb_net_init(void *arg) { - struct ntb_netdev *ntb_softc = arg; + struct ntb_transport_ctx *ntb_softc = arg; struct ifnet *ifp = ntb_softc->ifp; ifp->if_drv_flags |= IFF_DRV_RUNNING; ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; ifp->if_flags |= IFF_UP; if_link_state_change(ifp, LINK_STATE_UP); } static int ntb_ioctl(struct ifnet *ifp, u_long command, caddr_t data) { - struct ntb_netdev *nt = ifp->if_softc; + struct ntb_transport_ctx *nt = ifp->if_softc; struct ifreq *ifr = (struct ifreq *)data; int error = 0; switch (command) { case SIOCSIFMTU: { if (ifr->ifr_mtu > ntb_transport_max_size(nt->qp) - ETHER_HDR_LEN - ETHER_CRC_LEN) { error = EINVAL; break; } ifp->if_mtu = ifr->ifr_mtu; break; } default: error = ether_ioctl(ifp, command, data); break; } return (error); } static void ntb_start(struct ifnet *ifp) { struct mbuf *m_head; - struct ntb_netdev *nt = ifp->if_softc; + struct ntb_transport_ctx *nt = ifp->if_softc; int rc; mtx_lock(&nt->tx_lock); ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; CTR0(KTR_NTB, "TX: ntb_start"); while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); CTR1(KTR_NTB, "TX: start mbuf %p", m_head); rc = ntb_transport_tx_enqueue(nt->qp, m_head, m_head, m_length(m_head, NULL)); if (rc != 0) { CTR1(KTR_NTB, "TX: could not tx mbuf %p. Returning to snd q", m_head); if (rc == EAGAIN) { ifp->if_drv_flags |= IFF_DRV_OACTIVE; IFQ_DRV_PREPEND(&ifp->if_snd, m_head); callout_reset(&nt->qp->queue_full, hz / 1000, ntb_qp_full, ifp); } break; } } mtx_unlock(&nt->tx_lock); } /* Network Device Callbacks */ static void ntb_net_tx_handler(struct ntb_transport_qp *qp, void *qp_data, void *data, int len) { m_freem(data); CTR1(KTR_NTB, "TX: tx_handler freeing mbuf %p", data); } static void ntb_net_rx_handler(struct ntb_transport_qp *qp, void *qp_data, void *data, int len) { struct mbuf *m = data; struct ifnet *ifp = qp_data; CTR0(KTR_NTB, "RX: rx handler"); (*ifp->if_input)(ifp, m); } static void -ntb_net_event_handler(void *data, int status) +ntb_net_event_handler(void *data, enum ntb_link_event status) { + struct ifnet *ifp; + ifp = data; + (void)ifp; + + /* XXX The Linux driver munges with the carrier status here. */ + + switch (status) { + case NTB_LINK_DOWN: + break; + case NTB_LINK_UP: + break; + default: + panic("Bogus ntb_link_event %u\n", status); + } } /* Transport Init and teardown */ +static void +xeon_link_watchdog_hb(void *arg) +{ + struct ntb_transport_ctx *nt; + + nt = arg; + ntb_spad_write(nt->ntb, IF_NTB_WATCHDOG_SPAD, 0); + callout_reset(&nt->link_watchdog, 1 * hz, xeon_link_watchdog_hb, nt); +} + static int -ntb_transport_init(struct ntb_softc *ntb) +ntb_transport_probe(struct ntb_softc *ntb) { - struct ntb_netdev *nt = &net_softc; - int rc, i; + struct ntb_transport_ctx *nt = &net_softc; + struct ntb_transport_mw *mw; + uint64_t qp_bitmap; + int rc; + unsigned i; - nt->max_qps = max_num_clients; - ntb_register_transport(ntb, nt); + nt->mw_count = ntb_mw_count(ntb); + for (i = 0; i < nt->mw_count; i++) { + mw = &nt->mw_vec[i]; + + rc = ntb_mw_get_range(ntb, i, &mw->phys_addr, &mw->vbase, + &mw->phys_size, &mw->xlat_align, &mw->xlat_align_size, + &mw->addr_limit); + if (rc != 0) + goto err; + + mw->buff_size = 0; + mw->xlat_size = 0; + mw->virt_addr = NULL; + mw->dma_addr = 0; + } + + qp_bitmap = ntb_db_valid_mask(ntb); + nt->qp_count = flsll(qp_bitmap); + KASSERT(nt->qp_count != 0, ("bogus db bitmap")); + nt->qp_count -= 1; + + if (max_num_clients != 0 && max_num_clients < nt->qp_count) + nt->qp_count = max_num_clients; + else if (nt->mw_count < nt->qp_count) + nt->qp_count = nt->mw_count; + KASSERT(nt->qp_count <= QP_SETSIZE, ("invalid qp_count")); + mtx_init(&nt->tx_lock, "ntb transport tx", NULL, MTX_DEF); mtx_init(&nt->rx_lock, "ntb transport rx", NULL, MTX_DEF); - nt->qps = malloc(nt->max_qps * sizeof(struct ntb_transport_qp), - M_NTB_IF, M_WAITOK|M_ZERO); + nt->qp_vec = malloc(nt->qp_count * sizeof(*nt->qp_vec), M_NTB_IF, + M_WAITOK | M_ZERO); - nt->qp_bitmap = ((uint64_t) 1 << nt->max_qps) - 1; - - for (i = 0; i < nt->max_qps; i++) + for (i = 0; i < nt->qp_count; i++) { + set_bit(i, &nt->qp_bitmap); + set_bit(i, &nt->qp_bitmap_free); ntb_transport_init_queue(nt, i); + } callout_init(&nt->link_work, 0); + callout_init(&nt->link_watchdog, 0); + TASK_INIT(&nt->link_cleanup, 0, ntb_transport_link_cleanup_work, nt); - rc = ntb_register_event_callback(ntb, - ntb_transport_event_callback); + rc = ntb_set_ctx(ntb, nt, &ntb_transport_ops); if (rc != 0) goto err; - if (ntb_query_link_status(ntb)) { - if (bootverbose) - device_printf(ntb_get_device(ntb), "link up\n"); - callout_reset(&nt->link_work, 0, ntb_transport_link_work, nt); - } + nt->link_is_up = false; + ntb_link_enable(ntb, NTB_SPEED_AUTO, NTB_WIDTH_AUTO); + ntb_link_event(ntb); + callout_reset(&nt->link_work, 0, ntb_transport_link_work, nt); + if (enable_xeon_watchdog != 0) + callout_reset(&nt->link_watchdog, 0, xeon_link_watchdog_hb, nt); return (0); err: - free(nt->qps, M_NTB_IF); - ntb_unregister_transport(ntb); + free(nt->qp_vec, M_NTB_IF); + nt->qp_vec = NULL; return (rc); } static void -ntb_transport_free(void *transport) +ntb_transport_free(struct ntb_transport_ctx *nt) { - struct ntb_netdev *nt = transport; struct ntb_softc *ntb = nt->ntb; - int i; + struct _qpset qp_bitmap_alloc; + uint8_t i; - nt->transport_link = NTB_LINK_DOWN; - + ntb_transport_link_cleanup(nt); + taskqueue_drain(taskqueue_swi, &nt->link_cleanup); callout_drain(&nt->link_work); + callout_drain(&nt->link_watchdog); - /* verify that all the qps are freed */ - for (i = 0; i < nt->max_qps; i++) - if (!test_bit(i, &nt->qp_bitmap)) - ntb_transport_free_queue(&nt->qps[i]); + BIT_COPY(QP_SETSIZE, &nt->qp_bitmap, &qp_bitmap_alloc); + BIT_NAND(QP_SETSIZE, &qp_bitmap_alloc, &nt->qp_bitmap_free); + /* Verify that all the QPs are freed */ + for (i = 0; i < nt->qp_count; i++) + if (test_bit(i, &qp_bitmap_alloc)) + ntb_transport_free_queue(&nt->qp_vec[i]); - ntb_unregister_event_callback(ntb); + ntb_link_disable(ntb); + ntb_clear_ctx(ntb); - for (i = 0; i < NTB_NUM_MW; i++) - if (nt->mw[i].virt_addr != NULL) - contigfree(nt->mw[i].virt_addr, nt->mw[i].size, - M_NTB_IF); + for (i = 0; i < nt->mw_count; i++) + ntb_free_mw(nt, i); - free(nt->qps, M_NTB_IF); - ntb_unregister_transport(ntb); + free(nt->qp_vec, M_NTB_IF); } static void -ntb_transport_init_queue(struct ntb_netdev *nt, unsigned int qp_num) +ntb_transport_init_queue(struct ntb_transport_ctx *nt, unsigned int qp_num) { + struct ntb_transport_mw *mw; struct ntb_transport_qp *qp; - unsigned int num_qps_mw, tx_size; - uint8_t mw_num = QP_TO_MW(qp_num); + vm_paddr_t mw_base; + uint64_t mw_size, qp_offset; + size_t tx_size; + unsigned num_qps_mw, mw_num, mw_count; - qp = &nt->qps[qp_num]; + mw_count = nt->mw_count; + mw_num = QP_TO_MW(nt, qp_num); + mw = &nt->mw_vec[mw_num]; + + qp = &nt->qp_vec[qp_num]; qp->qp_num = qp_num; qp->transport = nt; qp->ntb = nt->ntb; - qp->qp_link = NTB_LINK_DOWN; - qp->client_ready = NTB_LINK_DOWN; + qp->client_ready = false; qp->event_handler = NULL; + ntb_qp_link_down_reset(qp); - if (nt->max_qps % NTB_NUM_MW && mw_num < nt->max_qps % NTB_NUM_MW) - num_qps_mw = nt->max_qps / NTB_NUM_MW + 1; + if (nt->qp_count % mw_count && mw_num + 1 < nt->qp_count / mw_count) + num_qps_mw = nt->qp_count / mw_count + 1; else - num_qps_mw = nt->max_qps / NTB_NUM_MW; + num_qps_mw = nt->qp_count / mw_count; - tx_size = (unsigned int) ntb_get_mw_size(qp->ntb, mw_num) / num_qps_mw; - qp->rx_info = (struct ntb_rx_info *) - ((char *)ntb_get_mw_vbase(qp->ntb, mw_num) + - (qp_num / NTB_NUM_MW * tx_size)); + mw_base = mw->phys_addr; + mw_size = mw->phys_size; + + tx_size = mw_size / num_qps_mw; + qp_offset = tx_size * (qp_num / mw_count); + + qp->tx_mw = mw->vbase + qp_offset; + KASSERT(qp->tx_mw != NULL, ("uh oh?")); + + /* XXX Assumes that a vm_paddr_t is equivalent to bus_addr_t */ + qp->tx_mw_phys = mw_base + qp_offset; + KASSERT(qp->tx_mw_phys != 0, ("uh oh?")); + tx_size -= sizeof(struct ntb_rx_info); + qp->rx_info = (void *)(qp->tx_mw + tx_size); - qp->tx_mw = qp->rx_info + sizeof(struct ntb_rx_info); - qp->tx_max_frame = min(transport_mtu + sizeof(struct ntb_payload_header), - tx_size); + /* Due to house-keeping, there must be at least 2 buffs */ + qp->tx_max_frame = qmin(tx_size / 2, + transport_mtu + sizeof(struct ntb_payload_header)); qp->tx_max_entry = tx_size / qp->tx_max_frame; - qp->tx_index = 0; callout_init(&qp->link_work, 0); callout_init(&qp->queue_full, CALLOUT_MPSAFE); callout_init(&qp->rx_full, CALLOUT_MPSAFE); - mtx_init(&qp->ntb_rx_pend_q_lock, "ntb rx pend q", NULL, MTX_SPIN); - mtx_init(&qp->ntb_rx_free_q_lock, "ntb rx free q", NULL, MTX_SPIN); + mtx_init(&qp->ntb_rx_q_lock, "ntb rx q", NULL, MTX_SPIN); mtx_init(&qp->ntb_tx_free_q_lock, "ntb tx free q", NULL, MTX_SPIN); - TASK_INIT(&qp->rx_completion_task, 0, ntb_rx_completion_task, qp); + TASK_INIT(&qp->rx_completion_task, 0, ntb_complete_rxc, qp); + TASK_INIT(&qp->rxc_db_work, 0, ntb_transport_rxc_db, qp); + STAILQ_INIT(&qp->rx_post_q); STAILQ_INIT(&qp->rx_pend_q); - STAILQ_INIT(&qp->rx_free_q); STAILQ_INIT(&qp->tx_free_q); + + callout_reset(&qp->link_work, 0, ntb_qp_link_work, qp); } static void ntb_transport_free_queue(struct ntb_transport_qp *qp) { struct ntb_queue_entry *entry; if (qp == NULL) return; callout_drain(&qp->link_work); - ntb_unregister_db_callback(qp->ntb, qp->qp_num); + ntb_db_set_mask(qp->ntb, 1ull << qp->qp_num); + taskqueue_drain(taskqueue_swi, &qp->rxc_db_work); + taskqueue_drain(taskqueue_swi, &qp->rx_completion_task); - while ((entry = ntb_list_rm(&qp->ntb_rx_free_q_lock, &qp->rx_free_q))) + qp->cb_data = NULL; + qp->rx_handler = NULL; + qp->tx_handler = NULL; + qp->event_handler = NULL; + + while ((entry = ntb_list_rm(&qp->ntb_rx_q_lock, &qp->rx_pend_q))) free(entry, M_NTB_IF); - while ((entry = ntb_list_rm(&qp->ntb_rx_pend_q_lock, &qp->rx_pend_q))) + while ((entry = ntb_list_rm(&qp->ntb_rx_q_lock, &qp->rx_post_q))) free(entry, M_NTB_IF); while ((entry = ntb_list_rm(&qp->ntb_tx_free_q_lock, &qp->tx_free_q))) free(entry, M_NTB_IF); - set_bit(qp->qp_num, &qp->transport->qp_bitmap); + set_bit(qp->qp_num, &qp->transport->qp_bitmap_free); } /** * ntb_transport_create_queue - Create a new NTB transport layer queue * @rx_handler: receive callback function * @tx_handler: transmit callback function * @event_handler: event callback function * * Create a new NTB transport layer queue and provide the queue with a callback * routine for both transmit and receive. The receive callback routine will be * used to pass up data when the transport has received it on the queue. The * transmit callback routine will be called when the transport has completed the * transmission of the data on the queue and the data is ready to be freed. * * RETURNS: pointer to newly created ntb_queue, NULL on error. */ static struct ntb_transport_qp * -ntb_transport_create_queue(void *data, struct ntb_softc *pdev, +ntb_transport_create_queue(void *data, struct ntb_softc *ntb, const struct ntb_queue_handlers *handlers) { struct ntb_queue_entry *entry; struct ntb_transport_qp *qp; - struct ntb_netdev *nt; + struct ntb_transport_ctx *nt; unsigned int free_queue; - int rc, i; + int i; - nt = ntb_find_transport(pdev); - if (nt == NULL) - goto err; + nt = ntb_get_ctx(ntb, NULL); + KASSERT(nt != NULL, ("bogus")); - free_queue = ffs(nt->qp_bitmap); + free_queue = ffs_bit(&nt->qp_bitmap); if (free_queue == 0) - goto err; + return (NULL); /* decrement free_queue to make it zero based */ free_queue--; - clear_bit(free_queue, &nt->qp_bitmap); - - qp = &nt->qps[free_queue]; + qp = &nt->qp_vec[free_queue]; + clear_bit(qp->qp_num, &nt->qp_bitmap_free); qp->cb_data = data; qp->rx_handler = handlers->rx_handler; qp->tx_handler = handlers->tx_handler; qp->event_handler = handlers->event_handler; for (i = 0; i < NTB_QP_DEF_NUM_ENTRIES; i++) { - entry = malloc(sizeof(struct ntb_queue_entry), M_NTB_IF, - M_WAITOK|M_ZERO); + entry = malloc(sizeof(*entry), M_NTB_IF, M_WAITOK | M_ZERO); entry->cb_data = nt->ifp; entry->buf = NULL; entry->len = transport_mtu; - ntb_list_add(&qp->ntb_rx_pend_q_lock, entry, &qp->rx_pend_q); + ntb_list_add(&qp->ntb_rx_q_lock, entry, &qp->rx_pend_q); } for (i = 0; i < NTB_QP_DEF_NUM_ENTRIES; i++) { - entry = malloc(sizeof(struct ntb_queue_entry), M_NTB_IF, - M_WAITOK|M_ZERO); + entry = malloc(sizeof(*entry), M_NTB_IF, M_WAITOK | M_ZERO); ntb_list_add(&qp->ntb_tx_free_q_lock, entry, &qp->tx_free_q); } - rc = ntb_register_db_callback(qp->ntb, free_queue, qp, - ntb_transport_rxc_db); - if (rc != 0) - goto err1; - + ntb_db_clear(ntb, 1ull << qp->qp_num); + ntb_db_clear_mask(ntb, 1ull << qp->qp_num); return (qp); - -err1: - while ((entry = ntb_list_rm(&qp->ntb_tx_free_q_lock, &qp->tx_free_q))) - free(entry, M_NTB_IF); - while ((entry = ntb_list_rm(&qp->ntb_rx_free_q_lock, &qp->rx_free_q))) - free(entry, M_NTB_IF); - set_bit(free_queue, &nt->qp_bitmap); -err: - return (NULL); } /** * ntb_transport_link_up - Notify NTB transport of client readiness to use queue * @qp: NTB transport layer queue to be enabled * * Notify NTB transport layer of client readiness to use queue */ static void ntb_transport_link_up(struct ntb_transport_qp *qp) { + struct ntb_transport_ctx *nt; if (qp == NULL) return; - qp->client_ready = NTB_LINK_UP; - if (bootverbose) - device_printf(ntb_get_device(qp->ntb), "qp client ready\n"); + qp->client_ready = true; - if (qp->transport->transport_link == NTB_LINK_UP) + nt = qp->transport; + ntb_printf(2, "qp client ready\n"); + + if (qp->transport->link_is_up) callout_reset(&qp->link_work, 0, ntb_qp_link_work, qp); } /* Transport Tx */ /** * ntb_transport_tx_enqueue - Enqueue a new NTB queue entry * @qp: NTB transport layer queue the entry is to be enqueued on * @cb: per buffer pointer for callback function to use * @data: pointer to data buffer that will be sent * @len: length of the data buffer * * Enqueue a new transmit buffer onto the transport queue from which a NTB - * payload will be transmitted. This assumes that a lock is behing held to + * payload will be transmitted. This assumes that a lock is being held to * serialize access to the qp. * * RETURNS: An appropriate ERRNO error value on error, or zero for success. */ static int ntb_transport_tx_enqueue(struct ntb_transport_qp *qp, void *cb, void *data, unsigned int len) { struct ntb_queue_entry *entry; int rc; - if (qp == NULL || qp->qp_link != NTB_LINK_UP || len == 0) { + if (qp == NULL || !qp->link_is_up || len == 0) { CTR0(KTR_NTB, "TX: link not up"); return (EINVAL); } entry = ntb_list_rm(&qp->ntb_tx_free_q_lock, &qp->tx_free_q); if (entry == NULL) { CTR0(KTR_NTB, "TX: could not get entry from tx_free_q"); - return (ENOMEM); + qp->tx_err_no_buf++; + return (EBUSY); } CTR1(KTR_NTB, "TX: got entry %p from tx_free_q", entry); entry->cb_data = cb; entry->buf = data; entry->len = len; entry->flags = 0; rc = ntb_process_tx(qp, entry); if (rc != 0) { ntb_list_add(&qp->ntb_tx_free_q_lock, entry, &qp->tx_free_q); CTR1(KTR_NTB, "TX: process_tx failed. Returning entry %p to tx_free_q", entry); } return (rc); } static int ntb_process_tx(struct ntb_transport_qp *qp, struct ntb_queue_entry *entry) { void *offset; - offset = (char *)qp->tx_mw + qp->tx_max_frame * qp->tx_index; + offset = qp->tx_mw + qp->tx_max_frame * qp->tx_index; CTR3(KTR_NTB, - "TX: process_tx: tx_pkts=%u, tx_index=%u, remote entry=%u", + "TX: process_tx: tx_pkts=%lu, tx_index=%u, remote entry=%u", qp->tx_pkts, qp->tx_index, qp->remote_rx_info->entry); if (qp->tx_index == qp->remote_rx_info->entry) { CTR0(KTR_NTB, "TX: ring full"); qp->tx_ring_full++; return (EAGAIN); } if (entry->len > qp->tx_max_frame - sizeof(struct ntb_payload_header)) { if (qp->tx_handler != NULL) qp->tx_handler(qp, qp->cb_data, entry->buf, - EIO); + EIO); + else + m_freem(entry->buf); + entry->buf = NULL; ntb_list_add(&qp->ntb_tx_free_q_lock, entry, &qp->tx_free_q); CTR1(KTR_NTB, "TX: frame too big. returning entry %p to tx_free_q", entry); return (0); } CTR2(KTR_NTB, "TX: copying entry %p to offset %p", entry, offset); - ntb_tx_copy_task(qp, entry, offset); + ntb_memcpy_tx(qp, entry, offset); qp->tx_index++; qp->tx_index %= qp->tx_max_entry; qp->tx_pkts++; return (0); } static void -ntb_tx_copy_task(struct ntb_transport_qp *qp, struct ntb_queue_entry *entry, +ntb_memcpy_tx(struct ntb_transport_qp *qp, struct ntb_queue_entry *entry, void *offset) { struct ntb_payload_header *hdr; + /* This piece is from Linux' ntb_async_tx() */ + hdr = (struct ntb_payload_header *)((char *)offset + qp->tx_max_frame - + sizeof(struct ntb_payload_header)); + entry->x_hdr = hdr; + iowrite32(entry->len, &hdr->len); + iowrite32(qp->tx_pkts, &hdr->ver); + + /* This piece is ntb_memcpy_tx() */ CTR2(KTR_NTB, "TX: copying %d bytes to offset %p", entry->len, offset); - if (entry->buf != NULL) + if (entry->buf != NULL) { m_copydata((struct mbuf *)entry->buf, 0, entry->len, offset); - hdr = (struct ntb_payload_header *)((char *)offset + qp->tx_max_frame - - sizeof(struct ntb_payload_header)); - hdr->len = entry->len; /* TODO: replace with bus_space_write */ - hdr->ver = qp->tx_pkts; /* TODO: replace with bus_space_write */ - wmb(); - /* TODO: replace with bus_space_write */ - hdr->flags = entry->flags | IF_NTB_DESC_DONE_FLAG; + /* + * Ensure that the data is fully copied before setting the + * flags + */ + wmb(); + } - ntb_ring_sdb(qp->ntb, qp->qp_num); + /* The rest is ntb_tx_copy_callback() */ + iowrite32(entry->flags | IF_NTB_DESC_DONE_FLAG, &hdr->flags); + CTR1(KTR_NTB, "TX: hdr %p set DESC_DONE", hdr); - /* + ntb_peer_db_set(qp->ntb, 1ull << qp->qp_num); + + /* * The entry length can only be zero if the packet is intended to be a * "link down" or similar. Since no payload is being sent in these * cases, there is nothing to add to the completion queue. */ if (entry->len > 0) { qp->tx_bytes += entry->len; if (qp->tx_handler) - qp->tx_handler(qp, qp->cb_data, entry->cb_data, - entry->len); + qp->tx_handler(qp, qp->cb_data, entry->buf, + entry->len); + else + m_freem(entry->buf); + entry->buf = NULL; } - CTR2(KTR_NTB, - "TX: entry %p sent. hdr->ver = %d, Returning to tx_free_q", entry, - hdr->ver); + CTR3(KTR_NTB, + "TX: entry %p sent. hdr->ver = %u, hdr->flags = 0x%x, Returning " + "to tx_free_q", entry, hdr->ver, hdr->flags); ntb_list_add(&qp->ntb_tx_free_q_lock, entry, &qp->tx_free_q); } static void ntb_qp_full(void *arg) { CTR0(KTR_NTB, "TX: qp_full callout"); ntb_start(arg); } /* Transport Rx */ static void -ntb_transport_rxc_db(void *data, int db_num) +ntb_transport_rxc_db(void *arg, int pending __unused) { - struct ntb_transport_qp *qp = data; + struct ntb_transport_qp *qp = arg; + ntb_q_idx_t i; + int rc; - ntb_transport_rx(qp); -} - -static void -ntb_rx_pendq_full(void *arg) -{ - - CTR0(KTR_NTB, "RX: ntb_rx_pendq_full callout"); - ntb_transport_rx(arg); -} - -static void -ntb_transport_rx(struct ntb_transport_qp *qp) -{ - int rc, i; - - /* + /* * Limit the number of packets processed in a single interrupt to * provide fairness to others */ - mtx_lock(&qp->transport->rx_lock); CTR0(KTR_NTB, "RX: transport_rx"); - for (i = 0; i < NTB_RX_MAX_PKTS; i++) { + mtx_lock(&qp->transport->rx_lock); + for (i = 0; i < qp->rx_max_entry; i++) { rc = ntb_process_rxc(qp); if (rc != 0) { CTR0(KTR_NTB, "RX: process_rxc failed"); break; } } mtx_unlock(&qp->transport->rx_lock); + + if (i == qp->rx_max_entry) + taskqueue_enqueue(taskqueue_swi, &qp->rxc_db_work); + else if ((ntb_db_read(qp->ntb) & (1ull << qp->qp_num)) != 0) { + /* If db is set, clear it and read it back to commit clear. */ + ntb_db_clear(qp->ntb, 1ull << qp->qp_num); + (void)ntb_db_read(qp->ntb); + + /* + * An interrupt may have arrived between finishing + * ntb_process_rxc and clearing the doorbell bit: there might + * be some more work to do. + */ + taskqueue_enqueue(taskqueue_swi, &qp->rxc_db_work); + } } static int ntb_process_rxc(struct ntb_transport_qp *qp) { struct ntb_payload_header *hdr; struct ntb_queue_entry *entry; - void *offset; + caddr_t offset; - offset = (void *) - ((char *)qp->rx_buff + qp->rx_max_frame * qp->rx_index); - hdr = (void *) - ((char *)offset + qp->rx_max_frame - - sizeof(struct ntb_payload_header)); + offset = qp->rx_buff + qp->rx_max_frame * qp->rx_index; + hdr = (void *)(offset + qp->rx_max_frame - + sizeof(struct ntb_payload_header)); CTR1(KTR_NTB, "RX: process_rxc rx_index = %u", qp->rx_index); - entry = ntb_list_rm(&qp->ntb_rx_pend_q_lock, &qp->rx_pend_q); - if (entry == NULL) { - qp->rx_err_no_buf++; - CTR0(KTR_NTB, "RX: No entries in rx_pend_q"); - return (ENOMEM); - } - callout_stop(&qp->rx_full); - CTR1(KTR_NTB, "RX: rx entry %p from rx_pend_q", entry); - if ((hdr->flags & IF_NTB_DESC_DONE_FLAG) == 0) { - CTR1(KTR_NTB, - "RX: hdr not done. Returning entry %p to rx_pend_q", entry); - ntb_list_add(&qp->ntb_rx_pend_q_lock, entry, &qp->rx_pend_q); + CTR0(KTR_NTB, "RX: hdr not done"); qp->rx_ring_empty++; return (EAGAIN); } - if (hdr->ver != (uint32_t) qp->rx_pkts) { - CTR3(KTR_NTB,"RX: ver != rx_pkts (%x != %lx). " - "Returning entry %p to rx_pend_q", hdr->ver, qp->rx_pkts, - entry); - ntb_list_add(&qp->ntb_rx_pend_q_lock, entry, &qp->rx_pend_q); + if ((hdr->flags & IF_NTB_LINK_DOWN_FLAG) != 0) { + CTR0(KTR_NTB, "RX: link down"); + ntb_qp_link_down(qp); + hdr->flags = 0; + return (EAGAIN); + } + + if (hdr->ver != (uint32_t)qp->rx_pkts) { + CTR2(KTR_NTB,"RX: ver != rx_pkts (%x != %lx). " + "Returning entry to rx_pend_q", hdr->ver, qp->rx_pkts); qp->rx_err_ver++; return (EIO); } - if ((hdr->flags & IF_NTB_LINK_DOWN_FLAG) != 0) { - ntb_qp_link_down(qp); - CTR1(KTR_NTB, - "RX: link down. adding entry %p back to rx_pend_q", entry); - ntb_list_add(&qp->ntb_rx_pend_q_lock, entry, &qp->rx_pend_q); - goto out; + entry = ntb_list_mv(&qp->ntb_rx_q_lock, &qp->rx_pend_q, &qp->rx_post_q); + if (entry == NULL) { + qp->rx_err_no_buf++; + CTR0(KTR_NTB, "RX: No entries in rx_pend_q"); + return (EAGAIN); } + callout_stop(&qp->rx_full); + CTR1(KTR_NTB, "RX: rx entry %p from rx_pend_q", entry); - if (hdr->len <= entry->len) { - entry->len = hdr->len; - ntb_rx_copy_task(qp, entry, offset); - } else { - CTR1(KTR_NTB, - "RX: len too long. Returning entry %p to rx_pend_q", entry); - ntb_list_add(&qp->ntb_rx_pend_q_lock, entry, &qp->rx_pend_q); + entry->x_hdr = hdr; + entry->index = qp->rx_index; + if (hdr->len > entry->len) { + CTR2(KTR_NTB, "RX: len too long. Wanted %ju got %ju", + (uintmax_t)hdr->len, (uintmax_t)entry->len); qp->rx_err_oflow++; - } - qp->rx_bytes += hdr->len; - qp->rx_pkts++; - CTR1(KTR_NTB, "RX: received %ld rx_pkts", qp->rx_pkts); + entry->len = -EIO; + entry->flags |= IF_NTB_DESC_DONE_FLAG; + taskqueue_enqueue(taskqueue_swi, &qp->rx_completion_task); + } else { + qp->rx_bytes += hdr->len; + qp->rx_pkts++; -out: - /* Ensure that the data is globally visible before clearing the flag */ - wmb(); - hdr->flags = 0; - /* TODO: replace with bus_space_write */ - qp->rx_info->entry = qp->rx_index; + CTR1(KTR_NTB, "RX: received %ld rx_pkts", qp->rx_pkts); + entry->len = hdr->len; + + ntb_memcpy_rx(qp, entry, offset); + } + qp->rx_index++; qp->rx_index %= qp->rx_max_entry; - return (0); } static void -ntb_rx_copy_task(struct ntb_transport_qp *qp, struct ntb_queue_entry *entry, +ntb_memcpy_rx(struct ntb_transport_qp *qp, struct ntb_queue_entry *entry, void *offset) { struct ifnet *ifp = entry->cb_data; unsigned int len = entry->len; struct mbuf *m; CTR2(KTR_NTB, "RX: copying %d bytes from offset %p", len, offset); m = m_devget(offset, len, 0, ifp, NULL); m->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID; entry->buf = (void *)m; - CTR2(KTR_NTB, - "RX: copied entry %p to mbuf %p. Adding entry to rx_free_q", entry, - m); - ntb_list_add(&qp->ntb_rx_free_q_lock, entry, &qp->rx_free_q); + /* Ensure that the data is globally visible before clearing the flag */ + wmb(); + CTR2(KTR_NTB, "RX: copied entry %p to mbuf %p.", entry, m); + ntb_rx_copy_callback(qp, entry); +} + +static inline void +ntb_rx_copy_callback(struct ntb_transport_qp *qp, void *data) +{ + struct ntb_queue_entry *entry; + + entry = data; + entry->flags |= IF_NTB_DESC_DONE_FLAG; taskqueue_enqueue(taskqueue_swi, &qp->rx_completion_task); } static void -ntb_rx_completion_task(void *arg, int pending) +ntb_complete_rxc(void *arg, int pending) { struct ntb_transport_qp *qp = arg; - struct mbuf *m; struct ntb_queue_entry *entry; + struct mbuf *m; + unsigned len; CTR0(KTR_NTB, "RX: rx_completion_task"); - while ((entry = ntb_list_rm(&qp->ntb_rx_free_q_lock, &qp->rx_free_q))) { + mtx_lock_spin(&qp->ntb_rx_q_lock); + + while (!STAILQ_EMPTY(&qp->rx_post_q)) { + entry = STAILQ_FIRST(&qp->rx_post_q); + if ((entry->flags & IF_NTB_DESC_DONE_FLAG) == 0) + break; + + entry->x_hdr->flags = 0; + iowrite32(entry->index, &qp->rx_info->entry); + + STAILQ_REMOVE_HEAD(&qp->rx_post_q, entry); + + len = entry->len; m = entry->buf; - CTR2(KTR_NTB, "RX: completing entry %p, mbuf %p", entry, m); - if (qp->rx_handler && qp->client_ready == NTB_LINK_UP) - qp->rx_handler(qp, qp->cb_data, m, entry->len); + /* + * Re-initialize queue_entry for reuse; rx_handler takes + * ownership of the mbuf. + */ entry->buf = NULL; - entry->len = qp->transport->bufsize; + entry->len = transport_mtu; + entry->cb_data = qp->transport->ifp; - CTR1(KTR_NTB,"RX: entry %p removed from rx_free_q " - "and added to rx_pend_q", entry); - ntb_list_add(&qp->ntb_rx_pend_q_lock, entry, &qp->rx_pend_q); - if (qp->rx_err_no_buf > qp->last_rx_no_buf) { - qp->last_rx_no_buf = qp->rx_err_no_buf; - CTR0(KTR_NTB, "RX: could spawn rx task"); - callout_reset(&qp->rx_full, hz / 1000, ntb_rx_pendq_full, - qp); + STAILQ_INSERT_TAIL(&qp->rx_pend_q, entry, entry); + + mtx_unlock_spin(&qp->ntb_rx_q_lock); + + CTR2(KTR_NTB, "RX: completing entry %p, mbuf %p", entry, m); + if (qp->rx_handler != NULL && qp->client_ready) + qp->rx_handler(qp, qp->cb_data, m, len); + else + m_freem(m); + + mtx_lock_spin(&qp->ntb_rx_q_lock); + } + + mtx_unlock_spin(&qp->ntb_rx_q_lock); +} + +static void +ntb_transport_doorbell_callback(void *data, uint32_t vector) +{ + struct ntb_transport_ctx *nt = data; + struct ntb_transport_qp *qp; + struct _qpset db_bits; + uint64_t vec_mask; + unsigned qp_num; + + BIT_COPY(QP_SETSIZE, &nt->qp_bitmap, &db_bits); + BIT_NAND(QP_SETSIZE, &db_bits, &nt->qp_bitmap_free); + + vec_mask = ntb_db_vector_mask(nt->ntb, vector); + while (vec_mask != 0) { + qp_num = ffsll(vec_mask) - 1; + + if (test_bit(qp_num, &db_bits)) { + qp = &nt->qp_vec[qp_num]; + taskqueue_enqueue(taskqueue_swi, &qp->rxc_db_work); } + + vec_mask &= ~(1ull << qp_num); } } /* Link Event handler */ static void -ntb_transport_event_callback(void *data, enum ntb_hw_event event) +ntb_transport_event_callback(void *data) { - struct ntb_netdev *nt = data; + struct ntb_transport_ctx *nt = data; - switch (event) { - case NTB_EVENT_HW_LINK_UP: - if (bootverbose) - device_printf(ntb_get_device(nt->ntb), "HW link up\n"); + if (ntb_link_is_up(nt->ntb, NULL, NULL)) { + ntb_printf(1, "HW link up\n"); callout_reset(&nt->link_work, 0, ntb_transport_link_work, nt); - break; - case NTB_EVENT_HW_LINK_DOWN: - if (bootverbose) - device_printf(ntb_get_device(nt->ntb), "HW link down\n"); - ntb_transport_link_cleanup(nt); - break; - default: - panic("ntb: Unknown NTB event"); + } else { + ntb_printf(1, "HW link down\n"); + taskqueue_enqueue(taskqueue_swi, &nt->link_cleanup); } } /* Link bring up */ static void ntb_transport_link_work(void *arg) { - struct ntb_netdev *nt = arg; + struct ntb_transport_ctx *nt = arg; struct ntb_softc *ntb = nt->ntb; struct ntb_transport_qp *qp; + uint64_t val64, size; uint32_t val; - int rc, i; + unsigned i; + int rc; - /* send the local info */ - rc = ntb_write_remote_spad(ntb, IF_NTB_VERSION, NTB_TRANSPORT_VERSION); - if (rc != 0) - goto out; + /* send the local info, in the opposite order of the way we read it */ + for (i = 0; i < nt->mw_count; i++) { + size = nt->mw_vec[i].phys_size; - rc = ntb_write_remote_spad(ntb, IF_NTB_MW0_SZ, ntb_get_mw_size(ntb, 0)); - if (rc != 0) - goto out; + if (max_mw_size != 0 && size > max_mw_size) + size = max_mw_size; - rc = ntb_write_remote_spad(ntb, IF_NTB_MW1_SZ, ntb_get_mw_size(ntb, 1)); - if (rc != 0) - goto out; + ntb_peer_spad_write(ntb, IF_NTB_MW0_SZ_HIGH + (i * 2), + size >> 32); + ntb_peer_spad_write(ntb, IF_NTB_MW0_SZ_LOW + (i * 2), size); + } - rc = ntb_write_remote_spad(ntb, IF_NTB_NUM_QPS, nt->max_qps); - if (rc != 0) - goto out; + ntb_peer_spad_write(ntb, IF_NTB_NUM_MWS, nt->mw_count); - rc = ntb_read_remote_spad(ntb, IF_NTB_QP_LINKS, &val); - if (rc != 0) - goto out; + ntb_peer_spad_write(ntb, IF_NTB_NUM_QPS, nt->qp_count); - rc = ntb_write_remote_spad(ntb, IF_NTB_QP_LINKS, val); - if (rc != 0) - goto out; + ntb_peer_spad_write(ntb, IF_NTB_VERSION, NTB_TRANSPORT_VERSION); /* Query the remote side for its info */ - rc = ntb_read_local_spad(ntb, IF_NTB_VERSION, &val); - if (rc != 0) - goto out; - + val = 0; + ntb_spad_read(ntb, IF_NTB_VERSION, &val); if (val != NTB_TRANSPORT_VERSION) goto out; - rc = ntb_read_local_spad(ntb, IF_NTB_NUM_QPS, &val); - if (rc != 0) + ntb_spad_read(ntb, IF_NTB_NUM_QPS, &val); + if (val != nt->qp_count) goto out; - if (val != nt->max_qps) + ntb_spad_read(ntb, IF_NTB_NUM_MWS, &val); + if (val != nt->mw_count) goto out; - rc = ntb_read_local_spad(ntb, IF_NTB_MW0_SZ, &val); - if (rc != 0) - goto out; + for (i = 0; i < nt->mw_count; i++) { + ntb_spad_read(ntb, IF_NTB_MW0_SZ_HIGH + (i * 2), &val); + val64 = (uint64_t)val << 32; - if (val == 0) - goto out; + ntb_spad_read(ntb, IF_NTB_MW0_SZ_LOW + (i * 2), &val); + val64 |= val; - rc = ntb_set_mw(nt, 0, val); - if (rc != 0) - return; + rc = ntb_set_mw(nt, i, val64); + if (rc != 0) + goto free_mws; + } - rc = ntb_read_local_spad(ntb, IF_NTB_MW1_SZ, &val); - if (rc != 0) - goto out; + nt->link_is_up = true; + ntb_printf(1, "transport link up\n"); - if (val == 0) - goto out; + for (i = 0; i < nt->qp_count; i++) { + qp = &nt->qp_vec[i]; - rc = ntb_set_mw(nt, 1, val); - if (rc != 0) - return; - - nt->transport_link = NTB_LINK_UP; - if (bootverbose) - device_printf(ntb_get_device(ntb), "transport link up\n"); - - for (i = 0; i < nt->max_qps; i++) { - qp = &nt->qps[i]; - ntb_transport_setup_qp_mw(nt, i); - if (qp->client_ready == NTB_LINK_UP) + if (qp->client_ready) callout_reset(&qp->link_work, 0, ntb_qp_link_work, qp); } return; +free_mws: + for (i = 0; i < nt->mw_count; i++) + ntb_free_mw(nt, i); out: - if (ntb_query_link_status(ntb)) + if (ntb_link_is_up(ntb, NULL, NULL)) callout_reset(&nt->link_work, - NTB_LINK_DOWN_TIMEOUT * hz / 1000, ntb_transport_link_work, nt); + NTB_LINK_DOWN_TIMEOUT * hz / 1000, ntb_transport_link_work, nt); } static int -ntb_set_mw(struct ntb_netdev *nt, int num_mw, unsigned int size) +ntb_set_mw(struct ntb_transport_ctx *nt, int num_mw, size_t size) { - struct ntb_transport_mw *mw = &nt->mw[num_mw]; + struct ntb_transport_mw *mw = &nt->mw_vec[num_mw]; + size_t xlat_size, buff_size; + int rc; - /* Alloc memory for receiving data. Must be 4k aligned */ - mw->size = size; + if (size == 0) + return (EINVAL); - mw->virt_addr = contigmalloc(mw->size, M_NTB_IF, M_ZERO, 0, - BUS_SPACE_MAXADDR, mw->size, 0); + xlat_size = roundup(size, mw->xlat_align_size); + buff_size = xlat_size; + + /* No need to re-setup */ + if (mw->xlat_size == xlat_size) + return (0); + + if (mw->buff_size != 0) + ntb_free_mw(nt, num_mw); + + /* Alloc memory for receiving data. Must be aligned */ + mw->xlat_size = xlat_size; + mw->buff_size = buff_size; + + mw->virt_addr = contigmalloc(mw->buff_size, M_NTB_IF, M_ZERO, 0, + mw->addr_limit, mw->xlat_align, 0); if (mw->virt_addr == NULL) { - printf("ntb: Unable to allocate MW buffer of size %d\n", - (int)mw->size); + ntb_printf(0, "Unable to allocate MW buffer of size %zu/%zu\n", + mw->buff_size, mw->xlat_size); + mw->xlat_size = 0; + mw->buff_size = 0; return (ENOMEM); } /* TODO: replace with bus_space_* functions */ mw->dma_addr = vtophys(mw->virt_addr); + /* + * Ensure that the allocation from contigmalloc is aligned as + * requested. XXX: This may not be needed -- brought in for parity + * with the Linux driver. + */ + if (mw->dma_addr % mw->xlat_align != 0) { + ntb_printf(0, + "DMA memory 0x%jx not aligned to BAR size 0x%zx\n", + (uintmax_t)mw->dma_addr, size); + ntb_free_mw(nt, num_mw); + return (ENOMEM); + } + /* Notify HW the memory location of the receive buffer */ - ntb_set_mw_addr(nt->ntb, num_mw, mw->dma_addr); + rc = ntb_mw_set_trans(nt->ntb, num_mw, mw->dma_addr, mw->xlat_size); + if (rc) { + ntb_printf(0, "Unable to set mw%d translation\n", num_mw); + ntb_free_mw(nt, num_mw); + return (rc); + } return (0); } static void -ntb_transport_setup_qp_mw(struct ntb_netdev *nt, unsigned int qp_num) +ntb_free_mw(struct ntb_transport_ctx *nt, int num_mw) { - struct ntb_transport_qp *qp = &nt->qps[qp_num]; + struct ntb_transport_mw *mw = &nt->mw_vec[num_mw]; + + if (mw->virt_addr == NULL) + return; + + ntb_mw_clear_trans(nt->ntb, num_mw); + contigfree(mw->virt_addr, mw->xlat_size, M_NTB_IF); + mw->xlat_size = 0; + mw->buff_size = 0; + mw->virt_addr = NULL; +} + +static int +ntb_transport_setup_qp_mw(struct ntb_transport_ctx *nt, unsigned int qp_num) +{ + struct ntb_transport_qp *qp = &nt->qp_vec[qp_num]; + struct ntb_transport_mw *mw; void *offset; - unsigned int rx_size, num_qps_mw; - uint8_t mw_num = QP_TO_MW(qp_num); - unsigned int i; + ntb_q_idx_t i; + size_t rx_size; + unsigned num_qps_mw, mw_num, mw_count; - if (nt->max_qps % NTB_NUM_MW && mw_num < nt->max_qps % NTB_NUM_MW) - num_qps_mw = nt->max_qps / NTB_NUM_MW + 1; + mw_count = nt->mw_count; + mw_num = QP_TO_MW(nt, qp_num); + mw = &nt->mw_vec[mw_num]; + + if (mw->virt_addr == NULL) + return (ENOMEM); + + if (nt->qp_count % mw_count && mw_num + 1 < nt->qp_count / mw_count) + num_qps_mw = nt->qp_count / mw_count + 1; else - num_qps_mw = nt->max_qps / NTB_NUM_MW; + num_qps_mw = nt->qp_count / mw_count; - rx_size = (unsigned int) nt->mw[mw_num].size / num_qps_mw; - qp->remote_rx_info = (void *)((uint8_t *)nt->mw[mw_num].virt_addr + - (qp_num / NTB_NUM_MW * rx_size)); + rx_size = mw->xlat_size / num_qps_mw; + qp->rx_buff = mw->virt_addr + rx_size * (qp_num / mw_count); rx_size -= sizeof(struct ntb_rx_info); - qp->rx_buff = qp->remote_rx_info + sizeof(struct ntb_rx_info); - qp->rx_max_frame = min(transport_mtu + sizeof(struct ntb_payload_header), - rx_size); + qp->remote_rx_info = (void*)(qp->rx_buff + rx_size); + + /* Due to house-keeping, there must be at least 2 buffs */ + qp->rx_max_frame = qmin(rx_size / 2, + transport_mtu + sizeof(struct ntb_payload_header)); qp->rx_max_entry = rx_size / qp->rx_max_frame; qp->rx_index = 0; - qp->tx_index = 0; - qp->remote_rx_info->entry = qp->rx_max_entry; + qp->remote_rx_info->entry = qp->rx_max_entry - 1; - /* setup the hdr offsets with 0's */ + /* Set up the hdr offsets with 0s */ for (i = 0; i < qp->rx_max_entry; i++) { - offset = (void *)((uint8_t *)qp->rx_buff + - qp->rx_max_frame * (i + 1) - + offset = (void *)(qp->rx_buff + qp->rx_max_frame * (i + 1) - sizeof(struct ntb_payload_header)); memset(offset, 0, sizeof(struct ntb_payload_header)); } qp->rx_pkts = 0; qp->tx_pkts = 0; + qp->tx_index = 0; + + return (0); } static void ntb_qp_link_work(void *arg) { struct ntb_transport_qp *qp = arg; struct ntb_softc *ntb = qp->ntb; - struct ntb_netdev *nt = qp->transport; - int rc, val; + struct ntb_transport_ctx *nt = qp->transport; + uint32_t val, dummy; + ntb_spad_read(ntb, IF_NTB_QP_LINKS, &val); - rc = ntb_read_remote_spad(ntb, IF_NTB_QP_LINKS, &val); - if (rc != 0) - return; + ntb_peer_spad_write(ntb, IF_NTB_QP_LINKS, val | (1ull << qp->qp_num)); - rc = ntb_write_remote_spad(ntb, IF_NTB_QP_LINKS, val | 1 << qp->qp_num); - /* query remote spad for qp ready bits */ - rc = ntb_read_local_spad(ntb, IF_NTB_QP_LINKS, &val); + ntb_peer_spad_read(ntb, IF_NTB_QP_LINKS, &dummy); /* See if the remote side is up */ - if ((1 << qp->qp_num & val) != 0) { - qp->qp_link = NTB_LINK_UP; + if ((val & (1ull << qp->qp_num)) != 0) { + ntb_printf(2, "qp link up\n"); + qp->link_is_up = true; + if (qp->event_handler != NULL) qp->event_handler(qp->cb_data, NTB_LINK_UP); - if (bootverbose) - device_printf(ntb_get_device(ntb), "qp link up\n"); - } else if (nt->transport_link == NTB_LINK_UP) { + + taskqueue_enqueue(taskqueue_swi, &qp->rxc_db_work); + } else if (nt->link_is_up) callout_reset(&qp->link_work, NTB_LINK_DOWN_TIMEOUT * hz / 1000, ntb_qp_link_work, qp); - } } /* Link down event*/ static void -ntb_transport_link_cleanup(struct ntb_netdev *nt) +ntb_transport_link_cleanup(struct ntb_transport_ctx *nt) { - int i; + struct ntb_transport_qp *qp; + struct _qpset qp_bitmap_alloc; + unsigned i; - if (nt->transport_link == NTB_LINK_DOWN) - callout_drain(&nt->link_work); - else - nt->transport_link = NTB_LINK_DOWN; + BIT_COPY(QP_SETSIZE, &nt->qp_bitmap, &qp_bitmap_alloc); + BIT_NAND(QP_SETSIZE, &qp_bitmap_alloc, &nt->qp_bitmap_free); /* Pass along the info to any clients */ - for (i = 0; i < nt->max_qps; i++) - if (!test_bit(i, &nt->qp_bitmap)) - ntb_qp_link_down(&nt->qps[i]); + for (i = 0; i < nt->qp_count; i++) + if (test_bit(i, &qp_bitmap_alloc)) { + qp = &nt->qp_vec[i]; + ntb_qp_link_cleanup(qp); + callout_drain(&qp->link_work); + } - /* + if (!nt->link_is_up) + callout_drain(&nt->link_work); + + /* * The scratchpad registers keep the values if the remote side * goes down, blast them now to give them a sane value the next * time they are accessed */ for (i = 0; i < IF_NTB_MAX_SPAD; i++) - ntb_write_local_spad(nt->ntb, i, 0); + ntb_spad_write(nt->ntb, i, 0); } +static void +ntb_transport_link_cleanup_work(void *arg, int pending __unused) +{ + ntb_transport_link_cleanup(arg); +} + static void ntb_qp_link_down(struct ntb_transport_qp *qp) { ntb_qp_link_cleanup(qp); } static void +ntb_qp_link_down_reset(struct ntb_transport_qp *qp) +{ + + qp->link_is_up = false; + + qp->tx_index = qp->rx_index = 0; + qp->tx_bytes = qp->rx_bytes = 0; + qp->tx_pkts = qp->rx_pkts = 0; + + qp->rx_ring_empty = 0; + qp->tx_ring_full = 0; + + qp->rx_err_no_buf = qp->tx_err_no_buf = 0; + qp->rx_err_oflow = qp->rx_err_ver = 0; +} + +static void ntb_qp_link_cleanup(struct ntb_transport_qp *qp) { - struct ntb_netdev *nt = qp->transport; + struct ntb_transport_ctx *nt = qp->transport; - if (qp->qp_link == NTB_LINK_DOWN) { - callout_drain(&qp->link_work); - return; - } + callout_drain(&qp->link_work); + ntb_qp_link_down_reset(qp); if (qp->event_handler != NULL) qp->event_handler(qp->cb_data, NTB_LINK_DOWN); - qp->qp_link = NTB_LINK_DOWN; - - if (nt->transport_link == NTB_LINK_UP) + if (nt->link_is_up) callout_reset(&qp->link_work, NTB_LINK_DOWN_TIMEOUT * hz / 1000, ntb_qp_link_work, qp); } /* Link commanded down */ /** * ntb_transport_link_down - Notify NTB transport to no longer enqueue data * @qp: NTB transport layer queue to be disabled * * Notify NTB transport layer of client's desire to no longer receive data on * transport queue specified. It is the client's responsibility to ensure all - * entries on queue are purged or otherwise handled appropraitely. + * entries on queue are purged or otherwise handled appropriately. */ static void ntb_transport_link_down(struct ntb_transport_qp *qp) { - int rc, val; + uint32_t val; if (qp == NULL) return; - qp->client_ready = NTB_LINK_DOWN; + qp->client_ready = false; - rc = ntb_read_remote_spad(qp->ntb, IF_NTB_QP_LINKS, &val); - if (rc != 0) - return; + ntb_spad_read(qp->ntb, IF_NTB_QP_LINKS, &val); - rc = ntb_write_remote_spad(qp->ntb, IF_NTB_QP_LINKS, + ntb_peer_spad_write(qp->ntb, IF_NTB_QP_LINKS, val & ~(1 << qp->qp_num)); - if (qp->qp_link == NTB_LINK_UP) + if (qp->link_is_up) ntb_send_link_down(qp); else callout_drain(&qp->link_work); - } static void ntb_send_link_down(struct ntb_transport_qp *qp) { struct ntb_queue_entry *entry; int i, rc; - if (qp->qp_link == NTB_LINK_DOWN) + if (!qp->link_is_up) return; - qp->qp_link = NTB_LINK_DOWN; - for (i = 0; i < NTB_LINK_DOWN_TIMEOUT; i++) { entry = ntb_list_rm(&qp->ntb_tx_free_q_lock, &qp->tx_free_q); if (entry != NULL) break; pause("NTB Wait for link down", hz / 10); } if (entry == NULL) return; entry->cb_data = NULL; entry->buf = NULL; entry->len = 0; entry->flags = IF_NTB_LINK_DOWN_FLAG; mtx_lock(&qp->transport->tx_lock); rc = ntb_process_tx(qp, entry); if (rc != 0) printf("ntb: Failed to send link down\n"); mtx_unlock(&qp->transport->tx_lock); + + ntb_qp_link_down_reset(qp); } /* List Management */ static void ntb_list_add(struct mtx *lock, struct ntb_queue_entry *entry, struct ntb_queue_list *list) { mtx_lock_spin(lock); STAILQ_INSERT_TAIL(list, entry, entry); mtx_unlock_spin(lock); } static struct ntb_queue_entry * ntb_list_rm(struct mtx *lock, struct ntb_queue_list *list) { struct ntb_queue_entry *entry; mtx_lock_spin(lock); if (STAILQ_EMPTY(list)) { entry = NULL; goto out; } entry = STAILQ_FIRST(list); STAILQ_REMOVE_HEAD(list, entry); out: mtx_unlock_spin(lock); + return (entry); +} + +static struct ntb_queue_entry * +ntb_list_mv(struct mtx *lock, struct ntb_queue_list *from, + struct ntb_queue_list *to) +{ + struct ntb_queue_entry *entry; + + mtx_lock_spin(lock); + if (STAILQ_EMPTY(from)) { + entry = NULL; + goto out; + } + entry = STAILQ_FIRST(from); + STAILQ_REMOVE_HEAD(from, entry); + STAILQ_INSERT_TAIL(to, entry, entry); + +out: + mtx_unlock_spin(lock); return (entry); } /* Helper functions */ /* TODO: This too should really be part of the kernel */ #define EUI48_MULTICAST 1 << 0 #define EUI48_LOCALLY_ADMINISTERED 1 << 1 static void create_random_local_eui48(u_char *eaddr) { static uint8_t counter = 0; uint32_t seed = ticks; eaddr[0] = EUI48_LOCALLY_ADMINISTERED; memcpy(&eaddr[1], &seed, sizeof(uint32_t)); eaddr[5] = counter++; } /** * ntb_transport_max_size - Query the max payload size of a qp * @qp: NTB transport layer queue to be queried * * Query the maximum payload size permissible on the given qp * * RETURNS: the max payload size of a qp */ static unsigned int ntb_transport_max_size(struct ntb_transport_qp *qp) { if (qp == NULL) return (0); return (qp->tx_max_frame - sizeof(struct ntb_payload_header)); } Index: stable/10/sys/dev/ntb/ntb_hw/ntb_hw.c =================================================================== --- stable/10/sys/dev/ntb/ntb_hw/ntb_hw.c (revision 300372) +++ stable/10/sys/dev/ntb/ntb_hw/ntb_hw.c (revision 300373) @@ -1,1414 +1,2935 @@ /*- * Copyright (C) 2013 Intel Corporation + * Copyright (C) 2015 EMC Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include +#include #include #include #include #include +#include +#include #include #include #include #include #include #include #include #include "ntb_regs.h" #include "ntb_hw.h" /* * The Non-Transparent Bridge (NTB) is a device on some Intel processors that * allows you to connect two systems using a PCI-e link. * * This module contains the hardware abstraction layer for the NTB. It allows * you to send and recieve interrupts, map the memory windows and send and * receive messages in the scratch-pad registers. * * NOTE: Much of the code in this module is shared with Linux. Any patches may * be picked up and redistributed in Linux with a dual GPL/BSD license. */ -#define NTB_CONFIG_BAR 0 -#define NTB_B2B_BAR_1 1 -#define NTB_B2B_BAR_2 2 -#define NTB_MAX_BARS 3 -#define NTB_MW_TO_BAR(mw) ((mw) + 1) +#define MAX_MSIX_INTERRUPTS MAX(XEON_DB_COUNT, ATOM_DB_COUNT) -#define MAX_MSIX_INTERRUPTS MAX(XEON_MAX_DB_BITS, SOC_MAX_DB_BITS) +#define NTB_HB_TIMEOUT 1 /* second */ +#define ATOM_LINK_RECOVERY_TIME 500 /* ms */ +#define BAR_HIGH_MASK (~((1ull << 12) - 1)) -#define NTB_HB_TIMEOUT 1 /* second */ -#define SOC_LINK_RECOVERY_TIME 500 - #define DEVICE2SOFTC(dev) ((struct ntb_softc *) device_get_softc(dev)) enum ntb_device_type { NTB_XEON, - NTB_SOC + NTB_ATOM }; +/* ntb_conn_type are hardware numbers, cannot change. */ +enum ntb_conn_type { + NTB_CONN_TRANSPARENT = 0, + NTB_CONN_B2B = 1, + NTB_CONN_RP = 2, +}; + +enum ntb_b2b_direction { + NTB_DEV_USD = 0, + NTB_DEV_DSD = 1, +}; + +enum ntb_bar { + NTB_CONFIG_BAR = 0, + NTB_B2B_BAR_1, + NTB_B2B_BAR_2, + NTB_B2B_BAR_3, + NTB_MAX_BARS +}; + /* Device features and workarounds */ #define HAS_FEATURE(feature) \ ((ntb->features & (feature)) != 0) -#define NTB_BAR_SIZE_4K (1 << 0) -#define NTB_REGS_THRU_MW (1 << 1) - struct ntb_hw_info { uint32_t device_id; const char *desc; enum ntb_device_type type; - uint64_t features; + uint32_t features; }; struct ntb_pci_bar_info { bus_space_tag_t pci_bus_tag; bus_space_handle_t pci_bus_handle; int pci_resource_id; struct resource *pci_resource; vm_paddr_t pbase; - void *vbase; - u_long size; + caddr_t vbase; + vm_size_t size; + vm_memattr_t map_mode; + + /* Configuration register offsets */ + uint32_t psz_off; + uint32_t ssz_off; + uint32_t pbarxlat_off; }; struct ntb_int_info { struct resource *res; int rid; void *tag; }; -struct ntb_db_cb { - ntb_db_callback callback; - unsigned int db_num; - void *data; +struct ntb_vec { struct ntb_softc *ntb; + uint32_t num; }; +struct ntb_reg { + uint32_t ntb_ctl; + uint32_t lnk_sta; + uint8_t db_size; + unsigned mw_bar[NTB_MAX_BARS]; +}; + +struct ntb_alt_reg { + uint32_t db_bell; + uint32_t db_mask; + uint32_t spad; +}; + +struct ntb_xlat_reg { + uint32_t bar0_base; + uint32_t bar2_base; + uint32_t bar4_base; + uint32_t bar5_base; + + uint32_t bar2_xlat; + uint32_t bar4_xlat; + uint32_t bar5_xlat; + + uint32_t bar2_limit; + uint32_t bar4_limit; + uint32_t bar5_limit; +}; + +struct ntb_b2b_addr { + uint64_t bar0_addr; + uint64_t bar2_addr64; + uint64_t bar4_addr64; + uint64_t bar4_addr32; + uint64_t bar5_addr32; +}; + struct ntb_softc { device_t device; enum ntb_device_type type; - uint64_t features; + uint32_t features; struct ntb_pci_bar_info bar_info[NTB_MAX_BARS]; struct ntb_int_info int_info[MAX_MSIX_INTERRUPTS]; uint32_t allocated_interrupts; struct callout heartbeat_timer; struct callout lr_timer; - void *ntb_transport; - ntb_event_callback event_cb; - struct ntb_db_cb *db_cb; + void *ntb_ctx; + const struct ntb_ctx_ops *ctx_ops; + struct ntb_vec *msix_vec; +#define CTX_LOCK(sc) mtx_lock(&(sc)->ctx_lock) +#define CTX_UNLOCK(sc) mtx_unlock(&(sc)->ctx_lock) +#define CTX_ASSERT(sc,f) mtx_assert(&(sc)->ctx_lock, (f)) + struct mtx ctx_lock; - struct { - uint32_t max_spads; - uint32_t max_db_bits; - uint32_t msix_cnt; - } limits; - struct { - uint32_t pdb; - uint32_t pdb_mask; - uint32_t sdb; - uint32_t sbar2_xlat; - uint32_t sbar4_xlat; - uint32_t spad_remote; - uint32_t spad_local; - uint32_t lnk_cntl; - uint32_t lnk_stat; - uint32_t spci_cmd; - } reg_ofs; - uint8_t conn_type; - uint8_t dev_type; - uint8_t bits_per_vector; - uint8_t link_status; - uint8_t link_width; - uint8_t link_speed; + uint32_t ppd; + enum ntb_conn_type conn_type; + enum ntb_b2b_direction dev_type; + + /* Offset of peer bar0 in B2B BAR */ + uint64_t b2b_off; + /* Memory window used to access peer bar0 */ +#define B2B_MW_DISABLED UINT8_MAX + uint8_t b2b_mw_idx; + + uint8_t mw_count; + uint8_t spad_count; + uint8_t db_count; + uint8_t db_vec_count; + uint8_t db_vec_shift; + + /* Protects local db_mask. */ +#define DB_MASK_LOCK(sc) mtx_lock_spin(&(sc)->db_mask_lock) +#define DB_MASK_UNLOCK(sc) mtx_unlock_spin(&(sc)->db_mask_lock) +#define DB_MASK_ASSERT(sc,f) mtx_assert(&(sc)->db_mask_lock, (f)) + struct mtx db_mask_lock; + + volatile uint32_t ntb_ctl; + volatile uint32_t lnk_sta; + + uint64_t db_valid_mask; + uint64_t db_link_mask; + uint64_t db_mask; + + int last_ts; /* ticks @ last irq */ + + const struct ntb_reg *reg; + const struct ntb_alt_reg *self_reg; + const struct ntb_alt_reg *peer_reg; + const struct ntb_xlat_reg *xlat_reg; }; +#ifdef __i386__ +static __inline uint64_t +bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, + bus_size_t offset) +{ + + return (bus_space_read_4(tag, handle, offset) | + ((uint64_t)bus_space_read_4(tag, handle, offset + 4)) << 32); +} + +static __inline void +bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t handle, + bus_size_t offset, uint64_t val) +{ + + bus_space_write_4(tag, handle, offset, val); + bus_space_write_4(tag, handle, offset + 4, val >> 32); +} +#endif + #define ntb_bar_read(SIZE, bar, offset) \ bus_space_read_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ ntb->bar_info[(bar)].pci_bus_handle, (offset)) #define ntb_bar_write(SIZE, bar, offset, val) \ bus_space_write_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ ntb->bar_info[(bar)].pci_bus_handle, (offset), (val)) #define ntb_reg_read(SIZE, offset) ntb_bar_read(SIZE, NTB_CONFIG_BAR, offset) #define ntb_reg_write(SIZE, offset, val) \ ntb_bar_write(SIZE, NTB_CONFIG_BAR, offset, val) -#define ntb_mw_read(SIZE, offset) ntb_bar_read(SIZE, NTB_B2B_BAR_2, offset) +#define ntb_mw_read(SIZE, offset) \ + ntb_bar_read(SIZE, ntb_mw_to_bar(ntb, ntb->b2b_mw_idx), offset) #define ntb_mw_write(SIZE, offset, val) \ - ntb_bar_write(SIZE, NTB_B2B_BAR_2, offset, val) + ntb_bar_write(SIZE, ntb_mw_to_bar(ntb, ntb->b2b_mw_idx), \ + offset, val) -typedef int (*bar_map_strategy)(struct ntb_softc *ntb, - struct ntb_pci_bar_info *bar); - static int ntb_probe(device_t device); static int ntb_attach(device_t device); static int ntb_detach(device_t device); +static unsigned ntb_user_mw_to_idx(struct ntb_softc *, unsigned uidx); +static inline enum ntb_bar ntb_mw_to_bar(struct ntb_softc *, unsigned mw); +static inline bool bar_is_64bit(struct ntb_softc *, enum ntb_bar); +static inline void bar_get_xlat_params(struct ntb_softc *, enum ntb_bar, + uint32_t *base, uint32_t *xlat, uint32_t *lmt); static int ntb_map_pci_bars(struct ntb_softc *ntb); -static int map_pci_bar(struct ntb_softc *ntb, bar_map_strategy strategy, - struct ntb_pci_bar_info *bar); +static int ntb_mw_set_wc_internal(struct ntb_softc *, unsigned idx, + vm_memattr_t); +static void print_map_success(struct ntb_softc *, struct ntb_pci_bar_info *, + const char *); static int map_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar); static int map_memory_window_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar); static void ntb_unmap_pci_bar(struct ntb_softc *ntb); -static int ntb_setup_interrupts(struct ntb_softc *ntb); +static int ntb_remap_msix(device_t, uint32_t desired, uint32_t avail); +static int ntb_init_isr(struct ntb_softc *ntb); +static int ntb_setup_legacy_interrupt(struct ntb_softc *ntb); +static int ntb_setup_msix(struct ntb_softc *ntb, uint32_t num_vectors); static void ntb_teardown_interrupts(struct ntb_softc *ntb); -static void handle_soc_irq(void *arg); -static void handle_xeon_irq(void *arg); -static void handle_xeon_event_irq(void *arg); -static void ntb_handle_legacy_interrupt(void *arg); -static int ntb_create_callbacks(struct ntb_softc *ntb, int num_vectors); -static void ntb_free_callbacks(struct ntb_softc *ntb); +static inline uint64_t ntb_vec_mask(struct ntb_softc *, uint64_t db_vector); +static void ntb_interrupt(struct ntb_softc *, uint32_t vec); +static void ndev_vec_isr(void *arg); +static void ndev_irq_isr(void *arg); +static inline uint64_t db_ioread(struct ntb_softc *, uint64_t regoff); +static inline void db_iowrite(struct ntb_softc *, uint64_t regoff, uint64_t); +static inline void db_iowrite_raw(struct ntb_softc *, uint64_t regoff, uint64_t); +static int ntb_create_msix_vec(struct ntb_softc *ntb, uint32_t num_vectors); +static void ntb_free_msix_vec(struct ntb_softc *ntb); static struct ntb_hw_info *ntb_get_device_info(uint32_t device_id); -static int ntb_initialize_hw(struct ntb_softc *ntb); -static int ntb_setup_xeon(struct ntb_softc *ntb); -static int ntb_setup_soc(struct ntb_softc *ntb); -static void configure_soc_secondary_side_bars(struct ntb_softc *ntb); -static void configure_xeon_secondary_side_bars(struct ntb_softc *ntb); -static void ntb_handle_heartbeat(void *arg); -static void ntb_handle_link_event(struct ntb_softc *ntb, int link_state); -static void recover_soc_link(void *arg); -static int ntb_check_link_status(struct ntb_softc *ntb); +static void ntb_detect_max_mw(struct ntb_softc *ntb); +static int ntb_detect_xeon(struct ntb_softc *ntb); +static int ntb_detect_atom(struct ntb_softc *ntb); +static int ntb_xeon_init_dev(struct ntb_softc *ntb); +static int ntb_atom_init_dev(struct ntb_softc *ntb); +static void ntb_teardown_xeon(struct ntb_softc *ntb); +static void configure_atom_secondary_side_bars(struct ntb_softc *ntb); +static void xeon_reset_sbar_size(struct ntb_softc *, enum ntb_bar idx, + enum ntb_bar regbar); +static void xeon_set_sbar_base_and_limit(struct ntb_softc *, + uint64_t base_addr, enum ntb_bar idx, enum ntb_bar regbar); +static void xeon_set_pbar_xlat(struct ntb_softc *, uint64_t base_addr, + enum ntb_bar idx); +static int xeon_setup_b2b_mw(struct ntb_softc *, + const struct ntb_b2b_addr *addr, const struct ntb_b2b_addr *peer_addr); +static inline bool link_is_up(struct ntb_softc *ntb); +static inline bool atom_link_is_err(struct ntb_softc *ntb); +static inline enum ntb_speed ntb_link_sta_speed(struct ntb_softc *); +static inline enum ntb_width ntb_link_sta_width(struct ntb_softc *); +static void atom_link_hb(void *arg); +static void ntb_db_event(struct ntb_softc *ntb, uint32_t vec); +static void recover_atom_link(void *arg); +static bool ntb_poll_link(struct ntb_softc *ntb); static void save_bar_parameters(struct ntb_pci_bar_info *bar); +static void ntb_sysctl_init(struct ntb_softc *); +static int sysctl_handle_features(SYSCTL_HANDLER_ARGS); +static int sysctl_handle_link_status(SYSCTL_HANDLER_ARGS); +static int sysctl_handle_register(SYSCTL_HANDLER_ARGS); +static unsigned g_ntb_hw_debug_level; +SYSCTL_UINT(_hw_ntb, OID_AUTO, debug_level, CTLFLAG_RWTUN, + &g_ntb_hw_debug_level, 0, "ntb_hw log level -- higher is more verbose"); +#define ntb_printf(lvl, ...) do { \ + if ((lvl) <= g_ntb_hw_debug_level) { \ + device_printf(ntb->device, __VA_ARGS__); \ + } \ +} while (0) + +#define _NTB_PAT_UC 0 +#define _NTB_PAT_WC 1 +#define _NTB_PAT_WT 4 +#define _NTB_PAT_WP 5 +#define _NTB_PAT_WB 6 +#define _NTB_PAT_UCM 7 +static unsigned g_ntb_mw_pat = _NTB_PAT_UC; +SYSCTL_UINT(_hw_ntb, OID_AUTO, default_mw_pat, CTLFLAG_RDTUN, + &g_ntb_mw_pat, 0, "Configure the default memory window cache flags (PAT): " + "UC: " __XSTRING(_NTB_PAT_UC) ", " + "WC: " __XSTRING(_NTB_PAT_WC) ", " + "WT: " __XSTRING(_NTB_PAT_WT) ", " + "WP: " __XSTRING(_NTB_PAT_WP) ", " + "WB: " __XSTRING(_NTB_PAT_WB) ", " + "UC-: " __XSTRING(_NTB_PAT_UCM)); + +static inline vm_memattr_t +ntb_pat_flags(void) +{ + + switch (g_ntb_mw_pat) { + case _NTB_PAT_WC: + return (VM_MEMATTR_WRITE_COMBINING); + case _NTB_PAT_WT: + return (VM_MEMATTR_WRITE_THROUGH); + case _NTB_PAT_WP: + return (VM_MEMATTR_WRITE_PROTECTED); + case _NTB_PAT_WB: + return (VM_MEMATTR_WRITE_BACK); + case _NTB_PAT_UCM: + return (VM_MEMATTR_WEAK_UNCACHEABLE); + case _NTB_PAT_UC: + /* FALLTHROUGH */ + default: + return (VM_MEMATTR_UNCACHEABLE); + } +} + +/* + * Well, this obviously doesn't belong here, but it doesn't seem to exist + * anywhere better yet. + */ +static inline const char * +ntb_vm_memattr_to_str(vm_memattr_t pat) +{ + + switch (pat) { + case VM_MEMATTR_WRITE_COMBINING: + return ("WRITE_COMBINING"); + case VM_MEMATTR_WRITE_THROUGH: + return ("WRITE_THROUGH"); + case VM_MEMATTR_WRITE_PROTECTED: + return ("WRITE_PROTECTED"); + case VM_MEMATTR_WRITE_BACK: + return ("WRITE_BACK"); + case VM_MEMATTR_WEAK_UNCACHEABLE: + return ("UNCACHED"); + case VM_MEMATTR_UNCACHEABLE: + return ("UNCACHEABLE"); + default: + return ("UNKNOWN"); + } +} + +static int g_ntb_mw_idx = -1; +SYSCTL_INT(_hw_ntb, OID_AUTO, b2b_mw_idx, CTLFLAG_RDTUN, &g_ntb_mw_idx, + 0, "Use this memory window to access the peer NTB registers. A " + "non-negative value starts from the first MW index; a negative value " + "starts from the last MW index. The default is -1, i.e., the last " + "available memory window. Both sides of the NTB MUST set the same " + "value here! (Applies on Xeon platforms with SDOORBELL_LOCKUP errata.)"); + static struct ntb_hw_info pci_ids[] = { - { 0x3C0D8086, "Xeon E5/Core i7 Non-Transparent Bridge B2B", NTB_XEON, - NTB_REGS_THRU_MW }, - { 0x0C4E8086, "Atom Processor S1200 NTB Primary B2B", NTB_SOC, 0 }, - { 0x0E0D8086, "Xeon E5 V2 Non-Transparent Bridge B2B", NTB_XEON, - NTB_REGS_THRU_MW | NTB_BAR_SIZE_4K }, - { 0x00000000, NULL, NTB_SOC, 0 } + /* XXX: PS/SS IDs left out until they are supported. */ + { 0x0C4E8086, "BWD Atom Processor S1200 Non-Transparent Bridge B2B", + NTB_ATOM, 0 }, + + { 0x37258086, "JSF Xeon C35xx/C55xx Non-Transparent Bridge B2B", + NTB_XEON, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 }, + { 0x3C0D8086, "SNB Xeon E5/Core i7 Non-Transparent Bridge B2B", + NTB_XEON, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 }, + { 0x0E0D8086, "IVT Xeon E5 V2 Non-Transparent Bridge B2B", NTB_XEON, + NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | + NTB_SB01BASE_LOCKUP | NTB_BAR_SIZE_4K }, + { 0x2F0D8086, "HSX Xeon E5 V3 Non-Transparent Bridge B2B", NTB_XEON, + NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | + NTB_SB01BASE_LOCKUP }, + { 0x6F0D8086, "BDX Xeon E5 V4 Non-Transparent Bridge B2B", NTB_XEON, + NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | + NTB_SB01BASE_LOCKUP }, + + { 0x00000000, NULL, NTB_ATOM, 0 } }; +static const struct ntb_reg atom_reg = { + .ntb_ctl = ATOM_NTBCNTL_OFFSET, + .lnk_sta = ATOM_LINK_STATUS_OFFSET, + .db_size = sizeof(uint64_t), + .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2 }, +}; + +static const struct ntb_alt_reg atom_pri_reg = { + .db_bell = ATOM_PDOORBELL_OFFSET, + .db_mask = ATOM_PDBMSK_OFFSET, + .spad = ATOM_SPAD_OFFSET, +}; + +static const struct ntb_alt_reg atom_b2b_reg = { + .db_bell = ATOM_B2B_DOORBELL_OFFSET, + .spad = ATOM_B2B_SPAD_OFFSET, +}; + +static const struct ntb_xlat_reg atom_sec_xlat = { +#if 0 + /* "FIXME" says the Linux driver. */ + .bar0_base = ATOM_SBAR0BASE_OFFSET, + .bar2_base = ATOM_SBAR2BASE_OFFSET, + .bar4_base = ATOM_SBAR4BASE_OFFSET, + + .bar2_limit = ATOM_SBAR2LMT_OFFSET, + .bar4_limit = ATOM_SBAR4LMT_OFFSET, +#endif + + .bar2_xlat = ATOM_SBAR2XLAT_OFFSET, + .bar4_xlat = ATOM_SBAR4XLAT_OFFSET, +}; + +static const struct ntb_reg xeon_reg = { + .ntb_ctl = XEON_NTBCNTL_OFFSET, + .lnk_sta = XEON_LINK_STATUS_OFFSET, + .db_size = sizeof(uint16_t), + .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2, NTB_B2B_BAR_3 }, +}; + +static const struct ntb_alt_reg xeon_pri_reg = { + .db_bell = XEON_PDOORBELL_OFFSET, + .db_mask = XEON_PDBMSK_OFFSET, + .spad = XEON_SPAD_OFFSET, +}; + +static const struct ntb_alt_reg xeon_b2b_reg = { + .db_bell = XEON_B2B_DOORBELL_OFFSET, + .spad = XEON_B2B_SPAD_OFFSET, +}; + +static const struct ntb_xlat_reg xeon_sec_xlat = { + .bar0_base = XEON_SBAR0BASE_OFFSET, + .bar2_base = XEON_SBAR2BASE_OFFSET, + .bar4_base = XEON_SBAR4BASE_OFFSET, + .bar5_base = XEON_SBAR5BASE_OFFSET, + + .bar2_limit = XEON_SBAR2LMT_OFFSET, + .bar4_limit = XEON_SBAR4LMT_OFFSET, + .bar5_limit = XEON_SBAR5LMT_OFFSET, + + .bar2_xlat = XEON_SBAR2XLAT_OFFSET, + .bar4_xlat = XEON_SBAR4XLAT_OFFSET, + .bar5_xlat = XEON_SBAR5XLAT_OFFSET, +}; + +static struct ntb_b2b_addr xeon_b2b_usd_addr = { + .bar0_addr = XEON_B2B_BAR0_ADDR, + .bar2_addr64 = XEON_B2B_BAR2_ADDR64, + .bar4_addr64 = XEON_B2B_BAR4_ADDR64, + .bar4_addr32 = XEON_B2B_BAR4_ADDR32, + .bar5_addr32 = XEON_B2B_BAR5_ADDR32, +}; + +static struct ntb_b2b_addr xeon_b2b_dsd_addr = { + .bar0_addr = XEON_B2B_BAR0_ADDR, + .bar2_addr64 = XEON_B2B_BAR2_ADDR64, + .bar4_addr64 = XEON_B2B_BAR4_ADDR64, + .bar4_addr32 = XEON_B2B_BAR4_ADDR32, + .bar5_addr32 = XEON_B2B_BAR5_ADDR32, +}; + +SYSCTL_NODE(_hw_ntb, OID_AUTO, xeon_b2b, CTLFLAG_RW, 0, + "B2B MW segment overrides -- MUST be the same on both sides"); + +SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar2_addr64, CTLFLAG_RDTUN, + &xeon_b2b_usd_addr.bar2_addr64, 0, "If using B2B topology on Xeon " + "hardware, use this 64-bit address on the bus between the NTB devices for " + "the window at BAR2, on the upstream side of the link. MUST be the same " + "address on both sides."); +SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar4_addr64, CTLFLAG_RDTUN, + &xeon_b2b_usd_addr.bar4_addr64, 0, "See usd_bar2_addr64, but BAR4."); +SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar4_addr32, CTLFLAG_RDTUN, + &xeon_b2b_usd_addr.bar4_addr32, 0, "See usd_bar2_addr64, but BAR4 " + "(split-BAR mode)."); +SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar5_addr32, CTLFLAG_RDTUN, + &xeon_b2b_usd_addr.bar5_addr32, 0, "See usd_bar2_addr64, but BAR5 " + "(split-BAR mode)."); + +SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar2_addr64, CTLFLAG_RDTUN, + &xeon_b2b_dsd_addr.bar2_addr64, 0, "If using B2B topology on Xeon " + "hardware, use this 64-bit address on the bus between the NTB devices for " + "the window at BAR2, on the downstream side of the link. MUST be the same" + " address on both sides."); +SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar4_addr64, CTLFLAG_RDTUN, + &xeon_b2b_dsd_addr.bar4_addr64, 0, "See dsd_bar2_addr64, but BAR4."); +SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar4_addr32, CTLFLAG_RDTUN, + &xeon_b2b_dsd_addr.bar4_addr32, 0, "See dsd_bar2_addr64, but BAR4 " + "(split-BAR mode)."); +SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar5_addr32, CTLFLAG_RDTUN, + &xeon_b2b_dsd_addr.bar5_addr32, 0, "See dsd_bar2_addr64, but BAR5 " + "(split-BAR mode)."); + /* * OS <-> Driver interface structures */ MALLOC_DEFINE(M_NTB, "ntb_hw", "ntb_hw driver memory allocations"); static device_method_t ntb_pci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ntb_probe), DEVMETHOD(device_attach, ntb_attach), DEVMETHOD(device_detach, ntb_detach), DEVMETHOD_END }; static driver_t ntb_pci_driver = { "ntb_hw", ntb_pci_methods, sizeof(struct ntb_softc), }; static devclass_t ntb_devclass; DRIVER_MODULE(ntb_hw, pci, ntb_pci_driver, ntb_devclass, NULL, NULL); MODULE_VERSION(ntb_hw, 1); +SYSCTL_NODE(_hw, OID_AUTO, ntb, CTLFLAG_RW, 0, "NTB sysctls"); + /* * OS <-> Driver linkage functions */ static int ntb_probe(device_t device) { - struct ntb_hw_info *p = ntb_get_device_info(pci_get_devid(device)); + struct ntb_hw_info *p; - if (p != NULL) { - device_set_desc(device, p->desc); - return (0); - } else + p = ntb_get_device_info(pci_get_devid(device)); + if (p == NULL) return (ENXIO); + + device_set_desc(device, p->desc); + return (0); } -#define DETACH_ON_ERROR(func) \ - error = func; \ - if (error < 0) { \ - ntb_detach(device); \ - return (error); \ - } - static int ntb_attach(device_t device) { - struct ntb_softc *ntb = DEVICE2SOFTC(device); - struct ntb_hw_info *p = ntb_get_device_info(pci_get_devid(device)); + struct ntb_softc *ntb; + struct ntb_hw_info *p; int error; + ntb = DEVICE2SOFTC(device); + p = ntb_get_device_info(pci_get_devid(device)); + ntb->device = device; ntb->type = p->type; ntb->features = p->features; + ntb->b2b_mw_idx = B2B_MW_DISABLED; - /* Heartbeat timer for NTB_SOC since there is no link interrupt */ + /* Heartbeat timer for NTB_ATOM since there is no link interrupt */ callout_init(&ntb->heartbeat_timer, CALLOUT_MPSAFE); callout_init(&ntb->lr_timer, CALLOUT_MPSAFE); + mtx_init(&ntb->db_mask_lock, "ntb hw bits", NULL, MTX_SPIN); + mtx_init(&ntb->ctx_lock, "ntb ctx", NULL, MTX_DEF); - DETACH_ON_ERROR(ntb_map_pci_bars(ntb)); - DETACH_ON_ERROR(ntb_initialize_hw(ntb)); - DETACH_ON_ERROR(ntb_setup_interrupts(ntb)); + if (ntb->type == NTB_ATOM) + error = ntb_detect_atom(ntb); + else + error = ntb_detect_xeon(ntb); + if (error != 0) + goto out; + ntb_detect_max_mw(ntb); + pci_enable_busmaster(ntb->device); + error = ntb_map_pci_bars(ntb); + if (error != 0) + goto out; + if (ntb->type == NTB_ATOM) + error = ntb_atom_init_dev(ntb); + else + error = ntb_xeon_init_dev(ntb); + if (error != 0) + goto out; + + ntb_poll_link(ntb); + + ntb_sysctl_init(ntb); + +out: + if (error != 0) + ntb_detach(device); return (error); } static int ntb_detach(device_t device) { - struct ntb_softc *ntb = DEVICE2SOFTC(device); + struct ntb_softc *ntb; + ntb = DEVICE2SOFTC(device); + + if (ntb->self_reg != NULL) + ntb_db_set_mask(ntb, ntb->db_valid_mask); callout_drain(&ntb->heartbeat_timer); callout_drain(&ntb->lr_timer); + pci_disable_busmaster(ntb->device); + if (ntb->type == NTB_XEON) + ntb_teardown_xeon(ntb); ntb_teardown_interrupts(ntb); + + mtx_destroy(&ntb->db_mask_lock); + mtx_destroy(&ntb->ctx_lock); + ntb_unmap_pci_bar(ntb); return (0); } +/* + * Driver internal routines + */ +static inline enum ntb_bar +ntb_mw_to_bar(struct ntb_softc *ntb, unsigned mw) +{ + + KASSERT(mw < ntb->mw_count, + ("%s: mw:%u > count:%u", __func__, mw, (unsigned)ntb->mw_count)); + KASSERT(ntb->reg->mw_bar[mw] != 0, ("invalid mw")); + + return (ntb->reg->mw_bar[mw]); +} + +static inline bool +bar_is_64bit(struct ntb_softc *ntb, enum ntb_bar bar) +{ + /* XXX This assertion could be stronger. */ + KASSERT(bar < NTB_MAX_BARS, ("bogus bar")); + return (bar < NTB_B2B_BAR_2 || !HAS_FEATURE(NTB_SPLIT_BAR)); +} + +static inline void +bar_get_xlat_params(struct ntb_softc *ntb, enum ntb_bar bar, uint32_t *base, + uint32_t *xlat, uint32_t *lmt) +{ + uint32_t basev, lmtv, xlatv; + + switch (bar) { + case NTB_B2B_BAR_1: + basev = ntb->xlat_reg->bar2_base; + lmtv = ntb->xlat_reg->bar2_limit; + xlatv = ntb->xlat_reg->bar2_xlat; + break; + case NTB_B2B_BAR_2: + basev = ntb->xlat_reg->bar4_base; + lmtv = ntb->xlat_reg->bar4_limit; + xlatv = ntb->xlat_reg->bar4_xlat; + break; + case NTB_B2B_BAR_3: + basev = ntb->xlat_reg->bar5_base; + lmtv = ntb->xlat_reg->bar5_limit; + xlatv = ntb->xlat_reg->bar5_xlat; + break; + default: + KASSERT(bar >= NTB_B2B_BAR_1 && bar < NTB_MAX_BARS, + ("bad bar")); + basev = lmtv = xlatv = 0; + break; + } + + if (base != NULL) + *base = basev; + if (xlat != NULL) + *xlat = xlatv; + if (lmt != NULL) + *lmt = lmtv; +} + static int ntb_map_pci_bars(struct ntb_softc *ntb) { int rc; ntb->bar_info[NTB_CONFIG_BAR].pci_resource_id = PCIR_BAR(0); - rc = map_pci_bar(ntb, map_mmr_bar, &ntb->bar_info[NTB_CONFIG_BAR]); + rc = map_mmr_bar(ntb, &ntb->bar_info[NTB_CONFIG_BAR]); if (rc != 0) - return rc; + goto out; - ntb->bar_info[NTB_B2B_BAR_1].pci_resource_id = PCIR_BAR(2); - rc = map_pci_bar(ntb, map_memory_window_bar, - &ntb->bar_info[NTB_B2B_BAR_1]); + ntb->bar_info[NTB_B2B_BAR_1].pci_resource_id = PCIR_BAR(2); + rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_1]); if (rc != 0) - return rc; + goto out; + ntb->bar_info[NTB_B2B_BAR_1].psz_off = XEON_PBAR23SZ_OFFSET; + ntb->bar_info[NTB_B2B_BAR_1].ssz_off = XEON_SBAR23SZ_OFFSET; + ntb->bar_info[NTB_B2B_BAR_1].pbarxlat_off = XEON_PBAR2XLAT_OFFSET; - ntb->bar_info[NTB_B2B_BAR_2].pci_resource_id = PCIR_BAR(4); - if (HAS_FEATURE(NTB_REGS_THRU_MW)) - rc = map_pci_bar(ntb, map_mmr_bar, - &ntb->bar_info[NTB_B2B_BAR_2]); - else - rc = map_pci_bar(ntb, map_memory_window_bar, - &ntb->bar_info[NTB_B2B_BAR_2]); + ntb->bar_info[NTB_B2B_BAR_2].pci_resource_id = PCIR_BAR(4); + rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_2]); if (rc != 0) - return rc; + goto out; + ntb->bar_info[NTB_B2B_BAR_2].psz_off = XEON_PBAR4SZ_OFFSET; + ntb->bar_info[NTB_B2B_BAR_2].ssz_off = XEON_SBAR4SZ_OFFSET; + ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off = XEON_PBAR4XLAT_OFFSET; - return (0); -} + if (!HAS_FEATURE(NTB_SPLIT_BAR)) + goto out; -static int -map_pci_bar(struct ntb_softc *ntb, bar_map_strategy strategy, - struct ntb_pci_bar_info *bar) -{ - int rc; + ntb->bar_info[NTB_B2B_BAR_3].pci_resource_id = PCIR_BAR(5); + rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_3]); + ntb->bar_info[NTB_B2B_BAR_3].psz_off = XEON_PBAR5SZ_OFFSET; + ntb->bar_info[NTB_B2B_BAR_3].ssz_off = XEON_SBAR5SZ_OFFSET; + ntb->bar_info[NTB_B2B_BAR_3].pbarxlat_off = XEON_PBAR5XLAT_OFFSET; - rc = strategy(ntb, bar); - if (rc != 0) { +out: + if (rc != 0) device_printf(ntb->device, "unable to allocate pci resource\n"); - } else { - device_printf(ntb->device, - "Bar size = %lx, v %p, p %p\n", - bar->size, bar->vbase, - (void *)(bar->pbase)); - } return (rc); } +static void +print_map_success(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar, + const char *kind) +{ + + device_printf(ntb->device, + "Mapped BAR%d v:[%p-%p] p:[%p-%p] (0x%jx bytes) (%s)\n", + PCI_RID2BAR(bar->pci_resource_id), bar->vbase, + (char *)bar->vbase + bar->size - 1, + (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), + (uintmax_t)bar->size, kind); +} + static int map_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) { bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY, - &bar->pci_resource_id, RF_ACTIVE); - + &bar->pci_resource_id, RF_ACTIVE); if (bar->pci_resource == NULL) return (ENXIO); - else { - save_bar_parameters(bar); - return (0); - } + + save_bar_parameters(bar); + bar->map_mode = VM_MEMATTR_UNCACHEABLE; + print_map_success(ntb, bar, "mmr"); + return (0); } static int map_memory_window_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) { int rc; + vm_memattr_t mapmode; uint8_t bar_size_bits = 0; - bar->pci_resource = bus_alloc_resource_any(ntb->device, - SYS_RES_MEMORY, &bar->pci_resource_id, RF_ACTIVE); + bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY, + &bar->pci_resource_id, RF_ACTIVE); if (bar->pci_resource == NULL) return (ENXIO); - else { - save_bar_parameters(bar); - /* - * Ivytown NTB BAR sizes are misreported by the hardware due to - * a hardware issue. To work around this, query the size it - * should be configured to by the device and modify the resource - * to correspond to this new size. The BIOS on systems with this - * problem is required to provide enough address space to allow - * the driver to make this change safely. - * - * Ideally I could have just specified the size when I allocated - * the resource like: - * bus_alloc_resource(ntb->device, - * SYS_RES_MEMORY, &bar->pci_resource_id, 0ul, ~0ul, - * 1ul << bar_size_bits, RF_ACTIVE); - * but the PCI driver does not honor the size in this call, so - * we have to modify it after the fact. - */ - if (HAS_FEATURE(NTB_BAR_SIZE_4K)) { - if (bar->pci_resource_id == PCIR_BAR(2)) - bar_size_bits = pci_read_config(ntb->device, - XEON_PBAR23SZ_OFFSET, 1); - else - bar_size_bits = pci_read_config(ntb->device, - XEON_PBAR45SZ_OFFSET, 1); - rc = bus_adjust_resource(ntb->device, SYS_RES_MEMORY, - bar->pci_resource, bar->pbase, - bar->pbase + (1ul << bar_size_bits) - 1); - if (rc != 0 ) { - device_printf(ntb->device, - "unable to resize bar\n"); - return (rc); - } else - save_bar_parameters(bar); - } - /* Mark bar region as write combining to improve performance. */ - rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, - VM_MEMATTR_WRITE_COMBINING); + save_bar_parameters(bar); + /* + * Ivytown NTB BAR sizes are misreported by the hardware due to a + * hardware issue. To work around this, query the size it should be + * configured to by the device and modify the resource to correspond to + * this new size. The BIOS on systems with this problem is required to + * provide enough address space to allow the driver to make this change + * safely. + * + * Ideally I could have just specified the size when I allocated the + * resource like: + * bus_alloc_resource(ntb->device, + * SYS_RES_MEMORY, &bar->pci_resource_id, 0ul, ~0ul, + * 1ul << bar_size_bits, RF_ACTIVE); + * but the PCI driver does not honor the size in this call, so we have + * to modify it after the fact. + */ + if (HAS_FEATURE(NTB_BAR_SIZE_4K)) { + if (bar->pci_resource_id == PCIR_BAR(2)) + bar_size_bits = pci_read_config(ntb->device, + XEON_PBAR23SZ_OFFSET, 1); + else + bar_size_bits = pci_read_config(ntb->device, + XEON_PBAR45SZ_OFFSET, 1); + + rc = bus_adjust_resource(ntb->device, SYS_RES_MEMORY, + bar->pci_resource, bar->pbase, + bar->pbase + (1ul << bar_size_bits) - 1); if (rc != 0) { - device_printf(ntb->device, "unable to mark bar as" - " WRITE_COMBINING\n"); + device_printf(ntb->device, + "unable to resize bar\n"); return (rc); } + + save_bar_parameters(bar); } + + bar->map_mode = VM_MEMATTR_UNCACHEABLE; + print_map_success(ntb, bar, "mw"); + + /* + * Optionally, mark MW BARs as anything other than UC to improve + * performance. + */ + mapmode = ntb_pat_flags(); + if (mapmode == bar->map_mode) + return (0); + + rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, mapmode); + if (rc == 0) { + bar->map_mode = mapmode; + device_printf(ntb->device, + "Marked BAR%d v:[%p-%p] p:[%p-%p] as " + "%s.\n", + PCI_RID2BAR(bar->pci_resource_id), bar->vbase, + (char *)bar->vbase + bar->size - 1, + (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), + ntb_vm_memattr_to_str(mapmode)); + } else + device_printf(ntb->device, + "Unable to mark BAR%d v:[%p-%p] p:[%p-%p] as " + "%s: %d\n", + PCI_RID2BAR(bar->pci_resource_id), bar->vbase, + (char *)bar->vbase + bar->size - 1, + (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), + ntb_vm_memattr_to_str(mapmode), rc); + /* Proceed anyway */ return (0); } static void ntb_unmap_pci_bar(struct ntb_softc *ntb) { struct ntb_pci_bar_info *current_bar; int i; - for (i = 0; i< NTB_MAX_BARS; i++) { + for (i = 0; i < NTB_MAX_BARS; i++) { current_bar = &ntb->bar_info[i]; if (current_bar->pci_resource != NULL) bus_release_resource(ntb->device, SYS_RES_MEMORY, current_bar->pci_resource_id, current_bar->pci_resource); } } static int -ntb_setup_interrupts(struct ntb_softc *ntb) +ntb_setup_msix(struct ntb_softc *ntb, uint32_t num_vectors) { - void (*interrupt_handler)(void *); - void *int_arg; - bool use_msix = 0; - uint32_t num_vectors; - int i; + uint32_t i; + int rc; + for (i = 0; i < num_vectors; i++) { + ntb->int_info[i].rid = i + 1; + ntb->int_info[i].res = bus_alloc_resource_any(ntb->device, + SYS_RES_IRQ, &ntb->int_info[i].rid, RF_ACTIVE); + if (ntb->int_info[i].res == NULL) { + device_printf(ntb->device, + "bus_alloc_resource failed\n"); + return (ENOMEM); + } + ntb->int_info[i].tag = NULL; + ntb->allocated_interrupts++; + rc = bus_setup_intr(ntb->device, ntb->int_info[i].res, + INTR_MPSAFE | INTR_TYPE_MISC, NULL, ndev_vec_isr, + &ntb->msix_vec[i], &ntb->int_info[i].tag); + if (rc != 0) { + device_printf(ntb->device, "bus_setup_intr failed\n"); + return (ENXIO); + } + } + return (0); +} + +/* + * The Linux NTB driver drops from MSI-X to legacy INTx if a unique vector + * cannot be allocated for each MSI-X message. JHB seems to think remapping + * should be okay. This tunable should enable us to test that hypothesis + * when someone gets their hands on some Xeon hardware. + */ +static int ntb_force_remap_mode; +SYSCTL_INT(_hw_ntb, OID_AUTO, force_remap_mode, CTLFLAG_RDTUN, + &ntb_force_remap_mode, 0, "If enabled, force MSI-X messages to be remapped" + " to a smaller number of ithreads, even if the desired number are " + "available"); + +/* + * In case it is NOT ok, give consumers an abort button. + */ +static int ntb_prefer_intx; +SYSCTL_INT(_hw_ntb, OID_AUTO, prefer_intx_to_remap, CTLFLAG_RDTUN, + &ntb_prefer_intx, 0, "If enabled, prefer to use legacy INTx mode rather " + "than remapping MSI-X messages over available slots (match Linux driver " + "behavior)"); + +/* + * Remap the desired number of MSI-X messages to available ithreads in a simple + * round-robin fashion. + */ +static int +ntb_remap_msix(device_t dev, uint32_t desired, uint32_t avail) +{ + u_int *vectors; + uint32_t i; + int rc; + + if (ntb_prefer_intx != 0) + return (ENXIO); + + vectors = malloc(desired * sizeof(*vectors), M_NTB, M_ZERO | M_WAITOK); + + for (i = 0; i < desired; i++) + vectors[i] = (i % avail) + 1; + + rc = pci_remap_msix(dev, desired, vectors); + free(vectors, M_NTB); + return (rc); +} + +static int +ntb_init_isr(struct ntb_softc *ntb) +{ + uint32_t desired_vectors, num_vectors; + int rc; + ntb->allocated_interrupts = 0; + ntb->last_ts = ticks; + /* - * On SOC, disable all interrupts. On XEON, disable all but Link - * Interrupt. The rest will be unmasked as callbacks are registered. + * Mask all doorbell interrupts. */ - if (ntb->type == NTB_SOC) - ntb_reg_write(8, ntb->reg_ofs.pdb_mask, ~0); - else - ntb_reg_write(2, ntb->reg_ofs.pdb_mask, - ~(1 << ntb->limits.max_db_bits)); + ntb_db_set_mask(ntb, ntb->db_valid_mask); - num_vectors = MIN(pci_msix_count(ntb->device), - ntb->limits.max_db_bits); - if (num_vectors >= 1) { - pci_alloc_msix(ntb->device, &num_vectors); - if (num_vectors >= 4) - use_msix = TRUE; - } + num_vectors = desired_vectors = MIN(pci_msix_count(ntb->device), + ntb->db_count); + if (desired_vectors >= 1) { + rc = pci_alloc_msix(ntb->device, &num_vectors); - ntb_create_callbacks(ntb, num_vectors); - if (use_msix == TRUE) { - for (i = 0; i < num_vectors; i++) { - ntb->int_info[i].rid = i + 1; - ntb->int_info[i].res = bus_alloc_resource_any( - ntb->device, SYS_RES_IRQ, &ntb->int_info[i].rid, - RF_ACTIVE); - if (ntb->int_info[i].res == NULL) { - device_printf(ntb->device, - "bus_alloc_resource failed\n"); - return (-1); - } - ntb->int_info[i].tag = NULL; - ntb->allocated_interrupts++; - if (ntb->type == NTB_SOC) { - interrupt_handler = handle_soc_irq; - int_arg = &ntb->db_cb[i]; - } else { - if (i == num_vectors - 1) { - interrupt_handler = - handle_xeon_event_irq; - int_arg = ntb; - } else { - interrupt_handler = - handle_xeon_irq; - int_arg = &ntb->db_cb[i]; - } - } - if (bus_setup_intr(ntb->device, ntb->int_info[i].res, - INTR_MPSAFE | INTR_TYPE_MISC, NULL, - interrupt_handler, int_arg, - &ntb->int_info[i].tag) != 0) { - device_printf(ntb->device, - "bus_setup_intr failed\n"); - return (ENXIO); - } + if (ntb_force_remap_mode != 0 && rc == 0 && + num_vectors == desired_vectors) + num_vectors--; + + if (rc == 0 && num_vectors < desired_vectors) { + rc = ntb_remap_msix(ntb->device, desired_vectors, + num_vectors); + if (rc == 0) + num_vectors = desired_vectors; + else + pci_release_msi(ntb->device); } + if (rc != 0) + num_vectors = 1; + } else + num_vectors = 1; + + if (ntb->type == NTB_XEON && num_vectors < ntb->db_vec_count) { + ntb->db_vec_count = 1; + ntb->db_vec_shift = XEON_DB_TOTAL_SHIFT; + rc = ntb_setup_legacy_interrupt(ntb); + } else { + ntb_create_msix_vec(ntb, num_vectors); + rc = ntb_setup_msix(ntb, num_vectors); } - else { - ntb->int_info[0].rid = 0; - ntb->int_info[0].res = bus_alloc_resource_any(ntb->device, - SYS_RES_IRQ, &ntb->int_info[0].rid, RF_SHAREABLE|RF_ACTIVE); - interrupt_handler = ntb_handle_legacy_interrupt; - if (ntb->int_info[0].res == NULL) { - device_printf(ntb->device, - "bus_alloc_resource failed\n"); - return (-1); - } - ntb->int_info[0].tag = NULL; - ntb->allocated_interrupts = 1; + if (rc != 0) { + device_printf(ntb->device, + "Error allocating interrupts: %d\n", rc); + ntb_free_msix_vec(ntb); + } - if (bus_setup_intr(ntb->device, ntb->int_info[0].res, - INTR_MPSAFE | INTR_TYPE_MISC, NULL, - interrupt_handler, ntb, &ntb->int_info[0].tag) != 0) { + return (rc); +} - device_printf(ntb->device, "bus_setup_intr failed\n"); - return (ENXIO); - } +static int +ntb_setup_legacy_interrupt(struct ntb_softc *ntb) +{ + int rc; + + ntb->int_info[0].rid = 0; + ntb->int_info[0].res = bus_alloc_resource_any(ntb->device, SYS_RES_IRQ, + &ntb->int_info[0].rid, RF_SHAREABLE|RF_ACTIVE); + if (ntb->int_info[0].res == NULL) { + device_printf(ntb->device, "bus_alloc_resource failed\n"); + return (ENOMEM); } + ntb->int_info[0].tag = NULL; + ntb->allocated_interrupts = 1; + + rc = bus_setup_intr(ntb->device, ntb->int_info[0].res, + INTR_MPSAFE | INTR_TYPE_MISC, NULL, ndev_irq_isr, + ntb, &ntb->int_info[0].tag); + if (rc != 0) { + device_printf(ntb->device, "bus_setup_intr failed\n"); + return (ENXIO); + } + return (0); } static void ntb_teardown_interrupts(struct ntb_softc *ntb) { struct ntb_int_info *current_int; int i; - for (i=0; iallocated_interrupts; i++) { + for (i = 0; i < ntb->allocated_interrupts; i++) { current_int = &ntb->int_info[i]; if (current_int->tag != NULL) bus_teardown_intr(ntb->device, current_int->res, current_int->tag); if (current_int->res != NULL) bus_release_resource(ntb->device, SYS_RES_IRQ, rman_get_rid(current_int->res), current_int->res); } - ntb_free_callbacks(ntb); + ntb_free_msix_vec(ntb); pci_release_msi(ntb->device); } -static void -handle_soc_irq(void *arg) +/* + * Doorbell register and mask are 64-bit on Atom, 16-bit on Xeon. Abstract it + * out to make code clearer. + */ +static inline uint64_t +db_ioread(struct ntb_softc *ntb, uint64_t regoff) { - struct ntb_db_cb *db_cb = arg; - struct ntb_softc *ntb = db_cb->ntb; - ntb_reg_write(8, ntb->reg_ofs.pdb, (uint64_t) 1 << db_cb->db_num); + if (ntb->type == NTB_ATOM) + return (ntb_reg_read(8, regoff)); - if (db_cb->callback != NULL) - db_cb->callback(db_cb->data, db_cb->db_num); + KASSERT(ntb->type == NTB_XEON, ("bad ntb type")); + + return (ntb_reg_read(2, regoff)); } -static void -handle_xeon_irq(void *arg) +static inline void +db_iowrite(struct ntb_softc *ntb, uint64_t regoff, uint64_t val) { - struct ntb_db_cb *db_cb = arg; - struct ntb_softc *ntb = db_cb->ntb; - /* - * On Xeon, there are 16 bits in the interrupt register - * but only 4 vectors. So, 5 bits are assigned to the first 3 - * vectors, with the 4th having a single bit for link - * interrupts. - */ - ntb_reg_write(2, ntb->reg_ofs.pdb, - ((1 << ntb->bits_per_vector) - 1) << - (db_cb->db_num * ntb->bits_per_vector)); + KASSERT((val & ~ntb->db_valid_mask) == 0, + ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, + (uintmax_t)(val & ~ntb->db_valid_mask), + (uintmax_t)ntb->db_valid_mask)); - if (db_cb->callback != NULL) - db_cb->callback(db_cb->data, db_cb->db_num); + if (regoff == ntb->self_reg->db_mask) + DB_MASK_ASSERT(ntb, MA_OWNED); + db_iowrite_raw(ntb, regoff, val); } -/* Since we do not have a HW doorbell in SOC, this is only used in JF/JT */ -static void -handle_xeon_event_irq(void *arg) +static inline void +db_iowrite_raw(struct ntb_softc *ntb, uint64_t regoff, uint64_t val) { - struct ntb_softc *ntb = arg; - int rc; - rc = ntb_check_link_status(ntb); - if (rc != 0) - device_printf(ntb->device, "Error determining link status\n"); + if (ntb->type == NTB_ATOM) { + ntb_reg_write(8, regoff, val); + return; + } - /* bit 15 is always the link bit */ - ntb_reg_write(2, ntb->reg_ofs.pdb, 1 << ntb->limits.max_db_bits); + KASSERT(ntb->type == NTB_XEON, ("bad ntb type")); + ntb_reg_write(2, regoff, (uint16_t)val); } -static void -ntb_handle_legacy_interrupt(void *arg) +void +ntb_db_set_mask(struct ntb_softc *ntb, uint64_t bits) { - struct ntb_softc *ntb = arg; - unsigned int i = 0; - uint64_t pdb64; - uint16_t pdb16; - if (ntb->type == NTB_SOC) { - pdb64 = ntb_reg_read(8, ntb->reg_ofs.pdb); + DB_MASK_LOCK(ntb); + ntb->db_mask |= bits; + db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); + DB_MASK_UNLOCK(ntb); +} - while (pdb64) { - i = ffs(pdb64); - pdb64 &= pdb64 - 1; - handle_soc_irq(&ntb->db_cb[i]); - } - } else { - pdb16 = ntb_reg_read(2, ntb->reg_ofs.pdb); +void +ntb_db_clear_mask(struct ntb_softc *ntb, uint64_t bits) +{ - if ((pdb16 & XEON_DB_HW_LINK) != 0) { - handle_xeon_event_irq(ntb); - pdb16 &= ~XEON_DB_HW_LINK; - } + KASSERT((bits & ~ntb->db_valid_mask) == 0, + ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, + (uintmax_t)(bits & ~ntb->db_valid_mask), + (uintmax_t)ntb->db_valid_mask)); - while (pdb16 != 0) { - i = ffs(pdb16); - pdb16 &= pdb16 - 1; - handle_xeon_irq(&ntb->db_cb[i]); - } + DB_MASK_LOCK(ntb); + ntb->db_mask &= ~bits; + db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); + DB_MASK_UNLOCK(ntb); +} + +uint64_t +ntb_db_read(struct ntb_softc *ntb) +{ + + return (db_ioread(ntb, ntb->self_reg->db_bell)); +} + +void +ntb_db_clear(struct ntb_softc *ntb, uint64_t bits) +{ + + KASSERT((bits & ~ntb->db_valid_mask) == 0, + ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, + (uintmax_t)(bits & ~ntb->db_valid_mask), + (uintmax_t)ntb->db_valid_mask)); + + db_iowrite(ntb, ntb->self_reg->db_bell, bits); +} + +static inline uint64_t +ntb_vec_mask(struct ntb_softc *ntb, uint64_t db_vector) +{ + uint64_t shift, mask; + + shift = ntb->db_vec_shift; + mask = (1ull << shift) - 1; + return (mask << (shift * db_vector)); +} + +static void +ntb_interrupt(struct ntb_softc *ntb, uint32_t vec) +{ + uint64_t vec_mask; + + ntb->last_ts = ticks; + vec_mask = ntb_vec_mask(ntb, vec); + + if ((vec_mask & ntb->db_link_mask) != 0) { + if (ntb_poll_link(ntb)) + ntb_link_event(ntb); } + if ((vec_mask & ntb->db_valid_mask) != 0) + ntb_db_event(ntb, vec); } +static void +ndev_vec_isr(void *arg) +{ + struct ntb_vec *nvec = arg; + + ntb_interrupt(nvec->ntb, nvec->num); +} + +static void +ndev_irq_isr(void *arg) +{ + /* If we couldn't set up MSI-X, we only have the one vector. */ + ntb_interrupt(arg, 0); +} + static int -ntb_create_callbacks(struct ntb_softc *ntb, int num_vectors) +ntb_create_msix_vec(struct ntb_softc *ntb, uint32_t num_vectors) { - int i; + uint32_t i; - ntb->db_cb = malloc(num_vectors * sizeof(struct ntb_db_cb), M_NTB, + ntb->msix_vec = malloc(num_vectors * sizeof(*ntb->msix_vec), M_NTB, M_ZERO | M_WAITOK); for (i = 0; i < num_vectors; i++) { - ntb->db_cb[i].db_num = i; - ntb->db_cb[i].ntb = ntb; + ntb->msix_vec[i].num = i; + ntb->msix_vec[i].ntb = ntb; } return (0); } static void -ntb_free_callbacks(struct ntb_softc *ntb) +ntb_free_msix_vec(struct ntb_softc *ntb) { - int i; - for (i = 0; i < ntb->limits.max_db_bits; i++) - ntb_unregister_db_callback(ntb, i); + if (ntb->msix_vec == NULL) + return; - free(ntb->db_cb, M_NTB); + free(ntb->msix_vec, M_NTB); + ntb->msix_vec = NULL; } static struct ntb_hw_info * ntb_get_device_info(uint32_t device_id) { struct ntb_hw_info *ep = pci_ids; while (ep->device_id) { if (ep->device_id == device_id) return (ep); ++ep; } return (NULL); } -static int -ntb_initialize_hw(struct ntb_softc *ntb) +static void +ntb_teardown_xeon(struct ntb_softc *ntb) { - if (ntb->type == NTB_SOC) - return (ntb_setup_soc(ntb)); + if (ntb->reg != NULL) + ntb_link_disable(ntb); +} + +static void +ntb_detect_max_mw(struct ntb_softc *ntb) +{ + + if (ntb->type == NTB_ATOM) { + ntb->mw_count = ATOM_MW_COUNT; + return; + } + + if (HAS_FEATURE(NTB_SPLIT_BAR)) + ntb->mw_count = XEON_HSX_SPLIT_MW_COUNT; else - return (ntb_setup_xeon(ntb)); + ntb->mw_count = XEON_SNB_MW_COUNT; } static int -ntb_setup_xeon(struct ntb_softc *ntb) +ntb_detect_xeon(struct ntb_softc *ntb) { - uint8_t val, connection_type; + uint8_t ppd, conn_type; - val = pci_read_config(ntb->device, NTB_PPD_OFFSET, 1); + ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 1); + ntb->ppd = ppd; - connection_type = val & XEON_PPD_CONN_TYPE; - switch (connection_type) { + if ((ppd & XEON_PPD_DEV_TYPE) != 0) + ntb->dev_type = NTB_DEV_DSD; + else + ntb->dev_type = NTB_DEV_USD; + + if ((ppd & XEON_PPD_SPLIT_BAR) != 0) + ntb->features |= NTB_SPLIT_BAR; + + /* SB01BASE_LOCKUP errata is a superset of SDOORBELL errata */ + if (HAS_FEATURE(NTB_SB01BASE_LOCKUP)) + ntb->features |= NTB_SDOORBELL_LOCKUP; + + conn_type = ppd & XEON_PPD_CONN_TYPE; + switch (conn_type) { case NTB_CONN_B2B: - ntb->conn_type = NTB_CONN_B2B; + ntb->conn_type = conn_type; break; - case NTB_CONN_CLASSIC: case NTB_CONN_RP: + case NTB_CONN_TRANSPARENT: default: - device_printf(ntb->device, "Connection type %d not supported\n", - connection_type); + device_printf(ntb->device, "Unsupported connection type: %u\n", + (unsigned)conn_type); return (ENXIO); } + return (0); +} - if ((val & XEON_PPD_DEV_TYPE) != 0) +static int +ntb_detect_atom(struct ntb_softc *ntb) +{ + uint32_t ppd, conn_type; + + ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 4); + ntb->ppd = ppd; + + if ((ppd & ATOM_PPD_DEV_TYPE) != 0) ntb->dev_type = NTB_DEV_DSD; else ntb->dev_type = NTB_DEV_USD; - ntb->reg_ofs.pdb = XEON_PDOORBELL_OFFSET; - ntb->reg_ofs.pdb_mask = XEON_PDBMSK_OFFSET; - ntb->reg_ofs.sbar2_xlat = XEON_SBAR2XLAT_OFFSET; - ntb->reg_ofs.sbar4_xlat = XEON_SBAR4XLAT_OFFSET; - ntb->reg_ofs.lnk_cntl = XEON_NTBCNTL_OFFSET; - ntb->reg_ofs.lnk_stat = XEON_LINK_STATUS_OFFSET; - ntb->reg_ofs.spad_local = XEON_SPAD_OFFSET; - ntb->reg_ofs.spci_cmd = XEON_PCICMD_OFFSET; - - if (ntb->conn_type == NTB_CONN_B2B) { - ntb->reg_ofs.sdb = XEON_B2B_DOORBELL_OFFSET; - ntb->reg_ofs.spad_remote = XEON_B2B_SPAD_OFFSET; - ntb->limits.max_spads = XEON_MAX_SPADS; - } else { - ntb->reg_ofs.sdb = XEON_SDOORBELL_OFFSET; - ntb->reg_ofs.spad_remote = XEON_SPAD_OFFSET; - ntb->limits.max_spads = XEON_MAX_COMPAT_SPADS; + conn_type = (ppd & ATOM_PPD_CONN_TYPE) >> 8; + switch (conn_type) { + case NTB_CONN_B2B: + ntb->conn_type = conn_type; + break; + default: + device_printf(ntb->device, "Unsupported NTB configuration\n"); + return (ENXIO); } - - ntb->limits.max_db_bits = XEON_MAX_DB_BITS; - ntb->limits.msix_cnt = XEON_MSIX_CNT; - ntb->bits_per_vector = XEON_DB_BITS_PER_VEC; - - configure_xeon_secondary_side_bars(ntb); - /* Enable Bus Master and Memory Space on the secondary side */ - ntb_reg_write(2, ntb->reg_ofs.spci_cmd, - PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); - - /* Enable link training */ - ntb_reg_write(4, ntb->reg_ofs.lnk_cntl, - NTB_CNTL_BAR23_SNOOP | NTB_CNTL_BAR45_SNOOP); - return (0); } static int -ntb_setup_soc(struct ntb_softc *ntb) +ntb_xeon_init_dev(struct ntb_softc *ntb) { - uint32_t val, connection_type; + int rc; - val = pci_read_config(ntb->device, NTB_PPD_OFFSET, 4); + ntb->spad_count = XEON_SPAD_COUNT; + ntb->db_count = XEON_DB_COUNT; + ntb->db_link_mask = XEON_DB_LINK_BIT; + ntb->db_vec_count = XEON_DB_MSIX_VECTOR_COUNT; + ntb->db_vec_shift = XEON_DB_MSIX_VECTOR_SHIFT; - connection_type = (val & SOC_PPD_CONN_TYPE) >> 8; - switch (connection_type) { - case NTB_CONN_B2B: - ntb->conn_type = NTB_CONN_B2B; - break; - case NTB_CONN_RP: - default: + if (ntb->conn_type != NTB_CONN_B2B) { device_printf(ntb->device, "Connection type %d not supported\n", - connection_type); + ntb->conn_type); return (ENXIO); } - if ((val & SOC_PPD_DEV_TYPE) != 0) - ntb->dev_type = NTB_DEV_DSD; + ntb->reg = &xeon_reg; + ntb->self_reg = &xeon_pri_reg; + ntb->peer_reg = &xeon_b2b_reg; + ntb->xlat_reg = &xeon_sec_xlat; + + /* + * There is a Xeon hardware errata related to writes to SDOORBELL or + * B2BDOORBELL in conjunction with inbound access to NTB MMIO space, + * which may hang the system. To workaround this, use a memory + * window to access the interrupt and scratch pad registers on the + * remote system. + */ + if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) { + ntb->b2b_mw_idx = (ntb->mw_count + g_ntb_mw_idx) % + ntb->mw_count; + ntb_printf(2, "Setting up b2b mw idx %d means %u\n", + g_ntb_mw_idx, ntb->b2b_mw_idx); + rc = ntb_mw_set_wc_internal(ntb, ntb->b2b_mw_idx, VM_MEMATTR_UNCACHEABLE); + KASSERT(rc == 0, ("shouldn't fail")); + } else if (HAS_FEATURE(NTB_B2BDOORBELL_BIT14)) + /* + * HW Errata on bit 14 of b2bdoorbell register. Writes will not be + * mirrored to the remote system. Shrink the number of bits by one, + * since bit 14 is the last bit. + * + * On REGS_THRU_MW errata mode, we don't use the b2bdoorbell register + * anyway. Nor for non-B2B connection types. + */ + ntb->db_count = XEON_DB_COUNT - 1; + + ntb->db_valid_mask = (1ull << ntb->db_count) - 1; + + if (ntb->dev_type == NTB_DEV_USD) + rc = xeon_setup_b2b_mw(ntb, &xeon_b2b_dsd_addr, + &xeon_b2b_usd_addr); else - ntb->dev_type = NTB_DEV_USD; + rc = xeon_setup_b2b_mw(ntb, &xeon_b2b_usd_addr, + &xeon_b2b_dsd_addr); + if (rc != 0) + return (rc); - /* Initiate PCI-E link training */ - pci_write_config(ntb->device, NTB_PPD_OFFSET, val | SOC_PPD_INIT_LINK, - 4); + /* Enable Bus Master and Memory Space on the secondary side */ + ntb_reg_write(2, XEON_SPCICMD_OFFSET, + PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); - ntb->reg_ofs.pdb = SOC_PDOORBELL_OFFSET; - ntb->reg_ofs.pdb_mask = SOC_PDBMSK_OFFSET; - ntb->reg_ofs.sbar2_xlat = SOC_SBAR2XLAT_OFFSET; - ntb->reg_ofs.sbar4_xlat = SOC_SBAR4XLAT_OFFSET; - ntb->reg_ofs.lnk_cntl = SOC_NTBCNTL_OFFSET; - ntb->reg_ofs.lnk_stat = SOC_LINK_STATUS_OFFSET; - ntb->reg_ofs.spad_local = SOC_SPAD_OFFSET; - ntb->reg_ofs.spci_cmd = SOC_PCICMD_OFFSET; + /* + * Mask all doorbell interrupts. + */ + ntb_db_set_mask(ntb, ntb->db_valid_mask); - if (ntb->conn_type == NTB_CONN_B2B) { - ntb->reg_ofs.sdb = SOC_B2B_DOORBELL_OFFSET; - ntb->reg_ofs.spad_remote = SOC_B2B_SPAD_OFFSET; - ntb->limits.max_spads = SOC_MAX_SPADS; - } else { - ntb->reg_ofs.sdb = SOC_PDOORBELL_OFFSET; - ntb->reg_ofs.spad_remote = SOC_SPAD_OFFSET; - ntb->limits.max_spads = SOC_MAX_COMPAT_SPADS; - } + rc = ntb_init_isr(ntb); + return (rc); +} - ntb->limits.max_db_bits = SOC_MAX_DB_BITS; - ntb->limits.msix_cnt = SOC_MSIX_CNT; - ntb->bits_per_vector = SOC_DB_BITS_PER_VEC; +static int +ntb_atom_init_dev(struct ntb_softc *ntb) +{ + int error; + KASSERT(ntb->conn_type == NTB_CONN_B2B, + ("Unsupported NTB configuration (%d)\n", ntb->conn_type)); + + ntb->spad_count = ATOM_SPAD_COUNT; + ntb->db_count = ATOM_DB_COUNT; + ntb->db_vec_count = ATOM_DB_MSIX_VECTOR_COUNT; + ntb->db_vec_shift = ATOM_DB_MSIX_VECTOR_SHIFT; + ntb->db_valid_mask = (1ull << ntb->db_count) - 1; + + ntb->reg = &atom_reg; + ntb->self_reg = &atom_pri_reg; + ntb->peer_reg = &atom_b2b_reg; + ntb->xlat_reg = &atom_sec_xlat; + /* - * FIXME - MSI-X bug on early SOC HW, remove once internal issue is + * FIXME - MSI-X bug on early Atom HW, remove once internal issue is * resolved. Mask transaction layer internal parity errors. */ pci_write_config(ntb->device, 0xFC, 0x4, 4); - configure_soc_secondary_side_bars(ntb); + configure_atom_secondary_side_bars(ntb); /* Enable Bus Master and Memory Space on the secondary side */ - ntb_reg_write(2, ntb->reg_ofs.spci_cmd, + ntb_reg_write(2, ATOM_SPCICMD_OFFSET, PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); - callout_reset(&ntb->heartbeat_timer, 0, ntb_handle_heartbeat, ntb); + error = ntb_init_isr(ntb); + if (error != 0) + return (error); + + /* Initiate PCI-E link training */ + ntb_link_enable(ntb, NTB_SPEED_AUTO, NTB_WIDTH_AUTO); + + callout_reset(&ntb->heartbeat_timer, 0, atom_link_hb, ntb); + return (0); } +/* XXX: Linux driver doesn't seem to do any of this for Atom. */ static void -configure_soc_secondary_side_bars(struct ntb_softc *ntb) +configure_atom_secondary_side_bars(struct ntb_softc *ntb) { if (ntb->dev_type == NTB_DEV_USD) { - ntb_reg_write(8, SOC_PBAR2XLAT_OFFSET, PBAR2XLAT_USD_ADDR); - ntb_reg_write(8, SOC_PBAR4XLAT_OFFSET, PBAR4XLAT_USD_ADDR); - ntb_reg_write(8, SOC_MBAR23_OFFSET, MBAR23_USD_ADDR); - ntb_reg_write(8, SOC_MBAR45_OFFSET, MBAR45_USD_ADDR); + ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET, + XEON_B2B_BAR2_ADDR64); + ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET, + XEON_B2B_BAR4_ADDR64); + ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_ADDR64); + ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_ADDR64); } else { - ntb_reg_write(8, SOC_PBAR2XLAT_OFFSET, PBAR2XLAT_DSD_ADDR); - ntb_reg_write(8, SOC_PBAR4XLAT_OFFSET, PBAR4XLAT_DSD_ADDR); - ntb_reg_write(8, SOC_MBAR23_OFFSET, MBAR23_DSD_ADDR); - ntb_reg_write(8, SOC_MBAR45_OFFSET, MBAR45_DSD_ADDR); + ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET, + XEON_B2B_BAR2_ADDR64); + ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET, + XEON_B2B_BAR4_ADDR64); + ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_ADDR64); + ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_ADDR64); } } + +/* + * When working around Xeon SDOORBELL errata by remapping remote registers in a + * MW, limit the B2B MW to half a MW. By sharing a MW, half the shared MW + * remains for use by a higher layer. + * + * Will only be used if working around SDOORBELL errata and the BIOS-configured + * MW size is sufficiently large. + */ +static unsigned int ntb_b2b_mw_share; +SYSCTL_UINT(_hw_ntb, OID_AUTO, b2b_mw_share, CTLFLAG_RDTUN, &ntb_b2b_mw_share, + 0, "If enabled (non-zero), prefer to share half of the B2B peer register " + "MW with higher level consumers. Both sides of the NTB MUST set the same " + "value here."); + static void -configure_xeon_secondary_side_bars(struct ntb_softc *ntb) +xeon_reset_sbar_size(struct ntb_softc *ntb, enum ntb_bar idx, + enum ntb_bar regbar) { + struct ntb_pci_bar_info *bar; + uint8_t bar_sz; - if (ntb->dev_type == NTB_DEV_USD) { - ntb_reg_write(8, XEON_PBAR2XLAT_OFFSET, PBAR2XLAT_USD_ADDR); - if (HAS_FEATURE(NTB_REGS_THRU_MW)) - ntb_reg_write(8, XEON_PBAR4XLAT_OFFSET, - MBAR01_DSD_ADDR); + if (!HAS_FEATURE(NTB_SPLIT_BAR) && idx >= NTB_B2B_BAR_3) + return; + + bar = &ntb->bar_info[idx]; + bar_sz = pci_read_config(ntb->device, bar->psz_off, 1); + if (idx == regbar) { + if (ntb->b2b_off != 0) + bar_sz--; else - ntb_reg_write(8, XEON_PBAR4XLAT_OFFSET, - PBAR4XLAT_USD_ADDR); - ntb_reg_write(8, XEON_SBAR0BASE_OFFSET, MBAR01_USD_ADDR); - ntb_reg_write(8, XEON_SBAR2BASE_OFFSET, MBAR23_USD_ADDR); - ntb_reg_write(8, XEON_SBAR4BASE_OFFSET, MBAR45_USD_ADDR); + bar_sz = 0; + } + pci_write_config(ntb->device, bar->ssz_off, bar_sz, 1); + bar_sz = pci_read_config(ntb->device, bar->ssz_off, 1); + (void)bar_sz; +} + +static void +xeon_set_sbar_base_and_limit(struct ntb_softc *ntb, uint64_t bar_addr, + enum ntb_bar idx, enum ntb_bar regbar) +{ + uint64_t reg_val; + uint32_t base_reg, lmt_reg; + + bar_get_xlat_params(ntb, idx, &base_reg, NULL, &lmt_reg); + if (idx == regbar) + bar_addr += ntb->b2b_off; + + if (!bar_is_64bit(ntb, idx)) { + ntb_reg_write(4, base_reg, bar_addr); + reg_val = ntb_reg_read(4, base_reg); + (void)reg_val; + + ntb_reg_write(4, lmt_reg, bar_addr); + reg_val = ntb_reg_read(4, lmt_reg); + (void)reg_val; } else { - ntb_reg_write(8, XEON_PBAR2XLAT_OFFSET, PBAR2XLAT_DSD_ADDR); - if (HAS_FEATURE(NTB_REGS_THRU_MW)) - ntb_reg_write(8, XEON_PBAR4XLAT_OFFSET, - MBAR01_USD_ADDR); - else - ntb_reg_write(8, XEON_PBAR4XLAT_OFFSET, - PBAR4XLAT_DSD_ADDR); - ntb_reg_write(8, XEON_SBAR0BASE_OFFSET, MBAR01_DSD_ADDR); - ntb_reg_write(8, XEON_SBAR2BASE_OFFSET, MBAR23_DSD_ADDR); - ntb_reg_write(8, XEON_SBAR4BASE_OFFSET, MBAR45_DSD_ADDR); + ntb_reg_write(8, base_reg, bar_addr); + reg_val = ntb_reg_read(8, base_reg); + (void)reg_val; + + ntb_reg_write(8, lmt_reg, bar_addr); + reg_val = ntb_reg_read(8, lmt_reg); + (void)reg_val; } } -/* SOC does not have link status interrupt, poll on that platform */ static void -ntb_handle_heartbeat(void *arg) +xeon_set_pbar_xlat(struct ntb_softc *ntb, uint64_t base_addr, enum ntb_bar idx) { - struct ntb_softc *ntb = arg; - uint32_t status32; - int rc = ntb_check_link_status(ntb); + struct ntb_pci_bar_info *bar; - if (rc != 0) - device_printf(ntb->device, - "Error determining link status\n"); - /* Check to see if a link error is the cause of the link down */ - if (ntb->link_status == NTB_LINK_DOWN) { - status32 = ntb_reg_read(4, SOC_LTSSMSTATEJMP_OFFSET); - if ((status32 & SOC_LTSSMSTATEJMP_FORCEDETECT) != 0) { - callout_reset(&ntb->lr_timer, 0, recover_soc_link, - ntb); - return; + bar = &ntb->bar_info[idx]; + if (HAS_FEATURE(NTB_SPLIT_BAR) && idx >= NTB_B2B_BAR_2) { + ntb_reg_write(4, bar->pbarxlat_off, base_addr); + base_addr = ntb_reg_read(4, bar->pbarxlat_off); + } else { + ntb_reg_write(8, bar->pbarxlat_off, base_addr); + base_addr = ntb_reg_read(8, bar->pbarxlat_off); + } + (void)base_addr; +} + +static int +xeon_setup_b2b_mw(struct ntb_softc *ntb, const struct ntb_b2b_addr *addr, + const struct ntb_b2b_addr *peer_addr) +{ + struct ntb_pci_bar_info *b2b_bar; + vm_size_t bar_size; + uint64_t bar_addr; + enum ntb_bar b2b_bar_num, i; + + if (ntb->b2b_mw_idx == B2B_MW_DISABLED) { + b2b_bar = NULL; + b2b_bar_num = NTB_CONFIG_BAR; + ntb->b2b_off = 0; + } else { + b2b_bar_num = ntb_mw_to_bar(ntb, ntb->b2b_mw_idx); + KASSERT(b2b_bar_num > 0 && b2b_bar_num < NTB_MAX_BARS, + ("invalid b2b mw bar")); + + b2b_bar = &ntb->bar_info[b2b_bar_num]; + bar_size = b2b_bar->size; + + if (ntb_b2b_mw_share != 0 && + (bar_size >> 1) >= XEON_B2B_MIN_SIZE) + ntb->b2b_off = bar_size >> 1; + else if (bar_size >= XEON_B2B_MIN_SIZE) { + ntb->b2b_off = 0; + } else { + device_printf(ntb->device, + "B2B bar size is too small!\n"); + return (EIO); } } - callout_reset(&ntb->heartbeat_timer, NTB_HB_TIMEOUT * hz, - ntb_handle_heartbeat, ntb); + /* + * Reset the secondary bar sizes to match the primary bar sizes. + * (Except, disable or halve the size of the B2B secondary bar.) + */ + for (i = NTB_B2B_BAR_1; i < NTB_MAX_BARS; i++) + xeon_reset_sbar_size(ntb, i, b2b_bar_num); + + bar_addr = 0; + if (b2b_bar_num == NTB_CONFIG_BAR) + bar_addr = addr->bar0_addr; + else if (b2b_bar_num == NTB_B2B_BAR_1) + bar_addr = addr->bar2_addr64; + else if (b2b_bar_num == NTB_B2B_BAR_2 && !HAS_FEATURE(NTB_SPLIT_BAR)) + bar_addr = addr->bar4_addr64; + else if (b2b_bar_num == NTB_B2B_BAR_2) + bar_addr = addr->bar4_addr32; + else if (b2b_bar_num == NTB_B2B_BAR_3) + bar_addr = addr->bar5_addr32; + else + KASSERT(false, ("invalid bar")); + + ntb_reg_write(8, XEON_SBAR0BASE_OFFSET, bar_addr); + + /* + * Other SBARs are normally hit by the PBAR xlat, except for the b2b + * register BAR. The B2B BAR is either disabled above or configured + * half-size. It starts at PBAR xlat + offset. + * + * Also set up incoming BAR limits == base (zero length window). + */ + xeon_set_sbar_base_and_limit(ntb, addr->bar2_addr64, NTB_B2B_BAR_1, + b2b_bar_num); + if (HAS_FEATURE(NTB_SPLIT_BAR)) { + xeon_set_sbar_base_and_limit(ntb, addr->bar4_addr32, + NTB_B2B_BAR_2, b2b_bar_num); + xeon_set_sbar_base_and_limit(ntb, addr->bar5_addr32, + NTB_B2B_BAR_3, b2b_bar_num); + } else + xeon_set_sbar_base_and_limit(ntb, addr->bar4_addr64, + NTB_B2B_BAR_2, b2b_bar_num); + + /* Zero incoming translation addrs */ + ntb_reg_write(8, XEON_SBAR2XLAT_OFFSET, 0); + ntb_reg_write(8, XEON_SBAR4XLAT_OFFSET, 0); + + /* Zero outgoing translation limits (whole bar size windows) */ + ntb_reg_write(8, XEON_PBAR2LMT_OFFSET, 0); + ntb_reg_write(8, XEON_PBAR4LMT_OFFSET, 0); + + /* Set outgoing translation offsets */ + xeon_set_pbar_xlat(ntb, peer_addr->bar2_addr64, NTB_B2B_BAR_1); + if (HAS_FEATURE(NTB_SPLIT_BAR)) { + xeon_set_pbar_xlat(ntb, peer_addr->bar4_addr32, NTB_B2B_BAR_2); + xeon_set_pbar_xlat(ntb, peer_addr->bar5_addr32, NTB_B2B_BAR_3); + } else + xeon_set_pbar_xlat(ntb, peer_addr->bar4_addr64, NTB_B2B_BAR_2); + + /* Set the translation offset for B2B registers */ + bar_addr = 0; + if (b2b_bar_num == NTB_CONFIG_BAR) + bar_addr = peer_addr->bar0_addr; + else if (b2b_bar_num == NTB_B2B_BAR_1) + bar_addr = peer_addr->bar2_addr64; + else if (b2b_bar_num == NTB_B2B_BAR_2 && !HAS_FEATURE(NTB_SPLIT_BAR)) + bar_addr = peer_addr->bar4_addr64; + else if (b2b_bar_num == NTB_B2B_BAR_2) + bar_addr = peer_addr->bar4_addr32; + else if (b2b_bar_num == NTB_B2B_BAR_3) + bar_addr = peer_addr->bar5_addr32; + else + KASSERT(false, ("invalid bar")); + + /* + * B2B_XLAT_OFFSET is a 64-bit register but can only be written 32 bits + * at a time. + */ + ntb_reg_write(4, XEON_B2B_XLAT_OFFSETL, bar_addr & 0xffffffff); + ntb_reg_write(4, XEON_B2B_XLAT_OFFSETU, bar_addr >> 32); + return (0); } +static inline bool +link_is_up(struct ntb_softc *ntb) +{ + + if (ntb->type == NTB_XEON) { + if (ntb->conn_type == NTB_CONN_TRANSPARENT) + return (true); + return ((ntb->lnk_sta & NTB_LINK_STATUS_ACTIVE) != 0); + } + + KASSERT(ntb->type == NTB_ATOM, ("ntb type")); + return ((ntb->ntb_ctl & ATOM_CNTL_LINK_DOWN) == 0); +} + +static inline bool +atom_link_is_err(struct ntb_softc *ntb) +{ + uint32_t status; + + KASSERT(ntb->type == NTB_ATOM, ("ntb type")); + + status = ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET); + if ((status & ATOM_LTSSMSTATEJMP_FORCEDETECT) != 0) + return (true); + + status = ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET); + return ((status & ATOM_IBIST_ERR_OFLOW) != 0); +} + +/* Atom does not have link status interrupt, poll on that platform */ static void -soc_perform_link_restart(struct ntb_softc *ntb) +atom_link_hb(void *arg) { + struct ntb_softc *ntb = arg; + sbintime_t timo, poll_ts; + + timo = NTB_HB_TIMEOUT * hz; + poll_ts = ntb->last_ts + timo; + + /* + * Delay polling the link status if an interrupt was received, unless + * the cached link status says the link is down. + */ + if ((sbintime_t)ticks - poll_ts < 0 && link_is_up(ntb)) { + timo = poll_ts - ticks; + goto out; + } + + if (ntb_poll_link(ntb)) + ntb_link_event(ntb); + + if (!link_is_up(ntb) && atom_link_is_err(ntb)) { + /* Link is down with error, proceed with recovery */ + callout_reset(&ntb->lr_timer, 0, recover_atom_link, ntb); + return; + } + +out: + callout_reset(&ntb->heartbeat_timer, timo, atom_link_hb, ntb); +} + +static void +atom_perform_link_restart(struct ntb_softc *ntb) +{ uint32_t status; /* Driver resets the NTB ModPhy lanes - magic! */ - ntb_reg_write(1, SOC_MODPHY_PCSREG6, 0xe0); - ntb_reg_write(1, SOC_MODPHY_PCSREG4, 0x40); - ntb_reg_write(1, SOC_MODPHY_PCSREG4, 0x60); - ntb_reg_write(1, SOC_MODPHY_PCSREG6, 0x60); + ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0xe0); + ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x40); + ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x60); + ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0x60); /* Driver waits 100ms to allow the NTB ModPhy to settle */ pause("ModPhy", hz / 10); /* Clear AER Errors, write to clear */ - status = ntb_reg_read(4, SOC_ERRCORSTS_OFFSET); + status = ntb_reg_read(4, ATOM_ERRCORSTS_OFFSET); status &= PCIM_AER_COR_REPLAY_ROLLOVER; - ntb_reg_write(4, SOC_ERRCORSTS_OFFSET, status); + ntb_reg_write(4, ATOM_ERRCORSTS_OFFSET, status); /* Clear unexpected electrical idle event in LTSSM, write to clear */ - status = ntb_reg_read(4, SOC_LTSSMERRSTS0_OFFSET); - status |= SOC_LTSSMERRSTS0_UNEXPECTEDEI; - ntb_reg_write(4, SOC_LTSSMERRSTS0_OFFSET, status); + status = ntb_reg_read(4, ATOM_LTSSMERRSTS0_OFFSET); + status |= ATOM_LTSSMERRSTS0_UNEXPECTEDEI; + ntb_reg_write(4, ATOM_LTSSMERRSTS0_OFFSET, status); /* Clear DeSkew Buffer error, write to clear */ - status = ntb_reg_read(4, SOC_DESKEWSTS_OFFSET); - status |= SOC_DESKEWSTS_DBERR; - ntb_reg_write(4, SOC_DESKEWSTS_OFFSET, status); + status = ntb_reg_read(4, ATOM_DESKEWSTS_OFFSET); + status |= ATOM_DESKEWSTS_DBERR; + ntb_reg_write(4, ATOM_DESKEWSTS_OFFSET, status); - status = ntb_reg_read(4, SOC_IBSTERRRCRVSTS0_OFFSET); - status &= SOC_IBIST_ERR_OFLOW; - ntb_reg_write(4, SOC_IBSTERRRCRVSTS0_OFFSET, status); + status = ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET); + status &= ATOM_IBIST_ERR_OFLOW; + ntb_reg_write(4, ATOM_IBSTERRRCRVSTS0_OFFSET, status); /* Releases the NTB state machine to allow the link to retrain */ - status = ntb_reg_read(4, SOC_LTSSMSTATEJMP_OFFSET); - status &= ~SOC_LTSSMSTATEJMP_FORCEDETECT; - ntb_reg_write(4, SOC_LTSSMSTATEJMP_OFFSET, status); + status = ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET); + status &= ~ATOM_LTSSMSTATEJMP_FORCEDETECT; + ntb_reg_write(4, ATOM_LTSSMSTATEJMP_OFFSET, status); } +/* + * ntb_set_ctx() - associate a driver context with an ntb device + * @ntb: NTB device context + * @ctx: Driver context + * @ctx_ops: Driver context operations + * + * Associate a driver context and operations with a ntb device. The context is + * provided by the client driver, and the driver may associate a different + * context with each ntb device. + * + * Return: Zero if the context is associated, otherwise an error number. + */ +int +ntb_set_ctx(struct ntb_softc *ntb, void *ctx, const struct ntb_ctx_ops *ops) +{ + + if (ctx == NULL || ops == NULL) + return (EINVAL); + if (ntb->ctx_ops != NULL) + return (EINVAL); + + CTX_LOCK(ntb); + if (ntb->ctx_ops != NULL) { + CTX_UNLOCK(ntb); + return (EINVAL); + } + ntb->ntb_ctx = ctx; + ntb->ctx_ops = ops; + CTX_UNLOCK(ntb); + + return (0); +} + +/* + * It is expected that this will only be used from contexts where the ctx_lock + * is not needed to protect ntb_ctx lifetime. + */ +void * +ntb_get_ctx(struct ntb_softc *ntb, const struct ntb_ctx_ops **ops) +{ + + KASSERT(ntb->ntb_ctx != NULL && ntb->ctx_ops != NULL, ("bogus")); + if (ops != NULL) + *ops = ntb->ctx_ops; + return (ntb->ntb_ctx); +} + +/* + * ntb_clear_ctx() - disassociate any driver context from an ntb device + * @ntb: NTB device context + * + * Clear any association that may exist between a driver context and the ntb + * device. + */ +void +ntb_clear_ctx(struct ntb_softc *ntb) +{ + + CTX_LOCK(ntb); + ntb->ntb_ctx = NULL; + ntb->ctx_ops = NULL; + CTX_UNLOCK(ntb); +} + +/* + * ntb_link_event() - notify driver context of a change in link status + * @ntb: NTB device context + * + * Notify the driver context that the link status may have changed. The driver + * should call ntb_link_is_up() to get the current status. + */ +void +ntb_link_event(struct ntb_softc *ntb) +{ + + CTX_LOCK(ntb); + if (ntb->ctx_ops != NULL && ntb->ctx_ops->link_event != NULL) + ntb->ctx_ops->link_event(ntb->ntb_ctx); + CTX_UNLOCK(ntb); +} + +/* + * ntb_db_event() - notify driver context of a doorbell event + * @ntb: NTB device context + * @vector: Interrupt vector number + * + * Notify the driver context of a doorbell event. If hardware supports + * multiple interrupt vectors for doorbells, the vector number indicates which + * vector received the interrupt. The vector number is relative to the first + * vector used for doorbells, starting at zero, and must be less than + * ntb_db_vector_count(). The driver may call ntb_db_read() to check which + * doorbell bits need service, and ntb_db_vector_mask() to determine which of + * those bits are associated with the vector number. + */ static void -ntb_handle_link_event(struct ntb_softc *ntb, int link_state) +ntb_db_event(struct ntb_softc *ntb, uint32_t vec) { - enum ntb_hw_event event; - uint16_t status; - if (ntb->link_status == link_state) - return; + CTX_LOCK(ntb); + if (ntb->ctx_ops != NULL && ntb->ctx_ops->db_event != NULL) + ntb->ctx_ops->db_event(ntb->ntb_ctx, vec); + CTX_UNLOCK(ntb); +} - if (link_state == NTB_LINK_UP) { - device_printf(ntb->device, "Link Up\n"); - ntb->link_status = NTB_LINK_UP; - event = NTB_EVENT_HW_LINK_UP; +/* + * ntb_link_enable() - enable the link on the secondary side of the ntb + * @ntb: NTB device context + * @max_speed: The maximum link speed expressed as PCIe generation number[0] + * @max_width: The maximum link width expressed as the number of PCIe lanes[0] + * + * Enable the link on the secondary side of the ntb. This can only be done + * from the primary side of the ntb in primary or b2b topology. The ntb device + * should train the link to its maximum speed and width, or the requested speed + * and width, whichever is smaller, if supported. + * + * Return: Zero on success, otherwise an error number. + * + * [0]: Only NTB_SPEED_AUTO and NTB_WIDTH_AUTO are valid inputs; other speed + * and width input will be ignored. + */ +int +ntb_link_enable(struct ntb_softc *ntb, enum ntb_speed s __unused, + enum ntb_width w __unused) +{ + uint32_t cntl; - if (ntb->type == NTB_SOC) - status = ntb_reg_read(2, ntb->reg_ofs.lnk_stat); - else - status = pci_read_config(ntb->device, - XEON_LINK_STATUS_OFFSET, 2); - ntb->link_width = (status & NTB_LINK_WIDTH_MASK) >> 4; - ntb->link_speed = (status & NTB_LINK_SPEED_MASK); - device_printf(ntb->device, "Link Width %d, Link Speed %d\n", - ntb->link_width, ntb->link_speed); - callout_reset(&ntb->heartbeat_timer, NTB_HB_TIMEOUT * hz, - ntb_handle_heartbeat, ntb); - } else { - device_printf(ntb->device, "Link Down\n"); - ntb->link_status = NTB_LINK_DOWN; - event = NTB_EVENT_HW_LINK_DOWN; - /* Do not modify link width/speed, we need it in link recovery */ + if (ntb->type == NTB_ATOM) { + pci_write_config(ntb->device, NTB_PPD_OFFSET, + ntb->ppd | ATOM_PPD_INIT_LINK, 4); + return (0); } - /* notify the upper layer if we have an event change */ - if (ntb->event_cb != NULL) - ntb->event_cb(ntb->ntb_transport, event); + if (ntb->conn_type == NTB_CONN_TRANSPARENT) { + ntb_link_event(ntb); + return (0); + } + + cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); + cntl &= ~(NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK); + cntl |= NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP; + cntl |= NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP; + if (HAS_FEATURE(NTB_SPLIT_BAR)) + cntl |= NTB_CNTL_P2S_BAR5_SNOOP | NTB_CNTL_S2P_BAR5_SNOOP; + ntb_reg_write(4, ntb->reg->ntb_ctl, cntl); + return (0); } +/* + * ntb_link_disable() - disable the link on the secondary side of the ntb + * @ntb: NTB device context + * + * Disable the link on the secondary side of the ntb. This can only be done + * from the primary side of the ntb in primary or b2b topology. The ntb device + * should disable the link. Returning from this call must indicate that a + * barrier has passed, though with no more writes may pass in either direction + * across the link, except if this call returns an error number. + * + * Return: Zero on success, otherwise an error number. + */ +int +ntb_link_disable(struct ntb_softc *ntb) +{ + uint32_t cntl; + + if (ntb->conn_type == NTB_CONN_TRANSPARENT) { + ntb_link_event(ntb); + return (0); + } + + cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); + cntl &= ~(NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP); + cntl &= ~(NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP); + if (HAS_FEATURE(NTB_SPLIT_BAR)) + cntl &= ~(NTB_CNTL_P2S_BAR5_SNOOP | NTB_CNTL_S2P_BAR5_SNOOP); + cntl |= NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK; + ntb_reg_write(4, ntb->reg->ntb_ctl, cntl); + return (0); +} + static void -recover_soc_link(void *arg) +recover_atom_link(void *arg) { struct ntb_softc *ntb = arg; - uint8_t speed, width; + unsigned speed, width, oldspeed, oldwidth; uint32_t status32; - uint16_t status16; - soc_perform_link_restart(ntb); - pause("Link", SOC_LINK_RECOVERY_TIME * hz / 1000); + atom_perform_link_restart(ntb); - status32 = ntb_reg_read(4, SOC_LTSSMSTATEJMP_OFFSET); - if ((status32 & SOC_LTSSMSTATEJMP_FORCEDETECT) != 0) - goto retry; + /* + * There is a potential race between the 2 NTB devices recovering at + * the same time. If the times are the same, the link will not recover + * and the driver will be stuck in this loop forever. Add a random + * interval to the recovery time to prevent this race. + */ + status32 = arc4random() % ATOM_LINK_RECOVERY_TIME; + pause("Link", (ATOM_LINK_RECOVERY_TIME + status32) * hz / 1000); - status32 = ntb_reg_read(4, SOC_IBSTERRRCRVSTS0_OFFSET); - if ((status32 & SOC_IBIST_ERR_OFLOW) != 0) + if (atom_link_is_err(ntb)) goto retry; - status16 = ntb_reg_read(2, ntb->reg_ofs.lnk_stat); - width = (status16 & NTB_LINK_WIDTH_MASK) >> 4; - speed = (status16 & NTB_LINK_SPEED_MASK); - if (ntb->link_width != width || ntb->link_speed != speed) + status32 = ntb_reg_read(4, ntb->reg->ntb_ctl); + if ((status32 & ATOM_CNTL_LINK_DOWN) != 0) + goto out; + + status32 = ntb_reg_read(4, ntb->reg->lnk_sta); + width = NTB_LNK_STA_WIDTH(status32); + speed = status32 & NTB_LINK_SPEED_MASK; + + oldwidth = NTB_LNK_STA_WIDTH(ntb->lnk_sta); + oldspeed = ntb->lnk_sta & NTB_LINK_SPEED_MASK; + if (oldwidth != width || oldspeed != speed) goto retry; - callout_reset(&ntb->heartbeat_timer, NTB_HB_TIMEOUT * hz, - ntb_handle_heartbeat, ntb); +out: + callout_reset(&ntb->heartbeat_timer, NTB_HB_TIMEOUT * hz, atom_link_hb, + ntb); return; retry: - callout_reset(&ntb->lr_timer, NTB_HB_TIMEOUT * hz, recover_soc_link, + callout_reset(&ntb->lr_timer, NTB_HB_TIMEOUT * hz, recover_atom_link, ntb); } -static int -ntb_check_link_status(struct ntb_softc *ntb) +/* + * Polls the HW link status register(s); returns true if something has changed. + */ +static bool +ntb_poll_link(struct ntb_softc *ntb) { - int link_state; uint32_t ntb_cntl; - uint16_t status; + uint16_t reg_val; - if (ntb->type == NTB_SOC) { - ntb_cntl = ntb_reg_read(4, ntb->reg_ofs.lnk_cntl); - if ((ntb_cntl & SOC_CNTL_LINK_DOWN) != 0) - link_state = NTB_LINK_DOWN; - else - link_state = NTB_LINK_UP; + if (ntb->type == NTB_ATOM) { + ntb_cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); + if (ntb_cntl == ntb->ntb_ctl) + return (false); + + ntb->ntb_ctl = ntb_cntl; + ntb->lnk_sta = ntb_reg_read(4, ntb->reg->lnk_sta); } else { - status = pci_read_config(ntb->device, XEON_LINK_STATUS_OFFSET, - 2); + db_iowrite_raw(ntb, ntb->self_reg->db_bell, ntb->db_link_mask); - if ((status & NTB_LINK_STATUS_ACTIVE) != 0) - link_state = NTB_LINK_UP; - else - link_state = NTB_LINK_DOWN; + reg_val = pci_read_config(ntb->device, ntb->reg->lnk_sta, 2); + if (reg_val == ntb->lnk_sta) + return (false); + + ntb->lnk_sta = reg_val; } + return (true); +} - ntb_handle_link_event(ntb, link_state); +static inline enum ntb_speed +ntb_link_sta_speed(struct ntb_softc *ntb) +{ - return (0); + if (!link_is_up(ntb)) + return (NTB_SPEED_NONE); + return (ntb->lnk_sta & NTB_LINK_SPEED_MASK); } -/** - * ntb_register_event_callback() - register event callback - * @ntb: pointer to ntb_softc instance - * @func: callback function to register - * - * This function registers a callback for any HW driver events such as link - * up/down, power management notices and etc. - * - * RETURNS: An appropriate -ERRNO error value on error, or zero for success. - */ -int -ntb_register_event_callback(struct ntb_softc *ntb, ntb_event_callback func) +static inline enum ntb_width +ntb_link_sta_width(struct ntb_softc *ntb) { - if (ntb->event_cb != NULL) - return (EINVAL); + if (!link_is_up(ntb)) + return (NTB_WIDTH_NONE); + return (NTB_LNK_STA_WIDTH(ntb->lnk_sta)); +} - ntb->event_cb = func; +SYSCTL_NODE(_hw_ntb, OID_AUTO, debug_info, CTLFLAG_RW, 0, + "Driver state, statistics, and HW registers"); - return (0); -} +#define NTB_REGSZ_MASK (3ul << 30) +#define NTB_REG_64 (1ul << 30) +#define NTB_REG_32 (2ul << 30) +#define NTB_REG_16 (3ul << 30) +#define NTB_REG_8 (0ul << 30) -/** - * ntb_unregister_event_callback() - unregisters the event callback - * @ntb: pointer to ntb_softc instance - * - * This function unregisters the existing callback from transport - */ -void -ntb_unregister_event_callback(struct ntb_softc *ntb) +#define NTB_DB_READ (1ul << 29) +#define NTB_PCI_REG (1ul << 28) +#define NTB_REGFLAGS_MASK (NTB_REGSZ_MASK | NTB_DB_READ | NTB_PCI_REG) + +static void +ntb_sysctl_init(struct ntb_softc *ntb) { + struct sysctl_oid_list *tree_par, *regpar, *statpar, *errpar; + struct sysctl_ctx_list *ctx; + struct sysctl_oid *tree, *tmptree; - ntb->event_cb = NULL; -} + ctx = device_get_sysctl_ctx(ntb->device); -/** - * ntb_register_db_callback() - register a callback for doorbell interrupt - * @ntb: pointer to ntb_softc instance - * @idx: doorbell index to register callback, zero based - * @func: callback function to register - * - * This function registers a callback function for the doorbell interrupt - * on the primary side. The function will unmask the doorbell as well to - * allow interrupt. - * - * RETURNS: An appropriate -ERRNO error value on error, or zero for success. - */ -int -ntb_register_db_callback(struct ntb_softc *ntb, unsigned int idx, void *data, - ntb_db_callback func) -{ - uint16_t mask; + tree = SYSCTL_ADD_NODE(ctx, + SYSCTL_CHILDREN(device_get_sysctl_tree(ntb->device)), OID_AUTO, + "debug_info", CTLFLAG_RD, NULL, + "Driver state, statistics, and HW registers"); + tree_par = SYSCTL_CHILDREN(tree); - if (idx >= ntb->allocated_interrupts || ntb->db_cb[idx].callback) { - device_printf(ntb->device, "Invalid Index.\n"); - return (EINVAL); + SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "conn_type", CTLFLAG_RD, + &ntb->conn_type, 0, "0 - Transparent; 1 - B2B; 2 - Root Port"); + SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "dev_type", CTLFLAG_RD, + &ntb->dev_type, 0, "0 - USD; 1 - DSD"); + SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "ppd", CTLFLAG_RD, + &ntb->ppd, 0, "Raw PPD register (cached)"); + + if (ntb->b2b_mw_idx != B2B_MW_DISABLED) { +#ifdef notyet + SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "b2b_idx", CTLFLAG_RD, + &ntb->b2b_mw_idx, 0, + "Index of the MW used for B2B remote register access"); +#endif + SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "b2b_off", + CTLFLAG_RD, &ntb->b2b_off, + "If non-zero, offset of B2B register region in shared MW"); } - ntb->db_cb[idx].callback = func; - ntb->db_cb[idx].data = data; + SYSCTL_ADD_PROC(ctx, tree_par, OID_AUTO, "features", + CTLFLAG_RD | CTLTYPE_STRING, ntb, 0, sysctl_handle_features, "A", + "Features/errata of this NTB device"); - /* unmask interrupt */ - mask = ntb_reg_read(2, ntb->reg_ofs.pdb_mask); - mask &= ~(1 << (idx * ntb->bits_per_vector)); - ntb_reg_write(2, ntb->reg_ofs.pdb_mask, mask); + SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "ntb_ctl", CTLFLAG_RD, + __DEVOLATILE(uint32_t *, &ntb->ntb_ctl), 0, + "NTB CTL register (cached)"); + SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "lnk_sta", CTLFLAG_RD, + __DEVOLATILE(uint32_t *, &ntb->lnk_sta), 0, + "LNK STA register (cached)"); - return (0); -} + SYSCTL_ADD_PROC(ctx, tree_par, OID_AUTO, "link_status", + CTLFLAG_RD | CTLTYPE_STRING, ntb, 0, sysctl_handle_link_status, + "A", "Link status"); -/** - * ntb_unregister_db_callback() - unregister a callback for doorbell interrupt - * @ntb: pointer to ntb_softc instance - * @idx: doorbell index to register callback, zero based - * - * This function unregisters a callback function for the doorbell interrupt - * on the primary side. The function will also mask the said doorbell. - */ -void -ntb_unregister_db_callback(struct ntb_softc *ntb, unsigned int idx) -{ - unsigned long mask; +#ifdef notyet + SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "mw_count", CTLFLAG_RD, + &ntb->mw_count, 0, "MW count"); + SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "spad_count", CTLFLAG_RD, + &ntb->spad_count, 0, "Scratchpad count"); + SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_count", CTLFLAG_RD, + &ntb->db_count, 0, "Doorbell count"); + SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_vec_count", CTLFLAG_RD, + &ntb->db_vec_count, 0, "Doorbell vector count"); + SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_vec_shift", CTLFLAG_RD, + &ntb->db_vec_shift, 0, "Doorbell vector shift"); +#endif - if (idx >= ntb->allocated_interrupts || !ntb->db_cb[idx].callback) + SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_valid_mask", CTLFLAG_RD, + &ntb->db_valid_mask, "Doorbell valid mask"); + SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_link_mask", CTLFLAG_RD, + &ntb->db_link_mask, "Doorbell link mask"); + SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_mask", CTLFLAG_RD, + &ntb->db_mask, "Doorbell mask (cached)"); + + tmptree = SYSCTL_ADD_NODE(ctx, tree_par, OID_AUTO, "registers", + CTLFLAG_RD, NULL, "Raw HW registers (big-endian)"); + regpar = SYSCTL_CHILDREN(tmptree); + + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "ntbcntl", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 | + ntb->reg->ntb_ctl, sysctl_handle_register, "IU", + "NTB Control register"); + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnkcap", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 | + 0x19c, sysctl_handle_register, "IU", + "NTB Link Capabilities"); + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnkcon", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 | + 0x1a0, sysctl_handle_register, "IU", + "NTB Link Control register"); + + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "db_mask", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_64 | NTB_DB_READ | ntb->self_reg->db_mask, + sysctl_handle_register, "QU", "Doorbell mask register"); + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "db_bell", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_64 | NTB_DB_READ | ntb->self_reg->db_bell, + sysctl_handle_register, "QU", "Doorbell register"); + + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat23", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_64 | ntb->xlat_reg->bar2_xlat, + sysctl_handle_register, "QU", "Incoming XLAT23 register"); + if (HAS_FEATURE(NTB_SPLIT_BAR)) { + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat4", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_32 | ntb->xlat_reg->bar4_xlat, + sysctl_handle_register, "IU", "Incoming XLAT4 register"); + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat5", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_32 | ntb->xlat_reg->bar5_xlat, + sysctl_handle_register, "IU", "Incoming XLAT5 register"); + } else { + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat45", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_64 | ntb->xlat_reg->bar4_xlat, + sysctl_handle_register, "QU", "Incoming XLAT45 register"); + } + + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt23", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_64 | ntb->xlat_reg->bar2_limit, + sysctl_handle_register, "QU", "Incoming LMT23 register"); + if (HAS_FEATURE(NTB_SPLIT_BAR)) { + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt4", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_32 | ntb->xlat_reg->bar4_limit, + sysctl_handle_register, "IU", "Incoming LMT4 register"); + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt5", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_32 | ntb->xlat_reg->bar5_limit, + sysctl_handle_register, "IU", "Incoming LMT5 register"); + } else { + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt45", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_64 | ntb->xlat_reg->bar4_limit, + sysctl_handle_register, "QU", "Incoming LMT45 register"); + } + + if (ntb->type == NTB_ATOM) return; - mask = ntb_reg_read(2, ntb->reg_ofs.pdb_mask); - mask |= 1 << (idx * ntb->bits_per_vector); - ntb_reg_write(2, ntb->reg_ofs.pdb_mask, mask); + tmptree = SYSCTL_ADD_NODE(ctx, regpar, OID_AUTO, "xeon_stats", + CTLFLAG_RD, NULL, "Xeon HW statistics"); + statpar = SYSCTL_CHILDREN(tmptree); + SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "upstream_mem_miss", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_16 | XEON_USMEMMISS_OFFSET, + sysctl_handle_register, "SU", "Upstream Memory Miss"); - ntb->db_cb[idx].callback = NULL; + tmptree = SYSCTL_ADD_NODE(ctx, regpar, OID_AUTO, "xeon_hw_err", + CTLFLAG_RD, NULL, "Xeon HW errors"); + errpar = SYSCTL_CHILDREN(tmptree); + + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "ppd", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_8 | NTB_PCI_REG | NTB_PPD_OFFSET, + sysctl_handle_register, "CU", "PPD"); + + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar23_sz", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_8 | NTB_PCI_REG | XEON_PBAR23SZ_OFFSET, + sysctl_handle_register, "CU", "PBAR23 SZ (log2)"); + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar4_sz", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_8 | NTB_PCI_REG | XEON_PBAR4SZ_OFFSET, + sysctl_handle_register, "CU", "PBAR4 SZ (log2)"); + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar5_sz", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_8 | NTB_PCI_REG | XEON_PBAR5SZ_OFFSET, + sysctl_handle_register, "CU", "PBAR5 SZ (log2)"); + + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar23_sz", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_8 | NTB_PCI_REG | XEON_SBAR23SZ_OFFSET, + sysctl_handle_register, "CU", "SBAR23 SZ (log2)"); + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar4_sz", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_8 | NTB_PCI_REG | XEON_SBAR4SZ_OFFSET, + sysctl_handle_register, "CU", "SBAR4 SZ (log2)"); + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar5_sz", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_8 | NTB_PCI_REG | XEON_SBAR5SZ_OFFSET, + sysctl_handle_register, "CU", "SBAR5 SZ (log2)"); + + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "devsts", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_16 | NTB_PCI_REG | XEON_DEVSTS_OFFSET, + sysctl_handle_register, "SU", "DEVSTS"); + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnksts", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_16 | NTB_PCI_REG | XEON_LINK_STATUS_OFFSET, + sysctl_handle_register, "SU", "LNKSTS"); + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "slnksts", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_16 | NTB_PCI_REG | XEON_SLINK_STATUS_OFFSET, + sysctl_handle_register, "SU", "SLNKSTS"); + + SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "uncerrsts", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_32 | NTB_PCI_REG | XEON_UNCERRSTS_OFFSET, + sysctl_handle_register, "IU", "UNCERRSTS"); + SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "corerrsts", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_32 | NTB_PCI_REG | XEON_CORERRSTS_OFFSET, + sysctl_handle_register, "IU", "CORERRSTS"); + + if (ntb->conn_type != NTB_CONN_B2B) + return; + + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat23", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_64 | ntb->bar_info[NTB_B2B_BAR_1].pbarxlat_off, + sysctl_handle_register, "QU", "Outgoing XLAT23 register"); + if (HAS_FEATURE(NTB_SPLIT_BAR)) { + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat4", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_32 | ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off, + sysctl_handle_register, "IU", "Outgoing XLAT4 register"); + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat5", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_32 | ntb->bar_info[NTB_B2B_BAR_3].pbarxlat_off, + sysctl_handle_register, "IU", "Outgoing XLAT5 register"); + } else { + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat45", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_64 | ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off, + sysctl_handle_register, "QU", "Outgoing XLAT45 register"); + } + + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt23", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_64 | XEON_PBAR2LMT_OFFSET, + sysctl_handle_register, "QU", "Outgoing LMT23 register"); + if (HAS_FEATURE(NTB_SPLIT_BAR)) { + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt4", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_32 | XEON_PBAR4LMT_OFFSET, + sysctl_handle_register, "IU", "Outgoing LMT4 register"); + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt5", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_32 | XEON_PBAR5LMT_OFFSET, + sysctl_handle_register, "IU", "Outgoing LMT5 register"); + } else { + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt45", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_64 | XEON_PBAR4LMT_OFFSET, + sysctl_handle_register, "QU", "Outgoing LMT45 register"); + } + + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar01_base", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_64 | ntb->xlat_reg->bar0_base, + sysctl_handle_register, "QU", "Secondary BAR01 base register"); + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar23_base", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_64 | ntb->xlat_reg->bar2_base, + sysctl_handle_register, "QU", "Secondary BAR23 base register"); + if (HAS_FEATURE(NTB_SPLIT_BAR)) { + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar4_base", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_32 | ntb->xlat_reg->bar4_base, + sysctl_handle_register, "IU", + "Secondary BAR4 base register"); + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar5_base", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_32 | ntb->xlat_reg->bar5_base, + sysctl_handle_register, "IU", + "Secondary BAR5 base register"); + } else { + SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar45_base", + CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, + NTB_REG_64 | ntb->xlat_reg->bar4_base, + sysctl_handle_register, "QU", + "Secondary BAR45 base register"); + } } -/** - * ntb_find_transport() - find the transport pointer - * @transport: pointer to pci device - * - * Given the pci device pointer, return the transport pointer passed in when - * the transport attached when it was inited. - * - * RETURNS: pointer to transport. - */ -void * -ntb_find_transport(struct ntb_softc *ntb) +static int +sysctl_handle_features(SYSCTL_HANDLER_ARGS) { + struct ntb_softc *ntb; + struct sbuf sb; + int error; - return (ntb->ntb_transport); + error = 0; + ntb = arg1; + + sbuf_new_for_sysctl(&sb, NULL, 256, req); + + sbuf_printf(&sb, "%b", ntb->features, NTB_FEATURES_STR); + error = sbuf_finish(&sb); + sbuf_delete(&sb); + + if (error || !req->newptr) + return (error); + return (EINVAL); } -/** - * ntb_register_transport() - Register NTB transport with NTB HW driver - * @transport: transport identifier - * - * This function allows a transport to reserve the hardware driver for - * NTB usage. - * - * RETURNS: pointer to ntb_softc, NULL on error. - */ -struct ntb_softc * -ntb_register_transport(struct ntb_softc *ntb, void *transport) +static int +sysctl_handle_link_status(SYSCTL_HANDLER_ARGS) { + struct ntb_softc *ntb; + struct sbuf sb; + enum ntb_speed speed; + enum ntb_width width; + int error; - /* - * TODO: when we have more than one transport, we will need to rewrite - * this to prevent race conditions - */ - if (ntb->ntb_transport != NULL) - return (NULL); + error = 0; + ntb = arg1; - ntb->ntb_transport = transport; - return (ntb); + sbuf_new_for_sysctl(&sb, NULL, 32, req); + + if (ntb_link_is_up(ntb, &speed, &width)) + sbuf_printf(&sb, "up / PCIe Gen %u / Width x%u", + (unsigned)speed, (unsigned)width); + else + sbuf_printf(&sb, "down"); + + error = sbuf_finish(&sb); + sbuf_delete(&sb); + + if (error || !req->newptr) + return (error); + return (EINVAL); } -/** - * ntb_unregister_transport() - Unregister the transport with the NTB HW driver - * @ntb - ntb_softc of the transport to be freed - * - * This function unregisters the transport from the HW driver and performs any - * necessary cleanups. - */ -void -ntb_unregister_transport(struct ntb_softc *ntb) +static int +sysctl_handle_register(SYSCTL_HANDLER_ARGS) { - int i; + struct ntb_softc *ntb; + const void *outp; + uintptr_t sz; + uint64_t umv; + char be[sizeof(umv)]; + size_t outsz; + uint32_t reg; + bool db, pci; + int error; - if (ntb->ntb_transport == NULL) - return; + ntb = arg1; + reg = arg2 & ~NTB_REGFLAGS_MASK; + sz = arg2 & NTB_REGSZ_MASK; + db = (arg2 & NTB_DB_READ) != 0; + pci = (arg2 & NTB_PCI_REG) != 0; - for (i = 0; i < ntb->allocated_interrupts; i++) - ntb_unregister_db_callback(ntb, i); + KASSERT(!(db && pci), ("bogus")); - ntb_unregister_event_callback(ntb); - ntb->ntb_transport = NULL; + if (db) { + KASSERT(sz == NTB_REG_64, ("bogus")); + umv = db_ioread(ntb, reg); + outsz = sizeof(uint64_t); + } else { + switch (sz) { + case NTB_REG_64: + if (pci) + umv = pci_read_config(ntb->device, reg, 8); + else + umv = ntb_reg_read(8, reg); + outsz = sizeof(uint64_t); + break; + case NTB_REG_32: + if (pci) + umv = pci_read_config(ntb->device, reg, 4); + else + umv = ntb_reg_read(4, reg); + outsz = sizeof(uint32_t); + break; + case NTB_REG_16: + if (pci) + umv = pci_read_config(ntb->device, reg, 2); + else + umv = ntb_reg_read(2, reg); + outsz = sizeof(uint16_t); + break; + case NTB_REG_8: + if (pci) + umv = pci_read_config(ntb->device, reg, 1); + else + umv = ntb_reg_read(1, reg); + outsz = sizeof(uint8_t); + break; + default: + panic("bogus"); + break; + } + } + + /* Encode bigendian so that sysctl -x is legible. */ + be64enc(be, umv); + outp = ((char *)be) + sizeof(umv) - outsz; + + error = SYSCTL_OUT(req, outp, outsz); + if (error || !req->newptr) + return (error); + return (EINVAL); } +static unsigned +ntb_user_mw_to_idx(struct ntb_softc *ntb, unsigned uidx) +{ + + if (ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0 && + uidx >= ntb->b2b_mw_idx) + return (uidx + 1); + return (uidx); +} + +/* + * Public API to the rest of the OS + */ + /** * ntb_get_max_spads() - get the total scratch regs usable * @ntb: pointer to ntb_softc instance * * This function returns the max 32bit scratchpad registers usable by the * upper layer. * * RETURNS: total number of scratch pad registers available */ -int +uint8_t ntb_get_max_spads(struct ntb_softc *ntb) { - return (ntb->limits.max_spads); + return (ntb->spad_count); } +/* + * ntb_mw_count() - Get the number of memory windows available for KPI + * consumers. + * + * (Excludes any MW wholly reserved for register access.) + */ +uint8_t +ntb_mw_count(struct ntb_softc *ntb) +{ + + if (ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0) + return (ntb->mw_count - 1); + return (ntb->mw_count); +} + /** - * ntb_write_local_spad() - write to the secondary scratchpad register + * ntb_spad_write() - write to the secondary scratchpad register * @ntb: pointer to ntb_softc instance * @idx: index to the scratchpad register, 0 based * @val: the data value to put into the register * * This function allows writing of a 32bit value to the indexed scratchpad * register. The register resides on the secondary (external) side. * - * RETURNS: An appropriate -ERRNO error value on error, or zero for success. + * RETURNS: An appropriate ERRNO error value on error, or zero for success. */ int -ntb_write_local_spad(struct ntb_softc *ntb, unsigned int idx, uint32_t val) +ntb_spad_write(struct ntb_softc *ntb, unsigned int idx, uint32_t val) { - if (idx >= ntb->limits.max_spads) + if (idx >= ntb->spad_count) return (EINVAL); - ntb_reg_write(4, ntb->reg_ofs.spad_local + idx * 4, val); + ntb_reg_write(4, ntb->self_reg->spad + idx * 4, val); return (0); } /** - * ntb_read_local_spad() - read from the primary scratchpad register + * ntb_spad_read() - read from the primary scratchpad register * @ntb: pointer to ntb_softc instance * @idx: index to scratchpad register, 0 based * @val: pointer to 32bit integer for storing the register value * * This function allows reading of the 32bit scratchpad register on * the primary (internal) side. * - * RETURNS: An appropriate -ERRNO error value on error, or zero for success. + * RETURNS: An appropriate ERRNO error value on error, or zero for success. */ int -ntb_read_local_spad(struct ntb_softc *ntb, unsigned int idx, uint32_t *val) +ntb_spad_read(struct ntb_softc *ntb, unsigned int idx, uint32_t *val) { - if (idx >= ntb->limits.max_spads) + if (idx >= ntb->spad_count) return (EINVAL); - *val = ntb_reg_read(4, ntb->reg_ofs.spad_local + idx * 4); + *val = ntb_reg_read(4, ntb->self_reg->spad + idx * 4); return (0); } /** - * ntb_write_remote_spad() - write to the secondary scratchpad register + * ntb_peer_spad_write() - write to the secondary scratchpad register * @ntb: pointer to ntb_softc instance * @idx: index to the scratchpad register, 0 based * @val: the data value to put into the register * * This function allows writing of a 32bit value to the indexed scratchpad * register. The register resides on the secondary (external) side. * - * RETURNS: An appropriate -ERRNO error value on error, or zero for success. + * RETURNS: An appropriate ERRNO error value on error, or zero for success. */ int -ntb_write_remote_spad(struct ntb_softc *ntb, unsigned int idx, uint32_t val) +ntb_peer_spad_write(struct ntb_softc *ntb, unsigned int idx, uint32_t val) { - if (idx >= ntb->limits.max_spads) + if (idx >= ntb->spad_count) return (EINVAL); - if (HAS_FEATURE(NTB_REGS_THRU_MW)) - ntb_mw_write(4, XEON_SHADOW_SPAD_OFFSET + idx * 4, val); + if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) + ntb_mw_write(4, XEON_SPAD_OFFSET + idx * 4, val); else - ntb_reg_write(4, ntb->reg_ofs.spad_remote + idx * 4, val); + ntb_reg_write(4, ntb->peer_reg->spad + idx * 4, val); return (0); } /** - * ntb_read_remote_spad() - read from the primary scratchpad register + * ntb_peer_spad_read() - read from the primary scratchpad register * @ntb: pointer to ntb_softc instance * @idx: index to scratchpad register, 0 based * @val: pointer to 32bit integer for storing the register value * * This function allows reading of the 32bit scratchpad register on * the primary (internal) side. * - * RETURNS: An appropriate -ERRNO error value on error, or zero for success. + * RETURNS: An appropriate ERRNO error value on error, or zero for success. */ int -ntb_read_remote_spad(struct ntb_softc *ntb, unsigned int idx, uint32_t *val) +ntb_peer_spad_read(struct ntb_softc *ntb, unsigned int idx, uint32_t *val) { - if (idx >= ntb->limits.max_spads) + if (idx >= ntb->spad_count) return (EINVAL); - if (HAS_FEATURE(NTB_REGS_THRU_MW)) - *val = ntb_mw_read(4, XEON_SHADOW_SPAD_OFFSET + idx * 4); + if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) + *val = ntb_mw_read(4, XEON_SPAD_OFFSET + idx * 4); else - *val = ntb_reg_read(4, ntb->reg_ofs.spad_remote + idx * 4); + *val = ntb_reg_read(4, ntb->peer_reg->spad + idx * 4); return (0); } -/** - * ntb_get_mw_vbase() - get virtual addr for the NTB memory window - * @ntb: pointer to ntb_softc instance - * @mw: memory window number +/* + * ntb_mw_get_range() - get the range of a memory window + * @ntb: NTB device context + * @idx: Memory window number + * @base: OUT - the base address for mapping the memory window + * @size: OUT - the size for mapping the memory window + * @align: OUT - the base alignment for translating the memory window + * @align_size: OUT - the size alignment for translating the memory window * - * This function provides the base virtual address of the memory window - * specified. + * Get the range of a memory window. NULL may be given for any output + * parameter if the value is not needed. The base and size may be used for + * mapping the memory window, to access the peer memory. The alignment and + * size may be used for translating the memory window, for the peer to access + * memory on the local system. * - * RETURNS: pointer to virtual address, or NULL on error. + * Return: Zero on success, otherwise an error number. */ -void * -ntb_get_mw_vbase(struct ntb_softc *ntb, unsigned int mw) +int +ntb_mw_get_range(struct ntb_softc *ntb, unsigned mw_idx, vm_paddr_t *base, + caddr_t *vbase, size_t *size, size_t *align, size_t *align_size, + bus_addr_t *plimit) { + struct ntb_pci_bar_info *bar; + bus_addr_t limit; + size_t bar_b2b_off; + enum ntb_bar bar_num; - if (mw >= NTB_NUM_MW) - return (NULL); + if (mw_idx >= ntb_mw_count(ntb)) + return (EINVAL); + mw_idx = ntb_user_mw_to_idx(ntb, mw_idx); - return (ntb->bar_info[NTB_MW_TO_BAR(mw)].vbase); + bar_num = ntb_mw_to_bar(ntb, mw_idx); + bar = &ntb->bar_info[bar_num]; + bar_b2b_off = 0; + if (mw_idx == ntb->b2b_mw_idx) { + KASSERT(ntb->b2b_off != 0, + ("user shouldn't get non-shared b2b mw")); + bar_b2b_off = ntb->b2b_off; + } + + if (bar_is_64bit(ntb, bar_num)) + limit = BUS_SPACE_MAXADDR; + else + limit = BUS_SPACE_MAXADDR_32BIT; + + if (base != NULL) + *base = bar->pbase + bar_b2b_off; + if (vbase != NULL) + *vbase = bar->vbase + bar_b2b_off; + if (size != NULL) + *size = bar->size - bar_b2b_off; + if (align != NULL) + *align = bar->size; + if (align_size != NULL) + *align_size = 1; + if (plimit != NULL) + *plimit = limit; + return (0); } -vm_paddr_t -ntb_get_mw_pbase(struct ntb_softc *ntb, unsigned int mw) +/* + * ntb_mw_set_trans() - set the translation of a memory window + * @ntb: NTB device context + * @idx: Memory window number + * @addr: The dma address local memory to expose to the peer + * @size: The size of the local memory to expose to the peer + * + * Set the translation of a memory window. The peer may access local memory + * through the window starting at the address, up to the size. The address + * must be aligned to the alignment specified by ntb_mw_get_range(). The size + * must be aligned to the size alignment specified by ntb_mw_get_range(). The + * address must be below the plimit specified by ntb_mw_get_range() (i.e. for + * 32-bit BARs). + * + * Return: Zero on success, otherwise an error number. + */ +int +ntb_mw_set_trans(struct ntb_softc *ntb, unsigned idx, bus_addr_t addr, + size_t size) { + struct ntb_pci_bar_info *bar; + uint64_t base, limit, reg_val; + size_t bar_size, mw_size; + uint32_t base_reg, xlat_reg, limit_reg; + enum ntb_bar bar_num; - if (mw >= NTB_NUM_MW) - return (0); + if (idx >= ntb_mw_count(ntb)) + return (EINVAL); + idx = ntb_user_mw_to_idx(ntb, idx); - return (ntb->bar_info[NTB_MW_TO_BAR(mw)].pbase); + bar_num = ntb_mw_to_bar(ntb, idx); + bar = &ntb->bar_info[bar_num]; + + bar_size = bar->size; + if (idx == ntb->b2b_mw_idx) + mw_size = bar_size - ntb->b2b_off; + else + mw_size = bar_size; + + /* Hardware requires that addr is aligned to bar size */ + if ((addr & (bar_size - 1)) != 0) + return (EINVAL); + + if (size > mw_size) + return (EINVAL); + + bar_get_xlat_params(ntb, bar_num, &base_reg, &xlat_reg, &limit_reg); + + limit = 0; + if (bar_is_64bit(ntb, bar_num)) { + base = ntb_reg_read(8, base_reg) & BAR_HIGH_MASK; + + if (limit_reg != 0 && size != mw_size) + limit = base + size; + + /* Set and verify translation address */ + ntb_reg_write(8, xlat_reg, addr); + reg_val = ntb_reg_read(8, xlat_reg) & BAR_HIGH_MASK; + if (reg_val != addr) { + ntb_reg_write(8, xlat_reg, 0); + return (EIO); + } + + /* Set and verify the limit */ + ntb_reg_write(8, limit_reg, limit); + reg_val = ntb_reg_read(8, limit_reg) & BAR_HIGH_MASK; + if (reg_val != limit) { + ntb_reg_write(8, limit_reg, base); + ntb_reg_write(8, xlat_reg, 0); + return (EIO); + } + } else { + /* Configure 32-bit (split) BAR MW */ + + if ((addr & UINT32_MAX) != addr) + return (ERANGE); + if (((addr + size) & UINT32_MAX) != (addr + size)) + return (ERANGE); + + base = ntb_reg_read(4, base_reg) & BAR_HIGH_MASK; + + if (limit_reg != 0 && size != mw_size) + limit = base + size; + + /* Set and verify translation address */ + ntb_reg_write(4, xlat_reg, addr); + reg_val = ntb_reg_read(4, xlat_reg) & BAR_HIGH_MASK; + if (reg_val != addr) { + ntb_reg_write(4, xlat_reg, 0); + return (EIO); + } + + /* Set and verify the limit */ + ntb_reg_write(4, limit_reg, limit); + reg_val = ntb_reg_read(4, limit_reg) & BAR_HIGH_MASK; + if (reg_val != limit) { + ntb_reg_write(4, limit_reg, base); + ntb_reg_write(4, xlat_reg, 0); + return (EIO); + } + } + return (0); } -/** - * ntb_get_mw_size() - return size of NTB memory window - * @ntb: pointer to ntb_softc instance - * @mw: memory window number +/* + * ntb_mw_clear_trans() - clear the translation of a memory window + * @ntb: NTB device context + * @idx: Memory window number * - * This function provides the physical size of the memory window specified + * Clear the translation of a memory window. The peer may no longer access + * local memory through the window. * - * RETURNS: the size of the memory window or zero on error + * Return: Zero on success, otherwise an error number. */ -u_long -ntb_get_mw_size(struct ntb_softc *ntb, unsigned int mw) +int +ntb_mw_clear_trans(struct ntb_softc *ntb, unsigned mw_idx) { - if (mw >= NTB_NUM_MW) + return (ntb_mw_set_trans(ntb, mw_idx, 0, 0)); +} + +/* + * ntb_mw_get_wc - Get the write-combine status of a memory window + * + * Returns: Zero on success, setting *wc; otherwise an error number (e.g. if + * idx is an invalid memory window). + * + * Mode is a VM_MEMATTR_* type. + */ +int +ntb_mw_get_wc(struct ntb_softc *ntb, unsigned idx, vm_memattr_t *mode) +{ + struct ntb_pci_bar_info *bar; + + if (idx >= ntb_mw_count(ntb)) + return (EINVAL); + idx = ntb_user_mw_to_idx(ntb, idx); + + bar = &ntb->bar_info[ntb_mw_to_bar(ntb, idx)]; + *mode = bar->map_mode; + return (0); +} + +/* + * ntb_mw_set_wc - Set the write-combine status of a memory window + * + * If 'mode' matches the current status, this does nothing and succeeds. Mode + * is a VM_MEMATTR_* type. + * + * Returns: Zero on success, setting the caching attribute on the virtual + * mapping of the BAR; otherwise an error number (e.g. if idx is an invalid + * memory window, or if changing the caching attribute fails). + */ +int +ntb_mw_set_wc(struct ntb_softc *ntb, unsigned idx, vm_memattr_t mode) +{ + + if (idx >= ntb_mw_count(ntb)) + return (EINVAL); + + idx = ntb_user_mw_to_idx(ntb, idx); + return (ntb_mw_set_wc_internal(ntb, idx, mode)); +} + +static int +ntb_mw_set_wc_internal(struct ntb_softc *ntb, unsigned idx, vm_memattr_t mode) +{ + struct ntb_pci_bar_info *bar; + int rc; + + bar = &ntb->bar_info[ntb_mw_to_bar(ntb, idx)]; + if (bar->map_mode == mode) return (0); - return (ntb->bar_info[NTB_MW_TO_BAR(mw)].size); + rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, mode); + if (rc == 0) + bar->map_mode = mode; + + return (rc); } /** - * ntb_set_mw_addr - set the memory window address + * ntb_peer_db_set() - Set the doorbell on the secondary/external side * @ntb: pointer to ntb_softc instance - * @mw: memory window number - * @addr: base address for data + * @bit: doorbell bits to ring * - * This function sets the base physical address of the memory window. This - * memory address is where data from the remote system will be transfered into - * or out of depending on how the transport is configured. + * This function allows triggering of a doorbell on the secondary/external + * side that will initiate an interrupt on the remote host */ void -ntb_set_mw_addr(struct ntb_softc *ntb, unsigned int mw, uint64_t addr) +ntb_peer_db_set(struct ntb_softc *ntb, uint64_t bit) { - if (mw >= NTB_NUM_MW) + if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) { + ntb_mw_write(2, XEON_PDOORBELL_OFFSET, bit); return; + } - switch (NTB_MW_TO_BAR(mw)) { - case NTB_B2B_BAR_1: - ntb_reg_write(8, ntb->reg_ofs.sbar2_xlat, addr); - break; - case NTB_B2B_BAR_2: - ntb_reg_write(8, ntb->reg_ofs.sbar4_xlat, addr); - break; + db_iowrite(ntb, ntb->peer_reg->db_bell, bit); +} + +/* + * ntb_get_peer_db_addr() - Return the address of the remote doorbell register, + * as well as the size of the register (via *sz_out). + * + * This function allows a caller using I/OAT DMA to chain the remote doorbell + * ring to its memory window write. + * + * Note that writing the peer doorbell via a memory window will *not* generate + * an interrupt on the remote host; that must be done seperately. + */ +bus_addr_t +ntb_get_peer_db_addr(struct ntb_softc *ntb, vm_size_t *sz_out) +{ + struct ntb_pci_bar_info *bar; + uint64_t regoff; + + KASSERT(sz_out != NULL, ("must be non-NULL")); + + if (!HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) { + bar = &ntb->bar_info[NTB_CONFIG_BAR]; + regoff = ntb->peer_reg->db_bell; + } else { + KASSERT(ntb->b2b_mw_idx != B2B_MW_DISABLED, + ("invalid b2b idx")); + + bar = &ntb->bar_info[ntb_mw_to_bar(ntb, ntb->b2b_mw_idx)]; + regoff = XEON_PDOORBELL_OFFSET; } + KASSERT(bar->pci_bus_tag != X86_BUS_SPACE_IO, ("uh oh")); + + *sz_out = ntb->reg->db_size; + /* HACK: Specific to current x86 bus implementation. */ + return ((uint64_t)bar->pci_bus_handle + regoff); } -/** - * ntb_ring_sdb() - Set the doorbell on the secondary/external side - * @ntb: pointer to ntb_softc instance - * @db: doorbell to ring +/* + * ntb_db_valid_mask() - get a mask of doorbell bits supported by the ntb + * @ntb: NTB device context * - * This function allows triggering of a doorbell on the secondary/external - * side that will initiate an interrupt on the remote host + * Hardware may support different number or arrangement of doorbell bits. * - * RETURNS: An appropriate -ERRNO error value on error, or zero for success. + * Return: A mask of doorbell bits supported by the ntb. */ -void -ntb_ring_sdb(struct ntb_softc *ntb, unsigned int db) +uint64_t +ntb_db_valid_mask(struct ntb_softc *ntb) { - if (ntb->type == NTB_SOC) - ntb_reg_write(8, ntb->reg_ofs.sdb, (uint64_t) 1 << db); - else - if (HAS_FEATURE(NTB_REGS_THRU_MW)) - ntb_mw_write(2, XEON_SHADOW_PDOORBELL_OFFSET, - ((1 << ntb->bits_per_vector) - 1) << - (db * ntb->bits_per_vector)); - else - ntb_reg_write(2, ntb->reg_ofs.sdb, - ((1 << ntb->bits_per_vector) - 1) << - (db * ntb->bits_per_vector)); + return (ntb->db_valid_mask); } -/** - * ntb_query_link_status() - return the hardware link status - * @ndev: pointer to ntb_device instance +/* + * ntb_db_vector_mask() - get a mask of doorbell bits serviced by a vector + * @ntb: NTB device context + * @vector: Doorbell vector number * - * Returns true if the hardware is connected to the remote system + * Each interrupt vector may have a different number or arrangement of bits. * + * Return: A mask of doorbell bits serviced by a vector. + */ +uint64_t +ntb_db_vector_mask(struct ntb_softc *ntb, uint32_t vector) +{ + + if (vector > ntb->db_vec_count) + return (0); + return (ntb->db_valid_mask & ntb_vec_mask(ntb, vector)); +} + +/** + * ntb_link_is_up() - get the current ntb link state + * @ntb: NTB device context + * @speed: OUT - The link speed expressed as PCIe generation number + * @width: OUT - The link width expressed as the number of PCIe lanes + * * RETURNS: true or false based on the hardware link state */ bool -ntb_query_link_status(struct ntb_softc *ntb) +ntb_link_is_up(struct ntb_softc *ntb, enum ntb_speed *speed, + enum ntb_width *width) { - return (ntb->link_status == NTB_LINK_UP); + if (speed != NULL) + *speed = ntb_link_sta_speed(ntb); + if (width != NULL) + *width = ntb_link_sta_width(ntb); + return (link_is_up(ntb)); } static void save_bar_parameters(struct ntb_pci_bar_info *bar) { - bar->pci_bus_tag = - rman_get_bustag(bar->pci_resource); - bar->pci_bus_handle = - rman_get_bushandle(bar->pci_resource); - bar->pbase = - rman_get_start(bar->pci_resource); - bar->size = - rman_get_size(bar->pci_resource); - bar->vbase = - rman_get_virtual(bar->pci_resource); + bar->pci_bus_tag = rman_get_bustag(bar->pci_resource); + bar->pci_bus_handle = rman_get_bushandle(bar->pci_resource); + bar->pbase = rman_get_start(bar->pci_resource); + bar->size = rman_get_size(bar->pci_resource); + bar->vbase = rman_get_virtual(bar->pci_resource); } -device_t ntb_get_device(struct ntb_softc *ntb) +device_t +ntb_get_device(struct ntb_softc *ntb) { return (ntb->device); +} + +/* Export HW-specific errata information. */ +bool +ntb_has_feature(struct ntb_softc *ntb, uint32_t feature) +{ + + return (HAS_FEATURE(feature)); } Index: stable/10/sys/dev/ntb/ntb_hw/ntb_hw.h =================================================================== --- stable/10/sys/dev/ntb/ntb_hw/ntb_hw.h (revision 300372) +++ stable/10/sys/dev/ntb/ntb_hw/ntb_hw.h (revision 300373) @@ -1,74 +1,123 @@ /*- * Copyright (C) 2013 Intel Corporation + * Copyright (C) 2015 EMC Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _NTB_HW_H_ #define _NTB_HW_H_ struct ntb_softc; -#define NTB_NUM_MW 2 -#define NTB_LINK_DOWN 0 -#define NTB_LINK_UP 1 +#define NTB_MAX_NUM_MW 3 -enum ntb_hw_event { - NTB_EVENT_SW_EVENT0 = 0, - NTB_EVENT_SW_EVENT1, - NTB_EVENT_SW_EVENT2, - NTB_EVENT_HW_ERROR, - NTB_EVENT_HW_LINK_UP, - NTB_EVENT_HW_LINK_DOWN, +enum ntb_speed { + NTB_SPEED_AUTO = -1, + NTB_SPEED_NONE = 0, + NTB_SPEED_GEN1 = 1, + NTB_SPEED_GEN2 = 2, + NTB_SPEED_GEN3 = 3, }; -typedef void (*ntb_db_callback)(void *data, int db_num); -typedef void (*ntb_event_callback)(void *data, enum ntb_hw_event event); +enum ntb_width { + NTB_WIDTH_AUTO = -1, + NTB_WIDTH_NONE = 0, + NTB_WIDTH_1 = 1, + NTB_WIDTH_2 = 2, + NTB_WIDTH_4 = 4, + NTB_WIDTH_8 = 8, + NTB_WIDTH_12 = 12, + NTB_WIDTH_16 = 16, + NTB_WIDTH_32 = 32, +}; -int ntb_register_event_callback(struct ntb_softc *ntb, ntb_event_callback func); -void ntb_unregister_event_callback(struct ntb_softc *ntb); -int ntb_register_db_callback(struct ntb_softc *ntb, unsigned int idx, - void *data, ntb_db_callback func); -void ntb_unregister_db_callback(struct ntb_softc *ntb, unsigned int idx); -void *ntb_find_transport(struct ntb_softc *ntb); -struct ntb_softc *ntb_register_transport(struct ntb_softc *ntb, - void *transport); -void ntb_unregister_transport(struct ntb_softc *ntb); -int ntb_get_max_spads(struct ntb_softc *ntb); -int ntb_write_local_spad(struct ntb_softc *ntb, unsigned int idx, uint32_t val); -int ntb_read_local_spad(struct ntb_softc *ntb, unsigned int idx, uint32_t *val); -int ntb_write_remote_spad(struct ntb_softc *ntb, unsigned int idx, +SYSCTL_DECL(_hw_ntb); + +typedef void (*ntb_db_callback)(void *data, uint32_t vector); +typedef void (*ntb_event_callback)(void *data); + +struct ntb_ctx_ops { + ntb_event_callback link_event; + ntb_db_callback db_event; +}; + +device_t ntb_get_device(struct ntb_softc *); + +bool ntb_link_is_up(struct ntb_softc *, enum ntb_speed *, enum ntb_width *); +void ntb_link_event(struct ntb_softc *); +int ntb_link_enable(struct ntb_softc *, enum ntb_speed, enum ntb_width); +int ntb_link_disable(struct ntb_softc *); + +int ntb_set_ctx(struct ntb_softc *, void *, const struct ntb_ctx_ops *); +void *ntb_get_ctx(struct ntb_softc *, const struct ntb_ctx_ops **); +void ntb_clear_ctx(struct ntb_softc *); + +uint8_t ntb_mw_count(struct ntb_softc *); +int ntb_mw_get_range(struct ntb_softc *, unsigned mw_idx, vm_paddr_t *base, + caddr_t *vbase, size_t *size, size_t *align, size_t *align_size, + bus_addr_t *plimit); +int ntb_mw_set_trans(struct ntb_softc *, unsigned mw_idx, bus_addr_t, size_t); +int ntb_mw_clear_trans(struct ntb_softc *, unsigned mw_idx); + +int ntb_mw_get_wc(struct ntb_softc *, unsigned mw_idx, vm_memattr_t *mode); +int ntb_mw_set_wc(struct ntb_softc *, unsigned mw_idx, vm_memattr_t mode); + +uint8_t ntb_get_max_spads(struct ntb_softc *ntb); +int ntb_spad_write(struct ntb_softc *ntb, unsigned int idx, uint32_t val); +int ntb_spad_read(struct ntb_softc *ntb, unsigned int idx, uint32_t *val); +int ntb_peer_spad_write(struct ntb_softc *ntb, unsigned int idx, uint32_t val); -int ntb_read_remote_spad(struct ntb_softc *ntb, unsigned int idx, +int ntb_peer_spad_read(struct ntb_softc *ntb, unsigned int idx, uint32_t *val); -void *ntb_get_mw_vbase(struct ntb_softc *ntb, unsigned int mw); -vm_paddr_t ntb_get_mw_pbase(struct ntb_softc *ntb, unsigned int mw); -u_long ntb_get_mw_size(struct ntb_softc *ntb, unsigned int mw); -void ntb_set_mw_addr(struct ntb_softc *ntb, unsigned int mw, uint64_t addr); -void ntb_ring_sdb(struct ntb_softc *ntb, unsigned int db); -bool ntb_query_link_status(struct ntb_softc *ntb); -device_t ntb_get_device(struct ntb_softc *ntb); + +uint64_t ntb_db_valid_mask(struct ntb_softc *); +uint64_t ntb_db_vector_mask(struct ntb_softc *, uint32_t vector); +bus_addr_t ntb_get_peer_db_addr(struct ntb_softc *, vm_size_t *sz_out); + +void ntb_db_clear(struct ntb_softc *, uint64_t bits); +void ntb_db_clear_mask(struct ntb_softc *, uint64_t bits); +uint64_t ntb_db_read(struct ntb_softc *); +void ntb_db_set_mask(struct ntb_softc *, uint64_t bits); +void ntb_peer_db_set(struct ntb_softc *, uint64_t bits); + +#define XEON_SPAD_COUNT 16 +#define ATOM_SPAD_COUNT 16 + +/* Hardware owns the low 16 bits of features. */ +#define NTB_BAR_SIZE_4K (1 << 0) +#define NTB_SDOORBELL_LOCKUP (1 << 1) +#define NTB_SB01BASE_LOCKUP (1 << 2) +#define NTB_B2BDOORBELL_BIT14 (1 << 3) +/* Software/configuration owns the top 16 bits. */ +#define NTB_SPLIT_BAR (1ull << 16) + +#define NTB_FEATURES_STR \ + "\20\21SPLIT_BAR4\04B2B_DOORBELL_BIT14\03SB01BASE_LOCKUP" \ + "\02SDOORBELL_LOCKUP\01BAR_SIZE_4K" + +bool ntb_has_feature(struct ntb_softc *, uint32_t); #endif /* _NTB_HW_H_ */ Index: stable/10/sys/dev/ntb/ntb_hw/ntb_regs.h =================================================================== --- stable/10/sys/dev/ntb/ntb_hw/ntb_regs.h (revision 300372) +++ stable/10/sys/dev/ntb/ntb_hw/ntb_regs.h (revision 300373) @@ -1,154 +1,164 @@ /*- * Copyright (C) 2013 Intel Corporation + * Copyright (C) 2015 EMC Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _NTB_REGS_H_ #define _NTB_REGS_H_ -#define NTB_LINK_ENABLE 0x0000 -#define NTB_LINK_DISABLE 0x0002 #define NTB_LINK_STATUS_ACTIVE 0x2000 #define NTB_LINK_SPEED_MASK 0x000f #define NTB_LINK_WIDTH_MASK 0x03f0 +#define NTB_LNK_STA_WIDTH(sta) (((sta) & NTB_LINK_WIDTH_MASK) >> 4) -#define XEON_MSIX_CNT 4 -#define XEON_MAX_SPADS 16 -#define XEON_MAX_COMPAT_SPADS 8 +#define XEON_SNB_MW_COUNT 2 +#define XEON_HSX_SPLIT_MW_COUNT 3 /* Reserve the uppermost bit for link interrupt */ -#define XEON_MAX_DB_BITS 15 -#define XEON_DB_BITS_PER_VEC 5 +#define XEON_DB_COUNT 15 +#define XEON_DB_TOTAL_SHIFT 16 +#define XEON_DB_LINK 15 +#define XEON_DB_MSIX_VECTOR_COUNT 4 +#define XEON_DB_MSIX_VECTOR_SHIFT 5 +#define XEON_DB_LINK_BIT (1 << XEON_DB_LINK) -#define XEON_DB_HW_LINK 0x8000 - -#define XEON_PCICMD_OFFSET 0x0504 +#define XEON_SPCICMD_OFFSET 0x0504 #define XEON_DEVCTRL_OFFSET 0x0598 +#define XEON_DEVSTS_OFFSET 0x059a #define XEON_LINK_STATUS_OFFSET 0x01a2 +#define XEON_SLINK_STATUS_OFFSET 0x05a2 #define XEON_PBAR2LMT_OFFSET 0x0000 #define XEON_PBAR4LMT_OFFSET 0x0008 +#define XEON_PBAR5LMT_OFFSET 0x000c #define XEON_PBAR2XLAT_OFFSET 0x0010 #define XEON_PBAR4XLAT_OFFSET 0x0018 +#define XEON_PBAR5XLAT_OFFSET 0x001c #define XEON_SBAR2LMT_OFFSET 0x0020 #define XEON_SBAR4LMT_OFFSET 0x0028 +#define XEON_SBAR5LMT_OFFSET 0x002c #define XEON_SBAR2XLAT_OFFSET 0x0030 #define XEON_SBAR4XLAT_OFFSET 0x0038 +#define XEON_SBAR5XLAT_OFFSET 0x003c #define XEON_SBAR0BASE_OFFSET 0x0040 #define XEON_SBAR2BASE_OFFSET 0x0048 #define XEON_SBAR4BASE_OFFSET 0x0050 +#define XEON_SBAR5BASE_OFFSET 0x0054 #define XEON_NTBCNTL_OFFSET 0x0058 #define XEON_SBDF_OFFSET 0x005c #define XEON_PDOORBELL_OFFSET 0x0060 #define XEON_PDBMSK_OFFSET 0x0062 #define XEON_SDOORBELL_OFFSET 0x0064 #define XEON_SDBMSK_OFFSET 0x0066 -#define XEON_USMEMMISS 0x0070 +#define XEON_USMEMMISS_OFFSET 0x0070 #define XEON_SPAD_OFFSET 0x0080 #define XEON_SPADSEMA4_OFFSET 0x00c0 #define XEON_WCCNTRL_OFFSET 0x00e0 +#define XEON_UNCERRSTS_OFFSET 0x014c +#define XEON_CORERRSTS_OFFSET 0x0158 #define XEON_B2B_SPAD_OFFSET 0x0100 #define XEON_B2B_DOORBELL_OFFSET 0x0140 -#define XEON_B2B_XLAT_OFFSET 0x0144 +#define XEON_B2B_XLAT_OFFSETL 0x0144 +#define XEON_B2B_XLAT_OFFSETU 0x0148 -#define SOC_MSIX_CNT 34 -#define SOC_MAX_SPADS 16 -#define SOC_MAX_COMPAT_SPADS 16 -#define SOC_MAX_DB_BITS 34 -#define SOC_DB_BITS_PER_VEC 1 +#define ATOM_MW_COUNT 2 +#define ATOM_DB_COUNT 34 +#define ATOM_DB_MSIX_VECTOR_COUNT 34 +#define ATOM_DB_MSIX_VECTOR_SHIFT 1 -#define SOC_PCICMD_OFFSET 0xb004 -#define SOC_MBAR23_OFFSET 0xb018 -#define SOC_MBAR45_OFFSET 0xb020 -#define SOC_DEVCTRL_OFFSET 0xb048 -#define SOC_LINK_STATUS_OFFSET 0xb052 -#define SOC_ERRCORSTS_OFFSET 0xb110 +#define ATOM_SPCICMD_OFFSET 0xb004 +#define ATOM_MBAR23_OFFSET 0xb018 +#define ATOM_MBAR45_OFFSET 0xb020 +#define ATOM_DEVCTRL_OFFSET 0xb048 +#define ATOM_LINK_STATUS_OFFSET 0xb052 +#define ATOM_ERRCORSTS_OFFSET 0xb110 -#define SOC_SBAR2XLAT_OFFSET 0x0008 -#define SOC_SBAR4XLAT_OFFSET 0x0010 -#define SOC_PDOORBELL_OFFSET 0x0020 -#define SOC_PDBMSK_OFFSET 0x0028 -#define SOC_NTBCNTL_OFFSET 0x0060 -#define SOC_EBDF_OFFSET 0x0064 -#define SOC_SPAD_OFFSET 0x0080 -#define SOC_SPADSEMA_OFFSET 0x00c0 -#define SOC_STKYSPAD_OFFSET 0x00c4 -#define SOC_PBAR2XLAT_OFFSET 0x8008 -#define SOC_PBAR4XLAT_OFFSET 0x8010 -#define SOC_B2B_DOORBELL_OFFSET 0x8020 -#define SOC_B2B_SPAD_OFFSET 0x8080 -#define SOC_B2B_SPADSEMA_OFFSET 0x80c0 -#define SOC_B2B_STKYSPAD_OFFSET 0x80c4 +#define ATOM_SBAR2XLAT_OFFSET 0x0008 +#define ATOM_SBAR4XLAT_OFFSET 0x0010 +#define ATOM_PDOORBELL_OFFSET 0x0020 +#define ATOM_PDBMSK_OFFSET 0x0028 +#define ATOM_NTBCNTL_OFFSET 0x0060 +#define ATOM_EBDF_OFFSET 0x0064 +#define ATOM_SPAD_OFFSET 0x0080 +#define ATOM_SPADSEMA_OFFSET 0x00c0 +#define ATOM_STKYSPAD_OFFSET 0x00c4 +#define ATOM_PBAR2XLAT_OFFSET 0x8008 +#define ATOM_PBAR4XLAT_OFFSET 0x8010 +#define ATOM_B2B_DOORBELL_OFFSET 0x8020 +#define ATOM_B2B_SPAD_OFFSET 0x8080 +#define ATOM_B2B_SPADSEMA_OFFSET 0x80c0 +#define ATOM_B2B_STKYSPAD_OFFSET 0x80c4 -#define SOC_MODPHY_PCSREG4 0x1c004 -#define SOC_MODPHY_PCSREG6 0x1c006 +#define ATOM_MODPHY_PCSREG4 0x1c004 +#define ATOM_MODPHY_PCSREG6 0x1c006 -#define SOC_IP_BASE 0xc000 -#define SOC_DESKEWSTS_OFFSET (SOC_IP_BASE + 0x3024) -#define SOC_LTSSMERRSTS0_OFFSET (SOC_IP_BASE + 0x3180) -#define SOC_LTSSMSTATEJMP_OFFSET (SOC_IP_BASE + 0x3040) -#define SOC_IBSTERRRCRVSTS0_OFFSET (SOC_IP_BASE + 0x3324) +#define ATOM_IP_BASE 0xc000 +#define ATOM_DESKEWSTS_OFFSET (ATOM_IP_BASE + 0x3024) +#define ATOM_LTSSMERRSTS0_OFFSET (ATOM_IP_BASE + 0x3180) +#define ATOM_LTSSMSTATEJMP_OFFSET (ATOM_IP_BASE + 0x3040) +#define ATOM_IBSTERRRCRVSTS0_OFFSET (ATOM_IP_BASE + 0x3324) -#define SOC_DESKEWSTS_DBERR (1 << 15) -#define SOC_LTSSMERRSTS0_UNEXPECTEDEI (1 << 20) -#define SOC_LTSSMSTATEJMP_FORCEDETECT (1 << 2) -#define SOC_IBIST_ERR_OFLOW 0x7fff7fff +#define ATOM_DESKEWSTS_DBERR (1 << 15) +#define ATOM_LTSSMERRSTS0_UNEXPECTEDEI (1 << 20) +#define ATOM_LTSSMSTATEJMP_FORCEDETECT (1 << 2) +#define ATOM_IBIST_ERR_OFLOW 0x7fff7fff -#define NTB_CNTL_BAR23_SNOOP (1 << 2) -#define NTB_CNTL_BAR45_SNOOP (1 << 6) -#define SOC_CNTL_LINK_DOWN (1 << 16) +#define NTB_CNTL_CFG_LOCK (1 << 0) +#define NTB_CNTL_LINK_DISABLE (1 << 1) +#define NTB_CNTL_S2P_BAR23_SNOOP (1 << 2) +#define NTB_CNTL_P2S_BAR23_SNOOP (1 << 4) +#define NTB_CNTL_S2P_BAR4_SNOOP (1 << 6) +#define NTB_CNTL_P2S_BAR4_SNOOP (1 << 8) +#define NTB_CNTL_S2P_BAR5_SNOOP (1 << 12) +#define NTB_CNTL_P2S_BAR5_SNOOP (1 << 14) +#define ATOM_CNTL_LINK_DOWN (1 << 16) #define XEON_PBAR23SZ_OFFSET 0x00d0 #define XEON_PBAR45SZ_OFFSET 0x00d1 +#define XEON_PBAR4SZ_OFFSET 0x00d1 +#define XEON_PBAR5SZ_OFFSET 0x00d5 +#define XEON_SBAR23SZ_OFFSET 0x00d2 +#define XEON_SBAR4SZ_OFFSET 0x00d3 +#define XEON_SBAR5SZ_OFFSET 0x00d6 #define NTB_PPD_OFFSET 0x00d4 #define XEON_PPD_CONN_TYPE 0x0003 #define XEON_PPD_DEV_TYPE 0x0010 -#define SOC_PPD_INIT_LINK 0x0008 -#define SOC_PPD_CONN_TYPE 0x0300 -#define SOC_PPD_DEV_TYPE 0x1000 +#define XEON_PPD_SPLIT_BAR 0x0040 +#define ATOM_PPD_INIT_LINK 0x0008 +#define ATOM_PPD_CONN_TYPE 0x0300 +#define ATOM_PPD_DEV_TYPE 0x1000 -#define NTB_CONN_CLASSIC 0 -#define NTB_CONN_B2B 1 -#define NTB_CONN_RP 2 +/* All addresses are in low 32-bit space so 32-bit BARs can function */ +#define XEON_B2B_BAR0_ADDR 0x1000000000000000ull +#define XEON_B2B_BAR2_ADDR64 0x2000000000000000ull +#define XEON_B2B_BAR4_ADDR64 0x4000000000000000ull +#define XEON_B2B_BAR4_ADDR32 0x20000000ull +#define XEON_B2B_BAR5_ADDR32 0x40000000ull -#define NTB_DEV_DSD 1 -#define NTB_DEV_USD 0 - -#define PBAR2XLAT_USD_ADDR 0x0000004000000000 -#define PBAR4XLAT_USD_ADDR 0x0000008000000000 -#define MBAR01_USD_ADDR 0x000000210000000c -#define MBAR23_USD_ADDR 0x000000410000000c -#define MBAR45_USD_ADDR 0x000000810000000c -#define PBAR2XLAT_DSD_ADDR 0x0000004100000000 -#define PBAR4XLAT_DSD_ADDR 0x0000008100000000 -#define MBAR01_DSD_ADDR 0x000000200000000c -#define MBAR23_DSD_ADDR 0x000000400000000c -#define MBAR45_DSD_ADDR 0x000000800000000c - -/* XEON Shadowed MMIO Space */ -#define XEON_SHADOW_PDOORBELL_OFFSET 0x60 -#define XEON_SHADOW_SPAD_OFFSET 0x80 +/* The peer ntb secondary config space is 32KB fixed size */ +#define XEON_B2B_MIN_SIZE 0x8000 #endif /* _NTB_REGS_H_ */ Index: stable/10 =================================================================== --- stable/10 (revision 300372) +++ stable/10 (revision 300373) Property changes on: stable/10 ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head:r289152-289157,289205-289209,289232-289234,289255,289257,289259,289265-289266,289271-289274,289280-289281,289340-289348,289396-289397,289538-289546,289596-289598,289607-289617,289645-289654,289774-289775,290130,290158,290678-290688,290725,290810,291028-291034,291084-291085,291263,291280,291705-291706,295486-295487