Index: head/sys/conf/files.arm64 =================================================================== --- head/sys/conf/files.arm64 (revision 300293) +++ head/sys/conf/files.arm64 (revision 300294) @@ -1,103 +1,103 @@ # $FreeBSD$ arm/arm/generic_timer.c standard arm/arm/gic.c optional intrng arm/arm/pmu.c standard arm64/acpica/acpi_machdep.c optional acpi arm64/acpica/OsdEnvironment.c optional acpi arm64/acpica/acpi_wakeup.c optional acpi arm64/acpica/pci_cfgreg.c optional acpi pci arm64/arm64/autoconf.c standard arm64/arm64/bcopy.c standard arm64/arm64/bus_machdep.c standard arm64/arm64/bus_space_asm.S standard arm64/arm64/busdma_bounce.c standard arm64/arm64/busdma_machdep.c standard arm64/arm64/bzero.S standard arm64/arm64/clock.c standard arm64/arm64/copyinout.S standard arm64/arm64/copystr.c standard arm64/arm64/cpufunc_asm.S standard arm64/arm64/db_disasm.c optional ddb arm64/arm64/db_interface.c optional ddb arm64/arm64/db_trace.c optional ddb arm64/arm64/debug_monitor.c optional kdb arm64/arm64/disassem.c optional ddb arm64/arm64/dump_machdep.c standard arm64/arm64/elf_machdep.c standard arm64/arm64/exception.S standard arm64/arm64/gic.c optional !intrng arm64/arm64/gic_acpi.c optional !intrng acpi arm64/arm64/gic_fdt.c optional !intrng fdt arm64/arm64/gic_v3.c standard arm64/arm64/gic_v3_fdt.c optional fdt arm64/arm64/gic_v3_its.c optional !intrng arm64/arm64/identcpu.c standard arm64/arm64/intr_machdep.c optional !intrng arm64/arm64/in_cksum.c optional inet | inet6 arm64/arm64/locore.S standard no-obj arm64/arm64/machdep.c standard arm64/arm64/mem.c standard arm64/arm64/minidump_machdep.c standard arm64/arm64/mp_machdep.c optional smp arm64/arm64/nexus.c standard arm64/arm64/ofw_machdep.c optional fdt arm64/arm64/pic_if.m optional !intrng arm64/arm64/pmap.c standard arm64/arm64/stack_machdep.c optional ddb | stack arm64/arm64/support.S standard arm64/arm64/swtch.S standard arm64/arm64/sys_machdep.c standard arm64/arm64/trap.c standard arm64/arm64/uio_machdep.c standard arm64/arm64/uma_machdep.c standard arm64/arm64/unwind.c optional ddb | kdtrace_hooks | stack arm64/arm64/vfp.c standard arm64/arm64/vm_machdep.c standard arm64/cavium/thunder_pcie_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_pem.c optional soc_cavm_thunderx pci arm64/cavium/thunder_pcie_pem_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_common.c optional soc_cavm_thunderx pci arm64/cloudabi64/cloudabi64_sysvec.c optional compat_cloudabi64 crypto/blowfish/bf_enc.c optional crypto | ipsec crypto/des/des_enc.c optional crypto | ipsec | netsmb dev/acpica/acpi_if.m optional acpi dev/ahci/ahci_generic.c optional ahci fdt dev/hwpmc/hwpmc_arm64.c optional hwpmc dev/hwpmc/hwpmc_arm64_md.c optional hwpmc dev/mmc/host/dwmmc.c optional dwmmc dev/mmc/host/dwmmc_hisi.c optional dwmmc soc_hisi_hi6220 dev/ofw/ofw_cpu.c optional fdt dev/ofw/ofwpci.c optional fdt pci dev/pci/pci_host_generic.c optional pci fdt dev/psci/psci.c optional psci dev/psci/psci_arm64.S optional psci dev/uart/uart_cpu_fdt.c optional uart fdt dev/uart/uart_dev_pl011.c optional uart pl011 dev/usb/controller/dwc_otg_hisi.c optional dwcotg soc_hisi_hi6220 dev/vnic/mrml_bridge.c optional vnic fdt dev/vnic/nic_main.c optional vnic pci dev/vnic/nicvf_main.c optional vnic pci pci_iov dev/vnic/nicvf_queues.c optional vnic pci pci_iov dev/vnic/thunder_bgx_fdt.c optional vnic fdt dev/vnic/thunder_bgx.c optional vnic pci dev/vnic/thunder_mdio_fdt.c optional vnic fdt dev/vnic/thunder_mdio.c optional vnic -dev/vnic/lmac_if.m optional vnic +dev/vnic/lmac_if.m optional inet | inet6 | vnic kern/kern_clocksource.c standard kern/msi_if.m optional intrng kern/pic_if.m optional intrng kern/subr_devmap.c standard kern/subr_intr.c optional intrng libkern/bcmp.c standard libkern/ffs.c standard libkern/ffsl.c standard libkern/ffsll.c standard libkern/fls.c standard libkern/flsl.c standard libkern/flsll.c standard libkern/memmove.c standard libkern/memset.c standard cddl/contrib/opensolaris/common/atomic/aarch64/opensolaris_atomic.S optional zfs | dtrace compile-with "${CDDL_C}" cddl/dev/dtrace/aarch64/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/aarch64/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" Index: head/sys/dev/vnic/mrml_bridge.c =================================================================== --- head/sys/dev/vnic/mrml_bridge.c (revision 300293) +++ head/sys/dev/vnic/mrml_bridge.c (revision 300294) @@ -1,280 +1,281 @@ /* * Copyright (C) 2016 Cavium Inc. * All rights reserved. * * Developed by Semihalf. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include static MALLOC_DEFINE(M_MRMLB, "MRML bridge", "Cavium MRML bridge"); static device_probe_t mrmlb_fdt_probe; static device_attach_t mrmlb_fdt_attach; static struct resource * mrmlb_ofw_bus_alloc_res(device_t, device_t, int, int *, rman_res_t, rman_res_t, rman_res_t, u_int); static const struct ofw_bus_devinfo * mrmlb_ofw_get_devinfo(device_t, device_t); static device_method_t mrmlbus_fdt_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mrmlb_fdt_probe), DEVMETHOD(device_attach, mrmlb_fdt_attach), /* Bus interface */ DEVMETHOD(bus_alloc_resource, mrmlb_ofw_bus_alloc_res), DEVMETHOD(bus_release_resource, bus_generic_release_resource), DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_devinfo, mrmlb_ofw_get_devinfo), DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), DEVMETHOD_END }; DEFINE_CLASS_0(mrmlbus, mrmlbus_fdt_driver, mrmlbus_fdt_methods, sizeof(struct simplebus_softc)); static devclass_t mrmlbus_fdt_devclass; EARLY_DRIVER_MODULE(mrmlbus, pcib, mrmlbus_fdt_driver, mrmlbus_fdt_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); +MODULE_VERSION(mrmlbus, 1); static int mrmlb_ofw_fill_ranges(phandle_t, struct simplebus_softc *); static int mrmlb_ofw_bus_attach(device_t); static int mrmlb_fdt_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "cavium,thunder-8890-mrml-bridge")) return (ENXIO); device_set_desc(dev, "Cavium ThunderX MRML bridge"); return (BUS_PROBE_SPECIFIC); } static int mrmlb_fdt_attach(device_t dev) { int err; err = mrmlb_ofw_bus_attach(dev); if (err != 0) return (err); return (bus_generic_attach(dev)); } /* OFW bus interface */ struct mrmlb_ofw_devinfo { struct ofw_bus_devinfo di_dinfo; struct resource_list di_rl; }; static const struct ofw_bus_devinfo * mrmlb_ofw_get_devinfo(device_t bus __unused, device_t child) { struct mrmlb_ofw_devinfo *di; di = device_get_ivars(child); return (&di->di_dinfo); } static struct resource * mrmlb_ofw_bus_alloc_res(device_t bus, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) { struct simplebus_softc *sc; struct mrmlb_ofw_devinfo *di; struct resource_list_entry *rle; int i; if (RMAN_IS_DEFAULT_RANGE(start, end)) { if ((di = device_get_ivars(child)) == NULL) return (NULL); if (type == SYS_RES_IOPORT) type = SYS_RES_MEMORY; /* Find defaults for this rid */ rle = resource_list_find(&di->di_rl, type, *rid); if (rle == NULL) return (NULL); start = rle->start; end = rle->end; count = rle->count; } sc = device_get_softc(bus); if (type == SYS_RES_MEMORY) { /* Remap through ranges property */ for (i = 0; i < sc->nranges; i++) { if (start >= sc->ranges[i].bus && end < sc->ranges[i].bus + sc->ranges[i].size) { start -= sc->ranges[i].bus; start += sc->ranges[i].host; end -= sc->ranges[i].bus; end += sc->ranges[i].host; break; } } if (i == sc->nranges && sc->nranges != 0) { device_printf(bus, "Could not map resource " "%#lx-%#lx\n", start, end); return (NULL); } } return (bus_generic_alloc_resource(bus, child, type, rid, start, end, count, flags)); } /* Helper functions */ static int mrmlb_ofw_fill_ranges(phandle_t node, struct simplebus_softc *sc) { int host_address_cells; cell_t *base_ranges; ssize_t nbase_ranges; int err; int i, j, k; err = OF_searchencprop(OF_parent(node), "#address-cells", &host_address_cells, sizeof(host_address_cells)); if (err <= 0) return (-1); nbase_ranges = OF_getproplen(node, "ranges"); if (nbase_ranges < 0) return (-1); sc->nranges = nbase_ranges / sizeof(cell_t) / (sc->acells + host_address_cells + sc->scells); if (sc->nranges == 0) return (0); sc->ranges = malloc(sc->nranges * sizeof(sc->ranges[0]), M_MRMLB, M_WAITOK); base_ranges = malloc(nbase_ranges, M_MRMLB, M_WAITOK); OF_getencprop(node, "ranges", base_ranges, nbase_ranges); for (i = 0, j = 0; i < sc->nranges; i++) { sc->ranges[i].bus = 0; for (k = 0; k < sc->acells; k++) { sc->ranges[i].bus <<= 32; sc->ranges[i].bus |= base_ranges[j++]; } sc->ranges[i].host = 0; for (k = 0; k < host_address_cells; k++) { sc->ranges[i].host <<= 32; sc->ranges[i].host |= base_ranges[j++]; } sc->ranges[i].size = 0; for (k = 0; k < sc->scells; k++) { sc->ranges[i].size <<= 32; sc->ranges[i].size |= base_ranges[j++]; } } free(base_ranges, M_MRMLB); return (sc->nranges); } static int mrmlb_ofw_bus_attach(device_t dev) { struct simplebus_softc *sc; struct mrmlb_ofw_devinfo *di; device_t child; phandle_t parent, node; parent = ofw_bus_get_node(dev); simplebus_init(dev, parent); sc = device_get_softc(dev); if (mrmlb_ofw_fill_ranges(parent, sc) < 0) { device_printf(dev, "could not get ranges\n"); return (ENXIO); } /* Iterate through all bus subordinates */ for (node = OF_child(parent); node > 0; node = OF_peer(node)) { /* Allocate and populate devinfo. */ di = malloc(sizeof(*di), M_MRMLB, M_WAITOK | M_ZERO); if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) { free(di, M_MRMLB); continue; } /* Initialize and populate resource list. */ resource_list_init(&di->di_rl); ofw_bus_reg_to_rl(dev, node, sc->acells, sc->scells, &di->di_rl); ofw_bus_intr_to_rl(dev, node, &di->di_rl, NULL); /* Add newbus device for this FDT node */ child = device_add_child(dev, NULL, -1); if (child == NULL) { resource_list_free(&di->di_rl); ofw_bus_gen_destroy_devinfo(&di->di_dinfo); free(di, M_MRMLB); continue; } device_set_ivars(child, di); } return (0); } Index: head/sys/dev/vnic/nic_main.c =================================================================== --- head/sys/dev/vnic/nic_main.c (revision 300293) +++ head/sys/dev/vnic/nic_main.c (revision 300294) @@ -1,1221 +1,1222 @@ /* * Copyright (C) 2015 Cavium Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef PCI_IOV #include #include #endif #include "thunder_bgx.h" #include "nic_reg.h" #include "nic.h" #include "q_struct.h" #define VNIC_PF_DEVSTR "Cavium Thunder NIC Physical Function Driver" #define VNIC_PF_REG_RID PCIR_BAR(PCI_CFG_REG_BAR_NUM) #define NIC_SET_VF_LMAC_MAP(bgx, lmac) ((((bgx) & 0xF) << 4) | ((lmac) & 0xF)) #define NIC_GET_BGX_FROM_VF_LMAC_MAP(map) (((map) >> 4) & 0xF) #define NIC_GET_LMAC_FROM_VF_LMAC_MAP(map) ((map) & 0xF) /* Structure to be used by the SR-IOV for VF configuration schemas */ struct nicvf_info { boolean_t vf_enabled; int vf_flags; }; struct nicpf { device_t dev; uint8_t node; u_int flags; uint8_t num_vf_en; /* No of VF enabled */ struct nicvf_info vf_info[MAX_NUM_VFS_SUPPORTED]; struct resource * reg_base; /* Register start address */ struct pkind_cfg pkind; uint8_t vf_lmac_map[MAX_LMAC]; boolean_t mbx_lock[MAX_NUM_VFS_SUPPORTED]; struct callout check_link; struct mtx check_link_mtx; uint8_t link[MAX_LMAC]; uint8_t duplex[MAX_LMAC]; uint32_t speed[MAX_LMAC]; uint16_t cpi_base[MAX_NUM_VFS_SUPPORTED]; uint16_t rssi_base[MAX_NUM_VFS_SUPPORTED]; uint16_t rss_ind_tbl_size; /* MSI-X */ boolean_t msix_enabled; uint8_t num_vec; struct msix_entry msix_entries[NIC_PF_MSIX_VECTORS]; struct resource * msix_table_res; }; static int nicpf_probe(device_t); static int nicpf_attach(device_t); static int nicpf_detach(device_t); #ifdef PCI_IOV static int nicpf_iov_init(device_t, uint16_t, const nvlist_t *); static void nicpf_iov_uninit(device_t); static int nicpf_iov_add_vf(device_t, uint16_t, const nvlist_t *); #endif static device_method_t nicpf_methods[] = { /* Device interface */ DEVMETHOD(device_probe, nicpf_probe), DEVMETHOD(device_attach, nicpf_attach), DEVMETHOD(device_detach, nicpf_detach), /* PCI SR-IOV interface */ #ifdef PCI_IOV DEVMETHOD(pci_iov_init, nicpf_iov_init), DEVMETHOD(pci_iov_uninit, nicpf_iov_uninit), DEVMETHOD(pci_iov_add_vf, nicpf_iov_add_vf), #endif DEVMETHOD_END, }; -static driver_t nicpf_driver = { +static driver_t vnicpf_driver = { "vnicpf", nicpf_methods, sizeof(struct nicpf), }; -static devclass_t nicpf_devclass; +static devclass_t vnicpf_devclass; -DRIVER_MODULE(nicpf, pci, nicpf_driver, nicpf_devclass, 0, 0); -MODULE_DEPEND(nicpf, pci, 1, 1, 1); -MODULE_DEPEND(nicpf, ether, 1, 1, 1); -MODULE_DEPEND(nicpf, thunder_bgx, 1, 1, 1); +DRIVER_MODULE(vnicpf, pci, vnicpf_driver, vnicpf_devclass, 0, 0); +MODULE_VERSION(vnicpf, 1); +MODULE_DEPEND(vnicpf, pci, 1, 1, 1); +MODULE_DEPEND(vnicpf, ether, 1, 1, 1); +MODULE_DEPEND(vnicpf, thunder_bgx, 1, 1, 1); static int nicpf_alloc_res(struct nicpf *); static void nicpf_free_res(struct nicpf *); static void nic_set_lmac_vf_mapping(struct nicpf *); static void nic_init_hw(struct nicpf *); static int nic_sriov_init(device_t, struct nicpf *); static void nic_poll_for_link(void *); static int nic_register_interrupts(struct nicpf *); static void nic_unregister_interrupts(struct nicpf *); /* * Device interface */ static int nicpf_probe(device_t dev) { uint16_t vendor_id; uint16_t device_id; vendor_id = pci_get_vendor(dev); device_id = pci_get_device(dev); if (vendor_id == PCI_VENDOR_ID_CAVIUM && device_id == PCI_DEVICE_ID_THUNDER_NIC_PF) { device_set_desc(dev, VNIC_PF_DEVSTR); return (BUS_PROBE_DEFAULT); } return (ENXIO); } static int nicpf_attach(device_t dev) { struct nicpf *nic; int err; nic = device_get_softc(dev); nic->dev = dev; /* Enable bus mastering */ pci_enable_busmaster(dev); /* Allocate PCI resources */ err = nicpf_alloc_res(nic); if (err != 0) { device_printf(dev, "Could not allocate PCI resources\n"); return (err); } nic->node = nic_get_node_id(nic->reg_base); /* Enable Traffic Network Switch (TNS) bypass mode by default */ nic->flags &= ~NIC_TNS_ENABLED; nic_set_lmac_vf_mapping(nic); /* Initialize hardware */ nic_init_hw(nic); /* Set RSS TBL size for each VF */ nic->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE; /* Setup interrupts */ err = nic_register_interrupts(nic); if (err != 0) goto err_free_res; /* Configure SRIOV */ err = nic_sriov_init(dev, nic); if (err != 0) goto err_free_intr; if (nic->flags & NIC_TNS_ENABLED) return (0); mtx_init(&nic->check_link_mtx, "VNIC PF link poll", NULL, MTX_DEF); /* Register physical link status poll callout */ callout_init_mtx(&nic->check_link, &nic->check_link_mtx, 0); mtx_lock(&nic->check_link_mtx); nic_poll_for_link(nic); mtx_unlock(&nic->check_link_mtx); return (0); err_free_intr: nic_unregister_interrupts(nic); err_free_res: nicpf_free_res(nic); pci_disable_busmaster(dev); return (err); } static int nicpf_detach(device_t dev) { struct nicpf *nic; nic = device_get_softc(dev); callout_drain(&nic->check_link); mtx_destroy(&nic->check_link_mtx); nic_unregister_interrupts(nic); nicpf_free_res(nic); pci_disable_busmaster(dev); return (0); } /* * SR-IOV interface */ #ifdef PCI_IOV static int nicpf_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) { struct nicpf *nic; nic = device_get_softc(dev); if (num_vfs == 0) return (ENXIO); nic->flags |= NIC_SRIOV_ENABLED; return (0); } static void nicpf_iov_uninit(device_t dev) { /* ARM64TODO: Implement this function */ } static int nicpf_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) { const void *mac; struct nicpf *nic; size_t size; int bgx, lmac; nic = device_get_softc(dev); if ((nic->flags & NIC_SRIOV_ENABLED) == 0) return (ENXIO); if (vfnum > (nic->num_vf_en - 1)) return (EINVAL); if (nvlist_exists_binary(params, "mac-addr") != 0) { mac = nvlist_get_binary(params, "mac-addr", &size); bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vfnum]); lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vfnum]); bgx_set_lmac_mac(nic->node, bgx, lmac, mac); } return (0); } #endif /* * Helper routines */ static int nicpf_alloc_res(struct nicpf *nic) { device_t dev; int rid; dev = nic->dev; rid = VNIC_PF_REG_RID; nic->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (nic->reg_base == NULL) { /* For verbose output print some more details */ if (bootverbose) { device_printf(dev, "Could not allocate registers memory\n"); } return (ENXIO); } return (0); } static void nicpf_free_res(struct nicpf *nic) { device_t dev; dev = nic->dev; if (nic->reg_base != NULL) { bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(nic->reg_base), nic->reg_base); } } /* Register read/write APIs */ static __inline void nic_reg_write(struct nicpf *nic, bus_space_handle_t offset, uint64_t val) { bus_write_8(nic->reg_base, offset, val); } static __inline uint64_t nic_reg_read(struct nicpf *nic, uint64_t offset) { uint64_t val; val = bus_read_8(nic->reg_base, offset); return (val); } /* PF -> VF mailbox communication APIs */ static void nic_enable_mbx_intr(struct nicpf *nic) { /* Enable mailbox interrupt for all 128 VFs */ nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, ~0UL); nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S + sizeof(uint64_t), ~0UL); } static void nic_clear_mbx_intr(struct nicpf *nic, int vf, int mbx_reg) { nic_reg_write(nic, NIC_PF_MAILBOX_INT + (mbx_reg << 3), (1UL << vf)); } static uint64_t nic_get_mbx_addr(int vf) { return (NIC_PF_VF_0_127_MAILBOX_0_1 + (vf << NIC_VF_NUM_SHIFT)); } /* * Send a mailbox message to VF * @vf: vf to which this message to be sent * @mbx: Message to be sent */ static void nic_send_msg_to_vf(struct nicpf *nic, int vf, union nic_mbx *mbx) { bus_space_handle_t mbx_addr = nic_get_mbx_addr(vf); uint64_t *msg = (uint64_t *)mbx; /* * In first revision HW, mbox interrupt is triggerred * when PF writes to MBOX(1), in next revisions when * PF writes to MBOX(0) */ if (pass1_silicon(nic->dev)) { nic_reg_write(nic, mbx_addr + 0, msg[0]); nic_reg_write(nic, mbx_addr + 8, msg[1]); } else { nic_reg_write(nic, mbx_addr + 8, msg[1]); nic_reg_write(nic, mbx_addr + 0, msg[0]); } } /* * Responds to VF's READY message with VF's * ID, node, MAC address e.t.c * @vf: VF which sent READY message */ static void nic_mbx_send_ready(struct nicpf *nic, int vf) { union nic_mbx mbx = {}; int bgx_idx, lmac; const char *mac; mbx.nic_cfg.msg = NIC_MBOX_MSG_READY; mbx.nic_cfg.vf_id = vf; if (nic->flags & NIC_TNS_ENABLED) mbx.nic_cfg.tns_mode = NIC_TNS_MODE; else mbx.nic_cfg.tns_mode = NIC_TNS_BYPASS_MODE; if (vf < MAX_LMAC) { bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); mac = bgx_get_lmac_mac(nic->node, bgx_idx, lmac); if (mac) { memcpy((uint8_t *)&mbx.nic_cfg.mac_addr, mac, ETHER_ADDR_LEN); } } mbx.nic_cfg.node_id = nic->node; mbx.nic_cfg.loopback_supported = vf < MAX_LMAC; nic_send_msg_to_vf(nic, vf, &mbx); } /* * ACKs VF's mailbox message * @vf: VF to which ACK to be sent */ static void nic_mbx_send_ack(struct nicpf *nic, int vf) { union nic_mbx mbx = {}; mbx.msg.msg = NIC_MBOX_MSG_ACK; nic_send_msg_to_vf(nic, vf, &mbx); } /* * NACKs VF's mailbox message that PF is not able to * complete the action * @vf: VF to which ACK to be sent */ static void nic_mbx_send_nack(struct nicpf *nic, int vf) { union nic_mbx mbx = {}; mbx.msg.msg = NIC_MBOX_MSG_NACK; nic_send_msg_to_vf(nic, vf, &mbx); } /* * Flush all in flight receive packets to memory and * bring down an active RQ */ static int nic_rcv_queue_sw_sync(struct nicpf *nic) { uint16_t timeout = ~0x00; nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x01); /* Wait till sync cycle is finished */ while (timeout) { if (nic_reg_read(nic, NIC_PF_SW_SYNC_RX_DONE) & 0x1) break; timeout--; } nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x00); if (!timeout) { device_printf(nic->dev, "Receive queue software sync failed\n"); return (ETIMEDOUT); } return (0); } /* Get BGX Rx/Tx stats and respond to VF's request */ static void nic_get_bgx_stats(struct nicpf *nic, struct bgx_stats_msg *bgx) { int bgx_idx, lmac; union nic_mbx mbx = {}; bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]); lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]); mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS; mbx.bgx_stats.vf_id = bgx->vf_id; mbx.bgx_stats.rx = bgx->rx; mbx.bgx_stats.idx = bgx->idx; if (bgx->rx != 0) { mbx.bgx_stats.stats = bgx_get_rx_stats(nic->node, bgx_idx, lmac, bgx->idx); } else { mbx.bgx_stats.stats = bgx_get_tx_stats(nic->node, bgx_idx, lmac, bgx->idx); } nic_send_msg_to_vf(nic, bgx->vf_id, &mbx); } /* Update hardware min/max frame size */ static int nic_update_hw_frs(struct nicpf *nic, int new_frs, int vf) { if ((new_frs > NIC_HW_MAX_FRS) || (new_frs < NIC_HW_MIN_FRS)) { device_printf(nic->dev, "Invalid MTU setting from VF%d rejected, " "should be between %d and %d\n", vf, NIC_HW_MIN_FRS, NIC_HW_MAX_FRS); return (EINVAL); } new_frs += ETHER_HDR_LEN; if (new_frs <= nic->pkind.maxlen) return (0); nic->pkind.maxlen = new_frs; nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG, *(uint64_t *)&nic->pkind); return (0); } /* Set minimum transmit packet size */ static void nic_set_tx_pkt_pad(struct nicpf *nic, int size) { int lmac; uint64_t lmac_cfg; /* Max value that can be set is 60 */ if (size > 60) size = 60; for (lmac = 0; lmac < (MAX_BGX_PER_CN88XX * MAX_LMAC_PER_BGX); lmac++) { lmac_cfg = nic_reg_read(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3)); lmac_cfg &= ~(0xF << 2); lmac_cfg |= ((size / 4) << 2); nic_reg_write(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3), lmac_cfg); } } /* * Function to check number of LMACs present and set VF::LMAC mapping. * Mapping will be used while initializing channels. */ static void nic_set_lmac_vf_mapping(struct nicpf *nic) { unsigned bgx_map = bgx_get_map(nic->node); int bgx, next_bgx_lmac = 0; int lmac, lmac_cnt = 0; uint64_t lmac_credit; nic->num_vf_en = 0; if (nic->flags & NIC_TNS_ENABLED) { nic->num_vf_en = DEFAULT_NUM_VF_ENABLED; return; } for (bgx = 0; bgx < NIC_MAX_BGX; bgx++) { if ((bgx_map & (1 << bgx)) == 0) continue; lmac_cnt = bgx_get_lmac_count(nic->node, bgx); for (lmac = 0; lmac < lmac_cnt; lmac++) nic->vf_lmac_map[next_bgx_lmac++] = NIC_SET_VF_LMAC_MAP(bgx, lmac); nic->num_vf_en += lmac_cnt; /* Program LMAC credits */ lmac_credit = (1UL << 1); /* channel credit enable */ lmac_credit |= (0x1ff << 2); /* Max outstanding pkt count */ /* 48KB BGX Tx buffer size, each unit is of size 16bytes */ lmac_credit |= (((((48 * 1024) / lmac_cnt) - NIC_HW_MAX_FRS) / 16) << 12); lmac = bgx * MAX_LMAC_PER_BGX; for (; lmac < lmac_cnt + (bgx * MAX_LMAC_PER_BGX); lmac++) { nic_reg_write(nic, NIC_PF_LMAC_0_7_CREDIT + (lmac * 8), lmac_credit); } } } #define TNS_PORT0_BLOCK 6 #define TNS_PORT1_BLOCK 7 #define BGX0_BLOCK 8 #define BGX1_BLOCK 9 static void nic_init_hw(struct nicpf *nic) { int i; /* Enable NIC HW block */ nic_reg_write(nic, NIC_PF_CFG, 0x3); /* Enable backpressure */ nic_reg_write(nic, NIC_PF_BP_CFG, (1UL << 6) | 0x03); if (nic->flags & NIC_TNS_ENABLED) { nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG, (NIC_TNS_MODE << 7) | TNS_PORT0_BLOCK); nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8), (NIC_TNS_MODE << 7) | TNS_PORT1_BLOCK); nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG, (1UL << 63) | TNS_PORT0_BLOCK); nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8), (1UL << 63) | TNS_PORT1_BLOCK); } else { /* Disable TNS mode on both interfaces */ nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG, (NIC_TNS_BYPASS_MODE << 7) | BGX0_BLOCK); nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8), (NIC_TNS_BYPASS_MODE << 7) | BGX1_BLOCK); nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG, (1UL << 63) | BGX0_BLOCK); nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8), (1UL << 63) | BGX1_BLOCK); } /* PKIND configuration */ nic->pkind.minlen = 0; nic->pkind.maxlen = NIC_HW_MAX_FRS + ETHER_HDR_LEN; nic->pkind.lenerr_en = 1; nic->pkind.rx_hdr = 0; nic->pkind.hdr_sl = 0; for (i = 0; i < NIC_MAX_PKIND; i++) { nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (i << 3), *(uint64_t *)&nic->pkind); } nic_set_tx_pkt_pad(nic, NIC_HW_MIN_FRS); /* Timer config */ nic_reg_write(nic, NIC_PF_INTR_TIMER_CFG, NICPF_CLK_PER_INT_TICK); /* Enable VLAN ethertype matching and stripping */ nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7, (2 << 19) | (ETYPE_ALG_VLAN_STRIP << 16) | ETHERTYPE_VLAN); } /* Channel parse index configuration */ static void nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg) { uint32_t vnic, bgx, lmac, chan; uint32_t padd, cpi_count = 0; uint64_t cpi_base, cpi, rssi_base, rssi; uint8_t qset, rq_idx = 0; vnic = cfg->vf_id; bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]); lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]); chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF); cpi_base = (lmac * NIC_MAX_CPI_PER_LMAC) + (bgx * NIC_CPI_PER_BGX); rssi_base = (lmac * nic->rss_ind_tbl_size) + (bgx * NIC_RSSI_PER_BGX); /* Rx channel configuration */ nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_BP_CFG | (chan << 3), (1UL << 63) | (vnic << 0)); nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_CFG | (chan << 3), ((uint64_t)cfg->cpi_alg << 62) | (cpi_base << 48)); if (cfg->cpi_alg == CPI_ALG_NONE) cpi_count = 1; else if (cfg->cpi_alg == CPI_ALG_VLAN) /* 3 bits of PCP */ cpi_count = 8; else if (cfg->cpi_alg == CPI_ALG_VLAN16) /* 3 bits PCP + DEI */ cpi_count = 16; else if (cfg->cpi_alg == CPI_ALG_DIFF) /* 6bits DSCP */ cpi_count = NIC_MAX_CPI_PER_LMAC; /* RSS Qset, Qidx mapping */ qset = cfg->vf_id; rssi = rssi_base; for (; rssi < (rssi_base + cfg->rq_cnt); rssi++) { nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3), (qset << 3) | rq_idx); rq_idx++; } rssi = 0; cpi = cpi_base; for (; cpi < (cpi_base + cpi_count); cpi++) { /* Determine port to channel adder */ if (cfg->cpi_alg != CPI_ALG_DIFF) padd = cpi % cpi_count; else padd = cpi % 8; /* 3 bits CS out of 6bits DSCP */ /* Leave RSS_SIZE as '0' to disable RSS */ if (pass1_silicon(nic->dev)) { nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3), (vnic << 24) | (padd << 16) | (rssi_base + rssi)); } else { /* Set MPI_ALG to '0' to disable MCAM parsing */ nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3), (padd << 16)); /* MPI index is same as CPI if MPI_ALG is not enabled */ nic_reg_write(nic, NIC_PF_MPI_0_2047_CFG | (cpi << 3), (vnic << 24) | (rssi_base + rssi)); } if ((rssi + 1) >= cfg->rq_cnt) continue; if (cfg->cpi_alg == CPI_ALG_VLAN) rssi++; else if (cfg->cpi_alg == CPI_ALG_VLAN16) rssi = ((cpi - cpi_base) & 0xe) >> 1; else if (cfg->cpi_alg == CPI_ALG_DIFF) rssi = ((cpi - cpi_base) & 0x38) >> 3; } nic->cpi_base[cfg->vf_id] = cpi_base; nic->rssi_base[cfg->vf_id] = rssi_base; } /* Responsds to VF with its RSS indirection table size */ static void nic_send_rss_size(struct nicpf *nic, int vf) { union nic_mbx mbx = {}; uint64_t *msg; msg = (uint64_t *)&mbx; mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE; mbx.rss_size.ind_tbl_size = nic->rss_ind_tbl_size; nic_send_msg_to_vf(nic, vf, &mbx); } /* * Receive side scaling configuration * configure: * - RSS index * - indir table i.e hash::RQ mapping * - no of hash bits to consider */ static void nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg) { uint8_t qset, idx; uint64_t cpi_cfg, cpi_base, rssi_base, rssi; uint64_t idx_addr; idx = 0; rssi_base = nic->rssi_base[cfg->vf_id] + cfg->tbl_offset; rssi = rssi_base; qset = cfg->vf_id; for (; rssi < (rssi_base + cfg->tbl_len); rssi++) { nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3), (qset << 3) | (cfg->ind_tbl[idx] & 0x7)); idx++; } cpi_base = nic->cpi_base[cfg->vf_id]; if (pass1_silicon(nic->dev)) idx_addr = NIC_PF_CPI_0_2047_CFG; else idx_addr = NIC_PF_MPI_0_2047_CFG; cpi_cfg = nic_reg_read(nic, idx_addr | (cpi_base << 3)); cpi_cfg &= ~(0xFUL << 20); cpi_cfg |= (cfg->hash_bits << 20); nic_reg_write(nic, idx_addr | (cpi_base << 3), cpi_cfg); } /* * 4 level transmit side scheduler configutation * for TNS bypass mode * * Sample configuration for SQ0 * VNIC0-SQ0 -> TL4(0) -> TL3[0] -> TL2[0] -> TL1[0] -> BGX0 * VNIC1-SQ0 -> TL4(8) -> TL3[2] -> TL2[0] -> TL1[0] -> BGX0 * VNIC2-SQ0 -> TL4(16) -> TL3[4] -> TL2[1] -> TL1[0] -> BGX0 * VNIC3-SQ0 -> TL4(24) -> TL3[6] -> TL2[1] -> TL1[0] -> BGX0 * VNIC4-SQ0 -> TL4(512) -> TL3[128] -> TL2[32] -> TL1[1] -> BGX1 * VNIC5-SQ0 -> TL4(520) -> TL3[130] -> TL2[32] -> TL1[1] -> BGX1 * VNIC6-SQ0 -> TL4(528) -> TL3[132] -> TL2[33] -> TL1[1] -> BGX1 * VNIC7-SQ0 -> TL4(536) -> TL3[134] -> TL2[33] -> TL1[1] -> BGX1 */ static void nic_tx_channel_cfg(struct nicpf *nic, uint8_t vnic, struct sq_cfg_msg *sq) { uint32_t bgx, lmac, chan; uint32_t tl2, tl3, tl4; uint32_t rr_quantum; uint8_t sq_idx = sq->sq_num; uint8_t pqs_vnic; pqs_vnic = vnic; bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]); lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]); /* 24 bytes for FCS, IPG and preamble */ rr_quantum = ((NIC_HW_MAX_FRS + 24) / 4); tl4 = (lmac * NIC_TL4_PER_LMAC) + (bgx * NIC_TL4_PER_BGX); tl4 += sq_idx; tl3 = tl4 / (NIC_MAX_TL4 / NIC_MAX_TL3); nic_reg_write(nic, NIC_PF_QSET_0_127_SQ_0_7_CFG2 | ((uint64_t)vnic << NIC_QS_ID_SHIFT) | ((uint32_t)sq_idx << NIC_Q_NUM_SHIFT), tl4); nic_reg_write(nic, NIC_PF_TL4_0_1023_CFG | (tl4 << 3), ((uint64_t)vnic << 27) | ((uint32_t)sq_idx << 24) | rr_quantum); nic_reg_write(nic, NIC_PF_TL3_0_255_CFG | (tl3 << 3), rr_quantum); chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF); nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), chan); /* Enable backpressure on the channel */ nic_reg_write(nic, NIC_PF_CHAN_0_255_TX_CFG | (chan << 3), 1); tl2 = tl3 >> 2; nic_reg_write(nic, NIC_PF_TL3A_0_63_CFG | (tl2 << 3), tl2); nic_reg_write(nic, NIC_PF_TL2_0_63_CFG | (tl2 << 3), rr_quantum); /* No priorities as of now */ nic_reg_write(nic, NIC_PF_TL2_0_63_PRI | (tl2 << 3), 0x00); } static int nic_config_loopback(struct nicpf *nic, struct set_loopback *lbk) { int bgx_idx, lmac_idx; if (lbk->vf_id > MAX_LMAC) return (ENXIO); bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]); lmac_idx = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]); bgx_lmac_internal_loopback(nic->node, bgx_idx, lmac_idx, lbk->enable); return (0); } /* Interrupt handler to handle mailbox messages from VFs */ static void nic_handle_mbx_intr(struct nicpf *nic, int vf) { union nic_mbx mbx = {}; uint64_t *mbx_data; uint64_t mbx_addr; uint64_t reg_addr; uint64_t cfg; int bgx, lmac; int i; int ret = 0; nic->mbx_lock[vf] = TRUE; mbx_addr = nic_get_mbx_addr(vf); mbx_data = (uint64_t *)&mbx; for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) { *mbx_data = nic_reg_read(nic, mbx_addr); mbx_data++; mbx_addr += sizeof(uint64_t); } switch (mbx.msg.msg) { case NIC_MBOX_MSG_READY: nic_mbx_send_ready(nic, vf); if (vf < MAX_LMAC) { nic->link[vf] = 0; nic->duplex[vf] = 0; nic->speed[vf] = 0; } ret = 1; break; case NIC_MBOX_MSG_QS_CFG: reg_addr = NIC_PF_QSET_0_127_CFG | (mbx.qs.num << NIC_QS_ID_SHIFT); cfg = mbx.qs.cfg; nic_reg_write(nic, reg_addr, cfg); break; case NIC_MBOX_MSG_RQ_CFG: reg_addr = NIC_PF_QSET_0_127_RQ_0_7_CFG | (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); nic_reg_write(nic, reg_addr, mbx.rq.cfg); break; case NIC_MBOX_MSG_RQ_BP_CFG: reg_addr = NIC_PF_QSET_0_127_RQ_0_7_BP_CFG | (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); nic_reg_write(nic, reg_addr, mbx.rq.cfg); break; case NIC_MBOX_MSG_RQ_SW_SYNC: ret = nic_rcv_queue_sw_sync(nic); break; case NIC_MBOX_MSG_RQ_DROP_CFG: reg_addr = NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG | (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); nic_reg_write(nic, reg_addr, mbx.rq.cfg); break; case NIC_MBOX_MSG_SQ_CFG: reg_addr = NIC_PF_QSET_0_127_SQ_0_7_CFG | (mbx.sq.qs_num << NIC_QS_ID_SHIFT) | (mbx.sq.sq_num << NIC_Q_NUM_SHIFT); nic_reg_write(nic, reg_addr, mbx.sq.cfg); nic_tx_channel_cfg(nic, mbx.qs.num, &mbx.sq); break; case NIC_MBOX_MSG_SET_MAC: lmac = mbx.mac.vf_id; bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]); lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]); bgx_set_lmac_mac(nic->node, bgx, lmac, mbx.mac.mac_addr); break; case NIC_MBOX_MSG_SET_MAX_FRS: ret = nic_update_hw_frs(nic, mbx.frs.max_frs, mbx.frs.vf_id); break; case NIC_MBOX_MSG_CPI_CFG: nic_config_cpi(nic, &mbx.cpi_cfg); break; case NIC_MBOX_MSG_RSS_SIZE: nic_send_rss_size(nic, vf); goto unlock; case NIC_MBOX_MSG_RSS_CFG: case NIC_MBOX_MSG_RSS_CFG_CONT: /* fall through */ nic_config_rss(nic, &mbx.rss_cfg); break; case NIC_MBOX_MSG_CFG_DONE: /* Last message of VF config msg sequence */ nic->vf_info[vf].vf_enabled = TRUE; goto unlock; case NIC_MBOX_MSG_SHUTDOWN: /* First msg in VF teardown sequence */ nic->vf_info[vf].vf_enabled = FALSE; break; case NIC_MBOX_MSG_BGX_STATS: nic_get_bgx_stats(nic, &mbx.bgx_stats); goto unlock; case NIC_MBOX_MSG_LOOPBACK: ret = nic_config_loopback(nic, &mbx.lbk); break; default: device_printf(nic->dev, "Invalid msg from VF%d, msg 0x%x\n", vf, mbx.msg.msg); break; } if (ret == 0) nic_mbx_send_ack(nic, vf); else if (mbx.msg.msg != NIC_MBOX_MSG_READY) nic_mbx_send_nack(nic, vf); unlock: nic->mbx_lock[vf] = FALSE; } static void nic_mbx_intr_handler(struct nicpf *nic, int mbx) { uint64_t intr; uint8_t vf, vf_per_mbx_reg = 64; intr = nic_reg_read(nic, NIC_PF_MAILBOX_INT + (mbx << 3)); for (vf = 0; vf < vf_per_mbx_reg; vf++) { if (intr & (1UL << vf)) { nic_handle_mbx_intr(nic, vf + (mbx * vf_per_mbx_reg)); nic_clear_mbx_intr(nic, vf, mbx); } } } static void nic_mbx0_intr_handler (void *arg) { struct nicpf *nic = (struct nicpf *)arg; nic_mbx_intr_handler(nic, 0); } static void nic_mbx1_intr_handler (void *arg) { struct nicpf *nic = (struct nicpf *)arg; nic_mbx_intr_handler(nic, 1); } static int nic_enable_msix(struct nicpf *nic) { struct pci_devinfo *dinfo; int rid, count; int ret; dinfo = device_get_ivars(nic->dev); rid = dinfo->cfg.msix.msix_table_bar; nic->msix_table_res = bus_alloc_resource_any(nic->dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (nic->msix_table_res == NULL) { device_printf(nic->dev, "Could not allocate memory for MSI-X table\n"); return (ENXIO); } count = nic->num_vec = NIC_PF_MSIX_VECTORS; ret = pci_alloc_msix(nic->dev, &count); if ((ret != 0) || (count != nic->num_vec)) { device_printf(nic->dev, "Request for #%d msix vectors failed, error: %d\n", nic->num_vec, ret); return (ret); } nic->msix_enabled = 1; return (0); } static void nic_disable_msix(struct nicpf *nic) { if (nic->msix_enabled) { pci_release_msi(nic->dev); nic->msix_enabled = 0; nic->num_vec = 0; } } static void nic_free_all_interrupts(struct nicpf *nic) { int irq; for (irq = 0; irq < nic->num_vec; irq++) { if (nic->msix_entries[irq].irq_res == NULL) continue; if (nic->msix_entries[irq].handle != NULL) { bus_teardown_intr(nic->dev, nic->msix_entries[irq].irq_res, nic->msix_entries[irq].handle); } bus_release_resource(nic->dev, SYS_RES_IRQ, irq, nic->msix_entries[irq].irq_res); } } static int nic_register_interrupts(struct nicpf *nic) { int irq, rid; int ret; /* Enable MSI-X */ ret = nic_enable_msix(nic); if (ret != 0) return (ret); /* Register mailbox interrupt handlers */ irq = NIC_PF_INTR_ID_MBOX0; rid = irq + 1; nic->msix_entries[irq].irq_res = bus_alloc_resource_any(nic->dev, SYS_RES_IRQ, &rid, (RF_SHAREABLE | RF_ACTIVE)); if (nic->msix_entries[irq].irq_res == NULL) { ret = ENXIO; goto fail; } ret = bus_setup_intr(nic->dev, nic->msix_entries[irq].irq_res, (INTR_MPSAFE | INTR_TYPE_MISC), NULL, nic_mbx0_intr_handler, nic, &nic->msix_entries[irq].handle); if (ret != 0) goto fail; irq = NIC_PF_INTR_ID_MBOX1; rid = irq + 1; nic->msix_entries[irq].irq_res = bus_alloc_resource_any(nic->dev, SYS_RES_IRQ, &rid, (RF_SHAREABLE | RF_ACTIVE)); if (nic->msix_entries[irq].irq_res == NULL) { ret = ENXIO; goto fail; } ret = bus_setup_intr(nic->dev, nic->msix_entries[irq].irq_res, (INTR_MPSAFE | INTR_TYPE_MISC), NULL, nic_mbx1_intr_handler, nic, &nic->msix_entries[irq].handle); if (ret != 0) goto fail; /* Enable mailbox interrupt */ nic_enable_mbx_intr(nic); return (0); fail: nic_free_all_interrupts(nic); return (ret); } static void nic_unregister_interrupts(struct nicpf *nic) { nic_free_all_interrupts(nic); nic_disable_msix(nic); } static int nic_sriov_init(device_t dev, struct nicpf *nic) { #ifdef PCI_IOV nvlist_t *pf_schema, *vf_schema; int iov_pos; int err; uint16_t total_vf_cnt; err = pci_find_extcap(dev, PCIZ_SRIOV, &iov_pos); if (err != 0) { device_printf(dev, "SR-IOV capability is not found in PCIe config space\n"); return (err); } /* Fix-up the number of enabled VFs */ total_vf_cnt = pci_read_config(dev, iov_pos + PCIR_SRIOV_TOTAL_VFS, 2); if (total_vf_cnt == 0) return (ENXIO); /* Attach SR-IOV */ pf_schema = pci_iov_schema_alloc_node(); vf_schema = pci_iov_schema_alloc_node(); pci_iov_schema_add_unicast_mac(vf_schema, "mac-addr", 0, NULL); /* * All VFs can change their MACs. * This flag will be ignored but we set it just for the record. */ pci_iov_schema_add_bool(vf_schema, "allow-set-mac", IOV_SCHEMA_HASDEFAULT, TRUE); err = pci_iov_attach(dev, pf_schema, vf_schema); if (err != 0) { device_printf(dev, "Failed to initialize SR-IOV (error=%d)\n", err); return (err); } #endif return (0); } /* * Poll for BGX LMAC link status and update corresponding VF * if there is a change, valid only if internal L2 switch * is not present otherwise VF link is always treated as up */ static void nic_poll_for_link(void *arg) { union nic_mbx mbx = {}; struct nicpf *nic; struct bgx_link_status link; uint8_t vf, bgx, lmac; nic = (struct nicpf *)arg; mbx.link_status.msg = NIC_MBOX_MSG_BGX_LINK_CHANGE; for (vf = 0; vf < nic->num_vf_en; vf++) { /* Poll only if VF is UP */ if (!nic->vf_info[vf].vf_enabled) continue; /* Get BGX, LMAC indices for the VF */ bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); /* Get interface link status */ bgx_get_lmac_link_state(nic->node, bgx, lmac, &link); /* Inform VF only if link status changed */ if (nic->link[vf] == link.link_up) continue; if (!nic->mbx_lock[vf]) { nic->link[vf] = link.link_up; nic->duplex[vf] = link.duplex; nic->speed[vf] = link.speed; /* Send a mbox message to VF with current link status */ mbx.link_status.link_up = link.link_up; mbx.link_status.duplex = link.duplex; mbx.link_status.speed = link.speed; nic_send_msg_to_vf(nic, vf, &mbx); } } callout_reset(&nic->check_link, hz * 2, nic_poll_for_link, nic); } Index: head/sys/dev/vnic/nicvf_main.c =================================================================== --- head/sys/dev/vnic/nicvf_main.c (revision 300293) +++ head/sys/dev/vnic/nicvf_main.c (revision 300294) @@ -1,1626 +1,1627 @@ /* * Copyright (C) 2015 Cavium Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #include __FBSDID("$FreeBSD$"); #include "opt_inet.h" #include "opt_inet6.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "thunder_bgx.h" #include "nic_reg.h" #include "nic.h" #include "nicvf_queues.h" #define VNIC_VF_DEVSTR "Cavium Thunder NIC Virtual Function Driver" #define VNIC_VF_REG_RID PCIR_BAR(PCI_CFG_REG_BAR_NUM) /* Lock for core interface settings */ #define NICVF_CORE_LOCK_INIT(nic) \ sx_init(&(nic)->core_sx, device_get_nameunit((nic)->dev)) #define NICVF_CORE_LOCK_DESTROY(nic) \ sx_destroy(&(nic)->core_sx) #define NICVF_CORE_LOCK(nic) sx_xlock(&(nic)->core_sx) #define NICVF_CORE_UNLOCK(nic) sx_xunlock(&(nic)->core_sx) #define NICVF_CORE_LOCK_ASSERT(nic) sx_assert(&(nic)->core_sx, SA_XLOCKED) #define SPEED_10 10 #define SPEED_100 100 #define SPEED_1000 1000 #define SPEED_10000 10000 #define SPEED_40000 40000 MALLOC_DEFINE(M_NICVF, "nicvf", "ThunderX VNIC VF dynamic memory"); static int nicvf_probe(device_t); static int nicvf_attach(device_t); static int nicvf_detach(device_t); static device_method_t nicvf_methods[] = { /* Device interface */ DEVMETHOD(device_probe, nicvf_probe), DEVMETHOD(device_attach, nicvf_attach), DEVMETHOD(device_detach, nicvf_detach), DEVMETHOD_END, }; static driver_t nicvf_driver = { "vnic", nicvf_methods, sizeof(struct nicvf), }; static devclass_t nicvf_devclass; -DRIVER_MODULE(nicvf, pci, nicvf_driver, nicvf_devclass, 0, 0); -MODULE_DEPEND(nicvf, pci, 1, 1, 1); -MODULE_DEPEND(nicvf, ether, 1, 1, 1); -MODULE_DEPEND(nicvf, vnic_pf, 1, 1, 1); +DRIVER_MODULE(vnicvf, pci, nicvf_driver, nicvf_devclass, 0, 0); +MODULE_VERSION(vnicvf, 1); +MODULE_DEPEND(vnicvf, pci, 1, 1, 1); +MODULE_DEPEND(vnicvf, ether, 1, 1, 1); +MODULE_DEPEND(vnicvf, vnicpf, 1, 1, 1); static int nicvf_allocate_misc_interrupt(struct nicvf *); static int nicvf_enable_misc_interrupt(struct nicvf *); static int nicvf_allocate_net_interrupts(struct nicvf *); static void nicvf_release_all_interrupts(struct nicvf *); static int nicvf_update_hw_max_frs(struct nicvf *, int); static int nicvf_hw_set_mac_addr(struct nicvf *, uint8_t *); static void nicvf_config_cpi(struct nicvf *); static int nicvf_rss_init(struct nicvf *); static int nicvf_init_resources(struct nicvf *); static int nicvf_setup_ifnet(struct nicvf *); static int nicvf_setup_ifmedia(struct nicvf *); static void nicvf_hw_addr_random(uint8_t *); static int nicvf_if_ioctl(struct ifnet *, u_long, caddr_t); static void nicvf_if_init(void *); static void nicvf_if_init_locked(struct nicvf *); static int nicvf_if_transmit(struct ifnet *, struct mbuf *); static void nicvf_if_qflush(struct ifnet *); static uint64_t nicvf_if_getcounter(struct ifnet *, ift_counter); static int nicvf_stop_locked(struct nicvf *); static void nicvf_media_status(struct ifnet *, struct ifmediareq *); static int nicvf_media_change(struct ifnet *); static void nicvf_tick_stats(void *); static int nicvf_probe(device_t dev) { uint16_t vendor_id; uint16_t device_id; vendor_id = pci_get_vendor(dev); device_id = pci_get_device(dev); if (vendor_id != PCI_VENDOR_ID_CAVIUM) return (ENXIO); if (device_id == PCI_DEVICE_ID_THUNDER_NIC_VF || device_id == PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF) { device_set_desc(dev, VNIC_VF_DEVSTR); return (BUS_PROBE_DEFAULT); } return (ENXIO); } static int nicvf_attach(device_t dev) { struct nicvf *nic; int rid, qcount; int err = 0; uint8_t hwaddr[ETHER_ADDR_LEN]; uint8_t zeromac[] = {[0 ... (ETHER_ADDR_LEN - 1)] = 0}; nic = device_get_softc(dev); nic->dev = dev; nic->pnicvf = nic; NICVF_CORE_LOCK_INIT(nic); /* Enable HW TSO on Pass2 */ if (!pass1_silicon(dev)) nic->hw_tso = TRUE; rid = VNIC_VF_REG_RID; nic->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (nic->reg_base == NULL) { device_printf(dev, "Could not allocate registers memory\n"); return (ENXIO); } qcount = MAX_CMP_QUEUES_PER_QS; nic->max_queues = qcount; err = nicvf_set_qset_resources(nic); if (err != 0) goto err_free_res; /* Check if PF is alive and get MAC address for this VF */ err = nicvf_allocate_misc_interrupt(nic); if (err != 0) goto err_free_res; NICVF_CORE_LOCK(nic); err = nicvf_enable_misc_interrupt(nic); NICVF_CORE_UNLOCK(nic); if (err != 0) goto err_release_intr; err = nicvf_allocate_net_interrupts(nic); if (err != 0) { device_printf(dev, "Could not allocate network interface interrupts\n"); goto err_free_ifnet; } /* If no MAC address was obtained we generate random one */ if (memcmp(nic->hwaddr, zeromac, ETHER_ADDR_LEN) == 0) { nicvf_hw_addr_random(hwaddr); memcpy(nic->hwaddr, hwaddr, ETHER_ADDR_LEN); NICVF_CORE_LOCK(nic); nicvf_hw_set_mac_addr(nic, hwaddr); NICVF_CORE_UNLOCK(nic); } /* Configure CPI alorithm */ nic->cpi_alg = CPI_ALG_NONE; NICVF_CORE_LOCK(nic); nicvf_config_cpi(nic); /* Configure receive side scaling */ if (nic->qs->rq_cnt > 1) nicvf_rss_init(nic); NICVF_CORE_UNLOCK(nic); err = nicvf_setup_ifnet(nic); if (err != 0) { device_printf(dev, "Could not set-up ifnet\n"); goto err_release_intr; } err = nicvf_setup_ifmedia(nic); if (err != 0) { device_printf(dev, "Could not set-up ifmedia\n"); goto err_free_ifnet; } mtx_init(&nic->stats_mtx, "VNIC stats", NULL, MTX_DEF); callout_init_mtx(&nic->stats_callout, &nic->stats_mtx, 0); ether_ifattach(nic->ifp, nic->hwaddr); return (0); err_free_ifnet: if_free(nic->ifp); err_release_intr: nicvf_release_all_interrupts(nic); err_free_res: bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(nic->reg_base), nic->reg_base); return (err); } static int nicvf_detach(device_t dev) { struct nicvf *nic; nic = device_get_softc(dev); NICVF_CORE_LOCK(nic); /* Shut down the port and release ring resources */ nicvf_stop_locked(nic); /* Release stats lock */ mtx_destroy(&nic->stats_mtx); /* Release interrupts */ nicvf_release_all_interrupts(nic); /* Release memory resource */ if (nic->reg_base != NULL) { bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(nic->reg_base), nic->reg_base); } /* Remove all ifmedia configurations */ ifmedia_removeall(&nic->if_media); /* Free this ifnet */ if_free(nic->ifp); NICVF_CORE_UNLOCK(nic); /* Finally destroy the lock */ NICVF_CORE_LOCK_DESTROY(nic); return (0); } static void nicvf_hw_addr_random(uint8_t *hwaddr) { uint32_t rnd; uint8_t addr[ETHER_ADDR_LEN]; /* * Create randomized MAC address. * Set 'bsd' + random 24 low-order bits. */ rnd = arc4random() & 0x00ffffff; addr[0] = 'b'; addr[1] = 's'; addr[2] = 'd'; addr[3] = rnd >> 16; addr[4] = rnd >> 8; addr[5] = rnd >> 0; memcpy(hwaddr, addr, ETHER_ADDR_LEN); } static int nicvf_setup_ifnet(struct nicvf *nic) { struct ifnet *ifp; ifp = if_alloc(IFT_ETHER); if (ifp == NULL) { device_printf(nic->dev, "Could not allocate ifnet structure\n"); return (ENOMEM); } nic->ifp = ifp; if_setsoftc(ifp, nic); if_initname(ifp, device_get_name(nic->dev), device_get_unit(nic->dev)); if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX); if_settransmitfn(ifp, nicvf_if_transmit); if_setqflushfn(ifp, nicvf_if_qflush); if_setioctlfn(ifp, nicvf_if_ioctl); if_setinitfn(ifp, nicvf_if_init); if_setgetcounterfn(ifp, nicvf_if_getcounter); if_setmtu(ifp, ETHERMTU); /* Reset caps */ if_setcapabilities(ifp, 0); /* Set the default values */ if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_JUMBO_MTU, 0); if_setcapabilitiesbit(ifp, IFCAP_LRO, 0); if (nic->hw_tso) { /* TSO */ if_setcapabilitiesbit(ifp, IFCAP_TSO4, 0); /* TSO parameters */ ifp->if_hw_tsomax = NICVF_TSO_MAXSIZE; ifp->if_hw_tsomaxsegcount = NICVF_TSO_NSEGS; ifp->if_hw_tsomaxsegsize = MCLBYTES; } /* IP/TCP/UDP HW checksums */ if_setcapabilitiesbit(ifp, IFCAP_HWCSUM, 0); if_setcapabilitiesbit(ifp, IFCAP_HWSTATS, 0); /* * HW offload enable */ if_clearhwassist(ifp); if_sethwassistbits(ifp, (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP), 0); if (nic->hw_tso) if_sethwassistbits(ifp, (CSUM_TSO), 0); if_setcapenable(ifp, if_getcapabilities(ifp)); return (0); } static int nicvf_setup_ifmedia(struct nicvf *nic) { ifmedia_init(&nic->if_media, IFM_IMASK, nicvf_media_change, nicvf_media_status); /* * Advertise availability of all possible connection types, * even though not all are possible at the same time. */ ifmedia_add(&nic->if_media, (IFM_ETHER | IFM_10_T | IFM_FDX), 0, NULL); ifmedia_add(&nic->if_media, (IFM_ETHER | IFM_100_TX | IFM_FDX), 0, NULL); ifmedia_add(&nic->if_media, (IFM_ETHER | IFM_1000_T | IFM_FDX), 0, NULL); ifmedia_add(&nic->if_media, (IFM_ETHER | IFM_10G_SR | IFM_FDX), 0, NULL); ifmedia_add(&nic->if_media, (IFM_ETHER | IFM_40G_CR4 | IFM_FDX), 0, NULL); ifmedia_add(&nic->if_media, (IFM_ETHER | IFM_AUTO | IFM_FDX), 0, NULL); ifmedia_set(&nic->if_media, (IFM_ETHER | IFM_AUTO | IFM_FDX)); return (0); } static int nicvf_if_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) { struct nicvf *nic; struct rcv_queue *rq; struct ifreq *ifr; uint32_t flags; int mask, err; int rq_idx; #if defined(INET) || defined(INET6) struct ifaddr *ifa; boolean_t avoid_reset = FALSE; #endif nic = if_getsoftc(ifp); ifr = (struct ifreq *)data; #if defined(INET) || defined(INET6) ifa = (struct ifaddr *)data; #endif err = 0; switch (cmd) { case SIOCSIFADDR: #ifdef INET if (ifa->ifa_addr->sa_family == AF_INET) avoid_reset = TRUE; #endif #ifdef INET6 if (ifa->ifa_addr->sa_family == AF_INET6) avoid_reset = TRUE; #endif #if defined(INET) || defined(INET6) /* Avoid reinitialization unless it's necessary */ if (avoid_reset) { ifp->if_flags |= IFF_UP; if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) nicvf_if_init(nic); #ifdef INET if (!(if_getflags(ifp) & IFF_NOARP)) arp_ifinit(ifp, ifa); #endif return (0); } #endif err = ether_ioctl(ifp, cmd, data); break; case SIOCSIFMTU: if (ifr->ifr_mtu < NIC_HW_MIN_FRS || ifr->ifr_mtu > NIC_HW_MAX_FRS) { err = EINVAL; } else { NICVF_CORE_LOCK(nic); err = nicvf_update_hw_max_frs(nic, ifr->ifr_mtu); if (err == 0) if_setmtu(ifp, ifr->ifr_mtu); NICVF_CORE_UNLOCK(nic); } break; case SIOCSIFFLAGS: NICVF_CORE_LOCK(nic); if (if_getflags(ifp) & IFF_UP) { if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { flags = ifp->if_flags ^ nic->if_flags; if ((nic->if_flags & ifp->if_flags) & IFF_PROMISC) { /* Change promiscous mode */ #if 0 /* ARM64TODO */ nicvf_set_promiscous(nic); #endif } if ((nic->if_flags ^ ifp->if_flags) & IFF_ALLMULTI) { /* Change multicasting settings */ #if 0 /* ARM64TODO */ nicvf_set_multicast(nic); #endif } } else { nicvf_if_init_locked(nic); } } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) nicvf_stop_locked(nic); nic->if_flags = ifp->if_flags; NICVF_CORE_UNLOCK(nic); break; case SIOCADDMULTI: case SIOCDELMULTI: if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { #if 0 NICVF_CORE_LOCK(nic); /* ARM64TODO */ nicvf_set_multicast(nic); NICVF_CORE_UNLOCK(nic); #endif } break; case SIOCSIFMEDIA: case SIOCGIFMEDIA: err = ifmedia_ioctl(ifp, ifr, &nic->if_media, cmd); break; case SIOCSIFCAP: mask = ifp->if_capenable ^ ifr->ifr_reqcap; if (mask & IFCAP_VLAN_MTU) { /* No work to do except acknowledge the change took. */ ifp->if_capenable ^= IFCAP_VLAN_MTU; } if (mask & IFCAP_TXCSUM) ifp->if_capenable ^= IFCAP_TXCSUM; if (mask & IFCAP_RXCSUM) ifp->if_capenable ^= IFCAP_RXCSUM; if ((mask & IFCAP_TSO4) && nic->hw_tso) ifp->if_capenable ^= IFCAP_TSO4; if (mask & IFCAP_LRO) { /* * Lock the driver for a moment to avoid * mismatch in per-queue settings. */ NICVF_CORE_LOCK(nic); ifp->if_capenable ^= IFCAP_LRO; if ((if_getdrvflags(nic->ifp) & IFF_DRV_RUNNING) != 0) { /* * Now disable LRO for subsequent packets. * Atomicity of this change is not necessary * as we don't need precise toggle of this * feature for all threads processing the * completion queue. */ for (rq_idx = 0; rq_idx < nic->qs->rq_cnt; rq_idx++) { rq = &nic->qs->rq[rq_idx]; rq->lro_enabled = !rq->lro_enabled; } } NICVF_CORE_UNLOCK(nic); } break; default: err = ether_ioctl(ifp, cmd, data); break; } return (err); } static void nicvf_if_init_locked(struct nicvf *nic) { struct queue_set *qs = nic->qs; struct ifnet *ifp; int qidx; int err; caddr_t if_addr; NICVF_CORE_LOCK_ASSERT(nic); ifp = nic->ifp; if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) nicvf_stop_locked(nic); err = nicvf_enable_misc_interrupt(nic); if (err != 0) { if_printf(ifp, "Could not reenable Mbox interrupt\n"); return; } /* Get the latest MAC address */ if_addr = if_getlladdr(ifp); /* Update MAC address if changed */ if (memcmp(nic->hwaddr, if_addr, ETHER_ADDR_LEN) != 0) { memcpy(nic->hwaddr, if_addr, ETHER_ADDR_LEN); nicvf_hw_set_mac_addr(nic, if_addr); } /* Initialize the queues */ err = nicvf_init_resources(nic); if (err != 0) goto error; /* Make sure queue initialization is written */ wmb(); nicvf_reg_write(nic, NIC_VF_INT, ~0UL); /* Enable Qset err interrupt */ nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0); /* Enable completion queue interrupt */ for (qidx = 0; qidx < qs->cq_cnt; qidx++) nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx); /* Enable RBDR threshold interrupt */ for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) nicvf_enable_intr(nic, NICVF_INTR_RBDR, qidx); nic->drv_stats.txq_stop = 0; nic->drv_stats.txq_wake = 0; /* Activate network interface */ if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); /* Schedule callout to update stats */ callout_reset(&nic->stats_callout, hz, nicvf_tick_stats, nic); return; error: /* Something went very wrong. Disable this ifnet for good */ if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); } static void nicvf_if_init(void *if_softc) { struct nicvf *nic = if_softc; NICVF_CORE_LOCK(nic); nicvf_if_init_locked(nic); NICVF_CORE_UNLOCK(nic); } static int nicvf_if_transmit(struct ifnet *ifp, struct mbuf *mbuf) { struct nicvf *nic = if_getsoftc(ifp); struct queue_set *qs = nic->qs; struct snd_queue *sq; struct mbuf *mtmp; int qidx; int err = 0; if (__predict_false(qs == NULL)) { panic("%s: missing queue set for %s", __func__, device_get_nameunit(nic->dev)); } /* Select queue */ if (M_HASHTYPE_GET(mbuf) != M_HASHTYPE_NONE) qidx = mbuf->m_pkthdr.flowid % qs->sq_cnt; else qidx = curcpu % qs->sq_cnt; sq = &qs->sq[qidx]; if (mbuf->m_next != NULL && (mbuf->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP)) != 0) { if (M_WRITABLE(mbuf) == 0) { mtmp = m_dup(mbuf, M_NOWAIT); m_freem(mbuf); if (mtmp == NULL) return (ENOBUFS); mbuf = mtmp; } } err = drbr_enqueue(ifp, sq->br, mbuf); if (((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING) || !nic->link_up || (err != 0)) { /* * Try to enqueue packet to the ring buffer. * If the driver is not active, link down or enqueue operation * failed, return with the appropriate error code. */ return (err); } if (NICVF_TX_TRYLOCK(sq) != 0) { err = nicvf_xmit_locked(sq); NICVF_TX_UNLOCK(sq); return (err); } else taskqueue_enqueue(sq->snd_taskq, &sq->snd_task); return (0); } static void nicvf_if_qflush(struct ifnet *ifp) { struct nicvf *nic; struct queue_set *qs; struct snd_queue *sq; struct mbuf *mbuf; size_t idx; nic = if_getsoftc(ifp); qs = nic->qs; for (idx = 0; idx < qs->sq_cnt; idx++) { sq = &qs->sq[idx]; NICVF_TX_LOCK(sq); while ((mbuf = buf_ring_dequeue_sc(sq->br)) != NULL) m_freem(mbuf); NICVF_TX_UNLOCK(sq); } if_qflush(ifp); } static uint64_t nicvf_if_getcounter(struct ifnet *ifp, ift_counter cnt) { struct nicvf *nic; struct nicvf_hw_stats *hw_stats; struct nicvf_drv_stats *drv_stats; nic = if_getsoftc(ifp); hw_stats = &nic->hw_stats; drv_stats = &nic->drv_stats; switch (cnt) { case IFCOUNTER_IPACKETS: return (drv_stats->rx_frames_ok); case IFCOUNTER_OPACKETS: return (drv_stats->tx_frames_ok); case IFCOUNTER_IBYTES: return (hw_stats->rx_bytes); case IFCOUNTER_OBYTES: return (hw_stats->tx_bytes_ok); case IFCOUNTER_IMCASTS: return (hw_stats->rx_mcast_frames); case IFCOUNTER_COLLISIONS: return (0); case IFCOUNTER_IQDROPS: return (drv_stats->rx_drops); case IFCOUNTER_OQDROPS: return (drv_stats->tx_drops); default: return (if_get_counter_default(ifp, cnt)); } } static void nicvf_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) { struct nicvf *nic = if_getsoftc(ifp); NICVF_CORE_LOCK(nic); ifmr->ifm_status = IFM_AVALID; ifmr->ifm_active = IFM_ETHER; if (nic->link_up) { /* Device attached to working network */ ifmr->ifm_status |= IFM_ACTIVE; } switch (nic->speed) { case SPEED_10: ifmr->ifm_active |= IFM_10_T; break; case SPEED_100: ifmr->ifm_active |= IFM_100_TX; break; case SPEED_1000: ifmr->ifm_active |= IFM_1000_T; break; case SPEED_10000: ifmr->ifm_active |= IFM_10G_SR; break; case SPEED_40000: ifmr->ifm_active |= IFM_40G_CR4; break; default: ifmr->ifm_active |= IFM_AUTO; break; } if (nic->duplex) ifmr->ifm_active |= IFM_FDX; else ifmr->ifm_active |= IFM_HDX; NICVF_CORE_UNLOCK(nic); } static int nicvf_media_change(struct ifnet *ifp __unused) { return (0); } /* Register read/write APIs */ void nicvf_reg_write(struct nicvf *nic, bus_space_handle_t offset, uint64_t val) { bus_write_8(nic->reg_base, offset, val); } uint64_t nicvf_reg_read(struct nicvf *nic, uint64_t offset) { return (bus_read_8(nic->reg_base, offset)); } void nicvf_queue_reg_write(struct nicvf *nic, bus_space_handle_t offset, uint64_t qidx, uint64_t val) { bus_write_8(nic->reg_base, offset + (qidx << NIC_Q_NUM_SHIFT), val); } uint64_t nicvf_queue_reg_read(struct nicvf *nic, bus_space_handle_t offset, uint64_t qidx) { return (bus_read_8(nic->reg_base, offset + (qidx << NIC_Q_NUM_SHIFT))); } /* VF -> PF mailbox communication */ static void nicvf_write_to_mbx(struct nicvf *nic, union nic_mbx *mbx) { uint64_t *msg = (uint64_t *)mbx; nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 0, msg[0]); nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 8, msg[1]); } int nicvf_send_msg_to_pf(struct nicvf *nic, union nic_mbx *mbx) { int timeout = NIC_MBOX_MSG_TIMEOUT * 10; int sleep = 2; NICVF_CORE_LOCK_ASSERT(nic); nic->pf_acked = FALSE; nic->pf_nacked = FALSE; nicvf_write_to_mbx(nic, mbx); /* Wait for previous message to be acked, timeout 2sec */ while (!nic->pf_acked) { if (nic->pf_nacked) return (EINVAL); DELAY(sleep * 1000); if (nic->pf_acked) break; timeout -= sleep; if (!timeout) { device_printf(nic->dev, "PF didn't ack to mbox msg %d from VF%d\n", (mbx->msg.msg & 0xFF), nic->vf_id); return (EBUSY); } } return (0); } /* * Checks if VF is able to comminicate with PF * and also gets the VNIC number this VF is associated to. */ static int nicvf_check_pf_ready(struct nicvf *nic) { union nic_mbx mbx = {}; mbx.msg.msg = NIC_MBOX_MSG_READY; if (nicvf_send_msg_to_pf(nic, &mbx)) { device_printf(nic->dev, "PF didn't respond to READY msg\n"); return 0; } return 1; } static void nicvf_read_bgx_stats(struct nicvf *nic, struct bgx_stats_msg *bgx) { if (bgx->rx) nic->bgx_stats.rx_stats[bgx->idx] = bgx->stats; else nic->bgx_stats.tx_stats[bgx->idx] = bgx->stats; } static void nicvf_handle_mbx_intr(struct nicvf *nic) { union nic_mbx mbx = {}; uint64_t *mbx_data; uint64_t mbx_addr; int i; mbx_addr = NIC_VF_PF_MAILBOX_0_1; mbx_data = (uint64_t *)&mbx; for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) { *mbx_data = nicvf_reg_read(nic, mbx_addr); mbx_data++; mbx_addr += sizeof(uint64_t); } switch (mbx.msg.msg) { case NIC_MBOX_MSG_READY: nic->pf_acked = TRUE; nic->vf_id = mbx.nic_cfg.vf_id & 0x7F; nic->tns_mode = mbx.nic_cfg.tns_mode & 0x7F; nic->node = mbx.nic_cfg.node_id; memcpy(nic->hwaddr, mbx.nic_cfg.mac_addr, ETHER_ADDR_LEN); nic->loopback_supported = mbx.nic_cfg.loopback_supported; nic->link_up = FALSE; nic->duplex = 0; nic->speed = 0; break; case NIC_MBOX_MSG_ACK: nic->pf_acked = TRUE; break; case NIC_MBOX_MSG_NACK: nic->pf_nacked = TRUE; break; case NIC_MBOX_MSG_RSS_SIZE: nic->rss_info.rss_size = mbx.rss_size.ind_tbl_size; nic->pf_acked = TRUE; break; case NIC_MBOX_MSG_BGX_STATS: nicvf_read_bgx_stats(nic, &mbx.bgx_stats); nic->pf_acked = TRUE; break; case NIC_MBOX_MSG_BGX_LINK_CHANGE: nic->pf_acked = TRUE; nic->link_up = mbx.link_status.link_up; nic->duplex = mbx.link_status.duplex; nic->speed = mbx.link_status.speed; if (nic->link_up) { if_setbaudrate(nic->ifp, nic->speed * 1000000); if_link_state_change(nic->ifp, LINK_STATE_UP); } else { if_setbaudrate(nic->ifp, 0); if_link_state_change(nic->ifp, LINK_STATE_DOWN); } break; default: device_printf(nic->dev, "Invalid message from PF, msg 0x%x\n", mbx.msg.msg); break; } nicvf_clear_intr(nic, NICVF_INTR_MBOX, 0); } static int nicvf_update_hw_max_frs(struct nicvf *nic, int mtu) { union nic_mbx mbx = {}; mbx.frs.msg = NIC_MBOX_MSG_SET_MAX_FRS; mbx.frs.max_frs = mtu; mbx.frs.vf_id = nic->vf_id; return nicvf_send_msg_to_pf(nic, &mbx); } static int nicvf_hw_set_mac_addr(struct nicvf *nic, uint8_t *hwaddr) { union nic_mbx mbx = {}; mbx.mac.msg = NIC_MBOX_MSG_SET_MAC; mbx.mac.vf_id = nic->vf_id; memcpy(mbx.mac.mac_addr, hwaddr, ETHER_ADDR_LEN); return (nicvf_send_msg_to_pf(nic, &mbx)); } static void nicvf_config_cpi(struct nicvf *nic) { union nic_mbx mbx = {}; mbx.cpi_cfg.msg = NIC_MBOX_MSG_CPI_CFG; mbx.cpi_cfg.vf_id = nic->vf_id; mbx.cpi_cfg.cpi_alg = nic->cpi_alg; mbx.cpi_cfg.rq_cnt = nic->qs->rq_cnt; nicvf_send_msg_to_pf(nic, &mbx); } static void nicvf_get_rss_size(struct nicvf *nic) { union nic_mbx mbx = {}; mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE; mbx.rss_size.vf_id = nic->vf_id; nicvf_send_msg_to_pf(nic, &mbx); } static void nicvf_config_rss(struct nicvf *nic) { union nic_mbx mbx = {}; struct nicvf_rss_info *rss; int ind_tbl_len; int i, nextq; rss = &nic->rss_info; ind_tbl_len = rss->rss_size; nextq = 0; mbx.rss_cfg.vf_id = nic->vf_id; mbx.rss_cfg.hash_bits = rss->hash_bits; while (ind_tbl_len != 0) { mbx.rss_cfg.tbl_offset = nextq; mbx.rss_cfg.tbl_len = MIN(ind_tbl_len, RSS_IND_TBL_LEN_PER_MBX_MSG); mbx.rss_cfg.msg = mbx.rss_cfg.tbl_offset ? NIC_MBOX_MSG_RSS_CFG_CONT : NIC_MBOX_MSG_RSS_CFG; for (i = 0; i < mbx.rss_cfg.tbl_len; i++) mbx.rss_cfg.ind_tbl[i] = rss->ind_tbl[nextq++]; nicvf_send_msg_to_pf(nic, &mbx); ind_tbl_len -= mbx.rss_cfg.tbl_len; } } static void nicvf_set_rss_key(struct nicvf *nic) { struct nicvf_rss_info *rss; uint64_t key_addr; int idx; rss = &nic->rss_info; key_addr = NIC_VNIC_RSS_KEY_0_4; for (idx = 0; idx < RSS_HASH_KEY_SIZE; idx++) { nicvf_reg_write(nic, key_addr, rss->key[idx]); key_addr += sizeof(uint64_t); } } static int nicvf_rss_init(struct nicvf *nic) { struct nicvf_rss_info *rss; int idx; nicvf_get_rss_size(nic); rss = &nic->rss_info; if (nic->cpi_alg != CPI_ALG_NONE) { rss->enable = FALSE; rss->hash_bits = 0; return (ENXIO); } rss->enable = TRUE; /* Using the HW reset value for now */ rss->key[0] = 0xFEED0BADFEED0BADUL; rss->key[1] = 0xFEED0BADFEED0BADUL; rss->key[2] = 0xFEED0BADFEED0BADUL; rss->key[3] = 0xFEED0BADFEED0BADUL; rss->key[4] = 0xFEED0BADFEED0BADUL; nicvf_set_rss_key(nic); rss->cfg = RSS_IP_HASH_ENA | RSS_TCP_HASH_ENA | RSS_UDP_HASH_ENA; nicvf_reg_write(nic, NIC_VNIC_RSS_CFG, rss->cfg); rss->hash_bits = fls(rss->rss_size) - 1; for (idx = 0; idx < rss->rss_size; idx++) rss->ind_tbl[idx] = idx % nic->rx_queues; nicvf_config_rss(nic); return (0); } static int nicvf_init_resources(struct nicvf *nic) { int err; union nic_mbx mbx = {}; mbx.msg.msg = NIC_MBOX_MSG_CFG_DONE; /* Enable Qset */ nicvf_qset_config(nic, TRUE); /* Initialize queues and HW for data transfer */ err = nicvf_config_data_transfer(nic, TRUE); if (err) { device_printf(nic->dev, "Failed to alloc/config VF's QSet resources\n"); return (err); } /* Send VF config done msg to PF */ nicvf_write_to_mbx(nic, &mbx); return (0); } static void nicvf_misc_intr_handler(void *arg) { struct nicvf *nic = (struct nicvf *)arg; uint64_t intr; intr = nicvf_reg_read(nic, NIC_VF_INT); /* Check for spurious interrupt */ if (!(intr & NICVF_INTR_MBOX_MASK)) return; nicvf_handle_mbx_intr(nic); } static int nicvf_intr_handler(void *arg) { struct nicvf *nic; struct cmp_queue *cq; int qidx; cq = (struct cmp_queue *)arg; nic = cq->nic; qidx = cq->idx; /* Disable interrupts */ nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx); taskqueue_enqueue(cq->cmp_taskq, &cq->cmp_task); /* Clear interrupt */ nicvf_clear_intr(nic, NICVF_INTR_CQ, qidx); return (FILTER_HANDLED); } static void nicvf_rbdr_intr_handler(void *arg) { struct nicvf *nic; struct queue_set *qs; struct rbdr *rbdr; int qidx; nic = (struct nicvf *)arg; /* Disable RBDR interrupt and schedule softirq */ for (qidx = 0; qidx < nic->qs->rbdr_cnt; qidx++) { if (!nicvf_is_intr_enabled(nic, NICVF_INTR_RBDR, qidx)) continue; nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx); qs = nic->qs; rbdr = &qs->rbdr[qidx]; taskqueue_enqueue(rbdr->rbdr_taskq, &rbdr->rbdr_task_nowait); /* Clear interrupt */ nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx); } } static void nicvf_qs_err_intr_handler(void *arg) { struct nicvf *nic = (struct nicvf *)arg; struct queue_set *qs = nic->qs; /* Disable Qset err interrupt and schedule softirq */ nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0); taskqueue_enqueue(qs->qs_err_taskq, &qs->qs_err_task); nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0); } static int nicvf_enable_msix(struct nicvf *nic) { struct pci_devinfo *dinfo; int rid, count; int ret; dinfo = device_get_ivars(nic->dev); rid = dinfo->cfg.msix.msix_table_bar; nic->msix_table_res = bus_alloc_resource_any(nic->dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (nic->msix_table_res == NULL) { device_printf(nic->dev, "Could not allocate memory for MSI-X table\n"); return (ENXIO); } count = nic->num_vec = NIC_VF_MSIX_VECTORS; ret = pci_alloc_msix(nic->dev, &count); if ((ret != 0) || (count != nic->num_vec)) { device_printf(nic->dev, "Request for #%d msix vectors failed, error: %d\n", nic->num_vec, ret); return (ret); } nic->msix_enabled = 1; return (0); } static void nicvf_disable_msix(struct nicvf *nic) { if (nic->msix_enabled) { pci_release_msi(nic->dev); nic->msix_enabled = 0; nic->num_vec = 0; } } static void nicvf_release_all_interrupts(struct nicvf *nic) { struct resource *res; int irq; int err; /* Free registered interrupts */ for (irq = 0; irq < nic->num_vec; irq++) { res = nic->msix_entries[irq].irq_res; if (res == NULL) continue; /* Teardown interrupt first */ if (nic->msix_entries[irq].handle != NULL) { err = bus_teardown_intr(nic->dev, nic->msix_entries[irq].irq_res, nic->msix_entries[irq].handle); KASSERT(err == 0, ("ERROR: Unable to teardown interrupt %d", irq)); nic->msix_entries[irq].handle = NULL; } bus_release_resource(nic->dev, SYS_RES_IRQ, rman_get_rid(res), nic->msix_entries[irq].irq_res); nic->msix_entries[irq].irq_res = NULL; } /* Disable MSI-X */ nicvf_disable_msix(nic); } /* * Initialize MSIX vectors and register MISC interrupt. * Send READY message to PF to check if its alive */ static int nicvf_allocate_misc_interrupt(struct nicvf *nic) { struct resource *res; int irq, rid; int ret = 0; /* Return if mailbox interrupt is already registered */ if (nic->msix_enabled) return (0); /* Enable MSI-X */ if (nicvf_enable_msix(nic) != 0) return (ENXIO); irq = NICVF_INTR_ID_MISC; rid = irq + 1; nic->msix_entries[irq].irq_res = bus_alloc_resource_any(nic->dev, SYS_RES_IRQ, &rid, (RF_SHAREABLE | RF_ACTIVE)); if (nic->msix_entries[irq].irq_res == NULL) { device_printf(nic->dev, "Could not allocate Mbox interrupt for VF%d\n", device_get_unit(nic->dev)); return (ENXIO); } ret = bus_setup_intr(nic->dev, nic->msix_entries[irq].irq_res, (INTR_MPSAFE | INTR_TYPE_MISC), NULL, nicvf_misc_intr_handler, nic, &nic->msix_entries[irq].handle); if (ret != 0) { res = nic->msix_entries[irq].irq_res; bus_release_resource(nic->dev, SYS_RES_IRQ, rman_get_rid(res), res); nic->msix_entries[irq].irq_res = NULL; return (ret); } return (0); } static int nicvf_enable_misc_interrupt(struct nicvf *nic) { /* Enable mailbox interrupt */ nicvf_enable_intr(nic, NICVF_INTR_MBOX, 0); /* Check if VF is able to communicate with PF */ if (!nicvf_check_pf_ready(nic)) { nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0); return (ENXIO); } return (0); } static void nicvf_release_net_interrupts(struct nicvf *nic) { struct resource *res; int irq; int err; for_each_cq_irq(irq) { res = nic->msix_entries[irq].irq_res; if (res == NULL) continue; /* Teardown active interrupts first */ if (nic->msix_entries[irq].handle != NULL) { err = bus_teardown_intr(nic->dev, nic->msix_entries[irq].irq_res, nic->msix_entries[irq].handle); KASSERT(err == 0, ("ERROR: Unable to teardown CQ interrupt %d", (irq - NICVF_INTR_ID_CQ))); if (err != 0) continue; } /* Release resource */ bus_release_resource(nic->dev, SYS_RES_IRQ, rman_get_rid(res), res); nic->msix_entries[irq].irq_res = NULL; } for_each_rbdr_irq(irq) { res = nic->msix_entries[irq].irq_res; if (res == NULL) continue; /* Teardown active interrupts first */ if (nic->msix_entries[irq].handle != NULL) { err = bus_teardown_intr(nic->dev, nic->msix_entries[irq].irq_res, nic->msix_entries[irq].handle); KASSERT(err == 0, ("ERROR: Unable to teardown RDBR interrupt %d", (irq - NICVF_INTR_ID_RBDR))); if (err != 0) continue; } /* Release resource */ bus_release_resource(nic->dev, SYS_RES_IRQ, rman_get_rid(res), res); nic->msix_entries[irq].irq_res = NULL; } irq = NICVF_INTR_ID_QS_ERR; res = nic->msix_entries[irq].irq_res; if (res != NULL) { /* Teardown active interrupts first */ if (nic->msix_entries[irq].handle != NULL) { err = bus_teardown_intr(nic->dev, nic->msix_entries[irq].irq_res, nic->msix_entries[irq].handle); KASSERT(err == 0, ("ERROR: Unable to teardown QS Error interrupt %d", irq)); if (err != 0) return; } /* Release resource */ bus_release_resource(nic->dev, SYS_RES_IRQ, rman_get_rid(res), res); nic->msix_entries[irq].irq_res = NULL; } } static int nicvf_allocate_net_interrupts(struct nicvf *nic) { u_int cpuid; int irq, rid; int qidx; int ret = 0; /* MSI-X must be configured by now */ if (!nic->msix_enabled) { device_printf(nic->dev, "Cannot alloacte queue interrups. " "MSI-X interrupts disabled.\n"); return (ENXIO); } /* Register CQ interrupts */ for_each_cq_irq(irq) { if (irq >= (NICVF_INTR_ID_CQ + nic->qs->cq_cnt)) break; qidx = irq - NICVF_INTR_ID_CQ; rid = irq + 1; nic->msix_entries[irq].irq_res = bus_alloc_resource_any(nic->dev, SYS_RES_IRQ, &rid, (RF_SHAREABLE | RF_ACTIVE)); if (nic->msix_entries[irq].irq_res == NULL) { device_printf(nic->dev, "Could not allocate CQ interrupt %d for VF%d\n", (irq - NICVF_INTR_ID_CQ), device_get_unit(nic->dev)); ret = ENXIO; goto error; } ret = bus_setup_intr(nic->dev, nic->msix_entries[irq].irq_res, (INTR_MPSAFE | INTR_TYPE_NET), nicvf_intr_handler, NULL, &nic->qs->cq[qidx], &nic->msix_entries[irq].handle); if (ret != 0) { device_printf(nic->dev, "Could not setup CQ interrupt %d for VF%d\n", (irq - NICVF_INTR_ID_CQ), device_get_unit(nic->dev)); goto error; } cpuid = (device_get_unit(nic->dev) * CMP_QUEUE_CNT) + qidx; cpuid %= mp_ncpus; /* * Save CPU ID for later use when system-wide RSS is enabled. * It will be used to pit the CQ task to the same CPU that got * interrupted. */ nic->qs->cq[qidx].cmp_cpuid = cpuid; if (bootverbose) { device_printf(nic->dev, "bind CQ%d IRQ to CPU%d\n", qidx, cpuid); } /* Bind interrupts to the given CPU */ bus_bind_intr(nic->dev, nic->msix_entries[irq].irq_res, cpuid); } /* Register RBDR interrupt */ for_each_rbdr_irq(irq) { if (irq >= (NICVF_INTR_ID_RBDR + nic->qs->rbdr_cnt)) break; rid = irq + 1; nic->msix_entries[irq].irq_res = bus_alloc_resource_any(nic->dev, SYS_RES_IRQ, &rid, (RF_SHAREABLE | RF_ACTIVE)); if (nic->msix_entries[irq].irq_res == NULL) { device_printf(nic->dev, "Could not allocate RBDR interrupt %d for VF%d\n", (irq - NICVF_INTR_ID_RBDR), device_get_unit(nic->dev)); ret = ENXIO; goto error; } ret = bus_setup_intr(nic->dev, nic->msix_entries[irq].irq_res, (INTR_MPSAFE | INTR_TYPE_NET), NULL, nicvf_rbdr_intr_handler, nic, &nic->msix_entries[irq].handle); if (ret != 0) { device_printf(nic->dev, "Could not setup RBDR interrupt %d for VF%d\n", (irq - NICVF_INTR_ID_RBDR), device_get_unit(nic->dev)); goto error; } } /* Register QS error interrupt */ irq = NICVF_INTR_ID_QS_ERR; rid = irq + 1; nic->msix_entries[irq].irq_res = bus_alloc_resource_any(nic->dev, SYS_RES_IRQ, &rid, (RF_SHAREABLE | RF_ACTIVE)); if (nic->msix_entries[irq].irq_res == NULL) { device_printf(nic->dev, "Could not allocate QS Error interrupt for VF%d\n", device_get_unit(nic->dev)); ret = ENXIO; goto error; } ret = bus_setup_intr(nic->dev, nic->msix_entries[irq].irq_res, (INTR_MPSAFE | INTR_TYPE_NET), NULL, nicvf_qs_err_intr_handler, nic, &nic->msix_entries[irq].handle); if (ret != 0) { device_printf(nic->dev, "Could not setup QS Error interrupt for VF%d\n", device_get_unit(nic->dev)); goto error; } return (0); error: nicvf_release_net_interrupts(nic); return (ret); } static int nicvf_stop_locked(struct nicvf *nic) { struct ifnet *ifp; int qidx; struct queue_set *qs = nic->qs; union nic_mbx mbx = {}; NICVF_CORE_LOCK_ASSERT(nic); /* Stop callout. Can block here since holding SX lock */ callout_drain(&nic->stats_callout); ifp = nic->ifp; mbx.msg.msg = NIC_MBOX_MSG_SHUTDOWN; nicvf_send_msg_to_pf(nic, &mbx); /* Disable RBDR & QS error interrupts */ for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) { nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx); nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx); } nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0); nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0); /* Deactivate network interface */ if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); /* Free resources */ nicvf_config_data_transfer(nic, FALSE); /* Disable HW Qset */ nicvf_qset_config(nic, FALSE); /* disable mailbox interrupt */ nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0); return (0); } static void nicvf_update_stats(struct nicvf *nic) { int qidx; struct nicvf_hw_stats *stats = &nic->hw_stats; struct nicvf_drv_stats *drv_stats = &nic->drv_stats; struct queue_set *qs = nic->qs; #define GET_RX_STATS(reg) \ nicvf_reg_read(nic, NIC_VNIC_RX_STAT_0_13 | ((reg) << 3)) #define GET_TX_STATS(reg) \ nicvf_reg_read(nic, NIC_VNIC_TX_STAT_0_4 | ((reg) << 3)) stats->rx_bytes = GET_RX_STATS(RX_OCTS); stats->rx_ucast_frames = GET_RX_STATS(RX_UCAST); stats->rx_bcast_frames = GET_RX_STATS(RX_BCAST); stats->rx_mcast_frames = GET_RX_STATS(RX_MCAST); stats->rx_fcs_errors = GET_RX_STATS(RX_FCS); stats->rx_l2_errors = GET_RX_STATS(RX_L2ERR); stats->rx_drop_red = GET_RX_STATS(RX_RED); stats->rx_drop_red_bytes = GET_RX_STATS(RX_RED_OCTS); stats->rx_drop_overrun = GET_RX_STATS(RX_ORUN); stats->rx_drop_overrun_bytes = GET_RX_STATS(RX_ORUN_OCTS); stats->rx_drop_bcast = GET_RX_STATS(RX_DRP_BCAST); stats->rx_drop_mcast = GET_RX_STATS(RX_DRP_MCAST); stats->rx_drop_l3_bcast = GET_RX_STATS(RX_DRP_L3BCAST); stats->rx_drop_l3_mcast = GET_RX_STATS(RX_DRP_L3MCAST); stats->tx_bytes_ok = GET_TX_STATS(TX_OCTS); stats->tx_ucast_frames_ok = GET_TX_STATS(TX_UCAST); stats->tx_bcast_frames_ok = GET_TX_STATS(TX_BCAST); stats->tx_mcast_frames_ok = GET_TX_STATS(TX_MCAST); stats->tx_drops = GET_TX_STATS(TX_DROP); drv_stats->tx_frames_ok = stats->tx_ucast_frames_ok + stats->tx_bcast_frames_ok + stats->tx_mcast_frames_ok; drv_stats->rx_drops = stats->rx_drop_red + stats->rx_drop_overrun; drv_stats->tx_drops = stats->tx_drops; /* Update RQ and SQ stats */ for (qidx = 0; qidx < qs->rq_cnt; qidx++) nicvf_update_rq_stats(nic, qidx); for (qidx = 0; qidx < qs->sq_cnt; qidx++) nicvf_update_sq_stats(nic, qidx); } static void nicvf_tick_stats(void *arg) { struct nicvf *nic; nic = (struct nicvf *)arg; /* Read the statistics */ nicvf_update_stats(nic); callout_reset(&nic->stats_callout, hz, nicvf_tick_stats, nic); } Index: head/sys/dev/vnic/thunder_bgx.c =================================================================== --- head/sys/dev/vnic/thunder_bgx.c (revision 300293) +++ head/sys/dev/vnic/thunder_bgx.c (revision 300294) @@ -1,1135 +1,1136 @@ /* * Copyright (C) 2015 Cavium Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "thunder_bgx.h" #include "thunder_bgx_var.h" #include "nic_reg.h" #include "nic.h" #include "lmac_if.h" #define THUNDER_BGX_DEVSTR "ThunderX BGX Ethernet I/O Interface" MALLOC_DEFINE(M_BGX, "thunder_bgx", "ThunderX BGX dynamic memory"); #define BGX_NODE_ID_MASK 0x1 #define BGX_NODE_ID_SHIFT 24 #define DRV_NAME "thunder-BGX" #define DRV_VERSION "1.0" static int bgx_init_phy(struct bgx *); static struct bgx *bgx_vnic[MAX_BGX_THUNDER]; static int lmac_count __unused; /* Total no of LMACs in system */ static int bgx_xaui_check_link(struct lmac *lmac); static void bgx_get_qlm_mode(struct bgx *); static void bgx_init_hw(struct bgx *); static int bgx_lmac_enable(struct bgx *, uint8_t); static void bgx_lmac_disable(struct bgx *, uint8_t); static int thunder_bgx_probe(device_t); static int thunder_bgx_attach(device_t); static int thunder_bgx_detach(device_t); static device_method_t thunder_bgx_methods[] = { /* Device interface */ DEVMETHOD(device_probe, thunder_bgx_probe), DEVMETHOD(device_attach, thunder_bgx_attach), DEVMETHOD(device_detach, thunder_bgx_detach), DEVMETHOD_END, }; static driver_t thunder_bgx_driver = { "bgx", thunder_bgx_methods, sizeof(struct lmac), }; static devclass_t thunder_bgx_devclass; DRIVER_MODULE(thunder_bgx, pci, thunder_bgx_driver, thunder_bgx_devclass, 0, 0); +MODULE_VERSION(thunder_bgx, 1); MODULE_DEPEND(thunder_bgx, pci, 1, 1, 1); MODULE_DEPEND(thunder_bgx, ether, 1, 1, 1); -MODULE_DEPEND(thunder_bgx, octeon_mdio, 1, 1, 1); +MODULE_DEPEND(thunder_bgx, thunder_mdio, 1, 1, 1); static int thunder_bgx_probe(device_t dev) { uint16_t vendor_id; uint16_t device_id; vendor_id = pci_get_vendor(dev); device_id = pci_get_device(dev); if (vendor_id == PCI_VENDOR_ID_CAVIUM && device_id == PCI_DEVICE_ID_THUNDER_BGX) { device_set_desc(dev, THUNDER_BGX_DEVSTR); return (BUS_PROBE_DEFAULT); } return (ENXIO); } static int thunder_bgx_attach(device_t dev) { struct bgx *bgx; uint8_t lmac; int err; int rid; bgx = malloc(sizeof(*bgx), M_BGX, (M_WAITOK | M_ZERO)); bgx->dev = dev; /* Enable bus mastering */ pci_enable_busmaster(dev); /* Allocate resources - configuration registers */ rid = PCIR_BAR(PCI_CFG_REG_BAR_NUM); bgx->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (bgx->reg_base == NULL) { device_printf(dev, "Could not allocate CSR memory space\n"); err = ENXIO; goto err_disable_device; } bgx->bgx_id = (rman_get_start(bgx->reg_base) >> BGX_NODE_ID_SHIFT) & BGX_NODE_ID_MASK; bgx->bgx_id += nic_get_node_id(bgx->reg_base) * MAX_BGX_PER_CN88XX; bgx_vnic[bgx->bgx_id] = bgx; bgx_get_qlm_mode(bgx); err = bgx_init_phy(bgx); if (err != 0) goto err_free_res; bgx_init_hw(bgx); /* Enable all LMACs */ for (lmac = 0; lmac < bgx->lmac_count; lmac++) { err = bgx_lmac_enable(bgx, lmac); if (err) { device_printf(dev, "BGX%d failed to enable lmac%d\n", bgx->bgx_id, lmac); goto err_free_res; } } return (0); err_free_res: bgx_vnic[bgx->bgx_id] = NULL; bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(bgx->reg_base), bgx->reg_base); err_disable_device: free(bgx, M_BGX); pci_disable_busmaster(dev); return (err); } static int thunder_bgx_detach(device_t dev) { struct lmac *lmac; struct bgx *bgx; uint8_t lmacid; lmac = device_get_softc(dev); bgx = lmac->bgx; /* Disable all LMACs */ for (lmacid = 0; lmacid < bgx->lmac_count; lmacid++) bgx_lmac_disable(bgx, lmacid); return (0); } /* Register read/write APIs */ static uint64_t bgx_reg_read(struct bgx *bgx, uint8_t lmac, uint64_t offset) { bus_space_handle_t addr; addr = ((uint32_t)lmac << 20) + offset; return (bus_read_8(bgx->reg_base, addr)); } static void bgx_reg_write(struct bgx *bgx, uint8_t lmac, uint64_t offset, uint64_t val) { bus_space_handle_t addr; addr = ((uint32_t)lmac << 20) + offset; bus_write_8(bgx->reg_base, addr, val); } static void bgx_reg_modify(struct bgx *bgx, uint8_t lmac, uint64_t offset, uint64_t val) { bus_space_handle_t addr; addr = ((uint32_t)lmac << 20) + offset; bus_write_8(bgx->reg_base, addr, val | bus_read_8(bgx->reg_base, addr)); } static int bgx_poll_reg(struct bgx *bgx, uint8_t lmac, uint64_t reg, uint64_t mask, boolean_t zero) { int timeout = 10; uint64_t reg_val; while (timeout) { reg_val = bgx_reg_read(bgx, lmac, reg); if (zero && !(reg_val & mask)) return (0); if (!zero && (reg_val & mask)) return (0); DELAY(100); timeout--; } return (ETIMEDOUT); } /* Return number of BGX present in HW */ u_int bgx_get_map(int node) { int i; u_int map = 0; for (i = 0; i < MAX_BGX_PER_CN88XX; i++) { if (bgx_vnic[(node * MAX_BGX_PER_CN88XX) + i]) map |= (1 << i); } return (map); } /* Return number of LMAC configured for this BGX */ int bgx_get_lmac_count(int node, int bgx_idx) { struct bgx *bgx; bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx]; if (bgx != NULL) return (bgx->lmac_count); return (0); } /* Returns the current link status of LMAC */ void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status) { struct bgx_link_status *link = (struct bgx_link_status *)status; struct bgx *bgx; struct lmac *lmac; bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx]; if (bgx == NULL) return; lmac = &bgx->lmac[lmacid]; link->link_up = lmac->link_up; link->duplex = lmac->last_duplex; link->speed = lmac->last_speed; } const uint8_t *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid) { struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx]; if (bgx != NULL) return (bgx->lmac[lmacid].mac); return (NULL); } void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const uint8_t *mac) { struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx]; if (bgx == NULL) return; memcpy(bgx->lmac[lmacid].mac, mac, ETHER_ADDR_LEN); } static void bgx_sgmii_change_link_state(struct lmac *lmac) { struct bgx *bgx = lmac->bgx; uint64_t cmr_cfg; uint64_t port_cfg = 0; uint64_t misc_ctl = 0; cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG); cmr_cfg &= ~CMR_EN; bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg); port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG); misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL); if (lmac->link_up) { misc_ctl &= ~PCS_MISC_CTL_GMX_ENO; port_cfg &= ~GMI_PORT_CFG_DUPLEX; port_cfg |= (lmac->last_duplex << 2); } else { misc_ctl |= PCS_MISC_CTL_GMX_ENO; } switch (lmac->last_speed) { case 10: port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */ port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */ port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */ misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK; misc_ctl |= 50; /* samp_pt */ bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64); bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0); break; case 100: port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */ port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */ port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */ misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK; misc_ctl |= 5; /* samp_pt */ bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64); bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0); break; case 1000: port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */ port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */ port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */ misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK; misc_ctl |= 1; /* samp_pt */ bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512); if (lmac->last_duplex) bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0); else bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 8192); break; default: break; } bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl); bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg); port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG); /* renable lmac */ cmr_cfg |= CMR_EN; bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg); } static void bgx_lmac_handler(void *arg) { struct lmac *lmac; int link, duplex, speed; int link_changed = 0; int err; lmac = (struct lmac *)arg; err = LMAC_MEDIA_STATUS(lmac->phy_if_dev, lmac->lmacid, &link, &duplex, &speed); if (err != 0) goto out; if (!link && lmac->last_link) link_changed = -1; if (link && (lmac->last_duplex != duplex || lmac->last_link != link || lmac->last_speed != speed)) { link_changed = 1; } lmac->last_link = link; lmac->last_speed = speed; lmac->last_duplex = duplex; if (!link_changed) goto out; if (link_changed > 0) lmac->link_up = true; else lmac->link_up = false; if (lmac->is_sgmii) bgx_sgmii_change_link_state(lmac); else bgx_xaui_check_link(lmac); out: callout_reset(&lmac->check_link, hz * 2, bgx_lmac_handler, lmac); } uint64_t bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx) { struct bgx *bgx; bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx]; if (bgx == NULL) return (0); if (idx > 8) lmac = (0); return (bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8))); } uint64_t bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx) { struct bgx *bgx; bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx]; if (bgx == NULL) return (0); return (bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8))); } static void bgx_flush_dmac_addrs(struct bgx *bgx, int lmac) { uint64_t offset; while (bgx->lmac[lmac].dmac > 0) { offset = ((bgx->lmac[lmac].dmac - 1) * sizeof(uint64_t)) + (lmac * MAX_DMAC_PER_LMAC * sizeof(uint64_t)); bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + offset, 0); bgx->lmac[lmac].dmac--; } } void bgx_add_dmac_addr(uint64_t dmac, int node, int bgx_idx, int lmac) { uint64_t offset; struct bgx *bgx; #ifdef BGX_IN_PROMISCUOUS_MODE return; #endif bgx_idx += node * MAX_BGX_PER_CN88XX; bgx = bgx_vnic[bgx_idx]; if (!bgx) { device_printf(bgx->dev, "BGX%d not yet initialized, ignoring DMAC addition\n", bgx_idx); return; } dmac = dmac | (1UL << 48) | ((uint64_t)lmac << 49); /* Enable DMAC */ if (bgx->lmac[lmac].dmac == MAX_DMAC_PER_LMAC) { device_printf(bgx->dev, "Max DMAC filters for LMAC%d reached, ignoring\n", lmac); return; } if (bgx->lmac[lmac].dmac == MAX_DMAC_PER_LMAC_TNS_BYPASS_MODE) bgx->lmac[lmac].dmac = 1; offset = (bgx->lmac[lmac].dmac * sizeof(uint64_t)) + (lmac * MAX_DMAC_PER_LMAC * sizeof(uint64_t)); bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + offset, dmac); bgx->lmac[lmac].dmac++; bgx_reg_write(bgx, lmac, BGX_CMRX_RX_DMAC_CTL, (CAM_ACCEPT << 3) | (MCAST_MODE_CAM_FILTER << 1) | (BCAST_ACCEPT << 0)); } /* Configure BGX LMAC in internal loopback mode */ void bgx_lmac_internal_loopback(int node, int bgx_idx, int lmac_idx, boolean_t enable) { struct bgx *bgx; struct lmac *lmac; uint64_t cfg; bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx]; if (bgx == NULL) return; lmac = &bgx->lmac[lmac_idx]; if (lmac->is_sgmii) { cfg = bgx_reg_read(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL); if (enable) cfg |= PCS_MRX_CTL_LOOPBACK1; else cfg &= ~PCS_MRX_CTL_LOOPBACK1; bgx_reg_write(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL, cfg); } else { cfg = bgx_reg_read(bgx, lmac_idx, BGX_SPUX_CONTROL1); if (enable) cfg |= SPU_CTL_LOOPBACK; else cfg &= ~SPU_CTL_LOOPBACK; bgx_reg_write(bgx, lmac_idx, BGX_SPUX_CONTROL1, cfg); } } static int bgx_lmac_sgmii_init(struct bgx *bgx, int lmacid) { uint64_t cfg; bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30); /* max packet size */ bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE); /* Disable frame alignment if using preamble */ cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND); if (cfg & 1) bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0); /* Enable lmac */ bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN); /* PCS reset */ bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET); if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET, TRUE) != 0) { device_printf(bgx->dev, "BGX PCS reset not completed\n"); return (ENXIO); } /* power down, reset autoneg, autoneg enable */ cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL); cfg &= ~PCS_MRX_CTL_PWR_DN; cfg |= (PCS_MRX_CTL_RST_AN | PCS_MRX_CTL_AN_EN); bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg); if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS, PCS_MRX_STATUS_AN_CPT, FALSE) != 0) { device_printf(bgx->dev, "BGX AN_CPT not completed\n"); return (ENXIO); } return (0); } static int bgx_lmac_xaui_init(struct bgx *bgx, int lmacid, int lmac_type) { uint64_t cfg; /* Reset SPU */ bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET); if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, TRUE) != 0) { device_printf(bgx->dev, "BGX SPU reset not completed\n"); return (ENXIO); } /* Disable LMAC */ cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG); cfg &= ~CMR_EN; bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg); bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER); /* Set interleaved running disparity for RXAUI */ if (bgx->lmac_type != BGX_MODE_RXAUI) { bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL, SPU_MISC_CTL_RX_DIS); } else { bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL, SPU_MISC_CTL_RX_DIS | SPU_MISC_CTL_INTLV_RDISP); } /* clear all interrupts */ cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT); bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg); cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT); bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg); cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT); bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg); if (bgx->use_training) { bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00); bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00); bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00); /* training enable */ bgx_reg_modify(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN); } /* Append FCS to each packet */ bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D); /* Disable forward error correction */ cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL); cfg &= ~SPU_FEC_CTL_FEC_EN; bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg); /* Disable autoneg */ cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL); cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN); bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg); cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV); if (bgx->lmac_type == BGX_MODE_10G_KR) cfg |= (1 << 23); else if (bgx->lmac_type == BGX_MODE_40G_KR) cfg |= (1 << 24); else cfg &= ~((1 << 23) | (1 << 24)); cfg = cfg & (~((1UL << 25) | (1UL << 22) | (1UL << 12))); bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg); cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL); cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN; bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg); /* Enable lmac */ bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN); cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1); cfg &= ~SPU_CTL_LOW_POWER; bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg); cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL); cfg &= ~SMU_TX_CTL_UNI_EN; cfg |= SMU_TX_CTL_DIC_EN; bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg); /* take lmac_count into account */ bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1)); /* max packet size */ bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE); return (0); } static int bgx_xaui_check_link(struct lmac *lmac) { struct bgx *bgx = lmac->bgx; int lmacid = lmac->lmacid; int lmac_type = bgx->lmac_type; uint64_t cfg; bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL, SPU_MISC_CTL_RX_DIS); if (bgx->use_training) { cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT); if ((cfg & (1UL << 13)) == 0) { cfg = (1UL << 13) | (1UL << 14); bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg); cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL); cfg |= (1UL << 0); bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg); return (ENXIO); } } /* wait for PCS to come out of reset */ if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, TRUE) != 0) { device_printf(bgx->dev, "BGX SPU reset not completed\n"); return (ENXIO); } if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) || (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) { if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1, SPU_BR_STATUS_BLK_LOCK, FALSE)) { device_printf(bgx->dev, "SPU_BR_STATUS_BLK_LOCK not completed\n"); return (ENXIO); } } else { if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS, SPU_BX_STATUS_RX_ALIGN, FALSE) != 0) { device_printf(bgx->dev, "SPU_BX_STATUS_RX_ALIGN not completed\n"); return (ENXIO); } } /* Clear rcvflt bit (latching high) and read it back */ bgx_reg_modify(bgx, lmacid, BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT); if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) { device_printf(bgx->dev, "Receive fault, retry training\n"); if (bgx->use_training) { cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT); if ((cfg & (1UL << 13)) == 0) { cfg = (1UL << 13) | (1UL << 14); bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg); cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL); cfg |= (1UL << 0); bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg); return (ENXIO); } } return (ENXIO); } /* Wait for MAC RX to be ready */ if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_RX_CTL, SMU_RX_CTL_STATUS, TRUE) != 0) { device_printf(bgx->dev, "SMU RX link not okay\n"); return (ENXIO); } /* Wait for BGX RX to be idle */ if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, FALSE) != 0) { device_printf(bgx->dev, "SMU RX not idle\n"); return (ENXIO); } /* Wait for BGX TX to be idle */ if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, FALSE) != 0) { device_printf(bgx->dev, "SMU TX not idle\n"); return (ENXIO); } if ((bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) != 0) { device_printf(bgx->dev, "Receive fault\n"); return (ENXIO); } /* Receive link is latching low. Force it high and verify it */ bgx_reg_modify(bgx, lmacid, BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK); if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK, FALSE) != 0) { device_printf(bgx->dev, "SPU receive link down\n"); return (ENXIO); } cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL); cfg &= ~SPU_MISC_CTL_RX_DIS; bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg); return (0); } static void bgx_poll_for_link(void *arg) { struct lmac *lmac; uint64_t link; lmac = (struct lmac *)arg; /* Receive link is latching low. Force it high and verify it */ bgx_reg_modify(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK); bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK, false); link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1); if (link & SPU_STATUS1_RCV_LNK) { lmac->link_up = 1; if (lmac->bgx->lmac_type == BGX_MODE_XLAUI) lmac->last_speed = 40000; else lmac->last_speed = 10000; lmac->last_duplex = 1; } else { lmac->link_up = 0; } if (lmac->last_link != lmac->link_up) { lmac->last_link = lmac->link_up; if (lmac->link_up) bgx_xaui_check_link(lmac); } callout_reset(&lmac->check_link, hz * 2, bgx_poll_for_link, lmac); } static int bgx_lmac_enable(struct bgx *bgx, uint8_t lmacid) { uint64_t __unused dmac_bcast = (1UL << 48) - 1; struct lmac *lmac; uint64_t cfg; lmac = &bgx->lmac[lmacid]; lmac->bgx = bgx; if (bgx->lmac_type == BGX_MODE_SGMII) { lmac->is_sgmii = 1; if (bgx_lmac_sgmii_init(bgx, lmacid) != 0) return -1; } else { lmac->is_sgmii = 0; if (bgx_lmac_xaui_init(bgx, lmacid, bgx->lmac_type)) return -1; } if (lmac->is_sgmii) { cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND); cfg |= ((1UL << 2) | (1UL << 1)); /* FCS and PAD */ bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg); bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1); } else { cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND); cfg |= ((1UL << 2) | (1UL << 1)); /* FCS and PAD */ bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg); bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4); } /* Enable lmac */ bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN | CMR_PKT_RX_EN | CMR_PKT_TX_EN); /* Restore default cfg, incase low level firmware changed it */ bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03); /* Add broadcast MAC into all LMAC's DMAC filters */ bgx_add_dmac_addr(dmac_bcast, 0, bgx->bgx_id, lmacid); if ((bgx->lmac_type != BGX_MODE_XFI) && (bgx->lmac_type != BGX_MODE_XAUI) && (bgx->lmac_type != BGX_MODE_XLAUI) && (bgx->lmac_type != BGX_MODE_40G_KR) && (bgx->lmac_type != BGX_MODE_10G_KR)) { if (lmac->phy_if_dev == NULL) { device_printf(bgx->dev, "LMAC%d missing interface to PHY\n", lmacid); return (ENXIO); } if (LMAC_PHY_CONNECT(lmac->phy_if_dev, lmac->phyaddr, lmacid) != 0) { device_printf(bgx->dev, "LMAC%d could not connect to PHY\n", lmacid); return (ENXIO); } mtx_init(&lmac->check_link_mtx, "BGX link poll", NULL, MTX_DEF); callout_init_mtx(&lmac->check_link, &lmac->check_link_mtx, 0); mtx_lock(&lmac->check_link_mtx); bgx_lmac_handler(lmac); mtx_unlock(&lmac->check_link_mtx); } else { mtx_init(&lmac->check_link_mtx, "BGX link poll", NULL, MTX_DEF); callout_init_mtx(&lmac->check_link, &lmac->check_link_mtx, 0); mtx_lock(&lmac->check_link_mtx); bgx_poll_for_link(lmac); mtx_unlock(&lmac->check_link_mtx); } return (0); } static void bgx_lmac_disable(struct bgx *bgx, uint8_t lmacid) { struct lmac *lmac; uint64_t cmrx_cfg; lmac = &bgx->lmac[lmacid]; /* Stop callout */ callout_drain(&lmac->check_link); mtx_destroy(&lmac->check_link_mtx); cmrx_cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG); cmrx_cfg &= ~(1 << 15); bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cmrx_cfg); bgx_flush_dmac_addrs(bgx, lmacid); if ((bgx->lmac_type != BGX_MODE_XFI) && (bgx->lmac_type != BGX_MODE_XLAUI) && (bgx->lmac_type != BGX_MODE_40G_KR) && (bgx->lmac_type != BGX_MODE_10G_KR)) { if (lmac->phy_if_dev == NULL) { device_printf(bgx->dev, "LMAC%d missing interface to PHY\n", lmacid); return; } if (LMAC_PHY_DISCONNECT(lmac->phy_if_dev, lmac->phyaddr, lmacid) != 0) { device_printf(bgx->dev, "LMAC%d could not disconnect PHY\n", lmacid); return; } lmac->phy_if_dev = NULL; } } static void bgx_set_num_ports(struct bgx *bgx) { uint64_t lmac_count; switch (bgx->qlm_mode) { case QLM_MODE_SGMII: bgx->lmac_count = 4; bgx->lmac_type = BGX_MODE_SGMII; bgx->lane_to_sds = 0; break; case QLM_MODE_XAUI_1X4: bgx->lmac_count = 1; bgx->lmac_type = BGX_MODE_XAUI; bgx->lane_to_sds = 0xE4; break; case QLM_MODE_RXAUI_2X2: bgx->lmac_count = 2; bgx->lmac_type = BGX_MODE_RXAUI; bgx->lane_to_sds = 0xE4; break; case QLM_MODE_XFI_4X1: bgx->lmac_count = 4; bgx->lmac_type = BGX_MODE_XFI; bgx->lane_to_sds = 0; break; case QLM_MODE_XLAUI_1X4: bgx->lmac_count = 1; bgx->lmac_type = BGX_MODE_XLAUI; bgx->lane_to_sds = 0xE4; break; case QLM_MODE_10G_KR_4X1: bgx->lmac_count = 4; bgx->lmac_type = BGX_MODE_10G_KR; bgx->lane_to_sds = 0; bgx->use_training = 1; break; case QLM_MODE_40G_KR4_1X4: bgx->lmac_count = 1; bgx->lmac_type = BGX_MODE_40G_KR; bgx->lane_to_sds = 0xE4; bgx->use_training = 1; break; default: bgx->lmac_count = 0; break; } /* * Check if low level firmware has programmed LMAC count * based on board type, if yes consider that otherwise * the default static values */ lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7; if (lmac_count != 4) bgx->lmac_count = lmac_count; } static void bgx_init_hw(struct bgx *bgx) { int i; bgx_set_num_ports(bgx); bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP); if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS)) device_printf(bgx->dev, "BGX%d BIST failed\n", bgx->bgx_id); /* Set lmac type and lane2serdes mapping */ for (i = 0; i < bgx->lmac_count; i++) { if (bgx->lmac_type == BGX_MODE_RXAUI) { if (i) bgx->lane_to_sds = 0x0e; else bgx->lane_to_sds = 0x04; bgx_reg_write(bgx, i, BGX_CMRX_CFG, (bgx->lmac_type << 8) | bgx->lane_to_sds); continue; } bgx_reg_write(bgx, i, BGX_CMRX_CFG, (bgx->lmac_type << 8) | (bgx->lane_to_sds + i)); bgx->lmac[i].lmacid_bd = lmac_count; lmac_count++; } bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count); bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count); /* Set the backpressure AND mask */ for (i = 0; i < bgx->lmac_count; i++) { bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND, ((1UL << MAX_BGX_CHANS_PER_LMAC) - 1) << (i * MAX_BGX_CHANS_PER_LMAC)); } /* Disable all MAC filtering */ for (i = 0; i < RX_DMAC_COUNT; i++) bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00); /* Disable MAC steering (NCSI traffic) */ for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++) bgx_reg_write(bgx, 0, BGX_CMR_RX_STREERING + (i * 8), 0x00); } static void bgx_get_qlm_mode(struct bgx *bgx) { device_t dev = bgx->dev;; int lmac_type; int train_en; /* Read LMAC0 type to figure out QLM mode * This is configured by low level firmware */ lmac_type = bgx_reg_read(bgx, 0, BGX_CMRX_CFG); lmac_type = (lmac_type >> 8) & 0x07; train_en = bgx_reg_read(bgx, 0, BGX_SPUX_BR_PMD_CRTL) & SPU_PMD_CRTL_TRAIN_EN; switch (lmac_type) { case BGX_MODE_SGMII: bgx->qlm_mode = QLM_MODE_SGMII; if (bootverbose) { device_printf(dev, "BGX%d QLM mode: SGMII\n", bgx->bgx_id); } break; case BGX_MODE_XAUI: bgx->qlm_mode = QLM_MODE_XAUI_1X4; if (bootverbose) { device_printf(dev, "BGX%d QLM mode: XAUI\n", bgx->bgx_id); } break; case BGX_MODE_RXAUI: bgx->qlm_mode = QLM_MODE_RXAUI_2X2; if (bootverbose) { device_printf(dev, "BGX%d QLM mode: RXAUI\n", bgx->bgx_id); } break; case BGX_MODE_XFI: if (!train_en) { bgx->qlm_mode = QLM_MODE_XFI_4X1; if (bootverbose) { device_printf(dev, "BGX%d QLM mode: XFI\n", bgx->bgx_id); } } else { bgx->qlm_mode = QLM_MODE_10G_KR_4X1; if (bootverbose) { device_printf(dev, "BGX%d QLM mode: 10G_KR\n", bgx->bgx_id); } } break; case BGX_MODE_XLAUI: if (!train_en) { bgx->qlm_mode = QLM_MODE_XLAUI_1X4; if (bootverbose) { device_printf(dev, "BGX%d QLM mode: XLAUI\n", bgx->bgx_id); } } else { bgx->qlm_mode = QLM_MODE_40G_KR4_1X4; if (bootverbose) { device_printf(dev, "BGX%d QLM mode: 40G_KR4\n", bgx->bgx_id); } } break; default: bgx->qlm_mode = QLM_MODE_SGMII; if (bootverbose) { device_printf(dev, "BGX%d QLM default mode: SGMII\n", bgx->bgx_id); } } } static int bgx_init_phy(struct bgx *bgx) { int err; /* By default we fail */ err = ENXIO; #ifdef FDT err = bgx_fdt_init_phy(bgx); #endif #ifdef ACPI if (err != 0) { /* ARM64TODO: Add ACPI function here */ } #endif return (err); } Index: head/sys/dev/vnic/thunder_mdio.c =================================================================== --- head/sys/dev/vnic/thunder_mdio.c (revision 300293) +++ head/sys/dev/vnic/thunder_mdio.c (revision 300294) @@ -1,512 +1,514 @@ /*- * Copyright (c) 2015 The FreeBSD Foundation * All rights reserved. * * This software was developed by Semihalf under * the sponsorship of the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "thunder_mdio_var.h" #include "lmac_if.h" #include "miibus_if.h" #define REG_BASE_RID 0 #define SMI_CMD 0x00 #define SMI_CMD_PHY_REG_ADR_SHIFT (0) #define SMI_CMD_PHY_REG_ADR_MASK (0x1FUL << SMI_CMD_PHY_REG_ADR_SHIFT) #define SMI_CMD_PHY_ADR_SHIFT (8) #define SMI_CMD_PHY_ADR_MASK (0x1FUL << SMI_CMD_PHY_ADR_SHIFT) #define SMI_CMD_PHY_OP_MASK (0x3UL << 16) #define SMI_CMD_PHY_OP_C22_READ (0x1UL << 16) #define SMI_CMD_PHY_OP_C22_WRITE (0x0UL << 16) #define SMI_CMD_PHY_OP_C45_READ (0x3UL << 16) #define SMI_CMD_PHY_OP_C45_WRITE (0x1UL << 16) #define SMI_CMD_PHY_OP_C45_ADDR (0x0UL << 16) #define SMI_WR_DAT 0x08 #define SMI_WR_DAT_PENDING (1UL << 17) #define SMI_WR_DAT_VAL (1UL << 16) #define SMI_WR_DAT_DAT_MASK (0xFFFFUL << 0) #define SMI_RD_DAT 0x10 #define SMI_RD_DAT_PENDING (1UL << 17) #define SMI_RD_DAT_VAL (1UL << 16) #define SMI_RD_DAT_DAT_MASK (0xFFFFUL << 0) #define SMI_CLK 0x18 #define SMI_CLK_PREAMBLE (1UL << 12) #define SMI_CLK_MODE (1UL << 24) #define SMI_EN 0x20 #define SMI_EN_EN (1UL << 0) /* Enabele interface */ #define SMI_DRV_CTL 0x28 static int thunder_mdio_detach(device_t); static int thunder_mdio_read(device_t, int, int); static int thunder_mdio_write(device_t, int, int, int); static int thunder_ifmedia_change_stub(struct ifnet *); static void thunder_ifmedia_status_stub(struct ifnet *, struct ifmediareq *); static int thunder_mdio_media_status(device_t, int, int *, int *, int *); static int thunder_mdio_media_change(device_t, int, int, int, int); static int thunder_mdio_phy_connect(device_t, int, int); static int thunder_mdio_phy_disconnect(device_t, int, int); static device_method_t thunder_mdio_methods[] = { /* Device interface */ DEVMETHOD(device_detach, thunder_mdio_detach), /* LMAC interface */ DEVMETHOD(lmac_media_status, thunder_mdio_media_status), DEVMETHOD(lmac_media_change, thunder_mdio_media_change), DEVMETHOD(lmac_phy_connect, thunder_mdio_phy_connect), DEVMETHOD(lmac_phy_disconnect, thunder_mdio_phy_disconnect), /* MII interface */ DEVMETHOD(miibus_readreg, thunder_mdio_read), DEVMETHOD(miibus_writereg, thunder_mdio_write), /* End */ DEVMETHOD_END }; DEFINE_CLASS_0(thunder_mdio, thunder_mdio_driver, thunder_mdio_methods, sizeof(struct thunder_mdio_softc)); DRIVER_MODULE(miibus, thunder_mdio, miibus_driver, miibus_devclass, 0, 0); +MODULE_VERSION(thunder_mdio, 1); MODULE_DEPEND(thunder_mdio, ether, 1, 1, 1); MODULE_DEPEND(thunder_mdio, miibus, 1, 1, 1); +MODULE_DEPEND(thunder_mdio, mrmlbus, 1, 1, 1); MALLOC_DEFINE(M_THUNDER_MDIO, "ThunderX MDIO", "Cavium ThunderX MDIO dynamic memory"); #define MDIO_LOCK_INIT(sc, name) \ mtx_init(&(sc)->mtx, name, NULL, MTX_DEF) #define MDIO_LOCK_DESTROY(sc) \ mtx_destroy(&(sc)->mtx) #define MDIO_LOCK(sc) mtx_lock(&(sc)->mtx) #define MDIO_UNLOCK(sc) mtx_unlock(&(sc)->mtx) #define MDIO_LOCK_ASSERT(sc) \ mtx_assert(&(sc)->mtx, MA_OWNED) #define mdio_reg_read(sc, reg) \ bus_read_8((sc)->reg_base, (reg)) #define mdio_reg_write(sc, reg, val) \ bus_write_8((sc)->reg_base, (reg), (val)) int thunder_mdio_attach(device_t dev) { struct thunder_mdio_softc *sc; int rid; sc = device_get_softc(dev); sc->dev = dev; /* Allocate memory resources */ rid = REG_BASE_RID; sc->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->reg_base == NULL) { device_printf(dev, "Could not allocate memory\n"); return (ENXIO); } TAILQ_INIT(&sc->phy_desc_head); MDIO_LOCK_INIT(sc, "ThunderX MDIO lock"); /* Enable SMI/MDIO interface */ mdio_reg_write(sc, SMI_EN, SMI_EN_EN); return (0); } static int thunder_mdio_detach(device_t dev) { struct thunder_mdio_softc *sc; sc = device_get_softc(dev); if (sc->reg_base != NULL) { bus_release_resource(dev, SYS_RES_MEMORY, REG_BASE_RID, sc->reg_base); } return (0); } static __inline void thunder_mdio_set_mode(struct thunder_mdio_softc *sc, enum thunder_mdio_mode mode) { uint64_t smi_clk; if (sc->mode == mode) return; /* Set mode, IEEE CLAUSE 22 or IEEE CAUSE 45 */ smi_clk = mdio_reg_read(sc, SMI_CLK); if (mode == MODE_IEEE_C22) smi_clk &= ~SMI_CLK_MODE; else smi_clk |= SMI_CLK_MODE; /* Enable sending 32 bit preable on SMI transactions */ smi_clk |= SMI_CLK_PREAMBLE; /* Saved setings */ mdio_reg_write(sc, SMI_CLK, smi_clk); sc->mode = mode; } static int thunder_mdio_c45_addr(struct thunder_mdio_softc *sc, int phy, int reg) { uint64_t smi_cmd, smi_wr_dat; ssize_t timeout; thunder_mdio_set_mode(sc, MODE_IEEE_C45); /* Prepare data for transmission */ mdio_reg_write(sc, SMI_WR_DAT, reg & SMI_WR_DAT_DAT_MASK); /* * Assemble command */ smi_cmd = 0; /* Set opcode */ smi_cmd |= SMI_CMD_PHY_OP_C45_WRITE; /* Set PHY address */ smi_cmd |= ((phy << SMI_CMD_PHY_ADR_SHIFT) & SMI_CMD_PHY_ADR_MASK); /* Set PHY register offset */ smi_cmd |= ((reg << SMI_CMD_PHY_REG_ADR_SHIFT) & SMI_CMD_PHY_REG_ADR_MASK); mdio_reg_write(sc, SMI_CMD, smi_cmd); for (timeout = 1000; timeout > 0; timeout--) { smi_wr_dat = mdio_reg_read(sc, SMI_WR_DAT); if (smi_wr_dat & SMI_WR_DAT_PENDING) DELAY(1000); else break; } if (timeout <= 0) return (EIO); else { /* Return 0 on success */ return (0); } } static int thunder_mdio_read(device_t dev, int phy, int reg) { struct thunder_mdio_softc *sc; uint64_t smi_cmd, smi_rd_dat; ssize_t timeout; int err; sc = device_get_softc(dev); /* XXX Always C22 - for <= 1Gbps only */ thunder_mdio_set_mode(sc, MODE_IEEE_C22); /* * Assemble command */ smi_cmd = 0; /* Set opcode */ if (sc->mode == MODE_IEEE_C22) smi_cmd |= SMI_CMD_PHY_OP_C22_READ; else { smi_cmd |= SMI_CMD_PHY_OP_C45_READ; err = thunder_mdio_c45_addr(sc, phy, reg); if (err != 0) return (err); reg = (reg >> 16) & 0x1F; } /* Set PHY address */ smi_cmd |= ((phy << SMI_CMD_PHY_ADR_SHIFT) & SMI_CMD_PHY_ADR_MASK); /* Set PHY register offset */ smi_cmd |= ((reg << SMI_CMD_PHY_REG_ADR_SHIFT) & SMI_CMD_PHY_REG_ADR_MASK); mdio_reg_write(sc, SMI_CMD, smi_cmd); for (timeout = 1000; timeout > 0; timeout--) { smi_rd_dat = mdio_reg_read(sc, SMI_RD_DAT); if (smi_rd_dat & SMI_RD_DAT_PENDING) DELAY(1000); else break; } if (smi_rd_dat & SMI_RD_DAT_VAL) return (smi_rd_dat & SMI_RD_DAT_DAT_MASK); else { /* Return 0 on error */ return (0); } } static int thunder_mdio_write(device_t dev, int phy, int reg, int data) { struct thunder_mdio_softc *sc; uint64_t smi_cmd, smi_wr_dat; ssize_t timeout; sc = device_get_softc(dev); /* XXX Always C22 - for <= 1Gbps only */ thunder_mdio_set_mode(sc, MODE_IEEE_C22); /* Prepare data for transmission */ mdio_reg_write(sc, SMI_WR_DAT, data & SMI_WR_DAT_DAT_MASK); /* * Assemble command */ smi_cmd = 0; /* Set opcode */ if (sc->mode == MODE_IEEE_C22) smi_cmd |= SMI_CMD_PHY_OP_C22_WRITE; else smi_cmd |= SMI_CMD_PHY_OP_C45_WRITE; /* Set PHY address */ smi_cmd |= ((phy << SMI_CMD_PHY_ADR_SHIFT) & SMI_CMD_PHY_ADR_MASK); /* Set PHY register offset */ smi_cmd |= ((reg << SMI_CMD_PHY_REG_ADR_SHIFT) & SMI_CMD_PHY_REG_ADR_MASK); mdio_reg_write(sc, SMI_CMD, smi_cmd); for (timeout = 1000; timeout > 0; timeout--) { smi_wr_dat = mdio_reg_read(sc, SMI_WR_DAT); if (smi_wr_dat & SMI_WR_DAT_PENDING) DELAY(1000); else break; } if (timeout <= 0) return (EIO); else { /* Return 0 on success */ return (0); } } static int thunder_ifmedia_change_stub(struct ifnet *ifp __unused) { /* Will never be called by if_media */ return (0); } static void thunder_ifmedia_status_stub(struct ifnet *ifp __unused, struct ifmediareq *ifmr __unused) { /* Will never be called by if_media */ } static __inline struct phy_desc * get_phy_desc(struct thunder_mdio_softc *sc, int lmacid) { struct phy_desc *pd = NULL; MDIO_LOCK_ASSERT(sc); TAILQ_FOREACH(pd, &sc->phy_desc_head, phy_desc_list) { if (pd->lmacid == lmacid) break; } return (pd); } static int thunder_mdio_media_status(device_t dev, int lmacid, int *link, int *duplex, int *speed) { struct thunder_mdio_softc *sc; struct mii_data *mii_sc; struct phy_desc *pd; sc = device_get_softc(dev); MDIO_LOCK(sc); pd = get_phy_desc(sc, lmacid); if (pd == NULL) { /* Panic when invariants are enabled, fail otherwise. */ KASSERT(0, ("%s: no PHY descriptor for LMAC%d", __func__, lmacid)); MDIO_UNLOCK(sc); return (ENXIO); } mii_sc = device_get_softc(pd->miibus); mii_tick(mii_sc); if ((mii_sc->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == (IFM_ACTIVE | IFM_AVALID)) { /* Link is up */ *link = 1; } else *link = 0; switch (IFM_SUBTYPE(mii_sc->mii_media_active)) { case IFM_10_T: *speed = 10; break; case IFM_100_TX: *speed = 100; break; case IFM_1000_T: *speed = 1000; break; default: /* IFM_NONE */ *speed = 0; } if ((IFM_OPTIONS(mii_sc->mii_media_active) & IFM_FDX) != 0) *duplex = 1; else *duplex = 0; MDIO_UNLOCK(sc); return (0); } static int thunder_mdio_media_change(device_t dev, int lmacid, int link, int duplex, int speed) { return (EIO); } static int thunder_mdio_phy_connect(device_t dev, int lmacid, int phy) { struct thunder_mdio_softc *sc; struct phy_desc *pd; int err; sc = device_get_softc(dev); MDIO_LOCK(sc); pd = get_phy_desc(sc, lmacid); MDIO_UNLOCK(sc); if (pd == NULL) { pd = malloc(sizeof(*pd), M_THUNDER_MDIO, (M_NOWAIT | M_ZERO)); if (pd == NULL) return (ENOMEM); pd->ifp = if_alloc(IFT_ETHER); if (pd->ifp == NULL) { free(pd, M_THUNDER_MDIO); return (ENOMEM); } pd->lmacid = lmacid; } err = mii_attach(dev, &pd->miibus, pd->ifp, thunder_ifmedia_change_stub, thunder_ifmedia_status_stub, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); if (err != 0) { device_printf(dev, "Could not attach PHY%d\n", phy); if_free(pd->ifp); free(pd, M_THUNDER_MDIO); return (ENXIO); } MDIO_LOCK(sc); TAILQ_INSERT_TAIL(&sc->phy_desc_head, pd, phy_desc_list); MDIO_UNLOCK(sc); return (0); } static int thunder_mdio_phy_disconnect(device_t dev, int lmacid, int phy) { struct thunder_mdio_softc *sc; struct phy_desc *pd; sc = device_get_softc(dev); MDIO_LOCK(sc); pd = get_phy_desc(sc, lmacid); if (pd == NULL) { MDIO_UNLOCK(sc); return (EINVAL); } /* Remove this PHY descriptor from the list */ TAILQ_REMOVE(&sc->phy_desc_head, pd, phy_desc_list); /* Detach miibus */ bus_generic_detach(dev); device_delete_child(dev, pd->miibus); /* Free fake ifnet */ if_free(pd->ifp); /* Free memory under phy descriptor */ free(pd, M_THUNDER_MDIO); MDIO_UNLOCK(sc); return (0); } Index: head/sys/modules/vnic/Makefile =================================================================== --- head/sys/modules/vnic/Makefile (nonexistent) +++ head/sys/modules/vnic/Makefile (revision 300294) @@ -0,0 +1,10 @@ +# $FreeBSD$ + +SYSDIR?=${.CURDIR}/../.. +.include "${SYSDIR}/conf/kern.opts.mk" + +CFLAGS+= -DFDT + +SUBDIR = mrmlbus thunder_mdio thunder_bgx vnicpf vnicvf + +.include Property changes on: head/sys/modules/vnic/Makefile ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/modules/vnic/mrmlbus/Makefile =================================================================== --- head/sys/modules/vnic/mrmlbus/Makefile (nonexistent) +++ head/sys/modules/vnic/mrmlbus/Makefile (revision 300294) @@ -0,0 +1,16 @@ +# $FreeBSD$ + +SYSDIR?=${.CURDIR}/../../.. +.include "${SYSDIR}/conf/kern.opts.mk" + +S= ${.CURDIR}/../../.. + +.PATH: $S/dev/vnic + +KMOD= mrmlbus +SRCS= device_if.h bus_if.h opt_platform.h pci_if.h ofw_bus_if.h miibus_if.h lmac_if.h +SRCS+= mrml_bridge.c + +CFLAGS+= -DFDT + +.include Property changes on: head/sys/modules/vnic/mrmlbus/Makefile ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/modules/vnic/thunder_bgx/Makefile =================================================================== --- head/sys/modules/vnic/thunder_bgx/Makefile (nonexistent) +++ head/sys/modules/vnic/thunder_bgx/Makefile (revision 300294) @@ -0,0 +1,16 @@ +# $FreeBSD$ + +SYSDIR?=${.CURDIR}/../../.. +.include "${SYSDIR}/conf/kern.opts.mk" + +S= ${.CURDIR}/../../.. + +.PATH: $S/dev/vnic + +KMOD= thunder_bgx +SRCS= thunder_bgx.c thunder_bgx_fdt.c +SRCS+= opt_platform.h device_if.h bus_if.h pci_if.h lmac_if.h ofw_bus_if.h + +CFLAGS+= -DFDT + +.include Property changes on: head/sys/modules/vnic/thunder_bgx/Makefile ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/modules/vnic/thunder_mdio/Makefile =================================================================== --- head/sys/modules/vnic/thunder_mdio/Makefile (nonexistent) +++ head/sys/modules/vnic/thunder_mdio/Makefile (revision 300294) @@ -0,0 +1,16 @@ +# $FreeBSD$ + +SYSDIR?=${.CURDIR}/../../.. +.include "${SYSDIR}/conf/kern.opts.mk" + +S= ${.CURDIR}/../../.. + +.PATH: $S/dev/vnic + +KMOD= thunder_mdio +SRCS= opt_platform.h device_if.h bus_if.h pci_if.h ofw_bus_if.h miibus_if.h lmac_if.h +SRCS+= thunder_mdio.c thunder_mdio_fdt.c + +CFLAGS+= -DFDT + +.include Property changes on: head/sys/modules/vnic/thunder_mdio/Makefile ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/modules/vnic/vnicpf/Makefile =================================================================== --- head/sys/modules/vnic/vnicpf/Makefile (nonexistent) +++ head/sys/modules/vnic/vnicpf/Makefile (revision 300294) @@ -0,0 +1,16 @@ +# $FreeBSD$ + +SYSDIR?=${.CURDIR}/../../.. +.include "${SYSDIR}/conf/kern.opts.mk" + +S= ${.CURDIR}/../../.. + +.PATH: $S/dev/vnic + +KMOD= vnicpf +SRCS= pci_iov_if.h opt_platform.h device_if.h bus_if.h pci_if.h ofw_bus_if.h miibus_if.h lmac_if.h +SRCS+= nic_main.c + +CFLAGS+= -DFDT -DPCI_IOV + +.include Property changes on: head/sys/modules/vnic/vnicpf/Makefile ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/modules/vnic/vnicvf/Makefile =================================================================== --- head/sys/modules/vnic/vnicvf/Makefile (nonexistent) +++ head/sys/modules/vnic/vnicvf/Makefile (revision 300294) @@ -0,0 +1,16 @@ +# $FreeBSD$ + +SYSDIR?=${.CURDIR}/../../.. +.include "${SYSDIR}/conf/kern.opts.mk" + +S= ${.CURDIR}/../../.. + +.PATH: $S/dev/vnic + +KMOD= vnicvf +SRCS= nicvf_main.c nicvf_queues.c +SRCS+= opt_platform.h ofw_bus_if.h lmac_if.h miibus_if.h pci_if.h bus_if.h device_if.h opt_inet.h opt_inet6.h + +CFLAGS+= -DFDT -DPCI_IOV + +.include Property changes on: head/sys/modules/vnic/vnicvf/Makefile ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property