Index: head/sys/dev/vnic/nic.h =================================================================== --- head/sys/dev/vnic/nic.h (revision 299443) +++ head/sys/dev/vnic/nic.h (revision 299444) @@ -1,500 +1,519 @@ /* * Copyright (C) 2015 Cavium Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #ifndef NIC_H #define NIC_H /* PCI vendor ID */ #define PCI_VENDOR_ID_CAVIUM 0x177D /* PCI device IDs */ #define PCI_DEVICE_ID_THUNDER_NIC_PF 0xA01E #define PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF 0x0011 #define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034 #define PCI_DEVICE_ID_THUNDER_BGX 0xA026 /* PCI BAR nos */ #define PCI_CFG_REG_BAR_NUM 0 #define PCI_MSIX_REG_BAR_NUM 4 /* PCI revision IDs */ #define PCI_REVID_PASS2 8 /* NIC SRIOV VF count */ #define MAX_NUM_VFS_SUPPORTED 128 #define DEFAULT_NUM_VF_ENABLED 8 #define NIC_TNS_BYPASS_MODE 0 #define NIC_TNS_MODE 1 /* NIC priv flags */ #define NIC_SRIOV_ENABLED (1 << 0) #define NIC_TNS_ENABLED (1 << 1) /* ARM64TODO */ #if 0 /* VNIC HW optimiation features */ #define VNIC_RSS_SUPPORT #define VNIC_MULTI_QSET_SUPPORT #endif /* Min/Max packet size */ #define NIC_HW_MIN_FRS 64 #define NIC_HW_MAX_FRS 9200 /* 9216 max packet including FCS */ /* Max pkinds */ #define NIC_MAX_PKIND 16 /* * Rx Channels */ /* Receive channel configuration in TNS bypass mode * Below is configuration in TNS bypass mode * BGX0-LMAC0-CHAN0 - VNIC CHAN0 * BGX0-LMAC1-CHAN0 - VNIC CHAN16 * ... * BGX1-LMAC0-CHAN0 - VNIC CHAN128 * ... * BGX1-LMAC3-CHAN0 - VNIC CHAN174 */ #define NIC_INTF_COUNT 2 /* Interfaces btw VNIC and TNS/BGX */ #define NIC_CHANS_PER_INF 128 #define NIC_MAX_CHANS (NIC_INTF_COUNT * NIC_CHANS_PER_INF) #define NIC_CPI_COUNT 2048 /* No of channel parse indices */ /* TNS bypass mode: 1-1 mapping between VNIC and BGX:LMAC */ #define NIC_MAX_BGX MAX_BGX_PER_CN88XX #define NIC_CPI_PER_BGX (NIC_CPI_COUNT / NIC_MAX_BGX) #define NIC_MAX_CPI_PER_LMAC 64 /* Max when CPI_ALG is IP diffserv */ #define NIC_RSSI_PER_BGX (NIC_RSSI_COUNT / NIC_MAX_BGX) /* Tx scheduling */ #define NIC_MAX_TL4 1024 #define NIC_MAX_TL4_SHAPERS 256 /* 1 shaper for 4 TL4s */ #define NIC_MAX_TL3 256 #define NIC_MAX_TL3_SHAPERS 64 /* 1 shaper for 4 TL3s */ #define NIC_MAX_TL2 64 #define NIC_MAX_TL2_SHAPERS 2 /* 1 shaper for 32 TL2s */ #define NIC_MAX_TL1 2 /* TNS bypass mode */ #define NIC_TL2_PER_BGX 32 #define NIC_TL4_PER_BGX (NIC_MAX_TL4 / NIC_MAX_BGX) #define NIC_TL4_PER_LMAC (NIC_MAX_TL4 / NIC_CHANS_PER_INF) /* NIC VF Interrupts */ #define NICVF_INTR_CQ 0 #define NICVF_INTR_SQ 1 #define NICVF_INTR_RBDR 2 #define NICVF_INTR_PKT_DROP 3 #define NICVF_INTR_TCP_TIMER 4 #define NICVF_INTR_MBOX 5 #define NICVF_INTR_QS_ERR 6 #define NICVF_INTR_CQ_SHIFT 0 #define NICVF_INTR_SQ_SHIFT 8 #define NICVF_INTR_RBDR_SHIFT 16 #define NICVF_INTR_PKT_DROP_SHIFT 20 #define NICVF_INTR_TCP_TIMER_SHIFT 21 #define NICVF_INTR_MBOX_SHIFT 22 #define NICVF_INTR_QS_ERR_SHIFT 23 #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT) #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT) #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT) #define NICVF_INTR_PKT_DROP_MASK (1 << NICVF_INTR_PKT_DROP_SHIFT) #define NICVF_INTR_TCP_TIMER_MASK (1 << NICVF_INTR_TCP_TIMER_SHIFT) #define NICVF_INTR_MBOX_MASK (1 << NICVF_INTR_MBOX_SHIFT) #define NICVF_INTR_QS_ERR_MASK (1 << NICVF_INTR_QS_ERR_SHIFT) /* MSI-X interrupts */ #define NIC_PF_MSIX_VECTORS 10 #define NIC_VF_MSIX_VECTORS 20 #define NIC_PF_INTR_ID_ECC0_SBE 0 #define NIC_PF_INTR_ID_ECC0_DBE 1 #define NIC_PF_INTR_ID_ECC1_SBE 2 #define NIC_PF_INTR_ID_ECC1_DBE 3 #define NIC_PF_INTR_ID_ECC2_SBE 4 #define NIC_PF_INTR_ID_ECC2_DBE 5 #define NIC_PF_INTR_ID_ECC3_SBE 6 #define NIC_PF_INTR_ID_ECC3_DBE 7 #define NIC_PF_INTR_ID_MBOX0 8 #define NIC_PF_INTR_ID_MBOX1 9 struct msix_entry { struct resource * irq_res; void * handle; }; /* * Global timer for CQ timer thresh interrupts * Calculated for SCLK of 700Mhz * value written should be a 1/16th of what is expected * * 1 tick per 0.05usec = value of 2.2 * This 10% would be covered in CQ timer thresh value */ #define NICPF_CLK_PER_INT_TICK 2 /* * Time to wait before we decide that a SQ is stuck. * * Since both pkt rx and tx notifications are done with same CQ, * when packets are being received at very high rate (eg: L2 forwarding) * then freeing transmitted skbs will be delayed and watchdog * will kick in, resetting interface. Hence keeping this value high. */ #define NICVF_TX_TIMEOUT (50 * HZ) #define NIC_RSSI_COUNT 4096 /* Total no of RSS indices */ #define NIC_MAX_RSS_HASH_BITS 8 #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS) #define RSS_HASH_KEY_SIZE 5 /* 320 bit key */ +struct nicvf_rss_info { + boolean_t enable; +#define RSS_L2_EXTENDED_HASH_ENA (1UL << 0) +#define RSS_IP_HASH_ENA (1UL << 1) +#define RSS_TCP_HASH_ENA (1UL << 2) +#define RSS_TCP_SYN_DIS (1UL << 3) +#define RSS_UDP_HASH_ENA (1UL << 4) +#define RSS_L4_EXTENDED_HASH_ENA (1UL << 5) +#define RSS_ROCE_ENA (1UL << 6) +#define RSS_L3_BI_DIRECTION_ENA (1UL << 7) +#define RSS_L4_BI_DIRECTION_ENA (1UL << 8) + uint64_t cfg; + uint8_t hash_bits; + uint16_t rss_size; + uint8_t ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; + uint64_t key[RSS_HASH_KEY_SIZE]; +}; + enum rx_stats_reg_offset { RX_OCTS = 0x0, RX_UCAST = 0x1, RX_BCAST = 0x2, RX_MCAST = 0x3, RX_RED = 0x4, RX_RED_OCTS = 0x5, RX_ORUN = 0x6, RX_ORUN_OCTS = 0x7, RX_FCS = 0x8, RX_L2ERR = 0x9, RX_DRP_BCAST = 0xa, RX_DRP_MCAST = 0xb, RX_DRP_L3BCAST = 0xc, RX_DRP_L3MCAST = 0xd, RX_STATS_ENUM_LAST, }; enum tx_stats_reg_offset { TX_OCTS = 0x0, TX_UCAST = 0x1, TX_BCAST = 0x2, TX_MCAST = 0x3, TX_DROP = 0x4, TX_STATS_ENUM_LAST, }; struct nicvf_hw_stats { uint64_t rx_bytes; uint64_t rx_ucast_frames; uint64_t rx_bcast_frames; uint64_t rx_mcast_frames; uint64_t rx_fcs_errors; uint64_t rx_l2_errors; uint64_t rx_drop_red; uint64_t rx_drop_red_bytes; uint64_t rx_drop_overrun; uint64_t rx_drop_overrun_bytes; uint64_t rx_drop_bcast; uint64_t rx_drop_mcast; uint64_t rx_drop_l3_bcast; uint64_t rx_drop_l3_mcast; uint64_t rx_bgx_truncated_pkts; uint64_t rx_jabber_errs; uint64_t rx_fcs_errs; uint64_t rx_bgx_errs; uint64_t rx_prel2_errs; uint64_t rx_l2_hdr_malformed; uint64_t rx_oversize; uint64_t rx_undersize; uint64_t rx_l2_len_mismatch; uint64_t rx_l2_pclp; uint64_t rx_ip_ver_errs; uint64_t rx_ip_csum_errs; uint64_t rx_ip_hdr_malformed; uint64_t rx_ip_payload_malformed; uint64_t rx_ip_ttl_errs; uint64_t rx_l3_pclp; uint64_t rx_l4_malformed; uint64_t rx_l4_csum_errs; uint64_t rx_udp_len_errs; uint64_t rx_l4_port_errs; uint64_t rx_tcp_flag_errs; uint64_t rx_tcp_offset_errs; uint64_t rx_l4_pclp; uint64_t rx_truncated_pkts; uint64_t tx_bytes_ok; uint64_t tx_ucast_frames_ok; uint64_t tx_bcast_frames_ok; uint64_t tx_mcast_frames_ok; uint64_t tx_drops; }; struct nicvf_drv_stats { /* Rx */ uint64_t rx_frames_ok; uint64_t rx_frames_64; uint64_t rx_frames_127; uint64_t rx_frames_255; uint64_t rx_frames_511; uint64_t rx_frames_1023; uint64_t rx_frames_1518; uint64_t rx_frames_jumbo; uint64_t rx_drops; /* Tx */ uint64_t tx_frames_ok; uint64_t tx_drops; uint64_t tx_tso; uint64_t txq_stop; uint64_t txq_wake; }; struct nicvf { struct nicvf *pnicvf; device_t dev; struct ifnet * ifp; struct sx core_sx; struct ifmedia if_media; uint32_t if_flags; uint8_t hwaddr[ETHER_ADDR_LEN]; uint8_t vf_id; uint8_t node; boolean_t tns_mode:1; boolean_t sqs_mode:1; bool loopback_supported:1; + struct nicvf_rss_info rss_info; uint16_t mtu; struct queue_set *qs; uint8_t rx_queues; uint8_t tx_queues; uint8_t max_queues; struct resource *reg_base; boolean_t link_up; boolean_t hw_tso; uint8_t duplex; uint32_t speed; uint8_t cpi_alg; /* Interrupt coalescing settings */ uint32_t cq_coalesce_usecs; uint32_t msg_enable; struct nicvf_hw_stats hw_stats; struct nicvf_drv_stats drv_stats; struct bgx_stats bgx_stats; /* Interface statistics */ struct callout stats_callout; struct mtx stats_mtx; /* MSI-X */ boolean_t msix_enabled; uint8_t num_vec; struct msix_entry msix_entries[NIC_VF_MSIX_VECTORS]; struct resource * msix_table_res; char irq_name[NIC_VF_MSIX_VECTORS][20]; boolean_t irq_allocated[NIC_VF_MSIX_VECTORS]; /* VF <-> PF mailbox communication */ boolean_t pf_acked; boolean_t pf_nacked; } __aligned(CACHE_LINE_SIZE); /* * PF <--> VF Mailbox communication * Eight 64bit registers are shared between PF and VF. * Separate set for each VF. * Writing '1' into last register mbx7 means end of message. */ /* PF <--> VF mailbox communication */ #define NIC_PF_VF_MAILBOX_SIZE 2 #define NIC_MBOX_MSG_TIMEOUT 2000 /* ms */ /* Mailbox message types */ #define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */ #define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */ #define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */ #define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */ #define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */ #define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */ #define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */ #define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */ #define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */ #define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */ #define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */ #define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */ #define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */ #define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */ #define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */ #define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */ #define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */ #define NIC_MBOX_MSG_ALLOC_SQS 0x12 /* Allocate secondary Qset */ #define NIC_MBOX_MSG_NICVF_PTR 0x13 /* Send nicvf ptr to PF */ #define NIC_MBOX_MSG_PNICVF_PTR 0x14 /* Get primary qset nicvf ptr */ #define NIC_MBOX_MSG_SNICVF_PTR 0x15 /* Send sqet nicvf ptr to PVF */ #define NIC_MBOX_MSG_LOOPBACK 0x16 /* Set interface in loopback */ #define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */ #define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */ struct nic_cfg_msg { uint8_t msg; uint8_t vf_id; uint8_t node_id; boolean_t tns_mode:1; boolean_t sqs_mode:1; boolean_t loopback_supported:1; uint8_t mac_addr[ETHER_ADDR_LEN]; }; /* Qset configuration */ struct qs_cfg_msg { uint8_t msg; uint8_t num; uint8_t sqs_count; uint64_t cfg; }; /* Receive queue configuration */ struct rq_cfg_msg { uint8_t msg; uint8_t qs_num; uint8_t rq_num; uint64_t cfg; }; /* Send queue configuration */ struct sq_cfg_msg { uint8_t msg; uint8_t qs_num; uint8_t sq_num; boolean_t sqs_mode; uint64_t cfg; }; /* Set VF's MAC address */ struct set_mac_msg { uint8_t msg; uint8_t vf_id; uint8_t mac_addr[ETHER_ADDR_LEN]; }; /* Set Maximum frame size */ struct set_frs_msg { uint8_t msg; uint8_t vf_id; uint16_t max_frs; }; /* Set CPI algorithm type */ struct cpi_cfg_msg { uint8_t msg; uint8_t vf_id; uint8_t rq_cnt; uint8_t cpi_alg; }; /* Get RSS table size */ struct rss_sz_msg { uint8_t msg; uint8_t vf_id; uint16_t ind_tbl_size; }; /* Set RSS configuration */ struct rss_cfg_msg { uint8_t msg; uint8_t vf_id; uint8_t hash_bits; uint8_t tbl_len; uint8_t tbl_offset; #define RSS_IND_TBL_LEN_PER_MBX_MSG 8 uint8_t ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG]; }; struct bgx_stats_msg { uint8_t msg; uint8_t vf_id; uint8_t rx; uint8_t idx; uint64_t stats; }; /* Physical interface link status */ struct bgx_link_status { uint8_t msg; uint8_t link_up; uint8_t duplex; uint32_t speed; }; /* Set interface in loopback mode */ struct set_loopback { uint8_t msg; uint8_t vf_id; boolean_t enable; }; /* 128 bit shared memory between PF and each VF */ union nic_mbx { struct { uint8_t msg; } msg; struct nic_cfg_msg nic_cfg; struct qs_cfg_msg qs; struct rq_cfg_msg rq; struct sq_cfg_msg sq; struct set_mac_msg mac; struct set_frs_msg frs; struct cpi_cfg_msg cpi_cfg; struct rss_sz_msg rss_size; struct rss_cfg_msg rss_cfg; struct bgx_stats_msg bgx_stats; struct bgx_link_status link_status; struct set_loopback lbk; }; #define NIC_NODE_ID_MASK 0x03 #define NIC_NODE_ID_SHIFT 44 static __inline int nic_get_node_id(struct resource *res) { pci_addr_t addr; addr = rman_get_start(res); return ((addr >> NIC_NODE_ID_SHIFT) & NIC_NODE_ID_MASK); } static __inline boolean_t pass1_silicon(device_t dev) { /* Check if the chip revision is < Pass2 */ return (pci_get_revid(dev) < PCI_REVID_PASS2); } int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx); #endif /* NIC_H */ Index: head/sys/dev/vnic/nic_main.c =================================================================== --- head/sys/dev/vnic/nic_main.c (revision 299443) +++ head/sys/dev/vnic/nic_main.c (revision 299444) @@ -1,1161 +1,1221 @@ /* * Copyright (C) 2015 Cavium Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef PCI_IOV #include #include #endif #include "thunder_bgx.h" #include "nic_reg.h" #include "nic.h" #include "q_struct.h" #define VNIC_PF_DEVSTR "Cavium Thunder NIC Physical Function Driver" #define VNIC_PF_REG_RID PCIR_BAR(PCI_CFG_REG_BAR_NUM) #define NIC_SET_VF_LMAC_MAP(bgx, lmac) ((((bgx) & 0xF) << 4) | ((lmac) & 0xF)) #define NIC_GET_BGX_FROM_VF_LMAC_MAP(map) (((map) >> 4) & 0xF) #define NIC_GET_LMAC_FROM_VF_LMAC_MAP(map) ((map) & 0xF) /* Structure to be used by the SR-IOV for VF configuration schemas */ struct nicvf_info { boolean_t vf_enabled; int vf_flags; }; struct nicpf { device_t dev; uint8_t node; u_int flags; uint8_t num_vf_en; /* No of VF enabled */ struct nicvf_info vf_info[MAX_NUM_VFS_SUPPORTED]; struct resource * reg_base; /* Register start address */ struct pkind_cfg pkind; uint8_t vf_lmac_map[MAX_LMAC]; boolean_t mbx_lock[MAX_NUM_VFS_SUPPORTED]; struct callout check_link; struct mtx check_link_mtx; uint8_t link[MAX_LMAC]; uint8_t duplex[MAX_LMAC]; uint32_t speed[MAX_LMAC]; uint16_t cpi_base[MAX_NUM_VFS_SUPPORTED]; + uint16_t rssi_base[MAX_NUM_VFS_SUPPORTED]; uint16_t rss_ind_tbl_size; /* MSI-X */ boolean_t msix_enabled; uint8_t num_vec; struct msix_entry msix_entries[NIC_PF_MSIX_VECTORS]; struct resource * msix_table_res; }; static int nicpf_probe(device_t); static int nicpf_attach(device_t); static int nicpf_detach(device_t); #ifdef PCI_IOV static int nicpf_iov_init(device_t, uint16_t, const nvlist_t *); static void nicpf_iov_uninit(device_t); static int nicpf_iov_add_vf(device_t, uint16_t, const nvlist_t *); #endif static device_method_t nicpf_methods[] = { /* Device interface */ DEVMETHOD(device_probe, nicpf_probe), DEVMETHOD(device_attach, nicpf_attach), DEVMETHOD(device_detach, nicpf_detach), /* PCI SR-IOV interface */ #ifdef PCI_IOV DEVMETHOD(pci_iov_init, nicpf_iov_init), DEVMETHOD(pci_iov_uninit, nicpf_iov_uninit), DEVMETHOD(pci_iov_add_vf, nicpf_iov_add_vf), #endif DEVMETHOD_END, }; static driver_t nicpf_driver = { "vnicpf", nicpf_methods, sizeof(struct nicpf), }; static devclass_t nicpf_devclass; DRIVER_MODULE(nicpf, pci, nicpf_driver, nicpf_devclass, 0, 0); MODULE_DEPEND(nicpf, pci, 1, 1, 1); MODULE_DEPEND(nicpf, ether, 1, 1, 1); MODULE_DEPEND(nicpf, thunder_bgx, 1, 1, 1); static int nicpf_alloc_res(struct nicpf *); static void nicpf_free_res(struct nicpf *); static void nic_set_lmac_vf_mapping(struct nicpf *); static void nic_init_hw(struct nicpf *); static int nic_sriov_init(device_t, struct nicpf *); static void nic_poll_for_link(void *); static int nic_register_interrupts(struct nicpf *); static void nic_unregister_interrupts(struct nicpf *); /* * Device interface */ static int nicpf_probe(device_t dev) { uint16_t vendor_id; uint16_t device_id; vendor_id = pci_get_vendor(dev); device_id = pci_get_device(dev); if (vendor_id == PCI_VENDOR_ID_CAVIUM && device_id == PCI_DEVICE_ID_THUNDER_NIC_PF) { device_set_desc(dev, VNIC_PF_DEVSTR); return (BUS_PROBE_DEFAULT); } return (ENXIO); } static int nicpf_attach(device_t dev) { struct nicpf *nic; int err; nic = device_get_softc(dev); nic->dev = dev; /* Enable bus mastering */ pci_enable_busmaster(dev); /* Allocate PCI resources */ err = nicpf_alloc_res(nic); if (err != 0) { device_printf(dev, "Could not allocate PCI resources\n"); return (err); } nic->node = nic_get_node_id(nic->reg_base); /* Enable Traffic Network Switch (TNS) bypass mode by default */ nic->flags &= ~NIC_TNS_ENABLED; nic_set_lmac_vf_mapping(nic); /* Initialize hardware */ nic_init_hw(nic); /* Set RSS TBL size for each VF */ nic->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE; /* Setup interrupts */ err = nic_register_interrupts(nic); if (err != 0) goto err_free_res; /* Configure SRIOV */ err = nic_sriov_init(dev, nic); if (err != 0) goto err_free_intr; if (nic->flags & NIC_TNS_ENABLED) return (0); mtx_init(&nic->check_link_mtx, "VNIC PF link poll", NULL, MTX_DEF); /* Register physical link status poll callout */ callout_init_mtx(&nic->check_link, &nic->check_link_mtx, 0); mtx_lock(&nic->check_link_mtx); nic_poll_for_link(nic); mtx_unlock(&nic->check_link_mtx); return (0); err_free_intr: nic_unregister_interrupts(nic); err_free_res: nicpf_free_res(nic); pci_disable_busmaster(dev); return (err); } static int nicpf_detach(device_t dev) { struct nicpf *nic; nic = device_get_softc(dev); callout_drain(&nic->check_link); mtx_destroy(&nic->check_link_mtx); nic_unregister_interrupts(nic); nicpf_free_res(nic); pci_disable_busmaster(dev); return (0); } /* * SR-IOV interface */ #ifdef PCI_IOV static int nicpf_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) { struct nicpf *nic; nic = device_get_softc(dev); if (num_vfs == 0) return (ENXIO); nic->flags |= NIC_SRIOV_ENABLED; return (0); } static void nicpf_iov_uninit(device_t dev) { /* ARM64TODO: Implement this function */ } static int nicpf_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) { const void *mac; struct nicpf *nic; size_t size; int bgx, lmac; nic = device_get_softc(dev); if ((nic->flags & NIC_SRIOV_ENABLED) == 0) return (ENXIO); if (vfnum > (nic->num_vf_en - 1)) return (EINVAL); if (nvlist_exists_binary(params, "mac-addr") != 0) { mac = nvlist_get_binary(params, "mac-addr", &size); bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vfnum]); lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vfnum]); bgx_set_lmac_mac(nic->node, bgx, lmac, mac); } return (0); } #endif /* * Helper routines */ static int nicpf_alloc_res(struct nicpf *nic) { device_t dev; int rid; dev = nic->dev; rid = VNIC_PF_REG_RID; nic->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (nic->reg_base == NULL) { /* For verbose output print some more details */ if (bootverbose) { device_printf(dev, "Could not allocate registers memory\n"); } return (ENXIO); } return (0); } static void nicpf_free_res(struct nicpf *nic) { device_t dev; dev = nic->dev; if (nic->reg_base != NULL) { bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(nic->reg_base), nic->reg_base); } } /* Register read/write APIs */ static __inline void nic_reg_write(struct nicpf *nic, bus_space_handle_t offset, uint64_t val) { bus_write_8(nic->reg_base, offset, val); } static __inline uint64_t nic_reg_read(struct nicpf *nic, uint64_t offset) { uint64_t val; val = bus_read_8(nic->reg_base, offset); return (val); } /* PF -> VF mailbox communication APIs */ static void nic_enable_mbx_intr(struct nicpf *nic) { /* Enable mailbox interrupt for all 128 VFs */ nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, ~0UL); nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S + sizeof(uint64_t), ~0UL); } static void nic_clear_mbx_intr(struct nicpf *nic, int vf, int mbx_reg) { nic_reg_write(nic, NIC_PF_MAILBOX_INT + (mbx_reg << 3), (1UL << vf)); } static uint64_t nic_get_mbx_addr(int vf) { return (NIC_PF_VF_0_127_MAILBOX_0_1 + (vf << NIC_VF_NUM_SHIFT)); } /* * Send a mailbox message to VF * @vf: vf to which this message to be sent * @mbx: Message to be sent */ static void nic_send_msg_to_vf(struct nicpf *nic, int vf, union nic_mbx *mbx) { bus_space_handle_t mbx_addr = nic_get_mbx_addr(vf); uint64_t *msg = (uint64_t *)mbx; /* * In first revision HW, mbox interrupt is triggerred * when PF writes to MBOX(1), in next revisions when * PF writes to MBOX(0) */ if (pass1_silicon(nic->dev)) { nic_reg_write(nic, mbx_addr + 0, msg[0]); nic_reg_write(nic, mbx_addr + 8, msg[1]); } else { nic_reg_write(nic, mbx_addr + 8, msg[1]); nic_reg_write(nic, mbx_addr + 0, msg[0]); } } /* * Responds to VF's READY message with VF's * ID, node, MAC address e.t.c * @vf: VF which sent READY message */ static void nic_mbx_send_ready(struct nicpf *nic, int vf) { union nic_mbx mbx = {}; int bgx_idx, lmac; const char *mac; mbx.nic_cfg.msg = NIC_MBOX_MSG_READY; mbx.nic_cfg.vf_id = vf; if (nic->flags & NIC_TNS_ENABLED) mbx.nic_cfg.tns_mode = NIC_TNS_MODE; else mbx.nic_cfg.tns_mode = NIC_TNS_BYPASS_MODE; if (vf < MAX_LMAC) { bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); mac = bgx_get_lmac_mac(nic->node, bgx_idx, lmac); if (mac) { memcpy((uint8_t *)&mbx.nic_cfg.mac_addr, mac, ETHER_ADDR_LEN); } } mbx.nic_cfg.node_id = nic->node; mbx.nic_cfg.loopback_supported = vf < MAX_LMAC; nic_send_msg_to_vf(nic, vf, &mbx); } /* * ACKs VF's mailbox message * @vf: VF to which ACK to be sent */ static void nic_mbx_send_ack(struct nicpf *nic, int vf) { union nic_mbx mbx = {}; mbx.msg.msg = NIC_MBOX_MSG_ACK; nic_send_msg_to_vf(nic, vf, &mbx); } /* * NACKs VF's mailbox message that PF is not able to * complete the action * @vf: VF to which ACK to be sent */ static void nic_mbx_send_nack(struct nicpf *nic, int vf) { union nic_mbx mbx = {}; mbx.msg.msg = NIC_MBOX_MSG_NACK; nic_send_msg_to_vf(nic, vf, &mbx); } /* * Flush all in flight receive packets to memory and * bring down an active RQ */ static int nic_rcv_queue_sw_sync(struct nicpf *nic) { uint16_t timeout = ~0x00; nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x01); /* Wait till sync cycle is finished */ while (timeout) { if (nic_reg_read(nic, NIC_PF_SW_SYNC_RX_DONE) & 0x1) break; timeout--; } nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x00); if (!timeout) { device_printf(nic->dev, "Receive queue software sync failed\n"); return (ETIMEDOUT); } return (0); } /* Get BGX Rx/Tx stats and respond to VF's request */ static void nic_get_bgx_stats(struct nicpf *nic, struct bgx_stats_msg *bgx) { int bgx_idx, lmac; union nic_mbx mbx = {}; bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]); lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]); mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS; mbx.bgx_stats.vf_id = bgx->vf_id; mbx.bgx_stats.rx = bgx->rx; mbx.bgx_stats.idx = bgx->idx; if (bgx->rx != 0) { mbx.bgx_stats.stats = bgx_get_rx_stats(nic->node, bgx_idx, lmac, bgx->idx); } else { mbx.bgx_stats.stats = bgx_get_tx_stats(nic->node, bgx_idx, lmac, bgx->idx); } nic_send_msg_to_vf(nic, bgx->vf_id, &mbx); } /* Update hardware min/max frame size */ static int nic_update_hw_frs(struct nicpf *nic, int new_frs, int vf) { if ((new_frs > NIC_HW_MAX_FRS) || (new_frs < NIC_HW_MIN_FRS)) { device_printf(nic->dev, "Invalid MTU setting from VF%d rejected, " "should be between %d and %d\n", vf, NIC_HW_MIN_FRS, NIC_HW_MAX_FRS); return (EINVAL); } new_frs += ETHER_HDR_LEN; if (new_frs <= nic->pkind.maxlen) return (0); nic->pkind.maxlen = new_frs; nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG, *(uint64_t *)&nic->pkind); return (0); } /* Set minimum transmit packet size */ static void nic_set_tx_pkt_pad(struct nicpf *nic, int size) { int lmac; uint64_t lmac_cfg; /* Max value that can be set is 60 */ if (size > 60) size = 60; for (lmac = 0; lmac < (MAX_BGX_PER_CN88XX * MAX_LMAC_PER_BGX); lmac++) { lmac_cfg = nic_reg_read(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3)); lmac_cfg &= ~(0xF << 2); lmac_cfg |= ((size / 4) << 2); nic_reg_write(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3), lmac_cfg); } } /* * Function to check number of LMACs present and set VF::LMAC mapping. * Mapping will be used while initializing channels. */ static void nic_set_lmac_vf_mapping(struct nicpf *nic) { unsigned bgx_map = bgx_get_map(nic->node); int bgx, next_bgx_lmac = 0; int lmac, lmac_cnt = 0; uint64_t lmac_credit; nic->num_vf_en = 0; if (nic->flags & NIC_TNS_ENABLED) { nic->num_vf_en = DEFAULT_NUM_VF_ENABLED; return; } for (bgx = 0; bgx < NIC_MAX_BGX; bgx++) { if ((bgx_map & (1 << bgx)) == 0) continue; lmac_cnt = bgx_get_lmac_count(nic->node, bgx); for (lmac = 0; lmac < lmac_cnt; lmac++) nic->vf_lmac_map[next_bgx_lmac++] = NIC_SET_VF_LMAC_MAP(bgx, lmac); nic->num_vf_en += lmac_cnt; /* Program LMAC credits */ lmac_credit = (1UL << 1); /* channel credit enable */ lmac_credit |= (0x1ff << 2); /* Max outstanding pkt count */ /* 48KB BGX Tx buffer size, each unit is of size 16bytes */ lmac_credit |= (((((48 * 1024) / lmac_cnt) - NIC_HW_MAX_FRS) / 16) << 12); lmac = bgx * MAX_LMAC_PER_BGX; for (; lmac < lmac_cnt + (bgx * MAX_LMAC_PER_BGX); lmac++) { nic_reg_write(nic, NIC_PF_LMAC_0_7_CREDIT + (lmac * 8), lmac_credit); } } } #define TNS_PORT0_BLOCK 6 #define TNS_PORT1_BLOCK 7 #define BGX0_BLOCK 8 #define BGX1_BLOCK 9 static void nic_init_hw(struct nicpf *nic) { int i; /* Enable NIC HW block */ nic_reg_write(nic, NIC_PF_CFG, 0x3); /* Enable backpressure */ nic_reg_write(nic, NIC_PF_BP_CFG, (1UL << 6) | 0x03); if (nic->flags & NIC_TNS_ENABLED) { nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG, (NIC_TNS_MODE << 7) | TNS_PORT0_BLOCK); nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8), (NIC_TNS_MODE << 7) | TNS_PORT1_BLOCK); nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG, (1UL << 63) | TNS_PORT0_BLOCK); nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8), (1UL << 63) | TNS_PORT1_BLOCK); } else { /* Disable TNS mode on both interfaces */ nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG, (NIC_TNS_BYPASS_MODE << 7) | BGX0_BLOCK); nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8), (NIC_TNS_BYPASS_MODE << 7) | BGX1_BLOCK); nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG, (1UL << 63) | BGX0_BLOCK); nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8), (1UL << 63) | BGX1_BLOCK); } /* PKIND configuration */ nic->pkind.minlen = 0; nic->pkind.maxlen = NIC_HW_MAX_FRS + ETHER_HDR_LEN; nic->pkind.lenerr_en = 1; nic->pkind.rx_hdr = 0; nic->pkind.hdr_sl = 0; for (i = 0; i < NIC_MAX_PKIND; i++) { nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (i << 3), *(uint64_t *)&nic->pkind); } nic_set_tx_pkt_pad(nic, NIC_HW_MIN_FRS); /* Timer config */ nic_reg_write(nic, NIC_PF_INTR_TIMER_CFG, NICPF_CLK_PER_INT_TICK); /* Enable VLAN ethertype matching and stripping */ nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7, (2 << 19) | (ETYPE_ALG_VLAN_STRIP << 16) | ETHERTYPE_VLAN); } /* Channel parse index configuration */ static void nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg) { uint32_t vnic, bgx, lmac, chan; uint32_t padd, cpi_count = 0; uint64_t cpi_base, cpi, rssi_base, rssi; uint8_t qset, rq_idx = 0; vnic = cfg->vf_id; bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]); lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]); chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF); cpi_base = (lmac * NIC_MAX_CPI_PER_LMAC) + (bgx * NIC_CPI_PER_BGX); rssi_base = (lmac * nic->rss_ind_tbl_size) + (bgx * NIC_RSSI_PER_BGX); /* Rx channel configuration */ nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_BP_CFG | (chan << 3), (1UL << 63) | (vnic << 0)); nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_CFG | (chan << 3), ((uint64_t)cfg->cpi_alg << 62) | (cpi_base << 48)); if (cfg->cpi_alg == CPI_ALG_NONE) cpi_count = 1; else if (cfg->cpi_alg == CPI_ALG_VLAN) /* 3 bits of PCP */ cpi_count = 8; else if (cfg->cpi_alg == CPI_ALG_VLAN16) /* 3 bits PCP + DEI */ cpi_count = 16; else if (cfg->cpi_alg == CPI_ALG_DIFF) /* 6bits DSCP */ cpi_count = NIC_MAX_CPI_PER_LMAC; /* RSS Qset, Qidx mapping */ qset = cfg->vf_id; rssi = rssi_base; for (; rssi < (rssi_base + cfg->rq_cnt); rssi++) { nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3), (qset << 3) | rq_idx); rq_idx++; } rssi = 0; cpi = cpi_base; for (; cpi < (cpi_base + cpi_count); cpi++) { /* Determine port to channel adder */ if (cfg->cpi_alg != CPI_ALG_DIFF) padd = cpi % cpi_count; else padd = cpi % 8; /* 3 bits CS out of 6bits DSCP */ /* Leave RSS_SIZE as '0' to disable RSS */ if (pass1_silicon(nic->dev)) { nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3), (vnic << 24) | (padd << 16) | (rssi_base + rssi)); } else { /* Set MPI_ALG to '0' to disable MCAM parsing */ nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3), (padd << 16)); /* MPI index is same as CPI if MPI_ALG is not enabled */ nic_reg_write(nic, NIC_PF_MPI_0_2047_CFG | (cpi << 3), (vnic << 24) | (rssi_base + rssi)); } if ((rssi + 1) >= cfg->rq_cnt) continue; if (cfg->cpi_alg == CPI_ALG_VLAN) rssi++; else if (cfg->cpi_alg == CPI_ALG_VLAN16) rssi = ((cpi - cpi_base) & 0xe) >> 1; else if (cfg->cpi_alg == CPI_ALG_DIFF) rssi = ((cpi - cpi_base) & 0x38) >> 3; } nic->cpi_base[cfg->vf_id] = cpi_base; + nic->rssi_base[cfg->vf_id] = rssi_base; } +/* Responsds to VF with its RSS indirection table size */ +static void +nic_send_rss_size(struct nicpf *nic, int vf) +{ + union nic_mbx mbx = {}; + uint64_t *msg; + + msg = (uint64_t *)&mbx; + + mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE; + mbx.rss_size.ind_tbl_size = nic->rss_ind_tbl_size; + nic_send_msg_to_vf(nic, vf, &mbx); +} + /* + * Receive side scaling configuration + * configure: + * - RSS index + * - indir table i.e hash::RQ mapping + * - no of hash bits to consider + */ +static void +nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg) +{ + uint8_t qset, idx; + uint64_t cpi_cfg, cpi_base, rssi_base, rssi; + uint64_t idx_addr; + + idx = 0; + rssi_base = nic->rssi_base[cfg->vf_id] + cfg->tbl_offset; + + rssi = rssi_base; + qset = cfg->vf_id; + + for (; rssi < (rssi_base + cfg->tbl_len); rssi++) { + nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3), + (qset << 3) | (cfg->ind_tbl[idx] & 0x7)); + idx++; + } + + cpi_base = nic->cpi_base[cfg->vf_id]; + if (pass1_silicon(nic->dev)) + idx_addr = NIC_PF_CPI_0_2047_CFG; + else + idx_addr = NIC_PF_MPI_0_2047_CFG; + cpi_cfg = nic_reg_read(nic, idx_addr | (cpi_base << 3)); + cpi_cfg &= ~(0xFUL << 20); + cpi_cfg |= (cfg->hash_bits << 20); + nic_reg_write(nic, idx_addr | (cpi_base << 3), cpi_cfg); +} + +/* * 4 level transmit side scheduler configutation * for TNS bypass mode * * Sample configuration for SQ0 * VNIC0-SQ0 -> TL4(0) -> TL3[0] -> TL2[0] -> TL1[0] -> BGX0 * VNIC1-SQ0 -> TL4(8) -> TL3[2] -> TL2[0] -> TL1[0] -> BGX0 * VNIC2-SQ0 -> TL4(16) -> TL3[4] -> TL2[1] -> TL1[0] -> BGX0 * VNIC3-SQ0 -> TL4(24) -> TL3[6] -> TL2[1] -> TL1[0] -> BGX0 * VNIC4-SQ0 -> TL4(512) -> TL3[128] -> TL2[32] -> TL1[1] -> BGX1 * VNIC5-SQ0 -> TL4(520) -> TL3[130] -> TL2[32] -> TL1[1] -> BGX1 * VNIC6-SQ0 -> TL4(528) -> TL3[132] -> TL2[33] -> TL1[1] -> BGX1 * VNIC7-SQ0 -> TL4(536) -> TL3[134] -> TL2[33] -> TL1[1] -> BGX1 */ static void nic_tx_channel_cfg(struct nicpf *nic, uint8_t vnic, struct sq_cfg_msg *sq) { uint32_t bgx, lmac, chan; uint32_t tl2, tl3, tl4; uint32_t rr_quantum; uint8_t sq_idx = sq->sq_num; uint8_t pqs_vnic; pqs_vnic = vnic; bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]); lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]); /* 24 bytes for FCS, IPG and preamble */ rr_quantum = ((NIC_HW_MAX_FRS + 24) / 4); tl4 = (lmac * NIC_TL4_PER_LMAC) + (bgx * NIC_TL4_PER_BGX); tl4 += sq_idx; tl3 = tl4 / (NIC_MAX_TL4 / NIC_MAX_TL3); nic_reg_write(nic, NIC_PF_QSET_0_127_SQ_0_7_CFG2 | ((uint64_t)vnic << NIC_QS_ID_SHIFT) | ((uint32_t)sq_idx << NIC_Q_NUM_SHIFT), tl4); nic_reg_write(nic, NIC_PF_TL4_0_1023_CFG | (tl4 << 3), ((uint64_t)vnic << 27) | ((uint32_t)sq_idx << 24) | rr_quantum); nic_reg_write(nic, NIC_PF_TL3_0_255_CFG | (tl3 << 3), rr_quantum); chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF); nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), chan); /* Enable backpressure on the channel */ nic_reg_write(nic, NIC_PF_CHAN_0_255_TX_CFG | (chan << 3), 1); tl2 = tl3 >> 2; nic_reg_write(nic, NIC_PF_TL3A_0_63_CFG | (tl2 << 3), tl2); nic_reg_write(nic, NIC_PF_TL2_0_63_CFG | (tl2 << 3), rr_quantum); /* No priorities as of now */ nic_reg_write(nic, NIC_PF_TL2_0_63_PRI | (tl2 << 3), 0x00); } static int nic_config_loopback(struct nicpf *nic, struct set_loopback *lbk) { int bgx_idx, lmac_idx; if (lbk->vf_id > MAX_LMAC) return (ENXIO); bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]); lmac_idx = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]); bgx_lmac_internal_loopback(nic->node, bgx_idx, lmac_idx, lbk->enable); return (0); } /* Interrupt handler to handle mailbox messages from VFs */ static void nic_handle_mbx_intr(struct nicpf *nic, int vf) { union nic_mbx mbx = {}; uint64_t *mbx_data; uint64_t mbx_addr; uint64_t reg_addr; uint64_t cfg; int bgx, lmac; int i; int ret = 0; nic->mbx_lock[vf] = TRUE; mbx_addr = nic_get_mbx_addr(vf); mbx_data = (uint64_t *)&mbx; for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) { *mbx_data = nic_reg_read(nic, mbx_addr); mbx_data++; mbx_addr += sizeof(uint64_t); } switch (mbx.msg.msg) { case NIC_MBOX_MSG_READY: nic_mbx_send_ready(nic, vf); if (vf < MAX_LMAC) { nic->link[vf] = 0; nic->duplex[vf] = 0; nic->speed[vf] = 0; } ret = 1; break; case NIC_MBOX_MSG_QS_CFG: reg_addr = NIC_PF_QSET_0_127_CFG | (mbx.qs.num << NIC_QS_ID_SHIFT); cfg = mbx.qs.cfg; nic_reg_write(nic, reg_addr, cfg); break; case NIC_MBOX_MSG_RQ_CFG: reg_addr = NIC_PF_QSET_0_127_RQ_0_7_CFG | (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); nic_reg_write(nic, reg_addr, mbx.rq.cfg); break; case NIC_MBOX_MSG_RQ_BP_CFG: reg_addr = NIC_PF_QSET_0_127_RQ_0_7_BP_CFG | (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); nic_reg_write(nic, reg_addr, mbx.rq.cfg); break; case NIC_MBOX_MSG_RQ_SW_SYNC: ret = nic_rcv_queue_sw_sync(nic); break; case NIC_MBOX_MSG_RQ_DROP_CFG: reg_addr = NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG | (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); nic_reg_write(nic, reg_addr, mbx.rq.cfg); break; case NIC_MBOX_MSG_SQ_CFG: reg_addr = NIC_PF_QSET_0_127_SQ_0_7_CFG | (mbx.sq.qs_num << NIC_QS_ID_SHIFT) | (mbx.sq.sq_num << NIC_Q_NUM_SHIFT); nic_reg_write(nic, reg_addr, mbx.sq.cfg); nic_tx_channel_cfg(nic, mbx.qs.num, &mbx.sq); break; case NIC_MBOX_MSG_SET_MAC: lmac = mbx.mac.vf_id; bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]); lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]); bgx_set_lmac_mac(nic->node, bgx, lmac, mbx.mac.mac_addr); break; case NIC_MBOX_MSG_SET_MAX_FRS: ret = nic_update_hw_frs(nic, mbx.frs.max_frs, mbx.frs.vf_id); break; case NIC_MBOX_MSG_CPI_CFG: nic_config_cpi(nic, &mbx.cpi_cfg); + break; + case NIC_MBOX_MSG_RSS_SIZE: + nic_send_rss_size(nic, vf); + goto unlock; + case NIC_MBOX_MSG_RSS_CFG: + case NIC_MBOX_MSG_RSS_CFG_CONT: /* fall through */ + nic_config_rss(nic, &mbx.rss_cfg); break; case NIC_MBOX_MSG_CFG_DONE: /* Last message of VF config msg sequence */ nic->vf_info[vf].vf_enabled = TRUE; goto unlock; case NIC_MBOX_MSG_SHUTDOWN: /* First msg in VF teardown sequence */ nic->vf_info[vf].vf_enabled = FALSE; break; case NIC_MBOX_MSG_BGX_STATS: nic_get_bgx_stats(nic, &mbx.bgx_stats); goto unlock; case NIC_MBOX_MSG_LOOPBACK: ret = nic_config_loopback(nic, &mbx.lbk); break; default: device_printf(nic->dev, "Invalid msg from VF%d, msg 0x%x\n", vf, mbx.msg.msg); break; } if (ret == 0) nic_mbx_send_ack(nic, vf); else if (mbx.msg.msg != NIC_MBOX_MSG_READY) nic_mbx_send_nack(nic, vf); unlock: nic->mbx_lock[vf] = FALSE; } static void nic_mbx_intr_handler(struct nicpf *nic, int mbx) { uint64_t intr; uint8_t vf, vf_per_mbx_reg = 64; intr = nic_reg_read(nic, NIC_PF_MAILBOX_INT + (mbx << 3)); for (vf = 0; vf < vf_per_mbx_reg; vf++) { if (intr & (1UL << vf)) { nic_handle_mbx_intr(nic, vf + (mbx * vf_per_mbx_reg)); nic_clear_mbx_intr(nic, vf, mbx); } } } static void nic_mbx0_intr_handler (void *arg) { struct nicpf *nic = (struct nicpf *)arg; nic_mbx_intr_handler(nic, 0); } static void nic_mbx1_intr_handler (void *arg) { struct nicpf *nic = (struct nicpf *)arg; nic_mbx_intr_handler(nic, 1); } static int nic_enable_msix(struct nicpf *nic) { struct pci_devinfo *dinfo; int rid, count; int ret; dinfo = device_get_ivars(nic->dev); rid = dinfo->cfg.msix.msix_table_bar; nic->msix_table_res = bus_alloc_resource_any(nic->dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (nic->msix_table_res == NULL) { device_printf(nic->dev, "Could not allocate memory for MSI-X table\n"); return (ENXIO); } count = nic->num_vec = NIC_PF_MSIX_VECTORS; ret = pci_alloc_msix(nic->dev, &count); if ((ret != 0) || (count != nic->num_vec)) { device_printf(nic->dev, "Request for #%d msix vectors failed, error: %d\n", nic->num_vec, ret); return (ret); } nic->msix_enabled = 1; return (0); } static void nic_disable_msix(struct nicpf *nic) { if (nic->msix_enabled) { pci_release_msi(nic->dev); nic->msix_enabled = 0; nic->num_vec = 0; } } static void nic_free_all_interrupts(struct nicpf *nic) { int irq; for (irq = 0; irq < nic->num_vec; irq++) { if (nic->msix_entries[irq].irq_res == NULL) continue; if (nic->msix_entries[irq].handle != NULL) { bus_teardown_intr(nic->dev, nic->msix_entries[irq].irq_res, nic->msix_entries[irq].handle); } bus_release_resource(nic->dev, SYS_RES_IRQ, irq, nic->msix_entries[irq].irq_res); } } static int nic_register_interrupts(struct nicpf *nic) { int irq, rid; int ret; /* Enable MSI-X */ ret = nic_enable_msix(nic); if (ret != 0) return (ret); /* Register mailbox interrupt handlers */ irq = NIC_PF_INTR_ID_MBOX0; rid = irq + 1; nic->msix_entries[irq].irq_res = bus_alloc_resource_any(nic->dev, SYS_RES_IRQ, &rid, (RF_SHAREABLE | RF_ACTIVE)); if (nic->msix_entries[irq].irq_res == NULL) { ret = ENXIO; goto fail; } ret = bus_setup_intr(nic->dev, nic->msix_entries[irq].irq_res, (INTR_MPSAFE | INTR_TYPE_MISC), NULL, nic_mbx0_intr_handler, nic, &nic->msix_entries[irq].handle); if (ret != 0) goto fail; irq = NIC_PF_INTR_ID_MBOX1; rid = irq + 1; nic->msix_entries[irq].irq_res = bus_alloc_resource_any(nic->dev, SYS_RES_IRQ, &rid, (RF_SHAREABLE | RF_ACTIVE)); if (nic->msix_entries[irq].irq_res == NULL) { ret = ENXIO; goto fail; } ret = bus_setup_intr(nic->dev, nic->msix_entries[irq].irq_res, (INTR_MPSAFE | INTR_TYPE_MISC), NULL, nic_mbx1_intr_handler, nic, &nic->msix_entries[irq].handle); if (ret != 0) goto fail; /* Enable mailbox interrupt */ nic_enable_mbx_intr(nic); return (0); fail: nic_free_all_interrupts(nic); return (ret); } static void nic_unregister_interrupts(struct nicpf *nic) { nic_free_all_interrupts(nic); nic_disable_msix(nic); } static int nic_sriov_init(device_t dev, struct nicpf *nic) { #ifdef PCI_IOV nvlist_t *pf_schema, *vf_schema; int iov_pos; int err; uint16_t total_vf_cnt; err = pci_find_extcap(dev, PCIZ_SRIOV, &iov_pos); if (err != 0) { device_printf(dev, "SR-IOV capability is not found in PCIe config space\n"); return (err); } /* Fix-up the number of enabled VFs */ total_vf_cnt = pci_read_config(dev, iov_pos + PCIR_SRIOV_TOTAL_VFS, 2); if (total_vf_cnt == 0) return (ENXIO); /* Attach SR-IOV */ pf_schema = pci_iov_schema_alloc_node(); vf_schema = pci_iov_schema_alloc_node(); pci_iov_schema_add_unicast_mac(vf_schema, "mac-addr", 0, NULL); /* * All VFs can change their MACs. * This flag will be ignored but we set it just for the record. */ pci_iov_schema_add_bool(vf_schema, "allow-set-mac", IOV_SCHEMA_HASDEFAULT, TRUE); err = pci_iov_attach(dev, pf_schema, vf_schema); if (err != 0) { device_printf(dev, "Failed to initialize SR-IOV (error=%d)\n", err); return (err); } #endif return (0); } /* * Poll for BGX LMAC link status and update corresponding VF * if there is a change, valid only if internal L2 switch * is not present otherwise VF link is always treated as up */ static void nic_poll_for_link(void *arg) { union nic_mbx mbx = {}; struct nicpf *nic; struct bgx_link_status link; uint8_t vf, bgx, lmac; nic = (struct nicpf *)arg; mbx.link_status.msg = NIC_MBOX_MSG_BGX_LINK_CHANGE; for (vf = 0; vf < nic->num_vf_en; vf++) { /* Poll only if VF is UP */ if (!nic->vf_info[vf].vf_enabled) continue; /* Get BGX, LMAC indices for the VF */ bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); /* Get interface link status */ bgx_get_lmac_link_state(nic->node, bgx, lmac, &link); /* Inform VF only if link status changed */ if (nic->link[vf] == link.link_up) continue; if (!nic->mbx_lock[vf]) { nic->link[vf] = link.link_up; nic->duplex[vf] = link.duplex; nic->speed[vf] = link.speed; /* Send a mbox message to VF with current link status */ mbx.link_status.link_up = link.link_up; mbx.link_status.duplex = link.duplex; mbx.link_status.speed = link.speed; nic_send_msg_to_vf(nic, vf, &mbx); } } callout_reset(&nic->check_link, hz * 2, nic_poll_for_link, nic); } Index: head/sys/dev/vnic/nicvf_main.c =================================================================== --- head/sys/dev/vnic/nicvf_main.c (revision 299443) +++ head/sys/dev/vnic/nicvf_main.c (revision 299444) @@ -1,1506 +1,1608 @@ /* * Copyright (C) 2015 Cavium Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #include __FBSDID("$FreeBSD$"); #include "opt_inet.h" #include "opt_inet6.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "thunder_bgx.h" #include "nic_reg.h" #include "nic.h" #include "nicvf_queues.h" #define VNIC_VF_DEVSTR "Cavium Thunder NIC Virtual Function Driver" #define VNIC_VF_REG_RID PCIR_BAR(PCI_CFG_REG_BAR_NUM) /* Lock for core interface settings */ #define NICVF_CORE_LOCK_INIT(nic) \ sx_init(&(nic)->core_sx, device_get_nameunit((nic)->dev)) #define NICVF_CORE_LOCK_DESTROY(nic) \ sx_destroy(&(nic)->core_sx) #define NICVF_CORE_LOCK(nic) sx_xlock(&(nic)->core_sx) #define NICVF_CORE_UNLOCK(nic) sx_xunlock(&(nic)->core_sx) #define NICVF_CORE_LOCK_ASSERT(nic) sx_assert(&(nic)->core_sx, SA_XLOCKED) #define SPEED_10 10 #define SPEED_100 100 #define SPEED_1000 1000 #define SPEED_10000 10000 #define SPEED_40000 40000 MALLOC_DEFINE(M_NICVF, "nicvf", "ThunderX VNIC VF dynamic memory"); static int nicvf_probe(device_t); static int nicvf_attach(device_t); static int nicvf_detach(device_t); static device_method_t nicvf_methods[] = { /* Device interface */ DEVMETHOD(device_probe, nicvf_probe), DEVMETHOD(device_attach, nicvf_attach), DEVMETHOD(device_detach, nicvf_detach), DEVMETHOD_END, }; static driver_t nicvf_driver = { "vnic", nicvf_methods, sizeof(struct nicvf), }; static devclass_t nicvf_devclass; DRIVER_MODULE(nicvf, pci, nicvf_driver, nicvf_devclass, 0, 0); MODULE_DEPEND(nicvf, pci, 1, 1, 1); MODULE_DEPEND(nicvf, ether, 1, 1, 1); MODULE_DEPEND(nicvf, vnic_pf, 1, 1, 1); static int nicvf_allocate_misc_interrupt(struct nicvf *); static int nicvf_enable_misc_interrupt(struct nicvf *); static int nicvf_allocate_net_interrupts(struct nicvf *); static void nicvf_release_all_interrupts(struct nicvf *); static int nicvf_hw_set_mac_addr(struct nicvf *, uint8_t *); static void nicvf_config_cpi(struct nicvf *); +static int nicvf_rss_init(struct nicvf *); static int nicvf_init_resources(struct nicvf *); static int nicvf_setup_ifnet(struct nicvf *); static int nicvf_setup_ifmedia(struct nicvf *); static void nicvf_hw_addr_random(uint8_t *); static int nicvf_if_ioctl(struct ifnet *, u_long, caddr_t); static void nicvf_if_init(void *); static void nicvf_if_init_locked(struct nicvf *); static int nicvf_if_transmit(struct ifnet *, struct mbuf *); static void nicvf_if_qflush(struct ifnet *); static uint64_t nicvf_if_getcounter(struct ifnet *, ift_counter); static int nicvf_stop_locked(struct nicvf *); static void nicvf_media_status(struct ifnet *, struct ifmediareq *); static int nicvf_media_change(struct ifnet *); static void nicvf_tick_stats(void *); static int nicvf_probe(device_t dev) { uint16_t vendor_id; uint16_t device_id; vendor_id = pci_get_vendor(dev); device_id = pci_get_device(dev); if (vendor_id != PCI_VENDOR_ID_CAVIUM) return (ENXIO); if (device_id == PCI_DEVICE_ID_THUNDER_NIC_VF || device_id == PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF) { device_set_desc(dev, VNIC_VF_DEVSTR); return (BUS_PROBE_DEFAULT); } return (ENXIO); } static int nicvf_attach(device_t dev) { struct nicvf *nic; int rid, qcount; int err = 0; uint8_t hwaddr[ETHER_ADDR_LEN]; uint8_t zeromac[] = {[0 ... (ETHER_ADDR_LEN - 1)] = 0}; nic = device_get_softc(dev); nic->dev = dev; nic->pnicvf = nic; NICVF_CORE_LOCK_INIT(nic); /* Enable HW TSO on Pass2 */ if (!pass1_silicon(dev)) nic->hw_tso = TRUE; rid = VNIC_VF_REG_RID; nic->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (nic->reg_base == NULL) { device_printf(dev, "Could not allocate registers memory\n"); return (ENXIO); } qcount = MAX_CMP_QUEUES_PER_QS; nic->max_queues = qcount; err = nicvf_set_qset_resources(nic); if (err != 0) goto err_free_res; /* Check if PF is alive and get MAC address for this VF */ err = nicvf_allocate_misc_interrupt(nic); if (err != 0) goto err_free_res; NICVF_CORE_LOCK(nic); err = nicvf_enable_misc_interrupt(nic); NICVF_CORE_UNLOCK(nic); if (err != 0) goto err_release_intr; err = nicvf_allocate_net_interrupts(nic); if (err != 0) { device_printf(dev, "Could not allocate network interface interrupts\n"); goto err_free_ifnet; } /* If no MAC address was obtained we generate random one */ if (memcmp(nic->hwaddr, zeromac, ETHER_ADDR_LEN) == 0) { nicvf_hw_addr_random(hwaddr); memcpy(nic->hwaddr, hwaddr, ETHER_ADDR_LEN); NICVF_CORE_LOCK(nic); nicvf_hw_set_mac_addr(nic, hwaddr); NICVF_CORE_UNLOCK(nic); } /* Configure CPI alorithm */ nic->cpi_alg = CPI_ALG_NONE; NICVF_CORE_LOCK(nic); nicvf_config_cpi(nic); + /* Configure receive side scaling */ + if (nic->qs->rq_cnt > 1) + nicvf_rss_init(nic); NICVF_CORE_UNLOCK(nic); err = nicvf_setup_ifnet(nic); if (err != 0) { device_printf(dev, "Could not set-up ifnet\n"); goto err_release_intr; } err = nicvf_setup_ifmedia(nic); if (err != 0) { device_printf(dev, "Could not set-up ifmedia\n"); goto err_free_ifnet; } mtx_init(&nic->stats_mtx, "VNIC stats", NULL, MTX_DEF); callout_init_mtx(&nic->stats_callout, &nic->stats_mtx, 0); ether_ifattach(nic->ifp, nic->hwaddr); return (0); err_free_ifnet: if_free(nic->ifp); err_release_intr: nicvf_release_all_interrupts(nic); err_free_res: bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(nic->reg_base), nic->reg_base); return (err); } static int nicvf_detach(device_t dev) { struct nicvf *nic; nic = device_get_softc(dev); NICVF_CORE_LOCK(nic); /* Shut down the port and release ring resources */ nicvf_stop_locked(nic); /* Release stats lock */ mtx_destroy(&nic->stats_mtx); /* Release interrupts */ nicvf_release_all_interrupts(nic); /* Release memory resource */ if (nic->reg_base != NULL) { bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(nic->reg_base), nic->reg_base); } /* Remove all ifmedia configurations */ ifmedia_removeall(&nic->if_media); /* Free this ifnet */ if_free(nic->ifp); NICVF_CORE_UNLOCK(nic); /* Finally destroy the lock */ NICVF_CORE_LOCK_DESTROY(nic); return (0); } static void nicvf_hw_addr_random(uint8_t *hwaddr) { uint32_t rnd; uint8_t addr[ETHER_ADDR_LEN]; /* * Create randomized MAC address. * Set 'bsd' + random 24 low-order bits. */ rnd = arc4random() & 0x00ffffff; addr[0] = 'b'; addr[1] = 's'; addr[2] = 'd'; addr[3] = rnd >> 16; addr[4] = rnd >> 8; addr[5] = rnd >> 0; memcpy(hwaddr, addr, ETHER_ADDR_LEN); } static int nicvf_setup_ifnet(struct nicvf *nic) { struct ifnet *ifp; ifp = if_alloc(IFT_ETHER); if (ifp == NULL) { device_printf(nic->dev, "Could not allocate ifnet structure\n"); return (ENOMEM); } nic->ifp = ifp; if_setsoftc(ifp, nic); if_initname(ifp, device_get_name(nic->dev), device_get_unit(nic->dev)); if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX); if_settransmitfn(ifp, nicvf_if_transmit); if_setqflushfn(ifp, nicvf_if_qflush); if_setioctlfn(ifp, nicvf_if_ioctl); if_setinitfn(ifp, nicvf_if_init); if_setgetcounterfn(ifp, nicvf_if_getcounter); if_setmtu(ifp, ETHERMTU); /* Reset caps */ if_setcapabilities(ifp, 0); /* Set the default values */ if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); if_setcapabilitiesbit(ifp, IFCAP_LRO, 0); if (nic->hw_tso) { /* TSO */ if_setcapabilitiesbit(ifp, IFCAP_TSO4, 0); /* TSO parameters */ ifp->if_hw_tsomax = NICVF_TSO_MAXSIZE; ifp->if_hw_tsomaxsegcount = NICVF_TSO_NSEGS; ifp->if_hw_tsomaxsegsize = MCLBYTES; } /* IP/TCP/UDP HW checksums */ if_setcapabilitiesbit(ifp, IFCAP_HWCSUM, 0); if_setcapabilitiesbit(ifp, IFCAP_HWSTATS, 0); /* * HW offload enable */ if_clearhwassist(ifp); if_sethwassistbits(ifp, (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP), 0); if (nic->hw_tso) if_sethwassistbits(ifp, (CSUM_TSO), 0); if_setcapenable(ifp, if_getcapabilities(ifp)); return (0); } static int nicvf_setup_ifmedia(struct nicvf *nic) { ifmedia_init(&nic->if_media, IFM_IMASK, nicvf_media_change, nicvf_media_status); /* * Advertise availability of all possible connection types, * even though not all are possible at the same time. */ ifmedia_add(&nic->if_media, (IFM_ETHER | IFM_10_T | IFM_FDX), 0, NULL); ifmedia_add(&nic->if_media, (IFM_ETHER | IFM_100_TX | IFM_FDX), 0, NULL); ifmedia_add(&nic->if_media, (IFM_ETHER | IFM_1000_T | IFM_FDX), 0, NULL); ifmedia_add(&nic->if_media, (IFM_ETHER | IFM_10G_SR | IFM_FDX), 0, NULL); ifmedia_add(&nic->if_media, (IFM_ETHER | IFM_40G_CR4 | IFM_FDX), 0, NULL); ifmedia_add(&nic->if_media, (IFM_ETHER | IFM_AUTO | IFM_FDX), 0, NULL); ifmedia_set(&nic->if_media, (IFM_ETHER | IFM_AUTO | IFM_FDX)); return (0); } static int nicvf_if_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) { struct nicvf *nic; struct rcv_queue *rq; struct ifreq *ifr; uint32_t flags; int mask, err; int rq_idx; #if defined(INET) || defined(INET6) struct ifaddr *ifa; boolean_t avoid_reset = FALSE; #endif nic = if_getsoftc(ifp); ifr = (struct ifreq *)data; #if defined(INET) || defined(INET6) ifa = (struct ifaddr *)data; #endif err = 0; switch (cmd) { case SIOCSIFADDR: #ifdef INET if (ifa->ifa_addr->sa_family == AF_INET) avoid_reset = TRUE; #endif #ifdef INET6 if (ifa->ifa_addr->sa_family == AF_INET6) avoid_reset = TRUE; #endif #if defined(INET) || defined(INET6) /* Avoid reinitialization unless it's necessary */ if (avoid_reset) { ifp->if_flags |= IFF_UP; if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) nicvf_if_init(nic); #ifdef INET if (!(if_getflags(ifp) & IFF_NOARP)) arp_ifinit(ifp, ifa); #endif return (0); } #endif err = ether_ioctl(ifp, cmd, data); break; case SIOCSIFMTU: /* * ARM64TODO: Needs to be implemented. * Currently ETHERMTU is set by default. */ err = ether_ioctl(ifp, cmd, data); break; case SIOCSIFFLAGS: NICVF_CORE_LOCK(nic); if (if_getflags(ifp) & IFF_UP) { if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { flags = ifp->if_flags ^ nic->if_flags; if ((nic->if_flags & ifp->if_flags) & IFF_PROMISC) { /* Change promiscous mode */ #if 0 /* ARM64TODO */ nicvf_set_promiscous(nic); #endif } if ((nic->if_flags ^ ifp->if_flags) & IFF_ALLMULTI) { /* Change multicasting settings */ #if 0 /* ARM64TODO */ nicvf_set_multicast(nic); #endif } } else { nicvf_if_init_locked(nic); } } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) nicvf_stop_locked(nic); nic->if_flags = ifp->if_flags; NICVF_CORE_UNLOCK(nic); break; case SIOCADDMULTI: case SIOCDELMULTI: if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { #if 0 NICVF_CORE_LOCK(nic); /* ARM64TODO */ nicvf_set_multicast(nic); NICVF_CORE_UNLOCK(nic); #endif } break; case SIOCSIFMEDIA: case SIOCGIFMEDIA: err = ifmedia_ioctl(ifp, ifr, &nic->if_media, cmd); break; case SIOCSIFCAP: mask = ifp->if_capenable ^ ifr->ifr_reqcap; if (mask & IFCAP_VLAN_MTU) { /* No work to do except acknowledge the change took. */ ifp->if_capenable ^= IFCAP_VLAN_MTU; } if (mask & IFCAP_TXCSUM) ifp->if_capenable ^= IFCAP_TXCSUM; if (mask & IFCAP_RXCSUM) ifp->if_capenable ^= IFCAP_RXCSUM; if ((mask & IFCAP_TSO4) && nic->hw_tso) ifp->if_capenable ^= IFCAP_TSO4; if (mask & IFCAP_LRO) { /* * Lock the driver for a moment to avoid * mismatch in per-queue settings. */ NICVF_CORE_LOCK(nic); ifp->if_capenable ^= IFCAP_LRO; if ((if_getdrvflags(nic->ifp) & IFF_DRV_RUNNING) != 0) { /* * Now disable LRO for subsequent packets. * Atomicity of this change is not necessary * as we don't need precise toggle of this * feature for all threads processing the * completion queue. */ for (rq_idx = 0; rq_idx < nic->qs->rq_cnt; rq_idx++) { rq = &nic->qs->rq[rq_idx]; rq->lro_enabled = !rq->lro_enabled; } } NICVF_CORE_UNLOCK(nic); } break; default: err = ether_ioctl(ifp, cmd, data); break; } return (err); } static void nicvf_if_init_locked(struct nicvf *nic) { struct queue_set *qs = nic->qs; struct ifnet *ifp; int qidx; int err; caddr_t if_addr; NICVF_CORE_LOCK_ASSERT(nic); ifp = nic->ifp; if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) nicvf_stop_locked(nic); err = nicvf_enable_misc_interrupt(nic); if (err != 0) { if_printf(ifp, "Could not reenable Mbox interrupt\n"); return; } /* Get the latest MAC address */ if_addr = if_getlladdr(ifp); /* Update MAC address if changed */ if (memcmp(nic->hwaddr, if_addr, ETHER_ADDR_LEN) != 0) { memcpy(nic->hwaddr, if_addr, ETHER_ADDR_LEN); nicvf_hw_set_mac_addr(nic, if_addr); } /* Initialize the queues */ err = nicvf_init_resources(nic); if (err != 0) goto error; /* Make sure queue initialization is written */ wmb(); nicvf_reg_write(nic, NIC_VF_INT, ~0UL); /* Enable Qset err interrupt */ nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0); /* Enable completion queue interrupt */ for (qidx = 0; qidx < qs->cq_cnt; qidx++) nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx); /* Enable RBDR threshold interrupt */ for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) nicvf_enable_intr(nic, NICVF_INTR_RBDR, qidx); nic->drv_stats.txq_stop = 0; nic->drv_stats.txq_wake = 0; /* Activate network interface */ if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); /* Schedule callout to update stats */ callout_reset(&nic->stats_callout, hz, nicvf_tick_stats, nic); return; error: /* Something went very wrong. Disable this ifnet for good */ if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); } static void nicvf_if_init(void *if_softc) { struct nicvf *nic = if_softc; NICVF_CORE_LOCK(nic); nicvf_if_init_locked(nic); NICVF_CORE_UNLOCK(nic); } static int nicvf_if_transmit(struct ifnet *ifp, struct mbuf *mbuf) { struct nicvf *nic = if_getsoftc(ifp); struct queue_set *qs = nic->qs; struct snd_queue *sq; struct mbuf *mtmp; int qidx; int err = 0; if (__predict_false(qs == NULL)) { panic("%s: missing queue set for %s", __func__, device_get_nameunit(nic->dev)); } /* Select queue */ if (M_HASHTYPE_GET(mbuf) != M_HASHTYPE_NONE) qidx = mbuf->m_pkthdr.flowid % qs->sq_cnt; else qidx = curcpu % qs->sq_cnt; sq = &qs->sq[qidx]; if (mbuf->m_next != NULL && (mbuf->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP)) != 0) { if (M_WRITABLE(mbuf) == 0) { mtmp = m_dup(mbuf, M_NOWAIT); m_freem(mbuf); if (mtmp == NULL) return (ENOBUFS); mbuf = mtmp; } } err = drbr_enqueue(ifp, sq->br, mbuf); if (((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING) || !nic->link_up || (err != 0)) { /* * Try to enqueue packet to the ring buffer. * If the driver is not active, link down or enqueue operation * failed, return with the appropriate error code. */ return (err); } if (NICVF_TX_TRYLOCK(sq) != 0) { err = nicvf_xmit_locked(sq); NICVF_TX_UNLOCK(sq); return (err); } else taskqueue_enqueue(sq->snd_taskq, &sq->snd_task); return (0); } static void nicvf_if_qflush(struct ifnet *ifp) { struct nicvf *nic; struct queue_set *qs; struct snd_queue *sq; struct mbuf *mbuf; size_t idx; nic = if_getsoftc(ifp); qs = nic->qs; for (idx = 0; idx < qs->sq_cnt; idx++) { sq = &qs->sq[idx]; NICVF_TX_LOCK(sq); while ((mbuf = buf_ring_dequeue_sc(sq->br)) != NULL) m_freem(mbuf); NICVF_TX_UNLOCK(sq); } if_qflush(ifp); } static uint64_t nicvf_if_getcounter(struct ifnet *ifp, ift_counter cnt) { struct nicvf *nic; struct nicvf_hw_stats *hw_stats; struct nicvf_drv_stats *drv_stats; nic = if_getsoftc(ifp); hw_stats = &nic->hw_stats; drv_stats = &nic->drv_stats; switch (cnt) { case IFCOUNTER_IPACKETS: return (drv_stats->rx_frames_ok); case IFCOUNTER_OPACKETS: return (drv_stats->tx_frames_ok); case IFCOUNTER_IBYTES: return (hw_stats->rx_bytes); case IFCOUNTER_OBYTES: return (hw_stats->tx_bytes_ok); case IFCOUNTER_IMCASTS: return (hw_stats->rx_mcast_frames); case IFCOUNTER_COLLISIONS: return (0); case IFCOUNTER_IQDROPS: return (drv_stats->rx_drops); case IFCOUNTER_OQDROPS: return (drv_stats->tx_drops); default: return (if_get_counter_default(ifp, cnt)); } } static void nicvf_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) { struct nicvf *nic = if_getsoftc(ifp); NICVF_CORE_LOCK(nic); ifmr->ifm_status = IFM_AVALID; ifmr->ifm_active = IFM_ETHER; if (nic->link_up) { /* Device attached to working network */ ifmr->ifm_status |= IFM_ACTIVE; } switch (nic->speed) { case SPEED_10: ifmr->ifm_active |= IFM_10_T; break; case SPEED_100: ifmr->ifm_active |= IFM_100_TX; break; case SPEED_1000: ifmr->ifm_active |= IFM_1000_T; break; case SPEED_10000: ifmr->ifm_active |= IFM_10G_SR; break; case SPEED_40000: ifmr->ifm_active |= IFM_40G_CR4; break; default: ifmr->ifm_active |= IFM_AUTO; break; } if (nic->duplex) ifmr->ifm_active |= IFM_FDX; else ifmr->ifm_active |= IFM_HDX; NICVF_CORE_UNLOCK(nic); } static int nicvf_media_change(struct ifnet *ifp __unused) { return (0); } /* Register read/write APIs */ void nicvf_reg_write(struct nicvf *nic, bus_space_handle_t offset, uint64_t val) { bus_write_8(nic->reg_base, offset, val); } uint64_t nicvf_reg_read(struct nicvf *nic, uint64_t offset) { return (bus_read_8(nic->reg_base, offset)); } void nicvf_queue_reg_write(struct nicvf *nic, bus_space_handle_t offset, uint64_t qidx, uint64_t val) { bus_write_8(nic->reg_base, offset + (qidx << NIC_Q_NUM_SHIFT), val); } uint64_t nicvf_queue_reg_read(struct nicvf *nic, bus_space_handle_t offset, uint64_t qidx) { return (bus_read_8(nic->reg_base, offset + (qidx << NIC_Q_NUM_SHIFT))); } /* VF -> PF mailbox communication */ static void nicvf_write_to_mbx(struct nicvf *nic, union nic_mbx *mbx) { uint64_t *msg = (uint64_t *)mbx; nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 0, msg[0]); nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 8, msg[1]); } int nicvf_send_msg_to_pf(struct nicvf *nic, union nic_mbx *mbx) { int timeout = NIC_MBOX_MSG_TIMEOUT * 10; int sleep = 2; NICVF_CORE_LOCK_ASSERT(nic); nic->pf_acked = FALSE; nic->pf_nacked = FALSE; nicvf_write_to_mbx(nic, mbx); /* Wait for previous message to be acked, timeout 2sec */ while (!nic->pf_acked) { if (nic->pf_nacked) return (EINVAL); DELAY(sleep * 1000); if (nic->pf_acked) break; timeout -= sleep; if (!timeout) { device_printf(nic->dev, "PF didn't ack to mbox msg %d from VF%d\n", (mbx->msg.msg & 0xFF), nic->vf_id); return (EBUSY); } } return (0); } /* * Checks if VF is able to comminicate with PF * and also gets the VNIC number this VF is associated to. */ static int nicvf_check_pf_ready(struct nicvf *nic) { union nic_mbx mbx = {}; mbx.msg.msg = NIC_MBOX_MSG_READY; if (nicvf_send_msg_to_pf(nic, &mbx)) { device_printf(nic->dev, "PF didn't respond to READY msg\n"); return 0; } return 1; } static void nicvf_read_bgx_stats(struct nicvf *nic, struct bgx_stats_msg *bgx) { if (bgx->rx) nic->bgx_stats.rx_stats[bgx->idx] = bgx->stats; else nic->bgx_stats.tx_stats[bgx->idx] = bgx->stats; } static void nicvf_handle_mbx_intr(struct nicvf *nic) { union nic_mbx mbx = {}; uint64_t *mbx_data; uint64_t mbx_addr; int i; mbx_addr = NIC_VF_PF_MAILBOX_0_1; mbx_data = (uint64_t *)&mbx; for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) { *mbx_data = nicvf_reg_read(nic, mbx_addr); mbx_data++; mbx_addr += sizeof(uint64_t); } switch (mbx.msg.msg) { case NIC_MBOX_MSG_READY: nic->pf_acked = TRUE; nic->vf_id = mbx.nic_cfg.vf_id & 0x7F; nic->tns_mode = mbx.nic_cfg.tns_mode & 0x7F; nic->node = mbx.nic_cfg.node_id; memcpy(nic->hwaddr, mbx.nic_cfg.mac_addr, ETHER_ADDR_LEN); nic->loopback_supported = mbx.nic_cfg.loopback_supported; nic->link_up = FALSE; nic->duplex = 0; nic->speed = 0; break; case NIC_MBOX_MSG_ACK: nic->pf_acked = TRUE; break; case NIC_MBOX_MSG_NACK: nic->pf_nacked = TRUE; break; + case NIC_MBOX_MSG_RSS_SIZE: + nic->rss_info.rss_size = mbx.rss_size.ind_tbl_size; + nic->pf_acked = TRUE; + break; case NIC_MBOX_MSG_BGX_STATS: nicvf_read_bgx_stats(nic, &mbx.bgx_stats); nic->pf_acked = TRUE; break; case NIC_MBOX_MSG_BGX_LINK_CHANGE: nic->pf_acked = TRUE; nic->link_up = mbx.link_status.link_up; nic->duplex = mbx.link_status.duplex; nic->speed = mbx.link_status.speed; if (nic->link_up) { if_setbaudrate(nic->ifp, nic->speed * 1000000); if_link_state_change(nic->ifp, LINK_STATE_UP); } else { if_setbaudrate(nic->ifp, 0); if_link_state_change(nic->ifp, LINK_STATE_DOWN); } break; default: device_printf(nic->dev, "Invalid message from PF, msg 0x%x\n", mbx.msg.msg); break; } nicvf_clear_intr(nic, NICVF_INTR_MBOX, 0); } static int nicvf_hw_set_mac_addr(struct nicvf *nic, uint8_t *hwaddr) { union nic_mbx mbx = {}; mbx.mac.msg = NIC_MBOX_MSG_SET_MAC; mbx.mac.vf_id = nic->vf_id; memcpy(mbx.mac.mac_addr, hwaddr, ETHER_ADDR_LEN); return (nicvf_send_msg_to_pf(nic, &mbx)); } static void nicvf_config_cpi(struct nicvf *nic) { union nic_mbx mbx = {}; mbx.cpi_cfg.msg = NIC_MBOX_MSG_CPI_CFG; mbx.cpi_cfg.vf_id = nic->vf_id; mbx.cpi_cfg.cpi_alg = nic->cpi_alg; mbx.cpi_cfg.rq_cnt = nic->qs->rq_cnt; nicvf_send_msg_to_pf(nic, &mbx); +} + +static void +nicvf_get_rss_size(struct nicvf *nic) +{ + union nic_mbx mbx = {}; + + mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE; + mbx.rss_size.vf_id = nic->vf_id; + nicvf_send_msg_to_pf(nic, &mbx); +} + +static void +nicvf_config_rss(struct nicvf *nic) +{ + union nic_mbx mbx = {}; + struct nicvf_rss_info *rss; + int ind_tbl_len; + int i, nextq; + + rss = &nic->rss_info; + ind_tbl_len = rss->rss_size; + nextq = 0; + + mbx.rss_cfg.vf_id = nic->vf_id; + mbx.rss_cfg.hash_bits = rss->hash_bits; + while (ind_tbl_len != 0) { + mbx.rss_cfg.tbl_offset = nextq; + mbx.rss_cfg.tbl_len = MIN(ind_tbl_len, + RSS_IND_TBL_LEN_PER_MBX_MSG); + mbx.rss_cfg.msg = mbx.rss_cfg.tbl_offset ? + NIC_MBOX_MSG_RSS_CFG_CONT : NIC_MBOX_MSG_RSS_CFG; + + for (i = 0; i < mbx.rss_cfg.tbl_len; i++) + mbx.rss_cfg.ind_tbl[i] = rss->ind_tbl[nextq++]; + + nicvf_send_msg_to_pf(nic, &mbx); + + ind_tbl_len -= mbx.rss_cfg.tbl_len; + } +} + +static void +nicvf_set_rss_key(struct nicvf *nic) +{ + struct nicvf_rss_info *rss; + uint64_t key_addr; + int idx; + + rss = &nic->rss_info; + key_addr = NIC_VNIC_RSS_KEY_0_4; + + for (idx = 0; idx < RSS_HASH_KEY_SIZE; idx++) { + nicvf_reg_write(nic, key_addr, rss->key[idx]); + key_addr += sizeof(uint64_t); + } +} + +static int +nicvf_rss_init(struct nicvf *nic) +{ + struct nicvf_rss_info *rss; + int idx; + + nicvf_get_rss_size(nic); + + rss = &nic->rss_info; + if (nic->cpi_alg != CPI_ALG_NONE) { + rss->enable = FALSE; + rss->hash_bits = 0; + return (ENXIO); + } + + rss->enable = TRUE; + + /* Using the HW reset value for now */ + rss->key[0] = 0xFEED0BADFEED0BADUL; + rss->key[1] = 0xFEED0BADFEED0BADUL; + rss->key[2] = 0xFEED0BADFEED0BADUL; + rss->key[3] = 0xFEED0BADFEED0BADUL; + rss->key[4] = 0xFEED0BADFEED0BADUL; + + nicvf_set_rss_key(nic); + + rss->cfg = RSS_IP_HASH_ENA | RSS_TCP_HASH_ENA | RSS_UDP_HASH_ENA; + nicvf_reg_write(nic, NIC_VNIC_RSS_CFG, rss->cfg); + + rss->hash_bits = fls(rss->rss_size) - 1; + for (idx = 0; idx < rss->rss_size; idx++) + rss->ind_tbl[idx] = idx % nic->rx_queues; + + nicvf_config_rss(nic); + + return (0); } static int nicvf_init_resources(struct nicvf *nic) { int err; union nic_mbx mbx = {}; mbx.msg.msg = NIC_MBOX_MSG_CFG_DONE; /* Enable Qset */ nicvf_qset_config(nic, TRUE); /* Initialize queues and HW for data transfer */ err = nicvf_config_data_transfer(nic, TRUE); if (err) { device_printf(nic->dev, "Failed to alloc/config VF's QSet resources\n"); return (err); } /* Send VF config done msg to PF */ nicvf_write_to_mbx(nic, &mbx); return (0); } static void nicvf_misc_intr_handler(void *arg) { struct nicvf *nic = (struct nicvf *)arg; uint64_t intr; intr = nicvf_reg_read(nic, NIC_VF_INT); /* Check for spurious interrupt */ if (!(intr & NICVF_INTR_MBOX_MASK)) return; nicvf_handle_mbx_intr(nic); } static int nicvf_intr_handler(void *arg) { struct nicvf *nic; struct cmp_queue *cq; int qidx; cq = (struct cmp_queue *)arg; nic = cq->nic; qidx = cq->idx; /* Disable interrupts */ nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx); taskqueue_enqueue(cq->cmp_taskq, &cq->cmp_task); /* Clear interrupt */ nicvf_clear_intr(nic, NICVF_INTR_CQ, qidx); return (FILTER_HANDLED); } static void nicvf_rbdr_intr_handler(void *arg) { struct nicvf *nic; struct queue_set *qs; struct rbdr *rbdr; int qidx; nic = (struct nicvf *)arg; /* Disable RBDR interrupt and schedule softirq */ for (qidx = 0; qidx < nic->qs->rbdr_cnt; qidx++) { if (!nicvf_is_intr_enabled(nic, NICVF_INTR_RBDR, qidx)) continue; nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx); qs = nic->qs; rbdr = &qs->rbdr[qidx]; taskqueue_enqueue(rbdr->rbdr_taskq, &rbdr->rbdr_task_nowait); /* Clear interrupt */ nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx); } } static void nicvf_qs_err_intr_handler(void *arg) { struct nicvf *nic = (struct nicvf *)arg; struct queue_set *qs = nic->qs; /* Disable Qset err interrupt and schedule softirq */ nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0); taskqueue_enqueue(qs->qs_err_taskq, &qs->qs_err_task); nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0); } static int nicvf_enable_msix(struct nicvf *nic) { struct pci_devinfo *dinfo; int rid, count; int ret; dinfo = device_get_ivars(nic->dev); rid = dinfo->cfg.msix.msix_table_bar; nic->msix_table_res = bus_alloc_resource_any(nic->dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (nic->msix_table_res == NULL) { device_printf(nic->dev, "Could not allocate memory for MSI-X table\n"); return (ENXIO); } count = nic->num_vec = NIC_VF_MSIX_VECTORS; ret = pci_alloc_msix(nic->dev, &count); if ((ret != 0) || (count != nic->num_vec)) { device_printf(nic->dev, "Request for #%d msix vectors failed, error: %d\n", nic->num_vec, ret); return (ret); } nic->msix_enabled = 1; return (0); } static void nicvf_disable_msix(struct nicvf *nic) { if (nic->msix_enabled) { pci_release_msi(nic->dev); nic->msix_enabled = 0; nic->num_vec = 0; } } static void nicvf_release_all_interrupts(struct nicvf *nic) { struct resource *res; int irq; int err; /* Free registered interrupts */ for (irq = 0; irq < nic->num_vec; irq++) { res = nic->msix_entries[irq].irq_res; if (res == NULL) continue; /* Teardown interrupt first */ if (nic->msix_entries[irq].handle != NULL) { err = bus_teardown_intr(nic->dev, nic->msix_entries[irq].irq_res, nic->msix_entries[irq].handle); KASSERT(err == 0, ("ERROR: Unable to teardown interrupt %d", irq)); nic->msix_entries[irq].handle = NULL; } bus_release_resource(nic->dev, SYS_RES_IRQ, rman_get_rid(res), nic->msix_entries[irq].irq_res); nic->msix_entries[irq].irq_res = NULL; } /* Disable MSI-X */ nicvf_disable_msix(nic); } /* * Initialize MSIX vectors and register MISC interrupt. * Send READY message to PF to check if its alive */ static int nicvf_allocate_misc_interrupt(struct nicvf *nic) { struct resource *res; int irq, rid; int ret = 0; /* Return if mailbox interrupt is already registered */ if (nic->msix_enabled) return (0); /* Enable MSI-X */ if (nicvf_enable_msix(nic) != 0) return (ENXIO); irq = NICVF_INTR_ID_MISC; rid = irq + 1; nic->msix_entries[irq].irq_res = bus_alloc_resource_any(nic->dev, SYS_RES_IRQ, &rid, (RF_SHAREABLE | RF_ACTIVE)); if (nic->msix_entries[irq].irq_res == NULL) { device_printf(nic->dev, "Could not allocate Mbox interrupt for VF%d\n", device_get_unit(nic->dev)); return (ENXIO); } ret = bus_setup_intr(nic->dev, nic->msix_entries[irq].irq_res, (INTR_MPSAFE | INTR_TYPE_MISC), NULL, nicvf_misc_intr_handler, nic, &nic->msix_entries[irq].handle); if (ret != 0) { res = nic->msix_entries[irq].irq_res; bus_release_resource(nic->dev, SYS_RES_IRQ, rman_get_rid(res), res); nic->msix_entries[irq].irq_res = NULL; return (ret); } return (0); } static int nicvf_enable_misc_interrupt(struct nicvf *nic) { /* Enable mailbox interrupt */ nicvf_enable_intr(nic, NICVF_INTR_MBOX, 0); /* Check if VF is able to communicate with PF */ if (!nicvf_check_pf_ready(nic)) { nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0); return (ENXIO); } return (0); } static void nicvf_release_net_interrupts(struct nicvf *nic) { struct resource *res; int irq; int err; for_each_cq_irq(irq) { res = nic->msix_entries[irq].irq_res; if (res == NULL) continue; /* Teardown active interrupts first */ if (nic->msix_entries[irq].handle != NULL) { err = bus_teardown_intr(nic->dev, nic->msix_entries[irq].irq_res, nic->msix_entries[irq].handle); KASSERT(err == 0, ("ERROR: Unable to teardown CQ interrupt %d", (irq - NICVF_INTR_ID_CQ))); if (err != 0) continue; } /* Release resource */ bus_release_resource(nic->dev, SYS_RES_IRQ, rman_get_rid(res), res); nic->msix_entries[irq].irq_res = NULL; } for_each_rbdr_irq(irq) { res = nic->msix_entries[irq].irq_res; if (res == NULL) continue; /* Teardown active interrupts first */ if (nic->msix_entries[irq].handle != NULL) { err = bus_teardown_intr(nic->dev, nic->msix_entries[irq].irq_res, nic->msix_entries[irq].handle); KASSERT(err == 0, ("ERROR: Unable to teardown RDBR interrupt %d", (irq - NICVF_INTR_ID_RBDR))); if (err != 0) continue; } /* Release resource */ bus_release_resource(nic->dev, SYS_RES_IRQ, rman_get_rid(res), res); nic->msix_entries[irq].irq_res = NULL; } irq = NICVF_INTR_ID_QS_ERR; res = nic->msix_entries[irq].irq_res; if (res != NULL) { /* Teardown active interrupts first */ if (nic->msix_entries[irq].handle != NULL) { err = bus_teardown_intr(nic->dev, nic->msix_entries[irq].irq_res, nic->msix_entries[irq].handle); KASSERT(err == 0, ("ERROR: Unable to teardown QS Error interrupt %d", irq)); if (err != 0) return; } /* Release resource */ bus_release_resource(nic->dev, SYS_RES_IRQ, rman_get_rid(res), res); nic->msix_entries[irq].irq_res = NULL; } } static int nicvf_allocate_net_interrupts(struct nicvf *nic) { u_int cpuid; int irq, rid; int qidx; int ret = 0; /* MSI-X must be configured by now */ if (!nic->msix_enabled) { device_printf(nic->dev, "Cannot alloacte queue interrups. " "MSI-X interrupts disabled.\n"); return (ENXIO); } /* Register CQ interrupts */ for_each_cq_irq(irq) { if (irq >= (NICVF_INTR_ID_CQ + nic->qs->cq_cnt)) break; qidx = irq - NICVF_INTR_ID_CQ; rid = irq + 1; nic->msix_entries[irq].irq_res = bus_alloc_resource_any(nic->dev, SYS_RES_IRQ, &rid, (RF_SHAREABLE | RF_ACTIVE)); if (nic->msix_entries[irq].irq_res == NULL) { device_printf(nic->dev, "Could not allocate CQ interrupt %d for VF%d\n", (irq - NICVF_INTR_ID_CQ), device_get_unit(nic->dev)); ret = ENXIO; goto error; } ret = bus_setup_intr(nic->dev, nic->msix_entries[irq].irq_res, (INTR_MPSAFE | INTR_TYPE_NET), nicvf_intr_handler, NULL, &nic->qs->cq[qidx], &nic->msix_entries[irq].handle); if (ret != 0) { device_printf(nic->dev, "Could not setup CQ interrupt %d for VF%d\n", (irq - NICVF_INTR_ID_CQ), device_get_unit(nic->dev)); goto error; } cpuid = (device_get_unit(nic->dev) * CMP_QUEUE_CNT) + qidx; cpuid %= mp_ncpus; /* * Save CPU ID for later use when system-wide RSS is enabled. * It will be used to pit the CQ task to the same CPU that got * interrupted. */ nic->qs->cq[qidx].cmp_cpuid = cpuid; if (bootverbose) { device_printf(nic->dev, "bind CQ%d IRQ to CPU%d\n", qidx, cpuid); } /* Bind interrupts to the given CPU */ bus_bind_intr(nic->dev, nic->msix_entries[irq].irq_res, cpuid); } /* Register RBDR interrupt */ for_each_rbdr_irq(irq) { if (irq >= (NICVF_INTR_ID_RBDR + nic->qs->rbdr_cnt)) break; rid = irq + 1; nic->msix_entries[irq].irq_res = bus_alloc_resource_any(nic->dev, SYS_RES_IRQ, &rid, (RF_SHAREABLE | RF_ACTIVE)); if (nic->msix_entries[irq].irq_res == NULL) { device_printf(nic->dev, "Could not allocate RBDR interrupt %d for VF%d\n", (irq - NICVF_INTR_ID_RBDR), device_get_unit(nic->dev)); ret = ENXIO; goto error; } ret = bus_setup_intr(nic->dev, nic->msix_entries[irq].irq_res, (INTR_MPSAFE | INTR_TYPE_NET), NULL, nicvf_rbdr_intr_handler, nic, &nic->msix_entries[irq].handle); if (ret != 0) { device_printf(nic->dev, "Could not setup RBDR interrupt %d for VF%d\n", (irq - NICVF_INTR_ID_RBDR), device_get_unit(nic->dev)); goto error; } } /* Register QS error interrupt */ irq = NICVF_INTR_ID_QS_ERR; rid = irq + 1; nic->msix_entries[irq].irq_res = bus_alloc_resource_any(nic->dev, SYS_RES_IRQ, &rid, (RF_SHAREABLE | RF_ACTIVE)); if (nic->msix_entries[irq].irq_res == NULL) { device_printf(nic->dev, "Could not allocate QS Error interrupt for VF%d\n", device_get_unit(nic->dev)); ret = ENXIO; goto error; } ret = bus_setup_intr(nic->dev, nic->msix_entries[irq].irq_res, (INTR_MPSAFE | INTR_TYPE_NET), NULL, nicvf_qs_err_intr_handler, nic, &nic->msix_entries[irq].handle); if (ret != 0) { device_printf(nic->dev, "Could not setup QS Error interrupt for VF%d\n", device_get_unit(nic->dev)); goto error; } return (0); error: nicvf_release_net_interrupts(nic); return (ret); } static int nicvf_stop_locked(struct nicvf *nic) { struct ifnet *ifp; int qidx; struct queue_set *qs = nic->qs; union nic_mbx mbx = {}; NICVF_CORE_LOCK_ASSERT(nic); /* Stop callout. Can block here since holding SX lock */ callout_drain(&nic->stats_callout); ifp = nic->ifp; mbx.msg.msg = NIC_MBOX_MSG_SHUTDOWN; nicvf_send_msg_to_pf(nic, &mbx); /* Disable RBDR & QS error interrupts */ for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) { nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx); nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx); } nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0); nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0); /* Deactivate network interface */ if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); /* Free resources */ nicvf_config_data_transfer(nic, FALSE); /* Disable HW Qset */ nicvf_qset_config(nic, FALSE); /* disable mailbox interrupt */ nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0); return (0); } static void nicvf_update_stats(struct nicvf *nic) { int qidx; struct nicvf_hw_stats *stats = &nic->hw_stats; struct nicvf_drv_stats *drv_stats = &nic->drv_stats; struct queue_set *qs = nic->qs; #define GET_RX_STATS(reg) \ nicvf_reg_read(nic, NIC_VNIC_RX_STAT_0_13 | ((reg) << 3)) #define GET_TX_STATS(reg) \ nicvf_reg_read(nic, NIC_VNIC_TX_STAT_0_4 | ((reg) << 3)) stats->rx_bytes = GET_RX_STATS(RX_OCTS); stats->rx_ucast_frames = GET_RX_STATS(RX_UCAST); stats->rx_bcast_frames = GET_RX_STATS(RX_BCAST); stats->rx_mcast_frames = GET_RX_STATS(RX_MCAST); stats->rx_fcs_errors = GET_RX_STATS(RX_FCS); stats->rx_l2_errors = GET_RX_STATS(RX_L2ERR); stats->rx_drop_red = GET_RX_STATS(RX_RED); stats->rx_drop_red_bytes = GET_RX_STATS(RX_RED_OCTS); stats->rx_drop_overrun = GET_RX_STATS(RX_ORUN); stats->rx_drop_overrun_bytes = GET_RX_STATS(RX_ORUN_OCTS); stats->rx_drop_bcast = GET_RX_STATS(RX_DRP_BCAST); stats->rx_drop_mcast = GET_RX_STATS(RX_DRP_MCAST); stats->rx_drop_l3_bcast = GET_RX_STATS(RX_DRP_L3BCAST); stats->rx_drop_l3_mcast = GET_RX_STATS(RX_DRP_L3MCAST); stats->tx_bytes_ok = GET_TX_STATS(TX_OCTS); stats->tx_ucast_frames_ok = GET_TX_STATS(TX_UCAST); stats->tx_bcast_frames_ok = GET_TX_STATS(TX_BCAST); stats->tx_mcast_frames_ok = GET_TX_STATS(TX_MCAST); stats->tx_drops = GET_TX_STATS(TX_DROP); drv_stats->tx_frames_ok = stats->tx_ucast_frames_ok + stats->tx_bcast_frames_ok + stats->tx_mcast_frames_ok; drv_stats->rx_drops = stats->rx_drop_red + stats->rx_drop_overrun; drv_stats->tx_drops = stats->tx_drops; /* Update RQ and SQ stats */ for (qidx = 0; qidx < qs->rq_cnt; qidx++) nicvf_update_rq_stats(nic, qidx); for (qidx = 0; qidx < qs->sq_cnt; qidx++) nicvf_update_sq_stats(nic, qidx); } static void nicvf_tick_stats(void *arg) { struct nicvf *nic; nic = (struct nicvf *)arg; /* Read the statistics */ nicvf_update_stats(nic); callout_reset(&nic->stats_callout, hz, nicvf_tick_stats, nic); } Index: head/sys/dev/vnic/nicvf_queues.c =================================================================== --- head/sys/dev/vnic/nicvf_queues.c (revision 299443) +++ head/sys/dev/vnic/nicvf_queues.c (revision 299444) @@ -1,2374 +1,2373 @@ /* * Copyright (C) 2015 Cavium Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #include __FBSDID("$FreeBSD$"); #include "opt_inet.h" #include "opt_inet6.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "thunder_bgx.h" #include "nic_reg.h" #include "nic.h" #include "q_struct.h" #include "nicvf_queues.h" #define DEBUG #undef DEBUG #ifdef DEBUG #define dprintf(dev, fmt, ...) device_printf(dev, fmt, ##__VA_ARGS__) #else #define dprintf(dev, fmt, ...) #endif MALLOC_DECLARE(M_NICVF); static void nicvf_free_snd_queue(struct nicvf *, struct snd_queue *); static struct mbuf * nicvf_get_rcv_mbuf(struct nicvf *, struct cqe_rx_t *); static void nicvf_sq_disable(struct nicvf *, int); static void nicvf_sq_enable(struct nicvf *, struct snd_queue *, int); static void nicvf_put_sq_desc(struct snd_queue *, int); static void nicvf_cmp_queue_config(struct nicvf *, struct queue_set *, int, boolean_t); static void nicvf_sq_free_used_descs(struct nicvf *, struct snd_queue *, int); static int nicvf_tx_mbuf_locked(struct snd_queue *, struct mbuf **); static void nicvf_rbdr_task(void *, int); static void nicvf_rbdr_task_nowait(void *, int); struct rbuf_info { bus_dma_tag_t dmat; bus_dmamap_t dmap; struct mbuf * mbuf; }; #define GET_RBUF_INFO(x) ((struct rbuf_info *)((x) - NICVF_RCV_BUF_ALIGN_BYTES)) /* Poll a register for a specific value */ static int nicvf_poll_reg(struct nicvf *nic, int qidx, uint64_t reg, int bit_pos, int bits, int val) { uint64_t bit_mask; uint64_t reg_val; int timeout = 10; bit_mask = (1UL << bits) - 1; bit_mask = (bit_mask << bit_pos); while (timeout) { reg_val = nicvf_queue_reg_read(nic, reg, qidx); if (((reg_val & bit_mask) >> bit_pos) == val) return (0); DELAY(1000); timeout--; } device_printf(nic->dev, "Poll on reg 0x%lx failed\n", reg); return (ETIMEDOUT); } /* Callback for bus_dmamap_load() */ static void nicvf_dmamap_q_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) { bus_addr_t *paddr; KASSERT(nseg == 1, ("wrong number of segments, should be 1")); paddr = arg; *paddr = segs->ds_addr; } /* Allocate memory for a queue's descriptors */ static int nicvf_alloc_q_desc_mem(struct nicvf *nic, struct q_desc_mem *dmem, int q_len, int desc_size, int align_bytes) { int err, err_dmat; /* Create DMA tag first */ err = bus_dma_tag_create( bus_get_dma_tag(nic->dev), /* parent tag */ align_bytes, /* alignment */ 0, /* boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filtfunc, filtfuncarg */ (q_len * desc_size), /* maxsize */ 1, /* nsegments */ (q_len * desc_size), /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockfuncarg */ &dmem->dmat); /* dmat */ if (err != 0) { device_printf(nic->dev, "Failed to create busdma tag for descriptors ring\n"); return (err); } /* Allocate segment of continuous DMA safe memory */ err = bus_dmamem_alloc( dmem->dmat, /* DMA tag */ &dmem->base, /* virtual address */ (BUS_DMA_NOWAIT | BUS_DMA_ZERO), /* flags */ &dmem->dmap); /* DMA map */ if (err != 0) { device_printf(nic->dev, "Failed to allocate DMA safe memory for" "descriptors ring\n"); goto dmamem_fail; } err = bus_dmamap_load( dmem->dmat, dmem->dmap, dmem->base, (q_len * desc_size), /* allocation size */ nicvf_dmamap_q_cb, /* map to DMA address cb. */ &dmem->phys_base, /* physical address */ BUS_DMA_NOWAIT); if (err != 0) { device_printf(nic->dev, "Cannot load DMA map of descriptors ring\n"); goto dmamap_fail; } dmem->q_len = q_len; dmem->size = (desc_size * q_len); return (0); dmamap_fail: bus_dmamem_free(dmem->dmat, dmem->base, dmem->dmap); dmem->phys_base = 0; dmamem_fail: err_dmat = bus_dma_tag_destroy(dmem->dmat); dmem->base = NULL; KASSERT(err_dmat == 0, ("%s: Trying to destroy BUSY DMA tag", __func__)); return (err); } /* Free queue's descriptor memory */ static void nicvf_free_q_desc_mem(struct nicvf *nic, struct q_desc_mem *dmem) { int err; if ((dmem == NULL) || (dmem->base == NULL)) return; /* Unload a map */ bus_dmamap_sync(dmem->dmat, dmem->dmap, BUS_DMASYNC_POSTREAD); bus_dmamap_unload(dmem->dmat, dmem->dmap); /* Free DMA memory */ bus_dmamem_free(dmem->dmat, dmem->base, dmem->dmap); /* Destroy DMA tag */ err = bus_dma_tag_destroy(dmem->dmat); KASSERT(err == 0, ("%s: Trying to destroy BUSY DMA tag", __func__)); dmem->phys_base = 0; dmem->base = NULL; } /* * Allocate buffer for packet reception * HW returns memory address where packet is DMA'ed but not a pointer * into RBDR ring, so save buffer address at the start of fragment and * align the start address to a cache aligned address */ static __inline int nicvf_alloc_rcv_buffer(struct nicvf *nic, struct rbdr *rbdr, bus_dmamap_t dmap, int mflags, uint32_t buf_len, bus_addr_t *rbuf) { struct mbuf *mbuf; struct rbuf_info *rinfo; bus_dma_segment_t segs[1]; int nsegs; int err; mbuf = m_getjcl(mflags, MT_DATA, M_PKTHDR, MCLBYTES); if (mbuf == NULL) return (ENOMEM); /* * The length is equal to the actual length + one 128b line * used as a room for rbuf_info structure. */ mbuf->m_len = mbuf->m_pkthdr.len = buf_len; err = bus_dmamap_load_mbuf_sg(rbdr->rbdr_buff_dmat, dmap, mbuf, segs, &nsegs, BUS_DMA_NOWAIT); if (err != 0) { device_printf(nic->dev, "Failed to map mbuf into DMA visible memory, err: %d\n", err); m_freem(mbuf); bus_dmamap_destroy(rbdr->rbdr_buff_dmat, dmap); return (err); } if (nsegs != 1) panic("Unexpected number of DMA segments for RB: %d", nsegs); /* * Now use the room for rbuf_info structure * and adjust mbuf data and length. */ rinfo = (struct rbuf_info *)mbuf->m_data; m_adj(mbuf, NICVF_RCV_BUF_ALIGN_BYTES); rinfo->dmat = rbdr->rbdr_buff_dmat; rinfo->dmap = dmap; rinfo->mbuf = mbuf; *rbuf = segs[0].ds_addr + NICVF_RCV_BUF_ALIGN_BYTES; return (0); } /* Retrieve mbuf for received packet */ static struct mbuf * nicvf_rb_ptr_to_mbuf(struct nicvf *nic, bus_addr_t rb_ptr) { struct mbuf *mbuf; struct rbuf_info *rinfo; /* Get buffer start address and alignment offset */ rinfo = GET_RBUF_INFO(PHYS_TO_DMAP(rb_ptr)); /* Now retrieve mbuf to give to stack */ mbuf = rinfo->mbuf; if (__predict_false(mbuf == NULL)) { panic("%s: Received packet fragment with NULL mbuf", device_get_nameunit(nic->dev)); } /* * Clear the mbuf in the descriptor to indicate * that this slot is processed and free to use. */ rinfo->mbuf = NULL; bus_dmamap_sync(rinfo->dmat, rinfo->dmap, BUS_DMASYNC_POSTREAD); bus_dmamap_unload(rinfo->dmat, rinfo->dmap); return (mbuf); } /* Allocate RBDR ring and populate receive buffers */ static int nicvf_init_rbdr(struct nicvf *nic, struct rbdr *rbdr, int ring_len, int buf_size, int qidx) { bus_dmamap_t dmap; bus_addr_t rbuf; struct rbdr_entry_t *desc; int idx; int err; /* Allocate rbdr descriptors ring */ err = nicvf_alloc_q_desc_mem(nic, &rbdr->dmem, ring_len, sizeof(struct rbdr_entry_t), NICVF_RCV_BUF_ALIGN_BYTES); if (err != 0) { device_printf(nic->dev, "Failed to create RBDR descriptors ring\n"); return (err); } rbdr->desc = rbdr->dmem.base; /* * Buffer size has to be in multiples of 128 bytes. * Make room for metadata of size of one line (128 bytes). */ rbdr->dma_size = buf_size - NICVF_RCV_BUF_ALIGN_BYTES; rbdr->enable = TRUE; rbdr->thresh = RBDR_THRESH; rbdr->nic = nic; rbdr->idx = qidx; /* * Create DMA tag for Rx buffers. * Each map created using this tag is intended to store Rx payload for * one fragment and one header structure containing rbuf_info (thus * additional 128 byte line since RB must be a multiple of 128 byte * cache line). */ if (buf_size > MCLBYTES) { device_printf(nic->dev, "Buffer size to large for mbuf cluster\n"); return (EINVAL); } err = bus_dma_tag_create( bus_get_dma_tag(nic->dev), /* parent tag */ NICVF_RCV_BUF_ALIGN_BYTES, /* alignment */ 0, /* boundary */ DMAP_MAX_PHYSADDR, /* lowaddr */ DMAP_MIN_PHYSADDR, /* highaddr */ NULL, NULL, /* filtfunc, filtfuncarg */ roundup2(buf_size, MCLBYTES), /* maxsize */ 1, /* nsegments */ roundup2(buf_size, MCLBYTES), /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockfuncarg */ &rbdr->rbdr_buff_dmat); /* dmat */ if (err != 0) { device_printf(nic->dev, "Failed to create busdma tag for RBDR buffers\n"); return (err); } rbdr->rbdr_buff_dmaps = malloc(sizeof(*rbdr->rbdr_buff_dmaps) * ring_len, M_NICVF, (M_WAITOK | M_ZERO)); for (idx = 0; idx < ring_len; idx++) { err = bus_dmamap_create(rbdr->rbdr_buff_dmat, 0, &dmap); if (err != 0) { device_printf(nic->dev, "Failed to create DMA map for RB\n"); return (err); } rbdr->rbdr_buff_dmaps[idx] = dmap; err = nicvf_alloc_rcv_buffer(nic, rbdr, dmap, M_WAITOK, DMA_BUFFER_LEN, &rbuf); if (err != 0) return (err); desc = GET_RBDR_DESC(rbdr, idx); desc->buf_addr = (rbuf >> NICVF_RCV_BUF_ALIGN); } /* Allocate taskqueue */ TASK_INIT(&rbdr->rbdr_task, 0, nicvf_rbdr_task, rbdr); TASK_INIT(&rbdr->rbdr_task_nowait, 0, nicvf_rbdr_task_nowait, rbdr); rbdr->rbdr_taskq = taskqueue_create_fast("nicvf_rbdr_taskq", M_WAITOK, taskqueue_thread_enqueue, &rbdr->rbdr_taskq); taskqueue_start_threads(&rbdr->rbdr_taskq, 1, PI_NET, "%s: rbdr_taskq", device_get_nameunit(nic->dev)); return (0); } /* Free RBDR ring and its receive buffers */ static void nicvf_free_rbdr(struct nicvf *nic, struct rbdr *rbdr) { struct mbuf *mbuf; struct queue_set *qs; struct rbdr_entry_t *desc; struct rbuf_info *rinfo; bus_addr_t buf_addr; int head, tail, idx; int err; qs = nic->qs; if ((qs == NULL) || (rbdr == NULL)) return; rbdr->enable = FALSE; if (rbdr->rbdr_taskq != NULL) { /* Remove tasks */ while (taskqueue_cancel(rbdr->rbdr_taskq, &rbdr->rbdr_task_nowait, NULL) != 0) { /* Finish the nowait task first */ taskqueue_drain(rbdr->rbdr_taskq, &rbdr->rbdr_task_nowait); } taskqueue_free(rbdr->rbdr_taskq); rbdr->rbdr_taskq = NULL; while (taskqueue_cancel(taskqueue_thread, &rbdr->rbdr_task, NULL) != 0) { /* Now finish the sleepable task */ taskqueue_drain(taskqueue_thread, &rbdr->rbdr_task); } } /* * Free all of the memory under the RB descriptors. * There are assumptions here: * 1. Corresponding RBDR is disabled * - it is safe to operate using head and tail indexes * 2. All bffers that were received are properly freed by * the receive handler * - there is no need to unload DMA map and free MBUF for other * descriptors than unused ones */ if (rbdr->rbdr_buff_dmat != NULL) { head = rbdr->head; tail = rbdr->tail; while (head != tail) { desc = GET_RBDR_DESC(rbdr, head); buf_addr = desc->buf_addr << NICVF_RCV_BUF_ALIGN; rinfo = GET_RBUF_INFO(PHYS_TO_DMAP(buf_addr)); bus_dmamap_unload(rbdr->rbdr_buff_dmat, rinfo->dmap); mbuf = rinfo->mbuf; /* This will destroy everything including rinfo! */ m_freem(mbuf); head++; head &= (rbdr->dmem.q_len - 1); } /* Free tail descriptor */ desc = GET_RBDR_DESC(rbdr, tail); buf_addr = desc->buf_addr << NICVF_RCV_BUF_ALIGN; rinfo = GET_RBUF_INFO(PHYS_TO_DMAP(buf_addr)); bus_dmamap_unload(rbdr->rbdr_buff_dmat, rinfo->dmap); mbuf = rinfo->mbuf; /* This will destroy everything including rinfo! */ m_freem(mbuf); /* Destroy DMA maps */ for (idx = 0; idx < qs->rbdr_len; idx++) { if (rbdr->rbdr_buff_dmaps[idx] == NULL) continue; err = bus_dmamap_destroy(rbdr->rbdr_buff_dmat, rbdr->rbdr_buff_dmaps[idx]); KASSERT(err == 0, ("%s: Could not destroy DMA map for RB, desc: %d", __func__, idx)); rbdr->rbdr_buff_dmaps[idx] = NULL; } /* Now destroy the tag */ err = bus_dma_tag_destroy(rbdr->rbdr_buff_dmat); KASSERT(err == 0, ("%s: Trying to destroy BUSY DMA tag", __func__)); rbdr->head = 0; rbdr->tail = 0; } /* Free RBDR ring */ nicvf_free_q_desc_mem(nic, &rbdr->dmem); } /* * Refill receive buffer descriptors with new buffers. */ static int nicvf_refill_rbdr(struct rbdr *rbdr, int mflags) { struct nicvf *nic; struct queue_set *qs; int rbdr_idx; int tail, qcount; int refill_rb_cnt; struct rbdr_entry_t *desc; bus_dmamap_t dmap; bus_addr_t rbuf; boolean_t rb_alloc_fail; int new_rb; rb_alloc_fail = TRUE; new_rb = 0; nic = rbdr->nic; qs = nic->qs; rbdr_idx = rbdr->idx; /* Check if it's enabled */ if (!rbdr->enable) return (0); /* Get no of desc's to be refilled */ qcount = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_STATUS0, rbdr_idx); qcount &= 0x7FFFF; /* Doorbell can be ringed with a max of ring size minus 1 */ if (qcount >= (qs->rbdr_len - 1)) { rb_alloc_fail = FALSE; goto out; } else refill_rb_cnt = qs->rbdr_len - qcount - 1; /* Start filling descs from tail */ tail = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_TAIL, rbdr_idx) >> 3; while (refill_rb_cnt) { tail++; tail &= (rbdr->dmem.q_len - 1); dmap = rbdr->rbdr_buff_dmaps[tail]; if (nicvf_alloc_rcv_buffer(nic, rbdr, dmap, mflags, DMA_BUFFER_LEN, &rbuf)) { /* Something went wrong. Resign */ break; } desc = GET_RBDR_DESC(rbdr, tail); desc->buf_addr = (rbuf >> NICVF_RCV_BUF_ALIGN); refill_rb_cnt--; new_rb++; } /* make sure all memory stores are done before ringing doorbell */ wmb(); /* Check if buffer allocation failed */ if (refill_rb_cnt == 0) rb_alloc_fail = FALSE; /* Notify HW */ nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_DOOR, rbdr_idx, new_rb); out: if (!rb_alloc_fail) { /* * Re-enable RBDR interrupts only * if buffer allocation is success. */ nicvf_enable_intr(nic, NICVF_INTR_RBDR, rbdr_idx); return (0); } return (ENOMEM); } /* Refill RBs even if sleep is needed to reclaim memory */ static void nicvf_rbdr_task(void *arg, int pending) { struct rbdr *rbdr; int err; rbdr = (struct rbdr *)arg; err = nicvf_refill_rbdr(rbdr, M_WAITOK); if (__predict_false(err != 0)) { panic("%s: Failed to refill RBs even when sleep enabled", __func__); } } /* Refill RBs as soon as possible without waiting */ static void nicvf_rbdr_task_nowait(void *arg, int pending) { struct rbdr *rbdr; int err; rbdr = (struct rbdr *)arg; err = nicvf_refill_rbdr(rbdr, M_NOWAIT); if (err != 0) { /* * Schedule another, sleepable kernel thread * that will for sure refill the buffers. */ taskqueue_enqueue(taskqueue_thread, &rbdr->rbdr_task); } } static int nicvf_rcv_pkt_handler(struct nicvf *nic, struct cmp_queue *cq, struct cqe_rx_t *cqe_rx, int cqe_type) { struct mbuf *mbuf; struct rcv_queue *rq; int rq_idx; int err = 0; rq_idx = cqe_rx->rq_idx; rq = &nic->qs->rq[rq_idx]; /* Check for errors */ err = nicvf_check_cqe_rx_errs(nic, cq, cqe_rx); if (err && !cqe_rx->rb_cnt) return (0); mbuf = nicvf_get_rcv_mbuf(nic, cqe_rx); if (mbuf == NULL) { dprintf(nic->dev, "Packet not received\n"); return (0); } /* If error packet */ if (err != 0) { m_freem(mbuf); return (0); } if (rq->lro_enabled && ((cqe_rx->l3_type == L3TYPE_IPV4) && (cqe_rx->l4_type == L4TYPE_TCP)) && (mbuf->m_pkthdr.csum_flags & (CSUM_DATA_VALID | CSUM_PSEUDO_HDR)) == (CSUM_DATA_VALID | CSUM_PSEUDO_HDR)) { /* * At this point it is known that there are no errors in the * packet. Attempt to LRO enqueue. Send to stack if no resources * or enqueue error. */ if ((rq->lro.lro_cnt != 0) && (tcp_lro_rx(&rq->lro, mbuf, 0) == 0)) return (0); } /* * Push this packet to the stack later to avoid * unlocking completion task in the middle of work. */ err = buf_ring_enqueue(cq->rx_br, mbuf); if (err != 0) { /* * Failed to enqueue this mbuf. * We don't drop it, just schedule another task. */ return (err); } return (0); } static int nicvf_snd_pkt_handler(struct nicvf *nic, struct cmp_queue *cq, struct cqe_send_t *cqe_tx, int cqe_type) { bus_dmamap_t dmap; struct mbuf *mbuf; struct snd_queue *sq; struct sq_hdr_subdesc *hdr; mbuf = NULL; sq = &nic->qs->sq[cqe_tx->sq_idx]; /* Avoid blocking here since we hold a non-sleepable NICVF_CMP_LOCK */ if (NICVF_TX_TRYLOCK(sq) == 0) return (EAGAIN); hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, cqe_tx->sqe_ptr); if (hdr->subdesc_type != SQ_DESC_TYPE_HEADER) { NICVF_TX_UNLOCK(sq); return (0); } dprintf(nic->dev, "%s Qset #%d SQ #%d SQ ptr #%d subdesc count %d\n", __func__, cqe_tx->sq_qs, cqe_tx->sq_idx, cqe_tx->sqe_ptr, hdr->subdesc_cnt); dmap = (bus_dmamap_t)sq->snd_buff[cqe_tx->sqe_ptr].dmap; bus_dmamap_unload(sq->snd_buff_dmat, dmap); mbuf = (struct mbuf *)sq->snd_buff[cqe_tx->sqe_ptr].mbuf; if (mbuf != NULL) { m_freem(mbuf); sq->snd_buff[cqe_tx->sqe_ptr].mbuf = NULL; nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1); } nicvf_check_cqe_tx_errs(nic, cq, cqe_tx); NICVF_TX_UNLOCK(sq); return (0); } static int nicvf_cq_intr_handler(struct nicvf *nic, uint8_t cq_idx) { struct mbuf *mbuf; struct ifnet *ifp; int processed_cqe, work_done = 0, tx_done = 0; int cqe_count, cqe_head; struct queue_set *qs = nic->qs; struct cmp_queue *cq = &qs->cq[cq_idx]; struct snd_queue *sq = &qs->sq[cq_idx]; struct rcv_queue *rq; struct cqe_rx_t *cq_desc; struct lro_ctrl *lro; int rq_idx; int cmp_err; NICVF_CMP_LOCK(cq); cmp_err = 0; processed_cqe = 0; /* Get no of valid CQ entries to process */ cqe_count = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS, cq_idx); cqe_count &= CQ_CQE_COUNT; if (cqe_count == 0) goto out; /* Get head of the valid CQ entries */ cqe_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD, cq_idx) >> 9; cqe_head &= 0xFFFF; dprintf(nic->dev, "%s CQ%d cqe_count %d cqe_head %d\n", __func__, cq_idx, cqe_count, cqe_head); while (processed_cqe < cqe_count) { /* Get the CQ descriptor */ cq_desc = (struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head); cqe_head++; cqe_head &= (cq->dmem.q_len - 1); /* Prefetch next CQ descriptor */ __builtin_prefetch((struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head)); dprintf(nic->dev, "CQ%d cq_desc->cqe_type %d\n", cq_idx, cq_desc->cqe_type); switch (cq_desc->cqe_type) { case CQE_TYPE_RX: cmp_err = nicvf_rcv_pkt_handler(nic, cq, cq_desc, CQE_TYPE_RX); if (__predict_false(cmp_err != 0)) { /* * Ups. Cannot finish now. * Let's try again later. */ goto done; } work_done++; break; case CQE_TYPE_SEND: cmp_err = nicvf_snd_pkt_handler(nic, cq, (void *)cq_desc, CQE_TYPE_SEND); if (__predict_false(cmp_err != 0)) { /* * Ups. Cannot finish now. * Let's try again later. */ goto done; } tx_done++; break; case CQE_TYPE_INVALID: case CQE_TYPE_RX_SPLIT: case CQE_TYPE_RX_TCP: case CQE_TYPE_SEND_PTP: /* Ignore for now */ break; } processed_cqe++; } done: dprintf(nic->dev, "%s CQ%d processed_cqe %d work_done %d\n", __func__, cq_idx, processed_cqe, work_done); /* Ring doorbell to inform H/W to reuse processed CQEs */ nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_DOOR, cq_idx, processed_cqe); if ((tx_done > 0) && ((if_getdrvflags(nic->ifp) & IFF_DRV_RUNNING) != 0)) { /* Reenable TXQ if its stopped earlier due to SQ full */ if_setdrvflagbits(nic->ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); taskqueue_enqueue(sq->snd_taskq, &sq->snd_task); } out: /* * Flush any outstanding LRO work */ rq_idx = cq_idx; rq = &nic->qs->rq[rq_idx]; lro = &rq->lro; tcp_lro_flush_all(lro); NICVF_CMP_UNLOCK(cq); ifp = nic->ifp; /* Push received MBUFs to the stack */ while (!buf_ring_empty(cq->rx_br)) { mbuf = buf_ring_dequeue_mc(cq->rx_br); if (__predict_true(mbuf != NULL)) (*ifp->if_input)(ifp, mbuf); } return (cmp_err); } /* * Qset error interrupt handler * * As of now only CQ errors are handled */ static void nicvf_qs_err_task(void *arg, int pending) { struct nicvf *nic; struct queue_set *qs; int qidx; uint64_t status; boolean_t enable = TRUE; nic = (struct nicvf *)arg; qs = nic->qs; /* Deactivate network interface */ if_setdrvflagbits(nic->ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); /* Check if it is CQ err */ for (qidx = 0; qidx < qs->cq_cnt; qidx++) { status = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS, qidx); if ((status & CQ_ERR_MASK) == 0) continue; /* Process already queued CQEs and reconfig CQ */ nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx); nicvf_sq_disable(nic, qidx); (void)nicvf_cq_intr_handler(nic, qidx); nicvf_cmp_queue_config(nic, qs, qidx, enable); nicvf_sq_free_used_descs(nic, &qs->sq[qidx], qidx); nicvf_sq_enable(nic, &qs->sq[qidx], qidx); nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx); } if_setdrvflagbits(nic->ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); /* Re-enable Qset error interrupt */ nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0); } static void nicvf_cmp_task(void *arg, int pending) { struct cmp_queue *cq; struct nicvf *nic; int cmp_err; cq = (struct cmp_queue *)arg; nic = cq->nic; /* Handle CQ descriptors */ cmp_err = nicvf_cq_intr_handler(nic, cq->idx); if (__predict_false(cmp_err != 0)) { /* * Schedule another thread here since we did not * process the entire CQ due to Tx or Rx CQ parse error. */ taskqueue_enqueue(cq->cmp_taskq, &cq->cmp_task); } nicvf_clear_intr(nic, NICVF_INTR_CQ, cq->idx); /* Reenable interrupt (previously disabled in nicvf_intr_handler() */ nicvf_enable_intr(nic, NICVF_INTR_CQ, cq->idx); } /* Initialize completion queue */ static int nicvf_init_cmp_queue(struct nicvf *nic, struct cmp_queue *cq, int q_len, int qidx) { int err; /* Initizalize lock */ snprintf(cq->mtx_name, sizeof(cq->mtx_name), "%s: CQ(%d) lock", device_get_nameunit(nic->dev), qidx); mtx_init(&cq->mtx, cq->mtx_name, NULL, MTX_DEF); err = nicvf_alloc_q_desc_mem(nic, &cq->dmem, q_len, CMP_QUEUE_DESC_SIZE, NICVF_CQ_BASE_ALIGN_BYTES); if (err != 0) { device_printf(nic->dev, "Could not allocate DMA memory for CQ\n"); return (err); } cq->desc = cq->dmem.base; cq->thresh = pass1_silicon(nic->dev) ? 0 : CMP_QUEUE_CQE_THRESH; cq->nic = nic; cq->idx = qidx; nic->cq_coalesce_usecs = (CMP_QUEUE_TIMER_THRESH * 0.05) - 1; cq->rx_br = buf_ring_alloc(CMP_QUEUE_LEN * 8, M_DEVBUF, M_WAITOK, &cq->mtx); /* Allocate taskqueue */ TASK_INIT(&cq->cmp_task, 0, nicvf_cmp_task, cq); cq->cmp_taskq = taskqueue_create_fast("nicvf_cmp_taskq", M_WAITOK, taskqueue_thread_enqueue, &cq->cmp_taskq); taskqueue_start_threads(&cq->cmp_taskq, 1, PI_NET, "%s: cmp_taskq(%d)", device_get_nameunit(nic->dev), qidx); return (0); } static void nicvf_free_cmp_queue(struct nicvf *nic, struct cmp_queue *cq) { if (cq == NULL) return; /* * The completion queue itself should be disabled by now * (ref. nicvf_snd_queue_config()). * Ensure that it is safe to disable it or panic. */ if (cq->enable) panic("%s: Trying to free working CQ(%d)", __func__, cq->idx); if (cq->cmp_taskq != NULL) { /* Remove task */ while (taskqueue_cancel(cq->cmp_taskq, &cq->cmp_task, NULL) != 0) taskqueue_drain(cq->cmp_taskq, &cq->cmp_task); taskqueue_free(cq->cmp_taskq); cq->cmp_taskq = NULL; } /* * Completion interrupt will possibly enable interrupts again * so disable interrupting now after we finished processing * completion task. It is safe to do so since the corresponding CQ * was already disabled. */ nicvf_disable_intr(nic, NICVF_INTR_CQ, cq->idx); nicvf_clear_intr(nic, NICVF_INTR_CQ, cq->idx); NICVF_CMP_LOCK(cq); nicvf_free_q_desc_mem(nic, &cq->dmem); drbr_free(cq->rx_br, M_DEVBUF); NICVF_CMP_UNLOCK(cq); mtx_destroy(&cq->mtx); memset(cq->mtx_name, 0, sizeof(cq->mtx_name)); } int nicvf_xmit_locked(struct snd_queue *sq) { struct nicvf *nic; struct ifnet *ifp; struct mbuf *next; int err; NICVF_TX_LOCK_ASSERT(sq); nic = sq->nic; ifp = nic->ifp; err = 0; while ((next = drbr_peek(ifp, sq->br)) != NULL) { err = nicvf_tx_mbuf_locked(sq, &next); if (err != 0) { if (next == NULL) drbr_advance(ifp, sq->br); else drbr_putback(ifp, sq->br, next); break; } drbr_advance(ifp, sq->br); /* Send a copy of the frame to the BPF listener */ ETHER_BPF_MTAP(ifp, next); } return (err); } static void nicvf_snd_task(void *arg, int pending) { struct snd_queue *sq = (struct snd_queue *)arg; struct nicvf *nic; struct ifnet *ifp; int err; nic = sq->nic; ifp = nic->ifp; /* * Skip sending anything if the driver is not running, * SQ full or link is down. */ if (((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING) || !nic->link_up) return; NICVF_TX_LOCK(sq); err = nicvf_xmit_locked(sq); NICVF_TX_UNLOCK(sq); /* Try again */ if (err != 0) taskqueue_enqueue(sq->snd_taskq, &sq->snd_task); } /* Initialize transmit queue */ static int nicvf_init_snd_queue(struct nicvf *nic, struct snd_queue *sq, int q_len, int qidx) { size_t i; int err; /* Initizalize TX lock for this queue */ snprintf(sq->mtx_name, sizeof(sq->mtx_name), "%s: SQ(%d) lock", device_get_nameunit(nic->dev), qidx); mtx_init(&sq->mtx, sq->mtx_name, NULL, MTX_DEF); NICVF_TX_LOCK(sq); /* Allocate buffer ring */ sq->br = buf_ring_alloc(q_len / MIN_SQ_DESC_PER_PKT_XMIT, M_DEVBUF, M_NOWAIT, &sq->mtx); if (sq->br == NULL) { device_printf(nic->dev, "ERROR: Could not set up buf ring for SQ(%d)\n", qidx); err = ENOMEM; goto error; } /* Allocate DMA memory for Tx descriptors */ err = nicvf_alloc_q_desc_mem(nic, &sq->dmem, q_len, SND_QUEUE_DESC_SIZE, NICVF_SQ_BASE_ALIGN_BYTES); if (err != 0) { device_printf(nic->dev, "Could not allocate DMA memory for SQ\n"); goto error; } sq->desc = sq->dmem.base; sq->head = sq->tail = 0; sq->free_cnt = q_len - 1; sq->thresh = SND_QUEUE_THRESH; sq->idx = qidx; sq->nic = nic; /* * Allocate DMA maps for Tx buffers */ /* Create DMA tag first */ err = bus_dma_tag_create( bus_get_dma_tag(nic->dev), /* parent tag */ 1, /* alignment */ 0, /* boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filtfunc, filtfuncarg */ NICVF_TSO_MAXSIZE, /* maxsize */ NICVF_TSO_NSEGS, /* nsegments */ MCLBYTES, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockfuncarg */ &sq->snd_buff_dmat); /* dmat */ if (err != 0) { device_printf(nic->dev, "Failed to create busdma tag for Tx buffers\n"); goto error; } /* Allocate send buffers array */ sq->snd_buff = malloc(sizeof(*sq->snd_buff) * q_len, M_NICVF, (M_NOWAIT | M_ZERO)); if (sq->snd_buff == NULL) { device_printf(nic->dev, "Could not allocate memory for Tx buffers array\n"); err = ENOMEM; goto error; } /* Now populate maps */ for (i = 0; i < q_len; i++) { err = bus_dmamap_create(sq->snd_buff_dmat, 0, &sq->snd_buff[i].dmap); if (err != 0) { device_printf(nic->dev, "Failed to create DMA maps for Tx buffers\n"); goto error; } } NICVF_TX_UNLOCK(sq); /* Allocate taskqueue */ TASK_INIT(&sq->snd_task, 0, nicvf_snd_task, sq); sq->snd_taskq = taskqueue_create_fast("nicvf_snd_taskq", M_WAITOK, taskqueue_thread_enqueue, &sq->snd_taskq); taskqueue_start_threads(&sq->snd_taskq, 1, PI_NET, "%s: snd_taskq(%d)", device_get_nameunit(nic->dev), qidx); return (0); error: NICVF_TX_UNLOCK(sq); return (err); } static void nicvf_free_snd_queue(struct nicvf *nic, struct snd_queue *sq) { struct queue_set *qs = nic->qs; size_t i; int err; if (sq == NULL) return; if (sq->snd_taskq != NULL) { /* Remove task */ while (taskqueue_cancel(sq->snd_taskq, &sq->snd_task, NULL) != 0) taskqueue_drain(sq->snd_taskq, &sq->snd_task); taskqueue_free(sq->snd_taskq); sq->snd_taskq = NULL; } NICVF_TX_LOCK(sq); if (sq->snd_buff_dmat != NULL) { if (sq->snd_buff != NULL) { for (i = 0; i < qs->sq_len; i++) { m_freem(sq->snd_buff[i].mbuf); sq->snd_buff[i].mbuf = NULL; bus_dmamap_unload(sq->snd_buff_dmat, sq->snd_buff[i].dmap); err = bus_dmamap_destroy(sq->snd_buff_dmat, sq->snd_buff[i].dmap); /* * If bus_dmamap_destroy fails it can cause * random panic later if the tag is also * destroyed in the process. */ KASSERT(err == 0, ("%s: Could not destroy DMA map for SQ", __func__)); } } free(sq->snd_buff, M_NICVF); err = bus_dma_tag_destroy(sq->snd_buff_dmat); KASSERT(err == 0, ("%s: Trying to destroy BUSY DMA tag", __func__)); } /* Free private driver ring for this send queue */ if (sq->br != NULL) drbr_free(sq->br, M_DEVBUF); if (sq->dmem.base != NULL) nicvf_free_q_desc_mem(nic, &sq->dmem); NICVF_TX_UNLOCK(sq); /* Destroy Tx lock */ mtx_destroy(&sq->mtx); memset(sq->mtx_name, 0, sizeof(sq->mtx_name)); } static void nicvf_reclaim_snd_queue(struct nicvf *nic, struct queue_set *qs, int qidx) { /* Disable send queue */ nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, 0); /* Check if SQ is stopped */ if (nicvf_poll_reg(nic, qidx, NIC_QSET_SQ_0_7_STATUS, 21, 1, 0x01)) return; /* Reset send queue */ nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, NICVF_SQ_RESET); } static void nicvf_reclaim_rcv_queue(struct nicvf *nic, struct queue_set *qs, int qidx) { union nic_mbx mbx = {}; /* Make sure all packets in the pipeline are written back into mem */ mbx.msg.msg = NIC_MBOX_MSG_RQ_SW_SYNC; nicvf_send_msg_to_pf(nic, &mbx); } static void nicvf_reclaim_cmp_queue(struct nicvf *nic, struct queue_set *qs, int qidx) { /* Disable timer threshold (doesn't get reset upon CQ reset */ nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG2, qidx, 0); /* Disable completion queue */ nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, 0); /* Reset completion queue */ nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, NICVF_CQ_RESET); } static void nicvf_reclaim_rbdr(struct nicvf *nic, struct rbdr *rbdr, int qidx) { uint64_t tmp, fifo_state; int timeout = 10; /* Save head and tail pointers for feeing up buffers */ rbdr->head = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_HEAD, qidx) >> 3; rbdr->tail = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_TAIL, qidx) >> 3; /* * If RBDR FIFO is in 'FAIL' state then do a reset first * before relaiming. */ fifo_state = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_STATUS0, qidx); if (((fifo_state >> 62) & 0x03) == 0x3) { nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx, NICVF_RBDR_RESET); } /* Disable RBDR */ nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx, 0); if (nicvf_poll_reg(nic, qidx, NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x00)) return; while (1) { tmp = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_PREFETCH_STATUS, qidx); if ((tmp & 0xFFFFFFFF) == ((tmp >> 32) & 0xFFFFFFFF)) break; DELAY(1000); timeout--; if (!timeout) { device_printf(nic->dev, "Failed polling on prefetch status\n"); return; } } nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx, NICVF_RBDR_RESET); if (nicvf_poll_reg(nic, qidx, NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x02)) return; nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx, 0x00); if (nicvf_poll_reg(nic, qidx, NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x00)) return; } /* Configures receive queue */ static void nicvf_rcv_queue_config(struct nicvf *nic, struct queue_set *qs, int qidx, bool enable) { union nic_mbx mbx = {}; struct rcv_queue *rq; struct rq_cfg rq_cfg; struct ifnet *ifp; struct lro_ctrl *lro; ifp = nic->ifp; rq = &qs->rq[qidx]; rq->enable = enable; lro = &rq->lro; /* Disable receive queue */ nicvf_queue_reg_write(nic, NIC_QSET_RQ_0_7_CFG, qidx, 0); if (!rq->enable) { nicvf_reclaim_rcv_queue(nic, qs, qidx); /* Free LRO memory */ tcp_lro_free(lro); rq->lro_enabled = FALSE; return; } /* Configure LRO if enabled */ rq->lro_enabled = FALSE; if ((if_getcapenable(ifp) & IFCAP_LRO) != 0) { if (tcp_lro_init(lro) != 0) { device_printf(nic->dev, "Failed to initialize LRO for RXQ%d\n", qidx); } else { rq->lro_enabled = TRUE; lro->ifp = nic->ifp; } } rq->cq_qs = qs->vnic_id; rq->cq_idx = qidx; rq->start_rbdr_qs = qs->vnic_id; rq->start_qs_rbdr_idx = qs->rbdr_cnt - 1; rq->cont_rbdr_qs = qs->vnic_id; rq->cont_qs_rbdr_idx = qs->rbdr_cnt - 1; /* all writes of RBDR data to be loaded into L2 Cache as well*/ rq->caching = 1; /* Send a mailbox msg to PF to config RQ */ mbx.rq.msg = NIC_MBOX_MSG_RQ_CFG; mbx.rq.qs_num = qs->vnic_id; mbx.rq.rq_num = qidx; mbx.rq.cfg = (rq->caching << 26) | (rq->cq_qs << 19) | (rq->cq_idx << 16) | (rq->cont_rbdr_qs << 9) | (rq->cont_qs_rbdr_idx << 8) | (rq->start_rbdr_qs << 1) | (rq->start_qs_rbdr_idx); nicvf_send_msg_to_pf(nic, &mbx); mbx.rq.msg = NIC_MBOX_MSG_RQ_BP_CFG; mbx.rq.cfg = (1UL << 63) | (1UL << 62) | (qs->vnic_id << 0); nicvf_send_msg_to_pf(nic, &mbx); /* * RQ drop config * Enable CQ drop to reserve sufficient CQEs for all tx packets */ mbx.rq.msg = NIC_MBOX_MSG_RQ_DROP_CFG; mbx.rq.cfg = (1UL << 62) | (RQ_CQ_DROP << 8); nicvf_send_msg_to_pf(nic, &mbx); nicvf_queue_reg_write(nic, NIC_QSET_RQ_GEN_CFG, 0, 0x00); /* Enable Receive queue */ rq_cfg.ena = 1; rq_cfg.tcp_ena = 0; nicvf_queue_reg_write(nic, NIC_QSET_RQ_0_7_CFG, qidx, *(uint64_t *)&rq_cfg); } /* Configures completion queue */ static void nicvf_cmp_queue_config(struct nicvf *nic, struct queue_set *qs, int qidx, boolean_t enable) { struct cmp_queue *cq; struct cq_cfg cq_cfg; cq = &qs->cq[qidx]; cq->enable = enable; if (!cq->enable) { nicvf_reclaim_cmp_queue(nic, qs, qidx); return; } /* Reset completion queue */ nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, NICVF_CQ_RESET); /* Set completion queue base address */ nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_BASE, qidx, (uint64_t)(cq->dmem.phys_base)); /* Enable Completion queue */ cq_cfg.ena = 1; cq_cfg.reset = 0; cq_cfg.caching = 0; cq_cfg.qsize = CMP_QSIZE; cq_cfg.avg_con = 0; nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, *(uint64_t *)&cq_cfg); /* Set threshold value for interrupt generation */ nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_THRESH, qidx, cq->thresh); nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG2, qidx, nic->cq_coalesce_usecs); } /* Configures transmit queue */ static void nicvf_snd_queue_config(struct nicvf *nic, struct queue_set *qs, int qidx, boolean_t enable) { union nic_mbx mbx = {}; struct snd_queue *sq; struct sq_cfg sq_cfg; sq = &qs->sq[qidx]; sq->enable = enable; if (!sq->enable) { nicvf_reclaim_snd_queue(nic, qs, qidx); return; } /* Reset send queue */ nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, NICVF_SQ_RESET); sq->cq_qs = qs->vnic_id; sq->cq_idx = qidx; /* Send a mailbox msg to PF to config SQ */ mbx.sq.msg = NIC_MBOX_MSG_SQ_CFG; mbx.sq.qs_num = qs->vnic_id; mbx.sq.sq_num = qidx; mbx.sq.sqs_mode = nic->sqs_mode; mbx.sq.cfg = (sq->cq_qs << 3) | sq->cq_idx; nicvf_send_msg_to_pf(nic, &mbx); /* Set queue base address */ nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_BASE, qidx, (uint64_t)(sq->dmem.phys_base)); /* Enable send queue & set queue size */ sq_cfg.ena = 1; sq_cfg.reset = 0; sq_cfg.ldwb = 0; sq_cfg.qsize = SND_QSIZE; sq_cfg.tstmp_bgx_intf = 0; nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, *(uint64_t *)&sq_cfg); /* Set threshold value for interrupt generation */ nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_THRESH, qidx, sq->thresh); } /* Configures receive buffer descriptor ring */ static void nicvf_rbdr_config(struct nicvf *nic, struct queue_set *qs, int qidx, boolean_t enable) { struct rbdr *rbdr; struct rbdr_cfg rbdr_cfg; rbdr = &qs->rbdr[qidx]; nicvf_reclaim_rbdr(nic, rbdr, qidx); if (!enable) return; /* Set descriptor base address */ nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_BASE, qidx, (uint64_t)(rbdr->dmem.phys_base)); /* Enable RBDR & set queue size */ /* Buffer size should be in multiples of 128 bytes */ rbdr_cfg.ena = 1; rbdr_cfg.reset = 0; rbdr_cfg.ldwb = 0; rbdr_cfg.qsize = RBDR_SIZE; rbdr_cfg.avg_con = 0; rbdr_cfg.lines = rbdr->dma_size / 128; nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx, *(uint64_t *)&rbdr_cfg); /* Notify HW */ nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_DOOR, qidx, qs->rbdr_len - 1); /* Set threshold value for interrupt generation */ nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_THRESH, qidx, rbdr->thresh - 1); } /* Requests PF to assign and enable Qset */ void nicvf_qset_config(struct nicvf *nic, boolean_t enable) { union nic_mbx mbx = {}; struct queue_set *qs; struct qs_cfg *qs_cfg; qs = nic->qs; if (qs == NULL) { device_printf(nic->dev, "Qset is still not allocated, don't init queues\n"); return; } qs->enable = enable; qs->vnic_id = nic->vf_id; /* Send a mailbox msg to PF to config Qset */ mbx.qs.msg = NIC_MBOX_MSG_QS_CFG; mbx.qs.num = qs->vnic_id; mbx.qs.cfg = 0; qs_cfg = (struct qs_cfg *)&mbx.qs.cfg; if (qs->enable) { qs_cfg->ena = 1; qs_cfg->vnic = qs->vnic_id; } nicvf_send_msg_to_pf(nic, &mbx); } static void nicvf_free_resources(struct nicvf *nic) { int qidx; struct queue_set *qs; qs = nic->qs; /* * Remove QS error task first since it has to be dead * to safely free completion queue tasks. */ if (qs->qs_err_taskq != NULL) { /* Shut down QS error tasks */ while (taskqueue_cancel(qs->qs_err_taskq, &qs->qs_err_task, NULL) != 0) { taskqueue_drain(qs->qs_err_taskq, &qs->qs_err_task); } taskqueue_free(qs->qs_err_taskq); qs->qs_err_taskq = NULL; } /* Free receive buffer descriptor ring */ for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) nicvf_free_rbdr(nic, &qs->rbdr[qidx]); /* Free completion queue */ for (qidx = 0; qidx < qs->cq_cnt; qidx++) nicvf_free_cmp_queue(nic, &qs->cq[qidx]); /* Free send queue */ for (qidx = 0; qidx < qs->sq_cnt; qidx++) nicvf_free_snd_queue(nic, &qs->sq[qidx]); } static int nicvf_alloc_resources(struct nicvf *nic) { struct queue_set *qs = nic->qs; int qidx; /* Alloc receive buffer descriptor ring */ for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) { if (nicvf_init_rbdr(nic, &qs->rbdr[qidx], qs->rbdr_len, DMA_BUFFER_LEN, qidx)) goto alloc_fail; } /* Alloc send queue */ for (qidx = 0; qidx < qs->sq_cnt; qidx++) { if (nicvf_init_snd_queue(nic, &qs->sq[qidx], qs->sq_len, qidx)) goto alloc_fail; } /* Alloc completion queue */ for (qidx = 0; qidx < qs->cq_cnt; qidx++) { if (nicvf_init_cmp_queue(nic, &qs->cq[qidx], qs->cq_len, qidx)) goto alloc_fail; } /* Allocate QS error taskqueue */ TASK_INIT(&qs->qs_err_task, 0, nicvf_qs_err_task, nic); qs->qs_err_taskq = taskqueue_create_fast("nicvf_qs_err_taskq", M_WAITOK, taskqueue_thread_enqueue, &qs->qs_err_taskq); taskqueue_start_threads(&qs->qs_err_taskq, 1, PI_NET, "%s: qs_taskq", device_get_nameunit(nic->dev)); return (0); alloc_fail: nicvf_free_resources(nic); return (ENOMEM); } int nicvf_set_qset_resources(struct nicvf *nic) { struct queue_set *qs; qs = malloc(sizeof(*qs), M_NICVF, (M_ZERO | M_WAITOK)); nic->qs = qs; /* Set count of each queue */ qs->rbdr_cnt = RBDR_CNT; - /* With no RSS we stay with single RQ */ - qs->rq_cnt = 1; + qs->rq_cnt = RCV_QUEUE_CNT; qs->sq_cnt = SND_QUEUE_CNT; qs->cq_cnt = CMP_QUEUE_CNT; /* Set queue lengths */ qs->rbdr_len = RCV_BUF_COUNT; qs->sq_len = SND_QUEUE_LEN; qs->cq_len = CMP_QUEUE_LEN; nic->rx_queues = qs->rq_cnt; nic->tx_queues = qs->sq_cnt; return (0); } int nicvf_config_data_transfer(struct nicvf *nic, boolean_t enable) { boolean_t disable = FALSE; struct queue_set *qs; int qidx; qs = nic->qs; if (qs == NULL) return (0); if (enable) { if (nicvf_alloc_resources(nic) != 0) return (ENOMEM); for (qidx = 0; qidx < qs->sq_cnt; qidx++) nicvf_snd_queue_config(nic, qs, qidx, enable); for (qidx = 0; qidx < qs->cq_cnt; qidx++) nicvf_cmp_queue_config(nic, qs, qidx, enable); for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) nicvf_rbdr_config(nic, qs, qidx, enable); for (qidx = 0; qidx < qs->rq_cnt; qidx++) nicvf_rcv_queue_config(nic, qs, qidx, enable); } else { for (qidx = 0; qidx < qs->rq_cnt; qidx++) nicvf_rcv_queue_config(nic, qs, qidx, disable); for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) nicvf_rbdr_config(nic, qs, qidx, disable); for (qidx = 0; qidx < qs->sq_cnt; qidx++) nicvf_snd_queue_config(nic, qs, qidx, disable); for (qidx = 0; qidx < qs->cq_cnt; qidx++) nicvf_cmp_queue_config(nic, qs, qidx, disable); nicvf_free_resources(nic); } return (0); } /* * Get a free desc from SQ * returns descriptor ponter & descriptor number */ static __inline int nicvf_get_sq_desc(struct snd_queue *sq, int desc_cnt) { int qentry; qentry = sq->tail; sq->free_cnt -= desc_cnt; sq->tail += desc_cnt; sq->tail &= (sq->dmem.q_len - 1); return (qentry); } /* Free descriptor back to SQ for future use */ static void nicvf_put_sq_desc(struct snd_queue *sq, int desc_cnt) { sq->free_cnt += desc_cnt; sq->head += desc_cnt; sq->head &= (sq->dmem.q_len - 1); } static __inline int nicvf_get_nxt_sqentry(struct snd_queue *sq, int qentry) { qentry++; qentry &= (sq->dmem.q_len - 1); return (qentry); } static void nicvf_sq_enable(struct nicvf *nic, struct snd_queue *sq, int qidx) { uint64_t sq_cfg; sq_cfg = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_CFG, qidx); sq_cfg |= NICVF_SQ_EN; nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, sq_cfg); /* Ring doorbell so that H/W restarts processing SQEs */ nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_DOOR, qidx, 0); } static void nicvf_sq_disable(struct nicvf *nic, int qidx) { uint64_t sq_cfg; sq_cfg = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_CFG, qidx); sq_cfg &= ~NICVF_SQ_EN; nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, sq_cfg); } static void nicvf_sq_free_used_descs(struct nicvf *nic, struct snd_queue *sq, int qidx) { uint64_t head, tail; struct snd_buff *snd_buff; struct sq_hdr_subdesc *hdr; NICVF_TX_LOCK(sq); head = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_HEAD, qidx) >> 4; tail = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_TAIL, qidx) >> 4; while (sq->head != head) { hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, sq->head); if (hdr->subdesc_type != SQ_DESC_TYPE_HEADER) { nicvf_put_sq_desc(sq, 1); continue; } snd_buff = &sq->snd_buff[sq->head]; if (snd_buff->mbuf != NULL) { bus_dmamap_unload(sq->snd_buff_dmat, snd_buff->dmap); m_freem(snd_buff->mbuf); sq->snd_buff[sq->head].mbuf = NULL; } nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1); } NICVF_TX_UNLOCK(sq); } /* * Add SQ HEADER subdescriptor. * First subdescriptor for every send descriptor. */ static __inline int nicvf_sq_add_hdr_subdesc(struct snd_queue *sq, int qentry, int subdesc_cnt, struct mbuf *mbuf, int len) { struct nicvf *nic; struct sq_hdr_subdesc *hdr; struct ether_vlan_header *eh; #ifdef INET struct ip *ip; struct tcphdr *th; #endif uint16_t etype; int ehdrlen, iphlen, poff; nic = sq->nic; hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, qentry); sq->snd_buff[qentry].mbuf = mbuf; memset(hdr, 0, SND_QUEUE_DESC_SIZE); hdr->subdesc_type = SQ_DESC_TYPE_HEADER; /* Enable notification via CQE after processing SQE */ hdr->post_cqe = 1; /* No of subdescriptors following this */ hdr->subdesc_cnt = subdesc_cnt; hdr->tot_len = len; eh = mtod(mbuf, struct ether_vlan_header *); if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; etype = ntohs(eh->evl_proto); } else { ehdrlen = ETHER_HDR_LEN; etype = ntohs(eh->evl_encap_proto); } switch (etype) { #ifdef INET6 case ETHERTYPE_IPV6: /* ARM64TODO: Add support for IPv6 */ hdr->csum_l3 = 0; sq->snd_buff[qentry].mbuf = NULL; return (ENXIO); #endif #ifdef INET case ETHERTYPE_IP: if (mbuf->m_len < ehdrlen + sizeof(struct ip)) { mbuf = m_pullup(mbuf, ehdrlen + sizeof(struct ip)); sq->snd_buff[qentry].mbuf = mbuf; if (mbuf == NULL) return (ENOBUFS); } ip = (struct ip *)(mbuf->m_data + ehdrlen); iphlen = ip->ip_hl << 2; poff = ehdrlen + iphlen; if (mbuf->m_pkthdr.csum_flags != 0) { hdr->csum_l3 = 1; /* Enable IP csum calculation */ switch (ip->ip_p) { case IPPROTO_TCP: if ((mbuf->m_pkthdr.csum_flags & CSUM_TCP) == 0) break; if (mbuf->m_len < (poff + sizeof(struct tcphdr))) { mbuf = m_pullup(mbuf, poff + sizeof(struct tcphdr)); sq->snd_buff[qentry].mbuf = mbuf; if (mbuf == NULL) return (ENOBUFS); } hdr->csum_l4 = SEND_L4_CSUM_TCP; break; case IPPROTO_UDP: if ((mbuf->m_pkthdr.csum_flags & CSUM_UDP) == 0) break; if (mbuf->m_len < (poff + sizeof(struct udphdr))) { mbuf = m_pullup(mbuf, poff + sizeof(struct udphdr)); sq->snd_buff[qentry].mbuf = mbuf; if (mbuf == NULL) return (ENOBUFS); } hdr->csum_l4 = SEND_L4_CSUM_UDP; break; case IPPROTO_SCTP: if ((mbuf->m_pkthdr.csum_flags & CSUM_SCTP) == 0) break; if (mbuf->m_len < (poff + sizeof(struct sctphdr))) { mbuf = m_pullup(mbuf, poff + sizeof(struct sctphdr)); sq->snd_buff[qentry].mbuf = mbuf; if (mbuf == NULL) return (ENOBUFS); } hdr->csum_l4 = SEND_L4_CSUM_SCTP; break; default: break; } hdr->l3_offset = ehdrlen; hdr->l4_offset = ehdrlen + iphlen; } if ((mbuf->m_pkthdr.tso_segsz != 0) && nic->hw_tso) { /* * Extract ip again as m_data could have been modified. */ ip = (struct ip *)(mbuf->m_data + ehdrlen); th = (struct tcphdr *)((caddr_t)ip + iphlen); hdr->tso = 1; hdr->tso_start = ehdrlen + iphlen + (th->th_off * 4); hdr->tso_max_paysize = mbuf->m_pkthdr.tso_segsz; hdr->inner_l3_offset = ehdrlen - 2; nic->drv_stats.tx_tso++; } break; #endif default: hdr->csum_l3 = 0; } return (0); } /* * SQ GATHER subdescriptor * Must follow HDR descriptor */ static inline void nicvf_sq_add_gather_subdesc(struct snd_queue *sq, int qentry, int size, uint64_t data) { struct sq_gather_subdesc *gather; qentry &= (sq->dmem.q_len - 1); gather = (struct sq_gather_subdesc *)GET_SQ_DESC(sq, qentry); memset(gather, 0, SND_QUEUE_DESC_SIZE); gather->subdesc_type = SQ_DESC_TYPE_GATHER; gather->ld_type = NIC_SEND_LD_TYPE_E_LDD; gather->size = size; gather->addr = data; } /* Put an mbuf to a SQ for packet transfer. */ static int nicvf_tx_mbuf_locked(struct snd_queue *sq, struct mbuf **mbufp) { bus_dma_segment_t segs[256]; struct snd_buff *snd_buff; size_t seg; int nsegs, qentry; int subdesc_cnt; int err; NICVF_TX_LOCK_ASSERT(sq); if (sq->free_cnt == 0) return (ENOBUFS); snd_buff = &sq->snd_buff[sq->tail]; err = bus_dmamap_load_mbuf_sg(sq->snd_buff_dmat, snd_buff->dmap, *mbufp, segs, &nsegs, BUS_DMA_NOWAIT); if (__predict_false(err != 0)) { /* ARM64TODO: Add mbuf defragmenting if we lack maps */ m_freem(*mbufp); *mbufp = NULL; return (err); } /* Set how many subdescriptors is required */ subdesc_cnt = MIN_SQ_DESC_PER_PKT_XMIT + nsegs - 1; if (subdesc_cnt > sq->free_cnt) { /* ARM64TODO: Add mbuf defragmentation if we lack descriptors */ bus_dmamap_unload(sq->snd_buff_dmat, snd_buff->dmap); return (ENOBUFS); } qentry = nicvf_get_sq_desc(sq, subdesc_cnt); /* Add SQ header subdesc */ err = nicvf_sq_add_hdr_subdesc(sq, qentry, subdesc_cnt - 1, *mbufp, (*mbufp)->m_pkthdr.len); if (err != 0) { nicvf_put_sq_desc(sq, subdesc_cnt); bus_dmamap_unload(sq->snd_buff_dmat, snd_buff->dmap); if (err == ENOBUFS) { m_freem(*mbufp); *mbufp = NULL; } return (err); } /* Add SQ gather subdescs */ for (seg = 0; seg < nsegs; seg++) { qentry = nicvf_get_nxt_sqentry(sq, qentry); nicvf_sq_add_gather_subdesc(sq, qentry, segs[seg].ds_len, segs[seg].ds_addr); } /* make sure all memory stores are done before ringing doorbell */ bus_dmamap_sync(sq->dmem.dmat, sq->dmem.dmap, BUS_DMASYNC_PREWRITE); dprintf(sq->nic->dev, "%s: sq->idx: %d, subdesc_cnt: %d\n", __func__, sq->idx, subdesc_cnt); /* Inform HW to xmit new packet */ nicvf_queue_reg_write(sq->nic, NIC_QSET_SQ_0_7_DOOR, sq->idx, subdesc_cnt); return (0); } static __inline u_int frag_num(u_int i) { #if BYTE_ORDER == BIG_ENDIAN return ((i & ~3) + 3 - (i & 3)); #else return (i); #endif } /* Returns MBUF for a received packet */ struct mbuf * nicvf_get_rcv_mbuf(struct nicvf *nic, struct cqe_rx_t *cqe_rx) { int frag; int payload_len = 0; struct mbuf *mbuf; struct mbuf *mbuf_frag; uint16_t *rb_lens = NULL; uint64_t *rb_ptrs = NULL; mbuf = NULL; rb_lens = (uint16_t *)((uint8_t *)cqe_rx + (3 * sizeof(uint64_t))); rb_ptrs = (uint64_t *)((uint8_t *)cqe_rx + (6 * sizeof(uint64_t))); dprintf(nic->dev, "%s rb_cnt %d rb0_ptr %lx rb0_sz %d\n", __func__, cqe_rx->rb_cnt, cqe_rx->rb0_ptr, cqe_rx->rb0_sz); for (frag = 0; frag < cqe_rx->rb_cnt; frag++) { payload_len = rb_lens[frag_num(frag)]; if (frag == 0) { /* First fragment */ mbuf = nicvf_rb_ptr_to_mbuf(nic, (*rb_ptrs - cqe_rx->align_pad)); mbuf->m_len = payload_len; mbuf->m_data += cqe_rx->align_pad; if_setrcvif(mbuf, nic->ifp); } else { /* Add fragments */ mbuf_frag = nicvf_rb_ptr_to_mbuf(nic, *rb_ptrs); m_append(mbuf, payload_len, mbuf_frag->m_data); m_freem(mbuf_frag); } /* Next buffer pointer */ rb_ptrs++; } if (__predict_true(mbuf != NULL)) { m_fixhdr(mbuf); mbuf->m_pkthdr.flowid = cqe_rx->rq_idx; M_HASHTYPE_SET(mbuf, M_HASHTYPE_OPAQUE); if (__predict_true((if_getcapenable(nic->ifp) & IFCAP_RXCSUM) != 0)) { /* * HW by default verifies IP & TCP/UDP/SCTP checksums */ if (__predict_true(cqe_rx->l3_type == L3TYPE_IPV4)) { mbuf->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | CSUM_IP_VALID); } switch (cqe_rx->l4_type) { case L4TYPE_UDP: case L4TYPE_TCP: /* fall through */ mbuf->m_pkthdr.csum_flags |= (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); mbuf->m_pkthdr.csum_data = 0xffff; break; case L4TYPE_SCTP: mbuf->m_pkthdr.csum_flags |= CSUM_SCTP_VALID; break; default: break; } } } return (mbuf); } /* Enable interrupt */ void nicvf_enable_intr(struct nicvf *nic, int int_type, int q_idx) { uint64_t reg_val; reg_val = nicvf_reg_read(nic, NIC_VF_ENA_W1S); switch (int_type) { case NICVF_INTR_CQ: reg_val |= ((1UL << q_idx) << NICVF_INTR_CQ_SHIFT); break; case NICVF_INTR_SQ: reg_val |= ((1UL << q_idx) << NICVF_INTR_SQ_SHIFT); break; case NICVF_INTR_RBDR: reg_val |= ((1UL << q_idx) << NICVF_INTR_RBDR_SHIFT); break; case NICVF_INTR_PKT_DROP: reg_val |= (1UL << NICVF_INTR_PKT_DROP_SHIFT); break; case NICVF_INTR_TCP_TIMER: reg_val |= (1UL << NICVF_INTR_TCP_TIMER_SHIFT); break; case NICVF_INTR_MBOX: reg_val |= (1UL << NICVF_INTR_MBOX_SHIFT); break; case NICVF_INTR_QS_ERR: reg_val |= (1UL << NICVF_INTR_QS_ERR_SHIFT); break; default: device_printf(nic->dev, "Failed to enable interrupt: unknown type\n"); break; } nicvf_reg_write(nic, NIC_VF_ENA_W1S, reg_val); } /* Disable interrupt */ void nicvf_disable_intr(struct nicvf *nic, int int_type, int q_idx) { uint64_t reg_val = 0; switch (int_type) { case NICVF_INTR_CQ: reg_val |= ((1UL << q_idx) << NICVF_INTR_CQ_SHIFT); break; case NICVF_INTR_SQ: reg_val |= ((1UL << q_idx) << NICVF_INTR_SQ_SHIFT); break; case NICVF_INTR_RBDR: reg_val |= ((1UL << q_idx) << NICVF_INTR_RBDR_SHIFT); break; case NICVF_INTR_PKT_DROP: reg_val |= (1UL << NICVF_INTR_PKT_DROP_SHIFT); break; case NICVF_INTR_TCP_TIMER: reg_val |= (1UL << NICVF_INTR_TCP_TIMER_SHIFT); break; case NICVF_INTR_MBOX: reg_val |= (1UL << NICVF_INTR_MBOX_SHIFT); break; case NICVF_INTR_QS_ERR: reg_val |= (1UL << NICVF_INTR_QS_ERR_SHIFT); break; default: device_printf(nic->dev, "Failed to disable interrupt: unknown type\n"); break; } nicvf_reg_write(nic, NIC_VF_ENA_W1C, reg_val); } /* Clear interrupt */ void nicvf_clear_intr(struct nicvf *nic, int int_type, int q_idx) { uint64_t reg_val = 0; switch (int_type) { case NICVF_INTR_CQ: reg_val = ((1UL << q_idx) << NICVF_INTR_CQ_SHIFT); break; case NICVF_INTR_SQ: reg_val = ((1UL << q_idx) << NICVF_INTR_SQ_SHIFT); break; case NICVF_INTR_RBDR: reg_val = ((1UL << q_idx) << NICVF_INTR_RBDR_SHIFT); break; case NICVF_INTR_PKT_DROP: reg_val = (1UL << NICVF_INTR_PKT_DROP_SHIFT); break; case NICVF_INTR_TCP_TIMER: reg_val = (1UL << NICVF_INTR_TCP_TIMER_SHIFT); break; case NICVF_INTR_MBOX: reg_val = (1UL << NICVF_INTR_MBOX_SHIFT); break; case NICVF_INTR_QS_ERR: reg_val |= (1UL << NICVF_INTR_QS_ERR_SHIFT); break; default: device_printf(nic->dev, "Failed to clear interrupt: unknown type\n"); break; } nicvf_reg_write(nic, NIC_VF_INT, reg_val); } /* Check if interrupt is enabled */ int nicvf_is_intr_enabled(struct nicvf *nic, int int_type, int q_idx) { uint64_t reg_val; uint64_t mask = 0xff; reg_val = nicvf_reg_read(nic, NIC_VF_ENA_W1S); switch (int_type) { case NICVF_INTR_CQ: mask = ((1UL << q_idx) << NICVF_INTR_CQ_SHIFT); break; case NICVF_INTR_SQ: mask = ((1UL << q_idx) << NICVF_INTR_SQ_SHIFT); break; case NICVF_INTR_RBDR: mask = ((1UL << q_idx) << NICVF_INTR_RBDR_SHIFT); break; case NICVF_INTR_PKT_DROP: mask = NICVF_INTR_PKT_DROP_MASK; break; case NICVF_INTR_TCP_TIMER: mask = NICVF_INTR_TCP_TIMER_MASK; break; case NICVF_INTR_MBOX: mask = NICVF_INTR_MBOX_MASK; break; case NICVF_INTR_QS_ERR: mask = NICVF_INTR_QS_ERR_MASK; break; default: device_printf(nic->dev, "Failed to check interrupt enable: unknown type\n"); break; } return (reg_val & mask); } void nicvf_update_rq_stats(struct nicvf *nic, int rq_idx) { struct rcv_queue *rq; #define GET_RQ_STATS(reg) \ nicvf_reg_read(nic, NIC_QSET_RQ_0_7_STAT_0_1 |\ (rq_idx << NIC_Q_NUM_SHIFT) | (reg << 3)) rq = &nic->qs->rq[rq_idx]; rq->stats.bytes = GET_RQ_STATS(RQ_SQ_STATS_OCTS); rq->stats.pkts = GET_RQ_STATS(RQ_SQ_STATS_PKTS); } void nicvf_update_sq_stats(struct nicvf *nic, int sq_idx) { struct snd_queue *sq; #define GET_SQ_STATS(reg) \ nicvf_reg_read(nic, NIC_QSET_SQ_0_7_STAT_0_1 |\ (sq_idx << NIC_Q_NUM_SHIFT) | (reg << 3)) sq = &nic->qs->sq[sq_idx]; sq->stats.bytes = GET_SQ_STATS(RQ_SQ_STATS_OCTS); sq->stats.pkts = GET_SQ_STATS(RQ_SQ_STATS_PKTS); } /* Check for errors in the receive cmp.queue entry */ int nicvf_check_cqe_rx_errs(struct nicvf *nic, struct cmp_queue *cq, struct cqe_rx_t *cqe_rx) { struct nicvf_hw_stats *stats = &nic->hw_stats; struct nicvf_drv_stats *drv_stats = &nic->drv_stats; if (!cqe_rx->err_level && !cqe_rx->err_opcode) { drv_stats->rx_frames_ok++; return (0); } switch (cqe_rx->err_opcode) { case CQ_RX_ERROP_RE_PARTIAL: stats->rx_bgx_truncated_pkts++; break; case CQ_RX_ERROP_RE_JABBER: stats->rx_jabber_errs++; break; case CQ_RX_ERROP_RE_FCS: stats->rx_fcs_errs++; break; case CQ_RX_ERROP_RE_RX_CTL: stats->rx_bgx_errs++; break; case CQ_RX_ERROP_PREL2_ERR: stats->rx_prel2_errs++; break; case CQ_RX_ERROP_L2_MAL: stats->rx_l2_hdr_malformed++; break; case CQ_RX_ERROP_L2_OVERSIZE: stats->rx_oversize++; break; case CQ_RX_ERROP_L2_UNDERSIZE: stats->rx_undersize++; break; case CQ_RX_ERROP_L2_LENMISM: stats->rx_l2_len_mismatch++; break; case CQ_RX_ERROP_L2_PCLP: stats->rx_l2_pclp++; break; case CQ_RX_ERROP_IP_NOT: stats->rx_ip_ver_errs++; break; case CQ_RX_ERROP_IP_CSUM_ERR: stats->rx_ip_csum_errs++; break; case CQ_RX_ERROP_IP_MAL: stats->rx_ip_hdr_malformed++; break; case CQ_RX_ERROP_IP_MALD: stats->rx_ip_payload_malformed++; break; case CQ_RX_ERROP_IP_HOP: stats->rx_ip_ttl_errs++; break; case CQ_RX_ERROP_L3_PCLP: stats->rx_l3_pclp++; break; case CQ_RX_ERROP_L4_MAL: stats->rx_l4_malformed++; break; case CQ_RX_ERROP_L4_CHK: stats->rx_l4_csum_errs++; break; case CQ_RX_ERROP_UDP_LEN: stats->rx_udp_len_errs++; break; case CQ_RX_ERROP_L4_PORT: stats->rx_l4_port_errs++; break; case CQ_RX_ERROP_TCP_FLAG: stats->rx_tcp_flag_errs++; break; case CQ_RX_ERROP_TCP_OFFSET: stats->rx_tcp_offset_errs++; break; case CQ_RX_ERROP_L4_PCLP: stats->rx_l4_pclp++; break; case CQ_RX_ERROP_RBDR_TRUNC: stats->rx_truncated_pkts++; break; } return (1); } /* Check for errors in the send cmp.queue entry */ int nicvf_check_cqe_tx_errs(struct nicvf *nic, struct cmp_queue *cq, struct cqe_send_t *cqe_tx) { struct cmp_queue_stats *stats = &cq->stats; switch (cqe_tx->send_status) { case CQ_TX_ERROP_GOOD: stats->tx.good++; return (0); case CQ_TX_ERROP_DESC_FAULT: stats->tx.desc_fault++; break; case CQ_TX_ERROP_HDR_CONS_ERR: stats->tx.hdr_cons_err++; break; case CQ_TX_ERROP_SUBDC_ERR: stats->tx.subdesc_err++; break; case CQ_TX_ERROP_IMM_SIZE_OFLOW: stats->tx.imm_size_oflow++; break; case CQ_TX_ERROP_DATA_SEQUENCE_ERR: stats->tx.data_seq_err++; break; case CQ_TX_ERROP_MEM_SEQUENCE_ERR: stats->tx.mem_seq_err++; break; case CQ_TX_ERROP_LOCK_VIOL: stats->tx.lock_viol++; break; case CQ_TX_ERROP_DATA_FAULT: stats->tx.data_fault++; break; case CQ_TX_ERROP_TSTMP_CONFLICT: stats->tx.tstmp_conflict++; break; case CQ_TX_ERROP_TSTMP_TIMEOUT: stats->tx.tstmp_timeout++; break; case CQ_TX_ERROP_MEM_FAULT: stats->tx.mem_fault++; break; case CQ_TX_ERROP_CK_OVERLAP: stats->tx.csum_overlap++; break; case CQ_TX_ERROP_CK_OFLOW: stats->tx.csum_overflow++; break; } return (1); }