Index: head/sys/dev/bhnd/cores/pci/bhnd_pci.c =================================================================== --- head/sys/dev/bhnd/cores/pci/bhnd_pci.c (revision 298946) +++ head/sys/dev/bhnd/cores/pci/bhnd_pci.c (revision 298947) @@ -1,549 +1,548 @@ /*- * Copyright (c) 2015 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); /* * Broadcom Common PCI/PCIe Support. * * This base driver implementation is shared by the bhnd_pcib (root complex) * and bhnd_pci_hostb (host bridge) drivers. */ #include #include #include #include #include #include #include #include #include #include #include #include "bhnd_pcireg.h" #include "bhnd_pcivar.h" static int bhnd_pcie_mdio_wait_idle(struct bhnd_pci_softc *sc); static int bhnd_pcie_mdio_ioctl(struct bhnd_pci_softc *sc, uint32_t cmd); static int bhnd_pcie_mdio_enable(struct bhnd_pci_softc *sc); static void bhnd_pcie_mdio_disable(struct bhnd_pci_softc *sc); static int bhnd_pcie_mdio_cmd_write(struct bhnd_pci_softc *sc, uint32_t cmd); static int bhnd_pcie_mdio_cmd_read(struct bhnd_pci_softc *sc, uint32_t cmd, uint16_t *data_read); static struct bhnd_device_quirk bhnd_pci_quirks[]; static struct bhnd_device_quirk bhnd_pcie_quirks[]; #define BHND_PCI_QUIRKS bhnd_pci_quirks #define BHND_PCIE_QUIRKS bhnd_pcie_quirks #define BHND_PCI_DEV(_core, _desc, ...) \ { BHND_DEVICE(_core, _desc, BHND_ ## _core ## _QUIRKS, \ ## __VA_ARGS__), BHND_PCI_REGFMT_ ## _core } static const struct bhnd_pci_device { struct bhnd_device device; bhnd_pci_regfmt_t regfmt; /**< register format */ } bhnd_pci_devs[] = { BHND_PCI_DEV(PCI, "Host-PCI bridge", BHND_DF_HOSTB), BHND_PCI_DEV(PCI, "PCI-BHND bridge"), BHND_PCI_DEV(PCIE, "PCIe-G1 Host-PCI bridge", BHND_DF_HOSTB), BHND_PCI_DEV(PCIE, "PCIe-G1 PCI-BHND bridge"), { BHND_DEVICE_END, 0 } }; /* Device quirks tables */ static struct bhnd_device_quirk bhnd_pci_quirks[] = { BHND_DEVICE_QUIRK_END }; static struct bhnd_device_quirk bhnd_pcie_quirks[] = { { BHND_HWREV_GTE (10), BHND_PCI_QUIRK_SD_C22_EXTADDR }, BHND_DEVICE_QUIRK_END }; #define BHND_PCIE_MDIO_CTL_DELAY 10 /**< usec delay required between * MDIO_CTL/MDIO_DATA accesses. */ #define BHND_PCIE_MDIO_RETRY_DELAY 2000 /**< usec delay before retrying * BHND_PCIE_MDIOCTL_DONE. */ #define BHND_PCIE_MDIO_RETRY_COUNT 200 /**< number of times to loop waiting * for BHND_PCIE_MDIOCTL_DONE. */ #define BHND_PCI_READ_4(_sc, _reg) \ bhnd_bus_read_4((_sc)->mem_res, (_reg)) #define BHND_PCI_WRITE_4(_sc, _reg, _val) \ bhnd_bus_write_4((_sc)->mem_res, (_reg), (_val)) #define BHND_PCIE_ASSERT(sc) \ KASSERT(bhnd_get_class(sc->dev) == BHND_DEVCLASS_PCIE, \ ("not a pcie device!")); int bhnd_pci_generic_probe(device_t dev) { const struct bhnd_device *id; id = bhnd_device_lookup(dev, &bhnd_pci_devs[0].device, sizeof(bhnd_pci_devs[0])); if (id == NULL) return (ENXIO); bhnd_set_custom_core_desc(dev, id->desc); return (BUS_PROBE_DEFAULT); } int bhnd_pci_generic_attach(device_t dev) { struct bhnd_pci_softc *sc; int error; sc = device_get_softc(dev); sc->dev = dev; sc->quirks = bhnd_device_quirks(dev, &bhnd_pci_devs[0].device, sizeof(bhnd_pci_devs[0])); /* Allocate bus resources */ sc->mem_res = bhnd_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, RF_ACTIVE); if (sc->mem_res == NULL) return (ENXIO); BHND_PCI_LOCK_INIT(sc); /* Probe and attach children */ if ((error = bus_generic_attach(dev))) goto cleanup; return (0); cleanup: bhnd_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res); BHND_PCI_LOCK_DESTROY(sc); return (error); } int bhnd_pci_generic_detach(device_t dev) { struct bhnd_pci_softc *sc; int error; sc = device_get_softc(dev); if ((error = bus_generic_detach(dev))) return (error); bhnd_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res); BHND_PCI_LOCK_DESTROY(sc); return (0); } static struct resource_list * bhnd_pci_get_resource_list(device_t dev, device_t child) { struct bhnd_pci_devinfo *dinfo; if (device_get_parent(child) != dev) return (NULL); dinfo = device_get_ivars(child); return (&dinfo->resources); } static device_t bhnd_pci_add_child(device_t dev, u_int order, const char *name, int unit) { struct bhnd_pci_devinfo *dinfo; device_t child; child = device_add_child_ordered(dev, order, name, unit); if (child == NULL) return (NULL); dinfo = malloc(sizeof(struct bhnd_pci_devinfo), M_DEVBUF, M_NOWAIT); if (dinfo == NULL) { device_delete_child(dev, child); return (NULL); } resource_list_init(&dinfo->resources); device_set_ivars(child, dinfo); return (child); } static void bhnd_pci_child_deleted(device_t dev, device_t child) { struct bhnd_pci_devinfo *dinfo; if (device_get_parent(child) != dev) return; dinfo = device_get_ivars(child); if (dinfo != NULL) { resource_list_free(&dinfo->resources); free(dinfo, M_DEVBUF); } device_set_ivars(child, NULL); } int bhnd_pci_generic_suspend(device_t dev) { return (bus_generic_suspend(dev)); } int bhnd_pci_generic_resume(device_t dev) { return (bus_generic_resume(dev)); } /** * Read a 32-bit PCIe TLP/DLLP/PLP protocol register. * * @param sc The bhndb_pci driver state. * @param addr The protocol register offset. */ uint32_t bhnd_pcie_read_proto_reg(struct bhnd_pci_softc *sc, uint32_t addr) { uint32_t val; BHND_PCIE_ASSERT(sc); BHND_PCI_LOCK(sc); BHND_PCI_WRITE_4(sc, BHND_PCIE_IND_ADDR, addr); val = BHND_PCI_READ_4(sc, BHND_PCIE_IND_DATA); BHND_PCI_UNLOCK(sc); return (val); } /** * Write a 32-bit PCIe TLP/DLLP/PLP protocol register value. * * @param sc The bhndb_pci driver state. * @param addr The protocol register offset. * @param val The value to write to @p addr. */ void bhnd_pcie_write_proto_reg(struct bhnd_pci_softc *sc, uint32_t addr, uint32_t val) { BHND_PCIE_ASSERT(sc); BHND_PCI_LOCK(sc); BHND_PCI_WRITE_4(sc, BHND_PCIE_IND_ADDR, addr); BHND_PCI_WRITE_4(sc, BHND_PCIE_IND_DATA, val); BHND_PCI_UNLOCK(sc); } /* Spin until the MDIO device reports itself as idle, or timeout is reached. */ static int bhnd_pcie_mdio_wait_idle(struct bhnd_pci_softc *sc) { uint32_t ctl; /* Spin waiting for the BUSY flag to clear */ for (int i = 0; i < BHND_PCIE_MDIO_RETRY_COUNT; i++) { ctl = BHND_PCI_READ_4(sc, BHND_PCIE_MDIO_CTL); if ((ctl & BHND_PCIE_MDIOCTL_DONE)) return (0); DELAY(BHND_PCIE_MDIO_RETRY_DELAY); } return (ETIMEDOUT); } /** * Write an MDIO IOCTL and wait for completion. */ static int bhnd_pcie_mdio_ioctl(struct bhnd_pci_softc *sc, uint32_t cmd) { BHND_PCI_LOCK_ASSERT(sc, MA_OWNED); BHND_PCI_WRITE_4(sc, BHND_PCIE_MDIO_CTL, cmd); DELAY(BHND_PCIE_MDIO_CTL_DELAY); return (0); } /** * Enable MDIO device */ static int bhnd_pcie_mdio_enable(struct bhnd_pci_softc *sc) { uint32_t ctl; BHND_PCIE_ASSERT(sc); /* Enable MDIO clock and preamble mode */ ctl = BHND_PCIE_MDIOCTL_PREAM_EN|BHND_PCIE_MDIOCTL_DIVISOR_VAL; return (bhnd_pcie_mdio_ioctl(sc, ctl)); } /** * Disable MDIO device. */ static void bhnd_pcie_mdio_disable(struct bhnd_pci_softc *sc) { if (bhnd_pcie_mdio_ioctl(sc, 0)) device_printf(sc->dev, "failed to disable MDIO clock\n"); } /** * Issue a write command and wait for completion */ static int bhnd_pcie_mdio_cmd_write(struct bhnd_pci_softc *sc, uint32_t cmd) { int error; BHND_PCI_LOCK_ASSERT(sc, MA_OWNED); cmd |= BHND_PCIE_MDIODATA_START|BHND_PCIE_MDIODATA_TA|BHND_PCIE_MDIODATA_CMD_WRITE; BHND_PCI_WRITE_4(sc, BHND_PCIE_MDIO_DATA, cmd); DELAY(BHND_PCIE_MDIO_CTL_DELAY); if ((error = bhnd_pcie_mdio_wait_idle(sc))) return (error); return (0); } /** * Issue an an MDIO read command, wait for completion, and return * the result in @p data_read. */ static int bhnd_pcie_mdio_cmd_read(struct bhnd_pci_softc *sc, uint32_t cmd, uint16_t *data_read) { int error; BHND_PCI_LOCK_ASSERT(sc, MA_OWNED); cmd |= BHND_PCIE_MDIODATA_START|BHND_PCIE_MDIODATA_TA|BHND_PCIE_MDIODATA_CMD_READ; BHND_PCI_WRITE_4(sc, BHND_PCIE_MDIO_DATA, cmd); DELAY(BHND_PCIE_MDIO_CTL_DELAY); if ((error = bhnd_pcie_mdio_wait_idle(sc))) return (error); *data_read = (BHND_PCI_READ_4(sc, BHND_PCIE_MDIO_DATA) & BHND_PCIE_MDIODATA_DATA_MASK); return (0); } int bhnd_pcie_mdio_read(struct bhnd_pci_softc *sc, int phy, int reg) { uint32_t cmd; uint16_t val; int error; /* Enable MDIO access */ BHND_PCI_LOCK(sc); bhnd_pcie_mdio_enable(sc); /* Issue the read */ cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg); error = bhnd_pcie_mdio_cmd_read(sc, cmd, &val); /* Disable MDIO access */ bhnd_pcie_mdio_disable(sc); BHND_PCI_UNLOCK(sc); if (error) return (~0U); return (val); } int bhnd_pcie_mdio_write(struct bhnd_pci_softc *sc, int phy, int reg, int val) { uint32_t cmd; int error; /* Enable MDIO access */ BHND_PCI_LOCK(sc); bhnd_pcie_mdio_enable(sc); /* Issue the write */ cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg) | (val & BHND_PCIE_MDIODATA_DATA_MASK); error = bhnd_pcie_mdio_cmd_write(sc, cmd); /* Disable MDIO access */ bhnd_pcie_mdio_disable(sc); BHND_PCI_UNLOCK(sc); return (error); } int bhnd_pcie_mdio_read_ext(struct bhnd_pci_softc *sc, int phy, int devaddr, int reg) { uint32_t cmd; uint16_t blk, val; uint8_t blk_reg; int error; if (devaddr == MDIO_DEVADDR_NONE) return (bhnd_pcie_mdio_read(sc, phy, reg)); /* Extended register access is only supported for the SerDes device, * using the non-standard C22 extended address mechanism */ if (!(sc->quirks & BHND_PCI_QUIRK_SD_C22_EXTADDR)) return (~0U); if (phy != BHND_PCIE_PHYADDR_SD || devaddr != BHND_PCIE_DEVAD_SD) return (~0U); /* Enable MDIO access */ BHND_PCI_LOCK(sc); bhnd_pcie_mdio_enable(sc); /* Determine the block and register values */ blk = (reg & BHND_PCIE_SD_ADDREXT_BLK_MASK); blk_reg = (reg & BHND_PCIE_SD_ADDREXT_REG_MASK); /* Write the block address to the address extension register */ cmd = BHND_PCIE_MDIODATA_ADDR(phy, BHND_PCIE_SD_ADDREXT) | (blk & BHND_PCIE_MDIODATA_DATA_MASK); if ((error = bhnd_pcie_mdio_cmd_write(sc, cmd))) goto cleanup; /* Issue the read */ cmd = BHND_PCIE_MDIODATA_ADDR(phy, blk_reg); error = bhnd_pcie_mdio_cmd_read(sc, cmd, &val); cleanup: bhnd_pcie_mdio_disable(sc); BHND_PCI_UNLOCK(sc); if (error) return (~0U); return (val); } int bhnd_pcie_mdio_write_ext(struct bhnd_pci_softc *sc, int phy, int devaddr, int reg, int val) { uint32_t cmd; uint16_t blk; uint8_t blk_reg; int error; if (devaddr == MDIO_DEVADDR_NONE) return (bhnd_pcie_mdio_write(sc, phy, reg, val)); /* Extended register access is only supported for the SerDes device, * using the non-standard C22 extended address mechanism */ if (!(sc->quirks & BHND_PCI_QUIRK_SD_C22_EXTADDR)) return (~0U); if (phy != BHND_PCIE_PHYADDR_SD || devaddr != BHND_PCIE_DEVAD_SD) return (~0U); /* Enable MDIO access */ BHND_PCI_LOCK(sc); bhnd_pcie_mdio_enable(sc); /* Determine the block and register values */ blk = (reg & BHND_PCIE_SD_ADDREXT_BLK_MASK); blk_reg = (reg & BHND_PCIE_SD_ADDREXT_REG_MASK); /* Write the block address to the address extension register */ cmd = BHND_PCIE_MDIODATA_ADDR(phy, BHND_PCIE_SD_ADDREXT) | (blk & BHND_PCIE_MDIODATA_DATA_MASK); if ((error = bhnd_pcie_mdio_cmd_write(sc, cmd))) goto cleanup; /* Issue the write */ cmd = BHND_PCIE_MDIODATA_ADDR(phy, blk_reg) | (val & BHND_PCIE_MDIODATA_DATA_MASK); error = bhnd_pcie_mdio_cmd_write(sc, cmd); cleanup: bhnd_pcie_mdio_disable(sc); BHND_PCI_UNLOCK(sc); return (error); } static device_method_t bhnd_pci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, bhnd_pci_generic_probe), DEVMETHOD(device_attach, bhnd_pci_generic_attach), DEVMETHOD(device_detach, bhnd_pci_generic_detach), DEVMETHOD(device_suspend, bhnd_pci_generic_suspend), DEVMETHOD(device_resume, bhnd_pci_generic_resume), /* Bus interface */ DEVMETHOD(bus_add_child, bhnd_pci_add_child), DEVMETHOD(bus_child_deleted, bhnd_pci_child_deleted), DEVMETHOD(bus_print_child, bus_generic_print_child), DEVMETHOD(bus_get_resource_list, bhnd_pci_get_resource_list), DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), DEVMETHOD_END }; DEFINE_CLASS_0(bhnd_pci, bhnd_pci_driver, bhnd_pci_methods, sizeof(struct bhnd_pci_softc)); - -MODULE_VERSION(bhnd_pci, 1); -MODULE_DEPEND(bhnd_pci, pci, 1, 1, 1); MODULE_DEPEND(bhnd_pci, bhnd, 1, 1, 1); +MODULE_DEPEND(bhnd_pci, pci, 1, 1, 1); +MODULE_VERSION(bhnd_pci, 1); Index: head/sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c =================================================================== --- head/sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c (revision 298946) +++ head/sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c (revision 298947) @@ -1,452 +1,453 @@ /*- * Copyright (c) 2015 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); /* * Broadcom BHND PCI/PCIe-Gen1 PCI-Host Bridge. * * This driver handles all interactions with PCI bridge cores operating in * endpoint mode. * * Host-level PCI operations are handled at the bhndb bridge level by the * bhndb_pci driver. */ #include #include #include #include #include #include #include #include #include #include #include "bhnd_pcireg.h" #include "bhnd_pci_hostbvar.h" #define BHND_PCI_ASSERT_QUIRK(_sc, _name) \ KASSERT((_sc)->quirks & (_name), ("quirk " __STRING(_name) " not set")) #define BHND_PCI_DEV(_core, _quirks) \ BHND_DEVICE(_core, "", _quirks, BHND_DF_HOSTB) static const struct bhnd_device_quirk bhnd_pci_quirks[]; static const struct bhnd_device_quirk bhnd_pcie_quirks[]; static int bhnd_pci_wars_early_once(struct bhnd_pcihb_softc *sc); static int bhnd_pci_wars_hwup(struct bhnd_pcihb_softc *sc); static int bhnd_pci_wars_hwdown(struct bhnd_pcihb_softc *sc); /* * device/quirk tables */ static const struct bhnd_device bhnd_pci_devs[] = { BHND_PCI_DEV(PCI, bhnd_pci_quirks), BHND_PCI_DEV(PCIE, bhnd_pcie_quirks), BHND_DEVICE_END }; static const struct bhnd_device_quirk bhnd_pci_quirks[] = { { BHND_HWREV_ANY, BHND_PCI_QUIRK_SBTOPCI2_PREF_BURST }, { BHND_HWREV_GTE(11), BHND_PCI_QUIRK_SBTOPCI2_READMULTI | BHND_PCI_QUIRK_CLKRUN_DSBL }, BHND_DEVICE_QUIRK_END }; static const struct bhnd_device_quirk bhnd_pcie_quirks[] = { { BHND_HWREV_EQ (0), BHND_PCIE_QUIRK_SDR9_L0s_HANG }, { BHND_HWREV_RANGE (0, 1), BHND_PCIE_QUIRK_UR_STATUS_FIX }, { BHND_HWREV_EQ (1), BHND_PCIE_QUIRK_PCIPM_REQEN }, { BHND_HWREV_RANGE (3, 5), BHND_PCIE_QUIRK_ASPM_OVR | BHND_PCIE_QUIRK_SDR9_POLARITY | BHND_PCIE_QUIRK_SDR9_NO_FREQRETRY }, { BHND_HWREV_LTE (6), BHND_PCIE_QUIRK_L1_IDLE_THRESH }, { BHND_HWREV_GTE (6), BHND_PCIE_QUIRK_SPROM_L23_PCI_RESET }, { BHND_HWREV_EQ (7), BHND_PCIE_QUIRK_SERDES_NOPLLDOWN }, { BHND_HWREV_GTE (8), BHND_PCIE_QUIRK_L1_TIMER_PERF }, { BHND_HWREV_GTE (10), BHND_PCIE_QUIRK_SD_C22_EXTADDR }, BHND_DEVICE_QUIRK_END }; // Quirk handling TODO // WARs for the following are not yet implemented: // - BHND_PCIE_QUIRK_ASPM_OVR // - BHND_PCIE_QUIRK_SERDES_NOPLLDOWN // Quirks (and WARs) for the following are not yet defined: // - Power savings via MDIO BLK1/PWR_MGMT3 on PCIe hwrev 15-20, 21-22 // - WOWL PME enable/disable // - 4360 PCIe SerDes Tx amplitude/deemphasis (vendor Apple, boards // BCM94360X51P2, BCM94360X51A). // - PCI latency timer (boards CB2_4321_BOARD, CB2_4321_AG_BOARD) // - Max SerDes TX drive strength (vendor Apple, pcie >= rev10, // board BCM94322X9) // - 700mV SerDes TX drive strength (chipid BCM4331, boards BCM94331X19, // BCM94331X28, BCM94331X29B, BCM94331X19C) #define BHND_PCI_SOFTC(_sc) (&((_sc)->common)) #define BHND_PCI_READ_2(_sc, _reg) \ bhnd_bus_read_2(BHND_PCI_SOFTC(_sc)->mem_res, (_reg)) #define BHND_PCI_READ_4(_sc, _reg) \ bhnd_bus_read_4(BHND_PCI_SOFTC(_sc)->mem_res, (_reg)) #define BHND_PCI_WRITE_2(_sc, _reg, _val) \ bhnd_bus_write_2(BHND_PCI_SOFTC(_sc)->mem_res, (_reg), (_val)) #define BHND_PCI_WRITE_4(_sc, _reg, _val) \ bhnd_bus_write_4(BHND_PCI_SOFTC(_sc)->mem_res, (_reg), (_val)) #define BHND_PCI_PROTO_READ_4(_sc, _reg) \ bhnd_pcie_read_proto_reg(BHND_PCI_SOFTC(_sc), (_reg)) #define BHND_PCI_PROTO_WRITE_4(_sc, _reg, _val) \ bhnd_pcie_write_proto_reg(BHND_PCI_SOFTC(_sc), (_reg), (_val)) #define BHND_PCI_MDIO_READ(_sc, _phy, _reg) \ bhnd_pcie_mdio_read(BHND_PCI_SOFTC(_sc), (_phy), (_reg)) #define BHND_PCI_MDIO_WRITE(_sc, _phy, _reg, _val) \ bhnd_pcie_mdio_write(BHND_PCI_SOFTC(_sc), (_phy), (_reg), (_val)) #define BPCI_REG_SET(_regv, _attr, _val) \ BHND_PCI_REG_SET((_regv), BHND_ ## _attr, (_val)) #define BPCI_REG_GET(_regv, _attr) \ BHND_PCI_REG_GET((_regv), BHND_ ## _attr) #define BPCI_CMN_REG_SET(_regv, _attr, _val) \ BHND_PCI_CMN_REG_SET(BHND_PCI_SOFTC(_sc)->regfmt, (_regv), \ BHND_ ## _attr, (_val)) #define BPCI_CMN_REG_GET(_regv, _attr) \ BHND_PCI_CMN_REG_GET(BHND_PCI_SOFTC(_sc)->regfmt, (_regv), \ BHND_ ## _attr) static int bhnd_pci_hostb_attach(device_t dev) { struct bhnd_pcihb_softc *sc; int error; sc = device_get_softc(dev); sc->quirks = bhnd_device_quirks(dev, bhnd_pci_devs, sizeof(bhnd_pci_devs[0])); if ((error = bhnd_pci_generic_attach(dev))) return (error); /* Apply early single-shot work-arounds */ if ((error = bhnd_pci_wars_early_once(sc))) { bhnd_pci_generic_detach(dev); return (error); } /* Apply attach/resume work-arounds */ if ((error = bhnd_pci_wars_hwup(sc))) { bhnd_pci_generic_detach(dev); return (error); } return (0); } static int bhnd_pci_hostb_detach(device_t dev) { struct bhnd_pcihb_softc *sc; int error; sc = device_get_softc(dev); /* Apply suspend/detach work-arounds */ if ((error = bhnd_pci_wars_hwdown(sc))) return (error); return (bhnd_pci_generic_detach(dev)); } static int bhnd_pci_hostb_suspend(device_t dev) { struct bhnd_pcihb_softc *sc; int error; sc = device_get_softc(dev); /* Apply suspend/detach work-arounds */ if ((error = bhnd_pci_wars_hwdown(sc))) return (error); return (bhnd_pci_generic_suspend(dev)); } static int bhnd_pci_hostb_resume(device_t dev) { struct bhnd_pcihb_softc *sc; int error; sc = device_get_softc(dev); if ((error = bhnd_pci_generic_resume(dev))) return (error); /* Apply attach/resume work-arounds */ if ((error = bhnd_pci_wars_hwup(sc))) { bhnd_pci_generic_detach(dev); return (error); } return (0); } /** * Apply any hardware work-arounds that must be executed exactly once, early in * the attach process. * * This must be called after core enumeration and discovery of all applicable * quirks, but prior to probe/attach of any cores, parsing of * SPROM, etc. */ static int bhnd_pci_wars_early_once(struct bhnd_pcihb_softc *sc) { /* Determine correct polarity by observing the attach-time PCIe PHY * link status. This is used later to reset/force the SerDes * polarity */ if (sc->quirks & BHND_PCIE_QUIRK_SDR9_POLARITY) { uint32_t st; bool inv; st = BHND_PCI_PROTO_READ_4(sc, BHND_PCIE_PLP_STATUSREG); inv = ((st & BHND_PCIE_PLP_POLARITY_INV) != 0); sc->sdr9_quirk_polarity.inv = inv; } return (0); } /** * Apply any hardware workarounds that are required upon attach or resume * of the bridge device. */ static int bhnd_pci_wars_hwup(struct bhnd_pcihb_softc *sc) { /* Note that the order here matters; these work-arounds * should not be re-ordered without careful review of their * interdependencies */ /* Enable PCI prefetch/burst/readmulti flags */ if (sc->quirks & BHND_PCI_QUIRK_SBTOPCI2_PREF_BURST || sc->quirks & BHND_PCI_QUIRK_SBTOPCI2_READMULTI) { uint32_t sbp2; sbp2 = BHND_PCI_READ_4(sc, BHND_PCI_SBTOPCI2); if (sc->quirks & BHND_PCI_QUIRK_SBTOPCI2_PREF_BURST) sbp2 |= (BHND_PCI_SBTOPCI_PREF|BHND_PCI_SBTOPCI_BURST); if (sc->quirks & BHND_PCI_QUIRK_SBTOPCI2_READMULTI) sbp2 |= BHND_PCI_SBTOPCI_RC_READMULTI; BHND_PCI_WRITE_4(sc, BHND_PCI_SBTOPCI2, sbp2); } /* Disable PCI CLKRUN# */ if (sc->quirks & BHND_PCI_QUIRK_CLKRUN_DSBL) { uint32_t ctl; ctl = BHND_PCI_READ_4(sc, BHND_PCI_CLKRUN_CTL); ctl |= BHND_PCI_CLKRUN_DSBL; BHND_PCI_WRITE_4(sc, BHND_PCI_CLKRUN_CTL, ctl); } /* Enable TLP unmatched address handling work-around */ if (sc->quirks & BHND_PCIE_QUIRK_UR_STATUS_FIX) { uint32_t wrs; wrs = BHND_PCI_PROTO_READ_4(sc, BHND_PCIE_TLP_WORKAROUNDSREG); wrs |= BHND_PCIE_TLP_WORKAROUND_URBIT; BHND_PCI_PROTO_WRITE_4(sc, BHND_PCIE_TLP_WORKAROUNDSREG, wrs); } /* Adjust SerDes CDR tuning to ensure that CDR is stable before sending * data during L0s to L0 exit transitions. */ if (sc->quirks & BHND_PCIE_QUIRK_SDR9_L0s_HANG) { uint16_t sdv; /* Set RX track/acquire timers to 2.064us/40.96us */ sdv = BPCI_REG_SET(0, PCIE_SDR9_RX_TIMER1_LKTRK, (2064/16)); sdv = BPCI_REG_SET(sdv, PCIE_SDR9_RX_TIMER1_LKACQ, (40960/1024)); BHND_PCI_MDIO_WRITE(sc, BHND_PCIE_PHY_SDR9_TXRX, BHND_PCIE_SDR9_RX_TIMER1, sdv); /* Apply CDR frequency workaround */ sdv = BHND_PCIE_SDR9_RX_CDR_FREQ_OVR_EN; sdv = BPCI_REG_SET(sdv, PCIE_SDR9_RX_CDR_FREQ_OVR, 0x0); BHND_PCI_MDIO_WRITE(sc, BHND_PCIE_PHY_SDR9_TXRX, BHND_PCIE_SDR9_RX_CDR, sdv); /* Apply CDR BW tunings */ sdv = 0; sdv = BPCI_REG_SET(sdv, PCIE_SDR9_RX_CDRBW_INTGTRK, 0x2); sdv = BPCI_REG_SET(sdv, PCIE_SDR9_RX_CDRBW_INTGACQ, 0x4); sdv = BPCI_REG_SET(sdv, PCIE_SDR9_RX_CDRBW_PROPTRK, 0x6); sdv = BPCI_REG_SET(sdv, PCIE_SDR9_RX_CDRBW_PROPACQ, 0x6); BHND_PCI_MDIO_WRITE(sc, BHND_PCIE_PHY_SDR9_TXRX, BHND_PCIE_SDR9_RX_CDRBW, sdv); } /* Force correct SerDes polarity */ if (sc->quirks & BHND_PCIE_QUIRK_SDR9_POLARITY) { uint16_t rxctl; rxctl = BHND_PCI_MDIO_READ(sc, BHND_PCIE_PHY_SDR9_TXRX, BHND_PCIE_SDR9_RX_CTRL); rxctl |= BHND_PCIE_SDR9_RX_CTRL_FORCE; if (sc->sdr9_quirk_polarity.inv) rxctl |= BHND_PCIE_SDR9_RX_CTRL_POLARITY_INV; else rxctl &= ~BHND_PCIE_SDR9_RX_CTRL_POLARITY_INV; BHND_PCI_MDIO_WRITE(sc, BHND_PCIE_PHY_SDR9_TXRX, BHND_PCIE_SDR9_RX_CTRL, rxctl); } /* Disable startup retry on PLL frequency detection failure */ if (sc->quirks & BHND_PCIE_QUIRK_SDR9_NO_FREQRETRY) { uint16_t pctl; pctl = BHND_PCI_MDIO_READ(sc, BHND_PCIE_PHY_SDR9_PLL, BHND_PCIE_SDR9_PLL_CTRL); pctl &= ~BHND_PCIE_SDR9_PLL_CTRL_FREQDET_EN; BHND_PCI_MDIO_WRITE(sc, BHND_PCIE_PHY_SDR9_PLL, BHND_PCIE_SDR9_PLL_CTRL, pctl); } /* Explicitly enable PCI-PM */ if (sc->quirks & BHND_PCIE_QUIRK_PCIPM_REQEN) { uint32_t lcreg; lcreg = BHND_PCI_PROTO_READ_4(sc, BHND_PCIE_DLLP_LCREG); lcreg |= BHND_PCIE_DLLP_LCREG_PCIPM_EN; BHND_PCI_PROTO_WRITE_4(sc, BHND_PCIE_DLLP_LCREG, lcreg); } /* Adjust L1 timer to fix slow L1->L0 transitions */ if (sc->quirks & BHND_PCIE_QUIRK_L1_IDLE_THRESH) { uint32_t pmt; pmt = BHND_PCI_PROTO_READ_4(sc, BHND_PCIE_DLLP_PMTHRESHREG); pmt = BPCI_REG_SET(pmt, PCIE_L1THRESHOLDTIME, BHND_PCIE_L1THRESHOLD_WARVAL); BHND_PCI_PROTO_WRITE_4(sc, BHND_PCIE_DLLP_PMTHRESHREG, pmt); } /* Extend L1 timer for better performance. * TODO: We could enable/disable this on demand for better power * savings if we tie this to HT clock request handling */ if (sc->quirks & BHND_PCIE_QUIRK_L1_TIMER_PERF) { uint32_t pmt; pmt = BHND_PCI_PROTO_READ_4(sc, BHND_PCIE_DLLP_PMTHRESHREG); pmt |= BHND_PCIE_ASPMTIMER_EXTEND; BHND_PCI_PROTO_WRITE_4(sc, BHND_PCIE_DLLP_PMTHRESHREG, pmt); } /* Enable L23READY_EXIT_NOPRST if not already set in SPROM. */ if (sc->quirks & BHND_PCIE_QUIRK_SPROM_L23_PCI_RESET) { bus_size_t reg; uint16_t cfg; /* Fetch the misc cfg flags from SPROM */ reg = BHND_PCIE_SPROM_SHADOW + BHND_PCIE_SRSH_PCIE_MISC_CONFIG; cfg = BHND_PCI_READ_2(sc, reg); /* Write EXIT_NOPRST flag if not already set in SPROM */ if (!(cfg & BHND_PCIE_SRSH_L23READY_EXIT_NOPRST)) { cfg |= BHND_PCIE_SRSH_L23READY_EXIT_NOPRST; BHND_PCI_WRITE_2(sc, reg, cfg); } } return (0); } /** * Apply any hardware workarounds that are required upon detach or suspend * of the bridge device. */ static int bhnd_pci_wars_hwdown(struct bhnd_pcihb_softc *sc) { /* Reduce L1 timer for better power savings. * TODO: We could enable/disable this on demand for better power * savings if we tie this to HT clock request handling */ if (sc->quirks & BHND_PCIE_QUIRK_L1_TIMER_PERF) { uint32_t pmt; pmt = BHND_PCI_PROTO_READ_4(sc, BHND_PCIE_DLLP_PMTHRESHREG); pmt &= ~BHND_PCIE_ASPMTIMER_EXTEND; BHND_PCI_PROTO_WRITE_4(sc, BHND_PCIE_DLLP_PMTHRESHREG, pmt); } return (0); } static device_method_t bhnd_pci_hostb_methods[] = { /* Device interface */ DEVMETHOD(device_attach, bhnd_pci_hostb_attach), DEVMETHOD(device_detach, bhnd_pci_hostb_detach), DEVMETHOD(device_suspend, bhnd_pci_hostb_suspend), DEVMETHOD(device_resume, bhnd_pci_hostb_resume), DEVMETHOD_END }; DEFINE_CLASS_1(bhnd_pci_hostb, bhnd_pci_hostb_driver, bhnd_pci_hostb_methods, sizeof(struct bhnd_pcihb_softc), bhnd_pci_driver); DRIVER_MODULE(bhnd_hostb, bhnd, bhnd_pci_hostb_driver, bhnd_hostb_devclass, 0, 0); MODULE_VERSION(bhnd_pci_hostb, 1); +MODULE_DEPEND(bhnd_pci_hostb, bhnd, 1, 1, 1); MODULE_DEPEND(bhnd_pci_hostb, bhnd_pci, 1, 1, 1); Index: head/sys/dev/bhnd/cores/pci/bhnd_pcib.c =================================================================== --- head/sys/dev/bhnd/cores/pci/bhnd_pcib.c (revision 298946) +++ head/sys/dev/bhnd/cores/pci/bhnd_pcib.c (revision 298947) @@ -1,94 +1,95 @@ /*- * Copyright (c) 2015 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); /* * Broadcom PCI/PCIe-Gen1 Host-PCI bridge. * * This driver handles all interactions with PCI bridge cores operating in * root complex mode. */ #include #include #include #include #include #include #include #include #include "bhnd_pcireg.h" #include "bhnd_pcibvar.h" static int bhnd_pcib_attach(device_t dev) { // TODO return (bhnd_pci_generic_attach(dev)); } static int bhnd_pcib_detach(device_t dev) { // TODO return (bhnd_pci_generic_detach(dev)); } static int bhnd_pcib_suspend(device_t dev) { return (bhnd_pci_generic_suspend(dev)); } static int bhnd_pcib_resume(device_t dev) { return (bhnd_pci_generic_resume(dev)); } static device_method_t bhnd_pcib_methods[] = { /* Device interface */ DEVMETHOD(device_attach, bhnd_pcib_attach), DEVMETHOD(device_detach, bhnd_pcib_detach), DEVMETHOD(device_suspend, bhnd_pcib_suspend), DEVMETHOD(device_resume, bhnd_pcib_resume), DEVMETHOD_END }; DEFINE_CLASS_1(bhnd_pcib, bhnd_pcib_driver, bhnd_pcib_methods, sizeof(struct bhnd_pcib_softc), bhnd_pci_driver); DRIVER_MODULE(bhnd_pcib, bhnd, bhnd_pcib_driver, bhnd_hostb_devclass, 0, 0); MODULE_VERSION(bhnd_pcib, 1); +MODULE_DEPEND(bhnd_pcib, bhnd, 1, 1, 1); +MODULE_DEPEND(bhnd_pcib, bhnd_pci, 1, 1, 1); MODULE_DEPEND(bhnd_pcib, pci, 1, 1, 1); -MODULE_DEPEND(bhnd_pcib, bhnd_pci_mdio, 1, 1, 1);