Index: head/sys/boot/arm/at91/bootiic/env_vars.c =================================================================== --- head/sys/boot/arm/at91/bootiic/env_vars.c (revision 298825) +++ head/sys/boot/arm/at91/bootiic/env_vars.c (revision 298826) @@ -1,207 +1,207 @@ /****************************************************************************** * * Filename: env_vars.c * * Instantiation of environment variables, structures, and other globals. * * Revision information: * * 20AUG2004 kb_admin initial creation * * BEGIN_KBDD_BLOCK * No warranty, expressed or implied, is included with this software. It is * provided "AS IS" and no warranty of any kind including statutory or aspects * relating to merchantability or fitness for any purpose is provided. All * intellectual property rights of others is maintained with the respective * owners. This software is not copyrighted and is intended for reference * only. * END_BLOCK * * $FreeBSD$ *****************************************************************************/ #include "env_vars.h" #include "loader_prompt.h" #include "lib.h" /******************************* GLOBALS *************************************/ char boot_commands[MAX_BOOT_COMMANDS][MAX_INPUT_SIZE]; char env_table[MAX_ENV_SIZE_BYTES]; extern char BootCommandSection; /************************** PRIVATE FUNCTIONS ********************************/ static int currentIndex; static int currentOffset; /* * .KB_C_FN_DEFINITION_START * int ReadCharFromEnvironment(char *) - * This private function reads characters from the enviroment variables + * This private function reads characters from the environment variables * to service the command prompt during auto-boot or just to setup the * default environment. Returns positive value if valid character was * set in the pointer. Returns negative value to signal input stream * terminated. Returns 0 to indicate _wait_ condition. * .KB_C_FN_DEFINITION_END */ static int ReadCharFromEnvironment(int timeout) { int ch; if (currentIndex < MAX_BOOT_COMMANDS) { ch = boot_commands[currentIndex][currentOffset++]; if (ch == '\0' || (currentOffset >= MAX_INPUT_SIZE)) { currentOffset = 0; ++currentIndex; ch = '\r'; } return (ch); } return (-1); } /*************************** GLOBAL FUNCTIONS ********************************/ /* * .KB_C_FN_DEFINITION_START * void WriteCommandTable(void) * This global function write the current command table to the non-volatile * memory. * .KB_C_FN_DEFINITION_END */ void WriteCommandTable(void) { int i, size = MAX_ENV_SIZE_BYTES, copySize; char *cPtr = env_table; p_memset(env_table, 0, sizeof(env_table)); for (i = 0; i < MAX_BOOT_COMMANDS; ++i) { copySize = p_strlen(boot_commands[i]); size -= copySize + 1; if (size < 0) { continue; } memcpy(cPtr, boot_commands[i], copySize); cPtr += copySize; *cPtr++ = 0; } /* We're executing in low RAM so addr in ram == offset in eeprom */ WriteEEPROM((unsigned)&BootCommandSection, env_table, sizeof(env_table)); } /* * .KB_C_FN_DEFINITION_START * void SetBootCommand(int index, char *command) * This global function replaces the specified index with the string residing * at command. Execute this function with a NULL string to clear the * associated command index. * .KB_C_FN_DEFINITION_END */ void SetBootCommand(int index, char *command) { int i; if ((unsigned)index < MAX_BOOT_COMMANDS) { p_memset(boot_commands[index], 0, MAX_INPUT_SIZE); if (!command) return ; for (i = 0; i < MAX_INPUT_SIZE; ++i) { boot_commands[index][i] = command[i]; if (!(boot_commands[index][i])) return; } } } /* * .KB_C_FN_DEFINITION_START * void DumpBootCommands(void) * This global function displays the current boot commands. * .KB_C_FN_DEFINITION_END */ void DumpBootCommands(void) { int i, j; for (i = 0; i < MAX_BOOT_COMMANDS; ++i) { printf("0x%x : ", i); for (j = 0; j < MAX_INPUT_SIZE; ++j) { putchar(boot_commands[i][j]); if (!(boot_commands[i][j])) break; } printf("[E]\n\r"); } } /* * .KB_C_FN_DEFINITION_START * void LoadBootCommands(void) * This global function loads the existing boot commands from raw format and * coverts it to the standard, command-index format. Notice, the processed * boot command table has much more space allocated than the actual table * stored in non-volatile memory. This is because the processed table * exists in RAM which is larger than the non-volatile space. * .KB_C_FN_DEFINITION_END */ void LoadBootCommands(void) { int index, j, size; char *cPtr; p_memset((char*)boot_commands, 0, sizeof(boot_commands)); cPtr = &BootCommandSection; size = MAX_ENV_SIZE_BYTES; for (index = 0; (index < MAX_BOOT_COMMANDS) && size; ++index) { for (j = 0; (j < MAX_INPUT_SIZE) && size; ++j) { size--; boot_commands[index][j] = *cPtr++; if (!(boot_commands[index][j])) { break; } } } } /* * .KB_C_FN_DEFINITION_START * void ExecuteEnvironmentFunctions(void) * This global function executes applicable entries in the environment. * .KB_C_FN_DEFINITION_END */ void ExecuteEnvironmentFunctions(void) { currentIndex = 0; currentOffset = 0; DumpBootCommands(); Bootloader(ReadCharFromEnvironment); } Index: head/sys/boot/arm/at91/bootspi/env_vars.c =================================================================== --- head/sys/boot/arm/at91/bootspi/env_vars.c (revision 298825) +++ head/sys/boot/arm/at91/bootspi/env_vars.c (revision 298826) @@ -1,130 +1,130 @@ /****************************************************************************** * * Filename: env_vars.c * * Instantiation of environment variables, structures, and other globals. * * Revision information: * * 20AUG2004 kb_admin initial creation * * BEGIN_KBDD_BLOCK * No warranty, expressed or implied, is included with this software. It is * provided "AS IS" and no warranty of any kind including statutory or aspects * relating to merchantability or fitness for any purpose is provided. All * intellectual property rights of others is maintained with the respective * owners. This software is not copyrighted and is intended for reference * only. * END_BLOCK * * $FreeBSD$ *****************************************************************************/ #include "env_vars.h" #include "loader_prompt.h" #include "lib.h" /******************************* GLOBALS *************************************/ char boot_commands[MAX_BOOT_COMMANDS][MAX_INPUT_SIZE]; char env_table[MAX_ENV_SIZE_BYTES]; extern char BootCommandSection; /************************** PRIVATE FUNCTIONS ********************************/ static int currentIndex; static int currentOffset; /* * .KB_C_FN_DEFINITION_START * int ReadCharFromEnvironment(char *) - * This private function reads characters from the enviroment variables + * This private function reads characters from the environment variables * to service the command prompt during auto-boot or just to setup the * default environment. Returns positive value if valid character was * set in the pointer. Returns negative value to signal input stream * terminated. Returns 0 to indicate _wait_ condition. * .KB_C_FN_DEFINITION_END */ static int ReadCharFromEnvironment(int timeout) { int ch; if (currentIndex < MAX_BOOT_COMMANDS) { ch = boot_commands[currentIndex][currentOffset++]; if (ch == '\0' || (currentOffset >= MAX_INPUT_SIZE)) { currentOffset = 0; ++currentIndex; ch = '\r'; } return (ch); } return (-1); } /*************************** GLOBAL FUNCTIONS ********************************/ /* * .KB_C_FN_DEFINITION_START * void DumpBootCommands(void) * This global function displays the current boot commands. * .KB_C_FN_DEFINITION_END */ void DumpBootCommands(void) { int i; for (i = 0; boot_commands[i][0]; i++) printf("0x%x : %s[E]\n", i, boot_commands[i]); } /* * .KB_C_FN_DEFINITION_START * void LoadBootCommands(void) * This global function loads the existing boot commands from raw format and * coverts it to the standard, command-index format. Notice, the processed * boot command table has much more space allocated than the actual table * stored in non-volatile memory. This is because the processed table * exists in RAM which is larger than the non-volatile space. * .KB_C_FN_DEFINITION_END */ void LoadBootCommands(void) { int index, j; char *cptr; p_memset((char*)boot_commands, 0, sizeof(boot_commands)); cptr = &BootCommandSection; for (index = 0; *cptr; index++) { for (j = 0; *cptr; j++) boot_commands[index][j] = *cptr++; cptr++; } } /* * .KB_C_FN_DEFINITION_START * void ExecuteEnvironmentFunctions(void) * This global function executes applicable entries in the environment. * .KB_C_FN_DEFINITION_END */ void ExecuteEnvironmentFunctions(void) { currentIndex = 0; currentOffset = 0; DumpBootCommands(); printf("Autoboot...\n"); Bootloader(ReadCharFromEnvironment); } Index: head/sys/boot/arm/at91/libat91/at91rm9200.h =================================================================== --- head/sys/boot/arm/at91/libat91/at91rm9200.h (revision 298825) +++ head/sys/boot/arm/at91/libat91/at91rm9200.h (revision 298826) @@ -1,2411 +1,2411 @@ // ---------------------------------------------------------------------------- // ATMEL Microcontroller Software Support - ROUSSET - // ---------------------------------------------------------------------------- // The software is delivered "AS IS" without warranty or condition of any // kind, either express, implied or statutory. This includes without // limitation any warranty or condition with respect to merchantability or // fitness for any particular purpose, or against the infringements of // intellectual property rights of others. // ---------------------------------------------------------------------------- // $FreeBSD$ // // File Name : AT91RM9200.h // Object : AT91RM9200 definitions // Generated : AT91 SW Application Group 07/04/2003 (11:05:04) // // CVS Reference : /AT91RM9200.pl/1.16/Fri Feb 07 09:29:50 2003// // CVS Reference : /SYS_AT91RM9200.pl/1.2/Fri Jan 17 11:44:36 2003// // CVS Reference : /MC_1760A.pl/1.1/Fri Aug 23 13:38:22 2002// // CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 08:36:46 2002// // CVS Reference : /PMC_2636A.pl/1.1.1.1/Fri Jun 28 08:36:48 2002// // CVS Reference : /ST_1763B.pl/1.1/Fri Aug 23 13:41:42 2002// // CVS Reference : /RTC_1245D.pl/1.2/Fri Jan 31 11:19:06 2003// // CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 08:36:46 2002// // CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 11:18:24 2003// // CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 02 13:45:38 2002// // CVS Reference : /MCI_1764A.pl/1.2/Thu Nov 14 16:48:24 2002// // CVS Reference : /US_1739C.pl/1.2/Fri Jul 12 06:49:24 2002// // CVS Reference : /SPI_AT91RMxxxx.pl/1.3/Tue Nov 26 09:20:28 2002// // CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 08 12:26:38 2002// // CVS Reference : /TC_1753B.pl/1.2/Fri Jan 31 11:19:54 2003// // CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 07 09:30:06 2003// // CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 15:38:22 2002// // CVS Reference : /UHP_xxxxA.pl/1.1/Mon Jul 22 11:21:58 2002// // CVS Reference : /EMAC_1794A.pl/1.4/Fri Jan 17 11:11:54 2003// // CVS Reference : /EBI_1759B.pl/1.10/Fri Jan 17 11:44:28 2003// // CVS Reference : /SMC_1783A.pl/1.3/Thu Oct 31 13:38:16 2002// // CVS Reference : /SDRC_1758B.pl/1.2/Thu Oct 03 12:04:40 2002// // CVS Reference : /BFC_1757B.pl/1.3/Thu Oct 31 13:38:00 2002// // ---------------------------------------------------------------------------- #ifndef AT91RM9200_H #define AT91RM9200_H #define ATMEL_ENV typedef volatile unsigned int AT91_REG;// Hardware register definition // ***************************************************************************** // SOFTWARE API DEFINITION FOR System Peripherals // ***************************************************************************** typedef struct _AT91S_SYS { AT91_REG AIC_SMR[32]; // Source Mode Register AT91_REG AIC_SVR[32]; // Source Vector Register AT91_REG AIC_IVR; // IRQ Vector Register AT91_REG AIC_FVR; // FIQ Vector Register AT91_REG AIC_ISR; // Interrupt Status Register AT91_REG AIC_IPR; // Interrupt Pending Register AT91_REG AIC_IMR; // Interrupt Mask Register AT91_REG AIC_CISR; // Core Interrupt Status Register AT91_REG Reserved0[2]; // AT91_REG AIC_IECR; // Interrupt Enable Command Register AT91_REG AIC_IDCR; // Interrupt Disable Command Register AT91_REG AIC_ICCR; // Interrupt Clear Command Register AT91_REG AIC_ISCR; // Interrupt Set Command Register AT91_REG AIC_EOICR; // End of Interrupt Command Register AT91_REG AIC_SPU; // Spurious Vector Register AT91_REG AIC_DCR; // Debug Control Register (Protect) AT91_REG Reserved1[1]; // AT91_REG AIC_FFER; // Fast Forcing Enable Register AT91_REG AIC_FFDR; // Fast Forcing Disable Register AT91_REG AIC_FFSR; // Fast Forcing Status Register AT91_REG Reserved2[45]; // AT91_REG DBGU_CR; // Control Register AT91_REG DBGU_MR; // Mode Register AT91_REG DBGU_IER; // Interrupt Enable Register AT91_REG DBGU_IDR; // Interrupt Disable Register AT91_REG DBGU_IMR; // Interrupt Mask Register AT91_REG DBGU_CSR; // Channel Status Register AT91_REG DBGU_RHR; // Receiver Holding Register AT91_REG DBGU_THR; // Transmitter Holding Register AT91_REG DBGU_BRGR; // Baud Rate Generator Register AT91_REG Reserved3[7]; // AT91_REG DBGU_C1R; // Chip ID1 Register AT91_REG DBGU_C2R; // Chip ID2 Register AT91_REG DBGU_FNTR; // Force NTRST Register AT91_REG Reserved4[45]; // AT91_REG DBGU_RPR; // Receive Pointer Register AT91_REG DBGU_RCR; // Receive Counter Register AT91_REG DBGU_TPR; // Transmit Pointer Register AT91_REG DBGU_TCR; // Transmit Counter Register AT91_REG DBGU_RNPR; // Receive Next Pointer Register AT91_REG DBGU_RNCR; // Receive Next Counter Register AT91_REG DBGU_TNPR; // Transmit Next Pointer Register AT91_REG DBGU_TNCR; // Transmit Next Counter Register AT91_REG DBGU_PTCR; // PDC Transfer Control Register AT91_REG DBGU_PTSR; // PDC Transfer Status Register AT91_REG Reserved5[54]; // AT91_REG PIOA_PER; // PIO Enable Register AT91_REG PIOA_PDR; // PIO Disable Register AT91_REG PIOA_PSR; // PIO Status Register AT91_REG Reserved6[1]; // AT91_REG PIOA_OER; // Output Enable Register AT91_REG PIOA_ODR; // Output Disable Registerr AT91_REG PIOA_OSR; // Output Status Register AT91_REG Reserved7[1]; // AT91_REG PIOA_IFER; // Input Filter Enable Register AT91_REG PIOA_IFDR; // Input Filter Disable Register AT91_REG PIOA_IFSR; // Input Filter Status Register AT91_REG Reserved8[1]; // AT91_REG PIOA_SODR; // Set Output Data Register AT91_REG PIOA_CODR; // Clear Output Data Register AT91_REG PIOA_ODSR; // Output Data Status Register AT91_REG PIOA_PDSR; // Pin Data Status Register AT91_REG PIOA_IER; // Interrupt Enable Register AT91_REG PIOA_IDR; // Interrupt Disable Register AT91_REG PIOA_IMR; // Interrupt Mask Register AT91_REG PIOA_ISR; // Interrupt Status Register AT91_REG PIOA_MDER; // Multi-driver Enable Register AT91_REG PIOA_MDDR; // Multi-driver Disable Register AT91_REG PIOA_MDSR; // Multi-driver Status Register AT91_REG Reserved9[1]; // AT91_REG PIOA_PPUDR; // Pull-up Disable Register AT91_REG PIOA_PPUER; // Pull-up Enable Register AT91_REG PIOA_PPUSR; // Pad Pull-up Status Register AT91_REG Reserved10[1]; // AT91_REG PIOA_ASR; // Select A Register AT91_REG PIOA_BSR; // Select B Register AT91_REG PIOA_ABSR; // AB Select Status Register AT91_REG Reserved11[9]; // AT91_REG PIOA_OWER; // Output Write Enable Register AT91_REG PIOA_OWDR; // Output Write Disable Register AT91_REG PIOA_OWSR; // Output Write Status Register AT91_REG Reserved12[85]; // AT91_REG PIOB_PER; // PIO Enable Register AT91_REG PIOB_PDR; // PIO Disable Register AT91_REG PIOB_PSR; // PIO Status Register AT91_REG Reserved13[1]; // AT91_REG PIOB_OER; // Output Enable Register AT91_REG PIOB_ODR; // Output Disable Registerr AT91_REG PIOB_OSR; // Output Status Register AT91_REG Reserved14[1]; // AT91_REG PIOB_IFER; // Input Filter Enable Register AT91_REG PIOB_IFDR; // Input Filter Disable Register AT91_REG PIOB_IFSR; // Input Filter Status Register AT91_REG Reserved15[1]; // AT91_REG PIOB_SODR; // Set Output Data Register AT91_REG PIOB_CODR; // Clear Output Data Register AT91_REG PIOB_ODSR; // Output Data Status Register AT91_REG PIOB_PDSR; // Pin Data Status Register AT91_REG PIOB_IER; // Interrupt Enable Register AT91_REG PIOB_IDR; // Interrupt Disable Register AT91_REG PIOB_IMR; // Interrupt Mask Register AT91_REG PIOB_ISR; // Interrupt Status Register AT91_REG PIOB_MDER; // Multi-driver Enable Register AT91_REG PIOB_MDDR; // Multi-driver Disable Register AT91_REG PIOB_MDSR; // Multi-driver Status Register AT91_REG Reserved16[1]; // AT91_REG PIOB_PPUDR; // Pull-up Disable Register AT91_REG PIOB_PPUER; // Pull-up Enable Register AT91_REG PIOB_PPUSR; // Pad Pull-up Status Register AT91_REG Reserved17[1]; // AT91_REG PIOB_ASR; // Select A Register AT91_REG PIOB_BSR; // Select B Register AT91_REG PIOB_ABSR; // AB Select Status Register AT91_REG Reserved18[9]; // AT91_REG PIOB_OWER; // Output Write Enable Register AT91_REG PIOB_OWDR; // Output Write Disable Register AT91_REG PIOB_OWSR; // Output Write Status Register AT91_REG Reserved19[85]; // AT91_REG PIOC_PER; // PIO Enable Register AT91_REG PIOC_PDR; // PIO Disable Register AT91_REG PIOC_PSR; // PIO Status Register AT91_REG Reserved20[1]; // AT91_REG PIOC_OER; // Output Enable Register AT91_REG PIOC_ODR; // Output Disable Registerr AT91_REG PIOC_OSR; // Output Status Register AT91_REG Reserved21[1]; // AT91_REG PIOC_IFER; // Input Filter Enable Register AT91_REG PIOC_IFDR; // Input Filter Disable Register AT91_REG PIOC_IFSR; // Input Filter Status Register AT91_REG Reserved22[1]; // AT91_REG PIOC_SODR; // Set Output Data Register AT91_REG PIOC_CODR; // Clear Output Data Register AT91_REG PIOC_ODSR; // Output Data Status Register AT91_REG PIOC_PDSR; // Pin Data Status Register AT91_REG PIOC_IER; // Interrupt Enable Register AT91_REG PIOC_IDR; // Interrupt Disable Register AT91_REG PIOC_IMR; // Interrupt Mask Register AT91_REG PIOC_ISR; // Interrupt Status Register AT91_REG PIOC_MDER; // Multi-driver Enable Register AT91_REG PIOC_MDDR; // Multi-driver Disable Register AT91_REG PIOC_MDSR; // Multi-driver Status Register AT91_REG Reserved23[1]; // AT91_REG PIOC_PPUDR; // Pull-up Disable Register AT91_REG PIOC_PPUER; // Pull-up Enable Register AT91_REG PIOC_PPUSR; // Pad Pull-up Status Register AT91_REG Reserved24[1]; // AT91_REG PIOC_ASR; // Select A Register AT91_REG PIOC_BSR; // Select B Register AT91_REG PIOC_ABSR; // AB Select Status Register AT91_REG Reserved25[9]; // AT91_REG PIOC_OWER; // Output Write Enable Register AT91_REG PIOC_OWDR; // Output Write Disable Register AT91_REG PIOC_OWSR; // Output Write Status Register AT91_REG Reserved26[85]; // AT91_REG PIOD_PER; // PIO Enable Register AT91_REG PIOD_PDR; // PIO Disable Register AT91_REG PIOD_PSR; // PIO Status Register AT91_REG Reserved27[1]; // AT91_REG PIOD_OER; // Output Enable Register AT91_REG PIOD_ODR; // Output Disable Registerr AT91_REG PIOD_OSR; // Output Status Register AT91_REG Reserved28[1]; // AT91_REG PIOD_IFER; // Input Filter Enable Register AT91_REG PIOD_IFDR; // Input Filter Disable Register AT91_REG PIOD_IFSR; // Input Filter Status Register AT91_REG Reserved29[1]; // AT91_REG PIOD_SODR; // Set Output Data Register AT91_REG PIOD_CODR; // Clear Output Data Register AT91_REG PIOD_ODSR; // Output Data Status Register AT91_REG PIOD_PDSR; // Pin Data Status Register AT91_REG PIOD_IER; // Interrupt Enable Register AT91_REG PIOD_IDR; // Interrupt Disable Register AT91_REG PIOD_IMR; // Interrupt Mask Register AT91_REG PIOD_ISR; // Interrupt Status Register AT91_REG PIOD_MDER; // Multi-driver Enable Register AT91_REG PIOD_MDDR; // Multi-driver Disable Register AT91_REG PIOD_MDSR; // Multi-driver Status Register AT91_REG Reserved30[1]; // AT91_REG PIOD_PPUDR; // Pull-up Disable Register AT91_REG PIOD_PPUER; // Pull-up Enable Register AT91_REG PIOD_PPUSR; // Pad Pull-up Status Register AT91_REG Reserved31[1]; // AT91_REG PIOD_ASR; // Select A Register AT91_REG PIOD_BSR; // Select B Register AT91_REG PIOD_ABSR; // AB Select Status Register AT91_REG Reserved32[9]; // AT91_REG PIOD_OWER; // Output Write Enable Register AT91_REG PIOD_OWDR; // Output Write Disable Register AT91_REG PIOD_OWSR; // Output Write Status Register AT91_REG Reserved33[85]; // AT91_REG PMC_SCER; // System Clock Enable Register AT91_REG PMC_SCDR; // System Clock Disable Register AT91_REG PMC_SCSR; // System Clock Status Register AT91_REG Reserved34[1]; // AT91_REG PMC_PCER; // Peripheral Clock Enable Register AT91_REG PMC_PCDR; // Peripheral Clock Disable Register AT91_REG PMC_PCSR; // Peripheral Clock Status Register AT91_REG Reserved35[1]; // AT91_REG CKGR_MOR; // Main Oscillator Register AT91_REG CKGR_MCFR; // Main Clock Frequency Register AT91_REG CKGR_PLLAR; // PLL A Register AT91_REG CKGR_PLLBR; // PLL B Register AT91_REG PMC_MCKR; // Master Clock Register AT91_REG Reserved36[3]; // AT91_REG PMC_PCKR[8]; // Programmable Clock Register AT91_REG PMC_IER; // Interrupt Enable Register AT91_REG PMC_IDR; // Interrupt Disable Register AT91_REG PMC_SR; // Status Register AT91_REG PMC_IMR; // Interrupt Mask Register AT91_REG Reserved37[36]; // AT91_REG ST_CR; // Control Register AT91_REG ST_PIMR; // Period Interval Mode Register AT91_REG ST_WDMR; // Watchdog Mode Register AT91_REG ST_RTMR; // Real-time Mode Register AT91_REG ST_SR; // Status Register AT91_REG ST_IER; // Interrupt Enable Register AT91_REG ST_IDR; // Interrupt Disable Register AT91_REG ST_IMR; // Interrupt Mask Register AT91_REG ST_RTAR; // Real-time Alarm Register AT91_REG ST_CRTR; // Current Real-time Register AT91_REG Reserved38[54]; // AT91_REG RTC_CR; // Control Register AT91_REG RTC_MR; // Mode Register AT91_REG RTC_TIMR; // Time Register AT91_REG RTC_CALR; // Calendar Register AT91_REG RTC_TIMALR; // Time Alarm Register AT91_REG RTC_CALALR; // Calendar Alarm Register AT91_REG RTC_SR; // Status Register AT91_REG RTC_SCCR; // Status Clear Command Register AT91_REG RTC_IER; // Interrupt Enable Register AT91_REG RTC_IDR; // Interrupt Disable Register AT91_REG RTC_IMR; // Interrupt Mask Register AT91_REG RTC_VER; // Valid Entry Register AT91_REG Reserved39[52]; // AT91_REG MC_RCR; // MC Remap Control Register AT91_REG MC_ASR; // MC Abort Status Register AT91_REG MC_AASR; // MC Abort Address Status Register AT91_REG Reserved40[1]; // AT91_REG MC_PUIA[16]; // MC Protection Unit Area AT91_REG MC_PUP; // MC Protection Unit Peripherals AT91_REG MC_PUER; // MC Protection Unit Enable Register AT91_REG Reserved41[2]; // AT91_REG EBI_CSA; // Chip Select Assignment Register AT91_REG EBI_CFGR; // Configuration Register AT91_REG Reserved42[2]; // AT91_REG EBI_SMC2_CSR[8]; // SMC2 Chip Select Register AT91_REG EBI_SDRC_MR; // SDRAM Controller Mode Register AT91_REG EBI_SDRC_TR; // SDRAM Controller Refresh Timer Register AT91_REG EBI_SDRC_CR; // SDRAM Controller Configuration Register AT91_REG EBI_SDRC_SRR; // SDRAM Controller Self Refresh Register AT91_REG EBI_SDRC_LPR; // SDRAM Controller Low Power Register AT91_REG EBI_SDRC_IER; // SDRAM Controller Interrupt Enable Register AT91_REG EBI_SDRC_IDR; // SDRAM Controller Interrupt Disable Register AT91_REG EBI_SDRC_IMR; // SDRAM Controller Interrupt Mask Register AT91_REG EBI_SDRC_ISR; // SDRAM Controller Interrupt Mask Register AT91_REG Reserved43[3]; // AT91_REG EBI_BFC_MR; // BFC Mode Register } AT91S_SYS, *AT91PS_SYS; // ***************************************************************************** // SOFTWARE API DEFINITION FOR Memory Controller Interface // ***************************************************************************** typedef struct _AT91S_MC { AT91_REG MC_RCR; // MC Remap Control Register AT91_REG MC_ASR; // MC Abort Status Register AT91_REG MC_AASR; // MC Abort Address Status Register AT91_REG Reserved0[1]; // AT91_REG MC_PUIA[16]; // MC Protection Unit Area AT91_REG MC_PUP; // MC Protection Unit Peripherals AT91_REG MC_PUER; // MC Protection Unit Enable Register } AT91S_MC, *AT91PS_MC; // -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- #define AT91C_MC_RCB (0x1u << 0) // (MC) Remap Command Bit // -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- #define AT91C_MC_UNDADD (0x1u << 0) // (MC) Undefined Addess Abort Status #define AT91C_MC_MISADD (0x1u << 1) // (MC) Misaligned Addess Abort Status #define AT91C_MC_MPU (0x1u << 2) // (MC) Memory protection Unit Abort Status #define AT91C_MC_ABTSZ (0x3u << 8) // (MC) Abort Size Status #define AT91C_MC_ABTSZ_BYTE (0x0u << 8) // (MC) Byte #define AT91C_MC_ABTSZ_HWORD (0x1u << 8) // (MC) Half-word #define AT91C_MC_ABTSZ_WORD (0x2u << 8) // (MC) Word #define AT91C_MC_ABTTYP (0x3u << 10) // (MC) Abort Type Status #define AT91C_MC_ABTTYP_DATAR (0x0u << 10) // (MC) Data Read #define AT91C_MC_ABTTYP_DATAW (0x1u << 10) // (MC) Data Write #define AT91C_MC_ABTTYP_FETCH (0x2u << 10) // (MC) Code Fetch #define AT91C_MC_MST0 (0x1u << 16) // (MC) Master 0 Abort Source #define AT91C_MC_MST1 (0x1u << 17) // (MC) Master 1 Abort Source #define AT91C_MC_SVMST0 (0x1u << 24) // (MC) Saved Master 0 Abort Source #define AT91C_MC_SVMST1 (0x1u << 25) // (MC) Saved Master 1 Abort Source // -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- #define AT91C_MC_PROT (0x3u << 0) // (MC) Protection #define AT91C_MC_PROT_PNAUNA 0x0u // (MC) Privilege: No Access, User: No Access #define AT91C_MC_PROT_PRWUNA 0x1u // (MC) Privilege: Read/Write, User: No Access #define AT91C_MC_PROT_PRWURO 0x2u // (MC) Privilege: Read/Write, User: Read Only #define AT91C_MC_PROT_PRWURW 0x3u // (MC) Privilege: Read/Write, User: Read/Write #define AT91C_MC_SIZE (0xFu << 4) // (MC) Internal Area Size #define AT91C_MC_SIZE_1KB (0x0u << 4) // (MC) Area size 1KByte #define AT91C_MC_SIZE_2KB (0x1u << 4) // (MC) Area size 2KByte #define AT91C_MC_SIZE_4KB (0x2u << 4) // (MC) Area size 4KByte #define AT91C_MC_SIZE_8KB (0x3u << 4) // (MC) Area size 8KByte #define AT91C_MC_SIZE_16KB (0x4u << 4) // (MC) Area size 16KByte #define AT91C_MC_SIZE_32KB (0x5u << 4) // (MC) Area size 32KByte #define AT91C_MC_SIZE_64KB (0x6u << 4) // (MC) Area size 64KByte #define AT91C_MC_SIZE_128KB (0x7u << 4) // (MC) Area size 128KByte #define AT91C_MC_SIZE_256KB (0x8u << 4) // (MC) Area size 256KByte #define AT91C_MC_SIZE_512KB (0x9u << 4) // (MC) Area size 512KByte #define AT91C_MC_SIZE_1MB (0xAu << 4) // (MC) Area size 1MByte #define AT91C_MC_SIZE_2MB (0xBu << 4) // (MC) Area size 2MByte #define AT91C_MC_SIZE_4MB (0xCu << 4) // (MC) Area size 4MByte #define AT91C_MC_SIZE_8MB (0xDu << 4) // (MC) Area size 8MByte #define AT91C_MC_SIZE_16MB (0xEu << 4) // (MC) Area size 16MByte #define AT91C_MC_SIZE_64MB (0xFu << 4) // (MC) Area size 64MByte #define AT91C_MC_BA (0x3FFFFu << 10) // (MC) Internal Area Base Address // -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- // -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- #define AT91C_MC_PUEB (0x1u << 0) // (MC) Protection Unit enable Bit // ***************************************************************************** // SOFTWARE API DEFINITION FOR Real-time Clock Alarm and Parallel Load Interface // ***************************************************************************** typedef struct _AT91S_RTC { AT91_REG RTC_CR; // Control Register AT91_REG RTC_MR; // Mode Register AT91_REG RTC_TIMR; // Time Register AT91_REG RTC_CALR; // Calendar Register AT91_REG RTC_TIMALR; // Time Alarm Register AT91_REG RTC_CALALR; // Calendar Alarm Register AT91_REG RTC_SR; // Status Register AT91_REG RTC_SCCR; // Status Clear Command Register AT91_REG RTC_IER; // Interrupt Enable Register AT91_REG RTC_IDR; // Interrupt Disable Register AT91_REG RTC_IMR; // Interrupt Mask Register AT91_REG RTC_VER; // Valid Entry Register } AT91S_RTC, *AT91PS_RTC; // -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- #define AT91C_RTC_UPDTIM (0x1u << 0) // (RTC) Update Request Time Register #define AT91C_RTC_UPDCAL (0x1u << 1) // (RTC) Update Request Calendar Register #define AT91C_RTC_TIMEVSEL (0x3u << 8) // (RTC) Time Event Selection #define AT91C_RTC_TIMEVSEL_MINUTE (0x0u << 8) // (RTC) Minute change. #define AT91C_RTC_TIMEVSEL_HOUR (0x1u << 8) // (RTC) Hour change. #define AT91C_RTC_TIMEVSEL_DAY24 (0x2u << 8) // (RTC) Every day at midnight. #define AT91C_RTC_TIMEVSEL_DAY12 (0x3u << 8) // (RTC) Every day at noon. #define AT91C_RTC_CALEVSEL (0x3u << 16) // (RTC) Calendar Event Selection #define AT91C_RTC_CALEVSEL_WEEK (0x0u << 16) // (RTC) Week change (every Monday at time 00:00:00). #define AT91C_RTC_CALEVSEL_MONTH (0x1u << 16) // (RTC) Month change (every 01 of each month at time 00:00:00). #define AT91C_RTC_CALEVSEL_YEAR (0x2u << 16) // (RTC) Year change (every January 1 at time 00:00:00). // -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- #define AT91C_RTC_HRMOD (0x1u << 0) // (RTC) 12-24 hour Mode // -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- #define AT91C_RTC_SEC (0x7Fu << 0) // (RTC) Current Second #define AT91C_RTC_MIN (0x7Fu << 8) // (RTC) Current Minute #define AT91C_RTC_HOUR (0x1Fu << 16) // (RTC) Current Hour #define AT91C_RTC_AMPM (0x1u << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator // -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- #define AT91C_RTC_CENT (0x3Fu << 0) // (RTC) Current Century #define AT91C_RTC_YEAR (0xFFu << 8) // (RTC) Current Year #define AT91C_RTC_MONTH (0x1Fu << 16) // (RTC) Current Month #define AT91C_RTC_DAY (0x7u << 21) // (RTC) Current Day #define AT91C_RTC_DATE (0x3Fu << 24) // (RTC) Current Date // -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- #define AT91C_RTC_SECEN (0x1u << 7) // (RTC) Second Alarm Enable #define AT91C_RTC_MINEN (0x1u << 15) // (RTC) Minute Alarm #define AT91C_RTC_HOUREN (0x1u << 23) // (RTC) Current Hour // -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- #define AT91C_RTC_MONTHEN (0x1u << 23) // (RTC) Month Alarm Enable #define AT91C_RTC_DATEEN (0x1u << 31) // (RTC) Date Alarm Enable // -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- #define AT91C_RTC_ACKUPD (0x1u << 0) // (RTC) Acknowledge for Update #define AT91C_RTC_ALARM (0x1u << 1) // (RTC) Alarm Flag #define AT91C_RTC_SECEV (0x1u << 2) // (RTC) Second Event #define AT91C_RTC_TIMEV (0x1u << 3) // (RTC) Time Event #define AT91C_RTC_CALEV (0x1u << 4) // (RTC) Calendar event // -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- // -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- // -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- // -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- // -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- #define AT91C_RTC_NVTIM (0x1u << 0) // (RTC) Non valid Time #define AT91C_RTC_NVCAL (0x1u << 1) // (RTC) Non valid Calendar #define AT91C_RTC_NVTIMALR (0x1u << 2) // (RTC) Non valid time Alarm #define AT91C_RTC_NVCALALR (0x1u << 3) // (RTC) Nonvalid Calendar Alarm // ***************************************************************************** // SOFTWARE API DEFINITION FOR System Timer Interface // ***************************************************************************** typedef struct _AT91S_ST { AT91_REG ST_CR; // Control Register AT91_REG ST_PIMR; // Period Interval Mode Register AT91_REG ST_WDMR; // Watchdog Mode Register AT91_REG ST_RTMR; // Real-time Mode Register AT91_REG ST_SR; // Status Register AT91_REG ST_IER; // Interrupt Enable Register AT91_REG ST_IDR; // Interrupt Disable Register AT91_REG ST_IMR; // Interrupt Mask Register AT91_REG ST_RTAR; // Real-time Alarm Register AT91_REG ST_CRTR; // Current Real-time Register } AT91S_ST, *AT91PS_ST; // -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- #define AT91C_ST_WDRST (0x1u << 0) // (ST) Watchdog Timer Restart // -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- #define AT91C_ST_PIV (0xFFFFu << 0) // (ST) Watchdog Timer Restart // -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- #define AT91C_ST_WDV (0xFFFFu << 0) // (ST) Watchdog Timer Restart #define AT91C_ST_RSTEN (0x1u << 16) // (ST) Reset Enable #define AT91C_ST_EXTEN (0x1u << 17) // (ST) External Signal Assertion Enable // -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- #define AT91C_ST_RTPRES (0xFFFFu << 0) // (ST) Real-time Timer Prescaler Value // -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- #define AT91C_ST_PITS (0x1u << 0) // (ST) Period Interval Timer Interrupt #define AT91C_ST_WDOVF (0x1u << 1) // (ST) Watchdog Overflow #define AT91C_ST_RTTINC (0x1u << 2) // (ST) Real-time Timer Increment #define AT91C_ST_ALMS (0x1u << 3) // (ST) Alarm Status // -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- // -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- // -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- // -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- #define AT91C_ST_ALMV (0xFFFFFu << 0) // (ST) Alarm Value Value // -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- #define AT91C_ST_CRTV (0xFFFFFu << 0) // (ST) Current Real-time Value // ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler +// SOFTWARE API DEFINITION FOR Power Management Controller // ***************************************************************************** typedef struct _AT91S_PMC { AT91_REG PMC_SCER; // System Clock Enable Register AT91_REG PMC_SCDR; // System Clock Disable Register AT91_REG PMC_SCSR; // System Clock Status Register AT91_REG Reserved0[1]; // AT91_REG PMC_PCER; // Peripheral Clock Enable Register AT91_REG PMC_PCDR; // Peripheral Clock Disable Register AT91_REG PMC_PCSR; // Peripheral Clock Status Register AT91_REG Reserved1[5]; // AT91_REG PMC_MCKR; // Master Clock Register AT91_REG Reserved2[3]; // AT91_REG PMC_PCKR[8]; // Programmable Clock Register AT91_REG PMC_IER; // Interrupt Enable Register AT91_REG PMC_IDR; // Interrupt Disable Register AT91_REG PMC_SR; // Status Register AT91_REG PMC_IMR; // Interrupt Mask Register } AT91S_PMC, *AT91PS_PMC; // -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- #define AT91C_PMC_PCK (0x1u << 0) // (PMC) Processor Clock #define AT91C_PMC_UDP (0x1u << 1) // (PMC) USB Device Port Clock #define AT91C_PMC_MCKUDP (0x1u << 2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend #define AT91C_PMC_UHP (0x1u << 4) // (PMC) USB Host Port Clock #define AT91C_PMC_PCK0 (0x1u << 8) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK1 (0x1u << 9) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK2 (0x1u << 10) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK3 (0x1u << 11) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK4 (0x1u << 12) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK5 (0x1u << 13) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK6 (0x1u << 14) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK7 (0x1u << 15) // (PMC) Programmable Clock Output // -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- #define AT91C_PMC_CSS (0x3u << 0) // (PMC) Programmable Clock Selection #define AT91C_PMC_CSS_SLOW_CLK 0x0u // (PMC) Slow Clock is selected #define AT91C_PMC_CSS_MAIN_CLK 0x1u // (PMC) Main Clock is selected #define AT91C_PMC_CSS_PLLA_CLK 0x2u // (PMC) Clock from PLL A is selected #define AT91C_PMC_CSS_PLLB_CLK 0x3u // (PMC) Clock from PLL B is selected #define AT91C_PMC_PRES (0x7u << 2) // (PMC) Programmable Clock Prescaler #define AT91C_PMC_PRES_CLK (0x0u << 2) // (PMC) Selected clock #define AT91C_PMC_PRES_CLK_2 (0x1u << 2) // (PMC) Selected clock divided by 2 #define AT91C_PMC_PRES_CLK_4 (0x2u << 2) // (PMC) Selected clock divided by 4 #define AT91C_PMC_PRES_CLK_8 (0x3u << 2) // (PMC) Selected clock divided by 8 #define AT91C_PMC_PRES_CLK_16 (0x4u << 2) // (PMC) Selected clock divided by 16 #define AT91C_PMC_PRES_CLK_32 (0x5u << 2) // (PMC) Selected clock divided by 32 #define AT91C_PMC_PRES_CLK_64 (0x6u << 2) // (PMC) Selected clock divided by 64 #define AT91C_PMC_MDIV (0x3u << 8) // (PMC) Master Clock Division #define AT91C_PMC_MDIV_1 (0x0u << 8) // (PMC) The master clock and the processor clock are the same #define AT91C_PMC_MDIV_2 (0x1u << 8) // (PMC) The processor clock is twice as fast as the master clock #define AT91C_PMC_MDIV_3 (0x2u << 8) // (PMC) The processor clock is three times faster than the master clock #define AT91C_PMC_MDIV_4 (0x3u << 8) // (PMC) The processor clock is four times faster than the master clock // -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- #define AT91C_PMC_MOSCS (0x1u << 0) // (PMC) MOSC Status/Enable/Disable/Mask #define AT91C_PMC_LOCKA (0x1u << 1) // (PMC) PLL A Status/Enable/Disable/Mask #define AT91C_PMC_LOCKB (0x1u << 2) // (PMC) PLL B Status/Enable/Disable/Mask #define AT91C_PMC_MCKRDY (0x1u << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK0RDY (0x1u << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK1RDY (0x1u << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK2RDY (0x1u << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK3RDY (0x1u << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK4RDY (0x1u << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK5RDY (0x1u << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK6RDY (0x1u << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK7RDY (0x1u << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask // -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- // ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler +// SOFTWARE API DEFINITION FOR Clock Generator Controller // ***************************************************************************** typedef struct _AT91S_CKGR { AT91_REG CKGR_MOR; // Main Oscillator Register AT91_REG CKGR_MCFR; // Main Clock Frequency Register AT91_REG CKGR_PLLAR; // PLL A Register AT91_REG CKGR_PLLBR; // PLL B Register } AT91S_CKGR, *AT91PS_CKGR; // -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- #define AT91C_CKGR_MOSCEN (0x1u << 0) // (CKGR) Main Oscillator Enable #define AT91C_CKGR_OSCTEST (0x1u << 1) // (CKGR) Oscillator Test #define AT91C_CKGR_OSCOUNT (0xFFu << 8) // (CKGR) Main Oscillator Start-up Time // -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- #define AT91C_CKGR_MAINF (0xFFFFu << 0) // (CKGR) Main Clock Frequency #define AT91C_CKGR_MAINRDY (0x1u << 16) // (CKGR) Main Clock Ready // -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- #define AT91C_CKGR_DIVA (0xFFu << 0) // (CKGR) Divider Selected #define AT91C_CKGR_DIVA_0 0x0u // (CKGR) Divider output is 0 #define AT91C_CKGR_DIVA_BYPASS 0x1u // (CKGR) Divider is bypassed #define AT91C_CKGR_PLLACOUNT (0x3Fu << 8) // (CKGR) PLL A Counter #define AT91C_CKGR_OUTA (0x3u << 14) // (CKGR) PLL A Output Frequency Range #define AT91C_CKGR_OUTA_0 (0x0u << 14) // (CKGR) Please refer to the PLLA datasheet #define AT91C_CKGR_OUTA_1 (0x1u << 14) // (CKGR) Please refer to the PLLA datasheet #define AT91C_CKGR_OUTA_2 (0x2u << 14) // (CKGR) Please refer to the PLLA datasheet #define AT91C_CKGR_OUTA_3 (0x3u << 14) // (CKGR) Please refer to the PLLA datasheet #define AT91C_CKGR_MULA (0x7FFu << 16) // (CKGR) PLL A Multiplier #define AT91C_CKGR_SRCA (0x1u << 29) // (CKGR) PLL A Source // -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- #define AT91C_CKGR_DIVB (0xFFu << 0) // (CKGR) Divider Selected #define AT91C_CKGR_DIVB_0 0x0u // (CKGR) Divider output is 0 #define AT91C_CKGR_DIVB_BYPASS 0x1u // (CKGR) Divider is bypassed #define AT91C_CKGR_PLLBCOUNT (0x3Fu << 8) // (CKGR) PLL B Counter #define AT91C_CKGR_OUTB (0x3u << 14) // (CKGR) PLL B Output Frequency Range #define AT91C_CKGR_OUTB_0 (0x0u << 14) // (CKGR) Please refer to the PLLB datasheet #define AT91C_CKGR_OUTB_1 (0x1u << 14) // (CKGR) Please refer to the PLLB datasheet #define AT91C_CKGR_OUTB_2 (0x2u << 14) // (CKGR) Please refer to the PLLB datasheet #define AT91C_CKGR_OUTB_3 (0x3u << 14) // (CKGR) Please refer to the PLLB datasheet #define AT91C_CKGR_MULB (0x7FFu << 16) // (CKGR) PLL B Multiplier #define AT91C_CKGR_USB_96M (0x1u << 28) // (CKGR) Divider for USB Ports #define AT91C_CKGR_USB_PLL (0x1u << 29) // (CKGR) PLL Use // ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// SOFTWARE API DEFINITION FOR Parallel Input Output Controller // ***************************************************************************** typedef struct _AT91S_PIO { AT91_REG PIO_PER; // PIO Enable Register AT91_REG PIO_PDR; // PIO Disable Register AT91_REG PIO_PSR; // PIO Status Register AT91_REG Reserved0[1]; // AT91_REG PIO_OER; // Output Enable Register AT91_REG PIO_ODR; // Output Disable Registerr AT91_REG PIO_OSR; // Output Status Register AT91_REG Reserved1[1]; // AT91_REG PIO_IFER; // Input Filter Enable Register AT91_REG PIO_IFDR; // Input Filter Disable Register AT91_REG PIO_IFSR; // Input Filter Status Register AT91_REG Reserved2[1]; // AT91_REG PIO_SODR; // Set Output Data Register AT91_REG PIO_CODR; // Clear Output Data Register AT91_REG PIO_ODSR; // Output Data Status Register AT91_REG PIO_PDSR; // Pin Data Status Register AT91_REG PIO_IER; // Interrupt Enable Register AT91_REG PIO_IDR; // Interrupt Disable Register AT91_REG PIO_IMR; // Interrupt Mask Register AT91_REG PIO_ISR; // Interrupt Status Register AT91_REG PIO_MDER; // Multi-driver Enable Register AT91_REG PIO_MDDR; // Multi-driver Disable Register AT91_REG PIO_MDSR; // Multi-driver Status Register AT91_REG Reserved3[1]; // AT91_REG PIO_PPUDR; // Pull-up Disable Register AT91_REG PIO_PPUER; // Pull-up Enable Register AT91_REG PIO_PPUSR; // Pad Pull-up Status Register AT91_REG Reserved4[1]; // AT91_REG PIO_ASR; // Select A Register AT91_REG PIO_BSR; // Select B Register AT91_REG PIO_ABSR; // AB Select Status Register AT91_REG Reserved5[9]; // AT91_REG PIO_OWER; // Output Write Enable Register AT91_REG PIO_OWDR; // Output Write Disable Register AT91_REG PIO_OWSR; // Output Write Status Register } AT91S_PIO, *AT91PS_PIO; // ***************************************************************************** // SOFTWARE API DEFINITION FOR Debug Unit // ***************************************************************************** typedef struct _AT91S_DBGU { AT91_REG DBGU_CR; // Control Register AT91_REG DBGU_MR; // Mode Register AT91_REG DBGU_IER; // Interrupt Enable Register AT91_REG DBGU_IDR; // Interrupt Disable Register AT91_REG DBGU_IMR; // Interrupt Mask Register AT91_REG DBGU_CSR; // Channel Status Register AT91_REG DBGU_RHR; // Receiver Holding Register AT91_REG DBGU_THR; // Transmitter Holding Register AT91_REG DBGU_BRGR; // Baud Rate Generator Register AT91_REG Reserved0[7]; // AT91_REG DBGU_C1R; // Chip ID1 Register AT91_REG DBGU_C2R; // Chip ID2 Register AT91_REG DBGU_FNTR; // Force NTRST Register AT91_REG Reserved1[45]; // AT91_REG DBGU_RPR; // Receive Pointer Register AT91_REG DBGU_RCR; // Receive Counter Register AT91_REG DBGU_TPR; // Transmit Pointer Register AT91_REG DBGU_TCR; // Transmit Counter Register AT91_REG DBGU_RNPR; // Receive Next Pointer Register AT91_REG DBGU_RNCR; // Receive Next Counter Register AT91_REG DBGU_TNPR; // Transmit Next Pointer Register AT91_REG DBGU_TNCR; // Transmit Next Counter Register AT91_REG DBGU_PTCR; // PDC Transfer Control Register AT91_REG DBGU_PTSR; // PDC Transfer Status Register } AT91S_DBGU, *AT91PS_DBGU; // -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- #define AT91C_US_RSTRX (0x1u << 2) // (DBGU) Reset Receiver #define AT91C_US_RSTTX (0x1u << 3) // (DBGU) Reset Transmitter #define AT91C_US_RXEN (0x1u << 4) // (DBGU) Receiver Enable #define AT91C_US_RXDIS (0x1u << 5) // (DBGU) Receiver Disable #define AT91C_US_TXEN (0x1u << 6) // (DBGU) Transmitter Enable #define AT91C_US_TXDIS (0x1u << 7) // (DBGU) Transmitter Disable // -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- #define AT91C_US_PAR (0x7u << 9) // (DBGU) Parity type #define AT91C_US_PAR_EVEN (0x0u << 9) // (DBGU) Even Parity #define AT91C_US_PAR_ODD (0x1u << 9) // (DBGU) Odd Parity #define AT91C_US_PAR_SPACE (0x2u << 9) // (DBGU) Parity forced to 0 (Space) #define AT91C_US_PAR_MARK (0x3u << 9) // (DBGU) Parity forced to 1 (Mark) #define AT91C_US_PAR_NONE (0x4u << 9) // (DBGU) No Parity #define AT91C_US_PAR_MULTI_DROP (0x6u << 9) // (DBGU) Multi-drop mode #define AT91C_US_CHMODE (0x3u << 14) // (DBGU) Channel Mode #define AT91C_US_CHMODE_NORMAL (0x0u << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. #define AT91C_US_CHMODE_AUTO (0x1u << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. #define AT91C_US_CHMODE_LOCAL (0x2u << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. #define AT91C_US_CHMODE_REMOTE (0x3u << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. // -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- #define AT91C_US_RXRDY (0x1u << 0) // (DBGU) RXRDY Interrupt #define AT91C_US_TXRDY (0x1u << 1) // (DBGU) TXRDY Interrupt #define AT91C_US_ENDRX (0x1u << 3) // (DBGU) End of Receive Transfer Interrupt #define AT91C_US_ENDTX (0x1u << 4) // (DBGU) End of Transmit Interrupt #define AT91C_US_OVRE (0x1u << 5) // (DBGU) Overrun Interrupt #define AT91C_US_FRAME (0x1u << 6) // (DBGU) Framing Error Interrupt #define AT91C_US_PARE (0x1u << 7) // (DBGU) Parity Error Interrupt #define AT91C_US_TXEMPTY (0x1u << 9) // (DBGU) TXEMPTY Interrupt #define AT91C_US_TXBUFE (0x1u << 11) // (DBGU) TXBUFE Interrupt #define AT91C_US_RXBUFF (0x1u << 12) // (DBGU) RXBUFF Interrupt #define AT91C_US_COMM_TX (0x1u << 30) // (DBGU) COMM_TX Interrupt #define AT91C_US_COMM_RX (0x1u << 31) // (DBGU) COMM_RX Interrupt // -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- // -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- // -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- // -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- #define AT91C_US_FORCE_NTRST (0x1u << 0) // (DBGU) Force NTRST in JTAG // ***************************************************************************** // SOFTWARE API DEFINITION FOR Peripheral Data Controller // ***************************************************************************** typedef struct _AT91S_PDC { AT91_REG PDC_RPR; // Receive Pointer Register AT91_REG PDC_RCR; // Receive Counter Register AT91_REG PDC_TPR; // Transmit Pointer Register AT91_REG PDC_TCR; // Transmit Counter Register AT91_REG PDC_RNPR; // Receive Next Pointer Register AT91_REG PDC_RNCR; // Receive Next Counter Register AT91_REG PDC_TNPR; // Transmit Next Pointer Register AT91_REG PDC_TNCR; // Transmit Next Counter Register AT91_REG PDC_PTCR; // PDC Transfer Control Register AT91_REG PDC_PTSR; // PDC Transfer Status Register } AT91S_PDC, *AT91PS_PDC; // -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- #define AT91C_PDC_RXTEN (0x1u << 0) // (PDC) Receiver Transfer Enable #define AT91C_PDC_RXTDIS (0x1u << 1) // (PDC) Receiver Transfer Disable #define AT91C_PDC_TXTEN (0x1u << 8) // (PDC) Transmitter Transfer Enable #define AT91C_PDC_TXTDIS (0x1u << 9) // (PDC) Transmitter Transfer Disable // -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Advanced Interrupt Controller // ***************************************************************************** typedef struct _AT91S_AIC { AT91_REG AIC_SMR[32]; // Source Mode Register AT91_REG AIC_SVR[32]; // Source Vector Register AT91_REG AIC_IVR; // IRQ Vector Register AT91_REG AIC_FVR; // FIQ Vector Register AT91_REG AIC_ISR; // Interrupt Status Register AT91_REG AIC_IPR; // Interrupt Pending Register AT91_REG AIC_IMR; // Interrupt Mask Register AT91_REG AIC_CISR; // Core Interrupt Status Register AT91_REG Reserved0[2]; // AT91_REG AIC_IECR; // Interrupt Enable Command Register AT91_REG AIC_IDCR; // Interrupt Disable Command Register AT91_REG AIC_ICCR; // Interrupt Clear Command Register AT91_REG AIC_ISCR; // Interrupt Set Command Register AT91_REG AIC_EOICR; // End of Interrupt Command Register AT91_REG AIC_SPU; // Spurious Vector Register AT91_REG AIC_DCR; // Debug Control Register (Protect) AT91_REG Reserved1[1]; // AT91_REG AIC_FFER; // Fast Forcing Enable Register AT91_REG AIC_FFDR; // Fast Forcing Disable Register AT91_REG AIC_FFSR; // Fast Forcing Status Register } AT91S_AIC, *AT91PS_AIC; // -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- #define AT91C_AIC_PRIOR (0x7u << 0) // (AIC) Priority Level #define AT91C_AIC_PRIOR_LOWEST 0x0u // (AIC) Lowest priority level #define AT91C_AIC_PRIOR_HIGHEST 0x7u // (AIC) Highest priority level #define AT91C_AIC_SRCTYPE (0x3u << 5) // (AIC) Interrupt Source Type #define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0u << 5) // (AIC) Internal Sources Code Label Level Sensitive #define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1u << 5) // (AIC) Internal Sources Code Label Edge triggered #define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2u << 5) // (AIC) External Sources Code Label High-level Sensitive #define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3u << 5) // (AIC) External Sources Code Label Positive Edge triggered // -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- #define AT91C_AIC_NFIQ (0x1u << 0) // (AIC) NFIQ Status #define AT91C_AIC_NIRQ (0x1u << 1) // (AIC) NIRQ Status // -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- #define AT91C_AIC_DCR_PROT (0x1u << 0) // (AIC) Protection Mode #define AT91C_AIC_DCR_GMSK (0x1u << 1) // (AIC) General Mask // ***************************************************************************** // SOFTWARE API DEFINITION FOR Serial Parallel Interface // ***************************************************************************** typedef struct _AT91S_SPI { AT91_REG SPI_CR; // Control Register AT91_REG SPI_MR; // Mode Register AT91_REG SPI_RDR; // Receive Data Register AT91_REG SPI_TDR; // Transmit Data Register AT91_REG SPI_SR; // Status Register AT91_REG SPI_IER; // Interrupt Enable Register AT91_REG SPI_IDR; // Interrupt Disable Register AT91_REG SPI_IMR; // Interrupt Mask Register AT91_REG Reserved0[4]; // AT91_REG SPI_CSR[4]; // Chip Select Register AT91_REG Reserved1[48]; // AT91_REG SPI_RPR; // Receive Pointer Register AT91_REG SPI_RCR; // Receive Counter Register AT91_REG SPI_TPR; // Transmit Pointer Register AT91_REG SPI_TCR; // Transmit Counter Register AT91_REG SPI_RNPR; // Receive Next Pointer Register AT91_REG SPI_RNCR; // Receive Next Counter Register AT91_REG SPI_TNPR; // Transmit Next Pointer Register AT91_REG SPI_TNCR; // Transmit Next Counter Register AT91_REG SPI_PTCR; // PDC Transfer Control Register AT91_REG SPI_PTSR; // PDC Transfer Status Register } AT91S_SPI, *AT91PS_SPI; // -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- #define AT91C_SPI_SPIEN (0x1u << 0) // (SPI) SPI Enable #define AT91C_SPI_SPIDIS (0x1u << 1) // (SPI) SPI Disable #define AT91C_SPI_SWRST (0x1u << 7) // (SPI) SPI Software reset // -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- #define AT91C_SPI_MSTR (0x1u << 0) // (SPI) Master/Slave Mode #define AT91C_SPI_PS (0x1u << 1) // (SPI) Peripheral Select #define AT91C_SPI_PS_FIXED (0x0u << 1) // (SPI) Fixed Peripheral Select #define AT91C_SPI_PS_VARIABLE (0x1u << 1) // (SPI) Variable Peripheral Select #define AT91C_SPI_PCSDEC (0x1u << 2) // (SPI) Chip Select Decode #define AT91C_SPI_DIV32 (0x1u << 3) // (SPI) Clock Selection #define AT91C_SPI_MODFDIS (0x1u << 4) // (SPI) Mode Fault Detection #define AT91C_SPI_LLB (0x1u << 7) // (SPI) Clock Selection #define AT91C_SPI_PCS (0xFu << 16) // (SPI) Peripheral Chip Select #define AT91C_SPI_DLYBCS (0xFFu << 24) // (SPI) Delay Between Chip Selects // -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- #define AT91C_SPI_RD (0xFFFFu << 0) // (SPI) Receive Data #define AT91C_SPI_RPCS (0xFu << 16) // (SPI) Peripheral Chip Select Status // -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- #define AT91C_SPI_TD (0xFFFFu << 0) // (SPI) Transmit Data #define AT91C_SPI_TPCS (0xFu << 16) // (SPI) Peripheral Chip Select Status // -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- #define AT91C_SPI_RDRF (0x1u << 0) // (SPI) Receive Data Register Full #define AT91C_SPI_TDRE (0x1u << 1) // (SPI) Transmit Data Register Empty #define AT91C_SPI_MODF (0x1u << 2) // (SPI) Mode Fault Error #define AT91C_SPI_OVRES (0x1u << 3) // (SPI) Overrun Error Status #define AT91C_SPI_SPENDRX (0x1u << 4) // (SPI) End of Receiver Transfer #define AT91C_SPI_SPENDTX (0x1u << 5) // (SPI) End of Receiver Transfer #define AT91C_SPI_RXBUFF (0x1u << 6) // (SPI) RXBUFF Interrupt #define AT91C_SPI_TXBUFE (0x1u << 7) // (SPI) TXBUFE Interrupt #define AT91C_SPI_SPIENS (0x1u << 16) // (SPI) Enable Status // -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- // -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- // -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- // -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- #define AT91C_SPI_CPOL (0x1u << 0) // (SPI) Clock Polarity #define AT91C_SPI_NCPHA (0x1u << 1) // (SPI) Clock Phase #define AT91C_SPI_BITS (0xFu << 4) // (SPI) Bits Per Transfer #define AT91C_SPI_BITS_8 (0x0u << 4) // (SPI) 8 Bits Per transfer #define AT91C_SPI_BITS_9 (0x1u << 4) // (SPI) 9 Bits Per transfer #define AT91C_SPI_BITS_10 (0x2u << 4) // (SPI) 10 Bits Per transfer #define AT91C_SPI_BITS_11 (0x3u << 4) // (SPI) 11 Bits Per transfer #define AT91C_SPI_BITS_12 (0x4u << 4) // (SPI) 12 Bits Per transfer #define AT91C_SPI_BITS_13 (0x5u << 4) // (SPI) 13 Bits Per transfer #define AT91C_SPI_BITS_14 (0x6u << 4) // (SPI) 14 Bits Per transfer #define AT91C_SPI_BITS_15 (0x7u << 4) // (SPI) 15 Bits Per transfer #define AT91C_SPI_BITS_16 (0x8u << 4) // (SPI) 16 Bits Per transfer #define AT91C_SPI_SCBR (0xFFu << 8) // (SPI) Serial Clock Baud Rate #define AT91C_SPI_DLYBS (0xFFu << 16) // (SPI) Serial Clock Baud Rate #define AT91C_SPI_DLYBCT (0xFFu << 24) // (SPI) Delay Between Consecutive Transfers // ***************************************************************************** // SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface // ***************************************************************************** typedef struct _AT91S_SSC { AT91_REG SSC_CR; // Control Register AT91_REG SSC_CMR; // Clock Mode Register AT91_REG Reserved0[2]; // AT91_REG SSC_RCMR; // Receive Clock ModeRegister AT91_REG SSC_RFMR; // Receive Frame Mode Register AT91_REG SSC_TCMR; // Transmit Clock Mode Register AT91_REG SSC_TFMR; // Transmit Frame Mode Register AT91_REG SSC_RHR; // Receive Holding Register AT91_REG SSC_THR; // Transmit Holding Register AT91_REG Reserved1[2]; // AT91_REG SSC_RSHR; // Receive Sync Holding Register AT91_REG SSC_TSHR; // Transmit Sync Holding Register AT91_REG SSC_RC0R; // Receive Compare 0 Register AT91_REG SSC_RC1R; // Receive Compare 1 Register AT91_REG SSC_SR; // Status Register AT91_REG SSC_IER; // Interrupt Enable Register AT91_REG SSC_IDR; // Interrupt Disable Register AT91_REG SSC_IMR; // Interrupt Mask Register AT91_REG Reserved2[44]; // AT91_REG SSC_RPR; // Receive Pointer Register AT91_REG SSC_RCR; // Receive Counter Register AT91_REG SSC_TPR; // Transmit Pointer Register AT91_REG SSC_TCR; // Transmit Counter Register AT91_REG SSC_RNPR; // Receive Next Pointer Register AT91_REG SSC_RNCR; // Receive Next Counter Register AT91_REG SSC_TNPR; // Transmit Next Pointer Register AT91_REG SSC_TNCR; // Transmit Next Counter Register AT91_REG SSC_PTCR; // PDC Transfer Control Register AT91_REG SSC_PTSR; // PDC Transfer Status Register } AT91S_SSC, *AT91PS_SSC; // -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- #define AT91C_SSC_RXEN (0x1u << 0) // (SSC) Receive Enable #define AT91C_SSC_RXDIS (0x1u << 1) // (SSC) Receive Disable #define AT91C_SSC_TXEN (0x1u << 8) // (SSC) Transmit Enable #define AT91C_SSC_TXDIS (0x1u << 9) // (SSC) Transmit Disable #define AT91C_SSC_SWRST (0x1u << 15) // (SSC) Software Reset // -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- #define AT91C_SSC_CKS (0x3u << 0) // (SSC) Receive/Transmit Clock Selection #define AT91C_SSC_CKS_DIV 0x0u // (SSC) Divided Clock #define AT91C_SSC_CKS_TK 0x1u // (SSC) TK Clock signal #define AT91C_SSC_CKS_RK 0x2u // (SSC) RK pin #define AT91C_SSC_CKO (0x7u << 2) // (SSC) Receive/Transmit Clock Output Mode Selection #define AT91C_SSC_CKO_NONE (0x0u << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only #define AT91C_SSC_CKO_CONTINOUS (0x1u << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output #define AT91C_SSC_CKO_DATA_TX (0x2u << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output #define AT91C_SSC_CKI (0x1u << 5) // (SSC) Receive/Transmit Clock Inversion #define AT91C_SSC_CKG (0x3u << 6) // (SSC) Receive/Transmit Clock Gating Selection #define AT91C_SSC_CKG_NONE (0x0u << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock #define AT91C_SSC_CKG_LOW (0x1u << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low #define AT91C_SSC_CKG_HIGH (0x2u << 6) // (SSC) Receive/Transmit Clock enabled only if RF High #define AT91C_SSC_START (0xFu << 8) // (SSC) Receive/Transmit Start Selection #define AT91C_SSC_START_CONTINOUS (0x0u << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. #define AT91C_SSC_START_TX (0x1u << 8) // (SSC) Transmit/Receive start #define AT91C_SSC_START_LOW_RF (0x2u << 8) // (SSC) Detection of a low level on RF input #define AT91C_SSC_START_HIGH_RF (0x3u << 8) // (SSC) Detection of a high level on RF input #define AT91C_SSC_START_FALL_RF (0x4u << 8) // (SSC) Detection of a falling edge on RF input #define AT91C_SSC_START_RISE_RF (0x5u << 8) // (SSC) Detection of a rising edge on RF input #define AT91C_SSC_START_LEVEL_RF (0x6u << 8) // (SSC) Detection of any level change on RF input #define AT91C_SSC_START_EDGE_RF (0x7u << 8) // (SSC) Detection of any edge on RF input #define AT91C_SSC_START_0 (0x8u << 8) // (SSC) Compare 0 #define AT91C_SSC_STOP (0x1u << 12) // (SSC) Receive Stop Selection #define AT91C_SSC_STTOUT (0x1u << 15) // (SSC) Receive/Transmit Start Output Selection #define AT91C_SSC_STTDLY (0xFFu << 16) // (SSC) Receive/Transmit Start Delay #define AT91C_SSC_PERIOD (0xFFu << 24) // (SSC) Receive/Transmit Period Divider Selection // -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- #define AT91C_SSC_DATLEN (0x1Fu << 0) // (SSC) Data Length #define AT91C_SSC_LOOP (0x1u << 5) // (SSC) Loop Mode #define AT91C_SSC_MSBF (0x1u << 7) // (SSC) Most Significant Bit First #define AT91C_SSC_DATNB (0xFu << 8) // (SSC) Data Number per Frame #define AT91C_SSC_FSLEN (0xFu << 16) // (SSC) Receive/Transmit Frame Sync length #define AT91C_SSC_FSOS (0x7u << 20) // (SSC) Receive/Transmit Frame Sync Output Selection #define AT91C_SSC_FSOS_NONE (0x0u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only #define AT91C_SSC_FSOS_NEGATIVE (0x1u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse #define AT91C_SSC_FSOS_POSITIVE (0x2u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse #define AT91C_SSC_FSOS_LOW (0x3u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer #define AT91C_SSC_FSOS_HIGH (0x4u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer #define AT91C_SSC_FSOS_TOGGLE (0x5u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer #define AT91C_SSC_FSEDGE (0x1u << 24) // (SSC) Frame Sync Edge Detection // -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- // -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- #define AT91C_SSC_DATDEF (0x1u << 5) // (SSC) Data Default Value #define AT91C_SSC_FSDEN (0x1u << 23) // (SSC) Frame Sync Data Enable // -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- #define AT91C_SSC_TXRDY (0x1u << 0) // (SSC) Transmit Ready #define AT91C_SSC_TXEMPTY (0x1u << 1) // (SSC) Transmit Empty #define AT91C_SSC_ENDTX (0x1u << 2) // (SSC) End Of Transmission #define AT91C_SSC_TXBUFE (0x1u << 3) // (SSC) Transmit Buffer Empty #define AT91C_SSC_RXRDY (0x1u << 4) // (SSC) Receive Ready #define AT91C_SSC_OVRUN (0x1u << 5) // (SSC) Receive Overrun #define AT91C_SSC_ENDRX (0x1u << 6) // (SSC) End of Reception #define AT91C_SSC_RXBUFF (0x1u << 7) // (SSC) Receive Buffer Full #define AT91C_SSC_CP0 (0x1u << 8) // (SSC) Compare 0 #define AT91C_SSC_CP1 (0x1u << 9) // (SSC) Compare 1 #define AT91C_SSC_TXSYN (0x1u << 10) // (SSC) Transmit Sync #define AT91C_SSC_RXSYN (0x1u << 11) // (SSC) Receive Sync #define AT91C_SSC_TXENA (0x1u << 16) // (SSC) Transmit Enable #define AT91C_SSC_RXENA (0x1u << 17) // (SSC) Receive Enable // -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- // -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- // -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Usart // ***************************************************************************** typedef struct _AT91S_USART { AT91_REG US_CR; // Control Register AT91_REG US_MR; // Mode Register AT91_REG US_IER; // Interrupt Enable Register AT91_REG US_IDR; // Interrupt Disable Register AT91_REG US_IMR; // Interrupt Mask Register AT91_REG US_CSR; // Channel Status Register AT91_REG US_RHR; // Receiver Holding Register AT91_REG US_THR; // Transmitter Holding Register AT91_REG US_BRGR; // Baud Rate Generator Register AT91_REG US_RTOR; // Receiver Time-out Register AT91_REG US_TTGR; // Transmitter Time-guard Register AT91_REG Reserved0[5]; // AT91_REG US_FIDI; // FI_DI_Ratio Register AT91_REG US_NER; // Nb Errors Register AT91_REG US_XXR; // XON_XOFF Register AT91_REG US_IF; // IRDA_FILTER Register AT91_REG Reserved1[44]; // AT91_REG US_RPR; // Receive Pointer Register AT91_REG US_RCR; // Receive Counter Register AT91_REG US_TPR; // Transmit Pointer Register AT91_REG US_TCR; // Transmit Counter Register AT91_REG US_RNPR; // Receive Next Pointer Register AT91_REG US_RNCR; // Receive Next Counter Register AT91_REG US_TNPR; // Transmit Next Pointer Register AT91_REG US_TNCR; // Transmit Next Counter Register AT91_REG US_PTCR; // PDC Transfer Control Register AT91_REG US_PTSR; // PDC Transfer Status Register } AT91S_USART, *AT91PS_USART; // -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- #define AT91C_US_RSTSTA (0x1u << 8) // (USART) Reset Status Bits #define AT91C_US_STTBRK (0x1u << 9) // (USART) Start Break #define AT91C_US_STPBRK (0x1u << 10) // (USART) Stop Break #define AT91C_US_STTTO (0x1u << 11) // (USART) Start Time-out #define AT91C_US_SENDA (0x1u << 12) // (USART) Send Address #define AT91C_US_RSTIT (0x1u << 13) // (USART) Reset Iterations #define AT91C_US_RSTNACK (0x1u << 14) // (USART) Reset Non Acknowledge #define AT91C_US_RETTO (0x1u << 15) // (USART) Rearm Time-out #define AT91C_US_DTREN (0x1u << 16) // (USART) Data Terminal ready Enable #define AT91C_US_DTRDIS (0x1u << 17) // (USART) Data Terminal ready Disable #define AT91C_US_RTSEN (0x1u << 18) // (USART) Request to Send enable #define AT91C_US_RTSDIS (0x1u << 19) // (USART) Request to Send Disable // -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- #define AT91C_US_USMODE (0xFu << 0) // (USART) Usart mode #define AT91C_US_USMODE_NORMAL 0x0u // (USART) Normal #define AT91C_US_USMODE_RS485 0x1u // (USART) RS485 #define AT91C_US_USMODE_HWHSH 0x2u // (USART) Hardware Handshaking #define AT91C_US_USMODE_MODEM 0x3u // (USART) Modem #define AT91C_US_USMODE_ISO7816_0 0x4u // (USART) ISO7816 protocol: T = 0 #define AT91C_US_USMODE_ISO7816_1 0x6u // (USART) ISO7816 protocol: T = 1 #define AT91C_US_USMODE_IRDA 0x8u // (USART) IrDA #define AT91C_US_USMODE_SWHSH 0xCu // (USART) Software Handshaking #define AT91C_US_CLKS (0x3u << 4) // (USART) Clock Selection (Baud Rate generator Input Clock #define AT91C_US_CLKS_CLOCK (0x0u << 4) // (USART) Clock #define AT91C_US_CLKS_FDIV1 (0x1u << 4) // (USART) fdiv1 #define AT91C_US_CLKS_SLOW (0x2u << 4) // (USART) slow_clock (ARM) #define AT91C_US_CLKS_EXT (0x3u << 4) // (USART) External (SCK) #define AT91C_US_CHRL (0x3u << 6) // (USART) Clock Selection (Baud Rate generator Input Clock #define AT91C_US_CHRL_5_BITS (0x0u << 6) // (USART) Character Length: 5 bits #define AT91C_US_CHRL_6_BITS (0x1u << 6) // (USART) Character Length: 6 bits #define AT91C_US_CHRL_7_BITS (0x2u << 6) // (USART) Character Length: 7 bits #define AT91C_US_CHRL_8_BITS (0x3u << 6) // (USART) Character Length: 8 bits #define AT91C_US_SYNC (0x1u << 8) // (USART) Synchronous Mode Select #define AT91C_US_NBSTOP (0x3u << 12) // (USART) Number of Stop bits #define AT91C_US_NBSTOP_1_BIT (0x0u << 12) // (USART) 1 stop bit #define AT91C_US_NBSTOP_15_BIT (0x1u << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits #define AT91C_US_NBSTOP_2_BIT (0x2u << 12) // (USART) 2 stop bits #define AT91C_US_MSBF (0x1u << 16) // (USART) Bit Order #define AT91C_US_MODE9 (0x1u << 17) // (USART) 9-bit Character length #define AT91C_US_CKLO (0x1u << 18) // (USART) Clock Output Select #define AT91C_US_OVER (0x1u << 19) // (USART) Over Sampling Mode #define AT91C_US_INACK (0x1u << 20) // (USART) Inhibit Non Acknowledge #define AT91C_US_DSNACK (0x1u << 21) // (USART) Disable Successive NACK #define AT91C_US_MAX_ITER (0x1u << 24) // (USART) Number of Repetitions #define AT91C_US_FILTER (0x1u << 28) // (USART) Receive Line Filter // -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- #define AT91C_US_RXBRK (0x1u << 2) // (USART) Break Received/End of Break #define AT91C_US_TIMEOUT (0x1u << 8) // (USART) Receiver Time-out #define AT91C_US_ITERATION (0x1u << 10) // (USART) Max number of Repetitions Reached #define AT91C_US_NACK (0x1u << 13) // (USART) Non Acknowledge #define AT91C_US_RIIC (0x1u << 16) // (USART) Ring INdicator Input Change Flag #define AT91C_US_DSRIC (0x1u << 17) // (USART) Data Set Ready Input Change Flag #define AT91C_US_DCDIC (0x1u << 18) // (USART) Data Carrier Flag #define AT91C_US_CTSIC (0x1u << 19) // (USART) Clear To Send Input Change Flag // -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- // -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- // -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- #define AT91C_US_RI (0x1u << 20) // (USART) Image of RI Input #define AT91C_US_DSR (0x1u << 21) // (USART) Image of DSR Input #define AT91C_US_DCD (0x1u << 22) // (USART) Image of DCD Input #define AT91C_US_CTS (0x1u << 23) // (USART) Image of CTS Input // ***************************************************************************** // SOFTWARE API DEFINITION FOR Two-wire Interface // ***************************************************************************** typedef struct _AT91S_TWI { AT91_REG TWI_CR; // Control Register AT91_REG TWI_MMR; // Master Mode Register AT91_REG TWI_SMR; // Slave Mode Register AT91_REG TWI_IADR; // Internal Address Register AT91_REG TWI_CWGR; // Clock Waveform Generator Register AT91_REG Reserved0[3]; // AT91_REG TWI_SR; // Status Register AT91_REG TWI_IER; // Interrupt Enable Register AT91_REG TWI_IDR; // Interrupt Disable Register AT91_REG TWI_IMR; // Interrupt Mask Register AT91_REG TWI_RHR; // Receive Holding Register AT91_REG TWI_THR; // Transmit Holding Register } AT91S_TWI, *AT91PS_TWI; // -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- #define AT91C_TWI_START (0x1u << 0) // (TWI) Send a START Condition #define AT91C_TWI_STOP (0x1u << 1) // (TWI) Send a STOP Condition #define AT91C_TWI_MSEN (0x1u << 2) // (TWI) TWI Master Transfer Enabled #define AT91C_TWI_MSDIS (0x1u << 3) // (TWI) TWI Master Transfer Disabled #define AT91C_TWI_SVEN (0x1u << 4) // (TWI) TWI Slave Transfer Enabled #define AT91C_TWI_SVDIS (0x1u << 5) // (TWI) TWI Slave Transfer Disabled #define AT91C_TWI_SWRST (0x1u << 7) // (TWI) Software Reset // -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- #define AT91C_TWI_IADRSZ (0x3u << 8) // (TWI) Internal Device Address Size #define AT91C_TWI_IADRSZ_NO (0x0u << 8) // (TWI) No internal device address #define AT91C_TWI_IADRSZ_1_BYTE (0x1u << 8) // (TWI) One-byte internal device address #define AT91C_TWI_IADRSZ_2_BYTE (0x2u << 8) // (TWI) Two-byte internal device address #define AT91C_TWI_IADRSZ_3_BYTE (0x3u << 8) // (TWI) Three-byte internal device address #define AT91C_TWI_MREAD (0x1u << 12) // (TWI) Master Read Direction #define AT91C_TWI_DADR (0x7Fu << 16) // (TWI) Device Address // -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- #define AT91C_TWI_SADR (0x7Fu << 16) // (TWI) Slave Device Address // -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- #define AT91C_TWI_CLDIV (0xFFu << 0) // (TWI) Clock Low Divider #define AT91C_TWI_CHDIV (0xFFu << 8) // (TWI) Clock High Divider #define AT91C_TWI_CKDIV (0x7u << 16) // (TWI) Clock Divider // -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- #define AT91C_TWI_TXCOMP (0x1u << 0) // (TWI) Transmission Completed #define AT91C_TWI_RXRDY (0x1u << 1) // (TWI) Receive holding register ReaDY #define AT91C_TWI_TXRDY (0x1u << 2) // (TWI) Transmit holding register ReaDY #define AT91C_TWI_SVREAD (0x1u << 3) // (TWI) Slave Read #define AT91C_TWI_SVACC (0x1u << 4) // (TWI) Slave Access #define AT91C_TWI_GCACC (0x1u << 5) // (TWI) General Call Access #define AT91C_TWI_OVRE (0x1u << 6) // (TWI) Overrun Error #define AT91C_TWI_UNRE (0x1u << 7) // (TWI) Underrun Error #define AT91C_TWI_NACK (0x1u << 8) // (TWI) Not Acknowledged #define AT91C_TWI_ARBLST (0x1u << 9) // (TWI) Arbitration Lost // -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- // -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- // -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Multimedia Card Interface // ***************************************************************************** typedef struct _AT91S_MCI { AT91_REG MCI_CR; // MCI Control Register AT91_REG MCI_MR; // MCI Mode Register AT91_REG MCI_DTOR; // MCI Data Timeout Register AT91_REG MCI_SDCR; // MCI SD Card Register AT91_REG MCI_ARGR; // MCI Argument Register AT91_REG MCI_CMDR; // MCI Command Register AT91_REG Reserved0[2]; // AT91_REG MCI_RSPR[4]; // MCI Response Register AT91_REG MCI_RDR; // MCI Receive Data Register AT91_REG MCI_TDR; // MCI Transmit Data Register AT91_REG Reserved1[2]; // AT91_REG MCI_SR; // MCI Status Register AT91_REG MCI_IER; // MCI Interrupt Enable Register AT91_REG MCI_IDR; // MCI Interrupt Disable Register AT91_REG MCI_IMR; // MCI Interrupt Mask Register AT91_REG Reserved2[44]; // AT91_REG MCI_RPR; // Receive Pointer Register AT91_REG MCI_RCR; // Receive Counter Register AT91_REG MCI_TPR; // Transmit Pointer Register AT91_REG MCI_TCR; // Transmit Counter Register AT91_REG MCI_RNPR; // Receive Next Pointer Register AT91_REG MCI_RNCR; // Receive Next Counter Register AT91_REG MCI_TNPR; // Transmit Next Pointer Register AT91_REG MCI_TNCR; // Transmit Next Counter Register AT91_REG MCI_PTCR; // PDC Transfer Control Register AT91_REG MCI_PTSR; // PDC Transfer Status Register } AT91S_MCI, *AT91PS_MCI; // -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- #define AT91C_MCI_MCIEN (0x1u << 0) // (MCI) Multimedia Interface Enable #define AT91C_MCI_MCIDIS (0x1u << 1) // (MCI) Multimedia Interface Disable #define AT91C_MCI_PWSEN (0x1u << 2) // (MCI) Power Save Mode Enable #define AT91C_MCI_PWSDIS (0x1u << 3) // (MCI) Power Save Mode Disable // -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- #define AT91C_MCI_CLKDIV (0x1u << 0) // (MCI) Clock Divider #define AT91C_MCI_PWSDIV (0x1u << 8) // (MCI) Power Saving Divider #define AT91C_MCI_PDCPADV (0x1u << 14) // (MCI) PDC Padding Value #define AT91C_MCI_PDCMODE (0x1u << 15) // (MCI) PDC Oriented Mode #define AT91C_MCI_BLKLEN (0x1u << 18) // (MCI) Data Block Length // -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- #define AT91C_MCI_DTOCYC (0x1u << 0) // (MCI) Data Timeout Cycle Number #define AT91C_MCI_DTOMUL (0x7u << 4) // (MCI) Data Timeout Multiplier #define AT91C_MCI_DTOMUL_1 (0x0u << 4) // (MCI) DTOCYC x 1 #define AT91C_MCI_DTOMUL_16 (0x1u << 4) // (MCI) DTOCYC x 16 #define AT91C_MCI_DTOMUL_128 (0x2u << 4) // (MCI) DTOCYC x 128 #define AT91C_MCI_DTOMUL_256 (0x3u << 4) // (MCI) DTOCYC x 256 #define AT91C_MCI_DTOMUL_1024 (0x4u << 4) // (MCI) DTOCYC x 1024 #define AT91C_MCI_DTOMUL_4096 (0x5u << 4) // (MCI) DTOCYC x 4096 #define AT91C_MCI_DTOMUL_65536 (0x6u << 4) // (MCI) DTOCYC x 65536 #define AT91C_MCI_DTOMUL_1048576 (0x7u << 4) // (MCI) DTOCYC x 1048576 // -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- #define AT91C_MCI_SCDSEL (0x1u << 0) // (MCI) SD Card Selector #define AT91C_MCI_SCDBUS (0x1u << 7) // (MCI) SD Card Bus Width // -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- // -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- #define AT91C_MCI_CMDRDY (0x1u << 0) // (MCI) Command Ready flag #define AT91C_MCI_RXRDY (0x1u << 1) // (MCI) RX Ready flag #define AT91C_MCI_TXRDY (0x1u << 2) // (MCI) TX Ready flag #define AT91C_MCI_BLKE (0x1u << 3) // (MCI) Data Block Transfer Ended flag #define AT91C_MCI_DTIP (0x1u << 4) // (MCI) Data Transfer in Progress flag #define AT91C_MCI_NOTBUSY (0x1u << 5) // (MCI) Data Line Not Busy flag #define AT91C_MCI_ENDRX (0x1u << 6) // (MCI) End of RX Buffer flag #define AT91C_MCI_ENDTX (0x1u << 7) // (MCI) End of TX Buffer flag #define AT91C_MCI_RXBUFF (0x1u << 14) // (MCI) RX Buffer Full flag #define AT91C_MCI_TXBUFE (0x1u << 15) // (MCI) TX Buffer Empty flag #define AT91C_MCI_RINDE (0x1u << 16) // (MCI) Response Index Error flag #define AT91C_MCI_RDIRE (0x1u << 17) // (MCI) Response Direction Error flag #define AT91C_MCI_RCRCE (0x1u << 18) // (MCI) Response CRC Error flag #define AT91C_MCI_RENDE (0x1u << 19) // (MCI) Response End Bit Error flag #define AT91C_MCI_RTOE (0x1u << 20) // (MCI) Response Time-out Error flag #define AT91C_MCI_DCRCE (0x1u << 21) // (MCI) data CRC Error flag #define AT91C_MCI_DTOE (0x1u << 22) // (MCI) Data timeout Error flag #define AT91C_MCI_OVRE (0x1u << 30) // (MCI) Overrun flag #define AT91C_MCI_UNRE (0x1u << 31) // (MCI) Underrun flag // -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- // -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- // -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR USB Device Interface // ***************************************************************************** typedef struct _AT91S_UDP { AT91_REG UDP_NUM; // Frame Number Register AT91_REG UDP_GLBSTATE; // Global State Register AT91_REG UDP_FADDR; // Function Address Register AT91_REG Reserved0[1]; // AT91_REG UDP_IER; // Interrupt Enable Register AT91_REG UDP_IDR; // Interrupt Disable Register AT91_REG UDP_IMR; // Interrupt Mask Register AT91_REG UDP_ISR; // Interrupt Status Register AT91_REG UDP_ICR; // Interrupt Clear Register AT91_REG Reserved1[1]; // AT91_REG UDP_RSTEP; // Reset Endpoint Register AT91_REG Reserved2[1]; // AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register } AT91S_UDP, *AT91PS_UDP; // -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- #define AT91C_UDP_FRM_NUM (0x7FFu << 0) // (UDP) Frame Number as Defined in the Packet Field Formats #define AT91C_UDP_FRM_ERR (0x1u << 16) // (UDP) Frame Error #define AT91C_UDP_FRM_OK (0x1u << 17) // (UDP) Frame OK // -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- #define AT91C_UDP_FADDEN (0x1u << 0) // (UDP) Function Address Enable #define AT91C_UDP_CONFG (0x1u << 1) // (UDP) Configured #define AT91C_UDP_RMWUPE (0x1u << 2) // (UDP) Remote Wake Up Enable #define AT91C_UDP_RSMINPR (0x1u << 3) // (UDP) A Resume Has Been Sent to the Host // -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- #define AT91C_UDP_FADD (0xFFu << 0) // (UDP) Function Address Value #define AT91C_UDP_FEN (0x1u << 8) // (UDP) Function Enable // -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- #define AT91C_UDP_EPINT0 (0x1u << 0) // (UDP) Endpoint 0 Interrupt #define AT91C_UDP_EPINT1 (0x1u << 1) // (UDP) Endpoint 0 Interrupt #define AT91C_UDP_EPINT2 (0x1u << 2) // (UDP) Endpoint 2 Interrupt #define AT91C_UDP_EPINT3 (0x1u << 3) // (UDP) Endpoint 3 Interrupt #define AT91C_UDP_EPINT4 (0x1u << 4) // (UDP) Endpoint 4 Interrupt #define AT91C_UDP_EPINT5 (0x1u << 5) // (UDP) Endpoint 5 Interrupt #define AT91C_UDP_EPINT6 (0x1u << 6) // (UDP) Endpoint 6 Interrupt #define AT91C_UDP_EPINT7 (0x1u << 7) // (UDP) Endpoint 7 Interrupt #define AT91C_UDP_RXSUSP (0x1u << 8) // (UDP) USB Suspend Interrupt #define AT91C_UDP_RXRSM (0x1u << 9) // (UDP) USB Resume Interrupt #define AT91C_UDP_EXTRSM (0x1u << 10) // (UDP) USB External Resume Interrupt #define AT91C_UDP_SOFINT (0x1u << 11) // (UDP) USB Start Of frame Interrupt #define AT91C_UDP_WAKEUP (0x1u << 13) // (UDP) USB Resume Interrupt // -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- // -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- // -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- #define AT91C_UDP_ENDBUSRES (0x1u << 12) // (UDP) USB End Of Bus Reset Interrupt // -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- // -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- #define AT91C_UDP_EP0 (0x1u << 0) // (UDP) Reset Endpoint 0 #define AT91C_UDP_EP1 (0x1u << 1) // (UDP) Reset Endpoint 1 #define AT91C_UDP_EP2 (0x1u << 2) // (UDP) Reset Endpoint 2 #define AT91C_UDP_EP3 (0x1u << 3) // (UDP) Reset Endpoint 3 #define AT91C_UDP_EP4 (0x1u << 4) // (UDP) Reset Endpoint 4 #define AT91C_UDP_EP5 (0x1u << 5) // (UDP) Reset Endpoint 5 #define AT91C_UDP_EP6 (0x1u << 6) // (UDP) Reset Endpoint 6 #define AT91C_UDP_EP7 (0x1u << 7) // (UDP) Reset Endpoint 7 // -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- #define AT91C_UDP_TXCOMP (0x1u << 0) // (UDP) Generates an IN packet with data previously written in the DPR #define AT91C_UDP_RX_DATA_BK0 (0x1u << 1) // (UDP) Receive Data Bank 0 #define AT91C_UDP_RXSETUP (0x1u << 2) // (UDP) Sends STALL to the Host (Control endpoints) #define AT91C_UDP_ISOERROR (0x1u << 3) // (UDP) Isochronous error (Isochronous endpoints) #define AT91C_UDP_TXPKTRDY (0x1u << 4) // (UDP) Transmit Packet Ready #define AT91C_UDP_FORCESTALL (0x1u << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). #define AT91C_UDP_RX_DATA_BK1 (0x1u << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). #define AT91C_UDP_DIR (0x1u << 7) // (UDP) Transfer Direction #define AT91C_UDP_EPTYPE (0x7u << 8) // (UDP) Endpoint type #define AT91C_UDP_EPTYPE_CTRL (0x0u << 8) // (UDP) Control #define AT91C_UDP_EPTYPE_ISO_OUT (0x1u << 8) // (UDP) Isochronous OUT #define AT91C_UDP_EPTYPE_BULK_OUT (0x2u << 8) // (UDP) Bulk OUT #define AT91C_UDP_EPTYPE_INT_OUT (0x3u << 8) // (UDP) Interrupt OUT #define AT91C_UDP_EPTYPE_ISO_IN (0x5u << 8) // (UDP) Isochronous IN #define AT91C_UDP_EPTYPE_BULK_IN (0x6u << 8) // (UDP) Bulk IN #define AT91C_UDP_EPTYPE_INT_IN (0x7u << 8) // (UDP) Interrupt IN #define AT91C_UDP_DTGLE (0x1u << 11) // (UDP) Data Toggle #define AT91C_UDP_EPEDS (0x1u << 15) // (UDP) Endpoint Enable Disable #define AT91C_UDP_RXBYTECNT (0x7FFu << 16) // (UDP) Number Of Bytes Available in the FIFO // ***************************************************************************** // SOFTWARE API DEFINITION FOR Timer Counter Channel Interface // ***************************************************************************** typedef struct _AT91S_TC { AT91_REG TC_CCR; // Channel Control Register AT91_REG TC_CMR; // Channel Mode Register AT91_REG Reserved0[2]; // AT91_REG TC_CV; // Counter Value AT91_REG TC_RA; // Register A AT91_REG TC_RB; // Register B AT91_REG TC_RC; // Register C AT91_REG TC_SR; // Status Register AT91_REG TC_IER; // Interrupt Enable Register AT91_REG TC_IDR; // Interrupt Disable Register AT91_REG TC_IMR; // Interrupt Mask Register } AT91S_TC, *AT91PS_TC; // -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- #define AT91C_TC_CLKEN (0x1u << 0) // (TC) Counter Clock Enable Command #define AT91C_TC_CLKDIS (0x1u << 1) // (TC) Counter Clock Disable Command #define AT91C_TC_SWTRG (0x1u << 2) // (TC) Software Trigger Command // -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- #define AT91C_TC_CPCSTOP (0x1u << 6) // (TC) Counter Clock Stopped with RC Compare #define AT91C_TC_CPCDIS (0x1u << 7) // (TC) Counter Clock Disable with RC Compare #define AT91C_TC_EEVTEDG (0x3u << 8) // (TC) External Event Edge Selection #define AT91C_TC_EEVTEDG_NONE (0x0u << 8) // (TC) Edge: None #define AT91C_TC_EEVTEDG_RISING (0x1u << 8) // (TC) Edge: rising edge #define AT91C_TC_EEVTEDG_FALLING (0x2u << 8) // (TC) Edge: falling edge #define AT91C_TC_EEVTEDG_BOTH (0x3u << 8) // (TC) Edge: each edge #define AT91C_TC_EEVT (0x3u << 10) // (TC) External Event Selection #define AT91C_TC_EEVT_NONE (0x0u << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input #define AT91C_TC_EEVT_RISING (0x1u << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output #define AT91C_TC_EEVT_FALLING (0x2u << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output #define AT91C_TC_EEVT_BOTH (0x3u << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output #define AT91C_TC_ENETRG (0x1u << 12) // (TC) External Event Trigger enable #define AT91C_TC_WAVESEL (0x3u << 13) // (TC) Waveform Selection #define AT91C_TC_WAVESEL_UP (0x0u << 13) // (TC) UP mode without atomatic trigger on RC Compare #define AT91C_TC_WAVESEL_UP_AUTO (0x1u << 13) // (TC) UP mode with automatic trigger on RC Compare #define AT91C_TC_WAVESEL_UPDOWN (0x2u << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare #define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3u << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare #define AT91C_TC_CPCTRG (0x1u << 14) // (TC) RC Compare Trigger Enable #define AT91C_TC_WAVE (0x1u << 15) // (TC) #define AT91C_TC_ACPA (0x3u << 16) // (TC) RA Compare Effect on TIOA #define AT91C_TC_ACPA_NONE (0x0u << 16) // (TC) Effect: none #define AT91C_TC_ACPA_SET (0x1u << 16) // (TC) Effect: set #define AT91C_TC_ACPA_CLEAR (0x2u << 16) // (TC) Effect: clear #define AT91C_TC_ACPA_TOGGLE (0x3u << 16) // (TC) Effect: toggle #define AT91C_TC_ACPC (0x3u << 18) // (TC) RC Compare Effect on TIOA #define AT91C_TC_ACPC_NONE (0x0u << 18) // (TC) Effect: none #define AT91C_TC_ACPC_SET (0x1u << 18) // (TC) Effect: set #define AT91C_TC_ACPC_CLEAR (0x2u << 18) // (TC) Effect: clear #define AT91C_TC_ACPC_TOGGLE (0x3u << 18) // (TC) Effect: toggle #define AT91C_TC_AEEVT (0x3u << 20) // (TC) External Event Effect on TIOA #define AT91C_TC_AEEVT_NONE (0x0u << 20) // (TC) Effect: none #define AT91C_TC_AEEVT_SET (0x1u << 20) // (TC) Effect: set #define AT91C_TC_AEEVT_CLEAR (0x2u << 20) // (TC) Effect: clear #define AT91C_TC_AEEVT_TOGGLE (0x3u << 20) // (TC) Effect: toggle #define AT91C_TC_ASWTRG (0x3u << 22) // (TC) Software Trigger Effect on TIOA #define AT91C_TC_ASWTRG_NONE (0x0u << 22) // (TC) Effect: none #define AT91C_TC_ASWTRG_SET (0x1u << 22) // (TC) Effect: set #define AT91C_TC_ASWTRG_CLEAR (0x2u << 22) // (TC) Effect: clear #define AT91C_TC_ASWTRG_TOGGLE (0x3u << 22) // (TC) Effect: toggle #define AT91C_TC_BCPB (0x3u << 24) // (TC) RB Compare Effect on TIOB #define AT91C_TC_BCPB_NONE (0x0u << 24) // (TC) Effect: none #define AT91C_TC_BCPB_SET (0x1u << 24) // (TC) Effect: set #define AT91C_TC_BCPB_CLEAR (0x2u << 24) // (TC) Effect: clear #define AT91C_TC_BCPB_TOGGLE (0x3u << 24) // (TC) Effect: toggle #define AT91C_TC_BCPC (0x3u << 26) // (TC) RC Compare Effect on TIOB #define AT91C_TC_BCPC_NONE (0x0u << 26) // (TC) Effect: none #define AT91C_TC_BCPC_SET (0x1u << 26) // (TC) Effect: set #define AT91C_TC_BCPC_CLEAR (0x2u << 26) // (TC) Effect: clear #define AT91C_TC_BCPC_TOGGLE (0x3u << 26) // (TC) Effect: toggle #define AT91C_TC_BEEVT (0x3u << 28) // (TC) External Event Effect on TIOB #define AT91C_TC_BEEVT_NONE (0x0u << 28) // (TC) Effect: none #define AT91C_TC_BEEVT_SET (0x1u << 28) // (TC) Effect: set #define AT91C_TC_BEEVT_CLEAR (0x2u << 28) // (TC) Effect: clear #define AT91C_TC_BEEVT_TOGGLE (0x3u << 28) // (TC) Effect: toggle #define AT91C_TC_BSWTRG (0x3u << 30) // (TC) Software Trigger Effect on TIOB #define AT91C_TC_BSWTRG_NONE (0x0u << 30) // (TC) Effect: none #define AT91C_TC_BSWTRG_SET (0x1u << 30) // (TC) Effect: set #define AT91C_TC_BSWTRG_CLEAR (0x2u << 30) // (TC) Effect: clear #define AT91C_TC_BSWTRG_TOGGLE (0x3u << 30) // (TC) Effect: toggle // -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- #define AT91C_TC_COVFS (0x1u << 0) // (TC) Counter Overflow #define AT91C_TC_LOVRS (0x1u << 1) // (TC) Load Overrun #define AT91C_TC_CPAS (0x1u << 2) // (TC) RA Compare #define AT91C_TC_CPBS (0x1u << 3) // (TC) RB Compare #define AT91C_TC_CPCS (0x1u << 4) // (TC) RC Compare #define AT91C_TC_LDRAS (0x1u << 5) // (TC) RA Loading #define AT91C_TC_LDRBS (0x1u << 6) // (TC) RB Loading #define AT91C_TC_ETRCS (0x1u << 7) // (TC) External Trigger #define AT91C_TC_ETRGS (0x1u << 16) // (TC) Clock Enabling #define AT91C_TC_MTIOA (0x1u << 17) // (TC) TIOA Mirror #define AT91C_TC_MTIOB (0x1u << 18) // (TC) TIOA Mirror // -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- // -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- // -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Timer Counter Interface // ***************************************************************************** typedef struct _AT91S_TCB { AT91S_TC TCB_TC0; // TC Channel 0 AT91_REG Reserved0[4]; // AT91S_TC TCB_TC1; // TC Channel 1 AT91_REG Reserved1[4]; // AT91S_TC TCB_TC2; // TC Channel 2 AT91_REG Reserved2[4]; // AT91_REG TCB_BCR; // TC Block Control Register AT91_REG TCB_BMR; // TC Block Mode Register } AT91S_TCB, *AT91PS_TCB; // -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- #define AT91C_TCB_SYNC (0x1u << 0) // (TCB) Synchro Command // -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- #define AT91C_TCB_TC0XC0S (0x1u << 0) // (TCB) External Clock Signal 0 Selection #define AT91C_TCB_TC0XC0S_TCLK0 0x0u // (TCB) TCLK0 connected to XC0 #define AT91C_TCB_TC0XC0S_NONE 0x1u // (TCB) None signal connected to XC0 #define AT91C_TCB_TC0XC0S_TIOA1 0x2u // (TCB) TIOA1 connected to XC0 #define AT91C_TCB_TC0XC0S_TIOA2 0x3u // (TCB) TIOA2 connected to XC0 #define AT91C_TCB_TC1XC1S (0x1u << 2) // (TCB) External Clock Signal 1 Selection #define AT91C_TCB_TC1XC1S_TCLK1 (0x0u << 2) // (TCB) TCLK1 connected to XC1 #define AT91C_TCB_TC1XC1S_NONE (0x1u << 2) // (TCB) None signal connected to XC1 #define AT91C_TCB_TC1XC1S_TIOA0 (0x2u << 2) // (TCB) TIOA0 connected to XC1 #define AT91C_TCB_TC1XC1S_TIOA2 (0x3u << 2) // (TCB) TIOA2 connected to XC1 #define AT91C_TCB_TC2XC2S (0x1u << 4) // (TCB) External Clock Signal 2 Selection #define AT91C_TCB_TC2XC2S_TCLK2 (0x0u << 4) // (TCB) TCLK2 connected to XC2 #define AT91C_TCB_TC2XC2S_NONE (0x1u << 4) // (TCB) None signal connected to XC2 #define AT91C_TCB_TC2XC2S_TIOA0 (0x2u << 4) // (TCB) TIOA0 connected to XC2 #define AT91C_TCB_TC2XC2S_TIOA2 (0x3u << 4) // (TCB) TIOA2 connected to XC2 // ***************************************************************************** // SOFTWARE API DEFINITION FOR USB Host Interface // ***************************************************************************** typedef struct _AT91S_UHP { AT91_REG UHP_HcRevision; // Revision AT91_REG UHP_HcControl; // Operating modes for the Host Controller AT91_REG UHP_HcCommandStatus; // Command & status Register AT91_REG UHP_HcInterruptStatus; // Interrupt Status Register AT91_REG UHP_HcInterruptEnable; // Interrupt Enable Register AT91_REG UHP_HcInterruptDisable; // Interrupt Disable Register AT91_REG UHP_HcHCCA; // Pointer to the Host Controller Communication Area AT91_REG UHP_HcPeriodCurrentED; // Current Isochronous or Interrupt Endpoint Descriptor AT91_REG UHP_HcControlHeadED; // First Endpoint Descriptor of the Control list AT91_REG UHP_HcControlCurrentED; // Endpoint Control and Status Register AT91_REG UHP_HcBulkHeadED; // First endpoint register of the Bulk list AT91_REG UHP_HcBulkCurrentED; // Current endpoint of the Bulk list AT91_REG UHP_HcBulkDoneHead; // Last completed transfer descriptor AT91_REG UHP_HcFmInterval; // Bit time between 2 consecutive SOFs AT91_REG UHP_HcFmRemaining; // Bit time remaining in the current Frame AT91_REG UHP_HcFmNumber; // Frame number AT91_REG UHP_HcPeriodicStart; // Periodic Start AT91_REG UHP_HcLSThreshold; // LS Threshold AT91_REG UHP_HcRhDescriptorA; // Root Hub characteristics A AT91_REG UHP_HcRhDescriptorB; // Root Hub characteristics B AT91_REG UHP_HcRhStatus; // Root Hub Status register AT91_REG UHP_HcRhPortStatus[2]; // Root Hub Port Status Register } AT91S_UHP, *AT91PS_UHP; // ***************************************************************************** // SOFTWARE API DEFINITION FOR Ethernet MAC // ***************************************************************************** typedef struct _AT91S_EMAC { AT91_REG EMAC_CTL; // Network Control Register AT91_REG EMAC_CFG; // Network Configuration Register AT91_REG EMAC_SR; // Network Status Register AT91_REG EMAC_TAR; // Transmit Address Register AT91_REG EMAC_TCR; // Transmit Control Register AT91_REG EMAC_TSR; // Transmit Status Register AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer AT91_REG Reserved0[1]; // AT91_REG EMAC_RSR; // Receive Status Register AT91_REG EMAC_ISR; // Interrupt Status Register AT91_REG EMAC_IER; // Interrupt Enable Register AT91_REG EMAC_IDR; // Interrupt Disable Register AT91_REG EMAC_IMR; // Interrupt Mask Register AT91_REG EMAC_MAN; // PHY Maintenance Register AT91_REG Reserved1[2]; // AT91_REG EMAC_FRA; // Frames Transmitted OK Register AT91_REG EMAC_SCOL; // Single Collision Frame Register AT91_REG EMAC_MCOL; // Multiple Collision Frame Register AT91_REG EMAC_OK; // Frames Received OK Register AT91_REG EMAC_SEQE; // Frame Check Sequence Error Register AT91_REG EMAC_ALE; // Alignment Error Register AT91_REG EMAC_DTE; // Deferred Transmission Frame Register AT91_REG EMAC_LCOL; // Late Collision Register AT91_REG EMAC_ECOL; // Excessive Collision Register AT91_REG EMAC_CSE; // Carrier Sense Error Register AT91_REG EMAC_TUE; // Transmit Underrun Error Register AT91_REG EMAC_CDE; // Code Error Register AT91_REG EMAC_ELR; // Excessive Length Error Register AT91_REG EMAC_RJB; // Receive Jabber Register AT91_REG EMAC_USF; // Undersize Frame Register AT91_REG EMAC_SQEE; // SQE Test Error Register AT91_REG EMAC_DRFC; // Discarded RX Frame Register AT91_REG Reserved2[3]; // AT91_REG EMAC_HSH; // Hash Address High[63:32] AT91_REG EMAC_HSL; // Hash Address Low[31:0] AT91_REG EMAC_SA1L; // Specific Address 1 Low, First 4 bytes AT91_REG EMAC_SA1H; // Specific Address 1 High, Last 2 bytes AT91_REG EMAC_SA2L; // Specific Address 2 Low, First 4 bytes AT91_REG EMAC_SA2H; // Specific Address 2 High, Last 2 bytes AT91_REG EMAC_SA3L; // Specific Address 3 Low, First 4 bytes AT91_REG EMAC_SA3H; // Specific Address 3 High, Last 2 bytes AT91_REG EMAC_SA4L; // Specific Address 4 Low, First 4 bytes AT91_REG EMAC_SA4H; // Specific Address 4 High, Last 2 bytesr } AT91S_EMAC, *AT91PS_EMAC; // -------- EMAC_CTL : (EMAC Offset: 0x0) -------- #define AT91C_EMAC_LB (0x1u << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. #define AT91C_EMAC_LBL (0x1u << 1) // (EMAC) Loopback local. #define AT91C_EMAC_RE (0x1u << 2) // (EMAC) Receive enable. #define AT91C_EMAC_TE (0x1u << 3) // (EMAC) Transmit enable. #define AT91C_EMAC_MPE (0x1u << 4) // (EMAC) Management port enable. #define AT91C_EMAC_CSR (0x1u << 5) // (EMAC) Clear statistics registers. #define AT91C_EMAC_ISR (0x1u << 6) // (EMAC) Increment statistics registers. #define AT91C_EMAC_WES (0x1u << 7) // (EMAC) Write enable for statistics registers. #define AT91C_EMAC_BP (0x1u << 8) // (EMAC) Back pressure. // -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- #define AT91C_EMAC_SPD (0x1u << 0) // (EMAC) Speed. #define AT91C_EMAC_FD (0x1u << 1) // (EMAC) Full duplex. #define AT91C_EMAC_BR (0x1u << 2) // (EMAC) Bit rate. #define AT91C_EMAC_CAF (0x1u << 4) // (EMAC) Copy all frames. #define AT91C_EMAC_NBC (0x1u << 5) // (EMAC) No broadcast. #define AT91C_EMAC_MTI (0x1u << 6) // (EMAC) Multicast hash enable #define AT91C_EMAC_UNI (0x1u << 7) // (EMAC) Unicast hash enable. #define AT91C_EMAC_BIG (0x1u << 8) // (EMAC) Receive 1522 bytes. #define AT91C_EMAC_EAE (0x1u << 9) // (EMAC) External address match enable. #define AT91C_EMAC_CLK (0x3u << 10) // (EMAC) #define AT91C_EMAC_CLK_HCLK_8 (0x0u << 10) // (EMAC) HCLK divided by 8 #define AT91C_EMAC_CLK_HCLK_16 (0x1u << 10) // (EMAC) HCLK divided by 16 #define AT91C_EMAC_CLK_HCLK_32 (0x2u << 10) // (EMAC) HCLK divided by 32 #define AT91C_EMAC_CLK_HCLK_64 (0x3u << 10) // (EMAC) HCLK divided by 64 #define AT91C_EMAC_RTY (0x1u << 12) // (EMAC) #define AT91C_EMAC_RMII (0x1u << 13) // (EMAC) // -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- #define AT91C_EMAC_MDIO (0x1u << 1) // (EMAC) #define AT91C_EMAC_IDLE (0x1u << 2) // (EMAC) // -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- #define AT91C_EMAC_LEN (0x7FFu << 0) // (EMAC) #define AT91C_EMAC_NCRC (0x1u << 15) // (EMAC) // -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- #define AT91C_EMAC_OVR (0x1u << 0) // (EMAC) #define AT91C_EMAC_COL (0x1u << 1) // (EMAC) #define AT91C_EMAC_RLE (0x1u << 2) // (EMAC) #define AT91C_EMAC_TXIDLE (0x1u << 3) // (EMAC) #define AT91C_EMAC_BNQ (0x1u << 4) // (EMAC) #define AT91C_EMAC_COMP (0x1u << 5) // (EMAC) #define AT91C_EMAC_UND (0x1u << 6) // (EMAC) // -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- #define AT91C_EMAC_BNA (0x1u << 0) // (EMAC) #define AT91C_EMAC_REC (0x1u << 1) // (EMAC) // -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- #define AT91C_EMAC_DONE (0x1u << 0) // (EMAC) #define AT91C_EMAC_RCOM (0x1u << 1) // (EMAC) #define AT91C_EMAC_RBNA (0x1u << 2) // (EMAC) #define AT91C_EMAC_TOVR (0x1u << 3) // (EMAC) #define AT91C_EMAC_TUND (0x1u << 4) // (EMAC) #define AT91C_EMAC_RTRY (0x1u << 5) // (EMAC) #define AT91C_EMAC_TBRE (0x1u << 6) // (EMAC) #define AT91C_EMAC_TCOM (0x1u << 7) // (EMAC) #define AT91C_EMAC_TIDLE (0x1u << 8) // (EMAC) #define AT91C_EMAC_LINK (0x1u << 9) // (EMAC) #define AT91C_EMAC_ROVR (0x1u << 10) // (EMAC) #define AT91C_EMAC_HRESP (0x1u << 11) // (EMAC) // -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- // -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- // -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- // -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- #define AT91C_EMAC_DATA (0xFFFFu << 0) // (EMAC) #define AT91C_EMAC_CODE (0x3u << 16) // (EMAC) #define AT91C_EMAC_REGA (0x1Fu << 18) // (EMAC) #define AT91C_EMAC_PHYA (0x1Fu << 23) // (EMAC) #define AT91C_EMAC_RW (0x3u << 28) // (EMAC) #define AT91C_EMAC_HIGH (0x1u << 30) // (EMAC) #define AT91C_EMAC_LOW (0x1u << 31) // (EMAC) // ***************************************************************************** // SOFTWARE API DEFINITION FOR External Bus Interface // ***************************************************************************** typedef struct _AT91S_EBI { AT91_REG EBI_CSA; // Chip Select Assignment Register AT91_REG EBI_CFGR; // Configuration Register } AT91S_EBI, *AT91PS_EBI; // -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- #define AT91C_EBI_CS0A (0x1u << 0) // (EBI) Chip Select 0 Assignment #define AT91C_EBI_CS0A_SMC 0x0u // (EBI) Chip Select 0 is assigned to the Static Memory Controller. #define AT91C_EBI_CS0A_BFC 0x1u // (EBI) Chip Select 0 is assigned to the Burst Flash Controller. #define AT91C_EBI_CS1A (0x1u << 1) // (EBI) Chip Select 1 Assignment #define AT91C_EBI_CS1A_SMC (0x0u << 1) // (EBI) Chip Select 1 is assigned to the Static Memory Controller. #define AT91C_EBI_CS1A_SDRAMC (0x1u << 1) // (EBI) Chip Select 1 is assigned to the SDRAM Controller. #define AT91C_EBI_CS3A (0x1u << 3) // (EBI) Chip Select 3 Assignment #define AT91C_EBI_CS3A_SMC (0x0u << 3) // (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2. #define AT91C_EBI_CS3A_SMC_SmartMedia (0x1u << 3) // (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. #define AT91C_EBI_CS4A (0x1u << 4) // (EBI) Chip Select 4 Assignment #define AT91C_EBI_CS4A_SMC (0x0u << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2. #define AT91C_EBI_CS4A_SMC_CompactFlash (0x1u << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. // -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- #define AT91C_EBI_DBPUC (0x1u << 0) // (EBI) Data Bus Pull-Up Configuration #define AT91C_EBI_EBSEN (0x1u << 1) // (EBI) Bus Sharing Enable // ***************************************************************************** // SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface // ***************************************************************************** typedef struct _AT91S_SMC2 { AT91_REG SMC2_CSR[8]; // SMC2 Chip Select Register } AT91S_SMC2, *AT91PS_SMC2; // -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- #define AT91C_SMC2_NWS (0x7Fu << 0) // (SMC2) Number of Wait States #define AT91C_SMC2_WSEN (0x1u << 7) // (SMC2) Wait State Enable #define AT91C_SMC2_TDF (0xFu << 8) // (SMC2) Data Float Time #define AT91C_SMC2_BAT (0x1u << 12) // (SMC2) Byte Access Type #define AT91C_SMC2_DBW (0x1u << 13) // (SMC2) Data Bus Width #define AT91C_SMC2_DBW_16 (0x1u << 13) // (SMC2) 16-bit. #define AT91C_SMC2_DBW_8 (0x2u << 13) // (SMC2) 8-bit. #define AT91C_SMC2_DRP (0x1u << 15) // (SMC2) Data Read Protocol #define AT91C_SMC2_ACSS (0x3u << 16) // (SMC2) Address to Chip Select Setup #define AT91C_SMC2_ACSS_STANDARD (0x0u << 16) // (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. #define AT91C_SMC2_ACSS_1_CYCLE (0x1u << 16) // (SMC2) One cycle less at the beginning and the end of the access. #define AT91C_SMC2_ACSS_2_CYCLES (0x2u << 16) // (SMC2) Two cycles less at the beginning and the end of the access. #define AT91C_SMC2_ACSS_3_CYCLES (0x3u << 16) // (SMC2) Three cycles less at the beginning and the end of the access. #define AT91C_SMC2_RWSETUP (0x7u << 24) // (SMC2) Read and Write Signal Setup Time #define AT91C_SMC2_RWHOLD (0x7u << 29) // (SMC2) Read and Write Signal Hold Time // ***************************************************************************** // SOFTWARE API DEFINITION FOR SDRAM Controller Interface // ***************************************************************************** typedef struct _AT91S_SDRC { AT91_REG SDRC_MR; // SDRAM Controller Mode Register AT91_REG SDRC_TR; // SDRAM Controller Refresh Timer Register AT91_REG SDRC_CR; // SDRAM Controller Configuration Register AT91_REG SDRC_SRR; // SDRAM Controller Self Refresh Register AT91_REG SDRC_LPR; // SDRAM Controller Low Power Register AT91_REG SDRC_IER; // SDRAM Controller Interrupt Enable Register AT91_REG SDRC_IDR; // SDRAM Controller Interrupt Disable Register AT91_REG SDRC_IMR; // SDRAM Controller Interrupt Mask Register AT91_REG SDRC_ISR; // SDRAM Controller Interrupt Mask Register } AT91S_SDRC, *AT91PS_SDRC; // -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- #define AT91C_SDRC_MODE (0xFu << 0) // (SDRC) Mode #define AT91C_SDRC_MODE_NORMAL_CMD 0x0u // (SDRC) Normal Mode #define AT91C_SDRC_MODE_NOP_CMD 0x1u // (SDRC) NOP Command #define AT91C_SDRC_MODE_PRCGALL_CMD 0x2u // (SDRC) All Banks Precharge Command #define AT91C_SDRC_MODE_LMR_CMD 0x3u // (SDRC) Load Mode Register Command #define AT91C_SDRC_MODE_RFSH_CMD 0x4u // (SDRC) Refresh Command #define AT91C_SDRC_DBW (0x1u << 4) // (SDRC) Data Bus Width #define AT91C_SDRC_DBW_32_BITS (0x0u << 4) // (SDRC) 32 Bits datas bus #define AT91C_SDRC_DBW_16_BITS (0x1u << 4) // (SDRC) 16 Bits datas bus // -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- #define AT91C_SDRC_COUNT (0xFFFu << 0) // (SDRC) Refresh Counter // -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- #define AT91C_SDRC_NC (0x3u << 0) // (SDRC) Number of Column Bits #define AT91C_SDRC_NC_8 0x0u // (SDRC) 8 Bits #define AT91C_SDRC_NC_9 0x1u // (SDRC) 9 Bits #define AT91C_SDRC_NC_10 0x2u // (SDRC) 10 Bits #define AT91C_SDRC_NC_11 0x3u // (SDRC) 11 Bits #define AT91C_SDRC_NR (0x3u << 2) // (SDRC) Number of Row Bits #define AT91C_SDRC_NR_11 (0x0u << 2) // (SDRC) 11 Bits #define AT91C_SDRC_NR_12 (0x1u << 2) // (SDRC) 12 Bits #define AT91C_SDRC_NR_13 (0x2u << 2) // (SDRC) 13 Bits #define AT91C_SDRC_NB (0x1u << 4) // (SDRC) Number of Banks #define AT91C_SDRC_NB_2_BANKS (0x0u << 4) // (SDRC) 2 banks #define AT91C_SDRC_NB_4_BANKS (0x1u << 4) // (SDRC) 4 banks #define AT91C_SDRC_CAS (0x3u << 5) // (SDRC) CAS Latency #define AT91C_SDRC_CAS_2 (0x2u << 5) // (SDRC) 2 cycles #define AT91C_SDRC_TWR (0xFu << 7) // (SDRC) Number of Write Recovery Time Cycles #define AT91C_SDRC_TRC (0xFu << 11) // (SDRC) Number of RAS Cycle Time Cycles #define AT91C_SDRC_TRP (0xFu << 15) // (SDRC) Number of RAS Precharge Time Cycles #define AT91C_SDRC_TRCD (0xFu << 19) // (SDRC) Number of RAS to CAS Delay Cycles #define AT91C_SDRC_TRAS (0xFu << 23) // (SDRC) Number of RAS Active Time Cycles #define AT91C_SDRC_TXSR (0xFu << 27) // (SDRC) Number of Command Recovery Time Cycles // -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- #define AT91C_SDRC_SRCB (0x1u << 0) // (SDRC) Self-refresh Command Bit // -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- #define AT91C_SDRC_LPCB (0x1u << 0) // (SDRC) Low-power Command Bit // -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- #define AT91C_SDRC_RES (0x1u << 0) // (SDRC) Refresh Error Status // -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- // -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- // -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Burst Flash Controller Interface // ***************************************************************************** typedef struct _AT91S_BFC { AT91_REG BFC_MR; // BFC Mode Register } AT91S_BFC, *AT91PS_BFC; // -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- #define AT91C_BFC_BFCOM (0x3u << 0) // (BFC) Burst Flash Controller Operating Mode #define AT91C_BFC_BFCOM_DISABLED 0x0u // (BFC) NPCS0 is driven by the SMC or remains high. #define AT91C_BFC_BFCOM_ASYNC 0x1u // (BFC) Asynchronous #define AT91C_BFC_BFCOM_BURST_READ 0x2u // (BFC) Burst Read #define AT91C_BFC_BFCC (0x3u << 2) // (BFC) Burst Flash Controller Operating Mode #define AT91C_BFC_BFCC_MCK (0x1u << 2) // (BFC) Master Clock. #define AT91C_BFC_BFCC_MCK_DIV_2 (0x2u << 2) // (BFC) Master Clock divided by 2. #define AT91C_BFC_BFCC_MCK_DIV_4 (0x3u << 2) // (BFC) Master Clock divided by 4. #define AT91C_BFC_AVL (0xFu << 4) // (BFC) Address Valid Latency #define AT91C_BFC_PAGES (0x7u << 8) // (BFC) Page Size #define AT91C_BFC_PAGES_NO_PAGE (0x0u << 8) // (BFC) No page handling. #define AT91C_BFC_PAGES_16 (0x1u << 8) // (BFC) 16 bytes page size. #define AT91C_BFC_PAGES_32 (0x2u << 8) // (BFC) 32 bytes page size. #define AT91C_BFC_PAGES_64 (0x3u << 8) // (BFC) 64 bytes page size. #define AT91C_BFC_PAGES_128 (0x4u << 8) // (BFC) 128 bytes page size. #define AT91C_BFC_PAGES_256 (0x5u << 8) // (BFC) 256 bytes page size. #define AT91C_BFC_PAGES_512 (0x6u << 8) // (BFC) 512 bytes page size. #define AT91C_BFC_PAGES_1024 (0x7u << 8) // (BFC) 1024 bytes page size. #define AT91C_BFC_OEL (0x3u << 12) // (BFC) Output Enable Latency #define AT91C_BFC_BAAEN (0x1u << 16) // (BFC) Burst Address Advance Enable #define AT91C_BFC_BFOEH (0x1u << 17) // (BFC) Burst Flash Output Enable Handling #define AT91C_BFC_MUXEN (0x1u << 18) // (BFC) Multiplexed Bus Enable #define AT91C_BFC_RDYEN (0x1u << 19) // (BFC) Ready Enable Mode // ***************************************************************************** // REGISTER ADDRESS DEFINITION FOR AT91RM9200 // ***************************************************************************** // ========== Register definition for SYS peripheral ========== // ========== Register definition for MC peripheral ========== #define AT91C_MC_PUER ((AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register #define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register #define AT91C_MC_PUP ((AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals #define AT91C_MC_PUIA ((AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area #define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register #define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register // ========== Register definition for RTC peripheral ========== #define AT91C_RTC_IMR ((AT91_REG *) 0xFFFFFE28) // (RTC) Interrupt Mask Register #define AT91C_RTC_IER ((AT91_REG *) 0xFFFFFE20) // (RTC) Interrupt Enable Register #define AT91C_RTC_SR ((AT91_REG *) 0xFFFFFE18) // (RTC) Status Register #define AT91C_RTC_TIMALR ((AT91_REG *) 0xFFFFFE10) // (RTC) Time Alarm Register #define AT91C_RTC_TIMR ((AT91_REG *) 0xFFFFFE08) // (RTC) Time Register #define AT91C_RTC_CR ((AT91_REG *) 0xFFFFFE00) // (RTC) Control Register #define AT91C_RTC_VER ((AT91_REG *) 0xFFFFFE2C) // (RTC) Valid Entry Register #define AT91C_RTC_IDR ((AT91_REG *) 0xFFFFFE24) // (RTC) Interrupt Disable Register #define AT91C_RTC_SCCR ((AT91_REG *) 0xFFFFFE1C) // (RTC) Status Clear Command Register #define AT91C_RTC_CALALR ((AT91_REG *) 0xFFFFFE14) // (RTC) Calendar Alarm Register #define AT91C_RTC_CALR ((AT91_REG *) 0xFFFFFE0C) // (RTC) Calendar Register #define AT91C_RTC_MR ((AT91_REG *) 0xFFFFFE04) // (RTC) Mode Register // ========== Register definition for ST peripheral ========== #define AT91C_ST_CRTR ((AT91_REG *) 0xFFFFFD24) // (ST) Current Real-time Register #define AT91C_ST_IMR ((AT91_REG *) 0xFFFFFD1C) // (ST) Interrupt Mask Register #define AT91C_ST_IER ((AT91_REG *) 0xFFFFFD14) // (ST) Interrupt Enable Register #define AT91C_ST_RTMR ((AT91_REG *) 0xFFFFFD0C) // (ST) Real-time Mode Register #define AT91C_ST_PIMR ((AT91_REG *) 0xFFFFFD04) // (ST) Period Interval Mode Register #define AT91C_ST_RTAR ((AT91_REG *) 0xFFFFFD20) // (ST) Real-time Alarm Register #define AT91C_ST_IDR ((AT91_REG *) 0xFFFFFD18) // (ST) Interrupt Disable Register #define AT91C_ST_SR ((AT91_REG *) 0xFFFFFD10) // (ST) Status Register #define AT91C_ST_WDMR ((AT91_REG *) 0xFFFFFD08) // (ST) Watchdog Mode Register #define AT91C_ST_CR ((AT91_REG *) 0xFFFFFD00) // (ST) Control Register // ========== Register definition for PMC peripheral ========== #define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register #define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register #define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register #define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register #define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register #define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register #define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register #define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register #define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register #define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register #define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register #define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register // ========== Register definition for CKGR peripheral ========== #define AT91C_CKGR_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL B Register #define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register #define AT91C_CKGR_PLLAR ((AT91_REG *) 0xFFFFFC28) // (CKGR) PLL A Register #define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register // ========== Register definition for PIOD peripheral ========== #define AT91C_PIOD_PDSR ((AT91_REG *) 0xFFFFFA3C) // (PIOD) Pin Data Status Register #define AT91C_PIOD_CODR ((AT91_REG *) 0xFFFFFA34) // (PIOD) Clear Output Data Register #define AT91C_PIOD_OWER ((AT91_REG *) 0xFFFFFAA0) // (PIOD) Output Write Enable Register #define AT91C_PIOD_MDER ((AT91_REG *) 0xFFFFFA50) // (PIOD) Multi-driver Enable Register #define AT91C_PIOD_IMR ((AT91_REG *) 0xFFFFFA48) // (PIOD) Interrupt Mask Register #define AT91C_PIOD_IER ((AT91_REG *) 0xFFFFFA40) // (PIOD) Interrupt Enable Register #define AT91C_PIOD_ODSR ((AT91_REG *) 0xFFFFFA38) // (PIOD) Output Data Status Register #define AT91C_PIOD_SODR ((AT91_REG *) 0xFFFFFA30) // (PIOD) Set Output Data Register #define AT91C_PIOD_PER ((AT91_REG *) 0xFFFFFA00) // (PIOD) PIO Enable Register #define AT91C_PIOD_OWDR ((AT91_REG *) 0xFFFFFAA4) // (PIOD) Output Write Disable Register #define AT91C_PIOD_PPUER ((AT91_REG *) 0xFFFFFA64) // (PIOD) Pull-up Enable Register #define AT91C_PIOD_MDDR ((AT91_REG *) 0xFFFFFA54) // (PIOD) Multi-driver Disable Register #define AT91C_PIOD_ISR ((AT91_REG *) 0xFFFFFA4C) // (PIOD) Interrupt Status Register #define AT91C_PIOD_IDR ((AT91_REG *) 0xFFFFFA44) // (PIOD) Interrupt Disable Register #define AT91C_PIOD_PDR ((AT91_REG *) 0xFFFFFA04) // (PIOD) PIO Disable Register #define AT91C_PIOD_ODR ((AT91_REG *) 0xFFFFFA14) // (PIOD) Output Disable Registerr #define AT91C_PIOD_OWSR ((AT91_REG *) 0xFFFFFAA8) // (PIOD) Output Write Status Register #define AT91C_PIOD_ABSR ((AT91_REG *) 0xFFFFFA78) // (PIOD) AB Select Status Register #define AT91C_PIOD_ASR ((AT91_REG *) 0xFFFFFA70) // (PIOD) Select A Register #define AT91C_PIOD_PPUSR ((AT91_REG *) 0xFFFFFA68) // (PIOD) Pad Pull-up Status Register #define AT91C_PIOD_PPUDR ((AT91_REG *) 0xFFFFFA60) // (PIOD) Pull-up Disable Register #define AT91C_PIOD_MDSR ((AT91_REG *) 0xFFFFFA58) // (PIOD) Multi-driver Status Register #define AT91C_PIOD_PSR ((AT91_REG *) 0xFFFFFA08) // (PIOD) PIO Status Register #define AT91C_PIOD_OER ((AT91_REG *) 0xFFFFFA10) // (PIOD) Output Enable Register #define AT91C_PIOD_OSR ((AT91_REG *) 0xFFFFFA18) // (PIOD) Output Status Register #define AT91C_PIOD_IFER ((AT91_REG *) 0xFFFFFA20) // (PIOD) Input Filter Enable Register #define AT91C_PIOD_BSR ((AT91_REG *) 0xFFFFFA74) // (PIOD) Select B Register #define AT91C_PIOD_IFDR ((AT91_REG *) 0xFFFFFA24) // (PIOD) Input Filter Disable Register #define AT91C_PIOD_IFSR ((AT91_REG *) 0xFFFFFA28) // (PIOD) Input Filter Status Register // ========== Register definition for PIOC peripheral ========== #define AT91C_PIOC_IFDR ((AT91_REG *) 0xFFFFF824) // (PIOC) Input Filter Disable Register #define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) // (PIOC) Output Disable Registerr #define AT91C_PIOC_ABSR ((AT91_REG *) 0xFFFFF878) // (PIOC) AB Select Status Register #define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) // (PIOC) Set Output Data Register #define AT91C_PIOC_IFSR ((AT91_REG *) 0xFFFFF828) // (PIOC) Input Filter Status Register #define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) // (PIOC) Clear Output Data Register #define AT91C_PIOC_ODSR ((AT91_REG *) 0xFFFFF838) // (PIOC) Output Data Status Register #define AT91C_PIOC_IER ((AT91_REG *) 0xFFFFF840) // (PIOC) Interrupt Enable Register #define AT91C_PIOC_IMR ((AT91_REG *) 0xFFFFF848) // (PIOC) Interrupt Mask Register #define AT91C_PIOC_OWDR ((AT91_REG *) 0xFFFFF8A4) // (PIOC) Output Write Disable Register #define AT91C_PIOC_MDDR ((AT91_REG *) 0xFFFFF854) // (PIOC) Multi-driver Disable Register #define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) // (PIOC) Pin Data Status Register #define AT91C_PIOC_IDR ((AT91_REG *) 0xFFFFF844) // (PIOC) Interrupt Disable Register #define AT91C_PIOC_ISR ((AT91_REG *) 0xFFFFF84C) // (PIOC) Interrupt Status Register #define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) // (PIOC) PIO Disable Register #define AT91C_PIOC_OWSR ((AT91_REG *) 0xFFFFF8A8) // (PIOC) Output Write Status Register #define AT91C_PIOC_OWER ((AT91_REG *) 0xFFFFF8A0) // (PIOC) Output Write Enable Register #define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register #define AT91C_PIOC_PPUSR ((AT91_REG *) 0xFFFFF868) // (PIOC) Pad Pull-up Status Register #define AT91C_PIOC_PPUDR ((AT91_REG *) 0xFFFFF860) // (PIOC) Pull-up Disable Register #define AT91C_PIOC_MDSR ((AT91_REG *) 0xFFFFF858) // (PIOC) Multi-driver Status Register #define AT91C_PIOC_MDER ((AT91_REG *) 0xFFFFF850) // (PIOC) Multi-driver Enable Register #define AT91C_PIOC_IFER ((AT91_REG *) 0xFFFFF820) // (PIOC) Input Filter Enable Register #define AT91C_PIOC_OSR ((AT91_REG *) 0xFFFFF818) // (PIOC) Output Status Register #define AT91C_PIOC_OER ((AT91_REG *) 0xFFFFF810) // (PIOC) Output Enable Register #define AT91C_PIOC_PSR ((AT91_REG *) 0xFFFFF808) // (PIOC) PIO Status Register #define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) // (PIOC) PIO Enable Register #define AT91C_PIOC_BSR ((AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register #define AT91C_PIOC_PPUER ((AT91_REG *) 0xFFFFF864) // (PIOC) Pull-up Enable Register // ========== Register definition for PIOB peripheral ========== #define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register #define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pad Pull-up Status Register #define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register #define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register #define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register #define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register #define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register #define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register #define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register #define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register #define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register #define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register #define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register #define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr #define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register #define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register #define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register #define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register #define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register #define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register #define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register #define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register #define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register #define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register #define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register #define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register #define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register #define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register #define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register // ========== Register definition for PIOA peripheral ========== #define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register #define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register #define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register #define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register #define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register #define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register #define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register #define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register #define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register #define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register #define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register #define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register #define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register #define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register #define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr #define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register #define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register #define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register #define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pad Pull-up Status Register #define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register #define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register #define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register #define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register #define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register #define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register #define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register #define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register #define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register #define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register // ========== Register definition for DBGU peripheral ========== #define AT91C_DBGU_C2R ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID2 Register #define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register #define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register #define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register #define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register #define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register #define AT91C_DBGU_C1R ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID1 Register #define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register #define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register #define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register #define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register #define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register // ========== Register definition for PDC_DBGU peripheral ========== #define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register #define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register #define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register #define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register #define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register #define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register #define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register #define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register #define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register #define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register // ========== Register definition for AIC peripheral ========== #define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register #define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register #define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register #define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register #define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register #define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) #define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register #define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register #define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register #define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register #define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register #define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register #define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register #define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register #define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register #define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register #define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register #define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register // ========== Register definition for PDC_SPI peripheral ========== #define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register #define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register #define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register #define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register #define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register #define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register #define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register #define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register #define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register #define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register // ========== Register definition for SPI peripheral ========== #define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register #define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register #define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register #define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register #define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register #define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register #define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register #define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register #define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register // ========== Register definition for PDC_SSC2 peripheral ========== #define AT91C_SSC2_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_SSC2) PDC Transfer Control Register #define AT91C_SSC2_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_SSC2) Transmit Next Pointer Register #define AT91C_SSC2_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_SSC2) Receive Next Pointer Register #define AT91C_SSC2_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_SSC2) Transmit Pointer Register #define AT91C_SSC2_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_SSC2) Receive Pointer Register #define AT91C_SSC2_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_SSC2) PDC Transfer Status Register #define AT91C_SSC2_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_SSC2) Transmit Next Counter Register #define AT91C_SSC2_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_SSC2) Receive Next Counter Register #define AT91C_SSC2_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_SSC2) Transmit Counter Register #define AT91C_SSC2_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_SSC2) Receive Counter Register // ========== Register definition for SSC2 peripheral ========== #define AT91C_SSC2_IMR ((AT91_REG *) 0xFFFD804C) // (SSC2) Interrupt Mask Register #define AT91C_SSC2_IER ((AT91_REG *) 0xFFFD8044) // (SSC2) Interrupt Enable Register #define AT91C_SSC2_RC1R ((AT91_REG *) 0xFFFD803C) // (SSC2) Receive Compare 1 Register #define AT91C_SSC2_TSHR ((AT91_REG *) 0xFFFD8034) // (SSC2) Transmit Sync Holding Register #define AT91C_SSC2_CMR ((AT91_REG *) 0xFFFD8004) // (SSC2) Clock Mode Register #define AT91C_SSC2_IDR ((AT91_REG *) 0xFFFD8048) // (SSC2) Interrupt Disable Register #define AT91C_SSC2_TCMR ((AT91_REG *) 0xFFFD8018) // (SSC2) Transmit Clock Mode Register #define AT91C_SSC2_RCMR ((AT91_REG *) 0xFFFD8010) // (SSC2) Receive Clock ModeRegister #define AT91C_SSC2_CR ((AT91_REG *) 0xFFFD8000) // (SSC2) Control Register #define AT91C_SSC2_RFMR ((AT91_REG *) 0xFFFD8014) // (SSC2) Receive Frame Mode Register #define AT91C_SSC2_TFMR ((AT91_REG *) 0xFFFD801C) // (SSC2) Transmit Frame Mode Register #define AT91C_SSC2_THR ((AT91_REG *) 0xFFFD8024) // (SSC2) Transmit Holding Register #define AT91C_SSC2_SR ((AT91_REG *) 0xFFFD8040) // (SSC2) Status Register #define AT91C_SSC2_RC0R ((AT91_REG *) 0xFFFD8038) // (SSC2) Receive Compare 0 Register #define AT91C_SSC2_RSHR ((AT91_REG *) 0xFFFD8030) // (SSC2) Receive Sync Holding Register #define AT91C_SSC2_RHR ((AT91_REG *) 0xFFFD8020) // (SSC2) Receive Holding Register // ========== Register definition for PDC_SSC1 peripheral ========== #define AT91C_SSC1_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC1) PDC Transfer Control Register #define AT91C_SSC1_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC1) Transmit Next Pointer Register #define AT91C_SSC1_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC1) Receive Next Pointer Register #define AT91C_SSC1_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC1) Transmit Pointer Register #define AT91C_SSC1_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC1) Receive Pointer Register #define AT91C_SSC1_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC1) PDC Transfer Status Register #define AT91C_SSC1_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC1) Transmit Next Counter Register #define AT91C_SSC1_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC1) Receive Next Counter Register #define AT91C_SSC1_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC1) Transmit Counter Register #define AT91C_SSC1_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC1) Receive Counter Register // ========== Register definition for SSC1 peripheral ========== #define AT91C_SSC1_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC1) Receive Frame Mode Register #define AT91C_SSC1_CMR ((AT91_REG *) 0xFFFD4004) // (SSC1) Clock Mode Register #define AT91C_SSC1_IDR ((AT91_REG *) 0xFFFD4048) // (SSC1) Interrupt Disable Register #define AT91C_SSC1_SR ((AT91_REG *) 0xFFFD4040) // (SSC1) Status Register #define AT91C_SSC1_RC0R ((AT91_REG *) 0xFFFD4038) // (SSC1) Receive Compare 0 Register #define AT91C_SSC1_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC1) Receive Sync Holding Register #define AT91C_SSC1_RHR ((AT91_REG *) 0xFFFD4020) // (SSC1) Receive Holding Register #define AT91C_SSC1_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC1) Transmit Clock Mode Register #define AT91C_SSC1_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC1) Receive Clock ModeRegister #define AT91C_SSC1_CR ((AT91_REG *) 0xFFFD4000) // (SSC1) Control Register #define AT91C_SSC1_IMR ((AT91_REG *) 0xFFFD404C) // (SSC1) Interrupt Mask Register #define AT91C_SSC1_IER ((AT91_REG *) 0xFFFD4044) // (SSC1) Interrupt Enable Register #define AT91C_SSC1_RC1R ((AT91_REG *) 0xFFFD403C) // (SSC1) Receive Compare 1 Register #define AT91C_SSC1_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC1) Transmit Sync Holding Register #define AT91C_SSC1_THR ((AT91_REG *) 0xFFFD4024) // (SSC1) Transmit Holding Register #define AT91C_SSC1_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC1) Transmit Frame Mode Register // ========== Register definition for PDC_SSC0 peripheral ========== #define AT91C_SSC0_PTCR ((AT91_REG *) 0xFFFD0120) // (PDC_SSC0) PDC Transfer Control Register #define AT91C_SSC0_TNPR ((AT91_REG *) 0xFFFD0118) // (PDC_SSC0) Transmit Next Pointer Register #define AT91C_SSC0_RNPR ((AT91_REG *) 0xFFFD0110) // (PDC_SSC0) Receive Next Pointer Register #define AT91C_SSC0_TPR ((AT91_REG *) 0xFFFD0108) // (PDC_SSC0) Transmit Pointer Register #define AT91C_SSC0_RPR ((AT91_REG *) 0xFFFD0100) // (PDC_SSC0) Receive Pointer Register #define AT91C_SSC0_PTSR ((AT91_REG *) 0xFFFD0124) // (PDC_SSC0) PDC Transfer Status Register #define AT91C_SSC0_TNCR ((AT91_REG *) 0xFFFD011C) // (PDC_SSC0) Transmit Next Counter Register #define AT91C_SSC0_RNCR ((AT91_REG *) 0xFFFD0114) // (PDC_SSC0) Receive Next Counter Register #define AT91C_SSC0_TCR ((AT91_REG *) 0xFFFD010C) // (PDC_SSC0) Transmit Counter Register #define AT91C_SSC0_RCR ((AT91_REG *) 0xFFFD0104) // (PDC_SSC0) Receive Counter Register // ========== Register definition for SSC0 peripheral ========== #define AT91C_SSC0_IMR ((AT91_REG *) 0xFFFD004C) // (SSC0) Interrupt Mask Register #define AT91C_SSC0_IER ((AT91_REG *) 0xFFFD0044) // (SSC0) Interrupt Enable Register #define AT91C_SSC0_RC1R ((AT91_REG *) 0xFFFD003C) // (SSC0) Receive Compare 1 Register #define AT91C_SSC0_TSHR ((AT91_REG *) 0xFFFD0034) // (SSC0) Transmit Sync Holding Register #define AT91C_SSC0_THR ((AT91_REG *) 0xFFFD0024) // (SSC0) Transmit Holding Register #define AT91C_SSC0_TFMR ((AT91_REG *) 0xFFFD001C) // (SSC0) Transmit Frame Mode Register #define AT91C_SSC0_RFMR ((AT91_REG *) 0xFFFD0014) // (SSC0) Receive Frame Mode Register #define AT91C_SSC0_CMR ((AT91_REG *) 0xFFFD0004) // (SSC0) Clock Mode Register #define AT91C_SSC0_IDR ((AT91_REG *) 0xFFFD0048) // (SSC0) Interrupt Disable Register #define AT91C_SSC0_SR ((AT91_REG *) 0xFFFD0040) // (SSC0) Status Register #define AT91C_SSC0_RC0R ((AT91_REG *) 0xFFFD0038) // (SSC0) Receive Compare 0 Register #define AT91C_SSC0_RSHR ((AT91_REG *) 0xFFFD0030) // (SSC0) Receive Sync Holding Register #define AT91C_SSC0_RHR ((AT91_REG *) 0xFFFD0020) // (SSC0) Receive Holding Register #define AT91C_SSC0_TCMR ((AT91_REG *) 0xFFFD0018) // (SSC0) Transmit Clock Mode Register #define AT91C_SSC0_RCMR ((AT91_REG *) 0xFFFD0010) // (SSC0) Receive Clock ModeRegister #define AT91C_SSC0_CR ((AT91_REG *) 0xFFFD0000) // (SSC0) Control Register // ========== Register definition for PDC_US3 peripheral ========== #define AT91C_US3_PTSR ((AT91_REG *) 0xFFFCC124) // (PDC_US3) PDC Transfer Status Register #define AT91C_US3_TNCR ((AT91_REG *) 0xFFFCC11C) // (PDC_US3) Transmit Next Counter Register #define AT91C_US3_RNCR ((AT91_REG *) 0xFFFCC114) // (PDC_US3) Receive Next Counter Register #define AT91C_US3_TCR ((AT91_REG *) 0xFFFCC10C) // (PDC_US3) Transmit Counter Register #define AT91C_US3_RCR ((AT91_REG *) 0xFFFCC104) // (PDC_US3) Receive Counter Register #define AT91C_US3_PTCR ((AT91_REG *) 0xFFFCC120) // (PDC_US3) PDC Transfer Control Register #define AT91C_US3_TNPR ((AT91_REG *) 0xFFFCC118) // (PDC_US3) Transmit Next Pointer Register #define AT91C_US3_RNPR ((AT91_REG *) 0xFFFCC110) // (PDC_US3) Receive Next Pointer Register #define AT91C_US3_TPR ((AT91_REG *) 0xFFFCC108) // (PDC_US3) Transmit Pointer Register #define AT91C_US3_RPR ((AT91_REG *) 0xFFFCC100) // (PDC_US3) Receive Pointer Register // ========== Register definition for US3 peripheral ========== #define AT91C_US3_IF ((AT91_REG *) 0xFFFCC04C) // (US3) IRDA_FILTER Register #define AT91C_US3_NER ((AT91_REG *) 0xFFFCC044) // (US3) Nb Errors Register #define AT91C_US3_RTOR ((AT91_REG *) 0xFFFCC024) // (US3) Receiver Time-out Register #define AT91C_US3_THR ((AT91_REG *) 0xFFFCC01C) // (US3) Transmitter Holding Register #define AT91C_US3_CSR ((AT91_REG *) 0xFFFCC014) // (US3) Channel Status Register #define AT91C_US3_IDR ((AT91_REG *) 0xFFFCC00C) // (US3) Interrupt Disable Register #define AT91C_US3_MR ((AT91_REG *) 0xFFFCC004) // (US3) Mode Register #define AT91C_US3_XXR ((AT91_REG *) 0xFFFCC048) // (US3) XON_XOFF Register #define AT91C_US3_FIDI ((AT91_REG *) 0xFFFCC040) // (US3) FI_DI_Ratio Register #define AT91C_US3_TTGR ((AT91_REG *) 0xFFFCC028) // (US3) Transmitter Time-guard Register #define AT91C_US3_BRGR ((AT91_REG *) 0xFFFCC020) // (US3) Baud Rate Generator Register #define AT91C_US3_RHR ((AT91_REG *) 0xFFFCC018) // (US3) Receiver Holding Register #define AT91C_US3_IMR ((AT91_REG *) 0xFFFCC010) // (US3) Interrupt Mask Register #define AT91C_US3_IER ((AT91_REG *) 0xFFFCC008) // (US3) Interrupt Enable Register #define AT91C_US3_CR ((AT91_REG *) 0xFFFCC000) // (US3) Control Register // ========== Register definition for PDC_US2 peripheral ========== #define AT91C_US2_PTSR ((AT91_REG *) 0xFFFC8124) // (PDC_US2) PDC Transfer Status Register #define AT91C_US2_TNCR ((AT91_REG *) 0xFFFC811C) // (PDC_US2) Transmit Next Counter Register #define AT91C_US2_RNCR ((AT91_REG *) 0xFFFC8114) // (PDC_US2) Receive Next Counter Register #define AT91C_US2_TCR ((AT91_REG *) 0xFFFC810C) // (PDC_US2) Transmit Counter Register #define AT91C_US2_PTCR ((AT91_REG *) 0xFFFC8120) // (PDC_US2) PDC Transfer Control Register #define AT91C_US2_RCR ((AT91_REG *) 0xFFFC8104) // (PDC_US2) Receive Counter Register #define AT91C_US2_TNPR ((AT91_REG *) 0xFFFC8118) // (PDC_US2) Transmit Next Pointer Register #define AT91C_US2_RPR ((AT91_REG *) 0xFFFC8100) // (PDC_US2) Receive Pointer Register #define AT91C_US2_TPR ((AT91_REG *) 0xFFFC8108) // (PDC_US2) Transmit Pointer Register #define AT91C_US2_RNPR ((AT91_REG *) 0xFFFC8110) // (PDC_US2) Receive Next Pointer Register // ========== Register definition for US2 peripheral ========== #define AT91C_US2_XXR ((AT91_REG *) 0xFFFC8048) // (US2) XON_XOFF Register #define AT91C_US2_FIDI ((AT91_REG *) 0xFFFC8040) // (US2) FI_DI_Ratio Register #define AT91C_US2_TTGR ((AT91_REG *) 0xFFFC8028) // (US2) Transmitter Time-guard Register #define AT91C_US2_BRGR ((AT91_REG *) 0xFFFC8020) // (US2) Baud Rate Generator Register #define AT91C_US2_RHR ((AT91_REG *) 0xFFFC8018) // (US2) Receiver Holding Register #define AT91C_US2_IMR ((AT91_REG *) 0xFFFC8010) // (US2) Interrupt Mask Register #define AT91C_US2_IER ((AT91_REG *) 0xFFFC8008) // (US2) Interrupt Enable Register #define AT91C_US2_CR ((AT91_REG *) 0xFFFC8000) // (US2) Control Register #define AT91C_US2_IF ((AT91_REG *) 0xFFFC804C) // (US2) IRDA_FILTER Register #define AT91C_US2_NER ((AT91_REG *) 0xFFFC8044) // (US2) Nb Errors Register #define AT91C_US2_RTOR ((AT91_REG *) 0xFFFC8024) // (US2) Receiver Time-out Register #define AT91C_US2_THR ((AT91_REG *) 0xFFFC801C) // (US2) Transmitter Holding Register #define AT91C_US2_CSR ((AT91_REG *) 0xFFFC8014) // (US2) Channel Status Register #define AT91C_US2_IDR ((AT91_REG *) 0xFFFC800C) // (US2) Interrupt Disable Register #define AT91C_US2_MR ((AT91_REG *) 0xFFFC8004) // (US2) Mode Register // ========== Register definition for PDC_US1 peripheral ========== #define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register #define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register #define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register #define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register #define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register #define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register #define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register #define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register #define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register #define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register // ========== Register definition for US1 peripheral ========== #define AT91C_US1_XXR ((AT91_REG *) 0xFFFC4048) // (US1) XON_XOFF Register #define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register #define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register #define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register #define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register #define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register #define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register #define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register #define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register #define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register #define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register #define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register #define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register #define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register #define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register // ========== Register definition for PDC_US0 peripheral ========== #define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register #define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register #define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register #define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register #define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register #define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register #define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register #define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register #define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register #define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register // ========== Register definition for US0 peripheral ========== #define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register #define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register #define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register #define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register #define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register #define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register #define AT91C_US0_XXR ((AT91_REG *) 0xFFFC0048) // (US0) XON_XOFF Register #define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register #define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register #define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register #define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register #define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register #define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register #define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register #define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register // ========== Register definition for TWI peripheral ========== #define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register #define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register #define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register #define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register #define AT91C_TWI_SMR ((AT91_REG *) 0xFFFB8008) // (TWI) Slave Mode Register #define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register #define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register #define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register #define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register #define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register #define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register // ========== Register definition for PDC_MCI peripheral ========== #define AT91C_MCI_PTCR ((AT91_REG *) 0xFFFB4120) // (PDC_MCI) PDC Transfer Control Register #define AT91C_MCI_TNPR ((AT91_REG *) 0xFFFB4118) // (PDC_MCI) Transmit Next Pointer Register #define AT91C_MCI_RNPR ((AT91_REG *) 0xFFFB4110) // (PDC_MCI) Receive Next Pointer Register #define AT91C_MCI_TPR ((AT91_REG *) 0xFFFB4108) // (PDC_MCI) Transmit Pointer Register #define AT91C_MCI_RPR ((AT91_REG *) 0xFFFB4100) // (PDC_MCI) Receive Pointer Register #define AT91C_MCI_PTSR ((AT91_REG *) 0xFFFB4124) // (PDC_MCI) PDC Transfer Status Register #define AT91C_MCI_TNCR ((AT91_REG *) 0xFFFB411C) // (PDC_MCI) Transmit Next Counter Register #define AT91C_MCI_RNCR ((AT91_REG *) 0xFFFB4114) // (PDC_MCI) Receive Next Counter Register #define AT91C_MCI_TCR ((AT91_REG *) 0xFFFB410C) // (PDC_MCI) Transmit Counter Register #define AT91C_MCI_RCR ((AT91_REG *) 0xFFFB4104) // (PDC_MCI) Receive Counter Register // ========== Register definition for MCI peripheral ========== #define AT91C_MCI_IDR ((AT91_REG *) 0xFFFB4048) // (MCI) MCI Interrupt Disable Register #define AT91C_MCI_SR ((AT91_REG *) 0xFFFB4040) // (MCI) MCI Status Register #define AT91C_MCI_RDR ((AT91_REG *) 0xFFFB4030) // (MCI) MCI Receive Data Register #define AT91C_MCI_RSPR ((AT91_REG *) 0xFFFB4020) // (MCI) MCI Response Register #define AT91C_MCI_ARGR ((AT91_REG *) 0xFFFB4010) // (MCI) MCI Argument Register #define AT91C_MCI_DTOR ((AT91_REG *) 0xFFFB4008) // (MCI) MCI Data Timeout Register #define AT91C_MCI_CR ((AT91_REG *) 0xFFFB4000) // (MCI) MCI Control Register #define AT91C_MCI_IMR ((AT91_REG *) 0xFFFB404C) // (MCI) MCI Interrupt Mask Register #define AT91C_MCI_IER ((AT91_REG *) 0xFFFB4044) // (MCI) MCI Interrupt Enable Register #define AT91C_MCI_TDR ((AT91_REG *) 0xFFFB4034) // (MCI) MCI Transmit Data Register #define AT91C_MCI_CMDR ((AT91_REG *) 0xFFFB4014) // (MCI) MCI Command Register #define AT91C_MCI_SDCR ((AT91_REG *) 0xFFFB400C) // (MCI) MCI SD Card Register #define AT91C_MCI_MR ((AT91_REG *) 0xFFFB4004) // (MCI) MCI Mode Register // ========== Register definition for UDP peripheral ========== #define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register #define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register #define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register #define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register #define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register #define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register #define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register #define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register #define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register #define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register #define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register // ========== Register definition for TC5 peripheral ========== #define AT91C_TC5_CMR ((AT91_REG *) 0xFFFA4084) // (TC5) Channel Mode Register #define AT91C_TC5_IDR ((AT91_REG *) 0xFFFA40A8) // (TC5) Interrupt Disable Register #define AT91C_TC5_SR ((AT91_REG *) 0xFFFA40A0) // (TC5) Status Register #define AT91C_TC5_RB ((AT91_REG *) 0xFFFA4098) // (TC5) Register B #define AT91C_TC5_CV ((AT91_REG *) 0xFFFA4090) // (TC5) Counter Value #define AT91C_TC5_CCR ((AT91_REG *) 0xFFFA4080) // (TC5) Channel Control Register #define AT91C_TC5_IMR ((AT91_REG *) 0xFFFA40AC) // (TC5) Interrupt Mask Register #define AT91C_TC5_IER ((AT91_REG *) 0xFFFA40A4) // (TC5) Interrupt Enable Register #define AT91C_TC5_RC ((AT91_REG *) 0xFFFA409C) // (TC5) Register C #define AT91C_TC5_RA ((AT91_REG *) 0xFFFA4094) // (TC5) Register A // ========== Register definition for TC4 peripheral ========== #define AT91C_TC4_IMR ((AT91_REG *) 0xFFFA406C) // (TC4) Interrupt Mask Register #define AT91C_TC4_IER ((AT91_REG *) 0xFFFA4064) // (TC4) Interrupt Enable Register #define AT91C_TC4_RC ((AT91_REG *) 0xFFFA405C) // (TC4) Register C #define AT91C_TC4_RA ((AT91_REG *) 0xFFFA4054) // (TC4) Register A #define AT91C_TC4_CMR ((AT91_REG *) 0xFFFA4044) // (TC4) Channel Mode Register #define AT91C_TC4_IDR ((AT91_REG *) 0xFFFA4068) // (TC4) Interrupt Disable Register #define AT91C_TC4_SR ((AT91_REG *) 0xFFFA4060) // (TC4) Status Register #define AT91C_TC4_RB ((AT91_REG *) 0xFFFA4058) // (TC4) Register B #define AT91C_TC4_CV ((AT91_REG *) 0xFFFA4050) // (TC4) Counter Value #define AT91C_TC4_CCR ((AT91_REG *) 0xFFFA4040) // (TC4) Channel Control Register // ========== Register definition for TC3 peripheral ========== #define AT91C_TC3_IMR ((AT91_REG *) 0xFFFA402C) // (TC3) Interrupt Mask Register #define AT91C_TC3_CV ((AT91_REG *) 0xFFFA4010) // (TC3) Counter Value #define AT91C_TC3_CCR ((AT91_REG *) 0xFFFA4000) // (TC3) Channel Control Register #define AT91C_TC3_IER ((AT91_REG *) 0xFFFA4024) // (TC3) Interrupt Enable Register #define AT91C_TC3_CMR ((AT91_REG *) 0xFFFA4004) // (TC3) Channel Mode Register #define AT91C_TC3_RA ((AT91_REG *) 0xFFFA4014) // (TC3) Register A #define AT91C_TC3_RC ((AT91_REG *) 0xFFFA401C) // (TC3) Register C #define AT91C_TC3_IDR ((AT91_REG *) 0xFFFA4028) // (TC3) Interrupt Disable Register #define AT91C_TC3_RB ((AT91_REG *) 0xFFFA4018) // (TC3) Register B #define AT91C_TC3_SR ((AT91_REG *) 0xFFFA4020) // (TC3) Status Register // ========== Register definition for TCB1 peripheral ========== #define AT91C_TCB1_BCR ((AT91_REG *) 0xFFFA4140) // (TCB1) TC Block Control Register #define AT91C_TCB1_BMR ((AT91_REG *) 0xFFFA4144) // (TCB1) TC Block Mode Register // ========== Register definition for TC2 peripheral ========== #define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register #define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register #define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C #define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A #define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register #define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register #define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B #define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value #define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register // ========== Register definition for TC1 peripheral ========== #define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register #define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register #define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C #define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A #define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register #define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register #define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B #define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value #define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register // ========== Register definition for TC0 peripheral ========== #define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register #define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register #define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C #define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A #define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register #define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register #define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B #define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value #define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register // ========== Register definition for TCB0 peripheral ========== #define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB0) TC Block Mode Register #define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB0) TC Block Control Register // ========== Register definition for UHP peripheral ========== #define AT91C_UHP_HcRhDescriptorA ((AT91_REG *) 0x00300048) // (UHP) Root Hub characteristics A #define AT91C_UHP_HcRhPortStatus ((AT91_REG *) 0x00300054) // (UHP) Root Hub Port Status Register #define AT91C_UHP_HcRhDescriptorB ((AT91_REG *) 0x0030004C) // (UHP) Root Hub characteristics B #define AT91C_UHP_HcControl ((AT91_REG *) 0x00300004) // (UHP) Operating modes for the Host Controller #define AT91C_UHP_HcInterruptStatus ((AT91_REG *) 0x0030000C) // (UHP) Interrupt Status Register #define AT91C_UHP_HcRhStatus ((AT91_REG *) 0x00300050) // (UHP) Root Hub Status register #define AT91C_UHP_HcRevision ((AT91_REG *) 0x00300000) // (UHP) Revision #define AT91C_UHP_HcCommandStatus ((AT91_REG *) 0x00300008) // (UHP) Command & status Register #define AT91C_UHP_HcInterruptEnable ((AT91_REG *) 0x00300010) // (UHP) Interrupt Enable Register #define AT91C_UHP_HcHCCA ((AT91_REG *) 0x00300018) // (UHP) Pointer to the Host Controller Communication Area #define AT91C_UHP_HcControlHeadED ((AT91_REG *) 0x00300020) // (UHP) First Endpoint Descriptor of the Control list #define AT91C_UHP_HcInterruptDisable ((AT91_REG *) 0x00300014) // (UHP) Interrupt Disable Register #define AT91C_UHP_HcPeriodCurrentED ((AT91_REG *) 0x0030001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor #define AT91C_UHP_HcControlCurrentED ((AT91_REG *) 0x00300024) // (UHP) Endpoint Control and Status Register #define AT91C_UHP_HcBulkCurrentED ((AT91_REG *) 0x0030002C) // (UHP) Current endpoint of the Bulk list #define AT91C_UHP_HcFmInterval ((AT91_REG *) 0x00300034) // (UHP) Bit time between 2 consecutive SOFs #define AT91C_UHP_HcBulkHeadED ((AT91_REG *) 0x00300028) // (UHP) First endpoint register of the Bulk list #define AT91C_UHP_HcBulkDoneHead ((AT91_REG *) 0x00300030) // (UHP) Last completed transfer descriptor #define AT91C_UHP_HcFmRemaining ((AT91_REG *) 0x00300038) // (UHP) Bit time remaining in the current Frame #define AT91C_UHP_HcPeriodicStart ((AT91_REG *) 0x00300040) // (UHP) Periodic Start #define AT91C_UHP_HcLSThreshold ((AT91_REG *) 0x00300044) // (UHP) LS Threshold #define AT91C_UHP_HcFmNumber ((AT91_REG *) 0x0030003C) // (UHP) Frame number // ========== Register definition for EMAC peripheral ========== #define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFBC020) // (EMAC) Receive Status Register #define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFBC034) // (EMAC) PHY Maintenance Register #define AT91C_EMAC_HSH ((AT91_REG *) 0xFFFBC090) // (EMAC) Hash Address High[63:32] #define AT91C_EMAC_MCOL ((AT91_REG *) 0xFFFBC048) // (EMAC) Multiple Collision Frame Register #define AT91C_EMAC_IER ((AT91_REG *) 0xFFFBC028) // (EMAC) Interrupt Enable Register #define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFBC0A4) // (EMAC) Specific Address 2 High, Last 2 bytes #define AT91C_EMAC_HSL ((AT91_REG *) 0xFFFBC094) // (EMAC) Hash Address Low[31:0] #define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFBC05C) // (EMAC) Late Collision Register #define AT91C_EMAC_OK ((AT91_REG *) 0xFFFBC04C) // (EMAC) Frames Received OK Register #define AT91C_EMAC_CFG ((AT91_REG *) 0xFFFBC004) // (EMAC) Network Configuration Register #define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFBC0A8) // (EMAC) Specific Address 3 Low, First 4 bytes #define AT91C_EMAC_SEQE ((AT91_REG *) 0xFFFBC050) // (EMAC) Frame Check Sequence Error Register #define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFBC060) // (EMAC) Excessive Collision Register #define AT91C_EMAC_ELR ((AT91_REG *) 0xFFFBC070) // (EMAC) Excessive Length Error Register #define AT91C_EMAC_SR ((AT91_REG *) 0xFFFBC008) // (EMAC) Network Status Register #define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFBC018) // (EMAC) Receive Buffer Queue Pointer #define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFBC064) // (EMAC) Carrier Sense Error Register #define AT91C_EMAC_RJB ((AT91_REG *) 0xFFFBC074) // (EMAC) Receive Jabber Register #define AT91C_EMAC_USF ((AT91_REG *) 0xFFFBC078) // (EMAC) Undersize Frame Register #define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFBC02C) // (EMAC) Interrupt Disable Register #define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFBC098) // (EMAC) Specific Address 1 Low, First 4 bytes #define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFBC030) // (EMAC) Interrupt Mask Register #define AT91C_EMAC_FRA ((AT91_REG *) 0xFFFBC040) // (EMAC) Frames Transmitted OK Register #define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFBC0AC) // (EMAC) Specific Address 3 High, Last 2 bytes #define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFBC09C) // (EMAC) Specific Address 1 High, Last 2 bytes #define AT91C_EMAC_SCOL ((AT91_REG *) 0xFFFBC044) // (EMAC) Single Collision Frame Register #define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFBC054) // (EMAC) Alignment Error Register #define AT91C_EMAC_TAR ((AT91_REG *) 0xFFFBC00C) // (EMAC) Transmit Address Register #define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFBC0B0) // (EMAC) Specific Address 4 Low, First 4 bytes #define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFBC0A0) // (EMAC) Specific Address 2 Low, First 4 bytes #define AT91C_EMAC_TUE ((AT91_REG *) 0xFFFBC068) // (EMAC) Transmit Underrun Error Register #define AT91C_EMAC_DTE ((AT91_REG *) 0xFFFBC058) // (EMAC) Deferred Transmission Frame Register #define AT91C_EMAC_TCR ((AT91_REG *) 0xFFFBC010) // (EMAC) Transmit Control Register #define AT91C_EMAC_CTL ((AT91_REG *) 0xFFFBC000) // (EMAC) Network Control Register #define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFBC0B4) // (EMAC) Specific Address 4 High, Last 2 bytesr #define AT91C_EMAC_CDE ((AT91_REG *) 0xFFFBC06C) // (EMAC) Code Error Register #define AT91C_EMAC_SQEE ((AT91_REG *) 0xFFFBC07C) // (EMAC) SQE Test Error Register #define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFBC014) // (EMAC) Transmit Status Register #define AT91C_EMAC_DRFC ((AT91_REG *) 0xFFFBC080) // (EMAC) Discarded RX Frame Register // ========== Register definition for EBI peripheral ========== #define AT91C_EBI_CFGR ((AT91_REG *) 0xFFFFFF64) // (EBI) Configuration Register #define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) // (EBI) Chip Select Assignment Register // ========== Register definition for SMC2 peripheral ========== #define AT91C_SMC2_CSR ((AT91_REG *) 0xFFFFFF70) // (SMC2) SMC2 Chip Select Register // ========== Register definition for SDRC peripheral ========== #define AT91C_SDRC_IMR ((AT91_REG *) 0xFFFFFFAC) // (SDRC) SDRAM Controller Interrupt Mask Register #define AT91C_SDRC_IER ((AT91_REG *) 0xFFFFFFA4) // (SDRC) SDRAM Controller Interrupt Enable Register #define AT91C_SDRC_SRR ((AT91_REG *) 0xFFFFFF9C) // (SDRC) SDRAM Controller Self Refresh Register #define AT91C_SDRC_TR ((AT91_REG *) 0xFFFFFF94) // (SDRC) SDRAM Controller Refresh Timer Register #define AT91C_SDRC_ISR ((AT91_REG *) 0xFFFFFFB0) // (SDRC) SDRAM Controller Interrupt Mask Register #define AT91C_SDRC_IDR ((AT91_REG *) 0xFFFFFFA8) // (SDRC) SDRAM Controller Interrupt Disable Register #define AT91C_SDRC_LPR ((AT91_REG *) 0xFFFFFFA0) // (SDRC) SDRAM Controller Low Power Register #define AT91C_SDRC_CR ((AT91_REG *) 0xFFFFFF98) // (SDRC) SDRAM Controller Configuration Register #define AT91C_SDRC_MR ((AT91_REG *) 0xFFFFFF90) // (SDRC) SDRAM Controller Mode Register // ========== Register definition for BFC peripheral ========== #define AT91C_BFC_MR ((AT91_REG *) 0xFFFFFFC0) // (BFC) BFC Mode Register #include // ***************************************************************************** // PERIPHERAL ID DEFINITIONS FOR AT91RM9200 // ***************************************************************************** #define AT91C_ID_FIQ 0u // Advanced Interrupt Controller (FIQ) #define AT91C_ID_SYS 1u // System Peripheral #define AT91C_ID_PIOA 2u // Parallel IO Controller A #define AT91C_ID_PIOB 3u // Parallel IO Controller B #define AT91C_ID_PIOC 4u // Parallel IO Controller C #define AT91C_ID_PIOD 5u // Parallel IO Controller D #define AT91C_ID_US0 6u // USART 0 #define AT91C_ID_US1 7u // USART 1 #define AT91C_ID_US2 8u // USART 2 #define AT91C_ID_US3 9u // USART 3 #define AT91C_ID_MCI 10u // Multimedia Card Interface #define AT91C_ID_UDP 11u // USB Device Port #define AT91C_ID_TWI 12u // Two-Wire Interface #define AT91C_ID_SPI 13u // Serial Peripheral Interface #define AT91C_ID_SSC0 14u // Serial Synchronous Controller 0 #define AT91C_ID_SSC1 15u // Serial Synchronous Controller 1 #define AT91C_ID_SSC2 16u // Serial Synchronous Controller 2 #define AT91C_ID_TC0 17u // Timer Counter 0 #define AT91C_ID_TC1 18u // Timer Counter 1 #define AT91C_ID_TC2 19u // Timer Counter 2 #define AT91C_ID_TC3 20u // Timer Counter 3 #define AT91C_ID_TC4 21u // Timer Counter 4 #define AT91C_ID_TC5 22u // Timer Counter 5 #define AT91C_ID_UHP 23u // USB Host port #define AT91C_ID_EMAC 24u // Ethernet MAC #define AT91C_ID_IRQ0 25u // Advanced Interrupt Controller (IRQ0) #define AT91C_ID_IRQ1 26u // Advanced Interrupt Controller (IRQ1) #define AT91C_ID_IRQ2 27u // Advanced Interrupt Controller (IRQ2) #define AT91C_ID_IRQ3 28u // Advanced Interrupt Controller (IRQ3) #define AT91C_ID_IRQ4 29u // Advanced Interrupt Controller (IRQ4) #define AT91C_ID_IRQ5 30u // Advanced Interrupt Controller (IRQ5) #define AT91C_ID_IRQ6 31u // Advanced Interrupt Controller (IRQ6) // ***************************************************************************** // BASE ADDRESS DEFINITIONS FOR AT91RM9200 // ***************************************************************************** #define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address #define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address #define AT91C_BASE_RTC ((AT91PS_RTC) 0xFFFFFE00) // (RTC) Base Address #define AT91C_BASE_ST ((AT91PS_ST) 0xFFFFFD00) // (ST) Base Address #define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address #define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address #define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFFA00) // (PIOD) Base Address #define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) // (PIOC) Base Address #define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address #define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address #define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address #define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address #define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address #define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address #define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address #define AT91C_BASE_PDC_SSC2 ((AT91PS_PDC) 0xFFFD8100) // (PDC_SSC2) Base Address #define AT91C_BASE_SSC2 ((AT91PS_SSC) 0xFFFD8000) // (SSC2) Base Address #define AT91C_BASE_PDC_SSC1 ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC1) Base Address #define AT91C_BASE_SSC1 ((AT91PS_SSC) 0xFFFD4000) // (SSC1) Base Address #define AT91C_BASE_PDC_SSC0 ((AT91PS_PDC) 0xFFFD0100) // (PDC_SSC0) Base Address #define AT91C_BASE_SSC0 ((AT91PS_SSC) 0xFFFD0000) // (SSC0) Base Address #define AT91C_BASE_PDC_US3 ((AT91PS_PDC) 0xFFFCC100) // (PDC_US3) Base Address #define AT91C_BASE_US3 ((AT91PS_USART) 0xFFFCC000) // (US3) Base Address #define AT91C_BASE_PDC_US2 ((AT91PS_PDC) 0xFFFC8100) // (PDC_US2) Base Address #define AT91C_BASE_US2 ((AT91PS_USART) 0xFFFC8000) // (US2) Base Address #define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address #define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address #define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address #define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address #define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address #define AT91C_BASE_PDC_MCI ((AT91PS_PDC) 0xFFFB4100) // (PDC_MCI) Base Address #define AT91C_BASE_MCI ((AT91PS_MCI) 0xFFFB4000) // (MCI) Base Address #define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address #define AT91C_BASE_TC5 ((AT91PS_TC) 0xFFFA4080) // (TC5) Base Address #define AT91C_BASE_TC4 ((AT91PS_TC) 0xFFFA4040) // (TC4) Base Address #define AT91C_BASE_TC3 ((AT91PS_TC) 0xFFFA4000) // (TC3) Base Address #define AT91C_BASE_TCB1 ((AT91PS_TCB) 0xFFFA4080) // (TCB1) Base Address #define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address #define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address #define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address #define AT91C_BASE_TCB0 ((AT91PS_TCB) 0xFFFA0000) // (TCB0) Base Address #define AT91C_BASE_UHP ((AT91PS_UHP) 0x00300000) // (UHP) Base Address #define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) // (EMAC) Base Address #define AT91C_BASE_EBI ((AT91PS_EBI) 0xFFFFFF60) // (EBI) Base Address #define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) // (SMC2) Base Address #define AT91C_BASE_SDRC ((AT91PS_SDRC) 0xFFFFFF90) // (SDRC) Base Address #define AT91C_BASE_BFC ((AT91PS_BFC) 0xFFFFFFC0) // (BFC) Base Address // ***************************************************************************** // MEMORY MAPPING DEFINITIONS FOR AT91RM9200 // ***************************************************************************** #define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address #define AT91C_ISRAM_SIZE 0x00004000u // Internal SRAM size in byte (16 Kbyte) #define AT91C_IROM ((char *) 0x00100000) // Internal ROM base address #define AT91C_IROM_SIZE 0x00020000u // Internal ROM size in byte (128 Kbyte) #endif Index: head/sys/boot/arm/at91/libat91/mci_device.h =================================================================== --- head/sys/boot/arm/at91/libat91/mci_device.h (revision 298825) +++ head/sys/boot/arm/at91/libat91/mci_device.h (revision 298826) @@ -1,434 +1,434 @@ /*- * Copyright (c) 2006 M. Warner Losh. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * This software is derived from software provide by Kwikbyte who specifically * disclaimed copyright on the code. * * $FreeBSD$ */ //*--------------------------------------------------------------------------- //* ATMEL Microcontroller Software Support - ROUSSET - //*--------------------------------------------------------------------------- //* The software is delivered "AS IS" without warranty or condition of any //* kind, either express, implied or statutory. This includes without //* limitation any warranty or condition with respect to merchantability or //* fitness for any particular purpose, or against the infringements of //* intellectual property rights of others. //*--------------------------------------------------------------------------- //* File Name : AT91C_MCI_Device.h //* Object : Data Flash Atmel Description File //* Translator : //* //* 1.0 26/11/02 FB : Creation //*--------------------------------------------------------------------------- #ifndef __MCI_Device_h #define __MCI_Device_h #include typedef unsigned int AT91S_MCIDeviceStatus; /////////////////////////////////////////////////////////////////////////////// #define AT91C_CARD_REMOVED 0 #define AT91C_MMC_CARD_INSERTED 1 #define AT91C_SD_CARD_INSERTED 2 #define AT91C_NO_ARGUMENT 0x0 #define AT91C_FIRST_RCA 0xCAFE #define AT91C_MAX_MCI_CARDS 10 #define AT91C_BUS_WIDTH_1BIT 0x00 #define AT91C_BUS_WIDTH_4BITS 0x02 /* Driver State */ #define AT91C_MCI_IDLE 0x0 #define AT91C_MCI_TIMEOUT_ERROR 0x1 #define AT91C_MCI_RX_SINGLE_BLOCK 0x2 #define AT91C_MCI_RX_MULTIPLE_BLOCK 0x3 #define AT91C_MCI_RX_STREAM 0x4 #define AT91C_MCI_TX_SINGLE_BLOCK 0x5 #define AT91C_MCI_TX_MULTIPLE_BLOCK 0x6 #define AT91C_MCI_TX_STREAM 0x7 /* TimeOut */ #define AT91C_TIMEOUT_CMDRDY 30 /////////////////////////////////////////////////////////////////////////////// // MMC & SDCard Structures /////////////////////////////////////////////////////////////////////////////// /*---------------------------------------------*/ /* MCI Device Structure Definition */ /*---------------------------------------------*/ typedef struct _AT91S_MciDevice { volatile unsigned char state; unsigned char SDCard_bus_width; unsigned char IsSDv2; unsigned char IsSDHC; unsigned int RCA; // RCA unsigned int READ_BL_LEN; #ifdef REPORT_SIZE unsigned int Memory_Capacity; #endif } AT91S_MciDevice; #include /////////////////////////////////////////////////////////////////////////////// // Functions returnals /////////////////////////////////////////////////////////////////////////////// #define AT91C_CMD_SEND_OK 0 // Command ok #define AT91C_CMD_SEND_ERROR -1 // Command failed -#define AT91C_INIT_OK 2 // Init Successfull +#define AT91C_INIT_OK 2 // Init Successful #define AT91C_INIT_ERROR 3 // Init Failed -#define AT91C_READ_OK 4 // Read Successfull +#define AT91C_READ_OK 4 // Read Successful #define AT91C_READ_ERROR 5 // Read Failed -#define AT91C_WRITE_OK 6 // Write Successfull +#define AT91C_WRITE_OK 6 // Write Successful #define AT91C_WRITE_ERROR 7 // Write Failed -#define AT91C_ERASE_OK 8 // Erase Successfull +#define AT91C_ERASE_OK 8 // Erase Successful #define AT91C_ERASE_ERROR 9 // Erase Failed -#define AT91C_CARD_SELECTED_OK 10 // Card Selection Successfull +#define AT91C_CARD_SELECTED_OK 10 // Card Selection Successful #define AT91C_CARD_SELECTED_ERROR 11 // Card Selection Failed #define AT91C_MCI_SR_ERROR (AT91C_MCI_UNRE | AT91C_MCI_OVRE | AT91C_MCI_DTOE | \ AT91C_MCI_DCRCE | AT91C_MCI_RTOE | AT91C_MCI_RENDE | AT91C_MCI_RCRCE | \ AT91C_MCI_RDIRE | AT91C_MCI_RINDE) #define MMC_CMDNB (0x1Fu << 0) // Command Number #define MMC_RSPTYP (0x3u << 6) // Response Type #define MMC_RSPTYP_NO (0x0u << 6) // No response #define MMC_RSPTYP_48 (0x1u << 6) // 48-bit response #define MMC_RSPTYP_136 (0x2u << 6) // 136-bit response #define MMC_SPCMD (0x7u << 8) // Special CMD #define MMC_SPCMD_NONE (0x0u << 8) // Not a special CMD #define MMC_SPCMD_INIT (0x1u << 8) // Initialization CMD #define MMC_SPCMD_SYNC (0x2u << 8) // Synchronized CMD #define MMC_SPCMD_IT_CMD (0x4u << 8) // Interrupt command #define MMC_SPCMD_IT_REP (0x5u << 8) // Interrupt response #define MMC_OPDCMD (0x1u << 11) // Open Drain Command #define MMC_MAXLAT (0x1u << 12) // Maximum Latency for Command to respond #define MMC_TRCMD (0x3u << 16) // Transfer CMD #define MMC_TRCMD_NO (0x0u << 16) // No transfer #define MMC_TRCMD_START (0x1u << 16) // Start transfer #define MMC_TRCMD_STOP (0x2u << 16) // Stop transfer #define MMC_TRDIR (0x1u << 18) // Transfer Direction #define MMC_TRTYP (0x3u << 19) // Transfer Type #define MMC_TRTYP_BLOCK (0x0u << 19) // Block Transfer type #define MMC_TRTYP_MULTIPLE (0x1u << 19) // Multiple Block transfer type #define MMC_TRTYP_STREAM (0x2u << 19) // Stream transfer type /////////////////////////////////////////////////////////////////////////////// // MCI_CMD Register Value /////////////////////////////////////////////////////////////////////////////// #define POWER_ON_INIT \ (0 | MMC_TRCMD_NO | MMC_SPCMD_INIT | MMC_OPDCMD) ///////////////////////////////////////////////////////////////// // Class 0 & 1 commands: Basic commands and Read Stream commands ///////////////////////////////////////////////////////////////// #define GO_IDLE_STATE_CMD \ (0 | MMC_TRCMD_NO | MMC_SPCMD_NONE ) #define MMC_GO_IDLE_STATE_CMD \ (0 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_OPDCMD) #define MMC_SEND_OP_COND_CMD \ (1 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \ MMC_OPDCMD) #define ALL_SEND_CID_CMD \ (2 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136) #define MMC_ALL_SEND_CID_CMD \ (2 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136 | \ MMC_OPDCMD) #define SET_RELATIVE_ADDR_CMD \ (3 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \ MMC_MAXLAT) #define MMC_SET_RELATIVE_ADDR_CMD \ (3 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \ MMC_MAXLAT | MMC_OPDCMD) #define SET_DSR_CMD \ (4 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_NO | \ MMC_MAXLAT) // no tested #define SEL_DESEL_CARD_CMD \ (7 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \ MMC_MAXLAT) #define SEND_CSD_CMD \ (9 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136 | \ MMC_MAXLAT) #define SEND_CID_CMD \ (10 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136 | \ MMC_MAXLAT) #define MMC_READ_DAT_UNTIL_STOP_CMD \ (11 | MMC_TRTYP_STREAM | MMC_SPCMD_NONE | \ MMC_RSPTYP_48 | MMC_TRDIR | MMC_TRCMD_START | \ MMC_MAXLAT) #define STOP_TRANSMISSION_CMD \ (12 | MMC_TRCMD_STOP | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \ MMC_MAXLAT) #define STOP_TRANSMISSION_SYNC_CMD \ (12 | MMC_TRCMD_STOP | MMC_SPCMD_SYNC | MMC_RSPTYP_48 | \ MMC_MAXLAT) #define SEND_STATUS_CMD \ (13 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \ MMC_MAXLAT) #define GO_INACTIVE_STATE_CMD \ (15 | MMC_RSPTYP_NO) #define SD_SEND_IF_COND_CMD \ (8 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \ MMC_MAXLAT) //*------------------------------------------------ //* Class 2 commands: Block oriented Read commands //*------------------------------------------------ #define SET_BLOCKLEN_CMD (16 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_MAXLAT ) #define READ_SINGLE_BLOCK_CMD (17 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | MMC_TRTYP_BLOCK | MMC_TRDIR | MMC_MAXLAT) #define READ_MULTIPLE_BLOCK_CMD (18 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | MMC_TRTYP_MULTIPLE | MMC_TRDIR | MMC_MAXLAT) //*-------------------------------------------- //* Class 3 commands: Sequential write commands //*-------------------------------------------- #define MMC_WRITE_DAT_UNTIL_STOP_CMD (20 | MMC_TRTYP_STREAM| MMC_SPCMD_NONE | MMC_RSPTYP_48 & ~(MMC_TRDIR) | MMC_TRCMD_START | MMC_MAXLAT ) // MMC //*------------------------------------------------ //* Class 4 commands: Block oriented write commands //*------------------------------------------------ #define WRITE_BLOCK_CMD (24 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | (MMC_TRTYP_BLOCK & ~(MMC_TRDIR)) | MMC_MAXLAT) #define WRITE_MULTIPLE_BLOCK_CMD (25 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | (MMC_TRTYP_MULTIPLE & ~(MMC_TRDIR)) | MMC_MAXLAT) #define PROGRAM_CSD_CMD (27 | MMC_RSPTYP_48 ) //*---------------------------------------- //* Class 6 commands: Group Write protect //*---------------------------------------- #define SET_WRITE_PROT_CMD (28 | MMC_RSPTYP_48 ) #define CLR_WRITE_PROT_CMD (29 | MMC_RSPTYP_48 ) #define SEND_WRITE_PROT_CMD (30 | MMC_RSPTYP_48 ) //*---------------------------------------- //* Class 5 commands: Erase commands //*---------------------------------------- #define TAG_SECTOR_START_CMD (32 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) #define TAG_SECTOR_END_CMD (33 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) #define MMC_UNTAG_SECTOR_CMD (34 | MMC_RSPTYP_48 ) #define MMC_TAG_ERASE_GROUP_START_CMD (35 | MMC_RSPTYP_48 ) #define MMC_TAG_ERASE_GROUP_END_CMD (36 | MMC_RSPTYP_48 ) #define MMC_UNTAG_ERASE_GROUP_CMD (37 | MMC_RSPTYP_48 ) #define ERASE_CMD (38 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT ) //*---------------------------------------- //* Class 7 commands: Lock commands //*---------------------------------------- #define LOCK_UNLOCK (42 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) // no tested //*----------------------------------------------- // Class 8 commands: Application specific commands //*----------------------------------------------- #define APP_CMD (55 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) #define GEN_CMD (56 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) // no tested #define SDCARD_SET_BUS_WIDTH_CMD (6 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) #define SDCARD_STATUS_CMD (13 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) #define SDCARD_SEND_NUM_WR_BLOCKS_CMD (22 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) #define SDCARD_SET_WR_BLK_ERASE_COUNT_CMD (23 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) #define SDCARD_APP_OP_COND_CMD (41 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) #define SDCARD_SET_CLR_CARD_DETECT_CMD (42 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) #define SDCARD_SEND_SCR_CMD (51 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) #define SDCARD_APP_ALL_CMD (SDCARD_SET_BUS_WIDTH_CMD +\ SDCARD_STATUS_CMD +\ SDCARD_SEND_NUM_WR_BLOCKS_CMD +\ SDCARD_SET_WR_BLK_ERASE_COUNT_CMD +\ SDCARD_APP_OP_COND_CMD +\ SDCARD_SET_CLR_CARD_DETECT_CMD +\ SDCARD_SEND_SCR_CMD) //*---------------------------------------- //* Class 9 commands: IO Mode commands //*---------------------------------------- #define MMC_FAST_IO_CMD (39 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_MAXLAT) #define MMC_GO_IRQ_STATE_CMD (40 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) /////////////////////////////////////////////////////////////////////////////// // OCR Register /////////////////////////////////////////////////////////////////////////////// #define AT91C_VDD_16_17 (1 << 4) #define AT91C_VDD_17_18 (1 << 5) #define AT91C_VDD_18_19 (1 << 6) #define AT91C_VDD_19_20 (1 << 7) #define AT91C_VDD_20_21 (1 << 8) #define AT91C_VDD_21_22 (1 << 9) #define AT91C_VDD_22_23 (1 << 10) #define AT91C_VDD_23_24 (1 << 11) #define AT91C_VDD_24_25 (1 << 12) #define AT91C_VDD_25_26 (1 << 13) #define AT91C_VDD_26_27 (1 << 14) #define AT91C_VDD_27_28 (1 << 15) #define AT91C_VDD_28_29 (1 << 16) #define AT91C_VDD_29_30 (1 << 17) #define AT91C_VDD_30_31 (1 << 18) #define AT91C_VDD_31_32 (1 << 19) #define AT91C_VDD_32_33 (1 << 20) #define AT91C_VDD_33_34 (1 << 21) #define AT91C_VDD_34_35 (1 << 22) #define AT91C_VDD_35_36 (1 << 23) #define AT91C_CCS (1 << 30) #define AT91C_CARD_POWER_UP_DONE (1U << 31) #define AT91C_MMC_HOST_VOLTAGE_RANGE (AT91C_VDD_27_28 | AT91C_VDD_28_29 | \ AT91C_VDD_29_30 | AT91C_VDD_30_31 | AT91C_VDD_31_32 | AT91C_VDD_32_33) /////////////////////////////////////////////////////////////////////////////// // CURRENT_STATE & READY_FOR_DATA in SDCard Status Register definition (response type R1) /////////////////////////////////////////////////////////////////////////////// #define AT91C_SR_READY_FOR_DATA (1 << 8) // corresponds to buffer empty signalling on the bus #define AT91C_SR_IDLE (0 << 9) #define AT91C_SR_READY (1 << 9) #define AT91C_SR_IDENT (2 << 9) #define AT91C_SR_STBY (3 << 9) #define AT91C_SR_TRAN (4 << 9) #define AT91C_SR_DATA (5 << 9) #define AT91C_SR_RCV (6 << 9) #define AT91C_SR_PRG (7 << 9) #define AT91C_SR_DIS (8 << 9) #define AT91C_SR_CARD_SELECTED (AT91C_SR_READY_FOR_DATA + AT91C_SR_TRAN) #define MMC_FIRST_RCA 0xCAFE /////////////////////////////////////////////////////////////////////////////// // MMC CSD register header File // CSD_x_xxx_S for shift value for word x // CSD_x_xxx_M for mask value for word x /////////////////////////////////////////////////////////////////////////////// // First Response INT <=> CSD[3] : bits 0 to 31 #define CSD_3_BIT0_S 0 // [0:0] #define CSD_3_BIT0_M 0x01 #define CSD_3_CRC_S 1 // [7:1] #define CSD_3_CRC_M 0x7F #define CSD_3_MMC_ECC_S 8 // [9:8] reserved for MMC compatibility #define CSD_3_MMC_ECC_M 0x03 #define CSD_3_FILE_FMT_S 10 // [11:10] #define CSD_3_FILE_FMT_M 0x03 #define CSD_3_TMP_WP_S 12 // [12:12] #define CSD_3_TMP_WP_M 0x01 #define CSD_3_PERM_WP_S 13 // [13:13] #define CSD_3_PERM_WP_M 0x01 #define CSD_3_COPY_S 14 // [14:14] #define CSD_3_COPY_M 0x01 #define CSD_3_FILE_FMT_GRP_S 15 // [15:15] #define CSD_3_FILE_FMT_GRP_M 0x01 // reserved 16 // [20:16] // reserved 0x1F #define CSD_3_WBLOCK_P_S 21 // [21:21] #define CSD_3_WBLOCK_P_M 0x01 #define CSD_3_WBLEN_S 22 // [25:22] #define CSD_3_WBLEN_M 0x0F #define CSD_3_R2W_F_S 26 // [28:26] #define CSD_3_R2W_F_M 0x07 #define CSD_3_MMC_DEF_ECC_S 29 // [30:29] reserved for MMC compatibility #define CSD_3_MMC_DEF_ECC_M 0x03 #define CSD_3_WP_GRP_EN_S 31 // [31:31] #define CSD_3_WP_GRP_EN_M 0x01 // Seconde Response INT <=> CSD[2] : bits 32 to 63 #define CSD_2_v21_WP_GRP_SIZE_S 0 // [38:32] #define CSD_2_v21_WP_GRP_SIZE_M 0x7F #define CSD_2_v21_SECT_SIZE_S 7 // [45:39] #define CSD_2_v21_SECT_SIZE_M 0x7F #define CSD_2_v21_ER_BLEN_EN_S 14 // [46:46] #define CSD_2_v21_ER_BLEN_EN_M 0x01 #define CSD_2_v22_WP_GRP_SIZE_S 0 // [36:32] #define CSD_2_v22_WP_GRP_SIZE_M 0x1F #define CSD_2_v22_ER_GRP_SIZE_S 5 // [41:37] #define CSD_2_v22_ER_GRP_SIZE_M 0x1F #define CSD_2_v22_SECT_SIZE_S 10 // [46:42] #define CSD_2_v22_SECT_SIZE_M 0x1F #define CSD_2_C_SIZE_M_S 15 // [49:47] #define CSD_2_C_SIZE_M_M 0x07 #define CSD_2_VDD_WMAX_S 18 // [52:50] #define CSD_2_VDD_WMAX_M 0x07 #define CSD_2_VDD_WMIN_S 21 // [55:53] #define CSD_2_VDD_WMIN_M 0x07 #define CSD_2_RCUR_MAX_S 24 // [58:56] #define CSD_2_RCUR_MAX_M 0x07 #define CSD_2_RCUR_MIN_S 27 // [61:59] #define CSD_2_RCUR_MIN_M 0x07 #define CSD_2_CSIZE_L_S 30 // [63:62] <=> 2 LSB of CSIZE #define CSD_2_CSIZE_L_M 0x03 // Third Response INT <=> CSD[1] : bits 64 to 95 #define CSD_1_CSIZE_H_S 0 // [73:64] <=> 10 MSB of CSIZE #define CSD_1_CSIZE_H_M 0x03FF // reserved 10 // [75:74] // reserved 0x03 #define CSD_1_DSR_I_S 12 // [76:76] #define CSD_1_DSR_I_M 0x01 #define CSD_1_RD_B_MIS_S 13 // [77:77] #define CSD_1_RD_B_MIS_M 0x01 #define CSD_1_WR_B_MIS_S 14 // [78:78] #define CSD_1_WR_B_MIS_M 0x01 #define CSD_1_RD_B_PAR_S 15 // [79:79] #define CSD_1_RD_B_PAR_M 0x01 #define CSD_1_RD_B_LEN_S 16 // [83:80] #define CSD_1_RD_B_LEN_M 0x0F #define CSD_1_CCC_S 20 // [95:84] #define CSD_1_CCC_M 0x0FFF // Fourth Response INT <=> CSD[0] : bits 96 to 127 #define CSD_0_TRANS_SPEED_S 0 // [103:96] #define CSD_0_TRANS_SPEED_M 0xFF #define CSD_0_NSAC_S 8 // [111:104] #define CSD_0_NSAC_M 0xFF #define CSD_0_TAAC_S 16 // [119:112] #define CSD_0_TAAC_M 0xFF // reserved 24 // [121:120] // reserved 0x03 #define CSD_0_MMC_SPEC_VERS_S 26 // [125:122] reserved for MMC compatibility #define CSD_0_MMC_SPEC_VERS_M 0x0F #define CSD_0_STRUCT_S 30 // [127:126] #define CSD_0_STRUCT_M 0x03 /////////////////////////////////////////////////////////////////////////////// #endif Index: head/sys/boot/efi/boot1/boot1.c =================================================================== --- head/sys/boot/efi/boot1/boot1.c (revision 298825) +++ head/sys/boot/efi/boot1/boot1.c (revision 298826) @@ -1,728 +1,728 @@ /*- * Copyright (c) 1998 Robert Nordier * All rights reserved. * Copyright (c) 2001 Robert Drehmel * All rights reserved. * Copyright (c) 2014 Nathan Whitehorn * All rights reserved. * Copyright (c) 2015 Eric McCorkle * All rights reserved. * * Redistribution and use in source and binary forms are freely * permitted provided that the above copyright notice and this * paragraph and the following disclaimer are duplicated in all * such forms. * * This software is provided "AS IS" and without any express or * implied warranties, including, without limitation, the implied * warranties of merchantability and fitness for a particular * purpose. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include "boot_module.h" #include "paths.h" static const boot_module_t *boot_modules[] = { #ifdef EFI_ZFS_BOOT &zfs_module, #endif #ifdef EFI_UFS_BOOT &ufs_module #endif }; #define NUM_BOOT_MODULES (sizeof(boot_modules) / sizeof(boot_module_t*)) /* The initial number of handles used to query EFI for partitions. */ #define NUM_HANDLES_INIT 24 void putchar(int c); EFI_STATUS efi_main(EFI_HANDLE Ximage, EFI_SYSTEM_TABLE* Xsystab); EFI_SYSTEM_TABLE *systab; EFI_BOOT_SERVICES *bs; static EFI_HANDLE *image; static EFI_GUID BlockIoProtocolGUID = BLOCK_IO_PROTOCOL; static EFI_GUID DevicePathGUID = DEVICE_PATH_PROTOCOL; static EFI_GUID LoadedImageGUID = LOADED_IMAGE_PROTOCOL; static EFI_GUID ConsoleControlGUID = EFI_CONSOLE_CONTROL_PROTOCOL_GUID; /* * Provide Malloc / Free backed by EFIs AllocatePool / FreePool which ensures * memory is correctly aligned avoiding EFI_INVALID_PARAMETER returns from * EFI methods. */ void * Malloc(size_t len, const char *file __unused, int line __unused) { void *out; if (bs->AllocatePool(EfiLoaderData, len, &out) == EFI_SUCCESS) return (out); return (NULL); } void Free(void *buf, const char *file __unused, int line __unused) { (void)bs->FreePool(buf); } /* * nodes_match returns TRUE if the imgpath isn't NULL and the nodes match, * FALSE otherwise. */ static BOOLEAN nodes_match(EFI_DEVICE_PATH *imgpath, EFI_DEVICE_PATH *devpath) { int len; if (imgpath == NULL || imgpath->Type != devpath->Type || imgpath->SubType != devpath->SubType) return (FALSE); len = DevicePathNodeLength(imgpath); if (len != DevicePathNodeLength(devpath)) return (FALSE); return (memcmp(imgpath, devpath, (size_t)len) == 0); } /* * device_paths_match returns TRUE if the imgpath isn't NULL and all nodes - * in imgpath and devpath match up to their respect occurances of a media - * node, FALSE otherwise. + * in imgpath and devpath match up to their respective occurrences of a + * media node, FALSE otherwise. */ static BOOLEAN device_paths_match(EFI_DEVICE_PATH *imgpath, EFI_DEVICE_PATH *devpath) { if (imgpath == NULL) return (FALSE); while (!IsDevicePathEnd(imgpath) && !IsDevicePathEnd(devpath)) { if (IsDevicePathType(imgpath, MEDIA_DEVICE_PATH) && IsDevicePathType(devpath, MEDIA_DEVICE_PATH)) return (TRUE); if (!nodes_match(imgpath, devpath)) return (FALSE); imgpath = NextDevicePathNode(imgpath); devpath = NextDevicePathNode(devpath); } return (FALSE); } /* * devpath_last returns the last non-path end node in devpath. */ static EFI_DEVICE_PATH * devpath_last(EFI_DEVICE_PATH *devpath) { while (!IsDevicePathEnd(NextDevicePathNode(devpath))) devpath = NextDevicePathNode(devpath); return (devpath); } /* * devpath_node_str is a basic output method for a devpath node which * only understands a subset of the available sub types. * * If we switch to UEFI 2.x then we should update it to use: * EFI_DEVICE_PATH_TO_TEXT_PROTOCOL. */ static int devpath_node_str(char *buf, size_t size, EFI_DEVICE_PATH *devpath) { switch (devpath->Type) { case MESSAGING_DEVICE_PATH: switch (devpath->SubType) { case MSG_ATAPI_DP: { ATAPI_DEVICE_PATH *atapi; atapi = (ATAPI_DEVICE_PATH *)(void *)devpath; return snprintf(buf, size, "ata(%s,%s,0x%x)", (atapi->PrimarySecondary == 1) ? "Sec" : "Pri", (atapi->SlaveMaster == 1) ? "Slave" : "Master", atapi->Lun); } case MSG_USB_DP: { USB_DEVICE_PATH *usb; usb = (USB_DEVICE_PATH *)devpath; return snprintf(buf, size, "usb(0x%02x,0x%02x)", usb->ParentPortNumber, usb->InterfaceNumber); } case MSG_SCSI_DP: { SCSI_DEVICE_PATH *scsi; scsi = (SCSI_DEVICE_PATH *)(void *)devpath; return snprintf(buf, size, "scsi(0x%02x,0x%02x)", scsi->Pun, scsi->Lun); } case MSG_SATA_DP: { SATA_DEVICE_PATH *sata; sata = (SATA_DEVICE_PATH *)(void *)devpath; return snprintf(buf, size, "sata(0x%x,0x%x,0x%x)", sata->HBAPortNumber, sata->PortMultiplierPortNumber, sata->Lun); } default: return snprintf(buf, size, "msg(0x%02x)", devpath->SubType); } break; case HARDWARE_DEVICE_PATH: switch (devpath->SubType) { case HW_PCI_DP: { PCI_DEVICE_PATH *pci; pci = (PCI_DEVICE_PATH *)devpath; return snprintf(buf, size, "pci(0x%02x,0x%02x)", pci->Device, pci->Function); } default: return snprintf(buf, size, "hw(0x%02x)", devpath->SubType); } break; case ACPI_DEVICE_PATH: { ACPI_HID_DEVICE_PATH *acpi; acpi = (ACPI_HID_DEVICE_PATH *)(void *)devpath; if ((acpi->HID & PNP_EISA_ID_MASK) == PNP_EISA_ID_CONST) { switch (EISA_ID_TO_NUM(acpi->HID)) { case 0x0a03: return snprintf(buf, size, "pciroot(0x%x)", acpi->UID); case 0x0a08: return snprintf(buf, size, "pcieroot(0x%x)", acpi->UID); case 0x0604: return snprintf(buf, size, "floppy(0x%x)", acpi->UID); case 0x0301: return snprintf(buf, size, "keyboard(0x%x)", acpi->UID); case 0x0501: return snprintf(buf, size, "serial(0x%x)", acpi->UID); case 0x0401: return snprintf(buf, size, "parallelport(0x%x)", acpi->UID); default: return snprintf(buf, size, "acpi(pnp%04x,0x%x)", EISA_ID_TO_NUM(acpi->HID), acpi->UID); } } return snprintf(buf, size, "acpi(0x%08x,0x%x)", acpi->HID, acpi->UID); } case MEDIA_DEVICE_PATH: switch (devpath->SubType) { case MEDIA_CDROM_DP: { CDROM_DEVICE_PATH *cdrom; cdrom = (CDROM_DEVICE_PATH *)(void *)devpath; return snprintf(buf, size, "cdrom(%x)", cdrom->BootEntry); } case MEDIA_HARDDRIVE_DP: { HARDDRIVE_DEVICE_PATH *hd; hd = (HARDDRIVE_DEVICE_PATH *)(void *)devpath; return snprintf(buf, size, "hd(%x)", hd->PartitionNumber); } default: return snprintf(buf, size, "media(0x%02x)", devpath->SubType); } case BBS_DEVICE_PATH: return snprintf(buf, size, "bbs(0x%02x)", devpath->SubType); case END_DEVICE_PATH_TYPE: return (0); } return snprintf(buf, size, "type(0x%02x, 0x%02x)", devpath->Type, devpath->SubType); } /* * devpath_strlcat appends a text description of devpath to buf but not more * than size - 1 characters followed by NUL-terminator. */ int devpath_strlcat(char *buf, size_t size, EFI_DEVICE_PATH *devpath) { size_t len, used; const char *sep; sep = ""; used = 0; while (!IsDevicePathEnd(devpath)) { len = snprintf(buf, size - used, "%s", sep); used += len; if (used > size) return (used); buf += len; len = devpath_node_str(buf, size - used, devpath); used += len; if (used > size) return (used); buf += len; devpath = NextDevicePathNode(devpath); sep = ":"; } return (used); } /* * devpath_str is convenience method which returns the text description of * devpath using a static buffer, so it isn't thread safe! */ char * devpath_str(EFI_DEVICE_PATH *devpath) { static char buf[256]; devpath_strlcat(buf, sizeof(buf), devpath); return buf; } /* * load_loader attempts to load the loader image data. * * It tries each module and its respective devices, identified by mod->probe, * in order until a successful load occurs at which point it returns EFI_SUCCESS * and EFI_NOT_FOUND otherwise. * * Only devices which have preferred matching the preferred parameter are tried. */ static EFI_STATUS load_loader(const boot_module_t **modp, dev_info_t **devinfop, void **bufp, size_t *bufsize, BOOLEAN preferred) { UINTN i; dev_info_t *dev; const boot_module_t *mod; for (i = 0; i < NUM_BOOT_MODULES; i++) { if (boot_modules[i] == NULL) continue; mod = boot_modules[i]; for (dev = mod->devices(); dev != NULL; dev = dev->next) { if (dev->preferred != preferred) continue; if (mod->load(PATH_LOADER_EFI, dev, bufp, bufsize) == EFI_SUCCESS) { *devinfop = dev; *modp = mod; return (EFI_SUCCESS); } } } return (EFI_NOT_FOUND); } /* * try_boot only returns if it fails to load the loader. If it succeeds * it simply boots, otherwise it returns the status of last EFI call. */ static EFI_STATUS try_boot() { size_t bufsize, loadersize, cmdsize; void *buf, *loaderbuf; char *cmd; dev_info_t *dev; const boot_module_t *mod; EFI_HANDLE loaderhandle; EFI_LOADED_IMAGE *loaded_image; EFI_STATUS status; status = load_loader(&mod, &dev, &loaderbuf, &loadersize, TRUE); if (status != EFI_SUCCESS) { status = load_loader(&mod, &dev, &loaderbuf, &loadersize, FALSE); if (status != EFI_SUCCESS) { printf("Failed to load '%s'\n", PATH_LOADER_EFI); return (status); } } /* * Read in and parse the command line from /boot.config or /boot/config, * if present. We'll pass it the next stage via a simple ASCII * string. loader.efi has a hack for ASCII strings, so we'll use that to * keep the size down here. We only try to read the alternate file if * we get EFI_NOT_FOUND because all other errors mean that the boot_module * had troubles with the filesystem. We could return early, but we'll let * loading the actual kernel sort all that out. Since these files are * optional, we don't report errors in trying to read them. */ cmd = NULL; cmdsize = 0; status = mod->load(PATH_DOTCONFIG, dev, &buf, &bufsize); if (status == EFI_NOT_FOUND) status = mod->load(PATH_CONFIG, dev, &buf, &bufsize); if (status == EFI_SUCCESS) { cmdsize = bufsize + 1; cmd = malloc(cmdsize); if (cmd == NULL) goto errout; memcpy(cmd, buf, bufsize); cmd[bufsize] = '\0'; free(buf); buf = NULL; } if ((status = bs->LoadImage(TRUE, image, devpath_last(dev->devpath), loaderbuf, loadersize, &loaderhandle)) != EFI_SUCCESS) { printf("Failed to load image provided by %s, size: %zu, (%lu)\n", mod->name, loadersize, EFI_ERROR_CODE(status)); goto errout; } if ((status = bs->HandleProtocol(loaderhandle, &LoadedImageGUID, (VOID**)&loaded_image)) != EFI_SUCCESS) { printf("Failed to query LoadedImage provided by %s (%lu)\n", mod->name, EFI_ERROR_CODE(status)); goto errout; } if (cmd != NULL) printf(" command args: %s\n", cmd); loaded_image->DeviceHandle = dev->devhandle; loaded_image->LoadOptionsSize = cmdsize; loaded_image->LoadOptions = cmd; DPRINTF("Starting '%s' in 5 seconds...", PATH_LOADER_EFI); DSTALL(1000000); DPRINTF("."); DSTALL(1000000); DPRINTF("."); DSTALL(1000000); DPRINTF("."); DSTALL(1000000); DPRINTF("."); DSTALL(1000000); DPRINTF(".\n"); if ((status = bs->StartImage(loaderhandle, NULL, NULL)) != EFI_SUCCESS) { printf("Failed to start image provided by %s (%lu)\n", mod->name, EFI_ERROR_CODE(status)); loaded_image->LoadOptionsSize = 0; loaded_image->LoadOptions = NULL; } errout: if (cmd != NULL) free(cmd); if (buf != NULL) free(buf); if (loaderbuf != NULL) free(loaderbuf); return (status); } /* * probe_handle determines if the passed handle represents a logical partition * if it does it uses each module in order to probe it and if successful it * returns EFI_SUCCESS. */ static EFI_STATUS probe_handle(EFI_HANDLE h, EFI_DEVICE_PATH *imgpath, BOOLEAN *preferred) { dev_info_t *devinfo; EFI_BLOCK_IO *blkio; EFI_DEVICE_PATH *devpath; EFI_STATUS status; UINTN i; /* Figure out if we're dealing with an actual partition. */ status = bs->HandleProtocol(h, &DevicePathGUID, (void **)&devpath); if (status == EFI_UNSUPPORTED) return (status); if (status != EFI_SUCCESS) { DPRINTF("\nFailed to query DevicePath (%lu)\n", EFI_ERROR_CODE(status)); return (status); } DPRINTF("probing: %s\n", devpath_str(devpath)); status = bs->HandleProtocol(h, &BlockIoProtocolGUID, (void **)&blkio); if (status == EFI_UNSUPPORTED) return (status); if (status != EFI_SUCCESS) { DPRINTF("\nFailed to query BlockIoProtocol (%lu)\n", EFI_ERROR_CODE(status)); return (status); } if (!blkio->Media->LogicalPartition) return (EFI_UNSUPPORTED); *preferred = device_paths_match(imgpath, devpath); /* Run through each module, see if it can load this partition */ for (i = 0; i < NUM_BOOT_MODULES; i++) { if (boot_modules[i] == NULL) continue; if ((status = bs->AllocatePool(EfiLoaderData, sizeof(*devinfo), (void **)&devinfo)) != EFI_SUCCESS) { DPRINTF("\nFailed to allocate devinfo (%lu)\n", EFI_ERROR_CODE(status)); continue; } devinfo->dev = blkio; devinfo->devpath = devpath; devinfo->devhandle = h; devinfo->devdata = NULL; devinfo->preferred = *preferred; devinfo->next = NULL; status = boot_modules[i]->probe(devinfo); if (status == EFI_SUCCESS) return (EFI_SUCCESS); (void)bs->FreePool(devinfo); } return (EFI_UNSUPPORTED); } /* * probe_handle_status calls probe_handle and outputs the returned status * of the call. */ static void probe_handle_status(EFI_HANDLE h, EFI_DEVICE_PATH *imgpath) { EFI_STATUS status; BOOLEAN preferred; status = probe_handle(h, imgpath, &preferred); DPRINTF("probe: "); switch (status) { case EFI_UNSUPPORTED: printf("."); DPRINTF(" not supported\n"); break; case EFI_SUCCESS: if (preferred) { printf("%c", '*'); DPRINTF(" supported (preferred)\n"); } else { printf("%c", '+'); DPRINTF(" supported\n"); } break; default: printf("x"); DPRINTF(" error (%lu)\n", EFI_ERROR_CODE(status)); break; } DSTALL(500000); } EFI_STATUS efi_main(EFI_HANDLE Ximage, EFI_SYSTEM_TABLE *Xsystab) { EFI_HANDLE *handles; EFI_LOADED_IMAGE *img; EFI_DEVICE_PATH *imgpath; EFI_STATUS status; EFI_CONSOLE_CONTROL_PROTOCOL *ConsoleControl = NULL; SIMPLE_TEXT_OUTPUT_INTERFACE *conout = NULL; UINTN i, max_dim, best_mode, cols, rows, hsize, nhandles; /* Basic initialization*/ systab = Xsystab; image = Ximage; bs = Xsystab->BootServices; /* Set up the console, so printf works. */ status = bs->LocateProtocol(&ConsoleControlGUID, NULL, (VOID **)&ConsoleControl); if (status == EFI_SUCCESS) (void)ConsoleControl->SetMode(ConsoleControl, EfiConsoleControlScreenText); /* * Reset the console and find the best text mode. */ conout = systab->ConOut; conout->Reset(conout, TRUE); max_dim = best_mode = 0; for (i = 0; ; i++) { status = conout->QueryMode(conout, i, &cols, &rows); if (EFI_ERROR(status)) break; if (cols * rows > max_dim) { max_dim = cols * rows; best_mode = i; } } if (max_dim > 0) conout->SetMode(conout, best_mode); conout->EnableCursor(conout, TRUE); conout->ClearScreen(conout); printf("\n>> FreeBSD EFI boot block\n"); printf(" Loader path: %s\n\n", PATH_LOADER_EFI); printf(" Initializing modules:"); for (i = 0; i < NUM_BOOT_MODULES; i++) { if (boot_modules[i] == NULL) continue; printf(" %s", boot_modules[i]->name); if (boot_modules[i]->init != NULL) boot_modules[i]->init(); } putchar('\n'); /* Get all the device handles */ hsize = (UINTN)NUM_HANDLES_INIT * sizeof(EFI_HANDLE); if ((status = bs->AllocatePool(EfiLoaderData, hsize, (void **)&handles)) != EFI_SUCCESS) panic("Failed to allocate %d handles (%lu)", NUM_HANDLES_INIT, EFI_ERROR_CODE(status)); status = bs->LocateHandle(ByProtocol, &BlockIoProtocolGUID, NULL, &hsize, handles); switch (status) { case EFI_SUCCESS: break; case EFI_BUFFER_TOO_SMALL: (void)bs->FreePool(handles); if ((status = bs->AllocatePool(EfiLoaderData, hsize, (void **)&handles) != EFI_SUCCESS)) { panic("Failed to allocate %zu handles (%lu)", hsize / sizeof(*handles), EFI_ERROR_CODE(status)); } status = bs->LocateHandle(ByProtocol, &BlockIoProtocolGUID, NULL, &hsize, handles); if (status != EFI_SUCCESS) panic("Failed to get device handles (%lu)\n", EFI_ERROR_CODE(status)); break; default: panic("Failed to get device handles (%lu)", EFI_ERROR_CODE(status)); } /* Scan all partitions, probing with all modules. */ nhandles = hsize / sizeof(*handles); printf(" Probing %zu block devices...", nhandles); DPRINTF("\n"); /* Determine the devpath of our image so we can prefer it. */ status = bs->HandleProtocol(image, &LoadedImageGUID, (VOID**)&img); imgpath = NULL; if (status == EFI_SUCCESS) { status = bs->HandleProtocol(img->DeviceHandle, &DevicePathGUID, (void **)&imgpath); if (status != EFI_SUCCESS) DPRINTF("Failed to get image DevicePath (%lu)\n", EFI_ERROR_CODE(status)); DPRINTF("boot1 imagepath: %s\n", devpath_str(imgpath)); } for (i = 0; i < nhandles; i++) probe_handle_status(handles[i], imgpath); printf(" done\n"); /* Status summary. */ for (i = 0; i < NUM_BOOT_MODULES; i++) { if (boot_modules[i] != NULL) { printf(" "); boot_modules[i]->status(); } } try_boot(); /* If we get here, we're out of luck... */ panic("No bootable partitions found!"); } /* * add_device adds a device to the passed devinfo list. */ void add_device(dev_info_t **devinfop, dev_info_t *devinfo) { dev_info_t *dev; if (*devinfop == NULL) { *devinfop = devinfo; return; } for (dev = *devinfop; dev->next != NULL; dev = dev->next) ; dev->next = devinfo; } void panic(const char *fmt, ...) { va_list ap; printf("panic: "); va_start(ap, fmt); vprintf(fmt, ap); va_end(ap); printf("\n"); while (1) {} } void putchar(int c) { CHAR16 buf[2]; if (c == '\n') { buf[0] = '\r'; buf[1] = 0; systab->ConOut->OutputString(systab->ConOut, buf); } buf[0] = c; buf[1] = 0; systab->ConOut->OutputString(systab->ConOut, buf); } Index: head/sys/boot/efi/include/amd64/efibind.h =================================================================== --- head/sys/boot/efi/include/amd64/efibind.h (revision 298825) +++ head/sys/boot/efi/include/amd64/efibind.h (revision 298826) @@ -1,271 +1,271 @@ /* $FreeBSD$ */ /*++ Copyright (c) 1999 - 2003 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. Module Name: efefind.h Abstract: EFI to compile bindings Revision History --*/ #pragma pack() #ifdef __FreeBSD__ #include #else // // Basic int types of various widths // #if (__STDC_VERSION__ < 199901L ) // No ANSI C 1999/2000 stdint.h integer width declarations #ifdef _MSC_EXTENSIONS // Use Microsoft C compiler integer width declarations typedef unsigned __int64 uint64_t; typedef __int64 int64_t; typedef unsigned __int32 uint32_t; typedef __int32 int32_t; typedef unsigned short uint16_t; typedef short int16_t; typedef unsigned char uint8_t; typedef char int8_t; #else #ifdef UNIX_LP64 // Use LP64 programming model from C_FLAGS for integer width declarations typedef unsigned long uint64_t; typedef long int64_t; typedef unsigned int uint32_t; typedef int int32_t; typedef unsigned short uint16_t; typedef short int16_t; typedef unsigned char uint8_t; typedef char int8_t; #else // Assume P64 programming model from C_FLAGS for integer width declarations typedef unsigned long long uint64_t; typedef long long int64_t; typedef unsigned int uint32_t; typedef int int32_t; typedef unsigned short uint16_t; typedef short int16_t; typedef unsigned char uint8_t; typedef char int8_t; #endif #endif #endif #endif /* __FreeBSD__ */ // // Basic EFI types of various widths // #ifndef ACPI_THREAD_ID /* ACPI's definitions are fine */ #define ACPI_USE_SYSTEM_INTTYPES 1 /* Tell ACPI we've defined types */ typedef uint64_t UINT64; typedef int64_t INT64; #ifndef _BASETSD_H_ typedef uint32_t UINT32; typedef int32_t INT32; #endif typedef uint16_t UINT16; typedef int16_t INT16; typedef uint8_t UINT8; typedef int8_t INT8; #endif #undef VOID #define VOID void typedef int64_t INTN; typedef uint64_t UINTN; #ifdef EFI_NT_EMULATOR #define POST_CODE(_Data) #else #ifdef EFI_DEBUG #define POST_CODE(_Data) __asm mov eax,(_Data) __asm out 0x80,al #else #define POST_CODE(_Data) #endif #endif #define EFIERR(a) (0x8000000000000000 | a) #define EFI_ERROR_MASK 0x8000000000000000 #define EFIERR_OEM(a) (0xc000000000000000 | a) #define BAD_POINTER 0xFBFBFBFBFBFBFBFB #define MAX_ADDRESS 0xFFFFFFFFFFFFFFFF #define BREAKPOINT() __asm { int 3 } // // Pointers must be aligned to these address to function // #define MIN_ALIGNMENT_SIZE 4 #define ALIGN_VARIABLE(Value ,Adjustment) \ (UINTN)Adjustment = 0; \ if((UINTN)Value % MIN_ALIGNMENT_SIZE) \ (UINTN)Adjustment = MIN_ALIGNMENT_SIZE - ((UINTN)Value % MIN_ALIGNMENT_SIZE); \ Value = (UINTN)Value + (UINTN)Adjustment // // Define macros to build data structure signatures from characters. // #define EFI_SIGNATURE_16(A,B) ((A) | (B<<8)) #define EFI_SIGNATURE_32(A,B,C,D) (EFI_SIGNATURE_16(A,B) | (EFI_SIGNATURE_16(C,D) << 16)) #define EFI_SIGNATURE_64(A,B,C,D,E,F,G,H) (EFI_SIGNATURE_32(A,B,C,D) | ((UINT64)(EFI_SIGNATURE_32(E,F,G,H)) << 32)) // // EFIAPI - prototype calling convention for EFI function pointers // BOOTSERVICE - prototype for implementation of a boot service interface // RUNTIMESERVICE - prototype for implementation of a runtime service interface // RUNTIMEFUNCTION - prototype for implementation of a runtime function that is not a service // RUNTIME_CODE - pragma macro for declaring runtime code // #ifdef __amd64__ #define EFIAPI __attribute__((ms_abi)) #endif #ifndef EFIAPI // Forces EFI calling conventions reguardless of compiler options #ifdef _MSC_EXTENSIONS #define EFIAPI __cdecl // Force C calling convention for Microsoft C compiler #else #define EFIAPI // Substitute expresion to force C calling convention #endif #endif #define BOOTSERVICE //#define RUNTIMESERVICE(proto,a) alloc_text("rtcode",a); proto a //#define RUNTIMEFUNCTION(proto,a) alloc_text("rtcode",a); proto a #define RUNTIMESERVICE #define RUNTIMEFUNCTION #define RUNTIME_CODE(a) alloc_text("rtcode", a) #define BEGIN_RUNTIME_DATA() data_seg("rtdata") #define END_RUNTIME_DATA() data_seg("") #define VOLATILE volatile #define MEMORY_FENCE() #ifdef EFI_NO_INTERFACE_DECL #define EFI_FORWARD_DECLARATION(x) #define EFI_INTERFACE_DECL(x) #else #define EFI_FORWARD_DECLARATION(x) typedef struct _##x x #define EFI_INTERFACE_DECL(x) typedef struct x #endif #ifdef EFI_NT_EMULATOR // // To help ensure proper coding of integrated drivers, they are // compiled as DLLs. In NT they require a dll init entry pointer. // The macro puts a stub entry point into the DLL so it will load. // #define EFI_DRIVER_ENTRY_POINT(InitFunction) \ EFI_STATUS \ InitFunction ( \ EFI_HANDLE ImageHandle, \ EFI_SYSTEM_TABLE *SystemTable \ ); \ \ UINTN \ __stdcall \ _DllMainCRTStartup ( \ UINTN Inst, \ UINTN reason_for_call, \ VOID *rserved \ ) \ { \ return 1; \ } \ \ int \ __declspec( dllexport ) \ __cdecl \ InitializeDriver ( \ void *ImageHandle, \ void *SystemTable \ ) \ { \ return InitFunction(ImageHandle, SystemTable); \ } #define LOAD_INTERNAL_DRIVER(_if, type, name, entry) \ (_if)->LoadInternal(type, name, NULL) #else // EFI_NT_EMULATOR // -// When build similiar to FW, then link everything together as +// When building similar to FW, link everything together as // one big module. // #define EFI_DRIVER_ENTRY_POINT(InitFunction) #define LOAD_INTERNAL_DRIVER(_if, type, name, entry) \ (_if)->LoadInternal(type, name, entry) #endif // EFI_FW_NT #ifdef __FreeBSD__ #define INTERFACE_DECL(x) struct x #else // // Some compilers don't support the forward reference construct: // typedef struct XXXXX // // The following macro provide a workaround for such cases. // #ifdef NO_INTERFACE_DECL #define INTERFACE_DECL(x) #else #define INTERFACE_DECL(x) typedef struct x #endif #endif /* __FreeBSD__ */ #ifdef _MSC_EXTENSIONS #pragma warning ( disable : 4731 ) // Suppress warnings about modification of EBP #endif Index: head/sys/boot/efi/include/arm/efibind.h =================================================================== --- head/sys/boot/efi/include/arm/efibind.h (revision 298825) +++ head/sys/boot/efi/include/arm/efibind.h (revision 298826) @@ -1,165 +1,165 @@ /* $FreeBSD$ */ /*++ Copyright (c) 2004 - 2012, Intel Corporation. All rights reserved. This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. Module Name: EfiBind.h Abstract: Processor or Compiler specific defines and types for IA-32. We are using the ANSI C 2000 _t type definitions for basic types. This it technically a violation of the coding standard, but they are used to make EfiTypes.h portable. Code other than EfiTypes.h should never use any ANSI C 2000 _t integer types. --*/ #ifndef _EFI_BIND_H_ #define _EFI_BIND_H_ #define EFI_DRIVER_ENTRY_POINT(InitFunction) #define EFI_APPLICATION_ENTRY_POINT EFI_DRIVER_ENTRY_POINT // -// Make sure we are useing the correct packing rules per EFI specification +// Make sure we are using the correct packing rules per EFI specification // #ifndef __GNUC__ #pragma pack() #endif #ifdef __FreeBSD__ #include #else // // Assume standard IA-32 alignment. // BugBug: Need to check portability of long long // typedef unsigned long long uint64_t; typedef long long int64_t; typedef unsigned int uint32_t; typedef int int32_t; typedef unsigned short uint16_t; typedef short int16_t; typedef unsigned char uint8_t; typedef signed char int8_t; #endif typedef uint64_t UINT64; typedef int64_t INT64; typedef uint32_t UINT32; typedef int32_t INT32; typedef uint16_t UINT16; typedef int16_t INT16; typedef uint8_t UINT8; typedef int8_t INT8; #undef VOID #define VOID void // // Native integer size in stdint.h // typedef uint32_t UINTN; typedef int32_t INTN; #define EFIERR(a) (0x80000000 | a) #define EFI_ERROR_MASK 0x80000000 #define EFIERR_OEM(a) (0xc0000000 | a) // // Processor specific defines // #define EFI_MAX_BIT 0x80000000 #define MAX_2_BITS 0xC0000000 // // Maximum legal IA-32 address // #define EFI_MAX_ADDRESS 0xFFFFFFFF // // Bad pointer value to use in check builds. // if you see this value you are using uninitialized or free'ed data // #define EFI_BAD_POINTER 0xAFAFAFAF #define EFI_BAD_POINTER_AS_BYTE 0xAF #define EFI_DEADLOOP() { volatile UINTN __iii; __iii = 1; while (__iii); } // // Inject a break point in the code to assist debugging for NT Emulation Environment // For real hardware, just put in a halt loop. Don't do a while(1) because the // compiler will optimize away the rest of the function following, so that you run out in // the weeds if you skip over it with a debugger. // #define EFI_BREAKPOINT EFI_DEADLOOP() // // Memory Fence forces serialization, and is needed to support out of order // memory transactions. The Memory Fence is mainly used to make sure IO // transactions complete in a deterministic sequence, and to syncronize locks // an other MP code. Currently no memory fencing is required. // #define MEMORY_FENCE() // // Some compilers don't support the forward reference construct: // typedef struct XXXXX. The forward reference is required for // ANSI compatibility. // // The following macro provide a workaround for such cases. // #ifdef EFI_NO_INTERFACE_DECL #define EFI_FORWARD_DECLARATION(x) #else #define EFI_FORWARD_DECLARATION(x) typedef struct _##x x #endif // // Some C compilers optimize the calling conventions to increase performance. // EFIAPI is used to make all public APIs follow the standard C calling // convention. // #define EFIAPI // // For symbol name in GNU assembly code, an extra "_" is necessary // #if defined(__GNUC__) /// /// Private worker functions for ASM_PFX() /// #define _CONCATENATE(a, b) __CONCATENATE(a, b) #define __CONCATENATE(a, b) a ## b /// /// The __USER_LABEL_PREFIX__ macro predefined by GNUC represents the prefix /// on symbols in assembly language. /// #define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name) #endif #define INTERFACE_DECL(x) struct x #endif Index: head/sys/boot/efi/include/arm64/efibind.h =================================================================== --- head/sys/boot/efi/include/arm64/efibind.h (revision 298825) +++ head/sys/boot/efi/include/arm64/efibind.h (revision 298826) @@ -1,217 +1,217 @@ /* $FreeBSD$ */ /*++ Copyright (c) 1999 - 2003 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. Module Name: efefind.h Abstract: EFI to compile bindings Revision History --*/ #pragma pack() #ifdef __FreeBSD__ #include #else // // Basic int types of various widths // #if (__STDC_VERSION__ < 199901L ) // No ANSI C 1999/2000 stdint.h integer width declarations #ifdef _MSC_EXTENSIONS // Use Microsoft C compiler integer width declarations typedef unsigned __int64 uint64_t; typedef __int64 int64_t; typedef unsigned __int32 uint32_t; typedef __int32 int32_t; typedef unsigned __int16 uint16_t; typedef __int16 int16_t; typedef unsigned __int8 uint8_t; typedef __int8 int8_t; #else #ifdef UNIX_LP64 // Use LP64 programming model from C_FLAGS for integer width declarations typedef unsigned long uint64_t; typedef long int64_t; typedef unsigned int uint32_t; typedef int int32_t; typedef unsigned short uint16_t; typedef short int16_t; typedef unsigned char uint8_t; typedef char int8_t; #else // Assume P64 programming model from C_FLAGS for integer width declarations typedef unsigned long long uint64_t; typedef long long int64_t; typedef unsigned int uint32_t; typedef int int32_t; typedef unsigned short uint16_t; typedef short int16_t; typedef unsigned char uint8_t; typedef char int8_t; #endif #endif #endif #endif /* __FreeBSD__ */ // // Basic EFI types of various widths // typedef uint64_t UINT64; typedef int64_t INT64; typedef uint32_t UINT32; typedef int32_t INT32; typedef uint16_t UINT16; typedef int16_t INT16; typedef uint8_t UINT8; typedef int8_t INT8; #undef VOID #define VOID void typedef int64_t INTN; typedef uint64_t UINTN; //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ // BugBug: Code to debug // #define BIT63 0x8000000000000000 #define PLATFORM_IOBASE_ADDRESS (0xffffc000000 | BIT63) #define PORT_TO_MEMD(_Port) (PLATFORM_IOBASE_ADDRESS | ( ( ( (_Port) & 0xfffc) << 10 ) | ( (_Port) & 0x0fff) ) ) // // Macro's with casts make this much easier to use and read. // #define PORT_TO_MEM8D(_Port) (*(UINT8 *)(PORT_TO_MEMD(_Port))) #define POST_CODE(_Data) (PORT_TO_MEM8D(0x80) = (_Data)) // // BugBug: End Debug Code!!! //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ #define EFIERR(a) (0x8000000000000000 | a) #define EFI_ERROR_MASK 0x8000000000000000 #define EFIERR_OEM(a) (0xc000000000000000 | a) #define BAD_POINTER 0xFBFBFBFBFBFBFBFB #define MAX_ADDRESS 0xFFFFFFFFFFFFFFFF #define BREAKPOINT() __break(0) // // Pointers must be aligned to these address to function // you will get an alignment fault if this value is less than 8 // #define MIN_ALIGNMENT_SIZE 8 #define ALIGN_VARIABLE(Value , Adjustment) \ (UINTN) Adjustment = 0; \ if((UINTN)Value % MIN_ALIGNMENT_SIZE) \ (UINTN)Adjustment = MIN_ALIGNMENT_SIZE - ((UINTN)Value % MIN_ALIGNMENT_SIZE); \ Value = (UINTN)Value + (UINTN)Adjustment // // Define macros to create data structure signatures. // #define EFI_SIGNATURE_16(A,B) ((A) | (B<<8)) #define EFI_SIGNATURE_32(A,B,C,D) (EFI_SIGNATURE_16(A,B) | (EFI_SIGNATURE_16(C,D) << 16)) #define EFI_SIGNATURE_64(A,B,C,D,E,F,G,H) (EFI_SIGNATURE_32(A,B,C,D) | ((UINT64)(EFI_SIGNATURE_32(E,F,G,H)) << 32)) // // EFIAPI - prototype calling convention for EFI function pointers // BOOTSERVICE - prototype for implementation of a boot service interface // RUNTIMESERVICE - prototype for implementation of a runtime service interface // RUNTIMEFUNCTION - prototype for implementation of a runtime function that is not a service // RUNTIME_CODE - pragma macro for declaring runtime code // #ifndef EFIAPI // Forces EFI calling conventions reguardless of compiler options #ifdef _MSC_EXTENSIONS #define EFIAPI __cdecl // Force C calling convention for Microsoft C compiler #else #define EFIAPI // Substitute expresion to force C calling convention #endif #endif #define BOOTSERVICE #define RUNTIMESERVICE #define RUNTIMEFUNCTION #define RUNTIME_CODE(a) alloc_text("rtcode", a) #define BEGIN_RUNTIME_DATA() data_seg("rtdata") #define END_RUNTIME_DATA() data_seg() #define VOLATILE volatile // -// BugBug: Need to find out if this is portable accross compliers. +// BugBug: Need to find out if this is portable across compilers. // void __mfa (void); #define MEMORY_FENCE() __mfa() #ifdef EFI_NO_INTERFACE_DECL #define EFI_FORWARD_DECLARATION(x) #define EFI_INTERFACE_DECL(x) #else #define EFI_FORWARD_DECLARATION(x) typedef struct _##x x #define EFI_INTERFACE_DECL(x) typedef struct x #endif // -// When build similiar to FW, then link everything together as +// When build similar to FW, then link everything together as // one big module. // #define EFI_DRIVER_ENTRY_POINT(InitFunction) #define LOAD_INTERNAL_DRIVER(_if, type, name, entry) \ (_if)->LoadInternal(type, name, entry) // entry(NULL, ST) #ifdef __FreeBSD__ #define INTERFACE_DECL(x) struct x #else // // Some compilers don't support the forward reference construct: // typedef struct XXXXX // // The following macro provide a workaround for such cases. // #ifdef NO_INTERFACE_DECL #define INTERFACE_DECL(x) #else #define INTERFACE_DECL(x) typedef struct x #endif #endif Index: head/sys/boot/efi/include/efiuga.h =================================================================== --- head/sys/boot/efi/include/efiuga.h (revision 298825) +++ head/sys/boot/efi/include/efiuga.h (revision 298826) @@ -1,168 +1,168 @@ /* $FreeBSD$ */ /** @file UGA Draw protocol from the EFI 1.1 specification. Abstraction of a very simple graphics device. Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at: http://opensource.org/licenses/bsd-license.php THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. File name: UgaDraw.h **/ #ifndef __UGA_DRAW_H__ #define __UGA_DRAW_H__ #define EFI_UGA_DRAW_PROTOCOL_GUID \ { 0x982c298b, 0xf4fa, 0x41cb, {0xb8, 0x38, 0x77, 0xaa, 0x68, 0x8f, 0xb8, 0x39} } typedef struct _EFI_UGA_DRAW_PROTOCOL EFI_UGA_DRAW_PROTOCOL; /** Return the current video mode information. @param This Protocol instance pointer. @param HorizontalResolution Current video horizontal resolution in pixels @param VerticalResolution Current video vertical resolution in pixels @param ColorDepth Current video color depth in bits per pixel @param RefreshRate Current video refresh rate in Hz. @retval EFI_SUCCESS Mode information returned. @retval EFI_NOT_STARTED Video display is not initialized. Call SetMode () @retval EFI_INVALID_PARAMETER One of the input args was NULL. **/ typedef EFI_STATUS (EFIAPI *EFI_UGA_DRAW_PROTOCOL_GET_MODE) ( IN EFI_UGA_DRAW_PROTOCOL *This, OUT UINT32 *HorizontalResolution, OUT UINT32 *VerticalResolution, OUT UINT32 *ColorDepth, OUT UINT32 *RefreshRate ) ; /** Return the current video mode information. @param This Protocol instance pointer. @param HorizontalResolution Current video horizontal resolution in pixels @param VerticalResolution Current video vertical resolution in pixels @param ColorDepth Current video color depth in bits per pixel @param RefreshRate Current video refresh rate in Hz. @retval EFI_SUCCESS Mode information returned. @retval EFI_NOT_STARTED Video display is not initialized. Call SetMode () **/ typedef EFI_STATUS (EFIAPI *EFI_UGA_DRAW_PROTOCOL_SET_MODE) ( IN EFI_UGA_DRAW_PROTOCOL *This, IN UINT32 HorizontalResolution, IN UINT32 VerticalResolution, IN UINT32 ColorDepth, IN UINT32 RefreshRate ) ; typedef struct { UINT8 Blue; UINT8 Green; UINT8 Red; UINT8 Reserved; } EFI_UGA_PIXEL; typedef union { EFI_UGA_PIXEL Pixel; UINT32 Raw; } EFI_UGA_PIXEL_UNION; typedef enum { EfiUgaVideoFill, EfiUgaVideoToBltBuffer, EfiUgaBltBufferToVideo, EfiUgaVideoToVideo, EfiUgaBltMax } EFI_UGA_BLT_OPERATION; /** Type specifying a pointer to a function to perform an UGA Blt operation. The following table defines actions for BltOperations: EfiUgaVideoFill - Write data from the BltBuffer pixel (SourceX, SourceY) directly to every pixel of the video display rectangle (DestinationX, DestinationY) (DestinationX + Width, DestinationY + Height). Only one pixel will be used from the BltBuffer. Delta is NOT used. EfiUgaVideoToBltBuffer - Read data from the video display rectangle (SourceX, SourceY) (SourceX + Width, SourceY + Height) and place it in the BltBuffer rectangle (DestinationX, DestinationY ) (DestinationX + Width, DestinationY + Height). If DestinationX or DestinationY is not zero then Delta must be set to the length in bytes of a row in the BltBuffer. EfiUgaBltBufferToVideo - Write data from the BltBuffer rectangle (SourceX, SourceY) (SourceX + Width, SourceY + Height) directly to the video display rectangle (DestinationX, DestinationY) (DestinationX + Width, DestinationY + Height). If SourceX or SourceY is not zero then Delta must be set to the length in bytes of a row in the BltBuffer. EfiUgaVideoToVideo - Copy from the video display rectangle (SourceX, SourceY) (SourceX + Width, SourceY + Height) .to the video display rectangle (DestinationX, DestinationY) (DestinationX + Width, DestinationY + Height). The BltBuffer and Delta are not used in this mode. @param[in] This - Protocol instance pointer. @param[in] BltBuffer - Buffer containing data to blit into video buffer. This buffer has a size of Width*Height*sizeof(EFI_UGA_PIXEL) @param[in] BltOperation - Operation to perform on BlitBuffer and video memory @param[in] SourceX - X coordinate of source for the BltBuffer. @param[in] SourceY - Y coordinate of source for the BltBuffer. @param[in] DestinationX - X coordinate of destination for the BltBuffer. @param[in] DestinationY - Y coordinate of destination for the BltBuffer. @param[in] Width - Width of rectangle in BltBuffer in pixels. @param[in] Height - Hight of rectangle in BltBuffer in pixels. @param[in] Delta - OPTIONAL @retval EFI_SUCCESS - The Blt operation completed. @retval EFI_INVALID_PARAMETER - BltOperation is not valid. - @retval EFI_DEVICE_ERROR - A hardware error occured writting to the video buffer. + @retval EFI_DEVICE_ERROR - A hardware error occurred writting to the video buffer. --*/ typedef EFI_STATUS (EFIAPI *EFI_UGA_DRAW_PROTOCOL_BLT) ( IN EFI_UGA_DRAW_PROTOCOL * This, IN EFI_UGA_PIXEL * BltBuffer, OPTIONAL IN EFI_UGA_BLT_OPERATION BltOperation, IN UINTN SourceX, IN UINTN SourceY, IN UINTN DestinationX, IN UINTN DestinationY, IN UINTN Width, IN UINTN Height, IN UINTN Delta OPTIONAL ); struct _EFI_UGA_DRAW_PROTOCOL { EFI_UGA_DRAW_PROTOCOL_GET_MODE GetMode; EFI_UGA_DRAW_PROTOCOL_SET_MODE SetMode; EFI_UGA_DRAW_PROTOCOL_BLT Blt; }; extern EFI_GUID gEfiUgaDrawProtocolGuid; #endif Index: head/sys/boot/efi/include/i386/efibind.h =================================================================== --- head/sys/boot/efi/include/i386/efibind.h (revision 298825) +++ head/sys/boot/efi/include/i386/efibind.h (revision 298826) @@ -1,267 +1,267 @@ /* $FreeBSD$ */ /*++ Copyright (c) 1999 - 2003 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. Module Name: efefind.h Abstract: EFI to compile bindings Revision History --*/ #pragma pack() #ifdef __FreeBSD__ #include #else // // Basic int types of various widths // #if (__STDC_VERSION__ < 199901L ) // No ANSI C 1999/2000 stdint.h integer width declarations #ifdef _MSC_EXTENSIONS // Use Microsoft C compiler integer width declarations typedef unsigned __int64 uint64_t; typedef __int64 int64_t; typedef unsigned __int32 uint32_t; typedef __int32 int32_t; typedef unsigned short uint16_t; typedef short int16_t; typedef unsigned char uint8_t; typedef char int8_t; #else #ifdef UNIX_LP64 // Use LP64 programming model from C_FLAGS for integer width declarations typedef unsigned long uint64_t; typedef long int64_t; typedef unsigned int uint32_t; typedef int int32_t; typedef unsigned short uint16_t; typedef short int16_t; typedef unsigned char uint8_t; typedef char int8_t; #else // Assume P64 programming model from C_FLAGS for integer width declarations typedef unsigned long long uint64_t; typedef long long int64_t; typedef unsigned int uint32_t; typedef int int32_t; typedef unsigned short uint16_t; typedef short int16_t; typedef unsigned char uint8_t; typedef char int8_t; #endif #endif #endif #endif /* __FreeBSD__ */ // // Basic EFI types of various widths // #ifndef ACPI_THREAD_ID /* ACPI's definitions are fine, use those */ #define ACPI_USE_SYSTEM_INTTYPES 1 /* Tell ACPI we've defined types */ typedef uint64_t UINT64; typedef int64_t INT64; #ifndef _BASETSD_H_ typedef uint32_t UINT32; typedef int32_t INT32; #endif typedef uint16_t UINT16; typedef int16_t INT16; typedef uint8_t UINT8; typedef int8_t INT8; #endif #undef VOID #define VOID void typedef int32_t INTN; typedef uint32_t UINTN; #ifdef EFI_NT_EMULATOR #define POST_CODE(_Data) #else #ifdef EFI_DEBUG #define POST_CODE(_Data) __asm mov eax,(_Data) __asm out 0x80,al #else #define POST_CODE(_Data) #endif #endif #define EFIERR(a) (0x80000000 | a) #define EFI_ERROR_MASK 0x80000000 #define EFIERR_OEM(a) (0xc0000000 | a) #define BAD_POINTER 0xFBFBFBFB #define MAX_ADDRESS 0xFFFFFFFF #define BREAKPOINT() __asm { int 3 } // // Pointers must be aligned to these address to function // #define MIN_ALIGNMENT_SIZE 4 #define ALIGN_VARIABLE(Value ,Adjustment) \ (UINTN)Adjustment = 0; \ if((UINTN)Value % MIN_ALIGNMENT_SIZE) \ (UINTN)Adjustment = MIN_ALIGNMENT_SIZE - ((UINTN)Value % MIN_ALIGNMENT_SIZE); \ Value = (UINTN)Value + (UINTN)Adjustment // // Define macros to build data structure signatures from characters. // #define EFI_SIGNATURE_16(A,B) ((A) | (B<<8)) #define EFI_SIGNATURE_32(A,B,C,D) (EFI_SIGNATURE_16(A,B) | (EFI_SIGNATURE_16(C,D) << 16)) #define EFI_SIGNATURE_64(A,B,C,D,E,F,G,H) (EFI_SIGNATURE_32(A,B,C,D) | ((UINT64)(EFI_SIGNATURE_32(E,F,G,H)) << 32)) // // EFIAPI - prototype calling convention for EFI function pointers // BOOTSERVICE - prototype for implementation of a boot service interface // RUNTIMESERVICE - prototype for implementation of a runtime service interface // RUNTIMEFUNCTION - prototype for implementation of a runtime function that is not a service // RUNTIME_CODE - pragma macro for declaring runtime code // #ifndef EFIAPI // Forces EFI calling conventions reguardless of compiler options #ifdef _MSC_EXTENSIONS #define EFIAPI __cdecl // Force C calling convention for Microsoft C compiler #else #define EFIAPI // Substitute expresion to force C calling convention #endif #endif #define BOOTSERVICE //#define RUNTIMESERVICE(proto,a) alloc_text("rtcode",a); proto a //#define RUNTIMEFUNCTION(proto,a) alloc_text("rtcode",a); proto a #define RUNTIMESERVICE #define RUNTIMEFUNCTION #define RUNTIME_CODE(a) alloc_text("rtcode", a) #define BEGIN_RUNTIME_DATA() data_seg("rtdata") #define END_RUNTIME_DATA() data_seg() #define VOLATILE volatile #define MEMORY_FENCE() #ifdef EFI_NO_INTERFACE_DECL #define EFI_FORWARD_DECLARATION(x) #define EFI_INTERFACE_DECL(x) #else #define EFI_FORWARD_DECLARATION(x) typedef struct _##x x #define EFI_INTERFACE_DECL(x) typedef struct x #endif #ifdef EFI_NT_EMULATOR // // To help ensure proper coding of integrated drivers, they are // compiled as DLLs. In NT they require a dll init entry pointer. // The macro puts a stub entry point into the DLL so it will load. // #define EFI_DRIVER_ENTRY_POINT(InitFunction) \ EFI_STATUS \ InitFunction ( \ EFI_HANDLE ImageHandle, \ EFI_SYSTEM_TABLE *SystemTable \ ); \ \ UINTN \ __stdcall \ _DllMainCRTStartup ( \ UINTN Inst, \ UINTN reason_for_call, \ VOID *rserved \ ) \ { \ return 1; \ } \ \ int \ __declspec( dllexport ) \ __cdecl \ InitializeDriver ( \ void *ImageHandle, \ void *SystemTable \ ) \ { \ return InitFunction(ImageHandle, SystemTable); \ } #define LOAD_INTERNAL_DRIVER(_if, type, name, entry) \ (_if)->LoadInternal(type, name, NULL) #else // EFI_NT_EMULATOR // -// When build similiar to FW, then link everything together as +// When build similar to FW, then link everything together as // one big module. // #define EFI_DRIVER_ENTRY_POINT(InitFunction) #define LOAD_INTERNAL_DRIVER(_if, type, name, entry) \ (_if)->LoadInternal(type, name, entry) #endif // EFI_FW_NT #ifdef __FreeBSD__ #define INTERFACE_DECL(x) struct x #else // // Some compilers don't support the forward reference construct: // typedef struct XXXXX // // The following macro provide a workaround for such cases. // #ifdef NO_INTERFACE_DECL #define INTERFACE_DECL(x) #else #define INTERFACE_DECL(x) typedef struct x #endif #endif /* __FreeBSD__ */ #ifdef _MSC_EXTENSIONS #pragma warning ( disable : 4731 ) // Suppress warnings about modification of EBP #endif Index: head/sys/boot/efi/loader/main.c =================================================================== --- head/sys/boot/efi/loader/main.c (revision 298825) +++ head/sys/boot/efi/loader/main.c (revision 298826) @@ -1,758 +1,758 @@ /*- * Copyright (c) 2008-2010 Rui Paulo * Copyright (c) 2006 Marcel Moolenaar * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #ifdef EFI_ZFS_BOOT #include #endif #include "loader_efi.h" extern char bootprog_name[]; extern char bootprog_rev[]; extern char bootprog_date[]; extern char bootprog_maker[]; struct arch_switch archsw; /* MI/MD interface boundary */ EFI_GUID acpi = ACPI_TABLE_GUID; EFI_GUID acpi20 = ACPI_20_TABLE_GUID; EFI_GUID devid = DEVICE_PATH_PROTOCOL; EFI_GUID imgid = LOADED_IMAGE_PROTOCOL; EFI_GUID mps = MPS_TABLE_GUID; EFI_GUID netid = EFI_SIMPLE_NETWORK_PROTOCOL; EFI_GUID smbios = SMBIOS_TABLE_GUID; EFI_GUID dxe = DXE_SERVICES_TABLE_GUID; EFI_GUID hoblist = HOB_LIST_TABLE_GUID; EFI_GUID memtype = MEMORY_TYPE_INFORMATION_TABLE_GUID; EFI_GUID debugimg = DEBUG_IMAGE_INFO_TABLE_GUID; EFI_GUID fdtdtb = FDT_TABLE_GUID; EFI_GUID inputid = SIMPLE_TEXT_INPUT_PROTOCOL; #ifdef EFI_ZFS_BOOT static void efi_zfs_probe(void); #endif /* * Need this because EFI uses UTF-16 unicode string constants, but we - * use UTF-8. We can't use printf due to the possiblity of \0 and we + * use UTF-8. We can't use printf due to the possibility of \0 and we * don't support support wide characters either. */ static void print_str16(const CHAR16 *str) { int i; for (i = 0; str[i]; i++) printf("%c", (char)str[i]); } static void cp16to8(const CHAR16 *src, char *dst, size_t len) { size_t i; for (i = 0; i < len && src[i]; i++) dst[i] = (char)src[i]; } static int has_keyboard(void) { EFI_STATUS status; EFI_DEVICE_PATH *path; EFI_HANDLE *hin, *hin_end, *walker; UINTN sz; int retval = 0; /* * Find all the handles that support the SIMPLE_TEXT_INPUT_PROTOCOL and * do the typical dance to get the right sized buffer. */ sz = 0; hin = NULL; status = BS->LocateHandle(ByProtocol, &inputid, 0, &sz, 0); if (status == EFI_BUFFER_TOO_SMALL) { hin = (EFI_HANDLE *)malloc(sz); status = BS->LocateHandle(ByProtocol, &inputid, 0, &sz, hin); if (EFI_ERROR(status)) free(hin); } if (EFI_ERROR(status)) return retval; /* * Look at each of the handles. If it supports the device path protocol, * use it to get the device path for this handle. Then see if that * device path matches either the USB device path for keyboards or the * legacy device path for keyboards. */ hin_end = &hin[sz / sizeof(*hin)]; for (walker = hin; walker < hin_end; walker++) { status = BS->HandleProtocol(*walker, &devid, (VOID **)&path); if (EFI_ERROR(status)) continue; while (!IsDevicePathEnd(path)) { /* * Check for the ACPI keyboard node. All PNP3xx nodes * are keyboards of different flavors. Note: It is * unclear of there's always a keyboard node when * there's a keyboard controller, or if there's only one * when a keyboard is detected at boot. */ if (DevicePathType(path) == ACPI_DEVICE_PATH && (DevicePathSubType(path) == ACPI_DP || DevicePathSubType(path) == ACPI_EXTENDED_DP)) { ACPI_HID_DEVICE_PATH *acpi; acpi = (ACPI_HID_DEVICE_PATH *)(void *)path; if ((EISA_ID_TO_NUM(acpi->HID) & 0xff00) == 0x300 && (acpi->HID & 0xffff) == PNP_EISA_ID_CONST) { retval = 1; goto out; } /* * Check for USB keyboard node, if present. Unlike a * PS/2 keyboard, these definitely only appear when * connected to the system. */ } else if (DevicePathType(path) == MESSAGING_DEVICE_PATH && DevicePathSubType(path) == MSG_USB_CLASS_DP) { USB_CLASS_DEVICE_PATH *usb; usb = (USB_CLASS_DEVICE_PATH *)(void *)path; if (usb->DeviceClass == 3 && /* HID */ usb->DeviceSubClass == 1 && /* Boot devices */ usb->DeviceProtocol == 1) { /* Boot keyboards */ retval = 1; goto out; } } path = NextDevicePathNode(path); } } out: free(hin); return retval; } EFI_STATUS main(int argc, CHAR16 *argv[]) { char var[128]; EFI_LOADED_IMAGE *img; EFI_GUID *guid; int i, j, vargood, unit, howto; struct devsw *dev; uint64_t pool_guid; UINTN k; int has_kbd; archsw.arch_autoload = efi_autoload; archsw.arch_getdev = efi_getdev; archsw.arch_copyin = efi_copyin; archsw.arch_copyout = efi_copyout; archsw.arch_readin = efi_readin; #ifdef EFI_ZFS_BOOT /* Note this needs to be set before ZFS init. */ archsw.arch_zfs_probe = efi_zfs_probe; #endif has_kbd = has_keyboard(); /* * XXX Chicken-and-egg problem; we want to have console output * early, but some console attributes may depend on reading from * eg. the boot device, which we can't do yet. We can use * printf() etc. once this is done. */ cons_probe(); /* * Initialise the block cache. Set the upper limit. */ bcache_init(32768, 512); /* * Parse the args to set the console settings, etc * boot1.efi passes these in, if it can read /boot.config or /boot/config * or iPXE may be setup to pass these in. * * Loop through the args, and for each one that contains an '=' that is * not the first character, add it to the environment. This allows * loader and kernel env vars to be passed on the command line. Convert * args from UCS-2 to ASCII (16 to 8 bit) as they are copied. */ howto = 0; for (i = 1; i < argc; i++) { if (argv[i][0] == '-') { for (j = 1; argv[i][j] != 0; j++) { int ch; ch = argv[i][j]; switch (ch) { case 'a': howto |= RB_ASKNAME; break; case 'd': howto |= RB_KDB; break; case 'D': howto |= RB_MULTIPLE; break; case 'h': howto |= RB_SERIAL; break; case 'm': howto |= RB_MUTE; break; case 'p': howto |= RB_PAUSE; break; case 'P': if (!has_kbd) howto |= RB_SERIAL | RB_MULTIPLE; break; case 'r': howto |= RB_DFLTROOT; break; case 's': howto |= RB_SINGLE; break; case 'S': if (argv[i][j + 1] == 0) { if (i + 1 == argc) { setenv("comconsole_speed", "115200", 1); } else { cp16to8(&argv[i + 1][0], var, sizeof(var)); setenv("comconsole_speedspeed", var, 1); } i++; break; } else { cp16to8(&argv[i][j + 1], var, sizeof(var)); setenv("comconsole_speed", var, 1); break; } case 'v': howto |= RB_VERBOSE; break; } } } else { vargood = 0; for (j = 0; argv[i][j] != 0; j++) { if (j == sizeof(var)) { vargood = 0; break; } if (j > 0 && argv[i][j] == '=') vargood = 1; var[j] = (char)argv[i][j]; } if (vargood) { var[j] = 0; putenv(var); } } } for (i = 0; howto_names[i].ev != NULL; i++) if (howto & howto_names[i].mask) setenv(howto_names[i].ev, "YES", 1); if (howto & RB_MULTIPLE) { if (howto & RB_SERIAL) setenv("console", "comconsole efi" , 1); else setenv("console", "efi comconsole" , 1); } else if (howto & RB_SERIAL) { setenv("console", "comconsole" , 1); } if (efi_copy_init()) { printf("failed to allocate staging area\n"); return (EFI_BUFFER_TOO_SMALL); } /* * March through the device switch probing for things. */ for (i = 0; devsw[i] != NULL; i++) if (devsw[i]->dv_init != NULL) (devsw[i]->dv_init)(); /* Get our loaded image protocol interface structure. */ BS->HandleProtocol(IH, &imgid, (VOID**)&img); printf("Command line arguments:"); for (i = 0; i < argc; i++) { printf(" "); print_str16(argv[i]); } printf("\n"); printf("Image base: 0x%lx\n", (u_long)img->ImageBase); printf("EFI version: %d.%02d\n", ST->Hdr.Revision >> 16, ST->Hdr.Revision & 0xffff); printf("EFI Firmware: "); /* printf doesn't understand EFI Unicode */ ST->ConOut->OutputString(ST->ConOut, ST->FirmwareVendor); printf(" (rev %d.%02d)\n", ST->FirmwareRevision >> 16, ST->FirmwareRevision & 0xffff); printf("\n"); printf("%s, Revision %s\n", bootprog_name, bootprog_rev); printf("(%s, %s)\n", bootprog_maker, bootprog_date); /* * Disable the watchdog timer. By default the boot manager sets * the timer to 5 minutes before invoking a boot option. If we * want to return to the boot manager, we have to disable the * watchdog timer and since we're an interactive program, we don't * want to wait until the user types "quit". The timer may have * fired by then. We don't care if this fails. It does not prevent * normal functioning in any way... */ BS->SetWatchdogTimer(0, 0, 0, NULL); if (efi_handle_lookup(img->DeviceHandle, &dev, &unit, &pool_guid) != 0) return (EFI_NOT_FOUND); switch (dev->dv_type) { #ifdef EFI_ZFS_BOOT case DEVT_ZFS: { struct zfs_devdesc currdev; currdev.d_dev = dev; currdev.d_unit = unit; currdev.d_type = currdev.d_dev->dv_type; currdev.d_opendata = NULL; currdev.pool_guid = pool_guid; currdev.root_guid = 0; env_setenv("currdev", EV_VOLATILE, efi_fmtdev(&currdev), efi_setcurrdev, env_nounset); env_setenv("loaddev", EV_VOLATILE, efi_fmtdev(&currdev), env_noset, env_nounset); init_zfs_bootenv(zfs_fmtdev(&currdev)); break; } #endif default: { struct devdesc currdev; currdev.d_dev = dev; currdev.d_unit = unit; currdev.d_opendata = NULL; currdev.d_type = currdev.d_dev->dv_type; env_setenv("currdev", EV_VOLATILE, efi_fmtdev(&currdev), efi_setcurrdev, env_nounset); env_setenv("loaddev", EV_VOLATILE, efi_fmtdev(&currdev), env_noset, env_nounset); break; } } setenv("LINES", "24", 1); /* optional */ for (k = 0; k < ST->NumberOfTableEntries; k++) { guid = &ST->ConfigurationTable[k].VendorGuid; if (!memcmp(guid, &smbios, sizeof(EFI_GUID))) { smbios_detect(ST->ConfigurationTable[k].VendorTable); break; } } interact(NULL); /* doesn't return */ return (EFI_SUCCESS); /* keep compiler happy */ } COMMAND_SET(reboot, "reboot", "reboot the system", command_reboot); static int command_reboot(int argc, char *argv[]) { int i; for (i = 0; devsw[i] != NULL; ++i) if (devsw[i]->dv_cleanup != NULL) (devsw[i]->dv_cleanup)(); RS->ResetSystem(EfiResetCold, EFI_SUCCESS, 23, (CHAR16 *)"Reboot from the loader"); /* NOTREACHED */ return (CMD_ERROR); } COMMAND_SET(quit, "quit", "exit the loader", command_quit); static int command_quit(int argc, char *argv[]) { exit(0); return (CMD_OK); } COMMAND_SET(memmap, "memmap", "print memory map", command_memmap); static int command_memmap(int argc, char *argv[]) { UINTN sz; EFI_MEMORY_DESCRIPTOR *map, *p; UINTN key, dsz; UINT32 dver; EFI_STATUS status; int i, ndesc; static char *types[] = { "Reserved", "LoaderCode", "LoaderData", "BootServicesCode", "BootServicesData", "RuntimeServicesCode", "RuntimeServicesData", "ConventionalMemory", "UnusableMemory", "ACPIReclaimMemory", "ACPIMemoryNVS", "MemoryMappedIO", "MemoryMappedIOPortSpace", "PalCode" }; sz = 0; status = BS->GetMemoryMap(&sz, 0, &key, &dsz, &dver); if (status != EFI_BUFFER_TOO_SMALL) { printf("Can't determine memory map size\n"); return (CMD_ERROR); } map = malloc(sz); status = BS->GetMemoryMap(&sz, map, &key, &dsz, &dver); if (EFI_ERROR(status)) { printf("Can't read memory map\n"); return (CMD_ERROR); } ndesc = sz / dsz; printf("%23s %12s %12s %8s %4s\n", "Type", "Physical", "Virtual", "#Pages", "Attr"); for (i = 0, p = map; i < ndesc; i++, p = NextMemoryDescriptor(p, dsz)) { printf("%23s %012jx %012jx %08jx ", types[p->Type], (uintmax_t)p->PhysicalStart, (uintmax_t)p->VirtualStart, (uintmax_t)p->NumberOfPages); if (p->Attribute & EFI_MEMORY_UC) printf("UC "); if (p->Attribute & EFI_MEMORY_WC) printf("WC "); if (p->Attribute & EFI_MEMORY_WT) printf("WT "); if (p->Attribute & EFI_MEMORY_WB) printf("WB "); if (p->Attribute & EFI_MEMORY_UCE) printf("UCE "); if (p->Attribute & EFI_MEMORY_WP) printf("WP "); if (p->Attribute & EFI_MEMORY_RP) printf("RP "); if (p->Attribute & EFI_MEMORY_XP) printf("XP "); printf("\n"); } return (CMD_OK); } COMMAND_SET(configuration, "configuration", "print configuration tables", command_configuration); static const char * guid_to_string(EFI_GUID *guid) { static char buf[40]; sprintf(buf, "%08x-%04x-%04x-%02x%02x-%02x%02x%02x%02x%02x%02x", guid->Data1, guid->Data2, guid->Data3, guid->Data4[0], guid->Data4[1], guid->Data4[2], guid->Data4[3], guid->Data4[4], guid->Data4[5], guid->Data4[6], guid->Data4[7]); return (buf); } static int command_configuration(int argc, char *argv[]) { UINTN i; printf("NumberOfTableEntries=%lu\n", (unsigned long)ST->NumberOfTableEntries); for (i = 0; i < ST->NumberOfTableEntries; i++) { EFI_GUID *guid; printf(" "); guid = &ST->ConfigurationTable[i].VendorGuid; if (!memcmp(guid, &mps, sizeof(EFI_GUID))) printf("MPS Table"); else if (!memcmp(guid, &acpi, sizeof(EFI_GUID))) printf("ACPI Table"); else if (!memcmp(guid, &acpi20, sizeof(EFI_GUID))) printf("ACPI 2.0 Table"); else if (!memcmp(guid, &smbios, sizeof(EFI_GUID))) printf("SMBIOS Table"); else if (!memcmp(guid, &dxe, sizeof(EFI_GUID))) printf("DXE Table"); else if (!memcmp(guid, &hoblist, sizeof(EFI_GUID))) printf("HOB List Table"); else if (!memcmp(guid, &memtype, sizeof(EFI_GUID))) printf("Memory Type Information Table"); else if (!memcmp(guid, &debugimg, sizeof(EFI_GUID))) printf("Debug Image Info Table"); else if (!memcmp(guid, &fdtdtb, sizeof(EFI_GUID))) printf("FDT Table"); else printf("Unknown Table (%s)", guid_to_string(guid)); printf(" at %p\n", ST->ConfigurationTable[i].VendorTable); } return (CMD_OK); } COMMAND_SET(mode, "mode", "change or display EFI text modes", command_mode); static int command_mode(int argc, char *argv[]) { UINTN cols, rows; unsigned int mode; int i; char *cp; char rowenv[8]; EFI_STATUS status; SIMPLE_TEXT_OUTPUT_INTERFACE *conout; extern void HO(void); conout = ST->ConOut; if (argc > 1) { mode = strtol(argv[1], &cp, 0); if (cp[0] != '\0') { printf("Invalid mode\n"); return (CMD_ERROR); } status = conout->QueryMode(conout, mode, &cols, &rows); if (EFI_ERROR(status)) { printf("invalid mode %d\n", mode); return (CMD_ERROR); } status = conout->SetMode(conout, mode); if (EFI_ERROR(status)) { printf("couldn't set mode %d\n", mode); return (CMD_ERROR); } sprintf(rowenv, "%u", (unsigned)rows); setenv("LINES", rowenv, 1); HO(); /* set cursor */ return (CMD_OK); } printf("Current mode: %d\n", conout->Mode->Mode); for (i = 0; i <= conout->Mode->MaxMode; i++) { status = conout->QueryMode(conout, i, &cols, &rows); if (EFI_ERROR(status)) continue; printf("Mode %d: %u columns, %u rows\n", i, (unsigned)cols, (unsigned)rows); } if (i != 0) printf("Select a mode with the command \"mode \"\n"); return (CMD_OK); } COMMAND_SET(nvram, "nvram", "get or set NVRAM variables", command_nvram); static int command_nvram(int argc, char *argv[]) { CHAR16 var[128]; CHAR16 *data; EFI_STATUS status; EFI_GUID varguid = { 0,0,0,{0,0,0,0,0,0,0,0} }; UINTN varsz, datasz, i; SIMPLE_TEXT_OUTPUT_INTERFACE *conout; conout = ST->ConOut; /* Initiate the search */ status = RS->GetNextVariableName(&varsz, NULL, NULL); for (; status != EFI_NOT_FOUND; ) { status = RS->GetNextVariableName(&varsz, var, &varguid); //if (EFI_ERROR(status)) //break; conout->OutputString(conout, var); printf("="); datasz = 0; status = RS->GetVariable(var, &varguid, NULL, &datasz, NULL); /* XXX: check status */ data = malloc(datasz); status = RS->GetVariable(var, &varguid, NULL, &datasz, data); if (EFI_ERROR(status)) printf(""); else { for (i = 0; i < datasz; i++) { if (isalnum(data[i]) || isspace(data[i])) printf("%c", data[i]); else printf("\\x%02x", data[i]); } } /* XXX */ pager_output("\n"); free(data); } return (CMD_OK); } #ifdef EFI_ZFS_BOOT COMMAND_SET(lszfs, "lszfs", "list child datasets of a zfs dataset", command_lszfs); static int command_lszfs(int argc, char *argv[]) { int err; if (argc != 2) { command_errmsg = "wrong number of arguments"; return (CMD_ERROR); } err = zfs_list(argv[1]); if (err != 0) { command_errmsg = strerror(err); return (CMD_ERROR); } return (CMD_OK); } COMMAND_SET(reloadbe, "reloadbe", "refresh the list of ZFS Boot Environments", command_reloadbe); static int command_reloadbe(int argc, char *argv[]) { int err; char *root; if (argc > 2) { command_errmsg = "wrong number of arguments"; return (CMD_ERROR); } if (argc == 2) { err = zfs_bootenv(argv[1]); } else { root = getenv("zfs_be_root"); if (root == NULL) { return (CMD_OK); } err = zfs_bootenv(root); } if (err != 0) { command_errmsg = strerror(err); return (CMD_ERROR); } return (CMD_OK); } #endif #ifdef LOADER_FDT_SUPPORT extern int command_fdt_internal(int argc, char *argv[]); /* * Since proper fdt command handling function is defined in fdt_loader_cmd.c, * and declaring it as extern is in contradiction with COMMAND_SET() macro * (which uses static pointer), we're defining wrapper function, which * calls the proper fdt handling routine. */ static int command_fdt(int argc, char *argv[]) { return (command_fdt_internal(argc, argv)); } COMMAND_SET(fdt, "fdt", "flattened device tree handling", command_fdt); #endif #ifdef EFI_ZFS_BOOT static void efi_zfs_probe(void) { EFI_HANDLE h; u_int unit; int i; char dname[SPECNAMELEN + 1]; uint64_t guid; unit = 0; h = efi_find_handle(&efipart_dev, 0); for (i = 0; h != NULL; h = efi_find_handle(&efipart_dev, ++i)) { snprintf(dname, sizeof(dname), "%s%d:", efipart_dev.dv_name, i); if (zfs_probe_dev(dname, &guid) == 0) (void)efi_handle_update_dev(h, &zfs_dev, unit++, guid); } } #endif Index: head/sys/boot/fdt/fdt_loader_cmd.c =================================================================== --- head/sys/boot/fdt/fdt_loader_cmd.c (revision 298825) +++ head/sys/boot/fdt/fdt_loader_cmd.c (revision 298826) @@ -1,1701 +1,1701 @@ /*- * Copyright (c) 2009-2010 The FreeBSD Foundation * All rights reserved. * * This software was developed by Semihalf under sponsorship from * the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include "bootstrap.h" #include "fdt_platform.h" #include "fdt_overlay.h" #ifdef DEBUG #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ printf(fmt,##args); } while (0) #else #define debugf(fmt, args...) #endif #define FDT_CWD_LEN 256 #define FDT_MAX_DEPTH 6 #define FDT_PROP_SEP " = " #define COPYOUT(s,d,l) archsw.arch_copyout(s, d, l) #define COPYIN(s,d,l) archsw.arch_copyin(s, d, l) #define FDT_STATIC_DTB_SYMBOL "fdt_static_dtb" #define CMD_REQUIRES_BLOB 0x01 /* Location of FDT yet to be loaded. */ /* This may be in read-only memory, so can't be manipulated directly. */ static struct fdt_header *fdt_to_load = NULL; /* Location of FDT on heap. */ /* This is the copy we actually manipulate. */ static struct fdt_header *fdtp = NULL; /* Size of FDT blob */ static size_t fdtp_size = 0; /* Location of FDT in kernel or module. */ /* This won't be set if FDT is loaded from disk or memory. */ /* If it is set, we'll update it when fdt_copy() gets called. */ static vm_offset_t fdtp_va = 0; static int fdt_load_dtb(vm_offset_t va); static int fdt_cmd_nyi(int argc, char *argv[]); static int fdt_cmd_addr(int argc, char *argv[]); static int fdt_cmd_mkprop(int argc, char *argv[]); static int fdt_cmd_cd(int argc, char *argv[]); static int fdt_cmd_hdr(int argc, char *argv[]); static int fdt_cmd_ls(int argc, char *argv[]); static int fdt_cmd_prop(int argc, char *argv[]); static int fdt_cmd_pwd(int argc, char *argv[]); static int fdt_cmd_rm(int argc, char *argv[]); static int fdt_cmd_mknode(int argc, char *argv[]); static int fdt_cmd_mres(int argc, char *argv[]); typedef int cmdf_t(int, char *[]); struct cmdtab { const char *name; cmdf_t *handler; int flags; }; static const struct cmdtab commands[] = { { "addr", &fdt_cmd_addr, 0 }, { "alias", &fdt_cmd_nyi, 0 }, { "cd", &fdt_cmd_cd, CMD_REQUIRES_BLOB }, { "header", &fdt_cmd_hdr, CMD_REQUIRES_BLOB }, { "ls", &fdt_cmd_ls, CMD_REQUIRES_BLOB }, { "mknode", &fdt_cmd_mknode, CMD_REQUIRES_BLOB }, { "mkprop", &fdt_cmd_mkprop, CMD_REQUIRES_BLOB }, { "mres", &fdt_cmd_mres, CMD_REQUIRES_BLOB }, { "prop", &fdt_cmd_prop, CMD_REQUIRES_BLOB }, { "pwd", &fdt_cmd_pwd, CMD_REQUIRES_BLOB }, { "rm", &fdt_cmd_rm, CMD_REQUIRES_BLOB }, { NULL, NULL } }; static char cwd[FDT_CWD_LEN] = "/"; static vm_offset_t fdt_find_static_dtb() { Elf_Ehdr *ehdr; Elf_Shdr *shdr; Elf_Sym sym; vm_offset_t strtab, symtab, fdt_start; uint64_t offs; struct preloaded_file *kfp; struct file_metadata *md; char *strp; int i, sym_count; debugf("fdt_find_static_dtb()\n"); sym_count = symtab = strtab = 0; strp = NULL; offs = __elfN(relocation_offset); kfp = file_findfile(NULL, NULL); if (kfp == NULL) return (0); /* Locate the dynamic symbols and strtab. */ md = file_findmetadata(kfp, MODINFOMD_ELFHDR); if (md == NULL) return (0); ehdr = (Elf_Ehdr *)md->md_data; md = file_findmetadata(kfp, MODINFOMD_SHDR); if (md == NULL) return (0); shdr = (Elf_Shdr *)md->md_data; for (i = 0; i < ehdr->e_shnum; ++i) { if (shdr[i].sh_type == SHT_DYNSYM && symtab == 0) { symtab = shdr[i].sh_addr + offs; sym_count = shdr[i].sh_size / sizeof(Elf_Sym); } else if (shdr[i].sh_type == SHT_STRTAB && strtab == 0) { strtab = shdr[i].sh_addr + offs; } } /* - * The most efficent way to find a symbol would be to calculate a + * The most efficient way to find a symbol would be to calculate a * hash, find proper bucket and chain, and thus find a symbol. * However, that would involve code duplication (e.g. for hash * function). So we're using simpler and a bit slower way: we're * iterating through symbols, searching for the one which name is * 'equal' to 'fdt_static_dtb'. To speed up the process a little bit, * we are eliminating symbols type of which is not STT_NOTYPE, or(and) * those which binding attribute is not STB_GLOBAL. */ fdt_start = 0; while (sym_count > 0 && fdt_start == 0) { COPYOUT(symtab, &sym, sizeof(sym)); symtab += sizeof(sym); --sym_count; if (ELF_ST_BIND(sym.st_info) != STB_GLOBAL || ELF_ST_TYPE(sym.st_info) != STT_NOTYPE) continue; strp = strdupout(strtab + sym.st_name); if (strcmp(strp, FDT_STATIC_DTB_SYMBOL) == 0) fdt_start = (vm_offset_t)sym.st_value + offs; free(strp); } return (fdt_start); } static int fdt_load_dtb(vm_offset_t va) { struct fdt_header header; int err; debugf("fdt_load_dtb(0x%08jx)\n", (uintmax_t)va); COPYOUT(va, &header, sizeof(header)); err = fdt_check_header(&header); if (err < 0) { if (err == -FDT_ERR_BADVERSION) sprintf(command_errbuf, "incompatible blob version: %d, should be: %d", fdt_version(fdtp), FDT_LAST_SUPPORTED_VERSION); else sprintf(command_errbuf, "error validating blob: %s", fdt_strerror(err)); return (1); } /* * Release previous blob */ if (fdtp) free(fdtp); fdtp_size = fdt_totalsize(&header); fdtp = malloc(fdtp_size); if (fdtp == NULL) { command_errmsg = "can't allocate memory for device tree copy"; return (1); } fdtp_va = va; COPYOUT(va, fdtp, fdtp_size); debugf("DTB blob found at 0x%jx, size: 0x%jx\n", (uintmax_t)va, (uintmax_t)fdtp_size); return (0); } int fdt_load_dtb_addr(struct fdt_header *header) { int err; debugf("fdt_load_dtb_addr(%p)\n", header); fdtp_size = fdt_totalsize(header); err = fdt_check_header(header); if (err < 0) { sprintf(command_errbuf, "error validating blob: %s", fdt_strerror(err)); return (err); } free(fdtp); if ((fdtp = malloc(fdtp_size)) == NULL) { command_errmsg = "can't allocate memory for device tree copy"; return (1); } fdtp_va = 0; // Don't write this back into module or kernel. bcopy(header, fdtp, fdtp_size); return (0); } int fdt_load_dtb_file(const char * filename) { struct preloaded_file *bfp, *oldbfp; int err; debugf("fdt_load_dtb_file(%s)\n", filename); oldbfp = file_findfile(NULL, "dtb"); /* Attempt to load and validate a new dtb from a file. */ if ((bfp = file_loadraw(filename, "dtb", 1)) == NULL) { sprintf(command_errbuf, "failed to load file '%s'", filename); return (1); } if ((err = fdt_load_dtb(bfp->f_addr)) != 0) { file_discard(bfp); return (err); } /* A new dtb was validated, discard any previous file. */ if (oldbfp) file_discard(oldbfp); return (0); } static int fdt_load_dtb_overlay(const char * filename) { struct preloaded_file *bfp, *oldbfp; struct fdt_header header; int err; debugf("fdt_load_dtb_overlay(%s)\n", filename); oldbfp = file_findfile(filename, "dtbo"); /* Attempt to load and validate a new dtb from a file. */ if ((bfp = file_loadraw(filename, "dtbo", 1)) == NULL) { printf("failed to load file '%s'\n", filename); return (1); } COPYOUT(bfp->f_addr, &header, sizeof(header)); err = fdt_check_header(&header); if (err < 0) { file_discard(bfp); if (err == -FDT_ERR_BADVERSION) printf("incompatible blob version: %d, should be: %d\n", fdt_version(fdtp), FDT_LAST_SUPPORTED_VERSION); else printf("error validating blob: %s\n", fdt_strerror(err)); return (1); } /* A new dtb was validated, discard any previous file. */ if (oldbfp) file_discard(oldbfp); return (0); } int fdt_load_dtb_overlays(const char * filenames) { char *names; char *name; char *comaptr; debugf("fdt_load_dtb_overlay(%s)\n", filenames); names = strdup(filenames); if (names == NULL) return (1); name = names; do { comaptr = strchr(name, ','); if (comaptr) *comaptr = '\0'; fdt_load_dtb_overlay(name); name = comaptr + 1; } while(comaptr); free(names); return (0); } void fdt_apply_overlays() { struct preloaded_file *fp; size_t overlays_size, max_overlay_size, new_fdtp_size; void *new_fdtp; void *overlay; int rv; if ((fdtp == NULL) || (fdtp_size == 0)) return; overlays_size = 0; max_overlay_size = 0; for (fp = file_findfile(NULL, "dtbo"); fp != NULL; fp = fp->f_next) { if (max_overlay_size < fp->f_size) max_overlay_size = fp->f_size; overlays_size += fp->f_size; } /* Nothing to apply */ if (overlays_size == 0) return; /* It's actually more than enough */ new_fdtp_size = fdtp_size + overlays_size; new_fdtp = malloc(new_fdtp_size); if (new_fdtp == NULL) { printf("failed to allocate memory for DTB blob with overlays\n"); return; } overlay = malloc(max_overlay_size); if (overlay == NULL) { printf("failed to allocate memory for DTB blob with overlays\n"); free(new_fdtp); return; } rv = fdt_open_into(fdtp, new_fdtp, new_fdtp_size); if (rv != 0) { printf("failed to open DTB blob for applying overlays\n"); return; } for (fp = file_findfile(NULL, "dtbo"); fp != NULL; fp = fp->f_next) { printf("applying DTB overlay '%s'\n", fp->f_name); COPYOUT(fp->f_addr, overlay, fp->f_size); fdt_overlay_apply(new_fdtp, overlay, fp->f_size); } free(fdtp); fdtp = new_fdtp; fdtp_size = new_fdtp_size; free(overlay); } int fdt_setup_fdtp() { struct preloaded_file *bfp; vm_offset_t va; debugf("fdt_setup_fdtp()\n"); /* If we already loaded a file, use it. */ if ((bfp = file_findfile(NULL, "dtb")) != NULL) { if (fdt_load_dtb(bfp->f_addr) == 0) { printf("Using DTB from loaded file '%s'.\n", bfp->f_name); return (0); } } /* If we were given the address of a valid blob in memory, use it. */ if (fdt_to_load != NULL) { if (fdt_load_dtb_addr(fdt_to_load) == 0) { printf("Using DTB from memory address 0x%p.\n", fdt_to_load); return (0); } } if (fdt_platform_load_dtb() == 0) return (0); /* If there is a dtb compiled into the kernel, use it. */ if ((va = fdt_find_static_dtb()) != 0) { if (fdt_load_dtb(va) == 0) { printf("Using DTB compiled into kernel.\n"); return (0); } } command_errmsg = "No device tree blob found!\n"; return (1); } #define fdt_strtovect(str, cellbuf, lim, cellsize) _fdt_strtovect((str), \ (cellbuf), (lim), (cellsize), 0); /* Force using base 16 */ #define fdt_strtovectx(str, cellbuf, lim, cellsize) _fdt_strtovect((str), \ (cellbuf), (lim), (cellsize), 16); static int _fdt_strtovect(const char *str, void *cellbuf, int lim, unsigned char cellsize, uint8_t base) { const char *buf = str; const char *end = str + strlen(str) - 2; uint32_t *u32buf = NULL; uint8_t *u8buf = NULL; int cnt = 0; if (cellsize == sizeof(uint32_t)) u32buf = (uint32_t *)cellbuf; else u8buf = (uint8_t *)cellbuf; if (lim == 0) return (0); while (buf < end) { /* Skip white whitespace(s)/separators */ while (!isxdigit(*buf) && buf < end) buf++; if (u32buf != NULL) u32buf[cnt] = cpu_to_fdt32((uint32_t)strtol(buf, NULL, base)); else u8buf[cnt] = (uint8_t)strtol(buf, NULL, base); if (cnt + 1 <= lim - 1) cnt++; else break; buf++; /* Find another number */ while ((isxdigit(*buf) || *buf == 'x') && buf < end) buf++; } return (cnt); } void fdt_fixup_ethernet(const char *str, char *ethstr, int len) { uint8_t tmp_addr[6]; /* Convert macaddr string into a vector of uints */ fdt_strtovectx(str, &tmp_addr, 6, sizeof(uint8_t)); /* Set actual property to a value from vect */ fdt_setprop(fdtp, fdt_path_offset(fdtp, ethstr), "local-mac-address", &tmp_addr, 6 * sizeof(uint8_t)); } void fdt_fixup_cpubusfreqs(unsigned long cpufreq, unsigned long busfreq) { int lo, o = 0, o2, maxo = 0, depth; const uint32_t zero = 0; /* We want to modify every subnode of /cpus */ o = fdt_path_offset(fdtp, "/cpus"); if (o < 0) return; /* maxo should contain offset of node next to /cpus */ depth = 0; maxo = o; while (depth != -1) maxo = fdt_next_node(fdtp, maxo, &depth); /* Find CPU frequency properties */ o = fdt_node_offset_by_prop_value(fdtp, o, "clock-frequency", &zero, sizeof(uint32_t)); o2 = fdt_node_offset_by_prop_value(fdtp, o, "bus-frequency", &zero, sizeof(uint32_t)); lo = MIN(o, o2); while (o != -FDT_ERR_NOTFOUND && o2 != -FDT_ERR_NOTFOUND) { o = fdt_node_offset_by_prop_value(fdtp, lo, "clock-frequency", &zero, sizeof(uint32_t)); o2 = fdt_node_offset_by_prop_value(fdtp, lo, "bus-frequency", &zero, sizeof(uint32_t)); /* We're only interested in /cpus subnode(s) */ if (lo > maxo) break; fdt_setprop_inplace_cell(fdtp, lo, "clock-frequency", (uint32_t)cpufreq); fdt_setprop_inplace_cell(fdtp, lo, "bus-frequency", (uint32_t)busfreq); lo = MIN(o, o2); } } #ifdef notyet static int fdt_reg_valid(uint32_t *reg, int len, int addr_cells, int size_cells) { int cells_in_tuple, i, tuples, tuple_size; uint32_t cur_start, cur_size; cells_in_tuple = (addr_cells + size_cells); tuple_size = cells_in_tuple * sizeof(uint32_t); tuples = len / tuple_size; if (tuples == 0) return (EINVAL); for (i = 0; i < tuples; i++) { if (addr_cells == 2) cur_start = fdt64_to_cpu(reg[i * cells_in_tuple]); else cur_start = fdt32_to_cpu(reg[i * cells_in_tuple]); if (size_cells == 2) cur_size = fdt64_to_cpu(reg[i * cells_in_tuple + 2]); else cur_size = fdt32_to_cpu(reg[i * cells_in_tuple + 1]); if (cur_size == 0) return (EINVAL); debugf(" reg#%d (start: 0x%0x size: 0x%0x) valid!\n", i, cur_start, cur_size); } return (0); } #endif void fdt_fixup_memory(struct fdt_mem_region *region, size_t num) { struct fdt_mem_region *curmr; uint32_t addr_cells, size_cells; uint32_t *addr_cellsp, *size_cellsp; int err, i, len, memory, root; size_t realmrno; uint8_t *buf, *sb; uint64_t rstart, rsize; int reserved; root = fdt_path_offset(fdtp, "/"); if (root < 0) { sprintf(command_errbuf, "Could not find root node !"); return; } memory = fdt_path_offset(fdtp, "/memory"); if (memory <= 0) { /* Create proper '/memory' node. */ memory = fdt_add_subnode(fdtp, root, "memory"); if (memory <= 0) { sprintf(command_errbuf, "Could not fixup '/memory' " "node, error code : %d!\n", memory); return; } err = fdt_setprop(fdtp, memory, "device_type", "memory", sizeof("memory")); if (err < 0) return; } addr_cellsp = (uint32_t *)fdt_getprop(fdtp, root, "#address-cells", NULL); size_cellsp = (uint32_t *)fdt_getprop(fdtp, root, "#size-cells", NULL); if (addr_cellsp == NULL || size_cellsp == NULL) { sprintf(command_errbuf, "Could not fixup '/memory' node : " "%s %s property not found in root node!\n", (!addr_cellsp) ? "#address-cells" : "", (!size_cellsp) ? "#size-cells" : ""); return; } addr_cells = fdt32_to_cpu(*addr_cellsp); size_cells = fdt32_to_cpu(*size_cellsp); /* * Convert memreserve data to memreserve property * Check if property already exists */ reserved = fdt_num_mem_rsv(fdtp); if (reserved && (fdt_getprop(fdtp, root, "memreserve", NULL) == NULL)) { len = (addr_cells + size_cells) * reserved * sizeof(uint32_t); sb = buf = (uint8_t *)malloc(len); if (!buf) return; bzero(buf, len); for (i = 0; i < reserved; i++) { if (fdt_get_mem_rsv(fdtp, i, &rstart, &rsize)) break; if (rsize) { - /* Ensure endianess, and put cells into a buffer */ + /* Ensure endianness, and put cells into a buffer */ if (addr_cells == 2) *(uint64_t *)buf = cpu_to_fdt64(rstart); else *(uint32_t *)buf = cpu_to_fdt32(rstart); buf += sizeof(uint32_t) * addr_cells; if (size_cells == 2) *(uint64_t *)buf = cpu_to_fdt64(rsize); else *(uint32_t *)buf = cpu_to_fdt32(rsize); buf += sizeof(uint32_t) * size_cells; } } /* Set property */ if ((err = fdt_setprop(fdtp, root, "memreserve", sb, len)) < 0) printf("Could not fixup 'memreserve' property.\n"); free(sb); } /* Count valid memory regions entries in sysinfo. */ realmrno = num; for (i = 0; i < num; i++) if (region[i].start == 0 && region[i].size == 0) realmrno--; if (realmrno == 0) { sprintf(command_errbuf, "Could not fixup '/memory' node : " "sysinfo doesn't contain valid memory regions info!\n"); return; } len = (addr_cells + size_cells) * realmrno * sizeof(uint32_t); sb = buf = (uint8_t *)malloc(len); if (!buf) return; bzero(buf, len); for (i = 0; i < num; i++) { curmr = ®ion[i]; if (curmr->size != 0) { - /* Ensure endianess, and put cells into a buffer */ + /* Ensure endianness, and put cells into a buffer */ if (addr_cells == 2) *(uint64_t *)buf = cpu_to_fdt64(curmr->start); else *(uint32_t *)buf = cpu_to_fdt32(curmr->start); buf += sizeof(uint32_t) * addr_cells; if (size_cells == 2) *(uint64_t *)buf = cpu_to_fdt64(curmr->size); else *(uint32_t *)buf = cpu_to_fdt32(curmr->size); buf += sizeof(uint32_t) * size_cells; } } /* Set property */ if ((err = fdt_setprop(fdtp, memory, "reg", sb, len)) < 0) sprintf(command_errbuf, "Could not fixup '/memory' node.\n"); free(sb); } void fdt_fixup_stdout(const char *str) { char *ptr; int serialno; int len, no, sero; const struct fdt_property *prop; char *tmp[10]; ptr = (char *)str + strlen(str) - 1; while (ptr > str && isdigit(*(str - 1))) str--; if (ptr == str) return; serialno = (int)strtol(ptr, NULL, 0); no = fdt_path_offset(fdtp, "/chosen"); if (no < 0) return; prop = fdt_get_property(fdtp, no, "stdout", &len); /* If /chosen/stdout does not extist, create it */ if (prop == NULL || (prop != NULL && len == 0)) { bzero(tmp, 10 * sizeof(char)); strcpy((char *)&tmp, "serial"); if (strlen(ptr) > 3) /* Serial number too long */ return; strncpy((char *)tmp + 6, ptr, 3); sero = fdt_path_offset(fdtp, (const char *)tmp); if (sero < 0) /* * If serial device we're trying to assign * stdout to doesn't exist in DT -- return. */ return; fdt_setprop(fdtp, no, "stdout", &tmp, strlen((char *)&tmp) + 1); fdt_setprop(fdtp, no, "stdin", &tmp, strlen((char *)&tmp) + 1); } } /* * Locate the blob, fix it up and return its location. */ static int fdt_fixup(void) { int chosen, len; len = 0; debugf("fdt_fixup()\n"); if (fdtp == NULL && fdt_setup_fdtp() != 0) return (0); /* Create /chosen node (if not exists) */ if ((chosen = fdt_subnode_offset(fdtp, 0, "chosen")) == -FDT_ERR_NOTFOUND) chosen = fdt_add_subnode(fdtp, 0, "chosen"); /* Value assigned to fixup-applied does not matter. */ if (fdt_getprop(fdtp, chosen, "fixup-applied", NULL)) return (1); fdt_platform_fixups(); fdt_setprop(fdtp, chosen, "fixup-applied", NULL, 0); return (1); } /* * Copy DTB blob to specified location and return size */ int fdt_copy(vm_offset_t va) { int err; debugf("fdt_copy va 0x%08x\n", va); if (fdtp == NULL) { err = fdt_setup_fdtp(); if (err) { printf("No valid device tree blob found!\n"); return (0); } } if (fdt_fixup() == 0) return (0); if (fdtp_va != 0) { /* Overwrite the FDT with the fixed version. */ /* XXX Is this really appropriate? */ COPYIN(fdtp, fdtp_va, fdtp_size); } COPYIN(fdtp, va, fdtp_size); return (fdtp_size); } int command_fdt_internal(int argc, char *argv[]) { cmdf_t *cmdh; int flags; char *cmd; int i, err; if (argc < 2) { command_errmsg = "usage is 'fdt []"; return (CMD_ERROR); } /* * Validate fdt . */ cmd = strdup(argv[1]); i = 0; cmdh = NULL; while (!(commands[i].name == NULL)) { if (strcmp(cmd, commands[i].name) == 0) { /* found it */ cmdh = commands[i].handler; flags = commands[i].flags; break; } i++; } if (cmdh == NULL) { command_errmsg = "unknown command"; return (CMD_ERROR); } if (flags & CMD_REQUIRES_BLOB) { /* * Check if uboot env vars were parsed already. If not, do it now. */ if (fdt_fixup() == 0) return (CMD_ERROR); } /* * Call command handler. */ err = (*cmdh)(argc, argv); return (err); } static int fdt_cmd_addr(int argc, char *argv[]) { struct preloaded_file *fp; struct fdt_header *hdr; const char *addr; char *cp; fdt_to_load = NULL; if (argc > 2) addr = argv[2]; else { sprintf(command_errbuf, "no address specified"); return (CMD_ERROR); } hdr = (struct fdt_header *)strtoul(addr, &cp, 16); if (cp == addr) { sprintf(command_errbuf, "Invalid address: %s", addr); return (CMD_ERROR); } while ((fp = file_findfile(NULL, "dtb")) != NULL) { file_discard(fp); } fdt_to_load = hdr; return (CMD_OK); } static int fdt_cmd_cd(int argc, char *argv[]) { char *path; char tmp[FDT_CWD_LEN]; int len, o; path = (argc > 2) ? argv[2] : "/"; if (path[0] == '/') { len = strlen(path); if (len >= FDT_CWD_LEN) goto fail; } else { /* Handle path specification relative to cwd */ len = strlen(cwd) + strlen(path) + 1; if (len >= FDT_CWD_LEN) goto fail; strcpy(tmp, cwd); strcat(tmp, "/"); strcat(tmp, path); path = tmp; } o = fdt_path_offset(fdtp, path); if (o < 0) { sprintf(command_errbuf, "could not find node: '%s'", path); return (CMD_ERROR); } strcpy(cwd, path); return (CMD_OK); fail: sprintf(command_errbuf, "path too long: %d, max allowed: %d", len, FDT_CWD_LEN - 1); return (CMD_ERROR); } static int fdt_cmd_hdr(int argc __unused, char *argv[] __unused) { char line[80]; int ver; if (fdtp == NULL) { command_errmsg = "no device tree blob pointer?!"; return (CMD_ERROR); } ver = fdt_version(fdtp); pager_open(); sprintf(line, "\nFlattened device tree header (%p):\n", fdtp); pager_output(line); sprintf(line, " magic = 0x%08x\n", fdt_magic(fdtp)); pager_output(line); sprintf(line, " size = %d\n", fdt_totalsize(fdtp)); pager_output(line); sprintf(line, " off_dt_struct = 0x%08x\n", fdt_off_dt_struct(fdtp)); pager_output(line); sprintf(line, " off_dt_strings = 0x%08x\n", fdt_off_dt_strings(fdtp)); pager_output(line); sprintf(line, " off_mem_rsvmap = 0x%08x\n", fdt_off_mem_rsvmap(fdtp)); pager_output(line); sprintf(line, " version = %d\n", ver); pager_output(line); sprintf(line, " last compatible version = %d\n", fdt_last_comp_version(fdtp)); pager_output(line); if (ver >= 2) { sprintf(line, " boot_cpuid = %d\n", fdt_boot_cpuid_phys(fdtp)); pager_output(line); } if (ver >= 3) { sprintf(line, " size_dt_strings = %d\n", fdt_size_dt_strings(fdtp)); pager_output(line); } if (ver >= 17) { sprintf(line, " size_dt_struct = %d\n", fdt_size_dt_struct(fdtp)); pager_output(line); } pager_close(); return (CMD_OK); } static int fdt_cmd_ls(int argc, char *argv[]) { const char *prevname[FDT_MAX_DEPTH] = { NULL }; const char *name; char *path; int i, o, depth, len; path = (argc > 2) ? argv[2] : NULL; if (path == NULL) path = cwd; o = fdt_path_offset(fdtp, path); if (o < 0) { sprintf(command_errbuf, "could not find node: '%s'", path); return (CMD_ERROR); } for (depth = 0; (o >= 0) && (depth >= 0); o = fdt_next_node(fdtp, o, &depth)) { name = fdt_get_name(fdtp, o, &len); if (depth > FDT_MAX_DEPTH) { printf("max depth exceeded: %d\n", depth); continue; } prevname[depth] = name; /* Skip root (i = 1) when printing devices */ for (i = 1; i <= depth; i++) { if (prevname[i] == NULL) break; if (strcmp(cwd, "/") == 0) printf("/"); printf("%s", prevname[i]); } printf("\n"); } return (CMD_OK); } static __inline int isprint(int c) { return (c >= ' ' && c <= 0x7e); } static int fdt_isprint(const void *data, int len, int *count) { const char *d; char ch; int yesno, i; if (len == 0) return (0); d = (const char *)data; if (d[len - 1] != '\0') return (0); *count = 0; yesno = 1; for (i = 0; i < len; i++) { ch = *(d + i); if (isprint(ch) || (ch == '\0' && i > 0)) { /* Count strings */ if (ch == '\0') (*count)++; continue; } yesno = 0; break; } return (yesno); } static int fdt_data_str(const void *data, int len, int count, char **buf) { char *b, *tmp; const char *d; int buf_len, i, l; /* * Calculate the length for the string and allocate memory. * * Note that 'len' already includes at least one terminator. */ buf_len = len; if (count > 1) { /* * Each token had already a terminator buried in 'len', but we * only need one eventually, don't count space for these. */ buf_len -= count - 1; /* Each consecutive token requires a ", " separator. */ buf_len += count * 2; } /* Add some space for surrounding double quotes. */ buf_len += count * 2; /* Note that string being put in 'tmp' may be as big as 'buf_len'. */ b = (char *)malloc(buf_len); tmp = (char *)malloc(buf_len); if (b == NULL) goto error; if (tmp == NULL) { free(b); goto error; } b[0] = '\0'; /* * Now that we have space, format the string. */ i = 0; do { d = (const char *)data + i; l = strlen(d) + 1; sprintf(tmp, "\"%s\"%s", d, (i + l) < len ? ", " : ""); strcat(b, tmp); i += l; } while (i < len); *buf = b; free(tmp); return (0); error: return (1); } static int fdt_data_cell(const void *data, int len, char **buf) { char *b, *tmp; const uint32_t *c; int count, i, l; /* Number of cells */ count = len / 4; /* * Calculate the length for the string and allocate memory. */ /* Each byte translates to 2 output characters */ l = len * 2; if (count > 1) { /* Each consecutive cell requires a " " separator. */ l += (count - 1) * 1; } /* Each cell will have a "0x" prefix */ l += count * 2; /* Space for surrounding <> and terminator */ l += 3; b = (char *)malloc(l); tmp = (char *)malloc(l); if (b == NULL) goto error; if (tmp == NULL) { free(b); goto error; } b[0] = '\0'; strcat(b, "<"); for (i = 0; i < len; i += 4) { c = (const uint32_t *)((const uint8_t *)data + i); sprintf(tmp, "0x%08x%s", fdt32_to_cpu(*c), i < (len - 4) ? " " : ""); strcat(b, tmp); } strcat(b, ">"); *buf = b; free(tmp); return (0); error: return (1); } static int fdt_data_bytes(const void *data, int len, char **buf) { char *b, *tmp; const char *d; int i, l; /* * Calculate the length for the string and allocate memory. */ /* Each byte translates to 2 output characters */ l = len * 2; if (len > 1) /* Each consecutive byte requires a " " separator. */ l += (len - 1) * 1; /* Each byte will have a "0x" prefix */ l += len * 2; /* Space for surrounding [] and terminator. */ l += 3; b = (char *)malloc(l); tmp = (char *)malloc(l); if (b == NULL) goto error; if (tmp == NULL) { free(b); goto error; } b[0] = '\0'; strcat(b, "["); for (i = 0, d = data; i < len; i++) { sprintf(tmp, "0x%02x%s", d[i], i < len - 1 ? " " : ""); strcat(b, tmp); } strcat(b, "]"); *buf = b; free(tmp); return (0); error: return (1); } static int fdt_data_fmt(const void *data, int len, char **buf) { int count; if (len == 0) { *buf = NULL; return (1); } if (fdt_isprint(data, len, &count)) return (fdt_data_str(data, len, count, buf)); else if ((len % 4) == 0) return (fdt_data_cell(data, len, buf)); else return (fdt_data_bytes(data, len, buf)); } static int fdt_prop(int offset) { char *line, *buf; const struct fdt_property *prop; const char *name; const void *data; int len, rv; line = NULL; prop = fdt_offset_ptr(fdtp, offset, sizeof(*prop)); if (prop == NULL) return (1); name = fdt_string(fdtp, fdt32_to_cpu(prop->nameoff)); len = fdt32_to_cpu(prop->len); rv = 0; buf = NULL; if (len == 0) { /* Property without value */ line = (char *)malloc(strlen(name) + 2); if (line == NULL) { rv = 2; goto out2; } sprintf(line, "%s\n", name); goto out1; } /* * Process property with value */ data = prop->data; if (fdt_data_fmt(data, len, &buf) != 0) { rv = 3; goto out2; } line = (char *)malloc(strlen(name) + strlen(FDT_PROP_SEP) + strlen(buf) + 2); if (line == NULL) { sprintf(command_errbuf, "could not allocate space for string"); rv = 4; goto out2; } sprintf(line, "%s" FDT_PROP_SEP "%s\n", name, buf); out1: pager_open(); pager_output(line); pager_close(); out2: if (buf) free(buf); if (line) free(line); return (rv); } static int fdt_modprop(int nodeoff, char *propname, void *value, char mode) { uint32_t cells[100]; const char *buf; int len, rv; const struct fdt_property *p; p = fdt_get_property(fdtp, nodeoff, propname, NULL); if (p != NULL) { if (mode == 1) { /* Adding inexistant value in mode 1 is forbidden */ sprintf(command_errbuf, "property already exists!"); return (CMD_ERROR); } } else if (mode == 0) { sprintf(command_errbuf, "property does not exist!"); return (CMD_ERROR); } len = strlen(value); rv = 0; buf = value; switch (*buf) { case '&': /* phandles */ break; case '<': /* Data cells */ len = fdt_strtovect(buf, (void *)&cells, 100, sizeof(uint32_t)); rv = fdt_setprop(fdtp, nodeoff, propname, &cells, len * sizeof(uint32_t)); break; case '[': /* Data bytes */ len = fdt_strtovect(buf, (void *)&cells, 100, sizeof(uint8_t)); rv = fdt_setprop(fdtp, nodeoff, propname, &cells, len * sizeof(uint8_t)); break; case '"': default: /* Default -- string */ rv = fdt_setprop_string(fdtp, nodeoff, propname, value); break; } if (rv != 0) { if (rv == -FDT_ERR_NOSPACE) sprintf(command_errbuf, "Device tree blob is too small!\n"); else sprintf(command_errbuf, "Could not add/modify property!\n"); } return (rv); } /* Merge strings from argv into a single string */ static int fdt_merge_strings(int argc, char *argv[], int start, char **buffer) { char *buf; int i, idx, sz; *buffer = NULL; sz = 0; for (i = start; i < argc; i++) sz += strlen(argv[i]); /* Additional bytes for whitespaces between args */ sz += argc - start; buf = (char *)malloc(sizeof(char) * sz); if (buf == NULL) { sprintf(command_errbuf, "could not allocate space " "for string"); return (1); } bzero(buf, sizeof(char) * sz); idx = 0; for (i = start, idx = 0; i < argc; i++) { strcpy(buf + idx, argv[i]); idx += strlen(argv[i]); buf[idx] = ' '; idx++; } buf[sz - 1] = '\0'; *buffer = buf; return (0); } /* Extract offset and name of node/property from a given path */ static int fdt_extract_nameloc(char **pathp, char **namep, int *nodeoff) { int o; char *path = *pathp, *name = NULL, *subpath = NULL; subpath = strrchr(path, '/'); if (subpath == NULL) { o = fdt_path_offset(fdtp, cwd); name = path; path = (char *)&cwd; } else { *subpath = '\0'; if (strlen(path) == 0) path = cwd; name = subpath + 1; o = fdt_path_offset(fdtp, path); } if (strlen(name) == 0) { sprintf(command_errbuf, "name not specified"); return (1); } if (o < 0) { sprintf(command_errbuf, "could not find node: '%s'", path); return (1); } *namep = name; *nodeoff = o; *pathp = path; return (0); } static int fdt_cmd_prop(int argc, char *argv[]) { char *path, *propname, *value; int o, next, depth, rv; uint32_t tag; path = (argc > 2) ? argv[2] : NULL; value = NULL; if (argc > 3) { /* Merge property value strings into one */ if (fdt_merge_strings(argc, argv, 3, &value) != 0) return (CMD_ERROR); } else value = NULL; if (path == NULL) path = cwd; rv = CMD_OK; if (value) { /* If value is specified -- try to modify prop. */ if (fdt_extract_nameloc(&path, &propname, &o) != 0) return (CMD_ERROR); rv = fdt_modprop(o, propname, value, 0); if (rv) return (CMD_ERROR); return (CMD_OK); } /* User wants to display properties */ o = fdt_path_offset(fdtp, path); if (o < 0) { sprintf(command_errbuf, "could not find node: '%s'", path); rv = CMD_ERROR; goto out; } depth = 0; while (depth >= 0) { tag = fdt_next_tag(fdtp, o, &next); switch (tag) { case FDT_NOP: break; case FDT_PROP: if (depth > 1) /* Don't process properties of nested nodes */ break; if (fdt_prop(o) != 0) { sprintf(command_errbuf, "could not process " "property"); rv = CMD_ERROR; goto out; } break; case FDT_BEGIN_NODE: depth++; if (depth > FDT_MAX_DEPTH) { printf("warning: nesting too deep: %d\n", depth); goto out; } break; case FDT_END_NODE: depth--; if (depth == 0) /* * This is the end of our starting node, force * the loop finish. */ depth--; break; } o = next; } out: return (rv); } static int fdt_cmd_mkprop(int argc, char *argv[]) { int o; char *path, *propname, *value; path = (argc > 2) ? argv[2] : NULL; value = NULL; if (argc > 3) { /* Merge property value strings into one */ if (fdt_merge_strings(argc, argv, 3, &value) != 0) return (CMD_ERROR); } else value = NULL; if (fdt_extract_nameloc(&path, &propname, &o) != 0) return (CMD_ERROR); if (fdt_modprop(o, propname, value, 1)) return (CMD_ERROR); return (CMD_OK); } static int fdt_cmd_rm(int argc, char *argv[]) { int o, rv; char *path = NULL, *propname; if (argc > 2) path = argv[2]; else { sprintf(command_errbuf, "no node/property name specified"); return (CMD_ERROR); } o = fdt_path_offset(fdtp, path); if (o < 0) { /* If node not found -- try to find & delete property */ if (fdt_extract_nameloc(&path, &propname, &o) != 0) return (CMD_ERROR); if ((rv = fdt_delprop(fdtp, o, propname)) != 0) { sprintf(command_errbuf, "could not delete" "%s\n", (rv == -FDT_ERR_NOTFOUND) ? "(property/node does not exist)" : ""); return (CMD_ERROR); } else return (CMD_OK); } /* If node exists -- remove node */ rv = fdt_del_node(fdtp, o); if (rv) { sprintf(command_errbuf, "could not delete node"); return (CMD_ERROR); } return (CMD_OK); } static int fdt_cmd_mknode(int argc, char *argv[]) { int o, rv; char *path = NULL, *nodename = NULL; if (argc > 2) path = argv[2]; else { sprintf(command_errbuf, "no node name specified"); return (CMD_ERROR); } if (fdt_extract_nameloc(&path, &nodename, &o) != 0) return (CMD_ERROR); rv = fdt_add_subnode(fdtp, o, nodename); if (rv < 0) { if (rv == -FDT_ERR_NOSPACE) sprintf(command_errbuf, "Device tree blob is too small!\n"); else sprintf(command_errbuf, "Could not add node!\n"); return (CMD_ERROR); } return (CMD_OK); } static int fdt_cmd_pwd(int argc, char *argv[]) { char line[FDT_CWD_LEN]; pager_open(); sprintf(line, "%s\n", cwd); pager_output(line); pager_close(); return (CMD_OK); } static int fdt_cmd_mres(int argc, char *argv[]) { uint64_t start, size; int i, total; char line[80]; pager_open(); total = fdt_num_mem_rsv(fdtp); if (total > 0) { pager_output("Reserved memory regions:\n"); for (i = 0; i < total; i++) { fdt_get_mem_rsv(fdtp, i, &start, &size); sprintf(line, "reg#%d: (start: 0x%jx, size: 0x%jx)\n", i, start, size); pager_output(line); } } else pager_output("No reserved memory regions\n"); pager_close(); return (CMD_OK); } static int fdt_cmd_nyi(int argc, char *argv[]) { printf("command not yet implemented\n"); return (CMD_ERROR); } Index: head/sys/boot/i386/libfirewire/dconsole.c =================================================================== --- head/sys/boot/i386/libfirewire/dconsole.c (revision 298825) +++ head/sys/boot/i386/libfirewire/dconsole.c (revision 298826) @@ -1,127 +1,127 @@ /*- * Copyright (c) 2004 Hidetoshi Shimokawa * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include void fw_enable(void); void fw_poll(void); static void dconsole_probe(struct console *cp); static int dconsole_init(int arg); static void dconsole_putchar(int c); static int dconsole_getchar(void); static int dconsole_ischar(void); static int dcons_started = 0; #define DCONS_BUF_SIZE (64*1024) static struct dcons_softc sc[DCONS_NPORT]; uint32_t dcons_paddr; /* The buffer must be allocated in BSS becase: * - The dcons driver in the kernel is initialized before VM/pmap is * initialized, so that the buffer must be allocate in the region * that is mapped at the very early boot state. * - We expect identiy map only for regions before KERNLOAD * (i386:4MB amd64:1MB). - * - It seems that heap in conventional memory(640KB) is not sufficent + * - It seems that heap in conventional memory(640KB) is not sufficient * and we move it to high address as LOADER_SUPPORT_BZIP2. * - BSS is placed in conventional memory. */ static char dcons_buffer[DCONS_BUF_SIZE + PAGE_SIZE]; struct console dconsole = { "dcons", "dumb console port", 0, dconsole_probe, dconsole_init, dconsole_putchar, dconsole_getchar, dconsole_ischar }; #define DCONSOLE_AS_MULTI_CONSOLE 1 static void dconsole_probe(struct console *cp) { /* XXX check the BIOS equipment list? */ cp->c_flags |= (C_PRESENTIN | C_PRESENTOUT); #if DCONSOLE_AS_MULTI_CONSOLE dconsole_init(0); cp->c_flags |= (C_ACTIVEIN | C_ACTIVEOUT); #endif } static int dconsole_init(int arg) { char buf[16], *dbuf; int size; if (dcons_started && arg == 0) return 0; dcons_started = 1; size = DCONS_BUF_SIZE; dbuf = (char *)round_page((vm_offset_t)&dcons_buffer[0]); dcons_paddr = VTOP(dbuf); sprintf(buf, "0x%08x", dcons_paddr); setenv("dcons.addr", buf, 1); dcons_init((struct dcons_buf *)dbuf, size, sc); sprintf(buf, "%d", size); setenv("dcons.size", buf, 1); fw_enable(); return(0); } static void dconsole_putchar(int c) { dcons_putc(&sc[0], c); } static int dconsole_getchar(void) { fw_poll(); return (dcons_checkc(&sc[0])); } static int dconsole_ischar(void) { fw_poll(); return (dcons_ischar(&sc[0])); } Index: head/sys/boot/i386/libfirewire/fwohci.c =================================================================== --- head/sys/boot/i386/libfirewire/fwohci.c (revision 298825) +++ head/sys/boot/i386/libfirewire/fwohci.c (revision 298826) @@ -1,479 +1,479 @@ /* * Copyright (c) 2003 Hidetoshi Shimokawa * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the acknowledgement as bellow: * * This product includes software developed by K. Kobayashi and H. Shimokawa * * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ * */ #include #include #include #include "fwohci.h" #include "fwohcireg.h" #include static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); int firewire_debug=0; #if 0 #define device_printf(a, x, ...) printf("FW1394: " x, ## __VA_ARGS__) #else #define device_printf(a, x, ...) #endif #define device_t int #define DELAY(x) delay(x) #define MAX_SPEED 3 #define MAXREC(x) (2 << (x)) char *linkspeed[] = { "S100", "S200", "S400", "S800", "S1600", "S3200", "undef", "undef" }; #define FW_EUI64_BYTE(eui, x) \ ((((x)<4)? \ ((eui)->hi >> (8*(3-(x)))): \ ((eui)->lo >> (8*(7-(x)))) \ ) & 0xff) /* * Communication with PHY device */ static uint32_t fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) { uint32_t fun; addr &= 0xf; data &= 0xff; fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); OWRITE(sc, OHCI_PHYACCESS, fun); DELAY(100); return(fwphy_rddata( sc, addr)); } static uint32_t fwphy_rddata(struct fwohci_softc *sc, u_int addr) { uint32_t fun, stat; u_int i, retry = 0; addr &= 0xf; #define MAX_RETRY 100 again: OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); OWRITE(sc, OHCI_PHYACCESS, fun); for ( i = 0 ; i < MAX_RETRY ; i ++ ){ fun = OREAD(sc, OHCI_PHYACCESS); if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) break; DELAY(100); } if(i >= MAX_RETRY) { if (firewire_debug) device_printf(sc->fc.dev, "phy read failed(1).\n"); if (++retry < MAX_RETRY) { DELAY(100); goto again; } } /* Make sure that SCLK is started */ stat = OREAD(sc, FWOHCI_INTSTAT); if ((stat & OHCI_INT_REG_FAIL) != 0 || ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { if (firewire_debug) device_printf(sc->fc.dev, "phy read failed(2).\n"); if (++retry < MAX_RETRY) { DELAY(100); goto again; } } if (firewire_debug || retry >= MAX_RETRY) device_printf(sc->fc.dev, "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); #undef MAX_RETRY return((fun >> PHYDEV_RDDATA )& 0xff); } static int fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) { uint32_t reg, reg2; int e1394a = 1; int nport, speed; /* * probe PHY parameters * 0. to prove PHY version, whether compliance of 1394a. * 1. to probe maximum speed supported by the PHY and * number of port supported by core-logic. * It is not actually available port on your PC . */ OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); DELAY(500); reg = fwphy_rddata(sc, FW_PHY_SPD_REG); if((reg >> 5) != 7 ){ nport = reg & FW_PHY_NP; speed = reg & FW_PHY_SPD >> 6; if (speed > MAX_SPEED) { device_printf(dev, "invalid speed %d (fixed to %d).\n", speed, MAX_SPEED); speed = MAX_SPEED; } device_printf(dev, "Phy 1394 only %s, %d ports.\n", linkspeed[speed], nport); }else{ reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); nport = reg & FW_PHY_NP; speed = (reg2 & FW_PHY_ESPD) >> 5; if (speed > MAX_SPEED) { device_printf(dev, "invalid speed %d (fixed to %d).\n", speed, MAX_SPEED); speed = MAX_SPEED; } device_printf(dev, "Phy 1394a available %s, %d ports.\n", linkspeed[speed], nport); /* check programPhyEnable */ reg2 = fwphy_rddata(sc, 5); #if 0 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { #else /* XXX force to enable 1394a */ if (e1394a) { #endif if (firewire_debug) device_printf(dev, "Enable 1394a Enhancements\n"); /* enable EAA EMC */ reg2 |= 0x03; /* set aPhyEnhanceEnable */ OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); } else { /* for safe */ reg2 &= ~0x83; } reg2 = fwphy_wrdata(sc, 5, reg2); } sc->speed = speed; reg = fwphy_rddata(sc, FW_PHY_SPD_REG); if((reg >> 5) == 7 ){ reg = fwphy_rddata(sc, 4); reg |= 1 << 6; fwphy_wrdata(sc, 4, reg); reg = fwphy_rddata(sc, 4); } return 0; } void fwohci_reset(struct fwohci_softc *sc, device_t dev) { int i, max_rec, speed; uint32_t reg, reg2; /* Disable interrupts */ OWRITE(sc, FWOHCI_INTMASKCLR, ~0); - /* FLUSH FIFO and reset Transmitter/Reciever */ + /* FLUSH FIFO and reset Transmitter/Receiver */ OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); if (firewire_debug) device_printf(dev, "resetting OHCI..."); i = 0; while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { if (i++ > 100) break; DELAY(1000); } if (firewire_debug) printf("done (loop=%d)\n", i); /* Probe phy */ fwohci_probe_phy(sc, dev); /* Probe link */ reg = OREAD(sc, OHCI_BUS_OPT); reg2 = reg | OHCI_BUSFNC; max_rec = (reg & 0x0000f000) >> 12; speed = (reg & 0x00000007); device_printf(dev, "Link %s, max_rec %d bytes.\n", linkspeed[speed], MAXREC(max_rec)); /* XXX fix max_rec */ sc->maxrec = sc->speed + 8; if (max_rec != sc->maxrec) { reg2 = (reg2 & 0xffff0fff) | (sc->maxrec << 12); device_printf(dev, "max_rec %d -> %d\n", MAXREC(max_rec), MAXREC(sc->maxrec)); } if (firewire_debug) device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); OWRITE(sc, OHCI_BUS_OPT, reg2); /* Initialize registers */ OWRITE(sc, OHCI_CROMHDR, sc->config_rom[0]); OWRITE(sc, OHCI_CROMPTR, VTOP(sc->config_rom)); #if 0 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); #endif OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); #if 0 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); #endif /* Enable link */ OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); } int fwohci_init(struct fwohci_softc *sc, device_t dev) { int i, mver; uint32_t reg; uint8_t ui[8]; /* OHCI version */ reg = OREAD(sc, OHCI_VERSION); mver = (reg >> 16) & 0xff; device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", mver, reg & 0xff, (reg>>24) & 1); if (mver < 1 || mver > 9) { device_printf(dev, "invalid OHCI version\n"); return (ENXIO); } /* Available Isochronous DMA channel probe */ OWRITE(sc, OHCI_IT_MASK, 0xffffffff); OWRITE(sc, OHCI_IR_MASK, 0xffffffff); reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); for (i = 0; i < 0x20; i++) if ((reg & (1 << i)) == 0) break; device_printf(dev, "No. of Isochronous channels is %d.\n", i); if (i == 0) return (ENXIO); #if 0 -/* SID recieve buffer must align 2^11 */ +/* SID receive buffer must align 2^11 */ #define OHCI_SIDSIZE (1 << 11) sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, &sc->sid_dma, BUS_DMA_WAITOK); if (sc->sid_buf == NULL) { device_printf(dev, "sid_buf alloc failed."); return ENOMEM; } #endif sc->eui.hi = OREAD(sc, FWOHCIGUID_H); sc->eui.lo = OREAD(sc, FWOHCIGUID_L); for( i = 0 ; i < 8 ; i ++) ui[i] = FW_EUI64_BYTE(&sc->eui,i); device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); fwohci_reset(sc, dev); return 0; } void fwohci_ibr(struct fwohci_softc *sc) { uint32_t fun; device_printf(sc->dev, "Initiate bus reset\n"); /* * Make sure our cached values from the config rom are * initialised. */ OWRITE(sc, OHCI_CROMHDR, ntohl(sc->config_rom[0])); OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->config_rom[2])); /* * Set root hold-off bit so that non cyclemaster capable node * shouldn't became the root node. */ #if 1 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); fun |= FW_PHY_IBR; fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); #else /* Short bus reset */ fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); fun |= FW_PHY_ISBR; fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); #endif } void fwohci_sid(struct fwohci_softc *sc) { uint32_t node_id; int plen; node_id = OREAD(sc, FWOHCI_NODEID); if (!(node_id & OHCI_NODE_VALID)) { #if 0 printf("Bus reset failure\n"); #endif return; } /* Enable bus reset interrupt */ OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); /* Allow async. request to us */ OWRITE(sc, OHCI_AREQHI, 1 << 31); /* XXX insecure ?? */ OWRITE(sc, OHCI_PREQHI, 0x7fffffff); OWRITE(sc, OHCI_PREQLO, 0xffffffff); OWRITE(sc, OHCI_PREQUPPER, 0x10000); /* Set ATRetries register */ OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); /* ** Checking whether the node is root or not. If root, turn on ** cycle master. */ plen = OREAD(sc, OHCI_SID_CNT); device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", node_id, (plen >> 16) & 0xff); if (node_id & OHCI_NODE_ROOT) { device_printf(sc->dev, "CYCLEMASTER mode\n"); OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); } else { device_printf(sc->dev, "non CYCLEMASTER mode\n"); OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); } if (plen & OHCI_SID_ERR) { device_printf(fc->dev, "SID Error\n"); return; } device_printf(sc->dev, "bus reset phase done\n"); sc->state = FWOHCI_STATE_NORMAL; } static void fwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count) { #undef OHCI_DEBUG #ifdef OHCI_DEBUG #if 0 if(stat & OREAD(sc, FWOHCI_INTMASK)) #else if (1) #endif device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", stat & OHCI_INT_EN ? "DMA_EN ":"", stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", stat & OHCI_INT_ERR ? "INT_ERR ":"", stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", stat & OHCI_INT_CYC_START ? "CYC_START ":"", stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", stat & OHCI_INT_PHY_SID ? "SID ":"", stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", stat, OREAD(sc, FWOHCI_INTMASK) ); #endif /* Bus reset */ if(stat & OHCI_INT_PHY_BUS_R ){ device_printf(fc->dev, "BUS reset\n"); if (sc->state == FWOHCI_STATE_BUSRESET) goto busresetout; sc->state = FWOHCI_STATE_BUSRESET; /* Disable bus reset interrupt until sid recv. */ OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); OWRITE(sc, OHCI_CROMHDR, ntohl(sc->config_rom[0])); OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->config_rom[2])); } else if (sc->state == FWOHCI_STATE_BUSRESET) { fwohci_sid(sc); } busresetout: return; } static uint32_t fwochi_check_stat(struct fwohci_softc *sc) { uint32_t stat; stat = OREAD(sc, FWOHCI_INTSTAT); if (stat == 0xffffffff) { device_printf(sc->fc.dev, "device physically ejected?\n"); return(stat); } if (stat) OWRITE(sc, FWOHCI_INTSTATCLR, stat); return(stat); } void fwohci_poll(struct fwohci_softc *sc) { uint32_t stat; stat = fwochi_check_stat(sc); if (stat != 0xffffffff) fwohci_intr_body(sc, stat, 1); } Index: head/sys/boot/i386/libi386/amd64_tramp.S =================================================================== --- head/sys/boot/i386/libi386/amd64_tramp.S (revision 298825) +++ head/sys/boot/i386/libi386/amd64_tramp.S (revision 298826) @@ -1,113 +1,113 @@ /*- * Copyright (c) 2003 Peter Wemm * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* * Quick and dirty trampoline to get into 64 bit (long) mode and running * with paging enabled so that we enter the kernel at its linked address. */ #define MSR_EFER 0xc0000080 #define EFER_LME 0x00000100 #define CR4_PAE 0x00000020 #define CR4_PSE 0x00000010 #define CR0_PG 0x80000000 /* GRRR. Deal with BTX that links us for a non-zero location */ #define VPBASE 0xa000 #define VTOP(x) ((x) + VPBASE) .data .p2align 12,0x40 .globl PT4 PT4: .space 0x1000 .globl PT3 PT3: .space 0x1000 .globl PT2 PT2: .space 0x1000 gdtdesc: .word gdtend - gdt .long VTOP(gdt) # low .long 0 # high gdt: .long 0 # null descriptor .long 0 .long 0x00000000 # %cs .long 0x00209800 .long 0x00000000 # %ds .long 0x00008000 gdtend: .text .code32 .globl amd64_tramp amd64_tramp: /* Be sure that interrupts are disabled */ cli /* Turn on EFER.LME */ movl $MSR_EFER, %ecx rdmsr orl $EFER_LME, %eax wrmsr /* Turn on PAE */ movl %cr4, %eax orl $CR4_PAE, %eax movl %eax, %cr4 /* Set %cr3 for PT4 */ movl $VTOP(PT4), %eax movl %eax, %cr3 /* Turn on paging (implicitly sets EFER.LMA) */ movl %cr0, %eax orl $CR0_PG, %eax movl %eax, %cr0 - /* Now we're in compatability mode. set %cs for long mode */ + /* Now we're in compatibility mode. set %cs for long mode */ movl $VTOP(gdtdesc), %eax movl VTOP(entry_hi), %esi movl VTOP(entry_lo), %edi lgdt (%eax) ljmp $0x8, $VTOP(longmode) .code64 longmode: /* We're still running V=P, jump to entry point */ movl %esi, %eax salq $32, %rax orq %rdi, %rax pushq %rax ret Index: head/sys/boot/i386/libi386/pxe.h =================================================================== --- head/sys/boot/i386/libi386/pxe.h (revision 298825) +++ head/sys/boot/i386/libi386/pxe.h (revision 298826) @@ -1,513 +1,513 @@ /* * Copyright (c) 2000 Alfred Perlstein * All rights reserved. * Copyright (c) 2000 Paul Saab * All rights reserved. * Copyright (c) 2000 John Baldwin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* * The typedefs and structures declared in this file * clearly violate style(9), the reason for this is to conform to the * typedefs/structure-names used in the Intel literature to avoid confusion. * * It's for your own good. :) */ /* It seems that intel didn't think about ABI, * either that or 16bit ABI != 32bit ABI (which seems reasonable) * I have to thank Intel for the hair loss I incurred trying to figure * out why PXE was mis-reading structures I was passing it (at least * from my point of view) * * Solution: use gcc's '__packed' to correctly align * structures passed into PXE * Question: does this really work for PXE's expected ABI? */ #define PACKED __packed #define S_SIZE(s) s, sizeof(s) - 1 #define PXENFSROOTPATH "/pxeroot" typedef struct { uint16_t offset; uint16_t segment; } SEGOFF16_t; typedef struct { uint16_t Seg_Addr; uint32_t Phy_Addr; uint16_t Seg_Size; } SEGDESC_t; typedef uint16_t SEGSEL_t; typedef uint16_t PXENV_STATUS_t; typedef uint32_t IP4_t; typedef uint32_t ADDR32_t; typedef uint16_t UDP_PORT_t; #define MAC_ADDR_LEN 16 typedef uint8_t MAC_ADDR[MAC_ADDR_LEN]; /* PXENV+ */ typedef struct { uint8_t Signature[6]; /* 'PXENV+' */ uint16_t Version; /* MSB = major, LSB = minor */ uint8_t Length; /* structure length */ uint8_t Checksum; /* checksum pad */ SEGOFF16_t RMEntry; /* SEG:OFF to PXE entry point */ /* don't use PMOffset and PMSelector (from the 2.1 PXE manual) */ uint32_t PMOffset; /* Protected mode entry */ SEGSEL_t PMSelector; /* Protected mode selector */ SEGSEL_t StackSeg; /* Stack segment address */ uint16_t StackSize; /* Stack segment size (bytes) */ SEGSEL_t BC_CodeSeg; /* BC Code segment address */ uint16_t BC_CodeSize; /* BC Code segment size (bytes) */ SEGSEL_t BC_DataSeg; /* BC Data segment address */ uint16_t BC_DataSize; /* BC Data segment size (bytes) */ SEGSEL_t UNDIDataSeg; /* UNDI Data segment address */ uint16_t UNDIDataSize; /* UNDI Data segment size (bytes) */ SEGSEL_t UNDICodeSeg; /* UNDI Code segment address */ uint16_t UNDICodeSize; /* UNDI Code segment size (bytes) */ SEGOFF16_t PXEPtr; /* SEG:OFF to !PXE struct, only present when Version > 2.1 */ } PACKED pxenv_t; /* !PXE */ typedef struct { uint8_t Signature[4]; uint8_t StructLength; uint8_t StructCksum; uint8_t StructRev; uint8_t reserved_1; SEGOFF16_t UNDIROMID; SEGOFF16_t BaseROMID; SEGOFF16_t EntryPointSP; SEGOFF16_t EntryPointESP; SEGOFF16_t StatusCallout; uint8_t reserved_2; uint8_t SegDescCn; SEGSEL_t FirstSelector; SEGDESC_t Stack; SEGDESC_t UNDIData; SEGDESC_t UNDICode; SEGDESC_t UNDICodeWrite; SEGDESC_t BC_Data; SEGDESC_t BC_Code; SEGDESC_t BC_CodeWrite; } PACKED pxe_t; #define PXENV_START_UNDI 0x0000 typedef struct { PXENV_STATUS_t Status; uint16_t ax; uint16_t bx; uint16_t dx; uint16_t di; uint16_t es; } PACKED t_PXENV_START_UNDI; #define PXENV_UNDI_STARTUP 0x0001 typedef struct { PXENV_STATUS_t Status; } PACKED t_PXENV_UNDI_STARTUP; #define PXENV_UNDI_CLEANUP 0x0002 typedef struct { PXENV_STATUS_t Status; } PACKED t_PXENV_UNDI_CLEANUP; #define PXENV_UNDI_INITIALIZE 0x0003 typedef struct { PXENV_STATUS_t Status; ADDR32_t ProtocolIni; /* Phys addr of a copy of the driver module */ uint8_t reserved[8]; } PACKED t_PXENV_UNDI_INITALIZE; #define MAXNUM_MCADDR 8 typedef struct { PXENV_STATUS_t Status; uint16_t MCastAddrCount; MAC_ADDR McastAddr[MAXNUM_MCADDR]; } PACKED t_PXENV_UNDI_MCAST_ADDRESS; #define PXENV_UNDI_RESET_ADAPTER 0x0004 typedef struct { PXENV_STATUS_t Status; t_PXENV_UNDI_MCAST_ADDRESS R_Mcast_Buf; } PACKED t_PXENV_UNDI_RESET; #define PXENV_UNDI_SHUTDOWN 0x0005 typedef struct { PXENV_STATUS_t Status; } PACKED t_PXENV_UNDI_SHUTDOWN; #define PXENV_UNDI_OPEN 0x0006 typedef struct { PXENV_STATUS_t Status; uint16_t OpenFlag; uint16_t PktFilter; # define FLTR_DIRECTED 0x0001 # define FLTR_BRDCST 0x0002 # define FLTR_PRMSCS 0x0003 # define FLTR_SRC_RTG 0x0004 t_PXENV_UNDI_MCAST_ADDRESS R_Mcast_Buf; } PACKED t_PXENV_UNDI_OPEN; #define PXENV_UNDI_CLOSE 0x0007 typedef struct { PXENV_STATUS_t Status; } PACKED t_PXENV_UNDI_CLOSE; #define PXENV_UNDI_TRANSMIT 0x0008 typedef struct { PXENV_STATUS_t Status; uint8_t Protocol; # define P_UNKNOWN 0 # define P_IP 1 # define P_ARP 2 # define P_RARP 3 uint8_t XmitFlag; # define XMT_DESTADDR 0x0000 # define XMT_BROADCAST 0x0001 SEGOFF16_t DestAddr; SEGOFF16_t TBD; uint32_t Reserved[2]; } PACKED t_PXENV_UNDI_TRANSMIT; #define MAX_DATA_BLKS 8 typedef struct { uint16_t ImmedLength; SEGOFF16_t Xmit; uint16_t DataBlkCount; struct DataBlk { uint8_t TDPtrType; uint8_t TDRsvdByte; uint16_t TDDataLen; SEGOFF16_t TDDataPtr; } DataBlock[MAX_DATA_BLKS]; } PACKED t_PXENV_UNDI_TBD; #define PXENV_UNDI_SET_MCAST_ADDRESS 0x0009 typedef struct { PXENV_STATUS_t Status; t_PXENV_UNDI_MCAST_ADDRESS R_Mcast_Buf; } PACKED t_PXENV_UNDI_SET_MCAST_ADDR; #define PXENV_UNDI_SET_STATION_ADDRESS 0x000A typedef struct { PXENV_STATUS_t Status; - MAC_ADDR StationAddress; /* Temp MAC addres to use */ + MAC_ADDR StationAddress; /* Temp MAC address to use */ } PACKED t_PXENV_UNDI_SET_STATION_ADDR; #define PXENV_UNDI_SET_PACKET_FILTER 0x000B typedef struct { PXENV_STATUS_t Status; uint8_t filter; /* see UNDI_OPEN (0x0006) */ } PACKED t_PXENV_UNDI_SET_PACKET_FILTER; #define PXENV_UNDI_GET_INFORMATION 0x000C typedef struct { PXENV_STATUS_t Status; uint16_t BaseIo; /* Adapter base I/O address */ uint16_t IntNumber; /* Adapter IRQ number */ uint16_t MaxTranUnit; /* Adapter maximum transmit unit */ uint16_t HwType; /* Type of protocol at the hardware addr */ # define ETHER_TYPE 1 # define EXP_ETHER_TYPE 2 # define IEEE_TYPE 6 # define ARCNET_TYPE 7 uint16_t HwAddrLen; /* Length of hardware address */ MAC_ADDR CurrentNodeAddress; /* Current hardware address */ MAC_ADDR PermNodeAddress; /* Permanent hardware address */ SEGSEL_t ROMAddress; /* Real mode ROM segment address */ uint16_t RxBufCt; /* Receive queue length */ uint16_t TxBufCt; /* Transmit queue length */ } PACKED t_PXENV_UNDI_GET_INFORMATION; #define PXENV_UNDI_GET_STATISTICS 0x000D typedef struct { PXENV_STATUS_t Status; uint32_t XmitGoodFrames; /* Number of successful transmissions */ uint32_t RcvGoodFrames; /* Number of good frames received */ uint32_t RcvCRCErrors; /* Number of frames with CRC errors */ uint32_t RcvResourceErrors; /* Number of frames dropped */ } PACKED t_PXENV_UNDI_GET_STATISTICS; #define PXENV_UNDI_CLEAR_STATISTICS 0x000E typedef struct { PXENV_STATUS_t Status; } PACKED t_PXENV_UNDI_CLEAR_STATISTICS; #define PXENV_UNDI_INITIATE_DIAGS 0x000F typedef struct { PXENV_STATUS_t Status; } PACKED t_PXENV_UNDI_INITIATE_DIAGS; #define PXENV_UNDI_FORCE_INTERRUPT 0x0010 typedef struct { PXENV_STATUS_t Status; } PACKED t_PXENV_UNDI_FORCE_INTERRUPT; #define PXENV_UNDI_GET_MCAST_ADDRESS 0x0011 typedef struct { PXENV_STATUS_t Status; IP4_t InetAddr; /* IP mulicast address */ MAC_ADDR MediaAddr; /* MAC multicast address */ } PACKED t_PXENV_UNDI_GET_MCAST_ADDR; #define PXENV_UNDI_GET_NIC_TYPE 0x0012 typedef struct { PXENV_STATUS_t Status; uint8_t NicType; /* Type of NIC */ # define PCI_NIC 2 # define PnP_NIC 3 # define CardBus_NIC 4 union { struct { uint16_t Vendor_ID; uint16_t Dev_ID; uint8_t Base_Class; uint8_t Sub_Class; uint8_t Prog_Intf; uint8_t Rev; uint16_t BusDevFunc; uint16_t SubVendor_ID; uint16_t SubDevice_ID; } pci, cardbus; struct { uint32_t EISA_Dev_ID; uint8_t Base_Class; uint8_t Sub_Class; uint8_t Prog_Intf; uint16_t CardSelNum; } pnp; } info; } PACKED t_PXENV_UNDI_GET_NIC_TYPE; #define PXENV_UNDI_GET_IFACE_INFO 0x0013 typedef struct { PXENV_STATUS_t Status; uint8_t IfaceType[16]; /* Name of MAC type in ASCII. */ uint32_t LinkSpeed; /* Defined in NDIS 2.0 spec */ uint32_t ServiceFlags; /* Defined in NDIS 2.0 spec */ uint32_t Reserved[4]; /* must be 0 */ } PACKED t_PXENV_UNDI_GET_NDIS_INFO; #define PXENV_UNDI_ISR 0x0014 typedef struct { PXENV_STATUS_t Status; uint16_t FuncFlag; /* PXENV_UNDI_ISR_OUT_xxx */ uint16_t BufferLength; /* Length of Frame */ - uint16_t FrameLength; /* Total length of reciever frame */ + uint16_t FrameLength; /* Total length of receiver frame */ uint16_t FrameHeaderLength; /* Length of the media header in Frame */ SEGOFF16_t Frame; /* receive buffer */ uint8_t ProtType; /* Protocol type */ uint8_t PktType; /* Packet Type */ # define PXENV_UNDI_ISR_IN_START 1 # define PXENV_UNDI_ISR_IN_PROCESS 2 # define PXENV_UNDI_ISR_IN_GET_NEXT 3 /* one of these will be returned for PXENV_UNDI_ISR_IN_START */ # define PXENV_UNDI_ISR_OUT_OURS 0 # define PXENV_UNDI_ISR_OUT_NOT_OUTS 1 /* - * one of these will bre returnd for PXEND_UNDI_ISR_IN_PROCESS + * one of these will bre returned for PXEND_UNDI_ISR_IN_PROCESS * and PXENV_UNDI_ISR_IN_GET_NEXT */ # define PXENV_UNDI_ISR_OUT_DONE 0 # define PXENV_UNDI_ISR_OUT_TRANSMIT 2 # define PXENV_UNDI_ISR_OUT_RECIEVE 3 # define PXENV_UNDI_ISR_OUT_BUSY 4 } PACKED t_PXENV_UNDI_ISR; #define PXENV_STOP_UNDI 0x0015 typedef struct { PXENV_STATUS_t Status; } PACKED t_PXENV_STOP_UNDI; #define PXENV_TFTP_OPEN 0x0020 typedef struct { PXENV_STATUS_t Status; IP4_t ServerIPAddress; IP4_t GatewayIPAddress; uint8_t FileName[128]; UDP_PORT_t TFTPPort; uint16_t PacketSize; } PACKED t_PXENV_TFTP_OPEN; #define PXENV_TFTP_CLOSE 0x0021 typedef struct { PXENV_STATUS_t Status; } PACKED t_PXENV_TFTP_CLOSE; #define PXENV_TFTP_READ 0x0022 typedef struct { PXENV_STATUS_t Status; uint16_t PacketNumber; uint16_t BufferSize; SEGOFF16_t Buffer; } PACKED t_PXENV_TFTP_READ; #define PXENV_TFTP_READ_FILE 0x0023 typedef struct { PXENV_STATUS_t Status; uint8_t FileName[128]; uint32_t BufferSize; ADDR32_t Buffer; IP4_t ServerIPAddress; IP4_t GatewayIPAdress; IP4_t McastIPAdress; UDP_PORT_t TFTPClntPort; UDP_PORT_t TFTPSrvPort; uint16_t TFTPOpenTimeOut; uint16_t TFTPReopenDelay; } PACKED t_PXENV_TFTP_READ_FILE; #define PXENV_TFTP_GET_FSIZE 0x0025 typedef struct { PXENV_STATUS_t Status; IP4_t ServerIPAddress; IP4_t GatewayIPAdress; uint8_t FileName[128]; uint32_t FileSize; } PACKED t_PXENV_TFTP_GET_FSIZE; #define PXENV_UDP_OPEN 0x0030 typedef struct { PXENV_STATUS_t status; IP4_t src_ip; /* IP address of this station */ } PACKED t_PXENV_UDP_OPEN; #define PXENV_UDP_CLOSE 0x0031 typedef struct { PXENV_STATUS_t status; } PACKED t_PXENV_UDP_CLOSE; #define PXENV_UDP_READ 0x0032 typedef struct { PXENV_STATUS_t status; IP4_t src_ip; /* IP of sender */ IP4_t dest_ip; /* Only accept packets sent to this IP */ UDP_PORT_t s_port; /* UDP source port of sender */ UDP_PORT_t d_port; /* Only accept packets sent to this port */ uint16_t buffer_size; /* Size of the packet buffer */ SEGOFF16_t buffer; /* SEG:OFF to the packet buffer */ } PACKED t_PXENV_UDP_READ; #define PXENV_UDP_WRITE 0x0033 typedef struct { PXENV_STATUS_t status; IP4_t ip; /* dest ip addr */ IP4_t gw; /* ip gateway */ UDP_PORT_t src_port; /* source udp port */ UDP_PORT_t dst_port; /* destination udp port */ uint16_t buffer_size; /* Size of the packet buffer */ SEGOFF16_t buffer; /* SEG:OFF to the packet buffer */ } PACKED t_PXENV_UDP_WRITE; #define PXENV_UNLOAD_STACK 0x0070 typedef struct { PXENV_STATUS_t Status; uint8_t reserved[10]; } PACKED t_PXENV_UNLOAD_STACK; #define PXENV_GET_CACHED_INFO 0x0071 typedef struct { PXENV_STATUS_t Status; uint16_t PacketType; /* type (defined right here) */ # define PXENV_PACKET_TYPE_DHCP_DISCOVER 1 # define PXENV_PACKET_TYPE_DHCP_ACK 2 # define PXENV_PACKET_TYPE_BINL_REPLY 3 uint16_t BufferSize; /* max to copy, leave at 0 for pointer */ SEGOFF16_t Buffer; /* copy to, leave at 0 for pointer */ uint16_t BufferLimit; /* max size of buffer in BC dataseg ? */ } PACKED t_PXENV_GET_CACHED_INFO; /* structure filled in by PXENV_GET_CACHED_INFO * (how we determine which IP we downloaded the initial bootstrap from) * words can't describe... */ typedef struct { uint8_t opcode; # define BOOTP_REQ 1 # define BOOTP_REP 2 uint8_t Hardware; /* hardware type */ uint8_t Hardlen; /* hardware addr len */ uint8_t Gatehops; /* zero it */ uint32_t ident; /* random number chosen by client */ uint16_t seconds; /* seconds since did initial bootstrap */ uint16_t Flags; /* seconds since did initial bootstrap */ # define BOOTP_BCAST 0x8000 /* ? */ IP4_t cip; /* Client IP */ IP4_t yip; /* Your IP */ IP4_t sip; /* IP to use for next boot stage */ IP4_t gip; /* Relay IP ? */ MAC_ADDR CAddr; /* Client hardware address */ uint8_t Sname[64]; /* Server's hostname (Optional) */ uint8_t bootfile[128]; /* boot filename */ union { # if 1 # define BOOTP_DHCPVEND 1024 /* DHCP extended vendor field size */ # else # define BOOTP_DHCPVEND 312 /* DHCP standard vendor field size */ # endif uint8_t d[BOOTP_DHCPVEND]; /* raw array of vendor/dhcp options */ struct { uint8_t magic[4]; /* DHCP magic cookie */ # ifndef VM_RFC1048 # define VM_RFC1048 0x63825363L /* ? */ # endif uint32_t flags; /* bootp flags/opcodes */ uint8_t pad[56]; /* I don't think intel knows what a union does... */ } v; } vendor; } PACKED BOOTPLAYER; #define PXENV_RESTART_TFTP 0x0073 #define t_PXENV_RESTART_TFTP t_PXENV_TFTP_READ_FILE #define PXENV_START_BASE 0x0075 typedef struct { PXENV_STATUS_t Status; } PACKED t_PXENV_START_BASE; #define PXENV_STOP_BASE 0x0076 typedef struct { PXENV_STATUS_t Status; } PACKED t_PXENV_STOP_BASE; Index: head/sys/boot/i386/zfsboot/zfsboot.c =================================================================== --- head/sys/boot/i386/zfsboot/zfsboot.c (revision 298825) +++ head/sys/boot/i386/zfsboot/zfsboot.c (revision 298826) @@ -1,950 +1,950 @@ /*- * Copyright (c) 1998 Robert Nordier * All rights reserved. * * Redistribution and use in source and binary forms are freely * permitted provided that the above copyright notice and this * paragraph and the following disclaimer are duplicated in all * such forms. * * This software is provided "AS IS" and without any express or * implied warranties, including, without limitation, the implied * warranties of merchantability and fitness for a particular * purpose. */ #include __FBSDID("$FreeBSD$"); #include #include #include #ifdef GPT #include #endif #include #include #include #include #include #include #include #include #include #include "lib.h" #include "rbx.h" #include "drv.h" #include "util.h" #include "cons.h" #include "bootargs.h" #include "paths.h" #include "libzfs.h" #define ARGS 0x900 #define NOPT 14 #define NDEV 3 #define BIOS_NUMDRIVES 0x475 #define DRV_HARD 0x80 #define DRV_MASK 0x7f #define TYPE_AD 0 #define TYPE_DA 1 #define TYPE_MAXHARD TYPE_DA #define TYPE_FD 2 #define DEV_GELIBOOT_BSIZE 4096 extern uint32_t _end; #ifdef GPT static const uuid_t freebsd_zfs_uuid = GPT_ENT_TYPE_FREEBSD_ZFS; #endif static const char optstr[NOPT] = "DhaCcdgmnpqrsv"; /* Also 'P', 'S' */ static const unsigned char flags[NOPT] = { RBX_DUAL, RBX_SERIAL, RBX_ASKNAME, RBX_CDROM, RBX_CONFIG, RBX_KDB, RBX_GDB, RBX_MUTE, RBX_NOINTR, RBX_PAUSE, RBX_QUIET, RBX_DFLTROOT, RBX_SINGLE, RBX_VERBOSE }; uint32_t opts; static const char *const dev_nm[NDEV] = {"ad", "da", "fd"}; static const unsigned char dev_maj[NDEV] = {30, 4, 2}; static char cmd[512]; static char cmddup[512]; static char kname[1024]; static char rootname[256]; static int comspeed = SIOSPD; static struct bootinfo bootinfo; static uint32_t bootdev; static struct zfs_boot_args zfsargs; static struct zfsmount zfsmount; vm_offset_t high_heap_base; uint32_t bios_basemem, bios_extmem, high_heap_size; static struct bios_smap smap; /* * The minimum amount of memory to reserve in bios_extmem for the heap. */ #define HEAP_MIN (3 * 1024 * 1024) static char *heap_next; static char *heap_end; /* Buffers that must not span a 64k boundary. */ #define READ_BUF_SIZE 8192 struct dmadat { char rdbuf[READ_BUF_SIZE]; /* for reading large things */ char secbuf[READ_BUF_SIZE]; /* for MBR/disklabel */ }; static struct dmadat *dmadat; void exit(int); static void load(void); static int parse(void); static void bios_getmem(void); void *malloc(size_t n); void free(void *ptr); void * malloc(size_t n) { char *p = heap_next; if (p + n > heap_end) { printf("malloc failure\n"); for (;;) ; /* NOTREACHED */ return (0); } heap_next += n; return (p); } void free(void *ptr) { return; } static char * strdup(const char *s) { char *p = malloc(strlen(s) + 1); strcpy(p, s); return (p); } #ifdef LOADER_GELI_SUPPORT #include "geliboot.c" static char gelipw[GELI_PW_MAXLEN]; #endif #include "zfsimpl.c" /* * Read from a dnode (which must be from a ZPL filesystem). */ static int zfs_read(spa_t *spa, const dnode_phys_t *dnode, off_t *offp, void *start, size_t size) { const znode_phys_t *zp = (const znode_phys_t *) dnode->dn_bonus; size_t n; int rc; n = size; if (*offp + n > zp->zp_size) n = zp->zp_size - *offp; rc = dnode_read(spa, dnode, *offp, start, n); if (rc) return (-1); *offp += n; return (n); } /* * Current ZFS pool */ static spa_t *spa; static spa_t *primary_spa; static vdev_t *primary_vdev; /* * A wrapper for dskread that doesn't have to worry about whether the * buffer pointer crosses a 64k boundary. */ static int vdev_read(vdev_t *vdev, void *priv, off_t off, void *buf, size_t bytes) { char *p; daddr_t lba, alignlba; off_t alignoff, diff; unsigned int nb, alignnb; struct dsk *dsk = (struct dsk *) priv; if ((off & (DEV_BSIZE - 1)) || (bytes & (DEV_BSIZE - 1))) return -1; p = buf; lba = off / DEV_BSIZE; lba += dsk->start; /* Align reads to 4k else 4k sector GELIs will not decrypt. */ alignoff = off & ~ (off_t)(DEV_GELIBOOT_BSIZE - 1); /* Round LBA down to nearest multiple of DEV_GELIBOOT_BSIZE bytes. */ alignlba = alignoff / DEV_BSIZE; /* * The read must be aligned to DEV_GELIBOOT_BSIZE bytes relative to the * start of the GELI partition, not the start of the actual disk. */ alignlba += dsk->start; diff = (lba - alignlba) * DEV_BSIZE; while (bytes > 0) { nb = bytes / DEV_BSIZE; if (nb > READ_BUF_SIZE / DEV_BSIZE) nb = READ_BUF_SIZE / DEV_BSIZE; /* * Ensure that the read size plus the leading offset does not * exceed the size of the read buffer. */ if (nb * DEV_BSIZE + diff > READ_BUF_SIZE) nb -= diff / DEV_BSIZE; /* * Round the number of blocks to read up to the nearest multiple * of DEV_GELIBOOT_BSIZE. */ alignnb = nb + (diff / DEV_BSIZE) + (DEV_GELIBOOT_BSIZE / DEV_BSIZE - 1) & ~ (unsigned int)(DEV_GELIBOOT_BSIZE / DEV_BSIZE - 1); if (drvread(dsk, dmadat->rdbuf, alignlba, alignnb)) return -1; #ifdef LOADER_GELI_SUPPORT /* decrypt */ if (is_geli(dsk) == 0) { if (geli_read(dsk, ((alignlba - dsk->start) * DEV_BSIZE), dmadat->rdbuf, alignnb * DEV_BSIZE)) return (-1); } #endif memcpy(p, dmadat->rdbuf + diff, nb * DEV_BSIZE); p += nb * DEV_BSIZE; lba += nb; alignlba += alignnb; bytes -= nb * DEV_BSIZE; /* Don't need the leading offset after the first block. */ diff = 0; } return 0; } static int xfsread(const dnode_phys_t *dnode, off_t *offp, void *buf, size_t nbyte) { if ((size_t)zfs_read(spa, dnode, offp, buf, nbyte) != nbyte) { printf("Invalid format\n"); return -1; } return 0; } static void bios_getmem(void) { uint64_t size; /* Parse system memory map */ v86.ebx = 0; do { v86.ctl = V86_FLAGS; v86.addr = 0x15; /* int 0x15 function 0xe820*/ v86.eax = 0xe820; v86.ecx = sizeof(struct bios_smap); v86.edx = SMAP_SIG; v86.es = VTOPSEG(&smap); v86.edi = VTOPOFF(&smap); v86int(); if (V86_CY(v86.efl) || (v86.eax != SMAP_SIG)) break; /* look for a low-memory segment that's large enough */ if ((smap.type == SMAP_TYPE_MEMORY) && (smap.base == 0) && (smap.length >= (512 * 1024))) bios_basemem = smap.length; /* look for the first segment in 'extended' memory */ if ((smap.type == SMAP_TYPE_MEMORY) && (smap.base == 0x100000)) { bios_extmem = smap.length; } /* * Look for the largest segment in 'extended' memory beyond * 1MB but below 4GB. */ if ((smap.type == SMAP_TYPE_MEMORY) && (smap.base > 0x100000) && (smap.base < 0x100000000ull)) { size = smap.length; /* * If this segment crosses the 4GB boundary, truncate it. */ if (smap.base + size > 0x100000000ull) size = 0x100000000ull - smap.base; if (size > high_heap_size) { high_heap_size = size; high_heap_base = smap.base; } } } while (v86.ebx != 0); /* Fall back to the old compatibility function for base memory */ if (bios_basemem == 0) { v86.ctl = 0; v86.addr = 0x12; /* int 0x12 */ v86int(); bios_basemem = (v86.eax & 0xffff) * 1024; } /* Fall back through several compatibility functions for extended memory */ if (bios_extmem == 0) { v86.ctl = V86_FLAGS; v86.addr = 0x15; /* int 0x15 function 0xe801*/ v86.eax = 0xe801; v86int(); if (!V86_CY(v86.efl)) { bios_extmem = ((v86.ecx & 0xffff) + ((v86.edx & 0xffff) * 64)) * 1024; } } if (bios_extmem == 0) { v86.ctl = 0; v86.addr = 0x15; /* int 0x15 function 0x88*/ v86.eax = 0x8800; v86int(); bios_extmem = (v86.eax & 0xffff) * 1024; } /* * If we have extended memory and did not find a suitable heap * region in the SMAP, use the last 3MB of 'extended' memory as a * high heap candidate. */ if (bios_extmem >= HEAP_MIN && high_heap_size < HEAP_MIN) { high_heap_size = HEAP_MIN; high_heap_base = bios_extmem + 0x100000 - HEAP_MIN; } } /* * Try to detect a device supported by the legacy int13 BIOS */ static int int13probe(int drive) { v86.ctl = V86_FLAGS; v86.addr = 0x13; v86.eax = 0x800; v86.edx = drive; v86int(); if (!V86_CY(v86.efl) && /* carry clear */ ((v86.edx & 0xff) != (drive & DRV_MASK))) { /* unit # OK */ if ((v86.ecx & 0x3f) == 0) { /* absurd sector size */ return(0); /* skip device */ } return (1); } return(0); } /* * We call this when we find a ZFS vdev - ZFS consumes the dsk * structure so we must make a new one. */ static struct dsk * copy_dsk(struct dsk *dsk) { struct dsk *newdsk; newdsk = malloc(sizeof(struct dsk)); *newdsk = *dsk; return (newdsk); } static void probe_drive(struct dsk *dsk) { #ifdef GPT struct gpt_hdr hdr; struct gpt_ent *ent; unsigned part, entries_per_sec; #endif daddr_t slba, elba; struct dos_partition *dp; char *sec; unsigned i; /* * If we find a vdev on the whole disk, stop here. */ if (vdev_probe(vdev_read, dsk, NULL) == 0) return; #ifdef LOADER_GELI_SUPPORT /* * Taste the disk, if it is GELI encrypted, decrypt it and check to see if * it is a usable vdev then. Otherwise dig * out the partition table and probe each slice/partition * in turn for a vdev or GELI encrypted vdev. */ elba = drvsize(dsk); if (elba > 0) { elba--; } if (geli_taste(vdev_read, dsk, elba) == 0) { if (geli_passphrase(&gelipw, dsk->unit, ':', 0, dsk) == 0) { if (vdev_probe(vdev_read, dsk, NULL) == 0) { return; } } } #endif /* LOADER_GELI_SUPPORT */ sec = dmadat->secbuf; dsk->start = 0; #ifdef GPT /* * First check for GPT. */ if (drvread(dsk, sec, 1, 1)) { return; } memcpy(&hdr, sec, sizeof(hdr)); if (memcmp(hdr.hdr_sig, GPT_HDR_SIG, sizeof(hdr.hdr_sig)) != 0 || hdr.hdr_lba_self != 1 || hdr.hdr_revision < 0x00010000 || hdr.hdr_entsz < sizeof(*ent) || DEV_BSIZE % hdr.hdr_entsz != 0) { goto trymbr; } /* - * Probe all GPT partitions for the presense of ZFS pools. We + * Probe all GPT partitions for the presence of ZFS pools. We * return the spa_t for the first we find (if requested). This * will have the effect of booting from the first pool on the * disk. * * If no vdev is found, GELI decrypting the device and try again */ entries_per_sec = DEV_BSIZE / hdr.hdr_entsz; slba = hdr.hdr_lba_table; elba = slba + hdr.hdr_entries / entries_per_sec; while (slba < elba) { dsk->start = 0; if (drvread(dsk, sec, slba, 1)) return; for (part = 0; part < entries_per_sec; part++) { ent = (struct gpt_ent *)(sec + part * hdr.hdr_entsz); if (memcmp(&ent->ent_type, &freebsd_zfs_uuid, sizeof(uuid_t)) == 0) { dsk->start = ent->ent_lba_start; dsk->slice = part + 1; dsk->part = 255; if (vdev_probe(vdev_read, dsk, NULL) == 0) { /* * This slice had a vdev. We need a new dsk * structure now since the vdev now owns this one. */ dsk = copy_dsk(dsk); } #ifdef LOADER_GELI_SUPPORT else if (geli_taste(vdev_read, dsk, ent->ent_lba_end - ent->ent_lba_start) == 0) { if (geli_passphrase(&gelipw, dsk->unit, 'p', dsk->slice, dsk) == 0) { /* * This slice has GELI, check it for ZFS. */ if (vdev_probe(vdev_read, dsk, NULL) == 0) { /* * This slice had a vdev. We need a new dsk * structure now since the vdev now owns this one. */ dsk = copy_dsk(dsk); } break; } } #endif /* LOADER_GELI_SUPPORT */ } } slba++; } return; trymbr: #endif /* GPT */ if (drvread(dsk, sec, DOSBBSECTOR, 1)) return; dp = (void *)(sec + DOSPARTOFF); for (i = 0; i < NDOSPART; i++) { if (!dp[i].dp_typ) continue; dsk->start = dp[i].dp_start; dsk->slice = i + 1; if (vdev_probe(vdev_read, dsk, NULL) == 0) { dsk = copy_dsk(dsk); } #ifdef LOADER_GELI_SUPPORT else if (geli_taste(vdev_read, dsk, dp[i].dp_size - dp[i].dp_start) == 0) { if (geli_passphrase(&gelipw, dsk->unit, 's', i, dsk) == 0) { /* * This slice has GELI, check it for ZFS. */ if (vdev_probe(vdev_read, dsk, NULL) == 0) { /* * This slice had a vdev. We need a new dsk * structure now since the vdev now owns this one. */ dsk = copy_dsk(dsk); } break; } } #endif /* LOADER_GELI_SUPPORT */ } } int main(void) { int autoboot, i; dnode_phys_t dn; off_t off; struct dsk *dsk; dmadat = (void *)(roundup2(__base + (int32_t)&_end, 0x10000) - __base); bios_getmem(); if (high_heap_size > 0) { heap_end = PTOV(high_heap_base + high_heap_size); heap_next = PTOV(high_heap_base); } else { heap_next = (char *)dmadat + sizeof(*dmadat); heap_end = (char *)PTOV(bios_basemem); } dsk = malloc(sizeof(struct dsk)); dsk->drive = *(uint8_t *)PTOV(ARGS); dsk->type = dsk->drive & DRV_HARD ? TYPE_AD : TYPE_FD; dsk->unit = dsk->drive & DRV_MASK; dsk->slice = *(uint8_t *)PTOV(ARGS + 1) + 1; dsk->part = 0; dsk->start = 0; dsk->init = 0; bootinfo.bi_version = BOOTINFO_VERSION; bootinfo.bi_size = sizeof(bootinfo); bootinfo.bi_basemem = bios_basemem / 1024; bootinfo.bi_extmem = bios_extmem / 1024; bootinfo.bi_memsizes_valid++; bootinfo.bi_bios_dev = dsk->drive; bootdev = MAKEBOOTDEV(dev_maj[dsk->type], dsk->slice, dsk->unit, dsk->part), /* Process configuration file */ autoboot = 1; #ifdef LOADER_GELI_SUPPORT geli_init(); #endif zfs_init(); /* * Probe the boot drive first - we will try to boot from whatever * pool we find on that drive. */ probe_drive(dsk); /* * Probe the rest of the drives that the bios knows about. This * will find any other available pools and it may fill in missing * vdevs for the boot pool. */ #ifndef VIRTUALBOX for (i = 0; i < *(unsigned char *)PTOV(BIOS_NUMDRIVES); i++) #else for (i = 0; i < MAXBDDEV; i++) #endif { if ((i | DRV_HARD) == *(uint8_t *)PTOV(ARGS)) continue; if (!int13probe(i | DRV_HARD)) break; dsk = malloc(sizeof(struct dsk)); dsk->drive = i | DRV_HARD; dsk->type = dsk->drive & TYPE_AD; dsk->unit = i; dsk->slice = 0; dsk->part = 0; dsk->start = 0; dsk->init = 0; probe_drive(dsk); } /* * The first discovered pool, if any, is the pool. */ spa = spa_get_primary(); if (!spa) { printf("%s: No ZFS pools located, can't boot\n", BOOTPROG); for (;;) ; } primary_spa = spa; primary_vdev = spa_get_primary_vdev(spa); if (zfs_spa_init(spa) != 0 || zfs_mount(spa, 0, &zfsmount) != 0) { printf("%s: failed to mount default pool %s\n", BOOTPROG, spa->spa_name); autoboot = 0; } else if (zfs_lookup(&zfsmount, PATH_CONFIG, &dn) == 0 || zfs_lookup(&zfsmount, PATH_DOTCONFIG, &dn) == 0) { off = 0; zfs_read(spa, &dn, &off, cmd, sizeof(cmd)); } if (*cmd) { /* * Note that parse() is destructive to cmd[] and we also want * to honor RBX_QUIET option that could be present in cmd[]. */ memcpy(cmddup, cmd, sizeof(cmd)); if (parse()) autoboot = 0; if (!OPT_CHECK(RBX_QUIET)) printf("%s: %s\n", PATH_CONFIG, cmddup); /* Do not process this command twice */ *cmd = 0; } /* * Try to exec /boot/loader. If interrupted by a keypress, * or in case of failure, try to load a kernel directly instead. */ if (autoboot && !*kname) { memcpy(kname, PATH_LOADER_ZFS, sizeof(PATH_LOADER_ZFS)); if (!keyhit(3)) { load(); memcpy(kname, PATH_KERNEL, sizeof(PATH_KERNEL)); } } /* Present the user with the boot2 prompt. */ for (;;) { if (!autoboot || !OPT_CHECK(RBX_QUIET)) { printf("\nFreeBSD/x86 boot\n"); if (zfs_rlookup(spa, zfsmount.rootobj, rootname) != 0) printf("Default: %s/<0x%llx>:%s\n" "boot: ", spa->spa_name, zfsmount.rootobj, kname); else if (rootname[0] != '\0') printf("Default: %s/%s:%s\n" "boot: ", spa->spa_name, rootname, kname); else printf("Default: %s:%s\n" "boot: ", spa->spa_name, kname); } if (ioctrl & IO_SERIAL) sio_flush(); if (!autoboot || keyhit(5)) getstr(cmd, sizeof(cmd)); else if (!autoboot || !OPT_CHECK(RBX_QUIET)) putchar('\n'); autoboot = 0; if (parse()) putchar('\a'); else load(); } } /* XXX - Needed for btxld to link the boot2 binary; do not remove. */ void exit(int x) { } static void load(void) { union { struct exec ex; Elf32_Ehdr eh; } hdr; static Elf32_Phdr ep[2]; static Elf32_Shdr es[2]; caddr_t p; dnode_phys_t dn; off_t off; uint32_t addr, x; int fmt, i, j; if (zfs_lookup(&zfsmount, kname, &dn)) { printf("\nCan't find %s\n", kname); return; } off = 0; if (xfsread(&dn, &off, &hdr, sizeof(hdr))) return; if (N_GETMAGIC(hdr.ex) == ZMAGIC) fmt = 0; else if (IS_ELF(hdr.eh)) fmt = 1; else { printf("Invalid %s\n", "format"); return; } if (fmt == 0) { addr = hdr.ex.a_entry & 0xffffff; p = PTOV(addr); off = PAGE_SIZE; if (xfsread(&dn, &off, p, hdr.ex.a_text)) return; p += roundup2(hdr.ex.a_text, PAGE_SIZE); if (xfsread(&dn, &off, p, hdr.ex.a_data)) return; p += hdr.ex.a_data + roundup2(hdr.ex.a_bss, PAGE_SIZE); bootinfo.bi_symtab = VTOP(p); memcpy(p, &hdr.ex.a_syms, sizeof(hdr.ex.a_syms)); p += sizeof(hdr.ex.a_syms); if (hdr.ex.a_syms) { if (xfsread(&dn, &off, p, hdr.ex.a_syms)) return; p += hdr.ex.a_syms; if (xfsread(&dn, &off, p, sizeof(int))) return; x = *(uint32_t *)p; p += sizeof(int); x -= sizeof(int); if (xfsread(&dn, &off, p, x)) return; p += x; } } else { off = hdr.eh.e_phoff; for (j = i = 0; i < hdr.eh.e_phnum && j < 2; i++) { if (xfsread(&dn, &off, ep + j, sizeof(ep[0]))) return; if (ep[j].p_type == PT_LOAD) j++; } for (i = 0; i < 2; i++) { p = PTOV(ep[i].p_paddr & 0xffffff); off = ep[i].p_offset; if (xfsread(&dn, &off, p, ep[i].p_filesz)) return; } p += roundup2(ep[1].p_memsz, PAGE_SIZE); bootinfo.bi_symtab = VTOP(p); if (hdr.eh.e_shnum == hdr.eh.e_shstrndx + 3) { off = hdr.eh.e_shoff + sizeof(es[0]) * (hdr.eh.e_shstrndx + 1); if (xfsread(&dn, &off, &es, sizeof(es))) return; for (i = 0; i < 2; i++) { memcpy(p, &es[i].sh_size, sizeof(es[i].sh_size)); p += sizeof(es[i].sh_size); off = es[i].sh_offset; if (xfsread(&dn, &off, p, es[i].sh_size)) return; p += es[i].sh_size; } } addr = hdr.eh.e_entry & 0xffffff; } bootinfo.bi_esymtab = VTOP(p); bootinfo.bi_kernelname = VTOP(kname); zfsargs.size = sizeof(zfsargs); zfsargs.pool = zfsmount.spa->spa_guid; zfsargs.root = zfsmount.rootobj; zfsargs.primary_pool = primary_spa->spa_guid; #ifdef LOADER_GELI_SUPPORT bcopy(gelipw, zfsargs.gelipw, sizeof(zfsargs.gelipw)); bzero(gelipw, sizeof(gelipw)); #else zfsargs.gelipw[0] = '\0'; #endif if (primary_vdev != NULL) zfsargs.primary_vdev = primary_vdev->v_guid; else printf("failed to detect primary vdev\n"); __exec((caddr_t)addr, RB_BOOTINFO | (opts & RBX_MASK), bootdev, KARGS_FLAGS_ZFS | KARGS_FLAGS_EXTARG, (uint32_t) spa->spa_guid, (uint32_t) (spa->spa_guid >> 32), VTOP(&bootinfo), zfsargs); } static int zfs_mount_ds(char *dsname) { uint64_t newroot; spa_t *newspa; char *q; q = strchr(dsname, '/'); if (q) *q++ = '\0'; newspa = spa_find_by_name(dsname); if (newspa == NULL) { printf("\nCan't find ZFS pool %s\n", dsname); return -1; } if (zfs_spa_init(newspa)) return -1; newroot = 0; if (q) { if (zfs_lookup_dataset(newspa, q, &newroot)) { printf("\nCan't find dataset %s in ZFS pool %s\n", q, newspa->spa_name); return -1; } } if (zfs_mount(newspa, newroot, &zfsmount)) { printf("\nCan't mount ZFS dataset\n"); return -1; } spa = newspa; return (0); } static int parse(void) { char *arg = cmd; char *ep, *p, *q; const char *cp; int c, i, j; while ((c = *arg++)) { if (c == ' ' || c == '\t' || c == '\n') continue; for (p = arg; *p && *p != '\n' && *p != ' ' && *p != '\t'; p++); ep = p; if (*p) *p++ = 0; if (c == '-') { while ((c = *arg++)) { if (c == 'P') { if (*(uint8_t *)PTOV(0x496) & 0x10) { cp = "yes"; } else { opts |= OPT_SET(RBX_DUAL) | OPT_SET(RBX_SERIAL); cp = "no"; } printf("Keyboard: %s\n", cp); continue; } else if (c == 'S') { j = 0; while ((unsigned int)(i = *arg++ - '0') <= 9) j = j * 10 + i; if (j > 0 && i == -'0') { comspeed = j; break; } /* Fall through to error below ('S' not in optstr[]). */ } for (i = 0; c != optstr[i]; i++) if (i == NOPT - 1) return -1; opts ^= OPT_SET(flags[i]); } ioctrl = OPT_CHECK(RBX_DUAL) ? (IO_SERIAL|IO_KEYBOARD) : OPT_CHECK(RBX_SERIAL) ? IO_SERIAL : IO_KEYBOARD; if (ioctrl & IO_SERIAL) { if (sio_init(115200 / comspeed) != 0) ioctrl &= ~IO_SERIAL; } } if (c == '?') { dnode_phys_t dn; if (zfs_lookup(&zfsmount, arg, &dn) == 0) { zap_list(spa, &dn); } return -1; } else { arg--; /* * Report pool status if the comment is 'status'. Lets * hope no-one wants to load /status as a kernel. */ if (!strcmp(arg, "status")) { spa_all_status(); return -1; } /* * If there is "zfs:" prefix simply ignore it. */ if (strncmp(arg, "zfs:", 4) == 0) arg += 4; /* * If there is a colon, switch pools. */ q = strchr(arg, ':'); if (q) { *q++ = '\0'; if (zfs_mount_ds(arg) != 0) return -1; arg = q; } if ((i = ep - arg)) { if ((size_t)i >= sizeof(kname)) return -1; memcpy(kname, arg, i + 1); } } arg = p; } return 0; } Index: head/sys/boot/ofw/common/main.c =================================================================== --- head/sys/boot/ofw/common/main.c (revision 298825) +++ head/sys/boot/ofw/common/main.c (revision 298826) @@ -1,190 +1,190 @@ /*- * Copyright (c) 2000 Benno Rice * Copyright (c) 2000 Stephane Potvin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include "openfirm.h" #include "libofw.h" #include "bootstrap.h" struct arch_switch archsw; /* MI/MD interface boundary */ extern char end[]; extern char bootprog_name[]; extern char bootprog_rev[]; extern char bootprog_date[]; extern char bootprog_maker[]; u_int32_t acells, scells; static char bootargs[128]; #define HEAP_SIZE 0x100000 #define OF_puts(fd, text) OF_write(fd, text, strlen(text)) void init_heap(void) { void *base; ihandle_t stdout; if ((base = ofw_alloc_heap(HEAP_SIZE)) == (void *)0xffffffff) { OF_getprop(chosen, "stdout", &stdout, sizeof(stdout)); OF_puts(stdout, "Heap memory claim failed!\n"); OF_enter(); } setheap(base, (void *)((int)base + HEAP_SIZE)); } uint64_t memsize(void) { phandle_t memoryp; cell_t reg[24]; int i, sz; u_int64_t memsz; memsz = 0; memoryp = OF_instance_to_package(memory); sz = OF_getprop(memoryp, "reg", ®, sizeof(reg)); sz /= sizeof(reg[0]); for (i = 0; i < sz; i += (acells + scells)) { if (scells > 1) memsz += (uint64_t)reg[i + acells] << 32; memsz += reg[i + acells + scells - 1]; } return (memsz); } int main(int (*openfirm)(void *)) { phandle_t root; int i; char bootpath[64]; char *ch; int bargc; char **bargv; /* - * Initalise the Open Firmware routines by giving them the entry point. + * Initialise the Open Firmware routines by giving them the entry point. */ OF_init(openfirm); root = OF_finddevice("/"); scells = acells = 1; OF_getprop(root, "#address-cells", &acells, sizeof(acells)); OF_getprop(root, "#size-cells", &scells, sizeof(scells)); /* * Initialise the heap as early as possible. Once this is done, * alloc() is usable. The stack is buried inside us, so this is * safe. */ init_heap(); /* * Set up console. */ cons_probe(); /* * March through the device switch probing for things. */ for (i = 0; devsw[i] != NULL; i++) if (devsw[i]->dv_init != NULL) (devsw[i]->dv_init)(); printf("\n"); printf("%s, Revision %s\n", bootprog_name, bootprog_rev); printf("(%s, %s)\n", bootprog_maker, bootprog_date); printf("Memory: %lldKB\n", memsize() / 1024); OF_getprop(chosen, "bootpath", bootpath, 64); ch = strchr(bootpath, ':'); *ch = '\0'; printf("Booted from: %s\n", bootpath); printf("\n"); /* * Only parse the first bootarg if present. It should * be simple to handle extra arguments */ OF_getprop(chosen, "bootargs", bootargs, sizeof(bootargs)); bargc = 0; parse(&bargc, &bargv, bootargs); if (bargc == 1) env_setenv("currdev", EV_VOLATILE, bargv[0], ofw_setcurrdev, env_nounset); else env_setenv("currdev", EV_VOLATILE, bootpath, ofw_setcurrdev, env_nounset); env_setenv("loaddev", EV_VOLATILE, bootpath, env_noset, env_nounset); setenv("LINES", "24", 1); /* optional */ archsw.arch_getdev = ofw_getdev; archsw.arch_copyin = ofw_copyin; archsw.arch_copyout = ofw_copyout; archsw.arch_readin = ofw_readin; archsw.arch_autoload = ofw_autoload; interact(NULL); /* doesn't return */ OF_exit(); return 0; } COMMAND_SET(halt, "halt", "halt the system", command_halt); static int command_halt(int argc, char *argv[]) { OF_exit(); return (CMD_OK); } COMMAND_SET(memmap, "memmap", "print memory map", command_memmap); int command_memmap(int argc, char **argv) { ofw_memmap(acells); return (CMD_OK); } Index: head/sys/boot/pc98/boot0.5/disk.s =================================================================== --- head/sys/boot/pc98/boot0.5/disk.s (revision 298825) +++ head/sys/boot/pc98/boot0.5/disk.s (revision 298826) @@ -1,296 +1,296 @@ # Copyright (c) KATO Takenori, 1999, 2000. # # All rights reserved. Unpublished rights reserved under the copyright # laws of Japan. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions # are met: # # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer as # the first lines of this file unmodified. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # $FreeBSD$ # .code16 .text # # Check magic number at the end of the sector 0 # check_magic: movw curdevice, %si shlw %si movw secsize(%si), %bx decw %bx decw %bx movw iplbuf(%bx), %ax cmpw $0xaa55, %ax je magic_ok movw $1, %ax ret magic_ok: xorw %ax, %ax ret # # Copy partition table from buffer to parttable. # setup_partition: push %cs pop %es movw curdevice, %bx shlw %bx movw maxpart(%bx), %cx # %cx = max num of partitions movw partoff(%bx), %di movw %di, %bx # %bx = offset to partition table xorw %dx, %dx # %dx = partition number setup_partition_loop: push %cx movw %dx, %si movb $5, %cl shlw %cl, %si addw %bx, %si movb iplbuf(%si), %al orb %al, %al jz unused_partition addw $iplbuf, %si movw npartition, %ax movw %ax, %di movb $5, %cl shlw %cl, %di addw $parttable, %di movw $32, %cx rep movsb movw %ax, %di addw $partnum, %di movb %dl, (%di) incw npartition unused_partition: incw %dx pop %cx loop setup_partition_loop ret # # Read IPL and partition table in the current device. # .global read_ipl read_ipl: movw curdevice, %ax movw %ax, %si # %si = device number movw %ax, %di shlw %di movw %cs, %ax movw %ax, %es movb $6, %ah movb daua(%si), %al movw $0x400, %bx xorw %cx, %cx xorw %dx, %dx movw $iplbuf, %bp int $0x1b jc read_ipl_error movw defflagoff(%di), %bx movb iplbuf(%bx), %al movb %al, defpartflag incw %bx movb iplbuf(%bx), %al movb %al, defpartnum movw $0, npartition call check_magic orw %ax, %ax jnz no_magic call setup_partition no_magic: xorw %ax, %ax read_ipl_error: xorw %bx, %bx movw %bx, %es ret # # Restore IPL from the buffer # .global write_ipl write_ipl: movw curdevice, %ax movw %ax, %si movw %ax, %di shlw %di # Restore default boot partition info. movw defflagoff(%di), %bx movb defpartflag, %al movb %al, iplbuf(%bx) incw %bx movb defpartnum, %al movb %al, iplbuf(%bx) movw %cs, %ax movw %ax, %es movb $5, %ah movb daua(%si), %al movw secsize(%di), %bx xorw %cx, %cx xorw %dx, %dx movw $iplbuf, %bp int $0x1b jc write_ipl_error xorw %ax, %ax write_ipl_error: xorw %bx, %bx movw %bx, %es ret # # Scan HDD devices # .global scan_sasi, scan_scsi # Scan SASI disk scan_sasi: # SASI Disk movw $4, %cx movw $0x0001, %ax # %ah = unit number, %al = for bit operation sasi_loop: movw %si, %di shlw %di movw $0x55d, %bx # DISK_EQUIP call read_biosparam testb %al, %dl jz no_sasi_unit movb $0x80, %dh addb %ah, %dh # %dh = DA/UA movb %dh, daua(%si) # Store DA/UA # Try new sense command push %ax push %cx movb %dh, %al movb $0x84, %ah int $0x1b pop %cx pop %ax jc err_newsense movw %bx, %dx jmp found_sasi_unit err_newsense: movw $0x457, %bx # capacity & sector size of IDE HDD call read_biosparam orb %ah, %ah jz sasi_1 cmpb $1, %ah jz sasi_2 # SASI #3/#4 movw $512, %dx # XXX jmp found_sasi_unit sasi_1: # SASI #1 testb $0x80, %dl jz sasi_256 jmp sasi_512 sasi_2: # SASI #2 testb $0x40, %dl jz sasi_256 jmp sasi_512 sasi_256: movw $256, %dx jmp found_sasi_unit sasi_512: movw $512, %dx found_sasi_unit: movw %dx, secsize(%di) incw %si no_sasi_unit: incb %ah shlb %al loop sasi_loop ret # # Scan SCSI disk # SI number of disks # destroyed: %ax, %bx, %cx, %dx scan_scsi: movw $8, %cx movw $0x0001, %ax # %ah = ID number, %al = for bit operation scsi_loop: # Check whether drive exist. movw %si, %di shlw %di movw $0x482, %bx # DISK_EQUIPS call read_biosparam testb %al, %dl jz no_scsi_unit xorw %bx, %bx movb %ah, %bl shlw %bx shlw %bx - addw $0x460, %bx # SCSI paramter block + addw $0x460, %bx # SCSI parameter block call read_biosparam orb %dl, %dl jz no_scsi_unit # SCSI harddrive found. movb $0xa0, %dh addb %ah, %dh movb %dh, daua(%si) # Check sector size. addw $3, %bx call read_biosparam andb $0x30, %dl cmpb $0x20, %dl je scsi_1024 cmpb $0x10, %dl je scsi_512 movw $256, %dx jmp found_scsi scsi_1024: movw $1024, %dx jmp found_scsi scsi_512: movw $512, %dx found_scsi: movw %dx, secsize(%di) incw %si no_scsi_unit: incb %ah shlb %al loop scsi_loop ret .data .global defpartflag, defpartnum, npartition defpartflag: .byte 0 defpartnum: .byte 0 npartition: .word 0 # number of partitions .bss .global partnum, parttable iplbuf: .space 0x400 # Read buffer for IPL partnum: .space 32 # Index of parttable parttable: .space 1024 # Copy of valid partition table Index: head/sys/boot/pc98/boot0.5/putssjis.s =================================================================== --- head/sys/boot/pc98/boot0.5/putssjis.s (revision 298825) +++ head/sys/boot/pc98/boot0.5/putssjis.s (revision 298826) @@ -1,137 +1,137 @@ # Copyright (c) KATO Takenori, 2007. # # All rights reserved. Unpublished rights reserved under the copyright # laws of Japan. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions # are met: # # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer as # the first lines of this file unmodified. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # $FreeBSD$ # .code16 .section .putssjis, "awx", @progbits # # Display string with Shift-JIS support - # %si: addres of string, %di: T-VRAM address, %cx: count + # %si: address of string, %di: T-VRAM address, %cx: count # # Absolute address of putssjis_entry must be 0x1243. putssjis_entry: push %es push %ax # Setup the T-VRAM segement address. xorw %ax, %ax movw %ax, %es movw $0xa000, %ax testb $0x08, %es:0x501 jz normalmode movw $0xe000, %ax normalmode: movw %ax, %es putssjis_loop: lodsw call check_sjis jc put_2byte_char # 1 byte character xorb %ah, %ah testb $0xe0, %al # Check control code. jnz put_1byte_char movb $0x20, %al # Convert control code into the space. put_1byte_char: stosw decw %si jmp putssjis_loop_end put_2byte_char: subb $0x20, %al # Check 2byte "hankaku" cmp $0x09, %al je put_2byte_hankaku cmp $0x0a, %al je put_2byte_hankaku cmp $0x0b, %al je put_2byte_hankaku jmp put_2byte_zenkaku put_2byte_hankaku: stosw jmp putssjis_loop_end put_2byte_zenkaku: stosw orb $0x80, %ah stosw decw %cx putssjis_loop_end: loop putssjis_loop pop %ax pop %es ret # Check 2-byte code. check_sjis: cmpb $0x80, %al jbe found_ank_kana cmpb $0xa0, %al jb found_2byte_char cmpb $0xe0, %al jb found_ank_kana cmpb $0xf0, %al jae found_ank_kana jmp found_2byte_char found_ank_kana: clc ret found_2byte_char: # Convert Shift-JIS into JIS. cmpb $0x9f, %al ja sjis_h_2 # Upper > 0x9f subb $0x71, %al # Upper -= 0x71 jmp sjis_lower sjis_h_2: subb $0xb1, %al # Upper -= 0xb1 sjis_lower: salb %al # Upper *= 2 incb %al # Upper += 1 cmpb $0x7f, %ah jbe sjis_l_2 decb %ah # Lower -= 1 if lower > 0x7f sjis_l_2: cmpb $0x9e, %ah jb sjis_l_3 subb $0x7d, %ah # Lower -= 0x7d incb %al # Upper += 1 jmp check_2byte_end sjis_l_3: subb $0x1f, %ah # Lower -= 0x1f check_2byte_end: stc ret Index: head/sys/boot/pc98/boot0.5/support.s =================================================================== --- head/sys/boot/pc98/boot0.5/support.s (revision 298825) +++ head/sys/boot/pc98/boot0.5/support.s (revision 298826) @@ -1,94 +1,94 @@ # Copyright (c) KATO Takenori, 1999, 2000. # # All rights reserved. Unpublished rights reserved under the copyright # laws of Japan. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions # are met: # # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer as # the first lines of this file unmodified. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # $FreeBSD$ # .code16 .text # # Wait 1ms # .global wait1ms wait1ms: push %cx movw $800, %cx wait_loop: outb %al, $0x5f loop wait_loop pop %cx ret # # Read one byte from BIOS parameter block # %bx offset # %dl value # .global read_biosparam read_biosparam: movb %es:(%bx), %dl ret # -# Write one byte to BIOS paramter block +# Write one byte to BIOS parameter block # %bx offset # %dl value # .global write_biosparam write_biosparam: movb %dl, %es:(%bx) ret # # beep # .global beep_on, beep_off, beep beep_on: movb $0x17, %ah int $0x18 ret beep_off: movb $0x18, %ah int $0x18 ret beep: push %cx call beep_on movw $100, %cx beep_loop1: call wait1ms loop beep_loop1 call beep_off movw $50, %cx beep_loop2: call wait1ms loop beep_loop2 pop %cx ret Index: head/sys/boot/uboot/fdt/uboot_fdt.c =================================================================== --- head/sys/boot/uboot/fdt/uboot_fdt.c (revision 298825) +++ head/sys/boot/uboot/fdt/uboot_fdt.c (revision 298826) @@ -1,196 +1,196 @@ /*- * Copyright (c) 2009-2010 The FreeBSD Foundation * All rights reserved. * * This software was developed by Semihalf under sponsorship from * the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include "glue.h" #define STR(number) #number #define STRINGIFY(number) STR(number) int fdt_platform_load_dtb(void) { struct fdt_header *hdr; const char *s; char *p; int rv; /* * If the U-boot environment contains a variable giving the address of a * valid blob in memory, use it. The U-boot README says the right * variable for fdt data loaded into ram is fdt_addr_r, so try that * first. Board vendors also use both fdtaddr and fdt_addr names. */ s = ub_env_get("fdt_addr_r"); if (s == NULL) s = ub_env_get("fdtaddr"); if (s == NULL) s = ub_env_get("fdt_addr"); if (s != NULL && *s != '\0') { hdr = (struct fdt_header *)strtoul(s, &p, 16); if (*p == '\0') { if (fdt_load_dtb_addr(hdr) == 0) { printf("Using DTB provided by U-Boot at " "address %p.\n", hdr); return (0); } } } rv = 1; /* * Try to get FDT filename first from loader env and then from u-boot env */ s = getenv("fdt_file"); if (s == NULL) s = ub_env_get("fdtfile"); if (s == NULL) s = ub_env_get("fdt_file"); if (s != NULL && *s != '\0') { if (fdt_load_dtb_file(s) == 0) { printf("Loaded DTB from file '%s'.\n", s); rv = 0; } } if (rv == 0) { s = getenv("fdt_overlays"); if (s == NULL) s = ub_env_get("fdt_overlays"); if (s != NULL && *s != '\0') { printf("Loading DTB overlays: '%s'\n", s); fdt_load_dtb_overlays(s); } } return (rv); } void fdt_platform_fixups(void) { static struct fdt_mem_region regions[UB_MAX_MR]; const char *env, *str; char *end, *ethstr; int eth_no, i, len, n; struct sys_info *si; env = NULL; eth_no = 0; ethstr = NULL; /* Apply overlays before anything else */ fdt_apply_overlays(); /* Acquire sys_info */ si = ub_get_sys_info(); while ((env = ub_env_enum(env)) != NULL) { if (strncmp(env, "eth", 3) == 0 && strncmp(env + (strlen(env) - 4), "addr", 4) == 0) { /* * Handle Ethernet addrs: parse uboot env eth%daddr */ if (!eth_no) { /* * Check how many chars we will need to store * maximal eth iface number. */ len = strlen(STRINGIFY(TMP_MAX_ETH)) + strlen("ethernet") + 1; /* * Reserve mem for string "ethernet" and len * chars for iface no. */ ethstr = (char *)malloc(len * sizeof(char)); bzero(ethstr, len * sizeof(char)); strcpy(ethstr, "ethernet0"); } /* Extract interface number */ i = strtol(env + 3, &end, 10); if (end == (env + 3)) /* 'ethaddr' means interface 0 address */ n = 0; else n = i; if (n > TMP_MAX_ETH) continue; str = ub_env_get(env); if (n != 0) { /* - * Find the lenght of the interface id by + * Find the length of the interface id by * taking in to account the first 3 and * last 4 characters. */ i = strlen(env) - 7; strncpy(ethstr + 8, env + 3, i); } /* Modify blob */ fdt_fixup_ethernet(str, ethstr, len); /* Clear ethernet..XXXX.. string */ bzero(ethstr + 8, len - 8); if (n + 1 > eth_no) eth_no = n + 1; } else if (strcmp(env, "consoledev") == 0) { str = ub_env_get(env); fdt_fixup_stdout(str); } } /* Modify cpu(s) and bus clock frequenties in /cpus node [Hz] */ fdt_fixup_cpubusfreqs(si->clk_cpu, si->clk_bus); /* Extract the DRAM regions into fdt_mem_region format. */ for (i = 0, n = 0; i < si->mr_no && n < nitems(regions); i++) { if (si->mr[i].flags == MR_ATTR_DRAM) { regions[n].start = si->mr[i].start; regions[n].size = si->mr[i].size; n++; } } /* Fixup memory regions */ fdt_fixup_memory(regions, n); }