Index: head/sys/dev/rt/if_rt.c =================================================================== --- head/sys/dev/rt/if_rt.c (revision 298058) +++ head/sys/dev/rt/if_rt.c (revision 298059) @@ -1,2839 +1,2840 @@ /*- * Copyright (c) 2015-2016, Stanislav Galabov * Copyright (c) 2014, Aleksandr A. Mityaev * Copyright (c) 2011, Aleksandr Rybalko * based on hard work * by Alexander Egorenkov * and by Damien Bergamini * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "if_rtvar.h" #include "if_rtreg.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "opt_platform.h" #include "opt_rt305x.h" #ifdef FDT #include #include #include #endif #include #include #if 0 #include #include #endif #ifdef IF_RT_PHY_SUPPORT #include "miibus_if.h" #endif /* * Defines and macros */ #define RT_MAX_AGG_SIZE 3840 #define RT_TX_DATA_SEG0_SIZE MJUMPAGESIZE #define RT_MS(_v, _f) (((_v) & _f) >> _f##_S) #define RT_SM(_v, _f) (((_v) << _f##_S) & _f) #define RT_TX_WATCHDOG_TIMEOUT 5 #define RT_CHIPID_RT3050 0x3050 #define RT_CHIPID_RT5350 0x5350 #define RT_CHIPID_MT7620 0x7620 #define RT_CHIPID_MT7621 0x7621 #ifdef FDT /* more specific and new models should go first */ static const struct ofw_compat_data rt_compat_data[] = { - { "ralink,rt3050-eth", RT_CHIPID_RT3050 }, - { "ralink,rt3352-eth", RT_CHIPID_RT3050 }, - { "ralink,rt3883-eth", RT_CHIPID_RT3050 }, - { "ralink,rt5350-eth", RT_CHIPID_RT5350 }, - { "ralink,mt7620a-eth", RT_CHIPID_MT7620 }, - { "ralink,mt7621-eth", RT_CHIPID_MT7621 }, - { NULL, 0 } + { "ralink,rt3050-eth", RT_CHIPID_RT3050 }, + { "ralink,rt3352-eth", RT_CHIPID_RT3050 }, + { "ralink,rt3883-eth", RT_CHIPID_RT3050 }, + { "ralink,rt5350-eth", RT_CHIPID_RT5350 }, + { "ralink,mt7620a-eth", RT_CHIPID_MT7620 }, + { "ralink,mt7621-eth", RT_CHIPID_MT7621 }, + { "mediatek,mt7621-eth", RT_CHIPID_MT7621 }, + { NULL, 0 } }; #endif /* * Static function prototypes */ static int rt_probe(device_t dev); static int rt_attach(device_t dev); static int rt_detach(device_t dev); static int rt_shutdown(device_t dev); static int rt_suspend(device_t dev); static int rt_resume(device_t dev); static void rt_init_locked(void *priv); static void rt_init(void *priv); static void rt_stop_locked(void *priv); static void rt_stop(void *priv); static void rt_start(struct ifnet *ifp); static int rt_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); static void rt_periodic(void *arg); static void rt_tx_watchdog(void *arg); static void rt_intr(void *arg); static void rt_rt5350_intr(void *arg); static void rt_tx_coherent_intr(struct rt_softc *sc); static void rt_rx_coherent_intr(struct rt_softc *sc); static void rt_rx_delay_intr(struct rt_softc *sc); static void rt_tx_delay_intr(struct rt_softc *sc); static void rt_rx_intr(struct rt_softc *sc, int qid); static void rt_tx_intr(struct rt_softc *sc, int qid); static void rt_rx_done_task(void *context, int pending); static void rt_tx_done_task(void *context, int pending); static void rt_periodic_task(void *context, int pending); static int rt_rx_eof(struct rt_softc *sc, struct rt_softc_rx_ring *ring, int limit); static void rt_tx_eof(struct rt_softc *sc, struct rt_softc_tx_ring *ring); static void rt_update_stats(struct rt_softc *sc); static void rt_watchdog(struct rt_softc *sc); static void rt_update_raw_counters(struct rt_softc *sc); static void rt_intr_enable(struct rt_softc *sc, uint32_t intr_mask); static void rt_intr_disable(struct rt_softc *sc, uint32_t intr_mask); static int rt_txrx_enable(struct rt_softc *sc); static int rt_alloc_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring, int qid); static void rt_reset_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring); static void rt_free_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring); static int rt_alloc_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring, int qid); static void rt_reset_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring); static void rt_free_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring); static void rt_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error); static void rt_sysctl_attach(struct rt_softc *sc); #ifdef IF_RT_PHY_SUPPORT void rt_miibus_statchg(device_t); static int rt_miibus_readreg(device_t, int, int); static int rt_miibus_writereg(device_t, int, int, int); #endif static int rt_ifmedia_upd(struct ifnet *); static void rt_ifmedia_sts(struct ifnet *, struct ifmediareq *); static SYSCTL_NODE(_hw, OID_AUTO, rt, CTLFLAG_RD, 0, "RT driver parameters"); #ifdef IF_RT_DEBUG static int rt_debug = 0; SYSCTL_INT(_hw_rt, OID_AUTO, debug, CTLFLAG_RWTUN, &rt_debug, 0, "RT debug level"); #endif static int rt_probe(device_t dev) { struct rt_softc *sc = device_get_softc(dev); char buf[80]; #ifdef FDT const struct ofw_compat_data * cd; cd = ofw_bus_search_compatible(dev, rt_compat_data); if (cd->ocd_data == 0) return (ENXIO); sc->rt_chipid = (unsigned int)(cd->ocd_data); #else #if defined(MT7620) sc->rt_chipid = RT_CHIPID_MT7620; #elif defined(MT7621) sc->rt_chipid = RT_CHIPID_MT7621; #elif defined(RT5350) sc->rt_chipid = RT_CHIPID_RT5350; #else sc->rt_chipid = RT_CHIPID_RT3050; #endif #endif snprintf(buf, sizeof(buf), "Ralink %cT%x onChip Ethernet driver", sc->rt_chipid >= 0x7600 ? 'M' : 'R', sc->rt_chipid); device_set_desc_copy(dev, buf); return (BUS_PROBE_GENERIC); } /* * macaddr_atoi - translate string MAC address to uint8_t array */ static int macaddr_atoi(const char *str, uint8_t *mac) { int count, i; unsigned int amac[ETHER_ADDR_LEN]; /* Aligned version */ count = sscanf(str, "%x%*c%x%*c%x%*c%x%*c%x%*c%x", &amac[0], &amac[1], &amac[2], &amac[3], &amac[4], &amac[5]); if (count < ETHER_ADDR_LEN) { memset(mac, 0, ETHER_ADDR_LEN); return (1); } /* Copy aligned to result */ for (i = 0; i < ETHER_ADDR_LEN; i ++) mac[i] = (amac[i] & 0xff); return (0); } #ifdef USE_GENERATED_MAC_ADDRESS /* * generate_mac(uin8_t *mac) * This is MAC address generator for cases when real device MAC address * unknown or not yet accessible. * Use 'b','s','d' signature and 3 octets from CRC32 on kenv. * MAC = 'b', 's', 'd', CRC[3]^CRC[2], CRC[1], CRC[0] * * Output - MAC address, that do not change between reboots, if hints or * bootloader info unchange. */ static void generate_mac(uint8_t *mac) { unsigned char *cp; int i = 0; uint32_t crc = 0xffffffff; /* Generate CRC32 on kenv */ for (cp = kenvp[0]; cp != NULL; cp = kenvp[++i]) { crc = calculate_crc32c(crc, cp, strlen(cp) + 1); } crc = ~crc; mac[0] = 'b'; mac[1] = 's'; mac[2] = 'd'; mac[3] = (crc >> 24) ^ ((crc >> 16) & 0xff); mac[4] = (crc >> 8) & 0xff; mac[5] = crc & 0xff; } #endif /* * ether_request_mac - try to find usable MAC address. */ static int ether_request_mac(device_t dev, uint8_t *mac) { char *var; /* * "ethaddr" is passed via envp on RedBoot platforms * "kmac" is passed via argv on RouterBOOT platforms */ #if defined(RT305X_UBOOT) || defined(__REDBOOT__) || defined(__ROUTERBOOT__) if ((var = kern_getenv("ethaddr")) != NULL || (var = kern_getenv("kmac")) != NULL ) { if(!macaddr_atoi(var, mac)) { printf("%s: use %s macaddr from KENV\n", device_get_nameunit(dev), var); freeenv(var); return (0); } freeenv(var); } #endif /* * Try from hints * hint.[dev].[unit].macaddr */ if (!resource_string_value(device_get_name(dev), device_get_unit(dev), "macaddr", (const char **)&var)) { if(!macaddr_atoi(var, mac)) { printf("%s: use %s macaddr from hints\n", device_get_nameunit(dev), var); return (0); } } #ifdef USE_GENERATED_MAC_ADDRESS generate_mac(mac); device_printf(dev, "use generated %02x:%02x:%02x:%02x:%02x:%02x " "macaddr\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); #else /* Hardcoded */ mac[0] = 0x00; mac[1] = 0x18; mac[2] = 0xe7; mac[3] = 0xd5; mac[4] = 0x83; mac[5] = 0x90; device_printf(dev, "use hardcoded 00:18:e7:d5:83:90 macaddr\n"); #endif return (0); } /* * Reset hardware */ static void reset_freng(struct rt_softc *sc) { /* XXX hard reset kills everything so skip it ... */ return; } static int rt_attach(device_t dev) { struct rt_softc *sc; struct ifnet *ifp; int error, i; sc = device_get_softc(dev); sc->dev = dev; mtx_init(&sc->lock, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE); sc->mem_rid = 0; sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, RF_ACTIVE); if (sc->mem == NULL) { device_printf(dev, "could not allocate memory resource\n"); error = ENXIO; goto fail; } sc->bst = rman_get_bustag(sc->mem); sc->bsh = rman_get_bushandle(sc->mem); sc->irq_rid = 0; sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, RF_ACTIVE); if (sc->irq == NULL) { device_printf(dev, "could not allocate interrupt resource\n"); error = ENXIO; goto fail; } #ifdef IF_RT_DEBUG sc->debug = rt_debug; SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "debug", CTLFLAG_RW, &sc->debug, 0, "rt debug level"); #endif /* Reset hardware */ reset_freng(sc); if (sc->rt_chipid == RT_CHIPID_MT7620) { sc->csum_fail_ip = MT7620_RXD_SRC_IP_CSUM_FAIL; sc->csum_fail_l4 = MT7620_RXD_SRC_L4_CSUM_FAIL; } else if (sc->rt_chipid == RT_CHIPID_MT7621) { sc->csum_fail_ip = MT7621_RXD_SRC_IP_CSUM_FAIL; sc->csum_fail_l4 = MT7621_RXD_SRC_L4_CSUM_FAIL; } else { sc->csum_fail_ip = RT305X_RXD_SRC_IP_CSUM_FAIL; sc->csum_fail_l4 = RT305X_RXD_SRC_L4_CSUM_FAIL; } /* Fill in soc-specific registers map */ switch(sc->rt_chipid) { case RT_CHIPID_MT7620: case RT_CHIPID_MT7621: case RT_CHIPID_RT5350: device_printf(dev, "%cT%x Ethernet MAC (rev 0x%08x)\n", sc->rt_chipid >= 0x7600 ? 'M' : 'R', sc->rt_chipid, sc->mac_rev); /* RT5350: No GDMA, PSE, CDMA, PPE */ RT_WRITE(sc, GE_PORT_BASE + 0x0C00, // UDPCS, TCPCS, IPCS=1 RT_READ(sc, GE_PORT_BASE + 0x0C00) | (0x7<<16)); sc->delay_int_cfg=RT5350_PDMA_BASE+RT5350_DELAY_INT_CFG; sc->fe_int_status=RT5350_FE_INT_STATUS; sc->fe_int_enable=RT5350_FE_INT_ENABLE; sc->pdma_glo_cfg=RT5350_PDMA_BASE+RT5350_PDMA_GLO_CFG; sc->pdma_rst_idx=RT5350_PDMA_BASE+RT5350_PDMA_RST_IDX; for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) { sc->tx_base_ptr[i]=RT5350_PDMA_BASE+RT5350_TX_BASE_PTR(i); sc->tx_max_cnt[i]=RT5350_PDMA_BASE+RT5350_TX_MAX_CNT(i); sc->tx_ctx_idx[i]=RT5350_PDMA_BASE+RT5350_TX_CTX_IDX(i); sc->tx_dtx_idx[i]=RT5350_PDMA_BASE+RT5350_TX_DTX_IDX(i); } sc->rx_ring_count=2; sc->rx_base_ptr[0]=RT5350_PDMA_BASE+RT5350_RX_BASE_PTR0; sc->rx_max_cnt[0]=RT5350_PDMA_BASE+RT5350_RX_MAX_CNT0; sc->rx_calc_idx[0]=RT5350_PDMA_BASE+RT5350_RX_CALC_IDX0; sc->rx_drx_idx[0]=RT5350_PDMA_BASE+RT5350_RX_DRX_IDX0; sc->rx_base_ptr[1]=RT5350_PDMA_BASE+RT5350_RX_BASE_PTR1; sc->rx_max_cnt[1]=RT5350_PDMA_BASE+RT5350_RX_MAX_CNT1; sc->rx_calc_idx[1]=RT5350_PDMA_BASE+RT5350_RX_CALC_IDX1; sc->rx_drx_idx[1]=RT5350_PDMA_BASE+RT5350_RX_DRX_IDX1; sc->int_rx_done_mask=RT5350_INT_RXQ0_DONE; sc->int_tx_done_mask=RT5350_INT_TXQ0_DONE; break; default: device_printf(dev, "RT305XF Ethernet MAC (rev 0x%08x)\n", sc->mac_rev); RT_WRITE(sc, GDMA1_BASE + GDMA_FWD_CFG, ( GDM_ICS_EN | /* Enable IP Csum */ GDM_TCS_EN | /* Enable TCP Csum */ GDM_UCS_EN | /* Enable UDP Csum */ GDM_STRPCRC | /* Strip CRC from packet */ GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* fwd UCast to CPU */ GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* fwd BCast to CPU */ GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* fwd MCast to CPU */ GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* fwd Other to CPU */ )); sc->delay_int_cfg=PDMA_BASE+DELAY_INT_CFG; sc->fe_int_status=GE_PORT_BASE+FE_INT_STATUS; sc->fe_int_enable=GE_PORT_BASE+FE_INT_ENABLE; sc->pdma_glo_cfg=PDMA_BASE+PDMA_GLO_CFG; sc->pdma_glo_cfg=PDMA_BASE+PDMA_GLO_CFG; sc->pdma_rst_idx=PDMA_BASE+PDMA_RST_IDX; for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) { sc->tx_base_ptr[i]=PDMA_BASE+TX_BASE_PTR(i); sc->tx_max_cnt[i]=PDMA_BASE+TX_MAX_CNT(i); sc->tx_ctx_idx[i]=PDMA_BASE+TX_CTX_IDX(i); sc->tx_dtx_idx[i]=PDMA_BASE+TX_DTX_IDX(i); } sc->rx_ring_count=1; sc->rx_base_ptr[0]=PDMA_BASE+RX_BASE_PTR0; sc->rx_max_cnt[0]=PDMA_BASE+RX_MAX_CNT0; sc->rx_calc_idx[0]=PDMA_BASE+RX_CALC_IDX0; sc->rx_drx_idx[0]=PDMA_BASE+RX_DRX_IDX0; sc->int_rx_done_mask=INT_RX_DONE; sc->int_tx_done_mask=INT_TXQ0_DONE; } /* allocate Tx and Rx rings */ for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) { error = rt_alloc_tx_ring(sc, &sc->tx_ring[i], i); if (error != 0) { device_printf(dev, "could not allocate Tx ring #%d\n", i); goto fail; } } sc->tx_ring_mgtqid = 5; for (i = 0; i < sc->rx_ring_count; i++) { error = rt_alloc_rx_ring(sc, &sc->rx_ring[i], i); if (error != 0) { device_printf(dev, "could not allocate Rx ring\n"); goto fail; } } callout_init(&sc->periodic_ch, 0); callout_init_mtx(&sc->tx_watchdog_ch, &sc->lock, 0); ifp = sc->ifp = if_alloc(IFT_ETHER); if (ifp == NULL) { device_printf(dev, "could not if_alloc()\n"); error = ENOMEM; goto fail; } ifp->if_softc = sc; if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev)); ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_init = rt_init; ifp->if_ioctl = rt_ioctl; ifp->if_start = rt_start; #define RT_TX_QLEN 256 IFQ_SET_MAXLEN(&ifp->if_snd, RT_TX_QLEN); ifp->if_snd.ifq_drv_maxlen = RT_TX_QLEN; IFQ_SET_READY(&ifp->if_snd); #ifdef IF_RT_PHY_SUPPORT error = mii_attach(dev, &sc->rt_miibus, ifp, rt_ifmedia_upd, rt_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); if (error != 0) { device_printf(dev, "attaching PHYs failed\n"); error = ENXIO; goto fail; } #else ifmedia_init(&sc->rt_ifmedia, 0, rt_ifmedia_upd, rt_ifmedia_sts); ifmedia_add(&sc->rt_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); ifmedia_set(&sc->rt_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX); #endif /* IF_RT_PHY_SUPPORT */ ether_request_mac(dev, sc->mac_addr); ether_ifattach(ifp, sc->mac_addr); /* * Tell the upper layer(s) we support long frames. */ ifp->if_hdrlen = sizeof(struct ether_vlan_header); ifp->if_capabilities |= IFCAP_VLAN_MTU; ifp->if_capenable |= IFCAP_VLAN_MTU; ifp->if_capabilities |= IFCAP_RXCSUM|IFCAP_TXCSUM; ifp->if_capenable |= IFCAP_RXCSUM|IFCAP_TXCSUM; /* init task queue */ TASK_INIT(&sc->rx_done_task, 0, rt_rx_done_task, sc); TASK_INIT(&sc->tx_done_task, 0, rt_tx_done_task, sc); TASK_INIT(&sc->periodic_task, 0, rt_periodic_task, sc); sc->rx_process_limit = 100; sc->taskqueue = taskqueue_create("rt_taskq", M_NOWAIT, taskqueue_thread_enqueue, &sc->taskqueue); taskqueue_start_threads(&sc->taskqueue, 1, PI_NET, "%s taskq", device_get_nameunit(sc->dev)); rt_sysctl_attach(sc); /* set up interrupt */ error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, NULL, (sc->rt_chipid == RT_CHIPID_RT5350 || sc->rt_chipid == RT_CHIPID_MT7620 || sc->rt_chipid == RT_CHIPID_MT7621) ? rt_rt5350_intr : rt_intr, sc, &sc->irqh); if (error != 0) { printf("%s: could not set up interrupt\n", device_get_nameunit(dev)); goto fail; } #ifdef IF_RT_DEBUG device_printf(dev, "debug var at %#08x\n", (u_int)&(sc->debug)); #endif return (0); fail: /* free Tx and Rx rings */ for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) rt_free_tx_ring(sc, &sc->tx_ring[i]); for (i = 0; i < sc->rx_ring_count; i++) rt_free_rx_ring(sc, &sc->rx_ring[i]); mtx_destroy(&sc->lock); if (sc->mem != NULL) bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); if (sc->irq != NULL) bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); return (error); } /* * Set media options. */ static int rt_ifmedia_upd(struct ifnet *ifp) { struct rt_softc *sc; #ifdef IF_RT_PHY_SUPPORT struct mii_data *mii; struct mii_softc *miisc; int error = 0; sc = ifp->if_softc; RT_SOFTC_LOCK(sc); mii = device_get_softc(sc->rt_miibus); LIST_FOREACH(miisc, &mii->mii_phys, mii_list) PHY_RESET(miisc); error = mii_mediachg(mii); RT_SOFTC_UNLOCK(sc); return (error); #else /* !IF_RT_PHY_SUPPORT */ struct ifmedia *ifm; struct ifmedia_entry *ife; sc = ifp->if_softc; ifm = &sc->rt_ifmedia; ife = ifm->ifm_cur; if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) return (EINVAL); if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { device_printf(sc->dev, "AUTO is not supported for multiphy MAC"); return (EINVAL); } /* * Ignore everything */ return (0); #endif /* IF_RT_PHY_SUPPORT */ } /* * Report current media status. */ static void rt_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) { #ifdef IF_RT_PHY_SUPPORT struct rt_softc *sc; struct mii_data *mii; sc = ifp->if_softc; RT_SOFTC_LOCK(sc); mii = device_get_softc(sc->rt_miibus); mii_pollstat(mii); ifmr->ifm_active = mii->mii_media_active; ifmr->ifm_status = mii->mii_media_status; ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; RT_SOFTC_UNLOCK(sc); #else /* !IF_RT_PHY_SUPPORT */ ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; #endif /* IF_RT_PHY_SUPPORT */ } static int rt_detach(device_t dev) { struct rt_softc *sc; struct ifnet *ifp; int i; sc = device_get_softc(dev); ifp = sc->ifp; RT_DPRINTF(sc, RT_DEBUG_ANY, "detaching\n"); RT_SOFTC_LOCK(sc); ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); callout_stop(&sc->periodic_ch); callout_stop(&sc->tx_watchdog_ch); taskqueue_drain(sc->taskqueue, &sc->rx_done_task); taskqueue_drain(sc->taskqueue, &sc->tx_done_task); taskqueue_drain(sc->taskqueue, &sc->periodic_task); /* free Tx and Rx rings */ for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) rt_free_tx_ring(sc, &sc->tx_ring[i]); for (i = 0; i < sc->rx_ring_count; i++) rt_free_rx_ring(sc, &sc->rx_ring[i]); RT_SOFTC_UNLOCK(sc); #ifdef IF_RT_PHY_SUPPORT if (sc->rt_miibus != NULL) device_delete_child(dev, sc->rt_miibus); #endif ether_ifdetach(ifp); if_free(ifp); taskqueue_free(sc->taskqueue); mtx_destroy(&sc->lock); bus_generic_detach(dev); bus_teardown_intr(dev, sc->irq, sc->irqh); bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); return (0); } static int rt_shutdown(device_t dev) { struct rt_softc *sc; sc = device_get_softc(dev); RT_DPRINTF(sc, RT_DEBUG_ANY, "shutting down\n"); rt_stop(sc); return (0); } static int rt_suspend(device_t dev) { struct rt_softc *sc; sc = device_get_softc(dev); RT_DPRINTF(sc, RT_DEBUG_ANY, "suspending\n"); rt_stop(sc); return (0); } static int rt_resume(device_t dev) { struct rt_softc *sc; struct ifnet *ifp; sc = device_get_softc(dev); ifp = sc->ifp; RT_DPRINTF(sc, RT_DEBUG_ANY, "resuming\n"); if (ifp->if_flags & IFF_UP) rt_init(sc); return (0); } /* * rt_init_locked - Run initialization process having locked mtx. */ static void rt_init_locked(void *priv) { struct rt_softc *sc; struct ifnet *ifp; #ifdef IF_RT_PHY_SUPPORT struct mii_data *mii; #endif int i, ntries; uint32_t tmp; sc = priv; ifp = sc->ifp; #ifdef IF_RT_PHY_SUPPORT mii = device_get_softc(sc->rt_miibus); #endif RT_DPRINTF(sc, RT_DEBUG_ANY, "initializing\n"); RT_SOFTC_ASSERT_LOCKED(sc); /* hardware reset */ //RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET); //rt305x_sysctl_set(SYSCTL_RSTCTRL, SYSCTL_RSTCTRL_FRENG); /* Fwd to CPU (uni|broad|multi)cast and Unknown */ if(sc->rt_chipid == RT_CHIPID_RT3050) RT_WRITE(sc, GDMA1_BASE + GDMA_FWD_CFG, ( GDM_ICS_EN | /* Enable IP Csum */ GDM_TCS_EN | /* Enable TCP Csum */ GDM_UCS_EN | /* Enable UDP Csum */ GDM_STRPCRC | /* Strip CRC from packet */ GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* Forward UCast to CPU */ GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* Forward BCast to CPU */ GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* Forward MCast to CPU */ GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* Forward Other to CPU */ )); /* disable DMA engine */ RT_WRITE(sc, sc->pdma_glo_cfg, 0); RT_WRITE(sc, sc->pdma_rst_idx, 0xffffffff); /* wait while DMA engine is busy */ for (ntries = 0; ntries < 100; ntries++) { tmp = RT_READ(sc, sc->pdma_glo_cfg); if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY))) break; DELAY(1000); } if (ntries == 100) { device_printf(sc->dev, "timeout waiting for DMA engine\n"); goto fail; } /* reset Rx and Tx rings */ tmp = FE_RST_DRX_IDX0 | FE_RST_DTX_IDX3 | FE_RST_DTX_IDX2 | FE_RST_DTX_IDX1 | FE_RST_DTX_IDX0; RT_WRITE(sc, sc->pdma_rst_idx, tmp); /* XXX switch set mac address */ for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) rt_reset_tx_ring(sc, &sc->tx_ring[i]); for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) { /* update TX_BASE_PTRx */ RT_WRITE(sc, sc->tx_base_ptr[i], sc->tx_ring[i].desc_phys_addr); RT_WRITE(sc, sc->tx_max_cnt[i], RT_SOFTC_TX_RING_DESC_COUNT); RT_WRITE(sc, sc->tx_ctx_idx[i], 0); } /* init Rx ring */ for (i = 0; i < sc->rx_ring_count; i++) rt_reset_rx_ring(sc, &sc->rx_ring[i]); /* update RX_BASE_PTRx */ for (i = 0; i < sc->rx_ring_count; i++) { RT_WRITE(sc, sc->rx_base_ptr[i], sc->rx_ring[i].desc_phys_addr); RT_WRITE(sc, sc->rx_max_cnt[i], RT_SOFTC_RX_RING_DATA_COUNT); RT_WRITE(sc, sc->rx_calc_idx[i], RT_SOFTC_RX_RING_DATA_COUNT - 1); } /* write back DDONE, 16byte burst enable RX/TX DMA */ tmp = FE_TX_WB_DDONE | FE_DMA_BT_SIZE16 | FE_RX_DMA_EN | FE_TX_DMA_EN; if (sc->rt_chipid == RT_CHIPID_MT7620 || sc->rt_chipid == RT_CHIPID_MT7621) tmp |= (1<<31); RT_WRITE(sc, sc->pdma_glo_cfg, tmp); /* disable interrupts mitigation */ RT_WRITE(sc, sc->delay_int_cfg, 0); /* clear pending interrupts */ RT_WRITE(sc, sc->fe_int_status, 0xffffffff); /* enable interrupts */ if (sc->rt_chipid == RT_CHIPID_RT5350 || sc->rt_chipid == RT_CHIPID_MT7620 || sc->rt_chipid == RT_CHIPID_MT7621) tmp = RT5350_INT_TX_COHERENT | RT5350_INT_RX_COHERENT | RT5350_INT_TXQ3_DONE | RT5350_INT_TXQ2_DONE | RT5350_INT_TXQ1_DONE | RT5350_INT_TXQ0_DONE | RT5350_INT_RXQ1_DONE | RT5350_INT_RXQ0_DONE; else tmp = CNT_PPE_AF | CNT_GDM_AF | PSE_P2_FC | GDM_CRC_DROP | PSE_BUF_DROP | GDM_OTHER_DROP | PSE_P1_FC | PSE_P0_FC | PSE_FQ_EMPTY | INT_TX_COHERENT | INT_RX_COHERENT | INT_TXQ3_DONE | INT_TXQ2_DONE | INT_TXQ1_DONE | INT_TXQ0_DONE | INT_RX_DONE; sc->intr_enable_mask = tmp; RT_WRITE(sc, sc->fe_int_enable, tmp); if (rt_txrx_enable(sc) != 0) goto fail; #ifdef IF_RT_PHY_SUPPORT if (mii) mii_mediachg(mii); #endif /* IF_RT_PHY_SUPPORT */ ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; ifp->if_drv_flags |= IFF_DRV_RUNNING; sc->periodic_round = 0; callout_reset(&sc->periodic_ch, hz / 10, rt_periodic, sc); return; fail: rt_stop_locked(sc); } /* * rt_init - lock and initialize device. */ static void rt_init(void *priv) { struct rt_softc *sc; sc = priv; RT_SOFTC_LOCK(sc); rt_init_locked(sc); RT_SOFTC_UNLOCK(sc); } /* * rt_stop_locked - stop TX/RX w/ lock */ static void rt_stop_locked(void *priv) { struct rt_softc *sc; struct ifnet *ifp; sc = priv; ifp = sc->ifp; RT_DPRINTF(sc, RT_DEBUG_ANY, "stopping\n"); RT_SOFTC_ASSERT_LOCKED(sc); sc->tx_timer = 0; ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); callout_stop(&sc->periodic_ch); callout_stop(&sc->tx_watchdog_ch); RT_SOFTC_UNLOCK(sc); taskqueue_block(sc->taskqueue); /* * Sometime rt_stop_locked called from isr and we get panic * When found, I fix it */ #ifdef notyet taskqueue_drain(sc->taskqueue, &sc->rx_done_task); taskqueue_drain(sc->taskqueue, &sc->tx_done_task); taskqueue_drain(sc->taskqueue, &sc->periodic_task); #endif RT_SOFTC_LOCK(sc); /* disable interrupts */ RT_WRITE(sc, sc->fe_int_enable, 0); if(sc->rt_chipid == RT_CHIPID_RT5350 || sc->rt_chipid == RT_CHIPID_MT7620 || sc->rt_chipid == RT_CHIPID_MT7621) { } else { /* reset adapter */ RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET); RT_WRITE(sc, GDMA1_BASE + GDMA_FWD_CFG, ( GDM_ICS_EN | /* Enable IP Csum */ GDM_TCS_EN | /* Enable TCP Csum */ GDM_UCS_EN | /* Enable UDP Csum */ GDM_STRPCRC | /* Strip CRC from packet */ GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* Forward UCast to CPU */ GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* Forward BCast to CPU */ GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* Forward MCast to CPU */ GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* Forward Other to CPU */ )); } } static void rt_stop(void *priv) { struct rt_softc *sc; sc = priv; RT_SOFTC_LOCK(sc); rt_stop_locked(sc); RT_SOFTC_UNLOCK(sc); } /* * rt_tx_data - transmit packet. */ static int rt_tx_data(struct rt_softc *sc, struct mbuf *m, int qid) { struct ifnet *ifp; struct rt_softc_tx_ring *ring; struct rt_softc_tx_data *data; struct rt_txdesc *desc; struct mbuf *m_d; bus_dma_segment_t dma_seg[RT_SOFTC_MAX_SCATTER]; int error, ndmasegs, ndescs, i; KASSERT(qid >= 0 && qid < RT_SOFTC_TX_RING_COUNT, ("%s: Tx data: invalid qid=%d\n", device_get_nameunit(sc->dev), qid)); RT_SOFTC_TX_RING_ASSERT_LOCKED(&sc->tx_ring[qid]); ifp = sc->ifp; ring = &sc->tx_ring[qid]; desc = &ring->desc[ring->desc_cur]; data = &ring->data[ring->data_cur]; error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, data->dma_map, m, dma_seg, &ndmasegs, 0); if (error != 0) { /* too many fragments, linearize */ RT_DPRINTF(sc, RT_DEBUG_TX, "could not load mbuf DMA map, trying to linearize " "mbuf: ndmasegs=%d, len=%d, error=%d\n", ndmasegs, m->m_pkthdr.len, error); m_d = m_collapse(m, M_NOWAIT, 16); if (m_d == NULL) { m_freem(m); m = NULL; return (ENOMEM); } m = m_d; sc->tx_defrag_packets++; error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, data->dma_map, m, dma_seg, &ndmasegs, 0); if (error != 0) { device_printf(sc->dev, "could not load mbuf DMA map: " "ndmasegs=%d, len=%d, error=%d\n", ndmasegs, m->m_pkthdr.len, error); m_freem(m); return (error); } } if (m->m_pkthdr.len == 0) ndmasegs = 0; /* determine how many Tx descs are required */ ndescs = 1 + ndmasegs / 2; if ((ring->desc_queued + ndescs) > (RT_SOFTC_TX_RING_DESC_COUNT - 2)) { RT_DPRINTF(sc, RT_DEBUG_TX, "there are not enough Tx descs\n"); sc->no_tx_desc_avail++; bus_dmamap_unload(ring->data_dma_tag, data->dma_map); m_freem(m); return (EFBIG); } data->m = m; /* set up Tx descs */ for (i = 0; i < ndmasegs; i += 2) { /* TODO: this needs to be refined as MT7620 for example has * a different word3 layout than RT305x and RT5350 (the last * one doesn't use word3 at all). And so does MT7621... */ if (sc->rt_chipid != RT_CHIPID_MT7621) { /* Set destination */ if (sc->rt_chipid != RT_CHIPID_MT7620) desc->dst = (TXDSCR_DST_PORT_GDMA1); if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) desc->dst |= (TXDSCR_IP_CSUM_GEN | TXDSCR_UDP_CSUM_GEN | TXDSCR_TCP_CSUM_GEN); /* Set queue id */ desc->qn = qid; /* No PPPoE */ desc->pppoe = 0; /* No VLAN */ desc->vid = 0; } else { desc->vid = 0; desc->pppoe = 0; desc->qn = 0; desc->dst = 2; } desc->sdp0 = htole32(dma_seg[i].ds_addr); desc->sdl0 = htole16(dma_seg[i].ds_len | ( ((i+1) == ndmasegs )?RT_TXDESC_SDL0_LASTSEG:0 )); if ((i+1) < ndmasegs) { desc->sdp1 = htole32(dma_seg[i+1].ds_addr); desc->sdl1 = htole16(dma_seg[i+1].ds_len | ( ((i+2) == ndmasegs )?RT_TXDESC_SDL1_LASTSEG:0 )); } else { desc->sdp1 = 0; desc->sdl1 = 0; } if ((i+2) < ndmasegs) { ring->desc_queued++; ring->desc_cur = (ring->desc_cur + 1) % RT_SOFTC_TX_RING_DESC_COUNT; } desc = &ring->desc[ring->desc_cur]; } RT_DPRINTF(sc, RT_DEBUG_TX, "sending data: len=%d, ndmasegs=%d, " "DMA ds_len=%d/%d/%d/%d/%d\n", m->m_pkthdr.len, ndmasegs, (int) dma_seg[0].ds_len, (int) dma_seg[1].ds_len, (int) dma_seg[2].ds_len, (int) dma_seg[3].ds_len, (int) dma_seg[4].ds_len); bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map, BUS_DMASYNC_PREWRITE); bus_dmamap_sync(ring->data_dma_tag, data->dma_map, BUS_DMASYNC_PREWRITE); bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, BUS_DMASYNC_PREWRITE); ring->desc_queued++; ring->desc_cur = (ring->desc_cur + 1) % RT_SOFTC_TX_RING_DESC_COUNT; ring->data_queued++; ring->data_cur = (ring->data_cur + 1) % RT_SOFTC_TX_RING_DATA_COUNT; /* kick Tx */ RT_WRITE(sc, sc->tx_ctx_idx[qid], ring->desc_cur); return (0); } /* * rt_start - start Transmit/Receive */ static void rt_start(struct ifnet *ifp) { struct rt_softc *sc; struct mbuf *m; int qid = 0 /* XXX must check QoS priority */; sc = ifp->if_softc; if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) return; for (;;) { IFQ_DRV_DEQUEUE(&ifp->if_snd, m); if (m == NULL) break; m->m_pkthdr.rcvif = NULL; RT_SOFTC_TX_RING_LOCK(&sc->tx_ring[qid]); if (sc->tx_ring[qid].data_queued >= RT_SOFTC_TX_RING_DATA_COUNT) { RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]); RT_DPRINTF(sc, RT_DEBUG_TX, "if_start: Tx ring with qid=%d is full\n", qid); m_freem(m); ifp->if_drv_flags |= IFF_DRV_OACTIVE; if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); sc->tx_data_queue_full[qid]++; break; } if (rt_tx_data(sc, m, qid) != 0) { RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]); if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); break; } RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]); sc->tx_timer = RT_TX_WATCHDOG_TIMEOUT; callout_reset(&sc->tx_watchdog_ch, hz, rt_tx_watchdog, sc); } } /* * rt_update_promisc - set/clear promiscuous mode. Unused yet, because * filtering done by attached Ethernet switch. */ static void rt_update_promisc(struct ifnet *ifp) { struct rt_softc *sc; sc = ifp->if_softc; printf("%s: %s promiscuous mode\n", device_get_nameunit(sc->dev), (ifp->if_flags & IFF_PROMISC) ? "entering" : "leaving"); } /* * rt_ioctl - ioctl handler. */ static int rt_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) { struct rt_softc *sc; struct ifreq *ifr; #ifdef IF_RT_PHY_SUPPORT struct mii_data *mii; #endif /* IF_RT_PHY_SUPPORT */ int error, startall; sc = ifp->if_softc; ifr = (struct ifreq *) data; error = 0; switch (cmd) { case SIOCSIFFLAGS: startall = 0; RT_SOFTC_LOCK(sc); if (ifp->if_flags & IFF_UP) { if (ifp->if_drv_flags & IFF_DRV_RUNNING) { if ((ifp->if_flags ^ sc->if_flags) & IFF_PROMISC) rt_update_promisc(ifp); } else { rt_init_locked(sc); startall = 1; } } else { if (ifp->if_drv_flags & IFF_DRV_RUNNING) rt_stop_locked(sc); } sc->if_flags = ifp->if_flags; RT_SOFTC_UNLOCK(sc); break; case SIOCGIFMEDIA: case SIOCSIFMEDIA: #ifdef IF_RT_PHY_SUPPORT mii = device_get_softc(sc->rt_miibus); error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); #else error = ifmedia_ioctl(ifp, ifr, &sc->rt_ifmedia, cmd); #endif /* IF_RT_PHY_SUPPORT */ break; default: error = ether_ioctl(ifp, cmd, data); break; } return (error); } /* * rt_periodic - Handler of PERIODIC interrupt */ static void rt_periodic(void *arg) { struct rt_softc *sc; sc = arg; RT_DPRINTF(sc, RT_DEBUG_PERIODIC, "periodic\n"); taskqueue_enqueue(sc->taskqueue, &sc->periodic_task); } /* * rt_tx_watchdog - Handler of TX Watchdog */ static void rt_tx_watchdog(void *arg) { struct rt_softc *sc; struct ifnet *ifp; sc = arg; ifp = sc->ifp; if (sc->tx_timer == 0) return; if (--sc->tx_timer == 0) { device_printf(sc->dev, "Tx watchdog timeout: resetting\n"); #ifdef notyet /* * XXX: Commented out, because reset break input. */ rt_stop_locked(sc); rt_init_locked(sc); #endif if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); sc->tx_watchdog_timeouts++; } callout_reset(&sc->tx_watchdog_ch, hz, rt_tx_watchdog, sc); } /* * rt_cnt_ppe_af - Handler of PPE Counter Table Almost Full interrupt */ static void rt_cnt_ppe_af(struct rt_softc *sc) { RT_DPRINTF(sc, RT_DEBUG_INTR, "PPE Counter Table Almost Full\n"); } /* * rt_cnt_gdm_af - Handler of GDMA 1 & 2 Counter Table Almost Full interrupt */ static void rt_cnt_gdm_af(struct rt_softc *sc) { RT_DPRINTF(sc, RT_DEBUG_INTR, "GDMA 1 & 2 Counter Table Almost Full\n"); } /* * rt_pse_p2_fc - Handler of PSE port2 (GDMA 2) flow control interrupt */ static void rt_pse_p2_fc(struct rt_softc *sc) { RT_DPRINTF(sc, RT_DEBUG_INTR, "PSE port2 (GDMA 2) flow control asserted.\n"); } /* * rt_gdm_crc_drop - Handler of GDMA 1/2 discard a packet due to CRC error * interrupt */ static void rt_gdm_crc_drop(struct rt_softc *sc) { RT_DPRINTF(sc, RT_DEBUG_INTR, "GDMA 1 & 2 discard a packet due to CRC error\n"); } /* * rt_pse_buf_drop - Handler of buffer sharing limitation interrupt */ static void rt_pse_buf_drop(struct rt_softc *sc) { RT_DPRINTF(sc, RT_DEBUG_INTR, "PSE discards a packet due to buffer sharing limitation\n"); } /* * rt_gdm_other_drop - Handler of discard on other reason interrupt */ static void rt_gdm_other_drop(struct rt_softc *sc) { RT_DPRINTF(sc, RT_DEBUG_INTR, "GDMA 1 & 2 discard a packet due to other reason\n"); } /* * rt_pse_p1_fc - Handler of PSE port1 (GDMA 1) flow control interrupt */ static void rt_pse_p1_fc(struct rt_softc *sc) { RT_DPRINTF(sc, RT_DEBUG_INTR, "PSE port1 (GDMA 1) flow control asserted.\n"); } /* * rt_pse_p0_fc - Handler of PSE port0 (CDMA) flow control interrupt */ static void rt_pse_p0_fc(struct rt_softc *sc) { RT_DPRINTF(sc, RT_DEBUG_INTR, "PSE port0 (CDMA) flow control asserted.\n"); } /* * rt_pse_fq_empty - Handler of PSE free Q empty threshold reached interrupt */ static void rt_pse_fq_empty(struct rt_softc *sc) { RT_DPRINTF(sc, RT_DEBUG_INTR, "PSE free Q empty threshold reached & forced drop " "condition occurred.\n"); } /* * rt_intr - main ISR */ static void rt_intr(void *arg) { struct rt_softc *sc; struct ifnet *ifp; uint32_t status; sc = arg; ifp = sc->ifp; /* acknowledge interrupts */ status = RT_READ(sc, sc->fe_int_status); RT_WRITE(sc, sc->fe_int_status, status); RT_DPRINTF(sc, RT_DEBUG_INTR, "interrupt: status=0x%08x\n", status); if (status == 0xffffffff || /* device likely went away */ status == 0) /* not for us */ return; sc->interrupts++; if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) return; if (status & CNT_PPE_AF) rt_cnt_ppe_af(sc); if (status & CNT_GDM_AF) rt_cnt_gdm_af(sc); if (status & PSE_P2_FC) rt_pse_p2_fc(sc); if (status & GDM_CRC_DROP) rt_gdm_crc_drop(sc); if (status & PSE_BUF_DROP) rt_pse_buf_drop(sc); if (status & GDM_OTHER_DROP) rt_gdm_other_drop(sc); if (status & PSE_P1_FC) rt_pse_p1_fc(sc); if (status & PSE_P0_FC) rt_pse_p0_fc(sc); if (status & PSE_FQ_EMPTY) rt_pse_fq_empty(sc); if (status & INT_TX_COHERENT) rt_tx_coherent_intr(sc); if (status & INT_RX_COHERENT) rt_rx_coherent_intr(sc); if (status & RX_DLY_INT) rt_rx_delay_intr(sc); if (status & TX_DLY_INT) rt_tx_delay_intr(sc); if (status & INT_RX_DONE) rt_rx_intr(sc, 0); if (status & INT_TXQ3_DONE) rt_tx_intr(sc, 3); if (status & INT_TXQ2_DONE) rt_tx_intr(sc, 2); if (status & INT_TXQ1_DONE) rt_tx_intr(sc, 1); if (status & INT_TXQ0_DONE) rt_tx_intr(sc, 0); } /* * rt_rt5350_intr - main ISR for Ralink 5350 SoC */ static void rt_rt5350_intr(void *arg) { struct rt_softc *sc; struct ifnet *ifp; uint32_t status; sc = arg; ifp = sc->ifp; /* acknowledge interrupts */ status = RT_READ(sc, sc->fe_int_status); RT_WRITE(sc, sc->fe_int_status, status); RT_DPRINTF(sc, RT_DEBUG_INTR, "interrupt: status=0x%08x\n", status); if (status == 0xffffffff || /* device likely went away */ status == 0) /* not for us */ return; sc->interrupts++; if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) return; if (status & RT5350_INT_TX_COHERENT) rt_tx_coherent_intr(sc); if (status & RT5350_INT_RX_COHERENT) rt_rx_coherent_intr(sc); if (status & RT5350_RX_DLY_INT) rt_rx_delay_intr(sc); if (status & RT5350_TX_DLY_INT) rt_tx_delay_intr(sc); if (status & RT5350_INT_RXQ1_DONE) rt_rx_intr(sc, 1); if (status & RT5350_INT_RXQ0_DONE) rt_rx_intr(sc, 0); if (status & RT5350_INT_TXQ3_DONE) rt_tx_intr(sc, 3); if (status & RT5350_INT_TXQ2_DONE) rt_tx_intr(sc, 2); if (status & RT5350_INT_TXQ1_DONE) rt_tx_intr(sc, 1); if (status & RT5350_INT_TXQ0_DONE) rt_tx_intr(sc, 0); } static void rt_tx_coherent_intr(struct rt_softc *sc) { uint32_t tmp; int i; RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx coherent interrupt\n"); sc->tx_coherent_interrupts++; /* restart DMA engine */ tmp = RT_READ(sc, sc->pdma_glo_cfg); tmp &= ~(FE_TX_WB_DDONE | FE_TX_DMA_EN); RT_WRITE(sc, sc->pdma_glo_cfg, tmp); for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) rt_reset_tx_ring(sc, &sc->tx_ring[i]); for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) { RT_WRITE(sc, sc->tx_base_ptr[i], sc->tx_ring[i].desc_phys_addr); RT_WRITE(sc, sc->tx_max_cnt[i], RT_SOFTC_TX_RING_DESC_COUNT); RT_WRITE(sc, sc->tx_ctx_idx[i], 0); } rt_txrx_enable(sc); } /* * rt_rx_coherent_intr */ static void rt_rx_coherent_intr(struct rt_softc *sc) { uint32_t tmp; int i; RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx coherent interrupt\n"); sc->rx_coherent_interrupts++; /* restart DMA engine */ tmp = RT_READ(sc, sc->pdma_glo_cfg); tmp &= ~(FE_RX_DMA_EN); RT_WRITE(sc, sc->pdma_glo_cfg, tmp); /* init Rx ring */ for (i = 0; i < sc->rx_ring_count; i++) rt_reset_rx_ring(sc, &sc->rx_ring[i]); for (i = 0; i < sc->rx_ring_count; i++) { RT_WRITE(sc, sc->rx_base_ptr[i], sc->rx_ring[i].desc_phys_addr); RT_WRITE(sc, sc->rx_max_cnt[i], RT_SOFTC_RX_RING_DATA_COUNT); RT_WRITE(sc, sc->rx_calc_idx[i], RT_SOFTC_RX_RING_DATA_COUNT - 1); } rt_txrx_enable(sc); } /* * rt_rx_intr - a packet received */ static void rt_rx_intr(struct rt_softc *sc, int qid) { KASSERT(qid >= 0 && qid < sc->rx_ring_count, ("%s: Rx interrupt: invalid qid=%d\n", device_get_nameunit(sc->dev), qid)); RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx interrupt\n"); sc->rx_interrupts[qid]++; RT_SOFTC_LOCK(sc); if (!(sc->intr_disable_mask & (sc->int_rx_done_mask << qid))) { rt_intr_disable(sc, (sc->int_rx_done_mask << qid)); taskqueue_enqueue(sc->taskqueue, &sc->rx_done_task); } sc->intr_pending_mask |= (sc->int_rx_done_mask << qid); RT_SOFTC_UNLOCK(sc); } static void rt_rx_delay_intr(struct rt_softc *sc) { RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx delay interrupt\n"); sc->rx_delay_interrupts++; } static void rt_tx_delay_intr(struct rt_softc *sc) { RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx delay interrupt\n"); sc->tx_delay_interrupts++; } /* * rt_tx_intr - Transsmition of packet done */ static void rt_tx_intr(struct rt_softc *sc, int qid) { KASSERT(qid >= 0 && qid < RT_SOFTC_TX_RING_COUNT, ("%s: Tx interrupt: invalid qid=%d\n", device_get_nameunit(sc->dev), qid)); RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx interrupt: qid=%d\n", qid); sc->tx_interrupts[qid]++; RT_SOFTC_LOCK(sc); if (!(sc->intr_disable_mask & (sc->int_tx_done_mask << qid))) { rt_intr_disable(sc, (sc->int_tx_done_mask << qid)); taskqueue_enqueue(sc->taskqueue, &sc->tx_done_task); } sc->intr_pending_mask |= (sc->int_tx_done_mask << qid); RT_SOFTC_UNLOCK(sc); } /* * rt_rx_done_task - run RX task */ static void rt_rx_done_task(void *context, int pending) { struct rt_softc *sc; struct ifnet *ifp; int again; sc = context; ifp = sc->ifp; RT_DPRINTF(sc, RT_DEBUG_RX, "Rx done task\n"); if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) return; sc->intr_pending_mask &= ~sc->int_rx_done_mask; again = rt_rx_eof(sc, &sc->rx_ring[0], sc->rx_process_limit); RT_SOFTC_LOCK(sc); if ((sc->intr_pending_mask & sc->int_rx_done_mask) || again) { RT_DPRINTF(sc, RT_DEBUG_RX, "Rx done task: scheduling again\n"); taskqueue_enqueue(sc->taskqueue, &sc->rx_done_task); } else { rt_intr_enable(sc, sc->int_rx_done_mask); } RT_SOFTC_UNLOCK(sc); } /* * rt_tx_done_task - check for pending TX task in all queues */ static void rt_tx_done_task(void *context, int pending) { struct rt_softc *sc; struct ifnet *ifp; uint32_t intr_mask; int i; sc = context; ifp = sc->ifp; RT_DPRINTF(sc, RT_DEBUG_TX, "Tx done task\n"); if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) return; for (i = RT_SOFTC_TX_RING_COUNT - 1; i >= 0; i--) { if (sc->intr_pending_mask & (sc->int_tx_done_mask << i)) { sc->intr_pending_mask &= ~(sc->int_tx_done_mask << i); rt_tx_eof(sc, &sc->tx_ring[i]); } } sc->tx_timer = 0; ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; if(sc->rt_chipid == RT_CHIPID_RT5350 || sc->rt_chipid == RT_CHIPID_MT7620 || sc->rt_chipid == RT_CHIPID_MT7621) intr_mask = ( RT5350_INT_TXQ3_DONE | RT5350_INT_TXQ2_DONE | RT5350_INT_TXQ1_DONE | RT5350_INT_TXQ0_DONE); else intr_mask = ( INT_TXQ3_DONE | INT_TXQ2_DONE | INT_TXQ1_DONE | INT_TXQ0_DONE); RT_SOFTC_LOCK(sc); rt_intr_enable(sc, ~sc->intr_pending_mask & (sc->intr_disable_mask & intr_mask)); if (sc->intr_pending_mask & intr_mask) { RT_DPRINTF(sc, RT_DEBUG_TX, "Tx done task: scheduling again\n"); taskqueue_enqueue(sc->taskqueue, &sc->tx_done_task); } RT_SOFTC_UNLOCK(sc); if (!IFQ_IS_EMPTY(&ifp->if_snd)) rt_start(ifp); } /* * rt_periodic_task - run periodic task */ static void rt_periodic_task(void *context, int pending) { struct rt_softc *sc; struct ifnet *ifp; sc = context; ifp = sc->ifp; RT_DPRINTF(sc, RT_DEBUG_PERIODIC, "periodic task: round=%lu\n", sc->periodic_round); if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) return; RT_SOFTC_LOCK(sc); sc->periodic_round++; rt_update_stats(sc); if ((sc->periodic_round % 10) == 0) { rt_update_raw_counters(sc); rt_watchdog(sc); } RT_SOFTC_UNLOCK(sc); callout_reset(&sc->periodic_ch, hz / 10, rt_periodic, sc); } /* * rt_rx_eof - check for frames that done by DMA engine and pass it into * network subsystem. */ static int rt_rx_eof(struct rt_softc *sc, struct rt_softc_rx_ring *ring, int limit) { struct ifnet *ifp; /* struct rt_softc_rx_ring *ring; */ struct rt_rxdesc *desc; struct rt_softc_rx_data *data; struct mbuf *m, *mnew; bus_dma_segment_t segs[1]; bus_dmamap_t dma_map; uint32_t index, desc_flags; int error, nsegs, len, nframes; ifp = sc->ifp; /* ring = &sc->rx_ring[0]; */ nframes = 0; while (limit != 0) { index = RT_READ(sc, sc->rx_drx_idx[0]); if (ring->cur == index) break; desc = &ring->desc[ring->cur]; data = &ring->data[ring->cur]; bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); #ifdef IF_RT_DEBUG if ( sc->debug & RT_DEBUG_RX ) { printf("\nRX Descriptor[%#08x] dump:\n", (u_int)desc); hexdump(desc, 16, 0, 0); printf("-----------------------------------\n"); } #endif /* XXX Sometime device don`t set DDONE bit */ #ifdef DDONE_FIXED if (!(desc->sdl0 & htole16(RT_RXDESC_SDL0_DDONE))) { RT_DPRINTF(sc, RT_DEBUG_RX, "DDONE=0, try next\n"); break; } #endif len = le16toh(desc->sdl0) & 0x3fff; RT_DPRINTF(sc, RT_DEBUG_RX, "new frame len=%d\n", len); nframes++; mnew = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); if (mnew == NULL) { sc->rx_mbuf_alloc_errors++; if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); goto skip; } mnew->m_len = mnew->m_pkthdr.len = MJUMPAGESIZE; error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, ring->spare_dma_map, mnew, segs, &nsegs, BUS_DMA_NOWAIT); if (error != 0) { RT_DPRINTF(sc, RT_DEBUG_RX, "could not load Rx mbuf DMA map: " "error=%d, nsegs=%d\n", error, nsegs); m_freem(mnew); sc->rx_mbuf_dmamap_errors++; if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); goto skip; } KASSERT(nsegs == 1, ("%s: too many DMA segments", device_get_nameunit(sc->dev))); bus_dmamap_sync(ring->data_dma_tag, data->dma_map, BUS_DMASYNC_POSTREAD); bus_dmamap_unload(ring->data_dma_tag, data->dma_map); dma_map = data->dma_map; data->dma_map = ring->spare_dma_map; ring->spare_dma_map = dma_map; bus_dmamap_sync(ring->data_dma_tag, data->dma_map, BUS_DMASYNC_PREREAD); m = data->m; desc_flags = desc->word3; data->m = mnew; /* Add 2 for proper align of RX IP header */ desc->sdp0 = htole32(segs[0].ds_addr+2); desc->sdl0 = htole32(segs[0].ds_len-2); desc->word3 = 0; RT_DPRINTF(sc, RT_DEBUG_RX, "Rx frame: rxdesc flags=0x%08x\n", desc_flags); m->m_pkthdr.rcvif = ifp; /* Add 2 to fix data align, after sdp0 = addr + 2 */ m->m_data += 2; m->m_pkthdr.len = m->m_len = len; /* check for crc errors */ if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { /*check for valid checksum*/ if (desc_flags & (sc->csum_fail_ip|sc->csum_fail_l4)) { RT_DPRINTF(sc, RT_DEBUG_RX, "rxdesc: crc error\n"); if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); if (!(ifp->if_flags & IFF_PROMISC)) { m_freem(m); goto skip; } } if ((desc_flags & sc->csum_fail_ip) == 0) { m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; m->m_pkthdr.csum_flags |= CSUM_IP_VALID; m->m_pkthdr.csum_data = 0xffff; } m->m_flags &= ~M_HASFCS; } (*ifp->if_input)(ifp, m); skip: desc->sdl0 &= ~htole16(RT_RXDESC_SDL0_DDONE); bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ring->cur = (ring->cur + 1) % RT_SOFTC_RX_RING_DATA_COUNT; limit--; } if (ring->cur == 0) RT_WRITE(sc, sc->rx_calc_idx[0], RT_SOFTC_RX_RING_DATA_COUNT - 1); else RT_WRITE(sc, sc->rx_calc_idx[0], ring->cur - 1); RT_DPRINTF(sc, RT_DEBUG_RX, "Rx eof: nframes=%d\n", nframes); sc->rx_packets += nframes; return (limit == 0); } /* * rt_tx_eof - check for successful transmitted frames and mark their * descriptor as free. */ static void rt_tx_eof(struct rt_softc *sc, struct rt_softc_tx_ring *ring) { struct ifnet *ifp; struct rt_txdesc *desc; struct rt_softc_tx_data *data; uint32_t index; int ndescs, nframes; ifp = sc->ifp; ndescs = 0; nframes = 0; for (;;) { index = RT_READ(sc, sc->tx_dtx_idx[ring->qid]); if (ring->desc_next == index) break; ndescs++; desc = &ring->desc[ring->desc_next]; bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); if (desc->sdl0 & htole16(RT_TXDESC_SDL0_LASTSEG) || desc->sdl1 & htole16(RT_TXDESC_SDL1_LASTSEG)) { nframes++; data = &ring->data[ring->data_next]; bus_dmamap_sync(ring->data_dma_tag, data->dma_map, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(ring->data_dma_tag, data->dma_map); m_freem(data->m); data->m = NULL; if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); RT_SOFTC_TX_RING_LOCK(ring); ring->data_queued--; ring->data_next = (ring->data_next + 1) % RT_SOFTC_TX_RING_DATA_COUNT; RT_SOFTC_TX_RING_UNLOCK(ring); } desc->sdl0 &= ~htole16(RT_TXDESC_SDL0_DDONE); bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); RT_SOFTC_TX_RING_LOCK(ring); ring->desc_queued--; ring->desc_next = (ring->desc_next + 1) % RT_SOFTC_TX_RING_DESC_COUNT; RT_SOFTC_TX_RING_UNLOCK(ring); } RT_DPRINTF(sc, RT_DEBUG_TX, "Tx eof: qid=%d, ndescs=%d, nframes=%d\n", ring->qid, ndescs, nframes); } /* * rt_update_stats - query statistics counters and update related variables. */ static void rt_update_stats(struct rt_softc *sc) { struct ifnet *ifp; ifp = sc->ifp; RT_DPRINTF(sc, RT_DEBUG_STATS, "update statistic: \n"); /* XXX do update stats here */ } /* * rt_watchdog - reinit device on watchdog event. */ static void rt_watchdog(struct rt_softc *sc) { uint32_t tmp; #ifdef notyet int ntries; #endif if(sc->rt_chipid != RT_CHIPID_RT5350 && sc->rt_chipid != RT_CHIPID_MT7620 && sc->rt_chipid != RT_CHIPID_MT7621) { tmp = RT_READ(sc, PSE_BASE + CDMA_OQ_STA); RT_DPRINTF(sc, RT_DEBUG_WATCHDOG, "watchdog: PSE_IQ_STA=0x%08x\n", tmp); } /* XXX: do not reset */ #ifdef notyet if (((tmp >> P0_IQ_PCNT_SHIFT) & 0xff) != 0) { sc->tx_queue_not_empty[0]++; for (ntries = 0; ntries < 10; ntries++) { tmp = RT_READ(sc, PSE_BASE + PSE_IQ_STA); if (((tmp >> P0_IQ_PCNT_SHIFT) & 0xff) == 0) break; DELAY(1); } } if (((tmp >> P1_IQ_PCNT_SHIFT) & 0xff) != 0) { sc->tx_queue_not_empty[1]++; for (ntries = 0; ntries < 10; ntries++) { tmp = RT_READ(sc, PSE_BASE + PSE_IQ_STA); if (((tmp >> P1_IQ_PCNT_SHIFT) & 0xff) == 0) break; DELAY(1); } } #endif } /* * rt_update_raw_counters - update counters. */ static void rt_update_raw_counters(struct rt_softc *sc) { sc->tx_bytes += RT_READ(sc, CNTR_BASE + GDMA_TX_GBCNT0); sc->tx_packets += RT_READ(sc, CNTR_BASE + GDMA_TX_GPCNT0); sc->tx_skip += RT_READ(sc, CNTR_BASE + GDMA_TX_SKIPCNT0); sc->tx_collision+= RT_READ(sc, CNTR_BASE + GDMA_TX_COLCNT0); sc->rx_bytes += RT_READ(sc, CNTR_BASE + GDMA_RX_GBCNT0); sc->rx_packets += RT_READ(sc, CNTR_BASE + GDMA_RX_GPCNT0); sc->rx_crc_err += RT_READ(sc, CNTR_BASE + GDMA_RX_CSUM_ERCNT0); sc->rx_short_err+= RT_READ(sc, CNTR_BASE + GDMA_RX_SHORT_ERCNT0); sc->rx_long_err += RT_READ(sc, CNTR_BASE + GDMA_RX_LONG_ERCNT0); sc->rx_phy_err += RT_READ(sc, CNTR_BASE + GDMA_RX_FERCNT0); sc->rx_fifo_overflows+= RT_READ(sc, CNTR_BASE + GDMA_RX_OERCNT0); } static void rt_intr_enable(struct rt_softc *sc, uint32_t intr_mask) { uint32_t tmp; sc->intr_disable_mask &= ~intr_mask; tmp = sc->intr_enable_mask & ~sc->intr_disable_mask; RT_WRITE(sc, sc->fe_int_enable, tmp); } static void rt_intr_disable(struct rt_softc *sc, uint32_t intr_mask) { uint32_t tmp; sc->intr_disable_mask |= intr_mask; tmp = sc->intr_enable_mask & ~sc->intr_disable_mask; RT_WRITE(sc, sc->fe_int_enable, tmp); } /* * rt_txrx_enable - enable TX/RX DMA */ static int rt_txrx_enable(struct rt_softc *sc) { struct ifnet *ifp; uint32_t tmp; int ntries; ifp = sc->ifp; /* enable Tx/Rx DMA engine */ for (ntries = 0; ntries < 200; ntries++) { tmp = RT_READ(sc, sc->pdma_glo_cfg); if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY))) break; DELAY(1000); } if (ntries == 200) { device_printf(sc->dev, "timeout waiting for DMA engine\n"); return (-1); } DELAY(50); tmp |= FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN; RT_WRITE(sc, sc->pdma_glo_cfg, tmp); /* XXX set Rx filter */ return (0); } /* * rt_alloc_rx_ring - allocate RX DMA ring buffer */ static int rt_alloc_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring, int qid) { struct rt_rxdesc *desc; struct rt_softc_rx_data *data; bus_dma_segment_t segs[1]; int i, nsegs, error; error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc), 1, RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc), 0, NULL, NULL, &ring->desc_dma_tag); if (error != 0) { device_printf(sc->dev, "could not create Rx desc DMA tag\n"); goto fail; } error = bus_dmamem_alloc(ring->desc_dma_tag, (void **) &ring->desc, BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_dma_map); if (error != 0) { device_printf(sc->dev, "could not allocate Rx desc DMA memory\n"); goto fail; } error = bus_dmamap_load(ring->desc_dma_tag, ring->desc_dma_map, ring->desc, RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc), rt_dma_map_addr, &ring->desc_phys_addr, 0); if (error != 0) { device_printf(sc->dev, "could not load Rx desc DMA map\n"); goto fail; } error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MJUMPAGESIZE, 1, MJUMPAGESIZE, 0, NULL, NULL, &ring->data_dma_tag); if (error != 0) { device_printf(sc->dev, "could not create Rx data DMA tag\n"); goto fail; } for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) { desc = &ring->desc[i]; data = &ring->data[i]; error = bus_dmamap_create(ring->data_dma_tag, 0, &data->dma_map); if (error != 0) { device_printf(sc->dev, "could not create Rx data DMA " "map\n"); goto fail; } data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); if (data->m == NULL) { device_printf(sc->dev, "could not allocate Rx mbuf\n"); error = ENOMEM; goto fail; } data->m->m_len = data->m->m_pkthdr.len = MJUMPAGESIZE; error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, data->dma_map, data->m, segs, &nsegs, BUS_DMA_NOWAIT); if (error != 0) { device_printf(sc->dev, "could not load Rx mbuf DMA map\n"); goto fail; } KASSERT(nsegs == 1, ("%s: too many DMA segments", device_get_nameunit(sc->dev))); /* Add 2 for proper align of RX IP header */ desc->sdp0 = htole32(segs[0].ds_addr+2); desc->sdl0 = htole32(segs[0].ds_len-2); } error = bus_dmamap_create(ring->data_dma_tag, 0, &ring->spare_dma_map); if (error != 0) { device_printf(sc->dev, "could not create Rx spare DMA map\n"); goto fail; } bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ring->qid = qid; return (0); fail: rt_free_rx_ring(sc, ring); return (error); } /* * rt_reset_rx_ring - reset RX ring buffer */ static void rt_reset_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring) { struct rt_rxdesc *desc; int i; for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) { desc = &ring->desc[i]; desc->sdl0 &= ~htole16(RT_RXDESC_SDL0_DDONE); } bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ring->cur = 0; } /* * rt_free_rx_ring - free memory used by RX ring buffer */ static void rt_free_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring) { struct rt_softc_rx_data *data; int i; if (ring->desc != NULL) { bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(ring->desc_dma_tag, ring->desc_dma_map); bus_dmamem_free(ring->desc_dma_tag, ring->desc, ring->desc_dma_map); } if (ring->desc_dma_tag != NULL) bus_dma_tag_destroy(ring->desc_dma_tag); for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) { data = &ring->data[i]; if (data->m != NULL) { bus_dmamap_sync(ring->data_dma_tag, data->dma_map, BUS_DMASYNC_POSTREAD); bus_dmamap_unload(ring->data_dma_tag, data->dma_map); m_freem(data->m); } if (data->dma_map != NULL) bus_dmamap_destroy(ring->data_dma_tag, data->dma_map); } if (ring->spare_dma_map != NULL) bus_dmamap_destroy(ring->data_dma_tag, ring->spare_dma_map); if (ring->data_dma_tag != NULL) bus_dma_tag_destroy(ring->data_dma_tag); } /* * rt_alloc_tx_ring - allocate TX ring buffer */ static int rt_alloc_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring, int qid) { struct rt_softc_tx_data *data; int error, i; mtx_init(&ring->lock, device_get_nameunit(sc->dev), NULL, MTX_DEF); error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, RT_SOFTC_TX_RING_DESC_COUNT * sizeof(struct rt_txdesc), 1, RT_SOFTC_TX_RING_DESC_COUNT * sizeof(struct rt_txdesc), 0, NULL, NULL, &ring->desc_dma_tag); if (error != 0) { device_printf(sc->dev, "could not create Tx desc DMA tag\n"); goto fail; } error = bus_dmamem_alloc(ring->desc_dma_tag, (void **) &ring->desc, BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_dma_map); if (error != 0) { device_printf(sc->dev, "could not allocate Tx desc DMA memory\n"); goto fail; } error = bus_dmamap_load(ring->desc_dma_tag, ring->desc_dma_map, ring->desc, (RT_SOFTC_TX_RING_DESC_COUNT * sizeof(struct rt_txdesc)), rt_dma_map_addr, &ring->desc_phys_addr, 0); if (error != 0) { device_printf(sc->dev, "could not load Tx desc DMA map\n"); goto fail; } ring->desc_queued = 0; ring->desc_cur = 0; ring->desc_next = 0; error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE, 1, RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE, 0, NULL, NULL, &ring->seg0_dma_tag); if (error != 0) { device_printf(sc->dev, "could not create Tx seg0 DMA tag\n"); goto fail; } error = bus_dmamem_alloc(ring->seg0_dma_tag, (void **) &ring->seg0, BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->seg0_dma_map); if (error != 0) { device_printf(sc->dev, "could not allocate Tx seg0 DMA memory\n"); goto fail; } error = bus_dmamap_load(ring->seg0_dma_tag, ring->seg0_dma_map, ring->seg0, RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE, rt_dma_map_addr, &ring->seg0_phys_addr, 0); if (error != 0) { device_printf(sc->dev, "could not load Tx seg0 DMA map\n"); goto fail; } error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MJUMPAGESIZE, RT_SOFTC_MAX_SCATTER, MJUMPAGESIZE, 0, NULL, NULL, &ring->data_dma_tag); if (error != 0) { device_printf(sc->dev, "could not create Tx data DMA tag\n"); goto fail; } for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) { data = &ring->data[i]; error = bus_dmamap_create(ring->data_dma_tag, 0, &data->dma_map); if (error != 0) { device_printf(sc->dev, "could not create Tx data DMA " "map\n"); goto fail; } } ring->data_queued = 0; ring->data_cur = 0; ring->data_next = 0; ring->qid = qid; return (0); fail: rt_free_tx_ring(sc, ring); return (error); } /* * rt_reset_tx_ring - reset TX ring buffer to empty state */ static void rt_reset_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring) { struct rt_softc_tx_data *data; struct rt_txdesc *desc; int i; for (i = 0; i < RT_SOFTC_TX_RING_DESC_COUNT; i++) { desc = &ring->desc[i]; desc->sdl0 = 0; desc->sdl1 = 0; } ring->desc_queued = 0; ring->desc_cur = 0; ring->desc_next = 0; bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, BUS_DMASYNC_PREWRITE); bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map, BUS_DMASYNC_PREWRITE); for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) { data = &ring->data[i]; if (data->m != NULL) { bus_dmamap_sync(ring->data_dma_tag, data->dma_map, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(ring->data_dma_tag, data->dma_map); m_freem(data->m); data->m = NULL; } } ring->data_queued = 0; ring->data_cur = 0; ring->data_next = 0; } /* * rt_free_tx_ring - free RX ring buffer */ static void rt_free_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring) { struct rt_softc_tx_data *data; int i; if (ring->desc != NULL) { bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(ring->desc_dma_tag, ring->desc_dma_map); bus_dmamem_free(ring->desc_dma_tag, ring->desc, ring->desc_dma_map); } if (ring->desc_dma_tag != NULL) bus_dma_tag_destroy(ring->desc_dma_tag); if (ring->seg0 != NULL) { bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(ring->seg0_dma_tag, ring->seg0_dma_map); bus_dmamem_free(ring->seg0_dma_tag, ring->seg0, ring->seg0_dma_map); } if (ring->seg0_dma_tag != NULL) bus_dma_tag_destroy(ring->seg0_dma_tag); for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) { data = &ring->data[i]; if (data->m != NULL) { bus_dmamap_sync(ring->data_dma_tag, data->dma_map, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(ring->data_dma_tag, data->dma_map); m_freem(data->m); } if (data->dma_map != NULL) bus_dmamap_destroy(ring->data_dma_tag, data->dma_map); } if (ring->data_dma_tag != NULL) bus_dma_tag_destroy(ring->data_dma_tag); mtx_destroy(&ring->lock); } /* * rt_dma_map_addr - get address of busdma segment */ static void rt_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) { if (error != 0) return; KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); *(bus_addr_t *) arg = segs[0].ds_addr; } /* * rt_sysctl_attach - attach sysctl nodes for NIC counters. */ static void rt_sysctl_attach(struct rt_softc *sc) { struct sysctl_ctx_list *ctx; struct sysctl_oid *tree; struct sysctl_oid *stats; ctx = device_get_sysctl_ctx(sc->dev); tree = device_get_sysctl_tree(sc->dev); /* statistic counters */ stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "stats", CTLFLAG_RD, 0, "statistic"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "interrupts", CTLFLAG_RD, &sc->interrupts, "all interrupts"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx_coherent_interrupts", CTLFLAG_RD, &sc->tx_coherent_interrupts, "Tx coherent interrupts"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx_coherent_interrupts", CTLFLAG_RD, &sc->rx_coherent_interrupts, "Rx coherent interrupts"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx_interrupts", CTLFLAG_RD, &sc->rx_interrupts[0], "Rx interrupts"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx_delay_interrupts", CTLFLAG_RD, &sc->rx_delay_interrupts, "Rx delay interrupts"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "TXQ3_interrupts", CTLFLAG_RD, &sc->tx_interrupts[3], "Tx AC3 interrupts"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "TXQ2_interrupts", CTLFLAG_RD, &sc->tx_interrupts[2], "Tx AC2 interrupts"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "TXQ1_interrupts", CTLFLAG_RD, &sc->tx_interrupts[1], "Tx AC1 interrupts"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "TXQ0_interrupts", CTLFLAG_RD, &sc->tx_interrupts[0], "Tx AC0 interrupts"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx_delay_interrupts", CTLFLAG_RD, &sc->tx_delay_interrupts, "Tx delay interrupts"); SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "TXQ3_desc_queued", CTLFLAG_RD, &sc->tx_ring[3].desc_queued, 0, "Tx AC3 descriptors queued"); SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "TXQ3_data_queued", CTLFLAG_RD, &sc->tx_ring[3].data_queued, 0, "Tx AC3 data queued"); SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "TXQ2_desc_queued", CTLFLAG_RD, &sc->tx_ring[2].desc_queued, 0, "Tx AC2 descriptors queued"); SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "TXQ2_data_queued", CTLFLAG_RD, &sc->tx_ring[2].data_queued, 0, "Tx AC2 data queued"); SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "TXQ1_desc_queued", CTLFLAG_RD, &sc->tx_ring[1].desc_queued, 0, "Tx AC1 descriptors queued"); SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "TXQ1_data_queued", CTLFLAG_RD, &sc->tx_ring[1].data_queued, 0, "Tx AC1 data queued"); SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "TXQ0_desc_queued", CTLFLAG_RD, &sc->tx_ring[0].desc_queued, 0, "Tx AC0 descriptors queued"); SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "TXQ0_data_queued", CTLFLAG_RD, &sc->tx_ring[0].data_queued, 0, "Tx AC0 data queued"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "TXQ3_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[3], "Tx AC3 data queue full"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "TXQ2_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[2], "Tx AC2 data queue full"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "TXQ1_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[1], "Tx AC1 data queue full"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "TXQ0_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[0], "Tx AC0 data queue full"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx_watchdog_timeouts", CTLFLAG_RD, &sc->tx_watchdog_timeouts, "Tx watchdog timeouts"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx_defrag_packets", CTLFLAG_RD, &sc->tx_defrag_packets, "Tx defragmented packets"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "no_tx_desc_avail", CTLFLAG_RD, &sc->no_tx_desc_avail, "no Tx descriptors available"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx_mbuf_alloc_errors", CTLFLAG_RD, &sc->rx_mbuf_alloc_errors, "Rx mbuf allocation errors"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx_mbuf_dmamap_errors", CTLFLAG_RD, &sc->rx_mbuf_dmamap_errors, "Rx mbuf DMA mapping errors"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx_queue_0_not_empty", CTLFLAG_RD, &sc->tx_queue_not_empty[0], "Tx queue 0 not empty"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx_queue_1_not_empty", CTLFLAG_RD, &sc->tx_queue_not_empty[1], "Tx queue 1 not empty"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx_packets", CTLFLAG_RD, &sc->rx_packets, "Rx packets"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx_crc_errors", CTLFLAG_RD, &sc->rx_crc_err, "Rx CRC errors"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx_phy_errors", CTLFLAG_RD, &sc->rx_phy_err, "Rx PHY errors"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx_dup_packets", CTLFLAG_RD, &sc->rx_dup_packets, "Rx duplicate packets"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx_fifo_overflows", CTLFLAG_RD, &sc->rx_fifo_overflows, "Rx FIFO overflows"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx_bytes", CTLFLAG_RD, &sc->rx_bytes, "Rx bytes"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx_long_err", CTLFLAG_RD, &sc->rx_long_err, "Rx too long frame errors"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx_short_err", CTLFLAG_RD, &sc->rx_short_err, "Rx too short frame errors"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx_bytes", CTLFLAG_RD, &sc->tx_bytes, "Tx bytes"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx_packets", CTLFLAG_RD, &sc->tx_packets, "Tx packets"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx_skip", CTLFLAG_RD, &sc->tx_skip, "Tx skip count for GDMA ports"); SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx_collision", CTLFLAG_RD, &sc->tx_collision, "Tx collision count for GDMA ports"); } #ifdef IF_RT_PHY_SUPPORT static int rt_miibus_readreg(device_t dev, int phy, int reg) { struct rt_softc *sc = device_get_softc(dev); /* * PSEUDO_PHYAD is a special value for indicate switch attached. * No one PHY use PSEUDO_PHYAD (0x1e) address. */ if (phy == 31) { /* Fake PHY ID for bfeswitch attach */ switch (reg) { case MII_BMSR: return (BMSR_EXTSTAT|BMSR_MEDIAMASK); case MII_PHYIDR1: return (0x40); /* As result of faking */ case MII_PHYIDR2: /* PHY will detect as */ return (0x6250); /* bfeswitch */ } } /* Wait prev command done if any */ while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO); RT_WRITE(sc, MDIO_ACCESS, MDIO_CMD_ONGO || ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) || ((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK)); while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO); return (RT_READ(sc, MDIO_ACCESS) & MDIO_PHY_DATA_MASK); } static int rt_miibus_writereg(device_t dev, int phy, int reg, int val) { struct rt_softc *sc = device_get_softc(dev); /* Wait prev command done if any */ while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO); RT_WRITE(sc, MDIO_ACCESS, MDIO_CMD_ONGO || MDIO_CMD_WR || ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) || ((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK) || (val & MDIO_PHY_DATA_MASK)); while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO); return (0); } void rt_miibus_statchg(device_t dev) { struct rt_softc *sc = device_get_softc(dev); struct mii_data *mii; mii = device_get_softc(sc->rt_miibus); if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == (IFM_ACTIVE | IFM_AVALID)) { switch (IFM_SUBTYPE(mii->mii_media_active)) { case IFM_10_T: case IFM_100_TX: /* XXX check link here */ sc->flags |= 1; break; default: break; } } } #endif /* IF_RT_PHY_SUPPORT */ static device_method_t rt_dev_methods[] = { DEVMETHOD(device_probe, rt_probe), DEVMETHOD(device_attach, rt_attach), DEVMETHOD(device_detach, rt_detach), DEVMETHOD(device_shutdown, rt_shutdown), DEVMETHOD(device_suspend, rt_suspend), DEVMETHOD(device_resume, rt_resume), #ifdef IF_RT_PHY_SUPPORT /* MII interface */ DEVMETHOD(miibus_readreg, rt_miibus_readreg), DEVMETHOD(miibus_writereg, rt_miibus_writereg), DEVMETHOD(miibus_statchg, rt_miibus_statchg), #endif DEVMETHOD_END }; static driver_t rt_driver = { "rt", rt_dev_methods, sizeof(struct rt_softc) }; static devclass_t rt_dev_class; DRIVER_MODULE(rt, nexus, rt_driver, rt_dev_class, 0, 0); #ifdef FDT DRIVER_MODULE(rt, simplebus, rt_driver, rt_dev_class, 0, 0); #endif MODULE_DEPEND(rt, ether, 1, 1, 1); MODULE_DEPEND(rt, miibus, 1, 1, 1); Index: head/sys/mips/mediatek/mtk_ehci.c =================================================================== --- head/sys/mips/mediatek/mtk_ehci.c (revision 298058) +++ head/sys/mips/mediatek/mtk_ehci.c (revision 298059) @@ -1,223 +1,223 @@ #include __FBSDID("$FreeBSD$"); /*- * Copyright (c) 2015 Stanislav Galabov. All rights reserved. * Copyright (c) 2010,2011 Aleksandr Rybalko. All rights reserved. * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define EHCI_HC_DEVSTR "MTK USB 2.0 Controller" static device_probe_t ehci_fdt_probe; static device_attach_t ehci_fdt_attach; static device_detach_t ehci_fdt_detach; static int ehci_fdt_probe(device_t self) { if (!ofw_bus_status_okay(self)) return (ENXIO); - if (!ofw_bus_is_compatible(self, "ralink,rt3xxx-ehci")) + if (!ofw_bus_is_compatible(self, "generic-ehci")) return (ENXIO); device_set_desc(self, EHCI_HC_DEVSTR); return (BUS_PROBE_DEFAULT); } static int ehci_fdt_attach(device_t self) { ehci_softc_t *sc = device_get_softc(self); int err; int rid; /* initialise some bus fields */ sc->sc_bus.parent = self; sc->sc_bus.devices = sc->sc_devices; sc->sc_bus.devices_max = EHCI_MAX_DEVICES; sc->sc_bus.dma_bits = 32; /* get all DMA memory */ if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) { printf("No mem\n"); return (ENOMEM); } rid = 0; sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_io_res) { device_printf(self, "Could not map memory\n"); goto error; } sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); sc->sc_io_size = rman_get_size(sc->sc_io_res); rid = 0; sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); if (sc->sc_irq_res == NULL) { device_printf(self, "Could not allocate irq\n"); goto error; } sc->sc_bus.bdev = device_add_child(self, "usbus", -1); if (!(sc->sc_bus.bdev)) { device_printf(self, "Could not add USB device\n"); goto error; } device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); device_set_desc(sc->sc_bus.bdev, EHCI_HC_DEVSTR); sprintf(sc->sc_vendor, "MediaTek"); err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl); if (err) { device_printf(self, "Could not setup irq, %d\n", err); sc->sc_intr_hdl = NULL; goto error; } err = ehci_init(sc); if (!err) { err = device_probe_and_attach(sc->sc_bus.bdev); } if (err) { device_printf(self, "USB init failed err=%d\n", err); goto error; } return (0); error: ehci_fdt_detach(self); return (ENXIO); } static int ehci_fdt_detach(device_t self) { ehci_softc_t *sc = device_get_softc(self); device_t bdev; int err; if (sc->sc_bus.bdev) { bdev = sc->sc_bus.bdev; device_detach(bdev); device_delete_child(self, bdev); } /* during module unload there are lots of children leftover */ device_delete_children(self); if (sc->sc_irq_res && sc->sc_intr_hdl) { /* * only call ehci_detach() after ehci_init() */ ehci_detach(sc); err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); if (err) device_printf(self, "Could not tear down irq, %d\n", err); sc->sc_intr_hdl = NULL; } if (sc->sc_irq_res) { bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res); sc->sc_irq_res = NULL; } if (sc->sc_io_res) { bus_release_resource(self, SYS_RES_MEMORY, 0, sc->sc_io_res); sc->sc_io_res = NULL; } usb_bus_mem_free_all(&sc->sc_bus, &ehci_iterate_hw_softc); return (0); } static device_method_t ehci_fdt_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ehci_fdt_probe), DEVMETHOD(device_attach, ehci_fdt_attach), DEVMETHOD(device_detach, ehci_fdt_detach), DEVMETHOD(device_suspend, bus_generic_suspend), DEVMETHOD(device_resume, bus_generic_resume), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD_END }; static driver_t ehci_fdt_driver = { .name = "ehci", .methods = ehci_fdt_methods, .size = sizeof(ehci_softc_t), }; static devclass_t ehci_fdt_devclass; DRIVER_MODULE(ehci, simplebus, ehci_fdt_driver, ehci_fdt_devclass, 0, 0); Index: head/sys/mips/mediatek/mtk_gpio_v1.c =================================================================== --- head/sys/mips/mediatek/mtk_gpio_v1.c (revision 298058) +++ head/sys/mips/mediatek/mtk_gpio_v1.c (revision 298059) @@ -1,675 +1,675 @@ /*- * Copyright 2016 Stanislav Galabov * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_platform.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "gpio_if.h" #include "pic_if.h" #define MTK_GPIO_PINS 32 struct mtk_gpio_pin_irqsrc { struct intr_irqsrc isrc; u_int irq; }; struct mtk_gpio_pin { uint32_t pin_caps; uint32_t pin_flags; enum intr_trigger intr_trigger; enum intr_polarity intr_polarity; char pin_name[GPIOMAXNAME]; struct mtk_gpio_pin_irqsrc pin_irqsrc; }; struct mtk_gpio_softc { device_t dev; device_t busdev; struct resource *res[2]; struct mtx mtx; struct mtk_gpio_pin pins[MTK_GPIO_PINS]; void *intrhand; uint32_t num_pins; uint8_t do_remap; }; #define PIC_INTR_ISRC(sc, irq) (&(sc)->pins[(irq)].pin_irqsrc.isrc) static struct resource_spec mtk_gpio_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, { -1, 0 } }; static int mtk_gpio_probe(device_t dev); static int mtk_gpio_attach(device_t dev); static int mtk_gpio_detach(device_t dev); static int mtk_gpio_intr(void *arg); #define MTK_GPIO_LOCK(sc) mtx_lock_spin(&(sc)->mtx) #define MTK_GPIO_UNLOCK(sc) mtx_unlock_spin(&(sc)->mtx) #define MTK_GPIO_LOCK_INIT(sc) \ mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \ "mtk_gpio", MTX_SPIN) #define MTK_GPIO_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) #define MTK_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) #define MTK_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg)) /* Register definitions */ #define GPIO_PIOINT(_sc) 0x0000 #define GPIO_PIOEDGE(_sc) 0x0004 #define GPIO_PIORENA(_sc) 0x0008 #define GPIO_PIOFENA(_sc) 0x000C #define GPIO_PIODATA(_sc) ((_sc)->do_remap ? 0x0020 : 0x0010) #define GPIO_PIODIR(_sc) ((_sc)->do_remap ? 0x0024 : 0x0014) #define GPIO_PIOPOL(_sc) ((_sc)->do_remap ? 0x0028 : 0x0018) #define GPIO_PIOSET(_sc) ((_sc)->do_remap ? 0x002C : 0x001C) #define GPIO_PIORESET(_sc) ((_sc)->do_remap ? 0x0030 : 0x0020) #define GPIO_PIOTOG(_sc) ((_sc)->do_remap ? 0x0034 : 0x0024) static struct ofw_compat_data compat_data[] = { { "ralink,rt2880-gpio", 1 }, { "ralink,rt3050-gpio", 1 }, { "ralink,rt3352-gpio", 1 }, { "ralink,rt3883-gpio", 1 }, { "ralink,rt5350-gpio", 1 }, { "ralink,mt7620a-gpio", 1 }, { NULL, 0 } }; static int mtk_gpio_probe(device_t dev) { phandle_t node; if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); node = ofw_bus_get_node(dev); if (!OF_hasprop(node, "gpio-controller")) return (ENXIO); device_set_desc(dev, "MTK GPIO Controller (v1)"); return (BUS_PROBE_DEFAULT); } static int mtk_pic_register_isrcs(struct mtk_gpio_softc *sc) { int error; uint32_t irq; struct intr_irqsrc *isrc; const char *name; name = device_get_nameunit(sc->dev); for (irq = 0; irq < sc->num_pins; irq++) { sc->pins[irq].pin_irqsrc.irq = irq; isrc = PIC_INTR_ISRC(sc, irq); error = intr_isrc_register(isrc, sc->dev, 0, "%s", name); if (error != 0) { /* XXX call intr_isrc_deregister */ device_printf(sc->dev, "%s failed", __func__); return (error); } } return (0); } static int mtk_gpio_pin_set_direction(struct mtk_gpio_softc *sc, uint32_t pin, uint32_t dir) { uint32_t regval, mask = (1u << pin); if (!(sc->pins[pin].pin_caps & dir)) return (EINVAL); regval = MTK_READ_4(sc, GPIO_PIODIR(sc)); if (dir == GPIO_PIN_INPUT) regval &= ~mask; else regval |= mask; MTK_WRITE_4(sc, GPIO_PIODIR(sc), regval); sc->pins[pin].pin_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); sc->pins[pin].pin_flags |= dir; return (0); } static int mtk_gpio_pin_set_invert(struct mtk_gpio_softc *sc, uint32_t pin, uint32_t val) { uint32_t regval, mask = (1u << pin); regval = MTK_READ_4(sc, GPIO_PIOPOL(sc)); if (val) regval |= mask; else regval &= ~mask; MTK_WRITE_4(sc, GPIO_PIOPOL(sc), regval); sc->pins[pin].pin_flags &= ~(GPIO_PIN_INVIN | GPIO_PIN_INVOUT); sc->pins[pin].pin_flags |= val; return (0); } static void mtk_gpio_pin_probe(struct mtk_gpio_softc *sc, uint32_t pin) { uint32_t mask = (1u << pin); uint32_t val; /* Clear cached gpio config */ sc->pins[pin].pin_flags = 0; val = MTK_READ_4(sc, GPIO_PIORENA(sc)) | MTK_READ_4(sc, GPIO_PIOFENA(sc)); if (val & mask) { /* Pin is in interrupt mode */ sc->pins[pin].intr_trigger = INTR_TRIGGER_EDGE; val = MTK_READ_4(sc, GPIO_PIORENA(sc)); if (val & mask) sc->pins[pin].intr_polarity = INTR_POLARITY_HIGH; else sc->pins[pin].intr_polarity = INTR_POLARITY_LOW; } val = MTK_READ_4(sc, GPIO_PIODIR(sc)); if (val & mask) sc->pins[pin].pin_flags |= GPIO_PIN_OUTPUT; else sc->pins[pin].pin_flags |= GPIO_PIN_INPUT; val = MTK_READ_4(sc, GPIO_PIOPOL(sc)); if (val & mask) { if (sc->pins[pin].pin_flags & GPIO_PIN_INPUT) { sc->pins[pin].pin_flags |= GPIO_PIN_INVIN; } else { sc->pins[pin].pin_flags |= GPIO_PIN_INVOUT; } } } static int mtk_gpio_attach(device_t dev) { struct mtk_gpio_softc *sc; phandle_t node; uint32_t i, num_pins; sc = device_get_softc(dev); sc->dev = dev; if (bus_alloc_resources(dev, mtk_gpio_spec, sc->res)) { device_printf(dev, "could not allocate resources for device\n"); return (ENXIO); } MTK_GPIO_LOCK_INIT(sc); node = ofw_bus_get_node(dev); if (OF_hasprop(node, "clocks")) mtk_soc_start_clock(dev); if (OF_hasprop(node, "resets")) mtk_soc_reset_device(dev); if (OF_hasprop(node, "mtk,register-gap")) { device_printf(dev, "\n"); sc->do_remap = 1; } else { device_printf(dev, "\n"); sc->do_remap = 0; } - if (OF_hasprop(node, "mtk,num-pins") && (OF_getencprop(node, - "mtk,num-pins", &num_pins, sizeof(num_pins)) >= 0)) + if (OF_hasprop(node, "ralink,num-gpios") && (OF_getencprop(node, + "ralink,num-gpios", &num_pins, sizeof(num_pins)) >= 0)) sc->num_pins = num_pins; else sc->num_pins = MTK_GPIO_PINS; for (i = 0; i < num_pins; i++) { sc->pins[i].pin_caps |= GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_INVIN | GPIO_PIN_INVOUT; sc->pins[i].intr_polarity = INTR_POLARITY_HIGH; sc->pins[i].intr_trigger = INTR_TRIGGER_EDGE; snprintf(sc->pins[i].pin_name, GPIOMAXNAME - 1, "gpio%c%d", device_get_unit(dev) + 'a', i); sc->pins[i].pin_name[GPIOMAXNAME - 1] = '\0'; mtk_gpio_pin_probe(sc, i); } if (mtk_pic_register_isrcs(sc) != 0) { device_printf(dev, "could not register PIC ISRCs\n"); goto fail; } if (intr_pic_register(dev, OF_xref_from_node(node)) != 0) { device_printf(dev, "could not register PIC\n"); goto fail; } if (bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE, mtk_gpio_intr, NULL, sc, &sc->intrhand) != 0) goto fail_pic; sc->busdev = gpiobus_attach_bus(dev); if (sc->busdev == NULL) goto fail_pic; return (0); fail_pic: intr_pic_deregister(dev, OF_xref_from_node(node)); fail: if(sc->intrhand != NULL) bus_teardown_intr(dev, sc->res[1], sc->intrhand); bus_release_resources(dev, mtk_gpio_spec, sc->res); MTK_GPIO_LOCK_DESTROY(sc); return (ENXIO); } static int mtk_gpio_detach(device_t dev) { struct mtk_gpio_softc *sc = device_get_softc(dev); phandle_t node; node = ofw_bus_get_node(dev); intr_pic_deregister(dev, OF_xref_from_node(node)); if (sc->intrhand != NULL) bus_teardown_intr(dev, sc->res[1], sc->intrhand); bus_release_resources(dev, mtk_gpio_spec, sc->res); MTK_GPIO_LOCK_DESTROY(sc); return (0); } static device_t mtk_gpio_get_bus(device_t dev) { struct mtk_gpio_softc *sc = device_get_softc(dev); return (sc->busdev); } static int mtk_gpio_pin_max(device_t dev, int *maxpin) { struct mtk_gpio_softc *sc = device_get_softc(dev); *maxpin = sc->num_pins - 1; return (0); } static int mtk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) { struct mtk_gpio_softc *sc = device_get_softc(dev); if (pin >= sc->num_pins) return (EINVAL); MTK_GPIO_LOCK(sc); *caps = sc->pins[pin].pin_caps; MTK_GPIO_UNLOCK(sc); return (0); } static int mtk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) { struct mtk_gpio_softc *sc = device_get_softc(dev); if (pin >= sc->num_pins) return (EINVAL); MTK_GPIO_LOCK(sc); *flags = sc->pins[pin].pin_flags; MTK_GPIO_UNLOCK(sc); return (0); } static int mtk_gpio_pin_getname(device_t dev, uint32_t pin, char *name) { struct mtk_gpio_softc *sc = device_get_softc(dev); if (pin >= sc->num_pins) return (EINVAL); strncpy(name, sc->pins[pin].pin_name, GPIOMAXNAME - 1); name[GPIOMAXNAME - 1] = '\0'; return (0); } static int mtk_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) { struct mtk_gpio_softc *sc; int retval; sc = device_get_softc(dev); if (pin >= sc->num_pins) return (EINVAL); MTK_GPIO_LOCK(sc); retval = mtk_gpio_pin_set_direction(sc, pin, flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)); if (retval == 0) retval = mtk_gpio_pin_set_invert(sc, pin, flags & (GPIO_PIN_INVIN | GPIO_PIN_INVOUT)); MTK_GPIO_UNLOCK(sc); return (retval); } static int mtk_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) { struct mtk_gpio_softc *sc; int ret; sc = device_get_softc(dev); ret = 0; if (pin >= sc->num_pins) return (EINVAL); MTK_GPIO_LOCK(sc); if(!(sc->pins[pin].pin_flags & GPIO_PIN_OUTPUT)) { ret = EINVAL; goto out; } if (value) MTK_WRITE_4(sc, GPIO_PIOSET(sc), (1u << pin)); else MTK_WRITE_4(sc, GPIO_PIORESET(sc), (1u << pin)); out: MTK_GPIO_UNLOCK(sc); return (ret); } static int mtk_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) { struct mtk_gpio_softc *sc; uint32_t data; int ret; sc = device_get_softc(dev); ret = 0; if (pin >= sc->num_pins) return (EINVAL); MTK_GPIO_LOCK(sc); if(!(sc->pins[pin].pin_flags & GPIO_PIN_INPUT)) { ret = EINVAL; goto out; } data = MTK_READ_4(sc, GPIO_PIODATA(sc)); *val = (data & (1u << pin)) ? 1 : 0; out: MTK_GPIO_UNLOCK(sc); return (ret); } static int mtk_gpio_pin_toggle(device_t dev, uint32_t pin) { struct mtk_gpio_softc *sc; int ret; if (pin >= sc->num_pins) return (EINVAL); sc = device_get_softc(dev); ret = 0; MTK_GPIO_LOCK(sc); if (!(sc->pins[pin].pin_flags & GPIO_PIN_OUTPUT)) { ret = EINVAL; goto out; } MTK_WRITE_4(sc, GPIO_PIOTOG(sc), (1u << pin)); out: MTK_GPIO_UNLOCK(sc); return (ret); } static int mtk_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, struct intr_irqsrc **isrcp) { struct mtk_gpio_softc *sc; sc = device_get_softc(dev); if (data == NULL || data->type != INTR_MAP_DATA_FDT || data->fdt.ncells != 1 || data->fdt.cells[0] >= sc->num_pins) return (EINVAL); *isrcp = PIC_INTR_ISRC(sc, data->fdt.cells[0]); return (0); } static void mtk_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) { struct mtk_gpio_softc *sc; struct mtk_gpio_pin_irqsrc *pisrc; uint32_t pin, mask, val; sc = device_get_softc(dev); pisrc = (struct mtk_gpio_pin_irqsrc *)isrc; pin = pisrc->irq; mask = 1u << pin; MTK_GPIO_LOCK(sc); if (sc->pins[pin].intr_polarity == INTR_POLARITY_LOW) { val = MTK_READ_4(sc, GPIO_PIORENA(sc)) & ~mask; MTK_WRITE_4(sc, GPIO_PIORENA(sc), val); val = MTK_READ_4(sc, GPIO_PIOFENA(sc)) | mask; MTK_WRITE_4(sc, GPIO_PIOFENA(sc), val); } else { val = MTK_READ_4(sc, GPIO_PIOFENA(sc)) & ~mask; MTK_WRITE_4(sc, GPIO_PIOFENA(sc), val); val = MTK_READ_4(sc, GPIO_PIORENA(sc)) | mask; MTK_WRITE_4(sc, GPIO_PIORENA(sc), val); } MTK_GPIO_UNLOCK(sc); } static void mtk_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) { struct mtk_gpio_softc *sc; struct mtk_gpio_pin_irqsrc *pisrc; uint32_t pin, mask, val; sc = device_get_softc(dev); pisrc = (struct mtk_gpio_pin_irqsrc *)isrc; pin = pisrc->irq; mask = 1u << pin; MTK_GPIO_LOCK(sc); val = MTK_READ_4(sc, GPIO_PIORENA(sc)) & ~mask; MTK_WRITE_4(sc, GPIO_PIORENA(sc), val); val = MTK_READ_4(sc, GPIO_PIOFENA(sc)) & ~mask; MTK_WRITE_4(sc, GPIO_PIOFENA(sc), val); MTK_GPIO_UNLOCK(sc); } static void mtk_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) { mtk_gpio_pic_disable_intr(dev, isrc); } static void mtk_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) { mtk_gpio_pic_enable_intr(dev, isrc); } static void mtk_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) { struct mtk_gpio_softc *sc; struct mtk_gpio_pin_irqsrc *pisrc; pisrc = (struct mtk_gpio_pin_irqsrc *)isrc; sc = device_get_softc(dev); MTK_GPIO_LOCK(sc); MTK_WRITE_4(sc, GPIO_PIOINT(sc), 1u << pisrc->irq); MTK_GPIO_UNLOCK(sc); } static int mtk_gpio_intr(void *arg) { struct mtk_gpio_softc *sc; uint32_t i, interrupts; sc = arg; interrupts = MTK_READ_4(sc, GPIO_PIOINT(sc)); for (i = 0; interrupts != 0; i++, interrupts >>= 1) { if ((interrupts & 0x1) == 0) continue; if (intr_isrc_dispatch(PIC_INTR_ISRC(sc, i), curthread->td_intr_frame) != 0) { device_printf(sc->dev, "spurious interrupt %d\n", i); } } return (FILTER_HANDLED); } static phandle_t mtk_gpio_get_node(device_t bus, device_t dev) { /* We only have one child, the GPIO bus, which needs our own node. */ return (ofw_bus_get_node(bus)); } static device_method_t mtk_gpio_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mtk_gpio_probe), DEVMETHOD(device_attach, mtk_gpio_attach), DEVMETHOD(device_detach, mtk_gpio_detach), /* GPIO protocol */ DEVMETHOD(gpio_get_bus, mtk_gpio_get_bus), DEVMETHOD(gpio_pin_max, mtk_gpio_pin_max), DEVMETHOD(gpio_pin_getname, mtk_gpio_pin_getname), DEVMETHOD(gpio_pin_getflags, mtk_gpio_pin_getflags), DEVMETHOD(gpio_pin_getcaps, mtk_gpio_pin_getcaps), DEVMETHOD(gpio_pin_setflags, mtk_gpio_pin_setflags), DEVMETHOD(gpio_pin_get, mtk_gpio_pin_get), DEVMETHOD(gpio_pin_set, mtk_gpio_pin_set), DEVMETHOD(gpio_pin_toggle, mtk_gpio_pin_toggle), /* Interrupt controller interface */ DEVMETHOD(pic_disable_intr, mtk_gpio_pic_disable_intr), DEVMETHOD(pic_enable_intr, mtk_gpio_pic_enable_intr), DEVMETHOD(pic_map_intr, mtk_gpio_pic_map_intr), DEVMETHOD(pic_post_filter, mtk_gpio_pic_post_filter), DEVMETHOD(pic_post_ithread, mtk_gpio_pic_post_ithread), DEVMETHOD(pic_pre_ithread, mtk_gpio_pic_pre_ithread), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, mtk_gpio_get_node), DEVMETHOD_END }; static driver_t mtk_gpio_driver = { "gpio", mtk_gpio_methods, sizeof(struct mtk_gpio_softc), }; static devclass_t mtk_gpio_devclass; EARLY_DRIVER_MODULE(mtk_gpio_v1, simplebus, mtk_gpio_driver, mtk_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); Index: head/sys/mips/mediatek/mtk_gpio_v2.c =================================================================== --- head/sys/mips/mediatek/mtk_gpio_v2.c (revision 298058) +++ head/sys/mips/mediatek/mtk_gpio_v2.c (revision 298059) @@ -1,675 +1,675 @@ /*- * Copyright 2016 Stanislav Galabov * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_platform.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "gpio_if.h" #include "pic_if.h" #define MTK_GPIO_PINS 32 struct mtk_gpio_pin_irqsrc { struct intr_irqsrc isrc; u_int irq; }; struct mtk_gpio_pin { uint32_t pin_caps; uint32_t pin_flags; enum intr_trigger intr_trigger; enum intr_polarity intr_polarity; char pin_name[GPIOMAXNAME]; struct mtk_gpio_pin_irqsrc pin_irqsrc; }; struct mtk_gpio_softc { device_t dev; device_t busdev; struct resource *res[2]; struct mtx mtx; struct mtk_gpio_pin pins[MTK_GPIO_PINS]; void *intrhand; uint32_t num_pins; uint32_t bank_id; }; #define PIC_INTR_ISRC(sc, irq) (&(sc)->pins[(irq)].pin_irqsrc.isrc) static struct resource_spec mtk_gpio_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE | RF_SHAREABLE }, { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, { -1, 0 } }; static int mtk_gpio_probe(device_t dev); static int mtk_gpio_attach(device_t dev); static int mtk_gpio_detach(device_t dev); static int mtk_gpio_intr(void *arg); #define MTK_GPIO_LOCK(sc) mtx_lock_spin(&(sc)->mtx) #define MTK_GPIO_UNLOCK(sc) mtx_unlock_spin(&(sc)->mtx) #define MTK_GPIO_LOCK_INIT(sc) \ mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \ "mtk_gpio", MTX_SPIN) #define MTK_GPIO_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) #define MTK_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) #define MTK_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg)) /* Register definitions */ #define GPIO_REG(_sc, _reg) ((_reg) + (_sc)->bank_id * 0x4) #define GPIO_PIOINT(_sc) GPIO_REG((_sc), 0x0090) #define GPIO_PIOEDGE(_sc) GPIO_REG((_sc), 0x00A0) #define GPIO_PIORENA(_sc) GPIO_REG((_sc), 0x0050) #define GPIO_PIOFENA(_sc) GPIO_REG((_sc), 0x0060) #define GPIO_PIODATA(_sc) GPIO_REG((_sc), 0x0020) #define GPIO_PIODIR(_sc) GPIO_REG((_sc), 0x0000) #define GPIO_PIOPOL(_sc) GPIO_REG((_sc), 0x0010) #define GPIO_PIOSET(_sc) GPIO_REG((_sc), 0x0030) #define GPIO_PIORESET(_sc) GPIO_REG((_sc), 0x0040) static struct ofw_compat_data compat_data[] = { - { "mtk,mt7621-gpio", 1 }, - { "mtk,mt7628-gpio", 1 }, + { "mtk,mt7621-gpio-bank", 1 }, + { "mtk,mt7628-gpio-bank", 1 }, { NULL, 0 } }; static int mtk_gpio_probe(device_t dev) { phandle_t node; if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); node = ofw_bus_get_node(dev); if (!OF_hasprop(node, "gpio-controller")) return (ENXIO); device_set_desc(dev, "MTK GPIO Controller (v2)"); return (BUS_PROBE_DEFAULT); } static int mtk_pic_register_isrcs(struct mtk_gpio_softc *sc) { int error; uint32_t irq; struct intr_irqsrc *isrc; const char *name; name = device_get_nameunit(sc->dev); for (irq = 0; irq < sc->num_pins; irq++) { sc->pins[irq].pin_irqsrc.irq = irq; isrc = PIC_INTR_ISRC(sc, irq); error = intr_isrc_register(isrc, sc->dev, 0, "%s", name); if (error != 0) { /* XXX call intr_isrc_deregister */ device_printf(sc->dev, "%s failed", __func__); return (error); } } return (0); } static int mtk_gpio_pin_set_direction(struct mtk_gpio_softc *sc, uint32_t pin, uint32_t dir) { uint32_t regval, mask = (1u << pin); if (!(sc->pins[pin].pin_caps & dir)) return (EINVAL); regval = MTK_READ_4(sc, GPIO_PIODIR(sc)); if (dir == GPIO_PIN_INPUT) regval &= ~mask; else regval |= mask; MTK_WRITE_4(sc, GPIO_PIODIR(sc), regval); sc->pins[pin].pin_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); sc->pins[pin].pin_flags |= dir; return (0); } static int mtk_gpio_pin_set_invert(struct mtk_gpio_softc *sc, uint32_t pin, uint32_t val) { uint32_t regval, mask = (1u << pin); regval = MTK_READ_4(sc, GPIO_PIOPOL(sc)); if (val) regval |= mask; else regval &= ~mask; MTK_WRITE_4(sc, GPIO_PIOPOL(sc), regval); sc->pins[pin].pin_flags &= ~(GPIO_PIN_INVIN | GPIO_PIN_INVOUT); sc->pins[pin].pin_flags |= val; return (0); } static void mtk_gpio_pin_probe(struct mtk_gpio_softc *sc, uint32_t pin) { uint32_t mask = (1u << pin); uint32_t val; /* Clear cached gpio config */ sc->pins[pin].pin_flags = 0; val = MTK_READ_4(sc, GPIO_PIORENA(sc)) | MTK_READ_4(sc, GPIO_PIOFENA(sc)); if (val & mask) { /* Pin is in interrupt mode */ sc->pins[pin].intr_trigger = INTR_TRIGGER_EDGE; val = MTK_READ_4(sc, GPIO_PIORENA(sc)); if (val & mask) sc->pins[pin].intr_polarity = INTR_POLARITY_HIGH; else sc->pins[pin].intr_polarity = INTR_POLARITY_LOW; } val = MTK_READ_4(sc, GPIO_PIODIR(sc)); if (val & mask) sc->pins[pin].pin_flags |= GPIO_PIN_OUTPUT; else sc->pins[pin].pin_flags |= GPIO_PIN_INPUT; val = MTK_READ_4(sc, GPIO_PIOPOL(sc)); if (val & mask) { if (sc->pins[pin].pin_flags & GPIO_PIN_INPUT) { sc->pins[pin].pin_flags |= GPIO_PIN_INVIN; } else { sc->pins[pin].pin_flags |= GPIO_PIN_INVOUT; } } } static int mtk_gpio_attach(device_t dev) { struct mtk_gpio_softc *sc; phandle_t node; uint32_t i, num_pins, bank_id; sc = device_get_softc(dev); sc->dev = dev; if (bus_alloc_resources(dev, mtk_gpio_spec, sc->res)) { device_printf(dev, "could not allocate resources for device\n"); return (ENXIO); } MTK_GPIO_LOCK_INIT(sc); node = ofw_bus_get_node(dev); if (OF_hasprop(node, "clocks")) mtk_soc_start_clock(dev); if (OF_hasprop(node, "resets")) mtk_soc_reset_device(dev); if (OF_hasprop(node, "mtk,bank-id") && (OF_getencprop(node, "mtk,bank-id", &bank_id, sizeof(bank_id)) >= 0)) sc->bank_id = bank_id; else sc->bank_id = device_get_unit(dev); if (OF_hasprop(node, "mtk,num-pins") && (OF_getencprop(node, "mtk,num-pins", &num_pins, sizeof(num_pins)) >= 0)) sc->num_pins = num_pins; else sc->num_pins = MTK_GPIO_PINS; - for (i = 0; i < num_pins; i++) { + for (i = 0; i < sc->num_pins; i++) { sc->pins[i].pin_caps |= GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_INVIN | GPIO_PIN_INVOUT; sc->pins[i].intr_polarity = INTR_POLARITY_HIGH; sc->pins[i].intr_trigger = INTR_TRIGGER_EDGE; snprintf(sc->pins[i].pin_name, GPIOMAXNAME - 1, "gpio%c%d", device_get_unit(dev) + 'a', i); sc->pins[i].pin_name[GPIOMAXNAME - 1] = '\0'; mtk_gpio_pin_probe(sc, i); } if (mtk_pic_register_isrcs(sc) != 0) { device_printf(dev, "could not register PIC ISRCs\n"); goto fail; } if (intr_pic_register(dev, OF_xref_from_node(node)) != 0) { device_printf(dev, "could not register PIC\n"); goto fail; } if (bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE, mtk_gpio_intr, NULL, sc, &sc->intrhand) != 0) goto fail_pic; sc->busdev = gpiobus_attach_bus(dev); if (sc->busdev == NULL) goto fail_pic; return (0); fail_pic: intr_pic_deregister(dev, OF_xref_from_node(node)); fail: if(sc->intrhand != NULL) bus_teardown_intr(dev, sc->res[1], sc->intrhand); bus_release_resources(dev, mtk_gpio_spec, sc->res); MTK_GPIO_LOCK_DESTROY(sc); return (ENXIO); } static int mtk_gpio_detach(device_t dev) { struct mtk_gpio_softc *sc = device_get_softc(dev); phandle_t node; node = ofw_bus_get_node(dev); intr_pic_deregister(dev, OF_xref_from_node(node)); if (sc->intrhand != NULL) bus_teardown_intr(dev, sc->res[1], sc->intrhand); bus_release_resources(dev, mtk_gpio_spec, sc->res); MTK_GPIO_LOCK_DESTROY(sc); return (0); } static device_t mtk_gpio_get_bus(device_t dev) { struct mtk_gpio_softc *sc = device_get_softc(dev); return (sc->busdev); } static int mtk_gpio_pin_max(device_t dev, int *maxpin) { struct mtk_gpio_softc *sc = device_get_softc(dev); *maxpin = sc->num_pins - 1; return (0); } static int mtk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) { struct mtk_gpio_softc *sc = device_get_softc(dev); if (pin >= sc->num_pins) return (EINVAL); MTK_GPIO_LOCK(sc); *caps = sc->pins[pin].pin_caps; MTK_GPIO_UNLOCK(sc); return (0); } static int mtk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) { struct mtk_gpio_softc *sc = device_get_softc(dev); if (pin >= sc->num_pins) return (EINVAL); MTK_GPIO_LOCK(sc); *flags = sc->pins[pin].pin_flags; MTK_GPIO_UNLOCK(sc); return (0); } static int mtk_gpio_pin_getname(device_t dev, uint32_t pin, char *name) { struct mtk_gpio_softc *sc = device_get_softc(dev); if (pin >= sc->num_pins) return (EINVAL); strncpy(name, sc->pins[pin].pin_name, GPIOMAXNAME - 1); name[GPIOMAXNAME - 1] = '\0'; return (0); } static int mtk_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) { struct mtk_gpio_softc *sc; int retval; sc = device_get_softc(dev); if (pin >= sc->num_pins) return (EINVAL); MTK_GPIO_LOCK(sc); retval = mtk_gpio_pin_set_direction(sc, pin, flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)); if (retval == 0) retval = mtk_gpio_pin_set_invert(sc, pin, flags & (GPIO_PIN_INVIN | GPIO_PIN_INVOUT)); MTK_GPIO_UNLOCK(sc); return (retval); } static int mtk_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) { struct mtk_gpio_softc *sc; int ret; if (pin >= sc->num_pins) return (EINVAL); sc = device_get_softc(dev); ret = 0; MTK_GPIO_LOCK(sc); if (!(sc->pins[pin].pin_flags & GPIO_PIN_OUTPUT)) { ret = EINVAL; goto out; } if (value) MTK_WRITE_4(sc, GPIO_PIOSET(sc), (1u << pin)); else MTK_WRITE_4(sc, GPIO_PIORESET(sc), (1u << pin)); out: MTK_GPIO_UNLOCK(sc); return (ret); } static int mtk_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) { struct mtk_gpio_softc *sc; uint32_t data; int ret; if (pin >= sc->num_pins) return (EINVAL); sc = device_get_softc(dev); ret = 0; MTK_GPIO_LOCK(sc); if (!(sc->pins[pin].pin_flags & GPIO_PIN_INPUT)) { ret = EINVAL; goto out; } data = MTK_READ_4(sc, GPIO_PIODATA(sc)); *val = (data & (1u << pin)) ? 1 : 0; out: MTK_GPIO_UNLOCK(sc); return (ret); } static int mtk_gpio_pin_toggle(device_t dev, uint32_t pin) { struct mtk_gpio_softc *sc; uint32_t val; int ret; if (pin >= sc->num_pins) return (EINVAL); sc = device_get_softc(dev); ret = 0; MTK_GPIO_LOCK(sc); if(!(sc->pins[pin].pin_flags & GPIO_PIN_OUTPUT)) { ret = EINVAL; goto out; } val = MTK_READ_4(sc, GPIO_PIODATA(sc)); val &= (1u << pin); if (val) MTK_WRITE_4(sc, GPIO_PIORESET(sc), (1u << pin)); else MTK_WRITE_4(sc, GPIO_PIOSET(sc), (1u << pin)); out: MTK_GPIO_UNLOCK(sc); return (ret); } static int mtk_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, struct intr_irqsrc **isrcp) { struct mtk_gpio_softc *sc; sc = device_get_softc(dev); if (data == NULL || data->type != INTR_MAP_DATA_FDT || data->fdt.ncells != 1 || data->fdt.cells[0] >= sc->num_pins) return (EINVAL); *isrcp = PIC_INTR_ISRC(sc, data->fdt.cells[0]); return (0); } static void mtk_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) { struct mtk_gpio_softc *sc; struct mtk_gpio_pin_irqsrc *pisrc; uint32_t pin, mask, val; sc = device_get_softc(dev); pisrc = (struct mtk_gpio_pin_irqsrc *)isrc; pin = pisrc->irq; mask = 1u << pin; MTK_GPIO_LOCK(sc); if (sc->pins[pin].intr_polarity == INTR_POLARITY_LOW) { val = MTK_READ_4(sc, GPIO_PIORENA(sc)) & ~mask; MTK_WRITE_4(sc, GPIO_PIORENA(sc), val); val = MTK_READ_4(sc, GPIO_PIOFENA(sc)) | mask; MTK_WRITE_4(sc, GPIO_PIOFENA(sc), val); } else { val = MTK_READ_4(sc, GPIO_PIOFENA(sc)) & ~mask; MTK_WRITE_4(sc, GPIO_PIOFENA(sc), val); val = MTK_READ_4(sc, GPIO_PIORENA(sc)) | mask; MTK_WRITE_4(sc, GPIO_PIORENA(sc), val); } MTK_GPIO_UNLOCK(sc); } static void mtk_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) { struct mtk_gpio_softc *sc; struct mtk_gpio_pin_irqsrc *pisrc; uint32_t pin, mask, val; sc = device_get_softc(dev); pisrc = (struct mtk_gpio_pin_irqsrc *)isrc; pin = pisrc->irq; mask = 1u << pin; MTK_GPIO_LOCK(sc); val = MTK_READ_4(sc, GPIO_PIORENA(sc)) & ~mask; MTK_WRITE_4(sc, GPIO_PIORENA(sc), val); val = MTK_READ_4(sc, GPIO_PIOFENA(sc)) & ~mask; MTK_WRITE_4(sc, GPIO_PIOFENA(sc), val); MTK_GPIO_UNLOCK(sc); } static void mtk_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) { mtk_gpio_pic_disable_intr(dev, isrc); } static void mtk_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) { mtk_gpio_pic_enable_intr(dev, isrc); } static void mtk_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) { struct mtk_gpio_softc *sc; struct mtk_gpio_pin_irqsrc *pisrc; pisrc = (struct mtk_gpio_pin_irqsrc *)isrc; sc = device_get_softc(dev); MTK_GPIO_LOCK(sc); MTK_WRITE_4(sc, GPIO_PIOINT(sc), 1u << pisrc->irq); MTK_GPIO_UNLOCK(sc); } static int mtk_gpio_intr(void *arg) { struct mtk_gpio_softc *sc; uint32_t i, interrupts; sc = arg; interrupts = MTK_READ_4(sc, GPIO_PIOINT(sc)); for (i = 0; interrupts != 0; i++, interrupts >>= 1) { if ((interrupts & 0x1) == 0) continue; if (intr_isrc_dispatch(PIC_INTR_ISRC(sc, i), curthread->td_intr_frame) != 0) { device_printf(sc->dev, "spurious interrupt %d\n", i); } } return (FILTER_HANDLED); } static phandle_t mtk_gpio_get_node(device_t bus, device_t dev) { /* We only have one child, the GPIO bus, which needs our own node. */ return (ofw_bus_get_node(bus)); } static device_method_t mtk_gpio_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mtk_gpio_probe), DEVMETHOD(device_attach, mtk_gpio_attach), DEVMETHOD(device_detach, mtk_gpio_detach), /* GPIO protocol */ DEVMETHOD(gpio_get_bus, mtk_gpio_get_bus), DEVMETHOD(gpio_pin_max, mtk_gpio_pin_max), DEVMETHOD(gpio_pin_getname, mtk_gpio_pin_getname), DEVMETHOD(gpio_pin_getflags, mtk_gpio_pin_getflags), DEVMETHOD(gpio_pin_getcaps, mtk_gpio_pin_getcaps), DEVMETHOD(gpio_pin_setflags, mtk_gpio_pin_setflags), DEVMETHOD(gpio_pin_get, mtk_gpio_pin_get), DEVMETHOD(gpio_pin_set, mtk_gpio_pin_set), DEVMETHOD(gpio_pin_toggle, mtk_gpio_pin_toggle), /* Interrupt controller interface */ DEVMETHOD(pic_disable_intr, mtk_gpio_pic_disable_intr), DEVMETHOD(pic_enable_intr, mtk_gpio_pic_enable_intr), DEVMETHOD(pic_map_intr, mtk_gpio_pic_map_intr), DEVMETHOD(pic_post_filter, mtk_gpio_pic_post_filter), DEVMETHOD(pic_post_ithread, mtk_gpio_pic_post_ithread), DEVMETHOD(pic_pre_ithread, mtk_gpio_pic_pre_ithread), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, mtk_gpio_get_node), DEVMETHOD_END }; static driver_t mtk_gpio_driver = { "gpio", mtk_gpio_methods, sizeof(struct mtk_gpio_softc), }; static devclass_t mtk_gpio_devclass; EARLY_DRIVER_MODULE(mtk_gpio_v2, simplebus, mtk_gpio_driver, mtk_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); Index: head/sys/mips/mediatek/mtk_intr_gic.c =================================================================== --- head/sys/mips/mediatek/mtk_intr_gic.c (revision 298058) +++ head/sys/mips/mediatek/mtk_intr_gic.c (revision 298059) @@ -1,377 +1,377 @@ /*- * Copyright (c) 2016 Stanislav Galabov * Copyright (c) 2015 Alexander Kabaev * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions, and the following disclaimer, * without modification, immediately at the beginning of the file. * 2. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "pic_if.h" #define MTK_NIRQS 64 /* We'll only use 64 for now */ #define MTK_INTPOL 0x0100 #define MTK_INTTRIG 0x0180 #define MTK_INTDIS 0x0300 #define MTK_INTENA 0x0380 #define MTK_INTMASK 0x0400 #define MTK_INTSTAT 0x0480 #define MTK_MAPPIN(_i) (0x0500 + (4 * (_i))) #define MTK_MAPVPE(_i, _v) (0x2000 + (32 * (_i)) + (((_v) / 32) * 4)) #define MTK_INTPOL_POS 1 #define MTK_INTPOL_NEG 0 #define MTK_INTTRIG_EDGE 1 #define MTK_INTTRIG_LEVEL 0 #define MTK_PIN_BITS(_i) ((1 << 31) | (_i)) #define MTK_VPE_BITS(_v) (1 << ((_v) % 32)) static int mtk_gic_intr(void *); struct mtk_gic_irqsrc { struct intr_irqsrc isrc; u_int irq; }; struct mtk_gic_softc { device_t gic_dev; void * gic_intrhand; struct resource * gic_res[2]; struct mtk_gic_irqsrc gic_irqs[MTK_NIRQS]; struct mtx mutex; uint32_t nirqs; }; #define GIC_INTR_ISRC(sc, irq) (&(sc)->gic_irqs[(irq)].isrc) static struct resource_spec mtk_gic_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Registers */ { SYS_RES_IRQ, 0, RF_ACTIVE }, /* Parent interrupt 1 */ { -1, 0 } }; static struct ofw_compat_data compat_data[] = { { "mti,gic", 1 }, { NULL, 0 } }; #if 0 #define READ4(_sc, _reg) \ bus_space_read_4((_sc)->bst, (_sc)->bsh, _reg) #define WRITE4(_sc, _reg, _val) \ bus_space_write_4((_sc)->bst, (_sc)->bsh, _reg, _val) #else #define READ4(_sc, _reg) bus_read_4((_sc)->gic_res[0], (_reg)) #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->gic_res[0], (_reg), (_val)) #endif static int mtk_gic_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "MTK Interrupt Controller (GIC)"); return (BUS_PROBE_DEFAULT); } static inline void gic_irq_unmask(struct mtk_gic_softc *sc, u_int irq) { WRITE4(sc, MTK_INTENA, (1u << (irq))); } static inline void gic_irq_mask(struct mtk_gic_softc *sc, u_int irq) { WRITE4(sc, MTK_INTDIS, (1u << (irq))); } static inline intptr_t gic_xref(device_t dev) { return (OF_xref_from_node(ofw_bus_get_node(dev))); } static int mtk_gic_register_isrcs(struct mtk_gic_softc *sc) { int error; uint32_t irq; struct intr_irqsrc *isrc; const char *name; name = device_get_nameunit(sc->gic_dev); for (irq = 0; irq < sc->nirqs; irq++) { sc->gic_irqs[irq].irq = irq; isrc = GIC_INTR_ISRC(sc, irq); error = intr_isrc_register(isrc, sc->gic_dev, 0, "%s", name); if (error != 0) { /* XXX call intr_isrc_deregister */ device_printf(sc->gic_dev, "%s failed", __func__); return (error); } } return (0); } static int mtk_gic_attach(device_t dev) { struct mtk_gic_softc *sc; intptr_t xref = gic_xref(dev); int i; sc = device_get_softc(dev); if (bus_alloc_resources(dev, mtk_gic_spec, sc->gic_res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } sc->gic_dev = dev; /* Initialize mutex */ mtx_init(&sc->mutex, "PIC lock", "", MTX_SPIN); /* Set the number of interrupts */ sc->nirqs = nitems(sc->gic_irqs); /* Mask all interrupts */ WRITE4(sc, MTK_INTDIS, 0xFFFFFFFF); /* All interrupts are of type level */ WRITE4(sc, MTK_INTTRIG, 0x00000000); /* All interrupts are of positive polarity */ WRITE4(sc, MTK_INTPOL, 0xFFFFFFFF); /* * Route all interrupts to pin 0 on VPE 0; */ for (i = 0; i < 32; i++) { WRITE4(sc, MTK_MAPPIN(i), MTK_PIN_BITS(0)); WRITE4(sc, MTK_MAPVPE(i, 0), MTK_VPE_BITS(0)); } /* Register the interrupts */ if (mtk_gic_register_isrcs(sc) != 0) { device_printf(dev, "could not register GIC ISRCs\n"); goto cleanup; } /* * Now, when everything is initialized, it's right time to * register interrupt controller to interrupt framefork. */ if (intr_pic_register(dev, xref) != 0) { device_printf(dev, "could not register PIC\n"); goto cleanup; } if (bus_setup_intr(dev, sc->gic_res[1], INTR_TYPE_CLK, mtk_gic_intr, NULL, sc, &sc->gic_intrhand)) { device_printf(dev, "could not setup irq handler\n"); intr_pic_deregister(dev, xref); goto cleanup; } return (0); cleanup: bus_release_resources(dev, mtk_gic_spec, sc->gic_res); return(ENXIO); } static int mtk_gic_intr(void *arg) { struct mtk_gic_softc *sc = arg; struct thread *td; uint32_t i, intr; td = curthread; /* Workaround: do not inflate intr nesting level */ td->td_intr_nesting_level--; intr = READ4(sc, MTK_INTSTAT) & READ4(sc, MTK_INTMASK); while ((i = fls(intr)) != 0) { i--; intr &= ~(1u << i); if (intr_isrc_dispatch(GIC_INTR_ISRC(sc, i), curthread->td_intr_frame) != 0) { device_printf(sc->gic_dev, "Stray interrupt %u detected\n", i); gic_irq_mask(sc, i); continue; } } KASSERT(i == 0, ("all interrupts handled")); td->td_intr_nesting_level++; return (FILTER_HANDLED); } static int mtk_gic_map_intr(device_t dev, struct intr_map_data *data, struct intr_irqsrc **isrcp) { #ifdef FDT struct mtk_gic_softc *sc; sc = device_get_softc(dev); if (data == NULL || data->type != INTR_MAP_DATA_FDT || - data->fdt.ncells != 1 || data->fdt.cells[0] >= sc->nirqs) + data->fdt.ncells != 3 || data->fdt.cells[1] >= sc->nirqs) return (EINVAL); - *isrcp = GIC_INTR_ISRC(sc, data->fdt.cells[0]); + *isrcp = GIC_INTR_ISRC(sc, data->fdt.cells[1]); return (0); #else return (EINVAL); #endif } static void mtk_gic_enable_intr(device_t dev, struct intr_irqsrc *isrc) { u_int irq; irq = ((struct mtk_gic_irqsrc *)isrc)->irq; gic_irq_unmask(device_get_softc(dev), irq); } static void mtk_gic_disable_intr(device_t dev, struct intr_irqsrc *isrc) { u_int irq; irq = ((struct mtk_gic_irqsrc *)isrc)->irq; gic_irq_mask(device_get_softc(dev), irq); } static void mtk_gic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) { mtk_gic_disable_intr(dev, isrc); } static void mtk_gic_post_ithread(device_t dev, struct intr_irqsrc *isrc) { mtk_gic_enable_intr(dev, isrc); } static void mtk_gic_post_filter(device_t dev, struct intr_irqsrc *isrc) { } #ifdef SMP static int mtk_gic_bind(device_t dev, struct intr_irqsrc *isrc) { return (EOPNOTSUPP); } static void mtk_gic_init_secondary(device_t dev) { } static void mtk_gic_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus) { } #endif static device_method_t mtk_gic_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mtk_gic_probe), DEVMETHOD(device_attach, mtk_gic_attach), /* Interrupt controller interface */ DEVMETHOD(pic_disable_intr, mtk_gic_disable_intr), DEVMETHOD(pic_enable_intr, mtk_gic_enable_intr), DEVMETHOD(pic_map_intr, mtk_gic_map_intr), DEVMETHOD(pic_post_filter, mtk_gic_post_filter), DEVMETHOD(pic_post_ithread, mtk_gic_post_ithread), DEVMETHOD(pic_pre_ithread, mtk_gic_pre_ithread), #ifdef SMP DEVMETHOD(pic_bind, mtk_gic_bind), DEVMETHOD(pic_init_secondary, mtk_gic_init_secondary), DEVMETHOD(pic_ipi_send, mtk_gic_ipi_send), #endif { 0, 0 } }; static driver_t mtk_gic_driver = { "intc", mtk_gic_methods, sizeof(struct mtk_gic_softc), }; static devclass_t mtk_gic_devclass; EARLY_DRIVER_MODULE(intc_gic, simplebus, mtk_gic_driver, mtk_gic_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); Index: head/sys/mips/mediatek/mtk_ohci.c =================================================================== --- head/sys/mips/mediatek/mtk_ohci.c (revision 298058) +++ head/sys/mips/mediatek/mtk_ohci.c (revision 298059) @@ -1,223 +1,223 @@ #include __FBSDID("$FreeBSD$"); /*- * Copyright (c) 2015 Stanislav Galabov. All rights reserved. * Copyright (c) 2010,2011 Aleksandr Rybalko. All rights reserved. * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define OHCI_HC_DEVSTR "MTK USB Controller" static device_probe_t ohci_fdt_probe; static device_attach_t ohci_fdt_attach; static device_detach_t ohci_fdt_detach; static int ohci_fdt_probe(device_t self) { if (!ofw_bus_status_okay(self)) return (ENXIO); - if (!ofw_bus_is_compatible(self, "ralink,rt3xxx-ohci")) + if (!ofw_bus_is_compatible(self, "generic-ohci")) return (ENXIO); device_set_desc(self, OHCI_HC_DEVSTR); return (BUS_PROBE_DEFAULT); } static int ohci_fdt_attach(device_t self) { ohci_softc_t *sc = device_get_softc(self); int err; int rid; /* initialise some bus fields */ sc->sc_bus.parent = self; sc->sc_bus.devices = sc->sc_devices; sc->sc_bus.devices_max = OHCI_MAX_DEVICES; sc->sc_bus.dma_bits = 32; /* get all DMA memory */ if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(self), &ohci_iterate_hw_softc)) { printf("No mem\n"); return (ENOMEM); } rid = 0; sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_io_res) { device_printf(self, "Could not map memory\n"); goto error; } sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); sc->sc_io_size = rman_get_size(sc->sc_io_res); rid = 0; sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); if (sc->sc_irq_res == NULL) { device_printf(self, "Could not allocate irq\n"); goto error; } sc->sc_bus.bdev = device_add_child(self, "usbus", -1); if (!(sc->sc_bus.bdev)) { device_printf(self, "Could not add USB device\n"); goto error; } device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); device_set_desc(sc->sc_bus.bdev, OHCI_HC_DEVSTR); sprintf(sc->sc_vendor, "MediaTek"); err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, NULL, (driver_intr_t *)ohci_interrupt, sc, &sc->sc_intr_hdl); if (err) { device_printf(self, "Could not setup irq, %d\n", err); sc->sc_intr_hdl = NULL; goto error; } err = ohci_init(sc); if (!err) { err = device_probe_and_attach(sc->sc_bus.bdev); } if (err) { device_printf(self, "USB init failed err=%d\n", err); goto error; } return (0); error: ohci_fdt_detach(self); return (ENXIO); } static int ohci_fdt_detach(device_t self) { ohci_softc_t *sc = device_get_softc(self); device_t bdev; int err; if (sc->sc_bus.bdev) { bdev = sc->sc_bus.bdev; device_detach(bdev); device_delete_child(self, bdev); } /* during module unload there are lots of children leftover */ device_delete_children(self); if (sc->sc_irq_res && sc->sc_intr_hdl) { /* * only call ohci_detach() after ohci_init() */ ohci_detach(sc); err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); if (err) device_printf(self, "Could not tear down irq, %d\n", err); sc->sc_intr_hdl = NULL; } if (sc->sc_irq_res) { bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res); sc->sc_irq_res = NULL; } if (sc->sc_io_res) { bus_release_resource(self, SYS_RES_MEMORY, 0, sc->sc_io_res); sc->sc_io_res = NULL; } usb_bus_mem_free_all(&sc->sc_bus, &ohci_iterate_hw_softc); return (0); } static device_method_t ohci_fdt_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ohci_fdt_probe), DEVMETHOD(device_attach, ohci_fdt_attach), DEVMETHOD(device_detach, ohci_fdt_detach), DEVMETHOD(device_suspend, bus_generic_suspend), DEVMETHOD(device_resume, bus_generic_resume), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD_END }; static driver_t ohci_fdt_driver = { .name = "ohci", .methods = ohci_fdt_methods, .size = sizeof(ohci_softc_t), }; static devclass_t ohci_fdt_devclass; DRIVER_MODULE(ohci, simplebus, ohci_fdt_driver, ohci_fdt_devclass, 0, 0); Index: head/sys/mips/mediatek/mtk_pcie.c =================================================================== --- head/sys/mips/mediatek/mtk_pcie.c (revision 298058) +++ head/sys/mips/mediatek/mtk_pcie.c (revision 298059) @@ -1,1263 +1,1270 @@ /*- * Copyright (c) 2016 Stanislav Galabov. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "ofw_bus_if.h" #include "pcib_if.h" #include "pic_if.h" /* * Note: We only support PCIe at the moment. * Most SoCs in the Ralink/Mediatek family that we target actually don't * support PCI anyway, with the notable exceptions being RT3662/RT3883, which * support both PCI and PCIe. If there exists a board based on one of them * which is of interest in the future it shouldn't be too hard to enable PCI * support for it. */ /* Chip specific function declarations */ static int mtk_pcie_phy_init(device_t); static int mtk_pcie_phy_start(device_t); static int mtk_pcie_phy_stop(device_t); static int mtk_pcie_phy_mt7621_init(device_t); static int mtk_pcie_phy_mt7628_init(device_t); static int mtk_pcie_phy_mt7620_init(device_t); static int mtk_pcie_phy_rt3883_init(device_t); static void mtk_pcie_phy_setup_slots(device_t); /* Generic declarations */ struct mtx mtk_pci_mtx; MTX_SYSINIT(mtk_pci_mtx, &mtk_pci_mtx, "MTK PCIe mutex", MTX_SPIN); static int mtk_pci_intr(void *); static struct mtk_pci_softc *mt_sc = NULL; struct mtk_pci_range { u_long base; u_long len; }; -#define FDT_RANGES_CELLS (3 * 2) +#define FDT_RANGES_CELLS ((1 + 2 + 3) * 2) static void mtk_pci_range_dump(struct mtk_pci_range *range) { #ifdef DEBUG printf("\n"); printf(" base = 0x%08lx\n", range->base); printf(" len = 0x%08lx\n", range->len); #endif } static int mtk_pci_ranges_decode(phandle_t node, struct mtk_pci_range *io_space, struct mtk_pci_range *mem_space) { struct mtk_pci_range *pci_space; pcell_t ranges[FDT_RANGES_CELLS]; + pcell_t addr_cells, size_cells, par_addr_cells; pcell_t *rangesptr; pcell_t cell0, cell1, cell2; - int tuples, i, rv, len; + int tuple_size, tuples, i, rv, len; /* * Retrieve 'ranges' property. */ - if (!OF_hasprop(node, "ranges")) { - printf("%s: %d\n", __FUNCTION__, 1); + if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) return (EINVAL); - } + if (addr_cells != 3 || size_cells != 2) + return (ERANGE); + par_addr_cells = fdt_parent_addr_cells(node); + if (par_addr_cells != 1) + return (ERANGE); + len = OF_getproplen(node, "ranges"); - if (len > sizeof(ranges)) { - printf("%s: %d\n", __FUNCTION__, 2); + if (len > sizeof(ranges)) return (ENOMEM); - } - if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0) { - printf("%s: %d\n", __FUNCTION__, 3); + if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0) return (EINVAL); - } - tuples = len / (sizeof(pcell_t) * 3); + tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + + size_cells); + tuples = len / tuple_size; /* * Initialize the ranges so that we don't have to worry about * having them all defined in the FDT. In particular, it is * perfectly fine not to want I/O space on PCI busses. */ bzero(io_space, sizeof(*io_space)); bzero(mem_space, sizeof(*mem_space)); rangesptr = &ranges[0]; for (i = 0; i < tuples; i++) { cell0 = fdt_data_get((void *)rangesptr, 1); rangesptr++; cell1 = fdt_data_get((void *)rangesptr, 1); rangesptr++; cell2 = fdt_data_get((void *)rangesptr, 1); rangesptr++; - if (cell0 == 2) { + if (cell0 & 0x02000000) { pci_space = mem_space; - } else if (cell0 == 1) { + } else if (cell0 & 0x01000000) { pci_space = io_space; } else { rv = ERANGE; - printf("%s: %d\n", __FUNCTION__, 4); goto out; } - pci_space->base = cell1; - pci_space->len = cell2; + pci_space->base = fdt_data_get((void *)rangesptr, + par_addr_cells); + rangesptr += par_addr_cells; + + pci_space->len = fdt_data_get((void *)rangesptr, size_cells); + rangesptr += size_cells; } rv = 0; out: return (rv); } static int mtk_pci_ranges(phandle_t node, struct mtk_pci_range *io_space, struct mtk_pci_range *mem_space) { int err; if ((err = mtk_pci_ranges_decode(node, io_space, mem_space)) != 0) { return (err); } mtk_pci_range_dump(io_space); mtk_pci_range_dump(mem_space); return (0); } static struct ofw_compat_data compat_data[] = { { "ralink,rt3662-pcie", MTK_SOC_RT3883 }, { "ralink,rt3883-pcie", MTK_SOC_RT3883 }, { "ralink,mt7620a-pcie", MTK_SOC_MT7620A }, { "ralink,mt7621-pcie", MTK_SOC_MT7621 }, + { "mediatek,mt7621-pci", MTK_SOC_MT7621 }, { "ralink,mt7628-pcie", MTK_SOC_MT7628 }, { "ralink,mt7688-pcie", MTK_SOC_MT7628 }, { NULL, MTK_SOC_UNKNOWN } }; static int mtk_pci_probe(device_t dev) { struct mtk_pci_softc *sc = device_get_softc(dev); if (!ofw_bus_status_okay(dev)) return (ENXIO); sc->socid = ofw_bus_search_compatible(dev, compat_data)->ocd_data; if (sc->socid == MTK_SOC_UNKNOWN) return (ENXIO); device_set_desc(dev, "MTK PCIe Controller"); return (0); } static int mtk_pci_attach(device_t dev) { struct mtk_pci_softc *sc = device_get_softc(dev); struct mtk_pci_range io_space, mem_space; phandle_t node; intptr_t xref; int i, rid; sc->sc_dev = dev; mt_sc = sc; sc->addr_mask = 0xffffffff; /* Request our memory */ rid = 0; sc->pci_res[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->pci_res[0] == NULL) { device_printf(dev, "could not allocate memory resource\n"); return (ENXIO); } /* See how many interrupts we need */ if (sc->socid == MTK_SOC_MT7621) sc->sc_num_irq = 3; else { sc->sc_num_irq = 1; sc->pci_res[2] = sc->pci_res[3] = NULL; sc->pci_intrhand[1] = sc->pci_intrhand[2] = NULL; } /* Request our interrupts */ for (i = 1; i <= sc->sc_num_irq ; i++) { rid = i - 1; sc->pci_res[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (sc->pci_res[i] == NULL) { device_printf(dev, "could not allocate interrupt " "resource %d\n", rid); goto cleanup_res; } } /* Parse our PCI 'ranges' property */ node = ofw_bus_get_node(dev); xref = OF_xref_from_node(node); if (mtk_pci_ranges(node, &io_space, &mem_space)) { device_printf(dev, "could not retrieve 'ranges' data\n"); goto cleanup_res; } /* Memory, I/O and IRQ resource limits */ sc->sc_io_base = io_space.base; sc->sc_io_size = io_space.len; sc->sc_mem_base = mem_space.base; sc->sc_mem_size = mem_space.len; sc->sc_irq_start = MTK_PCIE0_IRQ; sc->sc_irq_end = MTK_PCIE2_IRQ; /* Init resource managers for memory, I/O and IRQ */ sc->sc_mem_rman.rm_type = RMAN_ARRAY; sc->sc_mem_rman.rm_descr = "mtk pcie memory window"; if (rman_init(&sc->sc_mem_rman) != 0 || rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base, sc->sc_mem_base + sc->sc_mem_size - 1) != 0) { device_printf(dev, "failed to setup memory rman\n"); goto cleanup_res; } sc->sc_io_rman.rm_type = RMAN_ARRAY; sc->sc_io_rman.rm_descr = "mtk pcie io window"; if (rman_init(&sc->sc_io_rman) != 0 || rman_manage_region(&sc->sc_io_rman, sc->sc_io_base, sc->sc_io_base + sc->sc_io_size - 1) != 0) { device_printf(dev, "failed to setup io rman\n"); goto cleanup_res; } sc->sc_irq_rman.rm_type = RMAN_ARRAY; sc->sc_irq_rman.rm_descr = "mtk pcie irqs"; if (rman_init(&sc->sc_irq_rman) != 0 || rman_manage_region(&sc->sc_irq_rman, sc->sc_irq_start, sc->sc_irq_end) != 0) { device_printf(dev, "failed to setup irq rman\n"); goto cleanup_res; } /* Do SoC-specific PCIe initialization */ if (mtk_pcie_phy_init(dev)) { device_printf(dev, "pcie phy init failed\n"); goto cleanup_rman; } /* Register ourselves as an interrupt controller */ if (intr_pic_register(dev, xref) != 0) { device_printf(dev, "could not register PIC\n"); goto cleanup_rman; } /* Set up our interrupt handler */ for (i = 1; i <= sc->sc_num_irq; i++) { sc->pci_intrhand[i - 1] = NULL; if (bus_setup_intr(dev, sc->pci_res[i], INTR_TYPE_MISC, mtk_pci_intr, NULL, sc, &sc->pci_intrhand[i - 1])) { device_printf(dev, "could not setup intr handler %d\n", i); goto cleanup; } } /* Attach our PCI child so bus enumeration can start */ if (device_add_child(dev, "pci", -1) == NULL) { device_printf(dev, "could not attach pci bus\n"); goto cleanup; } /* And finally, attach ourselves to the bus */ if (bus_generic_attach(dev)) { device_printf(dev, "could not attach to bus\n"); goto cleanup; } return (0); cleanup: #ifdef notyet intr_pic_unregister(dev, xref); #endif for (i = 1; i <= sc->sc_num_irq; i++) { if (sc->pci_intrhand[i - 1] != NULL) bus_teardown_intr(dev, sc->pci_res[i], sc->pci_intrhand[i - 1]); } cleanup_rman: mtk_pcie_phy_stop(dev); rman_fini(&sc->sc_irq_rman); rman_fini(&sc->sc_io_rman); rman_fini(&sc->sc_mem_rman); cleanup_res: mt_sc = NULL; if (sc->pci_res[0] != NULL) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->pci_res[0]); if (sc->pci_res[1] != NULL) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pci_res[1]); if (sc->pci_res[2] != NULL) bus_release_resource(dev, SYS_RES_IRQ, 1, sc->pci_res[2]); if (sc->pci_res[3] != NULL) bus_release_resource(dev, SYS_RES_IRQ, 2, sc->pci_res[3]); return (ENXIO); } static int mtk_pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) { struct mtk_pci_softc *sc = device_get_softc(dev); switch (which) { case PCIB_IVAR_DOMAIN: *result = device_get_unit(dev); return (0); case PCIB_IVAR_BUS: *result = sc->sc_busno; return (0); } return (ENOENT); } static int mtk_pci_write_ivar(device_t dev, device_t child, int which, uintptr_t result) { struct mtk_pci_softc *sc = device_get_softc(dev); switch (which) { case PCIB_IVAR_BUS: sc->sc_busno = result; return (0); } return (ENOENT); } static struct resource * mtk_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) { struct mtk_pci_softc *sc = device_get_softc(bus); struct resource *rv; struct rman *rm; switch (type) { case PCI_RES_BUS: return pci_domain_alloc_bus(0, child, rid, start, end, count, flags); case SYS_RES_IRQ: rm = &sc->sc_irq_rman; break; case SYS_RES_IOPORT: rm = &sc->sc_io_rman; break; case SYS_RES_MEMORY: rm = &sc->sc_mem_rman; break; default: return (NULL); } rv = rman_reserve_resource(rm, start, end, count, flags, child); if (rv == NULL) return (NULL); rman_set_rid(rv, *rid); if ((flags & RF_ACTIVE) && type != SYS_RES_IRQ) { if (bus_activate_resource(child, type, *rid, rv)) { rman_release_resource(rv); return (NULL); } } return (rv); } static int mtk_pci_release_resource(device_t bus, device_t child, int type, int rid, struct resource *res) { if (type == PCI_RES_BUS) return (pci_domain_release_bus(0, child, rid, res)); return (bus_generic_release_resource(bus, child, type, rid, res)); } static int mtk_pci_adjust_resource(device_t bus, device_t child, int type, struct resource *res, rman_res_t start, rman_res_t end) { struct mtk_pci_softc *sc = device_get_softc(bus); struct rman *rm; switch (type) { case PCI_RES_BUS: return pci_domain_adjust_bus(0, child, res, start, end); case SYS_RES_IRQ: rm = &sc->sc_irq_rman; break; case SYS_RES_IOPORT: rm = &sc->sc_io_rman; break; case SYS_RES_MEMORY: rm = &sc->sc_mem_rman; break; default: rm = NULL; break; } if (rm != NULL) return (rman_adjust_resource(res, start, end)); return (bus_generic_adjust_resource(bus, child, type, res, start, end)); } static inline int mtk_idx_to_irq(int idx) { return ((idx == 0) ? MTK_PCIE0_IRQ : (idx == 1) ? MTK_PCIE1_IRQ : (idx == 2) ? MTK_PCIE2_IRQ : -1); } static inline int mtk_irq_to_idx(int irq) { return ((irq == MTK_PCIE0_IRQ) ? 0 : (irq == MTK_PCIE1_IRQ) ? 1 : (irq == MTK_PCIE2_IRQ) ? 2 : -1); } static void mtk_pci_mask_irq(void *source) { MT_WRITE32(mt_sc, MTK_PCI_PCIENA, MT_READ32(mt_sc, MTK_PCI_PCIENA) & ~(1<<((int)source))); } static void mtk_pci_unmask_irq(void *source) { MT_WRITE32(mt_sc, MTK_PCI_PCIENA, MT_READ32(mt_sc, MTK_PCI_PCIENA) | (1<<((int)source))); } static int mtk_pci_setup_intr(device_t bus, device_t child, struct resource *ires, int flags, driver_filter_t *filt, driver_intr_t *handler, void *arg, void **cookiep) { struct mtk_pci_softc *sc = device_get_softc(bus); struct intr_event *event; int irq, error, irqidx; irq = rman_get_start(ires); if (irq < sc->sc_irq_start || irq > sc->sc_irq_end) return (EINVAL); irqidx = irq - sc->sc_irq_start; event = sc->sc_eventstab[irqidx]; if (event == NULL) { error = intr_event_create(&event, (void *)irq, 0, irq, mtk_pci_mask_irq, mtk_pci_unmask_irq, NULL, NULL, "pci intr%d:", irq); if (error == 0) { sc->sc_eventstab[irqidx] = event; } else { return (error); } } intr_event_add_handler(event, device_get_nameunit(child), filt, handler, arg, intr_priority(flags), flags, cookiep); mtk_pci_unmask_irq((void*)irq); return (0); } static int mtk_pci_teardown_intr(device_t dev, device_t child, struct resource *ires, void *cookie) { struct mtk_pci_softc *sc = device_get_softc(dev); int irq, result, irqidx; irq = rman_get_start(ires); if (irq < sc->sc_irq_start || irq > sc->sc_irq_end) return (EINVAL); irqidx = irq - sc->sc_irq_start; if (sc->sc_eventstab[irqidx] == NULL) panic("Trying to teardown unoccupied IRQ"); mtk_pci_mask_irq((void*)irq); result = intr_event_remove_handler(cookie); if (!result) sc->sc_eventstab[irqidx] = NULL; return (result); } static inline uint32_t mtk_pci_make_addr(int bus, int slot, int func, int reg) { uint32_t addr; addr = ((((reg & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) | (func << 8) | (reg & 0xfc) | (1 << 31)); return (addr); } static int mtk_pci_maxslots(device_t dev) { return (PCI_SLOTMAX); } static inline int mtk_pci_slot_has_link(device_t dev, int slot) { struct mtk_pci_softc *sc = device_get_softc(dev); return !!(sc->pcie_link_status & (1<addr_mask; MT_WRITE32(sc, MTK_PCI_CFGADDR, addr); switch (bytes % 4) { case 0: data = MT_READ32(sc, MTK_PCI_CFGDATA); break; case 1: data = MT_READ8(sc, MTK_PCI_CFGDATA + (reg & 0x3)); break; case 2: data = MT_READ16(sc, MTK_PCI_CFGDATA + (reg & 0x3)); break; default: panic("%s(): Wrong number of bytes (%d) requested!\n", __FUNCTION__, bytes % 4); } mtx_unlock_spin(&mtk_pci_mtx); return (data); } static void mtk_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, uint32_t val, int bytes) { struct mtk_pci_softc *sc = device_get_softc(dev); uint32_t addr = 0, data = val; /* Do not write if slot has no link */ if (bus == 0 && mtk_pci_slot_has_link(dev, slot) == 0) return; mtx_lock_spin(&mtk_pci_mtx); addr = mtk_pci_make_addr(bus, slot, func, (reg & ~3)) & sc->addr_mask; MT_WRITE32(sc, MTK_PCI_CFGADDR, addr); switch (bytes % 4) { case 0: MT_WRITE32(sc, MTK_PCI_CFGDATA, data); break; case 1: MT_WRITE8(sc, MTK_PCI_CFGDATA + (reg & 0x3), data); break; case 2: MT_WRITE16(sc, MTK_PCI_CFGDATA + (reg & 0x3), data); break; default: panic("%s(): Wrong number of bytes (%d) requested!\n", __FUNCTION__, bytes % 4); } mtx_unlock_spin(&mtk_pci_mtx); } static int mtk_pci_route_interrupt(device_t pcib, device_t device, int pin) { int bus, sl, dev; bus = pci_get_bus(device); sl = pci_get_slot(device); dev = pci_get_device(device); if (bus != 0) panic("Unexpected bus number %d\n", bus); /* PCIe only */ switch (sl) { case 0: return MTK_PCIE0_IRQ; case 1: return MTK_PCIE0_IRQ + 1; case 2: return MTK_PCIE0_IRQ + 2; default: return (-1); } return (-1); } static device_method_t mtk_pci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mtk_pci_probe), DEVMETHOD(device_attach, mtk_pci_attach), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD(device_suspend, bus_generic_suspend), DEVMETHOD(device_resume, bus_generic_resume), /* Bus interface */ DEVMETHOD(bus_read_ivar, mtk_pci_read_ivar), DEVMETHOD(bus_write_ivar, mtk_pci_write_ivar), DEVMETHOD(bus_alloc_resource, mtk_pci_alloc_resource), DEVMETHOD(bus_release_resource, mtk_pci_release_resource), DEVMETHOD(bus_adjust_resource, mtk_pci_adjust_resource), DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), DEVMETHOD(bus_setup_intr, mtk_pci_setup_intr), DEVMETHOD(bus_teardown_intr, mtk_pci_teardown_intr), /* pcib interface */ DEVMETHOD(pcib_maxslots, mtk_pci_maxslots), DEVMETHOD(pcib_read_config, mtk_pci_read_config), DEVMETHOD(pcib_write_config, mtk_pci_write_config), DEVMETHOD(pcib_route_interrupt, mtk_pci_route_interrupt), /* OFW bus interface */ DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), DEVMETHOD_END }; static driver_t mtk_pci_driver = { "pcib", mtk_pci_methods, sizeof(struct mtk_pci_softc), }; static devclass_t mtk_pci_devclass; DRIVER_MODULE(mtk_pci, simplebus, mtk_pci_driver, mtk_pci_devclass, 0, 0); /* Our interrupt handler */ static int mtk_pci_intr(void *arg) { struct mtk_pci_softc *sc = arg; struct intr_event *event; uint32_t reg, irq, irqidx; reg = MT_READ32(sc, MTK_PCI_PCIINT); for (irq = sc->sc_irq_start; irq <= sc->sc_irq_end; irq++) { if (reg & (1u<sc_irq_start; event = sc->sc_eventstab[irqidx]; if (!event || TAILQ_EMPTY(&event->ie_handlers)) { if (irq != 0) printf("Stray PCI IRQ %d\n", irq); continue; } intr_event_handle(event, NULL); } } return (FILTER_HANDLED); } /* PCIe SoC-specific initialization */ static int mtk_pcie_phy_init(device_t dev) { struct mtk_pci_softc *sc; /* Get our softc */ sc = device_get_softc(dev); /* We don't know how many slots we have yet */ sc->num_slots = 0; /* Handle SoC specific PCIe init */ switch (sc->socid) { case MTK_SOC_MT7628: /* Fallthrough */ case MTK_SOC_MT7688: if (mtk_pcie_phy_mt7628_init(dev)) return (ENXIO); break; case MTK_SOC_MT7621: if (mtk_pcie_phy_mt7621_init(dev)) return (ENXIO); break; case MTK_SOC_MT7620A: if (mtk_pcie_phy_mt7620_init(dev)) return (ENXIO); break; case MTK_SOC_RT3662: /* Fallthrough */ case MTK_SOC_RT3883: if (mtk_pcie_phy_rt3883_init(dev)) return (ENXIO); break; default: device_printf(dev, "unsupported device %x\n", sc->socid); return (ENXIO); } /* * If we were successful so far go and set up the PCIe slots, so we * may allocate mem/io/irq resources and enumerate busses later. */ mtk_pcie_phy_setup_slots(dev); return (0); } static int mtk_pcie_phy_start(device_t dev) { struct mtk_pci_softc *sc = device_get_softc(dev); if (sc->socid == MTK_SOC_MT7621 && (mtk_sysctl_get(SYSCTL_REVID) & SYSCTL_REVID_MASK) != SYSCTL_MT7621_REV_E) { if (fdt_reset_assert_all(dev)) return (ENXIO); } else { if (fdt_reset_deassert_all(dev)) return (ENXIO); } if (fdt_clock_enable_all(dev)) return (ENXIO); return (0); } static int mtk_pcie_phy_stop(device_t dev) { struct mtk_pci_softc *sc = device_get_softc(dev); if (sc->socid == MTK_SOC_MT7621 && (mtk_sysctl_get(SYSCTL_REVID) & SYSCTL_REVID_MASK) != SYSCTL_MT7621_REV_E) { if (fdt_reset_deassert_all(dev)) return (ENXIO); } else { if (fdt_reset_assert_all(dev)) return (ENXIO); } if (fdt_clock_disable_all(dev)) return (ENXIO); return (0); } #define mtk_pcie_phy_set(_sc, _reg, _s, _n, _v) \ MT_WRITE32((_sc), (_reg), ((MT_READ32((_sc), (_reg)) & \ (~(((1ull << (_n)) - 1) << (_s)))) | ((_v) << (_s)))) static void mtk_pcie_phy_mt7621_bypass_pipe_rst(struct mtk_pci_softc *sc, uint32_t off) { mtk_pcie_phy_set(sc, off + 0x002c, 12, 1, 1); mtk_pcie_phy_set(sc, off + 0x002c, 4, 1, 1); mtk_pcie_phy_set(sc, off + 0x012c, 12, 1, 1); mtk_pcie_phy_set(sc, off + 0x012c, 4, 1, 1); mtk_pcie_phy_set(sc, off + 0x102c, 12, 1, 1); mtk_pcie_phy_set(sc, off + 0x102c, 4, 1, 1); } static void mtk_pcie_phy_mt7621_setup_ssc(struct mtk_pci_softc *sc, uint32_t off) { uint32_t xtal_sel; xtal_sel = mtk_sysctl_get(SYSCTL_SYSCFG) >> 6; xtal_sel &= 0x7; mtk_pcie_phy_set(sc, off + 0x400, 8, 1, 1); mtk_pcie_phy_set(sc, off + 0x400, 9, 2, 0); mtk_pcie_phy_set(sc, off + 0x000, 4, 1, 1); mtk_pcie_phy_set(sc, off + 0x100, 4, 1, 1); mtk_pcie_phy_set(sc, off + 0x000, 5, 1, 0); mtk_pcie_phy_set(sc, off + 0x100, 5, 1, 0); if (xtal_sel <= 5 && xtal_sel >= 3) { mtk_pcie_phy_set(sc, off + 0x490, 6, 2, 1); mtk_pcie_phy_set(sc, off + 0x4a8, 0, 12, 0x1a); mtk_pcie_phy_set(sc, off + 0x4a8, 16, 12, 0x1a); } else { mtk_pcie_phy_set(sc, off + 0x490, 6, 2, 0); if (xtal_sel >= 6) { mtk_pcie_phy_set(sc, off + 0x4bc, 4, 2, 0x01); mtk_pcie_phy_set(sc, off + 0x49c, 0, 31, 0x18000000); mtk_pcie_phy_set(sc, off + 0x4a4, 0, 16, 0x18d); mtk_pcie_phy_set(sc, off + 0x4a8, 0, 12, 0x4a); mtk_pcie_phy_set(sc, off + 0x4a8, 16, 12, 0x4a); mtk_pcie_phy_set(sc, off + 0x4a8, 0, 12, 0x11); mtk_pcie_phy_set(sc, off + 0x4a8, 16, 12, 0x11); } else { mtk_pcie_phy_set(sc, off + 0x4a8, 0, 12, 0x1a); mtk_pcie_phy_set(sc, off + 0x4a8, 16, 12, 0x1a); } } mtk_pcie_phy_set(sc, off + 0x4a0, 5, 1, 1); mtk_pcie_phy_set(sc, off + 0x490, 22, 2, 2); mtk_pcie_phy_set(sc, off + 0x490, 18, 4, 6); mtk_pcie_phy_set(sc, off + 0x490, 12, 4, 2); mtk_pcie_phy_set(sc, off + 0x490, 8, 4, 1); mtk_pcie_phy_set(sc, off + 0x4ac, 16, 3, 0); mtk_pcie_phy_set(sc, off + 0x490, 1, 3, 2); if (xtal_sel <= 5 && xtal_sel >= 3) { mtk_pcie_phy_set(sc, off + 0x414, 6, 2, 1); mtk_pcie_phy_set(sc, off + 0x414, 5, 1, 1); } mtk_pcie_phy_set(sc, off + 0x414, 28, 2, 1); mtk_pcie_phy_set(sc, off + 0x040, 17, 4, 7); mtk_pcie_phy_set(sc, off + 0x040, 16, 1, 1); mtk_pcie_phy_set(sc, off + 0x140, 17, 4, 7); mtk_pcie_phy_set(sc, off + 0x140, 16, 1, 1); mtk_pcie_phy_set(sc, off + 0x000, 5, 1, 1); mtk_pcie_phy_set(sc, off + 0x100, 5, 1, 1); mtk_pcie_phy_set(sc, off + 0x000, 4, 1, 0); mtk_pcie_phy_set(sc, off + 0x100, 4, 1, 0); } /* XXX: ugly, we need to fix this at some point */ #define MT7621_GPIO_CTRL0 *((volatile uint32_t *)0xbe000600) #define MT7621_GPIO_DATA0 *((volatile uint32_t *)0xbe000620) #define mtk_gpio_clr_set(_reg, _clr, _set) \ do { \ (_reg) = ((_reg) & (_clr)) | (_set); \ } while (0) static int mtk_pcie_phy_mt7621_init(device_t dev) { struct mtk_pci_softc *sc = device_get_softc(dev); /* First off, stop the PHY */ if (mtk_pcie_phy_stop(dev)) return (ENXIO); /* PCIe resets are GPIO pins */ mtk_sysctl_clr_set(SYSCTL_GPIOMODE, MT7621_PERST_GPIO_MODE | MT7621_UARTL3_GPIO_MODE, MT7621_PERST_GPIO | MT7621_UARTL3_GPIO); /* Set GPIO pins as outputs */ mtk_gpio_clr_set(MT7621_GPIO_CTRL0, 0, MT7621_PCIE_RST); /* Assert resets to PCIe devices */ mtk_gpio_clr_set(MT7621_GPIO_DATA0, MT7621_PCIE_RST, 0); /* Give everything a chance to sink in */ DELAY(100000); /* Now start the PHY again */ if (mtk_pcie_phy_start(dev)) return (ENXIO); /* Wait for things to settle */ DELAY(100000); /* Only apply below to REV-E hardware */ if ((mtk_sysctl_get(SYSCTL_REVID) & SYSCTL_REVID_MASK) == SYSCTL_MT7621_REV_E) mtk_pcie_phy_mt7621_bypass_pipe_rst(sc, 0x9000); /* Setup PCIe ports 0 and 1 */ mtk_pcie_phy_mt7621_setup_ssc(sc, 0x9000); /* Setup PCIe port 2 */ mtk_pcie_phy_mt7621_setup_ssc(sc, 0xa000); /* Deassert resets to PCIe devices */ mtk_gpio_clr_set(MT7621_GPIO_DATA0, 0, MT7621_PCIE_RST); /* Set number of slots supported */ sc->num_slots = 3; /* Give it a chance to sink in */ DELAY(100000); return (0); } static void mtk_pcie_phy_mt7628_setup(struct mtk_pci_softc *sc, uint32_t off) { uint32_t xtal_sel; xtal_sel = mtk_sysctl_get(SYSCTL_SYSCFG) >> 6; xtal_sel &= 0x1; mtk_pcie_phy_set(sc, off + 0x400, 8, 1, 1); mtk_pcie_phy_set(sc, off + 0x400, 9, 2, 0); mtk_pcie_phy_set(sc, off + 0x000, 4, 1, 1); mtk_pcie_phy_set(sc, off + 0x000, 5, 1, 0); mtk_pcie_phy_set(sc, off + 0x4ac, 16, 3, 3); if (xtal_sel == 1) { mtk_pcie_phy_set(sc, off + 0x4bc, 24, 8, 0x7d); mtk_pcie_phy_set(sc, off + 0x490, 12, 4, 0x08); mtk_pcie_phy_set(sc, off + 0x490, 6, 2, 0x01); mtk_pcie_phy_set(sc, off + 0x4c0, 0, 32, 0x1f400000); mtk_pcie_phy_set(sc, off + 0x4a4, 0, 16, 0x013d); mtk_pcie_phy_set(sc, off + 0x4a8, 16, 16, 0x74); mtk_pcie_phy_set(sc, off + 0x4a8, 0, 16, 0x74); } else { mtk_pcie_phy_set(sc, off + 0x4bc, 24, 8, 0x64); mtk_pcie_phy_set(sc, off + 0x490, 12, 4, 0x0a); mtk_pcie_phy_set(sc, off + 0x490, 6, 2, 0x00); mtk_pcie_phy_set(sc, off + 0x4c0, 0, 32, 0x19000000); mtk_pcie_phy_set(sc, off + 0x4a4, 0, 16, 0x018d); mtk_pcie_phy_set(sc, off + 0x4a8, 16, 16, 0x4a); mtk_pcie_phy_set(sc, off + 0x4a8, 0, 16, 0x4a); } mtk_pcie_phy_set(sc, off + 0x498, 0, 8, 5); mtk_pcie_phy_set(sc, off + 0x000, 5, 1, 1); mtk_pcie_phy_set(sc, off + 0x000, 4, 1, 0); } static int mtk_pcie_phy_mt7628_init(device_t dev) { struct mtk_pci_softc *sc = device_get_softc(dev); /* Set PCIe reset to normal mode */ mtk_sysctl_clr_set(SYSCTL_GPIOMODE, MT7628_PERST_GPIO_MODE, MT7628_PERST); /* Start the PHY */ if (mtk_pcie_phy_start(dev)) return (ENXIO); /* Give it a chance to sink in */ DELAY(100000); /* Setup the PHY */ mtk_pcie_phy_mt7628_setup(sc, 0x9000); /* Deassert PCIe device reset */ MT_CLR_SET32(sc, MTK_PCI_PCICFG, MTK_PCI_RESET, 0); /* Set number of slots supported */ sc->num_slots = 1; return (0); } static int mtk_pcie_phy_mt7620_wait_busy(struct mtk_pci_softc *sc) { uint32_t reg_value, retry; reg_value = retry = 0; while (retry++ < MT7620_MAX_RETRIES) { reg_value = MT_READ32(sc, MT7620_PCIE_PHY_CFG); if (reg_value & PHY_BUSY) DELAY(100000); else break; } if (retry >= MT7620_MAX_RETRIES) return (ENXIO); return (0); } static int mtk_pcie_phy_mt7620_set(struct mtk_pci_softc *sc, uint32_t reg, uint32_t val) { uint32_t reg_val; if (mtk_pcie_phy_mt7620_wait_busy(sc)) return (ENXIO); reg_val = PHY_MODE_WRITE | ((reg & 0xff) << PHY_ADDR_OFFSET) | (val & 0xff); MT_WRITE32(sc, MT7620_PCIE_PHY_CFG, reg_val); DELAY(1000); if (mtk_pcie_phy_mt7620_wait_busy(sc)) return (ENXIO); return (0); } static int mtk_pcie_phy_mt7620_init(device_t dev) { struct mtk_pci_softc *sc = device_get_softc(dev); /* * The below sets the PCIe PHY to bypass the PCIe DLL and enables * "elastic buffer control", whatever that may be... */ if (mtk_pcie_phy_mt7620_set(sc, 0x00, 0x80) || mtk_pcie_phy_mt7620_set(sc, 0x01, 0x04) || mtk_pcie_phy_mt7620_set(sc, 0x68, 0x84)) return (ENXIO); /* Stop PCIe */ if (mtk_pcie_phy_stop(dev)) return (ENXIO); /* Restore PPLL to a sane state before going on */ mtk_sysctl_clr_set(MT7620_PPLL_DRV, LC_CKDRVPD, PDRV_SW_SET); /* No PCIe on the MT7620N */ if (!(mtk_sysctl_get(SYSCTL_REVID) & MT7620_PKG_BGA)) { device_printf(dev, "PCIe disabled for MT7620N\n"); mtk_sysctl_clr_set(MT7620_PPLL_CFG0, 0, PPLL_SW_SET); mtk_sysctl_clr_set(MT7620_PPLL_CFG1, 0, PPLL_PD); return (ENXIO); } /* PCIe device reset pin is in normal mode */ mtk_sysctl_clr_set(SYSCTL_GPIOMODE, MT7620_PERST_GPIO_MODE, MT7620_PERST); /* Enable PCIe now */ if (mtk_pcie_phy_start(dev)) return (ENXIO); /* Give it a chance to sink in */ DELAY(100000); /* If PLL is not locked - bail */ if (!(mtk_sysctl_get(MT7620_PPLL_CFG1) & PPLL_LOCKED)) { device_printf(dev, "no PPLL not lock\n"); mtk_pcie_phy_stop(dev); return (ENXIO); } /* Configure PCIe PLL */ mtk_sysctl_clr_set(MT7620_PPLL_DRV, LC_CKDRVOHZ | LC_CKDRVHZ, LC_CKDRVPD | PDRV_SW_SET); /* and give it a chance to settle */ DELAY(100000); /* Deassert PCIe device reset */ MT_CLR_SET32(sc, MTK_PCI_PCICFG, MTK_PCI_RESET, 0); /* MT7620 supports one PCIe slot */ sc->num_slots = 1; return (0); } static int mtk_pcie_phy_rt3883_init(device_t dev) { struct mtk_pci_softc *sc = device_get_softc(dev); /* Enable PCI host mode and PCIe RC mode */ mtk_sysctl_clr_set(SYSCTL_SYSCFG1, 0, RT3883_PCI_HOST_MODE | RT3883_PCIE_RC_MODE); /* Enable PCIe PHY */ if (mtk_pcie_phy_start(dev)) return (ENXIO); /* Disable PCI, we only support PCIe for now */ mtk_sysctl_clr_set(SYSCTL_RSTCTRL, 0, RT3883_PCI_RST); mtk_sysctl_clr_set(SYSCTL_CLKCFG1, RT3883_PCI_CLK, 0); /* Give things a chance to sink in */ DELAY(500000); /* Set PCIe port number to 0 and lift PCIe reset */ MT_WRITE32(sc, MTK_PCI_PCICFG, 0); /* Configure PCI Arbiter */ MT_WRITE32(sc, MTK_PCI_ARBCTL, 0x79); /* We have a single PCIe slot */ sc->num_slots = 1; return (0); } static void mtk_pcie_phy_setup_slots(device_t dev) { struct mtk_pci_softc *sc = device_get_softc(dev); uint32_t bar0_val, val; int i; /* Disable all PCIe interrupts */ MT_WRITE32(sc, MTK_PCI_PCIENA, 0); /* Default bar0_val is 64M, enabled */ bar0_val = 0x03FF0001; /* But we override it to 2G, enabled for some SoCs */ if (sc->socid == MTK_SOC_MT7620A || sc->socid == MTK_SOC_MT7628 || sc->socid == MTK_SOC_MT7688 || sc->socid == MTK_SOC_MT7621) bar0_val = 0x7FFF0001; /* We still don't know which slots have linked up */ sc->pcie_link_status = 0; /* XXX: I am not sure if this delay is really necessary */ DELAY(500000); /* * See which slots have links and mark them. * Set up all slots' BARs and make them look like PCIe bridges. */ for (i = 0; i < sc->num_slots; i++) { /* If slot has link - mark it */ if (MT_READ32(sc, MTK_PCIE_STATUS(i)) & 1) sc->pcie_link_status |= (1< __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include static uint32_t mtk_soc_socid = MTK_SOC_UNKNOWN; static uint32_t mtk_soc_uartclk = 0; static uint32_t mtk_soc_cpuclk = MTK_CPU_CLK_880MHZ; static uint32_t mtk_soc_timerclk = MTK_CPU_CLK_880MHZ / 2; static const struct ofw_compat_data compat_data[] = { { "ralink,rt3050-soc", MTK_SOC_RT3050 }, { "ralink,rt3052-soc", MTK_SOC_RT3052 }, { "ralink,rt3350-soc", MTK_SOC_RT3350 }, { "ralink,rt3352-soc", MTK_SOC_RT3352 }, { "ralink,rt3662-soc", MTK_SOC_RT3662 }, { "ralink,rt3883-soc", MTK_SOC_RT3883 }, { "ralink,rt5350-soc", MTK_SOC_RT5350 }, { "ralink,mtk7620a-soc", MTK_SOC_MT7620A }, { "ralink,mtk7620n-soc", MTK_SOC_MT7620N }, { "mediatek,mtk7621-soc", MTK_SOC_MT7621 }, + { "mediatek,mt7621-soc", MTK_SOC_MT7621 }, { "ralink,mtk7621-soc", MTK_SOC_MT7621 }, { "ralink,mtk7628an-soc", MTK_SOC_MT7628 }, { "mediatek,mt7628an-soc", MTK_SOC_MT7628 }, { "ralink,mtk7688-soc", MTK_SOC_MT7688 }, /* Sentinel */ { NULL, MTK_SOC_UNKNOWN }, }; static uint32_t mtk_detect_cpuclk_rt305x(bus_space_tag_t bst, bus_space_handle_t bsh) { uint32_t clk; clk = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG); clk >>= RT305X_CPU_CLKSEL_OFF; clk &= RT305X_CPU_CLKSEL_MSK; return ((clk == 0) ? MTK_CPU_CLK_320MHZ : MTK_CPU_CLK_384MHZ); } static uint32_t mtk_detect_cpuclk_rt3352(bus_space_tag_t bst, bus_space_handle_t bsh) { uint32_t val; val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG); val >>= RT3352_CPU_CLKSEL_OFF; val &= RT3352_CPU_CLKSEL_MSK; if (val) return (MTK_CPU_CLK_400MHZ); return (MTK_CPU_CLK_384MHZ); } static uint32_t mtk_detect_cpuclk_rt3883(bus_space_tag_t bst, bus_space_handle_t bsh) { uint32_t val; val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG); val >>= RT3883_CPU_CLKSEL_OFF; val &= RT3883_CPU_CLKSEL_MSK; switch (val) { case 0: return (MTK_CPU_CLK_250MHZ); case 1: return (MTK_CPU_CLK_384MHZ); case 2: return (MTK_CPU_CLK_480MHZ); case 3: return (MTK_CPU_CLK_500MHZ); } /* Never reached */ return (0); } static uint32_t mtk_detect_cpuclk_rt5350(bus_space_tag_t bst, bus_space_handle_t bsh) { uint32_t val1, val2; val1 = val2 = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG); val1 >>= RT5350_CPU_CLKSEL_OFF1; val2 >>= RT5350_CPU_CLKSEL_OFF2; val1 &= RT5350_CPU_CLKSEL_MSK; val2 &= RT5350_CPU_CLKSEL_MSK; val1 |= (val2 << 1); switch (val1) { case 0: return (MTK_CPU_CLK_360MHZ); case 1: /* Reserved value, but we return UNKNOWN */ return (MTK_CPU_CLK_UNKNOWN); case 2: return (MTK_CPU_CLK_320MHZ); case 3: return (MTK_CPU_CLK_300MHZ); } /* Never reached */ return (0); } static uint32_t mtk_detect_cpuclk_mt7620(bus_space_tag_t bst, bus_space_handle_t bsh) { uint32_t val, mul, div, res; val = bus_space_read_4(bst, bsh, SYSCTL_MT7620_CPLL_CFG1); if (val & MT7620_CPU_CLK_AUX0) return (MTK_CPU_CLK_480MHZ); val = bus_space_read_4(bst, bsh, SYSCTL_MT7620_CPLL_CFG0); if (!(val & MT7620_CPLL_SW_CFG)) return (MTK_CPU_CLK_600MHZ); mul = MT7620_PLL_MULT_RATIO_BASE + ((val >> MT7620_PLL_MULT_RATIO_OFF) & MT7620_PLL_MULT_RATIO_MSK); div = (val >> MT7620_PLL_DIV_RATIO_OFF) & MT7620_PLL_DIV_RATIO_MSK; if (div != MT7620_PLL_DIV_RATIO_MSK) div += MT7620_PLL_DIV_RATIO_BASE; else div = MT7620_PLL_DIV_RATIO_MAX; res = (MT7620_XTAL_40 * mul) / div; return (MTK_MHZ(res)); } static uint32_t mtk_detect_cpuclk_mt7621(bus_space_tag_t bst, bus_space_handle_t bsh) { uint32_t val, div, res; val = bus_space_read_4(bst, bsh, SYSCTL_CLKCFG0); if (val & MT7621_USES_MEMDIV) { div = bus_space_read_4(bst, bsh, MTK_MT7621_CLKDIV_REG); div >>= MT7621_MEMDIV_OFF; div &= MT7621_MEMDIV_MSK; div += MT7621_MEMDIV_BASE; val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG); val >>= MT7621_CLKSEL_OFF; val &= MT7621_CLKSEL_MSK; if (val >= MT7621_CLKSEL_25MHZ_VAL) res = div * MT7621_CLKSEL_25MHZ; else if (val >= MT7621_CLKSEL_20MHZ_VAL) res = div * MT7621_CLKSEL_20MHZ; else res = div * 0; /* XXX: not sure about this */ } else { val = bus_space_read_4(bst, bsh, SYSCTL_CUR_CLK_STS); div = (val >> MT7621_CLK_STS_DIV_OFF) & MT7621_CLK_STS_MSK; val &= MT7621_CLK_STS_MSK; res = (MT7621_CLK_STS_BASE * val) / div; } return (MTK_MHZ(res)); } static uint32_t mtk_detect_cpuclk_mt7628(bus_space_tag_t bst, bus_space_handle_t bsh) { uint32_t val; val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG); val >>= MT7628_CPU_CLKSEL_OFF; val &= MT7628_CPU_CLKSEL_MSK; if (val) return (MTK_CPU_CLK_580MHZ); return (MTK_CPU_CLK_575MHZ); } void mtk_soc_try_early_detect(void) { bus_space_tag_t bst; bus_space_handle_t bsh; uint32_t base; phandle_t node; int i; if ((node = OF_finddevice("/")) == -1) return; for (i = 0; compat_data[i].ocd_str != NULL; i++) { if (fdt_is_compatible(node, compat_data[i].ocd_str)) { mtk_soc_socid = compat_data[i].ocd_data; break; } } if (mtk_soc_socid == MTK_SOC_UNKNOWN) { /* We don't know the SoC, so we don't know how to get clocks */ return; } bst = fdtbus_bs_tag; if (mtk_soc_socid == MTK_SOC_MT7621) base = MTK_MT7621_BASE; else base = MTK_DEFAULT_BASE; if (bus_space_map(bst, base, MTK_DEFAULT_SIZE, 0, &bsh)) return; /* First, figure out the CPU clock */ switch (mtk_soc_socid) { case MTK_SOC_RT3050: /* fallthrough */ case MTK_SOC_RT3052: mtk_soc_cpuclk = mtk_detect_cpuclk_rt305x(bst, bsh); break; case MTK_SOC_RT3350: mtk_soc_cpuclk = MTK_CPU_CLK_320MHZ; break; case MTK_SOC_RT3352: mtk_soc_cpuclk = mtk_detect_cpuclk_rt3352(bst, bsh); break; case MTK_SOC_RT3662: /* fallthrough */ case MTK_SOC_RT3883: mtk_soc_cpuclk = mtk_detect_cpuclk_rt3883(bst, bsh); break; case MTK_SOC_RT5350: mtk_soc_cpuclk = mtk_detect_cpuclk_rt5350(bst, bsh); break; case MTK_SOC_MT7620A: /* fallthrough */ case MTK_SOC_MT7620N: mtk_soc_cpuclk = mtk_detect_cpuclk_mt7620(bst, bsh); break; case MTK_SOC_MT7621: mtk_soc_cpuclk = mtk_detect_cpuclk_mt7621(bst, bsh); break; case MTK_SOC_MT7628: /* fallthrough */ case MTK_SOC_MT7688: mtk_soc_cpuclk = mtk_detect_cpuclk_mt7628(bst, bsh); break; default: /* We don't know the SoC, so we can't find the CPU clock */ break; } /* Now figure out the timer clock */ if (mtk_soc_socid == MTK_SOC_MT7621) { #ifdef notyet /* * We use the GIC timer for timing source and its clock freq is * the same as the CPU's clock freq */ mtk_soc_timerclk = mtk_soc_cpuclk; #else /* * When GIC timer and MIPS timer are ready to co-exist and * GIC timer is actually implemented, we need to switch to it. * Until then we use a fake GIC timer, which is actually a * normal MIPS ticker, so the timer clock is half the CPU clock */ mtk_soc_timerclk = mtk_soc_cpuclk / 2; #endif } else { /* * We use the MIPS ticker for the rest for now, so * the CPU clock is divided by 2 */ mtk_soc_timerclk = mtk_soc_cpuclk / 2; } switch (mtk_soc_socid) { case MTK_SOC_RT3350: /* fallthrough */ case MTK_SOC_RT3050: /* fallthrough */ case MTK_SOC_RT3052: /* UART clock is CPU clock / 3 */ mtk_soc_uartclk = mtk_soc_cpuclk / MTK_UARTDIV_3; break; case MTK_SOC_RT3352: /* fallthrough */ case MTK_SOC_RT3662: /* fallthrough */ case MTK_SOC_RT3883: /* fallthrough */ case MTK_SOC_RT5350: /* fallthrough */ case MTK_SOC_MT7620A: /* fallthrough */ case MTK_SOC_MT7620N: /* fallthrough */ case MTK_SOC_MT7628: /* fallthrough */ case MTK_SOC_MT7688: /* UART clock is always 40MHz */ mtk_soc_uartclk = MTK_UART_CLK_40MHZ; break; case MTK_SOC_MT7621: /* UART clock is always 50MHz */ mtk_soc_uartclk = MTK_UART_CLK_50MHZ; break; default: /* We don't know the SoC, so we don't know the UART clock */ break; } bus_space_unmap(bst, bsh, MTK_DEFAULT_SIZE); } uint32_t mtk_soc_get_uartclk(void) { return mtk_soc_uartclk; } uint32_t mtk_soc_get_cpuclk(void) { return mtk_soc_cpuclk; } uint32_t mtk_soc_get_timerclk(void) { return mtk_soc_timerclk; } uint32_t mtk_soc_get_socid(void) { return mtk_soc_socid; } /* * The following are generic reset and clock functions */ /* Default reset time is 100ms */ #define DEFAULT_RESET_TIME 100000 int mtk_soc_reset_device(device_t dev) { int res; res = fdt_reset_assert_all(dev); if (res == 0) { DELAY(DEFAULT_RESET_TIME); res = fdt_reset_deassert_all(dev); if (res == 0) DELAY(DEFAULT_RESET_TIME); } return (res); } int mtk_soc_stop_clock(device_t dev) { return (fdt_clock_disable_all(dev)); } int mtk_soc_start_clock(device_t dev) { return (fdt_clock_enable_all(dev)); } int mtk_soc_assert_reset(device_t dev) { return (fdt_reset_assert_all(dev)); } int mtk_soc_deassert_reset(device_t dev) { return (fdt_reset_deassert_all(dev)); } void mtk_soc_reset(void) { mtk_sysctl_clr_set(SYSCTL_RSTCTRL, 0, 1); mtk_sysctl_clr_set(SYSCTL_RSTCTRL, 1, 0); } Index: head/sys/mips/mediatek/mtk_usb_phy.c =================================================================== --- head/sys/mips/mediatek/mtk_usb_phy.c (revision 298058) +++ head/sys/mips/mediatek/mtk_usb_phy.c (revision 298059) @@ -1,324 +1,325 @@ /*- * Copyright (c) 2016 Stanislav Galabov. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define RESET_ASSERT_DELAY 1000 #define RESET_DEASSERT_DELAY 10000 struct mtk_usb_phy_softc { device_t dev; struct resource * res; uint32_t fm_base; uint32_t u2_base; uint32_t sr_coef; uint32_t socid; }; #define USB_PHY_READ(_sc, _off) bus_read_4((_sc)->res, (_off)) #define USB_PHY_WRITE(_sc, _off, _val) bus_write_4((_sc)->res, (_off), (_val)) #define USB_PHY_CLR_SET(_sc, _off, _clr, _set) \ USB_PHY_WRITE(_sc, _off, ((USB_PHY_READ(_sc, _off) & ~(_clr)) | (_set))) #define USB_PHY_READ_U2(_sc, _off) \ USB_PHY_READ((_sc), ((_sc)->u2_base + (_off))) #define USB_PHY_WRITE_U2(_sc, _off, _val) \ USB_PHY_WRITE((_sc), ((_sc)->u2_base + (_off)), (_val)) #define USB_PHY_CLR_SET_U2(_sc, _off, _clr, _set) \ USB_PHY_WRITE_U2((_sc), (_off), ((USB_PHY_READ_U2((_sc), (_off)) & \ ~(_clr)) | (_set))) #define USB_PHY_BARRIER(_sc) bus_barrier((_sc)->res, 0, 0, \ BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ) #define USB_PHY_READ_FM(_sc, _off) \ USB_PHY_READ((_sc), ((_sc)->fm_base + (_off))) #define USB_PHY_WRITE_FM(_sc, _off) \ USB_PHY_WRITE((_sc), ((_sc)->fm_base + (_off)), (_val)) #define USB_PHY_CLR_SET_FM(_sc, _off, _clr, _set) \ USB_PHY_WRITE_U2((_sc), (_off), ((USB_PHY_READ_U2((_sc), (_off)) & \ ~(_clr)) | (_set))) static void mtk_usb_phy_mt7621_init(device_t); static void mtk_usb_phy_mt7628_init(device_t); static struct ofw_compat_data compat_data[] = { - { "ralink,mt7620a-usbphy", MTK_SOC_MT7620A }, + { "ralink,mt7620-usbphy", MTK_SOC_MT7620A }, { "ralink,mt7628an-usbphy", MTK_SOC_MT7628 }, - { "ralink,rt3xxx-usbphy", MTK_SOC_RT3352 }, + { "ralink,rt3352-usbphy", MTK_SOC_RT3352 }, + { "ralink,rt3050-usbphy", MTK_SOC_RT3050 }, { NULL, MTK_SOC_UNKNOWN } }; static int mtk_usb_phy_probe(device_t dev) { struct mtk_usb_phy_softc *sc = device_get_softc(dev); if (!ofw_bus_status_okay(dev)) return (ENXIO); if ((sc->socid = ofw_bus_search_compatible(dev, compat_data)->ocd_data) == MTK_SOC_UNKNOWN) return (ENXIO); device_set_desc(dev, "MTK USB PHY"); return (0); } static int mtk_usb_phy_attach(device_t dev) { struct mtk_usb_phy_softc * sc = device_get_softc(dev); phandle_t node; uint32_t val; int rid; sc->dev = dev; /* Get our FDT node and SoC id */ node = ofw_bus_get_node(dev); /* Now let's see about setting USB to host or device mode */ /* XXX: is it the same for all SoCs? */ val = mtk_sysctl_get(SYSCTL_SYSCFG1); if (OF_hasprop(node, "mtk,usb-device")) val &= ~SYSCFG1_USB_HOST_MODE; else val |= SYSCFG1_USB_HOST_MODE; mtk_sysctl_set(SYSCTL_SYSCFG1, val); /* If we have clocks defined - enable them */ if (OF_hasprop(node, "clocks")) fdt_clock_enable_all(dev); /* If we have resets defined - perform a reset sequence */ if (OF_hasprop(node, "resets")) { fdt_reset_assert_all(dev); DELAY(RESET_ASSERT_DELAY); fdt_reset_deassert_all(dev); DELAY(RESET_DEASSERT_DELAY); } /* Careful, some devices actually require resources */ if (OF_hasprop(node, "reg")) { rid = 0; sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->res == NULL) { device_printf(dev, "could not map memory\n"); return (ENXIO); } } else { sc->res = NULL; } /* Some SoCs require specific USB PHY init... handle these */ switch (sc->socid) { case MTK_SOC_MT7628: /* Fallthrough */ case MTK_SOC_MT7688: if (sc->res == NULL) return (ENXIO); sc->fm_base = MT7628_FM_FEG_BASE; sc->u2_base = MT7628_U2_BASE; sc->sr_coef = MT7628_SR_COEF; mtk_usb_phy_mt7628_init(dev); break; case MTK_SOC_MT7621: if (sc->res == NULL) return (ENXIO); sc->fm_base = MT7621_FM_FEG_BASE; sc->u2_base = MT7621_U2_BASE; sc->sr_coef = MT7621_SR_COEF; mtk_usb_phy_mt7621_init(dev); break; } /* We no longer need the resources, release them */ if (sc->res != NULL) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res); return (0); } static int mtk_usb_phy_detach(device_t dev) { struct mtk_usb_phy_softc *sc = device_get_softc(dev); phandle_t node; /* Get our FDT node */ node = ofw_bus_get_node(dev); /* If we have resets defined - assert them */ if (OF_hasprop(node, "resets")) fdt_reset_assert_all(dev); /* If we have clocks defined - disable them */ if (OF_hasprop(node, "clocks")) fdt_clock_disable_all(dev); /* Finally, release resources, if any were allocated */ if (sc->res != NULL) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res); return (0); } /* * Things currently seem to work a lot better without slew rate calibration * both on MT7621 and MT7688, so we leave it out for now. */ #ifdef notyet static void mtk_usb_phy_slew_rate_calibration(struct mtk_usb_phy_softc *sc) { uint32_t val; int i; USB_PHY_CLR_SET_U2(sc, U2_PHY_ACR0, 0, SRCAL_EN); USB_PHY_BARRIER(sc); DELAY(1000); USB_PHY_CLR_SET_FM(sc, U2_PHY_FMMONR1, 0, FRCK_EN); USB_PHY_BARRIER(sc); USB_PHY_CLR_SET_FM(sc, U2_PHY_FMCR0, CYCLECNT, 0x400); USB_PHY_BARRIER(sc); USB_PHY_CLR_SET_FM(sc, U2_PHY_FMCR0, 0, FDET_EN); USB_PHY_BARRIER(sc); for (i = 0; i < 1000; i++) { if ((val = USB_PHY_READ_FM(sc, U2_PHY_FMMONR0)) != 0) { device_printf(sc->dev, "DONE with FDET\n"); break; } DELAY(10000); } device_printf(sc->dev, "After FDET\n"); USB_PHY_CLR_SET_FM(sc, U2_PHY_FMCR0, FDET_EN, 0); USB_PHY_BARRIER(sc); USB_PHY_CLR_SET_FM(sc, U2_PHY_FMMONR1, FRCK_EN, 0); USB_PHY_BARRIER(sc); USB_PHY_CLR_SET_U2(sc, U2_PHY_ACR0, SRCAL_EN, 0); USB_PHY_BARRIER(sc); DELAY(1000); if (val == 0) { USB_PHY_CLR_SET_U2(sc, U2_PHY_ACR0, SRCTRL, 0x4 << SRCTRL_OFF); USB_PHY_BARRIER(sc); } else { val = ((((1024 * 25 * sc->sr_coef) / val) + 500) / 1000) & SRCTRL_MSK; USB_PHY_CLR_SET_U2(sc, U2_PHY_ACR0, SRCTRL, val << SRCTRL_OFF); USB_PHY_BARRIER(sc); } } #endif static void mtk_usb_phy_mt7621_init(device_t dev) { #ifdef notyet struct mtk_usb_phy_softc *sc = device_get_softc(dev); /* Slew rate calibration only, but for 2 ports */ mtk_usb_phy_slew_rate_calibration(sc); sc->u2_base = MT7621_U2_BASE_P1; mtk_usb_phy_slew_rate_calibration(sc); #endif } static void mtk_usb_phy_mt7628_init(device_t dev) { struct mtk_usb_phy_softc *sc = device_get_softc(dev); /* XXX: possibly add barriers between the next writes? */ USB_PHY_WRITE_U2(sc, U2_PHY_DCR0, 0x00ffff02); USB_PHY_BARRIER(sc); USB_PHY_WRITE_U2(sc, U2_PHY_DCR0, 0x00555502); USB_PHY_BARRIER(sc); USB_PHY_WRITE_U2(sc, U2_PHY_DCR0, 0x00aaaa02); USB_PHY_BARRIER(sc); USB_PHY_WRITE_U2(sc, U2_PHY_DCR0, 0x00000402); USB_PHY_BARRIER(sc); USB_PHY_WRITE_U2(sc, U2_PHY_AC0, 0x0048086a); USB_PHY_BARRIER(sc); USB_PHY_WRITE_U2(sc, U2_PHY_AC1, 0x4400001c); USB_PHY_BARRIER(sc); USB_PHY_WRITE_U2(sc, U2_PHY_ACR3, 0xc0200000); USB_PHY_BARRIER(sc); USB_PHY_WRITE_U2(sc, U2_PHY_DTM0, 0x02000000); USB_PHY_BARRIER(sc); #ifdef notyet /* Slew rate calibration */ mtk_usb_phy_slew_rate_calibration(sc); #endif } static device_method_t mtk_usb_phy_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mtk_usb_phy_probe), DEVMETHOD(device_attach, mtk_usb_phy_attach), DEVMETHOD(device_detach, mtk_usb_phy_detach), DEVMETHOD(device_suspend, bus_generic_suspend), DEVMETHOD(device_resume, bus_generic_resume), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD_END }; static driver_t mtk_usb_phy_driver = { .name = "usbphy", .methods = mtk_usb_phy_methods, .size = sizeof(struct mtk_usb_phy_softc), }; static devclass_t mtk_usb_phy_devclass; DRIVER_MODULE(usbphy, simplebus, mtk_usb_phy_driver, mtk_usb_phy_devclass, 0, 0); Index: head/sys/mips/mediatek/mtk_xhci.c =================================================================== --- head/sys/mips/mediatek/mtk_xhci.c (revision 298058) +++ head/sys/mips/mediatek/mtk_xhci.c (revision 298059) @@ -1,297 +1,297 @@ #include __FBSDID("$FreeBSD$"); /*- * Copyright (c) 2015 Stanislav Galabov. All rights reserved. * Copyright (c) 2010,2011 Aleksandr Rybalko. All rights reserved. * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define XHCI_HC_DEVSTR "MTK USB 3.0 controller" static device_probe_t mtk_xhci_fdt_probe; static device_attach_t mtk_xhci_fdt_attach; static device_detach_t mtk_xhci_fdt_detach; static void mtk_xhci_fdt_init(device_t dev); static int mtk_xhci_fdt_probe(device_t self) { if (!ofw_bus_status_okay(self)) return (ENXIO); - if (!ofw_bus_is_compatible(self, "mtk,usb-xhci")) + if (!ofw_bus_is_compatible(self, "mediatek,mt8173-xhci")) return (ENXIO); device_set_desc(self, XHCI_HC_DEVSTR); return (BUS_PROBE_DEFAULT); } static int mtk_xhci_fdt_attach(device_t self) { struct xhci_softc *sc = device_get_softc(self); int err; int rid; /* initialise some bus fields */ sc->sc_bus.parent = self; sc->sc_bus.devices = sc->sc_devices; sc->sc_bus.devices_max = XHCI_MAX_DEVICES; rid = 0; sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_io_res) { device_printf(self, "Could not map memory\n"); goto error; } sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); sc->sc_io_size = rman_get_size(sc->sc_io_res); mtk_xhci_fdt_init(self); rid = 0; sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); if (sc->sc_irq_res == NULL) { device_printf(self, "Could not allocate irq\n"); goto error; } sc->sc_bus.bdev = device_add_child(self, "usbus", -1); if (!(sc->sc_bus.bdev)) { device_printf(self, "Could not add USB device\n"); goto error; } device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); device_set_desc(sc->sc_bus.bdev, XHCI_HC_DEVSTR); sprintf(sc->sc_vendor, "Mediatek"); err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl); if (err) { device_printf(self, "Could not setup irq, %d\n", err); sc->sc_intr_hdl = NULL; goto error; } err = xhci_init(sc, self, 1); if (err == 0) err = xhci_halt_controller(sc); if (err == 0) err = xhci_start_controller(sc); if (err == 0) err = device_probe_and_attach(sc->sc_bus.bdev); if (err) { device_printf(self, "USB init failed err=%d\n", err); goto error; } return (0); error: mtk_xhci_fdt_detach(self); return (ENXIO); } static int mtk_xhci_fdt_detach(device_t self) { struct xhci_softc *sc = device_get_softc(self); device_t bdev; int err; if (sc->sc_bus.bdev) { bdev = sc->sc_bus.bdev; device_detach(bdev); device_delete_child(self, bdev); } /* during module unload there are lots of children leftover */ device_delete_children(self); if (sc->sc_irq_res && sc->sc_intr_hdl) { /* * only call xhci_detach() after xhci_init() */ xhci_uninit(sc); err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); if (err) device_printf(self, "Could not tear down irq, %d\n", err); sc->sc_intr_hdl = NULL; } if (sc->sc_irq_res) { bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res); sc->sc_irq_res = NULL; } if (sc->sc_io_res) { bus_release_resource(self, SYS_RES_MEMORY, 0, sc->sc_io_res); sc->sc_io_res = NULL; } return (0); } static device_method_t mtk_xhci_fdt_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mtk_xhci_fdt_probe), DEVMETHOD(device_attach, mtk_xhci_fdt_attach), DEVMETHOD(device_detach, mtk_xhci_fdt_detach), DEVMETHOD(device_suspend, bus_generic_suspend), DEVMETHOD(device_resume, bus_generic_resume), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD_END }; static driver_t mtk_xhci_fdt_driver = { .name = "xhci", .methods = mtk_xhci_fdt_methods, .size = sizeof(struct xhci_softc), }; static devclass_t mtk_xhci_fdt_devclass; DRIVER_MODULE(xhci, simplebus, mtk_xhci_fdt_driver, mtk_xhci_fdt_devclass, 0, 0); #define USB_HDMA_CFG 0x950 #define USB_HDMA_CFG_MT7621_VAL 0x10E0E0C #define U3_LTSSM_TIMING_PARAM3 0x2514 #define U3_LTSSM_TIMING_VAL 0x3E8012C #define SYNC_HS_EOF 0x938 #define SYNC_HS_EOF_VAL 0x201F3 #define USB_IP_SPAR0 0x107C8 #define USB_IP_SPAR0_VAL 1 #define U2_PHY_BASE_P0 0x10800 #define U2_PHY_BASE_P1 0x11000 #define U2_PHYD_CR1 0x64 #define U2_PHYD_CR1_MASK (3<<18) #define U2_PHYD_CR1_VAL (1<<18) #define USB_IP_PW_CTRL 0x10700 #define USB_IP_PW_CTRL_1 0x10704 #define USB_IP_CAP 0x10724 #define USB_U3_CTRL(p) (0x10730 + ((p) * 0x08)) #define USB_U2_CTRL(p) (0x10750 + ((p) * 0x08)) #define USB_IP_SW_RST (1 << 0) #define USB_IP_PDN (1 << 0) #define USB_PORT_DIS (1 << 0) #define USB_PORT_PDN (1 << 1) #define U3_PORT_NUM(p) (p & 0xFF) #define U2_PORT_NUM(p) ((p>>8) & 0xFF) #define RD4(_sc, _reg) bus_read_4((_sc)->sc_io_res, (_reg)) #define WR4(_sc, _reg, _val) bus_write_4((_sc)->sc_io_res, (_reg), (_val)) #define CLRSET4(_sc, _reg, _clr, _set) \ WR4((_sc), (_reg), (RD4((_sc), (_reg)) & ~(_clr)) | (_set)) static void mtk_xhci_fdt_init(device_t dev) { struct xhci_softc *sc; uint32_t temp, u3_ports, u2_ports, i; sc = device_get_softc(dev); temp = RD4(sc, USB_IP_CAP); u3_ports = U3_PORT_NUM(temp); u2_ports = U2_PORT_NUM(temp); device_printf(dev, "%d USB3 ports, %d USB2 ports\n", u3_ports, u2_ports); CLRSET4(sc, USB_IP_PW_CTRL, 0, USB_IP_SW_RST); CLRSET4(sc, USB_IP_PW_CTRL, USB_IP_SW_RST, 0); CLRSET4(sc, USB_IP_PW_CTRL_1, USB_IP_PDN, 0); for (i = 0; i < u3_ports; i++) CLRSET4(sc, USB_U3_CTRL(i), USB_PORT_PDN | USB_PORT_DIS, 0); for (i = 0; i < u2_ports; i++) CLRSET4(sc, USB_U2_CTRL(i), USB_PORT_PDN | USB_PORT_DIS, 0); DELAY(100000); WR4(sc, USB_HDMA_CFG, USB_HDMA_CFG_MT7621_VAL); WR4(sc, U3_LTSSM_TIMING_PARAM3, U3_LTSSM_TIMING_VAL); WR4(sc, SYNC_HS_EOF, SYNC_HS_EOF_VAL); WR4(sc, USB_IP_SPAR0, USB_IP_SPAR0_VAL); CLRSET4(sc, U2_PHY_BASE_P0 + U2_PHYD_CR1, U2_PHYD_CR1_MASK, U2_PHYD_CR1_VAL); CLRSET4(sc, U2_PHY_BASE_P1 + U2_PHYD_CR1, U2_PHYD_CR1_MASK, U2_PHYD_CR1_VAL); }