Index: head/sys/arm/allwinner/a10_clk.c =================================================================== --- head/sys/arm/allwinner/a10_clk.c (revision 297626) +++ head/sys/arm/allwinner/a10_clk.c (nonexistent) @@ -1,862 +0,0 @@ -/*- - * Copyright (c) 2013 Ganbold Tsagaankhuu - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* Simple clock driver for Allwinner A10 */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "a10_clk.h" - -#define TCON_PLL_WORST 1000000 -#define TCON_PLL_N_MIN 1 -#define TCON_PLL_N_MAX 15 -#define TCON_PLL_M_MIN 9 -#define TCON_PLL_M_MAX 127 -#define TCON_PLLREF_SINGLE 3000 /* kHz */ -#define TCON_PLLREF_DOUBLE 6000 /* kHz */ -#define TCON_RATE_KHZ(rate_hz) ((rate_hz) / 1000) -#define TCON_RATE_HZ(rate_khz) ((rate_khz) * 1000) -#define HDMI_DEFAULT_RATE 297000000 -#define DEBE_DEFAULT_RATE 300000000 - -struct a10_ccm_softc { - struct resource *res; - bus_space_tag_t bst; - bus_space_handle_t bsh; - struct mtx mtx; - int pll6_enabled; - int ehci_cnt; - int ohci_cnt; - int usbphy_cnt; - int usb_cnt; -}; - -static struct a10_ccm_softc *a10_ccm_sc = NULL; - -static int a10_clk_usbphy_activate(struct a10_ccm_softc *sc); -static int a10_clk_usbphy_deactivate(struct a10_ccm_softc *sc); -static int a10_clk_usb_activate(struct a10_ccm_softc *sc); -static int a10_clk_usb_deactivate(struct a10_ccm_softc *sc); - -#define CCM_LOCK(sc) mtx_lock(&(sc)->mtx); -#define CCM_UNLOCK(sc) mtx_unlock(&(sc)->mtx); -#define CCM_LOCK_ASSERT(sc) mtx_assert(&(sc)->mtx, MA_OWNED) -#define ccm_read_4(sc, reg) \ - bus_space_read_4((sc)->bst, (sc)->bsh, (reg)) -#define ccm_write_4(sc, reg, val) \ - bus_space_write_4((sc)->bst, (sc)->bsh, (reg), (val)) - -static int -a10_ccm_probe(device_t dev) -{ - - if (!ofw_bus_status_okay(dev)) - return (ENXIO); - - if (ofw_bus_is_compatible(dev, "allwinner,sun4i-ccm")) { - device_set_desc(dev, "Allwinner Clock Control Module"); - return(BUS_PROBE_DEFAULT); - } - - return (ENXIO); -} - -static int -a10_ccm_attach(device_t dev) -{ - struct a10_ccm_softc *sc = device_get_softc(dev); - int rid = 0; - - if (a10_ccm_sc) - return (ENXIO); - - sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); - if (!sc->res) { - device_printf(dev, "could not allocate resource\n"); - return (ENXIO); - } - - sc->bst = rman_get_bustag(sc->res); - sc->bsh = rman_get_bushandle(sc->res); - - mtx_init(&sc->mtx, "a10_ccm", NULL, MTX_DEF); - - a10_ccm_sc = sc; - - return (0); -} - -static device_method_t a10_ccm_methods[] = { - DEVMETHOD(device_probe, a10_ccm_probe), - DEVMETHOD(device_attach, a10_ccm_attach), - { 0, 0 } -}; - -static driver_t a10_ccm_driver = { - "a10_ccm", - a10_ccm_methods, - sizeof(struct a10_ccm_softc), -}; - -static devclass_t a10_ccm_devclass; - -EARLY_DRIVER_MODULE(a10_ccm, simplebus, a10_ccm_driver, a10_ccm_devclass, 0, 0, - BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); - -int -a10_clk_ehci_activate(void) -{ - struct a10_ccm_softc *sc = a10_ccm_sc; - uint32_t reg_value; - - if (sc == NULL) - return (ENXIO); - - CCM_LOCK(sc); - - if (++sc->ehci_cnt == 1) { - /* Gating AHB clock for USB */ - reg_value = ccm_read_4(sc, CCM_AHB_GATING0); - reg_value |= CCM_AHB_GATING_EHCI0; /* AHB clock gate ehci0 */ - reg_value |= CCM_AHB_GATING_EHCI1; /* AHB clock gate ehci1 */ - ccm_write_4(sc, CCM_AHB_GATING0, reg_value); - } - - a10_clk_usb_activate(sc); - a10_clk_usbphy_activate(sc); - - CCM_UNLOCK(sc); - - return (0); -} - -int -a10_clk_ehci_deactivate(void) -{ - struct a10_ccm_softc *sc = a10_ccm_sc; - uint32_t reg_value; - - if (sc == NULL) - return (ENXIO); - - CCM_LOCK(sc); - - if (--sc->ehci_cnt == 0) { - /* Disable gating AHB clock for USB */ - reg_value = ccm_read_4(sc, CCM_AHB_GATING0); - reg_value &= ~CCM_AHB_GATING_EHCI0; /* disable AHB clock gate ehci0 */ - reg_value &= ~CCM_AHB_GATING_EHCI1; /* disable AHB clock gate ehci1 */ - ccm_write_4(sc, CCM_AHB_GATING0, reg_value); - } - - a10_clk_usb_deactivate(sc); - a10_clk_usbphy_deactivate(sc); - - CCM_UNLOCK(sc); - - return (0); -} - -int -a10_clk_ohci_activate(void) -{ - struct a10_ccm_softc *sc = a10_ccm_sc; - uint32_t reg_value; - - if (sc == NULL) - return (ENXIO); - - CCM_LOCK(sc); - - if (++sc->ohci_cnt == 1) { - /* Gating AHB clock for USB */ - reg_value = ccm_read_4(sc, CCM_AHB_GATING0); - reg_value |= CCM_AHB_GATING_OHCI0; /* AHB clock gate ohci0 */ - reg_value |= CCM_AHB_GATING_OHCI1; /* AHB clock gate ohci1 */ - ccm_write_4(sc, CCM_AHB_GATING0, reg_value); - - /* Enable clock for USB */ - reg_value = ccm_read_4(sc, CCM_USB_CLK); - reg_value |= CCM_SCLK_GATING_OHCI0; - reg_value |= CCM_SCLK_GATING_OHCI1; - ccm_write_4(sc, CCM_USB_CLK, reg_value); - } - - a10_clk_usb_activate(sc); - a10_clk_usbphy_activate(sc); - - CCM_UNLOCK(sc); - - return (0); -} - -int -a10_clk_ohci_deactivate(void) -{ - struct a10_ccm_softc *sc = a10_ccm_sc; - uint32_t reg_value; - - if (sc == NULL) - return (ENXIO); - - CCM_LOCK(sc); - - if (--sc->ohci_cnt == 0) { - /* Disable clock for USB */ - reg_value = ccm_read_4(sc, CCM_USB_CLK); - reg_value &= ~CCM_SCLK_GATING_OHCI0; - reg_value &= ~CCM_SCLK_GATING_OHCI1; - ccm_write_4(sc, CCM_USB_CLK, reg_value); - - /* Disable gating AHB clock for USB */ - reg_value = ccm_read_4(sc, CCM_AHB_GATING0); - reg_value &= ~CCM_AHB_GATING_OHCI0; /* disable AHB clock gate ohci0 */ - reg_value &= ~CCM_AHB_GATING_OHCI1; /* disable AHB clock gate ohci1 */ - ccm_write_4(sc, CCM_AHB_GATING0, reg_value); - } - - a10_clk_usb_deactivate(sc); - a10_clk_usbphy_deactivate(sc); - - CCM_UNLOCK(sc); - - return (0); -} - -static int -a10_clk_usb_activate(struct a10_ccm_softc *sc) -{ - uint32_t reg_value; - - CCM_LOCK_ASSERT(sc); - - if (++sc->usb_cnt == 1) { - /* Gating AHB clock for USB */ - reg_value = ccm_read_4(sc, CCM_AHB_GATING0); - reg_value |= CCM_AHB_GATING_USB0; /* AHB clock gate usb0 */ - ccm_write_4(sc, CCM_AHB_GATING0, reg_value); - } - - return (0); -} - -static int -a10_clk_usb_deactivate(struct a10_ccm_softc *sc) -{ - uint32_t reg_value; - - CCM_LOCK_ASSERT(sc); - - if (--sc->usb_cnt == 0) { - /* Disable gating AHB clock for USB */ - reg_value = ccm_read_4(sc, CCM_AHB_GATING0); - reg_value &= ~CCM_AHB_GATING_USB0; /* disable AHB clock gate usb0 */ - ccm_write_4(sc, CCM_AHB_GATING0, reg_value); - } - - return (0); -} - -static int -a10_clk_usbphy_activate(struct a10_ccm_softc *sc) -{ - uint32_t reg_value; - - CCM_LOCK_ASSERT(sc); - - if (++sc->usbphy_cnt == 1) { - /* Enable clock for USB */ - reg_value = ccm_read_4(sc, CCM_USB_CLK); - reg_value |= CCM_USB_PHY; /* USBPHY */ - reg_value |= CCM_USBPHY0_RESET; /* disable reset for USBPHY0 */ - reg_value |= CCM_USBPHY1_RESET; /* disable reset for USBPHY1 */ - reg_value |= CCM_USBPHY2_RESET; /* disable reset for USBPHY2 */ - ccm_write_4(sc, CCM_USB_CLK, reg_value); - } - - return (0); -} - -static int -a10_clk_usbphy_deactivate(struct a10_ccm_softc *sc) -{ - uint32_t reg_value; - - CCM_LOCK_ASSERT(sc); - - if (--sc->usbphy_cnt == 0) { - /* Disable clock for USB */ - reg_value = ccm_read_4(sc, CCM_USB_CLK); - reg_value &= ~CCM_USB_PHY; /* USBPHY */ - reg_value &= ~CCM_USBPHY0_RESET; /* reset for USBPHY0 */ - reg_value &= ~CCM_USBPHY1_RESET; /* reset for USBPHY1 */ - reg_value &= ~CCM_USBPHY2_RESET; /* reset for USBPHY2 */ - ccm_write_4(sc, CCM_USB_CLK, reg_value); - } - - return (0); -} - -int -a10_clk_emac_activate(void) -{ - struct a10_ccm_softc *sc = a10_ccm_sc; - uint32_t reg_value; - - if (sc == NULL) - return (ENXIO); - - /* Gating AHB clock for EMAC */ - reg_value = ccm_read_4(sc, CCM_AHB_GATING0); - reg_value |= CCM_AHB_GATING_EMAC; - ccm_write_4(sc, CCM_AHB_GATING0, reg_value); - - return (0); -} - -int -a10_clk_gmac_activate(phandle_t node) -{ - char *phy_type; - struct a10_ccm_softc *sc; - uint32_t reg_value; - - sc = a10_ccm_sc; - if (sc == NULL) - return (ENXIO); - - /* Gating AHB clock for GMAC */ - reg_value = ccm_read_4(sc, CCM_AHB_GATING1); - reg_value |= CCM_AHB_GATING_GMAC; - ccm_write_4(sc, CCM_AHB_GATING1, reg_value); - - /* Set GMAC mode. */ - reg_value = CCM_GMAC_CLK_MII; - if (OF_getprop_alloc(node, "phy-mode", 1, (void **)&phy_type) > 0) { - if (strcasecmp(phy_type, "rgmii") == 0) - reg_value = CCM_GMAC_CLK_RGMII | CCM_GMAC_MODE_RGMII; - else if (strcasecmp(phy_type, "rgmii-bpi") == 0) { - reg_value = CCM_GMAC_CLK_RGMII | CCM_GMAC_MODE_RGMII; - reg_value |= (3 << CCM_GMAC_CLK_DELAY_SHIFT); - } - free(phy_type, M_OFWPROP); - } - ccm_write_4(sc, CCM_GMAC_CLK, reg_value); - - return (0); -} - -static void -a10_clk_pll6_enable(void) -{ - struct a10_ccm_softc *sc; - uint32_t reg_value; - - /* - * SATA needs PLL6 to be a 100MHz clock. - * The SATA output frequency is 24MHz * n * k / m / 6. - * To get to 100MHz, k & m must be equal and n must be 25. - * For other uses the output frequency is 24MHz * n * k / 2. - */ - sc = a10_ccm_sc; - if (sc->pll6_enabled) - return; - reg_value = ccm_read_4(sc, CCM_PLL6_CFG); - reg_value &= ~CCM_PLL_CFG_BYPASS; - reg_value &= ~(CCM_PLL_CFG_FACTOR_K | CCM_PLL_CFG_FACTOR_M | - CCM_PLL_CFG_FACTOR_N); - reg_value |= (25 << CCM_PLL_CFG_FACTOR_N_SHIFT); - reg_value |= CCM_PLL6_CFG_SATA_CLKEN; - reg_value |= CCM_PLL_CFG_ENABLE; - ccm_write_4(sc, CCM_PLL6_CFG, reg_value); - sc->pll6_enabled = 1; -} - -static unsigned int -a10_clk_pll6_get_rate(void) -{ - struct a10_ccm_softc *sc; - uint32_t k, n, reg_value; - - sc = a10_ccm_sc; - reg_value = ccm_read_4(sc, CCM_PLL6_CFG); - n = ((reg_value & CCM_PLL_CFG_FACTOR_N) >> CCM_PLL_CFG_FACTOR_N_SHIFT); - k = ((reg_value & CCM_PLL_CFG_FACTOR_K) >> CCM_PLL_CFG_FACTOR_K_SHIFT) + - 1; - - return ((CCM_CLK_REF_FREQ * n * k) / 2); -} - -static int -a10_clk_pll2_set_rate(unsigned int freq) -{ - struct a10_ccm_softc *sc; - uint32_t reg_value; - unsigned int prediv, postdiv, n; - - sc = a10_ccm_sc; - if (sc == NULL) - return (ENXIO); - - reg_value = ccm_read_4(sc, CCM_PLL2_CFG); - reg_value &= ~(CCM_PLL2_CFG_PREDIV | CCM_PLL2_CFG_POSTDIV | - CCM_PLL_CFG_FACTOR_N); - - /* - * Audio Codec needs PLL2 to be either 24576000 Hz or 22579200 Hz - * - * PLL2 output frequency is 24MHz * n / prediv / postdiv. - * To get as close as possible to the desired rate, we use a - * pre-divider of 21 and a post-divider of 4. With these values, - * a multiplier of 86 or 79 gets us close to the target rates. - */ - prediv = 21; - postdiv = 4; - - switch (freq) { - case 24576000: - n = 86; - reg_value |= CCM_PLL_CFG_ENABLE; - break; - case 22579200: - n = 79; - reg_value |= CCM_PLL_CFG_ENABLE; - break; - case 0: - n = 1; - reg_value &= ~CCM_PLL_CFG_ENABLE; - break; - default: - return (EINVAL); - } - - reg_value |= (prediv << CCM_PLL2_CFG_PREDIV_SHIFT); - reg_value |= (postdiv << CCM_PLL2_CFG_POSTDIV_SHIFT); - reg_value |= (n << CCM_PLL_CFG_FACTOR_N_SHIFT); - ccm_write_4(sc, CCM_PLL2_CFG, reg_value); - - return (0); -} - -static int -a10_clk_pll3_set_rate(unsigned int freq) -{ - struct a10_ccm_softc *sc; - uint32_t reg_value; - int m; - - sc = a10_ccm_sc; - if (sc == NULL) - return (ENXIO); - - if (freq == 0) { - /* Disable PLL3 */ - ccm_write_4(sc, CCM_PLL3_CFG, 0); - return (0); - } - - m = freq / TCON_RATE_HZ(TCON_PLLREF_SINGLE); - - reg_value = CCM_PLL_CFG_ENABLE | CCM_PLL3_CFG_MODE_SEL_INT | m; - ccm_write_4(sc, CCM_PLL3_CFG, reg_value); - - return (0); -} - -static unsigned int -a10_clk_pll5x_get_rate(void) -{ - struct a10_ccm_softc *sc; - uint32_t k, n, p, reg_value; - - sc = a10_ccm_sc; - reg_value = ccm_read_4(sc, CCM_PLL5_CFG); - n = ((reg_value & CCM_PLL_CFG_FACTOR_N) >> CCM_PLL_CFG_FACTOR_N_SHIFT); - k = ((reg_value & CCM_PLL_CFG_FACTOR_K) >> CCM_PLL_CFG_FACTOR_K_SHIFT) + - 1; - p = ((reg_value & CCM_PLL5_CFG_OUT_EXT_DIV_P) >> CCM_PLL5_CFG_OUT_EXT_DIV_P_SHIFT); - - return ((CCM_CLK_REF_FREQ * n * k) >> p); -} - -int -a10_clk_ahci_activate(void) -{ - struct a10_ccm_softc *sc; - uint32_t reg_value; - - sc = a10_ccm_sc; - if (sc == NULL) - return (ENXIO); - - a10_clk_pll6_enable(); - - /* Gating AHB clock for SATA */ - reg_value = ccm_read_4(sc, CCM_AHB_GATING0); - reg_value |= CCM_AHB_GATING_SATA; - ccm_write_4(sc, CCM_AHB_GATING0, reg_value); - DELAY(1000); - - ccm_write_4(sc, CCM_SATA_CLK, CCM_PLL_CFG_ENABLE); - - return (0); -} - -int -a10_clk_mmc_activate(int devid) -{ - struct a10_ccm_softc *sc; - uint32_t reg_value; - - sc = a10_ccm_sc; - if (sc == NULL) - return (ENXIO); - - a10_clk_pll6_enable(); - - /* Gating AHB clock for SD/MMC */ - reg_value = ccm_read_4(sc, CCM_AHB_GATING0); - reg_value |= CCM_AHB_GATING_SDMMC0 << devid; - ccm_write_4(sc, CCM_AHB_GATING0, reg_value); - - return (0); -} - -int -a10_clk_mmc_cfg(int devid, int freq) -{ - struct a10_ccm_softc *sc; - uint32_t clksrc, m, n, ophase, phase, reg_value; - unsigned int pll_freq; - - sc = a10_ccm_sc; - if (sc == NULL) - return (ENXIO); - - freq /= 1000; - if (freq <= 400) { - pll_freq = CCM_CLK_REF_FREQ / 1000; - clksrc = CCM_SD_CLK_SRC_SEL_OSC24M; - ophase = 0; - phase = 0; - n = 2; - } else if (freq <= 25000) { - pll_freq = a10_clk_pll6_get_rate() / 1000; - clksrc = CCM_SD_CLK_SRC_SEL_PLL6; - ophase = 0; - phase = 5; - n = 2; - } else if (freq <= 50000) { - pll_freq = a10_clk_pll6_get_rate() / 1000; - clksrc = CCM_SD_CLK_SRC_SEL_PLL6; - ophase = 3; - phase = 5; - n = 0; - } else - return (EINVAL); - m = ((pll_freq / (1 << n)) / (freq)) - 1; - reg_value = ccm_read_4(sc, CCM_MMC0_SCLK_CFG + (devid * 4)); - reg_value &= ~CCM_SD_CLK_SRC_SEL; - reg_value |= (clksrc << CCM_SD_CLK_SRC_SEL_SHIFT); - reg_value &= ~CCM_SD_CLK_PHASE_CTR; - reg_value |= (phase << CCM_SD_CLK_PHASE_CTR_SHIFT); - reg_value &= ~CCM_SD_CLK_DIV_RATIO_N; - reg_value |= (n << CCM_SD_CLK_DIV_RATIO_N_SHIFT); - reg_value &= ~CCM_SD_CLK_OPHASE_CTR; - reg_value |= (ophase << CCM_SD_CLK_OPHASE_CTR_SHIFT); - reg_value &= ~CCM_SD_CLK_DIV_RATIO_M; - reg_value |= m; - reg_value |= CCM_PLL_CFG_ENABLE; - ccm_write_4(sc, CCM_MMC0_SCLK_CFG + (devid * 4), reg_value); - - return (0); -} - -int -a10_clk_i2c_activate(int devid) -{ - struct a10_ccm_softc *sc; - uint32_t reg_value; - - sc = a10_ccm_sc; - if (sc == NULL) - return (ENXIO); - - a10_clk_pll6_enable(); - - /* Gating APB clock for I2C/TWI */ - reg_value = ccm_read_4(sc, CCM_APB1_GATING); - if (devid == 4) - reg_value |= CCM_APB1_GATING_TWI << 15; - else - reg_value |= CCM_APB1_GATING_TWI << devid; - ccm_write_4(sc, CCM_APB1_GATING, reg_value); - - return (0); -} - -int -a10_clk_dmac_activate(void) -{ - struct a10_ccm_softc *sc; - uint32_t reg_value; - - sc = a10_ccm_sc; - if (sc == NULL) - return (ENXIO); - - /* Gating AHB clock for DMA controller */ - reg_value = ccm_read_4(sc, CCM_AHB_GATING0); - reg_value |= CCM_AHB_GATING_DMA; - ccm_write_4(sc, CCM_AHB_GATING0, reg_value); - - return (0); -} - -int -a10_clk_codec_activate(unsigned int freq) -{ - struct a10_ccm_softc *sc; - uint32_t reg_value; - - sc = a10_ccm_sc; - if (sc == NULL) - return (ENXIO); - - a10_clk_pll2_set_rate(freq); - - /* Gating APB clock for ADDA */ - reg_value = ccm_read_4(sc, CCM_APB0_GATING); - reg_value |= CCM_APB0_GATING_ADDA; - ccm_write_4(sc, CCM_APB0_GATING, reg_value); - - /* Enable audio codec clock */ - reg_value = ccm_read_4(sc, CCM_AUDIO_CODEC_CLK); - reg_value |= CCM_AUDIO_CODEC_ENABLE; - ccm_write_4(sc, CCM_AUDIO_CODEC_CLK, reg_value); - - return (0); -} - -static void -calc_tcon_pll(int f_ref, int f_out, int *pm, int *pn) -{ - int best, m, n, f_cur, diff; - - best = TCON_PLL_WORST; - for (n = TCON_PLL_N_MIN; n <= TCON_PLL_N_MAX; n++) { - for (m = TCON_PLL_M_MIN; m <= TCON_PLL_M_MAX; m++) { - f_cur = (m * f_ref) / n; - diff = f_out - f_cur; - if (diff > 0 && diff < best) { - best = diff; - *pm = m; - *pn = n; - } - } - } -} - -int -a10_clk_debe_activate(void) -{ - struct a10_ccm_softc *sc; - int pll_rate, clk_div; - uint32_t reg_value; - - sc = a10_ccm_sc; - if (sc == NULL) - return (ENXIO); - - /* Leave reset */ - reg_value = ccm_read_4(sc, CCM_BE0_SCLK); - reg_value |= CCM_BE_CLK_RESET; - ccm_write_4(sc, CCM_BE0_SCLK, reg_value); - - pll_rate = a10_clk_pll5x_get_rate(); - - clk_div = howmany(pll_rate, DEBE_DEFAULT_RATE); - - /* Set BE0 source to PLL5 (DDR external peripheral clock) */ - reg_value = CCM_BE_CLK_RESET; - reg_value |= (CCM_BE_CLK_SRC_SEL_PLL5 << CCM_BE_CLK_SRC_SEL_SHIFT); - reg_value |= (clk_div - 1); - ccm_write_4(sc, CCM_BE0_SCLK, reg_value); - - /* Gating AHB clock for BE0 */ - reg_value = ccm_read_4(sc, CCM_AHB_GATING1); - reg_value |= CCM_AHB_GATING_DE_BE0; - ccm_write_4(sc, CCM_AHB_GATING1, reg_value); - - /* Enable DRAM clock to BE0 */ - reg_value = ccm_read_4(sc, CCM_DRAM_CLK); - reg_value |= CCM_DRAM_CLK_BE0_CLK_ENABLE; - ccm_write_4(sc, CCM_DRAM_CLK, reg_value); - - /* Enable BE0 clock */ - reg_value = ccm_read_4(sc, CCM_BE0_SCLK); - reg_value |= CCM_BE_CLK_SCLK_GATING; - ccm_write_4(sc, CCM_BE0_SCLK, reg_value); - - return (0); -} - -int -a10_clk_lcd_activate(void) -{ - struct a10_ccm_softc *sc; - uint32_t reg_value; - - sc = a10_ccm_sc; - if (sc == NULL) - return (ENXIO); - - /* Clear LCD0 reset */ - reg_value = ccm_read_4(sc, CCM_LCD0_CH0_CLK); - reg_value |= CCM_LCD_CH0_RESET; - ccm_write_4(sc, CCM_LCD0_CH0_CLK, reg_value); - - /* Gating AHB clock for LCD0 */ - reg_value = ccm_read_4(sc, CCM_AHB_GATING1); - reg_value |= CCM_AHB_GATING_LCD0; - ccm_write_4(sc, CCM_AHB_GATING1, reg_value); - - return (0); -} - -int -a10_clk_tcon_activate(unsigned int freq) -{ - struct a10_ccm_softc *sc; - int m, n, m2, n2, f_single, f_double, dbl, src_sel; - - sc = a10_ccm_sc; - if (sc == NULL) - return (ENXIO); - - m = n = m2 = n2 = 0; - dbl = 0; - - calc_tcon_pll(TCON_PLLREF_SINGLE, TCON_RATE_KHZ(freq), &m, &n); - calc_tcon_pll(TCON_PLLREF_DOUBLE, TCON_RATE_KHZ(freq), &m2, &n2); - - f_single = n ? (m * TCON_PLLREF_SINGLE) / n : 0; - f_double = n2 ? (m2 * TCON_PLLREF_DOUBLE) / n2 : 0; - - if (f_double > f_single) { - dbl = 1; - m = m2; - n = n2; - } - src_sel = dbl ? CCM_LCD_CH1_SRC_SEL_PLL3_2X : CCM_LCD_CH1_SRC_SEL_PLL3; - - if (n == 0 || m == 0) - return (EINVAL); - - /* Set PLL3 to the closest possible rate */ - a10_clk_pll3_set_rate(TCON_RATE_HZ(m * TCON_PLLREF_SINGLE)); - - /* Enable LCD0 CH1 clock */ - ccm_write_4(sc, CCM_LCD0_CH1_CLK, - CCM_LCD_CH1_SCLK2_GATING | CCM_LCD_CH1_SCLK1_GATING | - (src_sel << CCM_LCD_CH1_SRC_SEL_SHIFT) | (n - 1)); - - return (0); -} - -int -a10_clk_tcon_get_config(int *pdiv, int *pdbl) -{ - struct a10_ccm_softc *sc; - uint32_t reg_value; - int src; - - sc = a10_ccm_sc; - if (sc == NULL) - return (ENXIO); - - reg_value = ccm_read_4(sc, CCM_LCD0_CH1_CLK); - - *pdiv = (reg_value & CCM_LCD_CH1_CLK_DIV_RATIO_M) + 1; - - src = (reg_value & CCM_LCD_CH1_SRC_SEL) >> CCM_LCD_CH1_SRC_SEL_SHIFT; - switch (src) { - case CCM_LCD_CH1_SRC_SEL_PLL3: - case CCM_LCD_CH1_SRC_SEL_PLL7: - *pdbl = 0; - break; - case CCM_LCD_CH1_SRC_SEL_PLL3_2X: - case CCM_LCD_CH1_SRC_SEL_PLL7_2X: - *pdbl = 1; - break; - } - - return (0); -} - -int -a10_clk_hdmi_activate(void) -{ - struct a10_ccm_softc *sc; - uint32_t reg_value; - int error; - - sc = a10_ccm_sc; - if (sc == NULL) - return (ENXIO); - - /* Set PLL3 to 297MHz */ - error = a10_clk_pll3_set_rate(HDMI_DEFAULT_RATE); - if (error != 0) - return (error); - - /* Enable HDMI clock, source PLL3 */ - reg_value = ccm_read_4(sc, CCM_HDMI_CLK); - reg_value |= CCM_HDMI_CLK_SCLK_GATING; - reg_value &= ~CCM_HDMI_CLK_SRC_SEL; - reg_value |= (CCM_HDMI_CLK_SRC_SEL_PLL3 << CCM_HDMI_CLK_SRC_SEL_SHIFT); - ccm_write_4(sc, CCM_HDMI_CLK, reg_value); - - /* Gating AHB clock for HDMI */ - reg_value = ccm_read_4(sc, CCM_AHB_GATING1); - reg_value |= CCM_AHB_GATING_HDMI; - ccm_write_4(sc, CCM_AHB_GATING1, reg_value); - - return (0); -} Property changes on: head/sys/arm/allwinner/a10_clk.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/arm/allwinner/a10_clk.h =================================================================== --- head/sys/arm/allwinner/a10_clk.h (revision 297626) +++ head/sys/arm/allwinner/a10_clk.h (nonexistent) @@ -1,247 +0,0 @@ -/*- - * Copyright (c) 2013 Ganbold Tsagaankhuu - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#ifndef _A10_CLK_H_ -#define _A10_CLK_H_ - -#define CCM_PLL1_CFG 0x0000 -#define CCM_PLL1_TUN 0x0004 -#define CCM_PLL2_CFG 0x0008 -#define CCM_PLL2_TUN 0x000c -#define CCM_PLL3_CFG 0x0010 -#define CCM_PLL3_TUN 0x0014 -#define CCM_PLL4_CFG 0x0018 -#define CCM_PLL4_TUN 0x001c -#define CCM_PLL5_CFG 0x0020 -#define CCM_PLL5_TUN 0x0024 -#define CCM_PLL6_CFG 0x0028 -#define CCM_PLL6_TUN 0x002c -#define CCM_PLL7_CFG 0x0030 -#define CCM_PLL7_TUN 0x0034 -#define CCM_PLL1_TUN2 0x0038 -#define CCM_PLL5_TUN2 0x003c -#define CCM_PLL_LOCK_DBG 0x004c -#define CCM_OSC24M_CFG 0x0050 -#define CCM_CPU_AHB_APB0_CFG 0x0054 -#define CCM_APB1_CLK_DIV 0x0058 -#define CCM_AXI_GATING 0x005c -#define CCM_AHB_GATING0 0x0060 -#define CCM_AHB_GATING1 0x0064 -#define CCM_APB0_GATING 0x0068 -#define CCM_APB1_GATING 0x006c -#define CCM_NAND_SCLK_CFG 0x0080 -#define CCM_MS_SCLK_CFG 0x0084 -#define CCM_MMC0_SCLK_CFG 0x0088 -#define CCM_MMC1_SCLK_CFG 0x008c -#define CCM_MMC2_SCLK_CFG 0x0090 -#define CCM_MMC3_SCLK_CFG 0x0094 -#define CCM_TS_CLK 0x0098 -#define CCM_SS_CLK 0x009c -#define CCM_SPI0_CLK 0x00a0 -#define CCM_SPI1_CLK 0x00a4 -#define CCM_SPI2_CLK 0x00a8 -#define CCM_PATA_CLK 0x00ac -#define CCM_IR0_CLK 0x00b0 -#define CCM_IR1_CLK 0x00b4 -#define CCM_IIS_CLK 0x00b8 -#define CCM_AC97_CLK 0x00bc -#define CCM_SPDIF_CLK 0x00c0 -#define CCM_KEYPAD_CLK 0x00c4 -#define CCM_SATA_CLK 0x00c8 -#define CCM_USB_CLK 0x00cc -#define CCM_GPS_CLK 0x00d0 -#define CCM_SPI3_CLK 0x00d4 -#define CCM_DRAM_CLK 0x0100 -#define CCM_BE0_SCLK 0x0104 -#define CCM_BE1_SCLK 0x0108 -#define CCM_FE0_CLK 0x010c -#define CCM_FE1_CLK 0x0110 -#define CCM_MP_CLK 0x0114 -#define CCM_LCD0_CH0_CLK 0x0118 -#define CCM_LCD1_CH0_CLK 0x011c -#define CCM_CSI_ISP_CLK 0x0120 -#define CCM_TVD_CLK 0x0128 -#define CCM_LCD0_CH1_CLK 0x012c -#define CCM_LCD1_CH1_CLK 0x0130 -#define CCM_CS0_CLK 0x0134 -#define CCM_CS1_CLK 0x0138 -#define CCM_VE_CLK 0x013c -#define CCM_AUDIO_CODEC_CLK 0x0140 -#define CCM_AVS_CLK 0x0144 -#define CCM_ACE_CLK 0x0148 -#define CCM_LVDS_CLK 0x014c -#define CCM_HDMI_CLK 0x0150 -#define CCM_MALI400_CLK 0x0154 -#define CCM_GMAC_CLK 0x0164 - -#define CCM_GMAC_CLK_DELAY_SHIFT 10 -#define CCM_GMAC_CLK_MODE_MASK 0x7 -#define CCM_GMAC_MODE_RGMII (1 << 2) -#define CCM_GMAC_CLK_MII 0x0 -#define CCM_GMAC_CLK_EXT_RGMII 0x1 -#define CCM_GMAC_CLK_RGMII 0x2 - -/* APB0_GATING */ -#define CCM_APB0_GATING_ADDA (1 << 0) - -/* AHB_GATING_REG0 */ -#define CCM_AHB_GATING_USB0 (1 << 0) -#define CCM_AHB_GATING_EHCI0 (1 << 1) -#define CCM_AHB_GATING_OHCI0 (1 << 2) -#define CCM_AHB_GATING_EHCI1 (1 << 3) -#define CCM_AHB_GATING_OHCI1 (1 << 4) -#define CCM_AHB_GATING_DMA (1 << 6) -#define CCM_AHB_GATING_SDMMC0 (1 << 8) -#define CCM_AHB_GATING_EMAC (1 << 17) -#define CCM_AHB_GATING_SATA (1 << 25) - -/* AHB_GATING_REG1 */ -#define CCM_AHB_GATING_GMAC (1 << 17) -#define CCM_AHB_GATING_DE_BE1 (1 << 13) -#define CCM_AHB_GATING_DE_BE0 (1 << 12) -#define CCM_AHB_GATING_HDMI (1 << 11) -#define CCM_AHB_GATING_LCD1 (1 << 5) -#define CCM_AHB_GATING_LCD0 (1 << 4) - -/* APB1_GATING_REG */ -#define CCM_APB1_GATING_TWI (1 << 0) - -/* USB */ -#define CCM_USB_PHY (1 << 8) -#define CCM_SCLK_GATING_OHCI1 (1 << 7) -#define CCM_SCLK_GATING_OHCI0 (1 << 6) -#define CCM_USBPHY2_RESET (1 << 2) -#define CCM_USBPHY1_RESET (1 << 1) -#define CCM_USBPHY0_RESET (1 << 0) - -#define CCM_PLL_CFG_ENABLE (1U << 31) -#define CCM_PLL_CFG_BYPASS (1U << 30) -#define CCM_PLL_CFG_PLL5 (1U << 25) -#define CCM_PLL_CFG_PLL6 (1U << 24) -#define CCM_PLL_CFG_FACTOR_N 0x1f00 -#define CCM_PLL_CFG_FACTOR_N_SHIFT 8 -#define CCM_PLL_CFG_FACTOR_K 0x30 -#define CCM_PLL_CFG_FACTOR_K_SHIFT 4 -#define CCM_PLL_CFG_FACTOR_M 0x3 - -#define CCM_PLL2_CFG_POSTDIV 0x3c000000 -#define CCM_PLL2_CFG_POSTDIV_SHIFT 26 -#define CCM_PLL2_CFG_PREDIV 0x1f -#define CCM_PLL2_CFG_PREDIV_SHIFT 0 - -#define CCM_PLL3_CFG_MODE_SEL_SHIFT 15 -#define CCM_PLL3_CFG_MODE_SEL_FRACT (0 << CCM_PLL3_CFG_MODE_SEL_SHIFT) -#define CCM_PLL3_CFG_MODE_SEL_INT (1 << CCM_PLL3_CFG_MODE_SEL_SHIFT) -#define CCM_PLL3_CFG_FUNC_SET_SHIFT 14 -#define CCM_PLL3_CFG_FUNC_SET_270MHZ (0 << CCM_PLL3_CFG_FUNC_SET_SHIFT) -#define CCM_PLL3_CFG_FUNC_SET_297MHZ (1 << CCM_PLL3_CFG_FUNC_SET_SHIFT) -#define CCM_PLL3_CFG_FACTOR_M 0x7f - -#define CCM_PLL5_CFG_OUT_EXT_DIV_P 0x30000 -#define CCM_PLL5_CFG_OUT_EXT_DIV_P_SHIFT 16 - -#define CCM_PLL6_CFG_SATA_CLKEN (1U << 14) - -#define CCM_SD_CLK_SRC_SEL 0x3000000 -#define CCM_SD_CLK_SRC_SEL_SHIFT 24 -#define CCM_SD_CLK_SRC_SEL_OSC24M 0 -#define CCM_SD_CLK_SRC_SEL_PLL6 1 -#define CCM_SD_CLK_PHASE_CTR 0x700000 -#define CCM_SD_CLK_PHASE_CTR_SHIFT 20 -#define CCM_SD_CLK_DIV_RATIO_N 0x30000 -#define CCM_SD_CLK_DIV_RATIO_N_SHIFT 16 -#define CCM_SD_CLK_OPHASE_CTR 0x700 -#define CCM_SD_CLK_OPHASE_CTR_SHIFT 8 -#define CCM_SD_CLK_DIV_RATIO_M 0xf - -#define CCM_AUDIO_CODEC_ENABLE (1U << 31) - -#define CCM_LCD_CH0_SCLK_GATING (1U << 31) -#define CCM_LCD_CH0_RESET (1U << 30) -#define CCM_LCD_CH0_SRC_SEL 0x03000000 -#define CCM_LCD_CH0_SRC_SEL_SHIFT 24 -#define CCM_LCD_CH0_SRC_SEL_PLL3 0 -#define CCM_LCD_CH0_SRC_SEL_PLL7 1 -#define CCM_LCD_CH0_SRC_SEL_PLL3_2X 2 -#define CCM_LCD_CH0_SRC_SEL_PLL6_2X 3 - -#define CCM_LCD_CH1_SCLK2_GATING (1U << 31) -#define CCM_LCD_CH1_SRC_SEL 0x03000000 -#define CCM_LCD_CH1_SRC_SEL_SHIFT 24 -#define CCM_LCD_CH1_SRC_SEL_PLL3 0 -#define CCM_LCD_CH1_SRC_SEL_PLL7 1 -#define CCM_LCD_CH1_SRC_SEL_PLL3_2X 2 -#define CCM_LCD_CH1_SRC_SEL_PLL7_2X 3 -#define CCM_LCD_CH1_SCLK1_GATING (1U << 15) -#define CCM_LCD_CH1_SCLK1_SRC_SEL_SHIFT 11 -#define CCM_LCD_CH1_SCLK1_SRC_SEL_SCLK2 0 -#define CCM_LCD_CH1_SCLK1_SRC_SEL_SCLK2_DIV2 1 -#define CCM_LCD_CH1_CLK_DIV_RATIO_M 0xf - -#define CCM_DRAM_CLK_BE1_CLK_ENABLE (1U << 27) -#define CCM_DRAM_CLK_BE0_CLK_ENABLE (1U << 26) - -#define CCM_BE_CLK_SCLK_GATING (1U << 31) -#define CCM_BE_CLK_RESET (1U << 30) -#define CCM_BE_CLK_SRC_SEL 0x03000000 -#define CCM_BE_CLK_SRC_SEL_SHIFT 24 -#define CCM_BE_CLK_SRC_SEL_PLL3 0 -#define CCM_BE_CLK_SRC_SEL_PLL7 1 -#define CCM_BE_CLK_SRC_SEL_PLL5 2 -#define CCM_BE_CLK_DIV_RATIO_M 0xf - -#define CCM_HDMI_CLK_SCLK_GATING (1U << 31) -#define CCM_HDMI_CLK_SRC_SEL 0x03000000 -#define CCM_HDMI_CLK_SRC_SEL_SHIFT 24 -#define CCM_HDMI_CLK_SRC_SEL_PLL3 0 -#define CCM_HDMI_CLK_SRC_SEL_PLL7 1 -#define CCM_HDMI_CLK_SRC_SEL_PLL3_2X 2 -#define CCM_HDMI_CLK_SRC_SEL_PLL7_2X 3 -#define CCM_HDMI_CLK_DIV_RATIO_M 0xf - -#define CCM_CLK_REF_FREQ 24000000U - -int a10_clk_ehci_activate(void); -int a10_clk_ehci_deactivate(void); -int a10_clk_ohci_activate(void); -int a10_clk_ohci_deactivate(void); -int a10_clk_emac_activate(void); -int a10_clk_gmac_activate(phandle_t); -int a10_clk_ahci_activate(void); -int a10_clk_mmc_activate(int); -int a10_clk_mmc_cfg(int, int); -int a10_clk_i2c_activate(int); -int a10_clk_dmac_activate(void); -int a10_clk_codec_activate(unsigned int); -int a10_clk_debe_activate(void); -int a10_clk_lcd_activate(void); -int a10_clk_tcon_activate(unsigned int); -int a10_clk_tcon_get_config(int *, int *); -int a10_clk_hdmi_activate(void); - -#endif /* _A10_CLK_H_ */ Property changes on: head/sys/arm/allwinner/a10_clk.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/arm/allwinner/a10_ahci.c =================================================================== --- head/sys/arm/allwinner/a10_ahci.c (revision 297626) +++ head/sys/arm/allwinner/a10_ahci.c (revision 297627) @@ -1,363 +1,397 @@ /*- * Copyright (c) 2014-2015 M. Warner Losh * Copyright (c) 2015 Luiz Otavio O Souza * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * The magic-bit-bang sequence used in this code may be based on a linux * platform driver in the Allwinner SDK from Allwinner Technology Co., Ltd. * www.allwinnertech.com, by Daniel Wang * though none of the original code was copied. */ #include "opt_bus.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include -#include +#include /* * Allwinner a1x/a2x/a8x SATA attachment. This is just the AHCI register * set with a few extra implementation-specific registers that need to * be accounted for. There's only one PHY in the system, and it needs * to be trained to bring the link up. In addition, there's some DMA * specific things that need to be done as well. These things are also * just about completely undocumented, except in ugly code in the Linux * SDK Allwinner releases. */ /* BITx -- Unknown bit that needs to be set/cleared at position x */ /* UFx -- Uknown multi-bit field frobbed during init */ #define AHCI_BISTAFR 0x00A0 #define AHCI_BISTCR 0x00A4 #define AHCI_BISTFCTR 0x00A8 #define AHCI_BISTSR 0x00AC #define AHCI_BISTDECR 0x00B0 #define AHCI_DIAGNR 0x00B4 #define AHCI_DIAGNR1 0x00B8 #define AHCI_OOBR 0x00BC #define AHCI_PHYCS0R 0x00C0 /* Bits 0..17 are a mystery */ #define PHYCS0R_BIT18 (1 << 18) #define PHYCS0R_POWER_ENABLE (1 << 19) #define PHYCS0R_UF1_MASK (7 << 20) /* Unknown Field 1 */ #define PHYCS0R_UF1_INIT (3 << 20) #define PHYCS0R_BIT23 (1 << 23) #define PHYCS0R_UF2_MASK (7 << 24) /* Uknown Field 2 */ #define PHYCS0R_UF2_INIT (5 << 24) /* Bit 27 mystery */ #define PHYCS0R_POWER_STATUS_MASK (7 << 28) #define PHYCS0R_PS_GOOD (2 << 28) /* Bit 31 mystery */ #define AHCI_PHYCS1R 0x00C4 /* Bits 0..5 are a mystery */ #define PHYCS1R_UF1_MASK (3 << 6) #define PHYCS1R_UF1_INIT (2 << 6) #define PHYCS1R_UF2_MASK (0x1f << 8) #define PHYCS1R_UF2_INIT (6 << 8) /* Bits 13..14 are a mystery */ #define PHYCS1R_BIT15 (1 << 15) #define PHYCS1R_UF3_MASK (3 << 16) #define PHYCS1R_UF3_INIT (2 << 16) /* Bit 18 mystery */ #define PHYCS1R_HIGHZ (1 << 19) /* Bits 20..27 mystery */ #define PHYCS1R_BIT28 (1 << 28) /* Bits 29..31 mystery */ #define AHCI_PHYCS2R 0x00C8 /* bits 0..4 mystery */ #define PHYCS2R_UF1_MASK (0x1f << 5) #define PHYCS2R_UF1_INIT (0x19 << 5) /* Bits 10..23 mystery */ #define PHYCS2R_CALIBRATE (1 << 24) /* Bits 25..31 mystery */ #define AHCI_TIMER1MS 0x00E0 #define AHCI_GPARAM1R 0x00E8 #define AHCI_GPARAM2R 0x00EC #define AHCI_PPARAMR 0x00F0 #define AHCI_TESTR 0x00F4 #define AHCI_VERSIONR 0x00F8 #define AHCI_IDR 0x00FC #define AHCI_RWCR 0x00FC #define AHCI_P0DMACR 0x0070 #define AHCI_P0PHYCR 0x0078 #define AHCI_P0PHYSR 0x007C +#define PLL_FREQ 100000000 + static void inline ahci_set(struct resource *m, bus_size_t off, uint32_t set) { uint32_t val = ATA_INL(m, off); val |= set; ATA_OUTL(m, off, val); } static void inline ahci_clr(struct resource *m, bus_size_t off, uint32_t clr) { uint32_t val = ATA_INL(m, off); val &= ~clr; ATA_OUTL(m, off, val); } static void inline ahci_mask_set(struct resource *m, bus_size_t off, uint32_t mask, uint32_t set) { uint32_t val = ATA_INL(m, off); val &= mask; val |= set; ATA_OUTL(m, off, val); } /* * Should this be phy_reset or phy_init */ #define PHY_RESET_TIMEOUT 1000 static void ahci_a10_phy_reset(device_t dev) { uint32_t to, val; struct ahci_controller *ctlr = device_get_softc(dev); /* * Here start the the magic -- most of the comments are based * on guesswork, names of routines and printf error * messages. The code works, but it will do that even if the * comments are 100% BS. */ /* * Lock out other access while we initialize. Or at least that * seems to be the case based on Linux SDK #defines. Maybe this * put things into reset? */ ATA_OUTL(ctlr->r_mem, AHCI_RWCR, 0); DELAY(100); /* * Set bit 19 in PHYCS1R. Guessing this disables driving the PHY * port for a bit while we reset things. */ ahci_set(ctlr->r_mem, AHCI_PHYCS1R, PHYCS1R_HIGHZ); /* * Frob PHYCS0R... */ ahci_mask_set(ctlr->r_mem, AHCI_PHYCS0R, ~PHYCS0R_UF2_MASK, PHYCS0R_UF2_INIT | PHYCS0R_BIT23 | PHYCS0R_BIT18); /* * Set three fields in PHYCS1R */ ahci_mask_set(ctlr->r_mem, AHCI_PHYCS1R, ~(PHYCS1R_UF1_MASK | PHYCS1R_UF2_MASK | PHYCS1R_UF3_MASK), PHYCS1R_UF1_INIT | PHYCS1R_UF2_INIT | PHYCS1R_UF3_INIT); /* * Two more mystery bits in PHYCS1R. -- can these be combined above? */ ahci_set(ctlr->r_mem, AHCI_PHYCS1R, PHYCS1R_BIT15 | PHYCS1R_BIT28); /* * Now clear that first mysery bit. Perhaps this starts * driving the PHY again so we can power it up and start * talking to the SATA drive, if any below. */ ahci_clr(ctlr->r_mem, AHCI_PHYCS1R, PHYCS1R_HIGHZ); /* * Frob PHYCS0R again... */ ahci_mask_set(ctlr->r_mem, AHCI_PHYCS0R, ~PHYCS0R_UF1_MASK, PHYCS0R_UF1_INIT); /* * Frob PHYCS2R, because 25 means something? */ ahci_mask_set(ctlr->r_mem, AHCI_PHYCS2R, ~PHYCS2R_UF1_MASK, PHYCS2R_UF1_INIT); DELAY(100); /* WAG */ /* * Turn on the power to the PHY and wait for it to report back * good? */ ahci_set(ctlr->r_mem, AHCI_PHYCS0R, PHYCS0R_POWER_ENABLE); for (to = PHY_RESET_TIMEOUT; to > 0; to--) { val = ATA_INL(ctlr->r_mem, AHCI_PHYCS0R); if ((val & PHYCS0R_POWER_STATUS_MASK) == PHYCS0R_PS_GOOD) break; DELAY(10); } if (to == 0 && bootverbose) device_printf(dev, "PHY Power Failed PHYCS0R = %#x\n", val); /* * Calibrate the clocks between the device and the host. This appears * to be an automated process that clears the bit when it is done. */ ahci_set(ctlr->r_mem, AHCI_PHYCS2R, PHYCS2R_CALIBRATE); for (to = PHY_RESET_TIMEOUT; to > 0; to--) { val = ATA_INL(ctlr->r_mem, AHCI_PHYCS2R); if ((val & PHYCS2R_CALIBRATE) == 0) break; DELAY(10); } if (to == 0 && bootverbose) device_printf(dev, "PHY Cal Failed PHYCS2R %#x\n", val); /* * OK, let things settle down a bit. */ DELAY(1000); /* * Go back into normal mode now that we've calibrated the PHY. */ ATA_OUTL(ctlr->r_mem, AHCI_RWCR, 7); } static void ahci_a10_ch_start(struct ahci_channel *ch) { uint32_t reg; /* * Magical values from Allwinner SDK, setup the DMA before start * operations on this channel. */ reg = ATA_INL(ch->r_mem, AHCI_P0DMACR); reg &= ~0xff00; reg |= 0x4400; ATA_OUTL(ch->r_mem, AHCI_P0DMACR, reg); } static int ahci_a10_ctlr_reset(device_t dev) { ahci_a10_phy_reset(dev); return (ahci_ctlr_reset(dev)); } static int ahci_a10_probe(device_t dev) { if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-ahci")) return (ENXIO); device_set_desc(dev, "Allwinner Integrated AHCI controller"); return (BUS_PROBE_DEFAULT); } static int ahci_a10_attach(device_t dev) { int error; struct ahci_controller *ctlr; + clk_t clk_pll, clk_gate; ctlr = device_get_softc(dev); + clk_pll = clk_gate = NULL; + ctlr->quirks = AHCI_Q_NOPMP; ctlr->vendorid = 0; ctlr->deviceid = 0; ctlr->subvendorid = 0; ctlr->subdeviceid = 0; ctlr->r_rid = 0; if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &ctlr->r_rid, RF_ACTIVE))) return (ENXIO); - /* Turn on the PLL for SATA */ - a10_clk_ahci_activate(); - + /* Enable clocks */ + error = clk_get_by_ofw_index(dev, 0, &clk_pll); + if (error != 0) { + device_printf(dev, "Cannot get PLL clock\n"); + goto fail; + } + error = clk_get_by_ofw_index(dev, 1, &clk_gate); + if (error != 0) { + device_printf(dev, "Cannot get gate clock\n"); + goto fail; + } + error = clk_set_freq(clk_pll, PLL_FREQ, CLK_SET_ROUND_DOWN); + if (error != 0) { + device_printf(dev, "Cannot set PLL frequency\n"); + goto fail; + } + error = clk_enable(clk_pll); + if (error != 0) { + device_printf(dev, "Cannot enable PLL\n"); + goto fail; + } + error = clk_enable(clk_gate); + if (error != 0) { + device_printf(dev, "Cannot enable clk gate\n"); + goto fail; + } + /* Reset controller */ - if ((error = ahci_a10_ctlr_reset(dev)) != 0) { - bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, - ctlr->r_mem); - return (error); - }; + if ((error = ahci_a10_ctlr_reset(dev)) != 0) + goto fail; /* * No MSI registers on this platform. */ ctlr->msi = 0; ctlr->numirqs = 1; /* Channel start callback(). */ ctlr->ch_start = ahci_a10_ch_start; /* * Note: ahci_attach will release ctlr->r_mem on errors automatically */ return (ahci_attach(dev)); + +fail: + if (clk_gate != NULL) + clk_release(clk_gate); + if (clk_pll != NULL) + clk_release(clk_pll); + bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); + return (error); } static int ahci_a10_detach(device_t dev) { return (ahci_detach(dev)); } devclass_t ahci_devclass; static device_method_t ahci_ata_methods[] = { DEVMETHOD(device_probe, ahci_a10_probe), DEVMETHOD(device_attach, ahci_a10_attach), DEVMETHOD(device_detach, ahci_a10_detach), DEVMETHOD(bus_print_child, ahci_print_child), DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), DEVMETHOD(bus_release_resource, ahci_release_resource), DEVMETHOD(bus_setup_intr, ahci_setup_intr), DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), DEVMETHOD(bus_child_location_str, ahci_child_location_str), DEVMETHOD_END }; static driver_t ahci_ata_driver = { "ahci", ahci_ata_methods, sizeof(struct ahci_controller) }; DRIVER_MODULE(ahci, simplebus, ahci_ata_driver, ahci_devclass, 0, 0); Index: head/sys/arm/allwinner/a10_codec.c =================================================================== --- head/sys/arm/allwinner/a10_codec.c (revision 297626) +++ head/sys/arm/allwinner/a10_codec.c (revision 297627) @@ -1,850 +1,879 @@ /*- * Copyright (c) 2014-2016 Jared D. McNeill * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* * Allwinner A10/A20 Audio Codec */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include -#include +#include #include "sunxi_dma_if.h" #include "mixer_if.h" #include "gpio_if.h" #define TX_TRIG_LEVEL 0xf #define RX_TRIG_LEVEL 0x7 #define DRQ_CLR_CNT 0x3 #define AC_DAC_DPC 0x00 #define DAC_DPC_EN_DA 0x80000000 #define AC_DAC_FIFOC 0x04 #define DAC_FIFOC_FS_SHIFT 29 #define DAC_FIFOC_FS_MASK (7U << DAC_FIFOC_FS_SHIFT) #define DAC_FS_48KHZ 0 #define DAC_FS_32KHZ 1 #define DAC_FS_24KHZ 2 #define DAC_FS_16KHZ 3 #define DAC_FS_12KHZ 4 #define DAC_FS_8KHZ 5 #define DAC_FS_192KHZ 6 #define DAC_FS_96KHZ 7 #define DAC_FIFOC_FIFO_MODE_SHIFT 24 #define DAC_FIFOC_FIFO_MODE_MASK (3U << DAC_FIFOC_FIFO_MODE_SHIFT) #define FIFO_MODE_24_31_8 0 #define FIFO_MODE_16_31_16 0 #define FIFO_MODE_16_15_0 1 #define DAC_FIFOC_DRQ_CLR_CNT_SHIFT 21 #define DAC_FIFOC_DRQ_CLR_CNT_MASK (3U << DAC_FIFOC_DRQ_CLR_CNT_SHIFT) #define DAC_FIFOC_TX_TRIG_LEVEL_SHIFT 8 #define DAC_FIFOC_TX_TRIG_LEVEL_MASK (0x7f << DAC_FIFOC_TX_TRIG_LEVEL_SHIFT) #define DAC_FIFOC_MONO_EN (1U << 6) #define DAC_FIFOC_TX_BITS (1U << 5) #define DAC_FIFOC_DRQ_EN (1U << 4) #define DAC_FIFOC_FIFO_FLUSH (1U << 0) #define AC_DAC_FIFOS 0x08 #define AC_DAC_TXDATA 0x0c #define AC_DAC_ACTL 0x10 #define DAC_ACTL_DACAREN (1U << 31) #define DAC_ACTL_DACALEN (1U << 30) #define DAC_ACTL_MIXEN (1U << 29) #define DAC_ACTL_DACPAS (1U << 8) #define DAC_ACTL_PAMUTE (1U << 6) #define DAC_ACTL_PAVOL_SHIFT 0 #define DAC_ACTL_PAVOL_MASK (0x3f << DAC_ACTL_PAVOL_SHIFT) #define AC_ADC_FIFOC 0x1c #define ADC_FIFOC_FS_SHIFT 29 #define ADC_FIFOC_FS_MASK (7U << ADC_FIFOC_FS_SHIFT) #define ADC_FS_48KHZ 0 #define ADC_FIFOC_EN_AD (1U << 28) #define ADC_FIFOC_RX_FIFO_MODE (1U << 24) #define ADC_FIFOC_RX_TRIG_LEVEL_SHIFT 8 #define ADC_FIFOC_RX_TRIG_LEVEL_MASK (0x1f << ADC_FIFOC_RX_TRIG_LEVEL_SHIFT) #define ADC_FIFOC_MONO_EN (1U << 7) #define ADC_FIFOC_RX_BITS (1U << 6) #define ADC_FIFOC_DRQ_EN (1U << 4) #define ADC_FIFOC_FIFO_FLUSH (1U << 1) #define AC_ADC_FIFOS 0x20 #define AC_ADC_RXDATA 0x24 #define AC_ADC_ACTL 0x28 #define ADC_ACTL_ADCREN (1U << 31) #define ADC_ACTL_ADCLEN (1U << 30) #define ADC_ACTL_PREG1EN (1U << 29) #define ADC_ACTL_PREG2EN (1U << 28) #define ADC_ACTL_VMICEN (1U << 27) #define ADC_ACTL_ADCG_SHIFT 20 #define ADC_ACTL_ADCG_MASK (7U << ADC_ACTL_ADCG_SHIFT) #define ADC_ACTL_ADCIS_SHIFT 17 #define ADC_ACTL_ADCIS_MASK (7U << ADC_ACTL_ADCIS_SHIFT) #define ADC_IS_LINEIN 0 #define ADC_IS_FMIN 1 #define ADC_IS_MIC1 2 #define ADC_IS_MIC2 3 #define ADC_IS_MIC1_L_MIC2_R 4 #define ADC_IS_MIC1_LR_MIC2_LR 5 #define ADC_IS_OMIX 6 #define ADC_IS_LINEIN_L_MIC1_R 7 #define ADC_ACTL_LNRDF (1U << 16) #define ADC_ACTL_LNPREG_SHIFT 13 #define ADC_ACTL_LNPREG_MASK (7U << ADC_ACTL_LNPREG_SHIFT) #define ADC_ACTL_PA_EN (1U << 4) #define ADC_ACTL_DDE (1U << 3) #define AC_DAC_CNT 0x30 #define AC_ADC_CNT 0x34 static uint32_t a10codec_fmt[] = { SND_FORMAT(AFMT_S16_LE, 1, 0), SND_FORMAT(AFMT_S16_LE, 2, 0), 0 }; static struct pcmchan_caps a10codec_pcaps = { 8000, 192000, a10codec_fmt, 0 }; static struct pcmchan_caps a10codec_rcaps = { 8000, 48000, a10codec_fmt, 0 }; struct a10codec_info; struct a10codec_chinfo { struct snd_dbuf *buffer; struct pcm_channel *channel; struct a10codec_info *parent; bus_dmamap_t dmamap; void *dmaaddr; bus_addr_t physaddr; bus_size_t fifo; device_t dmac; void *dmachan; int dir; int run; uint32_t pos; uint32_t format; uint32_t blocksize; uint32_t speed; }; struct a10codec_info { device_t dev; struct resource *res[2]; struct mtx *lock; bus_dma_tag_t dmat; unsigned dmasize; void *ih; unsigned drqtype_codec; unsigned drqtype_sdram; struct a10codec_chinfo play; struct a10codec_chinfo rec; }; static struct resource_spec a10codec_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE }, { -1, 0 } }; #define CODEC_READ(sc, reg) bus_read_4((sc)->res[0], (reg)) #define CODEC_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) /* * Mixer interface */ static int a10codec_mixer_init(struct snd_mixer *m) { struct a10codec_info *sc = mix_getdevinfo(m); pcell_t prop[4]; phandle_t node; device_t gpio; uint32_t val; ssize_t len; int pin; mix_setdevs(m, SOUND_MASK_VOLUME | SOUND_MASK_LINE | SOUND_MASK_RECLEV); mix_setrecdevs(m, SOUND_MASK_LINE | SOUND_MASK_LINE1 | SOUND_MASK_MIC); /* Unmute input source to PA */ val = CODEC_READ(sc, AC_DAC_ACTL); val |= DAC_ACTL_PAMUTE; CODEC_WRITE(sc, AC_DAC_ACTL, val); /* Enable PA */ val = CODEC_READ(sc, AC_ADC_ACTL); val |= ADC_ACTL_PA_EN; CODEC_WRITE(sc, AC_ADC_ACTL, val); /* Unmute PA */ node = ofw_bus_get_node(sc->dev); len = OF_getencprop(node, "allwinner,pa-gpios", prop, sizeof(prop)); if (len > 0 && (len / sizeof(prop[0])) == 4) { gpio = OF_device_from_xref(prop[0]); if (gpio != NULL) { pin = prop[1] * 32 + prop[2]; GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT); GPIO_PIN_SET(gpio, pin, GPIO_PIN_LOW); } } return (0); } static const struct a10codec_mixer { unsigned reg; unsigned mask; unsigned shift; } a10codec_mixers[SOUND_MIXER_NRDEVICES] = { [SOUND_MIXER_VOLUME] = { AC_DAC_ACTL, DAC_ACTL_PAVOL_MASK, DAC_ACTL_PAVOL_SHIFT }, [SOUND_MIXER_LINE] = { AC_ADC_ACTL, ADC_ACTL_LNPREG_MASK, ADC_ACTL_LNPREG_SHIFT }, [SOUND_MIXER_RECLEV] = { AC_ADC_ACTL, ADC_ACTL_ADCG_MASK, ADC_ACTL_ADCG_SHIFT }, }; static int a10codec_mixer_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) { struct a10codec_info *sc = mix_getdevinfo(m); uint32_t val; unsigned nvol, max; max = a10codec_mixers[dev].mask >> a10codec_mixers[dev].shift; nvol = (left * max) / 100; val = CODEC_READ(sc, a10codec_mixers[dev].reg); val &= ~a10codec_mixers[dev].mask; val |= (nvol << a10codec_mixers[dev].shift); CODEC_WRITE(sc, a10codec_mixers[dev].reg, val); left = right = (left * 100) / max; return (left | (right << 8)); } static uint32_t a10codec_mixer_setrecsrc(struct snd_mixer *m, uint32_t src) { struct a10codec_info *sc = mix_getdevinfo(m); uint32_t val; val = CODEC_READ(sc, AC_ADC_ACTL); switch (src) { case SOUND_MASK_LINE: /* line-in */ val &= ~ADC_ACTL_ADCIS_MASK; val |= (ADC_IS_LINEIN << ADC_ACTL_ADCIS_SHIFT); break; case SOUND_MASK_MIC: /* MIC1 */ val &= ~ADC_ACTL_ADCIS_MASK; val |= (ADC_IS_MIC1 << ADC_ACTL_ADCIS_SHIFT); break; case SOUND_MASK_LINE1: /* MIC2 */ val &= ~ADC_ACTL_ADCIS_MASK; val |= (ADC_IS_MIC2 << ADC_ACTL_ADCIS_SHIFT); break; default: break; } CODEC_WRITE(sc, AC_ADC_ACTL, val); switch ((val & ADC_ACTL_ADCIS_MASK) >> ADC_ACTL_ADCIS_SHIFT) { case ADC_IS_LINEIN: return (SOUND_MASK_LINE); case ADC_IS_MIC1: return (SOUND_MASK_MIC); case ADC_IS_MIC2: return (SOUND_MASK_LINE1); default: return (0); } } static kobj_method_t a10codec_mixer_methods[] = { KOBJMETHOD(mixer_init, a10codec_mixer_init), KOBJMETHOD(mixer_set, a10codec_mixer_set), KOBJMETHOD(mixer_setrecsrc, a10codec_mixer_setrecsrc), KOBJMETHOD_END }; MIXER_DECLARE(a10codec_mixer); /* * Channel interface */ static void a10codec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) { struct a10codec_chinfo *ch = arg; if (error != 0) return; ch->physaddr = segs[0].ds_addr; } static void a10codec_transfer(struct a10codec_chinfo *ch) { bus_addr_t src, dst; int error; if (ch->dir == PCMDIR_PLAY) { src = ch->physaddr + ch->pos; dst = ch->fifo; } else { src = ch->fifo; dst = ch->physaddr + ch->pos; } error = SUNXI_DMA_TRANSFER(ch->dmac, ch->dmachan, src, dst, ch->blocksize); if (error) { ch->run = 0; device_printf(ch->parent->dev, "DMA transfer failed: %d\n", error); } } static void a10codec_dmaconfig(struct a10codec_chinfo *ch) { struct a10codec_info *sc = ch->parent; struct sunxi_dma_config conf; memset(&conf, 0, sizeof(conf)); conf.src_width = conf.dst_width = 16; conf.src_burst_len = conf.dst_burst_len = 4; if (ch->dir == PCMDIR_PLAY) { conf.dst_noincr = true; conf.src_drqtype = sc->drqtype_sdram; conf.dst_drqtype = sc->drqtype_codec; } else { conf.src_noincr = true; conf.src_drqtype = sc->drqtype_codec; conf.dst_drqtype = sc->drqtype_sdram; } SUNXI_DMA_SET_CONFIG(ch->dmac, ch->dmachan, &conf); } static void a10codec_dmaintr(void *priv) { struct a10codec_chinfo *ch = priv; unsigned bufsize; bufsize = sndbuf_getsize(ch->buffer); ch->pos += ch->blocksize; if (ch->pos >= bufsize) ch->pos -= bufsize; if (ch->run) { chn_intr(ch->channel); a10codec_transfer(ch); } } static unsigned a10codec_fs(struct a10codec_chinfo *ch) { switch (ch->speed) { case 48000: return (DAC_FS_48KHZ); case 24000: return (DAC_FS_24KHZ); case 12000: return (DAC_FS_12KHZ); case 192000: return (DAC_FS_192KHZ); case 32000: return (DAC_FS_32KHZ); case 16000: return (DAC_FS_16KHZ); case 8000: return (DAC_FS_8KHZ); case 96000: return (DAC_FS_96KHZ); default: return (DAC_FS_48KHZ); } } static void a10codec_start(struct a10codec_chinfo *ch) { struct a10codec_info *sc = ch->parent; uint32_t val; ch->pos = 0; if (ch->dir == PCMDIR_PLAY) { /* Flush DAC FIFO */ CODEC_WRITE(sc, AC_DAC_FIFOC, DAC_FIFOC_FIFO_FLUSH); /* Clear DAC FIFO status */ CODEC_WRITE(sc, AC_DAC_FIFOS, CODEC_READ(sc, AC_DAC_FIFOS)); /* Enable DAC analog left/right channels and output mixer */ val = CODEC_READ(sc, AC_DAC_ACTL); val |= DAC_ACTL_DACAREN; val |= DAC_ACTL_DACALEN; val |= DAC_ACTL_DACPAS; CODEC_WRITE(sc, AC_DAC_ACTL, val); /* Configure DAC DMA channel */ a10codec_dmaconfig(ch); /* Configure DAC FIFO */ CODEC_WRITE(sc, AC_DAC_FIFOC, (AFMT_CHANNEL(ch->format) == 1 ? DAC_FIFOC_MONO_EN : 0) | (a10codec_fs(ch) << DAC_FIFOC_FS_SHIFT) | (FIFO_MODE_16_15_0 << DAC_FIFOC_FIFO_MODE_SHIFT) | (DRQ_CLR_CNT << DAC_FIFOC_DRQ_CLR_CNT_SHIFT) | (TX_TRIG_LEVEL << DAC_FIFOC_TX_TRIG_LEVEL_SHIFT)); /* Enable DAC DRQ */ val = CODEC_READ(sc, AC_DAC_FIFOC); val |= DAC_FIFOC_DRQ_EN; CODEC_WRITE(sc, AC_DAC_FIFOC, val); } else { /* Flush ADC FIFO */ CODEC_WRITE(sc, AC_ADC_FIFOC, ADC_FIFOC_FIFO_FLUSH); /* Clear ADC FIFO status */ CODEC_WRITE(sc, AC_ADC_FIFOS, CODEC_READ(sc, AC_ADC_FIFOS)); /* Enable ADC analog left/right channels, MIC1 preamp, * and VMIC pin voltage */ val = CODEC_READ(sc, AC_ADC_ACTL); val |= ADC_ACTL_ADCREN; val |= ADC_ACTL_ADCLEN; val |= ADC_ACTL_PREG1EN; val |= ADC_ACTL_VMICEN; CODEC_WRITE(sc, AC_ADC_ACTL, val); /* Configure ADC DMA channel */ a10codec_dmaconfig(ch); /* Configure ADC FIFO */ CODEC_WRITE(sc, AC_ADC_FIFOC, ADC_FIFOC_EN_AD | ADC_FIFOC_RX_FIFO_MODE | (AFMT_CHANNEL(ch->format) == 1 ? ADC_FIFOC_MONO_EN : 0) | (a10codec_fs(ch) << ADC_FIFOC_FS_SHIFT) | (RX_TRIG_LEVEL << ADC_FIFOC_RX_TRIG_LEVEL_SHIFT)); /* Enable ADC DRQ */ val = CODEC_READ(sc, AC_ADC_FIFOC); val |= ADC_FIFOC_DRQ_EN; CODEC_WRITE(sc, AC_ADC_FIFOC, val); } /* Start DMA transfer */ a10codec_transfer(ch); } static void a10codec_stop(struct a10codec_chinfo *ch) { struct a10codec_info *sc = ch->parent; uint32_t val; /* Disable DMA channel */ SUNXI_DMA_HALT(ch->dmac, ch->dmachan); if (ch->dir == PCMDIR_PLAY) { /* Disable DAC analog left/right channels and output mixer */ val = CODEC_READ(sc, AC_DAC_ACTL); val &= ~DAC_ACTL_DACAREN; val &= ~DAC_ACTL_DACALEN; val &= ~DAC_ACTL_DACPAS; CODEC_WRITE(sc, AC_DAC_ACTL, val); /* Disable DAC DRQ */ CODEC_WRITE(sc, AC_DAC_FIFOC, 0); } else { /* Disable ADC analog left/right channels, MIC1 preamp, * and VMIC pin voltage */ val = CODEC_READ(sc, AC_ADC_ACTL); val &= ~ADC_ACTL_ADCREN; val &= ~ADC_ACTL_ADCLEN; val &= ~ADC_ACTL_PREG1EN; val &= ~ADC_ACTL_VMICEN; CODEC_WRITE(sc, AC_ADC_ACTL, val); /* Disable ADC DRQ */ CODEC_WRITE(sc, AC_ADC_FIFOC, 0); } } static void * a10codec_chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) { struct a10codec_info *sc = devinfo; struct a10codec_chinfo *ch = dir == PCMDIR_PLAY ? &sc->play : &sc->rec; int error; ch->parent = sc; ch->channel = c; ch->buffer = b; ch->dir = dir; ch->fifo = rman_get_start(sc->res[0]) + (dir == PCMDIR_REC ? AC_ADC_RXDATA : AC_DAC_TXDATA); ch->dmac = devclass_get_device(devclass_find("a10dmac"), 0); if (ch->dmac == NULL) { device_printf(sc->dev, "cannot find DMA controller\n"); return (NULL); } ch->dmachan = SUNXI_DMA_ALLOC(ch->dmac, false, a10codec_dmaintr, ch); if (ch->dmachan == NULL) { device_printf(sc->dev, "cannot allocate DMA channel\n"); return (NULL); } error = bus_dmamem_alloc(sc->dmat, &ch->dmaaddr, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &ch->dmamap); if (error != 0) { device_printf(sc->dev, "cannot allocate channel buffer\n"); return (NULL); } error = bus_dmamap_load(sc->dmat, ch->dmamap, ch->dmaaddr, sc->dmasize, a10codec_dmamap_cb, ch, BUS_DMA_NOWAIT); if (error != 0) { device_printf(sc->dev, "cannot load DMA map\n"); return (NULL); } memset(ch->dmaaddr, 0, sc->dmasize); if (sndbuf_setup(ch->buffer, ch->dmaaddr, sc->dmasize) != 0) { device_printf(sc->dev, "cannot setup sndbuf\n"); return (NULL); } return (ch); } static int a10codec_chan_free(kobj_t obj, void *data) { struct a10codec_chinfo *ch = data; struct a10codec_info *sc = ch->parent; SUNXI_DMA_FREE(ch->dmac, ch->dmachan); bus_dmamap_unload(sc->dmat, ch->dmamap); bus_dmamem_free(sc->dmat, ch->dmaaddr, ch->dmamap); return (0); } static int a10codec_chan_setformat(kobj_t obj, void *data, uint32_t format) { struct a10codec_chinfo *ch = data; ch->format = format; return (0); } static uint32_t a10codec_chan_setspeed(kobj_t obj, void *data, uint32_t speed) { struct a10codec_chinfo *ch = data; /* * The codec supports full duplex operation but both DAC and ADC * use the same source clock (PLL2). Limit the available speeds to * those supported by a 24576000 Hz input. */ switch (speed) { case 8000: case 12000: case 16000: case 24000: case 32000: case 48000: ch->speed = speed; break; case 96000: case 192000: /* 96 KHz / 192 KHz mode only supported for playback */ if (ch->dir == PCMDIR_PLAY) { ch->speed = speed; } else { ch->speed = 48000; } break; case 44100: ch->speed = 48000; break; case 22050: ch->speed = 24000; break; case 11025: ch->speed = 12000; break; default: ch->speed = 48000; break; } return (ch->speed); } static uint32_t a10codec_chan_setblocksize(kobj_t obj, void *data, uint32_t blocksize) { struct a10codec_chinfo *ch = data; ch->blocksize = blocksize & ~3; return (ch->blocksize); } static int a10codec_chan_trigger(kobj_t obj, void *data, int go) { struct a10codec_chinfo *ch = data; struct a10codec_info *sc = ch->parent; if (!PCMTRIG_COMMON(go)) return (0); snd_mtxlock(sc->lock); switch (go) { case PCMTRIG_START: ch->run = 1; a10codec_start(ch); break; case PCMTRIG_STOP: case PCMTRIG_ABORT: ch->run = 0; a10codec_stop(ch); break; default: break; } snd_mtxunlock(sc->lock); return (0); } static uint32_t a10codec_chan_getptr(kobj_t obj, void *data) { struct a10codec_chinfo *ch = data; return (ch->pos); } static struct pcmchan_caps * a10codec_chan_getcaps(kobj_t obj, void *data) { struct a10codec_chinfo *ch = data; if (ch->dir == PCMDIR_PLAY) { return (&a10codec_pcaps); } else { return (&a10codec_rcaps); } } static kobj_method_t a10codec_chan_methods[] = { KOBJMETHOD(channel_init, a10codec_chan_init), KOBJMETHOD(channel_free, a10codec_chan_free), KOBJMETHOD(channel_setformat, a10codec_chan_setformat), KOBJMETHOD(channel_setspeed, a10codec_chan_setspeed), KOBJMETHOD(channel_setblocksize, a10codec_chan_setblocksize), KOBJMETHOD(channel_trigger, a10codec_chan_trigger), KOBJMETHOD(channel_getptr, a10codec_chan_getptr), KOBJMETHOD(channel_getcaps, a10codec_chan_getcaps), KOBJMETHOD_END }; CHANNEL_DECLARE(a10codec_chan); /* * Device interface */ static int a10codec_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "allwinner,sun7i-a20-codec")) return (ENXIO); device_set_desc(dev, "Allwinner Audio Codec"); return (BUS_PROBE_DEFAULT); } static int a10codec_attach(device_t dev) { struct a10codec_info *sc; char status[SND_STATUSLEN]; + clk_t clk_apb, clk_codec; uint32_t val; int error; sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); sc->dev = dev; sc->lock = snd_mtxcreate(device_get_nameunit(dev), "a10codec softc"); if (bus_alloc_resources(dev, a10codec_spec, sc->res)) { device_printf(dev, "cannot allocate resources for device\n"); error = ENXIO; goto fail; } /* XXX DRQ types should come from FDT, but how? */ if (ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-codec") || ofw_bus_is_compatible(dev, "allwinner,sun7i-a20-codec")) { sc->drqtype_codec = 19; sc->drqtype_sdram = 22; } else { device_printf(dev, "DRQ types not known for this SoC\n"); error = ENXIO; goto fail; } sc->dmasize = 131072; error = bus_dma_tag_create( bus_get_dma_tag(dev), 4, sc->dmasize, /* alignment, boundary */ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ sc->dmasize, 1, /* maxsize, nsegs */ sc->dmasize, 0, /* maxsegsize, flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->dmat); if (error != 0) { device_printf(dev, "cannot create DMA tag\n"); goto fail; } + /* Get clocks */ + error = clk_get_by_ofw_name(dev, "apb", &clk_apb); + if (error != 0) { + device_printf(dev, "cannot find apb clock\n"); + goto fail; + } + error = clk_get_by_ofw_name(dev, "codec", &clk_codec); + if (error != 0) { + device_printf(dev, "cannot find codec clock\n"); + goto fail; + } + + /* Gating APB clock for codec */ + error = clk_enable(clk_apb); + if (error != 0) { + device_printf(dev, "cannot enable apb clock\n"); + goto fail; + } /* Activate audio codec clock. According to the A10 and A20 user * manuals, Audio_pll can be either 24.576MHz or 22.5792MHz. Most * audio sampling rates require an 24.576MHz input clock with the * exception of 44.1kHz, 22.05kHz, and 11.025kHz. Unfortunately, * both capture and playback use the same clock source so to * safely support independent full duplex operation, we use a fixed * 24.576MHz clock source and don't advertise native support for * the three sampling rates that require a 22.5792MHz input. */ - a10_clk_codec_activate(24576000); + error = clk_set_freq(clk_codec, 24576000, CLK_SET_ROUND_DOWN); + if (error != 0) { + device_printf(dev, "cannot set codec clock frequency\n"); + goto fail; + } + /* Enable audio codec clock */ + error = clk_enable(clk_codec); + if (error != 0) { + device_printf(dev, "cannot enable codec clock\n"); + goto fail; + } /* Enable DAC */ val = CODEC_READ(sc, AC_DAC_DPC); val |= DAC_DPC_EN_DA; CODEC_WRITE(sc, AC_DAC_DPC, val); #ifdef notdef error = snd_setup_intr(dev, sc->irq, INTR_MPSAFE, a10codec_intr, sc, &sc->ih); if (error != 0) { device_printf(dev, "could not setup interrupt handler\n"); goto fail; } #endif if (mixer_init(dev, &a10codec_mixer_class, sc)) { device_printf(dev, "mixer_init failed\n"); goto fail; } pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); if (pcm_register(dev, sc, 1, 1)) { device_printf(dev, "pcm_register failed\n"); goto fail; } pcm_addchan(dev, PCMDIR_PLAY, &a10codec_chan_class, sc); pcm_addchan(dev, PCMDIR_REC, &a10codec_chan_class, sc); snprintf(status, SND_STATUSLEN, "at %s", ofw_bus_get_name(dev)); pcm_setstatus(dev, status); return (0); fail: bus_release_resources(dev, a10codec_spec, sc->res); snd_mtxfree(sc->lock); free(sc, M_DEVBUF); return (error); } static device_method_t a10codec_pcm_methods[] = { /* Device interface */ DEVMETHOD(device_probe, a10codec_probe), DEVMETHOD(device_attach, a10codec_attach), DEVMETHOD_END }; static driver_t a10codec_pcm_driver = { "pcm", a10codec_pcm_methods, PCM_SOFTC_SIZE, }; DRIVER_MODULE(a10codec, simplebus, a10codec_pcm_driver, pcm_devclass, 0, 0); MODULE_DEPEND(a10codec, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); MODULE_VERSION(a10codec, 1); Index: head/sys/arm/allwinner/a10_dmac.c =================================================================== --- head/sys/arm/allwinner/a10_dmac.c (revision 297626) +++ head/sys/arm/allwinner/a10_dmac.c (revision 297627) @@ -1,460 +1,470 @@ /*- * Copyright (c) 2014-2016 Jared D. McNeill * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ /* * Allwinner A10/A20 DMA controller */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include -#include +#include #include "sunxi_dma_if.h" #define NDMA_CHANNELS 8 #define DDMA_CHANNELS 8 enum a10dmac_type { CH_NDMA, CH_DDMA }; struct a10dmac_softc; struct a10dmac_channel { struct a10dmac_softc * ch_sc; uint8_t ch_index; enum a10dmac_type ch_type; void (*ch_callback)(void *); void * ch_callbackarg; uint32_t ch_regoff; }; struct a10dmac_softc { struct resource * sc_res[2]; struct mtx sc_mtx; void * sc_ih; struct a10dmac_channel sc_ndma_channels[NDMA_CHANNELS]; struct a10dmac_channel sc_ddma_channels[DDMA_CHANNELS]; }; static struct resource_spec a10dmac_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE }, { -1, 0 } }; #define DMA_READ(sc, reg) bus_read_4((sc)->sc_res[0], (reg)) #define DMA_WRITE(sc, reg, val) bus_write_4((sc)->sc_res[0], (reg), (val)) #define DMACH_READ(ch, reg) \ DMA_READ((ch)->ch_sc, (reg) + (ch)->ch_regoff) #define DMACH_WRITE(ch, reg, val) \ DMA_WRITE((ch)->ch_sc, (reg) + (ch)->ch_regoff, (val)) static void a10dmac_intr(void *); static int a10dmac_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-dma")) return (ENXIO); device_set_desc(dev, "Allwinner DMA controller"); return (BUS_PROBE_DEFAULT); } static int a10dmac_attach(device_t dev) { struct a10dmac_softc *sc; unsigned int index; + clk_t clk; int error; sc = device_get_softc(dev); if (bus_alloc_resources(dev, a10dmac_spec, sc->sc_res)) { device_printf(dev, "cannot allocate resources for device\n"); return (ENXIO); } mtx_init(&sc->sc_mtx, "a10 dmac", NULL, MTX_SPIN); /* Activate DMA controller clock */ - a10_clk_dmac_activate(); + error = clk_get_by_ofw_index(dev, 0, &clk); + if (error != 0) { + device_printf(dev, "cannot get clock\n"); + return (error); + } + error = clk_enable(clk); + if (error != 0) { + device_printf(dev, "cannot enable clock\n"); + return (error); + } /* Disable all interrupts and clear pending status */ DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, 0); DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, ~0); /* Initialize channels */ for (index = 0; index < NDMA_CHANNELS; index++) { sc->sc_ndma_channels[index].ch_sc = sc; sc->sc_ndma_channels[index].ch_index = index; sc->sc_ndma_channels[index].ch_type = CH_NDMA; sc->sc_ndma_channels[index].ch_callback = NULL; sc->sc_ndma_channels[index].ch_callbackarg = NULL; sc->sc_ndma_channels[index].ch_regoff = AWIN_NDMA_REG(index); DMACH_WRITE(&sc->sc_ndma_channels[index], AWIN_NDMA_CTL_REG, 0); } for (index = 0; index < DDMA_CHANNELS; index++) { sc->sc_ddma_channels[index].ch_sc = sc; sc->sc_ddma_channels[index].ch_index = index; sc->sc_ddma_channels[index].ch_type = CH_DDMA; sc->sc_ddma_channels[index].ch_callback = NULL; sc->sc_ddma_channels[index].ch_callbackarg = NULL; sc->sc_ddma_channels[index].ch_regoff = AWIN_DDMA_REG(index); DMACH_WRITE(&sc->sc_ddma_channels[index], AWIN_DDMA_CTL_REG, 0); } error = bus_setup_intr(dev, sc->sc_res[1], INTR_MPSAFE | INTR_TYPE_MISC, NULL, a10dmac_intr, sc, &sc->sc_ih); if (error != 0) { device_printf(dev, "could not setup interrupt handler\n"); bus_release_resources(dev, a10dmac_spec, sc->sc_res); mtx_destroy(&sc->sc_mtx); return (ENXIO); } return (0); } static void a10dmac_intr(void *priv) { struct a10dmac_softc *sc = priv; uint32_t sta, bit, mask; uint8_t index; sta = DMA_READ(sc, AWIN_DMA_IRQ_PEND_STA_REG); DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, sta); while ((bit = ffs(sta & AWIN_DMA_IRQ_END_MASK)) != 0) { mask = (1U << (bit - 1)); sta &= ~mask; /* * Map status bit to channel number. The status register is * encoded with two bits of status per channel (lowest bit * is half transfer pending, highest bit is end transfer * pending). The 8 normal DMA channel status are in the lower * 16 bits and the 8 dedicated DMA channel status are in * the upper 16 bits. The output is a channel number from 0-7. */ index = ((bit - 1) / 2) & 7; if (mask & AWIN_DMA_IRQ_NDMA) { if (sc->sc_ndma_channels[index].ch_callback == NULL) continue; sc->sc_ndma_channels[index].ch_callback( sc->sc_ndma_channels[index].ch_callbackarg); } else { if (sc->sc_ddma_channels[index].ch_callback == NULL) continue; sc->sc_ddma_channels[index].ch_callback( sc->sc_ddma_channels[index].ch_callbackarg); } } } static uint32_t a10dmac_read_ctl(struct a10dmac_channel *ch) { if (ch->ch_type == CH_NDMA) { return (DMACH_READ(ch, AWIN_NDMA_CTL_REG)); } else { return (DMACH_READ(ch, AWIN_DDMA_CTL_REG)); } } static void a10dmac_write_ctl(struct a10dmac_channel *ch, uint32_t val) { if (ch->ch_type == CH_NDMA) { DMACH_WRITE(ch, AWIN_NDMA_CTL_REG, val); } else { DMACH_WRITE(ch, AWIN_DDMA_CTL_REG, val); } } static int a10dmac_set_config(device_t dev, void *priv, const struct sunxi_dma_config *cfg) { struct a10dmac_channel *ch = priv; uint32_t val; unsigned int dst_dw, dst_bl, dst_bs, dst_wc, dst_am; unsigned int src_dw, src_bl, src_bs, src_wc, src_am; switch (cfg->dst_width) { case 8: dst_dw = AWIN_DMA_CTL_DATA_WIDTH_8; break; case 16: dst_dw = AWIN_DMA_CTL_DATA_WIDTH_16; break; case 32: dst_dw = AWIN_DMA_CTL_DATA_WIDTH_32; break; default: return (EINVAL); } switch (cfg->dst_burst_len) { case 1: dst_bl = AWIN_DMA_CTL_BURST_LEN_1; break; case 4: dst_bl = AWIN_DMA_CTL_BURST_LEN_4; break; case 8: dst_bl = AWIN_DMA_CTL_BURST_LEN_8; break; default: return (EINVAL); } switch (cfg->src_width) { case 8: src_dw = AWIN_DMA_CTL_DATA_WIDTH_8; break; case 16: src_dw = AWIN_DMA_CTL_DATA_WIDTH_16; break; case 32: src_dw = AWIN_DMA_CTL_DATA_WIDTH_32; break; default: return (EINVAL); } switch (cfg->src_burst_len) { case 1: src_bl = AWIN_DMA_CTL_BURST_LEN_1; break; case 4: src_bl = AWIN_DMA_CTL_BURST_LEN_4; break; case 8: src_bl = AWIN_DMA_CTL_BURST_LEN_8; break; default: return (EINVAL); } val = (dst_dw << AWIN_DMA_CTL_DST_DATA_WIDTH_SHIFT) | (dst_bl << AWIN_DMA_CTL_DST_BURST_LEN_SHIFT) | (cfg->dst_drqtype << AWIN_DMA_CTL_DST_DRQ_TYPE_SHIFT) | (src_dw << AWIN_DMA_CTL_SRC_DATA_WIDTH_SHIFT) | (src_bl << AWIN_DMA_CTL_SRC_BURST_LEN_SHIFT) | (cfg->src_drqtype << AWIN_DMA_CTL_SRC_DRQ_TYPE_SHIFT); if (ch->ch_type == CH_NDMA) { if (cfg->dst_noincr) val |= AWIN_NDMA_CTL_DST_ADDR_NOINCR; if (cfg->src_noincr) val |= AWIN_NDMA_CTL_SRC_ADDR_NOINCR; DMACH_WRITE(ch, AWIN_NDMA_CTL_REG, val); } else { dst_am = cfg->dst_noincr ? AWIN_DDMA_CTL_DMA_ADDR_IO : AWIN_DDMA_CTL_DMA_ADDR_LINEAR; src_am = cfg->src_noincr ? AWIN_DDMA_CTL_DMA_ADDR_IO : AWIN_DDMA_CTL_DMA_ADDR_LINEAR; val |= (dst_am << AWIN_DDMA_CTL_DST_ADDR_MODE_SHIFT); val |= (src_am << AWIN_DDMA_CTL_SRC_ADDR_MODE_SHIFT); DMACH_WRITE(ch, AWIN_DDMA_CTL_REG, val); dst_bs = cfg->dst_blksize - 1; dst_wc = cfg->dst_wait_cyc - 1; src_bs = cfg->src_blksize - 1; src_wc = cfg->src_wait_cyc - 1; DMACH_WRITE(ch, AWIN_DDMA_PARA_REG, (dst_bs << AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_SHIFT) | (dst_wc << AWIN_DDMA_PARA_DST_WAIT_CYC_SHIFT) | (src_bs << AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_SHIFT) | (src_wc << AWIN_DDMA_PARA_SRC_WAIT_CYC_SHIFT)); } return (0); } static void * a10dmac_alloc(device_t dev, bool dedicated, void (*cb)(void *), void *cbarg) { struct a10dmac_softc *sc = device_get_softc(dev); struct a10dmac_channel *ch_list; struct a10dmac_channel *ch = NULL; uint32_t irqen; uint8_t ch_count, index; if (dedicated) { ch_list = sc->sc_ddma_channels; ch_count = DDMA_CHANNELS; } else { ch_list = sc->sc_ndma_channels; ch_count = NDMA_CHANNELS; } mtx_lock_spin(&sc->sc_mtx); for (index = 0; index < ch_count; index++) { if (ch_list[index].ch_callback == NULL) { ch = &ch_list[index]; ch->ch_callback = cb; ch->ch_callbackarg = cbarg; irqen = DMA_READ(sc, AWIN_DMA_IRQ_EN_REG); if (ch->ch_type == CH_NDMA) irqen |= AWIN_DMA_IRQ_NDMA_END(index); else irqen |= AWIN_DMA_IRQ_DDMA_END(index); DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, irqen); break; } } mtx_unlock_spin(&sc->sc_mtx); return (ch); } static void a10dmac_free(device_t dev, void *priv) { struct a10dmac_channel *ch = priv; struct a10dmac_softc *sc = ch->ch_sc; uint32_t irqen, sta, cfg; mtx_lock_spin(&sc->sc_mtx); irqen = DMA_READ(sc, AWIN_DMA_IRQ_EN_REG); cfg = a10dmac_read_ctl(ch); if (ch->ch_type == CH_NDMA) { sta = AWIN_DMA_IRQ_NDMA_END(ch->ch_index); cfg &= ~AWIN_NDMA_CTL_DMA_LOADING; } else { sta = AWIN_DMA_IRQ_DDMA_END(ch->ch_index); cfg &= ~AWIN_DDMA_CTL_DMA_LOADING; } irqen &= ~sta; a10dmac_write_ctl(ch, cfg); DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, irqen); DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, sta); ch->ch_callback = NULL; ch->ch_callbackarg = NULL; mtx_unlock_spin(&sc->sc_mtx); } static int a10dmac_transfer(device_t dev, void *priv, bus_addr_t src, bus_addr_t dst, size_t nbytes) { struct a10dmac_channel *ch = priv; uint32_t cfg; cfg = a10dmac_read_ctl(ch); if (ch->ch_type == CH_NDMA) { if (cfg & AWIN_NDMA_CTL_DMA_LOADING) return (EBUSY); DMACH_WRITE(ch, AWIN_NDMA_SRC_ADDR_REG, src); DMACH_WRITE(ch, AWIN_NDMA_DEST_ADDR_REG, dst); DMACH_WRITE(ch, AWIN_NDMA_BC_REG, nbytes); cfg |= AWIN_NDMA_CTL_DMA_LOADING; a10dmac_write_ctl(ch, cfg); } else { if (cfg & AWIN_DDMA_CTL_DMA_LOADING) return (EBUSY); DMACH_WRITE(ch, AWIN_DDMA_SRC_START_ADDR_REG, src); DMACH_WRITE(ch, AWIN_DDMA_DEST_START_ADDR_REG, dst); DMACH_WRITE(ch, AWIN_DDMA_BC_REG, nbytes); cfg |= AWIN_DDMA_CTL_DMA_LOADING; a10dmac_write_ctl(ch, cfg); } return (0); } static void a10dmac_halt(device_t dev, void *priv) { struct a10dmac_channel *ch = priv; uint32_t cfg; cfg = a10dmac_read_ctl(ch); if (ch->ch_type == CH_NDMA) { cfg &= ~AWIN_NDMA_CTL_DMA_LOADING; } else { cfg &= ~AWIN_DDMA_CTL_DMA_LOADING; } a10dmac_write_ctl(ch, cfg); } static device_method_t a10dmac_methods[] = { /* Device interface */ DEVMETHOD(device_probe, a10dmac_probe), DEVMETHOD(device_attach, a10dmac_attach), /* sunxi DMA interface */ DEVMETHOD(sunxi_dma_alloc, a10dmac_alloc), DEVMETHOD(sunxi_dma_free, a10dmac_free), DEVMETHOD(sunxi_dma_set_config, a10dmac_set_config), DEVMETHOD(sunxi_dma_transfer, a10dmac_transfer), DEVMETHOD(sunxi_dma_halt, a10dmac_halt), DEVMETHOD_END }; static driver_t a10dmac_driver = { "a10dmac", a10dmac_methods, sizeof(struct a10dmac_softc) }; static devclass_t a10dmac_devclass; DRIVER_MODULE(a10dmac, simplebus, a10dmac_driver, a10dmac_devclass, 0, 0); Index: head/sys/arm/allwinner/a10_ehci.c =================================================================== --- head/sys/arm/allwinner/a10_ehci.c (revision 297626) +++ head/sys/arm/allwinner/a10_ehci.c (revision 297627) @@ -1,334 +1,353 @@ /*- * Copyright (c) 2012 Ganbold Tsagaankhuu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Allwinner A10 attachment driver for the USB Enhanced Host Controller. */ #include __FBSDID("$FreeBSD$"); #include "opt_bus.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include -#include -#include +#include +#include #define EHCI_HC_DEVSTR "Allwinner Integrated USB 2.0 controller" #define SW_USB_PMU_IRQ_ENABLE 0x800 #define SW_SDRAM_REG_HPCR_USB1 (0x250 + ((1 << 2) * 4)) #define SW_SDRAM_REG_HPCR_USB2 (0x250 + ((1 << 2) * 5)) #define SW_SDRAM_BP_HPCR_ACCESS (1 << 0) #define SW_ULPI_BYPASS (1 << 0) #define SW_AHB_INCRX_ALIGN (1 << 8) #define SW_AHB_INCR4 (1 << 9) #define SW_AHB_INCR8 (1 << 10) #define USB_CONF(d) \ (void *)ofw_bus_search_compatible((d), compat_data)->ocd_data #define A10_READ_4(sc, reg) \ bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) #define A10_WRITE_4(sc, reg, data) \ bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) static device_attach_t a10_ehci_attach; static device_detach_t a10_ehci_detach; bs_r_1_proto(reversed); bs_w_1_proto(reversed); +struct aw_ehci_softc { + ehci_softc_t sc; + clk_t clk; + hwreset_t rst; +}; + struct aw_ehci_conf { - int (*clk_activate)(void); - int (*clk_deactivate)(void); bool sdram_init; }; static const struct aw_ehci_conf a10_ehci_conf = { -#if defined(SOC_ALLWINNER_A10) || defined(SOC_ALLWINNER_A20) - .clk_activate = a10_clk_ehci_activate, - .clk_deactivate = a10_clk_ehci_deactivate, -#endif .sdram_init = true, }; static const struct aw_ehci_conf a31_ehci_conf = { -#if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S) - .clk_activate = a31_clk_ehci_activate, - .clk_deactivate = a31_clk_ehci_deactivate, -#endif + .sdram_init = false, }; static struct ofw_compat_data compat_data[] = { { "allwinner,sun4i-a10-ehci", (uintptr_t)&a10_ehci_conf }, { "allwinner,sun6i-a31-ehci", (uintptr_t)&a31_ehci_conf }, { "allwinner,sun7i-a20-ehci", (uintptr_t)&a10_ehci_conf }, { NULL, (uintptr_t)NULL } }; static int a10_ehci_probe(device_t self) { if (!ofw_bus_status_okay(self)) return (ENXIO); if (ofw_bus_search_compatible(self, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(self, EHCI_HC_DEVSTR); return (BUS_PROBE_DEFAULT); } static int a10_ehci_attach(device_t self) { - ehci_softc_t *sc = device_get_softc(self); + struct aw_ehci_softc *aw_sc = device_get_softc(self); + ehci_softc_t *sc = &aw_sc->sc; const struct aw_ehci_conf *conf; bus_space_handle_t bsh; int err; int rid; uint32_t reg_value = 0; conf = USB_CONF(self); - if (conf->clk_activate == NULL) { - device_printf(self, "clock not supported\n"); - return (ENXIO); - } /* initialise some bus fields */ sc->sc_bus.parent = self; sc->sc_bus.devices = sc->sc_devices; sc->sc_bus.devices_max = EHCI_MAX_DEVICES; sc->sc_bus.dma_bits = 32; /* get all DMA memory */ if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) { return (ENOMEM); } sc->sc_bus.usbrev = USB_REV_2_0; rid = 0; sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_io_res) { device_printf(self, "Could not map memory\n"); goto error; } sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); bsh = rman_get_bushandle(sc->sc_io_res); sc->sc_io_size = rman_get_size(sc->sc_io_res); if (bus_space_subregion(sc->sc_io_tag, bsh, 0x00, sc->sc_io_size, &sc->sc_io_hdl) != 0) panic("%s: unable to subregion USB host registers", device_get_name(self)); rid = 0; sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); if (sc->sc_irq_res == NULL) { device_printf(self, "Could not allocate irq\n"); goto error; } sc->sc_bus.bdev = device_add_child(self, "usbus", -1); if (!sc->sc_bus.bdev) { device_printf(self, "Could not add USB device\n"); goto error; } device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); device_set_desc(sc->sc_bus.bdev, EHCI_HC_DEVSTR); sprintf(sc->sc_vendor, "Allwinner"); err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl); if (err) { device_printf(self, "Could not setup irq, %d\n", err); sc->sc_intr_hdl = NULL; goto error; } sc->sc_flags |= EHCI_SCFLG_DONTRESET; + /* De-assert reset */ + if (hwreset_get_by_ofw_idx(self, 0, &aw_sc->rst) == 0) { + err = hwreset_deassert(aw_sc->rst); + if (err != 0) { + device_printf(self, "Could not de-assert reset\n"); + goto error; + } + } + /* Enable clock for USB */ - if (conf->clk_activate() != 0) { - device_printf(self, "Could not activate clock\n"); + err = clk_get_by_ofw_index(self, 0, &aw_sc->clk); + if (err != 0) { + device_printf(self, "Could not get clock\n"); goto error; } + err = clk_enable(aw_sc->clk); + if (err != 0) { + device_printf(self, "Could not enable clock\n"); + goto error; + } /* Enable passby */ reg_value = A10_READ_4(sc, SW_USB_PMU_IRQ_ENABLE); reg_value |= SW_AHB_INCR8; /* AHB INCR8 enable */ reg_value |= SW_AHB_INCR4; /* AHB burst type INCR4 enable */ reg_value |= SW_AHB_INCRX_ALIGN; /* AHB INCRX align enable */ reg_value |= SW_ULPI_BYPASS; /* ULPI bypass enable */ A10_WRITE_4(sc, SW_USB_PMU_IRQ_ENABLE, reg_value); /* Configure port */ if (conf->sdram_init) { reg_value = A10_READ_4(sc, SW_SDRAM_REG_HPCR_USB2); reg_value |= SW_SDRAM_BP_HPCR_ACCESS; A10_WRITE_4(sc, SW_SDRAM_REG_HPCR_USB2, reg_value); } err = ehci_init(sc); if (!err) { err = device_probe_and_attach(sc->sc_bus.bdev); } if (err) { device_printf(self, "USB init failed err=%d\n", err); goto error; } return (0); error: + if (aw_sc->clk) + clk_release(aw_sc->clk); a10_ehci_detach(self); return (ENXIO); } static int a10_ehci_detach(device_t self) { - ehci_softc_t *sc = device_get_softc(self); + struct aw_ehci_softc *aw_sc = device_get_softc(self); + ehci_softc_t *sc = &aw_sc->sc; const struct aw_ehci_conf *conf; device_t bdev; int err; uint32_t reg_value = 0; conf = USB_CONF(self); if (sc->sc_bus.bdev) { bdev = sc->sc_bus.bdev; device_detach(bdev); device_delete_child(self, bdev); } /* during module unload there are lots of children leftover */ device_delete_children(self); if (sc->sc_irq_res && sc->sc_intr_hdl) { /* * only call ehci_detach() after ehci_init() */ ehci_detach(sc); err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); if (err) /* XXX or should we panic? */ device_printf(self, "Could not tear down irq, %d\n", err); sc->sc_intr_hdl = NULL; } if (sc->sc_irq_res) { bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res); sc->sc_irq_res = NULL; } if (sc->sc_io_res) { bus_release_resource(self, SYS_RES_MEMORY, 0, sc->sc_io_res); sc->sc_io_res = NULL; } usb_bus_mem_free_all(&sc->sc_bus, &ehci_iterate_hw_softc); /* Disable configure port */ if (conf->sdram_init) { reg_value = A10_READ_4(sc, SW_SDRAM_REG_HPCR_USB2); reg_value &= ~SW_SDRAM_BP_HPCR_ACCESS; A10_WRITE_4(sc, SW_SDRAM_REG_HPCR_USB2, reg_value); } /* Disable passby */ reg_value = A10_READ_4(sc, SW_USB_PMU_IRQ_ENABLE); reg_value &= ~SW_AHB_INCR8; /* AHB INCR8 disable */ reg_value &= ~SW_AHB_INCR4; /* AHB burst type INCR4 disable */ reg_value &= ~SW_AHB_INCRX_ALIGN; /* AHB INCRX align disable */ reg_value &= ~SW_ULPI_BYPASS; /* ULPI bypass disable */ A10_WRITE_4(sc, SW_USB_PMU_IRQ_ENABLE, reg_value); /* Disable clock for USB */ - conf->clk_deactivate(); + clk_disable(aw_sc->clk); + clk_release(aw_sc->clk); + + /* Assert reset */ + if (aw_sc->rst != NULL) { + hwreset_assert(aw_sc->rst); + hwreset_release(aw_sc->rst); + } return (0); } static device_method_t ehci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, a10_ehci_probe), DEVMETHOD(device_attach, a10_ehci_attach), DEVMETHOD(device_detach, a10_ehci_detach), DEVMETHOD(device_suspend, bus_generic_suspend), DEVMETHOD(device_resume, bus_generic_resume), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD_END }; static driver_t ehci_driver = { .name = "ehci", .methods = ehci_methods, .size = sizeof(ehci_softc_t), }; static devclass_t ehci_devclass; DRIVER_MODULE(ehci, simplebus, ehci_driver, ehci_devclass, 0, 0); MODULE_DEPEND(ehci, usb, 1, 1, 1); Index: head/sys/arm/allwinner/a10_fb.c =================================================================== --- head/sys/arm/allwinner/a10_fb.c (revision 297626) +++ head/sys/arm/allwinner/a10_fb.c (revision 297627) @@ -1,545 +1,662 @@ /*- * Copyright (c) 2016 Jared McNeill * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* * Allwinner A10/A20 Framebuffer */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include -#include +#include +#include #include "fb_if.h" #include "hdmi_if.h" #define FB_DEFAULT_W 800 #define FB_DEFAULT_H 600 #define FB_DEFAULT_REF 60 #define FB_BPP 32 #define FB_ALIGN 0x1000 #define HDMI_ENABLE_DELAY 20000 +#define DEBE_FREQ 300000000 #define DOT_CLOCK_TO_HZ(c) ((c) * 1000) /* Display backend */ #define DEBE_REG_START 0x800 #define DEBE_REG_END 0x1000 #define DEBE_REG_WIDTH 4 #define DEBE_MODCTL 0x800 #define MODCTL_ITLMOD_EN (1 << 28) #define MODCTL_OUT_SEL_MASK (0x7 << 20) #define MODCTL_OUT_SEL(sel) ((sel) << 20) #define OUT_SEL_LCD 0 #define MODCTL_LAY0_EN (1 << 8) #define MODCTL_START_CTL (1 << 1) #define MODCTL_EN (1 << 0) #define DEBE_DISSIZE 0x808 #define DIS_HEIGHT(h) (((h) - 1) << 16) #define DIS_WIDTH(w) (((w) - 1) << 0) #define DEBE_LAYSIZE0 0x810 #define LAY_HEIGHT(h) (((h) - 1) << 16) #define LAY_WIDTH(w) (((w) - 1) << 0) #define DEBE_LAYCOOR0 0x820 #define LAY_XCOOR(x) ((x) << 16) #define LAY_YCOOR(y) ((y) << 0) #define DEBE_LAYLINEWIDTH0 0x840 #define DEBE_LAYFB_L32ADD0 0x850 #define LAYFB_L32ADD(pa) ((pa) << 3) #define DEBE_LAYFB_H4ADD 0x860 #define LAY0FB_H4ADD(pa) ((pa) >> 29) #define DEBE_REGBUFFCTL 0x870 #define REGBUFFCTL_LOAD (1 << 0) #define DEBE_ATTCTL1 0x8a0 #define ATTCTL1_FBFMT(fmt) ((fmt) << 8) #define FBFMT_XRGB8888 9 #define ATTCTL1_FBPS(ps) ((ps) << 0) #define FBPS_32BPP_ARGB 0 /* Timing controller */ #define TCON_GCTL 0x000 #define GCTL_TCON_EN (1 << 31) #define GCTL_IO_MAP_SEL_TCON1 (1 << 0) #define TCON_GINT1 0x008 #define GINT1_TCON1_LINENO(n) (((n) + 2) << 0) #define TCON0_DCLK 0x044 #define DCLK_EN 0xf0000000 #define TCON1_CTL 0x090 #define TCON1_EN (1 << 31) #define INTERLACE_EN (1 << 20) #define TCON1_SRC_SEL(src) ((src) << 0) #define TCON1_SRC_CH1 0 #define TCON1_SRC_CH2 1 #define TCON1_SRC_BLUE 2 #define TCON1_START_DELAY(sd) ((sd) << 4) #define TCON1_BASIC0 0x094 #define TCON1_BASIC1 0x098 #define TCON1_BASIC2 0x09c #define TCON1_BASIC3 0x0a0 #define TCON1_BASIC4 0x0a4 #define TCON1_BASIC5 0x0a8 #define BASIC_X(x) (((x) - 1) << 16) #define BASIC_Y(y) (((y) - 1) << 0) #define BASIC3_HT(ht) (((ht) - 1) << 16) #define BASIC3_HBP(hbp) (((hbp) - 1) << 0) #define BASIC4_VT(vt) ((vt) << 16) #define BASIC4_VBP(vbp) (((vbp) - 1) << 0) #define BASIC5_HSPW(hspw) (((hspw) - 1) << 16) #define BASIC5_VSPW(vspw) (((vspw) - 1) << 0) #define TCON1_IO_POL 0x0f0 #define IO_POL_IO2_INV (1 << 26) #define IO_POL_PHSYNC (1 << 25) #define IO_POL_PVSYNC (1 << 24) #define TCON1_IO_TRI 0x0f4 #define IO0_OUTPUT_TRI_EN (1 << 24) #define IO1_OUTPUT_TRI_EN (1 << 25) #define IO_TRI_MASK 0xffffffff #define START_DELAY(vbl) (MIN(32, (vbl)) - 2) #define VBLANK_LEN(vt, vd, i) ((((vt) << (i)) >> 1) - (vd) - 2) #define VTOTAL(vt) ((vt) * 2) #define DIVIDE(x, y) (((x) + ((y) / 2)) / (y)) struct a10fb_softc { device_t dev; device_t fbdev; struct resource *res[2]; /* Framebuffer */ struct fb_info info; size_t fbsize; bus_addr_t paddr; vm_offset_t vaddr; /* HDMI */ eventhandler_tag hdmi_evh; }; static struct resource_spec a10fb_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* DEBE */ { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* TCON */ { -1, 0 } }; #define DEBE_READ(sc, reg) bus_read_4((sc)->res[0], (reg)) #define DEBE_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) #define TCON_READ(sc, reg) bus_read_4((sc)->res[1], (reg)) #define TCON_WRITE(sc, reg, val) bus_write_4((sc)->res[1], (reg), (val)) static int a10fb_allocfb(struct a10fb_softc *sc) { sc->vaddr = kmem_alloc_contig(kernel_arena, sc->fbsize, M_NOWAIT | M_ZERO, 0, ~0, FB_ALIGN, 0, VM_MEMATTR_WRITE_COMBINING); if (sc->vaddr == 0) { device_printf(sc->dev, "failed to allocate FB memory\n"); return (ENOMEM); } sc->paddr = pmap_kextract(sc->vaddr); return (0); } static void a10fb_freefb(struct a10fb_softc *sc) { kmem_free(kernel_arena, sc->vaddr, sc->fbsize); } -static void +static int a10fb_setup_debe(struct a10fb_softc *sc, const struct videomode *mode) { int width, height, interlace, reg; + clk_t clk_ahb, clk_dram, clk_debe; + hwreset_t rst; uint32_t val; + int error; interlace = !!(mode->flags & VID_INTERLACE); width = mode->hdisplay; height = mode->vdisplay << interlace; - /* Enable DEBE clocks */ - a10_clk_debe_activate(); + /* Leave reset */ + error = hwreset_get_by_ofw_name(sc->dev, "de_be", &rst); + if (error != 0) { + device_printf(sc->dev, "cannot find reset 'de_be'\n"); + return (error); + } + error = hwreset_deassert(rst); + if (error != 0) { + device_printf(sc->dev, "couldn't de-assert reset 'de_be'\n"); + return (error); + } + /* Gating AHB clock for BE */ + error = clk_get_by_ofw_name(sc->dev, "ahb_de_be", &clk_ahb); + if (error != 0) { + device_printf(sc->dev, "cannot find clk 'ahb_de_be'\n"); + return (error); + } + error = clk_enable(clk_ahb); + if (error != 0) { + device_printf(sc->dev, "cannot enable clk 'ahb_de_be'\n"); + return (error); + } + /* Enable DRAM clock to BE */ + error = clk_get_by_ofw_name(sc->dev, "dram_de_be", &clk_dram); + if (error != 0) { + device_printf(sc->dev, "cannot find clk 'dram_de_be'\n"); + return (error); + } + error = clk_enable(clk_dram); + if (error != 0) { + device_printf(sc->dev, "cannot enable clk 'dram_de_be'\n"); + return (error); + } + /* Set BE clock to 300MHz and enable */ + error = clk_get_by_ofw_name(sc->dev, "de_be", &clk_debe); + if (error != 0) { + device_printf(sc->dev, "cannot find clk 'de_be'\n"); + return (error); + } + error = clk_set_freq(clk_debe, DEBE_FREQ, CLK_SET_ROUND_DOWN); + if (error != 0) { + device_printf(sc->dev, "cannot set 'de_be' frequency\n"); + return (error); + } + error = clk_enable(clk_debe); + if (error != 0) { + device_printf(sc->dev, "cannot enable clk 'de_be'\n"); + return (error); + } /* Initialize all registers to 0 */ for (reg = DEBE_REG_START; reg < DEBE_REG_END; reg += DEBE_REG_WIDTH) DEBE_WRITE(sc, reg, 0); /* Enable display backend */ DEBE_WRITE(sc, DEBE_MODCTL, MODCTL_EN); /* Set display size */ DEBE_WRITE(sc, DEBE_DISSIZE, DIS_HEIGHT(height) | DIS_WIDTH(width)); /* Set layer 0 size, position, and stride */ DEBE_WRITE(sc, DEBE_LAYSIZE0, LAY_HEIGHT(height) | LAY_WIDTH(width)); DEBE_WRITE(sc, DEBE_LAYCOOR0, LAY_XCOOR(0) | LAY_YCOOR(0)); DEBE_WRITE(sc, DEBE_LAYLINEWIDTH0, width * FB_BPP); /* Point layer 0 to FB memory */ DEBE_WRITE(sc, DEBE_LAYFB_L32ADD0, LAYFB_L32ADD(sc->paddr)); DEBE_WRITE(sc, DEBE_LAYFB_H4ADD, LAY0FB_H4ADD(sc->paddr)); /* Set backend format and pixel sequence */ DEBE_WRITE(sc, DEBE_ATTCTL1, ATTCTL1_FBFMT(FBFMT_XRGB8888) | ATTCTL1_FBPS(FBPS_32BPP_ARGB)); /* Enable layer 0, output to LCD, setup interlace */ val = DEBE_READ(sc, DEBE_MODCTL); val |= MODCTL_LAY0_EN; val &= ~MODCTL_OUT_SEL_MASK; val |= MODCTL_OUT_SEL(OUT_SEL_LCD); if (interlace) val |= MODCTL_ITLMOD_EN; else val &= ~MODCTL_ITLMOD_EN; DEBE_WRITE(sc, DEBE_MODCTL, val); /* Commit settings */ DEBE_WRITE(sc, DEBE_REGBUFFCTL, REGBUFFCTL_LOAD); /* Start DEBE */ val = DEBE_READ(sc, DEBE_MODCTL); val |= MODCTL_START_CTL; DEBE_WRITE(sc, DEBE_MODCTL, val); + + return (0); } -static void +static int +a10fb_setup_pll(struct a10fb_softc *sc, uint64_t freq) +{ + clk_t clk_sclk1, clk_sclk2; + int error; + + error = clk_get_by_ofw_name(sc->dev, "lcd_ch1_sclk1", &clk_sclk1); + if (error != 0) { + device_printf(sc->dev, "cannot find clk 'lcd_ch1_sclk1'\n"); + return (error); + } + error = clk_get_by_ofw_name(sc->dev, "lcd_ch1_sclk2", &clk_sclk2); + if (error != 0) { + device_printf(sc->dev, "cannot find clk 'lcd_ch1_sclk2'\n"); + return (error); + } + + error = clk_set_freq(clk_sclk2, freq, 0); + if (error != 0) { + device_printf(sc->dev, "cannot set lcd ch1 frequency\n"); + return (error); + } + error = clk_enable(clk_sclk2); + if (error != 0) { + device_printf(sc->dev, "cannot enable lcd ch1 sclk2\n"); + return (error); + } + error = clk_enable(clk_sclk1); + if (error != 0) { + device_printf(sc->dev, "cannot enable lcd ch1 sclk1\n"); + return (error); + } + + return (0); +} + +static int a10fb_setup_tcon(struct a10fb_softc *sc, const struct videomode *mode) { u_int interlace, hspw, hbp, vspw, vbp, vbl, width, height, start_delay; u_int vtotal, framerate, clk; + clk_t clk_ahb; + hwreset_t rst; uint32_t val; + int error; interlace = !!(mode->flags & VID_INTERLACE); width = mode->hdisplay; height = mode->vdisplay; hspw = mode->hsync_end - mode->hsync_start; hbp = mode->htotal - mode->hsync_start; vspw = mode->vsync_end - mode->vsync_start; vbp = mode->vtotal - mode->vsync_start; vbl = VBLANK_LEN(mode->vtotal, mode->vdisplay, interlace); start_delay = START_DELAY(vbl); - /* Enable LCD clocks */ - a10_clk_lcd_activate(); + /* Leave reset */ + error = hwreset_get_by_ofw_name(sc->dev, "lcd", &rst); + if (error != 0) { + device_printf(sc->dev, "cannot find reset 'lcd'\n"); + return (error); + } + error = hwreset_deassert(rst); + if (error != 0) { + device_printf(sc->dev, "couldn't de-assert reset 'lcd'\n"); + return (error); + } + /* Gating AHB clock for LCD */ + error = clk_get_by_ofw_name(sc->dev, "ahb_lcd", &clk_ahb); + if (error != 0) { + device_printf(sc->dev, "cannot find clk 'ahb_lcd'\n"); + return (error); + } + error = clk_enable(clk_ahb); + if (error != 0) { + device_printf(sc->dev, "cannot enable clk 'ahb_lcd'\n"); + return (error); + } /* Disable TCON and TCON1 */ TCON_WRITE(sc, TCON_GCTL, 0); TCON_WRITE(sc, TCON1_CTL, 0); /* Enable clocks */ TCON_WRITE(sc, TCON0_DCLK, DCLK_EN); /* Disable IO and data output ports */ TCON_WRITE(sc, TCON1_IO_TRI, IO_TRI_MASK); /* Disable TCON and select TCON1 */ TCON_WRITE(sc, TCON_GCTL, GCTL_IO_MAP_SEL_TCON1); /* Source width and height */ TCON_WRITE(sc, TCON1_BASIC0, BASIC_X(width) | BASIC_Y(height)); /* Scaler width and height */ TCON_WRITE(sc, TCON1_BASIC1, BASIC_X(width) | BASIC_Y(height)); /* Output width and height */ TCON_WRITE(sc, TCON1_BASIC2, BASIC_X(width) | BASIC_Y(height)); /* Horizontal total and back porch */ TCON_WRITE(sc, TCON1_BASIC3, BASIC3_HT(mode->htotal) | BASIC3_HBP(hbp)); /* Vertical total and back porch */ vtotal = VTOTAL(mode->vtotal); if (interlace) { framerate = DIVIDE(DIVIDE(DOT_CLOCK_TO_HZ(mode->dot_clock), mode->htotal), mode->vtotal); clk = mode->htotal * (VTOTAL(mode->vtotal) + 1) * framerate; if ((clk / 2) == DOT_CLOCK_TO_HZ(mode->dot_clock)) vtotal += 1; } TCON_WRITE(sc, TCON1_BASIC4, BASIC4_VT(vtotal) | BASIC4_VBP(vbp)); /* Horizontal and vertical sync */ TCON_WRITE(sc, TCON1_BASIC5, BASIC5_HSPW(hspw) | BASIC5_VSPW(vspw)); /* Polarity */ val = IO_POL_IO2_INV; if (mode->flags & VID_PHSYNC) val |= IO_POL_PHSYNC; if (mode->flags & VID_PVSYNC) val |= IO_POL_PVSYNC; TCON_WRITE(sc, TCON1_IO_POL, val); /* Set scan line for TCON1 line trigger */ TCON_WRITE(sc, TCON_GINT1, GINT1_TCON1_LINENO(start_delay)); /* Enable TCON1 */ val = TCON1_EN; if (interlace) val |= INTERLACE_EN; val |= TCON1_START_DELAY(start_delay); val |= TCON1_SRC_SEL(TCON1_SRC_CH1); TCON_WRITE(sc, TCON1_CTL, val); /* Setup PLL */ - a10_clk_tcon_activate(DOT_CLOCK_TO_HZ(mode->dot_clock)); + return (a10fb_setup_pll(sc, DOT_CLOCK_TO_HZ(mode->dot_clock))); } static void a10fb_enable_tcon(struct a10fb_softc *sc, int onoff) { uint32_t val; /* Enable TCON */ val = TCON_READ(sc, TCON_GCTL); if (onoff) val |= GCTL_TCON_EN; else val &= ~GCTL_TCON_EN; TCON_WRITE(sc, TCON_GCTL, val); /* Enable TCON1 IO0/IO1 outputs */ val = TCON_READ(sc, TCON1_IO_TRI); if (onoff) val &= ~(IO0_OUTPUT_TRI_EN | IO1_OUTPUT_TRI_EN); else val |= (IO0_OUTPUT_TRI_EN | IO1_OUTPUT_TRI_EN); TCON_WRITE(sc, TCON1_IO_TRI, val); } static int a10fb_configure(struct a10fb_softc *sc, const struct videomode *mode) { size_t fbsize; int error; fbsize = round_page(mode->hdisplay * mode->vdisplay * (FB_BPP / NBBY)); /* Detach the old FB device */ if (sc->fbdev != NULL) { device_delete_child(sc->dev, sc->fbdev); sc->fbdev = NULL; } /* If the FB size has changed, free the old FB memory */ if (sc->fbsize > 0 && sc->fbsize != fbsize) { a10fb_freefb(sc); sc->vaddr = 0; } /* Allocate the FB if necessary */ sc->fbsize = fbsize; if (sc->vaddr == 0) { error = a10fb_allocfb(sc); if (error != 0) { device_printf(sc->dev, "failed to allocate FB memory\n"); return (ENXIO); } } /* Setup display backend */ - a10fb_setup_debe(sc, mode); + error = a10fb_setup_debe(sc, mode); + if (error != 0) + return (error); /* Setup display timing controller */ - a10fb_setup_tcon(sc, mode); + error = a10fb_setup_tcon(sc, mode); + if (error != 0) + return (error); /* Attach framebuffer device */ sc->info.fb_name = device_get_nameunit(sc->dev); sc->info.fb_vbase = (intptr_t)sc->vaddr; sc->info.fb_pbase = sc->paddr; sc->info.fb_size = sc->fbsize; sc->info.fb_bpp = sc->info.fb_depth = FB_BPP; sc->info.fb_stride = mode->hdisplay * (FB_BPP / NBBY); sc->info.fb_width = mode->hdisplay; sc->info.fb_height = mode->vdisplay; sc->fbdev = device_add_child(sc->dev, "fbd", device_get_unit(sc->dev)); if (sc->fbdev == NULL) { device_printf(sc->dev, "failed to add fbd child\n"); return (ENOENT); } error = device_probe_and_attach(sc->fbdev); if (error != 0) { device_printf(sc->dev, "failed to attach fbd device\n"); return (error); } return (0); } static void a10fb_hdmi_event(void *arg, device_t hdmi_dev) { const struct videomode *mode; struct videomode hdmi_mode; struct a10fb_softc *sc; struct edid_info ei; uint8_t *edid; uint32_t edid_len; int error; sc = arg; edid = NULL; edid_len = 0; mode = NULL; error = HDMI_GET_EDID(hdmi_dev, &edid, &edid_len); if (error != 0) { device_printf(sc->dev, "failed to get EDID: %d\n", error); } else { error = edid_parse(edid, &ei); if (error != 0) { device_printf(sc->dev, "failed to parse EDID: %d\n", error); } else { if (bootverbose) edid_print(&ei); mode = ei.edid_preferred_mode; } } /* If the preferred mode could not be determined, use the default */ if (mode == NULL) mode = pick_mode_by_ref(FB_DEFAULT_W, FB_DEFAULT_H, FB_DEFAULT_REF); if (mode == NULL) { device_printf(sc->dev, "failed to find usable video mode\n"); return; } if (bootverbose) device_printf(sc->dev, "using %dx%d\n", mode->hdisplay, mode->vdisplay); /* Disable HDMI */ HDMI_ENABLE(hdmi_dev, 0); /* Disable timing controller */ a10fb_enable_tcon(sc, 0); /* Configure DEBE and TCON */ error = a10fb_configure(sc, mode); if (error != 0) { device_printf(sc->dev, "failed to configure FB: %d\n", error); return; } hdmi_mode = *mode; hdmi_mode.hskew = mode->hsync_end - mode->hsync_start; hdmi_mode.flags |= VID_HSKEW; HDMI_SET_VIDEOMODE(hdmi_dev, &hdmi_mode); /* Enable timing controller */ a10fb_enable_tcon(sc, 1); DELAY(HDMI_ENABLE_DELAY); /* Enable HDMI */ HDMI_ENABLE(hdmi_dev, 1); } static int a10fb_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "allwinner,sun7i-a20-fb")) return (ENXIO); device_set_desc(dev, "Allwinner Framebuffer"); return (BUS_PROBE_DEFAULT); } static int a10fb_attach(device_t dev) { struct a10fb_softc *sc; sc = device_get_softc(dev); sc->dev = dev; if (bus_alloc_resources(dev, a10fb_spec, sc->res)) { device_printf(dev, "cannot allocate resources for device\n"); return (ENXIO); } sc->hdmi_evh = EVENTHANDLER_REGISTER(hdmi_event, a10fb_hdmi_event, sc, 0); return (0); } static struct fb_info * a10fb_fb_getinfo(device_t dev) { struct a10fb_softc *sc; sc = device_get_softc(dev); return (&sc->info); } static device_method_t a10fb_methods[] = { /* Device interface */ DEVMETHOD(device_probe, a10fb_probe), DEVMETHOD(device_attach, a10fb_attach), /* FB interface */ DEVMETHOD(fb_getinfo, a10fb_fb_getinfo), DEVMETHOD_END }; static driver_t a10fb_driver = { "fb", a10fb_methods, sizeof(struct a10fb_softc), }; static devclass_t a10fb_devclass; DRIVER_MODULE(fb, simplebus, a10fb_driver, a10fb_devclass, 0, 0); Index: head/sys/arm/allwinner/a10_hdmi.c =================================================================== --- head/sys/arm/allwinner/a10_hdmi.c (revision 297626) +++ head/sys/arm/allwinner/a10_hdmi.c (revision 297627) @@ -1,653 +1,718 @@ /*- * Copyright (c) 2016 Jared McNeill * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* * Allwinner A10/A20 HDMI TX */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include -#include +#include #include "hdmi_if.h" #define HDMI_CTRL 0x004 #define CTRL_MODULE_EN (1 << 31) #define HDMI_INT_STATUS 0x008 #define HDMI_HPD 0x00c #define HPD_DET (1 << 0) #define HDMI_VID_CTRL 0x010 #define VID_CTRL_VIDEO_EN (1 << 31) #define VID_CTRL_HDMI_MODE (1 << 30) #define VID_CTRL_INTERLACE (1 << 4) #define VID_CTRL_REPEATER_2X (1 << 0) #define HDMI_VID_TIMING0 0x014 #define VID_ACT_V(v) (((v) - 1) << 16) #define VID_ACT_H(h) (((h) - 1) << 0) #define HDMI_VID_TIMING1 0x018 #define VID_VBP(vbp) (((vbp) - 1) << 16) #define VID_HBP(hbp) (((hbp) - 1) << 0) #define HDMI_VID_TIMING2 0x01c #define VID_VFP(vfp) (((vfp) - 1) << 16) #define VID_HFP(hfp) (((hfp) - 1) << 0) #define HDMI_VID_TIMING3 0x020 #define VID_VSPW(vspw) (((vspw) - 1) << 16) #define VID_HSPW(hspw) (((hspw) - 1) << 0) #define HDMI_VID_TIMING4 0x024 #define TX_CLOCK_NORMAL 0x03e00000 #define VID_VSYNC_ACTSEL (1 << 1) #define VID_HSYNC_ACTSEL (1 << 0) #define HDMI_AUD_CTRL 0x040 #define AUD_CTRL_EN (1 << 31) #define AUD_CTRL_RST (1 << 30) #define HDMI_ADMA_CTRL 0x044 #define HDMI_ADMA_MODE (1 << 31) #define HDMI_ADMA_MODE_DDMA (0 << 31) #define HDMI_ADMA_MODE_NDMA (1 << 31) #define HDMI_AUD_FMT 0x048 #define AUD_FMT_CH(n) ((n) - 1) #define HDMI_PCM_CTRL 0x04c #define HDMI_AUD_CTS 0x050 #define HDMI_AUD_N 0x054 #define HDMI_AUD_CH_STATUS0 0x058 #define CH_STATUS0_FS_FREQ (0xf << 24) #define CH_STATUS0_FS_FREQ_48 (2 << 24) #define HDMI_AUD_CH_STATUS1 0x05c #define CH_STATUS1_WORD_LEN (0x7 << 1) #define CH_STATUS1_WORD_LEN_16 (1 << 1) #define HDMI_AUDIO_RESET_RETRY 1000 #define HDMI_AUDIO_CHANNELS 2 #define HDMI_AUDIO_CHANNELMAP 0x76543210 #define HDMI_AUDIO_N 6144 /* 48 kHz */ #define HDMI_AUDIO_CTS(r, n) ((((r) * 10) * ((n) / 128)) / 480) #define HDMI_PADCTRL0 0x200 #define PADCTRL0_BIASEN (1 << 31) #define PADCTRL0_LDOCEN (1 << 30) #define PADCTRL0_LDODEN (1 << 29) #define PADCTRL0_PWENC (1 << 28) #define PADCTRL0_PWEND (1 << 27) #define PADCTRL0_PWENG (1 << 26) #define PADCTRL0_CKEN (1 << 25) #define PADCTRL0_SEN (1 << 24) #define PADCTRL0_TXEN (1 << 23) #define HDMI_PADCTRL1 0x204 #define PADCTRL1_AMP_OPT (1 << 23) #define PADCTRL1_AMPCK_OPT (1 << 22) #define PADCTRL1_DMP_OPT (1 << 21) #define PADCTRL1_EMP_OPT (1 << 20) #define PADCTRL1_EMPCK_OPT (1 << 19) #define PADCTRL1_PWSCK (1 << 18) #define PADCTRL1_PWSDT (1 << 17) #define PADCTRL1_REG_CSMPS (1 << 16) #define PADCTRL1_REG_DEN (1 << 15) #define PADCTRL1_REG_DENCK (1 << 14) #define PADCTRL1_REG_PLRCK (1 << 13) #define PADCTRL1_REG_EMP (0x7 << 10) #define PADCTRL1_REG_EMP_EN (0x2 << 10) #define PADCTRL1_REG_CD (0x3 << 8) #define PADCTRL1_REG_CKSS (0x3 << 6) #define PADCTRL1_REG_CKSS_1X (0x1 << 6) #define PADCTRL1_REG_CKSS_2X (0x0 << 6) #define PADCTRL1_REG_AMP (0x7 << 3) #define PADCTRL1_REG_AMP_EN (0x6 << 3) #define PADCTRL1_REG_PLR (0x7 << 0) #define HDMI_PLLCTRL0 0x208 #define PLLCTRL0_PLL_EN (1 << 31) #define PLLCTRL0_BWS (1 << 30) #define PLLCTRL0_HV_IS_33 (1 << 29) #define PLLCTRL0_LDO1_EN (1 << 28) #define PLLCTRL0_LDO2_EN (1 << 27) #define PLLCTRL0_SDIV2 (1 << 25) #define PLLCTRL0_VCO_GAIN (0x1 << 22) #define PLLCTRL0_S (0x7 << 17) #define PLLCTRL0_CP_S (0xf << 12) #define PLLCTRL0_CS (0x7 << 8) #define PLLCTRL0_PREDIV(x) ((x) << 4) #define PLLCTRL0_VCO_S (0x8 << 0) #define HDMI_PLLDBG0 0x20c #define PLLDBG0_CKIN_SEL (1 << 21) #define PLLDBG0_CKIN_SEL_PLL3 (0 << 21) #define PLLDBG0_CKIN_SEL_PLL7 (1 << 21) #define HDMI_PKTCTRL0 0x2f0 #define HDMI_PKTCTRL1 0x2f4 #define PKTCTRL_PACKET(n,t) ((t) << ((n) << 2)) #define PKT_NULL 0 #define PKT_GC 1 #define PKT_AVI 2 #define PKT_AI 3 #define PKT_SPD 5 #define PKT_END 15 #define DDC_CTRL 0x500 #define CTRL_DDC_EN (1 << 31) #define CTRL_DDC_ACMD_START (1 << 30) #define CTRL_DDC_FIFO_DIR (1 << 8) #define CTRL_DDC_FIFO_DIR_READ (0 << 8) #define CTRL_DDC_FIFO_DIR_WRITE (1 << 8) #define CTRL_DDC_SWRST (1 << 0) #define DDC_SLAVE_ADDR 0x504 #define SLAVE_ADDR_SEG_SHIFT 24 #define SLAVE_ADDR_EDDC_SHIFT 16 #define SLAVE_ADDR_OFFSET_SHIFT 8 #define SLAVE_ADDR_SHIFT 0 #define DDC_INT_STATUS 0x50c #define INT_STATUS_XFER_DONE (1 << 0) #define DDC_FIFO_CTRL 0x510 #define FIFO_CTRL_CLEAR (1 << 31) #define DDC_BYTE_COUNTER 0x51c #define DDC_COMMAND 0x520 #define COMMAND_EOREAD (4 << 0) #define DDC_CLOCK 0x528 #define DDC_CLOCK_M (1 << 3) #define DDC_CLOCK_N (5 << 0) #define DDC_FIFO 0x518 #define SWRST_DELAY 1000 #define DDC_DELAY 1000 #define DDC_RETRY 1000 #define DDC_BLKLEN 16 #define DDC_ADDR 0x50 #define EDDC_ADDR 0x60 #define EDID_LENGTH 128 #define HDMI_ENABLE_DELAY 50000 #define DDC_READ_RETRY 4 #define EXT_TAG 0x00 #define CEA_TAG_ID 0x02 #define CEA_DTD 0x03 #define DTD_BASIC_AUDIO (1 << 6) #define CEA_REV 0x02 #define CEA_DATA_OFF 0x03 #define CEA_DATA_START 4 #define BLOCK_TAG(x) (((x) >> 5) & 0x7) #define BLOCK_TAG_VSDB 3 #define BLOCK_LEN(x) ((x) & 0x1f) #define HDMI_VSDB_MINLEN 5 #define HDMI_OUI "\x03\x0c\x00" #define HDMI_OUI_LEN 3 +#define HDMI_DEFAULT_FREQ 297000000 struct a10hdmi_softc { struct resource *res; struct intr_config_hook mode_hook; uint8_t edid[EDID_LENGTH]; int has_hdmi; int has_audio; + + clk_t clk_ahb; + clk_t clk_hdmi; + clk_t clk_lcd; }; static struct resource_spec a10hdmi_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { -1, 0 } }; #define HDMI_READ(sc, reg) bus_read_4((sc)->res, (reg)) #define HDMI_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) static void a10hdmi_init(struct a10hdmi_softc *sc) { /* Enable the HDMI module */ HDMI_WRITE(sc, HDMI_CTRL, CTRL_MODULE_EN); /* Configure PLL/DRV settings */ HDMI_WRITE(sc, HDMI_PADCTRL0, PADCTRL0_BIASEN | PADCTRL0_LDOCEN | PADCTRL0_LDODEN | PADCTRL0_PWENC | PADCTRL0_PWEND | PADCTRL0_PWENG | PADCTRL0_CKEN | PADCTRL0_TXEN); HDMI_WRITE(sc, HDMI_PADCTRL1, PADCTRL1_AMP_OPT | PADCTRL1_AMPCK_OPT | PADCTRL1_EMP_OPT | PADCTRL1_EMPCK_OPT | PADCTRL1_REG_DEN | PADCTRL1_REG_DENCK | PADCTRL1_REG_EMP_EN | PADCTRL1_REG_AMP_EN); /* Select PLL3 as input clock */ HDMI_WRITE(sc, HDMI_PLLDBG0, PLLDBG0_CKIN_SEL_PLL3); DELAY(HDMI_ENABLE_DELAY); } static void a10hdmi_hpd(void *arg) { struct a10hdmi_softc *sc; device_t dev; uint32_t hpd; dev = arg; sc = device_get_softc(dev); hpd = HDMI_READ(sc, HDMI_HPD); if ((hpd & HPD_DET) == HPD_DET) EVENTHANDLER_INVOKE(hdmi_event, dev, HDMI_EVENT_CONNECTED); config_intrhook_disestablish(&sc->mode_hook); } static int a10hdmi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "allwinner,sun7i-a20-hdmi")) return (ENXIO); device_set_desc(dev, "Allwinner HDMI TX"); return (BUS_PROBE_DEFAULT); } static int a10hdmi_attach(device_t dev) { struct a10hdmi_softc *sc; int error; sc = device_get_softc(dev); if (bus_alloc_resources(dev, a10hdmi_spec, &sc->res)) { device_printf(dev, "cannot allocate resources for device\n"); return (ENXIO); } - a10_clk_hdmi_activate(); + /* Setup clocks */ + error = clk_get_by_ofw_name(dev, "ahb", &sc->clk_ahb); + if (error != 0) { + device_printf(dev, "cannot find ahb clock\n"); + return (error); + } + error = clk_get_by_ofw_name(dev, "hdmi", &sc->clk_hdmi); + if (error != 0) { + device_printf(dev, "cannot find hdmi clock\n"); + return (error); + } + error = clk_get_by_ofw_name(dev, "lcd", &sc->clk_lcd); + if (error != 0) { + device_printf(dev, "cannot find lcd clock\n"); + } + /* Enable HDMI clock */ + error = clk_enable(sc->clk_hdmi); + if (error != 0) { + device_printf(dev, "cannot enable hdmi clock\n"); + return (error); + } + /* Gating AHB clock for HDMI */ + error = clk_enable(sc->clk_ahb); + if (error != 0) { + device_printf(dev, "cannot enable ahb gate\n"); + return (error); + } a10hdmi_init(sc); sc->mode_hook.ich_func = a10hdmi_hpd; sc->mode_hook.ich_arg = dev; error = config_intrhook_establish(&sc->mode_hook); if (error != 0) return (error); return (0); } static int a10hdmi_ddc_xfer(struct a10hdmi_softc *sc, uint16_t addr, uint8_t seg, uint8_t off, int len) { uint32_t val; int retry; /* Set FIFO direction to read */ val = HDMI_READ(sc, DDC_CTRL); val &= ~CTRL_DDC_FIFO_DIR; val |= CTRL_DDC_FIFO_DIR_READ; HDMI_WRITE(sc, DDC_CTRL, val); /* Setup DDC slave address */ val = (addr << SLAVE_ADDR_SHIFT) | (seg << SLAVE_ADDR_SEG_SHIFT) | (EDDC_ADDR << SLAVE_ADDR_EDDC_SHIFT) | (off << SLAVE_ADDR_OFFSET_SHIFT); HDMI_WRITE(sc, DDC_SLAVE_ADDR, val); /* Clear FIFO */ val = HDMI_READ(sc, DDC_FIFO_CTRL); val |= FIFO_CTRL_CLEAR; HDMI_WRITE(sc, DDC_FIFO_CTRL, val); /* Set transfer length */ HDMI_WRITE(sc, DDC_BYTE_COUNTER, len); /* Set command to "Explicit Offset Address Read" */ HDMI_WRITE(sc, DDC_COMMAND, COMMAND_EOREAD); /* Start transfer */ val = HDMI_READ(sc, DDC_CTRL); val |= CTRL_DDC_ACMD_START; HDMI_WRITE(sc, DDC_CTRL, val); /* Wait for command to start */ retry = DDC_RETRY; while (--retry > 0) { val = HDMI_READ(sc, DDC_CTRL); if ((val & CTRL_DDC_ACMD_START) == 0) break; DELAY(DDC_DELAY); } if (retry == 0) return (ETIMEDOUT); /* Ensure that the transfer completed */ val = HDMI_READ(sc, DDC_INT_STATUS); if ((val & INT_STATUS_XFER_DONE) == 0) return (EIO); return (0); } static int a10hdmi_ddc_read(struct a10hdmi_softc *sc, int block, uint8_t *edid) { int resid, off, len, error; uint8_t *pbuf; pbuf = edid; resid = EDID_LENGTH; off = (block & 1) ? EDID_LENGTH : 0; while (resid > 0) { len = min(resid, DDC_BLKLEN); error = a10hdmi_ddc_xfer(sc, DDC_ADDR, block >> 1, off, len); if (error != 0) return (error); bus_read_multi_1(sc->res, DDC_FIFO, pbuf, len); pbuf += len; off += len; resid -= len; } return (0); } static int a10hdmi_detect_hdmi_vsdb(uint8_t *edid) { int off, p, btag, blen; if (edid[EXT_TAG] != CEA_TAG_ID) return (0); off = edid[CEA_DATA_OFF]; /* CEA data block collection starts at byte 4 */ if (off <= CEA_DATA_START) return (0); /* Parse the CEA data blocks */ for (p = CEA_DATA_START; p < off;) { btag = BLOCK_TAG(edid[p]); blen = BLOCK_LEN(edid[p]); /* Make sure the length is sane */ if (p + blen + 1 > off) break; /* Look for a VSDB with the HDMI 24-bit IEEE registration ID */ if (btag == BLOCK_TAG_VSDB && blen >= HDMI_VSDB_MINLEN && memcmp(&edid[p + 1], HDMI_OUI, HDMI_OUI_LEN) == 0) return (1); /* Next data block */ p += (1 + blen); } return (0); } static void a10hdmi_detect_hdmi(struct a10hdmi_softc *sc, int *phdmi, int *paudio) { struct edid_info ei; uint8_t edid[EDID_LENGTH]; int block; *phdmi = *paudio = 0; if (edid_parse(sc->edid, &ei) != 0) return; /* Scan through extension blocks, looking for a CEA-861 block. */ for (block = 1; block <= ei.edid_ext_block_count; block++) { if (a10hdmi_ddc_read(sc, block, edid) != 0) return; if (a10hdmi_detect_hdmi_vsdb(edid) != 0) { *phdmi = 1; *paudio = ((edid[CEA_DTD] & DTD_BASIC_AUDIO) != 0); return; } } } static int a10hdmi_get_edid(device_t dev, uint8_t **edid, uint32_t *edid_len) { struct a10hdmi_softc *sc; int error, retry; sc = device_get_softc(dev); retry = DDC_READ_RETRY; while (--retry > 0) { /* I2C software reset */ HDMI_WRITE(sc, DDC_FIFO_CTRL, 0); HDMI_WRITE(sc, DDC_CTRL, CTRL_DDC_EN | CTRL_DDC_SWRST); DELAY(SWRST_DELAY); if (HDMI_READ(sc, DDC_CTRL) & CTRL_DDC_SWRST) { device_printf(dev, "DDC software reset failed\n"); return (ENXIO); } /* Configure DDC clock */ HDMI_WRITE(sc, DDC_CLOCK, DDC_CLOCK_M | DDC_CLOCK_N); /* Read EDID block */ error = a10hdmi_ddc_read(sc, 0, sc->edid); if (error == 0) { *edid = sc->edid; *edid_len = sizeof(sc->edid); break; } } if (error == 0) a10hdmi_detect_hdmi(sc, &sc->has_hdmi, &sc->has_audio); else sc->has_hdmi = sc->has_audio = 0; return (error); } static void a10hdmi_set_audiomode(device_t dev, const struct videomode *mode) { struct a10hdmi_softc *sc; uint32_t val; int retry; sc = device_get_softc(dev); /* Disable and reset audio module and wait for reset bit to clear */ HDMI_WRITE(sc, HDMI_AUD_CTRL, AUD_CTRL_RST); for (retry = HDMI_AUDIO_RESET_RETRY; retry > 0; retry--) { val = HDMI_READ(sc, HDMI_AUD_CTRL); if ((val & AUD_CTRL_RST) == 0) break; } if (retry == 0) { device_printf(dev, "timeout waiting for audio module\n"); return; } if (!sc->has_audio) return; /* DMA and FIFO control */ HDMI_WRITE(sc, HDMI_ADMA_CTRL, HDMI_ADMA_MODE_DDMA); /* Audio format control (LPCM, S16LE, stereo) */ HDMI_WRITE(sc, HDMI_AUD_FMT, AUD_FMT_CH(HDMI_AUDIO_CHANNELS)); /* Channel mappings */ HDMI_WRITE(sc, HDMI_PCM_CTRL, HDMI_AUDIO_CHANNELMAP); /* Clocks */ HDMI_WRITE(sc, HDMI_AUD_CTS, HDMI_AUDIO_CTS(mode->dot_clock, HDMI_AUDIO_N)); HDMI_WRITE(sc, HDMI_AUD_N, HDMI_AUDIO_N); /* Set sampling frequency to 48 kHz, word length to 16-bit */ HDMI_WRITE(sc, HDMI_AUD_CH_STATUS0, CH_STATUS0_FS_FREQ_48); HDMI_WRITE(sc, HDMI_AUD_CH_STATUS1, CH_STATUS1_WORD_LEN_16); /* Enable */ HDMI_WRITE(sc, HDMI_AUD_CTRL, AUD_CTRL_EN); } static int +a10hdmi_get_tcon_config(struct a10hdmi_softc *sc, int *div, int *dbl) +{ + uint64_t lcd_fin, lcd_fout; + clk_t clk_lcd_parent; + const char *pname; + int error; + + error = clk_get_parent(sc->clk_lcd, &clk_lcd_parent); + if (error != 0) + return (error); + + /* Get the LCD CH1 special clock 2 divider */ + error = clk_get_freq(sc->clk_lcd, &lcd_fout); + if (error != 0) + return (error); + error = clk_get_freq(clk_lcd_parent, &lcd_fin); + if (error != 0) + return (error); + *div = lcd_fin / lcd_fout; + + /* Detect LCD CH1 special clock using a 1X or 2X source */ + /* XXX */ + pname = clk_get_name(clk_lcd_parent); + if (strcmp(pname, "pll3-1x") == 0 || strcmp(pname, "pll7-1x") == 0) + *dbl = 0; + else + *dbl = 1; + + return (0); +} + +static int a10hdmi_set_videomode(device_t dev, const struct videomode *mode) { struct a10hdmi_softc *sc; int error, clk_div, clk_dbl; int dblscan, hfp, hspw, hbp, vfp, vspw, vbp; uint32_t val; sc = device_get_softc(dev); dblscan = !!(mode->flags & VID_DBLSCAN); hfp = mode->hsync_start - mode->hdisplay; hspw = mode->hsync_end - mode->hsync_start; hbp = mode->htotal - mode->hsync_start; vfp = mode->vsync_start - mode->vdisplay; vspw = mode->vsync_end - mode->vsync_start; vbp = mode->vtotal - mode->vsync_start; - error = a10_clk_tcon_get_config(&clk_div, &clk_dbl); - if (error != 0) + error = a10hdmi_get_tcon_config(sc, &clk_div, &clk_dbl); + if (error != 0) { + device_printf(dev, "couldn't get tcon config: %d\n", error); return (error); + } /* Clear interrupt status */ HDMI_WRITE(sc, HDMI_INT_STATUS, HDMI_READ(sc, HDMI_INT_STATUS)); /* Clock setup */ val = HDMI_READ(sc, HDMI_PADCTRL1); val &= ~PADCTRL1_REG_CKSS; val |= (clk_dbl ? PADCTRL1_REG_CKSS_2X : PADCTRL1_REG_CKSS_1X); HDMI_WRITE(sc, HDMI_PADCTRL1, val); HDMI_WRITE(sc, HDMI_PLLCTRL0, PLLCTRL0_PLL_EN | PLLCTRL0_BWS | PLLCTRL0_HV_IS_33 | PLLCTRL0_LDO1_EN | PLLCTRL0_LDO2_EN | PLLCTRL0_SDIV2 | PLLCTRL0_VCO_GAIN | PLLCTRL0_S | PLLCTRL0_CP_S | PLLCTRL0_CS | PLLCTRL0_PREDIV(clk_div) | PLLCTRL0_VCO_S); /* Setup display settings */ if (bootverbose) device_printf(dev, "HDMI: %s, Audio: %s\n", sc->has_hdmi ? "yes" : "no", sc->has_audio ? "yes" : "no"); val = 0; if (sc->has_hdmi) val |= VID_CTRL_HDMI_MODE; if (mode->flags & VID_INTERLACE) val |= VID_CTRL_INTERLACE; if (mode->flags & VID_DBLSCAN) val |= VID_CTRL_REPEATER_2X; HDMI_WRITE(sc, HDMI_VID_CTRL, val); /* Setup display timings */ HDMI_WRITE(sc, HDMI_VID_TIMING0, VID_ACT_V(mode->vdisplay) | VID_ACT_H(mode->hdisplay << dblscan)); HDMI_WRITE(sc, HDMI_VID_TIMING1, VID_VBP(vbp) | VID_HBP(hbp << dblscan)); HDMI_WRITE(sc, HDMI_VID_TIMING2, VID_VFP(vfp) | VID_HFP(hfp << dblscan)); HDMI_WRITE(sc, HDMI_VID_TIMING3, VID_VSPW(vspw) | VID_HSPW(hspw << dblscan)); val = TX_CLOCK_NORMAL; if (mode->flags & VID_PVSYNC) val |= VID_VSYNC_ACTSEL; if (mode->flags & VID_PHSYNC) val |= VID_HSYNC_ACTSEL; HDMI_WRITE(sc, HDMI_VID_TIMING4, val); /* This is an ordered list of infoframe packets that the HDMI * transmitter will send. Transmit packets in the following order: * 1. General control packet * 2. AVI infoframe * 3. Audio infoframe * There are 2 registers with 4 slots each. The list is terminated * with the special PKT_END marker. */ HDMI_WRITE(sc, HDMI_PKTCTRL0, PKTCTRL_PACKET(0, PKT_GC) | PKTCTRL_PACKET(1, PKT_AVI) | PKTCTRL_PACKET(2, PKT_AI) | PKTCTRL_PACKET(3, PKT_END)); HDMI_WRITE(sc, HDMI_PKTCTRL1, 0); /* Setup audio */ a10hdmi_set_audiomode(dev, mode); return (0); } static int a10hdmi_enable(device_t dev, int onoff) { struct a10hdmi_softc *sc; uint32_t val; sc = device_get_softc(dev); /* Enable or disable video output */ val = HDMI_READ(sc, HDMI_VID_CTRL); if (onoff) val |= VID_CTRL_VIDEO_EN; else val &= ~VID_CTRL_VIDEO_EN; HDMI_WRITE(sc, HDMI_VID_CTRL, val); return (0); } static device_method_t a10hdmi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, a10hdmi_probe), DEVMETHOD(device_attach, a10hdmi_attach), /* HDMI interface */ DEVMETHOD(hdmi_get_edid, a10hdmi_get_edid), DEVMETHOD(hdmi_set_videomode, a10hdmi_set_videomode), DEVMETHOD(hdmi_enable, a10hdmi_enable), DEVMETHOD_END }; static driver_t a10hdmi_driver = { "a10hdmi", a10hdmi_methods, sizeof(struct a10hdmi_softc), }; static devclass_t a10hdmi_devclass; DRIVER_MODULE(a10hdmi, simplebus, a10hdmi_driver, a10hdmi_devclass, 0, 0); MODULE_VERSION(a10hdmi, 1); Index: head/sys/arm/allwinner/a10_mmc.c =================================================================== --- head/sys/arm/allwinner/a10_mmc.c (revision 297626) +++ head/sys/arm/allwinner/a10_mmc.c (revision 297627) @@ -1,946 +1,951 @@ /*- * Copyright (c) 2013 Alexander Fedorov * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include -#include #include -#include +#include +#include #define A10_MMC_MEMRES 0 #define A10_MMC_IRQRES 1 #define A10_MMC_RESSZ 2 #define A10_MMC_DMA_SEGS 16 #define A10_MMC_DMA_MAX_SIZE 0x2000 #define A10_MMC_DMA_FTRGLEVEL 0x20070008 +#define CARD_ID_FREQUENCY 400000 + static int a10_mmc_pio_mode = 0; TUNABLE_INT("hw.a10.mmc.pio_mode", &a10_mmc_pio_mode); static struct ofw_compat_data compat_data[] = { {"allwinner,sun4i-a10-mmc", 1}, {"allwinner,sun5i-a13-mmc", 1}, {NULL, 0} }; struct a10_mmc_softc { bus_space_handle_t a10_bsh; bus_space_tag_t a10_bst; device_t a10_dev; + clk_t a10_clk_ahb; + clk_t a10_clk_mmc; + hwreset_t a10_rst_ahb; int a10_bus_busy; int a10_id; int a10_resid; int a10_timeout; struct callout a10_timeoutc; struct mmc_host a10_host; struct mmc_request * a10_req; struct mtx a10_mtx; struct resource * a10_res[A10_MMC_RESSZ]; uint32_t a10_intr; uint32_t a10_intr_wait; void * a10_intrhand; bus_size_t a10_fifo_reg; /* Fields required for DMA access. */ bus_addr_t a10_dma_desc_phys; bus_dmamap_t a10_dma_map; bus_dma_tag_t a10_dma_tag; void * a10_dma_desc; bus_dmamap_t a10_dma_buf_map; bus_dma_tag_t a10_dma_buf_tag; int a10_dma_inuse; int a10_dma_map_err; }; static struct resource_spec a10_mmc_res_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, { -1, 0, 0 } }; static int a10_mmc_probe(device_t); static int a10_mmc_attach(device_t); static int a10_mmc_detach(device_t); static int a10_mmc_setup_dma(struct a10_mmc_softc *); static int a10_mmc_reset(struct a10_mmc_softc *); static void a10_mmc_intr(void *); static int a10_mmc_update_clock(struct a10_mmc_softc *); static int a10_mmc_update_ios(device_t, device_t); static int a10_mmc_request(device_t, device_t, struct mmc_request *); static int a10_mmc_get_ro(device_t, device_t); static int a10_mmc_acquire_host(device_t, device_t); static int a10_mmc_release_host(device_t, device_t); #define A10_MMC_LOCK(_sc) mtx_lock(&(_sc)->a10_mtx) #define A10_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->a10_mtx) #define A10_MMC_READ_4(_sc, _reg) \ bus_space_read_4((_sc)->a10_bst, (_sc)->a10_bsh, _reg) #define A10_MMC_WRITE_4(_sc, _reg, _value) \ bus_space_write_4((_sc)->a10_bst, (_sc)->a10_bsh, _reg, _value) static int a10_mmc_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Allwinner Integrated MMC/SD controller"); return (BUS_PROBE_DEFAULT); } static int a10_mmc_attach(device_t dev) { device_t child; struct a10_mmc_softc *sc; struct sysctl_ctx_list *ctx; struct sysctl_oid_list *tree; - int clk; + int error; sc = device_get_softc(dev); sc->a10_dev = dev; sc->a10_req = NULL; sc->a10_id = device_get_unit(dev); if (sc->a10_id > 3) { device_printf(dev, "only 4 hosts are supported (0-3)\n"); return (ENXIO); } if (bus_alloc_resources(dev, a10_mmc_res_spec, sc->a10_res) != 0) { device_printf(dev, "cannot allocate device resources\n"); return (ENXIO); } sc->a10_bst = rman_get_bustag(sc->a10_res[A10_MMC_MEMRES]); sc->a10_bsh = rman_get_bushandle(sc->a10_res[A10_MMC_MEMRES]); if (bus_setup_intr(dev, sc->a10_res[A10_MMC_IRQRES], INTR_TYPE_MISC | INTR_MPSAFE, NULL, a10_mmc_intr, sc, &sc->a10_intrhand)) { bus_release_resources(dev, a10_mmc_res_spec, sc->a10_res); device_printf(dev, "cannot setup interrupt handler\n"); return (ENXIO); } + mtx_init(&sc->a10_mtx, device_get_nameunit(sc->a10_dev), "a10_mmc", + MTX_DEF); + callout_init_mtx(&sc->a10_timeoutc, &sc->a10_mtx, 0); /* * Later chips use a different FIFO offset. Unfortunately the FDT * uses the same compatible string for old and new implementations. */ switch (allwinner_soc_family()) { case ALLWINNERSOC_SUN4I: case ALLWINNERSOC_SUN5I: case ALLWINNERSOC_SUN7I: sc->a10_fifo_reg = A10_MMC_FIFO; break; default: sc->a10_fifo_reg = A31_MMC_FIFO; break; } + /* De-assert reset */ + if (hwreset_get_by_ofw_name(dev, "ahb", &sc->a10_rst_ahb) == 0) { + error = hwreset_deassert(sc->a10_rst_ahb); + if (error != 0) { + device_printf(dev, "cannot de-assert reset\n"); + return (error); + } + } + /* Activate the module clock. */ - switch (allwinner_soc_type()) { -#if defined(SOC_ALLWINNER_A10) || defined(SOC_ALLWINNER_A20) - case ALLWINNERSOC_A10: - case ALLWINNERSOC_A10S: - case ALLWINNERSOC_A20: - clk = a10_clk_mmc_activate(sc->a10_id); - break; -#endif -#if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S) - case ALLWINNERSOC_A31: - case ALLWINNERSOC_A31S: - clk = a31_clk_mmc_activate(sc->a10_id); - break; -#endif - default: - clk = -1; + error = clk_get_by_ofw_name(dev, "ahb", &sc->a10_clk_ahb); + if (error != 0) { + device_printf(dev, "cannot get ahb clock\n"); + goto fail; } - if (clk != 0) { - bus_teardown_intr(dev, sc->a10_res[A10_MMC_IRQRES], - sc->a10_intrhand); - bus_release_resources(dev, a10_mmc_res_spec, sc->a10_res); - device_printf(dev, "cannot activate mmc clock\n"); - return (ENXIO); + error = clk_enable(sc->a10_clk_ahb); + if (error != 0) { + device_printf(dev, "cannot enable ahb clock\n"); + goto fail; } + error = clk_get_by_ofw_name(dev, "mmc", &sc->a10_clk_mmc); + if (error != 0) { + device_printf(dev, "cannot get mmc clock\n"); + goto fail; + } + error = clk_set_freq(sc->a10_clk_mmc, CARD_ID_FREQUENCY, + CLK_SET_ROUND_DOWN); + if (error != 0) { + device_printf(dev, "cannot init mmc clock\n"); + goto fail; + } + error = clk_enable(sc->a10_clk_mmc); + if (error != 0) { + device_printf(dev, "cannot enable mmc clock\n"); + goto fail; + } sc->a10_timeout = 10; ctx = device_get_sysctl_ctx(dev); tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW, &sc->a10_timeout, 0, "Request timeout in seconds"); - mtx_init(&sc->a10_mtx, device_get_nameunit(sc->a10_dev), "a10_mmc", - MTX_DEF); - callout_init_mtx(&sc->a10_timeoutc, &sc->a10_mtx, 0); /* Reset controller. */ if (a10_mmc_reset(sc) != 0) { device_printf(dev, "cannot reset the controller\n"); goto fail; } if (a10_mmc_pio_mode == 0 && a10_mmc_setup_dma(sc) != 0) { device_printf(sc->a10_dev, "Couldn't setup DMA!\n"); a10_mmc_pio_mode = 1; } if (bootverbose) device_printf(sc->a10_dev, "DMA status: %s\n", a10_mmc_pio_mode ? "disabled" : "enabled"); sc->a10_host.f_min = 400000; sc->a10_host.f_max = 52000000; sc->a10_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; sc->a10_host.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_HSPEED; sc->a10_host.mode = mode_sd; child = device_add_child(dev, "mmc", -1); if (child == NULL) { device_printf(dev, "attaching MMC bus failed!\n"); goto fail; } if (device_probe_and_attach(child) != 0) { device_printf(dev, "attaching MMC child failed!\n"); device_delete_child(dev, child); goto fail; } return (0); fail: callout_drain(&sc->a10_timeoutc); mtx_destroy(&sc->a10_mtx); bus_teardown_intr(dev, sc->a10_res[A10_MMC_IRQRES], sc->a10_intrhand); bus_release_resources(dev, a10_mmc_res_spec, sc->a10_res); return (ENXIO); } static int a10_mmc_detach(device_t dev) { return (EBUSY); } static void a10_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) { struct a10_mmc_softc *sc; sc = (struct a10_mmc_softc *)arg; if (err) { sc->a10_dma_map_err = err; return; } sc->a10_dma_desc_phys = segs[0].ds_addr; } static int a10_mmc_setup_dma(struct a10_mmc_softc *sc) { int dma_desc_size, error; /* Allocate the DMA descriptor memory. */ dma_desc_size = sizeof(struct a10_mmc_dma_desc) * A10_MMC_DMA_SEGS; error = bus_dma_tag_create(bus_get_dma_tag(sc->a10_dev), 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, dma_desc_size, 1, dma_desc_size, 0, NULL, NULL, &sc->a10_dma_tag); if (error) return (error); error = bus_dmamem_alloc(sc->a10_dma_tag, &sc->a10_dma_desc, BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->a10_dma_map); if (error) return (error); error = bus_dmamap_load(sc->a10_dma_tag, sc->a10_dma_map, sc->a10_dma_desc, dma_desc_size, a10_dma_desc_cb, sc, 0); if (error) return (error); if (sc->a10_dma_map_err) return (sc->a10_dma_map_err); /* Create the DMA map for data transfers. */ error = bus_dma_tag_create(bus_get_dma_tag(sc->a10_dev), 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, A10_MMC_DMA_MAX_SIZE * A10_MMC_DMA_SEGS, A10_MMC_DMA_SEGS, A10_MMC_DMA_MAX_SIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->a10_dma_buf_tag); if (error) return (error); error = bus_dmamap_create(sc->a10_dma_buf_tag, 0, &sc->a10_dma_buf_map); if (error) return (error); return (0); } static void a10_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) { int i; struct a10_mmc_dma_desc *dma_desc; struct a10_mmc_softc *sc; sc = (struct a10_mmc_softc *)arg; sc->a10_dma_map_err = err; dma_desc = sc->a10_dma_desc; /* Note nsegs is guaranteed to be zero if err is non-zero. */ for (i = 0; i < nsegs; i++) { dma_desc[i].buf_size = segs[i].ds_len; dma_desc[i].buf_addr = segs[i].ds_addr; dma_desc[i].config = A10_MMC_DMA_CONFIG_CH | A10_MMC_DMA_CONFIG_OWN; if (i == 0) dma_desc[i].config |= A10_MMC_DMA_CONFIG_FD; if (i < (nsegs - 1)) { dma_desc[i].config |= A10_MMC_DMA_CONFIG_DIC; dma_desc[i].next = sc->a10_dma_desc_phys + ((i + 1) * sizeof(struct a10_mmc_dma_desc)); } else { dma_desc[i].config |= A10_MMC_DMA_CONFIG_LD | A10_MMC_DMA_CONFIG_ER; dma_desc[i].next = 0; } } } static int a10_mmc_prepare_dma(struct a10_mmc_softc *sc) { bus_dmasync_op_t sync_op; int error; struct mmc_command *cmd; uint32_t val; cmd = sc->a10_req->cmd; if (cmd->data->len > A10_MMC_DMA_MAX_SIZE * A10_MMC_DMA_SEGS) return (EFBIG); error = bus_dmamap_load(sc->a10_dma_buf_tag, sc->a10_dma_buf_map, cmd->data->data, cmd->data->len, a10_dma_cb, sc, BUS_DMA_NOWAIT); if (error) return (error); if (sc->a10_dma_map_err) return (sc->a10_dma_map_err); sc->a10_dma_inuse = 1; if (cmd->data->flags & MMC_DATA_WRITE) sync_op = BUS_DMASYNC_PREWRITE; else sync_op = BUS_DMASYNC_PREREAD; bus_dmamap_sync(sc->a10_dma_buf_tag, sc->a10_dma_buf_map, sync_op); bus_dmamap_sync(sc->a10_dma_tag, sc->a10_dma_map, BUS_DMASYNC_PREWRITE); val = A10_MMC_READ_4(sc, A10_MMC_IMASK); val &= ~(A10_MMC_RX_DATA_REQ | A10_MMC_TX_DATA_REQ); A10_MMC_WRITE_4(sc, A10_MMC_IMASK, val); val = A10_MMC_READ_4(sc, A10_MMC_GCTRL); val &= ~A10_MMC_ACCESS_BY_AHB; val |= A10_MMC_DMA_ENABLE; A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, val); val |= A10_MMC_DMA_RESET; A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, val); A10_MMC_WRITE_4(sc, A10_MMC_DMAC, A10_MMC_IDMAC_SOFT_RST); A10_MMC_WRITE_4(sc, A10_MMC_DMAC, A10_MMC_IDMAC_IDMA_ON | A10_MMC_IDMAC_FIX_BURST); val = A10_MMC_READ_4(sc, A10_MMC_IDIE); val &= ~(A10_MMC_IDMAC_RECEIVE_INT | A10_MMC_IDMAC_TRANSMIT_INT); if (cmd->data->flags & MMC_DATA_WRITE) val |= A10_MMC_IDMAC_TRANSMIT_INT; else val |= A10_MMC_IDMAC_RECEIVE_INT; A10_MMC_WRITE_4(sc, A10_MMC_IDIE, val); A10_MMC_WRITE_4(sc, A10_MMC_DLBA, sc->a10_dma_desc_phys); A10_MMC_WRITE_4(sc, A10_MMC_FTRGL, A10_MMC_DMA_FTRGLEVEL); return (0); } static int a10_mmc_reset(struct a10_mmc_softc *sc) { int timeout; A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, A10_MMC_READ_4(sc, A10_MMC_GCTRL) | A10_MMC_RESET); timeout = 1000; while (--timeout > 0) { if ((A10_MMC_READ_4(sc, A10_MMC_GCTRL) & A10_MMC_RESET) == 0) break; DELAY(100); } if (timeout == 0) return (ETIMEDOUT); /* Set the timeout. */ A10_MMC_WRITE_4(sc, A10_MMC_TIMEOUT, 0xffffffff); /* Clear pending interrupts. */ A10_MMC_WRITE_4(sc, A10_MMC_RINTR, 0xffffffff); A10_MMC_WRITE_4(sc, A10_MMC_IDST, 0xffffffff); /* Unmask interrupts. */ A10_MMC_WRITE_4(sc, A10_MMC_IMASK, A10_MMC_CMD_DONE | A10_MMC_INT_ERR_BIT | A10_MMC_DATA_OVER | A10_MMC_AUTOCMD_DONE); /* Enable interrupts and AHB access. */ A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, A10_MMC_READ_4(sc, A10_MMC_GCTRL) | A10_MMC_INT_ENABLE); return (0); } static void a10_mmc_req_done(struct a10_mmc_softc *sc) { struct mmc_command *cmd; struct mmc_request *req; cmd = sc->a10_req->cmd; if (cmd->error != MMC_ERR_NONE) { /* Reset the controller. */ a10_mmc_reset(sc); a10_mmc_update_clock(sc); } if (sc->a10_dma_inuse == 0) { /* Reset the FIFO. */ A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, A10_MMC_READ_4(sc, A10_MMC_GCTRL) | A10_MMC_FIFO_RESET); } req = sc->a10_req; callout_stop(&sc->a10_timeoutc); sc->a10_req = NULL; sc->a10_intr = 0; sc->a10_resid = 0; sc->a10_dma_inuse = 0; sc->a10_dma_map_err = 0; sc->a10_intr_wait = 0; req->done(req); } static void a10_mmc_req_ok(struct a10_mmc_softc *sc) { int timeout; struct mmc_command *cmd; uint32_t status; timeout = 1000; while (--timeout > 0) { status = A10_MMC_READ_4(sc, A10_MMC_STAS); if ((status & A10_MMC_CARD_DATA_BUSY) == 0) break; DELAY(1000); } cmd = sc->a10_req->cmd; if (timeout == 0) { cmd->error = MMC_ERR_FAILED; a10_mmc_req_done(sc); return; } if (cmd->flags & MMC_RSP_PRESENT) { if (cmd->flags & MMC_RSP_136) { cmd->resp[0] = A10_MMC_READ_4(sc, A10_MMC_RESP3); cmd->resp[1] = A10_MMC_READ_4(sc, A10_MMC_RESP2); cmd->resp[2] = A10_MMC_READ_4(sc, A10_MMC_RESP1); cmd->resp[3] = A10_MMC_READ_4(sc, A10_MMC_RESP0); } else cmd->resp[0] = A10_MMC_READ_4(sc, A10_MMC_RESP0); } /* All data has been transferred ? */ if (cmd->data != NULL && (sc->a10_resid << 2) < cmd->data->len) cmd->error = MMC_ERR_FAILED; a10_mmc_req_done(sc); } static void a10_mmc_timeout(void *arg) { struct a10_mmc_softc *sc; sc = (struct a10_mmc_softc *)arg; if (sc->a10_req != NULL) { device_printf(sc->a10_dev, "controller timeout\n"); sc->a10_req->cmd->error = MMC_ERR_TIMEOUT; a10_mmc_req_done(sc); } else device_printf(sc->a10_dev, "Spurious timeout - no active request\n"); } static int a10_mmc_pio_transfer(struct a10_mmc_softc *sc, struct mmc_data *data) { int i, write; uint32_t bit, *buf; buf = (uint32_t *)data->data; write = (data->flags & MMC_DATA_WRITE) ? 1 : 0; bit = write ? A10_MMC_FIFO_FULL : A10_MMC_FIFO_EMPTY; for (i = sc->a10_resid; i < (data->len >> 2); i++) { if ((A10_MMC_READ_4(sc, A10_MMC_STAS) & bit)) return (1); if (write) A10_MMC_WRITE_4(sc, sc->a10_fifo_reg, buf[i]); else buf[i] = A10_MMC_READ_4(sc, sc->a10_fifo_reg); sc->a10_resid = i + 1; } return (0); } static void a10_mmc_intr(void *arg) { bus_dmasync_op_t sync_op; struct a10_mmc_softc *sc; struct mmc_data *data; uint32_t idst, imask, rint; sc = (struct a10_mmc_softc *)arg; A10_MMC_LOCK(sc); rint = A10_MMC_READ_4(sc, A10_MMC_RINTR); idst = A10_MMC_READ_4(sc, A10_MMC_IDST); imask = A10_MMC_READ_4(sc, A10_MMC_IMASK); if (idst == 0 && imask == 0 && rint == 0) { A10_MMC_UNLOCK(sc); return; } #ifdef DEBUG device_printf(sc->a10_dev, "idst: %#x, imask: %#x, rint: %#x\n", idst, imask, rint); #endif if (sc->a10_req == NULL) { device_printf(sc->a10_dev, "Spurious interrupt - no active request, rint: 0x%08X\n", rint); goto end; } if (rint & A10_MMC_INT_ERR_BIT) { device_printf(sc->a10_dev, "error rint: 0x%08X\n", rint); if (rint & A10_MMC_RESP_TIMEOUT) sc->a10_req->cmd->error = MMC_ERR_TIMEOUT; else sc->a10_req->cmd->error = MMC_ERR_FAILED; a10_mmc_req_done(sc); goto end; } if (idst & A10_MMC_IDMAC_ERROR) { device_printf(sc->a10_dev, "error idst: 0x%08x\n", idst); sc->a10_req->cmd->error = MMC_ERR_FAILED; a10_mmc_req_done(sc); goto end; } sc->a10_intr |= rint; data = sc->a10_req->cmd->data; if (data != NULL && sc->a10_dma_inuse == 1 && (idst & A10_MMC_IDMAC_COMPLETE)) { if (data->flags & MMC_DATA_WRITE) sync_op = BUS_DMASYNC_POSTWRITE; else sync_op = BUS_DMASYNC_POSTREAD; bus_dmamap_sync(sc->a10_dma_buf_tag, sc->a10_dma_buf_map, sync_op); bus_dmamap_sync(sc->a10_dma_tag, sc->a10_dma_map, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(sc->a10_dma_buf_tag, sc->a10_dma_buf_map); sc->a10_resid = data->len >> 2; } else if (data != NULL && sc->a10_dma_inuse == 0 && (rint & (A10_MMC_DATA_OVER | A10_MMC_RX_DATA_REQ | A10_MMC_TX_DATA_REQ)) != 0) a10_mmc_pio_transfer(sc, data); if ((sc->a10_intr & sc->a10_intr_wait) == sc->a10_intr_wait) a10_mmc_req_ok(sc); end: A10_MMC_WRITE_4(sc, A10_MMC_IDST, idst); A10_MMC_WRITE_4(sc, A10_MMC_RINTR, rint); A10_MMC_UNLOCK(sc); } static int a10_mmc_request(device_t bus, device_t child, struct mmc_request *req) { int blksz; struct a10_mmc_softc *sc; struct mmc_command *cmd; uint32_t cmdreg, val; sc = device_get_softc(bus); A10_MMC_LOCK(sc); if (sc->a10_req) { A10_MMC_UNLOCK(sc); return (EBUSY); } sc->a10_req = req; cmd = req->cmd; cmdreg = A10_MMC_START; if (cmd->opcode == MMC_GO_IDLE_STATE) cmdreg |= A10_MMC_SEND_INIT_SEQ; if (cmd->flags & MMC_RSP_PRESENT) cmdreg |= A10_MMC_RESP_EXP; if (cmd->flags & MMC_RSP_136) cmdreg |= A10_MMC_LONG_RESP; if (cmd->flags & MMC_RSP_CRC) cmdreg |= A10_MMC_CHECK_RESP_CRC; sc->a10_intr = 0; sc->a10_resid = 0; sc->a10_intr_wait = A10_MMC_CMD_DONE; cmd->error = MMC_ERR_NONE; if (cmd->data != NULL) { sc->a10_intr_wait |= A10_MMC_DATA_OVER; cmdreg |= A10_MMC_DATA_EXP | A10_MMC_WAIT_PREOVER; if (cmd->data->flags & MMC_DATA_MULTI) { cmdreg |= A10_MMC_SEND_AUTOSTOP; sc->a10_intr_wait |= A10_MMC_AUTOCMD_DONE; } if (cmd->data->flags & MMC_DATA_WRITE) cmdreg |= A10_MMC_WRITE; blksz = min(cmd->data->len, MMC_SECTOR_SIZE); A10_MMC_WRITE_4(sc, A10_MMC_BLKSZ, blksz); A10_MMC_WRITE_4(sc, A10_MMC_BCNTR, cmd->data->len); if (a10_mmc_pio_mode == 0) a10_mmc_prepare_dma(sc); /* Enable PIO access if sc->a10_dma_inuse is not set. */ if (sc->a10_dma_inuse == 0) { val = A10_MMC_READ_4(sc, A10_MMC_GCTRL); val &= ~A10_MMC_DMA_ENABLE; val |= A10_MMC_ACCESS_BY_AHB; A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, val); val = A10_MMC_READ_4(sc, A10_MMC_IMASK); val |= A10_MMC_RX_DATA_REQ | A10_MMC_TX_DATA_REQ; A10_MMC_WRITE_4(sc, A10_MMC_IMASK, val); } } A10_MMC_WRITE_4(sc, A10_MMC_CARG, cmd->arg); A10_MMC_WRITE_4(sc, A10_MMC_CMDR, cmdreg | cmd->opcode); callout_reset(&sc->a10_timeoutc, sc->a10_timeout * hz, a10_mmc_timeout, sc); A10_MMC_UNLOCK(sc); return (0); } static int a10_mmc_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) { struct a10_mmc_softc *sc; sc = device_get_softc(bus); switch (which) { default: return (EINVAL); case MMCBR_IVAR_BUS_MODE: *(int *)result = sc->a10_host.ios.bus_mode; break; case MMCBR_IVAR_BUS_WIDTH: *(int *)result = sc->a10_host.ios.bus_width; break; case MMCBR_IVAR_CHIP_SELECT: *(int *)result = sc->a10_host.ios.chip_select; break; case MMCBR_IVAR_CLOCK: *(int *)result = sc->a10_host.ios.clock; break; case MMCBR_IVAR_F_MIN: *(int *)result = sc->a10_host.f_min; break; case MMCBR_IVAR_F_MAX: *(int *)result = sc->a10_host.f_max; break; case MMCBR_IVAR_HOST_OCR: *(int *)result = sc->a10_host.host_ocr; break; case MMCBR_IVAR_MODE: *(int *)result = sc->a10_host.mode; break; case MMCBR_IVAR_OCR: *(int *)result = sc->a10_host.ocr; break; case MMCBR_IVAR_POWER_MODE: *(int *)result = sc->a10_host.ios.power_mode; break; case MMCBR_IVAR_VDD: *(int *)result = sc->a10_host.ios.vdd; break; case MMCBR_IVAR_CAPS: *(int *)result = sc->a10_host.caps; break; case MMCBR_IVAR_MAX_DATA: *(int *)result = 65535; break; } return (0); } static int a10_mmc_write_ivar(device_t bus, device_t child, int which, uintptr_t value) { struct a10_mmc_softc *sc; sc = device_get_softc(bus); switch (which) { default: return (EINVAL); case MMCBR_IVAR_BUS_MODE: sc->a10_host.ios.bus_mode = value; break; case MMCBR_IVAR_BUS_WIDTH: sc->a10_host.ios.bus_width = value; break; case MMCBR_IVAR_CHIP_SELECT: sc->a10_host.ios.chip_select = value; break; case MMCBR_IVAR_CLOCK: sc->a10_host.ios.clock = value; break; case MMCBR_IVAR_MODE: sc->a10_host.mode = value; break; case MMCBR_IVAR_OCR: sc->a10_host.ocr = value; break; case MMCBR_IVAR_POWER_MODE: sc->a10_host.ios.power_mode = value; break; case MMCBR_IVAR_VDD: sc->a10_host.ios.vdd = value; break; /* These are read-only */ case MMCBR_IVAR_CAPS: case MMCBR_IVAR_HOST_OCR: case MMCBR_IVAR_F_MIN: case MMCBR_IVAR_F_MAX: case MMCBR_IVAR_MAX_DATA: return (EINVAL); } return (0); } static int a10_mmc_update_clock(struct a10_mmc_softc *sc) { uint32_t cmdreg; int retry; cmdreg = A10_MMC_START | A10_MMC_UPCLK_ONLY | A10_MMC_WAIT_PREOVER; A10_MMC_WRITE_4(sc, A10_MMC_CMDR, cmdreg); retry = 0xfffff; while (--retry > 0) { if ((A10_MMC_READ_4(sc, A10_MMC_CMDR) & A10_MMC_START) == 0) { A10_MMC_WRITE_4(sc, A10_MMC_RINTR, 0xffffffff); return (0); } DELAY(10); } A10_MMC_WRITE_4(sc, A10_MMC_RINTR, 0xffffffff); device_printf(sc->a10_dev, "timeout updating clock\n"); return (ETIMEDOUT); } static int a10_mmc_update_ios(device_t bus, device_t child) { int error; struct a10_mmc_softc *sc; struct mmc_ios *ios; uint32_t clkcr; sc = device_get_softc(bus); clkcr = A10_MMC_READ_4(sc, A10_MMC_CLKCR); if (clkcr & A10_MMC_CARD_CLK_ON) { /* Disable clock. */ clkcr &= ~A10_MMC_CARD_CLK_ON; A10_MMC_WRITE_4(sc, A10_MMC_CLKCR, clkcr); error = a10_mmc_update_clock(sc); if (error != 0) return (error); } ios = &sc->a10_host.ios; if (ios->clock) { /* Reset the divider. */ clkcr &= ~A10_MMC_CLKCR_DIV; A10_MMC_WRITE_4(sc, A10_MMC_CLKCR, clkcr); error = a10_mmc_update_clock(sc); if (error != 0) return (error); /* Set the MMC clock. */ - switch (allwinner_soc_type()) { -#if defined(SOC_ALLWINNER_A10) || defined(SOC_ALLWINNER_A20) - case ALLWINNERSOC_A10: - case ALLWINNERSOC_A10S: - case ALLWINNERSOC_A20: - error = a10_clk_mmc_cfg(sc->a10_id, ios->clock); - break; -#endif -#if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S) - case ALLWINNERSOC_A31: - case ALLWINNERSOC_A31S: - error = a31_clk_mmc_cfg(sc->a10_id, ios->clock); - break; -#endif - default: - error = ENXIO; - } - if (error != 0) + error = clk_set_freq(sc->a10_clk_mmc, ios->clock, + CLK_SET_ROUND_DOWN); + if (error != 0) { + device_printf(sc->a10_dev, + "failed to set frequency to %u Hz: %d\n", + ios->clock, error); return (error); + } /* Enable clock. */ clkcr |= A10_MMC_CARD_CLK_ON; A10_MMC_WRITE_4(sc, A10_MMC_CLKCR, clkcr); error = a10_mmc_update_clock(sc); if (error != 0) return (error); } /* Set the bus width. */ switch (ios->bus_width) { case bus_width_1: A10_MMC_WRITE_4(sc, A10_MMC_WIDTH, A10_MMC_WIDTH1); break; case bus_width_4: A10_MMC_WRITE_4(sc, A10_MMC_WIDTH, A10_MMC_WIDTH4); break; case bus_width_8: A10_MMC_WRITE_4(sc, A10_MMC_WIDTH, A10_MMC_WIDTH8); break; } return (0); } static int a10_mmc_get_ro(device_t bus, device_t child) { return (0); } static int a10_mmc_acquire_host(device_t bus, device_t child) { struct a10_mmc_softc *sc; int error; sc = device_get_softc(bus); A10_MMC_LOCK(sc); while (sc->a10_bus_busy) { error = msleep(sc, &sc->a10_mtx, PCATCH, "mmchw", 0); if (error != 0) { A10_MMC_UNLOCK(sc); return (error); } } sc->a10_bus_busy++; A10_MMC_UNLOCK(sc); return (0); } static int a10_mmc_release_host(device_t bus, device_t child) { struct a10_mmc_softc *sc; sc = device_get_softc(bus); A10_MMC_LOCK(sc); sc->a10_bus_busy--; wakeup(sc); A10_MMC_UNLOCK(sc); return (0); } static device_method_t a10_mmc_methods[] = { /* Device interface */ DEVMETHOD(device_probe, a10_mmc_probe), DEVMETHOD(device_attach, a10_mmc_attach), DEVMETHOD(device_detach, a10_mmc_detach), /* Bus interface */ DEVMETHOD(bus_read_ivar, a10_mmc_read_ivar), DEVMETHOD(bus_write_ivar, a10_mmc_write_ivar), DEVMETHOD(bus_print_child, bus_generic_print_child), /* MMC bridge interface */ DEVMETHOD(mmcbr_update_ios, a10_mmc_update_ios), DEVMETHOD(mmcbr_request, a10_mmc_request), DEVMETHOD(mmcbr_get_ro, a10_mmc_get_ro), DEVMETHOD(mmcbr_acquire_host, a10_mmc_acquire_host), DEVMETHOD(mmcbr_release_host, a10_mmc_release_host), DEVMETHOD_END }; static devclass_t a10_mmc_devclass; static driver_t a10_mmc_driver = { "a10_mmc", a10_mmc_methods, sizeof(struct a10_mmc_softc), }; DRIVER_MODULE(a10_mmc, simplebus, a10_mmc_driver, a10_mmc_devclass, 0, 0); DRIVER_MODULE(mmc, a10_mmc, mmc_driver, mmc_devclass, NULL, NULL); MODULE_DEPEND(a10_mmc, mmc, 1, 1, 1); Index: head/sys/arm/allwinner/a20/a20_if_dwc.c =================================================================== --- head/sys/arm/allwinner/a20/a20_if_dwc.c (revision 297626) +++ head/sys/arm/allwinner/a20/a20_if_dwc.c (revision 297627) @@ -1,125 +1,134 @@ /*- * Copyright (c) 2015 Luiz Otavio O Souza * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include -#include -#include +#include #include "if_dwc_if.h" static int a20_if_dwc_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "allwinner,sun7i-a20-gmac")) return (ENXIO); device_set_desc(dev, "A20 Gigabit Ethernet Controller"); return (BUS_PROBE_DEFAULT); } static int a20_if_dwc_init(device_t dev) { - int clk; + const char *tx_parent_name; + char *phy_type; + clk_t clk_tx, clk_tx_parent; + phandle_t node; + int error; - /* Activate GMAC clock and set the pin mux to rgmii. */ - switch (allwinner_soc_type()) { -#if defined(SOC_ALLWINNER_A10) || defined(SOC_ALLWINNER_A20) - case ALLWINNERSOC_A10: - case ALLWINNERSOC_A10S: - case ALLWINNERSOC_A20: - clk = a10_clk_gmac_activate(ofw_bus_get_node(dev)); - break; -#endif -#if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S) - case ALLWINNERSOC_A31: - case ALLWINNERSOC_A31S: - clk = a31_clk_gmac_activate(ofw_bus_get_node(dev)); - break; -#endif - default: - clk = -1; - } - if (clk != 0) { - device_printf(dev, "could not activate gmac module\n"); - return (ENXIO); + node = ofw_bus_get_node(dev); + + /* Configure PHY for MII or RGMII mode */ + if (OF_getprop_alloc(node, "phy-mode", 1, (void **)&phy_type)) { + error = clk_get_by_ofw_name(dev, "allwinner_gmac_tx", &clk_tx); + if (error != 0) { + device_printf(dev, "could not get tx clk\n"); + return (error); + } + + if (strcmp(phy_type, "rgmii") == 0) + tx_parent_name = "gmac_int_tx"; + else + tx_parent_name = "mii_phy_tx"; + + error = clk_get_by_name(dev, tx_parent_name, &clk_tx_parent); + if (error != 0) { + device_printf(dev, "could not get clock '%s'\n", + tx_parent_name); + return (error); + } + + error = clk_set_parent_by_clk(clk_tx, clk_tx_parent); + if (error != 0) { + device_printf(dev, "could not set tx clk parent\n"); + return (error); + } } return (0); } static int a20_if_dwc_mac_type(device_t dev) { return (DWC_GMAC_ALT_DESC); } static int a20_if_dwc_mii_clk(device_t dev) { return (GMAC_MII_CLK_150_250M_DIV102); } static device_method_t a20_dwc_methods[] = { DEVMETHOD(device_probe, a20_if_dwc_probe), DEVMETHOD(if_dwc_init, a20_if_dwc_init), DEVMETHOD(if_dwc_mac_type, a20_if_dwc_mac_type), DEVMETHOD(if_dwc_mii_clk, a20_if_dwc_mii_clk), DEVMETHOD_END }; static devclass_t a20_dwc_devclass; extern driver_t dwc_driver; DEFINE_CLASS_1(dwc, a20_dwc_driver, a20_dwc_methods, sizeof(struct dwc_softc), dwc_driver); DRIVER_MODULE(a20_dwc, simplebus, a20_dwc_driver, a20_dwc_devclass, 0, 0); MODULE_DEPEND(a20_dwc, dwc, 1, 1, 1); Index: head/sys/arm/allwinner/a31/a31_clk.c =================================================================== --- head/sys/arm/allwinner/a31/a31_clk.c (revision 297626) +++ head/sys/arm/allwinner/a31/a31_clk.c (nonexistent) @@ -1,378 +0,0 @@ -/*- - * Copyright (c) 2013 Ganbold Tsagaankhuu - * Copyright (c) 2016 Emmanuel Vadot - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* - * Simple clock driver for Allwinner A31 - * Adapted from a10_clk.c -*/ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -struct a31_ccm_softc { - struct resource *res; - struct mtx mtx; - int pll6_enabled; - int ehci_refcnt; -}; - -static struct a31_ccm_softc *a31_ccm_sc = NULL; - -#define ccm_read_4(sc, reg) \ - bus_read_4((sc)->res, (reg)) -#define ccm_write_4(sc, reg, val) \ - bus_write_4((sc)->res, (reg), (val)) - -#define CCM_LOCK(sc) mtx_lock(&(sc)->mtx) -#define CCM_UNLOCK(sc) mtx_unlock(&(sc)->mtx) - -#define PLL6_TIMEOUT 10 - -static int -a31_ccm_probe(device_t dev) -{ - - if (!ofw_bus_status_okay(dev)) - return (ENXIO); - - if (ofw_bus_is_compatible(dev, "allwinner,sun6i-a31-ccm")) { - device_set_desc(dev, "Allwinner Clock Control Module"); - return(BUS_PROBE_DEFAULT); - } - - return (ENXIO); -} - -static int -a31_ccm_attach(device_t dev) -{ - struct a31_ccm_softc *sc = device_get_softc(dev); - int rid = 0; - - if (a31_ccm_sc) - return (ENXIO); - - sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); - if (!sc->res) { - device_printf(dev, "could not allocate resource\n"); - return (ENXIO); - } - - mtx_init(&sc->mtx, "a31 ccm", NULL, MTX_DEF); - - a31_ccm_sc = sc; - - return (0); -} - -static device_method_t a31_ccm_methods[] = { - DEVMETHOD(device_probe, a31_ccm_probe), - DEVMETHOD(device_attach, a31_ccm_attach), - { 0, 0 } -}; - -static driver_t a31_ccm_driver = { - "a31_ccm", - a31_ccm_methods, - sizeof(struct a31_ccm_softc), -}; - -static devclass_t a31_ccm_devclass; - -EARLY_DRIVER_MODULE(a31_ccm, simplebus, a31_ccm_driver, a31_ccm_devclass, 0, 0, - BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); - -static int -a31_clk_pll6_enable(void) -{ - struct a31_ccm_softc *sc; - uint32_t reg_value; - int i; - - /* Datasheet recommand to use the default 600Mhz value */ - sc = a31_ccm_sc; - if (sc->pll6_enabled) - return (0); - reg_value = ccm_read_4(sc, A31_CCM_PLL6_CFG); - reg_value |= A31_CCM_PLL_CFG_ENABLE; - ccm_write_4(sc, A31_CCM_PLL6_CFG, reg_value); - - /* Wait for PLL to be stable */ - for (i = 0; i < PLL6_TIMEOUT; i++) - if ((ccm_read_4(sc, A31_CCM_PLL6_CFG) & - A31_CCM_PLL6_CFG_REG_LOCK) == A31_CCM_PLL6_CFG_REG_LOCK) - break; - if (i == PLL6_TIMEOUT) - return (ENXIO); - sc->pll6_enabled = 1; - - return (0); -} - -static unsigned int -a31_clk_pll6_get_rate(void) -{ - struct a31_ccm_softc *sc; - uint32_t k, n, reg_value; - - sc = a31_ccm_sc; - reg_value = ccm_read_4(sc, A31_CCM_PLL6_CFG); - n = ((reg_value & A31_CCM_PLL_CFG_FACTOR_N) >> - A31_CCM_PLL_CFG_FACTOR_N_SHIFT); - k = ((reg_value & A31_CCM_PLL_CFG_FACTOR_K) >> - A31_CCM_PLL_CFG_FACTOR_K_SHIFT) + 1; - - return ((A31_CCM_CLK_REF_FREQ * n * k) / 2); -} - -int -a31_clk_gmac_activate(phandle_t node) -{ - char *phy_type; - struct a31_ccm_softc *sc; - uint32_t reg_value; - - sc = a31_ccm_sc; - if (sc == NULL) - return (ENXIO); - - if (a31_clk_pll6_enable()) - return (ENXIO); - - /* Gating AHB clock for GMAC */ - reg_value = ccm_read_4(sc, A31_CCM_AHB_GATING0); - reg_value |= A31_CCM_AHB_GATING_GMAC; - ccm_write_4(sc, A31_CCM_AHB_GATING0, reg_value); - - /* Set GMAC mode. */ - reg_value = A31_CCM_GMAC_CLK_MII; - if (OF_getprop_alloc(node, "phy-mode", 1, (void **)&phy_type) > 0) { - if (strcasecmp(phy_type, "rgmii") == 0) - reg_value = A31_CCM_GMAC_CLK_RGMII | - A31_CCM_GMAC_MODE_RGMII; - free(phy_type, M_OFWPROP); - } - ccm_write_4(sc, A31_CCM_GMAC_CLK, reg_value); - - /* Reset gmac */ - reg_value = ccm_read_4(sc, A31_CCM_AHB1_RST_REG0); - reg_value |= A31_CCM_AHB1_RST_REG0_GMAC; - ccm_write_4(sc, A31_CCM_AHB1_RST_REG0, reg_value); - - return (0); -} - -int -a31_clk_mmc_activate(int devid) -{ - struct a31_ccm_softc *sc; - uint32_t reg_value; - - sc = a31_ccm_sc; - if (sc == NULL) - return (ENXIO); - - if (a31_clk_pll6_enable()) - return (ENXIO); - - /* Gating AHB clock for SD/MMC */ - reg_value = ccm_read_4(sc, A31_CCM_AHB_GATING0); - reg_value |= A31_CCM_AHB_GATING_SDMMC0 << devid; - ccm_write_4(sc, A31_CCM_AHB_GATING0, reg_value); - - /* Soft reset */ - reg_value = ccm_read_4(sc, A31_CCM_AHB1_RST_REG0); - reg_value |= A31_CCM_AHB1_RST_REG0_SDMMC << devid; - ccm_write_4(sc, A31_CCM_AHB1_RST_REG0, reg_value); - - return (0); -} - -int -a31_clk_mmc_cfg(int devid, int freq) -{ - struct a31_ccm_softc *sc; - uint32_t clksrc, m, n, ophase, phase, reg_value; - unsigned int pll_freq; - - sc = a31_ccm_sc; - if (sc == NULL) - return (ENXIO); - - freq /= 1000; - if (freq <= 400) { - pll_freq = A31_CCM_CLK_REF_FREQ / 1000; - clksrc = A31_CCM_SD_CLK_SRC_SEL_OSC24M; - ophase = 0; - phase = 0; - n = 2; - } else if (freq <= 25000) { - pll_freq = a31_clk_pll6_get_rate() / 1000; - clksrc = A31_CCM_SD_CLK_SRC_SEL_PLL6; - ophase = 0; - phase = 5; - n = 2; - } else if (freq <= 50000) { - pll_freq = a31_clk_pll6_get_rate() / 1000; - clksrc = A31_CCM_SD_CLK_SRC_SEL_PLL6; - ophase = 3; - phase = 5; - n = 0; - } else - return (EINVAL); - m = ((pll_freq / (1 << n)) / (freq)) - 1; - reg_value = ccm_read_4(sc, A31_CCM_MMC0_SCLK_CFG + (devid * 4)); - reg_value &= ~A31_CCM_SD_CLK_SRC_SEL; - reg_value |= (clksrc << A31_CCM_SD_CLK_SRC_SEL_SHIFT); - reg_value &= ~A31_CCM_SD_CLK_PHASE_CTR; - reg_value |= (phase << A31_CCM_SD_CLK_PHASE_CTR_SHIFT); - reg_value &= ~A31_CCM_SD_CLK_DIV_RATIO_N; - reg_value |= (n << A31_CCM_SD_CLK_DIV_RATIO_N_SHIFT); - reg_value &= ~A31_CCM_SD_CLK_OPHASE_CTR; - reg_value |= (ophase << A31_CCM_SD_CLK_OPHASE_CTR_SHIFT); - reg_value &= ~A31_CCM_SD_CLK_DIV_RATIO_M; - reg_value |= m; - reg_value |= A31_CCM_PLL_CFG_ENABLE; - ccm_write_4(sc, A31_CCM_MMC0_SCLK_CFG + (devid * 4), reg_value); - - return (0); -} - -int -a31_clk_i2c_activate(int devid) -{ - struct a31_ccm_softc *sc; - uint32_t reg_value; - - sc = a31_ccm_sc; - if (sc == NULL) - return (ENXIO); - - if (a31_clk_pll6_enable()) - return (ENXIO); - - /* Gating APB clock for I2C/TWI */ - reg_value = ccm_read_4(sc, A31_CCM_APB2_GATING); - reg_value |= A31_CCM_APB2_GATING_TWI << devid; - ccm_write_4(sc, A31_CCM_APB2_GATING, reg_value); - - /* Soft reset */ - reg_value = ccm_read_4(sc, A31_CCM_APB2_RST); - reg_value |= A31_CCM_APB2_RST_TWI << devid; - ccm_write_4(sc, A31_CCM_APB2_RST, reg_value); - - return (0); -} - -int -a31_clk_ehci_activate(void) -{ - struct a31_ccm_softc *sc; - uint32_t reg_value; - - sc = a31_ccm_sc; - if (sc == NULL) - return (ENXIO); - - CCM_LOCK(sc); - if (++sc->ehci_refcnt == 1) { - /* Enable USB PHY */ - reg_value = ccm_read_4(sc, A31_CCM_USBPHY_CLK); - reg_value |= A31_CCM_USBPHY_CLK_GATING_USBPHY0; - reg_value |= A31_CCM_USBPHY_CLK_GATING_USBPHY1; - reg_value |= A31_CCM_USBPHY_CLK_GATING_USBPHY2; - reg_value |= A31_CCM_USBPHY_CLK_USBPHY1_RST; - reg_value |= A31_CCM_USBPHY_CLK_USBPHY2_RST; - ccm_write_4(sc, A31_CCM_USBPHY_CLK, reg_value); - - /* Gating AHB clock for EHCI */ - reg_value = ccm_read_4(sc, A31_CCM_AHB_GATING0); - reg_value |= A31_CCM_AHB_GATING_EHCI0; - reg_value |= A31_CCM_AHB_GATING_EHCI1; - ccm_write_4(sc, A31_CCM_AHB_GATING0, reg_value); - - /* De-assert reset */ - reg_value = ccm_read_4(sc, A31_CCM_AHB1_RST_REG0); - reg_value |= A31_CCM_AHB1_RST_REG0_EHCI0; - reg_value |= A31_CCM_AHB1_RST_REG0_EHCI1; - ccm_write_4(sc, A31_CCM_AHB1_RST_REG0, reg_value); - } - CCM_UNLOCK(sc); - - return (0); -} - -int -a31_clk_ehci_deactivate(void) -{ - struct a31_ccm_softc *sc; - uint32_t reg_value; - - sc = a31_ccm_sc; - if (sc == NULL) - return (ENXIO); - - CCM_LOCK(sc); - if (--sc->ehci_refcnt == 0) { - /* Disable USB PHY */ - reg_value = ccm_read_4(sc, A31_CCM_USBPHY_CLK); - reg_value &= ~A31_CCM_USBPHY_CLK_GATING_USBPHY0; - reg_value &= ~A31_CCM_USBPHY_CLK_GATING_USBPHY1; - reg_value &= ~A31_CCM_USBPHY_CLK_GATING_USBPHY2; - reg_value &= ~A31_CCM_USBPHY_CLK_USBPHY1_RST; - reg_value &= ~A31_CCM_USBPHY_CLK_USBPHY2_RST; - ccm_write_4(sc, A31_CCM_USBPHY_CLK, reg_value); - - /* Gating AHB clock for EHCI */ - reg_value = ccm_read_4(sc, A31_CCM_AHB_GATING0); - reg_value &= ~A31_CCM_AHB_GATING_EHCI0; - reg_value &= ~A31_CCM_AHB_GATING_EHCI1; - ccm_write_4(sc, A31_CCM_AHB_GATING0, reg_value); - - /* Assert reset */ - reg_value = ccm_read_4(sc, A31_CCM_AHB1_RST_REG0); - reg_value &= ~A31_CCM_AHB1_RST_REG0_EHCI0; - reg_value &= ~A31_CCM_AHB1_RST_REG0_EHCI1; - ccm_write_4(sc, A31_CCM_AHB1_RST_REG0, reg_value); - } - CCM_UNLOCK(sc); - - return (0); -} Property changes on: head/sys/arm/allwinner/a31/a31_clk.c ___________________________________________________________________ Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Index: head/sys/arm/allwinner/a31/a31_clk.h =================================================================== --- head/sys/arm/allwinner/a31/a31_clk.h (revision 297626) +++ head/sys/arm/allwinner/a31/a31_clk.h (nonexistent) @@ -1,213 +0,0 @@ -/*- - * Copyright (c) 2013 Ganbold Tsagaankhuu - * Copyright (c) 2016 Emmanuel Vadot - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#ifndef _A31_CLK_H_ -#define _A31_CLK_H_ - -#define A31_CCM_PLL1_CFG 0x0000 -#define A31_CCM_PLL2_CFG 0x0008 -#define A31_CCM_PLL3_CFG 0x0010 -#define A31_CCM_PLL4_CFG 0x0018 -#define A31_CCM_PLL5_CFG 0x0020 -#define A31_CCM_PLL6_CFG 0x0028 -#define A31_CCM_PLL7_CFG 0x0030 -#define A31_CCM_PLL8_CFG 0x0038 -#define A31_CCM_MIPI_PLL_CFG 0x0040 -#define A31_CCM_PLL9_CFG 0x0044 -#define A31_CCM_PLL10_CFG 0x0048 -#define A31_CCM_AXI_CFG_REG 0x0050 -#define A31_CCM_AHB1_APB1_CFG 0x0054 -#define A31_CCM_APB2_CLK_DIV 0x0058 -#define A31_CCM_AHB_GATING0 0x0060 -#define A31_CCM_AHB_GATING1 0x0064 -#define A31_CCM_APB1_GATING 0x0068 -#define A31_CCM_APB2_GATING 0x006c -#define A31_CCM_NAND0_SCLK_CFG 0x0080 -#define A31_CCM_NAND1_SCLK_CFG 0x0084 -#define A31_CCM_MMC0_SCLK_CFG 0x0088 -#define A31_CCM_MMC1_SCLK_CFG 0x008c -#define A31_CCM_MMC2_SCLK_CFG 0x0090 -#define A31_CCM_MMC3_SCLK_CFG 0x0094 -#define A31_CCM_TS_CLK 0x0098 -#define A31_CCM_SS_CLK 0x009c -#define A31_CCM_SPI0_CLK 0x00a0 -#define A31_CCM_SPI1_CLK 0x00a4 -#define A31_CCM_SPI2_CLK 0x00a8 -#define A31_CCM_SPI3_CLK 0x00ac -#define A31_CCM_DAUDIO0_CLK 0x00b0 -#define A31_CCM_DAUDIO1_CLK 0x00b4 -#define A31_CCM_USBPHY_CLK 0x00cc -#define A31_CCM_GMAC_CLK 0x00d0 -#define A31_CCM_MDFS_CLK 0x00f0 -#define A31_CCM_DRAM_CLK 0x00f4 -#define A31_CCM_DRAM_GATING 0x0100 -#define A31_CCM_BE0_SCLK 0x0104 -#define A31_CCM_BE1_SCLK 0x0108 -#define A31_CCM_FE0_CLK 0x010c -#define A31_CCM_FE1_CLK 0x0110 -#define A31_CCM_MP_CLK 0x0114 -#define A31_CCM_LCD0_CH0_CLK 0x0118 -#define A31_CCM_LCD1_CH0_CLK 0x011c -#define A31_CCM_LCD0_CH1_CLK 0x012c -#define A31_CCM_LCD1_CH1_CLK 0x0130 -#define A31_CCM_CSI0_CLK 0x0134 -#define A31_CCM_CSI1_CLK 0x0138 -#define A31_CCM_VE_CLK 0x013c -#define A31_CCM_AUDIO_CODEC_CLK 0x0140 -#define A31_CCM_AVS_CLK 0x0144 -#define A31_CCM_DIGITAL_MIC_CLK 0x0148 -#define A31_CCM_HDMI_CLK 0x0150 -#define A31_CCM_PS_CLK 0x0154 -#define A31_CCM_MBUS_SCLK_CFG0 0x015c -#define A31_CCM_MBUS_SCLK_CFG1 0x0160 -#define A31_CCM_MIPI_DSI_CLK 0x0168 -#define A31_CCM_MIPI_CSI0_CLK 0x016c -#define A31_CCM_DRC0_SCLK_CFG 0x0180 -#define A31_CCM_DRC1_SCLK_CFG 0x0184 -#define A31_CCM_DEU0_SCLK_CFG 0x0188 -#define A31_CCM_DEU1_SCLK_CFG 0x018c -#define A31_CCM_GPU_CORE_CLK 0x01a0 -#define A31_CCM_GPU_MEM_CLK 0x01a4 -#define A31_CCM_GPU_HYD_CLK 0x01a8 -#define A31_CCM_ATS_CLK 0x01b0 -#define A31_CCM_TRACE_CLK 0x01b4 -#define A31_CCM_PLL_LOCK_CFG 0x0200 -#define A31_CCM_PLL1_LOCK_CFG 0x0204 -#define A31_CCM_PLL1_BIAS 0x0220 -#define A31_CCM_PLL2_BIAS 0x0224 -#define A31_CCM_PLL3_BIAS 0x0228 -#define A31_CCM_PLL4_BIAS 0x022c -#define A31_CCM_PLL5_BIAS 0x0230 -#define A31_CCM_PLL6_BIAS 0x0234 -#define A31_CCM_PLL7_BIAS 0x0238 -#define A31_CCM_PLL8_BIAS 0x023c -#define A31_CCM_PLL9_BIAS 0x0240 -#define A31_CCM_MIPI_PLL_BIAS 0x0244 -#define A31_CCM_PLL10_BIAS 0x0248 -#define A31_CCM_PLL1_PAT_CFG 0x0280 -#define A31_CCM_PLL2_PAT_CFG 0x0284 -#define A31_CCM_PLL3_PAT_CFG 0x0288 -#define A31_CCM_PLL4_PAT_CFG 0x028c -#define A31_CCM_PLL5_PAT_CFG 0x0290 -#define A31_CCM_PLL6_PAT_CFG 0x0294 -#define A31_CCM_PLL7_PAT_CFG 0x0298 -#define A31_CCM_PLL8_PAT_CFG 0x029c -#define A31_CCM_MIPI_PLL_PAT_CFG 0x02a0 -#define A31_CCM_PLL9_PAT_CFG 0x02a4 -#define A31_CCM_PLL10_PAT_CFG 0x02a8 -#define A31_CCM_AHB1_RST_REG0 0x02c0 -#define A31_CCM_AHB1_RST_REG1 0x02c4 -#define A31_CCM_AHB1_RST_REG2 0x02c8 -#define A31_CCM_APB1_RST 0x02d0 -#define A31_CCM_APB2_RST 0x02d8 -#define A31_CCM_CLK_OUTA 0x0300 -#define A31_CCM_CLK_OUTB 0x0304 -#define A31_CCM_CLK_OUTC 0x0308 - -/* PLL6_CFG_REG */ -#define A31_CCM_PLL6_CFG_REG_LOCK (1 << 28) - -/* AHB_GATING_REG0 */ -#define A31_CCM_AHB_GATING_OHCI2 (1 << 31) -#define A31_CCM_AHB_GATING_OHCI1 (1 << 30) -#define A31_CCM_AHB_GATING_OHCI0 (1 << 29) -#define A31_CCM_AHB_GATING_EHCI1 (1 << 27) -#define A31_CCM_AHB_GATING_EHCI0 (1 << 26) -#define A31_CCM_AHB_GATING_USBDRD (1 << 24) -#define A31_CCM_AHB_GATING_GMAC (1 << 17) -#define A31_CCM_AHB_GATING_SDMMC0 (1 << 8) - -#define A31_CCM_PLL_CFG_ENABLE (1U << 31) -#define A31_CCM_PLL_CFG_BYPASS (1U << 30) -#define A31_CCM_PLL_CFG_PLL5 (1U << 25) -#define A31_CCM_PLL_CFG_PLL6 (1U << 24) -#define A31_CCM_PLL_CFG_FACTOR_N 0x1f00 -#define A31_CCM_PLL_CFG_FACTOR_N_SHIFT 8 -#define A31_CCM_PLL_CFG_FACTOR_K 0x30 -#define A31_CCM_PLL_CFG_FACTOR_K_SHIFT 4 -#define A31_CCM_PLL_CFG_FACTOR_M 0x3 - -/* APB2_GATING */ -#define A31_CCM_APB2_GATING_TWI (1 << 0) - -/* AHB1_RST_REG0 */ -#define A31_CCM_AHB1_RST_REG0_OHCI2 (1 << 31) -#define A31_CCM_AHB1_RST_REG0_OHCI1 (1 << 30) -#define A31_CCM_AHB1_RST_REG0_OHCI0 (1 << 29) -#define A31_CCM_AHB1_RST_REG0_EHCI1 (1 << 27) -#define A31_CCM_AHB1_RST_REG0_EHCI0 (1 << 26) -#define A31_CCM_AHB1_RST_REG0_GMAC (1 << 17) -#define A31_CCM_AHB1_RST_REG0_SDMMC (1 << 8) - -/* APB2_RST_REG */ -#define A31_CCM_APB2_RST_TWI (1 << 0) - - -/* GMAC */ -#define A31_CCM_GMAC_CLK_DELAY_SHIFT 10 -#define A31_CCM_GMAC_CLK_MODE_MASK 0x7 -#define A31_CCM_GMAC_MODE_RGMII (1 << 2) -#define A31_CCM_GMAC_CLK_MII 0x0 -#define A31_CCM_GMAC_CLK_EXT_RGMII 0x1 -#define A31_CCM_GMAC_CLK_RGMII 0x2 - -/* SD/MMC */ -#define A31_CCM_SD_CLK_SRC_SEL 0x3000000 -#define A31_CCM_SD_CLK_SRC_SEL_SHIFT 24 -#define A31_CCM_SD_CLK_SRC_SEL_OSC24M 0 -#define A31_CCM_SD_CLK_SRC_SEL_PLL6 1 -#define A31_CCM_SD_CLK_PHASE_CTR 0x700000 -#define A31_CCM_SD_CLK_PHASE_CTR_SHIFT 20 -#define A31_CCM_SD_CLK_DIV_RATIO_N 0x30000 -#define A31_CCM_SD_CLK_DIV_RATIO_N_SHIFT 16 -#define A31_CCM_SD_CLK_OPHASE_CTR 0x700 -#define A31_CCM_SD_CLK_OPHASE_CTR_SHIFT 8 -#define A31_CCM_SD_CLK_DIV_RATIO_M 0xf - -/* USB */ -#define A31_CCM_USBPHY_CLK_GATING_OHCI2 (1 << 18) -#define A31_CCM_USBPHY_CLK_GATING_OHCI1 (1 << 17) -#define A31_CCM_USBPHY_CLK_GATING_OHCI0 (1 << 16) -#define A31_CCM_USBPHY_CLK_GATING_USBPHY2 (1 << 10) -#define A31_CCM_USBPHY_CLK_GATING_USBPHY1 (1 << 9) -#define A31_CCM_USBPHY_CLK_GATING_USBPHY0 (1 << 8) -#define A31_CCM_USBPHY_CLK_USBPHY2_RST (1 << 2) -#define A31_CCM_USBPHY_CLK_USBPHY1_RST (1 << 1) -#define A31_CCM_USBPHY_CLK_USBPHY0_RST (1 << 0) - -#define A31_CCM_CLK_REF_FREQ 24000000U - -int a31_clk_gmac_activate(phandle_t); -int a31_clk_mmc_activate(int); -int a31_clk_mmc_cfg(int, int); -int a31_clk_i2c_activate(int); -int a31_clk_ehci_activate(void); -int a31_clk_ehci_deactivate(void); - -#endif /* _A31_CLK_H_ */ Property changes on: head/sys/arm/allwinner/a31/a31_clk.h ___________________________________________________________________ Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Index: head/sys/arm/allwinner/aw_ccu.c =================================================================== --- head/sys/arm/allwinner/aw_ccu.c (nonexistent) +++ head/sys/arm/allwinner/aw_ccu.c (revision 297627) @@ -0,0 +1,224 @@ +/*- + * Copyright (c) 2016 Jared McNeill + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Allwinner oscillator clock + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include + +#include "clkdev_if.h" + +#define CCU_BASE 0x01c20000 +#define CCU_SIZE 0x400 + +struct aw_ccu_softc { + struct simplebus_softc sc; + bus_space_tag_t bst; + bus_space_handle_t bsh; + struct mtx mtx; +}; + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun4i-a10", 1 }, + { "allwinner,sun7i-a20", 1 }, + { "allwinner,sun6i-a31", 1 }, + { "allwinner,sun6i-a31s", 1 }, + { NULL, 0 } +}; + +static int +aw_ccu_check_addr(bus_addr_t addr) +{ + if (addr < CCU_BASE || addr >= (CCU_BASE + CCU_SIZE)) + return (EINVAL); + return (0); +} + +static int +aw_ccu_write_4(device_t dev, bus_addr_t addr, uint32_t val) +{ + struct aw_ccu_softc *sc; + + if (aw_ccu_check_addr(addr) != 0) + return (EINVAL); + + sc = device_get_softc(dev); + mtx_assert(&sc->mtx, MA_OWNED); + bus_space_write_4(sc->bst, sc->bsh, addr - CCU_BASE, val); + + return (0); +} + +static int +aw_ccu_read_4(device_t dev, bus_addr_t addr, uint32_t *val) +{ + struct aw_ccu_softc *sc; + + if (aw_ccu_check_addr(addr) != 0) + return (EINVAL); + + sc = device_get_softc(dev); + mtx_assert(&sc->mtx, MA_OWNED); + *val = bus_space_read_4(sc->bst, sc->bsh, addr - CCU_BASE); + + return (0); +} + +static int +aw_ccu_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, uint32_t set) +{ + struct aw_ccu_softc *sc; + uint32_t val; + + if (aw_ccu_check_addr(addr) != 0) + return (EINVAL); + + sc = device_get_softc(dev); + mtx_assert(&sc->mtx, MA_OWNED); + val = bus_space_read_4(sc->bst, sc->bsh, addr - CCU_BASE); + val &= ~clr; + val |= set; + bus_space_write_4(sc->bst, sc->bsh, addr - CCU_BASE, val); + + return (0); +} + +static void +aw_ccu_device_lock(device_t dev) +{ + struct aw_ccu_softc *sc; + + sc = device_get_softc(dev); + mtx_lock(&sc->mtx); +} + +static void +aw_ccu_device_unlock(device_t dev) +{ + struct aw_ccu_softc *sc; + + sc = device_get_softc(dev); + mtx_unlock(&sc->mtx); +} + +static int +aw_ccu_probe(device_t dev) +{ + const char *name; + device_t pdev; + + name = ofw_bus_get_name(dev); + + if (name == NULL || strcmp(name, "clocks") != 0) + return (ENXIO); + + pdev = device_get_parent(dev); + if (ofw_bus_search_compatible(pdev, compat_data)->ocd_data == 0) + return (0); + + device_set_desc(dev, "Allwinner Clock Control Unit"); + return (BUS_PROBE_SPECIFIC); +} + +static int +aw_ccu_attach(device_t dev) +{ + struct aw_ccu_softc *sc; + phandle_t node, child; + device_t cdev; + int error; + + sc = device_get_softc(dev); + node = ofw_bus_get_node(dev); + + simplebus_init(dev, node); + + /* + * Map CCU registers. The DT doesn't have a "reg" property for the + * /clocks node and child nodes have conflicting "reg" properties. + */ + sc->bst = bus_get_bus_tag(dev); + error = bus_space_map(sc->bst, CCU_BASE, CCU_SIZE, 0, &sc->bsh); + if (error != 0) { + device_printf(dev, "couldn't map CCU: %d\n", error); + return (error); + } + + mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); + + /* Attach child devices */ + for (child = OF_child(node); child > 0; child = OF_peer(child)) { + cdev = simplebus_add_device(dev, child, 0, NULL, -1, NULL); + if (cdev != NULL) + device_probe_and_attach(cdev); + } + + return (bus_generic_attach(dev)); +} + +static device_method_t aw_ccu_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, aw_ccu_probe), + DEVMETHOD(device_attach, aw_ccu_attach), + + /* clkdev interface */ + DEVMETHOD(clkdev_write_4, aw_ccu_write_4), + DEVMETHOD(clkdev_read_4, aw_ccu_read_4), + DEVMETHOD(clkdev_modify_4, aw_ccu_modify_4), + DEVMETHOD(clkdev_device_lock, aw_ccu_device_lock), + DEVMETHOD(clkdev_device_unlock, aw_ccu_device_unlock), + + DEVMETHOD_END +}; + +DEFINE_CLASS_1(aw_ccu, aw_ccu_driver, aw_ccu_methods, + sizeof(struct aw_ccu_softc), simplebus_driver); + +static devclass_t aw_ccu_devclass; + +EARLY_DRIVER_MODULE(aw_ccu, simplebus, aw_ccu_driver, aw_ccu_devclass, + 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); + +MODULE_VERSION(aw_ccu, 1); Property changes on: head/sys/arm/allwinner/aw_ccu.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/allwinner/aw_reset.c =================================================================== --- head/sys/arm/allwinner/aw_reset.c (nonexistent) +++ head/sys/arm/allwinner/aw_reset.c (revision 297627) @@ -0,0 +1,163 @@ +/*- + * Copyright (c) 2016 Jared McNeill + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Allwinner module software reset registers + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include "hwreset_if.h" + +#define RESET_OFFSET(index) ((index / 32) * 4) +#define RESET_SHIFT(index) (index % 32) + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun6i-a31-ahb1-reset", 1 }, + { "allwinner,sun6i-a31-clock-reset", 1 }, + { NULL, 0 } +}; + +struct aw_reset_softc { + struct resource *res; + struct mtx mtx; +}; + +static struct resource_spec aw_reset_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { -1, 0 } +}; + +#define RESET_READ(sc, reg) bus_read_4((sc)->res, (reg)) +#define RESET_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) + +static int +aw_reset_assert(device_t dev, intptr_t id, bool reset) +{ + struct aw_reset_softc *sc; + uint32_t reg_value; + + sc = device_get_softc(dev); + + mtx_lock(&sc->mtx); + reg_value = RESET_READ(sc, RESET_OFFSET(id)); + if (reset) + reg_value &= ~(1 << RESET_SHIFT(id)); + else + reg_value |= (1 << RESET_SHIFT(id)); + RESET_WRITE(sc, RESET_OFFSET(id), reg_value); + mtx_unlock(&sc->mtx); + + return (0); +} + +static int +aw_reset_is_asserted(device_t dev, intptr_t id, bool *reset) +{ + struct aw_reset_softc *sc; + uint32_t reg_value; + + sc = device_get_softc(dev); + + mtx_lock(&sc->mtx); + reg_value = RESET_READ(sc, RESET_OFFSET(id)); + mtx_unlock(&sc->mtx); + + *reset = (reg_value & (1 << RESET_SHIFT(id))) != 0 ? false : true; + + return (0); +} + +static int +aw_reset_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Allwinner Module Resets"); + return (BUS_PROBE_DEFAULT); +} + +static int +aw_reset_attach(device_t dev) +{ + struct aw_reset_softc *sc; + + sc = device_get_softc(dev); + + if (bus_alloc_resources(dev, aw_reset_spec, &sc->res) != 0) { + device_printf(dev, "cannot allocate resources for device\n"); + return (ENXIO); + } + + mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); + + hwreset_register_ofw_provider(dev); + + return (0); +} + +static device_method_t aw_reset_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, aw_reset_probe), + DEVMETHOD(device_attach, aw_reset_attach), + + /* Reset interface */ + DEVMETHOD(hwreset_assert, aw_reset_assert), + DEVMETHOD(hwreset_is_asserted, aw_reset_is_asserted), + + DEVMETHOD_END +}; + +static driver_t aw_reset_driver = { + "aw_reset", + aw_reset_methods, + sizeof(struct aw_reset_softc), +}; + +static devclass_t aw_reset_devclass; + +DRIVER_MODULE(aw_reset, simplebus, aw_reset_driver, aw_reset_devclass, 0, 0); +MODULE_VERSION(aw_reset, 1); Property changes on: head/sys/arm/allwinner/aw_reset.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/allwinner/aw_usbphy.c =================================================================== --- head/sys/arm/allwinner/aw_usbphy.c (revision 297626) +++ head/sys/arm/allwinner/aw_usbphy.c (revision 297627) @@ -1,192 +1,149 @@ /*- * Copyright (c) 2016 Jared McNeill * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* * Allwinner USB PHY */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include -#include "gpio_if.h" +#include +#include +#include #define USBPHY_NUMOFF 3 -#define GPIO_POLARITY(flags) (((flags) & 1) ? GPIO_PIN_LOW : GPIO_PIN_HIGH) static struct ofw_compat_data compat_data[] = { { "allwinner,sun4i-a10-usb-phy", 1 }, { "allwinner,sun5i-a13-usb-phy", 1 }, { "allwinner,sun6i-a31-usb-phy", 1 }, { "allwinner,sun7i-a20-usb-phy", 1 }, { NULL, 0 } }; static int -awusbphy_gpio_set(device_t dev, phandle_t node, const char *pname) -{ - pcell_t gpio_prop[4]; - phandle_t gpio_node; - device_t gpio_dev; - uint32_t pin, flags; - ssize_t len; - int val; - - len = OF_getencprop(node, pname, gpio_prop, sizeof(gpio_prop)); - if (len == -1) - return (0); - - if (len != sizeof(gpio_prop)) { - device_printf(dev, "property %s length was %d, expected %d\n", - pname, len, sizeof(gpio_prop)); - return (ENXIO); - } - - gpio_node = OF_node_from_xref(gpio_prop[0]); - gpio_dev = OF_device_from_xref(gpio_prop[0]); - if (gpio_dev == NULL) { - device_printf(dev, "failed to get the GPIO device for %s\n", - pname); - return (ENOENT); - } - - if (GPIO_MAP_GPIOS(gpio_dev, node, gpio_node, - sizeof(gpio_prop) / sizeof(gpio_prop[0]) - 1, gpio_prop + 1, - &pin, &flags) != 0) { - device_printf(dev, "failed to map the GPIO pin for %s\n", - pname); - return (ENXIO); - } - - val = GPIO_POLARITY(flags); - - GPIO_PIN_SETFLAGS(gpio_dev, pin, GPIO_PIN_OUTPUT); - GPIO_PIN_SET(gpio_dev, pin, val); - - return (0); -} - -static int -awusbphy_supply_set(device_t dev, const char *pname) -{ - phandle_t node, reg_node; - pcell_t reg_xref; - - node = ofw_bus_get_node(dev); - - if (OF_getencprop(node, pname, ®_xref, sizeof(reg_xref)) == -1) - return (0); - - reg_node = OF_node_from_xref(reg_xref); - - return (awusbphy_gpio_set(dev, reg_node, "gpio")); -} - -static int awusbphy_init(device_t dev) { char pname[20]; - phandle_t node; int error, off; + regulator_t reg; + hwreset_t rst; + clk_t clk; - node = ofw_bus_get_node(dev); - - for (off = 0; off < USBPHY_NUMOFF; off++) { - snprintf(pname, sizeof(pname), "usb%d_id_det-gpio", off); - error = awusbphy_gpio_set(dev, node, pname); - if (error) + /* Enable clocks */ + for (off = 0; clk_get_by_ofw_index(dev, off, &clk) == 0; off++) { + error = clk_enable(clk); + if (error != 0) { + device_printf(dev, "couldn't enable clock %s\n", + clk_get_name(clk)); return (error); + } + } - snprintf(pname, sizeof(pname), "usb%d_vbus_det-gpio", off); - error = awusbphy_gpio_set(dev, node, pname); - if (error) + /* De-assert resets */ + for (off = 0; hwreset_get_by_ofw_idx(dev, off, &rst) == 0; off++) { + error = hwreset_deassert(rst); + if (error != 0) { + device_printf(dev, "couldn't de-assert reset %d\n", + off); return (error); + } + } + /* Enable regulator(s) */ + for (off = 0; off < USBPHY_NUMOFF; off++) { snprintf(pname, sizeof(pname), "usb%d_vbus-supply", off); - error = awusbphy_supply_set(dev, pname); - if (error) + if (regulator_get_by_ofw_property(dev, pname, ®) != 0) + continue; + error = regulator_enable(reg); + if (error != 0) { + device_printf(dev, "couldn't enable regulator %s\n", + pname); return (error); + } } return (0); } static int awusbphy_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Allwinner USB PHY"); return (BUS_PROBE_DEFAULT); } static int awusbphy_attach(device_t dev) { int error; error = awusbphy_init(dev); if (error) device_printf(dev, "failed to initialize USB PHY, error %d\n", error); return (error); } static device_method_t awusbphy_methods[] = { /* Device interface */ DEVMETHOD(device_probe, awusbphy_probe), DEVMETHOD(device_attach, awusbphy_attach), DEVMETHOD_END }; static driver_t awusbphy_driver = { "awusbphy", awusbphy_methods, 0, }; static devclass_t awusbphy_devclass; DRIVER_MODULE(awusbphy, simplebus, awusbphy_driver, awusbphy_devclass, 0, 0); MODULE_VERSION(awusbphy, 1); Index: head/sys/arm/allwinner/clk/aw_ahbclk.c =================================================================== --- head/sys/arm/allwinner/clk/aw_ahbclk.c (nonexistent) +++ head/sys/arm/allwinner/clk/aw_ahbclk.c (revision 297627) @@ -0,0 +1,308 @@ +/*- + * Copyright (c) 2016 Jared McNeill + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Allwinner AHB clock + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "clkdev_if.h" + +#define A10_AHB_CLK_DIV_RATIO (0x3 << 4) +#define A10_AHB_CLK_DIV_RATIO_SHIFT 4 + +#define A13_AHB_CLK_SRC_SEL (0x3 << 6) +#define A13_AHB_CLK_SRC_SEL_MAX 3 +#define A13_AHB_CLK_SRC_SEL_SHIFT 6 + +#define A31_AHB1_PRE_DIV (0x3 << 6) +#define A31_AHB1_PRE_DIV_SHIFT 6 +#define A31_AHB1_CLK_SRC_SEL (0x3 << 12) +#define A31_AHB1_CLK_SRC_SEL_PLL6 3 +#define A31_AHB1_CLK_SRC_SEL_MAX 3 +#define A31_AHB1_CLK_SRC_SEL_SHIFT 12 + +enum aw_ahbclk_type { + AW_A10_AHB = 1, + AW_A13_AHB, + AW_A31_AHB1, +}; + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun4i-a10-ahb-clk", AW_A10_AHB }, + { "allwinner,sun5i-a13-ahb-clk", AW_A13_AHB }, + { "allwinner,sun6i-a31-ahb1-clk", AW_A31_AHB1 }, + { NULL, 0 } +}; + +struct aw_ahbclk_sc { + device_t clkdev; + bus_addr_t reg; + enum aw_ahbclk_type type; +}; + +#define AHBCLK_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val)) +#define AHBCLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val)) +#define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev) +#define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev) + +static int +aw_ahbclk_init(struct clknode *clk, device_t dev) +{ + struct aw_ahbclk_sc *sc; + uint32_t val, index; + + sc = clknode_get_softc(clk); + + switch (sc->type) { + case AW_A10_AHB: + index = 0; + break; + case AW_A13_AHB: + DEVICE_LOCK(sc); + AHBCLK_READ(sc, &val); + DEVICE_UNLOCK(sc); + index = (val & A13_AHB_CLK_SRC_SEL) >> + A13_AHB_CLK_SRC_SEL_SHIFT; + break; + case AW_A31_AHB1: + DEVICE_LOCK(sc); + AHBCLK_READ(sc, &val); + DEVICE_UNLOCK(sc); + index = (val & A31_AHB1_CLK_SRC_SEL) >> + A31_AHB1_CLK_SRC_SEL_SHIFT; + break; + default: + return (ENXIO); + } + + clknode_init_parent_idx(clk, index); + return (0); +} + +static int +aw_ahbclk_recalc_freq(struct clknode *clk, uint64_t *freq) +{ + struct aw_ahbclk_sc *sc; + uint32_t val, src_sel, div, pre_div; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(sc); + AHBCLK_READ(sc, &val); + DEVICE_UNLOCK(sc); + + div = 1 << ((val & A10_AHB_CLK_DIV_RATIO) >> + A10_AHB_CLK_DIV_RATIO_SHIFT); + + switch (sc->type) { + case AW_A31_AHB1: + src_sel = (val & A31_AHB1_CLK_SRC_SEL) >> + A31_AHB1_CLK_SRC_SEL_SHIFT; + if (src_sel == A31_AHB1_CLK_SRC_SEL_PLL6) + pre_div = ((val & A31_AHB1_PRE_DIV) >> + A31_AHB1_PRE_DIV_SHIFT) + 1; + else + pre_div = 1; + break; + default: + pre_div = 1; + break; + } + + *freq = *freq / pre_div / div; + + return (0); +} + +static int +aw_ahbclk_set_mux(struct clknode *clk, int index) +{ + struct aw_ahbclk_sc *sc; + uint32_t val; + + sc = clknode_get_softc(clk); + + switch (sc->type) { + case AW_A10_AHB: + if (index != 0) + return (ERANGE); + break; + case AW_A13_AHB: + if (index < 0 || index > A13_AHB_CLK_SRC_SEL_MAX) + return (ERANGE); + DEVICE_LOCK(sc); + AHBCLK_READ(sc, &val); + val &= ~A13_AHB_CLK_SRC_SEL; + val |= (index << A13_AHB_CLK_SRC_SEL_SHIFT); + AHBCLK_WRITE(sc, val); + DEVICE_UNLOCK(sc); + break; + default: + return (ENXIO); + } + + return (0); +} + +static clknode_method_t aw_ahbclk_clknode_methods[] = { + /* Device interface */ + CLKNODEMETHOD(clknode_init, aw_ahbclk_init), + CLKNODEMETHOD(clknode_recalc_freq, aw_ahbclk_recalc_freq), + CLKNODEMETHOD(clknode_set_mux, aw_ahbclk_set_mux), + CLKNODEMETHOD_END +}; +DEFINE_CLASS_1(aw_ahbclk_clknode, aw_ahbclk_clknode_class, + aw_ahbclk_clknode_methods, sizeof(struct aw_ahbclk_sc), clknode_class); + +static int +aw_ahbclk_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Allwinner AHB Clock"); + return (BUS_PROBE_DEFAULT); +} + +static int +aw_ahbclk_attach(device_t dev) +{ + struct clknode_init_def def; + struct aw_ahbclk_sc *sc; + struct clkdom *clkdom; + struct clknode *clk; + clk_t clk_parent; + bus_addr_t paddr; + bus_size_t psize; + phandle_t node; + int error, ncells, i; + + node = ofw_bus_get_node(dev); + + if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) { + device_printf(dev, "cannot parse 'reg' property\n"); + return (ENXIO); + } + + error = ofw_bus_parse_xref_list_get_length(node, "clocks", + "#clock-cells", &ncells); + if (error != 0) { + device_printf(dev, "cannot get clock count\n"); + return (error); + } + + clkdom = clkdom_create(dev); + + memset(&def, 0, sizeof(def)); + def.id = 1; + def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, + M_WAITOK); + for (i = 0; i < ncells; i++) { + error = clk_get_by_ofw_index(dev, i, &clk_parent); + if (error != 0) { + device_printf(dev, "cannot get clock %d\n", i); + goto fail; + } + def.parent_names[i] = clk_get_name(clk_parent); + clk_release(clk_parent); + } + def.parent_cnt = ncells; + + error = clk_parse_ofw_clk_name(dev, node, &def.name); + if (error != 0) { + device_printf(dev, "cannot parse clock name\n"); + error = ENXIO; + goto fail; + } + + clk = clknode_create(clkdom, &aw_ahbclk_clknode_class, &def); + if (clk == NULL) { + device_printf(dev, "cannot create clknode\n"); + error = ENXIO; + goto fail; + } + sc = clknode_get_softc(clk); + sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; + sc->reg = paddr; + sc->clkdev = device_get_parent(dev); + + clknode_register(clkdom, clk); + + if (clkdom_finit(clkdom) != 0) { + device_printf(dev, "cannot finalize clkdom initialization\n"); + error = ENXIO; + goto fail; + } + + if (bootverbose) + clkdom_dump(clkdom); + + return (0); + +fail: + return (error); +} + +static device_method_t aw_ahbclk_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, aw_ahbclk_probe), + DEVMETHOD(device_attach, aw_ahbclk_attach), + + DEVMETHOD_END +}; + +static driver_t aw_ahbclk_driver = { + "aw_ahbclk", + aw_ahbclk_methods, + 0 +}; + +static devclass_t aw_ahbclk_devclass; + +EARLY_DRIVER_MODULE(aw_ahbclk, simplebus, aw_ahbclk_driver, + aw_ahbclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Property changes on: head/sys/arm/allwinner/clk/aw_ahbclk.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/allwinner/clk/aw_apbclk.c =================================================================== --- head/sys/arm/allwinner/clk/aw_apbclk.c (nonexistent) +++ head/sys/arm/allwinner/clk/aw_apbclk.c (revision 297627) @@ -0,0 +1,283 @@ +/*- + * Copyright (c) 2016 Jared McNeill + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Allwinner APB clock + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "clkdev_if.h" + +#define APB0_CLK_RATIO (0x3 << 8) +#define APB0_CLK_RATIO_SHIFT 8 +#define APB1_CLK_SRC_SEL (0x3 << 24) +#define APB1_CLK_SRC_SEL_SHIFT 24 +#define APB1_CLK_SRC_SEL_MAX 0x3 +#define APB1_CLK_RAT_N (0x3 << 16) +#define APB1_CLK_RAT_N_SHIFT 16 +#define APB1_CLK_RAT_M (0x1f << 0) +#define APB1_CLK_RAT_M_SHIFT 0 + +enum aw_apbclk_type { + AW_A10_APB0 = 1, + AW_A10_APB1, +}; + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun4i-a10-apb0-clk", AW_A10_APB0 }, + { "allwinner,sun4i-a10-apb1-clk", AW_A10_APB1 }, + { NULL, 0 } +}; + +struct aw_apbclk_sc { + device_t clkdev; + bus_addr_t reg; + enum aw_apbclk_type type; +}; + +#define APBCLK_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val)) +#define APBCLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val)) +#define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev) +#define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev) + +static int +aw_apbclk_init(struct clknode *clk, device_t dev) +{ + struct aw_apbclk_sc *sc; + uint32_t val, index; + + sc = clknode_get_softc(clk); + + switch (sc->type) { + case AW_A10_APB0: + index = 0; + break; + case AW_A10_APB1: + DEVICE_LOCK(sc); + APBCLK_READ(sc, &val); + DEVICE_UNLOCK(sc); + index = (val & APB1_CLK_SRC_SEL) >> APB1_CLK_SRC_SEL_SHIFT; + break; + default: + return (ENXIO); + } + + clknode_init_parent_idx(clk, index); + return (0); +} + +static int +aw_apbclk_recalc_freq(struct clknode *clk, uint64_t *freq) +{ + struct aw_apbclk_sc *sc; + uint32_t val, div, m, n; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(sc); + APBCLK_READ(sc, &val); + DEVICE_UNLOCK(sc); + + switch (sc->type) { + case AW_A10_APB0: + div = 1 << ((val & APB0_CLK_RATIO) >> APB0_CLK_RATIO_SHIFT); + if (div == 1) + div = 2; + *freq = *freq / div; + break; + case AW_A10_APB1: + n = 1 << ((val & APB1_CLK_RAT_N) >> APB1_CLK_RAT_N_SHIFT); + m = ((val & APB1_CLK_RAT_N) >> APB1_CLK_RAT_M_SHIFT) + 1; + *freq = *freq / n / m; + break; + default: + return (ENXIO); + } + + return (0); +} + +static int +aw_apbclk_set_mux(struct clknode *clk, int index) +{ + struct aw_apbclk_sc *sc; + uint32_t val; + + sc = clknode_get_softc(clk); + + if (sc->type != AW_A10_APB1) + return (ENXIO); + + if (index < 0 || index > APB1_CLK_SRC_SEL_MAX) + return (ERANGE); + + DEVICE_LOCK(sc); + APBCLK_READ(sc, &val); + val &= ~APB1_CLK_SRC_SEL; + val |= (index << APB1_CLK_SRC_SEL_SHIFT); + APBCLK_WRITE(sc, val); + DEVICE_UNLOCK(sc); + + return (0); +} + +static clknode_method_t aw_apbclk_clknode_methods[] = { + /* Device interface */ + CLKNODEMETHOD(clknode_init, aw_apbclk_init), + CLKNODEMETHOD(clknode_recalc_freq, aw_apbclk_recalc_freq), + CLKNODEMETHOD(clknode_set_mux, aw_apbclk_set_mux), + CLKNODEMETHOD_END +}; +DEFINE_CLASS_1(aw_apbclk_clknode, aw_apbclk_clknode_class, + aw_apbclk_clknode_methods, sizeof(struct aw_apbclk_sc), clknode_class); + +static int +aw_apbclk_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Allwinner APB Clock"); + return (BUS_PROBE_DEFAULT); +} + +static int +aw_apbclk_attach(device_t dev) +{ + struct clknode_init_def def; + struct aw_apbclk_sc *sc; + struct clkdom *clkdom; + struct clknode *clk; + clk_t clk_parent; + bus_addr_t paddr; + bus_size_t psize; + phandle_t node; + int error, ncells, i; + + node = ofw_bus_get_node(dev); + + if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) { + device_printf(dev, "cannot parse 'reg' property\n"); + return (ENXIO); + } + + error = ofw_bus_parse_xref_list_get_length(node, "clocks", + "#clock-cells", &ncells); + if (error != 0) { + device_printf(dev, "cannot get clock count\n"); + return (error); + } + + clkdom = clkdom_create(dev); + + memset(&def, 0, sizeof(def)); + error = clk_parse_ofw_clk_name(dev, node, &def.name); + if (error != 0) { + device_printf(dev, "cannot parse clock name\n"); + error = ENXIO; + goto fail; + } + def.id = 1; + def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK); + for (i = 0; i < ncells; i++) { + error = clk_get_by_ofw_index(dev, i, &clk_parent); + if (error != 0) { + device_printf(dev, "cannot get clock %d\n", i); + goto fail; + } + def.parent_names[i] = clk_get_name(clk_parent); + clk_release(clk_parent); + } + def.parent_cnt = ncells; + + clk = clknode_create(clkdom, &aw_apbclk_clknode_class, &def); + if (clk == NULL) { + device_printf(dev, "cannot create clknode\n"); + error = ENXIO; + goto fail; + } + + sc = clknode_get_softc(clk); + sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; + sc->reg = paddr; + sc->clkdev = device_get_parent(dev); + + clknode_register(clkdom, clk); + + if (clkdom_finit(clkdom) != 0) { + device_printf(dev, "cannot finalize clkdom initialization\n"); + error = ENXIO; + goto fail; + } + + if (bootverbose) + clkdom_dump(clkdom); + + return (0); + +fail: + return (error); +} + +static device_method_t aw_apbclk_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, aw_apbclk_probe), + DEVMETHOD(device_attach, aw_apbclk_attach), + + DEVMETHOD_END +}; + +static driver_t aw_apbclk_driver = { + "aw_apbclk", + aw_apbclk_methods, + 0 +}; + +static devclass_t aw_apbclk_devclass; + +EARLY_DRIVER_MODULE(aw_apbclk, simplebus, aw_apbclk_driver, + aw_apbclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Property changes on: head/sys/arm/allwinner/clk/aw_apbclk.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/allwinner/clk/aw_axiclk.c =================================================================== --- head/sys/arm/allwinner/clk/aw_axiclk.c (nonexistent) +++ head/sys/arm/allwinner/clk/aw_axiclk.c (revision 297627) @@ -0,0 +1,201 @@ +/*- + * Copyright (c) 2016 Jared McNeill + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Allwinner AXI clock + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "clkdev_if.h" + +#define AXI_CLK_DIV_RATIO (0x3 << 0) + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun4i-a10-axi-clk", 1 }, + { NULL, 0 } +}; + +struct aw_axiclk_sc { + device_t clkdev; + bus_addr_t reg; +}; + +#define AXICLK_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val)) +#define AXICLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val)) +#define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev) +#define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev) + +static int +aw_axiclk_init(struct clknode *clk, device_t dev) +{ + clknode_init_parent_idx(clk, 0); + return (0); +} + +static int +aw_axiclk_recalc_freq(struct clknode *clk, uint64_t *freq) +{ + struct aw_axiclk_sc *sc; + uint32_t val; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(sc); + AXICLK_READ(sc, &val); + DEVICE_UNLOCK(sc); + + *freq = *freq / ((val & AXI_CLK_DIV_RATIO) + 1); + + return (0); +} + +static clknode_method_t aw_axiclk_clknode_methods[] = { + /* Device interface */ + CLKNODEMETHOD(clknode_init, aw_axiclk_init), + CLKNODEMETHOD(clknode_recalc_freq, aw_axiclk_recalc_freq), + CLKNODEMETHOD_END +}; +DEFINE_CLASS_1(aw_axiclk_clknode, aw_axiclk_clknode_class, + aw_axiclk_clknode_methods, sizeof(struct aw_axiclk_sc), clknode_class); + +static int +aw_axiclk_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Allwinner AXI Clock"); + return (BUS_PROBE_DEFAULT); +} + +static int +aw_axiclk_attach(device_t dev) +{ + struct clknode_init_def def; + struct aw_axiclk_sc *sc; + struct clkdom *clkdom; + struct clknode *clk; + clk_t clk_parent; + bus_addr_t paddr; + bus_size_t psize; + phandle_t node; + int error; + + node = ofw_bus_get_node(dev); + + if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) { + device_printf(dev, "cannot parse 'reg' property\n"); + return (ENXIO); + } + + clkdom = clkdom_create(dev); + + error = clk_get_by_ofw_index(dev, 0, &clk_parent); + if (error != 0) { + device_printf(dev, "cannot parse clock parent\n"); + return (ENXIO); + } + + memset(&def, 0, sizeof(def)); + error = clk_parse_ofw_clk_name(dev, node, &def.name); + if (error != 0) { + device_printf(dev, "cannot parse clock name\n"); + error = ENXIO; + goto fail; + } + def.id = 1; + def.parent_names = malloc(sizeof(char *), M_OFWPROP, M_WAITOK); + def.parent_names[0] = clk_get_name(clk_parent); + def.parent_cnt = 1; + + clk = clknode_create(clkdom, &aw_axiclk_clknode_class, &def); + if (clk == NULL) { + device_printf(dev, "cannot create clknode\n"); + error = ENXIO; + goto fail; + } + + sc = clknode_get_softc(clk); + sc->reg = paddr; + sc->clkdev = device_get_parent(dev); + + clknode_register(clkdom, clk); + + if (clkdom_finit(clkdom) != 0) { + device_printf(dev, "cannot finalize clkdom initialization\n"); + error = ENXIO; + goto fail; + } + + if (bootverbose) + clkdom_dump(clkdom); + + return (0); + +fail: + return (error); +} + +static device_method_t aw_axiclk_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, aw_axiclk_probe), + DEVMETHOD(device_attach, aw_axiclk_attach), + + DEVMETHOD_END +}; + +static driver_t aw_axiclk_driver = { + "aw_axiclk", + aw_axiclk_methods, + 0 +}; + +static devclass_t aw_axiclk_devclass; + +EARLY_DRIVER_MODULE(aw_axiclk, simplebus, aw_axiclk_driver, + aw_axiclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Property changes on: head/sys/arm/allwinner/clk/aw_axiclk.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/allwinner/clk/aw_codecclk.c =================================================================== --- head/sys/arm/allwinner/clk/aw_codecclk.c (nonexistent) +++ head/sys/arm/allwinner/clk/aw_codecclk.c (revision 297627) @@ -0,0 +1,164 @@ +/*- + * Copyright (c) 2016 Jared McNeill + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Allwinner CODEC clock + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "clkdev_if.h" + +#define SCLK_GATING_SHIFT 31 + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun4i-a10-codec-clk", 1 }, + { NULL, 0 } +}; + +static int +aw_codecclk_create(device_t dev, bus_addr_t paddr, struct clkdom *clkdom, + const char *pclkname, const char *clkname, int index) +{ + const char *parent_names[1] = { pclkname }; + struct clk_gate_def def; + + memset(&def, 0, sizeof(def)); + def.clkdef.id = index; + def.clkdef.name = clkname; + def.clkdef.parent_names = parent_names; + def.clkdef.parent_cnt = 1; + def.offset = paddr; + def.shift = SCLK_GATING_SHIFT; + def.mask = 1; + def.on_value = 1; + def.off_value = 0; + + return (clknode_gate_register(clkdom, &def)); +} + +static int +aw_codecclk_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Allwinner CODEC Clock"); + return (BUS_PROBE_DEFAULT); +} + +static int +aw_codecclk_attach(device_t dev) +{ + struct clkdom *clkdom; + const char **names; + int nout, error; + uint32_t *indices; + clk_t clk_parent; + bus_addr_t paddr; + bus_size_t psize; + phandle_t node; + + node = ofw_bus_get_node(dev); + indices = NULL; + + if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) { + device_printf(dev, "cannot parse 'reg' property\n"); + return (ENXIO); + } + + clkdom = clkdom_create(dev); + + nout = clk_parse_ofw_out_names(dev, node, &names, &indices); + if (nout != 1) { + device_printf(dev, "must have exactly one output clock\n"); + error = ENOENT; + goto fail; + } + + error = clk_get_by_ofw_index(dev, 0, &clk_parent); + if (error != 0) { + device_printf(dev, "cannot parse clock parent\n"); + return (ENXIO); + } + + error = aw_codecclk_create(dev, paddr, clkdom, + clk_get_name(clk_parent), names[0], 1); + + if (clkdom_finit(clkdom) != 0) { + device_printf(dev, "cannot finalize clkdom initialization\n"); + error = ENXIO; + goto fail; + } + + if (bootverbose) + clkdom_dump(clkdom); + + return (0); + +fail: + return (error); +} + +static device_method_t aw_codecclk_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, aw_codecclk_probe), + DEVMETHOD(device_attach, aw_codecclk_attach), + + DEVMETHOD_END +}; + +static driver_t aw_codecclk_driver = { + "aw_codecclk", + aw_codecclk_methods, + 0 +}; + +static devclass_t aw_codecclk_devclass; + +EARLY_DRIVER_MODULE(aw_codecclk, simplebus, aw_codecclk_driver, + aw_codecclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Property changes on: head/sys/arm/allwinner/clk/aw_codecclk.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/allwinner/clk/aw_cpuclk.c =================================================================== --- head/sys/arm/allwinner/clk/aw_cpuclk.c (nonexistent) +++ head/sys/arm/allwinner/clk/aw_cpuclk.c (revision 297627) @@ -0,0 +1,161 @@ +/*- + * Copyright (c) 2016 Jared McNeill + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Allwinner CPU clock + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#define CPU_CLK_SRC_SEL_WIDTH 2 +#define CPU_CLK_SRC_SEL_SHIFT 16 + +static int +aw_cpuclk_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-cpu-clk")) + return (ENXIO); + + device_set_desc(dev, "Allwinner CPU Clock"); + return (BUS_PROBE_DEFAULT); +} + +static int +aw_cpuclk_attach(device_t dev) +{ + struct clk_mux_def def; + struct clkdom *clkdom; + bus_addr_t paddr; + bus_size_t psize; + phandle_t node; + int error, ncells, i; + clk_t clk; + + node = ofw_bus_get_node(dev); + + if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) { + device_printf(dev, "cannot parse 'reg' property\n"); + return (ENXIO); + } + + error = ofw_bus_parse_xref_list_get_length(node, "clocks", + "#clock-cells", &ncells); + if (error != 0) { + device_printf(dev, "cannot get clock count\n"); + return (error); + } + + clkdom = clkdom_create(dev); + + memset(&def, 0, sizeof(def)); + def.clkdef.id = 1; + def.clkdef.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, + M_WAITOK); + for (i = 0; i < ncells; i++) { + error = clk_get_by_ofw_index(dev, i, &clk); + if (error != 0) { + device_printf(dev, "cannot get clock %d\n", i); + goto fail; + } + def.clkdef.parent_names[i] = clk_get_name(clk); + clk_release(clk); + } + def.clkdef.parent_cnt = ncells; + def.offset = paddr; + def.shift = CPU_CLK_SRC_SEL_SHIFT; + def.width = CPU_CLK_SRC_SEL_WIDTH; + + error = clk_parse_ofw_clk_name(dev, node, &def.clkdef.name); + if (error != 0) { + device_printf(dev, "cannot parse clock name\n"); + error = ENXIO; + goto fail; + } + + error = clknode_mux_register(clkdom, &def); + if (error != 0) { + device_printf(dev, "cannot register mux clock\n"); + error = ENXIO; + goto fail; + } + + if (clkdom_finit(clkdom) != 0) { + device_printf(dev, "cannot finalize clkdom initialization\n"); + error = ENXIO; + goto fail; + } + + free(__DECONST(char *, def.clkdef.parent_names), M_OFWPROP); + free(__DECONST(char *, def.clkdef.name), M_OFWPROP); + + if (bootverbose) + clkdom_dump(clkdom); + + return (0); + +fail: + free(__DECONST(char *, def.clkdef.name), M_OFWPROP); + return (error); +} + +static device_method_t aw_cpuclk_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, aw_cpuclk_probe), + DEVMETHOD(device_attach, aw_cpuclk_attach), + + DEVMETHOD_END +}; + +static driver_t aw_cpuclk_driver = { + "aw_cpuclk", + aw_cpuclk_methods, + 0 +}; + +static devclass_t aw_cpuclk_devclass; + +EARLY_DRIVER_MODULE(aw_cpuclk, simplebus, aw_cpuclk_driver, + aw_cpuclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Property changes on: head/sys/arm/allwinner/clk/aw_cpuclk.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/allwinner/clk/aw_debeclk.c =================================================================== --- head/sys/arm/allwinner/clk/aw_debeclk.c (nonexistent) +++ head/sys/arm/allwinner/clk/aw_debeclk.c (revision 297627) @@ -0,0 +1,351 @@ +/*- + * Copyright (c) 2016 Jared McNeill + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Allwinner display backend clocks + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "clkdev_if.h" +#include "hwreset_if.h" + +#define SCLK_GATING (1 << 31) +#define BE_RST (1 << 30) +#define CLK_SRC_SEL (0x3 << 24) +#define CLK_SRC_SEL_SHIFT 24 +#define CLK_SRC_SEL_MAX 2 +#define CLK_SRC_SEL_PLL3 0 +#define CLK_SRC_SEL_PLL7 1 +#define CLK_SRC_SEL_PLL5 2 +#define CLK_RATIO_M (0xf << 0) +#define CLK_RATIO_M_SHIFT 0 +#define CLK_RATIO_M_MAX 0xf + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun4i-a10-de-be-clk", 1 }, + { NULL, 0 } +}; + +struct aw_debeclk_softc { + device_t clkdev; + bus_addr_t reg; +}; + +#define DEBECLK_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val)) +#define DEBECLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val)) +#define DEBECLK_MODIFY(sc, clr, set) \ + CLKDEV_MODIFY_4((sc)->clkdev, (sc)->reg, (clr), (set)) +#define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev) +#define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev) + +static int +aw_debeclk_hwreset_assert(device_t dev, intptr_t id, bool value) +{ + struct aw_debeclk_softc *sc; + int error; + + sc = device_get_softc(dev); + + DEVICE_LOCK(sc); + error = DEBECLK_MODIFY(sc, BE_RST, value ? 0 : BE_RST); + DEVICE_UNLOCK(sc); + + return (error); +} + +static int +aw_debeclk_hwreset_is_asserted(device_t dev, intptr_t id, bool *value) +{ + struct aw_debeclk_softc *sc; + uint32_t val; + int error; + + sc = device_get_softc(dev); + + DEVICE_LOCK(sc); + error = DEBECLK_READ(sc, &val); + DEVICE_UNLOCK(sc); + + if (error) + return (error); + + *value = (val & BE_RST) != 0 ? false : true; + + return (0); +} + +static int +aw_debeclk_init(struct clknode *clk, device_t dev) +{ + struct aw_debeclk_softc *sc; + uint32_t val, index; + + sc = clknode_get_softc(clk); + + /* Set BE source to PLL5 (DDR external peripheral clock) */ + index = CLK_SRC_SEL_PLL5; + + DEVICE_LOCK(sc); + DEBECLK_READ(sc, &val); + val &= ~CLK_SRC_SEL; + val |= (index << CLK_SRC_SEL_SHIFT); + DEBECLK_WRITE(sc, val); + DEVICE_UNLOCK(sc); + + clknode_init_parent_idx(clk, index); + return (0); +} + +static int +aw_debeclk_set_mux(struct clknode *clk, int index) +{ + struct aw_debeclk_softc *sc; + uint32_t val; + + sc = clknode_get_softc(clk); + + if (index < 0 || index > CLK_SRC_SEL_MAX) + return (ERANGE); + + DEVICE_LOCK(sc); + DEBECLK_READ(sc, &val); + val &= ~CLK_SRC_SEL; + val |= (index << CLK_SRC_SEL_SHIFT); + DEBECLK_WRITE(sc, val); + DEVICE_UNLOCK(sc); + + return (0); +} + +static int +aw_debeclk_set_gate(struct clknode *clk, bool enable) +{ + struct aw_debeclk_softc *sc; + uint32_t val; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(sc); + DEBECLK_READ(sc, &val); + if (enable) + val |= SCLK_GATING; + else + val &= ~SCLK_GATING; + DEBECLK_WRITE(sc, val); + DEVICE_UNLOCK(sc); + + return (0); +} + +static int +aw_debeclk_recalc_freq(struct clknode *clk, uint64_t *freq) +{ + struct aw_debeclk_softc *sc; + uint32_t val, m; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(sc); + DEBECLK_READ(sc, &val); + DEVICE_UNLOCK(sc); + + m = ((val & CLK_RATIO_M) >> CLK_RATIO_M_SHIFT) + 1; + + *freq = *freq / m; + + return (0); +} + +static int +aw_debeclk_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout, + int flags, int *stop) +{ + struct aw_debeclk_softc *sc; + uint32_t val, m; + + sc = clknode_get_softc(clk); + + m = howmany(fin, *fout) - 1; + + DEVICE_LOCK(sc); + DEBECLK_READ(sc, &val); + val &= ~CLK_RATIO_M; + val |= (m << CLK_RATIO_M_SHIFT); + DEBECLK_WRITE(sc, val); + DEVICE_UNLOCK(sc); + + *fout = fin / (m + 1); + *stop = 1; + + return (0); +} + +static clknode_method_t aw_debeclk_clknode_methods[] = { + /* Device interface */ + CLKNODEMETHOD(clknode_init, aw_debeclk_init), + CLKNODEMETHOD(clknode_set_gate, aw_debeclk_set_gate), + CLKNODEMETHOD(clknode_set_mux, aw_debeclk_set_mux), + CLKNODEMETHOD(clknode_recalc_freq, aw_debeclk_recalc_freq), + CLKNODEMETHOD(clknode_set_freq, aw_debeclk_set_freq), + CLKNODEMETHOD_END +}; +DEFINE_CLASS_1(aw_debeclk_clknode, aw_debeclk_clknode_class, + aw_debeclk_clknode_methods, sizeof(struct aw_debeclk_softc), clknode_class); + +static int +aw_debeclk_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Allwinner Display Engine Backend Clock"); + return (BUS_PROBE_DEFAULT); +} + +static int +aw_debeclk_attach(device_t dev) +{ + struct clknode_init_def def; + struct aw_debeclk_softc *sc, *clk_sc; + struct clkdom *clkdom; + struct clknode *clk; + clk_t clk_parent; + bus_size_t psize; + phandle_t node; + int error, ncells, i; + + sc = device_get_softc(dev); + sc->clkdev = device_get_parent(dev); + node = ofw_bus_get_node(dev); + + if (ofw_reg_to_paddr(node, 0, &sc->reg, &psize, NULL) != 0) { + device_printf(dev, "cannot parse 'reg' property\n"); + return (ENXIO); + } + + error = ofw_bus_parse_xref_list_get_length(node, "clocks", + "#clock-cells", &ncells); + if (error != 0) { + device_printf(dev, "cannot get clock count\n"); + return (error); + } + + clkdom = clkdom_create(dev); + + memset(&def, 0, sizeof(def)); + error = clk_parse_ofw_clk_name(dev, node, &def.name); + if (error != 0) { + device_printf(dev, "cannot parse clock name\n"); + error = ENXIO; + goto fail; + } + def.id = 1; + def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK); + for (i = 0; i < ncells; i++) { + error = clk_get_by_ofw_index(dev, i, &clk_parent); + if (error != 0) { + device_printf(dev, "cannot get clock %d\n", i); + goto fail; + } + def.parent_names[i] = clk_get_name(clk_parent); + clk_release(clk_parent); + } + def.parent_cnt = ncells; + + clk = clknode_create(clkdom, &aw_debeclk_clknode_class, &def); + if (clk == NULL) { + device_printf(dev, "cannot create clknode\n"); + error = ENXIO; + goto fail; + } + + clk_sc = clknode_get_softc(clk); + clk_sc->reg = sc->reg; + clk_sc->clkdev = device_get_parent(dev); + + clknode_register(clkdom, clk); + + if (clkdom_finit(clkdom) != 0) { + device_printf(dev, "cannot finalize clkdom initialization\n"); + error = ENXIO; + goto fail; + } + + if (bootverbose) + clkdom_dump(clkdom); + + hwreset_register_ofw_provider(dev); + + return (0); + +fail: + return (error); +} + +static device_method_t aw_debeclk_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, aw_debeclk_probe), + DEVMETHOD(device_attach, aw_debeclk_attach), + + /* Reset interface */ + DEVMETHOD(hwreset_assert, aw_debeclk_hwreset_assert), + DEVMETHOD(hwreset_is_asserted, aw_debeclk_hwreset_is_asserted), + + DEVMETHOD_END +}; + +static driver_t aw_debeclk_driver = { + "aw_debeclk", + aw_debeclk_methods, + sizeof(struct aw_debeclk_softc) +}; + +static devclass_t aw_debeclk_devclass; + +EARLY_DRIVER_MODULE(aw_debeclk, simplebus, aw_debeclk_driver, + aw_debeclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Property changes on: head/sys/arm/allwinner/clk/aw_debeclk.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/allwinner/clk/aw_gate.c =================================================================== --- head/sys/arm/allwinner/clk/aw_gate.c (nonexistent) +++ head/sys/arm/allwinner/clk/aw_gate.c (revision 297627) @@ -0,0 +1,198 @@ +/*- + * Copyright (c) 2016 Jared McNeill + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Allwinner clock gates + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#define GATE_OFFSET(index) ((index / 32) * 4) +#define GATE_SHIFT(index) (index % 32) + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun4i-a10-dram-gates-clk", + (uintptr_t)"Allwinner DRAM Clock Gates" }, + { "allwinner,sun4i-a10-ahb-gates-clk", + (uintptr_t)"Allwinner AHB Clock Gates" }, + { "allwinner,sun4i-a10-apb0-gates-clk", + (uintptr_t)"Allwinner APB0 Clock Gates" }, + { "allwinner,sun4i-a10-apb1-gates-clk", + (uintptr_t)"Allwinner APB1 Clock Gates" }, + + { "allwinner,sun7i-a20-ahb-gates-clk", + (uintptr_t)"Allwinner AHB Clock Gates" }, + { "allwinner,sun7i-a20-apb0-gates-clk", + (uintptr_t)"Allwinner APB0 Clock Gates" }, + { "allwinner,sun7i-a20-apb1-gates-clk", + (uintptr_t)"Allwinner APB1 Clock Gates" }, + + { "allwinner,sun6i-a31-ahb1-gates-clk", + (uintptr_t)"Allwinner AHB1 Clock Gates" }, + { "allwinner,sun6i-a31-apb0-gates-clk", + (uintptr_t)"Allwinner APB0 Clock Gates" }, + { "allwinner,sun6i-a31-apb1-gates-clk", + (uintptr_t)"Allwinner APB1 Clock Gates" }, + { "allwinner,sun6i-a31-apb2-gates-clk", + (uintptr_t)"Allwinner APB2 Clock Gates" }, + + { NULL, 0 } +}; + +static int +aw_gate_create(device_t dev, bus_addr_t paddr, struct clkdom *clkdom, + const char *pclkname, const char *clkname, int index) +{ + const char *parent_names[1] = { pclkname }; + struct clk_gate_def def; + + memset(&def, 0, sizeof(def)); + def.clkdef.id = index; + def.clkdef.name = clkname; + def.clkdef.parent_names = parent_names; + def.clkdef.parent_cnt = 1; + def.offset = paddr + GATE_OFFSET(index); + def.shift = GATE_SHIFT(index); + def.mask = 1; + def.on_value = 1; + def.off_value = 0; + + return (clknode_gate_register(clkdom, &def)); +} + +static int +aw_gate_probe(device_t dev) +{ + const char *d; + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + d = (const char *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; + if (d == NULL) + return (ENXIO); + + device_set_desc(dev, d); + return (BUS_PROBE_DEFAULT); +} + +static int +aw_gate_attach(device_t dev) +{ + struct clkdom *clkdom; + const char **names; + int index, nout, error; + uint32_t *indices; + clk_t clk_parent; + bus_addr_t paddr; + bus_size_t psize; + phandle_t node; + + node = ofw_bus_get_node(dev); + indices = NULL; + + if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) { + device_printf(dev, "cannot parse 'reg' property\n"); + return (ENXIO); + } + + clkdom = clkdom_create(dev); + + nout = clk_parse_ofw_out_names(dev, node, &names, &indices); + if (nout == 0) { + device_printf(dev, "no clock outputs found\n"); + error = ENOENT; + goto fail; + } + if (indices == NULL) { + device_printf(dev, "no clock-indices property\n"); + error = ENXIO; + goto fail; + } + + error = clk_get_by_ofw_index(dev, 0, &clk_parent); + if (error != 0) { + device_printf(dev, "cannot parse clock parent\n"); + return (ENXIO); + } + + for (index = 0; index < nout; index++) { + error = aw_gate_create(dev, paddr, clkdom, + clk_get_name(clk_parent), names[index], indices[index]); + if (error) + goto fail; + } + + if (clkdom_finit(clkdom) != 0) { + device_printf(dev, "cannot finalize clkdom initialization\n"); + error = ENXIO; + goto fail; + } + + if (bootverbose) + clkdom_dump(clkdom); + + return (0); + +fail: + return (error); +} + +static device_method_t aw_gate_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, aw_gate_probe), + DEVMETHOD(device_attach, aw_gate_attach), + + DEVMETHOD_END +}; + +static driver_t aw_gate_driver = { + "aw_gate", + aw_gate_methods, + 0 +}; + +static devclass_t aw_gate_devclass; + +EARLY_DRIVER_MODULE(aw_gate, simplebus, aw_gate_driver, + aw_gate_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Property changes on: head/sys/arm/allwinner/clk/aw_gate.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/allwinner/clk/aw_gmacclk.c =================================================================== --- head/sys/arm/allwinner/clk/aw_gmacclk.c (nonexistent) +++ head/sys/arm/allwinner/clk/aw_gmacclk.c (revision 297627) @@ -0,0 +1,259 @@ +/*- + * Copyright (c) 2016 Jared McNeill + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Allwinner GMAC clock + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "clkdev_if.h" + +#define GMAC_CLK_PIT (0x1 << 2) +#define GMAC_CLK_PIT_SHIFT 2 +#define GMAC_CLK_PIT_MII 0 +#define GMAC_CLK_PIT_RGMII 1 +#define GMAC_CLK_SRC (0x3 << 0) +#define GMAC_CLK_SRC_SHIFT 0 +#define GMAC_CLK_SRC_MII 0 +#define GMAC_CLK_SRC_EXT_RGMII 1 +#define GMAC_CLK_SRC_RGMII 2 + +#define CLK_IDX_MII 0 +#define CLK_IDX_RGMII 1 +#define CLK_IDX_COUNT 2 + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun7i-a20-gmac-clk", 1 }, + { NULL, 0 } +}; + +struct aw_gmacclk_sc { + device_t clkdev; + bus_addr_t reg; +}; + +#define GMACCLK_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val)) +#define GMACCLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val)) +#define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev) +#define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev) + +static int +aw_gmacclk_init(struct clknode *clk, device_t dev) +{ + struct aw_gmacclk_sc *sc; + uint32_t val, index; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(sc); + GMACCLK_READ(sc, &val); + DEVICE_UNLOCK(sc); + + switch ((val & GMAC_CLK_SRC) >> GMAC_CLK_SRC_SHIFT) { + case GMAC_CLK_SRC_MII: + index = CLK_IDX_MII; + break; + case GMAC_CLK_SRC_RGMII: + index = CLK_IDX_RGMII; + break; + default: + return (ENXIO); + } + + clknode_init_parent_idx(clk, index); + return (0); +} + +static int +aw_gmacclk_set_mux(struct clknode *clk, int index) +{ + struct aw_gmacclk_sc *sc; + uint32_t val, clk_src, pit; + int error; + + sc = clknode_get_softc(clk); + error = 0; + + switch (index) { + case CLK_IDX_MII: + clk_src = GMAC_CLK_SRC_MII; + pit = GMAC_CLK_PIT_MII; + break; + case CLK_IDX_RGMII: + clk_src = GMAC_CLK_SRC_RGMII; + pit = GMAC_CLK_PIT_RGMII; + break; + default: + return (ENXIO); + } + + DEVICE_LOCK(sc); + GMACCLK_READ(sc, &val); + val &= ~(GMAC_CLK_SRC | GMAC_CLK_PIT); + val |= (clk_src << GMAC_CLK_SRC_SHIFT); + val |= (pit << GMAC_CLK_PIT_SHIFT); + GMACCLK_WRITE(sc, val); + DEVICE_UNLOCK(sc); + + return (0); +} + +static clknode_method_t aw_gmacclk_clknode_methods[] = { + /* Device interface */ + CLKNODEMETHOD(clknode_init, aw_gmacclk_init), + CLKNODEMETHOD(clknode_set_mux, aw_gmacclk_set_mux), + CLKNODEMETHOD_END +}; +DEFINE_CLASS_1(aw_gmacclk_clknode, aw_gmacclk_clknode_class, + aw_gmacclk_clknode_methods, sizeof(struct aw_gmacclk_sc), clknode_class); + +static int +aw_gmacclk_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Allwinner Module Clock"); + return (BUS_PROBE_DEFAULT); +} + +static int +aw_gmacclk_attach(device_t dev) +{ + struct clknode_init_def def; + struct aw_gmacclk_sc *sc; + struct clkdom *clkdom; + struct clknode *clk; + clk_t clk_parent; + bus_addr_t paddr; + bus_size_t psize; + phandle_t node; + int error, ncells, i; + + node = ofw_bus_get_node(dev); + + if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) { + device_printf(dev, "cannot parse 'reg' property\n"); + return (ENXIO); + } + + error = ofw_bus_parse_xref_list_get_length(node, "clocks", + "#clock-cells", &ncells); + if (error != 0 || ncells != CLK_IDX_COUNT) { + device_printf(dev, "couldn't find parent clocks\n"); + return (ENXIO); + } + + clkdom = clkdom_create(dev); + + memset(&def, 0, sizeof(def)); + error = clk_parse_ofw_clk_name(dev, node, &def.name); + if (error != 0) { + device_printf(dev, "cannot parse clock name\n"); + error = ENXIO; + goto fail; + } + def.id = 1; + def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK); + for (i = 0; i < ncells; i++) { + error = clk_get_by_ofw_index(dev, i, &clk_parent); + if (error != 0) { + device_printf(dev, "cannot get clock %d\n", error); + goto fail; + } + def.parent_names[i] = clk_get_name(clk_parent); + clk_release(clk_parent); + } + def.parent_cnt = ncells; + + clk = clknode_create(clkdom, &aw_gmacclk_clknode_class, &def); + if (clk == NULL) { + device_printf(dev, "cannot create clknode\n"); + error = ENXIO; + goto fail; + } + + sc = clknode_get_softc(clk); + sc->reg = paddr; + sc->clkdev = device_get_parent(dev); + + clknode_register(clkdom, clk); + + if (clkdom_finit(clkdom) != 0) { + device_printf(dev, "cannot finalize clkdom initialization\n"); + error = ENXIO; + goto fail; + } + + if (bootverbose) + clkdom_dump(clkdom); + + return (0); + +fail: + return (error); +} + +static device_method_t aw_gmacclk_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, aw_gmacclk_probe), + DEVMETHOD(device_attach, aw_gmacclk_attach), + + DEVMETHOD_END +}; + +static driver_t aw_gmacclk_driver = { + "aw_gmacclk", + aw_gmacclk_methods, + 0 +}; + +static devclass_t aw_gmacclk_devclass; + +EARLY_DRIVER_MODULE(aw_gmacclk, simplebus, aw_gmacclk_driver, + aw_gmacclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Property changes on: head/sys/arm/allwinner/clk/aw_gmacclk.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/allwinner/clk/aw_hdmiclk.c =================================================================== --- head/sys/arm/allwinner/clk/aw_hdmiclk.c (nonexistent) +++ head/sys/arm/allwinner/clk/aw_hdmiclk.c (revision 297627) @@ -0,0 +1,315 @@ +/*- + * Copyright (c) 2016 Jared McNeill + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Allwinner HDMI clock + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "clkdev_if.h" + +#define SCLK_GATING (1 << 31) +#define CLK_SRC_SEL (0x3 << 24) +#define CLK_SRC_SEL_SHIFT 24 +#define CLK_SRC_SEL_MAX 0x3 +#define CLK_RATIO_N (0x3 << 16) +#define CLK_RATIO_N_SHIFT 16 +#define CLK_RATIO_N_MAX 0x3 +#define CLK_RATIO_M (0x1f << 0) +#define CLK_RATIO_M_SHIFT 0 +#define CLK_RATIO_M_MAX 0x1f + +#define CLK_IDX_PLL3_1X 0 + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun4i-a10-hdmi-clk", 1 }, + { NULL, 0 } +}; + +struct aw_hdmiclk_sc { + device_t clkdev; + bus_addr_t reg; +}; + +#define HDMICLK_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val)) +#define HDMICLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val)) +#define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev) +#define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev) + +static int +aw_hdmiclk_init(struct clknode *clk, device_t dev) +{ + struct aw_hdmiclk_sc *sc; + uint32_t val, index; + + sc = clknode_get_softc(clk); + + /* Select PLL3(1X) clock source */ + index = CLK_IDX_PLL3_1X; + + DEVICE_LOCK(sc); + HDMICLK_READ(sc, &val); + val &= ~CLK_SRC_SEL; + val |= (index << CLK_SRC_SEL_SHIFT); + HDMICLK_WRITE(sc, val); + DEVICE_UNLOCK(sc); + + clknode_init_parent_idx(clk, index); + return (0); +} + +static int +aw_hdmiclk_set_mux(struct clknode *clk, int index) +{ + struct aw_hdmiclk_sc *sc; + uint32_t val; + + sc = clknode_get_softc(clk); + + if (index < 0 || index > CLK_SRC_SEL_MAX) + return (ERANGE); + + DEVICE_LOCK(sc); + HDMICLK_READ(sc, &val); + val &= ~CLK_SRC_SEL; + val |= (index << CLK_SRC_SEL_SHIFT); + HDMICLK_WRITE(sc, val); + DEVICE_UNLOCK(sc); + + return (0); +} + +static int +aw_hdmiclk_set_gate(struct clknode *clk, bool enable) +{ + struct aw_hdmiclk_sc *sc; + uint32_t val; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(sc); + HDMICLK_READ(sc, &val); + if (enable) + val |= SCLK_GATING; + else + val &= ~SCLK_GATING; + HDMICLK_WRITE(sc, val); + DEVICE_UNLOCK(sc); + + return (0); +} + +static int +aw_hdmiclk_recalc_freq(struct clknode *clk, uint64_t *freq) +{ + struct aw_hdmiclk_sc *sc; + uint32_t val, m, n; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(sc); + HDMICLK_READ(sc, &val); + DEVICE_UNLOCK(sc); + + n = 1 << ((val & CLK_RATIO_N) >> CLK_RATIO_N_SHIFT); + m = ((val & CLK_RATIO_M) >> CLK_RATIO_M_SHIFT) + 1; + + *freq = *freq / n / m; + + return (0); +} + +static int +aw_hdmiclk_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout, + int flags, int *stop) +{ + struct aw_hdmiclk_sc *sc; + uint32_t val, m, n, best_m, best_n; + uint64_t cur_freq; + int64_t best_diff, cur_diff; + + sc = clknode_get_softc(clk); + best_n = best_m = 0; + best_diff = (int64_t)*fout; + + for (n = 0; n <= CLK_RATIO_N_MAX; n++) + for (m = 0; m <= CLK_RATIO_M_MAX; m++) { + cur_freq = fin / (1 << n) / (m + 1); + cur_diff = (int64_t)*fout - cur_freq; + if (cur_diff >= 0 && cur_diff < best_diff) { + best_diff = cur_diff; + best_m = m; + best_n = n; + } + } + + if (best_diff == (int64_t)*fout) + return (ERANGE); + + DEVICE_LOCK(sc); + HDMICLK_READ(sc, &val); + val &= ~(CLK_RATIO_N | CLK_RATIO_M); + val |= (best_n << CLK_RATIO_N_SHIFT); + val |= (best_m << CLK_RATIO_M_SHIFT); + HDMICLK_WRITE(sc, val); + DEVICE_UNLOCK(sc); + + *fout = fin / (1 << best_n) / (best_m + 1); + *stop = 1; + + return (0); +} + +static clknode_method_t aw_hdmiclk_clknode_methods[] = { + /* Device interface */ + CLKNODEMETHOD(clknode_init, aw_hdmiclk_init), + CLKNODEMETHOD(clknode_set_gate, aw_hdmiclk_set_gate), + CLKNODEMETHOD(clknode_set_mux, aw_hdmiclk_set_mux), + CLKNODEMETHOD(clknode_recalc_freq, aw_hdmiclk_recalc_freq), + CLKNODEMETHOD(clknode_set_freq, aw_hdmiclk_set_freq), + CLKNODEMETHOD_END +}; +DEFINE_CLASS_1(aw_hdmiclk_clknode, aw_hdmiclk_clknode_class, + aw_hdmiclk_clknode_methods, sizeof(struct aw_hdmiclk_sc), clknode_class); + +static int +aw_hdmiclk_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Allwinner HDMI Clock"); + return (BUS_PROBE_DEFAULT); +} + +static int +aw_hdmiclk_attach(device_t dev) +{ + struct clknode_init_def def; + struct aw_hdmiclk_sc *sc; + struct clkdom *clkdom; + struct clknode *clk; + clk_t clk_parent; + bus_addr_t paddr; + bus_size_t psize; + phandle_t node; + int error; + + node = ofw_bus_get_node(dev); + + if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) { + device_printf(dev, "cannot parse 'reg' property\n"); + return (ENXIO); + } + + clkdom = clkdom_create(dev); + + error = clk_get_by_ofw_index(dev, 0, &clk_parent); + if (error != 0) { + device_printf(dev, "cannot parse clock parent\n"); + return (ENXIO); + } + + memset(&def, 0, sizeof(def)); + error = clk_parse_ofw_clk_name(dev, node, &def.name); + if (error != 0) { + device_printf(dev, "cannot parse clock name\n"); + error = ENXIO; + goto fail; + } + def.id = 1; + def.parent_names = malloc(sizeof(char *), M_OFWPROP, M_WAITOK); + def.parent_names[0] = clk_get_name(clk_parent); + def.parent_cnt = 1; + + clk = clknode_create(clkdom, &aw_hdmiclk_clknode_class, &def); + if (clk == NULL) { + device_printf(dev, "cannot create clknode\n"); + error = ENXIO; + goto fail; + } + + sc = clknode_get_softc(clk); + sc->reg = paddr; + sc->clkdev = device_get_parent(dev); + + clknode_register(clkdom, clk); + + if (clkdom_finit(clkdom) != 0) { + device_printf(dev, "cannot finalize clkdom initialization\n"); + error = ENXIO; + goto fail; + } + + if (bootverbose) + clkdom_dump(clkdom); + + return (0); + +fail: + return (error); +} + +static device_method_t aw_hdmiclk_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, aw_hdmiclk_probe), + DEVMETHOD(device_attach, aw_hdmiclk_attach), + + DEVMETHOD_END +}; + +static driver_t aw_hdmiclk_driver = { + "aw_hdmiclk", + aw_hdmiclk_methods, + 0 +}; + +static devclass_t aw_hdmiclk_devclass; + +EARLY_DRIVER_MODULE(aw_hdmiclk, simplebus, aw_hdmiclk_driver, + aw_hdmiclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Property changes on: head/sys/arm/allwinner/clk/aw_hdmiclk.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/allwinner/clk/aw_lcdclk.c =================================================================== --- head/sys/arm/allwinner/clk/aw_lcdclk.c (nonexistent) +++ head/sys/arm/allwinner/clk/aw_lcdclk.c (revision 297627) @@ -0,0 +1,560 @@ +/*- + * Copyright (c) 2016 Jared McNeill + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Allwinner LCD clocks + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "clkdev_if.h" +#include "hwreset_if.h" + +/* CH0 */ +#define CH0_SCLK_GATING (1 << 31) +#define CH0_LCD_RST (1 << 30) +#define CH0_CLK_SRC_SEL (0x3 << 24) +#define CH0_CLK_SRC_SEL_SHIFT 24 +#define CH0_CLK_SRC_SEL_PLL3_1X 0 +#define CH0_CLK_SRC_SEL_PLL7_1X 1 +#define CH0_CLK_SRC_SEL_PLL3_2X 2 +#define CH0_CLK_SRC_SEL_PLL6 3 + +/* CH1 */ +#define CH1_SCLK2_GATING (1 << 31) +#define CH1_SCLK2_SEL (0x3 << 24) +#define CH1_SCLK2_SEL_SHIFT 24 +#define CH1_SCLK2_SEL_PLL3_1X 0 +#define CH1_SCLK2_SEL_PLL7_1X 1 +#define CH1_SCLK2_SEL_PLL3_2X 2 +#define CH1_SCLK2_SEL_PLL7_2X 3 +#define CH1_SCLK1_GATING (1 << 15) +#define CH1_SCLK1_SEL (0x1 << 11) +#define CH1_SCLK1_SEL_SHIFT 11 +#define CH1_SCLK1_SEL_SCLK2 0 +#define CH1_SCLK1_SEL_SCLK2_DIV2 1 +#define CH1_CLK_DIV_RATIO_M (0x1f << 0) +#define CH1_CLK_DIV_RATIO_M_SHIFT 0 + +#define TCON_PLLREF 3000000ULL +#define TCON_PLL_M_MIN 1 +#define TCON_PLL_M_MAX 15 +#define TCON_PLL_N_MIN 9 +#define TCON_PLL_N_MAX 127 + +#define CLK_IDX_CH1_SCLK1 0 +#define CLK_IDX_CH1_SCLK2 1 + +#define CLK_IDX_ + +enum aw_lcdclk_type { + AW_LCD_CH0 = 1, + AW_LCD_CH1, +}; + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun4i-a10-lcd-ch0-clk", AW_LCD_CH0 }, + { "allwinner,sun4i-a10-lcd-ch1-clk", AW_LCD_CH1 }, + { NULL, 0 } +}; + +struct aw_lcdclk_softc { + enum aw_lcdclk_type type; + device_t clkdev; + bus_addr_t reg; + int id; +}; + +#define LCDCLK_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val)) +#define LCDCLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val)) +#define LCDCLK_MODIFY(sc, clr, set) \ + CLKDEV_MODIFY_4((sc)->clkdev, (sc)->reg, (clr), (set)) +#define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev) +#define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev) + +static int +aw_lcdclk_hwreset_assert(device_t dev, intptr_t id, bool value) +{ + struct aw_lcdclk_softc *sc; + int error; + + sc = device_get_softc(dev); + + if (sc->type != AW_LCD_CH0) + return (ENXIO); + + DEVICE_LOCK(sc); + error = LCDCLK_MODIFY(sc, CH0_LCD_RST, value ? 0 : CH0_LCD_RST); + DEVICE_UNLOCK(sc); + + return (error); +} + +static int +aw_lcdclk_hwreset_is_asserted(device_t dev, intptr_t id, bool *value) +{ + struct aw_lcdclk_softc *sc; + uint32_t val; + int error; + + sc = device_get_softc(dev); + + if (sc->type != AW_LCD_CH0) + return (ENXIO); + + DEVICE_LOCK(sc); + error = LCDCLK_READ(sc, &val); + DEVICE_UNLOCK(sc); + + if (error) + return (error); + + *value = (val & CH0_LCD_RST) != 0 ? false : true; + + return (0); +} + +static int +aw_lcdclk_init(struct clknode *clk, device_t dev) +{ + struct aw_lcdclk_softc *sc; + uint32_t val, index; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(sc); + LCDCLK_READ(sc, &val); + DEVICE_UNLOCK(sc); + + switch (sc->type) { + case AW_LCD_CH0: + index = (val & CH0_CLK_SRC_SEL) >> CH0_CLK_SRC_SEL_SHIFT; + break; + case AW_LCD_CH1: + switch (sc->id) { + case CLK_IDX_CH1_SCLK1: + index = 0; + break; + case CLK_IDX_CH1_SCLK2: + index = (val & CH1_SCLK2_SEL_SHIFT) >> + CH1_SCLK2_SEL_SHIFT; + break; + default: + return (ENXIO); + } + break; + default: + return (ENXIO); + } + + clknode_init_parent_idx(clk, index); + return (0); +} + +static int +aw_lcdclk_set_mux(struct clknode *clk, int index) +{ + struct aw_lcdclk_softc *sc; + uint32_t val; + + sc = clknode_get_softc(clk); + + switch (sc->type) { + case AW_LCD_CH0: + DEVICE_LOCK(sc); + LCDCLK_READ(sc, &val); + val &= ~CH0_CLK_SRC_SEL; + val |= (index << CH0_CLK_SRC_SEL_SHIFT); + LCDCLK_WRITE(sc, val); + DEVICE_UNLOCK(sc); + break; + case AW_LCD_CH1: + switch (sc->id) { + case CLK_IDX_CH1_SCLK2: + DEVICE_LOCK(sc); + LCDCLK_READ(sc, &val); + val &= ~CH1_SCLK2_SEL; + val |= (index << CH1_SCLK2_SEL_SHIFT); + LCDCLK_WRITE(sc, val); + DEVICE_UNLOCK(sc); + break; + default: + return (ENXIO); + } + break; + default: + return (ENXIO); + } + + return (0); +} + +static int +aw_lcdclk_set_gate(struct clknode *clk, bool enable) +{ + struct aw_lcdclk_softc *sc; + uint32_t val, mask; + + sc = clknode_get_softc(clk); + + switch (sc->type) { + case AW_LCD_CH0: + mask = CH0_SCLK_GATING; + break; + case AW_LCD_CH1: + mask = (sc->id == CLK_IDX_CH1_SCLK1) ? CH1_SCLK1_GATING : + CH1_SCLK2_GATING; + break; + default: + return (ENXIO); + } + + DEVICE_LOCK(sc); + LCDCLK_READ(sc, &val); + if (enable) + val |= mask; + else + val &= ~mask; + LCDCLK_WRITE(sc, val); + DEVICE_UNLOCK(sc); + + return (0); +} + +static int +aw_lcdclk_recalc_freq(struct clknode *clk, uint64_t *freq) +{ + struct aw_lcdclk_softc *sc; + uint32_t val, m; + + sc = clknode_get_softc(clk); + + if (sc->type != AW_LCD_CH1) + return (0); + + DEVICE_LOCK(sc); + LCDCLK_READ(sc, &val); + DEVICE_UNLOCK(sc); + + m = ((val & CH1_CLK_DIV_RATIO_M) >> CH1_CLK_DIV_RATIO_M_SHIFT) + 1; + *freq = *freq / m; + + if (sc->id == CLK_IDX_CH1_SCLK1) { + if ((val & CH1_SCLK1_SEL) == CH1_SCLK1_SEL_SCLK2_DIV2) + *freq /= 2; + } + + return (0); +} + +static void +calc_tcon_pll(uint64_t fin, uint64_t fout, uint32_t *pm, uint32_t *pn) +{ + int64_t diff, fcur, best; + int m, n; + + best = fout; + for (m = TCON_PLL_M_MIN; m <= TCON_PLL_M_MAX; m++) { + for (n = TCON_PLL_N_MIN; n <= TCON_PLL_N_MAX; n++) { + fcur = (n * fin) / m; + diff = (int64_t)fout - fcur; + if (diff > 0 && diff < best) { + best = diff; + *pm = m; + *pn = n; + } + } + } +} + +static int +aw_lcdclk_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout, + int flags, int *stop) +{ + struct aw_lcdclk_softc *sc; + uint32_t val, m, m2, n, n2, src_sel; + uint64_t fsingle, fdouble; + int error; + bool dbl; + + sc = clknode_get_softc(clk); + + switch (sc->type) { + case AW_LCD_CH0: + *stop = 0; + break; + case AW_LCD_CH1: + if (sc->id != CLK_IDX_CH1_SCLK2) + return (ENXIO); + + m = n = m2 = n2 = 0; + dbl = false; + + /* Find the frequency closes to the target dot clock, using + * both 1X and 2X PLL inputs as possible candidates. + */ + calc_tcon_pll(TCON_PLLREF, *fout, &m, &n); + calc_tcon_pll(TCON_PLLREF * 2, *fout, &m2, &n2); + + fsingle = m ? (n * TCON_PLLREF) / m : 0; + fdouble = m2 ? (n2 * TCON_PLLREF * 2) / m2 : 0; + + if (fdouble > fsingle) { + dbl = true; + m = m2; + n = n2; + } + + src_sel = dbl ? CH0_CLK_SRC_SEL_PLL3_2X : + CH0_CLK_SRC_SEL_PLL3_1X; + + /* Switch parent clock if necessary */ + if (src_sel != clknode_get_parent_idx(clk)) { + error = clknode_set_parent_by_idx(clk, src_sel); + if (error != 0) + return (error); + } + + /* Set desired parent frequency */ + fin = n * TCON_PLLREF; + + error = clknode_set_freq(clknode_get_parent(clk), fin, 0, 0); + if (error != 0) + return (error); + + error = clknode_enable(clknode_get_parent(clk)); + if (error != 0) + return (error); + + /* Fetch new input frequency */ + error = clknode_get_freq(clknode_get_parent(clk), &fin); + if (error != 0) + return (error); + + /* Set LCD divisor */ + DEVICE_LOCK(sc); + LCDCLK_READ(sc, &val); + val &= ~CH1_CLK_DIV_RATIO_M; + val |= ((m - 1) << CH1_CLK_DIV_RATIO_M_SHIFT); + LCDCLK_WRITE(sc, val); + DEVICE_UNLOCK(sc); + + *fout = fin / m; + *stop = 1; + + break; + } + + return (0); +} + +static clknode_method_t aw_lcdclk_clknode_methods[] = { + /* Device interface */ + CLKNODEMETHOD(clknode_init, aw_lcdclk_init), + CLKNODEMETHOD(clknode_set_gate, aw_lcdclk_set_gate), + CLKNODEMETHOD(clknode_set_mux, aw_lcdclk_set_mux), + CLKNODEMETHOD(clknode_recalc_freq, aw_lcdclk_recalc_freq), + CLKNODEMETHOD(clknode_set_freq, aw_lcdclk_set_freq), + CLKNODEMETHOD_END +}; +DEFINE_CLASS_1(aw_lcdclk_clknode, aw_lcdclk_clknode_class, + aw_lcdclk_clknode_methods, sizeof(struct aw_lcdclk_softc), clknode_class); + +static int +aw_lcdclk_create(device_t dev, struct clkdom *clkdom, + const char **parent_names, int parent_cnt, const char *name, int index) +{ + struct aw_lcdclk_softc *sc, *clk_sc; + struct clknode_init_def def; + struct clknode *clk; + phandle_t node; + + sc = device_get_softc(dev); + node = ofw_bus_get_node(dev); + + memset(&def, 0, sizeof(def)); + def.id = index; + def.name = name; + def.parent_names = parent_names; + def.parent_cnt = parent_cnt; + + clk = clknode_create(clkdom, &aw_lcdclk_clknode_class, &def); + if (clk == NULL) { + device_printf(dev, "cannot create clknode\n"); + return (ENXIO); + } + + clk_sc = clknode_get_softc(clk); + clk_sc->type = sc->type; + clk_sc->reg = sc->reg; + clk_sc->clkdev = sc->clkdev; + clk_sc->id = index; + + clknode_register(clkdom, clk); + + return (0); +} + +static int +aw_lcdclk_probe(device_t dev) +{ + enum aw_lcdclk_type type; + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; + switch (type) { + case AW_LCD_CH0: + device_set_desc(dev, "Allwinner LCD CH0 Clock"); + break; + case AW_LCD_CH1: + device_set_desc(dev, "Allwinner LCD CH1 Clock"); + break; + default: + return (ENXIO); + } + + return (BUS_PROBE_DEFAULT); +} + +static int +aw_lcdclk_attach(device_t dev) +{ + struct aw_lcdclk_softc *sc; + struct clkdom *clkdom; + clk_t clk_parent; + bus_size_t psize; + phandle_t node; + uint32_t *indices; + const char **parent_names; + const char **names; + int error, ncells, nout, i; + + sc = device_get_softc(dev); + sc->clkdev = device_get_parent(dev); + sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; + + node = ofw_bus_get_node(dev); + + if (ofw_reg_to_paddr(node, 0, &sc->reg, &psize, NULL) != 0) { + device_printf(dev, "cannot parse 'reg' property\n"); + return (ENXIO); + } + + error = ofw_bus_parse_xref_list_get_length(node, "clocks", + "#clock-cells", &ncells); + if (error != 0) { + device_printf(dev, "cannot get clock count\n"); + return (error); + } + + parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK); + for (i = 0; i < ncells; i++) { + error = clk_get_by_ofw_index(dev, i, &clk_parent); + if (error != 0) { + device_printf(dev, "cannot get clock %d\n", i); + goto fail; + } + parent_names[i] = clk_get_name(clk_parent); + clk_release(clk_parent); + } + + nout = clk_parse_ofw_out_names(dev, node, &names, &indices); + if (nout == 0) { + device_printf(dev, "no clock outputs found\n"); + return (error); + } + + clkdom = clkdom_create(dev); + + for (i = 0; i < nout; i++) { + error = aw_lcdclk_create(dev, clkdom, parent_names, ncells, + names[i], nout == 1 ? 1 : i); + if (error) + goto fail; + } + + if (clkdom_finit(clkdom) != 0) { + device_printf(dev, "cannot finalize clkdom initialization\n"); + error = ENXIO; + goto fail; + } + + if (bootverbose) + clkdom_dump(clkdom); + + if (sc->type == AW_LCD_CH0) + hwreset_register_ofw_provider(dev); + + free(parent_names, M_OFWPROP); + return (0); + +fail: + free(parent_names, M_OFWPROP); + return (error); +} + +static device_method_t aw_lcdclk_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, aw_lcdclk_probe), + DEVMETHOD(device_attach, aw_lcdclk_attach), + + /* Reset interface */ + DEVMETHOD(hwreset_assert, aw_lcdclk_hwreset_assert), + DEVMETHOD(hwreset_is_asserted, aw_lcdclk_hwreset_is_asserted), + + DEVMETHOD_END +}; + +static driver_t aw_lcdclk_driver = { + "aw_lcdclk", + aw_lcdclk_methods, + sizeof(struct aw_lcdclk_softc) +}; + +static devclass_t aw_lcdclk_devclass; + +EARLY_DRIVER_MODULE(aw_lcdclk, simplebus, aw_lcdclk_driver, + aw_lcdclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Property changes on: head/sys/arm/allwinner/clk/aw_lcdclk.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/allwinner/clk/aw_mmcclk.c =================================================================== --- head/sys/arm/allwinner/clk/aw_mmcclk.c (nonexistent) +++ head/sys/arm/allwinner/clk/aw_mmcclk.c (revision 297627) @@ -0,0 +1,351 @@ +/*- + * Copyright (c) 2016 Jared McNeill + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Allwinner MMC clocks + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "clkdev_if.h" + +#define SCLK_GATING (1 << 31) +#define CLK_SRC_SEL (0x3 << 24) +#define CLK_SRC_SEL_SHIFT 24 +#define CLK_SRC_SEL_MAX 0x3 +#define CLK_SRC_SEL_OSC24M 0 +#define CLK_SRC_SEL_PLL6 1 +#define CLK_PHASE_CTR (0x7 << 20) +#define CLK_PHASE_CTR_SHIFT 20 +#define CLK_RATIO_N (0x3 << 16) +#define CLK_RATIO_N_SHIFT 16 +#define CLK_RATIO_N_MAX 0x3 +#define OUTPUT_CLK_PHASE_CTR (0x7 << 8) +#define OUTPUT_CLK_PHASE_CTR_SHIFT 8 +#define CLK_RATIO_M (0xf << 0) +#define CLK_RATIO_M_SHIFT 0 +#define CLK_RATIO_M_MAX 0xf + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun4i-a10-mmc-clk", 1 }, + { NULL, 0 } +}; + +struct aw_mmcclk_sc { + device_t clkdev; + bus_addr_t reg; +}; + +#define MODCLK_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val)) +#define MODCLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val)) +#define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev) +#define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev) + +static int +aw_mmcclk_init(struct clknode *clk, device_t dev) +{ + struct aw_mmcclk_sc *sc; + uint32_t val, index; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(sc); + MODCLK_READ(sc, &val); + DEVICE_UNLOCK(sc); + + index = (val & CLK_SRC_SEL) >> CLK_SRC_SEL_SHIFT; + + clknode_init_parent_idx(clk, index); + return (0); +} + +static int +aw_mmcclk_set_mux(struct clknode *clk, int index) +{ + struct aw_mmcclk_sc *sc; + uint32_t val; + + sc = clknode_get_softc(clk); + + if (index < 0 || index > CLK_SRC_SEL_MAX) + return (ERANGE); + + DEVICE_LOCK(sc); + MODCLK_READ(sc, &val); + val &= ~CLK_SRC_SEL; + val |= (index << CLK_SRC_SEL_SHIFT); + MODCLK_WRITE(sc, val); + DEVICE_UNLOCK(sc); + + return (0); +} + +static int +aw_mmcclk_set_gate(struct clknode *clk, bool enable) +{ + struct aw_mmcclk_sc *sc; + uint32_t val; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(sc); + MODCLK_READ(sc, &val); + if (enable) + val |= SCLK_GATING; + else + val &= ~SCLK_GATING; + MODCLK_WRITE(sc, val); + DEVICE_UNLOCK(sc); + + return (0); +} + +static int +aw_mmcclk_recalc_freq(struct clknode *clk, uint64_t *freq) +{ + struct aw_mmcclk_sc *sc; + uint32_t val, m, n; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(sc); + MODCLK_READ(sc, &val); + DEVICE_UNLOCK(sc); + + n = 1 << ((val & CLK_RATIO_N) >> CLK_RATIO_N_SHIFT); + m = ((val & CLK_RATIO_M) >> CLK_RATIO_M_SHIFT) + 1; + + *freq = *freq / n / m; + + return (0); +} + +static int +aw_mmcclk_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout, + int flags, int *stop) +{ + struct aw_mmcclk_sc *sc; + uint32_t val, m, n, phase, ophase; + int parent_idx, error; + + sc = clknode_get_softc(clk); + + /* XXX + * The ophase/phase values should be set by the MMC driver, but + * there is currently no way to do this with the clk API + */ + if (*fout <= 400000) { + parent_idx = CLK_SRC_SEL_OSC24M; + ophase = 0; + phase = 0; + n = 2; + } else if (*fout <= 25000000) { + parent_idx = CLK_SRC_SEL_PLL6; + ophase = 0; + phase = 5; + n = 2; + } else if (*fout <= 50000000) { + parent_idx = CLK_SRC_SEL_PLL6; + ophase = 3; + phase = 5; + n = 0; + } else + return (ERANGE); + + /* Switch parent clock, if necessary */ + if (parent_idx != clknode_get_parent_idx(clk)) { + error = clknode_set_parent_by_idx(clk, parent_idx); + if (error != 0) + return (error); + + /* Fetch new input frequency */ + error = clknode_get_freq(clknode_get_parent(clk), &fin); + if (error != 0) + return (error); + } + + m = ((fin / (1 << n)) / *fout) - 1; + + DEVICE_LOCK(sc); + MODCLK_READ(sc, &val); + val &= ~(CLK_RATIO_N | CLK_RATIO_M | CLK_PHASE_CTR | + OUTPUT_CLK_PHASE_CTR); + val |= (n << CLK_RATIO_N_SHIFT); + val |= (m << CLK_RATIO_M_SHIFT); + val |= (phase << CLK_PHASE_CTR_SHIFT); + val |= (ophase << OUTPUT_CLK_PHASE_CTR_SHIFT); + MODCLK_WRITE(sc, val); + DEVICE_UNLOCK(sc); + + *fout = fin / (1 << n) / (m + 1); + *stop = 1; + + return (0); +} + +static clknode_method_t aw_mmcclk_clknode_methods[] = { + /* Device interface */ + CLKNODEMETHOD(clknode_init, aw_mmcclk_init), + CLKNODEMETHOD(clknode_set_gate, aw_mmcclk_set_gate), + CLKNODEMETHOD(clknode_set_mux, aw_mmcclk_set_mux), + CLKNODEMETHOD(clknode_recalc_freq, aw_mmcclk_recalc_freq), + CLKNODEMETHOD(clknode_set_freq, aw_mmcclk_set_freq), + CLKNODEMETHOD_END +}; +DEFINE_CLASS_1(aw_mmcclk_clknode, aw_mmcclk_clknode_class, + aw_mmcclk_clknode_methods, sizeof(struct aw_mmcclk_sc), clknode_class); + +static int +aw_mmcclk_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Allwinner MMC Clock"); + return (BUS_PROBE_DEFAULT); +} + +static int +aw_mmcclk_attach(device_t dev) +{ + struct clknode_init_def def; + struct aw_mmcclk_sc *sc; + struct clkdom *clkdom; + struct clknode *clk; + const char **names; + uint32_t *indices; + clk_t clk_parent; + bus_addr_t paddr; + bus_size_t psize; + phandle_t node; + int error, nout, ncells, i; + + node = ofw_bus_get_node(dev); + + if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) { + device_printf(dev, "cannot parse 'reg' property\n"); + return (ENXIO); + } + + error = ofw_bus_parse_xref_list_get_length(node, "clocks", + "#clock-cells", &ncells); + if (error != 0 || ncells == 0) { + device_printf(dev, "couldn't find parent clocks\n"); + return (ENXIO); + } + + clkdom = clkdom_create(dev); + + nout = clk_parse_ofw_out_names(dev, node, &names, &indices); + if (nout == 0) { + device_printf(dev, "no output clocks found\n"); + error = ENXIO; + goto fail; + } + + memset(&def, 0, sizeof(def)); + def.name = names[0]; + def.id = 0; + def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK); + for (i = 0; i < ncells; i++) { + error = clk_get_by_ofw_index(dev, i, &clk_parent); + if (error != 0) { + device_printf(dev, "cannot get clock %d\n", i); + goto fail; + } + def.parent_names[i] = clk_get_name(clk_parent); + clk_release(clk_parent); + } + def.parent_cnt = ncells; + def.flags = CLK_NODE_GLITCH_FREE; + + clk = clknode_create(clkdom, &aw_mmcclk_clknode_class, &def); + if (clk == NULL) { + device_printf(dev, "cannot create clknode\n"); + error = ENXIO; + goto fail; + } + + sc = clknode_get_softc(clk); + sc->reg = paddr; + sc->clkdev = device_get_parent(dev); + + clknode_register(clkdom, clk); + + if (clkdom_finit(clkdom) != 0) { + device_printf(dev, "cannot finalize clkdom initialization\n"); + error = ENXIO; + goto fail; + } + + if (bootverbose) + clkdom_dump(clkdom); + + return (0); + +fail: + return (error); +} + +static device_method_t aw_mmcclk_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, aw_mmcclk_probe), + DEVMETHOD(device_attach, aw_mmcclk_attach), + + DEVMETHOD_END +}; + +static driver_t aw_mmcclk_driver = { + "aw_mmcclk", + aw_mmcclk_methods, + 0 +}; + +static devclass_t aw_mmcclk_devclass; + +EARLY_DRIVER_MODULE(aw_mmcclk, simplebus, aw_mmcclk_driver, + aw_mmcclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Property changes on: head/sys/arm/allwinner/clk/aw_mmcclk.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/allwinner/clk/aw_modclk.c =================================================================== --- head/sys/arm/allwinner/clk/aw_modclk.c (nonexistent) +++ head/sys/arm/allwinner/clk/aw_modclk.c (revision 297627) @@ -0,0 +1,318 @@ +/*- + * Copyright (c) 2016 Jared McNeill + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Allwinner module clocks + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "clkdev_if.h" + +#define SCLK_GATING (1 << 31) +#define CLK_SRC_SEL (0x3 << 24) +#define CLK_SRC_SEL_SHIFT 24 +#define CLK_SRC_SEL_MAX 0x3 +#define CLK_RATIO_N (0x3 << 16) +#define CLK_RATIO_N_SHIFT 16 +#define CLK_RATIO_N_MAX 0x3 +#define CLK_RATIO_M (0x1f << 0) +#define CLK_RATIO_M_SHIFT 0 +#define CLK_RATIO_M_MAX 0x1f + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun4i-a10-mod0-clk", 1 }, + { NULL, 0 } +}; + +struct aw_modclk_sc { + device_t clkdev; + bus_addr_t reg; +}; + +#define MODCLK_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val)) +#define MODCLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val)) +#define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev) +#define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev) + +static int +aw_modclk_init(struct clknode *clk, device_t dev) +{ + struct aw_modclk_sc *sc; + uint32_t val, index; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(sc); + MODCLK_READ(sc, &val); + DEVICE_UNLOCK(sc); + + index = (val & CLK_SRC_SEL) >> CLK_SRC_SEL_SHIFT; + + clknode_init_parent_idx(clk, index); + return (0); +} + +static int +aw_modclk_set_mux(struct clknode *clk, int index) +{ + struct aw_modclk_sc *sc; + uint32_t val; + + sc = clknode_get_softc(clk); + + if (index < 0 || index > CLK_SRC_SEL_MAX) + return (ERANGE); + + DEVICE_LOCK(sc); + MODCLK_READ(sc, &val); + val &= ~CLK_SRC_SEL; + val |= (index << CLK_SRC_SEL_SHIFT); + MODCLK_WRITE(sc, val); + DEVICE_UNLOCK(sc); + + return (0); +} + +static int +aw_modclk_set_gate(struct clknode *clk, bool enable) +{ + struct aw_modclk_sc *sc; + uint32_t val; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(sc); + MODCLK_READ(sc, &val); + if (enable) + val |= SCLK_GATING; + else + val &= ~SCLK_GATING; + MODCLK_WRITE(sc, val); + DEVICE_UNLOCK(sc); + + return (0); +} + +static int +aw_modclk_recalc_freq(struct clknode *clk, uint64_t *freq) +{ + struct aw_modclk_sc *sc; + uint32_t val, m, n; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(sc); + MODCLK_READ(sc, &val); + DEVICE_UNLOCK(sc); + + n = 1 << ((val & CLK_RATIO_N) >> CLK_RATIO_N_SHIFT); + m = ((val & CLK_RATIO_M) >> CLK_RATIO_M_SHIFT) + 1; + + *freq = *freq / n / m; + + return (0); +} + +static int +aw_modclk_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout, + int flags, int *stop) +{ + struct aw_modclk_sc *sc; + uint32_t val, m, n, best_m, best_n; + uint64_t cur_freq; + int64_t best_diff, cur_diff; + + sc = clknode_get_softc(clk); + best_n = best_m = 0; + best_diff = (int64_t)*fout; + + for (n = 0; n <= CLK_RATIO_N_MAX; n++) + for (m = 0; m <= CLK_RATIO_M_MAX; m++) { + cur_freq = fin / (1 << n) / (m + 1); + cur_diff = (int64_t)*fout - cur_freq; + if (cur_diff >= 0 && cur_diff < best_diff) { + best_diff = cur_diff; + best_m = m; + best_n = n; + } + } + + if (best_diff == (int64_t)*fout) + return (ERANGE); + + DEVICE_LOCK(sc); + MODCLK_READ(sc, &val); + val &= ~(CLK_RATIO_N | CLK_RATIO_M); + val |= (best_n << CLK_RATIO_N_SHIFT); + val |= (best_m << CLK_RATIO_M_SHIFT); + MODCLK_WRITE(sc, val); + DEVICE_UNLOCK(sc); + + *fout = fin / (1 << best_n) / (best_m + 1); + *stop = 1; + + return (0); +} + +static clknode_method_t aw_modclk_clknode_methods[] = { + /* Device interface */ + CLKNODEMETHOD(clknode_init, aw_modclk_init), + CLKNODEMETHOD(clknode_set_gate, aw_modclk_set_gate), + CLKNODEMETHOD(clknode_set_mux, aw_modclk_set_mux), + CLKNODEMETHOD(clknode_recalc_freq, aw_modclk_recalc_freq), + CLKNODEMETHOD(clknode_set_freq, aw_modclk_set_freq), + CLKNODEMETHOD_END +}; +DEFINE_CLASS_1(aw_modclk_clknode, aw_modclk_clknode_class, + aw_modclk_clknode_methods, sizeof(struct aw_modclk_sc), clknode_class); + +static int +aw_modclk_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Allwinner Module Clock"); + return (BUS_PROBE_DEFAULT); +} + +static int +aw_modclk_attach(device_t dev) +{ + struct clknode_init_def def; + struct aw_modclk_sc *sc; + struct clkdom *clkdom; + struct clknode *clk; + clk_t clk_parent; + bus_addr_t paddr; + bus_size_t psize; + phandle_t node; + int error, ncells, i; + + node = ofw_bus_get_node(dev); + + if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) { + device_printf(dev, "cannot parse 'reg' property\n"); + return (ENXIO); + } + + error = ofw_bus_parse_xref_list_get_length(node, "clocks", + "#clock-cells", &ncells); + if (error != 0) { + device_printf(dev, "cannot get clock count\n"); + return (error); + } + + clkdom = clkdom_create(dev); + + memset(&def, 0, sizeof(def)); + error = clk_parse_ofw_clk_name(dev, node, &def.name); + if (error != 0) { + device_printf(dev, "cannot parse clock name\n"); + error = ENXIO; + goto fail; + } + def.id = 1; + def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK); + for (i = 0; i < ncells; i++) { + error = clk_get_by_ofw_index(dev, i, &clk_parent); + if (error != 0) { + device_printf(dev, "cannot get clock %d\n", i); + goto fail; + } + def.parent_names[i] = clk_get_name(clk_parent); + clk_release(clk_parent); + } + def.parent_cnt = ncells; + + clk = clknode_create(clkdom, &aw_modclk_clknode_class, &def); + if (clk == NULL) { + device_printf(dev, "cannot create clknode\n"); + error = ENXIO; + goto fail; + } + + sc = clknode_get_softc(clk); + sc->reg = paddr; + sc->clkdev = device_get_parent(dev); + + clknode_register(clkdom, clk); + + if (clkdom_finit(clkdom) != 0) { + device_printf(dev, "cannot finalize clkdom initialization\n"); + error = ENXIO; + goto fail; + } + + if (bootverbose) + clkdom_dump(clkdom); + + return (0); + +fail: + return (error); +} + +static device_method_t aw_modclk_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, aw_modclk_probe), + DEVMETHOD(device_attach, aw_modclk_attach), + + DEVMETHOD_END +}; + +static driver_t aw_modclk_driver = { + "aw_modclk", + aw_modclk_methods, + 0 +}; + +static devclass_t aw_modclk_devclass; + +EARLY_DRIVER_MODULE(aw_modclk, simplebus, aw_modclk_driver, + aw_modclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Property changes on: head/sys/arm/allwinner/clk/aw_modclk.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/allwinner/clk/aw_oscclk.c =================================================================== --- head/sys/arm/allwinner/clk/aw_oscclk.c (nonexistent) +++ head/sys/arm/allwinner/clk/aw_oscclk.c (revision 297627) @@ -0,0 +1,132 @@ +/*- + * Copyright (c) 2016 Jared McNeill + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Allwinner oscillator clock + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +static int +aw_oscclk_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-osc-clk")) + return (ENXIO); + + device_set_desc(dev, "Allwinner Oscillator Clock"); + return (BUS_PROBE_DEFAULT); +} + +static int +aw_oscclk_attach(device_t dev) +{ + struct clk_fixed_def def; + struct clkdom *clkdom; + phandle_t node; + uint32_t freq; + int error; + + node = ofw_bus_get_node(dev); + + if (OF_getencprop(node, "clock-frequency", &freq, sizeof(freq)) <= 0) { + device_printf(dev, "missing clock-frequency property\n"); + error = ENXIO; + goto fail; + } + + clkdom = clkdom_create(dev); + + memset(&def, 0, sizeof(def)); + def.clkdef.id = 1; + def.freq = freq; + error = clk_parse_ofw_clk_name(dev, node, &def.clkdef.name); + if (error != 0) { + device_printf(dev, "cannot parse clock name\n"); + error = ENXIO; + goto fail; + } + + error = clknode_fixed_register(clkdom, &def); + if (error != 0) { + device_printf(dev, "cannot register fixed clock\n"); + error = ENXIO; + goto fail; + } + + if (clkdom_finit(clkdom) != 0) { + device_printf(dev, "cannot finalize clkdom initialization\n"); + error = ENXIO; + goto fail; + } + + if (bootverbose) + clkdom_dump(clkdom); + + free(__DECONST(char *, def.clkdef.name), M_OFWPROP); + + return (0); + +fail: + free(__DECONST(char *, def.clkdef.name), M_OFWPROP); + return (error); +} + +static device_method_t aw_oscclk_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, aw_oscclk_probe), + DEVMETHOD(device_attach, aw_oscclk_attach), + + DEVMETHOD_END +}; + +static driver_t aw_oscclk_driver = { + "aw_oscclk", + aw_oscclk_methods, + 0, +}; + +static devclass_t aw_oscclk_devclass; + +EARLY_DRIVER_MODULE(aw_oscclk, simplebus, aw_oscclk_driver, + aw_oscclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Property changes on: head/sys/arm/allwinner/clk/aw_oscclk.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/allwinner/clk/aw_pll.c =================================================================== --- head/sys/arm/allwinner/clk/aw_pll.c (nonexistent) +++ head/sys/arm/allwinner/clk/aw_pll.c (revision 297627) @@ -0,0 +1,757 @@ +/*- + * Copyright (c) 2016 Jared McNeill + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Allwinner PLL clock + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include + +#include "clkdev_if.h" + +#define AW_PLL_ENABLE (1 << 31) + +#define A10_PLL1_OUT_EXT_DIVP (0x3 << 16) +#define A10_PLL1_OUT_EXT_DIVP_SHIFT 16 +#define A10_PLL1_FACTOR_N (0x1f << 8) +#define A10_PLL1_FACTOR_N_SHIFT 8 +#define A10_PLL1_FACTOR_K (0x3 << 4) +#define A10_PLL1_FACTOR_K_SHIFT 4 +#define A10_PLL1_FACTOR_M (0x3 << 0) +#define A10_PLL1_FACTOR_M_SHIFT 0 + +#define A10_PLL2_POST_DIV (0xf << 26) +#define A10_PLL2_POST_DIV_SHIFT 26 +#define A10_PLL2_FACTOR_N (0x7f << 8) +#define A10_PLL2_FACTOR_N_SHIFT 8 +#define A10_PLL2_PRE_DIV (0x1f << 0) +#define A10_PLL2_PRE_DIV_SHIFT 0 + +#define A10_PLL3_MODE_SEL (0x1 << 15) +#define A10_PLL3_MODE_SEL_FRACT (0 << 15) +#define A10_PLL3_MODE_SEL_INT (1 << 15) +#define A10_PLL3_FUNC_SET (0x1 << 14) +#define A10_PLL3_FUNC_SET_270MHZ (0 << 14) +#define A10_PLL3_FUNC_SET_297MHZ (1 << 14) +#define A10_PLL3_FACTOR_M (0x7f << 0) +#define A10_PLL3_FACTOR_M_SHIFT 0 +#define A10_PLL3_REF_FREQ 3000000 + +#define A10_PLL5_OUT_EXT_DIVP (0x3 << 16) +#define A10_PLL5_OUT_EXT_DIVP_SHIFT 16 +#define A10_PLL5_FACTOR_N (0x1f << 8) +#define A10_PLL5_FACTOR_N_SHIFT 8 +#define A10_PLL5_FACTOR_K (0x3 << 4) +#define A10_PLL5_FACTOR_K_SHIFT 4 +#define A10_PLL5_FACTOR_M1 (0x3 << 2) +#define A10_PLL5_FACTOR_M1_SHIFT 2 +#define A10_PLL5_FACTOR_M (0x3 << 0) +#define A10_PLL5_FACTOR_M_SHIFT 0 + +#define A10_PLL6_BYPASS_EN (1 << 30) +#define A10_PLL6_SATA_CLK_EN (1 << 14) +#define A10_PLL6_FACTOR_N (0x1f << 8) +#define A10_PLL6_FACTOR_N_SHIFT 8 +#define A10_PLL6_FACTOR_K (0x3 << 4) +#define A10_PLL6_FACTOR_K_SHIFT 4 +#define A10_PLL6_FACTOR_M (0x3 << 0) +#define A10_PLL6_FACTOR_M_SHIFT 0 + +#define A10_PLL2_POST_DIV (0xf << 26) + +#define A31_PLL1_LOCK (1 << 28) +#define A31_PLL1_CPU_SIGMA_DELTA_EN (1 << 24) +#define A31_PLL1_FACTOR_N (0x1f << 8) +#define A31_PLL1_FACTOR_N_SHIFT 8 +#define A31_PLL1_FACTOR_K (0x3 << 4) +#define A31_PLL1_FACTOR_K_SHIFT 4 +#define A31_PLL1_FACTOR_M (0x3 << 0) +#define A31_PLL1_FACTOR_M_SHIFT 0 + +#define A31_PLL6_LOCK (1 << 28) +#define A31_PLL6_BYPASS_EN (1 << 25) +#define A31_PLL6_CLK_OUT_EN (1 << 24) +#define A31_PLL6_24M_OUT_EN (1 << 18) +#define A31_PLL6_24M_POST_DIV (0x3 << 16) +#define A31_PLL6_24M_POST_DIV_SHIFT 16 +#define A31_PLL6_FACTOR_N (0x1f << 8) +#define A31_PLL6_FACTOR_N_SHIFT 8 +#define A31_PLL6_FACTOR_K (0x3 << 4) +#define A31_PLL6_FACTOR_K_SHIFT 4 +#define A31_PLL6_DEFAULT_N 0x18 +#define A31_PLL6_DEFAULT_K 0x1 +#define A31_PLL6_TIMEOUT 10 + +#define CLKID_A10_PLL3_1X 0 +#define CLKID_A10_PLL3_2X 1 + +#define CLKID_A10_PLL5_DDR 0 +#define CLKID_A10_PLL5_OTHER 1 + +#define CLKID_A10_PLL6_SATA 0 +#define CLKID_A10_PLL6_OTHER 1 +#define CLKID_A10_PLL6 2 +#define CLKID_A10_PLL6_DIV_4 3 + +#define CLKID_A31_PLL6 0 +#define CLKID_A31_PLL6_X2 1 + +enum aw_pll_type { + AWPLL_A10_PLL1 = 1, + AWPLL_A10_PLL2, + AWPLL_A10_PLL3, + AWPLL_A10_PLL5, + AWPLL_A10_PLL6, + AWPLL_A31_PLL1, + AWPLL_A31_PLL6, +}; + +struct aw_pll_sc { + enum aw_pll_type type; + device_t clkdev; + bus_addr_t reg; + int id; +}; + +struct aw_pll_funcs { + int (*recalc)(struct aw_pll_sc *, uint64_t *); + int (*set_freq)(struct aw_pll_sc *, uint64_t, uint64_t *, int); + int (*init)(device_t, bus_addr_t, struct clknode_init_def *); +}; + +#define PLL_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val)) +#define PLL_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val)) +#define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev) +#define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev) + +static int +a10_pll1_recalc(struct aw_pll_sc *sc, uint64_t *freq) +{ + uint32_t val, m, n, k, p; + + DEVICE_LOCK(sc); + PLL_READ(sc, &val); + DEVICE_UNLOCK(sc); + + p = 1 << ((val & A10_PLL1_OUT_EXT_DIVP) >> A10_PLL1_OUT_EXT_DIVP_SHIFT); + m = ((val & A10_PLL1_FACTOR_M) >> A10_PLL1_FACTOR_M_SHIFT) + 1; + k = ((val & A10_PLL1_FACTOR_K) >> A10_PLL1_FACTOR_K_SHIFT) + 1; + n = (val & A10_PLL1_FACTOR_N) >> A10_PLL1_FACTOR_N_SHIFT; + if (n == 0) + n = 1; + + *freq = (*freq * n * k) / (m * p); + + return (0); +} + +static int +a10_pll2_recalc(struct aw_pll_sc *sc, uint64_t *freq) +{ + uint32_t val, post_div, n, pre_div; + + DEVICE_LOCK(sc); + PLL_READ(sc, &val); + DEVICE_UNLOCK(sc); + + post_div = (val & A10_PLL2_POST_DIV) >> A10_PLL2_POST_DIV_SHIFT; + if (post_div == 0) + post_div = 1; + n = (val & A10_PLL2_FACTOR_N) >> A10_PLL2_FACTOR_N_SHIFT; + if (n == 0) + n = 1; + pre_div = (val & A10_PLL2_PRE_DIV) >> A10_PLL2_PRE_DIV_SHIFT; + if (pre_div == 0) + pre_div = 1; + + switch (sc->id) { + case SUN4I_A10_PLL2_1X: + *freq = (*freq * 2 * n) / pre_div / post_div / 2; + break; + case SUN4I_A10_PLL2_2X: + *freq = (*freq * 2 * n) / pre_div / 4; + break; + case SUN4I_A10_PLL2_4X: + *freq = (*freq * 2 * n) / pre_div / 2; + break; + case SUN4I_A10_PLL2_8X: + *freq = (*freq * 2 * n) / pre_div; + break; + default: + return (EINVAL); + } + + return (0); +} + +static int +a10_pll2_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout, + int flags) +{ + uint32_t val, post_div, n, pre_div; + + if (sc->id != SUN4I_A10_PLL2_1X) + return (ENXIO); + + /* + * Audio Codec needs PLL2-1X to be either 24576000 or 22579200. + * + * PLL2-1X output frequency is (48MHz * n) / pre_div / post_div / 2. + * To get as close as possible to the desired rate, we use a + * pre-divider of 21 and a post-divider of 4. With these values, + * a multiplier of 86 or 79 gets us close to the target rates. + */ + if (*fout != 24576000 && *fout != 22579200) + return (EINVAL); + + pre_div = 21; + post_div = 4; + n = (*fout * pre_div * post_div * 2) / (2 * fin); + + DEVICE_LOCK(sc); + PLL_READ(sc, &val); + val &= ~(A10_PLL2_POST_DIV | A10_PLL2_FACTOR_N | A10_PLL2_PRE_DIV); + val |= (post_div << A10_PLL2_POST_DIV_SHIFT); + val |= (n << A10_PLL2_FACTOR_N_SHIFT); + val |= (pre_div << A10_PLL2_PRE_DIV_SHIFT); + PLL_WRITE(sc, val); + DEVICE_UNLOCK(sc); + + return (0); +} + +static int +a10_pll3_recalc(struct aw_pll_sc *sc, uint64_t *freq) +{ + uint32_t val, m; + + DEVICE_LOCK(sc); + PLL_READ(sc, &val); + DEVICE_UNLOCK(sc); + + if ((val & A10_PLL3_MODE_SEL) == A10_PLL3_MODE_SEL_INT) { + /* In integer mode, output is 3MHz * m */ + m = (val & A10_PLL3_FACTOR_M) >> A10_PLL3_FACTOR_M_SHIFT; + *freq = A10_PLL3_REF_FREQ * m; + } else { + /* In fractional mode, output is either 270MHz or 297MHz */ + if ((val & A10_PLL3_FUNC_SET) == A10_PLL3_FUNC_SET_270MHZ) + *freq = 270000000; + else + *freq = 297000000; + } + + if (sc->id == CLKID_A10_PLL3_2X) + *freq *= 2; + + return (0); +} + +static int +a10_pll3_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout, + int flags) +{ + uint32_t val, m, mode, func; + + m = *fout / A10_PLL3_REF_FREQ; + if (sc->id == CLKID_A10_PLL3_2X) + m /= 2; + + mode = A10_PLL3_MODE_SEL_INT; + func = 0; + *fout = m * A10_PLL3_REF_FREQ; + if (sc->id == CLKID_A10_PLL3_2X) + *fout *= 2; + + DEVICE_LOCK(sc); + PLL_READ(sc, &val); + val &= ~(A10_PLL3_MODE_SEL | A10_PLL3_FUNC_SET | A10_PLL3_FACTOR_M); + val |= mode; + val |= func; + val |= (m << A10_PLL3_FACTOR_M_SHIFT); + PLL_WRITE(sc, val); + DEVICE_UNLOCK(sc); + + return (0); +} + +static int +a10_pll3_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def) +{ + uint32_t val; + + /* Allow changing PLL frequency while enabled */ + def->flags = CLK_NODE_GLITCH_FREE; + + /* Set PLL to 297MHz */ + CLKDEV_DEVICE_LOCK(dev); + CLKDEV_READ_4(dev, reg, &val); + val &= ~(A10_PLL3_MODE_SEL | A10_PLL3_FUNC_SET | A10_PLL3_FACTOR_M); + val |= A10_PLL3_MODE_SEL_FRACT; + val |= A10_PLL3_FUNC_SET_297MHZ; + CLKDEV_WRITE_4(dev, reg, val); + CLKDEV_DEVICE_UNLOCK(dev); + + return (0); +} + +static int +a10_pll5_recalc(struct aw_pll_sc *sc, uint64_t *freq) +{ + uint32_t val, m, n, k, p; + + DEVICE_LOCK(sc); + PLL_READ(sc, &val); + DEVICE_UNLOCK(sc); + + p = 1 << ((val & A10_PLL5_OUT_EXT_DIVP) >> A10_PLL5_OUT_EXT_DIVP_SHIFT); + m = ((val & A10_PLL5_FACTOR_M) >> A10_PLL5_FACTOR_M_SHIFT) + 1; + k = ((val & A10_PLL5_FACTOR_K) >> A10_PLL5_FACTOR_K_SHIFT) + 1; + n = (val & A10_PLL5_FACTOR_N) >> A10_PLL5_FACTOR_N_SHIFT; + if (n == 0) + return (ENXIO); + + switch (sc->id) { + case CLKID_A10_PLL5_DDR: + *freq = (*freq * n * k) / m; + break; + case CLKID_A10_PLL5_OTHER: + *freq = (*freq * n * k) / p; + break; + default: + return (ENXIO); + } + + return (0); +} + +static int +a10_pll6_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def) +{ + uint32_t val, m, n, k; + + /* + * SATA needs PLL6 to be a 100MHz clock. + * + * The SATA output frequency is (24MHz * n * k) / m / 6. + * To get to 100MHz, k & m must be equal and n must be 25. + */ + m = k = 0; + n = 25; + + CLKDEV_DEVICE_LOCK(dev); + CLKDEV_READ_4(dev, reg, &val); + val &= ~(A10_PLL6_FACTOR_N | A10_PLL6_FACTOR_K | A10_PLL6_FACTOR_M); + val &= ~A10_PLL6_BYPASS_EN; + val |= A10_PLL6_SATA_CLK_EN; + val |= (n << A10_PLL6_FACTOR_N_SHIFT); + val |= (k << A10_PLL6_FACTOR_K_SHIFT); + val |= (m << A10_PLL6_FACTOR_M_SHIFT); + CLKDEV_WRITE_4(dev, reg, val); + CLKDEV_DEVICE_UNLOCK(dev); + + return (0); +} + +static int +a10_pll6_recalc(struct aw_pll_sc *sc, uint64_t *freq) +{ + uint32_t val, m, k, n; + + DEVICE_LOCK(sc); + PLL_READ(sc, &val); + DEVICE_UNLOCK(sc); + + m = ((val & A10_PLL6_FACTOR_M) >> A10_PLL6_FACTOR_M_SHIFT) + 1; + k = ((val & A10_PLL6_FACTOR_K) >> A10_PLL6_FACTOR_K_SHIFT) + 1; + n = (val & A10_PLL6_FACTOR_N) >> A10_PLL6_FACTOR_N_SHIFT; + if (n == 0) + return (ENXIO); + + switch (sc->id) { + case CLKID_A10_PLL6_SATA: + *freq = (*freq * n * k) / m / 6; + break; + case CLKID_A10_PLL6_OTHER: + *freq = (*freq * n * k) / 2; + break; + case CLKID_A10_PLL6: + *freq = (*freq * n * k); + break; + case CLKID_A10_PLL6_DIV_4: + *freq = (*freq * n * k) / 4; + break; + default: + return (ENXIO); + } + + return (0); +} + +static int +a10_pll6_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout, + int flags) +{ + if (sc->id != CLKID_A10_PLL6_SATA) + return (ENXIO); + + /* PLL6 SATA output has been set to 100MHz in a10_pll6_init */ + if (*fout != 100000000) + return (ERANGE); + + return (0); +} + +static int +a31_pll1_recalc(struct aw_pll_sc *sc, uint64_t *freq) +{ + uint32_t val, m, n, k; + + DEVICE_LOCK(sc); + PLL_READ(sc, &val); + DEVICE_UNLOCK(sc); + + m = ((val & A31_PLL1_FACTOR_M) >> A31_PLL1_FACTOR_M_SHIFT) + 1; + k = ((val & A31_PLL1_FACTOR_K) >> A31_PLL1_FACTOR_K_SHIFT) + 1; + n = ((val & A31_PLL1_FACTOR_N) >> A31_PLL1_FACTOR_N_SHIFT) + 1; + + *freq = (*freq * n * k) / m; + + return (0); +} + +static int +a31_pll6_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def) +{ + uint32_t val; + int retry; + + if (def->id != CLKID_A31_PLL6) + return (0); + + /* + * The datasheet recommends that PLL6 output should be fixed to + * 600MHz. + */ + CLKDEV_DEVICE_LOCK(dev); + CLKDEV_READ_4(dev, reg, &val); + val &= ~(A31_PLL6_FACTOR_N | A31_PLL6_FACTOR_K | A31_PLL6_BYPASS_EN); + val |= (A31_PLL6_DEFAULT_N << A31_PLL6_FACTOR_N_SHIFT); + val |= (A31_PLL6_DEFAULT_K << A31_PLL6_FACTOR_K_SHIFT); + CLKDEV_WRITE_4(dev, reg, val); + + /* Wait for PLL to become stable */ + for (retry = A31_PLL6_TIMEOUT; retry > 0; retry--) { + CLKDEV_READ_4(dev, reg, &val); + if ((val & A31_PLL6_LOCK) == A31_PLL6_LOCK) + break; + DELAY(1); + } + + CLKDEV_DEVICE_UNLOCK(dev); + + if (retry == 0) + return (ETIMEDOUT); + + return (0); +} + +static int +a31_pll6_recalc(struct aw_pll_sc *sc, uint64_t *freq) +{ + uint32_t val, k, n; + + DEVICE_LOCK(sc); + PLL_READ(sc, &val); + DEVICE_UNLOCK(sc); + + k = ((val & A10_PLL6_FACTOR_K) >> A10_PLL6_FACTOR_K_SHIFT) + 1; + n = ((val & A10_PLL6_FACTOR_N) >> A10_PLL6_FACTOR_N_SHIFT) + 1; + + switch (sc->id) { + case CLKID_A31_PLL6: + *freq = (*freq * n * k) / 2; + break; + case CLKID_A31_PLL6_X2: + *freq = *freq * n * k; + break; + default: + return (ENXIO); + } + + return (0); +} + +#define PLL(_type, _recalc, _set_freq, _init) \ + [(_type)] = { \ + .recalc = (_recalc), \ + .set_freq = (_set_freq), \ + .init = (_init) \ + } + +static struct aw_pll_funcs aw_pll_func[] = { + PLL(AWPLL_A10_PLL1, a10_pll1_recalc, NULL, NULL), + PLL(AWPLL_A10_PLL2, a10_pll2_recalc, a10_pll2_set_freq, NULL), + PLL(AWPLL_A10_PLL3, a10_pll3_recalc, a10_pll3_set_freq, a10_pll3_init), + PLL(AWPLL_A10_PLL5, a10_pll5_recalc, NULL, NULL), + PLL(AWPLL_A10_PLL6, a10_pll6_recalc, a10_pll6_set_freq, a10_pll6_init), + PLL(AWPLL_A31_PLL1, a31_pll1_recalc, NULL, NULL), + PLL(AWPLL_A31_PLL6, a31_pll6_recalc, NULL, a31_pll6_init), +}; + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun4i-a10-pll1-clk", AWPLL_A10_PLL1 }, + { "allwinner,sun4i-a10-pll2-clk", AWPLL_A10_PLL2 }, + { "allwinner,sun4i-a10-pll3-clk", AWPLL_A10_PLL3 }, + { "allwinner,sun4i-a10-pll5-clk", AWPLL_A10_PLL5 }, + { "allwinner,sun4i-a10-pll6-clk", AWPLL_A10_PLL6 }, + { "allwinner,sun6i-a31-pll1-clk", AWPLL_A31_PLL1 }, + { "allwinner,sun6i-a31-pll6-clk", AWPLL_A31_PLL6 }, + { NULL, 0 } +}; + +static int +aw_pll_init(struct clknode *clk, device_t dev) +{ + clknode_init_parent_idx(clk, 0); + return (0); +} + +static int +aw_pll_set_gate(struct clknode *clk, bool enable) +{ + struct aw_pll_sc *sc; + uint32_t val; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(sc); + PLL_READ(sc, &val); + if (enable) + val |= AW_PLL_ENABLE; + else + val &= ~AW_PLL_ENABLE; + PLL_WRITE(sc, val); + DEVICE_UNLOCK(sc); + + return (0); +} + +static int +aw_pll_recalc(struct clknode *clk, uint64_t *freq) +{ + struct aw_pll_sc *sc; + + sc = clknode_get_softc(clk); + + if (aw_pll_func[sc->type].recalc == NULL) + return (ENXIO); + + return (aw_pll_func[sc->type].recalc(sc, freq)); +} + +static int +aw_pll_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout, + int flags, int *stop) +{ + struct aw_pll_sc *sc; + + sc = clknode_get_softc(clk); + + *stop = 1; + + if (aw_pll_func[sc->type].set_freq == NULL) + return (ENXIO); + + return (aw_pll_func[sc->type].set_freq(sc, fin, fout, flags)); +} + +static clknode_method_t aw_pll_clknode_methods[] = { + /* Device interface */ + CLKNODEMETHOD(clknode_init, aw_pll_init), + CLKNODEMETHOD(clknode_set_gate, aw_pll_set_gate), + CLKNODEMETHOD(clknode_recalc_freq, aw_pll_recalc), + CLKNODEMETHOD(clknode_set_freq, aw_pll_set_freq), + CLKNODEMETHOD_END +}; + +DEFINE_CLASS_1(aw_pll_clknode, aw_pll_clknode_class, aw_pll_clknode_methods, + sizeof(struct aw_pll_sc), clknode_class); + +static int +aw_pll_create(device_t dev, bus_addr_t paddr, struct clkdom *clkdom, + const char *pclkname, const char *clkname, int index) +{ + enum aw_pll_type type; + struct clknode_init_def clkdef; + struct aw_pll_sc *sc; + struct clknode *clk; + int error; + + type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; + + memset(&clkdef, 0, sizeof(clkdef)); + clkdef.id = index; + clkdef.name = clkname; + if (pclkname != NULL) { + clkdef.parent_names = malloc(sizeof(char *), M_OFWPROP, + M_WAITOK); + clkdef.parent_names[0] = pclkname; + clkdef.parent_cnt = 1; + } else + clkdef.parent_cnt = 0; + + if (aw_pll_func[type].init != NULL) { + error = aw_pll_func[type].init(device_get_parent(dev), + paddr, &clkdef); + if (error != 0) { + device_printf(dev, "clock %s init failed\n", clkname); + return (error); + } + } + + clk = clknode_create(clkdom, &aw_pll_clknode_class, &clkdef); + if (clk == NULL) { + device_printf(dev, "cannot create clock node\n"); + return (ENXIO); + } + sc = clknode_get_softc(clk); + sc->clkdev = device_get_parent(dev); + sc->reg = paddr; + sc->type = type; + sc->id = clkdef.id; + + clknode_register(clkdom, clk); + + free(__DECONST(char *, clkdef.parent_names), M_OFWPROP); + + return (0); +} + +static int +aw_pll_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Allwinner PLL Clock"); + return (BUS_PROBE_DEFAULT); +} + +static int +aw_pll_attach(device_t dev) +{ + struct clkdom *clkdom; + const char **names; + int index, nout, error; + clk_t clk_parent; + uint32_t *indices; + bus_addr_t paddr; + bus_size_t psize; + phandle_t node; + + node = ofw_bus_get_node(dev); + + if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) { + device_printf(dev, "couldn't parse 'reg' property\n"); + return (ENXIO); + } + + clkdom = clkdom_create(dev); + + nout = clk_parse_ofw_out_names(dev, node, &names, &indices); + if (nout == 0) { + device_printf(dev, "no clock outputs found\n"); + error = ENOENT; + goto fail; + } + + if (clk_get_by_ofw_index(dev, 0, &clk_parent) != 0) + clk_parent = NULL; + + for (index = 0; index < nout; index++) { + error = aw_pll_create(dev, paddr, clkdom, + clk_parent ? clk_get_name(clk_parent) : NULL, + names[index], nout == 1 ? 1 : index); + if (error) + goto fail; + } + + if (clkdom_finit(clkdom) != 0) { + device_printf(dev, "cannot finalize clkdom initialization\n"); + error = ENXIO; + goto fail; + } + + if (bootverbose) + clkdom_dump(clkdom); + + return (0); + +fail: + return (error); +} + +static device_method_t aw_pll_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, aw_pll_probe), + DEVMETHOD(device_attach, aw_pll_attach), + + DEVMETHOD_END +}; + +static driver_t aw_pll_driver = { + "aw_pll", + aw_pll_methods, + 0, +}; + +static devclass_t aw_pll_devclass; + +EARLY_DRIVER_MODULE(aw_pll, simplebus, aw_pll_driver, + aw_pll_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Property changes on: head/sys/arm/allwinner/clk/aw_pll.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/allwinner/clk/aw_usbclk.c =================================================================== --- head/sys/arm/allwinner/clk/aw_usbclk.c (nonexistent) +++ head/sys/arm/allwinner/clk/aw_usbclk.c (revision 297627) @@ -0,0 +1,246 @@ +/*- + * Copyright (c) 2016 Jared McNeill + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Allwinner USB clocks + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "clkdev_if.h" +#include "hwreset_if.h" + +#define A10_SCLK_GATING_USBPHY (1 << 8) +#define A10_SCLK_GATING_OHCI1 (1 << 7) +#define A10_SCLK_GATING_OHCI0 (1 << 6) + +#define USBPHY2_RST (1 << 2) +#define USBPHY1_RST (1 << 1) +#define USBPHY0_RST (1 << 0) + +enum aw_usbclk_type { + AW_A10_USBCLK = 1, + AW_A31_USBCLK, +}; + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun4i-a10-usb-clk", AW_A10_USBCLK }, + { "allwinner,sun6i-a31-usb-clk", AW_A31_USBCLK }, + { NULL, 0 } +}; + +/* Clock indices for A10, as there is no clock-indices property in the DT */ +static uint32_t aw_usbclk_indices_a10[] = { 6, 7, 8 }; + +struct aw_usbclk_softc { + bus_addr_t reg; +}; + +static int +aw_usbclk_hwreset_assert(device_t dev, intptr_t id, bool value) +{ + struct aw_usbclk_softc *sc; + uint32_t mask; + device_t pdev; + int error; + + sc = device_get_softc(dev); + pdev = device_get_parent(dev); + + mask = USBPHY0_RST << id; + + CLKDEV_DEVICE_LOCK(pdev); + error = CLKDEV_MODIFY_4(pdev, sc->reg, mask, value ? 0 : mask); + CLKDEV_DEVICE_UNLOCK(pdev); + + return (error); +} + +static int +aw_usbclk_hwreset_is_asserted(device_t dev, intptr_t id, bool *value) +{ + struct aw_usbclk_softc *sc; + uint32_t mask, val; + device_t pdev; + int error; + + sc = device_get_softc(dev); + pdev = device_get_parent(dev); + + mask = USBPHY0_RST << id; + + CLKDEV_DEVICE_LOCK(pdev); + error = CLKDEV_READ_4(pdev, sc->reg, &val); + CLKDEV_DEVICE_UNLOCK(pdev); + + if (error) + return (error); + + *value = (val & mask) != 0 ? false : true; + + return (0); +} + +static int +aw_usbclk_create(device_t dev, bus_addr_t paddr, struct clkdom *clkdom, + const char *pclkname, const char *clkname, int index) +{ + const char *parent_names[1] = { pclkname }; + struct clk_gate_def def; + + memset(&def, 0, sizeof(def)); + def.clkdef.id = index; + def.clkdef.name = clkname; + def.clkdef.parent_names = parent_names; + def.clkdef.parent_cnt = 1; + def.offset = paddr; + def.shift = index; + def.mask = 1; + def.on_value = 1; + def.off_value = 0; + + return (clknode_gate_register(clkdom, &def)); +} + +static int +aw_usbclk_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Allwinner USB Clocks"); + return (BUS_PROBE_DEFAULT); +} + +static int +aw_usbclk_attach(device_t dev) +{ + struct aw_usbclk_softc *sc; + struct clkdom *clkdom; + const char **names; + int index, nout, error; + enum aw_usbclk_type type; + uint32_t *indices; + clk_t clk_parent; + bus_size_t psize; + phandle_t node; + + sc = device_get_softc(dev); + node = ofw_bus_get_node(dev); + indices = NULL; + type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; + + if (ofw_reg_to_paddr(node, 0, &sc->reg, &psize, NULL) != 0) { + device_printf(dev, "cannot parse 'reg' property\n"); + return (ENXIO); + } + + clkdom = clkdom_create(dev); + + nout = clk_parse_ofw_out_names(dev, node, &names, &indices); + if (nout == 0) { + device_printf(dev, "no clock outputs found\n"); + error = ENOENT; + goto fail; + } + + if (indices == NULL && type == AW_A10_USBCLK) + indices = aw_usbclk_indices_a10; + + error = clk_get_by_ofw_index(dev, 0, &clk_parent); + if (error != 0) { + device_printf(dev, "cannot parse clock parent\n"); + return (ENXIO); + } + + for (index = 0; index < nout; index++) { + error = aw_usbclk_create(dev, sc->reg, clkdom, + clk_get_name(clk_parent), names[index], + indices != NULL ? indices[index] : index); + if (error) + goto fail; + } + + if (clkdom_finit(clkdom) != 0) { + device_printf(dev, "cannot finalize clkdom initialization\n"); + error = ENXIO; + goto fail; + } + + if (bootverbose) + clkdom_dump(clkdom); + + hwreset_register_ofw_provider(dev); + + return (0); + +fail: + return (error); +} + +static device_method_t aw_usbclk_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, aw_usbclk_probe), + DEVMETHOD(device_attach, aw_usbclk_attach), + + /* Reset interface */ + DEVMETHOD(hwreset_assert, aw_usbclk_hwreset_assert), + DEVMETHOD(hwreset_is_asserted, aw_usbclk_hwreset_is_asserted), + + DEVMETHOD_END +}; + +static driver_t aw_usbclk_driver = { + "aw_usbclk", + aw_usbclk_methods, + sizeof(struct aw_usbclk_softc) +}; + +static devclass_t aw_usbclk_devclass; + +EARLY_DRIVER_MODULE(aw_usbclk, simplebus, aw_usbclk_driver, + aw_usbclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Property changes on: head/sys/arm/allwinner/clk/aw_usbclk.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/allwinner/files.allwinner =================================================================== --- head/sys/arm/allwinner/files.allwinner (revision 297626) +++ head/sys/arm/allwinner/files.allwinner (revision 297627) @@ -1,27 +1,44 @@ # $FreeBSD$ kern/kern_clocksource.c standard arm/allwinner/a10_ahci.c optional ahci -arm/allwinner/a10_clk.c standard arm/allwinner/a10_codec.c optional sound arm/allwinner/a10_common.c standard arm/allwinner/a10_dmac.c standard arm/allwinner/a10_ehci.c optional ehci arm/allwinner/aw_usbphy.c optional ehci arm/allwinner/a10_gpio.c optional gpio arm/allwinner/a10_mmc.c optional mmc arm/allwinner/a10_sramc.c standard arm/allwinner/aw_rtc.c standard arm/allwinner/aw_wdog.c standard arm/allwinner/a20/a20_cpu_cfg.c standard arm/allwinner/allwinner_machdep.c standard arm/allwinner/axp209.c optional axp209 arm/allwinner/if_emac.c optional emac arm/allwinner/sunxi_dma_if.m standard dev/iicbus/twsi/a10_twsi.c optional twsi #arm/allwinner/console.c standard arm/allwinner/a10_fb.c optional vt arm/allwinner/a10_hdmi.c optional hdmi arm/allwinner/a10_hdmiaudio.c optional hdmi sound arm/arm/hdmi_if.m optional hdmi + +arm/allwinner/aw_reset.c standard +arm/allwinner/aw_ccu.c standard +arm/allwinner/clk/aw_ahbclk.c standard +arm/allwinner/clk/aw_apbclk.c standard +arm/allwinner/clk/aw_axiclk.c standard +arm/allwinner/clk/aw_codecclk.c standard +arm/allwinner/clk/aw_cpuclk.c standard +arm/allwinner/clk/aw_debeclk.c standard +arm/allwinner/clk/aw_gate.c standard +arm/allwinner/clk/aw_gmacclk.c standard +arm/allwinner/clk/aw_hdmiclk.c standard +arm/allwinner/clk/aw_lcdclk.c standard +arm/allwinner/clk/aw_modclk.c standard +arm/allwinner/clk/aw_mmcclk.c standard +arm/allwinner/clk/aw_oscclk.c standard +arm/allwinner/clk/aw_pll.c standard +arm/allwinner/clk/aw_usbclk.c standard Index: head/sys/arm/allwinner/if_emac.c =================================================================== --- head/sys/arm/allwinner/if_emac.c (revision 297626) +++ head/sys/arm/allwinner/if_emac.c (revision 297627) @@ -1,1158 +1,1179 @@ /*- * Copyright (c) 2013 Ganbold Tsagaankhuu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* A10/A20 EMAC driver */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef INET #include #include #include #include #endif #include #include #include #include #include #include #include #include +#include + #include "miibus_if.h" #include "gpio_if.h" -#include "a10_clk.h" #include "a10_sramc.h" struct emac_softc { struct ifnet *emac_ifp; device_t emac_dev; device_t emac_miibus; bus_space_handle_t emac_handle; bus_space_tag_t emac_tag; struct resource *emac_res; struct resource *emac_irq; void *emac_intrhand; + clk_t emac_clk; int emac_if_flags; struct mtx emac_mtx; struct callout emac_tick_ch; int emac_watchdog_timer; int emac_rx_process_limit; int emac_link; uint32_t emac_fifo_mask; }; static int emac_probe(device_t); static int emac_attach(device_t); static int emac_detach(device_t); static int emac_shutdown(device_t); static int emac_suspend(device_t); static int emac_resume(device_t); -static void emac_sys_setup(void); +static int emac_sys_setup(struct emac_softc *); static void emac_reset(struct emac_softc *); static void emac_init_locked(struct emac_softc *); static void emac_start_locked(struct ifnet *); static void emac_init(void *); static void emac_stop_locked(struct emac_softc *); static void emac_intr(void *); static int emac_ioctl(struct ifnet *, u_long, caddr_t); static void emac_rxeof(struct emac_softc *, int); static void emac_txeof(struct emac_softc *, uint32_t); static int emac_miibus_readreg(device_t, int, int); static int emac_miibus_writereg(device_t, int, int, int); static void emac_miibus_statchg(device_t); static int emac_ifmedia_upd(struct ifnet *); static void emac_ifmedia_sts(struct ifnet *, struct ifmediareq *); static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); static int sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS); #define EMAC_READ_REG(sc, reg) \ bus_space_read_4(sc->emac_tag, sc->emac_handle, reg) #define EMAC_WRITE_REG(sc, reg, val) \ bus_space_write_4(sc->emac_tag, sc->emac_handle, reg, val) -static void -emac_sys_setup(void) +static int +emac_sys_setup(struct emac_softc *sc) { + int error; /* Activate EMAC clock. */ - a10_clk_emac_activate(); + error = clk_get_by_ofw_index(sc->emac_dev, 0, &sc->emac_clk); + if (error != 0) { + device_printf(sc->emac_dev, "cannot get clock\n"); + return (error); + } + error = clk_enable(sc->emac_clk); + if (error != 0) { + device_printf(sc->emac_dev, "cannot enable clock\n"); + return (error); + } + /* Map sram. */ a10_map_to_emac(); + + return (0); } static void emac_get_hwaddr(struct emac_softc *sc, uint8_t *hwaddr) { uint32_t val0, val1, rnd; /* * Try to get MAC address from running hardware. * If there is something non-zero there just use it. * * Otherwise set the address to a convenient locally assigned address, * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally * assigned bit set, and the broadcast/multicast bit clear. */ val0 = EMAC_READ_REG(sc, EMAC_MAC_A0); val1 = EMAC_READ_REG(sc, EMAC_MAC_A1); if ((val0 | val1) != 0 && (val0 | val1) != 0xffffff) { hwaddr[0] = (val1 >> 16) & 0xff; hwaddr[1] = (val1 >> 8) & 0xff; hwaddr[2] = (val1 >> 0) & 0xff; hwaddr[3] = (val0 >> 16) & 0xff; hwaddr[4] = (val0 >> 8) & 0xff; hwaddr[5] = (val0 >> 0) & 0xff; } else { rnd = arc4random() & 0x00ffffff; hwaddr[0] = 'b'; hwaddr[1] = 's'; hwaddr[2] = 'd'; hwaddr[3] = (rnd >> 16) & 0xff; hwaddr[4] = (rnd >> 8) & 0xff; hwaddr[5] = (rnd >> 0) & 0xff; } if (bootverbose) printf("MAC address: %s\n", ether_sprintf(hwaddr)); } static void emac_set_rx_mode(struct emac_softc *sc) { struct ifnet *ifp; struct ifmultiaddr *ifma; uint32_t h, hashes[2]; uint32_t rcr = 0; EMAC_ASSERT_LOCKED(sc); ifp = sc->emac_ifp; rcr = EMAC_READ_REG(sc, EMAC_RX_CTL); /* Unicast packet and DA filtering */ rcr |= EMAC_RX_UCAD; rcr |= EMAC_RX_DAF; hashes[0] = 0; hashes[1] = 0; if (ifp->if_flags & IFF_ALLMULTI) { hashes[0] = 0xffffffff; hashes[1] = 0xffffffff; } else { if_maddr_rlock(ifp); TAILQ_FOREACH(ifma, &sc->emac_ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; h = ether_crc32_be(LLADDR((struct sockaddr_dl *) ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; hashes[h >> 5] |= 1 << (h & 0x1f); } if_maddr_runlock(ifp); } rcr |= EMAC_RX_MCO; rcr |= EMAC_RX_MHF; EMAC_WRITE_REG(sc, EMAC_RX_HASH0, hashes[0]); EMAC_WRITE_REG(sc, EMAC_RX_HASH1, hashes[1]); if (ifp->if_flags & IFF_BROADCAST) { rcr |= EMAC_RX_BCO; rcr |= EMAC_RX_MCO; } if (ifp->if_flags & IFF_PROMISC) rcr |= EMAC_RX_PA; else rcr |= EMAC_RX_UCAD; EMAC_WRITE_REG(sc, EMAC_RX_CTL, rcr); } static void emac_reset(struct emac_softc *sc) { EMAC_WRITE_REG(sc, EMAC_CTL, 0); DELAY(200); EMAC_WRITE_REG(sc, EMAC_CTL, 1); DELAY(200); } static void emac_drain_rxfifo(struct emac_softc *sc) { uint32_t data; while (EMAC_READ_REG(sc, EMAC_RX_FBC) > 0) data = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); } static void emac_txeof(struct emac_softc *sc, uint32_t status) { struct ifnet *ifp; EMAC_ASSERT_LOCKED(sc); ifp = sc->emac_ifp; status &= (EMAC_TX_FIFO0 | EMAC_TX_FIFO1); sc->emac_fifo_mask &= ~status; if (status == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) if_inc_counter(ifp, IFCOUNTER_OPACKETS, 2); else if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; /* Unarm watchdog timer if no TX */ sc->emac_watchdog_timer = 0; } static void emac_rxeof(struct emac_softc *sc, int count) { struct ifnet *ifp; struct mbuf *m, *m0; uint32_t reg_val, rxcount; int16_t len; uint16_t status; int i; ifp = sc->emac_ifp; for (; count > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; count--) { /* * Race warning: The first packet might arrive with * the interrupts disabled, but the second will fix */ rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC); if (!rxcount) { /* Had one stuck? */ rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC); if (!rxcount) return; } /* Check packet header */ reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); if (reg_val != EMAC_PACKET_HEADER) { /* Packet header is wrong */ if (bootverbose) if_printf(ifp, "wrong packet header\n"); /* Disable RX */ reg_val = EMAC_READ_REG(sc, EMAC_CTL); reg_val &= ~EMAC_CTL_RX_EN; EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); /* Flush RX FIFO */ reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); reg_val |= EMAC_RX_FLUSH_FIFO; EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); for (i = 100; i > 0; i--) { DELAY(100); if ((EMAC_READ_REG(sc, EMAC_RX_CTL) & EMAC_RX_FLUSH_FIFO) == 0) break; } if (i == 0) { device_printf(sc->emac_dev, "flush FIFO timeout\n"); /* Reinitialize controller */ emac_init_locked(sc); return; } /* Enable RX */ reg_val = EMAC_READ_REG(sc, EMAC_CTL); reg_val |= EMAC_CTL_RX_EN; EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); return; } /* Get packet size and status */ reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); len = reg_val & 0xffff; status = (reg_val >> 16) & 0xffff; if (len < 64 || (status & EMAC_PKT_OK) == 0) { if (bootverbose) if_printf(ifp, "bad packet: len = %i status = %i\n", len, status); if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); emac_drain_rxfifo(sc); continue; } #if 0 if (status & (EMAC_CRCERR | EMAC_LENERR)) { good_packet = 0; if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); if (status & EMAC_CRCERR) if_printf(ifp, "crc error\n"); if (status & EMAC_LENERR) if_printf(ifp, "length error\n"); } #endif m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) { emac_drain_rxfifo(sc); return; } m->m_len = m->m_pkthdr.len = MCLBYTES; /* Copy entire frame to mbuf first. */ bus_space_read_multi_4(sc->emac_tag, sc->emac_handle, EMAC_RX_IO_DATA, mtod(m, uint32_t *), roundup2(len, 4) / 4); m->m_pkthdr.rcvif = ifp; m->m_len = m->m_pkthdr.len = len - ETHER_CRC_LEN; /* * Emac controller needs strict aligment, so to avoid * copying over an entire frame to align, we allocate * a new mbuf and copy ethernet header + IP header to * the new mbuf. The new mbuf is prepended into the * existing mbuf chain. */ if (m->m_len <= (MHLEN - ETHER_HDR_LEN)) { bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); m->m_data += ETHER_HDR_LEN; } else if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN) && m->m_len > (MHLEN - ETHER_HDR_LEN)) { MGETHDR(m0, M_NOWAIT, MT_DATA); if (m0 != NULL) { len = ETHER_HDR_LEN + m->m_pkthdr.l2hlen; bcopy(m->m_data, m0->m_data, len); m->m_data += len; m->m_len -= len; m0->m_len = len; M_MOVE_PKTHDR(m0, m); m0->m_next = m; m = m0; } else { if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); m_freem(m); m = NULL; continue; } } else if (m->m_len > EMAC_MAC_MAXF) { if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); m_freem(m); m = NULL; continue; } if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); EMAC_UNLOCK(sc); (*ifp->if_input)(ifp, m); EMAC_LOCK(sc); } } static void emac_watchdog(struct emac_softc *sc) { struct ifnet *ifp; EMAC_ASSERT_LOCKED(sc); if (sc->emac_watchdog_timer == 0 || --sc->emac_watchdog_timer) return; ifp = sc->emac_ifp; if (sc->emac_link == 0) { if (bootverbose) if_printf(sc->emac_ifp, "watchdog timeout " "(missed link)\n"); } else if_printf(sc->emac_ifp, "watchdog timeout -- resetting\n"); if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); ifp->if_drv_flags &= ~IFF_DRV_RUNNING; emac_init_locked(sc); if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) emac_start_locked(ifp); } static void emac_tick(void *arg) { struct emac_softc *sc; struct mii_data *mii; sc = (struct emac_softc *)arg; mii = device_get_softc(sc->emac_miibus); mii_tick(mii); emac_watchdog(sc); callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); } static void emac_init(void *xcs) { struct emac_softc *sc; sc = (struct emac_softc *)xcs; EMAC_LOCK(sc); emac_init_locked(sc); EMAC_UNLOCK(sc); } static void emac_init_locked(struct emac_softc *sc) { struct ifnet *ifp; struct mii_data *mii; uint32_t reg_val; uint8_t *eaddr; EMAC_ASSERT_LOCKED(sc); ifp = sc->emac_ifp; if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) return; /* Flush RX FIFO */ reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); reg_val |= EMAC_RX_FLUSH_FIFO; EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); DELAY(1); /* Soft reset MAC */ reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0); reg_val &= (~EMAC_MAC_CTL0_SOFT_RST); EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val); /* Set MII clock */ reg_val = EMAC_READ_REG(sc, EMAC_MAC_MCFG); reg_val &= (~(0xf << 2)); reg_val |= (0xd << 2); EMAC_WRITE_REG(sc, EMAC_MAC_MCFG, reg_val); /* Clear RX counter */ EMAC_WRITE_REG(sc, EMAC_RX_FBC, 0); /* Disable all interrupt and clear interrupt status */ EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); DELAY(1); /* Set up TX */ reg_val = EMAC_READ_REG(sc, EMAC_TX_MODE); reg_val |= EMAC_TX_AB_M; reg_val &= EMAC_TX_TM; EMAC_WRITE_REG(sc, EMAC_TX_MODE, reg_val); /* Set up RX */ reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); reg_val |= EMAC_RX_SETUP; reg_val &= EMAC_RX_TM; EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); /* Set up MAC CTL0. */ reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0); reg_val |= EMAC_MAC_CTL0_SETUP; EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val); /* Set up MAC CTL1. */ reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL1); reg_val |= EMAC_MAC_CTL1_SETUP; EMAC_WRITE_REG(sc, EMAC_MAC_CTL1, reg_val); /* Set up IPGT */ EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, EMAC_MAC_IPGT_FD); /* Set up IPGR */ EMAC_WRITE_REG(sc, EMAC_MAC_IPGR, EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8)); /* Set up Collison window */ EMAC_WRITE_REG(sc, EMAC_MAC_CLRT, EMAC_MAC_RM | (EMAC_MAC_CW << 8)); /* Set up Max Frame Length */ EMAC_WRITE_REG(sc, EMAC_MAC_MAXF, EMAC_MAC_MFL); /* Setup ethernet address */ eaddr = IF_LLADDR(ifp); EMAC_WRITE_REG(sc, EMAC_MAC_A1, eaddr[0] << 16 | eaddr[1] << 8 | eaddr[2]); EMAC_WRITE_REG(sc, EMAC_MAC_A0, eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); /* Setup rx filter */ emac_set_rx_mode(sc); /* Enable RX/TX0/RX Hlevel interrupt */ reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL); reg_val |= EMAC_INT_EN; EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val); ifp->if_drv_flags |= IFF_DRV_RUNNING; ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; sc->emac_link = 0; /* Switch to the current media. */ mii = device_get_softc(sc->emac_miibus); mii_mediachg(mii); callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); } static void emac_start(struct ifnet *ifp) { struct emac_softc *sc; sc = ifp->if_softc; EMAC_LOCK(sc); emac_start_locked(ifp); EMAC_UNLOCK(sc); } static void emac_start_locked(struct ifnet *ifp) { struct emac_softc *sc; struct mbuf *m, *m0; uint32_t fifo, reg; sc = ifp->if_softc; if (ifp->if_drv_flags & IFF_DRV_OACTIVE) return; if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) return; if (sc->emac_link == 0) return; IFQ_DRV_DEQUEUE(&ifp->if_snd, m); if (m == NULL) return; /* Select channel */ if (sc->emac_fifo_mask & EMAC_TX_FIFO0) fifo = 1; else fifo = 0; sc->emac_fifo_mask |= (1 << fifo); if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) ifp->if_drv_flags |= IFF_DRV_OACTIVE; EMAC_WRITE_REG(sc, EMAC_TX_INS, fifo); /* * Emac controller wants 4 byte aligned TX buffers. * We have to copy pretty much all the time. */ if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0) { m0 = m_defrag(m, M_NOWAIT); if (m0 == NULL) { m_freem(m); m = NULL; return; } m = m0; } /* Write data */ bus_space_write_multi_4(sc->emac_tag, sc->emac_handle, EMAC_TX_IO_DATA, mtod(m, uint32_t *), roundup2(m->m_len, 4) / 4); /* Send the data lengh. */ reg = (fifo == 0) ? EMAC_TX_PL0 : EMAC_TX_PL1; EMAC_WRITE_REG(sc, reg, m->m_len); /* Start translate from fifo to phy. */ reg = (fifo == 0) ? EMAC_TX_CTL0 : EMAC_TX_CTL1; EMAC_WRITE_REG(sc, reg, EMAC_READ_REG(sc, reg) | 1); /* Set timeout */ sc->emac_watchdog_timer = 5; /* Data have been sent to hardware, it is okay to free the mbuf now. */ BPF_MTAP(ifp, m); m_freem(m); } static void emac_stop_locked(struct emac_softc *sc) { struct ifnet *ifp; uint32_t reg_val; EMAC_ASSERT_LOCKED(sc); ifp = sc->emac_ifp; ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); sc->emac_link = 0; /* Disable all interrupt and clear interrupt status */ EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); /* Disable RX/TX */ reg_val = EMAC_READ_REG(sc, EMAC_CTL); reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN); EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); callout_stop(&sc->emac_tick_ch); } static void emac_intr(void *arg) { struct emac_softc *sc; struct ifnet *ifp; uint32_t reg_val; sc = (struct emac_softc *)arg; EMAC_LOCK(sc); /* Disable all interrupts */ EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); /* Get EMAC interrupt status */ reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); /* Clear ISR status */ EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); /* Received incoming packet */ if (reg_val & EMAC_INT_STA_RX) emac_rxeof(sc, sc->emac_rx_process_limit); /* Transmit Interrupt check */ if (reg_val & EMAC_INT_STA_TX) { emac_txeof(sc, reg_val); ifp = sc->emac_ifp; if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) emac_start_locked(ifp); } /* Re-enable interrupt mask */ reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL); reg_val |= EMAC_INT_EN; EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val); EMAC_UNLOCK(sc); } static int emac_ioctl(struct ifnet *ifp, u_long command, caddr_t data) { struct emac_softc *sc; struct mii_data *mii; struct ifreq *ifr; int error = 0; sc = ifp->if_softc; ifr = (struct ifreq *)data; switch (command) { case SIOCSIFFLAGS: EMAC_LOCK(sc); if (ifp->if_flags & IFF_UP) { if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { if ((ifp->if_flags ^ sc->emac_if_flags) & (IFF_PROMISC | IFF_ALLMULTI)) emac_set_rx_mode(sc); } else emac_init_locked(sc); } else { if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) emac_stop_locked(sc); } sc->emac_if_flags = ifp->if_flags; EMAC_UNLOCK(sc); break; case SIOCADDMULTI: case SIOCDELMULTI: EMAC_LOCK(sc); if (ifp->if_drv_flags & IFF_DRV_RUNNING) { emac_set_rx_mode(sc); } EMAC_UNLOCK(sc); break; case SIOCGIFMEDIA: case SIOCSIFMEDIA: mii = device_get_softc(sc->emac_miibus); error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); break; default: error = ether_ioctl(ifp, command, data); break; } return (error); } static int emac_probe(device_t dev) { if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-emac")) return (ENXIO); device_set_desc(dev, "A10/A20 EMAC ethernet controller"); return (BUS_PROBE_DEFAULT); } static int emac_detach(device_t dev) { struct emac_softc *sc; sc = device_get_softc(dev); sc->emac_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; if (device_is_attached(dev)) { ether_ifdetach(sc->emac_ifp); EMAC_LOCK(sc); emac_stop_locked(sc); EMAC_UNLOCK(sc); callout_drain(&sc->emac_tick_ch); } if (sc->emac_intrhand != NULL) bus_teardown_intr(sc->emac_dev, sc->emac_irq, sc->emac_intrhand); if (sc->emac_miibus != NULL) { device_delete_child(sc->emac_dev, sc->emac_miibus); bus_generic_detach(sc->emac_dev); } + if (sc->emac_clk != NULL) + clk_disable(sc->emac_clk); + if (sc->emac_res != NULL) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->emac_res); if (sc->emac_irq != NULL) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->emac_irq); if (sc->emac_ifp != NULL) if_free(sc->emac_ifp); if (mtx_initialized(&sc->emac_mtx)) mtx_destroy(&sc->emac_mtx); return (0); } static int emac_shutdown(device_t dev) { return (emac_suspend(dev)); } static int emac_suspend(device_t dev) { struct emac_softc *sc; struct ifnet *ifp; sc = device_get_softc(dev); EMAC_LOCK(sc); ifp = sc->emac_ifp; if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) emac_stop_locked(sc); EMAC_UNLOCK(sc); return (0); } static int emac_resume(device_t dev) { struct emac_softc *sc; struct ifnet *ifp; sc = device_get_softc(dev); EMAC_LOCK(sc); ifp = sc->emac_ifp; if ((ifp->if_flags & IFF_UP) != 0) { ifp->if_drv_flags &= ~IFF_DRV_RUNNING; emac_init_locked(sc); } EMAC_UNLOCK(sc); return (0); } static int emac_attach(device_t dev) { struct emac_softc *sc; struct ifnet *ifp; int error, rid; uint8_t eaddr[ETHER_ADDR_LEN]; sc = device_get_softc(dev); sc->emac_dev = dev; error = 0; mtx_init(&sc->emac_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); callout_init_mtx(&sc->emac_tick_ch, &sc->emac_mtx, 0); rid = 0; sc->emac_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->emac_res == NULL) { device_printf(dev, "unable to map memory\n"); error = ENXIO; goto fail; } sc->emac_tag = rman_get_bustag(sc->emac_res); sc->emac_handle = rman_get_bushandle(sc->emac_res); rid = 0; sc->emac_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); if (sc->emac_irq == NULL) { device_printf(dev, "cannot allocate IRQ resources.\n"); error = ENXIO; goto fail; } /* Create device sysctl node. */ SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, &sc->emac_rx_process_limit, 0, sysctl_hw_emac_proc_limit, "I", "max number of Rx events to process"); sc->emac_rx_process_limit = EMAC_PROC_DEFAULT; error = resource_int_value(device_get_name(dev), device_get_unit(dev), "process_limit", &sc->emac_rx_process_limit); if (error == 0) { if (sc->emac_rx_process_limit < EMAC_PROC_MIN || sc->emac_rx_process_limit > EMAC_PROC_MAX) { device_printf(dev, "process_limit value out of range; " "using default: %d\n", EMAC_PROC_DEFAULT); sc->emac_rx_process_limit = EMAC_PROC_DEFAULT; } } /* Setup EMAC */ - emac_sys_setup(); + error = emac_sys_setup(sc); + if (error != 0) + goto fail; + emac_reset(sc); ifp = sc->emac_ifp = if_alloc(IFT_ETHER); if (ifp == NULL) { device_printf(dev, "unable to allocate ifp\n"); error = ENOSPC; goto fail; } ifp->if_softc = sc; /* Setup MII */ error = mii_attach(dev, &sc->emac_miibus, ifp, emac_ifmedia_upd, emac_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); if (error != 0) { device_printf(dev, "PHY probe failed\n"); goto fail; } if_initname(ifp, device_get_name(dev), device_get_unit(dev)); ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_start = emac_start; ifp->if_ioctl = emac_ioctl; ifp->if_init = emac_init; IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); /* Get MAC address */ emac_get_hwaddr(sc, eaddr); ether_ifattach(ifp, eaddr); /* VLAN capability setup. */ ifp->if_capabilities |= IFCAP_VLAN_MTU; ifp->if_capenable = ifp->if_capabilities; /* Tell the upper layer we support VLAN over-sized frames. */ ifp->if_hdrlen = sizeof(struct ether_vlan_header); error = bus_setup_intr(dev, sc->emac_irq, INTR_TYPE_NET | INTR_MPSAFE, NULL, emac_intr, sc, &sc->emac_intrhand); if (error != 0) { device_printf(dev, "could not set up interrupt handler.\n"); ether_ifdetach(ifp); goto fail; } fail: if (error != 0) emac_detach(dev); return (error); } static boolean_t emac_miibus_iowait(struct emac_softc *sc) { uint32_t timeout; for (timeout = 100; timeout != 0; --timeout) { DELAY(100); if ((EMAC_READ_REG(sc, EMAC_MAC_MIND) & 0x1) == 0) return (true); } return (false); } /* * The MII bus interface */ static int emac_miibus_readreg(device_t dev, int phy, int reg) { struct emac_softc *sc; int rval; sc = device_get_softc(dev); /* Issue phy address and reg */ EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg); /* Pull up the phy io line */ EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1); if (!emac_miibus_iowait(sc)) { device_printf(dev, "timeout waiting for mii read\n"); return (0); } /* Push down the phy io line */ EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0); /* Read data */ rval = EMAC_READ_REG(sc, EMAC_MAC_MRDD); return (rval); } static int emac_miibus_writereg(device_t dev, int phy, int reg, int data) { struct emac_softc *sc; sc = device_get_softc(dev); /* Issue phy address and reg */ EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg); /* Write data */ EMAC_WRITE_REG(sc, EMAC_MAC_MWTD, data); /* Pull up the phy io line */ EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1); if (!emac_miibus_iowait(sc)) { device_printf(dev, "timeout waiting for mii write\n"); return (0); } /* Push down the phy io line */ EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0); return (0); } static void emac_miibus_statchg(device_t dev) { struct emac_softc *sc; struct mii_data *mii; struct ifnet *ifp; uint32_t reg_val; sc = device_get_softc(dev); mii = device_get_softc(sc->emac_miibus); ifp = sc->emac_ifp; if (mii == NULL || ifp == NULL || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) return; sc->emac_link = 0; if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == (IFM_ACTIVE | IFM_AVALID)) { switch (IFM_SUBTYPE(mii->mii_media_active)) { case IFM_10_T: case IFM_100_TX: sc->emac_link = 1; break; default: break; } } /* Program MACs with resolved speed/duplex. */ if (sc->emac_link != 0) { reg_val = EMAC_READ_REG(sc, EMAC_MAC_IPGT); if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { reg_val &= ~EMAC_MAC_IPGT_HD; reg_val |= EMAC_MAC_IPGT_FD; } else { reg_val &= ~EMAC_MAC_IPGT_FD; reg_val |= EMAC_MAC_IPGT_HD; } EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, reg_val); /* Enable RX/TX */ reg_val = EMAC_READ_REG(sc, EMAC_CTL); reg_val |= EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN; EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); } else { /* Disable RX/TX */ reg_val = EMAC_READ_REG(sc, EMAC_CTL); reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN); EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); } } static int emac_ifmedia_upd(struct ifnet *ifp) { struct emac_softc *sc; struct mii_data *mii; struct mii_softc *miisc; int error; sc = ifp->if_softc; mii = device_get_softc(sc->emac_miibus); EMAC_LOCK(sc); LIST_FOREACH(miisc, &mii->mii_phys, mii_list) PHY_RESET(miisc); error = mii_mediachg(mii); EMAC_UNLOCK(sc); return (error); } static void emac_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) { struct emac_softc *sc; struct mii_data *mii; sc = ifp->if_softc; mii = device_get_softc(sc->emac_miibus); EMAC_LOCK(sc); mii_pollstat(mii); ifmr->ifm_active = mii->mii_media_active; ifmr->ifm_status = mii->mii_media_status; EMAC_UNLOCK(sc); } static device_method_t emac_methods[] = { /* Device interface */ DEVMETHOD(device_probe, emac_probe), DEVMETHOD(device_attach, emac_attach), DEVMETHOD(device_detach, emac_detach), DEVMETHOD(device_shutdown, emac_shutdown), DEVMETHOD(device_suspend, emac_suspend), DEVMETHOD(device_resume, emac_resume), /* bus interface, for miibus */ DEVMETHOD(bus_print_child, bus_generic_print_child), DEVMETHOD(bus_driver_added, bus_generic_driver_added), /* MII interface */ DEVMETHOD(miibus_readreg, emac_miibus_readreg), DEVMETHOD(miibus_writereg, emac_miibus_writereg), DEVMETHOD(miibus_statchg, emac_miibus_statchg), DEVMETHOD_END }; static driver_t emac_driver = { "emac", emac_methods, sizeof(struct emac_softc) }; static devclass_t emac_devclass; DRIVER_MODULE(emac, simplebus, emac_driver, emac_devclass, 0, 0); DRIVER_MODULE(miibus, emac, miibus_driver, miibus_devclass, 0, 0); MODULE_DEPEND(emac, miibus, 1, 1, 1); MODULE_DEPEND(emac, ether, 1, 1, 1); static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) { int error, value; if (arg1 == NULL) return (EINVAL); value = *(int *)arg1; error = sysctl_handle_int(oidp, &value, 0, req); if (error || req->newptr == NULL) return (error); if (value < low || value > high) return (EINVAL); *(int *)arg1 = value; return (0); } static int sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS) { return (sysctl_int_range(oidp, arg1, arg2, req, EMAC_PROC_MIN, EMAC_PROC_MAX)); } Index: head/sys/arm/conf/A10 =================================================================== --- head/sys/arm/conf/A10 (revision 297626) +++ head/sys/arm/conf/A10 (revision 297627) @@ -1,112 +1,119 @@ # # A10 -- Custom configuration for the AllWinner A10 SoC # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ ident A10 include "std.armv6" include "../allwinner/std.a10" options SOC_ALLWINNER_A10 options HZ=100 options SCHED_4BSD # 4BSD scheduler options PLATFORM # Debugging for use in -current makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols options ALT_BREAK_TO_DEBUGGER #options VERBOSE_SYSINIT # Enable verbose sysinit messages options KDB # Enable kernel debugger support # For minimum debugger support (stable branch) use: #options KDB_TRACE # Print a stack trace for a panic # For full debugger support use this instead: options DDB # Enable the kernel debugger options INVARIANTS # Enable calls of extra sanity checking options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS options WITNESS # Enable checks to detect deadlocks and cycles options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed #options DIAGNOSTIC # NFS root from boopt/dhcp #options BOOTP #options BOOTP_NFSROOT #options BOOTP_COMPAT #options BOOTP_NFSV3 #options BOOTP_WIRED_TO=emac0 +# EXT_RESOURCES pseudo devices +options EXT_RESOURCES +device clk +device phy +device hwreset +device regulator + # MMC/SD/SDIO Card slot support device mmc # mmc/sd bus device mmcsd # mmc/sd flash cards # ATA controllers device ahci # AHCI-compatible SATA controllers #device ata # Legacy ATA/SATA controllers # Console and misc device uart device uart_snps device pty device snp device md device random # Entropy device # I2C support device iicbus device iic device twsi device axp209 # AXP209 Power Management Unit # GPIO device gpio device gpioled device scbus # SCSI bus (required for ATA/SCSI) device da # Direct Access (disks) device pass # Passthrough device (direct ATA/SCSI access) # USB support options USB_HOST_ALIGN=64 # Align usb buffers to cache line size. device usb options USB_DEBUG #options USB_REQ_DEBUG #options USB_VERBOSE #device uhci #device ohci device ehci device umass # Ethernet device loop device ether device mii device bpf device emac # USB ethernet support, requires miibus device miibus # Pinmux device fdt_pinctrl # Flattened Device Tree options FDT # Configure using FDT/DTB data makeoptions MODULES_EXTRA=dtb/allwinner Index: head/sys/arm/conf/A20 =================================================================== --- head/sys/arm/conf/A20 (revision 297626) +++ head/sys/arm/conf/A20 (revision 297627) @@ -1,134 +1,141 @@ # # A20 -- Custom configuration for the Allwinner A20 ARM SoC # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ ident A20 include "std.armv6" include "../allwinner/a20/std.a20" options ARM_INTRNG options SOC_ALLWINNER_A20 options HZ=100 options SCHED_ULE # ULE scheduler options SMP # Enable multiple cores options PLATFORM options PLATFORM_SMP # Debugging for use in -current makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols options ALT_BREAK_TO_DEBUGGER #options VERBOSE_SYSINIT # Enable verbose sysinit messages options KDB # Enable kernel debugger support # For minimum debugger support (stable branch) use: #options KDB_TRACE # Print a stack trace for a panic # For full debugger support use this instead: options DDB # Enable the kernel debugger options INVARIANTS # Enable calls of extra sanity checking options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS options WITNESS # Enable checks to detect deadlocks and cycles options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed #options DIAGNOSTIC # NFS root from boopt/dhcp #options BOOTP #options BOOTP_NFSROOT #options BOOTP_COMPAT #options BOOTP_NFSV3 #options BOOTP_WIRED_TO=dwc0 +# EXT_RESOURCES pseudo devices +options EXT_RESOURCES +device clk +device phy +device hwreset +device regulator + # Interrupt controller device gic # ARM Generic Timer device generic_timer # MMC/SD/SDIO Card slot support device mmc # mmc/sd bus device mmcsd # mmc/sd flash cards # ATA controllers device ahci # AHCI-compatible SATA controllers #device ata # Legacy ATA/SATA controllers # Console and misc device uart device uart_snps device pty device snp device md device random # Entropy device # I2C support device iicbus device iic device twsi device axp209 # AXP209 Power Management Unit # GPIO device gpio device gpioled device scbus # SCSI bus (required for ATA/SCSI) device da # Direct Access (disks) device pass # Passthrough device (direct ATA/SCSI access) # USB support options USB_HOST_ALIGN=64 # Align usb buffers to cache line size. device usb options USB_DEBUG #options USB_REQ_DEBUG #options USB_VERBOSE #device uhci #device ohci device ehci device umass # Ethernet device loop device ether device mii device bpf #device emac # 10/100 integrated EMAC controller device dwc # 10/100/1000 integrated GMAC controller # USB ethernet support, requires miibus device miibus # Sound support device sound # Pinmux device fdt_pinctrl # Framebuffer support device vt device kbdmux device ums device ukbd device videomode device hdmi # Flattened Device Tree options FDT # Configure using FDT/DTB data makeoptions MODULES_EXTRA=dtb/allwinner Index: head/sys/boot/fdt/dts/arm/sun7i-a20.dtsi =================================================================== --- head/sys/boot/fdt/dts/arm/sun7i-a20.dtsi (revision 297626) +++ head/sys/boot/fdt/dts/arm/sun7i-a20.dtsi (nonexistent) @@ -1,217 +0,0 @@ -/*- - * Copyright (c) 2014 Ganbold Tsagaankhuu - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#include -#include - -/ { - compatible = "allwinner,sun7i-a20"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&GIC>; - - aliases { - soc = &SOC; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - SOC: a20 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - bus-frequency = <0>; - - GIC: interrupt-controller@01c81000 { - compatible = "arm,gic"; - reg = <0x01c81000 0x1000>, /* Distributor Registers */ - <0x01c82000 0x0100>, /* CPU Interface Registers */ - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - sramc@01c00000 { - compatible = "allwinner,sun4i-sramc"; - #address-cells = <1>; - #size-cells = <1>; - reg = < 0x01c00000 0x1000 >; - }; - - cpu-cfg@01c25c00 { - compatible = "allwinner,sun7i-cpu-cfg"; - #address-cells = <1>; - #size-cells = <1>; - reg = < 0x01c25c00 0x400 >; - }; - - ccm@01c20000 { - compatible = "allwinner,sun4i-ccm"; - #address-cells = <1>; - #size-cells = <1>; - reg = < 0x01c20000 0x400 >; - }; - - timer@01c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0x90>; - interrupts = , - , - , - , - , - ; - interrupt-parent = <&GIC>; - clock-frequency = < 24000000 >; - }; - - watchdog@01c20c90 { - compatible = "allwinner,sun4i-a10-wdt"; - reg = <0x01c20c90 0x10>; - }; - - pio: gpio@01c20800 { - #gpio-cells = <3>; - compatible = "allwinner,sun7i-a20-pinctrl"; - gpio-controller; - reg =< 0x01c20800 0x400 >; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&GIC>; - - gmac_pins_mii: gmac_mii@0 { - allwinner,pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - allwinner,function = "gmac"; - allwinner,drive = ; - allwinner,pull = ; - }; - - gmac_pins_rgmii: gmac_rgmii@0 { - allwinner,pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA10", - "PA11", "PA12", "PA13", - "PA15", "PA16"; - allwinner,function = "gmac"; - allwinner,drive = ; - allwinner,pull = ; - }; - - }; - - usb1: usb@01c14000 { - compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; - reg = <0x01c14000 0x1000>; - interrupts = ; - interrupt-parent = <&GIC>; - }; - - usb2: usb@01c1c000 { - compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; - reg = <0x01c1c000 0x1000>; - interrupts = ; - interrupt-parent = <&GIC>; - }; - - mmc0: mmc@01c0f000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c0f000 0x1000>; - interrupts = ; - status = "disabled"; - }; - - sata@01c18000 { - compatible = "allwinner,sun4i-a10-ahci"; - reg = <0x01c18000 0x1000>; - interrupts = ; - interrupt-parent = <&GIC>; - status = "disabled"; - }; - - UART0: serial@01c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - reg-shift = <2>; - interrupts = ; - current-speed = <115200>; - clock-frequency = < 24000000 >; - }; - - emac@01c0b000 { - compatible = "allwinner,sun4i-a10-emac"; - reg = <0x01c0b000 0x1000>; - interrupts = ; - interrupt-parent = <&GIC>; - status = "disabled"; - }; - - gmac@01c50000 { - compatible = "allwinner,sun7i-a20-gmac"; - reg = <0x01c50000 0x10000>; - interrupts = ; - interrupt-parent = <&GIC>; - snps,pbl = <2>; - snps,fixed-burst; - snps,force_sf_dma_mode; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - dma: dma-controller@01c02000 { - compatible = "allwinner,sun4i-a10-dma"; - reg = <0x01c02000 0x1000>; - interrupts = <27>; - interrupt-parent = <&GIC>; - }; - - codec: codec@01c22c00 { - compatible = "allwinner,sun7i-a20-codec"; - reg = <0x01c22c00 0x40>; - interrupts = <30>; - interrupt-parent = <&GIC>; - status = "disabled"; - }; - }; -}; - Property changes on: head/sys/boot/fdt/dts/arm/sun7i-a20.dtsi ___________________________________________________________________ Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Index: head/sys/boot/fdt/dts/arm/sun4i-a10.dtsi =================================================================== --- head/sys/boot/fdt/dts/arm/sun4i-a10.dtsi (revision 297626) +++ head/sys/boot/fdt/dts/arm/sun4i-a10.dtsi (nonexistent) @@ -1,153 +0,0 @@ -/*- - * Copyright (c) 2014 Ganbold Tsagaankhuu - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#include - -/ { - compatible = "allwinner,sun4i-a10"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&AINTC>; - - aliases { - soc = &SOC; - }; - - SOC: a10 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - bus-frequency = <0>; - - AINTC: interrupt-controller@01c20400 { - compatible = "allwinner,sun4i-a10-ic"; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - reg = < 0x01c20400 0x400 >; - }; - - sramc@01c00000 { - compatible = "allwinner,sun4i-sramc"; - #address-cells = <1>; - #size-cells = <1>; - reg = < 0x01c00000 0x1000 >; - }; - - ccm@01c20000 { - compatible = "allwinner,sun4i-ccm"; - #address-cells = <1>; - #size-cells = <1>; - reg = < 0x01c20000 0x400 >; - }; - - timer@01c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0x90>; - interrupts = < 22 >; - interrupt-parent = <&AINTC>; - clock-frequency = < 24000000 >; - }; - - watchdog@01c20c90 { - compatible = "allwinner,sun4i-wdt"; - reg = <0x01c20c90 0x08>; - }; - - - GPIO: gpio@01c20800 { - #gpio-cells = <3>; - compatible = "allwinner,sun4i-a10-pinctrl"; - gpio-controller; - reg =< 0x01c20800 0x400 >; - interrupts = < 28 >; - interrupt-parent = <&AINTC>; - - emac_pins: emac@0 { - allwinner,pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - allwinner,function = "emac"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - usb1: usb@01c14000 { - compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; - reg = <0x01c14000 0x1000>; - interrupts = < 39 >; - interrupt-parent = <&AINTC>; - }; - - usb2: usb@01c1c000 { - compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; - reg = <0x01c1c000 0x1000>; - interrupts = < 40 >; - interrupt-parent = <&AINTC>; - }; - - mmc0: mmc@01c0f000 { - compatible = "allwinner,sun4i-a10-mmc"; - reg = <0x01c0f000 0x1000>; - interrupts = <32>; - interrupt-parent = <&AINTC>; - status = "disabled"; - }; - - sata@01c18000 { - compatible = "allwinner,sun4i-a10-ahci"; - reg = <0x01c18000 0x1000>; - interrupts = <56>; - interrupt-parent = <&AINTC>; - status = "disabled"; - }; - - UART0: serial@01c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - reg-shift = <2>; - interrupts = <1>; - interrupt-parent = <&AINTC>; - current-speed = <115200>; - clock-frequency = < 24000000 >; - }; - - emac@01c0b000 { - compatible = "allwinner,sun4i-a10-emac"; - reg = <0x01c0b000 0x1000>; - interrupts = <55>; - interrupt-parent = <&AINTC>; - }; - }; -}; - Property changes on: head/sys/boot/fdt/dts/arm/sun4i-a10.dtsi ___________________________________________________________________ Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Index: head/sys/boot/fdt/dts/arm/bananapi.dts =================================================================== --- head/sys/boot/fdt/dts/arm/bananapi.dts (revision 297626) +++ head/sys/boot/fdt/dts/arm/bananapi.dts (revision 297627) @@ -1,108 +1,46 @@ /*- * Copyright (c) 2013 Ganbold Tsagaankhuu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ -/dts-v1/; +#include "sun7i-a20-bananapi.dts" +#include "sun7i-a20-hdmi.dtsi" -#include "sun7i-a20.dtsi" - -#include - / { - model = "LeMaker Banana Pi"; - compatible = "lemaker,bananapi", "allwinner,sun7i-a20"; - - memory { - device_type = "memory"; - reg = < 0x40000000 0x40000000 >; /* 1GB RAM */ - }; - - aliases { - soc = &SOC; - UART0 = &UART0; - }; - - SOC: a20 { - - usb1: usb@01c14000 { + soc@01c00000 { + hdmi@01c16000 { status = "okay"; }; - usb2: usb@01c1c000 { + hdmiaudio { status = "okay"; }; - - UART0: serial@01c28000 { - status = "okay"; - }; - - mmc0: mmc@01c0f000 { - status = "okay"; - }; - - gmac@01c50000 { - phy-mode = "rgmii-bpi"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii>; - }; - - ahci: sata@01c18000 { - status = "okay"; - }; - - hdmi: hdmi@01c16000 { - compatible = "allwinner,sun7i-a20-hdmi"; - reg = <0x01c16000 0x1000>; - }; - - hdmiaudio { - compatible = "allwinner,sun7i-a20-hdmiaudio"; - }; - - fb: fb@01e60000 { - compatible = "allwinner,sun7i-a20-fb"; - reg = <0x01e60000 0x10000>, /* DEBE0 */ - <0x01c0c000 0x1000>; /* LCD0 */ - }; }; +}; - leds { - compatible = "gpio-leds"; - - green { - label = "bananapi:green:usr"; - gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; - }; - }; - - chosen { - bootargs = "-v"; - stdin = "UART0"; - stdout = "UART0"; - }; +&mmc0_pins_a { + allwinner,pull = ; }; Index: head/sys/boot/fdt/dts/arm/cubieboard.dts =================================================================== --- head/sys/boot/fdt/dts/arm/cubieboard.dts (revision 297626) +++ head/sys/boot/fdt/dts/arm/cubieboard.dts (revision 297627) @@ -1,81 +1,29 @@ /*- * Copyright (c) 2012 Ganbold Tsagaankhuu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ -/dts-v1/; - -#include "sun4i-a10.dtsi" - -/ { - model = "Cubietech Cubieboard"; - - memory { - device_type = "memory"; - reg = < 0x40000000 0x40000000 >; /* 1GB RAM */ - }; - - aliases { - soc = &SOC; - UART0 = &UART0; - }; - - SOC: a10 { - - usb1: usb@01c14000 { - status = "okay"; - }; - - usb2: usb@01c1c000 { - status = "okay"; - }; - - UART0: serial@01c28000 { - status = "okay"; - }; - - mmc0: mmc@01c0f000 { - status = "okay"; - }; - - emac@01c0b000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins>; - }; - - ahci: sata@01c18000 { - status = "okay"; - }; - }; - - chosen { - bootargs = "-v"; - stdin = "UART0"; - stdout = "UART0"; - }; -}; - +#include "sun4i-a10-cubieboard.dts" Index: head/sys/boot/fdt/dts/arm/cubieboard2.dts =================================================================== --- head/sys/boot/fdt/dts/arm/cubieboard2.dts (revision 297626) +++ head/sys/boot/fdt/dts/arm/cubieboard2.dts (revision 297627) @@ -1,50 +1,43 @@ /*- * Copyright (c) 2013 Ganbold Tsagaankhuu * Copyright (c) 2016 Emmanuel Vadot * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include "sun7i-a20-cubieboard2.dts" #include "sun7i-a20-hdmi.dtsi" / { soc@01c00000 { - ccm@01c20000 { - compatible = "allwinner,sun4i-ccm"; - #address-cells = <1>; - #size-cells = <1>; - reg = < 0x01c20000 0x400 >; - }; - hdmi@01c16000 { status = "okay"; }; hdmiaudio { status = "okay"; }; }; }; Index: head/sys/boot/fdt/dts/arm/olimex-a20-som-evb.dts =================================================================== --- head/sys/boot/fdt/dts/arm/olimex-a20-som-evb.dts (revision 297626) +++ head/sys/boot/fdt/dts/arm/olimex-a20-som-evb.dts (revision 297627) @@ -1,40 +1,42 @@ /*- * Copyright (c) 2015 Emmanuel Vadot * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include "sun7i-a20-olimex-som-evb.dts" +#include "sun7i-a20-hdmi.dtsi" / { soc@01c00000 { - ccm@01c20000 { - compatible = "allwinner,sun4i-ccm"; - #address-cells = <1>; - #size-cells = <1>; - reg = < 0x01c20000 0x400 >; + hdmi@01c16000 { + status = "okay"; + }; + + hdmiaudio { + status = "okay"; }; }; }; Index: head/sys/boot/fdt/dts/arm/olinuxino-lime.dts =================================================================== --- head/sys/boot/fdt/dts/arm/olinuxino-lime.dts (revision 297626) +++ head/sys/boot/fdt/dts/arm/olinuxino-lime.dts (revision 297627) @@ -1,40 +1,29 @@ /*- * Copyright (c) 2015 Emmanuel Vadot * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include "sun4i-a10-olinuxino-lime.dts" - -/ { - soc@01c00000 { - ccm@01c20000 { - compatible = "allwinner,sun4i-ccm"; - #address-cells = <1>; - #size-cells = <1>; - reg = < 0x01c20000 0x400 >; - }; - }; -}; Index: head/sys/boot/fdt/dts/arm/sun7i-a20-hdmi.dtsi =================================================================== --- head/sys/boot/fdt/dts/arm/sun7i-a20-hdmi.dtsi (revision 297626) +++ head/sys/boot/fdt/dts/arm/sun7i-a20-hdmi.dtsi (revision 297627) @@ -1,48 +1,111 @@ /*- * Copyright (c) 2016 Jared McNeill * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ / { + clocks { + pll3: clk@01c20010 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20010 0x4>; + clock-output-names = "pll3-1x", "pll3-2x"; + }; + + pll7: clk@01c20030 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20030 0x4>; + clock-output-names = "pll7-1x", "pll7-2x"; + }; + + hdmi_clk: clk@01c20150 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-hdmi-clk"; + reg = <0x01c20150 0x4>; + clocks = <&pll3 0>, <&pll7 0>, <&pll3 1>, <&pll7 1>; + clock-output-names = "hdmi"; + }; + + lcd0_ch0_clk: clk@01c20118 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-lcd-ch0-clk"; + reg = <0x01c20118 0x4>; + clocks = <&pll3 0>, <&pll7 0>, <&pll3 1>, <&pll6 2>; + clock-output-names = "lcd0_ch0"; + }; + + lcd0_ch1_clk: clk@01c2012c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-lcd-ch1-clk"; + reg = <0x01c2012c 0x4>; + clocks = <&pll3 0>, <&pll7 0>, <&pll3 1>, <&pll7 1>; + clock-output-names = "lcd0_ch1_sclk1", + "lcd0_ch1_sclk2"; + }; + + de_be0_clk: clk@01c20104 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-de-be-clk"; + reg = <0x01c20104 0x4>; + clocks = <&pll3 0>, <&pll7 0>, <&pll5 1>; + clock-output-names = "de_be0"; + }; + }; + soc@01c00000 { hdmi: hdmi@01c16000 { compatible = "allwinner,sun7i-a20-hdmi"; reg = <0x01c16000 0x1000>; + clocks = <&ahb_gates 43>, <&hdmi_clk>, + <&lcd0_ch1_clk 1>; + clock-names = "ahb", "hdmi", + "lcd"; status = "disabled"; }; hdmiaudio { compatible = "allwinner,sun7i-a20-hdmiaudio"; status = "disabled"; }; fb: fb@01e60000 { compatible = "allwinner,sun7i-a20-fb"; reg = <0x01e60000 0x10000>, /* DEBE0 */ <0x01c0c000 0x1000>; /* LCD0 */ + clocks = <&ahb_gates 44>, <&dram_gates 26>, + <&de_be0_clk>, <&ahb_gates 36>, + <&lcd0_ch1_clk 0>, <&lcd0_ch1_clk 1>; + clock-names = "ahb_de_be", "dram_de_be", + "de_be", "ahb_lcd", + "lcd_ch1_sclk1", "lcd_ch1_sclk2"; + resets = <&de_be0_clk>, <&lcd0_ch0_clk>; + reset-names = "de_be", "lcd"; }; }; }; Index: head/sys/dev/dwc/if_dwc.c =================================================================== --- head/sys/dev/dwc/if_dwc.c (revision 297626) +++ head/sys/dev/dwc/if_dwc.c (revision 297627) @@ -1,1339 +1,1379 @@ /*- * Copyright (c) 2014 Ruslan Bukin * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Ethernet media access controller (EMAC) * Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22) * * EMAC is an instance of the Synopsys DesignWare 3504-0 * Universal 10/100/1000 Ethernet MAC (DWC_gmac). */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include +#ifdef EXT_RESOURCES +#include +#include +#endif + #include "if_dwc_if.h" #include "gpio_if.h" #include "miibus_if.h" #define READ4(_sc, _reg) \ bus_read_4((_sc)->res[0], _reg) #define WRITE4(_sc, _reg, _val) \ bus_write_4((_sc)->res[0], _reg, _val) #define MAC_RESET_TIMEOUT 100 #define WATCHDOG_TIMEOUT_SECS 5 #define STATS_HARVEST_INTERVAL 2 #define DWC_LOCK(sc) mtx_lock(&(sc)->mtx) #define DWC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) #define DWC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) #define DWC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED) #define DDESC_TDES0_OWN (1U << 31) #define DDESC_TDES0_TXINT (1U << 30) #define DDESC_TDES0_TXLAST (1U << 29) #define DDESC_TDES0_TXFIRST (1U << 28) #define DDESC_TDES0_TXCRCDIS (1U << 27) #define DDESC_TDES0_TXRINGEND (1U << 21) #define DDESC_TDES0_TXCHAIN (1U << 20) #define DDESC_RDES0_OWN (1U << 31) #define DDESC_RDES0_FL_MASK 0x3fff #define DDESC_RDES0_FL_SHIFT 16 /* Frame Length */ #define DDESC_RDES1_CHAINED (1U << 14) /* Alt descriptor bits. */ #define DDESC_CNTL_TXINT (1U << 31) #define DDESC_CNTL_TXLAST (1U << 30) #define DDESC_CNTL_TXFIRST (1U << 29) #define DDESC_CNTL_TXCRCDIS (1U << 26) #define DDESC_CNTL_TXRINGEND (1U << 25) #define DDESC_CNTL_TXCHAIN (1U << 24) #define DDESC_CNTL_CHAINED (1U << 24) /* * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor * layout, but the bits in the fields have different meanings. */ struct dwc_hwdesc { uint32_t tdes0; /* status for alt layout */ uint32_t tdes1; /* cntl for alt layout */ uint32_t addr; /* pointer to buffer data */ uint32_t addr_next; /* link to next descriptor */ }; /* * The hardware imposes alignment restrictions on various objects involved in * DMA transfers. These values are expressed in bytes (not bits). */ #define DWC_DESC_RING_ALIGN 2048 static struct resource_spec dwc_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE }, { -1, 0 } }; static void dwc_txfinish_locked(struct dwc_softc *sc); static void dwc_rxfinish_locked(struct dwc_softc *sc); static void dwc_stop_locked(struct dwc_softc *sc); static void dwc_setup_rxfilter(struct dwc_softc *sc); static inline uint32_t next_rxidx(struct dwc_softc *sc, uint32_t curidx) { return ((curidx + 1) % RX_DESC_COUNT); } static inline uint32_t next_txidx(struct dwc_softc *sc, uint32_t curidx) { return ((curidx + 1) % TX_DESC_COUNT); } static void dwc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) { if (error != 0) return; *(bus_addr_t *)arg = segs[0].ds_addr; } inline static uint32_t dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr, uint32_t len) { uint32_t flags; uint32_t nidx; nidx = next_txidx(sc, idx); /* Addr/len 0 means we're clearing the descriptor after xmit done. */ if (paddr == 0 || len == 0) { flags = 0; --sc->txcount; } else { if (sc->mactype == DWC_GMAC_ALT_DESC) flags = DDESC_CNTL_TXCHAIN | DDESC_CNTL_TXFIRST | DDESC_CNTL_TXLAST | DDESC_CNTL_TXINT; else flags = DDESC_TDES0_TXCHAIN | DDESC_TDES0_TXFIRST | DDESC_TDES0_TXLAST | DDESC_TDES0_TXINT; ++sc->txcount; } sc->txdesc_ring[idx].addr = (uint32_t)(paddr); if (sc->mactype == DWC_GMAC_ALT_DESC) { sc->txdesc_ring[idx].tdes0 = 0; sc->txdesc_ring[idx].tdes1 = flags | len; } else { sc->txdesc_ring[idx].tdes0 = flags; sc->txdesc_ring[idx].tdes1 = len; } if (paddr && len) { wmb(); sc->txdesc_ring[idx].tdes0 |= DDESC_TDES0_OWN; wmb(); } return (nidx); } static int dwc_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp) { struct bus_dma_segment seg; int error, nsegs; struct mbuf * m; if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) return (ENOMEM); *mp = m; error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, m, &seg, &nsegs, 0); if (error != 0) { return (ENOMEM); } KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, BUS_DMASYNC_PREWRITE); sc->txbuf_map[idx].mbuf = m; dwc_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); return (0); } static void dwc_txstart_locked(struct dwc_softc *sc) { struct ifnet *ifp; struct mbuf *m; int enqueued; DWC_ASSERT_LOCKED(sc); if (!sc->link_is_up) return; ifp = sc->ifp; if (ifp->if_drv_flags & IFF_DRV_OACTIVE) { return; } enqueued = 0; for (;;) { if (sc->txcount == (TX_DESC_COUNT-1)) { ifp->if_drv_flags |= IFF_DRV_OACTIVE; break; } IFQ_DRV_DEQUEUE(&ifp->if_snd, m); if (m == NULL) break; if (dwc_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { IFQ_DRV_PREPEND(&ifp->if_snd, m); break; } BPF_MTAP(ifp, m); sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); ++enqueued; } if (enqueued != 0) { WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1); sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; } } static void dwc_txstart(struct ifnet *ifp) { struct dwc_softc *sc = ifp->if_softc; DWC_LOCK(sc); dwc_txstart_locked(sc); DWC_UNLOCK(sc); } static void dwc_stop_locked(struct dwc_softc *sc) { struct ifnet *ifp; uint32_t reg; DWC_ASSERT_LOCKED(sc); ifp = sc->ifp; ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); sc->tx_watchdog_count = 0; sc->stats_harvest_count = 0; callout_stop(&sc->dwc_callout); /* Stop DMA TX */ reg = READ4(sc, OPERATION_MODE); reg &= ~(MODE_ST); WRITE4(sc, OPERATION_MODE, reg); /* Flush TX */ reg = READ4(sc, OPERATION_MODE); reg |= (MODE_FTF); WRITE4(sc, OPERATION_MODE, reg); /* Stop transmitters */ reg = READ4(sc, MAC_CONFIGURATION); reg &= ~(CONF_TE | CONF_RE); WRITE4(sc, MAC_CONFIGURATION, reg); /* Stop DMA RX */ reg = READ4(sc, OPERATION_MODE); reg &= ~(MODE_SR); WRITE4(sc, OPERATION_MODE, reg); } static void dwc_clear_stats(struct dwc_softc *sc) { uint32_t reg; reg = READ4(sc, MMC_CONTROL); reg |= (MMC_CONTROL_CNTRST); WRITE4(sc, MMC_CONTROL, reg); } static void dwc_harvest_stats(struct dwc_softc *sc) { struct ifnet *ifp; /* We don't need to harvest too often. */ if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL) return; sc->stats_harvest_count = 0; ifp = sc->ifp; if_inc_counter(ifp, IFCOUNTER_IPACKETS, READ4(sc, RXFRAMECOUNT_GB)); if_inc_counter(ifp, IFCOUNTER_IMCASTS, READ4(sc, RXMULTICASTFRAMES_G)); if_inc_counter(ifp, IFCOUNTER_IERRORS, READ4(sc, RXOVERSIZE_G) + READ4(sc, RXUNDERSIZE_G) + READ4(sc, RXCRCERROR) + READ4(sc, RXALIGNMENTERROR) + READ4(sc, RXRUNTERROR) + READ4(sc, RXJABBERERROR) + READ4(sc, RXLENGTHERROR)); if_inc_counter(ifp, IFCOUNTER_OPACKETS, READ4(sc, TXFRAMECOUNT_G)); if_inc_counter(ifp, IFCOUNTER_OMCASTS, READ4(sc, TXMULTICASTFRAMES_G)); if_inc_counter(ifp, IFCOUNTER_OERRORS, READ4(sc, TXOVERSIZE_G) + READ4(sc, TXEXCESSDEF) + READ4(sc, TXCARRIERERR) + READ4(sc, TXUNDERFLOWERROR)); if_inc_counter(ifp, IFCOUNTER_COLLISIONS, READ4(sc, TXEXESSCOL) + READ4(sc, TXLATECOL)); dwc_clear_stats(sc); } static void dwc_tick(void *arg) { struct dwc_softc *sc; struct ifnet *ifp; int link_was_up; sc = arg; DWC_ASSERT_LOCKED(sc); ifp = sc->ifp; if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) return; /* * Typical tx watchdog. If this fires it indicates that we enqueued * packets for output and never got a txdone interrupt for them. Maybe * it's a missed interrupt somehow, just pretend we got one. */ if (sc->tx_watchdog_count > 0) { if (--sc->tx_watchdog_count == 0) { dwc_txfinish_locked(sc); } } /* Gather stats from hardware counters. */ dwc_harvest_stats(sc); /* Check the media status. */ link_was_up = sc->link_is_up; mii_tick(sc->mii_softc); if (sc->link_is_up && !link_was_up) dwc_txstart_locked(sc); /* Schedule another check one second from now. */ callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); } static void dwc_init_locked(struct dwc_softc *sc) { struct ifnet *ifp = sc->ifp; uint32_t reg; DWC_ASSERT_LOCKED(sc); if (ifp->if_drv_flags & IFF_DRV_RUNNING) return; ifp->if_drv_flags |= IFF_DRV_RUNNING; dwc_setup_rxfilter(sc); /* Initializa DMA and enable transmitters */ reg = READ4(sc, OPERATION_MODE); reg |= (MODE_TSF | MODE_OSF | MODE_FUF); reg &= ~(MODE_RSF); reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT); WRITE4(sc, OPERATION_MODE, reg); WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT); /* Start DMA */ reg = READ4(sc, OPERATION_MODE); reg |= (MODE_ST | MODE_SR); WRITE4(sc, OPERATION_MODE, reg); /* Enable transmitters */ reg = READ4(sc, MAC_CONFIGURATION); reg |= (CONF_JD | CONF_ACS | CONF_BE); reg |= (CONF_TE | CONF_RE); WRITE4(sc, MAC_CONFIGURATION, reg); /* * Call mii_mediachg() which will call back into dwc_miibus_statchg() * to set up the remaining config registers based on current media. */ mii_mediachg(sc->mii_softc); callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); } static void dwc_init(void *if_softc) { struct dwc_softc *sc = if_softc; DWC_LOCK(sc); dwc_init_locked(sc); DWC_UNLOCK(sc); } inline static uint32_t dwc_setup_rxdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr) { uint32_t nidx; sc->rxdesc_ring[idx].addr = (uint32_t)paddr; nidx = next_rxidx(sc, idx); sc->rxdesc_ring[idx].addr_next = sc->rxdesc_ring_paddr + \ (nidx * sizeof(struct dwc_hwdesc)); if (sc->mactype == DWC_GMAC_ALT_DESC) sc->rxdesc_ring[idx].tdes1 = DDESC_CNTL_CHAINED | RX_MAX_PACKET; else sc->rxdesc_ring[idx].tdes1 = DDESC_RDES1_CHAINED | MCLBYTES; wmb(); sc->rxdesc_ring[idx].tdes0 = DDESC_RDES0_OWN; wmb(); return (nidx); } static int dwc_setup_rxbuf(struct dwc_softc *sc, int idx, struct mbuf *m) { struct bus_dma_segment seg; int error, nsegs; m_adj(m, ETHER_ALIGN); error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, m, &seg, &nsegs, 0); if (error != 0) { return (error); } KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, BUS_DMASYNC_PREREAD); sc->rxbuf_map[idx].mbuf = m; dwc_setup_rxdesc(sc, idx, seg.ds_addr); return (0); } static struct mbuf * dwc_alloc_mbufcl(struct dwc_softc *sc) { struct mbuf *m; m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m != NULL) m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; return (m); } static void dwc_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) { struct dwc_softc *sc; struct mii_data *mii; sc = ifp->if_softc; mii = sc->mii_softc; DWC_LOCK(sc); mii_pollstat(mii); ifmr->ifm_active = mii->mii_media_active; ifmr->ifm_status = mii->mii_media_status; DWC_UNLOCK(sc); } static int dwc_media_change_locked(struct dwc_softc *sc) { return (mii_mediachg(sc->mii_softc)); } static int dwc_media_change(struct ifnet * ifp) { struct dwc_softc *sc; int error; sc = ifp->if_softc; DWC_LOCK(sc); error = dwc_media_change_locked(sc); DWC_UNLOCK(sc); return (error); } static const uint8_t nibbletab[] = { /* 0x0 0000 -> 0000 */ 0x0, /* 0x1 0001 -> 1000 */ 0x8, /* 0x2 0010 -> 0100 */ 0x4, /* 0x3 0011 -> 1100 */ 0xc, /* 0x4 0100 -> 0010 */ 0x2, /* 0x5 0101 -> 1010 */ 0xa, /* 0x6 0110 -> 0110 */ 0x6, /* 0x7 0111 -> 1110 */ 0xe, /* 0x8 1000 -> 0001 */ 0x1, /* 0x9 1001 -> 1001 */ 0x9, /* 0xa 1010 -> 0101 */ 0x5, /* 0xb 1011 -> 1101 */ 0xd, /* 0xc 1100 -> 0011 */ 0x3, /* 0xd 1101 -> 1011 */ 0xb, /* 0xe 1110 -> 0111 */ 0x7, /* 0xf 1111 -> 1111 */ 0xf, }; static uint8_t bitreverse(uint8_t x) { return (nibbletab[x & 0xf] << 4) | nibbletab[x >> 4]; } static void dwc_setup_rxfilter(struct dwc_softc *sc) { struct ifmultiaddr *ifma; struct ifnet *ifp; uint8_t *eaddr, val; uint32_t crc, ffval, hashbit, hashreg, hi, lo, reg; DWC_ASSERT_LOCKED(sc); ifp = sc->ifp; /* * Set the multicast (group) filter hash. */ if ((ifp->if_flags & IFF_ALLMULTI)) ffval = (FRAME_FILTER_PM); else { ffval = (FRAME_FILTER_HMC); if_maddr_rlock(ifp); TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) ifma->ifma_addr), ETHER_ADDR_LEN); /* Take lower 8 bits and reverse it */ val = bitreverse(~crc & 0xff); hashreg = (val >> 5); hashbit = (val & 31); reg = READ4(sc, HASH_TABLE_REG(hashreg)); reg |= (1 << hashbit); WRITE4(sc, HASH_TABLE_REG(hashreg), reg); } if_maddr_runlock(ifp); } /* * Set the individual address filter hash. */ if (ifp->if_flags & IFF_PROMISC) ffval |= (FRAME_FILTER_PR); /* * Set the primary address. */ eaddr = IF_LLADDR(ifp); lo = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) | (eaddr[3] << 24); hi = eaddr[4] | (eaddr[5] << 8); WRITE4(sc, MAC_ADDRESS_LOW(0), lo); WRITE4(sc, MAC_ADDRESS_HIGH(0), hi); WRITE4(sc, MAC_FRAME_FILTER, ffval); } static int dwc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) { struct dwc_softc *sc; struct mii_data *mii; struct ifreq *ifr; int mask, error; sc = ifp->if_softc; ifr = (struct ifreq *)data; error = 0; switch (cmd) { case SIOCSIFFLAGS: DWC_LOCK(sc); if (ifp->if_flags & IFF_UP) { if (ifp->if_drv_flags & IFF_DRV_RUNNING) { if ((ifp->if_flags ^ sc->if_flags) & (IFF_PROMISC | IFF_ALLMULTI)) dwc_setup_rxfilter(sc); } else { if (!sc->is_detaching) dwc_init_locked(sc); } } else { if (ifp->if_drv_flags & IFF_DRV_RUNNING) dwc_stop_locked(sc); } sc->if_flags = ifp->if_flags; DWC_UNLOCK(sc); break; case SIOCADDMULTI: case SIOCDELMULTI: if (ifp->if_drv_flags & IFF_DRV_RUNNING) { DWC_LOCK(sc); dwc_setup_rxfilter(sc); DWC_UNLOCK(sc); } break; case SIOCSIFMEDIA: case SIOCGIFMEDIA: mii = sc->mii_softc; error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); break; case SIOCSIFCAP: mask = ifp->if_capenable ^ ifr->ifr_reqcap; if (mask & IFCAP_VLAN_MTU) { /* No work to do except acknowledge the change took */ ifp->if_capenable ^= IFCAP_VLAN_MTU; } break; default: error = ether_ioctl(ifp, cmd, data); break; } return (error); } static void dwc_txfinish_locked(struct dwc_softc *sc) { struct dwc_bufmap *bmap; struct dwc_hwdesc *desc; struct ifnet *ifp; DWC_ASSERT_LOCKED(sc); ifp = sc->ifp; while (sc->tx_idx_tail != sc->tx_idx_head) { desc = &sc->txdesc_ring[sc->tx_idx_tail]; if ((desc->tdes0 & DDESC_TDES0_OWN) != 0) break; bmap = &sc->txbuf_map[sc->tx_idx_tail]; bus_dmamap_sync(sc->txbuf_tag, bmap->map, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(sc->txbuf_tag, bmap->map); m_freem(bmap->mbuf); bmap->mbuf = NULL; dwc_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); } /* If there are no buffers outstanding, muzzle the watchdog. */ if (sc->tx_idx_tail == sc->tx_idx_head) { sc->tx_watchdog_count = 0; } } static void dwc_rxfinish_locked(struct dwc_softc *sc) { struct ifnet *ifp; struct mbuf *m0; struct mbuf *m; int error, idx, len; uint32_t rdes0; ifp = sc->ifp; for (;;) { idx = sc->rx_idx; rdes0 = sc->rxdesc_ring[idx].tdes0; if ((rdes0 & DDESC_RDES0_OWN) != 0) break; bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, BUS_DMASYNC_POSTREAD); bus_dmamap_unload(sc->rxbuf_tag, sc->rxbuf_map[idx].map); len = (rdes0 >> DDESC_RDES0_FL_SHIFT) & DDESC_RDES0_FL_MASK; if (len != 0) { m = sc->rxbuf_map[idx].mbuf; m->m_pkthdr.rcvif = ifp; m->m_pkthdr.len = len; m->m_len = len; if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); DWC_UNLOCK(sc); (*ifp->if_input)(ifp, m); DWC_LOCK(sc); } else { /* XXX Zero-length packet ? */ } if ((m0 = dwc_alloc_mbufcl(sc)) != NULL) { if ((error = dwc_setup_rxbuf(sc, idx, m0)) != 0) { /* * XXX Now what? * We've got a hole in the rx ring. */ } } else if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); sc->rx_idx = next_rxidx(sc, sc->rx_idx); } } static void dwc_intr(void *arg) { struct dwc_softc *sc; uint32_t reg; sc = arg; DWC_LOCK(sc); reg = READ4(sc, INTERRUPT_STATUS); if (reg) READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS); reg = READ4(sc, DMA_STATUS); if (reg & DMA_STATUS_NIS) { if (reg & DMA_STATUS_RI) dwc_rxfinish_locked(sc); if (reg & DMA_STATUS_TI) { dwc_txfinish_locked(sc); dwc_txstart_locked(sc); } } if (reg & DMA_STATUS_AIS) { if (reg & DMA_STATUS_FBI) { /* Fatal bus error */ device_printf(sc->dev, "Ethernet DMA error, restarting controller.\n"); dwc_stop_locked(sc); dwc_init_locked(sc); } } WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK); DWC_UNLOCK(sc); } static int setup_dma(struct dwc_softc *sc) { struct mbuf *m; int error; int nidx; int idx; /* * Set up TX descriptor ring, descriptors, and dma maps. */ error = bus_dma_tag_create( bus_get_dma_tag(sc->dev), /* Parent tag. */ DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ TX_DESC_SIZE, 1, /* maxsize, nsegments */ TX_DESC_SIZE, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->txdesc_tag); if (error != 0) { device_printf(sc->dev, "could not create TX ring DMA tag.\n"); goto out; } error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map); if (error != 0) { device_printf(sc->dev, "could not allocate TX descriptor ring.\n"); goto out; } error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring, TX_DESC_SIZE, dwc_get1paddr, &sc->txdesc_ring_paddr, 0); if (error != 0) { device_printf(sc->dev, "could not load TX descriptor ring map.\n"); goto out; } for (idx = 0; idx < TX_DESC_COUNT; idx++) { nidx = next_txidx(sc, idx); sc->txdesc_ring[idx].addr_next = sc->txdesc_ring_paddr + (nidx * sizeof(struct dwc_hwdesc)); } error = bus_dma_tag_create( bus_get_dma_tag(sc->dev), /* Parent tag. */ 1, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ MCLBYTES, 1, /* maxsize, nsegments */ MCLBYTES, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->txbuf_tag); if (error != 0) { device_printf(sc->dev, "could not create TX ring DMA tag.\n"); goto out; } for (idx = 0; idx < TX_DESC_COUNT; idx++) { error = bus_dmamap_create(sc->txbuf_tag, BUS_DMA_COHERENT, &sc->txbuf_map[idx].map); if (error != 0) { device_printf(sc->dev, "could not create TX buffer DMA map.\n"); goto out; } dwc_setup_txdesc(sc, idx, 0, 0); } /* * Set up RX descriptor ring, descriptors, dma maps, and mbufs. */ error = bus_dma_tag_create( bus_get_dma_tag(sc->dev), /* Parent tag. */ DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ RX_DESC_SIZE, 1, /* maxsize, nsegments */ RX_DESC_SIZE, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->rxdesc_tag); if (error != 0) { device_printf(sc->dev, "could not create RX ring DMA tag.\n"); goto out; } error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map); if (error != 0) { device_printf(sc->dev, "could not allocate RX descriptor ring.\n"); goto out; } error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring, RX_DESC_SIZE, dwc_get1paddr, &sc->rxdesc_ring_paddr, 0); if (error != 0) { device_printf(sc->dev, "could not load RX descriptor ring map.\n"); goto out; } error = bus_dma_tag_create( bus_get_dma_tag(sc->dev), /* Parent tag. */ 1, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ MCLBYTES, 1, /* maxsize, nsegments */ MCLBYTES, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->rxbuf_tag); if (error != 0) { device_printf(sc->dev, "could not create RX buf DMA tag.\n"); goto out; } for (idx = 0; idx < RX_DESC_COUNT; idx++) { error = bus_dmamap_create(sc->rxbuf_tag, BUS_DMA_COHERENT, &sc->rxbuf_map[idx].map); if (error != 0) { device_printf(sc->dev, "could not create RX buffer DMA map.\n"); goto out; } if ((m = dwc_alloc_mbufcl(sc)) == NULL) { device_printf(sc->dev, "Could not alloc mbuf\n"); error = ENOMEM; goto out; } if ((error = dwc_setup_rxbuf(sc, idx, m)) != 0) { device_printf(sc->dev, "could not create new RX buffer.\n"); goto out; } } out: if (error != 0) return (ENXIO); return (0); } static int dwc_get_hwaddr(struct dwc_softc *sc, uint8_t *hwaddr) { uint32_t hi, lo, rnd; /* * Try to recover a MAC address from the running hardware. If there's * something non-zero there, assume the bootloader did the right thing * and just use it. * * Otherwise, set the address to a convenient locally assigned address, * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally * assigned bit set, and the broadcast/multicast bit clear. */ lo = READ4(sc, MAC_ADDRESS_LOW(0)); hi = READ4(sc, MAC_ADDRESS_HIGH(0)) & 0xffff; if ((lo != 0xffffffff) || (hi != 0xffff)) { hwaddr[0] = (lo >> 0) & 0xff; hwaddr[1] = (lo >> 8) & 0xff; hwaddr[2] = (lo >> 16) & 0xff; hwaddr[3] = (lo >> 24) & 0xff; hwaddr[4] = (hi >> 0) & 0xff; hwaddr[5] = (hi >> 8) & 0xff; } else { rnd = arc4random() & 0x00ffffff; hwaddr[0] = 'b'; hwaddr[1] = 's'; hwaddr[2] = 'd'; hwaddr[3] = rnd >> 16; hwaddr[4] = rnd >> 8; hwaddr[5] = rnd >> 0; } return (0); } #define GPIO_ACTIVE_LOW 1 static int dwc_reset(device_t dev) { pcell_t gpio_prop[4]; pcell_t delay_prop[3]; phandle_t node, gpio_node; device_t gpio; uint32_t pin, flags; uint32_t pin_value; node = ofw_bus_get_node(dev); if (OF_getencprop(node, "snps,reset-gpio", gpio_prop, sizeof(gpio_prop)) <= 0) return (0); if (OF_getencprop(node, "snps,reset-delays-us", delay_prop, sizeof(delay_prop)) <= 0) { device_printf(dev, "Wrong property for snps,reset-delays-us"); return (ENXIO); } gpio_node = OF_node_from_xref(gpio_prop[0]); if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL) { device_printf(dev, "Can't find gpio controller for phy reset\n"); return (ENXIO); } if (GPIO_MAP_GPIOS(gpio, node, gpio_node, sizeof(gpio_prop) / sizeof(gpio_prop[0]) - 1, gpio_prop + 1, &pin, &flags) != 0) { device_printf(dev, "Can't map gpio for phy reset\n"); return (ENXIO); } pin_value = GPIO_PIN_LOW; if (OF_hasprop(node, "snps,reset-active-low")) pin_value = GPIO_PIN_HIGH; if (flags & GPIO_ACTIVE_LOW) pin_value = !pin_value; GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT); GPIO_PIN_SET(gpio, pin, pin_value); DELAY(delay_prop[0]); GPIO_PIN_SET(gpio, pin, !pin_value); DELAY(delay_prop[1]); GPIO_PIN_SET(gpio, pin, pin_value); DELAY(delay_prop[2]); return (0); } +#ifdef EXT_RESOURCES static int +dwc_clock_init(device_t dev) +{ + hwreset_t rst; + clk_t clk; + int error; + + /* Enable clock */ + if (clk_get_by_ofw_name(dev, "stmmaceth", &clk) == 0) { + error = clk_enable(clk); + if (error != 0) { + device_printf(dev, "could not enable main clock\n"); + return (error); + } + } + + /* De-assert reset */ + if (hwreset_get_by_ofw_name(dev, "stmmaceth", &rst) == 0) { + error = hwreset_deassert(rst); + if (error != 0) { + device_printf(dev, "could not de-assert reset\n"); + return (error); + } + } + + return (0); +} +#endif + +static int dwc_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "snps,dwmac")) return (ENXIO); device_set_desc(dev, "Gigabit Ethernet Controller"); return (BUS_PROBE_DEFAULT); } static int dwc_attach(device_t dev) { uint8_t macaddr[ETHER_ADDR_LEN]; struct dwc_softc *sc; struct ifnet *ifp; int error, i; uint32_t reg; sc = device_get_softc(dev); sc->dev = dev; sc->rx_idx = 0; sc->txcount = TX_DESC_COUNT; sc->mii_clk = IF_DWC_MII_CLK(dev); sc->mactype = IF_DWC_MAC_TYPE(dev); if (IF_DWC_INIT(dev) != 0) return (ENXIO); + +#ifdef EXT_RESOURCES + if (dwc_clock_init(dev) != 0) + return (ENXIO); +#endif if (bus_alloc_resources(dev, dwc_spec, sc->res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } /* Memory interface */ sc->bst = rman_get_bustag(sc->res[0]); sc->bsh = rman_get_bushandle(sc->res[0]); /* Read MAC before reset */ if (dwc_get_hwaddr(sc, macaddr)) { device_printf(sc->dev, "can't get mac\n"); return (ENXIO); } /* Reset the PHY if needed */ if (dwc_reset(dev) != 0) { device_printf(dev, "Can't reset the PHY\n"); return (ENXIO); } /* Reset */ reg = READ4(sc, BUS_MODE); reg |= (BUS_MODE_SWR); WRITE4(sc, BUS_MODE, reg); for (i = 0; i < MAC_RESET_TIMEOUT; i++) { if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0) break; DELAY(10); } if (i >= MAC_RESET_TIMEOUT) { device_printf(sc->dev, "Can't reset DWC.\n"); return (ENXIO); } if (sc->mactype == DWC_GMAC_ALT_DESC) { reg = BUS_MODE_FIXEDBURST; reg |= (BUS_MODE_PRIORXTX_41 << BUS_MODE_PRIORXTX_SHIFT); } else reg = (BUS_MODE_EIGHTXPBL); reg |= (BUS_MODE_PBL_BEATS_8 << BUS_MODE_PBL_SHIFT); WRITE4(sc, BUS_MODE, reg); /* * DMA must be stop while changing descriptor list addresses. */ reg = READ4(sc, OPERATION_MODE); reg &= ~(MODE_ST | MODE_SR); WRITE4(sc, OPERATION_MODE, reg); if (setup_dma(sc)) return (ENXIO); /* Setup addresses */ WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr); WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr); mtx_init(&sc->mtx, device_get_nameunit(sc->dev), MTX_NETWORK_LOCK, MTX_DEF); callout_init_mtx(&sc->dwc_callout, &sc->mtx, 0); /* Setup interrupt handler. */ error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, NULL, dwc_intr, sc, &sc->intr_cookie); if (error != 0) { device_printf(dev, "could not setup interrupt handler.\n"); return (ENXIO); } /* Set up the ethernet interface. */ sc->ifp = ifp = if_alloc(IFT_ETHER); ifp->if_softc = sc; if_initname(ifp, device_get_name(dev), device_get_unit(dev)); ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_capabilities = IFCAP_VLAN_MTU; ifp->if_capenable = ifp->if_capabilities; ifp->if_start = dwc_txstart; ifp->if_ioctl = dwc_ioctl; ifp->if_init = dwc_init; IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; IFQ_SET_READY(&ifp->if_snd); /* Attach the mii driver. */ error = mii_attach(dev, &sc->miibus, ifp, dwc_media_change, dwc_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); if (error != 0) { device_printf(dev, "PHY attach failed\n"); return (ENXIO); } sc->mii_softc = device_get_softc(sc->miibus); /* All ready to run, attach the ethernet interface. */ ether_ifattach(ifp, macaddr); sc->is_attached = true; return (0); } static int dwc_miibus_read_reg(device_t dev, int phy, int reg) { struct dwc_softc *sc; uint16_t mii; size_t cnt; int rv = 0; sc = device_get_softc(dev); mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) | GMII_ADDRESS_GB; /* Busy flag */ WRITE4(sc, GMII_ADDRESS, mii); for (cnt = 0; cnt < 1000; cnt++) { if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { rv = READ4(sc, GMII_DATA); break; } DELAY(10); } return rv; } static int dwc_miibus_write_reg(device_t dev, int phy, int reg, int val) { struct dwc_softc *sc; uint16_t mii; size_t cnt; sc = device_get_softc(dev); mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) | GMII_ADDRESS_GB | GMII_ADDRESS_GW; WRITE4(sc, GMII_DATA, val); WRITE4(sc, GMII_ADDRESS, mii); for (cnt = 0; cnt < 1000; cnt++) { if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { break; } DELAY(10); } return (0); } static void dwc_miibus_statchg(device_t dev) { struct dwc_softc *sc; struct mii_data *mii; uint32_t reg; /* * Called by the MII bus driver when the PHY establishes * link to set the MAC interface registers. */ sc = device_get_softc(dev); DWC_ASSERT_LOCKED(sc); mii = sc->mii_softc; if (mii->mii_media_status & IFM_ACTIVE) sc->link_is_up = true; else sc->link_is_up = false; reg = READ4(sc, MAC_CONFIGURATION); switch (IFM_SUBTYPE(mii->mii_media_active)) { case IFM_1000_T: case IFM_1000_SX: reg &= ~(CONF_FES | CONF_PS); break; case IFM_100_TX: reg |= (CONF_FES | CONF_PS); break; case IFM_10_T: reg &= ~(CONF_FES); reg |= (CONF_PS); break; case IFM_NONE: sc->link_is_up = false; return; default: sc->link_is_up = false; device_printf(dev, "Unsupported media %u\n", IFM_SUBTYPE(mii->mii_media_active)); return; } if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) reg |= (CONF_DM); else reg &= ~(CONF_DM); WRITE4(sc, MAC_CONFIGURATION, reg); } static device_method_t dwc_methods[] = { DEVMETHOD(device_probe, dwc_probe), DEVMETHOD(device_attach, dwc_attach), /* MII Interface */ DEVMETHOD(miibus_readreg, dwc_miibus_read_reg), DEVMETHOD(miibus_writereg, dwc_miibus_write_reg), DEVMETHOD(miibus_statchg, dwc_miibus_statchg), { 0, 0 } }; driver_t dwc_driver = { "dwc", dwc_methods, sizeof(struct dwc_softc), }; static devclass_t dwc_devclass; DRIVER_MODULE(dwc, simplebus, dwc_driver, dwc_devclass, 0, 0); DRIVER_MODULE(miibus, dwc, miibus_driver, miibus_devclass, 0, 0); MODULE_DEPEND(dwc, ether, 1, 1, 1); MODULE_DEPEND(dwc, miibus, 1, 1, 1); Index: head/sys/dev/iicbus/twsi/a10_twsi.c =================================================================== --- head/sys/dev/iicbus/twsi/a10_twsi.c (revision 297626) +++ head/sys/dev/iicbus/twsi/a10_twsi.c (revision 297627) @@ -1,160 +1,157 @@ /*- * Copyright (c) 2016 Emmanuel Vadot * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include -#include -#include +#include +#include #include "iicbus_if.h" #define TWI_ADDR 0x0 #define TWI_XADDR 0x4 #define TWI_DATA 0x8 #define TWI_CNTR 0xC #define TWI_STAT 0x10 #define TWI_CCR 0x14 #define TWI_SRST 0x18 #define TWI_EFR 0x1C #define TWI_LCR 0x20 -#define A10_I2C 1 -#define A31_I2C 2 - static struct ofw_compat_data compat_data[] = { - {"allwinner,sun4i-a10-i2c", A10_I2C}, - {"allwinner,sun6i-a31-i2c", A31_I2C}, + {"allwinner,sun4i-a10-i2c", 1}, + {"allwinner,sun6i-a31-i2c", 1}, {NULL, 0}, }; static int a10_twsi_probe(device_t dev) { - struct twsi_softc *sc; - sc = device_get_softc(dev); if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Allwinner Integrated I2C Bus Controller"); return (BUS_PROBE_DEFAULT); } static int a10_twsi_attach(device_t dev) { struct twsi_softc *sc; - int clk; + clk_t clk; + hwreset_t rst; + int error; sc = device_get_softc(dev); - /* Activate clock */ - switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { -#if defined(SOC_ALLWINNER_A10) || defined(SOC_ALLWINNER_A20) - case A10_I2C: - clk = a10_clk_i2c_activate(device_get_unit(dev)); - break; -#endif -#if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S) - case A31_I2C: - clk = a31_clk_i2c_activate(device_get_unit(dev)); - break; -#endif - default: - clk = -1; + /* De-assert reset */ + if (hwreset_get_by_ofw_idx(dev, 0, &rst) == 0) { + error = hwreset_deassert(rst); + if (error != 0) { + device_printf(dev, "could not de-assert reset\n"); + return (error); + } } - if (clk != 0) { - device_printf(dev, "could not activate i2c clock\n"); - return (ENXIO); + /* Activate clock */ + error = clk_get_by_ofw_index(dev, 0, &clk); + if (error != 0) { + device_printf(dev, "could not find clock\n"); + return (error); + } + error = clk_enable(clk); + if (error != 0) { + device_printf(dev, "could not enable clock\n"); + return (error); } sc->reg_data = TWI_DATA; sc->reg_slave_addr = TWI_ADDR; sc->reg_slave_ext_addr = TWI_XADDR; sc->reg_control = TWI_CNTR; sc->reg_status = TWI_STAT; sc->reg_baud_rate = TWI_CCR; sc->reg_soft_reset = TWI_SRST; /* Setup baud rate params */ sc->baud_rate[IIC_SLOW].param = TWSI_BAUD_RATE_PARAM(11, 2); sc->baud_rate[IIC_FAST].param = TWSI_BAUD_RATE_PARAM(11, 2); sc->baud_rate[IIC_FASTEST].param = TWSI_BAUD_RATE_PARAM(2, 2); return (twsi_attach(dev)); } static phandle_t a10_twsi_get_node(device_t bus, device_t dev) { return (ofw_bus_get_node(bus)); } static device_method_t a10_twsi_methods[] = { /* device interface */ DEVMETHOD(device_probe, a10_twsi_probe), DEVMETHOD(device_attach, a10_twsi_attach), /* OFW methods */ DEVMETHOD(ofw_bus_get_node, a10_twsi_get_node), { 0, 0 } }; DEFINE_CLASS_1(iichb, a10_twsi_driver, a10_twsi_methods, sizeof(struct twsi_softc), twsi_driver); static devclass_t a10_twsi_devclass; DRIVER_MODULE(a10_twsi, simplebus, a10_twsi_driver, a10_twsi_devclass, 0, 0); DRIVER_MODULE(iicbus, a10_twsi, iicbus_driver, iicbus_devclass, 0, 0); MODULE_DEPEND(a10_twsi, iicbus, 1, 1, 1);