Index: head/sys/arm/allwinner/a10_clk.c =================================================================== --- head/sys/arm/allwinner/a10_clk.c (revision 296407) +++ head/sys/arm/allwinner/a10_clk.c (revision 296408) @@ -1,707 +1,862 @@ /*- * Copyright (c) 2013 Ganbold Tsagaankhuu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* Simple clock driver for Allwinner A10 */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include "a10_clk.h" #define TCON_PLL_WORST 1000000 #define TCON_PLL_N_MIN 1 #define TCON_PLL_N_MAX 15 #define TCON_PLL_M_MIN 9 #define TCON_PLL_M_MAX 127 #define TCON_PLLREF_SINGLE 3000 /* kHz */ #define TCON_PLLREF_DOUBLE 6000 /* kHz */ #define TCON_RATE_KHZ(rate_hz) ((rate_hz) / 1000) #define TCON_RATE_HZ(rate_khz) ((rate_khz) * 1000) #define HDMI_DEFAULT_RATE 297000000 #define DEBE_DEFAULT_RATE 300000000 struct a10_ccm_softc { struct resource *res; bus_space_tag_t bst; bus_space_handle_t bsh; + struct mtx mtx; int pll6_enabled; + int ehci_cnt; + int ohci_cnt; + int usbphy_cnt; + int usb_cnt; }; static struct a10_ccm_softc *a10_ccm_sc = NULL; -#define ccm_read_4(sc, reg) \ +static int a10_clk_usbphy_activate(struct a10_ccm_softc *sc); +static int a10_clk_usbphy_deactivate(struct a10_ccm_softc *sc); +static int a10_clk_usb_activate(struct a10_ccm_softc *sc); +static int a10_clk_usb_deactivate(struct a10_ccm_softc *sc); + +#define CCM_LOCK(sc) mtx_lock(&(sc)->mtx); +#define CCM_UNLOCK(sc) mtx_unlock(&(sc)->mtx); +#define CCM_LOCK_ASSERT(sc) mtx_assert(&(sc)->mtx, MA_OWNED) +#define ccm_read_4(sc, reg) \ bus_space_read_4((sc)->bst, (sc)->bsh, (reg)) -#define ccm_write_4(sc, reg, val) \ +#define ccm_write_4(sc, reg, val) \ bus_space_write_4((sc)->bst, (sc)->bsh, (reg), (val)) static int a10_ccm_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "allwinner,sun4i-ccm")) { device_set_desc(dev, "Allwinner Clock Control Module"); return(BUS_PROBE_DEFAULT); } return (ENXIO); } static int a10_ccm_attach(device_t dev) { struct a10_ccm_softc *sc = device_get_softc(dev); int rid = 0; if (a10_ccm_sc) return (ENXIO); sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->res) { device_printf(dev, "could not allocate resource\n"); return (ENXIO); } sc->bst = rman_get_bustag(sc->res); sc->bsh = rman_get_bushandle(sc->res); + mtx_init(&sc->mtx, "a10_ccm", NULL, MTX_DEF); + a10_ccm_sc = sc; return (0); } static device_method_t a10_ccm_methods[] = { DEVMETHOD(device_probe, a10_ccm_probe), DEVMETHOD(device_attach, a10_ccm_attach), { 0, 0 } }; static driver_t a10_ccm_driver = { "a10_ccm", a10_ccm_methods, sizeof(struct a10_ccm_softc), }; static devclass_t a10_ccm_devclass; EARLY_DRIVER_MODULE(a10_ccm, simplebus, a10_ccm_driver, a10_ccm_devclass, 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); int -a10_clk_usb_activate(void) +a10_clk_ehci_activate(void) { struct a10_ccm_softc *sc = a10_ccm_sc; uint32_t reg_value; if (sc == NULL) return (ENXIO); - /* Gating AHB clock for USB */ - reg_value = ccm_read_4(sc, CCM_AHB_GATING0); - reg_value |= CCM_AHB_GATING_USB0; /* AHB clock gate usb0 */ - reg_value |= CCM_AHB_GATING_EHCI0; /* AHB clock gate ehci0 */ - reg_value |= CCM_AHB_GATING_EHCI1; /* AHB clock gate ehci1 */ - ccm_write_4(sc, CCM_AHB_GATING0, reg_value); + CCM_LOCK(sc); - /* Enable clock for USB */ - reg_value = ccm_read_4(sc, CCM_USB_CLK); - reg_value |= CCM_USB_PHY; /* USBPHY */ - reg_value |= CCM_USB0_RESET; /* disable reset for USB0 */ - reg_value |= CCM_USB1_RESET; /* disable reset for USB1 */ - reg_value |= CCM_USB2_RESET; /* disable reset for USB2 */ - ccm_write_4(sc, CCM_USB_CLK, reg_value); + if (++sc->ehci_cnt == 1) { + /* Gating AHB clock for USB */ + reg_value = ccm_read_4(sc, CCM_AHB_GATING0); + reg_value |= CCM_AHB_GATING_EHCI0; /* AHB clock gate ehci0 */ + reg_value |= CCM_AHB_GATING_EHCI1; /* AHB clock gate ehci1 */ + ccm_write_4(sc, CCM_AHB_GATING0, reg_value); + } + a10_clk_usb_activate(sc); + a10_clk_usbphy_activate(sc); + + CCM_UNLOCK(sc); + return (0); } int -a10_clk_usb_deactivate(void) +a10_clk_ehci_deactivate(void) { struct a10_ccm_softc *sc = a10_ccm_sc; uint32_t reg_value; if (sc == NULL) return (ENXIO); - /* Disable clock for USB */ - reg_value = ccm_read_4(sc, CCM_USB_CLK); - reg_value &= ~CCM_USB_PHY; /* USBPHY */ - reg_value &= ~CCM_USB0_RESET; /* reset for USB0 */ - reg_value &= ~CCM_USB1_RESET; /* reset for USB1 */ - reg_value &= ~CCM_USB2_RESET; /* reset for USB2 */ - ccm_write_4(sc, CCM_USB_CLK, reg_value); + CCM_LOCK(sc); - /* Disable gating AHB clock for USB */ - reg_value = ccm_read_4(sc, CCM_AHB_GATING0); - reg_value &= ~CCM_AHB_GATING_USB0; /* disable AHB clock gate usb0 */ - reg_value &= ~CCM_AHB_GATING_EHCI0; /* disable AHB clock gate ehci0 */ - reg_value &= ~CCM_AHB_GATING_EHCI1; /* disable AHB clock gate ehci1 */ - ccm_write_4(sc, CCM_AHB_GATING0, reg_value); + if (--sc->ehci_cnt == 0) { + /* Disable gating AHB clock for USB */ + reg_value = ccm_read_4(sc, CCM_AHB_GATING0); + reg_value &= ~CCM_AHB_GATING_EHCI0; /* disable AHB clock gate ehci0 */ + reg_value &= ~CCM_AHB_GATING_EHCI1; /* disable AHB clock gate ehci1 */ + ccm_write_4(sc, CCM_AHB_GATING0, reg_value); + } + + a10_clk_usb_deactivate(sc); + a10_clk_usbphy_deactivate(sc); + + CCM_UNLOCK(sc); + + return (0); +} + +int +a10_clk_ohci_activate(void) +{ + struct a10_ccm_softc *sc = a10_ccm_sc; + uint32_t reg_value; + + if (sc == NULL) + return (ENXIO); + + CCM_LOCK(sc); + + if (++sc->ohci_cnt == 1) { + /* Gating AHB clock for USB */ + reg_value = ccm_read_4(sc, CCM_AHB_GATING0); + reg_value |= CCM_AHB_GATING_OHCI0; /* AHB clock gate ohci0 */ + reg_value |= CCM_AHB_GATING_OHCI1; /* AHB clock gate ohci1 */ + ccm_write_4(sc, CCM_AHB_GATING0, reg_value); + + /* Enable clock for USB */ + reg_value = ccm_read_4(sc, CCM_USB_CLK); + reg_value |= CCM_SCLK_GATING_OHCI0; + reg_value |= CCM_SCLK_GATING_OHCI1; + ccm_write_4(sc, CCM_USB_CLK, reg_value); + } + + a10_clk_usb_activate(sc); + a10_clk_usbphy_activate(sc); + + CCM_UNLOCK(sc); + + return (0); +} + +int +a10_clk_ohci_deactivate(void) +{ + struct a10_ccm_softc *sc = a10_ccm_sc; + uint32_t reg_value; + + if (sc == NULL) + return (ENXIO); + + CCM_LOCK(sc); + + if (--sc->ohci_cnt == 0) { + /* Disable clock for USB */ + reg_value = ccm_read_4(sc, CCM_USB_CLK); + reg_value &= ~CCM_SCLK_GATING_OHCI0; + reg_value &= ~CCM_SCLK_GATING_OHCI1; + ccm_write_4(sc, CCM_USB_CLK, reg_value); + + /* Disable gating AHB clock for USB */ + reg_value = ccm_read_4(sc, CCM_AHB_GATING0); + reg_value &= ~CCM_AHB_GATING_OHCI0; /* disable AHB clock gate ohci0 */ + reg_value &= ~CCM_AHB_GATING_OHCI1; /* disable AHB clock gate ohci1 */ + ccm_write_4(sc, CCM_AHB_GATING0, reg_value); + } + + a10_clk_usb_deactivate(sc); + a10_clk_usbphy_deactivate(sc); + + CCM_UNLOCK(sc); + + return (0); +} + +static int +a10_clk_usb_activate(struct a10_ccm_softc *sc) +{ + uint32_t reg_value; + + CCM_LOCK_ASSERT(sc); + + if (++sc->usb_cnt == 1) { + /* Gating AHB clock for USB */ + reg_value = ccm_read_4(sc, CCM_AHB_GATING0); + reg_value |= CCM_AHB_GATING_USB0; /* AHB clock gate usb0 */ + ccm_write_4(sc, CCM_AHB_GATING0, reg_value); + } + + return (0); +} + +static int +a10_clk_usb_deactivate(struct a10_ccm_softc *sc) +{ + uint32_t reg_value; + + CCM_LOCK_ASSERT(sc); + + if (--sc->usb_cnt == 0) { + /* Disable gating AHB clock for USB */ + reg_value = ccm_read_4(sc, CCM_AHB_GATING0); + reg_value &= ~CCM_AHB_GATING_USB0; /* disable AHB clock gate usb0 */ + ccm_write_4(sc, CCM_AHB_GATING0, reg_value); + } + + return (0); +} + +static int +a10_clk_usbphy_activate(struct a10_ccm_softc *sc) +{ + uint32_t reg_value; + + CCM_LOCK_ASSERT(sc); + + if (++sc->usbphy_cnt == 1) { + /* Enable clock for USB */ + reg_value = ccm_read_4(sc, CCM_USB_CLK); + reg_value |= CCM_USB_PHY; /* USBPHY */ + reg_value |= CCM_USBPHY0_RESET; /* disable reset for USBPHY0 */ + reg_value |= CCM_USBPHY1_RESET; /* disable reset for USBPHY1 */ + reg_value |= CCM_USBPHY2_RESET; /* disable reset for USBPHY2 */ + ccm_write_4(sc, CCM_USB_CLK, reg_value); + } + + return (0); +} + +static int +a10_clk_usbphy_deactivate(struct a10_ccm_softc *sc) +{ + uint32_t reg_value; + + CCM_LOCK_ASSERT(sc); + + if (--sc->usbphy_cnt == 0) { + /* Disable clock for USB */ + reg_value = ccm_read_4(sc, CCM_USB_CLK); + reg_value &= ~CCM_USB_PHY; /* USBPHY */ + reg_value &= ~CCM_USBPHY0_RESET; /* reset for USBPHY0 */ + reg_value &= ~CCM_USBPHY1_RESET; /* reset for USBPHY1 */ + reg_value &= ~CCM_USBPHY2_RESET; /* reset for USBPHY2 */ + ccm_write_4(sc, CCM_USB_CLK, reg_value); + } return (0); } int a10_clk_emac_activate(void) { struct a10_ccm_softc *sc = a10_ccm_sc; uint32_t reg_value; if (sc == NULL) return (ENXIO); /* Gating AHB clock for EMAC */ reg_value = ccm_read_4(sc, CCM_AHB_GATING0); reg_value |= CCM_AHB_GATING_EMAC; ccm_write_4(sc, CCM_AHB_GATING0, reg_value); return (0); } int a10_clk_gmac_activate(phandle_t node) { char *phy_type; struct a10_ccm_softc *sc; uint32_t reg_value; sc = a10_ccm_sc; if (sc == NULL) return (ENXIO); /* Gating AHB clock for GMAC */ reg_value = ccm_read_4(sc, CCM_AHB_GATING1); reg_value |= CCM_AHB_GATING_GMAC; ccm_write_4(sc, CCM_AHB_GATING1, reg_value); /* Set GMAC mode. */ reg_value = CCM_GMAC_CLK_MII; if (OF_getprop_alloc(node, "phy-mode", 1, (void **)&phy_type) > 0) { if (strcasecmp(phy_type, "rgmii") == 0) reg_value = CCM_GMAC_CLK_RGMII | CCM_GMAC_MODE_RGMII; else if (strcasecmp(phy_type, "rgmii-bpi") == 0) { reg_value = CCM_GMAC_CLK_RGMII | CCM_GMAC_MODE_RGMII; reg_value |= (3 << CCM_GMAC_CLK_DELAY_SHIFT); } free(phy_type, M_OFWPROP); } ccm_write_4(sc, CCM_GMAC_CLK, reg_value); return (0); } static void a10_clk_pll6_enable(void) { struct a10_ccm_softc *sc; uint32_t reg_value; /* * SATA needs PLL6 to be a 100MHz clock. * The SATA output frequency is 24MHz * n * k / m / 6. * To get to 100MHz, k & m must be equal and n must be 25. * For other uses the output frequency is 24MHz * n * k / 2. */ sc = a10_ccm_sc; if (sc->pll6_enabled) return; reg_value = ccm_read_4(sc, CCM_PLL6_CFG); reg_value &= ~CCM_PLL_CFG_BYPASS; reg_value &= ~(CCM_PLL_CFG_FACTOR_K | CCM_PLL_CFG_FACTOR_M | CCM_PLL_CFG_FACTOR_N); reg_value |= (25 << CCM_PLL_CFG_FACTOR_N_SHIFT); reg_value |= CCM_PLL6_CFG_SATA_CLKEN; reg_value |= CCM_PLL_CFG_ENABLE; ccm_write_4(sc, CCM_PLL6_CFG, reg_value); sc->pll6_enabled = 1; } static unsigned int a10_clk_pll6_get_rate(void) { struct a10_ccm_softc *sc; uint32_t k, n, reg_value; sc = a10_ccm_sc; reg_value = ccm_read_4(sc, CCM_PLL6_CFG); n = ((reg_value & CCM_PLL_CFG_FACTOR_N) >> CCM_PLL_CFG_FACTOR_N_SHIFT); k = ((reg_value & CCM_PLL_CFG_FACTOR_K) >> CCM_PLL_CFG_FACTOR_K_SHIFT) + 1; return ((CCM_CLK_REF_FREQ * n * k) / 2); } static int a10_clk_pll2_set_rate(unsigned int freq) { struct a10_ccm_softc *sc; uint32_t reg_value; unsigned int prediv, postdiv, n; sc = a10_ccm_sc; if (sc == NULL) return (ENXIO); reg_value = ccm_read_4(sc, CCM_PLL2_CFG); reg_value &= ~(CCM_PLL2_CFG_PREDIV | CCM_PLL2_CFG_POSTDIV | CCM_PLL_CFG_FACTOR_N); /* * Audio Codec needs PLL2 to be either 24576000 Hz or 22579200 Hz * * PLL2 output frequency is 24MHz * n / prediv / postdiv. * To get as close as possible to the desired rate, we use a * pre-divider of 21 and a post-divider of 4. With these values, * a multiplier of 86 or 79 gets us close to the target rates. */ prediv = 21; postdiv = 4; switch (freq) { case 24576000: n = 86; reg_value |= CCM_PLL_CFG_ENABLE; break; case 22579200: n = 79; reg_value |= CCM_PLL_CFG_ENABLE; break; case 0: n = 1; reg_value &= ~CCM_PLL_CFG_ENABLE; break; default: return (EINVAL); } reg_value |= (prediv << CCM_PLL2_CFG_PREDIV_SHIFT); reg_value |= (postdiv << CCM_PLL2_CFG_POSTDIV_SHIFT); reg_value |= (n << CCM_PLL_CFG_FACTOR_N_SHIFT); ccm_write_4(sc, CCM_PLL2_CFG, reg_value); return (0); } static int a10_clk_pll3_set_rate(unsigned int freq) { struct a10_ccm_softc *sc; uint32_t reg_value; int m; sc = a10_ccm_sc; if (sc == NULL) return (ENXIO); if (freq == 0) { /* Disable PLL3 */ ccm_write_4(sc, CCM_PLL3_CFG, 0); return (0); } m = freq / TCON_RATE_HZ(TCON_PLLREF_SINGLE); reg_value = CCM_PLL_CFG_ENABLE | CCM_PLL3_CFG_MODE_SEL_INT | m; ccm_write_4(sc, CCM_PLL3_CFG, reg_value); return (0); } static unsigned int a10_clk_pll5x_get_rate(void) { struct a10_ccm_softc *sc; uint32_t k, n, p, reg_value; sc = a10_ccm_sc; reg_value = ccm_read_4(sc, CCM_PLL5_CFG); n = ((reg_value & CCM_PLL_CFG_FACTOR_N) >> CCM_PLL_CFG_FACTOR_N_SHIFT); k = ((reg_value & CCM_PLL_CFG_FACTOR_K) >> CCM_PLL_CFG_FACTOR_K_SHIFT) + 1; p = ((reg_value & CCM_PLL5_CFG_OUT_EXT_DIV_P) >> CCM_PLL5_CFG_OUT_EXT_DIV_P_SHIFT); return ((CCM_CLK_REF_FREQ * n * k) >> p); } int a10_clk_ahci_activate(void) { struct a10_ccm_softc *sc; uint32_t reg_value; sc = a10_ccm_sc; if (sc == NULL) return (ENXIO); a10_clk_pll6_enable(); /* Gating AHB clock for SATA */ reg_value = ccm_read_4(sc, CCM_AHB_GATING0); reg_value |= CCM_AHB_GATING_SATA; ccm_write_4(sc, CCM_AHB_GATING0, reg_value); DELAY(1000); ccm_write_4(sc, CCM_SATA_CLK, CCM_PLL_CFG_ENABLE); return (0); } int a10_clk_mmc_activate(int devid) { struct a10_ccm_softc *sc; uint32_t reg_value; sc = a10_ccm_sc; if (sc == NULL) return (ENXIO); a10_clk_pll6_enable(); /* Gating AHB clock for SD/MMC */ reg_value = ccm_read_4(sc, CCM_AHB_GATING0); reg_value |= CCM_AHB_GATING_SDMMC0 << devid; ccm_write_4(sc, CCM_AHB_GATING0, reg_value); return (0); } int a10_clk_mmc_cfg(int devid, int freq) { struct a10_ccm_softc *sc; uint32_t clksrc, m, n, ophase, phase, reg_value; unsigned int pll_freq; sc = a10_ccm_sc; if (sc == NULL) return (ENXIO); freq /= 1000; if (freq <= 400) { pll_freq = CCM_CLK_REF_FREQ / 1000; clksrc = CCM_SD_CLK_SRC_SEL_OSC24M; ophase = 0; phase = 0; n = 2; } else if (freq <= 25000) { pll_freq = a10_clk_pll6_get_rate() / 1000; clksrc = CCM_SD_CLK_SRC_SEL_PLL6; ophase = 0; phase = 5; n = 2; } else if (freq <= 50000) { pll_freq = a10_clk_pll6_get_rate() / 1000; clksrc = CCM_SD_CLK_SRC_SEL_PLL6; ophase = 3; phase = 5; n = 0; } else return (EINVAL); m = ((pll_freq / (1 << n)) / (freq)) - 1; reg_value = ccm_read_4(sc, CCM_MMC0_SCLK_CFG + (devid * 4)); reg_value &= ~CCM_SD_CLK_SRC_SEL; reg_value |= (clksrc << CCM_SD_CLK_SRC_SEL_SHIFT); reg_value &= ~CCM_SD_CLK_PHASE_CTR; reg_value |= (phase << CCM_SD_CLK_PHASE_CTR_SHIFT); reg_value &= ~CCM_SD_CLK_DIV_RATIO_N; reg_value |= (n << CCM_SD_CLK_DIV_RATIO_N_SHIFT); reg_value &= ~CCM_SD_CLK_OPHASE_CTR; reg_value |= (ophase << CCM_SD_CLK_OPHASE_CTR_SHIFT); reg_value &= ~CCM_SD_CLK_DIV_RATIO_M; reg_value |= m; reg_value |= CCM_PLL_CFG_ENABLE; ccm_write_4(sc, CCM_MMC0_SCLK_CFG + (devid * 4), reg_value); return (0); } int a10_clk_i2c_activate(int devid) { struct a10_ccm_softc *sc; uint32_t reg_value; sc = a10_ccm_sc; if (sc == NULL) return (ENXIO); a10_clk_pll6_enable(); /* Gating APB clock for I2C/TWI */ reg_value = ccm_read_4(sc, CCM_APB1_GATING); if (devid == 4) reg_value |= CCM_APB1_GATING_TWI << 15; else reg_value |= CCM_APB1_GATING_TWI << devid; ccm_write_4(sc, CCM_APB1_GATING, reg_value); return (0); } int a10_clk_dmac_activate(void) { struct a10_ccm_softc *sc; uint32_t reg_value; sc = a10_ccm_sc; if (sc == NULL) return (ENXIO); /* Gating AHB clock for DMA controller */ reg_value = ccm_read_4(sc, CCM_AHB_GATING0); reg_value |= CCM_AHB_GATING_DMA; ccm_write_4(sc, CCM_AHB_GATING0, reg_value); return (0); } int a10_clk_codec_activate(unsigned int freq) { struct a10_ccm_softc *sc; uint32_t reg_value; sc = a10_ccm_sc; if (sc == NULL) return (ENXIO); a10_clk_pll2_set_rate(freq); /* Gating APB clock for ADDA */ reg_value = ccm_read_4(sc, CCM_APB0_GATING); reg_value |= CCM_APB0_GATING_ADDA; ccm_write_4(sc, CCM_APB0_GATING, reg_value); /* Enable audio codec clock */ reg_value = ccm_read_4(sc, CCM_AUDIO_CODEC_CLK); reg_value |= CCM_AUDIO_CODEC_ENABLE; ccm_write_4(sc, CCM_AUDIO_CODEC_CLK, reg_value); return (0); } static void calc_tcon_pll(int f_ref, int f_out, int *pm, int *pn) { int best, m, n, f_cur, diff; best = TCON_PLL_WORST; for (n = TCON_PLL_N_MIN; n <= TCON_PLL_N_MAX; n++) { for (m = TCON_PLL_M_MIN; m <= TCON_PLL_M_MAX; m++) { f_cur = (m * f_ref) / n; diff = f_out - f_cur; if (diff > 0 && diff < best) { best = diff; *pm = m; *pn = n; } } } } int a10_clk_debe_activate(void) { struct a10_ccm_softc *sc; int pll_rate, clk_div; uint32_t reg_value; sc = a10_ccm_sc; if (sc == NULL) return (ENXIO); /* Leave reset */ reg_value = ccm_read_4(sc, CCM_BE0_SCLK); reg_value |= CCM_BE_CLK_RESET; ccm_write_4(sc, CCM_BE0_SCLK, reg_value); pll_rate = a10_clk_pll5x_get_rate(); clk_div = howmany(pll_rate, DEBE_DEFAULT_RATE); /* Set BE0 source to PLL5 (DDR external peripheral clock) */ reg_value = CCM_BE_CLK_RESET; reg_value |= (CCM_BE_CLK_SRC_SEL_PLL5 << CCM_BE_CLK_SRC_SEL_SHIFT); reg_value |= (clk_div - 1); ccm_write_4(sc, CCM_BE0_SCLK, reg_value); /* Gating AHB clock for BE0 */ reg_value = ccm_read_4(sc, CCM_AHB_GATING1); reg_value |= CCM_AHB_GATING_DE_BE0; ccm_write_4(sc, CCM_AHB_GATING1, reg_value); /* Enable DRAM clock to BE0 */ reg_value = ccm_read_4(sc, CCM_DRAM_CLK); reg_value |= CCM_DRAM_CLK_BE0_CLK_ENABLE; ccm_write_4(sc, CCM_DRAM_CLK, reg_value); /* Enable BE0 clock */ reg_value = ccm_read_4(sc, CCM_BE0_SCLK); reg_value |= CCM_BE_CLK_SCLK_GATING; ccm_write_4(sc, CCM_BE0_SCLK, reg_value); return (0); } int a10_clk_lcd_activate(void) { struct a10_ccm_softc *sc; uint32_t reg_value; sc = a10_ccm_sc; if (sc == NULL) return (ENXIO); /* Clear LCD0 reset */ reg_value = ccm_read_4(sc, CCM_LCD0_CH0_CLK); reg_value |= CCM_LCD_CH0_RESET; ccm_write_4(sc, CCM_LCD0_CH0_CLK, reg_value); /* Gating AHB clock for LCD0 */ reg_value = ccm_read_4(sc, CCM_AHB_GATING1); reg_value |= CCM_AHB_GATING_LCD0; ccm_write_4(sc, CCM_AHB_GATING1, reg_value); return (0); } int a10_clk_tcon_activate(unsigned int freq) { struct a10_ccm_softc *sc; int m, n, m2, n2, f_single, f_double, dbl, src_sel; sc = a10_ccm_sc; if (sc == NULL) return (ENXIO); m = n = m2 = n2 = 0; dbl = 0; calc_tcon_pll(TCON_PLLREF_SINGLE, TCON_RATE_KHZ(freq), &m, &n); calc_tcon_pll(TCON_PLLREF_DOUBLE, TCON_RATE_KHZ(freq), &m2, &n2); f_single = n ? (m * TCON_PLLREF_SINGLE) / n : 0; f_double = n2 ? (m2 * TCON_PLLREF_DOUBLE) / n2 : 0; if (f_double > f_single) { dbl = 1; m = m2; n = n2; } src_sel = dbl ? CCM_LCD_CH1_SRC_SEL_PLL3_2X : CCM_LCD_CH1_SRC_SEL_PLL3; if (n == 0 || m == 0) return (EINVAL); /* Set PLL3 to the closest possible rate */ a10_clk_pll3_set_rate(TCON_RATE_HZ(m * TCON_PLLREF_SINGLE)); /* Enable LCD0 CH1 clock */ ccm_write_4(sc, CCM_LCD0_CH1_CLK, CCM_LCD_CH1_SCLK2_GATING | CCM_LCD_CH1_SCLK1_GATING | (src_sel << CCM_LCD_CH1_SRC_SEL_SHIFT) | (n - 1)); return (0); } int a10_clk_tcon_get_config(int *pdiv, int *pdbl) { struct a10_ccm_softc *sc; uint32_t reg_value; int src; sc = a10_ccm_sc; if (sc == NULL) return (ENXIO); reg_value = ccm_read_4(sc, CCM_LCD0_CH1_CLK); *pdiv = (reg_value & CCM_LCD_CH1_CLK_DIV_RATIO_M) + 1; src = (reg_value & CCM_LCD_CH1_SRC_SEL) >> CCM_LCD_CH1_SRC_SEL_SHIFT; switch (src) { case CCM_LCD_CH1_SRC_SEL_PLL3: case CCM_LCD_CH1_SRC_SEL_PLL7: *pdbl = 0; break; case CCM_LCD_CH1_SRC_SEL_PLL3_2X: case CCM_LCD_CH1_SRC_SEL_PLL7_2X: *pdbl = 1; break; } return (0); } int a10_clk_hdmi_activate(void) { struct a10_ccm_softc *sc; uint32_t reg_value; int error; sc = a10_ccm_sc; if (sc == NULL) return (ENXIO); /* Set PLL3 to 297MHz */ error = a10_clk_pll3_set_rate(HDMI_DEFAULT_RATE); if (error != 0) return (error); /* Enable HDMI clock, source PLL3 */ reg_value = ccm_read_4(sc, CCM_HDMI_CLK); reg_value |= CCM_HDMI_CLK_SCLK_GATING; reg_value &= ~CCM_HDMI_CLK_SRC_SEL; reg_value |= (CCM_HDMI_CLK_SRC_SEL_PLL3 << CCM_HDMI_CLK_SRC_SEL_SHIFT); ccm_write_4(sc, CCM_HDMI_CLK, reg_value); /* Gating AHB clock for HDMI */ reg_value = ccm_read_4(sc, CCM_AHB_GATING1); reg_value |= CCM_AHB_GATING_HDMI; ccm_write_4(sc, CCM_AHB_GATING1, reg_value); return (0); } Index: head/sys/arm/allwinner/a10_clk.h =================================================================== --- head/sys/arm/allwinner/a10_clk.h (revision 296407) +++ head/sys/arm/allwinner/a10_clk.h (revision 296408) @@ -1,240 +1,247 @@ /*- * Copyright (c) 2013 Ganbold Tsagaankhuu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _A10_CLK_H_ #define _A10_CLK_H_ #define CCM_PLL1_CFG 0x0000 #define CCM_PLL1_TUN 0x0004 #define CCM_PLL2_CFG 0x0008 #define CCM_PLL2_TUN 0x000c #define CCM_PLL3_CFG 0x0010 #define CCM_PLL3_TUN 0x0014 #define CCM_PLL4_CFG 0x0018 #define CCM_PLL4_TUN 0x001c #define CCM_PLL5_CFG 0x0020 #define CCM_PLL5_TUN 0x0024 #define CCM_PLL6_CFG 0x0028 #define CCM_PLL6_TUN 0x002c #define CCM_PLL7_CFG 0x0030 #define CCM_PLL7_TUN 0x0034 #define CCM_PLL1_TUN2 0x0038 #define CCM_PLL5_TUN2 0x003c #define CCM_PLL_LOCK_DBG 0x004c #define CCM_OSC24M_CFG 0x0050 #define CCM_CPU_AHB_APB0_CFG 0x0054 #define CCM_APB1_CLK_DIV 0x0058 #define CCM_AXI_GATING 0x005c #define CCM_AHB_GATING0 0x0060 #define CCM_AHB_GATING1 0x0064 #define CCM_APB0_GATING 0x0068 #define CCM_APB1_GATING 0x006c #define CCM_NAND_SCLK_CFG 0x0080 #define CCM_MS_SCLK_CFG 0x0084 #define CCM_MMC0_SCLK_CFG 0x0088 #define CCM_MMC1_SCLK_CFG 0x008c #define CCM_MMC2_SCLK_CFG 0x0090 #define CCM_MMC3_SCLK_CFG 0x0094 #define CCM_TS_CLK 0x0098 #define CCM_SS_CLK 0x009c #define CCM_SPI0_CLK 0x00a0 #define CCM_SPI1_CLK 0x00a4 #define CCM_SPI2_CLK 0x00a8 #define CCM_PATA_CLK 0x00ac #define CCM_IR0_CLK 0x00b0 #define CCM_IR1_CLK 0x00b4 #define CCM_IIS_CLK 0x00b8 #define CCM_AC97_CLK 0x00bc #define CCM_SPDIF_CLK 0x00c0 #define CCM_KEYPAD_CLK 0x00c4 #define CCM_SATA_CLK 0x00c8 #define CCM_USB_CLK 0x00cc #define CCM_GPS_CLK 0x00d0 #define CCM_SPI3_CLK 0x00d4 #define CCM_DRAM_CLK 0x0100 #define CCM_BE0_SCLK 0x0104 #define CCM_BE1_SCLK 0x0108 #define CCM_FE0_CLK 0x010c #define CCM_FE1_CLK 0x0110 #define CCM_MP_CLK 0x0114 #define CCM_LCD0_CH0_CLK 0x0118 #define CCM_LCD1_CH0_CLK 0x011c #define CCM_CSI_ISP_CLK 0x0120 #define CCM_TVD_CLK 0x0128 #define CCM_LCD0_CH1_CLK 0x012c #define CCM_LCD1_CH1_CLK 0x0130 #define CCM_CS0_CLK 0x0134 #define CCM_CS1_CLK 0x0138 #define CCM_VE_CLK 0x013c #define CCM_AUDIO_CODEC_CLK 0x0140 #define CCM_AVS_CLK 0x0144 #define CCM_ACE_CLK 0x0148 #define CCM_LVDS_CLK 0x014c #define CCM_HDMI_CLK 0x0150 #define CCM_MALI400_CLK 0x0154 #define CCM_GMAC_CLK 0x0164 #define CCM_GMAC_CLK_DELAY_SHIFT 10 #define CCM_GMAC_CLK_MODE_MASK 0x7 #define CCM_GMAC_MODE_RGMII (1 << 2) #define CCM_GMAC_CLK_MII 0x0 #define CCM_GMAC_CLK_EXT_RGMII 0x1 #define CCM_GMAC_CLK_RGMII 0x2 /* APB0_GATING */ #define CCM_APB0_GATING_ADDA (1 << 0) /* AHB_GATING_REG0 */ #define CCM_AHB_GATING_USB0 (1 << 0) #define CCM_AHB_GATING_EHCI0 (1 << 1) +#define CCM_AHB_GATING_OHCI0 (1 << 2) #define CCM_AHB_GATING_EHCI1 (1 << 3) +#define CCM_AHB_GATING_OHCI1 (1 << 4) #define CCM_AHB_GATING_DMA (1 << 6) #define CCM_AHB_GATING_SDMMC0 (1 << 8) #define CCM_AHB_GATING_EMAC (1 << 17) #define CCM_AHB_GATING_SATA (1 << 25) /* AHB_GATING_REG1 */ #define CCM_AHB_GATING_GMAC (1 << 17) #define CCM_AHB_GATING_DE_BE1 (1 << 13) #define CCM_AHB_GATING_DE_BE0 (1 << 12) #define CCM_AHB_GATING_HDMI (1 << 11) #define CCM_AHB_GATING_LCD1 (1 << 5) #define CCM_AHB_GATING_LCD0 (1 << 4) /* APB1_GATING_REG */ #define CCM_APB1_GATING_TWI (1 << 0) +/* USB */ #define CCM_USB_PHY (1 << 8) -#define CCM_USB0_RESET (1 << 0) -#define CCM_USB1_RESET (1 << 1) -#define CCM_USB2_RESET (1 << 2) +#define CCM_SCLK_GATING_OHCI1 (1 << 7) +#define CCM_SCLK_GATING_OHCI0 (1 << 6) +#define CCM_USBPHY2_RESET (1 << 2) +#define CCM_USBPHY1_RESET (1 << 1) +#define CCM_USBPHY0_RESET (1 << 0) #define CCM_PLL_CFG_ENABLE (1U << 31) #define CCM_PLL_CFG_BYPASS (1U << 30) #define CCM_PLL_CFG_PLL5 (1U << 25) #define CCM_PLL_CFG_PLL6 (1U << 24) #define CCM_PLL_CFG_FACTOR_N 0x1f00 #define CCM_PLL_CFG_FACTOR_N_SHIFT 8 #define CCM_PLL_CFG_FACTOR_K 0x30 #define CCM_PLL_CFG_FACTOR_K_SHIFT 4 #define CCM_PLL_CFG_FACTOR_M 0x3 #define CCM_PLL2_CFG_POSTDIV 0x3c000000 #define CCM_PLL2_CFG_POSTDIV_SHIFT 26 #define CCM_PLL2_CFG_PREDIV 0x1f #define CCM_PLL2_CFG_PREDIV_SHIFT 0 #define CCM_PLL3_CFG_MODE_SEL_SHIFT 15 #define CCM_PLL3_CFG_MODE_SEL_FRACT (0 << CCM_PLL3_CFG_MODE_SEL_SHIFT) #define CCM_PLL3_CFG_MODE_SEL_INT (1 << CCM_PLL3_CFG_MODE_SEL_SHIFT) #define CCM_PLL3_CFG_FUNC_SET_SHIFT 14 #define CCM_PLL3_CFG_FUNC_SET_270MHZ (0 << CCM_PLL3_CFG_FUNC_SET_SHIFT) #define CCM_PLL3_CFG_FUNC_SET_297MHZ (1 << CCM_PLL3_CFG_FUNC_SET_SHIFT) #define CCM_PLL3_CFG_FACTOR_M 0x7f #define CCM_PLL5_CFG_OUT_EXT_DIV_P 0x30000 #define CCM_PLL5_CFG_OUT_EXT_DIV_P_SHIFT 16 #define CCM_PLL6_CFG_SATA_CLKEN (1U << 14) #define CCM_SD_CLK_SRC_SEL 0x3000000 #define CCM_SD_CLK_SRC_SEL_SHIFT 24 #define CCM_SD_CLK_SRC_SEL_OSC24M 0 #define CCM_SD_CLK_SRC_SEL_PLL6 1 #define CCM_SD_CLK_PHASE_CTR 0x700000 #define CCM_SD_CLK_PHASE_CTR_SHIFT 20 #define CCM_SD_CLK_DIV_RATIO_N 0x30000 #define CCM_SD_CLK_DIV_RATIO_N_SHIFT 16 #define CCM_SD_CLK_OPHASE_CTR 0x700 #define CCM_SD_CLK_OPHASE_CTR_SHIFT 8 #define CCM_SD_CLK_DIV_RATIO_M 0xf #define CCM_AUDIO_CODEC_ENABLE (1U << 31) #define CCM_LCD_CH0_SCLK_GATING (1U << 31) #define CCM_LCD_CH0_RESET (1U << 30) #define CCM_LCD_CH0_SRC_SEL 0x03000000 #define CCM_LCD_CH0_SRC_SEL_SHIFT 24 #define CCM_LCD_CH0_SRC_SEL_PLL3 0 #define CCM_LCD_CH0_SRC_SEL_PLL7 1 #define CCM_LCD_CH0_SRC_SEL_PLL3_2X 2 #define CCM_LCD_CH0_SRC_SEL_PLL6_2X 3 #define CCM_LCD_CH1_SCLK2_GATING (1U << 31) #define CCM_LCD_CH1_SRC_SEL 0x03000000 #define CCM_LCD_CH1_SRC_SEL_SHIFT 24 #define CCM_LCD_CH1_SRC_SEL_PLL3 0 #define CCM_LCD_CH1_SRC_SEL_PLL7 1 #define CCM_LCD_CH1_SRC_SEL_PLL3_2X 2 #define CCM_LCD_CH1_SRC_SEL_PLL7_2X 3 #define CCM_LCD_CH1_SCLK1_GATING (1U << 15) #define CCM_LCD_CH1_SCLK1_SRC_SEL_SHIFT 11 #define CCM_LCD_CH1_SCLK1_SRC_SEL_SCLK2 0 #define CCM_LCD_CH1_SCLK1_SRC_SEL_SCLK2_DIV2 1 #define CCM_LCD_CH1_CLK_DIV_RATIO_M 0xf #define CCM_DRAM_CLK_BE1_CLK_ENABLE (1U << 27) #define CCM_DRAM_CLK_BE0_CLK_ENABLE (1U << 26) #define CCM_BE_CLK_SCLK_GATING (1U << 31) #define CCM_BE_CLK_RESET (1U << 30) #define CCM_BE_CLK_SRC_SEL 0x03000000 #define CCM_BE_CLK_SRC_SEL_SHIFT 24 #define CCM_BE_CLK_SRC_SEL_PLL3 0 #define CCM_BE_CLK_SRC_SEL_PLL7 1 #define CCM_BE_CLK_SRC_SEL_PLL5 2 #define CCM_BE_CLK_DIV_RATIO_M 0xf #define CCM_HDMI_CLK_SCLK_GATING (1U << 31) #define CCM_HDMI_CLK_SRC_SEL 0x03000000 #define CCM_HDMI_CLK_SRC_SEL_SHIFT 24 #define CCM_HDMI_CLK_SRC_SEL_PLL3 0 #define CCM_HDMI_CLK_SRC_SEL_PLL7 1 #define CCM_HDMI_CLK_SRC_SEL_PLL3_2X 2 #define CCM_HDMI_CLK_SRC_SEL_PLL7_2X 3 #define CCM_HDMI_CLK_DIV_RATIO_M 0xf #define CCM_CLK_REF_FREQ 24000000U -int a10_clk_usb_activate(void); -int a10_clk_usb_deactivate(void); +int a10_clk_ehci_activate(void); +int a10_clk_ehci_deactivate(void); +int a10_clk_ohci_activate(void); +int a10_clk_ohci_deactivate(void); int a10_clk_emac_activate(void); int a10_clk_gmac_activate(phandle_t); int a10_clk_ahci_activate(void); int a10_clk_mmc_activate(int); int a10_clk_mmc_cfg(int, int); int a10_clk_i2c_activate(int); int a10_clk_dmac_activate(void); int a10_clk_codec_activate(unsigned int); int a10_clk_debe_activate(void); int a10_clk_lcd_activate(void); int a10_clk_tcon_activate(unsigned int); int a10_clk_tcon_get_config(int *, int *); int a10_clk_hdmi_activate(void); #endif /* _A10_CLK_H_ */ Index: head/sys/arm/allwinner/a10_ehci.c =================================================================== --- head/sys/arm/allwinner/a10_ehci.c (revision 296407) +++ head/sys/arm/allwinner/a10_ehci.c (revision 296408) @@ -1,334 +1,334 @@ /*- * Copyright (c) 2012 Ganbold Tsagaankhuu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Allwinner A10 attachment driver for the USB Enhanced Host Controller. */ #include __FBSDID("$FreeBSD$"); #include "opt_bus.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define EHCI_HC_DEVSTR "Allwinner Integrated USB 2.0 controller" #define SW_USB_PMU_IRQ_ENABLE 0x800 #define SW_SDRAM_REG_HPCR_USB1 (0x250 + ((1 << 2) * 4)) #define SW_SDRAM_REG_HPCR_USB2 (0x250 + ((1 << 2) * 5)) #define SW_SDRAM_BP_HPCR_ACCESS (1 << 0) #define SW_ULPI_BYPASS (1 << 0) #define SW_AHB_INCRX_ALIGN (1 << 8) #define SW_AHB_INCR4 (1 << 9) #define SW_AHB_INCR8 (1 << 10) #define USB_CONF(d) \ (void *)ofw_bus_search_compatible((d), compat_data)->ocd_data #define A10_READ_4(sc, reg) \ bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) #define A10_WRITE_4(sc, reg, data) \ bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) static device_attach_t a10_ehci_attach; static device_detach_t a10_ehci_detach; bs_r_1_proto(reversed); bs_w_1_proto(reversed); struct aw_ehci_conf { int (*clk_activate)(void); int (*clk_deactivate)(void); bool sdram_init; }; static const struct aw_ehci_conf a10_ehci_conf = { #if defined(SOC_ALLWINNER_A10) || defined(SOC_ALLWINNER_A20) - .clk_activate = a10_clk_usb_activate, - .clk_deactivate = a10_clk_usb_deactivate, + .clk_activate = a10_clk_ehci_activate, + .clk_deactivate = a10_clk_ehci_deactivate, #endif .sdram_init = true, }; static const struct aw_ehci_conf a31_ehci_conf = { #if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S) .clk_activate = a31_clk_ehci_activate, .clk_deactivate = a31_clk_ehci_deactivate, #endif }; static struct ofw_compat_data compat_data[] = { { "allwinner,sun4i-a10-ehci", (uintptr_t)&a10_ehci_conf }, { "allwinner,sun6i-a31-ehci", (uintptr_t)&a31_ehci_conf }, { "allwinner,sun7i-a20-ehci", (uintptr_t)&a10_ehci_conf }, { NULL, (uintptr_t)NULL } }; static int a10_ehci_probe(device_t self) { if (!ofw_bus_status_okay(self)) return (ENXIO); if (ofw_bus_search_compatible(self, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(self, EHCI_HC_DEVSTR); return (BUS_PROBE_DEFAULT); } static int a10_ehci_attach(device_t self) { ehci_softc_t *sc = device_get_softc(self); const struct aw_ehci_conf *conf; bus_space_handle_t bsh; int err; int rid; uint32_t reg_value = 0; conf = USB_CONF(self); if (conf->clk_activate == NULL) { device_printf(self, "clock not supported\n"); return (ENXIO); } /* initialise some bus fields */ sc->sc_bus.parent = self; sc->sc_bus.devices = sc->sc_devices; sc->sc_bus.devices_max = EHCI_MAX_DEVICES; sc->sc_bus.dma_bits = 32; /* get all DMA memory */ if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) { return (ENOMEM); } sc->sc_bus.usbrev = USB_REV_2_0; rid = 0; sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_io_res) { device_printf(self, "Could not map memory\n"); goto error; } sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); bsh = rman_get_bushandle(sc->sc_io_res); sc->sc_io_size = rman_get_size(sc->sc_io_res); if (bus_space_subregion(sc->sc_io_tag, bsh, 0x00, sc->sc_io_size, &sc->sc_io_hdl) != 0) panic("%s: unable to subregion USB host registers", device_get_name(self)); rid = 0; sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); if (sc->sc_irq_res == NULL) { device_printf(self, "Could not allocate irq\n"); goto error; } sc->sc_bus.bdev = device_add_child(self, "usbus", -1); if (!sc->sc_bus.bdev) { device_printf(self, "Could not add USB device\n"); goto error; } device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); device_set_desc(sc->sc_bus.bdev, EHCI_HC_DEVSTR); sprintf(sc->sc_vendor, "Allwinner"); err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl); if (err) { device_printf(self, "Could not setup irq, %d\n", err); sc->sc_intr_hdl = NULL; goto error; } sc->sc_flags |= EHCI_SCFLG_DONTRESET; /* Enable clock for USB */ if (conf->clk_activate() != 0) { device_printf(self, "Could not activate clock\n"); goto error; } /* Enable passby */ reg_value = A10_READ_4(sc, SW_USB_PMU_IRQ_ENABLE); reg_value |= SW_AHB_INCR8; /* AHB INCR8 enable */ reg_value |= SW_AHB_INCR4; /* AHB burst type INCR4 enable */ reg_value |= SW_AHB_INCRX_ALIGN; /* AHB INCRX align enable */ reg_value |= SW_ULPI_BYPASS; /* ULPI bypass enable */ A10_WRITE_4(sc, SW_USB_PMU_IRQ_ENABLE, reg_value); /* Configure port */ if (conf->sdram_init) { reg_value = A10_READ_4(sc, SW_SDRAM_REG_HPCR_USB2); reg_value |= SW_SDRAM_BP_HPCR_ACCESS; A10_WRITE_4(sc, SW_SDRAM_REG_HPCR_USB2, reg_value); } err = ehci_init(sc); if (!err) { err = device_probe_and_attach(sc->sc_bus.bdev); } if (err) { device_printf(self, "USB init failed err=%d\n", err); goto error; } return (0); error: a10_ehci_detach(self); return (ENXIO); } static int a10_ehci_detach(device_t self) { ehci_softc_t *sc = device_get_softc(self); const struct aw_ehci_conf *conf; device_t bdev; int err; uint32_t reg_value = 0; conf = USB_CONF(self); if (sc->sc_bus.bdev) { bdev = sc->sc_bus.bdev; device_detach(bdev); device_delete_child(self, bdev); } /* during module unload there are lots of children leftover */ device_delete_children(self); if (sc->sc_irq_res && sc->sc_intr_hdl) { /* * only call ehci_detach() after ehci_init() */ ehci_detach(sc); err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); if (err) /* XXX or should we panic? */ device_printf(self, "Could not tear down irq, %d\n", err); sc->sc_intr_hdl = NULL; } if (sc->sc_irq_res) { bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res); sc->sc_irq_res = NULL; } if (sc->sc_io_res) { bus_release_resource(self, SYS_RES_MEMORY, 0, sc->sc_io_res); sc->sc_io_res = NULL; } usb_bus_mem_free_all(&sc->sc_bus, &ehci_iterate_hw_softc); /* Disable configure port */ if (conf->sdram_init) { reg_value = A10_READ_4(sc, SW_SDRAM_REG_HPCR_USB2); reg_value &= ~SW_SDRAM_BP_HPCR_ACCESS; A10_WRITE_4(sc, SW_SDRAM_REG_HPCR_USB2, reg_value); } /* Disable passby */ reg_value = A10_READ_4(sc, SW_USB_PMU_IRQ_ENABLE); reg_value &= ~SW_AHB_INCR8; /* AHB INCR8 disable */ reg_value &= ~SW_AHB_INCR4; /* AHB burst type INCR4 disable */ reg_value &= ~SW_AHB_INCRX_ALIGN; /* AHB INCRX align disable */ reg_value &= ~SW_ULPI_BYPASS; /* ULPI bypass disable */ A10_WRITE_4(sc, SW_USB_PMU_IRQ_ENABLE, reg_value); /* Disable clock for USB */ conf->clk_deactivate(); return (0); } static device_method_t ehci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, a10_ehci_probe), DEVMETHOD(device_attach, a10_ehci_attach), DEVMETHOD(device_detach, a10_ehci_detach), DEVMETHOD(device_suspend, bus_generic_suspend), DEVMETHOD(device_resume, bus_generic_resume), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD_END }; static driver_t ehci_driver = { .name = "ehci", .methods = ehci_methods, .size = sizeof(ehci_softc_t), }; static devclass_t ehci_devclass; DRIVER_MODULE(ehci, simplebus, ehci_driver, ehci_devclass, 0, 0); MODULE_DEPEND(ehci, usb, 1, 1, 1);