Index: head/sys/arm/allwinner/a10_ehci.c =================================================================== --- head/sys/arm/allwinner/a10_ehci.c (revision 296283) +++ head/sys/arm/allwinner/a10_ehci.c (revision 296284) @@ -1,311 +1,334 @@ /*- * Copyright (c) 2012 Ganbold Tsagaankhuu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Allwinner A10 attachment driver for the USB Enhanced Host Controller. */ #include __FBSDID("$FreeBSD$"); #include "opt_bus.h" #include #include #include #include #include #include #include -#include #include #include #include #include #include #include #include #include #include #include #include #include #include -#include "gpio_if.h" +#include +#include +#include -#include "a10_clk.h" - #define EHCI_HC_DEVSTR "Allwinner Integrated USB 2.0 controller" #define SW_USB_PMU_IRQ_ENABLE 0x800 #define SW_SDRAM_REG_HPCR_USB1 (0x250 + ((1 << 2) * 4)) #define SW_SDRAM_REG_HPCR_USB2 (0x250 + ((1 << 2) * 5)) #define SW_SDRAM_BP_HPCR_ACCESS (1 << 0) #define SW_ULPI_BYPASS (1 << 0) #define SW_AHB_INCRX_ALIGN (1 << 8) #define SW_AHB_INCR4 (1 << 9) #define SW_AHB_INCR8 (1 << 10) -#define GPIO_USB1_PWR 230 -#define GPIO_USB2_PWR 227 +#define USB_CONF(d) \ + (void *)ofw_bus_search_compatible((d), compat_data)->ocd_data + #define A10_READ_4(sc, reg) \ bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) #define A10_WRITE_4(sc, reg, data) \ bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) static device_attach_t a10_ehci_attach; static device_detach_t a10_ehci_detach; bs_r_1_proto(reversed); bs_w_1_proto(reversed); +struct aw_ehci_conf { + int (*clk_activate)(void); + int (*clk_deactivate)(void); + bool sdram_init; +}; + +static const struct aw_ehci_conf a10_ehci_conf = { +#if defined(SOC_ALLWINNER_A10) || defined(SOC_ALLWINNER_A20) + .clk_activate = a10_clk_usb_activate, + .clk_deactivate = a10_clk_usb_deactivate, +#endif + .sdram_init = true, +}; + +static const struct aw_ehci_conf a31_ehci_conf = { +#if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S) + .clk_activate = a31_clk_ehci_activate, + .clk_deactivate = a31_clk_ehci_deactivate, +#endif +}; + static struct ofw_compat_data compat_data[] = { - {"allwinner,sun4i-a10-ehci", 1}, - {"allwinner,sun7i-a20-ehci", 1}, - {NULL, 0} + { "allwinner,sun4i-a10-ehci", (uintptr_t)&a10_ehci_conf }, + { "allwinner,sun6i-a31-ehci", (uintptr_t)&a31_ehci_conf }, + { "allwinner,sun7i-a20-ehci", (uintptr_t)&a10_ehci_conf }, + { NULL, (uintptr_t)NULL } }; static int a10_ehci_probe(device_t self) { if (!ofw_bus_status_okay(self)) return (ENXIO); if (ofw_bus_search_compatible(self, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(self, EHCI_HC_DEVSTR); return (BUS_PROBE_DEFAULT); } static int a10_ehci_attach(device_t self) { ehci_softc_t *sc = device_get_softc(self); + const struct aw_ehci_conf *conf; bus_space_handle_t bsh; - device_t sc_gpio_dev; int err; int rid; uint32_t reg_value = 0; + conf = USB_CONF(self); + if (conf->clk_activate == NULL) { + device_printf(self, "clock not supported\n"); + return (ENXIO); + } + /* initialise some bus fields */ sc->sc_bus.parent = self; sc->sc_bus.devices = sc->sc_devices; sc->sc_bus.devices_max = EHCI_MAX_DEVICES; sc->sc_bus.dma_bits = 32; /* get all DMA memory */ if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) { return (ENOMEM); } sc->sc_bus.usbrev = USB_REV_2_0; rid = 0; sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_io_res) { device_printf(self, "Could not map memory\n"); goto error; } sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); bsh = rman_get_bushandle(sc->sc_io_res); sc->sc_io_size = rman_get_size(sc->sc_io_res); if (bus_space_subregion(sc->sc_io_tag, bsh, 0x00, sc->sc_io_size, &sc->sc_io_hdl) != 0) panic("%s: unable to subregion USB host registers", device_get_name(self)); rid = 0; sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); if (sc->sc_irq_res == NULL) { device_printf(self, "Could not allocate irq\n"); goto error; } sc->sc_bus.bdev = device_add_child(self, "usbus", -1); if (!sc->sc_bus.bdev) { device_printf(self, "Could not add USB device\n"); goto error; } device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); device_set_desc(sc->sc_bus.bdev, EHCI_HC_DEVSTR); sprintf(sc->sc_vendor, "Allwinner"); - /* Get the GPIO device, we need this to give power to USB */ - sc_gpio_dev = devclass_get_device(devclass_find("gpio"), 0); - if (sc_gpio_dev == NULL) { - device_printf(self, "Error: failed to get the GPIO device\n"); - goto error; - } - err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl); if (err) { device_printf(self, "Could not setup irq, %d\n", err); sc->sc_intr_hdl = NULL; goto error; } sc->sc_flags |= EHCI_SCFLG_DONTRESET; /* Enable clock for USB */ - a10_clk_usb_activate(); + if (conf->clk_activate() != 0) { + device_printf(self, "Could not activate clock\n"); + goto error; + } - /* Give power to USB */ - GPIO_PIN_SETFLAGS(sc_gpio_dev, GPIO_USB2_PWR, GPIO_PIN_OUTPUT); - GPIO_PIN_SET(sc_gpio_dev, GPIO_USB2_PWR, GPIO_PIN_HIGH); - - /* Give power to USB */ - GPIO_PIN_SETFLAGS(sc_gpio_dev, GPIO_USB1_PWR, GPIO_PIN_OUTPUT); - GPIO_PIN_SET(sc_gpio_dev, GPIO_USB1_PWR, GPIO_PIN_HIGH); - /* Enable passby */ reg_value = A10_READ_4(sc, SW_USB_PMU_IRQ_ENABLE); reg_value |= SW_AHB_INCR8; /* AHB INCR8 enable */ reg_value |= SW_AHB_INCR4; /* AHB burst type INCR4 enable */ reg_value |= SW_AHB_INCRX_ALIGN; /* AHB INCRX align enable */ reg_value |= SW_ULPI_BYPASS; /* ULPI bypass enable */ A10_WRITE_4(sc, SW_USB_PMU_IRQ_ENABLE, reg_value); /* Configure port */ - reg_value = A10_READ_4(sc, SW_SDRAM_REG_HPCR_USB2); - reg_value |= SW_SDRAM_BP_HPCR_ACCESS; - A10_WRITE_4(sc, SW_SDRAM_REG_HPCR_USB2, reg_value); + if (conf->sdram_init) { + reg_value = A10_READ_4(sc, SW_SDRAM_REG_HPCR_USB2); + reg_value |= SW_SDRAM_BP_HPCR_ACCESS; + A10_WRITE_4(sc, SW_SDRAM_REG_HPCR_USB2, reg_value); + } err = ehci_init(sc); if (!err) { err = device_probe_and_attach(sc->sc_bus.bdev); } if (err) { device_printf(self, "USB init failed err=%d\n", err); goto error; } return (0); error: a10_ehci_detach(self); return (ENXIO); } static int a10_ehci_detach(device_t self) { ehci_softc_t *sc = device_get_softc(self); + const struct aw_ehci_conf *conf; device_t bdev; int err; uint32_t reg_value = 0; + conf = USB_CONF(self); + if (sc->sc_bus.bdev) { bdev = sc->sc_bus.bdev; device_detach(bdev); device_delete_child(self, bdev); } /* during module unload there are lots of children leftover */ device_delete_children(self); if (sc->sc_irq_res && sc->sc_intr_hdl) { /* * only call ehci_detach() after ehci_init() */ ehci_detach(sc); err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); if (err) /* XXX or should we panic? */ device_printf(self, "Could not tear down irq, %d\n", err); sc->sc_intr_hdl = NULL; } if (sc->sc_irq_res) { bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res); sc->sc_irq_res = NULL; } if (sc->sc_io_res) { bus_release_resource(self, SYS_RES_MEMORY, 0, sc->sc_io_res); sc->sc_io_res = NULL; } usb_bus_mem_free_all(&sc->sc_bus, &ehci_iterate_hw_softc); /* Disable configure port */ - reg_value = A10_READ_4(sc, SW_SDRAM_REG_HPCR_USB2); - reg_value &= ~SW_SDRAM_BP_HPCR_ACCESS; - A10_WRITE_4(sc, SW_SDRAM_REG_HPCR_USB2, reg_value); + if (conf->sdram_init) { + reg_value = A10_READ_4(sc, SW_SDRAM_REG_HPCR_USB2); + reg_value &= ~SW_SDRAM_BP_HPCR_ACCESS; + A10_WRITE_4(sc, SW_SDRAM_REG_HPCR_USB2, reg_value); + } /* Disable passby */ reg_value = A10_READ_4(sc, SW_USB_PMU_IRQ_ENABLE); reg_value &= ~SW_AHB_INCR8; /* AHB INCR8 disable */ reg_value &= ~SW_AHB_INCR4; /* AHB burst type INCR4 disable */ reg_value &= ~SW_AHB_INCRX_ALIGN; /* AHB INCRX align disable */ reg_value &= ~SW_ULPI_BYPASS; /* ULPI bypass disable */ A10_WRITE_4(sc, SW_USB_PMU_IRQ_ENABLE, reg_value); /* Disable clock for USB */ - a10_clk_usb_deactivate(); + conf->clk_deactivate(); return (0); } static device_method_t ehci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, a10_ehci_probe), DEVMETHOD(device_attach, a10_ehci_attach), DEVMETHOD(device_detach, a10_ehci_detach), DEVMETHOD(device_suspend, bus_generic_suspend), DEVMETHOD(device_resume, bus_generic_resume), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD_END }; static driver_t ehci_driver = { .name = "ehci", .methods = ehci_methods, .size = sizeof(ehci_softc_t), }; static devclass_t ehci_devclass; DRIVER_MODULE(ehci, simplebus, ehci_driver, ehci_devclass, 0, 0); MODULE_DEPEND(ehci, usb, 1, 1, 1); Index: head/sys/arm/allwinner/a31/a31_clk.c =================================================================== --- head/sys/arm/allwinner/a31/a31_clk.c (revision 296283) +++ head/sys/arm/allwinner/a31/a31_clk.c (revision 296284) @@ -1,295 +1,378 @@ /*- * Copyright (c) 2013 Ganbold Tsagaankhuu * Copyright (c) 2016 Emmanuel Vadot * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Simple clock driver for Allwinner A31 * Adapted from a10_clk.c */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include struct a31_ccm_softc { struct resource *res; + struct mtx mtx; int pll6_enabled; + int ehci_refcnt; }; static struct a31_ccm_softc *a31_ccm_sc = NULL; #define ccm_read_4(sc, reg) \ bus_read_4((sc)->res, (reg)) #define ccm_write_4(sc, reg, val) \ bus_write_4((sc)->res, (reg), (val)) +#define CCM_LOCK(sc) mtx_lock(&(sc)->mtx) +#define CCM_UNLOCK(sc) mtx_unlock(&(sc)->mtx) + #define PLL6_TIMEOUT 10 static int a31_ccm_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "allwinner,sun6i-a31-ccm")) { device_set_desc(dev, "Allwinner Clock Control Module"); return(BUS_PROBE_DEFAULT); } return (ENXIO); } static int a31_ccm_attach(device_t dev) { struct a31_ccm_softc *sc = device_get_softc(dev); int rid = 0; if (a31_ccm_sc) return (ENXIO); sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->res) { device_printf(dev, "could not allocate resource\n"); return (ENXIO); } + mtx_init(&sc->mtx, "a31 ccm", NULL, MTX_DEF); + a31_ccm_sc = sc; return (0); } static device_method_t a31_ccm_methods[] = { DEVMETHOD(device_probe, a31_ccm_probe), DEVMETHOD(device_attach, a31_ccm_attach), { 0, 0 } }; static driver_t a31_ccm_driver = { "a31_ccm", a31_ccm_methods, sizeof(struct a31_ccm_softc), }; static devclass_t a31_ccm_devclass; EARLY_DRIVER_MODULE(a31_ccm, simplebus, a31_ccm_driver, a31_ccm_devclass, 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); static int a31_clk_pll6_enable(void) { struct a31_ccm_softc *sc; uint32_t reg_value; int i; /* Datasheet recommand to use the default 600Mhz value */ sc = a31_ccm_sc; if (sc->pll6_enabled) return (0); reg_value = ccm_read_4(sc, A31_CCM_PLL6_CFG); reg_value |= A31_CCM_PLL_CFG_ENABLE; ccm_write_4(sc, A31_CCM_PLL6_CFG, reg_value); /* Wait for PLL to be stable */ for (i = 0; i < PLL6_TIMEOUT; i++) if ((ccm_read_4(sc, A31_CCM_PLL6_CFG) & A31_CCM_PLL6_CFG_REG_LOCK) == A31_CCM_PLL6_CFG_REG_LOCK) break; if (i == PLL6_TIMEOUT) return (ENXIO); sc->pll6_enabled = 1; return (0); } static unsigned int a31_clk_pll6_get_rate(void) { struct a31_ccm_softc *sc; uint32_t k, n, reg_value; sc = a31_ccm_sc; reg_value = ccm_read_4(sc, A31_CCM_PLL6_CFG); n = ((reg_value & A31_CCM_PLL_CFG_FACTOR_N) >> A31_CCM_PLL_CFG_FACTOR_N_SHIFT); k = ((reg_value & A31_CCM_PLL_CFG_FACTOR_K) >> A31_CCM_PLL_CFG_FACTOR_K_SHIFT) + 1; return ((A31_CCM_CLK_REF_FREQ * n * k) / 2); } int a31_clk_gmac_activate(phandle_t node) { char *phy_type; struct a31_ccm_softc *sc; uint32_t reg_value; sc = a31_ccm_sc; if (sc == NULL) return (ENXIO); if (a31_clk_pll6_enable()) return (ENXIO); /* Gating AHB clock for GMAC */ reg_value = ccm_read_4(sc, A31_CCM_AHB_GATING0); reg_value |= A31_CCM_AHB_GATING_GMAC; ccm_write_4(sc, A31_CCM_AHB_GATING0, reg_value); /* Set GMAC mode. */ reg_value = A31_CCM_GMAC_CLK_MII; if (OF_getprop_alloc(node, "phy-mode", 1, (void **)&phy_type) > 0) { if (strcasecmp(phy_type, "rgmii") == 0) reg_value = A31_CCM_GMAC_CLK_RGMII | A31_CCM_GMAC_MODE_RGMII; free(phy_type, M_OFWPROP); } ccm_write_4(sc, A31_CCM_GMAC_CLK, reg_value); /* Reset gmac */ reg_value = ccm_read_4(sc, A31_CCM_AHB1_RST_REG0); reg_value |= A31_CCM_AHB1_RST_REG0_GMAC; ccm_write_4(sc, A31_CCM_AHB1_RST_REG0, reg_value); return (0); } int a31_clk_mmc_activate(int devid) { struct a31_ccm_softc *sc; uint32_t reg_value; sc = a31_ccm_sc; if (sc == NULL) return (ENXIO); if (a31_clk_pll6_enable()) return (ENXIO); /* Gating AHB clock for SD/MMC */ reg_value = ccm_read_4(sc, A31_CCM_AHB_GATING0); reg_value |= A31_CCM_AHB_GATING_SDMMC0 << devid; ccm_write_4(sc, A31_CCM_AHB_GATING0, reg_value); /* Soft reset */ reg_value = ccm_read_4(sc, A31_CCM_AHB1_RST_REG0); reg_value |= A31_CCM_AHB1_RST_REG0_SDMMC << devid; ccm_write_4(sc, A31_CCM_AHB1_RST_REG0, reg_value); return (0); } int a31_clk_mmc_cfg(int devid, int freq) { struct a31_ccm_softc *sc; uint32_t clksrc, m, n, ophase, phase, reg_value; unsigned int pll_freq; sc = a31_ccm_sc; if (sc == NULL) return (ENXIO); freq /= 1000; if (freq <= 400) { pll_freq = A31_CCM_CLK_REF_FREQ / 1000; clksrc = A31_CCM_SD_CLK_SRC_SEL_OSC24M; ophase = 0; phase = 0; n = 2; } else if (freq <= 25000) { pll_freq = a31_clk_pll6_get_rate() / 1000; clksrc = A31_CCM_SD_CLK_SRC_SEL_PLL6; ophase = 0; phase = 5; n = 2; } else if (freq <= 50000) { pll_freq = a31_clk_pll6_get_rate() / 1000; clksrc = A31_CCM_SD_CLK_SRC_SEL_PLL6; ophase = 3; phase = 5; n = 0; } else return (EINVAL); m = ((pll_freq / (1 << n)) / (freq)) - 1; reg_value = ccm_read_4(sc, A31_CCM_MMC0_SCLK_CFG + (devid * 4)); reg_value &= ~A31_CCM_SD_CLK_SRC_SEL; reg_value |= (clksrc << A31_CCM_SD_CLK_SRC_SEL_SHIFT); reg_value &= ~A31_CCM_SD_CLK_PHASE_CTR; reg_value |= (phase << A31_CCM_SD_CLK_PHASE_CTR_SHIFT); reg_value &= ~A31_CCM_SD_CLK_DIV_RATIO_N; reg_value |= (n << A31_CCM_SD_CLK_DIV_RATIO_N_SHIFT); reg_value &= ~A31_CCM_SD_CLK_OPHASE_CTR; reg_value |= (ophase << A31_CCM_SD_CLK_OPHASE_CTR_SHIFT); reg_value &= ~A31_CCM_SD_CLK_DIV_RATIO_M; reg_value |= m; reg_value |= A31_CCM_PLL_CFG_ENABLE; ccm_write_4(sc, A31_CCM_MMC0_SCLK_CFG + (devid * 4), reg_value); return (0); } int a31_clk_i2c_activate(int devid) { struct a31_ccm_softc *sc; uint32_t reg_value; sc = a31_ccm_sc; if (sc == NULL) return (ENXIO); if (a31_clk_pll6_enable()) return (ENXIO); /* Gating APB clock for I2C/TWI */ reg_value = ccm_read_4(sc, A31_CCM_APB2_GATING); reg_value |= A31_CCM_APB2_GATING_TWI << devid; ccm_write_4(sc, A31_CCM_APB2_GATING, reg_value); /* Soft reset */ reg_value = ccm_read_4(sc, A31_CCM_APB2_RST); reg_value |= A31_CCM_APB2_RST_TWI << devid; ccm_write_4(sc, A31_CCM_APB2_RST, reg_value); + + return (0); +} + +int +a31_clk_ehci_activate(void) +{ + struct a31_ccm_softc *sc; + uint32_t reg_value; + + sc = a31_ccm_sc; + if (sc == NULL) + return (ENXIO); + + CCM_LOCK(sc); + if (++sc->ehci_refcnt == 1) { + /* Enable USB PHY */ + reg_value = ccm_read_4(sc, A31_CCM_USBPHY_CLK); + reg_value |= A31_CCM_USBPHY_CLK_GATING_USBPHY0; + reg_value |= A31_CCM_USBPHY_CLK_GATING_USBPHY1; + reg_value |= A31_CCM_USBPHY_CLK_GATING_USBPHY2; + reg_value |= A31_CCM_USBPHY_CLK_USBPHY1_RST; + reg_value |= A31_CCM_USBPHY_CLK_USBPHY2_RST; + ccm_write_4(sc, A31_CCM_USBPHY_CLK, reg_value); + + /* Gating AHB clock for EHCI */ + reg_value = ccm_read_4(sc, A31_CCM_AHB_GATING0); + reg_value |= A31_CCM_AHB_GATING_EHCI0; + reg_value |= A31_CCM_AHB_GATING_EHCI1; + ccm_write_4(sc, A31_CCM_AHB_GATING0, reg_value); + + /* De-assert reset */ + reg_value = ccm_read_4(sc, A31_CCM_AHB1_RST_REG0); + reg_value |= A31_CCM_AHB1_RST_REG0_EHCI0; + reg_value |= A31_CCM_AHB1_RST_REG0_EHCI1; + ccm_write_4(sc, A31_CCM_AHB1_RST_REG0, reg_value); + } + CCM_UNLOCK(sc); + + return (0); +} + +int +a31_clk_ehci_deactivate(void) +{ + struct a31_ccm_softc *sc; + uint32_t reg_value; + + sc = a31_ccm_sc; + if (sc == NULL) + return (ENXIO); + + CCM_LOCK(sc); + if (--sc->ehci_refcnt == 0) { + /* Disable USB PHY */ + reg_value = ccm_read_4(sc, A31_CCM_USBPHY_CLK); + reg_value &= ~A31_CCM_USBPHY_CLK_GATING_USBPHY0; + reg_value &= ~A31_CCM_USBPHY_CLK_GATING_USBPHY1; + reg_value &= ~A31_CCM_USBPHY_CLK_GATING_USBPHY2; + reg_value &= ~A31_CCM_USBPHY_CLK_USBPHY1_RST; + reg_value &= ~A31_CCM_USBPHY_CLK_USBPHY2_RST; + ccm_write_4(sc, A31_CCM_USBPHY_CLK, reg_value); + + /* Gating AHB clock for EHCI */ + reg_value = ccm_read_4(sc, A31_CCM_AHB_GATING0); + reg_value &= ~A31_CCM_AHB_GATING_EHCI0; + reg_value &= ~A31_CCM_AHB_GATING_EHCI1; + ccm_write_4(sc, A31_CCM_AHB_GATING0, reg_value); + + /* Assert reset */ + reg_value = ccm_read_4(sc, A31_CCM_AHB1_RST_REG0); + reg_value &= ~A31_CCM_AHB1_RST_REG0_EHCI0; + reg_value &= ~A31_CCM_AHB1_RST_REG0_EHCI1; + ccm_write_4(sc, A31_CCM_AHB1_RST_REG0, reg_value); + } + CCM_UNLOCK(sc); return (0); } Index: head/sys/arm/allwinner/a31/a31_clk.h =================================================================== --- head/sys/arm/allwinner/a31/a31_clk.h (revision 296283) +++ head/sys/arm/allwinner/a31/a31_clk.h (revision 296284) @@ -1,189 +1,213 @@ /*- * Copyright (c) 2013 Ganbold Tsagaankhuu * Copyright (c) 2016 Emmanuel Vadot * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _A31_CLK_H_ #define _A31_CLK_H_ #define A31_CCM_PLL1_CFG 0x0000 #define A31_CCM_PLL2_CFG 0x0008 #define A31_CCM_PLL3_CFG 0x0010 #define A31_CCM_PLL4_CFG 0x0018 #define A31_CCM_PLL5_CFG 0x0020 #define A31_CCM_PLL6_CFG 0x0028 #define A31_CCM_PLL7_CFG 0x0030 #define A31_CCM_PLL8_CFG 0x0038 #define A31_CCM_MIPI_PLL_CFG 0x0040 #define A31_CCM_PLL9_CFG 0x0044 #define A31_CCM_PLL10_CFG 0x0048 #define A31_CCM_AXI_CFG_REG 0x0050 #define A31_CCM_AHB1_APB1_CFG 0x0054 #define A31_CCM_APB2_CLK_DIV 0x0058 #define A31_CCM_AHB_GATING0 0x0060 #define A31_CCM_AHB_GATING1 0x0064 #define A31_CCM_APB1_GATING 0x0068 #define A31_CCM_APB2_GATING 0x006c #define A31_CCM_NAND0_SCLK_CFG 0x0080 #define A31_CCM_NAND1_SCLK_CFG 0x0084 #define A31_CCM_MMC0_SCLK_CFG 0x0088 #define A31_CCM_MMC1_SCLK_CFG 0x008c #define A31_CCM_MMC2_SCLK_CFG 0x0090 #define A31_CCM_MMC3_SCLK_CFG 0x0094 #define A31_CCM_TS_CLK 0x0098 #define A31_CCM_SS_CLK 0x009c #define A31_CCM_SPI0_CLK 0x00a0 #define A31_CCM_SPI1_CLK 0x00a4 #define A31_CCM_SPI2_CLK 0x00a8 #define A31_CCM_SPI3_CLK 0x00ac #define A31_CCM_DAUDIO0_CLK 0x00b0 #define A31_CCM_DAUDIO1_CLK 0x00b4 #define A31_CCM_USBPHY_CLK 0x00cc #define A31_CCM_GMAC_CLK 0x00d0 #define A31_CCM_MDFS_CLK 0x00f0 #define A31_CCM_DRAM_CLK 0x00f4 #define A31_CCM_DRAM_GATING 0x0100 #define A31_CCM_BE0_SCLK 0x0104 #define A31_CCM_BE1_SCLK 0x0108 #define A31_CCM_FE0_CLK 0x010c #define A31_CCM_FE1_CLK 0x0110 #define A31_CCM_MP_CLK 0x0114 #define A31_CCM_LCD0_CH0_CLK 0x0118 #define A31_CCM_LCD1_CH0_CLK 0x011c #define A31_CCM_LCD0_CH1_CLK 0x012c #define A31_CCM_LCD1_CH1_CLK 0x0130 #define A31_CCM_CSI0_CLK 0x0134 #define A31_CCM_CSI1_CLK 0x0138 #define A31_CCM_VE_CLK 0x013c #define A31_CCM_AUDIO_CODEC_CLK 0x0140 #define A31_CCM_AVS_CLK 0x0144 #define A31_CCM_DIGITAL_MIC_CLK 0x0148 #define A31_CCM_HDMI_CLK 0x0150 #define A31_CCM_PS_CLK 0x0154 #define A31_CCM_MBUS_SCLK_CFG0 0x015c #define A31_CCM_MBUS_SCLK_CFG1 0x0160 #define A31_CCM_MIPI_DSI_CLK 0x0168 #define A31_CCM_MIPI_CSI0_CLK 0x016c #define A31_CCM_DRC0_SCLK_CFG 0x0180 #define A31_CCM_DRC1_SCLK_CFG 0x0184 #define A31_CCM_DEU0_SCLK_CFG 0x0188 #define A31_CCM_DEU1_SCLK_CFG 0x018c #define A31_CCM_GPU_CORE_CLK 0x01a0 #define A31_CCM_GPU_MEM_CLK 0x01a4 #define A31_CCM_GPU_HYD_CLK 0x01a8 #define A31_CCM_ATS_CLK 0x01b0 #define A31_CCM_TRACE_CLK 0x01b4 #define A31_CCM_PLL_LOCK_CFG 0x0200 #define A31_CCM_PLL1_LOCK_CFG 0x0204 #define A31_CCM_PLL1_BIAS 0x0220 #define A31_CCM_PLL2_BIAS 0x0224 #define A31_CCM_PLL3_BIAS 0x0228 #define A31_CCM_PLL4_BIAS 0x022c #define A31_CCM_PLL5_BIAS 0x0230 #define A31_CCM_PLL6_BIAS 0x0234 #define A31_CCM_PLL7_BIAS 0x0238 #define A31_CCM_PLL8_BIAS 0x023c #define A31_CCM_PLL9_BIAS 0x0240 #define A31_CCM_MIPI_PLL_BIAS 0x0244 #define A31_CCM_PLL10_BIAS 0x0248 #define A31_CCM_PLL1_PAT_CFG 0x0280 #define A31_CCM_PLL2_PAT_CFG 0x0284 #define A31_CCM_PLL3_PAT_CFG 0x0288 #define A31_CCM_PLL4_PAT_CFG 0x028c #define A31_CCM_PLL5_PAT_CFG 0x0290 #define A31_CCM_PLL6_PAT_CFG 0x0294 #define A31_CCM_PLL7_PAT_CFG 0x0298 #define A31_CCM_PLL8_PAT_CFG 0x029c #define A31_CCM_MIPI_PLL_PAT_CFG 0x02a0 #define A31_CCM_PLL9_PAT_CFG 0x02a4 #define A31_CCM_PLL10_PAT_CFG 0x02a8 #define A31_CCM_AHB1_RST_REG0 0x02c0 #define A31_CCM_AHB1_RST_REG1 0x02c4 #define A31_CCM_AHB1_RST_REG2 0x02c8 #define A31_CCM_APB1_RST 0x02d0 #define A31_CCM_APB2_RST 0x02d8 #define A31_CCM_CLK_OUTA 0x0300 #define A31_CCM_CLK_OUTB 0x0304 #define A31_CCM_CLK_OUTC 0x0308 /* PLL6_CFG_REG */ #define A31_CCM_PLL6_CFG_REG_LOCK (1 << 28) /* AHB_GATING_REG0 */ -#define A31_CCM_AHB_GATING_SDMMC0 (1 << 8) +#define A31_CCM_AHB_GATING_OHCI2 (1 << 31) +#define A31_CCM_AHB_GATING_OHCI1 (1 << 30) +#define A31_CCM_AHB_GATING_OHCI0 (1 << 29) +#define A31_CCM_AHB_GATING_EHCI1 (1 << 27) +#define A31_CCM_AHB_GATING_EHCI0 (1 << 26) +#define A31_CCM_AHB_GATING_USBDRD (1 << 24) #define A31_CCM_AHB_GATING_GMAC (1 << 17) +#define A31_CCM_AHB_GATING_SDMMC0 (1 << 8) #define A31_CCM_PLL_CFG_ENABLE (1U << 31) #define A31_CCM_PLL_CFG_BYPASS (1U << 30) #define A31_CCM_PLL_CFG_PLL5 (1U << 25) #define A31_CCM_PLL_CFG_PLL6 (1U << 24) #define A31_CCM_PLL_CFG_FACTOR_N 0x1f00 #define A31_CCM_PLL_CFG_FACTOR_N_SHIFT 8 #define A31_CCM_PLL_CFG_FACTOR_K 0x30 #define A31_CCM_PLL_CFG_FACTOR_K_SHIFT 4 #define A31_CCM_PLL_CFG_FACTOR_M 0x3 /* APB2_GATING */ #define A31_CCM_APB2_GATING_TWI (1 << 0) /* AHB1_RST_REG0 */ +#define A31_CCM_AHB1_RST_REG0_OHCI2 (1 << 31) +#define A31_CCM_AHB1_RST_REG0_OHCI1 (1 << 30) +#define A31_CCM_AHB1_RST_REG0_OHCI0 (1 << 29) +#define A31_CCM_AHB1_RST_REG0_EHCI1 (1 << 27) +#define A31_CCM_AHB1_RST_REG0_EHCI0 (1 << 26) #define A31_CCM_AHB1_RST_REG0_GMAC (1 << 17) #define A31_CCM_AHB1_RST_REG0_SDMMC (1 << 8) /* APB2_RST_REG */ #define A31_CCM_APB2_RST_TWI (1 << 0) /* GMAC */ #define A31_CCM_GMAC_CLK_DELAY_SHIFT 10 #define A31_CCM_GMAC_CLK_MODE_MASK 0x7 #define A31_CCM_GMAC_MODE_RGMII (1 << 2) #define A31_CCM_GMAC_CLK_MII 0x0 #define A31_CCM_GMAC_CLK_EXT_RGMII 0x1 #define A31_CCM_GMAC_CLK_RGMII 0x2 /* SD/MMC */ #define A31_CCM_SD_CLK_SRC_SEL 0x3000000 #define A31_CCM_SD_CLK_SRC_SEL_SHIFT 24 #define A31_CCM_SD_CLK_SRC_SEL_OSC24M 0 #define A31_CCM_SD_CLK_SRC_SEL_PLL6 1 #define A31_CCM_SD_CLK_PHASE_CTR 0x700000 #define A31_CCM_SD_CLK_PHASE_CTR_SHIFT 20 #define A31_CCM_SD_CLK_DIV_RATIO_N 0x30000 #define A31_CCM_SD_CLK_DIV_RATIO_N_SHIFT 16 #define A31_CCM_SD_CLK_OPHASE_CTR 0x700 #define A31_CCM_SD_CLK_OPHASE_CTR_SHIFT 8 #define A31_CCM_SD_CLK_DIV_RATIO_M 0xf +/* USB */ +#define A31_CCM_USBPHY_CLK_GATING_OHCI2 (1 << 18) +#define A31_CCM_USBPHY_CLK_GATING_OHCI1 (1 << 17) +#define A31_CCM_USBPHY_CLK_GATING_OHCI0 (1 << 16) +#define A31_CCM_USBPHY_CLK_GATING_USBPHY2 (1 << 10) +#define A31_CCM_USBPHY_CLK_GATING_USBPHY1 (1 << 9) +#define A31_CCM_USBPHY_CLK_GATING_USBPHY0 (1 << 8) +#define A31_CCM_USBPHY_CLK_USBPHY2_RST (1 << 2) +#define A31_CCM_USBPHY_CLK_USBPHY1_RST (1 << 1) +#define A31_CCM_USBPHY_CLK_USBPHY0_RST (1 << 0) + #define A31_CCM_CLK_REF_FREQ 24000000U int a31_clk_gmac_activate(phandle_t); int a31_clk_mmc_activate(int); int a31_clk_mmc_cfg(int, int); int a31_clk_i2c_activate(int); +int a31_clk_ehci_activate(void); +int a31_clk_ehci_deactivate(void); #endif /* _A31_CLK_H_ */ Index: head/sys/arm/allwinner/aw_usbphy.c =================================================================== --- head/sys/arm/allwinner/aw_usbphy.c (nonexistent) +++ head/sys/arm/allwinner/aw_usbphy.c (revision 296284) @@ -0,0 +1,192 @@ +/*- + * Copyright (c) 2016 Jared McNeill + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Allwinner USB PHY + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "gpio_if.h" + +#define USBPHY_NUMOFF 3 +#define GPIO_POLARITY(flags) (((flags) & 1) ? GPIO_PIN_LOW : GPIO_PIN_HIGH) + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun4i-a10-usb-phy", 1 }, + { "allwinner,sun5i-a13-usb-phy", 1 }, + { "allwinner,sun6i-a31-usb-phy", 1 }, + { "allwinner,sun7i-a20-usb-phy", 1 }, + { NULL, 0 } +}; + +static int +awusbphy_gpio_set(device_t dev, phandle_t node, const char *pname) +{ + pcell_t gpio_prop[4]; + phandle_t gpio_node; + device_t gpio_dev; + uint32_t pin, flags; + ssize_t len; + int val; + + len = OF_getencprop(node, pname, gpio_prop, sizeof(gpio_prop)); + if (len == -1) + return (0); + + if (len != sizeof(gpio_prop)) { + device_printf(dev, "property %s length was %d, expected %d\n", + pname, len, sizeof(gpio_prop)); + return (ENXIO); + } + + gpio_node = OF_node_from_xref(gpio_prop[0]); + gpio_dev = OF_device_from_xref(gpio_prop[0]); + if (gpio_dev == NULL) { + device_printf(dev, "failed to get the GPIO device for %s\n", + pname); + return (ENOENT); + } + + if (GPIO_MAP_GPIOS(gpio_dev, node, gpio_node, + sizeof(gpio_prop) / sizeof(gpio_prop[0]) - 1, gpio_prop + 1, + &pin, &flags) != 0) { + device_printf(dev, "failed to map the GPIO pin for %s\n", + pname); + return (ENXIO); + } + + val = GPIO_POLARITY(flags); + + GPIO_PIN_SETFLAGS(gpio_dev, pin, GPIO_PIN_OUTPUT); + GPIO_PIN_SET(gpio_dev, pin, val); + + return (0); +} + +static int +awusbphy_supply_set(device_t dev, const char *pname) +{ + phandle_t node, reg_node; + pcell_t reg_xref; + + node = ofw_bus_get_node(dev); + + if (OF_getencprop(node, pname, ®_xref, sizeof(reg_xref)) == -1) + return (0); + + reg_node = OF_node_from_xref(reg_xref); + + return (awusbphy_gpio_set(dev, reg_node, "gpio")); +} + +static int +awusbphy_init(device_t dev) +{ + char pname[20]; + phandle_t node; + int error, off; + + node = ofw_bus_get_node(dev); + + for (off = 0; off < USBPHY_NUMOFF; off++) { + snprintf(pname, sizeof(pname), "usb%d_id_det-gpio", off); + error = awusbphy_gpio_set(dev, node, pname); + if (error) + return (error); + + snprintf(pname, sizeof(pname), "usb%d_vbus_det-gpio", off); + error = awusbphy_gpio_set(dev, node, pname); + if (error) + return (error); + + snprintf(pname, sizeof(pname), "usb%d_vbus-supply", off); + error = awusbphy_supply_set(dev, pname); + if (error) + return (error); + } + + return (0); +} + +static int +awusbphy_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Allwinner USB PHY"); + return (BUS_PROBE_DEFAULT); +} + +static int +awusbphy_attach(device_t dev) +{ + int error; + + error = awusbphy_init(dev); + if (error) + device_printf(dev, "failed to initialize USB PHY, error %d\n", + error); + + return (error); +} + +static device_method_t awusbphy_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, awusbphy_probe), + DEVMETHOD(device_attach, awusbphy_attach), + + DEVMETHOD_END +}; + +static driver_t awusbphy_driver = { + "awusbphy", + awusbphy_methods, + 0, +}; + +static devclass_t awusbphy_devclass; + +DRIVER_MODULE(awusbphy, simplebus, awusbphy_driver, awusbphy_devclass, 0, 0); +MODULE_VERSION(awusbphy, 1); Property changes on: head/sys/arm/allwinner/aw_usbphy.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/allwinner/files.allwinner =================================================================== --- head/sys/arm/allwinner/files.allwinner (revision 296283) +++ head/sys/arm/allwinner/files.allwinner (revision 296284) @@ -1,26 +1,27 @@ # $FreeBSD$ kern/kern_clocksource.c standard arm/allwinner/a10_ahci.c optional ahci arm/allwinner/a10_clk.c standard arm/allwinner/a10_codec.c optional sound arm/allwinner/a10_common.c standard arm/allwinner/a10_dmac.c standard arm/allwinner/a10_ehci.c optional ehci +arm/allwinner/aw_usbphy.c optional ehci arm/allwinner/a10_gpio.c optional gpio arm/allwinner/a10_mmc.c optional mmc arm/allwinner/a10_sramc.c standard arm/allwinner/aw_rtc.c standard arm/allwinner/aw_wdog.c standard arm/allwinner/a20/a20_cpu_cfg.c standard arm/allwinner/allwinner_machdep.c standard arm/allwinner/axp209.c optional axp209 arm/allwinner/if_emac.c optional emac arm/allwinner/sunxi_dma_if.m standard dev/iicbus/twsi/a10_twsi.c optional twsi #arm/allwinner/console.c standard arm/allwinner/a10_fb.c optional vt arm/allwinner/a10_hdmi.c optional hdmi arm/allwinner/a10_hdmiaudio.c optional hdmi sound arm/arm/hdmi_if.m optional hdmi