Index: head/sys/arm64/cavium/thunder_pcie.c =================================================================== --- head/sys/arm64/cavium/thunder_pcie.c (revision 295961) +++ head/sys/arm64/cavium/thunder_pcie.c (nonexistent) @@ -1,425 +0,0 @@ -/*- - * Copyright (c) 2015 The FreeBSD Foundation - * All rights reserved. - * - * This software was developed by Semihalf under - * the sponsorship of the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* PCIe root complex driver for Cavium Thunder SOC */ -#include "opt_platform.h" - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "thunder_pcie_common.h" - -#include "pcib_if.h" - -/* Assembling ECAM Configuration Address */ -#define PCIE_BUS_SHIFT 20 -#define PCIE_SLOT_SHIFT 15 -#define PCIE_FUNC_SHIFT 12 -#define PCIE_BUS_MASK 0xFF -#define PCIE_SLOT_MASK 0x1F -#define PCIE_FUNC_MASK 0x07 -#define PCIE_REG_MASK 0xFFF - -#define PCIE_ADDR_OFFSET(bus, slot, func, reg) \ - ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \ - (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \ - (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \ - ((reg) & PCIE_REG_MASK)) - -#define THUNDER_ECAM0_CFG_BASE 0x848000000000UL -#define THUNDER_ECAM1_CFG_BASE 0x849000000000UL -#define THUNDER_ECAM2_CFG_BASE 0x84a000000000UL -#define THUNDER_ECAM3_CFG_BASE 0x84b000000000UL -#define THUNDER_ECAM4_CFG_BASE 0x948000000000UL -#define THUNDER_ECAM5_CFG_BASE 0x949000000000UL -#define THUNDER_ECAM6_CFG_BASE 0x94a000000000UL -#define THUNDER_ECAM7_CFG_BASE 0x94b000000000UL - -/* - * ThunderX supports up to 4 ethernet interfaces, so it's good - * value to use as default for numbers of VFs, since each eth - * interface represents separate virtual function. - */ -static int thunder_pcie_max_vfs = 4; -SYSCTL_INT(_hw, OID_AUTO, thunder_pcie_max_vfs, CTLFLAG_RWTUN, - &thunder_pcie_max_vfs, 0, "Max VFs supported by ThunderX internal PCIe"); - -/* Forward prototypes */ -static int thunder_pcie_identify_pcib(device_t); -static int thunder_pcie_maxslots(device_t); -static uint32_t thunder_pcie_read_config(device_t, u_int, u_int, u_int, u_int, - int); -static int thunder_pcie_read_ivar(device_t, device_t, int, uintptr_t *); -static void thunder_pcie_write_config(device_t, u_int, u_int, - u_int, u_int, uint32_t, int); -static int thunder_pcie_write_ivar(device_t, device_t, int, uintptr_t); - -int -thunder_pcie_attach(device_t dev) -{ - int rid; - struct thunder_pcie_softc *sc; - int error; - int tuple; - uint64_t base, size; - - sc = device_get_softc(dev); - sc->dev = dev; - - /* Identify pcib domain */ - if (thunder_pcie_identify_pcib(dev)) - return (ENXIO); - - rid = 0; - sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); - if (sc->res == NULL) { - device_printf(dev, "could not map memory.\n"); - return (ENXIO); - } - - sc->mem_rman.rm_type = RMAN_ARRAY; - sc->mem_rman.rm_descr = "PCIe Memory"; - - /* Initialize rman and allocate memory regions */ - error = rman_init(&sc->mem_rman); - if (error) { - device_printf(dev, "rman_init() failed. error = %d\n", error); - return (error); - } - - for (tuple = 0; tuple < RANGES_TUPLES_MAX; tuple++) { - base = sc->ranges[tuple].phys_base; - size = sc->ranges[tuple].size; - if ((base == 0) || (size == 0)) - continue; /* empty range element */ - - error = rman_manage_region(&sc->mem_rman, base, base + size - 1); - if (error) { - device_printf(dev, "rman_manage_region() failed. error = %d\n", error); - rman_fini(&sc->mem_rman); - return (error); - } - } - device_add_child(dev, "pci", -1); - - return (bus_generic_attach(dev)); -} - -static uint32_t -thunder_pcie_read_config(device_t dev, u_int bus, u_int slot, - u_int func, u_int reg, int bytes) -{ - uint64_t offset; - uint32_t data; - struct thunder_pcie_softc *sc; - bus_space_tag_t t; - bus_space_handle_t h; - - if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || - (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) - return (~0U); - - sc = device_get_softc(dev); - - offset = PCIE_ADDR_OFFSET(bus, slot, func, reg); - t = rman_get_bustag(sc->res); - h = rman_get_bushandle(sc->res); - - switch (bytes) { - case 1: - data = bus_space_read_1(t, h, offset); - break; - case 2: - data = le16toh(bus_space_read_2(t, h, offset)); - break; - case 4: - data = le32toh(bus_space_read_4(t, h, offset)); - break; - default: - return (~0U); - } - - return (data); -} - -static void -thunder_pcie_write_config(device_t dev, u_int bus, u_int slot, - u_int func, u_int reg, uint32_t val, int bytes) -{ - uint64_t offset; - struct thunder_pcie_softc *sc; - bus_space_tag_t t; - bus_space_handle_t h; - - if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || - (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) - return ; - - sc = device_get_softc(dev); - - offset = PCIE_ADDR_OFFSET(bus, slot, func, reg); - t = rman_get_bustag(sc->res); - h = rman_get_bushandle(sc->res); - - switch (bytes) { - case 1: - bus_space_write_1(t, h, offset, val); - break; - case 2: - bus_space_write_2(t, h, offset, htole16(val)); - break; - case 4: - bus_space_write_4(t, h, offset, htole32(val)); - break; - default: - return; - } - -} - -static int -thunder_pcie_maxslots(device_t dev) -{ - - /* max slots per bus acc. to standard */ - return (PCI_SLOTMAX); -} - -static int -thunder_pcie_read_ivar(device_t dev, device_t child, int index, - uintptr_t *result) -{ - struct thunder_pcie_softc *sc; - - sc = device_get_softc(dev); - - if (index == PCIB_IVAR_BUS) { - /* this pcib is always on bus 0 */ - *result = 0; - return (0); - } - if (index == PCIB_IVAR_DOMAIN) { - *result = sc->ecam; - return (0); - } - - return (ENOENT); -} - -static int -thunder_pcie_write_ivar(device_t dev, device_t child, int index, - uintptr_t value) -{ - - return (ENOENT); -} - -int -thunder_pcie_release_resource(device_t dev, device_t child, int type, int rid, - struct resource *res) -{ - - if (type != SYS_RES_MEMORY) - return (bus_generic_release_resource(dev, child, - type, rid, res)); - - return (rman_release_resource(res)); -} - -struct resource * -thunder_pcie_alloc_resource(device_t dev, device_t child, int type, int *rid, - rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) -{ - struct thunder_pcie_softc *sc = device_get_softc(dev); - struct rman *rm = NULL; - struct resource *res; - pci_addr_t map, testval; - - switch (type) { - case SYS_RES_IOPORT: - goto fail; - break; - case SYS_RES_MEMORY: - rm = &sc->mem_rman; - break; - default: - return (bus_generic_alloc_resource(dev, child, - type, rid, start, end, count, flags)); - }; - - if (RMAN_IS_DEFAULT_RANGE(start, end)) { - - /* Read BAR manually to get resource address and size */ - pci_read_bar(child, *rid, &map, &testval, NULL); - - /* Mask the information bits */ - if (PCI_BAR_MEM(map)) - map &= PCIM_BAR_MEM_BASE; - else - map &= PCIM_BAR_IO_BASE; - - if (PCI_BAR_MEM(testval)) - testval &= PCIM_BAR_MEM_BASE; - else - testval &= PCIM_BAR_IO_BASE; - - start = map; - count = (~testval) + 1; - /* - * Internal ThunderX devices supports up to 3 64-bit BARs. - * If we're allocating anything above, that means upper layer - * wants us to allocate VF-BAR. In that case reserve bigger - * slice to make a room for other VFs adjacent to this one. - */ - if (*rid > PCIR_BAR(5)) - count = count * thunder_pcie_max_vfs; - end = start + count - 1; - } - - /* Convert input BUS address to required PHYS */ - if (range_addr_is_pci(sc->ranges, start, count) == 0) - goto fail; - start = range_addr_pci_to_phys(sc->ranges, start); - end = start + count - 1; - - if (bootverbose) { - device_printf(dev, - "rman_reserve_resource: start=%#lx, end=%#lx, count=%#lx\n", - start, end, count); - } - - res = rman_reserve_resource(rm, start, end, count, flags, child); - if (res == NULL) - goto fail; - - rman_set_rid(res, *rid); - - if ((flags & RF_ACTIVE) != 0) - if (bus_activate_resource(child, type, *rid, res)) { - rman_release_resource(res); - goto fail; - } - - return (res); - -fail: - if (bootverbose) { - device_printf(dev, "%s FAIL: type=%d, rid=%d, " - "start=%016lx, end=%016lx, count=%016lx, flags=%x\n", - __func__, type, *rid, start, end, count, flags); - } - - return (NULL); -} - -static int -thunder_pcie_identify_pcib(device_t dev) -{ - struct thunder_pcie_softc *sc; - rman_res_t start; - - sc = device_get_softc(dev); - start = bus_get_resource_start(dev, SYS_RES_MEMORY, 0); - - switch(start) { - case THUNDER_ECAM0_CFG_BASE: - sc->ecam = 0; - break; - case THUNDER_ECAM1_CFG_BASE: - sc->ecam = 1; - break; - case THUNDER_ECAM2_CFG_BASE: - sc->ecam = 2; - break; - case THUNDER_ECAM3_CFG_BASE: - sc->ecam = 3; - break; - case THUNDER_ECAM4_CFG_BASE: - sc->ecam = 4; - break; - case THUNDER_ECAM5_CFG_BASE: - sc->ecam = 5; - break; - case THUNDER_ECAM6_CFG_BASE: - sc->ecam = 6; - break; - case THUNDER_ECAM7_CFG_BASE: - sc->ecam = 7; - break; - default: - device_printf(dev, - "error: incorrect resource address=%#lx.\n", start); - return (ENXIO); - } - return (0); -} - -static device_method_t thunder_pcie_methods[] = { - DEVMETHOD(pcib_maxslots, thunder_pcie_maxslots), - DEVMETHOD(pcib_read_config, thunder_pcie_read_config), - DEVMETHOD(pcib_write_config, thunder_pcie_write_config), - DEVMETHOD(bus_read_ivar, thunder_pcie_read_ivar), - DEVMETHOD(bus_write_ivar, thunder_pcie_write_ivar), - DEVMETHOD(bus_alloc_resource, thunder_pcie_alloc_resource), - DEVMETHOD(bus_release_resource, thunder_pcie_release_resource), - DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), - DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), - DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), - DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), - - DEVMETHOD(pcib_map_msi, arm_map_msi), - DEVMETHOD(pcib_alloc_msix, arm_alloc_msix), - DEVMETHOD(pcib_release_msix, arm_release_msix), - DEVMETHOD(pcib_alloc_msi, arm_alloc_msi), - DEVMETHOD(pcib_release_msi, arm_release_msi), - - DEVMETHOD_END -}; - -DEFINE_CLASS_0(pcib, thunder_pcie_driver, thunder_pcie_methods, - sizeof(struct thunder_pcie_softc)); Property changes on: head/sys/arm64/cavium/thunder_pcie.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/arm64/cavium/thunder_pcie_common.c =================================================================== --- head/sys/arm64/cavium/thunder_pcie_common.c (revision 295961) +++ head/sys/arm64/cavium/thunder_pcie_common.c (revision 295962) @@ -1,111 +1,144 @@ /*- * Copyright (c) 2015 The FreeBSD Foundation * All rights reserved. * * This software was developed by Semihalf under * the sponsorship of the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* Common PCIe functions for Cavium Thunder SOC */ #include __FBSDID("$FreeBSD$"); +#include "opt_platform.h" + #include #include #include #include #include #include #include #include #include +#ifdef FDT +#include +#include +#include +#include +#endif + +#include +#include +#include +#include + #include "thunder_pcie_common.h" MALLOC_DEFINE(M_THUNDER_PCIE, "Thunder PCIe driver", "Thunder PCIe driver memory"); +#define THUNDER_CFG_BASE_TO_ECAM(x) ((((x) >> 36UL) & 0x3) | (((x) >> 42UL) & 0x4)) + uint32_t range_addr_is_pci(struct pcie_range *ranges, uint64_t addr, uint64_t size) { struct pcie_range *r; int tuple; - for (tuple = 0; tuple < RANGES_TUPLES_MAX; tuple++) { + for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { r = &ranges[tuple]; if (addr >= r->pci_base && addr < (r->pci_base + r->size) && size < r->size) { /* Address is within PCI range */ return (1); } } /* Address is outside PCI range */ return (0); } uint32_t range_addr_is_phys(struct pcie_range *ranges, uint64_t addr, uint64_t size) { struct pcie_range *r; int tuple; - for (tuple = 0; tuple < RANGES_TUPLES_MAX; tuple++) { + for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { r = &ranges[tuple]; if (addr >= r->phys_base && addr < (r->phys_base + r->size) && size < r->size) { /* Address is within Physical range */ return (1); } } /* Address is outside Physical range */ return (0); } uint64_t range_addr_pci_to_phys(struct pcie_range *ranges, uint64_t pci_addr) { struct pcie_range *r; uint64_t offset; int tuple; /* Find physical address corresponding to given bus address */ - for (tuple = 0; tuple < RANGES_TUPLES_MAX; tuple++) { + for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { r = &ranges[tuple]; if (pci_addr >= r->pci_base && pci_addr < (r->pci_base + r->size)) { /* Given pci addr is in this range. * Translate bus addr to phys addr. */ offset = pci_addr - r->pci_base; return (r->phys_base + offset); } } return (0); } +int +thunder_pcie_identify_ecam(device_t dev, int *ecam) +{ + rman_res_t start; + + /* Check if we're running on Cavium ThunderX */ + if (!CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK, + CPU_IMPL_CAVIUM, CPU_PART_THUNDER, 0, 0)) + return (EINVAL); + + start = bus_get_resource_start(dev, SYS_RES_MEMORY, 0); + *ecam = THUNDER_CFG_BASE_TO_ECAM(start); + + device_printf(dev, "ThunderX quirk, setting ECAM to %d\n", *ecam); + + return (0); +} Index: head/sys/arm64/cavium/thunder_pcie_common.h =================================================================== --- head/sys/arm64/cavium/thunder_pcie_common.h (revision 295961) +++ head/sys/arm64/cavium/thunder_pcie_common.h (revision 295962) @@ -1,71 +1,43 @@ /*- * Copyright (c) 2015 The FreeBSD Foundation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _CAVIUM_THUNDER_PCIE_COMMON_H_ #define _CAVIUM_THUNDER_PCIE_COMMON_H_ -#define RANGES_TUPLES_MAX 6 -#define RANGES_TUPLES_INVALID (RANGES_TUPLES_MAX + 1) - DECLARE_CLASS(thunder_pcie_driver); DECLARE_CLASS(thunder_pem_driver); MALLOC_DECLARE(M_THUNDER_PCIE); -struct pcie_range { - uint64_t pci_base; - uint64_t phys_base; - uint64_t size; - uint64_t flags; -}; - -struct thunder_pcie_softc { - struct pcie_range ranges[RANGES_TUPLES_MAX]; - struct rman mem_rman; - struct resource *res; - int ecam; - device_t dev; -}; - uint32_t range_addr_is_pci(struct pcie_range *, uint64_t, uint64_t); uint32_t range_addr_is_phys(struct pcie_range *, uint64_t, uint64_t); uint64_t range_addr_pci_to_phys(struct pcie_range *, uint64_t); -int thunder_common_alloc_msi(device_t, device_t, int, int, int *); -int thunder_common_alloc_msix(device_t, device_t, int *); -int thunder_common_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); -int thunder_common_release_msi(device_t, device_t, int, int *); -int thunder_common_release_msix(device_t, device_t, int); -struct resource *thunder_pcie_alloc_resource(device_t, - device_t, int, int *, rman_res_t, rman_res_t, rman_res_t, u_int); -int thunder_pcie_release_resource(device_t, device_t, int, int, - struct resource *); - -int thunder_pcie_attach(device_t); +int thunder_pcie_identify_ecam(device_t, int *); #endif /* _CAVIUM_THUNDER_PCIE_COMMON_H_ */ Index: head/sys/arm64/cavium/thunder_pcie_fdt.c =================================================================== --- head/sys/arm64/cavium/thunder_pcie_fdt.c (revision 295961) +++ head/sys/arm64/cavium/thunder_pcie_fdt.c (revision 295962) @@ -1,382 +1,107 @@ /* * Copyright (C) 2016 Cavium Inc. * All rights reserved. * * Developed by Semihalf. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include +#include #include "thunder_pcie_common.h" -#define OFW_CELL_TO_UINT64(cell) \ - (((uint64_t)(*(cell)) << 32) | (uint64_t)(*((cell) + 1))) - -#define SPACE_CODE_SHIFT 24 -#define SPACE_CODE_MASK 0x3 -#define SPACE_CODE_IO_SPACE 0x1 -#define PROPS_CELL_SIZE 1 -#define PCI_ADDR_CELL_SIZE 2 - -static int thunder_pcie_fdt_probe(device_t); static int thunder_pcie_fdt_attach(device_t); +static int thunder_pcie_fdt_probe(device_t); -static struct resource * thunder_pcie_ofw_bus_alloc_res(device_t, device_t, - int, int *, rman_res_t, rman_res_t, rman_res_t, u_int); -static int thunder_pcie_ofw_bus_rel_res(device_t, device_t, int, int, - struct resource *); - -static const struct ofw_bus_devinfo *thunder_pcie_ofw_get_devinfo(device_t, - device_t); - static device_method_t thunder_pcie_fdt_methods[] = { /* Device interface */ DEVMETHOD(device_probe, thunder_pcie_fdt_probe), DEVMETHOD(device_attach, thunder_pcie_fdt_attach), - /* Bus interface */ - DEVMETHOD(bus_alloc_resource, thunder_pcie_ofw_bus_alloc_res), - DEVMETHOD(bus_release_resource, thunder_pcie_ofw_bus_rel_res), - DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), - - /* ofw_bus interface */ - DEVMETHOD(ofw_bus_get_devinfo, thunder_pcie_ofw_get_devinfo), - DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), - DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), - DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), - DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), - DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), - /* End */ DEVMETHOD_END }; DEFINE_CLASS_1(pcib, thunder_pcie_fdt_driver, thunder_pcie_fdt_methods, - sizeof(struct thunder_pcie_softc), thunder_pcie_driver); + sizeof(struct generic_pcie_softc), generic_pcie_driver); static devclass_t thunder_pcie_fdt_devclass; DRIVER_MODULE(thunder_pcib, simplebus, thunder_pcie_fdt_driver, thunder_pcie_fdt_devclass, 0, 0); DRIVER_MODULE(thunder_pcib, ofwbus, thunder_pcie_fdt_driver, thunder_pcie_fdt_devclass, 0, 0); -static int thunder_pcie_fdt_ranges(device_t); -static int thunder_pcie_ofw_bus_attach(device_t); static int thunder_pcie_fdt_probe(device_t dev) { + /* Check if we're running on Cavium ThunderX */ + if (!CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK, + CPU_IMPL_CAVIUM, CPU_PART_THUNDER, 0, 0)) + return (ENXIO); + if (!ofw_bus_status_okay(dev)) return (ENXIO); - if (ofw_bus_is_compatible(dev, "cavium,thunder-pcie") || + if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic") || + ofw_bus_is_compatible(dev, "cavium,thunder-pcie") || ofw_bus_is_compatible(dev, "cavium,pci-host-thunder-ecam")) { device_set_desc(dev, "Cavium Integrated PCI/PCI-E Controller"); return (BUS_PROBE_DEFAULT); } return (ENXIO); } static int thunder_pcie_fdt_attach(device_t dev) { - int err; + struct generic_pcie_softc *sc; - /* Retrieve 'ranges' property from FDT */ - if (thunder_pcie_fdt_ranges(dev) != 0) - return (ENXIO); - - err = thunder_pcie_ofw_bus_attach(dev); - if (err != 0) - return (err); - - return (thunder_pcie_attach(dev)); -} - -static __inline void -get_addr_size_cells(phandle_t node, pcell_t *addr_cells, pcell_t *size_cells) -{ - - *addr_cells = 2; - /* Find address cells if present */ - OF_getencprop(node, "#address-cells", addr_cells, sizeof(*addr_cells)); - - *size_cells = 2; - /* Find size cells if present */ - OF_getencprop(node, "#size-cells", size_cells, sizeof(*size_cells)); -} - -static int -thunder_pcie_fdt_ranges(device_t dev) -{ - struct thunder_pcie_softc *sc; - phandle_t node; - pcell_t pci_addr_cells, parent_addr_cells, size_cells; - pcell_t attributes; - pcell_t *ranges_buf, *cell_ptr; - int cells_count, tuples_count; - int tuple; - int rv; - sc = device_get_softc(dev); - node = ofw_bus_get_node(dev); + thunder_pcie_identify_ecam(dev, &sc->ecam); - get_addr_size_cells(node, &pci_addr_cells, &size_cells); - - /* Find parent address cells if present */ - if (OF_getencprop(OF_parent(node), "#address-cells", - &parent_addr_cells, sizeof(parent_addr_cells)) < sizeof(parent_addr_cells)) - parent_addr_cells = 2; - - /* Check if FDT format matches driver requirements */ - if ((parent_addr_cells != 2) || (pci_addr_cells != 3) || - (size_cells != 2)) { - device_printf(dev, - "Unexpected number of address or size cells in FDT " - " %d:%d:%d\n", - parent_addr_cells, pci_addr_cells, size_cells); - return (ENXIO); - } - - cells_count = OF_getencprop_alloc(node, "ranges", - sizeof(pcell_t), (void **)&ranges_buf); - if (cells_count == -1) { - device_printf(dev, "Error parsing FDT 'ranges' property\n"); - return (ENXIO); - } - - tuples_count = cells_count / - (pci_addr_cells + parent_addr_cells + size_cells); - if (tuples_count > RANGES_TUPLES_MAX) { - device_printf(dev, - "Unexpected number of 'ranges' tuples in FDT\n"); - rv = ENXIO; - goto out; - } - - cell_ptr = ranges_buf; - - for (tuple = 0; tuple < tuples_count; tuple++) { - /* - * TUPLE FORMAT: - * attributes - 32-bit attributes field - * PCI address - bus address combined of two cells in - * a following format: - * - * PA address - physical address combined of two cells in - * a following format: - * - * size - range size combined of two cells in - * a following format: - * - */ - attributes = *cell_ptr; - attributes = (attributes >> SPACE_CODE_SHIFT) & SPACE_CODE_MASK; - if (attributes == SPACE_CODE_IO_SPACE) { - /* Internal PCIe does not support IO space, ignore. */ - sc->ranges[tuple].phys_base = 0; - sc->ranges[tuple].size = 0; - cell_ptr += - (pci_addr_cells + parent_addr_cells + size_cells); - continue; - } - cell_ptr += PROPS_CELL_SIZE; - sc->ranges[tuple].pci_base = OFW_CELL_TO_UINT64(cell_ptr); - cell_ptr += PCI_ADDR_CELL_SIZE; - sc->ranges[tuple].phys_base = OFW_CELL_TO_UINT64(cell_ptr); - cell_ptr += parent_addr_cells; - sc->ranges[tuple].size = OFW_CELL_TO_UINT64(cell_ptr); - cell_ptr += size_cells; - - if (bootverbose) { - device_printf(dev, - "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx\n", - sc->ranges[tuple].pci_base, - sc->ranges[tuple].phys_base, - sc->ranges[tuple].size); - } - - } - for (; tuple < RANGES_TUPLES_MAX; tuple++) { - /* zero-fill remaining tuples to mark empty elements in array */ - sc->ranges[tuple].phys_base = 0; - sc->ranges[tuple].size = 0; - } - - rv = 0; -out: - free(ranges_buf, M_OFWPROP); - return (rv); + return (pci_host_generic_attach(dev)); } -/* OFW bus interface */ -struct thunder_pcie_ofw_devinfo { - struct ofw_bus_devinfo di_dinfo; - struct resource_list di_rl; -}; - -static const struct ofw_bus_devinfo * -thunder_pcie_ofw_get_devinfo(device_t bus __unused, device_t child) -{ - struct thunder_pcie_ofw_devinfo *di; - - di = device_get_ivars(child); - return (&di->di_dinfo); -} - -static struct resource * -thunder_pcie_ofw_bus_alloc_res(device_t bus, device_t child, int type, int *rid, - rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) -{ - struct thunder_pcie_softc *sc; - struct thunder_pcie_ofw_devinfo *di; - struct resource_list_entry *rle; - int i; - - /* For PCIe devices that do not have FDT nodes, use PCIB method */ - if ((int)ofw_bus_get_node(child) <= 0) { - return (thunder_pcie_alloc_resource(bus, child, type, rid, - start, end, count, flags)); - } - - sc = device_get_softc(bus); - - if (RMAN_IS_DEFAULT_RANGE(start, end)) { - if ((di = device_get_ivars(child)) == NULL) - return (NULL); - if (type == SYS_RES_IOPORT) - type = SYS_RES_MEMORY; - - /* Find defaults for this rid */ - rle = resource_list_find(&di->di_rl, type, *rid); - if (rle == NULL) - return (NULL); - - start = rle->start; - end = rle->end; - count = rle->count; - } - - if (type == SYS_RES_MEMORY) { - /* Remap through ranges property */ - for (i = 0; i < RANGES_TUPLES_MAX; i++) { - if (start >= sc->ranges[i].phys_base && end < - sc->ranges[i].pci_base + sc->ranges[i].size) { - start -= sc->ranges[i].phys_base; - start += sc->ranges[i].pci_base; - end -= sc->ranges[i].phys_base; - end += sc->ranges[i].pci_base; - break; - } - } - - if (i == RANGES_TUPLES_MAX) { - device_printf(bus, "Could not map resource " - "%#lx-%#lx\n", start, end); - return (NULL); - } - } - - return (bus_generic_alloc_resource(bus, child, type, rid, start, end, - count, flags)); -} - -static int -thunder_pcie_ofw_bus_rel_res(device_t bus, device_t child, int type, int rid, - struct resource *res) -{ - - /* For PCIe devices that do not have FDT nodes, use PCIB method */ - if ((int)ofw_bus_get_node(child) <= 0) { - return (thunder_pcie_release_resource(bus, - child, type, rid, res)); - } - - return (bus_generic_release_resource(bus, child, type, rid, res)); -} - -/* Helper functions */ - -static int -thunder_pcie_ofw_bus_attach(device_t dev) -{ - struct thunder_pcie_ofw_devinfo *di; - device_t child; - phandle_t parent, node; - pcell_t addr_cells, size_cells; - - parent = ofw_bus_get_node(dev); - if (parent > 0) { - get_addr_size_cells(parent, &addr_cells, &size_cells); - /* Iterate through all bus subordinates */ - for (node = OF_child(parent); node > 0; node = OF_peer(node)) { - /* Allocate and populate devinfo. */ - di = malloc(sizeof(*di), M_THUNDER_PCIE, M_WAITOK | M_ZERO); - if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) { - free(di, M_THUNDER_PCIE); - continue; - } - - /* Initialize and populate resource list. */ - resource_list_init(&di->di_rl); - ofw_bus_reg_to_rl(dev, node, addr_cells, size_cells, - &di->di_rl); - ofw_bus_intr_to_rl(dev, node, &di->di_rl, NULL); - - /* Add newbus device for this FDT node */ - child = device_add_child(dev, NULL, -1); - if (child == NULL) { - resource_list_free(&di->di_rl); - ofw_bus_gen_destroy_devinfo(&di->di_dinfo); - free(di, M_THUNDER_PCIE); - continue; - } - - device_set_ivars(child, di); - } - } - - return (0); -} Index: head/sys/arm64/cavium/thunder_pcie_pem.c =================================================================== --- head/sys/arm64/cavium/thunder_pcie_pem.c (revision 295961) +++ head/sys/arm64/cavium/thunder_pcie_pem.c (revision 295962) @@ -1,644 +1,654 @@ /*- * Copyright (c) 2015 The FreeBSD Foundation * All rights reserved. * * This software was developed by Semihalf under * the sponsorship of the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* PCIe external MAC root complex driver (PEM) for Cavium Thunder SOC */ #include __FBSDID("$FreeBSD$"); +#include "opt_platform.h" + #include #include #include #include #include #include #include #include +#ifdef FDT +#include +#include +#include +#include +#endif + #include #include +#include #include #include #include #include #include #include #include "pcib_if.h" #define THUNDER_PEM_DEVICE_ID 0xa020 #define THUNDER_PEM_VENDOR_ID 0x177d /* ThunderX specific defines */ #define THUNDER_PEMn_REG_BASE(unit) (0x87e0c0000000UL | ((unit) << 24)) #define PCIERC_CFG002 0x08 #define PCIERC_CFG006 0x18 #define PCIERC_CFG032 0x80 #define PCIERC_CFG006_SEC_BUS(reg) (((reg) >> 8) & 0xFF) #define PEM_CFG_RD_REG_ALIGN(reg) ((reg) & ~0x3) #define PEM_CFG_RD_REG_DATA(val) (((val) >> 32) & 0xFFFFFFFF) #define PEM_CFG_RD 0x30 #define PEM_CFG_LINK_MASK 0x3 #define PEM_CFG_LINK_RDY 0x3 #define PEM_CFG_SLIX_TO_REG(slix) ((slix) << 4) #define SBNUM_OFFSET 0x8 #define SBNUM_MASK 0xFF #define PEM_ON_REG 0x420 #define PEM_CTL_STATUS 0x0 #define PEM_LINK_ENABLE (1 << 4) #define PEM_LINK_DLLA (1 << 29) #define PEM_LINK_LT (1 << 27) #define PEM_BUS_SHIFT (24) #define PEM_SLOT_SHIFT (19) #define PEM_FUNC_SHIFT (16) #define SLIX_S2M_REGX_ACC 0x874001000000UL #define SLIX_S2M_REGX_ACC_SIZE 0x1000 #define SLIX_S2M_REGX_ACC_SPACING 0x001000000000UL #define SLI_BASE 0x880000000000UL #define SLI_WINDOW_SPACING 0x004000000000UL #define SLI_WINDOW_SIZE 0x0000FF000000UL #define SLI_PCI_OFFSET 0x001000000000UL #define SLI_NODE_SHIFT (44) #define SLI_NODE_MASK (3) #define SLI_GROUP_SHIFT (40) #define SLI_ID_SHIFT (24) #define SLI_ID_MASK (7) #define SLI_PEMS_PER_GROUP (3) #define SLI_GROUPS_PER_NODE (2) #define SLI_PEMS_PER_NODE (SLI_PEMS_PER_GROUP * SLI_GROUPS_PER_NODE) #define SLI_ACC_REG_CNT (256) /* * Each PEM device creates its own bus with * own address translation, so we can adjust bus addresses * as we want. To support 32-bit cards let's assume * PCI window assignment looks as following: * * 0x00000000 - 0x000FFFFF IO * 0x00100000 - 0xFFFFFFFF Memory */ #define PCI_IO_BASE 0x00000000UL #define PCI_IO_SIZE 0x00100000UL #define PCI_MEMORY_BASE PCI_IO_SIZE #define PCI_MEMORY_SIZE 0xFFF00000UL #define RID_PEM_SPACE 1 static struct resource * thunder_pem_alloc_resource(device_t, device_t, int, int *, rman_res_t, rman_res_t, rman_res_t, u_int); static int thunder_pem_attach(device_t); static int thunder_pem_detach(device_t); static uint64_t thunder_pem_config_reg_read(struct thunder_pem_softc *, int); static int thunder_pem_link_init(struct thunder_pem_softc *); static int thunder_pem_maxslots(device_t); static int thunder_pem_probe(device_t); static uint32_t thunder_pem_read_config(device_t, u_int, u_int, u_int, u_int, int); static int thunder_pem_read_ivar(device_t, device_t, int, uintptr_t *); static void thunder_pem_release_all(device_t); static int thunder_pem_release_resource(device_t, device_t, int, int, struct resource *); static void thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *, int, int); static void thunder_pem_write_config(device_t, u_int, u_int, u_int, u_int, uint32_t, int); static int thunder_pem_write_ivar(device_t, device_t, int, uintptr_t); /* Global handlers for SLI interface */ static bus_space_handle_t sli0_s2m_regx_base = 0; static bus_space_handle_t sli1_s2m_regx_base = 0; static device_method_t thunder_pem_methods[] = { /* Device interface */ DEVMETHOD(device_probe, thunder_pem_probe), DEVMETHOD(device_attach, thunder_pem_attach), DEVMETHOD(device_detach, thunder_pem_detach), DEVMETHOD(pcib_maxslots, thunder_pem_maxslots), DEVMETHOD(pcib_read_config, thunder_pem_read_config), DEVMETHOD(pcib_write_config, thunder_pem_write_config), DEVMETHOD(bus_read_ivar, thunder_pem_read_ivar), DEVMETHOD(bus_write_ivar, thunder_pem_write_ivar), DEVMETHOD(bus_alloc_resource, thunder_pem_alloc_resource), DEVMETHOD(bus_release_resource, thunder_pem_release_resource), DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), DEVMETHOD(pcib_map_msi, arm_map_msi), DEVMETHOD(pcib_alloc_msix, arm_alloc_msix), DEVMETHOD(pcib_release_msix, arm_release_msix), DEVMETHOD(pcib_alloc_msi, arm_alloc_msi), DEVMETHOD(pcib_release_msi, arm_release_msi), DEVMETHOD_END }; DEFINE_CLASS_0(pcib, thunder_pem_driver, thunder_pem_methods, sizeof(struct thunder_pem_softc)); static devclass_t thunder_pem_devclass; DRIVER_MODULE(thunder_pem, pci, thunder_pem_driver, thunder_pem_devclass, 0, 0); MODULE_DEPEND(thunder_pem, pci, 1, 1, 1); static int thunder_pem_maxslots(device_t dev) { #if 0 /* max slots per bus acc. to standard */ return (PCI_SLOTMAX); #else /* * ARM64TODO Workaround - otherwise an em(4) interface appears to be * present on every PCI function on the bus to which it is connected */ return (0); #endif } static int thunder_pem_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) { struct thunder_pem_softc *sc; int secondary_bus = 0; sc = device_get_softc(dev); if (index == PCIB_IVAR_BUS) { secondary_bus = thunder_pem_config_reg_read(sc, PCIERC_CFG006); *result = PCIERC_CFG006_SEC_BUS(secondary_bus); return (0); } if (index == PCIB_IVAR_DOMAIN) { *result = sc->id; return (0); } return (ENOENT); } static int thunder_pem_write_ivar(device_t dev, device_t child, int index, uintptr_t value) { return (ENOENT); } static int thunder_pem_identify(device_t dev) { struct thunder_pem_softc *sc; rman_res_t start; sc = device_get_softc(dev); start = rman_get_start(sc->reg); /* Calculate PEM designations from its address */ sc->node = (start >> SLI_NODE_SHIFT) & SLI_NODE_MASK; sc->id = ((start >> SLI_ID_SHIFT) & SLI_ID_MASK) + (SLI_PEMS_PER_NODE * sc->node); sc->sli = sc->id % SLI_PEMS_PER_GROUP; sc->sli_group = (sc->id / SLI_PEMS_PER_GROUP) % SLI_GROUPS_PER_NODE; sc->sli_window_base = SLI_BASE | (((uint64_t)sc->node) << SLI_NODE_SHIFT) | ((uint64_t)sc->sli_group << SLI_GROUP_SHIFT); sc->sli_window_base += SLI_WINDOW_SPACING * sc->sli; return (0); } static void thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *sc, int sli_group, int slix) { uint64_t regval; bus_space_handle_t handle = 0; KASSERT(slix >= 0 && slix <= SLI_ACC_REG_CNT, ("Invalid SLI index")); if (sli_group == 0) handle = sli0_s2m_regx_base; else if (sli_group == 1) handle = sli1_s2m_regx_base; else device_printf(sc->dev, "SLI group is not correct\n"); if (handle) { /* Clear lower 32-bits of the SLIx register */ regval = bus_space_read_8(sc->reg_bst, handle, PEM_CFG_SLIX_TO_REG(slix)); regval &= ~(0xFFFFFFFFUL); bus_space_write_8(sc->reg_bst, handle, PEM_CFG_SLIX_TO_REG(slix), regval); } } static int thunder_pem_link_init(struct thunder_pem_softc *sc) { uint64_t regval; /* check whether PEM is safe to access. */ regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_ON_REG); if ((regval & PEM_CFG_LINK_MASK) != PEM_CFG_LINK_RDY) { device_printf(sc->dev, "PEM%d is not ON\n", sc->id); return (ENXIO); } regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS); regval |= PEM_LINK_ENABLE; bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS, regval); /* Wait 1ms as per Cavium specification */ DELAY(1000); regval = thunder_pem_config_reg_read(sc, PCIERC_CFG032); if (((regval & PEM_LINK_DLLA) == 0) || ((regval & PEM_LINK_LT) != 0)) { device_printf(sc->dev, "PCIe RC: Port %d Link Timeout\n", sc->id); return (ENXIO); } return (0); } static int thunder_pem_init(struct thunder_pem_softc *sc) { int i, retval = 0; retval = thunder_pem_link_init(sc); if (retval) { device_printf(sc->dev, "%s failed\n", __func__); return retval; } retval = bus_space_map(sc->reg_bst, sc->sli_window_base, SLI_WINDOW_SIZE, 0, &sc->pem_sli_base); if (retval) { device_printf(sc->dev, "Unable to map RC%d pem_addr base address", sc->id); return (ENOMEM); } /* To support 32-bit PCIe devices, set S2M_REGx_ACC[BA]=0x0 */ for (i = 0; i < SLI_ACC_REG_CNT; i++) { thunder_pem_slix_s2m_regx_acc_modify(sc, sc->sli_group, i); } return (retval); } static uint64_t thunder_pem_config_reg_read(struct thunder_pem_softc *sc, int reg) { uint64_t data; /* Write to ADDR register */ bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, PEM_CFG_RD_REG_ALIGN(reg)); bus_space_barrier(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, 8, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); /* Read from DATA register */ data = PEM_CFG_RD_REG_DATA(bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD)); return (data); } static uint32_t thunder_pem_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, int bytes) { uint64_t offset; uint32_t data; struct thunder_pem_softc *sc; bus_space_tag_t t; bus_space_handle_t h; if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) return (~0U); sc = device_get_softc(dev); /* Calculate offset */ offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) | (func << PEM_FUNC_SHIFT) | reg; t = sc->reg_bst; h = sc->pem_sli_base; switch (bytes) { case 1: data = bus_space_read_1(t, h, offset); break; case 2: data = le16toh(bus_space_read_2(t, h, offset)); break; case 4: data = le32toh(bus_space_read_4(t, h, offset)); break; default: return (~0U); } return (data); } static void thunder_pem_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, uint32_t val, int bytes) { uint64_t offset; struct thunder_pem_softc *sc; bus_space_tag_t t; bus_space_handle_t h; if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) return; sc = device_get_softc(dev); /* Calculate offset */ offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) | (func << PEM_FUNC_SHIFT) | reg; t = sc->reg_bst; h = sc->pem_sli_base; switch (bytes) { case 1: bus_space_write_1(t, h, offset, val); break; case 2: bus_space_write_2(t, h, offset, htole16(val)); break; case 4: bus_space_write_4(t, h, offset, htole32(val)); break; default: return; } } static struct resource * thunder_pem_alloc_resource(device_t dev, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) { struct thunder_pem_softc *sc = device_get_softc(dev); struct rman *rm = NULL; struct resource *res; device_t parent_dev; switch (type) { case SYS_RES_IOPORT: rm = &sc->io_rman; break; case SYS_RES_MEMORY: rm = &sc->mem_rman; break; default: /* Find parent device. On ThunderX we know an exact path. */ parent_dev = device_get_parent(device_get_parent(dev)); return (BUS_ALLOC_RESOURCE(parent_dev, dev, type, rid, start, end, count, flags)); }; if (RMAN_IS_DEFAULT_RANGE(start, end)) { device_printf(dev, "Cannot allocate resource with unspecified range\n"); goto fail; } /* Translate PCI address to host PHYS */ if (range_addr_is_pci(sc->ranges, start, count) == 0) goto fail; start = range_addr_pci_to_phys(sc->ranges, start); end = start + count - 1; if (bootverbose) { device_printf(dev, "rman_reserve_resource: start=%#lx, end=%#lx, count=%#lx\n", start, end, count); } res = rman_reserve_resource(rm, start, end, count, flags, child); if (res == NULL) goto fail; rman_set_rid(res, *rid); if (flags & RF_ACTIVE) if (bus_activate_resource(child, type, *rid, res)) { rman_release_resource(res); goto fail; } return (res); fail: if (bootverbose) { device_printf(dev, "%s FAIL: type=%d, rid=%d, " "start=%016lx, end=%016lx, count=%016lx, flags=%x\n", __func__, type, *rid, start, end, count, flags); } return (NULL); } static int thunder_pem_release_resource(device_t dev, device_t child, int type, int rid, struct resource *res) { device_t parent_dev; /* Find parent device. On ThunderX we know an exact path. */ parent_dev = device_get_parent(device_get_parent(dev)); if ((type != SYS_RES_MEMORY) && (type != SYS_RES_IOPORT)) return (BUS_RELEASE_RESOURCE(parent_dev, child, type, rid, res)); return (rman_release_resource(res)); } static int thunder_pem_probe(device_t dev) { uint16_t pci_vendor_id; uint16_t pci_device_id; pci_vendor_id = pci_get_vendor(dev); pci_device_id = pci_get_device(dev); if ((pci_vendor_id == THUNDER_PEM_VENDOR_ID) && (pci_device_id == THUNDER_PEM_DEVICE_ID)) { device_set_desc_copy(dev, THUNDER_PEM_DESC); return (0); } return (ENXIO); } static int thunder_pem_attach(device_t dev) { devclass_t pci_class; device_t parent; struct thunder_pem_softc *sc; int error; int rid; sc = device_get_softc(dev); sc->dev = dev; /* Allocate memory for resource */ pci_class = devclass_find("pci"); parent = device_get_parent(dev); if (device_get_devclass(parent) == pci_class) rid = PCIR_BAR(0); else rid = RID_PEM_SPACE; sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->reg == NULL) { device_printf(dev, "Failed to allocate resource\n"); return (ENXIO); } sc->reg_bst = rman_get_bustag(sc->reg); sc->reg_bsh = rman_get_bushandle(sc->reg); /* Map SLI, do it only once */ if (!sli0_s2m_regx_base) { bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC, SLIX_S2M_REGX_ACC_SIZE, 0, &sli0_s2m_regx_base); } if (!sli1_s2m_regx_base) { bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC + SLIX_S2M_REGX_ACC_SPACING, SLIX_S2M_REGX_ACC_SIZE, 0, &sli1_s2m_regx_base); } if ((sli0_s2m_regx_base == 0) || (sli1_s2m_regx_base == 0)) { device_printf(dev, "bus_space_map failed to map slix_s2m_regx_base\n"); goto fail; } /* Identify PEM */ if (thunder_pem_identify(dev) != 0) goto fail; /* Initialize rman and allocate regions */ sc->mem_rman.rm_type = RMAN_ARRAY; sc->mem_rman.rm_descr = "PEM PCIe Memory"; error = rman_init(&sc->mem_rman); if (error != 0) { device_printf(dev, "memory rman_init() failed. error = %d\n", error); goto fail; } sc->io_rman.rm_type = RMAN_ARRAY; sc->io_rman.rm_descr = "PEM PCIe IO"; error = rman_init(&sc->io_rman); if (error != 0) { device_printf(dev, "IO rman_init() failed. error = %d\n", error); goto fail_mem; } /* * We ignore the values that may have been provided in FDT * and configure ranges according to the below formula * for all types of devices. This is because some DTBs provided * by EFI do not have proper ranges property or don't have them * at all. */ /* Fill memory window */ sc->ranges[0].pci_base = PCI_MEMORY_BASE; sc->ranges[0].size = PCI_MEMORY_SIZE; sc->ranges[0].phys_base = sc->sli_window_base + SLI_PCI_OFFSET + sc->ranges[0].pci_base; rman_manage_region(&sc->mem_rman, sc->ranges[0].phys_base, sc->ranges[0].phys_base + sc->ranges[0].size - 1); /* Fill IO window */ sc->ranges[1].pci_base = PCI_IO_BASE; sc->ranges[1].size = PCI_IO_SIZE; sc->ranges[1].phys_base = sc->sli_window_base + SLI_PCI_OFFSET + sc->ranges[1].pci_base; rman_manage_region(&sc->io_rman, sc->ranges[1].phys_base, sc->ranges[1].phys_base + sc->ranges[1].size - 1); if (thunder_pem_init(sc)) { device_printf(dev, "Failure during PEM init\n"); goto fail_io; } device_add_child(dev, "pci", -1); return (bus_generic_attach(dev)); fail_io: rman_fini(&sc->io_rman); fail_mem: rman_fini(&sc->mem_rman); fail: bus_free_resource(dev, SYS_RES_MEMORY, sc->reg); return (ENXIO); } static void thunder_pem_release_all(device_t dev) { struct thunder_pem_softc *sc; sc = device_get_softc(dev); rman_fini(&sc->io_rman); rman_fini(&sc->mem_rman); if (sc->reg != NULL) bus_free_resource(dev, SYS_RES_MEMORY, sc->reg); } static int thunder_pem_detach(device_t dev) { thunder_pem_release_all(dev); return (0); } Index: head/sys/arm64/cavium/thunder_pcie_pem.h =================================================================== --- head/sys/arm64/cavium/thunder_pcie_pem.h (revision 295961) +++ head/sys/arm64/cavium/thunder_pcie_pem.h (revision 295962) @@ -1,53 +1,53 @@ /* * Copyright (C) 2016 Cavium Inc. * All rights reserved. * * Developed by Semihalf. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #ifndef __THUNDER_PCIE_PEM_H__ #define __THUNDER_PCIE_PEM_H__ #define THUNDER_PEM_DESC "ThunderX PEM" struct thunder_pem_softc { device_t dev; struct resource *reg; bus_space_tag_t reg_bst; bus_space_handle_t reg_bsh; - struct pcie_range ranges[RANGES_TUPLES_MAX]; + struct pcie_range ranges[MAX_RANGES_TUPLES]; struct rman mem_rman; struct rman io_rman; bus_space_handle_t pem_sli_base; uint32_t node; uint32_t id; uint32_t sli; uint32_t sli_group; uint64_t sli_window_base; }; #endif Index: head/sys/arm64/cavium/thunder_pcie_pem_fdt.c =================================================================== --- head/sys/arm64/cavium/thunder_pcie_pem_fdt.c (revision 295961) +++ head/sys/arm64/cavium/thunder_pcie_pem_fdt.c (revision 295962) @@ -1,83 +1,90 @@ /* * Copyright (C) 2016 Cavium Inc. * All rights reserved. * * Developed by Semihalf. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); +#include "opt_platform.h" + #include #include #include #include #include #include #include #include #include #include #include #include #include #include + +#include +#include +#include +#include #include "thunder_pcie_common.h" #include "thunder_pcie_pem.h" static int thunder_pem_fdt_probe(device_t); static device_method_t thunder_pem_fdt_methods[] = { /* Device interface */ DEVMETHOD(device_probe, thunder_pem_fdt_probe), /* End */ DEVMETHOD_END }; DEFINE_CLASS_1(pcib, thunder_pem_fdt_driver, thunder_pem_fdt_methods, sizeof(struct thunder_pem_softc), thunder_pem_driver); static devclass_t thunder_pem_fdt_devclass; DRIVER_MODULE(thunder_pem, simplebus, thunder_pem_fdt_driver, thunder_pem_fdt_devclass, 0, 0); DRIVER_MODULE(thunder_pem, ofwbus, thunder_pem_fdt_driver, thunder_pem_fdt_devclass, 0, 0); static int thunder_pem_fdt_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "cavium,pci-host-thunder-pem")) { device_set_desc(dev, THUNDER_PEM_DESC); return (BUS_PROBE_DEFAULT); } return (ENXIO); } Index: head/sys/conf/files.arm64 =================================================================== --- head/sys/conf/files.arm64 (revision 295961) +++ head/sys/conf/files.arm64 (revision 295962) @@ -1,98 +1,97 @@ # $FreeBSD$ arm/arm/devmap.c standard arm/arm/generic_timer.c standard arm/arm/pmu.c standard arm64/acpica/acpi_machdep.c optional acpi arm64/acpica/OsdEnvironment.c optional acpi arm64/acpica/acpi_wakeup.c optional acpi arm64/acpica/pci_cfgreg.c optional acpi pci arm64/arm64/autoconf.c standard arm64/arm64/bcopy.c standard arm64/arm64/bus_machdep.c standard arm64/arm64/bus_space_asm.S standard arm64/arm64/busdma_bounce.c standard arm64/arm64/busdma_machdep.c standard arm64/arm64/clock.c standard arm64/arm64/copyinout.S standard arm64/arm64/copystr.c standard arm64/arm64/cpufunc_asm.S standard arm64/arm64/db_disasm.c optional ddb arm64/arm64/db_interface.c optional ddb arm64/arm64/db_trace.c optional ddb arm64/arm64/debug_monitor.c optional kdb arm64/arm64/disassem.c optional ddb arm64/arm64/dump_machdep.c standard arm64/arm64/elf_machdep.c standard arm64/arm64/exception.S standard arm64/arm64/gic.c standard arm64/arm64/gic_acpi.c optional acpi arm64/arm64/gic_fdt.c optional fdt arm64/arm64/gic_v3.c standard arm64/arm64/gic_v3_fdt.c optional fdt arm64/arm64/gic_v3_its.c standard arm64/arm64/identcpu.c standard arm64/arm64/intr_machdep.c standard arm64/arm64/in_cksum.c optional inet | inet6 arm64/arm64/locore.S standard no-obj arm64/arm64/machdep.c standard arm64/arm64/mem.c standard arm64/arm64/minidump_machdep.c standard arm64/arm64/mp_machdep.c optional smp arm64/arm64/nexus.c standard arm64/arm64/ofw_machdep.c optional fdt arm64/arm64/pic_if.m standard arm64/arm64/pmap.c standard arm64/arm64/stack_machdep.c optional ddb | stack arm64/arm64/support.S standard arm64/arm64/swtch.S standard arm64/arm64/sys_machdep.c standard arm64/arm64/trap.c standard arm64/arm64/uio_machdep.c standard arm64/arm64/uma_machdep.c standard arm64/arm64/unwind.c optional ddb | kdtrace_hooks | stack arm64/arm64/vfp.c standard arm64/arm64/vm_machdep.c standard -arm64/cavium/thunder_pcie.c optional soc_cavm_thunderx pci arm64/cavium/thunder_pcie_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_pem.c optional soc_cavm_thunderx pci arm64/cavium/thunder_pcie_pem_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_common.c optional soc_cavm_thunderx pci arm64/cloudabi64/cloudabi64_sysvec.c optional compat_cloudabi64 crypto/blowfish/bf_enc.c optional crypto | ipsec crypto/des/des_enc.c optional crypto | ipsec | netsmb dev/acpica/acpi_if.m optional acpi dev/ahci/ahci_generic.c optional ahci fdt dev/hwpmc/hwpmc_arm64.c optional hwpmc dev/hwpmc/hwpmc_arm64_md.c optional hwpmc dev/mmc/host/dwmmc.c optional dwmmc dev/mmc/host/dwmmc_hisi.c optional dwmmc soc_hisi_hi6220 dev/ofw/ofw_cpu.c optional fdt dev/pci/pci_host_generic.c optional pci fdt dev/psci/psci.c optional psci dev/psci/psci_arm64.S optional psci dev/uart/uart_cpu_fdt.c optional uart fdt dev/uart/uart_dev_pl011.c optional uart pl011 dev/usb/controller/dwc_otg_hisi.c optional dwcotg soc_hisi_hi6220 dev/vnic/mrml_bridge.c optional vnic fdt dev/vnic/nic_main.c optional vnic pci dev/vnic/nicvf_main.c optional vnic pci pci_iov dev/vnic/nicvf_queues.c optional vnic pci pci_iov dev/vnic/thunder_bgx_fdt.c optional vnic fdt dev/vnic/thunder_bgx.c optional vnic pci dev/vnic/thunder_mdio_fdt.c optional vnic fdt dev/vnic/thunder_mdio.c optional vnic dev/vnic/lmac_if.m optional vnic kern/kern_clocksource.c standard libkern/bcmp.c standard libkern/ffs.c standard libkern/ffsl.c standard libkern/ffsll.c standard libkern/fls.c standard libkern/flsl.c standard libkern/flsll.c standard libkern/memmove.c standard libkern/memset.c standard cddl/contrib/opensolaris/common/atomic/aarch64/opensolaris_atomic.S optional zfs | dtrace compile-with "${CDDL_C}" cddl/dev/dtrace/aarch64/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/aarch64/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" Index: head/sys/dev/pci/pci_host_generic.c =================================================================== --- head/sys/dev/pci/pci_host_generic.c (revision 295961) +++ head/sys/dev/pci/pci_host_generic.c (revision 295962) @@ -1,658 +1,818 @@ /*- * Copyright (c) 2015 Ruslan Bukin * Copyright (c) 2014 The FreeBSD Foundation * All rights reserved. * * This software was developed by Semihalf under * the sponsorship of the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* Generic ECAM PCIe driver */ #include __FBSDID("$FreeBSD$"); +#include "opt_platform.h" + #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include +#include #include #include #include #include #include "pcib_if.h" /* Assembling ECAM Configuration Address */ #define PCIE_BUS_SHIFT 20 #define PCIE_SLOT_SHIFT 15 #define PCIE_FUNC_SHIFT 12 #define PCIE_BUS_MASK 0xFF #define PCIE_SLOT_MASK 0x1F #define PCIE_FUNC_MASK 0x07 #define PCIE_REG_MASK 0xFFF #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \ ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \ (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \ (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \ ((reg) & PCIE_REG_MASK)) -#define MAX_RANGES_TUPLES 5 -#define MIN_RANGES_TUPLES 2 - #define PCI_IO_WINDOW_OFFSET 0x1000 #define SPACE_CODE_SHIFT 24 #define SPACE_CODE_MASK 0x3 #define SPACE_CODE_IO_SPACE 0x1 #define PROPS_CELL_SIZE 1 #define PCI_ADDR_CELL_SIZE 2 -struct pcie_range { - uint64_t pci_base; - uint64_t phys_base; - uint64_t size; - uint64_t flags; -#define FLAG_IO (1 << 0) -#define FLAG_MEM (1 << 1) +/* OFW bus interface */ +struct generic_pcie_ofw_devinfo { + struct ofw_bus_devinfo di_dinfo; + struct resource_list di_rl; }; -struct generic_pcie_softc { - struct pcie_range ranges[MAX_RANGES_TUPLES]; - int nranges; - struct rman mem_rman; - struct rman io_rman; - struct resource *res; - struct resource *res1; - int ecam; - bus_space_tag_t bst; - bus_space_handle_t bsh; - device_t dev; - bus_space_handle_t ioh; - struct ofw_bus_iinfo pci_iinfo; -}; - /* Forward prototypes */ static int generic_pcie_probe(device_t dev); -static int generic_pcie_attach(device_t dev); static int parse_pci_mem_ranges(struct generic_pcie_softc *sc); static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, int bytes); static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, uint32_t val, int bytes); static int generic_pcie_maxslots(device_t dev); static int generic_pcie_read_ivar(device_t dev, device_t child, int index, uintptr_t *result); static int generic_pcie_write_ivar(device_t dev, device_t child, int index, uintptr_t value); static struct resource *generic_pcie_alloc_resource(device_t dev, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags); +static struct resource *generic_pcie_alloc_resource_ofw(device_t, device_t, + int, int *, rman_res_t, rman_res_t, rman_res_t, u_int); +static struct resource *generic_pcie_alloc_resource_pcie(device_t dev, + device_t child, int type, int *rid, rman_res_t start, rman_res_t end, + rman_res_t count, u_int flags); static int generic_pcie_release_resource(device_t dev, device_t child, int type, int rid, struct resource *res); +static int generic_pcie_release_resource_ofw(device_t, device_t, int, int, + struct resource *); +static int generic_pcie_release_resource_pcie(device_t, device_t, int, int, + struct resource *); +static int generic_pcie_ofw_bus_attach(device_t); +static const struct ofw_bus_devinfo *generic_pcie_ofw_get_devinfo(device_t, + device_t); +static __inline void +get_addr_size_cells(phandle_t node, pcell_t *addr_cells, pcell_t *size_cells) +{ + + *addr_cells = 2; + /* Find address cells if present */ + OF_getencprop(node, "#address-cells", addr_cells, sizeof(*addr_cells)); + + *size_cells = 2; + /* Find size cells if present */ + OF_getencprop(node, "#size-cells", size_cells, sizeof(*size_cells)); +} + static int generic_pcie_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic")) { device_set_desc(dev, "Generic PCI host controller"); - return (BUS_PROBE_DEFAULT); + return (BUS_PROBE_GENERIC); } return (ENXIO); } -static int -generic_pcie_attach(device_t dev) +int +pci_host_generic_attach(device_t dev) { struct generic_pcie_softc *sc; uint64_t phys_base; uint64_t pci_base; uint64_t size; int error; int tuple; int rid; sc = device_get_softc(dev); sc->dev = dev; + /* Retrieve 'ranges' property from FDT */ + if (bootverbose) + device_printf(dev, "parsing FDT for ECAM%d:\n", + sc->ecam); + if (parse_pci_mem_ranges(sc)) + return (ENXIO); + + /* Attach OFW bus */ + if (generic_pcie_ofw_bus_attach(dev) != 0) + return (ENXIO); + rid = 0; sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->res == NULL) { device_printf(dev, "could not map memory.\n"); return (ENXIO); } sc->bst = rman_get_bustag(sc->res); sc->bsh = rman_get_bushandle(sc->res); sc->mem_rman.rm_type = RMAN_ARRAY; sc->mem_rman.rm_descr = "PCIe Memory"; sc->io_rman.rm_type = RMAN_ARRAY; sc->io_rman.rm_descr = "PCIe IO window"; - /* Retrieve 'ranges' property from FDT */ - if (bootverbose) - device_printf(dev, "parsing FDT for ECAM%d:\n", - sc->ecam); - if (parse_pci_mem_ranges(sc)) - return (ENXIO); - /* Initialize rman and allocate memory regions */ error = rman_init(&sc->mem_rman); if (error) { device_printf(dev, "rman_init() failed. error = %d\n", error); return (error); } error = rman_init(&sc->io_rman); if (error) { device_printf(dev, "rman_init() failed. error = %d\n", error); return (error); } for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { phys_base = sc->ranges[tuple].phys_base; pci_base = sc->ranges[tuple].pci_base; size = sc->ranges[tuple].size; if (phys_base == 0 || size == 0) continue; /* empty range element */ if (sc->ranges[tuple].flags & FLAG_MEM) { error = rman_manage_region(&sc->mem_rman, phys_base, phys_base + size); } else if (sc->ranges[tuple].flags & FLAG_IO) { error = rman_manage_region(&sc->io_rman, pci_base + PCI_IO_WINDOW_OFFSET, pci_base + PCI_IO_WINDOW_OFFSET + size); } else continue; if (error) { device_printf(dev, "rman_manage_region() failed." "error = %d\n", error); rman_fini(&sc->mem_rman); return (error); } } ofw_bus_setup_iinfo(ofw_bus_get_node(dev), &sc->pci_iinfo, sizeof(cell_t)); - device_add_child(dev, "pci", -1); return (bus_generic_attach(dev)); } static int parse_pci_mem_ranges(struct generic_pcie_softc *sc) { pcell_t pci_addr_cells, parent_addr_cells; pcell_t attributes, size_cells; cell_t *base_ranges; int nbase_ranges; phandle_t node; int i, j, k; int tuple; node = ofw_bus_get_node(sc->dev); OF_getencprop(node, "#address-cells", &pci_addr_cells, sizeof(pci_addr_cells)); OF_getencprop(node, "#size-cells", &size_cells, sizeof(size_cells)); OF_getencprop(OF_parent(node), "#address-cells", &parent_addr_cells, sizeof(parent_addr_cells)); if (parent_addr_cells != 2 || pci_addr_cells != 3 || size_cells != 2) { device_printf(sc->dev, "Unexpected number of address or size cells in FDT\n"); return (ENXIO); } nbase_ranges = OF_getproplen(node, "ranges"); sc->nranges = nbase_ranges / sizeof(cell_t) / (parent_addr_cells + pci_addr_cells + size_cells); base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK); OF_getencprop(node, "ranges", base_ranges, nbase_ranges); for (i = 0, j = 0; i < sc->nranges; i++) { attributes = (base_ranges[j++] >> SPACE_CODE_SHIFT) & \ SPACE_CODE_MASK; if (attributes == SPACE_CODE_IO_SPACE) { sc->ranges[i].flags |= FLAG_IO; } else { sc->ranges[i].flags |= FLAG_MEM; } sc->ranges[i].pci_base = 0; for (k = 0; k < (pci_addr_cells - 1); k++) { sc->ranges[i].pci_base <<= 32; sc->ranges[i].pci_base |= base_ranges[j++]; } sc->ranges[i].phys_base = 0; for (k = 0; k < parent_addr_cells; k++) { sc->ranges[i].phys_base <<= 32; sc->ranges[i].phys_base |= base_ranges[j++]; } sc->ranges[i].size = 0; for (k = 0; k < size_cells; k++) { sc->ranges[i].size <<= 32; sc->ranges[i].size |= base_ranges[j++]; } } for (; i < MAX_RANGES_TUPLES; i++) { /* zero-fill remaining tuples to mark empty elements in array */ sc->ranges[i].pci_base = 0; sc->ranges[i].phys_base = 0; sc->ranges[i].size = 0; } if (bootverbose) { for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { device_printf(sc->dev, "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx\n", sc->ranges[tuple].pci_base, sc->ranges[tuple].phys_base, sc->ranges[tuple].size); } } free(base_ranges, M_DEVBUF); return (0); } static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, int bytes) { struct generic_pcie_softc *sc; bus_space_handle_t h; bus_space_tag_t t; uint64_t offset; uint32_t data; - if (bus > 255 || slot > 31 || func > 7 || reg > 4095) + if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || + (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) return (~0U); sc = device_get_softc(dev); offset = PCIE_ADDR_OFFSET(bus, slot, func, reg); t = sc->bst; h = sc->bsh; switch (bytes) { case 1: data = bus_space_read_1(t, h, offset); break; case 2: data = le16toh(bus_space_read_2(t, h, offset)); break; case 4: data = le32toh(bus_space_read_4(t, h, offset)); break; default: return (~0U); } return (data); } static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, uint32_t val, int bytes) { struct generic_pcie_softc *sc; bus_space_handle_t h; bus_space_tag_t t; uint64_t offset; - if (bus > 255 || slot > 31 || func > 7 || reg > 4095) + if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || + (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) return; sc = device_get_softc(dev); offset = PCIE_ADDR_OFFSET(bus, slot, func, reg); t = sc->bst; h = sc->bsh; switch (bytes) { case 1: bus_space_write_1(t, h, offset, val); break; case 2: bus_space_write_2(t, h, offset, htole16(val)); break; case 4: bus_space_write_4(t, h, offset, htole32(val)); break; default: return; } } static int generic_pcie_maxslots(device_t dev) { return (31); /* max slots per bus acc. to standard */ } static int generic_pcie_route_interrupt(device_t bus, device_t dev, int pin) { struct generic_pcie_softc *sc; struct ofw_pci_register reg; uint32_t pintr, mintr[2]; phandle_t iparent; int intrcells; sc = device_get_softc(bus); pintr = pin; bzero(®, sizeof(reg)); reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); intrcells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr), mintr, sizeof(mintr), &iparent); if (intrcells) { pintr = ofw_bus_map_intr(dev, iparent, intrcells, mintr); return (pintr); } device_printf(bus, "could not route pin %d for device %d.%d\n", pin, pci_get_slot(dev), pci_get_function(dev)); return (PCI_INVALID_IRQ); } static int generic_pcie_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) { struct generic_pcie_softc *sc; int secondary_bus; sc = device_get_softc(dev); if (index == PCIB_IVAR_BUS) { /* this pcib adds only pci bus 0 as child */ secondary_bus = 0; *result = secondary_bus; return (0); } if (index == PCIB_IVAR_DOMAIN) { *result = sc->ecam; return (0); } - device_printf(dev, "ERROR: Unknown index.\n"); + if (bootverbose) + device_printf(dev, "ERROR: Unknown index %d.\n", index); return (ENOENT); } static int generic_pcie_write_ivar(device_t dev, device_t child, int index, uintptr_t value) { return (ENOENT); } static struct rman * generic_pcie_rman(struct generic_pcie_softc *sc, int type) { switch (type) { case SYS_RES_IOPORT: return (&sc->io_rman); case SYS_RES_MEMORY: return (&sc->mem_rman); default: break; } return (NULL); } static int -generic_pcie_release_resource(device_t dev, device_t child, int type, +generic_pcie_release_resource_pcie(device_t dev, device_t child, int type, int rid, struct resource *res) { struct generic_pcie_softc *sc; struct rman *rm; sc = device_get_softc(dev); rm = generic_pcie_rman(sc, type); if (rm != NULL) { KASSERT(rman_is_region_manager(res, rm), ("rman mismatch")); rman_release_resource(res); } return (bus_generic_release_resource(dev, child, type, rid, res)); } +static int +generic_pcie_release_resource(device_t dev, device_t child, int type, + int rid, struct resource *res) +{ + + /* For PCIe devices that do not have FDT nodes, use PCIB method */ + if ((int)ofw_bus_get_node(child) <= 0) { + return (generic_pcie_release_resource_pcie(dev, + child, type, rid, res)); + } + + /* For other devices use OFW method */ + return (generic_pcie_release_resource_ofw(dev, + child, type, rid, res)); +} + static struct resource * generic_pcie_alloc_resource(device_t dev, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) { + + /* For PCIe devices that do not have FDT nodes, use PCIB method */ + if ((int)ofw_bus_get_node(child) <= 0) + return (generic_pcie_alloc_resource_pcie(dev, child, type, rid, + start, end, count, flags)); + + /* For other devices use OFW method */ + return (generic_pcie_alloc_resource_ofw(dev, child, type, rid, + start, end, count, flags)); +} + +static struct resource * +generic_pcie_alloc_resource_pcie(device_t dev, device_t child, int type, int *rid, + rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) +{ struct generic_pcie_softc *sc; struct resource *res; struct rman *rm; sc = device_get_softc(dev); rm = generic_pcie_rman(sc, type); if (rm == NULL) return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, type, rid, start, end, count, flags)); if (bootverbose) { device_printf(dev, "rman_reserve_resource: start=%#lx, end=%#lx, count=%#lx\n", start, end, count); } res = rman_reserve_resource(rm, start, end, count, flags, child); if (res == NULL) goto fail; rman_set_rid(res, *rid); if (flags & RF_ACTIVE) if (bus_activate_resource(child, type, *rid, res)) { rman_release_resource(res); goto fail; } return (res); fail: - if (bootverbose) { - device_printf(dev, "%s FAIL: type=%d, rid=%d, " - "start=%016lx, end=%016lx, count=%016lx, flags=%x\n", - __func__, type, *rid, start, end, count, flags); - } + device_printf(dev, "%s FAIL: type=%d, rid=%d, " + "start=%016lx, end=%016lx, count=%016lx, flags=%x\n", + __func__, type, *rid, start, end, count, flags); return (NULL); } static int generic_pcie_adjust_resource(device_t dev, device_t child, int type, struct resource *res, rman_res_t start, rman_res_t end) { struct generic_pcie_softc *sc; struct rman *rm; sc = device_get_softc(dev); rm = generic_pcie_rman(sc, type); if (rm != NULL) return (rman_adjust_resource(res, start, end)); return (bus_generic_adjust_resource(dev, child, type, res, start, end)); } static int generic_pcie_activate_resource(device_t dev, device_t child, int type, int rid, struct resource *r) { struct generic_pcie_softc *sc; uint64_t phys_base; uint64_t pci_base; uint64_t size; int found; int res; int i; sc = device_get_softc(dev); if ((res = rman_activate_resource(r)) != 0) return (res); switch(type) { case SYS_RES_IOPORT: found = 0; for (i = 0; i < MAX_RANGES_TUPLES; i++) { pci_base = sc->ranges[i].pci_base; phys_base = sc->ranges[i].phys_base; size = sc->ranges[i].size; if ((rid > pci_base) && (rid < (pci_base + size))) { found = 1; break; } } if (found) { rman_set_start(r, rman_get_start(r) + phys_base); BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child, type, rid, r); } else { device_printf(dev, "Failed to activate IOPORT resource\n"); res = 0; } break; case SYS_RES_MEMORY: BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child, type, rid, r); break; default: break; } return (res); } static int generic_pcie_deactivate_resource(device_t dev, device_t child, int type, int rid, struct resource *r) { struct generic_pcie_softc *sc; vm_offset_t vaddr; int res; sc = device_get_softc(dev); if ((res = rman_deactivate_resource(r)) != 0) return (res); switch(type) { case SYS_RES_IOPORT: case SYS_RES_MEMORY: vaddr = (vm_offset_t)rman_get_virtual(r); pmap_unmapdev(vaddr, rman_get_size(r)); break; default: break; } return (res); } static device_method_t generic_pcie_methods[] = { DEVMETHOD(device_probe, generic_pcie_probe), - DEVMETHOD(device_attach, generic_pcie_attach), + DEVMETHOD(device_attach, pci_host_generic_attach), DEVMETHOD(bus_read_ivar, generic_pcie_read_ivar), DEVMETHOD(bus_write_ivar, generic_pcie_write_ivar), DEVMETHOD(bus_alloc_resource, generic_pcie_alloc_resource), DEVMETHOD(bus_adjust_resource, generic_pcie_adjust_resource), DEVMETHOD(bus_release_resource, generic_pcie_release_resource), DEVMETHOD(bus_activate_resource, generic_pcie_activate_resource), DEVMETHOD(bus_deactivate_resource, generic_pcie_deactivate_resource), DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), /* pcib interface */ DEVMETHOD(pcib_maxslots, generic_pcie_maxslots), DEVMETHOD(pcib_route_interrupt, generic_pcie_route_interrupt), DEVMETHOD(pcib_read_config, generic_pcie_read_config), DEVMETHOD(pcib_write_config, generic_pcie_write_config), #if defined(__aarch64__) DEVMETHOD(pcib_alloc_msi, arm_alloc_msi), DEVMETHOD(pcib_release_msi, arm_release_msi), DEVMETHOD(pcib_alloc_msix, arm_alloc_msix), DEVMETHOD(pcib_release_msix, arm_release_msix), DEVMETHOD(pcib_map_msi, arm_map_msi), #endif + /* ofw_bus interface */ + DEVMETHOD(ofw_bus_get_devinfo, generic_pcie_ofw_get_devinfo), + DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), + DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), + DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), + DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), + DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), + DEVMETHOD_END }; -static driver_t generic_pcie_driver = { - "pcib", - generic_pcie_methods, - sizeof(struct generic_pcie_softc), -}; +static const struct ofw_bus_devinfo * +generic_pcie_ofw_get_devinfo(device_t bus __unused, device_t child) +{ + struct generic_pcie_ofw_devinfo *di; -static devclass_t generic_pcie_devclass; + di = device_get_ivars(child); + return (&di->di_dinfo); +} +static struct resource * +generic_pcie_alloc_resource_ofw(device_t bus, device_t child, int type, int *rid, + rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) +{ + struct generic_pcie_softc *sc; + struct generic_pcie_ofw_devinfo *di; + struct resource_list_entry *rle; + int i; + + sc = device_get_softc(bus); + + if ((start == 0UL) && (end == ~0UL)) { + if ((di = device_get_ivars(child)) == NULL) + return (NULL); + if (type == SYS_RES_IOPORT) + type = SYS_RES_MEMORY; + + /* Find defaults for this rid */ + rle = resource_list_find(&di->di_rl, type, *rid); + if (rle == NULL) + return (NULL); + + start = rle->start; + end = rle->end; + count = rle->count; + } + + if (type == SYS_RES_MEMORY) { + /* Remap through ranges property */ + for (i = 0; i < MAX_RANGES_TUPLES; i++) { + if (start >= sc->ranges[i].phys_base && end < + sc->ranges[i].pci_base + sc->ranges[i].size) { + start -= sc->ranges[i].phys_base; + start += sc->ranges[i].pci_base; + end -= sc->ranges[i].phys_base; + end += sc->ranges[i].pci_base; + break; + } + } + + if (i == MAX_RANGES_TUPLES) { + device_printf(bus, "Could not map resource " + "%#lx-%#lx\n", start, end); + return (NULL); + } + } + + return (bus_generic_alloc_resource(bus, child, type, rid, start, end, + count, flags)); +} + +static int +generic_pcie_release_resource_ofw(device_t bus, device_t child, int type, int rid, + struct resource *res) +{ + + return (bus_generic_release_resource(bus, child, type, rid, res)); +} + +/* Helper functions */ + +static int +generic_pcie_ofw_bus_attach(device_t dev) +{ + struct generic_pcie_ofw_devinfo *di; + device_t child; + phandle_t parent, node; + pcell_t addr_cells, size_cells; + + parent = ofw_bus_get_node(dev); + if (parent > 0) { + get_addr_size_cells(parent, &addr_cells, &size_cells); + /* Iterate through all bus subordinates */ + for (node = OF_child(parent); node > 0; node = OF_peer(node)) { + + /* Allocate and populate devinfo. */ + di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO); + if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) { + free(di, M_DEVBUF); + continue; + } + + /* Initialize and populate resource list. */ + resource_list_init(&di->di_rl); + ofw_bus_reg_to_rl(dev, node, addr_cells, size_cells, + &di->di_rl); + ofw_bus_intr_to_rl(dev, node, &di->di_rl, NULL); + + /* Add newbus device for this FDT node */ + child = device_add_child(dev, NULL, -1); + if (child == NULL) { + resource_list_free(&di->di_rl); + ofw_bus_gen_destroy_devinfo(&di->di_dinfo); + free(di, M_DEVBUF); + continue; + } + + device_set_ivars(child, di); + } + } + + return (0); +} + +DEFINE_CLASS_0(pcib, generic_pcie_driver, + generic_pcie_methods, sizeof(struct generic_pcie_softc)); + +devclass_t generic_pcie_devclass; + DRIVER_MODULE(pcib, simplebus, generic_pcie_driver, -generic_pcie_devclass, 0, 0); + generic_pcie_devclass, 0, 0); DRIVER_MODULE(pcib, ofwbus, generic_pcie_driver, -generic_pcie_devclass, 0, 0); + generic_pcie_devclass, 0, 0); + Index: head/sys/dev/pci/pci_host_generic.h =================================================================== --- head/sys/dev/pci/pci_host_generic.h (nonexistent) +++ head/sys/dev/pci/pci_host_generic.h (revision 295962) @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2015 Ruslan Bukin + * Copyright (c) 2015 The FreeBSD Foundation + * All rights reserved. + * + * This software was developed by Semihalf. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + * $FreeBSD$ + * + */ + +#ifndef __PCI_HOST_GENERIC_H_ +#define __PCI_HOST_GENERIC_H_ + +#define MAX_RANGES_TUPLES 16 +#define MIN_RANGES_TUPLES 2 + +struct pcie_range { + uint64_t pci_base; + uint64_t phys_base; + uint64_t size; + uint64_t flags; +#define FLAG_IO (1 << 0) +#define FLAG_MEM (1 << 1) +}; + +struct generic_pcie_softc { + struct pcie_range ranges[MAX_RANGES_TUPLES]; + int nranges; + struct rman mem_rman; + struct rman io_rman; + struct resource *res; + struct resource *res1; + int ecam; + bus_space_tag_t bst; + bus_space_handle_t bsh; + device_t dev; + bus_space_handle_t ioh; +#ifdef FDT + struct ofw_bus_iinfo pci_iinfo; +#endif +}; + +extern devclass_t generic_pcie_devclass; +DECLARE_CLASS(generic_pcie_driver); + +int pci_host_generic_attach(device_t); + +#endif /* __PCI_HOST_GENERIC_H_ */ Property changes on: head/sys/dev/pci/pci_host_generic.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property