Index: head/sys/arm/allwinner/a10_dmac.c =================================================================== --- head/sys/arm/allwinner/a10_dmac.c (nonexistent) +++ head/sys/arm/allwinner/a10_dmac.c (revision 295635) @@ -0,0 +1,453 @@ +/*- + * Copyright (c) 2014-2016 Jared D. McNeill + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +/* + * Allwinner A10/A20 DMA controller + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include + +#include "sunxi_dma_if.h" + +#define NDMA_CHANNELS 8 +#define DDMA_CHANNELS 8 + +enum a10dmac_type { + CH_NDMA, + CH_DDMA +}; + +struct a10dmac_softc; + +struct a10dmac_channel { + struct a10dmac_softc * ch_sc; + uint8_t ch_index; + enum a10dmac_type ch_type; + void (*ch_callback)(void *); + void * ch_callbackarg; + uint32_t ch_regoff; +}; + +struct a10dmac_softc { + struct resource * sc_res[2]; + struct mtx sc_mtx; + void * sc_ih; + + struct a10dmac_channel sc_ndma_channels[NDMA_CHANNELS]; + struct a10dmac_channel sc_ddma_channels[DDMA_CHANNELS]; +}; + +static struct resource_spec a10dmac_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { SYS_RES_IRQ, 0, RF_ACTIVE }, + { -1, 0 } +}; + +#define DMA_READ(sc, reg) bus_read_4((sc)->sc_res[0], (reg)) +#define DMA_WRITE(sc, reg, val) bus_write_4((sc)->sc_res[0], (reg), (val)) +#define DMACH_READ(ch, reg) \ + DMA_READ((ch)->ch_sc, (reg) + (ch)->ch_regoff) +#define DMACH_WRITE(ch, reg, val) \ + DMA_WRITE((ch)->ch_sc, (reg) + (ch)->ch_regoff, (val)) + +static void a10dmac_intr(void *); + +static int +a10dmac_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-dma")) + return (ENXIO); + + device_set_desc(dev, "Allwinner DMA controller"); + return (BUS_PROBE_DEFAULT); +} + +static int +a10dmac_attach(device_t dev) +{ + struct a10dmac_softc *sc; + unsigned int index; + int error; + + sc = device_get_softc(dev); + + if (bus_alloc_resources(dev, a10dmac_spec, sc->sc_res)) { + device_printf(dev, "cannot allocate resources for device\n"); + return (ENXIO); + } + + mtx_init(&sc->sc_mtx, "a10 dmac", NULL, MTX_SPIN); + + /* Activate DMA controller clock */ + a10_clk_dmac_activate(); + + /* Disable all interrupts and clear pending status */ + DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, 0); + DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, ~0); + + /* Initialize channels */ + for (index = 0; index < NDMA_CHANNELS; index++) { + sc->sc_ndma_channels[index].ch_sc = sc; + sc->sc_ndma_channels[index].ch_index = index; + sc->sc_ndma_channels[index].ch_type = CH_NDMA; + sc->sc_ndma_channels[index].ch_callback = NULL; + sc->sc_ndma_channels[index].ch_callbackarg = NULL; + sc->sc_ndma_channels[index].ch_regoff = AWIN_NDMA_REG(index); + DMACH_WRITE(&sc->sc_ndma_channels[index], AWIN_NDMA_CTL_REG, 0); + } + for (index = 0; index < DDMA_CHANNELS; index++) { + sc->sc_ddma_channels[index].ch_sc = sc; + sc->sc_ddma_channels[index].ch_index = index; + sc->sc_ddma_channels[index].ch_type = CH_DDMA; + sc->sc_ddma_channels[index].ch_callback = NULL; + sc->sc_ddma_channels[index].ch_callbackarg = NULL; + sc->sc_ddma_channels[index].ch_regoff = AWIN_DDMA_REG(index); + DMACH_WRITE(&sc->sc_ddma_channels[index], AWIN_DDMA_CTL_REG, 0); + } + + error = bus_setup_intr(dev, sc->sc_res[1], INTR_MPSAFE | INTR_TYPE_MISC, + NULL, a10dmac_intr, sc, &sc->sc_ih); + if (error != 0) { + device_printf(dev, "could not setup interrupt handler\n"); + bus_release_resources(dev, a10dmac_spec, sc->sc_res); + mtx_destroy(&sc->sc_mtx); + return (ENXIO); + } + + return (0); +} + +static void +a10dmac_intr(void *priv) +{ + struct a10dmac_softc *sc = priv; + uint32_t sta, bit, mask; + uint8_t index; + + sta = DMA_READ(sc, AWIN_DMA_IRQ_PEND_STA_REG); + DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, sta); + + while ((bit = ffs(sta & AWIN_DMA_IRQ_END_MASK)) != 0) { + mask = (1U << (bit - 1)); + sta &= ~mask; + /* + * Map status bit to channel number. The status register is + * encoded with two bits of status per channel (lowest bit + * is half transfer pending, highest bit is end transfer + * pending). The 8 normal DMA channel status are in the lower + * 16 bits and the 8 dedicated DMA channel status are in + * the upper 16 bits. The output is a channel number from 0-7. + */ + index = ((bit - 1) / 2) & 7; + if (mask & AWIN_DMA_IRQ_NDMA) { + if (sc->sc_ndma_channels[index].ch_callback == NULL) + continue; + sc->sc_ndma_channels[index].ch_callback( + sc->sc_ndma_channels[index].ch_callbackarg); + } else { + if (sc->sc_ddma_channels[index].ch_callback == NULL) + continue; + sc->sc_ddma_channels[index].ch_callback( + sc->sc_ddma_channels[index].ch_callbackarg); + } + } +} + +static uint32_t +a10dmac_read_ctl(struct a10dmac_channel *ch) +{ + if (ch->ch_type == CH_NDMA) { + return (DMACH_READ(ch, AWIN_NDMA_CTL_REG)); + } else { + return (DMACH_READ(ch, AWIN_DDMA_CTL_REG)); + } +} + +static void +a10dmac_write_ctl(struct a10dmac_channel *ch, uint32_t val) +{ + if (ch->ch_type == CH_NDMA) { + DMACH_WRITE(ch, AWIN_NDMA_CTL_REG, val); + } else { + DMACH_WRITE(ch, AWIN_DDMA_CTL_REG, val); + } +} + +static int +a10dmac_set_config(device_t dev, void *priv, const struct sunxi_dma_config *cfg) +{ + struct a10dmac_channel *ch = priv; + uint32_t val; + unsigned int dst_dw, dst_bl, dst_bs, dst_wc; + unsigned int src_dw, src_bl, src_bs, src_wc; + + switch (cfg->dst_width) { + case 8: + dst_dw = AWIN_DMA_CTL_DATA_WIDTH_8; + break; + case 16: + dst_dw = AWIN_DMA_CTL_DATA_WIDTH_16; + break; + case 32: + dst_dw = AWIN_DMA_CTL_DATA_WIDTH_32; + break; + default: + return (EINVAL); + } + switch (cfg->dst_burst_len) { + case 1: + dst_bl = AWIN_DMA_CTL_BURST_LEN_1; + break; + case 4: + dst_bl = AWIN_DMA_CTL_BURST_LEN_4; + break; + case 8: + dst_bl = AWIN_DMA_CTL_BURST_LEN_8; + break; + default: + return (EINVAL); + } + switch (cfg->src_width) { + case 8: + src_dw = AWIN_DMA_CTL_DATA_WIDTH_8; + break; + case 16: + src_dw = AWIN_DMA_CTL_DATA_WIDTH_16; + break; + case 32: + src_dw = AWIN_DMA_CTL_DATA_WIDTH_32; + break; + default: + return (EINVAL); + } + switch (cfg->src_burst_len) { + case 1: + src_bl = AWIN_DMA_CTL_BURST_LEN_1; + break; + case 4: + src_bl = AWIN_DMA_CTL_BURST_LEN_4; + break; + case 8: + src_bl = AWIN_DMA_CTL_BURST_LEN_8; + break; + default: + return (EINVAL); + } + + val = (dst_dw << AWIN_DMA_CTL_DST_DATA_WIDTH_SHIFT) | + (dst_bl << AWIN_DMA_CTL_DST_BURST_LEN_SHIFT) | + (cfg->dst_drqtype << AWIN_DMA_CTL_DST_DRQ_TYPE_SHIFT) | + (src_dw << AWIN_DMA_CTL_SRC_DATA_WIDTH_SHIFT) | + (src_bl << AWIN_DMA_CTL_SRC_BURST_LEN_SHIFT) | + (cfg->src_drqtype << AWIN_DMA_CTL_SRC_DRQ_TYPE_SHIFT); + if (cfg->dst_noincr) { + val |= AWIN_NDMA_CTL_DST_ADDR_NOINCR; + } + if (cfg->src_noincr) { + val |= AWIN_NDMA_CTL_SRC_ADDR_NOINCR; + } + + if (ch->ch_type == CH_NDMA) { + DMACH_WRITE(ch, AWIN_NDMA_CTL_REG, val); + } else { + DMACH_WRITE(ch, AWIN_DDMA_CTL_REG, val); + + dst_bs = cfg->dst_blksize - 1; + dst_wc = cfg->dst_wait_cyc - 1; + src_bs = cfg->src_blksize - 1; + src_wc = cfg->src_wait_cyc - 1; + + DMACH_WRITE(ch, AWIN_DDMA_PARA_REG, + (dst_bs << AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_SHIFT) | + (dst_wc << AWIN_DDMA_PARA_DST_WAIT_CYC_SHIFT) | + (src_bs << AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_SHIFT) | + (src_wc << AWIN_DDMA_PARA_SRC_WAIT_CYC_SHIFT)); + } + + return (0); +} + +static void * +a10dmac_alloc(device_t dev, bool dedicated, void (*cb)(void *), void *cbarg) +{ + struct a10dmac_softc *sc = device_get_softc(dev); + struct a10dmac_channel *ch_list; + struct a10dmac_channel *ch = NULL; + uint32_t irqen; + uint8_t ch_count, index; + + if (dedicated) { + ch_list = sc->sc_ddma_channels; + ch_count = DDMA_CHANNELS; + } else { + ch_list = sc->sc_ndma_channels; + ch_count = NDMA_CHANNELS; + } + + mtx_lock_spin(&sc->sc_mtx); + for (index = 0; index < ch_count; index++) { + if (ch_list[index].ch_callback == NULL) { + ch = &ch_list[index]; + ch->ch_callback = cb; + ch->ch_callbackarg = cbarg; + + irqen = DMA_READ(sc, AWIN_DMA_IRQ_EN_REG); + if (ch->ch_type == CH_NDMA) + irqen |= AWIN_DMA_IRQ_NDMA_END(index); + else + irqen |= AWIN_DMA_IRQ_DDMA_END(index); + DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, irqen); + + break; + } + } + mtx_unlock_spin(&sc->sc_mtx); + + return (ch); +} + +static void +a10dmac_free(device_t dev, void *priv) +{ + struct a10dmac_channel *ch = priv; + struct a10dmac_softc *sc = ch->ch_sc; + uint32_t irqen, sta, cfg; + + mtx_lock_spin(&sc->sc_mtx); + + irqen = DMA_READ(sc, AWIN_DMA_IRQ_EN_REG); + cfg = a10dmac_read_ctl(ch); + if (ch->ch_type == CH_NDMA) { + sta = AWIN_DMA_IRQ_NDMA_END(ch->ch_index); + cfg &= ~AWIN_NDMA_CTL_DMA_LOADING; + } else { + sta = AWIN_DMA_IRQ_DDMA_END(ch->ch_index); + cfg &= ~AWIN_DDMA_CTL_DMA_LOADING; + } + irqen &= ~sta; + a10dmac_write_ctl(ch, cfg); + DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, irqen); + DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, sta); + + ch->ch_callback = NULL; + ch->ch_callbackarg = NULL; + + mtx_unlock_spin(&sc->sc_mtx); +} + +static int +a10dmac_transfer(device_t dev, void *priv, bus_addr_t src, bus_addr_t dst, + size_t nbytes) +{ + struct a10dmac_channel *ch = priv; + uint32_t cfg; + + cfg = a10dmac_read_ctl(ch); + if (ch->ch_type == CH_NDMA) { + if (cfg & AWIN_NDMA_CTL_DMA_LOADING) + return (EBUSY); + + DMACH_WRITE(ch, AWIN_NDMA_SRC_ADDR_REG, src); + DMACH_WRITE(ch, AWIN_NDMA_DEST_ADDR_REG, dst); + DMACH_WRITE(ch, AWIN_NDMA_BC_REG, nbytes); + + cfg |= AWIN_NDMA_CTL_DMA_LOADING; + a10dmac_write_ctl(ch, cfg); + } else { + if (cfg & AWIN_DDMA_CTL_DMA_LOADING) + return (EBUSY); + + DMACH_WRITE(ch, AWIN_DDMA_SRC_START_ADDR_REG, src); + DMACH_WRITE(ch, AWIN_DDMA_DEST_START_ADDR_REG, dst); + DMACH_WRITE(ch, AWIN_DDMA_BC_REG, nbytes); + + cfg |= AWIN_DDMA_CTL_DMA_LOADING; + a10dmac_write_ctl(ch, cfg); + } + + return (0); +} + +static void +a10dmac_halt(device_t dev, void *priv) +{ + struct a10dmac_channel *ch = priv; + uint32_t cfg; + + cfg = a10dmac_read_ctl(ch); + if (ch->ch_type == CH_NDMA) { + cfg &= ~AWIN_NDMA_CTL_DMA_LOADING; + } else { + cfg &= ~AWIN_DDMA_CTL_DMA_LOADING; + } + a10dmac_write_ctl(ch, cfg); +} + +static device_method_t a10dmac_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, a10dmac_probe), + DEVMETHOD(device_attach, a10dmac_attach), + + /* sunxi DMA interface */ + DEVMETHOD(sunxi_dma_alloc, a10dmac_alloc), + DEVMETHOD(sunxi_dma_free, a10dmac_free), + DEVMETHOD(sunxi_dma_set_config, a10dmac_set_config), + DEVMETHOD(sunxi_dma_transfer, a10dmac_transfer), + DEVMETHOD(sunxi_dma_halt, a10dmac_halt), + + DEVMETHOD_END +}; + +static driver_t a10dmac_driver = { + "a10dmac", + a10dmac_methods, + sizeof(struct a10dmac_softc) +}; + +static devclass_t a10dmac_devclass; + +DRIVER_MODULE(a10dmac, simplebus, a10dmac_driver, a10dmac_devclass, 0, 0); Property changes on: head/sys/arm/allwinner/a10_dmac.c ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/arm/allwinner/a10_dmac.h =================================================================== --- head/sys/arm/allwinner/a10_dmac.h (nonexistent) +++ head/sys/arm/allwinner/a10_dmac.h (revision 295635) @@ -0,0 +1,158 @@ +/*- + * Copyright (c) 2014-2016 Jared D. McNeill + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _A10_DMAC_H_ +#define _A10_DMAC_H_ + +#define AWIN_DMA_IRQ_EN_REG 0x0000 +#define AWIN_DMA_IRQ_PEND_STA_REG 0x0004 +#define AWIN_NDMA_AUTO_GATE_REG 0x0008 +#define AWIN_NDMA_REG(n) (0x100+0x20*(n)) +#define AWIN_NDMA_CTL_REG 0x0000 +#define AWIN_NDMA_SRC_ADDR_REG 0x0004 +#define AWIN_NDMA_DEST_ADDR_REG 0x0008 +#define AWIN_NDMA_BC_REG 0x000c +#define AWIN_DDMA_REG(n) (0x300+0x20*(n)) +#define AWIN_DDMA_CTL_REG 0x0000 +#define AWIN_DDMA_SRC_START_ADDR_REG 0x0004 +#define AWIN_DDMA_DEST_START_ADDR_REG 0x0008 +#define AWIN_DDMA_BC_REG 0x000c +#define AWIN_DDMA_PARA_REG 0x0018 +#define AWIN_DMA_IRQ_END_MASK 0xaaaaaaaa +#define AWIN_DMA_IRQ_HF_MASK 0x55555555 +#define AWIN_DMA_IRQ_DDMA 0xffff0000 +#define AWIN_DMA_IRQ_DDMA_END(n) (1U << (17+2*(n))) +#define AWIN_DMA_IRQ_DDMA_HF(n) (1U << (16+2*(n))) +#define AWIN_DMA_IRQ_NDMA 0x0000ffff +#define AWIN_DMA_IRQ_NDMA_END(n) (1U << (1+2*(n))) +#define AWIN_DMA_IRQ_NDMA_HF(n) (1U << (0+2*(n))) +#define AWIN_NDMA_AUTO_GATING_DIS (1U << 16) +#define AWIN_DMA_CTL_DST_DATA_WIDTH_SHIFT 25 +#define AWIN_DMA_CTL_DST_DATA_WIDTH_MASK (3U << AWIN_DMA_CTL_DST_DATA_WIDTH_SHIFT) +#define AWIN_DMA_CTL_DATA_WIDTH_8 0 +#define AWIN_DMA_CTL_DATA_WIDTH_16 1 +#define AWIN_DMA_CTL_DATA_WIDTH_32 2 +#define AWIN_DMA_CTL_DST_BURST_LEN_SHIFT 23 +#define AWIN_DMA_CTL_DST_BURST_LEN_MASK (3 << AWIN_DMA_CTL_DST_BURST_LEN_SHIFT) +#define AWIN_DMA_CTL_BURST_LEN_1 0 +#define AWIN_DMA_CTL_BURST_LEN_4 1 +#define AWIN_DMA_CTL_BURST_LEN_8 2 +#define AWIN_DMA_CTL_DST_DRQ_TYPE_SHIFT 16 +#define AWIN_DMA_CTL_DST_DRQ_TYPE_MASK (0x1f << AWIN_DMA_CTL_DST_DRQ_TYPE_SHIFT) +#define AWIN_DMA_CTL_BC_REMAINING (1U << 15) +#define AWIN_DMA_CTL_SRC_DATA_WIDTH_SHIFT 9 +#define AWIN_DMA_CTL_SRC_DATA_WIDTH_MASK (3U << AWIN_DMA_CTL_SRC_DATA_WIDTH_SHIFT) +#define AWIN_DMA_CTL_SRC_BURST_LEN_SHIFT 7 +#define AWIN_DMA_CTL_SRC_BURST_LEN_MASK (3U << AWIN_DMA_CTL_SRC_BURST_LEN_SHIFT) +#define AWIN_DMA_CTL_SRC_DRQ_TYPE_SHIFT 0 +#define AWIN_DMA_CTL_SRC_DRQ_TYPE_MASK (0x1f << AWIN_DMA_CTL_SRC_DRQ_TYPE_SHIFT) +#define AWIN_NDMA_CTL_DMA_LOADING (1U << 31) +#define AWIN_NDMA_CTL_DMA_CONTIN_MODE (1U << 30) +#define AWIN_NDMA_CTL_WAIT_STATE_LOG2_SHIFT 27 +#define AWIN_NDMA_CTL_WAIT_STATE_LOG2_MASK (7U << AWIN_NDMA_CTL_WAIT_STATE_LOG2_SHIFT) +#define AWIN_NDMA_CTL_DST_NON_SECURE (1U << 22) +#define AWIN_NDMA_CTL_DST_ADDR_NOINCR (1U << 21) +#define AWIN_NDMA_CTL_DRQ_IRO 0 +#define AWIN_NDMA_CTL_DRQ_IR1 1 +#define AWIN_NDMA_CTL_DRQ_SPDIF 2 +#define AWIN_NDMA_CTL_DRQ_IISO 3 +#define AWIN_NDMA_CTL_DRQ_IIS1 4 +#define AWIN_NDMA_CTL_DRQ_AC97 5 +#define AWIN_NDMA_CTL_DRQ_IIS2 6 +#define AWIN_NDMA_CTL_DRQ_UARTO 8 +#define AWIN_NDMA_CTL_DRQ_UART1 9 +#define AWIN_NDMA_CTL_DRQ_UART2 10 +#define AWIN_NDMA_CTL_DRQ_UART3 11 +#define AWIN_NDMA_CTL_DRQ_UART4 12 +#define AWIN_NDMA_CTL_DRQ_UART5 13 +#define AWIN_NDMA_CTL_DRQ_UART6 14 +#define AWIN_NDMA_CTL_DRQ_UART7 15 +#define AWIN_NDMA_CTL_DRQ_DDC 16 +#define AWIN_NDMA_CTL_DRQ_USB_EP1 17 +#define AWIN_NDMA_CTL_DRQ_CODEC 19 +#define AWIN_NDMA_CTL_DRQ_SRAM 21 +#define AWIN_NDMA_CTL_DRQ_SDRAM 22 +#define AWIN_NDMA_CTL_DRQ_TP_AD 23 +#define AWIN_NDMA_CTL_DRQ_SPI0 24 +#define AWIN_NDMA_CTL_DRQ_SPI1 25 +#define AWIN_NDMA_CTL_DRQ_SPI2 26 +#define AWIN_NDMA_CTL_DRQ_SPI3 27 +#define AWIN_NDMA_CTL_DRQ_USB_EP2 28 +#define AWIN_NDMA_CTL_DRQ_USB_EP3 29 +#define AWIN_NDMA_CTL_DRQ_USB_EP4 30 +#define AWIN_NDMA_CTL_DRQ_USB_EP5 31 +#define AWIN_NDMA_CTL_SRC_NON_SECURE (1U << 6) +#define AWIN_NDMA_CTL_SRC_ADDR_NOINCR (1U << 5) +#define AWIN_NDMA_BC_COUNT 0x0003ffff +#define AWIN_DDMA_CTL_DMA_LOADING (1U << 31) +#define AWIN_DDMA_CTL_BUSY (1U << 30) +#define AWIN_DDMA_CTL_DMA_CONTIN_MODE (1U << 29) +#define AWIN_DDMA_CTL_DST_NON_SECURE (1U << 28) +#define AWIN_DDMA_CTL_DST_ADDR_MODE_SHIFT 21 +#define AWIN_DDMA_CTL_DST_ADDR_MODE_MASK (3U << AWIN_DDMA_CTL_DST_ADDR_MODE_SHIFT) +#define AWIN_DDMA_CTL_DMA_ADDR_LINEAR 0 +#define AWIN_DDMA_CTL_DMA_ADDR_IO 1 +#define AWIN_DDMA_CTL_DMA_ADDR_HPAGE 2 +#define AWIN_DDMA_CTL_DMA_ADDR_VPAGE 3 +#define AWIN_DDMA_CTL_DST_DRQ_TYPE_SHIFT 16 +#define AWIN_DDMA_CTL_DST_DRQ_TYPE_MASK (0x1f << AWIN_DDMA_CTL_DST_DRQ_TYPE_SHIFT) +#define AWIN_DDMA_CTL_DRQ_SRAM 0 +#define AWIN_DDMA_CTL_DRQ_SDRAM 1 +#define AWIN_DDMA_CTL_DRQ_NFC 3 +#define AWIN_DDMA_CTL_DRQ_USB0 4 +#define AWIN_DDMA_CTL_DRQ_EMAC_TX 6 +#define AWIN_DDMA_CTL_DRQ_EMAC_RX 7 +#define AWIN_DDMA_CTL_DRQ_SPI1_TX 8 +#define AWIN_DDMA_CTL_DRQ_SPI1_RX 9 +#define AWIN_DDMA_CTL_DRQ_SS_TX 10 +#define AWIN_DDMA_CTL_DRQ_SS_RX 11 +#define AWIN_DDMA_CTL_DRQ_TCON0 14 +#define AWIN_DDMA_CTL_DRQ_TCON1 15 +#define AWIN_DDMA_CTL_DRQ_MS_TX 23 +#define AWIN_DDMA_CTL_DRQ_MS_RX 23 +#define AWIN_DDMA_CTL_DRQ_HDMI_AUDIO 24 +#define AWIN_DDMA_CTL_DRQ_SPI0_TX 26 +#define AWIN_DDMA_CTL_DRQ_SPI0_RX 27 +#define AWIN_DDMA_CTL_DRQ_SPI2_TX 28 +#define AWIN_DDMA_CTL_DRQ_SPI2_RX 29 +#define AWIN_DDMA_CTL_DRQ_SPI3_TX 30 +#define AWIN_DDMA_CTL_DRQ_SPI3_RX 31 +#define AWIN_DDMA_CTL_SRC_NON_SECURE (1U << 12) +#define AWIN_DDMA_CTL_SRC_ADDR_MODE_SHIFT 5 +#define AWIN_DDMA_CTL_SRC_ADDR_MODE_MASK (3U << AWIN_DDMA_CTL_SRC_ADDR_MODE_SHIFT) +#define AWIN_DDMA_BC_COUNT 0x00003fff +#define AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_SHIFT 24 +#define AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_MASK (0xff << AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_SHIFT) +#define AWIN_DDMA_PARA_DST_WAIT_CYC_SHIFT 16 +#define AWIN_DDMA_PARA_DST_WAIT_CYC_MASK (0xff << AWIN_DDMA_PARA_DST_WAIT_CYC_SHIFT) +#define AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_SHIFT 8 +#define AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_MASK (0xff << AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_SHIFT) +#define AWIN_DDMA_PARA_SRC_WAIT_CYC_SHIFT 0 +#define AWIN_DDMA_PARA_SRC_WAIT_CYC_MASK (0xff << AWIN_DDMA_PARA_SRC_WAIT_CYC_SHIFT) + +#endif /* !_A10_DMAC_H_ */ Property changes on: head/sys/arm/allwinner/a10_dmac.h ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/arm/allwinner/files.allwinner =================================================================== --- head/sys/arm/allwinner/files.allwinner (revision 295634) +++ head/sys/arm/allwinner/files.allwinner (revision 295635) @@ -1,17 +1,19 @@ # $FreeBSD$ kern/kern_clocksource.c standard arm/allwinner/a10_ahci.c optional ahci arm/allwinner/a10_clk.c standard arm/allwinner/a10_common.c standard +arm/allwinner/a10_dmac.c standard arm/allwinner/a10_ehci.c optional ehci arm/allwinner/a10_gpio.c optional gpio arm/allwinner/a10_mmc.c optional mmc arm/allwinner/a10_sramc.c standard arm/allwinner/a10_wdog.c standard arm/allwinner/a20/a20_cpu_cfg.c standard arm/allwinner/allwinner_machdep.c standard arm/allwinner/axp209.c optional axp209 arm/allwinner/if_emac.c optional emac +arm/allwinner/sunxi_dma_if.m standard dev/iicbus/twsi/a10_twsi.c optional twsi #arm/allwinner/console.c standard Index: head/sys/arm/allwinner/sunxi_dma_if.m =================================================================== --- head/sys/arm/allwinner/sunxi_dma_if.m (nonexistent) +++ head/sys/arm/allwinner/sunxi_dma_if.m (revision 295635) @@ -0,0 +1,98 @@ +#- +# Copyright (c) 2016 Jared D. McNeill +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +# SUCH DAMAGE. +# +# $FreeBSD$ +# + +#include + +INTERFACE sunxi_dma; + +HEADER { + #include + + struct sunxi_dma_config { + unsigned int dst_width; + unsigned int dst_burst_len; + unsigned int dst_drqtype; + bool dst_noincr; + unsigned int dst_blksize; /* DDMA-only */ + unsigned int dst_wait_cyc; /* DDMA-only */ + unsigned int src_width; + unsigned int src_burst_len; + unsigned int src_drqtype; + bool src_noincr; + unsigned int src_blksize; /* DDMA-only */ + unsigned int src_wait_cyc; /* DDMA-only */ + }; + + typedef void (*sunxi_dma_callback)(void *); +} + +# +# Allocate DMA channel +# +METHOD void * alloc { + device_t dev; + bool dedicated; + sunxi_dma_callback callback; + void *callback_arg; +}; + +# +# Free DMA channel +# +METHOD void free { + device_t dev; + void *dmachan; +}; + +# +# Set DMA channel configuration +# +METHOD int set_config { + device_t dev; + void *dmachan; + const struct sunxi_dma_config *cfg; +}; + +# +# Start DMA channel transfer +# +METHOD int transfer { + device_t dev; + void *dmachan; + bus_addr_t src; + bus_addr_t dst; + size_t nbytes; +}; + +# +# Halt DMA channel transfer +# +METHOD void halt { + device_t dev; + void *dmachan; +}; Property changes on: head/sys/arm/allwinner/sunxi_dma_if.m ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/arm/conf/A10 =================================================================== --- head/sys/arm/conf/A10 (revision 295634) +++ head/sys/arm/conf/A10 (revision 295635) @@ -1,106 +1,107 @@ # # A10 -- Custom configuration for the AllWinner A10 SoC # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ ident A10 include "std.armv6" include "../allwinner/std.a10" options HZ=100 options SCHED_4BSD # 4BSD scheduler options PLATFORM # Debugging for use in -current makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols options ALT_BREAK_TO_DEBUGGER #options VERBOSE_SYSINIT # Enable verbose sysinit messages options KDB # Enable kernel debugger support # For minimum debugger support (stable branch) use: #options KDB_TRACE # Print a stack trace for a panic # For full debugger support use this instead: options DDB # Enable the kernel debugger options INVARIANTS # Enable calls of extra sanity checking options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS options WITNESS # Enable checks to detect deadlocks and cycles options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed #options DIAGNOSTIC # NFS root from boopt/dhcp #options BOOTP #options BOOTP_NFSROOT #options BOOTP_COMPAT #options BOOTP_NFSV3 #options BOOTP_WIRED_TO=emac0 # MMC/SD/SDIO Card slot support device mmc # mmc/sd bus device mmcsd # mmc/sd flash cards # ATA controllers device ahci # AHCI-compatible SATA controllers #device ata # Legacy ATA/SATA controllers # Console and misc device uart device uart_ns8250 device pty device snp device md device random # Entropy device # I2C support device iicbus device iic device twsi +device axp209 # AXP209 Power Management Unit # GPIO device gpio device gpioled device scbus # SCSI bus (required for ATA/SCSI) device da # Direct Access (disks) device pass # Passthrough device (direct ATA/SCSI access) # USB support options USB_HOST_ALIGN=64 # Align usb buffers to cache line size. device usb options USB_DEBUG #options USB_REQ_DEBUG #options USB_VERBOSE #device uhci #device ohci device ehci device umass # Ethernet device loop device ether device mii device bpf device emac # USB ethernet support, requires miibus device miibus # Flattened Device Tree options FDT # Configure using FDT/DTB data makeoptions MODULES_EXTRA=dtb/allwinner Index: head/sys/arm/conf/A20 =================================================================== --- head/sys/arm/conf/A20 (revision 295634) +++ head/sys/arm/conf/A20 (revision 295635) @@ -1,116 +1,117 @@ # # A20 -- Custom configuration for the Allwinner A20 ARM SoC # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ ident A20 include "std.armv6" include "../allwinner/a20/std.a20" options ARM_INTRNG options HZ=100 options SCHED_ULE # ULE scheduler options SMP # Enable multiple cores options PLATFORM # Debugging for use in -current makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols options ALT_BREAK_TO_DEBUGGER #options VERBOSE_SYSINIT # Enable verbose sysinit messages options KDB # Enable kernel debugger support # For minimum debugger support (stable branch) use: #options KDB_TRACE # Print a stack trace for a panic # For full debugger support use this instead: options DDB # Enable the kernel debugger options INVARIANTS # Enable calls of extra sanity checking options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS options WITNESS # Enable checks to detect deadlocks and cycles options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed #options DIAGNOSTIC # NFS root from boopt/dhcp #options BOOTP #options BOOTP_NFSROOT #options BOOTP_COMPAT #options BOOTP_NFSV3 #options BOOTP_WIRED_TO=dwc0 # Interrupt controller device gic # ARM Generic Timer device generic_timer # MMC/SD/SDIO Card slot support device mmc # mmc/sd bus device mmcsd # mmc/sd flash cards # ATA controllers device ahci # AHCI-compatible SATA controllers #device ata # Legacy ATA/SATA controllers # Console and misc device uart device uart_ns8250 device pty device snp device md device random # Entropy device # I2C support device iicbus device iic device twsi +device axp209 # AXP209 Power Management Unit # GPIO device gpio device gpioled device scbus # SCSI bus (required for ATA/SCSI) device da # Direct Access (disks) device pass # Passthrough device (direct ATA/SCSI access) # USB support options USB_HOST_ALIGN=64 # Align usb buffers to cache line size. device usb options USB_DEBUG #options USB_REQ_DEBUG #options USB_VERBOSE #device uhci #device ohci device ehci device umass # Ethernet device loop device ether device mii device bpf #device emac # 10/100 integrated EMAC controller device dwc # 10/100/1000 integrated GMAC controller # USB ethernet support, requires miibus device miibus # Flattened Device Tree options FDT # Configure using FDT/DTB data makeoptions MODULES_EXTRA=dtb/allwinner Index: head/sys/boot/fdt/dts/arm/sun7i-a20.dtsi =================================================================== --- head/sys/boot/fdt/dts/arm/sun7i-a20.dtsi (revision 295634) +++ head/sys/boot/fdt/dts/arm/sun7i-a20.dtsi (revision 295635) @@ -1,178 +1,185 @@ /*- * Copyright (c) 2014 Ganbold Tsagaankhuu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include / { compatible = "allwinner,sun7i-a20"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&GIC>; aliases { soc = &SOC; }; timer { compatible = "arm,armv7-timer"; interrupts = , , , ; }; SOC: a20 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; ranges; bus-frequency = <0>; GIC: interrupt-controller@01c81000 { compatible = "arm,gic"; reg = <0x01c81000 0x1000>, /* Distributor Registers */ <0x01c82000 0x0100>, /* CPU Interface Registers */ <0x01c84000 0x2000>, <0x01c86000 0x2000>; interrupt-controller; #interrupt-cells = <3>; interrupts = ; }; sramc@01c00000 { compatible = "allwinner,sun4i-sramc"; #address-cells = <1>; #size-cells = <1>; reg = < 0x01c00000 0x1000 >; }; cpu-cfg@01c25c00 { compatible = "allwinner,sun7i-cpu-cfg"; #address-cells = <1>; #size-cells = <1>; reg = < 0x01c25c00 0x400 >; }; ccm@01c20000 { compatible = "allwinner,sun4i-ccm"; #address-cells = <1>; #size-cells = <1>; reg = < 0x01c20000 0x400 >; }; timer@01c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x90>; interrupts = , , , , , ; interrupt-parent = <&GIC>; clock-frequency = < 24000000 >; }; watchdog@01c20c90 { compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; }; pio: gpio@01c20800 { #gpio-cells = <3>; compatible = "allwinner,sun7i-a20-pinctrl"; gpio-controller; reg =< 0x01c20800 0x400 >; interrupts = ; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&GIC>; }; usb1: usb@01c14000 { compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; reg = <0x01c14000 0x1000>; interrupts = ; interrupt-parent = <&GIC>; }; usb2: usb@01c1c000 { compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; reg = <0x01c1c000 0x1000>; interrupts = ; interrupt-parent = <&GIC>; }; mmc0: mmc@01c0f000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c0f000 0x1000>; interrupts = ; status = "disabled"; }; sata@01c18000 { compatible = "allwinner,sun4i-a10-ahci"; reg = <0x01c18000 0x1000>; interrupts = ; interrupt-parent = <&GIC>; status = "disabled"; }; UART0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; reg-shift = <2>; interrupts = ; current-speed = <115200>; clock-frequency = < 24000000 >; }; emac@01c0b000 { compatible = "allwinner,sun4i-a10-emac"; reg = <0x01c0b000 0x1000>; interrupts = ; interrupt-parent = <&GIC>; status = "disabled"; }; gmac@01c50000 { compatible = "allwinner,sun7i-a20-gmac"; reg = <0x01c50000 0x10000>; interrupts = ; interrupt-parent = <&GIC>; snps,pbl = <2>; snps,fixed-burst; snps,force_sf_dma_mode; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; + + dma: dma-controller@01c02000 { + compatible = "allwinner,sun4i-a10-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <27>; + interrupt-parent = <&GIC>; + }; }; };