Index: head/sys/arm64/arm64/intr_machdep.c =================================================================== --- head/sys/arm64/arm64/intr_machdep.c (revision 295514) +++ head/sys/arm64/arm64/intr_machdep.c (revision 295515) @@ -1,506 +1,584 @@ /*- * Copyright (c) 1991 The Regents of the University of California. * Copyright (c) 2002 Benno Rice. * Copyright (c) 2014 The FreeBSD Foundation * All rights reserved. * * This software was developed by Semihalf under * the sponsorship of the FreeBSD Foundation. * * This code is derived from software contributed by * William Jolitz (Berkeley) and Benno Rice. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * form: src/sys/powerpc/powerpc/intr_machdep.c, r271712 2014/09/17 */ #include __FBSDID("$FreeBSD$"); #include +#include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef SMP #include #endif #include "pic_if.h" #define MAX_STRAY_LOG 5 #define INTRNAME_LEN (MAXCOMLEN + 1) #define NIRQS 1024 /* Maximum number of interrupts in the system */ static MALLOC_DEFINE(M_INTR, "intr", "Interrupt Services"); /* * Linked list of interrupts that have been set-up. * Each element holds the interrupt description * and has to be allocated and freed dynamically. */ static SLIST_HEAD(, arm64_intr_entry) irq_slist_head = SLIST_HEAD_INITIALIZER(irq_slist_head); struct arm64_intr_entry { SLIST_ENTRY(arm64_intr_entry) entries; struct intr_event *i_event; enum intr_trigger i_trig; enum intr_polarity i_pol; u_int i_hw_irq; /* Physical interrupt number */ u_int i_cntidx; /* Index in intrcnt table */ u_int i_handlers; /* Allocated handlers */ + u_int i_cpu; /* Assigned CPU */ u_long *i_cntp; /* Interrupt hit counter */ }; /* Counts and names for statistics - see sys/sys/interrupt.h */ /* Tables are indexed by i_cntidx */ u_long intrcnt[NIRQS]; char intrnames[NIRQS * INTRNAME_LEN]; size_t sintrcnt = sizeof(intrcnt); size_t sintrnames = sizeof(intrnames); static u_int intrcntidx; /* Current index into intrcnt table */ static u_int arm64_nintrs; /* Max interrupts number of the root PIC */ static u_int arm64_nstray; /* Number of received stray interrupts */ static device_t root_pic; /* PIC device for all incoming interrupts */ static device_t msi_pic; /* Device which handles MSI/MSI-X interrupts */ static struct mtx intr_list_lock; static void intr_init(void *dummy __unused) { mtx_init(&intr_list_lock, "intr sources lock", NULL, MTX_SPIN); } SYSINIT(intr_init, SI_SUB_INTR, SI_ORDER_FIRST, intr_init, NULL); /* * Helper routines. */ /* Set interrupt name for statistics */ static void intrcnt_setname(const char *name, u_int idx) { snprintf(&intrnames[idx * INTRNAME_LEN], INTRNAME_LEN, "%-*s", INTRNAME_LEN - 1, name); } /* * Find the interrupt descriptor in the list * based on the hardware IRQ number. */ static __inline struct arm64_intr_entry * intr_lookup_locked(u_int hw_irq) { struct arm64_intr_entry *intr; mtx_assert(&intr_list_lock, MA_OWNED); SLIST_FOREACH(intr, &irq_slist_head, entries) { if (intr->i_hw_irq == hw_irq) return (intr); } return (NULL); } /* * Get intr structure for the given interrupt number. * Allocate one if this is the first time. */ static struct arm64_intr_entry * intr_allocate(u_int hw_irq) { struct arm64_intr_entry *intr; /* Check if already allocated */ mtx_lock_spin(&intr_list_lock); intr = intr_lookup_locked(hw_irq); mtx_unlock_spin(&intr_list_lock); if (intr != NULL) return (intr); /* Do not alloc another intr when max number of IRQs has been reached */ if (intrcntidx >= NIRQS) return (NULL); intr = malloc(sizeof(*intr), M_INTR, M_NOWAIT); if (intr == NULL) return (NULL); + /* The default CPU is 0 but can be changed later by bind or shuffle */ + intr->i_cpu = 0; intr->i_event = NULL; intr->i_handlers = 0; intr->i_trig = INTR_TRIGGER_CONFORM; intr->i_pol = INTR_POLARITY_CONFORM; intr->i_cntidx = atomic_fetchadd_int(&intrcntidx, 1); intr->i_cntp = &intrcnt[intr->i_cntidx]; intr->i_hw_irq = hw_irq; mtx_lock_spin(&intr_list_lock); SLIST_INSERT_HEAD(&irq_slist_head, intr, entries); mtx_unlock_spin(&intr_list_lock); return intr; } +static int +intr_assign_cpu(void *arg, int cpu) +{ +#ifdef SMP + struct arm64_intr_entry *intr; + int error; + + if (root_pic == NULL) + panic("Cannot assing interrupt to CPU. No PIC configured"); + /* + * Set the interrupt to CPU affinity. + * Do not configure this in hardware during early boot. + * We will pick up the assignment once the APs are started. + */ + if (cpu != NOCPU) { + intr = arg; + if (!cold && smp_started) { + /* + * Bind the interrupt immediately + * if SMP is up and running. + */ + error = PIC_BIND(root_pic, intr->i_hw_irq, cpu); + if (error == 0) + intr->i_cpu = cpu; + } else { + /* Postpone binding until SMP is operational */ + intr->i_cpu = cpu; + error = 0; + } + } else + error = 0; + + return (error); +#else + return (EOPNOTSUPP); +#endif +} + static void intr_pre_ithread(void *arg) { struct arm64_intr_entry *intr = arg; PIC_PRE_ITHREAD(root_pic, intr->i_hw_irq); } static void intr_post_ithread(void *arg) { struct arm64_intr_entry *intr = arg; PIC_POST_ITHREAD(root_pic, intr->i_hw_irq); } static void intr_post_filter(void *arg) { struct arm64_intr_entry *intr = arg; PIC_POST_FILTER(root_pic, intr->i_hw_irq); } /* * Register PIC driver. * This is intended to be called by the very first PIC driver * at the end of the successful attach. * Note that during boot this can be called after first references * to bus_setup_intr() so it is required to not use root_pic if it * is not 100% safe. */ void arm_register_root_pic(device_t dev, u_int nirq) { KASSERT(root_pic == NULL, ("Unable to set the pic twice")); KASSERT(nirq <= NIRQS, ("PIC is trying to handle too many IRQs")); arm64_nintrs = NIRQS; /* Number of IRQs limited only by array size */ root_pic = dev; } /* Register device which allocates MSI interrupts */ void arm_register_msi_pic(device_t dev) { KASSERT(msi_pic == NULL, ("Unable to set msi_pic twice")); msi_pic = dev; } int arm_alloc_msi(device_t pci, device_t child, int count, int maxcount, int *irqs) { return (PIC_ALLOC_MSI(msi_pic, child, count, irqs)); } int arm_release_msi(device_t pci, device_t child, int count, int *irqs) { return (PIC_RELEASE_MSI(msi_pic, child, count, irqs)); } int arm_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, uint32_t *data) { return (PIC_MAP_MSI(msi_pic, child, irq, addr, data)); } int arm_alloc_msix(device_t pci, device_t child, int *irq) { return (PIC_ALLOC_MSIX(msi_pic, child, irq)); } int arm_release_msix(device_t pci, device_t child, int irq) { return (PIC_RELEASE_MSIX(msi_pic, child, irq)); } /* * Finalize interrupts bring-up (should be called from configure_final()). * Enables all interrupts registered by bus_setup_intr() during boot * as well as unlocks interrups reception on primary CPU. */ int arm_enable_intr(void) { struct arm64_intr_entry *intr; if (root_pic == NULL) panic("Cannot enable interrupts. No PIC configured"); /* * Iterate through all possible interrupts and perform * configuration if the interrupt is registered. */ SLIST_FOREACH(intr, &irq_slist_head, entries) { /* * XXX: In case we allowed to set up interrupt whose number * exceeds maximum number of interrupts for the root PIC * disable it and print proper error message. * * This can happen only when calling bus_setup_intr() * before the interrupt controller is attached. */ if (intr->i_cntidx >= arm64_nintrs) { /* Better fail when IVARIANTS enabled */ KASSERT(0, ("%s: Interrupt %u cannot be handled by the " "registered PIC. Max interrupt number: %u", __func__, intr->i_cntidx, arm64_nintrs - 1)); /* Print message and disable otherwise */ printf("ERROR: Cannot enable irq %u. Disabling.\n", intr->i_cntidx); PIC_MASK(root_pic, intr->i_hw_irq); } if (intr->i_trig != INTR_TRIGGER_CONFORM || intr->i_pol != INTR_POLARITY_CONFORM) { PIC_CONFIG(root_pic, intr->i_hw_irq, intr->i_trig, intr->i_pol); } if (intr->i_handlers > 0) PIC_UNMASK(root_pic, intr->i_hw_irq); } /* Enable interrupt reception on this CPU */ intr_enable(); return (0); } int arm_setup_intr(const char *name, driver_filter_t *filt, driver_intr_t handler, void *arg, u_int hw_irq, enum intr_type flags, void **cookiep) { struct arm64_intr_entry *intr; int error; intr = intr_allocate(hw_irq); if (intr == NULL) return (ENOMEM); /* * Watch out for interrupts' numbers. * If this is a system boot then don't allow to overfill interrupts * table (the interrupts will be deconfigured in arm_enable_intr()). */ if (intr->i_cntidx >= NIRQS) return (EINVAL); if (intr->i_event == NULL) { error = intr_event_create(&intr->i_event, (void *)intr, 0, hw_irq, intr_pre_ithread, intr_post_ithread, - intr_post_filter, NULL, "irq%u", hw_irq); + intr_post_filter, intr_assign_cpu, "irq%u", hw_irq); if (error) return (error); } error = intr_event_add_handler(intr->i_event, name, filt, handler, arg, intr_priority(flags), flags, cookiep); if (!error) { intrcnt_setname(intr->i_event->ie_fullname, intr->i_cntidx); intr->i_handlers++; if (!cold && intr->i_handlers == 1) { if (intr->i_trig != INTR_TRIGGER_CONFORM || intr->i_pol != INTR_POLARITY_CONFORM) { PIC_CONFIG(root_pic, intr->i_hw_irq, intr->i_trig, intr->i_pol); } PIC_UNMASK(root_pic, intr->i_hw_irq); } } return (error); } int arm_teardown_intr(void *cookie) { struct arm64_intr_entry *intr; int error; intr = intr_handler_source(cookie); error = intr_event_remove_handler(cookie); if (!error) { intr->i_handlers--; if (intr->i_handlers == 0) PIC_MASK(root_pic, intr->i_hw_irq); intrcnt_setname(intr->i_event->ie_fullname, intr->i_cntidx); } return (error); } int arm_config_intr(u_int hw_irq, enum intr_trigger trig, enum intr_polarity pol) { struct arm64_intr_entry *intr; mtx_lock_spin(&intr_list_lock); intr = intr_lookup_locked(hw_irq); mtx_unlock_spin(&intr_list_lock); if (intr == NULL) return (EINVAL); intr->i_trig = trig; intr->i_pol = pol; if (!cold && root_pic != NULL) PIC_CONFIG(root_pic, intr->i_hw_irq, trig, pol); return (0); } void arm_dispatch_intr(u_int hw_irq, struct trapframe *tf) { struct arm64_intr_entry *intr; mtx_lock_spin(&intr_list_lock); intr = intr_lookup_locked(hw_irq); mtx_unlock_spin(&intr_list_lock); if (intr == NULL) goto stray; (*intr->i_cntp)++; if (!intr_event_handle(intr->i_event, tf)) return; stray: if (arm64_nstray < MAX_STRAY_LOG) { arm64_nstray++; printf("Stray IRQ %u\n", hw_irq); if (arm64_nstray >= MAX_STRAY_LOG) { printf("Got %d stray IRQs. Not logging anymore.\n", MAX_STRAY_LOG); } } if (intr != NULL) PIC_MASK(root_pic, intr->i_hw_irq); #ifdef HWPMC_HOOKS if (pmc_hook && (PCPU_GET(curthread)->td_pflags & TDP_CALLCHAIN)) pmc_hook(PCPU_GET(curthread), PMC_FN_USER_CALLCHAIN, tf); #endif } void arm_cpu_intr(struct trapframe *tf) { critical_enter(); PIC_DISPATCH(root_pic, tf); critical_exit(); } #ifdef SMP +static void +arm_intr_smp_init(void *dummy __unused) +{ + struct arm64_intr_entry *intr; + int error; + + if (root_pic == NULL) + panic("Cannot assing interrupts to CPUs. No PIC configured"); + + mtx_lock_spin(&intr_list_lock); + SLIST_FOREACH(intr, &irq_slist_head, entries) { + mtx_unlock_spin(&intr_list_lock); + error = PIC_BIND(root_pic, intr->i_hw_irq, intr->i_cpu); + if (error != 0) + intr->i_cpu = 0; + mtx_lock_spin(&intr_list_lock); + } + mtx_unlock_spin(&intr_list_lock); +} +SYSINIT(arm_intr_smp_init, SI_SUB_SMP, SI_ORDER_ANY, arm_intr_smp_init, NULL); + +/* Attempt to bind the specified IRQ to the specified CPU. */ +int +arm_intr_bind(u_int hw_irq, int cpu) +{ + struct arm64_intr_entry *intr; + + mtx_lock_spin(&intr_list_lock); + intr = intr_lookup_locked(hw_irq); + mtx_unlock_spin(&intr_list_lock); + if (intr == NULL) + return (EINVAL); + + return (intr_event_bind(intr->i_event, cpu)); +} + void arm_setup_ipihandler(driver_filter_t *filt, u_int ipi) { arm_setup_intr("ipi", filt, NULL, (void *)((uintptr_t)ipi | 1<<16), ipi, INTR_TYPE_MISC | INTR_EXCL, NULL); arm_unmask_ipi(ipi); } void arm_unmask_ipi(u_int ipi) { PIC_UNMASK(root_pic, ipi); } void arm_init_secondary(void) { PIC_INIT_SECONDARY(root_pic); } /* Sending IPI */ void ipi_all_but_self(u_int ipi) { cpuset_t other_cpus; other_cpus = all_cpus; CPU_CLR(PCPU_GET(cpuid), &other_cpus); CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); PIC_IPI_SEND(root_pic, other_cpus, ipi); } void ipi_cpu(int cpu, u_int ipi) { cpuset_t cpus; CPU_ZERO(&cpus); CPU_SET(cpu, &cpus); CTR2(KTR_SMP, "ipi_cpu: cpu: %d, ipi: %x", cpu, ipi); PIC_IPI_SEND(root_pic, cpus, ipi); } void ipi_selected(cpuset_t cpus, u_int ipi) { CTR1(KTR_SMP, "ipi_selected: ipi: %x", ipi); PIC_IPI_SEND(root_pic, cpus, ipi); } #endif Index: head/sys/arm64/arm64/nexus.c =================================================================== --- head/sys/arm64/arm64/nexus.c (revision 295514) +++ head/sys/arm64/arm64/nexus.c (revision 295515) @@ -1,457 +1,471 @@ /*- * Copyright 1998 Massachusetts Institute of Technology * * Permission to use, copy, modify, and distribute this software and * its documentation for any purpose and without fee is hereby * granted, provided that both the above copyright notice and this * permission notice appear in all copies, that both the above * copyright notice and this permission notice appear in all * supporting documentation, and that the name of M.I.T. not be used * in advertising or publicity pertaining to distribution of the * software without specific, written prior permission. M.I.T. makes * no representations about the suitability of this software for any * purpose. It is provided "as is" without express or implied * warranty. * * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ /* * This code implements a `root nexus' for Arm Architecture * machines. The function of the root nexus is to serve as an * attachment point for both processors and buses, and to manage * resources which are common to all of them. In particular, * this code implements the core resource managers for interrupt * requests, DMA requests (which rightfully should be a part of the * ISA code but it's easier to do it here for now), I/O port addresses, * and I/O memory address space. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "opt_acpi.h" #include "opt_platform.h" #ifdef FDT #include #include "ofw_bus_if.h" #endif #ifdef DEV_ACPI #include #include #endif extern struct bus_space memmap_bus; static MALLOC_DEFINE(M_NEXUSDEV, "nexusdev", "Nexus device"); struct nexus_device { struct resource_list nx_resources; }; #define DEVTONX(dev) ((struct nexus_device *)device_get_ivars(dev)) static struct rman mem_rman; static struct rman irq_rman; static int nexus_attach(device_t); #ifdef FDT static device_probe_t nexus_fdt_probe; static device_attach_t nexus_fdt_attach; #endif #ifdef DEV_ACPI static device_probe_t nexus_acpi_probe; static device_attach_t nexus_acpi_attach; #endif static int nexus_print_child(device_t, device_t); static device_t nexus_add_child(device_t, u_int, const char *, int); static struct resource *nexus_alloc_resource(device_t, device_t, int, int *, rman_res_t, rman_res_t, rman_res_t, u_int); static int nexus_activate_resource(device_t, device_t, int, int, struct resource *); static int nexus_config_intr(device_t dev, int irq, enum intr_trigger trig, enum intr_polarity pol); static struct resource_list *nexus_get_reslist(device_t, device_t); static int nexus_set_resource(device_t, device_t, int, int, rman_res_t, rman_res_t); static int nexus_deactivate_resource(device_t, device_t, int, int, struct resource *); static int nexus_setup_intr(device_t dev, device_t child, struct resource *res, int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep); static int nexus_teardown_intr(device_t, device_t, struct resource *, void *); +#ifdef SMP +static int nexus_bind_intr(device_t, device_t, struct resource *, int); +#endif #ifdef FDT static int nexus_ofw_map_intr(device_t dev, device_t child, phandle_t iparent, int icells, pcell_t *intr); #endif static device_method_t nexus_methods[] = { /* Bus interface */ DEVMETHOD(bus_print_child, nexus_print_child), DEVMETHOD(bus_add_child, nexus_add_child), DEVMETHOD(bus_alloc_resource, nexus_alloc_resource), DEVMETHOD(bus_activate_resource, nexus_activate_resource), DEVMETHOD(bus_config_intr, nexus_config_intr), DEVMETHOD(bus_get_resource_list, nexus_get_reslist), DEVMETHOD(bus_set_resource, nexus_set_resource), DEVMETHOD(bus_deactivate_resource, nexus_deactivate_resource), DEVMETHOD(bus_setup_intr, nexus_setup_intr), DEVMETHOD(bus_teardown_intr, nexus_teardown_intr), - +#ifdef SMP + DEVMETHOD(bus_bind_intr, nexus_bind_intr), +#endif { 0, 0 } }; static driver_t nexus_driver = { "nexus", nexus_methods, 1 /* no softc */ }; static int nexus_attach(device_t dev) { mem_rman.rm_start = 0; mem_rman.rm_end = ~0ul; mem_rman.rm_type = RMAN_ARRAY; mem_rman.rm_descr = "I/O memory addresses"; if (rman_init(&mem_rman) || rman_manage_region(&mem_rman, 0, ~0)) panic("nexus_attach mem_rman"); irq_rman.rm_start = 0; irq_rman.rm_end = ~0ul; irq_rman.rm_type = RMAN_ARRAY; irq_rman.rm_descr = "Interrupts"; if (rman_init(&irq_rman) || rman_manage_region(&irq_rman, 0, ~0)) panic("nexus_attach irq_rman"); bus_generic_probe(dev); bus_generic_attach(dev); return (0); } static int nexus_print_child(device_t bus, device_t child) { int retval = 0; retval += bus_print_child_header(bus, child); retval += printf("\n"); return (retval); } static device_t nexus_add_child(device_t bus, u_int order, const char *name, int unit) { device_t child; struct nexus_device *ndev; ndev = malloc(sizeof(struct nexus_device), M_NEXUSDEV, M_NOWAIT|M_ZERO); if (!ndev) return (0); resource_list_init(&ndev->nx_resources); child = device_add_child_ordered(bus, order, name, unit); /* should we free this in nexus_child_detached? */ device_set_ivars(child, ndev); return (child); } /* * Allocate a resource on behalf of child. NB: child is usually going to be a * child of one of our descendants, not a direct child of nexus0. * (Exceptions include footbridge.) */ static struct resource * nexus_alloc_resource(device_t bus, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) { struct nexus_device *ndev = DEVTONX(child); struct resource *rv; struct resource_list_entry *rle; struct rman *rm; int needactivate = flags & RF_ACTIVE; /* * If this is an allocation of the "default" range for a given * RID, and we know what the resources for this device are * (ie. they aren't maintained by a child bus), then work out * the start/end values. */ if ((start == 0UL) && (end == ~0UL) && (count == 1)) { if (device_get_parent(child) != bus || ndev == NULL) return(NULL); rle = resource_list_find(&ndev->nx_resources, type, *rid); if (rle == NULL) return(NULL); start = rle->start; end = rle->end; count = rle->count; } switch (type) { case SYS_RES_IRQ: rm = &irq_rman; break; case SYS_RES_MEMORY: case SYS_RES_IOPORT: rm = &mem_rman; break; default: return (NULL); } rv = rman_reserve_resource(rm, start, end, count, flags, child); if (rv == 0) return (NULL); rman_set_rid(rv, *rid); rman_set_bushandle(rv, rman_get_start(rv)); if (needactivate) { if (bus_activate_resource(child, type, *rid, rv)) { rman_release_resource(rv); return (NULL); } } return (rv); } static int nexus_config_intr(device_t dev, int irq, enum intr_trigger trig, enum intr_polarity pol) { return (arm_config_intr(irq, trig, pol)); } static int nexus_setup_intr(device_t dev, device_t child, struct resource *res, int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep) { int error; if ((rman_get_flags(res) & RF_SHAREABLE) == 0) flags |= INTR_EXCL; /* We depend here on rman_activate_resource() being idempotent. */ error = rman_activate_resource(res); if (error) return (error); error = arm_setup_intr(device_get_nameunit(child), filt, intr, arg, rman_get_start(res), flags, cookiep); return (error); } static int nexus_teardown_intr(device_t dev, device_t child, struct resource *r, void *ih) { return (arm_teardown_intr(ih)); } + +#ifdef SMP +static int +nexus_bind_intr(device_t dev, device_t child, struct resource *irq, int cpu) +{ + + return (arm_intr_bind(rman_get_start(irq), cpu)); +} +#endif static int nexus_activate_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { int err; bus_addr_t paddr; bus_size_t psize; bus_space_handle_t vaddr; if ((err = rman_activate_resource(r)) != 0) return (err); /* * If this is a memory resource, map it into the kernel. */ if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) { paddr = (bus_addr_t)rman_get_start(r); psize = (bus_size_t)rman_get_size(r); err = bus_space_map(&memmap_bus, paddr, psize, 0, &vaddr); if (err != 0) { rman_deactivate_resource(r); return (err); } rman_set_bustag(r, &memmap_bus); rman_set_virtual(r, (void *)vaddr); rman_set_bushandle(r, vaddr); } return (0); } static struct resource_list * nexus_get_reslist(device_t dev, device_t child) { struct nexus_device *ndev = DEVTONX(child); return (&ndev->nx_resources); } static int nexus_set_resource(device_t dev, device_t child, int type, int rid, rman_res_t start, rman_res_t count) { struct nexus_device *ndev = DEVTONX(child); struct resource_list *rl = &ndev->nx_resources; /* XXX this should return a success/failure indicator */ resource_list_add(rl, type, rid, start, start + count - 1, count); return(0); } static int nexus_deactivate_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { bus_size_t psize; bus_space_handle_t vaddr; psize = (bus_size_t)rman_get_size(r); vaddr = rman_get_bushandle(r); if (vaddr != 0) { bus_space_unmap(&memmap_bus, vaddr, psize); rman_set_virtual(r, NULL); rman_set_bushandle(r, 0); } return (rman_deactivate_resource(r)); } #ifdef FDT static device_method_t nexus_fdt_methods[] = { /* Device interface */ DEVMETHOD(device_probe, nexus_fdt_probe), DEVMETHOD(device_attach, nexus_fdt_attach), /* OFW interface */ DEVMETHOD(ofw_bus_map_intr, nexus_ofw_map_intr), }; #define nexus_baseclasses nexus_fdt_baseclasses DEFINE_CLASS_1(nexus, nexus_fdt_driver, nexus_fdt_methods, 1, nexus_driver); #undef nexus_baseclasses static devclass_t nexus_fdt_devclass; EARLY_DRIVER_MODULE(nexus_fdt, root, nexus_fdt_driver, nexus_fdt_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_FIRST); static int nexus_fdt_probe(device_t dev) { if (OF_peer(0) == 0) return (ENXIO); device_quiet(dev); return (BUS_PROBE_DEFAULT); } static int nexus_fdt_attach(device_t dev) { nexus_add_child(dev, 10, "ofwbus", 0); return (nexus_attach(dev)); } static int nexus_ofw_map_intr(device_t dev, device_t child, phandle_t iparent, int icells, pcell_t *intr) { int irq; if (icells == 3) { irq = intr[1]; if (intr[0] == 0) irq += 32; /* SPI */ else irq += 16; /* PPI */ } else irq = intr[0]; return (irq); } #endif #ifdef DEV_ACPI static device_method_t nexus_acpi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, nexus_acpi_probe), DEVMETHOD(device_attach, nexus_acpi_attach), }; #define nexus_baseclasses nexus_acpi_baseclasses DEFINE_CLASS_1(nexus, nexus_acpi_driver, nexus_acpi_methods, 1, nexus_driver); #undef nexus_baseclasses static devclass_t nexus_acpi_devclass; EARLY_DRIVER_MODULE(nexus_acpi, root, nexus_acpi_driver, nexus_acpi_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_FIRST); static int nexus_acpi_probe(device_t dev) { if (acpi_identify() != 0) return (ENXIO); device_quiet(dev); return (BUS_PROBE_LOW_PRIORITY); } static int nexus_acpi_attach(device_t dev) { nexus_add_child(dev, 10, "acpi", 0); return (nexus_attach(dev)); } #endif Index: head/sys/arm64/arm64/pic_if.m =================================================================== --- head/sys/arm64/arm64/pic_if.m (revision 295514) +++ head/sys/arm64/arm64/pic_if.m (revision 295515) @@ -1,172 +1,176 @@ #- # Copyright (c) 1998 Doug Rabson # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions # are met: # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # # THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS # OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) # HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT # LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY # OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF # SUCH DAMAGE. # # from: src/sys/kern/bus_if.m,v 1.21 2002/04/21 11:16:10 markm Exp # $FreeBSD$ # #include #include #include INTERFACE pic; CODE { - static pic_translate_code_t pic_translate_code_default; + static int pic_bind_default(device_t dev, u_int irq, u_int cpu) + { + return (EOPNOTSUPP); + } + static void pic_translate_code_default(device_t dev, u_int irq, int code, enum intr_trigger *trig, enum intr_polarity *pol) { *trig = INTR_TRIGGER_CONFORM; *pol = INTR_POLARITY_CONFORM; } static void pic_pre_ithread(device_t dev, u_int irq) { PIC_MASK(dev, irq); PIC_EOI(dev, irq); } static void pic_post_ithread(device_t dev, u_int irq) { PIC_UNMASK(dev, irq); } static void pic_post_filter(device_t dev, u_int irq) { PIC_EOI(dev, irq); } }; -METHOD void bind { +METHOD int bind { device_t dev; u_int irq; - cpuset_t cpumask; -}; + u_int cpu; +} DEFAULT pic_bind_default; METHOD void translate_code { device_t dev; u_int irq; int code; enum intr_trigger *trig; enum intr_polarity *pol; } DEFAULT pic_translate_code_default; METHOD void config { device_t dev; u_int irq; enum intr_trigger trig; enum intr_polarity pol; }; METHOD void dispatch { device_t dev; struct trapframe *tf; }; METHOD void enable { device_t dev; u_int irq; u_int vector; }; METHOD void pre_ithread { device_t dev; u_int irq; } DEFAULT pic_pre_ithread; METHOD void post_ithread { device_t dev; u_int irq; } DEFAULT pic_post_ithread; METHOD void post_filter { device_t dev; u_int irq; } DEFAULT pic_post_filter; METHOD void eoi { device_t dev; u_int irq; }; METHOD void ipi { device_t dev; u_int cpu; }; METHOD void mask { device_t dev; u_int irq; }; METHOD void unmask { device_t dev; u_int irq; }; METHOD void init_secondary { device_t dev; }; METHOD void ipi_send { device_t dev; cpuset_t cpus; u_int ipi; }; METHOD int alloc_msi { device_t dev; device_t pci_dev; int count; int *irqs; }; METHOD int alloc_msix { device_t dev; device_t pci_dev; int *irq; }; METHOD int map_msi { device_t dev; device_t pci_dev; int irq; uint64_t *addr; uint32_t *data; }; METHOD int release_msi { device_t dev; device_t pci_dev; int count; int *irqs; }; METHOD int release_msix { device_t dev; device_t pci_dev; int irq; }; Index: head/sys/arm64/include/intr.h =================================================================== --- head/sys/arm64/include/intr.h (revision 295514) +++ head/sys/arm64/include/intr.h (revision 295515) @@ -1,56 +1,57 @@ /*- * Copyright (c) 2014 Andrew Turner * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _MACHINE_INTR_H_ #define _MACHINE_INTR_H_ int arm_config_intr(u_int, enum intr_trigger, enum intr_polarity); void arm_cpu_intr(struct trapframe *); void arm_dispatch_intr(u_int, struct trapframe *); int arm_enable_intr(void); void arm_mask_irq(u_int); void arm_register_root_pic(device_t, u_int); void arm_register_msi_pic(device_t); int arm_alloc_msi(device_t, device_t, int, int, int *); int arm_release_msi(device_t, device_t, int, int *); int arm_alloc_msix(device_t, device_t, int *); int arm_release_msix(device_t, device_t, int); int arm_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); int arm_map_msix(device_t, device_t, int, uint64_t *, uint32_t *); int arm_setup_intr(const char *, driver_filter_t *, driver_intr_t, void *, u_int, enum intr_type, void **); int arm_teardown_intr(void *); void arm_unmask_irq(u_int); #ifdef SMP void arm_init_secondary(void); +int arm_intr_bind(u_int, int); void arm_setup_ipihandler(driver_filter_t *, u_int); void arm_unmask_ipi(u_int); #endif #endif /* _MACHINE_INTR_H */