Index: head/sys/conf/options.mips =================================================================== --- head/sys/conf/options.mips (revision 295137) +++ head/sys/conf/options.mips (revision 295138) @@ -1,138 +1,142 @@ # Copyright (c) 2001, 2008, Juniper Networks, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions # are met: # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # 3. Neither the name of the Juniper Networks, Inc. nor the names of its # contributors may be used to endorse or promote products derived from # this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY JUNIPER NETWORKS AND CONTRIBUTORS ``AS IS'' AND # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL JUNIPER NETWORKS OR CONTRIBUTORS BE LIABLE # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS # OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) # HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT # LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY # OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF # SUCH DAMAGE. # # JNPR: options.mips,v 1.2 2006/09/15 12:52:34 # $FreeBSD$ CPU_MIPS4KC opt_global.h -CPU_MIPS24KC opt_global.h -CPU_MIPS74KC opt_global.h -CPU_MIPS1004KC opt_global.h +CPU_MIPS24K opt_global.h +CPU_MIPS34K opt_global.h +CPU_MIPS74K opt_global.h +CPU_MIPS1004K opt_global.h +CPU_MIPS1074K opt_global.h +CPU_INTERAPTIV opt_global.h +CPU_PROAPTIV opt_global.h CPU_MIPS32 opt_global.h CPU_MIPS64 opt_global.h CPU_SENTRY5 opt_global.h CPU_HAVEFPU opt_global.h CPU_SB1 opt_global.h CPU_CNMIPS opt_global.h CPU_RMI opt_global.h CPU_NLM opt_global.h CPU_BERI opt_global.h # which MACHINE_ARCH architecture MIPS MIPSEL MIPS64 MIPS64EL MIPSN32 COMPAT_FREEBSD32 opt_compat.h YAMON opt_global.h CFE opt_global.h CFE_CONSOLE opt_global.h CFE_ENV opt_global.h CFE_ENV_SIZE opt_global.h GFB_DEBUG opt_gfb.h GFB_NO_FONT_LOADING opt_gfb.h GFB_NO_MODE_CHANGE opt_gfb.h NOFPU opt_global.h TICK_USE_YAMON_FREQ opt_global.h TICK_USE_MALTA_RTC opt_global.h # # The highest memory address that can be used by the kernel in units of KB. # MAXMEM opt_global.h # # Manual override of cache config # MIPS_DISABLE_L1_CACHE opt_global.h # # Options that control the Cavium Simple Executive. # OCTEON_MODEL opt_cvmx.h OCTEON_VENDOR_LANNER opt_cvmx.h OCTEON_VENDOR_UBIQUITI opt_cvmx.h OCTEON_VENDOR_RADISYS opt_cvmx.h OCTEON_VENDOR_GEFES opt_cvmx.h OCTEON_BOARD_CAPK_0100ND opt_cvmx.h # # Options specific to the BERI platform. # BERI_LARGE_TLB opt_global.h # # Options that control the NetFPGA-10G Embedded CPU Ethernet Core. # NF10BMAC_64BIT opt_netfpga.h # # Options that control the Atheros SoC peripherals # ARGE_DEBUG opt_arge.h ARGE_MDIO opt_arge.h # # At least one of the AR71XX ubiquiti boards has a Redboot configuration # that "lies" about the amount of RAM it has. Until a cleaner method is # defined, this option will suffice in overriding what Redboot says. # AR71XX_REALMEM opt_ar71xx.h AR71XX_ENV_UBOOT opt_ar71xx.h AR71XX_ENV_REDBOOT opt_ar71xx.h AR71XX_ENV_ROUTERBOOT opt_ar71xx.h AR71XX_ATH_EEPROM opt_ar71xx.h # # Options that control the Ralink RT305xF Etherenet MAC. # IF_RT_DEBUG opt_if_rt.h IF_RT_PHY_SUPPORT opt_if_rt.h IF_RT_RING_DATA_COUNT opt_if_rt.h # # Options that control the Ralink/Mediatek SoC type. # MT7620 opt_rt305x.h RT5350 opt_rt305x.h RT305XF opt_rt305x.h RT3052F opt_rt305x.h RT3050F opt_rt305x.h RT305X opt_rt305x.h RT305X_UBOOT opt_rt305x.h RT305X_USE_UART opt_rt305x.h # # Options that affect the pmap. # PV_STATS opt_pmap.h Index: head/sys/mips/conf/AR934X_BASE =================================================================== --- head/sys/mips/conf/AR934X_BASE (revision 295137) +++ head/sys/mips/conf/AR934X_BASE (revision 295138) @@ -1,129 +1,129 @@ # # AR91XX -- Kernel configuration base file for the Atheros AR913x SoC. # # This file (and the hints file accompanying it) are not designed to be # used by themselves. Instead, users of this file should create a kernel # config file which includes this file (which gets the basic hints), then # override the default options (adding devices as needed) and adding # hints as needed (for example, the GPIO and LAN PHY.) # # $FreeBSD$ # machine mips mips ident AR934X_BASE -cpu CPU_MIPS74KC +cpu CPU_MIPS74K makeoptions KERNLOADADDR=0x80050000 options HZ=1000 files "../atheros/files.ar71xx" hints "AR934X_BASE.hints" makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols makeoptions MODULES_OVERRIDE="gpio ar71xx if_gif if_gre if_vlan if_bridge bridgestp usb wlan wlan_xauth wlan_acl wlan_wep wlan_tkip wlan_ccmp wlan_rssadapt wlan_amrr ath ath_ahb hwpmc ipfw ipfw_nat libalias" # makeoptions MODULES_OVERRIDE="" options DDB options KDB options ALQ options SCHED_4BSD #4BSD scheduler options INET #InterNETworking #options INET6 #InterNETworking #options NFSCL #Network Filesystem Client options PSEUDOFS #Pseudo-filesystem framework options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions # Don't include the SCSI/CAM strings in the default build options SCSI_NO_SENSE_STRINGS options SCSI_NO_OP_STRINGS # .. And no sysctl strings options NO_SYSCTL_DESCR # Limit IO size options NBUF=128 # Limit UMTX hash size # options UMTX_NUM_CHAINS=64 # PMC #options HWPMC_HOOKS #device hwpmc #device hwpmc_mips24k # options NFS_LEGACYRPC # Debugging for use in -current #options INVARIANTS #options INVARIANT_SUPPORT #options WITNESS #options WITNESS_SKIPSPIN options FFS #Berkeley Fast Filesystem #options SOFTUPDATES #Enable FFS soft updates support #options UFS_ACL #Support for access control lists #options UFS_DIRHASH #Improve performance on big directories options NO_FFS_SNAPSHOT # We don't require snapshot support # Wireless NIC cards options IEEE80211_DEBUG options IEEE80211_SUPPORT_MESH options IEEE80211_SUPPORT_TDMA options IEEE80211_SUPPORT_SUPERG options IEEE80211_ALQ # 802.11 ALQ logging support device wlan # 802.11 support device wlan_wep # 802.11 WEP support device wlan_ccmp # 802.11 CCMP support device wlan_tkip # 802.11 TKIP support device wlan_xauth # 802.11 hostap support # ath(4) device ath # Atheros network device device ath_rate_sample device ath_ahb # Atheros host bus glue options ATH_DEBUG options ATH_DIAGAPI option ATH_ENABLE_11N #device ath_hal device ath_ar9300 # AR9330 HAL; no need for the others option AH_DEBUG option AH_SUPPORT_AR5416 # 11n HAL support option AH_SUPPORT_AR9340 # Chipset support option AH_DEBUG_ALQ option AH_AR5416_INTERRUPT_MITIGATION device mii device arge device usb options USB_EHCI_BIG_ENDIAN_DESC # handle big-endian byte order options USB_DEBUG options USB_HOST_ALIGN=32 # AR71XX (MIPS in general?) requires this device ehci device pci device ar724x_pci device scbus device umass device da device spibus device ar71xx_spi device mx25l device ar71xx_wdog device uart device uart_ar71xx # XXX for now; later a separate APB mux is needed to demux PCI/WLAN interrupts. device ar71xx_apb device loop device ether device md device bpf device random device if_bridge device gpio device gpioled Index: head/sys/mips/conf/QCA955X_BASE =================================================================== --- head/sys/mips/conf/QCA955X_BASE (revision 295137) +++ head/sys/mips/conf/QCA955X_BASE (revision 295138) @@ -1,141 +1,141 @@ # # QCA955X_BASE -- Kernel configuration base file for the Qualcomm Atheros # QCA955x SoC. # # This file (and the hints file accompanying it) are not designed to be # used by themselves. Instead, users of this file should create a kernel # config file which includes this file (which gets the basic hints), then # override the default options (adding devices as needed) and adding # hints as needed (for example, the GPIO and LAN PHY.) # # $FreeBSD$ # machine mips mips ident QCA955X_BASE -cpu CPU_MIPS74KC +cpu CPU_MIPS74K makeoptions KERNLOADADDR=0x80050000 options HZ=1000 options BREAK_TO_DEBUGGER options ALT_BREAK_TO_DEBUGGER # options BOOTVERBOSE=10 files "../atheros/files.ar71xx" hints "QCA955X_BASE.hints" makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols # makeoptions MODULES_OVERRIDE="gpio ar71xx if_gif if_gre if_bridge bridgestp usb wlan wlan_xauth wlan_acl wlan_wep wlan_tkip wlan_ccmp wlan_rssadapt wlan_amrr ath ath_ahb hwpmc" makeoptions MODULES_OVERRIDE="if_vlan ipfw if_gre if_gif if_bridge bridgestp" options DDB options KDB options ALQ options SCHED_4BSD #4BSD scheduler options INET #InterNETworking #options INET6 #InterNETworking #options NFSCL #Network Filesystem Client options PSEUDOFS #Pseudo-filesystem framework options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions # Don't include the SCSI/CAM strings in the default build options SCSI_NO_SENSE_STRINGS options SCSI_NO_OP_STRINGS # .. And no sysctl strings options NO_SYSCTL_DESCR # Limit IO size options NBUF=128 # Limit UMTX hash size # options UMTX_NUM_CHAINS=64 # PMC - fow now there's no hwpmc module for mips74k #options HWPMC_HOOKS #device hwpmc #device hwpmc_mips74k # options NFS_LEGACYRPC # Debugging for use in -current #options INVARIANTS #options INVARIANT_SUPPORT #options WITNESS #options WITNESS_SKIPSPIN options FFS #Berkeley Fast Filesystem #options SOFTUPDATES #Enable FFS soft updates support #options UFS_ACL #Support for access control lists #options UFS_DIRHASH #Improve performance on big directories options NO_FFS_SNAPSHOT # We don't require snapshot support # Wireless NIC cards options IEEE80211_DEBUG options IEEE80211_SUPPORT_MESH options IEEE80211_SUPPORT_TDMA options IEEE80211_SUPPORT_SUPERG options IEEE80211_ALQ # 802.11 ALQ logging support device wlan # 802.11 support device wlan_wep # 802.11 WEP support device wlan_ccmp # 802.11 CCMP support device wlan_tkip # 802.11 TKIP support device wlan_xauth # 802.11 hostap support # ath(4) device ath # Atheros network device device ath_rate_sample device ath_ahb # Atheros host bus glue options ATH_DEBUG options ATH_DIAGAPI option ATH_ENABLE_11N option AH_DEBUG_ALQ #device ath_hal device ath_ar9300 # AR9330 HAL; no need for the others option AH_DEBUG option AH_SUPPORT_AR5416 # 11n HAL support option AH_SUPPORT_QCA9550 # Chipset support option AH_DEBUG_ALQ option AH_AR5416_INTERRUPT_MITIGATION device mii device arge options ARGE_DEBUG device usb options USB_EHCI_BIG_ENDIAN_DESC # handle big-endian byte order options USB_DEBUG options USB_HOST_ALIGN=32 # AR71XX (MIPS in general?) requires this device ehci device scbus device umass device da device spibus device ar71xx_spi device mx25l device ar71xx_wdog device uart device uart_ar71xx device ar71xx_apb # Until some better interrupt handling is shoehorned into qca955x_apb, # we'll have to stick to shared interrupts for IP2/IP3 demux. # device qca955x_apb device loop device ether device md device bpf device random device if_bridge device gpio device gpioled #options KTR #options KTR_MASK=(KTR_INTR) #options KTR_COMPILE=(KTR_INTR) #options KTR_VERBOSE Index: head/sys/mips/include/asm.h =================================================================== --- head/sys/mips/include/asm.h (revision 295137) +++ head/sys/mips/include/asm.h (revision 295138) @@ -1,711 +1,711 @@ /* $NetBSD: asm.h,v 1.29 2000/12/14 21:29:51 jeffs Exp $ */ /* * Copyright (c) 1992, 1993 * The Regents of the University of California. All rights reserved. * * This code is derived from software contributed to Berkeley by * Ralph Campbell. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * @(#)machAsmDefs.h 8.1 (Berkeley) 6/10/93 * JNPR: asm.h,v 1.10 2007/08/09 11:23:32 katta * $FreeBSD$ */ /* * machAsmDefs.h -- * * Macros used when writing assembler programs. * * Copyright (C) 1989 Digital Equipment Corporation. * Permission to use, copy, modify, and distribute this software and * its documentation for any purpose and without fee is hereby granted, * provided that the above copyright notice appears in all copies. * Digital Equipment Corporation makes no representations about the * suitability of this software for any purpose. It is provided "as is" * without express or implied warranty. * * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsmDefs.h, * v 1.2 89/08/15 18:28:24 rab Exp SPRITE (DECWRL) */ #ifndef _MACHINE_ASM_H_ #define _MACHINE_ASM_H_ #include #include #include #undef __FBSDID #if !defined(lint) && !defined(STRIP_FBSDID) #define __FBSDID(s) .ident s #else #define __FBSDID(s) /* nothing */ #endif /* * Define -pg profile entry code. * Must always be noreorder, must never use a macro instruction * Final addiu to t9 must always equal the size of this _KERN_MCOUNT */ #define _KERN_MCOUNT \ .set push; \ .set noreorder; \ .set noat; \ subu sp,sp,16; \ sw t9,12(sp); \ move AT,ra; \ lui t9,%hi(_mcount); \ addiu t9,t9,%lo(_mcount); \ jalr t9; \ nop; \ lw t9,4(sp); \ addiu sp,sp,8; \ addiu t9,t9,40; \ .set pop; #ifdef GPROF #define MCOUNT _KERN_MCOUNT #else #define MCOUNT #endif #define _C_LABEL(x) x #ifdef USE_AENT #define AENT(x) \ .aent x, 0 #else #define AENT(x) #endif /* * WARN_REFERENCES: create a warning if the specified symbol is referenced */ #define WARN_REFERENCES(_sym,_msg) \ .section .gnu.warning. ## _sym ; .ascii _msg ; .text #ifdef __ELF__ # define _C_LABEL(x) x #else # define _C_LABEL(x) _ ## x #endif /* * WEAK_ALIAS: create a weak alias. */ #define WEAK_ALIAS(alias,sym) \ .weak alias; \ alias = sym /* * STRONG_ALIAS: create a strong alias. */ #define STRONG_ALIAS(alias,sym) \ .globl alias; \ alias = sym #define GLOBAL(sym) \ .globl sym; sym: #define ENTRY(sym) \ .text; .globl sym; .ent sym; sym: #define ASM_ENTRY(sym) \ .text; .globl sym; .type sym,@function; sym: /* * LEAF * A leaf routine does * - call no other function, * - never use any register that callee-saved (S0-S8), and * - not use any local stack storage. */ #define LEAF(x) \ .globl _C_LABEL(x); \ .ent _C_LABEL(x), 0; \ _C_LABEL(x): ; \ .frame sp, 0, ra; \ MCOUNT /* * LEAF_NOPROFILE * No profilable leaf routine. */ #define LEAF_NOPROFILE(x) \ .globl _C_LABEL(x); \ .ent _C_LABEL(x), 0; \ _C_LABEL(x): ; \ .frame sp, 0, ra /* * XLEAF * declare alternate entry to leaf routine */ #define XLEAF(x) \ .globl _C_LABEL(x); \ AENT (_C_LABEL(x)); \ _C_LABEL(x): /* * NESTED * A function calls other functions and needs * therefore stack space to save/restore registers. */ #define NESTED(x, fsize, retpc) \ .globl _C_LABEL(x); \ .ent _C_LABEL(x), 0; \ _C_LABEL(x): ; \ .frame sp, fsize, retpc; \ MCOUNT /* * NESTED_NOPROFILE(x) * No profilable nested routine. */ #define NESTED_NOPROFILE(x, fsize, retpc) \ .globl _C_LABEL(x); \ .ent _C_LABEL(x), 0; \ _C_LABEL(x): ; \ .frame sp, fsize, retpc /* * XNESTED * declare alternate entry point to nested routine. */ #define XNESTED(x) \ .globl _C_LABEL(x); \ AENT (_C_LABEL(x)); \ _C_LABEL(x): /* * END * Mark end of a procedure. */ #define END(x) \ .end _C_LABEL(x) /* * IMPORT -- import external symbol */ #define IMPORT(sym, size) \ .extern _C_LABEL(sym),size /* * EXPORT -- export definition of symbol */ #define EXPORT(x) \ .globl _C_LABEL(x); \ _C_LABEL(x): /* * VECTOR * exception vector entrypoint * XXX: regmask should be used to generate .mask */ #define VECTOR(x, regmask) \ .ent _C_LABEL(x),0; \ EXPORT(x); \ #define VECTOR_END(x) \ EXPORT(x ## End); \ END(x) /* * Macros to panic and printf from assembly language. */ #define PANIC(msg) \ PTR_LA a0, 9f; \ jal _C_LABEL(panic); \ nop; \ MSG(msg) #define PANIC_KSEG0(msg, reg) PANIC(msg) #define PRINTF(msg) \ PTR_LA a0, 9f; \ jal _C_LABEL(printf); \ nop; \ MSG(msg) #define MSG(msg) \ .rdata; \ 9: .asciiz msg; \ .text #define ASMSTR(str) \ .asciiz str; \ .align 3 #if defined(__mips_o32) #define SZREG 4 #else #define SZREG 8 #endif #if defined(__mips_o32) || defined(__mips_o64) #define ALSK 7 /* stack alignment */ #define ALMASK -7 /* stack alignment */ #define SZFPREG 4 #define FP_L lwc1 #define FP_S swc1 #else #define ALSK 15 /* stack alignment */ #define ALMASK -15 /* stack alignment */ #define SZFPREG 8 #define FP_L ldc1 #define FP_S sdc1 #endif /* * standard callframe { * register_t cf_pad[N]; o32/64 (N=0), n32 (N=1) n64 (N=1) * register_t cf_args[4]; arg0 - arg3 (only on o32 and o64) * register_t cf_gp; global pointer (only on n32 and n64) * register_t cf_sp; frame pointer * register_t cf_ra; return address * }; */ #if defined(__mips_o32) || defined(__mips_o64) #define CALLFRAME_SIZ (SZREG * (4 + 2)) #define CALLFRAME_S0 0 #elif defined(__mips_n32) || defined(__mips_n64) #define CALLFRAME_SIZ (SZREG * 4) #define CALLFRAME_S0 (CALLFRAME_SIZ - 4 * SZREG) #endif #ifndef _KERNEL #define CALLFRAME_GP (CALLFRAME_SIZ - 3 * SZREG) #endif #define CALLFRAME_SP (CALLFRAME_SIZ - 2 * SZREG) #define CALLFRAME_RA (CALLFRAME_SIZ - 1 * SZREG) /* * Endian-independent assembly-code aliases for unaligned memory accesses. */ #if _BYTE_ORDER == _LITTLE_ENDIAN # define LWHI lwr # define LWLO lwl # define SWHI swr # define SWLO swl # if SZREG == 4 # define REG_LHI lwr # define REG_LLO lwl # define REG_SHI swr # define REG_SLO swl # else # define REG_LHI ldr # define REG_LLO ldl # define REG_SHI sdr # define REG_SLO sdl # endif #endif #if _BYTE_ORDER == _BIG_ENDIAN # define LWHI lwl # define LWLO lwr # define SWHI swl # define SWLO swr # if SZREG == 4 # define REG_LHI lwl # define REG_LLO lwr # define REG_SHI swl # define REG_SLO swr # else # define REG_LHI ldl # define REG_LLO ldr # define REG_SHI sdl # define REG_SLO sdr # endif #endif /* * While it would be nice to be compatible with the SGI * REG_L and REG_S macros, because they do not take parameters, it * is impossible to use them with the _MIPS_SIM_ABIX32 model. * * These macros hide the use of mips3 instructions from the * assembler to prevent the assembler from generating 64-bit style * ABI calls. */ #if _MIPS_SZPTR == 32 #define PTR_ADD add #define PTR_ADDI addi #define PTR_ADDU addu #define PTR_ADDIU addiu #define PTR_SUB add #define PTR_SUBI subi #define PTR_SUBU subu #define PTR_SUBIU subu #define PTR_L lw #define PTR_LA la #define PTR_LI li #define PTR_S sw #define PTR_SLL sll #define PTR_SLLV sllv #define PTR_SRL srl #define PTR_SRLV srlv #define PTR_SRA sra #define PTR_SRAV srav #define PTR_LL ll #define PTR_SC sc #define PTR_WORD .word #define PTR_SCALESHIFT 2 #else /* _MIPS_SZPTR == 64 */ #define PTR_ADD dadd #define PTR_ADDI daddi #define PTR_ADDU daddu #define PTR_ADDIU daddiu #define PTR_SUB dadd #define PTR_SUBI dsubi #define PTR_SUBU dsubu #define PTR_SUBIU dsubu #define PTR_L ld #define PTR_LA dla #define PTR_LI dli #define PTR_S sd #define PTR_SLL dsll #define PTR_SLLV dsllv #define PTR_SRL dsrl #define PTR_SRLV dsrlv #define PTR_SRA dsra #define PTR_SRAV dsrav #define PTR_LL lld #define PTR_SC scd #define PTR_WORD .dword #define PTR_SCALESHIFT 3 #endif /* _MIPS_SZPTR == 64 */ #if _MIPS_SZINT == 32 #define INT_ADD add #define INT_ADDI addi #define INT_ADDU addu #define INT_ADDIU addiu #define INT_SUB add #define INT_SUBI subi #define INT_SUBU subu #define INT_SUBIU subu #define INT_L lw #define INT_LA la #define INT_S sw #define INT_SLL sll #define INT_SLLV sllv #define INT_SRL srl #define INT_SRLV srlv #define INT_SRA sra #define INT_SRAV srav #define INT_LL ll #define INT_SC sc #define INT_WORD .word #define INT_SCALESHIFT 2 #else #define INT_ADD dadd #define INT_ADDI daddi #define INT_ADDU daddu #define INT_ADDIU daddiu #define INT_SUB dadd #define INT_SUBI dsubi #define INT_SUBU dsubu #define INT_SUBIU dsubu #define INT_L ld #define INT_LA dla #define INT_S sd #define INT_SLL dsll #define INT_SLLV dsllv #define INT_SRL dsrl #define INT_SRLV dsrlv #define INT_SRA dsra #define INT_SRAV dsrav #define INT_LL lld #define INT_SC scd #define INT_WORD .dword #define INT_SCALESHIFT 3 #endif #if _MIPS_SZLONG == 32 #define LONG_ADD add #define LONG_ADDI addi #define LONG_ADDU addu #define LONG_ADDIU addiu #define LONG_SUB add #define LONG_SUBI subi #define LONG_SUBU subu #define LONG_SUBIU subu #define LONG_L lw #define LONG_LA la #define LONG_S sw #define LONG_SLL sll #define LONG_SLLV sllv #define LONG_SRL srl #define LONG_SRLV srlv #define LONG_SRA sra #define LONG_SRAV srav #define LONG_LL ll #define LONG_SC sc #define LONG_WORD .word #define LONG_SCALESHIFT 2 #else #define LONG_ADD dadd #define LONG_ADDI daddi #define LONG_ADDU daddu #define LONG_ADDIU daddiu #define LONG_SUB dadd #define LONG_SUBI dsubi #define LONG_SUBU dsubu #define LONG_SUBIU dsubu #define LONG_L ld #define LONG_LA dla #define LONG_S sd #define LONG_SLL dsll #define LONG_SLLV dsllv #define LONG_SRL dsrl #define LONG_SRLV dsrlv #define LONG_SRA dsra #define LONG_SRAV dsrav #define LONG_LL lld #define LONG_SC scd #define LONG_WORD .dword #define LONG_SCALESHIFT 3 #endif #if SZREG == 4 #define REG_L lw #define REG_S sw #define REG_LI li #define REG_ADDU addu #define REG_SLL sll #define REG_SLLV sllv #define REG_SRL srl #define REG_SRLV srlv #define REG_SRA sra #define REG_SRAV srav #define REG_LL ll #define REG_SC sc #define REG_SCALESHIFT 2 #else #define REG_L ld #define REG_S sd #define REG_LI dli #define REG_ADDU daddu #define REG_SLL dsll #define REG_SLLV dsllv #define REG_SRL dsrl #define REG_SRLV dsrlv #define REG_SRA dsra #define REG_SRAV dsrav #define REG_LL lld #define REG_SC scd #define REG_SCALESHIFT 3 #endif #if _MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2 || \ _MIPS_ISA == _MIPS_ISA_MIPS32 #define MFC0 mfc0 #define MTC0 mtc0 #endif #if _MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4 || \ _MIPS_ISA == _MIPS_ISA_MIPS64 #define MFC0 dmfc0 #define MTC0 dmtc0 #endif #if defined(__mips_o32) || defined(__mips_o64) #ifdef __ABICALLS__ #define CPRESTORE(r) .cprestore r #define CPLOAD(r) .cpload r #else #define CPRESTORE(r) /* not needed */ #define CPLOAD(r) /* not needed */ #endif #define SETUP_GP \ .set push; \ .set noreorder; \ .cpload t9; \ .set pop #define SETUP_GPX(r) \ .set push; \ .set noreorder; \ move r,ra; /* save old ra */ \ bal 7f; \ nop; \ 7: .cpload ra; \ move ra,r; \ .set pop #define SETUP_GPX_L(r,lbl) \ .set push; \ .set noreorder; \ move r,ra; /* save old ra */ \ bal lbl; \ nop; \ lbl: .cpload ra; \ move ra,r; \ .set pop #define SAVE_GP(x) .cprestore x #define SETUP_GP64(a,b) /* n32/n64 specific */ #define SETUP_GP64_R(a,b) /* n32/n64 specific */ #define SETUP_GPX64(a,b) /* n32/n64 specific */ #define SETUP_GPX64_L(a,b,c) /* n32/n64 specific */ #define RESTORE_GP64 /* n32/n64 specific */ #define USE_ALT_CP(a) /* n32/n64 specific */ #endif /* __mips_o32 || __mips_o64 */ #if defined(__mips_o32) || defined(__mips_o64) #define REG_PROLOGUE .set push #define REG_EPILOGUE .set pop #endif #if defined(__mips_n32) || defined(__mips_n64) #define REG_PROLOGUE .set push ; .set mips3 #define REG_EPILOGUE .set pop #endif #if defined(__mips_n32) || defined(__mips_n64) #define SETUP_GP /* o32 specific */ #define SETUP_GPX(r) /* o32 specific */ #define SETUP_GPX_L(r,lbl) /* o32 specific */ #define SAVE_GP(x) /* o32 specific */ #define SETUP_GP64(a,b) .cpsetup $25, a, b #define SETUP_GPX64(a,b) \ .set push; \ move b,ra; \ .set noreorder; \ bal 7f; \ nop; \ 7: .set pop; \ .cpsetup ra, a, 7b; \ move ra,b #define SETUP_GPX64_L(a,b,c) \ .set push; \ move b,ra; \ .set noreorder; \ bal c; \ nop; \ c: .set pop; \ .cpsetup ra, a, c; \ move ra,b #define RESTORE_GP64 .cpreturn #define USE_ALT_CP(a) .cplocal a #endif /* __mips_n32 || __mips_n64 */ #define GET_CPU_PCPU(reg) \ PTR_L reg, _C_LABEL(pcpup); /* * Description of the setjmp buffer * * word 0 magic number (dependant on creator) * 1 RA * 2 S0 * 3 S1 * 4 S2 * 5 S3 * 6 S4 * 7 S5 * 8 S6 * 9 S7 * 10 SP * 11 S8 * 12 GP (dependent on ABI) * 13 signal mask (dependant on magic) * 14 (con't) * 15 (con't) * 16 (con't) * * The magic number number identifies the jmp_buf and * how the buffer was created as well as providing * a sanity check * */ #define _JB_MAGIC__SETJMP 0xBADFACED #define _JB_MAGIC_SETJMP 0xFACEDBAD /* Valid for all jmp_buf's */ #define _JB_MAGIC 0 #define _JB_REG_RA 1 #define _JB_REG_S0 2 #define _JB_REG_S1 3 #define _JB_REG_S2 4 #define _JB_REG_S3 5 #define _JB_REG_S4 6 #define _JB_REG_S5 7 #define _JB_REG_S6 8 #define _JB_REG_S7 9 #define _JB_REG_SP 10 #define _JB_REG_S8 11 #if defined(__mips_n32) || defined(__mips_n64) #define _JB_REG_GP 12 #endif /* Only valid with the _JB_MAGIC_SETJMP magic */ #define _JB_SIGMASK 13 #define __JB_SIGMASK_REMAINDER 14 /* sigmask_t is 128-bits */ #define _JB_FPREG_F20 15 #define _JB_FPREG_F21 16 #define _JB_FPREG_F22 17 #define _JB_FPREG_F23 18 #define _JB_FPREG_F24 19 #define _JB_FPREG_F25 20 #define _JB_FPREG_F26 21 #define _JB_FPREG_F27 22 #define _JB_FPREG_F28 23 #define _JB_FPREG_F29 24 #define _JB_FPREG_F30 25 #define _JB_FPREG_F31 26 #define _JB_FPREG_FCSR 27 /* * Various macros for dealing with TLB hazards * (a) why so many? * (b) when to use? * (c) why not used everywhere? */ /* * Assume that w alaways need nops to escape CP0 hazard * TODO: Make hazard delays configurable. Stuck with 5 cycles on the moment * For more info on CP0 hazards see Chapter 7 (p.99) of "MIPS32 Architecture * For Programmers Volume III: The MIPS32 Privileged Resource Architecture" */ #if defined(CPU_NLM) #define HAZARD_DELAY sll $0,3 #define ITLBNOPFIX sll $0,3 #elif defined(CPU_RMI) #define HAZARD_DELAY #define ITLBNOPFIX -#elif defined(CPU_MIPS74KC) +#elif defined(CPU_MIPS74K) #define HAZARD_DELAY sll $0,$0,3 #define ITLBNOPFIX sll $0,$0,3 #else #define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;sll $0,$0,3; #define HAZARD_DELAY nop;nop;nop;nop;sll $0,$0,3; #endif #endif /* !_MACHINE_ASM_H_ */ Index: head/sys/mips/include/cpufunc.h =================================================================== --- head/sys/mips/include/cpufunc.h (revision 295137) +++ head/sys/mips/include/cpufunc.h (revision 295138) @@ -1,374 +1,374 @@ /* $OpenBSD: pio.h,v 1.2 1998/09/15 10:50:12 pefo Exp $ */ /*- * Copyright (c) 2002-2004 Juli Mallett. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Copyright (c) 1995-1999 Per Fogelstrom. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Per Fogelstrom. * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * JNPR: cpufunc.h,v 1.5 2007/08/09 11:23:32 katta * $FreeBSD$ */ #ifndef _MACHINE_CPUFUNC_H_ #define _MACHINE_CPUFUNC_H_ #include #include /* * These functions are required by user-land atomi ops */ static __inline void mips_barrier(void) { #if defined(CPU_CNMIPS) || defined(CPU_RMI) || defined(CPU_NLM) __compiler_membar(); #else __asm __volatile (".set noreorder\n\t" "nop\n\t" "nop\n\t" "nop\n\t" "nop\n\t" "nop\n\t" "nop\n\t" "nop\n\t" "nop\n\t" ".set reorder\n\t" : : : "memory"); #endif } static __inline void mips_cp0_sync(void) { __asm __volatile (__XSTRING(COP0_SYNC)); } static __inline void mips_wbflush(void) { #if defined(CPU_CNMIPS) __asm __volatile (".set noreorder\n\t" "syncw\n\t" ".set reorder\n" : : : "memory"); #else __asm __volatile ("sync" : : : "memory"); mips_barrier(); #endif } #ifdef _KERNEL /* * XXX * It would be nice to add variants that read/write register_t, to avoid some * ABI checks. */ #if defined(__mips_n32) || defined(__mips_n64) #define MIPS_RW64_COP0(n,r) \ static __inline uint64_t \ mips_rd_ ## n (void) \ { \ int v0; \ __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)";" \ : [v0] "=&r"(v0)); \ mips_barrier(); \ return (v0); \ } \ static __inline void \ mips_wr_ ## n (uint64_t a0) \ { \ __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)";" \ __XSTRING(COP0_SYNC)";" \ "nop;" \ "nop;" \ : \ : [a0] "r"(a0)); \ mips_barrier(); \ } struct __hack #define MIPS_RW64_COP0_SEL(n,r,s) \ static __inline uint64_t \ mips_rd_ ## n(void) \ { \ int v0; \ __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \ : [v0] "=&r"(v0)); \ mips_barrier(); \ return (v0); \ } \ static __inline void \ mips_wr_ ## n(uint64_t a0) \ { \ __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \ __XSTRING(COP0_SYNC)";" \ : \ : [a0] "r"(a0)); \ mips_barrier(); \ } struct __hack #if defined(__mips_n64) MIPS_RW64_COP0(excpc, MIPS_COP_0_EXC_PC); MIPS_RW64_COP0(entryhi, MIPS_COP_0_TLB_HI); MIPS_RW64_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK); #ifdef CPU_CNMIPS MIPS_RW64_COP0_SEL(cvmcount, MIPS_COP_0_COUNT, 6); MIPS_RW64_COP0_SEL(cvmctl, MIPS_COP_0_COUNT, 7); MIPS_RW64_COP0_SEL(cvmmemctl, MIPS_COP_0_COMPARE, 7); MIPS_RW64_COP0_SEL(icache_err, MIPS_COP_0_CACHE_ERR, 0); MIPS_RW64_COP0_SEL(dcache_err, MIPS_COP_0_CACHE_ERR, 1); #endif #endif #if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */ MIPS_RW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0); MIPS_RW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1); #endif MIPS_RW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT); #undef MIPS_RW64_COP0 #undef MIPS_RW64_COP0_SEL #endif #define MIPS_RW32_COP0(n,r) \ static __inline uint32_t \ mips_rd_ ## n (void) \ { \ int v0; \ __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)";" \ : [v0] "=&r"(v0)); \ mips_barrier(); \ return (v0); \ } \ static __inline void \ mips_wr_ ## n (uint32_t a0) \ { \ __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)";" \ __XSTRING(COP0_SYNC)";" \ "nop;" \ "nop;" \ : \ : [a0] "r"(a0)); \ mips_barrier(); \ } struct __hack #define MIPS_RW32_COP0_SEL(n,r,s) \ static __inline uint32_t \ mips_rd_ ## n(void) \ { \ int v0; \ __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \ : [v0] "=&r"(v0)); \ mips_barrier(); \ return (v0); \ } \ static __inline void \ mips_wr_ ## n(uint32_t a0) \ { \ __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \ __XSTRING(COP0_SYNC)";" \ "nop;" \ "nop;" \ : \ : [a0] "r"(a0)); \ mips_barrier(); \ } struct __hack #ifdef CPU_CNMIPS static __inline void mips_sync_icache (void) { __asm __volatile ( ".set push\n" ".set mips64\n" ".word 0x041f0000\n" /* xxx ICACHE */ "nop\n" ".set pop\n" : : ); } #endif MIPS_RW32_COP0(compare, MIPS_COP_0_COMPARE); MIPS_RW32_COP0(config, MIPS_COP_0_CONFIG); MIPS_RW32_COP0_SEL(config1, MIPS_COP_0_CONFIG, 1); MIPS_RW32_COP0_SEL(config2, MIPS_COP_0_CONFIG, 2); MIPS_RW32_COP0_SEL(config3, MIPS_COP_0_CONFIG, 3); #ifdef CPU_CNMIPS MIPS_RW32_COP0_SEL(config4, MIPS_COP_0_CONFIG, 4); #endif #ifdef BERI_LARGE_TLB MIPS_RW32_COP0_SEL(config5, MIPS_COP_0_CONFIG, 5); #endif #if defined(CPU_NLM) || defined(BERI_LARGE_TLB) MIPS_RW32_COP0_SEL(config6, MIPS_COP_0_CONFIG, 6); #endif -#if defined(CPU_NLM) || defined(CPU_MIPS1004KC) +#if defined(CPU_NLM) || defined(CPU_MIPS1004K) MIPS_RW32_COP0_SEL(config7, MIPS_COP_0_CONFIG, 7); #endif MIPS_RW32_COP0(count, MIPS_COP_0_COUNT); MIPS_RW32_COP0(index, MIPS_COP_0_TLB_INDEX); MIPS_RW32_COP0(wired, MIPS_COP_0_TLB_WIRED); MIPS_RW32_COP0(cause, MIPS_COP_0_CAUSE); #if !defined(__mips_n64) MIPS_RW32_COP0(excpc, MIPS_COP_0_EXC_PC); #endif MIPS_RW32_COP0(status, MIPS_COP_0_STATUS); MIPS_RW32_COP0_SEL(cmgcrbase, 15, 3); /* XXX: Some of these registers are specific to MIPS32. */ #if !defined(__mips_n64) MIPS_RW32_COP0(entryhi, MIPS_COP_0_TLB_HI); MIPS_RW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK); #endif #ifdef CPU_NLM MIPS_RW32_COP0_SEL(pagegrain, MIPS_COP_0_TLB_PG_MASK, 1); #endif #if !defined(__mips_n64) && !defined(__mips_n32) /* !PHYSADDR_64_BIT */ MIPS_RW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0); MIPS_RW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1); #endif MIPS_RW32_COP0(prid, MIPS_COP_0_PRID); /* XXX 64-bit? */ MIPS_RW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1); MIPS_RW32_COP0(watchlo, MIPS_COP_0_WATCH_LO); MIPS_RW32_COP0_SEL(watchlo1, MIPS_COP_0_WATCH_LO, 1); MIPS_RW32_COP0_SEL(watchlo2, MIPS_COP_0_WATCH_LO, 2); MIPS_RW32_COP0_SEL(watchlo3, MIPS_COP_0_WATCH_LO, 3); MIPS_RW32_COP0(watchhi, MIPS_COP_0_WATCH_HI); MIPS_RW32_COP0_SEL(watchhi1, MIPS_COP_0_WATCH_HI, 1); MIPS_RW32_COP0_SEL(watchhi2, MIPS_COP_0_WATCH_HI, 2); MIPS_RW32_COP0_SEL(watchhi3, MIPS_COP_0_WATCH_HI, 3); MIPS_RW32_COP0_SEL(perfcnt0, MIPS_COP_0_PERFCNT, 0); MIPS_RW32_COP0_SEL(perfcnt1, MIPS_COP_0_PERFCNT, 1); MIPS_RW32_COP0_SEL(perfcnt2, MIPS_COP_0_PERFCNT, 2); MIPS_RW32_COP0_SEL(perfcnt3, MIPS_COP_0_PERFCNT, 3); #undef MIPS_RW32_COP0 #undef MIPS_RW32_COP0_SEL static __inline register_t intr_disable(void) { register_t s; s = mips_rd_status(); mips_wr_status(s & ~MIPS_SR_INT_IE); return (s & MIPS_SR_INT_IE); } static __inline register_t intr_enable(void) { register_t s; s = mips_rd_status(); mips_wr_status(s | MIPS_SR_INT_IE); return (s); } static __inline void intr_restore(register_t ie) { if (ie == MIPS_SR_INT_IE) { intr_enable(); } } static __inline uint32_t set_intr_mask(uint32_t mask) { uint32_t ostatus; ostatus = mips_rd_status(); mask = (ostatus & ~MIPS_SR_INT_MASK) | (mask & MIPS_SR_INT_MASK); mips_wr_status(mask); return (ostatus); } static __inline uint32_t get_intr_mask(void) { return (mips_rd_status() & MIPS_SR_INT_MASK); } static __inline void breakpoint(void) { __asm __volatile ("break"); } #if defined(__GNUC__) && !defined(__mips_o32) #define mips3_ld(a) (*(const volatile uint64_t *)(a)) #define mips3_sd(a, v) (*(volatile uint64_t *)(a) = (v)) #else uint64_t mips3_ld(volatile uint64_t *va); void mips3_sd(volatile uint64_t *, uint64_t); #endif /* __GNUC__ */ #endif /* _KERNEL */ #define readb(va) (*(volatile uint8_t *) (va)) #define readw(va) (*(volatile uint16_t *) (va)) #define readl(va) (*(volatile uint32_t *) (va)) #if defined(__GNUC__) && !defined(__mips_o32) #define readq(a) (*(volatile uint64_t *)(a)) #endif #define writeb(va, d) (*(volatile uint8_t *) (va) = (d)) #define writew(va, d) (*(volatile uint16_t *) (va) = (d)) #define writel(va, d) (*(volatile uint32_t *) (va) = (d)) #if defined(__GNUC__) && !defined(__mips_o32) #define writeq(va, d) (*(volatile uint64_t *) (va) = (d)) #endif #endif /* !_MACHINE_CPUFUNC_H_ */ Index: head/sys/mips/include/cpuregs.h =================================================================== --- head/sys/mips/include/cpuregs.h (revision 295137) +++ head/sys/mips/include/cpuregs.h (revision 295138) @@ -1,648 +1,648 @@ /* $NetBSD: cpuregs.h,v 1.70 2006/05/15 02:26:54 simonb Exp $ */ /* * Copyright (c) 1992, 1993 * The Regents of the University of California. All rights reserved. * * This code is derived from software contributed to Berkeley by * Ralph Campbell and Rick Macklem. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * @(#)machConst.h 8.1 (Berkeley) 6/10/93 * * machConst.h -- * * Machine dependent constants. * * Copyright (C) 1989 Digital Equipment Corporation. * Permission to use, copy, modify, and distribute this software and * its documentation for any purpose and without fee is hereby granted, * provided that the above copyright notice appears in all copies. * Digital Equipment Corporation makes no representations about the * suitability of this software for any purpose. It is provided "as is" * without express or implied warranty. * * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) * * $FreeBSD$ */ #ifndef _MIPS_CPUREGS_H_ #define _MIPS_CPUREGS_H_ /* * Address space. * 32-bit mips CPUS partition their 32-bit address space into four segments: * * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped * * Caching of mapped addresses is controlled by bits in the TLB entry. */ #define MIPS_KSEG0_LARGEST_PHYS (0x20000000) #define MIPS_KSEG0_PHYS_MASK (0x1fffffff) #define MIPS_XKPHYS_LARGEST_PHYS (0x10000000000) /* 40 bit PA */ #define MIPS_XKPHYS_PHYS_MASK (0x0ffffffffff) #ifndef LOCORE #define MIPS_KUSEG_START 0x00000000 #define MIPS_KSEG0_START ((intptr_t)(int32_t)0x80000000) #define MIPS_KSEG0_END ((intptr_t)(int32_t)0x9fffffff) #define MIPS_KSEG1_START ((intptr_t)(int32_t)0xa0000000) #define MIPS_KSEG1_END ((intptr_t)(int32_t)0xbfffffff) #define MIPS_KSSEG_START ((intptr_t)(int32_t)0xc0000000) #define MIPS_KSSEG_END ((intptr_t)(int32_t)0xdfffffff) #define MIPS_KSEG3_START ((intptr_t)(int32_t)0xe0000000) #define MIPS_KSEG3_END ((intptr_t)(int32_t)0xffffffff) #define MIPS_KSEG2_START MIPS_KSSEG_START #define MIPS_KSEG2_END MIPS_KSSEG_END #endif #define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | MIPS_KSEG0_START) #define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | MIPS_KSEG1_START) #define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK) #define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK) #define MIPS_IS_KSEG0_ADDR(x) \ (((vm_offset_t)(x) >= MIPS_KSEG0_START) && \ ((vm_offset_t)(x) <= MIPS_KSEG0_END)) #define MIPS_IS_KSEG1_ADDR(x) \ (((vm_offset_t)(x) >= MIPS_KSEG1_START) && \ ((vm_offset_t)(x) <= MIPS_KSEG1_END)) #define MIPS_IS_VALID_PTR(x) (MIPS_IS_KSEG0_ADDR(x) || \ MIPS_IS_KSEG1_ADDR(x)) /* * Cache Coherency Attributes: * UC: Uncached. * UA: Uncached accelerated. * C: Cacheable, coherency unspecified. * CNC: Cacheable non-coherent. * CC: Cacheable coherent. * CCE: Cacheable coherent, exclusive read. * CCEW: Cacheable coherent, exclusive write. * CCUOW: Cacheable coherent, update on write. * * Note that some bits vary in meaning across implementations (and that the * listing here is no doubt incomplete) and that the optimal cached mode varies * between implementations. 0x02 is required to be UC and 0x03 is required to * be a least C. * * We define the following logical bits: * UNCACHED: * The optimal uncached mode for the target CPU type. This must * be suitable for use in accessing memory-mapped devices. * CACHED: The optional cached mode for the target CPU type. */ #define MIPS_CCA_UC 0x02 /* Uncached. */ #define MIPS_CCA_C 0x03 /* Cacheable, coherency unspecified. */ #if defined(CPU_R4000) || defined(CPU_R10000) #define MIPS_CCA_CNC 0x03 #define MIPS_CCA_CCE 0x04 #define MIPS_CCA_CCEW 0x05 #ifdef CPU_R4000 #define MIPS_CCA_CCUOW 0x06 #endif #ifdef CPU_R10000 #define MIPS_CCA_UA 0x07 #endif #define MIPS_CCA_CACHED MIPS_CCA_CCEW #endif /* defined(CPU_R4000) || defined(CPU_R10000) */ #if defined(CPU_SB1) #define MIPS_CCA_CC 0x05 /* Cacheable Coherent. */ #endif -#if defined(CPU_MIPS74KC) +#if defined(CPU_MIPS74K) #define MIPS_CCA_UNCACHED 0x02 #define MIPS_CCA_CACHED 0x03 #endif -#if defined(CPU_MIPS1004KC) +#if defined(CPU_MIPS1004K) #define MIPS_CCA_UNCACHED 0x02 #define MIPS_CCA_CACHED 0x05 #endif #ifndef MIPS_CCA_UNCACHED #define MIPS_CCA_UNCACHED MIPS_CCA_UC #endif /* * If we don't know which cached mode to use and there is a cache coherent * mode, use it. If there is not a cache coherent mode, use the required * cacheable mode. */ #ifndef MIPS_CCA_CACHED #ifdef MIPS_CCA_CC #define MIPS_CCA_CACHED MIPS_CCA_CC #else #define MIPS_CCA_CACHED MIPS_CCA_C #endif #endif #define MIPS_PHYS_TO_XKPHYS(cca,x) \ ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x)) #define MIPS_PHYS_TO_XKPHYS_CACHED(x) \ ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_CACHED) << 59) | (x)) #define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \ ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_UNCACHED) << 59) | (x)) #define MIPS_XKPHYS_TO_PHYS(x) ((uintptr_t)(x) & MIPS_XKPHYS_PHYS_MASK) #define MIPS_XKPHYS_START 0x8000000000000000 #define MIPS_XKPHYS_END 0xbfffffffffffffff #define MIPS_XUSEG_START 0x0000000000000000 #define MIPS_XUSEG_END 0x0000010000000000 #define MIPS_XKSEG_START 0xc000000000000000 #define MIPS_XKSEG_END 0xc00000ff80000000 #define MIPS_XKSEG_COMPAT32_START 0xffffffff80000000 #define MIPS_XKSEG_COMPAT32_END 0xffffffffffffffff #define MIPS_XKSEG_TO_COMPAT32(va) ((va) & 0xffffffff) #ifdef __mips_n64 #define MIPS_DIRECT_MAPPABLE(pa) 1 #define MIPS_PHYS_TO_DIRECT(pa) MIPS_PHYS_TO_XKPHYS_CACHED(pa) #define MIPS_PHYS_TO_DIRECT_UNCACHED(pa) MIPS_PHYS_TO_XKPHYS_UNCACHED(pa) #define MIPS_DIRECT_TO_PHYS(va) MIPS_XKPHYS_TO_PHYS(va) #else #define MIPS_DIRECT_MAPPABLE(pa) ((pa) < MIPS_KSEG0_LARGEST_PHYS) #define MIPS_PHYS_TO_DIRECT(pa) MIPS_PHYS_TO_KSEG0(pa) #define MIPS_PHYS_TO_DIRECT_UNCACHED(pa) MIPS_PHYS_TO_KSEG1(pa) #define MIPS_DIRECT_TO_PHYS(va) MIPS_KSEG0_TO_PHYS(va) #endif /* CPU dependent mtc0 hazard hook */ #if defined(CPU_CNMIPS) || defined(CPU_RMI) #define COP0_SYNC #elif defined(CPU_NLM) #define COP0_SYNC .word 0xc0 /* ehb */ #elif defined(CPU_SB1) #define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop -#elif defined(CPU_MIPS74KC) || defined(CPU_MIPS1004KC) +#elif defined(CPU_MIPS74K) || defined(CPU_MIPS1004K) #define COP0_SYNC .word 0xc0 /* ehb */ #else /* * Pick a reasonable default based on the "typical" spacing described in the * "CP0 Hazards" chapter of MIPS Architecture Book Vol III. */ #define COP0_SYNC ssnop; ssnop; ssnop; ssnop; .word 0xc0; #endif #define COP0_HAZARD_FPUENABLE nop; nop; nop; nop; /* * The bits in the cause register. * * Bits common to r3000 and r4000: * * MIPS_CR_BR_DELAY Exception happened in branch delay slot. * MIPS_CR_COP_ERR Coprocessor error. * MIPS_CR_IP Interrupt pending bits defined below. * (same meaning as in CAUSE register). * MIPS_CR_EXC_CODE The exception type (see exception codes below). * * Differences: * r3k has 4 bits of execption type, r4k has 5 bits. */ #define MIPS_CR_BR_DELAY 0x80000000 #define MIPS_CR_COP_ERR 0x30000000 #define MIPS_CR_EXC_CODE 0x0000007C /* five bits */ #define MIPS_CR_IP 0x0000FF00 #define MIPS_CR_EXC_CODE_SHIFT 2 #define MIPS_CR_COP_ERR_SHIFT 28 /* * The bits in the status register. All bits are active when set to 1. * * R3000 status register fields: * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors. * MIPS_SR_TS TLB shutdown. * * MIPS_SR_INT_IE Master (current) interrupt enable bit. * * Differences: * r3k has cache control is via frobbing SR register bits, whereas the * r4k cache control is via explicit instructions. * r3k has a 3-entry stack of kernel/user bits, whereas the * r4k has kernel/supervisor/user. */ #define MIPS_SR_COP_USABILITY 0xf0000000 #define MIPS_SR_COP_0_BIT 0x10000000 #define MIPS_SR_COP_1_BIT 0x20000000 #define MIPS_SR_COP_2_BIT 0x40000000 /* r4k and r3k differences, see below */ #define MIPS_SR_MX 0x01000000 /* MIPS64 */ #define MIPS_SR_PX 0x00800000 /* MIPS64 */ #define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */ #define MIPS_SR_TS 0x00200000 #define MIPS_SR_DE 0x00010000 #define MIPS_SR_INT_IE 0x00000001 /*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ #define MIPS_SR_INT_MASK 0x0000ff00 /* * R4000 status register bit definitons, * where different from r2000/r3000. */ #define MIPS_SR_XX 0x80000000 #define MIPS_SR_RP 0x08000000 #define MIPS_SR_FR 0x04000000 #define MIPS_SR_RE 0x02000000 #define MIPS_SR_DIAG_DL 0x01000000 /* QED 52xx */ #define MIPS_SR_DIAG_IL 0x00800000 /* QED 52xx */ #define MIPS_SR_SR 0x00100000 #define MIPS_SR_NMI 0x00080000 /* MIPS32/64 */ #define MIPS_SR_DIAG_CH 0x00040000 #define MIPS_SR_DIAG_CE 0x00020000 #define MIPS_SR_DIAG_PE 0x00010000 #define MIPS_SR_EIE 0x00010000 /* TX79/R5900 */ #define MIPS_SR_KX 0x00000080 #define MIPS_SR_SX 0x00000040 #define MIPS_SR_UX 0x00000020 #define MIPS_SR_KSU_MASK 0x00000018 #define MIPS_SR_KSU_USER 0x00000010 #define MIPS_SR_KSU_SUPER 0x00000008 #define MIPS_SR_KSU_KERNEL 0x00000000 #define MIPS_SR_ERL 0x00000004 #define MIPS_SR_EXL 0x00000002 /* * The interrupt masks. * If a bit in the mask is 1 then the interrupt is enabled (or pending). */ #define MIPS_INT_MASK 0xff00 #define MIPS_INT_MASK_5 0x8000 #define MIPS_INT_MASK_4 0x4000 #define MIPS_INT_MASK_3 0x2000 #define MIPS_INT_MASK_2 0x1000 #define MIPS_INT_MASK_1 0x0800 #define MIPS_INT_MASK_0 0x0400 #define MIPS_HARD_INT_MASK 0xfc00 #define MIPS_SOFT_INT_MASK_1 0x0200 #define MIPS_SOFT_INT_MASK_0 0x0100 /* * The bits in the MIPS3 config register. * * bit 0..5: R/W, Bit 6..31: R/O */ /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ #define MIPS_CONFIG_K0_MASK 0x00000007 /* * R/W Update on Store Conditional * 0: Store Conditional uses coherency algorithm specified by TLB * 1: Store Conditional uses cacheable coherent update on write */ #define MIPS_CONFIG_CU 0x00000008 #define MIPS_CONFIG_DB 0x00000010 /* Primary D-cache line size */ #define MIPS_CONFIG_IB 0x00000020 /* Primary I-cache line size */ #define MIPS_CONFIG_CACHE_L1_LSIZE(config, bit) \ (((config) & (bit)) ? 32 : 16) #define MIPS_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */ #define MIPS_CONFIG_DC_SHIFT 6 #define MIPS_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */ #define MIPS_CONFIG_IC_SHIFT 9 #define MIPS_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */ /* Cache size mode indication: available only on Vr41xx CPUs */ #define MIPS_CONFIG_CS 0x00001000 #define MIPS_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */ #define MIPS_CONFIG_CACHE_SIZE(config, mask, base, shift) \ ((base) << (((config) & (mask)) >> (shift))) /* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */ #define MIPS_CONFIG_SE 0x00001000 /* Block ordering: 0: sequential, 1: sub-block */ #define MIPS_CONFIG_EB 0x00002000 /* ECC mode - 0: ECC mode, 1: parity mode */ #define MIPS_CONFIG_EM 0x00004000 /* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */ #define MIPS_CONFIG_BE 0x00008000 /* Dirty Shared coherency state - 0: enabled, 1: disabled */ #define MIPS_CONFIG_SM 0x00010000 /* Secondary Cache - 0: present, 1: not present */ #define MIPS_CONFIG_SC 0x00020000 /* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */ #define MIPS_CONFIG_EW_MASK 0x000c0000 #define MIPS_CONFIG_EW_SHIFT 18 /* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */ #define MIPS_CONFIG_SW 0x00100000 /* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */ #define MIPS_CONFIG_SS 0x00200000 /* Secondary Cache line size */ #define MIPS_CONFIG_SB_MASK 0x00c00000 #define MIPS_CONFIG_SB_SHIFT 22 #define MIPS_CONFIG_CACHE_L2_LSIZE(config) \ (0x10 << (((config) & MIPS_CONFIG_SB_MASK) >> MIPS_CONFIG_SB_SHIFT)) /* Write back data rate */ #define MIPS_CONFIG_EP_MASK 0x0f000000 #define MIPS_CONFIG_EP_SHIFT 24 /* System clock ratio - this value is CPU dependent */ #define MIPS_CONFIG_EC_MASK 0x70000000 #define MIPS_CONFIG_EC_SHIFT 28 /* Master-Checker Mode - 1: enabled */ #define MIPS_CONFIG_CM 0x80000000 /* * The bits in the MIPS4 config register. */ /* * Location of exception vectors. * * Common vectors: reset and UTLB miss. */ #define MIPS_RESET_EXC_VEC ((intptr_t)(int32_t)0xBFC00000) #define MIPS_UTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000000) /* * MIPS-III exception vectors */ #define MIPS_XTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000080) #define MIPS_CACHE_ERR_EXC_VEC ((intptr_t)(int32_t)0x80000100) #define MIPS_GEN_EXC_VEC ((intptr_t)(int32_t)0x80000180) /* * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector. */ #define MIPS_INTR_EXC_VEC 0x80000200 /* * Coprocessor 0 registers: * * v--- width for mips I,III,32,64 * (3=32bit, 6=64bit, i=impl dep) * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index. * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random. * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low. * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended. * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context. * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register. * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number. * 7 MIPS_COP_0_INFO ..33 Info registers * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address. * 9 MIPS_COP_0_COUNT .333 Count register. * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high. * 11 MIPS_COP_0_COMPARE .333 Compare (against Count). * 12 MIPS_COP_0_STATUS 3333 Status register. * 13 MIPS_COP_0_CAUSE 3333 Exception cause register. * 14 MIPS_COP_0_EXC_PC 3636 Exception PC. * 15 MIPS_COP_0_PRID 3333 Processor revision identifier. * 16 MIPS_COP_0_CONFIG 3333 Configuration register. * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1. * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2. * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3. * 16/4 MIPS_COP_0_CONFIG4 ..33 Configuration register 4. * 17 MIPS_COP_0_LLADDR .336 Load Linked Address. * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register. * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register. * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register. * 23 MIPS_COP_0_DEBUG .... Debug JTAG register. * 24 MIPS_COP_0_DEPC .... DEPC JTAG register. * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register. * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register. * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register. * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr). * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr). * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data). * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data). * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr). * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr). * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data). * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data). * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register. * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register. */ /* Deal with inclusion from an assembly file. */ #if defined(_LOCORE) || defined(LOCORE) #define _(n) $n #else #define _(n) n #endif #define MIPS_COP_0_TLB_INDEX _(0) #define MIPS_COP_0_TLB_RANDOM _(1) /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */ #define MIPS_COP_0_TLB_CONTEXT _(4) /* $5 and $6 new with MIPS-III */ #define MIPS_COP_0_BAD_VADDR _(8) #define MIPS_COP_0_TLB_HI _(10) #define MIPS_COP_0_STATUS _(12) #define MIPS_COP_0_CAUSE _(13) #define MIPS_COP_0_EXC_PC _(14) #define MIPS_COP_0_PRID _(15) /* MIPS-III */ #define MIPS_COP_0_TLB_LO0 _(2) #define MIPS_COP_0_TLB_LO1 _(3) #define MIPS_COP_0_TLB_PG_MASK _(5) #define MIPS_COP_0_TLB_WIRED _(6) #define MIPS_COP_0_COUNT _(9) #define MIPS_COP_0_COMPARE _(11) #define MIPS_COP_0_CONFIG _(16) #define MIPS_COP_0_LLADDR _(17) #define MIPS_COP_0_WATCH_LO _(18) #define MIPS_COP_0_WATCH_HI _(19) #define MIPS_COP_0_TLB_XCONTEXT _(20) #define MIPS_COP_0_ECC _(26) #define MIPS_COP_0_CACHE_ERR _(27) #define MIPS_COP_0_TAG_LO _(28) #define MIPS_COP_0_TAG_HI _(29) #define MIPS_COP_0_ERROR_PC _(30) /* MIPS32/64 */ #define MIPS_COP_0_INFO _(7) #define MIPS_COP_0_DEBUG _(23) #define MIPS_COP_0_DEPC _(24) #define MIPS_COP_0_PERFCNT _(25) #define MIPS_COP_0_DATA_LO _(28) #define MIPS_COP_0_DATA_HI _(29) #define MIPS_COP_0_DESAVE _(31) /* MIPS32 Config register definitions */ #define MIPS_MMU_NONE 0x00 /* No MMU present */ #define MIPS_MMU_TLB 0x01 /* Standard TLB */ #define MIPS_MMU_BAT 0x02 /* Standard BAT */ #define MIPS_MMU_FIXED 0x03 /* Standard fixed mapping */ #define MIPS_CONFIG0_MT_MASK 0x00000380 /* bits 9..7 MMU Type */ #define MIPS_CONFIG0_MT_SHIFT 7 #define MIPS_CONFIG0_BE 0x00008000 /* data is big-endian */ #define MIPS_CONFIG0_VI 0x00000008 /* instruction cache is virtual */ #define MIPS_CONFIG1_TLBSZ_MASK 0x7E000000 /* bits 30..25 # tlb entries minus one */ #define MIPS_CONFIG1_TLBSZ_SHIFT 25 #define MIPS_CONFIG1_IS_MASK 0x01C00000 /* bits 24..22 icache sets per way */ #define MIPS_CONFIG1_IS_SHIFT 22 #define MIPS_CONFIG1_IL_MASK 0x00380000 /* bits 21..19 icache line size */ #define MIPS_CONFIG1_IL_SHIFT 19 #define MIPS_CONFIG1_IA_MASK 0x00070000 /* bits 18..16 icache associativity */ #define MIPS_CONFIG1_IA_SHIFT 16 #define MIPS_CONFIG1_DS_MASK 0x0000E000 /* bits 15..13 dcache sets per way */ #define MIPS_CONFIG1_DS_SHIFT 13 #define MIPS_CONFIG1_DL_MASK 0x00001C00 /* bits 12..10 dcache line size */ #define MIPS_CONFIG1_DL_SHIFT 10 #define MIPS_CONFIG1_DA_MASK 0x00000380 /* bits 9.. 7 dcache associativity */ #define MIPS_CONFIG1_DA_SHIFT 7 #define MIPS_CONFIG1_LOWBITS 0x0000007F #define MIPS_CONFIG1_C2 0x00000040 /* Coprocessor 2 implemented */ #define MIPS_CONFIG1_MD 0x00000020 /* MDMX ASE implemented (MIPS64) */ #define MIPS_CONFIG1_PC 0x00000010 /* Performance counters implemented */ #define MIPS_CONFIG1_WR 0x00000008 /* Watch registers implemented */ #define MIPS_CONFIG1_CA 0x00000004 /* MIPS16e ISA implemented */ #define MIPS_CONFIG1_EP 0x00000002 /* EJTAG implemented */ #define MIPS_CONFIG1_FP 0x00000001 /* FPU implemented */ #define MIPS_CONFIG2_SA_SHIFT 0 /* Secondary cache associativity */ #define MIPS_CONFIG2_SA_MASK 0xf #define MIPS_CONFIG2_SL_SHIFT 4 /* Secondary cache line size */ #define MIPS_CONFIG2_SL_MASK 0xf #define MIPS_CONFIG2_SS_SHIFT 8 /* Secondary cache sets per way */ #define MIPS_CONFIG2_SS_MASK 0xf #define MIPS_CONFIG3_CMGCR_MASK (1 << 29) /* Coherence manager present */ #define MIPS_CONFIG4_MMUSIZEEXT 0x000000FF /* bits 7.. 0 MMU Size Extension */ #define MIPS_CONFIG4_MMUEXTDEF 0x0000C000 /* bits 15.14 MMU Extension Definition */ #define MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT 0x00004000 /* This values denotes CONFIG4 bits */ /* * Values for the code field in a break instruction. */ #define MIPS_BREAK_INSTR 0x0000000d #define MIPS_BREAK_VAL_MASK 0x03ff0000 #define MIPS_BREAK_VAL_SHIFT 16 #define MIPS_BREAK_KDB_VAL 512 #define MIPS_BREAK_SSTEP_VAL 513 #define MIPS_BREAK_BRKPT_VAL 514 #define MIPS_BREAK_SOVER_VAL 515 #define MIPS_BREAK_DDB_VAL 516 #define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \ (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT)) #define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \ (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT)) #define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \ (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT)) #define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \ (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT)) #define MIPS_BREAK_DDB (MIPS_BREAK_INSTR | \ (MIPS_BREAK_DDB_VAL << MIPS_BREAK_VAL_SHIFT)) /* * Mininum and maximum cache sizes. */ #define MIPS_MIN_CACHE_SIZE (16 * 1024) #define MIPS_MAX_CACHE_SIZE (256 * 1024) #define MIPS_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */ /* * The floating point version and status registers. */ #define MIPS_FPU_ID $0 #define MIPS_FPU_CSR $31 /* * The floating point coprocessor status register bits. */ #define MIPS_FPU_ROUNDING_BITS 0x00000003 #define MIPS_FPU_ROUND_RN 0x00000000 #define MIPS_FPU_ROUND_RZ 0x00000001 #define MIPS_FPU_ROUND_RP 0x00000002 #define MIPS_FPU_ROUND_RM 0x00000003 #define MIPS_FPU_STICKY_BITS 0x0000007c #define MIPS_FPU_STICKY_INEXACT 0x00000004 #define MIPS_FPU_STICKY_UNDERFLOW 0x00000008 #define MIPS_FPU_STICKY_OVERFLOW 0x00000010 #define MIPS_FPU_STICKY_DIV0 0x00000020 #define MIPS_FPU_STICKY_INVALID 0x00000040 #define MIPS_FPU_ENABLE_BITS 0x00000f80 #define MIPS_FPU_ENABLE_INEXACT 0x00000080 #define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100 #define MIPS_FPU_ENABLE_OVERFLOW 0x00000200 #define MIPS_FPU_ENABLE_DIV0 0x00000400 #define MIPS_FPU_ENABLE_INVALID 0x00000800 #define MIPS_FPU_EXCEPTION_BITS 0x0003f000 #define MIPS_FPU_EXCEPTION_INEXACT 0x00001000 #define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000 #define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000 #define MIPS_FPU_EXCEPTION_DIV0 0x00008000 #define MIPS_FPU_EXCEPTION_INVALID 0x00010000 #define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000 #define MIPS_FPU_COND_BIT 0x00800000 #define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ #define MIPS_FPC_MBZ_BITS 0xfe7c0000 /* * Constants to determine if have a floating point instruction. */ #define MIPS_OPCODE_SHIFT 26 #define MIPS_OPCODE_C1 0x11 /* Coherence manager constants */ #define MIPS_CMGCRB_BASE 11 #define MIPS_CMGCRF_BASE (~((1 << MIPS_CMGCRB_BASE) - 1)) #endif /* _MIPS_CPUREGS_H_ */