Index: head/sys/arm64/cavium/thunder_pcie.c =================================================================== --- head/sys/arm64/cavium/thunder_pcie.c (revision 294265) +++ head/sys/arm64/cavium/thunder_pcie.c (revision 294266) @@ -1,595 +1,595 @@ /*- * Copyright (c) 2015 The FreeBSD Foundation * All rights reserved. * * This software was developed by Semihalf under * the sponsorship of the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* PCIe root complex driver for Cavium Thunder SOC */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "thunder_pcie_common.h" #include "pcib_if.h" /* Assembling ECAM Configuration Address */ #define PCIE_BUS_SHIFT 20 #define PCIE_SLOT_SHIFT 15 #define PCIE_FUNC_SHIFT 12 #define PCIE_BUS_MASK 0xFF #define PCIE_SLOT_MASK 0x1F #define PCIE_FUNC_MASK 0x07 #define PCIE_REG_MASK 0xFFF #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \ ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \ (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \ (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \ ((reg) & PCIE_REG_MASK)) #define THUNDER_ECAM0_CFG_BASE 0x848000000000UL #define THUNDER_ECAM1_CFG_BASE 0x849000000000UL #define THUNDER_ECAM2_CFG_BASE 0x84a000000000UL #define THUNDER_ECAM3_CFG_BASE 0x84b000000000UL #define THUNDER_ECAM4_CFG_BASE 0x948000000000UL #define THUNDER_ECAM5_CFG_BASE 0x949000000000UL #define THUNDER_ECAM6_CFG_BASE 0x94a000000000UL #define THUNDER_ECAM7_CFG_BASE 0x94b000000000UL #define OFW_CELL_TO_UINT64(cell) \ (((uint64_t)(*(cell)) << 32) | (uint64_t)(*((cell) + 1))) #define SPACE_CODE_SHIFT 24 #define SPACE_CODE_MASK 0x3 #define SPACE_CODE_IO_SPACE 0x1 #define PROPS_CELL_SIZE 1 #define PCI_ADDR_CELL_SIZE 2 struct thunder_pcie_softc { - struct pcie_range ranges[MAX_RANGES_TUPLES]; + struct pcie_range ranges[RANGES_TUPLES_MAX]; struct rman mem_rman; struct resource *res; int ecam; device_t dev; }; /* * ThunderX supports up to 4 ethernet interfaces, so it's good * value to use as default for numbers of VFs, since each eth * interface represents separate virtual function. */ static int thunder_pcie_max_vfs = 4; SYSCTL_INT(_hw, OID_AUTO, thunder_pcie_max_vfs, CTLFLAG_RWTUN, &thunder_pcie_max_vfs, 0, "Max VFs supported by ThunderX internal PCIe"); /* Forward prototypes */ static struct resource *thunder_pcie_alloc_resource(device_t, device_t, int, int *, u_long, u_long, u_long, u_int); static int thunder_pcie_attach(device_t); static int thunder_pcie_identify_pcib(device_t); static int thunder_pcie_maxslots(device_t); static int parse_pci_mem_ranges(struct thunder_pcie_softc *); static int thunder_pcie_probe(device_t); static uint32_t thunder_pcie_read_config(device_t, u_int, u_int, u_int, u_int, int); static int thunder_pcie_read_ivar(device_t, device_t, int, uintptr_t *); static int thunder_pcie_release_resource(device_t, device_t, int, int, struct resource *); static void thunder_pcie_write_config(device_t, u_int, u_int, u_int, u_int, uint32_t, int); static int thunder_pcie_write_ivar(device_t, device_t, int, uintptr_t); static int thunder_pcie_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); - if (ofw_bus_is_compatible(dev, "cavium,thunder-pcie")) { + if (ofw_bus_is_compatible(dev, "cavium,thunder-pcie") || + ofw_bus_is_compatible(dev, "cavium,pci-host-thunder-ecam")) { device_set_desc(dev, "Cavium Integrated PCI/PCI-E Controller"); return (BUS_PROBE_DEFAULT); } return (ENXIO); } static int thunder_pcie_attach(device_t dev) { int rid; struct thunder_pcie_softc *sc; int error; int tuple; uint64_t base, size; sc = device_get_softc(dev); sc->dev = dev; /* Identify pcib domain */ if (thunder_pcie_identify_pcib(dev)) return (ENXIO); rid = 0; sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->res == NULL) { device_printf(dev, "could not map memory.\n"); return (ENXIO); } sc->mem_rman.rm_type = RMAN_ARRAY; sc->mem_rman.rm_descr = "PCIe Memory"; /* Retrieve 'ranges' property from FDT */ if (bootverbose) device_printf(dev, "parsing FDT for ECAM%d:\n", sc->ecam); if (parse_pci_mem_ranges(sc)) return (ENXIO); /* Initialize rman and allocate memory regions */ error = rman_init(&sc->mem_rman); if (error) { device_printf(dev, "rman_init() failed. error = %d\n", error); return (error); } - for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { + for (tuple = 0; tuple < RANGES_TUPLES_MAX; tuple++) { base = sc->ranges[tuple].phys_base; size = sc->ranges[tuple].size; if ((base == 0) || (size == 0)) continue; /* empty range element */ error = rman_manage_region(&sc->mem_rman, base, base + size - 1); if (error) { device_printf(dev, "rman_manage_region() failed. error = %d\n", error); rman_fini(&sc->mem_rman); return (error); } } device_add_child(dev, "pci", -1); return (bus_generic_attach(dev)); } static int parse_pci_mem_ranges(struct thunder_pcie_softc *sc) { phandle_t node; pcell_t pci_addr_cells, parent_addr_cells, size_cells; pcell_t attributes; pcell_t *ranges_buf, *cell_ptr; int cells_count, tuples_count; int tuple; int rv; node = ofw_bus_get_node(sc->dev); /* Find address cells if present */ if (OF_getencprop(node, "#address-cells", &pci_addr_cells, sizeof(pci_addr_cells)) < sizeof(pci_addr_cells)) pci_addr_cells = 2; /* Find size cells if present */ if (OF_getencprop(node, "#size-cells", &size_cells, sizeof(size_cells)) < sizeof(size_cells)) size_cells = 1; /* Find parent address cells if present */ if (OF_getencprop(OF_parent(node), "#address-cells", &parent_addr_cells, sizeof(parent_addr_cells)) < sizeof(parent_addr_cells)) parent_addr_cells = 2; /* Check if FDT format matches driver requirements */ if ((parent_addr_cells != 2) || (pci_addr_cells != 3) || (size_cells != 2)) { device_printf(sc->dev, "Unexpected number of address or size cells in FDT " " %d:%d:%d\n", parent_addr_cells, pci_addr_cells, size_cells); return (ENXIO); } cells_count = OF_getencprop_alloc(node, "ranges", sizeof(pcell_t), (void **)&ranges_buf); if (cells_count == -1) { device_printf(sc->dev, "Error parsing FDT 'ranges' property\n"); return (ENXIO); } tuples_count = cells_count / (pci_addr_cells + parent_addr_cells + size_cells); - if ((tuples_count > MAX_RANGES_TUPLES) || - (tuples_count < MIN_RANGES_TUPLES)) { + if (tuples_count > RANGES_TUPLES_MAX) { device_printf(sc->dev, "Unexpected number of 'ranges' tuples in FDT\n"); rv = ENXIO; goto out; } cell_ptr = ranges_buf; for (tuple = 0; tuple < tuples_count; tuple++) { /* * TUPLE FORMAT: * attributes - 32-bit attributes field * PCI address - bus address combined of two cells in * a following format: * * PA address - physical address combined of two cells in * a following format: * * size - range size combined of two cells in * a following format: * */ attributes = *cell_ptr; attributes = (attributes >> SPACE_CODE_SHIFT) & SPACE_CODE_MASK; if (attributes == SPACE_CODE_IO_SPACE) { /* Internal PCIe does not support IO space, ignore. */ sc->ranges[tuple].phys_base = 0; sc->ranges[tuple].size = 0; cell_ptr += (pci_addr_cells + parent_addr_cells + size_cells); continue; } cell_ptr += PROPS_CELL_SIZE; sc->ranges[tuple].pci_base = OFW_CELL_TO_UINT64(cell_ptr); cell_ptr += PCI_ADDR_CELL_SIZE; sc->ranges[tuple].phys_base = OFW_CELL_TO_UINT64(cell_ptr); cell_ptr += parent_addr_cells; sc->ranges[tuple].size = OFW_CELL_TO_UINT64(cell_ptr); cell_ptr += size_cells; if (bootverbose) { device_printf(sc->dev, "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx\n", sc->ranges[tuple].pci_base, sc->ranges[tuple].phys_base, sc->ranges[tuple].size); } } - for (; tuple < MAX_RANGES_TUPLES; tuple++) { + for (; tuple < RANGES_TUPLES_MAX; tuple++) { /* zero-fill remaining tuples to mark empty elements in array */ sc->ranges[tuple].phys_base = 0; sc->ranges[tuple].size = 0; } rv = 0; out: free(ranges_buf, M_OFWPROP); return (rv); } static uint32_t thunder_pcie_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, int bytes) { uint64_t offset; uint32_t data; struct thunder_pcie_softc *sc; bus_space_tag_t t; bus_space_handle_t h; if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) return (~0U); sc = device_get_softc(dev); offset = PCIE_ADDR_OFFSET(bus, slot, func, reg); t = rman_get_bustag(sc->res); h = rman_get_bushandle(sc->res); switch (bytes) { case 1: data = bus_space_read_1(t, h, offset); break; case 2: data = le16toh(bus_space_read_2(t, h, offset)); break; case 4: data = le32toh(bus_space_read_4(t, h, offset)); break; default: return (~0U); } return (data); } static void thunder_pcie_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, uint32_t val, int bytes) { uint64_t offset; struct thunder_pcie_softc *sc; bus_space_tag_t t; bus_space_handle_t h; if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) return ; sc = device_get_softc(dev); offset = PCIE_ADDR_OFFSET(bus, slot, func, reg); t = rman_get_bustag(sc->res); h = rman_get_bushandle(sc->res); switch (bytes) { case 1: bus_space_write_1(t, h, offset, val); break; case 2: bus_space_write_2(t, h, offset, htole16(val)); break; case 4: bus_space_write_4(t, h, offset, htole32(val)); break; default: return; } } static int thunder_pcie_maxslots(device_t dev) { /* max slots per bus acc. to standard */ return (PCI_SLOTMAX); } static int thunder_pcie_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) { struct thunder_pcie_softc *sc; sc = device_get_softc(dev); if (index == PCIB_IVAR_BUS) { /* this pcib is always on bus 0 */ *result = 0; return (0); } if (index == PCIB_IVAR_DOMAIN) { *result = sc->ecam; return (0); } return (ENOENT); } static int thunder_pcie_write_ivar(device_t dev, device_t child, int index, uintptr_t value) { return (ENOENT); } static int thunder_pcie_release_resource(device_t dev, device_t child, int type, int rid, struct resource *res) { if (type != SYS_RES_MEMORY) return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, type, rid, res)); return (rman_release_resource(res)); } static struct resource * thunder_pcie_alloc_resource(device_t dev, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct thunder_pcie_softc *sc = device_get_softc(dev); struct rman *rm = NULL; struct resource *res; pci_addr_t map, testval; switch (type) { case SYS_RES_IOPORT: goto fail; break; case SYS_RES_MEMORY: rm = &sc->mem_rman; break; default: return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, type, rid, start, end, count, flags)); }; if ((start == 0UL) && (end == ~0UL)) { /* Read BAR manually to get resource address and size */ pci_read_bar(child, *rid, &map, &testval, NULL); /* Mask the information bits */ if (PCI_BAR_MEM(map)) map &= PCIM_BAR_MEM_BASE; else map &= PCIM_BAR_IO_BASE; if (PCI_BAR_MEM(testval)) testval &= PCIM_BAR_MEM_BASE; else testval &= PCIM_BAR_IO_BASE; start = map; count = (~testval) + 1; /* * Internal ThunderX devices supports up to 3 64-bit BARs. * If we're allocating anything above, that means upper layer * wants us to allocate VF-BAR. In that case reserve bigger * slice to make a room for other VFs adjacent to this one. */ if (*rid > PCIR_BAR(5)) count = count * thunder_pcie_max_vfs; end = start + count - 1; } /* Convert input BUS address to required PHYS */ if (range_addr_is_pci(sc->ranges, start, count) == 0) goto fail; start = range_addr_pci_to_phys(sc->ranges, start); end = start + count - 1; if (bootverbose) { device_printf(dev, "rman_reserve_resource: start=%#lx, end=%#lx, count=%#lx\n", start, end, count); } res = rman_reserve_resource(rm, start, end, count, flags, child); if (res == NULL) goto fail; rman_set_rid(res, *rid); if ((flags & RF_ACTIVE) != 0) if (bus_activate_resource(child, type, *rid, res)) { rman_release_resource(res); goto fail; } return (res); fail: if (bootverbose) { device_printf(dev, "%s FAIL: type=%d, rid=%d, " "start=%016lx, end=%016lx, count=%016lx, flags=%x\n", __func__, type, *rid, start, end, count, flags); } return (NULL); } static int thunder_pcie_identify_pcib(device_t dev) { struct thunder_pcie_softc *sc; u_long start; sc = device_get_softc(dev); start = bus_get_resource_start(dev, SYS_RES_MEMORY, 0); switch(start) { case THUNDER_ECAM0_CFG_BASE: sc->ecam = 0; break; case THUNDER_ECAM1_CFG_BASE: sc->ecam = 1; break; case THUNDER_ECAM2_CFG_BASE: sc->ecam = 2; break; case THUNDER_ECAM3_CFG_BASE: sc->ecam = 3; break; case THUNDER_ECAM4_CFG_BASE: sc->ecam = 4; break; case THUNDER_ECAM5_CFG_BASE: sc->ecam = 5; break; case THUNDER_ECAM6_CFG_BASE: sc->ecam = 6; break; case THUNDER_ECAM7_CFG_BASE: sc->ecam = 7; break; default: device_printf(dev, "error: incorrect resource address=%#lx.\n", start); return (ENXIO); } return (0); } static device_method_t thunder_pcie_methods[] = { DEVMETHOD(device_probe, thunder_pcie_probe), DEVMETHOD(device_attach, thunder_pcie_attach), DEVMETHOD(pcib_maxslots, thunder_pcie_maxslots), DEVMETHOD(pcib_read_config, thunder_pcie_read_config), DEVMETHOD(pcib_write_config, thunder_pcie_write_config), DEVMETHOD(bus_read_ivar, thunder_pcie_read_ivar), DEVMETHOD(bus_write_ivar, thunder_pcie_write_ivar), DEVMETHOD(bus_alloc_resource, thunder_pcie_alloc_resource), DEVMETHOD(bus_release_resource, thunder_pcie_release_resource), DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), DEVMETHOD(pcib_map_msi, arm_map_msi), DEVMETHOD(pcib_alloc_msix, arm_alloc_msix), DEVMETHOD(pcib_release_msix, arm_release_msix), DEVMETHOD(pcib_alloc_msi, arm_alloc_msi), DEVMETHOD(pcib_release_msi, arm_release_msi), DEVMETHOD_END }; static driver_t thunder_pcie_driver = { "pcib", thunder_pcie_methods, sizeof(struct thunder_pcie_softc), }; static devclass_t thunder_pcie_devclass; DRIVER_MODULE(thunder_pcib, simplebus, thunder_pcie_driver, thunder_pcie_devclass, 0, 0); DRIVER_MODULE(thunder_pcib, ofwbus, thunder_pcie_driver, thunder_pcie_devclass, 0, 0); Index: head/sys/arm64/cavium/thunder_pcie_common.c =================================================================== --- head/sys/arm64/cavium/thunder_pcie_common.c (revision 294265) +++ head/sys/arm64/cavium/thunder_pcie_common.c (revision 294266) @@ -1,106 +1,106 @@ /*- * Copyright (c) 2015 The FreeBSD Foundation * All rights reserved. * * This software was developed by Semihalf under * the sponsorship of the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* Common PCIe functions for Cavium Thunder SOC */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include "thunder_pcie_common.h" uint32_t range_addr_is_pci(struct pcie_range *ranges, uint64_t addr, uint64_t size) { struct pcie_range *r; int tuple; - for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { + for (tuple = 0; tuple < RANGES_TUPLES_MAX; tuple++) { r = &ranges[tuple]; if (addr >= r->pci_base && addr < (r->pci_base + r->size) && size < r->size) { /* Address is within PCI range */ return (1); } } /* Address is outside PCI range */ return (0); } uint32_t range_addr_is_phys(struct pcie_range *ranges, uint64_t addr, uint64_t size) { struct pcie_range *r; int tuple; - for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { + for (tuple = 0; tuple < RANGES_TUPLES_MAX; tuple++) { r = &ranges[tuple]; if (addr >= r->phys_base && addr < (r->phys_base + r->size) && size < r->size) { /* Address is within Physical range */ return (1); } } /* Address is outside Physical range */ return (0); } uint64_t range_addr_pci_to_phys(struct pcie_range *ranges, uint64_t pci_addr) { struct pcie_range *r; uint64_t offset; int tuple; /* Find physical address corresponding to given bus address */ - for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { + for (tuple = 0; tuple < RANGES_TUPLES_MAX; tuple++) { r = &ranges[tuple]; if (pci_addr >= r->pci_base && pci_addr < (r->pci_base + r->size)) { /* Given pci addr is in this range. * Translate bus addr to phys addr. */ offset = pci_addr - r->pci_base; return (r->phys_base + offset); } } return (0); } Index: head/sys/arm64/cavium/thunder_pcie_common.h =================================================================== --- head/sys/arm64/cavium/thunder_pcie_common.h (revision 294265) +++ head/sys/arm64/cavium/thunder_pcie_common.h (revision 294266) @@ -1,51 +1,51 @@ /*- * Copyright (c) 2015 The FreeBSD Foundation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _CAVIUM_THUNDER_PCIE_COMMON_H_ #define _CAVIUM_THUNDER_PCIE_COMMON_H_ -#define MAX_RANGES_TUPLES 5 -#define MIN_RANGES_TUPLES 2 +#define RANGES_TUPLES_MAX 6 +#define RANGES_TUPLES_INVALID (RANGES_TUPLES_MAX + 1) struct pcie_range { uint64_t pci_base; uint64_t phys_base; uint64_t size; uint64_t flags; }; uint32_t range_addr_is_pci(struct pcie_range *, uint64_t, uint64_t); uint32_t range_addr_is_phys(struct pcie_range *, uint64_t, uint64_t); uint64_t range_addr_pci_to_phys(struct pcie_range *, uint64_t); int thunder_common_alloc_msi(device_t, device_t, int, int, int *); int thunder_common_alloc_msix(device_t, device_t, int *); int thunder_common_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); int thunder_common_release_msi(device_t, device_t, int, int *); int thunder_common_release_msix(device_t, device_t, int); #endif /* _CAVIUM_THUNDER_PCIE_COMMON_H_ */ Index: head/sys/arm64/cavium/thunder_pcie_pem.c =================================================================== --- head/sys/arm64/cavium/thunder_pcie_pem.c (revision 294265) +++ head/sys/arm64/cavium/thunder_pcie_pem.c (revision 294266) @@ -1,646 +1,646 @@ /*- * Copyright (c) 2015 The FreeBSD Foundation * All rights reserved. * * This software was developed by Semihalf under * the sponsorship of the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* PCIe external MAC root complex driver (PEM) for Cavium Thunder SOC */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "thunder_pcie_common.h" #include "pcib_if.h" #define THUNDER_PEM_DEVICE_ID 0xa020 #define THUNDER_PEM_VENDOR_ID 0x177d #define THUNDER_PEM_DESC "ThunderX PEM" /* ThunderX specific defines */ #define THUNDER_PEMn_REG_BASE(unit) (0x87e0c0000000UL | ((unit) << 24)) #define PCIERC_CFG002 0x08 #define PCIERC_CFG006 0x18 #define PCIERC_CFG032 0x80 #define PCIERC_CFG006_SEC_BUS(reg) (((reg) >> 8) & 0xFF) #define PEM_CFG_RD_REG_ALIGN(reg) ((reg) & ~0x3) #define PEM_CFG_RD_REG_DATA(val) (((val) >> 32) & 0xFFFFFFFF) #define PEM_CFG_RD 0x30 #define PEM_CFG_LINK_MASK 0x3 #define PEM_CFG_LINK_RDY 0x3 #define PEM_CFG_SLIX_TO_REG(slix) ((slix) << 4) #define SBNUM_OFFSET 0x8 #define SBNUM_MASK 0xFF #define PEM_ON_REG 0x420 #define PEM_CTL_STATUS 0x0 #define PEM_LINK_ENABLE (1 << 4) #define PEM_LINK_DLLA (1 << 29) #define PEM_LINK_LT (1 << 27) #define PEM_BUS_SHIFT (24) #define PEM_SLOT_SHIFT (19) #define PEM_FUNC_SHIFT (16) #define SLIX_S2M_REGX_ACC 0x874001000000UL #define SLIX_S2M_REGX_ACC_SIZE 0x1000 #define SLIX_S2M_REGX_ACC_SPACING 0x001000000000UL #define SLI_BASE 0x880000000000UL #define SLI_WINDOW_SPACING 0x004000000000UL #define SLI_WINDOW_SIZE 0x0000FF000000UL #define SLI_PCI_OFFSET 0x001000000000UL #define SLI_NODE_SHIFT (44) #define SLI_NODE_MASK (3) #define SLI_GROUP_SHIFT (40) #define SLI_ID_SHIFT (24) #define SLI_ID_MASK (7) #define SLI_PEMS_PER_GROUP (3) #define SLI_GROUPS_PER_NODE (2) #define SLI_PEMS_PER_NODE (SLI_PEMS_PER_GROUP * SLI_GROUPS_PER_NODE) #define SLI_ACC_REG_CNT (256) /* * Each PEM device creates its own bus with * own address translation, so we can adjust bus addresses * as we want. To support 32-bit cards let's assume * PCI window assignment looks as following: * * 0x00000000 - 0x000FFFFF IO * 0x00100000 - 0xFFFFFFFF Memory */ #define PCI_IO_BASE 0x00000000UL #define PCI_IO_SIZE 0x00100000UL #define PCI_MEMORY_BASE PCI_IO_SIZE #define PCI_MEMORY_SIZE 0xFFF00000UL struct thunder_pem_softc { device_t dev; struct resource *reg; bus_space_tag_t reg_bst; bus_space_handle_t reg_bsh; - struct pcie_range ranges[MAX_RANGES_TUPLES]; + struct pcie_range ranges[RANGES_TUPLES_MAX]; struct rman mem_rman; struct rman io_rman; bus_space_handle_t pem_sli_base; uint32_t node; uint32_t id; uint32_t sli; uint32_t sli_group; uint64_t sli_window_base; }; static struct resource * thunder_pem_alloc_resource(device_t, device_t, int, int *, u_long, u_long, u_long, u_int); static int thunder_pem_attach(device_t); static int thunder_pem_detach(device_t); static uint64_t thunder_pem_config_reg_read(struct thunder_pem_softc *, int); static int thunder_pem_link_init(struct thunder_pem_softc *); static int thunder_pem_maxslots(device_t); static int thunder_pem_probe(device_t); static uint32_t thunder_pem_read_config(device_t, u_int, u_int, u_int, u_int, int); static int thunder_pem_read_ivar(device_t, device_t, int, uintptr_t *); static void thunder_pem_release_all(device_t); static int thunder_pem_release_resource(device_t, device_t, int, int, struct resource *); static void thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *, int, int); static void thunder_pem_write_config(device_t, u_int, u_int, u_int, u_int, uint32_t, int); static int thunder_pem_write_ivar(device_t, device_t, int, uintptr_t); /* Global handlers for SLI interface */ static bus_space_handle_t sli0_s2m_regx_base = 0; static bus_space_handle_t sli1_s2m_regx_base = 0; static device_method_t thunder_pem_methods[] = { /* Device interface */ DEVMETHOD(device_probe, thunder_pem_probe), DEVMETHOD(device_attach, thunder_pem_attach), DEVMETHOD(device_detach, thunder_pem_detach), DEVMETHOD(pcib_maxslots, thunder_pem_maxslots), DEVMETHOD(pcib_read_config, thunder_pem_read_config), DEVMETHOD(pcib_write_config, thunder_pem_write_config), DEVMETHOD(bus_read_ivar, thunder_pem_read_ivar), DEVMETHOD(bus_write_ivar, thunder_pem_write_ivar), DEVMETHOD(bus_alloc_resource, thunder_pem_alloc_resource), DEVMETHOD(bus_release_resource, thunder_pem_release_resource), DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), DEVMETHOD(pcib_map_msi, arm_map_msi), DEVMETHOD(pcib_alloc_msix, arm_alloc_msix), DEVMETHOD(pcib_release_msix, arm_release_msix), DEVMETHOD(pcib_alloc_msi, arm_alloc_msi), DEVMETHOD(pcib_release_msi, arm_release_msi), DEVMETHOD_END }; static driver_t thunder_pem_driver = { "pcib", thunder_pem_methods, sizeof(struct thunder_pem_softc), }; static int thunder_pem_maxslots(device_t dev) { #if 0 /* max slots per bus acc. to standard */ return (PCI_SLOTMAX); #else /* * ARM64TODO Workaround - otherwise an em(4) interface appears to be * present on every PCI function on the bus to which it is connected */ return (0); #endif } static int thunder_pem_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) { struct thunder_pem_softc *sc; int secondary_bus = 0; sc = device_get_softc(dev); if (index == PCIB_IVAR_BUS) { secondary_bus = thunder_pem_config_reg_read(sc, PCIERC_CFG006); *result = PCIERC_CFG006_SEC_BUS(secondary_bus); return (0); } if (index == PCIB_IVAR_DOMAIN) { *result = sc->id; return (0); } return (ENOENT); } static int thunder_pem_write_ivar(device_t dev, device_t child, int index, uintptr_t value) { return (ENOENT); } static int thunder_pem_identify(device_t dev) { struct thunder_pem_softc *sc; u_long start; sc = device_get_softc(dev); start = rman_get_start(sc->reg); /* Calculate PEM designations from its address */ sc->node = (start >> SLI_NODE_SHIFT) & SLI_NODE_MASK; sc->id = ((start >> SLI_ID_SHIFT) & SLI_ID_MASK) + (SLI_PEMS_PER_NODE * sc->node); sc->sli = sc->id % SLI_PEMS_PER_GROUP; sc->sli_group = (sc->id / SLI_PEMS_PER_GROUP) % SLI_GROUPS_PER_NODE; sc->sli_window_base = SLI_BASE | (((uint64_t)sc->node) << SLI_NODE_SHIFT) | ((uint64_t)sc->sli_group << SLI_GROUP_SHIFT); sc->sli_window_base += SLI_WINDOW_SPACING * sc->sli; return (0); } static void thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *sc, int sli_group, int slix) { uint64_t regval; bus_space_handle_t handle = 0; KASSERT(slix >= 0 && slix <= SLI_ACC_REG_CNT, ("Invalid SLI index")); if (sli_group == 0) handle = sli0_s2m_regx_base; else if (sli_group == 1) handle = sli1_s2m_regx_base; else device_printf(sc->dev, "SLI group is not correct\n"); if (handle) { /* Clear lower 32-bits of the SLIx register */ regval = bus_space_read_8(sc->reg_bst, handle, PEM_CFG_SLIX_TO_REG(slix)); regval &= ~(0xFFFFFFFFUL); bus_space_write_8(sc->reg_bst, handle, PEM_CFG_SLIX_TO_REG(slix), regval); } } static int thunder_pem_link_init(struct thunder_pem_softc *sc) { uint64_t regval; /* check whether PEM is safe to access. */ regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_ON_REG); if ((regval & PEM_CFG_LINK_MASK) != PEM_CFG_LINK_RDY) { device_printf(sc->dev, "PEM%d is not ON\n", sc->id); return (ENXIO); } regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS); regval |= PEM_LINK_ENABLE; bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS, regval); /* Wait 1ms as per Cavium specification */ DELAY(1000); regval = thunder_pem_config_reg_read(sc, PCIERC_CFG032); if (((regval & PEM_LINK_DLLA) == 0) || ((regval & PEM_LINK_LT) != 0)) { device_printf(sc->dev, "PCIe RC: Port %d Link Timeout\n", sc->id); return (ENXIO); } return (0); } static int thunder_pem_init(struct thunder_pem_softc *sc) { int i, retval = 0; retval = thunder_pem_link_init(sc); if (retval) { device_printf(sc->dev, "%s failed\n", __func__); return retval; } retval = bus_space_map(sc->reg_bst, sc->sli_window_base, SLI_WINDOW_SIZE, 0, &sc->pem_sli_base); if (retval) { device_printf(sc->dev, "Unable to map RC%d pem_addr base address", sc->id); return (ENOMEM); } /* To support 32-bit PCIe devices, set S2M_REGx_ACC[BA]=0x0 */ for (i = 0; i < SLI_ACC_REG_CNT; i++) { thunder_pem_slix_s2m_regx_acc_modify(sc, sc->sli_group, i); } return (retval); } static uint64_t thunder_pem_config_reg_read(struct thunder_pem_softc *sc, int reg) { uint64_t data; /* Write to ADDR register */ bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, PEM_CFG_RD_REG_ALIGN(reg)); bus_space_barrier(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, 8, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); /* Read from DATA register */ data = PEM_CFG_RD_REG_DATA(bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD)); return (data); } static uint32_t thunder_pem_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, int bytes) { uint64_t offset; uint32_t data; struct thunder_pem_softc *sc; bus_space_tag_t t; bus_space_handle_t h; if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) return (~0U); sc = device_get_softc(dev); /* Calculate offset */ offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) | (func << PEM_FUNC_SHIFT) | reg; t = sc->reg_bst; h = sc->pem_sli_base; switch (bytes) { case 1: data = bus_space_read_1(t, h, offset); break; case 2: data = le16toh(bus_space_read_2(t, h, offset)); break; case 4: data = le32toh(bus_space_read_4(t, h, offset)); break; default: return (~0U); } return (data); } static void thunder_pem_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, uint32_t val, int bytes) { uint64_t offset; struct thunder_pem_softc *sc; bus_space_tag_t t; bus_space_handle_t h; if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) return; sc = device_get_softc(dev); /* Calculate offset */ offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) | (func << PEM_FUNC_SHIFT) | reg; t = sc->reg_bst; h = sc->pem_sli_base; switch (bytes) { case 1: bus_space_write_1(t, h, offset, val); break; case 2: bus_space_write_2(t, h, offset, htole16(val)); break; case 4: bus_space_write_4(t, h, offset, htole32(val)); break; default: return; } } static struct resource * thunder_pem_alloc_resource(device_t dev, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct thunder_pem_softc *sc = device_get_softc(dev); struct rman *rm = NULL; struct resource *res; device_t parent_dev; switch (type) { case SYS_RES_IOPORT: rm = &sc->io_rman; break; case SYS_RES_MEMORY: rm = &sc->mem_rman; break; default: /* Find parent device. On ThunderX we know an exact path. */ parent_dev = device_get_parent(device_get_parent(dev)); return (BUS_ALLOC_RESOURCE(parent_dev, dev, type, rid, start, end, count, flags)); }; if ((start == 0UL) && (end == ~0UL)) { device_printf(dev, "Cannot allocate resource with unspecified range\n"); goto fail; } /* Translate PCI address to host PHYS */ if (range_addr_is_pci(sc->ranges, start, count) == 0) goto fail; start = range_addr_pci_to_phys(sc->ranges, start); end = start + count - 1; if (bootverbose) { device_printf(dev, "rman_reserve_resource: start=%#lx, end=%#lx, count=%#lx\n", start, end, count); } res = rman_reserve_resource(rm, start, end, count, flags, child); if (res == NULL) goto fail; rman_set_rid(res, *rid); if (flags & RF_ACTIVE) if (bus_activate_resource(child, type, *rid, res)) { rman_release_resource(res); goto fail; } return (res); fail: if (bootverbose) { device_printf(dev, "%s FAIL: type=%d, rid=%d, " "start=%016lx, end=%016lx, count=%016lx, flags=%x\n", __func__, type, *rid, start, end, count, flags); } return (NULL); } static int thunder_pem_release_resource(device_t dev, device_t child, int type, int rid, struct resource *res) { device_t parent_dev; /* Find parent device. On ThunderX we know an exact path. */ parent_dev = device_get_parent(device_get_parent(dev)); if ((type != SYS_RES_MEMORY) && (type != SYS_RES_IOPORT)) return (BUS_RELEASE_RESOURCE(parent_dev, child, type, rid, res)); return (rman_release_resource(res)); } static int thunder_pem_probe(device_t dev) { uint16_t pci_vendor_id; uint16_t pci_device_id; pci_vendor_id = pci_get_vendor(dev); pci_device_id = pci_get_device(dev); if ((pci_vendor_id == THUNDER_PEM_VENDOR_ID) && (pci_device_id == THUNDER_PEM_DEVICE_ID)) { device_set_desc_copy(dev, THUNDER_PEM_DESC); return (0); } return (ENXIO); } static int thunder_pem_attach(device_t dev) { struct thunder_pem_softc *sc; int error; int rid; sc = device_get_softc(dev); sc->dev = dev; /* Allocate memory for BAR(0) */ rid = PCIR_BAR(0); sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->reg == NULL) { device_printf(dev, "Failed to allocate resource\n"); return (ENXIO); } sc->reg_bst = rman_get_bustag(sc->reg); sc->reg_bsh = rman_get_bushandle(sc->reg); /* Map SLI, do it only once */ if (!sli0_s2m_regx_base) { bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC, SLIX_S2M_REGX_ACC_SIZE, 0, &sli0_s2m_regx_base); } if (!sli1_s2m_regx_base) { bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC + SLIX_S2M_REGX_ACC_SPACING, SLIX_S2M_REGX_ACC_SIZE, 0, &sli1_s2m_regx_base); } if ((sli0_s2m_regx_base == 0) || (sli1_s2m_regx_base == 0)) { device_printf(dev, "bus_space_map failed to map slix_s2m_regx_base\n"); goto fail; } /* Identify PEM */ if (thunder_pem_identify(dev) != 0) goto fail; /* Initialize rman and allocate regions */ sc->mem_rman.rm_type = RMAN_ARRAY; sc->mem_rman.rm_descr = "PEM PCIe Memory"; error = rman_init(&sc->mem_rman); if (error != 0) { device_printf(dev, "memory rman_init() failed. error = %d\n", error); goto fail; } sc->io_rman.rm_type = RMAN_ARRAY; sc->io_rman.rm_descr = "PEM PCIe IO"; error = rman_init(&sc->io_rman); if (error != 0) { device_printf(dev, "IO rman_init() failed. error = %d\n", error); goto fail_mem; } /* Fill memory window */ sc->ranges[0].pci_base = PCI_MEMORY_BASE; sc->ranges[0].size = PCI_MEMORY_SIZE; sc->ranges[0].phys_base = sc->sli_window_base + SLI_PCI_OFFSET + sc->ranges[0].pci_base; rman_manage_region(&sc->mem_rman, sc->ranges[0].phys_base, sc->ranges[0].phys_base + sc->ranges[0].size - 1); /* Fill IO window */ sc->ranges[1].pci_base = PCI_IO_BASE; sc->ranges[1].size = PCI_IO_SIZE; sc->ranges[1].phys_base = sc->sli_window_base + SLI_PCI_OFFSET + sc->ranges[1].pci_base; rman_manage_region(&sc->io_rman, sc->ranges[1].phys_base, sc->ranges[1].phys_base + sc->ranges[1].size - 1); if (thunder_pem_init(sc)) { device_printf(dev, "Failure during PEM init\n"); goto fail_io; } device_add_child(dev, "pci", -1); return (bus_generic_attach(dev)); fail_io: rman_fini(&sc->io_rman); fail_mem: rman_fini(&sc->mem_rman); fail: bus_free_resource(dev, SYS_RES_MEMORY, sc->reg); return (ENXIO); } static void thunder_pem_release_all(device_t dev) { struct thunder_pem_softc *sc; sc = device_get_softc(dev); rman_fini(&sc->io_rman); rman_fini(&sc->mem_rman); if (sc->reg != NULL) bus_free_resource(dev, SYS_RES_MEMORY, sc->reg); } static int thunder_pem_detach(device_t dev) { thunder_pem_release_all(dev); return (0); } static devclass_t thunder_pem_devclass; DRIVER_MODULE(thunder_pem, pci, thunder_pem_driver, thunder_pem_devclass, 0, 0); MODULE_DEPEND(thunder_pem, pci, 1, 1, 1);