Index: stable/9/sys/conf/files
===================================================================
--- stable/9/sys/conf/files	(revision 292780)
+++ stable/9/sys/conf/files	(revision 292781)
@@ -1,3702 +1,3702 @@
 # $FreeBSD$
 #
 # The long compile-with and dependency lines are required because of
 # limitations in config: backslash-newline doesn't work in strings, and
 # dependency lines other than the first are silently ignored.
 #
 acpi_quirks.h			optional acpi				   \
 	dependency	"$S/tools/acpi_quirks2h.awk $S/dev/acpica/acpi_quirks" \
 	compile-with	"${AWK} -f $S/tools/acpi_quirks2h.awk $S/dev/acpica/acpi_quirks" \
 	no-obj no-implicit-rule before-depend				   \
 	clean		"acpi_quirks.h"
 aicasm				optional ahc | ahd			   \
 	dependency	"$S/dev/aic7xxx/aicasm/*.[chyl]"		   \
 	compile-with	"CC='${CC}' ${MAKE} -f $S/dev/aic7xxx/aicasm/Makefile MAKESRCPATH=$S/dev/aic7xxx/aicasm" \
 	no-obj no-implicit-rule						   \
 	clean		"aicasm* y.tab.h"
 aic7xxx_seq.h			optional ahc				   \
 	compile-with	"./aicasm ${INCLUDES} -I$S/cam/scsi -I$S/dev/aic7xxx -o aic7xxx_seq.h -r aic7xxx_reg.h -p aic7xxx_reg_print.c -i $S/dev/aic7xxx/aic7xxx_osm.h $S/dev/aic7xxx/aic7xxx.seq"   \
 	no-obj no-implicit-rule before-depend local			   \
 	clean		"aic7xxx_seq.h"					   \
 	dependency	"$S/dev/aic7xxx/aic7xxx.{reg,seq} $S/cam/scsi/scsi_message.h aicasm"
 aic7xxx_reg.h			optional ahc				   \
 	compile-with	"./aicasm ${INCLUDES} -I$S/cam/scsi -I$S/dev/aic7xxx -o aic7xxx_seq.h -r aic7xxx_reg.h -p aic7xxx_reg_print.c -i $S/dev/aic7xxx/aic7xxx_osm.h $S/dev/aic7xxx/aic7xxx.seq"   \
 	no-obj no-implicit-rule before-depend local			   \
 	clean		"aic7xxx_reg.h"					   \
 	dependency	"$S/dev/aic7xxx/aic7xxx.{reg,seq} $S/cam/scsi/scsi_message.h aicasm"
 aic7xxx_reg_print.c		optional ahc				   \
 	compile-with	"./aicasm ${INCLUDES} -I$S/cam/scsi -I$S/dev/aic7xxx -o aic7xxx_seq.h -r aic7xxx_reg.h -p aic7xxx_reg_print.c -i $S/dev/aic7xxx/aic7xxx_osm.h $S/dev/aic7xxx/aic7xxx.seq"   \
 	no-obj no-implicit-rule local					   \
 	clean		"aic7xxx_reg_print.c"				   \
 	dependency	"$S/dev/aic7xxx/aic7xxx.{reg,seq} $S/cam/scsi/scsi_message.h aicasm"
 aic7xxx_reg_print.o		optional ahc ahc_reg_pretty_print	   \
 	compile-with	"${NORMAL_C}"					   \
 	no-implicit-rule local
 aic79xx_seq.h		optional ahd pci				   \
 	compile-with	"./aicasm ${INCLUDES} -I$S/cam/scsi -I$S/dev/aic7xxx -o aic79xx_seq.h -r aic79xx_reg.h -p aic79xx_reg_print.c -i $S/dev/aic7xxx/aic79xx_osm.h $S/dev/aic7xxx/aic79xx.seq"   \
 	no-obj no-implicit-rule before-depend local			   \
 	clean		"aic79xx_seq.h"					   \
 	dependency	"$S/dev/aic7xxx/aic79xx.{reg,seq} $S/cam/scsi/scsi_message.h aicasm"
 aic79xx_reg.h		optional ahd pci				   \
 	compile-with	"./aicasm ${INCLUDES} -I$S/cam/scsi -I$S/dev/aic7xxx -o aic79xx_seq.h -r aic79xx_reg.h -p aic79xx_reg_print.c -i $S/dev/aic7xxx/aic79xx_osm.h $S/dev/aic7xxx/aic79xx.seq"   \
 	no-obj no-implicit-rule before-depend local			   \
 	clean		"aic79xx_reg.h"					   \
 	dependency	"$S/dev/aic7xxx/aic79xx.{reg,seq} $S/cam/scsi/scsi_message.h aicasm"
 aic79xx_reg_print.c	optional ahd pci				   \
 	compile-with	"./aicasm ${INCLUDES} -I$S/cam/scsi -I$S/dev/aic7xxx -o aic79xx_seq.h -r aic79xx_reg.h -p aic79xx_reg_print.c -i $S/dev/aic7xxx/aic79xx_osm.h $S/dev/aic7xxx/aic79xx.seq"   \
 	no-obj no-implicit-rule local					   \
 	clean		"aic79xx_reg_print.c"				   \
 	dependency	"$S/dev/aic7xxx/aic79xx.{reg,seq} $S/cam/scsi/scsi_message.h aicasm"
 aic79xx_reg_print.o		optional ahd pci ahd_reg_pretty_print	   \
 	compile-with	"${NORMAL_C}"					   \
 	no-implicit-rule local
 #
 # The 'fdt_dtb_file' target covers an actual DTB file name, which is derived
 # from the specified source (DTS) file: <platform>.dts -> <platform>.dtb
 #
 fdt_dtb_file			optional fdt \
 	compile-with "if [ -f $S/boot/fdt/dts/${FDT_DTS_FILE} ]; then dtc -O dtb -o `echo ${FDT_DTS_FILE} | cut -d. -f1`.dtb -b 0 -p 1024 $S/boot/fdt/dts/${FDT_DTS_FILE}; fi" \
 	no-obj no-implicit-rule before-depend	\
 	clean		"`echo ${FDT_DTS_FILE} | cut -d. -f1`.dtb"
 fdt_static_dtb.h		optional fdt fdt_dtb_static \
 	compile-with "sh $S/tools/fdt/make_dtbh.sh ${FDT_DTS_FILE} ." \
 	no-obj no-implicit-rule before-depend \
 	clean		"fdt_static_dtb.h"
 feeder_eq_gen.h			optional sound				   \
 	dependency	"$S/tools/sound/feeder_eq_mkfilter.awk"		   \
 	compile-with	"${AWK} -f $S/tools/sound/feeder_eq_mkfilter.awk -- ${FEEDER_EQ_PRESETS} > feeder_eq_gen.h" \
 	no-obj no-implicit-rule before-depend				   \
 	clean		"feeder_eq_gen.h"
 feeder_rate_gen.h		optional sound				   \
 	dependency	"$S/tools/sound/feeder_rate_mkfilter.awk"	   \
 	compile-with	"${AWK} -f $S/tools/sound/feeder_rate_mkfilter.awk -- ${FEEDER_RATE_PRESETS} > feeder_rate_gen.h" \
 	no-obj no-implicit-rule before-depend				   \
 	clean		"feeder_rate_gen.h"
 snd_fxdiv_gen.h			optional sound				   \
 	dependency	"$S/tools/sound/snd_fxdiv_gen.awk"		   \
 	compile-with	"${AWK} -f $S/tools/sound/snd_fxdiv_gen.awk -- > snd_fxdiv_gen.h" \
 	no-obj no-implicit-rule before-depend				   \
 	clean		"snd_fxdiv_gen.h"
 miidevs.h			optional miibus | mii			   \
 	dependency	"$S/tools/miidevs2h.awk $S/dev/mii/miidevs"	   \
 	compile-with	"${AWK} -f $S/tools/miidevs2h.awk $S/dev/mii/miidevs" \
 	no-obj no-implicit-rule before-depend				   \
 	clean		"miidevs.h"
 pccarddevs.h			standard				   \
 	dependency	"$S/tools/pccarddevs2h.awk $S/dev/pccard/pccarddevs" \
 	compile-with	"${AWK} -f $S/tools/pccarddevs2h.awk $S/dev/pccard/pccarddevs" \
 	no-obj no-implicit-rule before-depend				   \
 	clean		"pccarddevs.h"
 teken_state.h		optional sc | vt				   \
 	dependency	"$S/teken/gensequences $S/teken/sequences" \
 	compile-with	"${AWK} -f $S/teken/gensequences $S/teken/sequences > teken_state.h" \
 	no-obj no-implicit-rule before-depend				   \
 	clean		"teken_state.h"
 usbdevs.h			optional usb				   \
 	dependency	"$S/tools/usbdevs2h.awk $S/dev/usb/usbdevs" \
 	compile-with	"${AWK} -f $S/tools/usbdevs2h.awk $S/dev/usb/usbdevs -h" \
 	no-obj no-implicit-rule before-depend				   \
 	clean		"usbdevs.h"
 usbdevs_data.h			optional usb				   \
 	dependency	"$S/tools/usbdevs2h.awk $S/dev/usb/usbdevs" \
 	compile-with	"${AWK} -f $S/tools/usbdevs2h.awk $S/dev/usb/usbdevs -d" \
 	no-obj no-implicit-rule before-depend				   \
 	clean		"usbdevs_data.h"
 cam/cam.c			optional scbus
 cam/cam_compat.c		optional scbus
 cam/cam_periph.c		optional scbus
 cam/cam_queue.c			optional scbus
 cam/cam_sim.c			optional scbus
 cam/cam_xpt.c			optional scbus
 cam/ata/ata_all.c		optional scbus
 cam/ata/ata_xpt.c		optional scbus
 cam/ata/ata_pmp.c		optional scbus
 cam/scsi/scsi_xpt.c		optional scbus
 cam/scsi/scsi_all.c		optional scbus
 cam/scsi/scsi_cd.c		optional cd
 cam/scsi/scsi_ch.c		optional ch
 cam/ata/ata_da.c		optional ada | da
 cam/ctl/ctl.c			optional ctl
 cam/ctl/ctl_backend.c		optional ctl
 cam/ctl/ctl_backend_block.c	optional ctl
 cam/ctl/ctl_backend_ramdisk.c	optional ctl
 cam/ctl/ctl_cmd_table.c		optional ctl
 cam/ctl/ctl_frontend.c		optional ctl
 cam/ctl/ctl_frontend_cam_sim.c	optional ctl
 cam/ctl/ctl_frontend_internal.c	optional ctl
 cam/ctl/ctl_scsi_all.c		optional ctl
 cam/ctl/ctl_error.c		optional ctl
 cam/ctl/ctl_util.c		optional ctl
 cam/ctl/scsi_ctl.c		optional ctl
 cam/scsi/scsi_da.c		optional da
 cam/scsi/scsi_low.c		optional ct | ncv | nsp | stg
 cam/scsi/scsi_low_pisa.c	optional ct | ncv | nsp | stg
 cam/scsi/scsi_pass.c		optional pass
 cam/scsi/scsi_pt.c		optional pt
 cam/scsi/scsi_sa.c		optional sa
 cam/scsi/scsi_enc.c		optional ses
 cam/scsi/scsi_enc_ses.c		optional ses
 cam/scsi/scsi_enc_safte.c	optional ses
 cam/scsi/scsi_sg.c		optional sg
 cam/scsi/scsi_targ_bh.c		optional targbh
 cam/scsi/scsi_target.c		optional targ
 cam/scsi/smp_all.c		optional scbus
 contrib/altq/altq/altq_cbq.c	optional altq \
 	compile-with "${NORMAL_C} -I$S/contrib/pf"
 contrib/altq/altq/altq_cdnr.c	optional altq
 contrib/altq/altq/altq_hfsc.c	optional altq \
 	compile-with "${NORMAL_C} -I$S/contrib/pf"
 contrib/altq/altq/altq_priq.c	optional altq \
 	compile-with "${NORMAL_C} -I$S/contrib/pf"
 contrib/altq/altq/altq_red.c	optional altq \
 	compile-with "${NORMAL_C} -I$S/contrib/pf"
 contrib/altq/altq/altq_rio.c	optional altq \
 	compile-with "${NORMAL_C} -I$S/contrib/pf"
 contrib/altq/altq/altq_rmclass.c optional altq
 contrib/altq/altq/altq_subr.c	optional altq \
 	compile-with "${NORMAL_C} -I$S/contrib/pf"
 contrib/dev/acpica/debugger/dbcmds.c	optional acpi acpi_debug
 contrib/dev/acpica/debugger/dbdisply.c	optional acpi acpi_debug
 contrib/dev/acpica/debugger/dbexec.c	optional acpi acpi_debug
 contrib/dev/acpica/debugger/dbfileio.c	optional acpi acpi_debug
 contrib/dev/acpica/debugger/dbhistry.c	optional acpi acpi_debug
 contrib/dev/acpica/debugger/dbinput.c	optional acpi acpi_debug
 contrib/dev/acpica/debugger/dbmethod.c	optional acpi acpi_debug
 contrib/dev/acpica/debugger/dbnames.c	optional acpi acpi_debug
 contrib/dev/acpica/debugger/dbstats.c	optional acpi acpi_debug
 contrib/dev/acpica/debugger/dbutils.c	optional acpi acpi_debug
 contrib/dev/acpica/debugger/dbxface.c	optional acpi acpi_debug
 contrib/dev/acpica/disassembler/dmbuffer.c	optional acpi acpi_debug
 contrib/dev/acpica/disassembler/dmnames.c	optional acpi acpi_debug
 contrib/dev/acpica/disassembler/dmopcode.c	optional acpi acpi_debug
 contrib/dev/acpica/disassembler/dmobject.c	optional acpi acpi_debug
 contrib/dev/acpica/disassembler/dmresrc.c	optional acpi acpi_debug
 contrib/dev/acpica/disassembler/dmresrcl.c	optional acpi acpi_debug
 contrib/dev/acpica/disassembler/dmresrcs.c	optional acpi acpi_debug
 contrib/dev/acpica/disassembler/dmutils.c	optional acpi acpi_debug
 contrib/dev/acpica/disassembler/dmwalk.c	optional acpi acpi_debug
 contrib/dev/acpica/dispatcher/dsargs.c		optional acpi
 contrib/dev/acpica/dispatcher/dscontrol.c	optional acpi
 contrib/dev/acpica/dispatcher/dsfield.c		optional acpi
 contrib/dev/acpica/dispatcher/dsinit.c		optional acpi
 contrib/dev/acpica/dispatcher/dsmethod.c	optional acpi
 contrib/dev/acpica/dispatcher/dsmthdat.c	optional acpi
 contrib/dev/acpica/dispatcher/dsobject.c	optional acpi
 contrib/dev/acpica/dispatcher/dsopcode.c	optional acpi
 contrib/dev/acpica/dispatcher/dsutils.c		optional acpi
 contrib/dev/acpica/dispatcher/dswexec.c		optional acpi
 contrib/dev/acpica/dispatcher/dswload.c		optional acpi
 contrib/dev/acpica/dispatcher/dswload2.c	optional acpi
 contrib/dev/acpica/dispatcher/dswscope.c	optional acpi
 contrib/dev/acpica/dispatcher/dswstate.c	optional acpi
 contrib/dev/acpica/events/evevent.c		optional acpi
 contrib/dev/acpica/events/evglock.c		optional acpi
 contrib/dev/acpica/events/evgpe.c		optional acpi
 contrib/dev/acpica/events/evgpeblk.c		optional acpi
 contrib/dev/acpica/events/evgpeinit.c		optional acpi
 contrib/dev/acpica/events/evgpeutil.c		optional acpi
 contrib/dev/acpica/events/evmisc.c		optional acpi
 contrib/dev/acpica/events/evregion.c		optional acpi
 contrib/dev/acpica/events/evrgnini.c		optional acpi
 contrib/dev/acpica/events/evsci.c		optional acpi
 contrib/dev/acpica/events/evxface.c		optional acpi
 contrib/dev/acpica/events/evxfevnt.c		optional acpi
 contrib/dev/acpica/events/evxfgpe.c		optional acpi
 contrib/dev/acpica/events/evxfregn.c		optional acpi
 contrib/dev/acpica/executer/exconfig.c		optional acpi
 contrib/dev/acpica/executer/exconvrt.c		optional acpi
 contrib/dev/acpica/executer/excreate.c		optional acpi
 contrib/dev/acpica/executer/exdebug.c		optional acpi
 contrib/dev/acpica/executer/exdump.c		optional acpi
 contrib/dev/acpica/executer/exfield.c		optional acpi
 contrib/dev/acpica/executer/exfldio.c		optional acpi
 contrib/dev/acpica/executer/exmisc.c		optional acpi
 contrib/dev/acpica/executer/exmutex.c		optional acpi
 contrib/dev/acpica/executer/exnames.c		optional acpi
 contrib/dev/acpica/executer/exoparg1.c		optional acpi
 contrib/dev/acpica/executer/exoparg2.c		optional acpi
 contrib/dev/acpica/executer/exoparg3.c		optional acpi
 contrib/dev/acpica/executer/exoparg6.c		optional acpi
 contrib/dev/acpica/executer/exprep.c		optional acpi
 contrib/dev/acpica/executer/exregion.c		optional acpi
 contrib/dev/acpica/executer/exresnte.c		optional acpi
 contrib/dev/acpica/executer/exresolv.c		optional acpi
 contrib/dev/acpica/executer/exresop.c		optional acpi
 contrib/dev/acpica/executer/exstore.c		optional acpi
 contrib/dev/acpica/executer/exstoren.c		optional acpi
 contrib/dev/acpica/executer/exstorob.c		optional acpi
 contrib/dev/acpica/executer/exsystem.c		optional acpi
 contrib/dev/acpica/executer/exutils.c		optional acpi
 contrib/dev/acpica/hardware/hwacpi.c		optional acpi
 contrib/dev/acpica/hardware/hwgpe.c		optional acpi
 contrib/dev/acpica/hardware/hwpci.c		optional acpi
 contrib/dev/acpica/hardware/hwregs.c		optional acpi
 contrib/dev/acpica/hardware/hwsleep.c		optional acpi
 contrib/dev/acpica/hardware/hwtimer.c		optional acpi
 contrib/dev/acpica/hardware/hwvalid.c		optional acpi
 contrib/dev/acpica/hardware/hwxface.c		optional acpi
 contrib/dev/acpica/namespace/nsaccess.c		optional acpi
 contrib/dev/acpica/namespace/nsalloc.c		optional acpi
 contrib/dev/acpica/namespace/nsdump.c		optional acpi
 contrib/dev/acpica/namespace/nseval.c		optional acpi
 contrib/dev/acpica/namespace/nsinit.c		optional acpi
 contrib/dev/acpica/namespace/nsload.c		optional acpi
 contrib/dev/acpica/namespace/nsnames.c		optional acpi
 contrib/dev/acpica/namespace/nsobject.c		optional acpi
 contrib/dev/acpica/namespace/nsparse.c		optional acpi
 contrib/dev/acpica/namespace/nspredef.c		optional acpi
 contrib/dev/acpica/namespace/nsrepair.c		optional acpi
 contrib/dev/acpica/namespace/nsrepair2.c	optional acpi
 contrib/dev/acpica/namespace/nssearch.c		optional acpi
 contrib/dev/acpica/namespace/nsutils.c		optional acpi
 contrib/dev/acpica/namespace/nswalk.c		optional acpi
 contrib/dev/acpica/namespace/nsxfeval.c		optional acpi
 contrib/dev/acpica/namespace/nsxfname.c		optional acpi
 contrib/dev/acpica/namespace/nsxfobj.c		optional acpi
 contrib/dev/acpica/parser/psargs.c		optional acpi
 contrib/dev/acpica/parser/psloop.c		optional acpi
 contrib/dev/acpica/parser/psopcode.c		optional acpi
 contrib/dev/acpica/parser/psparse.c		optional acpi
 contrib/dev/acpica/parser/psscope.c		optional acpi
 contrib/dev/acpica/parser/pstree.c		optional acpi
 contrib/dev/acpica/parser/psutils.c		optional acpi
 contrib/dev/acpica/parser/pswalk.c		optional acpi
 contrib/dev/acpica/parser/psxface.c		optional acpi
 contrib/dev/acpica/resources/rsaddr.c		optional acpi
 contrib/dev/acpica/resources/rscalc.c		optional acpi
 contrib/dev/acpica/resources/rscreate.c		optional acpi
 contrib/dev/acpica/resources/rsdump.c		optional acpi
 contrib/dev/acpica/resources/rsinfo.c		optional acpi
 contrib/dev/acpica/resources/rsio.c		optional acpi
 contrib/dev/acpica/resources/rsirq.c		optional acpi
 contrib/dev/acpica/resources/rslist.c		optional acpi
 contrib/dev/acpica/resources/rsmemory.c		optional acpi
 contrib/dev/acpica/resources/rsmisc.c		optional acpi
 contrib/dev/acpica/resources/rsutils.c		optional acpi
 contrib/dev/acpica/resources/rsxface.c		optional acpi
 contrib/dev/acpica/tables/tbfadt.c		optional acpi
 contrib/dev/acpica/tables/tbfind.c		optional acpi
 contrib/dev/acpica/tables/tbinstal.c		optional acpi
 contrib/dev/acpica/tables/tbutils.c		optional acpi
 contrib/dev/acpica/tables/tbxface.c		optional acpi
 contrib/dev/acpica/tables/tbxfroot.c		optional acpi
 contrib/dev/acpica/utilities/utalloc.c		optional acpi
 contrib/dev/acpica/utilities/utcache.c		optional acpi
 contrib/dev/acpica/utilities/utcopy.c		optional acpi
 contrib/dev/acpica/utilities/utdebug.c		optional acpi
 contrib/dev/acpica/utilities/utdecode.c		optional acpi
 contrib/dev/acpica/utilities/utdelete.c		optional acpi
 contrib/dev/acpica/utilities/uteval.c		optional acpi
 contrib/dev/acpica/utilities/utglobal.c		optional acpi
 contrib/dev/acpica/utilities/utids.c		optional acpi
 contrib/dev/acpica/utilities/utinit.c		optional acpi
 contrib/dev/acpica/utilities/utlock.c		optional acpi
 contrib/dev/acpica/utilities/utmath.c		optional acpi
 contrib/dev/acpica/utilities/utmisc.c		optional acpi
 contrib/dev/acpica/utilities/utmutex.c		optional acpi
 contrib/dev/acpica/utilities/utobject.c		optional acpi
 contrib/dev/acpica/utilities/utosi.c		optional acpi
 contrib/dev/acpica/utilities/utresrc.c		optional acpi
 contrib/dev/acpica/utilities/utstate.c		optional acpi
 contrib/dev/acpica/utilities/utxface.c		optional acpi
 contrib/dev/acpica/utilities/utxferror.c	optional acpi
 contrib/ipfilter/netinet/fil.c	optional ipfilter inet \
 	compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN} -Wno-unused -I$S/contrib/ipfilter"
 contrib/ipfilter/netinet/ip_auth.c optional ipfilter inet \
 	compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter"
 contrib/ipfilter/netinet/ip_fil_freebsd.c optional ipfilter inet \
 	compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter"
 contrib/ipfilter/netinet/ip_frag.c optional ipfilter inet \
 	compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter"
 contrib/ipfilter/netinet/ip_log.c optional ipfilter inet \
 	compile-with "${NORMAL_C} -I$S/contrib/ipfilter"
 contrib/ipfilter/netinet/ip_nat.c optional ipfilter inet \
 	compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter"
 contrib/ipfilter/netinet/ip_proxy.c optional ipfilter inet \
 	compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN} -Wno-unused -I$S/contrib/ipfilter"
 contrib/ipfilter/netinet/ip_state.c optional ipfilter inet \
 	compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter"
 contrib/ipfilter/netinet/ip_lookup.c optional ipfilter inet \
 	compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN} -Wno-unused -Wno-error -I$S/contrib/ipfilter"
 contrib/ipfilter/netinet/ip_pool.c optional ipfilter inet \
 	compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter"
 contrib/ipfilter/netinet/ip_htable.c optional ipfilter inet \
 	compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter"
 contrib/ipfilter/netinet/ip_sync.c optional ipfilter inet \
 	compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter"
 contrib/ipfilter/netinet/mlfk_ipl.c optional ipfilter inet \
 	compile-with "${NORMAL_C} -I$S/contrib/ipfilter"
 contrib/libfdt/fdt.c			optional	fdt
 contrib/libfdt/fdt_ro.c			optional	fdt
 contrib/libfdt/fdt_rw.c			optional	fdt
 contrib/libfdt/fdt_strerror.c		optional	fdt
 contrib/libfdt/fdt_sw.c			optional	fdt
 contrib/libfdt/fdt_wip.c		optional	fdt
 contrib/ngatm/netnatm/api/cc_conn.c optional ngatm_ccatm \
 	compile-with "${NORMAL_C_NOWERROR} -I$S/contrib/ngatm"
 contrib/ngatm/netnatm/api/cc_data.c optional ngatm_ccatm \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 contrib/ngatm/netnatm/api/cc_dump.c optional ngatm_ccatm \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 contrib/ngatm/netnatm/api/cc_port.c optional ngatm_ccatm \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 contrib/ngatm/netnatm/api/cc_sig.c optional ngatm_ccatm \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 contrib/ngatm/netnatm/api/cc_user.c optional ngatm_ccatm \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 contrib/ngatm/netnatm/api/unisap.c optional ngatm_ccatm \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 contrib/ngatm/netnatm/misc/straddr.c optional ngatm_atmbase \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 contrib/ngatm/netnatm/misc/unimsg_common.c optional ngatm_atmbase \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 contrib/ngatm/netnatm/msg/traffic.c optional ngatm_atmbase \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 contrib/ngatm/netnatm/msg/uni_ie.c optional ngatm_atmbase \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 contrib/ngatm/netnatm/msg/uni_msg.c optional ngatm_atmbase \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 contrib/ngatm/netnatm/saal/saal_sscfu.c	optional ngatm_sscfu \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 contrib/ngatm/netnatm/saal/saal_sscop.c	optional ngatm_sscop \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 contrib/ngatm/netnatm/sig/sig_call.c optional ngatm_uni \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 contrib/ngatm/netnatm/sig/sig_coord.c optional ngatm_uni \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 contrib/ngatm/netnatm/sig/sig_party.c optional ngatm_uni \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 contrib/ngatm/netnatm/sig/sig_print.c optional ngatm_uni \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 contrib/ngatm/netnatm/sig/sig_reset.c optional ngatm_uni \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 contrib/ngatm/netnatm/sig/sig_uni.c optional ngatm_uni \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 contrib/ngatm/netnatm/sig/sig_unimsgcpy.c optional ngatm_uni \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 contrib/ngatm/netnatm/sig/sig_verify.c optional ngatm_uni \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 contrib/pf/net/if_pflog.c	optional pflog pf inet \
 	compile-with "${NORMAL_C} -I$S/contrib/pf"
 contrib/pf/net/if_pfsync.c	optional pfsync pf inet \
 	compile-with "${NORMAL_C} -I$S/contrib/pf"
 contrib/pf/net/pf.c		optional pf inet \
 	compile-with "${NORMAL_C} -I$S/contrib/pf"
 contrib/pf/net/pf_if.c		optional pf inet \
 	compile-with "${NORMAL_C} -I$S/contrib/pf"
 contrib/pf/net/pf_ioctl.c	optional pf inet \
 	compile-with "${NORMAL_C} -I$S/contrib/pf"
 contrib/pf/net/pf_lb.c		optional pf inet \
 	compile-with "${NORMAL_C} -I$S/contrib/pf"
 contrib/pf/net/pf_norm.c	optional pf inet \
 	compile-with "${NORMAL_C} -I$S/contrib/pf"
 contrib/pf/net/pf_osfp.c	optional pf inet \
 	compile-with "${NORMAL_C} -I$S/contrib/pf"
 contrib/pf/net/pf_ruleset.c	optional pf inet \
 	compile-with "${NORMAL_C} -I$S/contrib/pf"
 contrib/pf/net/pf_table.c	optional pf inet \
 	compile-with "${NORMAL_C} -I$S/contrib/pf"
 contrib/pf/netinet/in4_cksum.c	optional pf inet
 crypto/blowfish/bf_ecb.c	optional ipsec 
 crypto/blowfish/bf_skey.c	optional crypto | ipsec 
 crypto/camellia/camellia.c	optional crypto | ipsec 
 crypto/camellia/camellia-api.c	optional crypto | ipsec 
 crypto/des/des_ecb.c		optional crypto | ipsec | netsmb
 crypto/des/des_setkey.c		optional crypto | ipsec | netsmb
 crypto/rc4/rc4.c		optional netgraph_mppc_encryption | kgssapi
 crypto/rijndael/rijndael-alg-fst.c optional crypto | geom_bde | \
 					 ipsec | random | wlan_ccmp
 crypto/rijndael/rijndael-api-fst.c optional geom_bde | random
 crypto/rijndael/rijndael-api.c	optional crypto | ipsec | wlan_ccmp
 crypto/sha1.c			optional carp | crypto | ipsec | \
 					 netgraph_mppc_encryption | sctp
 crypto/sha2/sha2.c		optional crypto | geom_bde | ipsec | random | \
 					 sctp
 ddb/db_access.c			optional	ddb
 ddb/db_break.c			optional	ddb
 ddb/db_capture.c		optional	ddb
 ddb/db_command.c		optional	ddb
 ddb/db_examine.c		optional	ddb
 ddb/db_expr.c			optional	ddb
 ddb/db_input.c			optional	ddb
 ddb/db_lex.c			optional	ddb
 ddb/db_main.c			optional	ddb
 ddb/db_output.c			optional	ddb
 ddb/db_print.c			optional	ddb
 ddb/db_ps.c			optional	ddb
 ddb/db_run.c			optional	ddb
 ddb/db_script.c			optional	ddb
 ddb/db_sym.c			optional	ddb
 ddb/db_thread.c			optional	ddb
 ddb/db_textdump.c		optional	ddb
 ddb/db_variables.c		optional	ddb
 ddb/db_watch.c			optional	ddb
 ddb/db_write_cmd.c		optional	ddb
 #dev/dpt/dpt_control.c		optional dpt
 dev/aac/aac.c			optional aac
 dev/aac/aac_cam.c		optional aacp aac
 dev/aac/aac_debug.c		optional aac
 dev/aac/aac_disk.c		optional aac
 dev/aac/aac_linux.c		optional aac compat_linux
 dev/aac/aac_pci.c		optional aac pci
 dev/aacraid/aacraid.c		optional aacraid
 dev/aacraid/aacraid_cam.c	optional aacraid scbus
 dev/aacraid/aacraid_debug.c	optional aacraid
 dev/aacraid/aacraid_linux.c	optional aacraid compat_linux
 dev/aacraid/aacraid_pci.c	optional aacraid pci
 dev/acpi_support/acpi_wmi.c	optional acpi_wmi acpi
 dev/acpi_support/acpi_asus.c	optional acpi_asus acpi
 dev/acpi_support/acpi_fujitsu.c	optional acpi_fujitsu acpi
 dev/acpi_support/acpi_hp.c	optional acpi_hp acpi
 dev/acpi_support/acpi_ibm.c	optional acpi_ibm acpi
 dev/acpi_support/acpi_panasonic.c optional acpi_panasonic acpi
 dev/acpi_support/acpi_sony.c	optional acpi_sony acpi
 dev/acpi_support/acpi_toshiba.c	optional acpi_toshiba acpi
 dev/acpi_support/atk0110.c	optional aibs acpi
 dev/acpica/Osd/OsdDebug.c	optional acpi
 dev/acpica/Osd/OsdHardware.c	optional acpi
 dev/acpica/Osd/OsdInterrupt.c	optional acpi
 dev/acpica/Osd/OsdMemory.c	optional acpi
 dev/acpica/Osd/OsdSchedule.c	optional acpi
 dev/acpica/Osd/OsdStream.c	optional acpi
 dev/acpica/Osd/OsdSynch.c	optional acpi
 dev/acpica/Osd/OsdTable.c	optional acpi
 dev/acpica/acpi.c		optional acpi
 dev/acpica/acpi_acad.c		optional acpi
 dev/acpica/acpi_battery.c	optional acpi
 dev/acpica/acpi_button.c	optional acpi
 dev/acpica/acpi_cmbat.c		optional acpi
 dev/acpica/acpi_cpu.c		optional acpi
 dev/acpica/acpi_ec.c		optional acpi
 dev/acpica/acpi_hpet.c		optional acpi
 dev/acpica/acpi_isab.c		optional acpi isa
 dev/acpica/acpi_lid.c		optional acpi
 dev/acpica/acpi_package.c	optional acpi
 dev/acpica/acpi_pci.c		optional acpi pci
 dev/acpica/acpi_pci_link.c	optional acpi pci
 dev/acpica/acpi_pcib.c		optional acpi pci
 dev/acpica/acpi_pcib_acpi.c	optional acpi pci
 dev/acpica/acpi_pcib_pci.c	optional acpi pci
 dev/acpica/acpi_perf.c		optional acpi
 dev/acpica/acpi_powerres.c	optional acpi
 dev/acpica/acpi_quirk.c		optional acpi
 dev/acpica/acpi_resource.c	optional acpi
 dev/acpica/acpi_smbat.c		optional acpi
 dev/acpica/acpi_thermal.c	optional acpi
 dev/acpica/acpi_throttle.c	optional acpi
 dev/acpica/acpi_timer.c		optional acpi
 dev/acpica/acpi_video.c		optional acpi_video acpi
 dev/acpica/acpi_dock.c		optional acpi_dock acpi
 dev/adlink/adlink.c		optional adlink
 dev/advansys/adv_eisa.c		optional adv eisa
 dev/advansys/adv_pci.c		optional adv pci
 dev/advansys/advansys.c		optional adv
 dev/advansys/advlib.c		optional adv
 dev/advansys/advmcode.c		optional adv
 dev/advansys/adw_pci.c		optional adw pci
 dev/advansys/adwcam.c		optional adw
 dev/advansys/adwlib.c		optional adw
 dev/advansys/adwmcode.c		optional adw
 dev/ae/if_ae.c			optional ae pci
 dev/age/if_age.c		optional age pci
 dev/agp/agp.c			optional agp pci
 dev/agp/agp_if.m			optional agp pci
 dev/aha/aha.c			optional aha
 dev/aha/aha_isa.c		optional aha isa
 dev/aha/aha_mca.c		optional aha mca
 dev/ahb/ahb.c			optional ahb eisa
 dev/ahci/ahci.c			optional ahci pci
 dev/aic/aic.c			optional aic
 dev/aic/aic_pccard.c		optional aic pccard
 dev/aic7xxx/ahc_eisa.c		optional ahc eisa
 dev/aic7xxx/ahc_isa.c		optional ahc isa
 dev/aic7xxx/ahc_pci.c		optional ahc pci \
 	compile-with "${NORMAL_C} ${NO_WCONSTANT_CONVERSION}"
 dev/aic7xxx/ahd_pci.c		optional ahd pci \
 	compile-with "${NORMAL_C} ${NO_WCONSTANT_CONVERSION}"
 dev/aic7xxx/aic7770.c		optional ahc
 dev/aic7xxx/aic79xx.c		optional ahd pci
 dev/aic7xxx/aic79xx_osm.c	optional ahd pci
 dev/aic7xxx/aic79xx_pci.c	optional ahd pci
 dev/aic7xxx/aic7xxx.c		optional ahc
 dev/aic7xxx/aic7xxx_93cx6.c	optional ahc
 dev/aic7xxx/aic7xxx_osm.c	optional ahc
 dev/aic7xxx/aic7xxx_pci.c	optional ahc pci
 dev/alc/if_alc.c		optional alc pci
 dev/ale/if_ale.c		optional ale pci
 dev/amd/amd.c			optional amd
 dev/amr/amr.c			optional amr
 dev/amr/amr_cam.c		optional amrp amr
 dev/amr/amr_disk.c		optional amr
 dev/amr/amr_linux.c		optional amr compat_linux
 dev/amr/amr_pci.c		optional amr pci
 dev/an/if_an.c			optional an
 dev/an/if_an_isa.c		optional an isa
 dev/an/if_an_pccard.c		optional an pccard
 dev/an/if_an_pci.c		optional an pci
 dev/asr/asr.c			optional asr pci \
 	compile-with "${NORMAL_C} ${NO_WARRAY_BOUNDS}"
 #
 dev/ata/ata_if.m		optional ata | atacore
 dev/ata/ata-all.c		optional ata | atacore
 dev/ata/ata-dma.c		optional ata | atacore
 dev/ata/ata-lowlevel.c		optional ata | atacore
 dev/ata/ata-queue.c		optional ata | atacore
 dev/ata/ata-sata.c		optional ata | atacore
 dev/ata/ata-card.c		optional ata pccard | atapccard
 dev/ata/ata-cbus.c		optional ata pc98 | atapc98
 dev/ata/ata-isa.c		optional ata isa | ataisa
 dev/ata/ata-pci.c		optional ata pci | atapci
 dev/ata/chipsets/ata-ahci.c	optional ata pci | ataahci | ataacerlabs | \
 					 ataati | ataintel | atajmicron | \
 					 atavia | atanvidia
 dev/ata/chipsets/ata-acard.c	optional ata pci | ataacard
 dev/ata/chipsets/ata-acerlabs.c	optional ata pci | ataacerlabs
 dev/ata/chipsets/ata-adaptec.c	optional ata pci | ataadaptec
 dev/ata/chipsets/ata-amd.c	optional ata pci | ataamd
 dev/ata/chipsets/ata-ati.c	optional ata pci | ataati
 dev/ata/chipsets/ata-cenatek.c	optional ata pci | atacenatek
 dev/ata/chipsets/ata-cypress.c	optional ata pci | atacypress
 dev/ata/chipsets/ata-cyrix.c	optional ata pci | atacyrix
 dev/ata/chipsets/ata-highpoint.c	optional ata pci | atahighpoint
 dev/ata/chipsets/ata-intel.c	optional ata pci | ataintel
 dev/ata/chipsets/ata-ite.c	optional ata pci | ataite
 dev/ata/chipsets/ata-jmicron.c	optional ata pci | atajmicron
 dev/ata/chipsets/ata-marvell.c	optional ata pci | atamarvell | ataadaptec
 dev/ata/chipsets/ata-micron.c	optional ata pci | atamicron
 dev/ata/chipsets/ata-national.c	optional ata pci | atanational
 dev/ata/chipsets/ata-netcell.c	optional ata pci | atanetcell
 dev/ata/chipsets/ata-nvidia.c	optional ata pci | atanvidia
 dev/ata/chipsets/ata-promise.c	optional ata pci | atapromise
 dev/ata/chipsets/ata-serverworks.c	optional ata pci | ataserverworks
 dev/ata/chipsets/ata-siliconimage.c	optional ata pci | atasiliconimage | ataati
 dev/ata/chipsets/ata-sis.c	optional ata pci | atasis
 dev/ata/chipsets/ata-via.c	optional ata pci | atavia
 dev/ata/ata-disk.c		optional atadisk
 dev/ata/ata-raid.c		optional ataraid
 dev/ata/atapi-cd.c		optional atapicd
 dev/ata/atapi-fd.c		optional atapifd
 dev/ata/atapi-tape.c		optional atapist
 dev/ata/atapi-cam.c		optional atapicam
 #
 dev/ath/if_ath_pci.c		optional ath_pci pci \
 	compile-with "${NORMAL_C} -I$S/dev/ath"
 #
 dev/ath/if_ath_ahb.c		optional ath_ahb \
 	compile-with "${NORMAL_C} -I$S/dev/ath"
 #
 # XXX Work around clang warning, until maintainer approves fix.
 dev/ath/if_ath.c		optional ath \
 	compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED} -I$S/dev/ath"
 dev/ath/if_ath_debug.c		optional ath \
 	compile-with "${NORMAL_C} -I$S/dev/ath"
 dev/ath/if_ath_keycache.c	optional ath \
 	compile-with "${NORMAL_C} -I$S/dev/ath"
 dev/ath/if_ath_tx.c		optional ath \
 	compile-with "${NORMAL_C} -I$S/dev/ath"
 dev/ath/if_ath_tx_ht.c		optional ath \
 	compile-with "${NORMAL_C} -I$S/dev/ath"
 dev/ath/if_ath_sysctl.c		optional ath \
 	compile-with "${NORMAL_C} -I$S/dev/ath"
 dev/ath/ah_osdep.c		optional ath \
 	compile-with "${NORMAL_C} -I$S/dev/ath"
 #
 dev/ath/ath_hal/ah.c		optional ath \
 	compile-with "${NORMAL_C} -I$S/dev/ath"
 dev/ath/ath_hal/ah_eeprom_v1.c	optional ath_hal | ath_ar5210 \
 	compile-with "${NORMAL_C} -I$S/dev/ath"
 dev/ath/ath_hal/ah_eeprom_v3.c	optional ath_hal | ath_ar5211 | ath_ar5212 \
 	compile-with "${NORMAL_C} -I$S/dev/ath"
 dev/ath/ath_hal/ah_eeprom_v14.c \
 	optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \
 	compile-with "${NORMAL_C} -I$S/dev/ath"
 dev/ath/ath_hal/ah_eeprom_v4k.c \
 	optional ath_hal | ath_ar9285 \
 	compile-with "${NORMAL_C} -I$S/dev/ath"
 # XXX Work around clang warning, until maintainer approves fix.
 dev/ath/ath_hal/ah_eeprom_9287.c \
 	optional ath_hal | ath_ar9287 \
 	compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED} -I$S/dev/ath"
 dev/ath/ath_hal/ah_regdomain.c	optional ath \
 	compile-with "${NORMAL_C} ${NO_WSHIFT_COUNT_NEGATIVE} ${NO_WSHIFT_COUNT_OVERFLOW} -I$S/dev/ath"
 # ar5210
 dev/ath/ath_hal/ar5210/ar5210_attach.c		optional ath_hal | ath_ar5210 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5210/ar5210_beacon.c		optional ath_hal | ath_ar5210 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5210/ar5210_interrupts.c	optional ath_hal | ath_ar5210 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5210/ar5210_keycache.c	optional ath_hal | ath_ar5210 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5210/ar5210_misc.c		optional ath_hal | ath_ar5210 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5210/ar5210_phy.c		optional ath_hal | ath_ar5210 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5210/ar5210_power.c		optional ath_hal | ath_ar5210 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5210/ar5210_recv.c		optional ath_hal | ath_ar5210 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5210/ar5210_reset.c		optional ath_hal | ath_ar5210 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5210/ar5210_xmit.c		optional ath_hal | ath_ar5210 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 # ar5211
 dev/ath/ath_hal/ar5211/ar5211_attach.c		optional ath_hal | ath_ar5211 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5211/ar5211_beacon.c		optional ath_hal | ath_ar5211 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5211/ar5211_interrupts.c	optional ath_hal | ath_ar5211 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5211/ar5211_keycache.c	optional ath_hal | ath_ar5211 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5211/ar5211_misc.c		optional ath_hal | ath_ar5211 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5211/ar5211_phy.c		optional ath_hal | ath_ar5211 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5211/ar5211_power.c		optional ath_hal | ath_ar5211 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5211/ar5211_recv.c		optional ath_hal | ath_ar5211 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5211/ar5211_reset.c		optional ath_hal | ath_ar5211 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5211/ar5211_xmit.c		optional ath_hal | ath_ar5211 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 # ar5212
 dev/ath/ath_hal/ar5212/ar5212_ani.c \
 	optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
 	ath_ar9285 ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5212/ar5212_attach.c \
 	optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
 	ath_ar9285 ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5212/ar5212_beacon.c \
 	optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
 	ath_ar9285 ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5212/ar5212_eeprom.c \
 	optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
 	ath_ar9285 ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5212/ar5212_gpio.c \
 	optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
 	ath_ar9285 ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5212/ar5212_interrupts.c \
 	optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
 	ath_ar9285 ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5212/ar5212_keycache.c \
 	optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
 	ath_ar9285 ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5212/ar5212_misc.c \
 	optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
 	ath_ar9285 ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5212/ar5212_phy.c \
 	optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
 	ath_ar9285 ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5212/ar5212_power.c \
 	optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
 	ath_ar9285 ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5212/ar5212_recv.c \
 	optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
 	ath_ar9285 ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5212/ar5212_reset.c \
 	optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
 	ath_ar9285 ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5212/ar5212_rfgain.c \
 	optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
 	ath_ar9285 ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5212/ar5212_xmit.c \
 	optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
 	ath_ar9285 ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 # ar5416 (depends on ar5212)
 dev/ath/ath_hal/ar5416/ar5416_ani.c \
 	optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \
 	ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5416/ar5416_attach.c \
 	optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \
 	ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5416/ar5416_beacon.c \
 	optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \
 	ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5416/ar5416_cal.c \
 	optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \
 	ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5416/ar5416_cal_iq.c \
 	optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \
 	ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c \
 	optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \
 	ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c \
 	optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \
 	ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5416/ar5416_eeprom.c \
 	optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \
 	ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5416/ar5416_gpio.c \
 	optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \
 	ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5416/ar5416_interrupts.c \
 	optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \
 	ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5416/ar5416_keycache.c \
 	optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \
 	ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5416/ar5416_misc.c \
 	optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \
 	ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5416/ar5416_phy.c \
 	optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \
 	ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5416/ar5416_power.c \
 	optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \
 	ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5416/ar5416_recv.c \
 	optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \
 	ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5416/ar5416_reset.c \
 	optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \
 	ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5416/ar5416_xmit.c \
 	optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \
 	ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 # ar9130 (depends upon ar5416) - also requires AH_SUPPORT_AR9130
 dev/ath/ath_hal/ar9001/ar9130_attach.c optional ath_hal | ath_ar9130 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar9001/ar9130_phy.c optional ath_hal | ath_ar9130 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar9001/ar9130_eeprom.c optional ath_hal | ath_ar9130 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 
 # ar9160 (depends on ar5416)
 dev/ath/ath_hal/ar9001/ar9160_attach.c optional ath_hal | ath_ar9160 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 # ar9280 (depends on ar5416)
 dev/ath/ath_hal/ar9002/ar9280_attach.c optional ath_hal | ath_ar9280 | \
 	ath_ar9285 \ 
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar9002/ar9280_olc.c optional ath_hal | ath_ar9280 | \
 	ath_ar9285 \ 
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 # ar9285 (depends on ar5416 and ar9280)
 dev/ath/ath_hal/ar9002/ar9285_attach.c optional ath_hal | ath_ar9285 \ 
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar9002/ar9285_reset.c optional ath_hal | ath_ar9285 \ 
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar9002/ar9285_cal.c optional ath_hal | ath_ar9285 \ 
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar9002/ar9285_phy.c optional ath_hal | ath_ar9285 \ 
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar9002/ar9285_diversity.c optional ath_hal | ath_ar9285 \ 
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 # ar9287 (depends on ar5416)
 dev/ath/ath_hal/ar9002/ar9287_attach.c optional ath_hal | ath_ar9287 \ 
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar9002/ar9287_reset.c optional ath_hal | ath_ar9287 \ 
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar9002/ar9287_cal.c optional ath_hal | ath_ar9287 \ 
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar9002/ar9287_olc.c optional ath_hal | ath_ar9287 \ 
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 
 # rf backends
 dev/ath/ath_hal/ar5212/ar2316.c	optional ath_rf2316 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5212/ar2317.c	optional ath_rf2317 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5212/ar2413.c	optional ath_hal | ath_rf2413 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5212/ar2425.c	optional ath_hal | ath_rf2425 | ath_rf2417 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5212/ar5111.c	optional ath_hal | ath_rf5111 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5212/ar5112.c	optional ath_hal | ath_rf5112 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5212/ar5413.c	optional ath_hal | ath_rf5413 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar5416/ar2133.c optional ath_hal | ath_ar5416 | ath_ar9160 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar9002/ar9280.c optional ath_hal | ath_ar9280 | ath_ar9285 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar9002/ar9285.c optional ath_hal | ath_ar9285 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 dev/ath/ath_hal/ar9002/ar9287.c optional ath_hal | ath_ar9287 \
 	compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
 # ath rate control algorithms
 dev/ath/ath_rate/amrr/amrr.c	optional ath_rate_amrr \
 	compile-with "${NORMAL_C} -I$S/dev/ath"
 dev/ath/ath_rate/onoe/onoe.c	optional ath_rate_onoe \
 	compile-with "${NORMAL_C} -I$S/dev/ath"
 dev/ath/ath_rate/sample/sample.c	optional ath_rate_sample \
 	compile-with "${NORMAL_C} -I$S/dev/ath"
 # ath DFS modules
 dev/ath/ath_dfs/null/dfs_null.c	optional	ath \
 	compile-with "${NORMAL_C} -I$S/dev/ath"
 # 
 dev/bce/if_bce.c		optional bce
 dev/bfe/if_bfe.c		optional bfe
 dev/bge/if_bge.c		optional bge
 dev/bktr/bktr_audio.c		optional bktr pci
 dev/bktr/bktr_card.c		optional bktr pci
 dev/bktr/bktr_core.c		optional bktr pci
 dev/bktr/bktr_i2c.c		optional bktr pci smbus
 dev/bktr/bktr_os.c		optional bktr pci
 dev/bktr/bktr_tuner.c		optional bktr pci
 dev/bktr/msp34xx.c		optional bktr pci
 dev/buslogic/bt.c		optional bt
 dev/buslogic/bt_eisa.c		optional bt eisa
 dev/buslogic/bt_isa.c		optional bt isa
 dev/buslogic/bt_mca.c		optional bt mca
 dev/buslogic/bt_pci.c		optional bt pci
 dev/bwi/bwimac.c		optional bwi
 dev/bwi/bwiphy.c		optional bwi
 dev/bwi/bwirf.c			optional bwi
 dev/bwi/if_bwi.c		optional bwi
 dev/bwi/if_bwi_pci.c		optional bwi pci
 # XXX Work around clang warning, until maintainer approves fix.
 dev/bwn/if_bwn.c		optional bwn siba_bwn \
 	compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}"
 dev/cardbus/cardbus.c		optional cardbus
 dev/cardbus/cardbus_cis.c	optional cardbus
 dev/cardbus/cardbus_device.c	optional cardbus
 dev/cas/if_cas.c		optional cas
 dev/cfi/cfi_core.c		optional cfi
 dev/cfi/cfi_dev.c		optional cfi
 dev/cfi/cfi_disk.c		optional cfid
 dev/ciss/ciss.c			optional ciss
 dev/cm/smc90cx6.c		optional cm
 dev/cmx/cmx.c			optional cmx
 dev/cmx/cmx_pccard.c		optional cmx pccard
 dev/cpufreq/ichss.c		optional cpufreq
 dev/cs/if_cs.c			optional cs
 dev/cs/if_cs_isa.c		optional cs isa
 dev/cs/if_cs_pccard.c		optional cs pccard
 dev/cxgb/cxgb_main.c		optional cxgb pci \
 	compile-with "${NORMAL_C} -I$S/dev/cxgb"
 dev/cxgb/cxgb_sge.c		optional cxgb pci \
 	compile-with "${NORMAL_C} -I$S/dev/cxgb"
 dev/cxgb/common/cxgb_mc5.c	optional cxgb pci \
 	compile-with "${NORMAL_C} -I$S/dev/cxgb"
 dev/cxgb/common/cxgb_vsc7323.c	optional cxgb pci \
 	compile-with "${NORMAL_C} -I$S/dev/cxgb"
 dev/cxgb/common/cxgb_vsc8211.c	optional cxgb pci \
 	compile-with "${NORMAL_C} -I$S/dev/cxgb"
 dev/cxgb/common/cxgb_ael1002.c	optional cxgb pci \
 	compile-with "${NORMAL_C} -I$S/dev/cxgb"
 dev/cxgb/common/cxgb_aq100x.c	optional cxgb pci \
 	compile-with "${NORMAL_C} -I$S/dev/cxgb"
 dev/cxgb/common/cxgb_mv88e1xxx.c	optional cxgb pci \
 	compile-with "${NORMAL_C} -I$S/dev/cxgb"
 dev/cxgb/common/cxgb_xgmac.c	optional cxgb pci \
 	compile-with "${NORMAL_C} -I$S/dev/cxgb"
 dev/cxgb/common/cxgb_t3_hw.c	optional cxgb pci \
 	compile-with "${NORMAL_C} -I$S/dev/cxgb"
 dev/cxgb/common/cxgb_tn1010.c	optional cxgb pci \
 	compile-with "${NORMAL_C} -I$S/dev/cxgb"	
 dev/cxgb/sys/uipc_mvec.c	optional cxgb pci \
 	compile-with "${NORMAL_C} -I$S/dev/cxgb"
 dev/cxgb/cxgb_t3fw.c		optional cxgb cxgb_t3fw \
 	compile-with "${NORMAL_C} -I$S/dev/cxgb"
 dev/cxgbe/t4_main.c		optional cxgbe pci \
 	compile-with "${NORMAL_C} -I$S/dev/cxgbe"
 dev/cxgbe/t4_sge.c		optional cxgbe pci \
 	compile-with "${NORMAL_C} -I$S/dev/cxgbe"
 dev/cxgbe/t4_l2t.c		optional cxgbe pci \
 	compile-with "${NORMAL_C} -I$S/dev/cxgbe"
 dev/cxgbe/common/t4_hw.c	optional cxgbe pci \
 	compile-with "${NORMAL_C} -I$S/dev/cxgbe"
 t4fw_cfg.c		optional cxgbe					\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk t4fw_cfg.fw:t4fw_cfg t4fw_cfg_uwire.fw:t4fw_cfg_uwire t4fw.fw:t4fw -mt4fw_cfg -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
 	clean		"t4fw_cfg.c"
 t4fw_cfg.fwo		optional cxgbe					\
 	dependency	"t4fw_cfg.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"t4fw_cfg.fwo"
 t4fw_cfg.fw		optional cxgbe					\
 	dependency	"$S/dev/cxgbe/firmware/t4fw_cfg.txt"		\
 	compile-with	"${CP} ${.ALLSRC} ${.TARGET}"			\
 	no-obj no-implicit-rule						\
 	clean		"t4fw_cfg.fw"
 t4fw_cfg_uwire.fwo	optional cxgbe					\
 	dependency	"t4fw_cfg_uwire.fw"				\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"t4fw_cfg_uwire.fwo"
 t4fw_cfg_uwire.fw	optional cxgbe					\
 	dependency	"$S/dev/cxgbe/firmware/t4fw_cfg_uwire.txt"	\
 	compile-with	"${CP} ${.ALLSRC} ${.TARGET}"			\
 	no-obj no-implicit-rule						\
 	clean		"t4fw_cfg_uwire.fw"
 t4fw.fwo		optional cxgbe					\
 	dependency	"t4fw.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"t4fw.fwo"
 t4fw.fw			optional cxgbe					\
 	dependency	"$S/dev/cxgbe/firmware/t4fw-1.11.27.0.bin.uu"	\
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"t4fw.fw"
 t5fw_cfg.c		optional cxgbe					\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk t5fw_cfg.fw:t5fw_cfg t5fw.fw:t5fw -mt5fw_cfg -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
 	clean		"t5fw_cfg.c"
 t5fw_cfg.fwo		optional cxgbe					\
 	dependency	"t5fw_cfg.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"t5fw_cfg.fwo"
 t5fw_cfg.fw		optional cxgbe					\
 	dependency	"$S/dev/cxgbe/firmware/t5fw_cfg.txt"		\
 	compile-with	"${CP} ${.ALLSRC} ${.TARGET}"			\
 	no-obj no-implicit-rule						\
 	clean		"t5fw_cfg.fw"
 t5fw.fwo		optional cxgbe					\
 	dependency	"t5fw.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"t5fw.fwo"
 t5fw.fw			optional cxgbe					\
 	dependency	"$S/dev/cxgbe/firmware/t5fw-1.11.27.0.bin.uu"	\
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"t5fw.fw"
 dev/cy/cy.c			optional cy
 dev/cy/cy_isa.c			optional cy isa
 dev/cy/cy_pci.c			optional cy pci
 dev/dc/if_dc.c			optional dc pci
 dev/dc/dcphy.c			optional dc pci
 dev/dc/pnphy.c			optional dc pci
 dev/dcons/dcons.c		optional dcons
 dev/dcons/dcons_crom.c		optional dcons_crom
 dev/dcons/dcons_os.c		optional dcons
 dev/de/if_de.c			optional de pci
 dev/digi/CX.c			optional digi_CX
 dev/digi/CX_PCI.c		optional digi_CX_PCI
 dev/digi/EPCX.c			optional digi_EPCX
 dev/digi/EPCX_PCI.c		optional digi_EPCX_PCI
 dev/digi/Xe.c			optional digi_Xe
 dev/digi/Xem.c			optional digi_Xem
 dev/digi/Xr.c			optional digi_Xr
 dev/digi/digi.c			optional digi
 dev/digi/digi_isa.c		optional digi isa
 dev/digi/digi_pci.c		optional digi pci
 dev/dpt/dpt_eisa.c		optional dpt eisa
 dev/dpt/dpt_pci.c		optional dpt pci
 dev/dpt/dpt_scsi.c		optional dpt
 dev/drm/ati_pcigart.c		optional drm
 dev/drm/drm_agpsupport.c	optional drm
 dev/drm/drm_auth.c		optional drm
 dev/drm/drm_bufs.c		optional drm
 dev/drm/drm_context.c		optional drm
 dev/drm/drm_dma.c		optional drm
 dev/drm/drm_drawable.c		optional drm
 dev/drm/drm_drv.c		optional drm
 dev/drm/drm_fops.c		optional drm
 dev/drm/drm_hashtab.c		optional drm
 dev/drm/drm_ioctl.c		optional drm
 dev/drm/drm_irq.c		optional drm
 dev/drm/drm_lock.c		optional drm
 dev/drm/drm_memory.c		optional drm
 dev/drm/drm_mm.c		optional drm
 dev/drm/drm_pci.c		optional drm
 dev/drm/drm_scatter.c		optional drm
 dev/drm/drm_sman.c		optional drm
 dev/drm/drm_sysctl.c		optional drm
 dev/drm/drm_vm.c		optional drm
 dev/drm/i915_dma.c		optional i915drm
 dev/drm/i915_drv.c		optional i915drm
 dev/drm/i915_irq.c		optional i915drm
 dev/drm/i915_mem.c		optional i915drm
 dev/drm/i915_suspend.c		optional i915drm
 dev/drm/mach64_dma.c		optional mach64drm
 dev/drm/mach64_drv.c		optional mach64drm
 dev/drm/mach64_irq.c		optional mach64drm
 dev/drm/mach64_state.c		optional mach64drm
 dev/drm/mga_dma.c		optional mgadrm
 dev/drm/mga_drv.c		optional mgadrm
 dev/drm/mga_irq.c		optional mgadrm
 dev/drm/mga_state.c		optional mgadrm \
 	compile-with "${NORMAL_C} -finline-limit=13500"
 dev/drm/mga_warp.c		optional mgadrm
 dev/drm/r128_cce.c		optional r128drm \
 	compile-with "${NORMAL_C} ${NO_WUNUSED_VALUE} ${NO_WCONSTANT_CONVERSION}"
 dev/drm/r128_drv.c		optional r128drm
 dev/drm/r128_irq.c		optional r128drm
 dev/drm/r128_state.c		optional r128drm \
 	compile-with "${NORMAL_C} ${NO_WUNUSED_VALUE} -finline-limit=13500"
 dev/drm/r300_cmdbuf.c		optional radeondrm
 dev/drm/r600_blit.c		optional radeondrm
 dev/drm/r600_cp.c		optional radeondrm \
 	compile-with "${NORMAL_C} ${NO_WUNUSED_VALUE} ${NO_WCONSTANT_CONVERSION}"
 dev/drm/radeon_cp.c		optional radeondrm \
 	compile-with "${NORMAL_C} ${NO_WUNUSED_VALUE} ${NO_WCONSTANT_CONVERSION}"
 dev/drm/radeon_cs.c		optional radeondrm
 dev/drm/radeon_drv.c		optional radeondrm
 dev/drm/radeon_irq.c		optional radeondrm
 dev/drm/radeon_mem.c		optional radeondrm
 dev/drm/radeon_state.c		optional radeondrm
 dev/drm/savage_bci.c		optional savagedrm
 dev/drm/savage_drv.c		optional savagedrm
 dev/drm/savage_state.c		optional savagedrm
 dev/drm/sis_drv.c		optional sisdrm
 dev/drm/sis_ds.c		optional sisdrm
 dev/drm/sis_mm.c		optional sisdrm
 dev/drm/tdfx_drv.c		optional tdfxdrm
 dev/drm/via_dma.c		optional viadrm
 dev/drm/via_dmablit.c		optional viadrm
 dev/drm/via_drv.c		optional viadrm
 dev/drm/via_irq.c		optional viadrm
 dev/drm/via_map.c		optional viadrm
 dev/drm/via_mm.c		optional viadrm
 dev/drm/via_verifier.c		optional viadrm
 dev/drm/via_video.c		optional viadrm
 dev/ed/if_ed.c			optional ed
 dev/ed/if_ed_novell.c		optional ed
 dev/ed/if_ed_rtl80x9.c		optional ed
 dev/ed/if_ed_pccard.c		optional ed pccard
 dev/ed/if_ed_pci.c		optional ed pci
 dev/eisa/eisa_if.m		standard
 dev/eisa/eisaconf.c		optional eisa
 dev/e1000/if_em.c		optional em \
 	compile-with "${NORMAL_C} -I$S/dev/e1000"
 dev/e1000/if_lem.c		optional em \
 	compile-with "${NORMAL_C} -I$S/dev/e1000"
 dev/e1000/if_igb.c		optional igb \
 	compile-with "${NORMAL_C} -I$S/dev/e1000"
 dev/e1000/e1000_80003es2lan.c	optional em | igb \
 	compile-with "${NORMAL_C} -I$S/dev/e1000"
 dev/e1000/e1000_82540.c		optional em | igb \
 	compile-with "${NORMAL_C} -I$S/dev/e1000"
 dev/e1000/e1000_82541.c		optional em | igb \
 	compile-with "${NORMAL_C} -I$S/dev/e1000"
 dev/e1000/e1000_82542.c		optional em | igb \
 	compile-with "${NORMAL_C} -I$S/dev/e1000"
 dev/e1000/e1000_82543.c		optional em | igb \
 	compile-with "${NORMAL_C} -I$S/dev/e1000"
 dev/e1000/e1000_82571.c		optional em | igb \
 	compile-with "${NORMAL_C} -I$S/dev/e1000"
 dev/e1000/e1000_82575.c		optional em | igb \
 	compile-with "${NORMAL_C} -I$S/dev/e1000"
 dev/e1000/e1000_ich8lan.c	optional em | igb \
 	compile-with "${NORMAL_C} -I$S/dev/e1000"
 dev/e1000/e1000_i210.c		optional em | igb \
 	compile-with "${NORMAL_C} -I$S/dev/e1000"
 dev/e1000/e1000_api.c		optional em | igb \
 	compile-with "${NORMAL_C} -I$S/dev/e1000"
 dev/e1000/e1000_mac.c		optional em | igb \
 	compile-with "${NORMAL_C} -I$S/dev/e1000"
 dev/e1000/e1000_manage.c	optional em | igb \
 	compile-with "${NORMAL_C} -I$S/dev/e1000"
 dev/e1000/e1000_nvm.c		optional em | igb \
 	compile-with "${NORMAL_C} -I$S/dev/e1000"
 dev/e1000/e1000_phy.c		optional em | igb \
 	compile-with "${NORMAL_C} -I$S/dev/e1000"
 dev/e1000/e1000_vf.c		optional em | igb \
 	compile-with "${NORMAL_C} -I$S/dev/e1000"
 dev/e1000/e1000_mbx.c		optional em | igb \
 	compile-with "${NORMAL_C} -I$S/dev/e1000"
 dev/e1000/e1000_osdep.c		optional em | igb \
 	compile-with "${NORMAL_C} -I$S/dev/e1000"
 dev/et/if_et.c			optional et
 dev/en/if_en_pci.c		optional en pci
 dev/en/midway.c			optional en
 dev/ep/if_ep.c			optional ep
 dev/ep/if_ep_eisa.c		optional ep eisa
 dev/ep/if_ep_isa.c		optional ep isa
 dev/ep/if_ep_mca.c		optional ep mca
 dev/ep/if_ep_pccard.c		optional ep pccard
 dev/esp/esp_pci.c		optional esp pci
 dev/esp/ncr53c9x.c		optional esp
 dev/ex/if_ex.c			optional ex
 dev/ex/if_ex_isa.c		optional ex isa
 dev/ex/if_ex_pccard.c		optional ex pccard
 dev/exca/exca.c			optional cbb
 dev/fatm/if_fatm.c		optional fatm pci
 dev/fb/fbd.c			optional fbd | vt
 dev/fb/fb_if.m			standard
 dev/fb/splash.c			optional sc splash
 dev/fdt/fdt_common.c		optional fdt
 dev/fdt/fdt_pci.c		optional fdt pci
 dev/fdt/fdt_static_dtb.S	optional fdt fdt_dtb_static
 dev/fdt/fdtbus.c		optional fdt
 dev/fdt/simplebus.c		optional fdt
 dev/fe/if_fe.c			optional fe
 dev/fe/if_fe_pccard.c		optional fe pccard
 dev/firewire/firewire.c		optional firewire
 dev/firewire/fwcrom.c		optional firewire
 dev/firewire/fwdev.c		optional firewire
 dev/firewire/fwdma.c		optional firewire
 dev/firewire/fwmem.c		optional firewire
 dev/firewire/fwohci.c		optional firewire
 dev/firewire/fwohci_pci.c	optional firewire pci
 dev/firewire/if_fwe.c		optional fwe
 dev/firewire/if_fwip.c		optional fwip
 dev/firewire/sbp.c		optional sbp
 dev/firewire/sbp_targ.c		optional sbp_targ
 dev/flash/at45d.c		optional at45d
 dev/flash/mx25l.c		optional mx25l
 dev/fxp/if_fxp.c		optional fxp
 dev/fxp/inphy.c			optional fxp
 dev/gem/if_gem.c		optional gem
 dev/gem/if_gem_pci.c		optional gem pci
 dev/gem/if_gem_sbus.c		optional gem sbus
 dev/gpio/gpiobus.c		optional gpio				\
 	dependency	"gpiobus_if.h"
 dev/gpio/gpioc.c		optional gpio				\
 	dependency	"gpio_if.h"
 dev/gpio/gpioiic.c		optional gpioiic
 dev/gpio/gpioled.c		optional gpioled
 dev/gpio/gpio_if.m		optional gpio
 dev/gpio/gpiobus_if.m		optional gpio
 dev/hatm/if_hatm.c		optional hatm pci
 dev/hatm/if_hatm_intr.c		optional hatm pci
 dev/hatm/if_hatm_ioctl.c	optional hatm pci
 dev/hatm/if_hatm_rx.c		optional hatm pci
 dev/hatm/if_hatm_tx.c		optional hatm pci
 dev/hifn/hifn7751.c		optional hifn
 dev/hme/if_hme.c		optional hme
 dev/hme/if_hme_pci.c		optional hme pci
 dev/hme/if_hme_sbus.c		optional hme sbus
 dev/hptiop/hptiop.c		optional hptiop scbus
 dev/hwpmc/hwpmc_logging.c	optional hwpmc
 dev/hwpmc/hwpmc_mod.c		optional hwpmc
 dev/hwpmc/hwpmc_soft.c		optional hwpmc
 dev/ichsmb/ichsmb.c		optional ichsmb
 dev/ichsmb/ichsmb_pci.c		optional ichsmb pci
 dev/ida/ida.c			optional ida
 dev/ida/ida_disk.c		optional ida
 dev/ida/ida_eisa.c		optional ida eisa
 dev/ida/ida_pci.c		optional ida pci
 dev/ie/if_ie.c			optional ie isa nowerror
 dev/ie/if_ie_isa.c		optional ie isa
 dev/ieee488/ibfoo.c		optional pcii | tnt4882
 dev/ieee488/pcii.c		optional pcii
 dev/ieee488/tnt4882.c		optional tnt4882
 dev/ieee488/upd7210.c		optional pcii | tnt4882
 dev/iicbus/ad7418.c		optional ad7418
 dev/iicbus/ds133x.c		optional ds133x
 dev/iicbus/ds1672.c		optional ds1672
 dev/iicbus/icee.c		optional icee
 dev/iicbus/if_ic.c		optional ic
 dev/iicbus/iic.c		optional iic
 dev/iicbus/iicbb.c		optional iicbb
 dev/iicbus/iicbb_if.m		optional iicbb
 dev/iicbus/iicbus.c		optional iicbus
 dev/iicbus/iicbus_if.m		optional iicbus
 dev/iicbus/iiconf.c		optional iicbus
 dev/iicbus/iicsmb.c		optional iicsmb				\
 	dependency	"iicbus_if.h"
 dev/iicbus/pcf8563.c		optional pcf8563
 dev/iir/iir.c			optional iir
 dev/iir/iir_ctrl.c		optional iir
 dev/iir/iir_pci.c		optional iir pci
 # XXX Work around clang warning, until maintainer approves fix.
 dev/ips/ips.c			optional ips \
 	compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}"
 dev/ips/ips_commands.c		optional ips
 dev/ips/ips_disk.c		optional ips
 dev/ips/ips_ioctl.c		optional ips
 dev/ips/ips_pci.c		optional ips pci
 dev/ipw/if_ipw.c		optional ipw
 ipwbssfw.c			optional ipwbssfw | ipwfw		\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk ipw_bss.fw:ipw_bss:130 -lintel_ipw -mipw_bss -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
 	clean		"ipwbssfw.c"
 ipw_bss.fwo			optional ipwbssfw | ipwfw		\
 	dependency	"ipw_bss.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"ipw_bss.fwo"
 ipw_bss.fw			optional ipwbssfw | ipwfw		\
 	dependency	"$S/contrib/dev/ipw/ipw2100-1.3.fw.uu"		\
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"ipw_bss.fw"
 ipwibssfw.c			optional ipwibssfw | ipwfw		\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk ipw_ibss.fw:ipw_ibss:130 -lintel_ipw -mipw_ibss -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
 	clean		"ipwibssfw.c"
 ipw_ibss.fwo			optional ipwibssfw | ipwfw		\
 	dependency	"ipw_ibss.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"ipw_ibss.fwo"
 ipw_ibss.fw			optional ipwibssfw | ipwfw		\
 	dependency	"$S/contrib/dev/ipw/ipw2100-1.3-i.fw.uu"	\
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"ipw_ibss.fw"
 ipwmonitorfw.c			optional ipwmonitorfw | ipwfw		\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk ipw_monitor.fw:ipw_monitor:130 -lintel_ipw -mipw_monitor -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
 	clean		"ipwmonitorfw.c"
 ipw_monitor.fwo			optional ipwmonitorfw | ipwfw		\
 	dependency	"ipw_monitor.fw"				\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"ipw_monitor.fwo"
 ipw_monitor.fw			optional ipwmonitorfw | ipwfw		\
 	dependency	"$S/contrib/dev/ipw/ipw2100-1.3-p.fw.uu"	\
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"ipw_monitor.fw"
 dev/iscsi/initiator/iscsi.c	optional iscsi_initiator scbus
 dev/iscsi/initiator/iscsi_subr.c	optional iscsi_initiator scbus
 dev/iscsi/initiator/isc_cam.c	optional iscsi_initiator scbus
 dev/iscsi/initiator/isc_soc.c	optional iscsi_initiator scbus
 dev/iscsi/initiator/isc_sm.c	optional iscsi_initiator scbus
 dev/iscsi/initiator/isc_subr.c	optional iscsi_initiator scbus
 dev/isp/isp.c			optional isp
 dev/isp/isp_freebsd.c		optional isp
 dev/isp/isp_library.c		optional isp
 dev/isp/isp_pci.c		optional isp pci
 dev/isp/isp_sbus.c		optional isp sbus
 dev/isp/isp_target.c		optional isp
 dev/ispfw/ispfw.c		optional ispfw
 dev/iwi/if_iwi.c		optional iwi
 iwibssfw.c			optional iwibssfw | iwifw		\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk iwi_bss.fw:iwi_bss:300 -lintel_iwi -miwi_bss -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
 	clean		"iwibssfw.c"
 iwi_bss.fwo			optional iwibssfw | iwifw		\
 	dependency	"iwi_bss.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"iwi_bss.fwo"
 iwi_bss.fw			optional iwibssfw | iwifw		\
 	dependency	"$S/contrib/dev/iwi/ipw2200-bss.fw.uu"		\
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"iwi_bss.fw"
 iwiibssfw.c			optional iwiibssfw | iwifw		\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk iwi_ibss.fw:iwi_ibss:300 -lintel_iwi -miwi_ibss -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
 	clean		"iwiibssfw.c"
 iwi_ibss.fwo			optional iwiibssfw | iwifw		\
 	dependency	"iwi_ibss.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"iwi_ibss.fwo"
 iwi_ibss.fw			optional iwiibssfw | iwifw		\
 	dependency	"$S/contrib/dev/iwi/ipw2200-ibss.fw.uu"		\
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"iwi_ibss.fw"
 iwimonitorfw.c			optional iwimonitorfw | iwifw		\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk iwi_monitor.fw:iwi_monitor:300 -lintel_iwi -miwi_monitor -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
 	clean		"iwimonitorfw.c"
 iwi_monitor.fwo			optional iwimonitorfw | iwifw		\
 	dependency	"iwi_monitor.fw"				\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"iwi_monitor.fwo"
 iwi_monitor.fw			optional iwimonitorfw | iwifw		\
 	dependency	"$S/contrib/dev/iwi/ipw2200-sniffer.fw.uu"	\
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"iwi_monitor.fw"
 dev/iwn/if_iwn.c		optional iwn
 iwn1000fw.c			optional iwn1000fw | iwnfw		\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk iwn1000.fw:iwn1000fw -miwn1000fw -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
 	clean		"iwn1000fw.c"
 iwn1000fw.fwo			optional iwn1000fw | iwnfw		\
 	dependency	"iwn1000.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"iwn1000fw.fwo"
 iwn1000.fw			optional iwn1000fw | iwnfw		\
 	dependency	"$S/contrib/dev/iwn/iwlwifi-1000-39.31.5.1.fw.uu" \
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"iwn1000.fw"
 iwn4965fw.c			optional iwn4965fw | iwnfw		\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk iwn4965.fw:iwn4965fw -miwn4965fw -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
 	clean		"iwn4965fw.c"
 iwn4965fw.fwo			optional iwn4965fw | iwnfw		\
 	dependency	"iwn4965.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"iwn4965fw.fwo"
 iwn4965.fw			optional iwn4965fw | iwnfw		\
 	dependency	"$S/contrib/dev/iwn/iwlwifi-4965-228.61.2.24.fw.uu" \
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"iwn4965.fw"
 iwn5000fw.c			optional iwn5000fw | iwnfw		\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk iwn5000.fw:iwn5000fw -miwn5000fw -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
 	clean		"iwn5000fw.c"
 iwn5000fw.fwo		optional iwn5000fw | iwnfw			\
 	dependency	"iwn5000.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"iwn5000fw.fwo"
 iwn5000.fw			optional iwn5000fw | iwnfw		\
 	dependency	"$S/contrib/dev/iwn/iwlwifi-5000-8.83.5.1.fw.uu" \
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"iwn5000.fw"
 iwn5150fw.c			optional iwn5150fw | iwnfw		\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk iwn5150.fw:iwn5150fw -miwn5150fw -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
 	clean		"iwn5150fw.c"
 iwn5150fw.fwo			optional iwn5150fw | iwnfw		\
 	dependency	"iwn5150.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"iwn5150fw.fwo"
 iwn5150.fw			optional iwn5150fw | iwnfw		\
 	dependency	"$S/contrib/dev/iwn/iwlwifi-5150-8.24.2.2.fw.uu"\
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"iwn5150.fw"
 iwn6000fw.c			optional iwn6000fw | iwnfw		\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk iwn6000.fw:iwn6000fw -miwn6000fw -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
 	clean		"iwn6000fw.c"
 iwn6000fw.fwo			optional iwn6000fw | iwnfw		\
 	dependency	"iwn6000.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"iwn6000fw.fwo"
 iwn6000.fw			optional iwn6000fw | iwnfw		\
 	dependency	"$S/contrib/dev/iwn/iwlwifi-6000-9.221.4.1.fw.uu" \
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"iwn6000.fw"
 iwn6000g2afw.c			optional iwn6000g2afw | iwnfw		\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk iwn6000g2a.fw:iwn6000g2afw -miwn6000g2afw -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
 	clean		"iwn6000g2afw.c"
 iwn6000g2afw.fwo		optional iwn6000g2afw | iwnfw		\
 	dependency	"iwn6000g2a.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"iwn6000g2afw.fwo"
 iwn6000g2a.fw			optional iwn6000g2afw | iwnfw		\
 	dependency	"$S/contrib/dev/iwn/iwlwifi-6000g2a-17.168.5.2.fw.uu" \
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"iwn6000g2a.fw"
 iwn6000g2bfw.c			optional iwn6000g2bfw | iwnfw		\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk iwn6000g2b.fw:iwn6000g2bfw -miwn6000g2bfw -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
 	clean		"iwn6000g2bfw.c"
 iwn6000g2bfw.fwo		optional iwn6000g2bfw | iwnfw		\
 	dependency	"iwn6000g2b.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"iwn6000g2bfw.fwo"
 iwn6000g2b.fw			optional iwn6000g2bfw | iwnfw		\
 	dependency	"$S/contrib/dev/iwn/iwlwifi-6000g2b-17.168.5.2.fw.uu" \
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"iwn6000g2b.fw"
 iwn6050fw.c			optional iwn6050fw | iwnfw		\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk iwn6050.fw:iwn6050fw -miwn6050fw -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
 	clean		"iwn6050fw.c"
 iwn6050fw.fwo			optional iwn6050fw | iwnfw		\
 	dependency	"iwn6050.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"iwn6050fw.fwo"
 iwn6050.fw			optional iwn6050fw | iwnfw		\
 	dependency	"$S/contrib/dev/iwn/iwlwifi-6050-41.28.5.1.fw.uu" \
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"iwn6050.fw"
 dev/ixgb/if_ixgb.c		optional ixgb
 dev/ixgb/ixgb_ee.c		optional ixgb
 dev/ixgb/ixgb_hw.c		optional ixgb
 dev/ixgbe/ixgbe.c		optional ixgbe inet \
 	compile-with "${NORMAL_C} -I$S/dev/ixgbe"
 dev/ixgbe/ixv.c			optional ixgbe inet \
 	compile-with "${NORMAL_C} -I$S/dev/ixgbe"
 dev/ixgbe/ixgbe_phy.c		optional ixgbe inet \
 	compile-with "${NORMAL_C} -I$S/dev/ixgbe"
 dev/ixgbe/ixgbe_api.c		optional ixgbe inet \
 	compile-with "${NORMAL_C} -I$S/dev/ixgbe"
 dev/ixgbe/ixgbe_common.c	optional ixgbe inet \
 	compile-with "${NORMAL_C} -I$S/dev/ixgbe"
 dev/ixgbe/ixgbe_mbx.c		optional ixgbe inet \
 	compile-with "${NORMAL_C} -I$S/dev/ixgbe"
 dev/ixgbe/ixgbe_vf.c		optional ixgbe inet \
 	compile-with "${NORMAL_C} -I$S/dev/ixgbe"
 dev/ixgbe/ixgbe_82598.c		optional ixgbe inet \
 	compile-with "${NORMAL_C} -I$S/dev/ixgbe"
 dev/ixgbe/ixgbe_82599.c		optional ixgbe inet \
 	compile-with "${NORMAL_C} -I$S/dev/ixgbe"
 dev/ixgbe/ixgbe_x540.c		optional ixgbe inet \
 	compile-with "${NORMAL_C} -I$S/dev/ixgbe"
 dev/ixgbe/ixgbe_dcb.c		optional ixgbe inet \
 	compile-with "${NORMAL_C} -I$S/dev/ixgbe"
 dev/ixgbe/ixgbe_dcb_82598.c	optional ixgbe inet \
 	compile-with "${NORMAL_C} -I$S/dev/ixgbe"
 dev/ixgbe/ixgbe_dcb_82599.c	optional ixgbe inet \
 	compile-with "${NORMAL_C} -I$S/dev/ixgbe"
 dev/jme/if_jme.c		optional jme pci
 dev/joy/joy.c			optional joy
 dev/joy/joy_isa.c		optional joy isa
 dev/joy/joy_pccard.c		optional joy pccard
 dev/kbdmux/kbdmux.c		optional kbdmux
 dev/ksyms/ksyms.c		optional ksyms
 dev/le/am7990.c			optional le
 dev/le/am79900.c		optional le
 dev/le/if_le_pci.c		optional le pci
 dev/le/lance.c			optional le
 dev/led/led.c			standard
 dev/lge/if_lge.c		optional lge
 dev/lmc/if_lmc.c		optional lmc
 dev/malo/if_malo.c		optional malo
 dev/malo/if_malohal.c		optional malo
 dev/malo/if_malo_pci.c		optional malo pci
 dev/mc146818/mc146818.c		optional mc146818
 dev/mca/mca_bus.c		optional mca
 dev/mcd/mcd.c			optional mcd isa nowerror
 dev/mcd/mcd_isa.c		optional mcd isa nowerror
 dev/md/md.c			optional md
 dev/mem/memdev.c		optional mem
 dev/mem/memutil.c		optional mem
 dev/mfi/mfi.c			optional mfi
 dev/mfi/mfi_debug.c		optional mfi
 dev/mfi/mfi_pci.c		optional mfi pci
 dev/mfi/mfi_disk.c		optional mfi
 dev/mfi/mfi_syspd.c		optional mfi
 dev/mfi/mfi_tbolt.c		optional mfi
 dev/mfi/mfi_linux.c		optional mfi compat_linux
 dev/mfi/mfi_cam.c		optional mfip scbus
 dev/mii/acphy.c			optional miibus | acphy
 dev/mii/amphy.c			optional miibus | amphy
 dev/mii/atphy.c			optional miibus | atphy
 dev/mii/axphy.c			optional miibus | axphy
 dev/mii/bmtphy.c		optional miibus | bmtphy
 dev/mii/brgphy.c		optional miibus | brgphy
 dev/mii/ciphy.c			optional miibus | ciphy
 dev/mii/e1000phy.c		optional miibus | e1000phy
 dev/mii/gentbi.c		optional miibus | gentbi
 dev/mii/icsphy.c		optional miibus | icsphy
 dev/mii/ip1000phy.c		optional miibus | ip1000phy
 dev/mii/jmphy.c			optional miibus | jmphy
 dev/mii/lxtphy.c		optional miibus | lxtphy
 dev/mii/mii.c			optional miibus | mii
 dev/mii/mii_bitbang.c		optional miibus | mii_bitbang
 dev/mii/mii_physubr.c		optional miibus | mii
 dev/mii/miibus_if.m		optional miibus | mii
 dev/mii/mlphy.c			optional miibus | mlphy
 dev/mii/nsgphy.c		optional miibus | nsgphy
 dev/mii/nsphy.c			optional miibus | nsphy
 dev/mii/nsphyter.c		optional miibus | nsphyter
 dev/mii/pnaphy.c		optional miibus | pnaphy
 dev/mii/qsphy.c			optional miibus | qsphy
 dev/mii/rdcphy.c		optional miibus | rdcphy
 dev/mii/rgephy.c		optional miibus | rgephy
 dev/mii/rlphy.c			optional miibus | rlphy
 dev/mii/rlswitch.c		optional rlswitch
 dev/mii/smcphy.c		optional miibus | smcphy
 dev/mii/tdkphy.c		optional miibus | tdkphy
 dev/mii/tlphy.c			optional miibus | tlphy
 dev/mii/truephy.c		optional miibus | truephy
 dev/mii/ukphy.c			optional miibus | mii
 dev/mii/ukphy_subr.c		optional miibus | mii
 dev/mii/xmphy.c			optional miibus | xmphy
 dev/mk48txx/mk48txx.c		optional mk48txx
 dev/mlx/mlx.c			optional mlx
 dev/mlx/mlx_disk.c		optional mlx
 dev/mlx/mlx_pci.c		optional mlx pci
 dev/mly/mly.c			optional mly
 dev/mmc/mmc.c			optional mmc
 dev/mmc/mmcbr_if.m		standard
 dev/mmc/mmcbus_if.m		standard
 dev/mmc/mmcsd.c			optional mmcsd
 dev/mn/if_mn.c			optional mn pci
 dev/mpr/mpr.c			optional mpr
 dev/mpr/mpr_config.c		optional mpr
 # XXX Work around clang warning, until maintainer approves fix.
 dev/mpr/mpr_mapping.c		optional mpr \
 	compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}"
 dev/mpr/mpr_pci.c		optional mpr pci
 dev/mpr/mpr_sas.c		optional mpr \
 	compile-with "${NORMAL_C} ${NO_WUNNEEDED_INTERNAL_DECL}"
 dev/mpr/mpr_sas_lsi.c		optional mpr
 dev/mpr/mpr_table.c		optional mpr
 dev/mpr/mpr_user.c		optional mpr
 dev/mps/mps.c			optional mps
 dev/mps/mps_config.c		optional mps
 # XXX Work around clang warning, until maintainer approves fix.
 dev/mps/mps_mapping.c		optional mps \
 	compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}"
 dev/mps/mps_pci.c		optional mps pci
 dev/mps/mps_sas.c		optional mps \
 	compile-with "${NORMAL_C} ${NO_WUNNEEDED_INTERNAL_DECL}"
 dev/mps/mps_sas_lsi.c		optional mps
 dev/mps/mps_table.c		optional mps
 dev/mps/mps_user.c		optional mps
 dev/mpt/mpt.c			optional mpt
 dev/mpt/mpt_cam.c		optional mpt
 dev/mpt/mpt_debug.c		optional mpt
 dev/mpt/mpt_pci.c		optional mpt pci
 dev/mpt/mpt_raid.c		optional mpt
 dev/mpt/mpt_user.c		optional mpt
 dev/mrsas/mrsas.c		optional mrsas
 dev/mrsas/mrsas_cam.c		optional mrsas
 dev/mrsas/mrsas_ioctl.c		optional mrsas
 dev/mrsas/mrsas_fp.c		optional mrsas
 dev/msk/if_msk.c		optional msk
 dev/mvs/mvs.c			optional mvs
 dev/mvs/mvs_if.m		optional mvs
 dev/mvs/mvs_pci.c		optional mvs pci
 dev/mwl/if_mwl.c		optional mwl
 dev/mwl/if_mwl_pci.c		optional mwl pci
 dev/mwl/mwlhal.c		optional mwl
 mwlfw.c				optional mwlfw				\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk mw88W8363.fw:mw88W8363fw mwlboot.fw:mwlboot -mmwl -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
 	clean		"mwlfw.c"
 mw88W8363.fwo		optional mwlfw					\
 	dependency	"mw88W8363.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"mw88W8363.fwo"
 mw88W8363.fw		optional mwlfw					\
 	dependency	"$S/contrib/dev/mwl/mw88W8363.fw.uu"		\
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"mw88W8363.fw"
 mwlboot.fwo		optional mwlfw					\
 	dependency	"mwlboot.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"mwlboot.fwo"
 mwlboot.fw		optional mwlfw					\
 	dependency	"$S/contrib/dev/mwl/mwlboot.fw.uu"		\
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"mwlboot.fw"
 dev/mxge/if_mxge.c		optional mxge pci
 dev/mxge/mxge_eth_z8e.c		optional mxge pci
 dev/mxge/mxge_ethp_z8e.c	optional mxge pci
 dev/mxge/mxge_rss_eth_z8e.c	optional mxge pci
 dev/mxge/mxge_rss_ethp_z8e.c	optional mxge pci
 dev/my/if_my.c			optional my
 dev/ncv/ncr53c500.c		optional ncv
 dev/ncv/ncr53c500_pccard.c	optional ncv pccard
 dev/netmap/netmap.c		optional netmap
 dev/netmap/netmap_freebsd.c	optional netmap
 dev/netmap/netmap_generic.c	optional netmap
 dev/netmap/netmap_mbq.c		optional netmap
 dev/netmap/netmap_mem2.c	optional netmap
 dev/netmap/netmap_offloadings.c	optional netmap
 dev/netmap/netmap_pipe.c	optional netmap
 dev/netmap/netmap_vale.c	optional netmap
 dev/nge/if_nge.c		optional nge
 dev/nxge/if_nxge.c		optional nxge \
 	compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}"
 dev/nxge/xgehal/xgehal-device.c	optional nxge \
 	compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}"
 dev/nxge/xgehal/xgehal-mm.c	optional nxge
 dev/nxge/xgehal/xge-queue.c	optional nxge
 dev/nxge/xgehal/xgehal-driver.c	optional nxge \
 	compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}"
 dev/nxge/xgehal/xgehal-ring.c	optional nxge \
 	compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}"
 dev/nxge/xgehal/xgehal-channel.c	optional nxge \
 	compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}"
 dev/nxge/xgehal/xgehal-fifo.c	optional nxge \
 	compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}"
 dev/nxge/xgehal/xgehal-stats.c	optional nxge \
 	compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}"
 dev/nxge/xgehal/xgehal-config.c	optional nxge
 dev/nxge/xgehal/xgehal-mgmt.c	optional nxge \
 	compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}"
 dev/nmdm/nmdm.c			optional nmdm
 dev/nsp/nsp.c			optional nsp
 dev/nsp/nsp_pccard.c		optional nsp pccard
 dev/null/null.c			standard
 dev/oce/oce_hw.c		optional oce pci
 dev/oce/oce_if.c		optional oce pci
 dev/oce/oce_mbox.c		optional oce pci
 dev/oce/oce_queue.c		optional oce pci
 dev/oce/oce_sysctl.c		optional oce pci
 dev/oce/oce_util.c		optional oce pci
 dev/patm/if_patm.c		optional patm pci
 dev/patm/if_patm_attach.c	optional patm pci
 dev/patm/if_patm_intr.c		optional patm pci
 dev/patm/if_patm_ioctl.c	optional patm pci
 dev/patm/if_patm_rtables.c	optional patm pci
 dev/patm/if_patm_rx.c		optional patm pci
 dev/patm/if_patm_tx.c		optional patm pci
 dev/pbio/pbio.c			optional pbio isa
 dev/pccard/card_if.m		standard
 dev/pccard/pccard.c		optional pccard
 dev/pccard/pccard_cis.c		optional pccard
 dev/pccard/pccard_cis_quirks.c	optional pccard
 dev/pccard/pccard_device.c	optional pccard
 dev/pccard/power_if.m		standard
 dev/pccbb/pccbb.c		optional cbb
 dev/pccbb/pccbb_isa.c		optional cbb isa
 dev/pccbb/pccbb_pci.c		optional cbb pci
 dev/pcf/pcf.c			optional pcf
 dev/pci/eisa_pci.c		optional pci eisa
 dev/pci/fixup_pci.c		optional pci
 dev/pci/hostb_pci.c		optional pci
 dev/pci/ignore_pci.c		optional pci
 dev/pci/isa_pci.c		optional pci isa
 dev/pci/pci.c			optional pci
 dev/pci/pci_if.m		standard
 dev/pci/pci_pci.c		optional pci
 dev/pci/pci_subr.c		optional pci
 dev/pci/pci_user.c		optional pci
 dev/pci/pcib_if.m		standard
 dev/pci/vga_pci.c		optional pci
 dev/pcn/if_pcn.c		optional pcn pci
 dev/pdq/if_fea.c		optional fea eisa
 dev/pdq/if_fpa.c		optional fpa pci
 dev/pdq/pdq.c			optional nowerror fea eisa | fpa pci
 dev/pdq/pdq_ifsubr.c		optional nowerror fea eisa | fpa pci
 dev/ppbus/if_plip.c		optional plip
 dev/ppbus/immio.c		optional vpo
 dev/ppbus/lpbb.c		optional lpbb
 dev/ppbus/lpt.c			optional lpt
 dev/ppbus/pcfclock.c		optional pcfclock
 dev/ppbus/ppb_1284.c		optional ppbus
 dev/ppbus/ppb_base.c		optional ppbus
 dev/ppbus/ppb_msq.c		optional ppbus
 dev/ppbus/ppbconf.c		optional ppbus
 dev/ppbus/ppbus_if.m		optional ppbus
 dev/ppbus/ppi.c			optional ppi
 dev/ppbus/pps.c			optional pps
 dev/ppbus/vpo.c			optional vpo
 dev/ppbus/vpoio.c		optional vpo
 dev/ppc/ppc.c			optional ppc
 dev/ppc/ppc_acpi.c		optional ppc acpi
 dev/ppc/ppc_isa.c		optional ppc isa
 dev/ppc/ppc_pci.c		optional ppc pci
 dev/ppc/ppc_puc.c		optional ppc puc
 dev/pst/pst-iop.c		optional pst
 dev/pst/pst-pci.c		optional pst pci
 dev/pst/pst-raid.c		optional pst
 dev/pty/pty.c			optional pty
 dev/puc/puc.c			optional puc
 dev/puc/puc_cfg.c		optional puc
 dev/puc/puc_pccard.c		optional puc pccard
 dev/puc/puc_pci.c		optional puc pci
 dev/puc/pucdata.c		optional puc pci
 dev/quicc/quicc_core.c		optional quicc
 dev/ral/rt2560.c		optional ral
 dev/ral/rt2661.c		optional ral
 dev/ral/rt2860.c		optional ral
 dev/ral/if_ral_pci.c		optional ral pci
 rt2561fw.c			optional rt2561fw | ralfw		\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk rt2561.fw:rt2561fw -mrt2561 -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
 	clean		"rt2561fw.c"
 rt2561fw.fwo			optional rt2561fw | ralfw		\
 	dependency	"rt2561.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"rt2561fw.fwo"
 rt2561.fw			optional rt2561fw | ralfw		\
 	dependency	"$S/contrib/dev/ral/rt2561.fw.uu"		\
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"rt2561.fw"
 rt2561sfw.c			optional rt2561sfw | ralfw		\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk rt2561s.fw:rt2561sfw -mrt2561s -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
 	clean		"rt2561sfw.c"
 rt2561sfw.fwo			optional rt2561sfw | ralfw		\
 	dependency	"rt2561s.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"rt2561sfw.fwo"
 rt2561s.fw			optional rt2561sfw | ralfw		\
 	dependency	"$S/contrib/dev/ral/rt2561s.fw.uu"		\
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"rt2561s.fw"
 rt2661fw.c			optional rt2661fw | ralfw		\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk rt2661.fw:rt2661fw -mrt2661 -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
 	clean		"rt2661fw.c"
 rt2661fw.fwo			optional rt2661fw | ralfw		\
 	dependency	"rt2661.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"rt2661fw.fwo"
 rt2661.fw			optional rt2661fw | ralfw		\
 	dependency	"$S/contrib/dev/ral/rt2661.fw.uu"		\
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"rt2661.fw"
 rt2860fw.c			optional rt2860fw | ralfw		\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk rt2860.fw:rt2860fw -mrt2860 -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
 	clean		"rt2860fw.c"
 rt2860fw.fwo			optional rt2860fw | ralfw		\
 	dependency	"rt2860.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"rt2860fw.fwo"
 rt2860.fw			optional rt2860fw | ralfw		\
 	dependency	"$S/contrib/dev/ral/rt2860.fw.uu"		\
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"rt2860.fw"
 dev/random/harvest.c		standard
 dev/random/hash.c		optional random
 dev/random/probe.c		optional random
 dev/random/randomdev.c		optional random
 dev/random/randomdev_soft.c	optional random
 dev/random/yarrow.c		optional random
 dev/rc/rc.c			optional rc
 dev/re/if_re.c			optional re
+dev/rl/if_rl.c			optional rl pci
 dev/rndtest/rndtest.c		optional rndtest
 dev/rp/rp.c			optional rp
 dev/rp/rp_isa.c			optional rp isa
 dev/rp/rp_pci.c			optional rp pci
 dev/safe/safe.c			optional safe
 dev/scc/scc_if.m		optional scc
 dev/scc/scc_bfe_ebus.c		optional scc ebus
 dev/scc/scc_bfe_quicc.c		optional scc quicc
 dev/scc/scc_bfe_sbus.c		optional scc fhc | scc sbus
 dev/scc/scc_core.c		optional scc
 dev/scc/scc_dev_quicc.c		optional scc quicc
 dev/scc/scc_dev_sab82532.c	optional scc
 dev/scc/scc_dev_z8530.c		optional scc
 dev/scd/scd.c			optional scd isa
 dev/scd/scd_isa.c		optional scd isa
 dev/sdhci/sdhci.c		optional sdhci pci
 dev/sf/if_sf.c			optional sf pci
 dev/sge/if_sge.c		optional sge pci
 dev/si/si.c			optional si
 dev/si/si2_z280.c		optional si
 dev/si/si3_t225.c		optional si
 dev/si/si_eisa.c		optional si eisa
 dev/si/si_isa.c			optional si isa
 dev/si/si_pci.c			optional si pci
 dev/siba/siba_bwn.c		optional siba_bwn pci
 dev/siba/siba_core.c		optional siba_bwn pci
 dev/siis/siis.c			optional siis pci
 dev/sis/if_sis.c		optional sis pci
 dev/sk/if_sk.c			optional sk pci
 dev/smbus/smb.c			optional smb
 dev/smbus/smbconf.c		optional smbus
 dev/smbus/smbus.c		optional smbus
 dev/smbus/smbus_if.m		optional smbus
 dev/smc/if_smc.c		optional smc
 dev/sn/if_sn.c			optional sn
 dev/sn/if_sn_isa.c		optional sn isa
 dev/sn/if_sn_pccard.c		optional sn pccard
 dev/snp/snp.c			optional snp
 dev/sound/clone.c		optional sound
 dev/sound/unit.c		optional sound
 dev/sound/isa/ad1816.c		optional snd_ad1816 isa
 dev/sound/isa/ess.c		optional snd_ess isa
 dev/sound/isa/gusc.c		optional snd_gusc isa
 dev/sound/isa/mss.c		optional snd_mss isa
 dev/sound/isa/sb16.c		optional snd_sb16 isa
 dev/sound/isa/sb8.c		optional snd_sb8 isa
 dev/sound/isa/sbc.c		optional snd_sbc isa
 dev/sound/isa/sndbuf_dma.c	optional sound isa
 dev/sound/pci/als4000.c		optional snd_als4000 pci
 dev/sound/pci/atiixp.c		optional snd_atiixp pci
 dev/sound/pci/cmi.c		optional snd_cmi pci
 dev/sound/pci/cs4281.c		optional snd_cs4281 pci
 dev/sound/pci/csa.c		optional snd_csa pci
 dev/sound/pci/csapcm.c		optional snd_csa pci
 dev/sound/pci/ds1.c		optional snd_ds1 pci
 dev/sound/pci/emu10k1.c		optional snd_emu10k1 pci
 dev/sound/pci/emu10kx.c		optional snd_emu10kx pci
 dev/sound/pci/emu10kx-pcm.c	optional snd_emu10kx pci
 dev/sound/pci/emu10kx-midi.c	optional snd_emu10kx pci
 dev/sound/pci/envy24.c		optional snd_envy24 pci
 dev/sound/pci/envy24ht.c	optional snd_envy24ht pci
 dev/sound/pci/es137x.c		optional snd_es137x pci
 dev/sound/pci/fm801.c		optional snd_fm801 pci
 dev/sound/pci/ich.c		optional snd_ich pci
 dev/sound/pci/maestro.c		optional snd_maestro pci
 dev/sound/pci/maestro3.c	optional snd_maestro3 pci
 dev/sound/pci/neomagic.c	optional snd_neomagic pci
 dev/sound/pci/solo.c		optional snd_solo pci
 dev/sound/pci/spicds.c		optional snd_spicds pci
 dev/sound/pci/t4dwave.c		optional snd_t4dwave pci
 dev/sound/pci/via8233.c		optional snd_via8233 pci
 dev/sound/pci/via82c686.c	optional snd_via82c686 pci
 dev/sound/pci/vibes.c		optional snd_vibes pci
 dev/sound/pci/hda/hdaa.c	optional snd_hda pci
 dev/sound/pci/hda/hdaa_patches.c	optional snd_hda pci
 dev/sound/pci/hda/hdac.c	optional snd_hda pci
 dev/sound/pci/hda/hdac_if.m	optional snd_hda pci
 dev/sound/pci/hda/hdacc.c	optional snd_hda pci
 dev/sound/pci/hdspe.c		optional snd_hdspe pci
 dev/sound/pci/hdspe-pcm.c	optional snd_hdspe pci
 dev/sound/pcm/ac97.c		optional sound
 dev/sound/pcm/ac97_if.m		optional sound
 dev/sound/pcm/ac97_patch.c	optional sound
 dev/sound/pcm/buffer.c		optional sound	\
 	dependency	"snd_fxdiv_gen.h"
 dev/sound/pcm/channel.c		optional sound
 dev/sound/pcm/channel_if.m	optional sound
 dev/sound/pcm/dsp.c		optional sound
 dev/sound/pcm/feeder.c		optional sound
 dev/sound/pcm/feeder_chain.c	optional sound
 dev/sound/pcm/feeder_eq.c	optional sound	\
 	dependency	"feeder_eq_gen.h"	\
 	dependency	"snd_fxdiv_gen.h"
 dev/sound/pcm/feeder_if.m	optional sound
 dev/sound/pcm/feeder_format.c	optional sound  \
 	dependency	"snd_fxdiv_gen.h"
 dev/sound/pcm/feeder_matrix.c	optional sound  \
 	dependency	"snd_fxdiv_gen.h"
 dev/sound/pcm/feeder_mixer.c	optional sound  \
 	dependency	"snd_fxdiv_gen.h"
 dev/sound/pcm/feeder_rate.c	optional sound	\
 	dependency	"feeder_rate_gen.h"	\
 	dependency	"snd_fxdiv_gen.h"
 dev/sound/pcm/feeder_volume.c	optional sound  \
 	dependency	"snd_fxdiv_gen.h"
 dev/sound/pcm/mixer.c		optional sound
 dev/sound/pcm/mixer_if.m	optional sound
 dev/sound/pcm/sndstat.c		optional sound
 dev/sound/pcm/sound.c		optional sound
 dev/sound/pcm/vchan.c		optional sound
 dev/sound/usb/uaudio.c		optional snd_uaudio usb
 dev/sound/usb/uaudio_pcm.c	optional snd_uaudio usb
 dev/sound/midi/midi.c		optional sound
 dev/sound/midi/mpu401.c		optional sound
 dev/sound/midi/mpu_if.m		optional sound
 dev/sound/midi/mpufoi_if.m	optional sound
 dev/sound/midi/sequencer.c	optional sound
 dev/sound/midi/synth_if.m	optional sound
 dev/spibus/spibus.c		optional spibus				\
 	dependency	"spibus_if.h"
 dev/spibus/spibus_if.m		optional spibus
 dev/ste/if_ste.c		optional ste pci
 dev/stg/tmc18c30.c		optional stg
 dev/stg/tmc18c30_isa.c		optional stg isa
 dev/stg/tmc18c30_pccard.c	optional stg pccard
 dev/stg/tmc18c30_pci.c		optional stg pci
 dev/stg/tmc18c30_subr.c		optional stg
 dev/stge/if_stge.c		optional stge
 dev/streams/streams.c		optional streams
 dev/sym/sym_hipd.c		optional sym				\
 	dependency	"$S/dev/sym/sym_{conf,defs}.h"
 dev/syscons/blank/blank_saver.c	optional blank_saver
 dev/syscons/daemon/daemon_saver.c optional daemon_saver
 dev/syscons/dragon/dragon_saver.c optional dragon_saver
 dev/syscons/fade/fade_saver.c	optional fade_saver
 dev/syscons/fire/fire_saver.c	optional fire_saver
 dev/syscons/green/green_saver.c	optional green_saver
 dev/syscons/logo/logo.c		optional logo_saver
 dev/syscons/logo/logo_saver.c	optional logo_saver
 dev/syscons/rain/rain_saver.c	optional rain_saver
 dev/syscons/schistory.c		optional sc
 dev/syscons/scmouse.c		optional sc
 dev/syscons/scterm.c		optional sc
 dev/syscons/scvidctl.c		optional sc
 dev/syscons/snake/snake_saver.c	optional snake_saver
 dev/syscons/star/star_saver.c	optional star_saver
 dev/syscons/syscons.c		optional sc
 dev/syscons/sysmouse.c		optional sc
 dev/syscons/warp/warp_saver.c	optional warp_saver
 dev/tdfx/tdfx_linux.c		optional tdfx_linux tdfx compat_linux
 dev/tdfx/tdfx_pci.c		optional tdfx pci
 dev/ti/if_ti.c			optional ti pci
 dev/tl/if_tl.c			optional tl pci
 dev/trm/trm.c			optional trm
 dev/twa/tw_cl_init.c		optional twa \
 	compile-with "${NORMAL_C} -I$S/dev/twa"
 dev/twa/tw_cl_intr.c		optional twa \
 	compile-with "${NORMAL_C} -I$S/dev/twa"
 dev/twa/tw_cl_io.c		optional twa \
 	compile-with "${NORMAL_C} -I$S/dev/twa"
 dev/twa/tw_cl_misc.c		optional twa \
 	compile-with "${NORMAL_C} -I$S/dev/twa"
 dev/twa/tw_osl_cam.c		optional twa \
 	compile-with "${NORMAL_C} -I$S/dev/twa"
 dev/twa/tw_osl_freebsd.c	optional twa \
 	compile-with "${NORMAL_C} -I$S/dev/twa"
 dev/twe/twe.c			optional twe
 dev/twe/twe_freebsd.c		optional twe
 dev/tws/tws.c			optional tws
 dev/tws/tws_cam.c		optional tws
 dev/tws/tws_hdm.c		optional tws
 dev/tws/tws_services.c		optional tws
 dev/tws/tws_user.c		optional tws
 dev/tx/if_tx.c			optional tx
 dev/txp/if_txp.c		optional txp
 dev/uart/uart_bus_acpi.c	optional uart acpi
 #dev/uart/uart_bus_cbus.c	optional uart cbus
 dev/uart/uart_bus_ebus.c	optional uart ebus
 dev/uart/uart_bus_fdt.c		optional uart fdt
 dev/uart/uart_bus_isa.c		optional uart isa
 dev/uart/uart_bus_pccard.c	optional uart pccard
 dev/uart/uart_bus_pci.c		optional uart pci
 dev/uart/uart_bus_puc.c		optional uart puc
 dev/uart/uart_bus_scc.c		optional uart scc
 dev/uart/uart_core.c		optional uart
 dev/uart/uart_dbg.c		optional uart gdb
 dev/uart/uart_dev_ns8250.c	optional uart uart_ns8250
 dev/uart/uart_dev_quicc.c	optional uart quicc
 dev/uart/uart_dev_sab82532.c	optional uart uart_sab82532
 dev/uart/uart_dev_sab82532.c	optional uart scc
 dev/uart/uart_dev_z8530.c	optional uart uart_z8530
 dev/uart/uart_dev_z8530.c	optional uart scc
 dev/uart/uart_if.m		optional uart
 dev/uart/uart_subr.c		optional uart
 dev/uart/uart_tty.c		optional uart
 dev/ubsec/ubsec.c		optional ubsec
 #
 # USB controller drivers
 #
 dev/usb/controller/at91dci.c		optional at91dci
 dev/usb/controller/at91dci_atmelarm.c	optional at91dci at91rm9200
 dev/usb/controller/musb_otg.c		optional musb
 dev/usb/controller/musb_otg_atmelarm.c	optional musb at91rm9200
 dev/usb/controller/ehci.c		optional ehci
 dev/usb/controller/ehci_pci.c		optional ehci pci
 dev/usb/controller/ohci.c		optional ohci
 dev/usb/controller/ohci_atmelarm.c	optional ohci at91rm9200
 dev/usb/controller/ohci_pci.c		optional ohci pci
 dev/usb/controller/uhci.c		optional uhci
 dev/usb/controller/uhci_pci.c		optional uhci pci
 dev/usb/controller/xhci.c		optional xhci
 dev/usb/controller/xhci_pci.c		optional xhci pci
 dev/usb/controller/uss820dci.c		optional uss820dci
 dev/usb/controller/uss820dci_atmelarm.c	optional uss820dci at91rm9200
 dev/usb/controller/usb_controller.c	optional usb
 #
 # USB storage drivers
 #
 dev/usb/storage/umass.c		optional umass
 dev/usb/storage/urio.c		optional urio
 dev/usb/storage/ustorage_fs.c	optional usfs
 #
 # USB core
 #
 dev/usb/usb_busdma.c		optional usb
 dev/usb/usb_compat_linux.c	optional usb
 dev/usb/usb_core.c		optional usb
 dev/usb/usb_debug.c		optional usb
 dev/usb/usb_dev.c		optional usb
 dev/usb/usb_device.c		optional usb
 dev/usb/usb_dynamic.c		optional usb
 dev/usb/usb_error.c		optional usb
 dev/usb/usb_generic.c		optional usb
 dev/usb/usb_handle_request.c	optional usb
 dev/usb/usb_hid.c		optional usb
 dev/usb/usb_hub.c		optional usb
 dev/usb/usb_if.m		optional usb
 dev/usb/usb_lookup.c		optional usb
 dev/usb/usb_mbuf.c		optional usb
 dev/usb/usb_msctest.c		optional usb
 dev/usb/usb_parse.c		optional usb
 dev/usb/usb_pf.c		optional usb
 dev/usb/usb_process.c		optional usb
 dev/usb/usb_request.c		optional usb
 dev/usb/usb_transfer.c		optional usb
 dev/usb/usb_util.c		optional usb
 #
 # USB network drivers
 #
 dev/usb/net/if_aue.c		optional aue
 dev/usb/net/if_axe.c		optional axe
 dev/usb/net/if_axge.c		optional axge
 dev/usb/net/if_cdce.c		optional cdce
 dev/usb/net/if_cue.c		optional cue
 dev/usb/net/if_ipheth.c		optional ipheth
 dev/usb/net/if_kue.c		optional kue
 dev/usb/net/if_mos.c		optional mos
 dev/usb/net/if_rue.c		optional rue
 dev/usb/net/if_udav.c		optional udav
 dev/usb/net/if_usie.c		optional usie
 dev/usb/net/if_urndis.c		optional urndis
 dev/usb/net/ruephy.c		optional rue
 dev/usb/net/usb_ethernet.c	optional aue | axe | axge | cdce | cue | kue | \
 					 mos | rue | udav | ipheth | urndis
 dev/usb/net/uhso.c		optional uhso
 #
 # USB WLAN drivers
 #
 dev/usb/wlan/if_rum.c		optional rum
 dev/usb/wlan/if_run.c		optional run
 runfw.c				optional runfw							\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk run.fw:runfw -mrunfw -c${.TARGET}"	\
 	no-implicit-rule before-depend local							\
 	clean		"runfw.c"
 runfw.fwo			optional runfw							\
 	dependency	"run.fw"								\
 	compile-with	"${NORMAL_FWO}"								\
 	no-implicit-rule									\
 	clean		"runfw.fwo"
 run.fw				optional runfw							\
 	dependency	"$S/contrib/dev/run/rt2870.fw.uu"					\
 	compile-with	"${NORMAL_FW}"								\
 	no-obj no-implicit-rule									\
 	clean		"run.fw"
 dev/usb/wlan/if_uath.c		optional uath
 dev/usb/wlan/if_upgt.c		optional upgt
 dev/usb/wlan/if_ural.c		optional ural
 dev/usb/wlan/if_urtw.c		optional urtw
 dev/usb/wlan/if_zyd.c		optional zyd
 #
 # USB serial and parallel port drivers
 #
 dev/usb/serial/u3g.c		optional u3g
 dev/usb/serial/uark.c		optional uark
 dev/usb/serial/ubsa.c		optional ubsa
 dev/usb/serial/ubser.c		optional ubser
 dev/usb/serial/uchcom.c		optional uchcom
 dev/usb/serial/ucycom.c		optional ucycom
 dev/usb/serial/ufoma.c		optional ufoma
 dev/usb/serial/uftdi.c		optional uftdi
 dev/usb/serial/ugensa.c		optional ugensa
 dev/usb/serial/uipaq.c		optional uipaq
 dev/usb/serial/ulpt.c		optional ulpt
 dev/usb/serial/umcs.c		optional umcs
 dev/usb/serial/umct.c		optional umct
 dev/usb/serial/umodem.c		optional umodem
 dev/usb/serial/umoscom.c	optional umoscom
 dev/usb/serial/uplcom.c		optional uplcom
 dev/usb/serial/uslcom.c		optional uslcom
 dev/usb/serial/uvisor.c		optional uvisor
 dev/usb/serial/uvscom.c		optional uvscom
 dev/usb/serial/usb_serial.c 	optional ucom | u3g | uark | ubsa | ubser | \
 					 uchcom | ucycom | ufoma | uftdi | \
 					 ugensa | uipaq | umcs | umct | \
 					 umodem | umoscom | uplcom | usie | \
 					 uslcom | uvisor | uvscom
 #
 # USB misc drivers
 #
 dev/usb/misc/ufm.c		optional ufm
 dev/usb/misc/udbp.c		optional udbp
 #
 # USB input drivers
 #
 dev/usb/input/atp.c		optional atp
 dev/usb/input/uep.c		optional uep
 dev/usb/input/uhid.c		optional uhid
 dev/usb/input/ukbd.c		optional ukbd
 dev/usb/input/ums.c		optional ums
 dev/usb/input/wsp.c		optional wsp
 #
 # USB quirks
 #
 dev/usb/quirk/usb_quirk.c	optional usb
 #
 # USB templates
 #
 dev/usb/template/usb_template.c		optional usb_template
 dev/usb/template/usb_template_audio.c	optional usb_template
 dev/usb/template/usb_template_cdce.c	optional usb_template
 dev/usb/template/usb_template_kbd.c	optional usb_template
 dev/usb/template/usb_template_modem.c	optional usb_template
 dev/usb/template/usb_template_mouse.c	optional usb_template
 dev/usb/template/usb_template_msc.c	optional usb_template
 dev/usb/template/usb_template_mtp.c	optional usb_template
 #
 # USB END
 #
 dev/utopia/idtphy.c		optional utopia
 dev/utopia/suni.c		optional utopia
 dev/utopia/utopia.c		optional utopia
 dev/vge/if_vge.c		optional vge
 dev/vkbd/vkbd.c			optional vkbd
 dev/vr/if_vr.c			optional vr pci
 dev/vt/colors/vt_termcolors.c	optional vt
 dev/vt/font/vt_font_default.c	optional vt
 dev/vt/font/vt_mouse_cursor.c	optional vt
 dev/vt/hw/fb/vt_fb.c		optional vt
 dev/vt/hw/vga/vga.c		optional vt vt_vga
 dev/vt/logo/logo_freebsd.c	optional vt splash
 dev/vt/vt_buf.c			optional vt
 dev/vt/vt_consolectl.c		optional vt
 dev/vt/vt_core.c		optional vt
 dev/vt/vt_font.c		optional vt
 dev/vt/vt_sysmouse.c		optional vt
 dev/vte/if_vte.c		optional vte pci
 dev/vx/if_vx.c			optional vx
 dev/vx/if_vx_eisa.c		optional vx eisa
 dev/vx/if_vx_pci.c		optional vx pci
 dev/vxge/vxge.c				optional vxge
 dev/vxge/vxgehal/vxgehal-ifmsg.c	optional vxge
 dev/vxge/vxgehal/vxgehal-mrpcim.c	optional vxge
 dev/vxge/vxgehal/vxge-queue.c		optional vxge
 dev/vxge/vxgehal/vxgehal-ring.c		optional vxge
 dev/vxge/vxgehal/vxgehal-swapper.c	optional vxge
 dev/vxge/vxgehal/vxgehal-mgmt.c		optional vxge
 dev/vxge/vxgehal/vxgehal-srpcim.c	optional vxge
 dev/vxge/vxgehal/vxgehal-config.c	optional vxge
 dev/vxge/vxgehal/vxgehal-blockpool.c	optional vxge
 dev/vxge/vxgehal/vxgehal-doorbells.c	optional vxge
 dev/vxge/vxgehal/vxgehal-mgmtaux.c	optional vxge
 dev/vxge/vxgehal/vxgehal-device.c	optional vxge
 dev/vxge/vxgehal/vxgehal-mm.c		optional vxge
 dev/vxge/vxgehal/vxgehal-driver.c	optional vxge
 dev/vxge/vxgehal/vxgehal-virtualpath.c	optional vxge
 dev/vxge/vxgehal/vxgehal-channel.c	optional vxge
 dev/vxge/vxgehal/vxgehal-fifo.c		optional vxge
 dev/watchdog/watchdog.c		standard
 dev/wb/if_wb.c			optional wb pci
 dev/wds/wd7000.c		optional wds isa
 dev/wi/if_wi.c			optional wi
 dev/wi/if_wi_pccard.c		optional wi pccard
 dev/wi/if_wi_pci.c		optional wi pci
 dev/wl/if_wl.c			optional wl isa
 dev/wpi/if_wpi.c		optional wpi pci
 wpifw.c			optional wpifw					\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk wpi.fw:wpifw:153229 -mwpi -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
 	clean		"wpifw.c"
 wpifw.fwo			optional wpifw				\
 	dependency	"wpi.fw"					\
 	compile-with	"${NORMAL_FWO}"					\
 	no-implicit-rule						\
 	clean		"wpifw.fwo"
 wpi.fw			optional wpifw					\
 	dependency	"$S/contrib/dev/wpi/iwlwifi-3945-15.32.2.9.fw.uu"	\
 	compile-with	"${NORMAL_FW}"					\
 	no-obj no-implicit-rule						\
 	clean		"wpi.fw"
 dev/xe/if_xe.c			optional xe
 dev/xe/if_xe_pccard.c		optional xe pccard
 dev/xl/if_xl.c			optional xl pci
 dev/xl/xlphy.c			optional xl pci
 fs/coda/coda_fbsd.c		optional vcoda
 fs/coda/coda_psdev.c		optional vcoda
 fs/coda/coda_subr.c		optional vcoda
 fs/coda/coda_venus.c		optional vcoda
 fs/coda/coda_vfsops.c		optional vcoda
 fs/coda/coda_vnops.c		optional vcoda
 fs/deadfs/dead_vnops.c		standard
 fs/devfs/devfs_devs.c		standard
 fs/devfs/devfs_dir.c		standard
 fs/devfs/devfs_rule.c		standard
 fs/devfs/devfs_vfsops.c		standard
 fs/devfs/devfs_vnops.c		standard
 fs/fdescfs/fdesc_vfsops.c	optional fdescfs
 fs/fdescfs/fdesc_vnops.c	optional fdescfs
 fs/fifofs/fifo_vnops.c		standard
 fs/hpfs/hpfs_alsubr.c		optional hpfs
 fs/hpfs/hpfs_lookup.c		optional hpfs
 fs/hpfs/hpfs_subr.c		optional hpfs
 fs/hpfs/hpfs_vfsops.c		optional hpfs
 fs/hpfs/hpfs_vnops.c		optional hpfs
 fs/msdosfs/msdosfs_conv.c	optional msdosfs
 fs/msdosfs/msdosfs_denode.c	optional msdosfs
 fs/msdosfs/msdosfs_fat.c	optional msdosfs
 fs/msdosfs/msdosfs_fileno.c	optional msdosfs
 fs/msdosfs/msdosfs_iconv.c	optional msdosfs_iconv
 fs/msdosfs/msdosfs_lookup.c	optional msdosfs
 fs/msdosfs/msdosfs_vfsops.c	optional msdosfs
 fs/msdosfs/msdosfs_vnops.c	optional msdosfs
 fs/nfs/nfs_commonkrpc.c		optional nfscl | nfsd
 fs/nfs/nfs_commonsubs.c		optional nfscl | nfsd
 fs/nfs/nfs_commonport.c		optional nfscl | nfsd
 fs/nfs/nfs_commonacl.c		optional nfscl | nfsd
 fs/nfsclient/nfs_clcomsubs.c	optional nfscl
 fs/nfsclient/nfs_clsubs.c	optional nfscl
 fs/nfsclient/nfs_clstate.c	optional nfscl
 fs/nfsclient/nfs_clkrpc.c	optional nfscl
 fs/nfsclient/nfs_clrpcops.c	optional nfscl
 fs/nfsclient/nfs_clvnops.c	optional nfscl
 fs/nfsclient/nfs_clnode.c	optional nfscl
 fs/nfsclient/nfs_clvfsops.c	optional nfscl
 fs/nfsclient/nfs_clport.c	optional nfscl
 fs/nfsclient/nfs_clbio.c	optional nfscl
 fs/nfsclient/nfs_clnfsiod.c	optional nfscl
 fs/nfsserver/nfs_fha_new.c	optional nfsd inet
 fs/nfsserver/nfs_nfsdsocket.c	optional nfsd inet
 fs/nfsserver/nfs_nfsdsubs.c	optional nfsd inet
 fs/nfsserver/nfs_nfsdstate.c	optional nfsd inet
 fs/nfsserver/nfs_nfsdkrpc.c	optional nfsd inet
 fs/nfsserver/nfs_nfsdserv.c	optional nfsd inet
 fs/nfsserver/nfs_nfsdport.c	optional nfsd inet
 fs/nfsserver/nfs_nfsdcache.c	optional nfsd inet
 fs/ntfs/ntfs_compr.c		optional ntfs
 fs/ntfs/ntfs_iconv.c		optional ntfs_iconv
 fs/ntfs/ntfs_ihash.c		optional ntfs
 fs/ntfs/ntfs_subr.c		optional ntfs
 fs/ntfs/ntfs_vfsops.c		optional ntfs
 fs/ntfs/ntfs_vnops.c		optional ntfs
 fs/nullfs/null_subr.c		optional nullfs
 fs/nullfs/null_vfsops.c		optional nullfs
 fs/nullfs/null_vnops.c		optional nullfs
 fs/nwfs/nwfs_io.c		optional nwfs
 fs/nwfs/nwfs_ioctl.c		optional nwfs
 fs/nwfs/nwfs_node.c		optional nwfs
 fs/nwfs/nwfs_subr.c		optional nwfs
 fs/nwfs/nwfs_vfsops.c		optional nwfs
 fs/nwfs/nwfs_vnops.c		optional nwfs
 fs/portalfs/portal_vfsops.c	optional portalfs
 fs/portalfs/portal_vnops.c	optional portalfs
 fs/procfs/procfs.c		optional procfs
 fs/procfs/procfs_ctl.c		optional procfs
 fs/procfs/procfs_dbregs.c	optional procfs
 fs/procfs/procfs_fpregs.c	optional procfs
 fs/procfs/procfs_ioctl.c	optional procfs
 fs/procfs/procfs_map.c		optional procfs
 fs/procfs/procfs_mem.c		optional procfs
 fs/procfs/procfs_note.c		optional procfs
 fs/procfs/procfs_osrel.c	optional procfs
 fs/procfs/procfs_regs.c		optional procfs
 fs/procfs/procfs_rlimit.c	optional procfs
 fs/procfs/procfs_status.c	optional procfs
 fs/procfs/procfs_type.c		optional procfs
 fs/pseudofs/pseudofs.c		optional pseudofs
 fs/pseudofs/pseudofs_fileno.c	optional pseudofs
 fs/pseudofs/pseudofs_vncache.c	optional pseudofs
 fs/pseudofs/pseudofs_vnops.c	optional pseudofs
 fs/smbfs/smbfs_io.c		optional smbfs
 fs/smbfs/smbfs_node.c		optional smbfs
 fs/smbfs/smbfs_smb.c		optional smbfs
 fs/smbfs/smbfs_subr.c		optional smbfs
 fs/smbfs/smbfs_vfsops.c		optional smbfs
 fs/smbfs/smbfs_vnops.c		optional smbfs
 fs/udf/osta.c			optional udf
 fs/udf/udf_iconv.c		optional udf_iconv
 fs/udf/udf_vfsops.c		optional udf
 fs/udf/udf_vnops.c		optional udf
 fs/unionfs/union_subr.c		optional unionfs
 fs/unionfs/union_vfsops.c	optional unionfs
 fs/unionfs/union_vnops.c	optional unionfs
 fs/tmpfs/tmpfs_vnops.c		optional tmpfs
 fs/tmpfs/tmpfs_fifoops.c 	optional tmpfs
 fs/tmpfs/tmpfs_vfsops.c 	optional tmpfs
 fs/tmpfs/tmpfs_subr.c 		optional tmpfs
 gdb/gdb_cons.c			optional gdb
 gdb/gdb_main.c			optional gdb
 gdb/gdb_packet.c		optional gdb
 geom/bde/g_bde.c		optional geom_bde
 geom/bde/g_bde_crypt.c		optional geom_bde
 geom/bde/g_bde_lock.c		optional geom_bde
 geom/bde/g_bde_work.c		optional geom_bde
 geom/cache/g_cache.c		optional geom_cache
 geom/concat/g_concat.c		optional geom_concat
 geom/eli/g_eli.c		optional geom_eli
 geom/eli/g_eli_crypto.c		optional geom_eli
 geom/eli/g_eli_ctl.c		optional geom_eli
 geom/eli/g_eli_integrity.c	optional geom_eli
 geom/eli/g_eli_key.c		optional geom_eli
 geom/eli/g_eli_key_cache.c	optional geom_eli
 geom/eli/g_eli_privacy.c	optional geom_eli
 geom/eli/pkcs5v2.c		optional geom_eli
 geom/gate/g_gate.c		optional geom_gate
 geom/geom_aes.c			optional geom_aes
 geom/geom_bsd.c			optional geom_bsd
 geom/geom_bsd_enc.c		optional geom_bsd
 geom/geom_ccd.c			optional ccd | geom_ccd
 geom/geom_ctl.c			standard
 geom/geom_dev.c			standard
 geom/geom_disk.c		standard
 geom/geom_dump.c		standard
 geom/geom_event.c		standard
 geom/geom_fox.c			optional geom_fox
 geom/geom_io.c			standard
 geom/geom_kern.c		standard
 geom/geom_map.c			optional geom_map
 geom/geom_mbr.c			optional geom_mbr
 geom/geom_mbr_enc.c		optional geom_mbr
 geom/geom_pc98.c		optional geom_pc98
 geom/geom_pc98_enc.c		optional geom_pc98
 geom/geom_redboot.c		optional geom_redboot
 geom/geom_slice.c		standard
 geom/geom_subr.c		standard
 geom/geom_sunlabel.c		optional geom_sunlabel
 geom/geom_sunlabel_enc.c	optional geom_sunlabel
 geom/geom_vfs.c			standard
 geom/geom_vol_ffs.c		optional geom_vol
 geom/journal/g_journal.c	optional geom_journal
 geom/journal/g_journal_ufs.c	optional geom_journal
 geom/label/g_label.c		optional geom_label
 geom/label/g_label_ext2fs.c	optional geom_label
 geom/label/g_label_iso9660.c	optional geom_label
 geom/label/g_label_msdosfs.c	optional geom_label
 geom/label/g_label_ntfs.c	optional geom_label
 geom/label/g_label_reiserfs.c	optional geom_label
 geom/label/g_label_ufs.c	optional geom_label
 geom/label/g_label_gpt.c	optional geom_label
 geom/linux_lvm/g_linux_lvm.c	optional geom_linux_lvm
 geom/mirror/g_mirror.c		optional geom_mirror
 geom/mirror/g_mirror_ctl.c	optional geom_mirror
 geom/mountver/g_mountver.c	optional geom_mountver
 geom/multipath/g_multipath.c	optional geom_multipath
 geom/nop/g_nop.c		optional geom_nop
 geom/part/g_part.c		standard
 geom/part/g_part_if.m		standard
 geom/part/g_part_apm.c		optional geom_part_apm
 geom/part/g_part_bsd.c		optional geom_part_bsd
 geom/part/g_part_ebr.c		optional geom_part_ebr
 geom/part/g_part_gpt.c		optional geom_part_gpt
 geom/part/g_part_ldm.c		optional geom_part_ldm
 geom/part/g_part_mbr.c		optional geom_part_mbr
 geom/part/g_part_pc98.c		optional geom_part_pc98
 geom/part/g_part_vtoc8.c	optional geom_part_vtoc8
 geom/raid/g_raid.c		optional geom_raid
 geom/raid/g_raid_ctl.c		optional geom_raid
 geom/raid/g_raid_md_if.m	optional geom_raid
 geom/raid/g_raid_tr_if.m	optional geom_raid
 geom/raid/md_ddf.c		optional geom_raid
 geom/raid/md_intel.c		optional geom_raid
 geom/raid/md_jmicron.c		optional geom_raid
 geom/raid/md_nvidia.c		optional geom_raid
 geom/raid/md_promise.c		optional geom_raid
 geom/raid/md_sii.c		optional geom_raid
 geom/raid/tr_concat.c		optional geom_raid
 geom/raid/tr_raid0.c		optional geom_raid
 geom/raid/tr_raid1.c		optional geom_raid
 geom/raid/tr_raid1e.c		optional geom_raid
 geom/raid/tr_raid5.c		optional geom_raid
 geom/raid3/g_raid3.c		optional geom_raid3
 geom/raid3/g_raid3_ctl.c	optional geom_raid3
 geom/shsec/g_shsec.c		optional geom_shsec
 geom/stripe/g_stripe.c		optional geom_stripe
 geom/uncompress/g_uncompress.c	optional geom_uncompress
 contrib/xz-embedded/freebsd/xz_malloc.c	\
 	optional xz_embedded | geom_uncompress \
 	compile-with "${NORMAL_C} -I$S/contrib/xz-embedded/freebsd/ -I$S/contrib/xz-embedded/linux/lib/xz/ -I$S/contrib/xz-embedded/linux/include/linux/"
 contrib/xz-embedded/linux/lib/xz/xz_crc32.c \
 	optional xz_embedded | geom_uncompress \
 	compile-with "${NORMAL_C} -I$S/contrib/xz-embedded/freebsd/ -I$S/contrib/xz-embedded/linux/lib/xz/ -I$S/contrib/xz-embedded/linux/include/linux/"
 contrib/xz-embedded/linux/lib/xz/xz_dec_bcj.c \
 	optional xz_embedded | geom_uncompress \
 	compile-with "${NORMAL_C} -I$S/contrib/xz-embedded/freebsd/ -I$S/contrib/xz-embedded/linux/lib/xz/ -I$S/contrib/xz-embedded/linux/include/linux/"
 contrib/xz-embedded/linux/lib/xz/xz_dec_lzma2.c \
 	optional xz_embedded | geom_uncompress \
 	compile-with "${NORMAL_C} -I$S/contrib/xz-embedded/freebsd/ -I$S/contrib/xz-embedded/linux/lib/xz/ -I$S/contrib/xz-embedded/linux/include/linux/"
 contrib/xz-embedded/linux/lib/xz/xz_dec_stream.c \
 	optional xz_embedded | geom_uncompress \
 	compile-with "${NORMAL_C} -I$S/contrib/xz-embedded/freebsd/ -I$S/contrib/xz-embedded/linux/lib/xz/ -I$S/contrib/xz-embedded/linux/include/linux/"
 geom/uzip/g_uzip.c		optional geom_uzip
 geom/vinum/geom_vinum.c		optional geom_vinum
 geom/vinum/geom_vinum_create.c	optional geom_vinum
 geom/vinum/geom_vinum_drive.c	optional geom_vinum
 geom/vinum/geom_vinum_plex.c	optional geom_vinum
 geom/vinum/geom_vinum_volume.c	optional geom_vinum
 geom/vinum/geom_vinum_subr.c	optional geom_vinum
 geom/vinum/geom_vinum_raid5.c	optional geom_vinum
 geom/vinum/geom_vinum_share.c	optional geom_vinum
 geom/vinum/geom_vinum_list.c	optional geom_vinum
 geom/vinum/geom_vinum_rm.c	optional geom_vinum
 geom/vinum/geom_vinum_init.c	optional geom_vinum
 geom/vinum/geom_vinum_state.c	optional geom_vinum
 geom/vinum/geom_vinum_rename.c	optional geom_vinum
 geom/vinum/geom_vinum_move.c	optional geom_vinum
 geom/vinum/geom_vinum_events.c	optional geom_vinum
 geom/virstor/binstream.c	optional geom_virstor
 geom/virstor/g_virstor.c	optional geom_virstor
 geom/virstor/g_virstor_md.c	optional geom_virstor
 geom/zero/g_zero.c		optional geom_zero
 fs/ext2fs/ext2_alloc.c		optional ext2fs
 fs/ext2fs/ext2_balloc.c		optional ext2fs
 fs/ext2fs/ext2_bmap.c		optional ext2fs
 fs/ext2fs/ext2_extents.c	optional ext2fs
 fs/ext2fs/ext2_inode.c		optional ext2fs
 fs/ext2fs/ext2_inode_cnv.c	optional ext2fs
 fs/ext2fs/ext2_lookup.c		optional ext2fs
 fs/ext2fs/ext2_subr.c		optional ext2fs
 fs/ext2fs/ext2_vfsops.c		optional ext2fs
 fs/ext2fs/ext2_vnops.c		optional ext2fs
 gnu/fs/reiserfs/reiserfs_hashes.c	optional reiserfs \
 	warning "kernel contains GPL contaminated ReiserFS filesystem"
 gnu/fs/reiserfs/reiserfs_inode.c	optional reiserfs
 gnu/fs/reiserfs/reiserfs_item_ops.c	optional reiserfs
 gnu/fs/reiserfs/reiserfs_namei.c	optional reiserfs
 gnu/fs/reiserfs/reiserfs_prints.c	optional reiserfs
 gnu/fs/reiserfs/reiserfs_stree.c	optional reiserfs
 gnu/fs/reiserfs/reiserfs_vfsops.c	optional reiserfs
 gnu/fs/reiserfs/reiserfs_vnops.c	optional reiserfs
 #
 isa/isa_if.m			standard
 isa/isa_common.c		optional isa
 isa/isahint.c			optional isa
 isa/pnp.c			optional isa isapnp
 isa/pnpparse.c			optional isa isapnp
 fs/cd9660/cd9660_bmap.c	optional cd9660
 fs/cd9660/cd9660_lookup.c	optional cd9660
 fs/cd9660/cd9660_node.c	optional cd9660
 fs/cd9660/cd9660_rrip.c	optional cd9660
 fs/cd9660/cd9660_util.c	optional cd9660
 fs/cd9660/cd9660_vfsops.c	optional cd9660
 fs/cd9660/cd9660_vnops.c	optional cd9660
 fs/cd9660/cd9660_iconv.c	optional cd9660_iconv
 kern/bus_if.m			standard
 kern/clock_if.m			standard
 kern/cpufreq_if.m		standard
 kern/device_if.m		standard
 kern/imgact_elf.c		standard
 kern/imgact_shell.c		standard
 kern/inflate.c			optional gzip
 kern/init_main.c		standard
 kern/init_sysent.c		standard
 kern/ksched.c			optional _kposix_priority_scheduling
 kern/kern_acct.c		standard
 kern/kern_alq.c			optional alq
 kern/kern_clock.c		standard
 kern/kern_condvar.c		standard
 kern/kern_conf.c		standard
 kern/kern_cons.c		standard
 kern/kern_cpu.c			standard
 kern/kern_cpuset.c		standard
 kern/kern_context.c		standard
 kern/kern_descrip.c		standard
 kern/kern_dtrace.c		optional kdtrace_hooks
 kern/kern_environment.c		standard
 kern/kern_et.c			standard
 kern/kern_event.c		standard
 kern/kern_exec.c		standard
 kern/kern_exit.c		standard
 kern/kern_fail.c		standard
 kern/kern_fork.c		standard
 kern/kern_gzio.c		optional gzio
 kern/kern_hhook.c		standard
 kern/kern_idle.c		standard
 kern/kern_intr.c		standard
 kern/kern_jail.c		standard
 kern/kern_khelp.c		standard
 kern/kern_kthread.c		standard
 kern/kern_ktr.c			optional ktr
 kern/kern_ktrace.c		standard
 kern/kern_linker.c		standard
 kern/kern_lock.c		standard
 kern/kern_lockf.c		standard
 kern/kern_lockstat.c		optional kdtrace_hooks
 kern/kern_loginclass.c		standard
 kern/kern_malloc.c		standard
 kern/kern_mbuf.c		standard
 kern/kern_mib.c			standard
 kern/kern_module.c		standard
 kern/kern_mtxpool.c		standard
 kern/kern_mutex.c		standard
 kern/kern_ntptime.c		standard
 kern/kern_osd.c			standard
 kern/kern_physio.c		standard
 kern/kern_pmc.c			standard
 kern/kern_poll.c		optional device_polling
 kern/kern_priv.c		standard
 kern/kern_proc.c		standard
 kern/kern_prot.c		standard
 kern/kern_racct.c		standard
 kern/kern_rangelock.c		standard
 kern/kern_rctl.c		standard
 kern/kern_resource.c		standard
 kern/kern_rmlock.c		standard
 kern/kern_rwlock.c		standard
 kern/kern_sdt.c			optional kdtrace_hooks
 kern/kern_sema.c		standard
 kern/kern_sharedpage.c		standard
 kern/kern_shutdown.c		standard
 kern/kern_sig.c			standard
 kern/kern_switch.c		standard
 kern/kern_sx.c			standard
 kern/kern_synch.c		standard
 kern/kern_syscalls.c		standard
 kern/kern_sysctl.c		standard
 kern/kern_tc.c			standard
 kern/kern_thr.c			standard
 kern/kern_thread.c		standard
 kern/kern_time.c		standard
 kern/kern_timeout.c		standard
 kern/kern_umtx.c		standard
 kern/kern_uuid.c		standard
 kern/kern_xxx.c			standard
 kern/link_elf.c			standard
 kern/linker_if.m		standard
 kern/md4c.c			optional netsmb
 kern/md5c.c			standard
 kern/p1003_1b.c			standard
 kern/posix4_mib.c		standard
 kern/sched_4bsd.c		optional sched_4bsd
 kern/sched_ule.c		optional sched_ule
 kern/serdev_if.m		standard
 kern/stack_protector.c		standard \
 	compile-with "${NORMAL_C:N-fstack-protector*}"
 kern/subr_acl_nfs4.c		standard
 kern/subr_acl_posix1e.c		standard
 kern/subr_autoconf.c		standard
 kern/subr_blist.c		standard
 kern/subr_bus.c			standard
 kern/subr_bus_dma.c		standard
 kern/subr_bufring.c		standard
 kern/subr_clock.c		standard
 kern/subr_devstat.c		standard
 kern/subr_disk.c		standard
 kern/subr_eventhandler.c	standard
 kern/subr_fattime.c		standard
 kern/subr_firmware.c		optional firmware
 kern/subr_hash.c		standard
 kern/subr_hints.c		standard
 kern/subr_kdb.c			standard
 kern/subr_kobj.c		standard
 kern/subr_lock.c		standard
 kern/subr_log.c			standard
 kern/subr_mbpool.c		optional libmbpool
 kern/subr_mchain.c		optional libmchain
 kern/subr_module.c		standard
 kern/subr_msgbuf.c		standard
 kern/subr_param.c		standard
 kern/subr_pcpu.c		standard
 kern/subr_power.c		standard
 kern/subr_prf.c			standard
 kern/subr_prof.c		standard
 kern/subr_rman.c		standard
 kern/subr_rtc.c			standard
 kern/subr_sbuf.c		standard
 kern/subr_scanf.c		standard
 kern/subr_sglist.c		standard
 kern/subr_sleepqueue.c		standard
 kern/subr_smp.c			standard
 kern/subr_stack.c		optional ddb | stack | ktr
 kern/subr_taskqueue.c		standard
 kern/subr_terminal.c		optional vt
 kern/subr_trap.c		standard
 kern/subr_turnstile.c		standard
 kern/subr_uio.c			standard
 kern/subr_unit.c		standard
 kern/subr_witness.c		optional witness
 kern/sys_capability.c		standard
 kern/sys_generic.c		standard
 kern/sys_pipe.c			standard
 kern/sys_procdesc.c		standard
 kern/sys_process.c		standard
 kern/sys_socket.c		standard
 kern/syscalls.c			standard
 kern/sysv_ipc.c			standard
 kern/sysv_msg.c			optional sysvmsg
 kern/sysv_sem.c			optional sysvsem
 kern/sysv_shm.c			optional sysvshm
 kern/tty.c			standard
 kern/tty_compat.c		optional compat_43tty
 kern/tty_info.c			standard
 kern/tty_inq.c			standard
 kern/tty_outq.c			standard
 kern/tty_pts.c			standard
 kern/tty_tty.c			standard
 kern/tty_ttydisc.c		standard
 kern/uipc_accf.c		optional inet
 kern/uipc_cow.c			optional zero_copy_sockets
 kern/uipc_debug.c		optional ddb
 kern/uipc_domain.c		standard
 kern/uipc_mbuf.c		standard
 kern/uipc_mbuf2.c		standard
 kern/uipc_mqueue.c		optional p1003_1b_mqueue
 kern/uipc_sem.c			optional p1003_1b_semaphores
 kern/uipc_shm.c			standard
 kern/uipc_sockbuf.c		standard
 kern/uipc_socket.c		standard
 kern/uipc_syscalls.c		standard
 kern/uipc_usrreq.c		standard
 kern/vfs_acl.c			standard
 kern/vfs_aio.c			optional vfs_aio
 kern/vfs_bio.c			standard
 kern/vfs_cache.c		standard
 kern/vfs_cluster.c		standard
 kern/vfs_default.c		standard
 kern/vfs_export.c		standard
 kern/vfs_extattr.c		standard
 kern/vfs_hash.c			standard
 kern/vfs_init.c			standard
 kern/vfs_lookup.c		standard
 kern/vfs_mount.c		standard
 kern/vfs_mountroot.c		standard
 kern/vfs_subr.c			standard
 kern/vfs_syscalls.c		standard
 kern/vfs_vnops.c		standard
 #
 # Kernel GSS-API
 #
 gssd.h				optional kgssapi			\
 	dependency		"$S/kgssapi/gssd.x"			\
 	compile-with		"RPCGEN_CPP='${CPP}' rpcgen -hM $S/kgssapi/gssd.x | grep -v pthread.h > gssd.h" \
 	no-obj no-implicit-rule before-depend local			\
 	clean			"gssd.h"
 gssd_xdr.c			optional kgssapi			\
 	dependency		"$S/kgssapi/gssd.x gssd.h"		\
 	compile-with		"RPCGEN_CPP='${CPP}' rpcgen -c $S/kgssapi/gssd.x -o gssd_xdr.c" \
 	no-implicit-rule before-depend local				\
 	clean			"gssd_xdr.c"
 gssd_clnt.c			optional kgssapi			\
 	dependency		"$S/kgssapi/gssd.x gssd.h"		\
 	compile-with		"RPCGEN_CPP='${CPP}' rpcgen -lM $S/kgssapi/gssd.x | grep -v string.h > gssd_clnt.c" \
 	no-implicit-rule before-depend local				\
 	clean			"gssd_clnt.c"
 kgssapi/gss_accept_sec_context.c optional kgssapi
 kgssapi/gss_add_oid_set_member.c optional kgssapi
 kgssapi/gss_acquire_cred.c	optional kgssapi
 kgssapi/gss_canonicalize_name.c	optional kgssapi
 kgssapi/gss_create_empty_oid_set.c optional kgssapi
 kgssapi/gss_delete_sec_context.c optional kgssapi
 kgssapi/gss_display_status.c	optional kgssapi
 kgssapi/gss_export_name.c	optional kgssapi
 kgssapi/gss_get_mic.c		optional kgssapi
 kgssapi/gss_init_sec_context.c	optional kgssapi
 kgssapi/gss_impl.c		optional kgssapi
 kgssapi/gss_import_name.c	optional kgssapi
 kgssapi/gss_names.c		optional kgssapi
 kgssapi/gss_pname_to_uid.c	optional kgssapi
 kgssapi/gss_release_buffer.c	optional kgssapi
 kgssapi/gss_release_cred.c	optional kgssapi
 kgssapi/gss_release_name.c	optional kgssapi
 kgssapi/gss_release_oid_set.c	optional kgssapi
 kgssapi/gss_set_cred_option.c	optional kgssapi
 kgssapi/gss_test_oid_set_member.c optional kgssapi
 kgssapi/gss_unwrap.c		optional kgssapi
 kgssapi/gss_verify_mic.c	optional kgssapi
 kgssapi/gss_wrap.c		optional kgssapi
 kgssapi/gss_wrap_size_limit.c	optional kgssapi
 kgssapi/gssd_prot.c		optional kgssapi
 kgssapi/krb5/krb5_mech.c	optional kgssapi
 kgssapi/krb5/kcrypto.c		optional kgssapi
 kgssapi/krb5/kcrypto_aes.c	optional kgssapi
 kgssapi/krb5/kcrypto_arcfour.c	optional kgssapi
 kgssapi/krb5/kcrypto_des.c	optional kgssapi
 kgssapi/krb5/kcrypto_des3.c	optional kgssapi
 kgssapi/kgss_if.m		optional kgssapi
 kgssapi/gsstest.c		optional kgssapi_debug
 # These files in libkern/ are those needed by all architectures.  Some
 # of the files in libkern/ are only needed on some architectures, e.g.,
 # libkern/divdi3.c is needed by i386 but not alpha.  Also, some of these
 # routines may be optimized for a particular platform.  In either case,
 # the file should be moved to conf/files.<arch> from here.
 #
 libkern/arc4random.c		standard
 libkern/bcd.c			standard
 libkern/bsearch.c		standard
 libkern/crc32.c			standard
 libkern/fnmatch.c		standard
 libkern/iconv.c			optional libiconv
 libkern/iconv_converter_if.m	optional libiconv
 libkern/iconv_ucs.c		optional libiconv
 libkern/iconv_xlat.c		optional libiconv
 libkern/iconv_xlat16.c		optional libiconv
 libkern/index.c			standard
 libkern/inet_aton.c		standard
 libkern/inet_ntoa.c		standard
 libkern/inet_ntop.c		standard
 libkern/inet_pton.c		standard
 libkern/mcount.c		optional profiling-routine
 libkern/memcmp.c		standard
 libkern/qsort.c			standard
 libkern/qsort_r.c		standard
 libkern/random.c		standard
 libkern/rindex.c		standard
 libkern/scanc.c			standard
 libkern/skpc.c			standard
 libkern/strcasecmp.c		standard
 libkern/strcat.c		standard
 libkern/strcmp.c		standard
 libkern/strcpy.c		standard
 libkern/strcspn.c		standard
 libkern/strdup.c		standard
 libkern/strlcat.c		standard
 libkern/strlcpy.c		standard
 libkern/strlen.c		standard
 libkern/strncmp.c		standard
 libkern/strncpy.c		standard
 libkern/strnlen.c		standard
 libkern/strsep.c		standard
 libkern/strspn.c		standard
 libkern/strstr.c		standard
 libkern/strtol.c		standard
 libkern/strtoq.c		standard
 libkern/strtoul.c		standard
 libkern/strtouq.c		standard
 libkern/strvalid.c		standard
 net/bpf.c			standard
 net/bpf_buffer.c		optional bpf
 net/bpf_jitter.c		optional bpf_jitter
 net/bpf_filter.c		optional bpf | netgraph_bpf
 net/bpf_zerocopy.c		optional bpf
 net/bridgestp.c			optional bridge | if_bridge
 net/flowtable.c			optional flowtable inet | flowtable inet6
 net/ieee8023ad_lacp.c		optional lagg
 net/if.c			standard
 net/if_arcsubr.c		optional arcnet
 net/if_atmsubr.c		optional atm
 net/if_bridge.c			optional bridge inet | if_bridge inet
 net/if_clone.c			standard
 net/if_dead.c			standard
 net/if_debug.c			optional ddb
 net/if_disc.c			optional disc
 net/if_edsc.c			optional edsc
 net/if_ef.c			optional ef
 net/if_enc.c			optional enc ipsec inet | enc ipsec inet6
 net/if_epair.c			optional epair
 net/if_ethersubr.c		optional ether \
 	compile-with "${NORMAL_C} -I$S/contrib/pf"
 net/if_faith.c			optional faith
 net/if_fddisubr.c		optional fddi
 net/if_fwsubr.c			optional fwip
 net/if_gif.c			optional gif | netgraph_gif
 net/if_gre.c			optional gre inet
 net/if_iso88025subr.c		optional token
 net/if_lagg.c			optional lagg
 net/if_loop.c			optional loop
 net/if_llatbl.c			standard
 net/if_media.c			standard
 net/if_mib.c			standard
 net/if_spppfr.c			optional sppp | netgraph_sppp
 net/if_spppsubr.c		optional sppp | netgraph_sppp
 net/if_stf.c			optional stf inet inet6
 net/if_tun.c			optional tun
 net/if_tap.c			optional tap
 net/if_vlan.c			optional vlan
 net/mppcc.c			optional netgraph_mppc_compression
 net/mppcd.c			optional netgraph_mppc_compression
 net/netisr.c			standard
 net/pfil.c			optional ether | inet
 net/radix.c			standard
 net/radix_mpath.c		standard
 net/raw_cb.c			standard
 net/raw_usrreq.c		standard
 net/route.c			standard
 net/rtsock.c			standard
 net/slcompress.c		optional netgraph_vjc | sppp | \
 					 netgraph_sppp
 net/vnet.c			optional vimage
 net/zlib.c			optional crypto | geom_uzip | ipsec | \
 					 mxge | netgraph_deflate | \
 					 ddb_ctf | gzio | geom_uncompress
 net80211/ieee80211.c		optional wlan
 net80211/ieee80211_acl.c	optional wlan wlan_acl
 net80211/ieee80211_action.c	optional wlan
 net80211/ieee80211_ageq.c	optional wlan
 net80211/ieee80211_adhoc.c	optional wlan \
 	compile-with "${NORMAL_C} -Wno-unused-function"
 net80211/ieee80211_ageq.c	optional wlan
 net80211/ieee80211_amrr.c	optional wlan | wlan_amrr
 net80211/ieee80211_crypto.c	optional wlan \
 	compile-with "${NORMAL_C} -Wno-unused-function"
 net80211/ieee80211_crypto_ccmp.c optional wlan wlan_ccmp
 net80211/ieee80211_crypto_none.c optional wlan
 net80211/ieee80211_crypto_tkip.c optional wlan wlan_tkip
 net80211/ieee80211_crypto_wep.c	optional wlan wlan_wep
 net80211/ieee80211_ddb.c	optional wlan ddb
 net80211/ieee80211_dfs.c	optional wlan
 net80211/ieee80211_freebsd.c	optional wlan
 net80211/ieee80211_hostap.c	optional wlan \
 	compile-with "${NORMAL_C} -Wno-unused-function"
 net80211/ieee80211_ht.c		optional wlan
 net80211/ieee80211_hwmp.c	optional wlan ieee80211_support_mesh
 net80211/ieee80211_input.c	optional wlan
 net80211/ieee80211_ioctl.c	optional wlan
 net80211/ieee80211_mesh.c	optional wlan ieee80211_support_mesh \
 	compile-with "${NORMAL_C} -Wno-unused-function"
 net80211/ieee80211_monitor.c	optional wlan
 net80211/ieee80211_node.c	optional wlan
 net80211/ieee80211_output.c	optional wlan
 net80211/ieee80211_phy.c	optional wlan
 net80211/ieee80211_power.c	optional wlan
 net80211/ieee80211_proto.c	optional wlan
 net80211/ieee80211_radiotap.c	optional wlan
 net80211/ieee80211_ratectl.c	optional wlan
 net80211/ieee80211_ratectl_none.c optional wlan
 net80211/ieee80211_regdomain.c	optional wlan
 net80211/ieee80211_rssadapt.c	optional wlan wlan_rssadapt
 net80211/ieee80211_scan.c	optional wlan
 net80211/ieee80211_scan_sta.c	optional wlan
 net80211/ieee80211_sta.c	optional wlan \
 	compile-with "${NORMAL_C} -Wno-unused-function"
 net80211/ieee80211_superg.c	optional wlan ieee80211_support_superg
 net80211/ieee80211_tdma.c	optional wlan ieee80211_support_tdma
 net80211/ieee80211_wds.c	optional wlan
 net80211/ieee80211_xauth.c	optional wlan wlan_xauth
 net80211/ieee80211_alq.c	optional wlan ieee80211_alq
 netatalk/aarp.c			optional netatalk
 netatalk/at_control.c		optional netatalk
 netatalk/at_proto.c		optional netatalk
 netatalk/at_rmx.c		optional netatalk
 netatalk/ddp_input.c		optional netatalk
 netatalk/ddp_output.c		optional netatalk
 netatalk/ddp_pcb.c		optional netatalk
 netatalk/ddp_usrreq.c		optional netatalk
 netgraph/atm/ccatm/ng_ccatm.c	optional ngatm_ccatm \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 netgraph/atm/ng_atm.c		optional ngatm_atm
 netgraph/atm/ngatmbase.c	optional ngatm_atmbase \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 netgraph/atm/sscfu/ng_sscfu.c	optional ngatm_sscfu \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 netgraph/atm/sscop/ng_sscop.c optional ngatm_sscop \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 netgraph/atm/uni/ng_uni.c	optional ngatm_uni \
 	compile-with "${NORMAL_C} -I$S/contrib/ngatm"
 netgraph/bluetooth/common/ng_bluetooth.c optional netgraph_bluetooth
 netgraph/bluetooth/drivers/bt3c/ng_bt3c_pccard.c optional netgraph_bluetooth_bt3c
 netgraph/bluetooth/drivers/h4/ng_h4.c optional netgraph_bluetooth_h4
 netgraph/bluetooth/drivers/ubt/ng_ubt.c optional netgraph_bluetooth_ubt usb
 netgraph/bluetooth/drivers/ubtbcmfw/ubtbcmfw.c optional netgraph_bluetooth_ubtbcmfw usb
 netgraph/bluetooth/hci/ng_hci_cmds.c optional netgraph_bluetooth_hci
 netgraph/bluetooth/hci/ng_hci_evnt.c optional netgraph_bluetooth_hci
 netgraph/bluetooth/hci/ng_hci_main.c optional netgraph_bluetooth_hci
 netgraph/bluetooth/hci/ng_hci_misc.c optional netgraph_bluetooth_hci
 netgraph/bluetooth/hci/ng_hci_ulpi.c optional netgraph_bluetooth_hci
 netgraph/bluetooth/l2cap/ng_l2cap_cmds.c optional netgraph_bluetooth_l2cap
 netgraph/bluetooth/l2cap/ng_l2cap_evnt.c optional netgraph_bluetooth_l2cap
 netgraph/bluetooth/l2cap/ng_l2cap_llpi.c optional netgraph_bluetooth_l2cap
 netgraph/bluetooth/l2cap/ng_l2cap_main.c optional netgraph_bluetooth_l2cap
 netgraph/bluetooth/l2cap/ng_l2cap_misc.c optional netgraph_bluetooth_l2cap
 netgraph/bluetooth/l2cap/ng_l2cap_ulpi.c optional netgraph_bluetooth_l2cap
 netgraph/bluetooth/socket/ng_btsocket.c optional netgraph_bluetooth_socket
 netgraph/bluetooth/socket/ng_btsocket_hci_raw.c	optional netgraph_bluetooth_socket
 netgraph/bluetooth/socket/ng_btsocket_l2cap.c optional netgraph_bluetooth_socket
 netgraph/bluetooth/socket/ng_btsocket_l2cap_raw.c optional netgraph_bluetooth_socket
 netgraph/bluetooth/socket/ng_btsocket_rfcomm.c optional netgraph_bluetooth_socket
 netgraph/bluetooth/socket/ng_btsocket_sco.c optional netgraph_bluetooth_socket
 netgraph/netflow/netflow.c	optional netgraph_netflow
 netgraph/netflow/netflow_v9.c	optional netgraph_netflow
 netgraph/netflow/ng_netflow.c	optional netgraph_netflow
 netgraph/ng_UI.c		optional netgraph_UI
 netgraph/ng_async.c		optional netgraph_async
 netgraph/ng_atmllc.c		optional netgraph_atmllc
 netgraph/ng_base.c		optional netgraph
 netgraph/ng_bpf.c		optional netgraph_bpf
 netgraph/ng_bridge.c		optional netgraph_bridge
 netgraph/ng_car.c		optional netgraph_car
 netgraph/ng_cisco.c		optional netgraph_cisco
 netgraph/ng_deflate.c		optional netgraph_deflate
 netgraph/ng_device.c		optional netgraph_device
 netgraph/ng_echo.c		optional netgraph_echo
 netgraph/ng_eiface.c		optional netgraph_eiface
 netgraph/ng_ether.c		optional netgraph_ether
 netgraph/ng_ether_echo.c	optional netgraph_ether_echo
 netgraph/ng_fec.c		optional netgraph_fec
 netgraph/ng_frame_relay.c	optional netgraph_frame_relay
 netgraph/ng_gif.c		optional netgraph_gif
 netgraph/ng_gif_demux.c		optional netgraph_gif_demux
 netgraph/ng_hole.c		optional netgraph_hole
 netgraph/ng_iface.c		optional netgraph_iface
 netgraph/ng_ip_input.c		optional netgraph_ip_input
 netgraph/ng_ipfw.c		optional netgraph_ipfw inet ipfirewall
 netgraph/ng_ksocket.c		optional netgraph_ksocket
 netgraph/ng_l2tp.c		optional netgraph_l2tp
 netgraph/ng_lmi.c		optional netgraph_lmi
 netgraph/ng_mppc.c		optional netgraph_mppc_compression | \
 					 netgraph_mppc_encryption
 netgraph/ng_nat.c		optional netgraph_nat inet libalias
 netgraph/ng_one2many.c		optional netgraph_one2many
 netgraph/ng_parse.c		optional netgraph
 netgraph/ng_patch.c		optional netgraph_patch
 netgraph/ng_pipe.c		optional netgraph_pipe
 netgraph/ng_ppp.c		optional netgraph_ppp
 netgraph/ng_pppoe.c		optional netgraph_pppoe
 netgraph/ng_pptpgre.c		optional netgraph_pptpgre
 netgraph/ng_pred1.c		optional netgraph_pred1
 netgraph/ng_rfc1490.c		optional netgraph_rfc1490
 netgraph/ng_socket.c		optional netgraph_socket
 netgraph/ng_split.c		optional netgraph_split
 netgraph/ng_sppp.c		optional netgraph_sppp
 netgraph/ng_tag.c		optional netgraph_tag
 netgraph/ng_tcpmss.c		optional netgraph_tcpmss
 netgraph/ng_tee.c		optional netgraph_tee
 netgraph/ng_tty.c		optional netgraph_tty
 netgraph/ng_vjc.c		optional netgraph_vjc
 netgraph/ng_vlan.c		optional netgraph_vlan
 netinet/accf_data.c		optional accept_filter_data inet
 netinet/accf_dns.c		optional accept_filter_dns inet
 netinet/accf_http.c		optional accept_filter_http inet
 netinet/if_atm.c		optional atm
 netinet/if_ether.c		optional inet ether
 netinet/igmp.c			optional inet
 netinet/in.c			optional inet
 netinet/in_debug.c		optional inet ddb
 netinet/ip_carp.c		optional inet carp | inet6 carp
 netinet/in_gif.c		optional gif inet | netgraph_gif inet
 netinet/ip_gre.c		optional gre inet
 netinet/ip_id.c			optional inet
 netinet/in_mcast.c		optional inet
 netinet/in_pcb.c		optional inet | inet6
 netinet/in_pcbgroup.c		optional inet pcbgroup | inet6 pcbgroup
 netinet/in_proto.c		optional inet | inet6 \
 	compile-with "${NORMAL_C} -I$S/contrib/pf"
 netinet/in_rmx.c		optional inet
 netinet/ip_divert.c		optional inet ipdivert ipfirewall
 netinet/ip_ecn.c		optional inet | inet6
 netinet/ip_encap.c		optional inet | inet6
 netinet/ip_fastfwd.c		optional inet
 netinet/ip_icmp.c		optional inet | inet6
 netinet/ip_input.c		optional inet
 netinet/ip_ipsec.c		optional inet ipsec
 netinet/ip_mroute.c		optional mrouting inet
 netinet/ip_options.c		optional inet
 netinet/ip_output.c		optional inet
 netinet/raw_ip.c		optional inet | inet6
 netinet/cc/cc.c			optional inet | inet6
 netinet/cc/cc_newreno.c		optional inet | inet6
 netinet/sctp_asconf.c		optional inet sctp | inet6 sctp
 netinet/sctp_auth.c		optional inet sctp | inet6 sctp
 netinet/sctp_bsd_addr.c		optional inet sctp | inet6 sctp
 netinet/sctp_cc_functions.c	optional inet sctp | inet6 sctp
 netinet/sctp_crc32.c		optional inet sctp | inet6 sctp
 netinet/sctp_indata.c		optional inet sctp | inet6 sctp
 netinet/sctp_input.c		optional inet sctp | inet6 sctp
 netinet/sctp_output.c		optional inet sctp | inet6 sctp
 netinet/sctp_pcb.c		optional inet sctp | inet6 sctp
 netinet/sctp_peeloff.c		optional inet sctp | inet6 sctp
 netinet/sctp_ss_functions.c	optional inet sctp | inet6 sctp
 netinet/sctp_sysctl.c		optional inet sctp | inet6 sctp
 netinet/sctp_timer.c		optional inet sctp | inet6 sctp
 netinet/sctp_usrreq.c		optional inet sctp | inet6 sctp
 netinet/sctputil.c		optional inet sctp | inet6 sctp
 netinet/tcp_debug.c		optional tcpdebug
 netinet/tcp_hostcache.c		optional inet | inet6
 netinet/tcp_input.c		optional inet | inet6
 netinet/tcp_lro.c		optional inet | inet6
 netinet/tcp_output.c		optional inet | inet6
 netinet/tcp_offload.c		optional tcp_offload inet | tcp_offload inet6
 netinet/tcp_reass.c		optional inet | inet6
 netinet/tcp_sack.c		optional inet | inet6
 netinet/tcp_subr.c		optional inet | inet6
 netinet/tcp_syncache.c		optional inet | inet6
 netinet/tcp_timer.c		optional inet | inet6
 netinet/tcp_timewait.c		optional inet | inet6
 netinet/tcp_usrreq.c		optional inet | inet6
 netinet/udp_usrreq.c		optional inet | inet6
 netinet/libalias/alias.c	optional libalias inet | netgraph_nat inet
 netinet/libalias/alias_db.c	optional libalias inet | netgraph_nat inet
 netinet/libalias/alias_mod.c	optional libalias | netgraph_nat
 netinet/libalias/alias_proxy.c	optional libalias inet | netgraph_nat inet
 netinet/libalias/alias_util.c	optional libalias inet | netgraph_nat inet
 netinet/libalias/alias_sctp.c	optional libalias inet | netgraph_nat inet
 netinet6/dest6.c		optional inet6
 netinet6/frag6.c		optional inet6
 netinet6/icmp6.c		optional inet6
 netinet6/in6.c			optional inet6
 netinet6/in6_cksum.c		optional inet6
 netinet6/in6_gif.c		optional gif inet6 | netgraph_gif inet6
 netinet6/in6_ifattach.c		optional inet6
 netinet6/in6_mcast.c		optional inet6
 netinet6/in6_pcb.c		optional inet6
 netinet6/in6_pcbgroup.c		optional inet6 pcbgroup
 netinet6/in6_proto.c		optional inet6
 netinet6/in6_rmx.c		optional inet6
 netinet6/in6_src.c		optional inet6
 netinet6/ip6_forward.c		optional inet6
 netinet6/ip6_id.c		optional inet6
 netinet6/ip6_input.c		optional inet6
 netinet6/ip6_mroute.c		optional mrouting inet6
 netinet6/ip6_output.c		optional inet6
 netinet6/ip6_ipsec.c		optional inet6 ipsec
 netinet6/mld6.c			optional inet6
 netinet6/nd6.c			optional inet6
 netinet6/nd6_nbr.c		optional inet6
 netinet6/nd6_rtr.c		optional inet6
 netinet6/raw_ip6.c		optional inet6
 netinet6/route6.c		optional inet6
 netinet6/scope6.c		optional inet6
 netinet6/sctp6_usrreq.c		optional inet6 sctp
 netinet6/udp6_usrreq.c		optional inet6
 netipsec/ipsec.c		optional ipsec inet | ipsec inet6
 netipsec/ipsec_input.c		optional ipsec inet | ipsec inet6
 netipsec/ipsec_mbuf.c		optional ipsec inet | ipsec inet6
 netipsec/ipsec_output.c		optional ipsec inet | ipsec inet6
 netipsec/key.c			optional ipsec inet | ipsec inet6
 netipsec/key_debug.c		optional ipsec inet | ipsec inet6
 netipsec/keysock.c		optional ipsec inet | ipsec inet6
 netipsec/xform_ah.c		optional ipsec inet | ipsec inet6
 netipsec/xform_esp.c		optional ipsec inet | ipsec inet6
 netipsec/xform_ipcomp.c		optional ipsec inet | ipsec inet6
 netipsec/xform_ipip.c		optional ipsec inet | ipsec inet6
 netipsec/xform_tcp.c		optional ipsec inet tcp_signature | \
 					 ipsec inet6 tcp_signature
 netipx/ipx.c			optional ipx
 netipx/ipx_cksum.c		optional ipx
 netipx/ipx_input.c		optional ipx
 netipx/ipx_outputfl.c		optional ipx
 netipx/ipx_pcb.c		optional ipx
 netipx/ipx_proto.c		optional ipx
 netipx/ipx_usrreq.c		optional ipx
 netipx/spx_debug.c		optional ipx
 netipx/spx_reass.c		optional ipx
 netipx/spx_usrreq.c		optional ipx
 netnatm/natm.c			optional natm
 netnatm/natm_pcb.c		optional natm
 netnatm/natm_proto.c		optional natm
 netncp/ncp_conn.c		optional ncp
 netncp/ncp_crypt.c		optional ncp
 netncp/ncp_login.c		optional ncp
 netncp/ncp_mod.c		optional ncp
 netncp/ncp_ncp.c		optional ncp
 netncp/ncp_nls.c		optional ncp
 netncp/ncp_rq.c			optional ncp
 netncp/ncp_sock.c		optional ncp
 netncp/ncp_subr.c		optional ncp
 netpfil/ipfw/dn_heap.c		optional inet dummynet
 netpfil/ipfw/dn_sched_fifo.c	optional inet dummynet
 netpfil/ipfw/dn_sched_prio.c	optional inet dummynet
 netpfil/ipfw/dn_sched_qfq.c	optional inet dummynet
 netpfil/ipfw/dn_sched_rr.c	optional inet dummynet
 netpfil/ipfw/dn_sched_wf2q.c	optional inet dummynet
 netpfil/ipfw/ip_dummynet.c	optional inet dummynet
 netpfil/ipfw/ip_dn_io.c		optional inet dummynet
 netpfil/ipfw/ip_dn_glue.c	optional inet dummynet
 netpfil/ipfw/ip_fw2.c		optional inet ipfirewall \
 	compile-with "${NORMAL_C} -I$S/contrib/pf"
 netpfil/ipfw/ip_fw_dynamic.c	optional inet ipfirewall
 netpfil/ipfw/ip_fw_log.c	optional inet ipfirewall
 netpfil/ipfw/ip_fw_pfil.c	optional inet ipfirewall
 netpfil/ipfw/ip_fw_sockopt.c	optional inet ipfirewall
 netpfil/ipfw/ip_fw_table.c	optional inet ipfirewall
 netpfil/ipfw/ip_fw_nat.c	optional inet ipfirewall_nat
 netsmb/smb_conn.c		optional netsmb
 netsmb/smb_crypt.c		optional netsmb
 netsmb/smb_dev.c		optional netsmb
 netsmb/smb_iod.c		optional netsmb
 netsmb/smb_rq.c			optional netsmb
 netsmb/smb_smb.c		optional netsmb
 netsmb/smb_subr.c		optional netsmb
 netsmb/smb_trantcp.c		optional netsmb
 netsmb/smb_usr.c		optional netsmb
 nfs/bootp_subr.c		optional bootp nfsclient | bootp nfscl
 nfs/krpc_subr.c			optional bootp nfsclient | bootp nfscl
 nfs/nfs_common.c		optional nfsclient | nfsserver
 nfs/nfs_diskless.c		optional nfsclient nfs_root | nfscl nfs_root
 nfs/nfs_fha.c			optional nfsserver | nfsd
 nfs/nfs_lock.c			optional nfsclient | nfscl | nfslockd | nfsd
 nfsclient/nfs_bio.c		optional nfsclient
 nfsclient/nfs_node.c		optional nfsclient
 nfsclient/nfs_krpc.c		optional nfsclient
 nfsclient/nfs_subs.c		optional nfsclient
 nfsclient/nfs_nfsiod.c		optional nfsclient
 nfsclient/nfs_vfsops.c		optional nfsclient
 nfsclient/nfs_vnops.c		optional nfsclient
 nfsserver/nfs_fha_old.c		optional nfsserver
 nfsserver/nfs_serv.c		optional nfsserver
 nfsserver/nfs_srvkrpc.c		optional nfsserver
 nfsserver/nfs_srvsubs.c		optional nfsserver
 nfs/nfs_nfssvc.c		optional nfsserver | nfscl | nfsd
 nlm/nlm_advlock.c		optional nfslockd | nfsd
 nlm/nlm_prot_clnt.c		optional nfslockd | nfsd
 nlm/nlm_prot_impl.c		optional nfslockd | nfsd
 nlm/nlm_prot_server.c		optional nfslockd | nfsd
 nlm/nlm_prot_svc.c		optional nfslockd | nfsd
 nlm/nlm_prot_xdr.c		optional nfslockd | nfsd
 nlm/sm_inter_xdr.c		optional nfslockd | nfsd
 
 # OpenFabrics Enterprise Distribution (Infiniband)
 ofed/include/linux/linux_compat.c		optional ofed		\
 	no-depend compile-with "${OFED_C}"
 ofed/include/linux/linux_idr.c			optional ofed		\
 	no-depend compile-with "${OFED_C}"
 ofed/include/linux/linux_radix.c		optional ofed		\
 	no-depend compile-with "${OFED_C}"
 ofed/drivers/infiniband/core/addr.c		optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"	
 ofed/drivers/infiniband/core/agent.c		optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/cache.c		optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 # XXX Mad.c must be ordered before cm.c for sysinit sets to occur in
 # the correct order.
 ofed/drivers/infiniband/core/mad.c		optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/cm.c		optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/ -Wno-unused-function"
 ofed/drivers/infiniband/core/cma.c		optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/device.c		optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/fmr_pool.c		optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/iwcm.c		optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/local_sa.c		optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/mad_rmpp.c		optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/multicast.c	optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/notice.c		optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/packer.c		optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/sa_query.c		optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/smi.c		optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/sysfs.c		optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/ucm.c		optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/ucma.c		optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/ud_header.c	optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/umem.c		optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/user_mad.c		optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/uverbs_cmd.c	optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/uverbs_main.c	optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/uverbs_marshall.c	optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/verbs.c		optional ofed		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 
 ofed/drivers/infiniband/ulp/ipoib/ipoib_cm.c	optional ipoib		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/"
 #ofed/drivers/infiniband/ulp/ipoib/ipoib_fs.c	optional ipoib		\
 #	no-depend							\
 #	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/"
 ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c	optional ipoib		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/"
 ofed/drivers/infiniband/ulp/ipoib/ipoib_main.c	optional ipoib		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/"
 ofed/drivers/infiniband/ulp/ipoib/ipoib_multicast.c	optional ipoib	\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/"
 ofed/drivers/infiniband/ulp/ipoib/ipoib_verbs.c	optional ipoib		\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/"
 #ofed/drivers/infiniband/ulp/ipoib/ipoib_vlan.c	optional ipoib		\
 #	no-depend							\
 #	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/"
 
 ofed/drivers/infiniband/ulp/sdp/sdp_bcopy.c	optional sdp inet	\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/"
 ofed/drivers/infiniband/ulp/sdp/sdp_main.c	optional sdp inet 	\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/"
 ofed/drivers/infiniband/ulp/sdp/sdp_rx.c	optional sdp inet 	\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/"
 ofed/drivers/infiniband/ulp/sdp/sdp_cma.c	optional sdp inet 	\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/"
 ofed/drivers/infiniband/ulp/sdp/sdp_tx.c	optional sdp inet 	\
 	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/"
 
 ofed/drivers/infiniband/hw/mlx4/alias_GUID.c    optional mlx4ib         \
         no-depend obj-prefix "mlx4ib_"                                  \
         compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/"
 ofed/drivers/infiniband/hw/mlx4/mcg.c           optional mlx4ib         \
         no-depend obj-prefix "mlx4ib_"                                  \
         compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/"
 ofed/drivers/infiniband/hw/mlx4/sysfs.c         optional mlx4ib         \
         no-depend obj-prefix "mlx4ib_"                                  \
         compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/"
 ofed/drivers/infiniband/hw/mlx4/cm.c            optional mlx4ib         \
         no-depend obj-prefix "mlx4ib_"                                  \
         compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/"
 ofed/drivers/infiniband/hw/mlx4/ah.c		optional mlx4ib		\
 	no-depend obj-prefix "mlx4ib_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/"
 ofed/drivers/infiniband/hw/mlx4/cq.c		optional mlx4ib		\
 	no-depend obj-prefix "mlx4ib_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/"
 ofed/drivers/infiniband/hw/mlx4/doorbell.c	optional mlx4ib		\
 	no-depend obj-prefix "mlx4ib_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/"
 ofed/drivers/infiniband/hw/mlx4/mad.c		optional mlx4ib		\
 	no-depend obj-prefix "mlx4ib_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/"
 ofed/drivers/infiniband/hw/mlx4/main.c		optional mlx4ib		\
 	no-depend obj-prefix "mlx4ib_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/"
 ofed/drivers/infiniband/hw/mlx4/mr.c		optional mlx4ib		\
 	no-depend obj-prefix "mlx4ib_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/"
 ofed/drivers/infiniband/hw/mlx4/qp.c		optional mlx4ib		\
 	no-depend obj-prefix "mlx4ib_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/"
 ofed/drivers/infiniband/hw/mlx4/srq.c		optional mlx4ib		\
 	no-depend obj-prefix "mlx4ib_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/"
 ofed/drivers/infiniband/hw/mlx4/wc.c		optional mlx4ib		\
 	no-depend obj-prefix "mlx4ib_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/"
 
 ofed/drivers/net/mlx4/alloc.c			optional mlx4ib | mlxen	\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/catas.c			optional mlx4ib | mlxen	\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/cmd.c			optional mlx4ib | mlxen	\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/cq.c			optional mlx4ib | mlxen	\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/eq.c			optional mlx4ib | mlxen	\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/fw.c			optional mlx4ib | mlxen	\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/icm.c			optional mlx4ib | mlxen	\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/intf.c			optional mlx4ib | mlxen	\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/main.c			optional mlx4ib | mlxen	\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/mcg.c			optional mlx4ib | mlxen	\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/ -Wno-unused"
 ofed/drivers/net/mlx4/mr.c			optional mlx4ib | mlxen	\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/pd.c			optional mlx4ib | mlxen	\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/port.c			optional mlx4ib | mlxen	\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/profile.c			optional mlx4ib | mlxen	\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/qp.c			optional mlx4ib | mlxen	\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/reset.c			optional mlx4ib | mlxen	\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/sense.c			optional mlx4ib | mlxen	\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/srq.c			optional mlx4ib | mlxen	\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/resource_tracker.c        optional mlx4ib | mlxen	\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/sys_tune.c		optional mlx4ib | mlxen	\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 
 ofed/drivers/net/mlx4/en_cq.c			optional mlxen		\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/utils.c			optional mlxen		\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/en_main.c			optional mlxen		\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/en_netdev.c		optional mlxen		\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/en_port.c			optional mlxen		\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/en_resources.c		optional mlxen		\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/en_rx.c			optional mlxen		\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 ofed/drivers/net/mlx4/en_tx.c			optional mlxen		\
 	no-depend obj-prefix "mlx4_"					\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 
 ofed/drivers/infiniband/hw/mthca/mthca_allocator.c	optional mthca	\
 	no-depend compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_av.c		optional mthca	\
 	no-depend compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_catas.c		optional mthca	\
 	no-depend compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_cmd.c		optional mthca	\
 	no-depend compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_cq.c		optional mthca	\
 	no-depend compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_eq.c		optional mthca	\
 	no-depend compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_mad.c		optional mthca	\
 	no-depend compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_main.c		optional mthca	\
 	no-depend compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_mcg.c		optional mthca	\
 	no-depend compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_memfree.c	optional mthca	\
 	no-depend compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_mr.c		optional mthca	\
 	no-depend compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_pd.c		optional mthca	\
 	no-depend compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_profile.c	optional mthca	\
 	no-depend compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_provider.c	optional mthca	\
 	no-depend compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_qp.c		optional mthca	\
 	no-depend compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_reset.c		optional mthca	\
 	no-depend compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_srq.c		optional mthca	\
 	no-depend compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_uar.c		optional mthca	\
 	no-depend compile-with "${OFED_C}"
 
 # crypto support
 opencrypto/cast.c		optional crypto | ipsec
 opencrypto/criov.c		optional crypto
 opencrypto/crypto.c		optional crypto
 opencrypto/cryptodev.c		optional cryptodev
 opencrypto/cryptodev_if.m	optional crypto
 opencrypto/cryptosoft.c		optional crypto
 opencrypto/deflate.c		optional crypto
 opencrypto/rmd160.c		optional crypto | ipsec
 opencrypto/skipjack.c		optional crypto
 opencrypto/xform.c		optional crypto
 pci/alpm.c			optional alpm pci
 pci/amdpm.c			optional amdpm pci | nfpm pci
 pci/amdsmb.c			optional amdsmb pci
-pci/if_rl.c			optional rl pci
 pci/intpm.c			optional intpm pci
 pci/ncr.c			optional ncr pci \
 	compile-with "${NORMAL_C} -Wno-unused"
 pci/nfsmb.c			optional nfsmb pci
 pci/viapm.c			optional viapm pci
 rpc/auth_none.c			optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd
 rpc/auth_unix.c			optional krpc | nfslockd | nfsclient | nfscl | nfsd
 rpc/authunix_prot.c		optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd
 rpc/clnt_dg.c			optional krpc | nfslockd | nfsclient | nfscl | nfsd
 rpc/clnt_rc.c			optional krpc | nfslockd | nfsclient | nfscl | nfsd
 rpc/clnt_vc.c			optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd
 rpc/getnetconfig.c		optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd
 rpc/replay.c			optional krpc | nfslockd | nfsserver | nfscl | nfsd
 rpc/rpc_callmsg.c		optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd
 rpc/rpc_generic.c		optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd
 rpc/rpc_prot.c			optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd
 rpc/rpcb_clnt.c			optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd
 rpc/rpcb_prot.c			optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd
 rpc/svc.c			optional krpc | nfslockd | nfsserver | nfscl | nfsd
 rpc/svc_auth.c			optional krpc | nfslockd | nfsserver | nfscl | nfsd
 rpc/svc_auth_unix.c		optional krpc | nfslockd | nfsserver | nfscl | nfsd
 rpc/svc_dg.c			optional krpc | nfslockd | nfsserver | nfscl | nfsd
 rpc/svc_generic.c		optional krpc | nfslockd | nfsserver | nfscl | nfsd
 rpc/svc_vc.c			optional krpc | nfslockd | nfsserver | nfscl | nfsd
 rpc/rpcsec_gss/rpcsec_gss.c	optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi
 rpc/rpcsec_gss/rpcsec_gss_conf.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi
 rpc/rpcsec_gss/rpcsec_gss_misc.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi
 rpc/rpcsec_gss/rpcsec_gss_prot.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi
 rpc/rpcsec_gss/svc_rpcsec_gss.c	optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi
 security/audit/audit.c		optional audit
 security/audit/audit_arg.c	optional audit
 security/audit/audit_bsm.c	optional audit
 security/audit/audit_bsm_domain.c	optional audit
 security/audit/audit_bsm_errno.c	optional audit
 security/audit/audit_bsm_fcntl.c	optional audit
 security/audit/audit_bsm_klib.c	optional audit
 security/audit/audit_bsm_socket_type.c	optional audit
 security/audit/audit_bsm_token.c	optional audit
 security/audit/audit_pipe.c	optional audit
 security/audit/audit_syscalls.c	standard
 security/audit/audit_trigger.c	optional audit
 security/audit/audit_worker.c	optional audit
 security/mac/mac_atalk.c	optional mac netatalk
 security/mac/mac_audit.c	optional mac audit
 security/mac/mac_cred.c		optional mac
 security/mac/mac_framework.c	optional mac
 security/mac/mac_inet.c		optional mac inet | mac inet6
 security/mac/mac_inet6.c	optional mac inet6
 security/mac/mac_label.c	optional mac
 security/mac/mac_net.c		optional mac
 security/mac/mac_pipe.c		optional mac
 security/mac/mac_posix_sem.c	optional mac
 security/mac/mac_posix_shm.c	optional mac
 security/mac/mac_priv.c		optional mac
 security/mac/mac_process.c	optional mac
 security/mac/mac_socket.c	optional mac
 security/mac/mac_syscalls.c	standard
 security/mac/mac_system.c	optional mac
 security/mac/mac_sysv_msg.c	optional mac
 security/mac/mac_sysv_sem.c	optional mac
 security/mac/mac_sysv_shm.c	optional mac
 security/mac/mac_vfs.c		optional mac
 security/mac_biba/mac_biba.c	optional mac_biba
 security/mac_bsdextended/mac_bsdextended.c optional mac_bsdextended
 security/mac_bsdextended/ugidfw_system.c optional mac_bsdextended
 security/mac_bsdextended/ugidfw_vnode.c optional mac_bsdextended
 security/mac_ifoff/mac_ifoff.c	optional mac_ifoff
 security/mac_lomac/mac_lomac.c	optional mac_lomac
 security/mac_mls/mac_mls.c	optional mac_mls
 security/mac_none/mac_none.c	optional mac_none
 security/mac_partition/mac_partition.c optional mac_partition
 security/mac_portacl/mac_portacl.c optional mac_portacl
 security/mac_seeotheruids/mac_seeotheruids.c optional mac_seeotheruids
 security/mac_stub/mac_stub.c	optional mac_stub
 security/mac_test/mac_test.c	optional mac_test
 teken/teken.c			optional sc | vt
 ufs/ffs/ffs_alloc.c		optional ffs
 ufs/ffs/ffs_balloc.c		optional ffs
 ufs/ffs/ffs_inode.c		optional ffs
 ufs/ffs/ffs_snapshot.c		optional ffs
 ufs/ffs/ffs_softdep.c		optional ffs
 ufs/ffs/ffs_subr.c		optional ffs
 ufs/ffs/ffs_tables.c		optional ffs
 ufs/ffs/ffs_vfsops.c		optional ffs
 ufs/ffs/ffs_vnops.c		optional ffs
 ufs/ffs/ffs_rawread.c		optional directio
 ufs/ffs/ffs_suspend.c		optional ffs
 ufs/ufs/ufs_acl.c		optional ffs
 ufs/ufs/ufs_bmap.c		optional ffs
 ufs/ufs/ufs_dirhash.c		optional ffs
 ufs/ufs/ufs_extattr.c		optional ffs
 ufs/ufs/ufs_gjournal.c		optional ffs UFS_GJOURNAL
 ufs/ufs/ufs_inode.c		optional ffs
 ufs/ufs/ufs_lookup.c		optional ffs
 ufs/ufs/ufs_quota.c		optional ffs
 ufs/ufs/ufs_vfsops.c		optional ffs
 ufs/ufs/ufs_vnops.c		optional ffs
 vm/default_pager.c		standard
 vm/device_pager.c		standard
 vm/phys_pager.c			standard
 vm/redzone.c			optional DEBUG_REDZONE
 vm/sg_pager.c			standard
 vm/swap_pager.c			standard
 vm/uma_core.c			standard
 vm/uma_dbg.c			standard
 vm/vm_contig.c			standard
 vm/memguard.c			optional DEBUG_MEMGUARD
 vm/vm_fault.c			standard
 vm/vm_glue.c			standard
 vm/vm_init.c			standard
 vm/vm_kern.c			standard
 vm/vm_map.c			standard
 vm/vm_meter.c			standard
 vm/vm_mmap.c			standard
 vm/vm_object.c			standard
 vm/vm_page.c			standard
 vm/vm_pageout.c			standard
 vm/vm_pager.c			standard
 vm/vm_phys.c			standard
 vm/vm_reserv.c			standard
 vm/vm_unix.c			standard
 vm/vm_zeroidle.c		standard
 vm/vnode_pager.c		standard
 xdr/xdr.c			optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd
 xdr/xdr_array.c			optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd
 xdr/xdr_mbuf.c			optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd
 xdr/xdr_mem.c			optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd
 xdr/xdr_reference.c		optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd
 xdr/xdr_sizeof.c		optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd
 #
 gnu/fs/xfs/xfs_alloc.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" \
 	warning "kernel contains GPL contaminated xfs filesystem"
 gnu/fs/xfs/xfs_alloc_btree.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_bit.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_bmap.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_bmap_btree.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_btree.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_buf_item.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_da_btree.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_dir.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_dir2.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_dir2_block.c	optional xfs \
 	compile-with "${NORMAL_C} ${NO_WARRAY_BOUNDS} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_dir2_data.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_dir2_leaf.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_dir2_node.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_dir2_sf.c	optional xfs \
 	compile-with "${NORMAL_C} ${NO_WARRAY_BOUNDS} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_dir2_trace.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_dir_leaf.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_error.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_extfree_item.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_fsops.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_ialloc.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_ialloc_btree.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_inode.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_inode_item.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_iocore.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_itable.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_dfrag.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_log.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_log_recover.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_mount.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_rename.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_trans.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_trans_ail.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_trans_buf.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_trans_extfree.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_trans_inode.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_trans_item.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_utils.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_vfsops.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_vnodeops.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_rw.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_attr_leaf.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_attr.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_dmops.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_qmops.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_iget.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/FreeBSD/xfs_freebsd_iget.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/FreeBSD/xfs_mountops.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/FreeBSD/xfs_vnops.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/FreeBSD/xfs_frw.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/FreeBSD/xfs_buf.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/FreeBSD/xfs_globals.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/FreeBSD/xfs_dmistubs.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/FreeBSD/xfs_super.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/FreeBSD/xfs_stats.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/FreeBSD/xfs_vfs.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/FreeBSD/xfs_vnode.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/FreeBSD/xfs_sysctl.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/FreeBSD/xfs_fs_subr.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/FreeBSD/xfs_ioctl.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/FreeBSD/support/debug.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/FreeBSD/support/ktrace.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/FreeBSD/support/mrlock.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/FreeBSD/support/uuid.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/FreeBSD/support/kmem.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_iomap.c		optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 gnu/fs/xfs/xfs_behavior.c	optional xfs \
 	compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs"
 
 xen/gnttab.c			optional xen | xenhvm
 xen/features.c			optional xen | xenhvm
 xen/evtchn/evtchn.c		optional xen
 xen/evtchn/evtchn_dev.c		optional xen | xenhvm
 xen/xenbus/xenbus_if.m		optional xen | xenhvm
 xen/xenbus/xenbus.c		optional xen | xenhvm
 xen/xenbus/xenbusb_if.m		optional xen | xenhvm
 xen/xenbus/xenbusb.c		optional xen | xenhvm
 xen/xenbus/xenbusb_front.c	optional xen | xenhvm
 xen/xenbus/xenbusb_back.c	optional xen | xenhvm
 xen/xenstore/xenstore.c		optional xen | xenhvm
 xen/xenstore/xenstore_dev.c	optional xen | xenhvm
 dev/xen/balloon/balloon.c	optional xen | xenhvm
 dev/xen/blkfront/blkfront.c	optional xen | xenhvm
 dev/xen/blkback/blkback.c	optional xen | xenhvm
 dev/xen/console/console.c	optional xen
 dev/xen/console/xencons_ring.c	optional xen
 dev/xen/control/control.c	optional xen | xenhvm
 dev/xen/netback/netback.c	optional xen | xenhvm
 dev/xen/netfront/netfront.c	optional xen | xenhvm
 dev/xen/xenpci/xenpci.c		optional xenpci
 dev/xen/xenpci/evtchn.c         optional xenpci
Index: stable/9/sys/conf
===================================================================
--- stable/9/sys/conf	(revision 292780)
+++ stable/9/sys/conf	(revision 292781)

Property changes on: stable/9/sys/conf
___________________________________________________________________
Modified: svn:mergeinfo
## -0,0 +0,1 ##
   Merged /head/sys/conf:r271864
Index: stable/9/sys/dev/mii/rgephy.c
===================================================================
--- stable/9/sys/dev/mii/rgephy.c	(revision 292780)
+++ stable/9/sys/dev/mii/rgephy.c	(revision 292781)
@@ -1,562 +1,562 @@
 /*-
  * Copyright (c) 2003
  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Bill Paul.
  * 4. Neither the name of the author nor the names of any co-contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
 /*
  * Driver for the RealTek 8169S/8110S/8211B/8211C internal 10/100/1000 PHY.
  */
 
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/module.h>
 #include <sys/socket.h>
 #include <sys/bus.h>
 
 #include <net/if.h>
 #include <net/if_arp.h>
 #include <net/if_media.h>
 
 #include <dev/mii/mii.h>
 #include <dev/mii/miivar.h>
 #include "miidevs.h"
 
 #include <dev/mii/rgephyreg.h>
 
 #include "miibus_if.h"
 
 #include <machine/bus.h>
-#include <pci/if_rlreg.h>
+#include <dev/rl/if_rlreg.h>
 
 static int rgephy_probe(device_t);
 static int rgephy_attach(device_t);
 
 static device_method_t rgephy_methods[] = {
 	/* device interface */
 	DEVMETHOD(device_probe,		rgephy_probe),
 	DEVMETHOD(device_attach,	rgephy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
 	DEVMETHOD_END
 };
 
 static devclass_t rgephy_devclass;
 
 static driver_t rgephy_driver = {
 	"rgephy",
 	rgephy_methods,
 	sizeof(struct mii_softc)
 };
 
 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0);
 
 static int	rgephy_service(struct mii_softc *, struct mii_data *, int);
 static void	rgephy_status(struct mii_softc *);
 static int	rgephy_mii_phy_auto(struct mii_softc *, int);
 static void	rgephy_reset(struct mii_softc *);
 static int	rgephy_linkup(struct mii_softc *);
 static void	rgephy_loop(struct mii_softc *);
 static void	rgephy_load_dspcode(struct mii_softc *);
 
 static const struct mii_phydesc rgephys[] = {
 	MII_PHY_DESC(REALTEK, RTL8169S),
 	MII_PHY_DESC(REALTEK, RTL8251),
 	MII_PHY_END
 };
 
 static const struct mii_phy_funcs rgephy_funcs = {
 	rgephy_service,
 	rgephy_status,
 	rgephy_reset
 };
 
 static int
 rgephy_probe(device_t dev)
 {
 
 	return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT));
 }
 
 static int
 rgephy_attach(device_t dev)
 {
 	struct mii_softc *sc;
 	struct mii_attach_args *ma;
 	u_int flags;
 
 	sc = device_get_softc(dev);
 	ma = device_get_ivars(dev);
 	flags = 0;
 	if (strcmp(ma->mii_data->mii_ifp->if_dname, "re") == 0)
 		flags |= MIIF_PHYPRIV0;
 	mii_phy_dev_attach(dev, flags, &rgephy_funcs, 0);
 
 	/* RTL8169S do not report auto-sense; add manually. */
 	sc->mii_capabilities = (PHY_READ(sc, MII_BMSR) | BMSR_ANEG) &
 	    sc->mii_capmask;
 	if (sc->mii_capabilities & BMSR_EXTSTAT)
 		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
 	device_printf(dev, " ");
 	mii_phy_add_media(sc);
 	printf("\n");
 	/*
 	 * Allow IFM_FLAG0 to be set indicating that auto-negotiation with
 	 * manual configuration, which is used to work around issues with
 	 * certain setups by default, should not be triggered as it may in
 	 * turn cause harm in some edge cases.
 	 */
 	sc->mii_pdata->mii_media.ifm_mask |= IFM_FLAG0;
 
 	PHY_RESET(sc);
 
 	MIIBUS_MEDIAINIT(sc->mii_dev);
 	return (0);
 }
 
 static int
 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
 {
 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
 	int speed, gig, anar;
 
 	switch (cmd) {
 	case MII_POLLSTAT:
 		break;
 
 	case MII_MEDIACHG:
 		/*
 		 * If the interface is not up, don't do anything.
 		 */
 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 			break;
 
 		PHY_RESET(sc);	/* XXX hardware bug work-around */
 
 		anar = PHY_READ(sc, RGEPHY_MII_ANAR);
 		anar &= ~(RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP |
 		    RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX |
 		    RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10);
 
 		switch (IFM_SUBTYPE(ife->ifm_media)) {
 		case IFM_AUTO:
 #ifdef foo
 			/*
 			 * If we're already in auto mode, just return.
 			 */
 			if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
 				return (0);
 #endif
 			(void)rgephy_mii_phy_auto(sc, ife->ifm_media);
 			break;
 		case IFM_1000_T:
 			speed = RGEPHY_S1000;
 			goto setit;
 		case IFM_100_TX:
 			speed = RGEPHY_S100;
 			anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX;
 			goto setit;
 		case IFM_10_T:
 			speed = RGEPHY_S10;
 			anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10;
 setit:
 			if ((ife->ifm_media & IFM_FLOW) != 0 &&
 			    (mii->mii_media.ifm_media & IFM_FLAG0) != 0)
 				return (EINVAL);
 
 			if ((ife->ifm_media & IFM_FDX) != 0) {
 				speed |= RGEPHY_BMCR_FDX;
 				gig = RGEPHY_1000CTL_AFD;
 				anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10);
 				if ((ife->ifm_media & IFM_FLOW) != 0 ||
 				    (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
 					anar |=
 					    RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP;
 			} else {
 				gig = RGEPHY_1000CTL_AHD;
 				anar &=
 				    ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD);
 			}
 			if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
 				gig |= RGEPHY_1000CTL_MSE;
 				if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
 				    gig |= RGEPHY_1000CTL_MSC;
 			} else {
 				gig = 0;
 				anar &= ~RGEPHY_ANAR_ASP;
 			}
 			if ((mii->mii_media.ifm_media & IFM_FLAG0) == 0)
 				speed |=
 				    RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG;
 			rgephy_loop(sc);
 			PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig);
 			PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
 			PHY_WRITE(sc, RGEPHY_MII_BMCR, speed);
 			break;
 		case IFM_NONE:
 			PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);
 			break;
 		default:
 			return (EINVAL);
 		}
 		break;
 
 	case MII_TICK:
 		/*
 		 * Is the interface even up?
 		 */
 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 			return (0);
 
 		/*
 		 * Only used for autonegotiation.
 		 */
 		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
 			sc->mii_ticks = 0;
 			break;
 		}
 
 		/*
 		 * Check to see if we have link.  If we do, we don't
 		 * need to restart the autonegotiation process.
 		 */
 		if (rgephy_linkup(sc) != 0) {
 			sc->mii_ticks = 0;
 			break;
 		}
 
 		/* Announce link loss right after it happens. */
 		if (sc->mii_ticks++ == 0)
 			break;
 
 		/* Only retry autonegotiation every mii_anegticks seconds. */
 		if (sc->mii_ticks <= sc->mii_anegticks)
 			return (0);
 
 		sc->mii_ticks = 0;
 		rgephy_mii_phy_auto(sc, ife->ifm_media);
 		break;
 	}
 
 	/* Update the media status. */
 	PHY_STATUS(sc);
 
 	/*
 	 * Callback if something changed. Note that we need to poke
 	 * the DSP on the RealTek PHYs if the media changes.
 	 *
 	 */
 	if (sc->mii_media_active != mii->mii_media_active ||
 	    sc->mii_media_status != mii->mii_media_status ||
 	    cmd == MII_MEDIACHG) {
 		rgephy_load_dspcode(sc);
 	}
 	mii_phy_update(sc, cmd);
 	return (0);
 }
 
 static int
 rgephy_linkup(struct mii_softc *sc)
 {
 	int linkup;
 	uint16_t reg;
 
 	linkup = 0;
 	if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 &&
 	    sc->mii_mpd_rev >= RGEPHY_8211B) {
 		if (sc->mii_mpd_rev == RGEPHY_8211F) {
 			reg = PHY_READ(sc, RGEPHY_F_MII_SSR);
 			if (reg & RGEPHY_F_SSR_LINK)
 				linkup++;
 		} else {
 			reg = PHY_READ(sc, RGEPHY_MII_SSR);
 			if (reg & RGEPHY_SSR_LINK)
 				linkup++;
 		}
 	} else {
 		reg = PHY_READ(sc, RL_GMEDIASTAT);
 		if (reg & RL_GMEDIASTAT_LINK)
 			linkup++;
 	}
 
 	return (linkup);
 }
 
 static void
 rgephy_status(struct mii_softc *sc)
 {
 	struct mii_data *mii = sc->mii_pdata;
 	int bmsr, bmcr;
 	uint16_t ssr;
 
 	mii->mii_media_status = IFM_AVALID;
 	mii->mii_media_active = IFM_ETHER;
 
 	if (rgephy_linkup(sc) != 0)
 		mii->mii_media_status |= IFM_ACTIVE;
 
 	bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
 	bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
 	if (bmcr & RGEPHY_BMCR_ISO) {
 		mii->mii_media_active |= IFM_NONE;
 		mii->mii_media_status = 0;
 		return;
 	}
 
 	if (bmcr & RGEPHY_BMCR_LOOP)
 		mii->mii_media_active |= IFM_LOOP;
 
 	if (bmcr & RGEPHY_BMCR_AUTOEN) {
 		if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
 			/* Erg, still trying, I guess... */
 			mii->mii_media_active |= IFM_NONE;
 			return;
 		}
 	}
 
 	if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 &&
 	    sc->mii_mpd_rev >= RGEPHY_8211B) {
 		if (sc->mii_mpd_rev == RGEPHY_8211F) {
 			ssr = PHY_READ(sc, RGEPHY_F_MII_SSR);
 			switch (ssr & RGEPHY_F_SSR_SPD_MASK) {
 			case RGEPHY_F_SSR_S1000:
 				mii->mii_media_active |= IFM_1000_T;
 				break;
 			case RGEPHY_F_SSR_S100:
 				mii->mii_media_active |= IFM_100_TX;
 				break;
 			case RGEPHY_F_SSR_S10:
 				mii->mii_media_active |= IFM_10_T;
 				break;
 			default:
 				mii->mii_media_active |= IFM_NONE;
 				break;
 			}
 			if (ssr & RGEPHY_F_SSR_FDX)
 				mii->mii_media_active |= IFM_FDX;
 			else
 				mii->mii_media_active |= IFM_HDX;
 
 		} else {
 			ssr = PHY_READ(sc, RGEPHY_MII_SSR);
 			switch (ssr & RGEPHY_SSR_SPD_MASK) {
 			case RGEPHY_SSR_S1000:
 				mii->mii_media_active |= IFM_1000_T;
 				break;
 			case RGEPHY_SSR_S100:
 				mii->mii_media_active |= IFM_100_TX;
 				break;
 			case RGEPHY_SSR_S10:
 				mii->mii_media_active |= IFM_10_T;
 				break;
 			default:
 				mii->mii_media_active |= IFM_NONE;
 				break;
 			}
 			if (ssr & RGEPHY_SSR_FDX)
 				mii->mii_media_active |= IFM_FDX;
 			else
 				mii->mii_media_active |= IFM_HDX;
 		}
 	} else {
 		bmsr = PHY_READ(sc, RL_GMEDIASTAT);
 		if (bmsr & RL_GMEDIASTAT_1000MBPS)
 			mii->mii_media_active |= IFM_1000_T;
 		else if (bmsr & RL_GMEDIASTAT_100MBPS)
 			mii->mii_media_active |= IFM_100_TX;
 		else if (bmsr & RL_GMEDIASTAT_10MBPS)
 			mii->mii_media_active |= IFM_10_T;
 		else
 			mii->mii_media_active |= IFM_NONE;
 		if (bmsr & RL_GMEDIASTAT_FDX)
 			mii->mii_media_active |= IFM_FDX;
 		else
 			mii->mii_media_active |= IFM_HDX;
 	}
 
 	if ((mii->mii_media_active & IFM_FDX) != 0)
 		mii->mii_media_active |= mii_phy_flowstatus(sc);
 
 	if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
 	    (PHY_READ(sc, RGEPHY_MII_1000STS) & RGEPHY_1000STS_MSR) != 0)
 		mii->mii_media_active |= IFM_ETH_MASTER;
 }
 
 static int
 rgephy_mii_phy_auto(struct mii_softc *sc, int media)
 {
 	int anar;
 
 	rgephy_loop(sc);
 	PHY_RESET(sc);
 
 	anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
 	if ((media & IFM_FLOW) != 0 || (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
 		anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP;
 	PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
 	DELAY(1000);
 	PHY_WRITE(sc, RGEPHY_MII_1000CTL,
 	    RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD);
 	DELAY(1000);
 	PHY_WRITE(sc, RGEPHY_MII_BMCR,
 	    RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
 	DELAY(100);
 
 	return (EJUSTRETURN);
 }
 
 static void
 rgephy_loop(struct mii_softc *sc)
 {
 	int i;
 
 	if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 &&
 	    sc->mii_mpd_rev < RGEPHY_8211B) {
 		PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
 		DELAY(1000);
 	}
 
 	for (i = 0; i < 15000; i++) {
 		if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) {
 #if 0
 			device_printf(sc->mii_dev, "looped %d\n", i);
 #endif
 			break;
 		}
 		DELAY(10);
 	}
 }
 
 #define PHY_SETBIT(x, y, z) \
 	PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
 #define PHY_CLRBIT(x, y, z) \
 	PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
 
 /*
  * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
  * existing revisions of the 8169S/8110S chips need to be tuned in
  * order to reliably negotiate a 1000Mbps link. This is only needed
  * for rev 0 and rev 1 of the PHY. Later versions work without
  * any fixups.
  */
 static void
 rgephy_load_dspcode(struct mii_softc *sc)
 {
 	int val;
 
 	if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8251 ||
 	    sc->mii_mpd_rev >= RGEPHY_8211B)
 		return;
 
 	PHY_WRITE(sc, 31, 0x0001);
 	PHY_WRITE(sc, 21, 0x1000);
 	PHY_WRITE(sc, 24, 0x65C7);
 	PHY_CLRBIT(sc, 4, 0x0800);
 	val = PHY_READ(sc, 4) & 0xFFF;
 	PHY_WRITE(sc, 4, val);
 	PHY_WRITE(sc, 3, 0x00A1);
 	PHY_WRITE(sc, 2, 0x0008);
 	PHY_WRITE(sc, 1, 0x1020);
 	PHY_WRITE(sc, 0, 0x1000);
 	PHY_SETBIT(sc, 4, 0x0800);
 	PHY_CLRBIT(sc, 4, 0x0800);
 	val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
 	PHY_WRITE(sc, 4, val);
 	PHY_WRITE(sc, 3, 0xFF41);
 	PHY_WRITE(sc, 2, 0xDE60);
 	PHY_WRITE(sc, 1, 0x0140);
 	PHY_WRITE(sc, 0, 0x0077);
 	val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
 	PHY_WRITE(sc, 4, val);
 	PHY_WRITE(sc, 3, 0xDF01);
 	PHY_WRITE(sc, 2, 0xDF20);
 	PHY_WRITE(sc, 1, 0xFF95);
 	PHY_WRITE(sc, 0, 0xFA00);
 	val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
 	PHY_WRITE(sc, 4, val);
 	PHY_WRITE(sc, 3, 0xFF41);
 	PHY_WRITE(sc, 2, 0xDE20);
 	PHY_WRITE(sc, 1, 0x0140);
 	PHY_WRITE(sc, 0, 0x00BB);
 	val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
 	PHY_WRITE(sc, 4, val);
 	PHY_WRITE(sc, 3, 0xDF01);
 	PHY_WRITE(sc, 2, 0xDF20);
 	PHY_WRITE(sc, 1, 0xFF95);
 	PHY_WRITE(sc, 0, 0xBF00);
 	PHY_SETBIT(sc, 4, 0x0800);
 	PHY_CLRBIT(sc, 4, 0x0800);
 	PHY_WRITE(sc, 31, 0x0000);
 
 	DELAY(40);
 }
 
 static void
 rgephy_reset(struct mii_softc *sc)
 {
 	uint16_t pcr, ssr;
 
 	switch (sc->mii_mpd_rev) {
 	case RGEPHY_8211F:
 		pcr = PHY_READ(sc, RGEPHY_F_MII_PCR1);
 		if ((pcr & RGEPHY_F_PCR1_MDI_MM) != 0) {
 			pcr &= ~RGEPHY_F_PCR1_MDI_MM;
 			PHY_WRITE(sc, RGEPHY_F_MII_PCR1, pcr);
 		}
 		break;
 	case RGEPHY_8211C:
 		if ((sc->mii_flags & MIIF_PHYPRIV0) == 0) {
 			/* RTL8211C(L) */
 			ssr = PHY_READ(sc, RGEPHY_MII_SSR);
 			if ((ssr & RGEPHY_SSR_ALDPS) != 0) {
 				ssr &= ~RGEPHY_SSR_ALDPS;
 				PHY_WRITE(sc, RGEPHY_MII_SSR, ssr);
 			}
 		}
 		/* FALLTHROUGH */
 	default:
 		if (sc->mii_mpd_rev >= RGEPHY_8211B) {
 			pcr = PHY_READ(sc, RGEPHY_MII_PCR);
 			if ((pcr & RGEPHY_PCR_MDIX_AUTO) == 0) {
 				pcr &= ~RGEPHY_PCR_MDI_MASK;
 				pcr |= RGEPHY_PCR_MDIX_AUTO;
 				PHY_WRITE(sc, RGEPHY_MII_PCR, pcr);
 			}
 		}
 		break;
 	}
 
 	mii_phy_reset(sc);
 	DELAY(1000);
 	rgephy_load_dspcode(sc);
 }
Index: stable/9/sys/dev/mii/rlphy.c
===================================================================
--- stable/9/sys/dev/mii/rlphy.c	(revision 292780)
+++ stable/9/sys/dev/mii/rlphy.c	(revision 292781)
@@ -1,272 +1,272 @@
 /*-
  * Copyright (c) 1997, 1998, 1999
  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Bill Paul.
  * 4. Neither the name of the author nor the names of any co-contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
 /*
  * driver for RealTek 8139 internal PHYs
  */
 
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/module.h>
 #include <sys/socket.h>
 #include <sys/bus.h>
 
 #include <net/if.h>
 #include <net/if_arp.h>
 #include <net/if_media.h>
 
 #include <dev/mii/mii.h>
 #include <dev/mii/miivar.h>
 #include "miidevs.h"
 
 #include <machine/bus.h>
-#include <pci/if_rlreg.h>
+#include <dev/rl/if_rlreg.h>
 
 #include "miibus_if.h"
 
 static int rlphy_probe(device_t);
 static int rlphy_attach(device_t);
 
 static device_method_t rlphy_methods[] = {
 	/* device interface */
 	DEVMETHOD(device_probe,		rlphy_probe),
 	DEVMETHOD(device_attach,	rlphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
 	DEVMETHOD_END
 };
 
 static devclass_t rlphy_devclass;
 
 static driver_t rlphy_driver = {
 	"rlphy",
 	rlphy_methods,
 	sizeof(struct mii_softc)
 };
 
 DRIVER_MODULE(rlphy, miibus, rlphy_driver, rlphy_devclass, 0, 0);
 
 static int	rlphy_service(struct mii_softc *, struct mii_data *, int);
 static void	rlphy_status(struct mii_softc *);
 
 /*
  * RealTek internal PHYs don't have vendor/device ID registers;
  * re(4) and rl(4) fake up a return value of all zeros.
  */
 static const struct mii_phydesc rlintphys[] = {
 	{ 0, 0, "RealTek internal media interface" },
 	MII_PHY_END
 };
 
 static const struct mii_phydesc rlphys[] = {
 	MII_PHY_DESC(yyREALTEK, RTL8201L),
 	MII_PHY_DESC(REALTEK, RTL8201E),
 	MII_PHY_DESC(xxICPLUS, IP101),
 	MII_PHY_END
 };
 
 static const struct mii_phy_funcs rlphy_funcs = {
 	rlphy_service,
 	rlphy_status,
 	mii_phy_reset
 };
 
 static int
 rlphy_probe(device_t dev)
 {
 	const char *nic;
 	int rv;
 
 	rv = mii_phy_dev_probe(dev, rlphys, BUS_PROBE_DEFAULT);
 	if (rv <= 0)
 		return (rv);
 
 	nic = device_get_name(device_get_parent(device_get_parent(dev)));
 	if (strcmp(nic, "rl") == 0 || strcmp(nic, "re") == 0)
 		return (mii_phy_dev_probe(dev, rlintphys, BUS_PROBE_DEFAULT));
 	return (ENXIO);
 }
 
 static int
 rlphy_attach(device_t dev)
 {
 
 	/*
 	 * The RealTek PHY can never be isolated.
 	 */
 	mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
 	    &rlphy_funcs, 1);
 	return (0);
 }
 
 static int
 rlphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
 {
 
 	switch (cmd) {
 	case MII_POLLSTAT:
 		break;
 
 	case MII_MEDIACHG:
 		/*
 		 * If the interface is not up, don't do anything.
 		 */
 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 			break;
 
 		mii_phy_setmedia(sc);
 		break;
 
 	case MII_TICK:
 		/*
 		 * Is the interface even up?
 		 */
 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 			return (0);
 
 		/*
 		 * The RealTek PHY's autonegotiation doesn't need to be
 		 * kicked; it continues in the background.
 		 */
 		break;
 	}
 
 	/* Update the media status. */
 	PHY_STATUS(sc);
 
 	/* Callback if something changed. */
 	mii_phy_update(sc, cmd);
 	return (0);
 }
 
 static void
 rlphy_status(struct mii_softc *phy)
 {
 	struct mii_data *mii = phy->mii_pdata;
 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
 	int bmsr, bmcr, anlpar;
 
 	mii->mii_media_status = IFM_AVALID;
 	mii->mii_media_active = IFM_ETHER;
 
 	bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR);
 	if (bmsr & BMSR_LINK)
 		mii->mii_media_status |= IFM_ACTIVE;
 
 	bmcr = PHY_READ(phy, MII_BMCR);
 	if (bmcr & BMCR_ISO) {
 		mii->mii_media_active |= IFM_NONE;
 		mii->mii_media_status = 0;
 		return;
 	}
 
 	if (bmcr & BMCR_LOOP)
 		mii->mii_media_active |= IFM_LOOP;
 
 	if (bmcr & BMCR_AUTOEN) {
 		/*
 		 * NWay autonegotiation takes the highest-order common
 		 * bit of the ANAR and ANLPAR (i.e. best media advertised
 		 * both by us and our link partner).
 		 */
 		if ((bmsr & BMSR_ACOMP) == 0) {
 			/* Erg, still trying, I guess... */
 			mii->mii_media_active |= IFM_NONE;
 			return;
 		}
 
 		if ((anlpar = PHY_READ(phy, MII_ANAR) &
 		    PHY_READ(phy, MII_ANLPAR))) {
 			if (anlpar & ANLPAR_TX_FD)
 				mii->mii_media_active |= IFM_100_TX|IFM_FDX;
 			else if (anlpar & ANLPAR_T4)
 				mii->mii_media_active |= IFM_100_T4|IFM_HDX;
 			else if (anlpar & ANLPAR_TX)
 				mii->mii_media_active |= IFM_100_TX|IFM_HDX;
 			else if (anlpar & ANLPAR_10_FD)
 				mii->mii_media_active |= IFM_10_T|IFM_FDX;
 			else if (anlpar & ANLPAR_10)
 				mii->mii_media_active |= IFM_10_T|IFM_HDX;
 			else
 				mii->mii_media_active |= IFM_NONE;
 			if ((mii->mii_media_active & IFM_FDX) != 0)
 				mii->mii_media_active |=
 				    mii_phy_flowstatus(phy);
 			return;
 		}
 		/*
 		 * If the other side doesn't support NWAY, then the
 		 * best we can do is determine if we have a 10Mbps or
 		 * 100Mbps link. There's no way to know if the link
 		 * is full or half duplex, so we default to half duplex
 		 * and hope that the user is clever enough to manually
 		 * change the media settings if we're wrong.
 		 */
 
 		/*
 		 * The RealTek PHY supports non-NWAY link speed
 		 * detection, however it does not report the link
 		 * detection results via the ANLPAR or BMSR registers.
 		 * (What? RealTek doesn't do things the way everyone
 		 * else does? I'm just shocked, shocked I tell you.)
 		 * To determine the link speed, we have to do one
 		 * of two things:
 		 *
 		 * - If this is a standalone RealTek RTL8201(L) or
 		 *   workalike PHY, we can determine the link speed by
 		 *   testing bit 0 in the magic, vendor-specific register
 		 *   at offset 0x19.
 		 *
 		 * - If this is a RealTek MAC with integrated PHY, we
 		 *   can test the 'SPEED10' bit of the MAC's media status
 		 *   register.
 		 */
 		if (!(phy->mii_mpd_model == 0 && phy->mii_mpd_rev == 0)) {
 			if (PHY_READ(phy, 0x0019) & 0x01)
 				mii->mii_media_active |= IFM_100_TX;
 			else
 				mii->mii_media_active |= IFM_10_T;
 		} else {
 			if (PHY_READ(phy, RL_MEDIASTAT) &
 			    RL_MEDIASTAT_SPEED10)
 				mii->mii_media_active |= IFM_10_T;
 			else
 				mii->mii_media_active |= IFM_100_TX;
 		}
 		mii->mii_media_active |= IFM_HDX;
 	} else
 		mii->mii_media_active = ife->ifm_media;
 }
Index: stable/9/sys/dev/mii/rlswitch.c
===================================================================
--- stable/9/sys/dev/mii/rlswitch.c	(revision 292780)
+++ stable/9/sys/dev/mii/rlswitch.c	(revision 292781)
@@ -1,401 +1,401 @@
 /*-
  * Copyright (c) 1997, 1998, 1999
  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
  * Copyright (c) 2006 Bernd Walter.  All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Bill Paul.
  * 4. Neither the name of the author nor the names of any co-contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
 /*
  * driver for RealTek 8305 pseudo PHYs
  */
 
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/module.h>
 #include <sys/socket.h>
 #include <sys/bus.h>
 
 #include <net/if.h>
 #include <net/if_arp.h>
 #include <net/if_media.h>
 
 #include <dev/mii/mii.h>
 #include <dev/mii/miivar.h>
 #include "miidevs.h"
 
 #include <machine/bus.h>
-#include <pci/if_rlreg.h>
+#include <dev/rl/if_rlreg.h>
 
 #include "miibus_if.h"
 
 //#define RL_DEBUG
 #define RL_VLAN
 
 static int rlswitch_probe(device_t);
 static int rlswitch_attach(device_t);
 
 static device_method_t rlswitch_methods[] = {
 	/* device interface */
 	DEVMETHOD(device_probe,		rlswitch_probe),
 	DEVMETHOD(device_attach,	rlswitch_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
 	DEVMETHOD_END
 };
 
 static devclass_t rlswitch_devclass;
 
 static driver_t rlswitch_driver = {
 	"rlswitch",
 	rlswitch_methods,
 	sizeof(struct mii_softc)
 };
 
 DRIVER_MODULE(rlswitch, miibus, rlswitch_driver, rlswitch_devclass, 0, 0);
 
 static int	rlswitch_service(struct mii_softc *, struct mii_data *, int);
 static void	rlswitch_status(struct mii_softc *);
 
 #ifdef RL_DEBUG
 static void	rlswitch_phydump(device_t dev);
 #endif
 
 static const struct mii_phydesc rlswitches[] = {
 	MII_PHY_DESC(REALTEK, RTL8305SC),
 	MII_PHY_END
 };
 
 static const struct mii_phy_funcs rlswitch_funcs = {
 	rlswitch_service,
 	rlswitch_status,
 	mii_phy_reset
 };
 
 static int
 rlswitch_probe(device_t dev)
 {
 	int rv;
 
 	rv = mii_phy_dev_probe(dev, rlswitches, BUS_PROBE_DEFAULT);
 	if (rv <= 0)
 		return (rv);
 
 	return (ENXIO);
 }
 
 static int
 rlswitch_attach(device_t dev)
 {
 	struct mii_softc	*sc;
 
 	sc = device_get_softc(dev);
 
 	/*
 	 * We handle all pseudo PHYs in a single instance.
 	 */
 	mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
 	    &rlswitch_funcs, 0);
 
 	sc->mii_capabilities = BMSR_100TXFDX & sc->mii_capmask;
 	device_printf(dev, " ");
 	mii_phy_add_media(sc);
 	printf("\n");
 #ifdef RL_DEBUG
 	rlswitch_phydump(dev);
 #endif
 	
 #ifdef RL_VLAN
 	int val;
 
 	/* Global Control 0 */
 	val = 0;
 	val |= 0 << 10;		/* enable 802.1q VLAN Tag support */
 	val |= 0 << 9;		/* enable VLAN ingress filtering */
 	val |= 1 << 8;		/* disable VLAN tag admit control */
 	val |= 1 << 6;		/* internal use */
 	val |= 1 << 5;		/* internal use */
 	val |= 1 << 4;		/* internal use */
 	val |= 1 << 3;		/* internal use */
 	val |= 1 << 1;		/* reserved */
 	MIIBUS_WRITEREG(sc->mii_dev, 0, 16, val);
 
 	/* Global Control 2 */
 	val = 0;
 	val |= 1 << 15;		/* reserved */
 	val |= 0 << 14;		/* enable 1552 Bytes support */
 	val |= 1 << 13;		/* enable broadcast input drop */
 	val |= 1 << 12;		/* forward reserved control frames */
 	val |= 1 << 11;		/* disable forwarding unicast frames to other VLAN's */
 	val |= 1 << 10;		/* disable forwarding ARP broadcasts to other VLAN's */
 	val |= 1 << 9;		/* enable 48 pass 1 */
 	val |= 0 << 8;		/* enable VLAN */
 	val |= 1 << 7;		/* reserved */
 	val |= 1 << 6;		/* enable defer */
 	val |= 1 << 5;		/* 43ms LED blink time */
 	val |= 3 << 3;		/* 16:1 queue weight */
 	val |= 1 << 2;		/* disable broadcast storm control */
 	val |= 1 << 1;		/* enable power-on LED blinking */
 	val |= 1 << 0;		/* reserved */
 	MIIBUS_WRITEREG(sc->mii_dev, 0, 18, val);
 
 	/* Port 0 Control Register 0 */
 	val = 0;
 	val |= 1 << 15;		/* reserved */
 	val |= 1 << 11;		/* drop received packets with wrong VLAN tag */
 	val |= 1 << 10;		/* disable 802.1p priority classification */
 	val |= 1 << 9;		/* disable diffserv priority classification */
 	val |= 1 << 6;		/* internal use */
 	val |= 3 << 4;		/* internal use */
 	val |= 1 << 3;		/* internal use */
 	val |= 1 << 2;		/* internal use */
 	val |= 1 << 0;		/* remove VLAN tags on output */
 	MIIBUS_WRITEREG(sc->mii_dev, 0, 22, val);
 
 	/* Port 1 Control Register 0 */
 	val = 0;
 	val |= 1 << 15;		/* reserved */
 	val |= 1 << 11;		/* drop received packets with wrong VLAN tag */
 	val |= 1 << 10;		/* disable 802.1p priority classification */
 	val |= 1 << 9;		/* disable diffserv priority classification */
 	val |= 1 << 6;		/* internal use */
 	val |= 3 << 4;		/* internal use */
 	val |= 1 << 3;		/* internal use */
 	val |= 1 << 2;		/* internal use */
 	val |= 1 << 0;		/* remove VLAN tags on output */
 	MIIBUS_WRITEREG(sc->mii_dev, 1, 22, val);
 
 	/* Port 2 Control Register 0 */
 	val = 0;
 	val |= 1 << 15;		/* reserved */
 	val |= 1 << 11;		/* drop received packets with wrong VLAN tag */
 	val |= 1 << 10;		/* disable 802.1p priority classification */
 	val |= 1 << 9;		/* disable diffserv priority classification */
 	val |= 1 << 6;		/* internal use */
 	val |= 3 << 4;		/* internal use */
 	val |= 1 << 3;		/* internal use */
 	val |= 1 << 2;		/* internal use */
 	val |= 1 << 0;		/* remove VLAN tags on output */
 	MIIBUS_WRITEREG(sc->mii_dev, 2, 22, val);
 
 	/* Port 3 Control Register 0 */
 	val = 0;
 	val |= 1 << 15;		/* reserved */
 	val |= 1 << 11;		/* drop received packets with wrong VLAN tag */
 	val |= 1 << 10;		/* disable 802.1p priority classification */
 	val |= 1 << 9;		/* disable diffserv priority classification */
 	val |= 1 << 6;		/* internal use */
 	val |= 3 << 4;		/* internal use */
 	val |= 1 << 3;		/* internal use */
 	val |= 1 << 2;		/* internal use */
 	val |= 1 << 0;		/* remove VLAN tags on output */
 	MIIBUS_WRITEREG(sc->mii_dev, 3, 22, val);
 
 	/* Port 4 (system port) Control Register 0 */
 	val = 0;
 	val |= 1 << 15;		/* reserved */
 	val |= 0 << 11;		/* don't drop received packets with wrong VLAN tag */
 	val |= 1 << 10;		/* disable 802.1p priority classification */
 	val |= 1 << 9;		/* disable diffserv priority classification */
 	val |= 1 << 6;		/* internal use */
 	val |= 3 << 4;		/* internal use */
 	val |= 1 << 3;		/* internal use */
 	val |= 1 << 2;		/* internal use */
 	val |= 2 << 0;		/* add VLAN tags for untagged packets on output */
 	MIIBUS_WRITEREG(sc->mii_dev, 4, 22, val);
 
 	/* Port 0 Control Register 1 and VLAN A */
 	val = 0;
 	val |= 0x0 << 12;	/* Port 0 VLAN Index */
 	val |= 1 << 11;		/* internal use */
 	val |= 1 << 10;		/* internal use */
 	val |= 1 << 9;		/* internal use */
 	val |= 1 << 7;		/* internal use */
 	val |= 1 << 6;		/* internal use */
 	val |= 0x11 << 0;	/* VLAN A membership */
 	MIIBUS_WRITEREG(sc->mii_dev, 0, 24, val);
 
 	/* Port 0 Control Register 2 and VLAN A */
 	val = 0;
 	val |= 1 << 15;		/* internal use */
 	val |= 1 << 14;		/* internal use */
 	val |= 1 << 13;		/* internal use */
 	val |= 1 << 12;		/* internal use */
 	val |= 0x100 << 0;	/* VLAN A ID */
 	MIIBUS_WRITEREG(sc->mii_dev, 0, 25, val);
 
 	/* Port 1 Control Register 1 and VLAN B */
 	val = 0;
 	val |= 0x1 << 12;	/* Port 1 VLAN Index */
 	val |= 1 << 11;		/* internal use */
 	val |= 1 << 10;		/* internal use */
 	val |= 1 << 9;		/* internal use */
 	val |= 1 << 7;		/* internal use */
 	val |= 1 << 6;		/* internal use */
 	val |= 0x12 << 0;	/* VLAN B membership */
 	MIIBUS_WRITEREG(sc->mii_dev, 1, 24, val);
 
 	/* Port 1 Control Register 2 and VLAN B */
 	val = 0;
 	val |= 1 << 15;		/* internal use */
 	val |= 1 << 14;		/* internal use */
 	val |= 1 << 13;		/* internal use */
 	val |= 1 << 12;		/* internal use */
 	val |= 0x101 << 0;	/* VLAN B ID */
 	MIIBUS_WRITEREG(sc->mii_dev, 1, 25, val);
 
 	/* Port 2 Control Register 1 and VLAN C */
 	val = 0;
 	val |= 0x2 << 12;	/* Port 2 VLAN Index */
 	val |= 1 << 11;		/* internal use */
 	val |= 1 << 10;		/* internal use */
 	val |= 1 << 9;		/* internal use */
 	val |= 1 << 7;		/* internal use */
 	val |= 1 << 6;		/* internal use */
 	val |= 0x14 << 0;	/* VLAN C membership */
 	MIIBUS_WRITEREG(sc->mii_dev, 2, 24, val);
 
 	/* Port 2 Control Register 2 and VLAN C */
 	val = 0;
 	val |= 1 << 15;		/* internal use */
 	val |= 1 << 14;		/* internal use */
 	val |= 1 << 13;		/* internal use */
 	val |= 1 << 12;		/* internal use */
 	val |= 0x102 << 0;	/* VLAN C ID */
 	MIIBUS_WRITEREG(sc->mii_dev, 2, 25, val);
 
 	/* Port 3 Control Register 1 and VLAN D */
 	val = 0;
 	val |= 0x3 << 12;	/* Port 3 VLAN Index */
 	val |= 1 << 11;		/* internal use */
 	val |= 1 << 10;		/* internal use */
 	val |= 1 << 9;		/* internal use */
 	val |= 1 << 7;		/* internal use */
 	val |= 1 << 6;		/* internal use */
 	val |= 0x18 << 0;	/* VLAN D membership */
 	MIIBUS_WRITEREG(sc->mii_dev, 3, 24, val);
 
 	/* Port 3 Control Register 2 and VLAN D */
 	val = 0;
 	val |= 1 << 15;		/* internal use */
 	val |= 1 << 14;		/* internal use */
 	val |= 1 << 13;		/* internal use */
 	val |= 1 << 12;		/* internal use */
 	val |= 0x103 << 0;	/* VLAN D ID */
 	MIIBUS_WRITEREG(sc->mii_dev, 3, 25, val);
 
 	/* Port 4 Control Register 1 and VLAN E */
 	val = 0;
 	val |= 0x0 << 12;	/* Port 4 VLAN Index */
 	val |= 1 << 11;		/* internal use */
 	val |= 1 << 10;		/* internal use */
 	val |= 1 << 9;		/* internal use */
 	val |= 1 << 7;		/* internal use */
 	val |= 1 << 6;		/* internal use */
 	val |= 0 << 0;		/* VLAN E membership */
 	MIIBUS_WRITEREG(sc->mii_dev, 4, 24, val);
 
 	/* Port 4 Control Register 2 and VLAN E */
 	val = 0;
 	val |= 1 << 15;		/* internal use */
 	val |= 1 << 14;		/* internal use */
 	val |= 1 << 13;		/* internal use */
 	val |= 1 << 12;		/* internal use */
 	val |= 0x104 << 0;	/* VLAN E ID */
 	MIIBUS_WRITEREG(sc->mii_dev, 4, 25, val);
 #endif
 
 #ifdef RL_DEBUG
 	rlswitch_phydump(dev);
 #endif
 	MIIBUS_MEDIAINIT(sc->mii_dev);
 	return (0);
 }
 
 static int
 rlswitch_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
 {
 
 	switch (cmd) {
 	case MII_POLLSTAT:
 		break;
 
 	case MII_MEDIACHG:
 		break;
 
 	case MII_TICK:
 		/*
 		 * Is the interface even up?
 		 */
 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 			return (0);
 		break;
 	}
 
 	/* Update the media status. */
 	PHY_STATUS(sc);
 
 	/* Callback if something changed. */
 	// mii_phy_update(sc, cmd);
 	return (0);
 }
 
 static void
 rlswitch_status(struct mii_softc *phy)
 {
 	struct mii_data *mii = phy->mii_pdata;
 
 	mii->mii_media_status = IFM_AVALID;
 	mii->mii_media_active = IFM_ETHER;
 	mii->mii_media_status |= IFM_ACTIVE;
 	mii->mii_media_active |=
 	    IFM_100_TX | IFM_FDX | mii_phy_flowstatus(phy);
 }
 
 #ifdef RL_DEBUG
 static void
 rlswitch_phydump(device_t dev) {
 	int phy, reg, val;
 	struct mii_softc *sc;
 
 	sc = device_get_softc(dev);
 	device_printf(dev, "rlswitchphydump\n");
 	for (phy = 0; phy <= 5; phy++) {
 		printf("PHY%i:", phy);
 		for (reg = 0; reg <= 31; reg++) {
 			val = MIIBUS_READREG(sc->mii_dev, phy, reg);
 			printf(" 0x%x", val);
 		}
 		printf("\n");
 	}
 }
 #endif
Index: stable/9/sys/dev/re/if_re.c
===================================================================
--- stable/9/sys/dev/re/if_re.c	(revision 292780)
+++ stable/9/sys/dev/re/if_re.c	(revision 292781)
@@ -1,4048 +1,4048 @@
 /*-
  * Copyright (c) 1997, 1998-2003
  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Bill Paul.
  * 4. Neither the name of the author nor the names of any co-contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
 /*
  * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
  *
  * Written by Bill Paul <wpaul@windriver.com>
  * Senior Networking Software Engineer
  * Wind River Systems
  */
 
 /*
  * This driver is designed to support RealTek's next generation of
  * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
  * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
  * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
  *
  * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
  * with the older 8139 family, however it also supports a special
  * C+ mode of operation that provides several new performance enhancing
  * features. These include:
  *
  *	o Descriptor based DMA mechanism. Each descriptor represents
  *	  a single packet fragment. Data buffers may be aligned on
  *	  any byte boundary.
  *
  *	o 64-bit DMA
  *
  *	o TCP/IP checksum offload for both RX and TX
  *
  *	o High and normal priority transmit DMA rings
  *
  *	o VLAN tag insertion and extraction
  *
  *	o TCP large send (segmentation offload)
  *
  * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
  * programming API is fairly straightforward. The RX filtering, EEPROM
  * access and PHY access is the same as it is on the older 8139 series
  * chips.
  *
  * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
  * same programming API and feature set as the 8139C+ with the following
  * differences and additions:
  *
  *	o 1000Mbps mode
  *
  *	o Jumbo frames
  *
  *	o GMII and TBI ports/registers for interfacing with copper
  *	  or fiber PHYs
  *
  *	o RX and TX DMA rings can have up to 1024 descriptors
  *	  (the 8139C+ allows a maximum of 64)
  *
  *	o Slight differences in register layout from the 8139C+
  *
  * The TX start and timer interrupt registers are at different locations
  * on the 8169 than they are on the 8139C+. Also, the status word in the
  * RX descriptor has a slightly different bit layout. The 8169 does not
  * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
  * copper gigE PHY.
  *
  * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
  * (the 'S' stands for 'single-chip'). These devices have the same
  * programming API as the older 8169, but also have some vendor-specific
  * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
  * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
  *
  * This driver takes advantage of the RX and TX checksum offload and
  * VLAN tag insertion/extraction features. It also implements TX
  * interrupt moderation using the timer interrupt registers, which
  * significantly reduces TX interrupt load. There is also support
  * for jumbo frames, however the 8169/8169S/8110S can not transmit
  * jumbo frames larger than 7440, so the max MTU possible with this
  * driver is 7422 bytes.
  */
 
 #ifdef HAVE_KERNEL_OPTION_HEADERS
 #include "opt_device_polling.h"
 #endif
 
 #include <sys/param.h>
 #include <sys/endian.h>
 #include <sys/systm.h>
 #include <sys/sockio.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/module.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <sys/lock.h>
 #include <sys/mutex.h>
 #include <sys/sysctl.h>
 #include <sys/taskqueue.h>
 
 #include <net/if.h>
 #include <net/if_arp.h>
 #include <net/ethernet.h>
 #include <net/if_dl.h>
 #include <net/if_media.h>
 #include <net/if_types.h>
 #include <net/if_vlan_var.h>
 
 #include <net/bpf.h>
 
 #include <machine/bus.h>
 #include <machine/resource.h>
 #include <sys/bus.h>
 #include <sys/rman.h>
 
 #include <dev/mii/mii.h>
 #include <dev/mii/miivar.h>
 
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 
-#include <pci/if_rlreg.h>
+#include <dev/rl/if_rlreg.h>
 
 MODULE_DEPEND(re, pci, 1, 1, 1);
 MODULE_DEPEND(re, ether, 1, 1, 1);
 MODULE_DEPEND(re, miibus, 1, 1, 1);
 
 /* "device miibus" required.  See GENERIC if you get errors here. */
 #include "miibus_if.h"
 
 /* Tunables. */
 static int intr_filter = 0;
 TUNABLE_INT("hw.re.intr_filter", &intr_filter);
 static int msi_disable = 0;
 TUNABLE_INT("hw.re.msi_disable", &msi_disable);
 static int msix_disable = 0;
 TUNABLE_INT("hw.re.msix_disable", &msix_disable);
 static int prefer_iomap = 0;
 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap);
 
 #define RE_CSUM_FEATURES    (CSUM_IP | CSUM_TCP | CSUM_UDP)
 
 /*
  * Various supported device vendors/types and their names.
  */
 static const struct rl_type re_devs[] = {
 	{ DLINK_VENDORID, DLINK_DEVICEID_528T, 0,
 	    "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
 	{ DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0,
 	    "D-Link DGE-530(T) Gigabit Ethernet Adapter" },
 	{ RT_VENDORID, RT_DEVICEID_8139, 0,
 	    "RealTek 8139C+ 10/100BaseTX" },
 	{ RT_VENDORID, RT_DEVICEID_8101E, 0,
 	    "RealTek 810xE PCIe 10/100baseTX" },
 	{ RT_VENDORID, RT_DEVICEID_8168, 0,
 	    "RealTek 8168/8111 B/C/CP/D/DP/E/F/G PCIe Gigabit Ethernet" },
 	{ RT_VENDORID, RT_DEVICEID_8169, 0,
 	    "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" },
 	{ RT_VENDORID, RT_DEVICEID_8169SC, 0,
 	    "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
 	{ COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0,
 	    "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
 	{ LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0,
 	    "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
 	{ USR_VENDORID, USR_DEVICEID_997902, 0,
 	    "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }
 };
 
 static const struct rl_hwrev re_hwrevs[] = {
 	{ RL_HWREV_8139, RL_8139, "", RL_MTU },
 	{ RL_HWREV_8139A, RL_8139, "A", RL_MTU },
 	{ RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU },
 	{ RL_HWREV_8139B, RL_8139, "B", RL_MTU },
 	{ RL_HWREV_8130, RL_8139, "8130", RL_MTU },
 	{ RL_HWREV_8139C, RL_8139, "C", RL_MTU },
 	{ RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU },
 	{ RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU },
 	{ RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU },
 	{ RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU },
 	{ RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU },
 	{ RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU },
 	{ RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU },
 	{ RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU },
 	{ RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU },
 	{ RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU },
 	{ RL_HWREV_8100, RL_8139, "8100", RL_MTU },
 	{ RL_HWREV_8101, RL_8139, "8101", RL_MTU },
 	{ RL_HWREV_8100E, RL_8169, "8100E", RL_MTU },
 	{ RL_HWREV_8101E, RL_8169, "8101E", RL_MTU },
 	{ RL_HWREV_8102E, RL_8169, "8102E", RL_MTU },
 	{ RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU },
 	{ RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU },
 	{ RL_HWREV_8103E, RL_8169, "8103E", RL_MTU },
 	{ RL_HWREV_8401E, RL_8169, "8401E", RL_MTU },
 	{ RL_HWREV_8402, RL_8169, "8402", RL_MTU },
 	{ RL_HWREV_8105E, RL_8169, "8105E", RL_MTU },
 	{ RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU },
 	{ RL_HWREV_8106E, RL_8169, "8106E", RL_MTU },
 	{ RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU },
 	{ RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU },
 	{ RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
 	{ RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
 	{ RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K },
 	{ RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K },
 	{ RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K },
 	{ RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K},
 	{ RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K},
 	{ RL_HWREV_8168EP, RL_8169, "8168EP/8111EP", RL_JUMBO_MTU_9K},
 	{ RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K},
 	{ RL_HWREV_8168G, RL_8169, "8168G/8111G", RL_JUMBO_MTU_9K},
 	{ RL_HWREV_8168GU, RL_8169, "8168GU/8111GU", RL_JUMBO_MTU_9K},
 	{ RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K},
 	{ RL_HWREV_8411B, RL_8169, "8411B", RL_JUMBO_MTU_9K},
 	{ 0, 0, NULL, 0 }
 };
 
 static int re_probe		(device_t);
 static int re_attach		(device_t);
 static int re_detach		(device_t);
 
 static int re_encap		(struct rl_softc *, struct mbuf **);
 
 static void re_dma_map_addr	(void *, bus_dma_segment_t *, int, int);
 static int re_allocmem		(device_t, struct rl_softc *);
 static __inline void re_discard_rxbuf
 				(struct rl_softc *, int);
 static int re_newbuf		(struct rl_softc *, int);
 static int re_jumbo_newbuf	(struct rl_softc *, int);
 static int re_rx_list_init	(struct rl_softc *);
 static int re_jrx_list_init	(struct rl_softc *);
 static int re_tx_list_init	(struct rl_softc *);
 #ifdef RE_FIXUP_RX
 static __inline void re_fixup_rx
 				(struct mbuf *);
 #endif
 static int re_rxeof		(struct rl_softc *, int *);
 static void re_txeof		(struct rl_softc *);
 #ifdef DEVICE_POLLING
 static int re_poll		(struct ifnet *, enum poll_cmd, int);
 static int re_poll_locked	(struct ifnet *, enum poll_cmd, int);
 #endif
 static int re_intr		(void *);
 static void re_intr_msi		(void *);
 static void re_tick		(void *);
 static void re_int_task		(void *, int);
 static void re_start		(struct ifnet *);
 static void re_start_locked	(struct ifnet *);
 static int re_ioctl		(struct ifnet *, u_long, caddr_t);
 static void re_init		(void *);
 static void re_init_locked	(struct rl_softc *);
 static void re_stop		(struct rl_softc *);
 static void re_watchdog		(struct rl_softc *);
 static int re_suspend		(device_t);
 static int re_resume		(device_t);
 static int re_shutdown		(device_t);
 static int re_ifmedia_upd	(struct ifnet *);
 static void re_ifmedia_sts	(struct ifnet *, struct ifmediareq *);
 
 static void re_eeprom_putbyte	(struct rl_softc *, int);
 static void re_eeprom_getword	(struct rl_softc *, int, u_int16_t *);
 static void re_read_eeprom	(struct rl_softc *, caddr_t, int, int);
 static int re_gmii_readreg	(device_t, int, int);
 static int re_gmii_writereg	(device_t, int, int, int);
 
 static int re_miibus_readreg	(device_t, int, int);
 static int re_miibus_writereg	(device_t, int, int, int);
 static void re_miibus_statchg	(device_t);
 
 static void re_set_jumbo	(struct rl_softc *, int);
 static void re_set_rxmode		(struct rl_softc *);
 static void re_reset		(struct rl_softc *);
 static void re_setwol		(struct rl_softc *);
 static void re_clrwol		(struct rl_softc *);
 static void re_set_linkspeed	(struct rl_softc *);
 
 #ifdef DEV_NETMAP	/* see ixgbe.c for details */
 #include <dev/netmap/if_re_netmap.h>
 #endif /* !DEV_NETMAP */
 
 #ifdef RE_DIAG
 static int re_diag		(struct rl_softc *);
 #endif
 
 static void re_add_sysctls	(struct rl_softc *);
 static int re_sysctl_stats	(SYSCTL_HANDLER_ARGS);
 static int sysctl_int_range	(SYSCTL_HANDLER_ARGS, int, int);
 static int sysctl_hw_re_int_mod	(SYSCTL_HANDLER_ARGS);
 
 static device_method_t re_methods[] = {
 	/* Device interface */
 	DEVMETHOD(device_probe,		re_probe),
 	DEVMETHOD(device_attach,	re_attach),
 	DEVMETHOD(device_detach,	re_detach),
 	DEVMETHOD(device_suspend,	re_suspend),
 	DEVMETHOD(device_resume,	re_resume),
 	DEVMETHOD(device_shutdown,	re_shutdown),
 
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	re_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	re_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	re_miibus_statchg),
 
 	DEVMETHOD_END
 };
 
 static driver_t re_driver = {
 	"re",
 	re_methods,
 	sizeof(struct rl_softc)
 };
 
 static devclass_t re_devclass;
 
 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
 
 #define EE_SET(x)					\
 	CSR_WRITE_1(sc, RL_EECMD,			\
 		CSR_READ_1(sc, RL_EECMD) | x)
 
 #define EE_CLR(x)					\
 	CSR_WRITE_1(sc, RL_EECMD,			\
 		CSR_READ_1(sc, RL_EECMD) & ~x)
 
 /*
  * Send a read command and address to the EEPROM, check for ACK.
  */
 static void
 re_eeprom_putbyte(struct rl_softc *sc, int addr)
 {
 	int			d, i;
 
 	d = addr | (RL_9346_READ << sc->rl_eewidth);
 
 	/*
 	 * Feed in each bit and strobe the clock.
 	 */
 
 	for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) {
 		if (d & i) {
 			EE_SET(RL_EE_DATAIN);
 		} else {
 			EE_CLR(RL_EE_DATAIN);
 		}
 		DELAY(100);
 		EE_SET(RL_EE_CLK);
 		DELAY(150);
 		EE_CLR(RL_EE_CLK);
 		DELAY(100);
 	}
 }
 
 /*
  * Read a word of data stored in the EEPROM at address 'addr.'
  */
 static void
 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest)
 {
 	int			i;
 	u_int16_t		word = 0;
 
 	/*
 	 * Send address of word we want to read.
 	 */
 	re_eeprom_putbyte(sc, addr);
 
 	/*
 	 * Start reading bits from EEPROM.
 	 */
 	for (i = 0x8000; i; i >>= 1) {
 		EE_SET(RL_EE_CLK);
 		DELAY(100);
 		if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
 			word |= i;
 		EE_CLR(RL_EE_CLK);
 		DELAY(100);
 	}
 
 	*dest = word;
 }
 
 /*
  * Read a sequence of words from the EEPROM.
  */
 static void
 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt)
 {
 	int			i;
 	u_int16_t		word = 0, *ptr;
 
 	CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
 
         DELAY(100);
 
 	for (i = 0; i < cnt; i++) {
 		CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL);
 		re_eeprom_getword(sc, off + i, &word);
 		CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL);
 		ptr = (u_int16_t *)(dest + (i * 2));
                 *ptr = word;
 	}
 
 	CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
 }
 
 static int
 re_gmii_readreg(device_t dev, int phy, int reg)
 {
 	struct rl_softc		*sc;
 	u_int32_t		rval;
 	int			i;
 
 	sc = device_get_softc(dev);
 
 	/* Let the rgephy driver read the GMEDIASTAT register */
 
 	if (reg == RL_GMEDIASTAT) {
 		rval = CSR_READ_1(sc, RL_GMEDIASTAT);
 		return (rval);
 	}
 
 	CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
 
 	for (i = 0; i < RL_PHY_TIMEOUT; i++) {
 		rval = CSR_READ_4(sc, RL_PHYAR);
 		if (rval & RL_PHYAR_BUSY)
 			break;
 		DELAY(25);
 	}
 
 	if (i == RL_PHY_TIMEOUT) {
 		device_printf(sc->rl_dev, "PHY read failed\n");
 		return (0);
 	}
 
 	/*
 	 * Controller requires a 20us delay to process next MDIO request.
 	 */
 	DELAY(20);
 
 	return (rval & RL_PHYAR_PHYDATA);
 }
 
 static int
 re_gmii_writereg(device_t dev, int phy, int reg, int data)
 {
 	struct rl_softc		*sc;
 	u_int32_t		rval;
 	int			i;
 
 	sc = device_get_softc(dev);
 
 	CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
 	    (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
 
 	for (i = 0; i < RL_PHY_TIMEOUT; i++) {
 		rval = CSR_READ_4(sc, RL_PHYAR);
 		if (!(rval & RL_PHYAR_BUSY))
 			break;
 		DELAY(25);
 	}
 
 	if (i == RL_PHY_TIMEOUT) {
 		device_printf(sc->rl_dev, "PHY write failed\n");
 		return (0);
 	}
 
 	/*
 	 * Controller requires a 20us delay to process next MDIO request.
 	 */
 	DELAY(20);
 
 	return (0);
 }
 
 static int
 re_miibus_readreg(device_t dev, int phy, int reg)
 {
 	struct rl_softc		*sc;
 	u_int16_t		rval = 0;
 	u_int16_t		re8139_reg = 0;
 
 	sc = device_get_softc(dev);
 
 	if (sc->rl_type == RL_8169) {
 		rval = re_gmii_readreg(dev, phy, reg);
 		return (rval);
 	}
 
 	switch (reg) {
 	case MII_BMCR:
 		re8139_reg = RL_BMCR;
 		break;
 	case MII_BMSR:
 		re8139_reg = RL_BMSR;
 		break;
 	case MII_ANAR:
 		re8139_reg = RL_ANAR;
 		break;
 	case MII_ANER:
 		re8139_reg = RL_ANER;
 		break;
 	case MII_ANLPAR:
 		re8139_reg = RL_LPAR;
 		break;
 	case MII_PHYIDR1:
 	case MII_PHYIDR2:
 		return (0);
 	/*
 	 * Allow the rlphy driver to read the media status
 	 * register. If we have a link partner which does not
 	 * support NWAY, this is the register which will tell
 	 * us the results of parallel detection.
 	 */
 	case RL_MEDIASTAT:
 		rval = CSR_READ_1(sc, RL_MEDIASTAT);
 		return (rval);
 	default:
 		device_printf(sc->rl_dev, "bad phy register\n");
 		return (0);
 	}
 	rval = CSR_READ_2(sc, re8139_reg);
 	if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) {
 		/* 8139C+ has different bit layout. */
 		rval &= ~(BMCR_LOOP | BMCR_ISO);
 	}
 	return (rval);
 }
 
 static int
 re_miibus_writereg(device_t dev, int phy, int reg, int data)
 {
 	struct rl_softc		*sc;
 	u_int16_t		re8139_reg = 0;
 	int			rval = 0;
 
 	sc = device_get_softc(dev);
 
 	if (sc->rl_type == RL_8169) {
 		rval = re_gmii_writereg(dev, phy, reg, data);
 		return (rval);
 	}
 
 	switch (reg) {
 	case MII_BMCR:
 		re8139_reg = RL_BMCR;
 		if (sc->rl_type == RL_8139CPLUS) {
 			/* 8139C+ has different bit layout. */
 			data &= ~(BMCR_LOOP | BMCR_ISO);
 		}
 		break;
 	case MII_BMSR:
 		re8139_reg = RL_BMSR;
 		break;
 	case MII_ANAR:
 		re8139_reg = RL_ANAR;
 		break;
 	case MII_ANER:
 		re8139_reg = RL_ANER;
 		break;
 	case MII_ANLPAR:
 		re8139_reg = RL_LPAR;
 		break;
 	case MII_PHYIDR1:
 	case MII_PHYIDR2:
 		return (0);
 		break;
 	default:
 		device_printf(sc->rl_dev, "bad phy register\n");
 		return (0);
 	}
 	CSR_WRITE_2(sc, re8139_reg, data);
 	return (0);
 }
 
 static void
 re_miibus_statchg(device_t dev)
 {
 	struct rl_softc		*sc;
 	struct ifnet		*ifp;
 	struct mii_data		*mii;
 
 	sc = device_get_softc(dev);
 	mii = device_get_softc(sc->rl_miibus);
 	ifp = sc->rl_ifp;
 	if (mii == NULL || ifp == NULL ||
 	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
 		return;
 
 	sc->rl_flags &= ~RL_FLAG_LINK;
 	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 	    (IFM_ACTIVE | IFM_AVALID)) {
 		switch (IFM_SUBTYPE(mii->mii_media_active)) {
 		case IFM_10_T:
 		case IFM_100_TX:
 			sc->rl_flags |= RL_FLAG_LINK;
 			break;
 		case IFM_1000_T:
 			if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0)
 				break;
 			sc->rl_flags |= RL_FLAG_LINK;
 			break;
 		default:
 			break;
 		}
 	}
 	/*
 	 * RealTek controllers does not provide any interface to
 	 * Tx/Rx MACs for resolved speed, duplex and flow-control
 	 * parameters.
 	 */
 }
 
 /*
  * Set the RX configuration and 64-bit multicast hash filter.
  */
 static void
 re_set_rxmode(struct rl_softc *sc)
 {
 	struct ifnet		*ifp;
 	struct ifmultiaddr	*ifma;
 	uint32_t		hashes[2] = { 0, 0 };
 	uint32_t		h, rxfilt;
 
 	RL_LOCK_ASSERT(sc);
 
 	ifp = sc->rl_ifp;
 
 	rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD;
 	if ((sc->rl_flags & RL_FLAG_EARLYOFF) != 0)
 		rxfilt |= RL_RXCFG_EARLYOFF;
 	else if ((sc->rl_flags & RL_FLAG_EARLYOFFV2) != 0)
 		rxfilt |= RL_RXCFG_EARLYOFFV2;
 
 	if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
 		if (ifp->if_flags & IFF_PROMISC)
 			rxfilt |= RL_RXCFG_RX_ALLPHYS;
 		/*
 		 * Unlike other hardwares, we have to explicitly set
 		 * RL_RXCFG_RX_MULTI to receive multicast frames in
 		 * promiscuous mode.
 		 */
 		rxfilt |= RL_RXCFG_RX_MULTI;
 		hashes[0] = hashes[1] = 0xffffffff;
 		goto done;
 	}
 
 	if_maddr_rlock(ifp);
 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 		if (ifma->ifma_addr->sa_family != AF_LINK)
 			continue;
 		h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
 		    ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
 		if (h < 32)
 			hashes[0] |= (1 << h);
 		else
 			hashes[1] |= (1 << (h - 32));
 	}
 	if_maddr_runlock(ifp);
 
 	if (hashes[0] != 0 || hashes[1] != 0) {
 		/*
 		 * For some unfathomable reason, RealTek decided to
 		 * reverse the order of the multicast hash registers
 		 * in the PCI Express parts.  This means we have to
 		 * write the hash pattern in reverse order for those
 		 * devices.
 		 */
 		if ((sc->rl_flags & RL_FLAG_PCIE) != 0) {
 			h = bswap32(hashes[0]);
 			hashes[0] = bswap32(hashes[1]);
 			hashes[1] = h;
 		}
 		rxfilt |= RL_RXCFG_RX_MULTI;
 	}
 
 	if  (sc->rl_hwrev->rl_rev == RL_HWREV_8168F) {
 		/* Disable multicast filtering due to silicon bug. */
 		hashes[0] = 0xffffffff;
 		hashes[1] = 0xffffffff;
 	}
 
 done:
 	CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
 	CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
 	CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
 }
 
 static void
 re_reset(struct rl_softc *sc)
 {
 	int			i;
 
 	RL_LOCK_ASSERT(sc);
 
 	CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
 
 	for (i = 0; i < RL_TIMEOUT; i++) {
 		DELAY(10);
 		if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
 			break;
 	}
 	if (i == RL_TIMEOUT)
 		device_printf(sc->rl_dev, "reset never completed!\n");
 
 	if ((sc->rl_flags & RL_FLAG_MACRESET) != 0)
 		CSR_WRITE_1(sc, 0x82, 1);
 	if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S)
 		re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0);
 }
 
 #ifdef RE_DIAG
 
 /*
  * The following routine is designed to test for a defect on some
  * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
  * lines connected to the bus, however for a 32-bit only card, they
  * should be pulled high. The result of this defect is that the
  * NIC will not work right if you plug it into a 64-bit slot: DMA
  * operations will be done with 64-bit transfers, which will fail
  * because the 64-bit data lines aren't connected.
  *
  * There's no way to work around this (short of talking a soldering
  * iron to the board), however we can detect it. The method we use
  * here is to put the NIC into digital loopback mode, set the receiver
  * to promiscuous mode, and then try to send a frame. We then compare
  * the frame data we sent to what was received. If the data matches,
  * then the NIC is working correctly, otherwise we know the user has
  * a defective NIC which has been mistakenly plugged into a 64-bit PCI
  * slot. In the latter case, there's no way the NIC can work correctly,
  * so we print out a message on the console and abort the device attach.
  */
 
 static int
 re_diag(struct rl_softc *sc)
 {
 	struct ifnet		*ifp = sc->rl_ifp;
 	struct mbuf		*m0;
 	struct ether_header	*eh;
 	struct rl_desc		*cur_rx;
 	u_int16_t		status;
 	u_int32_t		rxstat;
 	int			total_len, i, error = 0, phyaddr;
 	u_int8_t		dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
 	u_int8_t		src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
 
 	/* Allocate a single mbuf */
 	MGETHDR(m0, M_NOWAIT, MT_DATA);
 	if (m0 == NULL)
 		return (ENOBUFS);
 
 	RL_LOCK(sc);
 
 	/*
 	 * Initialize the NIC in test mode. This sets the chip up
 	 * so that it can send and receive frames, but performs the
 	 * following special functions:
 	 * - Puts receiver in promiscuous mode
 	 * - Enables digital loopback mode
 	 * - Leaves interrupts turned off
 	 */
 
 	ifp->if_flags |= IFF_PROMISC;
 	sc->rl_testmode = 1;
 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 	re_init_locked(sc);
 	sc->rl_flags |= RL_FLAG_LINK;
 	if (sc->rl_type == RL_8169)
 		phyaddr = 1;
 	else
 		phyaddr = 0;
 
 	re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET);
 	for (i = 0; i < RL_TIMEOUT; i++) {
 		status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR);
 		if (!(status & BMCR_RESET))
 			break;
 	}
 
 	re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP);
 	CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
 
 	DELAY(100000);
 
 	/* Put some data in the mbuf */
 
 	eh = mtod(m0, struct ether_header *);
 	bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
 	bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
 	eh->ether_type = htons(ETHERTYPE_IP);
 	m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
 
 	/*
 	 * Queue the packet, start transmission.
 	 * Note: IF_HANDOFF() ultimately calls re_start() for us.
 	 */
 
 	CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
 	RL_UNLOCK(sc);
 	/* XXX: re_diag must not be called when in ALTQ mode */
 	IF_HANDOFF(&ifp->if_snd, m0, ifp);
 	RL_LOCK(sc);
 	m0 = NULL;
 
 	/* Wait for it to propagate through the chip */
 
 	DELAY(100000);
 	for (i = 0; i < RL_TIMEOUT; i++) {
 		status = CSR_READ_2(sc, RL_ISR);
 		CSR_WRITE_2(sc, RL_ISR, status);
 		if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
 		    (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
 			break;
 		DELAY(10);
 	}
 
 	if (i == RL_TIMEOUT) {
 		device_printf(sc->rl_dev,
 		    "diagnostic failed, failed to receive packet in"
 		    " loopback mode\n");
 		error = EIO;
 		goto done;
 	}
 
 	/*
 	 * The packet should have been dumped into the first
 	 * entry in the RX DMA ring. Grab it from there.
 	 */
 
 	bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
 	    sc->rl_ldata.rl_rx_list_map,
 	    BUS_DMASYNC_POSTREAD);
 	bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
 	    sc->rl_ldata.rl_rx_desc[0].rx_dmamap,
 	    BUS_DMASYNC_POSTREAD);
 	bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
 	    sc->rl_ldata.rl_rx_desc[0].rx_dmamap);
 
 	m0 = sc->rl_ldata.rl_rx_desc[0].rx_m;
 	sc->rl_ldata.rl_rx_desc[0].rx_m = NULL;
 	eh = mtod(m0, struct ether_header *);
 
 	cur_rx = &sc->rl_ldata.rl_rx_list[0];
 	total_len = RL_RXBYTES(cur_rx);
 	rxstat = le32toh(cur_rx->rl_cmdstat);
 
 	if (total_len != ETHER_MIN_LEN) {
 		device_printf(sc->rl_dev,
 		    "diagnostic failed, received short packet\n");
 		error = EIO;
 		goto done;
 	}
 
 	/* Test that the received packet data matches what we sent. */
 
 	if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
 	    bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
 	    ntohs(eh->ether_type) != ETHERTYPE_IP) {
 		device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n");
 		device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n",
 		    dst, ":", src, ":", ETHERTYPE_IP);
 		device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n",
 		    eh->ether_dhost, ":", eh->ether_shost, ":",
 		    ntohs(eh->ether_type));
 		device_printf(sc->rl_dev, "You may have a defective 32-bit "
 		    "NIC plugged into a 64-bit PCI slot.\n");
 		device_printf(sc->rl_dev, "Please re-install the NIC in a "
 		    "32-bit slot for proper operation.\n");
 		device_printf(sc->rl_dev, "Read the re(4) man page for more "
 		    "details.\n");
 		error = EIO;
 	}
 
 done:
 	/* Turn interface off, release resources */
 
 	sc->rl_testmode = 0;
 	sc->rl_flags &= ~RL_FLAG_LINK;
 	ifp->if_flags &= ~IFF_PROMISC;
 	re_stop(sc);
 	if (m0 != NULL)
 		m_freem(m0);
 
 	RL_UNLOCK(sc);
 
 	return (error);
 }
 
 #endif
 
 /*
  * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
  * IDs against our list and return a device name if we find a match.
  */
 static int
 re_probe(device_t dev)
 {
 	const struct rl_type	*t;
 	uint16_t		devid, vendor;
 	uint16_t		revid, sdevid;
 	int			i;
 
 	vendor = pci_get_vendor(dev);
 	devid = pci_get_device(dev);
 	revid = pci_get_revid(dev);
 	sdevid = pci_get_subdevice(dev);
 
 	if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) {
 		if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) {
 			/*
 			 * Only attach to rev. 3 of the Linksys EG1032 adapter.
 			 * Rev. 2 is supported by sk(4).
 			 */
 			return (ENXIO);
 		}
 	}
 
 	if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
 		if (revid != 0x20) {
 			/* 8139, let rl(4) take care of this device. */
 			return (ENXIO);
 		}
 	}
 
 	t = re_devs;
 	for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) {
 		if (vendor == t->rl_vid && devid == t->rl_did) {
 			device_set_desc(dev, t->rl_name);
 			return (BUS_PROBE_DEFAULT);
 		}
 	}
 
 	return (ENXIO);
 }
 
 /*
  * Map a single buffer address.
  */
 
 static void
 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 {
 	bus_addr_t		*addr;
 
 	if (error)
 		return;
 
 	KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
 	addr = arg;
 	*addr = segs->ds_addr;
 }
 
 static int
 re_allocmem(device_t dev, struct rl_softc *sc)
 {
 	bus_addr_t		lowaddr;
 	bus_size_t		rx_list_size, tx_list_size;
 	int			error;
 	int			i;
 
 	rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc);
 	tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc);
 
 	/*
 	 * Allocate the parent bus DMA tag appropriate for PCI.
 	 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD
 	 * register should be set. However some RealTek chips are known
 	 * to be buggy on DAC handling, therefore disable DAC by limiting
 	 * DMA address space to 32bit. PCIe variants of RealTek chips
 	 * may not have the limitation.
 	 */
 	lowaddr = BUS_SPACE_MAXADDR;
 	if ((sc->rl_flags & RL_FLAG_PCIE) == 0)
 		lowaddr = BUS_SPACE_MAXADDR_32BIT;
 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
 	    lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
 	    BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
 	    NULL, NULL, &sc->rl_parent_tag);
 	if (error) {
 		device_printf(dev, "could not allocate parent DMA tag\n");
 		return (error);
 	}
 
 	/*
 	 * Allocate map for TX mbufs.
 	 */
 	error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0,
 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
 	    NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0,
 	    NULL, NULL, &sc->rl_ldata.rl_tx_mtag);
 	if (error) {
 		device_printf(dev, "could not allocate TX DMA tag\n");
 		return (error);
 	}
 
 	/*
 	 * Allocate map for RX mbufs.
 	 */
 
 	if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
 		error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t),
 		    0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
 		    MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL,
 		    &sc->rl_ldata.rl_jrx_mtag);
 		if (error) {
 			device_printf(dev,
 			    "could not allocate jumbo RX DMA tag\n");
 			return (error);
 		}
 	}
 	error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0,
 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
 	    MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag);
 	if (error) {
 		device_printf(dev, "could not allocate RX DMA tag\n");
 		return (error);
 	}
 
 	/*
 	 * Allocate map for TX descriptor list.
 	 */
 	error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
 	    0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
 	    NULL, tx_list_size, 1, tx_list_size, 0,
 	    NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
 	if (error) {
 		device_printf(dev, "could not allocate TX DMA ring tag\n");
 		return (error);
 	}
 
 	/* Allocate DMA'able memory for the TX ring */
 
 	error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
 	    (void **)&sc->rl_ldata.rl_tx_list,
 	    BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
 	    &sc->rl_ldata.rl_tx_list_map);
 	if (error) {
 		device_printf(dev, "could not allocate TX DMA ring\n");
 		return (error);
 	}
 
 	/* Load the map for the TX ring. */
 
 	sc->rl_ldata.rl_tx_list_addr = 0;
 	error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
 	     sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
 	     tx_list_size, re_dma_map_addr,
 	     &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
 	if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) {
 		device_printf(dev, "could not load TX DMA ring\n");
 		return (ENOMEM);
 	}
 
 	/* Create DMA maps for TX buffers */
 
 	for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
 		error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0,
 		    &sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
 		if (error) {
 			device_printf(dev, "could not create DMA map for TX\n");
 			return (error);
 		}
 	}
 
 	/*
 	 * Allocate map for RX descriptor list.
 	 */
 	error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
 	    0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
 	    NULL, rx_list_size, 1, rx_list_size, 0,
 	    NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
 	if (error) {
 		device_printf(dev, "could not create RX DMA ring tag\n");
 		return (error);
 	}
 
 	/* Allocate DMA'able memory for the RX ring */
 
 	error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
 	    (void **)&sc->rl_ldata.rl_rx_list,
 	    BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
 	    &sc->rl_ldata.rl_rx_list_map);
 	if (error) {
 		device_printf(dev, "could not allocate RX DMA ring\n");
 		return (error);
 	}
 
 	/* Load the map for the RX ring. */
 
 	sc->rl_ldata.rl_rx_list_addr = 0;
 	error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
 	     sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
 	     rx_list_size, re_dma_map_addr,
 	     &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
 	if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) {
 		device_printf(dev, "could not load RX DMA ring\n");
 		return (ENOMEM);
 	}
 
 	/* Create DMA maps for RX buffers */
 
 	if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
 		error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
 		    &sc->rl_ldata.rl_jrx_sparemap);
 		if (error) {
 			device_printf(dev,
 			    "could not create spare DMA map for jumbo RX\n");
 			return (error);
 		}
 		for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
 			error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
 			    &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
 			if (error) {
 				device_printf(dev,
 				    "could not create DMA map for jumbo RX\n");
 				return (error);
 			}
 		}
 	}
 	error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
 	    &sc->rl_ldata.rl_rx_sparemap);
 	if (error) {
 		device_printf(dev, "could not create spare DMA map for RX\n");
 		return (error);
 	}
 	for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
 		error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
 		    &sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
 		if (error) {
 			device_printf(dev, "could not create DMA map for RX\n");
 			return (error);
 		}
 	}
 
 	/* Create DMA map for statistics. */
 	error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0,
 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
 	    sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL,
 	    &sc->rl_ldata.rl_stag);
 	if (error) {
 		device_printf(dev, "could not create statistics DMA tag\n");
 		return (error);
 	}
 	/* Allocate DMA'able memory for statistics. */
 	error = bus_dmamem_alloc(sc->rl_ldata.rl_stag,
 	    (void **)&sc->rl_ldata.rl_stats,
 	    BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
 	    &sc->rl_ldata.rl_smap);
 	if (error) {
 		device_printf(dev,
 		    "could not allocate statistics DMA memory\n");
 		return (error);
 	}
 	/* Load the map for statistics. */
 	sc->rl_ldata.rl_stats_addr = 0;
 	error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap,
 	    sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr,
 	     &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT);
 	if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) {
 		device_printf(dev, "could not load statistics DMA memory\n");
 		return (ENOMEM);
 	}
 
 	return (0);
 }
 
 /*
  * Attach the interface. Allocate softc structures, do ifmedia
  * setup and ethernet/BPF attach.
  */
 static int
 re_attach(device_t dev)
 {
 	u_char			eaddr[ETHER_ADDR_LEN];
 	u_int16_t		as[ETHER_ADDR_LEN / 2];
 	struct rl_softc		*sc;
 	struct ifnet		*ifp;
 	const struct rl_hwrev	*hw_rev;
 	u_int32_t		cap, ctl;
 	int			hwrev;
 	u_int16_t		devid, re_did = 0;
 	int			error = 0, i, phy, rid;
 	int			msic, msixc, reg;
 	uint8_t			cfg;
 
 	sc = device_get_softc(dev);
 	sc->rl_dev = dev;
 
 	mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
 	    MTX_DEF);
 	callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
 
 	/*
 	 * Map control/status registers.
 	 */
 	pci_enable_busmaster(dev);
 
 	devid = pci_get_device(dev);
 	/*
 	 * Prefer memory space register mapping over IO space.
 	 * Because RTL8169SC does not seem to work when memory mapping
 	 * is used always activate io mapping.
 	 */
 	if (devid == RT_DEVICEID_8169SC)
 		prefer_iomap = 1;
 	if (prefer_iomap == 0) {
 		sc->rl_res_id = PCIR_BAR(1);
 		sc->rl_res_type = SYS_RES_MEMORY;
 		/* RTL8168/8101E seems to use different BARs. */
 		if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E)
 			sc->rl_res_id = PCIR_BAR(2);
 	} else {
 		sc->rl_res_id = PCIR_BAR(0);
 		sc->rl_res_type = SYS_RES_IOPORT;
 	}
 	sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
 	    &sc->rl_res_id, RF_ACTIVE);
 	if (sc->rl_res == NULL && prefer_iomap == 0) {
 		sc->rl_res_id = PCIR_BAR(0);
 		sc->rl_res_type = SYS_RES_IOPORT;
 		sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
 		    &sc->rl_res_id, RF_ACTIVE);
 	}
 	if (sc->rl_res == NULL) {
 		device_printf(dev, "couldn't map ports/memory\n");
 		error = ENXIO;
 		goto fail;
 	}
 
 	sc->rl_btag = rman_get_bustag(sc->rl_res);
 	sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
 
 	msic = pci_msi_count(dev);
 	msixc = pci_msix_count(dev);
 	if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
 		sc->rl_flags |= RL_FLAG_PCIE;
 		sc->rl_expcap = reg;
 	}
 	if (bootverbose) {
 		device_printf(dev, "MSI count : %d\n", msic);
 		device_printf(dev, "MSI-X count : %d\n", msixc);
 	}
 	if (msix_disable > 0)
 		msixc = 0;
 	if (msi_disable > 0)
 		msic = 0;
 	/* Prefer MSI-X to MSI. */
 	if (msixc > 0) {
 		msixc = RL_MSI_MESSAGES;
 		rid = PCIR_BAR(4);
 		sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 		    &rid, RF_ACTIVE);
 		if (sc->rl_res_pba == NULL) {
 			device_printf(sc->rl_dev,
 			    "could not allocate MSI-X PBA resource\n");
 		}
 		if (sc->rl_res_pba != NULL &&
 		    pci_alloc_msix(dev, &msixc) == 0) {
 			if (msixc == RL_MSI_MESSAGES) {
 				device_printf(dev, "Using %d MSI-X message\n",
 				    msixc);
 				sc->rl_flags |= RL_FLAG_MSIX;
 			} else
 				pci_release_msi(dev);
 		}
 		if ((sc->rl_flags & RL_FLAG_MSIX) == 0) {
 			if (sc->rl_res_pba != NULL)
 				bus_release_resource(dev, SYS_RES_MEMORY, rid,
 				    sc->rl_res_pba);
 			sc->rl_res_pba = NULL;
 			msixc = 0;
 		}
 	}
 	/* Prefer MSI to INTx. */
 	if (msixc == 0 && msic > 0) {
 		msic = RL_MSI_MESSAGES;
 		if (pci_alloc_msi(dev, &msic) == 0) {
 			if (msic == RL_MSI_MESSAGES) {
 				device_printf(dev, "Using %d MSI message\n",
 				    msic);
 				sc->rl_flags |= RL_FLAG_MSI;
 				/* Explicitly set MSI enable bit. */
 				CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
 				cfg = CSR_READ_1(sc, RL_CFG2);
 				cfg |= RL_CFG2_MSI;
 				CSR_WRITE_1(sc, RL_CFG2, cfg);
 				CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
 			} else
 				pci_release_msi(dev);
 		}
 		if ((sc->rl_flags & RL_FLAG_MSI) == 0)
 			msic = 0;
 	}
 
 	/* Allocate interrupt */
 	if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) {
 		rid = 0;
 		sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 		    RF_SHAREABLE | RF_ACTIVE);
 		if (sc->rl_irq[0] == NULL) {
 			device_printf(dev, "couldn't allocate IRQ resources\n");
 			error = ENXIO;
 			goto fail;
 		}
 	} else {
 		for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) {
 			sc->rl_irq[i] = bus_alloc_resource_any(dev,
 			    SYS_RES_IRQ, &rid, RF_ACTIVE);
 			if (sc->rl_irq[i] == NULL) {
 				device_printf(dev,
 				    "couldn't llocate IRQ resources for "
 				    "message %d\n", rid);
 				error = ENXIO;
 				goto fail;
 			}
 		}
 	}
 
 	if ((sc->rl_flags & RL_FLAG_MSI) == 0) {
 		CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
 		cfg = CSR_READ_1(sc, RL_CFG2);
 		if ((cfg & RL_CFG2_MSI) != 0) {
 			device_printf(dev, "turning off MSI enable bit.\n");
 			cfg &= ~RL_CFG2_MSI;
 			CSR_WRITE_1(sc, RL_CFG2, cfg);
 		}
 		CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
 	}
 
 	/* Disable ASPM L0S/L1. */
 	if (sc->rl_expcap != 0) {
 		cap = pci_read_config(dev, sc->rl_expcap +
 		    PCIER_LINK_CAP, 2);
 		if ((cap & PCIEM_LINK_CAP_ASPM) != 0) {
 			ctl = pci_read_config(dev, sc->rl_expcap +
 			    PCIER_LINK_CTL, 2);
 			if ((ctl & 0x0003) != 0) {
 				ctl &= ~0x0003;
 				pci_write_config(dev, sc->rl_expcap +
 				    PCIER_LINK_CTL, ctl, 2);
 				device_printf(dev, "ASPM disabled\n");
 			}
 		} else
 			device_printf(dev, "no ASPM capability\n");
 	}
 
 	hw_rev = re_hwrevs;
 	hwrev = CSR_READ_4(sc, RL_TXCFG);
 	switch (hwrev & 0x70000000) {
 	case 0x00000000:
 	case 0x10000000:
 		device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000);
 		hwrev &= (RL_TXCFG_HWREV | 0x80000000);
 		break;
 	default:
 		device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000);
 		sc->rl_macrev = hwrev & 0x00700000;
 		hwrev &= RL_TXCFG_HWREV;
 		break;
 	}
 	device_printf(dev, "MAC rev. 0x%08x\n", sc->rl_macrev);
 	while (hw_rev->rl_desc != NULL) {
 		if (hw_rev->rl_rev == hwrev) {
 			sc->rl_type = hw_rev->rl_type;
 			sc->rl_hwrev = hw_rev;
 			break;
 		}
 		hw_rev++;
 	}
 	if (hw_rev->rl_desc == NULL) {
 		device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev);
 		error = ENXIO;
 		goto fail;
 	}
 
 	switch (hw_rev->rl_rev) {
 	case RL_HWREV_8139CPLUS:
 		sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD;
 		break;
 	case RL_HWREV_8100E:
 	case RL_HWREV_8101E:
 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER;
 		break;
 	case RL_HWREV_8102E:
 	case RL_HWREV_8102EL:
 	case RL_HWREV_8102EL_SPIN1:
 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
 		    RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
 		    RL_FLAG_AUTOPAD;
 		break;
 	case RL_HWREV_8103E:
 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
 		    RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
 		    RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP;
 		break;
 	case RL_HWREV_8401E:
 	case RL_HWREV_8105E:
 	case RL_HWREV_8105E_SPIN1:
 	case RL_HWREV_8106E:
 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
 		    RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
 		    RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD;
 		break;
 	case RL_HWREV_8402:
 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
 		    RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
 		    RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD |
 		    RL_FLAG_CMDSTOP_WAIT_TXQ;
 		break;
 	case RL_HWREV_8168B_SPIN1:
 	case RL_HWREV_8168B_SPIN2:
 		sc->rl_flags |= RL_FLAG_WOLRXENB;
 		/* FALLTHROUGH */
 	case RL_HWREV_8168B_SPIN3:
 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT;
 		break;
 	case RL_HWREV_8168C_SPIN2:
 		sc->rl_flags |= RL_FLAG_MACSLEEP;
 		/* FALLTHROUGH */
 	case RL_HWREV_8168C:
 		if (sc->rl_macrev == 0x00200000)
 			sc->rl_flags |= RL_FLAG_MACSLEEP;
 		/* FALLTHROUGH */
 	case RL_HWREV_8168CP:
 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
 		    RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
 		    RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK;
 		break;
 	case RL_HWREV_8168D:
 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
 		    RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
 		    RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
 		    RL_FLAG_WOL_MANLINK;
 		break;
 	case RL_HWREV_8168DP:
 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
 		    RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD |
 		    RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK;
 		break;
 	case RL_HWREV_8168E:
 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
 		    RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
 		    RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
 		    RL_FLAG_WOL_MANLINK;
 		break;
 	case RL_HWREV_8168E_VL:
 	case RL_HWREV_8168F:
 		sc->rl_flags |= RL_FLAG_EARLYOFF;
 		/* FALLTHROUGH */
 	case RL_HWREV_8411:
 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
 		    RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
 		    RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
 		    RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK;
 		break;
 	case RL_HWREV_8168EP:
 	case RL_HWREV_8168G:
 	case RL_HWREV_8411B:
 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
 		    RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
 		    RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
 		    RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK |
 		    RL_FLAG_EARLYOFFV2 | RL_FLAG_RXDV_GATED;
 		break;
 	case RL_HWREV_8168GU:
 		if (pci_get_device(dev) == RT_DEVICEID_8101E) {
 			/* RTL8106EUS */
 			sc->rl_flags |= RL_FLAG_FASTETHER;
 		} else
 			sc->rl_flags |= RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK;
 
 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
 		    RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
 		    RL_FLAG_AUTOPAD | RL_FLAG_CMDSTOP_WAIT_TXQ |
 		    RL_FLAG_EARLYOFFV2 | RL_FLAG_RXDV_GATED;
 		break;
 	case RL_HWREV_8169_8110SB:
 	case RL_HWREV_8169_8110SBL:
 	case RL_HWREV_8169_8110SC:
 	case RL_HWREV_8169_8110SCE:
 		sc->rl_flags |= RL_FLAG_PHYWAKE;
 		/* FALLTHROUGH */
 	case RL_HWREV_8169:
 	case RL_HWREV_8169S:
 	case RL_HWREV_8110S:
 		sc->rl_flags |= RL_FLAG_MACRESET;
 		break;
 	default:
 		break;
 	}
 
 	if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) {
 		sc->rl_cfg0 = RL_8139_CFG0;
 		sc->rl_cfg1 = RL_8139_CFG1;
 		sc->rl_cfg2 = 0;
 		sc->rl_cfg3 = RL_8139_CFG3;
 		sc->rl_cfg4 = RL_8139_CFG4;
 		sc->rl_cfg5 = RL_8139_CFG5;
 	} else {
 		sc->rl_cfg0 = RL_CFG0;
 		sc->rl_cfg1 = RL_CFG1;
 		sc->rl_cfg2 = RL_CFG2;
 		sc->rl_cfg3 = RL_CFG3;
 		sc->rl_cfg4 = RL_CFG4;
 		sc->rl_cfg5 = RL_CFG5;
 	}
 
 	/* Reset the adapter. */
 	RL_LOCK(sc);
 	re_reset(sc);
 	RL_UNLOCK(sc);
 
 	/* Enable PME. */
 	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
 	cfg = CSR_READ_1(sc, sc->rl_cfg1);
 	cfg |= RL_CFG1_PME;
 	CSR_WRITE_1(sc, sc->rl_cfg1, cfg);
 	cfg = CSR_READ_1(sc, sc->rl_cfg5);
 	cfg &= RL_CFG5_PME_STS;
 	CSR_WRITE_1(sc, sc->rl_cfg5, cfg);
 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
 
 	if ((sc->rl_flags & RL_FLAG_PAR) != 0) {
 		/*
 		 * XXX Should have a better way to extract station
 		 * address from EEPROM.
 		 */
 		for (i = 0; i < ETHER_ADDR_LEN; i++)
 			eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
 	} else {
 		sc->rl_eewidth = RL_9356_ADDR_LEN;
 		re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
 		if (re_did != 0x8129)
 			sc->rl_eewidth = RL_9346_ADDR_LEN;
 
 		/*
 		 * Get station address from the EEPROM.
 		 */
 		re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3);
 		for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
 			as[i] = le16toh(as[i]);
 		bcopy(as, eaddr, ETHER_ADDR_LEN);
 	}
 
 	if (sc->rl_type == RL_8169) {
 		/* Set RX length mask and number of descriptors. */
 		sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
 		sc->rl_txstart = RL_GTXSTART;
 		sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT;
 		sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT;
 	} else {
 		/* Set RX length mask and number of descriptors. */
 		sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
 		sc->rl_txstart = RL_TXSTART;
 		sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT;
 		sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT;
 	}
 
 	error = re_allocmem(dev, sc);
 	if (error)
 		goto fail;
 	re_add_sysctls(sc);
 
 	ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
 	if (ifp == NULL) {
 		device_printf(dev, "can not if_alloc()\n");
 		error = ENOSPC;
 		goto fail;
 	}
 
 	/* Take controller out of deep sleep mode. */
 	if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
 		if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
 			CSR_WRITE_1(sc, RL_GPIO,
 			    CSR_READ_1(sc, RL_GPIO) | 0x01);
 		else
 			CSR_WRITE_1(sc, RL_GPIO,
 			    CSR_READ_1(sc, RL_GPIO) & ~0x01);
 	}
 
 	/* Take PHY out of power down mode. */
 	if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) {
 		CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80);
 		if (hw_rev->rl_rev == RL_HWREV_8401E)
 			CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08);
 	}
 	if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) {
 		re_gmii_writereg(dev, 1, 0x1f, 0);
 		re_gmii_writereg(dev, 1, 0x0e, 0);
 	}
 
 	ifp->if_softc = sc;
 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 	ifp->if_ioctl = re_ioctl;
 	ifp->if_start = re_start;
 	/*
 	 * RTL8168/8111C generates wrong IP checksummed frame if the
 	 * packet has IP options so disable TX checksum offloading.
 	 */
 	if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C ||
 	    sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 ||
 	    sc->rl_hwrev->rl_rev == RL_HWREV_8168CP) {
 		ifp->if_hwassist = 0;
 		ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TSO4;
 	} else {
 		ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP;
 		ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
 	}
 	ifp->if_hwassist |= CSUM_TSO;
 	ifp->if_capenable = ifp->if_capabilities;
 	ifp->if_init = re_init;
 	IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
 	ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
 	IFQ_SET_READY(&ifp->if_snd);
 
 	TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc);
 
 #define	RE_PHYAD_INTERNAL	 0
 
 	/* Do MII setup. */
 	phy = RE_PHYAD_INTERNAL;
 	if (sc->rl_type == RL_8169)
 		phy = 1;
 	error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd,
 	    re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE);
 	if (error != 0) {
 		device_printf(dev, "attaching PHYs failed\n");
 		goto fail;
 	}
 
 	/*
 	 * Call MI attach routine.
 	 */
 	ether_ifattach(ifp, eaddr);
 
 	/* VLAN capability setup */
 	ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
 	if (ifp->if_capabilities & IFCAP_HWCSUM)
 		ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
 	/* Enable WOL if PM is supported. */
 	if (pci_find_cap(sc->rl_dev, PCIY_PMG, &reg) == 0)
 		ifp->if_capabilities |= IFCAP_WOL;
 	ifp->if_capenable = ifp->if_capabilities;
 	ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST);
 	/*
 	 * Don't enable TSO by default.  It is known to generate
 	 * corrupted TCP segments(bad TCP options) under certain
 	 * circumtances.
 	 */
 	ifp->if_hwassist &= ~CSUM_TSO;
 	ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
 #ifdef DEVICE_POLLING
 	ifp->if_capabilities |= IFCAP_POLLING;
 #endif
 	/*
 	 * Tell the upper layer(s) we support long frames.
 	 * Must appear after the call to ether_ifattach() because
 	 * ether_ifattach() sets ifi_hdrlen to the default value.
 	 */
 	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
 
 #ifdef DEV_NETMAP
 	re_netmap_attach(sc);
 #endif /* DEV_NETMAP */
 #ifdef RE_DIAG
 	/*
 	 * Perform hardware diagnostic on the original RTL8169.
 	 * Some 32-bit cards were incorrectly wired and would
 	 * malfunction if plugged into a 64-bit slot.
 	 */
 
 	if (hwrev == RL_HWREV_8169) {
 		error = re_diag(sc);
 		if (error) {
 			device_printf(dev,
 		    	"attach aborted due to hardware diag failure\n");
 			ether_ifdetach(ifp);
 			goto fail;
 		}
 	}
 #endif
 
 #ifdef RE_TX_MODERATION
 	intr_filter = 1;
 #endif
 	/* Hook interrupt last to avoid having to lock softc */
 	if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
 	    intr_filter == 0) {
 		error = bus_setup_intr(dev, sc->rl_irq[0],
 		    INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc,
 		    &sc->rl_intrhand[0]);
 	} else {
 		error = bus_setup_intr(dev, sc->rl_irq[0],
 		    INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc,
 		    &sc->rl_intrhand[0]);
 	}
 	if (error) {
 		device_printf(dev, "couldn't set up irq\n");
 		ether_ifdetach(ifp);
 	}
 
 fail:
 
 	if (error)
 		re_detach(dev);
 
 	return (error);
 }
 
 /*
  * Shutdown hardware and free up resources. This can be called any
  * time after the mutex has been initialized. It is called in both
  * the error case in attach and the normal detach case so it needs
  * to be careful about only freeing resources that have actually been
  * allocated.
  */
 static int
 re_detach(device_t dev)
 {
 	struct rl_softc		*sc;
 	struct ifnet		*ifp;
 	int			i, rid;
 
 	sc = device_get_softc(dev);
 	ifp = sc->rl_ifp;
 	KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
 
 	/* These should only be active if attach succeeded */
 	if (device_is_attached(dev)) {
 #ifdef DEVICE_POLLING
 		if (ifp->if_capenable & IFCAP_POLLING)
 			ether_poll_deregister(ifp);
 #endif
 		RL_LOCK(sc);
 #if 0
 		sc->suspended = 1;
 #endif
 		re_stop(sc);
 		RL_UNLOCK(sc);
 		callout_drain(&sc->rl_stat_callout);
 		taskqueue_drain(taskqueue_fast, &sc->rl_inttask);
 		/*
 		 * Force off the IFF_UP flag here, in case someone
 		 * still had a BPF descriptor attached to this
 		 * interface. If they do, ether_ifdetach() will cause
 		 * the BPF code to try and clear the promisc mode
 		 * flag, which will bubble down to re_ioctl(),
 		 * which will try to call re_init() again. This will
 		 * turn the NIC back on and restart the MII ticker,
 		 * which will panic the system when the kernel tries
 		 * to invoke the re_tick() function that isn't there
 		 * anymore.
 		 */
 		ifp->if_flags &= ~IFF_UP;
 		ether_ifdetach(ifp);
 	}
 	if (sc->rl_miibus)
 		device_delete_child(dev, sc->rl_miibus);
 	bus_generic_detach(dev);
 
 	/*
 	 * The rest is resource deallocation, so we should already be
 	 * stopped here.
 	 */
 
 	if (sc->rl_intrhand[0] != NULL) {
 		bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
 		sc->rl_intrhand[0] = NULL;
 	}
 	if (ifp != NULL) {
 #ifdef DEV_NETMAP
 		netmap_detach(ifp);
 #endif /* DEV_NETMAP */
 		if_free(ifp);
 	}
 	if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
 		rid = 0;
 	else
 		rid = 1;
 	if (sc->rl_irq[0] != NULL) {
 		bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]);
 		sc->rl_irq[0] = NULL;
 	}
 	if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0)
 		pci_release_msi(dev);
 	if (sc->rl_res_pba) {
 		rid = PCIR_BAR(4);
 		bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba);
 	}
 	if (sc->rl_res)
 		bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
 		    sc->rl_res);
 
 	/* Unload and free the RX DMA ring memory and map */
 
 	if (sc->rl_ldata.rl_rx_list_tag) {
 		if (sc->rl_ldata.rl_rx_list_map)
 			bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
 			    sc->rl_ldata.rl_rx_list_map);
 		if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list)
 			bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
 			    sc->rl_ldata.rl_rx_list,
 			    sc->rl_ldata.rl_rx_list_map);
 		bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
 	}
 
 	/* Unload and free the TX DMA ring memory and map */
 
 	if (sc->rl_ldata.rl_tx_list_tag) {
 		if (sc->rl_ldata.rl_tx_list_map)
 			bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
 			    sc->rl_ldata.rl_tx_list_map);
 		if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list)
 			bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
 			    sc->rl_ldata.rl_tx_list,
 			    sc->rl_ldata.rl_tx_list_map);
 		bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
 	}
 
 	/* Destroy all the RX and TX buffer maps */
 
 	if (sc->rl_ldata.rl_tx_mtag) {
 		for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
 			if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap)
 				bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag,
 				    sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
 		}
 		bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag);
 	}
 	if (sc->rl_ldata.rl_rx_mtag) {
 		for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
 			if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap)
 				bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
 				    sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
 		}
 		if (sc->rl_ldata.rl_rx_sparemap)
 			bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
 			    sc->rl_ldata.rl_rx_sparemap);
 		bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag);
 	}
 	if (sc->rl_ldata.rl_jrx_mtag) {
 		for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
 			if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap)
 				bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
 				    sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
 		}
 		if (sc->rl_ldata.rl_jrx_sparemap)
 			bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
 			    sc->rl_ldata.rl_jrx_sparemap);
 		bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag);
 	}
 	/* Unload and free the stats buffer and map */
 
 	if (sc->rl_ldata.rl_stag) {
 		if (sc->rl_ldata.rl_smap)
 			bus_dmamap_unload(sc->rl_ldata.rl_stag,
 			    sc->rl_ldata.rl_smap);
 		if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats)
 			bus_dmamem_free(sc->rl_ldata.rl_stag,
 			    sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap);
 		bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
 	}
 
 	if (sc->rl_parent_tag)
 		bus_dma_tag_destroy(sc->rl_parent_tag);
 
 	mtx_destroy(&sc->rl_mtx);
 
 	return (0);
 }
 
 static __inline void
 re_discard_rxbuf(struct rl_softc *sc, int idx)
 {
 	struct rl_desc		*desc;
 	struct rl_rxdesc	*rxd;
 	uint32_t		cmdstat;
 
 	if (sc->rl_ifp->if_mtu > RL_MTU &&
 	    (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
 		rxd = &sc->rl_ldata.rl_jrx_desc[idx];
 	else
 		rxd = &sc->rl_ldata.rl_rx_desc[idx];
 	desc = &sc->rl_ldata.rl_rx_list[idx];
 	desc->rl_vlanctl = 0;
 	cmdstat = rxd->rx_size;
 	if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
 		cmdstat |= RL_RDESC_CMD_EOR;
 	desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
 }
 
 static int
 re_newbuf(struct rl_softc *sc, int idx)
 {
 	struct mbuf		*m;
 	struct rl_rxdesc	*rxd;
 	bus_dma_segment_t	segs[1];
 	bus_dmamap_t		map;
 	struct rl_desc		*desc;
 	uint32_t		cmdstat;
 	int			error, nsegs;
 
 	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
 	if (m == NULL)
 		return (ENOBUFS);
 
 	m->m_len = m->m_pkthdr.len = MCLBYTES;
 #ifdef RE_FIXUP_RX
 	/*
 	 * This is part of an evil trick to deal with non-x86 platforms.
 	 * The RealTek chip requires RX buffers to be aligned on 64-bit
 	 * boundaries, but that will hose non-x86 machines. To get around
 	 * this, we leave some empty space at the start of each buffer
 	 * and for non-x86 hosts, we copy the buffer back six bytes
 	 * to achieve word alignment. This is slightly more efficient
 	 * than allocating a new buffer, copying the contents, and
 	 * discarding the old buffer.
 	 */
 	m_adj(m, RE_ETHER_ALIGN);
 #endif
 	error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag,
 	    sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
 	if (error != 0) {
 		m_freem(m);
 		return (ENOBUFS);
 	}
 	KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
 
 	rxd = &sc->rl_ldata.rl_rx_desc[idx];
 	if (rxd->rx_m != NULL) {
 		bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
 		    BUS_DMASYNC_POSTREAD);
 		bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap);
 	}
 
 	rxd->rx_m = m;
 	map = rxd->rx_dmamap;
 	rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap;
 	rxd->rx_size = segs[0].ds_len;
 	sc->rl_ldata.rl_rx_sparemap = map;
 	bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
 	    BUS_DMASYNC_PREREAD);
 
 	desc = &sc->rl_ldata.rl_rx_list[idx];
 	desc->rl_vlanctl = 0;
 	desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
 	desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
 	cmdstat = segs[0].ds_len;
 	if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
 		cmdstat |= RL_RDESC_CMD_EOR;
 	desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
 
 	return (0);
 }
 
 static int
 re_jumbo_newbuf(struct rl_softc *sc, int idx)
 {
 	struct mbuf		*m;
 	struct rl_rxdesc	*rxd;
 	bus_dma_segment_t	segs[1];
 	bus_dmamap_t		map;
 	struct rl_desc		*desc;
 	uint32_t		cmdstat;
 	int			error, nsegs;
 
 	m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
 	if (m == NULL)
 		return (ENOBUFS);
 	m->m_len = m->m_pkthdr.len = MJUM9BYTES;
 #ifdef RE_FIXUP_RX
 	m_adj(m, RE_ETHER_ALIGN);
 #endif
 	error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag,
 	    sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
 	if (error != 0) {
 		m_freem(m);
 		return (ENOBUFS);
 	}
 	KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
 
 	rxd = &sc->rl_ldata.rl_jrx_desc[idx];
 	if (rxd->rx_m != NULL) {
 		bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
 		    BUS_DMASYNC_POSTREAD);
 		bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap);
 	}
 
 	rxd->rx_m = m;
 	map = rxd->rx_dmamap;
 	rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap;
 	rxd->rx_size = segs[0].ds_len;
 	sc->rl_ldata.rl_jrx_sparemap = map;
 	bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
 	    BUS_DMASYNC_PREREAD);
 
 	desc = &sc->rl_ldata.rl_rx_list[idx];
 	desc->rl_vlanctl = 0;
 	desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
 	desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
 	cmdstat = segs[0].ds_len;
 	if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
 		cmdstat |= RL_RDESC_CMD_EOR;
 	desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
 
 	return (0);
 }
 
 #ifdef RE_FIXUP_RX
 static __inline void
 re_fixup_rx(struct mbuf *m)
 {
 	int                     i;
 	uint16_t                *src, *dst;
 
 	src = mtod(m, uint16_t *);
 	dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
 
 	for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
 		*dst++ = *src++;
 
 	m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
 }
 #endif
 
 static int
 re_tx_list_init(struct rl_softc *sc)
 {
 	struct rl_desc		*desc;
 	int			i;
 
 	RL_LOCK_ASSERT(sc);
 
 	bzero(sc->rl_ldata.rl_tx_list,
 	    sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc));
 	for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++)
 		sc->rl_ldata.rl_tx_desc[i].tx_m = NULL;
 #ifdef DEV_NETMAP
 	re_netmap_tx_init(sc);
 #endif /* DEV_NETMAP */
 	/* Set EOR. */
 	desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1];
 	desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR);
 
 	bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
 	    sc->rl_ldata.rl_tx_list_map,
 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 
 	sc->rl_ldata.rl_tx_prodidx = 0;
 	sc->rl_ldata.rl_tx_considx = 0;
 	sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt;
 
 	return (0);
 }
 
 static int
 re_rx_list_init(struct rl_softc *sc)
 {
 	int			error, i;
 
 	bzero(sc->rl_ldata.rl_rx_list,
 	    sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
 	for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
 		sc->rl_ldata.rl_rx_desc[i].rx_m = NULL;
 		if ((error = re_newbuf(sc, i)) != 0)
 			return (error);
 	}
 #ifdef DEV_NETMAP
 	re_netmap_rx_init(sc);
 #endif /* DEV_NETMAP */
 
 	/* Flush the RX descriptors */
 
 	bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
 	    sc->rl_ldata.rl_rx_list_map,
 	    BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
 
 	sc->rl_ldata.rl_rx_prodidx = 0;
 	sc->rl_head = sc->rl_tail = NULL;
 	sc->rl_int_rx_act = 0;
 
 	return (0);
 }
 
 static int
 re_jrx_list_init(struct rl_softc *sc)
 {
 	int			error, i;
 
 	bzero(sc->rl_ldata.rl_rx_list,
 	    sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
 	for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
 		sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL;
 		if ((error = re_jumbo_newbuf(sc, i)) != 0)
 			return (error);
 	}
 
 	bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
 	    sc->rl_ldata.rl_rx_list_map,
 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 
 	sc->rl_ldata.rl_rx_prodidx = 0;
 	sc->rl_head = sc->rl_tail = NULL;
 	sc->rl_int_rx_act = 0;
 
 	return (0);
 }
 
 /*
  * RX handler for C+ and 8169. For the gigE chips, we support
  * the reception of jumbo frames that have been fragmented
  * across multiple 2K mbuf cluster buffers.
  */
 static int
 re_rxeof(struct rl_softc *sc, int *rx_npktsp)
 {
 	struct mbuf		*m;
 	struct ifnet		*ifp;
 	int			i, rxerr, total_len;
 	struct rl_desc		*cur_rx;
 	u_int32_t		rxstat, rxvlan;
 	int			jumbo, maxpkt = 16, rx_npkts = 0;
 
 	RL_LOCK_ASSERT(sc);
 
 	ifp = sc->rl_ifp;
 #ifdef DEV_NETMAP
 	if (netmap_rx_irq(ifp, 0, &rx_npkts))
 		return 0;
 #endif /* DEV_NETMAP */
 	if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
 		jumbo = 1;
 	else
 		jumbo = 0;
 
 	/* Invalidate the descriptor memory */
 
 	bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
 	    sc->rl_ldata.rl_rx_list_map,
 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 
 	for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0;
 	    i = RL_RX_DESC_NXT(sc, i)) {
 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
 			break;
 		cur_rx = &sc->rl_ldata.rl_rx_list[i];
 		rxstat = le32toh(cur_rx->rl_cmdstat);
 		if ((rxstat & RL_RDESC_STAT_OWN) != 0)
 			break;
 		total_len = rxstat & sc->rl_rxlenmask;
 		rxvlan = le32toh(cur_rx->rl_vlanctl);
 		if (jumbo != 0)
 			m = sc->rl_ldata.rl_jrx_desc[i].rx_m;
 		else
 			m = sc->rl_ldata.rl_rx_desc[i].rx_m;
 
 		if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
 		    (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) !=
 		    (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) {
 			/*
 			 * RTL8168C or later controllers do not
 			 * support multi-fragment packet.
 			 */
 			re_discard_rxbuf(sc, i);
 			continue;
 		} else if ((rxstat & RL_RDESC_STAT_EOF) == 0) {
 			if (re_newbuf(sc, i) != 0) {
 				/*
 				 * If this is part of a multi-fragment packet,
 				 * discard all the pieces.
 				 */
 				if (sc->rl_head != NULL) {
 					m_freem(sc->rl_head);
 					sc->rl_head = sc->rl_tail = NULL;
 				}
 				re_discard_rxbuf(sc, i);
 				continue;
 			}
 			m->m_len = RE_RX_DESC_BUFLEN;
 			if (sc->rl_head == NULL)
 				sc->rl_head = sc->rl_tail = m;
 			else {
 				m->m_flags &= ~M_PKTHDR;
 				sc->rl_tail->m_next = m;
 				sc->rl_tail = m;
 			}
 			continue;
 		}
 
 		/*
 		 * NOTE: for the 8139C+, the frame length field
 		 * is always 12 bits in size, but for the gigE chips,
 		 * it is 13 bits (since the max RX frame length is 16K).
 		 * Unfortunately, all 32 bits in the status word
 		 * were already used, so to make room for the extra
 		 * length bit, RealTek took out the 'frame alignment
 		 * error' bit and shifted the other status bits
 		 * over one slot. The OWN, EOR, FS and LS bits are
 		 * still in the same places. We have already extracted
 		 * the frame length and checked the OWN bit, so rather
 		 * than using an alternate bit mapping, we shift the
 		 * status bits one space to the right so we can evaluate
 		 * them using the 8169 status as though it was in the
 		 * same format as that of the 8139C+.
 		 */
 		if (sc->rl_type == RL_8169)
 			rxstat >>= 1;
 
 		/*
 		 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
 		 * set, but if CRC is clear, it will still be a valid frame.
 		 */
 		if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) {
 			rxerr = 1;
 			if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 &&
 			    total_len > 8191 &&
 			    (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)
 				rxerr = 0;
 			if (rxerr != 0) {
 				ifp->if_ierrors++;
 				/*
 				 * If this is part of a multi-fragment packet,
 				 * discard all the pieces.
 				 */
 				if (sc->rl_head != NULL) {
 					m_freem(sc->rl_head);
 					sc->rl_head = sc->rl_tail = NULL;
 				}
 				re_discard_rxbuf(sc, i);
 				continue;
 			}
 		}
 
 		/*
 		 * If allocating a replacement mbuf fails,
 		 * reload the current one.
 		 */
 		if (jumbo != 0)
 			rxerr = re_jumbo_newbuf(sc, i);
 		else
 			rxerr = re_newbuf(sc, i);
 		if (rxerr != 0) {
 			ifp->if_iqdrops++;
 			if (sc->rl_head != NULL) {
 				m_freem(sc->rl_head);
 				sc->rl_head = sc->rl_tail = NULL;
 			}
 			re_discard_rxbuf(sc, i);
 			continue;
 		}
 
 		if (sc->rl_head != NULL) {
 			if (jumbo != 0)
 				m->m_len = total_len;
 			else {
 				m->m_len = total_len % RE_RX_DESC_BUFLEN;
 				if (m->m_len == 0)
 					m->m_len = RE_RX_DESC_BUFLEN;
 			}
 			/*
 			 * Special case: if there's 4 bytes or less
 			 * in this buffer, the mbuf can be discarded:
 			 * the last 4 bytes is the CRC, which we don't
 			 * care about anyway.
 			 */
 			if (m->m_len <= ETHER_CRC_LEN) {
 				sc->rl_tail->m_len -=
 				    (ETHER_CRC_LEN - m->m_len);
 				m_freem(m);
 			} else {
 				m->m_len -= ETHER_CRC_LEN;
 				m->m_flags &= ~M_PKTHDR;
 				sc->rl_tail->m_next = m;
 			}
 			m = sc->rl_head;
 			sc->rl_head = sc->rl_tail = NULL;
 			m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
 		} else
 			m->m_pkthdr.len = m->m_len =
 			    (total_len - ETHER_CRC_LEN);
 
 #ifdef RE_FIXUP_RX
 		re_fixup_rx(m);
 #endif
 		ifp->if_ipackets++;
 		m->m_pkthdr.rcvif = ifp;
 
 		/* Do RX checksumming if enabled */
 
 		if (ifp->if_capenable & IFCAP_RXCSUM) {
 			if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
 				/* Check IP header checksum */
 				if (rxstat & RL_RDESC_STAT_PROTOID)
 					m->m_pkthdr.csum_flags |=
 					    CSUM_IP_CHECKED;
 				if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
 					m->m_pkthdr.csum_flags |=
 					    CSUM_IP_VALID;
 
 				/* Check TCP/UDP checksum */
 				if ((RL_TCPPKT(rxstat) &&
 				    !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
 				    (RL_UDPPKT(rxstat) &&
 				     !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
 					m->m_pkthdr.csum_flags |=
 						CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
 					m->m_pkthdr.csum_data = 0xffff;
 				}
 			} else {
 				/*
 				 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP
 				 */
 				if ((rxstat & RL_RDESC_STAT_PROTOID) &&
 				    (rxvlan & RL_RDESC_IPV4))
 					m->m_pkthdr.csum_flags |=
 					    CSUM_IP_CHECKED;
 				if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) &&
 				    (rxvlan & RL_RDESC_IPV4))
 					m->m_pkthdr.csum_flags |=
 					    CSUM_IP_VALID;
 				if (((rxstat & RL_RDESC_STAT_TCP) &&
 				    !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
 				    ((rxstat & RL_RDESC_STAT_UDP) &&
 				    !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
 					m->m_pkthdr.csum_flags |=
 						CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
 					m->m_pkthdr.csum_data = 0xffff;
 				}
 			}
 		}
 		maxpkt--;
 		if (rxvlan & RL_RDESC_VLANCTL_TAG) {
 			m->m_pkthdr.ether_vtag =
 			    bswap16((rxvlan & RL_RDESC_VLANCTL_DATA));
 			m->m_flags |= M_VLANTAG;
 		}
 		RL_UNLOCK(sc);
 		(*ifp->if_input)(ifp, m);
 		RL_LOCK(sc);
 		rx_npkts++;
 	}
 
 	/* Flush the RX DMA ring */
 
 	bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
 	    sc->rl_ldata.rl_rx_list_map,
 	    BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
 
 	sc->rl_ldata.rl_rx_prodidx = i;
 
 	if (rx_npktsp != NULL)
 		*rx_npktsp = rx_npkts;
 	if (maxpkt)
 		return (EAGAIN);
 
 	return (0);
 }
 
 static void
 re_txeof(struct rl_softc *sc)
 {
 	struct ifnet		*ifp;
 	struct rl_txdesc	*txd;
 	u_int32_t		txstat;
 	int			cons;
 
 	cons = sc->rl_ldata.rl_tx_considx;
 	if (cons == sc->rl_ldata.rl_tx_prodidx)
 		return;
 
 	ifp = sc->rl_ifp;
 #ifdef DEV_NETMAP
 	if (netmap_tx_irq(ifp, 0))
 		return;
 #endif /* DEV_NETMAP */
 	/* Invalidate the TX descriptor list */
 	bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
 	    sc->rl_ldata.rl_tx_list_map,
 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 
 	for (; cons != sc->rl_ldata.rl_tx_prodidx;
 	    cons = RL_TX_DESC_NXT(sc, cons)) {
 		txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat);
 		if (txstat & RL_TDESC_STAT_OWN)
 			break;
 		/*
 		 * We only stash mbufs in the last descriptor
 		 * in a fragment chain, which also happens to
 		 * be the only place where the TX status bits
 		 * are valid.
 		 */
 		if (txstat & RL_TDESC_CMD_EOF) {
 			txd = &sc->rl_ldata.rl_tx_desc[cons];
 			bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
 			    txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
 			bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
 			    txd->tx_dmamap);
 			KASSERT(txd->tx_m != NULL,
 			    ("%s: freeing NULL mbufs!", __func__));
 			m_freem(txd->tx_m);
 			txd->tx_m = NULL;
 			if (txstat & (RL_TDESC_STAT_EXCESSCOL|
 			    RL_TDESC_STAT_COLCNT))
 				ifp->if_collisions++;
 			if (txstat & RL_TDESC_STAT_TXERRSUM)
 				ifp->if_oerrors++;
 			else
 				ifp->if_opackets++;
 		}
 		sc->rl_ldata.rl_tx_free++;
 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 	}
 	sc->rl_ldata.rl_tx_considx = cons;
 
 	/* No changes made to the TX ring, so no flush needed */
 
 	if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) {
 #ifdef RE_TX_MODERATION
 		/*
 		 * If not all descriptors have been reaped yet, reload
 		 * the timer so that we will eventually get another
 		 * interrupt that will cause us to re-enter this routine.
 		 * This is done in case the transmitter has gone idle.
 		 */
 		CSR_WRITE_4(sc, RL_TIMERCNT, 1);
 #endif
 	} else
 		sc->rl_watchdog_timer = 0;
 }
 
 static void
 re_tick(void *xsc)
 {
 	struct rl_softc		*sc;
 	struct mii_data		*mii;
 
 	sc = xsc;
 
 	RL_LOCK_ASSERT(sc);
 
 	mii = device_get_softc(sc->rl_miibus);
 	mii_tick(mii);
 	if ((sc->rl_flags & RL_FLAG_LINK) == 0)
 		re_miibus_statchg(sc->rl_dev);
 	/*
 	 * Reclaim transmitted frames here. Technically it is not
 	 * necessary to do here but it ensures periodic reclamation
 	 * regardless of Tx completion interrupt which seems to be
 	 * lost on PCIe based controllers under certain situations.
 	 */
 	re_txeof(sc);
 	re_watchdog(sc);
 	callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
 }
 
 #ifdef DEVICE_POLLING
 static int
 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
 {
 	struct rl_softc *sc = ifp->if_softc;
 	int rx_npkts = 0;
 
 	RL_LOCK(sc);
 	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
 		rx_npkts = re_poll_locked(ifp, cmd, count);
 	RL_UNLOCK(sc);
 	return (rx_npkts);
 }
 
 static int
 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
 {
 	struct rl_softc *sc = ifp->if_softc;
 	int rx_npkts;
 
 	RL_LOCK_ASSERT(sc);
 
 	sc->rxcycles = count;
 	re_rxeof(sc, &rx_npkts);
 	re_txeof(sc);
 
 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
 		re_start_locked(ifp);
 
 	if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
 		u_int16_t       status;
 
 		status = CSR_READ_2(sc, RL_ISR);
 		if (status == 0xffff)
 			return (rx_npkts);
 		if (status)
 			CSR_WRITE_2(sc, RL_ISR, status);
 		if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
 		    (sc->rl_flags & RL_FLAG_PCIE))
 			CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
 
 		/*
 		 * XXX check behaviour on receiver stalls.
 		 */
 
 		if (status & RL_ISR_SYSTEM_ERR) {
 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 			re_init_locked(sc);
 		}
 	}
 	return (rx_npkts);
 }
 #endif /* DEVICE_POLLING */
 
 static int
 re_intr(void *arg)
 {
 	struct rl_softc		*sc;
 	uint16_t		status;
 
 	sc = arg;
 
 	status = CSR_READ_2(sc, RL_ISR);
 	if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0)
                 return (FILTER_STRAY);
 	CSR_WRITE_2(sc, RL_IMR, 0);
 
 	taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
 
 	return (FILTER_HANDLED);
 }
 
 static void
 re_int_task(void *arg, int npending)
 {
 	struct rl_softc		*sc;
 	struct ifnet		*ifp;
 	u_int16_t		status;
 	int			rval = 0;
 
 	sc = arg;
 	ifp = sc->rl_ifp;
 
 	RL_LOCK(sc);
 
 	status = CSR_READ_2(sc, RL_ISR);
         CSR_WRITE_2(sc, RL_ISR, status);
 
 	if (sc->suspended ||
 	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
 		RL_UNLOCK(sc);
 		return;
 	}
 
 #ifdef DEVICE_POLLING
 	if  (ifp->if_capenable & IFCAP_POLLING) {
 		RL_UNLOCK(sc);
 		return;
 	}
 #endif
 
 	if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW))
 		rval = re_rxeof(sc, NULL);
 
 	/*
 	 * Some chips will ignore a second TX request issued
 	 * while an existing transmission is in progress. If
 	 * the transmitter goes idle but there are still
 	 * packets waiting to be sent, we need to restart the
 	 * channel here to flush them out. This only seems to
 	 * be required with the PCIe devices.
 	 */
 	if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
 	    (sc->rl_flags & RL_FLAG_PCIE))
 		CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
 	if (status & (
 #ifdef RE_TX_MODERATION
 	    RL_ISR_TIMEOUT_EXPIRED|
 #else
 	    RL_ISR_TX_OK|
 #endif
 	    RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL))
 		re_txeof(sc);
 
 	if (status & RL_ISR_SYSTEM_ERR) {
 		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 		re_init_locked(sc);
 	}
 
 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
 		re_start_locked(ifp);
 
 	RL_UNLOCK(sc);
 
         if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) {
 		taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
 		return;
 	}
 
 	CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
 }
 
 static void
 re_intr_msi(void *xsc)
 {
 	struct rl_softc		*sc;
 	struct ifnet		*ifp;
 	uint16_t		intrs, status;
 
 	sc = xsc;
 	RL_LOCK(sc);
 
 	ifp = sc->rl_ifp;
 #ifdef DEVICE_POLLING
 	if (ifp->if_capenable & IFCAP_POLLING) {
 		RL_UNLOCK(sc);
 		return;
 	}
 #endif
 	/* Disable interrupts. */
 	CSR_WRITE_2(sc, RL_IMR, 0);
 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
 		RL_UNLOCK(sc);
 		return;
 	}
 
 	intrs = RL_INTRS_CPLUS;
 	status = CSR_READ_2(sc, RL_ISR);
         CSR_WRITE_2(sc, RL_ISR, status);
 	if (sc->rl_int_rx_act > 0) {
 		intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW |
 		    RL_ISR_RX_OVERRUN);
 		status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW |
 		    RL_ISR_RX_OVERRUN);
 	}
 
 	if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR |
 	    RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) {
 		re_rxeof(sc, NULL);
 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
 			if (sc->rl_int_rx_mod != 0 &&
 			    (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR |
 			    RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) {
 				/* Rearm one-shot timer. */
 				CSR_WRITE_4(sc, RL_TIMERCNT, 1);
 				intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR |
 				    RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN);
 				sc->rl_int_rx_act = 1;
 			} else {
 				intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR |
 				    RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN;
 				sc->rl_int_rx_act = 0;
 			}
 		}
 	}
 
 	/*
 	 * Some chips will ignore a second TX request issued
 	 * while an existing transmission is in progress. If
 	 * the transmitter goes idle but there are still
 	 * packets waiting to be sent, we need to restart the
 	 * channel here to flush them out. This only seems to
 	 * be required with the PCIe devices.
 	 */
 	if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
 	    (sc->rl_flags & RL_FLAG_PCIE))
 		CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
 	if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL))
 		re_txeof(sc);
 
 	if (status & RL_ISR_SYSTEM_ERR) {
 		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 		re_init_locked(sc);
 	}
 
 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
 		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
 			re_start_locked(ifp);
 		CSR_WRITE_2(sc, RL_IMR, intrs);
 	}
 	RL_UNLOCK(sc);
 }
 
 static int
 re_encap(struct rl_softc *sc, struct mbuf **m_head)
 {
 	struct rl_txdesc	*txd, *txd_last;
 	bus_dma_segment_t	segs[RL_NTXSEGS];
 	bus_dmamap_t		map;
 	struct mbuf		*m_new;
 	struct rl_desc		*desc;
 	int			nsegs, prod;
 	int			i, error, ei, si;
 	int			padlen;
 	uint32_t		cmdstat, csum_flags, vlanctl;
 
 	RL_LOCK_ASSERT(sc);
 	M_ASSERTPKTHDR((*m_head));
 
 	/*
 	 * With some of the RealTek chips, using the checksum offload
 	 * support in conjunction with the autopadding feature results
 	 * in the transmission of corrupt frames. For example, if we
 	 * need to send a really small IP fragment that's less than 60
 	 * bytes in size, and IP header checksumming is enabled, the
 	 * resulting ethernet frame that appears on the wire will
 	 * have garbled payload. To work around this, if TX IP checksum
 	 * offload is enabled, we always manually pad short frames out
 	 * to the minimum ethernet frame size.
 	 */
 	if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 &&
 	    (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN &&
 	    ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) {
 		padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len;
 		if (M_WRITABLE(*m_head) == 0) {
 			/* Get a writable copy. */
 			m_new = m_dup(*m_head, M_NOWAIT);
 			m_freem(*m_head);
 			if (m_new == NULL) {
 				*m_head = NULL;
 				return (ENOBUFS);
 			}
 			*m_head = m_new;
 		}
 		if ((*m_head)->m_next != NULL ||
 		    M_TRAILINGSPACE(*m_head) < padlen) {
 			m_new = m_defrag(*m_head, M_NOWAIT);
 			if (m_new == NULL) {
 				m_freem(*m_head);
 				*m_head = NULL;
 				return (ENOBUFS);
 			}
 		} else
 			m_new = *m_head;
 
 		/*
 		 * Manually pad short frames, and zero the pad space
 		 * to avoid leaking data.
 		 */
 		bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen);
 		m_new->m_pkthdr.len += padlen;
 		m_new->m_len = m_new->m_pkthdr.len;
 		*m_head = m_new;
 	}
 
 	prod = sc->rl_ldata.rl_tx_prodidx;
 	txd = &sc->rl_ldata.rl_tx_desc[prod];
 	error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
 	    *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
 	if (error == EFBIG) {
 		m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS);
 		if (m_new == NULL) {
 			m_freem(*m_head);
 			*m_head = NULL;
 			return (ENOBUFS);
 		}
 		*m_head = m_new;
 		error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag,
 		    txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
 		if (error != 0) {
 			m_freem(*m_head);
 			*m_head = NULL;
 			return (error);
 		}
 	} else if (error != 0)
 		return (error);
 	if (nsegs == 0) {
 		m_freem(*m_head);
 		*m_head = NULL;
 		return (EIO);
 	}
 
 	/* Check for number of available descriptors. */
 	if (sc->rl_ldata.rl_tx_free - nsegs <= 1) {
 		bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap);
 		return (ENOBUFS);
 	}
 
 	bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
 	    BUS_DMASYNC_PREWRITE);
 
 	/*
 	 * Set up checksum offload. Note: checksum offload bits must
 	 * appear in all descriptors of a multi-descriptor transmit
 	 * attempt. This is according to testing done with an 8169
 	 * chip. This is a requirement.
 	 */
 	vlanctl = 0;
 	csum_flags = 0;
 	if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
 		if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) {
 			csum_flags |= RL_TDESC_CMD_LGSEND;
 			vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
 			    RL_TDESC_CMD_MSSVALV2_SHIFT);
 		} else {
 			csum_flags |= RL_TDESC_CMD_LGSEND |
 			    ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
 			    RL_TDESC_CMD_MSSVAL_SHIFT);
 		}
 	} else {
 		/*
 		 * Unconditionally enable IP checksum if TCP or UDP
 		 * checksum is required. Otherwise, TCP/UDP checksum
 		 * does't make effects.
 		 */
 		if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) {
 			if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
 				csum_flags |= RL_TDESC_CMD_IPCSUM;
 				if (((*m_head)->m_pkthdr.csum_flags &
 				    CSUM_TCP) != 0)
 					csum_flags |= RL_TDESC_CMD_TCPCSUM;
 				if (((*m_head)->m_pkthdr.csum_flags &
 				    CSUM_UDP) != 0)
 					csum_flags |= RL_TDESC_CMD_UDPCSUM;
 			} else {
 				vlanctl |= RL_TDESC_CMD_IPCSUMV2;
 				if (((*m_head)->m_pkthdr.csum_flags &
 				    CSUM_TCP) != 0)
 					vlanctl |= RL_TDESC_CMD_TCPCSUMV2;
 				if (((*m_head)->m_pkthdr.csum_flags &
 				    CSUM_UDP) != 0)
 					vlanctl |= RL_TDESC_CMD_UDPCSUMV2;
 			}
 		}
 	}
 
 	/*
 	 * Set up hardware VLAN tagging. Note: vlan tag info must
 	 * appear in all descriptors of a multi-descriptor
 	 * transmission attempt.
 	 */
 	if ((*m_head)->m_flags & M_VLANTAG)
 		vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) |
 		    RL_TDESC_VLANCTL_TAG;
 
 	si = prod;
 	for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) {
 		desc = &sc->rl_ldata.rl_tx_list[prod];
 		desc->rl_vlanctl = htole32(vlanctl);
 		desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
 		desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
 		cmdstat = segs[i].ds_len;
 		if (i != 0)
 			cmdstat |= RL_TDESC_CMD_OWN;
 		if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1)
 			cmdstat |= RL_TDESC_CMD_EOR;
 		desc->rl_cmdstat = htole32(cmdstat | csum_flags);
 		sc->rl_ldata.rl_tx_free--;
 	}
 	/* Update producer index. */
 	sc->rl_ldata.rl_tx_prodidx = prod;
 
 	/* Set EOF on the last descriptor. */
 	ei = RL_TX_DESC_PRV(sc, prod);
 	desc = &sc->rl_ldata.rl_tx_list[ei];
 	desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
 
 	desc = &sc->rl_ldata.rl_tx_list[si];
 	/* Set SOF and transfer ownership of packet to the chip. */
 	desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF);
 
 	/*
 	 * Insure that the map for this transmission
 	 * is placed at the array index of the last descriptor
 	 * in this chain.  (Swap last and first dmamaps.)
 	 */
 	txd_last = &sc->rl_ldata.rl_tx_desc[ei];
 	map = txd->tx_dmamap;
 	txd->tx_dmamap = txd_last->tx_dmamap;
 	txd_last->tx_dmamap = map;
 	txd_last->tx_m = *m_head;
 
 	return (0);
 }
 
 static void
 re_start(struct ifnet *ifp)
 {
 	struct rl_softc		*sc;
 
 	sc = ifp->if_softc;
 	RL_LOCK(sc);
 	re_start_locked(ifp);
 	RL_UNLOCK(sc);
 }
 
 /*
  * Main transmit routine for C+ and gigE NICs.
  */
 static void
 re_start_locked(struct ifnet *ifp)
 {
 	struct rl_softc		*sc;
 	struct mbuf		*m_head;
 	int			queued;
 
 	sc = ifp->if_softc;
 
 #ifdef DEV_NETMAP
 	/* XXX is this necessary ? */
 	if (ifp->if_capenable & IFCAP_NETMAP) {
 		struct netmap_kring *kring = &NA(ifp)->tx_rings[0];
 		if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) {
 			/* kick the tx unit */
 			CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
 #ifdef RE_TX_MODERATION
 			CSR_WRITE_4(sc, RL_TIMERCNT, 1);
 #endif
 			sc->rl_watchdog_timer = 5;
 		}
 		return;
 	}
 #endif /* DEV_NETMAP */
 	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
 	    IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
 		return;
 
 	for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
 	    sc->rl_ldata.rl_tx_free > 1;) {
 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
 		if (m_head == NULL)
 			break;
 
 		if (re_encap(sc, &m_head) != 0) {
 			if (m_head == NULL)
 				break;
 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 			break;
 		}
 
 		/*
 		 * If there's a BPF listener, bounce a copy of this frame
 		 * to him.
 		 */
 		ETHER_BPF_MTAP(ifp, m_head);
 
 		queued++;
 	}
 
 	if (queued == 0) {
 #ifdef RE_TX_MODERATION
 		if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt)
 			CSR_WRITE_4(sc, RL_TIMERCNT, 1);
 #endif
 		return;
 	}
 
 	/* Flush the TX descriptors */
 
 	bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
 	    sc->rl_ldata.rl_tx_list_map,
 	    BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
 
 	CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
 
 #ifdef RE_TX_MODERATION
 	/*
 	 * Use the countdown timer for interrupt moderation.
 	 * 'TX done' interrupts are disabled. Instead, we reset the
 	 * countdown timer, which will begin counting until it hits
 	 * the value in the TIMERINT register, and then trigger an
 	 * interrupt. Each time we write to the TIMERCNT register,
 	 * the timer count is reset to 0.
 	 */
 	CSR_WRITE_4(sc, RL_TIMERCNT, 1);
 #endif
 
 	/*
 	 * Set a timeout in case the chip goes out to lunch.
 	 */
 	sc->rl_watchdog_timer = 5;
 }
 
 static void
 re_set_jumbo(struct rl_softc *sc, int jumbo)
 {
 
 	if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) {
 		pci_set_max_read_req(sc->rl_dev, 4096);
 		return;
 	}
 
 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
 	if (jumbo != 0) {
 		CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) |
 		    RL_CFG3_JUMBO_EN0);
 		switch (sc->rl_hwrev->rl_rev) {
 		case RL_HWREV_8168DP:
 			break;
 		case RL_HWREV_8168E:
 			CSR_WRITE_1(sc, sc->rl_cfg4,
 			    CSR_READ_1(sc, sc->rl_cfg4) | 0x01);
 			break;
 		default:
 			CSR_WRITE_1(sc, sc->rl_cfg4,
 			    CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1);
 		}
 	} else {
 		CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) &
 		    ~RL_CFG3_JUMBO_EN0);
 		switch (sc->rl_hwrev->rl_rev) {
 		case RL_HWREV_8168DP:
 			break;
 		case RL_HWREV_8168E:
 			CSR_WRITE_1(sc, sc->rl_cfg4,
 			    CSR_READ_1(sc, sc->rl_cfg4) & ~0x01);
 			break;
 		default:
 			CSR_WRITE_1(sc, sc->rl_cfg4,
 			    CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1);
 		}
 	}
 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
 
 	switch (sc->rl_hwrev->rl_rev) {
 	case RL_HWREV_8168DP:
 		pci_set_max_read_req(sc->rl_dev, 4096);
 		break;
 	default:
 		if (jumbo != 0)
 			pci_set_max_read_req(sc->rl_dev, 512);
 		else
 			pci_set_max_read_req(sc->rl_dev, 4096);
 	}
 }
 
 static void
 re_init(void *xsc)
 {
 	struct rl_softc		*sc = xsc;
 
 	RL_LOCK(sc);
 	re_init_locked(sc);
 	RL_UNLOCK(sc);
 }
 
 static void
 re_init_locked(struct rl_softc *sc)
 {
 	struct ifnet		*ifp = sc->rl_ifp;
 	struct mii_data		*mii;
 	uint32_t		reg;
 	uint16_t		cfg;
 	union {
 		uint32_t align_dummy;
 		u_char eaddr[ETHER_ADDR_LEN];
         } eaddr;
 
 	RL_LOCK_ASSERT(sc);
 
 	mii = device_get_softc(sc->rl_miibus);
 
 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
 		return;
 
 	/*
 	 * Cancel pending I/O and free all RX/TX buffers.
 	 */
 	re_stop(sc);
 
 	/* Put controller into known state. */
 	re_reset(sc);
 
 	/*
 	 * For C+ mode, initialize the RX descriptors and mbufs.
 	 */
 	if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
 		if (ifp->if_mtu > RL_MTU) {
 			if (re_jrx_list_init(sc) != 0) {
 				device_printf(sc->rl_dev,
 				    "no memory for jumbo RX buffers\n");
 				re_stop(sc);
 				return;
 			}
 			/* Disable checksum offloading for jumbo frames. */
 			ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4);
 			ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO);
 		} else {
 			if (re_rx_list_init(sc) != 0) {
 				device_printf(sc->rl_dev,
 				    "no memory for RX buffers\n");
 				re_stop(sc);
 				return;
 			}
 		}
 		re_set_jumbo(sc, ifp->if_mtu > RL_MTU);
 	} else {
 		if (re_rx_list_init(sc) != 0) {
 			device_printf(sc->rl_dev, "no memory for RX buffers\n");
 			re_stop(sc);
 			return;
 		}
 		if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
 		    pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) {
 			if (ifp->if_mtu > RL_MTU)
 				pci_set_max_read_req(sc->rl_dev, 512);
 			else
 				pci_set_max_read_req(sc->rl_dev, 4096);
 		}
 	}
 	re_tx_list_init(sc);
 
 	/*
 	 * Enable C+ RX and TX mode, as well as VLAN stripping and
 	 * RX checksum offload. We must configure the C+ register
 	 * before all others.
 	 */
 	cfg = RL_CPLUSCMD_PCI_MRW;
 	if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
 		cfg |= RL_CPLUSCMD_RXCSUM_ENB;
 	if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
 		cfg |= RL_CPLUSCMD_VLANSTRIP;
 	if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) {
 		cfg |= RL_CPLUSCMD_MACSTAT_DIS;
 		/* XXX magic. */
 		cfg |= 0x0001;
 	} else
 		cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB;
 	CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg);
 	if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC ||
 	    sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) {
 		reg = 0x000fff00;
 		if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0)
 			reg |= 0x000000ff;
 		if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE)
 			reg |= 0x00f00000;
 		CSR_WRITE_4(sc, 0x7c, reg);
 		/* Disable interrupt mitigation. */
 		CSR_WRITE_2(sc, 0xe2, 0);
 	}
 	/*
 	 * Disable TSO if interface MTU size is greater than MSS
 	 * allowed in controller.
 	 */
 	if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) {
 		ifp->if_capenable &= ~IFCAP_TSO4;
 		ifp->if_hwassist &= ~CSUM_TSO;
 	}
 
 	/*
 	 * Init our MAC address.  Even though the chipset
 	 * documentation doesn't mention it, we need to enter "Config
 	 * register write enable" mode to modify the ID registers.
 	 */
 	/* Copy MAC address on stack to align. */
 	bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN);
 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
 	CSR_WRITE_4(sc, RL_IDR0,
 	    htole32(*(u_int32_t *)(&eaddr.eaddr[0])));
 	CSR_WRITE_4(sc, RL_IDR4,
 	    htole32(*(u_int32_t *)(&eaddr.eaddr[4])));
 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
 
 	/*
 	 * Load the addresses of the RX and TX lists into the chip.
 	 */
 
 	CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
 	    RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
 	CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
 	    RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
 
 	CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
 	    RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
 	CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
 	    RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
 
 	if ((sc->rl_flags & RL_FLAG_RXDV_GATED) != 0)
 		CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) &
 		    ~0x00080000);
 
 	/*
 	 * Set the initial TX configuration.
 	 */
 	if (sc->rl_testmode) {
 		if (sc->rl_type == RL_8169)
 			CSR_WRITE_4(sc, RL_TXCFG,
 			    RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
 		else
 			CSR_WRITE_4(sc, RL_TXCFG,
 			    RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
 	} else
 		CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
 
 	CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
 
 	/*
 	 * Set the initial RX configuration.
 	 */
 	re_set_rxmode(sc);
 
 	/* Configure interrupt moderation. */
 	if (sc->rl_type == RL_8169) {
 		/* Magic from vendor. */
 		CSR_WRITE_2(sc, RL_INTRMOD, 0x5100);
 	}
 
 	/*
 	 * Enable transmit and receive.
 	 */
 	CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB);
 
 #ifdef DEVICE_POLLING
 	/*
 	 * Disable interrupts if we are polling.
 	 */
 	if (ifp->if_capenable & IFCAP_POLLING)
 		CSR_WRITE_2(sc, RL_IMR, 0);
 	else	/* otherwise ... */
 #endif
 
 	/*
 	 * Enable interrupts.
 	 */
 	if (sc->rl_testmode)
 		CSR_WRITE_2(sc, RL_IMR, 0);
 	else
 		CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
 	CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS);
 
 	/* Set initial TX threshold */
 	sc->rl_txthresh = RL_TX_THRESH_INIT;
 
 	/* Start RX/TX process. */
 	CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
 
 	/*
 	 * Initialize the timer interrupt register so that
 	 * a timer interrupt will be generated once the timer
 	 * reaches a certain number of ticks. The timer is
 	 * reloaded on each transmit.
 	 */
 #ifdef RE_TX_MODERATION
 	/*
 	 * Use timer interrupt register to moderate TX interrupt
 	 * moderation, which dramatically improves TX frame rate.
 	 */
 	if (sc->rl_type == RL_8169)
 		CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
 	else
 		CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
 #else
 	/*
 	 * Use timer interrupt register to moderate RX interrupt
 	 * moderation.
 	 */
 	if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
 	    intr_filter == 0) {
 		if (sc->rl_type == RL_8169)
 			CSR_WRITE_4(sc, RL_TIMERINT_8169,
 			    RL_USECS(sc->rl_int_rx_mod));
 	} else {
 		if (sc->rl_type == RL_8169)
 			CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0));
 	}
 #endif
 
 	/*
 	 * For 8169 gigE NICs, set the max allowed RX packet
 	 * size so we can receive jumbo frames.
 	 */
 	if (sc->rl_type == RL_8169) {
 		if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
 			/*
 			 * For controllers that use new jumbo frame scheme,
 			 * set maximum size of jumbo frame depedning on
 			 * controller revisions.
 			 */
 			if (ifp->if_mtu > RL_MTU)
 				CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
 				    sc->rl_hwrev->rl_max_mtu +
 				    ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN +
 				    ETHER_CRC_LEN);
 			else
 				CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
 				    RE_RX_DESC_BUFLEN);
 		} else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
 		    sc->rl_hwrev->rl_max_mtu == RL_MTU) {
 			/* RTL810x has no jumbo frame support. */
 			CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN);
 		} else
 			CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
 	}
 
 	if (sc->rl_testmode)
 		return;
 
 	CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) |
 	    RL_CFG1_DRVLOAD);
 
 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 
 	sc->rl_flags &= ~RL_FLAG_LINK;
 	mii_mediachg(mii);
 
 	sc->rl_watchdog_timer = 0;
 	callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
 }
 
 /*
  * Set media options.
  */
 static int
 re_ifmedia_upd(struct ifnet *ifp)
 {
 	struct rl_softc		*sc;
 	struct mii_data		*mii;
 	int			error;
 
 	sc = ifp->if_softc;
 	mii = device_get_softc(sc->rl_miibus);
 	RL_LOCK(sc);
 	error = mii_mediachg(mii);
 	RL_UNLOCK(sc);
 
 	return (error);
 }
 
 /*
  * Report current media status.
  */
 static void
 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 {
 	struct rl_softc		*sc;
 	struct mii_data		*mii;
 
 	sc = ifp->if_softc;
 	mii = device_get_softc(sc->rl_miibus);
 
 	RL_LOCK(sc);
 	mii_pollstat(mii);
 	ifmr->ifm_active = mii->mii_media_active;
 	ifmr->ifm_status = mii->mii_media_status;
 	RL_UNLOCK(sc);
 }
 
 static int
 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 {
 	struct rl_softc		*sc = ifp->if_softc;
 	struct ifreq		*ifr = (struct ifreq *) data;
 	struct mii_data		*mii;
 	int			error = 0;
 
 	switch (command) {
 	case SIOCSIFMTU:
 		if (ifr->ifr_mtu < ETHERMIN ||
 		    ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu ||
 		    ((sc->rl_flags & RL_FLAG_FASTETHER) != 0 &&
 		    ifr->ifr_mtu > RL_MTU)) {
 			error = EINVAL;
 			break;
 		}
 		RL_LOCK(sc);
 		if (ifp->if_mtu != ifr->ifr_mtu) {
 			ifp->if_mtu = ifr->ifr_mtu;
 			if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
 			    (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
 				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 				re_init_locked(sc);
 			}
 			if (ifp->if_mtu > RL_TSO_MTU &&
 			    (ifp->if_capenable & IFCAP_TSO4) != 0) {
 				ifp->if_capenable &= ~(IFCAP_TSO4 |
 				    IFCAP_VLAN_HWTSO);
 				ifp->if_hwassist &= ~CSUM_TSO;
 			}
 			VLAN_CAPABILITIES(ifp);
 		}
 		RL_UNLOCK(sc);
 		break;
 	case SIOCSIFFLAGS:
 		RL_LOCK(sc);
 		if ((ifp->if_flags & IFF_UP) != 0) {
 			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
 				if (((ifp->if_flags ^ sc->rl_if_flags)
 				    & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
 					re_set_rxmode(sc);
 			} else
 				re_init_locked(sc);
 		} else {
 			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
 				re_stop(sc);
 		}
 		sc->rl_if_flags = ifp->if_flags;
 		RL_UNLOCK(sc);
 		break;
 	case SIOCADDMULTI:
 	case SIOCDELMULTI:
 		RL_LOCK(sc);
 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
 			re_set_rxmode(sc);
 		RL_UNLOCK(sc);
 		break;
 	case SIOCGIFMEDIA:
 	case SIOCSIFMEDIA:
 		mii = device_get_softc(sc->rl_miibus);
 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
 		break;
 	case SIOCSIFCAP:
 	    {
 		int mask, reinit;
 
 		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 		reinit = 0;
 #ifdef DEVICE_POLLING
 		if (mask & IFCAP_POLLING) {
 			if (ifr->ifr_reqcap & IFCAP_POLLING) {
 				error = ether_poll_register(re_poll, ifp);
 				if (error)
 					return (error);
 				RL_LOCK(sc);
 				/* Disable interrupts */
 				CSR_WRITE_2(sc, RL_IMR, 0x0000);
 				ifp->if_capenable |= IFCAP_POLLING;
 				RL_UNLOCK(sc);
 			} else {
 				error = ether_poll_deregister(ifp);
 				/* Enable interrupts. */
 				RL_LOCK(sc);
 				CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
 				ifp->if_capenable &= ~IFCAP_POLLING;
 				RL_UNLOCK(sc);
 			}
 		}
 #endif /* DEVICE_POLLING */
 		RL_LOCK(sc);
 		if ((mask & IFCAP_TXCSUM) != 0 &&
 		    (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
 			ifp->if_capenable ^= IFCAP_TXCSUM;
 			if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
 				ifp->if_hwassist |= RE_CSUM_FEATURES;
 			else
 				ifp->if_hwassist &= ~RE_CSUM_FEATURES;
 			reinit = 1;
 		}
 		if ((mask & IFCAP_RXCSUM) != 0 &&
 		    (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
 			ifp->if_capenable ^= IFCAP_RXCSUM;
 			reinit = 1;
 		}
 		if ((mask & IFCAP_TSO4) != 0 &&
 		    (ifp->if_capabilities & IFCAP_TSO4) != 0) {
 			ifp->if_capenable ^= IFCAP_TSO4;
 			if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
 				ifp->if_hwassist |= CSUM_TSO;
 			else
 				ifp->if_hwassist &= ~CSUM_TSO;
 			if (ifp->if_mtu > RL_TSO_MTU &&
 			    (ifp->if_capenable & IFCAP_TSO4) != 0) {
 				ifp->if_capenable &= ~IFCAP_TSO4;
 				ifp->if_hwassist &= ~CSUM_TSO;
 			}
 		}
 		if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
 		    (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
 			ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
 		if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
 		    (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
 			ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
 			/* TSO over VLAN requires VLAN hardware tagging. */
 			if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
 				ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
 			reinit = 1;
 		}
 		if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
 		    (mask & (IFCAP_HWCSUM | IFCAP_TSO4 |
 		    IFCAP_VLAN_HWTSO)) != 0)
 				reinit = 1;
 		if ((mask & IFCAP_WOL) != 0 &&
 		    (ifp->if_capabilities & IFCAP_WOL) != 0) {
 			if ((mask & IFCAP_WOL_UCAST) != 0)
 				ifp->if_capenable ^= IFCAP_WOL_UCAST;
 			if ((mask & IFCAP_WOL_MCAST) != 0)
 				ifp->if_capenable ^= IFCAP_WOL_MCAST;
 			if ((mask & IFCAP_WOL_MAGIC) != 0)
 				ifp->if_capenable ^= IFCAP_WOL_MAGIC;
 		}
 		if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) {
 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 			re_init_locked(sc);
 		}
 		RL_UNLOCK(sc);
 		VLAN_CAPABILITIES(ifp);
 	    }
 		break;
 	default:
 		error = ether_ioctl(ifp, command, data);
 		break;
 	}
 
 	return (error);
 }
 
 static void
 re_watchdog(struct rl_softc *sc)
 {
 	struct ifnet		*ifp;
 
 	RL_LOCK_ASSERT(sc);
 
 	if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0)
 		return;
 
 	ifp = sc->rl_ifp;
 	re_txeof(sc);
 	if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) {
 		if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
 		    "-- recovering\n");
 		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
 			re_start_locked(ifp);
 		return;
 	}
 
 	if_printf(ifp, "watchdog timeout\n");
 	ifp->if_oerrors++;
 
 	re_rxeof(sc, NULL);
 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 	re_init_locked(sc);
 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
 		re_start_locked(ifp);
 }
 
 /*
  * Stop the adapter and free any mbufs allocated to the
  * RX and TX lists.
  */
 static void
 re_stop(struct rl_softc *sc)
 {
 	int			i;
 	struct ifnet		*ifp;
 	struct rl_txdesc	*txd;
 	struct rl_rxdesc	*rxd;
 
 	RL_LOCK_ASSERT(sc);
 
 	ifp = sc->rl_ifp;
 
 	sc->rl_watchdog_timer = 0;
 	callout_stop(&sc->rl_stat_callout);
 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
 
 	/*
 	 * Disable accepting frames to put RX MAC into idle state.
 	 * Otherwise it's possible to get frames while stop command
 	 * execution is in progress and controller can DMA the frame
 	 * to already freed RX buffer during that period.
 	 */
 	CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) &
 	    ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI |
 	    RL_RXCFG_RX_BROAD));
 
 	if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) {
 		for (i = RL_TIMEOUT; i > 0; i--) {
 			if ((CSR_READ_1(sc, sc->rl_txstart) &
 			    RL_TXSTART_START) == 0)
 				break;
 			DELAY(20);
 		}
 		if (i == 0)
 			device_printf(sc->rl_dev,
 			    "stopping TX poll timed out!\n");
 		CSR_WRITE_1(sc, RL_COMMAND, 0x00);
 	} else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) {
 		CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB |
 		    RL_CMD_RX_ENB);
 		if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) {
 			for (i = RL_TIMEOUT; i > 0; i--) {
 				if ((CSR_READ_4(sc, RL_TXCFG) &
 				    RL_TXCFG_QUEUE_EMPTY) != 0)
 					break;
 				DELAY(100);
 			}
 			if (i == 0)
 				device_printf(sc->rl_dev,
 				   "stopping TXQ timed out!\n");
 		}
 	} else
 		CSR_WRITE_1(sc, RL_COMMAND, 0x00);
 	DELAY(1000);
 	CSR_WRITE_2(sc, RL_IMR, 0x0000);
 	CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
 
 	if (sc->rl_head != NULL) {
 		m_freem(sc->rl_head);
 		sc->rl_head = sc->rl_tail = NULL;
 	}
 
 	/* Free the TX list buffers. */
 	for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
 		txd = &sc->rl_ldata.rl_tx_desc[i];
 		if (txd->tx_m != NULL) {
 			bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
 			    txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
 			bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
 			    txd->tx_dmamap);
 			m_freem(txd->tx_m);
 			txd->tx_m = NULL;
 		}
 	}
 
 	/* Free the RX list buffers. */
 	for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
 		rxd = &sc->rl_ldata.rl_rx_desc[i];
 		if (rxd->rx_m != NULL) {
 			bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
 			    rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
 			bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
 			    rxd->rx_dmamap);
 			m_freem(rxd->rx_m);
 			rxd->rx_m = NULL;
 		}
 	}
 
 	if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
 		for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
 			rxd = &sc->rl_ldata.rl_jrx_desc[i];
 			if (rxd->rx_m != NULL) {
 				bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag,
 				    rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
 				bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag,
 				    rxd->rx_dmamap);
 				m_freem(rxd->rx_m);
 				rxd->rx_m = NULL;
 			}
 		}
 	}
 }
 
 /*
  * Device suspend routine.  Stop the interface and save some PCI
  * settings in case the BIOS doesn't restore them properly on
  * resume.
  */
 static int
 re_suspend(device_t dev)
 {
 	struct rl_softc		*sc;
 
 	sc = device_get_softc(dev);
 
 	RL_LOCK(sc);
 	re_stop(sc);
 	re_setwol(sc);
 	sc->suspended = 1;
 	RL_UNLOCK(sc);
 
 	return (0);
 }
 
 /*
  * Device resume routine.  Restore some PCI settings in case the BIOS
  * doesn't, re-enable busmastering, and restart the interface if
  * appropriate.
  */
 static int
 re_resume(device_t dev)
 {
 	struct rl_softc		*sc;
 	struct ifnet		*ifp;
 
 	sc = device_get_softc(dev);
 
 	RL_LOCK(sc);
 
 	ifp = sc->rl_ifp;
 	/* Take controller out of sleep mode. */
 	if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
 		if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
 			CSR_WRITE_1(sc, RL_GPIO,
 			    CSR_READ_1(sc, RL_GPIO) | 0x01);
 	}
 
 	/*
 	 * Clear WOL matching such that normal Rx filtering
 	 * wouldn't interfere with WOL patterns.
 	 */
 	re_clrwol(sc);
 
 	/* reinitialize interface if necessary */
 	if (ifp->if_flags & IFF_UP)
 		re_init_locked(sc);
 
 	sc->suspended = 0;
 	RL_UNLOCK(sc);
 
 	return (0);
 }
 
 /*
  * Stop all chip I/O so that the kernel's probe routines don't
  * get confused by errant DMAs when rebooting.
  */
 static int
 re_shutdown(device_t dev)
 {
 	struct rl_softc		*sc;
 
 	sc = device_get_softc(dev);
 
 	RL_LOCK(sc);
 	re_stop(sc);
 	/*
 	 * Mark interface as down since otherwise we will panic if
 	 * interrupt comes in later on, which can happen in some
 	 * cases.
 	 */
 	sc->rl_ifp->if_flags &= ~IFF_UP;
 	re_setwol(sc);
 	RL_UNLOCK(sc);
 
 	return (0);
 }
 
 static void
 re_set_linkspeed(struct rl_softc *sc)
 {
 	struct mii_softc *miisc;
 	struct mii_data *mii;
 	int aneg, i, phyno;
 
 	RL_LOCK_ASSERT(sc);
 
 	mii = device_get_softc(sc->rl_miibus);
 	mii_pollstat(mii);
 	aneg = 0;
 	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 	    (IFM_ACTIVE | IFM_AVALID)) {
 		switch IFM_SUBTYPE(mii->mii_media_active) {
 		case IFM_10_T:
 		case IFM_100_TX:
 			return;
 		case IFM_1000_T:
 			aneg++;
 			break;
 		default:
 			break;
 		}
 	}
 	miisc = LIST_FIRST(&mii->mii_phys);
 	phyno = miisc->mii_phy;
 	LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 		PHY_RESET(miisc);
 	re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0);
 	re_miibus_writereg(sc->rl_dev, phyno,
 	    MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
 	re_miibus_writereg(sc->rl_dev, phyno,
 	    MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
 	DELAY(1000);
 	if (aneg != 0) {
 		/*
 		 * Poll link state until re(4) get a 10/100Mbps link.
 		 */
 		for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
 			mii_pollstat(mii);
 			if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
 			    == (IFM_ACTIVE | IFM_AVALID)) {
 				switch (IFM_SUBTYPE(mii->mii_media_active)) {
 				case IFM_10_T:
 				case IFM_100_TX:
 					return;
 				default:
 					break;
 				}
 			}
 			RL_UNLOCK(sc);
 			pause("relnk", hz);
 			RL_LOCK(sc);
 		}
 		if (i == MII_ANEGTICKS_GIGE)
 			device_printf(sc->rl_dev,
 			    "establishing a link failed, WOL may not work!");
 	}
 	/*
 	 * No link, force MAC to have 100Mbps, full-duplex link.
 	 * MAC does not require reprogramming on resolved speed/duplex,
 	 * so this is just for completeness.
 	 */
 	mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
 	mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
 }
 
 static void
 re_setwol(struct rl_softc *sc)
 {
 	struct ifnet		*ifp;
 	int			pmc;
 	uint16_t		pmstat;
 	uint8_t			v;
 
 	RL_LOCK_ASSERT(sc);
 
 	if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
 		return;
 
 	ifp = sc->rl_ifp;
 	/* Put controller into sleep mode. */
 	if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
 		if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
 			CSR_WRITE_1(sc, RL_GPIO,
 			    CSR_READ_1(sc, RL_GPIO) & ~0x01);
 	}
 	if ((ifp->if_capenable & IFCAP_WOL) != 0) {
 		re_set_rxmode(sc);
 		if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0)
 			re_set_linkspeed(sc);
 		if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0)
 			CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB);
 	}
 	/* Enable config register write. */
 	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
 
 	/* Enable PME. */
 	v = CSR_READ_1(sc, sc->rl_cfg1);
 	v &= ~RL_CFG1_PME;
 	if ((ifp->if_capenable & IFCAP_WOL) != 0)
 		v |= RL_CFG1_PME;
 	CSR_WRITE_1(sc, sc->rl_cfg1, v);
 
 	v = CSR_READ_1(sc, sc->rl_cfg3);
 	v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
 	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
 		v |= RL_CFG3_WOL_MAGIC;
 	CSR_WRITE_1(sc, sc->rl_cfg3, v);
 
 	v = CSR_READ_1(sc, sc->rl_cfg5);
 	v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST |
 	    RL_CFG5_WOL_LANWAKE);
 	if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
 		v |= RL_CFG5_WOL_UCAST;
 	if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
 		v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
 	if ((ifp->if_capenable & IFCAP_WOL) != 0)
 		v |= RL_CFG5_WOL_LANWAKE;
 	CSR_WRITE_1(sc, sc->rl_cfg5, v);
 
 	/* Config register write done. */
 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
 
 	if ((ifp->if_capenable & IFCAP_WOL) == 0 &&
 	    (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0)
 		CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80);
 	/*
 	 * It seems that hardware resets its link speed to 100Mbps in
 	 * power down mode so switching to 100Mbps in driver is not
 	 * needed.
 	 */
 
 	/* Request PME if WOL is requested. */
 	pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
 	pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
 	if ((ifp->if_capenable & IFCAP_WOL) != 0)
 		pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
 	pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
 }
 
 static void
 re_clrwol(struct rl_softc *sc)
 {
 	int			pmc;
 	uint8_t			v;
 
 	RL_LOCK_ASSERT(sc);
 
 	if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
 		return;
 
 	/* Enable config register write. */
 	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
 
 	v = CSR_READ_1(sc, sc->rl_cfg3);
 	v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
 	CSR_WRITE_1(sc, sc->rl_cfg3, v);
 
 	/* Config register write done. */
 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
 
 	v = CSR_READ_1(sc, sc->rl_cfg5);
 	v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
 	v &= ~RL_CFG5_WOL_LANWAKE;
 	CSR_WRITE_1(sc, sc->rl_cfg5, v);
 }
 
 static void
 re_add_sysctls(struct rl_softc *sc)
 {
 	struct sysctl_ctx_list	*ctx;
 	struct sysctl_oid_list	*children;
 	int			error;
 
 	ctx = device_get_sysctl_ctx(sc->rl_dev);
 	children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
 
 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats",
 	    CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I",
 	    "Statistics Information");
 	if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
 		return;
 
 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod",
 	    CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0,
 	    sysctl_hw_re_int_mod, "I", "re RX interrupt moderation");
 	/* Pull in device tunables. */
 	sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
 	error = resource_int_value(device_get_name(sc->rl_dev),
 	    device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod);
 	if (error == 0) {
 		if (sc->rl_int_rx_mod < RL_TIMER_MIN ||
 		    sc->rl_int_rx_mod > RL_TIMER_MAX) {
 			device_printf(sc->rl_dev, "int_rx_mod value out of "
 			    "range; using default: %d\n",
 			    RL_TIMER_DEFAULT);
 			sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
 		}
 	}
 
 }
 
 static int
 re_sysctl_stats(SYSCTL_HANDLER_ARGS)
 {
 	struct rl_softc		*sc;
 	struct rl_stats		*stats;
 	int			error, i, result;
 
 	result = -1;
 	error = sysctl_handle_int(oidp, &result, 0, req);
 	if (error || req->newptr == NULL)
 		return (error);
 
 	if (result == 1) {
 		sc = (struct rl_softc *)arg1;
 		RL_LOCK(sc);
 		if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
 			RL_UNLOCK(sc);
 			goto done;
 		}
 		bus_dmamap_sync(sc->rl_ldata.rl_stag,
 		    sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD);
 		CSR_WRITE_4(sc, RL_DUMPSTATS_HI,
 		    RL_ADDR_HI(sc->rl_ldata.rl_stats_addr));
 		CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
 		    RL_ADDR_LO(sc->rl_ldata.rl_stats_addr));
 		CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
 		    RL_ADDR_LO(sc->rl_ldata.rl_stats_addr |
 		    RL_DUMPSTATS_START));
 		for (i = RL_TIMEOUT; i > 0; i--) {
 			if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) &
 			    RL_DUMPSTATS_START) == 0)
 				break;
 			DELAY(1000);
 		}
 		bus_dmamap_sync(sc->rl_ldata.rl_stag,
 		    sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD);
 		RL_UNLOCK(sc);
 		if (i == 0) {
 			device_printf(sc->rl_dev,
 			    "DUMP statistics request timedout\n");
 			return (ETIMEDOUT);
 		}
 done:
 		stats = sc->rl_ldata.rl_stats;
 		printf("%s statistics:\n", device_get_nameunit(sc->rl_dev));
 		printf("Tx frames : %ju\n",
 		    (uintmax_t)le64toh(stats->rl_tx_pkts));
 		printf("Rx frames : %ju\n",
 		    (uintmax_t)le64toh(stats->rl_rx_pkts));
 		printf("Tx errors : %ju\n",
 		    (uintmax_t)le64toh(stats->rl_tx_errs));
 		printf("Rx errors : %u\n",
 		    le32toh(stats->rl_rx_errs));
 		printf("Rx missed frames : %u\n",
 		    (uint32_t)le16toh(stats->rl_missed_pkts));
 		printf("Rx frame alignment errs : %u\n",
 		    (uint32_t)le16toh(stats->rl_rx_framealign_errs));
 		printf("Tx single collisions : %u\n",
 		    le32toh(stats->rl_tx_onecoll));
 		printf("Tx multiple collisions : %u\n",
 		    le32toh(stats->rl_tx_multicolls));
 		printf("Rx unicast frames : %ju\n",
 		    (uintmax_t)le64toh(stats->rl_rx_ucasts));
 		printf("Rx broadcast frames : %ju\n",
 		    (uintmax_t)le64toh(stats->rl_rx_bcasts));
 		printf("Rx multicast frames : %u\n",
 		    le32toh(stats->rl_rx_mcasts));
 		printf("Tx aborts : %u\n",
 		    (uint32_t)le16toh(stats->rl_tx_aborts));
 		printf("Tx underruns : %u\n",
 		    (uint32_t)le16toh(stats->rl_rx_underruns));
 	}
 
 	return (error);
 }
 
 static int
 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
 {
 	int error, value;
 
 	if (arg1 == NULL)
 		return (EINVAL);
 	value = *(int *)arg1;
 	error = sysctl_handle_int(oidp, &value, 0, req);
 	if (error || req->newptr == NULL)
 		return (error);
 	if (value < low || value > high)
 		return (EINVAL);
 	*(int *)arg1 = value;
 
 	return (0);
 }
 
 static int
 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS)
 {
 
 	return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN,
 	    RL_TIMER_MAX));
 }
Index: stable/9/sys/dev/rl/if_rl.c
===================================================================
--- stable/9/sys/dev/rl/if_rl.c	(nonexistent)
+++ stable/9/sys/dev/rl/if_rl.c	(revision 292781)
@@ -0,0 +1,2126 @@
+/*-
+ * Copyright (c) 1997, 1998
+ *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * RealTek 8129/8139 PCI NIC driver
+ *
+ * Supports several extremely cheap PCI 10/100 adapters based on
+ * the RealTek chipset. Datasheets can be obtained from
+ * www.realtek.com.tw.
+ *
+ * Written by Bill Paul <wpaul@ctr.columbia.edu>
+ * Electrical Engineering Department
+ * Columbia University, New York City
+ */
+/*
+ * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
+ * probably the worst PCI ethernet controller ever made, with the possible
+ * exception of the FEAST chip made by SMC. The 8139 supports bus-master
+ * DMA, but it has a terrible interface that nullifies any performance
+ * gains that bus-master DMA usually offers.
+ *
+ * For transmission, the chip offers a series of four TX descriptor
+ * registers. Each transmit frame must be in a contiguous buffer, aligned
+ * on a longword (32-bit) boundary. This means we almost always have to
+ * do mbuf copies in order to transmit a frame, except in the unlikely
+ * case where a) the packet fits into a single mbuf, and b) the packet
+ * is 32-bit aligned within the mbuf's data area. The presence of only
+ * four descriptor registers means that we can never have more than four
+ * packets queued for transmission at any one time.
+ *
+ * Reception is not much better. The driver has to allocate a single large
+ * buffer area (up to 64K in size) into which the chip will DMA received
+ * frames. Because we don't know where within this region received packets
+ * will begin or end, we have no choice but to copy data from the buffer
+ * area into mbufs in order to pass the packets up to the higher protocol
+ * levels.
+ *
+ * It's impossible given this rotten design to really achieve decent
+ * performance at 100Mbps, unless you happen to have a 400Mhz PII or
+ * some equally overmuscled CPU to drive it.
+ *
+ * On the bright side, the 8139 does have a built-in PHY, although
+ * rather than using an MDIO serial interface like most other NICs, the
+ * PHY registers are directly accessible through the 8139's register
+ * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
+ * filter.
+ *
+ * The 8129 chip is an older version of the 8139 that uses an external PHY
+ * chip. The 8129 has a serial MDIO interface for accessing the MII where
+ * the 8139 lets you directly access the on-board PHY registers. We need
+ * to select which interface to use depending on the chip type.
+ */
+
+#ifdef HAVE_KERNEL_OPTION_HEADERS
+#include "opt_device_polling.h"
+#endif
+
+#include <sys/param.h>
+#include <sys/endian.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/socket.h>
+#include <sys/sysctl.h>
+
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/ethernet.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+
+#include <net/bpf.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/mii_bitbang.h>
+#include <dev/mii/miivar.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+MODULE_DEPEND(rl, pci, 1, 1, 1);
+MODULE_DEPEND(rl, ether, 1, 1, 1);
+MODULE_DEPEND(rl, miibus, 1, 1, 1);
+
+/* "device miibus" required.  See GENERIC if you get errors here. */
+#include "miibus_if.h"
+
+#include <dev/rl/if_rlreg.h>
+
+/*
+ * Various supported device vendors/types and their names.
+ */
+static const struct rl_type rl_devs[] = {
+	{ RT_VENDORID, RT_DEVICEID_8129, RL_8129,
+		"RealTek 8129 10/100BaseTX" },
+	{ RT_VENDORID, RT_DEVICEID_8139, RL_8139,
+		"RealTek 8139 10/100BaseTX" },
+	{ RT_VENDORID, RT_DEVICEID_8139D, RL_8139,
+		"RealTek 8139 10/100BaseTX" },
+	{ RT_VENDORID, RT_DEVICEID_8138, RL_8139,
+		"RealTek 8139 10/100BaseTX CardBus" },
+	{ RT_VENDORID, RT_DEVICEID_8100, RL_8139,
+		"RealTek 8100 10/100BaseTX" },
+	{ ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
+		"Accton MPX 5030/5038 10/100BaseTX" },
+	{ DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
+		"Delta Electronics 8139 10/100BaseTX" },
+	{ ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
+		"Addtron Technology 8139 10/100BaseTX" },
+	{ DLINK_VENDORID, DLINK_DEVICEID_520TX_REVC1, RL_8139,
+		"D-Link DFE-520TX (rev. C1) 10/100BaseTX" },
+	{ DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
+		"D-Link DFE-530TX+ 10/100BaseTX" },
+	{ DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
+		"D-Link DFE-690TXD 10/100BaseTX" },
+	{ NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
+		"Nortel Networks 10/100BaseTX" },
+	{ COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
+		"Corega FEther CB-TXD" },
+	{ COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
+		"Corega FEtherII CB-TXD" },
+	{ PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
+		"Peppercon AG ROL-F" },
+	{ PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139,
+		"Planex FNW-3603-TX" },
+	{ PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
+		"Planex FNW-3800-TX" },
+	{ CP_VENDORID, RT_DEVICEID_8139, RL_8139,
+		"Compaq HNE-300" },
+	{ LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
+		"LevelOne FPC-0106TX" },
+	{ EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
+		"Edimax EP-4103DL CardBus" }
+};
+
+static int rl_attach(device_t);
+static int rl_detach(device_t);
+static void rl_dmamap_cb(void *, bus_dma_segment_t *, int, int);
+static int rl_dma_alloc(struct rl_softc *);
+static void rl_dma_free(struct rl_softc *);
+static void rl_eeprom_putbyte(struct rl_softc *, int);
+static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
+static int rl_encap(struct rl_softc *, struct mbuf **);
+static int rl_list_tx_init(struct rl_softc *);
+static int rl_list_rx_init(struct rl_softc *);
+static int rl_ifmedia_upd(struct ifnet *);
+static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
+static int rl_ioctl(struct ifnet *, u_long, caddr_t);
+static void rl_intr(void *);
+static void rl_init(void *);
+static void rl_init_locked(struct rl_softc *sc);
+static int rl_miibus_readreg(device_t, int, int);
+static void rl_miibus_statchg(device_t);
+static int rl_miibus_writereg(device_t, int, int, int);
+#ifdef DEVICE_POLLING
+static int rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
+static int rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
+#endif
+static int rl_probe(device_t);
+static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
+static void rl_reset(struct rl_softc *);
+static int rl_resume(device_t);
+static int rl_rxeof(struct rl_softc *);
+static void rl_rxfilter(struct rl_softc *);
+static int rl_shutdown(device_t);
+static void rl_start(struct ifnet *);
+static void rl_start_locked(struct ifnet *);
+static void rl_stop(struct rl_softc *);
+static int rl_suspend(device_t);
+static void rl_tick(void *);
+static void rl_txeof(struct rl_softc *);
+static void rl_watchdog(struct rl_softc *);
+static void rl_setwol(struct rl_softc *);
+static void rl_clrwol(struct rl_softc *);
+
+/*
+ * MII bit-bang glue
+ */
+static uint32_t rl_mii_bitbang_read(device_t);
+static void rl_mii_bitbang_write(device_t, uint32_t);
+
+static const struct mii_bitbang_ops rl_mii_bitbang_ops = {
+	rl_mii_bitbang_read,
+	rl_mii_bitbang_write,
+	{
+		RL_MII_DATAOUT,	/* MII_BIT_MDO */
+		RL_MII_DATAIN,	/* MII_BIT_MDI */
+		RL_MII_CLK,	/* MII_BIT_MDC */
+		RL_MII_DIR,	/* MII_BIT_DIR_HOST_PHY */
+		0,		/* MII_BIT_DIR_PHY_HOST */
+	}
+};
+
+static device_method_t rl_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		rl_probe),
+	DEVMETHOD(device_attach,	rl_attach),
+	DEVMETHOD(device_detach,	rl_detach),
+	DEVMETHOD(device_suspend,	rl_suspend),
+	DEVMETHOD(device_resume,	rl_resume),
+	DEVMETHOD(device_shutdown,	rl_shutdown),
+
+	/* MII interface */
+	DEVMETHOD(miibus_readreg,	rl_miibus_readreg),
+	DEVMETHOD(miibus_writereg,	rl_miibus_writereg),
+	DEVMETHOD(miibus_statchg,	rl_miibus_statchg),
+
+	DEVMETHOD_END
+};
+
+static driver_t rl_driver = {
+	"rl",
+	rl_methods,
+	sizeof(struct rl_softc)
+};
+
+static devclass_t rl_devclass;
+
+DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
+DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
+DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
+
+#define EE_SET(x)					\
+	CSR_WRITE_1(sc, RL_EECMD,			\
+		CSR_READ_1(sc, RL_EECMD) | x)
+
+#define EE_CLR(x)					\
+	CSR_WRITE_1(sc, RL_EECMD,			\
+		CSR_READ_1(sc, RL_EECMD) & ~x)
+
+/*
+ * Send a read command and address to the EEPROM, check for ACK.
+ */
+static void
+rl_eeprom_putbyte(struct rl_softc *sc, int addr)
+{
+	register int		d, i;
+
+	d = addr | sc->rl_eecmd_read;
+
+	/*
+	 * Feed in each bit and strobe the clock.
+	 */
+	for (i = 0x400; i; i >>= 1) {
+		if (d & i) {
+			EE_SET(RL_EE_DATAIN);
+		} else {
+			EE_CLR(RL_EE_DATAIN);
+		}
+		DELAY(100);
+		EE_SET(RL_EE_CLK);
+		DELAY(150);
+		EE_CLR(RL_EE_CLK);
+		DELAY(100);
+	}
+}
+
+/*
+ * Read a word of data stored in the EEPROM at address 'addr.'
+ */
+static void
+rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
+{
+	register int		i;
+	uint16_t		word = 0;
+
+	/* Enter EEPROM access mode. */
+	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
+
+	/*
+	 * Send address of word we want to read.
+	 */
+	rl_eeprom_putbyte(sc, addr);
+
+	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
+
+	/*
+	 * Start reading bits from EEPROM.
+	 */
+	for (i = 0x8000; i; i >>= 1) {
+		EE_SET(RL_EE_CLK);
+		DELAY(100);
+		if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
+			word |= i;
+		EE_CLR(RL_EE_CLK);
+		DELAY(100);
+	}
+
+	/* Turn off EEPROM access mode. */
+	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
+
+	*dest = word;
+}
+
+/*
+ * Read a sequence of words from the EEPROM.
+ */
+static void
+rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
+{
+	int			i;
+	uint16_t		word = 0, *ptr;
+
+	for (i = 0; i < cnt; i++) {
+		rl_eeprom_getword(sc, off + i, &word);
+		ptr = (uint16_t *)(dest + (i * 2));
+		if (swap)
+			*ptr = ntohs(word);
+		else
+			*ptr = word;
+	}
+}
+
+/*
+ * Read the MII serial port for the MII bit-bang module.
+ */
+static uint32_t
+rl_mii_bitbang_read(device_t dev)
+{
+	struct rl_softc *sc;
+	uint32_t val;
+
+	sc = device_get_softc(dev);
+
+	val = CSR_READ_1(sc, RL_MII);
+	CSR_BARRIER(sc, RL_MII, 1,
+	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
+
+	return (val);
+}
+
+/*
+ * Write the MII serial port for the MII bit-bang module.
+ */
+static void
+rl_mii_bitbang_write(device_t dev, uint32_t val)
+{
+	struct rl_softc *sc;
+
+	sc = device_get_softc(dev);
+
+	CSR_WRITE_1(sc, RL_MII, val);
+	CSR_BARRIER(sc, RL_MII, 1,
+	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
+}
+
+static int
+rl_miibus_readreg(device_t dev, int phy, int reg)
+{
+	struct rl_softc		*sc;
+	uint16_t		rl8139_reg;
+
+	sc = device_get_softc(dev);
+
+	if (sc->rl_type == RL_8139) {
+		switch (reg) {
+		case MII_BMCR:
+			rl8139_reg = RL_BMCR;
+			break;
+		case MII_BMSR:
+			rl8139_reg = RL_BMSR;
+			break;
+		case MII_ANAR:
+			rl8139_reg = RL_ANAR;
+			break;
+		case MII_ANER:
+			rl8139_reg = RL_ANER;
+			break;
+		case MII_ANLPAR:
+			rl8139_reg = RL_LPAR;
+			break;
+		case MII_PHYIDR1:
+		case MII_PHYIDR2:
+			return (0);
+		/*
+		 * Allow the rlphy driver to read the media status
+		 * register. If we have a link partner which does not
+		 * support NWAY, this is the register which will tell
+		 * us the results of parallel detection.
+		 */
+		case RL_MEDIASTAT:
+			return (CSR_READ_1(sc, RL_MEDIASTAT));
+		default:
+			device_printf(sc->rl_dev, "bad phy register\n");
+			return (0);
+		}
+		return (CSR_READ_2(sc, rl8139_reg));
+	}
+
+	return (mii_bitbang_readreg(dev, &rl_mii_bitbang_ops, phy, reg));
+}
+
+static int
+rl_miibus_writereg(device_t dev, int phy, int reg, int data)
+{
+	struct rl_softc		*sc;
+	uint16_t		rl8139_reg;
+
+	sc = device_get_softc(dev);
+
+	if (sc->rl_type == RL_8139) {
+		switch (reg) {
+		case MII_BMCR:
+			rl8139_reg = RL_BMCR;
+			break;
+		case MII_BMSR:
+			rl8139_reg = RL_BMSR;
+			break;
+		case MII_ANAR:
+			rl8139_reg = RL_ANAR;
+			break;
+		case MII_ANER:
+			rl8139_reg = RL_ANER;
+			break;
+		case MII_ANLPAR:
+			rl8139_reg = RL_LPAR;
+			break;
+		case MII_PHYIDR1:
+		case MII_PHYIDR2:
+			return (0);
+			break;
+		default:
+			device_printf(sc->rl_dev, "bad phy register\n");
+			return (0);
+		}
+		CSR_WRITE_2(sc, rl8139_reg, data);
+		return (0);
+	}
+
+	mii_bitbang_writereg(dev, &rl_mii_bitbang_ops, phy, reg, data);
+
+	return (0);
+}
+
+static void
+rl_miibus_statchg(device_t dev)
+{
+	struct rl_softc		*sc;
+	struct ifnet		*ifp;
+	struct mii_data		*mii;
+
+	sc = device_get_softc(dev);
+	mii = device_get_softc(sc->rl_miibus);
+	ifp = sc->rl_ifp;
+	if (mii == NULL || ifp == NULL ||
+	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
+		return;
+
+	sc->rl_flags &= ~RL_FLAG_LINK;
+	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
+	    (IFM_ACTIVE | IFM_AVALID)) {
+		switch (IFM_SUBTYPE(mii->mii_media_active)) {
+		case IFM_10_T:
+		case IFM_100_TX:
+			sc->rl_flags |= RL_FLAG_LINK;
+			break;
+		default:
+			break;
+		}
+	}
+	/*
+	 * RealTek controllers do not provide any interface to
+	 * Tx/Rx MACs for resolved speed, duplex and flow-control
+	 * parameters.
+	 */
+}
+
+/*
+ * Program the 64-bit multicast hash filter.
+ */
+static void
+rl_rxfilter(struct rl_softc *sc)
+{
+	struct ifnet		*ifp = sc->rl_ifp;
+	int			h = 0;
+	uint32_t		hashes[2] = { 0, 0 };
+	struct ifmultiaddr	*ifma;
+	uint32_t		rxfilt;
+
+	RL_LOCK_ASSERT(sc);
+
+	rxfilt = CSR_READ_4(sc, RL_RXCFG);
+	rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_BROAD |
+	    RL_RXCFG_RX_MULTI);
+	/* Always accept frames destined for this host. */
+	rxfilt |= RL_RXCFG_RX_INDIV;
+	/* Set capture broadcast bit to capture broadcast frames. */
+	if (ifp->if_flags & IFF_BROADCAST)
+		rxfilt |= RL_RXCFG_RX_BROAD;
+	if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
+		rxfilt |= RL_RXCFG_RX_MULTI;
+		if (ifp->if_flags & IFF_PROMISC)
+			rxfilt |= RL_RXCFG_RX_ALLPHYS;
+		hashes[0] = 0xFFFFFFFF;
+		hashes[1] = 0xFFFFFFFF;
+	} else {
+		/* Now program new ones. */
+		if_maddr_rlock(ifp);
+		TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
+			if (ifma->ifma_addr->sa_family != AF_LINK)
+				continue;
+			h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
+			    ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
+			if (h < 32)
+				hashes[0] |= (1 << h);
+			else
+				hashes[1] |= (1 << (h - 32));
+		}
+		if_maddr_runlock(ifp);
+		if (hashes[0] != 0 || hashes[1] != 0)
+			rxfilt |= RL_RXCFG_RX_MULTI;
+	}
+
+	CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
+	CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
+	CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
+}
+
+static void
+rl_reset(struct rl_softc *sc)
+{
+	register int		i;
+
+	RL_LOCK_ASSERT(sc);
+
+	CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
+
+	for (i = 0; i < RL_TIMEOUT; i++) {
+		DELAY(10);
+		if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
+			break;
+	}
+	if (i == RL_TIMEOUT)
+		device_printf(sc->rl_dev, "reset never completed!\n");
+}
+
+/*
+ * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
+ * IDs against our list and return a device name if we find a match.
+ */
+static int
+rl_probe(device_t dev)
+{
+	const struct rl_type	*t;
+	uint16_t		devid, revid, vendor;
+	int			i;
+	
+	vendor = pci_get_vendor(dev);
+	devid = pci_get_device(dev);
+	revid = pci_get_revid(dev);
+
+	if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
+		if (revid == 0x20) {
+			/* 8139C+, let re(4) take care of this device. */
+			return (ENXIO);
+		}
+	}
+	t = rl_devs;
+	for (i = 0; i < sizeof(rl_devs) / sizeof(rl_devs[0]); i++, t++) {
+		if (vendor == t->rl_vid && devid == t->rl_did) {
+			device_set_desc(dev, t->rl_name);
+			return (BUS_PROBE_DEFAULT);
+		}
+	}
+
+	return (ENXIO);
+}
+
+struct rl_dmamap_arg {
+	bus_addr_t	rl_busaddr;
+};
+
+static void
+rl_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
+{
+	struct rl_dmamap_arg	*ctx;
+
+	if (error != 0)
+		return;
+
+	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
+
+        ctx = (struct rl_dmamap_arg *)arg;
+        ctx->rl_busaddr = segs[0].ds_addr;
+}
+
+/*
+ * Attach the interface. Allocate softc structures, do ifmedia
+ * setup and ethernet/BPF attach.
+ */
+static int
+rl_attach(device_t dev)
+{
+	uint8_t			eaddr[ETHER_ADDR_LEN];
+	uint16_t		as[3];
+	struct ifnet		*ifp;
+	struct rl_softc		*sc;
+	const struct rl_type	*t;
+	struct sysctl_ctx_list	*ctx;
+	struct sysctl_oid_list	*children;
+	int			error = 0, hwrev, i, phy, pmc, rid;
+	int			prefer_iomap, unit;
+	uint16_t		rl_did = 0;
+	char			tn[32];
+
+	sc = device_get_softc(dev);
+	unit = device_get_unit(dev);
+	sc->rl_dev = dev;
+
+	sc->rl_twister_enable = 0;
+	snprintf(tn, sizeof(tn), "dev.rl.%d.twister_enable", unit);
+	TUNABLE_INT_FETCH(tn, &sc->rl_twister_enable);
+	ctx = device_get_sysctl_ctx(sc->rl_dev);
+	children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
+	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "twister_enable", CTLFLAG_RD,
+	   &sc->rl_twister_enable, 0, "");
+
+	mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
+	    MTX_DEF);
+	callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
+
+	pci_enable_busmaster(dev);
+
+
+	/*
+	 * Map control/status registers.
+	 * Default to using PIO access for this driver. On SMP systems,
+	 * there appear to be problems with memory mapped mode: it looks
+	 * like doing too many memory mapped access back to back in rapid
+	 * succession can hang the bus. I'm inclined to blame this on
+	 * crummy design/construction on the part of RealTek. Memory
+	 * mapped mode does appear to work on uniprocessor systems though.
+	 */
+	prefer_iomap = 1;
+	snprintf(tn, sizeof(tn), "dev.rl.%d.prefer_iomap", unit);
+	TUNABLE_INT_FETCH(tn, &prefer_iomap);
+	if (prefer_iomap) {
+		sc->rl_res_id = PCIR_BAR(0);
+		sc->rl_res_type = SYS_RES_IOPORT;
+		sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
+		    &sc->rl_res_id, RF_ACTIVE);
+	}
+	if (prefer_iomap == 0 || sc->rl_res == NULL) {
+		sc->rl_res_id = PCIR_BAR(1);
+		sc->rl_res_type = SYS_RES_MEMORY;
+		sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
+		    &sc->rl_res_id, RF_ACTIVE);
+	}
+	if (sc->rl_res == NULL) {
+		device_printf(dev, "couldn't map ports/memory\n");
+		error = ENXIO;
+		goto fail;
+	}
+
+#ifdef notdef
+	/*
+	 * Detect the Realtek 8139B. For some reason, this chip is very
+	 * unstable when left to autoselect the media
+	 * The best workaround is to set the device to the required
+	 * media type or to set it to the 10 Meg speed.
+	 */
+	if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
+		device_printf(dev,
+"Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
+#endif
+
+	sc->rl_btag = rman_get_bustag(sc->rl_res);
+	sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
+
+	/* Allocate interrupt */
+	rid = 0;
+	sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
+	    RF_SHAREABLE | RF_ACTIVE);
+
+	if (sc->rl_irq[0] == NULL) {
+		device_printf(dev, "couldn't map interrupt\n");
+		error = ENXIO;
+		goto fail;
+	}
+
+	sc->rl_cfg0 = RL_8139_CFG0;
+	sc->rl_cfg1 = RL_8139_CFG1;
+	sc->rl_cfg2 = 0;
+	sc->rl_cfg3 = RL_8139_CFG3;
+	sc->rl_cfg4 = RL_8139_CFG4;
+	sc->rl_cfg5 = RL_8139_CFG5;
+
+	/*
+	 * Reset the adapter. Only take the lock here as it's needed in
+	 * order to call rl_reset().
+	 */
+	RL_LOCK(sc);
+	rl_reset(sc);
+	RL_UNLOCK(sc);
+
+	sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
+	rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
+	if (rl_did != 0x8129)
+		sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
+
+	/*
+	 * Get station address from the EEPROM.
+	 */
+	rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
+	for (i = 0; i < 3; i++) {
+		eaddr[(i * 2) + 0] = as[i] & 0xff;
+		eaddr[(i * 2) + 1] = as[i] >> 8;
+	}
+
+	/*
+	 * Now read the exact device type from the EEPROM to find
+	 * out if it's an 8129 or 8139.
+	 */
+	rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
+
+	t = rl_devs;
+	sc->rl_type = 0;
+	while(t->rl_name != NULL) {
+		if (rl_did == t->rl_did) {
+			sc->rl_type = t->rl_basetype;
+			break;
+		}
+		t++;
+	}
+
+	if (sc->rl_type == 0) {
+		device_printf(dev, "unknown device ID: %x assuming 8139\n",
+		    rl_did);
+		sc->rl_type = RL_8139;
+		/*
+		 * Read RL_IDR register to get ethernet address as accessing
+		 * EEPROM may not extract correct address.
+		 */
+		for (i = 0; i < ETHER_ADDR_LEN; i++)
+			eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
+	}
+
+	if ((error = rl_dma_alloc(sc)) != 0)
+		goto fail;
+
+	ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
+	if (ifp == NULL) {
+		device_printf(dev, "can not if_alloc()\n");
+		error = ENOSPC;
+		goto fail;
+	}
+
+#define	RL_PHYAD_INTERNAL	0
+
+	/* Do MII setup */
+	phy = MII_PHY_ANY;
+	if (sc->rl_type == RL_8139)
+		phy = RL_PHYAD_INTERNAL;
+	error = mii_attach(dev, &sc->rl_miibus, ifp, rl_ifmedia_upd,
+	    rl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
+	if (error != 0) {
+		device_printf(dev, "attaching PHYs failed\n");
+		goto fail;
+	}
+
+	ifp->if_softc = sc;
+	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
+	ifp->if_mtu = ETHERMTU;
+	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+	ifp->if_ioctl = rl_ioctl;
+	ifp->if_start = rl_start;
+	ifp->if_init = rl_init;
+	ifp->if_capabilities = IFCAP_VLAN_MTU;
+	/* Check WOL for RTL8139B or newer controllers. */
+	if (sc->rl_type == RL_8139 &&
+	    pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
+		hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
+		switch (hwrev) {
+		case RL_HWREV_8139B:
+		case RL_HWREV_8130:
+		case RL_HWREV_8139C:
+		case RL_HWREV_8139D:
+		case RL_HWREV_8101:
+		case RL_HWREV_8100:
+			ifp->if_capabilities |= IFCAP_WOL;
+			/* Disable WOL. */
+			rl_clrwol(sc);
+			break;
+		default:
+			break;
+		}
+	}
+	ifp->if_capenable = ifp->if_capabilities;
+	ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST);
+#ifdef DEVICE_POLLING
+	ifp->if_capabilities |= IFCAP_POLLING;
+#endif
+	IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
+	ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
+	IFQ_SET_READY(&ifp->if_snd);
+
+	/*
+	 * Call MI attach routine.
+	 */
+	ether_ifattach(ifp, eaddr);
+
+	/* Hook interrupt last to avoid having to lock softc */
+	error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE,
+	    NULL, rl_intr, sc, &sc->rl_intrhand[0]);
+	if (error) {
+		device_printf(sc->rl_dev, "couldn't set up irq\n");
+		ether_ifdetach(ifp);
+	}
+
+fail:
+	if (error)
+		rl_detach(dev);
+
+	return (error);
+}
+
+/*
+ * Shutdown hardware and free up resources. This can be called any
+ * time after the mutex has been initialized. It is called in both
+ * the error case in attach and the normal detach case so it needs
+ * to be careful about only freeing resources that have actually been
+ * allocated.
+ */
+static int
+rl_detach(device_t dev)
+{
+	struct rl_softc		*sc;
+	struct ifnet		*ifp;
+
+	sc = device_get_softc(dev);
+	ifp = sc->rl_ifp;
+
+	KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
+
+#ifdef DEVICE_POLLING
+	if (ifp->if_capenable & IFCAP_POLLING)
+		ether_poll_deregister(ifp);
+#endif
+	/* These should only be active if attach succeeded */
+	if (device_is_attached(dev)) {
+		RL_LOCK(sc);
+		rl_stop(sc);
+		RL_UNLOCK(sc);
+		callout_drain(&sc->rl_stat_callout);
+		ether_ifdetach(ifp);
+	}
+#if 0
+	sc->suspended = 1;
+#endif
+	if (sc->rl_miibus)
+		device_delete_child(dev, sc->rl_miibus);
+	bus_generic_detach(dev);
+
+	if (sc->rl_intrhand[0])
+		bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
+	if (sc->rl_irq[0])
+		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]);
+	if (sc->rl_res)
+		bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
+		    sc->rl_res);
+
+	if (ifp)
+		if_free(ifp);
+
+	rl_dma_free(sc);
+
+	mtx_destroy(&sc->rl_mtx);
+
+	return (0);
+}
+
+static int
+rl_dma_alloc(struct rl_softc *sc)
+{
+	struct rl_dmamap_arg	ctx;
+	int			error, i;
+
+	/*
+	 * Allocate the parent bus DMA tag appropriate for PCI.
+	 */
+	error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev),	/* parent */
+	    1, 0,			/* alignment, boundary */
+	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
+	    BUS_SPACE_MAXADDR,		/* highaddr */
+	    NULL, NULL,			/* filter, filterarg */
+	    BUS_SPACE_MAXSIZE_32BIT, 0,	/* maxsize, nsegments */
+	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
+	    0,				/* flags */
+	    NULL, NULL,			/* lockfunc, lockarg */
+	    &sc->rl_parent_tag);
+	if (error) {
+                device_printf(sc->rl_dev,
+		    "failed to create parent DMA tag.\n");
+		goto fail;
+	}
+	/* Create DMA tag for Rx memory block. */
+	error = bus_dma_tag_create(sc->rl_parent_tag,	/* parent */
+	    RL_RX_8139_BUF_ALIGN, 0,	/* alignment, boundary */
+	    BUS_SPACE_MAXADDR,		/* lowaddr */
+	    BUS_SPACE_MAXADDR,		/* highaddr */
+	    NULL, NULL,			/* filter, filterarg */
+	    RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, 1,	/* maxsize,nsegments */
+	    RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ,	/* maxsegsize */
+	    0,				/* flags */
+	    NULL, NULL,			/* lockfunc, lockarg */
+	    &sc->rl_cdata.rl_rx_tag);
+	if (error) {
+                device_printf(sc->rl_dev,
+		    "failed to create Rx memory block DMA tag.\n");
+		goto fail;
+	}
+	/* Create DMA tag for Tx buffer. */
+	error = bus_dma_tag_create(sc->rl_parent_tag,	/* parent */
+	    RL_TX_8139_BUF_ALIGN, 0,	/* alignment, boundary */
+	    BUS_SPACE_MAXADDR,		/* lowaddr */
+	    BUS_SPACE_MAXADDR,		/* highaddr */
+	    NULL, NULL,			/* filter, filterarg */
+	    MCLBYTES, 1,		/* maxsize, nsegments */
+	    MCLBYTES,			/* maxsegsize */
+	    0,				/* flags */
+	    NULL, NULL,			/* lockfunc, lockarg */
+	    &sc->rl_cdata.rl_tx_tag);
+	if (error) {
+                device_printf(sc->rl_dev, "failed to create Tx DMA tag.\n");
+		goto fail;
+	}
+
+	/*
+	 * Allocate DMA'able memory and load DMA map for Rx memory block.
+	 */
+	error = bus_dmamem_alloc(sc->rl_cdata.rl_rx_tag,
+	    (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_WAITOK |
+	    BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->rl_cdata.rl_rx_dmamap);
+	if (error != 0) {
+		device_printf(sc->rl_dev,
+		    "failed to allocate Rx DMA memory block.\n");
+		goto fail;
+	}
+	ctx.rl_busaddr = 0;
+	error = bus_dmamap_load(sc->rl_cdata.rl_rx_tag,
+	    sc->rl_cdata.rl_rx_dmamap, sc->rl_cdata.rl_rx_buf,
+	    RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, rl_dmamap_cb, &ctx,
+	    BUS_DMA_NOWAIT);
+	if (error != 0 || ctx.rl_busaddr == 0) {
+		device_printf(sc->rl_dev,
+		    "could not load Rx DMA memory block.\n");
+		goto fail;
+	}
+	sc->rl_cdata.rl_rx_buf_paddr = ctx.rl_busaddr;
+
+	/* Create DMA maps for Tx buffers. */
+	for (i = 0; i < RL_TX_LIST_CNT; i++) {
+		sc->rl_cdata.rl_tx_chain[i] = NULL;
+		sc->rl_cdata.rl_tx_dmamap[i] = NULL;
+		error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 0,
+		    &sc->rl_cdata.rl_tx_dmamap[i]);
+		if (error != 0) {
+			device_printf(sc->rl_dev,
+			    "could not create Tx dmamap.\n");
+			goto fail;
+		}
+	}
+
+	/* Leave a few bytes before the start of the RX ring buffer. */
+	sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
+	sc->rl_cdata.rl_rx_buf += RL_RX_8139_BUF_RESERVE;
+
+fail:
+	return (error);
+}
+
+static void
+rl_dma_free(struct rl_softc *sc)
+{
+	int			i;
+
+	/* Rx memory block. */
+	if (sc->rl_cdata.rl_rx_tag != NULL) {
+		if (sc->rl_cdata.rl_rx_dmamap != NULL)
+			bus_dmamap_unload(sc->rl_cdata.rl_rx_tag,
+			    sc->rl_cdata.rl_rx_dmamap);
+		if (sc->rl_cdata.rl_rx_dmamap != NULL &&
+		    sc->rl_cdata.rl_rx_buf_ptr != NULL)
+			bus_dmamem_free(sc->rl_cdata.rl_rx_tag,
+			    sc->rl_cdata.rl_rx_buf_ptr,
+			    sc->rl_cdata.rl_rx_dmamap);
+		sc->rl_cdata.rl_rx_buf_ptr = NULL;
+		sc->rl_cdata.rl_rx_buf = NULL;
+		sc->rl_cdata.rl_rx_dmamap = NULL;
+		bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag);
+		sc->rl_cdata.rl_tx_tag = NULL;
+	}
+
+	/* Tx buffers. */
+	if (sc->rl_cdata.rl_tx_tag != NULL) {
+		for (i = 0; i < RL_TX_LIST_CNT; i++) {
+			if (sc->rl_cdata.rl_tx_dmamap[i] != NULL) {
+				bus_dmamap_destroy(
+				    sc->rl_cdata.rl_tx_tag,
+				    sc->rl_cdata.rl_tx_dmamap[i]);
+				sc->rl_cdata.rl_tx_dmamap[i] = NULL;
+			}
+		}
+		bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag);
+		sc->rl_cdata.rl_tx_tag = NULL;
+	}
+
+	if (sc->rl_parent_tag != NULL) {
+		bus_dma_tag_destroy(sc->rl_parent_tag);
+		sc->rl_parent_tag = NULL;
+	}
+}
+
+/*
+ * Initialize the transmit descriptors.
+ */
+static int
+rl_list_tx_init(struct rl_softc *sc)
+{
+	struct rl_chain_data	*cd;
+	int			i;
+
+	RL_LOCK_ASSERT(sc);
+
+	cd = &sc->rl_cdata;
+	for (i = 0; i < RL_TX_LIST_CNT; i++) {
+		cd->rl_tx_chain[i] = NULL;
+		CSR_WRITE_4(sc,
+		    RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
+	}
+
+	sc->rl_cdata.cur_tx = 0;
+	sc->rl_cdata.last_tx = 0;
+
+	return (0);
+}
+
+static int
+rl_list_rx_init(struct rl_softc *sc)
+{
+
+	RL_LOCK_ASSERT(sc);
+
+	bzero(sc->rl_cdata.rl_rx_buf_ptr,
+	    RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ);
+	bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, sc->rl_cdata.rl_rx_dmamap,
+	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+
+	return (0);
+}
+
+/*
+ * A frame has been uploaded: pass the resulting mbuf chain up to
+ * the higher level protocols.
+ *
+ * You know there's something wrong with a PCI bus-master chip design
+ * when you have to use m_devget().
+ *
+ * The receive operation is badly documented in the datasheet, so I'll
+ * attempt to document it here. The driver provides a buffer area and
+ * places its base address in the RX buffer start address register.
+ * The chip then begins copying frames into the RX buffer. Each frame
+ * is preceded by a 32-bit RX status word which specifies the length
+ * of the frame and certain other status bits. Each frame (starting with
+ * the status word) is also 32-bit aligned. The frame length is in the
+ * first 16 bits of the status word; the lower 15 bits correspond with
+ * the 'rx status register' mentioned in the datasheet.
+ *
+ * Note: to make the Alpha happy, the frame payload needs to be aligned
+ * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
+ * as the offset argument to m_devget().
+ */
+static int
+rl_rxeof(struct rl_softc *sc)
+{
+	struct mbuf		*m;
+	struct ifnet		*ifp = sc->rl_ifp;
+	uint8_t			*rxbufpos;
+	int			total_len = 0;
+	int			wrap = 0;
+	int			rx_npkts = 0;
+	uint32_t		rxstat;
+	uint16_t		cur_rx;
+	uint16_t		limit;
+	uint16_t		max_bytes, rx_bytes = 0;
+
+	RL_LOCK_ASSERT(sc);
+
+	bus_dmamap_sync(sc->rl_cdata.rl_rx_tag, sc->rl_cdata.rl_rx_dmamap,
+	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
+
+	cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
+
+	/* Do not try to read past this point. */
+	limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
+
+	if (limit < cur_rx)
+		max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
+	else
+		max_bytes = limit - cur_rx;
+
+	while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
+#ifdef DEVICE_POLLING
+		if (ifp->if_capenable & IFCAP_POLLING) {
+			if (sc->rxcycles <= 0)
+				break;
+			sc->rxcycles--;
+		}
+#endif
+		rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
+		rxstat = le32toh(*(uint32_t *)rxbufpos);
+
+		/*
+		 * Here's a totally undocumented fact for you. When the
+		 * RealTek chip is in the process of copying a packet into
+		 * RAM for you, the length will be 0xfff0. If you spot a
+		 * packet header with this value, you need to stop. The
+		 * datasheet makes absolutely no mention of this and
+		 * RealTek should be shot for this.
+		 */
+		total_len = rxstat >> 16;
+		if (total_len == RL_RXSTAT_UNFINISHED)
+			break;
+
+		if (!(rxstat & RL_RXSTAT_RXOK) ||
+		    total_len < ETHER_MIN_LEN ||
+		    total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) {
+			ifp->if_ierrors++;
+			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+			rl_init_locked(sc);
+			return (rx_npkts);
+		}
+
+		/* No errors; receive the packet. */
+		rx_bytes += total_len + 4;
+
+		/*
+		 * XXX The RealTek chip includes the CRC with every
+		 * received frame, and there's no way to turn this
+		 * behavior off (at least, I can't find anything in
+		 * the manual that explains how to do it) so we have
+		 * to trim off the CRC manually.
+		 */
+		total_len -= ETHER_CRC_LEN;
+
+		/*
+		 * Avoid trying to read more bytes than we know
+		 * the chip has prepared for us.
+		 */
+		if (rx_bytes > max_bytes)
+			break;
+
+		rxbufpos = sc->rl_cdata.rl_rx_buf +
+			((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
+		if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
+			rxbufpos = sc->rl_cdata.rl_rx_buf;
+
+		wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
+		if (total_len > wrap) {
+			m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
+			    NULL);
+			if (m != NULL)
+				m_copyback(m, wrap, total_len - wrap,
+					sc->rl_cdata.rl_rx_buf);
+			cur_rx = (total_len - wrap + ETHER_CRC_LEN);
+		} else {
+			m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
+			    NULL);
+			cur_rx += total_len + 4 + ETHER_CRC_LEN;
+		}
+
+		/* Round up to 32-bit boundary. */
+		cur_rx = (cur_rx + 3) & ~3;
+		CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
+
+		if (m == NULL) {
+			ifp->if_iqdrops++;
+			continue;
+		}
+
+		ifp->if_ipackets++;
+		RL_UNLOCK(sc);
+		(*ifp->if_input)(ifp, m);
+		RL_LOCK(sc);
+		rx_npkts++;
+	}
+
+	/* No need to sync Rx memory block as we didn't modify it. */
+	return (rx_npkts);
+}
+
+/*
+ * A frame was downloaded to the chip. It's safe for us to clean up
+ * the list buffers.
+ */
+static void
+rl_txeof(struct rl_softc *sc)
+{
+	struct ifnet		*ifp = sc->rl_ifp;
+	uint32_t		txstat;
+
+	RL_LOCK_ASSERT(sc);
+
+	/*
+	 * Go through our tx list and free mbufs for those
+	 * frames that have been uploaded.
+	 */
+	do {
+		if (RL_LAST_TXMBUF(sc) == NULL)
+			break;
+		txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
+		if (!(txstat & (RL_TXSTAT_TX_OK|
+		    RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
+			break;
+
+		ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
+
+		bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc),
+		    BUS_DMASYNC_POSTWRITE);
+		bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc));
+		m_freem(RL_LAST_TXMBUF(sc));
+		RL_LAST_TXMBUF(sc) = NULL;
+		/*
+		 * If there was a transmit underrun, bump the TX threshold.
+		 * Make sure not to overflow the 63 * 32byte we can address
+		 * with the 6 available bit.
+		 */
+		if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
+		    (sc->rl_txthresh < 2016))
+			sc->rl_txthresh += 32;
+		if (txstat & RL_TXSTAT_TX_OK)
+			ifp->if_opackets++;
+		else {
+			int			oldthresh;
+			ifp->if_oerrors++;
+			if ((txstat & RL_TXSTAT_TXABRT) ||
+			    (txstat & RL_TXSTAT_OUTOFWIN))
+				CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
+			oldthresh = sc->rl_txthresh;
+			/* error recovery */
+			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+			rl_init_locked(sc);
+			/* restore original threshold */
+			sc->rl_txthresh = oldthresh;
+			return;
+		}
+		RL_INC(sc->rl_cdata.last_tx);
+		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+	} while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
+
+	if (RL_LAST_TXMBUF(sc) == NULL)
+		sc->rl_watchdog_timer = 0;
+}
+
+static void
+rl_twister_update(struct rl_softc *sc)
+{
+	uint16_t linktest;
+	/*
+	 * Table provided by RealTek (Kinston <shangh@realtek.com.tw>) for
+	 * Linux driver.  Values undocumented otherwise.
+	 */
+	static const uint32_t param[4][4] = {
+		{0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
+		{0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
+		{0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
+		{0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
+	};
+
+	/*
+	 * Tune the so-called twister registers of the RTL8139.  These
+	 * are used to compensate for impedance mismatches.  The
+	 * method for tuning these registers is undocumented and the
+	 * following procedure is collected from public sources.
+	 */
+	switch (sc->rl_twister)
+	{
+	case CHK_LINK:
+		/*
+		 * If we have a sufficient link, then we can proceed in
+		 * the state machine to the next stage.  If not, then
+		 * disable further tuning after writing sane defaults.
+		 */
+		if (CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_LINK_OK) {
+			CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD);
+			sc->rl_twister = FIND_ROW;
+		} else {
+			CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD);
+			CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
+			CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
+			CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
+			sc->rl_twister = DONE;
+		}
+		break;
+	case FIND_ROW:
+		/*
+		 * Read how long it took to see the echo to find the tuning
+		 * row to use.
+		 */
+		linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
+		if (linktest == RL_CSCFG_ROW3)
+			sc->rl_twist_row = 3;
+		else if (linktest == RL_CSCFG_ROW2)
+			sc->rl_twist_row = 2;
+		else if (linktest == RL_CSCFG_ROW1)
+			sc->rl_twist_row = 1;
+		else
+			sc->rl_twist_row = 0;
+		sc->rl_twist_col = 0;
+		sc->rl_twister = SET_PARAM;
+		break;
+	case SET_PARAM:
+		if (sc->rl_twist_col == 0)
+			CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
+		CSR_WRITE_4(sc, RL_PARA7C,
+		    param[sc->rl_twist_row][sc->rl_twist_col]);
+		if (++sc->rl_twist_col == 4) {
+			if (sc->rl_twist_row == 3)
+				sc->rl_twister = RECHK_LONG;
+			else
+				sc->rl_twister = DONE;
+		}
+		break;
+	case RECHK_LONG:
+		/*
+		 * For long cables, we have to double check to make sure we
+		 * don't mistune.
+		 */
+		linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
+		if (linktest == RL_CSCFG_ROW3)
+			sc->rl_twister = DONE;
+		else {
+			CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_RETUNE);
+			sc->rl_twister = RETUNE;
+		}
+		break;
+	case RETUNE:
+		/* Retune for a shorter cable (try column 2) */
+		CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
+		CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
+		CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
+		CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
+		sc->rl_twist_row--;
+		sc->rl_twist_col = 0;
+		sc->rl_twister = SET_PARAM;
+		break;
+
+	case DONE:
+		break;
+	}
+	
+}
+
+static void
+rl_tick(void *xsc)
+{
+	struct rl_softc		*sc = xsc;
+	struct mii_data		*mii;
+	int ticks;
+
+	RL_LOCK_ASSERT(sc);
+	/*
+	 * If we're doing the twister cable calibration, then we need to defer
+	 * watchdog timeouts.  This is a no-op in normal operations, but
+	 * can falsely trigger when the cable calibration takes a while and
+	 * there was traffic ready to go when rl was started.
+	 *
+	 * We don't defer mii_tick since that updates the mii status, which
+	 * helps the twister process, at least according to similar patches
+	 * for the Linux driver I found online while doing the fixes.  Worst
+	 * case is a few extra mii reads during calibration.
+	 */
+	mii = device_get_softc(sc->rl_miibus);
+	mii_tick(mii);
+	if ((sc->rl_flags & RL_FLAG_LINK) == 0)
+		rl_miibus_statchg(sc->rl_dev);
+	if (sc->rl_twister_enable) {
+		if (sc->rl_twister == DONE)
+			rl_watchdog(sc);
+		else
+			rl_twister_update(sc);
+		if (sc->rl_twister == DONE)
+			ticks = hz;
+		else
+			ticks = hz / 10;
+	} else {
+		rl_watchdog(sc);
+		ticks = hz;
+	}
+
+	callout_reset(&sc->rl_stat_callout, ticks, rl_tick, sc);
+}
+
+#ifdef DEVICE_POLLING
+static int
+rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
+{
+	struct rl_softc *sc = ifp->if_softc;
+	int rx_npkts = 0;
+
+	RL_LOCK(sc);
+	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
+		rx_npkts = rl_poll_locked(ifp, cmd, count);
+	RL_UNLOCK(sc);
+	return (rx_npkts);
+}
+
+static int
+rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
+{
+	struct rl_softc *sc = ifp->if_softc;
+	int rx_npkts;
+
+	RL_LOCK_ASSERT(sc);
+
+	sc->rxcycles = count;
+	rx_npkts = rl_rxeof(sc);
+	rl_txeof(sc);
+
+	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
+		rl_start_locked(ifp);
+
+	if (cmd == POLL_AND_CHECK_STATUS) {
+		uint16_t	status;
+
+		/* We should also check the status register. */
+		status = CSR_READ_2(sc, RL_ISR);
+		if (status == 0xffff)
+			return (rx_npkts);
+		if (status != 0)
+			CSR_WRITE_2(sc, RL_ISR, status);
+
+		/* XXX We should check behaviour on receiver stalls. */
+
+		if (status & RL_ISR_SYSTEM_ERR) {
+			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+			rl_init_locked(sc);
+		}
+	}
+	return (rx_npkts);
+}
+#endif /* DEVICE_POLLING */
+
+static void
+rl_intr(void *arg)
+{
+	struct rl_softc		*sc = arg;
+	struct ifnet		*ifp = sc->rl_ifp;
+	uint16_t		status;
+	int			count;
+
+	RL_LOCK(sc);
+
+	if (sc->suspended)
+		goto done_locked;
+
+#ifdef DEVICE_POLLING
+	if  (ifp->if_capenable & IFCAP_POLLING)
+		goto done_locked;
+#endif
+
+	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
+		goto done_locked2;
+	status = CSR_READ_2(sc, RL_ISR);
+	if (status == 0xffff || (status & RL_INTRS) == 0)
+		goto done_locked;
+	/*
+	 * Ours, disable further interrupts.
+	 */
+	CSR_WRITE_2(sc, RL_IMR, 0);
+	for (count = 16; count > 0; count--) {
+		CSR_WRITE_2(sc, RL_ISR, status);
+		if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
+			if (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR))
+				rl_rxeof(sc);
+			if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR))
+				rl_txeof(sc);
+			if (status & RL_ISR_SYSTEM_ERR) {
+				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+				rl_init_locked(sc);
+				RL_UNLOCK(sc);
+				return;
+			}
+		}
+		status = CSR_READ_2(sc, RL_ISR);
+		/* If the card has gone away, the read returns 0xffff. */
+		if (status == 0xffff || (status & RL_INTRS) == 0)
+			break;
+	}
+
+	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
+		rl_start_locked(ifp);
+
+done_locked2:
+	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
+		CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
+done_locked:
+	RL_UNLOCK(sc);
+}
+
+/*
+ * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
+ * pointers to the fragment pointers.
+ */
+static int
+rl_encap(struct rl_softc *sc, struct mbuf **m_head)
+{
+	struct mbuf		*m;
+	bus_dma_segment_t	txsegs[1];
+	int			error, nsegs, padlen;
+
+	RL_LOCK_ASSERT(sc);
+
+	m = *m_head;
+	padlen = 0;
+	/*
+	 * Hardware doesn't auto-pad, so we have to make sure
+	 * pad short frames out to the minimum frame length.
+	 */
+	if (m->m_pkthdr.len < RL_MIN_FRAMELEN)
+		padlen = RL_MIN_FRAMELEN - m->m_pkthdr.len;
+	/*
+	 * The RealTek is brain damaged and wants longword-aligned
+	 * TX buffers, plus we can only have one fragment buffer
+	 * per packet. We have to copy pretty much all the time.
+	 */
+	if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0 ||
+	    (padlen > 0 && M_TRAILINGSPACE(m) < padlen)) {
+		m = m_defrag(*m_head, M_DONTWAIT);
+		if (m == NULL) {
+			m_freem(*m_head);
+			*m_head = NULL;
+			return (ENOMEM);
+		}
+	}
+	*m_head = m;
+
+	if (padlen > 0) {
+		/*
+		 * Make security-conscious people happy: zero out the
+		 * bytes in the pad area, since we don't know what
+		 * this mbuf cluster buffer's previous user might
+		 * have left in it.
+		 */
+		bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
+		m->m_pkthdr.len += padlen;
+		m->m_len = m->m_pkthdr.len;
+	}
+
+	error = bus_dmamap_load_mbuf_sg(sc->rl_cdata.rl_tx_tag,
+	    RL_CUR_DMAMAP(sc), m, txsegs, &nsegs, 0);
+	if (error != 0)
+		return (error);
+	if (nsegs == 0) {
+		m_freem(*m_head);
+		*m_head = NULL;
+		return (EIO);
+	}
+
+	RL_CUR_TXMBUF(sc) = m;
+	bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc),
+	    BUS_DMASYNC_PREWRITE);
+	CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), RL_ADDR_LO(txsegs[0].ds_addr));
+
+	return (0);
+}
+
+/*
+ * Main transmit routine.
+ */
+static void
+rl_start(struct ifnet *ifp)
+{
+	struct rl_softc		*sc = ifp->if_softc;
+
+	RL_LOCK(sc);
+	rl_start_locked(ifp);
+	RL_UNLOCK(sc);
+}
+
+static void
+rl_start_locked(struct ifnet *ifp)
+{
+	struct rl_softc		*sc = ifp->if_softc;
+	struct mbuf		*m_head = NULL;
+
+	RL_LOCK_ASSERT(sc);
+
+	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
+	    IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
+		return;
+
+	while (RL_CUR_TXMBUF(sc) == NULL) {
+
+		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
+
+		if (m_head == NULL)
+			break;
+
+		if (rl_encap(sc, &m_head)) {
+			if (m_head == NULL)
+				break;
+			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
+			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+			break;
+		}
+
+		/* Pass a copy of this mbuf chain to the bpf subsystem. */
+		BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
+
+		/* Transmit the frame. */
+		CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
+		    RL_TXTHRESH(sc->rl_txthresh) |
+		    RL_CUR_TXMBUF(sc)->m_pkthdr.len);
+
+		RL_INC(sc->rl_cdata.cur_tx);
+
+		/* Set a timeout in case the chip goes out to lunch. */
+		sc->rl_watchdog_timer = 5;
+	}
+
+	/*
+	 * We broke out of the loop because all our TX slots are
+	 * full. Mark the NIC as busy until it drains some of the
+	 * packets from the queue.
+	 */
+	if (RL_CUR_TXMBUF(sc) != NULL)
+		ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+}
+
+static void
+rl_init(void *xsc)
+{
+	struct rl_softc		*sc = xsc;
+
+	RL_LOCK(sc);
+	rl_init_locked(sc);
+	RL_UNLOCK(sc);
+}
+
+static void
+rl_init_locked(struct rl_softc *sc)
+{
+	struct ifnet		*ifp = sc->rl_ifp;
+	struct mii_data		*mii;
+	uint32_t		eaddr[2];
+
+	RL_LOCK_ASSERT(sc);
+
+	mii = device_get_softc(sc->rl_miibus);
+
+	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
+		return;
+
+	/*
+	 * Cancel pending I/O and free all RX/TX buffers.
+	 */
+	rl_stop(sc);
+
+	rl_reset(sc);
+	if (sc->rl_twister_enable) {
+		/*
+		 * Reset twister register tuning state.  The twister
+		 * registers and their tuning are undocumented, but
+		 * are necessary to cope with bad links.  rl_twister =
+		 * DONE here will disable this entirely.
+		 */
+		sc->rl_twister = CHK_LINK;
+	}
+
+	/*
+	 * Init our MAC address.  Even though the chipset
+	 * documentation doesn't mention it, we need to enter "Config
+	 * register write enable" mode to modify the ID registers.
+	 */
+	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
+	bzero(eaddr, sizeof(eaddr));
+	bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN);
+	CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]);
+	CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]);
+	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
+
+	/* Init the RX memory block pointer register. */
+	CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr +
+	    RL_RX_8139_BUF_RESERVE);
+	/* Init TX descriptors. */
+	rl_list_tx_init(sc);
+	/* Init Rx memory block. */
+	rl_list_rx_init(sc);
+
+	/*
+	 * Enable transmit and receive.
+	 */
+	CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
+
+	/*
+	 * Set the initial TX and RX configuration.
+	 */
+	CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
+	CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
+
+	/* Set RX filter. */
+	rl_rxfilter(sc);
+
+#ifdef DEVICE_POLLING
+	/* Disable interrupts if we are polling. */
+	if (ifp->if_capenable & IFCAP_POLLING)
+		CSR_WRITE_2(sc, RL_IMR, 0);
+	else
+#endif
+	/* Enable interrupts. */
+	CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
+
+	/* Set initial TX threshold */
+	sc->rl_txthresh = RL_TX_THRESH_INIT;
+
+	/* Start RX/TX process. */
+	CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
+
+	/* Enable receiver and transmitter. */
+	CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
+
+	sc->rl_flags &= ~RL_FLAG_LINK;
+	mii_mediachg(mii);
+
+	CSR_WRITE_1(sc, sc->rl_cfg1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
+
+	ifp->if_drv_flags |= IFF_DRV_RUNNING;
+	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+
+	callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
+}
+
+/*
+ * Set media options.
+ */
+static int
+rl_ifmedia_upd(struct ifnet *ifp)
+{
+	struct rl_softc		*sc = ifp->if_softc;
+	struct mii_data		*mii;
+
+	mii = device_get_softc(sc->rl_miibus);
+
+	RL_LOCK(sc);
+	mii_mediachg(mii);
+	RL_UNLOCK(sc);
+
+	return (0);
+}
+
+/*
+ * Report current media status.
+ */
+static void
+rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
+	struct rl_softc		*sc = ifp->if_softc;
+	struct mii_data		*mii;
+
+	mii = device_get_softc(sc->rl_miibus);
+
+	RL_LOCK(sc);
+	mii_pollstat(mii);
+	ifmr->ifm_active = mii->mii_media_active;
+	ifmr->ifm_status = mii->mii_media_status;
+	RL_UNLOCK(sc);
+}
+
+static int
+rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
+{
+	struct ifreq		*ifr = (struct ifreq *)data;
+	struct mii_data		*mii;
+	struct rl_softc		*sc = ifp->if_softc;
+	int			error = 0, mask;
+
+	switch (command) {
+	case SIOCSIFFLAGS:
+		RL_LOCK(sc);
+		if (ifp->if_flags & IFF_UP) {
+			if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
+			    ((ifp->if_flags ^ sc->rl_if_flags) &
+                            (IFF_PROMISC | IFF_ALLMULTI)))
+				rl_rxfilter(sc);
+                        else
+				rl_init_locked(sc);
+                } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
+			rl_stop(sc);
+		sc->rl_if_flags = ifp->if_flags;
+		RL_UNLOCK(sc);
+		break;
+	case SIOCADDMULTI:
+	case SIOCDELMULTI:
+		RL_LOCK(sc);
+		rl_rxfilter(sc);
+		RL_UNLOCK(sc);
+		break;
+	case SIOCGIFMEDIA:
+	case SIOCSIFMEDIA:
+		mii = device_get_softc(sc->rl_miibus);
+		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
+		break;
+	case SIOCSIFCAP:
+		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
+#ifdef DEVICE_POLLING
+		if (ifr->ifr_reqcap & IFCAP_POLLING &&
+		    !(ifp->if_capenable & IFCAP_POLLING)) {
+			error = ether_poll_register(rl_poll, ifp);
+			if (error)
+				return(error);
+			RL_LOCK(sc);
+			/* Disable interrupts */
+			CSR_WRITE_2(sc, RL_IMR, 0x0000);
+			ifp->if_capenable |= IFCAP_POLLING;
+			RL_UNLOCK(sc);
+			return (error);
+			
+		}
+		if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
+		    ifp->if_capenable & IFCAP_POLLING) {
+			error = ether_poll_deregister(ifp);
+			/* Enable interrupts. */
+			RL_LOCK(sc);
+			CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
+			ifp->if_capenable &= ~IFCAP_POLLING;
+			RL_UNLOCK(sc);
+			return (error);
+		}
+#endif /* DEVICE_POLLING */
+		if ((mask & IFCAP_WOL) != 0 &&
+		    (ifp->if_capabilities & IFCAP_WOL) != 0) {
+			if ((mask & IFCAP_WOL_UCAST) != 0)
+				ifp->if_capenable ^= IFCAP_WOL_UCAST;
+			if ((mask & IFCAP_WOL_MCAST) != 0)
+				ifp->if_capenable ^= IFCAP_WOL_MCAST;
+			if ((mask & IFCAP_WOL_MAGIC) != 0)
+				ifp->if_capenable ^= IFCAP_WOL_MAGIC;
+		}
+		break;
+	default:
+		error = ether_ioctl(ifp, command, data);
+		break;
+	}
+
+	return (error);
+}
+
+static void
+rl_watchdog(struct rl_softc *sc)
+{
+
+	RL_LOCK_ASSERT(sc);
+
+	if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0)
+		return;
+
+	device_printf(sc->rl_dev, "watchdog timeout\n");
+	sc->rl_ifp->if_oerrors++;
+
+	rl_txeof(sc);
+	rl_rxeof(sc);
+	sc->rl_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+	rl_init_locked(sc);
+}
+
+/*
+ * Stop the adapter and free any mbufs allocated to the
+ * RX and TX lists.
+ */
+static void
+rl_stop(struct rl_softc *sc)
+{
+	register int		i;
+	struct ifnet		*ifp = sc->rl_ifp;
+
+	RL_LOCK_ASSERT(sc);
+
+	sc->rl_watchdog_timer = 0;
+	callout_stop(&sc->rl_stat_callout);
+	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
+	sc->rl_flags &= ~RL_FLAG_LINK;
+
+	CSR_WRITE_1(sc, RL_COMMAND, 0x00);
+	CSR_WRITE_2(sc, RL_IMR, 0x0000);
+	for (i = 0; i < RL_TIMEOUT; i++) {
+		DELAY(10);
+		if ((CSR_READ_1(sc, RL_COMMAND) &
+		    (RL_CMD_RX_ENB | RL_CMD_TX_ENB)) == 0)
+			break;
+	}
+	if (i == RL_TIMEOUT)
+		device_printf(sc->rl_dev, "Unable to stop Tx/Rx MAC\n");
+
+	/*
+	 * Free the TX list buffers.
+	 */
+	for (i = 0; i < RL_TX_LIST_CNT; i++) {
+		if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
+			if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
+				bus_dmamap_sync(sc->rl_cdata.rl_tx_tag,
+				    sc->rl_cdata.rl_tx_dmamap[i],
+				    BUS_DMASYNC_POSTWRITE);
+				bus_dmamap_unload(sc->rl_cdata.rl_tx_tag,
+				    sc->rl_cdata.rl_tx_dmamap[i]);
+				m_freem(sc->rl_cdata.rl_tx_chain[i]);
+				sc->rl_cdata.rl_tx_chain[i] = NULL;
+			}
+			CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
+			    0x0000000);
+		}
+	}
+}
+
+/*
+ * Device suspend routine.  Stop the interface and save some PCI
+ * settings in case the BIOS doesn't restore them properly on
+ * resume.
+ */
+static int
+rl_suspend(device_t dev)
+{
+	struct rl_softc		*sc;
+
+	sc = device_get_softc(dev);
+
+	RL_LOCK(sc);
+	rl_stop(sc);
+	rl_setwol(sc);
+	sc->suspended = 1;
+	RL_UNLOCK(sc);
+
+	return (0);
+}
+
+/*
+ * Device resume routine.  Restore some PCI settings in case the BIOS
+ * doesn't, re-enable busmastering, and restart the interface if
+ * appropriate.
+ */
+static int
+rl_resume(device_t dev)
+{
+	struct rl_softc		*sc;
+	struct ifnet		*ifp;
+	int			pmc;
+	uint16_t		pmstat;
+
+	sc = device_get_softc(dev);
+	ifp = sc->rl_ifp;
+
+	RL_LOCK(sc);
+
+	if ((ifp->if_capabilities & IFCAP_WOL) != 0 &&
+	    pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
+		/* Disable PME and clear PME status. */
+		pmstat = pci_read_config(sc->rl_dev,
+		    pmc + PCIR_POWER_STATUS, 2);
+		if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
+			pmstat &= ~PCIM_PSTAT_PMEENABLE;
+			pci_write_config(sc->rl_dev,
+			    pmc + PCIR_POWER_STATUS, pmstat, 2);
+		}
+		/*
+		 * Clear WOL matching such that normal Rx filtering
+		 * wouldn't interfere with WOL patterns.
+		 */
+		rl_clrwol(sc);
+	}
+
+	/* reinitialize interface if necessary */
+	if (ifp->if_flags & IFF_UP)
+		rl_init_locked(sc);
+
+	sc->suspended = 0;
+
+	RL_UNLOCK(sc);
+
+	return (0);
+}
+
+/*
+ * Stop all chip I/O so that the kernel's probe routines don't
+ * get confused by errant DMAs when rebooting.
+ */
+static int
+rl_shutdown(device_t dev)
+{
+	struct rl_softc		*sc;
+
+	sc = device_get_softc(dev);
+
+	RL_LOCK(sc);
+	rl_stop(sc);
+	/*
+	 * Mark interface as down since otherwise we will panic if
+	 * interrupt comes in later on, which can happen in some
+	 * cases.
+	 */
+	sc->rl_ifp->if_flags &= ~IFF_UP;
+	rl_setwol(sc);
+	RL_UNLOCK(sc);
+
+	return (0);
+}
+
+static void
+rl_setwol(struct rl_softc *sc)
+{
+	struct ifnet		*ifp;
+	int			pmc;
+	uint16_t		pmstat;
+	uint8_t			v;
+
+	RL_LOCK_ASSERT(sc);
+
+	ifp = sc->rl_ifp;
+	if ((ifp->if_capabilities & IFCAP_WOL) == 0)
+		return;
+	if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
+		return;
+
+	/* Enable config register write. */
+	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
+
+	/* Enable PME. */
+	v = CSR_READ_1(sc, sc->rl_cfg1);
+	v &= ~RL_CFG1_PME;
+	if ((ifp->if_capenable & IFCAP_WOL) != 0)
+		v |= RL_CFG1_PME;
+	CSR_WRITE_1(sc, sc->rl_cfg1, v);
+
+	v = CSR_READ_1(sc, sc->rl_cfg3);
+	v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
+	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
+		v |= RL_CFG3_WOL_MAGIC;
+	CSR_WRITE_1(sc, sc->rl_cfg3, v);
+
+	v = CSR_READ_1(sc, sc->rl_cfg5);
+	v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
+	v &= ~RL_CFG5_WOL_LANWAKE;
+	if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
+		v |= RL_CFG5_WOL_UCAST;
+	if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
+		v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
+	if ((ifp->if_capenable & IFCAP_WOL) != 0)
+		v |= RL_CFG5_WOL_LANWAKE;
+	CSR_WRITE_1(sc, sc->rl_cfg5, v);
+
+	/* Config register write done. */
+	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
+
+	/* Request PME if WOL is requested. */
+	pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
+	pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
+	if ((ifp->if_capenable & IFCAP_WOL) != 0)
+		pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
+	pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
+}
+
+static void
+rl_clrwol(struct rl_softc *sc)
+{
+	struct ifnet		*ifp;
+	uint8_t			v;
+
+	ifp = sc->rl_ifp;
+	if ((ifp->if_capabilities & IFCAP_WOL) == 0)
+		return;
+
+	/* Enable config register write. */
+	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
+
+	v = CSR_READ_1(sc, sc->rl_cfg3);
+	v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
+	CSR_WRITE_1(sc, sc->rl_cfg3, v);
+
+	/* Config register write done. */
+	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
+
+	v = CSR_READ_1(sc, sc->rl_cfg5);
+	v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
+	v &= ~RL_CFG5_WOL_LANWAKE;
+	CSR_WRITE_1(sc, sc->rl_cfg5, v);
+}

Property changes on: stable/9/sys/dev/rl/if_rl.c
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+FreeBSD=%H
\ No newline at end of property
Index: stable/9/sys/dev/rl/if_rlreg.h
===================================================================
--- stable/9/sys/dev/rl/if_rlreg.h	(nonexistent)
+++ stable/9/sys/dev/rl/if_rlreg.h	(revision 292781)
@@ -0,0 +1,1160 @@
+/*-
+ * Copyright (c) 1997, 1998-2003
+ *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ * RealTek 8129/8139 register offsets
+ */
+#define	RL_IDR0		0x0000		/* ID register 0 (station addr) */
+#define	RL_IDR1		0x0001		/* Must use 32-bit accesses (?) */
+#define	RL_IDR2		0x0002
+#define	RL_IDR3		0x0003
+#define	RL_IDR4		0x0004
+#define	RL_IDR5		0x0005
+					/* 0006-0007 reserved */
+#define	RL_MAR0		0x0008		/* Multicast hash table */
+#define	RL_MAR1		0x0009
+#define	RL_MAR2		0x000A
+#define	RL_MAR3		0x000B
+#define	RL_MAR4		0x000C
+#define	RL_MAR5		0x000D
+#define	RL_MAR6		0x000E
+#define	RL_MAR7		0x000F
+
+#define	RL_TXSTAT0	0x0010		/* status of TX descriptor 0 */
+#define	RL_TXSTAT1	0x0014		/* status of TX descriptor 1 */
+#define	RL_TXSTAT2	0x0018		/* status of TX descriptor 2 */
+#define	RL_TXSTAT3	0x001C		/* status of TX descriptor 3 */
+
+#define	RL_TXADDR0	0x0020		/* address of TX descriptor 0 */
+#define	RL_TXADDR1	0x0024		/* address of TX descriptor 1 */
+#define	RL_TXADDR2	0x0028		/* address of TX descriptor 2 */
+#define	RL_TXADDR3	0x002C		/* address of TX descriptor 3 */
+
+#define	RL_RXADDR		0x0030	/* RX ring start address */
+#define	RL_RX_EARLY_BYTES	0x0034	/* RX early byte count */
+#define	RL_RX_EARLY_STAT	0x0036	/* RX early status */
+#define	RL_COMMAND	0x0037		/* command register */
+#define	RL_CURRXADDR	0x0038		/* current address of packet read */
+#define	RL_CURRXBUF	0x003A		/* current RX buffer address */
+#define	RL_IMR		0x003C		/* interrupt mask register */
+#define	RL_ISR		0x003E		/* interrupt status register */
+#define	RL_TXCFG	0x0040		/* transmit config */
+#define	RL_RXCFG	0x0044		/* receive config */
+#define	RL_TIMERCNT	0x0048		/* timer count register */
+#define	RL_MISSEDPKT	0x004C		/* missed packet counter */
+#define	RL_EECMD	0x0050		/* EEPROM command register */
+
+/* RTL8139/RTL8139C+ only */
+#define	RL_8139_CFG0	0x0051		/* config register #0 */
+#define	RL_8139_CFG1	0x0052		/* config register #1 */
+#define	RL_8139_CFG3	0x0059		/* config register #3 */
+#define	RL_8139_CFG4	0x005A		/* config register #4 */
+#define	RL_8139_CFG5	0x00D8		/* config register #5 */
+
+#define	RL_CFG0		0x0051		/* config register #0 */
+#define	RL_CFG1		0x0052		/* config register #1 */
+#define	RL_CFG2		0x0053		/* config register #2 */
+#define	RL_CFG3		0x0054		/* config register #3 */
+#define	RL_CFG4		0x0055		/* config register #4 */
+#define	RL_CFG5		0x0056		/* config register #5 */
+					/* 0057 reserved */
+#define	RL_MEDIASTAT	0x0058		/* media status register (8139) */
+					/* 0059-005A reserved */
+#define	RL_MII		0x005A		/* 8129 chip only */
+#define	RL_HALTCLK	0x005B
+#define	RL_MULTIINTR	0x005C		/* multiple interrupt */
+#define	RL_PCIREV	0x005E		/* PCI revision value */
+					/* 005F reserved */
+#define	RL_TXSTAT_ALL	0x0060		/* TX status of all descriptors */
+
+/* Direct PHY access registers only available on 8139 */
+#define	RL_BMCR		0x0062		/* PHY basic mode control */
+#define	RL_BMSR		0x0064		/* PHY basic mode status */
+#define	RL_ANAR		0x0066		/* PHY autoneg advert */
+#define	RL_LPAR		0x0068		/* PHY link partner ability */
+#define	RL_ANER		0x006A		/* PHY autoneg expansion */
+
+#define	RL_DISCCNT	0x006C		/* disconnect counter */
+#define	RL_FALSECAR	0x006E		/* false carrier counter */
+#define	RL_NWAYTST	0x0070		/* NWAY test register */
+#define	RL_RX_ER	0x0072		/* RX_ER counter */
+#define	RL_CSCFG	0x0074		/* CS configuration register */
+
+/*
+ * When operating in special C+ mode, some of the registers in an
+ * 8139C+ chip have different definitions. These are also used for
+ * the 8169 gigE chip.
+ */
+#define	RL_DUMPSTATS_LO		0x0010	/* counter dump command register */
+#define	RL_DUMPSTATS_HI		0x0014	/* counter dump command register */
+#define	RL_TXLIST_ADDR_LO	0x0020	/* 64 bits, 256 byte alignment */
+#define	RL_TXLIST_ADDR_HI	0x0024	/* 64 bits, 256 byte alignment */
+#define	RL_TXLIST_ADDR_HPRIO_LO	0x0028	/* 64 bits, 256 byte alignment */
+#define	RL_TXLIST_ADDR_HPRIO_HI	0x002C	/* 64 bits, 256 byte alignment */
+#define	RL_CFG2			0x0053
+#define	RL_TIMERINT		0x0054	/* interrupt on timer expire */
+#define	RL_TXSTART		0x00D9	/* 8 bits */
+#define	RL_CPLUS_CMD		0x00E0	/* 16 bits */
+#define	RL_RXLIST_ADDR_LO	0x00E4	/* 64 bits, 256 byte alignment */
+#define	RL_RXLIST_ADDR_HI	0x00E8	/* 64 bits, 256 byte alignment */
+#define	RL_EARLY_TX_THRESH	0x00EC	/* 8 bits */
+
+/*
+ * Registers specific to the 8169 gigE chip
+ */
+#define	RL_GTXSTART		0x0038	/* 8 bits */
+#define	RL_TIMERINT_8169	0x0058	/* different offset than 8139 */
+#define	RL_PHYAR		0x0060
+#define	RL_TBICSR		0x0064
+#define	RL_TBI_ANAR		0x0068
+#define	RL_TBI_LPAR		0x006A
+#define	RL_GMEDIASTAT		0x006C	/* 8 bits */
+#define	RL_MACDBG		0x006D	/* 8 bits, 8168C SPIN2 only */
+#define	RL_GPIO			0x006E	/* 8 bits, 8168C SPIN2 only */
+#define	RL_PMCH			0x006F	/* 8 bits */
+#define	RL_MAXRXPKTLEN		0x00DA	/* 16 bits, chip multiplies by 8 */
+#define	RL_INTRMOD		0x00E2	/* 16 bits */
+#define	RL_MISC			0x00F0
+
+/*
+ * TX config register bits
+ */
+#define	RL_TXCFG_CLRABRT	0x00000001	/* retransmit aborted pkt */
+#define	RL_TXCFG_MAXDMA		0x00000700	/* max DMA burst size */
+#define	RL_TXCFG_QUEUE_EMPTY	0x00000800	/* 8168E-VL or higher */
+#define	RL_TXCFG_CRCAPPEND	0x00010000	/* CRC append (0 = yes) */
+#define	RL_TXCFG_LOOPBKTST	0x00060000	/* loopback test */
+#define	RL_TXCFG_IFG2		0x00080000	/* 8169 only */
+#define	RL_TXCFG_IFG		0x03000000	/* interframe gap */
+#define	RL_TXCFG_HWREV		0x7CC00000
+
+#define	RL_LOOPTEST_OFF		0x00000000
+#define	RL_LOOPTEST_ON		0x00020000
+#define	RL_LOOPTEST_ON_CPLUS	0x00060000
+
+/* Known revision codes. */
+#define	RL_HWREV_8169		0x00000000
+#define	RL_HWREV_8169S		0x00800000
+#define	RL_HWREV_8110S		0x04000000
+#define	RL_HWREV_8169_8110SB	0x10000000
+#define	RL_HWREV_8169_8110SC	0x18000000
+#define	RL_HWREV_8401E		0x24000000
+#define	RL_HWREV_8102EL		0x24800000
+#define	RL_HWREV_8102EL_SPIN1	0x24C00000
+#define	RL_HWREV_8168D		0x28000000
+#define	RL_HWREV_8168DP		0x28800000
+#define	RL_HWREV_8168E		0x2C000000
+#define	RL_HWREV_8168E_VL	0x2C800000
+#define	RL_HWREV_8168B_SPIN1	0x30000000
+#define	RL_HWREV_8100E		0x30800000
+#define	RL_HWREV_8101E		0x34000000
+#define	RL_HWREV_8102E		0x34800000
+#define	RL_HWREV_8103E		0x34C00000
+#define	RL_HWREV_8168B_SPIN2	0x38000000
+#define	RL_HWREV_8168B_SPIN3	0x38400000
+#define	RL_HWREV_8168C		0x3C000000
+#define	RL_HWREV_8168C_SPIN2	0x3C400000
+#define	RL_HWREV_8168CP		0x3C800000
+#define	RL_HWREV_8105E		0x40800000
+#define	RL_HWREV_8105E_SPIN1	0x40C00000
+#define	RL_HWREV_8402		0x44000000
+#define	RL_HWREV_8106E		0x44800000
+#define	RL_HWREV_8168F		0x48000000
+#define	RL_HWREV_8411		0x48800000
+#define	RL_HWREV_8168G		0x4C000000
+#define	RL_HWREV_8168EP		0x50000000
+#define	RL_HWREV_8168GU		0x50800000
+#define	RL_HWREV_8411B		0x5C800000
+#define	RL_HWREV_8139		0x60000000
+#define	RL_HWREV_8139A		0x70000000
+#define	RL_HWREV_8139AG		0x70800000
+#define	RL_HWREV_8139B		0x78000000
+#define	RL_HWREV_8130		0x7C000000
+#define	RL_HWREV_8139C		0x74000000
+#define	RL_HWREV_8139D		0x74400000
+#define	RL_HWREV_8139CPLUS	0x74800000
+#define	RL_HWREV_8101		0x74C00000
+#define	RL_HWREV_8100		0x78800000
+#define	RL_HWREV_8169_8110SBL	0x7CC00000
+#define	RL_HWREV_8169_8110SCE	0x98000000
+
+#define	RL_TXDMA_16BYTES	0x00000000
+#define	RL_TXDMA_32BYTES	0x00000100
+#define	RL_TXDMA_64BYTES	0x00000200
+#define	RL_TXDMA_128BYTES	0x00000300
+#define	RL_TXDMA_256BYTES	0x00000400
+#define	RL_TXDMA_512BYTES	0x00000500
+#define	RL_TXDMA_1024BYTES	0x00000600
+#define	RL_TXDMA_2048BYTES	0x00000700
+
+/*
+ * Transmit descriptor status register bits.
+ */
+#define	RL_TXSTAT_LENMASK	0x00001FFF
+#define	RL_TXSTAT_OWN		0x00002000
+#define	RL_TXSTAT_TX_UNDERRUN	0x00004000
+#define	RL_TXSTAT_TX_OK		0x00008000
+#define	RL_TXSTAT_EARLY_THRESH	0x003F0000
+#define	RL_TXSTAT_COLLCNT	0x0F000000
+#define	RL_TXSTAT_CARR_HBEAT	0x10000000
+#define	RL_TXSTAT_OUTOFWIN	0x20000000
+#define	RL_TXSTAT_TXABRT	0x40000000
+#define	RL_TXSTAT_CARRLOSS	0x80000000
+
+/*
+ * Interrupt status register bits.
+ */
+#define	RL_ISR_RX_OK		0x0001
+#define	RL_ISR_RX_ERR		0x0002
+#define	RL_ISR_TX_OK		0x0004
+#define	RL_ISR_TX_ERR		0x0008
+#define	RL_ISR_RX_OVERRUN	0x0010
+#define	RL_ISR_PKT_UNDERRUN	0x0020
+#define	RL_ISR_LINKCHG		0x0020	/* 8169 only */
+#define	RL_ISR_FIFO_OFLOW	0x0040	/* 8139 only */
+#define	RL_ISR_TX_DESC_UNAVAIL	0x0080	/* C+ only */
+#define	RL_ISR_SWI		0x0100	/* C+ only */
+#define	RL_ISR_CABLE_LEN_CHGD	0x2000
+#define	RL_ISR_PCS_TIMEOUT	0x4000	/* 8129 only */
+#define	RL_ISR_TIMEOUT_EXPIRED	0x4000
+#define	RL_ISR_SYSTEM_ERR	0x8000
+
+#define	RL_INTRS	\
+	(RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|		\
+	RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|	\
+	RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
+
+#ifdef RE_TX_MODERATION
+#define	RL_INTRS_CPLUS	\
+	(RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|			\
+	RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|	\
+	RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
+#else
+#define	RL_INTRS_CPLUS	\
+	(RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK|		\
+	RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|	\
+	RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
+#endif
+
+/*
+ * Media status register. (8139 only)
+ */
+#define	RL_MEDIASTAT_RXPAUSE	0x01
+#define	RL_MEDIASTAT_TXPAUSE	0x02
+#define	RL_MEDIASTAT_LINK	0x04
+#define	RL_MEDIASTAT_SPEED10	0x08
+#define	RL_MEDIASTAT_RXFLOWCTL	0x40	/* duplex mode */
+#define	RL_MEDIASTAT_TXFLOWCTL	0x80	/* duplex mode */
+
+/*
+ * Receive config register.
+ */
+#define	RL_RXCFG_RX_ALLPHYS	0x00000001	/* accept all nodes */
+#define	RL_RXCFG_RX_INDIV	0x00000002	/* match filter */
+#define	RL_RXCFG_RX_MULTI	0x00000004	/* accept all multicast */
+#define	RL_RXCFG_RX_BROAD	0x00000008	/* accept all broadcast */
+#define	RL_RXCFG_RX_RUNT	0x00000010
+#define	RL_RXCFG_RX_ERRPKT	0x00000020
+#define	RL_RXCFG_WRAP		0x00000080
+#define	RL_RXCFG_EARLYOFFV2	0x00000800
+#define	RL_RXCFG_MAXDMA		0x00000700
+#define	RL_RXCFG_BUFSZ		0x00001800
+#define	RL_RXCFG_EARLYOFF	0x00003800
+#define	RL_RXCFG_FIFOTHRESH	0x0000E000
+#define	RL_RXCFG_EARLYTHRESH	0x07000000
+
+#define	RL_RXDMA_16BYTES	0x00000000
+#define	RL_RXDMA_32BYTES	0x00000100
+#define	RL_RXDMA_64BYTES	0x00000200
+#define	RL_RXDMA_128BYTES	0x00000300
+#define	RL_RXDMA_256BYTES	0x00000400
+#define	RL_RXDMA_512BYTES	0x00000500
+#define	RL_RXDMA_1024BYTES	0x00000600
+#define	RL_RXDMA_UNLIMITED	0x00000700
+
+#define	RL_RXBUF_8		0x00000000
+#define	RL_RXBUF_16		0x00000800
+#define	RL_RXBUF_32		0x00001000
+#define	RL_RXBUF_64		0x00001800
+
+#define	RL_RXFIFO_16BYTES	0x00000000
+#define	RL_RXFIFO_32BYTES	0x00002000
+#define	RL_RXFIFO_64BYTES	0x00004000
+#define	RL_RXFIFO_128BYTES	0x00006000
+#define	RL_RXFIFO_256BYTES	0x00008000
+#define	RL_RXFIFO_512BYTES	0x0000A000
+#define	RL_RXFIFO_1024BYTES	0x0000C000
+#define	RL_RXFIFO_NOTHRESH	0x0000E000
+
+/*
+ * Bits in RX status header (included with RX'ed packet
+ * in ring buffer).
+ */
+#define	RL_RXSTAT_RXOK		0x00000001
+#define	RL_RXSTAT_ALIGNERR	0x00000002
+#define	RL_RXSTAT_CRCERR	0x00000004
+#define	RL_RXSTAT_GIANT		0x00000008
+#define	RL_RXSTAT_RUNT		0x00000010
+#define	RL_RXSTAT_BADSYM	0x00000020
+#define	RL_RXSTAT_BROAD		0x00002000
+#define	RL_RXSTAT_INDIV		0x00004000
+#define	RL_RXSTAT_MULTI		0x00008000
+#define	RL_RXSTAT_LENMASK	0xFFFF0000
+#define	RL_RXSTAT_UNFINISHED	0x0000FFF0	/* DMA still in progress */
+
+/*
+ * Command register.
+ */
+#define	RL_CMD_EMPTY_RXBUF	0x0001
+#define	RL_CMD_TX_ENB		0x0004
+#define	RL_CMD_RX_ENB		0x0008
+#define	RL_CMD_RESET		0x0010
+#define	RL_CMD_STOPREQ		0x0080
+
+/*
+ * Twister register values.  These are completely undocumented and derived
+ * from public sources.
+ */
+#define	RL_CSCFG_LINK_OK	0x0400
+#define	RL_CSCFG_CHANGE		0x0800
+#define	RL_CSCFG_STATUS		0xf000
+#define	RL_CSCFG_ROW3		0x7000
+#define	RL_CSCFG_ROW2		0x3000
+#define	RL_CSCFG_ROW1		0x1000
+#define	RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0
+#define	RL_CSCFG_LINK_DOWN_CMD	0xf3c0
+
+#define	RL_NWAYTST_RESET	0
+#define	RL_NWAYTST_CBL_TEST	0x20
+
+#define	RL_PARA78		0x78
+#define	RL_PARA78_DEF		0x78fa8388
+#define	RL_PARA7C		0x7C
+#define	RL_PARA7C_DEF		0xcb38de43
+#define	RL_PARA7C_RETUNE	0xfb38de03
+
+/*
+ * EEPROM control register
+ */
+#define	RL_EE_DATAOUT		0x01	/* Data out */
+#define	RL_EE_DATAIN		0x02	/* Data in */
+#define	RL_EE_CLK		0x04	/* clock */
+#define	RL_EE_SEL		0x08	/* chip select */
+#define	RL_EE_MODE		(0x40|0x80)
+
+#define	RL_EEMODE_OFF		0x00
+#define	RL_EEMODE_AUTOLOAD	0x40
+#define	RL_EEMODE_PROGRAM	0x80
+#define	RL_EEMODE_WRITECFG	(0x80|0x40)
+
+/* 9346 EEPROM commands */
+#define	RL_9346_ADDR_LEN	6	/* 93C46 1K: 128x16 */
+#define	RL_9356_ADDR_LEN	8	/* 93C56 2K: 256x16 */
+
+#define	RL_9346_WRITE		0x5
+#define	RL_9346_READ		0x6
+#define	RL_9346_ERASE		0x7
+#define	RL_9346_EWEN		0x4
+#define	RL_9346_EWEN_ADDR	0x30
+#define	RL_9456_EWDS		0x4
+#define	RL_9346_EWDS_ADDR	0x00
+
+#define	RL_EECMD_WRITE		0x140
+#define	RL_EECMD_READ_6BIT	0x180
+#define	RL_EECMD_READ_8BIT	0x600
+#define	RL_EECMD_ERASE		0x1c0
+
+#define	RL_EE_ID		0x00
+#define	RL_EE_PCI_VID		0x01
+#define	RL_EE_PCI_DID		0x02
+/* Location of station address inside EEPROM */
+#define	RL_EE_EADDR		0x07
+
+/*
+ * MII register (8129 only)
+ */
+#define	RL_MII_CLK		0x01
+#define	RL_MII_DATAIN		0x02
+#define	RL_MII_DATAOUT		0x04
+#define	RL_MII_DIR		0x80	/* 0 == input, 1 == output */
+
+/*
+ * Config 0 register
+ */
+#define	RL_CFG0_ROM0		0x01
+#define	RL_CFG0_ROM1		0x02
+#define	RL_CFG0_ROM2		0x04
+#define	RL_CFG0_PL0		0x08
+#define	RL_CFG0_PL1		0x10
+#define	RL_CFG0_10MBPS		0x20	/* 10 Mbps internal mode */
+#define	RL_CFG0_PCS		0x40
+#define	RL_CFG0_SCR		0x80
+
+/*
+ * Config 1 register
+ */
+#define	RL_CFG1_PWRDWN		0x01
+#define	RL_CFG1_PME		0x01
+#define	RL_CFG1_SLEEP		0x02
+#define	RL_CFG1_VPDEN		0x02
+#define	RL_CFG1_IOMAP		0x04
+#define	RL_CFG1_MEMMAP		0x08
+#define	RL_CFG1_RSVD		0x10
+#define	RL_CFG1_LWACT		0x10
+#define	RL_CFG1_DRVLOAD		0x20
+#define	RL_CFG1_LED0		0x40
+#define	RL_CFG1_FULLDUPLEX	0x40	/* 8129 only */
+#define	RL_CFG1_LED1		0x80
+
+/*
+ * Config 2 register
+ */
+#define	RL_CFG2_PCI33MHZ	0x00
+#define	RL_CFG2_PCI66MHZ	0x01
+#define	RL_CFG2_PCI64BIT	0x08
+#define	RL_CFG2_AUXPWR		0x10
+#define	RL_CFG2_MSI		0x20
+
+/*
+ * Config 3 register
+ */
+#define	RL_CFG3_GRANTSEL	0x80
+#define	RL_CFG3_WOL_MAGIC	0x20
+#define	RL_CFG3_WOL_LINK	0x10
+#define	RL_CFG3_JUMBO_EN0	0x04	/* RTL8168C or later. */
+#define	RL_CFG3_FAST_B2B	0x01
+
+/*
+ * Config 4 register
+ */
+#define	RL_CFG4_LWPTN		0x04
+#define	RL_CFG4_LWPME		0x10
+#define	RL_CFG4_JUMBO_EN1	0x02	/* RTL8168C or later. */
+
+/*
+ * Config 5 register
+ */
+#define	RL_CFG5_WOL_BCAST	0x40
+#define	RL_CFG5_WOL_MCAST	0x20
+#define	RL_CFG5_WOL_UCAST	0x10
+#define	RL_CFG5_WOL_LANWAKE	0x02
+#define	RL_CFG5_PME_STS		0x01
+
+/*
+ * 8139C+ register definitions
+ */
+
+/* RL_DUMPSTATS_LO register */
+#define	RL_DUMPSTATS_START	0x00000008
+
+/* Transmit start register */
+#define	RL_TXSTART_SWI		0x01	/* generate TX interrupt */
+#define	RL_TXSTART_START	0x40	/* start normal queue transmit */
+#define	RL_TXSTART_HPRIO_START	0x80	/* start hi prio queue transmit */
+
+/*
+ * Config 2 register, 8139C+/8169/8169S/8110S only
+ */
+#define	RL_CFG2_BUSFREQ		0x07
+#define	RL_CFG2_BUSWIDTH	0x08
+#define	RL_CFG2_AUXPWRSTS	0x10
+
+#define	RL_BUSFREQ_33MHZ	0x00
+#define	RL_BUSFREQ_66MHZ	0x01
+
+#define	RL_BUSWIDTH_32BITS	0x00
+#define	RL_BUSWIDTH_64BITS	0x08
+
+/* C+ mode command register */
+#define	RL_CPLUSCMD_TXENB	0x0001	/* enable C+ transmit mode */
+#define	RL_CPLUSCMD_RXENB	0x0002	/* enable C+ receive mode */
+#define	RL_CPLUSCMD_PCI_MRW	0x0008	/* enable PCI multi-read/write */
+#define	RL_CPLUSCMD_PCI_DAC	0x0010	/* PCI dual-address cycle only */
+#define	RL_CPLUSCMD_RXCSUM_ENB	0x0020	/* enable RX checksum offload */
+#define	RL_CPLUSCMD_VLANSTRIP	0x0040	/* enable VLAN tag stripping */
+#define	RL_CPLUSCMD_MACSTAT_DIS	0x0080	/* 8168B/C/CP */
+#define	RL_CPLUSCMD_ASF		0x0100	/* 8168C/CP */
+#define	RL_CPLUSCMD_DBG_SEL	0x0200	/* 8168C/CP */
+#define	RL_CPLUSCMD_FORCE_TXFC	0x0400	/* 8168C/CP */
+#define	RL_CPLUSCMD_FORCE_RXFC	0x0800	/* 8168C/CP */
+#define	RL_CPLUSCMD_FORCE_HDPX	0x1000	/* 8168C/CP */
+#define	RL_CPLUSCMD_NORMAL_MODE	0x2000	/* 8168C/CP */
+#define	RL_CPLUSCMD_DBG_ENB	0x4000	/* 8168C/CP */
+#define	RL_CPLUSCMD_BIST_ENB	0x8000	/* 8168C/CP */
+
+/* C+ early transmit threshold */
+#define	RL_EARLYTXTHRESH_CNT	0x003F	/* byte count times 8 */
+
+/* Timer interrupt register */
+#define	RL_TIMERINT_8169_VAL	0x00001FFF
+#define	RL_TIMER_MIN		0
+#define	RL_TIMER_MAX		65	/* 65.528us */
+#define	RL_TIMER_DEFAULT	RL_TIMER_MAX
+#define	RL_TIMER_PCIE_CLK	125	/* 125MHZ */
+#define	RL_USECS(x)		((x) * RL_TIMER_PCIE_CLK)
+
+/*
+ * Gigabit PHY access register (8169 only)
+ */
+#define	RL_PHYAR_PHYDATA	0x0000FFFF
+#define	RL_PHYAR_PHYREG		0x001F0000
+#define	RL_PHYAR_BUSY		0x80000000
+
+/*
+ * Gigabit media status (8169 only)
+ */
+#define	RL_GMEDIASTAT_FDX	0x01	/* full duplex */
+#define	RL_GMEDIASTAT_LINK	0x02	/* link up */
+#define	RL_GMEDIASTAT_10MBPS	0x04	/* 10mps link */
+#define	RL_GMEDIASTAT_100MBPS	0x08	/* 100mbps link */
+#define	RL_GMEDIASTAT_1000MBPS	0x10	/* gigE link */
+#define	RL_GMEDIASTAT_RXFLOW	0x20	/* RX flow control on */
+#define	RL_GMEDIASTAT_TXFLOW	0x40	/* TX flow control on */
+#define	RL_GMEDIASTAT_TBI	0x80	/* TBI enabled */
+
+/*
+ * The RealTek doesn't use a fragment-based descriptor mechanism.
+ * Instead, there are only four register sets, each or which represents
+ * one 'descriptor.' Basically, each TX descriptor is just a contiguous
+ * packet buffer (32-bit aligned!) and we place the buffer addresses in
+ * the registers so the chip knows where they are.
+ *
+ * We can sort of kludge together the same kind of buffer management
+ * used in previous drivers, but we have to do buffer copies almost all
+ * the time, so it doesn't really buy us much.
+ *
+ * For reception, there's just one large buffer where the chip stores
+ * all received packets.
+ */
+#define	RL_RX_BUF_SZ		RL_RXBUF_64
+#define	RL_RXBUFLEN		(1 << ((RL_RX_BUF_SZ >> 11) + 13))
+#define	RL_TX_LIST_CNT		4
+#define	RL_MIN_FRAMELEN		60
+#define	RL_TX_8139_BUF_ALIGN	4
+#define	RL_RX_8139_BUF_ALIGN	8
+#define	RL_RX_8139_BUF_RESERVE	sizeof(int64_t)
+#define	RL_RX_8139_BUF_GUARD_SZ	\
+	(ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE)
+#define	RL_TXTHRESH(x)		((x) << 11)
+#define	RL_TX_THRESH_INIT	96
+#define	RL_RX_FIFOTHRESH	RL_RXFIFO_NOTHRESH
+#define	RL_RX_MAXDMA		RL_RXDMA_UNLIMITED
+#define	RL_TX_MAXDMA		RL_TXDMA_2048BYTES
+
+#define	RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ)
+#define	RL_TXCFG_CONFIG	(RL_TXCFG_IFG|RL_TX_MAXDMA)
+
+#define	RL_ETHER_ALIGN	2
+
+/*
+ * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets.
+ */
+#define	RL_IP4CSUMTX_MINLEN	28
+#define	RL_IP4CSUMTX_PADLEN	(ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN)
+
+struct rl_chain_data {
+	uint16_t		cur_rx;
+	uint8_t			*rl_rx_buf;
+	uint8_t			*rl_rx_buf_ptr;
+
+	struct mbuf		*rl_tx_chain[RL_TX_LIST_CNT];
+	bus_dmamap_t		rl_tx_dmamap[RL_TX_LIST_CNT];
+	bus_dma_tag_t		rl_tx_tag;
+	bus_dma_tag_t		rl_rx_tag;
+	bus_dmamap_t		rl_rx_dmamap;
+	bus_addr_t		rl_rx_buf_paddr;
+	uint8_t			last_tx;
+	uint8_t			cur_tx;
+};
+
+#define	RL_INC(x)		(x = (x + 1) % RL_TX_LIST_CNT)
+#define	RL_CUR_TXADDR(x)	((x->rl_cdata.cur_tx * 4) + RL_TXADDR0)
+#define	RL_CUR_TXSTAT(x)	((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0)
+#define	RL_CUR_TXMBUF(x)	(x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx])
+#define	RL_CUR_DMAMAP(x)	(x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx])
+#define	RL_LAST_TXADDR(x)	((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
+#define	RL_LAST_TXSTAT(x)	((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
+#define	RL_LAST_TXMBUF(x)	(x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
+#define	RL_LAST_DMAMAP(x)	(x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
+
+struct rl_type {
+	uint16_t		rl_vid;
+	uint16_t		rl_did;
+	int			rl_basetype;
+	const char		*rl_name;
+};
+
+struct rl_hwrev {
+	uint32_t		rl_rev;
+	int			rl_type;
+	const char		*rl_desc;
+	int			rl_max_mtu;
+};
+
+#define	RL_8129			1
+#define	RL_8139			2
+#define	RL_8139CPLUS		3
+#define	RL_8169			4
+
+#define	RL_ISCPLUS(x)		((x)->rl_type == RL_8139CPLUS ||	\
+				 (x)->rl_type == RL_8169)
+
+/*
+ * The 8139C+ and 8160 gigE chips support descriptor-based TX
+ * and RX. In fact, they even support TCP large send. Descriptors
+ * must be allocated in contiguous blocks that are aligned on a
+ * 256-byte boundary. The rings can hold a maximum of 64 descriptors.
+ */
+
+/*
+ * RX/TX descriptor definition. When large send mode is enabled, the
+ * lower 11 bits of the TX rl_cmdstat word are used to hold the MSS, and
+ * the checksum offload bits are disabled. The structure layout is
+ * the same for RX and TX descriptors
+ */
+struct rl_desc {
+	uint32_t		rl_cmdstat;
+	uint32_t		rl_vlanctl;
+	uint32_t		rl_bufaddr_lo;
+	uint32_t		rl_bufaddr_hi;
+};
+
+#define	RL_TDESC_CMD_FRAGLEN	0x0000FFFF
+#define	RL_TDESC_CMD_TCPCSUM	0x00010000	/* TCP checksum enable */
+#define	RL_TDESC_CMD_UDPCSUM	0x00020000	/* UDP checksum enable */
+#define	RL_TDESC_CMD_IPCSUM	0x00040000	/* IP header checksum enable */
+#define	RL_TDESC_CMD_MSSVAL	0x07FF0000	/* Large send MSS value */
+#define	RL_TDESC_CMD_MSSVAL_SHIFT	16	/* Large send MSS value shift */
+#define	RL_TDESC_CMD_LGSEND	0x08000000	/* TCP large send enb */
+#define	RL_TDESC_CMD_EOF	0x10000000	/* end of frame marker */
+#define	RL_TDESC_CMD_SOF	0x20000000	/* start of frame marker */
+#define	RL_TDESC_CMD_EOR	0x40000000	/* end of ring marker */
+#define	RL_TDESC_CMD_OWN	0x80000000	/* chip owns descriptor */
+
+#define	RL_TDESC_VLANCTL_TAG	0x00020000	/* Insert VLAN tag */
+#define	RL_TDESC_VLANCTL_DATA	0x0000FFFF	/* TAG data */
+/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
+#define	RL_TDESC_CMD_UDPCSUMV2	0x80000000
+#define	RL_TDESC_CMD_TCPCSUMV2	0x40000000
+#define	RL_TDESC_CMD_IPCSUMV2	0x20000000
+#define	RL_TDESC_CMD_MSSVALV2	0x1FFC0000
+#define	RL_TDESC_CMD_MSSVALV2_SHIFT	18
+
+/*
+ * Error bits are valid only on the last descriptor of a frame
+ * (i.e. RL_TDESC_CMD_EOF == 1)
+ */
+#define	RL_TDESC_STAT_COLCNT	0x000F0000	/* collision count */
+#define	RL_TDESC_STAT_EXCESSCOL	0x00100000	/* excessive collisions */
+#define	RL_TDESC_STAT_LINKFAIL	0x00200000	/* link faulure */
+#define	RL_TDESC_STAT_OWINCOL	0x00400000	/* out-of-window collision */
+#define	RL_TDESC_STAT_TXERRSUM	0x00800000	/* transmit error summary */
+#define	RL_TDESC_STAT_UNDERRUN	0x02000000	/* TX underrun occured */
+#define	RL_TDESC_STAT_OWN	0x80000000
+
+/*
+ * RX descriptor cmd/vlan definitions
+ */
+#define	RL_RDESC_CMD_EOR	0x40000000
+#define	RL_RDESC_CMD_OWN	0x80000000
+#define	RL_RDESC_CMD_BUFLEN	0x00001FFF
+
+#define	RL_RDESC_STAT_OWN	0x80000000
+#define	RL_RDESC_STAT_EOR	0x40000000
+#define	RL_RDESC_STAT_SOF	0x20000000
+#define	RL_RDESC_STAT_EOF	0x10000000
+#define	RL_RDESC_STAT_FRALIGN	0x08000000	/* frame alignment error */
+#define	RL_RDESC_STAT_MCAST	0x04000000	/* multicast pkt received */
+#define	RL_RDESC_STAT_UCAST	0x02000000	/* unicast pkt received */
+#define	RL_RDESC_STAT_BCAST	0x01000000	/* broadcast pkt received */
+#define	RL_RDESC_STAT_BUFOFLOW	0x00800000	/* out of buffer space */
+#define	RL_RDESC_STAT_FIFOOFLOW	0x00400000	/* FIFO overrun */
+#define	RL_RDESC_STAT_GIANT	0x00200000	/* pkt > 4096 bytes */
+#define	RL_RDESC_STAT_RXERRSUM	0x00100000	/* RX error summary */
+#define	RL_RDESC_STAT_RUNT	0x00080000	/* runt packet received */
+#define	RL_RDESC_STAT_CRCERR	0x00040000	/* CRC error */
+#define	RL_RDESC_STAT_PROTOID	0x00030000	/* Protocol type */
+#define	RL_RDESC_STAT_UDP	0x00020000	/* UDP, 8168C/CP, 8111C/CP */
+#define	RL_RDESC_STAT_TCP	0x00010000	/* TCP, 8168C/CP, 8111C/CP */
+#define	RL_RDESC_STAT_IPSUMBAD	0x00008000	/* IP header checksum bad */
+#define	RL_RDESC_STAT_UDPSUMBAD	0x00004000	/* UDP checksum bad */
+#define	RL_RDESC_STAT_TCPSUMBAD	0x00002000	/* TCP checksum bad */
+#define	RL_RDESC_STAT_FRAGLEN	0x00001FFF	/* RX'ed frame/frag len */
+#define	RL_RDESC_STAT_GFRAGLEN	0x00003FFF	/* RX'ed frame/frag len */
+#define	RL_RDESC_STAT_ERRS	(RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \
+				 RL_RDESC_STAT_CRCERR)
+
+#define	RL_RDESC_VLANCTL_TAG	0x00010000	/* VLAN tag available
+						   (rl_vlandata valid)*/
+#define	RL_RDESC_VLANCTL_DATA	0x0000FFFF	/* TAG data */
+/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
+#define	RL_RDESC_IPV6		0x80000000
+#define	RL_RDESC_IPV4		0x40000000
+
+#define	RL_PROTOID_NONIP	0x00000000
+#define	RL_PROTOID_TCPIP	0x00010000
+#define	RL_PROTOID_UDPIP	0x00020000
+#define	RL_PROTOID_IP		0x00030000
+#define	RL_TCPPKT(x)		(((x) & RL_RDESC_STAT_PROTOID) == \
+				 RL_PROTOID_TCPIP)
+#define	RL_UDPPKT(x)		(((x) & RL_RDESC_STAT_PROTOID) == \
+				 RL_PROTOID_UDPIP)
+
+/*
+ * Statistics counter structure (8139C+ and 8169 only)
+ */
+struct rl_stats {
+	uint64_t		rl_tx_pkts;
+	uint64_t		rl_rx_pkts;
+	uint64_t		rl_tx_errs;
+	uint32_t		rl_rx_errs;
+	uint16_t		rl_missed_pkts;
+	uint16_t		rl_rx_framealign_errs;
+	uint32_t		rl_tx_onecoll;
+	uint32_t		rl_tx_multicolls;
+	uint64_t		rl_rx_ucasts;
+	uint64_t		rl_rx_bcasts;
+	uint32_t		rl_rx_mcasts;
+	uint16_t		rl_tx_aborts;
+	uint16_t		rl_rx_underruns;
+};
+
+/*
+ * Rx/Tx descriptor parameters (8139C+ and 8169 only)
+ *
+ * 8139C+
+ *  Number of descriptors supported : up to 64
+ *  Descriptor alignment : 256 bytes
+ *  Tx buffer : At least 4 bytes in length.
+ *  Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
+ *
+ * 8169
+ *  Number of descriptors supported : up to 1024
+ *  Descriptor alignment : 256 bytes
+ *  Tx buffer : At least 4 bytes in length.
+ *  Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
+ */
+#ifndef	__NO_STRICT_ALIGNMENT
+#define	RE_FIXUP_RX	1
+#endif
+
+#define	RL_8169_TX_DESC_CNT	256
+#define	RL_8169_RX_DESC_CNT	256
+#define	RL_8139_TX_DESC_CNT	64
+#define	RL_8139_RX_DESC_CNT	64
+#define	RL_TX_DESC_CNT		RL_8169_TX_DESC_CNT
+#define	RL_RX_DESC_CNT		RL_8169_RX_DESC_CNT
+#define	RL_RX_JUMBO_DESC_CNT	RL_RX_DESC_CNT
+#define	RL_NTXSEGS		35
+
+#define	RL_RING_ALIGN		256
+#define	RL_DUMP_ALIGN		64
+#define	RL_IFQ_MAXLEN		512
+#define	RL_TX_DESC_NXT(sc,x)	((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
+#define	RL_TX_DESC_PRV(sc,x)	((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
+#define	RL_RX_DESC_NXT(sc,x)	((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1))
+#define	RL_OWN(x)		(le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
+#define	RL_RXBYTES(x)		(le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask)
+#define	RL_PKTSZ(x)		((x)/* >> 3*/)
+#ifdef RE_FIXUP_RX
+#define	RE_ETHER_ALIGN	sizeof(uint64_t)
+#define	RE_RX_DESC_BUFLEN	(MCLBYTES - RE_ETHER_ALIGN)
+#else
+#define	RE_ETHER_ALIGN	0
+#define	RE_RX_DESC_BUFLEN	MCLBYTES
+#endif
+
+#define	RL_MSI_MESSAGES	1
+
+#define	RL_ADDR_LO(y)		((uint64_t) (y) & 0xFFFFFFFF)
+#define	RL_ADDR_HI(y)		((uint64_t) (y) >> 32)
+
+/*
+ * The number of bits reserved for MSS in RealTek controllers is
+ * 11bits. This limits the maximum interface MTU size in TSO case
+ * as upper stack should not generate TCP segments with MSS greater
+ * than the limit.
+ */
+#define	RL_TSO_MTU		(2047 - ETHER_HDR_LEN - ETHER_CRC_LEN)
+
+/* see comment in dev/re/if_re.c */
+#define	RL_JUMBO_FRAMELEN	7440
+#define	RL_JUMBO_MTU		\
+	(RL_JUMBO_FRAMELEN-ETHER_VLAN_ENCAP_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
+#define	RL_JUMBO_MTU_6K		\
+	((6 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
+#define	RL_JUMBO_MTU_9K		\
+	((9 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
+#define	RL_MTU			\
+	(ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
+
+struct rl_txdesc {
+	struct mbuf		*tx_m;
+	bus_dmamap_t		tx_dmamap;
+};
+
+struct rl_rxdesc {
+	struct mbuf		*rx_m;
+	bus_dmamap_t		rx_dmamap;
+	bus_size_t		rx_size;
+};
+
+struct rl_list_data {
+	struct rl_txdesc	rl_tx_desc[RL_TX_DESC_CNT];
+	struct rl_rxdesc	rl_rx_desc[RL_RX_DESC_CNT];
+	struct rl_rxdesc	rl_jrx_desc[RL_RX_JUMBO_DESC_CNT];
+	int			rl_tx_desc_cnt;
+	int			rl_rx_desc_cnt;
+	int			rl_tx_prodidx;
+	int			rl_rx_prodidx;
+	int			rl_tx_considx;
+	int			rl_tx_free;
+	bus_dma_tag_t		rl_tx_mtag;	/* mbuf TX mapping tag */
+	bus_dma_tag_t		rl_rx_mtag;	/* mbuf RX mapping tag */
+	bus_dma_tag_t		rl_jrx_mtag;	/* mbuf RX mapping tag */
+	bus_dmamap_t		rl_rx_sparemap;
+	bus_dmamap_t		rl_jrx_sparemap;
+	bus_dma_tag_t		rl_stag;	/* stats mapping tag */
+	bus_dmamap_t		rl_smap;	/* stats map */
+	struct rl_stats		*rl_stats;
+	bus_addr_t		rl_stats_addr;
+	bus_dma_tag_t		rl_rx_list_tag;
+	bus_dmamap_t		rl_rx_list_map;
+	struct rl_desc		*rl_rx_list;
+	bus_addr_t		rl_rx_list_addr;
+	bus_dma_tag_t		rl_tx_list_tag;
+	bus_dmamap_t		rl_tx_list_map;
+	struct rl_desc		*rl_tx_list;
+	bus_addr_t		rl_tx_list_addr;
+};
+
+enum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE };
+
+struct rl_softc {
+	struct ifnet		*rl_ifp;	/* interface info */
+	bus_space_handle_t	rl_bhandle;	/* bus space handle */
+	bus_space_tag_t		rl_btag;	/* bus space tag */
+	device_t		rl_dev;
+	struct resource		*rl_res;
+	int			rl_res_id;
+	int			rl_res_type;
+	struct resource		*rl_res_pba;
+	struct resource		*rl_irq[RL_MSI_MESSAGES];
+	void			*rl_intrhand[RL_MSI_MESSAGES];
+	device_t		rl_miibus;
+	bus_dma_tag_t		rl_parent_tag;
+	uint8_t			rl_type;
+	const struct rl_hwrev	*rl_hwrev;
+	uint32_t		rl_macrev;
+	int			rl_eecmd_read;
+	int			rl_eewidth;
+	int			rl_expcap;
+	int			rl_txthresh;
+	bus_size_t		rl_cfg0;
+	bus_size_t		rl_cfg1;
+	bus_size_t		rl_cfg2;
+	bus_size_t		rl_cfg3;
+	bus_size_t		rl_cfg4;
+	bus_size_t		rl_cfg5;
+	struct rl_chain_data	rl_cdata;
+	struct rl_list_data	rl_ldata;
+	struct callout		rl_stat_callout;
+	int			rl_watchdog_timer;
+	struct mtx		rl_mtx;
+	struct mbuf		*rl_head;
+	struct mbuf		*rl_tail;
+	uint32_t		rl_rxlenmask;
+	int			rl_testmode;
+	int			rl_if_flags;
+	int			rl_twister_enable;
+	enum rl_twist		rl_twister;
+	int			rl_twist_row;
+	int			rl_twist_col;
+	int			suspended;	/* 0 = normal  1 = suspended */
+#ifdef DEVICE_POLLING
+	int			rxcycles;
+#endif
+
+	struct task		rl_inttask;
+
+	int			rl_txstart;
+	int			rl_int_rx_act;
+	int			rl_int_rx_mod;
+	uint32_t		rl_flags;
+#define	RL_FLAG_MSI		0x00000001
+#define	RL_FLAG_AUTOPAD		0x00000002
+#define	RL_FLAG_PHYWAKE_PM	0x00000004
+#define	RL_FLAG_PHYWAKE		0x00000008
+#define	RL_FLAG_JUMBOV2		0x00000010
+#define	RL_FLAG_PAR		0x00000020
+#define	RL_FLAG_DESCV2		0x00000040
+#define	RL_FLAG_MACSTAT		0x00000080
+#define	RL_FLAG_FASTETHER	0x00000100
+#define	RL_FLAG_CMDSTOP		0x00000200
+#define	RL_FLAG_MACRESET	0x00000400
+#define	RL_FLAG_MSIX		0x00000800
+#define	RL_FLAG_WOLRXENB	0x00001000
+#define	RL_FLAG_MACSLEEP	0x00002000
+#define	RL_FLAG_WAIT_TXPOLL	0x00004000
+#define	RL_FLAG_CMDSTOP_WAIT_TXQ	0x00008000
+#define	RL_FLAG_WOL_MANLINK	0x00010000
+#define	RL_FLAG_EARLYOFF	0x00020000
+#define	RL_FLAG_EARLYOFFV2	0x00040000
+#define	RL_FLAG_RXDV_GATED	0x00080000
+#define	RL_FLAG_PCIE		0x40000000
+#define	RL_FLAG_LINK		0x80000000
+};
+
+#define	RL_LOCK(_sc)		mtx_lock(&(_sc)->rl_mtx)
+#define	RL_UNLOCK(_sc)		mtx_unlock(&(_sc)->rl_mtx)
+#define	RL_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->rl_mtx, MA_OWNED)
+
+/*
+ * register space access macros
+ */
+#define	CSR_WRITE_STREAM_4(sc, reg, val)	\
+	bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val)
+#define	CSR_WRITE_4(sc, reg, val)	\
+	bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val)
+#define	CSR_WRITE_2(sc, reg, val)	\
+	bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val)
+#define	CSR_WRITE_1(sc, reg, val)	\
+	bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val)
+
+#define	CSR_READ_4(sc, reg)		\
+	bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg)
+#define	CSR_READ_2(sc, reg)		\
+	bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg)
+#define	CSR_READ_1(sc, reg)		\
+	bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg)
+
+#define	CSR_BARRIER(sc, reg, length, flags)				\
+	bus_space_barrier(sc->rl_btag, sc->rl_bhandle, reg, length, flags)
+
+#define	CSR_SETBIT_1(sc, offset, val)		\
+	CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
+
+#define	CSR_CLRBIT_1(sc, offset, val)		\
+	CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
+
+#define	CSR_SETBIT_2(sc, offset, val)		\
+	CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
+
+#define	CSR_CLRBIT_2(sc, offset, val)		\
+	CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
+
+#define	CSR_SETBIT_4(sc, offset, val)		\
+	CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val))
+
+#define	CSR_CLRBIT_4(sc, offset, val)		\
+	CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val))
+
+#define	RL_TIMEOUT		1000
+#define	RL_PHY_TIMEOUT		2000
+
+/*
+ * General constants that are fun to know.
+ *
+ * RealTek PCI vendor ID
+ */
+#define	RT_VENDORID				0x10EC
+
+/*
+ * RealTek chip device IDs.
+ */
+#define	RT_DEVICEID_8139D			0x8039
+#define	RT_DEVICEID_8129			0x8129
+#define	RT_DEVICEID_8101E			0x8136
+#define	RT_DEVICEID_8138			0x8138
+#define	RT_DEVICEID_8139			0x8139
+#define	RT_DEVICEID_8169SC			0x8167
+#define	RT_DEVICEID_8168			0x8168
+#define	RT_DEVICEID_8169			0x8169
+#define	RT_DEVICEID_8100			0x8100
+
+#define	RT_REVID_8139CPLUS			0x20
+
+/*
+ * Accton PCI vendor ID
+ */
+#define	ACCTON_VENDORID				0x1113
+
+/*
+ * Accton MPX 5030/5038 device ID.
+ */
+#define	ACCTON_DEVICEID_5030			0x1211
+
+/*
+ * Nortel PCI vendor ID
+ */
+#define	NORTEL_VENDORID				0x126C
+
+/*
+ * Delta Electronics Vendor ID.
+ */
+#define	DELTA_VENDORID				0x1500
+
+/*
+ * Delta device IDs.
+ */
+#define	DELTA_DEVICEID_8139			0x1360
+
+/*
+ * Addtron vendor ID.
+ */
+#define	ADDTRON_VENDORID			0x4033
+
+/*
+ * Addtron device IDs.
+ */
+#define	ADDTRON_DEVICEID_8139			0x1360
+
+/*
+ * D-Link vendor ID.
+ */
+#define	DLINK_VENDORID				0x1186
+
+/*
+ * D-Link DFE-530TX+ device ID
+ */
+#define	DLINK_DEVICEID_530TXPLUS		0x1300
+
+/*
+ * D-Link DFE-520TX rev. C1 device ID
+ */
+#define	DLINK_DEVICEID_520TX_REVC1		0x4200
+
+/*
+ * D-Link DFE-5280T device ID
+ */
+#define	DLINK_DEVICEID_528T			0x4300
+#define	DLINK_DEVICEID_530T_REVC		0x4302
+
+/*
+ * D-Link DFE-690TXD device ID
+ */
+#define	DLINK_DEVICEID_690TXD			0x1340
+
+/*
+ * Corega K.K vendor ID
+ */
+#define	COREGA_VENDORID				0x1259
+
+/*
+ * Corega FEther CB-TXD device ID
+ */
+#define	COREGA_DEVICEID_FETHERCBTXD		0xa117
+
+/*
+ * Corega FEtherII CB-TXD device ID
+ */
+#define	COREGA_DEVICEID_FETHERIICBTXD		0xa11e
+
+/*
+ * Corega CG-LAPCIGT device ID
+ */
+#define	COREGA_DEVICEID_CGLAPCIGT		0xc107
+
+/*
+ * Linksys vendor ID
+ */
+#define	LINKSYS_VENDORID			0x1737
+
+/*
+ * Linksys EG1032 device ID
+ */
+#define	LINKSYS_DEVICEID_EG1032			0x1032
+
+/*
+ * Linksys EG1032 rev 3 sub-device ID
+ */
+#define	LINKSYS_SUBDEVICE_EG1032_REV3		0x0024
+
+/*
+ * Peppercon vendor ID
+ */
+#define	PEPPERCON_VENDORID			0x1743
+
+/*
+ * Peppercon ROL-F device ID
+ */
+#define	PEPPERCON_DEVICEID_ROLF			0x8139
+
+/*
+ * Planex Communications, Inc. vendor ID
+ */
+#define	PLANEX_VENDORID				0x14ea
+
+/*
+ * Planex FNW-3603-TX device ID
+ */
+#define	PLANEX_DEVICEID_FNW3603TX		0xab06
+
+/*
+ * Planex FNW-3800-TX device ID
+ */
+#define	PLANEX_DEVICEID_FNW3800TX		0xab07
+
+/*
+ * LevelOne vendor ID
+ */
+#define	LEVEL1_VENDORID				0x018A
+
+/*
+ * LevelOne FPC-0106TX devide ID
+ */
+#define	LEVEL1_DEVICEID_FPC0106TX		0x0106
+
+/*
+ * Compaq vendor ID
+ */
+#define	CP_VENDORID				0x021B
+
+/*
+ * Edimax vendor ID
+ */
+#define	EDIMAX_VENDORID				0x13D1
+
+/*
+ * Edimax EP-4103DL cardbus device ID
+ */
+#define	EDIMAX_DEVICEID_EP4103DL		0xAB06
+
+/* US Robotics vendor ID */
+
+#define	USR_VENDORID		0x16EC
+
+/* US Robotics 997902 device ID */
+
+#define	USR_DEVICEID_997902	0x0116

Property changes on: stable/9/sys/dev/rl/if_rlreg.h
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+FreeBSD=%H
\ No newline at end of property
Index: stable/9/sys/dev
===================================================================
--- stable/9/sys/dev	(revision 292780)
+++ stable/9/sys/dev	(revision 292781)

Property changes on: stable/9/sys/dev
___________________________________________________________________
Modified: svn:mergeinfo
## -0,0 +0,1 ##
   Merged /head/sys/dev:r271864
Index: stable/9/sys/modules/rl/Makefile
===================================================================
--- stable/9/sys/modules/rl/Makefile	(revision 292780)
+++ stable/9/sys/modules/rl/Makefile	(revision 292781)
@@ -1,9 +1,9 @@
 # $FreeBSD$
 
-.PATH: ${.CURDIR}/../../pci
+.PATH: ${.CURDIR}/../../dev/rl
 
 KMOD=	if_rl
 SRCS=	if_rl.c device_if.h bus_if.h pci_if.h
 SRCS+=	miibus_if.h
 
 .include <bsd.kmod.mk>
Index: stable/9/sys/modules
===================================================================
--- stable/9/sys/modules	(revision 292780)
+++ stable/9/sys/modules	(revision 292781)

Property changes on: stable/9/sys/modules
___________________________________________________________________
Modified: svn:mergeinfo
## -0,0 +0,1 ##
   Merged /head/sys/modules:r271864
Index: stable/9/sys/pci/if_rl.c
===================================================================
--- stable/9/sys/pci/if_rl.c	(revision 292780)
+++ stable/9/sys/pci/if_rl.c	(nonexistent)
@@ -1,2126 +0,0 @@
-/*-
- * Copyright (c) 1997, 1998
- *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by Bill Paul.
- * 4. Neither the name of the author nor the names of any co-contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- * THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-/*
- * RealTek 8129/8139 PCI NIC driver
- *
- * Supports several extremely cheap PCI 10/100 adapters based on
- * the RealTek chipset. Datasheets can be obtained from
- * www.realtek.com.tw.
- *
- * Written by Bill Paul <wpaul@ctr.columbia.edu>
- * Electrical Engineering Department
- * Columbia University, New York City
- */
-/*
- * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
- * probably the worst PCI ethernet controller ever made, with the possible
- * exception of the FEAST chip made by SMC. The 8139 supports bus-master
- * DMA, but it has a terrible interface that nullifies any performance
- * gains that bus-master DMA usually offers.
- *
- * For transmission, the chip offers a series of four TX descriptor
- * registers. Each transmit frame must be in a contiguous buffer, aligned
- * on a longword (32-bit) boundary. This means we almost always have to
- * do mbuf copies in order to transmit a frame, except in the unlikely
- * case where a) the packet fits into a single mbuf, and b) the packet
- * is 32-bit aligned within the mbuf's data area. The presence of only
- * four descriptor registers means that we can never have more than four
- * packets queued for transmission at any one time.
- *
- * Reception is not much better. The driver has to allocate a single large
- * buffer area (up to 64K in size) into which the chip will DMA received
- * frames. Because we don't know where within this region received packets
- * will begin or end, we have no choice but to copy data from the buffer
- * area into mbufs in order to pass the packets up to the higher protocol
- * levels.
- *
- * It's impossible given this rotten design to really achieve decent
- * performance at 100Mbps, unless you happen to have a 400Mhz PII or
- * some equally overmuscled CPU to drive it.
- *
- * On the bright side, the 8139 does have a built-in PHY, although
- * rather than using an MDIO serial interface like most other NICs, the
- * PHY registers are directly accessible through the 8139's register
- * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
- * filter.
- *
- * The 8129 chip is an older version of the 8139 that uses an external PHY
- * chip. The 8129 has a serial MDIO interface for accessing the MII where
- * the 8139 lets you directly access the on-board PHY registers. We need
- * to select which interface to use depending on the chip type.
- */
-
-#ifdef HAVE_KERNEL_OPTION_HEADERS
-#include "opt_device_polling.h"
-#endif
-
-#include <sys/param.h>
-#include <sys/endian.h>
-#include <sys/systm.h>
-#include <sys/sockio.h>
-#include <sys/mbuf.h>
-#include <sys/malloc.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/socket.h>
-#include <sys/sysctl.h>
-
-#include <net/if.h>
-#include <net/if_arp.h>
-#include <net/ethernet.h>
-#include <net/if_dl.h>
-#include <net/if_media.h>
-#include <net/if_types.h>
-
-#include <net/bpf.h>
-
-#include <machine/bus.h>
-#include <machine/resource.h>
-#include <sys/bus.h>
-#include <sys/rman.h>
-
-#include <dev/mii/mii.h>
-#include <dev/mii/mii_bitbang.h>
-#include <dev/mii/miivar.h>
-
-#include <dev/pci/pcireg.h>
-#include <dev/pci/pcivar.h>
-
-MODULE_DEPEND(rl, pci, 1, 1, 1);
-MODULE_DEPEND(rl, ether, 1, 1, 1);
-MODULE_DEPEND(rl, miibus, 1, 1, 1);
-
-/* "device miibus" required.  See GENERIC if you get errors here. */
-#include "miibus_if.h"
-
-#include <pci/if_rlreg.h>
-
-/*
- * Various supported device vendors/types and their names.
- */
-static const struct rl_type rl_devs[] = {
-	{ RT_VENDORID, RT_DEVICEID_8129, RL_8129,
-		"RealTek 8129 10/100BaseTX" },
-	{ RT_VENDORID, RT_DEVICEID_8139, RL_8139,
-		"RealTek 8139 10/100BaseTX" },
-	{ RT_VENDORID, RT_DEVICEID_8139D, RL_8139,
-		"RealTek 8139 10/100BaseTX" },
-	{ RT_VENDORID, RT_DEVICEID_8138, RL_8139,
-		"RealTek 8139 10/100BaseTX CardBus" },
-	{ RT_VENDORID, RT_DEVICEID_8100, RL_8139,
-		"RealTek 8100 10/100BaseTX" },
-	{ ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
-		"Accton MPX 5030/5038 10/100BaseTX" },
-	{ DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
-		"Delta Electronics 8139 10/100BaseTX" },
-	{ ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
-		"Addtron Technology 8139 10/100BaseTX" },
-	{ DLINK_VENDORID, DLINK_DEVICEID_520TX_REVC1, RL_8139,
-		"D-Link DFE-520TX (rev. C1) 10/100BaseTX" },
-	{ DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
-		"D-Link DFE-530TX+ 10/100BaseTX" },
-	{ DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
-		"D-Link DFE-690TXD 10/100BaseTX" },
-	{ NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
-		"Nortel Networks 10/100BaseTX" },
-	{ COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
-		"Corega FEther CB-TXD" },
-	{ COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
-		"Corega FEtherII CB-TXD" },
-	{ PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
-		"Peppercon AG ROL-F" },
-	{ PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139,
-		"Planex FNW-3603-TX" },
-	{ PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
-		"Planex FNW-3800-TX" },
-	{ CP_VENDORID, RT_DEVICEID_8139, RL_8139,
-		"Compaq HNE-300" },
-	{ LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
-		"LevelOne FPC-0106TX" },
-	{ EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
-		"Edimax EP-4103DL CardBus" }
-};
-
-static int rl_attach(device_t);
-static int rl_detach(device_t);
-static void rl_dmamap_cb(void *, bus_dma_segment_t *, int, int);
-static int rl_dma_alloc(struct rl_softc *);
-static void rl_dma_free(struct rl_softc *);
-static void rl_eeprom_putbyte(struct rl_softc *, int);
-static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
-static int rl_encap(struct rl_softc *, struct mbuf **);
-static int rl_list_tx_init(struct rl_softc *);
-static int rl_list_rx_init(struct rl_softc *);
-static int rl_ifmedia_upd(struct ifnet *);
-static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
-static int rl_ioctl(struct ifnet *, u_long, caddr_t);
-static void rl_intr(void *);
-static void rl_init(void *);
-static void rl_init_locked(struct rl_softc *sc);
-static int rl_miibus_readreg(device_t, int, int);
-static void rl_miibus_statchg(device_t);
-static int rl_miibus_writereg(device_t, int, int, int);
-#ifdef DEVICE_POLLING
-static int rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
-static int rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
-#endif
-static int rl_probe(device_t);
-static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
-static void rl_reset(struct rl_softc *);
-static int rl_resume(device_t);
-static int rl_rxeof(struct rl_softc *);
-static void rl_rxfilter(struct rl_softc *);
-static int rl_shutdown(device_t);
-static void rl_start(struct ifnet *);
-static void rl_start_locked(struct ifnet *);
-static void rl_stop(struct rl_softc *);
-static int rl_suspend(device_t);
-static void rl_tick(void *);
-static void rl_txeof(struct rl_softc *);
-static void rl_watchdog(struct rl_softc *);
-static void rl_setwol(struct rl_softc *);
-static void rl_clrwol(struct rl_softc *);
-
-/*
- * MII bit-bang glue
- */
-static uint32_t rl_mii_bitbang_read(device_t);
-static void rl_mii_bitbang_write(device_t, uint32_t);
-
-static const struct mii_bitbang_ops rl_mii_bitbang_ops = {
-	rl_mii_bitbang_read,
-	rl_mii_bitbang_write,
-	{
-		RL_MII_DATAOUT,	/* MII_BIT_MDO */
-		RL_MII_DATAIN,	/* MII_BIT_MDI */
-		RL_MII_CLK,	/* MII_BIT_MDC */
-		RL_MII_DIR,	/* MII_BIT_DIR_HOST_PHY */
-		0,		/* MII_BIT_DIR_PHY_HOST */
-	}
-};
-
-static device_method_t rl_methods[] = {
-	/* Device interface */
-	DEVMETHOD(device_probe,		rl_probe),
-	DEVMETHOD(device_attach,	rl_attach),
-	DEVMETHOD(device_detach,	rl_detach),
-	DEVMETHOD(device_suspend,	rl_suspend),
-	DEVMETHOD(device_resume,	rl_resume),
-	DEVMETHOD(device_shutdown,	rl_shutdown),
-
-	/* MII interface */
-	DEVMETHOD(miibus_readreg,	rl_miibus_readreg),
-	DEVMETHOD(miibus_writereg,	rl_miibus_writereg),
-	DEVMETHOD(miibus_statchg,	rl_miibus_statchg),
-
-	DEVMETHOD_END
-};
-
-static driver_t rl_driver = {
-	"rl",
-	rl_methods,
-	sizeof(struct rl_softc)
-};
-
-static devclass_t rl_devclass;
-
-DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
-DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
-DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
-
-#define EE_SET(x)					\
-	CSR_WRITE_1(sc, RL_EECMD,			\
-		CSR_READ_1(sc, RL_EECMD) | x)
-
-#define EE_CLR(x)					\
-	CSR_WRITE_1(sc, RL_EECMD,			\
-		CSR_READ_1(sc, RL_EECMD) & ~x)
-
-/*
- * Send a read command and address to the EEPROM, check for ACK.
- */
-static void
-rl_eeprom_putbyte(struct rl_softc *sc, int addr)
-{
-	register int		d, i;
-
-	d = addr | sc->rl_eecmd_read;
-
-	/*
-	 * Feed in each bit and strobe the clock.
-	 */
-	for (i = 0x400; i; i >>= 1) {
-		if (d & i) {
-			EE_SET(RL_EE_DATAIN);
-		} else {
-			EE_CLR(RL_EE_DATAIN);
-		}
-		DELAY(100);
-		EE_SET(RL_EE_CLK);
-		DELAY(150);
-		EE_CLR(RL_EE_CLK);
-		DELAY(100);
-	}
-}
-
-/*
- * Read a word of data stored in the EEPROM at address 'addr.'
- */
-static void
-rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
-{
-	register int		i;
-	uint16_t		word = 0;
-
-	/* Enter EEPROM access mode. */
-	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
-
-	/*
-	 * Send address of word we want to read.
-	 */
-	rl_eeprom_putbyte(sc, addr);
-
-	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
-
-	/*
-	 * Start reading bits from EEPROM.
-	 */
-	for (i = 0x8000; i; i >>= 1) {
-		EE_SET(RL_EE_CLK);
-		DELAY(100);
-		if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
-			word |= i;
-		EE_CLR(RL_EE_CLK);
-		DELAY(100);
-	}
-
-	/* Turn off EEPROM access mode. */
-	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
-
-	*dest = word;
-}
-
-/*
- * Read a sequence of words from the EEPROM.
- */
-static void
-rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
-{
-	int			i;
-	uint16_t		word = 0, *ptr;
-
-	for (i = 0; i < cnt; i++) {
-		rl_eeprom_getword(sc, off + i, &word);
-		ptr = (uint16_t *)(dest + (i * 2));
-		if (swap)
-			*ptr = ntohs(word);
-		else
-			*ptr = word;
-	}
-}
-
-/*
- * Read the MII serial port for the MII bit-bang module.
- */
-static uint32_t
-rl_mii_bitbang_read(device_t dev)
-{
-	struct rl_softc *sc;
-	uint32_t val;
-
-	sc = device_get_softc(dev);
-
-	val = CSR_READ_1(sc, RL_MII);
-	CSR_BARRIER(sc, RL_MII, 1,
-	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
-
-	return (val);
-}
-
-/*
- * Write the MII serial port for the MII bit-bang module.
- */
-static void
-rl_mii_bitbang_write(device_t dev, uint32_t val)
-{
-	struct rl_softc *sc;
-
-	sc = device_get_softc(dev);
-
-	CSR_WRITE_1(sc, RL_MII, val);
-	CSR_BARRIER(sc, RL_MII, 1,
-	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
-}
-
-static int
-rl_miibus_readreg(device_t dev, int phy, int reg)
-{
-	struct rl_softc		*sc;
-	uint16_t		rl8139_reg;
-
-	sc = device_get_softc(dev);
-
-	if (sc->rl_type == RL_8139) {
-		switch (reg) {
-		case MII_BMCR:
-			rl8139_reg = RL_BMCR;
-			break;
-		case MII_BMSR:
-			rl8139_reg = RL_BMSR;
-			break;
-		case MII_ANAR:
-			rl8139_reg = RL_ANAR;
-			break;
-		case MII_ANER:
-			rl8139_reg = RL_ANER;
-			break;
-		case MII_ANLPAR:
-			rl8139_reg = RL_LPAR;
-			break;
-		case MII_PHYIDR1:
-		case MII_PHYIDR2:
-			return (0);
-		/*
-		 * Allow the rlphy driver to read the media status
-		 * register. If we have a link partner which does not
-		 * support NWAY, this is the register which will tell
-		 * us the results of parallel detection.
-		 */
-		case RL_MEDIASTAT:
-			return (CSR_READ_1(sc, RL_MEDIASTAT));
-		default:
-			device_printf(sc->rl_dev, "bad phy register\n");
-			return (0);
-		}
-		return (CSR_READ_2(sc, rl8139_reg));
-	}
-
-	return (mii_bitbang_readreg(dev, &rl_mii_bitbang_ops, phy, reg));
-}
-
-static int
-rl_miibus_writereg(device_t dev, int phy, int reg, int data)
-{
-	struct rl_softc		*sc;
-	uint16_t		rl8139_reg;
-
-	sc = device_get_softc(dev);
-
-	if (sc->rl_type == RL_8139) {
-		switch (reg) {
-		case MII_BMCR:
-			rl8139_reg = RL_BMCR;
-			break;
-		case MII_BMSR:
-			rl8139_reg = RL_BMSR;
-			break;
-		case MII_ANAR:
-			rl8139_reg = RL_ANAR;
-			break;
-		case MII_ANER:
-			rl8139_reg = RL_ANER;
-			break;
-		case MII_ANLPAR:
-			rl8139_reg = RL_LPAR;
-			break;
-		case MII_PHYIDR1:
-		case MII_PHYIDR2:
-			return (0);
-			break;
-		default:
-			device_printf(sc->rl_dev, "bad phy register\n");
-			return (0);
-		}
-		CSR_WRITE_2(sc, rl8139_reg, data);
-		return (0);
-	}
-
-	mii_bitbang_writereg(dev, &rl_mii_bitbang_ops, phy, reg, data);
-
-	return (0);
-}
-
-static void
-rl_miibus_statchg(device_t dev)
-{
-	struct rl_softc		*sc;
-	struct ifnet		*ifp;
-	struct mii_data		*mii;
-
-	sc = device_get_softc(dev);
-	mii = device_get_softc(sc->rl_miibus);
-	ifp = sc->rl_ifp;
-	if (mii == NULL || ifp == NULL ||
-	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
-		return;
-
-	sc->rl_flags &= ~RL_FLAG_LINK;
-	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
-	    (IFM_ACTIVE | IFM_AVALID)) {
-		switch (IFM_SUBTYPE(mii->mii_media_active)) {
-		case IFM_10_T:
-		case IFM_100_TX:
-			sc->rl_flags |= RL_FLAG_LINK;
-			break;
-		default:
-			break;
-		}
-	}
-	/*
-	 * RealTek controllers do not provide any interface to
-	 * Tx/Rx MACs for resolved speed, duplex and flow-control
-	 * parameters.
-	 */
-}
-
-/*
- * Program the 64-bit multicast hash filter.
- */
-static void
-rl_rxfilter(struct rl_softc *sc)
-{
-	struct ifnet		*ifp = sc->rl_ifp;
-	int			h = 0;
-	uint32_t		hashes[2] = { 0, 0 };
-	struct ifmultiaddr	*ifma;
-	uint32_t		rxfilt;
-
-	RL_LOCK_ASSERT(sc);
-
-	rxfilt = CSR_READ_4(sc, RL_RXCFG);
-	rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_BROAD |
-	    RL_RXCFG_RX_MULTI);
-	/* Always accept frames destined for this host. */
-	rxfilt |= RL_RXCFG_RX_INDIV;
-	/* Set capture broadcast bit to capture broadcast frames. */
-	if (ifp->if_flags & IFF_BROADCAST)
-		rxfilt |= RL_RXCFG_RX_BROAD;
-	if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
-		rxfilt |= RL_RXCFG_RX_MULTI;
-		if (ifp->if_flags & IFF_PROMISC)
-			rxfilt |= RL_RXCFG_RX_ALLPHYS;
-		hashes[0] = 0xFFFFFFFF;
-		hashes[1] = 0xFFFFFFFF;
-	} else {
-		/* Now program new ones. */
-		if_maddr_rlock(ifp);
-		TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
-			if (ifma->ifma_addr->sa_family != AF_LINK)
-				continue;
-			h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
-			    ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
-			if (h < 32)
-				hashes[0] |= (1 << h);
-			else
-				hashes[1] |= (1 << (h - 32));
-		}
-		if_maddr_runlock(ifp);
-		if (hashes[0] != 0 || hashes[1] != 0)
-			rxfilt |= RL_RXCFG_RX_MULTI;
-	}
-
-	CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
-	CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
-	CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
-}
-
-static void
-rl_reset(struct rl_softc *sc)
-{
-	register int		i;
-
-	RL_LOCK_ASSERT(sc);
-
-	CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
-
-	for (i = 0; i < RL_TIMEOUT; i++) {
-		DELAY(10);
-		if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
-			break;
-	}
-	if (i == RL_TIMEOUT)
-		device_printf(sc->rl_dev, "reset never completed!\n");
-}
-
-/*
- * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
- * IDs against our list and return a device name if we find a match.
- */
-static int
-rl_probe(device_t dev)
-{
-	const struct rl_type	*t;
-	uint16_t		devid, revid, vendor;
-	int			i;
-	
-	vendor = pci_get_vendor(dev);
-	devid = pci_get_device(dev);
-	revid = pci_get_revid(dev);
-
-	if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
-		if (revid == 0x20) {
-			/* 8139C+, let re(4) take care of this device. */
-			return (ENXIO);
-		}
-	}
-	t = rl_devs;
-	for (i = 0; i < sizeof(rl_devs) / sizeof(rl_devs[0]); i++, t++) {
-		if (vendor == t->rl_vid && devid == t->rl_did) {
-			device_set_desc(dev, t->rl_name);
-			return (BUS_PROBE_DEFAULT);
-		}
-	}
-
-	return (ENXIO);
-}
-
-struct rl_dmamap_arg {
-	bus_addr_t	rl_busaddr;
-};
-
-static void
-rl_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
-{
-	struct rl_dmamap_arg	*ctx;
-
-	if (error != 0)
-		return;
-
-	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
-
-        ctx = (struct rl_dmamap_arg *)arg;
-        ctx->rl_busaddr = segs[0].ds_addr;
-}
-
-/*
- * Attach the interface. Allocate softc structures, do ifmedia
- * setup and ethernet/BPF attach.
- */
-static int
-rl_attach(device_t dev)
-{
-	uint8_t			eaddr[ETHER_ADDR_LEN];
-	uint16_t		as[3];
-	struct ifnet		*ifp;
-	struct rl_softc		*sc;
-	const struct rl_type	*t;
-	struct sysctl_ctx_list	*ctx;
-	struct sysctl_oid_list	*children;
-	int			error = 0, hwrev, i, phy, pmc, rid;
-	int			prefer_iomap, unit;
-	uint16_t		rl_did = 0;
-	char			tn[32];
-
-	sc = device_get_softc(dev);
-	unit = device_get_unit(dev);
-	sc->rl_dev = dev;
-
-	sc->rl_twister_enable = 0;
-	snprintf(tn, sizeof(tn), "dev.rl.%d.twister_enable", unit);
-	TUNABLE_INT_FETCH(tn, &sc->rl_twister_enable);
-	ctx = device_get_sysctl_ctx(sc->rl_dev);
-	children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
-	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "twister_enable", CTLFLAG_RD,
-	   &sc->rl_twister_enable, 0, "");
-
-	mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
-	    MTX_DEF);
-	callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
-
-	pci_enable_busmaster(dev);
-
-
-	/*
-	 * Map control/status registers.
-	 * Default to using PIO access for this driver. On SMP systems,
-	 * there appear to be problems with memory mapped mode: it looks
-	 * like doing too many memory mapped access back to back in rapid
-	 * succession can hang the bus. I'm inclined to blame this on
-	 * crummy design/construction on the part of RealTek. Memory
-	 * mapped mode does appear to work on uniprocessor systems though.
-	 */
-	prefer_iomap = 1;
-	snprintf(tn, sizeof(tn), "dev.rl.%d.prefer_iomap", unit);
-	TUNABLE_INT_FETCH(tn, &prefer_iomap);
-	if (prefer_iomap) {
-		sc->rl_res_id = PCIR_BAR(0);
-		sc->rl_res_type = SYS_RES_IOPORT;
-		sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
-		    &sc->rl_res_id, RF_ACTIVE);
-	}
-	if (prefer_iomap == 0 || sc->rl_res == NULL) {
-		sc->rl_res_id = PCIR_BAR(1);
-		sc->rl_res_type = SYS_RES_MEMORY;
-		sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
-		    &sc->rl_res_id, RF_ACTIVE);
-	}
-	if (sc->rl_res == NULL) {
-		device_printf(dev, "couldn't map ports/memory\n");
-		error = ENXIO;
-		goto fail;
-	}
-
-#ifdef notdef
-	/*
-	 * Detect the Realtek 8139B. For some reason, this chip is very
-	 * unstable when left to autoselect the media
-	 * The best workaround is to set the device to the required
-	 * media type or to set it to the 10 Meg speed.
-	 */
-	if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
-		device_printf(dev,
-"Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
-#endif
-
-	sc->rl_btag = rman_get_bustag(sc->rl_res);
-	sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
-
-	/* Allocate interrupt */
-	rid = 0;
-	sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
-	    RF_SHAREABLE | RF_ACTIVE);
-
-	if (sc->rl_irq[0] == NULL) {
-		device_printf(dev, "couldn't map interrupt\n");
-		error = ENXIO;
-		goto fail;
-	}
-
-	sc->rl_cfg0 = RL_8139_CFG0;
-	sc->rl_cfg1 = RL_8139_CFG1;
-	sc->rl_cfg2 = 0;
-	sc->rl_cfg3 = RL_8139_CFG3;
-	sc->rl_cfg4 = RL_8139_CFG4;
-	sc->rl_cfg5 = RL_8139_CFG5;
-
-	/*
-	 * Reset the adapter. Only take the lock here as it's needed in
-	 * order to call rl_reset().
-	 */
-	RL_LOCK(sc);
-	rl_reset(sc);
-	RL_UNLOCK(sc);
-
-	sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
-	rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
-	if (rl_did != 0x8129)
-		sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
-
-	/*
-	 * Get station address from the EEPROM.
-	 */
-	rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
-	for (i = 0; i < 3; i++) {
-		eaddr[(i * 2) + 0] = as[i] & 0xff;
-		eaddr[(i * 2) + 1] = as[i] >> 8;
-	}
-
-	/*
-	 * Now read the exact device type from the EEPROM to find
-	 * out if it's an 8129 or 8139.
-	 */
-	rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
-
-	t = rl_devs;
-	sc->rl_type = 0;
-	while(t->rl_name != NULL) {
-		if (rl_did == t->rl_did) {
-			sc->rl_type = t->rl_basetype;
-			break;
-		}
-		t++;
-	}
-
-	if (sc->rl_type == 0) {
-		device_printf(dev, "unknown device ID: %x assuming 8139\n",
-		    rl_did);
-		sc->rl_type = RL_8139;
-		/*
-		 * Read RL_IDR register to get ethernet address as accessing
-		 * EEPROM may not extract correct address.
-		 */
-		for (i = 0; i < ETHER_ADDR_LEN; i++)
-			eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
-	}
-
-	if ((error = rl_dma_alloc(sc)) != 0)
-		goto fail;
-
-	ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
-	if (ifp == NULL) {
-		device_printf(dev, "can not if_alloc()\n");
-		error = ENOSPC;
-		goto fail;
-	}
-
-#define	RL_PHYAD_INTERNAL	0
-
-	/* Do MII setup */
-	phy = MII_PHY_ANY;
-	if (sc->rl_type == RL_8139)
-		phy = RL_PHYAD_INTERNAL;
-	error = mii_attach(dev, &sc->rl_miibus, ifp, rl_ifmedia_upd,
-	    rl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
-	if (error != 0) {
-		device_printf(dev, "attaching PHYs failed\n");
-		goto fail;
-	}
-
-	ifp->if_softc = sc;
-	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
-	ifp->if_mtu = ETHERMTU;
-	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
-	ifp->if_ioctl = rl_ioctl;
-	ifp->if_start = rl_start;
-	ifp->if_init = rl_init;
-	ifp->if_capabilities = IFCAP_VLAN_MTU;
-	/* Check WOL for RTL8139B or newer controllers. */
-	if (sc->rl_type == RL_8139 &&
-	    pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
-		hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
-		switch (hwrev) {
-		case RL_HWREV_8139B:
-		case RL_HWREV_8130:
-		case RL_HWREV_8139C:
-		case RL_HWREV_8139D:
-		case RL_HWREV_8101:
-		case RL_HWREV_8100:
-			ifp->if_capabilities |= IFCAP_WOL;
-			/* Disable WOL. */
-			rl_clrwol(sc);
-			break;
-		default:
-			break;
-		}
-	}
-	ifp->if_capenable = ifp->if_capabilities;
-	ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST);
-#ifdef DEVICE_POLLING
-	ifp->if_capabilities |= IFCAP_POLLING;
-#endif
-	IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
-	ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
-	IFQ_SET_READY(&ifp->if_snd);
-
-	/*
-	 * Call MI attach routine.
-	 */
-	ether_ifattach(ifp, eaddr);
-
-	/* Hook interrupt last to avoid having to lock softc */
-	error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE,
-	    NULL, rl_intr, sc, &sc->rl_intrhand[0]);
-	if (error) {
-		device_printf(sc->rl_dev, "couldn't set up irq\n");
-		ether_ifdetach(ifp);
-	}
-
-fail:
-	if (error)
-		rl_detach(dev);
-
-	return (error);
-}
-
-/*
- * Shutdown hardware and free up resources. This can be called any
- * time after the mutex has been initialized. It is called in both
- * the error case in attach and the normal detach case so it needs
- * to be careful about only freeing resources that have actually been
- * allocated.
- */
-static int
-rl_detach(device_t dev)
-{
-	struct rl_softc		*sc;
-	struct ifnet		*ifp;
-
-	sc = device_get_softc(dev);
-	ifp = sc->rl_ifp;
-
-	KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
-
-#ifdef DEVICE_POLLING
-	if (ifp->if_capenable & IFCAP_POLLING)
-		ether_poll_deregister(ifp);
-#endif
-	/* These should only be active if attach succeeded */
-	if (device_is_attached(dev)) {
-		RL_LOCK(sc);
-		rl_stop(sc);
-		RL_UNLOCK(sc);
-		callout_drain(&sc->rl_stat_callout);
-		ether_ifdetach(ifp);
-	}
-#if 0
-	sc->suspended = 1;
-#endif
-	if (sc->rl_miibus)
-		device_delete_child(dev, sc->rl_miibus);
-	bus_generic_detach(dev);
-
-	if (sc->rl_intrhand[0])
-		bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
-	if (sc->rl_irq[0])
-		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]);
-	if (sc->rl_res)
-		bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
-		    sc->rl_res);
-
-	if (ifp)
-		if_free(ifp);
-
-	rl_dma_free(sc);
-
-	mtx_destroy(&sc->rl_mtx);
-
-	return (0);
-}
-
-static int
-rl_dma_alloc(struct rl_softc *sc)
-{
-	struct rl_dmamap_arg	ctx;
-	int			error, i;
-
-	/*
-	 * Allocate the parent bus DMA tag appropriate for PCI.
-	 */
-	error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev),	/* parent */
-	    1, 0,			/* alignment, boundary */
-	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
-	    BUS_SPACE_MAXADDR,		/* highaddr */
-	    NULL, NULL,			/* filter, filterarg */
-	    BUS_SPACE_MAXSIZE_32BIT, 0,	/* maxsize, nsegments */
-	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
-	    0,				/* flags */
-	    NULL, NULL,			/* lockfunc, lockarg */
-	    &sc->rl_parent_tag);
-	if (error) {
-                device_printf(sc->rl_dev,
-		    "failed to create parent DMA tag.\n");
-		goto fail;
-	}
-	/* Create DMA tag for Rx memory block. */
-	error = bus_dma_tag_create(sc->rl_parent_tag,	/* parent */
-	    RL_RX_8139_BUF_ALIGN, 0,	/* alignment, boundary */
-	    BUS_SPACE_MAXADDR,		/* lowaddr */
-	    BUS_SPACE_MAXADDR,		/* highaddr */
-	    NULL, NULL,			/* filter, filterarg */
-	    RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, 1,	/* maxsize,nsegments */
-	    RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ,	/* maxsegsize */
-	    0,				/* flags */
-	    NULL, NULL,			/* lockfunc, lockarg */
-	    &sc->rl_cdata.rl_rx_tag);
-	if (error) {
-                device_printf(sc->rl_dev,
-		    "failed to create Rx memory block DMA tag.\n");
-		goto fail;
-	}
-	/* Create DMA tag for Tx buffer. */
-	error = bus_dma_tag_create(sc->rl_parent_tag,	/* parent */
-	    RL_TX_8139_BUF_ALIGN, 0,	/* alignment, boundary */
-	    BUS_SPACE_MAXADDR,		/* lowaddr */
-	    BUS_SPACE_MAXADDR,		/* highaddr */
-	    NULL, NULL,			/* filter, filterarg */
-	    MCLBYTES, 1,		/* maxsize, nsegments */
-	    MCLBYTES,			/* maxsegsize */
-	    0,				/* flags */
-	    NULL, NULL,			/* lockfunc, lockarg */
-	    &sc->rl_cdata.rl_tx_tag);
-	if (error) {
-                device_printf(sc->rl_dev, "failed to create Tx DMA tag.\n");
-		goto fail;
-	}
-
-	/*
-	 * Allocate DMA'able memory and load DMA map for Rx memory block.
-	 */
-	error = bus_dmamem_alloc(sc->rl_cdata.rl_rx_tag,
-	    (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_WAITOK |
-	    BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->rl_cdata.rl_rx_dmamap);
-	if (error != 0) {
-		device_printf(sc->rl_dev,
-		    "failed to allocate Rx DMA memory block.\n");
-		goto fail;
-	}
-	ctx.rl_busaddr = 0;
-	error = bus_dmamap_load(sc->rl_cdata.rl_rx_tag,
-	    sc->rl_cdata.rl_rx_dmamap, sc->rl_cdata.rl_rx_buf,
-	    RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, rl_dmamap_cb, &ctx,
-	    BUS_DMA_NOWAIT);
-	if (error != 0 || ctx.rl_busaddr == 0) {
-		device_printf(sc->rl_dev,
-		    "could not load Rx DMA memory block.\n");
-		goto fail;
-	}
-	sc->rl_cdata.rl_rx_buf_paddr = ctx.rl_busaddr;
-
-	/* Create DMA maps for Tx buffers. */
-	for (i = 0; i < RL_TX_LIST_CNT; i++) {
-		sc->rl_cdata.rl_tx_chain[i] = NULL;
-		sc->rl_cdata.rl_tx_dmamap[i] = NULL;
-		error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 0,
-		    &sc->rl_cdata.rl_tx_dmamap[i]);
-		if (error != 0) {
-			device_printf(sc->rl_dev,
-			    "could not create Tx dmamap.\n");
-			goto fail;
-		}
-	}
-
-	/* Leave a few bytes before the start of the RX ring buffer. */
-	sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
-	sc->rl_cdata.rl_rx_buf += RL_RX_8139_BUF_RESERVE;
-
-fail:
-	return (error);
-}
-
-static void
-rl_dma_free(struct rl_softc *sc)
-{
-	int			i;
-
-	/* Rx memory block. */
-	if (sc->rl_cdata.rl_rx_tag != NULL) {
-		if (sc->rl_cdata.rl_rx_dmamap != NULL)
-			bus_dmamap_unload(sc->rl_cdata.rl_rx_tag,
-			    sc->rl_cdata.rl_rx_dmamap);
-		if (sc->rl_cdata.rl_rx_dmamap != NULL &&
-		    sc->rl_cdata.rl_rx_buf_ptr != NULL)
-			bus_dmamem_free(sc->rl_cdata.rl_rx_tag,
-			    sc->rl_cdata.rl_rx_buf_ptr,
-			    sc->rl_cdata.rl_rx_dmamap);
-		sc->rl_cdata.rl_rx_buf_ptr = NULL;
-		sc->rl_cdata.rl_rx_buf = NULL;
-		sc->rl_cdata.rl_rx_dmamap = NULL;
-		bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag);
-		sc->rl_cdata.rl_tx_tag = NULL;
-	}
-
-	/* Tx buffers. */
-	if (sc->rl_cdata.rl_tx_tag != NULL) {
-		for (i = 0; i < RL_TX_LIST_CNT; i++) {
-			if (sc->rl_cdata.rl_tx_dmamap[i] != NULL) {
-				bus_dmamap_destroy(
-				    sc->rl_cdata.rl_tx_tag,
-				    sc->rl_cdata.rl_tx_dmamap[i]);
-				sc->rl_cdata.rl_tx_dmamap[i] = NULL;
-			}
-		}
-		bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag);
-		sc->rl_cdata.rl_tx_tag = NULL;
-	}
-
-	if (sc->rl_parent_tag != NULL) {
-		bus_dma_tag_destroy(sc->rl_parent_tag);
-		sc->rl_parent_tag = NULL;
-	}
-}
-
-/*
- * Initialize the transmit descriptors.
- */
-static int
-rl_list_tx_init(struct rl_softc *sc)
-{
-	struct rl_chain_data	*cd;
-	int			i;
-
-	RL_LOCK_ASSERT(sc);
-
-	cd = &sc->rl_cdata;
-	for (i = 0; i < RL_TX_LIST_CNT; i++) {
-		cd->rl_tx_chain[i] = NULL;
-		CSR_WRITE_4(sc,
-		    RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
-	}
-
-	sc->rl_cdata.cur_tx = 0;
-	sc->rl_cdata.last_tx = 0;
-
-	return (0);
-}
-
-static int
-rl_list_rx_init(struct rl_softc *sc)
-{
-
-	RL_LOCK_ASSERT(sc);
-
-	bzero(sc->rl_cdata.rl_rx_buf_ptr,
-	    RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ);
-	bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, sc->rl_cdata.rl_rx_dmamap,
-	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
-
-	return (0);
-}
-
-/*
- * A frame has been uploaded: pass the resulting mbuf chain up to
- * the higher level protocols.
- *
- * You know there's something wrong with a PCI bus-master chip design
- * when you have to use m_devget().
- *
- * The receive operation is badly documented in the datasheet, so I'll
- * attempt to document it here. The driver provides a buffer area and
- * places its base address in the RX buffer start address register.
- * The chip then begins copying frames into the RX buffer. Each frame
- * is preceded by a 32-bit RX status word which specifies the length
- * of the frame and certain other status bits. Each frame (starting with
- * the status word) is also 32-bit aligned. The frame length is in the
- * first 16 bits of the status word; the lower 15 bits correspond with
- * the 'rx status register' mentioned in the datasheet.
- *
- * Note: to make the Alpha happy, the frame payload needs to be aligned
- * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
- * as the offset argument to m_devget().
- */
-static int
-rl_rxeof(struct rl_softc *sc)
-{
-	struct mbuf		*m;
-	struct ifnet		*ifp = sc->rl_ifp;
-	uint8_t			*rxbufpos;
-	int			total_len = 0;
-	int			wrap = 0;
-	int			rx_npkts = 0;
-	uint32_t		rxstat;
-	uint16_t		cur_rx;
-	uint16_t		limit;
-	uint16_t		max_bytes, rx_bytes = 0;
-
-	RL_LOCK_ASSERT(sc);
-
-	bus_dmamap_sync(sc->rl_cdata.rl_rx_tag, sc->rl_cdata.rl_rx_dmamap,
-	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
-
-	cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
-
-	/* Do not try to read past this point. */
-	limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
-
-	if (limit < cur_rx)
-		max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
-	else
-		max_bytes = limit - cur_rx;
-
-	while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
-#ifdef DEVICE_POLLING
-		if (ifp->if_capenable & IFCAP_POLLING) {
-			if (sc->rxcycles <= 0)
-				break;
-			sc->rxcycles--;
-		}
-#endif
-		rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
-		rxstat = le32toh(*(uint32_t *)rxbufpos);
-
-		/*
-		 * Here's a totally undocumented fact for you. When the
-		 * RealTek chip is in the process of copying a packet into
-		 * RAM for you, the length will be 0xfff0. If you spot a
-		 * packet header with this value, you need to stop. The
-		 * datasheet makes absolutely no mention of this and
-		 * RealTek should be shot for this.
-		 */
-		total_len = rxstat >> 16;
-		if (total_len == RL_RXSTAT_UNFINISHED)
-			break;
-
-		if (!(rxstat & RL_RXSTAT_RXOK) ||
-		    total_len < ETHER_MIN_LEN ||
-		    total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) {
-			ifp->if_ierrors++;
-			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
-			rl_init_locked(sc);
-			return (rx_npkts);
-		}
-
-		/* No errors; receive the packet. */
-		rx_bytes += total_len + 4;
-
-		/*
-		 * XXX The RealTek chip includes the CRC with every
-		 * received frame, and there's no way to turn this
-		 * behavior off (at least, I can't find anything in
-		 * the manual that explains how to do it) so we have
-		 * to trim off the CRC manually.
-		 */
-		total_len -= ETHER_CRC_LEN;
-
-		/*
-		 * Avoid trying to read more bytes than we know
-		 * the chip has prepared for us.
-		 */
-		if (rx_bytes > max_bytes)
-			break;
-
-		rxbufpos = sc->rl_cdata.rl_rx_buf +
-			((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
-		if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
-			rxbufpos = sc->rl_cdata.rl_rx_buf;
-
-		wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
-		if (total_len > wrap) {
-			m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
-			    NULL);
-			if (m != NULL)
-				m_copyback(m, wrap, total_len - wrap,
-					sc->rl_cdata.rl_rx_buf);
-			cur_rx = (total_len - wrap + ETHER_CRC_LEN);
-		} else {
-			m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
-			    NULL);
-			cur_rx += total_len + 4 + ETHER_CRC_LEN;
-		}
-
-		/* Round up to 32-bit boundary. */
-		cur_rx = (cur_rx + 3) & ~3;
-		CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
-
-		if (m == NULL) {
-			ifp->if_iqdrops++;
-			continue;
-		}
-
-		ifp->if_ipackets++;
-		RL_UNLOCK(sc);
-		(*ifp->if_input)(ifp, m);
-		RL_LOCK(sc);
-		rx_npkts++;
-	}
-
-	/* No need to sync Rx memory block as we didn't modify it. */
-	return (rx_npkts);
-}
-
-/*
- * A frame was downloaded to the chip. It's safe for us to clean up
- * the list buffers.
- */
-static void
-rl_txeof(struct rl_softc *sc)
-{
-	struct ifnet		*ifp = sc->rl_ifp;
-	uint32_t		txstat;
-
-	RL_LOCK_ASSERT(sc);
-
-	/*
-	 * Go through our tx list and free mbufs for those
-	 * frames that have been uploaded.
-	 */
-	do {
-		if (RL_LAST_TXMBUF(sc) == NULL)
-			break;
-		txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
-		if (!(txstat & (RL_TXSTAT_TX_OK|
-		    RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
-			break;
-
-		ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
-
-		bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc),
-		    BUS_DMASYNC_POSTWRITE);
-		bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc));
-		m_freem(RL_LAST_TXMBUF(sc));
-		RL_LAST_TXMBUF(sc) = NULL;
-		/*
-		 * If there was a transmit underrun, bump the TX threshold.
-		 * Make sure not to overflow the 63 * 32byte we can address
-		 * with the 6 available bit.
-		 */
-		if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
-		    (sc->rl_txthresh < 2016))
-			sc->rl_txthresh += 32;
-		if (txstat & RL_TXSTAT_TX_OK)
-			ifp->if_opackets++;
-		else {
-			int			oldthresh;
-			ifp->if_oerrors++;
-			if ((txstat & RL_TXSTAT_TXABRT) ||
-			    (txstat & RL_TXSTAT_OUTOFWIN))
-				CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
-			oldthresh = sc->rl_txthresh;
-			/* error recovery */
-			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
-			rl_init_locked(sc);
-			/* restore original threshold */
-			sc->rl_txthresh = oldthresh;
-			return;
-		}
-		RL_INC(sc->rl_cdata.last_tx);
-		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
-	} while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
-
-	if (RL_LAST_TXMBUF(sc) == NULL)
-		sc->rl_watchdog_timer = 0;
-}
-
-static void
-rl_twister_update(struct rl_softc *sc)
-{
-	uint16_t linktest;
-	/*
-	 * Table provided by RealTek (Kinston <shangh@realtek.com.tw>) for
-	 * Linux driver.  Values undocumented otherwise.
-	 */
-	static const uint32_t param[4][4] = {
-		{0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
-		{0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
-		{0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
-		{0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
-	};
-
-	/*
-	 * Tune the so-called twister registers of the RTL8139.  These
-	 * are used to compensate for impedance mismatches.  The
-	 * method for tuning these registers is undocumented and the
-	 * following procedure is collected from public sources.
-	 */
-	switch (sc->rl_twister)
-	{
-	case CHK_LINK:
-		/*
-		 * If we have a sufficient link, then we can proceed in
-		 * the state machine to the next stage.  If not, then
-		 * disable further tuning after writing sane defaults.
-		 */
-		if (CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_LINK_OK) {
-			CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD);
-			sc->rl_twister = FIND_ROW;
-		} else {
-			CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD);
-			CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
-			CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
-			CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
-			sc->rl_twister = DONE;
-		}
-		break;
-	case FIND_ROW:
-		/*
-		 * Read how long it took to see the echo to find the tuning
-		 * row to use.
-		 */
-		linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
-		if (linktest == RL_CSCFG_ROW3)
-			sc->rl_twist_row = 3;
-		else if (linktest == RL_CSCFG_ROW2)
-			sc->rl_twist_row = 2;
-		else if (linktest == RL_CSCFG_ROW1)
-			sc->rl_twist_row = 1;
-		else
-			sc->rl_twist_row = 0;
-		sc->rl_twist_col = 0;
-		sc->rl_twister = SET_PARAM;
-		break;
-	case SET_PARAM:
-		if (sc->rl_twist_col == 0)
-			CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
-		CSR_WRITE_4(sc, RL_PARA7C,
-		    param[sc->rl_twist_row][sc->rl_twist_col]);
-		if (++sc->rl_twist_col == 4) {
-			if (sc->rl_twist_row == 3)
-				sc->rl_twister = RECHK_LONG;
-			else
-				sc->rl_twister = DONE;
-		}
-		break;
-	case RECHK_LONG:
-		/*
-		 * For long cables, we have to double check to make sure we
-		 * don't mistune.
-		 */
-		linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
-		if (linktest == RL_CSCFG_ROW3)
-			sc->rl_twister = DONE;
-		else {
-			CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_RETUNE);
-			sc->rl_twister = RETUNE;
-		}
-		break;
-	case RETUNE:
-		/* Retune for a shorter cable (try column 2) */
-		CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
-		CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
-		CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
-		CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
-		sc->rl_twist_row--;
-		sc->rl_twist_col = 0;
-		sc->rl_twister = SET_PARAM;
-		break;
-
-	case DONE:
-		break;
-	}
-	
-}
-
-static void
-rl_tick(void *xsc)
-{
-	struct rl_softc		*sc = xsc;
-	struct mii_data		*mii;
-	int ticks;
-
-	RL_LOCK_ASSERT(sc);
-	/*
-	 * If we're doing the twister cable calibration, then we need to defer
-	 * watchdog timeouts.  This is a no-op in normal operations, but
-	 * can falsely trigger when the cable calibration takes a while and
-	 * there was traffic ready to go when rl was started.
-	 *
-	 * We don't defer mii_tick since that updates the mii status, which
-	 * helps the twister process, at least according to similar patches
-	 * for the Linux driver I found online while doing the fixes.  Worst
-	 * case is a few extra mii reads during calibration.
-	 */
-	mii = device_get_softc(sc->rl_miibus);
-	mii_tick(mii);
-	if ((sc->rl_flags & RL_FLAG_LINK) == 0)
-		rl_miibus_statchg(sc->rl_dev);
-	if (sc->rl_twister_enable) {
-		if (sc->rl_twister == DONE)
-			rl_watchdog(sc);
-		else
-			rl_twister_update(sc);
-		if (sc->rl_twister == DONE)
-			ticks = hz;
-		else
-			ticks = hz / 10;
-	} else {
-		rl_watchdog(sc);
-		ticks = hz;
-	}
-
-	callout_reset(&sc->rl_stat_callout, ticks, rl_tick, sc);
-}
-
-#ifdef DEVICE_POLLING
-static int
-rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
-{
-	struct rl_softc *sc = ifp->if_softc;
-	int rx_npkts = 0;
-
-	RL_LOCK(sc);
-	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
-		rx_npkts = rl_poll_locked(ifp, cmd, count);
-	RL_UNLOCK(sc);
-	return (rx_npkts);
-}
-
-static int
-rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
-{
-	struct rl_softc *sc = ifp->if_softc;
-	int rx_npkts;
-
-	RL_LOCK_ASSERT(sc);
-
-	sc->rxcycles = count;
-	rx_npkts = rl_rxeof(sc);
-	rl_txeof(sc);
-
-	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
-		rl_start_locked(ifp);
-
-	if (cmd == POLL_AND_CHECK_STATUS) {
-		uint16_t	status;
-
-		/* We should also check the status register. */
-		status = CSR_READ_2(sc, RL_ISR);
-		if (status == 0xffff)
-			return (rx_npkts);
-		if (status != 0)
-			CSR_WRITE_2(sc, RL_ISR, status);
-
-		/* XXX We should check behaviour on receiver stalls. */
-
-		if (status & RL_ISR_SYSTEM_ERR) {
-			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
-			rl_init_locked(sc);
-		}
-	}
-	return (rx_npkts);
-}
-#endif /* DEVICE_POLLING */
-
-static void
-rl_intr(void *arg)
-{
-	struct rl_softc		*sc = arg;
-	struct ifnet		*ifp = sc->rl_ifp;
-	uint16_t		status;
-	int			count;
-
-	RL_LOCK(sc);
-
-	if (sc->suspended)
-		goto done_locked;
-
-#ifdef DEVICE_POLLING
-	if  (ifp->if_capenable & IFCAP_POLLING)
-		goto done_locked;
-#endif
-
-	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
-		goto done_locked2;
-	status = CSR_READ_2(sc, RL_ISR);
-	if (status == 0xffff || (status & RL_INTRS) == 0)
-		goto done_locked;
-	/*
-	 * Ours, disable further interrupts.
-	 */
-	CSR_WRITE_2(sc, RL_IMR, 0);
-	for (count = 16; count > 0; count--) {
-		CSR_WRITE_2(sc, RL_ISR, status);
-		if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
-			if (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR))
-				rl_rxeof(sc);
-			if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR))
-				rl_txeof(sc);
-			if (status & RL_ISR_SYSTEM_ERR) {
-				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
-				rl_init_locked(sc);
-				RL_UNLOCK(sc);
-				return;
-			}
-		}
-		status = CSR_READ_2(sc, RL_ISR);
-		/* If the card has gone away, the read returns 0xffff. */
-		if (status == 0xffff || (status & RL_INTRS) == 0)
-			break;
-	}
-
-	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
-		rl_start_locked(ifp);
-
-done_locked2:
-	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
-		CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
-done_locked:
-	RL_UNLOCK(sc);
-}
-
-/*
- * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
- * pointers to the fragment pointers.
- */
-static int
-rl_encap(struct rl_softc *sc, struct mbuf **m_head)
-{
-	struct mbuf		*m;
-	bus_dma_segment_t	txsegs[1];
-	int			error, nsegs, padlen;
-
-	RL_LOCK_ASSERT(sc);
-
-	m = *m_head;
-	padlen = 0;
-	/*
-	 * Hardware doesn't auto-pad, so we have to make sure
-	 * pad short frames out to the minimum frame length.
-	 */
-	if (m->m_pkthdr.len < RL_MIN_FRAMELEN)
-		padlen = RL_MIN_FRAMELEN - m->m_pkthdr.len;
-	/*
-	 * The RealTek is brain damaged and wants longword-aligned
-	 * TX buffers, plus we can only have one fragment buffer
-	 * per packet. We have to copy pretty much all the time.
-	 */
-	if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0 ||
-	    (padlen > 0 && M_TRAILINGSPACE(m) < padlen)) {
-		m = m_defrag(*m_head, M_DONTWAIT);
-		if (m == NULL) {
-			m_freem(*m_head);
-			*m_head = NULL;
-			return (ENOMEM);
-		}
-	}
-	*m_head = m;
-
-	if (padlen > 0) {
-		/*
-		 * Make security-conscious people happy: zero out the
-		 * bytes in the pad area, since we don't know what
-		 * this mbuf cluster buffer's previous user might
-		 * have left in it.
-		 */
-		bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
-		m->m_pkthdr.len += padlen;
-		m->m_len = m->m_pkthdr.len;
-	}
-
-	error = bus_dmamap_load_mbuf_sg(sc->rl_cdata.rl_tx_tag,
-	    RL_CUR_DMAMAP(sc), m, txsegs, &nsegs, 0);
-	if (error != 0)
-		return (error);
-	if (nsegs == 0) {
-		m_freem(*m_head);
-		*m_head = NULL;
-		return (EIO);
-	}
-
-	RL_CUR_TXMBUF(sc) = m;
-	bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc),
-	    BUS_DMASYNC_PREWRITE);
-	CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), RL_ADDR_LO(txsegs[0].ds_addr));
-
-	return (0);
-}
-
-/*
- * Main transmit routine.
- */
-static void
-rl_start(struct ifnet *ifp)
-{
-	struct rl_softc		*sc = ifp->if_softc;
-
-	RL_LOCK(sc);
-	rl_start_locked(ifp);
-	RL_UNLOCK(sc);
-}
-
-static void
-rl_start_locked(struct ifnet *ifp)
-{
-	struct rl_softc		*sc = ifp->if_softc;
-	struct mbuf		*m_head = NULL;
-
-	RL_LOCK_ASSERT(sc);
-
-	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
-	    IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
-		return;
-
-	while (RL_CUR_TXMBUF(sc) == NULL) {
-
-		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
-
-		if (m_head == NULL)
-			break;
-
-		if (rl_encap(sc, &m_head)) {
-			if (m_head == NULL)
-				break;
-			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
-			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
-			break;
-		}
-
-		/* Pass a copy of this mbuf chain to the bpf subsystem. */
-		BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
-
-		/* Transmit the frame. */
-		CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
-		    RL_TXTHRESH(sc->rl_txthresh) |
-		    RL_CUR_TXMBUF(sc)->m_pkthdr.len);
-
-		RL_INC(sc->rl_cdata.cur_tx);
-
-		/* Set a timeout in case the chip goes out to lunch. */
-		sc->rl_watchdog_timer = 5;
-	}
-
-	/*
-	 * We broke out of the loop because all our TX slots are
-	 * full. Mark the NIC as busy until it drains some of the
-	 * packets from the queue.
-	 */
-	if (RL_CUR_TXMBUF(sc) != NULL)
-		ifp->if_drv_flags |= IFF_DRV_OACTIVE;
-}
-
-static void
-rl_init(void *xsc)
-{
-	struct rl_softc		*sc = xsc;
-
-	RL_LOCK(sc);
-	rl_init_locked(sc);
-	RL_UNLOCK(sc);
-}
-
-static void
-rl_init_locked(struct rl_softc *sc)
-{
-	struct ifnet		*ifp = sc->rl_ifp;
-	struct mii_data		*mii;
-	uint32_t		eaddr[2];
-
-	RL_LOCK_ASSERT(sc);
-
-	mii = device_get_softc(sc->rl_miibus);
-
-	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
-		return;
-
-	/*
-	 * Cancel pending I/O and free all RX/TX buffers.
-	 */
-	rl_stop(sc);
-
-	rl_reset(sc);
-	if (sc->rl_twister_enable) {
-		/*
-		 * Reset twister register tuning state.  The twister
-		 * registers and their tuning are undocumented, but
-		 * are necessary to cope with bad links.  rl_twister =
-		 * DONE here will disable this entirely.
-		 */
-		sc->rl_twister = CHK_LINK;
-	}
-
-	/*
-	 * Init our MAC address.  Even though the chipset
-	 * documentation doesn't mention it, we need to enter "Config
-	 * register write enable" mode to modify the ID registers.
-	 */
-	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
-	bzero(eaddr, sizeof(eaddr));
-	bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN);
-	CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]);
-	CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]);
-	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
-
-	/* Init the RX memory block pointer register. */
-	CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr +
-	    RL_RX_8139_BUF_RESERVE);
-	/* Init TX descriptors. */
-	rl_list_tx_init(sc);
-	/* Init Rx memory block. */
-	rl_list_rx_init(sc);
-
-	/*
-	 * Enable transmit and receive.
-	 */
-	CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
-
-	/*
-	 * Set the initial TX and RX configuration.
-	 */
-	CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
-	CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
-
-	/* Set RX filter. */
-	rl_rxfilter(sc);
-
-#ifdef DEVICE_POLLING
-	/* Disable interrupts if we are polling. */
-	if (ifp->if_capenable & IFCAP_POLLING)
-		CSR_WRITE_2(sc, RL_IMR, 0);
-	else
-#endif
-	/* Enable interrupts. */
-	CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
-
-	/* Set initial TX threshold */
-	sc->rl_txthresh = RL_TX_THRESH_INIT;
-
-	/* Start RX/TX process. */
-	CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
-
-	/* Enable receiver and transmitter. */
-	CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
-
-	sc->rl_flags &= ~RL_FLAG_LINK;
-	mii_mediachg(mii);
-
-	CSR_WRITE_1(sc, sc->rl_cfg1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
-
-	ifp->if_drv_flags |= IFF_DRV_RUNNING;
-	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
-
-	callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
-}
-
-/*
- * Set media options.
- */
-static int
-rl_ifmedia_upd(struct ifnet *ifp)
-{
-	struct rl_softc		*sc = ifp->if_softc;
-	struct mii_data		*mii;
-
-	mii = device_get_softc(sc->rl_miibus);
-
-	RL_LOCK(sc);
-	mii_mediachg(mii);
-	RL_UNLOCK(sc);
-
-	return (0);
-}
-
-/*
- * Report current media status.
- */
-static void
-rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
-{
-	struct rl_softc		*sc = ifp->if_softc;
-	struct mii_data		*mii;
-
-	mii = device_get_softc(sc->rl_miibus);
-
-	RL_LOCK(sc);
-	mii_pollstat(mii);
-	ifmr->ifm_active = mii->mii_media_active;
-	ifmr->ifm_status = mii->mii_media_status;
-	RL_UNLOCK(sc);
-}
-
-static int
-rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
-{
-	struct ifreq		*ifr = (struct ifreq *)data;
-	struct mii_data		*mii;
-	struct rl_softc		*sc = ifp->if_softc;
-	int			error = 0, mask;
-
-	switch (command) {
-	case SIOCSIFFLAGS:
-		RL_LOCK(sc);
-		if (ifp->if_flags & IFF_UP) {
-			if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
-			    ((ifp->if_flags ^ sc->rl_if_flags) &
-                            (IFF_PROMISC | IFF_ALLMULTI)))
-				rl_rxfilter(sc);
-                        else
-				rl_init_locked(sc);
-                } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
-			rl_stop(sc);
-		sc->rl_if_flags = ifp->if_flags;
-		RL_UNLOCK(sc);
-		break;
-	case SIOCADDMULTI:
-	case SIOCDELMULTI:
-		RL_LOCK(sc);
-		rl_rxfilter(sc);
-		RL_UNLOCK(sc);
-		break;
-	case SIOCGIFMEDIA:
-	case SIOCSIFMEDIA:
-		mii = device_get_softc(sc->rl_miibus);
-		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
-		break;
-	case SIOCSIFCAP:
-		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
-#ifdef DEVICE_POLLING
-		if (ifr->ifr_reqcap & IFCAP_POLLING &&
-		    !(ifp->if_capenable & IFCAP_POLLING)) {
-			error = ether_poll_register(rl_poll, ifp);
-			if (error)
-				return(error);
-			RL_LOCK(sc);
-			/* Disable interrupts */
-			CSR_WRITE_2(sc, RL_IMR, 0x0000);
-			ifp->if_capenable |= IFCAP_POLLING;
-			RL_UNLOCK(sc);
-			return (error);
-			
-		}
-		if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
-		    ifp->if_capenable & IFCAP_POLLING) {
-			error = ether_poll_deregister(ifp);
-			/* Enable interrupts. */
-			RL_LOCK(sc);
-			CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
-			ifp->if_capenable &= ~IFCAP_POLLING;
-			RL_UNLOCK(sc);
-			return (error);
-		}
-#endif /* DEVICE_POLLING */
-		if ((mask & IFCAP_WOL) != 0 &&
-		    (ifp->if_capabilities & IFCAP_WOL) != 0) {
-			if ((mask & IFCAP_WOL_UCAST) != 0)
-				ifp->if_capenable ^= IFCAP_WOL_UCAST;
-			if ((mask & IFCAP_WOL_MCAST) != 0)
-				ifp->if_capenable ^= IFCAP_WOL_MCAST;
-			if ((mask & IFCAP_WOL_MAGIC) != 0)
-				ifp->if_capenable ^= IFCAP_WOL_MAGIC;
-		}
-		break;
-	default:
-		error = ether_ioctl(ifp, command, data);
-		break;
-	}
-
-	return (error);
-}
-
-static void
-rl_watchdog(struct rl_softc *sc)
-{
-
-	RL_LOCK_ASSERT(sc);
-
-	if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0)
-		return;
-
-	device_printf(sc->rl_dev, "watchdog timeout\n");
-	sc->rl_ifp->if_oerrors++;
-
-	rl_txeof(sc);
-	rl_rxeof(sc);
-	sc->rl_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
-	rl_init_locked(sc);
-}
-
-/*
- * Stop the adapter and free any mbufs allocated to the
- * RX and TX lists.
- */
-static void
-rl_stop(struct rl_softc *sc)
-{
-	register int		i;
-	struct ifnet		*ifp = sc->rl_ifp;
-
-	RL_LOCK_ASSERT(sc);
-
-	sc->rl_watchdog_timer = 0;
-	callout_stop(&sc->rl_stat_callout);
-	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
-	sc->rl_flags &= ~RL_FLAG_LINK;
-
-	CSR_WRITE_1(sc, RL_COMMAND, 0x00);
-	CSR_WRITE_2(sc, RL_IMR, 0x0000);
-	for (i = 0; i < RL_TIMEOUT; i++) {
-		DELAY(10);
-		if ((CSR_READ_1(sc, RL_COMMAND) &
-		    (RL_CMD_RX_ENB | RL_CMD_TX_ENB)) == 0)
-			break;
-	}
-	if (i == RL_TIMEOUT)
-		device_printf(sc->rl_dev, "Unable to stop Tx/Rx MAC\n");
-
-	/*
-	 * Free the TX list buffers.
-	 */
-	for (i = 0; i < RL_TX_LIST_CNT; i++) {
-		if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
-			if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
-				bus_dmamap_sync(sc->rl_cdata.rl_tx_tag,
-				    sc->rl_cdata.rl_tx_dmamap[i],
-				    BUS_DMASYNC_POSTWRITE);
-				bus_dmamap_unload(sc->rl_cdata.rl_tx_tag,
-				    sc->rl_cdata.rl_tx_dmamap[i]);
-				m_freem(sc->rl_cdata.rl_tx_chain[i]);
-				sc->rl_cdata.rl_tx_chain[i] = NULL;
-			}
-			CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
-			    0x0000000);
-		}
-	}
-}
-
-/*
- * Device suspend routine.  Stop the interface and save some PCI
- * settings in case the BIOS doesn't restore them properly on
- * resume.
- */
-static int
-rl_suspend(device_t dev)
-{
-	struct rl_softc		*sc;
-
-	sc = device_get_softc(dev);
-
-	RL_LOCK(sc);
-	rl_stop(sc);
-	rl_setwol(sc);
-	sc->suspended = 1;
-	RL_UNLOCK(sc);
-
-	return (0);
-}
-
-/*
- * Device resume routine.  Restore some PCI settings in case the BIOS
- * doesn't, re-enable busmastering, and restart the interface if
- * appropriate.
- */
-static int
-rl_resume(device_t dev)
-{
-	struct rl_softc		*sc;
-	struct ifnet		*ifp;
-	int			pmc;
-	uint16_t		pmstat;
-
-	sc = device_get_softc(dev);
-	ifp = sc->rl_ifp;
-
-	RL_LOCK(sc);
-
-	if ((ifp->if_capabilities & IFCAP_WOL) != 0 &&
-	    pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
-		/* Disable PME and clear PME status. */
-		pmstat = pci_read_config(sc->rl_dev,
-		    pmc + PCIR_POWER_STATUS, 2);
-		if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
-			pmstat &= ~PCIM_PSTAT_PMEENABLE;
-			pci_write_config(sc->rl_dev,
-			    pmc + PCIR_POWER_STATUS, pmstat, 2);
-		}
-		/*
-		 * Clear WOL matching such that normal Rx filtering
-		 * wouldn't interfere with WOL patterns.
-		 */
-		rl_clrwol(sc);
-	}
-
-	/* reinitialize interface if necessary */
-	if (ifp->if_flags & IFF_UP)
-		rl_init_locked(sc);
-
-	sc->suspended = 0;
-
-	RL_UNLOCK(sc);
-
-	return (0);
-}
-
-/*
- * Stop all chip I/O so that the kernel's probe routines don't
- * get confused by errant DMAs when rebooting.
- */
-static int
-rl_shutdown(device_t dev)
-{
-	struct rl_softc		*sc;
-
-	sc = device_get_softc(dev);
-
-	RL_LOCK(sc);
-	rl_stop(sc);
-	/*
-	 * Mark interface as down since otherwise we will panic if
-	 * interrupt comes in later on, which can happen in some
-	 * cases.
-	 */
-	sc->rl_ifp->if_flags &= ~IFF_UP;
-	rl_setwol(sc);
-	RL_UNLOCK(sc);
-
-	return (0);
-}
-
-static void
-rl_setwol(struct rl_softc *sc)
-{
-	struct ifnet		*ifp;
-	int			pmc;
-	uint16_t		pmstat;
-	uint8_t			v;
-
-	RL_LOCK_ASSERT(sc);
-
-	ifp = sc->rl_ifp;
-	if ((ifp->if_capabilities & IFCAP_WOL) == 0)
-		return;
-	if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
-		return;
-
-	/* Enable config register write. */
-	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
-
-	/* Enable PME. */
-	v = CSR_READ_1(sc, sc->rl_cfg1);
-	v &= ~RL_CFG1_PME;
-	if ((ifp->if_capenable & IFCAP_WOL) != 0)
-		v |= RL_CFG1_PME;
-	CSR_WRITE_1(sc, sc->rl_cfg1, v);
-
-	v = CSR_READ_1(sc, sc->rl_cfg3);
-	v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
-	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
-		v |= RL_CFG3_WOL_MAGIC;
-	CSR_WRITE_1(sc, sc->rl_cfg3, v);
-
-	v = CSR_READ_1(sc, sc->rl_cfg5);
-	v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
-	v &= ~RL_CFG5_WOL_LANWAKE;
-	if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
-		v |= RL_CFG5_WOL_UCAST;
-	if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
-		v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
-	if ((ifp->if_capenable & IFCAP_WOL) != 0)
-		v |= RL_CFG5_WOL_LANWAKE;
-	CSR_WRITE_1(sc, sc->rl_cfg5, v);
-
-	/* Config register write done. */
-	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
-
-	/* Request PME if WOL is requested. */
-	pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
-	pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
-	if ((ifp->if_capenable & IFCAP_WOL) != 0)
-		pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
-	pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
-}
-
-static void
-rl_clrwol(struct rl_softc *sc)
-{
-	struct ifnet		*ifp;
-	uint8_t			v;
-
-	ifp = sc->rl_ifp;
-	if ((ifp->if_capabilities & IFCAP_WOL) == 0)
-		return;
-
-	/* Enable config register write. */
-	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
-
-	v = CSR_READ_1(sc, sc->rl_cfg3);
-	v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
-	CSR_WRITE_1(sc, sc->rl_cfg3, v);
-
-	/* Config register write done. */
-	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
-
-	v = CSR_READ_1(sc, sc->rl_cfg5);
-	v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
-	v &= ~RL_CFG5_WOL_LANWAKE;
-	CSR_WRITE_1(sc, sc->rl_cfg5, v);
-}

Property changes on: stable/9/sys/pci/if_rl.c
___________________________________________________________________
Deleted: svn:keywords
## -1 +0,0 ##
-FreeBSD=%H
\ No newline at end of property
Index: stable/9/sys/pci/if_rlreg.h
===================================================================
--- stable/9/sys/pci/if_rlreg.h	(revision 292780)
+++ stable/9/sys/pci/if_rlreg.h	(nonexistent)
@@ -1,1160 +0,0 @@
-/*-
- * Copyright (c) 1997, 1998-2003
- *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by Bill Paul.
- * 4. Neither the name of the author nor the names of any co-contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- * THE POSSIBILITY OF SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-/*
- * RealTek 8129/8139 register offsets
- */
-#define	RL_IDR0		0x0000		/* ID register 0 (station addr) */
-#define	RL_IDR1		0x0001		/* Must use 32-bit accesses (?) */
-#define	RL_IDR2		0x0002
-#define	RL_IDR3		0x0003
-#define	RL_IDR4		0x0004
-#define	RL_IDR5		0x0005
-					/* 0006-0007 reserved */
-#define	RL_MAR0		0x0008		/* Multicast hash table */
-#define	RL_MAR1		0x0009
-#define	RL_MAR2		0x000A
-#define	RL_MAR3		0x000B
-#define	RL_MAR4		0x000C
-#define	RL_MAR5		0x000D
-#define	RL_MAR6		0x000E
-#define	RL_MAR7		0x000F
-
-#define	RL_TXSTAT0	0x0010		/* status of TX descriptor 0 */
-#define	RL_TXSTAT1	0x0014		/* status of TX descriptor 1 */
-#define	RL_TXSTAT2	0x0018		/* status of TX descriptor 2 */
-#define	RL_TXSTAT3	0x001C		/* status of TX descriptor 3 */
-
-#define	RL_TXADDR0	0x0020		/* address of TX descriptor 0 */
-#define	RL_TXADDR1	0x0024		/* address of TX descriptor 1 */
-#define	RL_TXADDR2	0x0028		/* address of TX descriptor 2 */
-#define	RL_TXADDR3	0x002C		/* address of TX descriptor 3 */
-
-#define	RL_RXADDR		0x0030	/* RX ring start address */
-#define	RL_RX_EARLY_BYTES	0x0034	/* RX early byte count */
-#define	RL_RX_EARLY_STAT	0x0036	/* RX early status */
-#define	RL_COMMAND	0x0037		/* command register */
-#define	RL_CURRXADDR	0x0038		/* current address of packet read */
-#define	RL_CURRXBUF	0x003A		/* current RX buffer address */
-#define	RL_IMR		0x003C		/* interrupt mask register */
-#define	RL_ISR		0x003E		/* interrupt status register */
-#define	RL_TXCFG	0x0040		/* transmit config */
-#define	RL_RXCFG	0x0044		/* receive config */
-#define	RL_TIMERCNT	0x0048		/* timer count register */
-#define	RL_MISSEDPKT	0x004C		/* missed packet counter */
-#define	RL_EECMD	0x0050		/* EEPROM command register */
-
-/* RTL8139/RTL8139C+ only */
-#define	RL_8139_CFG0	0x0051		/* config register #0 */
-#define	RL_8139_CFG1	0x0052		/* config register #1 */
-#define	RL_8139_CFG3	0x0059		/* config register #3 */
-#define	RL_8139_CFG4	0x005A		/* config register #4 */
-#define	RL_8139_CFG5	0x00D8		/* config register #5 */
-
-#define	RL_CFG0		0x0051		/* config register #0 */
-#define	RL_CFG1		0x0052		/* config register #1 */
-#define	RL_CFG2		0x0053		/* config register #2 */
-#define	RL_CFG3		0x0054		/* config register #3 */
-#define	RL_CFG4		0x0055		/* config register #4 */
-#define	RL_CFG5		0x0056		/* config register #5 */
-					/* 0057 reserved */
-#define	RL_MEDIASTAT	0x0058		/* media status register (8139) */
-					/* 0059-005A reserved */
-#define	RL_MII		0x005A		/* 8129 chip only */
-#define	RL_HALTCLK	0x005B
-#define	RL_MULTIINTR	0x005C		/* multiple interrupt */
-#define	RL_PCIREV	0x005E		/* PCI revision value */
-					/* 005F reserved */
-#define	RL_TXSTAT_ALL	0x0060		/* TX status of all descriptors */
-
-/* Direct PHY access registers only available on 8139 */
-#define	RL_BMCR		0x0062		/* PHY basic mode control */
-#define	RL_BMSR		0x0064		/* PHY basic mode status */
-#define	RL_ANAR		0x0066		/* PHY autoneg advert */
-#define	RL_LPAR		0x0068		/* PHY link partner ability */
-#define	RL_ANER		0x006A		/* PHY autoneg expansion */
-
-#define	RL_DISCCNT	0x006C		/* disconnect counter */
-#define	RL_FALSECAR	0x006E		/* false carrier counter */
-#define	RL_NWAYTST	0x0070		/* NWAY test register */
-#define	RL_RX_ER	0x0072		/* RX_ER counter */
-#define	RL_CSCFG	0x0074		/* CS configuration register */
-
-/*
- * When operating in special C+ mode, some of the registers in an
- * 8139C+ chip have different definitions. These are also used for
- * the 8169 gigE chip.
- */
-#define	RL_DUMPSTATS_LO		0x0010	/* counter dump command register */
-#define	RL_DUMPSTATS_HI		0x0014	/* counter dump command register */
-#define	RL_TXLIST_ADDR_LO	0x0020	/* 64 bits, 256 byte alignment */
-#define	RL_TXLIST_ADDR_HI	0x0024	/* 64 bits, 256 byte alignment */
-#define	RL_TXLIST_ADDR_HPRIO_LO	0x0028	/* 64 bits, 256 byte alignment */
-#define	RL_TXLIST_ADDR_HPRIO_HI	0x002C	/* 64 bits, 256 byte alignment */
-#define	RL_CFG2			0x0053
-#define	RL_TIMERINT		0x0054	/* interrupt on timer expire */
-#define	RL_TXSTART		0x00D9	/* 8 bits */
-#define	RL_CPLUS_CMD		0x00E0	/* 16 bits */
-#define	RL_RXLIST_ADDR_LO	0x00E4	/* 64 bits, 256 byte alignment */
-#define	RL_RXLIST_ADDR_HI	0x00E8	/* 64 bits, 256 byte alignment */
-#define	RL_EARLY_TX_THRESH	0x00EC	/* 8 bits */
-
-/*
- * Registers specific to the 8169 gigE chip
- */
-#define	RL_GTXSTART		0x0038	/* 8 bits */
-#define	RL_TIMERINT_8169	0x0058	/* different offset than 8139 */
-#define	RL_PHYAR		0x0060
-#define	RL_TBICSR		0x0064
-#define	RL_TBI_ANAR		0x0068
-#define	RL_TBI_LPAR		0x006A
-#define	RL_GMEDIASTAT		0x006C	/* 8 bits */
-#define	RL_MACDBG		0x006D	/* 8 bits, 8168C SPIN2 only */
-#define	RL_GPIO			0x006E	/* 8 bits, 8168C SPIN2 only */
-#define	RL_PMCH			0x006F	/* 8 bits */
-#define	RL_MAXRXPKTLEN		0x00DA	/* 16 bits, chip multiplies by 8 */
-#define	RL_INTRMOD		0x00E2	/* 16 bits */
-#define	RL_MISC			0x00F0
-
-/*
- * TX config register bits
- */
-#define	RL_TXCFG_CLRABRT	0x00000001	/* retransmit aborted pkt */
-#define	RL_TXCFG_MAXDMA		0x00000700	/* max DMA burst size */
-#define	RL_TXCFG_QUEUE_EMPTY	0x00000800	/* 8168E-VL or higher */
-#define	RL_TXCFG_CRCAPPEND	0x00010000	/* CRC append (0 = yes) */
-#define	RL_TXCFG_LOOPBKTST	0x00060000	/* loopback test */
-#define	RL_TXCFG_IFG2		0x00080000	/* 8169 only */
-#define	RL_TXCFG_IFG		0x03000000	/* interframe gap */
-#define	RL_TXCFG_HWREV		0x7CC00000
-
-#define	RL_LOOPTEST_OFF		0x00000000
-#define	RL_LOOPTEST_ON		0x00020000
-#define	RL_LOOPTEST_ON_CPLUS	0x00060000
-
-/* Known revision codes. */
-#define	RL_HWREV_8169		0x00000000
-#define	RL_HWREV_8169S		0x00800000
-#define	RL_HWREV_8110S		0x04000000
-#define	RL_HWREV_8169_8110SB	0x10000000
-#define	RL_HWREV_8169_8110SC	0x18000000
-#define	RL_HWREV_8401E		0x24000000
-#define	RL_HWREV_8102EL		0x24800000
-#define	RL_HWREV_8102EL_SPIN1	0x24C00000
-#define	RL_HWREV_8168D		0x28000000
-#define	RL_HWREV_8168DP		0x28800000
-#define	RL_HWREV_8168E		0x2C000000
-#define	RL_HWREV_8168E_VL	0x2C800000
-#define	RL_HWREV_8168B_SPIN1	0x30000000
-#define	RL_HWREV_8100E		0x30800000
-#define	RL_HWREV_8101E		0x34000000
-#define	RL_HWREV_8102E		0x34800000
-#define	RL_HWREV_8103E		0x34C00000
-#define	RL_HWREV_8168B_SPIN2	0x38000000
-#define	RL_HWREV_8168B_SPIN3	0x38400000
-#define	RL_HWREV_8168C		0x3C000000
-#define	RL_HWREV_8168C_SPIN2	0x3C400000
-#define	RL_HWREV_8168CP		0x3C800000
-#define	RL_HWREV_8105E		0x40800000
-#define	RL_HWREV_8105E_SPIN1	0x40C00000
-#define	RL_HWREV_8402		0x44000000
-#define	RL_HWREV_8106E		0x44800000
-#define	RL_HWREV_8168F		0x48000000
-#define	RL_HWREV_8411		0x48800000
-#define	RL_HWREV_8168G		0x4C000000
-#define	RL_HWREV_8168EP		0x50000000
-#define	RL_HWREV_8168GU		0x50800000
-#define	RL_HWREV_8411B		0x5C800000
-#define	RL_HWREV_8139		0x60000000
-#define	RL_HWREV_8139A		0x70000000
-#define	RL_HWREV_8139AG		0x70800000
-#define	RL_HWREV_8139B		0x78000000
-#define	RL_HWREV_8130		0x7C000000
-#define	RL_HWREV_8139C		0x74000000
-#define	RL_HWREV_8139D		0x74400000
-#define	RL_HWREV_8139CPLUS	0x74800000
-#define	RL_HWREV_8101		0x74C00000
-#define	RL_HWREV_8100		0x78800000
-#define	RL_HWREV_8169_8110SBL	0x7CC00000
-#define	RL_HWREV_8169_8110SCE	0x98000000
-
-#define	RL_TXDMA_16BYTES	0x00000000
-#define	RL_TXDMA_32BYTES	0x00000100
-#define	RL_TXDMA_64BYTES	0x00000200
-#define	RL_TXDMA_128BYTES	0x00000300
-#define	RL_TXDMA_256BYTES	0x00000400
-#define	RL_TXDMA_512BYTES	0x00000500
-#define	RL_TXDMA_1024BYTES	0x00000600
-#define	RL_TXDMA_2048BYTES	0x00000700
-
-/*
- * Transmit descriptor status register bits.
- */
-#define	RL_TXSTAT_LENMASK	0x00001FFF
-#define	RL_TXSTAT_OWN		0x00002000
-#define	RL_TXSTAT_TX_UNDERRUN	0x00004000
-#define	RL_TXSTAT_TX_OK		0x00008000
-#define	RL_TXSTAT_EARLY_THRESH	0x003F0000
-#define	RL_TXSTAT_COLLCNT	0x0F000000
-#define	RL_TXSTAT_CARR_HBEAT	0x10000000
-#define	RL_TXSTAT_OUTOFWIN	0x20000000
-#define	RL_TXSTAT_TXABRT	0x40000000
-#define	RL_TXSTAT_CARRLOSS	0x80000000
-
-/*
- * Interrupt status register bits.
- */
-#define	RL_ISR_RX_OK		0x0001
-#define	RL_ISR_RX_ERR		0x0002
-#define	RL_ISR_TX_OK		0x0004
-#define	RL_ISR_TX_ERR		0x0008
-#define	RL_ISR_RX_OVERRUN	0x0010
-#define	RL_ISR_PKT_UNDERRUN	0x0020
-#define	RL_ISR_LINKCHG		0x0020	/* 8169 only */
-#define	RL_ISR_FIFO_OFLOW	0x0040	/* 8139 only */
-#define	RL_ISR_TX_DESC_UNAVAIL	0x0080	/* C+ only */
-#define	RL_ISR_SWI		0x0100	/* C+ only */
-#define	RL_ISR_CABLE_LEN_CHGD	0x2000
-#define	RL_ISR_PCS_TIMEOUT	0x4000	/* 8129 only */
-#define	RL_ISR_TIMEOUT_EXPIRED	0x4000
-#define	RL_ISR_SYSTEM_ERR	0x8000
-
-#define	RL_INTRS	\
-	(RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|		\
-	RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|	\
-	RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
-
-#ifdef RE_TX_MODERATION
-#define	RL_INTRS_CPLUS	\
-	(RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|			\
-	RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|	\
-	RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
-#else
-#define	RL_INTRS_CPLUS	\
-	(RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK|		\
-	RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|	\
-	RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
-#endif
-
-/*
- * Media status register. (8139 only)
- */
-#define	RL_MEDIASTAT_RXPAUSE	0x01
-#define	RL_MEDIASTAT_TXPAUSE	0x02
-#define	RL_MEDIASTAT_LINK	0x04
-#define	RL_MEDIASTAT_SPEED10	0x08
-#define	RL_MEDIASTAT_RXFLOWCTL	0x40	/* duplex mode */
-#define	RL_MEDIASTAT_TXFLOWCTL	0x80	/* duplex mode */
-
-/*
- * Receive config register.
- */
-#define	RL_RXCFG_RX_ALLPHYS	0x00000001	/* accept all nodes */
-#define	RL_RXCFG_RX_INDIV	0x00000002	/* match filter */
-#define	RL_RXCFG_RX_MULTI	0x00000004	/* accept all multicast */
-#define	RL_RXCFG_RX_BROAD	0x00000008	/* accept all broadcast */
-#define	RL_RXCFG_RX_RUNT	0x00000010
-#define	RL_RXCFG_RX_ERRPKT	0x00000020
-#define	RL_RXCFG_WRAP		0x00000080
-#define	RL_RXCFG_EARLYOFFV2	0x00000800
-#define	RL_RXCFG_MAXDMA		0x00000700
-#define	RL_RXCFG_BUFSZ		0x00001800
-#define	RL_RXCFG_EARLYOFF	0x00003800
-#define	RL_RXCFG_FIFOTHRESH	0x0000E000
-#define	RL_RXCFG_EARLYTHRESH	0x07000000
-
-#define	RL_RXDMA_16BYTES	0x00000000
-#define	RL_RXDMA_32BYTES	0x00000100
-#define	RL_RXDMA_64BYTES	0x00000200
-#define	RL_RXDMA_128BYTES	0x00000300
-#define	RL_RXDMA_256BYTES	0x00000400
-#define	RL_RXDMA_512BYTES	0x00000500
-#define	RL_RXDMA_1024BYTES	0x00000600
-#define	RL_RXDMA_UNLIMITED	0x00000700
-
-#define	RL_RXBUF_8		0x00000000
-#define	RL_RXBUF_16		0x00000800
-#define	RL_RXBUF_32		0x00001000
-#define	RL_RXBUF_64		0x00001800
-
-#define	RL_RXFIFO_16BYTES	0x00000000
-#define	RL_RXFIFO_32BYTES	0x00002000
-#define	RL_RXFIFO_64BYTES	0x00004000
-#define	RL_RXFIFO_128BYTES	0x00006000
-#define	RL_RXFIFO_256BYTES	0x00008000
-#define	RL_RXFIFO_512BYTES	0x0000A000
-#define	RL_RXFIFO_1024BYTES	0x0000C000
-#define	RL_RXFIFO_NOTHRESH	0x0000E000
-
-/*
- * Bits in RX status header (included with RX'ed packet
- * in ring buffer).
- */
-#define	RL_RXSTAT_RXOK		0x00000001
-#define	RL_RXSTAT_ALIGNERR	0x00000002
-#define	RL_RXSTAT_CRCERR	0x00000004
-#define	RL_RXSTAT_GIANT		0x00000008
-#define	RL_RXSTAT_RUNT		0x00000010
-#define	RL_RXSTAT_BADSYM	0x00000020
-#define	RL_RXSTAT_BROAD		0x00002000
-#define	RL_RXSTAT_INDIV		0x00004000
-#define	RL_RXSTAT_MULTI		0x00008000
-#define	RL_RXSTAT_LENMASK	0xFFFF0000
-#define	RL_RXSTAT_UNFINISHED	0x0000FFF0	/* DMA still in progress */
-
-/*
- * Command register.
- */
-#define	RL_CMD_EMPTY_RXBUF	0x0001
-#define	RL_CMD_TX_ENB		0x0004
-#define	RL_CMD_RX_ENB		0x0008
-#define	RL_CMD_RESET		0x0010
-#define	RL_CMD_STOPREQ		0x0080
-
-/*
- * Twister register values.  These are completely undocumented and derived
- * from public sources.
- */
-#define	RL_CSCFG_LINK_OK	0x0400
-#define	RL_CSCFG_CHANGE		0x0800
-#define	RL_CSCFG_STATUS		0xf000
-#define	RL_CSCFG_ROW3		0x7000
-#define	RL_CSCFG_ROW2		0x3000
-#define	RL_CSCFG_ROW1		0x1000
-#define	RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0
-#define	RL_CSCFG_LINK_DOWN_CMD	0xf3c0
-
-#define	RL_NWAYTST_RESET	0
-#define	RL_NWAYTST_CBL_TEST	0x20
-
-#define	RL_PARA78		0x78
-#define	RL_PARA78_DEF		0x78fa8388
-#define	RL_PARA7C		0x7C
-#define	RL_PARA7C_DEF		0xcb38de43
-#define	RL_PARA7C_RETUNE	0xfb38de03
-
-/*
- * EEPROM control register
- */
-#define	RL_EE_DATAOUT		0x01	/* Data out */
-#define	RL_EE_DATAIN		0x02	/* Data in */
-#define	RL_EE_CLK		0x04	/* clock */
-#define	RL_EE_SEL		0x08	/* chip select */
-#define	RL_EE_MODE		(0x40|0x80)
-
-#define	RL_EEMODE_OFF		0x00
-#define	RL_EEMODE_AUTOLOAD	0x40
-#define	RL_EEMODE_PROGRAM	0x80
-#define	RL_EEMODE_WRITECFG	(0x80|0x40)
-
-/* 9346 EEPROM commands */
-#define	RL_9346_ADDR_LEN	6	/* 93C46 1K: 128x16 */
-#define	RL_9356_ADDR_LEN	8	/* 93C56 2K: 256x16 */
-
-#define	RL_9346_WRITE		0x5
-#define	RL_9346_READ		0x6
-#define	RL_9346_ERASE		0x7
-#define	RL_9346_EWEN		0x4
-#define	RL_9346_EWEN_ADDR	0x30
-#define	RL_9456_EWDS		0x4
-#define	RL_9346_EWDS_ADDR	0x00
-
-#define	RL_EECMD_WRITE		0x140
-#define	RL_EECMD_READ_6BIT	0x180
-#define	RL_EECMD_READ_8BIT	0x600
-#define	RL_EECMD_ERASE		0x1c0
-
-#define	RL_EE_ID		0x00
-#define	RL_EE_PCI_VID		0x01
-#define	RL_EE_PCI_DID		0x02
-/* Location of station address inside EEPROM */
-#define	RL_EE_EADDR		0x07
-
-/*
- * MII register (8129 only)
- */
-#define	RL_MII_CLK		0x01
-#define	RL_MII_DATAIN		0x02
-#define	RL_MII_DATAOUT		0x04
-#define	RL_MII_DIR		0x80	/* 0 == input, 1 == output */
-
-/*
- * Config 0 register
- */
-#define	RL_CFG0_ROM0		0x01
-#define	RL_CFG0_ROM1		0x02
-#define	RL_CFG0_ROM2		0x04
-#define	RL_CFG0_PL0		0x08
-#define	RL_CFG0_PL1		0x10
-#define	RL_CFG0_10MBPS		0x20	/* 10 Mbps internal mode */
-#define	RL_CFG0_PCS		0x40
-#define	RL_CFG0_SCR		0x80
-
-/*
- * Config 1 register
- */
-#define	RL_CFG1_PWRDWN		0x01
-#define	RL_CFG1_PME		0x01
-#define	RL_CFG1_SLEEP		0x02
-#define	RL_CFG1_VPDEN		0x02
-#define	RL_CFG1_IOMAP		0x04
-#define	RL_CFG1_MEMMAP		0x08
-#define	RL_CFG1_RSVD		0x10
-#define	RL_CFG1_LWACT		0x10
-#define	RL_CFG1_DRVLOAD		0x20
-#define	RL_CFG1_LED0		0x40
-#define	RL_CFG1_FULLDUPLEX	0x40	/* 8129 only */
-#define	RL_CFG1_LED1		0x80
-
-/*
- * Config 2 register
- */
-#define	RL_CFG2_PCI33MHZ	0x00
-#define	RL_CFG2_PCI66MHZ	0x01
-#define	RL_CFG2_PCI64BIT	0x08
-#define	RL_CFG2_AUXPWR		0x10
-#define	RL_CFG2_MSI		0x20
-
-/*
- * Config 3 register
- */
-#define	RL_CFG3_GRANTSEL	0x80
-#define	RL_CFG3_WOL_MAGIC	0x20
-#define	RL_CFG3_WOL_LINK	0x10
-#define	RL_CFG3_JUMBO_EN0	0x04	/* RTL8168C or later. */
-#define	RL_CFG3_FAST_B2B	0x01
-
-/*
- * Config 4 register
- */
-#define	RL_CFG4_LWPTN		0x04
-#define	RL_CFG4_LWPME		0x10
-#define	RL_CFG4_JUMBO_EN1	0x02	/* RTL8168C or later. */
-
-/*
- * Config 5 register
- */
-#define	RL_CFG5_WOL_BCAST	0x40
-#define	RL_CFG5_WOL_MCAST	0x20
-#define	RL_CFG5_WOL_UCAST	0x10
-#define	RL_CFG5_WOL_LANWAKE	0x02
-#define	RL_CFG5_PME_STS		0x01
-
-/*
- * 8139C+ register definitions
- */
-
-/* RL_DUMPSTATS_LO register */
-#define	RL_DUMPSTATS_START	0x00000008
-
-/* Transmit start register */
-#define	RL_TXSTART_SWI		0x01	/* generate TX interrupt */
-#define	RL_TXSTART_START	0x40	/* start normal queue transmit */
-#define	RL_TXSTART_HPRIO_START	0x80	/* start hi prio queue transmit */
-
-/*
- * Config 2 register, 8139C+/8169/8169S/8110S only
- */
-#define	RL_CFG2_BUSFREQ		0x07
-#define	RL_CFG2_BUSWIDTH	0x08
-#define	RL_CFG2_AUXPWRSTS	0x10
-
-#define	RL_BUSFREQ_33MHZ	0x00
-#define	RL_BUSFREQ_66MHZ	0x01
-
-#define	RL_BUSWIDTH_32BITS	0x00
-#define	RL_BUSWIDTH_64BITS	0x08
-
-/* C+ mode command register */
-#define	RL_CPLUSCMD_TXENB	0x0001	/* enable C+ transmit mode */
-#define	RL_CPLUSCMD_RXENB	0x0002	/* enable C+ receive mode */
-#define	RL_CPLUSCMD_PCI_MRW	0x0008	/* enable PCI multi-read/write */
-#define	RL_CPLUSCMD_PCI_DAC	0x0010	/* PCI dual-address cycle only */
-#define	RL_CPLUSCMD_RXCSUM_ENB	0x0020	/* enable RX checksum offload */
-#define	RL_CPLUSCMD_VLANSTRIP	0x0040	/* enable VLAN tag stripping */
-#define	RL_CPLUSCMD_MACSTAT_DIS	0x0080	/* 8168B/C/CP */
-#define	RL_CPLUSCMD_ASF		0x0100	/* 8168C/CP */
-#define	RL_CPLUSCMD_DBG_SEL	0x0200	/* 8168C/CP */
-#define	RL_CPLUSCMD_FORCE_TXFC	0x0400	/* 8168C/CP */
-#define	RL_CPLUSCMD_FORCE_RXFC	0x0800	/* 8168C/CP */
-#define	RL_CPLUSCMD_FORCE_HDPX	0x1000	/* 8168C/CP */
-#define	RL_CPLUSCMD_NORMAL_MODE	0x2000	/* 8168C/CP */
-#define	RL_CPLUSCMD_DBG_ENB	0x4000	/* 8168C/CP */
-#define	RL_CPLUSCMD_BIST_ENB	0x8000	/* 8168C/CP */
-
-/* C+ early transmit threshold */
-#define	RL_EARLYTXTHRESH_CNT	0x003F	/* byte count times 8 */
-
-/* Timer interrupt register */
-#define	RL_TIMERINT_8169_VAL	0x00001FFF
-#define	RL_TIMER_MIN		0
-#define	RL_TIMER_MAX		65	/* 65.528us */
-#define	RL_TIMER_DEFAULT	RL_TIMER_MAX
-#define	RL_TIMER_PCIE_CLK	125	/* 125MHZ */
-#define	RL_USECS(x)		((x) * RL_TIMER_PCIE_CLK)
-
-/*
- * Gigabit PHY access register (8169 only)
- */
-#define	RL_PHYAR_PHYDATA	0x0000FFFF
-#define	RL_PHYAR_PHYREG		0x001F0000
-#define	RL_PHYAR_BUSY		0x80000000
-
-/*
- * Gigabit media status (8169 only)
- */
-#define	RL_GMEDIASTAT_FDX	0x01	/* full duplex */
-#define	RL_GMEDIASTAT_LINK	0x02	/* link up */
-#define	RL_GMEDIASTAT_10MBPS	0x04	/* 10mps link */
-#define	RL_GMEDIASTAT_100MBPS	0x08	/* 100mbps link */
-#define	RL_GMEDIASTAT_1000MBPS	0x10	/* gigE link */
-#define	RL_GMEDIASTAT_RXFLOW	0x20	/* RX flow control on */
-#define	RL_GMEDIASTAT_TXFLOW	0x40	/* TX flow control on */
-#define	RL_GMEDIASTAT_TBI	0x80	/* TBI enabled */
-
-/*
- * The RealTek doesn't use a fragment-based descriptor mechanism.
- * Instead, there are only four register sets, each or which represents
- * one 'descriptor.' Basically, each TX descriptor is just a contiguous
- * packet buffer (32-bit aligned!) and we place the buffer addresses in
- * the registers so the chip knows where they are.
- *
- * We can sort of kludge together the same kind of buffer management
- * used in previous drivers, but we have to do buffer copies almost all
- * the time, so it doesn't really buy us much.
- *
- * For reception, there's just one large buffer where the chip stores
- * all received packets.
- */
-#define	RL_RX_BUF_SZ		RL_RXBUF_64
-#define	RL_RXBUFLEN		(1 << ((RL_RX_BUF_SZ >> 11) + 13))
-#define	RL_TX_LIST_CNT		4
-#define	RL_MIN_FRAMELEN		60
-#define	RL_TX_8139_BUF_ALIGN	4
-#define	RL_RX_8139_BUF_ALIGN	8
-#define	RL_RX_8139_BUF_RESERVE	sizeof(int64_t)
-#define	RL_RX_8139_BUF_GUARD_SZ	\
-	(ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE)
-#define	RL_TXTHRESH(x)		((x) << 11)
-#define	RL_TX_THRESH_INIT	96
-#define	RL_RX_FIFOTHRESH	RL_RXFIFO_NOTHRESH
-#define	RL_RX_MAXDMA		RL_RXDMA_UNLIMITED
-#define	RL_TX_MAXDMA		RL_TXDMA_2048BYTES
-
-#define	RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ)
-#define	RL_TXCFG_CONFIG	(RL_TXCFG_IFG|RL_TX_MAXDMA)
-
-#define	RL_ETHER_ALIGN	2
-
-/*
- * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets.
- */
-#define	RL_IP4CSUMTX_MINLEN	28
-#define	RL_IP4CSUMTX_PADLEN	(ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN)
-
-struct rl_chain_data {
-	uint16_t		cur_rx;
-	uint8_t			*rl_rx_buf;
-	uint8_t			*rl_rx_buf_ptr;
-
-	struct mbuf		*rl_tx_chain[RL_TX_LIST_CNT];
-	bus_dmamap_t		rl_tx_dmamap[RL_TX_LIST_CNT];
-	bus_dma_tag_t		rl_tx_tag;
-	bus_dma_tag_t		rl_rx_tag;
-	bus_dmamap_t		rl_rx_dmamap;
-	bus_addr_t		rl_rx_buf_paddr;
-	uint8_t			last_tx;
-	uint8_t			cur_tx;
-};
-
-#define	RL_INC(x)		(x = (x + 1) % RL_TX_LIST_CNT)
-#define	RL_CUR_TXADDR(x)	((x->rl_cdata.cur_tx * 4) + RL_TXADDR0)
-#define	RL_CUR_TXSTAT(x)	((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0)
-#define	RL_CUR_TXMBUF(x)	(x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx])
-#define	RL_CUR_DMAMAP(x)	(x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx])
-#define	RL_LAST_TXADDR(x)	((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
-#define	RL_LAST_TXSTAT(x)	((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
-#define	RL_LAST_TXMBUF(x)	(x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
-#define	RL_LAST_DMAMAP(x)	(x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
-
-struct rl_type {
-	uint16_t		rl_vid;
-	uint16_t		rl_did;
-	int			rl_basetype;
-	const char		*rl_name;
-};
-
-struct rl_hwrev {
-	uint32_t		rl_rev;
-	int			rl_type;
-	const char		*rl_desc;
-	int			rl_max_mtu;
-};
-
-#define	RL_8129			1
-#define	RL_8139			2
-#define	RL_8139CPLUS		3
-#define	RL_8169			4
-
-#define	RL_ISCPLUS(x)		((x)->rl_type == RL_8139CPLUS ||	\
-				 (x)->rl_type == RL_8169)
-
-/*
- * The 8139C+ and 8160 gigE chips support descriptor-based TX
- * and RX. In fact, they even support TCP large send. Descriptors
- * must be allocated in contiguous blocks that are aligned on a
- * 256-byte boundary. The rings can hold a maximum of 64 descriptors.
- */
-
-/*
- * RX/TX descriptor definition. When large send mode is enabled, the
- * lower 11 bits of the TX rl_cmdstat word are used to hold the MSS, and
- * the checksum offload bits are disabled. The structure layout is
- * the same for RX and TX descriptors
- */
-struct rl_desc {
-	uint32_t		rl_cmdstat;
-	uint32_t		rl_vlanctl;
-	uint32_t		rl_bufaddr_lo;
-	uint32_t		rl_bufaddr_hi;
-};
-
-#define	RL_TDESC_CMD_FRAGLEN	0x0000FFFF
-#define	RL_TDESC_CMD_TCPCSUM	0x00010000	/* TCP checksum enable */
-#define	RL_TDESC_CMD_UDPCSUM	0x00020000	/* UDP checksum enable */
-#define	RL_TDESC_CMD_IPCSUM	0x00040000	/* IP header checksum enable */
-#define	RL_TDESC_CMD_MSSVAL	0x07FF0000	/* Large send MSS value */
-#define	RL_TDESC_CMD_MSSVAL_SHIFT	16	/* Large send MSS value shift */
-#define	RL_TDESC_CMD_LGSEND	0x08000000	/* TCP large send enb */
-#define	RL_TDESC_CMD_EOF	0x10000000	/* end of frame marker */
-#define	RL_TDESC_CMD_SOF	0x20000000	/* start of frame marker */
-#define	RL_TDESC_CMD_EOR	0x40000000	/* end of ring marker */
-#define	RL_TDESC_CMD_OWN	0x80000000	/* chip owns descriptor */
-
-#define	RL_TDESC_VLANCTL_TAG	0x00020000	/* Insert VLAN tag */
-#define	RL_TDESC_VLANCTL_DATA	0x0000FFFF	/* TAG data */
-/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
-#define	RL_TDESC_CMD_UDPCSUMV2	0x80000000
-#define	RL_TDESC_CMD_TCPCSUMV2	0x40000000
-#define	RL_TDESC_CMD_IPCSUMV2	0x20000000
-#define	RL_TDESC_CMD_MSSVALV2	0x1FFC0000
-#define	RL_TDESC_CMD_MSSVALV2_SHIFT	18
-
-/*
- * Error bits are valid only on the last descriptor of a frame
- * (i.e. RL_TDESC_CMD_EOF == 1)
- */
-#define	RL_TDESC_STAT_COLCNT	0x000F0000	/* collision count */
-#define	RL_TDESC_STAT_EXCESSCOL	0x00100000	/* excessive collisions */
-#define	RL_TDESC_STAT_LINKFAIL	0x00200000	/* link faulure */
-#define	RL_TDESC_STAT_OWINCOL	0x00400000	/* out-of-window collision */
-#define	RL_TDESC_STAT_TXERRSUM	0x00800000	/* transmit error summary */
-#define	RL_TDESC_STAT_UNDERRUN	0x02000000	/* TX underrun occured */
-#define	RL_TDESC_STAT_OWN	0x80000000
-
-/*
- * RX descriptor cmd/vlan definitions
- */
-#define	RL_RDESC_CMD_EOR	0x40000000
-#define	RL_RDESC_CMD_OWN	0x80000000
-#define	RL_RDESC_CMD_BUFLEN	0x00001FFF
-
-#define	RL_RDESC_STAT_OWN	0x80000000
-#define	RL_RDESC_STAT_EOR	0x40000000
-#define	RL_RDESC_STAT_SOF	0x20000000
-#define	RL_RDESC_STAT_EOF	0x10000000
-#define	RL_RDESC_STAT_FRALIGN	0x08000000	/* frame alignment error */
-#define	RL_RDESC_STAT_MCAST	0x04000000	/* multicast pkt received */
-#define	RL_RDESC_STAT_UCAST	0x02000000	/* unicast pkt received */
-#define	RL_RDESC_STAT_BCAST	0x01000000	/* broadcast pkt received */
-#define	RL_RDESC_STAT_BUFOFLOW	0x00800000	/* out of buffer space */
-#define	RL_RDESC_STAT_FIFOOFLOW	0x00400000	/* FIFO overrun */
-#define	RL_RDESC_STAT_GIANT	0x00200000	/* pkt > 4096 bytes */
-#define	RL_RDESC_STAT_RXERRSUM	0x00100000	/* RX error summary */
-#define	RL_RDESC_STAT_RUNT	0x00080000	/* runt packet received */
-#define	RL_RDESC_STAT_CRCERR	0x00040000	/* CRC error */
-#define	RL_RDESC_STAT_PROTOID	0x00030000	/* Protocol type */
-#define	RL_RDESC_STAT_UDP	0x00020000	/* UDP, 8168C/CP, 8111C/CP */
-#define	RL_RDESC_STAT_TCP	0x00010000	/* TCP, 8168C/CP, 8111C/CP */
-#define	RL_RDESC_STAT_IPSUMBAD	0x00008000	/* IP header checksum bad */
-#define	RL_RDESC_STAT_UDPSUMBAD	0x00004000	/* UDP checksum bad */
-#define	RL_RDESC_STAT_TCPSUMBAD	0x00002000	/* TCP checksum bad */
-#define	RL_RDESC_STAT_FRAGLEN	0x00001FFF	/* RX'ed frame/frag len */
-#define	RL_RDESC_STAT_GFRAGLEN	0x00003FFF	/* RX'ed frame/frag len */
-#define	RL_RDESC_STAT_ERRS	(RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \
-				 RL_RDESC_STAT_CRCERR)
-
-#define	RL_RDESC_VLANCTL_TAG	0x00010000	/* VLAN tag available
-						   (rl_vlandata valid)*/
-#define	RL_RDESC_VLANCTL_DATA	0x0000FFFF	/* TAG data */
-/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
-#define	RL_RDESC_IPV6		0x80000000
-#define	RL_RDESC_IPV4		0x40000000
-
-#define	RL_PROTOID_NONIP	0x00000000
-#define	RL_PROTOID_TCPIP	0x00010000
-#define	RL_PROTOID_UDPIP	0x00020000
-#define	RL_PROTOID_IP		0x00030000
-#define	RL_TCPPKT(x)		(((x) & RL_RDESC_STAT_PROTOID) == \
-				 RL_PROTOID_TCPIP)
-#define	RL_UDPPKT(x)		(((x) & RL_RDESC_STAT_PROTOID) == \
-				 RL_PROTOID_UDPIP)
-
-/*
- * Statistics counter structure (8139C+ and 8169 only)
- */
-struct rl_stats {
-	uint64_t		rl_tx_pkts;
-	uint64_t		rl_rx_pkts;
-	uint64_t		rl_tx_errs;
-	uint32_t		rl_rx_errs;
-	uint16_t		rl_missed_pkts;
-	uint16_t		rl_rx_framealign_errs;
-	uint32_t		rl_tx_onecoll;
-	uint32_t		rl_tx_multicolls;
-	uint64_t		rl_rx_ucasts;
-	uint64_t		rl_rx_bcasts;
-	uint32_t		rl_rx_mcasts;
-	uint16_t		rl_tx_aborts;
-	uint16_t		rl_rx_underruns;
-};
-
-/*
- * Rx/Tx descriptor parameters (8139C+ and 8169 only)
- *
- * 8139C+
- *  Number of descriptors supported : up to 64
- *  Descriptor alignment : 256 bytes
- *  Tx buffer : At least 4 bytes in length.
- *  Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
- *
- * 8169
- *  Number of descriptors supported : up to 1024
- *  Descriptor alignment : 256 bytes
- *  Tx buffer : At least 4 bytes in length.
- *  Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
- */
-#ifndef	__NO_STRICT_ALIGNMENT
-#define	RE_FIXUP_RX	1
-#endif
-
-#define	RL_8169_TX_DESC_CNT	256
-#define	RL_8169_RX_DESC_CNT	256
-#define	RL_8139_TX_DESC_CNT	64
-#define	RL_8139_RX_DESC_CNT	64
-#define	RL_TX_DESC_CNT		RL_8169_TX_DESC_CNT
-#define	RL_RX_DESC_CNT		RL_8169_RX_DESC_CNT
-#define	RL_RX_JUMBO_DESC_CNT	RL_RX_DESC_CNT
-#define	RL_NTXSEGS		35
-
-#define	RL_RING_ALIGN		256
-#define	RL_DUMP_ALIGN		64
-#define	RL_IFQ_MAXLEN		512
-#define	RL_TX_DESC_NXT(sc,x)	((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
-#define	RL_TX_DESC_PRV(sc,x)	((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
-#define	RL_RX_DESC_NXT(sc,x)	((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1))
-#define	RL_OWN(x)		(le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
-#define	RL_RXBYTES(x)		(le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask)
-#define	RL_PKTSZ(x)		((x)/* >> 3*/)
-#ifdef RE_FIXUP_RX
-#define	RE_ETHER_ALIGN	sizeof(uint64_t)
-#define	RE_RX_DESC_BUFLEN	(MCLBYTES - RE_ETHER_ALIGN)
-#else
-#define	RE_ETHER_ALIGN	0
-#define	RE_RX_DESC_BUFLEN	MCLBYTES
-#endif
-
-#define	RL_MSI_MESSAGES	1
-
-#define	RL_ADDR_LO(y)		((uint64_t) (y) & 0xFFFFFFFF)
-#define	RL_ADDR_HI(y)		((uint64_t) (y) >> 32)
-
-/*
- * The number of bits reserved for MSS in RealTek controllers is
- * 11bits. This limits the maximum interface MTU size in TSO case
- * as upper stack should not generate TCP segments with MSS greater
- * than the limit.
- */
-#define	RL_TSO_MTU		(2047 - ETHER_HDR_LEN - ETHER_CRC_LEN)
-
-/* see comment in dev/re/if_re.c */
-#define	RL_JUMBO_FRAMELEN	7440
-#define	RL_JUMBO_MTU		\
-	(RL_JUMBO_FRAMELEN-ETHER_VLAN_ENCAP_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
-#define	RL_JUMBO_MTU_6K		\
-	((6 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
-#define	RL_JUMBO_MTU_9K		\
-	((9 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
-#define	RL_MTU			\
-	(ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
-
-struct rl_txdesc {
-	struct mbuf		*tx_m;
-	bus_dmamap_t		tx_dmamap;
-};
-
-struct rl_rxdesc {
-	struct mbuf		*rx_m;
-	bus_dmamap_t		rx_dmamap;
-	bus_size_t		rx_size;
-};
-
-struct rl_list_data {
-	struct rl_txdesc	rl_tx_desc[RL_TX_DESC_CNT];
-	struct rl_rxdesc	rl_rx_desc[RL_RX_DESC_CNT];
-	struct rl_rxdesc	rl_jrx_desc[RL_RX_JUMBO_DESC_CNT];
-	int			rl_tx_desc_cnt;
-	int			rl_rx_desc_cnt;
-	int			rl_tx_prodidx;
-	int			rl_rx_prodidx;
-	int			rl_tx_considx;
-	int			rl_tx_free;
-	bus_dma_tag_t		rl_tx_mtag;	/* mbuf TX mapping tag */
-	bus_dma_tag_t		rl_rx_mtag;	/* mbuf RX mapping tag */
-	bus_dma_tag_t		rl_jrx_mtag;	/* mbuf RX mapping tag */
-	bus_dmamap_t		rl_rx_sparemap;
-	bus_dmamap_t		rl_jrx_sparemap;
-	bus_dma_tag_t		rl_stag;	/* stats mapping tag */
-	bus_dmamap_t		rl_smap;	/* stats map */
-	struct rl_stats		*rl_stats;
-	bus_addr_t		rl_stats_addr;
-	bus_dma_tag_t		rl_rx_list_tag;
-	bus_dmamap_t		rl_rx_list_map;
-	struct rl_desc		*rl_rx_list;
-	bus_addr_t		rl_rx_list_addr;
-	bus_dma_tag_t		rl_tx_list_tag;
-	bus_dmamap_t		rl_tx_list_map;
-	struct rl_desc		*rl_tx_list;
-	bus_addr_t		rl_tx_list_addr;
-};
-
-enum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE };
-
-struct rl_softc {
-	struct ifnet		*rl_ifp;	/* interface info */
-	bus_space_handle_t	rl_bhandle;	/* bus space handle */
-	bus_space_tag_t		rl_btag;	/* bus space tag */
-	device_t		rl_dev;
-	struct resource		*rl_res;
-	int			rl_res_id;
-	int			rl_res_type;
-	struct resource		*rl_res_pba;
-	struct resource		*rl_irq[RL_MSI_MESSAGES];
-	void			*rl_intrhand[RL_MSI_MESSAGES];
-	device_t		rl_miibus;
-	bus_dma_tag_t		rl_parent_tag;
-	uint8_t			rl_type;
-	const struct rl_hwrev	*rl_hwrev;
-	uint32_t		rl_macrev;
-	int			rl_eecmd_read;
-	int			rl_eewidth;
-	int			rl_expcap;
-	int			rl_txthresh;
-	bus_size_t		rl_cfg0;
-	bus_size_t		rl_cfg1;
-	bus_size_t		rl_cfg2;
-	bus_size_t		rl_cfg3;
-	bus_size_t		rl_cfg4;
-	bus_size_t		rl_cfg5;
-	struct rl_chain_data	rl_cdata;
-	struct rl_list_data	rl_ldata;
-	struct callout		rl_stat_callout;
-	int			rl_watchdog_timer;
-	struct mtx		rl_mtx;
-	struct mbuf		*rl_head;
-	struct mbuf		*rl_tail;
-	uint32_t		rl_rxlenmask;
-	int			rl_testmode;
-	int			rl_if_flags;
-	int			rl_twister_enable;
-	enum rl_twist		rl_twister;
-	int			rl_twist_row;
-	int			rl_twist_col;
-	int			suspended;	/* 0 = normal  1 = suspended */
-#ifdef DEVICE_POLLING
-	int			rxcycles;
-#endif
-
-	struct task		rl_inttask;
-
-	int			rl_txstart;
-	int			rl_int_rx_act;
-	int			rl_int_rx_mod;
-	uint32_t		rl_flags;
-#define	RL_FLAG_MSI		0x00000001
-#define	RL_FLAG_AUTOPAD		0x00000002
-#define	RL_FLAG_PHYWAKE_PM	0x00000004
-#define	RL_FLAG_PHYWAKE		0x00000008
-#define	RL_FLAG_JUMBOV2		0x00000010
-#define	RL_FLAG_PAR		0x00000020
-#define	RL_FLAG_DESCV2		0x00000040
-#define	RL_FLAG_MACSTAT		0x00000080
-#define	RL_FLAG_FASTETHER	0x00000100
-#define	RL_FLAG_CMDSTOP		0x00000200
-#define	RL_FLAG_MACRESET	0x00000400
-#define	RL_FLAG_MSIX		0x00000800
-#define	RL_FLAG_WOLRXENB	0x00001000
-#define	RL_FLAG_MACSLEEP	0x00002000
-#define	RL_FLAG_WAIT_TXPOLL	0x00004000
-#define	RL_FLAG_CMDSTOP_WAIT_TXQ	0x00008000
-#define	RL_FLAG_WOL_MANLINK	0x00010000
-#define	RL_FLAG_EARLYOFF	0x00020000
-#define	RL_FLAG_EARLYOFFV2	0x00040000
-#define	RL_FLAG_RXDV_GATED	0x00080000
-#define	RL_FLAG_PCIE		0x40000000
-#define	RL_FLAG_LINK		0x80000000
-};
-
-#define	RL_LOCK(_sc)		mtx_lock(&(_sc)->rl_mtx)
-#define	RL_UNLOCK(_sc)		mtx_unlock(&(_sc)->rl_mtx)
-#define	RL_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->rl_mtx, MA_OWNED)
-
-/*
- * register space access macros
- */
-#define	CSR_WRITE_STREAM_4(sc, reg, val)	\
-	bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val)
-#define	CSR_WRITE_4(sc, reg, val)	\
-	bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val)
-#define	CSR_WRITE_2(sc, reg, val)	\
-	bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val)
-#define	CSR_WRITE_1(sc, reg, val)	\
-	bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val)
-
-#define	CSR_READ_4(sc, reg)		\
-	bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg)
-#define	CSR_READ_2(sc, reg)		\
-	bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg)
-#define	CSR_READ_1(sc, reg)		\
-	bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg)
-
-#define	CSR_BARRIER(sc, reg, length, flags)				\
-	bus_space_barrier(sc->rl_btag, sc->rl_bhandle, reg, length, flags)
-
-#define	CSR_SETBIT_1(sc, offset, val)		\
-	CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
-
-#define	CSR_CLRBIT_1(sc, offset, val)		\
-	CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
-
-#define	CSR_SETBIT_2(sc, offset, val)		\
-	CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
-
-#define	CSR_CLRBIT_2(sc, offset, val)		\
-	CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
-
-#define	CSR_SETBIT_4(sc, offset, val)		\
-	CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val))
-
-#define	CSR_CLRBIT_4(sc, offset, val)		\
-	CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val))
-
-#define	RL_TIMEOUT		1000
-#define	RL_PHY_TIMEOUT		2000
-
-/*
- * General constants that are fun to know.
- *
- * RealTek PCI vendor ID
- */
-#define	RT_VENDORID				0x10EC
-
-/*
- * RealTek chip device IDs.
- */
-#define	RT_DEVICEID_8139D			0x8039
-#define	RT_DEVICEID_8129			0x8129
-#define	RT_DEVICEID_8101E			0x8136
-#define	RT_DEVICEID_8138			0x8138
-#define	RT_DEVICEID_8139			0x8139
-#define	RT_DEVICEID_8169SC			0x8167
-#define	RT_DEVICEID_8168			0x8168
-#define	RT_DEVICEID_8169			0x8169
-#define	RT_DEVICEID_8100			0x8100
-
-#define	RT_REVID_8139CPLUS			0x20
-
-/*
- * Accton PCI vendor ID
- */
-#define	ACCTON_VENDORID				0x1113
-
-/*
- * Accton MPX 5030/5038 device ID.
- */
-#define	ACCTON_DEVICEID_5030			0x1211
-
-/*
- * Nortel PCI vendor ID
- */
-#define	NORTEL_VENDORID				0x126C
-
-/*
- * Delta Electronics Vendor ID.
- */
-#define	DELTA_VENDORID				0x1500
-
-/*
- * Delta device IDs.
- */
-#define	DELTA_DEVICEID_8139			0x1360
-
-/*
- * Addtron vendor ID.
- */
-#define	ADDTRON_VENDORID			0x4033
-
-/*
- * Addtron device IDs.
- */
-#define	ADDTRON_DEVICEID_8139			0x1360
-
-/*
- * D-Link vendor ID.
- */
-#define	DLINK_VENDORID				0x1186
-
-/*
- * D-Link DFE-530TX+ device ID
- */
-#define	DLINK_DEVICEID_530TXPLUS		0x1300
-
-/*
- * D-Link DFE-520TX rev. C1 device ID
- */
-#define	DLINK_DEVICEID_520TX_REVC1		0x4200
-
-/*
- * D-Link DFE-5280T device ID
- */
-#define	DLINK_DEVICEID_528T			0x4300
-#define	DLINK_DEVICEID_530T_REVC		0x4302
-
-/*
- * D-Link DFE-690TXD device ID
- */
-#define	DLINK_DEVICEID_690TXD			0x1340
-
-/*
- * Corega K.K vendor ID
- */
-#define	COREGA_VENDORID				0x1259
-
-/*
- * Corega FEther CB-TXD device ID
- */
-#define	COREGA_DEVICEID_FETHERCBTXD		0xa117
-
-/*
- * Corega FEtherII CB-TXD device ID
- */
-#define	COREGA_DEVICEID_FETHERIICBTXD		0xa11e
-
-/*
- * Corega CG-LAPCIGT device ID
- */
-#define	COREGA_DEVICEID_CGLAPCIGT		0xc107
-
-/*
- * Linksys vendor ID
- */
-#define	LINKSYS_VENDORID			0x1737
-
-/*
- * Linksys EG1032 device ID
- */
-#define	LINKSYS_DEVICEID_EG1032			0x1032
-
-/*
- * Linksys EG1032 rev 3 sub-device ID
- */
-#define	LINKSYS_SUBDEVICE_EG1032_REV3		0x0024
-
-/*
- * Peppercon vendor ID
- */
-#define	PEPPERCON_VENDORID			0x1743
-
-/*
- * Peppercon ROL-F device ID
- */
-#define	PEPPERCON_DEVICEID_ROLF			0x8139
-
-/*
- * Planex Communications, Inc. vendor ID
- */
-#define	PLANEX_VENDORID				0x14ea
-
-/*
- * Planex FNW-3603-TX device ID
- */
-#define	PLANEX_DEVICEID_FNW3603TX		0xab06
-
-/*
- * Planex FNW-3800-TX device ID
- */
-#define	PLANEX_DEVICEID_FNW3800TX		0xab07
-
-/*
- * LevelOne vendor ID
- */
-#define	LEVEL1_VENDORID				0x018A
-
-/*
- * LevelOne FPC-0106TX devide ID
- */
-#define	LEVEL1_DEVICEID_FPC0106TX		0x0106
-
-/*
- * Compaq vendor ID
- */
-#define	CP_VENDORID				0x021B
-
-/*
- * Edimax vendor ID
- */
-#define	EDIMAX_VENDORID				0x13D1
-
-/*
- * Edimax EP-4103DL cardbus device ID
- */
-#define	EDIMAX_DEVICEID_EP4103DL		0xAB06
-
-/* US Robotics vendor ID */
-
-#define	USR_VENDORID		0x16EC
-
-/* US Robotics 997902 device ID */
-
-#define	USR_DEVICEID_997902	0x0116

Property changes on: stable/9/sys/pci/if_rlreg.h
___________________________________________________________________
Deleted: svn:keywords
## -1 +0,0 ##
-FreeBSD=%H
\ No newline at end of property
Index: stable/9/sys
===================================================================
--- stable/9/sys	(revision 292780)
+++ stable/9/sys	(revision 292781)

Property changes on: stable/9/sys
___________________________________________________________________
Modified: svn:mergeinfo
## -0,0 +0,1 ##
   Merged /head/sys:r271864