Index: head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_attach.c =================================================================== --- head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_attach.c (revision 291432) +++ head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_attach.c (revision 291433) @@ -1,4148 +1,4172 @@ /* * Copyright (c) 2013 Qualcomm Atheros, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ #include "opt_ah.h" #include "ah.h" #include "ah_internal.h" #include "ah_devid.h" #include "ar9300/ar9300desc.h" #include "ar9300/ar9300.h" #include "ar9300/ar9300reg.h" #include "ar9300/ar9300phy.h" #include "ar9300/ar9300paprd.h" #include "ar9300/ar9300_stub.h" #include "ar9300/ar9300_stub_funcs.h" /* Add static register initialization vectors */ #include "ar9300/ar9300_osprey22.ini" #include "ar9300/ar9330_11.ini" #include "ar9300/ar9330_12.ini" #include "ar9300/ar9340.ini" #include "ar9300/ar9485.ini" #include "ar9300/ar9485_1_1.ini" #include "ar9300/ar9300_jupiter10.ini" #include "ar9300/ar9300_jupiter20.ini" +#include "ar9300/ar9462_2p1_initvals.h" #include "ar9300/ar9580.ini" #include "ar9300/ar955x.ini" #include "ar9300/ar9300_aphrodite10.ini" /* Include various freebsd specific HAL methods */ #include "ar9300/ar9300_freebsd.h" /* XXX duplicate in ar9300_radio.c ? */ static HAL_BOOL ar9300_get_chip_power_limits(struct ath_hal *ah, struct ieee80211_channel *chan); static inline HAL_STATUS ar9300_init_mac_addr(struct ath_hal *ah); static inline HAL_STATUS ar9300_hw_attach(struct ath_hal *ah); static inline void ar9300_hw_detach(struct ath_hal *ah); static int16_t ar9300_get_nf_adjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c); #if 0 int ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp, HAL_CAL_QUERY query); #endif #if ATH_TRAFFIC_FAST_RECOVER unsigned long ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah); #endif static int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid); static void ar9300_disable_pcie_phy(struct ath_hal *ah); static const HAL_PERCAL_DATA iq_cal_single_sample = {IQ_MISMATCH_CAL, MIN_CAL_SAMPLES, PER_MAX_LOG_COUNT, ar9300_iq_cal_collect, ar9300_iq_calibration}; #if 0 static HAL_CALIBRATION_TIMER ar9300_cals[] = { {IQ_MISMATCH_CAL, /* Cal type */ 1200000, /* Cal interval */ 0 /* Cal timestamp */ }, {TEMP_COMP_CAL, 5000, 0 }, }; #endif #if ATH_PCIE_ERROR_MONITOR int ar9300_start_pcie_error_monitor(struct ath_hal *ah, int b_auto_stop) { u_int32_t val; /* Clear the counters */ OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR0, 0); OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR1, 0); /* Read the previous value */ val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL); /* Set auto_stop */ if (b_auto_stop) { val |= RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP | BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP | RPLY_NUM_RO_ERR_CTR_AUTO_STOP; } else { val &= ~( RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP | BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP | RPLY_NUM_RO_ERR_CTR_AUTO_STOP); } OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val ); /* * Start to run. * This has to be done separately from the above auto_stop flag setting, * to avoid a HW race condition. */ val |= RCVD_ERR_CTR_RUN | BAD_TLP_ERR_CTR_RUN | BAD_DLLP_ERR_CTR_RUN | RPLY_TO_ERR_CTR_RUN | RPLY_NUM_RO_ERR_CTR_RUN; OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val); return 0; } int ar9300_read_pcie_error_monitor(struct ath_hal *ah, void* p_read_counters) { u_int32_t val; ar_pcie_error_moniter_counters *p_counters = (ar_pcie_error_moniter_counters*) p_read_counters; val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR0); p_counters->uc_receiver_errors = MS(val, RCVD_ERR_MASK); p_counters->uc_bad_tlp_errors = MS(val, BAD_TLP_ERR_MASK); p_counters->uc_bad_dllp_errors = MS(val, BAD_DLLP_ERR_MASK); val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR1); p_counters->uc_replay_timeout_errors = MS(val, RPLY_TO_ERR_MASK); p_counters->uc_replay_number_rollover_errors= MS(val, RPLY_NUM_RO_ERR_MASK); return 0; } int ar9300_stop_pcie_error_monitor(struct ath_hal *ah) { u_int32_t val; /* Read the previous value */ val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL); val &= ~( RCVD_ERR_CTR_RUN | BAD_TLP_ERR_CTR_RUN | BAD_DLLP_ERR_CTR_RUN | RPLY_TO_ERR_CTR_RUN | RPLY_NUM_RO_ERR_CTR_RUN); /* Start to stop */ OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val ); return 0; } #endif /* ATH_PCIE_ERROR_MONITOR */ #if 0 /* WIN32 does not support C99 */ static const struct ath_hal_private ar9300hal = { { ar9300_get_rate_table, /* ah_get_rate_table */ ar9300_detach, /* ah_detach */ /* Reset Functions */ ar9300_reset, /* ah_reset */ ar9300_phy_disable, /* ah_phy_disable */ ar9300_disable, /* ah_disable */ ar9300_config_pci_power_save, /* ah_config_pci_power_save */ ar9300_set_pcu_config, /* ah_set_pcu_config */ ar9300_calibration, /* ah_per_calibration */ ar9300_reset_cal_valid, /* ah_reset_cal_valid */ ar9300_set_tx_power_limit, /* ah_set_tx_power_limit */ #if ATH_ANT_DIV_COMB ar9300_ant_ctrl_set_lna_div_use_bt_ant, /* ah_ant_ctrl_set_lna_div_use_bt_ant */ #endif /* ATH_ANT_DIV_COMB */ #ifdef ATH_SUPPORT_DFS ar9300_radar_wait, /* ah_radar_wait */ /* New DFS functions */ ar9300_check_dfs, /* ah_ar_check_dfs */ ar9300_dfs_found, /* ah_ar_dfs_found */ ar9300_enable_dfs, /* ah_ar_enable_dfs */ ar9300_get_dfs_thresh, /* ah_ar_get_dfs_thresh */ ar9300_get_dfs_radars, /* ah_ar_get_dfs_radars */ ar9300_adjust_difs, /* ah_adjust_difs */ ar9300_dfs_config_fft, /* ah_dfs_config_fft */ ar9300_dfs_cac_war, /* ah_dfs_cac_war */ ar9300_cac_tx_quiet, /* ah_cac_tx_quiet */ #endif ar9300_get_extension_channel, /* ah_get_extension_channel */ ar9300_is_fast_clock_enabled, /* ah_is_fast_clock_enabled */ /* Transmit functions */ ar9300_update_tx_trig_level, /* ah_update_tx_trig_level */ ar9300_get_tx_trig_level, /* ah_get_tx_trig_level */ ar9300_setup_tx_queue, /* ah_setup_tx_queue */ ar9300_set_tx_queue_props, /* ah_set_tx_queue_props */ ar9300_get_tx_queue_props, /* ah_get_tx_queue_props */ ar9300_release_tx_queue, /* ah_release_tx_queue */ ar9300_reset_tx_queue, /* ah_reset_tx_queue */ ar9300_get_tx_dp, /* ah_get_tx_dp */ ar9300_set_tx_dp, /* ah_set_tx_dp */ ar9300_num_tx_pending, /* ah_num_tx_pending */ ar9300_start_tx_dma, /* ah_start_tx_dma */ ar9300_stop_tx_dma, /* ah_stop_tx_dma */ ar9300_stop_tx_dma_indv_que, /* ah_stop_tx_dma_indv_que */ ar9300_abort_tx_dma, /* ah_abort_tx_dma */ ar9300_fill_tx_desc, /* ah_fill_tx_desc */ ar9300_set_desc_link, /* ah_set_desc_link */ ar9300_get_desc_link_ptr, /* ah_get_desc_link_ptr */ ar9300_clear_tx_desc_status, /* ah_clear_tx_desc_status */ #ifdef ATH_SWRETRY ar9300_clear_dest_mask, /* ah_clear_dest_mask */ #endif ar9300_proc_tx_desc, /* ah_proc_tx_desc */ ar9300_get_raw_tx_desc, /* ah_get_raw_tx_desc */ ar9300_get_tx_rate_code, /* ah_get_tx_rate_code */ AH_NULL, /* ah_get_tx_intr_queue */ ar9300_tx_req_intr_desc, /* ah_req_tx_intr_desc */ ar9300_calc_tx_airtime, /* ah_calc_tx_airtime */ ar9300_setup_tx_status_ring, /* ah_setup_tx_status_ring */ /* RX Functions */ ar9300_get_rx_dp, /* ah_get_rx_dp */ ar9300_set_rx_dp, /* ah_set_rx_dp */ ar9300_enable_receive, /* ah_enable_receive */ ar9300_stop_dma_receive, /* ah_stop_dma_receive */ ar9300_start_pcu_receive, /* ah_start_pcu_receive */ ar9300_stop_pcu_receive, /* ah_stop_pcu_receive */ ar9300_set_multicast_filter, /* ah_set_multicast_filter */ ar9300_get_rx_filter, /* ah_get_rx_filter */ ar9300_set_rx_filter, /* ah_set_rx_filter */ ar9300_set_rx_sel_evm, /* ah_set_rx_sel_evm */ ar9300_set_rx_abort, /* ah_set_rx_abort */ AH_NULL, /* ah_setup_rx_desc */ ar9300_proc_rx_desc, /* ah_proc_rx_desc */ ar9300_get_rx_key_idx, /* ah_get_rx_key_idx */ ar9300_proc_rx_desc_fast, /* ah_proc_rx_desc_fast */ ar9300_ani_ar_poll, /* ah_rx_monitor */ ar9300_process_mib_intr, /* ah_proc_mib_event */ /* Misc Functions */ ar9300_get_capability, /* ah_get_capability */ ar9300_set_capability, /* ah_set_capability */ ar9300_get_diag_state, /* ah_get_diag_state */ ar9300_get_mac_address, /* ah_get_mac_address */ ar9300_set_mac_address, /* ah_set_mac_address */ ar9300_get_bss_id_mask, /* ah_get_bss_id_mask */ ar9300_set_bss_id_mask, /* ah_set_bss_id_mask */ ar9300_set_regulatory_domain, /* ah_set_regulatory_domain */ ar9300_set_led_state, /* ah_set_led_state */ ar9300_set_power_led_state, /* ah_setpowerledstate */ ar9300_set_network_led_state, /* ah_setnetworkledstate */ ar9300_write_associd, /* ah_write_associd */ ar9300_force_tsf_sync, /* ah_force_tsf_sync */ ar9300_gpio_cfg_input, /* ah_gpio_cfg_input */ ar9300_gpio_cfg_output, /* ah_gpio_cfg_output */ ar9300_gpio_cfg_output_led_off, /* ah_gpio_cfg_output_led_off */ ar9300_gpio_get, /* ah_gpio_get */ ar9300_gpio_set, /* ah_gpio_set */ ar9300_gpio_get_intr, /* ah_gpio_get_intr */ ar9300_gpio_set_intr, /* ah_gpio_set_intr */ ar9300_gpio_get_polarity, /* ah_gpio_get_polarity */ ar9300_gpio_set_polarity, /* ah_gpio_set_polarity */ ar9300_gpio_get_mask, /* ah_gpio_get_mask */ ar9300_gpio_set_mask, /* ah_gpio_set_mask */ ar9300_get_tsf32, /* ah_get_tsf32 */ ar9300_get_tsf64, /* ah_get_tsf64 */ ar9300_get_tsf2_32, /* ah_get_tsf2_32 */ ar9300_reset_tsf, /* ah_reset_tsf */ ar9300_detect_card_present, /* ah_detect_card_present */ ar9300_update_mib_mac_stats, /* ah_update_mib_mac_stats */ ar9300_get_mib_mac_stats, /* ah_get_mib_mac_stats */ ar9300_get_rfgain, /* ah_get_rf_gain */ ar9300_get_def_antenna, /* ah_get_def_antenna */ ar9300_set_def_antenna, /* ah_set_def_antenna */ ar9300_set_slot_time, /* ah_set_slot_time */ ar9300_set_ack_timeout, /* ah_set_ack_timeout */ ar9300_get_ack_timeout, /* ah_get_ack_timeout */ ar9300_set_coverage_class, /* ah_set_coverage_class */ ar9300_set_quiet, /* ah_set_quiet */ ar9300_set_antenna_switch, /* ah_set_antenna_switch */ ar9300_get_desc_info, /* ah_get_desc_info */ ar9300_select_ant_config, /* ah_select_ant_config */ ar9300_ant_ctrl_common_get, /* ah_ant_ctrl_common_get */ ar9300_ant_swcom_sel, /* ah_ant_swcom_sel */ ar9300_enable_tpc, /* ah_enable_tpc */ AH_NULL, /* ah_olpc_temp_compensation */ #if ATH_SUPPORT_CRDC ar9300_chain_rssi_diff_compensation,/*ah_chain_rssi_diff_compensation*/ #endif ar9300_disable_phy_restart, /* ah_disable_phy_restart */ ar9300_enable_keysearch_always, ar9300_interference_is_present, /* ah_interference_is_present */ ar9300_disp_tpc_tables, /* ah_disp_tpc_tables */ ar9300_get_tpc_tables, /* ah_get_tpc_tables */ /* Key Cache Functions */ ar9300_get_key_cache_size, /* ah_get_key_cache_size */ ar9300_reset_key_cache_entry, /* ah_reset_key_cache_entry */ ar9300_is_key_cache_entry_valid, /* ah_is_key_cache_entry_valid */ ar9300_set_key_cache_entry, /* ah_set_key_cache_entry */ ar9300_set_key_cache_entry_mac, /* ah_set_key_cache_entry_mac */ ar9300_print_keycache, /* ah_print_key_cache */ #if ATH_SUPPORT_KEYPLUMB_WAR ar9300_check_key_cache_entry, /* ah_check_key_cache_entry */ #endif /* Power Management Functions */ ar9300_set_power_mode, /* ah_set_power_mode */ ar9300_set_sm_power_mode, /* ah_set_sm_ps_mode */ #if ATH_WOW ar9300_wow_apply_pattern, /* ah_wow_apply_pattern */ ar9300_wow_enable, /* ah_wow_enable */ ar9300_wow_wake_up, /* ah_wow_wake_up */ #if ATH_WOW_OFFLOAD ar9300_wowoffload_prep, /* ah_wow_offload_prep */ ar9300_wowoffload_post, /* ah_wow_offload_post */ ar9300_wowoffload_download_rekey_data, /* ah_wow_offload_download_rekey_data */ ar9300_wowoffload_retrieve_data, /* ah_wow_offload_retrieve_data */ ar9300_wowoffload_download_acer_magic, /* ah_wow_offload_download_acer_magic */ ar9300_wowoffload_download_acer_swka, /* ah_wow_offload_download_acer_swka */ ar9300_wowoffload_download_arp_info, /* ah_wow_offload_download_arp_info */ ar9300_wowoffload_download_ns_info, /* ah_wow_offload_download_ns_info */ #endif /* ATH_WOW_OFFLOAD */ #endif /* Get Channel Noise */ ath_hal_get_chan_noise, /* ah_get_chan_noise */ ar9300_chain_noise_floor, /* ah_get_chain_noise_floor */ ar9300_get_nf_from_reg, /* ah_get_nf_from_reg */ ar9300_get_rx_nf_offset, /* ah_get_rx_nf_offset */ /* Beacon Functions */ ar9300_beacon_init, /* ah_beacon_init */ ar9300_set_sta_beacon_timers, /* ah_set_station_beacon_timers */ /* Interrupt Functions */ ar9300_is_interrupt_pending, /* ah_is_interrupt_pending */ ar9300_get_pending_interrupts, /* ah_get_pending_interrupts */ ar9300_get_interrupts, /* ah_get_interrupts */ ar9300_set_interrupts, /* ah_set_interrupts */ ar9300_set_intr_mitigation_timer, /* ah_set_intr_mitigation_timer */ ar9300_get_intr_mitigation_timer, /* ah_get_intr_mitigation_timer */ ar9300ForceVCS, ar9300SetDfs3StreamFix, ar9300Get3StreamSignature, /* 11n specific functions (NOT applicable to ar9300) */ ar9300_set_11n_tx_desc, /* ah_set_11n_tx_desc */ /* Update rxchain */ ar9300_set_rx_chainmask, /*ah_set_rx_chainmask*/ /*Updating locationing register */ ar9300_update_loc_ctl_reg, /*ah_update_loc_ctl_reg*/ /* Start PAPRD functions */ ar9300_set_paprd_tx_desc, /* ah_set_paprd_tx_desc */ ar9300_paprd_init_table, /* ah_paprd_init_table */ ar9300_paprd_setup_gain_table, /* ah_paprd_setup_gain_table */ ar9300_paprd_create_curve, /* ah_paprd_create_curve */ ar9300_paprd_is_done, /* ah_paprd_is_done */ ar9300_enable_paprd, /* ah_PAPRDEnable */ ar9300_populate_paprd_single_table,/* ah_paprd_populate_table */ ar9300_is_tx_done, /* ah_is_tx_done */ ar9300_paprd_dec_tx_pwr, /* ah_paprd_dec_tx_pwr*/ ar9300_paprd_thermal_send, /* ah_paprd_thermal_send */ /* End PAPRD functions */ ar9300_set_11n_rate_scenario, /* ah_set_11n_rate_scenario */ ar9300_set_11n_aggr_first, /* ah_set_11n_aggr_first */ ar9300_set_11n_aggr_middle, /* ah_set_11n_aggr_middle */ ar9300_set_11n_aggr_last, /* ah_set_11n_aggr_last */ ar9300_clr_11n_aggr, /* ah_clr_11n_aggr */ ar9300_set_11n_rifs_burst_middle, /* ah_set_11n_rifs_burst_middle */ ar9300_set_11n_rifs_burst_last, /* ah_set_11n_rifs_burst_last */ ar9300_clr_11n_rifs_burst, /* ah_clr_11n_rifs_burst */ ar9300_set_11n_aggr_rifs_burst, /* ah_set_11n_aggr_rifs_burst */ ar9300_set_11n_rx_rifs, /* ah_set_11n_rx_rifs */ ar9300_set_smart_antenna, /* ah_setSmartAntenna */ ar9300_detect_bb_hang, /* ah_detect_bb_hang */ ar9300_detect_mac_hang, /* ah_detect_mac_hang */ ar9300_set_immunity, /* ah_immunity */ ar9300_get_hw_hangs, /* ah_get_hang_types */ ar9300_set_11n_burst_duration, /* ah_set_11n_burst_duration */ ar9300_set_11n_virtual_more_frag, /* ah_set_11n_virtual_more_frag */ ar9300_get_11n_ext_busy, /* ah_get_11n_ext_busy */ ar9300_set_11n_mac2040, /* ah_set_11n_mac2040 */ ar9300_get_11n_rx_clear, /* ah_get_11n_rx_clear */ ar9300_set_11n_rx_clear, /* ah_set_11n_rx_clear */ ar9300_get_mib_cycle_counts_pct, /* ah_get_mib_cycle_counts_pct */ ar9300_dma_reg_dump, /* ah_dma_reg_dump */ /* force_ppm specific functions */ ar9300_ppm_get_rssi_dump, /* ah_ppm_get_rssi_dump */ ar9300_ppm_arm_trigger, /* ah_ppm_arm_trigger */ ar9300_ppm_get_trigger, /* ah_ppm_get_trigger */ ar9300_ppm_force, /* ah_ppm_force */ ar9300_ppm_un_force, /* ah_ppm_un_force */ ar9300_ppm_get_force_state, /* ah_ppm_get_force_state */ ar9300_get_spur_info, /* ah_get_spur_info */ ar9300_set_spur_info, /* ah_get_spur_info */ ar9300_get_min_cca_pwr, /* ah_ar_get_noise_floor_val */ ar9300_green_ap_ps_on_off, /* ah_set_rx_green_ap_ps_on_off */ ar9300_is_single_ant_power_save_possible, /* ah_is_single_ant_power_save_possible */ /* radio measurement specific functions */ ar9300_get_mib_cycle_counts, /* ah_get_mib_cycle_counts */ ar9300_get_vow_stats, /* ah_get_vow_stats */ ar9300_clear_mib_counters, /* ah_clear_mib_counters */ #if ATH_GEN_RANDOMNESS ar9300_get_rssi_chain0, /* ah_get_rssi_chain0 */ #endif #ifdef ATH_BT_COEX /* Bluetooth Coexistence functions */ ar9300_set_bt_coex_info, /* ah_set_bt_coex_info */ ar9300_bt_coex_config, /* ah_bt_coex_config */ ar9300_bt_coex_set_qcu_thresh, /* ah_bt_coex_set_qcu_thresh */ ar9300_bt_coex_set_weights, /* ah_bt_coex_set_weights */ ar9300_bt_coex_setup_bmiss_thresh, /* ah_bt_coex_set_bmiss_thresh */ ar9300_bt_coex_set_parameter, /* ah_bt_coex_set_parameter */ ar9300_bt_coex_disable, /* ah_bt_coex_disable */ ar9300_bt_coex_enable, /* ah_bt_coex_enable */ ar9300_get_bt_active_gpio, /* ah_bt_coex_info*/ ar9300_get_wlan_active_gpio, /* ah__coex_wlan_info*/ #endif /* Generic Timer functions */ ar9300_alloc_generic_timer, /* ah_gentimer_alloc */ ar9300_free_generic_timer, /* ah_gentimer_free */ ar9300_start_generic_timer, /* ah_gentimer_start */ ar9300_stop_generic_timer, /* ah_gentimer_stop */ ar9300_get_gen_timer_interrupts, /* ah_gentimer_get_intr */ ar9300_set_dcs_mode, /* ah_set_dcs_mode */ ar9300_get_dcs_mode, /* ah_get_dcs_mode */ #if ATH_ANT_DIV_COMB ar9300_ant_div_comb_get_config, /* ah_get_ant_dvi_comb_conf */ ar9300_ant_div_comb_set_config, /* ah_set_ant_dvi_comb_conf */ #endif ar9300_get_bb_panic_info, /* ah_get_bb_panic_info */ ar9300_handle_radar_bb_panic, /* ah_handle_radar_bb_panic */ ar9300_set_hal_reset_reason, /* ah_set_hal_reset_reason */ #if ATH_PCIE_ERROR_MONITOR ar9300_start_pcie_error_monitor, /* ah_start_pcie_error_monitor */ ar9300_read_pcie_error_monitor, /* ah_read_pcie_error_monitor*/ ar9300_stop_pcie_error_monitor, /* ah_stop_pcie_error_monitor*/ #endif /* ATH_PCIE_ERROR_MONITOR */ #if ATH_SUPPORT_SPECTRAL /* Spectral scan */ ar9300_configure_spectral_scan, /* ah_ar_configure_spectral */ ar9300_get_spectral_params, /* ah_ar_get_spectral_config */ ar9300_start_spectral_scan, /* ah_ar_start_spectral_scan */ ar9300_stop_spectral_scan, /* ah_ar_stop_spectral_scan */ ar9300_is_spectral_enabled, /* ah_ar_is_spectral_enabled */ ar9300_is_spectral_active, /* ah_ar_is_spectral_active */ ar9300_get_ctl_chan_nf, /* ah_ar_get_ctl_nf */ ar9300_get_ext_chan_nf, /* ah_ar_get_ext_nf */ #endif /* ATH_SUPPORT_SPECTRAL */ ar9300_promisc_mode, /* ah_promisc_mode */ ar9300_read_pktlog_reg, /* ah_read_pktlog_reg */ ar9300_write_pktlog_reg, /* ah_write_pktlog_reg */ ar9300_set_proxy_sta, /* ah_set_proxy_sta */ ar9300_get_cal_intervals, /* ah_get_cal_intervals */ #if ATH_TRAFFIC_FAST_RECOVER ar9300_get_pll3_sqsum_dvc, /* ah_get_pll3_sqsum_dvc */ #endif #ifdef ATH_SUPPORT_HTC AH_NULL, #endif #ifdef ATH_TX99_DIAG /* Tx99 functions */ #ifdef ATH_SUPPORT_HTC AH_NULL, AH_NULL, AH_NULL, AH_NULL, AH_NULL, AH_NULL, AH_NULL, #else AH_NULL, AH_NULL, ar9300_tx99_channel_pwr_update, /* ah_tx99channelpwrupdate */ ar9300_tx99_start, /* ah_tx99start */ ar9300_tx99_stop, /* ah_tx99stop */ ar9300_tx99_chainmsk_setup, /* ah_tx99_chainmsk_setup */ ar9300_tx99_set_single_carrier, /* ah_tx99_set_single_carrier */ #endif #endif ar9300_chk_rssi_update_tx_pwr, ar9300_is_skip_paprd_by_greentx, /* ah_is_skip_paprd_by_greentx */ ar9300_hwgreentx_set_pal_spare, /* ah_hwgreentx_set_pal_spare */ #if ATH_SUPPORT_MCI /* MCI Coexistence Functions */ ar9300_mci_setup, /* ah_mci_setup */ ar9300_mci_send_message, /* ah_mci_send_message */ ar9300_mci_get_interrupt, /* ah_mci_get_interrupt */ ar9300_mci_state, /* ah_mci_state */ ar9300_mci_detach, /* ah_mci_detach */ #endif ar9300_reset_hw_beacon_proc_crc, /* ah_reset_hw_beacon_proc_crc */ ar9300_get_hw_beacon_rssi, /* ah_get_hw_beacon_rssi */ ar9300_set_hw_beacon_rssi_threshold,/*ah_set_hw_beacon_rssi_threshold*/ ar9300_reset_hw_beacon_rssi, /* ah_reset_hw_beacon_rssi */ ar9300_mat_enable, /* ah_mat_enable */ ar9300_dump_keycache, /* ah_dump_keycache */ ar9300_is_ani_noise_spur, /* ah_is_ani_noise_spur */ ar9300_set_hw_beacon_proc, /* ah_set_hw_beacon_proc */ ar9300_set_ctl_pwr, /* ah_set_ctl_pwr */ ar9300_set_txchainmaskopt, /* ah_set_txchainmaskopt */ }, ar9300_get_channel_edges, /* ah_get_channel_edges */ ar9300_get_wireless_modes, /* ah_get_wireless_modes */ ar9300_eeprom_read_word, /* ah_eeprom_read */ AH_NULL, ar9300_eeprom_dump_support, /* ah_eeprom_dump */ ar9300_get_chip_power_limits, /* ah_get_chip_power_limits */ ar9300_get_nf_adjust, /* ah_get_nf_adjust */ /* rest is zero'd by compiler */ }; #endif /* * Read MAC version/revision information from Chip registers and initialize * local data structures. */ void ar9300_read_revisions(struct ath_hal *ah) { u_int32_t val; /* XXX verify if this is the correct way to read revision on Osprey */ /* new SREV format for Sowl and later */ val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)); if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9340) { /* XXX: AR_SREV register in Wasp reads 0 */ AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_WASP; } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_QCA955X) { /* XXX: AR_SREV register in Scorpion reads 0 */ AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_SCORPION; } else { /* * Include 6-bit Chip Type (masked to 0) * to differentiate from pre-Sowl versions */ AH_PRIVATE(ah)->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; } #ifdef AH_SUPPORT_HORNET /* * EV74984, due to Hornet 1.1 didn't update WMAC revision, * so that have to read SoC's revision ID instead */ if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_HORNET) { #define AR_SOC_RST_REVISION_ID 0xB8060090 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) if ((REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_HORNET_11_MASK) == AR_SREV_REVISION_HORNET_11) { AH_PRIVATE(ah)->ah_macRev = AR_SREV_REVISION_HORNET_11; } else { AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2); } #undef REG_READ #undef AR_SOC_RST_REVISION_ID } else #endif if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_WASP) { #define AR_SOC_RST_REVISION_ID 0xB8060090 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) AH_PRIVATE(ah)->ah_macRev = REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_WASP_MASK; #undef REG_READ #undef AR_SOC_RST_REVISION_ID } else AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2); if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { AH_PRIVATE(ah)->ah_ispcie = AH_TRUE; } else { AH_PRIVATE(ah)->ah_ispcie = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; } } /* * Attach for an AR9300 part. */ struct ath_hal * ar9300_attach(u_int16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, HAL_OPS_CONFIG *ah_config, HAL_STATUS *status) { struct ath_hal_9300 *ahp; struct ath_hal *ah; struct ath_hal_private *ahpriv; HAL_STATUS ecode; HAL_NO_INTERSPERSED_READS; /* NB: memory is returned zero'd */ ahp = ar9300_new_state(devid, sc, st, sh, eepromdata, ah_config, status); if (ahp == AH_NULL) { return AH_NULL; } ah = &ahp->ah_priv.h; ar9300_init_offsets(ah, devid); ahpriv = AH_PRIVATE(ah); // AH_PRIVATE(ah)->ah_bustype = bustype; /* FreeBSD: to make OTP work for now, provide this.. */ AH9300(ah)->ah_cal_mem = ath_hal_malloc(HOST_CALDATA_SIZE); if (AH9300(ah)->ah_cal_mem == NULL) { ath_hal_printf(ah, "%s: caldata malloc failed!\n", __func__); ecode = HAL_EIO; goto bad; } /* * If eepromdata is not NULL, copy it it into ah_cal_mem. */ if (eepromdata != NULL) OS_MEMCPY(AH9300(ah)->ah_cal_mem, eepromdata, HOST_CALDATA_SIZE); /* XXX FreeBSD: enable RX mitigation */ ah->ah_config.ath_hal_intr_mitigation_rx = 1; /* interrupt mitigation */ #ifdef AR5416_INT_MITIGATION if (ah->ah_config.ath_hal_intr_mitigation_rx != 0) { ahp->ah_intr_mitigation_rx = AH_TRUE; } #else /* Enable Rx mitigation (default) */ ahp->ah_intr_mitigation_rx = AH_TRUE; ah->ah_config.ath_hal_intr_mitigation_rx = 1; #endif #ifdef HOST_OFFLOAD /* Reset default Rx mitigation values for Hornet */ if (AR_SREV_HORNET(ah)) { ahp->ah_intr_mitigation_rx = AH_FALSE; #ifdef AR5416_INT_MITIGATION ah->ah_config.ath_hal_intr_mitigation_rx = 0; #endif } #endif if (ah->ah_config.ath_hal_intr_mitigation_tx != 0) { ahp->ah_intr_mitigation_tx = AH_TRUE; } /* * Read back AR_WA into a permanent copy and set bits 14 and 17. * We need to do this to avoid RMW of this register. * Do this before calling ar9300_set_reset_reg. * If not, the AR_WA register which was inited via EEPROM * will get wiped out. */ ahp->ah_wa_reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_WA)); /* Set Bits 14 and 17 in the AR_WA register. */ ahp->ah_wa_reg_val |= AR_WA_D3_TO_L1_DISABLE | AR_WA_ASPM_TIMER_BASED_DISABLE; if (!ar9300_set_reset_reg(ah, HAL_RESET_POWER_ON)) { /* reset chip */ HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't reset chip\n", __func__); ecode = HAL_EIO; goto bad; } if (AR_SREV_JUPITER(ah) #if ATH_WOW_OFFLOAD && !HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_SET_4004_BIT14) #endif ) { /* Jupiter doesn't need bit 14 to be set. */ ahp->ah_wa_reg_val &= ~AR_WA_D3_TO_L1_DISABLE; OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val); } #if ATH_SUPPORT_MCI if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { #if 0 ah->ah_bt_coex_set_weights = ar9300_mci_bt_coex_set_weights; ah->ah_bt_coex_disable = ar9300_mci_bt_coex_disable; ah->ah_bt_coex_enable = ar9300_mci_bt_coex_enable; #endif ahp->ah_mci_ready = AH_FALSE; ahp->ah_mci_bt_state = MCI_BT_SLEEP; ahp->ah_mci_coex_major_version_wlan = MCI_GPM_COEX_MAJOR_VERSION_WLAN; ahp->ah_mci_coex_minor_version_wlan = MCI_GPM_COEX_MINOR_VERSION_WLAN; ahp->ah_mci_coex_major_version_bt = MCI_GPM_COEX_MAJOR_VERSION_DEFAULT; ahp->ah_mci_coex_minor_version_bt = MCI_GPM_COEX_MINOR_VERSION_DEFAULT; ahp->ah_mci_coex_bt_version_known = AH_FALSE; ahp->ah_mci_coex_2g5g_update = AH_TRUE; /* track if 2g5g status sent */ /* will be updated before boot up sequence */ ahp->ah_mci_coex_is_2g = AH_TRUE; ahp->ah_mci_coex_wlan_channels_update = AH_FALSE; ahp->ah_mci_coex_wlan_channels[0] = 0x00000000; ahp->ah_mci_coex_wlan_channels[1] = 0xffffffff; ahp->ah_mci_coex_wlan_channels[2] = 0xffffffff; ahp->ah_mci_coex_wlan_channels[3] = 0x7fffffff; ahp->ah_mci_query_bt = AH_TRUE; /* In case WLAN start after BT */ ahp->ah_mci_unhalt_bt_gpm = AH_TRUE; /* Send UNHALT at beginning */ ahp->ah_mci_halted_bt_gpm = AH_FALSE; /* Allow first HALT */ ahp->ah_mci_need_flush_btinfo = AH_FALSE; ahp->ah_mci_wlan_cal_seq = 0; ahp->ah_mci_wlan_cal_done = 0; } #endif /* ATH_SUPPORT_MCI */ #if ATH_WOW_OFFLOAD ahp->ah_mcast_filter_l32_set = 0; ahp->ah_mcast_filter_u32_set = 0; #endif if (AR_SREV_HORNET(ah)) { #ifdef AH_SUPPORT_HORNET if (!AR_SREV_HORNET_11(ah)) { /* * Do not check bootstrap register, which cannot be trusted * due to s26 switch issue on CUS164/AP121. */ ahp->clk_25mhz = 1; HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n"); } else { /* check bootstrap clock setting */ #define AR_SOC_SEL_25M_40M 0xB80600AC #define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val); #define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) if (REG_READ(AR_SOC_SEL_25M_40M) & 0x1) { ahp->clk_25mhz = 0; HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 40MHz\n"); } else { ahp->clk_25mhz = 1; HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n"); } #undef REG_READ #undef REG_WRITE #undef AR_SOC_SEL_25M_40M } #endif /* AH_SUPPORT_HORNET */ } if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { /* check bootstrap clock setting */ #define AR9340_SOC_SEL_25M_40M 0xB80600B0 #define AR9340_REF_CLK_40 (1 << 4) /* 0 - 25MHz 1 - 40 MHz */ #define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) if (REG_READ(AR9340_SOC_SEL_25M_40M) & AR9340_REF_CLK_40) { ahp->clk_25mhz = 0; HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 40MHz\n"); } else { ahp->clk_25mhz = 1; HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n"); } #undef REG_READ #undef AR9340_SOC_SEL_25M_40M #undef AR9340_REF_CLK_40 } ar9300_init_pll(ah, AH_NULL); if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't wakeup chip\n", __func__); ecode = HAL_EIO; goto bad; } /* No serialization of Register Accesses needed. */ ah->ah_config.ah_serialise_reg_war = SER_REG_MODE_OFF; HALDEBUG(ah, HAL_DEBUG_RESET, "%s: ah_serialise_reg_war is %d\n", __func__, ah->ah_config.ah_serialise_reg_war); /* * Add mac revision check when needed. * - Osprey 1.0 and 2.0 no longer supported. */ if (((ahpriv->ah_macVersion == AR_SREV_VERSION_OSPREY) && (ahpriv->ah_macRev <= AR_SREV_REVISION_OSPREY_20)) || (ahpriv->ah_macVersion != AR_SREV_VERSION_OSPREY && ahpriv->ah_macVersion != AR_SREV_VERSION_WASP && ahpriv->ah_macVersion != AR_SREV_VERSION_HORNET && ahpriv->ah_macVersion != AR_SREV_VERSION_POSEIDON && ahpriv->ah_macVersion != AR_SREV_VERSION_SCORPION && ahpriv->ah_macVersion != AR_SREV_VERSION_JUPITER && ahpriv->ah_macVersion != AR_SREV_VERSION_APHRODITE) ) { HALDEBUG(ah, HAL_DEBUG_RESET, "%s: Mac Chip Rev 0x%02x.%x is not supported by this driver\n", __func__, ahpriv->ah_macVersion, ahpriv->ah_macRev); ecode = HAL_ENOTSUPP; goto bad; } AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); /* Setup supported calibrations */ ahp->ah_iq_cal_data.cal_data = &iq_cal_single_sample; ahp->ah_supp_cals = IQ_MISMATCH_CAL; /* Enable ANI */ ahp->ah_ani_function = HAL_ANI_ALL; /* Enable RIFS */ ahp->ah_rifs_enabled = AH_TRUE; /* by default, stop RX also in abort txdma, due to "Unable to stop TxDMA" msg observed */ ahp->ah_abort_txdma_norx = AH_TRUE; /* do not use optional tx chainmask by default */ ahp->ah_tx_chainmaskopt = 0; ahp->ah_skip_rx_iq_cal = AH_FALSE; ahp->ah_rx_cal_complete = AH_FALSE; ahp->ah_rx_cal_chan = 0; ahp->ah_rx_cal_chan_flag = 0; HALDEBUG(ah, HAL_DEBUG_RESET, "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__, ahpriv->ah_macVersion, ahpriv->ah_macRev); if (AR_SREV_HORNET_12(ah)) { /* mac */ INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], ar9331_hornet1_2_mac_core, ARRAY_LENGTH(ar9331_hornet1_2_mac_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], ar9331_hornet1_2_mac_postamble, ARRAY_LENGTH(ar9331_hornet1_2_mac_postamble), 5); /* bb */ INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], ar9331_hornet1_2_baseband_core, ARRAY_LENGTH(ar9331_hornet1_2_baseband_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], ar9331_hornet1_2_baseband_postamble, ARRAY_LENGTH(ar9331_hornet1_2_baseband_postamble), 5); /* radio */ INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], ar9331_hornet1_2_radio_core, ARRAY_LENGTH(ar9331_hornet1_2_radio_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0); /* soc */ INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], ar9331_hornet1_2_soc_preamble, ARRAY_LENGTH(ar9331_hornet1_2_soc_preamble), 2); INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], ar9331_hornet1_2_soc_postamble, ARRAY_LENGTH(ar9331_hornet1_2_soc_postamble), 2); /* rx/tx gain */ INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9331_common_rx_gain_hornet1_2, ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2); INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9331_modes_lowest_ob_db_tx_gain_hornet1_2, ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5); ah->ah_config.ath_hal_pcie_power_save_enable = 0; /* Japan 2484Mhz CCK settings */ INIT_INI_ARRAY(&ahp->ah_ini_japan2484, ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484, ARRAY_LENGTH( ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484), 2); #if 0 /* ATH_WOW */ /* SerDes values during WOW sleep */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); #endif /* additional clock settings */ if (AH9300(ah)->clk_25mhz) { INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, ar9331_hornet1_2_xtal_25M, ARRAY_LENGTH(ar9331_hornet1_2_xtal_25M), 2); } else { INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, ar9331_hornet1_2_xtal_40M, ARRAY_LENGTH(ar9331_hornet1_2_xtal_40M), 2); } } else if (AR_SREV_HORNET_11(ah)) { /* mac */ INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], ar9331_hornet1_1_mac_core, ARRAY_LENGTH(ar9331_hornet1_1_mac_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], ar9331_hornet1_1_mac_postamble, ARRAY_LENGTH(ar9331_hornet1_1_mac_postamble), 5); /* bb */ INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], ar9331_hornet1_1_baseband_core, ARRAY_LENGTH(ar9331_hornet1_1_baseband_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], ar9331_hornet1_1_baseband_postamble, ARRAY_LENGTH(ar9331_hornet1_1_baseband_postamble), 5); /* radio */ INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], ar9331_hornet1_1_radio_core, ARRAY_LENGTH(ar9331_hornet1_1_radio_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0); /* soc */ INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], ar9331_hornet1_1_soc_preamble, ARRAY_LENGTH(ar9331_hornet1_1_soc_preamble), 2); INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], ar9331_hornet1_1_soc_postamble, ARRAY_LENGTH(ar9331_hornet1_1_soc_postamble), 2); /* rx/tx gain */ INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9331_common_rx_gain_hornet1_1, ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2); INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9331_modes_lowest_ob_db_tx_gain_hornet1_1, ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5); ah->ah_config.ath_hal_pcie_power_save_enable = 0; /* Japan 2484Mhz CCK settings */ INIT_INI_ARRAY(&ahp->ah_ini_japan2484, ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484, ARRAY_LENGTH( ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484), 2); #if 0 /* ATH_WOW */ /* SerDes values during WOW sleep */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, N(ar9300_pcie_phy_awow), 2); #endif /* additional clock settings */ if (AH9300(ah)->clk_25mhz) { INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, ar9331_hornet1_1_xtal_25M, ARRAY_LENGTH(ar9331_hornet1_1_xtal_25M), 2); } else { INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, ar9331_hornet1_1_xtal_40M, ARRAY_LENGTH(ar9331_hornet1_1_xtal_40M), 2); } } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { /* mac */ INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], ar9485_poseidon1_1_mac_core, ARRAY_LENGTH( ar9485_poseidon1_1_mac_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], ar9485_poseidon1_1_mac_postamble, ARRAY_LENGTH(ar9485_poseidon1_1_mac_postamble), 5); /* bb */ INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], ar9485_poseidon1_1, ARRAY_LENGTH(ar9485_poseidon1_1), 2); INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], ar9485_poseidon1_1_baseband_core, ARRAY_LENGTH(ar9485_poseidon1_1_baseband_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], ar9485_poseidon1_1_baseband_postamble, ARRAY_LENGTH(ar9485_poseidon1_1_baseband_postamble), 5); /* radio */ INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], ar9485_poseidon1_1_radio_core, ARRAY_LENGTH(ar9485_poseidon1_1_radio_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], ar9485_poseidon1_1_radio_postamble, ARRAY_LENGTH(ar9485_poseidon1_1_radio_postamble), 2); /* soc */ INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], ar9485_poseidon1_1_soc_preamble, ARRAY_LENGTH(ar9485_poseidon1_1_soc_preamble), 2); INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0); /* rx/tx gain */ INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9485_common_wo_xlna_rx_gain_poseidon1_1, ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1, ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5); /* Japan 2484Mhz CCK settings */ INIT_INI_ARRAY(&ahp->ah_ini_japan2484, ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484, ARRAY_LENGTH( ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484), 2); /* Load PCIE SERDES settings from INI */ if (ah->ah_config.ath_hal_pcie_clock_req) { /* Pci-e Clock Request = 1 */ if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_CONTROL) { /* Sleep Setting */ if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D3) { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, ARRAY_LENGTH( ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 2); } else { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1, ARRAY_LENGTH( ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1), 2); } /* Awake Setting */ if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D0) { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, ARRAY_LENGTH( ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 2); } else { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1, ARRAY_LENGTH( ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1), 2); } } else { /*Use driver default setting*/ /* Sleep Setting */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 2); /* Awake Setting */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 2); } } else { /* Pci-e Clock Request = 0 */ if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_CONTROL) { /* Sleep Setting */ if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D3) { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, ARRAY_LENGTH( ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 2); } else { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1, ARRAY_LENGTH( ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1), 2); } /* Awake Setting */ if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D0) { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, ARRAY_LENGTH( ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 2); } else { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1, ARRAY_LENGTH( ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1), 2); } } else { /*Use driver default setting*/ /* Sleep Setting */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 2); /* Awake Setting */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 2); } } /* pcie ps setting will honor registry setting, default is 0 */ //ah->ah_config.ath_hal_pciePowerSaveEnable = 0; } else if (AR_SREV_POSEIDON(ah)) { /* mac */ INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], ar9485_poseidon1_0_mac_core, ARRAY_LENGTH(ar9485_poseidon1_0_mac_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], ar9485_poseidon1_0_mac_postamble, ARRAY_LENGTH(ar9485_poseidon1_0_mac_postamble), 5); /* bb */ INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], ar9485_poseidon1_0, ARRAY_LENGTH(ar9485_poseidon1_0), 2); INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], ar9485_poseidon1_0_baseband_core, ARRAY_LENGTH(ar9485_poseidon1_0_baseband_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], ar9485_poseidon1_0_baseband_postamble, ARRAY_LENGTH(ar9485_poseidon1_0_baseband_postamble), 5); /* radio */ INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], ar9485_poseidon1_0_radio_core, ARRAY_LENGTH(ar9485_poseidon1_0_radio_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], ar9485_poseidon1_0_radio_postamble, ARRAY_LENGTH(ar9485_poseidon1_0_radio_postamble), 2); /* soc */ INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], ar9485_poseidon1_0_soc_preamble, ARRAY_LENGTH(ar9485_poseidon1_0_soc_preamble), 2); INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0); /* rx/tx gain */ INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9485Common_wo_xlna_rx_gain_poseidon1_0, ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0, ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5); /* Japan 2484Mhz CCK settings */ INIT_INI_ARRAY(&ahp->ah_ini_japan2484, ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484, ARRAY_LENGTH( ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484), 2); /* Load PCIE SERDES settings from INI */ if (ah->ah_config.ath_hal_pcie_clock_req) { /* Pci-e Clock Request = 1 */ if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_CONTROL) { /* Sleep Setting */ if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D3) { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1, ARRAY_LENGTH( ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1), 2); } else { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, ARRAY_LENGTH( ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 2); } /* Awake Setting */ if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D0) { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1, ARRAY_LENGTH( ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1), 2); } else { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, ARRAY_LENGTH( ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 2); } } else { /*Use driver default setting*/ /* Sleep Setting */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, ARRAY_LENGTH( ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 2); /* Awake Setting */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, ARRAY_LENGTH( ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 2); } } else { /* Pci-e Clock Request = 0 */ if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_CONTROL) { /* Sleep Setting */ if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D3) { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1, ARRAY_LENGTH( ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1), 2); } else { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, ARRAY_LENGTH( ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 2); } /* Awake Setting */ if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D0) { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1, ARRAY_LENGTH( ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1), 2); } else { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, ARRAY_LENGTH( ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 2); } } else { /*Use driver default setting*/ /* Sleep Setting */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, ARRAY_LENGTH( ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 2); /* Awake Setting */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, ARRAY_LENGTH( ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 2); } } /* pcie ps setting will honor registry setting, default is 0 */ /*ah->ah_config.ath_hal_pcie_power_save_enable = 0;*/ #if 0 /* ATH_WOW */ /* SerDes values during WOW sleep */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); #endif } else if (AR_SREV_WASP(ah)) { /* mac */ INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], ar9340_wasp_1p0_mac_core, ARRAY_LENGTH(ar9340_wasp_1p0_mac_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], ar9340_wasp_1p0_mac_postamble, ARRAY_LENGTH(ar9340_wasp_1p0_mac_postamble), 5); /* bb */ INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], ar9340_wasp_1p0_baseband_core, ARRAY_LENGTH(ar9340_wasp_1p0_baseband_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], ar9340_wasp_1p0_baseband_postamble, ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble), 5); /* radio */ INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], ar9340_wasp_1p0_radio_core, ARRAY_LENGTH(ar9340_wasp_1p0_radio_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], ar9340_wasp_1p0_radio_postamble, ARRAY_LENGTH(ar9340_wasp_1p0_radio_postamble), 5); /* soc */ INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], ar9340_wasp_1p0_soc_preamble, ARRAY_LENGTH(ar9340_wasp_1p0_soc_preamble), 2); INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], ar9340_wasp_1p0_soc_postamble, ARRAY_LENGTH(ar9340_wasp_1p0_soc_postamble), 5); /* rx/tx gain */ INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9340Common_wo_xlna_rx_gain_table_wasp_1p0, ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2); INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0, ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5); ah->ah_config.ath_hal_pcie_power_save_enable = 0; /* Fast clock modal settings */ INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, ar9340Modes_fast_clock_wasp_1p0, ARRAY_LENGTH(ar9340Modes_fast_clock_wasp_1p0), 3); /* Additional setttings for 40Mhz */ INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40mhz, ar9340_wasp_1p0_radio_core_40M, ARRAY_LENGTH(ar9340_wasp_1p0_radio_core_40M), 2); /* DFS */ INIT_INI_ARRAY(&ahp->ah_ini_dfs, ar9340_wasp_1p0_baseband_postamble_dfs_channel, ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble_dfs_channel), 3); } else if (AR_SREV_SCORPION(ah)) { /* mac */ INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], ar955x_scorpion_1p0_mac_core, ARRAY_LENGTH(ar955x_scorpion_1p0_mac_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], ar955x_scorpion_1p0_mac_postamble, ARRAY_LENGTH(ar955x_scorpion_1p0_mac_postamble), 5); /* bb */ INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], ar955x_scorpion_1p0_baseband_core, ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], ar955x_scorpion_1p0_baseband_postamble, ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_postamble), 5); /* radio */ INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], ar955x_scorpion_1p0_radio_core, ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], ar955x_scorpion_1p0_radio_postamble, ARRAY_LENGTH(ar955x_scorpion_1p0_radio_postamble), 5); /* soc */ INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], ar955x_scorpion_1p0_soc_preamble, ARRAY_LENGTH(ar955x_scorpion_1p0_soc_preamble), 2); INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], ar955x_scorpion_1p0_soc_postamble, ARRAY_LENGTH(ar955x_scorpion_1p0_soc_postamble), 5); /* rx/tx gain */ INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0, ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2); INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0, ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5); INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar955xModes_no_xpa_tx_gain_table_scorpion_1p0, ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 5); /*ath_hal_pciePowerSaveEnable should be 2 for OWL/Condor and 0 for merlin */ ah->ah_config.ath_hal_pcie_power_save_enable = 0; /* Fast clock modal settings */ INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, ar955xModes_fast_clock_scorpion_1p0, ARRAY_LENGTH(ar955xModes_fast_clock_scorpion_1p0), 3); /* Additional setttings for 40Mhz */ //INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40M, // ar955x_scorpion_1p0_radio_core_40M, // ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core_40M), 2); } else if (AR_SREV_JUPITER_10(ah)) { /* Jupiter: new INI format (pre, core, post arrays per subsystem) */ /* mac */ INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], ar9300_jupiter_1p0_mac_core, ARRAY_LENGTH(ar9300_jupiter_1p0_mac_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], ar9300_jupiter_1p0_mac_postamble, ARRAY_LENGTH(ar9300_jupiter_1p0_mac_postamble), 5); /* bb */ INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], ar9300_jupiter_1p0_baseband_core, ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], ar9300_jupiter_1p0_baseband_postamble, ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_postamble), 5); /* radio */ INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], ar9300_jupiter_1p0_radio_core, ARRAY_LENGTH(ar9300_jupiter_1p0_radio_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], ar9300_jupiter_1p0_radio_postamble, ARRAY_LENGTH(ar9300_jupiter_1p0_radio_postamble), 5); /* soc */ INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], ar9300_jupiter_1p0_soc_preamble, ARRAY_LENGTH(ar9300_jupiter_1p0_soc_preamble), 2); INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], ar9300_jupiter_1p0_soc_postamble, ARRAY_LENGTH(ar9300_jupiter_1p0_soc_postamble), 5); /* rx/tx gain */ INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9300_common_rx_gain_table_jupiter_1p0, ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2); /* Load PCIE SERDES settings from INI */ if (ah->ah_config.ath_hal_pcie_clock_req) { /* Pci-e Clock Request = 1 */ /* * PLL ON + clkreq enable is not a valid combination, * thus to ignore ath_hal_pll_pwr_save, use PLL OFF. */ { /*Use driver default setting*/ /* Awake -> Sleep Setting */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0, ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0), 2); /* Sleep -> Awake Setting */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0, ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0), 2); } } else { /* * Since Jupiter 1.0 and 2.0 share the same device id and will be * installed with same INF, but Jupiter 1.0 has issue with PLL OFF. * * Force Jupiter 1.0 to use ON/ON setting. */ ah->ah_config.ath_hal_pll_pwr_save = 0; /* Pci-e Clock Request = 0 */ if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_CONTROL) { /* Awake -> Sleep Setting */ if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D3) { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0, ARRAY_LENGTH( ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0), 2); } else { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, ARRAY_LENGTH( ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 2); } /* Sleep -> Awake Setting */ if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D0) { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0, ARRAY_LENGTH( ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0), 2); } else { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, ARRAY_LENGTH( ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 2); } } else { /*Use driver default setting*/ /* Awake -> Sleep Setting */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, ARRAY_LENGTH( ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 2); /* Sleep -> Awake Setting */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, ARRAY_LENGTH( ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 2); } } /* * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and * 0 for merlin */ ah->ah_config.ath_hal_pcie_power_save_enable = 0; #if 0 // ATH_WOW /* SerDes values during WOW sleep */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); #endif /* Fast clock modal settings */ INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, ar9300_modes_fast_clock_jupiter_1p0, ARRAY_LENGTH(ar9300_modes_fast_clock_jupiter_1p0), 3); INIT_INI_ARRAY(&ahp->ah_ini_japan2484, ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484, ARRAY_LENGTH( ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484), 2); } else if (AR_SREV_JUPITER_20(ah)) { /* Jupiter: new INI format (pre, core, post arrays per subsystem) */ + /* FreeBSD: just override the registers for jupiter 2.1 */ + /* mac */ INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); - INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], - ar9300_jupiter_2p0_mac_core, - ARRAY_LENGTH(ar9300_jupiter_2p0_mac_core), 2); + + if (AR_SREV_JUPITER_21(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], + ar9462_2p1_mac_core, + ARRAY_LENGTH(ar9462_2p1_mac_core), 2); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], + ar9300_jupiter_2p0_mac_core, + ARRAY_LENGTH(ar9300_jupiter_2p0_mac_core), 2); + } + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], ar9300_jupiter_2p0_mac_postamble, ARRAY_LENGTH(ar9300_jupiter_2p0_mac_postamble), 5); /* bb */ INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], ar9300_jupiter_2p0_baseband_core, ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_core), 2); - INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], - ar9300_jupiter_2p0_baseband_postamble, - ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_postamble), 5); + if (AR_SREV_JUPITER_21(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], + ar9462_2p1_baseband_postamble, + ARRAY_LENGTH(ar9462_2p1_baseband_postamble), 5); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], + ar9300_jupiter_2p0_baseband_postamble, + ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_postamble), 5); + } + /* radio */ INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], ar9300_jupiter_2p0_radio_core, ARRAY_LENGTH(ar9300_jupiter_2p0_radio_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], ar9300_jupiter_2p0_radio_postamble, ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble), 5); INIT_INI_ARRAY(&ahp->ah_ini_radio_post_sys2ant, ar9300_jupiter_2p0_radio_postamble_sys2ant, ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble_sys2ant), 5); /* soc */ - INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], - ar9300_jupiter_2p0_soc_preamble, - ARRAY_LENGTH(ar9300_jupiter_2p0_soc_preamble), 2); + if (AR_SREV_JUPITER_21(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], + ar9462_2p1_soc_preamble, + ARRAY_LENGTH(ar9462_2p1_soc_preamble), 2); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], + ar9300_jupiter_2p0_soc_preamble, + ARRAY_LENGTH(ar9300_jupiter_2p0_soc_preamble), 2); + } INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], ar9300_jupiter_2p0_soc_postamble, ARRAY_LENGTH(ar9300_jupiter_2p0_soc_postamble), 5); /* rx/tx gain */ INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9300Common_rx_gain_table_jupiter_2p0, ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2); /* BTCOEX */ INIT_INI_ARRAY(&ahp->ah_ini_BTCOEX_MAX_TXPWR, ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table, ARRAY_LENGTH(ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table), 2); /* Load PCIE SERDES settings from INI */ if (ah->ah_config.ath_hal_pcie_clock_req) { /* Pci-e Clock Request = 1 */ /* * PLL ON + clkreq enable is not a valid combination, * thus to ignore ath_hal_pll_pwr_save, use PLL OFF. */ { /*Use driver default setting*/ /* Awake -> Sleep Setting */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0, ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0), 2); /* Sleep -> Awake Setting */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0, ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0), 2); } } else { /* Pci-e Clock Request = 0 */ if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_CONTROL) { /* Awake -> Sleep Setting */ if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D3) { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0, ARRAY_LENGTH( ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0), 2); } else { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, ARRAY_LENGTH( ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 2); } /* Sleep -> Awake Setting */ if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D0) { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0, ARRAY_LENGTH( ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0), 2); } else { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, ARRAY_LENGTH( ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 2); } } else { /*Use driver default setting*/ /* Awake -> Sleep Setting */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, ARRAY_LENGTH( ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 2); /* Sleep -> Awake Setting */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, ARRAY_LENGTH( ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 2); } } /* * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and * 0 for merlin */ ah->ah_config.ath_hal_pcie_power_save_enable = 0; #if 0 // ATH_WOW /* SerDes values during WOW sleep */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); #endif /* Fast clock modal settings */ INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, ar9300Modes_fast_clock_jupiter_2p0, ARRAY_LENGTH(ar9300Modes_fast_clock_jupiter_2p0), 3); INIT_INI_ARRAY(&ahp->ah_ini_japan2484, ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484, ARRAY_LENGTH( ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484), 2); } else if (AR_SREV_APHRODITE(ah)) { /* Aphrodite: new INI format (pre, core, post arrays per subsystem) */ /* mac */ INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], ar956X_aphrodite_1p0_mac_core, ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], ar956X_aphrodite_1p0_mac_postamble, ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_postamble), 5); /* bb */ INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], ar956X_aphrodite_1p0_baseband_core, ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], ar956X_aphrodite_1p0_baseband_postamble, ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_postamble), 5); //mark jupiter have but aphrodite don't have // /* radio */ // INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); // INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], // ar9300_aphrodite_1p0_radio_core, // ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_core), 2); // INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], // ar9300_aphrodite_1p0_radio_postamble, // ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_postamble), 5); /* soc */ INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], ar956X_aphrodite_1p0_soc_preamble, ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_preamble), 2); INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], ar956X_aphrodite_1p0_soc_postamble, ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_postamble), 5); /* rx/tx gain */ INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar956XCommon_rx_gain_table_aphrodite_1p0, ARRAY_LENGTH(ar956XCommon_rx_gain_table_aphrodite_1p0), 2); //INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, // ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0, // ARRAY_LENGTH(ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0), // 5); /* * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and * 0 for merlin */ ah->ah_config.ath_hal_pcie_power_save_enable = 0; #if 0 // ATH_WOW /* SerDes values during WOW sleep */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); #endif /* Fast clock modal settings */ INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, ar956XModes_fast_clock_aphrodite_1p0, ARRAY_LENGTH(ar956XModes_fast_clock_aphrodite_1p0), 3); } else if (AR_SREV_AR9580(ah)) { /* * AR9580/Peacock - * new INI format (pre, core, post arrays per subsystem) */ /* mac */ INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], ar9300_ar9580_1p0_mac_core, ARRAY_LENGTH(ar9300_ar9580_1p0_mac_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], ar9300_ar9580_1p0_mac_postamble, ARRAY_LENGTH(ar9300_ar9580_1p0_mac_postamble), 5); /* bb */ INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], ar9300_ar9580_1p0_baseband_core, ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], ar9300_ar9580_1p0_baseband_postamble, ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble), 5); /* radio */ INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], ar9300_ar9580_1p0_radio_core, ARRAY_LENGTH(ar9300_ar9580_1p0_radio_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], ar9300_ar9580_1p0_radio_postamble, ARRAY_LENGTH(ar9300_ar9580_1p0_radio_postamble), 5); /* soc */ INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], ar9300_ar9580_1p0_soc_preamble, ARRAY_LENGTH(ar9300_ar9580_1p0_soc_preamble), 2); INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], ar9300_ar9580_1p0_soc_postamble, ARRAY_LENGTH(ar9300_ar9580_1p0_soc_postamble), 5); /* rx/tx gain */ INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9300_common_rx_gain_table_ar9580_1p0, ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2); INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0, ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0), 5); /* DFS */ INIT_INI_ARRAY(&ahp->ah_ini_dfs, ar9300_ar9580_1p0_baseband_postamble_dfs_channel, ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble_dfs_channel), 3); /* Load PCIE SERDES settings from INI */ /*D3 Setting */ if (ah->ah_config.ath_hal_pcie_clock_req) { if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_CONTROL) { //registry control if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D3) { //bit1, in to D3 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300PciePhy_clkreq_enable_L1_ar9580_1p0, ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0), 2); } else { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, ARRAY_LENGTH( ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2); } } else {//no registry control, default is pll on INIT_INI_ARRAY( &ahp->ah_ini_pcie_serdes, ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, ARRAY_LENGTH( ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2); } } else { if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_CONTROL) { //registry control if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D3) { //bit1, in to D3 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300PciePhy_clkreq_disable_L1_ar9580_1p0, ARRAY_LENGTH( ar9300PciePhy_clkreq_disable_L1_ar9580_1p0), 2); } else { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, ARRAY_LENGTH( ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2); } } else {//no registry control, default is pll on INIT_INI_ARRAY( &ahp->ah_ini_pcie_serdes, ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, ARRAY_LENGTH( ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2); } } /*D0 Setting */ if (ah->ah_config.ath_hal_pcie_clock_req) { if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_CONTROL) { //registry control if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D0) { //bit2, out of D3 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9300PciePhy_clkreq_enable_L1_ar9580_1p0, ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0), 2); } else { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, ARRAY_LENGTH( ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2); } } else { //no registry control, default is pll on INIT_INI_ARRAY( &ahp->ah_ini_pcie_serdes_low_power, ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, ARRAY_LENGTH( ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2); } } else { if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_CONTROL) {//registry control if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D0) {//bit2, out of D3 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9300PciePhy_clkreq_disable_L1_ar9580_1p0, ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_ar9580_1p0), 2); } else { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, ARRAY_LENGTH( ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2); } } else { //no registry control, default is pll on INIT_INI_ARRAY( &ahp->ah_ini_pcie_serdes_low_power, ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, ARRAY_LENGTH( ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2); } } ah->ah_config.ath_hal_pcie_power_save_enable = 0; #if 0 /* ATH_WOW */ /* SerDes values during WOW sleep */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); #endif /* Fast clock modal settings */ INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, ar9300Modes_fast_clock_ar9580_1p0, ARRAY_LENGTH(ar9300Modes_fast_clock_ar9580_1p0), 3); INIT_INI_ARRAY(&ahp->ah_ini_japan2484, ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484, ARRAY_LENGTH( ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484), 2); } else { /* * Osprey 2.2 - new INI format (pre, core, post arrays per subsystem) */ /* mac */ INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], ar9300_osprey_2p2_mac_core, ARRAY_LENGTH(ar9300_osprey_2p2_mac_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], ar9300_osprey_2p2_mac_postamble, ARRAY_LENGTH(ar9300_osprey_2p2_mac_postamble), 5); /* bb */ INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], ar9300_osprey_2p2_baseband_core, ARRAY_LENGTH(ar9300_osprey_2p2_baseband_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], ar9300_osprey_2p2_baseband_postamble, ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble), 5); /* radio */ INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], ar9300_osprey_2p2_radio_core, ARRAY_LENGTH(ar9300_osprey_2p2_radio_core), 2); INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], ar9300_osprey_2p2_radio_postamble, ARRAY_LENGTH(ar9300_osprey_2p2_radio_postamble), 5); /* soc */ INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], ar9300_osprey_2p2_soc_preamble, ARRAY_LENGTH(ar9300_osprey_2p2_soc_preamble), 2); INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], ar9300_osprey_2p2_soc_postamble, ARRAY_LENGTH(ar9300_osprey_2p2_soc_postamble), 5); /* rx/tx gain */ INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9300_common_rx_gain_table_osprey_2p2, ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2); INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2, ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2), 5); /* DFS */ INIT_INI_ARRAY(&ahp->ah_ini_dfs, ar9300_osprey_2p2_baseband_postamble_dfs_channel, ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble_dfs_channel), 3); /* Load PCIE SERDES settings from INI */ /*D3 Setting */ if (ah->ah_config.ath_hal_pcie_clock_req) { if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_CONTROL) { //registry control if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D3) { //bit1, in to D3 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300PciePhy_clkreq_enable_L1_osprey_2p2, ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2), 2); } else { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, ARRAY_LENGTH( ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2); } } else {//no registry control, default is pll on #ifndef ATH_BUS_PM INIT_INI_ARRAY( &ahp->ah_ini_pcie_serdes, ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, ARRAY_LENGTH( ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2); #else //no registry control, default is pll off INIT_INI_ARRAY( &ahp->ah_ini_pcie_serdes, ar9300PciePhy_clkreq_disable_L1_osprey_2p2, ARRAY_LENGTH( ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2); #endif } } else { if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_CONTROL) { //registry control if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D3) { //bit1, in to D3 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300PciePhy_clkreq_disable_L1_osprey_2p2, ARRAY_LENGTH( ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2); } else { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, ARRAY_LENGTH( ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2); } } else { #ifndef ATH_BUS_PM //no registry control, default is pll on INIT_INI_ARRAY( &ahp->ah_ini_pcie_serdes, ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, ARRAY_LENGTH( ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2); #else //no registry control, default is pll off INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300PciePhy_clkreq_disable_L1_osprey_2p2, ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2); #endif } } /*D0 Setting */ if (ah->ah_config.ath_hal_pcie_clock_req) { if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_CONTROL) { //registry control if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D0) { //bit2, out of D3 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9300PciePhy_clkreq_enable_L1_osprey_2p2, ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2), 2); } else { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, ARRAY_LENGTH( ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2); } } else { //no registry control, default is pll on INIT_INI_ARRAY( &ahp->ah_ini_pcie_serdes_low_power, ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, ARRAY_LENGTH( ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2); } } else { if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_CONTROL) {//registry control if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D0) {//bit2, out of D3 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9300PciePhy_clkreq_disable_L1_osprey_2p2, ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2); } else { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, ARRAY_LENGTH( ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2); } } else { //no registry control, default is pll on INIT_INI_ARRAY( &ahp->ah_ini_pcie_serdes_low_power, ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, ARRAY_LENGTH( ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2); } } ah->ah_config.ath_hal_pcie_power_save_enable = 0; #ifdef ATH_BUS_PM /*Use HAL to config PCI powersave by writing into the SerDes Registers */ ah->ah_config.ath_hal_pcie_ser_des_write = 1; #endif #if 0 /* ATH_WOW */ /* SerDes values during WOW sleep */ INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); #endif /* Fast clock modal settings */ INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, ar9300Modes_fast_clock_osprey_2p2, ARRAY_LENGTH(ar9300Modes_fast_clock_osprey_2p2), 3); INIT_INI_ARRAY(&ahp->ah_ini_japan2484, ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484, ARRAY_LENGTH( ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484), 2); } if(AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { #define AR_SOC_RST_OTP_INTF 0xB80600B4 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) ahp->ah_enterprise_mode = REG_READ(AR_SOC_RST_OTP_INTF); if (AR_SREV_SCORPION(ah)) { ahp->ah_enterprise_mode = ahp->ah_enterprise_mode << 12; } ath_hal_printf (ah, "Enterprise mode: 0x%08x\n", ahp->ah_enterprise_mode); #undef REG_READ #undef AR_SOC_RST_OTP_INTF } else { ahp->ah_enterprise_mode = OS_REG_READ(ah, AR_ENT_OTP); } if (ahpriv->ah_ispcie) { ar9300_config_pci_power_save(ah, 0, 0); } else { ar9300_disable_pcie_phy(ah); } ath_hal_printf(ah, "%s: calling ar9300_hw_attach\n", __func__); ecode = ar9300_hw_attach(ah); if (ecode != HAL_OK) { goto bad; } /* set gain table pointers according to values read from the eeprom */ ar9300_tx_gain_table_apply(ah); ar9300_rx_gain_table_apply(ah); /* ** ** Got everything we need now to setup the capabilities. */ if (!ar9300_fill_capability_info(ah)) { HALDEBUG(ah, HAL_DEBUG_RESET, "%s:failed ar9300_fill_capability_info\n", __func__); ecode = HAL_EEREAD; goto bad; } ecode = ar9300_init_mac_addr(ah); if (ecode != HAL_OK) { HALDEBUG(ah, HAL_DEBUG_RESET, "%s: failed initializing mac address\n", __func__); goto bad; } /* * Initialize receive buffer size to MAC default */ ahp->rx_buf_size = HAL_RXBUFSIZE_DEFAULT; #if ATH_WOW #if 0 /* * Needs to be removed once we stop using XB92 XXX * FIXME: Check with latest boards too - SriniK */ ar9300_wow_set_gpio_reset_low(ah); #endif /* * Clear the Wow Status. */ OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)) | AR_PMCTRL_WOW_PME_CLR); OS_REG_WRITE(ah, AR_WOW_PATTERN_REG, AR_WOW_CLEAR_EVENTS(OS_REG_READ(ah, AR_WOW_PATTERN_REG))); #endif /* * Set the cur_trig_level to a value that works all modes - 11a/b/g or 11n * with aggregation enabled or disabled. */ ahp->ah_tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); if (AR_SREV_HORNET(ah)) { ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_HORNET_2GHZ; ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ; ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ; ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ; ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; } else if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){ ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_2GHZ; ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_2GHZ; ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_5GHZ; ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_5GHZ; ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; } else { ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_2GHZ; ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ; if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_PEACOCK_5GHZ; } else { ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ; } ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ; ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; } /* init BB Panic Watchdog timeout */ if (AR_SREV_HORNET(ah)) { ahp->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO_HORNET; } else { ahp->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO; } /* * Determine whether tx IQ calibration HW should be enabled, * and whether tx IQ calibration should be performed during * AGC calibration, or separately. */ if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { /* * Register not initialized yet. This flag will be re-initialized * after INI loading following each reset. */ ahp->tx_iq_cal_enable = 1; /* if tx IQ cal is enabled, do it together with AGC cal */ ahp->tx_iq_cal_during_agc_cal = 1; } else if (AR_SREV_POSEIDON_OR_LATER(ah) && !AR_SREV_WASP(ah)) { ahp->tx_iq_cal_enable = 1; ahp->tx_iq_cal_during_agc_cal = 1; } else { /* osprey, hornet, wasp */ ahp->tx_iq_cal_enable = 1; ahp->tx_iq_cal_during_agc_cal = 0; } return ah; bad: if (ahp) { ar9300_detach((struct ath_hal *) ahp); } if (status) { *status = ecode; } return AH_NULL; } void ar9300_detach(struct ath_hal *ah) { HALASSERT(ah != AH_NULL); HALASSERT(ah->ah_magic == AR9300_MAGIC); /* Make sure that chip is awake before writing to it */ if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: failed to wake up chip\n", __func__); } ar9300_hw_detach(ah); ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); // ath_hal_hdprintf_deregister(ah); if (AH9300(ah)->ah_cal_mem) ath_hal_free(AH9300(ah)->ah_cal_mem); AH9300(ah)->ah_cal_mem = AH_NULL; ath_hal_free(ah); } struct ath_hal_9300 * ar9300_new_state(u_int16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, HAL_OPS_CONFIG *ah_config, HAL_STATUS *status) { static const u_int8_t defbssidmask[IEEE80211_ADDR_LEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; struct ath_hal_9300 *ahp; struct ath_hal *ah; /* NB: memory is returned zero'd */ ahp = ath_hal_malloc(sizeof(struct ath_hal_9300)); if (ahp == AH_NULL) { HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "%s: cannot allocate memory for state block\n", __func__); *status = HAL_ENOMEM; return AH_NULL; } ah = &ahp->ah_priv.h; /* set initial values */ /* stub everything first */ ar9300_set_stub_functions(ah); /* setup the FreeBSD HAL methods */ ar9300_attach_freebsd_ops(ah); /* These are private to this particular file, so .. */ ah->ah_disablePCIE = ar9300_disable_pcie_phy; AH_PRIVATE(ah)->ah_getNfAdjust = ar9300_get_nf_adjust; AH_PRIVATE(ah)->ah_getChipPowerLimits = ar9300_get_chip_power_limits; #if 0 /* Attach Osprey structure as default hal structure */ OS_MEMCPY(&ahp->ah_priv.priv, &ar9300hal, sizeof(ahp->ah_priv.priv)); #endif #if 0 AH_PRIVATE(ah)->amem_handle = amem_handle; AH_PRIVATE(ah)->ah_osdev = osdev; #endif ah->ah_sc = sc; ah->ah_st = st; ah->ah_sh = sh; ah->ah_magic = AR9300_MAGIC; AH_PRIVATE(ah)->ah_devid = devid; AH_PRIVATE(ah)->ah_flags = 0; /* ** Initialize factory defaults in the private space */ // ath_hal_factory_defaults(AH_PRIVATE(ah), hal_conf_parm); ar9300_config_defaults_freebsd(ah, ah_config); /* XXX FreeBSD: cal is always in EEPROM */ #if 0 if (!hal_conf_parm->calInFlash) { AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM; } #endif AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM; #if 0 if (ar9300_eep_data_in_flash(ah)) { ahp->ah_priv.priv.ah_eeprom_read = ar9300_flash_read; ahp->ah_priv.priv.ah_eeprom_dump = AH_NULL; } else { ahp->ah_priv.priv.ah_eeprom_read = ar9300_eeprom_read_word; } #endif /* XXX FreeBSD - for now, just supports EEPROM reading */ ahp->ah_priv.ah_eepromRead = ar9300_eeprom_read_word; AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ ahp->ah_atim_window = 0; /* [0..1000] */ ahp->ah_diversity_control = ah->ah_config.ath_hal_diversity_control; ahp->ah_antenna_switch_swap = ah->ah_config.ath_hal_antenna_switch_swap; /* * Enable MIC handling. */ ahp->ah_sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE; ahp->ah_enable32k_hz_clock = DONT_USE_32KHZ;/* XXX */ ahp->ah_slot_time = (u_int) -1; ahp->ah_ack_timeout = (u_int) -1; OS_MEMCPY(&ahp->ah_bssid_mask, defbssidmask, IEEE80211_ADDR_LEN); /* * 11g-specific stuff */ ahp->ah_g_beacon_rate = 0; /* adhoc beacon fixed rate */ /* SM power mode: Attach time, disable any setting */ ahp->ah_sm_power_mode = HAL_SMPS_DEFAULT; return ahp; } HAL_BOOL ar9300_chip_test(struct ath_hal *ah) { /*u_int32_t reg_addr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };*/ u_int32_t reg_addr[2] = { AR_STA_ID0 }; u_int32_t reg_hold[2]; u_int32_t pattern_data[4] = { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; int i, j; /* Test PHY & MAC registers */ for (i = 0; i < 1; i++) { u_int32_t addr = reg_addr[i]; u_int32_t wr_data, rd_data; reg_hold[i] = OS_REG_READ(ah, addr); for (j = 0; j < 0x100; j++) { wr_data = (j << 16) | j; OS_REG_WRITE(ah, addr, wr_data); rd_data = OS_REG_READ(ah, addr); if (rd_data != wr_data) { HALDEBUG(ah, HAL_DEBUG_REGIO, "%s: address test failed addr: " "0x%08x - wr:0x%08x != rd:0x%08x\n", __func__, addr, wr_data, rd_data); return AH_FALSE; } } for (j = 0; j < 4; j++) { wr_data = pattern_data[j]; OS_REG_WRITE(ah, addr, wr_data); rd_data = OS_REG_READ(ah, addr); if (wr_data != rd_data) { HALDEBUG(ah, HAL_DEBUG_REGIO, "%s: address test failed addr: " "0x%08x - wr:0x%08x != rd:0x%08x\n", __func__, addr, wr_data, rd_data); return AH_FALSE; } } OS_REG_WRITE(ah, reg_addr[i], reg_hold[i]); } OS_DELAY(100); return AH_TRUE; } /* * Store the channel edges for the requested operational mode */ HAL_BOOL ar9300_get_channel_edges(struct ath_hal *ah, u_int16_t flags, u_int16_t *low, u_int16_t *high) { struct ath_hal_private *ahpriv = AH_PRIVATE(ah); HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps; if (flags & IEEE80211_CHAN_5GHZ) { *low = p_cap->halLow5GhzChan; *high = p_cap->halHigh5GhzChan; return AH_TRUE; } if ((flags & IEEE80211_CHAN_2GHZ)) { *low = p_cap->halLow2GhzChan; *high = p_cap->halHigh2GhzChan; return AH_TRUE; } return AH_FALSE; } HAL_BOOL ar9300_regulatory_domain_override(struct ath_hal *ah, u_int16_t regdmn) { AH_PRIVATE(ah)->ah_currentRD = regdmn; return AH_TRUE; } /* * Fill all software cached or static hardware state information. * Return failure if capabilities are to come from EEPROM and * cannot be read. */ HAL_BOOL ar9300_fill_capability_info(struct ath_hal *ah) { #define AR_KEYTABLE_SIZE 128 struct ath_hal_9300 *ahp = AH9300(ah); struct ath_hal_private *ahpriv = AH_PRIVATE(ah); HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps; u_int16_t cap_field = 0, eeval; ahpriv->ah_devType = (u_int16_t)ar9300_eeprom_get(ahp, EEP_DEV_TYPE); eeval = ar9300_eeprom_get(ahp, EEP_REG_0); /* XXX record serial number */ AH_PRIVATE(ah)->ah_currentRD = eeval; /* Always enable fast clock; leave it up to EEPROM and channel */ p_cap->halSupportsFastClock5GHz = AH_TRUE; p_cap->halIntrMitigation = AH_TRUE; eeval = ar9300_eeprom_get(ahp, EEP_REG_1); AH_PRIVATE(ah)->ah_currentRDext = eeval | AR9300_RDEXT_DEFAULT; /* Read the capability EEPROM location */ cap_field = ar9300_eeprom_get(ahp, EEP_OP_CAP); /* Construct wireless mode from EEPROM */ p_cap->halWirelessModes = 0; eeval = ar9300_eeprom_get(ahp, EEP_OP_MODE); /* * XXX FreeBSD specific: for now, set ath_hal_ht_enable to 1, * or we won't have 11n support. */ ah->ah_config.ath_hal_ht_enable = 1; if (eeval & AR9300_OPFLAGS_11A) { p_cap->halWirelessModes |= HAL_MODE_11A | ((!ah->ah_config.ath_hal_ht_enable || (eeval & AR9300_OPFLAGS_N_5G_HT20)) ? 0 : (HAL_MODE_11NA_HT20 | ((eeval & AR9300_OPFLAGS_N_5G_HT40) ? 0 : (HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS)))); } if (eeval & AR9300_OPFLAGS_11G) { p_cap->halWirelessModes |= HAL_MODE_11B | HAL_MODE_11G | ((!ah->ah_config.ath_hal_ht_enable || (eeval & AR9300_OPFLAGS_N_2G_HT20)) ? 0 : (HAL_MODE_11NG_HT20 | ((eeval & AR9300_OPFLAGS_N_2G_HT40) ? 0 : (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS)))); } /* Get chainamsks from eeprom */ p_cap->halTxChainMask = ar9300_eeprom_get(ahp, EEP_TX_MASK); p_cap->halRxChainMask = ar9300_eeprom_get(ahp, EEP_RX_MASK); #define owl_get_ntxchains(_txchainmask) \ (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) /* FreeBSD: Update number of TX/RX streams */ p_cap->halTxStreams = owl_get_ntxchains(p_cap->halTxChainMask); p_cap->halRxStreams = owl_get_ntxchains(p_cap->halRxChainMask); /* * This being a newer chip supports TKIP non-splitmic mode. * */ ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; p_cap->halTkipMicTxRxKeySupport = AH_TRUE; p_cap->halLow2GhzChan = 2312; p_cap->halHigh2GhzChan = 2732; p_cap->halLow5GhzChan = 4920; p_cap->halHigh5GhzChan = 6100; p_cap->halCipherCkipSupport = AH_FALSE; p_cap->halCipherTkipSupport = AH_TRUE; p_cap->halCipherAesCcmSupport = AH_TRUE; p_cap->halMicCkipSupport = AH_FALSE; p_cap->halMicTkipSupport = AH_TRUE; p_cap->halMicAesCcmSupport = AH_TRUE; p_cap->halChanSpreadSupport = AH_TRUE; p_cap->halSleepAfterBeaconBroken = AH_TRUE; p_cap->halBurstSupport = AH_TRUE; p_cap->halChapTuningSupport = AH_TRUE; p_cap->halTurboPrimeSupport = AH_TRUE; p_cap->halFastFramesSupport = AH_TRUE; p_cap->halTurboGSupport = p_cap->halWirelessModes & HAL_MODE_108G; // p_cap->hal_xr_support = AH_FALSE; p_cap->halHTSupport = ah->ah_config.ath_hal_ht_enable ? AH_TRUE : AH_FALSE; p_cap->halGTTSupport = AH_TRUE; p_cap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ p_cap->halNumMRRetries = 4; /* Hardware supports 4 MRR */ p_cap->halHTSGI20Support = AH_TRUE; p_cap->halVEOLSupport = AH_TRUE; p_cap->halBssIdMaskSupport = AH_TRUE; /* Bug 26802, fixed in later revs? */ p_cap->halMcastKeySrchSupport = AH_TRUE; p_cap->halTsfAddSupport = AH_TRUE; if (cap_field & AR_EEPROM_EEPCAP_MAXQCU) { p_cap->halTotalQueues = MS(cap_field, AR_EEPROM_EEPCAP_MAXQCU); } else { p_cap->halTotalQueues = HAL_NUM_TX_QUEUES; } if (cap_field & AR_EEPROM_EEPCAP_KC_ENTRIES) { p_cap->halKeyCacheSize = 1 << MS(cap_field, AR_EEPROM_EEPCAP_KC_ENTRIES); } else { p_cap->halKeyCacheSize = AR_KEYTABLE_SIZE; } p_cap->halFastCCSupport = AH_TRUE; // p_cap->hal_num_mr_retries = 4; // ahp->hal_tx_trig_level_max = MAX_TX_FIFO_THRESHOLD; p_cap->halNumGpioPins = AR9382_MAX_GPIO_PIN_NUM; #if 0 /* XXX Verify support in Osprey */ if (AR_SREV_MERLIN_10_OR_LATER(ah)) { p_cap->halWowSupport = AH_TRUE; p_cap->hal_wow_match_pattern_exact = AH_TRUE; if (AR_SREV_MERLIN(ah)) { p_cap->hal_wow_pattern_match_dword = AH_TRUE; } } else { p_cap->halWowSupport = AH_FALSE; p_cap->hal_wow_match_pattern_exact = AH_FALSE; } #endif p_cap->halWowSupport = AH_TRUE; p_cap->halWowMatchPatternExact = AH_TRUE; if (AR_SREV_POSEIDON(ah)) { p_cap->halWowMatchPatternExact = AH_TRUE; } p_cap->halCSTSupport = AH_TRUE; p_cap->halRifsRxSupport = AH_TRUE; p_cap->halRifsTxSupport = AH_TRUE; #define IEEE80211_AMPDU_LIMIT_MAX (65536) p_cap->halRtsAggrLimit = IEEE80211_AMPDU_LIMIT_MAX; #undef IEEE80211_AMPDU_LIMIT_MAX p_cap->halMfpSupport = ah->ah_config.ath_hal_mfp_support; p_cap->halForcePpmSupport = AH_TRUE; p_cap->halHwBeaconProcSupport = AH_TRUE; /* ar9300 - has the HW UAPSD trigger support, * but it has the following limitations * The power state change from the following * frames are not put in High priority queue. * i) Mgmt frames * ii) NoN QoS frames * iii) QoS frames form the access categories for which * UAPSD is not enabled. * so we can not enable this feature currently. * could be enabled, if these limitations are fixed * in later versions of ar9300 chips */ p_cap->halHasUapsdSupport = AH_FALSE; /* Number of buffers that can be help in a single TxD */ p_cap->halNumTxMaps = 4; p_cap->halTxDescLen = sizeof(struct ar9300_txc); p_cap->halTxStatusLen = sizeof(struct ar9300_txs); p_cap->halRxStatusLen = sizeof(struct ar9300_rxs); p_cap->halRxHpFifoDepth = HAL_HP_RXFIFO_DEPTH; p_cap->halRxLpFifoDepth = HAL_LP_RXFIFO_DEPTH; /* Enable extension channel DFS support */ p_cap->halUseCombinedRadarRssi = AH_TRUE; p_cap->halExtChanDfsSupport = AH_TRUE; #if ATH_SUPPORT_SPECTRAL p_cap->halSpectralScanSupport = AH_TRUE; #endif ahpriv->ah_rfsilent = ar9300_eeprom_get(ahp, EEP_RF_SILENT); if (ahpriv->ah_rfsilent & EEP_RFSILENT_ENABLED) { ahp->ah_gpio_select = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_GPIO_SEL); ahp->ah_polarity = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_POLARITY); ath_hal_enable_rfkill(ah, AH_TRUE); p_cap->halRfSilentSupport = AH_TRUE; } /* XXX */ p_cap->halWpsPushButtonSupport = AH_FALSE; #ifdef ATH_BT_COEX p_cap->halBtCoexSupport = AH_TRUE; p_cap->halBtCoexApsmWar = AH_FALSE; #endif p_cap->halGenTimerSupport = AH_TRUE; ahp->ah_avail_gen_timers = ~((1 << AR_FIRST_NDP_TIMER) - 1); ahp->ah_avail_gen_timers &= (1 << AR_NUM_GEN_TIMERS) - 1; /* * According to Kyungwan, generic timer 0 and 8 are special * timers. Remove timer 8 from the available gen timer list. * Jupiter testing shows timer won't trigger with timer 8. */ ahp->ah_avail_gen_timers &= ~(1 << AR_GEN_TIMER_RESERVED); if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { #if ATH_SUPPORT_MCI if (ah->ah_config.ath_hal_mci_config & ATH_MCI_CONFIG_DISABLE_MCI) { p_cap->halMciSupport = AH_FALSE; } else #endif { p_cap->halMciSupport = (ahp->ah_enterprise_mode & AR_ENT_OTP_49GHZ_DISABLE) ? AH_FALSE: AH_TRUE; } HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "%s: (MCI) MCI support = %d\n", __func__, p_cap->halMciSupport); } else { p_cap->halMciSupport = AH_FALSE; } if (AR_SREV_JUPITER_20(ah)) { p_cap->halRadioRetentionSupport = AH_TRUE; } else { p_cap->halRadioRetentionSupport = AH_FALSE; } p_cap->halAutoSleepSupport = AH_TRUE; p_cap->halMbssidAggrSupport = AH_TRUE; // p_cap->hal_proxy_sta_support = AH_TRUE; /* XXX Mark it true after it is verfied as fixed */ p_cap->hal4kbSplitTransSupport = AH_FALSE; /* Read regulatory domain flag */ if (AH_PRIVATE(ah)->ah_currentRDext & (1 << REG_EXT_JAPAN_MIDBAND)) { /* * If REG_EXT_JAPAN_MIDBAND is set, turn on U1 EVEN, U2, and MIDBAND. */ p_cap->halRegCap = AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | AR_EEPROM_EEREGCAP_EN_KK_U2 | AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; } else { p_cap->halRegCap = AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; } /* For AR9300 and above, midband channels are always supported */ p_cap->halRegCap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; p_cap->halNumAntCfg5GHz = ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_5GHZ); p_cap->halNumAntCfg2GHz = ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_2GHZ); /* STBC supported */ p_cap->halRxStbcSupport = 1; /* number of streams for STBC recieve. */ if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { p_cap->halTxStbcSupport = 0; } else { p_cap->halTxStbcSupport = 1; } p_cap->halEnhancedDmaSupport = AH_TRUE; p_cap->halEnhancedDfsSupport = AH_TRUE; /* * EV61133 (missing interrupts due to AR_ISR_RAC). * Fixed in Osprey 2.0. */ p_cap->halIsrRacSupport = AH_TRUE; /* XXX FreeBSD won't support TKIP and WEP aggregation */ #if 0 p_cap->hal_wep_tkip_aggr_support = AH_TRUE; p_cap->hal_wep_tkip_aggr_num_tx_delim = 10; /* TBD */ p_cap->hal_wep_tkip_aggr_num_rx_delim = 10; /* TBD */ p_cap->hal_wep_tkip_max_ht_rate = 15; /* TBD */ #endif /* * XXX FreeBSD won't need these; but eventually add them * and add the WARs - AGGR extra delim WAR is useful to know * about. */ #if 0 p_cap->hal_cfend_fix_support = AH_FALSE; p_cap->hal_aggr_extra_delim_war = AH_FALSE; #endif p_cap->halHasLongRxDescTsf = AH_TRUE; // p_cap->hal_rx_desc_timestamp_bits = 32; p_cap->halRxTxAbortSupport = AH_TRUE; p_cap->hal_ani_poll_interval = AR9300_ANI_POLLINTERVAL; p_cap->hal_channel_switch_time_usec = AR9300_CHANNEL_SWITCH_TIME_USEC; /* Transmit Beamforming supported, fill capabilities */ p_cap->halPaprdEnabled = ar9300_eeprom_get(ahp, EEP_PAPRD_ENABLED); p_cap->halChanHalfRate = !(ahp->ah_enterprise_mode & AR_ENT_OTP_10MHZ_DISABLE); p_cap->halChanQuarterRate = !(ahp->ah_enterprise_mode & AR_ENT_OTP_5MHZ_DISABLE); if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){ /* There is no AR_ENT_OTP_49GHZ_DISABLE feature in Jupiter, now the bit is used to disable BT. */ p_cap->hal49GhzSupport = 1; } else { p_cap->hal49GhzSupport = !(ahp->ah_enterprise_mode & AR_ENT_OTP_49GHZ_DISABLE); } if (AR_SREV_POSEIDON(ah) || AR_SREV_HORNET(ah) || AR_SREV_APHRODITE(ah)) { /* LDPC supported */ /* Poseidon doesn't support LDPC, or it will cause receiver CRC Error */ p_cap->halLDPCSupport = AH_FALSE; /* PCI_E LCR offset */ if (AR_SREV_POSEIDON(ah)) { p_cap->hal_pcie_lcr_offset = 0x80; /*for Poseidon*/ } /*WAR method for APSM L0s with Poseidon 1.0*/ if (AR_SREV_POSEIDON_10(ah)) { p_cap->hal_pcie_lcr_extsync_en = AH_TRUE; } } else { p_cap->halLDPCSupport = AH_TRUE; } /* XXX is this a flag, or a chainmask number? */ p_cap->halApmEnable = !! ar9300_eeprom_get(ahp, EEP_CHAIN_MASK_REDUCE); #if ATH_ANT_DIV_COMB if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah)) { if (ahp->ah_diversity_control == HAL_ANT_VARIABLE) { u_int8_t ant_div_control1 = ar9300_eeprom_get(ahp, EEP_ANTDIV_control); /* if enable_lnadiv is 0x1 and enable_fast_div is 0x1, * we enable the diversity-combining algorithm. */ if ((ant_div_control1 >> 0x6) == 0x3) { p_cap->halAntDivCombSupport = AH_TRUE; } p_cap->halAntDivCombSupportOrg = p_cap->halAntDivCombSupport; } } #endif /* ATH_ANT_DIV_COMB */ /* * FreeBSD: enable LNA mixing if the chip is Hornet or Poseidon. */ if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah)) { p_cap->halRxUsingLnaMixing = AH_TRUE; } /* * AR5416 and later NICs support MYBEACON filtering. */ p_cap->halRxDoMyBeacon = AH_TRUE; #if ATH_WOW_OFFLOAD if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) { p_cap->hal_wow_gtk_offload_support = AH_TRUE; p_cap->hal_wow_arp_offload_support = AH_TRUE; p_cap->hal_wow_ns_offload_support = AH_TRUE; p_cap->hal_wow_4way_hs_wakeup_support = AH_TRUE; p_cap->hal_wow_acer_magic_support = AH_TRUE; p_cap->hal_wow_acer_swka_support = AH_TRUE; } else { p_cap->hal_wow_gtk_offload_support = AH_FALSE; p_cap->hal_wow_arp_offload_support = AH_FALSE; p_cap->hal_wow_ns_offload_support = AH_FALSE; p_cap->hal_wow_4way_hs_wakeup_support = AH_FALSE; p_cap->hal_wow_acer_magic_support = AH_FALSE; p_cap->hal_wow_acer_swka_support = AH_FALSE; } #endif /* ATH_WOW_OFFLOAD */ return AH_TRUE; #undef AR_KEYTABLE_SIZE } #if 0 static HAL_BOOL ar9300_get_chip_power_limits(struct ath_hal *ah, HAL_CHANNEL *chans, u_int32_t nchans) { struct ath_hal_9300 *ahp = AH9300(ah); return ahp->ah_rf_hal.get_chip_power_lim(ah, chans, nchans); } #endif /* XXX FreeBSD */ static HAL_BOOL ar9300_get_chip_power_limits(struct ath_hal *ah, struct ieee80211_channel *chan) { chan->ic_maxpower = AR9300_MAX_RATE_POWER; chan->ic_minpower = 0; return AH_TRUE; } /* * Disable PLL when in L0s as well as receiver clock when in L1. * This power saving option must be enabled through the Serdes. * * Programming the Serdes must go through the same 288 bit serial shift * register as the other analog registers. Hence the 9 writes. * * XXX Clean up the magic numbers. */ void ar9300_config_pci_power_save(struct ath_hal *ah, int restore, int power_off) { struct ath_hal_9300 *ahp = AH9300(ah); int i; if (AH_PRIVATE(ah)->ah_ispcie != AH_TRUE) { return; } /* * Increase L1 Entry Latency. Some WB222 boards don't have * this change in eeprom/OTP. */ if (AR_SREV_JUPITER(ah)) { u_int32_t val = ah->ah_config.ath_hal_war70c; if ((val & 0xff000000) == 0x17000000) { val &= 0x00ffffff; val |= 0x27000000; OS_REG_WRITE(ah, 0x570c, val); } } /* Do not touch SERDES registers */ if (ah->ah_config.ath_hal_pcie_power_save_enable == 2) { return; } /* Nothing to do on restore for 11N */ if (!restore) { /* set bit 19 to allow forcing of pcie core into L1 state */ OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), AR_PCIE_PM_CTRL_ENA); /* * Set PCIE workaround config only if requested, else use the reset * value of this register. */ if (ah->ah_config.ath_hal_pcie_waen) { OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ah->ah_config.ath_hal_pcie_waen); } else { /* Set Bits 17 and 14 in the AR_WA register. */ OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val); } } /* Configure PCIE after Ini init. SERDES values now come from ini file */ if (ah->ah_config.ath_hal_pcie_ser_des_write) { if (power_off) { for (i = 0; i < ahp->ah_ini_pcie_serdes.ia_rows; i++) { OS_REG_WRITE(ah, INI_RA(&ahp->ah_ini_pcie_serdes, i, 0), INI_RA(&ahp->ah_ini_pcie_serdes, i, 1)); } } else { for (i = 0; i < ahp->ah_ini_pcie_serdes_low_power.ia_rows; i++) { OS_REG_WRITE(ah, INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 0), INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 1)); } } } } /* * Recipe from charles to turn off PCIe PHY in PCI mode for power savings */ void ar9300_disable_pcie_phy(struct ath_hal *ah) { /* Osprey does not support PCI mode */ } static inline HAL_STATUS ar9300_init_mac_addr(struct ath_hal *ah) { u_int32_t sum; int i; u_int16_t eeval; struct ath_hal_9300 *ahp = AH9300(ah); u_int32_t EEP_MAC [] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; sum = 0; for (i = 0; i < 3; i++) { eeval = ar9300_eeprom_get(ahp, EEP_MAC[i]); sum += eeval; ahp->ah_macaddr[2*i] = eeval >> 8; ahp->ah_macaddr[2*i + 1] = eeval & 0xff; } if (sum == 0 || sum == 0xffff*3) { HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: mac address read failed: %s\n", __func__, ath_hal_ether_sprintf(ahp->ah_macaddr)); return HAL_EEBADMAC; } return HAL_OK; } /* * Code for the "real" chip i.e. non-emulation. Review and revisit * when actual hardware is at hand. */ static inline HAL_STATUS ar9300_hw_attach(struct ath_hal *ah) { HAL_STATUS ecode; if (!ar9300_chip_test(ah)) { HALDEBUG(ah, HAL_DEBUG_REGIO, "%s: hardware self-test failed\n", __func__); return HAL_ESELFTEST; } ath_hal_printf(ah, "%s: calling ar9300_eeprom_attach\n", __func__); ecode = ar9300_eeprom_attach(ah); ath_hal_printf(ah, "%s: ar9300_eeprom_attach returned %d\n", __func__, ecode); if (ecode != HAL_OK) { return ecode; } if (!ar9300_rf_attach(ah, &ecode)) { HALDEBUG(ah, HAL_DEBUG_RESET, "%s: RF setup failed, status %u\n", __func__, ecode); } if (ecode != HAL_OK) { return ecode; } ar9300_ani_attach(ah); return HAL_OK; } static inline void ar9300_hw_detach(struct ath_hal *ah) { /* XXX EEPROM allocated state */ ar9300_ani_detach(ah); } static int16_t ar9300_get_nf_adjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c) { return 0; } void ar9300_set_immunity(struct ath_hal *ah, HAL_BOOL enable) { struct ath_hal_9300 *ahp = AH9300(ah); u_int32_t m1_thresh_low = enable ? 127 : ahp->ah_immunity_vals[0], m2_thresh_low = enable ? 127 : ahp->ah_immunity_vals[1], m1_thresh = enable ? 127 : ahp->ah_immunity_vals[2], m2_thresh = enable ? 127 : ahp->ah_immunity_vals[3], m2_count_thr = enable ? 31 : ahp->ah_immunity_vals[4], m2_count_thr_low = enable ? 63 : ahp->ah_immunity_vals[5]; if (ahp->ah_immunity_on == enable) { return; } ahp->ah_immunity_on = enable; OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1_thresh_low); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2_thresh_low); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, AR_PHY_SFCORR_M1_THRESH, m1_thresh); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, AR_PHY_SFCORR_M2_THRESH, m2_thresh); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, AR_PHY_SFCORR_M2COUNT_THR, m2_count_thr); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2_count_thr_low); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1_thresh_low); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2_thresh_low); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M1_THRESH, m1_thresh); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M2_THRESH, m2_thresh); if (!enable) { OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); } else { OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); } } /* XXX FreeBSD: I'm not sure how to implement this.. */ #if 0 int ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp, HAL_CAL_QUERY query) { #define AR9300_IS_CHAIN_RX_IQCAL_INVALID(_ah, _reg) \ ((OS_REG_READ((_ah), _reg) & 0x3fff) == 0) #define AR9300_IS_RX_IQCAL_DISABLED(_ah) \ (!(OS_REG_READ((_ah), AR_PHY_RX_IQCAL_CORR_B0) & \ AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE)) /* Avoid comilation warnings. Variables are not used when EMULATION. */ struct ath_hal_9300 *ahp = AH9300(ah); u_int8_t rxchainmask = ahp->ah_rx_chainmask, i; int rx_iqcal_invalid = 0, num_chains = 0; static const u_int32_t offset_array[3] = { AR_PHY_RX_IQCAL_CORR_B0, AR_PHY_RX_IQCAL_CORR_B1, AR_PHY_RX_IQCAL_CORR_B2}; *timerp = ar9300_cals; switch (query) { case HAL_QUERY_CALS: return AR9300_NUM_CAL_TYPES; case HAL_QUERY_RERUN_CALS: for (i = 0; i < AR9300_MAX_CHAINS; i++) { if (rxchainmask & (1 << i)) { num_chains++; } } for (i = 0; i < num_chains; i++) { if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { HALASSERT(num_chains == 0x1); } if (AR9300_IS_CHAIN_RX_IQCAL_INVALID(ah, offset_array[i])) { rx_iqcal_invalid = 1; } } if (AR9300_IS_RX_IQCAL_DISABLED(ah)) { rx_iqcal_invalid = 1; } return rx_iqcal_invalid; default: HALASSERT(0); } return 0; } #endif #if ATH_TRAFFIC_FAST_RECOVER #define PLL3 0x16188 #define PLL3_DO_MEAS_MASK 0x40000000 #define PLL4 0x1618c #define PLL4_MEAS_DONE 0x8 #define SQSUM_DVC_MASK 0x007ffff8 unsigned long ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah) { if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) & ~(PLL3_DO_MEAS_MASK))); OS_DELAY(100); OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) | PLL3_DO_MEAS_MASK)); while ( (OS_REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { OS_DELAY(100); } return (( OS_REG_READ(ah, PLL3) & SQSUM_DVC_MASK ) >> 3); } else { HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: unable to get pll3_sqsum_dvc\n", __func__); return 0; } } #endif #define RX_GAIN_TABLE_LENGTH 128 // this will be called if rfGainCAP is enabled and rfGainCAP setting is changed, // or rxGainTable setting is changed HAL_BOOL ar9300_rf_gain_cap_apply(struct ath_hal *ah, int is_2GHz) { int i, done = 0, i_rx_gain = 32; u_int32_t rf_gain_cap; u_int32_t rx_gain_value, a_Byte, rx_gain_value_caped; static u_int32_t rx_gain_table[RX_GAIN_TABLE_LENGTH * 2][2]; ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; struct ath_hal_9300 *ahp = AH9300(ah); if ( !((eep->base_eep_header.misc_configuration & 0x80) >> 7) ) return AH_FALSE; if (is_2GHz) { rf_gain_cap = (u_int32_t) eep->modal_header_2g.rf_gain_cap; } else { rf_gain_cap = (u_int32_t) eep->modal_header_5g.rf_gain_cap; } if (rf_gain_cap == 0) return AH_FALSE; for (i = 0; i< RX_GAIN_TABLE_LENGTH * 2; i++) { if (AR_SREV_AR9580(ah)) { // BB_rx_ocgain2 i_rx_gain = 128 + 32; switch (ar9300_rx_gain_index_get(ah)) { case 0: rx_gain_table[i][0] = ar9300_common_rx_gain_table_ar9580_1p0[i][0]; rx_gain_table[i][1] = ar9300_common_rx_gain_table_ar9580_1p0[i][1]; break; case 1: rx_gain_table[i][0] = ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][0]; rx_gain_table[i][1] = ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][1]; break; } } else if (AR_SREV_OSPREY_22(ah)) { i_rx_gain = 128 + 32; switch (ar9300_rx_gain_index_get(ah)) { case 0: rx_gain_table[i][0] = ar9300_common_rx_gain_table_osprey_2p2[i][0]; rx_gain_table[i][1] = ar9300_common_rx_gain_table_osprey_2p2[i][1]; break; case 1: rx_gain_table[i][0] = ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][0]; rx_gain_table[i][1] = ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][1]; break; } } else { return AH_FALSE; } } while (1) { rx_gain_value = rx_gain_table[i_rx_gain][1]; rx_gain_value_caped = rx_gain_value; a_Byte = rx_gain_value & (0x000000FF); if (a_Byte>rf_gain_cap) { rx_gain_value_caped = (rx_gain_value_caped & (0xFFFFFF00)) + rf_gain_cap; } a_Byte = rx_gain_value & (0x0000FF00); if ( a_Byte > ( rf_gain_cap << 8 ) ) { rx_gain_value_caped = (rx_gain_value_caped & (0xFFFF00FF)) + (rf_gain_cap<<8); } a_Byte = rx_gain_value & (0x00FF0000); if ( a_Byte > ( rf_gain_cap << 16 ) ) { rx_gain_value_caped = (rx_gain_value_caped & (0xFF00FFFF)) + (rf_gain_cap<<16); } a_Byte = rx_gain_value & (0xFF000000); if ( a_Byte > ( rf_gain_cap << 24 ) ) { rx_gain_value_caped = (rx_gain_value_caped & (0x00FFFFFF)) + (rf_gain_cap<<24); } else { done = 1; } HALDEBUG(ah, HAL_DEBUG_RESET, "%s: rx_gain_address: %x, rx_gain_value: %x rx_gain_value_caped: %x\n", __func__, rx_gain_table[i_rx_gain][0], rx_gain_value, rx_gain_value_caped); if (rx_gain_value_caped != rx_gain_value) { rx_gain_table[i_rx_gain][1] = rx_gain_value_caped; } if (done == 1) break; i_rx_gain ++; } INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, rx_gain_table, ARRAY_LENGTH(rx_gain_table), 2); return AH_TRUE; } void ar9300_rx_gain_table_apply(struct ath_hal *ah) { struct ath_hal_9300 *ahp = AH9300(ah); //struct ath_hal_private *ahpriv = AH_PRIVATE(ah); u_int32_t xlan_gpio_cfg; u_int8_t i; if (AR_SREV_OSPREY(ah) || AR_SREV_AR9580(ah)) { // this will be called if rxGainTable setting is changed if (ar9300_rf_gain_cap_apply(ah, 1)) return; } switch (ar9300_rx_gain_index_get(ah)) { case 2: if (AR_SREV_JUPITER_10(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9300_common_mixed_rx_gain_table_jupiter_1p0, ARRAY_LENGTH(ar9300_common_mixed_rx_gain_table_jupiter_1p0), 2); break; } else if (AR_SREV_JUPITER_20(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9300Common_mixed_rx_gain_table_jupiter_2p0, ARRAY_LENGTH(ar9300Common_mixed_rx_gain_table_jupiter_2p0), 2); break; } case 0: default: if (AR_SREV_HORNET_12(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9331_common_rx_gain_hornet1_2, ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2); } else if (AR_SREV_HORNET_11(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9331_common_rx_gain_hornet1_1, ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2); } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9485_common_wo_xlna_rx_gain_poseidon1_1, ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); /* XXX FreeBSD: this needs to be revisited!! */ xlan_gpio_cfg = ah->ah_config.ath_hal_ext_lna_ctl_gpio; if (xlan_gpio_cfg) { for (i = 0; i < 32; i++) { if (xlan_gpio_cfg & (1 << i)) { /* * XXX FreeBSD: definitely make sure this * results in the correct value being written * to the hardware, or weird crap is very likely * to occur! */ ath_hal_gpioCfgOutput(ah, i, HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED); } } } } else if (AR_SREV_POSEIDON(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9485Common_wo_xlna_rx_gain_poseidon1_0, ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); } else if (AR_SREV_JUPITER_10(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9300_common_rx_gain_table_jupiter_1p0, ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2); } else if (AR_SREV_JUPITER_20(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9300Common_rx_gain_table_jupiter_2p0, ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2); } else if (AR_SREV_AR9580(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9300_common_rx_gain_table_ar9580_1p0, ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2); } else if (AR_SREV_WASP(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9340Common_rx_gain_table_wasp_1p0, ARRAY_LENGTH(ar9340Common_rx_gain_table_wasp_1p0), 2); } else if (AR_SREV_SCORPION(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar955xCommon_rx_gain_table_scorpion_1p0, ARRAY_LENGTH(ar955xCommon_rx_gain_table_scorpion_1p0), 2); INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, ar955xCommon_rx_gain_bounds_scorpion_1p0, ARRAY_LENGTH(ar955xCommon_rx_gain_bounds_scorpion_1p0), 5); } else { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9300_common_rx_gain_table_osprey_2p2, ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2); } break; case 1: if (AR_SREV_HORNET_12(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9331_common_wo_xlna_rx_gain_hornet1_2, ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_2), 2); } else if (AR_SREV_HORNET_11(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9331_common_wo_xlna_rx_gain_hornet1_1, ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_1), 2); } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9485_common_wo_xlna_rx_gain_poseidon1_1, ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); } else if (AR_SREV_POSEIDON(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9485Common_wo_xlna_rx_gain_poseidon1_0, ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); } else if (AR_SREV_JUPITER_10(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0, ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0), 2); } else if (AR_SREV_JUPITER_20(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0, ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0), 2); } else if (AR_SREV_APHRODITE(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0, ARRAY_LENGTH(ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0), 2); } else if (AR_SREV_AR9580(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0, ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0), 2); } else if (AR_SREV_WASP(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9340Common_wo_xlna_rx_gain_table_wasp_1p0, ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2); } else if (AR_SREV_SCORPION(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0, ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2); INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0, ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5); } else { INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, ar9300Common_wo_xlna_rx_gain_table_osprey_2p2, ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_osprey_2p2), 2); } break; } } void ar9300_tx_gain_table_apply(struct ath_hal *ah) { struct ath_hal_9300 *ahp = AH9300(ah); switch (ar9300_tx_gain_index_get(ah)) { case 0: default: if (AR_SREV_HORNET_12(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9331_modes_lowest_ob_db_tx_gain_hornet1_2, ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5); } else if (AR_SREV_HORNET_11(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9331_modes_lowest_ob_db_tx_gain_hornet1_1, ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5); } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1, ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5); } else if (AR_SREV_POSEIDON(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0, ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5); } else if (AR_SREV_AR9580(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0, ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0), 5); } else if (AR_SREV_WASP(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0, ARRAY_LENGTH(ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0), 5); } else if (AR_SREV_SCORPION(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar955xModes_xpa_tx_gain_table_scorpion_1p0, ARRAY_LENGTH(ar955xModes_xpa_tx_gain_table_scorpion_1p0), 9); } else if (AR_SREV_JUPITER_10(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0, ARRAY_LENGTH(ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0), 5); } else if (AR_SREV_JUPITER_20(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0, ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0), 5); } else if (AR_SREV_APHRODITE(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0, ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0), 5); } else { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2, ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2), 5); } break; case 1: if (AR_SREV_HORNET_12(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9331_modes_high_ob_db_tx_gain_hornet1_2, ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_2), 5); } else if (AR_SREV_HORNET_11(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9331_modes_high_ob_db_tx_gain_hornet1_1, ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_1), 5); } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9485_modes_high_ob_db_tx_gain_poseidon1_1, ARRAY_LENGTH(ar9485_modes_high_ob_db_tx_gain_poseidon1_1), 5); } else if (AR_SREV_POSEIDON(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9485Modes_high_ob_db_tx_gain_poseidon1_0, ARRAY_LENGTH(ar9485Modes_high_ob_db_tx_gain_poseidon1_0), 5); } else if (AR_SREV_AR9580(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0, ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0), 5); } else if (AR_SREV_WASP(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0, ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5); } else if (AR_SREV_SCORPION(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar955xModes_no_xpa_tx_gain_table_scorpion_1p0, ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 9); } else if (AR_SREV_JUPITER_10(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0, ARRAY_LENGTH( ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0), 5); } else if (AR_SREV_JUPITER_20(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0, ARRAY_LENGTH( ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0), 5); } else if (AR_SREV_APHRODITE(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0, ARRAY_LENGTH( ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0), 5); } else { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2, ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2), 5); } break; case 2: if (AR_SREV_HORNET_12(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9331_modes_low_ob_db_tx_gain_hornet1_2, ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_2), 5); } else if (AR_SREV_HORNET_11(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9331_modes_low_ob_db_tx_gain_hornet1_1, ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_1), 5); } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9485_modes_low_ob_db_tx_gain_poseidon1_1, ARRAY_LENGTH(ar9485_modes_low_ob_db_tx_gain_poseidon1_1), 5); } else if (AR_SREV_POSEIDON(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9485Modes_low_ob_db_tx_gain_poseidon1_0, ARRAY_LENGTH(ar9485Modes_low_ob_db_tx_gain_poseidon1_0), 5); } else if (AR_SREV_AR9580(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0, ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0), 5); } else if (AR_SREV_WASP(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0, ARRAY_LENGTH(ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0), 5); } else if (AR_SREV_APHRODITE(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0, ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0), 5); } else { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2, ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2), 5); } break; case 3: if (AR_SREV_HORNET_12(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9331_modes_high_power_tx_gain_hornet1_2, ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_2), 5); } else if (AR_SREV_HORNET_11(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9331_modes_high_power_tx_gain_hornet1_1, ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_1), 5); } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9485_modes_high_power_tx_gain_poseidon1_1, ARRAY_LENGTH(ar9485_modes_high_power_tx_gain_poseidon1_1), 5); } else if (AR_SREV_POSEIDON(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9485Modes_high_power_tx_gain_poseidon1_0, ARRAY_LENGTH(ar9485Modes_high_power_tx_gain_poseidon1_0), 5); } else if (AR_SREV_AR9580(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9300Modes_high_power_tx_gain_table_ar9580_1p0, ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_ar9580_1p0), 5); } else if (AR_SREV_WASP(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9340Modes_high_power_tx_gain_table_wasp_1p0, ARRAY_LENGTH(ar9340Modes_high_power_tx_gain_table_wasp_1p0), 5); } else if (AR_SREV_APHRODITE(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar956XModes_high_power_tx_gain_table_aphrodite_1p0, ARRAY_LENGTH(ar956XModes_high_power_tx_gain_table_aphrodite_1p0), 5); } else { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9300Modes_high_power_tx_gain_table_osprey_2p2, ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_osprey_2p2), 5); } break; case 4: if (AR_SREV_WASP(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0, ARRAY_LENGTH(ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0), 5); } else if (AR_SREV_AR9580(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0, ARRAY_LENGTH(ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0), 5); } else { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2, ARRAY_LENGTH(ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2), 5); } break; case 5: /* HW Green TX */ if (AR_SREV_POSEIDON(ah)) { if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9485_modes_green_ob_db_tx_gain_poseidon1_1, sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1) / sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1[0]), 5); } else { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9485_modes_green_ob_db_tx_gain_poseidon1_0, sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0) / sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0[0]), 5); } ahp->ah_hw_green_tx_enable = 1; } else if (AR_SREV_WASP(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9340_modes_ub124_tx_gain_table_wasp_1p0, sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0) / sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0[0]), 5); } else if (AR_SREV_AR9580(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9300_modes_type5_tx_gain_table_ar9580_1p0, ARRAY_LENGTH( ar9300_modes_type5_tx_gain_table_ar9580_1p0), 5); } else if (AR_SREV_OSPREY_22(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9300_modes_number_5_tx_gain_table_osprey_2p2, ARRAY_LENGTH( ar9300_modes_number_5_tx_gain_table_osprey_2p2), 5); } break; case 6: if (AR_SREV_WASP(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0, sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0) / sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0[0]), 5); } /* HW Green TX */ else if (AR_SREV_POSEIDON(ah)) { if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1, sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1) / sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1[0]), 5); } ahp->ah_hw_green_tx_enable = 1; } else if (AR_SREV_AR9580(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9300_modes_type6_tx_gain_table_ar9580_1p0, ARRAY_LENGTH( ar9300_modes_type6_tx_gain_table_ar9580_1p0), 5); } break; case 7: if (AR_SREV_WASP(ah)) { INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, ar9340Modes_cus227_tx_gain_table_wasp_1p0, sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0) / sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0[0]), 5); } break; } } #if ATH_ANT_DIV_COMB void ar9300_ant_div_comb_get_config(struct ath_hal *ah, HAL_ANT_COMB_CONFIG *div_comb_conf) { u_int32_t reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); div_comb_conf->main_lna_conf = MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__READ(reg_val); div_comb_conf->alt_lna_conf = MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__READ(reg_val); div_comb_conf->fast_div_bias = MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__READ(reg_val); if (AR_SREV_HORNET_11(ah)) { div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_1; } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_2; } else { div_comb_conf->antdiv_configgroup = DEFAULT_ANTDIV_CONFIG_GROUP; } /* * XXX TODO: allow the HAL to override the rssithres and fast_div_bias * values (eg CUS198.) */ } void ar9300_ant_div_comb_set_config(struct ath_hal *ah, HAL_ANT_COMB_CONFIG *div_comb_conf) { u_int32_t reg_val; struct ath_hal_9300 *ahp = AH9300(ah); /* DO NOTHING when set to fixed antenna for manufacturing purpose */ if (AR_SREV_POSEIDON(ah) && ( ahp->ah_diversity_control == HAL_ANT_FIXED_A || ahp->ah_diversity_control == HAL_ANT_FIXED_B)) { return; } reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); reg_val &= ~(MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK | MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MASK | MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MASK | MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MASK | MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MASK ); reg_val |= MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__WRITE( div_comb_conf->main_gaintb); reg_val |= MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__WRITE( div_comb_conf->alt_gaintb); reg_val |= MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__WRITE( div_comb_conf->main_lna_conf); reg_val |= MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__WRITE( div_comb_conf->alt_lna_conf); reg_val |= MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__WRITE( div_comb_conf->fast_div_bias); OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, reg_val); } #endif /* ATH_ANT_DIV_COMB */ static void ar9300_init_hostif_offsets(struct ath_hal *ah) { AR_HOSTIF_REG(ah, AR_RC) = AR9300_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL); AR_HOSTIF_REG(ah, AR_WA) = AR9300_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND); AR_HOSTIF_REG(ah, AR_PM_STATE) = AR9300_HOSTIF_OFFSET(HOST_INTF_PM_STATE); AR_HOSTIF_REG(ah, AR_H_INFOL) = AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOL); AR_HOSTIF_REG(ah, AR_H_INFOH) = AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOH); AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) = AR9300_HOSTIF_OFFSET(HOST_INTF_PM_CTRL); AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) = AR9300_HOSTIF_OFFSET(HOST_INTF_TIMEOUT); AR_HOSTIF_REG(ah, AR_EEPROM) = AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_CTRL); AR_HOSTIF_REG(ah, AR_SREV) = AR9300_HOSTIF_OFFSET(HOST_INTF_SREV); AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) = AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) = AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) = AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE); AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) = AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK); AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) = AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK); AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) = AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) = AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) = AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE); AR_HOSTIF_REG(ah, AR_PCIE_SERDES) = AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_RW); AR_HOSTIF_REG(ah, AR_PCIE_SERDES2) = AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LOAD); AR_HOSTIF_REG(ah, AR_GPIO_OUT) = AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT); AR_HOSTIF_REG(ah, AR_GPIO_IN) = AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_IN); AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) = AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE); AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) = AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1); AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) = AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR); AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) = AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE); AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) = AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1); AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) = AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2); AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) = AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1); AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) = AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2); AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) = AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3); AR_HOSTIF_REG(ah, AR_INPUT_STATE) = AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE); AR_HOSTIF_REG(ah, AR_SPARE) = AR9300_HOSTIF_OFFSET(HOST_INTF_SPARE); AR_HOSTIF_REG(ah, AR_PCIE_CORE_RESET_EN) = AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_CORE_RST_EN); AR_HOSTIF_REG(ah, AR_CLKRUN) = AR9300_HOSTIF_OFFSET(HOST_INTF_CLKRUN); AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) = AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS); AR_HOSTIF_REG(ah, AR_OBS) = AR9300_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL); AR_HOSTIF_REG(ah, AR_RFSILENT) = AR9300_HOSTIF_OFFSET(HOST_INTF_RFSILENT); AR_HOSTIF_REG(ah, AR_GPIO_PDPU) = AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_PDPU); AR_HOSTIF_REG(ah, AR_GPIO_DS) = AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_DS); AR_HOSTIF_REG(ah, AR_MISC) = AR9300_HOSTIF_OFFSET(HOST_INTF_MISC); AR_HOSTIF_REG(ah, AR_PCIE_MSI) = AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI); #if 0 /* Offsets are not defined in reg_map structure */ AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_ACTIVE) = AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_ACTIVE); AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_PRIORITY) = AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_PRIORITY); AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_CNTL) = AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TSF_SNAPSHOT_BT_CNTL); #endif AR_HOSTIF_REG(ah, AR_PCIE_PHY_LATENCY_NFTS_ADJ) = AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ); AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) = AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL); AR_HOSTIF_REG(ah, AR_TXAPSYNC) = AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC); AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) = AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR); AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) = AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE); AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) = AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE); AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) = AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK); AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) = AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK); AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) = AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE); AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) = AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE); } static void ar9340_init_hostif_offsets(struct ath_hal *ah) { AR_HOSTIF_REG(ah, AR_RC) = AR9340_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL); AR_HOSTIF_REG(ah, AR_WA) = AR9340_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND); AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) = AR9340_HOSTIF_OFFSET(HOST_INTF_PM_CTRL); AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) = AR9340_HOSTIF_OFFSET(HOST_INTF_TIMEOUT); AR_HOSTIF_REG(ah, AR_SREV) = AR9340_HOSTIF_OFFSET(HOST_INTF_SREV); AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) = AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) = AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) = AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE); AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) = AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK); AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) = AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK); AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) = AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) = AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) = AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE); AR_HOSTIF_REG(ah, AR_GPIO_OUT) = AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT); AR_HOSTIF_REG(ah, AR_GPIO_IN) = AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_IN); AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) = AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE); AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) = AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1); AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) = AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR); AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) = AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE); AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) = AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1); AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) = AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2); AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) = AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1); AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) = AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2); AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) = AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3); AR_HOSTIF_REG(ah, AR_INPUT_STATE) = AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE); AR_HOSTIF_REG(ah, AR_CLKRUN) = AR9340_HOSTIF_OFFSET(HOST_INTF_CLKRUN); AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) = AR9340_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS); AR_HOSTIF_REG(ah, AR_OBS) = AR9340_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL); AR_HOSTIF_REG(ah, AR_RFSILENT) = AR9340_HOSTIF_OFFSET(HOST_INTF_RFSILENT); AR_HOSTIF_REG(ah, AR_MISC) = AR9340_HOSTIF_OFFSET(HOST_INTF_MISC); AR_HOSTIF_REG(ah, AR_PCIE_MSI) = AR9340_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI); AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) = AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL); AR_HOSTIF_REG(ah, AR_TXAPSYNC) = AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC); AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) = AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR); AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) = AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE); AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) = AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE); AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) = AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK); AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) = AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK); AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) = AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE); AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) = AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE); } /* * Host interface register offsets are different for Osprey and Wasp * and hence store the offsets in hal structure */ static int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid) { if (devid == AR9300_DEVID_AR9340) { ar9340_init_hostif_offsets(ah); } else { ar9300_init_hostif_offsets(ah); } return 0; } static const char* ar9300_probe(uint16_t vendorid, uint16_t devid) { if (vendorid != ATHEROS_VENDOR_ID) return AH_NULL; switch (devid) { case AR9300_DEVID_AR9380_PCIE: /* PCIE (Osprey) */ return "Atheros AR938x"; case AR9300_DEVID_AR9340: /* Wasp */ return "Atheros AR934x"; case AR9300_DEVID_AR9485_PCIE: /* Poseidon */ return "Atheros AR9485"; case AR9300_DEVID_AR9580_PCIE: /* Peacock */ return "Atheros AR9580"; case AR9300_DEVID_AR946X_PCIE: /* AR9462, AR9463, AR9482 */ return "Atheros AR946x/AR948x"; case AR9300_DEVID_AR9330: /* Hornet */ return "Atheros AR933x"; case AR9300_DEVID_QCA955X: /* Scorpion */ return "Qualcomm Atheros QCA955x"; case AR9300_DEVID_QCA9565: /* Aphrodite */ return "Qualcomm Atheros AR9565"; case AR9300_DEVID_AR1111_PCIE: return "Atheros AR1111"; default: return AH_NULL; } return AH_NULL; } AH_CHIP(AR9300, ar9300_probe, ar9300_attach); Index: head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300reg.h =================================================================== --- head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300reg.h (revision 291432) +++ head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300reg.h (revision 291433) @@ -1,3119 +1,3128 @@ /* * Copyright (c) 2013 Qualcomm Atheros, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ #ifndef _DEV_ATH_AR9300REG_H #define _DEV_ATH_AR9300REG_H #include "osprey_reg_map.h" #include "wasp_reg_map.h" /****************************************************************************** * MAC Register Map ******************************************************************************/ #define AR_MAC_DMA_OFFSET(_x) offsetof(struct mac_dma_reg, _x) /* * MAC DMA Registers */ /* MAC Control Register - only write values of 1 have effect */ #define AR_CR AR_MAC_DMA_OFFSET(MAC_DMA_CR) #define AR_CR_LP_RXE 0x00000004 // Receive LPQ enable #define AR_CR_HP_RXE 0x00000008 // Receive HPQ enable #define AR_CR_RXD 0x00000020 // Receive disable #define AR_CR_SWI 0x00000040 // One-shot software interrupt #define AR_CR_RXE (AR_CR_LP_RXE|AR_CR_HP_RXE) /* MAC configuration and status register */ #define AR_CFG AR_MAC_DMA_OFFSET(MAC_DMA_CFG) #define AR_CFG_SWTD 0x00000001 // byteswap tx descriptor words #define AR_CFG_SWTB 0x00000002 // byteswap tx data buffer words #define AR_CFG_SWRD 0x00000004 // byteswap rx descriptor words #define AR_CFG_SWRB 0x00000008 // byteswap rx data buffer words #define AR_CFG_SWRG 0x00000010 // byteswap register access data words #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc) #define AR_CFG_PHOK 0x00000100 // PHY OK status #define AR_CFG_CLK_GATE_DIS 0x00000400 // Clock gating disable #define AR_CFG_EEBS 0x00000200 // EEPROM busy #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000 // Mask of PCI core master request queue full threshold #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 // Shift for PCI core master request queue full threshold #define AR_CFG_MISSING_TX_INTR_FIX_ENABLE 0x00080000 // See EV 61133 for details. /* Rx DMA Data Buffer Pointer Threshold - High and Low Priority register */ #define AR_RXBP_THRESH AR_MAC_DMA_OFFSET(MAC_DMA_RXBUFPTR_THRESH) #define AR_RXBP_THRESH_HP 0x0000000f #define AR_RXBP_THRESH_HP_S 0 #define AR_RXBP_THRESH_LP 0x00003f00 #define AR_RXBP_THRESH_LP_S 8 /* Tx DMA Descriptor Pointer Threshold register */ #define AR_TXDP_THRESH AR_MAC_DMA_OFFSET(MAC_DMA_TXDPPTR_THRESH) /* Mac Interrupt rate threshold register */ #define AR_MIRT AR_MAC_DMA_OFFSET(MAC_DMA_MIRT) #define AR_MIRT_VAL 0x0000ffff // in uS #define AR_MIRT_VAL_S 16 /* MAC Global Interrupt enable register */ #define AR_IER AR_MAC_DMA_OFFSET(MAC_DMA_GLOBAL_IER) #define AR_IER_ENABLE 0x00000001 // Global interrupt enable #define AR_IER_DISABLE 0x00000000 // Global interrupt disable /* Mac Tx Interrupt mitigation threshold */ #define AR_TIMT AR_MAC_DMA_OFFSET(MAC_DMA_TIMT) #define AR_TIMT_LAST 0x0000ffff // Last packet threshold #define AR_TIMT_LAST_S 0 #define AR_TIMT_FIRST 0xffff0000 // First packet threshold #define AR_TIMT_FIRST_S 16 /* Mac Rx Interrupt mitigation threshold */ #define AR_RIMT AR_MAC_DMA_OFFSET(MAC_DMA_RIMT) #define AR_RIMT_LAST 0x0000ffff // Last packet threshold #define AR_RIMT_LAST_S 0 #define AR_RIMT_FIRST 0xffff0000 // First packet threshold #define AR_RIMT_FIRST_S 16 #define AR_DMASIZE_4B 0x00000000 // DMA size 4 bytes (TXCFG + RXCFG) #define AR_DMASIZE_8B 0x00000001 // DMA size 8 bytes #define AR_DMASIZE_16B 0x00000002 // DMA size 16 bytes #define AR_DMASIZE_32B 0x00000003 // DMA size 32 bytes #define AR_DMASIZE_64B 0x00000004 // DMA size 64 bytes #define AR_DMASIZE_128B 0x00000005 // DMA size 128 bytes #define AR_DMASIZE_256B 0x00000006 // DMA size 256 bytes #define AR_DMASIZE_512B 0x00000007 // DMA size 512 bytes /* MAC Tx DMA size config register */ #define AR_TXCFG AR_MAC_DMA_OFFSET(MAC_DMA_TXCFG) #define AR_TXCFG_DMASZ_MASK 0x00000007 #define AR_TXCFG_DMASZ_4B 0 #define AR_TXCFG_DMASZ_8B 1 #define AR_TXCFG_DMASZ_16B 2 #define AR_TXCFG_DMASZ_32B 3 #define AR_TXCFG_DMASZ_64B 4 #define AR_TXCFG_DMASZ_128B 5 #define AR_TXCFG_DMASZ_256B 6 #define AR_TXCFG_DMASZ_512B 7 #define AR_FTRIG 0x000003F0 // Mask for Frame trigger level #define AR_FTRIG_S 4 // Shift for Frame trigger level #define AR_FTRIG_IMMED 0x00000000 // bytes in PCU TX FIFO before air #define AR_FTRIG_64B 0x00000010 // default #define AR_FTRIG_128B 0x00000020 #define AR_FTRIG_192B 0x00000030 #define AR_FTRIG_256B 0x00000040 // 5 bits total #define AR_FTRIG_512B 0x00000080 // 5 bits total #define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800 #define AR_TXCFG_RTS_FAIL_EXCESSIVE_RETRIES 0x00080000 #define AR_TXCFG_RTS_FAIL_EXCESSIVE_RETRIES_S 19 /* MAC Rx DMA size config register */ #define AR_RXCFG AR_MAC_DMA_OFFSET(MAC_DMA_RXCFG) #define AR_RXCFG_CHIRP 0x00000008 // Only double chirps #define AR_RXCFG_ZLFDMA 0x00000010 // Enable DMA of zero-length frame #define AR_RXCFG_DMASZ_MASK 0x00000007 #define AR_RXCFG_DMASZ_4B 0 #define AR_RXCFG_DMASZ_8B 1 #define AR_RXCFG_DMASZ_16B 2 #define AR_RXCFG_DMASZ_32B 3 #define AR_RXCFG_DMASZ_64B 4 #define AR_RXCFG_DMASZ_128B 5 #define AR_RXCFG_DMASZ_256B 6 #define AR_RXCFG_DMASZ_512B 7 /* MAC Rx jumbo descriptor last address register */ #define AR_RXJLA AR_MAC_DMA_OFFSET(MAC_DMA_RXJLA) /* MAC MIB control register */ #define AR_MIBC AR_MAC_DMA_OFFSET(MAC_DMA_MIBC) #define AR_MIBC_COW 0x00000001 // counter overflow warning #define AR_MIBC_FMC 0x00000002 // freeze MIB counters #define AR_MIBC_CMC 0x00000004 // clear MIB counters #define AR_MIBC_MCS 0x00000008 // MIB counter strobe increment all /* MAC timeout prescale count */ #define AR_TOPS AR_MAC_DMA_OFFSET(MAC_DMA_TOPS) #define AR_TOPS_MASK 0x0000FFFF // Mask for timeout prescale /* MAC no frame received timeout */ #define AR_RXNPTO AR_MAC_DMA_OFFSET(MAC_DMA_RXNPTO) #define AR_RXNPTO_MASK 0x000003FF // Mask for no frame received timeout /* MAC no frame trasmitted timeout */ #define AR_TXNPTO AR_MAC_DMA_OFFSET(MAC_DMA_TXNPTO) #define AR_TXNPTO_MASK 0x000003FF // Mask for no frame transmitted timeout #define AR_TXNPTO_QCU_MASK 0x000FFC00 // Mask indicating the set of QCUs // for which frame completions will cause // a reset of the no frame transmitted timeout /* MAC receive frame gap timeout */ #define AR_RPGTO AR_MAC_DMA_OFFSET(MAC_DMA_RPGTO) #define AR_RPGTO_MASK 0x000003FF // Mask for receive frame gap timeout /* MAC miscellaneous control/status register */ #define AR_MACMISC AR_MAC_DMA_OFFSET(MAC_DMA_MACMISC) #define AR_MACMISC_PCI_EXT_FORCE 0x00000010 //force msb to 10 to ahb #define AR_MACMISC_DMA_OBS 0x000001E0 // Mask for DMA observation bus mux select #define AR_MACMISC_DMA_OBS_S 5 // Shift for DMA observation bus mux select #define AR_MACMISC_DMA_OBS_LINE_0 0 // Observation DMA line 0 #define AR_MACMISC_DMA_OBS_LINE_1 1 // Observation DMA line 1 #define AR_MACMISC_DMA_OBS_LINE_2 2 // Observation DMA line 2 #define AR_MACMISC_DMA_OBS_LINE_3 3 // Observation DMA line 3 #define AR_MACMISC_DMA_OBS_LINE_4 4 // Observation DMA line 4 #define AR_MACMISC_DMA_OBS_LINE_5 5 // Observation DMA line 5 #define AR_MACMISC_DMA_OBS_LINE_6 6 // Observation DMA line 6 #define AR_MACMISC_DMA_OBS_LINE_7 7 // Observation DMA line 7 #define AR_MACMISC_DMA_OBS_LINE_8 8 // Observation DMA line 8 #define AR_MACMISC_MISC_OBS 0x00000E00 // Mask for MISC observation bus mux select #define AR_MACMISC_MISC_OBS_S 9 // Shift for MISC observation bus mux select #define AR_MACMISC_MISC_OBS_BUS_LSB 0x00007000 // Mask for MAC observation bus mux select (lsb) #define AR_MACMISC_MISC_OBS_BUS_LSB_S 12 // Shift for MAC observation bus mux select (lsb) #define AR_MACMISC_MISC_OBS_BUS_MSB 0x00038000 // Mask for MAC observation bus mux select (msb) #define AR_MACMISC_MISC_OBS_BUS_MSB_S 15 // Shift for MAC observation bus mux select (msb) #define AR_MACMISC_MISC_OBS_BUS_1 1 // MAC observation bus mux select /* MAC Interrupt Config register */ #define AR_INTCFG AR_MAC_DMA_OFFSET(MAC_DMA_INTER) #define AR_INTCFG_REQ 0x00000001 // Interrupt request flag // Indicates whether the DMA engine should generate // an interrupt upon completion of the frame #define AR_INTCFG_MSI_RXOK 0x00000000 // Rx interrupt for MSI logic is RXOK #define AR_INTCFG_MSI_RXINTM 0x00000004 // Rx interrupt for MSI logic is RXINTM #define AR_INTCFG_MSI_RXMINTR 0x00000006 // Rx interrupt for MSI logic is RXMINTR #define AR_INTCFG_MSI_TXOK 0x00000000 // Rx interrupt for MSI logic is TXOK #define AR_INTCFG_MSI_TXINTM 0x00000010 // Rx interrupt for MSI logic is TXINTM #define AR_INTCFG_MSI_TXMINTR 0x00000018 // Rx interrupt for MSI logic is TXMINTR /* MAC DMA Data Buffer length, in bytes */ #define AR_DATABUF AR_MAC_DMA_OFFSET(MAC_DMA_DATABUF) #define AR_DATABUF_MASK 0x00000FFF /* MAC global transmit timeout */ #define AR_GTXTO AR_MAC_DMA_OFFSET(MAC_DMA_GTT) #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) #define AR_GTXTO_TIMEOUT_LIMIT_S 16 // Shift for timeout limit /* MAC global transmit timeout mode */ #define AR_GTTM AR_MAC_DMA_OFFSET(MAC_DMA_GTTM) #define AR_GTTM_USEC 0x00000001 // usec strobe #define AR_GTTM_IGNORE_IDLE 0x00000002 // ignore channel idle #define AR_GTTM_RESET_IDLE 0x00000004 // reset counter on channel idle low #define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe /* MAC carrier sense timeout */ #define AR_CST AR_MAC_DMA_OFFSET(MAC_DMA_CST) #define AR_CST_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) #define AR_CST_TIMEOUT_LIMIT_S 16 // Shift for timeout limit /* MAC Indicates the size of High and Low priority rx_dp FIFOs */ #define AR_RXDP_SIZE AR_MAC_DMA_OFFSET(MAC_DMA_RXDP_SIZE) #define AR_RXDP_LP_SZ_MASK 0x0000007f #define AR_RXDP_LP_SZ_S 0 #define AR_RXDP_HP_SZ_MASK 0x00001f00 #define AR_RXDP_HP_SZ_S 8 /* MAC Rx High Priority Queue RXDP Pointer (lower 32 bits) */ #define AR_HP_RXDP AR_MAC_DMA_OFFSET(MAC_DMA_RX_QUEUE_HP_RXDP) /* MAC Rx Low Priority Queue RXDP Pointer (lower 32 bits) */ #define AR_LP_RXDP AR_MAC_DMA_OFFSET(MAC_DMA_RX_QUEUE_LP_RXDP) /* Primary Interrupt Status Register */ #define AR_ISR AR_MAC_DMA_OFFSET(MAC_DMA_ISR_P) #define AR_ISR_HP_RXOK 0x00000001 // At least one frame rx on high-priority queue sans errors #define AR_ISR_LP_RXOK 0x00000002 // At least one frame rx on low-priority queue sans errors #define AR_ISR_RXERR 0x00000004 // Receive error interrupt #define AR_ISR_RXNOPKT 0x00000008 // No frame received within timeout clock #define AR_ISR_RXEOL 0x00000010 // Received descriptor empty interrupt #define AR_ISR_RXORN 0x00000020 // Receive FIFO overrun interrupt #define AR_ISR_TXOK 0x00000040 // Transmit okay interrupt #define AR_ISR_TXERR 0x00000100 // Transmit error interrupt #define AR_ISR_TXNOPKT 0x00000200 // No frame transmitted interrupt #define AR_ISR_TXEOL 0x00000400 // Transmit descriptor empty interrupt #define AR_ISR_TXURN 0x00000800 // Transmit FIFO underrun interrupt #define AR_ISR_MIB 0x00001000 // MIB interrupt - see MIBC #define AR_ISR_SWI 0x00002000 // Software interrupt #define AR_ISR_RXPHY 0x00004000 // PHY receive error interrupt #define AR_ISR_RXKCM 0x00008000 // Key-cache miss interrupt #define AR_ISR_SWBA 0x00010000 // Software beacon alert interrupt #define AR_ISR_BRSSI 0x00020000 // Beacon threshold interrupt #define AR_ISR_BMISS 0x00040000 // Beacon missed interrupt #define AR_ISR_TXMINTR 0x00080000 // Maximum interrupt transmit rate #define AR_ISR_BNR 0x00100000 // Beacon not ready interrupt #define AR_ISR_RXCHIRP 0x00200000 // Phy received a 'chirp' #define AR_ISR_HCFPOLL 0x00400000 // Received directed HCF poll #define AR_ISR_BCNMISC 0x00800000 // CST, GTT, TIM, CABEND, DTIMSYNC, BCNTO, CABTO, // TSFOOR, DTIM, and TBTT_TIME bits bits from ISR_S2 #define AR_ISR_TIM 0x00800000 // TIM interrupt #define AR_ISR_RXMINTR 0x01000000 // Maximum interrupt receive rate #define AR_ISR_QCBROVF 0x02000000 // QCU CBR overflow interrupt #define AR_ISR_QCBRURN 0x04000000 // QCU CBR underrun interrupt #define AR_ISR_QTRIG 0x08000000 // QCU scheduling trigger interrupt #define AR_ISR_GENTMR 0x10000000 // OR of generic timer bits in ISR 5 #define AR_ISR_HCFTO 0x20000000 // HCF poll timeout #define AR_ISR_TXINTM 0x40000000 // Tx interrupt after mitigation #define AR_ISR_RXINTM 0x80000000 // Rx interrupt after mitigation /* MAC Secondary interrupt status register 0 */ #define AR_ISR_S0 AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S0) #define AR_ISR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9) #define AR_ISR_S0_QCU_TXOK_S 0 // Shift for TXOK (QCU 0-9) /* MAC Secondary interrupt status register 1 */ #define AR_ISR_S1 AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S1) #define AR_ISR_S1_QCU_TXERR 0x000003FF // Mask for TXERR (QCU 0-9) #define AR_ISR_S1_QCU_TXERR_S 0 // Shift for TXERR (QCU 0-9) #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 // Mask for TXEOL (QCU 0-9) #define AR_ISR_S1_QCU_TXEOL_S 16 // Shift for TXEOL (QCU 0-9) /* MAC Secondary interrupt status register 2 */ #define AR_ISR_S2 AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S2) #define AR_ISR_S2_QCU_TXURN 0x000003FF // Mask for TXURN (QCU 0-9) #define AR_ISR_S2_BBPANIC 0x00010000 // Panic watchdog IRQ from BB #define AR_ISR_S2_CST 0x00400000 // Carrier sense timeout #define AR_ISR_S2_GTT 0x00800000 // Global transmit timeout #define AR_ISR_S2_TIM 0x01000000 // TIM #define AR_ISR_S2_CABEND 0x02000000 // CABEND #define AR_ISR_S2_DTIMSYNC 0x04000000 // DTIMSYNC #define AR_ISR_S2_BCNTO 0x08000000 // BCNTO #define AR_ISR_S2_CABTO 0x10000000 // CABTO #define AR_ISR_S2_DTIM 0x20000000 // DTIM #define AR_ISR_S2_TSFOOR 0x40000000 // Rx TSF out of range #define AR_ISR_S2_TBTT_TIME 0x80000000 // TBTT-referenced timer /* MAC Secondary interrupt status register 3 */ #define AR_ISR_S3 AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S3) #define AR_ISR_S3_QCU_QCBROVF 0x000003FF // Mask for QCBROVF (QCU 0-9) #define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 // Mask for QCBRURN (QCU 0-9) /* MAC Secondary interrupt status register 4 */ #define AR_ISR_S4 AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S4) #define AR_ISR_S4_QCU_QTRIG 0x000003FF // Mask for QTRIG (QCU 0-9) #define AR_ISR_S4_RESV0 0xFFFFFC00 // Reserved /* MAC Secondary interrupt status register 5 */ #define AR_ISR_S5 AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S5) #define AR_ISR_S5_TIMER_TRIG 0x000000FF // Mask for timer trigger (0-7) #define AR_ISR_S5_TIMER_THRESH 0x0007FE00 // Mask for timer threshold(0-7) #define AR_ISR_S5_TIM_TIMER 0x00000010 // TIM Timer ISR #define AR_ISR_S5_DTIM_TIMER 0x00000020 // DTIM Timer ISR #define AR_ISR_S5_GENTIMER_TRIG 0x0000FF80 // ISR for generic timer trigger 7 #define AR_ISR_S5_GENTIMER_TRIG_S 0 #define AR_ISR_S5_GENTIMER_THRESH 0xFF800000 // ISR for generic timer threshold 7 #define AR_ISR_S5_GENTIMER_THRESH_S 16 /* Primary Interrupt Mask Register */ #define AR_IMR AR_MAC_DMA_OFFSET(MAC_DMA_IMR_P) #define AR_IMR_RXOK_HP 0x00000001 // Receive high-priority interrupt enable mask #define AR_IMR_RXOK_LP 0x00000002 // Receive low-priority interrupt enable mask #define AR_IMR_RXERR 0x00000004 // Receive error interrupt #define AR_IMR_RXNOPKT 0x00000008 // No frame received within timeout clock #define AR_IMR_RXEOL 0x00000010 // Received descriptor empty interrupt #define AR_IMR_RXORN 0x00000020 // Receive FIFO overrun interrupt #define AR_IMR_TXOK 0x00000040 // Transmit okay interrupt #define AR_IMR_TXERR 0x00000100 // Transmit error interrupt #define AR_IMR_TXNOPKT 0x00000200 // No frame transmitted interrupt #define AR_IMR_TXEOL 0x00000400 // Transmit descriptor empty interrupt #define AR_IMR_TXURN 0x00000800 // Transmit FIFO underrun interrupt #define AR_IMR_MIB 0x00001000 // MIB interrupt - see MIBC #define AR_IMR_SWI 0x00002000 // Software interrupt #define AR_IMR_RXPHY 0x00004000 // PHY receive error interrupt #define AR_IMR_RXKCM 0x00008000 // Key-cache miss interrupt #define AR_IMR_SWBA 0x00010000 // Software beacon alert interrupt #define AR_IMR_BRSSI 0x00020000 // Beacon threshold interrupt #define AR_IMR_BMISS 0x00040000 // Beacon missed interrupt #define AR_IMR_TXMINTR 0x00080000 // Maximum interrupt transmit rate #define AR_IMR_BNR 0x00100000 // BNR interrupt #define AR_IMR_RXCHIRP 0x00200000 // RXCHIRP interrupt #define AR_IMR_BCNMISC 0x00800000 // Venice: BCNMISC #define AR_IMR_TIM 0x00800000 // TIM interrupt #define AR_IMR_RXMINTR 0x01000000 // Maximum interrupt receive rate #define AR_IMR_QCBROVF 0x02000000 // QCU CBR overflow interrupt #define AR_IMR_QCBRURN 0x04000000 // QCU CBR underrun interrupt #define AR_IMR_QTRIG 0x08000000 // QCU scheduling trigger interrupt #define AR_IMR_GENTMR 0x10000000 // Generic timer interrupt #define AR_IMR_TXINTM 0x40000000 // Tx interrupt after mitigation #define AR_IMR_RXINTM 0x80000000 // Rx interrupt after mitigation /* MAC Secondary interrupt mask register 0 */ #define AR_IMR_S0 AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S0) #define AR_IMR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9) #define AR_IMR_S0_QCU_TXOK_S 0 // Shift for TXOK (QCU 0-9) /* MAC Secondary interrupt mask register 1 */ #define AR_IMR_S1 AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S1) #define AR_IMR_S1_QCU_TXERR 0x000003FF // Mask for TXERR (QCU 0-9) #define AR_IMR_S1_QCU_TXERR_S 0 // Shift for TXERR (QCU 0-9) #define AR_IMR_S1_QCU_TXEOL 0x03FF0000 // Mask for TXEOL (QCU 0-9) #define AR_IMR_S1_QCU_TXEOL_S 16 // Shift for TXEOL (QCU 0-9) /* MAC Secondary interrupt mask register 2 */ #define AR_IMR_S2 AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S2) #define AR_IMR_S2_QCU_TXURN 0x000003FF // Mask for TXURN (QCU 0-9) #define AR_IMR_S2_QCU_TXURN_S 0 // Shift for TXURN (QCU 0-9) #define AR_IMR_S2_BBPANIC 0x00010000 // Panic watchdog IRQ from BB #define AR_IMR_S2_CST 0x00400000 // Carrier sense timeout #define AR_IMR_S2_GTT 0x00800000 // Global transmit timeout #define AR_IMR_S2_TIM 0x01000000 // TIM #define AR_IMR_S2_CABEND 0x02000000 // CABEND #define AR_IMR_S2_DTIMSYNC 0x04000000 // DTIMSYNC #define AR_IMR_S2_BCNTO 0x08000000 // BCNTO #define AR_IMR_S2_CABTO 0x10000000 // CABTO #define AR_IMR_S2_DTIM 0x20000000 // DTIM #define AR_IMR_S2_TSFOOR 0x40000000 // TSF out of range /* MAC Secondary interrupt mask register 3 */ #define AR_IMR_S3 AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S3) #define AR_IMR_S3_QCU_QCBROVF 0x000003FF // Mask for QCBROVF (QCU 0-9) #define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 // Mask for QCBRURN (QCU 0-9) #define AR_IMR_S3_QCU_QCBRURN_S 16 // Shift for QCBRURN (QCU 0-9) /* MAC Secondary interrupt mask register 4 */ #define AR_IMR_S4 AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S4) #define AR_IMR_S4_QCU_QTRIG 0x000003FF // Mask for QTRIG (QCU 0-9) #define AR_IMR_S4_RESV0 0xFFFFFC00 // Reserved /* MAC Secondary interrupt mask register 5 */ #define AR_IMR_S5 AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S5) #define AR_IMR_S5_TIMER_TRIG 0x000000FF // Mask for timer trigger (0-7) #define AR_IMR_S5_TIMER_THRESH 0x0000FF00 // Mask for timer threshold(0-7) #define AR_IMR_S5_TIM_TIMER 0x00000010 // TIM Timer Mask #define AR_IMR_S5_DTIM_TIMER 0x00000020 // DTIM Timer Mask #define AR_IMR_S5_GENTIMER7 0x00000080 // Mask for timer 7 trigger #define AR_IMR_S5_GENTIMER_TRIG 0x0000FF80 // Mask for generic timer trigger 7-15 #define AR_IMR_S5_GENTIMER_TRIG_S 0 #define AR_IMR_S5_GENTIMER_THRESH 0xFF800000 // Mask for generic timer threshold 7-15 #define AR_IMR_S5_GENTIMER_THRESH_S 16 /* Interrupt status registers (read-and-clear access secondary shadow copies) */ /* MAC Primary interrupt status register read-and-clear access */ #define AR_ISR_RAC AR_MAC_DMA_OFFSET(MAC_DMA_ISR_P_RAC) /* MAC Secondary interrupt status register 0 - shadow copy */ #define AR_ISR_S0_S AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S0_S) #define AR_ISR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9) #define AR_ISR_S0_QCU_TXOK_S 0 // Shift for TXOK (QCU 0-9) /* MAC Secondary interrupt status register 1 - shadow copy */ #define AR_ISR_S1_S AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S1_S) #define AR_ISR_S1_QCU_TXERR 0x000003FF // Mask for TXERR (QCU 0-9) #define AR_ISR_S1_QCU_TXERR_S 0 // Shift for TXERR (QCU 0-9) #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 // Mask for TXEOL (QCU 0-9) #define AR_ISR_S1_QCU_TXEOL_S 16 // Shift for TXEOL (QCU 0-9) /* MAC Secondary interrupt status register 2 - shadow copy */ #define AR_ISR_S2_S AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S2_S) /* MAC Secondary interrupt status register 3 - shadow copy */ #define AR_ISR_S3_S AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S3_S) /* MAC Secondary interrupt status register 4 - shadow copy */ #define AR_ISR_S4_S AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S4_S) /* MAC Secondary interrupt status register 5 - shadow copy */ #define AR_ISR_S5_S AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S5_S) /* MAC DMA Debug Registers */ #define AR_DMADBG_0 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_0) #define AR_DMADBG_1 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_1) #define AR_DMADBG_2 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_2) #define AR_DMADBG_3 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_3) #define AR_DMADBG_4 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_4) #define AR_DMADBG_5 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_5) #define AR_DMADBG_6 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_6) #define AR_DMADBG_7 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_7) #define AR_DMATXDP_QCU_7_0 AR_MAC_DMA_OFFSET(MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0) #define AR_DMATXDP_QCU_9_8 AR_MAC_DMA_OFFSET(MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8) #define AR_DMADBG_RX_STATE 0x00000F00 // Mask for Rx DMA State machine /* * MAC QCU Registers */ #define AR_MAC_QCU_OFFSET(_x) offsetof(struct mac_qcu_reg, _x) #define AR_NUM_QCU 10 // Only use QCU 0-9 for forward QCU compatibility #define AR_QCU_0 0x0001 #define AR_QCU_1 0x0002 #define AR_QCU_2 0x0004 #define AR_QCU_3 0x0008 #define AR_QCU_4 0x0010 #define AR_QCU_5 0x0020 #define AR_QCU_6 0x0040 #define AR_QCU_7 0x0080 #define AR_QCU_8 0x0100 #define AR_QCU_9 0x0200 /* MAC Transmit Queue descriptor pointer */ #define AR_Q0_TXDP AR_MAC_QCU_OFFSET(MAC_QCU_TXDP) #define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2)) /* MAC Transmit Status Ring Start Address */ #define AR_Q_STATUS_RING_START AR_MAC_QCU_OFFSET(MAC_QCU_STATUS_RING_START) /* MAC Transmit Status Ring End Address */ #define AR_Q_STATUS_RING_END AR_MAC_QCU_OFFSET(MAC_QCU_STATUS_RING_END) /* Current Address in the Transmit Status Ring pointed to by the MAC */ #define AR_Q_STATUS_RING_CURRENT AR_MAC_QCU_OFFSET(MAC_QCU_STATUS_RING_CURRENT) /* MAC Transmit Queue enable */ #define AR_Q_TXE AR_MAC_QCU_OFFSET(MAC_QCU_TXE) #define AR_Q_TXE_M 0x000003FF // Mask for TXE (QCU 0-9) /* MAC Transmit Queue disable */ #define AR_Q_TXD AR_MAC_QCU_OFFSET(MAC_QCU_TXD) #define AR_Q_TXD_M 0x000003FF // Mask for TXD (QCU 0-9) /* MAC CBR configuration */ #define AR_Q0_CBRCFG AR_MAC_QCU_OFFSET(MAC_QCU_CBR) #define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2)) #define AR_Q_CBRCFG_INTERVAL 0x00FFFFFF // Mask for CBR interval (us) #define AR_Q_CBRCFG_INTERVAL_S 0 // Shift for CBR interval (us) #define AR_Q_CBRCFG_OVF_THRESH 0xFF000000 // Mask for CBR overflow threshold #define AR_Q_CBRCFG_OVF_THRESH_S 24 // Shift for CBR overflow threshold /* MAC ready_time configuration */ #define AR_Q0_RDYTIMECFG AR_MAC_QCU_OFFSET(MAC_QCU_RDYTIME) #define AR_QRDYTIMECFG(_i) (AR_Q0_RDYTIMECFG + ((_i)<<2)) #define AR_Q_RDYTIMECFG_DURATION 0x00FFFFFF // Mask for ready_time duration (us) #define AR_Q_RDYTIMECFG_DURATION_S 0 // Shift for ready_time duration (us) #define AR_Q_RDYTIMECFG_EN 0x01000000 // ready_time enable /* MAC OneShotArm set control */ #define AR_Q_ONESHOTARM_SC AR_MAC_QCU_OFFSET(MAC_QCU_ONESHOT_ARM_SC) #define AR_Q_ONESHOTARM_SC_M 0x000003FF // Mask for #define AR_Q_ONESHOTARM_SC (QCU 0-9) #define AR_Q_ONESHOTARM_SC_RESV0 0xFFFFFC00 // Reserved /* MAC OneShotArm clear control */ #define AR_Q_ONESHOTARM_CC AR_MAC_QCU_OFFSET(MAC_QCU_ONESHOT_ARM_CC) #define AR_Q_ONESHOTARM_CC_M 0x000003FF // Mask for #define AR_Q_ONESHOTARM_CC (QCU 0-9) #define AR_Q_ONESHOTARM_CC_RESV0 0xFFFFFC00 // Reserved /* MAC Miscellaneous QCU settings */ #define AR_Q0_MISC AR_MAC_QCU_OFFSET(MAC_QCU_MISC) #define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2)) #define AR_Q_MISC_FSP 0x0000000F // Mask for Frame Scheduling Policy #define AR_Q_MISC_FSP_ASAP 0 // ASAP #define AR_Q_MISC_FSP_CBR 1 // CBR #define AR_Q_MISC_FSP_DBA_GATED 2 // DMA Beacon Alert gated #define AR_Q_MISC_FSP_TIM_GATED 3 // TIM gated #define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 // Beacon-sent-gated #define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5 // Beacon-received-gated #define AR_Q_MISC_ONE_SHOT_EN 0x00000010 // OneShot enable #define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 // Disable CBR expired counter incr (empty q) #define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 // Disable CBR expired counter incr (empty beacon q) #define AR_Q_MISC_BEACON_USE 0x00000080 // Beacon use indication #define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100 // CBR expired counter limit enable #define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 // Enable TXE cleared on ready_time expired or VEOL #define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 // Reset CBR expired counter #define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 // DCU frame early termination request control #define AR_Q_MISC_RESV0 0xFFFFF000 // Reserved /* MAC Miscellaneous QCU status */ #define AR_Q0_STS AR_MAC_QCU_OFFSET(MAC_QCU_CNT) #define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<2)) #define AR_Q_STS_PEND_FR_CNT 0x00000003 // Mask for Pending Frame Count #define AR_Q_STS_RESV0 0x000000FC // Reserved #define AR_Q_STS_CBR_EXP_CNT 0x0000FF00 // Mask for CBR expired counter #define AR_Q_STS_RESV1 0xFFFF0000 // Reserved /* MAC ReadyTimeShutdown status */ #define AR_Q_RDYTIMESHDN AR_MAC_QCU_OFFSET(MAC_QCU_RDYTIME_SHDN) #define AR_Q_RDYTIMESHDN_M 0x000003FF // Mask for ReadyTimeShutdown status (QCU 0-9) /* MAC Descriptor CRC check */ #define AR_Q_DESC_CRCCHK AR_MAC_QCU_OFFSET(MAC_QCU_DESC_CRC_CHK) #define AR_Q_DESC_CRCCHK_EN 1 // Enable CRC check on the descriptor fetched from HOST #define AR_MAC_QCU_EOL AR_MAC_QCU_OFFSET(MAC_QCU_EOL) #define AR_MAC_QCU_EOL_DUR_CAL_EN 0x000003FF // Adjusts EOL for frame duration (QCU 0-9) #define AR_MAC_QCU_EOL_DUR_CAL_EN_S 0 /* * MAC DCU Registers */ #define AR_MAC_DCU_OFFSET(_x) offsetof(struct mac_dcu_reg, _x) #define AR_NUM_DCU 10 // Only use 10 DCU's for forward QCU/DCU compatibility #define AR_DCU_0 0x0001 #define AR_DCU_1 0x0002 #define AR_DCU_2 0x0004 #define AR_DCU_3 0x0008 #define AR_DCU_4 0x0010 #define AR_DCU_5 0x0020 #define AR_DCU_6 0x0040 #define AR_DCU_7 0x0080 #define AR_DCU_8 0x0100 #define AR_DCU_9 0x0200 /* MAC QCU Mask */ #define AR_D0_QCUMASK AR_MAC_DCU_OFFSET(MAC_DCU_QCUMASK) #define AR_DQCUMASK(_i) (AR_D0_QCUMASK + ((_i)<<2)) #define AR_D_QCUMASK 0x000003FF // Mask for QCU Mask (QCU 0-9) #define AR_D_QCUMASK_RESV0 0xFFFFFC00 // Reserved /* DCU transmit filter cmd (w/only) */ #define AR_D_TXBLK_CMD AR_MAC_DCU_OFFSET(MAC_DCU_TXFILTER_DCU0_31_0) #define AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i)) // DCU transmit filter data /* MAC DCU-global IFS settings: SIFS duration */ #define AR_D_GBL_IFS_SIFS AR_MAC_DCU_OFFSET(MAC_DCU_GBL_IFS_SIFS) #define AR_D_GBL_IFS_SIFS_M 0x0000FFFF // Mask for SIFS duration (core clocks) #define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF // Reserved /* MAC DCU-global IFS settings: slot duration */ #define AR_D_GBL_IFS_SLOT AR_MAC_DCU_OFFSET(MAC_DCU_GBL_IFS_SLOT) #define AR_D_GBL_IFS_SLOT_M 0x0000FFFF // Mask for Slot duration (core clocks) #define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000 // Reserved /* MAC Retry limits */ #define AR_D0_RETRY_LIMIT AR_MAC_DCU_OFFSET(MAC_DCU_RETRY_LIMIT) #define AR_DRETRY_LIMIT(_i) (AR_D0_RETRY_LIMIT + ((_i)<<2)) #define AR_D_RETRY_LIMIT_FR_SH 0x0000000F // Mask for frame short retry limit #define AR_D_RETRY_LIMIT_FR_SH_S 0 // Shift for frame short retry limit #define AR_D_RETRY_LIMIT_STA_SH 0x00003F00 // Mask for station short retry limit #define AR_D_RETRY_LIMIT_STA_SH_S 8 // Shift for station short retry limit #define AR_D_RETRY_LIMIT_STA_LG 0x000FC000 // Mask for station short retry limit #define AR_D_RETRY_LIMIT_STA_LG_S 14 // Shift for station short retry limit #define AR_D_RETRY_LIMIT_RESV0 0xFFF00000 // Reserved /* MAC DCU-global IFS settings: EIFS duration */ #define AR_D_GBL_IFS_EIFS AR_MAC_DCU_OFFSET(MAC_DCU_GBL_IFS_EIFS) #define AR_D_GBL_IFS_EIFS_M 0x0000FFFF // Mask for Slot duration (core clocks) #define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000 // Reserved /* MAC ChannelTime settings */ #define AR_D0_CHNTIME AR_MAC_DCU_OFFSET(MAC_DCU_CHANNEL_TIME) #define AR_DCHNTIME(_i) (AR_D0_CHNTIME + ((_i)<<2)) #define AR_D_CHNTIME_DUR 0x000FFFFF // Mask for ChannelTime duration (us) #define AR_D_CHNTIME_DUR_S 0 // Shift for ChannelTime duration (us) #define AR_D_CHNTIME_EN 0x00100000 // ChannelTime enable #define AR_D_CHNTIME_RESV0 0xFFE00000 // Reserved /* MAC DCU-global IFS settings: Miscellaneous */ #define AR_D_GBL_IFS_MISC AR_MAC_DCU_OFFSET(MAC_DCU_GBL_IFS_MISC) #define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 // Mask forLFSR slice select #define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 // Turbo mode indication #define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 // Mask for DCU arbiter delay #define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000 // Random LSFR slice disable #define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000 // Slot transmission window length mask #define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000 // Force transmission on slot boundaries #define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000 // Ignore backoff /* MAC Miscellaneous DCU-specific settings */ #define AR_D0_MISC AR_MAC_DCU_OFFSET(MAC_DCU_MISC) #define AR_DMISC(_i) (AR_D0_MISC + ((_i)<<2)) #define AR_D_MISC_BKOFF_THRESH 0x0000003F // Mask for Backoff threshold setting #define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040 // End of tx series station RTS/data failure count reset policy #define AR_D_MISC_CW_RESET_EN 0x00000080 // End of tx series CW reset enable #define AR_D_MISC_FRAG_WAIT_EN 0x00000100 // Fragment Starvation Policy #define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 // Backoff during a frag burst #define AR_D_MISC_CW_BKOFF_EN 0x00001000 // Use binary exponential CW backoff #define AR_D_MISC_VIR_COL_HANDLING 0x0000C000 // Mask for Virtual collision handling policy #define AR_D_MISC_VIR_COL_HANDLING_S 14 // Shift for Virtual collision handling policy #define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0 // Normal #define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1 // Ignore #define AR_D_MISC_BEACON_USE 0x00010000 // Beacon use indication #define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000 // Mask for DCU arbiter lockout control #define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17 // Shift for DCU arbiter lockout control #define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 // No lockout #define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 // Intra-frame #define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 // Global #define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 // DCU arbiter lockout ignore control #define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 // Sequence number increment disable #define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 // Post-frame backoff disable #define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000 // Virtual coll. handling policy #define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000 // Initiate Retry procedure on Blown IFS #define AR_D_MISC_RESV0 0xFF000000 // Reserved /* MAC Frame sequence number control/status */ #define AR_D_SEQNUM AR_MAC_DCU_OFFSET(MAC_DCU_SEQ) /* MAC DCU transmit pause control/status */ #define AR_D_TXPSE AR_MAC_DCU_OFFSET(MAC_DCU_PAUSE) #define AR_D_TXPSE_CTRL 0x000003FF // Mask of DCUs to pause (DCUs 0-9) #define AR_D_TXPSE_RESV0 0x0000FC00 // Reserved #define AR_D_TXPSE_STATUS 0x00010000 // Transmit pause status #define AR_D_TXPSE_RESV1 0xFFFE0000 // Reserved /* MAC DCU WOW Keep-Alive Config register */ #define AR_D_WOW_KACFG AR_MAC_DCU_OFFSET(MAC_DCU_WOW_KACFG) /* MAC DCU transmission slot mask */ #define AR_D_TXSLOTMASK AR_MAC_DCU_OFFSET(MAC_DCU_TXSLOT) #define AR_D_TXSLOTMASK_NUM 0x0000000F // slot numbers /* MAC DCU-specific IFS settings */ #define AR_D0_LCL_IFS AR_MAC_DCU_OFFSET(MAC_DCU_LCL_IFS) #define AR_DLCL_IFS(_i) (AR_D0_LCL_IFS + ((_i)<<2)) #define AR_D9_LCL_IFS AR_DLCL_IFS(9) #define AR_D_LCL_IFS_CWMIN 0x000003FF // Mask for CW_MIN #define AR_D_LCL_IFS_CWMIN_S 0 // Shift for CW_MIN #define AR_D_LCL_IFS_CWMAX 0x000FFC00 // Mask for CW_MAX #define AR_D_LCL_IFS_CWMAX_S 10 // Shift for CW_MAX #define AR_D_LCL_IFS_AIFS 0x0FF00000 // Mask for AIFS #define AR_D_LCL_IFS_AIFS_S 20 // Shift for AIFS /* * Note: even though this field is 8 bits wide the * maximum supported AIFS value is 0xfc. Setting the AIFS value * to 0xfd 0xfe or 0xff will not work correctly and will cause * the DCU to hang. */ #define AR_D_LCL_IFS_RESV0 0xF0000000 // Reserved #define AR_CFG_LED 0x1f04 /* LED control */ #define AR_CFG_SCLK_RATE_IND 0x00000003 /* sleep clock indication */ #define AR_CFG_SCLK_RATE_IND_S 0 #define AR_CFG_SCLK_32MHZ 0x00000000 /* Sleep clock rate */ #define AR_CFG_SCLK_4MHZ 0x00000001 /* Sleep clock rate */ #define AR_CFG_SCLK_1MHZ 0x00000002 /* Sleep clock rate */ #define AR_CFG_SCLK_32KHZ 0x00000003 /* Sleep clock rate */ #define AR_CFG_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */ #define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */ #define AR_CFG_LED_MODE_SEL 0x00000380 /* LED mode: bits 7..9 */ #define AR_CFG_LED_MODE_SEL_S 7 /* LED mode: bits 7..9 */ #define AR_CFG_LED_POWER 0x00000280 /* Power LED: bit 9=1, bit 7= */ #define AR_CFG_LED_POWER_S 7 /* LED mode: bits 7..9 */ #define AR_CFG_LED_NETWORK 0x00000300 /* Network LED: bit 9=1, bit 8= */ #define AR_CFG_LED_NETWORK_S 7 /* LED mode: bits 7..9 */ #define AR_CFG_LED_MODE_PROP 0x0 /* Blink prop to filtered tx/rx */ #define AR_CFG_LED_MODE_RPROP 0x1 /* Blink prop to unfiltered tx/rx */ #define AR_CFG_LED_MODE_SPLIT 0x2 /* Blink power for tx/net for rx */ #define AR_CFG_LED_MODE_RAND 0x3 /* Blink randomly */ #define AR_CFG_LED_MODE_POWER_OFF 0x4 /* Power LED OFF */ #define AR_CFG_LED_MODE_POWER_ON 0x5 /* Power LED ON */ #define AR_CFG_LED_MODE_NETWORK_OFF 0x4 /* Network LED OFF */ #define AR_CFG_LED_MODE_NETWORK_ON 0x6 /* Network LED ON */ #define AR_CFG_LED_ASSOC_CTL 0x00000c00 /* LED control: bits 10..11 */ #define AR_CFG_LED_ASSOC_CTL_S 10 /* LED control: bits 10..11 */ #define AR_CFG_LED_ASSOC_NONE 0x0 /* 0x00000000: STA is not associated or trying */ #define AR_CFG_LED_ASSOC_ACTIVE 0x1 /* 0x00000400: STA is associated */ #define AR_CFG_LED_ASSOC_PENDING 0x2 /* 0x00000800: STA is trying to associate */ #define AR_CFG_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode: bit 3 */ #define AR_CFG_LED_BLINK_SLOW_S 3 /* LED slowest blink rate mode: bit 3 */ #define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select: bits 4..6 */ #define AR_CFG_LED_BLINK_THRESH_SEL_S 4 /* LED blink threshold select: bits 4..6 */ #define AR_MAC_SLEEP 0x1f00 #define AR_MAC_SLEEP_MAC_AWAKE 0x00000000 // mac is now awake #define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001 // mac is now asleep /****************************************************************************** * Host Interface Register Map ******************************************************************************/ // DMA & PCI Registers in PCI space (usable during sleep) #define AR_HOSTIF_REG(_ah, _reg) (AH9300(_ah)->ah_hostifregs._reg) #define AR9300_HOSTIF_OFFSET(_x) offsetof(struct host_intf_reg, _x) #define AR9340_HOSTIF_OFFSET(_x) offsetof(struct host_intf_reg_ar9340, _x) /* Interface Reset Control Register */ #define AR_RC_AHB 0x00000001 // ahb reset #define AR_RC_APB 0x00000002 // apb reset #define AR_RC_HOSTIF 0x00000100 // host interface reset /* PCI express work-arounds */ #define AR_WA_D3_TO_L1_DISABLE (1 << 14) #define AR_WA_UNTIE_RESET_EN (1 << 15) /* Enable PCI Reset to POR (power-on-reset) */ #define AR_WA_D3_TO_L1_DISABLE_REAL (1 << 16) #define AR_WA_ASPM_TIMER_BASED_DISABLE (1 << 17) #define AR_WA_RESET_EN (1 << 18) /* Sw Control to enable PCI-Reset to POR (bit 15) */ #define AR_WA_ANALOG_SHIFT (1 << 20) #define AR_WA_POR_SHORT (1 << 21) /* PCI-E Phy reset control */ #define AR_WA_COLD_RESET_OVERRIDE (1 << 13) /* PCI-E Cold reset override */ /* power management state */ #define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 //for wow /* CXPL Debug signals which help debug Link Negotiation */ /* CXPL Debug signals which help debug Link Negotiation */ /* XXX check bit feilds */ /* Power Management Control Register */ #define AR_PCIE_PM_CTRL_ENA 0x00080000 #define AR_PMCTRL_WOW_PME_CLR 0x00200000 /* Clear WoW event */ #define AR_PMCTRL_HOST_PME_EN 0x00400000 /* Send OOB WAKE_L on WoW event */ #define AR_PMCTRL_D3COLD_VAUX 0x00800000 #define AR_PMCTRL_PWR_STATE_MASK 0x0F000000 /* Power State Mask */ #define AR_PMCTRL_PWR_STATE_D1D3 0x0F000000 /* Activate D1 and D3 */ #define AR_PMCTRL_PWR_STATE_D0 0x08000000 /* Activate D0 */ #define AR_PMCTRL_PWR_PM_CTRL_ENA 0x00008000 /* Enable power management */ #define AR_PMCTRL_AUX_PWR_DET 0x10000000 /* Puts Chip in L2 state */ /* APB and Local Bus Timeout Counters */ #define AR_HOST_TIMEOUT_APB_CNTR 0x0000FFFF #define AR_HOST_TIMEOUT_APB_CNTR_S 0 #define AR_HOST_TIMEOUT_LCL_CNTR 0xFFFF0000 #define AR_HOST_TIMEOUT_LCL_CNTR_S 16 /* EEPROM Control Register */ #define AR_EEPROM_ABSENT 0x00000100 #define AR_EEPROM_CORRUPT 0x00000200 #define AR_EEPROM_PROT_MASK 0x03FFFC00 #define AR_EEPROM_PROT_MASK_S 10 // Protect Bits RP is read protect WP is write protect #define EEPROM_PROTECT_RP_0_31 0x0001 #define EEPROM_PROTECT_WP_0_31 0x0002 #define EEPROM_PROTECT_RP_32_63 0x0004 #define EEPROM_PROTECT_WP_32_63 0x0008 #define EEPROM_PROTECT_RP_64_127 0x0010 #define EEPROM_PROTECT_WP_64_127 0x0020 #define EEPROM_PROTECT_RP_128_191 0x0040 #define EEPROM_PROTECT_WP_128_191 0x0080 #define EEPROM_PROTECT_RP_192_255 0x0100 #define EEPROM_PROTECT_WP_192_255 0x0200 #define EEPROM_PROTECT_RP_256_511 0x0400 #define EEPROM_PROTECT_WP_256_511 0x0800 #define EEPROM_PROTECT_RP_512_1023 0x1000 #define EEPROM_PROTECT_WP_512_1023 0x2000 #define EEPROM_PROTECT_RP_1024_2047 0x4000 #define EEPROM_PROTECT_WP_1024_2047 0x8000 /* RF silent */ #define AR_RFSILENT_FORCE 0x01 /* MAC silicon Rev ID */ #define AR_SREV_ID 0x000000FF /* Mask to read SREV info */ #define AR_SREV_VERSION 0x000000F0 /* Mask for Chip version */ #define AR_SREV_VERSION_S 4 /* Mask to shift Major Rev Info */ #define AR_SREV_REVISION 0x00000007 /* Mask for Chip revision level */ /* Sowl extension to SREV. AR_SREV_ID must be 0xFF */ #define AR_SREV_ID2 0xFFFFFFFF /* Mask to read SREV info */ #define AR_SREV_VERSION2 0xFFFC0000 /* Mask for Chip version */ #define AR_SREV_VERSION2_S 18 /* Mask to shift Major Rev Info */ #define AR_SREV_TYPE2 0x0003F000 /* Mask for Chip type */ #define AR_SREV_TYPE2_S 12 /* Mask to shift Major Rev Info */ #define AR_SREV_TYPE2_CHAIN 0x00001000 /* chain mode (1 = 3 chains, 0 = 2 chains) */ #define AR_SREV_TYPE2_HOST_MODE 0x00002000 /* host mode (1 = PCI, 0 = PCIe) */ /* Jupiter has a different TYPE2 definition. */ #define AR_SREV_TYPE2_JUPITER_CHAIN 0x00001000 /* chain (1 = 2 chains, 0 = 1 chain) */ #define AR_SREV_TYPE2_JUPITER_BAND 0x00002000 /* band (1 = dual band, 0 = single band) */ #define AR_SREV_TYPE2_JUPITER_BT 0x00004000 /* BT (1 = shared BT, 0 = no BT) */ #define AR_SREV_TYPE2_JUPITER_MODE 0x00008000 /* mode (1 = premium, 0 = standard) */ #define AR_SREV_REVISION2 0x00000F00 #define AR_SREV_REVISION2_S 8 #define AR_RADIO_SREV_MAJOR 0xf0 #define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */ #define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */ #define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */ #define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */ #if 0 #define AR_AHB_MODE 0x4024 // ahb mode for dma #define AR_AHB_EXACT_WR_EN 0x00000000 // write exact bytes #define AR_AHB_BUF_WR_EN 0x00000001 // buffer write upto cacheline #define AR_AHB_EXACT_RD_EN 0x00000000 // read exact bytes #define AR_AHB_CACHELINE_RD_EN 0x00000002 // read upto end of cacheline #define AR_AHB_PREFETCH_RD_EN 0x00000004 // prefetch upto page boundary #define AR_AHB_PAGE_SIZE_1K 0x00000000 // set page-size as 1k #define AR_AHB_PAGE_SIZE_2K 0x00000008 // set page-size as 2k #define AR_AHB_PAGE_SIZE_4K 0x00000010 // set page-size as 4k #endif #define AR_INTR_RTC_IRQ 0x00000001 // rtc in shutdown state #define AR_INTR_MAC_IRQ 0x00000002 // pending mac interrupt #if 0 /* * the following definitions might be differents for WASP so * disable them to avoid improper use */ #define AR_INTR_EEP_PROT_ACCESS 0x00000004 // eeprom protected area access #define AR_INTR_MAC_AWAKE 0x00020000 // mac is awake #define AR_INTR_MAC_ASLEEP 0x00040000 // mac is asleep #endif #define AR_INTR_SPURIOUS 0xFFFFFFFF /* TODO: fill in other values */ /* Synchronous Interrupt Cause Register */ /* Synchronous Interrupt Enable Register */ #define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 // enable interrupts: bits 18..31 #define AR_INTR_SYNC_ENABLE_GPIO_S 18 // enable interrupts: bits 18..31 /* * synchronous interrupt signals */ enum { AR9300_INTR_SYNC_RTC_IRQ = 0x00000001, AR9300_INTR_SYNC_MAC_IRQ = 0x00000002, AR9300_INTR_SYNC_EEPROM_ILLEGAL_ACCESS = 0x00000004, AR9300_INTR_SYNC_APB_TIMEOUT = 0x00000008, AR9300_INTR_SYNC_PCI_MODE_CONFLICT = 0x00000010, AR9300_INTR_SYNC_HOST1_FATAL = 0x00000020, AR9300_INTR_SYNC_HOST1_PERR = 0x00000040, AR9300_INTR_SYNC_TRCV_FIFO_PERR = 0x00000080, AR9300_INTR_SYNC_RADM_CPL_EP = 0x00000100, AR9300_INTR_SYNC_RADM_CPL_DLLP_ABORT = 0x00000200, AR9300_INTR_SYNC_RADM_CPL_TLP_ABORT = 0x00000400, AR9300_INTR_SYNC_RADM_CPL_ECRC_ERR = 0x00000800, AR9300_INTR_SYNC_RADM_CPL_TIMEOUT = 0x00001000, AR9300_INTR_SYNC_LOCAL_TIMEOUT = 0x00002000, AR9300_INTR_SYNC_PM_ACCESS = 0x00004000, AR9300_INTR_SYNC_MAC_AWAKE = 0x00008000, AR9300_INTR_SYNC_MAC_ASLEEP = 0x00010000, AR9300_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00020000, AR9300_INTR_SYNC_ALL = 0x0003FFFF, /* * Do not enable and turn on mask for both sync and async interrupt, since * chip can generate interrupt storm. */ AR9300_INTR_SYNC_DEF_NO_HOST1_PERR = (AR9300_INTR_SYNC_HOST1_FATAL | AR9300_INTR_SYNC_RADM_CPL_EP | AR9300_INTR_SYNC_RADM_CPL_DLLP_ABORT | AR9300_INTR_SYNC_RADM_CPL_TLP_ABORT | AR9300_INTR_SYNC_RADM_CPL_ECRC_ERR | AR9300_INTR_SYNC_RADM_CPL_TIMEOUT | AR9300_INTR_SYNC_LOCAL_TIMEOUT | AR9300_INTR_SYNC_MAC_SLEEP_ACCESS), AR9300_INTR_SYNC_DEFAULT = (AR9300_INTR_SYNC_DEF_NO_HOST1_PERR | AR9300_INTR_SYNC_HOST1_PERR), AR9300_INTR_SYNC_SPURIOUS = 0xFFFFFFFF, /* WASP */ AR9340_INTR_SYNC_RTC_IRQ = 0x00000001, AR9340_INTR_SYNC_MAC_IRQ = 0x00000002, AR9340_INTR_SYNC_HOST1_FATAL = 0x00000004, AR9340_INTR_SYNC_HOST1_PERR = 0x00000008, AR9340_INTR_SYNC_LOCAL_TIMEOUT = 0x00000010, AR9340_INTR_SYNC_MAC_ASLEEP = 0x00000020, AR9340_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00000040, AR9340_INTR_SYNC_DEFAULT = (AR9340_INTR_SYNC_HOST1_FATAL | AR9340_INTR_SYNC_HOST1_PERR | AR9340_INTR_SYNC_LOCAL_TIMEOUT | AR9340_INTR_SYNC_MAC_SLEEP_ACCESS), AR9340_INTR_SYNC_SPURIOUS = 0xFFFFFFFF, }; /* Asynchronous Interrupt Mask Register */ #define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 // asynchronous interrupt mask: bits 18..31 #define AR_INTR_ASYNC_MASK_GPIO_S 18 // asynchronous interrupt mask: bits 18..31 #define AR_INTR_ASYNC_MASK_MCI 0x00000080 #define AR_INTR_ASYNC_MASK_MCI_S 7 /* Synchronous Interrupt Mask Register */ #define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 // synchronous interrupt mask: bits 18..31 #define AR_INTR_SYNC_MASK_GPIO_S 18 // synchronous interrupt mask: bits 18..31 /* Asynchronous Interrupt Cause Register */ #define AR_INTR_ASYNC_CAUSE_GPIO 0xFFFC0000 // GPIO interrupts: bits 18..31 #define AR_INTR_ASYNC_CAUSE_MCI 0x00000080 #define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_CAUSE_GPIO | AR_INTR_ASYNC_CAUSE_MCI) /* Asynchronous Interrupt Enable Register */ #define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 // enable interrupts: bits 18..31 #define AR_INTR_ASYNC_ENABLE_GPIO_S 18 // enable interrupts: bits 18..31 #define AR_INTR_ASYNC_ENABLE_MCI 0x00000080 #define AR_INTR_ASYNC_ENABLE_MCI_S 7 /* PCIE PHY Data Register */ /* PCIE PHY Load Register */ #define AR_PCIE_PM_CTRL_ENA 0x00080000 #define AR93XX_NUM_GPIO 16 // 0 to 15 /* GPIO Output Register */ #define AR_GPIO_OUT_VAL 0x000FFFF #define AR_GPIO_OUT_VAL_S 0 /* GPIO Input Register */ #define AR_GPIO_IN_VAL 0x000FFFF #define AR_GPIO_IN_VAL_S 0 /* Host GPIO output enable bits */ #define AR_GPIO_OE_OUT_DRV 0x3 // 2 bit field mask, shifted by 2*bitpos #define AR_GPIO_OE_OUT_DRV_NO 0x0 // tristate #define AR_GPIO_OE_OUT_DRV_LOW 0x1 // drive if low #define AR_GPIO_OE_OUT_DRV_HI 0x2 // drive if high #define AR_GPIO_OE_OUT_DRV_ALL 0x3 // drive always /* Host GPIO output enable bits */ /* Host GPIO Interrupt Polarity */ #define AR_GPIO_INTR_POL_VAL 0x0001FFFF // bits 16:0 correspond to gpio 16:0 #define AR_GPIO_INTR_POL_VAL_S 0 // bits 16:0 correspond to gpio 16:0 /* Host GPIO Input Value */ #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 // default value for bt_priority_async #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 // default value for bt_frequency_async #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S 3 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010 // default value for bt_active_async #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S 4 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 // default value for rfsilent_bb_l #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400 // 0 == set bt_priority_async to default, 1 == connect bt_prority_async to baseband #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S 10 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_BB 0x00000800 // 0 == set bt_frequency_async to default, 1 == connect bt_frequency_async to baseband #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_BB_S 11 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 // 0 == set bt_active_async to default, 1 == connect bt_active_async to baseband #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 // 0 == set rfsilent_bb_l to default, 1 == connect rfsilent_bb_l to baseband #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 #define AR_GPIO_JTAG_DISABLE 0x00020000 // 1 == disable JTAG /* GPIO Input Mux1 */ #define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00 /* bits 8..11: input mux for BT priority input */ #define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8 /* bits 8..11: input mux for BT priority input */ #define AR_GPIO_INPUT_MUX1_BT_FREQUENCY 0x0000f000 /* bits 12..15: input mux for BT frequency input */ #define AR_GPIO_INPUT_MUX1_BT_FREQUENCY_S 12 /* bits 12..15: input mux for BT frequency input */ #define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000 /* bits 16..19: input mux for BT active input */ #define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 /* bits 16..19: input mux for BT active input */ /* GPIO Input Mux2 */ #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f // bits 0..3: input mux for clk25 input #define AR_GPIO_INPUT_MUX2_CLK25_S 0 // bits 0..3: input mux for clk25 input #define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 // bits 4..7: input mux for rfsilent_bb_l input #define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 // bits 4..7: input mux for rfsilent_bb_l input #define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 // bits 8..11: input mux for RTC Reset input #define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 // bits 8..11: input mux for RTC Reset input /* GPIO Output Mux1 */ /* GPIO Output Mux2 */ /* GPIO Output Mux3 */ #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e #define AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0 0x1d #define AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1 0x1e #define AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2 0x1b /* The above three seems to be functional values for peacock chip. For some * reason these are continued for different boards as simple place holders. * Now continuing to use these and adding the extra definitions for Scropion */ #define AR_GPIO_OUTPUT_MUX_AS_SWCOM3 0x26 #define AR_ENABLE_SMARTANTENNA 0x00000001 /* Host GPIO Input State */ /* Host Spare */ /* Host PCIE Core Reset Enable */ /* Host CLKRUN */ /* Host EEPROM Status */ #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff #define AR_EEPROM_STATUS_DATA_VAL_S 0 #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 #define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 /* Host Observation Control */ /* Host RF Silent */ /* Host GPIO PDPU */ #define AR_GPIO_PDPU_OPTION 0x03 #define AR_GPIO_PULL_DOWN 0x02 /* Host GPIO Drive Strength */ /* Host Miscellaneous */ /* Host PCIE MSI Control Register */ #define AR_PCIE_MSI_ENABLE 0x00000001 #define AR_PCIE_MSI_HW_DBI_WR_EN 0x02000000 #define AR_PCIE_MSI_HW_INT_PENDING_ADDR 0xFFA0C1FF // bits 8..11: value must be 0x5060 #define AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64 0xFFA0C9FF // bits 8..11: value must be 0x5064 #define AR_INTR_PRIO_TX 0x00000001 #define AR_INTR_PRIO_RXLP 0x00000002 #define AR_INTR_PRIO_RXHP 0x00000004 /* OTP Interface Register */ #define AR_ENT_OTP AR9300_HOSTIF_OFFSET(HOST_INTF_OTP) #define AR_ENT_OTP_DUAL_BAND_DISABLE 0x00010000 #define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000 #define AR_ENT_OTP_5MHZ_DISABLE 0x00040000 #define AR_ENT_OTP_10MHZ_DISABLE 0x00080000 #define AR_ENT_OTP_49GHZ_DISABLE 0x00100000 #define AR_ENT_OTP_LOOPBACK_DISABLE 0x00200000 #define AR_ENT_OTP_TPC_PERF_DISABLE 0x00400000 #define AR_ENT_OTP_MIN_PKT_SIZE_DISABLE 0x00800000 #define AR_ENT_OTP_SPECTRAL_PRECISION 0x03000000 /* OTP EFUSE registers */ #define AR_OTP_EFUSE_OFFSET(_x) offsetof(struct efuse_reg_WLAN, _x) #define AR_OTP_EFUSE_INTF0 AR_OTP_EFUSE_OFFSET(OTP_INTF0) #define AR_OTP_EFUSE_INTF5 AR_OTP_EFUSE_OFFSET(OTP_INTF5) #define AR_OTP_EFUSE_PGENB_SETUP_HOLD_TIME AR_OTP_EFUSE_OFFSET(OTP_PGENB_SETUP_HOLD_TIME) #define AR_OTP_EFUSE_MEM AR_OTP_EFUSE_OFFSET(OTP_MEM) /****************************************************************************** * RTC Register Map ******************************************************************************/ #define AR_RTC_OFFSET(_x) offsetof(struct rtc_reg, _x) /* Reset Control */ #define AR_RTC_RC AR_RTC_OFFSET(RESET_CONTROL) #define AR_RTC_RC_M 0x00000003 #define AR_RTC_RC_MAC_WARM 0x00000001 #define AR_RTC_RC_MAC_COLD 0x00000002 /* Crystal Control */ #define AR_RTC_XTAL_CONTROL AR_RTC_OFFSET(XTAL_CONTROL) /* Reg Control 0 */ #define AR_RTC_REG_CONTROL0 AR_RTC_OFFSET(REG_CONTROL0) /* Reg Control 1 */ #define AR_RTC_REG_CONTROL1 AR_RTC_OFFSET(REG_CONTROL1) #define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x00000001 /* TCXO Detect */ #define AR_RTC_TCXO_DETECT AR_RTC_OFFSET(TCXO_DETECT) /* Crystal Test */ #define AR_RTC_XTAL_TEST AR_RTC_OFFSET(XTAL_TEST) /* Sets the ADC/DAC clock quadrature */ #define AR_RTC_QUADRATURE AR_RTC_OFFSET(QUADRATURE) /* PLL Control */ #define AR_RTC_PLL_CONTROL AR_RTC_OFFSET(PLL_CONTROL) #define AR_RTC_PLL_DIV 0x000003ff #define AR_RTC_PLL_DIV_S 0 #define AR_RTC_PLL_REFDIV 0x00003C00 #define AR_RTC_PLL_REFDIV_S 10 #define AR_RTC_PLL_CLKSEL 0x0000C000 #define AR_RTC_PLL_CLKSEL_S 14 #define AR_RTC_PLL_BYPASS 0x00010000 #define AR_RTC_PLL_BYPASS_S 16 /* PLL Control 2: for Hornet */ #define AR_RTC_PLL_CONTROL2 AR_RTC_OFFSET(PLL_CONTROL2) /* PLL Settle */ #define AR_RTC_PLL_SETTLE AR_RTC_OFFSET(PLL_SETTLE) /* Crystal Settle */ #define AR_RTC_XTAL_SETTLE AR_RTC_OFFSET(XTAL_SETTLE) /* Controls CLK_OUT pin clock speed */ #define AR_RTC_CLOCK_OUT AR_RTC_OFFSET(CLOCK_OUT) /* Forces bias block on at all times */ #define AR_RTC_BIAS_OVERRIDE AR_RTC_OFFSET(BIAS_OVERRIDE) /* System Sleep status bits */ #define AR_RTC_SYSTEM_SLEEP AR_RTC_OFFSET(SYSTEM_SLEEP) /* Controls sleep options for MAC */ #define AR_RTC_MAC_SLEEP_CONTROL AR_RTC_OFFSET(MAC_SLEEP_CONTROL) /* Keep Awake Timer */ #define AR_RTC_KEEP_AWAKE AR_RTC_OFFSET(KEEP_AWAKE) /* Create a 32kHz clock derived from HF */ #define AR_RTC_DERIVED_RTC_CLK AR_RTC_OFFSET(DERIVED_RTC_CLK) /****************************************************************************** * RTC SYNC Register Map ******************************************************************************/ #define AR_RTC_SYNC_OFFSET(_x) offsetof(struct rtc_sync_reg, _x) /* reset RTC */ #define AR_RTC_RESET AR_RTC_SYNC_OFFSET(RTC_SYNC_RESET) #define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */ /* system sleep status */ #define AR_RTC_STATUS AR_RTC_SYNC_OFFSET(RTC_SYNC_STATUS) #define AR_RTC_STATUS_M 0x0000003f #define AR_RTC_STATUS_SHUTDOWN 0x00000001 #define AR_RTC_STATUS_ON 0x00000002 #define AR_RTC_STATUS_SLEEP 0x00000004 #define AR_RTC_STATUS_WAKEUP 0x00000008 #define AR_RTC_STATUS_SLEEP_ACCESS 0x00000010 #define AR_RTC_STATUS_PLL_CHANGING 0x00000020 /* RTC Derived Register */ #define AR_RTC_SLEEP_CLK AR_RTC_SYNC_OFFSET(RTC_SYNC_DERIVED) #define AR_RTC_FORCE_DERIVED_CLK 0x00000002 #define AR_RTC_FORCE_SWREG_PRD 0x00000004 #define AR_RTC_PCIE_RST_PWDN_EN 0x00000008 /* RTC Force Wake Register */ #define AR_RTC_FORCE_WAKE AR_RTC_SYNC_OFFSET(RTC_SYNC_FORCE_WAKE) #define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ /* RTC interrupt cause/clear */ #define AR_RTC_INTR_CAUSE AR_RTC_SYNC_OFFSET(RTC_SYNC_INTR_CAUSE) /* RTC interrupt enable */ #define AR_RTC_INTR_ENABLE AR_RTC_SYNC_OFFSET(RTC_SYNC_INTR_ENABLE) /* RTC interrupt mask */ #define AR_RTC_INTR_MASK AR_RTC_SYNC_OFFSET(RTC_SYNC_INTR_MASK) /****************************************************************************** * Analog Interface Register Map ******************************************************************************/ #define AR_AN_OFFSET(_x) offsetof(struct analog_intf_reg_csr, _x) /* XXX */ #if 1 // AR9280: rf long shift registers #define AR_AN_RF2G1_CH0 0x7810 #define AR_AN_RF2G1_CH0_OB 0x03800000 #define AR_AN_RF2G1_CH0_OB_S 23 #define AR_AN_RF2G1_CH0_DB 0x1C000000 #define AR_AN_RF2G1_CH0_DB_S 26 #define AR_AN_RF5G1_CH0 0x7818 #define AR_AN_RF5G1_CH0_OB5 0x00070000 #define AR_AN_RF5G1_CH0_OB5_S 16 #define AR_AN_RF5G1_CH0_DB5 0x00380000 #define AR_AN_RF5G1_CH0_DB5_S 19 #define AR_AN_RF2G1_CH1 0x7834 #define AR_AN_RF2G1_CH1_OB 0x03800000 #define AR_AN_RF2G1_CH1_OB_S 23 #define AR_AN_RF2G1_CH1_DB 0x1C000000 #define AR_AN_RF2G1_CH1_DB_S 26 #define AR_AN_RF5G1_CH1 0x783C #define AR_AN_RF5G1_CH1_OB5 0x00070000 #define AR_AN_RF5G1_CH1_OB5_S 16 #define AR_AN_RF5G1_CH1_DB5 0x00380000 #define AR_AN_RF5G1_CH1_DB5_S 19 #define AR_AN_TOP2 0x7894 #define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 #define AR_AN_TOP2_XPABIAS_LVL_S 30 #define AR_AN_TOP2_LOCALBIAS 0x00200000 #define AR_AN_TOP2_LOCALBIAS_S 21 #define AR_AN_TOP2_PWDCLKIND 0x00400000 #define AR_AN_TOP2_PWDCLKIND_S 22 #define AR_AN_SYNTH9 0x7868 #define AR_AN_SYNTH9_REFDIVA 0xf8000000 #define AR_AN_SYNTH9_REFDIVA_S 27 // AR9285 Analog registers #define AR9285_AN_RF2G1 0x7820 #define AR9285_AN_RF2G2 0x7824 #define AR9285_AN_RF2G3 0x7828 #define AR9285_AN_RF2G3_OB_0 0x00E00000 #define AR9285_AN_RF2G3_OB_0_S 21 #define AR9285_AN_RF2G3_OB_1 0x001C0000 #define AR9285_AN_RF2G3_OB_1_S 18 #define AR9285_AN_RF2G3_OB_2 0x00038000 #define AR9285_AN_RF2G3_OB_2_S 15 #define AR9285_AN_RF2G3_OB_3 0x00007000 #define AR9285_AN_RF2G3_OB_3_S 12 #define AR9285_AN_RF2G3_OB_4 0x00000E00 #define AR9285_AN_RF2G3_OB_4_S 9 #define AR9285_AN_RF2G3_DB1_0 0x000001C0 #define AR9285_AN_RF2G3_DB1_0_S 6 #define AR9285_AN_RF2G3_DB1_1 0x00000038 #define AR9285_AN_RF2G3_DB1_1_S 3 #define AR9285_AN_RF2G3_DB1_2 0x00000007 #define AR9285_AN_RF2G3_DB1_2_S 0 #define AR9285_AN_RF2G4 0x782C #define AR9285_AN_RF2G4_DB1_3 0xE0000000 #define AR9285_AN_RF2G4_DB1_3_S 29 #define AR9285_AN_RF2G4_DB1_4 0x1C000000 #define AR9285_AN_RF2G4_DB1_4_S 26 #define AR9285_AN_RF2G4_DB2_0 0x03800000 #define AR9285_AN_RF2G4_DB2_0_S 23 #define AR9285_AN_RF2G4_DB2_1 0x00700000 #define AR9285_AN_RF2G4_DB2_1_S 20 #define AR9285_AN_RF2G4_DB2_2 0x000E0000 #define AR9285_AN_RF2G4_DB2_2_S 17 #define AR9285_AN_RF2G4_DB2_3 0x0001C000 #define AR9285_AN_RF2G4_DB2_3_S 14 #define AR9285_AN_RF2G4_DB2_4 0x00003800 #define AR9285_AN_RF2G4_DB2_4_S 11 #define AR9285_AN_RF2G6 0x7834 #define AR9285_AN_RF2G7 0x7838 #define AR9285_AN_RF2G9 0x7840 #define AR9285_AN_RXTXBB1 0x7854 #define AR9285_AN_TOP2 0x7868 #define AR9285_AN_TOP3 0x786c #define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C #define AR9285_AN_TOP3_XPABIAS_LVL_S 2 #define AR9285_AN_TOP4 0x7870 #define AR9285_AN_TOP4_DEFAULT 0x10142c00 #endif /****************************************************************************** * MAC PCU Register Map ******************************************************************************/ #define AR_MAC_PCU_OFFSET(_x) offsetof(struct mac_pcu_reg, _x) /* MAC station ID0 - low 32 bits */ #define AR_STA_ID0 AR_MAC_PCU_OFFSET(MAC_PCU_STA_ADDR_L32) /* MAC station ID1 - upper 16 bits */ #define AR_STA_ID1 AR_MAC_PCU_OFFSET(MAC_PCU_STA_ADDR_U16) #define AR_STA_ID1_SADH_MASK 0x0000FFFF // Mask for 16 msb of MAC addr #define AR_STA_ID1_STA_AP 0x00010000 // Device is AP #define AR_STA_ID1_ADHOC 0x00020000 // Device is ad-hoc #define AR_STA_ID1_PWR_SAV 0x00040000 // Power save in generated frames #define AR_STA_ID1_KSRCHDIS 0x00080000 // Key search disable #define AR_STA_ID1_PCF 0x00100000 // Observe PCF #define AR_STA_ID1_USE_DEFANT 0x00200000 // Use default antenna #define AR_STA_ID1_DEFANT_UPDATE 0x00400000 // Update default ant w/TX antenna #define AR_STA_ID1_RTS_USE_DEF 0x00800000 // Use default antenna to send RTS #define AR_STA_ID1_ACKCTS_6MB 0x01000000 // Use 6Mb/s rate for ACK & CTS #define AR_STA_ID1_BASE_RATE_11B 0x02000000 // Use 11b base rate for ACK & CTS #define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000 // default ant for generated frames #define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 // Enable Michael #define AR_STA_ID1_KSRCH_MODE 0x10000000 // Look-up unique key when !keyID #define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 // Don't replace seq num #define AR_STA_ID1_CBCIV_ENDIAN 0x40000000 // IV endian-ness in CBC nonce #define AR_STA_ID1_MCAST_KSRCH 0x80000000 // Adhoc key search enable /* MAC BSSID low 32 bits */ #define AR_BSS_ID0 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID_L32) /* MAC BSSID upper 16 bits / AID */ #define AR_BSS_ID1 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID_U16) #define AR_BSS_ID1_U16 0x0000FFFF // Mask for upper 16 bits of BSSID #define AR_BSS_ID1_AID 0x07FF0000 // Mask for association ID #define AR_BSS_ID1_AID_S 16 // Shift for association ID /* * Added to support dual BSSID/TSF which are needed in the application * of Mesh networking. See bug 35189. Note that the only function added * with this BSSID2 is to receive multi/broadcast from BSSID2 as well */ /* MAC BSSID low 32 bits */ #define AR_BSS2_ID0 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID2_L32) /* MAC BSSID upper 16 bits / AID */ #define AR_BSS2_ID1 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID2_U16) /* MAC Beacon average RSSI * * This register holds the average RSSI with 1/16 dB resolution. * The RSSI is averaged over multiple beacons which matched our BSSID. * Note that AVE_VALUE is 12 bits with 4 bits below the normal 8 bits. * These lowest 4 bits provide for a resolution of 1/16 dB. * */ #define AR_BCN_RSSI_AVE AR_MAC_PCU_OFFSET(MAC_PCU_BCN_RSSI_AVE) #define AR_BCN_RSSI_AVE_VAL 0x00000FFF // Beacon RSSI value #define AR_BCN_RSSI_AVE_VAL_S 0 /* MAC ACK & CTS time-out */ #define AR_TIME_OUT AR_MAC_PCU_OFFSET(MAC_PCU_ACK_CTS_TIMEOUT) #define AR_TIME_OUT_ACK 0x00003FFF // Mask for ACK time-out #define AR_TIME_OUT_ACK_S 0 #define AR_TIME_OUT_CTS 0x3FFF0000 // Mask for CTS time-out #define AR_TIME_OUT_CTS_S 16 /* beacon RSSI warning / bmiss threshold */ #define AR_RSSI_THR AR_MAC_PCU_OFFSET(MAC_PCU_BCN_RSSI_CTL) #define AR_RSSI_THR_VAL 0x000000FF // Beacon RSSI warning threshold #define AR_RSSI_THR_VAL_S 0 #define AR_RSSI_THR_BM_THR 0x0000FF00 // Mask for Missed beacon threshold #define AR_RSSI_THR_BM_THR_S 8 // Shift for Missed beacon threshold #define AR_RSSI_BCN_WEIGHT 0x1F000000 // RSSI average weight #define AR_RSSI_BCN_WEIGHT_S 24 #define AR_RSSI_BCN_RSSI_RST 0x20000000 // Reset RSSI value /* MAC transmit latency register */ #define AR_USEC AR_MAC_PCU_OFFSET(MAC_PCU_USEC_LATENCY) #define AR_USEC_USEC 0x000000FF // Mask for clock cycles in 1 usec #define AR_USEC_USEC_S 0 // Shift for clock cycles in 1 usec #define AR_USEC_TX_LAT 0x007FC000 // tx latency to start of SIGNAL (usec) #define AR_USEC_TX_LAT_S 14 // tx latency to start of SIGNAL (usec) #define AR_USEC_RX_LAT 0x1F800000 // rx latency to start of SIGNAL (usec) #define AR_USEC_RX_LAT_S 23 // rx latency to start of SIGNAL (usec) #define AR_SLOT_HALF 13 #define AR_SLOT_QUARTER 21 #define AR_USEC_RX_LATENCY 0x1f800000 #define AR_USEC_RX_LATENCY_S 23 #define AR_RX_LATENCY_FULL 37 #define AR_RX_LATENCY_HALF 74 #define AR_RX_LATENCY_QUARTER 148 #define AR_RX_LATENCY_FULL_FAST_CLOCK 41 #define AR_RX_LATENCY_HALF_FAST_CLOCK 82 #define AR_RX_LATENCY_QUARTER_FAST_CLOCK 163 #define AR_USEC_TX_LATENCY 0x007fc000 #define AR_USEC_TX_LATENCY_S 14 #define AR_TX_LATENCY_FULL 54 #define AR_TX_LATENCY_HALF 108 #define AR_TX_LATENCY_QUARTER 216 #define AR_TX_LATENCY_FULL_FAST_CLOCK 54 #define AR_TX_LATENCY_HALF_FAST_CLOCK 119 #define AR_TX_LATENCY_QUARTER_FAST_CLOCK 238 #define AR_USEC_HALF 19 #define AR_USEC_QUARTER 9 #define AR_USEC_HALF_FAST_CLOCK 21 #define AR_USEC_QUARTER_FAST_CLOCK 10 #define AR_EIFS_HALF 175 #define AR_EIFS_QUARTER 340 #define AR_RESET_TSF AR_MAC_PCU_OFFSET(MAC_PCU_RESET_TSF) #define AR_RESET_TSF_ONCE 0x01000000 // reset tsf once ; self-clears bit #define AR_RESET_TSF2_ONCE 0x02000000 // reset tsf2 once ; self-clears bit /* MAC CFP Interval (TU/msec) */ #define AR_CFP_PERIOD 0x8024 /* MAC CFP Interval (TU/msec) */ #define AR_TIMER0 0x8028 /* MAC Next beacon time (TU/msec) */ #define AR_TIMER1 0x802c /* MAC DMA beacon alert time (1/8 TU) */ #define AR_TIMER2 0x8030 /* MAC Software beacon alert (1/8 TU) */ #define AR_TIMER3 0x8034 /* MAC ATIM window time */ /* MAC maximum CFP duration */ #define AR_MAX_CFP_DUR AR_MAC_PCU_OFFSET(MAC_PCU_MAX_CFP_DUR) #define AR_CFP_VAL 0x0000FFFF // CFP value in uS /* MAC receive filter register */ #define AR_RX_FILTER AR_MAC_PCU_OFFSET(MAC_PCU_RX_FILTER) #define AR_RX_FILTER_ALL 0x00000000 // Disallow all frames #define AR_RX_UCAST 0x00000001 // Allow unicast frames #define AR_RX_MCAST 0x00000002 // Allow multicast frames #define AR_RX_BCAST 0x00000004 // Allow broadcast frames #define AR_RX_CONTROL 0x00000008 // Allow control frames #define AR_RX_BEACON 0x00000010 // Allow beacon frames #define AR_RX_PROM 0x00000020 // Promiscuous mode all packets #define AR_RX_PROBE_REQ 0x00000080 // Any probe request frameA #define AR_RX_MY_BEACON 0x00000200 // Any beacon frame with matching BSSID #define AR_RX_COMPR_BAR 0x00000400 // Compressed directed block ack request #define AR_RX_COMPR_BA 0x00000800 // Compressed directed block ack #define AR_RX_UNCOM_BA_BAR 0x00001000 // Uncompressed directed BA or BAR #define AR_RX_HWBCNPROC_EN 0x00020000 // Enable hw beacon processing (see AR_HWBCNPROC1) #define AR_RX_CONTROL_WRAPPER 0x00080000 // Control wrapper. Jupiter only. #define AR_RX_4ADDRESS 0x00100000 // 4-Address frames #define AR_PHY_ERR_MASK_REG AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERROR_MASK_CONT) /* MAC multicast filter lower 32 bits */ #define AR_MCAST_FIL0 AR_MAC_PCU_OFFSET(MAC_PCU_MCAST_FILTER_L32) /* MAC multicast filter upper 32 bits */ #define AR_MCAST_FIL1 AR_MAC_PCU_OFFSET(MAC_PCU_MCAST_FILTER_U32) /* MAC PCU diagnostic switches */ #define AR_DIAG_SW AR_MAC_PCU_OFFSET(MAC_PCU_DIAG_SW) #define AR_DIAG_CACHE_ACK 0x00000001 // disable ACK when no valid key #define AR_DIAG_ACK_DIS 0x00000002 // disable ACK generation #define AR_DIAG_CTS_DIS 0x00000004 // disable CTS generation #define AR_DIAG_ENCRYPT_DIS 0x00000008 // disable encryption #define AR_DIAG_DECRYPT_DIS 0x00000010 // disable decryption #define AR_DIAG_RX_DIS 0x00000020 // disable receive #define AR_DIAG_LOOP_BACK 0x00000040 // enable loopback #define AR_DIAG_CORR_FCS 0x00000080 // corrupt FCS #define AR_DIAG_CHAN_INFO 0x00000100 // dump channel info #define AR_DIAG_FRAME_NV0 0x00020000 // accept w/protocol version !0 #define AR_DIAG_OBS_PT_SEL1 0x000C0000 // observation point select #define AR_DIAG_OBS_PT_SEL1_S 18 // Shift for observation point select #define AR_DIAG_FORCE_RX_CLEAR 0x00100000 // force rx_clear high #define AR_DIAG_IGNORE_VIRT_CS 0x00200000 // ignore virtual carrier sense #define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 // force channel idle high #define AR_DIAG_EIFS_CTRL_ENA 0x00800000 // use framed and ~wait_wep if 0 #define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 // dual chain channel info #define AR_DIAG_RX_ABORT 0x02000000 // abort rx #define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000 // saturate cycle cnts (no shift) #define AR_DIAG_OBS_PT_SEL2 0x08000000 // Mask for observation point sel #define AR_DIAG_OBS_PT_SEL2_S 27 #define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000 // force rx_clear (ctl) low (i.e. busy) #define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000 // force rx_clear (ext) low (i.e. busy) /* MAC local clock lower 32 bits */ #define AR_TSF_L32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF_L32) /* MAC local clock upper 32 bits */ #define AR_TSF_U32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF_U32) /* * Secondary TSF support added for dual BSSID/TSF * which is needed in the application of DirectConnect or * Mesh networking */ /* MAC local clock lower 32 bits */ #define AR_TSF2_L32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF2_L32) /* MAC local clock upper 32 bits */ #define AR_TSF2_U32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF2_U32) /* ADDAC test register */ #define AR_TST_ADDAC AR_MAC_PCU_OFFSET(MAC_PCU_TST_ADDAC) #define AR_TST_ADDAC_TST_MODE 0x1 #define AR_TST_ADDAC_TST_MODE_S 0 #define AR_TST_ADDAC_TST_LOOP_ENA 0x2 #define AR_TST_ADDAC_TST_LOOP_ENA_S 1 #define AR_TST_ADDAC_BEGIN_CAPTURE 0x80000 #define AR_TST_ADDAC_BEGIN_CAPTURE_S 19 /* default antenna register */ #define AR_DEF_ANTENNA AR_MAC_PCU_OFFSET(MAC_PCU_DEF_ANTENNA) /* MAC AES mute mask */ #define AR_AES_MUTE_MASK0 AR_MAC_PCU_OFFSET(MAC_PCU_AES_MUTE_MASK_0) #define AR_AES_MUTE_MASK0_FC 0x0000FFFF // frame ctrl mask bits #define AR_AES_MUTE_MASK0_QOS 0xFFFF0000 // qos ctrl mask bits #define AR_AES_MUTE_MASK0_QOS_S 16 /* MAC AES mute mask 1 */ #define AR_AES_MUTE_MASK1 AR_MAC_PCU_OFFSET(MAC_PCU_AES_MUTE_MASK_1) #define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF // seq + frag mask bits #define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF0000 // frame ctrl mask for mgmt frames (Sowl) #define AR_AES_MUTE_MASK1_FC_MGMT_S 16 /* control clock domain */ #define AR_GATED_CLKS AR_MAC_PCU_OFFSET(MAC_PCU_GATED_CLKS) #define AR_GATED_CLKS_TX 0x00000002 #define AR_GATED_CLKS_RX 0x00000004 #define AR_GATED_CLKS_REG 0x00000008 /* MAC PCU observation bus 2 */ #define AR_OBS_BUS_CTRL AR_MAC_PCU_OFFSET(MAC_PCU_OBS_BUS_2) #define AR_OBS_BUS_SEL_1 0x00040000 #define AR_OBS_BUS_SEL_2 0x00080000 #define AR_OBS_BUS_SEL_3 0x000C0000 #define AR_OBS_BUS_SEL_4 0x08040000 #define AR_OBS_BUS_SEL_5 0x08080000 /* MAC PCU observation bus 1 */ #define AR_OBS_BUS_1 AR_MAC_PCU_OFFSET(MAC_PCU_OBS_BUS_1) #define AR_OBS_BUS_1_PCU 0x00000001 #define AR_OBS_BUS_1_RX_END 0x00000002 #define AR_OBS_BUS_1_RX_WEP 0x00000004 #define AR_OBS_BUS_1_RX_BEACON 0x00000008 #define AR_OBS_BUS_1_RX_FILTER 0x00000010 #define AR_OBS_BUS_1_TX_HCF 0x00000020 #define AR_OBS_BUS_1_QUIET_TIME 0x00000040 #define AR_OBS_BUS_1_CHAN_IDLE 0x00000080 #define AR_OBS_BUS_1_TX_HOLD 0x00000100 #define AR_OBS_BUS_1_TX_FRAME 0x00000200 #define AR_OBS_BUS_1_RX_FRAME 0x00000400 #define AR_OBS_BUS_1_RX_CLEAR 0x00000800 #define AR_OBS_BUS_1_WEP_STATE 0x0003F000 #define AR_OBS_BUS_1_WEP_STATE_S 12 #define AR_OBS_BUS_1_RX_STATE 0x01F00000 #define AR_OBS_BUS_1_RX_STATE_S 20 #define AR_OBS_BUS_1_TX_STATE 0x7E000000 #define AR_OBS_BUS_1_TX_STATE_S 25 /* MAC PCU dynamic MIMO power save */ #define AR_PCU_SMPS AR_MAC_PCU_OFFSET(MAC_PCU_DYM_MIMO_PWR_SAVE) #define AR_PCU_SMPS_MAC_CHAINMASK 0x00000001 // Use the Rx Chainmask of MAC's setting #define AR_PCU_SMPS_HW_CTRL_EN 0x00000002 // Enable hardware control of dynamic MIMO PS #define AR_PCU_SMPS_SW_CTRL_HPWR 0x00000004 // Software controlled High power chainmask setting #define AR_PCU_SMPS_LPWR_CHNMSK 0x00000070 // Low power setting of Rx Chainmask #define AR_PCU_SMPS_LPWR_CHNMSK_S 4 #define AR_PCU_SMPS_HPWR_CHNMSK 0x00000700 // High power setting of Rx Chainmask #define AR_PCU_SMPS_HPWR_CHNMSK_S 8 #define AR_PCU_SMPS_LPWR_CHNMSK_VAL 0x1 /* MAC PCU frame start time trigger for the AP's Downlink Traffic in TDMA mode */ #define AR_TDMA_TXSTARTTRIG_LSB AR_MAC_PCU_OFFSET(MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB) #define AR_TDMA_TXSTARTTRIG_MSB AR_MAC_PCU_OFFSET(MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB) /* MAC Time stamp of the last beacon received */ #define AR_LAST_TSTP AR_MAC_PCU_OFFSET(MAC_PCU_LAST_BEACON_TSF) /* MAC current NAV value */ #define AR_NAV AR_MAC_PCU_OFFSET(MAC_PCU_NAV) /* MAC RTS exchange success counter */ #define AR_RTS_OK AR_MAC_PCU_OFFSET(MAC_PCU_RTS_SUCCESS_CNT) /* MAC RTS exchange failure counter */ #define AR_RTS_FAIL AR_MAC_PCU_OFFSET(MAC_PCU_RTS_FAIL_CNT) /* MAC ACK failure counter */ #define AR_ACK_FAIL AR_MAC_PCU_OFFSET(MAC_PCU_ACK_FAIL_CNT) /* MAC FCS check failure counter */ #define AR_FCS_FAIL AR_MAC_PCU_OFFSET(MAC_PCU_FCS_FAIL_CNT) /* MAC Valid beacon value */ #define AR_BEACON_CNT AR_MAC_PCU_OFFSET(MAC_PCU_BEACON_CNT) /* MAC PCU tdma slot alert control */ #define AR_TDMA_SLOT_ALERT_CNTL AR_MAC_PCU_OFFSET(MAC_PCU_TDMA_SLOT_ALERT_CNTL) /* MAC PCU Basic MCS set for MCS 0 to 31 */ #define AR_BASIC_SET AR_MAC_PCU_OFFSET(MAC_PCU_BASIC_SET) #define ALL_RATE 0xff /* MAC_PCU_ _SEQ */ #define AR_MGMT_SEQ AR_MAC_PCU_OFFSET(MAC_PCU_MGMT_SEQ) #define AR_MGMT_SEQ_MIN 0xFFF /* sequence minimum value*/ #define AR_MGMT_SEQ_MIN_S 0 #define AR_MIN_HW_SEQ 0 #define AR_MGMT_SEQ_MAX 0xFFF0000 /* sequence maximum value*/ #define AR_MGMT_SEQ_MAX_S 16 #define AR_MAX_HW_SEQ 0xFF /*MAC PCU Key Cache Antenna 1 */ #define AR_TX_ANT_1 AR_MAC_PCU_OFFSET(MAC_PCU_TX_ANT_1) /*MAC PCU Key Cache Antenna 2 */ #define AR_TX_ANT_2 AR_MAC_PCU_OFFSET(MAC_PCU_TX_ANT_2) /*MAC PCU Key Cache Antenna 3 */ #define AR_TX_ANT_3 AR_MAC_PCU_OFFSET(MAC_PCU_TX_ANT_3) /*MAC PCU Key Cache Antenna 4 */ #define AR_TX_ANT_4 AR_MAC_PCU_OFFSET(MAC_PCU_TX_ANT_4) /* Extended range mode */ #define AR_XRMODE AR_MAC_PCU_OFFSET(MAC_PCU_XRMODE) /* Extended range mode delay */ #define AR_XRDEL AR_MAC_PCU_OFFSET(MAC_PCU_XRDEL) /* Extended range mode timeout */ #define AR_XRTO AR_MAC_PCU_OFFSET(MAC_PCU_XRTO) /* Extended range mode chirp */ #define AR_XRCRP AR_MAC_PCU_OFFSET(MAC_PCU_XRCRP) /* Extended range stomp */ #define AR_XRSTMP AR_MAC_PCU_OFFSET(MAC_PCU_XRSTMP) /* Enhanced sleep control 1 */ #define AR_SLEEP1 AR_MAC_PCU_OFFSET(MAC_PCU_SLP1) #define AR_SLEEP1_ASSUME_DTIM 0x00080000 // Assume DTIM on missed beacon #define AR_SLEEP1_CAB_TIMEOUT 0xFFE00000 // Cab timeout(TU) mask #define AR_SLEEP1_CAB_TIMEOUT_S 21 // Cab timeout(TU) shift /* Enhanced sleep control 2 */ #define AR_SLEEP2 AR_MAC_PCU_OFFSET(MAC_PCU_SLP2) #define AR_SLEEP2_BEACON_TIMEOUT 0xFFE00000 // Beacon timeout(TU) mask #define AR_SLEEP2_BEACON_TIMEOUT_S 21 // Beacon timeout(TU) shift /*MAC_PCU_SELF_GEN_DEFAULT*/ #define AR_SELFGEN AR_MAC_PCU_OFFSET(MAC_PCU_SELF_GEN_DEFAULT) #define AR_MMSS 0x00000007 #define AR_MMSS_S 0 #define AR_SELFGEN_MMSS_NO RESTRICTION 0 #define AR_SELFGEN_MMSS_ONEOVER4_us 1 #define AR_SELFGEN_MMSS_ONEOVER2_us 2 #define AR_SELFGEN_MMSS_ONE_us 3 #define AR_SELFGEN_MMSS_TWO_us 4 #define AR_SELFGEN_MMSS_FOUR_us 5 #define AR_SELFGEN_MMSS_EIGHT_us 6 #define AR_SELFGEN_MMSS_SIXTEEN_us 7 #define AR_CEC 0x00000018 #define AR_CEC_S 3 /* Although in original standard 0 is for 1 stream and 1 is for 2 stream */ /* due to H/W resaon, Here should set 1 for 1 stream and 2 for 2 stream */ #define AR_SELFGEN_CEC_ONE_SPACETIMESTREAM 1 #define AR_SELFGEN_CEC_TWO_SPACETIMESTREAM 2 /* BSSID mask lower 32 bits */ #define AR_BSSMSKL AR_MAC_PCU_OFFSET(MAC_PCU_ADDR1_MASK_L32) /* BSSID mask upper 16 bits */ #define AR_BSSMSKU AR_MAC_PCU_OFFSET(MAC_PCU_ADDR1_MASK_U16) /* Transmit power control for gen frames */ #define AR_TPC AR_MAC_PCU_OFFSET(MAC_PCU_TPC) #define AR_TPC_ACK 0x0000003f // ack frames mask #define AR_TPC_ACK_S 0x00 // ack frames shift #define AR_TPC_CTS 0x00003f00 // cts frames mask #define AR_TPC_CTS_S 0x08 // cts frames shift #define AR_TPC_CHIRP 0x003f0000 // chirp frames mask #define AR_TPC_CHIRP_S 16 // chirp frames shift #define AR_TPC_RPT 0x3f000000 // rpt frames mask #define AR_TPC_RPT_S 24 // rpt frames shift /* Profile count transmit frames */ #define AR_TFCNT AR_MAC_PCU_OFFSET(MAC_PCU_TX_FRAME_CNT) /* Profile count receive frames */ #define AR_RFCNT AR_MAC_PCU_OFFSET(MAC_PCU_RX_FRAME_CNT) /* Profile count receive clear */ #define AR_RCCNT AR_MAC_PCU_OFFSET(MAC_PCU_RX_CLEAR_CNT) /* Profile count cycle counter */ #define AR_CCCNT AR_MAC_PCU_OFFSET(MAC_PCU_CYCLE_CNT) /* Quiet time programming for TGh */ #define AR_QUIET1 AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1) #define AR_QUIET1_NEXT_QUIET_S 0 // TSF of next quiet period (TU) #define AR_QUIET1_NEXT_QUIET_M 0x0000ffff #define AR_QUIET1_QUIET_ENABLE 0x00010000 // Enable Quiet time operation #define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000 // ack/cts in quiet period #define AR_QUIET1_QUIET_ACK_CTS_ENABLE_S 17 #define AR_QUIET2 AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_2) #define AR_QUIET2_QUIET_PERIOD_S 0 // Periodicity of quiet period (TU) #define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff #define AR_QUIET2_QUIET_DUR_S 16 // quiet period (TU) #define AR_QUIET2_QUIET_DUR 0xffff0000 /* locate no_ack in qos */ #define AR_QOS_NO_ACK AR_MAC_PCU_OFFSET(MAC_PCU_QOS_NO_ACK) #define AR_QOS_NO_ACK_TWO_BIT 0x0000000f // 2 bit sentinel for no-ack #define AR_QOS_NO_ACK_TWO_BIT_S 0 #define AR_QOS_NO_ACK_BIT_OFF 0x00000070 // offset for no-ack #define AR_QOS_NO_ACK_BIT_OFF_S 4 #define AR_QOS_NO_ACK_BYTE_OFF 0x00000180 // from end of header #define AR_QOS_NO_ACK_BYTE_OFF_S 7 /* Phy errors to be filtered */ #define AR_PHY_ERR AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERROR_MASK) /* XXX validate! XXX */ #define AR_PHY_ERR_DCHIRP 0x00000008 // Bit 3 enables double chirp #define AR_PHY_ERR_RADAR 0x00000020 // Bit 5 is Radar signal #define AR_PHY_ERR_OFDM_TIMING 0x00020000 // Bit 17 is AH_FALSE detect for OFDM #define AR_PHY_ERR_CCK_TIMING 0x02000000 // Bit 25 is AH_FALSE detect for CCK /* MAC PCU extended range latency */ #define AR_XRLAT AR_MAC_PCU_OFFSET(MAC_PCU_XRLAT) /* MAC PCU Receive Buffer settings */ #define AR_RXFIFO_CFG AR_MAC_PCU_OFFSET(MAC_PCU_RXBUF) #define AR_RXFIFO_CFG_REG_RD_ENA_S 11 #define AR_RXFIFO_CFG_REG_RD_ENA (0x1 << AR_RXFIFO_CFG_REG_RD_ENA_S) /* MAC PCU QoS control */ #define AR_MIC_QOS_CONTROL AR_MAC_PCU_OFFSET(MAC_PCU_MIC_QOS_CONTROL) /* MAC PCU Michael QoS select */ #define AR_MIC_QOS_SELECT AR_MAC_PCU_OFFSET(MAC_PCU_MIC_QOS_SELECT) /* PCU Miscellaneous Mode */ #define AR_PCU_MISC AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE) #define AR_PCU_FORCE_BSSID_MATCH 0x00000001 // force bssid to match #define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 // tx/rx mic key are together #define AR_PCU_TX_ADD_TSF 0x00000008 // add tx_tsf + int_tsf #define AR_PCU_CCK_SIFS_MODE 0x00000010 // assume 11b sifs programmed #define AR_PCU_RX_ANT_UPDT 0x00000800 // KC_RX_ANT_UPDATE #define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 // enforce txop / tbtt #define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 // count bmiss's when sleeping #define AR_PCU_BUG_12306_FIX_ENA 0x00020000 // use rx_clear to count sifs #define AR_PCU_FORCE_QUIET_COLL 0x00040000 // kill xmit for channel change #define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 #define AR_PCU_BT_ANT_PREVENT_RX_S 20 #define AR_PCU_TBTT_PROTECT 0x00200000 // no xmit upto tbtt + 20 uS #define AR_PCU_CLEAR_VMF 0x01000000 // clear vmf mode (fast cc) #define AR_PCU_CLEAR_BA_VALID 0x04000000 // clear ba state #define AR_PCU_SEL_EVM 0x08000000 // select EVM data or PLCP header #define AR_PCU_ALWAYS_PERFORM_KEYSEARCH 0x10000000 /* always perform key search */ /* count of filtered ofdm */ #define AR_FILT_OFDM AR_MAC_PCU_OFFSET(MAC_PCU_FILTER_OFDM_CNT) #define AR_FILT_OFDM_COUNT 0x00FFFFFF // count of filtered ofdm /* count of filtered cck */ #define AR_FILT_CCK AR_MAC_PCU_OFFSET(MAC_PCU_FILTER_CCK_CNT) #define AR_FILT_CCK_COUNT 0x00FFFFFF // count of filtered cck /* MAC PCU PHY error counter 1 */ #define AR_PHY_ERR_1 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_1) #define AR_PHY_ERR_1_COUNT 0x00FFFFFF // phy errs that pass mask_1 /* MAC PCU PHY error mask 1 */ #define AR_PHY_ERR_MASK_1 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_1_MASK) /* MAC PCU PHY error counter 2 */ #define AR_PHY_ERR_2 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_2) #define AR_PHY_ERR_2_COUNT 0x00FFFFFF // phy errs that pass mask_2 /* MAC PCU PHY error mask 2 */ #define AR_PHY_ERR_MASK_2 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_2_MASK) #define AR_PHY_COUNTMAX (3 << 22) // Max counted before intr #define AR_MIBCNT_INTRMASK (3 << 22) // Mask top 2 bits of counters /* interrupt if rx_tsf-int_tsf */ #define AR_TSFOOR_THRESHOLD AR_MAC_PCU_OFFSET(MAC_PCU_TSF_THRESHOLD) #define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF // field width /* MAC PCU PHY error counter 3 */ #define AR_PHY_ERR_3 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_3) #define AR_PHY_ERR_3_COUNT 0x00FFFFFF // phy errs that pass mask_3 /* MAC PCU PHY error mask 3 */ #define AR_PHY_ERR_MASK_3 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_3_MASK) /* Bluetooth coexistance mode */ #define AR_BT_COEX_MODE AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_MODE) #define AR_BT_TIME_EXTEND 0x000000ff #define AR_BT_TIME_EXTEND_S 0 #define AR_BT_TXSTATE_EXTEND 0x00000100 #define AR_BT_TXSTATE_EXTEND_S 8 #define AR_BT_TX_FRAME_EXTEND 0x00000200 #define AR_BT_TX_FRAME_EXTEND_S 9 #define AR_BT_MODE 0x00000c00 #define AR_BT_MODE_S 10 #define AR_BT_QUIET 0x00001000 #define AR_BT_QUIET_S 12 #define AR_BT_QCU_THRESH 0x0001e000 #define AR_BT_QCU_THRESH_S 13 #define AR_BT_RX_CLEAR_POLARITY 0x00020000 #define AR_BT_RX_CLEAR_POLARITY_S 17 #define AR_BT_PRIORITY_TIME 0x00fc0000 #define AR_BT_PRIORITY_TIME_S 18 #define AR_BT_FIRST_SLOT_TIME 0xff000000 #define AR_BT_FIRST_SLOT_TIME_S 24 /* BlueTooth coexistance WLAN weights */ #define AR_BT_COEX_WL_WEIGHTS0 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_WL_WEIGHTS0) #define AR_BT_BT_WGHT 0x0000ffff #define AR_BT_BT_WGHT_S 0 #define AR_BT_WL_WGHT 0xffff0000 #define AR_BT_WL_WGHT_S 16 /* HCF timeout: Slotted behavior */ #define AR_HCFTO AR_MAC_PCU_OFFSET(MAC_PCU_HCF_TIMEOUT) /* BlueTooth mode 2: Slotted behavior */ #define AR_BT_COEX_MODE2 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_MODE2) #define AR_BT_BCN_MISS_THRESH 0x000000ff #define AR_BT_BCN_MISS_THRESH_S 0 #define AR_BT_BCN_MISS_CNT 0x0000ff00 #define AR_BT_BCN_MISS_CNT_S 8 #define AR_BT_HOLD_RX_CLEAR 0x00010000 #define AR_BT_HOLD_RX_CLEAR_S 16 #define AR_BT_SLEEP_ALLOW_BT 0x00020000 #define AR_BT_SLEEP_ALLOW_BT_S 17 #define AR_BT_PROTECT_AFTER_WAKE 0x00080000 #define AR_BT_PROTECT_AFTER_WAKE_S 19 #define AR_BT_DISABLE_BT_ANT 0x00100000 #define AR_BT_DISABLE_BT_ANT_S 20 #define AR_BT_QUIET_2_WIRE 0x00200000 #define AR_BT_QUIET_2_WIRE_S 21 #define AR_BT_WL_ACTIVE_MODE 0x00c00000 #define AR_BT_WL_ACTIVE_MODE_S 22 #define AR_BT_WL_TXRX_SEPARATE 0x01000000 #define AR_BT_WL_TXRX_SEPARATE_S 24 #define AR_BT_RS_DISCARD_EXTEND 0x02000000 #define AR_BT_RS_DISCARD_EXTEND_S 25 #define AR_BT_TSF_BT_ACTIVE_CTRL 0x0c000000 #define AR_BT_TSF_BT_ACTIVE_CTRL_S 26 #define AR_BT_TSF_BT_PRIORITY_CTRL 0x30000000 #define AR_BT_TSF_BT_PRIORITY_CTRL_S 28 #define AR_BT_INTERRUPT_ENABLE 0x40000000 #define AR_BT_INTERRUPT_ENABLE_S 30 #define AR_BT_PHY_ERR_BT_COLL_ENABLE 0x80000000 #define AR_BT_PHY_ERR_BT_COLL_ENABLE_S 31 /* Generic Timers 2 */ #define AR_GEN_TIMERS2_0 AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS2) #define AR_GEN_TIMERS2_NEXT(_i) (AR_GEN_TIMERS2_0 + ((_i)<<2)) #define AR_GEN_TIMERS2_PERIOD(_i) (AR_GEN_TIMERS2_NEXT(8) + ((_i)<<2)) #define AR_GEN_TIMERS2_0_NEXT AR_GEN_TIMERS2_NEXT(0) #define AR_GEN_TIMERS2_1_NEXT AR_GEN_TIMERS2_NEXT(1) #define AR_GEN_TIMERS2_2_NEXT AR_GEN_TIMERS2_NEXT(2) #define AR_GEN_TIMERS2_3_NEXT AR_GEN_TIMERS2_NEXT(3) #define AR_GEN_TIMERS2_4_NEXT AR_GEN_TIMERS2_NEXT(4) #define AR_GEN_TIMERS2_5_NEXT AR_GEN_TIMERS2_NEXT(5) #define AR_GEN_TIMERS2_6_NEXT AR_GEN_TIMERS2_NEXT(6) #define AR_GEN_TIMERS2_7_NEXT AR_GEN_TIMERS2_NEXT(7) #define AR_GEN_TIMERS2_0_PERIOD AR_GEN_TIMERS2_PERIOD(0) #define AR_GEN_TIMERS2_1_PERIOD AR_GEN_TIMERS2_PERIOD(1) #define AR_GEN_TIMERS2_2_PERIOD AR_GEN_TIMERS2_PERIOD(2) #define AR_GEN_TIMERS2_3_PERIOD AR_GEN_TIMERS2_PERIOD(3) #define AR_GEN_TIMERS2_4_PERIOD AR_GEN_TIMERS2_PERIOD(4) #define AR_GEN_TIMERS2_5_PERIOD AR_GEN_TIMERS2_PERIOD(5) #define AR_GEN_TIMERS2_6_PERIOD AR_GEN_TIMERS2_PERIOD(6) #define AR_GEN_TIMERS2_7_PERIOD AR_GEN_TIMERS2_PERIOD(7) #define AR_GEN_TIMER_BANK_1_LEN 8 #define AR_FIRST_NDP_TIMER 7 #define AR_NUM_GEN_TIMERS 16 #define AR_GEN_TIMER_RESERVED 8 /* Generic Timers 2 Mode */ #define AR_GEN_TIMERS2_MODE AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS2_MODE) /* BlueTooth coexistance WLAN weights 1 */ #define AR_BT_COEX_WL_WEIGHTS1 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_WL_WEIGHTS1) /* BlueTooth Coexistence TSF Snapshot for BT_ACTIVE */ #define AR_BT_TSF_ACTIVE AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE) /* BlueTooth Coexistence TSF Snapshot for BT_PRIORITY */ #define AR_BT_TSF_PRIORITY AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY) /* SIFS, TX latency and ACK shift */ #define AR_TXSIFS AR_MAC_PCU_OFFSET(MAC_PCU_TXSIFS) #define AR_TXSIFS_TIME 0x000000FF // uS in SIFS #define AR_TXSIFS_TX_LATENCY 0x00000F00 // uS for transmission thru bb #define AR_TXSIFS_TX_LATENCY_S 8 #define AR_TXSIFS_ACK_SHIFT 0x00007000 // chan width for ack #define AR_TXSIFS_ACK_SHIFT_S 12 /* BlueTooth mode 3 */ #define AR_BT_COEX_MODE3 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_MODE3) /* TXOP for legacy non-qos */ #define AR_TXOP_X AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_X) #define AR_TXOP_X_VAL 0x000000FF /* TXOP for TID 0 to 3 */ #define AR_TXOP_0_3 AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_0_3) /* TXOP for TID 4 to 7 */ #define AR_TXOP_4_7 AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_4_7) /* TXOP for TID 8 to 11 */ #define AR_TXOP_8_11 AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_8_11) /* TXOP for TID 12 to 15 */ #define AR_TXOP_12_15 AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_12_15) /* Generic Timers */ #define AR_GEN_TIMERS_0 AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS) #define AR_GEN_TIMERS(_i) (AR_GEN_TIMERS_0 + ((_i)<<2)) /* generic timers based on tsf - all uS */ #define AR_NEXT_TBTT_TIMER AR_GEN_TIMERS(0) #define AR_NEXT_DMA_BEACON_ALERT AR_GEN_TIMERS(1) #define AR_NEXT_SWBA AR_GEN_TIMERS(2) #define AR_NEXT_HCF AR_GEN_TIMERS(3) #define AR_NEXT_TIM AR_GEN_TIMERS(4) #define AR_NEXT_DTIM AR_GEN_TIMERS(5) #define AR_NEXT_QUIET_TIMER AR_GEN_TIMERS(6) #define AR_NEXT_NDP_TIMER AR_GEN_TIMERS(7) #define AR_BEACON_PERIOD AR_GEN_TIMERS(8) #define AR_DMA_BEACON_PERIOD AR_GEN_TIMERS(9) #define AR_SWBA_PERIOD AR_GEN_TIMERS(10) #define AR_HCF_PERIOD AR_GEN_TIMERS(11) #define AR_TIM_PERIOD AR_GEN_TIMERS(12) #define AR_DTIM_PERIOD AR_GEN_TIMERS(13) #define AR_QUIET_PERIOD AR_GEN_TIMERS(14) #define AR_NDP_PERIOD AR_GEN_TIMERS(15) /* Generic Timers Mode */ #define AR_TIMER_MODE AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS_MODE) #define AR_TBTT_TIMER_EN 0x00000001 #define AR_DBA_TIMER_EN 0x00000002 #define AR_SWBA_TIMER_EN 0x00000004 #define AR_HCF_TIMER_EN 0x00000008 #define AR_TIM_TIMER_EN 0x00000010 #define AR_DTIM_TIMER_EN 0x00000020 #define AR_QUIET_TIMER_EN 0x00000040 #define AR_NDP_TIMER_EN 0x00000080 #define AR_TIMER_OVERFLOW_INDEX 0x00000700 #define AR_TIMER_OVERFLOW_INDEX_S 8 #define AR_TIMER_THRESH 0xFFFFF000 #define AR_TIMER_THRESH_S 12 #define AR_SLP32_MODE AR_MAC_PCU_OFFSET(MAC_PCU_SLP32_MODE) #define AR_SLP32_HALF_CLK_LATENCY 0x000FFFFF // rising <-> falling edge #define AR_SLP32_ENA 0x00100000 #define AR_SLP32_TSF_WRITE_STATUS 0x00200000 // tsf update in progress #define AR_SLP32_WAKE AR_MAC_PCU_OFFSET(MAC_PCU_SLP32_WAKE) #define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF // time to wake crystal #define AR_SLP32_INC AR_MAC_PCU_OFFSET(MAC_PCU_SLP32_INC) #define AR_SLP32_TST_INC 0x000FFFFF /* Sleep MIB cycle count 32kHz cycles for which mac is asleep */ #define AR_SLP_CNT AR_MAC_PCU_OFFSET(MAC_PCU_SLP_MIB1) #define AR_SLP_CYCLE_CNT 0x8254 // absolute number of 32kHz cycles /* Sleep MIB cycle count 2 */ #define AR_SLP_MIB2 AR_MAC_PCU_OFFSET(MAC_PCU_SLP_MIB2) /* Sleep MIB control status */ #define AR_SLP_MIB_CTRL AR_MAC_PCU_OFFSET(MAC_PCU_SLP_MIB3) #define AR_SLP_MIB_CLEAR 0x00000001 // clear pending #define AR_SLP_MIB_PENDING 0x00000002 // clear counters //#ifdef AR9300_EMULATION // MAC trace buffer registers (emulation only) #define AR_MAC_PCU_LOGIC_ANALYZER AR_MAC_PCU_OFFSET(MAC_PCU_LOGIC_ANALYZER) #define AR_MAC_PCU_LOGIC_ANALYZER_CTL 0x0000000F #define AR_MAC_PCU_LOGIC_ANALYZER_HOLD 0x00000001 #define AR_MAC_PCU_LOGIC_ANALYZER_CLEAR 0x00000002 #define AR_MAC_PCU_LOGIC_ANALYZER_STATE 0x00000004 #define AR_MAC_PCU_LOGIC_ANALYZER_ENABLE 0x00000008 #define AR_MAC_PCU_LOGIC_ANALYZER_QCU_SEL 0x000000F0 #define AR_MAC_PCU_LOGIC_ANALYZER_QCU_SEL_S 4 #define AR_MAC_PCU_LOGIC_ANALYZER_INT_ADDR 0x0003FF00 #define AR_MAC_PCU_LOGIC_ANALYZER_INT_ADDR_S 8 #define AR_MAC_PCU_LOGIC_ANALYZER_DIAG_MODE 0xFFFC0000 #define AR_MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_S 18 #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20614 0x00040000 #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000 #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20803 0x40000000 #define AR_MAC_PCU_LOGIC_ANALYZER_PSTABUG75996 0x9d500010 #define AR_MAC_PCU_LOGIC_ANALYZER_VC_MODE 0x9d400010 #define AR_MAC_PCU_LOGIC_ANALYZER_32L AR_MAC_PCU_OFFSET(MAC_PCU_LOGIC_ANALYZER_32L) #define AR_MAC_PCU_LOGIC_ANALYZER_16U AR_MAC_PCU_OFFSET(MAC_PCU_LOGIC_ANALYZER_16U) #define AR_MAC_PCU_TRACE_REG_START 0xE000 #define AR_MAC_PCU_TRACE_REG_END 0xFFFC #define AR_MAC_PCU_TRACE_BUFFER_LENGTH (AR_MAC_PCU_TRACE_REG_END - AR_MAC_PCU_TRACE_REG_START + sizeof(uint32_t)) //#endif // AR9300_EMULATION /* MAC PCU global mode register */ #define AR_2040_MODE AR_MAC_PCU_OFFSET(MAC_PCU_20_40_MODE) #define AR_2040_JOINED_RX_CLEAR 0x00000001 // use ctl + ext rx_clear for cca /* MAC PCU H transfer timeout register */ #define AR_H_XFER_TIMEOUT AR_MAC_PCU_OFFSET(MAC_PCU_H_XFER_TIMEOUT) #define AR_EXBF_IMMDIATE_RESP 0x00000040 #define AR_EXBF_NOACK_NO_RPT 0x00000100 #define AR_H_XFER_TIMEOUT_COUNT 0xf #define AR_H_XFER_TIMEOUT_COUNT_S 0 /* * Additional cycle counter. See also AR_CCCNT * extension channel rx clear count * counts number of cycles rx_clear (ext) is low (i.e. busy) * when the MAC is not actively transmitting/receiving */ #define AR_EXTRCCNT AR_MAC_PCU_OFFSET(MAC_PCU_RX_CLEAR_DIFF_CNT) /* antenna mask for self generated files */ #define AR_SELFGEN_MASK AR_MAC_PCU_OFFSET(MAC_PCU_SELF_GEN_ANTENNA_MASK) /* control registers for block BA control fields */ #define AR_BA_BAR_CONTROL AR_MAC_PCU_OFFSET(MAC_PCU_BA_BAR_CONTROL) /* legacy PLCP spoof */ #define AR_LEG_PLCP_SPOOF AR_MAC_PCU_OFFSET(MAC_PCU_LEGACY_PLCP_SPOOF) /* PHY error mask and EIFS mask continued */ #define AR_PHY_ERR_MASK_CONT AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERROR_MASK_CONT) /* MAC PCU transmit timer */ #define AR_TX_TIMER AR_MAC_PCU_OFFSET(MAC_PCU_TX_TIMER) /* MAC PCU transmit buffer control */ #define AR_PCU_TXBUF_CTRL AR_MAC_PCU_OFFSET(MAC_PCU_TXBUF_CTRL) #define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF #define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 /* * MAC PCU miscellaneous mode 2 * WAR flags for various bugs, see mac_pcu_reg documentation. */ #define AR_PCU_MISC_MODE2 AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE2) #define AR_PCU_MISC_MODE2_BUG_21532_ENABLE 0x00000001 #define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 /* Decrypt MGT frames using MFP method */ #define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 /* Don't decrypt MGT frames at all */ #define AR_BUG_58603_FIX_ENABLE 0x00000008 /* Enable fix for bug 58603. This allows * the use of AR_AGG_WEP_ENABLE. */ #define AR_PCU_MISC_MODE2_PROM_VC_MODE 0xa148103b /* Enable promiscous in azimuth mode */ #define AR_PCU_MISC_MODE2_RESERVED 0x00000038 #define AR_ADHOC_MCAST_KEYID_ENABLE 0x00000040 /* This bit enables the Multicast search * based on both MAC Address and Key ID. * If bit is 0, then Multicast search is * based on MAC address only. * For Merlin and above only. */ #define AR_PCU_MISC_MODE2_CFP_IGNORE 0x00000080 #define AR_PCU_MISC_MODE2_MGMT_QOS 0x0000FF00 #define AR_PCU_MISC_MODE2_MGMT_QOS_S 8 #define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION 0x00010000 #define AR_AGG_WEP_ENABLE 0x00020000 /* This field enables AGG_WEP feature, * when it is enable, AGG_WEP would takes * charge of the encryption interface of * pcu_txsm. */ #define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 #define AR_PCU_MISC_MODE2_PROXY_STA 0x01000000 /* see EV 75996 */ #define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 #define AR_DECOUPLE_DECRYPTION 0x08000000 #define AR_PCU_MISC_MODE2_RESERVED2 0xFFFE0000 /* MAC PCU Alternate AES QoS mute mask */ #define AR_ALT_AES_MUTE_MASK AR_MAC_PCU_OFFSET(MAC_PCU_ALT_AES_MUTE_MASK) /* Async Fifo registers - debug only */ #define AR_ASYNC_FIFO_1 AR_MAC_PCU_OFFSET(ASYNC_FIFO_REG1) #define AR_ASYNC_FIFO_2 AR_MAC_PCU_OFFSET(ASYNC_FIFO_REG2) #define AR_ASYNC_FIFO_3 AR_MAC_PCU_OFFSET(ASYNC_FIFO_REG3) /* Maps the 16 user priority TID values to Access categories */ #define AR_TID_TO_AC_MAP AR_MAC_PCU_OFFSET(MAC_PCU_TID_TO_AC) /* High Priority Queue Control */ #define AR_HP_Q_CONTROL AR_MAC_PCU_OFFSET(MAC_PCU_HP_QUEUE) /* Rx High Priority Queue Control */ #define AR_HPQ_CONTROL AR_MAC_PCU_OFFSET(MAC_PCU_HP_QUEUE) #define AR_HPQ_ENABLE 0x00000001 #define AR_HPQ_MASK_BE 0x00000002 #define AR_HPQ_MASK_BK 0x00000004 #define AR_HPQ_MASK_VI 0x00000008 #define AR_HPQ_MASK_VO 0x00000010 #define AR_HPQ_UAPSD 0x00000020 #define AR_HPQ_FRAME_FILTER_0 0x00000040 #define AR_HPQ_FRAME_BSSID_MATCH_0 0x00000080 #define AR_HPQ_UAPSD_TRIGGER_EN 0x00100000 #define AR_BT_COEX_BT_WEIGHTS0 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_BT_WEIGHTS0) #define AR_BT_COEX_BT_WEIGHTS1 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_BT_WEIGHTS1) #define AR_BT_COEX_BT_WEIGHTS2 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_BT_WEIGHTS2) #define AR_BT_COEX_BT_WEIGHTS3 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_BT_WEIGHTS3) #define AR_AGC_SATURATION_CNT0 AR_MAC_PCU_OFFSET(MAC_PCU_AGC_SATURATION_CNT0) #define AR_AGC_SATURATION_CNT1 AR_MAC_PCU_OFFSET(MAC_PCU_AGC_SATURATION_CNT1) #define AR_AGC_SATURATION_CNT2 AR_MAC_PCU_OFFSET(MAC_PCU_AGC_SATURATION_CNT2) /* Hardware beacon processing */ #define AR_HWBCNPROC1 AR_MAC_PCU_OFFSET(MAC_PCU_HW_BCN_PROC1) #define AR_HWBCNPROC1_CRC_ENABLE 0x00000001 /* Enable hw beacon processing */ #define AR_HWBCNPROC1_RESET_CRC 0x00000002 /* Reset the last beacon CRC calculated */ #define AR_HWBCNPROC1_EXCLUDE_BCN_INTVL 0x00000004 /* Exclude Beacon interval in CRC calculation */ #define AR_HWBCNPROC1_EXCLUDE_CAP_INFO 0x00000008 /* Exclude Beacon capability information in CRC calculation */ #define AR_HWBCNPROC1_EXCLUDE_TIM_ELM 0x00000010 /* Exclude Beacon TIM element in CRC calculation */ #define AR_HWBCNPROC1_EXCLUDE_ELM0 0x00000020 /* Exclude element ID ELM0 in CRC calculation */ #define AR_HWBCNPROC1_EXCLUDE_ELM1 0x00000040 /* Exclude element ID ELM1 in CRC calculation */ #define AR_HWBCNPROC1_EXCLUDE_ELM2 0x00000080 /* Exclude element ID ELM2 in CRC calculation */ #define AR_HWBCNPROC1_ELM0_ID 0x0000FF00 /* Element ID 0 */ #define AR_HWBCNPROC1_ELM0_ID_S 8 #define AR_HWBCNPROC1_ELM1_ID 0x00FF0000 /* Element ID 1 */ #define AR_HWBCNPROC1_ELM1_ID_S 16 #define AR_HWBCNPROC1_ELM2_ID 0xFF000000 /* Element ID 2 */ #define AR_HWBCNPROC1_ELM2_ID_S 24 #define AR_HWBCNPROC2 AR_MAC_PCU_OFFSET(MAC_PCU_HW_BCN_PROC2) #define AR_HWBCNPROC2_FILTER_INTERVAL_ENABLE 0x00000001 /* Enable filtering beacons based on filter interval */ #define AR_HWBCNPROC2_RESET_INTERVAL 0x00000002 /* Reset internal interval counter interval */ #define AR_HWBCNPROC2_EXCLUDE_ELM3 0x00000004 /* Exclude element ID ELM3 in CRC calculation */ #define AR_HWBCNPROC2_RSVD 0x000000F8 /* reserved */ #define AR_HWBCNPROC2_FILTER_INTERVAL 0x0000FF00 /* Filter interval for beacons */ #define AR_HWBCNPROC2_FILTER_INTERVAL_S 8 #define AR_HWBCNPROC2_ELM3_ID 0x00FF0000 /* Element ID 3 */ #define AR_HWBCNPROC2_ELM3_ID_S 16 #define AR_HWBCNPROC2_RSVD2 0xFF000000 /* reserved */ #define AR_MAC_PCU_MISC_MODE3 AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE3) #define AR_BUG_61936_FIX_ENABLE 0x00000040 /* EV61936 - rx descriptor corruption */ #define AR_TIME_BASED_DISCARD_EN 0x80000000 #define AR_TIME_BASED_DISCARD_EN_S 31 #define AR_MAC_PCU_GEN_TIMER_TSF_SEL AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS_TSF_SEL) #define AR_MAC_PCU_TBD_FILTER AR_MAC_PCU_OFFSET(MAC_PCU_TBD_FILTER) #define AR_MAC_PCU_USE_WBTIMER_TX_TS 0x00000001 #define AR_MAC_PCU_USE_WBTIMER_TX_TS_S 0 #define AR_MAC_PCU_USE_WBTIMER_RX_TS 0x00000002 #define AR_MAC_PCU_USE_WBTIMER_RX_TS_S 1 #define AR_TXBUF_BA AR_MAC_PCU_OFFSET(MAC_PCU_TXBUF_BA) /* MAC Key Cache */ #define AR_KEYTABLE_0 AR_MAC_PCU_OFFSET(MAC_PCU_KEY_CACHE) #define AR_KEYTABLE(_n) (AR_KEYTABLE_0 + ((_n)*32)) #define AR_KEY_CACHE_SIZE 128 #define AR_RSVD_KEYTABLE_ENTRIES 4 #define AR_KEY_TYPE 0x00000007 // MAC Key Type Mask #define AR_KEYTABLE_TYPE_40 0x00000000 /* WEP 40 bit key */ #define AR_KEYTABLE_TYPE_104 0x00000001 /* WEP 104 bit key */ #define AR_KEYTABLE_TYPE_128 0x00000003 /* WEP 128 bit key */ #define AR_KEYTABLE_TYPE_TKIP 0x00000004 /* TKIP and Michael */ #define AR_KEYTABLE_TYPE_AES 0x00000005 /* AES/OCB 128 bit key */ #define AR_KEYTABLE_TYPE_CCM 0x00000006 /* AES/CCM 128 bit key */ #define AR_KEYTABLE_TYPE_CLR 0x00000007 /* no encryption */ #define AR_KEYTABLE_ANT 0x00000008 /* previous transmit antenna */ #define AR_KEYTABLE_UAPSD 0x000001E0 /* UAPSD AC mask */ #define AR_KEYTABLE_UAPSD_S 5 #define AR_KEYTABLE_PWRMGT 0x00000200 /* hw managed PowerMgt bit */ #define AR_KEYTABLE_MMSS 0x00001c00 /* remote's MMSS*/ #define AR_KEYTABLE_MMSS_S 10 #define AR_KEYTABLE_CEC 0x00006000 /* remote's CEC*/ #define AR_KEYTABLE_CEC_S 13 #define AR_KEYTABLE_STAGGED 0x00010000 /* remote's stagged sounding*/ #define AR_KEYTABLE_STAGGED_S 16 #define AR_KEYTABLE_VALID 0x00008000 /* key and MAC address valid */ #define AR_KEYTABLE_KEY0(_n) (AR_KEYTABLE(_n) + 0) /* key bit 0-31 */ #define AR_KEYTABLE_KEY1(_n) (AR_KEYTABLE(_n) + 4) /* key bit 32-47 */ #define AR_KEYTABLE_KEY2(_n) (AR_KEYTABLE(_n) + 8) /* key bit 48-79 */ #define AR_KEYTABLE_KEY3(_n) (AR_KEYTABLE(_n) + 12) /* key bit 80-95 */ #define AR_KEYTABLE_KEY4(_n) (AR_KEYTABLE(_n) + 16) /* key bit 96-127 */ #define AR_KEYTABLE_TYPE(_n) (AR_KEYTABLE(_n) + 20) /* key type */ #define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) /* MAC address 1-32 */ #define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) /* MAC address 33-47 */ #define AR_KEYTABLE_DIR_ACK_BIT 0x00000010 /* Directed ACK bit */ /* * MAC WoW Registers. */ #define AR_WOW_PATTERN_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW1) #define AR_WOW_PAT_BACKOFF 0x00000004 #define AR_WOW_BACK_OFF_SHIFT(x) ((x & 0xf) << 27) /* in usecs */ #define AR_WOW_MAC_INTR_EN 0x00040000 #define AR_WOW_MAGIC_EN 0x00010000 #define AR_WOW_PATTERN_EN(x) ((x & 0xff) << 0) #define AR_WOW_PATTERN_FOUND_SHIFT 8 #define AR_WOW_PATTERN_FOUND(x) (x & (0xff << AR_WOW_PATTERN_FOUND_SHIFT)) #define AR_WOW_PATTERN_FOUND_MASK ((0xff) << AR_WOW_PATTERN_FOUND_SHIFT) #define AR_WOW_MAGIC_PAT_FOUND 0x00020000 #define AR_WOW_MAC_INTR 0x00080000 #define AR_WOW_KEEP_ALIVE_FAIL 0x00100000 #define AR_WOW_BEACON_FAIL 0x00200000 #define AR_WOW_COUNT_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW2) #define AR_WOW_AIFS_CNT(x) ((x & 0xff) << 0) #define AR_WOW_SLOT_CNT(x) ((x & 0xff) << 8) #define AR_WOW_KEEP_ALIVE_CNT(x) ((x & 0xff) << 16) /* * Default values for Wow Configuration for backoff, aifs, slot, keep-alive, etc. * to be programmed into various registers. */ #define AR_WOW_CNT_AIFS_CNT 0x00000022 // AR_WOW_COUNT_REG #define AR_WOW_CNT_SLOT_CNT 0x00000009 // AR_WOW_COUNT_REG /* * Keepalive count applicable for Merlin 2.0 and above. */ #define AR_WOW_CNT_KA_CNT 0x00000008 // AR_WOW_COUNT_REG #define AR_WOW_BCN_EN_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW3_BEACON_FAIL) #define AR_WOW_BEACON_FAIL_EN 0x00000001 #define AR_WOW_BCN_TIMO_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW3_BEACON) #define AR_WOW_BEACON_TIMO 0x40000000 /* Valid if BCN_EN is set */ #define AR_WOW_BEACON_TIMO_MAX 0xFFFFFFFF /* Max. value for Beacon Timeout */ #define AR_WOW_KEEP_ALIVE_TIMO_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW3_KEEP_ALIVE) #define AR_WOW_KEEP_ALIVE_TIMO 0x00007A12 #define AR_WOW_KEEP_ALIVE_NEVER 0xFFFFFFFF #define AR_WOW_KEEP_ALIVE_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW_KA) #define AR_WOW_KEEP_ALIVE_AUTO_DIS 0x00000001 #define AR_WOW_KEEP_ALIVE_FAIL_DIS 0x00000002 #define AR_WOW_US_SCALAR_REG AR_MAC_PCU_OFFSET(PCU_1US) #define AR_WOW_KEEP_ALIVE_DELAY_REG AR_MAC_PCU_OFFSET(PCU_KA) #define AR_WOW_KEEP_ALIVE_DELAY 0x000003E8 // 1 msec #define AR_WOW_PATTERN_MATCH_REG AR_MAC_PCU_OFFSET(WOW_EXACT) #define AR_WOW_PAT_END_OF_PKT(x) ((x & 0xf) << 0) #define AR_WOW_PAT_OFF_MATCH(x) ((x & 0xf) << 8) #define AR_WOW_PATTERN_MATCH_REG_2 AR_MAC_PCU_OFFSET(WOW2_EXACT) #define AR_WOW_PATTERN_OFF1_REG AR_MAC_PCU_OFFSET(PCU_WOW4) /* Pattern bytes 0 -> 3 */ #define AR_WOW_PATTERN_OFF2_REG AR_MAC_PCU_OFFSET(PCU_WOW5) /* Pattern bytes 4 -> 7 */ #define AR_WOW_PATTERN_OFF3_REG AR_MAC_PCU_OFFSET(PCU_WOW6) /* Pattern bytes 8 -> 11 */ #define AR_WOW_PATTERN_OFF4_REG AR_MAC_PCU_OFFSET(PCU_WOW7) /* Pattern bytes 12 -> 15 */ /* start address of the frame in RxBUF */ #define AR_WOW_RXBUF_START_ADDR AR_MAC_PCU_OFFSET(MAC_PCU_WOW6) /* Pattern detect and enable bits */ #define AR_WOW_PATTERN_DETECT_ENABLE AR_MAC_PCU_OFFSET(MAC_PCU_WOW4) /* Rx Abort Enable */ #define AR_WOW_RX_ABORT_ENABLE AR_MAC_PCU_OFFSET(MAC_PCU_WOW5) /* PHY error counter 1, 2, and 3 mask continued */ #define AR_PHY_ERR_CNT_MASK_CONT AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_MASK_CONT) /* AZIMUTH mode reg can be used for proxySTA */ #define AR_AZIMUTH_MODE AR_MAC_PCU_OFFSET(MAC_PCU_AZIMUTH_MODE) #define AR_AZIMUTH_KEY_SEARCH_AD1 0x00000002 #define AR_AZIMUTH_CTS_MATCH_TX_AD2 0x00000040 #define AR_AZIMUTH_BA_USES_AD1 0x00000080 #define AR_AZIMUTH_FILTER_PASS_HOLD 0x00000200 /* Length of Pattern Match for Pattern */ #define AR_WOW_LENGTH1_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW_LENGTH1) #define AR_WOW_LENGTH2_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW_LENGTH2) #define AR_WOW_LENGTH3_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW_LENGTH3) #define AR_WOW_LENGTH4_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW_LENGTH4) #define AR_LOC_CTL_REG AR_MAC_PCU_OFFSET(MAC_PCU_LOCATION_MODE_CONTROL) #define AR_LOC_TIMER_REG AR_MAC_PCU_OFFSET(MAC_PCU_LOCATION_MODE_TIMER) #define AR_LOC_CTL_REG_FS 0x1 /* Register to enable pattern match for less than 256 bytes packets */ #define AR_WOW_PATTERN_MATCH_LT_256B_REG AR_MAC_PCU_OFFSET(WOW_PATTERN_MATCH_LESS_THAN_256_BYTES) #define AR_WOW_STATUS(x) (x & (AR_WOW_PATTERN_FOUND_MASK | AR_WOW_MAGIC_PAT_FOUND | \ AR_WOW_KEEP_ALIVE_FAIL | AR_WOW_BEACON_FAIL)) #define AR_WOW_CLEAR_EVENTS(x) (x & ~(AR_WOW_PATTERN_EN(0xff) | \ AR_WOW_MAGIC_EN | AR_WOW_MAC_INTR_EN | AR_WOW_BEACON_FAIL | \ AR_WOW_KEEP_ALIVE_FAIL)) /* * Keep it long for Beacon workaround - ensures no AH_FALSE alarm */ #define AR_WOW_BMISSTHRESHOLD 0x20 /* WoW - Transmit buffer for keep alive frames */ #define AR_WOW_TRANSMIT_BUFFER AR_MAC_PCU_OFFSET(MAC_PCU_BUF) #define AR_WOW_TXBUF(_i) (AR_WOW_TRANSMIT_BUFFER + ((_i)<<2)) #define AR_WOW_KA_DESC_WORD2 AR_WOW_TXBUF(0) #define AR_WOW_KA_DESC_WORD3 AR_WOW_TXBUF(1) #define AR_WOW_KA_DESC_WORD4 AR_WOW_TXBUF(2) #define AR_WOW_KA_DESC_WORD5 AR_WOW_TXBUF(3) #define AR_WOW_KA_DESC_WORD6 AR_WOW_TXBUF(4) #define AR_WOW_KA_DESC_WORD7 AR_WOW_TXBUF(5) #define AR_WOW_KA_DESC_WORD8 AR_WOW_TXBUF(6) #define AR_WOW_KA_DESC_WORD9 AR_WOW_TXBUF(7) #define AR_WOW_KA_DESC_WORD10 AR_WOW_TXBUF(8) #define AR_WOW_KA_DESC_WORD11 AR_WOW_TXBUF(9) #define AR_WOW_KA_DESC_WORD12 AR_WOW_TXBUF(10) #define AR_WOW_KA_DESC_WORD13 AR_WOW_TXBUF(11) /* KA_DATA_WORD = 6 words. Depending on the number of * descriptor words, it can start at AR_WOW_TXBUF(12) * or AR_WOW_TXBUF(13) */ #define AR_WOW_OFFLOAD_GTK_DATA_START AR_WOW_TXBUF(19) #define AR_WOW_KA_DATA_WORD_END_JUPITER AR_WOW_TXBUF(60) #define AR_WOW_SW_NULL_PARAMETER AR_WOW_TXBUF(61) #define AR_WOW_SW_NULL_LONG_PERIOD_MASK 0x0000FFFF #define AR_WOW_SW_NULL_LONG_PERIOD_MASK_S 0 #define AR_WOW_SW_NULL_SHORT_PERIOD_MASK 0xFFFF0000 #define AR_WOW_SW_NULL_SHORT_PERIOD_MASK_S 16 #define AR_WOW_OFFLOAD_COMMAND_JUPITER AR_WOW_TXBUF(62) #define AR_WOW_OFFLOAD_ENA_GTK 0x80000000 #define AR_WOW_OFFLOAD_ENA_ACER_MAGIC 0x40000000 #define AR_WOW_OFFLOAD_ENA_STD_MAGIC 0x20000000 #define AR_WOW_OFFLOAD_ENA_SWKA 0x10000000 #define AR_WOW_OFFLOAD_ENA_ARP_OFFLOAD 0x08000000 #define AR_WOW_OFFLOAD_ENA_NS_OFFLOAD 0x04000000 #define AR_WOW_OFFLOAD_ENA_4WAY_WAKE 0x02000000 #define AR_WOW_OFFLOAD_ENA_GTK_ERROR_WAKE 0x01000000 #define AR_WOW_OFFLOAD_ENA_AP_LOSS_WAKE 0x00800000 #define AR_WOW_OFFLOAD_ENA_BT_SLEEP 0x00080000 #define AR_WOW_OFFLOAD_ENA_SW_NULL 0x00040000 #define AR_WOW_OFFLOAD_ENA_HWKA_FAIL 0x00020000 #define AR_WOW_OFFLOAD_ENA_DEVID_SWAR 0x00010000 #define AR_WOW_OFFLOAD_STATUS_JUPITER AR_WOW_TXBUF(63) /* WoW Transmit Buffer for patterns */ #define AR_WOW_TB_PATTERN0 AR_WOW_TXBUF(64) #define AR_WOW_TB_PATTERN1 AR_WOW_TXBUF(128) #define AR_WOW_TB_PATTERN2 AR_WOW_TXBUF(192) #define AR_WOW_TB_PATTERN3 AR_WOW_TXBUF(256) #define AR_WOW_TB_PATTERN4 AR_WOW_TXBUF(320) #define AR_WOW_TB_PATTERN5 AR_WOW_TXBUF(384) #define AR_WOW_TB_PATTERN6 AR_WOW_TXBUF(448) #define AR_WOW_TB_PATTERN7 AR_WOW_TXBUF(512) #define AR_WOW_TB_MASK0 AR_WOW_TXBUF(768) #define AR_WOW_TB_MASK1 AR_WOW_TXBUF(776) #define AR_WOW_TB_MASK2 AR_WOW_TXBUF(784) #define AR_WOW_TB_MASK3 AR_WOW_TXBUF(792) #define AR_WOW_TB_MASK4 AR_WOW_TXBUF(800) #define AR_WOW_TB_MASK5 AR_WOW_TXBUF(808) #define AR_WOW_TB_MASK6 AR_WOW_TXBUF(816) #define AR_WOW_TB_MASK7 AR_WOW_TXBUF(824) #define AR_WOW_OFFLOAD_GTK_TXDESC_PARAM_START AR_WOW_TXBUF(825) #define AR_WOW_OFFLOAD_GTK_TXDESC_PARAM_START_JUPITER AR_WOW_TXBUF(832) #define AR_WOW_OFFLOAD_GTK_TXDESC_PARAM_WORDS 4 #define AR_WOW_OFFLOAD_GTK_DATA_START_JUPITER AR_WOW_TXBUF(836) #define AR_WOW_OFFLOAD_GTK_DATA_WORDS_JUPITER 20 #define AR_WOW_OFFLOAD_ACER_MAGIC_START AR_WOW_TXBUF(856) #define AR_WOW_OFFLOAD_ACER_MAGIC_WORDS 2 #define AR_WOW_OFFLOAD_ACER_KA0_START AR_WOW_TXBUF(858) #define AR_WOW_OFFLOAD_ACER_KA0_PERIOD_MS AR_WOW_TXBUF(858) #define AR_WOW_OFFLOAD_ACER_KA0_SIZE AR_WOW_TXBUF(859) #define AR_WOW_OFFLOAD_ACER_KA0_DATA AR_WOW_TXBUF(860) #define AR_WOW_OFFLOAD_ACER_KA0_DATA_WORDS 20 #define AR_WOW_OFFLOAD_ACER_KA0_WORDS 22 #define AR_WOW_OFFLOAD_ACER_KA1_START AR_WOW_TXBUF(880) #define AR_WOW_OFFLOAD_ACER_KA1_PERIOD_MS AR_WOW_TXBUF(880) #define AR_WOW_OFFLOAD_ACER_KA1_SIZE AR_WOW_TXBUF(881) #define AR_WOW_OFFLOAD_ACER_KA1_DATA AR_WOW_TXBUF(882) #define AR_WOW_OFFLOAD_ACER_KA1_DATA_WORDS 20 #define AR_WOW_OFFLOAD_ACER_KA1_WORDS 22 #define AR_WOW_OFFLOAD_ARP0_START AR_WOW_TXBUF(902) #define AR_WOW_OFFLOAD_ARP0_VALID AR_WOW_TXBUF(902) #define AR_WOW_OFFLOAD_ARP0_RMT_IP AR_WOW_TXBUF(903) #define AR_WOW_OFFLOAD_ARP0_HOST_IP AR_WOW_TXBUF(904) #define AR_WOW_OFFLOAD_ARP0_MAC_L AR_WOW_TXBUF(905) #define AR_WOW_OFFLOAD_ARP0_MAC_H AR_WOW_TXBUF(906) #define AR_WOW_OFFLOAD_ARP0_WORDS 5 #define AR_WOW_OFFLOAD_ARP1_START AR_WOW_TXBUF(907) #define AR_WOW_OFFLOAD_ARP1_VALID AR_WOW_TXBUF(907) #define AR_WOW_OFFLOAD_ARP1_RMT_IP AR_WOW_TXBUF(908) #define AR_WOW_OFFLOAD_ARP1_HOST_IP AR_WOW_TXBUF(909) #define AR_WOW_OFFLOAD_ARP1_MAC_L AR_WOW_TXBUF(910) #define AR_WOW_OFFLOAD_ARP1_MAC_H AR_WOW_TXBUF(911) #define AR_WOW_OFFLOAD_ARP1_WORDS 5 #define AR_WOW_OFFLOAD_NS0_START AR_WOW_TXBUF(912) #define AR_WOW_OFFLOAD_NS0_VALID AR_WOW_TXBUF(912) #define AR_WOW_OFFLOAD_NS0_RMT_IPV6 AR_WOW_TXBUF(913) #define AR_WOW_OFFLOAD_NS0_SOLICIT_IPV6 AR_WOW_TXBUF(917) #define AR_WOW_OFFLOAD_NS0_MAC_L AR_WOW_TXBUF(921) #define AR_WOW_OFFLOAD_NS0_MAC_H AR_WOW_TXBUF(922) #define AR_WOW_OFFLOAD_NS0_TGT0_IPV6 AR_WOW_TXBUF(923) #define AR_WOW_OFFLOAD_NS0_TGT1_IPV6 AR_WOW_TXBUF(927) #define AR_WOW_OFFLOAD_NS0_WORDS 19 #define AR_WOW_OFFLOAD_NS1_START AR_WOW_TXBUF(931) #define AR_WOW_OFFLOAD_NS1_VALID AR_WOW_TXBUF(931) #define AR_WOW_OFFLOAD_NS1_RMT_IPV6 AR_WOW_TXBUF(932) #define AR_WOW_OFFLOAD_NS1_SOLICIT_IPV6 AR_WOW_TXBUF(936) #define AR_WOW_OFFLOAD_NS1_MAC_L AR_WOW_TXBUF(940) #define AR_WOW_OFFLOAD_NS1_MAC_H AR_WOW_TXBUF(941) #define AR_WOW_OFFLOAD_NS1_TGT0_IPV6 AR_WOW_TXBUF(942) #define AR_WOW_OFFLOAD_NS1_TGT1_IPV6 AR_WOW_TXBUF(946) #define AR_WOW_OFFLOAD_NS1_WORDS 19 #define AR_WOW_OFFLOAD_WLAN_REGSET_START AR_WOW_TXBUF(950) #define AR_WOW_OFFLOAD_WLAN_REGSET_NUM AR_WOW_TXBUF(950) #define AR_WOW_OFFLOAD_WLAN_REGSET_REGVAL AR_WOW_TXBUF(951) #define AR_WOW_OFFLOAD_WLAN_REGSET_MAX_PAIR 32 #define AR_WOW_OFFLOAD_WLAN_REGSET_WORDS 65 //(1 + AR_WOW_OFFLOAD_WLAN_REGSET_MAX_PAIR * 2) /* Currently Pattern 0-7 are supported - so bit 0-7 are set */ #define AR_WOW_PATTERN_SUPPORTED 0xFF #define AR_WOW_LENGTH_MAX 0xFF #define AR_WOW_LENGTH1_SHIFT(_i) ((0x3 - ((_i) & 0x3)) << 0x3) #define AR_WOW_LENGTH1_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LENGTH1_SHIFT(_i)) #define AR_WOW_LENGTH2_SHIFT(_i) ((0x7 - ((_i) & 0x7)) << 0x3) #define AR_WOW_LENGTH2_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LENGTH2_SHIFT(_i)) /* * MAC Direct Connect registers * * Added to support dual BSSID/TSF which are needed in the application * of Mesh networking or Direct Connect. */ /* * Note that the only function added with this BSSID2 is to receive * multi/broadcast from BSSID2 as well */ /* MAC BSSID low 32 bits */ #define AR_BSS2_ID0 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID2_L32) /* MAC BSSID upper 16 bits / AID */ #define AR_BSS2_ID1 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID2_U16) /* * Secondary TSF support added for dual BSSID/TSF */ /* MAC local clock lower 32 bits */ #define AR_TSF2_L32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF2_L32) /* MAC local clock upper 32 bits */ #define AR_TSF2_U32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF2_U32) /* MAC Direct Connect Control */ #define AR_DIRECT_CONNECT AR_MAC_PCU_OFFSET(MAC_PCU_DIRECT_CONNECT) #define AR_DC_AP_STA_EN 0x00000001 #define AR_DC_AP_STA_EN_S 0 /* * tx_bf Register */ #define AR_SVD_OFFSET(_x) offsetof(struct svd_reg, _x) #define AR_TXBF_DBG AR_SVD_OFFSET(TXBF_DBG) #define AR_TXBF AR_SVD_OFFSET(TXBF) #define AR_TXBF_CB_TX 0x00000003 #define AR_TXBF_CB_TX_S 0 #define AR_TXBF_PSI_1_PHI_3 0 #define AR_TXBF_PSI_2_PHI_4 1 #define AR_TXBF_PSI_3_PHI_5 2 #define AR_TXBF_PSI_4_PHI_6 3 #define AR_TXBF_NB_TX 0x0000000C #define AR_TXBF_NB_TX_S 2 #define AR_TXBF_NUMBEROFBIT_4 0 #define AR_TXBF_NUMBEROFBIT_2 1 #define AR_TXBF_NUMBEROFBIT_6 2 #define AR_TXBF_NUMBEROFBIT_8 3 #define AR_TXBF_NG_RPT_TX 0x00000030 #define AR_TXBF_NG_RPT_TX_S 4 #define AR_TXBF_No_GROUP 0 #define AR_TXBF_TWO_GROUP 1 #define AR_TXBF_FOUR_GROUP 2 #define AR_TXBF_NG_CVCACHE 0x000000C0 #define AR_TXBF_NG_CVCACHE_S 6 #define AR_TXBF_FOUR_CLIENTS 0 #define AR_TXBF_EIGHT_CLIENTS 1 #define AR_TXBF_SIXTEEN_CLIENTS 2 #define AR_TXBF_TXCV_BFWEIGHT_METHOD 0x00000600 #define AR_TXBF_TXCV_BFWEIGHT_METHOD_S 9 #define AR_TXBF_NO_WEIGHTING 0 #define AR_TXBF_MAX_POWER 1 #define AR_TXBF_KEEP_RATIO 2 #define AR_TXBF_RLR_EN 0x00000800 #define AR_TXBF_RC_20_U_DONE 0x00001000 #define AR_TXBF_RC_20_L_DONE 0x00002000 #define AR_TXBF_RC_40_DONE 0x00004000 #define AR_TXBF_FORCE_UPDATE_V2BB 0x00008000 #define AR_TXBF_TIMER AR_SVD_OFFSET(TXBF_TIMER) #define AR_TXBF_TIMER_TIMEOUT 0x000000FF #define AR_TXBF_TIMER_TIMEOUT_S 0 #define AR_TXBF_TIMER_ATIMEOU 0x0000FF00 #define AR_TXBF_TIMER_ATIMEOUT_S 8 /* for SVD cache update */ #define AR_TXBF_SW AR_SVD_OFFSET(TXBF_SW) #define AR_LRU_ACK 0x00000001 #define AR_LRU_ADDR 0x000003FE #define AR_LRU_ADDR_S 1 #define AR_LRU_EN 0x00000800 #define AR_LRU_EN_S 11 #define AR_DEST_IDX 0x0007f000 #define AR_DEST_IDX_S 12 #define AR_LRU_WR_ACK 0x00080000 #define AR_LRU_WR_ACK_S 19 #define AR_LRU_RD_ACK 0x00100000 #define AR_LRU_RD_ACK_S 20 #define AR_RC0_0 AR_SVD_OFFSET(RC0) #define AR_RC0(_idx) (AR_RC0_0+(_idx)) #define AR_RC1_0 AR_SVD_OFFSET(RC1) #define AR_RC1(_idx) (AR_RC1_0+(_idx)) #define AR_CVCACHE_0 AR_SVD_OFFSET(CVCACHE) #define AR_CVCACHE(_idx) (AR_CVCACHE_0+(_idx)) /* for CV CACHE Header */ #define AR_CVCACHE_Ng_IDX 0x0000C000 #define AR_CVCACHE_Ng_IDX_S 14 #define AR_CVCACHE_BW40 0x00010000 #define AR_CVCACHE_BW40_S 16 #define AR_CVCACHE_IMPLICIT 0x00020000 #define AR_CVCACHE_IMPLICIT_S 17 #define AR_CVCACHE_DEST_IDX 0x01FC0000 #define AR_CVCACHE_DEST_IDX_S 18 #define AR_CVCACHE_Nc_IDX 0x06000000 #define AR_CVCACHE_Nc_IDX_S 25 #define AR_CVCACHE_Nr_IDX 0x18000000 #define AR_CVCACHE_Nr_IDX_S 27 #define AR_CVCACHE_EXPIRED 0x20000000 #define AR_CVCACHE_EXPIRED_S 29 #define AR_CVCACHE_WRITE 0x80000000 /* for CV cache data*/ #define AR_CVCACHE_RD_EN 0x40000000 #define AR_CVCACHE_DATA 0x3fffffff /* * ANT DIV setting */ #define ANT_DIV_CONTROL_ALL (0x7e000000) #define ANT_DIV_CONTROL_ALL_S (25) #define ANT_DIV_ENABLE (0x1000000) #define ANT_DIV_ENABLE_S (24) #define FAST_DIV_ENABLE (0x2000) #define FAST_DIV_ENABLE_S (13) /* Global register */ #define AR_GLB_REG_OFFSET(_x) offsetof(struct wlan_bt_glb_reg_pcie, _x) #define AR_MBOX_CTRL_STATUS AR_GLB_REG_OFFSET(GLB_MBOX_CONTROL_STATUS) #define AR_MBOX_INT_EMB_CPU 0x0001 #define AR_MBOX_INT_WLAN 0x0002 #define AR_MBOX_RESET 0x0004 #define AR_MBOX_RAM_REQ_MASK 0x0018 #define AR_MBOX_RAM_REQ_NO_RAM 0x0000 #define AR_MBOX_RAM_REQ_USB 0x0008 #define AR_MBOX_RAM_REQ_WLAN_BUF 0x0010 #define AR_MBOX_RAM_REQ_PATCH_REAPPY 0x0018 #define AR_MBOX_RAM_CONF 0x0020 #define AR_MBOX_WLAN_BUF 0x0040 #define AR_MBOX_WOW_REQ 0x0080 #define AR_MBOX_WOW_CONF 0x0100 #define AR_MBOX_WOW_ERROR_MASK 0x1e00 #define AR_MBOX_WOW_ERROR_NONE 0x0000 #define AR_MBOX_WOW_ERROR_INVALID_MSG 0x0200 #define AR_MBOX_WOW_ERROR_MALFORMED_MSG 0x0400 #define AR_MBOX_WOW_ERROR_INVALID_RAM_IMAGE 0x0600 #define AR_WLAN_WOW_STATUS AR_GLB_REG_OFFSET(GLB_WLAN_WOW_STATUS) #define AR_WLAN_WOW_ENABLE AR_GLB_REG_OFFSET(GLB_WLAN_WOW_ENABLE) #define AR_EMB_CPU_WOW_STATUS AR_GLB_REG_OFFSET(GLB_EMB_CPU_WOW_STATUS) #define AR_EMB_CPU_WOW_STATUS_KEEP_ALIVE_FAIL 0x1 #define AR_EMB_CPU_WOW_STATUS_BEACON_MISS 0x2 #define AR_EMB_CPU_WOW_STATUS_PATTERN_MATCH 0x4 #define AR_EMB_CPU_WOW_STATUS_MAGIC_PATTERN 0x8 #define AR_EMB_CPU_WOW_ENABLE AR_GLB_REG_OFFSET(GLB_EMB_CPU_WOW_ENABLE) #define AR_EMB_CPU_WOW_ENABLE_KEEP_ALIVE_FAIL 0x1 #define AR_EMB_CPU_WOW_ENABLE_BEACON_MISS 0x2 #define AR_EMB_CPU_WOW_ENABLE_PATTERN_MATCH 0x4 #define AR_EMB_CPU_WOW_ENABLE_MAGIC_PATTERN 0x8 #define AR_SW_WOW_CONTROL AR_GLB_REG_OFFSET(GLB_SW_WOW_CONTROL) #define AR_SW_WOW_ENABLE 0x1 #define AR_SWITCH_TO_REFCLK 0x2 #define AR_RESET_CONTROL 0x4 #define AR_RESET_VALUE_MASK 0x8 #define AR_HW_WOW_DISABLE 0x10 #define AR_CLR_MAC_INTERRUPT 0x20 #define AR_CLR_KA_INTERRUPT 0x40 /* * WLAN coex registers */ #define AR_WLAN_COEX_OFFSET(_x) offsetof(struct wlan_coex_reg, _x) #define AR_MCI_COMMAND0 AR_WLAN_COEX_OFFSET(MCI_COMMAND0) #define AR_MCI_COMMAND0_HEADER 0xFF #define AR_MCI_COMMAND0_HEADER_S 0 #define AR_MCI_COMMAND0_LEN 0x1f00 #define AR_MCI_COMMAND0_LEN_S 8 #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP 0x2000 #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP_S 13 #define AR_MCI_COMMAND1 AR_WLAN_COEX_OFFSET(MCI_COMMAND1) #define AR_MCI_COMMAND2 AR_WLAN_COEX_OFFSET(MCI_COMMAND2) #define AR_MCI_COMMAND2_RESET_TX 0x01 #define AR_MCI_COMMAND2_RESET_TX_S 0 #define AR_MCI_COMMAND2_RESET_RX 0x02 #define AR_MCI_COMMAND2_RESET_RX_S 1 #define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES 0x3FC #define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES_S 2 #define AR_MCI_COMMAND2_RESET_REQ_WAKEUP 0x400 #define AR_MCI_COMMAND2_RESET_REQ_WAKEUP_S 10 #define AR_MCI_RX_CTRL AR_WLAN_COEX_OFFSET(MCI_RX_CTRL) #define AR_MCI_TX_CTRL AR_WLAN_COEX_OFFSET(MCI_TX_CTRL) /* 0 = no division, 1 = divide by 2, 2 = divide by 4, 3 = divide by 8 */ #define AR_MCI_TX_CTRL_CLK_DIV 0x03 #define AR_MCI_TX_CTRL_CLK_DIV_S 0 #define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE 0x04 #define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE_S 2 #define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ 0xFFFFF8 #define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ_S 3 #define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM 0xF000000 #define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM_S 24 #define AR_MCI_MSG_ATTRIBUTES_TABLE AR_WLAN_COEX_OFFSET(MCI_MSG_ATTRIBUTES_TABLE) #define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM 0xFFFF #define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM_S 0 #define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR 0xFFFF0000 #define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR_S 16 #define AR_MCI_SCHD_TABLE_0 AR_WLAN_COEX_OFFSET(MCI_SCHD_TABLE_0) #define AR_MCI_SCHD_TABLE_1 AR_WLAN_COEX_OFFSET(MCI_SCHD_TABLE_1) #define AR_MCI_GPM_0 AR_WLAN_COEX_OFFSET(MCI_GPM_0) #define AR_MCI_GPM_1 AR_WLAN_COEX_OFFSET(MCI_GPM_1) #define AR_MCI_GPM_WRITE_PTR 0xFFFF0000 #define AR_MCI_GPM_WRITE_PTR_S 16 #define AR_MCI_GPM_BUF_LEN 0x0000FFFF #define AR_MCI_GPM_BUF_LEN_S 0 #define AR_MCI_INTERRUPT_RAW AR_WLAN_COEX_OFFSET(MCI_INTERRUPT_RAW) #define AR_MCI_INTERRUPT_EN AR_WLAN_COEX_OFFSET(MCI_INTERRUPT_EN) #define AR_MCI_INTERRUPT_SW_MSG_DONE 0x00000001 #define AR_MCI_INTERRUPT_SW_MSG_DONE_S 0 #define AR_MCI_INTERRUPT_CPU_INT_MSG 0x00000002 #define AR_MCI_INTERRUPT_CPU_INT_MSG_S 1 #define AR_MCI_INTERRUPT_RX_CKSUM_FAIL 0x00000004 #define AR_MCI_INTERRUPT_RX_CKSUM_FAIL_S 2 #define AR_MCI_INTERRUPT_RX_INVALID_HDR 0x00000008 #define AR_MCI_INTERRUPT_RX_INVALID_HDR_S 3 #define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x00000010 #define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL_S 4 #define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x00000020 #define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL_S 5 #define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x00000080 #define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL_S 7 #define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x00000100 #define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL_S 8 #define AR_MCI_INTERRUPT_RX_MSG 0x00000200 #define AR_MCI_INTERRUPT_RX_MSG_S 9 #define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x00000400 #define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE_S 10 #define AR_MCI_INTERRUPT_BT_PRI 0x07fff800 #define AR_MCI_INTERRUPT_BT_PRI_S 11 #define AR_MCI_INTERRUPT_BT_PRI_THRESH 0x08000000 #define AR_MCI_INTERRUPT_BT_PRI_THRESH_S 27 #define AR_MCI_INTERRUPT_BT_FREQ 0x10000000 #define AR_MCI_INTERRUPT_BT_FREQ_S 28 #define AR_MCI_INTERRUPT_BT_STOMP 0x20000000 #define AR_MCI_INTERRUPT_BT_STOMP_S 29 #define AR_MCI_INTERRUPT_BB_AIC_IRQ 0x40000000 #define AR_MCI_INTERRUPT_BB_AIC_IRQ_S 30 #define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000 #define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT_S 31 #define AR_MCI_INTERRUPT_MSG_FAIL_MASK ( AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ AR_MCI_INTERRUPT_TX_SW_MSG_FAIL ) #define AR_MCI_INTERRUPT_DEFAULT ( AR_MCI_INTERRUPT_SW_MSG_DONE | \ AR_MCI_INTERRUPT_RX_INVALID_HDR | \ AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ AR_MCI_INTERRUPT_TX_SW_MSG_FAIL | \ AR_MCI_INTERRUPT_RX_MSG | \ AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE | \ AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT ) #define AR_MCI_REMOTE_CPU_INT AR_WLAN_COEX_OFFSET(MCI_REMOTE_CPU_INT) #define AR_MCI_REMOTE_CPU_INT_EN AR_WLAN_COEX_OFFSET(MCI_REMOTE_CPU_INT_EN) #define AR_MCI_INTERRUPT_RX_MSG_RAW AR_WLAN_COEX_OFFSET(MCI_INTERRUPT_RX_MSG_RAW) #define AR_MCI_INTERRUPT_RX_MSG_EN AR_WLAN_COEX_OFFSET(MCI_INTERRUPT_RX_MSG_EN) #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001 #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET_S 0 #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002 #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL_S 1 #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004 #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK_S 2 #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008 #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO_S 3 #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010 #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST_S 4 #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020 #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO_S 5 #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040 #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT_S 6 #define AR_MCI_INTERRUPT_RX_MSG_GPM 0x00000100 #define AR_MCI_INTERRUPT_RX_MSG_GPM_S 8 #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200 #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO_S 9 #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400 #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING_S 10 #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800 #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING_S 11 #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000 #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE_S 12 #ifdef AH_DEBUG #define AR_MCI_INTERRUPT_RX_MSG_DEFAULT ( AR_MCI_INTERRUPT_RX_MSG_GPM | \ AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET | \ AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING | \ AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING | \ AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \ AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \ AR_MCI_INTERRUPT_RX_MSG_LNA_INFO | \ AR_MCI_INTERRUPT_RX_MSG_CONT_NACK | \ AR_MCI_INTERRUPT_RX_MSG_CONT_INFO | \ AR_MCI_INTERRUPT_RX_MSG_CONT_RST | \ AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE ) #else #define AR_MCI_INTERRUPT_RX_MSG_DEFAULT ( AR_MCI_INTERRUPT_RX_MSG_GPM | \ AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET | \ AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING | \ AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING | \ AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE ) #endif #define AR_MCI_INTERRUPT_RX_HW_MSG_MASK ( AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \ AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \ AR_MCI_INTERRUPT_RX_MSG_LNA_INFO | \ AR_MCI_INTERRUPT_RX_MSG_CONT_NACK | \ AR_MCI_INTERRUPT_RX_MSG_CONT_INFO | \ AR_MCI_INTERRUPT_RX_MSG_CONT_RST ) #define AR_MCI_CPU_INT AR_WLAN_COEX_OFFSET(MCI_CPU_INT) #define AR_MCI_RX_STATUS AR_WLAN_COEX_OFFSET(MCI_RX_STATUS) #define AR_MCI_RX_LAST_SCHD_MSG_INDEX 0x00000F00 #define AR_MCI_RX_LAST_SCHD_MSG_INDEX_S 8 #define AR_MCI_RX_REMOTE_SLEEP 0x00001000 #define AR_MCI_RX_REMOTE_SLEEP_S 12 #define AR_MCI_RX_MCI_CLK_REQ 0x00002000 #define AR_MCI_RX_MCI_CLK_REQ_S 13 #define AR_MCI_CONT_STATUS AR_WLAN_COEX_OFFSET(MCI_CONT_STATUS) #define AR_MCI_CONT_RSSI_POWER 0x000000FF #define AR_MCI_CONT_RSSI_POWER_S 0 #define AR_MCI_CONT_RRIORITY 0x0000FF00 #define AR_MCI_CONT_RRIORITY_S 8 #define AR_MCI_CONT_TXRX 0x00010000 #define AR_MCI_CONT_TXRX_S 16 #define AR_MCI_BT_PRI0 AR_WLAN_COEX_OFFSET(MCI_BT_PRI0) #define AR_MCI_BT_PRI1 AR_WLAN_COEX_OFFSET(MCI_BT_PRI1) #define AR_MCI_BT_PRI2 AR_WLAN_COEX_OFFSET(MCI_BT_PRI2) #define AR_MCI_BT_PRI3 AR_WLAN_COEX_OFFSET(MCI_BT_PRI3) #define AR_MCI_BT_PRI AR_WLAN_COEX_OFFSET(MCI_BT_PRI) #define AR_MCI_WL_FREQ0 AR_WLAN_COEX_OFFSET(MCI_WL_FREQ0) #define AR_MCI_WL_FREQ1 AR_WLAN_COEX_OFFSET(MCI_WL_FREQ1) #define AR_MCI_WL_FREQ2 AR_WLAN_COEX_OFFSET(MCI_WL_FREQ2) #define AR_MCI_GAIN AR_WLAN_COEX_OFFSET(MCI_GAIN) #define AR_MCI_WBTIMER1 AR_WLAN_COEX_OFFSET(MCI_WBTIMER1) #define AR_MCI_WBTIMER2 AR_WLAN_COEX_OFFSET(MCI_WBTIMER2) #define AR_MCI_WBTIMER3 AR_WLAN_COEX_OFFSET(MCI_WBTIMER3) #define AR_MCI_WBTIMER4 AR_WLAN_COEX_OFFSET(MCI_WBTIMER4) #define AR_MCI_MAXGAIN AR_WLAN_COEX_OFFSET(MCI_MAXGAIN) #define AR_MCI_HW_SCHD_TBL_CTL AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_CTL) #define AR_MCI_HW_SCHD_TBL_D0 AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_D0) #define AR_MCI_HW_SCHD_TBL_D1 AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_D1) #define AR_MCI_HW_SCHD_TBL_D2 AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_D2) #define AR_MCI_HW_SCHD_TBL_D3 AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_D3) #define AR_MCI_TX_PAYLOAD0 AR_WLAN_COEX_OFFSET(MCI_TX_PAYLOAD0) #define AR_MCI_TX_PAYLOAD1 AR_WLAN_COEX_OFFSET(MCI_TX_PAYLOAD1) #define AR_MCI_TX_PAYLOAD2 AR_WLAN_COEX_OFFSET(MCI_TX_PAYLOAD2) #define AR_MCI_TX_PAYLOAD3 AR_WLAN_COEX_OFFSET(MCI_TX_PAYLOAD3) #define AR_BTCOEX_WBTIMER AR_WLAN_COEX_OFFSET(BTCOEX_WBTIMER) #define AR_BTCOEX_CTRL AR_WLAN_COEX_OFFSET(BTCOEX_CTRL) #define AR_BTCOEX_CTRL_JUPITER_MODE 0x00000001 #define AR_BTCOEX_CTRL_JUPITER_MODE_S 0 #define AR_BTCOEX_CTRL_WBTIMER_EN 0x00000002 #define AR_BTCOEX_CTRL_WBTIMER_EN_S 1 #define AR_BTCOEX_CTRL_MCI_MODE_EN 0x00000004 #define AR_BTCOEX_CTRL_MCI_MODE_EN_S 2 #define AR_BTCOEX_CTRL_LNA_SHARED 0x00000008 #define AR_BTCOEX_CTRL_LNA_SHARED_S 3 #define AR_BTCOEX_CTRL_PA_SHARED 0x00000010 #define AR_BTCOEX_CTRL_PA_SHARED_S 4 #define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN 0x00000020 #define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN_S 5 #define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN 0x00000040 #define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN_S 6 #define AR_BTCOEX_CTRL_NUM_ANTENNAS 0x00000180 #define AR_BTCOEX_CTRL_NUM_ANTENNAS_S 7 #define AR_BTCOEX_CTRL_RX_CHAIN_MASK 0x00000E00 #define AR_BTCOEX_CTRL_RX_CHAIN_MASK_S 9 #define AR_BTCOEX_CTRL_AGGR_THRESH 0x00007000 #define AR_BTCOEX_CTRL_AGGR_THRESH_S 12 #define AR_BTCOEX_CTRL_1_CHAIN_BCN 0x00080000 #define AR_BTCOEX_CTRL_1_CHAIN_BCN_S 19 #define AR_BTCOEX_CTRL_1_CHAIN_ACK 0x00100000 #define AR_BTCOEX_CTRL_1_CHAIN_ACK_S 20 #define AR_BTCOEX_CTRL_WAIT_BA_MARGIN 0x1FE00000 #define AR_BTCOEX_CTRL_WAIT_BA_MARGIN_S 28 #define AR_BTCOEX_CTRL_REDUCE_TXPWR 0x20000000 #define AR_BTCOEX_CTRL_REDUCE_TXPWR_S 29 #define AR_BTCOEX_CTRL_SPDT_ENABLE_10 0x40000000 #define AR_BTCOEX_CTRL_SPDT_ENABLE_10_S 30 #define AR_BTCOEX_CTRL_SPDT_POLARITY 0x80000000 #define AR_BTCOEX_CTRL_SPDT_POLARITY_S 31 #define AR_BTCOEX_WL_WEIGHTS0 AR_WLAN_COEX_OFFSET(BTCOEX_WL_WEIGHTS0) #define AR_BTCOEX_WL_WEIGHTS1 AR_WLAN_COEX_OFFSET(BTCOEX_WL_WEIGHTS1) #define AR_BTCOEX_WL_WEIGHTS2 AR_WLAN_COEX_OFFSET(BTCOEX_WL_WEIGHTS2) #define AR_BTCOEX_WL_WEIGHTS3 AR_WLAN_COEX_OFFSET(BTCOEX_WL_WEIGHTS3) #define AR_BTCOEX_MAX_TXPWR(_x) (AR_WLAN_COEX_OFFSET(BTCOEX_MAX_TXPWR) + ((_x) << 2)) #define AR_BTCOEX_WL_LNA AR_WLAN_COEX_OFFSET(BTCOEX_WL_LNA) #define AR_BTCOEX_RFGAIN_CTRL AR_WLAN_COEX_OFFSET(BTCOEX_RFGAIN_CTRL) #define AR_BTCOEX_CTRL2 AR_WLAN_COEX_OFFSET(BTCOEX_CTRL2) #define AR_BTCOEX_CTRL2_TXPWR_THRESH 0x0007F800 #define AR_BTCOEX_CTRL2_TXPWR_THRESH_S 11 #define AR_BTCOEX_CTRL2_TX_CHAIN_MASK 0x00380000 #define AR_BTCOEX_CTRL2_TX_CHAIN_MASK_S 19 #define AR_BTCOEX_CTRL2_RX_DEWEIGHT 0x00400000 #define AR_BTCOEX_CTRL2_RX_DEWEIGHT_S 22 #define AR_BTCOEX_CTRL2_GPIO_OBS_SEL 0x00800000 #define AR_BTCOEX_CTRL2_GPIO_OBS_SEL_S 23 #define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL 0x01000000 #define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL_S 24 #define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE 0x02000000 #define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE_S 25 #define AR_BTCOEX_RC AR_WLAN_COEX_OFFSET(BTCOEX_RC) #define AR_BTCOEX_MAX_RFGAIN(_x) AR_WLAN_COEX_OFFSET(BTCOEX_MAX_RFGAIN[_x]) #define AR_BTCOEX_DBG AR_WLAN_COEX_OFFSET(BTCOEX_DBG) #define AR_MCI_LAST_HW_MSG_HDR AR_WLAN_COEX_OFFSET(MCI_LAST_HW_MSG_HDR) #define AR_MCI_LAST_HW_MSG_BDY AR_WLAN_COEX_OFFSET(MCI_LAST_HW_MSG_BDY) #define AR_MCI_SCHD_TABLE_2 AR_WLAN_COEX_OFFSET(MCI_SCHD_TABLE_2) #define AR_MCI_SCHD_TABLE_2_MEM_BASED 0x00000001 #define AR_MCI_SCHD_TABLE_2_MEM_BASED_S 0 #define AR_MCI_SCHD_TABLE_2_HW_BASED 0x00000002 #define AR_MCI_SCHD_TABLE_2_HW_BASED_S 1 #define AR_BTCOEX_CTRL3 AR_WLAN_COEX_OFFSET(BTCOEX_CTRL3) #define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT 0x00000FFF #define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT_S 0 /****************************************************************************** * WLAN BT Global Register Map ******************************************************************************/ #define AR_WLAN_BT_GLB_OFFSET(_x) offsetof(struct wlan_bt_glb_reg_pcie, _x) /* * WLAN BT Global Registers */ #define AR_GLB_GPIO_CONTROL AR_WLAN_BT_GLB_OFFSET(GLB_GPIO_CONTROL) #define AR_GLB_WLAN_WOW_STATUS AR_WLAN_BT_GLB_OFFSET(GLB_WLAN_WOW_STATUS) #define AR_GLB_WLAN_WOW_ENABLE AR_WLAN_BT_GLB_OFFSET(GLB_WLAN_WOW_ENABLE) #define AR_GLB_EMB_CPU_WOW_STATUS AR_WLAN_BT_GLB_OFFSET(GLB_EMB_CPU_WOW_STATUS) #define AR_GLB_EMB_CPU_WOW_ENABLE AR_WLAN_BT_GLB_OFFSET(GLB_EMB_CPU_WOW_ENABLE) #define AR_GLB_MBOX_CONTROL_STATUS AR_WLAN_BT_GLB_OFFSET(GLB_MBOX_CONTROL_STATUS) #define AR_GLB_SW_WOW_CLK_CONTROL AR_WLAN_BT_GLB_OFFSET(GLB_SW_WOW_CLK_CONTROL) #define AR_GLB_APB_TIMEOUT AR_WLAN_BT_GLB_OFFSET(GLB_APB_TIMEOUT) #define AR_GLB_OTP_LDO_CONTROL AR_WLAN_BT_GLB_OFFSET(GLB_OTP_LDO_CONTROL) #define AR_GLB_OTP_LDO_POWER_GOOD AR_WLAN_BT_GLB_OFFSET(GLB_OTP_LDO_POWER_GOOD) #define AR_GLB_OTP_LDO_STATUS AR_WLAN_BT_GLB_OFFSET(GLB_OTP_LDO_STATUS) #define AR_GLB_SWREG_DISCONT_MODE AR_WLAN_BT_GLB_OFFSET(GLB_SWREG_DISCONT_MODE) #define AR_GLB_BT_GPIO_REMAP_OUT_CONTROL0 AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_OUT_CONTROL0) #define AR_GLB_BT_GPIO_REMAP_OUT_CONTROL1 AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_OUT_CONTROL1) #define AR_GLB_BT_GPIO_REMAP_IN_CONTROL0 AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_IN_CONTROL0) #define AR_GLB_BT_GPIO_REMAP_IN_CONTROL1 AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_IN_CONTROL1) #define AR_GLB_BT_GPIO_REMAP_IN_CONTROL2 AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_IN_CONTROL2) #define AR_GLB_SCRATCH(_ah) \ (AR_SREV_APHRODITE(_ah)? \ AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Aphrodite_10.GLB_SCRATCH) : \ (AR_SREV_JUPITER_20(_ah) ? \ AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Jupiter_20.GLB_SCRATCH) : \ AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Jupiter_10.GLB_SCRATCH))) #define AR_GLB_CONTROL AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Jupiter_20.GLB_CONTROL) #define AR_BTCOEX_CTRL_SPDT_ENABLE 0x00000001 #define AR_BTCOEX_CTRL_SPDT_ENABLE_S 0 #define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL 0x00000002 #define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL_S 1 #define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT 0x00000004 #define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT_S 2 #define AR_GLB_WLAN_UART_INTF_EN 0x00020000 #define AR_GLB_WLAN_UART_INTF_EN_S 17 #define AR_GLB_DS_JTAG_DISABLE 0x00040000 #define AR_GLB_DS_JTAG_DISABLE_S 18 #define AR_GLB_STATUS AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Jupiter_20.GLB_STATUS) /* * MAC Version and Revision */ #define AR_SREV_VERSION_OSPREY 0x1C0 #define AR_SREV_VERSION_AR9580 0x1C0 #define AR_SREV_VERSION_JUPITER 0x280 #define AR_SREV_VERSION_HORNET 0x200 #define AR_SREV_VERSION_WASP 0x300 /* XXX: Check Wasp version number */ #define AR_SREV_VERSION_SCORPION 0x400 #define AR_SREV_VERSION_POSEIDON 0x240 #define AR_SREV_VERSION_APHRODITE 0x2C0 #define AR_SREV_REVISION_OSPREY_10 0 /* Osprey 1.0 */ #define AR_SREV_REVISION_OSPREY_20 2 /* Osprey 2.0/2.1 */ #define AR_SREV_REVISION_OSPREY_22 3 /* Osprey 2.2 */ #define AR_SREV_REVISION_AR9580_10 4 /* AR9580/Peacock 1.0 */ #define AR_SREV_REVISION_HORNET_10 0 /* Hornet 1.0 */ #define AR_SREV_REVISION_HORNET_11 1 /* Hornet 1.1 */ #define AR_SREV_REVISION_HORNET_12 2 /* Hornet 1.2 */ #define AR_SREV_REVISION_HORNET_11_MASK 0xf /* Hornet 1.1 revision mask */ #define AR_SREV_REVISION_POSEIDON_10 0 /* Poseidon 1.0 */ #define AR_SREV_REVISION_POSEIDON_11 1 /* Poseidon 1.1 */ #define AR_SREV_REVISION_WASP_10 0 /* Wasp 1.0 */ #define AR_SREV_REVISION_WASP_11 1 /* Wasp 1.1 */ #define AR_SREV_REVISION_WASP_12 2 /* Wasp 1.2 */ #define AR_SREV_REVISION_WASP_13 3 /* Wasp 1.3 */ #define AR_SREV_REVISION_WASP_MASK 0xf /* Wasp revision mask */ #define AR_SREV_REVISION_WASP_MINOR_MINOR_MASK 0x10000 /* Wasp minor minor revision mask */ #define AR_SREV_REVISION_WASP_MINOR_MINOR_SHIFT 16 /* Wasp minor minor revision shift */ #define AR_SREV_REVISION_JUPITER_10 0 /* Jupiter 1.0 */ #define AR_SREV_REVISION_JUPITER_20 2 /* Jupiter 2.0 */ +#define AR_SREV_REVISION_JUPITER_21 3 /* Jupiter 2.1 */ #define AR_SREV_REVISION_APHRODITE_10 0 /* Aphrodite 1.0 */ #if defined(AH_SUPPORT_OSPREY) #define AR_SREV_OSPREY(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_OSPREY)) #define AR_SREV_OSPREY_22(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) && \ (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_OSPREY_22)) #else #define AR_SREV_OSPREY(_ah) 0 #define AR_SREV_OSPREY_10(_ah) 0 #define AR_SREV_OSPREY_20(_ah) 0 #define AR_SREV_OSPREY_22(_ah) 0 #define AR_SREV_OSPREY_20_OR_LATER(_ah) 0 #define AR_SREV_OSPREY_22_OR_LATER(_ah) 0 #endif /* #if defined(AH_SUPPORT_OSPREY) */ #define AR_SREV_AR9580(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_AR9580) && \ (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_AR9580_10)) #define AR_SREV_AR9580_10(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_AR9580) && \ (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_AR9580_10)) /* NOTE: When adding chips newer than Peacock, add chip check here. */ #define AR_SREV_AR9580_10_OR_LATER(_ah) \ (AR_SREV_AR9580(_ah)) #define AR_SREV_JUPITER(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER)) #define AR_SREV_JUPITER_10(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \ (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_JUPITER_10)) #define AR_SREV_JUPITER_20(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \ (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_JUPITER_20)) +#define AR_SREV_JUPITER_21(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \ + (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_JUPITER_21)) + #define AR_SREV_JUPITER_20_OR_LATER(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \ (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_JUPITER_20)) + +#define AR_SREV_JUPITER_21_OR_LATER(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \ + (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_JUPITER_21)) #define AR_SREV_APHRODITE(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_APHRODITE)) #define AR_SREV_APHRODITE_10(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_APHRODITE) && \ (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_APHRODITE_10)) #if defined(AH_SUPPORT_HORNET) #define AR_SREV_HORNET_10(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HORNET) && \ (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HORNET_10)) #define AR_SREV_HORNET_11(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HORNET) && \ (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HORNET_11)) #define AR_SREV_HORNET_12(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HORNET) && \ (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HORNET_12)) #define AR_SREV_HORNET(_ah) \ ( AR_SREV_HORNET_10(_ah) || AR_SREV_HORNET_11(_ah) || AR_SREV_HORNET_12(_ah) ) #else #define AR_SREV_HORNET_10(_ah) 0 #define AR_SREV_HORNET_11(_ah) 0 #define AR_SREV_HORNET_12(_ah) 0 #define AR_SREV_HORNET(_ah) 0 #endif /* #if defined(AH_SUPPORT_HORNET) */ #if defined(AH_SUPPORT_WASP) #define AR_SREV_WASP(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_WASP)) #else #define AR_SREV_WASP(_ah) 0 #endif /* #if defined(AH_SUPPORT_WASP) */ #define AR_SREV_WASP_10(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_WASP) && \ (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_WASP_10)) #define AR_SREV_WASP_11(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_WASP) && \ (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_WASP_11)) #define AR_SREV_WASP_12(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_WASP) && \ (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_WASP_12)) #if defined(AH_SUPPORT_SCORPION) #define AR_SREV_SCORPION(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_SCORPION)) #else #define AR_SREV_SCORPION(_ah) 0 #endif /* #if defined(AH_SUPPORT_SCORPION) */ #if defined(AH_SUPPORT_POSEIDON) #define AR_SREV_POSEIDON(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_POSEIDON)) #define AR_SREV_POSEIDON_10(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_POSEIDON) && \ (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_POSEIDON_10)) #define AR_SREV_POSEIDON_11(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_POSEIDON) && \ (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_POSEIDON_11)) #else #define AR_SREV_POSEIDON(_ah) 0 #define AR_SREV_POSEIDON_10(_ah) 0 #define AR_SREV_POSEIDON_11(_ah) 0 #endif /* #if defined(AH_SUPPORT_POSEIDON) */ #define AR_SREV_POSEIDON_11_OR_LATER(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_POSEIDON) && \ (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_POSEIDON_11)) #define AR_SREV_POSEIDON_OR_LATER(_ah) \ (AH_PRIVATE((_ah))->ah_macVersion >= AR_SREV_VERSION_POSEIDON) #define AR_SREV_SOC(_ah) (AR_SREV_HORNET(_ah) || AR_SREV_POSEIDON(_ah) || AR_SREV_WASP(_ah)) /* * Mask used to construct AAD for CCMP-AES * Cisco spec defined bits 0-3 as mask * IEEE802.11w defined as bit 4. */ #define AR_MFP_QOS_MASK_IEEE 0x10 #define AR_MFP_QOS_MASK_CISCO 0xf /* * frame control field mask: * 0 0 0 0 0 0 0 0 * | | | | | | | | _ Order bit * | | | | | | | _ _ Protected Frame bit * | | | | | | _ _ _ More data bit * | | | | | _ _ _ _ Power management bit * | | | | _ _ _ _ _ Retry bit * | | | _ _ _ _ _ _ More fragments bit * | | _ _ _ _ _ _ _ FromDS bit * | _ _ _ _ _ _ _ _ ToDS bit */ #define AR_AES_MUTE_MASK1_FC_MGMT_MFP 0xC7FF #endif Index: head/sys/contrib/dev/ath/ath_hal/ar9300/ar9462_2p0_initvals.h =================================================================== --- head/sys/contrib/dev/ath/ath_hal/ar9300/ar9462_2p0_initvals.h (nonexistent) +++ head/sys/contrib/dev/ath/ath_hal/ar9300/ar9462_2p0_initvals.h (revision 291433) @@ -0,0 +1,1250 @@ +/* + * Copyright (c) 2010-2011 Atheros Communications Inc. + * Copyright (c) 2011-2012 Qualcomm Atheros Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef INITVALS_9462_2P0_H +#define INITVALS_9462_2P0_H + +/* AR9462 2.0 */ + +#define ar9462_2p0_mac_postamble ar9331_1p1_mac_postamble + +#define ar9462_2p0_common_wo_xlna_rx_gain ar9300Common_wo_xlna_rx_gain_table_2p2 + +#define ar9462_2p0_common_5g_xlna_only_rxgain ar9462_2p0_common_mixed_rx_gain + +#define ar9462_2p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484 + +static const u32 ar9462_2p0_modes_fast_clock[][3] = { + /* Addr 5G_HT20 5G_HT40 */ + {0x00001030, 0x00000268, 0x000004d0}, + {0x00001070, 0x0000018c, 0x00000318}, + {0x000010b0, 0x00000fd0, 0x00001fa0}, + {0x00008014, 0x044c044c, 0x08980898}, + {0x0000801c, 0x148ec02b, 0x148ec057}, + {0x00008318, 0x000044c0, 0x00008980}, + {0x00009e00, 0x0372131c, 0x0372131c}, + {0x0000a230, 0x0000400b, 0x00004016}, + {0x0000a254, 0x00000898, 0x00001130}, +}; + +static const u32 ar9462_2p0_baseband_postamble[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a800d}, + {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a01ae}, + {0x00009824, 0x63c640de, 0x5ac640d0, 0x5ac640d0, 0x63c640da}, + {0x00009828, 0x0796be89, 0x0696b081, 0x0696b881, 0x09143e81}, + {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4}, + {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c}, + {0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4}, + {0x00009e00, 0x0372111a, 0x0372111a, 0x037216a0, 0x037216a2}, + {0x00009e04, 0x001c2020, 0x001c2020, 0x001c2020, 0x001c2020}, + {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000d8}, + {0x00009e10, 0x92c88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec86d2e}, + {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3236605e, 0x32365a5e}, + {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c}, + {0x00009e20, 0x000003a5, 0x000003a5, 0x000003a5, 0x000003a5}, + {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021}, + {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282}, + {0x00009e44, 0x62321e27, 0x62321e27, 0xfe291e27, 0xfe291e27}, + {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012}, + {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000}, + {0x0000a204, 0x01318fc0, 0x01318fc4, 0x01318fc4, 0x01318fc0}, + {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004}, + {0x0000a22c, 0x01026a2f, 0x01026a27, 0x01026a2f, 0x01026a2f}, + {0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b}, + {0x0000a234, 0x00000fff, 0x10000fff, 0x10000fff, 0x00000fff}, + {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018}, + {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108}, + {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898}, + {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002}, + {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e}, + {0x0000a260, 0x0a021501, 0x0a021501, 0x3a021501, 0x3a021501}, + {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, + {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b}, + {0x0000a284, 0x00000000, 0x00000000, 0x00000150, 0x00000150}, + {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110}, + {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222}, + {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18}, + {0x0000a2d0, 0x00041981, 0x00041981, 0x00041981, 0x00041982}, + {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b}, + {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a3a4, 0x00000050, 0x00000050, 0x00000000, 0x00000000}, + {0x0000a3a8, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa}, + {0x0000a3ac, 0xaaaaaa00, 0xaa30aa30, 0xaaaaaa00, 0xaaaaaa00}, + {0x0000a41c, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce}, + {0x0000a420, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce}, + {0x0000a424, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce}, + {0x0000a428, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce}, + {0x0000a42c, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce}, + {0x0000a430, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce}, + {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c}, + {0x0000ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x00100000}, + {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c}, + {0x0000ae20, 0x000001a6, 0x000001a6, 0x000001aa, 0x000001aa}, + {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550}, +}; + +static const u32 ar9462_2p0_common_rx_gain[][2] = { + /* Addr allmodes */ + {0x0000a000, 0x00010000}, + {0x0000a004, 0x00030002}, + {0x0000a008, 0x00050004}, + {0x0000a00c, 0x00810080}, + {0x0000a010, 0x00830082}, + {0x0000a014, 0x01810180}, + {0x0000a018, 0x01830182}, + {0x0000a01c, 0x01850184}, + {0x0000a020, 0x01890188}, + {0x0000a024, 0x018b018a}, + {0x0000a028, 0x018d018c}, + {0x0000a02c, 0x01910190}, + {0x0000a030, 0x01930192}, + {0x0000a034, 0x01950194}, + {0x0000a038, 0x038a0196}, + {0x0000a03c, 0x038c038b}, + {0x0000a040, 0x0390038d}, + {0x0000a044, 0x03920391}, + {0x0000a048, 0x03940393}, + {0x0000a04c, 0x03960395}, + {0x0000a050, 0x00000000}, + {0x0000a054, 0x00000000}, + {0x0000a058, 0x00000000}, + {0x0000a05c, 0x00000000}, + {0x0000a060, 0x00000000}, + {0x0000a064, 0x00000000}, + {0x0000a068, 0x00000000}, + {0x0000a06c, 0x00000000}, + {0x0000a070, 0x00000000}, + {0x0000a074, 0x00000000}, + {0x0000a078, 0x00000000}, + {0x0000a07c, 0x00000000}, + {0x0000a080, 0x22222229}, + {0x0000a084, 0x1d1d1d1d}, + {0x0000a088, 0x1d1d1d1d}, + {0x0000a08c, 0x1d1d1d1d}, + {0x0000a090, 0x171d1d1d}, + {0x0000a094, 0x11111717}, + {0x0000a098, 0x00030311}, + {0x0000a09c, 0x00000000}, + {0x0000a0a0, 0x00000000}, + {0x0000a0a4, 0x00000000}, + {0x0000a0a8, 0x00000000}, + {0x0000a0ac, 0x00000000}, + {0x0000a0b0, 0x00000000}, + {0x0000a0b4, 0x00000000}, + {0x0000a0b8, 0x00000000}, + {0x0000a0bc, 0x00000000}, + {0x0000a0c0, 0x001f0000}, + {0x0000a0c4, 0x01000101}, + {0x0000a0c8, 0x011e011f}, + {0x0000a0cc, 0x011c011d}, + {0x0000a0d0, 0x02030204}, + {0x0000a0d4, 0x02010202}, + {0x0000a0d8, 0x021f0200}, + {0x0000a0dc, 0x0302021e}, + {0x0000a0e0, 0x03000301}, + {0x0000a0e4, 0x031e031f}, + {0x0000a0e8, 0x0402031d}, + {0x0000a0ec, 0x04000401}, + {0x0000a0f0, 0x041e041f}, + {0x0000a0f4, 0x0502041d}, + {0x0000a0f8, 0x05000501}, + {0x0000a0fc, 0x051e051f}, + {0x0000a100, 0x06010602}, + {0x0000a104, 0x061f0600}, + {0x0000a108, 0x061d061e}, + {0x0000a10c, 0x07020703}, + {0x0000a110, 0x07000701}, + {0x0000a114, 0x00000000}, + {0x0000a118, 0x00000000}, + {0x0000a11c, 0x00000000}, + {0x0000a120, 0x00000000}, + {0x0000a124, 0x00000000}, + {0x0000a128, 0x00000000}, + {0x0000a12c, 0x00000000}, + {0x0000a130, 0x00000000}, + {0x0000a134, 0x00000000}, + {0x0000a138, 0x00000000}, + {0x0000a13c, 0x00000000}, + {0x0000a140, 0x001f0000}, + {0x0000a144, 0x01000101}, + {0x0000a148, 0x011e011f}, + {0x0000a14c, 0x011c011d}, + {0x0000a150, 0x02030204}, + {0x0000a154, 0x02010202}, + {0x0000a158, 0x021f0200}, + {0x0000a15c, 0x0302021e}, + {0x0000a160, 0x03000301}, + {0x0000a164, 0x031e031f}, + {0x0000a168, 0x0402031d}, + {0x0000a16c, 0x04000401}, + {0x0000a170, 0x041e041f}, + {0x0000a174, 0x0502041d}, + {0x0000a178, 0x05000501}, + {0x0000a17c, 0x051e051f}, + {0x0000a180, 0x06010602}, + {0x0000a184, 0x061f0600}, + {0x0000a188, 0x061d061e}, + {0x0000a18c, 0x07020703}, + {0x0000a190, 0x07000701}, + {0x0000a194, 0x00000000}, + {0x0000a198, 0x00000000}, + {0x0000a19c, 0x00000000}, + {0x0000a1a0, 0x00000000}, + {0x0000a1a4, 0x00000000}, + {0x0000a1a8, 0x00000000}, + {0x0000a1ac, 0x00000000}, + {0x0000a1b0, 0x00000000}, + {0x0000a1b4, 0x00000000}, + {0x0000a1b8, 0x00000000}, + {0x0000a1bc, 0x00000000}, + {0x0000a1c0, 0x00000000}, + {0x0000a1c4, 0x00000000}, + {0x0000a1c8, 0x00000000}, + {0x0000a1cc, 0x00000000}, + {0x0000a1d0, 0x00000000}, + {0x0000a1d4, 0x00000000}, + {0x0000a1d8, 0x00000000}, + {0x0000a1dc, 0x00000000}, + {0x0000a1e0, 0x00000000}, + {0x0000a1e4, 0x00000000}, + {0x0000a1e8, 0x00000000}, + {0x0000a1ec, 0x00000000}, + {0x0000a1f0, 0x00000396}, + {0x0000a1f4, 0x00000396}, + {0x0000a1f8, 0x00000396}, + {0x0000a1fc, 0x00000196}, + {0x0000b000, 0x00010000}, + {0x0000b004, 0x00030002}, + {0x0000b008, 0x00050004}, + {0x0000b00c, 0x00810080}, + {0x0000b010, 0x00830082}, + {0x0000b014, 0x01810180}, + {0x0000b018, 0x01830182}, + {0x0000b01c, 0x01850184}, + {0x0000b020, 0x02810280}, + {0x0000b024, 0x02830282}, + {0x0000b028, 0x02850284}, + {0x0000b02c, 0x02890288}, + {0x0000b030, 0x028b028a}, + {0x0000b034, 0x0388028c}, + {0x0000b038, 0x038a0389}, + {0x0000b03c, 0x038c038b}, + {0x0000b040, 0x0390038d}, + {0x0000b044, 0x03920391}, + {0x0000b048, 0x03940393}, + {0x0000b04c, 0x03960395}, + {0x0000b050, 0x00000000}, + {0x0000b054, 0x00000000}, + {0x0000b058, 0x00000000}, + {0x0000b05c, 0x00000000}, + {0x0000b060, 0x00000000}, + {0x0000b064, 0x00000000}, + {0x0000b068, 0x00000000}, + {0x0000b06c, 0x00000000}, + {0x0000b070, 0x00000000}, + {0x0000b074, 0x00000000}, + {0x0000b078, 0x00000000}, + {0x0000b07c, 0x00000000}, + {0x0000b080, 0x2a2d2f32}, + {0x0000b084, 0x21232328}, + {0x0000b088, 0x19191c1e}, + {0x0000b08c, 0x12141417}, + {0x0000b090, 0x07070e0e}, + {0x0000b094, 0x03030305}, + {0x0000b098, 0x00000003}, + {0x0000b09c, 0x00000000}, + {0x0000b0a0, 0x00000000}, + {0x0000b0a4, 0x00000000}, + {0x0000b0a8, 0x00000000}, + {0x0000b0ac, 0x00000000}, + {0x0000b0b0, 0x00000000}, + {0x0000b0b4, 0x00000000}, + {0x0000b0b8, 0x00000000}, + {0x0000b0bc, 0x00000000}, + {0x0000b0c0, 0x003f0020}, + {0x0000b0c4, 0x00400041}, + {0x0000b0c8, 0x0140005f}, + {0x0000b0cc, 0x0160015f}, + {0x0000b0d0, 0x017e017f}, + {0x0000b0d4, 0x02410242}, + {0x0000b0d8, 0x025f0240}, + {0x0000b0dc, 0x027f0260}, + {0x0000b0e0, 0x0341027e}, + {0x0000b0e4, 0x035f0340}, + {0x0000b0e8, 0x037f0360}, + {0x0000b0ec, 0x04400441}, + {0x0000b0f0, 0x0460045f}, + {0x0000b0f4, 0x0541047f}, + {0x0000b0f8, 0x055f0540}, + {0x0000b0fc, 0x057f0560}, + {0x0000b100, 0x06400641}, + {0x0000b104, 0x0660065f}, + {0x0000b108, 0x067e067f}, + {0x0000b10c, 0x07410742}, + {0x0000b110, 0x075f0740}, + {0x0000b114, 0x077f0760}, + {0x0000b118, 0x07800781}, + {0x0000b11c, 0x07a0079f}, + {0x0000b120, 0x07c107bf}, + {0x0000b124, 0x000007c0}, + {0x0000b128, 0x00000000}, + {0x0000b12c, 0x00000000}, + {0x0000b130, 0x00000000}, + {0x0000b134, 0x00000000}, + {0x0000b138, 0x00000000}, + {0x0000b13c, 0x00000000}, + {0x0000b140, 0x003f0020}, + {0x0000b144, 0x00400041}, + {0x0000b148, 0x0140005f}, + {0x0000b14c, 0x0160015f}, + {0x0000b150, 0x017e017f}, + {0x0000b154, 0x02410242}, + {0x0000b158, 0x025f0240}, + {0x0000b15c, 0x027f0260}, + {0x0000b160, 0x0341027e}, + {0x0000b164, 0x035f0340}, + {0x0000b168, 0x037f0360}, + {0x0000b16c, 0x04400441}, + {0x0000b170, 0x0460045f}, + {0x0000b174, 0x0541047f}, + {0x0000b178, 0x055f0540}, + {0x0000b17c, 0x057f0560}, + {0x0000b180, 0x06400641}, + {0x0000b184, 0x0660065f}, + {0x0000b188, 0x067e067f}, + {0x0000b18c, 0x07410742}, + {0x0000b190, 0x075f0740}, + {0x0000b194, 0x077f0760}, + {0x0000b198, 0x07800781}, + {0x0000b19c, 0x07a0079f}, + {0x0000b1a0, 0x07c107bf}, + {0x0000b1a4, 0x000007c0}, + {0x0000b1a8, 0x00000000}, + {0x0000b1ac, 0x00000000}, + {0x0000b1b0, 0x00000000}, + {0x0000b1b4, 0x00000000}, + {0x0000b1b8, 0x00000000}, + {0x0000b1bc, 0x00000000}, + {0x0000b1c0, 0x00000000}, + {0x0000b1c4, 0x00000000}, + {0x0000b1c8, 0x00000000}, + {0x0000b1cc, 0x00000000}, + {0x0000b1d0, 0x00000000}, + {0x0000b1d4, 0x00000000}, + {0x0000b1d8, 0x00000000}, + {0x0000b1dc, 0x00000000}, + {0x0000b1e0, 0x00000000}, + {0x0000b1e4, 0x00000000}, + {0x0000b1e8, 0x00000000}, + {0x0000b1ec, 0x00000000}, + {0x0000b1f0, 0x00000396}, + {0x0000b1f4, 0x00000396}, + {0x0000b1f8, 0x00000396}, + {0x0000b1fc, 0x00000196}, +}; + +static const u32 ar9462_2p0_pciephy_clkreq_disable_L1[][2] = { + /* Addr allmodes */ + {0x00018c00, 0x18213ede}, + {0x00018c04, 0x000801d8}, + {0x00018c08, 0x0003780c}, +}; + +static const u32 ar9462_2p0_radio_postamble_sys2ant[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808}, + {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008}, + {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008}, +}; + +static const u32 ar9462_2p0_modes_low_ob_db_tx_gain[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, + {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, + {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, + {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800}, + {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, + {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9}, + {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002}, + {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004}, + {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200}, + {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202}, + {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400}, + {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402}, + {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404}, + {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603}, + {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02}, + {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04}, + {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20}, + {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20}, + {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22}, + {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24}, + {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640}, + {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660}, + {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861}, + {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81}, + {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83}, + {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84}, + {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3}, + {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5}, + {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9}, + {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb}, + {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, + {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, + {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, + {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, + {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, + {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, + {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, + {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000}, + {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501}, + {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501}, + {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03}, + {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04}, + {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04}, + {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005}, + {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, + {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, + {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, + {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, + {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, + {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, + {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800}, + {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, + {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4}, + {0x00016048, 0x64992060, 0x64992060, 0x64992060, 0x64992060}, + {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, + {0x00016444, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4}, + {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000}, + {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, +}; + +static const u32 ar9462_2p0_soc_postamble[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x00007010, 0x00000033, 0x00000033, 0x00000033, 0x00000033}, +}; + +static const u32 ar9462_2p0_baseband_core[][2] = { + /* Addr allmodes */ + {0x00009800, 0xafe68e30}, + {0x00009804, 0xfd14e000}, + {0x00009808, 0x9c0a9f6b}, + {0x0000980c, 0x04900000}, + {0x00009814, 0x9280c00a}, + {0x00009818, 0x00000000}, + {0x0000981c, 0x00020028}, + {0x00009834, 0x6400a290}, + {0x00009838, 0x0108ecff}, + {0x0000983c, 0x0d000600}, + {0x00009880, 0x201fff00}, + {0x00009884, 0x00001042}, + {0x000098a4, 0x00200400}, + {0x000098b0, 0x32440bbe}, + {0x000098d0, 0x004b6a8e}, + {0x000098d4, 0x00000820}, + {0x000098dc, 0x00000000}, + {0x000098e4, 0x01ffffff}, + {0x000098e8, 0x01ffffff}, + {0x000098ec, 0x01ffffff}, + {0x000098f0, 0x00000000}, + {0x000098f4, 0x00000000}, + {0x00009bf0, 0x80000000}, + {0x00009c04, 0xff55ff55}, + {0x00009c08, 0x0320ff55}, + {0x00009c0c, 0x00000000}, + {0x00009c10, 0x00000000}, + {0x00009c14, 0x00046384}, + {0x00009c18, 0x05b6b440}, + {0x00009c1c, 0x00b6b440}, + {0x00009d00, 0xc080a333}, + {0x00009d04, 0x40206c10}, + {0x00009d08, 0x009c4060}, + {0x00009d0c, 0x9883800a}, + {0x00009d10, 0x01834061}, + {0x00009d14, 0x00c0040b}, + {0x00009d18, 0x00000000}, + {0x00009e08, 0x0038230c}, + {0x00009e24, 0x990bb515}, + {0x00009e28, 0x0c6f0000}, + {0x00009e30, 0x06336f77}, + {0x00009e34, 0x6af6532f}, + {0x00009e38, 0x0cc80c00}, + {0x00009e40, 0x15262820}, + {0x00009e4c, 0x00001004}, + {0x00009e50, 0x00ff03f1}, + {0x00009e54, 0xe4c555c2}, + {0x00009e58, 0xfd857722}, + {0x00009e5c, 0xe9198724}, + {0x00009fc0, 0x803e4788}, + {0x00009fc4, 0x0001efb5}, + {0x00009fcc, 0x40000014}, + {0x00009fd0, 0x0a193b93}, + {0x0000a20c, 0x00000000}, + {0x0000a220, 0x00000000}, + {0x0000a224, 0x00000000}, + {0x0000a228, 0x10002310}, + {0x0000a23c, 0x00000000}, + {0x0000a244, 0x0c000000}, + {0x0000a2a0, 0x00000001}, + {0x0000a2c0, 0x00000001}, + {0x0000a2c8, 0x00000000}, + {0x0000a2cc, 0x18c43433}, + {0x0000a2d4, 0x00000000}, + {0x0000a2ec, 0x00000000}, + {0x0000a2f0, 0x00000000}, + {0x0000a2f4, 0x00000000}, + {0x0000a2f8, 0x00000000}, + {0x0000a344, 0x00000000}, + {0x0000a34c, 0x00000000}, + {0x0000a350, 0x0000a000}, + {0x0000a364, 0x00000000}, + {0x0000a370, 0x00000000}, + {0x0000a390, 0x00000001}, + {0x0000a394, 0x00000444}, + {0x0000a398, 0x001f0e0f}, + {0x0000a39c, 0x0075393f}, + {0x0000a3a0, 0xb79f6427}, + {0x0000a3c0, 0x20202020}, + {0x0000a3c4, 0x22222220}, + {0x0000a3c8, 0x20200020}, + {0x0000a3cc, 0x20202020}, + {0x0000a3d0, 0x20202020}, + {0x0000a3d4, 0x20202020}, + {0x0000a3d8, 0x20202020}, + {0x0000a3dc, 0x20202020}, + {0x0000a3e0, 0x20202020}, + {0x0000a3e4, 0x20202020}, + {0x0000a3e8, 0x20202020}, + {0x0000a3ec, 0x20202020}, + {0x0000a3f0, 0x00000000}, + {0x0000a3f4, 0x00000006}, + {0x0000a3f8, 0x0c9bd380}, + {0x0000a3fc, 0x000f0f01}, + {0x0000a400, 0x8fa91f01}, + {0x0000a404, 0x00000000}, + {0x0000a408, 0x0e79e5c6}, + {0x0000a40c, 0x00820820}, + {0x0000a414, 0x1ce739ce}, + {0x0000a418, 0x2d001dce}, + {0x0000a434, 0x00000000}, + {0x0000a438, 0x00001801}, + {0x0000a43c, 0x00100000}, + {0x0000a444, 0x00000000}, + {0x0000a448, 0x05000080}, + {0x0000a44c, 0x00000001}, + {0x0000a450, 0x00010000}, + {0x0000a454, 0x07000000}, + {0x0000a644, 0xbfad9d74}, + {0x0000a648, 0x0048060a}, + {0x0000a64c, 0x00002037}, + {0x0000a670, 0x03020100}, + {0x0000a674, 0x09080504}, + {0x0000a678, 0x0d0c0b0a}, + {0x0000a67c, 0x13121110}, + {0x0000a680, 0x31301514}, + {0x0000a684, 0x35343332}, + {0x0000a688, 0x00000036}, + {0x0000a690, 0x00000838}, + {0x0000a6b0, 0x0000000a}, + {0x0000a6b4, 0x00512c01}, + {0x0000a7c0, 0x00000000}, + {0x0000a7c4, 0xfffffffc}, + {0x0000a7c8, 0x00000000}, + {0x0000a7cc, 0x00000000}, + {0x0000a7d0, 0x00000000}, + {0x0000a7d4, 0x00000004}, + {0x0000a7dc, 0x00000000}, + {0x0000a7f0, 0x80000000}, + {0x0000a8d0, 0x004b6a8e}, + {0x0000a8d4, 0x00000820}, + {0x0000a8dc, 0x00000000}, + {0x0000a8f0, 0x00000000}, + {0x0000a8f4, 0x00000000}, + {0x0000abf0, 0x80000000}, + {0x0000b2d0, 0x00000080}, + {0x0000b2d4, 0x00000000}, + {0x0000b2ec, 0x00000000}, + {0x0000b2f0, 0x00000000}, + {0x0000b2f4, 0x00000000}, + {0x0000b2f8, 0x00000000}, + {0x0000b408, 0x0e79e5c0}, + {0x0000b40c, 0x00820820}, + {0x0000b420, 0x00000000}, + {0x0000b6b0, 0x0000000a}, + {0x0000b6b4, 0x00000001}, +}; + +static const u32 ar9462_2p0_radio_postamble[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524}, + {0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70}, + {0x0001610c, 0x48000000, 0x40000000, 0x40000000, 0x40000000}, + {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000}, +}; + +static const u32 ar9462_2p0_modes_mix_ob_db_tx_gain[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, + {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, + {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584}, + {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800}, + {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, + {0x0000a410, 0x0000d0da, 0x0000d0da, 0x0000d0de, 0x0000d0de}, + {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000}, + {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002}, + {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004}, + {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200}, + {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202}, + {0x0000a514, 0x18022622, 0x18022622, 0x12000400, 0x12000400}, + {0x0000a518, 0x1b022822, 0x1b022822, 0x16000402, 0x16000402}, + {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404}, + {0x0000a520, 0x22022c41, 0x22022c41, 0x1c000603, 0x1c000603}, + {0x0000a524, 0x28023042, 0x28023042, 0x21000a02, 0x21000a02}, + {0x0000a528, 0x2c023044, 0x2c023044, 0x25000a04, 0x25000a04}, + {0x0000a52c, 0x2f023644, 0x2f023644, 0x28000a20, 0x28000a20}, + {0x0000a530, 0x34025643, 0x34025643, 0x2c000e20, 0x2c000e20}, + {0x0000a534, 0x38025a44, 0x38025a44, 0x30000e22, 0x30000e22}, + {0x0000a538, 0x3b025e45, 0x3b025e45, 0x34000e24, 0x34000e24}, + {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x38001640, 0x38001640}, + {0x0000a540, 0x48025e6c, 0x48025e6c, 0x3c001660, 0x3c001660}, + {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3f001861, 0x3f001861}, + {0x0000a548, 0x55025eb3, 0x55025eb3, 0x43001a81, 0x43001a81}, + {0x0000a54c, 0x58025ef3, 0x58025ef3, 0x47001a83, 0x47001a83}, + {0x0000a550, 0x5d025ef6, 0x5d025ef6, 0x4a001c84, 0x4a001c84}, + {0x0000a554, 0x62025f56, 0x62025f56, 0x4e001ce3, 0x4e001ce3}, + {0x0000a558, 0x66027f56, 0x66027f56, 0x52001ce5, 0x52001ce5}, + {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x56001ce9, 0x56001ce9}, + {0x0000a560, 0x70049f56, 0x70049f56, 0x5a001ceb, 0x5a001ceb}, + {0x0000a564, 0x751ffff6, 0x751ffff6, 0x5c001eec, 0x5c001eec}, + {0x0000a568, 0x751ffff6, 0x751ffff6, 0x5e001ef0, 0x5e001ef0}, + {0x0000a56c, 0x751ffff6, 0x751ffff6, 0x60001ef4, 0x60001ef4}, + {0x0000a570, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6}, + {0x0000a574, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6}, + {0x0000a578, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6}, + {0x0000a57c, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6}, + {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000}, + {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000}, + {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501}, + {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501}, + {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03}, + {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04}, + {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04}, + {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, + {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, + {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, + {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, + {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, + {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, + {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584}, + {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800}, + {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, +}; + +static const u32 ar9462_2p0_modes_high_ob_db_tx_gain[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, + {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, + {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584}, + {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800}, + {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, + {0x0000a410, 0x000050da, 0x000050da, 0x000050de, 0x000050de}, + {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000}, + {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002}, + {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004}, + {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200}, + {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202}, + {0x0000a514, 0x18022622, 0x18022622, 0x11000400, 0x11000400}, + {0x0000a518, 0x1b022822, 0x1b022822, 0x15000402, 0x15000402}, + {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404}, + {0x0000a520, 0x22022c41, 0x22022c41, 0x1b000603, 0x1b000603}, + {0x0000a524, 0x28023042, 0x28023042, 0x1f000a02, 0x1f000a02}, + {0x0000a528, 0x2c023044, 0x2c023044, 0x23000a04, 0x23000a04}, + {0x0000a52c, 0x2f023644, 0x2f023644, 0x26000a20, 0x26000a20}, + {0x0000a530, 0x34025643, 0x34025643, 0x2a000e20, 0x2a000e20}, + {0x0000a534, 0x38025a44, 0x38025a44, 0x2e000e22, 0x2e000e22}, + {0x0000a538, 0x3b025e45, 0x3b025e45, 0x31000e24, 0x31000e24}, + {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x34001640, 0x34001640}, + {0x0000a540, 0x48025e6c, 0x48025e6c, 0x38001660, 0x38001660}, + {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3b001861, 0x3b001861}, + {0x0000a548, 0x55025eb3, 0x55025eb3, 0x3e001a81, 0x3e001a81}, + {0x0000a54c, 0x58025ef3, 0x58025ef3, 0x42001a83, 0x42001a83}, + {0x0000a550, 0x5d025ef6, 0x5d025ef6, 0x44001a84, 0x44001a84}, + {0x0000a554, 0x62025f56, 0x62025f56, 0x48001ce3, 0x48001ce3}, + {0x0000a558, 0x66027f56, 0x66027f56, 0x4c001ce5, 0x4c001ce5}, + {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x50001ce9, 0x50001ce9}, + {0x0000a560, 0x70049f56, 0x70049f56, 0x54001ceb, 0x54001ceb}, + {0x0000a564, 0x751ffff6, 0x751ffff6, 0x56001eec, 0x56001eec}, + {0x0000a568, 0x751ffff6, 0x751ffff6, 0x58001ef0, 0x58001ef0}, + {0x0000a56c, 0x751ffff6, 0x751ffff6, 0x5a001ef4, 0x5a001ef4}, + {0x0000a570, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6}, + {0x0000a574, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6}, + {0x0000a578, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6}, + {0x0000a57c, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6}, + {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000}, + {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000}, + {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501}, + {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501}, + {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03}, + {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04}, + {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04}, + {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, + {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, + {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, + {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, + {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, + {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, + {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584}, + {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800}, + {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, + {0x00016044, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4}, + {0x00016048, 0x8db49060, 0x8db49060, 0x8db49060, 0x8db49060}, + {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, + {0x00016444, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4}, + {0x00016448, 0x8db49000, 0x8db49000, 0x8db49000, 0x8db49000}, + {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, +}; + +static const u32 ar9462_2p0_radio_core[][2] = { + /* Addr allmodes */ + {0x00016000, 0x36db6db6}, + {0x00016004, 0x6db6db40}, + {0x00016008, 0x73f00000}, + {0x0001600c, 0x00000000}, + {0x00016010, 0x6d820001}, + {0x00016040, 0x7f80fff8}, + {0x0001604c, 0x2699e04f}, + {0x00016050, 0x6db6db6c}, + {0x00016058, 0x6c200000}, + {0x00016080, 0x000c0000}, + {0x00016084, 0x9a68048c}, + {0x00016088, 0x54214514}, + {0x0001608c, 0x1203040b}, + {0x00016090, 0x24926490}, + {0x00016098, 0xd2888888}, + {0x000160a0, 0x0a108ffe}, + {0x000160a4, 0x812fc491}, + {0x000160a8, 0x423c8000}, + {0x000160b4, 0x92000000}, + {0x000160b8, 0x0285dddc}, + {0x000160bc, 0x02908888}, + {0x000160c0, 0x00adb6d0}, + {0x000160c4, 0x6db6db60}, + {0x000160c8, 0x6db6db6c}, + {0x000160cc, 0x0de6c1b0}, + {0x00016100, 0x3fffbe04}, + {0x00016104, 0xfff80000}, + {0x00016108, 0x00200400}, + {0x00016110, 0x00000000}, + {0x00016144, 0x02084080}, + {0x00016148, 0x000080c0}, + {0x00016280, 0x050a0001}, + {0x00016284, 0x3d841418}, + {0x00016288, 0x00000000}, + {0x0001628c, 0xe3000000}, + {0x00016290, 0xa1005080}, + {0x00016294, 0x00000020}, + {0x00016298, 0x54a82900}, + {0x00016340, 0x121e4276}, + {0x00016344, 0x00300000}, + {0x00016400, 0x36db6db6}, + {0x00016404, 0x6db6db40}, + {0x00016408, 0x73f00000}, + {0x0001640c, 0x00000000}, + {0x00016410, 0x6c800001}, + {0x00016440, 0x7f80fff8}, + {0x0001644c, 0x4699e04f}, + {0x00016450, 0x6db6db6c}, + {0x00016500, 0x3fffbe04}, + {0x00016504, 0xfff80000}, + {0x00016508, 0x00200400}, + {0x00016510, 0x00000000}, + {0x00016544, 0x02084080}, + {0x00016548, 0x000080c0}, +}; + +static const u32 ar9462_2p0_soc_preamble[][2] = { + /* Addr allmodes */ + {0x000040a4, 0x00a0c1c9}, + {0x00007020, 0x00000000}, + {0x00007034, 0x00000002}, + {0x00007038, 0x000004c2}, +}; + +static const u32 ar9462_2p0_mac_core[][2] = { + /* Addr allmodes */ + {0x00000008, 0x00000000}, + {0x00000030, 0x000e0085}, + {0x00000034, 0x00000005}, + {0x00000040, 0x00000000}, + {0x00000044, 0x00000000}, + {0x00000048, 0x00000008}, + {0x0000004c, 0x00000010}, + {0x00000050, 0x00000000}, + {0x00001040, 0x002ffc0f}, + {0x00001044, 0x002ffc0f}, + {0x00001048, 0x002ffc0f}, + {0x0000104c, 0x002ffc0f}, + {0x00001050, 0x002ffc0f}, + {0x00001054, 0x002ffc0f}, + {0x00001058, 0x002ffc0f}, + {0x0000105c, 0x002ffc0f}, + {0x00001060, 0x002ffc0f}, + {0x00001064, 0x002ffc0f}, + {0x000010f0, 0x00000100}, + {0x00001270, 0x00000000}, + {0x000012b0, 0x00000000}, + {0x000012f0, 0x00000000}, + {0x0000143c, 0x00000000}, + {0x0000147c, 0x00000000}, + {0x00001810, 0x0f000003}, + {0x00008000, 0x00000000}, + {0x00008004, 0x00000000}, + {0x00008008, 0x00000000}, + {0x0000800c, 0x00000000}, + {0x00008018, 0x00000000}, + {0x00008020, 0x00000000}, + {0x00008038, 0x00000000}, + {0x0000803c, 0x00080000}, + {0x00008040, 0x00000000}, + {0x00008044, 0x00000000}, + {0x00008048, 0x00000000}, + {0x0000804c, 0xffffffff}, + {0x00008054, 0x00000000}, + {0x00008058, 0x00000000}, + {0x0000805c, 0x000fc78f}, + {0x00008060, 0x0000000f}, + {0x00008064, 0x00000000}, + {0x00008070, 0x00000310}, + {0x00008074, 0x00000020}, + {0x00008078, 0x00000000}, + {0x0000809c, 0x0000000f}, + {0x000080a0, 0x00000000}, + {0x000080a4, 0x02ff0000}, + {0x000080a8, 0x0e070605}, + {0x000080ac, 0x0000000d}, + {0x000080b0, 0x00000000}, + {0x000080b4, 0x00000000}, + {0x000080b8, 0x00000000}, + {0x000080bc, 0x00000000}, + {0x000080c0, 0x2a800000}, + {0x000080c4, 0x06900168}, + {0x000080c8, 0x13881c20}, + {0x000080cc, 0x01f40000}, + {0x000080d0, 0x00252500}, + {0x000080d4, 0x00b00005}, + {0x000080d8, 0x00400002}, + {0x000080dc, 0x00000000}, + {0x000080e0, 0xffffffff}, + {0x000080e4, 0x0000ffff}, + {0x000080e8, 0x3f3f3f3f}, + {0x000080ec, 0x00000000}, + {0x000080f0, 0x00000000}, + {0x000080f4, 0x00000000}, + {0x000080fc, 0x00020000}, + {0x00008100, 0x00000000}, + {0x00008108, 0x00000052}, + {0x0000810c, 0x00000000}, + {0x00008110, 0x00000000}, + {0x00008114, 0x000007ff}, + {0x00008118, 0x000000aa}, + {0x0000811c, 0x00003210}, + {0x00008124, 0x00000000}, + {0x00008128, 0x00000000}, + {0x0000812c, 0x00000000}, + {0x00008130, 0x00000000}, + {0x00008134, 0x00000000}, + {0x00008138, 0x00000000}, + {0x0000813c, 0x0000ffff}, + {0x00008144, 0xffffffff}, + {0x00008168, 0x00000000}, + {0x0000816c, 0x00000000}, + {0x00008170, 0x18486e00}, + {0x00008174, 0x33332210}, + {0x00008178, 0x00000000}, + {0x0000817c, 0x00020000}, + {0x000081c4, 0x33332210}, + {0x000081c8, 0x00000000}, + {0x000081cc, 0x00000000}, + {0x000081d4, 0x00000000}, + {0x000081ec, 0x00000000}, + {0x000081f0, 0x00000000}, + {0x000081f4, 0x00000000}, + {0x000081f8, 0x00000000}, + {0x000081fc, 0x00000000}, + {0x00008240, 0x00100000}, + {0x00008244, 0x0010f400}, + {0x00008248, 0x00000800}, + {0x0000824c, 0x0001e800}, + {0x00008250, 0x00000000}, + {0x00008254, 0x00000000}, + {0x00008258, 0x00000000}, + {0x0000825c, 0x40000000}, + {0x00008260, 0x00080922}, + {0x00008264, 0x99c00010}, + {0x00008268, 0xffffffff}, + {0x0000826c, 0x0000ffff}, + {0x00008270, 0x00000000}, + {0x00008274, 0x40000000}, + {0x00008278, 0x003e4180}, + {0x0000827c, 0x00000004}, + {0x00008284, 0x0000002c}, + {0x00008288, 0x0000002c}, + {0x0000828c, 0x000000ff}, + {0x00008294, 0x00000000}, + {0x00008298, 0x00000000}, + {0x0000829c, 0x00000000}, + {0x00008300, 0x00000140}, + {0x00008314, 0x00000000}, + {0x0000831c, 0x0000010d}, + {0x00008328, 0x00000000}, + {0x0000832c, 0x0000001f}, + {0x00008330, 0x00000302}, + {0x00008334, 0x00000700}, + {0x00008338, 0xffff0000}, + {0x0000833c, 0x02400000}, + {0x00008340, 0x000107ff}, + {0x00008344, 0xaa48105b}, + {0x00008348, 0x008f0000}, + {0x0000835c, 0x00000000}, + {0x00008360, 0xffffffff}, + {0x00008364, 0xffffffff}, + {0x00008368, 0x00000000}, + {0x00008370, 0x00000000}, + {0x00008374, 0x000000ff}, + {0x00008378, 0x00000000}, + {0x0000837c, 0x00000000}, + {0x00008380, 0xffffffff}, + {0x00008384, 0xffffffff}, + {0x00008390, 0xffffffff}, + {0x00008394, 0xffffffff}, + {0x00008398, 0x00000000}, + {0x0000839c, 0x00000000}, + {0x000083a4, 0x0000fa14}, + {0x000083a8, 0x000f0c00}, + {0x000083ac, 0x33332210}, + {0x000083b0, 0x33332210}, + {0x000083b4, 0x33332210}, + {0x000083b8, 0x33332210}, + {0x000083bc, 0x00000000}, + {0x000083c0, 0x00000000}, + {0x000083c4, 0x00000000}, + {0x000083c8, 0x00000000}, + {0x000083cc, 0x00000200}, + {0x000083d0, 0x000301ff}, +}; + +static const u32 ar9462_2p0_common_mixed_rx_gain[][2] = { + /* Addr allmodes */ + {0x0000a000, 0x00010000}, + {0x0000a004, 0x00030002}, + {0x0000a008, 0x00050004}, + {0x0000a00c, 0x00810080}, + {0x0000a010, 0x00830082}, + {0x0000a014, 0x01810180}, + {0x0000a018, 0x01830182}, + {0x0000a01c, 0x01850184}, + {0x0000a020, 0x01890188}, + {0x0000a024, 0x018b018a}, + {0x0000a028, 0x018d018c}, + {0x0000a02c, 0x03820190}, + {0x0000a030, 0x03840383}, + {0x0000a034, 0x03880385}, + {0x0000a038, 0x038a0389}, + {0x0000a03c, 0x038c038b}, + {0x0000a040, 0x0390038d}, + {0x0000a044, 0x03920391}, + {0x0000a048, 0x03940393}, + {0x0000a04c, 0x03960395}, + {0x0000a050, 0x00000000}, + {0x0000a054, 0x00000000}, + {0x0000a058, 0x00000000}, + {0x0000a05c, 0x00000000}, + {0x0000a060, 0x00000000}, + {0x0000a064, 0x00000000}, + {0x0000a068, 0x00000000}, + {0x0000a06c, 0x00000000}, + {0x0000a070, 0x00000000}, + {0x0000a074, 0x00000000}, + {0x0000a078, 0x00000000}, + {0x0000a07c, 0x00000000}, + {0x0000a080, 0x29292929}, + {0x0000a084, 0x29292929}, + {0x0000a088, 0x29292929}, + {0x0000a08c, 0x29292929}, + {0x0000a090, 0x22292929}, + {0x0000a094, 0x1d1d2222}, + {0x0000a098, 0x0c111117}, + {0x0000a09c, 0x00030303}, + {0x0000a0a0, 0x00000000}, + {0x0000a0a4, 0x00000000}, + {0x0000a0a8, 0x00000000}, + {0x0000a0ac, 0x00000000}, + {0x0000a0b0, 0x00000000}, + {0x0000a0b4, 0x00000000}, + {0x0000a0b8, 0x00000000}, + {0x0000a0bc, 0x00000000}, + {0x0000a0c0, 0x001f0000}, + {0x0000a0c4, 0x01000101}, + {0x0000a0c8, 0x011e011f}, + {0x0000a0cc, 0x011c011d}, + {0x0000a0d0, 0x02030204}, + {0x0000a0d4, 0x02010202}, + {0x0000a0d8, 0x021f0200}, + {0x0000a0dc, 0x0302021e}, + {0x0000a0e0, 0x03000301}, + {0x0000a0e4, 0x031e031f}, + {0x0000a0e8, 0x0402031d}, + {0x0000a0ec, 0x04000401}, + {0x0000a0f0, 0x041e041f}, + {0x0000a0f4, 0x0502041d}, + {0x0000a0f8, 0x05000501}, + {0x0000a0fc, 0x051e051f}, + {0x0000a100, 0x06010602}, + {0x0000a104, 0x061f0600}, + {0x0000a108, 0x061d061e}, + {0x0000a10c, 0x07020703}, + {0x0000a110, 0x07000701}, + {0x0000a114, 0x00000000}, + {0x0000a118, 0x00000000}, + {0x0000a11c, 0x00000000}, + {0x0000a120, 0x00000000}, + {0x0000a124, 0x00000000}, + {0x0000a128, 0x00000000}, + {0x0000a12c, 0x00000000}, + {0x0000a130, 0x00000000}, + {0x0000a134, 0x00000000}, + {0x0000a138, 0x00000000}, + {0x0000a13c, 0x00000000}, + {0x0000a140, 0x001f0000}, + {0x0000a144, 0x01000101}, + {0x0000a148, 0x011e011f}, + {0x0000a14c, 0x011c011d}, + {0x0000a150, 0x02030204}, + {0x0000a154, 0x02010202}, + {0x0000a158, 0x021f0200}, + {0x0000a15c, 0x0302021e}, + {0x0000a160, 0x03000301}, + {0x0000a164, 0x031e031f}, + {0x0000a168, 0x0402031d}, + {0x0000a16c, 0x04000401}, + {0x0000a170, 0x041e041f}, + {0x0000a174, 0x0502041d}, + {0x0000a178, 0x05000501}, + {0x0000a17c, 0x051e051f}, + {0x0000a180, 0x06010602}, + {0x0000a184, 0x061f0600}, + {0x0000a188, 0x061d061e}, + {0x0000a18c, 0x07020703}, + {0x0000a190, 0x07000701}, + {0x0000a194, 0x00000000}, + {0x0000a198, 0x00000000}, + {0x0000a19c, 0x00000000}, + {0x0000a1a0, 0x00000000}, + {0x0000a1a4, 0x00000000}, + {0x0000a1a8, 0x00000000}, + {0x0000a1ac, 0x00000000}, + {0x0000a1b0, 0x00000000}, + {0x0000a1b4, 0x00000000}, + {0x0000a1b8, 0x00000000}, + {0x0000a1bc, 0x00000000}, + {0x0000a1c0, 0x00000000}, + {0x0000a1c4, 0x00000000}, + {0x0000a1c8, 0x00000000}, + {0x0000a1cc, 0x00000000}, + {0x0000a1d0, 0x00000000}, + {0x0000a1d4, 0x00000000}, + {0x0000a1d8, 0x00000000}, + {0x0000a1dc, 0x00000000}, + {0x0000a1e0, 0x00000000}, + {0x0000a1e4, 0x00000000}, + {0x0000a1e8, 0x00000000}, + {0x0000a1ec, 0x00000000}, + {0x0000a1f0, 0x00000396}, + {0x0000a1f4, 0x00000396}, + {0x0000a1f8, 0x00000396}, + {0x0000a1fc, 0x00000196}, + {0x0000b000, 0x00010000}, + {0x0000b004, 0x00030002}, + {0x0000b008, 0x00050004}, + {0x0000b00c, 0x00810080}, + {0x0000b010, 0x00830082}, + {0x0000b014, 0x01810180}, + {0x0000b018, 0x01830182}, + {0x0000b01c, 0x01850184}, + {0x0000b020, 0x02810280}, + {0x0000b024, 0x02830282}, + {0x0000b028, 0x02850284}, + {0x0000b02c, 0x02890288}, + {0x0000b030, 0x028b028a}, + {0x0000b034, 0x0388028c}, + {0x0000b038, 0x038a0389}, + {0x0000b03c, 0x038c038b}, + {0x0000b040, 0x0390038d}, + {0x0000b044, 0x03920391}, + {0x0000b048, 0x03940393}, + {0x0000b04c, 0x03960395}, + {0x0000b050, 0x00000000}, + {0x0000b054, 0x00000000}, + {0x0000b058, 0x00000000}, + {0x0000b05c, 0x00000000}, + {0x0000b060, 0x00000000}, + {0x0000b064, 0x00000000}, + {0x0000b068, 0x00000000}, + {0x0000b06c, 0x00000000}, + {0x0000b070, 0x00000000}, + {0x0000b074, 0x00000000}, + {0x0000b078, 0x00000000}, + {0x0000b07c, 0x00000000}, + {0x0000b080, 0x2a2d2f32}, + {0x0000b084, 0x21232328}, + {0x0000b088, 0x19191c1e}, + {0x0000b08c, 0x12141417}, + {0x0000b090, 0x07070e0e}, + {0x0000b094, 0x03030305}, + {0x0000b098, 0x00000003}, + {0x0000b09c, 0x00000000}, + {0x0000b0a0, 0x00000000}, + {0x0000b0a4, 0x00000000}, + {0x0000b0a8, 0x00000000}, + {0x0000b0ac, 0x00000000}, + {0x0000b0b0, 0x00000000}, + {0x0000b0b4, 0x00000000}, + {0x0000b0b8, 0x00000000}, + {0x0000b0bc, 0x00000000}, + {0x0000b0c0, 0x003f0020}, + {0x0000b0c4, 0x00400041}, + {0x0000b0c8, 0x0140005f}, + {0x0000b0cc, 0x0160015f}, + {0x0000b0d0, 0x017e017f}, + {0x0000b0d4, 0x02410242}, + {0x0000b0d8, 0x025f0240}, + {0x0000b0dc, 0x027f0260}, + {0x0000b0e0, 0x0341027e}, + {0x0000b0e4, 0x035f0340}, + {0x0000b0e8, 0x037f0360}, + {0x0000b0ec, 0x04400441}, + {0x0000b0f0, 0x0460045f}, + {0x0000b0f4, 0x0541047f}, + {0x0000b0f8, 0x055f0540}, + {0x0000b0fc, 0x057f0560}, + {0x0000b100, 0x06400641}, + {0x0000b104, 0x0660065f}, + {0x0000b108, 0x067e067f}, + {0x0000b10c, 0x07410742}, + {0x0000b110, 0x075f0740}, + {0x0000b114, 0x077f0760}, + {0x0000b118, 0x07800781}, + {0x0000b11c, 0x07a0079f}, + {0x0000b120, 0x07c107bf}, + {0x0000b124, 0x000007c0}, + {0x0000b128, 0x00000000}, + {0x0000b12c, 0x00000000}, + {0x0000b130, 0x00000000}, + {0x0000b134, 0x00000000}, + {0x0000b138, 0x00000000}, + {0x0000b13c, 0x00000000}, + {0x0000b140, 0x003f0020}, + {0x0000b144, 0x00400041}, + {0x0000b148, 0x0140005f}, + {0x0000b14c, 0x0160015f}, + {0x0000b150, 0x017e017f}, + {0x0000b154, 0x02410242}, + {0x0000b158, 0x025f0240}, + {0x0000b15c, 0x027f0260}, + {0x0000b160, 0x0341027e}, + {0x0000b164, 0x035f0340}, + {0x0000b168, 0x037f0360}, + {0x0000b16c, 0x04400441}, + {0x0000b170, 0x0460045f}, + {0x0000b174, 0x0541047f}, + {0x0000b178, 0x055f0540}, + {0x0000b17c, 0x057f0560}, + {0x0000b180, 0x06400641}, + {0x0000b184, 0x0660065f}, + {0x0000b188, 0x067e067f}, + {0x0000b18c, 0x07410742}, + {0x0000b190, 0x075f0740}, + {0x0000b194, 0x077f0760}, + {0x0000b198, 0x07800781}, + {0x0000b19c, 0x07a0079f}, + {0x0000b1a0, 0x07c107bf}, + {0x0000b1a4, 0x000007c0}, + {0x0000b1a8, 0x00000000}, + {0x0000b1ac, 0x00000000}, + {0x0000b1b0, 0x00000000}, + {0x0000b1b4, 0x00000000}, + {0x0000b1b8, 0x00000000}, + {0x0000b1bc, 0x00000000}, + {0x0000b1c0, 0x00000000}, + {0x0000b1c4, 0x00000000}, + {0x0000b1c8, 0x00000000}, + {0x0000b1cc, 0x00000000}, + {0x0000b1d0, 0x00000000}, + {0x0000b1d4, 0x00000000}, + {0x0000b1d8, 0x00000000}, + {0x0000b1dc, 0x00000000}, + {0x0000b1e0, 0x00000000}, + {0x0000b1e4, 0x00000000}, + {0x0000b1e8, 0x00000000}, + {0x0000b1ec, 0x00000000}, + {0x0000b1f0, 0x00000396}, + {0x0000b1f4, 0x00000396}, + {0x0000b1f8, 0x00000396}, + {0x0000b1fc, 0x00000196}, +}; + +static const u32 ar9462_2p0_baseband_postamble_5g_xlna[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282}, +}; + +static const u32 ar9462_2p0_baseband_core_mix_rxgain[][2] = { + /* Addr allmodes */ + {0x00009fd0, 0x0a2d6b93}, +}; + +static const u32 ar9462_2p0_baseband_postamble_mix_rxgain[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x00009820, 0x206a022e, 0x206a022e, 0x206a01ae, 0x206a01ae}, + {0x00009824, 0x63c640de, 0x5ac640d0, 0x63c640da, 0x63c640da}, + {0x00009828, 0x0796be89, 0x0696b081, 0x0916be81, 0x0916be81}, + {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000d8, 0x6c4000d8}, + {0x00009e10, 0x92c88d2e, 0x7ec88d2e, 0x7ec86d2e, 0x7ec86d2e}, + {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3236605e, 0x32395c5e}, +}; + +#endif /* INITVALS_9462_2P0_H */ Property changes on: head/sys/contrib/dev/ath/ath_hal/ar9300/ar9462_2p0_initvals.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/contrib/dev/ath/ath_hal/ar9300/ar9462_2p1_initvals.h =================================================================== --- head/sys/contrib/dev/ath/ath_hal/ar9300/ar9462_2p1_initvals.h (nonexistent) +++ head/sys/contrib/dev/ath/ath_hal/ar9300/ar9462_2p1_initvals.h (revision 291433) @@ -0,0 +1,291 @@ +/* + * Copyright (c) 2010-2011 Atheros Communications Inc. + * Copyright (c) 2011-2012 Qualcomm Atheros Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef INITVALS_9462_2P1_H +#define INITVALS_9462_2P1_H + +/* AR9462 2.1 */ + +#define ar9462_2p1_mac_postamble ar9462_2p0_mac_postamble + +#define ar9462_2p1_baseband_core ar9462_2p0_baseband_core + +#define ar9462_2p1_radio_core ar9462_2p0_radio_core + +#define ar9462_2p1_radio_postamble ar9462_2p0_radio_postamble + +#define ar9462_2p1_soc_postamble ar9462_2p0_soc_postamble + +#define ar9462_2p1_radio_postamble_sys2ant ar9462_2p0_radio_postamble_sys2ant + +#define ar9462_2p1_common_rx_gain ar9462_2p0_common_rx_gain + +#define ar9462_2p1_common_mixed_rx_gain ar9462_2p0_common_mixed_rx_gain + +#define ar9462_2p1_common_5g_xlna_only_rxgain ar9462_2p0_common_5g_xlna_only_rxgain + +#define ar9462_2p1_baseband_core_mix_rxgain ar9462_2p0_baseband_core_mix_rxgain + +#define ar9462_2p1_baseband_postamble_mix_rxgain ar9462_2p0_baseband_postamble_mix_rxgain + +#define ar9462_2p1_baseband_postamble_5g_xlna ar9462_2p0_baseband_postamble_5g_xlna + +#define ar9462_2p1_common_wo_xlna_rx_gain ar9462_2p0_common_wo_xlna_rx_gain + +#define ar9462_2p1_modes_low_ob_db_tx_gain ar9462_2p0_modes_low_ob_db_tx_gain + +#define ar9462_2p1_modes_high_ob_db_tx_gain ar9462_2p0_modes_high_ob_db_tx_gain + +#define ar9462_2p1_modes_mix_ob_db_tx_gain ar9462_2p0_modes_mix_ob_db_tx_gain + +#define ar9462_2p1_modes_fast_clock ar9462_2p0_modes_fast_clock + +#define ar9462_2p1_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484 + +#define ar9462_2p1_pciephy_clkreq_disable_L1 ar9462_2p0_pciephy_clkreq_disable_L1 + +static const u32 ar9462_2p1_mac_core[][2] = { + /* Addr allmodes */ + {0x00000008, 0x00000000}, + {0x00000030, 0x000e0085}, + {0x00000034, 0x00000005}, + {0x00000040, 0x00000000}, + {0x00000044, 0x00000000}, + {0x00000048, 0x00000008}, + {0x0000004c, 0x00000010}, + {0x00000050, 0x00000000}, + {0x00001040, 0x002ffc0f}, + {0x00001044, 0x002ffc0f}, + {0x00001048, 0x002ffc0f}, + {0x0000104c, 0x002ffc0f}, + {0x00001050, 0x002ffc0f}, + {0x00001054, 0x002ffc0f}, + {0x00001058, 0x002ffc0f}, + {0x0000105c, 0x002ffc0f}, + {0x00001060, 0x002ffc0f}, + {0x00001064, 0x002ffc0f}, + {0x000010f0, 0x00000100}, + {0x00001270, 0x00000000}, + {0x000012b0, 0x00000000}, + {0x000012f0, 0x00000000}, + {0x0000143c, 0x00000000}, + {0x0000147c, 0x00000000}, + {0x00001810, 0x0f000003}, + {0x00008000, 0x00000000}, + {0x00008004, 0x00000000}, + {0x00008008, 0x00000000}, + {0x0000800c, 0x00000000}, + {0x00008018, 0x00000000}, + {0x00008020, 0x00000000}, + {0x00008038, 0x00000000}, + {0x0000803c, 0x00080000}, + {0x00008040, 0x00000000}, + {0x00008044, 0x00000000}, + {0x00008048, 0x00000000}, + {0x0000804c, 0xffffffff}, + {0x00008054, 0x00000000}, + {0x00008058, 0x00000000}, + {0x0000805c, 0x000fc78f}, + {0x00008060, 0x0000000f}, + {0x00008064, 0x00000000}, + {0x00008070, 0x00000310}, + {0x00008074, 0x00000020}, + {0x00008078, 0x00000000}, + {0x0000809c, 0x0000000f}, + {0x000080a0, 0x00000000}, + {0x000080a4, 0x02ff0000}, + {0x000080a8, 0x0e070605}, + {0x000080ac, 0x0000000d}, + {0x000080b0, 0x00000000}, + {0x000080b4, 0x00000000}, + {0x000080b8, 0x00000000}, + {0x000080bc, 0x00000000}, + {0x000080c0, 0x2a800000}, + {0x000080c4, 0x06900168}, + {0x000080c8, 0x13881c20}, + {0x000080cc, 0x01f40000}, + {0x000080d0, 0x00252500}, + {0x000080d4, 0x00b00005}, + {0x000080d8, 0x00400002}, + {0x000080dc, 0x00000000}, + {0x000080e0, 0xffffffff}, + {0x000080e4, 0x0000ffff}, + {0x000080e8, 0x3f3f3f3f}, + {0x000080ec, 0x00000000}, + {0x000080f0, 0x00000000}, + {0x000080f4, 0x00000000}, + {0x000080fc, 0x00020000}, + {0x00008100, 0x00000000}, + {0x00008108, 0x00000052}, + {0x0000810c, 0x00000000}, + {0x00008110, 0x00000000}, + {0x00008114, 0x000007ff}, + {0x00008118, 0x000000aa}, + {0x0000811c, 0x00003210}, + {0x00008124, 0x00000000}, + {0x00008128, 0x00000000}, + {0x0000812c, 0x00000000}, + {0x00008130, 0x00000000}, + {0x00008134, 0x00000000}, + {0x00008138, 0x00000000}, + {0x0000813c, 0x0000ffff}, + {0x00008144, 0xffffffff}, + {0x00008168, 0x00000000}, + {0x0000816c, 0x00000000}, + {0x00008170, 0x18486e00}, + {0x00008174, 0x33332210}, + {0x00008178, 0x00000000}, + {0x0000817c, 0x00020000}, + {0x000081c4, 0x33332210}, + {0x000081c8, 0x00000000}, + {0x000081cc, 0x00000000}, + {0x000081d4, 0x00000000}, + {0x000081ec, 0x00000000}, + {0x000081f0, 0x00000000}, + {0x000081f4, 0x00000000}, + {0x000081f8, 0x00000000}, + {0x000081fc, 0x00000000}, + {0x00008240, 0x00100000}, + {0x00008244, 0x0010f400}, + {0x00008248, 0x00000800}, + {0x0000824c, 0x0001e800}, + {0x00008250, 0x00000000}, + {0x00008254, 0x00000000}, + {0x00008258, 0x00000000}, + {0x0000825c, 0x40000000}, + {0x00008260, 0x00080922}, + {0x00008264, 0x99c00010}, + {0x00008268, 0xffffffff}, + {0x0000826c, 0x0000ffff}, + {0x00008270, 0x00000000}, + {0x00008274, 0x40000000}, + {0x00008278, 0x003e4180}, + {0x0000827c, 0x00000004}, + {0x00008284, 0x0000002c}, + {0x00008288, 0x0000002c}, + {0x0000828c, 0x000000ff}, + {0x00008294, 0x00000000}, + {0x00008298, 0x00000000}, + {0x0000829c, 0x00000000}, + {0x00008300, 0x00000140}, + {0x00008314, 0x00000000}, + {0x0000831c, 0x0000010d}, + {0x00008328, 0x00000000}, + {0x0000832c, 0x0000001f}, + {0x00008330, 0x00000302}, + {0x00008334, 0x00000700}, + {0x00008338, 0xffff0000}, + {0x0000833c, 0x02400000}, + {0x00008340, 0x000107ff}, + {0x00008344, 0xaa48107b}, + {0x00008348, 0x008f0000}, + {0x0000835c, 0x00000000}, + {0x00008360, 0xffffffff}, + {0x00008364, 0xffffffff}, + {0x00008368, 0x00000000}, + {0x00008370, 0x00000000}, + {0x00008374, 0x000000ff}, + {0x00008378, 0x00000000}, + {0x0000837c, 0x00000000}, + {0x00008380, 0xffffffff}, + {0x00008384, 0xffffffff}, + {0x00008390, 0xffffffff}, + {0x00008394, 0xffffffff}, + {0x00008398, 0x00000000}, + {0x0000839c, 0x00000000}, + {0x000083a4, 0x0000fa14}, + {0x000083a8, 0x000f0c00}, + {0x000083ac, 0x33332210}, + {0x000083b0, 0x33332210}, + {0x000083b4, 0x33332210}, + {0x000083b8, 0x33332210}, + {0x000083bc, 0x00000000}, + {0x000083c0, 0x00000000}, + {0x000083c4, 0x00000000}, + {0x000083c8, 0x00000000}, + {0x000083cc, 0x00000200}, + {0x000083d0, 0x000301ff}, +}; + +static const u32 ar9462_2p1_baseband_postamble[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a800d}, + {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a01ae}, + {0x00009824, 0x63c640de, 0x5ac640d0, 0x5ac640d0, 0x63c640da}, + {0x00009828, 0x0796be89, 0x0696b081, 0x0696b881, 0x09143e81}, + {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4}, + {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c}, + {0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4}, + {0x00009e00, 0x0372111a, 0x0372111a, 0x037216a0, 0x037216a2}, + {0x00009e04, 0x001c2020, 0x001c2020, 0x001c2020, 0x001c2020}, + {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000d8}, + {0x00009e10, 0x92c88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec86d2e}, + {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3236605e, 0x32365a5e}, + {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c}, + {0x00009e20, 0x000003a5, 0x000003a5, 0x000003a5, 0x000003a5}, + {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021}, + {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282}, + {0x00009e44, 0x62321e27, 0x62321e27, 0xfe291e27, 0xfe291e27}, + {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012}, + {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000}, + {0x0000a204, 0x01318fc0, 0x01318fc4, 0x01318fc4, 0x01318fc0}, + {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004}, + {0x0000a22c, 0x01026a2f, 0x01026a27, 0x01026a2f, 0x01026a2f}, + {0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b}, + {0x0000a234, 0x00000fff, 0x10000fff, 0x10000fff, 0x00000fff}, + {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018}, + {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108}, + {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898}, + {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002}, + {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e}, + {0x0000a260, 0x0a021501, 0x0a021501, 0x3a021501, 0x3a021501}, + {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, + {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b}, + {0x0000a284, 0x00000000, 0x00000000, 0x00000150, 0x00000150}, + {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110}, + {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222}, + {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18}, + {0x0000a2d0, 0x00041981, 0x00041981, 0x00041981, 0x00041982}, + {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b}, + {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a3a4, 0x00000050, 0x00000050, 0x00000000, 0x00000000}, + {0x0000a3a8, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa}, + {0x0000a3ac, 0xaaaaaa00, 0xaa30aa30, 0xaaaaaa00, 0xaaaaaa00}, + {0x0000a41c, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce}, + {0x0000a420, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce}, + {0x0000a424, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce}, + {0x0000a428, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce}, + {0x0000a42c, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce}, + {0x0000a430, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce}, + {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c}, + {0x0000ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x00100000}, + {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c}, + {0x0000ae20, 0x000001a6, 0x000001a6, 0x000001aa, 0x000001aa}, + {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550}, +}; + +static const u32 ar9462_2p1_soc_preamble[][2] = { + /* Addr allmodes */ + {0x000040a4, 0x00a0c9c9}, + {0x00007020, 0x00000000}, + {0x00007034, 0x00000002}, + {0x00007038, 0x000004c2}, +}; + +#endif /* INITVALS_9462_2P1_H */ Property changes on: head/sys/contrib/dev/ath/ath_hal/ar9300/ar9462_2p1_initvals.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property