Index: stable/10/sys/arm/freescale/imx/imx_i2c.c =================================================================== --- stable/10/sys/arm/freescale/imx/imx_i2c.c (revision 289665) +++ stable/10/sys/arm/freescale/imx/imx_i2c.c (revision 289666) @@ -1,531 +1,482 @@ /*- * Copyright (C) 2008-2009 Semihalf, Michal Hajduk * Copyright (c) 2012, 2013 The FreeBSD Foundation + * Copyright (c) 2015 Ian Lepore * All rights reserved. * * Portions of this software were developed by Oleksandr Rybalko * under sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ +/* + * I2C driver for Freescale i.MX hardware. + * + * Note that the hardware is capable of running as both a master and a slave. + * This driver currently implements only master-mode operations. + * + * This driver supports multi-master i2c busses, by detecting bus arbitration + * loss and returning IIC_EBUSBSY status. Notably, it does not do any kind of + * retries if some other master jumps onto the bus and interrupts one of our + * transfer cycles resulting in arbitration loss in mid-transfer. The caller + * must handle retries in a way that makes sense for the slave being addressed. + */ + #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include -#include -#include - #include #include #include #include "iicbus_if.h" #include #include #include #include #define I2C_ADDR_REG 0x00 /* I2C slave address register */ #define I2C_FDR_REG 0x04 /* I2C frequency divider register */ #define I2C_CONTROL_REG 0x08 /* I2C control register */ #define I2C_STATUS_REG 0x0C /* I2C status register */ #define I2C_DATA_REG 0x10 /* I2C data register */ #define I2C_DFSRR_REG 0x14 /* I2C Digital Filter Sampling rate */ #define I2CCR_MEN (1 << 7) /* Module enable */ #define I2CCR_MSTA (1 << 5) /* Master/slave mode */ #define I2CCR_MTX (1 << 4) /* Transmit/receive mode */ #define I2CCR_TXAK (1 << 3) /* Transfer acknowledge */ #define I2CCR_RSTA (1 << 2) /* Repeated START */ #define I2CSR_MCF (1 << 7) /* Data transfer */ #define I2CSR_MASS (1 << 6) /* Addressed as a slave */ #define I2CSR_MBB (1 << 5) /* Bus busy */ #define I2CSR_MAL (1 << 4) /* Arbitration lost */ #define I2CSR_SRW (1 << 2) /* Slave read/write */ #define I2CSR_MIF (1 << 1) /* Module interrupt */ #define I2CSR_RXAK (1 << 0) /* Received acknowledge */ #define I2C_BAUD_RATE_FAST 0x31 #define I2C_BAUD_RATE_DEF 0x3F #define I2C_DFSSR_DIV 0x10 /* * A table of available divisors and the associated coded values to put in the * FDR register to achieve that divisor.. There is no algorithmic relationship I * can see between divisors and the codes that go into the register. The table * begins and ends with entries that handle insane configuration values. */ struct clkdiv { u_int divisor; u_int regcode; }; static struct clkdiv clkdiv_table[] = { { 0, 0x20 }, { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2a }, { 72, 0x2b }, { 80, 0x2c }, { 88, 0x09 }, { 96, 0x2d }, { 104, 0x0a }, { 112, 0x2e }, { 128, 0x2f }, { 144, 0x0c }, { 160, 0x30 }, { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0f }, { 256, 0x33 }, { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, { 768, 0x39 }, { 896, 0x3a }, { 960, 0x17 }, { 1024, 0x3b }, { 1152, 0x18 }, { 1280, 0x3c }, { 1536, 0x3d }, { 1792, 0x3e }, { 1920, 0x1b }, { 2048, 0x3f }, { 2304, 0x1c }, { 2560, 0x1d }, { 3072, 0x1e }, { 3840, 0x1f }, {UINT_MAX, 0x1f} }; -#ifdef DEBUG -#define debugf(fmt, args...) do { printf("%s(): ", __func__); \ - printf(fmt,##args); } while (0) -#else -#define debugf(fmt, args...) -#endif - static struct ofw_compat_data compat_data[] = { {"fsl,imx6q-i2c", 1}, {"fsl,imx-i2c", 1}, {NULL, 0} }; struct i2c_softc { device_t dev; device_t iicbus; struct resource *res; - struct mtx mutex; int rid; - bus_space_handle_t bsh; - bus_space_tag_t bst; + sbintime_t byte_time_sbt; }; static phandle_t i2c_get_node(device_t, device_t); static int i2c_probe(device_t); static int i2c_attach(device_t); static int i2c_repeated_start(device_t, u_char, int); static int i2c_start(device_t, u_char, int); static int i2c_stop(device_t); static int i2c_reset(device_t, u_char, u_char, u_char *); static int i2c_read(device_t, char *, int, int *, int, int); static int i2c_write(device_t, const char *, int, int *, int); static device_method_t i2c_methods[] = { DEVMETHOD(device_probe, i2c_probe), DEVMETHOD(device_attach, i2c_attach), /* OFW methods */ DEVMETHOD(ofw_bus_get_node, i2c_get_node), DEVMETHOD(iicbus_callback, iicbus_null_callback), DEVMETHOD(iicbus_repeated_start, i2c_repeated_start), DEVMETHOD(iicbus_start, i2c_start), DEVMETHOD(iicbus_stop, i2c_stop), DEVMETHOD(iicbus_reset, i2c_reset), DEVMETHOD(iicbus_read, i2c_read), DEVMETHOD(iicbus_write, i2c_write), DEVMETHOD(iicbus_transfer, iicbus_transfer_gen), - { 0, 0 } + DEVMETHOD_END }; static driver_t i2c_driver = { "iichb", i2c_methods, sizeof(struct i2c_softc), }; static devclass_t i2c_devclass; DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0); DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0); static phandle_t i2c_get_node(device_t bus, device_t dev) { /* * Share controller node with iicbus device */ return ofw_bus_get_node(bus); } static __inline void i2c_write_reg(struct i2c_softc *sc, bus_size_t off, uint8_t val) { - bus_space_write_1(sc->bst, sc->bsh, off, val); + bus_write_1(sc->res, off, val); } static __inline uint8_t i2c_read_reg(struct i2c_softc *sc, bus_size_t off) { - return (bus_space_read_1(sc->bst, sc->bsh, off)); + return (bus_read_1(sc->res, off)); } static __inline void i2c_flag_set(struct i2c_softc *sc, bus_size_t off, uint8_t mask) { uint8_t status; status = i2c_read_reg(sc, off); status |= mask; i2c_write_reg(sc, off, status); } -/* Wait for transfer interrupt flag */ +/* Wait for bus to become busy or not-busy. */ static int -wait_for_iif(struct i2c_softc *sc) +wait_for_busbusy(struct i2c_softc *sc, int wantbusy) { - int retry; + int retry, srb; retry = 1000; while (retry --) { - if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MIF) + srb = i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB; + if ((srb && wantbusy) || (!srb && !wantbusy)) return (IIC_NOERR); - DELAY(10); + DELAY(1); } - return (IIC_ETIMEOUT); } -/* Wait for free bus */ +/* Wait for transfer to complete, optionally check RXAK. */ static int -wait_for_nibb(struct i2c_softc *sc) +wait_for_xfer(struct i2c_softc *sc, int checkack) { - int retry; + int retry, sr; - retry = 1000; + /* + * Sleep for about the time it takes to transfer a byte (with precision + * set to tolerate 5% oversleep). We calculate the approximate byte + * transfer time when we set the bus speed divisor. Slaves are allowed + * to do clock-stretching so the actual transfer time can be larger, but + * this gets the bulk of the waiting out of the way without tying up the + * processor the whole time. + */ + pause_sbt("imxi2c", sc->byte_time_sbt, sc->byte_time_sbt / 20, 0); + + retry = 10000; while (retry --) { - if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0) - return (IIC_NOERR); - DELAY(10); + sr = i2c_read_reg(sc, I2C_STATUS_REG); + if (sr & I2CSR_MIF) { + if (sr & I2CSR_MAL) + return (IIC_EBUSERR); + else if (checkack && (sr & I2CSR_RXAK)) + return (IIC_ENOACK); + else + return (IIC_NOERR); + } + DELAY(1); } - return (IIC_ETIMEOUT); } -/* Wait for transfer complete+interrupt flag */ +/* + * Implement the error handling shown in the state diagram of the imx6 reference + * manual. If there was an error, then: + * - Clear master mode (MSTA and MTX). + * - Wait for the bus to become free or for a timeout to happen. + * - Disable the controller. + */ static int -wait_for_icf(struct i2c_softc *sc) +i2c_error_handler(struct i2c_softc *sc, int error) { - int retry; - retry = 1000; - while (retry --) { - - if ((i2c_read_reg(sc, I2C_STATUS_REG) & - (I2CSR_MCF|I2CSR_MIF)) == (I2CSR_MCF|I2CSR_MIF)) - return (IIC_NOERR); - DELAY(10); + if (error != 0) { + i2c_write_reg(sc, I2C_STATUS_REG, 0); + i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); + wait_for_busbusy(sc, false); + i2c_write_reg(sc, I2C_CONTROL_REG, 0); } - - return (IIC_ETIMEOUT); + return (error); } static int i2c_probe(device_t dev) { - struct i2c_softc *sc; if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); - sc = device_get_softc(dev); - sc->rid = 0; + device_set_desc(dev, "Freescale i.MX I2C"); - sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid, - RF_ACTIVE); - if (sc->res == NULL) { - device_printf(dev, "could not allocate resources\n"); - return (ENXIO); - } - - sc->bst = rman_get_bustag(sc->res); - sc->bsh = rman_get_bushandle(sc->res); - - /* Enable I2C */ - i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); - bus_release_resource(dev, SYS_RES_MEMORY, sc->rid, sc->res); - device_set_desc(dev, "Freescale i.MX I2C bus controller"); - return (BUS_PROBE_DEFAULT); } static int i2c_attach(device_t dev) { struct i2c_softc *sc; sc = device_get_softc(dev); sc->dev = dev; sc->rid = 0; - mtx_init(&sc->mutex, device_get_nameunit(dev), "I2C", MTX_DEF); - sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid, RF_ACTIVE); if (sc->res == NULL) { device_printf(dev, "could not allocate resources"); - mtx_destroy(&sc->mutex); return (ENXIO); } - sc->bst = rman_get_bustag(sc->res); - sc->bsh = rman_get_bushandle(sc->res); - sc->iicbus = device_add_child(dev, "iicbus", -1); if (sc->iicbus == NULL) { device_printf(dev, "could not add iicbus child"); - mtx_destroy(&sc->mutex); return (ENXIO); } bus_generic_attach(dev); - return (IIC_NOERR); + return (0); } static int i2c_repeated_start(device_t dev, u_char slave, int timeout) { struct i2c_softc *sc; int error; sc = device_get_softc(dev); - mtx_lock(&sc->mutex); - - i2c_write_reg(sc, I2C_ADDR_REG, slave); if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0) { - mtx_unlock(&sc->mutex); - return (IIC_EBUSBSY); + return (IIC_EBUSERR); } - /* Set repeated start condition */ - DELAY(10); + /* + * Set repeated start condition, delay (per reference manual, min 156nS) + * before writing slave address, wait for ack after write. + */ i2c_flag_set(sc, I2C_CONTROL_REG, I2CCR_RSTA); - DELAY(10); - /* Clear status */ + DELAY(1); i2c_write_reg(sc, I2C_STATUS_REG, 0x0); - /* Write target address - LSB is R/W bit */ i2c_write_reg(sc, I2C_DATA_REG, slave); - - error = wait_for_iif(sc); - - /* Clear status */ - i2c_write_reg(sc, I2C_STATUS_REG, 0x0); - - mtx_unlock(&sc->mutex); - - if (error) - return (error); - - return (IIC_NOERR); + error = wait_for_xfer(sc, true); + return (i2c_error_handler(sc, error)); } static int i2c_start(device_t dev, u_char slave, int timeout) { struct i2c_softc *sc; int error; sc = device_get_softc(dev); - mtx_lock(&sc->mutex); - i2c_write_reg(sc, I2C_ADDR_REG, slave); + i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); + DELAY(10); /* Delay for controller to sample bus state. */ if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) { - mtx_unlock(&sc->mutex); - return (IIC_EBUSBSY); + return (i2c_error_handler(sc, IIC_EBUSERR)); } - - /* Set start condition */ - i2c_write_reg(sc, I2C_CONTROL_REG, - I2CCR_MEN | I2CCR_MSTA | I2CCR_TXAK); - DELAY(100); - i2c_write_reg(sc, I2C_CONTROL_REG, - I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX | I2CCR_TXAK); - /* Clear status */ - i2c_write_reg(sc, I2C_STATUS_REG, 0x0); - /* Write target address - LSB is R/W bit */ + i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX); + if ((error = wait_for_busbusy(sc, true)) != IIC_NOERR) + return (i2c_error_handler(sc, error)); + i2c_write_reg(sc, I2C_STATUS_REG, 0); i2c_write_reg(sc, I2C_DATA_REG, slave); - - error = wait_for_iif(sc); - - mtx_unlock(&sc->mutex); - if (error) - return (error); - - return (IIC_NOERR); + error = wait_for_xfer(sc, true); + return (i2c_error_handler(sc, error)); } - static int i2c_stop(device_t dev) { struct i2c_softc *sc; sc = device_get_softc(dev); - mtx_lock(&sc->mutex); - i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_TXAK); - DELAY(100); - /* Reset controller if bus still busy after STOP */ - if (wait_for_nibb(sc) == IIC_ETIMEOUT) { - i2c_write_reg(sc, I2C_CONTROL_REG, 0); - DELAY(1000); - i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_TXAK); - i2c_write_reg(sc, I2C_STATUS_REG, 0x0); - } - mtx_unlock(&sc->mutex); - + i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); + wait_for_busbusy(sc, false); + i2c_write_reg(sc, I2C_CONTROL_REG, 0); return (IIC_NOERR); } static int i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr) { struct i2c_softc *sc; u_int busfreq, div, i, ipgfreq; sc = device_get_softc(dev); /* * Look up the divisor that gives the nearest speed that doesn't exceed * the configured value for the bus. */ ipgfreq = imx_ccm_ipg_hz(); busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed); div = (ipgfreq + busfreq - 1) / busfreq; for (i = 0; i < nitems(clkdiv_table); i++) { if (clkdiv_table[i].divisor >= div) break; } - div = clkdiv_table[i].regcode; - mtx_lock(&sc->mutex); - i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); - i2c_write_reg(sc, I2C_STATUS_REG, 0x0); - DELAY(1000); + /* + * Calculate roughly how long it will take to transfer a byte (which + * requires 9 clock cycles) at the new bus speed. This value is used to + * pause() while waiting for transfer-complete. With a 66MHz IPG clock + * and the actual i2c bus speeds that leads to, for nominal 100KHz and + * 400KHz bus speeds the transfer times are roughly 104uS and 22uS. + */ + busfreq = ipgfreq / clkdiv_table[i].divisor; + sc->byte_time_sbt = SBT_1US * (9000000 / busfreq); - i2c_write_reg(sc, I2C_FDR_REG, (uint8_t)div); - i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); - DELAY(1000); + /* + * Disable the controller (do the reset), and set the new clock divisor. + */ i2c_write_reg(sc, I2C_STATUS_REG, 0x0); - mtx_unlock(&sc->mutex); - + i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); + i2c_write_reg(sc, I2C_FDR_REG, (uint8_t)clkdiv_table[i].regcode); return (IIC_NOERR); } static int i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay) { struct i2c_softc *sc; int error, reg; sc = device_get_softc(dev); *read = 0; - mtx_lock(&sc->mutex); - if (len) { if (len == 1) i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_TXAK); - else i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA); - - /* dummy read */ + /* Dummy read to prime the receiver. */ + i2c_write_reg(sc, I2C_STATUS_REG, 0x0); i2c_read_reg(sc, I2C_DATA_REG); - DELAY(1000); } + error = 0; + *read = 0; while (*read < len) { - error = wait_for_icf(sc); - if (error) { - mtx_unlock(&sc->mutex); - return (error); - } + if ((error = wait_for_xfer(sc, false)) != IIC_NOERR) + break; i2c_write_reg(sc, I2C_STATUS_REG, 0x0); - if ((*read == len - 2) && last) { - /* NO ACK on last byte */ - i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | - I2CCR_MSTA | I2CCR_TXAK); + if (last) { + if (*read == len - 2) { + /* NO ACK on last byte */ + i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | + I2CCR_MSTA | I2CCR_TXAK); + } else if (*read == len - 1) { + /* Transfer done, signal stop. */ + i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | + I2CCR_TXAK); + wait_for_busbusy(sc, false); + } } - - if ((*read == len - 1) && last) { - /* Transfer done, remove master bit */ - i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | - I2CCR_TXAK); - } - reg = i2c_read_reg(sc, I2C_DATA_REG); *buf++ = reg; (*read)++; } - mtx_unlock(&sc->mutex); - return (IIC_NOERR); + return (i2c_error_handler(sc, error)); } static int i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout) { struct i2c_softc *sc; int error; sc = device_get_softc(dev); - *sent = 0; - mtx_lock(&sc->mutex); + error = 0; + *sent = 0; while (*sent < len) { i2c_write_reg(sc, I2C_STATUS_REG, 0x0); i2c_write_reg(sc, I2C_DATA_REG, *buf++); - - error = wait_for_iif(sc); - if (error) { - mtx_unlock(&sc->mutex); - return (error); - } - + if ((error = wait_for_xfer(sc, true)) != IIC_NOERR) + break; (*sent)++; } - mtx_unlock(&sc->mutex); - return (IIC_NOERR); + return (i2c_error_handler(sc, error)); } Index: stable/10/sys/arm/freescale/vybrid/vf_i2c.c =================================================================== --- stable/10/sys/arm/freescale/vybrid/vf_i2c.c (revision 289665) +++ stable/10/sys/arm/freescale/vybrid/vf_i2c.c (revision 289666) @@ -1,471 +1,471 @@ /*- * Copyright (c) 2014 Ruslan Bukin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Vybrid Family Inter-Integrated Circuit (I2C) * Chapter 48, Vybrid Reference Manual, Rev. 5, 07/2013 */ /* * This driver is based on the I2C driver for i.MX */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include "iicbus_if.h" #include #include #include #include #include #include #include #include #include #define I2C_IBAD 0x0 /* I2C Bus Address Register */ #define I2C_IBFD 0x1 /* I2C Bus Frequency Divider Register */ #define I2C_IBCR 0x2 /* I2C Bus Control Register */ #define IBCR_MDIS (1 << 7) /* Module disable. */ #define IBCR_IBIE (1 << 6) /* I-Bus Interrupt Enable. */ #define IBCR_MSSL (1 << 5) /* Master/Slave mode select. */ #define IBCR_TXRX (1 << 4) /* Transmit/Receive mode select. */ #define IBCR_NOACK (1 << 3) /* Data Acknowledge disable. */ #define IBCR_RSTA (1 << 2) /* Repeat Start. */ #define IBCR_DMAEN (1 << 1) /* DMA Enable. */ #define I2C_IBSR 0x3 /* I2C Bus Status Register */ #define IBSR_TCF (1 << 7) /* Transfer complete. */ #define IBSR_IAAS (1 << 6) /* Addressed as a slave. */ #define IBSR_IBB (1 << 5) /* Bus busy. */ #define IBSR_IBAL (1 << 4) /* Arbitration Lost. */ #define IBSR_SRW (1 << 2) /* Slave Read/Write. */ #define IBSR_IBIF (1 << 1) /* I-Bus Interrupt Flag. */ #define IBSR_RXAK (1 << 0) /* Received Acknowledge. */ #define I2C_IBDR 0x4 /* I2C Bus Data I/O Register */ #define I2C_IBIC 0x5 /* I2C Bus Interrupt Config Register */ #define IBIC_BIIE (1 << 7) /* Bus Idle Interrupt Enable bit. */ #define I2C_IBDBG 0x6 /* I2C Bus Debug Register */ #ifdef DEBUG #define vf_i2c_dbg(_sc, fmt, args...) \ device_printf((_sc)->dev, fmt, ##args) #else #define vf_i2c_dbg(_sc, fmt, args...) #endif static int i2c_repeated_start(device_t, u_char, int); static int i2c_start(device_t, u_char, int); static int i2c_stop(device_t); static int i2c_reset(device_t, u_char, u_char, u_char *); static int i2c_read(device_t, char *, int, int *, int, int); static int i2c_write(device_t, const char *, int, int *, int); struct i2c_softc { struct resource *res[2]; bus_space_tag_t bst; bus_space_handle_t bsh; device_t dev; device_t iicbus; struct mtx mutex; }; static struct resource_spec i2c_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE }, { -1, 0 } }; static int i2c_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "fsl,mvf600-i2c")) return (ENXIO); device_set_desc(dev, "Vybrid Family Inter-Integrated Circuit (I2C)"); return (BUS_PROBE_DEFAULT); } static int i2c_attach(device_t dev) { struct i2c_softc *sc; sc = device_get_softc(dev); sc->dev = dev; mtx_init(&sc->mutex, device_get_nameunit(dev), "I2C", MTX_DEF); if (bus_alloc_resources(dev, i2c_spec, sc->res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } /* Memory interface */ sc->bst = rman_get_bustag(sc->res[0]); sc->bsh = rman_get_bushandle(sc->res[0]); WRITE1(sc, I2C_IBIC, IBIC_BIIE); sc->iicbus = device_add_child(dev, "iicbus", -1); if (sc->iicbus == NULL) { device_printf(dev, "could not add iicbus child"); mtx_destroy(&sc->mutex); return (ENXIO); } bus_generic_attach(dev); return (0); } /* Wait for transfer interrupt flag */ static int wait_for_iif(struct i2c_softc *sc) { int retry; retry = 1000; while (retry --) { if (READ1(sc, I2C_IBSR) & IBSR_IBIF) { WRITE1(sc, I2C_IBSR, IBSR_IBIF); return (IIC_NOERR); } DELAY(10); } return (IIC_ETIMEOUT); } /* Wait for free bus */ static int wait_for_nibb(struct i2c_softc *sc) { int retry; retry = 1000; while (retry --) { if ((READ1(sc, I2C_IBSR) & IBSR_IBB) == 0) return (IIC_NOERR); DELAY(10); } return (IIC_ETIMEOUT); } /* Wait for transfer complete+interrupt flag */ static int wait_for_icf(struct i2c_softc *sc) { int retry; retry = 1000; while (retry --) { if (READ1(sc, I2C_IBSR) & IBSR_TCF) { if (READ1(sc, I2C_IBSR) & IBSR_IBIF) { WRITE1(sc, I2C_IBSR, IBSR_IBIF); return (IIC_NOERR); } } DELAY(10); } return (IIC_ETIMEOUT); } static int i2c_repeated_start(device_t dev, u_char slave, int timeout) { struct i2c_softc *sc; int error; int reg; sc = device_get_softc(dev); vf_i2c_dbg(sc, "i2c repeated start\n"); mtx_lock(&sc->mutex); WRITE1(sc, I2C_IBAD, slave); if ((READ1(sc, I2C_IBSR) & IBSR_IBB) == 0) { mtx_unlock(&sc->mutex); - return (IIC_EBUSBSY); + return (IIC_EBUSERR); } /* Set repeated start condition */ DELAY(10); reg = READ1(sc, I2C_IBCR); reg |= (IBCR_RSTA | IBCR_IBIE); WRITE1(sc, I2C_IBCR, reg); DELAY(10); /* Write target address - LSB is R/W bit */ WRITE1(sc, I2C_IBDR, slave); error = wait_for_iif(sc); mtx_unlock(&sc->mutex); if (error) return (error); return (IIC_NOERR); } static int i2c_start(device_t dev, u_char slave, int timeout) { struct i2c_softc *sc; int error; int reg; sc = device_get_softc(dev); vf_i2c_dbg(sc, "i2c start\n"); mtx_lock(&sc->mutex); WRITE1(sc, I2C_IBAD, slave); if (READ1(sc, I2C_IBSR) & IBSR_IBB) { mtx_unlock(&sc->mutex); vf_i2c_dbg(sc, "cant i2c start: IIC_EBUSBSY\n"); - return (IIC_EBUSBSY); + return (IIC_EBUSERR); } /* Set start condition */ reg = (IBCR_MSSL | IBCR_NOACK | IBCR_IBIE); WRITE1(sc, I2C_IBCR, reg); DELAY(100); reg |= (IBCR_TXRX); WRITE1(sc, I2C_IBCR, reg); /* Write target address - LSB is R/W bit */ WRITE1(sc, I2C_IBDR, slave); error = wait_for_iif(sc); mtx_unlock(&sc->mutex); if (error) { vf_i2c_dbg(sc, "cant i2c start: iif error\n"); return (error); } return (IIC_NOERR); } static int i2c_stop(device_t dev) { struct i2c_softc *sc; sc = device_get_softc(dev); vf_i2c_dbg(sc, "i2c stop\n"); mtx_lock(&sc->mutex); WRITE1(sc, I2C_IBCR, IBCR_NOACK | IBCR_IBIE); DELAY(100); /* Reset controller if bus still busy after STOP */ if (wait_for_nibb(sc) == IIC_ETIMEOUT) { WRITE1(sc, I2C_IBCR, IBCR_MDIS); DELAY(1000); WRITE1(sc, I2C_IBCR, IBCR_NOACK); } mtx_unlock(&sc->mutex); return (IIC_NOERR); } static int i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr) { struct i2c_softc *sc; sc = device_get_softc(dev); vf_i2c_dbg(sc, "i2c reset\n"); switch (speed) { case IIC_FAST: case IIC_SLOW: case IIC_UNKNOWN: case IIC_FASTEST: default: break; } mtx_lock(&sc->mutex); WRITE1(sc, I2C_IBCR, IBCR_MDIS); DELAY(1000); WRITE1(sc, I2C_IBFD, 20); WRITE1(sc, I2C_IBCR, 0x0); /* Enable i2c */ DELAY(1000); mtx_unlock(&sc->mutex); return (IIC_NOERR); } static int i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay) { struct i2c_softc *sc; int error; sc = device_get_softc(dev); vf_i2c_dbg(sc, "i2c read\n"); *read = 0; mtx_lock(&sc->mutex); if (len) { if (len == 1) WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL | \ IBCR_NOACK); else WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL); /* dummy read */ READ1(sc, I2C_IBDR); DELAY(1000); } while (*read < len) { error = wait_for_icf(sc); if (error) { mtx_unlock(&sc->mutex); return (error); } if ((*read == len - 2) && last) { /* NO ACK on last byte */ WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL | \ IBCR_NOACK); } if ((*read == len - 1) && last) { /* Transfer done, remove master bit */ WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_NOACK); } *buf++ = READ1(sc, I2C_IBDR); (*read)++; } mtx_unlock(&sc->mutex); return (IIC_NOERR); } static int i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout) { struct i2c_softc *sc; int error; sc = device_get_softc(dev); vf_i2c_dbg(sc, "i2c write\n"); *sent = 0; mtx_lock(&sc->mutex); while (*sent < len) { WRITE1(sc, I2C_IBDR, *buf++); error = wait_for_iif(sc); if (error) { mtx_unlock(&sc->mutex); return (error); } (*sent)++; } mtx_unlock(&sc->mutex); return (IIC_NOERR); } static device_method_t i2c_methods[] = { DEVMETHOD(device_probe, i2c_probe), DEVMETHOD(device_attach, i2c_attach), DEVMETHOD(iicbus_callback, iicbus_null_callback), DEVMETHOD(iicbus_repeated_start, i2c_repeated_start), DEVMETHOD(iicbus_start, i2c_start), DEVMETHOD(iicbus_stop, i2c_stop), DEVMETHOD(iicbus_reset, i2c_reset), DEVMETHOD(iicbus_read, i2c_read), DEVMETHOD(iicbus_write, i2c_write), DEVMETHOD(iicbus_transfer, iicbus_transfer_gen), { 0, 0 } }; static driver_t i2c_driver = { "i2c", i2c_methods, sizeof(struct i2c_softc), }; static devclass_t i2c_devclass; DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0); DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0); Index: stable/10/sys/arm/samsung/exynos/exynos5_i2c.c =================================================================== --- stable/10/sys/arm/samsung/exynos/exynos5_i2c.c (revision 289665) +++ stable/10/sys/arm/samsung/exynos/exynos5_i2c.c (revision 289666) @@ -1,476 +1,476 @@ /*- * Copyright (c) 2014 Ruslan Bukin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Samsung Exynos 5 Inter-Integrated Circuit (I2C) * Chapter 13, Exynos 5 Dual User's Manual Public Rev 1.00 */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include "iicbus_if.h" #include #include #include #include #include #include #include #include #include #define I2CCON 0x00 /* Control register */ #define ACKGEN (1 << 7) /* Acknowledge Enable */ /* * Source Clock of I2C-bus Transmit Clock Prescaler * * 0 = I2CCLK = fPCLK/16 * 1 = I2CCLK = fPCLK/512 */ #define I2CCLK (1 << 6) #define IRQ_EN (1 << 5) /* Tx/Rx Interrupt Enable/Disable */ #define IPEND (1 << 4) /* Tx/Rx Interrupt Pending Flag */ #define CLKVAL_M 0xf /* Transmit Clock Prescaler Mask */ #define CLKVAL_S 0 #define I2CSTAT 0x04 /* Control/status register */ #define I2CMODE_M 0x3 /* Master/Slave Tx/Rx Mode Select */ #define I2CMODE_S 6 #define I2CMODE_SR 0x0 /* Slave Receive Mode */ #define I2CMODE_ST 0x1 /* Slave Transmit Mode */ #define I2CMODE_MR 0x2 /* Master Receive Mode */ #define I2CMODE_MT 0x3 /* Master Transmit Mode */ #define I2CSTAT_BSY (1 << 5) /* Busy Signal Status bit */ #define I2C_START_STOP (1 << 5) /* Busy Signal Status bit */ #define RXTX_EN (1 << 4) /* Data Output Enable/Disable */ #define ARBST (1 << 3) /* Arbitration status flag */ #define ADDAS (1 << 2) /* Address-as-slave Status Flag */ #define ADDZERO (1 << 1) /* Address Zero Status Flag */ #define ACKRECVD (1 << 0) /* Last-received Bit Status Flag */ #define I2CADD 0x08 /* Address register */ #define I2CDS 0x0C /* Transmit/receive data shift */ #define I2CLC 0x10 /* Multi-master line control */ #define FILTER_EN (1 << 2) /* Filter Enable bit */ #define SDAOUT_DELAY_M 0x3 /* SDA Line Delay Length */ #define SDAOUT_DELAY_S 0 #ifdef DEBUG #define DPRINTF(fmt, args...) \ printf(fmt, ##args) #else #define DPRINTF(fmt, args...) #endif static int i2c_start(device_t, u_char, int); static int i2c_stop(device_t); static int i2c_reset(device_t, u_char, u_char, u_char *); static int i2c_read(device_t, char *, int, int *, int, int); static int i2c_write(device_t, const char *, int, int *, int); struct i2c_softc { struct resource *res[2]; bus_space_tag_t bst; bus_space_handle_t bsh; device_t dev; device_t iicbus; struct mtx mutex; void *ih; int intr; }; static struct resource_spec i2c_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE }, { -1, 0 } }; static int i2c_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "exynos,i2c")) return (ENXIO); device_set_desc(dev, "Samsung Exynos 5 I2C controller"); return (BUS_PROBE_DEFAULT); } static int clear_ipend(struct i2c_softc *sc) { int reg; reg = READ1(sc, I2CCON); reg &= ~(IPEND); WRITE1(sc, I2CCON, reg); return (0); } static int i2c_attach(device_t dev) { struct i2c_softc *sc; int reg; sc = device_get_softc(dev); sc->dev = dev; mtx_init(&sc->mutex, device_get_nameunit(dev), "I2C", MTX_DEF); if (bus_alloc_resources(dev, i2c_spec, sc->res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } /* Memory interface */ sc->bst = rman_get_bustag(sc->res[0]); sc->bsh = rman_get_bushandle(sc->res[0]); sc->iicbus = device_add_child(dev, "iicbus", -1); if (sc->iicbus == NULL) { device_printf(dev, "could not add iicbus child"); mtx_destroy(&sc->mutex); return (ENXIO); } WRITE1(sc, I2CSTAT, 0); WRITE1(sc, I2CADD, 0x00); /* Mode */ reg = (RXTX_EN); reg |= (I2CMODE_MT << I2CMODE_S); WRITE1(sc, I2CSTAT, reg); bus_generic_attach(dev); return (0); } static int wait_for_iif(struct i2c_softc *sc) { int retry; int reg; retry = 1000; while (retry --) { reg = READ1(sc, I2CCON); if (reg & IPEND) { return (IIC_NOERR); } DELAY(50); } return (IIC_ETIMEOUT); } static int wait_for_nibb(struct i2c_softc *sc) { int retry; retry = 1000; while (retry --) { if ((READ1(sc, I2CSTAT) & I2CSTAT_BSY) == 0) return (IIC_NOERR); DELAY(10); } return (IIC_ETIMEOUT); } static int is_ack(struct i2c_softc *sc) { int stat; stat = READ1(sc, I2CSTAT); if (!(stat & 1)) { /* ACK received */ return (1); } return (0); } static int i2c_start(device_t dev, u_char slave, int timeout) { struct i2c_softc *sc; int error; int reg; sc = device_get_softc(dev); DPRINTF("i2c start\n"); mtx_lock(&sc->mutex); #if 0 DPRINTF("I2CCON == 0x%08x\n", READ1(sc, I2CCON)); DPRINTF("I2CSTAT == 0x%08x\n", READ1(sc, I2CSTAT)); #endif if (slave & 1) { slave &= ~(1); slave <<= 1; slave |= 1; } else { slave <<= 1; } error = wait_for_nibb(sc); if (error) { mtx_unlock(&sc->mutex); - DPRINTF("cant i2c start: IIC_EBUSBSY\n"); - return (IIC_EBUSBSY); + DPRINTF("cant i2c start: IIC_EBUSERR\n"); + return (IIC_EBUSERR); } reg = READ1(sc, I2CCON); reg |= (IRQ_EN | ACKGEN); WRITE1(sc, I2CCON, reg); WRITE1(sc, I2CDS, slave); DELAY(50); reg = (RXTX_EN); reg |= I2C_START_STOP; reg |= (I2CMODE_MT << I2CMODE_S); WRITE1(sc, I2CSTAT, reg); error = wait_for_iif(sc); if (error) { DPRINTF("cant i2c start: iif error\n"); mtx_unlock(&sc->mutex); return (error); } if (!is_ack(sc)) { DPRINTF("cant i2c start: no ack\n"); mtx_unlock(&sc->mutex); return (IIC_ENOACK); }; mtx_unlock(&sc->mutex); return (IIC_NOERR); } static int i2c_stop(device_t dev) { struct i2c_softc *sc; int reg; int error; sc = device_get_softc(dev); DPRINTF("i2c stop\n"); mtx_lock(&sc->mutex); reg = READ1(sc, I2CSTAT); int mode = (reg >> I2CMODE_S) & I2CMODE_M; reg = (RXTX_EN); reg |= (mode << I2CMODE_S); WRITE1(sc, I2CSTAT, reg); clear_ipend(sc); error = wait_for_nibb(sc); if (error) { DPRINTF("cant i2c stop: nibb error\n"); return (error); } mtx_unlock(&sc->mutex); return (IIC_NOERR); } static int i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr) { struct i2c_softc *sc; sc = device_get_softc(dev); DPRINTF("i2c reset\n"); mtx_lock(&sc->mutex); /* TODO */ mtx_unlock(&sc->mutex); return (IIC_NOERR); } static int i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay) { struct i2c_softc *sc; int error; int reg; uint8_t d; sc = device_get_softc(dev); DPRINTF("i2c read\n"); reg = (RXTX_EN); reg |= (I2CMODE_MR << I2CMODE_S); reg |= I2C_START_STOP; WRITE1(sc, I2CSTAT, reg); *read = 0; mtx_lock(&sc->mutex); /* dummy read */ READ1(sc, I2CDS); DPRINTF("Read "); while (*read < len) { /* Do not ack last read */ if (*read == (len - 1)) { reg = READ1(sc, I2CCON); reg &= ~(ACKGEN); WRITE1(sc, I2CCON, reg); }; clear_ipend(sc); error = wait_for_iif(sc); if (error) { DPRINTF("cant i2c read: iif error\n"); mtx_unlock(&sc->mutex); return (error); } d = READ1(sc, I2CDS); DPRINTF("0x%02x ", d); *buf++ = d; (*read)++; } DPRINTF("\n"); mtx_unlock(&sc->mutex); return (IIC_NOERR); } static int i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout) { struct i2c_softc *sc; int error; sc = device_get_softc(dev); DPRINTF("i2c write\n"); *sent = 0; mtx_lock(&sc->mutex); DPRINTF("writing "); while (*sent < len) { uint8_t d = *buf++; DPRINTF("0x%02x ", d); WRITE1(sc, I2CDS, d); DELAY(50); clear_ipend(sc); error = wait_for_iif(sc); if (error) { DPRINTF("cant i2c write: iif error\n"); mtx_unlock(&sc->mutex); return (error); } if (!is_ack(sc)) { DPRINTF("cant i2c write: no ack\n"); mtx_unlock(&sc->mutex); return (IIC_ENOACK); }; (*sent)++; } DPRINTF("\n"); mtx_unlock(&sc->mutex); return (IIC_NOERR); } static device_method_t i2c_methods[] = { DEVMETHOD(device_probe, i2c_probe), DEVMETHOD(device_attach, i2c_attach), DEVMETHOD(iicbus_callback, iicbus_null_callback), DEVMETHOD(iicbus_start, i2c_start), DEVMETHOD(iicbus_stop, i2c_stop), DEVMETHOD(iicbus_reset, i2c_reset), DEVMETHOD(iicbus_read, i2c_read), DEVMETHOD(iicbus_write, i2c_write), DEVMETHOD(iicbus_transfer, iicbus_transfer_gen), { 0, 0 } }; static driver_t i2c_driver = { "i2c", i2c_methods, sizeof(struct i2c_softc), }; static devclass_t i2c_devclass; DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0); DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0); Index: stable/10/sys/dev/iicbus/icee.c =================================================================== --- stable/10/sys/dev/iicbus/icee.c (revision 289665) +++ stable/10/sys/dev/iicbus/icee.c (revision 289666) @@ -1,277 +1,278 @@ /*- * Copyright (c) 2006 Warner Losh. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * Generic IIC eeprom support, modeled after the AT24C family of products. */ #include #include #include #include #include #include #include #include #include #include #include #include #include "iicbus_if.h" #define IIC_M_WR 0 /* write operation */ #define MAX_RD_SZ 256 /* Largest read size we support */ #define MAX_WR_SZ 256 /* Largest write size we support */ struct icee_softc { device_t sc_dev; /* Myself */ - struct sx sc_lock; /* basically a perimeter lock */ + device_t sc_busdev; /* Parent bus */ struct cdev *cdev; /* user interface */ int addr; int size; /* How big am I? */ int type; /* What type 8 or 16 bit? */ int rd_sz; /* What's the read page size */ int wr_sz; /* What's the write page size */ }; -#define ICEE_LOCK(_sc) sx_xlock(&(_sc)->sc_lock) -#define ICEE_UNLOCK(_sc) sx_xunlock(&(_sc)->sc_lock) -#define ICEE_LOCK_INIT(_sc) sx_init(&_sc->sc_lock, "icee") -#define ICEE_LOCK_DESTROY(_sc) sx_destroy(&_sc->sc_lock); -#define ICEE_ASSERT_LOCKED(_sc) sx_assert(&_sc->sc_lock, SA_XLOCKED); -#define ICEE_ASSERT_UNLOCKED(_sc) sx_assert(&_sc->sc_lock, SA_UNLOCKED); #define CDEV2SOFTC(dev) ((dev)->si_drv1) /* cdev routines */ static d_open_t icee_open; static d_close_t icee_close; static d_read_t icee_read; static d_write_t icee_write; static struct cdevsw icee_cdevsw = { .d_version = D_VERSION, .d_flags = D_TRACKCLOSE, .d_open = icee_open, .d_close = icee_close, .d_read = icee_read, .d_write = icee_write }; static int icee_probe(device_t dev) { - /* XXX really probe? -- not until we know the size... */ + device_set_desc(dev, "I2C EEPROM"); return (BUS_PROBE_NOWILDCARD); } static int icee_attach(device_t dev) { struct icee_softc *sc = device_get_softc(dev); const char *dname; int dunit, err; sc->sc_dev = dev; + sc->sc_busdev = device_get_parent(sc->sc_dev); sc->addr = iicbus_get_addr(dev); err = 0; dname = device_get_name(dev); dunit = device_get_unit(dev); resource_int_value(dname, dunit, "size", &sc->size); resource_int_value(dname, dunit, "type", &sc->type); resource_int_value(dname, dunit, "rd_sz", &sc->rd_sz); if (sc->rd_sz > MAX_RD_SZ) sc->rd_sz = MAX_RD_SZ; resource_int_value(dname, dunit, "wr_sz", &sc->wr_sz); if (bootverbose) device_printf(dev, "size: %d bytes bus_width: %d-bits\n", sc->size, sc->type); sc->cdev = make_dev(&icee_cdevsw, device_get_unit(dev), UID_ROOT, GID_WHEEL, 0600, "icee%d", device_get_unit(dev)); if (sc->cdev == NULL) { err = ENOMEM; goto out; } sc->cdev->si_drv1 = sc; - ICEE_LOCK_INIT(sc); -out:; +out: return (err); } static int icee_open(struct cdev *dev, int oflags, int devtype, struct thread *td) { - return (0); + return (0); } static int icee_close(struct cdev *dev, int fflag, int devtype, struct thread *td) { return (0); } static int icee_read(struct cdev *dev, struct uio *uio, int ioflag) { struct icee_softc *sc; uint8_t addr[2]; uint8_t data[MAX_RD_SZ]; int error, i, len, slave; struct iic_msg msgs[2] = { { 0, IIC_M_WR, 1, addr }, { 0, IIC_M_RD, 0, data }, }; sc = CDEV2SOFTC(dev); if (uio->uio_offset == sc->size) return (0); if (uio->uio_offset > sc->size) return (EIO); if (sc->type != 8 && sc->type != 16) return (EINVAL); - ICEE_LOCK(sc); + error = iicbus_request_bus(sc->sc_busdev, sc->sc_dev, IIC_INTRWAIT); + if (error!= 0) + return (iic2errno(error)); slave = error = 0; while (uio->uio_resid > 0) { if (uio->uio_offset >= sc->size) break; len = MIN(sc->rd_sz - (uio->uio_offset & (sc->rd_sz - 1)), uio->uio_resid); switch (sc->type) { case 8: slave = (uio->uio_offset >> 7) | sc->addr; msgs[0].len = 1; msgs[1].len = len; addr[0] = uio->uio_offset & 0xff; break; case 16: slave = sc->addr | (uio->uio_offset >> 15); msgs[0].len = 2; msgs[1].len = len; addr[0] = (uio->uio_offset >> 8) & 0xff; addr[1] = uio->uio_offset & 0xff; break; } for (i = 0; i < 2; i++) msgs[i].slave = slave; error = iicbus_transfer(sc->sc_dev, msgs, 2); - if (error) + if (error) { + error = iic2errno(error); break; + } error = uiomove(data, len, uio); if (error) break; } - ICEE_UNLOCK(sc); + iicbus_release_bus(sc->sc_busdev, sc->sc_dev); return (error); } /* * Write to the part. We use three transfers here since we're actually * doing a write followed by a read to make sure that the write finished. * It is easier to encode the dummy read here than to break things up * into smaller chunks... */ static int icee_write(struct cdev *dev, struct uio *uio, int ioflag) { struct icee_softc *sc; int error, len, slave, waitlimit; uint8_t data[MAX_WR_SZ + 2]; struct iic_msg wr[1] = { { 0, IIC_M_WR, 0, data }, }; struct iic_msg rd[1] = { { 0, IIC_M_RD, 1, data }, }; sc = CDEV2SOFTC(dev); if (uio->uio_offset >= sc->size) return (EIO); if (sc->type != 8 && sc->type != 16) return (EINVAL); - ICEE_LOCK(sc); + + error = iicbus_request_bus(sc->sc_busdev, sc->sc_dev, IIC_INTRWAIT); + if (error!= 0) + return (iic2errno(error)); slave = error = 0; while (uio->uio_resid > 0) { if (uio->uio_offset >= sc->size) break; len = MIN(sc->wr_sz - (uio->uio_offset & (sc->wr_sz - 1)), uio->uio_resid); switch (sc->type) { case 8: slave = (uio->uio_offset >> 7) | sc->addr; wr[0].len = 1 + len; data[0] = uio->uio_offset & 0xff; break; case 16: slave = sc->addr | (uio->uio_offset >> 15); wr[0].len = 2 + len; data[0] = (uio->uio_offset >> 8) & 0xff; data[1] = uio->uio_offset & 0xff; break; } wr[0].slave = slave; error = uiomove(data + sc->type / 8, len, uio); if (error) break; error = iicbus_transfer(sc->sc_dev, wr, 1); - if (error) + if (error) { + error = iic2errno(error); break; - // Now wait for the write to be done by trying to read - // the part. + } + /* Read after write to wait for write-done. */ waitlimit = 10000; rd[0].slave = slave; - do - { - error = iicbus_transfer(sc->sc_dev, rd, 1); + do { + error = iicbus_transfer(sc->sc_dev, rd, 1); } while (waitlimit-- > 0 && error != 0); if (error) { - printf("waiting for write failed %d\n", error); - break; + error = iic2errno(error); + break; } } - ICEE_UNLOCK(sc); + iicbus_release_bus(sc->sc_busdev, sc->sc_dev); return error; } static device_method_t icee_methods[] = { DEVMETHOD(device_probe, icee_probe), DEVMETHOD(device_attach, icee_attach), DEVMETHOD_END }; static driver_t icee_driver = { "icee", icee_methods, sizeof(struct icee_softc), }; static devclass_t icee_devclass; DRIVER_MODULE(icee, iicbus, icee_driver, icee_devclass, 0, 0); MODULE_VERSION(icee, 1); MODULE_DEPEND(icee, iicbus, 1, 1, 1); Index: stable/10/sys/dev/iicbus/iic.c =================================================================== --- stable/10/sys/dev/iicbus/iic.c (revision 289665) +++ stable/10/sys/dev/iicbus/iic.c (revision 289666) @@ -1,399 +1,492 @@ /*- * Copyright (c) 1998, 2001 Nicolas Souchu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #include #include #include #include #include #include #include #include #include #include #include +#include #include #include #include #include "iicbus_if.h" -#define BUFSIZE 1024 - struct iic_softc { - device_t sc_dev; - u_char sc_addr; /* 7 bit address on iicbus */ - int sc_count; /* >0 if device opened */ - - char sc_buffer[BUFSIZE]; /* output buffer */ - char sc_inbuf[BUFSIZE]; /* input buffer */ - struct cdev *sc_devnode; - struct sx sc_lock; }; -#define IIC_LOCK(sc) sx_xlock(&(sc)->sc_lock) -#define IIC_UNLOCK(sc) sx_xunlock(&(sc)->sc_lock) +struct iic_cdevpriv { + struct sx lock; + struct iic_softc *sc; + bool started; + uint8_t addr; +}; + +#define IIC_LOCK(cdp) sx_xlock(&(cdp)->lock) +#define IIC_UNLOCK(cdp) sx_xunlock(&(cdp)->lock) + +static MALLOC_DEFINE(M_IIC, "iic", "I2C device data"); + static int iic_probe(device_t); static int iic_attach(device_t); static int iic_detach(device_t); static void iic_identify(driver_t *driver, device_t parent); +static void iicdtor(void *data); +static int iicuio_move(struct iic_cdevpriv *priv, struct uio *uio, int last); +static int iicuio(struct cdev *dev, struct uio *uio, int ioflag); +static int iicrdwr(struct iic_cdevpriv *priv, struct iic_rdwr_data *d, int flags); static devclass_t iic_devclass; static device_method_t iic_methods[] = { /* device interface */ DEVMETHOD(device_identify, iic_identify), DEVMETHOD(device_probe, iic_probe), DEVMETHOD(device_attach, iic_attach), DEVMETHOD(device_detach, iic_detach), /* iicbus interface */ DEVMETHOD(iicbus_intr, iicbus_generic_intr), { 0, 0 } }; static driver_t iic_driver = { "iic", iic_methods, sizeof(struct iic_softc), }; static d_open_t iicopen; -static d_close_t iicclose; -static d_write_t iicwrite; -static d_read_t iicread; static d_ioctl_t iicioctl; static struct cdevsw iic_cdevsw = { .d_version = D_VERSION, - .d_flags = D_TRACKCLOSE, .d_open = iicopen, - .d_close = iicclose, - .d_read = iicread, - .d_write = iicwrite, + .d_read = iicuio, + .d_write = iicuio, .d_ioctl = iicioctl, .d_name = "iic", }; static void iic_identify(driver_t *driver, device_t parent) { if (device_find_child(parent, "iic", -1) == NULL) BUS_ADD_CHILD(parent, 0, "iic", -1); } static int iic_probe(device_t dev) { if (iicbus_get_addr(dev) > 0) return (ENXIO); device_set_desc(dev, "I2C generic I/O"); return (0); } static int iic_attach(device_t dev) { - struct iic_softc *sc = (struct iic_softc *)device_get_softc(dev); + struct iic_softc *sc; + sc = device_get_softc(dev); sc->sc_dev = dev; - sx_init(&sc->sc_lock, "iic"); sc->sc_devnode = make_dev(&iic_cdevsw, device_get_unit(dev), UID_ROOT, GID_WHEEL, 0600, "iic%d", device_get_unit(dev)); if (sc->sc_devnode == NULL) { device_printf(dev, "failed to create character device\n"); - sx_destroy(&sc->sc_lock); return (ENXIO); } sc->sc_devnode->si_drv1 = sc; return (0); } static int iic_detach(device_t dev) { - struct iic_softc *sc = (struct iic_softc *)device_get_softc(dev); + struct iic_softc *sc; + sc = device_get_softc(dev); + if (sc->sc_devnode) destroy_dev(sc->sc_devnode); - sx_destroy(&sc->sc_lock); return (0); } static int iicopen(struct cdev *dev, int flags, int fmt, struct thread *td) { - struct iic_softc *sc = dev->si_drv1; + struct iic_cdevpriv *priv; + int error; - IIC_LOCK(sc); - if (sc->sc_count > 0) { - IIC_UNLOCK(sc); - return (EBUSY); - } + priv = malloc(sizeof(*priv), M_IIC, M_WAITOK | M_ZERO); - sc->sc_count++; - IIC_UNLOCK(sc); + sx_init(&priv->lock, "iic"); + priv->sc = dev->si_drv1; - return (0); + error = devfs_set_cdevpriv(priv, iicdtor); + if (error != 0) + free(priv, M_IIC); + + return (error); } -static int -iicclose(struct cdev *dev, int flags, int fmt, struct thread *td) +static void +iicdtor(void *data) { - struct iic_softc *sc = dev->si_drv1; + device_t iicdev, parent; + struct iic_cdevpriv *priv; - IIC_LOCK(sc); - if (!sc->sc_count) { - /* XXX: I don't think this can happen. */ - IIC_UNLOCK(sc); - return (EINVAL); - } + priv = data; + KASSERT(priv != NULL, ("iic cdevpriv should not be NULL!")); - sc->sc_count--; + iicdev = priv->sc->sc_dev; + parent = device_get_parent(iicdev); - if (sc->sc_count < 0) - panic("%s: iic_count < 0!", __func__); - IIC_UNLOCK(sc); + if (priv->started) { + iicbus_stop(parent); + iicbus_reset(parent, IIC_UNKNOWN, 0, NULL); + iicbus_release_bus(parent, iicdev); + } - return (0); + sx_destroy(&priv->lock); + free(priv, M_IIC); } static int -iicwrite(struct cdev *dev, struct uio * uio, int ioflag) +iicuio_move(struct iic_cdevpriv *priv, struct uio *uio, int last) { - struct iic_softc *sc = dev->si_drv1; - device_t iicdev = sc->sc_dev; - int sent, error, count; + device_t parent; + int error, num_bytes, transferred_bytes, written_bytes; + char buffer[128]; - IIC_LOCK(sc); - if (!sc->sc_addr) { - IIC_UNLOCK(sc); - return (EINVAL); - } + parent = device_get_parent(priv->sc->sc_dev); + error = 0; - if (sc->sc_count == 0) { - /* XXX: I don't think this can happen. */ - IIC_UNLOCK(sc); - return (EINVAL); + /* + * We can only transfer up to sizeof(buffer) bytes in 1 shot, so loop until + * everything has been transferred. + */ + while ((error == 0) && (uio->uio_resid > 0)) { + + num_bytes = MIN(uio->uio_resid, sizeof(buffer)); + transferred_bytes = 0; + + if (uio->uio_rw == UIO_WRITE) { + error = uiomove(buffer, num_bytes, uio); + + while ((error == 0) && (transferred_bytes < num_bytes)) { + written_bytes = 0; + error = iicbus_write(parent, &buffer[transferred_bytes], + num_bytes - transferred_bytes, &written_bytes, 0); + transferred_bytes += written_bytes; + } + + } else if (uio->uio_rw == UIO_READ) { + error = iicbus_read(parent, buffer, + num_bytes, &transferred_bytes, + ((uio->uio_resid <= sizeof(buffer)) ? last : 0), 0); + if (error == 0) + error = uiomove(buffer, transferred_bytes, uio); + } } - error = iicbus_request_bus(device_get_parent(iicdev), iicdev, - IIC_DONTWAIT); - if (error) { - IIC_UNLOCK(sc); + return (error); +} + +static int +iicuio(struct cdev *dev, struct uio *uio, int ioflag) +{ + device_t parent; + struct iic_cdevpriv *priv; + int error; + uint8_t addr; + + priv = NULL; + error = devfs_get_cdevpriv((void**)&priv); + + if (error != 0) return (error); + KASSERT(priv != NULL, ("iic cdevpriv should not be NULL!")); + + IIC_LOCK(priv); + if (priv->started || (priv->addr == 0)) { + IIC_UNLOCK(priv); + return (ENXIO); } + parent = device_get_parent(priv->sc->sc_dev); - count = min(uio->uio_resid, BUFSIZE); - error = uiomove(sc->sc_buffer, count, uio); - if (error) { - IIC_UNLOCK(sc); + error = iicbus_request_bus(parent, priv->sc->sc_dev, + (ioflag & O_NONBLOCK) ? IIC_DONTWAIT : (IIC_WAIT | IIC_INTR)); + if (error != 0) { + IIC_UNLOCK(priv); return (error); } - error = iicbus_block_write(device_get_parent(iicdev), sc->sc_addr, - sc->sc_buffer, count, &sent); + if (uio->uio_rw == UIO_READ) + addr = priv->addr | LSB; + else + addr = priv->addr & ~LSB; - iicbus_release_bus(device_get_parent(iicdev), iicdev); - IIC_UNLOCK(sc); + error = iicbus_start(parent, addr, 0); + if (error != 0) + { + iicbus_release_bus(parent, priv->sc->sc_dev); + IIC_UNLOCK(priv); + return (error); + } + error = iicuio_move(priv, uio, IIC_LAST_READ); + + iicbus_stop(parent); + iicbus_release_bus(parent, priv->sc->sc_dev); + IIC_UNLOCK(priv); return (error); } static int -iicread(struct cdev *dev, struct uio * uio, int ioflag) +iicrdwr(struct iic_cdevpriv *priv, struct iic_rdwr_data *d, int flags) { - struct iic_softc *sc = dev->si_drv1; - device_t iicdev = sc->sc_dev; - int len, error = 0; - int bufsize; + struct iic_msg *buf, *m; + void **usrbufs; + device_t iicdev, parent; + int error, i; - IIC_LOCK(sc); - if (!sc->sc_addr) { - IIC_UNLOCK(sc); - return (EINVAL); - } + iicdev = priv->sc->sc_dev; + parent = device_get_parent(iicdev); + error = 0; - if (sc->sc_count == 0) { - /* XXX: I don't think this can happen. */ - IIC_UNLOCK(sc); - return (EINVAL); - } + buf = malloc(sizeof(*d->msgs) * d->nmsgs, M_IIC, M_WAITOK); - error = iicbus_request_bus(device_get_parent(iicdev), iicdev, - IIC_DONTWAIT); - if (error) { - IIC_UNLOCK(sc); - return (error); - } + error = copyin(d->msgs, buf, sizeof(*d->msgs) * d->nmsgs); - /* max amount of data to read */ - len = min(uio->uio_resid, BUFSIZE); + /* Alloc kernel buffers for userland data, copyin write data */ + usrbufs = malloc(sizeof(void *) * d->nmsgs, M_IIC, M_WAITOK | M_ZERO); - error = iicbus_block_read(device_get_parent(iicdev), sc->sc_addr, - sc->sc_inbuf, len, &bufsize); - if (error) { - IIC_UNLOCK(sc); - return (error); + for (i = 0; i < d->nmsgs; i++) { + m = &(buf[i]); + usrbufs[i] = m->buf; + + /* + * At least init the buffer to NULL so we can safely free() it later. + * If the copyin() to buf failed, don't try to malloc bogus m->len. + */ + m->buf = NULL; + if (error != 0) + continue; + m->buf = malloc(m->len, M_IIC, M_WAITOK); + if (!(m->flags & IIC_M_RD)) + error = copyin(usrbufs[i], m->buf, m->len); } - if (bufsize > uio->uio_resid) - panic("%s: too much data read!", __func__); + if (error == 0) + error = iicbus_request_bus(parent, iicdev, + (flags & O_NONBLOCK) ? IIC_DONTWAIT : (IIC_WAIT | IIC_INTR)); - iicbus_release_bus(device_get_parent(iicdev), iicdev); + if (error == 0) { + error = iicbus_transfer(iicdev, buf, d->nmsgs); + iicbus_release_bus(parent, iicdev); + } - error = uiomove(sc->sc_inbuf, bufsize, uio); - IIC_UNLOCK(sc); + /* Copyout all read segments, free up kernel buffers */ + for (i = 0; i < d->nmsgs; i++) { + m = &(buf[i]); + if ((error == 0) && (m->flags & IIC_M_RD)) + error = copyout(m->buf, usrbufs[i], m->len); + free(m->buf, M_IIC); + } + + free(usrbufs, M_IIC); + free(buf, M_IIC); return (error); } static int iicioctl(struct cdev *dev, u_long cmd, caddr_t data, int flags, struct thread *td) { - struct iic_softc *sc = dev->si_drv1; - device_t iicdev = sc->sc_dev; - device_t parent = device_get_parent(iicdev); - struct iiccmd *s = (struct iiccmd *)data; - struct iic_rdwr_data *d = (struct iic_rdwr_data *)data; - struct iic_msg *m; - int error, count, i; - char *buf = NULL; - void **usrbufs = NULL; + device_t parent, iicdev; + struct iiccmd *s; + struct uio ubuf; + struct iovec uvec; + struct iic_cdevpriv *priv; + int error; - if ((error = iicbus_request_bus(parent, iicdev, - (flags & O_NONBLOCK) ? IIC_DONTWAIT : (IIC_WAIT | IIC_INTR)))) + s = (struct iiccmd *)data; + error = devfs_get_cdevpriv((void**)&priv); + if (error != 0) return (error); + KASSERT(priv != NULL, ("iic cdevpriv should not be NULL!")); + + iicdev = priv->sc->sc_dev; + parent = device_get_parent(iicdev); + IIC_LOCK(priv); + + switch (cmd) { case I2CSTART: - IIC_LOCK(sc); - error = iicbus_start(parent, s->slave, 0); + if (priv->started) { + error = EINVAL; + break; + } + error = iicbus_request_bus(parent, iicdev, + (flags & O_NONBLOCK) ? IIC_DONTWAIT : (IIC_WAIT | IIC_INTR)); - /* - * Implicitly set the chip addr to the slave addr passed as - * parameter. Consequently, start/stop shall be called before - * the read or the write of a block. - */ - if (!error) - sc->sc_addr = s->slave; - IIC_UNLOCK(sc); + if (error == 0) + error = iicbus_start(parent, s->slave, 0); + if (error == 0) { + priv->addr = s->slave; + priv->started = true; + } else + iicbus_release_bus(parent, iicdev); + break; case I2CSTOP: - error = iicbus_stop(parent); + if (priv->started) { + error = iicbus_stop(parent); + iicbus_release_bus(parent, iicdev); + priv->started = false; + } + break; case I2CRSTCARD: - error = iicbus_reset(parent, IIC_UNKNOWN, 0, NULL); /* - * Ignore IIC_ENOADDR as it only means we have a master-only - * controller. - */ - if (error == IIC_ENOADDR) - error = 0; + * Bus should be owned before we reset it. + * We allow the bus to be already owned as the result of an in-progress + * sequence; however, bus reset will always be followed by release + * (a new start is presumably needed for I/O anyway). */ + if (!priv->started) + error = iicbus_request_bus(parent, iicdev, + (flags & O_NONBLOCK) ? IIC_DONTWAIT : (IIC_WAIT | IIC_INTR)); + + if (error == 0) { + error = iicbus_reset(parent, IIC_UNKNOWN, 0, NULL); + /* + * Ignore IIC_ENOADDR as it only means we have a master-only + * controller. + */ + if (error == IIC_ENOADDR) + error = 0; + + iicbus_release_bus(parent, iicdev); + priv->started = false; + } break; case I2CWRITE: - if (s->count <= 0) { + if (!priv->started) { error = EINVAL; break; } - buf = malloc((unsigned long)s->count, M_TEMP, M_WAITOK); - error = copyin(s->buf, buf, s->count); - if (error) - break; - error = iicbus_write(parent, buf, s->count, &count, 10); + uvec.iov_base = s->buf; + uvec.iov_len = s->count; + ubuf.uio_iov = &uvec; + ubuf.uio_iovcnt = 1; + ubuf.uio_segflg = UIO_USERSPACE; + ubuf.uio_td = td; + ubuf.uio_resid = s->count; + ubuf.uio_offset = 0; + ubuf.uio_rw = UIO_WRITE; + error = iicuio_move(priv, &ubuf, 0); break; case I2CREAD: - if (s->count <= 0) { + if (!priv->started) { error = EINVAL; break; } - buf = malloc((unsigned long)s->count, M_TEMP, M_WAITOK); - error = iicbus_read(parent, buf, s->count, &count, s->last, 10); - if (error) - break; - error = copyout(buf, s->buf, s->count); + uvec.iov_base = s->buf; + uvec.iov_len = s->count; + ubuf.uio_iov = &uvec; + ubuf.uio_iovcnt = 1; + ubuf.uio_segflg = UIO_USERSPACE; + ubuf.uio_td = td; + ubuf.uio_resid = s->count; + ubuf.uio_offset = 0; + ubuf.uio_rw = UIO_READ; + error = iicuio_move(priv, &ubuf, s->last); break; case I2CRDWR: - buf = malloc(sizeof(*d->msgs) * d->nmsgs, M_TEMP, M_WAITOK); - error = copyin(d->msgs, buf, sizeof(*d->msgs) * d->nmsgs); - if (error) + /* + * The rdwr list should be a self-contained set of + * transactions. Fail if another transaction is in progress. + */ + if (priv->started) { + error = EINVAL; break; - /* Alloc kernel buffers for userland data, copyin write data */ - usrbufs = malloc(sizeof(void *) * d->nmsgs, M_TEMP, M_ZERO | M_WAITOK); - for (i = 0; i < d->nmsgs; i++) { - m = &((struct iic_msg *)buf)[i]; - usrbufs[i] = m->buf; - m->buf = malloc(m->len, M_TEMP, M_WAITOK); - if (!(m->flags & IIC_M_RD)) - copyin(usrbufs[i], m->buf, m->len); } - error = iicbus_transfer(iicdev, (struct iic_msg *)buf, d->nmsgs); - /* Copyout all read segments, free up kernel buffers */ - for (i = 0; i < d->nmsgs; i++) { - m = &((struct iic_msg *)buf)[i]; - if (m->flags & IIC_M_RD) - copyout(m->buf, usrbufs[i], m->len); - free(m->buf, M_TEMP); - } - free(usrbufs, M_TEMP); + + error = iicrdwr(priv, (struct iic_rdwr_data *)data, flags); + break; case I2CRPTSTART: + if (!priv->started) { + error = EINVAL; + break; + } error = iicbus_repeated_start(parent, s->slave, 0); break; + case I2CSADDR: + priv->addr = *((uint8_t*)data); + break; + default: error = ENOTTY; } - iicbus_release_bus(parent, iicdev); - - if (buf != NULL) - free(buf, M_TEMP); + IIC_UNLOCK(priv); return (error); } DRIVER_MODULE(iic, iicbus, iic_driver, iic_devclass, 0, 0); MODULE_DEPEND(iic, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); MODULE_VERSION(iic, 1); Index: stable/10/sys/dev/iicbus/iic.h =================================================================== --- stable/10/sys/dev/iicbus/iic.h (revision 289665) +++ stable/10/sys/dev/iicbus/iic.h (revision 289666) @@ -1,67 +1,68 @@ /*- * Copyright (c) 1998 Nicolas Souchu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #ifndef __IIC_H #define __IIC_H #include /* Designed to be compatible with linux's struct i2c_msg */ struct iic_msg { uint16_t slave; uint16_t flags; #define IIC_M_WR 0 /* Fake flag for write */ #define IIC_M_RD 0x0001 /* read vs write */ #define IIC_M_NOSTOP 0x0002 /* do not send a I2C stop after message */ #define IIC_M_NOSTART 0x0004 /* do not send a I2C start before message */ uint16_t len; /* msg length */ uint8_t * buf; }; struct iiccmd { u_char slave; int count; int last; char *buf; }; struct iic_rdwr_data { struct iic_msg *msgs; uint32_t nmsgs; }; #define I2CSTART _IOW('i', 1, struct iiccmd) /* start condition */ #define I2CSTOP _IO('i', 2) /* stop condition */ #define I2CRSTCARD _IOW('i', 3, struct iiccmd) /* reset the card */ #define I2CWRITE _IOW('i', 4, struct iiccmd) /* send data */ #define I2CREAD _IOW('i', 5, struct iiccmd) /* receive data */ #define I2CRDWR _IOW('i', 6, struct iic_rdwr_data) /* General read/write interface */ #define I2CRPTSTART _IOW('i', 7, struct iiccmd) /* repeated start */ +#define I2CSADDR _IOW('i', 8, uint8_t) /* set slave address for future I/O */ #endif Index: stable/10/sys/dev/iicbus/iicbus_if.m =================================================================== --- stable/10/sys/dev/iicbus/iicbus_if.m (revision 289665) +++ stable/10/sys/dev/iicbus/iicbus_if.m (revision 289666) @@ -1,137 +1,141 @@ #- # Copyright (c) 1998 Nicolas Souchu # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions # are met: # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # # THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS # OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) # HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT # LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY # OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF # SUCH DAMAGE. # # $FreeBSD$ # #include #include INTERFACE iicbus; CODE { static u_int iicbus_default_frequency(device_t bus, u_char speed) { return (100000); } }; # # Interpret interrupt # METHOD int intr { device_t dev; int event; char *buf; }; # # iicbus callback +# Request ownership of bus +# index: IIC_REQUEST_BUS or IIC_RELEASE_BUS +# data: pointer to int containing IIC_WAIT or IIC_DONTWAIT and either IIC_INTR or IIC_NOINTR +# This function is allowed to sleep if *data contains IIC_WAIT. # METHOD int callback { device_t dev; int index; caddr_t data; }; # # Send REPEATED_START condition # METHOD int repeated_start { device_t dev; u_char slave; int timeout; }; # # Send START condition # METHOD int start { device_t dev; u_char slave; int timeout; }; # # Send STOP condition # METHOD int stop { device_t dev; }; # # Read from I2C bus # METHOD int read { device_t dev; char *buf; int len; int *bytes; int last; int delay; }; # # Write to the I2C bus # METHOD int write { device_t dev; const char *buf; int len; int *bytes; int timeout; }; # # Reset I2C bus # METHOD int reset { device_t dev; u_char speed; u_char addr; u_char *oldaddr; }; # # Generalized Read/Write interface # METHOD int transfer { device_t dev; struct iic_msg *msgs; uint32_t nmsgs; }; # # Return the frequency in Hz for the bus running at the given # symbolic speed. Only the IIC_SLOW speed has meaning, it is always # 100KHz. The UNKNOWN, FAST, and FASTEST rates all map to the # configured bus frequency, or 100KHz when not otherwise configured. # METHOD u_int get_frequency { device_t dev; u_char speed; } DEFAULT iicbus_default_frequency; Index: stable/10/sys/dev/iicbus/iicoc.c =================================================================== --- stable/10/sys/dev/iicbus/iicoc.c (revision 289665) +++ stable/10/sys/dev/iicbus/iicoc.c (revision 289666) @@ -1,390 +1,390 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "iicbus_if.h" static devclass_t iicoc_devclass; /* * Device methods */ static int iicoc_probe(device_t); static int iicoc_attach(device_t); static int iicoc_detach(device_t); static int iicoc_start(device_t dev, u_char slave, int timeout); static int iicoc_stop(device_t dev); static int iicoc_read(device_t dev, char *buf, int len, int *read, int last, int delay); static int iicoc_write(device_t dev, const char *buf, int len, int *sent, int timeout); static int iicoc_repeated_start(device_t dev, u_char slave, int timeout); struct iicoc_softc { device_t dev; /* Self */ u_int reg_shift; /* Chip specific */ u_int clockfreq; u_int i2cfreq; struct resource *mem_res; /* Memory resource */ int mem_rid; int sc_started; uint8_t i2cdev_addr; device_t iicbus; struct mtx sc_mtx; }; static void iicoc_dev_write(device_t dev, int reg, int value) { struct iicoc_softc *sc; sc = device_get_softc(dev); bus_write_1(sc->mem_res, reg<reg_shift, value); } static int iicoc_dev_read(device_t dev, int reg) { uint8_t val; struct iicoc_softc *sc; sc = device_get_softc(dev); val = bus_read_1(sc->mem_res, reg<reg_shift); return (val); } static int iicoc_wait_on_status(device_t dev, uint8_t bit) { int tries = I2C_TIMEOUT; uint8_t status; do { status = iicoc_dev_read(dev, OC_I2C_STATUS_REG); } while ((status & bit) != 0 && --tries > 0); return (tries == 0 ? -1: 0); } static int iicoc_rd_cmd(device_t dev, uint8_t cmd) { uint8_t data; iicoc_dev_write(dev, OC_I2C_CMD_REG, cmd); if (iicoc_wait_on_status(dev, OC_STATUS_TIP) < 0) { device_printf(dev, "read: Timeout waiting for TIP clear.\n"); return (-1); } data = iicoc_dev_read(dev, OC_I2C_DATA_REG); return (data); } static int iicoc_wr_cmd(device_t dev, uint8_t data, uint8_t cmd) { iicoc_dev_write(dev, OC_I2C_DATA_REG, data); iicoc_dev_write(dev, OC_I2C_CMD_REG, cmd); if (iicoc_wait_on_status(dev, OC_STATUS_TIP) < 0) { device_printf(dev, "write: Timeout waiting for TIP clear.\n"); return (-1); } return (0); } static int iicoc_wr_ack_cmd(device_t dev, uint8_t data, uint8_t cmd) { if (iicoc_wr_cmd(dev, data, cmd) < 0) return (-1); if (iicoc_dev_read(dev, OC_I2C_STATUS_REG) & OC_STATUS_NACK) { device_printf(dev, "write: I2C command ACK Error.\n"); return (IIC_ENOACK); } return (0); } static int iicoc_init(device_t dev) { struct iicoc_softc *sc; int value; sc = device_get_softc(dev); value = iicoc_dev_read(dev, OC_I2C_CTRL_REG); iicoc_dev_write(dev, OC_I2C_CTRL_REG, value & ~(OC_CONTROL_EN | OC_CONTROL_IEN)); value = (sc->clockfreq/(5 * sc->i2cfreq)) - 1; iicoc_dev_write(dev, OC_I2C_PRESCALE_LO_REG, value & 0xff); iicoc_dev_write(dev, OC_I2C_PRESCALE_HI_REG, value >> 8); value = iicoc_dev_read(dev, OC_I2C_CTRL_REG); iicoc_dev_write(dev, OC_I2C_CTRL_REG, value | OC_CONTROL_EN); value = iicoc_dev_read(dev, OC_I2C_CTRL_REG); /* return 0 on success, 1 on error */ return ((value & OC_CONTROL_EN) == 0); } static int iicoc_probe(device_t dev) { struct iicoc_softc *sc; sc = device_get_softc(dev); if ((pci_get_vendor(dev) == 0x184e) && (pci_get_device(dev) == 0x1011)) { sc->clockfreq = XLP_I2C_CLKFREQ; sc->i2cfreq = XLP_I2C_FREQ; sc->reg_shift = 2; device_set_desc(dev, "Netlogic XLP I2C Controller"); return (BUS_PROBE_DEFAULT); } return (ENXIO); } /* * We add all the devices which we know about. * The generic attach routine will attach them if they are alive. */ static int iicoc_attach(device_t dev) { int bus; struct iicoc_softc *sc; sc = device_get_softc(dev); bus = device_get_unit(dev); sc->dev = dev; mtx_init(&sc->sc_mtx, "iicoc", "iicoc", MTX_DEF); sc->mem_rid = 0; sc->mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->mem_rid, 0ul, ~0ul, 0x100, RF_ACTIVE); if (sc->mem_res == NULL) { device_printf(dev, "Could not allocate bus resource.\n"); return (-1); } iicoc_init(dev); sc->iicbus = device_add_child(dev, "iicbus", -1); if (sc->iicbus == NULL) { device_printf(dev, "Could not allocate iicbus instance.\n"); return (-1); } bus_generic_attach(dev); return (0); } static int iicoc_detach(device_t dev) { bus_generic_detach(dev); return (0); } static int iicoc_start(device_t dev, u_char slave, int timeout) { - int error = IIC_EBUSBSY; + int error = IIC_EBUSERR; struct iicoc_softc *sc; sc = device_get_softc(dev); mtx_lock(&sc->sc_mtx); sc->i2cdev_addr = (slave >> 1); /* Verify the bus is idle */ if (iicoc_wait_on_status(dev, OC_STATUS_BUSY) < 0) goto i2c_stx_error; /* Write Slave Address */ if (iicoc_wr_ack_cmd(dev, slave, OC_COMMAND_START)) { device_printf(dev, "I2C write slave address [0x%x] failed.\n", slave); error = IIC_ENOACK; goto i2c_stx_error; } /* Verify Arbitration is not Lost */ if (iicoc_dev_read(dev, OC_I2C_STATUS_REG) & OC_STATUS_AL) { device_printf(dev, "I2C Bus Arbitration Lost, Aborting.\n"); error = IIC_EBUSERR; goto i2c_stx_error; } error = IIC_NOERR; mtx_unlock(&sc->sc_mtx); return (error); i2c_stx_error: iicoc_dev_write(dev, OC_I2C_CMD_REG, OC_COMMAND_STOP); iicoc_wait_on_status(dev, OC_STATUS_BUSY); /* wait for idle */ mtx_unlock(&sc->sc_mtx); return (error); } static int iicoc_stop(device_t dev) { int error = 0; struct iicoc_softc *sc; sc = device_get_softc(dev); mtx_lock(&sc->sc_mtx); iicoc_dev_write(dev, OC_I2C_CMD_REG, OC_COMMAND_STOP); iicoc_wait_on_status(dev, OC_STATUS_BUSY); /* wait for idle */ mtx_unlock(&sc->sc_mtx); return (error); } static int iicoc_write(device_t dev, const char *buf, int len, int *sent, int timeout /* us */ ) { uint8_t value; int i; value = buf[0]; /* Write Slave Offset */ if (iicoc_wr_ack_cmd(dev, value, OC_COMMAND_WRITE)) { device_printf(dev, "I2C write slave offset failed.\n"); goto i2c_tx_error; } for (i = 1; i < len; i++) { /* Write data byte */ value = buf[i]; if (iicoc_wr_cmd(dev, value, OC_COMMAND_WRITE)) { device_printf(dev, "I2C write data byte %d failed.\n", i); goto i2c_tx_error; } } *sent = len; return (IIC_NOERR); i2c_tx_error: return (IIC_EBUSERR); } static int iicoc_read(device_t dev, char *buf, int len, int *read, int last, int delay) { int data, i; uint8_t cmd; for (i = 0; i < len; i++) { /* Read data byte */ cmd = (i == len - 1) ? OC_COMMAND_RDNACK : OC_COMMAND_READ; data = iicoc_rd_cmd(dev, cmd); if (data < 0) { device_printf(dev, "I2C read data byte %d failed.\n", i); goto i2c_rx_error; } buf[i] = (uint8_t)data; } *read = len; return (IIC_NOERR); i2c_rx_error: return (IIC_EBUSERR); } static int iicoc_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr) { int error; struct iicoc_softc *sc; sc = device_get_softc(dev); mtx_lock(&sc->sc_mtx); error = iicoc_init(dev); mtx_unlock(&sc->sc_mtx); return (error); } static int iicoc_repeated_start(device_t dev, u_char slave, int timeout) { return 0; } static device_method_t iicoc_methods[] = { /* device interface */ DEVMETHOD(device_probe, iicoc_probe), DEVMETHOD(device_attach, iicoc_attach), DEVMETHOD(device_detach, iicoc_detach), /* iicbus interface */ DEVMETHOD(iicbus_callback, iicbus_null_callback), DEVMETHOD(iicbus_repeated_start, iicoc_repeated_start), DEVMETHOD(iicbus_start, iicoc_start), DEVMETHOD(iicbus_stop, iicoc_stop), DEVMETHOD(iicbus_reset, iicoc_reset), DEVMETHOD(iicbus_write, iicoc_write), DEVMETHOD(iicbus_read, iicoc_read), DEVMETHOD(iicbus_transfer, iicbus_transfer_gen), DEVMETHOD_END }; static driver_t iicoc_driver = { "iicoc", iicoc_methods, sizeof(struct iicoc_softc), }; DRIVER_MODULE(iicoc, pci, iicoc_driver, iicoc_devclass, 0, 0); DRIVER_MODULE(iicbus, iicoc, iicbus_driver, iicbus_devclass, 0, 0); Index: stable/10/sys/dev/iicbus/iiconf.c =================================================================== --- stable/10/sys/dev/iicbus/iiconf.c (revision 289665) +++ stable/10/sys/dev/iicbus/iiconf.c (revision 289666) @@ -1,413 +1,456 @@ /*- * Copyright (c) 1998 Nicolas Souchu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include "iicbus_if.h" /* + * Translate IIC_Exxxxx status values to vaguely-equivelent errno values. + */ +int +iic2errno(int iic_status) +{ + switch (iic_status) { + case IIC_NOERR: return (0); + case IIC_EBUSERR: return (EALREADY); + case IIC_ENOACK: return (EIO); + case IIC_ETIMEOUT: return (ETIMEDOUT); + case IIC_EBUSBSY: return (EWOULDBLOCK); + case IIC_ESTATUS: return (EPROTO); + case IIC_EUNDERFLOW: return (EIO); + case IIC_EOVERFLOW: return (EOVERFLOW); + case IIC_ENOTSUPP: return (EOPNOTSUPP); + case IIC_ENOADDR: return (EADDRNOTAVAIL); + case IIC_ERESOURCE: return (ENOMEM); + default: return (EIO); + } +} + +/* * iicbus_intr() */ void iicbus_intr(device_t bus, int event, char *buf) { struct iicbus_softc *sc = (struct iicbus_softc *)device_get_softc(bus); /* call owner's intr routine */ if (sc->owner) IICBUS_INTR(sc->owner, event, buf); return; } static int iicbus_poll(struct iicbus_softc *sc, int how) { int error; IICBUS_ASSERT_LOCKED(sc); switch (how) { case IIC_WAIT | IIC_INTR: error = mtx_sleep(sc, &sc->lock, IICPRI|PCATCH, "iicreq", 0); break; case IIC_WAIT | IIC_NOINTR: error = mtx_sleep(sc, &sc->lock, IICPRI, "iicreq", 0); break; default: - return (EWOULDBLOCK); - break; + return (IIC_EBUSBSY); } return (error); } /* * iicbus_request_bus() * * Allocate the device to perform transfers. * * how : IIC_WAIT or IIC_DONTWAIT */ int iicbus_request_bus(device_t bus, device_t dev, int how) { struct iicbus_softc *sc = (struct iicbus_softc *)device_get_softc(bus); int error = 0; - /* first, ask the underlying layers if the request is ok */ IICBUS_LOCK(sc); - do { - error = IICBUS_CALLBACK(device_get_parent(bus), - IIC_REQUEST_BUS, (caddr_t)&how); - if (error) - error = iicbus_poll(sc, how); - } while (error == EWOULDBLOCK); - while (!error) { - if (sc->owner && sc->owner != dev) { + while ((error == 0) && (sc->owner != NULL)) + error = iicbus_poll(sc, how); - error = iicbus_poll(sc, how); - } else { - sc->owner = dev; + if (error == 0) { + sc->owner = dev; + /* + * Drop the lock around the call to the bus driver. + * This call should be allowed to sleep in the IIC_WAIT case. + * Drivers might also need to grab locks that would cause LOR + * if our lock is held. + */ + IICBUS_UNLOCK(sc); + /* Ask the underlying layers if the request is ok */ + error = IICBUS_CALLBACK(device_get_parent(bus), + IIC_REQUEST_BUS, (caddr_t)&how); + IICBUS_LOCK(sc); - IICBUS_UNLOCK(sc); - return (0); + if (error != 0) { + sc->owner = NULL; + wakeup_one(sc); } - - /* free any allocated resource */ - if (error) - IICBUS_CALLBACK(device_get_parent(bus), IIC_RELEASE_BUS, - (caddr_t)&how); } + + IICBUS_UNLOCK(sc); return (error); } /* * iicbus_release_bus() * * Release the device allocated with iicbus_request_dev() */ int iicbus_release_bus(device_t bus, device_t dev) { struct iicbus_softc *sc = (struct iicbus_softc *)device_get_softc(bus); int error; - /* first, ask the underlying layers if the release is ok */ - error = IICBUS_CALLBACK(device_get_parent(bus), IIC_RELEASE_BUS, NULL); - - if (error) - return (error); - IICBUS_LOCK(sc); if (sc->owner != dev) { IICBUS_UNLOCK(sc); - return (EACCES); + return (IIC_EBUSBSY); } - sc->owner = NULL; - - /* wakeup waiting processes */ - wakeup(sc); + /* + * Drop the lock around the call to the bus driver. + * This call should be allowed to sleep in the IIC_WAIT case. + * Drivers might also need to grab locks that would cause LOR + * if our lock is held. + */ IICBUS_UNLOCK(sc); + /* Ask the underlying layers if the release is ok */ + error = IICBUS_CALLBACK(device_get_parent(bus), IIC_RELEASE_BUS, NULL); - return (0); + if (error == 0) { + IICBUS_LOCK(sc); + sc->owner = NULL; + + /* wakeup a waiting thread */ + wakeup_one(sc); + IICBUS_UNLOCK(sc); + } + + return (error); } /* * iicbus_started() * * Test if the iicbus is started by the controller */ int iicbus_started(device_t bus) { struct iicbus_softc *sc = (struct iicbus_softc *)device_get_softc(bus); return (sc->started); } /* * iicbus_start() * * Send start condition to the slave addressed by 'slave' */ int iicbus_start(device_t bus, u_char slave, int timeout) { struct iicbus_softc *sc = (struct iicbus_softc *)device_get_softc(bus); int error = 0; if (sc->started) - return (EINVAL); /* bus already started */ + return (IIC_ESTATUS); /* protocol error, bus already started */ if (!(error = IICBUS_START(device_get_parent(bus), slave, timeout))) sc->started = slave; else sc->started = 0; return (error); } /* * iicbus_repeated_start() * * Send start condition to the slave addressed by 'slave' */ int iicbus_repeated_start(device_t bus, u_char slave, int timeout) { struct iicbus_softc *sc = (struct iicbus_softc *)device_get_softc(bus); int error = 0; if (!sc->started) - return (EINVAL); /* bus should have been already started */ + return (IIC_ESTATUS); /* protocol error, bus not started */ if (!(error = IICBUS_REPEATED_START(device_get_parent(bus), slave, timeout))) sc->started = slave; else sc->started = 0; return (error); } /* * iicbus_stop() * * Send stop condition to the bus */ int iicbus_stop(device_t bus) { struct iicbus_softc *sc = (struct iicbus_softc *)device_get_softc(bus); int error = 0; if (!sc->started) - return (EINVAL); /* bus not started */ + return (IIC_ESTATUS); /* protocol error, bus not started */ error = IICBUS_STOP(device_get_parent(bus)); /* refuse any further access */ sc->started = 0; return (error); } /* * iicbus_write() * * Write a block of data to the slave previously started by * iicbus_start() call */ int iicbus_write(device_t bus, const char *buf, int len, int *sent, int timeout) { struct iicbus_softc *sc = (struct iicbus_softc *)device_get_softc(bus); /* a slave must have been started for writing */ if (sc->started == 0 || (sc->strict != 0 && (sc->started & LSB) != 0)) - return (EINVAL); + return (IIC_ESTATUS); return (IICBUS_WRITE(device_get_parent(bus), buf, len, sent, timeout)); } /* * iicbus_read() * * Read a block of data from the slave previously started by * iicbus_read() call */ int iicbus_read(device_t bus, char *buf, int len, int *read, int last, int delay) { struct iicbus_softc *sc = (struct iicbus_softc *)device_get_softc(bus); /* a slave must have been started for reading */ if (sc->started == 0 || (sc->strict != 0 && (sc->started & LSB) == 0)) - return (EINVAL); + return (IIC_ESTATUS); return (IICBUS_READ(device_get_parent(bus), buf, len, read, last, delay)); } /* * iicbus_write_byte() * * Write a byte to the slave previously started by iicbus_start() call */ int iicbus_write_byte(device_t bus, char byte, int timeout) { + struct iicbus_softc *sc = device_get_softc(bus); char data = byte; int sent; + /* a slave must have been started for writing */ + if (sc->started == 0 || (sc->strict != 0 && (sc->started & LSB) != 0)) + return (IIC_ESTATUS); + return (iicbus_write(bus, &data, 1, &sent, timeout)); } /* * iicbus_read_byte() * * Read a byte from the slave previously started by iicbus_start() call */ int iicbus_read_byte(device_t bus, char *byte, int timeout) { + struct iicbus_softc *sc = device_get_softc(bus); int read; + /* a slave must have been started for reading */ + if (sc->started == 0 || (sc->strict != 0 && (sc->started & LSB) == 0)) + return (IIC_ESTATUS); + return (iicbus_read(bus, byte, 1, &read, IIC_LAST_READ, timeout)); } /* * iicbus_block_write() * * Write a block of data to slave ; start/stop protocol managed */ int iicbus_block_write(device_t bus, u_char slave, char *buf, int len, int *sent) { u_char addr = slave & ~LSB; int error; if ((error = iicbus_start(bus, addr, 0))) return (error); error = iicbus_write(bus, buf, len, sent, 0); iicbus_stop(bus); return (error); } /* * iicbus_block_read() * * Read a block of data from slave ; start/stop protocol managed */ int iicbus_block_read(device_t bus, u_char slave, char *buf, int len, int *read) { u_char addr = slave | LSB; int error; if ((error = iicbus_start(bus, addr, 0))) return (error); error = iicbus_read(bus, buf, len, read, IIC_LAST_READ, 0); iicbus_stop(bus); return (error); } /* * iicbus_transfer() * * Do an aribtrary number of transfers on the iicbus. We pass these * raw requests to the bridge driver. If the bridge driver supports * them directly, then it manages all the details. If not, it can use * the helper function iicbus_transfer_gen() which will do the * transfers at a low level. * * Pointers passed in as part of iic_msg must be kernel pointers. * Callers that have user addresses to manage must do so on their own. */ int iicbus_transfer(device_t bus, struct iic_msg *msgs, uint32_t nmsgs) { + return (IICBUS_TRANSFER(device_get_parent(bus), msgs, nmsgs)); } /* * Generic version of iicbus_transfer that calls the appropriate * routines to accomplish this. See note above about acceptable * buffer addresses. */ int iicbus_transfer_gen(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) { int i, error, lenread, lenwrote, nkid, rpstart, addr; device_t *children, bus; bool nostop; if ((error = device_get_children(dev, &children, &nkid)) != 0) - return (error); + return (IIC_ERESOURCE); if (nkid != 1) { free(children, M_TEMP); - return (EIO); + return (IIC_ENOTSUPP); } bus = children[0]; rpstart = 0; free(children, M_TEMP); nostop = iicbus_get_nostop(dev); for (i = 0, error = 0; i < nmsgs && error == 0; i++) { addr = msgs[i].slave; if (msgs[i].flags & IIC_M_RD) addr |= LSB; else addr &= ~LSB; if (!(msgs[i].flags & IIC_M_NOSTART)) { if (rpstart) error = iicbus_repeated_start(bus, addr, 0); else error = iicbus_start(bus, addr, 0); } - - if (error) + if (error != 0) break; if (msgs[i].flags & IIC_M_RD) error = iicbus_read(bus, msgs[i].buf, msgs[i].len, &lenread, IIC_LAST_READ, 0); else error = iicbus_write(bus, msgs[i].buf, msgs[i].len, &lenwrote, 0); + if (error != 0) + break; if ((msgs[i].flags & IIC_M_NOSTOP) != 0 || (nostop && i + 1 < nmsgs)) { rpstart = 1; /* Next message gets repeated start */ } else { rpstart = 0; iicbus_stop(bus); } } + if (error != 0 && !nostop) + iicbus_stop(bus); return (error); } Index: stable/10/sys/dev/iicbus/iiconf.h =================================================================== --- stable/10/sys/dev/iicbus/iiconf.h (revision 289665) +++ stable/10/sys/dev/iicbus/iiconf.h (revision 289666) @@ -1,140 +1,147 @@ /*- * Copyright (c) 1998, 2001 Nicolas Souchu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef __IICONF_H #define __IICONF_H #include #include #define IICPRI (PZERO+8) /* XXX sleep/wakeup queue priority */ #define LSB 0x1 /* * How tsleep() is called in iic_request_bus(). */ #define IIC_DONTWAIT 0 #define IIC_NOINTR 0 #define IIC_WAIT 0x1 #define IIC_INTR 0x2 +#define IIC_INTRWAIT (IIC_INTR | IIC_WAIT) /* * i2c modes */ #define IIC_MASTER 0x1 #define IIC_SLAVE 0x2 #define IIC_POLLED 0x4 /* * i2c speed */ #define IIC_UNKNOWN 0x0 #define IIC_SLOW 0x1 #define IIC_FAST 0x2 #define IIC_FASTEST 0x3 #define IIC_LAST_READ 0x1 /* * callback index */ #define IIC_REQUEST_BUS 0x1 #define IIC_RELEASE_BUS 0x2 /* * interrupt events */ #define INTR_GENERAL 0x1 /* general call received */ #define INTR_START 0x2 /* the I2C interface is addressed */ #define INTR_STOP 0x3 /* stop condition received */ #define INTR_RECEIVE 0x4 /* character received */ #define INTR_TRANSMIT 0x5 /* character to transmit */ #define INTR_ERROR 0x6 /* error */ #define INTR_NOACK 0x7 /* no ack from master receiver */ /* * adapter layer errors */ #define IIC_NOERR 0x0 /* no error occured */ -#define IIC_EBUSERR 0x1 /* bus error */ +#define IIC_EBUSERR 0x1 /* bus error (hardware not in expected state) */ #define IIC_ENOACK 0x2 /* ack not received until timeout */ #define IIC_ETIMEOUT 0x3 /* timeout */ -#define IIC_EBUSBSY 0x4 /* bus busy */ +#define IIC_EBUSBSY 0x4 /* bus busy (reserved by another client) */ #define IIC_ESTATUS 0x5 /* status error */ #define IIC_EUNDERFLOW 0x6 /* slave ready for more data */ #define IIC_EOVERFLOW 0x7 /* too much data */ #define IIC_ENOTSUPP 0x8 /* request not supported */ #define IIC_ENOADDR 0x9 /* no address assigned to the interface */ +#define IIC_ERESOURCE 0xa /* resources (memory, whatever) unavailable */ +/* + * Note that all iicbus functions return IIC_Exxxxx status values, + * except iic2errno() (obviously) and iicbus_started() (returns bool). + */ +extern int iic2errno(int); extern int iicbus_request_bus(device_t, device_t, int); extern int iicbus_release_bus(device_t, device_t); extern device_t iicbus_alloc_bus(device_t); extern void iicbus_intr(device_t, int, char *); extern int iicbus_null_repeated_start(device_t, u_char); extern int iicbus_null_callback(device_t, int, caddr_t); #define iicbus_reset(bus,speed,addr,oldaddr) \ (IICBUS_RESET(device_get_parent(bus), speed, addr, oldaddr)) /* basic I2C operations */ extern int iicbus_started(device_t); extern int iicbus_start(device_t, u_char, int); extern int iicbus_stop(device_t); extern int iicbus_repeated_start(device_t, u_char, int); extern int iicbus_write(device_t, const char *, int, int *, int); extern int iicbus_read(device_t, char *, int, int *, int, int); /* single byte read/write functions, start/stop not managed */ extern int iicbus_write_byte(device_t, char, int); extern int iicbus_read_byte(device_t, char *, int); /* Read/write operations with start/stop conditions managed */ extern int iicbus_block_write(device_t, u_char, char *, int, int *); extern int iicbus_block_read(device_t, u_char, char *, int, int *); /* vectors of iic operations to pass to bridge */ int iicbus_transfer(device_t bus, struct iic_msg *msgs, uint32_t nmsgs); int iicbus_transfer_gen(device_t bus, struct iic_msg *msgs, uint32_t nmsgs); #define IICBUS_MODVER 1 #define IICBUS_MINVER 1 #define IICBUS_MAXVER 1 #define IICBUS_PREFVER IICBUS_MODVER extern driver_t iicbb_driver; extern devclass_t iicbb_devclass; #define IICBB_MODVER 1 #define IICBB_MINVER 1 #define IICBB_MAXVER 1 #define IICBB_PREFVER IICBB_MODVER #endif Index: stable/10/sys/dev/pcf/pcf.c =================================================================== --- stable/10/sys/dev/pcf/pcf.c (revision 289665) +++ stable/10/sys/dev/pcf/pcf.c (revision 289666) @@ -1,485 +1,485 @@ /*- * Copyright (c) 1998 Nicolas Souchu, Marc Bouget * Copyright (c) 2004 Joerg Wunsch * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include "iicbus_if.h" /* Not so official debugging option. */ /* #define PCFDEBUG */ static int pcf_wait_byte(struct pcf_softc *pcf); static int pcf_noack(struct pcf_softc *pcf, int timeout); static void pcf_stop_locked(struct pcf_softc *pcf); /* * Polling mode for master operations wait for a new * byte incoming or outgoing */ static int pcf_wait_byte(struct pcf_softc *sc) { int counter = TIMEOUT; PCF_ASSERT_LOCKED(sc); while (counter--) { if ((pcf_get_S1(sc) & PIN) == 0) return (0); } #ifdef PCFDEBUG printf("pcf: timeout!\n"); #endif return (IIC_ETIMEOUT); } static void pcf_stop_locked(struct pcf_softc *sc) { PCF_ASSERT_LOCKED(sc); #ifdef PCFDEBUG device_printf(dev, " >> stop\n"); #endif /* * Send STOP condition iff the START condition was previously sent. * STOP is sent only once even if an iicbus_stop() is called after * an iicbus_read()... see pcf_read(): the PCF needs to send the stop * before the last char is read. */ if (sc->pcf_started) { /* set stop condition and enable IT */ pcf_set_S1(sc, PIN|ESO|ENI|STO|ACK); sc->pcf_started = 0; } } static int pcf_noack(struct pcf_softc *sc, int timeout) { int noack; int k = timeout/10; PCF_ASSERT_LOCKED(sc); do { noack = pcf_get_S1(sc) & LRB; if (!noack) break; DELAY(10); /* XXX wait 10 us */ } while (k--); return (noack); } int pcf_repeated_start(device_t dev, u_char slave, int timeout) { struct pcf_softc *sc = DEVTOSOFTC(dev); int error = 0; PCF_LOCK(sc); #ifdef PCFDEBUG device_printf(dev, " >> repeated start for slave %#x\n", (unsigned)slave); #endif /* repeated start */ pcf_set_S1(sc, ESO|STA|STO|ACK); /* set slave address to PCF. Last bit (LSB) must be set correctly * according to transfer direction */ pcf_set_S0(sc, slave); /* wait for address sent, polling */ if ((error = pcf_wait_byte(sc))) goto error; /* check for ack */ if (pcf_noack(sc, timeout)) { error = IIC_ENOACK; #ifdef PCFDEBUG printf("pcf: no ack on repeated_start!\n"); #endif goto error; } PCF_UNLOCK(sc); return (0); error: pcf_stop_locked(sc); PCF_UNLOCK(sc); return (error); } int pcf_start(device_t dev, u_char slave, int timeout) { struct pcf_softc *sc = DEVTOSOFTC(dev); int error = 0; PCF_LOCK(sc); #ifdef PCFDEBUG device_printf(dev, " >> start for slave %#x\n", (unsigned)slave); #endif if ((pcf_get_S1(sc) & nBB) == 0) { #ifdef PCFDEBUG printf("pcf: busy!\n"); #endif PCF_UNLOCK(sc); - return (IIC_EBUSBSY); + return (IIC_EBUSERR); } /* set slave address to PCF. Last bit (LSB) must be set correctly * according to transfer direction */ pcf_set_S0(sc, slave); /* START only */ pcf_set_S1(sc, PIN|ESO|STA|ACK); sc->pcf_started = 1; /* wait for address sent, polling */ if ((error = pcf_wait_byte(sc))) goto error; /* check for ACK */ if (pcf_noack(sc, timeout)) { error = IIC_ENOACK; #ifdef PCFDEBUG printf("pcf: no ack on start!\n"); #endif goto error; } PCF_UNLOCK(sc); return (0); error: pcf_stop_locked(sc); PCF_UNLOCK(sc); return (error); } int pcf_stop(device_t dev) { struct pcf_softc *sc = DEVTOSOFTC(dev); #ifdef PCFDEBUG device_printf(dev, " >> stop\n"); #endif PCF_LOCK(sc); pcf_stop_locked(sc); PCF_UNLOCK(sc); return (0); } void pcf_intr(void *arg) { struct pcf_softc *sc = arg; char data, status, addr; char error = 0; PCF_LOCK(sc); status = pcf_get_S1(sc); if (status & PIN) { printf("pcf: spurious interrupt, status=0x%x\n", status & 0xff); goto error; } if (status & LAB) printf("pcf: bus arbitration lost!\n"); if (status & BER) { error = IIC_EBUSERR; iicbus_intr(sc->iicbus, INTR_ERROR, &error); goto error; } do { status = pcf_get_S1(sc); switch(sc->pcf_slave_mode) { case SLAVE_TRANSMITTER: if (status & LRB) { /* ack interrupt line */ dummy_write(sc); /* no ack, don't send anymore */ sc->pcf_slave_mode = SLAVE_RECEIVER; iicbus_intr(sc->iicbus, INTR_NOACK, NULL); break; } /* get data from upper code */ iicbus_intr(sc->iicbus, INTR_TRANSMIT, &data); pcf_set_S0(sc, data); break; case SLAVE_RECEIVER: if (status & AAS) { addr = pcf_get_S0(sc); if (status & AD0) iicbus_intr(sc->iicbus, INTR_GENERAL, &addr); else iicbus_intr(sc->iicbus, INTR_START, &addr); if (addr & LSB) { sc->pcf_slave_mode = SLAVE_TRANSMITTER; /* get the first char from upper code */ iicbus_intr(sc->iicbus, INTR_TRANSMIT, &data); /* send first data byte */ pcf_set_S0(sc, data); } break; } /* stop condition received? */ if (status & STS) { /* ack interrupt line */ dummy_read(sc); /* emulate intr stop condition */ iicbus_intr(sc->iicbus, INTR_STOP, NULL); } else { /* get data, ack interrupt line */ data = pcf_get_S0(sc); /* deliver the character */ iicbus_intr(sc->iicbus, INTR_RECEIVE, &data); } break; default: panic("%s: unknown slave mode (%d)!", __func__, sc->pcf_slave_mode); } } while ((pcf_get_S1(sc) & PIN) == 0); PCF_UNLOCK(sc); return; error: /* unknown event on bus...reset PCF */ pcf_set_S1(sc, PIN|ESO|ENI|ACK); sc->pcf_slave_mode = SLAVE_RECEIVER; PCF_UNLOCK(sc); return; } int pcf_rst_card(device_t dev, u_char speed, u_char addr, u_char *oldaddr) { struct pcf_softc *sc = DEVTOSOFTC(dev); PCF_LOCK(sc); if (oldaddr) *oldaddr = sc->pcf_addr; /* retrieve own address from bus level */ if (!addr) sc->pcf_addr = PCF_DEFAULT_ADDR; else sc->pcf_addr = addr; pcf_set_S1(sc, PIN); /* initialize S1 */ /* own address S'O<>0 */ pcf_set_S0(sc, sc->pcf_addr >> 1); /* select clock register */ pcf_set_S1(sc, PIN|ES1); /* select bus speed : 18=90kb, 19=45kb, 1A=11kb, 1B=1.5kb */ switch (speed) { case IIC_SLOW: pcf_set_S0(sc, 0x1b); /* XXX Sun uses 0x1f */ break; case IIC_FAST: pcf_set_S0(sc, 0x19); /* XXX Sun: 0x1d */ break; case IIC_UNKNOWN: case IIC_FASTEST: default: pcf_set_S0(sc, 0x18); /* XXX Sun: 0x1c */ break; } /* set bus on, ack=yes, INT=yes */ pcf_set_S1(sc, PIN|ESO|ENI|ACK); sc->pcf_slave_mode = SLAVE_RECEIVER; PCF_UNLOCK(sc); return (0); } int pcf_write(device_t dev, const char *buf, int len, int *sent, int timeout /* us */) { struct pcf_softc *sc = DEVTOSOFTC(dev); int bytes, error = 0; #ifdef PCFDEBUG device_printf(dev, " >> writing %d bytes: %#x%s\n", len, (unsigned)buf[0], len > 1? "...": ""); #endif bytes = 0; PCF_LOCK(sc); while (len) { pcf_set_S0(sc, *buf++); /* wait for the byte to be send */ if ((error = pcf_wait_byte(sc))) goto error; /* check if ack received */ if (pcf_noack(sc, timeout)) { error = IIC_ENOACK; goto error; } len --; bytes ++; } error: *sent = bytes; PCF_UNLOCK(sc); #ifdef PCFDEBUG device_printf(dev, " >> %d bytes written (%d)\n", bytes, error); #endif return (error); } int pcf_read(device_t dev, char *buf, int len, int *read, int last, int delay /* us */) { struct pcf_softc *sc = DEVTOSOFTC(dev); int bytes, error = 0; #ifdef PCFDEBUG char *obuf = buf; device_printf(dev, " << reading %d bytes\n", len); #endif PCF_LOCK(sc); /* trig the bus to get the first data byte in S0 */ if (len) { if (len == 1 && last) /* just one byte to read */ pcf_set_S1(sc, ESO); /* no ack */ dummy_read(sc); } bytes = 0; while (len) { /* XXX delay needed here */ /* wait for trigged byte */ if ((error = pcf_wait_byte(sc))) { pcf_stop_locked(sc); goto error; } if (len == 1 && last) /* ok, last data byte already in S0, no I2C activity * on next pcf_get_S0() */ pcf_stop_locked(sc); else if (len == 2 && last) /* next trigged byte with no ack */ pcf_set_S1(sc, ESO); /* receive byte, trig next byte */ *buf++ = pcf_get_S0(sc); len --; bytes ++; }; error: *read = bytes; PCF_UNLOCK(sc); #ifdef PCFDEBUG device_printf(dev, " << %d bytes read (%d): %#x%s\n", bytes, error, (unsigned)obuf[0], bytes > 1? "...": ""); #endif return (error); } DRIVER_MODULE(iicbus, pcf, iicbus_driver, iicbus_devclass, 0, 0); MODULE_DEPEND(pcf, iicbus, PCF_MINVER, PCF_PREFVER, PCF_MAXVER); MODULE_VERSION(pcf, PCF_MODVER); Index: stable/10/sys/powerpc/mpc85xx/i2c.c =================================================================== --- stable/10/sys/powerpc/mpc85xx/i2c.c (revision 289665) +++ stable/10/sys/powerpc/mpc85xx/i2c.c (revision 289666) @@ -1,427 +1,427 @@ /*- * Copyright (C) 2008-2009 Semihalf, Michal Hajduk * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include "iicbus_if.h" #include #include #define I2C_ADDR_REG 0x00 /* I2C slave address register */ #define I2C_FDR_REG 0x04 /* I2C frequency divider register */ #define I2C_CONTROL_REG 0x08 /* I2C control register */ #define I2C_STATUS_REG 0x0C /* I2C status register */ #define I2C_DATA_REG 0x10 /* I2C data register */ #define I2C_DFSRR_REG 0x14 /* I2C Digital Filter Sampling rate */ #define I2C_ENABLE 0x80 /* Module enable - interrupt disable */ #define I2CSR_RXAK 0x01 /* Received acknowledge */ #define I2CSR_MCF (1<<7) /* Data transfer */ #define I2CSR_MASS (1<<6) /* Addressed as a slave */ #define I2CSR_MBB (1<<5) /* Bus busy */ #define I2CSR_MAL (1<<4) /* Arbitration lost */ #define I2CSR_SRW (1<<2) /* Slave read/write */ #define I2CSR_MIF (1<<1) /* Module interrupt */ #define I2CCR_MEN (1<<7) /* Module enable */ #define I2CCR_MSTA (1<<5) /* Master/slave mode */ #define I2CCR_MTX (1<<4) /* Transmit/receive mode */ #define I2CCR_TXAK (1<<3) /* Transfer acknowledge */ #define I2CCR_RSTA (1<<2) /* Repeated START */ #define I2C_BAUD_RATE_FAST 0x31 #define I2C_BAUD_RATE_DEF 0x3F #define I2C_DFSSR_DIV 0x10 #ifdef DEBUG #define debugf(fmt, args...) do { printf("%s(): ", __func__); printf(fmt,##args); } while (0) #else #define debugf(fmt, args...) #endif struct i2c_softc { device_t dev; device_t iicbus; struct resource *res; struct mtx mutex; int rid; bus_space_handle_t bsh; bus_space_tag_t bst; }; static int i2c_probe(device_t); static int i2c_attach(device_t); static int i2c_repeated_start(device_t dev, u_char slave, int timeout); static int i2c_start(device_t dev, u_char slave, int timeout); static int i2c_stop(device_t dev); static int i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr); static int i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay); static int i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout); static device_method_t i2c_methods[] = { DEVMETHOD(device_probe, i2c_probe), DEVMETHOD(device_attach, i2c_attach), DEVMETHOD(iicbus_callback, iicbus_null_callback), DEVMETHOD(iicbus_repeated_start, i2c_repeated_start), DEVMETHOD(iicbus_start, i2c_start), DEVMETHOD(iicbus_stop, i2c_stop), DEVMETHOD(iicbus_reset, i2c_reset), DEVMETHOD(iicbus_read, i2c_read), DEVMETHOD(iicbus_write, i2c_write), DEVMETHOD(iicbus_transfer, iicbus_transfer_gen), { 0, 0 } }; static driver_t i2c_driver = { "i2c", i2c_methods, sizeof(struct i2c_softc), }; static devclass_t i2c_devclass; DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0); DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0); static __inline void i2c_write_reg(struct i2c_softc *sc, bus_size_t off, uint8_t val) { bus_space_write_1(sc->bst, sc->bsh, off, val); } static __inline uint8_t i2c_read_reg(struct i2c_softc *sc, bus_size_t off) { return (bus_space_read_1(sc->bst, sc->bsh, off)); } static __inline void i2c_flag_set(struct i2c_softc *sc, bus_size_t off, uint8_t mask) { uint8_t status; status = i2c_read_reg(sc, off); status |= mask; i2c_write_reg(sc, off, status); } static int i2c_do_wait(device_t dev, struct i2c_softc *sc, int write, int start) { int err; uint8_t status; status = i2c_read_reg(sc, I2C_STATUS_REG); if (status & I2CSR_MIF) { if (write && start && (status & I2CSR_RXAK)) { debugf("no ack %s", start ? "after sending slave address" : ""); err = IIC_ENOACK; goto error; } if (status & I2CSR_MAL) { debugf("arbitration lost"); err = IIC_EBUSERR; goto error; } if (!write && !(status & I2CSR_MCF)) { debugf("transfer unfinished"); err = IIC_EBUSERR; goto error; } } return (IIC_NOERR); error: i2c_write_reg(sc, I2C_STATUS_REG, 0x0); i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_TXAK); return (err); } static int i2c_probe(device_t dev) { struct i2c_softc *sc; if (!ofw_bus_is_compatible(dev, "fsl-i2c")) return (ENXIO); sc = device_get_softc(dev); sc->rid = 0; sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid, RF_ACTIVE); if (sc->res == NULL) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } sc->bst = rman_get_bustag(sc->res); sc->bsh = rman_get_bushandle(sc->res); /* Enable I2C */ i2c_write_reg(sc, I2C_CONTROL_REG, I2C_ENABLE); bus_release_resource(dev, SYS_RES_MEMORY, sc->rid, sc->res); device_set_desc(dev, "I2C bus controller"); return (BUS_PROBE_DEFAULT); } static int i2c_attach(device_t dev) { struct i2c_softc *sc; sc = device_get_softc(dev); sc->dev = dev; sc->rid = 0; mtx_init(&sc->mutex, device_get_nameunit(dev), "I2C", MTX_DEF); sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid, RF_ACTIVE); if (sc->res == NULL) { device_printf(dev, "could not allocate resources"); mtx_destroy(&sc->mutex); return (ENXIO); } sc->bst = rman_get_bustag(sc->res); sc->bsh = rman_get_bushandle(sc->res); sc->iicbus = device_add_child(dev, "iicbus", -1); if (sc->iicbus == NULL) { device_printf(dev, "could not add iicbus child"); mtx_destroy(&sc->mutex); return (ENXIO); } bus_generic_attach(dev); return (IIC_NOERR); } static int i2c_repeated_start(device_t dev, u_char slave, int timeout) { struct i2c_softc *sc; int error; sc = device_get_softc(dev); mtx_lock(&sc->mutex); /* Set repeated start condition */ i2c_flag_set(sc, I2C_CONTROL_REG ,I2CCR_RSTA); /* Write target address - LSB is R/W bit */ i2c_write_reg(sc, I2C_DATA_REG, slave); DELAY(1250); error = i2c_do_wait(dev, sc, 1, 1); mtx_unlock(&sc->mutex); if (error) return (error); return (IIC_NOERR); } static int i2c_start(device_t dev, u_char slave, int timeout) { struct i2c_softc *sc; uint8_t status; int error; sc = device_get_softc(dev); DELAY(1000); mtx_lock(&sc->mutex); status = i2c_read_reg(sc, I2C_STATUS_REG); /* Check if bus is idle or busy */ if (status & I2CSR_MBB) { debugf("bus busy"); mtx_unlock(&sc->mutex); i2c_stop(dev); - return (IIC_EBUSBSY); + return (IIC_EBUSERR); } /* Set start condition */ i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX); /* Write target address - LSB is R/W bit */ i2c_write_reg(sc, I2C_DATA_REG, slave); DELAY(1250); error = i2c_do_wait(dev, sc, 1, 1); mtx_unlock(&sc->mutex); if (error) return (error); return (IIC_NOERR); } static int i2c_stop(device_t dev) { struct i2c_softc *sc; sc = device_get_softc(dev); mtx_lock(&sc->mutex); i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_TXAK); DELAY(1000); mtx_unlock(&sc->mutex); return (IIC_NOERR); } static int i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr) { struct i2c_softc *sc; uint8_t baud_rate; sc = device_get_softc(dev); switch (speed) { case IIC_FAST: baud_rate = I2C_BAUD_RATE_FAST; break; case IIC_SLOW: case IIC_UNKNOWN: case IIC_FASTEST: default: baud_rate = I2C_BAUD_RATE_DEF; break; } mtx_lock(&sc->mutex); i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); i2c_write_reg(sc, I2C_STATUS_REG, 0x0); DELAY(1000); i2c_write_reg(sc, I2C_FDR_REG, baud_rate); i2c_write_reg(sc, I2C_DFSRR_REG, I2C_DFSSR_DIV); i2c_write_reg(sc, I2C_CONTROL_REG, I2C_ENABLE); DELAY(1000); mtx_unlock(&sc->mutex); return (IIC_NOERR); } static int i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay) { struct i2c_softc *sc; int error; sc = device_get_softc(dev); *read = 0; mtx_lock(&sc->mutex); if (len) { if (len == 1) i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_TXAK); else i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA); /* dummy read */ i2c_read_reg(sc, I2C_DATA_REG); DELAY(1000); } while (*read < len) { DELAY(1000); error = i2c_do_wait(dev, sc, 0, 0); if (error) { mtx_unlock(&sc->mutex); return (error); } if ((*read == len - 2) && last) { i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_TXAK); } if ((*read == len - 1) && last) { i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_TXAK); } *buf++ = i2c_read_reg(sc, I2C_DATA_REG); (*read)++; DELAY(1250); } mtx_unlock(&sc->mutex); return (IIC_NOERR); } static int i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout) { struct i2c_softc *sc; int error; sc = device_get_softc(dev); *sent = 0; mtx_lock(&sc->mutex); while (*sent < len) { i2c_write_reg(sc, I2C_DATA_REG, *buf++); DELAY(1250); error = i2c_do_wait(dev, sc, 1, 0); if (error) { mtx_unlock(&sc->mutex); return (error); } (*sent)++; } mtx_unlock(&sc->mutex); return (IIC_NOERR); } Index: stable/10 =================================================================== --- stable/10 (revision 289665) +++ stable/10 (revision 289666) Property changes on: stable/10 ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head:r281828,289083-289084,289091,289093,289095,289097-289098,289104-289105,289118