Index: head/sys/dev/iwm/if_iwmvar.h =================================================================== --- head/sys/dev/iwm/if_iwmvar.h (revision 289167) +++ head/sys/dev/iwm/if_iwmvar.h (revision 289168) @@ -1,530 +1,528 @@ /* $OpenBSD: if_iwmvar.h,v 1.7 2015/03/02 13:51:10 jsg Exp $ */ /* $FreeBSD$ */ /* * Copyright (c) 2014 genua mbh * Copyright (c) 2014 Fixup Software Ltd. * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ /*- * Based on BSD-licensed source modules in the Linux iwlwifi driver, * which were used as the reference documentation for this implementation. * * Driver version we are currently based off of is * Linux 3.14.3 (tag id a2df521e42b1d9a23f620ac79dbfe8655a8391dd) * *********************************************************************** * * This file is provided under a dual BSD/GPLv2 license. When using or * redistributing this file, you may do so under either license. * * GPL LICENSE SUMMARY * * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, * USA * * The full GNU General Public License is included in this distribution * in the file called COPYING. * * Contact Information: * Intel Linux Wireless * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 * * * BSD LICENSE * * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * * Neither the name Intel Corporation nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /*- * Copyright (c) 2007-2010 Damien Bergamini * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ struct iwm_rx_radiotap_header { struct ieee80211_radiotap_header wr_ihdr; uint64_t wr_tsft; uint8_t wr_flags; uint8_t wr_rate; uint16_t wr_chan_freq; uint16_t wr_chan_flags; int8_t wr_dbm_antsignal; int8_t wr_dbm_antnoise; } __packed; #define IWM_RX_RADIOTAP_PRESENT \ ((1 << IEEE80211_RADIOTAP_TSFT) | \ (1 << IEEE80211_RADIOTAP_FLAGS) | \ (1 << IEEE80211_RADIOTAP_RATE) | \ (1 << IEEE80211_RADIOTAP_CHANNEL) | \ (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE)) struct iwm_tx_radiotap_header { struct ieee80211_radiotap_header wt_ihdr; uint8_t wt_flags; uint8_t wt_rate; uint16_t wt_chan_freq; uint16_t wt_chan_flags; uint8_t wt_hwqueue; } __packed; #define IWM_TX_RADIOTAP_PRESENT \ ((1 << IEEE80211_RADIOTAP_FLAGS) | \ (1 << IEEE80211_RADIOTAP_RATE) | \ (1 << IEEE80211_RADIOTAP_CHANNEL)) #define IWM_UCODE_SECT_MAX 6 #define IWM_FWDMASEGSZ (192*1024) /* sanity check value */ #define IWM_FWMAXSIZE (2*1024*1024) /* * fw_status is used to determine if we've already parsed the firmware file * * In addition to the following, status < 0 ==> -error */ #define IWM_FW_STATUS_NONE 0 #define IWM_FW_STATUS_INPROGRESS 1 #define IWM_FW_STATUS_DONE 2 #define IWM_LOCK(_sc) mtx_lock(&sc->sc_mtx) #define IWM_UNLOCK(_sc) mtx_unlock(&sc->sc_mtx) enum iwm_ucode_type { IWM_UCODE_TYPE_INIT, IWM_UCODE_TYPE_REGULAR, IWM_UCODE_TYPE_WOW, IWM_UCODE_TYPE_MAX }; struct iwm_fw_info { const void *fw_rawdata; size_t fw_rawsize; int fw_status; struct iwm_fw_sects { struct iwm_fw_onesect { const void *fws_data; uint32_t fws_len; uint32_t fws_devoff; } fw_sect[IWM_UCODE_SECT_MAX]; size_t fw_totlen; int fw_count; } fw_sects[IWM_UCODE_TYPE_MAX]; }; struct iwm_nvm_data { int n_hw_addrs; uint8_t hw_addr[IEEE80211_ADDR_LEN]; uint8_t calib_version; uint16_t calib_voltage; uint16_t raw_temperature; uint16_t kelvin_temperature; uint16_t kelvin_voltage; uint16_t xtal_calib[2]; int sku_cap_band_24GHz_enable; int sku_cap_band_52GHz_enable; int sku_cap_11n_enable; int sku_cap_amt_enable; int sku_cap_ipan_enable; uint8_t radio_cfg_type; uint8_t radio_cfg_step; uint8_t radio_cfg_dash; uint8_t radio_cfg_pnum; uint8_t valid_tx_ant, valid_rx_ant; uint16_t nvm_version; uint8_t max_tx_pwr_half_dbm; }; /* max bufs per tfd the driver will use */ #define IWM_MAX_CMD_TBS_PER_TFD 2 struct iwm_rx_packet; struct iwm_host_cmd { const void *data[IWM_MAX_CMD_TBS_PER_TFD]; struct iwm_rx_packet *resp_pkt; unsigned long _rx_page_addr; uint32_t _rx_page_order; int handler_status; uint32_t flags; uint16_t len[IWM_MAX_CMD_TBS_PER_TFD]; uint8_t dataflags[IWM_MAX_CMD_TBS_PER_TFD]; uint8_t id; }; /* * DMA glue is from iwn */ typedef caddr_t iwm_caddr_t; typedef void *iwm_hookarg_t; struct iwm_dma_info { bus_dma_tag_t tag; bus_dmamap_t map; bus_dma_segment_t seg; bus_addr_t paddr; void *vaddr; bus_size_t size; }; #define IWM_TX_RING_COUNT 256 #define IWM_TX_RING_LOMARK 192 #define IWM_TX_RING_HIMARK 224 struct iwm_tx_data { bus_dmamap_t map; bus_addr_t cmd_paddr; bus_addr_t scratch_paddr; struct mbuf *m; struct iwm_node *in; int done; }; struct iwm_tx_ring { struct iwm_dma_info desc_dma; struct iwm_dma_info cmd_dma; struct iwm_tfd *desc; struct iwm_device_cmd *cmd; bus_dma_tag_t data_dmat; struct iwm_tx_data data[IWM_TX_RING_COUNT]; int qid; int queued; int cur; }; #define IWM_RX_RING_COUNT 256 #define IWM_RBUF_COUNT (IWM_RX_RING_COUNT + 32) /* Linux driver optionally uses 8k buffer */ #define IWM_RBUF_SIZE 4096 #define IWM_MAX_SCATTER 20 struct iwm_softc; struct iwm_rbuf { struct iwm_softc *sc; void *vaddr; bus_addr_t paddr; }; struct iwm_rx_data { struct mbuf *m; bus_dmamap_t map; int wantresp; }; struct iwm_rx_ring { struct iwm_dma_info desc_dma; struct iwm_dma_info stat_dma; struct iwm_dma_info buf_dma; uint32_t *desc; struct iwm_rb_status *stat; struct iwm_rx_data data[IWM_RX_RING_COUNT]; bus_dma_tag_t data_dmat; int cur; }; #define IWM_FLAG_USE_ICT 0x01 #define IWM_FLAG_HW_INITED 0x02 #define IWM_FLAG_STOPPED 0x04 #define IWM_FLAG_RFKILL 0x08 #define IWM_FLAG_BUSY 0x10 struct iwm_ucode_status { uint32_t uc_error_event_table; uint32_t uc_log_event_table; int uc_ok; int uc_intr; }; #define IWM_CMD_RESP_MAX PAGE_SIZE #define IWM_OTP_LOW_IMAGE_SIZE 2048 #define IWM_MVM_TE_SESSION_PROTECTION_MAX_TIME_MS 500 #define IWM_MVM_TE_SESSION_PROTECTION_MIN_TIME_MS 400 /* * Command headers are in iwl-trans.h, which is full of all * kinds of other junk, so we just replicate the structures here. * First the software bits: */ enum IWM_CMD_MODE { IWM_CMD_SYNC = 0, IWM_CMD_ASYNC = (1 << 0), IWM_CMD_WANT_SKB = (1 << 1), IWM_CMD_SEND_IN_RFKILL = (1 << 2), }; enum iwm_hcmd_dataflag { IWM_HCMD_DFL_NOCOPY = (1 << 0), IWM_HCMD_DFL_DUP = (1 << 1), }; /* * iwlwifi/iwl-phy-db */ #define IWM_NUM_PAPD_CH_GROUPS 4 #define IWM_NUM_TXP_CH_GROUPS 9 struct iwm_phy_db_entry { uint16_t size; uint8_t *data; }; struct iwm_phy_db { struct iwm_phy_db_entry cfg; struct iwm_phy_db_entry calib_nch; struct iwm_phy_db_entry calib_ch_group_papd[IWM_NUM_PAPD_CH_GROUPS]; struct iwm_phy_db_entry calib_ch_group_txp[IWM_NUM_TXP_CH_GROUPS]; }; struct iwm_int_sta { uint32_t sta_id; uint32_t tfd_queue_msk; }; struct iwm_mvm_phy_ctxt { uint16_t id; uint16_t color; uint32_t ref; struct ieee80211_channel *channel; }; struct iwm_bf_data { int bf_enabled; /* filtering */ int ba_enabled; /* abort */ int ave_beacon_signal; int last_cqm_event; }; struct iwm_vap { struct ieee80211vap iv_vap; uint8_t macaddr[IEEE80211_ADDR_LEN]; int is_uploaded; int (*iv_newstate)(struct ieee80211vap *, enum ieee80211_state, int); }; #define IWM_VAP(_vap) ((struct iwm_vap *)(_vap)) struct iwm_softc { struct mtx sc_mtx; struct mbufq sc_snd; struct ieee80211com sc_ic; device_t sc_dev; struct intr_config_hook sc_preinit_hook; struct callout sc_watchdog_to; struct task init_task; struct resource *sc_irq; struct resource *sc_mem; bus_space_tag_t sc_st; bus_space_handle_t sc_sh; bus_size_t sc_sz; bus_dma_tag_t sc_dmat; void *sc_ih; /* TX scheduler rings. */ struct iwm_dma_info sched_dma; uint32_t sched_base; /* TX/RX rings. */ struct iwm_tx_ring txq[IWM_MVM_MAX_QUEUES]; struct iwm_rx_ring rxq; int qfullmsk; int sc_sf_state; /* ICT table. */ struct iwm_dma_info ict_dma; int ict_cur; int sc_hw_rev; int sc_hw_id; struct iwm_dma_info kw_dma; struct iwm_dma_info fw_dma; int sc_fw_chunk_done; int sc_init_complete; struct iwm_ucode_status sc_uc; enum iwm_ucode_type sc_uc_current; int sc_fwver; int sc_capaflags; int sc_capa_max_probe_len; int sc_intmask; int sc_flags; uint32_t sc_debug; /* * So why do we need a separate stopped flag and a generation? * the former protects the device from issueing commands when it's * stopped (duh). The latter protects against race from a very * fast stop/unstop cycle where threads waiting for responses do * not have a chance to run in between. Notably: we want to stop * the device from interrupt context when it craps out, so we * don't have the luxury of waiting for quiescense. */ int sc_generation; const char *sc_fwname; bus_size_t sc_fwdmasegsz; struct iwm_fw_info sc_fw; int sc_fw_phy_config; struct iwm_tlv_calib_ctrl sc_default_calib[IWM_UCODE_TYPE_MAX]; struct iwm_nvm_data sc_nvm; struct iwm_phy_db sc_phy_db; struct iwm_bf_data sc_bf; int sc_tx_timer; struct iwm_scan_cmd *sc_scan_cmd; size_t sc_scan_cmd_len; int sc_scan_last_antenna; int sc_scanband; int sc_auth_prot; int sc_fixed_ridx; int sc_staid; int sc_nodecolor; uint8_t sc_cmd_resp[IWM_CMD_RESP_MAX]; int sc_wantresp; struct taskqueue *sc_tq; struct task sc_es_task; struct iwm_rx_phy_info sc_last_phy_info; int sc_ampdu_ref; struct iwm_int_sta sc_aux_sta; /* phy contexts. we only use the first one */ struct iwm_mvm_phy_ctxt sc_phyctxt[IWM_NUM_PHY_CTX]; struct iwm_notif_statistics sc_stats; int sc_noise; int host_interrupt_operation_mode; caddr_t sc_drvbpf; union { struct iwm_rx_radiotap_header th; uint8_t pad[IEEE80211_RADIOTAP_HDRLEN]; } sc_rxtapu; #define sc_rxtap sc_rxtapu.th - int sc_rxtap_len; union { struct iwm_tx_radiotap_header th; uint8_t pad[IEEE80211_RADIOTAP_HDRLEN]; } sc_txtapu; #define sc_txtap sc_txtapu.th - int sc_txtap_len; int sc_max_rssi; }; #define IWM_DEFAULT_MACID 0 #define IWM_DEFAULT_COLOR 0 #define IWM_DEFAULT_TSFID 0 struct iwm_node { struct ieee80211_node in_ni; struct iwm_mvm_phy_ctxt *in_phyctxt; /* status "bits" */ int in_assoc; struct iwm_lq_cmd in_lq; uint8_t in_ridx[IEEE80211_RATE_MAXSIZE]; }; #define IWM_STATION_ID 0 #define IWM_ICT_SIZE 4096 #define IWM_ICT_COUNT (IWM_ICT_SIZE / sizeof (uint32_t)) #define IWM_ICT_PADDR_SHIFT 12 Index: head/sys/dev/otus/if_otus.c =================================================================== --- head/sys/dev/otus/if_otus.c (revision 289167) +++ head/sys/dev/otus/if_otus.c (revision 289168) @@ -1,3155 +1,3154 @@ /* $OpenBSD: if_otus.c,v 1.46 2015/03/14 03:38:49 jsg Exp $ */ /*- * Copyright (c) 2009 Damien Bergamini * Copyright (c) 2015 Adrian Chadd * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ /* * Driver for Atheros AR9001U chipset. */ #include __FBSDID("$FreeBSD$"); #include "opt_wlan.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef IEEE80211_SUPPORT_SUPERG #include #endif #include #include #include "usbdevs.h" #define USB_DEBUG_VAR otus_debug #include #include "if_otusreg.h" static int otus_debug = 0; static SYSCTL_NODE(_hw_usb, OID_AUTO, otus, CTLFLAG_RW, 0, "USB otus"); SYSCTL_INT(_hw_usb_otus, OID_AUTO, debug, CTLFLAG_RWTUN, &otus_debug, 0, "Debug level"); #define OTUS_DEBUG_XMIT 0x00000001 #define OTUS_DEBUG_RECV 0x00000002 #define OTUS_DEBUG_TXDONE 0x00000004 #define OTUS_DEBUG_RXDONE 0x00000008 #define OTUS_DEBUG_CMD 0x00000010 #define OTUS_DEBUG_CMDDONE 0x00000020 #define OTUS_DEBUG_RESET 0x00000040 #define OTUS_DEBUG_STATE 0x00000080 #define OTUS_DEBUG_CMDNOTIFY 0x00000100 #define OTUS_DEBUG_REGIO 0x00000200 #define OTUS_DEBUG_IRQ 0x00000400 #define OTUS_DEBUG_TXCOMP 0x00000800 #define OTUS_DEBUG_ANY 0xffffffff #define OTUS_DPRINTF(sc, dm, ...) \ do { \ if ((dm == OTUS_DEBUG_ANY) || (dm & otus_debug)) \ device_printf(sc->sc_dev, __VA_ARGS__); \ } while (0) #define OTUS_DEV(v, p) { USB_VPI(v, p, 0) } static const STRUCT_USB_HOST_ID otus_devs[] = { OTUS_DEV(USB_VENDOR_ACCTON, USB_PRODUCT_ACCTON_WN7512), OTUS_DEV(USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_3CRUSBN275), OTUS_DEV(USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_TG121N), OTUS_DEV(USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_AR9170), OTUS_DEV(USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_WN612), OTUS_DEV(USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_WN821NV2), OTUS_DEV(USB_VENDOR_AVM, USB_PRODUCT_AVM_FRITZWLAN), OTUS_DEV(USB_VENDOR_CACE, USB_PRODUCT_CACE_AIRPCAPNX), OTUS_DEV(USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA130D1), OTUS_DEV(USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA160A1), OTUS_DEV(USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA160A2), OTUS_DEV(USB_VENDOR_IODATA, USB_PRODUCT_IODATA_WNGDNUS2), OTUS_DEV(USB_VENDOR_NEC, USB_PRODUCT_NEC_WL300NUG), OTUS_DEV(USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WN111V2), OTUS_DEV(USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNA1000), OTUS_DEV(USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNDA3100), OTUS_DEV(USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_GW_US300), OTUS_DEV(USB_VENDOR_WISTRONNEWEB, USB_PRODUCT_WISTRONNEWEB_O8494), OTUS_DEV(USB_VENDOR_WISTRONNEWEB, USB_PRODUCT_WISTRONNEWEB_WNC0600), OTUS_DEV(USB_VENDOR_ZCOM, USB_PRODUCT_ZCOM_UB81), OTUS_DEV(USB_VENDOR_ZCOM, USB_PRODUCT_ZCOM_UB82), OTUS_DEV(USB_VENDOR_ZYDAS, USB_PRODUCT_ZYDAS_ZD1221), OTUS_DEV(USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_NWD271N), }; static device_probe_t otus_match; static device_attach_t otus_attach; static device_detach_t otus_detach; static int otus_attachhook(struct otus_softc *); void otus_get_chanlist(struct otus_softc *); int otus_load_firmware(struct otus_softc *, const char *, uint32_t); int otus_open_pipes(struct otus_softc *); void otus_close_pipes(struct otus_softc *); static int otus_alloc_tx_cmd_list(struct otus_softc *); static void otus_free_tx_cmd_list(struct otus_softc *); static int otus_alloc_rx_list(struct otus_softc *); static void otus_free_rx_list(struct otus_softc *); static int otus_alloc_tx_list(struct otus_softc *); static void otus_free_tx_list(struct otus_softc *); static void otus_free_list(struct otus_softc *, struct otus_data [], int); static struct otus_data *_otus_getbuf(struct otus_softc *); static struct otus_data *otus_getbuf(struct otus_softc *); static void otus_freebuf(struct otus_softc *, struct otus_data *); static struct otus_tx_cmd *_otus_get_txcmd(struct otus_softc *); static struct otus_tx_cmd *otus_get_txcmd(struct otus_softc *); static void otus_free_txcmd(struct otus_softc *, struct otus_tx_cmd *); void otus_next_scan(void *, int); static void otus_tx_task(void *, int pending); static void otus_wme_update_task(void *, int pending); void otus_do_async(struct otus_softc *, void (*)(struct otus_softc *, void *), void *, int); int otus_newstate(struct ieee80211vap *, enum ieee80211_state, int); int otus_cmd(struct otus_softc *, uint8_t, const void *, int, void *, int); void otus_write(struct otus_softc *, uint32_t, uint32_t); int otus_write_barrier(struct otus_softc *); struct ieee80211_node *otus_node_alloc(struct ieee80211com *); int otus_media_change(struct ifnet *); int otus_read_eeprom(struct otus_softc *); void otus_newassoc(struct ieee80211_node *, int); void otus_cmd_rxeof(struct otus_softc *, uint8_t *, int); void otus_sub_rxeof(struct otus_softc *, uint8_t *, int, struct mbufq *); static int otus_tx(struct otus_softc *, struct ieee80211_node *, struct mbuf *, struct otus_data *); int otus_ioctl(struct ifnet *, u_long, caddr_t); int otus_set_multi(struct otus_softc *); static void otus_updateedca(struct otus_softc *sc); static void otus_updateslot(struct otus_softc *sc); int otus_init_mac(struct otus_softc *); uint32_t otus_phy_get_def(struct otus_softc *, uint32_t); int otus_set_board_values(struct otus_softc *, struct ieee80211_channel *); int otus_program_phy(struct otus_softc *, struct ieee80211_channel *); int otus_set_rf_bank4(struct otus_softc *, struct ieee80211_channel *); void otus_get_delta_slope(uint32_t, uint32_t *, uint32_t *); static int otus_set_chan(struct otus_softc *, struct ieee80211_channel *, int); int otus_set_key(struct ieee80211com *, struct ieee80211_node *, struct ieee80211_key *); void otus_set_key_cb(struct otus_softc *, void *); void otus_delete_key(struct ieee80211com *, struct ieee80211_node *, struct ieee80211_key *); void otus_delete_key_cb(struct otus_softc *, void *); void otus_calibrate_to(void *, int); int otus_set_bssid(struct otus_softc *, const uint8_t *); int otus_set_macaddr(struct otus_softc *, const uint8_t *); void otus_led_newstate_type1(struct otus_softc *); void otus_led_newstate_type2(struct otus_softc *); void otus_led_newstate_type3(struct otus_softc *); int otus_init(struct otus_softc *sc); void otus_stop(struct otus_softc *sc); static device_method_t otus_methods[] = { DEVMETHOD(device_probe, otus_match), DEVMETHOD(device_attach, otus_attach), DEVMETHOD(device_detach, otus_detach), DEVMETHOD_END }; static driver_t otus_driver = { .name = "otus", .methods = otus_methods, .size = sizeof(struct otus_softc) }; static devclass_t otus_devclass; DRIVER_MODULE(otus, uhub, otus_driver, otus_devclass, NULL, 0); MODULE_DEPEND(otus, wlan, 1, 1, 1); MODULE_DEPEND(otus, usb, 1, 1, 1); MODULE_DEPEND(otus, firmware, 1, 1, 1); MODULE_VERSION(otus, 1); static usb_callback_t otus_bulk_tx_callback; static usb_callback_t otus_bulk_rx_callback; static usb_callback_t otus_bulk_irq_callback; static usb_callback_t otus_bulk_cmd_callback; static const struct usb_config otus_config[OTUS_N_XFER] = { [OTUS_BULK_TX] = { .type = UE_BULK, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_OUT, .bufsize = 0x200, .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, .callback = otus_bulk_tx_callback, .timeout = 5000, /* ms */ }, [OTUS_BULK_RX] = { .type = UE_BULK, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_IN, .bufsize = OTUS_RXBUFSZ, .flags = { .ext_buffer = 1, .pipe_bof = 1,.short_xfer_ok = 1,}, .callback = otus_bulk_rx_callback, }, [OTUS_BULK_IRQ] = { .type = UE_INTERRUPT, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_IN, .bufsize = OTUS_MAX_CTRLSZ, .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, .callback = otus_bulk_irq_callback, }, [OTUS_BULK_CMD] = { .type = UE_INTERRUPT, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_OUT, .bufsize = OTUS_MAX_CTRLSZ, .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, .callback = otus_bulk_cmd_callback, .timeout = 5000, /* ms */ }, }; static int otus_match(device_t self) { struct usb_attach_arg *uaa = device_get_ivars(self); if (uaa->usb_mode != USB_MODE_HOST || uaa->info.bIfaceIndex != 0 || uaa->info.bConfigIndex != 0) return (ENXIO); return (usbd_lookup_id_by_uaa(otus_devs, sizeof(otus_devs), uaa)); } static int otus_attach(device_t self) { struct usb_attach_arg *uaa = device_get_ivars(self); struct otus_softc *sc = device_get_softc(self); int error; uint8_t iface_index; device_set_usb_desc(self); sc->sc_udev = uaa->device; sc->sc_dev = self; mtx_init(&sc->sc_mtx, device_get_nameunit(self), MTX_NETWORK_LOCK, MTX_DEF); TIMEOUT_TASK_INIT(taskqueue_thread, &sc->scan_to, 0, otus_next_scan, sc); TIMEOUT_TASK_INIT(taskqueue_thread, &sc->calib_to, 0, otus_calibrate_to, sc); TASK_INIT(&sc->tx_task, 0, otus_tx_task, sc); TASK_INIT(&sc->wme_update_task, 0, otus_wme_update_task, sc); mbufq_init(&sc->sc_snd, ifqmaxlen); iface_index = 0; error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, otus_config, OTUS_N_XFER, sc, &sc->sc_mtx); if (error) { device_printf(sc->sc_dev, "could not allocate USB transfers, err=%s\n", usbd_errstr(error)); goto fail_usb; } if ((error = otus_open_pipes(sc)) != 0) { device_printf(sc->sc_dev, "%s: could not open pipes\n", __func__); goto fail; } /* XXX check return status; fail out if appropriate */ if (otus_attachhook(sc) != 0) goto fail; return (0); fail: otus_close_pipes(sc); fail_usb: mtx_destroy(&sc->sc_mtx); return (ENXIO); } static int otus_detach(device_t self) { struct otus_softc *sc = device_get_softc(self); struct ieee80211com *ic = &sc->sc_ic; otus_stop(sc); usbd_transfer_unsetup(sc->sc_xfer, OTUS_N_XFER); taskqueue_drain_timeout(taskqueue_thread, &sc->scan_to); taskqueue_drain_timeout(taskqueue_thread, &sc->calib_to); taskqueue_drain(taskqueue_thread, &sc->tx_task); taskqueue_drain(taskqueue_thread, &sc->wme_update_task); otus_close_pipes(sc); #if 0 /* Wait for all queued asynchronous commands to complete. */ usb_rem_wait_task(sc->sc_udev, &sc->sc_task); usbd_ref_wait(sc->sc_udev); #endif ieee80211_ifdetach(ic); mtx_destroy(&sc->sc_mtx); return 0; } static void otus_delay_ms(struct otus_softc *sc, int ms) { DELAY(1000 * ms); } static struct ieee80211vap * otus_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, enum ieee80211_opmode opmode, int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], const uint8_t mac[IEEE80211_ADDR_LEN]) { struct otus_vap *uvp; struct ieee80211vap *vap; if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ return (NULL); uvp = malloc(sizeof(struct otus_vap), M_80211_VAP, M_WAITOK | M_ZERO); vap = &uvp->vap; if (ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid) != 0) { /* out of memory */ free(uvp, M_80211_VAP); return (NULL); } /* override state transition machine */ uvp->newstate = vap->iv_newstate; vap->iv_newstate = otus_newstate; /* XXX TODO: double-check */ vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_16; vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_32K; ieee80211_ratectl_init(vap); /* complete setup */ ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status, mac); ic->ic_opmode = opmode; return (vap); } static void otus_vap_delete(struct ieee80211vap *vap) { struct otus_vap *uvp = OTUS_VAP(vap); ieee80211_ratectl_deinit(vap); ieee80211_vap_detach(vap); free(uvp, M_80211_VAP); } static void otus_parent(struct ieee80211com *ic) { struct otus_softc *sc = ic->ic_softc; int startall = 0; if (ic->ic_nrunning > 0) { if (!sc->sc_running) { otus_init(sc); startall = 1; } else { (void) otus_set_multi(sc); } } else if (sc->sc_running) otus_stop(sc); if (startall) ieee80211_start_all(ic); } static void otus_drain_mbufq(struct otus_softc *sc) { struct mbuf *m; struct ieee80211_node *ni; OTUS_LOCK_ASSERT(sc); while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; m->m_pkthdr.rcvif = NULL; ieee80211_free_node(ni); m_freem(m); } } static void otus_tx_start(struct otus_softc *sc) { taskqueue_enqueue(taskqueue_thread, &sc->tx_task); } static int otus_transmit(struct ieee80211com *ic, struct mbuf *m) { struct otus_softc *sc = ic->ic_softc; int error; OTUS_LOCK(sc); if (! sc->sc_running) { OTUS_UNLOCK(sc); return (ENXIO); } /* XXX TODO: handle fragments */ error = mbufq_enqueue(&sc->sc_snd, m); if (error) { OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, "%s: mbufq_enqueue failed: %d\n", __func__, error); OTUS_UNLOCK(sc); return (error); } OTUS_UNLOCK(sc); /* Kick TX */ otus_tx_start(sc); return (0); } static void _otus_start(struct otus_softc *sc) { struct ieee80211_node *ni; struct otus_data *bf; struct mbuf *m; OTUS_LOCK_ASSERT(sc); while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { bf = otus_getbuf(sc); if (bf == NULL) { OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, "%s: failed to get buffer\n", __func__); mbufq_prepend(&sc->sc_snd, m); break; } ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; m->m_pkthdr.rcvif = NULL; if (otus_tx(sc, ni, m, bf) != 0) { OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, "%s: failed to transmit\n", __func__); if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1); otus_freebuf(sc, bf); ieee80211_free_node(ni); m_freem(m); break; } } } static void otus_tx_task(void *arg, int pending) { struct otus_softc *sc = arg; OTUS_LOCK(sc); _otus_start(sc); OTUS_UNLOCK(sc); } static int otus_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, const struct ieee80211_bpf_params *params) { struct ieee80211com *ic= ni->ni_ic; struct otus_softc *sc = ic->ic_softc; struct otus_data *bf = NULL; int error = 0; /* Don't transmit if we're not running */ OTUS_LOCK(sc); if (! sc->sc_running) { error = ENETDOWN; goto error; } bf = otus_getbuf(sc); if (bf == NULL) { error = ENOBUFS; goto error; } /* * XXX TODO: support TX bpf params */ if (otus_tx(sc, ni, m, bf) != 0) { error = EIO; goto error; } OTUS_UNLOCK(sc); return (0); error: if (bf) otus_freebuf(sc, bf); OTUS_UNLOCK(sc); m_freem(m); return (ENXIO); } static void otus_update_chw(struct ieee80211com *ic) { printf("%s: TODO\n", __func__); } static void otus_set_channel(struct ieee80211com *ic) { struct otus_softc *sc = ic->ic_softc; OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, "%s: set channel: %d\n", __func__, ic->ic_curchan->ic_freq); OTUS_LOCK(sc); (void) otus_set_chan(sc, ic->ic_curchan, 0); OTUS_UNLOCK(sc); } static void otus_wme_update_task(void *arg, int pending) { struct otus_softc *sc = arg; OTUS_LOCK(sc); /* * XXX TODO: take temporary copy of EDCA information * when scheduling this so we have a more time-correct view * of things. */ otus_updateedca(sc); OTUS_UNLOCK(sc); } static void otus_wme_schedule_update(struct otus_softc *sc) { taskqueue_enqueue(taskqueue_thread, &sc->wme_update_task); } /* * This is called by net80211 in RX packet context, so we * can't sleep here. * * TODO: have net80211 schedule an update itself for its * own internal taskqueue. */ static int otus_wme_update(struct ieee80211com *ic) { struct otus_softc *sc = ic->ic_softc; otus_wme_schedule_update(sc); return (0); } static int otus_ampdu_enable(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) { /* For now, no A-MPDU TX support in the driver */ return (0); } static void otus_scan_start(struct ieee80211com *ic) { // printf("%s: TODO\n", __func__); } static void otus_scan_end(struct ieee80211com *ic) { // printf("%s: TODO\n", __func__); } static void otus_update_mcast(struct ieee80211com *ic) { struct otus_softc *sc = ic->ic_softc; (void) otus_set_multi(sc); } static int otus_attachhook(struct otus_softc *sc) { struct ieee80211com *ic = &sc->sc_ic; usb_device_request_t req; uint32_t in, out; int error; uint8_t bands; /* Not locked */ error = otus_load_firmware(sc, "otusfw_init", AR_FW_INIT_ADDR); if (error != 0) { device_printf(sc->sc_dev, "%s: could not load %s firmware\n", __func__, "init"); return (ENXIO); } /* XXX not locked? */ otus_delay_ms(sc, 1000); /* Not locked */ error = otus_load_firmware(sc, "otusfw_main", AR_FW_MAIN_ADDR); if (error != 0) { device_printf(sc->sc_dev, "%s: could not load %s firmware\n", __func__, "main"); return (ENXIO); } OTUS_LOCK(sc); /* Tell device that firmware transfer is complete. */ req.bmRequestType = UT_WRITE_VENDOR_DEVICE; req.bRequest = AR_FW_DOWNLOAD_COMPLETE; USETW(req.wValue, 0); USETW(req.wIndex, 0); USETW(req.wLength, 0); if (usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, &req, NULL, 0, NULL, 250) != 0) { OTUS_UNLOCK(sc); device_printf(sc->sc_dev, "%s: firmware initialization failed\n", __func__); return (ENXIO); } /* Send an ECHO command to check that everything is settled. */ in = 0xbadc0ffe; if (otus_cmd(sc, AR_CMD_ECHO, &in, sizeof in, &out, sizeof(out)) != 0) { OTUS_UNLOCK(sc); device_printf(sc->sc_dev, "%s: echo command failed\n", __func__); return (ENXIO); } if (in != out) { OTUS_UNLOCK(sc); device_printf(sc->sc_dev, "%s: echo reply mismatch: 0x%08x!=0x%08x\n", __func__, in, out); return (ENXIO); } /* Read entire EEPROM. */ if (otus_read_eeprom(sc) != 0) { OTUS_UNLOCK(sc); device_printf(sc->sc_dev, "%s: could not read EEPROM\n", __func__); return (ENXIO); } OTUS_UNLOCK(sc); sc->txmask = sc->eeprom.baseEepHeader.txMask; sc->rxmask = sc->eeprom.baseEepHeader.rxMask; sc->capflags = sc->eeprom.baseEepHeader.opCapFlags; IEEE80211_ADDR_COPY(ic->ic_macaddr, sc->eeprom.baseEepHeader.macAddr); sc->sc_led_newstate = otus_led_newstate_type3; /* XXX */ device_printf(sc->sc_dev, "MAC/BBP AR9170, RF AR%X, MIMO %dT%dR, address %s\n", (sc->capflags & AR5416_OPFLAGS_11A) ? 0x9104 : ((sc->txmask == 0x5) ? 0x9102 : 0x9101), (sc->txmask == 0x5) ? 2 : 1, (sc->rxmask == 0x5) ? 2 : 1, ether_sprintf(ic->ic_macaddr)); ic->ic_softc = sc; ic->ic_name = device_get_nameunit(sc->sc_dev); ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ /* Set device capabilities. */ ic->ic_caps = IEEE80211_C_STA | /* station mode */ #if 0 IEEE80211_C_BGSCAN | /* Background scan. */ #endif IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ IEEE80211_C_WME | /* WME/QoS */ IEEE80211_C_SHSLOT | /* Short slot time supported. */ IEEE80211_C_FF | /* Atheros fast-frames supported. */ IEEE80211_C_WPA; /* WPA/RSN. */ /* XXX TODO: 11n */ #if 0 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11G) { /* Set supported .11b and .11g rates. */ ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; } if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11A) { /* Set supported .11a rates. */ ic->ic_sup_rates[IEEE80211_MODE_11A] = ieee80211_std_rateset_11a; } #endif #if 0 /* Build the list of supported channels. */ otus_get_chanlist(sc); #else /* Set supported .11b and .11g rates. */ bands = 0; if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11G) { setbit(&bands, IEEE80211_MODE_11B); setbit(&bands, IEEE80211_MODE_11G); } if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11A) { setbit(&bands, IEEE80211_MODE_11A); } #if 0 if (sc->sc_ht) setbit(&bands, IEEE80211_MODE_11NG); #endif ieee80211_init_channels(ic, NULL, &bands); #endif ieee80211_ifattach(ic); ic->ic_raw_xmit = otus_raw_xmit; ic->ic_scan_start = otus_scan_start; ic->ic_scan_end = otus_scan_end; ic->ic_set_channel = otus_set_channel; ic->ic_vap_create = otus_vap_create; ic->ic_vap_delete = otus_vap_delete; ic->ic_update_mcast = otus_update_mcast; ic->ic_update_promisc = otus_update_mcast; ic->ic_parent = otus_parent; ic->ic_transmit = otus_transmit; ic->ic_update_chw = otus_update_chw; ic->ic_ampdu_enable = otus_ampdu_enable; ic->ic_wme.wme_update = otus_wme_update; ic->ic_newassoc = otus_newassoc; #ifdef notyet ic->ic_set_key = otus_set_key; ic->ic_delete_key = otus_delete_key; #endif ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), OTUS_TX_RADIOTAP_PRESENT, &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), OTUS_RX_RADIOTAP_PRESENT); return (0); } void otus_get_chanlist(struct otus_softc *sc) { struct ieee80211com *ic = &sc->sc_ic; uint16_t domain; uint8_t chan; int i; /* XXX regulatory domain. */ domain = le16toh(sc->eeprom.baseEepHeader.regDmn[0]); OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, "regdomain=0x%04x\n", domain); if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11G) { for (i = 0; i < 14; i++) { chan = ar_chans[i]; ic->ic_channels[chan].ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; } } if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11A) { for (i = 14; i < nitems(ar_chans); i++) { chan = ar_chans[i]; ic->ic_channels[chan].ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; } } } int otus_load_firmware(struct otus_softc *sc, const char *name, uint32_t addr) { usb_device_request_t req; char *ptr; const struct firmware *fw; int mlen, error, size; error = 0; /* Read firmware image from the filesystem. */ if ((fw = firmware_get(name)) == NULL) { device_printf(sc->sc_dev, "%s: failed loadfirmware of file %s\n", __func__, name); return (ENXIO); } req.bmRequestType = UT_WRITE_VENDOR_DEVICE; req.bRequest = AR_FW_DOWNLOAD; USETW(req.wIndex, 0); OTUS_LOCK(sc); /* XXX const */ ptr = __DECONST(char *, fw->data); size = fw->datasize; addr >>= 8; while (size > 0) { mlen = MIN(size, 4096); USETW(req.wValue, addr); USETW(req.wLength, mlen); if (usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, &req, ptr, 0, NULL, 250) != 0) { error = EIO; break; } addr += mlen >> 8; ptr += mlen; size -= mlen; } OTUS_UNLOCK(sc); firmware_put(fw, FIRMWARE_UNLOAD); if (error != 0) device_printf(sc->sc_dev, "%s: %s: error=%d\n", __func__, name, error); return error; } int otus_open_pipes(struct otus_softc *sc) { #if 0 int isize, error; int i; #endif int error; OTUS_UNLOCK_ASSERT(sc); if ((error = otus_alloc_tx_cmd_list(sc)) != 0) { device_printf(sc->sc_dev, "%s: could not allocate command xfer\n", __func__); goto fail; } if ((error = otus_alloc_tx_list(sc)) != 0) { device_printf(sc->sc_dev, "%s: could not allocate Tx xfers\n", __func__); goto fail; } if ((error = otus_alloc_rx_list(sc)) != 0) { device_printf(sc->sc_dev, "%s: could not allocate Rx xfers\n", __func__); goto fail; } /* Enable RX transfers; needed for initial firmware messages */ OTUS_LOCK(sc); usbd_transfer_start(sc->sc_xfer[OTUS_BULK_RX]); usbd_transfer_start(sc->sc_xfer[OTUS_BULK_IRQ]); OTUS_UNLOCK(sc); return 0; fail: otus_close_pipes(sc); return error; } void otus_close_pipes(struct otus_softc *sc) { OTUS_LOCK(sc); otus_free_tx_cmd_list(sc); otus_free_tx_list(sc); otus_free_rx_list(sc); OTUS_UNLOCK(sc); usbd_transfer_unsetup(sc->sc_xfer, OTUS_N_XFER); } static void otus_free_cmd_list(struct otus_softc *sc, struct otus_tx_cmd cmd[], int ndata) { int i; /* XXX TODO: someone has to have waken up waiters! */ for (i = 0; i < ndata; i++) { struct otus_tx_cmd *dp = &cmd[i]; if (dp->buf != NULL) { free(dp->buf, M_USBDEV); dp->buf = NULL; } } } static int otus_alloc_cmd_list(struct otus_softc *sc, struct otus_tx_cmd cmd[], int ndata, int maxsz) { int i, error; for (i = 0; i < ndata; i++) { struct otus_tx_cmd *dp = &cmd[i]; dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); dp->odata = NULL; if (dp->buf == NULL) { device_printf(sc->sc_dev, "could not allocate buffer\n"); error = ENOMEM; goto fail; } } return (0); fail: otus_free_cmd_list(sc, cmd, ndata); return (error); } static int otus_alloc_tx_cmd_list(struct otus_softc *sc) { int error, i; error = otus_alloc_cmd_list(sc, sc->sc_cmd, OTUS_CMD_LIST_COUNT, OTUS_MAX_TXCMDSZ); if (error != 0) return (error); STAILQ_INIT(&sc->sc_cmd_active); STAILQ_INIT(&sc->sc_cmd_inactive); STAILQ_INIT(&sc->sc_cmd_pending); STAILQ_INIT(&sc->sc_cmd_waiting); for (i = 0; i < OTUS_CMD_LIST_COUNT; i++) STAILQ_INSERT_HEAD(&sc->sc_cmd_inactive, &sc->sc_cmd[i], next_cmd); return (0); } static void otus_free_tx_cmd_list(struct otus_softc *sc) { /* * XXX TODO: something needs to wake up any pending/sleeping * waiters! */ STAILQ_INIT(&sc->sc_cmd_active); STAILQ_INIT(&sc->sc_cmd_inactive); STAILQ_INIT(&sc->sc_cmd_pending); STAILQ_INIT(&sc->sc_cmd_waiting); otus_free_cmd_list(sc, sc->sc_cmd, OTUS_CMD_LIST_COUNT); } static int otus_alloc_list(struct otus_softc *sc, struct otus_data data[], int ndata, int maxsz) { int i, error; for (i = 0; i < ndata; i++) { struct otus_data *dp = &data[i]; dp->sc = sc; dp->m = NULL; dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); if (dp->buf == NULL) { device_printf(sc->sc_dev, "could not allocate buffer\n"); error = ENOMEM; goto fail; } dp->ni = NULL; } return (0); fail: otus_free_list(sc, data, ndata); return (error); } static int otus_alloc_rx_list(struct otus_softc *sc) { int error, i; error = otus_alloc_list(sc, sc->sc_rx, OTUS_RX_LIST_COUNT, OTUS_RXBUFSZ); if (error != 0) return (error); STAILQ_INIT(&sc->sc_rx_active); STAILQ_INIT(&sc->sc_rx_inactive); for (i = 0; i < OTUS_RX_LIST_COUNT; i++) STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); return (0); } static int otus_alloc_tx_list(struct otus_softc *sc) { int error, i; error = otus_alloc_list(sc, sc->sc_tx, OTUS_TX_LIST_COUNT, OTUS_TXBUFSZ); if (error != 0) return (error); STAILQ_INIT(&sc->sc_tx_inactive); for (i = 0; i != OTUS_N_XFER; i++) { STAILQ_INIT(&sc->sc_tx_active[i]); STAILQ_INIT(&sc->sc_tx_pending[i]); } for (i = 0; i < OTUS_TX_LIST_COUNT; i++) { STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); } return (0); } static void otus_free_tx_list(struct otus_softc *sc) { int i; /* prevent further allocations from TX list(s) */ STAILQ_INIT(&sc->sc_tx_inactive); for (i = 0; i != OTUS_N_XFER; i++) { STAILQ_INIT(&sc->sc_tx_active[i]); STAILQ_INIT(&sc->sc_tx_pending[i]); } otus_free_list(sc, sc->sc_tx, OTUS_TX_LIST_COUNT); } static void otus_free_rx_list(struct otus_softc *sc) { /* prevent further allocations from RX list(s) */ STAILQ_INIT(&sc->sc_rx_inactive); STAILQ_INIT(&sc->sc_rx_active); otus_free_list(sc, sc->sc_rx, OTUS_RX_LIST_COUNT); } static void otus_free_list(struct otus_softc *sc, struct otus_data data[], int ndata) { int i; for (i = 0; i < ndata; i++) { struct otus_data *dp = &data[i]; if (dp->buf != NULL) { free(dp->buf, M_USBDEV); dp->buf = NULL; } if (dp->ni != NULL) { ieee80211_free_node(dp->ni); dp->ni = NULL; } } } static struct otus_data * _otus_getbuf(struct otus_softc *sc) { struct otus_data *bf; bf = STAILQ_FIRST(&sc->sc_tx_inactive); if (bf != NULL) STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); else bf = NULL; return (bf); } static struct otus_data * otus_getbuf(struct otus_softc *sc) { struct otus_data *bf; OTUS_LOCK_ASSERT(sc); bf = _otus_getbuf(sc); return (bf); } static void otus_freebuf(struct otus_softc *sc, struct otus_data *bf) { OTUS_LOCK_ASSERT(sc); STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, bf, next); } static struct otus_tx_cmd * _otus_get_txcmd(struct otus_softc *sc) { struct otus_tx_cmd *bf; bf = STAILQ_FIRST(&sc->sc_cmd_inactive); if (bf != NULL) STAILQ_REMOVE_HEAD(&sc->sc_cmd_inactive, next_cmd); else bf = NULL; return (bf); } static struct otus_tx_cmd * otus_get_txcmd(struct otus_softc *sc) { struct otus_tx_cmd *bf; OTUS_LOCK_ASSERT(sc); bf = _otus_get_txcmd(sc); if (bf == NULL) { device_printf(sc->sc_dev, "%s: no tx cmd buffers\n", __func__); } return (bf); } static void otus_free_txcmd(struct otus_softc *sc, struct otus_tx_cmd *bf) { OTUS_LOCK_ASSERT(sc); STAILQ_INSERT_TAIL(&sc->sc_cmd_inactive, bf, next_cmd); } void otus_next_scan(void *arg, int pending) { #if 0 struct otus_softc *sc = arg; if (usbd_is_dying(sc->sc_udev)) return; usbd_ref_incr(sc->sc_udev); if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) ieee80211_next_scan(&sc->sc_ic.ic_if); usbd_ref_decr(sc->sc_udev); #endif } int otus_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) { struct otus_vap *uvp = OTUS_VAP(vap); struct ieee80211com *ic = vap->iv_ic; struct otus_softc *sc = ic->ic_softc; struct ieee80211_node *ni; enum ieee80211_state ostate; ostate = vap->iv_state; OTUS_DPRINTF(sc, OTUS_DEBUG_STATE, "%s: %s -> %s\n", __func__, ieee80211_state_name[ostate], ieee80211_state_name[nstate]); IEEE80211_UNLOCK(ic); OTUS_LOCK(sc); /* XXX TODO: more fleshing out! */ switch (nstate) { case IEEE80211_S_RUN: ni = ieee80211_ref_node(vap->iv_bss); if (ic->ic_opmode == IEEE80211_M_STA) { otus_updateslot(sc); otus_set_bssid(sc, ni->ni_bssid); /* Start calibration timer. */ taskqueue_enqueue_timeout(taskqueue_thread, &sc->calib_to, hz); } break; default: break; } /* XXX TODO: calibration? */ sc->sc_led_newstate(sc); OTUS_UNLOCK(sc); IEEE80211_LOCK(ic); return (uvp->newstate(vap, nstate, arg)); } int otus_cmd(struct otus_softc *sc, uint8_t code, const void *idata, int ilen, void *odata, int odatalen) { struct otus_tx_cmd *cmd; struct ar_cmd_hdr *hdr; int xferlen, error; OTUS_LOCK_ASSERT(sc); /* Always bulk-out a multiple of 4 bytes. */ xferlen = (sizeof (*hdr) + ilen + 3) & ~3; if (xferlen > OTUS_MAX_TXCMDSZ) { device_printf(sc->sc_dev, "%s: command (0x%02x) size (%d) > %d\n", __func__, code, xferlen, OTUS_MAX_TXCMDSZ); return (EIO); } cmd = otus_get_txcmd(sc); if (cmd == NULL) { device_printf(sc->sc_dev, "%s: failed to get buf\n", __func__); return (EIO); } hdr = (struct ar_cmd_hdr *)cmd->buf; hdr->code = code; hdr->len = ilen; hdr->token = ++sc->token; /* Don't care about endianness. */ cmd->token = hdr->token; /* XXX TODO: check max cmd length? */ memcpy((uint8_t *)&hdr[1], idata, ilen); OTUS_DPRINTF(sc, OTUS_DEBUG_CMD, "%s: sending command code=0x%02x len=%d token=%d\n", __func__, code, ilen, hdr->token); cmd->odata = odata; cmd->odatalen = odatalen; cmd->buflen = xferlen; /* Queue the command to the endpoint */ STAILQ_INSERT_TAIL(&sc->sc_cmd_pending, cmd, next_cmd); usbd_transfer_start(sc->sc_xfer[OTUS_BULK_CMD]); /* Sleep on the command; wait for it to complete */ error = msleep(cmd, &sc->sc_mtx, PCATCH, "otuscmd", hz); /* * At this point we don't own cmd any longer; it'll be * freed by the cmd bulk path or the RX notification * path. If the data is made available then it'll be copied * to the caller. All that is left to do is communicate * status back to the caller. */ if (error != 0) { device_printf(sc->sc_dev, "%s: timeout waiting for command 0x%02x reply\n", __func__, code); } return error; } void otus_write(struct otus_softc *sc, uint32_t reg, uint32_t val) { OTUS_LOCK_ASSERT(sc); sc->write_buf[sc->write_idx].reg = htole32(reg); sc->write_buf[sc->write_idx].val = htole32(val); if (++sc->write_idx > (AR_MAX_WRITE_IDX-1)) (void)otus_write_barrier(sc); } int otus_write_barrier(struct otus_softc *sc) { int error; OTUS_LOCK_ASSERT(sc); if (sc->write_idx == 0) return 0; /* Nothing to flush. */ OTUS_DPRINTF(sc, OTUS_DEBUG_REGIO, "%s: called; %d updates\n", __func__, sc->write_idx); error = otus_cmd(sc, AR_CMD_WREG, sc->write_buf, sizeof (sc->write_buf[0]) * sc->write_idx, NULL, 0); sc->write_idx = 0; return error; } struct ieee80211_node * otus_node_alloc(struct ieee80211com *ic) { return malloc(sizeof (struct otus_node), M_DEVBUF, M_NOWAIT | M_ZERO); } #if 0 int otus_media_change(struct ifnet *ifp) { struct otus_softc *sc = ifp->if_softc; struct ieee80211com *ic = &sc->sc_ic; uint8_t rate, ridx; int error; error = ieee80211_media_change(ifp); if (error != ENETRESET) return error; if (ic->ic_fixed_rate != -1) { rate = ic->ic_sup_rates[ic->ic_curmode]. rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; for (ridx = 0; ridx <= OTUS_RIDX_MAX; ridx++) if (otus_rates[ridx].rate == rate) break; sc->fixed_ridx = ridx; } if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) error = otus_init(sc); return error; } #endif int otus_read_eeprom(struct otus_softc *sc) { uint32_t regs[8], reg; uint8_t *eep; int i, j, error; OTUS_LOCK_ASSERT(sc); /* Read EEPROM by blocks of 32 bytes. */ eep = (uint8_t *)&sc->eeprom; reg = AR_EEPROM_OFFSET; for (i = 0; i < sizeof (sc->eeprom) / 32; i++) { for (j = 0; j < 8; j++, reg += 4) regs[j] = htole32(reg); error = otus_cmd(sc, AR_CMD_RREG, regs, sizeof regs, eep, 32); if (error != 0) break; eep += 32; } return error; } void otus_newassoc(struct ieee80211_node *ni, int isnew) { struct ieee80211com *ic = ni->ni_ic; struct otus_softc *sc = ic->ic_softc; struct otus_node *on = OTUS_NODE(ni); OTUS_DPRINTF(sc, OTUS_DEBUG_STATE, "new assoc isnew=%d addr=%s\n", isnew, ether_sprintf(ni->ni_macaddr)); on->tx_done = 0; on->tx_err = 0; on->tx_retries = 0; } static void otus_cmd_handle_response(struct otus_softc *sc, struct ar_cmd_hdr *hdr) { struct otus_tx_cmd *cmd; OTUS_LOCK_ASSERT(sc); OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, "%s: received reply code=0x%02x len=%d token=%d\n", __func__, hdr->code, hdr->len, hdr->token); /* * Walk the list, freeing items that aren't ours, * stopping when we hit our token. */ while ((cmd = STAILQ_FIRST(&sc->sc_cmd_waiting)) != NULL) { STAILQ_REMOVE_HEAD(&sc->sc_cmd_waiting, next_cmd); OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, "%s: cmd=%p; hdr.token=%d, cmd.token=%d\n", __func__, cmd, (int) hdr->token, (int) cmd->token); if (hdr->token == cmd->token) { /* Copy answer into caller's supplied buffer. */ if (cmd->odata != NULL) { if (hdr->len != cmd->odatalen) { device_printf(sc->sc_dev, "%s: code 0x%02x, len=%d, olen=%d\n", __func__, (int) hdr->code, (int) hdr->len, (int) cmd->odatalen); } memcpy(cmd->odata, &hdr[1], MIN(cmd->odatalen, hdr->len)); } wakeup(cmd); } STAILQ_INSERT_TAIL(&sc->sc_cmd_inactive, cmd, next_cmd); } } void otus_cmd_rxeof(struct otus_softc *sc, uint8_t *buf, int len) { struct ieee80211com *ic = &sc->sc_ic; struct ar_cmd_hdr *hdr; OTUS_LOCK_ASSERT(sc); if (__predict_false(len < sizeof (*hdr))) { OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, "cmd too small %d\n", len); return; } hdr = (struct ar_cmd_hdr *)buf; if (__predict_false(sizeof (*hdr) + hdr->len > len || sizeof (*hdr) + hdr->len > 64)) { OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, "cmd too large %d\n", hdr->len); return; } OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, "%s: code=%.02x\n", __func__, hdr->code); /* * This has to reach into the cmd queue "waiting for * an RX response" list, grab the head entry and check * if we need to wake anyone up. */ if ((hdr->code & 0xc0) != 0xc0) { otus_cmd_handle_response(sc, hdr); return; } /* Received unsolicited notification. */ switch (hdr->code & 0x3f) { case AR_EVT_BEACON: break; case AR_EVT_TX_COMP: { struct ar_evt_tx_comp *tx = (struct ar_evt_tx_comp *)&hdr[1]; struct ieee80211_node *ni; ni = ieee80211_find_node(&ic->ic_sta, tx->macaddr); if (ni == NULL) { device_printf(sc->sc_dev, "%s: txcomp on unknown node (%s)\n", __func__, ether_sprintf(tx->macaddr)); break; } OTUS_DPRINTF(sc, OTUS_DEBUG_TXCOMP, "tx completed %s status=%d phy=0x%x\n", ether_sprintf(tx->macaddr), le16toh(tx->status), le32toh(tx->phy)); switch (le16toh(tx->status)) { case AR_TX_STATUS_COMP: #if 0 ackfailcnt = 0; ieee80211_ratectl_tx_complete(ni->ni_vap, ni, IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); #endif /* * We don't get the above; only error notifications. * Sigh. So, don't worry about this. */ break; case AR_TX_STATUS_RETRY_COMP: OTUS_NODE(ni)->tx_retries++; break; case AR_TX_STATUS_FAILED: OTUS_NODE(ni)->tx_err++; break; } ieee80211_free_node(ni); break; } case AR_EVT_TBTT: break; case AR_EVT_DO_BB_RESET: /* * This is "tell driver to reset baseband" from ar9170-fw. * * I'm not sure what we should do here, so I'm going to * fall through; it gets generated when RTSRetryCnt internally * reaches '5' - I guess the firmware authors thought that * meant that the BB may have gone deaf or something. */ default: device_printf(sc->sc_dev, "%s: received notification code=0x%02x len=%d\n", __func__, hdr->code, hdr->len); } } void otus_sub_rxeof(struct otus_softc *sc, uint8_t *buf, int len, struct mbufq *rxq) { struct ieee80211com *ic = &sc->sc_ic; struct ieee80211_rx_stats rxs; #if 0 struct ieee80211_node *ni; #endif struct ar_rx_tail *tail; struct ieee80211_frame *wh; struct mbuf *m; uint8_t *plcp; // int s; int mlen; if (__predict_false(len < AR_PLCP_HDR_LEN)) { OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, "sub-xfer too short %d\n", len); return; } plcp = buf; /* All bits in the PLCP header are set to 1 for non-MPDU. */ if (memcmp(plcp, AR_PLCP_HDR_INTR, AR_PLCP_HDR_LEN) == 0) { otus_cmd_rxeof(sc, plcp + AR_PLCP_HDR_LEN, len - AR_PLCP_HDR_LEN); return; } /* Received MPDU. */ if (__predict_false(len < AR_PLCP_HDR_LEN + sizeof (*tail))) { OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, "MPDU too short %d\n", len); counter_u64_add(ic->ic_ierrors, 1); return; } tail = (struct ar_rx_tail *)(plcp + len - sizeof (*tail)); /* Discard error frames. */ if (__predict_false(tail->error != 0)) { OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, "error frame 0x%02x\n", tail->error); if (tail->error & AR_RX_ERROR_FCS) { OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, "bad FCS\n"); } else if (tail->error & AR_RX_ERROR_MMIC) { /* Report Michael MIC failures to net80211. */ #if 0 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyidx); #endif device_printf(sc->sc_dev, "%s: MIC failure\n", __func__); } counter_u64_add(ic->ic_ierrors, 1); return; } /* Compute MPDU's length. */ mlen = len - AR_PLCP_HDR_LEN - sizeof (*tail); /* Make sure there's room for an 802.11 header + FCS. */ if (__predict_false(mlen < IEEE80211_MIN_LEN)) { counter_u64_add(ic->ic_ierrors, 1); return; } mlen -= IEEE80211_CRC_LEN; /* strip 802.11 FCS */ wh = (struct ieee80211_frame *)(plcp + AR_PLCP_HDR_LEN); m = m_get2(mlen, M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) { device_printf(sc->sc_dev, "%s: failed m_get2()\n", __func__); counter_u64_add(ic->ic_ierrors, 1); } /* Finalize mbuf. */ memcpy(mtod(m, uint8_t *), wh, mlen); m->m_pkthdr.len = m->m_len = mlen; #if 0 if (__predict_false(sc->sc_drvbpf != NULL)) { struct otus_rx_radiotap_header *tap = &sc->sc_rxtap; struct mbuf mb; tap->wr_flags = 0; tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); tap->wr_antsignal = tail->rssi; tap->wr_rate = 2; /* In case it can't be found below. */ switch (tail->status & AR_RX_STATUS_MT_MASK) { case AR_RX_STATUS_MT_CCK: switch (plcp[0]) { case 10: tap->wr_rate = 2; break; case 20: tap->wr_rate = 4; break; case 55: tap->wr_rate = 11; break; case 110: tap->wr_rate = 22; break; } if (tail->status & AR_RX_STATUS_SHPREAMBLE) tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; break; case AR_RX_STATUS_MT_OFDM: switch (plcp[0] & 0xf) { case 0xb: tap->wr_rate = 12; break; case 0xf: tap->wr_rate = 18; break; case 0xa: tap->wr_rate = 24; break; case 0xe: tap->wr_rate = 36; break; case 0x9: tap->wr_rate = 48; break; case 0xd: tap->wr_rate = 72; break; case 0x8: tap->wr_rate = 96; break; case 0xc: tap->wr_rate = 108; break; } break; } mb.m_data = (caddr_t)tap; - mb.m_len = sc->sc_rxtap_len; mb.m_next = m; mb.m_nextpkt = NULL; mb.m_type = 0; mb.m_flags = 0; bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); } #endif /* Add RSSI/NF to this mbuf */ bzero(&rxs, sizeof(rxs)); rxs.r_flags = IEEE80211_R_NF | IEEE80211_R_RSSI; rxs.nf = sc->sc_nf[0]; /* XXX chain 0 != combined rssi/nf */ rxs.rssi = tail->rssi; /* XXX TODO: add MIMO RSSI/NF as well */ ieee80211_add_rx_params(m, &rxs); /* XXX make a method */ STAILQ_INSERT_TAIL(&rxq->mq_head, m, m_stailqpkt); #if 0 OTUS_UNLOCK(sc); ni = ieee80211_find_rxnode(ic, wh); rxi.rxi_flags = 0; rxi.rxi_rssi = tail->rssi; rxi.rxi_tstamp = 0; /* unused */ ieee80211_input(ifp, m, ni, &rxi); /* Node is no longer needed. */ ieee80211_release_node(ic, ni); OTUS_LOCK(sc); #endif } static void otus_rxeof(struct usb_xfer *xfer, struct otus_data *data, struct mbufq *rxq) { struct otus_softc *sc = usbd_xfer_softc(xfer); caddr_t buf = data->buf; struct ar_rx_head *head; uint16_t hlen; int len; usbd_xfer_status(xfer, &len, NULL, NULL, NULL); while (len >= sizeof (*head)) { head = (struct ar_rx_head *)buf; if (__predict_false(head->tag != htole16(AR_RX_HEAD_TAG))) { OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, "tag not valid 0x%x\n", le16toh(head->tag)); break; } hlen = le16toh(head->len); if (__predict_false(sizeof (*head) + hlen > len)) { OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, "xfer too short %d/%d\n", len, hlen); break; } /* Process sub-xfer. */ otus_sub_rxeof(sc, (uint8_t *)&head[1], hlen, rxq); /* Next sub-xfer is aligned on a 32-bit boundary. */ hlen = (sizeof (*head) + hlen + 3) & ~3; buf += hlen; len -= hlen; } } static void otus_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) { struct otus_softc *sc = usbd_xfer_softc(xfer); struct ieee80211com *ic = &sc->sc_ic; struct ieee80211_frame *wh; struct ieee80211_node *ni; struct mbuf *m; struct mbufq scrx; struct otus_data *data; OTUS_LOCK_ASSERT(sc); mbufq_init(&scrx, 1024); #if 0 device_printf(sc->sc_dev, "%s: called; state=%d; error=%d\n", __func__, USB_GET_STATE(xfer), error); #endif switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: data = STAILQ_FIRST(&sc->sc_rx_active); if (data == NULL) goto tr_setup; STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); otus_rxeof(xfer, data, &scrx); STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: /* * XXX TODO: what if sc_rx isn't empty, but data * is empty? Then we leak mbufs. */ data = STAILQ_FIRST(&sc->sc_rx_inactive); if (data == NULL) { //KASSERT(m == NULL, ("mbuf isn't NULL")); return; } STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); usbd_xfer_set_frame_data(xfer, 0, data->buf, usbd_xfer_max_len(xfer)); usbd_transfer_submit(xfer); /* * To avoid LOR we should unlock our private mutex here to call * ieee80211_input() because here is at the end of a USB * callback and safe to unlock. */ OTUS_UNLOCK(sc); while ((m = mbufq_dequeue(&scrx)) != NULL) { wh = mtod(m, struct ieee80211_frame *); ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); if (ni != NULL) { if (ni->ni_flags & IEEE80211_NODE_HT) m->m_flags |= M_AMPDU; (void)ieee80211_input_mimo(ni, m, NULL); ieee80211_free_node(ni); } else (void)ieee80211_input_mimo_all(ic, m, NULL); } #ifdef IEEE80211_SUPPORT_SUPERG ieee80211_ff_age_all(ic, 100); #endif OTUS_LOCK(sc); break; default: /* needs it to the inactive queue due to a error. */ data = STAILQ_FIRST(&sc->sc_rx_active); if (data != NULL) { STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); } if (error != USB_ERR_CANCELLED) { usbd_xfer_set_stall(xfer); counter_u64_add(ic->ic_ierrors, 1); goto tr_setup; } break; } } static void otus_txeof(struct usb_xfer *xfer, struct otus_data *data) { struct otus_softc *sc = usbd_xfer_softc(xfer); OTUS_DPRINTF(sc, OTUS_DEBUG_TXDONE, "%s: called; data=%p\n", __func__, data); OTUS_LOCK_ASSERT(sc); if (sc->sc_tx_n_active == 0) { device_printf(sc->sc_dev, "%s: completed but tx_active=0\n", __func__); } else { sc->sc_tx_n_active--; } if (data->m) { /* XXX status? */ /* XXX we get TX status via the RX path.. */ ieee80211_tx_complete(data->ni, data->m, 0); data->m = NULL; data->ni = NULL; } } static void otus_txcmdeof(struct usb_xfer *xfer, struct otus_tx_cmd *cmd) { struct otus_softc *sc = usbd_xfer_softc(xfer); OTUS_LOCK_ASSERT(sc); OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, "%s: called; data=%p; odata=%p\n", __func__, cmd, cmd->odata); /* * Non-response commands still need wakeup so the caller * knows it was submitted and completed OK; response commands should * wait until they're ACKed by the firmware with a response. */ if (cmd->odata) { STAILQ_INSERT_TAIL(&sc->sc_cmd_waiting, cmd, next_cmd); } else { wakeup(cmd); otus_free_txcmd(sc, cmd); } } static void otus_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) { uint8_t which = OTUS_BULK_TX; struct otus_softc *sc = usbd_xfer_softc(xfer); struct ieee80211com *ic = &sc->sc_ic; struct otus_data *data; OTUS_LOCK_ASSERT(sc); switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: data = STAILQ_FIRST(&sc->sc_tx_active[which]); if (data == NULL) goto tr_setup; OTUS_DPRINTF(sc, OTUS_DEBUG_TXDONE, "%s: transfer done %p\n", __func__, data); STAILQ_REMOVE_HEAD(&sc->sc_tx_active[which], next); otus_txeof(xfer, data); otus_freebuf(sc, data); /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: data = STAILQ_FIRST(&sc->sc_tx_pending[which]); if (data == NULL) { OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, "%s: empty pending queue sc %p\n", __func__, sc); sc->sc_tx_n_active = 0; goto finish; } STAILQ_REMOVE_HEAD(&sc->sc_tx_pending[which], next); STAILQ_INSERT_TAIL(&sc->sc_tx_active[which], data, next); usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, "%s: submitting transfer %p\n", __func__, data); usbd_transfer_submit(xfer); sc->sc_tx_n_active++; break; default: data = STAILQ_FIRST(&sc->sc_tx_active[which]); if (data != NULL) { STAILQ_REMOVE_HEAD(&sc->sc_tx_active[which], next); otus_txeof(xfer, data); otus_freebuf(sc, data); } counter_u64_add(ic->ic_oerrors, 1); if (error != USB_ERR_CANCELLED) { usbd_xfer_set_stall(xfer); goto tr_setup; } break; } finish: #ifdef IEEE80211_SUPPORT_SUPERG /* * If the TX active queue drops below a certain * threshold, ensure we age fast-frames out so they're * transmitted. */ if (sc->sc_tx_n_active < 2) { /* XXX ew - net80211 should defer this for us! */ OTUS_UNLOCK(sc); ieee80211_ff_flush(ic, WME_AC_VO); ieee80211_ff_flush(ic, WME_AC_VI); ieee80211_ff_flush(ic, WME_AC_BE); ieee80211_ff_flush(ic, WME_AC_BK); OTUS_LOCK(sc); } #endif /* Kick TX */ otus_tx_start(sc); } static void otus_bulk_cmd_callback(struct usb_xfer *xfer, usb_error_t error) { struct otus_softc *sc = usbd_xfer_softc(xfer); #if 0 struct ieee80211com *ic = &sc->sc_ic; #endif struct otus_tx_cmd *cmd; OTUS_LOCK_ASSERT(sc); switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: cmd = STAILQ_FIRST(&sc->sc_cmd_active); if (cmd == NULL) goto tr_setup; OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, "%s: transfer done %p\n", __func__, cmd); STAILQ_REMOVE_HEAD(&sc->sc_cmd_active, next_cmd); otus_txcmdeof(xfer, cmd); /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: cmd = STAILQ_FIRST(&sc->sc_cmd_pending); if (cmd == NULL) { OTUS_DPRINTF(sc, OTUS_DEBUG_CMD, "%s: empty pending queue sc %p\n", __func__, sc); return; } STAILQ_REMOVE_HEAD(&sc->sc_cmd_pending, next_cmd); STAILQ_INSERT_TAIL(&sc->sc_cmd_active, cmd, next_cmd); usbd_xfer_set_frame_data(xfer, 0, cmd->buf, cmd->buflen); OTUS_DPRINTF(sc, OTUS_DEBUG_CMD, "%s: submitting transfer %p; buf=%p, buflen=%d\n", __func__, cmd, cmd->buf, cmd->buflen); usbd_transfer_submit(xfer); break; default: cmd = STAILQ_FIRST(&sc->sc_cmd_active); if (cmd != NULL) { STAILQ_REMOVE_HEAD(&sc->sc_cmd_active, next_cmd); otus_txcmdeof(xfer, cmd); } if (error != USB_ERR_CANCELLED) { usbd_xfer_set_stall(xfer); goto tr_setup; } break; } } /* * This isn't used by carl9170; it however may be used by the * initial bootloader. */ static void otus_bulk_irq_callback(struct usb_xfer *xfer, usb_error_t error) { struct otus_softc *sc = usbd_xfer_softc(xfer); int actlen; int sumlen; usbd_xfer_status(xfer, &actlen, &sumlen, NULL, NULL); OTUS_DPRINTF(sc, OTUS_DEBUG_IRQ, "%s: called; state=%d\n", __func__, USB_GET_STATE(xfer)); switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: /* * Read usb frame data, if any. * "actlen" has the total length for all frames * transferred. */ OTUS_DPRINTF(sc, OTUS_DEBUG_IRQ, "%s: comp; %d bytes\n", __func__, actlen); #if 0 pc = usbd_xfer_get_frame(xfer, 0); otus_dump_usb_rx_page(sc, pc, actlen); #endif /* XXX fallthrough */ case USB_ST_SETUP: /* * Setup xfer frame lengths/count and data */ OTUS_DPRINTF(sc, OTUS_DEBUG_IRQ, "%s: setup\n", __func__); usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); usbd_transfer_submit(xfer); break; default: /* Error */ /* * Print error message and clear stall * for example. */ OTUS_DPRINTF(sc, OTUS_DEBUG_IRQ, "%s: ERROR?\n", __func__); break; } } /* * Map net80211 rate to hw rate for otus MAC/PHY. */ static uint8_t otus_rate_to_hw_rate(struct otus_softc *sc, uint8_t rate) { int is_2ghz; is_2ghz = !! (IEEE80211_IS_CHAN_2GHZ(sc->sc_ic.ic_curchan)); switch (rate) { /* CCK */ case 2: return (0x0); case 4: return (0x1); case 11: return (0x2); case 22: return (0x3); /* OFDM */ case 12: return (0xb); case 18: return (0xf); case 24: return (0xa); case 36: return (0xe); case 48: return (0x9); case 72: return (0xd); case 96: return (0x8); case 108: return (0xc); default: device_printf(sc->sc_dev, "%s: unknown rate '%d'\n", __func__, (int) rate); case 0: if (is_2ghz) return (0x0); /* 1MB CCK */ else return (0xb); /* 6MB OFDM */ /* XXX TODO: HT */ } } static int otus_hw_rate_is_ofdm(struct otus_softc *sc, uint8_t hw_rate) { switch (hw_rate) { case 0x0: case 0x1: case 0x2: case 0x3: return (0); default: return (1); } } static void otus_tx_update_ratectl(struct otus_softc *sc, struct ieee80211_node *ni) { int tx, tx_success, tx_retry; tx = OTUS_NODE(ni)->tx_done; tx_success = OTUS_NODE(ni)->tx_done - OTUS_NODE(ni)->tx_err; tx_retry = OTUS_NODE(ni)->tx_retries; ieee80211_ratectl_tx_update(ni->ni_vap, ni, &tx, &tx_success, &tx_retry); } /* * XXX TODO: support tx bpf parameters for configuration! */ static int otus_tx(struct otus_softc *sc, struct ieee80211_node *ni, struct mbuf *m, struct otus_data *data) { struct ieee80211com *ic = &sc->sc_ic; struct ieee80211vap *vap = ni->ni_vap; struct ieee80211_frame *wh; struct ieee80211_key *k; struct ar_tx_head *head; uint32_t phyctl; uint16_t macctl, qos; uint8_t qid, rate; int hasqos, xferlen; wh = mtod(m, struct ieee80211_frame *); if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { k = ieee80211_crypto_encap(ni, m); if (k == NULL) { device_printf(sc->sc_dev, "%s: m=%p: ieee80211_crypto_encap returns NULL\n", __func__, m); return (ENOBUFS); } wh = mtod(m, struct ieee80211_frame *); } /* Calculate transfer length; ensure data buffer is large enough */ xferlen = sizeof (*head) + m->m_pkthdr.len; if (xferlen > OTUS_TXBUFSZ) { device_printf(sc->sc_dev, "%s: 802.11 TX frame is %d bytes, max %d bytes\n", __func__, xferlen, OTUS_TXBUFSZ); return (ENOBUFS); } hasqos = !! IEEE80211_QOS_HAS_SEQ(wh); if (hasqos) { uint8_t tid; qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; tid = qos & IEEE80211_QOS_TID; qid = TID_TO_WME_AC(tid); } else { qos = 0; qid = WME_AC_BE; } /* Pickup a rate index. */ if (IEEE80211_IS_MULTICAST(wh->i_addr1) || (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_DATA) { /* Get lowest rate */ rate = otus_rate_to_hw_rate(sc, 0); } else { (void) ieee80211_ratectl_rate(ni, NULL, 0); rate = otus_rate_to_hw_rate(sc, ni->ni_txrate); } phyctl = 0; macctl = AR_TX_MAC_BACKOFF | AR_TX_MAC_HW_DUR | AR_TX_MAC_QID(qid); if (IEEE80211_IS_MULTICAST(wh->i_addr1) || (hasqos && ((qos & IEEE80211_QOS_ACKPOLICY) == IEEE80211_QOS_ACKPOLICY_NOACK))) macctl |= AR_TX_MAC_NOACK; if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { if (m->m_pkthdr.len + IEEE80211_CRC_LEN >= vap->iv_rtsthreshold) macctl |= AR_TX_MAC_RTS; else if (ic->ic_flags & IEEE80211_F_USEPROT) { if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) macctl |= AR_TX_MAC_CTS; else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) macctl |= AR_TX_MAC_RTS; } } phyctl |= AR_TX_PHY_MCS(rate); if (otus_hw_rate_is_ofdm(sc, rate)) { phyctl |= AR_TX_PHY_MT_OFDM; /* Always use all tx antennas for now, just to be safe */ phyctl |= AR_TX_PHY_ANTMSK(sc->txmask); } else { /* CCK */ phyctl |= AR_TX_PHY_MT_CCK; phyctl |= AR_TX_PHY_ANTMSK(sc->txmask); } /* Update net80211 with the current counters */ otus_tx_update_ratectl(sc, ni); /* Update rate control stats for frames that are ACK'ed. */ if (!(macctl & AR_TX_MAC_NOACK)) OTUS_NODE(ni)->tx_done++; /* Fill Tx descriptor. */ head = (struct ar_tx_head *)data->buf; head->len = htole16(m->m_pkthdr.len + IEEE80211_CRC_LEN); head->macctl = htole16(macctl); head->phyctl = htole32(phyctl); m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&head[1]); data->buflen = xferlen; data->ni = ni; data->m = m; OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, "%s: tx: m=%p; data=%p; len=%d mac=0x%04x phy=0x%08x rate=0x%02x, ni_txrate=%d\n", __func__, m, data, head->len, head->macctl, head->phyctl, (int) rate, (int) ni->ni_txrate); /* Submit transfer */ STAILQ_INSERT_TAIL(&sc->sc_tx_pending[OTUS_BULK_TX], data, next); usbd_transfer_start(sc->sc_xfer[OTUS_BULK_TX]); return 0; } int otus_set_multi(struct otus_softc *sc) { uint32_t lo, hi; struct ieee80211com *ic = &sc->sc_ic; int r; if (ic->ic_allmulti > 0 || ic->ic_promisc > 0 || ic->ic_opmode == IEEE80211_M_MONITOR) { lo = 0xffffffff; hi = 0xffffffff; } else { struct ieee80211vap *vap; struct ifnet *ifp; struct ifmultiaddr *ifma; lo = hi = 0; TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { ifp = vap->iv_ifp; if_maddr_rlock(ifp); TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { caddr_t dl; uint32_t val; dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); val = LE_READ_4(dl + 4); /* Get address byte 5 */ val = val & 0x0000ff00; val = val >> 8; /* As per below, shift it >> 2 to get only 6 bits */ val = val >> 2; if (val < 32) lo |= 1 << val; else hi |= 1 << (val - 32); } if_maddr_runlock(ifp); } } #if 0 /* XXX openbsd code */ while (enm != NULL) { bit = enm->enm_addrlo[5] >> 2; if (bit < 32) lo |= 1 << bit; else hi |= 1 << (bit - 32); ETHER_NEXT_MULTI(step, enm); } #endif hi |= 1U << 31; /* Make sure the broadcast bit is set. */ OTUS_LOCK(sc); otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_L, lo); otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_H, hi); r = otus_write_barrier(sc); OTUS_UNLOCK(sc); return (r); } static void otus_updateedca(struct otus_softc *sc) { #define EXP2(val) ((1 << (val)) - 1) #define AIFS(val) ((val) * 9 + 10) struct ieee80211com *ic = &sc->sc_ic; const struct wmeParams *edca; OTUS_LOCK_ASSERT(sc); edca = ic->ic_wme.wme_chanParams.cap_wmeParams; /* Set CWmin/CWmax values. */ otus_write(sc, AR_MAC_REG_AC0_CW, EXP2(edca[WME_AC_BE].wmep_logcwmax) << 16 | EXP2(edca[WME_AC_BE].wmep_logcwmin)); otus_write(sc, AR_MAC_REG_AC1_CW, EXP2(edca[WME_AC_BK].wmep_logcwmax) << 16 | EXP2(edca[WME_AC_BK].wmep_logcwmin)); otus_write(sc, AR_MAC_REG_AC2_CW, EXP2(edca[WME_AC_VI].wmep_logcwmax) << 16 | EXP2(edca[WME_AC_VI].wmep_logcwmin)); otus_write(sc, AR_MAC_REG_AC3_CW, EXP2(edca[WME_AC_VO].wmep_logcwmax) << 16 | EXP2(edca[WME_AC_VO].wmep_logcwmin)); otus_write(sc, AR_MAC_REG_AC4_CW, /* Special TXQ. */ EXP2(edca[WME_AC_VO].wmep_logcwmax) << 16 | EXP2(edca[WME_AC_VO].wmep_logcwmin)); /* Set AIFSN values. */ otus_write(sc, AR_MAC_REG_AC1_AC0_AIFS, AIFS(edca[WME_AC_VI].wmep_aifsn) << 24 | AIFS(edca[WME_AC_BK].wmep_aifsn) << 12 | AIFS(edca[WME_AC_BE].wmep_aifsn)); otus_write(sc, AR_MAC_REG_AC3_AC2_AIFS, AIFS(edca[WME_AC_VO].wmep_aifsn) << 16 | /* Special TXQ. */ AIFS(edca[WME_AC_VO].wmep_aifsn) << 4 | AIFS(edca[WME_AC_VI].wmep_aifsn) >> 8); /* Set TXOP limit. */ otus_write(sc, AR_MAC_REG_AC1_AC0_TXOP, edca[WME_AC_BK].wmep_txopLimit << 16 | edca[WME_AC_BE].wmep_txopLimit); otus_write(sc, AR_MAC_REG_AC3_AC2_TXOP, edca[WME_AC_VO].wmep_txopLimit << 16 | edca[WME_AC_VI].wmep_txopLimit); /* XXX ACK policy? */ (void)otus_write_barrier(sc); #undef AIFS #undef EXP2 } static void otus_updateslot(struct otus_softc *sc) { struct ieee80211com *ic = &sc->sc_ic; uint32_t slottime; OTUS_LOCK_ASSERT(sc); slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; otus_write(sc, AR_MAC_REG_SLOT_TIME, slottime << 10); (void)otus_write_barrier(sc); } int otus_init_mac(struct otus_softc *sc) { int error; OTUS_LOCK_ASSERT(sc); otus_write(sc, AR_MAC_REG_ACK_EXTENSION, 0x40); otus_write(sc, AR_MAC_REG_RETRY_MAX, 0); otus_write(sc, AR_MAC_REG_SNIFFER, 0x2000000); otus_write(sc, AR_MAC_REG_RX_THRESHOLD, 0xc1f80); otus_write(sc, AR_MAC_REG_RX_PE_DELAY, 0x70); otus_write(sc, AR_MAC_REG_EIFS_AND_SIFS, 0xa144000); otus_write(sc, AR_MAC_REG_SLOT_TIME, 9 << 10); otus_write(sc, 0x1c3b2c, 0x19000000); /* NAV protects ACK only (in TXOP). */ otus_write(sc, 0x1c3b38, 0x201); /* Set beacon Tx power to 0x7. */ otus_write(sc, AR_MAC_REG_BCN_HT1, 0x8000170); otus_write(sc, AR_MAC_REG_BACKOFF_PROTECT, 0x105); otus_write(sc, 0x1c3b9c, 0x10000a); /* Filter any control frames, BAR is bit 24. */ otus_write(sc, 0x1c368c, 0x0500ffff); otus_write(sc, 0x1c3c40, 0x1); otus_write(sc, AR_MAC_REG_BASIC_RATE, 0x150f); otus_write(sc, AR_MAC_REG_MANDATORY_RATE, 0x150f); otus_write(sc, AR_MAC_REG_RTS_CTS_RATE, 0x10b01bb); otus_write(sc, 0x1c3694, 0x4003c1e); /* Enable LED0 and LED1. */ otus_write(sc, 0x1d0100, 0x3); otus_write(sc, 0x1d0104, 0x3); /* Switch MAC to OTUS interface. */ otus_write(sc, 0x1c3600, 0x3); otus_write(sc, 0x1c3c50, 0xffff); otus_write(sc, 0x1c3680, 0xf00008); /* Disable Rx timeout (workaround). */ otus_write(sc, 0x1c362c, 0); /* Set USB Rx stream mode maximum frame number to 2. */ otus_write(sc, 0x1e1110, 0x4); /* Set USB Rx stream mode timeout to 10us. */ otus_write(sc, 0x1e1114, 0x80); /* Set clock frequency to 88/80MHz. */ otus_write(sc, 0x1d4008, 0x73); /* Set WLAN DMA interrupt mode: generate intr per packet. */ otus_write(sc, 0x1c3d7c, 0x110011); otus_write(sc, 0x1c3bb0, 0x4); otus_write(sc, AR_MAC_REG_TXOP_NOT_ENOUGH_INDICATION, 0x141e0f48); /* Disable HW decryption for now. */ otus_write(sc, 0x1c3678, 0x78); if ((error = otus_write_barrier(sc)) != 0) return error; /* Set default EDCA parameters. */ otus_updateedca(sc); return 0; } /* * Return default value for PHY register based on current operating mode. */ uint32_t otus_phy_get_def(struct otus_softc *sc, uint32_t reg) { int i; for (i = 0; i < nitems(ar5416_phy_regs); i++) if (AR_PHY(ar5416_phy_regs[i]) == reg) return sc->phy_vals[i]; return 0; /* Register not found. */ } /* * Update PHY's programming based on vendor-specific data stored in EEPROM. * This is for FEM-type devices only. */ int otus_set_board_values(struct otus_softc *sc, struct ieee80211_channel *c) { const struct ModalEepHeader *eep; uint32_t tmp, offset; if (IEEE80211_IS_CHAN_5GHZ(c)) eep = &sc->eeprom.modalHeader[0]; else eep = &sc->eeprom.modalHeader[1]; /* Offset of chain 2. */ offset = 2 * 0x1000; tmp = le32toh(eep->antCtrlCommon); otus_write(sc, AR_PHY_SWITCH_COM, tmp); tmp = le32toh(eep->antCtrlChain[0]); otus_write(sc, AR_PHY_SWITCH_CHAIN_0, tmp); tmp = le32toh(eep->antCtrlChain[1]); otus_write(sc, AR_PHY_SWITCH_CHAIN_0 + offset, tmp); if (1 /* sc->sc_sco == AR_SCO_SCN */) { tmp = otus_phy_get_def(sc, AR_PHY_SETTLING); tmp &= ~(0x7f << 7); tmp |= (eep->switchSettling & 0x7f) << 7; otus_write(sc, AR_PHY_SETTLING, tmp); } tmp = otus_phy_get_def(sc, AR_PHY_DESIRED_SZ); tmp &= ~0xffff; tmp |= eep->pgaDesiredSize << 8 | eep->adcDesiredSize; otus_write(sc, AR_PHY_DESIRED_SZ, tmp); tmp = eep->txEndToXpaOff << 24 | eep->txEndToXpaOff << 16 | eep->txFrameToXpaOn << 8 | eep->txFrameToXpaOn; otus_write(sc, AR_PHY_RF_CTL4, tmp); tmp = otus_phy_get_def(sc, AR_PHY_RF_CTL3); tmp &= ~(0xff << 16); tmp |= eep->txEndToRxOn << 16; otus_write(sc, AR_PHY_RF_CTL3, tmp); tmp = otus_phy_get_def(sc, AR_PHY_CCA); tmp &= ~(0x7f << 12); tmp |= (eep->thresh62 & 0x7f) << 12; otus_write(sc, AR_PHY_CCA, tmp); tmp = otus_phy_get_def(sc, AR_PHY_RXGAIN); tmp &= ~(0x3f << 12); tmp |= (eep->txRxAttenCh[0] & 0x3f) << 12; otus_write(sc, AR_PHY_RXGAIN, tmp); tmp = otus_phy_get_def(sc, AR_PHY_RXGAIN + offset); tmp &= ~(0x3f << 12); tmp |= (eep->txRxAttenCh[1] & 0x3f) << 12; otus_write(sc, AR_PHY_RXGAIN + offset, tmp); tmp = otus_phy_get_def(sc, AR_PHY_GAIN_2GHZ); tmp &= ~(0x3f << 18); tmp |= (eep->rxTxMarginCh[0] & 0x3f) << 18; if (IEEE80211_IS_CHAN_5GHZ(c)) { tmp &= ~(0xf << 10); tmp |= (eep->bswMargin[0] & 0xf) << 10; } otus_write(sc, AR_PHY_GAIN_2GHZ, tmp); tmp = otus_phy_get_def(sc, AR_PHY_GAIN_2GHZ + offset); tmp &= ~(0x3f << 18); tmp |= (eep->rxTxMarginCh[1] & 0x3f) << 18; otus_write(sc, AR_PHY_GAIN_2GHZ + offset, tmp); tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4); tmp &= ~(0x3f << 5 | 0x1f); tmp |= (eep->iqCalICh[0] & 0x3f) << 5 | (eep->iqCalQCh[0] & 0x1f); otus_write(sc, AR_PHY_TIMING_CTRL4, tmp); tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4 + offset); tmp &= ~(0x3f << 5 | 0x1f); tmp |= (eep->iqCalICh[1] & 0x3f) << 5 | (eep->iqCalQCh[1] & 0x1f); otus_write(sc, AR_PHY_TIMING_CTRL4 + offset, tmp); tmp = otus_phy_get_def(sc, AR_PHY_TPCRG1); tmp &= ~(0xf << 16); tmp |= (eep->xpd & 0xf) << 16; otus_write(sc, AR_PHY_TPCRG1, tmp); return otus_write_barrier(sc); } int otus_program_phy(struct otus_softc *sc, struct ieee80211_channel *c) { const uint32_t *vals; int error, i; /* Select PHY programming based on band and bandwidth. */ if (IEEE80211_IS_CHAN_2GHZ(c)) vals = ar5416_phy_vals_2ghz_20mhz; else vals = ar5416_phy_vals_5ghz_20mhz; for (i = 0; i < nitems(ar5416_phy_regs); i++) otus_write(sc, AR_PHY(ar5416_phy_regs[i]), vals[i]); sc->phy_vals = vals; if (sc->eeprom.baseEepHeader.deviceType == 0x80) /* FEM */ if ((error = otus_set_board_values(sc, c)) != 0) return error; /* Initial Tx power settings. */ otus_write(sc, AR_PHY_POWER_TX_RATE_MAX, 0x7f); otus_write(sc, AR_PHY_POWER_TX_RATE1, 0x3f3f3f3f); otus_write(sc, AR_PHY_POWER_TX_RATE2, 0x3f3f3f3f); otus_write(sc, AR_PHY_POWER_TX_RATE3, 0x3f3f3f3f); otus_write(sc, AR_PHY_POWER_TX_RATE4, 0x3f3f3f3f); otus_write(sc, AR_PHY_POWER_TX_RATE5, 0x3f3f3f3f); otus_write(sc, AR_PHY_POWER_TX_RATE6, 0x3f3f3f3f); otus_write(sc, AR_PHY_POWER_TX_RATE7, 0x3f3f3f3f); otus_write(sc, AR_PHY_POWER_TX_RATE8, 0x3f3f3f3f); otus_write(sc, AR_PHY_POWER_TX_RATE9, 0x3f3f3f3f); if (IEEE80211_IS_CHAN_2GHZ(c)) otus_write(sc, 0x1d4014, 0x5163); else otus_write(sc, 0x1d4014, 0x5143); return otus_write_barrier(sc); } static __inline uint8_t otus_reverse_bits(uint8_t v) { v = ((v >> 1) & 0x55) | ((v & 0x55) << 1); v = ((v >> 2) & 0x33) | ((v & 0x33) << 2); v = ((v >> 4) & 0x0f) | ((v & 0x0f) << 4); return v; } int otus_set_rf_bank4(struct otus_softc *sc, struct ieee80211_channel *c) { uint8_t chansel, d0, d1; uint16_t data; int error; OTUS_LOCK_ASSERT(sc); d0 = 0; if (IEEE80211_IS_CHAN_5GHZ(c)) { chansel = (c->ic_freq - 4800) / 5; if (chansel & 1) d0 |= AR_BANK4_AMODE_REFSEL(2); else d0 |= AR_BANK4_AMODE_REFSEL(1); } else { d0 |= AR_BANK4_AMODE_REFSEL(2); if (c->ic_freq == 2484) { /* CH 14 */ d0 |= AR_BANK4_BMODE_LF_SYNTH_FREQ; chansel = 10 + (c->ic_freq - 2274) / 5; } else chansel = 16 + (c->ic_freq - 2272) / 5; chansel <<= 2; } d0 |= AR_BANK4_ADDR(1) | AR_BANK4_CHUP; d1 = otus_reverse_bits(chansel); /* Write bits 0-4 of d0 and d1. */ data = (d1 & 0x1f) << 5 | (d0 & 0x1f); otus_write(sc, AR_PHY(44), data); /* Write bits 5-7 of d0 and d1. */ data = (d1 >> 5) << 5 | (d0 >> 5); otus_write(sc, AR_PHY(58), data); if ((error = otus_write_barrier(sc)) == 0) otus_delay_ms(sc, 10); return error; } void otus_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) { #define COEFF_SCALE_SHIFT 24 uint32_t exp, man; /* exponent = 14 - floor(log2(coeff)) */ for (exp = 31; exp > 0; exp--) if (coeff & (1 << exp)) break; KASSERT(exp != 0, ("exp")); exp = 14 - (exp - COEFF_SCALE_SHIFT); /* mantissa = floor(coeff * 2^exponent + 0.5) */ man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); *mantissa = man >> (COEFF_SCALE_SHIFT - exp); *exponent = exp - 16; #undef COEFF_SCALE_SHIFT } static int otus_set_chan(struct otus_softc *sc, struct ieee80211_channel *c, int assoc) { struct ieee80211com *ic = &sc->sc_ic; struct ar_cmd_frequency cmd; struct ar_rsp_frequency rsp; const uint32_t *vals; uint32_t coeff, exp, man, tmp; uint8_t code; int error, chan, i; error = 0; chan = ieee80211_chan2ieee(ic, c); OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, "setting channel %d (%dMHz)\n", chan, c->ic_freq); tmp = IEEE80211_IS_CHAN_2GHZ(c) ? 0x105 : 0x104; otus_write(sc, AR_MAC_REG_DYNAMIC_SIFS_ACK, tmp); if ((error = otus_write_barrier(sc)) != 0) goto finish; /* Disable BB Heavy Clip. */ otus_write(sc, AR_PHY_HEAVY_CLIP_ENABLE, 0x200); if ((error = otus_write_barrier(sc)) != 0) goto finish; /* XXX Is that FREQ_START ? */ error = otus_cmd(sc, AR_CMD_FREQ_STRAT, NULL, 0, NULL, 0); if (error != 0) goto finish; /* Reprogram PHY and RF on channel band or bandwidth changes. */ if (sc->bb_reset || c->ic_flags != sc->sc_curchan->ic_flags) { OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, "band switch\n"); /* Cold/Warm reset BB/ADDA. */ otus_write(sc, 0x1d4004, sc->bb_reset ? 0x800 : 0x400); if ((error = otus_write_barrier(sc)) != 0) goto finish; otus_write(sc, 0x1d4004, 0); if ((error = otus_write_barrier(sc)) != 0) goto finish; sc->bb_reset = 0; if ((error = otus_program_phy(sc, c)) != 0) { device_printf(sc->sc_dev, "%s: could not program PHY\n", __func__); goto finish; } /* Select RF programming based on band. */ if (IEEE80211_IS_CHAN_5GHZ(c)) vals = ar5416_banks_vals_5ghz; else vals = ar5416_banks_vals_2ghz; for (i = 0; i < nitems(ar5416_banks_regs); i++) otus_write(sc, AR_PHY(ar5416_banks_regs[i]), vals[i]); if ((error = otus_write_barrier(sc)) != 0) { device_printf(sc->sc_dev, "%s: could not program RF\n", __func__); goto finish; } code = AR_CMD_RF_INIT; } else { code = AR_CMD_FREQUENCY; } if ((error = otus_set_rf_bank4(sc, c)) != 0) goto finish; tmp = (sc->txmask == 0x5) ? 0x340 : 0x240; otus_write(sc, AR_PHY_TURBO, tmp); if ((error = otus_write_barrier(sc)) != 0) goto finish; /* Send firmware command to set channel. */ cmd.freq = htole32((uint32_t)c->ic_freq * 1000); cmd.dynht2040 = htole32(0); cmd.htena = htole32(1); /* Set Delta Slope (exponent and mantissa). */ coeff = (100 << 24) / c->ic_freq; otus_get_delta_slope(coeff, &exp, &man); cmd.dsc_exp = htole32(exp); cmd.dsc_man = htole32(man); OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, "ds coeff=%u exp=%u man=%u\n", coeff, exp, man); /* For Short GI, coeff is 9/10 that of normal coeff. */ coeff = (9 * coeff) / 10; otus_get_delta_slope(coeff, &exp, &man); cmd.dsc_shgi_exp = htole32(exp); cmd.dsc_shgi_man = htole32(man); OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, "ds shgi coeff=%u exp=%u man=%u\n", coeff, exp, man); /* Set wait time for AGC and noise calibration (100 or 200ms). */ cmd.check_loop_count = assoc ? htole32(2000) : htole32(1000); OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, "%s\n", (code == AR_CMD_RF_INIT) ? "RF_INIT" : "FREQUENCY"); error = otus_cmd(sc, code, &cmd, sizeof cmd, &rsp, sizeof(rsp)); if (error != 0) goto finish; if ((rsp.status & htole32(AR_CAL_ERR_AGC | AR_CAL_ERR_NF_VAL)) != 0) { OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, "status=0x%x\n", le32toh(rsp.status)); /* Force cold reset on next channel. */ sc->bb_reset = 1; } #ifdef USB_DEBUG if (otus_debug & OTUS_DEBUG_RESET) { device_printf(sc->sc_dev, "calibration status=0x%x\n", le32toh(rsp.status)); for (i = 0; i < 2; i++) { /* 2 Rx chains */ /* Sign-extend 9-bit NF values. */ device_printf(sc->sc_dev, "noisefloor chain %d=%d\n", i, (((int32_t)le32toh(rsp.nf[i])) << 4) >> 23); device_printf(sc->sc_dev, "noisefloor ext chain %d=%d\n", i, ((int32_t)le32toh(rsp.nf_ext[i])) >> 23); } } #endif for (i = 0; i < OTUS_NUM_CHAINS; i++) { sc->sc_nf[i] = ((((int32_t)le32toh(rsp.nf[i])) << 4) >> 23); } sc->sc_curchan = c; finish: return (error); } #ifdef notyet int otus_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, struct ieee80211_key *k) { struct otus_softc *sc = ic->ic_softc; struct otus_cmd_key cmd; /* Defer setting of WEP keys until interface is brought up. */ if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != (IFF_UP | IFF_RUNNING)) return 0; /* Do it in a process context. */ cmd.key = *k; cmd.associd = (ni != NULL) ? ni->ni_associd : 0; otus_do_async(sc, otus_set_key_cb, &cmd, sizeof cmd); return 0; } void otus_set_key_cb(struct otus_softc *sc, void *arg) { struct otus_cmd_key *cmd = arg; struct ieee80211_key *k = &cmd->key; struct ar_cmd_ekey key; uint16_t cipher; int error; memset(&key, 0, sizeof key); if (k->k_flags & IEEE80211_KEY_GROUP) { key.uid = htole16(k->k_id); IEEE80211_ADDR_COPY(key.macaddr, sc->sc_ic.ic_myaddr); key.macaddr[0] |= 0x80; } else { key.uid = htole16(OTUS_UID(cmd->associd)); IEEE80211_ADDR_COPY(key.macaddr, ni->ni_macaddr); } key.kix = htole16(0); /* Map net80211 cipher to hardware. */ switch (k->k_cipher) { case IEEE80211_CIPHER_WEP40: cipher = AR_CIPHER_WEP64; break; case IEEE80211_CIPHER_WEP104: cipher = AR_CIPHER_WEP128; break; case IEEE80211_CIPHER_TKIP: cipher = AR_CIPHER_TKIP; break; case IEEE80211_CIPHER_CCMP: cipher = AR_CIPHER_AES; break; default: return; } key.cipher = htole16(cipher); memcpy(key.key, k->k_key, MIN(k->k_len, 16)); error = otus_cmd(sc, AR_CMD_EKEY, &key, sizeof key, NULL, 0); if (error != 0 || k->k_cipher != IEEE80211_CIPHER_TKIP) return; /* TKIP: set Tx/Rx MIC Key. */ key.kix = htole16(1); memcpy(key.key, k->k_key + 16, 16); (void)otus_cmd(sc, AR_CMD_EKEY, &key, sizeof key, NULL, 0); } void otus_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, struct ieee80211_key *k) { struct otus_softc *sc = ic->ic_softc; struct otus_cmd_key cmd; if (!(ic->ic_if.if_flags & IFF_RUNNING) || ic->ic_state != IEEE80211_S_RUN) return; /* Nothing to do. */ /* Do it in a process context. */ cmd.key = *k; cmd.associd = (ni != NULL) ? ni->ni_associd : 0; otus_do_async(sc, otus_delete_key_cb, &cmd, sizeof cmd); } void otus_delete_key_cb(struct otus_softc *sc, void *arg) { struct otus_cmd_key *cmd = arg; struct ieee80211_key *k = &cmd->key; uint32_t uid; if (k->k_flags & IEEE80211_KEY_GROUP) uid = htole32(k->k_id); else uid = htole32(OTUS_UID(cmd->associd)); (void)otus_cmd(sc, AR_CMD_DKEY, &uid, sizeof uid, NULL, 0); } #endif /* * XXX TODO: check if we have to be doing any calibration in the host * or whether it's purely a firmware thing. */ void otus_calibrate_to(void *arg, int pending) { #if 0 struct otus_softc *sc = arg; device_printf(sc->sc_dev, "%s: called\n", __func__); struct ieee80211com *ic = &sc->sc_ic; struct ieee80211_node *ni; int s; if (usbd_is_dying(sc->sc_udev)) return; usbd_ref_incr(sc->sc_udev); s = splnet(); ni = ic->ic_bss; ieee80211_amrr_choose(&sc->amrr, ni, &((struct otus_node *)ni)->amn); splx(s); if (!usbd_is_dying(sc->sc_udev)) timeout_add_sec(&sc->calib_to, 1); usbd_ref_decr(sc->sc_udev); #endif } int otus_set_bssid(struct otus_softc *sc, const uint8_t *bssid) { OTUS_LOCK_ASSERT(sc); otus_write(sc, AR_MAC_REG_BSSID_L, bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); otus_write(sc, AR_MAC_REG_BSSID_H, bssid[4] | bssid[5] << 8); return otus_write_barrier(sc); } int otus_set_macaddr(struct otus_softc *sc, const uint8_t *addr) { OTUS_LOCK_ASSERT(sc); otus_write(sc, AR_MAC_REG_MAC_ADDR_L, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); otus_write(sc, AR_MAC_REG_MAC_ADDR_H, addr[4] | addr[5] << 8); return otus_write_barrier(sc); } /* Default single-LED. */ void otus_led_newstate_type1(struct otus_softc *sc) { /* TBD */ device_printf(sc->sc_dev, "%s: TODO\n", __func__); } /* NETGEAR, dual-LED. */ void otus_led_newstate_type2(struct otus_softc *sc) { /* TBD */ device_printf(sc->sc_dev, "%s: TODO\n", __func__); } /* NETGEAR, single-LED/3 colors (blue, red, purple.) */ void otus_led_newstate_type3(struct otus_softc *sc) { #if 0 struct ieee80211com *ic = &sc->sc_ic; struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); uint32_t state = sc->led_state; OTUS_LOCK_ASSERT(sc); if (!vap) { state = 0; /* led off */ } else if (vap->iv_state == IEEE80211_S_INIT) { state = 0; /* LED off. */ } else if (vap->iv_state == IEEE80211_S_RUN) { /* Associated, LED always on. */ if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) state = AR_LED0_ON; /* 2GHz=>Red. */ else state = AR_LED1_ON; /* 5GHz=>Blue. */ } else { /* Scanning, blink LED. */ state ^= AR_LED0_ON | AR_LED1_ON; if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) state &= ~AR_LED1_ON; else state &= ~AR_LED0_ON; } if (state != sc->led_state) { otus_write(sc, 0x1d0104, state); if (otus_write_barrier(sc) == 0) sc->led_state = state; } #endif } int otus_init(struct otus_softc *sc) { struct ieee80211com *ic = &sc->sc_ic; int error; OTUS_UNLOCK_ASSERT(sc); OTUS_LOCK(sc); /* Drain any pending TX frames */ otus_drain_mbufq(sc); /* Init MAC */ if ((error = otus_init_mac(sc)) != 0) { OTUS_UNLOCK(sc); device_printf(sc->sc_dev, "%s: could not initialize MAC\n", __func__); return error; } (void) otus_set_macaddr(sc, ic->ic_macaddr); #if 0 switch (ic->ic_opmode) { #ifdef notyet #ifndef IEEE80211_STA_ONLY case IEEE80211_M_HOSTAP: otus_write(sc, 0x1c3700, 0x0f0000a1); otus_write(sc, 0x1c3c40, 0x1); break; case IEEE80211_M_IBSS: otus_write(sc, 0x1c3700, 0x0f000000); otus_write(sc, 0x1c3c40, 0x1); break; #endif #endif case IEEE80211_M_STA: otus_write(sc, 0x1c3700, 0x0f000002); otus_write(sc, 0x1c3c40, 0x1); break; default: break; } #endif /* Expect STA operation */ otus_write(sc, 0x1c3700, 0x0f000002); otus_write(sc, 0x1c3c40, 0x1); /* XXX ic_opmode? */ otus_write(sc, AR_MAC_REG_SNIFFER, (ic->ic_opmode == IEEE80211_M_MONITOR) ? 0x2000001 : 0x2000000); (void)otus_write_barrier(sc); sc->bb_reset = 1; /* Force cold reset. */ if ((error = otus_set_chan(sc, ic->ic_curchan, 0)) != 0) { OTUS_UNLOCK(sc); device_printf(sc->sc_dev, "%s: could not set channel\n", __func__); return error; } /* Start Rx. */ otus_write(sc, 0x1c3d30, 0x100); (void)otus_write_barrier(sc); sc->sc_running = 1; OTUS_UNLOCK(sc); return 0; } void otus_stop(struct otus_softc *sc) { #if 0 int s; #endif OTUS_UNLOCK_ASSERT(sc); OTUS_LOCK(sc); sc->sc_running = 0; sc->sc_tx_timer = 0; OTUS_UNLOCK(sc); taskqueue_drain_timeout(taskqueue_thread, &sc->scan_to); taskqueue_drain_timeout(taskqueue_thread, &sc->calib_to); taskqueue_drain(taskqueue_thread, &sc->tx_task); taskqueue_drain(taskqueue_thread, &sc->wme_update_task); OTUS_LOCK(sc); sc->sc_running = 0; /* Stop Rx. */ otus_write(sc, 0x1c3d30, 0); (void)otus_write_barrier(sc); /* Drain any pending TX frames */ otus_drain_mbufq(sc); OTUS_UNLOCK(sc); } Index: head/sys/dev/otus/if_otusreg.h =================================================================== --- head/sys/dev/otus/if_otusreg.h (revision 289167) +++ head/sys/dev/otus/if_otusreg.h (revision 289168) @@ -1,1030 +1,1028 @@ /* $OpenBSD: if_otusreg.h,v 1.9 2013/11/26 20:33:18 deraadt Exp $ */ /*- * Copyright (c) 2009 Damien Bergamini * Copyright (c) 2007-2008 Atheros Communications, Inc. * Copyright (c) 2015 Adrian Chadd * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ #ifndef __IF_OTUSREG_H__ #define __IF_OTUSREG_H__ /* USB Endpoints addresses. */ #define AR_EPT_BULK_TX_NO (UE_DIR_OUT | 1) #define AR_EPT_BULK_RX_NO (UE_DIR_IN | 2) #define AR_EPT_INTR_RX_NO (UE_DIR_IN | 3) #define AR_EPT_INTR_TX_NO (UE_DIR_OUT | 4) /* USB Requests. */ #define AR_FW_DOWNLOAD 0x30 #define AR_FW_DOWNLOAD_COMPLETE 0x31 /* Maximum number of writes that can fit in a single FW command is 7. */ #define AR_MAX_WRITE_IDX 6 /* 56 bytes */ #define AR_FW_INIT_ADDR 0x102800 #define AR_FW_MAIN_ADDR 0x200000 #define AR_USB_MODE_CTRL 0x1e1108 /* * AR9170 MAC registers. */ #define AR_MAC_REG_BASE 0x1c3000 #define AR_MAC_REG_MAC_ADDR_L (AR_MAC_REG_BASE + 0x610) #define AR_MAC_REG_MAC_ADDR_H (AR_MAC_REG_BASE + 0x614) #define AR_MAC_REG_BSSID_L (AR_MAC_REG_BASE + 0x618) #define AR_MAC_REG_BSSID_H (AR_MAC_REG_BASE + 0x61c) #define AR_MAC_REG_GROUP_HASH_TBL_L (AR_MAC_REG_BASE + 0x624) #define AR_MAC_REG_GROUP_HASH_TBL_H (AR_MAC_REG_BASE + 0x628) #define AR_MAC_REG_BASIC_RATE (AR_MAC_REG_BASE + 0x630) #define AR_MAC_REG_MANDATORY_RATE (AR_MAC_REG_BASE + 0x634) #define AR_MAC_REG_RTS_CTS_RATE (AR_MAC_REG_BASE + 0x638) #define AR_MAC_REG_BACKOFF_PROTECT (AR_MAC_REG_BASE + 0x63c) #define AR_MAC_REG_RX_THRESHOLD (AR_MAC_REG_BASE + 0x640) #define AR_MAC_REG_RX_PE_DELAY (AR_MAC_REG_BASE + 0x64c) #define AR_MAC_REG_DYNAMIC_SIFS_ACK (AR_MAC_REG_BASE + 0x658) #define AR_MAC_REG_SNIFFER (AR_MAC_REG_BASE + 0x674) #define AR_MAC_REG_ACK_EXTENSION (AR_MAC_REG_BASE + 0x690) #define AR_MAC_REG_EIFS_AND_SIFS (AR_MAC_REG_BASE + 0x698) #define AR_MAC_REG_BUSY (AR_MAC_REG_BASE + 0x6e8) #define AR_MAC_REG_BUSY_EXT (AR_MAC_REG_BASE + 0x6ec) #define AR_MAC_REG_SLOT_TIME (AR_MAC_REG_BASE + 0x6f0) #define AR_MAC_REG_AC0_CW (AR_MAC_REG_BASE + 0xb00) #define AR_MAC_REG_AC1_CW (AR_MAC_REG_BASE + 0xb04) #define AR_MAC_REG_AC2_CW (AR_MAC_REG_BASE + 0xb08) #define AR_MAC_REG_AC3_CW (AR_MAC_REG_BASE + 0xb0c) #define AR_MAC_REG_AC4_CW (AR_MAC_REG_BASE + 0xb10) #define AR_MAC_REG_AC1_AC0_AIFS (AR_MAC_REG_BASE + 0xb14) #define AR_MAC_REG_AC3_AC2_AIFS (AR_MAC_REG_BASE + 0xb18) #define AR_MAC_REG_RETRY_MAX (AR_MAC_REG_BASE + 0xb28) #define AR_MAC_REG_TXOP_NOT_ENOUGH_INDICATION \ (AR_MAC_REG_BASE + 0xb30) #define AR_MAC_REG_AC1_AC0_TXOP (AR_MAC_REG_BASE + 0xb44) #define AR_MAC_REG_AC3_AC2_TXOP (AR_MAC_REG_BASE + 0xb48) #define AR_MAC_REG_OFDM_PHY_ERRORS (AR_MAC_REG_BASE + 0xcb4) #define AR_MAC_REG_CCK_PHY_ERRORS (AR_MAC_REG_BASE + 0xcb8) #define AR_MAC_REG_BCN_HT1 (AR_MAC_REG_BASE + 0xda0) /* Possible values for register AR_USB_MODE_CTRL. */ #define AR_USB_DS_ENA (1 << 0) #define AR_USB_US_ENA (1 << 1) #define AR_USB_US_PACKET_MODE (1 << 3) #define AR_USB_RX_STREAM_4K (0 << 4) #define AR_USB_RX_STREAM_8K (1 << 4) #define AR_USB_RX_STREAM_16K (2 << 4) #define AR_USB_RX_STREAM_32K (3 << 4) #define AR_USB_TX_STREAM_MODE (1 << 6) #define AR_LED0_ON (1 << 0) #define AR_LED1_ON (1 << 1) /* * PHY registers. */ #define AR_PHY_BASE 0x1c5800 #define AR_PHY(reg) (AR_PHY_BASE + (reg) * 4) #define AR_PHY_TURBO (AR_PHY_BASE + 0x0004) #define AR_PHY_RF_CTL3 (AR_PHY_BASE + 0x0028) #define AR_PHY_RF_CTL4 (AR_PHY_BASE + 0x0034) #define AR_PHY_SETTLING (AR_PHY_BASE + 0x0044) #define AR_PHY_RXGAIN (AR_PHY_BASE + 0x0048) #define AR_PHY_DESIRED_SZ (AR_PHY_BASE + 0x0050) #define AR_PHY_FIND_SIG (AR_PHY_BASE + 0x0058) #define AR_PHY_AGC_CTL1 (AR_PHY_BASE + 0x005c) #define AR_PHY_SFCORR (AR_PHY_BASE + 0x0068) #define AR_PHY_SFCORR_LOW (AR_PHY_BASE + 0x006c) #define AR_PHY_TIMING_CTRL4 (AR_PHY_BASE + 0x0120) #define AR_PHY_TIMING5 (AR_PHY_BASE + 0x0124) #define AR_PHY_POWER_TX_RATE1 (AR_PHY_BASE + 0x0134) #define AR_PHY_POWER_TX_RATE2 (AR_PHY_BASE + 0x0138) #define AR_PHY_POWER_TX_RATE_MAX (AR_PHY_BASE + 0x013c) #define AR_PHY_SWITCH_CHAIN_0 (AR_PHY_BASE + 0x0160) #define AR_PHY_SWITCH_COM (AR_PHY_BASE + 0x0164) #define AR_PHY_HEAVY_CLIP_ENABLE (AR_PHY_BASE + 0x01e0) #define AR_PHY_CCK_DETECT (AR_PHY_BASE + 0x0a08) #define AR_PHY_GAIN_2GHZ (AR_PHY_BASE + 0x0a0c) #define AR_PHY_POWER_TX_RATE3 (AR_PHY_BASE + 0x0a34) #define AR_PHY_POWER_TX_RATE4 (AR_PHY_BASE + 0x0a38) #define AR_PHY_TPCRG1 (AR_PHY_BASE + 0x0a58) #define AR_PHY_POWER_TX_RATE5 (AR_PHY_BASE + 0x0b8c) #define AR_PHY_POWER_TX_RATE6 (AR_PHY_BASE + 0x0b90) #define AR_PHY_POWER_TX_RATE7 (AR_PHY_BASE + 0x0bcc) #define AR_PHY_POWER_TX_RATE8 (AR_PHY_BASE + 0x0bd0) #define AR_PHY_POWER_TX_RATE9 (AR_PHY_BASE + 0x0bd4) #define AR_PHY_CCA (AR_PHY_BASE + 0x3064) #define AR_SEEPROM_HW_TYPE_OFFSET 0x1374 #define AR_EEPROM_OFFSET 0x1600 #define AR_BANK4_CHUP (1 << 0) #define AR_BANK4_BMODE_LF_SYNTH_FREQ (1 << 1) #define AR_BANK4_AMODE_REFSEL(x) ((x) << 2) #define AR_BANK4_ADDR(x) ((x) << 5) /* Tx descriptor. */ struct ar_tx_head { uint16_t len; uint16_t macctl; #define AR_TX_MAC_RTS (1 << 0) #define AR_TX_MAC_CTS (1 << 1) #define AR_TX_MAC_BACKOFF (1 << 3) #define AR_TX_MAC_NOACK (1 << 2) #define AR_TX_MAC_HW_DUR (1 << 9) #define AR_TX_MAC_QID(qid) ((qid) << 10) #define AR_TX_MAC_RATE_PROBING (1 << 15) uint32_t phyctl; /* Modulation type. */ #define AR_TX_PHY_MT_CCK 0 #define AR_TX_PHY_MT_OFDM 1 #define AR_TX_PHY_MT_HT 2 #define AR_TX_PHY_GF (1 << 2) #define AR_TX_PHY_BW_SHIFT 3 #define AR_TX_PHY_TPC_SHIFT 9 #define AR_TX_PHY_ANTMSK(msk) ((msk) << 15) #define AR_TX_PHY_MCS(mcs) ((mcs) << 18) #define AR_TX_PHY_SHGI (1U << 31) } __packed; /* USB Rx stream mode header. */ struct ar_rx_head { uint16_t len; uint16_t tag; #define AR_RX_HEAD_TAG 0x4e00 } __packed; /* Rx descriptor. */ struct ar_rx_tail { uint8_t rssi_ant[3]; uint8_t rssi_ant_ext[3]; uint8_t rssi; /* Combined RSSI. */ uint8_t evm[2][6]; /* Error Vector Magnitude. */ uint8_t phy_err; uint8_t sa_idx; uint8_t da_idx; uint8_t error; #define AR_RX_ERROR_TIMEOUT (1 << 0) #define AR_RX_ERROR_OVERRUN (1 << 1) #define AR_RX_ERROR_DECRYPT (1 << 2) #define AR_RX_ERROR_FCS (1 << 3) #define AR_RX_ERROR_BAD_RA (1 << 4) #define AR_RX_ERROR_PLCP (1 << 5) #define AR_RX_ERROR_MMIC (1 << 6) uint8_t status; /* Modulation type (same as AR_TX_PHY_MT). */ #define AR_RX_STATUS_MT_MASK 0x3 #define AR_RX_STATUS_MT_CCK 0 #define AR_RX_STATUS_MT_OFDM 1 #define AR_RX_STATUS_MT_HT 2 #define AR_RX_STATUS_SHPREAMBLE (1 << 3) } __packed; #define AR_PLCP_HDR_LEN 12 /* Magic PLCP header for firmware notifications through Rx bulk pipe. */ static uint8_t AR_PLCP_HDR_INTR[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; /* Firmware command/reply header. */ struct ar_cmd_hdr { uint8_t len; uint8_t code; #define AR_CMD_RREG 0x00 #define AR_CMD_WREG 0x01 #define AR_CMD_RMEM 0x02 #define AR_CMD_WMEM 0x03 #define AR_CMD_BITAND 0x04 #define AR_CMD_BITOR 0x05 #define AR_CMD_EKEY 0x28 #define AR_CMD_DKEY 0x29 #define AR_CMD_FREQUENCY 0x30 #define AR_CMD_RF_INIT 0x31 #define AR_CMD_SYNTH 0x32 #define AR_CMD_FREQ_STRAT 0x33 #define AR_CMD_ECHO 0x80 #define AR_CMD_TALLY 0x81 #define AR_CMD_TALLY_APD 0x82 #define AR_CMD_CONFIG 0x83 #define AR_CMD_RESET 0x90 #define AR_CMD_DKRESET 0x91 #define AR_CMD_DKTX_STATUS 0x92 #define AR_CMD_FDC 0xa0 #define AR_CMD_WREEPROM 0xb0 #define AR_CMD_WFLASH AR_CMD_WREEPROM #define AR_CMD_FLASH_ERASE 0xb1 #define AR_CMD_FLASH_PROG 0xb2 #define AR_CMD_FLASH_CHKSUM 0xb3 #define AR_CMD_FLASH_READ 0xb4 #define AR_CMD_FW_DL_INIT 0xb5 #define AR_CMD_MEM_WREEPROM 0xbb /* Those have the 2 MSB set to 1. */ #define AR_EVT_BEACON 0x00 #define AR_EVT_TX_COMP 0x01 #define AR_EVT_TBTT 0x02 #define AR_EVT_ATIM 0x03 #define AR_EVT_DO_BB_RESET 0x09 uint16_t token; /* Driver private data. */ } __packed; /* Structure for command AR_CMD_RF_INIT/AR_CMD_FREQUENCY. */ struct ar_cmd_frequency { uint32_t freq; uint32_t dynht2040; uint32_t htena; uint32_t dsc_exp; uint32_t dsc_man; uint32_t dsc_shgi_exp; uint32_t dsc_shgi_man; uint32_t check_loop_count; } __packed; /* Firmware reply for command AR_CMD_FREQUENCY. */ struct ar_rsp_frequency { uint32_t status; #define AR_CAL_ERR_AGC (1 << 0) /* AGC cal unfinished. */ #define AR_CAL_ERR_NF (1 << 1) /* Noise cal unfinished. */ #define AR_CAL_ERR_NF_VAL (1 << 2) /* NF value unexpected. */ uint32_t nf[3]; /* Noisefloor. */ uint32_t nf_ext[3]; /* Noisefloor ext. */ } __packed; /* Structure for command AR_CMD_EKEY. */ struct ar_cmd_ekey { uint16_t uid; /* user ID */ uint16_t kix; uint16_t cipher; #define AR_CIPHER_NONE 0 #define AR_CIPHER_WEP64 1 #define AR_CIPHER_TKIP 2 #define AR_CIPHER_AES 4 #define AR_CIPHER_WEP128 5 #define AR_CIPHER_WEP256 6 #define AR_CIPHER_CENC 7 uint8_t macaddr[IEEE80211_ADDR_LEN]; uint8_t key[16]; } __packed; /* Structure for event AR_EVT_TX_COMP. */ struct ar_evt_tx_comp { uint8_t macaddr[IEEE80211_ADDR_LEN]; uint32_t phy; uint16_t status; #define AR_TX_STATUS_COMP 0 #define AR_TX_STATUS_RETRY_COMP 1 #define AR_TX_STATUS_FAILED 2 } __packed; /* List of supported channels. */ static const uint8_t ar_chans[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, 34, 38, 42, 46 }; /* * This data is automatically generated from the "otus.ini" file. * It is stored in a different way though, to reduce kernel's .rodata * section overhead (5.1KB instead of 8.5KB). */ /* NB: apply AR_PHY(). */ static const uint16_t ar5416_phy_regs[] = { 0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007, 0x008, 0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f, 0x010, 0x011, 0x012, 0x013, 0x014, 0x015, 0x016, 0x017, 0x018, 0x01a, 0x01b, 0x040, 0x041, 0x042, 0x043, 0x045, 0x046, 0x047, 0x048, 0x049, 0x04a, 0x04b, 0x04d, 0x04e, 0x04f, 0x051, 0x052, 0x053, 0x055, 0x056, 0x058, 0x059, 0x05c, 0x05d, 0x05e, 0x05f, 0x060, 0x061, 0x062, 0x063, 0x064, 0x065, 0x066, 0x067, 0x068, 0x069, 0x06a, 0x06b, 0x06c, 0x06d, 0x070, 0x071, 0x072, 0x073, 0x074, 0x075, 0x076, 0x077, 0x078, 0x079, 0x07a, 0x07b, 0x07c, 0x07f, 0x080, 0x081, 0x082, 0x083, 0x084, 0x085, 0x086, 0x087, 0x088, 0x089, 0x08a, 0x08b, 0x08c, 0x08d, 0x08e, 0x08f, 0x090, 0x091, 0x092, 0x093, 0x094, 0x095, 0x096, 0x097, 0x098, 0x099, 0x09a, 0x09b, 0x09c, 0x09d, 0x09e, 0x09f, 0x0a0, 0x0a1, 0x0a2, 0x0a3, 0x0a4, 0x0a5, 0x0a6, 0x0a7, 0x0a8, 0x0a9, 0x0aa, 0x0ab, 0x0ac, 0x0ad, 0x0ae, 0x0af, 0x0b0, 0x0b1, 0x0b2, 0x0b3, 0x0b4, 0x0b5, 0x0b6, 0x0b7, 0x0b8, 0x0b9, 0x0ba, 0x0bb, 0x0bc, 0x0bd, 0x0be, 0x0bf, 0x0c0, 0x0c1, 0x0c2, 0x0c3, 0x0c4, 0x0c5, 0x0c6, 0x0c7, 0x0c8, 0x0c9, 0x0ca, 0x0cb, 0x0cc, 0x0cd, 0x0ce, 0x0cf, 0x0d0, 0x0d1, 0x0d2, 0x0d3, 0x0d4, 0x0d5, 0x0d6, 0x0d7, 0x0d8, 0x0d9, 0x0da, 0x0db, 0x0dc, 0x0dd, 0x0de, 0x0df, 0x0e0, 0x0e1, 0x0e2, 0x0e3, 0x0e4, 0x0e5, 0x0e6, 0x0e7, 0x0e8, 0x0e9, 0x0ea, 0x0eb, 0x0ec, 0x0ed, 0x0ee, 0x0ef, 0x0f0, 0x0f1, 0x0f2, 0x0f3, 0x0f4, 0x0f5, 0x0f6, 0x0f7, 0x0f8, 0x0f9, 0x0fa, 0x0fb, 0x0fc, 0x0fd, 0x0fe, 0x0ff, 0x100, 0x103, 0x104, 0x105, 0x106, 0x107, 0x108, 0x109, 0x10a, 0x10b, 0x10c, 0x10d, 0x10e, 0x10f, 0x13c, 0x13d, 0x13e, 0x13f, 0x280, 0x281, 0x282, 0x283, 0x284, 0x285, 0x286, 0x287, 0x288, 0x289, 0x28a, 0x28b, 0x28c, 0x28d, 0x28e, 0x28f, 0x290, 0x291, 0x292, 0x293, 0x294, 0x295, 0x296, 0x297, 0x298, 0x299, 0x29a, 0x29b, 0x29d, 0x29e, 0x29f, 0x2c0, 0x2c1, 0x2c2, 0x2c3, 0x2c4, 0x2c5, 0x2c6, 0x2c7, 0x2c8, 0x2c9, 0x2ca, 0x2cb, 0x2cc, 0x2cd, 0x2ce, 0x2cf, 0x2d0, 0x2d1, 0x2d2, 0x2d3, 0x2d4, 0x2d5, 0x2d6, 0x2e2, 0x2e3, 0x2e4, 0x2e5, 0x2e6, 0x2e7, 0x2e8, 0x2e9, 0x2ea, 0x2eb, 0x2ec, 0x2ed, 0x2ee, 0x2ef, 0x2f0, 0x2f1, 0x2f2, 0x2f3, 0x2f4, 0x2f5, 0x2f6, 0x2f7, 0x2f8, 0x412, 0x448, 0x458, 0x683, 0x69b, 0x812, 0x848, 0x858, 0xa83, 0xa9b, 0xc19, 0xc57, 0xc5a, 0xc6f, 0xe9c, 0xed7, 0xed8, 0xed9, 0xeda, 0xedb, 0xedc, 0xedd, 0xede, 0xedf, 0xee0, 0xee1 }; static const uint32_t ar5416_phy_vals_5ghz_20mhz[] = { 0x00000007, 0x00000300, 0x00000000, 0xad848e19, 0x7d14e000, 0x9c0a9f6b, 0x00000090, 0x00000000, 0x02020200, 0x00000e0e, 0x0a020001, 0x0000a000, 0x00000000, 0x00000e0e, 0x00000007, 0x00200400, 0x206a002e, 0x1372161e, 0x001a6a65, 0x1284233c, 0x6c48b4e4, 0x00000859, 0x7ec80d2e, 0x31395c5e, 0x0004dd10, 0x409a4190, 0x050cb081, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000007d0, 0x00000118, 0x10000fff, 0x0510081c, 0xd0058a15, 0x00000001, 0x00000004, 0x3f3f3f3f, 0x3f3f3f3f, 0x0000007f, 0xdfb81020, 0x9280b212, 0x00020028, 0x5d50e188, 0x00081fff, 0x00009b40, 0x00001120, 0x190fb515, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000007, 0x001fff00, 0x006f00c4, 0x03051000, 0x00000820, 0x038919be, 0x06336f77, 0x60f6532c, 0x08f186c8, 0x00046384, 0x00000000, 0x00000000, 0x00000000, 0x00000200, 0x64646464, 0x3c787878, 0x000000aa, 0x00000000, 0x00001042, 0x00000000, 0x00000040, 0x00000080, 0x000001a1, 0x000001e1, 0x00000021, 0x00000061, 0x00000168, 0x000001a8, 0x000001e8, 0x00000028, 0x00000068, 0x00000189, 0x000001c9, 0x00000009, 0x00000049, 0x00000089, 0x00000170, 0x000001b0, 0x000001f0, 0x00000030, 0x00000070, 0x00000191, 0x000001d1, 0x00000011, 0x00000051, 0x00000091, 0x000001b8, 0x000001f8, 0x00000038, 0x00000078, 0x00000199, 0x000001d9, 0x00000019, 0x00000059, 0x00000099, 0x000000d9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 0x00000008, 0x00000009, 0x0000000a, 0x0000000b, 0x0000000c, 0x0000000d, 0x00000010, 0x00000011, 0x00000012, 0x00000013, 0x00000014, 0x00000015, 0x00000018, 0x00000019, 0x0000001a, 0x0000001b, 0x0000001c, 0x0000001d, 0x00000020, 0x00000021, 0x00000022, 0x00000023, 0x00000024, 0x00000025, 0x00000028, 0x00000029, 0x0000002a, 0x0000002b, 0x0000002c, 0x0000002d, 0x00000030, 0x00000031, 0x00000032, 0x00000033, 0x00000034, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000010, 0x0000001a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008, 0x00000440, 0xd6be4788, 0x012e8160, 0x40806333, 0x00106c10, 0x009c4060, 0x1883800a, 0x018830c6, 0x00000400, 0x000009b5, 0x00000000, 0x00000108, 0x3f3f3f3f, 0x3f3f3f3f, 0x13c889af, 0x38490a20, 0x00007bb6, 0x0fff3ffc, 0x00000001, 0x0000a000, 0x00000000, 0x0cc75380, 0x0f0f0f01, 0xdfa91f01, 0x00418a11, 0x00000000, 0x09249126, 0x0a1a9caa, 0x1ce739ce, 0x051701ce, 0x18010000, 0x30032602, 0x48073e06, 0x560b4c0a, 0x641a600f, 0x7a4f6e1b, 0x8c5b7e5a, 0x9d0f96cf, 0xb51fa69f, 0xcb3fbd07, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x0003ffff, 0x79a8aa1f, 0x08000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x1ce739ce, 0x000001ce, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x00000000, 0x1ce739ce, 0x000000c0, 0x00180a65, 0x0510001c, 0x00009b40, 0x012e8160, 0x09249126, 0x00180a65, 0x0510001c, 0x00009b40, 0x012e8160, 0x09249126, 0x0001c600, 0x004b6a8e, 0x000003ce, 0x00181400, 0x00820820, 0x066c420f, 0x0f282207, 0x17601685, 0x1f801104, 0x37a00c03, 0x3fc40883, 0x57c00803, 0x5fd80682, 0x7fe00482, 0x7f3c7bba, 0xf3307ff0 }; #ifdef notyet static const uint32_t ar5416_phy_vals_5ghz_40mhz[] = { 0x00000007, 0x000003c4, 0x00000000, 0xad848e19, 0x7d14e000, 0x9c0a9f6b, 0x00000090, 0x00000000, 0x02020200, 0x00000e0e, 0x0a020001, 0x0000a000, 0x00000000, 0x00000e0e, 0x00000007, 0x00200400, 0x206a002e, 0x13721c1e, 0x001a6a65, 0x1284233c, 0x6c48b4e4, 0x00000859, 0x7ec80d2e, 0x31395c5e, 0x0004dd10, 0x409a4190, 0x050cb081, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000007d0, 0x00000230, 0x10000fff, 0x0510081c, 0xd0058a15, 0x00000001, 0x00000004, 0x3f3f3f3f, 0x3f3f3f3f, 0x0000007f, 0xdfb81020, 0x9280b212, 0x00020028, 0x5d50e188, 0x00081fff, 0x00009b40, 0x00001120, 0x190fb515, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000007, 0x001fff00, 0x006f00c4, 0x03051000, 0x00000820, 0x038919be, 0x06336f77, 0x60f6532c, 0x08f186c8, 0x00046384, 0x00000000, 0x00000000, 0x00000000, 0x00000200, 0x64646464, 0x3c787878, 0x000000aa, 0x00000000, 0x00001042, 0x00000000, 0x00000040, 0x00000080, 0x000001a1, 0x000001e1, 0x00000021, 0x00000061, 0x00000168, 0x000001a8, 0x000001e8, 0x00000028, 0x00000068, 0x00000189, 0x000001c9, 0x00000009, 0x00000049, 0x00000089, 0x00000170, 0x000001b0, 0x000001f0, 0x00000030, 0x00000070, 0x00000191, 0x000001d1, 0x00000011, 0x00000051, 0x00000091, 0x000001b8, 0x000001f8, 0x00000038, 0x00000078, 0x00000199, 0x000001d9, 0x00000019, 0x00000059, 0x00000099, 0x000000d9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 0x00000008, 0x00000009, 0x0000000a, 0x0000000b, 0x0000000c, 0x0000000d, 0x00000010, 0x00000011, 0x00000012, 0x00000013, 0x00000014, 0x00000015, 0x00000018, 0x00000019, 0x0000001a, 0x0000001b, 0x0000001c, 0x0000001d, 0x00000020, 0x00000021, 0x00000022, 0x00000023, 0x00000024, 0x00000025, 0x00000028, 0x00000029, 0x0000002a, 0x0000002b, 0x0000002c, 0x0000002d, 0x00000030, 0x00000031, 0x00000032, 0x00000033, 0x00000034, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000010, 0x0000001a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008, 0x00000440, 0xd6be4788, 0x012e8160, 0x40806333, 0x00106c10, 0x009c4060, 0x1883800a, 0x018830c6, 0x00000400, 0x000009b5, 0x00000000, 0x00000210, 0x3f3f3f3f, 0x3f3f3f3f, 0x13c889af, 0x38490a20, 0x00007bb6, 0x0fff3ffc, 0x00000001, 0x0000a000, 0x00000000, 0x0cc75380, 0x0f0f0f01, 0xdfa91f01, 0x00418a11, 0x00000000, 0x09249126, 0x0a1a9caa, 0x1ce739ce, 0x051701ce, 0x18010000, 0x30032602, 0x48073e06, 0x560b4c0a, 0x641a600f, 0x7a4f6e1b, 0x8c5b7e5a, 0x9d0f96cf, 0xb51fa69f, 0xcb3fbcbf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x0003ffff, 0x79a8aa1f, 0x08000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x1ce739ce, 0x000001ce, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x00000000, 0x1ce739ce, 0x000000c0, 0x00180a65, 0x0510001c, 0x00009b40, 0x012e8160, 0x09249126, 0x00180a65, 0x0510001c, 0x00009b40, 0x012e8160, 0x09249126, 0x0001c600, 0x004b6a8e, 0x000003ce, 0x00181400, 0x00820820, 0x066c420f, 0x0f282207, 0x17601685, 0x1f801104, 0x37a00c03, 0x3fc40883, 0x57c00803, 0x5fd80682, 0x7fe00482, 0x7f3c7bba, 0xf3307ff0 }; #endif #ifdef notyet static const uint32_t ar5416_phy_vals_2ghz_40mhz[] = { 0x00000007, 0x000003c4, 0x00000000, 0xad848e19, 0x7d14e000, 0x9c0a9f6b, 0x00000090, 0x00000000, 0x02020200, 0x00000e0e, 0x0a020001, 0x0000a000, 0x00000000, 0x00000e0e, 0x00000007, 0x00200400, 0x206a002e, 0x13721c24, 0x00197a68, 0x1284233c, 0x6c48b0e4, 0x00000859, 0x7ec80d2e, 0x31395c5e, 0x0004dd20, 0x409a4190, 0x050cb081, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000898, 0x00000268, 0x10000fff, 0x0510001c, 0xd0058a15, 0x00000001, 0x00000004, 0x3f3f3f3f, 0x3f3f3f3f, 0x0000007f, 0xdfb81020, 0x9280b212, 0x00020028, 0x5d50e188, 0x00081fff, 0x00009b40, 0x00001120, 0x190fb515, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000007, 0x001fff00, 0x006f00c4, 0x03051000, 0x00000820, 0x038919be, 0x06336f77, 0x60f6532c, 0x08f186c8, 0x00046384, 0x00000000, 0x00000000, 0x00000000, 0x00000200, 0x64646464, 0x3c787878, 0x000000aa, 0x00000000, 0x00001042, 0x00000000, 0x00000040, 0x00000080, 0x00000141, 0x00000181, 0x000001c1, 0x00000001, 0x00000041, 0x000001a8, 0x000001e8, 0x00000028, 0x00000068, 0x000000a8, 0x00000169, 0x000001a9, 0x000001e9, 0x00000029, 0x00000069, 0x00000190, 0x000001d0, 0x00000010, 0x00000050, 0x00000090, 0x00000151, 0x00000191, 0x000001d1, 0x00000011, 0x00000051, 0x00000198, 0x000001d8, 0x00000018, 0x00000058, 0x00000098, 0x00000159, 0x00000199, 0x000001d9, 0x00000019, 0x00000059, 0x00000099, 0x000000d9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 0x00000008, 0x00000009, 0x0000000a, 0x0000000b, 0x0000000c, 0x0000000d, 0x00000010, 0x00000011, 0x00000012, 0x00000013, 0x00000014, 0x00000015, 0x00000018, 0x00000019, 0x0000001a, 0x0000001b, 0x0000001c, 0x0000001d, 0x00000020, 0x00000021, 0x00000022, 0x00000023, 0x00000024, 0x00000025, 0x00000028, 0x00000029, 0x0000002a, 0x0000002b, 0x0000002c, 0x0000002d, 0x00000030, 0x00000031, 0x00000032, 0x00000033, 0x00000034, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000010, 0x0000001a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000e, 0x00000440, 0xd03e4788, 0x012a8160, 0x40806333, 0x00106c10, 0x009c4060, 0x1883800a, 0x018830c6, 0x00000400, 0x000009b5, 0x00000000, 0x00000210, 0x3f3f3f3f, 0x3f3f3f3f, 0x13c889af, 0x38490a20, 0x00007bb6, 0x0fff3ffc, 0x00000001, 0x0000a000, 0x00000000, 0x0cc75380, 0x0f0f0f01, 0xdfa91f01, 0x00418a11, 0x00000000, 0x09249126, 0x0a1a7caa, 0x1ce739ce, 0x051701ce, 0x18010000, 0x2e032402, 0x4a0a3c06, 0x621a540b, 0x764f6c1b, 0x845b7a5a, 0x950f8ccf, 0xa5cf9b4f, 0xbddfaf1f, 0xd1ffc93f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x0003ffff, 0x79a8aa1f, 0x08000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x1ce739ce, 0x000001ce, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x00000000, 0x1ce739ce, 0x000000c0, 0x00180a68, 0x0510001c, 0x00009b40, 0x012a8160, 0x09249126, 0x00180a68, 0x0510001c, 0x00009b40, 0x012a8160, 0x09249126, 0x0001c600, 0x004b6a8e, 0x000003ce, 0x00181400, 0x00820820, 0x066c420f, 0x0f282207, 0x17601685, 0x1f801104, 0x37a00c03, 0x3fc40883, 0x57c00803, 0x5fd80682, 0x7fe00482, 0x7f3c7bba, 0xf3307ff0 }; #endif static const uint32_t ar5416_phy_vals_2ghz_20mhz[] = { 0x00000007, 0x00000300, 0x00000000, 0xad848e19, 0x7d14e000, 0x9c0a9f6b, 0x00000090, 0x00000000, 0x02020200, 0x00000e0e, 0x0a020001, 0x0000a000, 0x00000000, 0x00000e0e, 0x00000007, 0x00200400, 0x206a002e, 0x137216a4, 0x00197a68, 0x1284233c, 0x6c48b0e4, 0x00000859, 0x7ec80d2e, 0x31395c5e, 0x0004dd20, 0x409a4190, 0x050cb081, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000898, 0x00000134, 0x10000fff, 0x0510001c, 0xd0058a15, 0x00000001, 0x00000004, 0x3f3f3f3f, 0x3f3f3f3f, 0x0000007f, 0xdfb81020, 0x9280b212, 0x00020028, 0x5d50e188, 0x00081fff, 0x00009b40, 0x00001120, 0x190fb515, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000007, 0x001fff00, 0x006f00c4, 0x03051000, 0x00000820, 0x038919be, 0x06336f77, 0x60f6532c, 0x08f186c8, 0x00046384, 0x00000000, 0x00000000, 0x00000000, 0x00000200, 0x64646464, 0x3c787878, 0x000000aa, 0x00000000, 0x00001042, 0x00000000, 0x00000040, 0x00000080, 0x00000141, 0x00000181, 0x000001c1, 0x00000001, 0x00000041, 0x000001a8, 0x000001e8, 0x00000028, 0x00000068, 0x000000a8, 0x00000169, 0x000001a9, 0x000001e9, 0x00000029, 0x00000069, 0x00000190, 0x000001d0, 0x00000010, 0x00000050, 0x00000090, 0x00000151, 0x00000191, 0x000001d1, 0x00000011, 0x00000051, 0x00000198, 0x000001d8, 0x00000018, 0x00000058, 0x00000098, 0x00000159, 0x00000199, 0x000001d9, 0x00000019, 0x00000059, 0x00000099, 0x000000d9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 0x00000008, 0x00000009, 0x0000000a, 0x0000000b, 0x0000000c, 0x0000000d, 0x00000010, 0x00000011, 0x00000012, 0x00000013, 0x00000014, 0x00000015, 0x00000018, 0x00000019, 0x0000001a, 0x0000001b, 0x0000001c, 0x0000001d, 0x00000020, 0x00000021, 0x00000022, 0x00000023, 0x00000024, 0x00000025, 0x00000028, 0x00000029, 0x0000002a, 0x0000002b, 0x0000002c, 0x0000002d, 0x00000030, 0x00000031, 0x00000032, 0x00000033, 0x00000034, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000010, 0x0000001a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000e, 0x00000440, 0xd03e4788, 0x012a8160, 0x40806333, 0x00106c10, 0x009c4060, 0x1883800a, 0x018830c6, 0x00000400, 0x000009b5, 0x00000000, 0x00000108, 0x3f3f3f3f, 0x3f3f3f3f, 0x13c889af, 0x38490a20, 0x00007bb6, 0x0fff3ffc, 0x00000001, 0x0000a000, 0x00000000, 0x0cc75380, 0x0f0f0f01, 0xdfa91f01, 0x00418a11, 0x00000000, 0x09249126, 0x0a1a7caa, 0x1ce739ce, 0x051701ce, 0x18010000, 0x2e032402, 0x4a0a3c06, 0x621a540b, 0x764f6c1b, 0x845b7a5a, 0x950f8ccf, 0xa5cf9b4f, 0xbddfaf1f, 0xd1ffc93f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x0003ffff, 0x79a8aa1f, 0x08000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x1ce739ce, 0x000001ce, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x00000000, 0x1ce739ce, 0x000000c0, 0x00180a68, 0x0510001c, 0x00009b40, 0x012a8160, 0x09249126, 0x00180a68, 0x0510001c, 0x00009b40, 0x012a8160, 0x09249126, 0x0001c600, 0x004b6a8e, 0x000003ce, 0x00181400, 0x00820820, 0x066c420f, 0x0f282207, 0x17601685, 0x1f801104, 0x37a00c03, 0x3fc40883, 0x57c00803, 0x5fd80682, 0x7fe00482, 0x7f3c7bba, 0xf3307ff0 }; /* NB: apply AR_PHY(). */ static const uint8_t ar5416_banks_regs[] = { 0x2c, 0x38, 0x2c, 0x3b, 0x2c, 0x38, 0x3c, 0x2c, 0x3a, 0x2c, 0x39, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x38, 0x2c, 0x2c, 0x2c, 0x3c }; static const uint32_t ar5416_banks_vals_5ghz[] = { 0x1e5795e5, 0x02008020, 0x02108421, 0x00000008, 0x0e73ff17, 0x00000420, 0x01400018, 0x000001a1, 0x00000001, 0x00000013, 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004000, 0x00006c00, 0x00002c00, 0x00004800, 0x00004000, 0x00006000, 0x00001000, 0x00004000, 0x00007c00, 0x00007c00, 0x00007c00, 0x00007c00, 0x00007c00, 0x00087c00, 0x00007c00, 0x00005400, 0x00000c00, 0x00001800, 0x00007c00, 0x00006c00, 0x00006c00, 0x00007c00, 0x00002c00, 0x00003c00, 0x00003800, 0x00001c00, 0x00000800, 0x00000408, 0x00004c15, 0x00004188, 0x0000201e, 0x00010408, 0x00000801, 0x00000c08, 0x0000181e, 0x00001016, 0x00002800, 0x00004010, 0x0000081c, 0x00000115, 0x00000015, 0x00000066, 0x0000001c, 0x00000000, 0x00000004, 0x00000015, 0x0000001f, 0x00000000, 0x000000a0, 0x00000000, 0x00000040, 0x0000001c }; static const uint32_t ar5416_banks_vals_2ghz[] = { 0x1e5795e5, 0x02008020, 0x02108421, 0x00000008, 0x0e73ff17, 0x00000420, 0x01c00018, 0x000001a1, 0x00000001, 0x00000013, 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004000, 0x00006c00, 0x00002c00, 0x00004800, 0x00004000, 0x00006000, 0x00001000, 0x00004000, 0x00007c00, 0x00007c00, 0x00007c00, 0x00007c00, 0x00007c00, 0x00087c00, 0x00007c00, 0x00005400, 0x00000c00, 0x00001800, 0x00007c00, 0x00006c00, 0x00006c00, 0x00007c00, 0x00002c00, 0x00003c00, 0x00003800, 0x00001c00, 0x00000800, 0x00000408, 0x00004c15, 0x00004188, 0x0000201e, 0x00010408, 0x00000801, 0x00000c08, 0x0000181e, 0x00001016, 0x00002800, 0x00004010, 0x0000081c, 0x00000115, 0x00000015, 0x00000066, 0x0000001c, 0x00000000, 0x00000004, 0x00000015, 0x0000001f, 0x00000400, 0x000000a0, 0x00000000, 0x00000040, 0x0000001c }; /* * EEPROM. */ /* Possible flags for opCapFlags. */ #define AR5416_OPFLAGS_11A 0x01 #define AR5416_OPFLAGS_11G 0x02 #define AR5416_OPFLAGS_5G_HT40 0x04 #define AR5416_OPFLAGS_2G_HT40 0x08 #define AR5416_OPFLAGS_5G_HT20 0x10 #define AR5416_OPFLAGS_2G_HT20 0x20 #define AR5416_NUM_5G_CAL_PIERS 8 #define AR5416_NUM_2G_CAL_PIERS 4 #define AR5416_NUM_5G_20_TARGET_POWERS 8 #define AR5416_NUM_5G_40_TARGET_POWERS 8 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3 #define AR5416_NUM_2G_20_TARGET_POWERS 4 #define AR5416_NUM_2G_40_TARGET_POWERS 4 #define AR5416_NUM_CTLS 24 #define AR5416_NUM_BAND_EDGES 8 #define AR5416_NUM_PD_GAINS 4 #define AR5416_PD_GAIN_ICEPTS 5 #define AR5416_EEPROM_MODAL_SPURS 5 #define AR5416_MAX_CHAINS 2 struct BaseEepHeader { uint16_t length; uint16_t checksum; uint16_t version; uint8_t opCapFlags; uint8_t eepMisc; uint16_t regDmn[2]; uint8_t macAddr[6]; uint8_t rxMask; uint8_t txMask; uint16_t rfSilent; uint16_t blueToothOptions; uint16_t deviceCap; uint32_t binBuildNumber; uint8_t deviceType; uint8_t futureBase[33]; } __packed; struct spurChanStruct { uint16_t spurChan; uint8_t spurRangeLow; uint8_t spurRangeHigh; } __packed; struct ModalEepHeader { uint32_t antCtrlChain[AR5416_MAX_CHAINS]; uint32_t antCtrlCommon; int8_t antennaGainCh[AR5416_MAX_CHAINS]; uint8_t switchSettling; uint8_t txRxAttenCh[AR5416_MAX_CHAINS]; uint8_t rxTxMarginCh[AR5416_MAX_CHAINS]; uint8_t adcDesiredSize; int8_t pgaDesiredSize; uint8_t xlnaGainCh[AR5416_MAX_CHAINS]; uint8_t txEndToXpaOff; uint8_t txEndToRxOn; uint8_t txFrameToXpaOn; uint8_t thresh62; uint8_t noiseFloorThreshCh[AR5416_MAX_CHAINS]; uint8_t xpdGain; uint8_t xpd; int8_t iqCalICh[AR5416_MAX_CHAINS]; int8_t iqCalQCh[AR5416_MAX_CHAINS]; uint8_t pdGainOverlap; uint8_t ob; uint8_t db; uint8_t xpaBiasLvl; uint8_t pwrDecreaseFor2Chain; uint8_t pwrDecreaseFor3Chain; uint8_t txFrameToDataStart; uint8_t txFrameToPaOn; uint8_t ht40PowerIncForPdadc; uint8_t bswAtten[AR5416_MAX_CHAINS]; uint8_t bswMargin[AR5416_MAX_CHAINS]; uint8_t swSettleHt40; uint8_t futureModal[22]; struct spurChanStruct spurChans[AR5416_EEPROM_MODAL_SPURS]; } __packed; struct calDataPerFreq { uint8_t pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; uint8_t vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; } __packed; struct CalTargetPowerLegacy { uint8_t bChannel; uint8_t tPow2x[4]; } __packed; struct CalTargetPowerHt { uint8_t bChannel; uint8_t tPow2x[8]; } __packed; struct CalCtlEdges { uint8_t bChannel; uint8_t tPowerFlag; } __packed; struct CalCtlData { struct CalCtlEdges ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; } __packed; struct ar5416eeprom { struct BaseEepHeader baseEepHeader; uint8_t custData[64]; struct ModalEepHeader modalHeader[2]; uint8_t calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; uint8_t calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; struct calDataPerFreq calPierData5G[AR5416_MAX_CHAINS] [AR5416_NUM_5G_CAL_PIERS]; struct calDataPerFreq calPierData2G[AR5416_MAX_CHAINS] [AR5416_NUM_2G_CAL_PIERS]; struct CalTargetPowerLegacy calTPow5G[AR5416_NUM_5G_20_TARGET_POWERS]; struct CalTargetPowerHt calTPow5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; struct CalTargetPowerHt calTPow5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; struct CalTargetPowerLegacy calTPowCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; struct CalTargetPowerLegacy calTPow2G[AR5416_NUM_2G_20_TARGET_POWERS]; struct CalTargetPowerHt calTPow2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; struct CalTargetPowerHt calTPow2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; uint8_t ctlIndex[AR5416_NUM_CTLS]; struct CalCtlData ctlData[AR5416_NUM_CTLS]; uint8_t padding; } __packed; #define OTUS_NUM_CHAINS 2 #define OTUS_UID(aid) (IEEE80211_AID(aid) + 4) #define OTUS_MAX_TXCMDSZ 64 #define OTUS_RXBUFSZ (8 * 1024) /* Bumped for later A-MSDU and legacy fast-frames TX support */ #define OTUS_TXBUFSZ (8 * 1024) /* Default EDCA parameters for when QoS is disabled. */ static const struct wmeParams otus_edca_def[WME_NUM_AC] = { { 4, 10, 3, 0 }, { 4, 10, 7, 0 }, { 3, 4, 2, 94 }, { 2, 3, 2, 47 } }; #define OTUS_RIDX_CCK1 0 #define OTUS_RIDX_OFDM6 4 #define OTUS_RIDX_OFDM24 8 #define OTUS_RIDX_MAX 11 static const struct otus_rate { uint8_t rate; uint8_t mcs; } otus_rates[] = { { 2, 0x0 }, { 4, 0x1 }, { 11, 0x2 }, { 22, 0x3 }, { 12, 0xb }, { 18, 0xf }, { 24, 0xa }, { 36, 0xe }, { 48, 0x9 }, { 72, 0xd }, { 96, 0x8 }, { 108, 0xc } }; struct otus_rx_radiotap_header { struct ieee80211_radiotap_header wr_ihdr; uint8_t wr_flags; uint8_t wr_rate; uint16_t wr_chan_freq; uint16_t wr_chan_flags; uint8_t wr_antsignal; } __packed; #define OTUS_RX_RADIOTAP_PRESENT \ (1 << IEEE80211_RADIOTAP_FLAGS | \ 1 << IEEE80211_RADIOTAP_RATE | \ 1 << IEEE80211_RADIOTAP_CHANNEL | \ 1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL) struct otus_tx_radiotap_header { struct ieee80211_radiotap_header wt_ihdr; uint8_t wt_flags; uint8_t wt_rate; uint16_t wt_chan_freq; uint16_t wt_chan_flags; } __packed; #define OTUS_TX_RADIOTAP_PRESENT \ (1 << IEEE80211_RADIOTAP_FLAGS | \ 1 << IEEE80211_RADIOTAP_RATE | \ 1 << IEEE80211_RADIOTAP_CHANNEL) struct otus_softc; /* Firmware commands */ struct otus_tx_cmd { uint8_t *buf; uint16_t buflen; void *odata; uint16_t odatalen; uint16_t token; STAILQ_ENTRY(otus_tx_cmd) next_cmd; }; /* TX, RX buffers */ struct otus_data { struct otus_softc *sc; uint8_t *buf; uint16_t buflen; struct mbuf *m; struct ieee80211_node *ni; STAILQ_ENTRY(otus_data) next; }; struct otus_node { struct ieee80211_node ni; uint64_t tx_done; uint64_t tx_err; uint64_t tx_retries; }; #define OTUS_CONFIG_INDEX 0 #define OTUS_IFACE_INDEX 0 /* * The carl9170 firmware has the following specification: * * 0 - USB control * 1 - TX * 2 - RX * 3 - IRQ * 4 - CMD * .. * 10 - end */ enum { OTUS_BULK_TX, OTUS_BULK_RX, OTUS_BULK_IRQ, OTUS_BULK_CMD, OTUS_N_XFER }; struct otus_vap { struct ieee80211vap vap; int (*newstate)(struct ieee80211vap *, enum ieee80211_state, int); }; #define OTUS_VAP(vap) ((struct otus_vap *)(vap)) #define OTUS_NODE(ni) ((struct otus_node *)(ni)) #define OTUS_LOCK(sc) mtx_lock(&(sc)->sc_mtx) #define OTUS_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) #define OTUS_LOCK_ASSERT(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) #define OTUS_UNLOCK_ASSERT(sc) mtx_assert(&(sc)->sc_mtx, MA_NOTOWNED) /* XXX the TX/RX endpoint dump says it's 0x200, (512)? */ #define OTUS_MAX_TXSZ 512 #define OTUS_MAX_RXSZ 512 /* intr/cmd endpoint dump says 0x40 */ #define OTUS_MAX_CTRLSZ 64 #define OTUS_CMD_LIST_COUNT 32 #define OTUS_RX_LIST_COUNT 128 #define OTUS_TX_LIST_COUNT 32 struct otus_softc { struct ieee80211com sc_ic; struct mbufq sc_snd; device_t sc_dev; struct usb_device *sc_udev; int (*sc_newstate)(struct ieee80211com *, enum ieee80211_state, int); void (*sc_led_newstate)(struct otus_softc *); struct usbd_interface *sc_iface; struct mtx sc_mtx; struct ar5416eeprom eeprom; uint8_t capflags; uint8_t rxmask; uint8_t txmask; int sc_running:1, sc_calibrating:1, sc_scanning:1; int sc_if_flags; int sc_tx_timer; int fixed_ridx; int bb_reset; struct ieee80211_channel *sc_curchan; struct task tx_task; struct task wme_update_task; struct timeout_task scan_to; struct timeout_task calib_to; /* register batch writes */ int write_idx; uint32_t led_state; /* current firmware message serial / token number */ int token; /* current noisefloor, from SET_FREQUENCY */ int sc_nf[OTUS_NUM_CHAINS]; /* How many pending, active transmit frames */ int sc_tx_n_pending; int sc_tx_n_active; const uint32_t *phy_vals; struct { uint32_t reg; uint32_t val; } __packed write_buf[AR_MAX_WRITE_IDX + 1]; struct otus_data sc_rx[OTUS_RX_LIST_COUNT]; struct otus_data sc_tx[OTUS_TX_LIST_COUNT]; struct otus_tx_cmd sc_cmd[OTUS_CMD_LIST_COUNT]; struct usb_xfer *sc_xfer[OTUS_N_XFER]; STAILQ_HEAD(, otus_data) sc_rx_active; STAILQ_HEAD(, otus_data) sc_rx_inactive; STAILQ_HEAD(, otus_data) sc_tx_active[OTUS_N_XFER]; STAILQ_HEAD(, otus_data) sc_tx_inactive; STAILQ_HEAD(, otus_data) sc_tx_pending[OTUS_N_XFER]; STAILQ_HEAD(, otus_tx_cmd) sc_cmd_active; STAILQ_HEAD(, otus_tx_cmd) sc_cmd_inactive; STAILQ_HEAD(, otus_tx_cmd) sc_cmd_pending; STAILQ_HEAD(, otus_tx_cmd) sc_cmd_waiting; union { struct otus_rx_radiotap_header th; uint8_t pad[64]; } sc_rxtapu; #define sc_rxtap sc_rxtapu.th - int sc_rxtap_len; union { struct otus_tx_radiotap_header th; uint8_t pad[64]; } sc_txtapu; #define sc_txtap sc_txtapu.th - int sc_txtap_len; }; #endif /* __IF_OTUSREG_H__ */ Index: head/sys/dev/ral/rt2560var.h =================================================================== --- head/sys/dev/ral/rt2560var.h (revision 289167) +++ head/sys/dev/ral/rt2560var.h (revision 289168) @@ -1,166 +1,164 @@ /* $FreeBSD$ */ /*- * Copyright (c) 2005, 2006 * Damien Bergamini * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ struct rt2560_rx_radiotap_header { struct ieee80211_radiotap_header wr_ihdr; uint64_t wr_tsf; uint8_t wr_flags; uint8_t wr_rate; uint16_t wr_chan_freq; uint16_t wr_chan_flags; int8_t wr_antsignal; int8_t wr_antnoise; uint8_t wr_antenna; }; #define RT2560_RX_RADIOTAP_PRESENT \ ((1 << IEEE80211_RADIOTAP_TSFT) | \ (1 << IEEE80211_RADIOTAP_FLAGS) | \ (1 << IEEE80211_RADIOTAP_RATE) | \ (1 << IEEE80211_RADIOTAP_CHANNEL) | \ (1 << IEEE80211_RADIOTAP_ANTENNA) | \ (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE)) struct rt2560_tx_radiotap_header { struct ieee80211_radiotap_header wt_ihdr; uint8_t wt_flags; uint8_t wt_rate; uint16_t wt_chan_freq; uint16_t wt_chan_flags; uint8_t wt_antenna; }; #define RT2560_TX_RADIOTAP_PRESENT \ ((1 << IEEE80211_RADIOTAP_FLAGS) | \ (1 << IEEE80211_RADIOTAP_RATE) | \ (1 << IEEE80211_RADIOTAP_CHANNEL) | \ (1 << IEEE80211_RADIOTAP_ANTENNA)) struct rt2560_tx_data { bus_dmamap_t map; struct mbuf *m; struct ieee80211_node *ni; uint8_t rix; int8_t rssi; }; struct rt2560_tx_ring { bus_dma_tag_t desc_dmat; bus_dma_tag_t data_dmat; bus_dmamap_t desc_map; bus_addr_t physaddr; struct rt2560_tx_desc *desc; struct rt2560_tx_data *data; int count; int queued; int cur; int next; int cur_encrypt; int next_encrypt; }; struct rt2560_rx_data { bus_dmamap_t map; struct mbuf *m; int drop; }; struct rt2560_rx_ring { bus_dma_tag_t desc_dmat; bus_dma_tag_t data_dmat; bus_dmamap_t desc_map; bus_addr_t physaddr; struct rt2560_rx_desc *desc; struct rt2560_rx_data *data; int count; int cur; int next; int cur_decrypt; }; struct rt2560_vap { struct ieee80211vap ral_vap; int (*ral_newstate)(struct ieee80211vap *, enum ieee80211_state, int); }; #define RT2560_VAP(vap) ((struct rt2560_vap *)(vap)) struct rt2560_softc { struct ieee80211com sc_ic; struct mtx sc_mtx; struct mbufq sc_snd; device_t sc_dev; bus_space_tag_t sc_st; bus_space_handle_t sc_sh; struct callout watchdog_ch; int sc_tx_timer; int sc_invalid; int sc_debug; /* * The same in both up to here * ------------------------------------------------ */ uint32_t asic_rev; uint32_t eeprom_rev; uint8_t rf_rev; uint8_t rssi_corr; struct rt2560_tx_ring txq; struct rt2560_tx_ring prioq; struct rt2560_tx_ring atimq; struct rt2560_tx_ring bcnq; struct rt2560_rx_ring rxq; uint32_t rf_regs[4]; uint8_t txpow[14]; struct { uint8_t reg; uint8_t val; } bbp_prom[16]; int led_mode; int hw_radio; int rx_ant; int tx_ant; int nb_ant; struct rt2560_rx_radiotap_header sc_rxtap; - int sc_rxtap_len; - struct rt2560_tx_radiotap_header sc_txtap; - int sc_txtap_len; + #define RT2560_F_INPUT_RUNNING 0x1 #define RT2560_F_RUNNING 0x2 int sc_flags; }; int rt2560_attach(device_t, int); int rt2560_detach(void *); void rt2560_stop(void *); void rt2560_resume(void *); void rt2560_intr(void *); #define RAL_LOCK(sc) mtx_lock(&(sc)->sc_mtx) #define RAL_LOCK_ASSERT(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) #define RAL_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) Index: head/sys/dev/ral/rt2661var.h =================================================================== --- head/sys/dev/ral/rt2661var.h (revision 289167) +++ head/sys/dev/ral/rt2661var.h (revision 289168) @@ -1,174 +1,172 @@ /* $FreeBSD$ */ /*- * Copyright (c) 2005 * Damien Bergamini * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ struct rt2661_rx_radiotap_header { struct ieee80211_radiotap_header wr_ihdr; uint64_t wr_tsf; uint8_t wr_flags; uint8_t wr_rate; uint16_t wr_chan_freq; uint16_t wr_chan_flags; int8_t wr_antsignal; int8_t wr_antnoise; } __packed; #define RT2661_RX_RADIOTAP_PRESENT \ ((1 << IEEE80211_RADIOTAP_TSFT) | \ (1 << IEEE80211_RADIOTAP_FLAGS) | \ (1 << IEEE80211_RADIOTAP_RATE) | \ (1 << IEEE80211_RADIOTAP_CHANNEL) | \ (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE)) struct rt2661_tx_radiotap_header { struct ieee80211_radiotap_header wt_ihdr; uint8_t wt_flags; uint8_t wt_rate; uint16_t wt_chan_freq; uint16_t wt_chan_flags; } __packed; #define RT2661_TX_RADIOTAP_PRESENT \ ((1 << IEEE80211_RADIOTAP_FLAGS) | \ (1 << IEEE80211_RADIOTAP_RATE) | \ (1 << IEEE80211_RADIOTAP_CHANNEL)) struct rt2661_tx_data { bus_dmamap_t map; struct mbuf *m; struct ieee80211_node *ni; uint8_t rix; int8_t rssi; }; struct rt2661_tx_ring { bus_dma_tag_t desc_dmat; bus_dma_tag_t data_dmat; bus_dmamap_t desc_map; bus_addr_t physaddr; struct rt2661_tx_desc *desc; struct rt2661_tx_data *data; int count; int queued; int cur; int next; int stat; }; struct rt2661_rx_data { bus_dmamap_t map; struct mbuf *m; }; struct rt2661_rx_ring { bus_dma_tag_t desc_dmat; bus_dma_tag_t data_dmat; bus_dmamap_t desc_map; bus_addr_t physaddr; struct rt2661_rx_desc *desc; struct rt2661_rx_data *data; int count; int cur; int next; }; struct rt2661_vap { struct ieee80211vap ral_vap; int (*ral_newstate)(struct ieee80211vap *, enum ieee80211_state, int); }; #define RT2661_VAP(vap) ((struct rt2661_vap *)(vap)) struct rt2661_softc { struct ieee80211com sc_ic; struct mtx sc_mtx; struct mbufq sc_snd; device_t sc_dev; bus_space_tag_t sc_st; bus_space_handle_t sc_sh; struct callout watchdog_ch; int sc_tx_timer; int sc_invalid; int sc_debug; /* * The same in both up to here * ------------------------------------------------ */ int sc_flags; #define RAL_FW_LOADED 0x1 #define RAL_INPUT_RUNNING 0x2 #define RAL_RUNNING 0x4 int sc_id; struct ieee80211_channel *sc_curchan; uint8_t rf_rev; uint8_t rfprog; uint8_t rffreq; struct rt2661_tx_ring txq[4]; struct rt2661_tx_ring mgtq; struct rt2661_rx_ring rxq; uint32_t rf_regs[4]; int8_t txpow[38]; struct { uint8_t reg; uint8_t val; } bbp_prom[16]; int hw_radio; int rx_ant; int tx_ant; int nb_ant; int ext_2ghz_lna; int ext_5ghz_lna; int rssi_2ghz_corr; int rssi_5ghz_corr; uint8_t bbp18; uint8_t bbp21; uint8_t bbp22; uint8_t bbp16; uint8_t bbp17; uint8_t bbp64; int dwelltime; struct rt2661_rx_radiotap_header sc_rxtap; - int sc_rxtap_len; struct rt2661_tx_radiotap_header sc_txtap; - int sc_txtap_len; }; int rt2661_attach(device_t, int); int rt2661_detach(void *); void rt2661_shutdown(void *); void rt2661_suspend(void *); void rt2661_resume(void *); void rt2661_intr(void *); #define RAL_LOCK(sc) mtx_lock(&(sc)->sc_mtx) #define RAL_LOCK_ASSERT(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) #define RAL_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) Index: head/sys/dev/ral/rt2860var.h =================================================================== --- head/sys/dev/ral/rt2860var.h (revision 289167) +++ head/sys/dev/ral/rt2860var.h (revision 289168) @@ -1,211 +1,209 @@ /*- * Copyright (c) 2007 Damien Bergamini * Copyright (c) 2012 Bernhard Schmidt * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $OpenBSD: rt2860var.h,v 1.20 2010/09/07 16:21:42 deraadt Exp $ * $FreeBSD$ */ #define RT2860_TX_RING_COUNT 64 #define RT2860_RX_RING_COUNT 128 #define RT2860_TX_POOL_COUNT (RT2860_TX_RING_COUNT * 2) #define RT2860_MAX_SCATTER ((RT2860_TX_RING_COUNT * 2) - 1) /* HW supports up to 255 STAs */ #define RT2860_WCID_MAX 254 #define RT2860_AID2WCID(aid) ((aid) & 0xff) struct rt2860_rx_radiotap_header { struct ieee80211_radiotap_header wr_ihdr; uint64_t wr_tsf; uint8_t wr_flags; uint8_t wr_rate; uint16_t wr_chan_freq; uint16_t wr_chan_flags; uint8_t wr_antenna; int8_t wr_antsignal; int8_t wr_antnoise; } __packed; #define RT2860_RX_RADIOTAP_PRESENT \ ((1 << IEEE80211_RADIOTAP_TSFT) | \ (1 << IEEE80211_RADIOTAP_FLAGS) | \ (1 << IEEE80211_RADIOTAP_RATE) | \ (1 << IEEE80211_RADIOTAP_CHANNEL) | \ (1 << IEEE80211_RADIOTAP_ANTENNA) | \ (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE)) struct rt2860_tx_radiotap_header { struct ieee80211_radiotap_header wt_ihdr; uint8_t wt_flags; uint8_t wt_rate; uint16_t wt_chan_freq; uint16_t wt_chan_flags; } __packed; #define RT2860_TX_RADIOTAP_PRESENT \ ((1 << IEEE80211_RADIOTAP_FLAGS) | \ (1 << IEEE80211_RADIOTAP_RATE) | \ (1 << IEEE80211_RADIOTAP_CHANNEL)) struct rt2860_tx_data { struct rt2860_txwi *txwi; struct mbuf *m; struct ieee80211_node *ni; bus_dmamap_t map; bus_addr_t paddr; SLIST_ENTRY(rt2860_tx_data) next; }; struct rt2860_tx_ring { struct rt2860_txd *txd; bus_addr_t paddr; bus_dma_tag_t desc_dmat; bus_dmamap_t desc_map; bus_dma_segment_t seg; struct rt2860_tx_data *data[RT2860_TX_RING_COUNT]; int cur; int next; int queued; }; struct rt2860_rx_data { struct mbuf *m; bus_dmamap_t map; }; struct rt2860_rx_ring { struct rt2860_rxd *rxd; bus_addr_t paddr; bus_dma_tag_t desc_dmat; bus_dmamap_t desc_map; bus_dma_tag_t data_dmat; bus_dma_segment_t seg; unsigned int cur; /* must be unsigned */ struct rt2860_rx_data data[RT2860_RX_RING_COUNT]; }; struct rt2860_node { struct ieee80211_node ni; uint8_t wcid; uint8_t ridx[IEEE80211_RATE_MAXSIZE]; uint8_t ctl_ridx[IEEE80211_RATE_MAXSIZE]; }; struct rt2860_vap { struct ieee80211vap ral_vap; int (*ral_newstate)(struct ieee80211vap *, enum ieee80211_state, int); }; #define RT2860_VAP(vap) ((struct rt2860_vap *)(vap)) struct rt2860_softc { struct ieee80211com sc_ic; struct mbufq sc_snd; struct mtx sc_mtx; device_t sc_dev; bus_space_tag_t sc_st; bus_space_handle_t sc_sh; struct callout watchdog_ch; int sc_invalid; int sc_debug; /* * The same in both up to here * ------------------------------------------------ */ uint16_t (*sc_srom_read)(struct rt2860_softc *, uint16_t); void (*sc_node_free)(struct ieee80211_node *); int sc_flags; #define RT2860_ENABLED (1 << 0) #define RT2860_ADVANCED_PS (1 << 1) #define RT2860_PCIE (1 << 2) #define RT2860_RUNNNING (1 << 3) struct ieee80211_node *wcid2ni[RT2860_WCID_MAX]; struct rt2860_tx_ring txq[6]; struct rt2860_rx_ring rxq; SLIST_HEAD(, rt2860_tx_data) data_pool; struct rt2860_tx_data data[RT2860_TX_POOL_COUNT]; bus_dma_tag_t txwi_dmat; bus_dmamap_t txwi_map; bus_dma_segment_t txwi_seg; caddr_t txwi_vaddr; int sc_tx_timer; int mgtqid; uint8_t qfullmsk; uint16_t mac_ver; uint16_t mac_rev; uint8_t rf_rev; uint8_t freq; uint8_t ntxchains; uint8_t nrxchains; uint8_t pslevel; int8_t txpow1[54]; int8_t txpow2[54]; int8_t rssi_2ghz[3]; int8_t rssi_5ghz[3]; uint8_t lna[4]; uint8_t rf24_20mhz; uint8_t rf24_40mhz; uint8_t patch_dac; uint8_t rfswitch; uint8_t ext_2ghz_lna; uint8_t ext_5ghz_lna; uint8_t calib_2ghz; uint8_t calib_5ghz; uint8_t txmixgain_2ghz; uint8_t txmixgain_5ghz; uint8_t tssi_2ghz[9]; uint8_t tssi_5ghz[9]; uint8_t step_2ghz; uint8_t step_5ghz; struct { uint8_t reg; uint8_t val; } bbp[8], rf[10]; uint8_t leds; uint16_t led[3]; uint32_t txpow20mhz[5]; uint32_t txpow40mhz_2ghz[5]; uint32_t txpow40mhz_5ghz[5]; struct rt2860_rx_radiotap_header sc_rxtap; - int sc_rxtap_len; struct rt2860_tx_radiotap_header sc_txtap; - int sc_txtap_len; }; int rt2860_attach(device_t, int); int rt2860_detach(void *); void rt2860_shutdown(void *); void rt2860_suspend(void *); void rt2860_resume(void *); void rt2860_intr(void *); #define RAL_LOCK(sc) mtx_lock(&(sc)->sc_mtx) #define RAL_LOCK_ASSERT(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) #define RAL_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) Index: head/sys/dev/usb/wlan/if_rsureg.h =================================================================== --- head/sys/dev/usb/wlan/if_rsureg.h (revision 289167) +++ head/sys/dev/usb/wlan/if_rsureg.h (revision 289168) @@ -1,804 +1,802 @@ /*- * Copyright (c) 2010 Damien Bergamini * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $OpenBSD: if_rsureg.h,v 1.3 2013/04/15 09:23:01 mglocker Exp $ * $FreeBSD$ */ /* USB Requests. */ #define R92S_REQ_REGS 0x05 /* * MAC registers. */ #define R92S_SYSCFG 0x0000 #define R92S_SYS_ISO_CTRL (R92S_SYSCFG + 0x000) #define R92S_SYS_FUNC_EN (R92S_SYSCFG + 0x002) #define R92S_PMC_FSM (R92S_SYSCFG + 0x004) #define R92S_SYS_CLKR (R92S_SYSCFG + 0x008) #define R92S_EE_9346CR (R92S_SYSCFG + 0x00a) #define R92S_AFE_MISC (R92S_SYSCFG + 0x010) #define R92S_SPS0_CTRL (R92S_SYSCFG + 0x011) #define R92S_SPS1_CTRL (R92S_SYSCFG + 0x018) #define R92S_RF_CTRL (R92S_SYSCFG + 0x01f) #define R92S_LDOA15_CTRL (R92S_SYSCFG + 0x020) #define R92S_LDOV12D_CTRL (R92S_SYSCFG + 0x021) #define R92S_AFE_XTAL_CTRL (R92S_SYSCFG + 0x026) #define R92S_AFE_PLL_CTRL (R92S_SYSCFG + 0x028) #define R92S_EFUSE_CTRL (R92S_SYSCFG + 0x030) #define R92S_EFUSE_TEST (R92S_SYSCFG + 0x034) #define R92S_EFUSE_CLK_CTRL (R92S_SYSCFG + 0x2f8) #define R92S_CMDCTRL 0x0040 #define R92S_CR (R92S_CMDCTRL + 0x000) #define R92S_TCR (R92S_CMDCTRL + 0x004) #define R92S_RCR (R92S_CMDCTRL + 0x008) #define R92S_MACIDSETTING 0x0050 #define R92S_MACID (R92S_MACIDSETTING + 0x000) #define R92S_GP 0x01e0 #define R92S_GPIO_CTRL (R92S_GP + 0x00c) #define R92S_GPIO_IO_SEL (R92S_GP + 0x00e) #define R92S_MAC_PINMUX_CTRL (R92S_GP + 0x011) #define R92S_IOCMD_CTRL 0x0370 #define R92S_IOCMD_DATA 0x0374 #define R92S_USB_HRPWM 0xfe58 /* Bits for R92S_SYS_FUNC_EN. */ #define R92S_FEN_CPUEN 0x0400 /* Bits for R92S_PMC_FSM. */ #define R92S_PMC_FSM_CUT_M 0x000f8000 #define R92S_PMC_FSM_CUT_S 15 /* Bits for R92S_SYS_CLKR. */ #define R92S_SYS_CLKSEL 0x0001 #define R92S_SYS_PS_CLKSEL 0x0002 #define R92S_SYS_CPU_CLKSEL 0x0004 #define R92S_MAC_CLK_EN 0x0800 #define R92S_SYS_CLK_EN 0x1000 #define R92S_SWHW_SEL 0x4000 #define R92S_FWHW_SEL 0x8000 /* Bits for R92S_EE_9346CR. */ #define R92S_9356SEL 0x10 #define R92S_EEPROM_EN 0x20 /* Bits for R92S_AFE_MISC. */ #define R92S_AFE_MISC_BGEN 0x01 #define R92S_AFE_MISC_MBEN 0x02 #define R92S_AFE_MISC_I32_EN 0x08 /* Bits for R92S_SPS1_CTRL. */ #define R92S_SPS1_LDEN 0x01 #define R92S_SPS1_SWEN 0x02 /* Bits for R92S_LDOA15_CTRL. */ #define R92S_LDA15_EN 0x01 /* Bits for R92S_LDOV12D_CTRL. */ #define R92S_LDV12_EN 0x01 /* Bits for R92C_EFUSE_CTRL. */ #define R92S_EFUSE_CTRL_DATA_M 0x000000ff #define R92S_EFUSE_CTRL_DATA_S 0 #define R92S_EFUSE_CTRL_ADDR_M 0x0003ff00 #define R92S_EFUSE_CTRL_ADDR_S 8 #define R92S_EFUSE_CTRL_VALID 0x80000000 /* Bits for R92S_CR. */ #define R92S_CR_TXDMA_EN 0x10 /* Bits for R92S_TCR. */ #define R92S_TCR_IMEM_CODE_DONE 0x01 #define R92S_TCR_IMEM_CHK_RPT 0x02 #define R92S_TCR_EMEM_CODE_DONE 0x04 #define R92S_TCR_EMEM_CHK_RPT 0x08 #define R92S_TCR_DMEM_CODE_DONE 0x10 #define R92S_TCR_IMEM_RDY 0x20 #define R92S_TCR_FWRDY 0x80 /* Bits for R92S_GPIO_IO_SEL. */ #define R92S_GPIO_WPS 0x10 /* Bits for R92S_MAC_PINMUX_CTRL. */ #define R92S_GPIOSEL_GPIO_M 0x03 #define R92S_GPIOSEL_GPIO_S 0 #define R92S_GPIOSEL_GPIO_JTAG 0 #define R92S_GPIOSEL_GPIO_PHYDBG 1 #define R92S_GPIOSEL_GPIO_BT 2 #define R92S_GPIOSEL_GPIO_WLANDBG 3 #define R92S_GPIOMUX_EN 0x08 /* Bits for R92S_IOCMD_CTRL. */ #define R92S_IOCMD_CLASS_M 0xff000000 #define R92S_IOCMD_CLASS_S 24 #define R92S_IOCMD_CLASS_BB_RF 0xf0 #define R92S_IOCMD_VALUE_M 0x00ffff00 #define R92S_IOCMD_VALUE_S 8 #define R92S_IOCMD_INDEX_M 0x000000ff #define R92S_IOCMD_INDEX_S 0 #define R92S_IOCMD_INDEX_BB_READ 0 #define R92S_IOCMD_INDEX_BB_WRITE 1 #define R92S_IOCMD_INDEX_RF_READ 2 #define R92S_IOCMD_INDEX_RF_WRITE 3 /* Bits for R92S_USB_HRPWM. */ #define R92S_USB_HRPWM_PS_ALL_ON 0x04 #define R92S_USB_HRPWM_PS_ST_ACTIVE 0x08 /* * Macros to access subfields in registers. */ /* Mask and Shift (getter). */ #define MS(val, field) \ (((val) & field##_M) >> field##_S) /* Shift and Mask (setter). */ #define SM(field, val) \ (((val) << field##_S) & field##_M) /* Rewrite. */ #define RW(var, field, val) \ (((var) & ~field##_M) | SM(field, val)) /* * ROM field with RF config. */ enum { RTL8712_RFCONFIG_1T = 0x10, RTL8712_RFCONFIG_2T = 0x20, RTL8712_RFCONFIG_1R = 0x01, RTL8712_RFCONFIG_2R = 0x02, RTL8712_RFCONFIG_1T1R = 0x11, RTL8712_RFCONFIG_1T2R = 0x12, RTL8712_RFCONFIG_TURBO = 0x92, RTL8712_RFCONFIG_2T2R = 0x22 }; /* * Firmware image header. */ struct r92s_fw_priv { /* QWORD0 */ uint16_t signature; uint8_t hci_sel; #define R92S_HCI_SEL_PCIE 0x01 #define R92S_HCI_SEL_USB 0x02 #define R92S_HCI_SEL_SDIO 0x04 #define R92S_HCI_SEL_8172 0x10 #define R92S_HCI_SEL_AP 0x80 uint8_t chip_version; uint16_t custid; uint8_t rf_config; //0x11: 1T1R, 0x12: 1T2R, 0x92: 1T2R turbo, 0x22: 2T2R uint8_t nendpoints; /* QWORD1 */ uint32_t regulatory; uint8_t rfintfs; uint8_t def_nettype; uint8_t turbo_mode; uint8_t lowpower_mode; /* QWORD2 */ uint8_t lbk_mode; uint8_t mp_mode; uint8_t vcs_type; #define R92S_VCS_TYPE_DISABLE 0 #define R92S_VCS_TYPE_ENABLE 1 #define R92S_VCS_TYPE_AUTO 2 uint8_t vcs_mode; #define R92S_VCS_MODE_NONE 0 #define R92S_VCS_MODE_RTS_CTS 1 #define R92S_VCS_MODE_CTS2SELF 2 uint32_t reserved1; /* QWORD3 */ uint8_t qos_en; uint8_t bw40_en; uint8_t amsdu2ampdu_en; uint8_t ampdu_en; uint8_t rc_offload; uint8_t agg_offload; uint16_t reserved2; /* QWORD4 */ uint8_t beacon_offload; uint8_t mlme_offload; uint8_t hwpc_offload; uint8_t tcpcsum_offload; uint8_t tcp_offload; uint8_t ps_offload; uint8_t wwlan_offload; uint8_t reserved3; /* QWORD5 */ uint16_t tcp_tx_len; uint16_t tcp_rx_len; uint32_t reserved4; } __packed; struct r92s_fw_hdr { uint16_t signature; uint16_t version; uint32_t dmemsz; uint32_t imemsz; uint32_t sramsz; uint32_t privsz; uint16_t efuse_addr; uint16_t h2c_resp_addr; uint32_t svnrev; uint8_t month; uint8_t day; uint8_t hour; uint8_t minute; struct r92s_fw_priv priv; } __packed; /* Structure for FW commands and FW events notifications. */ struct r92s_fw_cmd_hdr { uint16_t len; uint8_t code; uint8_t seq; #define R92S_FW_CMD_MORE 0x80 uint32_t reserved; } __packed; /* FW commands codes. */ #define R92S_CMD_READ_MACREG 0 #define R92S_CMD_WRITE_MACREG 1 #define R92S_CMD_READ_BBREG 2 #define R92S_CMD_WRITE_BBREG 3 #define R92S_CMD_READ_RFREG 4 #define R92S_CMD_WRITE_RFREG 5 #define R92S_CMD_READ_EEPROM 6 #define R92S_CMD_WRITE_EEPROM 7 #define R92S_CMD_READ_EFUSE 8 #define R92S_CMD_WRITE_EFUSE 9 #define R92S_CMD_READ_CAM 10 #define R92S_CMD_WRITE_CAM 11 #define R92S_CMD_SET_BCNITV 12 #define R92S_CMD_SET_MBIDCFG 13 #define R92S_CMD_JOIN_BSS 14 #define R92S_CMD_DISCONNECT 15 #define R92S_CMD_CREATE_BSS 16 #define R92S_CMD_SET_OPMODE 17 #define R92S_CMD_SITE_SURVEY 18 #define R92S_CMD_SET_AUTH 19 #define R92S_CMD_SET_KEY 20 #define R92S_CMD_SET_STA_KEY 21 #define R92S_CMD_SET_ASSOC_STA 22 #define R92S_CMD_DEL_ASSOC_STA 23 #define R92S_CMD_SET_STAPWRSTATE 24 #define R92S_CMD_SET_BASIC_RATE 25 #define R92S_CMD_GET_BASIC_RATE 26 #define R92S_CMD_SET_DATA_RATE 27 #define R92S_CMD_GET_DATA_RATE 28 #define R92S_CMD_SET_PHY_INFO 29 #define R92S_CMD_GET_PHY_INFO 30 #define R92S_CMD_SET_PHY 31 #define R92S_CMD_GET_PHY 32 #define R92S_CMD_READ_RSSI 33 #define R92S_CMD_READ_GAIN 34 #define R92S_CMD_SET_ATIM 35 #define R92S_CMD_SET_PWR_MODE 36 #define R92S_CMD_JOIN_BSS_RPT 37 #define R92S_CMD_SET_RA_TABLE 38 #define R92S_CMD_GET_RA_TABLE 39 #define R92S_CMD_GET_CCX_REPORT 40 #define R92S_CMD_GET_DTM_REPORT 41 #define R92S_CMD_GET_TXRATE_STATS 42 #define R92S_CMD_SET_USB_SUSPEND 43 #define R92S_CMD_SET_H2C_LBK 44 #define R92S_CMD_ADDBA_REQ 45 #define R92S_CMD_SET_CHANNEL 46 #define R92S_CMD_SET_TXPOWER 47 #define R92S_CMD_SWITCH_ANTENNA 48 #define R92S_CMD_SET_CRYSTAL_CAL 49 #define R92S_CMD_SET_SINGLE_CARRIER_TX 50 #define R92S_CMD_SET_SINGLE_TONE_TX 51 #define R92S_CMD_SET_CARRIER_SUPPR_TX 52 #define R92S_CMD_SET_CONTINUOUS_TX 53 #define R92S_CMD_SWITCH_BANDWIDTH 54 #define R92S_CMD_TX_BEACON 55 #define R92S_CMD_SET_POWER_TRACKING 56 #define R92S_CMD_AMSDU_TO_AMPDU 57 #define R92S_CMD_SET_MAC_ADDRESS 58 #define R92S_CMD_GET_H2C_LBK 59 #define R92S_CMD_SET_PBREQ_IE 60 #define R92S_CMD_SET_ASSOCREQ_IE 61 #define R92S_CMD_SET_PBRESP_IE 62 #define R92S_CMD_SET_ASSOCRESP_IE 63 #define R92S_CMD_GET_CURDATARATE 64 #define R92S_CMD_GET_TXRETRY_CNT 65 #define R92S_CMD_GET_RXRETRY_CNT 66 #define R92S_CMD_GET_BCNOK_CNT 67 #define R92S_CMD_GET_BCNERR_CNT 68 #define R92S_CMD_GET_CURTXPWR_LEVEL 69 #define R92S_CMD_SET_DIG 70 #define R92S_CMD_SET_RA 71 #define R92S_CMD_SET_PT 72 #define R92S_CMD_READ_TSSI 73 /* FW events notifications codes. */ #define R92S_EVT_READ_MACREG 0 #define R92S_EVT_READ_BBREG 1 #define R92S_EVT_READ_RFREG 2 #define R92S_EVT_READ_EEPROM 3 #define R92S_EVT_READ_EFUSE 4 #define R92S_EVT_READ_CAM 5 #define R92S_EVT_GET_BASICRATE 6 #define R92S_EVT_GET_DATARATE 7 #define R92S_EVT_SURVEY 8 #define R92S_EVT_SURVEY_DONE 9 #define R92S_EVT_JOIN_BSS 10 #define R92S_EVT_ADD_STA 11 #define R92S_EVT_DEL_STA 12 #define R92S_EVT_ATIM_DONE 13 #define R92S_EVT_TX_REPORT 14 #define R92S_EVT_CCX_REPORT 15 #define R92S_EVT_DTM_REPORT 16 #define R92S_EVT_TXRATE_STATS 17 #define R92S_EVT_C2H_LBK 18 #define R92S_EVT_FWDBG 19 #define R92S_EVT_C2H_FEEDBACK 20 #define R92S_EVT_ADDBA 21 #define R92S_EVT_C2H_BCN 22 #define R92S_EVT_PWR_STATE 23 #define R92S_EVT_WPS_PBC 24 #define R92S_EVT_ADDBA_REQ_REPORT 25 /* Structure for R92S_CMD_SITE_SURVEY. */ struct r92s_fw_cmd_sitesurvey { uint32_t active; uint32_t limit; uint32_t ssidlen; uint8_t ssid[32 + 1]; } __packed; /* Structure for R92S_CMD_SET_AUTH. */ struct r92s_fw_cmd_auth { uint8_t mode; #define R92S_AUTHMODE_OPEN 0 #define R92S_AUTHMODE_SHARED 1 #define R92S_AUTHMODE_WPA 2 uint8_t dot1x; } __packed; /* Structure for R92S_CMD_SET_KEY. */ struct r92s_fw_cmd_set_key { uint8_t algo; #define R92S_KEY_ALGO_NONE 0 #define R92S_KEY_ALGO_WEP40 1 #define R92S_KEY_ALGO_TKIP 2 #define R92S_KEY_ALGO_TKIP_MMIC 3 #define R92S_KEY_ALGO_AES 4 #define R92S_KEY_ALGO_WEP104 5 uint8_t id; uint8_t grpkey; uint8_t key[16]; } __packed; /* Structures for R92S_EVENT_SURVEY/R92S_CMD_JOIN_BSS. */ /* NDIS_802_11_SSID. */ struct ndis_802_11_ssid { uint32_t ssidlen; uint8_t ssid[32]; } __packed; /* NDIS_802_11_CONFIGURATION_FH. */ struct ndis_802_11_configuration_fh { uint32_t len; uint32_t hoppattern; uint32_t hopset; uint32_t dwelltime; } __packed; /* NDIS_802_11_CONFIGURATION. */ struct ndis_802_11_configuration { uint32_t len; uint32_t bintval; uint32_t atim; uint32_t dsconfig; struct ndis_802_11_configuration_fh fhconfig; } __packed; /* NDIS_WLAN_BSSID_EX. */ struct ndis_wlan_bssid_ex { uint32_t len; uint8_t macaddr[IEEE80211_ADDR_LEN]; uint8_t reserved[2]; struct ndis_802_11_ssid ssid; uint32_t privacy; int32_t rssi; uint32_t networktype; #define NDIS802_11FH 0 #define NDIS802_11DS 1 #define NDIS802_11OFDM5 2 #define NDIS802_11OFDM24 3 #define NDIS802_11AUTOMODE 4 struct ndis_802_11_configuration config; uint32_t inframode; #define NDIS802_11IBSS 0 #define NDIS802_11INFRASTRUCTURE 1 #define NDIS802_11AUTOUNKNOWN 2 #define NDIS802_11MONITOR 3 #define NDIS802_11APMODE 4 uint8_t supprates[16]; uint32_t ieslen; /* Followed by ``ieslen'' bytes. */ } __packed; /* NDIS_802_11_FIXED_IEs. */ struct ndis_802_11_fixed_ies { uint8_t tstamp[8]; uint16_t bintval; uint16_t capabilities; } __packed; /* Structure for R92S_CMD_SET_PWR_MODE. */ struct r92s_set_pwr_mode { uint8_t mode; #define R92S_PS_MODE_ACTIVE 0 #define R92S_PS_MODE_MIN 1 #define R92S_PS_MODE_MAX 2 #define R92S_PS_MODE_DTIM 3 #define R92S_PS_MODE_VOIP 4 #define R92S_PS_MODE_UAPSD_WMM 5 #define R92S_PS_MODE_UAPSD 6 #define R92S_PS_MODE_IBSS 7 #define R92S_PS_MODE_WWLAN 8 #define R92S_PS_MODE_RADIOOFF 9 #define R92S_PS_MODE_DISABLE 10 uint8_t low_traffic_en; uint8_t lpnav_en; uint8_t rf_low_snr_en; uint8_t dps_en; uint8_t bcn_rx_en; uint8_t bcn_pass_cnt; uint8_t bcn_to; uint16_t bcn_itv; uint8_t app_itv; uint8_t awake_bcn_itv; uint8_t smart_ps; uint8_t bcn_pass_time; } __packed; /* Structure for event R92S_EVENT_JOIN_BSS. */ struct r92s_event_join_bss { uint32_t next; uint32_t prev; uint32_t networktype; uint32_t fixed; uint32_t lastscanned; uint32_t associd; uint32_t join_res; struct ndis_wlan_bssid_ex bss; } __packed; #define R92S_MACID_BSS 5 /* Rx MAC descriptor. */ struct r92s_rx_stat { uint32_t rxdw0; #define R92S_RXDW0_PKTLEN_M 0x00003fff #define R92S_RXDW0_PKTLEN_S 0 #define R92S_RXDW0_CRCERR 0x00004000 #define R92S_RXDW0_INFOSZ_M 0x000f0000 #define R92S_RXDW0_INFOSZ_S 16 #define R92S_RXDW0_QOS 0x00800000 #define R92S_RXDW0_SHIFT_M 0x03000000 #define R92S_RXDW0_SHIFT_S 24 #define R92S_RXDW0_DECRYPTED 0x08000000 uint32_t rxdw1; #define R92S_RXDW1_MOREFRAG 0x08000000 uint32_t rxdw2; #define R92S_RXDW2_FRAG_M 0x0000f000 #define R92S_RXDW2_FRAG_S 12 #define R92S_RXDW2_PKTCNT_M 0x00ff0000 #define R92S_RXDW2_PKTCNT_S 16 uint32_t rxdw3; #define R92S_RXDW3_RATE_M 0x0000003f #define R92S_RXDW3_RATE_S 0 #define R92S_RXDW3_TCPCHKRPT 0x00000800 #define R92S_RXDW3_IPCHKRPT 0x00001000 #define R92S_RXDW3_TCPCHKVALID 0x00002000 #define R92S_RXDW3_HTC 0x00004000 uint32_t rxdw4; uint32_t rxdw5; } __packed __aligned(4); /* Rx PHY descriptor. */ struct r92s_rx_phystat { uint32_t phydw0; uint32_t phydw1; uint32_t phydw2; uint32_t phydw3; uint32_t phydw4; uint32_t phydw5; uint32_t phydw6; uint32_t phydw7; } __packed __aligned(4); /* Rx PHY CCK descriptor. */ struct r92s_rx_cck { uint8_t adc_pwdb[4]; uint8_t sq_rpt; uint8_t agc_rpt; } __packed; /* Tx MAC descriptor. */ struct r92s_tx_desc { uint32_t txdw0; #define R92S_TXDW0_PKTLEN_M 0x0000ffff #define R92S_TXDW0_PKTLEN_S 0 #define R92S_TXDW0_OFFSET_M 0x00ff0000 #define R92S_TXDW0_OFFSET_S 16 #define R92S_TXDW0_TYPE_M 0x03000000 #define R92S_TXDW0_TYPE_S 24 #define R92S_TXDW0_LSG 0x04000000 #define R92S_TXDW0_FSG 0x08000000 #define R92S_TXDW0_LINIP 0x10000000 #define R92S_TXDW0_OWN 0x80000000 uint32_t txdw1; #define R92S_TXDW1_MACID_M 0x0000001f #define R92S_TXDW1_MACID_S 0 #define R92S_TXDW1_MOREDATA 0x00000020 #define R92S_TXDW1_MOREFRAG 0x00000040 #define R92S_TXDW1_QSEL_M 0x00001f00 #define R92S_TXDW1_QSEL_S 8 #define R92S_TXDW1_QSEL_BE 0x03 #define R92S_TXDW1_QSEL_H2C 0x1f #define R92S_TXDW1_NONQOS 0x00010000 #define R92S_TXDW1_KEYIDX_M 0x00060000 #define R92S_TXDW1_KEYIDX_S 17 #define R92S_TXDW1_CIPHER_M 0x00c00000 #define R92S_TXDW1_CIPHER_S 22 #define R92S_TXDW1_CIPHER_WEP 1 #define R92S_TXDW1_CIPHER_TKIP 2 #define R92S_TXDW1_CIPHER_AES 3 #define R92S_TXDW1_HWPC 0x80000000 uint32_t txdw2; #define R92S_TXDW2_BMCAST 0x00000080 #define R92S_TXDW2_AGGEN 0x20000000 #define R92S_TXDW2_BK 0x40000000 uint32_t txdw3; #define R92S_TXDW3_SEQ_M 0x0fff0000 #define R92S_TXDW3_SEQ_S 16 #define R92S_TXDW3_FRAG_M 0xf0000000 #define R92S_TXDW3_FRAG_S 28 uint32_t txdw4; #define R92S_TXDW4_TXBW 0x00040000 uint32_t txdw5; #define R92S_TXDW5_DISFB 0x00008000 uint16_t ipchksum; uint16_t tcpchksum; uint16_t txbufsize; uint16_t reserved1; } __packed __aligned(4); struct r92s_add_ba_event { uint8_t mac_addr[IEEE80211_ADDR_LEN]; uint16_t ssn; uint8_t tid; }; struct r92s_add_ba_req { uint32_t tid; }; /* * Driver definitions. */ #define RSU_RX_LIST_COUNT 100 #define RSU_TX_LIST_COUNT 32 #define RSU_HOST_CMD_RING_COUNT 32 #define RSU_RXBUFSZ (8 * 1024) #define RSU_TXBUFSZ \ ((sizeof(struct r92s_tx_desc) + IEEE80211_MAX_LEN + 3) & ~3) #define RSU_TX_TIMEOUT 5000 /* ms */ #define RSU_CMD_TIMEOUT 2000 /* ms */ /* Queue ids (used by soft only). */ #define RSU_QID_BCN 0 #define RSU_QID_MGT 1 #define RSU_QID_BMC 2 #define RSU_QID_VO 3 #define RSU_QID_VI 4 #define RSU_QID_BE 5 #define RSU_QID_BK 6 #define RSU_QID_RXOFF 7 #define RSU_QID_H2C 8 #define RSU_QID_C2H 9 /* Map AC to queue id. */ static const uint8_t rsu_ac2qid[WME_NUM_AC] = { RSU_QID_BE, RSU_QID_BK, RSU_QID_VI, RSU_QID_VO }; /* Pipe index to endpoint address mapping. */ static const uint8_t r92s_epaddr[] = { 0x83, 0x04, 0x06, 0x0d, 0x05, 0x07, 0x89, 0x0a, 0x0b, 0x0c }; /* Queue id to pipe index mapping for 4 endpoints configurations. */ static const uint8_t rsu_qid2idx_4ep[] = { 3, 3, 3, 1, 1, 2, 2, 0, 3, 0 }; /* Queue id to pipe index mapping for 6 endpoints configurations. */ static const uint8_t rsu_qid2idx_6ep[] = { 3, 3, 3, 1, 4, 2, 5, 0, 3, 0 }; /* Queue id to pipe index mapping for 11 endpoints configurations. */ static const uint8_t rsu_qid2idx_11ep[] = { 7, 9, 8, 1, 4, 2, 5, 0, 3, 6 }; struct rsu_rx_radiotap_header { struct ieee80211_radiotap_header wr_ihdr; uint8_t wr_flags; uint8_t wr_rate; uint16_t wr_chan_freq; uint16_t wr_chan_flags; uint8_t wr_dbm_antsignal; } __packed __aligned(8); #define RSU_RX_RADIOTAP_PRESENT \ (1 << IEEE80211_RADIOTAP_FLAGS | \ 1 << IEEE80211_RADIOTAP_RATE | \ 1 << IEEE80211_RADIOTAP_CHANNEL | \ 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) struct rsu_tx_radiotap_header { struct ieee80211_radiotap_header wt_ihdr; uint8_t wt_flags; uint16_t wt_chan_freq; uint16_t wt_chan_flags; } __packed __aligned(8); #define RSU_TX_RADIOTAP_PRESENT \ (1 << IEEE80211_RADIOTAP_FLAGS | \ 1 << IEEE80211_RADIOTAP_CHANNEL) struct rsu_softc; struct rsu_host_cmd { void (*cb)(struct rsu_softc *, void *); uint8_t data[256]; }; struct rsu_cmd_newstate { enum ieee80211_state state; int arg; }; struct rsu_cmd_key { struct ieee80211_key key; }; struct rsu_host_cmd_ring { struct rsu_host_cmd cmd[RSU_HOST_CMD_RING_COUNT]; int cur; int next; int queued; }; enum { RSU_BULK_RX, RSU_BULK_TX_BE_BK, /* = WME_AC_BE/BK */ RSU_BULK_TX_VI_VO, /* = WME_AC_VI/VO */ RSU_BULK_TX_H2C, /* H2C */ RSU_N_TRANSFER, }; struct rsu_data { struct rsu_softc *sc; uint8_t *buf; uint16_t buflen; struct mbuf *m; struct ieee80211_node *ni; STAILQ_ENTRY(rsu_data) next; }; struct rsu_vap { struct ieee80211vap vap; int (*newstate)(struct ieee80211vap *, enum ieee80211_state, int); }; #define RSU_VAP(vap) ((struct rsu_vap *)(vap)) #define RSU_LOCK(sc) mtx_lock(&(sc)->sc_mtx) #define RSU_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) #define RSU_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) struct rsu_softc { struct ieee80211com sc_ic; struct mbufq sc_snd; device_t sc_dev; struct usb_device *sc_udev; int (*sc_newstate)(struct ieee80211com *, enum ieee80211_state, int); struct usbd_interface *sc_iface; struct timeout_task calib_task; struct task tx_task; const uint8_t *qid2idx; struct mtx sc_mtx; int sc_ht; int sc_nendpoints; int sc_curpwrstate; int sc_currssi; u_int sc_running:1, sc_calibrating:1, sc_scanning:1, sc_scan_pass:1; u_int cut; uint8_t sc_rftype; int8_t sc_nrxstream; int8_t sc_ntxstream; struct rsu_host_cmd_ring cmdq; struct rsu_data sc_rx[RSU_RX_LIST_COUNT]; struct rsu_data sc_tx[RSU_TX_LIST_COUNT]; struct rsu_data *fwcmd_data; uint8_t cmd_seq; uint8_t rom[128]; struct usb_xfer *sc_xfer[RSU_N_TRANSFER]; STAILQ_HEAD(, rsu_data) sc_rx_active; STAILQ_HEAD(, rsu_data) sc_rx_inactive; STAILQ_HEAD(, rsu_data) sc_tx_active[RSU_N_TRANSFER]; STAILQ_HEAD(, rsu_data) sc_tx_inactive; STAILQ_HEAD(, rsu_data) sc_tx_pending[RSU_N_TRANSFER]; union { struct rsu_rx_radiotap_header th; uint8_t pad[64]; } sc_rxtapu; #define sc_rxtap sc_rxtapu.th - int sc_rxtap_len; union { struct rsu_tx_radiotap_header th; uint8_t pad[64]; } sc_txtapu; #define sc_txtap sc_txtapu.th - int sc_txtap_len; }; Index: head/sys/dev/usb/wlan/if_runvar.h =================================================================== --- head/sys/dev/usb/wlan/if_runvar.h (revision 289167) +++ head/sys/dev/usb/wlan/if_runvar.h (revision 289168) @@ -1,270 +1,268 @@ /* $OpenBSD: if_runvar.h,v 1.3 2009/03/26 20:17:27 damien Exp $ */ /*- * Copyright (c) 2008,2009 Damien Bergamini * ported to FreeBSD by Akinori Furukoshi * USB Consulting, Hans Petter Selasky * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ #ifndef _IF_RUNVAR_H_ #define _IF_RUNVAR_H_ #define RUN_MAX_RXSZ \ MIN(4096, MJUMPAGESIZE) /* NB: "11" is the maximum number of padding bytes needed for Tx */ #define RUN_MAX_TXSZ \ (sizeof (struct rt2870_txd) + \ sizeof (struct rt2860_txwi) + \ MCLBYTES + 11) #define RUN_TX_TIMEOUT 5000 /* ms */ /* Tx ring count was 8/endpoint, now 32 for all 4 (or 6) endpoints. */ #define RUN_TX_RING_COUNT 32 #define RUN_RX_RING_COUNT 1 #define RT2870_WCID_MAX 64 #define RUN_AID2WCID(aid) ((aid) & 0xff) #define RUN_VAP_MAX 8 struct run_rx_radiotap_header { struct ieee80211_radiotap_header wr_ihdr; uint64_t wr_tsf; uint8_t wr_flags; uint8_t wr_rate; uint16_t wr_chan_freq; uint16_t wr_chan_flags; int8_t wr_dbm_antsignal; uint8_t wr_antenna; uint8_t wr_antsignal; } __packed __aligned(8); #define RUN_RX_RADIOTAP_PRESENT \ (1 << IEEE80211_RADIOTAP_TSFT | \ 1 << IEEE80211_RADIOTAP_FLAGS | \ 1 << IEEE80211_RADIOTAP_RATE | \ 1 << IEEE80211_RADIOTAP_CHANNEL | \ 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL | \ 1 << IEEE80211_RADIOTAP_ANTENNA | \ 1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL) struct run_tx_radiotap_header { struct ieee80211_radiotap_header wt_ihdr; uint64_t wt_tsf; uint8_t wt_flags; uint8_t wt_rate; uint16_t wt_chan_freq; uint16_t wt_chan_flags; uint8_t wt_hwqueue; } __packed __aligned(8); #define IEEE80211_RADIOTAP_HWQUEUE 15 #define RUN_TX_RADIOTAP_PRESENT \ (1 << IEEE80211_RADIOTAP_TSFT | \ 1 << IEEE80211_RADIOTAP_FLAGS | \ 1 << IEEE80211_RADIOTAP_RATE | \ 1 << IEEE80211_RADIOTAP_CHANNEL | \ 1 << IEEE80211_RADIOTAP_HWQUEUE) struct run_softc; struct run_tx_data { STAILQ_ENTRY(run_tx_data) next; struct run_softc *sc; struct mbuf *m; struct ieee80211_node *ni; uint32_t align[0]; /* dummy field */ uint8_t desc[sizeof(struct rt2870_txd) + sizeof(struct rt2860_txwi)]; uint8_t ridx; }; STAILQ_HEAD(run_tx_data_head, run_tx_data); struct run_node { struct ieee80211_node ni; uint8_t ridx[IEEE80211_RATE_MAXSIZE]; uint8_t ctl_ridx[IEEE80211_RATE_MAXSIZE]; uint8_t amrr_ridx; uint8_t mgt_ridx; uint8_t fix_ridx; }; #define RUN_NODE(ni) ((struct run_node *)(ni)) struct run_cmdq { void *arg0; void *arg1; void (*func)(void *); struct ieee80211_key *k; struct ieee80211_key key; uint8_t mac[IEEE80211_ADDR_LEN]; uint8_t wcid; }; struct run_vap { struct ieee80211vap vap; struct mbuf *beacon_mbuf; int (*newstate)(struct ieee80211vap *, enum ieee80211_state, int); void (*recv_mgmt)(struct ieee80211_node *, struct mbuf *, int, const struct ieee80211_rx_stats *, int, int); uint8_t rvp_id; }; #define RUN_VAP(vap) ((struct run_vap *)(vap)) /* * There are 7 bulk endpoints: 1 for RX * and 6 for TX (4 EDCAs + HCCA + Prio). * Update 03-14-2009: some devices like the Planex GW-US300MiniS * seem to have only 4 TX bulk endpoints (Fukaumi Naoki). */ enum { RUN_BULK_TX_BE, /* = WME_AC_BE */ RUN_BULK_TX_BK, /* = WME_AC_BK */ RUN_BULK_TX_VI, /* = WME_AC_VI */ RUN_BULK_TX_VO, /* = WME_AC_VO */ RUN_BULK_TX_HCCA, RUN_BULK_TX_PRIO, RUN_BULK_RX, RUN_N_XFER, }; #define RUN_EP_QUEUES RUN_BULK_RX struct run_endpoint_queue { struct run_tx_data tx_data[RUN_TX_RING_COUNT]; struct run_tx_data_head tx_qh; struct run_tx_data_head tx_fh; uint32_t tx_nfree; }; struct run_softc { struct mtx sc_mtx; struct ieee80211com sc_ic; struct mbufq sc_snd; device_t sc_dev; struct usb_device *sc_udev; int sc_need_fwload; int sc_flags; #define RUN_FLAG_FWLOAD_NEEDED 0x01 #define RUN_RUNNING 0x02 uint16_t wcid_stats[RT2870_WCID_MAX + 1][3]; #define RUN_TXCNT 0 #define RUN_SUCCESS 1 #define RUN_RETRY 2 int (*sc_srom_read)(struct run_softc *, uint16_t, uint16_t *); uint16_t mac_ver; uint16_t mac_rev; uint16_t rf_rev; uint8_t freq; uint8_t ntxchains; uint8_t nrxchains; uint8_t bbp25; uint8_t bbp26; uint8_t rf24_20mhz; uint8_t rf24_40mhz; uint8_t patch_dac; uint8_t rfswitch; uint8_t ext_2ghz_lna; uint8_t ext_5ghz_lna; uint8_t calib_2ghz; uint8_t calib_5ghz; uint8_t txmixgain_2ghz; uint8_t txmixgain_5ghz; int8_t txpow1[54]; int8_t txpow2[54]; int8_t txpow3[54]; int8_t rssi_2ghz[3]; int8_t rssi_5ghz[3]; uint8_t lna[4]; struct { uint8_t reg; uint8_t val; } bbp[10], rf[10]; uint8_t leds; uint16_t led[3]; uint32_t txpow20mhz[5]; uint32_t txpow40mhz_2ghz[5]; uint32_t txpow40mhz_5ghz[5]; struct run_endpoint_queue sc_epq[RUN_EP_QUEUES]; struct task ratectl_task; struct usb_callout ratectl_ch; uint8_t ratectl_run; #define RUN_RATECTL_OFF 0 /* need to be power of 2, otherwise RUN_CMDQ_GET fails */ #define RUN_CMDQ_MAX 16 #define RUN_CMDQ_MASQ (RUN_CMDQ_MAX - 1) struct run_cmdq cmdq[RUN_CMDQ_MAX]; struct task cmdq_task; uint32_t cmdq_store; uint8_t cmdq_exec; uint8_t cmdq_run; uint8_t cmdq_key_set; #define RUN_CMDQ_ABORT 0 #define RUN_CMDQ_GO 1 struct usb_xfer *sc_xfer[RUN_N_XFER]; struct mbuf *rx_m; uint8_t fifo_cnt; uint8_t running; uint8_t runbmap; uint8_t ap_running; uint8_t adhoc_running; uint8_t sta_running; uint8_t rvp_cnt; uint8_t rvp_bmap; uint8_t sc_detached; union { struct run_rx_radiotap_header th; uint8_t pad[64]; } sc_rxtapu; #define sc_rxtap sc_rxtapu.th - int sc_rxtap_len; union { struct run_tx_radiotap_header th; uint8_t pad[64]; } sc_txtapu; #define sc_txtap sc_txtapu.th - int sc_txtap_len; }; #define RUN_LOCK(sc) mtx_lock(&(sc)->sc_mtx) #define RUN_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) #define RUN_LOCK_ASSERT(sc, t) mtx_assert(&(sc)->sc_mtx, t) #endif /* _IF_RUNVAR_H_ */ Index: head/sys/dev/usb/wlan/if_uathvar.h =================================================================== --- head/sys/dev/usb/wlan/if_uathvar.h (revision 289167) +++ head/sys/dev/usb/wlan/if_uathvar.h (revision 289168) @@ -1,247 +1,245 @@ /* $OpenBSD: if_uathvar.h,v 1.3 2006/09/20 19:47:17 damien Exp $ */ /* $FreeBSD$ */ /*- * Copyright (c) 2006 * Damien Bergamini * Copyright (c) 2006 Sam Leffler, Errno Consulting * Copyright (c) 2008-2009 Weongyo Jeong * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ enum { UATH_INTR_RX, UATH_INTR_TX, UATH_BULK_RX, UATH_BULK_TX, UATH_N_XFERS = 4, }; #define UATH_ID_BSS 2 /* Connection ID */ #define UATH_RX_DATA_LIST_COUNT 128 #define UATH_TX_DATA_LIST_COUNT 16 #define UATH_CMD_LIST_COUNT 60 #define UATH_DATA_TIMEOUT 10000 #define UATH_CMD_TIMEOUT 1000 /* flags for sending firmware commands */ #define UATH_CMD_FLAG_ASYNC (1 << 0) #define UATH_CMD_FLAG_READ (1 << 1) #define UATH_CMD_FLAG_MAGIC (1 << 2) struct uath_rx_radiotap_header { struct ieee80211_radiotap_header wr_ihdr; u_int64_t wr_tsf; u_int8_t wr_flags; u_int8_t wr_rate; uint16_t wr_chan_freq; uint16_t wr_chan_flags; int8_t wr_antsignal; int8_t wr_antnoise; u_int8_t wr_antenna; } __packed __aligned(8); #define UATH_RX_RADIOTAP_PRESENT ( \ (1 << IEEE80211_RADIOTAP_TSFT) | \ (1 << IEEE80211_RADIOTAP_FLAGS) | \ (1 << IEEE80211_RADIOTAP_RATE) | \ (1 << IEEE80211_RADIOTAP_ANTENNA) | \ (1 << IEEE80211_RADIOTAP_CHANNEL) | \ (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \ 0) struct uath_tx_radiotap_header { struct ieee80211_radiotap_header wt_ihdr; uint8_t wt_flags; uint16_t wt_chan_freq; uint16_t wt_chan_flags; } __packed __aligned(8); #define UATH_TX_RADIOTAP_PRESENT \ ((1 << IEEE80211_RADIOTAP_FLAGS) | \ (1 << IEEE80211_RADIOTAP_CHANNEL)) struct uath_data { struct uath_softc *sc; uint8_t *buf; uint16_t buflen; struct mbuf *m; struct ieee80211_node *ni; /* NB: tx only */ STAILQ_ENTRY(uath_data) next; }; typedef STAILQ_HEAD(, uath_data) uath_datahead; struct uath_cmd { struct uath_softc *sc; uint32_t flags; uint32_t msgid; uint8_t *buf; uint16_t buflen; void *odata; /* NB: tx only */ int olen; /* space in odata */ STAILQ_ENTRY(uath_cmd) next; }; typedef STAILQ_HEAD(, uath_cmd) uath_cmdhead; struct uath_wme_settings { uint8_t aifsn; uint8_t logcwmin; uint8_t logcwmax; uint16_t txop; uint8_t acm; }; struct uath_devcap { uint32_t targetVersion; uint32_t targetRevision; uint32_t macVersion; uint32_t macRevision; uint32_t phyRevision; uint32_t analog5GhzRevision; uint32_t analog2GhzRevision; uint32_t regDomain; uint32_t regCapBits; uint32_t countryCode; uint32_t keyCacheSize; uint32_t numTxQueues; uint32_t connectionIdMax; uint32_t wirelessModes; #define UATH_WIRELESS_MODE_11A 0x01 #define UATH_WIRELESS_MODE_TURBO 0x02 #define UATH_WIRELESS_MODE_11B 0x04 #define UATH_WIRELESS_MODE_11G 0x08 #define UATH_WIRELESS_MODE_108G 0x10 uint32_t chanSpreadSupport; uint32_t compressSupport; uint32_t burstSupport; uint32_t fastFramesSupport; uint32_t chapTuningSupport; uint32_t turboGSupport; uint32_t turboPrimeSupport; uint32_t deviceType; uint32_t wmeSupport; uint32_t low2GhzChan; uint32_t high2GhzChan; uint32_t low5GhzChan; uint32_t high5GhzChan; uint32_t supportCipherWEP; uint32_t supportCipherAES_CCM; uint32_t supportCipherTKIP; uint32_t supportCipherMicAES_CCM; uint32_t supportMicTKIP; uint32_t twiceAntennaGain5G; uint32_t twiceAntennaGain2G; }; struct uath_stat { uint32_t st_badchunkseqnum; uint32_t st_invalidlen; uint32_t st_multichunk; uint32_t st_toobigrxpkt; uint32_t st_stopinprogress; uint32_t st_crcerr; uint32_t st_phyerr; uint32_t st_decrypt_crcerr; uint32_t st_decrypt_micerr; uint32_t st_decomperr; uint32_t st_keyerr; uint32_t st_err; /* CMD/RX/TX queues */ uint32_t st_cmd_active; uint32_t st_cmd_inactive; uint32_t st_cmd_pending; uint32_t st_cmd_waiting; uint32_t st_rx_active; uint32_t st_rx_inactive; uint32_t st_tx_active; uint32_t st_tx_inactive; uint32_t st_tx_pending; }; #define UATH_STAT_INC(sc, var) (sc)->sc_stat.var++ #define UATH_STAT_DEC(sc, var) (sc)->sc_stat.var-- struct uath_vap { struct ieee80211vap vap; int (*newstate)(struct ieee80211vap *, enum ieee80211_state, int); }; #define UATH_VAP(vap) ((struct uath_vap *)(vap)) struct uath_softc { struct ieee80211com sc_ic; struct mbufq sc_snd; device_t sc_dev; struct usb_device *sc_udev; void *sc_cmd_dma_buf; void *sc_tx_dma_buf; struct mtx sc_mtx; uint32_t sc_debug; struct uath_stat sc_stat; int (*sc_newstate)(struct ieee80211com *, enum ieee80211_state, int); struct usb_xfer *sc_xfer[UATH_N_XFERS]; struct uath_cmd sc_cmd[UATH_CMD_LIST_COUNT]; uath_cmdhead sc_cmd_active; uath_cmdhead sc_cmd_inactive; uath_cmdhead sc_cmd_pending; uath_cmdhead sc_cmd_waiting; struct uath_data sc_rx[UATH_RX_DATA_LIST_COUNT]; uath_datahead sc_rx_active; uath_datahead sc_rx_inactive; struct uath_data sc_tx[UATH_TX_DATA_LIST_COUNT]; uath_datahead sc_tx_active; uath_datahead sc_tx_inactive; uath_datahead sc_tx_pending; uint32_t sc_msgid; uint32_t sc_seqnum; int sc_tx_timer; struct callout watchdog_ch; struct callout stat_ch; /* multi-chunked support */ struct mbuf *sc_intrx_head; struct mbuf *sc_intrx_tail; uint8_t sc_intrx_nextnum; uint32_t sc_intrx_len; #define UATH_MAX_INTRX_SIZE 3616 struct uath_devcap sc_devcap; uint8_t sc_serial[16]; /* unsorted */ uint32_t sc_flags; #define UATH_FLAG_INVALID (1 << 1) #define UATH_FLAG_INITDONE (1 << 2) struct uath_rx_radiotap_header sc_rxtap; - int sc_rxtap_len; struct uath_tx_radiotap_header sc_txtap; - int sc_txtap_len; }; #define UATH_LOCK(sc) mtx_lock(&(sc)->sc_mtx) #define UATH_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) #define UATH_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) #define UATH_RESET_INTRX(sc) do { \ (sc)->sc_intrx_head = NULL; \ (sc)->sc_intrx_tail = NULL; \ (sc)->sc_intrx_nextnum = 0; \ (sc)->sc_intrx_len = 0; \ } while (0) Index: head/sys/dev/usb/wlan/if_upgtvar.h =================================================================== --- head/sys/dev/usb/wlan/if_upgtvar.h (revision 289167) +++ head/sys/dev/usb/wlan/if_upgtvar.h (revision 289168) @@ -1,482 +1,480 @@ /* $OpenBSD: if_upgtvar.h,v 1.14 2008/02/02 13:48:44 mglocker Exp $ */ /* $FreeBSD$ */ /* * Copyright (c) 2007 Marcus Glocker * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ struct upgt_softc; /* * General values. */ enum { UPGT_BULK_RX, UPGT_BULK_TX, UPGT_N_XFERS = 2, }; #define UPGT_CONFIG_INDEX 0 #define UPGT_IFACE_INDEX 0 #define UPGT_USB_TIMEOUT 1000 #define UPGT_FIRMWARE_TIMEOUT 10 #define UPGT_MEMADDR_FIRMWARE_START 0x00020000 /* 512 bytes large */ #define UPGT_MEMSIZE_FRAME_HEAD 0x0070 #define UPGT_MEMSIZE_RX 0x3500 #define UPGT_RX_MAXCOUNT 6 #define UPGT_TX_MAXCOUNT 128 #define UPGT_TX_STAT_INTERVAL 5 #define UPGT_RX_MINSZ (sizeof(struct upgt_lmac_header) + 4) /* device flags */ #define UPGT_DEVICE_ATTACHED (1 << 0) /* leds */ #define UPGT_LED_OFF 0 #define UPGT_LED_ON 1 #define UPGT_LED_BLINK 2 /* * Firmware. */ #define UPGT_FW_BLOCK_SIZE 256 #define UPGT_BRA_FWTYPE_SIZE 4 #define UPGT_BRA_FWTYPE_LM86 "LM86" #define UPGT_BRA_FWTYPE_LM87 "LM87" enum upgt_fw_type { UPGT_FWTYPE_LM86, UPGT_FWTYPE_LM87 }; #define UPGT_BRA_TYPE_FW 0x80000001 #define UPGT_BRA_TYPE_VERSION 0x80000002 #define UPGT_BRA_TYPE_DEPIF 0x80000003 #define UPGT_BRA_TYPE_EXPIF 0x80000004 #define UPGT_BRA_TYPE_DESCR 0x80000101 #define UPGT_BRA_TYPE_END 0xff0000ff struct upgt_fw_bra_option { uint32_t type; uint32_t len; uint8_t data[]; } __packed; struct upgt_fw_bra_descr { uint32_t unknown1; uint32_t memaddr_space_start; uint32_t memaddr_space_end; uint32_t unknown2; uint32_t unknown3; uint8_t rates[20]; } __packed; #define UPGT_X2_SIGNATURE_SIZE 4 #define UPGT_X2_SIGNATURE "x2 " struct upgt_fw_x2_header { uint8_t signature[4]; uint32_t startaddr; uint32_t len; uint32_t crc; } __packed; /* * EEPROM. */ #define UPGT_EEPROM_SIZE 8192 #define UPGT_EEPROM_BLOCK_SIZE 1020 struct upgt_eeprom_header { /* 14 bytes */ uint32_t magic; uint16_t pad1; uint16_t preamble_len; uint32_t pad2; /* data */ } __packed; #define UPGT_EEPROM_TYPE_END 0x0000 #define UPGT_EEPROM_TYPE_NAME 0x0001 #define UPGT_EEPROM_TYPE_SERIAL 0x0003 #define UPGT_EEPROM_TYPE_MAC 0x0101 #define UPGT_EEPROM_TYPE_HWRX 0x1001 #define UPGT_EEPROM_TYPE_CHIP 0x1002 #define UPGT_EEPROM_TYPE_FREQ3 0x1903 #define UPGT_EEPROM_TYPE_FREQ4 0x1904 #define UPGT_EEPROM_TYPE_FREQ5 0x1905 #define UPGT_EEPROM_TYPE_FREQ6 0x1906 #define UPGT_EEPROM_TYPE_OFF 0xffff struct upgt_eeprom_option { uint16_t len; uint16_t type; uint8_t data[]; /* data */ } __packed; #define UPGT_EEPROM_RX_CONST 0x88 struct upgt_eeprom_option_hwrx { uint32_t pad1; uint8_t rxfilter; uint8_t pad2[15]; } __packed; struct upgt_eeprom_freq3_header { uint8_t flags; uint8_t elements; } __packed; struct upgt_eeprom_freq4_header { uint8_t flags; uint8_t elements; uint8_t settings; uint8_t type; } __packed; struct upgt_eeprom_freq4_1 { uint16_t freq; uint8_t data[50]; } __packed; struct upgt_eeprom_freq4_2 { uint16_t head; uint8_t subtails[4]; uint8_t tail; } __packed; /* * LMAC protocol. */ struct upgt_lmac_mem { uint32_t addr; uint32_t chksum; } __packed; #define UPGT_H1_FLAGS_TX_MGMT 0x00 /* for TX: mgmt frame */ #define UPGT_H1_FLAGS_TX_NO_CALLBACK 0x01 /* for TX: no USB callback */ #define UPGT_H1_FLAGS_TX_DATA 0x10 /* for TX: data frame */ #define UPGT_H1_TYPE_RX_DATA 0x00 /* 802.11 RX data frame */ #define UPGT_H1_TYPE_RX_DATA_MGMT 0x04 /* 802.11 RX mgmt frame */ #define UPGT_H1_TYPE_TX_DATA 0x40 /* 802.11 TX data frame */ #define UPGT_H1_TYPE_CTRL 0x80 /* control frame */ struct upgt_lmac_h1 { /* 4 bytes */ uint8_t flags; uint8_t type; uint16_t len; } __packed; #define UPGT_H2_TYPE_TX_ACK_NO 0x0000 #define UPGT_H2_TYPE_TX_ACK_YES 0x0001 #define UPGT_H2_TYPE_MACFILTER 0x0000 #define UPGT_H2_TYPE_CHANNEL 0x0001 #define UPGT_H2_TYPE_TX_DONE 0x0008 #define UPGT_H2_TYPE_STATS 0x000a #define UPGT_H2_TYPE_EEPROM 0x000c #define UPGT_H2_TYPE_LED 0x000d #define UPGT_H2_FLAGS_TX_ACK_NO 0x0101 #define UPGT_H2_FLAGS_TX_ACK_YES 0x0707 struct upgt_lmac_h2 { /* 8 bytes */ uint32_t reqid; uint16_t type; uint16_t flags; } __packed; struct upgt_lmac_header { /* 12 bytes */ struct upgt_lmac_h1 header1; struct upgt_lmac_h2 header2; } __packed; struct upgt_lmac_eeprom { /* 16 bytes */ struct upgt_lmac_h1 header1; struct upgt_lmac_h2 header2; uint16_t offset; uint16_t len; /* data */ } __packed; #define UPGT_FILTER_TYPE_NONE 0x0000 #define UPGT_FILTER_TYPE_STA 0x0001 #define UPGT_FILTER_TYPE_IBSS 0x0002 #define UPGT_FILTER_TYPE_HOSTAP 0x0004 #define UPGT_FILTER_TYPE_MONITOR 0x0010 #define UPGT_FILTER_TYPE_RESET 0x0020 #define UPGT_FILTER_UNKNOWN1 0x0002 #define UPGT_FILTER_UNKNOWN2 0x0ca8 #define UPGT_FILTER_UNKNOWN3 0xffff #define UPGT_FILTER_MONITOR_UNKNOWN1 0x0000 #define UPGT_FILTER_MONITOR_UNKNOWN2 0x0000 #define UPGT_FILTER_MONITOR_UNKNOWN3 0x0000 struct upgt_lmac_filter { struct upgt_lmac_h1 header1; struct upgt_lmac_h2 header2; /* 32 bytes */ uint16_t type; uint8_t dst[IEEE80211_ADDR_LEN]; uint8_t src[IEEE80211_ADDR_LEN]; uint16_t unknown1; uint32_t rxaddr; uint16_t unknown2; uint32_t rxhw; uint16_t unknown3; uint32_t unknown4; } __packed; /* frequence 3 data */ struct upgt_lmac_freq3 { uint16_t freq; uint8_t data[6]; } __packed; /* frequence 4 data */ struct upgt_lmac_freq4 { struct upgt_eeprom_freq4_2 cmd; uint8_t pad; }; /* frequence 6 data */ struct upgt_lmac_freq6 { uint16_t freq; uint8_t data[8]; } __packed; #define UPGT_CHANNEL_UNKNOWN1 0x0001 #define UPGT_CHANNEL_UNKNOWN2 0x0000 #define UPGT_CHANNEL_UNKNOWN3 0x48 struct upgt_lmac_channel { struct upgt_lmac_h1 header1; struct upgt_lmac_h2 header2; /* 112 bytes */ uint16_t unknown1; uint16_t unknown2; uint8_t pad1[20]; struct upgt_lmac_freq6 freq6; uint8_t settings; uint8_t unknown3; uint8_t freq3_1[4]; struct upgt_lmac_freq4 freq4[8]; uint8_t freq3_2[4]; uint32_t pad2; } __packed; #define UPGT_LED_MODE_SET 0x0003 #define UPGT_LED_ACTION_OFF 0x0002 #define UPGT_LED_ACTION_ON 0x0003 #define UPGT_LED_ACTION_TMP_DUR 100 /* ms */ struct upgt_lmac_led { struct upgt_lmac_h1 header1; struct upgt_lmac_h2 header2; uint16_t mode; uint16_t action_fix; uint16_t action_tmp; uint16_t action_tmp_dur; } __packed; struct upgt_lmac_stats { struct upgt_lmac_h1 header1; struct upgt_lmac_h2 header2; uint8_t data[76]; } __packed; struct upgt_lmac_rx_desc { struct upgt_lmac_h1 header1; /* 16 bytes */ uint16_t freq; uint8_t unknown1; uint8_t rate; uint8_t rssi; uint8_t pad; uint16_t unknown2; uint32_t timestamp; uint32_t unknown3; uint8_t data[]; } __packed; #define UPGT_TX_DESC_KEY_EXISTS 0x01 struct upgt_lmac_tx_desc_wep { uint8_t key_exists; uint8_t key_len; uint8_t key_val[16]; } __packed; #define UPGT_TX_DESC_TYPE_BEACON 0x00000000 #define UPGT_TX_DESC_TYPE_PROBE 0x00000001 #define UPGT_TX_DESC_TYPE_MGMT 0x00000002 #define UPGT_TX_DESC_TYPE_DATA 0x00000004 #define UPGT_TX_DESC_PAD3_SIZE 2 struct upgt_lmac_tx_desc { struct upgt_lmac_h1 header1; struct upgt_lmac_h2 header2; uint8_t rates[8]; uint16_t pad1; struct upgt_lmac_tx_desc_wep wep_key; uint32_t type; uint32_t pad2; uint32_t unknown1; uint32_t unknown2; uint8_t pad3[2]; /* 802.11 frame data */ } __packed; #define UPGT_TX_DONE_DESC_STATUS_OK 0x0001 struct upgt_lmac_tx_done_desc { struct upgt_lmac_h1 header1; struct upgt_lmac_h2 header2; uint16_t status; uint16_t rssi; uint16_t seq; uint16_t unknown; } __packed; /* * USB xfers. */ struct upgt_data { uint8_t *buf; uint32_t buflen; struct ieee80211_node *ni; struct mbuf *m; uint32_t addr; STAILQ_ENTRY(upgt_data) next; }; typedef STAILQ_HEAD(, upgt_data) upgt_datahead; /* * Prism memory. */ struct upgt_memory_page { uint8_t used; uint32_t addr; } __packed; #define UPGT_MEMORY_MAX_PAGES 8 struct upgt_memory { uint8_t pages; struct upgt_memory_page page[UPGT_MEMORY_MAX_PAGES]; } __packed; /* * BPF */ struct upgt_rx_radiotap_header { struct ieee80211_radiotap_header wr_ihdr; uint8_t wr_flags; uint8_t wr_rate; uint16_t wr_chan_freq; uint16_t wr_chan_flags; int8_t wr_antsignal; } __packed __aligned(8); #define UPGT_RX_RADIOTAP_PRESENT \ ((1 << IEEE80211_RADIOTAP_FLAGS) | \ (1 << IEEE80211_RADIOTAP_RATE) | \ (1 << IEEE80211_RADIOTAP_CHANNEL) | \ (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL)) struct upgt_tx_radiotap_header { struct ieee80211_radiotap_header wt_ihdr; uint8_t wt_flags; uint8_t wt_rate; uint16_t wt_chan_freq; uint16_t wt_chan_flags; } __packed __aligned(8); #define UPGT_TX_RADIOTAP_PRESENT \ ((1 << IEEE80211_RADIOTAP_FLAGS) | \ (1 << IEEE80211_RADIOTAP_RATE) | \ (1 << IEEE80211_RADIOTAP_CHANNEL)) struct upgt_stat { uint32_t st_tx_active; uint32_t st_tx_inactive; uint32_t st_tx_pending; }; #define UPGT_STAT_INC(sc, var) (sc)->sc_stat.var++ #define UPGT_STAT_DEC(sc, var) (sc)->sc_stat.var-- struct upgt_vap { struct ieee80211vap vap; int (*newstate)(struct ieee80211vap *, enum ieee80211_state, int); }; #define UPGT_VAP(vap) ((struct upgt_vap *)(vap)) struct upgt_softc { struct ieee80211com sc_ic; struct mbufq sc_snd; device_t sc_dev; struct usb_device *sc_udev; void *sc_rx_dma_buf; void *sc_tx_dma_buf; struct mtx sc_mtx; struct upgt_stat sc_stat; int sc_flags; #define UPGT_FLAG_FWLOADED (1 << 0) #define UPGT_FLAG_INITDONE (1 << 1) #define UPGT_FLAG_DETACHED (1 << 2) int sc_debug; enum ieee80211_state sc_state; int sc_arg; int sc_led_blink; struct callout sc_led_ch; uint8_t sc_cur_rateset[8]; /* watchdog */ int sc_tx_timer; struct callout sc_watchdog_ch; /* Firmware. */ int sc_fw_type; /* memory addresses on device */ uint32_t sc_memaddr_frame_start; uint32_t sc_memaddr_frame_end; uint32_t sc_memaddr_rx_start; struct upgt_memory sc_memory; /* data which we found in the EEPROM */ uint8_t sc_eeprom[2 * UPGT_EEPROM_SIZE] __aligned(4); uint16_t sc_eeprom_hwrx; struct upgt_lmac_freq3 sc_eeprom_freq3[IEEE80211_CHAN_MAX]; struct upgt_lmac_freq4 sc_eeprom_freq4[IEEE80211_CHAN_MAX][8]; struct upgt_lmac_freq6 sc_eeprom_freq6[IEEE80211_CHAN_MAX]; uint8_t sc_eeprom_freq6_settings; /* RX/TX */ struct usb_xfer *sc_xfer[UPGT_N_XFERS]; int sc_rx_no; int sc_tx_no; struct upgt_data sc_rx_data[UPGT_RX_MAXCOUNT]; upgt_datahead sc_rx_active; upgt_datahead sc_rx_inactive; struct upgt_data sc_tx_data[UPGT_TX_MAXCOUNT]; upgt_datahead sc_tx_active; upgt_datahead sc_tx_inactive; upgt_datahead sc_tx_pending; /* BPF */ struct upgt_rx_radiotap_header sc_rxtap; - int sc_rxtap_len; struct upgt_tx_radiotap_header sc_txtap; - int sc_txtap_len; }; #define UPGT_LOCK(sc) mtx_lock(&(sc)->sc_mtx) #define UPGT_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) #define UPGT_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) Index: head/sys/dev/usb/wlan/if_uralvar.h =================================================================== --- head/sys/dev/usb/wlan/if_uralvar.h (revision 289167) +++ head/sys/dev/usb/wlan/if_uralvar.h (revision 289168) @@ -1,136 +1,133 @@ /* $FreeBSD$ */ /*- * Copyright (c) 2005 * Damien Bergamini * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #define RAL_TX_LIST_COUNT 8 #define RAL_TX_MINFREE 2 #define URAL_SCAN_START 1 #define URAL_SCAN_END 2 #define URAL_SET_CHANNEL 3 struct ural_rx_radiotap_header { struct ieee80211_radiotap_header wr_ihdr; uint8_t wr_flags; uint8_t wr_rate; uint16_t wr_chan_freq; uint16_t wr_chan_flags; int8_t wr_antsignal; int8_t wr_antnoise; uint8_t wr_antenna; } __packed __aligned(8); #define RAL_RX_RADIOTAP_PRESENT \ ((1 << IEEE80211_RADIOTAP_FLAGS) | \ (1 << IEEE80211_RADIOTAP_RATE) | \ (1 << IEEE80211_RADIOTAP_CHANNEL) | \ (1 << IEEE80211_RADIOTAP_ANTENNA) | \ (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE)) struct ural_tx_radiotap_header { struct ieee80211_radiotap_header wt_ihdr; uint8_t wt_flags; uint8_t wt_rate; uint16_t wt_chan_freq; uint16_t wt_chan_flags; uint8_t wt_antenna; } __packed __aligned(8); #define RAL_TX_RADIOTAP_PRESENT \ ((1 << IEEE80211_RADIOTAP_FLAGS) | \ (1 << IEEE80211_RADIOTAP_RATE) | \ (1 << IEEE80211_RADIOTAP_CHANNEL) | \ (1 << IEEE80211_RADIOTAP_ANTENNA)) struct ural_softc; struct ural_tx_data { STAILQ_ENTRY(ural_tx_data) next; struct ural_softc *sc; struct ural_tx_desc desc; struct mbuf *m; struct ieee80211_node *ni; int rate; }; typedef STAILQ_HEAD(, ural_tx_data) ural_txdhead; struct ural_vap { struct ieee80211vap vap; struct usb_callout ratectl_ch; struct task ratectl_task; int (*newstate)(struct ieee80211vap *, enum ieee80211_state, int); }; #define URAL_VAP(vap) ((struct ural_vap *)(vap)) enum { URAL_BULK_WR, URAL_BULK_RD, URAL_N_TRANSFER = 2, }; struct ural_softc { struct ieee80211com sc_ic; struct mbufq sc_snd; device_t sc_dev; struct usb_device *sc_udev; uint32_t asic_rev; uint8_t rf_rev; struct usb_xfer *sc_xfer[URAL_N_TRANSFER]; struct ural_tx_data tx_data[RAL_TX_LIST_COUNT]; ural_txdhead tx_q; ural_txdhead tx_free; int tx_nfree; struct ural_rx_desc sc_rx_desc; struct mtx sc_mtx; uint16_t sta[11]; uint32_t rf_regs[4]; uint8_t txpow[14]; u_int sc_detached:1, sc_running:1; struct { uint8_t val; uint8_t reg; } __packed bbp_prom[16]; int led_mode; int hw_radio; int rx_ant; int tx_ant; int nb_ant; struct ural_rx_radiotap_header sc_rxtap; - int sc_rxtap_len; - struct ural_tx_radiotap_header sc_txtap; - int sc_txtap_len; }; #define RAL_LOCK(sc) mtx_lock(&(sc)->sc_mtx) #define RAL_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) #define RAL_LOCK_ASSERT(sc, t) mtx_assert(&(sc)->sc_mtx, t) Index: head/sys/dev/usb/wlan/if_urtwnvar.h =================================================================== --- head/sys/dev/usb/wlan/if_urtwnvar.h (revision 289167) +++ head/sys/dev/usb/wlan/if_urtwnvar.h (revision 289168) @@ -1,206 +1,203 @@ /*- * Copyright (c) 2010 Damien Bergamini * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $ * $FreeBSD$ */ #define URTWN_RX_LIST_COUNT 1 #define URTWN_TX_LIST_COUNT 8 #define URTWN_HOST_CMD_RING_COUNT 32 #define URTWN_RXBUFSZ (16 * 1024) #define URTWN_TXBUFSZ (sizeof(struct r92c_tx_desc) + IEEE80211_MAX_LEN) #define URTWN_RX_DESC_SIZE (sizeof(struct r92c_rx_stat)) #define URTWN_TX_DESC_SIZE (sizeof(struct r92c_tx_desc)) #define URTWN_RIDX_COUNT 28 #define URTWN_TX_TIMEOUT 5000 /* ms */ #define URTWN_LED_LINK 0 #define URTWN_LED_DATA 1 struct urtwn_rx_radiotap_header { struct ieee80211_radiotap_header wr_ihdr; uint8_t wr_flags; uint8_t wr_rate; uint16_t wr_chan_freq; uint16_t wr_chan_flags; uint8_t wr_dbm_antsignal; } __packed __aligned(8); #define URTWN_RX_RADIOTAP_PRESENT \ (1 << IEEE80211_RADIOTAP_FLAGS | \ 1 << IEEE80211_RADIOTAP_RATE | \ 1 << IEEE80211_RADIOTAP_CHANNEL | \ 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) struct urtwn_tx_radiotap_header { struct ieee80211_radiotap_header wt_ihdr; uint8_t wt_flags; uint16_t wt_chan_freq; uint16_t wt_chan_flags; } __packed __aligned(8); #define URTWN_TX_RADIOTAP_PRESENT \ (1 << IEEE80211_RADIOTAP_FLAGS | \ 1 << IEEE80211_RADIOTAP_CHANNEL) struct urtwn_softc; struct urtwn_data { struct urtwn_softc *sc; uint8_t *buf; uint16_t buflen; struct mbuf *m; struct ieee80211_node *ni; STAILQ_ENTRY(urtwn_data) next; }; typedef STAILQ_HEAD(, urtwn_data) urtwn_datahead; struct urtwn_cmdq { void *arg0; void *arg1; void (*func)(void *); struct ieee80211_key *k; struct ieee80211_key key; uint8_t mac[IEEE80211_ADDR_LEN]; uint8_t wcid; }; struct urtwn_fw_info { const uint8_t *data; size_t size; }; struct urtwn_vap { struct ieee80211vap vap; int (*newstate)(struct ieee80211vap *, enum ieee80211_state, int); }; #define URTWN_VAP(vap) ((struct urtwn_vap *)(vap)) struct urtwn_host_cmd { void (*cb)(struct urtwn_softc *, void *); uint8_t data[256]; }; struct urtwn_cmd_newstate { enum ieee80211_state state; int arg; }; struct urtwn_cmd_key { struct ieee80211_key key; uint16_t associd; }; enum { URTWN_BULK_RX, URTWN_BULK_TX_BE, /* = WME_AC_BE */ URTWN_BULK_TX_BK, /* = WME_AC_BK */ URTWN_BULK_TX_VI, /* = WME_AC_VI */ URTWN_BULK_TX_VO, /* = WME_AC_VI */ URTWN_N_TRANSFER = 5, }; #define URTWN_EP_QUEUES URTWN_BULK_RX struct urtwn_softc { struct ieee80211com sc_ic; struct mbufq sc_snd; device_t sc_dev; struct usb_device *sc_udev; int ac2idx[WME_NUM_AC]; u_int sc_flags; #define URTWN_FLAG_CCK_HIPWR 0x01 #define URTWN_DETACHED 0x02 #define URTWN_RUNNING 0x04 u_int chip; #define URTWN_CHIP_92C 0x01 #define URTWN_CHIP_92C_1T2R 0x02 #define URTWN_CHIP_UMC 0x04 #define URTWN_CHIP_UMC_A_CUT 0x08 #define URTWN_CHIP_88E 0x10 void (*sc_rf_write)(struct urtwn_softc *, int, uint8_t, uint32_t); int (*sc_power_on)(struct urtwn_softc *); int (*sc_dma_init)(struct urtwn_softc *); uint8_t board_type; uint8_t regulatory; uint8_t pa_setting; int avg_pwdb; int thcal_state; int thcal_lctemp; int ntxchains; int nrxchains; int ledlink; int sc_txtimer; int fwcur; struct urtwn_data sc_rx[URTWN_RX_LIST_COUNT]; urtwn_datahead sc_rx_active; urtwn_datahead sc_rx_inactive; struct urtwn_data sc_tx[URTWN_TX_LIST_COUNT]; urtwn_datahead sc_tx_active; urtwn_datahead sc_tx_inactive; urtwn_datahead sc_tx_pending; const char *fwname; const struct firmware *fw_fp; struct urtwn_fw_info fw; void *fw_virtaddr; struct r92c_rom rom; uint8_t r88e_rom[512]; uint8_t cck_tx_pwr[6]; uint8_t ht40_tx_pwr[5]; int8_t bw20_tx_pwr_diff; int8_t ofdm_tx_pwr_diff; struct callout sc_watchdog_ch; struct mtx sc_mtx; /* need to be power of 2, otherwise URTWN_CMDQ_GET fails */ #define URTWN_CMDQ_MAX 16 #define URTWN_CMDQ_MASQ (URTWN_CMDQ_MAX - 1) struct urtwn_cmdq cmdq[URTWN_CMDQ_MAX]; struct task cmdq_task; uint32_t cmdq_store; uint8_t cmdq_exec; uint8_t cmdq_run; uint8_t cmdq_key_set; #define URTWN_CMDQ_ABORT 0 #define URTWN_CMDQ_GO 1 uint32_t rf_chnlbw[R92C_MAX_CHAINS]; struct usb_xfer *sc_xfer[URTWN_N_TRANSFER]; struct urtwn_rx_radiotap_header sc_rxtap; - int sc_rxtap_len; - struct urtwn_tx_radiotap_header sc_txtap; - int sc_txtap_len; }; #define URTWN_LOCK(sc) mtx_lock(&(sc)->sc_mtx) #define URTWN_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) -#define URTWN_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) \ No newline at end of file +#define URTWN_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) Index: head/sys/dev/usb/wlan/if_urtwvar.h =================================================================== --- head/sys/dev/usb/wlan/if_urtwvar.h (revision 289167) +++ head/sys/dev/usb/wlan/if_urtwvar.h (revision 289168) @@ -1,188 +1,186 @@ /* $FreeBSD$ */ /*- * Copyright (c) 2008 Weongyo Jeong * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ enum { URTW_8187B_BULK_RX, URTW_8187B_BULK_TX_STATUS, URTW_8187B_BULK_TX_BE, URTW_8187B_BULK_TX_BK, URTW_8187B_BULK_TX_VI, URTW_8187B_BULK_TX_VO, URTW_8187B_BULK_TX_EP12, URTW_8187B_N_XFERS = 7 }; enum { URTW_8187L_BULK_RX, URTW_8187L_BULK_TX_LOW, URTW_8187L_BULK_TX_NORMAL, URTW_8187L_N_XFERS = 3 }; /* XXX no definition at net80211? */ #define URTW_MAX_CHANNELS 15 struct urtw_data { struct urtw_softc *sc; uint8_t *buf; uint16_t buflen; struct mbuf *m; struct ieee80211_node *ni; /* NB: tx only */ STAILQ_ENTRY(urtw_data) next; }; typedef STAILQ_HEAD(, urtw_data) urtw_datahead; /* XXX not correct.. */ #define URTW_MIN_RXBUFSZ \ (sizeof(struct ieee80211_frame_min)) #define URTW_RX_DATA_LIST_COUNT 4 #define URTW_TX_DATA_LIST_COUNT 16 #define URTW_RX_MAXSIZE 0x9c4 #define URTW_TX_MAXSIZE 0x9c4 #define URTW_TX_MAXRETRY 11 struct urtw_rx_radiotap_header { struct ieee80211_radiotap_header wr_ihdr; uint8_t wr_flags; uint16_t wr_chan_freq; uint16_t wr_chan_flags; int8_t wr_dbm_antsignal; } __packed __aligned(8); #define URTW_RX_RADIOTAP_PRESENT \ ((1 << IEEE80211_RADIOTAP_FLAGS) | \ (1 << IEEE80211_RADIOTAP_CHANNEL) | \ (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL)) struct urtw_tx_radiotap_header { struct ieee80211_radiotap_header wt_ihdr; uint8_t wt_flags; uint16_t wt_chan_freq; uint16_t wt_chan_flags; } __packed __aligned(8); #define URTW_TX_RADIOTAP_PRESENT \ ((1 << IEEE80211_RADIOTAP_FLAGS) | \ (1 << IEEE80211_RADIOTAP_CHANNEL)) struct urtw_stats { unsigned int txrates[12]; }; struct urtw_vap { struct ieee80211vap vap; int (*newstate)(struct ieee80211vap *, enum ieee80211_state, int); }; #define URTW_VAP(vap) ((struct urtw_vap *)(vap)) struct urtw_softc { struct ieee80211com sc_ic; struct mbufq sc_snd; device_t sc_dev; struct usb_device *sc_udev; struct mtx sc_mtx; void *sc_tx_dma_buf; int sc_debug; int sc_flags; #define URTW_INIT_ONCE (1 << 1) #define URTW_RTL8187B (1 << 2) #define URTW_RTL8187B_REV_B (1 << 3) #define URTW_RTL8187B_REV_D (1 << 4) #define URTW_RTL8187B_REV_E (1 << 5) #define URTW_DETACHED (1 << 6) #define URTW_RUNNING (1 << 7) enum ieee80211_state sc_state; int sc_epromtype; #define URTW_EEPROM_93C46 0 #define URTW_EEPROM_93C56 1 uint8_t sc_crcmon; struct ieee80211_channel *sc_curchan; /* for RF */ usb_error_t (*sc_rf_init)(struct urtw_softc *); usb_error_t (*sc_rf_set_chan)(struct urtw_softc *, int); usb_error_t (*sc_rf_set_sens)(struct urtw_softc *, int); usb_error_t (*sc_rf_stop)(struct urtw_softc *); uint8_t sc_rfchip; uint32_t sc_max_sens; uint32_t sc_sens; /* for LED */ struct usb_callout sc_led_ch; struct task sc_led_task; uint8_t sc_psr; uint8_t sc_strategy; #define URTW_LED_GPIO 1 uint8_t sc_gpio_ledon; uint8_t sc_gpio_ledinprogress; uint8_t sc_gpio_ledstate; uint8_t sc_gpio_ledpin; uint8_t sc_gpio_blinktime; uint8_t sc_gpio_blinkstate; /* RX/TX */ struct usb_xfer *sc_xfer[URTW_8187B_N_XFERS]; #define URTW_PRIORITY_LOW 0 #define URTW_PRIORITY_NORMAL 1 #define URTW_DATA_TIMEOUT 10000 /* 10 sec */ #define URTW_8187B_TXPIPE_BE 0x6 /* best effort */ #define URTW_8187B_TXPIPE_BK 0x7 /* background */ #define URTW_8187B_TXPIPE_VI 0x5 /* video */ #define URTW_8187B_TXPIPE_VO 0x4 /* voice */ #define URTW_8187B_TXPIPE_MAX 4 struct urtw_data sc_rx[URTW_RX_DATA_LIST_COUNT]; urtw_datahead sc_rx_active; urtw_datahead sc_rx_inactive; struct urtw_data sc_tx[URTW_TX_DATA_LIST_COUNT]; urtw_datahead sc_tx_active; urtw_datahead sc_tx_inactive; urtw_datahead sc_tx_pending; uint8_t sc_rts_retry; uint8_t sc_tx_retry; uint8_t sc_preamble_mode; #define URTW_PREAMBLE_MODE_SHORT 1 #define URTW_PREAMBLE_MODE_LONG 2 struct callout sc_watchdog_ch; int sc_txtimer; int sc_currate; /* TX power */ uint8_t sc_txpwr_cck[URTW_MAX_CHANNELS]; uint8_t sc_txpwr_cck_base; uint8_t sc_txpwr_ofdm[URTW_MAX_CHANNELS]; uint8_t sc_txpwr_ofdm_base; uint8_t sc_acmctl; uint64_t sc_txstatus; /* only for 8187B */ struct task sc_updateslot_task; struct urtw_stats sc_stats; struct urtw_rx_radiotap_header sc_rxtap; - int sc_rxtap_len; struct urtw_tx_radiotap_header sc_txtap; - int sc_txtap_len; }; #define URTW_LOCK(sc) mtx_lock(&(sc)->sc_mtx) #define URTW_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) #define URTW_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) Index: head/sys/dev/usb/wlan/if_zydreg.h =================================================================== --- head/sys/dev/usb/wlan/if_zydreg.h (revision 289167) +++ head/sys/dev/usb/wlan/if_zydreg.h (revision 289168) @@ -1,1315 +1,1313 @@ /* $OpenBSD: if_zydreg.h,v 1.19 2006/11/30 19:28:07 damien Exp $ */ /* $NetBSD: if_zydreg.h,v 1.2 2007/06/16 11:18:45 kiyohara Exp $ */ /* $FreeBSD$ */ /*- * Copyright (c) 2006 by Damien Bergamini * Copyright (c) 2006 by Florian Stoehr * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ /* * ZyDAS ZD1211/ZD1211B USB WLAN driver. */ #define ZYD_CR_GPI_EN 0x9418 #define ZYD_CR_RADIO_PD 0x942c #define ZYD_CR_RF2948_PD 0x942c #define ZYD_CR_EN_PS_MANUAL_AGC 0x943c #define ZYD_CR_CONFIG_PHILIPS 0x9440 #define ZYD_CR_I2C_WRITE 0x9444 #define ZYD_CR_SA2400_SER_RP 0x9448 #define ZYD_CR_RADIO_PE 0x9458 #define ZYD_CR_RST_BUS_MASTER 0x945c #define ZYD_CR_RFCFG 0x9464 #define ZYD_CR_HSTSCHG 0x946c #define ZYD_CR_PHY_ON 0x9474 #define ZYD_CR_RX_DELAY 0x9478 #define ZYD_CR_RX_PE_DELAY 0x947c #define ZYD_CR_GPIO_1 0x9490 #define ZYD_CR_GPIO_2 0x9494 #define ZYD_CR_EnZYD_CRyBufMux 0x94a8 #define ZYD_CR_PS_CTRL 0x9500 #define ZYD_CR_ADDA_PWR_DWN 0x9504 #define ZYD_CR_ADDA_MBIAS_WT 0x9508 #define ZYD_CR_INTERRUPT 0x9510 #define ZYD_CR_MAC_PS_STATE 0x950c #define ZYD_CR_ATIM_WND_PERIOD 0x951c #define ZYD_CR_BCN_INTERVAL 0x9520 #define ZYD_CR_PRE_TBTT 0x9524 /* * MAC registers. */ #define ZYD_MAC_MACADRL 0x9610 /* MAC address (low) */ #define ZYD_MAC_MACADRH 0x9614 /* MAC address (high) */ #define ZYD_MAC_BSSADRL 0x9618 /* BSS address (low) */ #define ZYD_MAC_BSSADRH 0x961c /* BSS address (high) */ #define ZYD_MAC_BCNCFG 0x9620 /* BCN configuration */ #define ZYD_MAC_GHTBL 0x9624 /* Group hash table (low) */ #define ZYD_MAC_GHTBH 0x9628 /* Group hash table (high) */ #define ZYD_MAC_RX_TIMEOUT 0x962c /* Rx timeout value */ #define ZYD_MAC_BAS_RATE 0x9630 /* Basic rate setting */ #define ZYD_MAC_MAN_RATE 0x9634 /* Mandatory rate setting */ #define ZYD_MAC_RTSCTSRATE 0x9638 /* RTS CTS rate */ #define ZYD_MAC_BACKOFF_PROTECT 0x963c /* Backoff protection */ #define ZYD_MAC_RX_THRESHOLD 0x9640 /* Rx threshold */ #define ZYD_MAC_TX_PE_CONTROL 0x9644 /* Tx_PE control */ #define ZYD_MAC_AFTER_PNP 0x9648 /* After PnP */ #define ZYD_MAC_RX_PE_DELAY 0x964c /* Rx_pe delay */ #define ZYD_MAC_RX_ADDR2_L 0x9650 /* RX address2 (low) */ #define ZYD_MAC_RX_ADDR2_H 0x9654 /* RX address2 (high) */ #define ZYD_MAC_SIFS_ACK_TIME 0x9658 /* Dynamic SIFS ack time */ #define ZYD_MAC_PHY_DELAY 0x9660 /* PHY delay */ #define ZYD_MAC_PHY_DELAY2 0x966c /* PHY delay */ #define ZYD_MAC_BCNFIFO 0x9670 /* Beacon FIFO I/O port */ #define ZYD_MAC_SNIFFER 0x9674 /* Sniffer on/off */ #define ZYD_MAC_ENCRYPTION_TYPE 0x9678 /* Encryption type */ #define ZYD_MAC_RETRY 0x967c /* Retry time */ #define ZYD_MAC_MISC 0x9680 /* Misc */ #define ZYD_MAC_STMACHINESTAT 0x9684 /* State machine status */ #define ZYD_MAC_TX_UNDERRUN_CNT 0x9688 /* TX underrun counter */ #define ZYD_MAC_RXFILTER 0x968c /* Send to host settings */ #define ZYD_MAC_ACK_EXT 0x9690 /* Acknowledge extension */ #define ZYD_MAC_BCNFIFOST 0x9694 /* BCN FIFO set and status */ #define ZYD_MAC_DIFS_EIFS_SIFS 0x9698 /* DIFS, EIFS & SIFS settings */ #define ZYD_MAC_RX_TIMEOUT_CNT 0x969c /* RX timeout count */ #define ZYD_MAC_RX_TOTAL_FRAME 0x96a0 /* RX total frame count */ #define ZYD_MAC_RX_CRC32_CNT 0x96a4 /* RX CRC32 frame count */ #define ZYD_MAC_RX_CRC16_CNT 0x96a8 /* RX CRC16 frame count */ #define ZYD_MAC_RX_UDEC 0x96ac /* RX unicast decr. error count */ #define ZYD_MAC_RX_OVERRUN_CNT 0x96b0 /* RX FIFO overrun count */ #define ZYD_MAC_RX_MDEC 0x96bc /* RX multicast decr. err. cnt. */ #define ZYD_MAC_NAV_TCR 0x96c4 /* NAV timer count read */ #define ZYD_MAC_BACKOFF_ST_RD 0x96c8 /* Backoff status read */ #define ZYD_MAC_DM_RETRY_CNT_RD 0x96cc /* DM retry count read */ #define ZYD_MAC_RX_ACR 0x96d0 /* RX arbitration count read */ #define ZYD_MAC_TX_CCR 0x96d4 /* Tx complete count read */ #define ZYD_MAC_TCB_ADDR 0x96e8 /* Current PCI process TCP addr */ #define ZYD_MAC_RCB_ADDR 0x96ec /* Next RCB address */ #define ZYD_MAC_CONT_WIN_LIMIT 0x96f0 /* Contention window limit */ #define ZYD_MAC_TX_PKT 0x96f4 /* Tx total packet count read */ #define ZYD_MAC_DL_CTRL 0x96f8 /* Download control */ #define ZYD_MAC_CAM_MODE 0x9700 /* CAM: Continuous Access Mode */ #define ZYD_MACB_TXPWR_CTL1 0x9b00 #define ZYD_MACB_TXPWR_CTL2 0x9b04 #define ZYD_MACB_TXPWR_CTL3 0x9b08 #define ZYD_MACB_TXPWR_CTL4 0x9b0c #define ZYD_MACB_AIFS_CTL1 0x9b10 #define ZYD_MACB_AIFS_CTL2 0x9b14 #define ZYD_MACB_TXOP 0x9b20 #define ZYD_MACB_MAX_RETRY 0x9b28 /* * Miscellaneous registers. */ #define ZYD_FIRMWARE_START_ADDR 0xee00 #define ZYD_FIRMWARE_BASE_ADDR 0xee1d /* Firmware base address */ /* * EEPROM registers. */ #define ZYD_EEPROM_START_HEAD 0xf800 /* EEPROM start */ #define ZYD_EEPROM_SUBID 0xf817 #define ZYD_EEPROM_POD 0xf819 #define ZYD_EEPROM_MAC_ADDR_P1 0xf81b /* Part 1 of the MAC address */ #define ZYD_EEPROM_MAC_ADDR_P2 0xf81d /* Part 2 of the MAC address */ #define ZYD_EEPROM_PWR_CAL 0xf81f /* Calibration */ #define ZYD_EEPROM_PWR_INT 0xf827 /* Calibration */ #define ZYD_EEPROM_ALLOWEDCHAN 0xf82f /* Allowed CH mask, 1 bit each */ #define ZYD_EEPROM_DEVICE_VER 0xf837 /* Device version */ #define ZYD_EEPROM_PHY_REG 0xf83c /* PHY registers */ #define ZYD_EEPROM_36M_CAL 0xf83f /* Calibration */ #define ZYD_EEPROM_11A_INT 0xf847 /* Interpolation */ #define ZYD_EEPROM_48M_CAL 0xf84f /* Calibration */ #define ZYD_EEPROM_48M_INT 0xf857 /* Interpolation */ #define ZYD_EEPROM_54M_CAL 0xf85f /* Calibration */ #define ZYD_EEPROM_54M_INT 0xf867 /* Interpolation */ /* * Firmware registers offsets (relative to fwbase). */ #define ZYD_FW_FIRMWARE_REV 0x0000 /* Firmware version */ #define ZYD_FW_USB_SPEED 0x0001 /* USB speed (!=0 if highspeed) */ #define ZYD_FW_FIX_TX_RATE 0x0002 /* Fixed TX rate */ #define ZYD_FW_LINK_STATUS 0x0003 #define ZYD_FW_SOFT_RESET 0x0004 #define ZYD_FW_FLASH_CHK 0x0005 /* possible flags for register ZYD_FW_LINK_STATUS */ #define ZYD_LED1 (1 << 8) #define ZYD_LED2 (1 << 9) /* * RF IDs. */ #define ZYD_RF_UW2451 0x2 /* not supported yet */ #define ZYD_RF_UCHIP 0x3 /* not supported yet */ #define ZYD_RF_AL2230 0x4 #define ZYD_RF_AL7230B 0x5 #define ZYD_RF_THETA 0x6 /* not supported yet */ #define ZYD_RF_AL2210 0x7 #define ZYD_RF_MAXIM_NEW 0x8 #define ZYD_RF_GCT 0x9 #define ZYD_RF_AL2230S 0xa /* not supported yet */ #define ZYD_RF_RALINK 0xb /* not supported yet */ #define ZYD_RF_INTERSIL 0xc /* not supported yet */ #define ZYD_RF_RFMD 0xd #define ZYD_RF_MAXIM_NEW2 0xe #define ZYD_RF_PHILIPS 0xf /* not supported yet */ /* * PHY registers (8 bits, not documented). */ #define ZYD_CR0 0x9000 #define ZYD_CR1 0x9004 #define ZYD_CR2 0x9008 #define ZYD_CR3 0x900c #define ZYD_CR5 0x9010 #define ZYD_CR6 0x9014 #define ZYD_CR7 0x9018 #define ZYD_CR8 0x901c #define ZYD_CR4 0x9020 #define ZYD_CR9 0x9024 #define ZYD_CR10 0x9028 #define ZYD_CR11 0x902c #define ZYD_CR12 0x9030 #define ZYD_CR13 0x9034 #define ZYD_CR14 0x9038 #define ZYD_CR15 0x903c #define ZYD_CR16 0x9040 #define ZYD_CR17 0x9044 #define ZYD_CR18 0x9048 #define ZYD_CR19 0x904c #define ZYD_CR20 0x9050 #define ZYD_CR21 0x9054 #define ZYD_CR22 0x9058 #define ZYD_CR23 0x905c #define ZYD_CR24 0x9060 #define ZYD_CR25 0x9064 #define ZYD_CR26 0x9068 #define ZYD_CR27 0x906c #define ZYD_CR28 0x9070 #define ZYD_CR29 0x9074 #define ZYD_CR30 0x9078 #define ZYD_CR31 0x907c #define ZYD_CR32 0x9080 #define ZYD_CR33 0x9084 #define ZYD_CR34 0x9088 #define ZYD_CR35 0x908c #define ZYD_CR36 0x9090 #define ZYD_CR37 0x9094 #define ZYD_CR38 0x9098 #define ZYD_CR39 0x909c #define ZYD_CR40 0x90a0 #define ZYD_CR41 0x90a4 #define ZYD_CR42 0x90a8 #define ZYD_CR43 0x90ac #define ZYD_CR44 0x90b0 #define ZYD_CR45 0x90b4 #define ZYD_CR46 0x90b8 #define ZYD_CR47 0x90bc #define ZYD_CR48 0x90c0 #define ZYD_CR49 0x90c4 #define ZYD_CR50 0x90c8 #define ZYD_CR51 0x90cc #define ZYD_CR52 0x90d0 #define ZYD_CR53 0x90d4 #define ZYD_CR54 0x90d8 #define ZYD_CR55 0x90dc #define ZYD_CR56 0x90e0 #define ZYD_CR57 0x90e4 #define ZYD_CR58 0x90e8 #define ZYD_CR59 0x90ec #define ZYD_CR60 0x90f0 #define ZYD_CR61 0x90f4 #define ZYD_CR62 0x90f8 #define ZYD_CR63 0x90fc #define ZYD_CR64 0x9100 #define ZYD_CR65 0x9104 #define ZYD_CR66 0x9108 #define ZYD_CR67 0x910c #define ZYD_CR68 0x9110 #define ZYD_CR69 0x9114 #define ZYD_CR70 0x9118 #define ZYD_CR71 0x911c #define ZYD_CR72 0x9120 #define ZYD_CR73 0x9124 #define ZYD_CR74 0x9128 #define ZYD_CR75 0x912c #define ZYD_CR76 0x9130 #define ZYD_CR77 0x9134 #define ZYD_CR78 0x9138 #define ZYD_CR79 0x913c #define ZYD_CR80 0x9140 #define ZYD_CR81 0x9144 #define ZYD_CR82 0x9148 #define ZYD_CR83 0x914c #define ZYD_CR84 0x9150 #define ZYD_CR85 0x9154 #define ZYD_CR86 0x9158 #define ZYD_CR87 0x915c #define ZYD_CR88 0x9160 #define ZYD_CR89 0x9164 #define ZYD_CR90 0x9168 #define ZYD_CR91 0x916c #define ZYD_CR92 0x9170 #define ZYD_CR93 0x9174 #define ZYD_CR94 0x9178 #define ZYD_CR95 0x917c #define ZYD_CR96 0x9180 #define ZYD_CR97 0x9184 #define ZYD_CR98 0x9188 #define ZYD_CR99 0x918c #define ZYD_CR100 0x9190 #define ZYD_CR101 0x9194 #define ZYD_CR102 0x9198 #define ZYD_CR103 0x919c #define ZYD_CR104 0x91a0 #define ZYD_CR105 0x91a4 #define ZYD_CR106 0x91a8 #define ZYD_CR107 0x91ac #define ZYD_CR108 0x91b0 #define ZYD_CR109 0x91b4 #define ZYD_CR110 0x91b8 #define ZYD_CR111 0x91bc #define ZYD_CR112 0x91c0 #define ZYD_CR113 0x91c4 #define ZYD_CR114 0x91c8 #define ZYD_CR115 0x91cc #define ZYD_CR116 0x91d0 #define ZYD_CR117 0x91d4 #define ZYD_CR118 0x91d8 #define ZYD_CR119 0x91dc #define ZYD_CR120 0x91e0 #define ZYD_CR121 0x91e4 #define ZYD_CR122 0x91e8 #define ZYD_CR123 0x91ec #define ZYD_CR124 0x91f0 #define ZYD_CR125 0x91f4 #define ZYD_CR126 0x91f8 #define ZYD_CR127 0x91fc #define ZYD_CR128 0x9200 #define ZYD_CR129 0x9204 #define ZYD_CR130 0x9208 #define ZYD_CR131 0x920c #define ZYD_CR132 0x9210 #define ZYD_CR133 0x9214 #define ZYD_CR134 0x9218 #define ZYD_CR135 0x921c #define ZYD_CR136 0x9220 #define ZYD_CR137 0x9224 #define ZYD_CR138 0x9228 #define ZYD_CR139 0x922c #define ZYD_CR140 0x9230 #define ZYD_CR141 0x9234 #define ZYD_CR142 0x9238 #define ZYD_CR143 0x923c #define ZYD_CR144 0x9240 #define ZYD_CR145 0x9244 #define ZYD_CR146 0x9248 #define ZYD_CR147 0x924c #define ZYD_CR148 0x9250 #define ZYD_CR149 0x9254 #define ZYD_CR150 0x9258 #define ZYD_CR151 0x925c #define ZYD_CR152 0x9260 #define ZYD_CR153 0x9264 #define ZYD_CR154 0x9268 #define ZYD_CR155 0x926c #define ZYD_CR156 0x9270 #define ZYD_CR157 0x9274 #define ZYD_CR158 0x9278 #define ZYD_CR159 0x927c #define ZYD_CR160 0x9280 #define ZYD_CR161 0x9284 #define ZYD_CR162 0x9288 #define ZYD_CR163 0x928c #define ZYD_CR164 0x9290 #define ZYD_CR165 0x9294 #define ZYD_CR166 0x9298 #define ZYD_CR167 0x929c #define ZYD_CR168 0x92a0 #define ZYD_CR169 0x92a4 #define ZYD_CR170 0x92a8 #define ZYD_CR171 0x92ac #define ZYD_CR172 0x92b0 #define ZYD_CR173 0x92b4 #define ZYD_CR174 0x92b8 #define ZYD_CR175 0x92bc #define ZYD_CR176 0x92c0 #define ZYD_CR177 0x92c4 #define ZYD_CR178 0x92c8 #define ZYD_CR179 0x92cc #define ZYD_CR180 0x92d0 #define ZYD_CR181 0x92d4 #define ZYD_CR182 0x92d8 #define ZYD_CR183 0x92dc #define ZYD_CR184 0x92e0 #define ZYD_CR185 0x92e4 #define ZYD_CR186 0x92e8 #define ZYD_CR187 0x92ec #define ZYD_CR188 0x92f0 #define ZYD_CR189 0x92f4 #define ZYD_CR190 0x92f8 #define ZYD_CR191 0x92fc #define ZYD_CR192 0x9300 #define ZYD_CR193 0x9304 #define ZYD_CR194 0x9308 #define ZYD_CR195 0x930c #define ZYD_CR196 0x9310 #define ZYD_CR197 0x9314 #define ZYD_CR198 0x9318 #define ZYD_CR199 0x931c #define ZYD_CR200 0x9320 #define ZYD_CR201 0x9324 #define ZYD_CR202 0x9328 #define ZYD_CR203 0x932c #define ZYD_CR204 0x9330 #define ZYD_CR205 0x9334 #define ZYD_CR206 0x9338 #define ZYD_CR207 0x933c #define ZYD_CR208 0x9340 #define ZYD_CR209 0x9344 #define ZYD_CR210 0x9348 #define ZYD_CR211 0x934c #define ZYD_CR212 0x9350 #define ZYD_CR213 0x9354 #define ZYD_CR214 0x9358 #define ZYD_CR215 0x935c #define ZYD_CR216 0x9360 #define ZYD_CR217 0x9364 #define ZYD_CR218 0x9368 #define ZYD_CR219 0x936c #define ZYD_CR220 0x9370 #define ZYD_CR221 0x9374 #define ZYD_CR222 0x9378 #define ZYD_CR223 0x937c #define ZYD_CR224 0x9380 #define ZYD_CR225 0x9384 #define ZYD_CR226 0x9388 #define ZYD_CR227 0x938c #define ZYD_CR228 0x9390 #define ZYD_CR229 0x9394 #define ZYD_CR230 0x9398 #define ZYD_CR231 0x939c #define ZYD_CR232 0x93a0 #define ZYD_CR233 0x93a4 #define ZYD_CR234 0x93a8 #define ZYD_CR235 0x93ac #define ZYD_CR236 0x93b0 #define ZYD_CR240 0x93c0 #define ZYD_CR241 0x93c4 #define ZYD_CR242 0x93c8 #define ZYD_CR243 0x93cc #define ZYD_CR244 0x93d0 #define ZYD_CR245 0x93d4 #define ZYD_CR251 0x93ec #define ZYD_CR252 0x93f0 #define ZYD_CR253 0x93f4 #define ZYD_CR254 0x93f8 #define ZYD_CR255 0x93fc /* copied nearly verbatim from the Linux driver rewrite */ #define ZYD_DEF_PHY \ { \ { ZYD_CR0, 0x0a }, { ZYD_CR1, 0x06 }, { ZYD_CR2, 0x26 }, \ { ZYD_CR3, 0x38 }, { ZYD_CR4, 0x80 }, { ZYD_CR9, 0xa0 }, \ { ZYD_CR10, 0x81 }, { ZYD_CR11, 0x00 }, { ZYD_CR12, 0x7f }, \ { ZYD_CR13, 0x8c }, { ZYD_CR14, 0x80 }, { ZYD_CR15, 0x3d }, \ { ZYD_CR16, 0x20 }, { ZYD_CR17, 0x1e }, { ZYD_CR18, 0x0a }, \ { ZYD_CR19, 0x48 }, { ZYD_CR20, 0x0c }, { ZYD_CR21, 0x0c }, \ { ZYD_CR22, 0x23 }, { ZYD_CR23, 0x90 }, { ZYD_CR24, 0x14 }, \ { ZYD_CR25, 0x40 }, { ZYD_CR26, 0x10 }, { ZYD_CR27, 0x19 }, \ { ZYD_CR28, 0x7f }, { ZYD_CR29, 0x80 }, { ZYD_CR30, 0x4b }, \ { ZYD_CR31, 0x60 }, { ZYD_CR32, 0x43 }, { ZYD_CR33, 0x08 }, \ { ZYD_CR34, 0x06 }, { ZYD_CR35, 0x0a }, { ZYD_CR36, 0x00 }, \ { ZYD_CR37, 0x00 }, { ZYD_CR38, 0x38 }, { ZYD_CR39, 0x0c }, \ { ZYD_CR40, 0x84 }, { ZYD_CR41, 0x2a }, { ZYD_CR42, 0x80 }, \ { ZYD_CR43, 0x10 }, { ZYD_CR44, 0x12 }, { ZYD_CR46, 0xff }, \ { ZYD_CR47, 0x1e }, { ZYD_CR48, 0x26 }, { ZYD_CR49, 0x5b }, \ { ZYD_CR64, 0xd0 }, { ZYD_CR65, 0x04 }, { ZYD_CR66, 0x58 }, \ { ZYD_CR67, 0xc9 }, { ZYD_CR68, 0x88 }, { ZYD_CR69, 0x41 }, \ { ZYD_CR70, 0x23 }, { ZYD_CR71, 0x10 }, { ZYD_CR72, 0xff }, \ { ZYD_CR73, 0x32 }, { ZYD_CR74, 0x30 }, { ZYD_CR75, 0x65 }, \ { ZYD_CR76, 0x41 }, { ZYD_CR77, 0x1b }, { ZYD_CR78, 0x30 }, \ { ZYD_CR79, 0x68 }, { ZYD_CR80, 0x64 }, { ZYD_CR81, 0x64 }, \ { ZYD_CR82, 0x00 }, { ZYD_CR83, 0x00 }, { ZYD_CR84, 0x00 }, \ { ZYD_CR85, 0x02 }, { ZYD_CR86, 0x00 }, { ZYD_CR87, 0x00 }, \ { ZYD_CR88, 0xff }, { ZYD_CR89, 0xfc }, { ZYD_CR90, 0x00 }, \ { ZYD_CR91, 0x00 }, { ZYD_CR92, 0x00 }, { ZYD_CR93, 0x08 }, \ { ZYD_CR94, 0x00 }, { ZYD_CR95, 0x00 }, { ZYD_CR96, 0xff }, \ { ZYD_CR97, 0xe7 }, { ZYD_CR98, 0x00 }, { ZYD_CR99, 0x00 }, \ { ZYD_CR100, 0x00 }, { ZYD_CR101, 0xae }, { ZYD_CR102, 0x02 }, \ { ZYD_CR103, 0x00 }, { ZYD_CR104, 0x03 }, { ZYD_CR105, 0x65 }, \ { ZYD_CR106, 0x04 }, { ZYD_CR107, 0x00 }, { ZYD_CR108, 0x0a }, \ { ZYD_CR109, 0xaa }, { ZYD_CR110, 0xaa }, { ZYD_CR111, 0x25 }, \ { ZYD_CR112, 0x25 }, { ZYD_CR113, 0x00 }, { ZYD_CR119, 0x1e }, \ { ZYD_CR125, 0x90 }, { ZYD_CR126, 0x00 }, { ZYD_CR127, 0x00 }, \ { ZYD_CR5, 0x00 }, { ZYD_CR6, 0x00 }, { ZYD_CR7, 0x00 }, \ { ZYD_CR8, 0x00 }, { ZYD_CR9, 0x20 }, { ZYD_CR12, 0xf0 }, \ { ZYD_CR20, 0x0e }, { ZYD_CR21, 0x0e }, { ZYD_CR27, 0x10 }, \ { ZYD_CR44, 0x33 }, { ZYD_CR47, 0x1E }, { ZYD_CR83, 0x24 }, \ { ZYD_CR84, 0x04 }, { ZYD_CR85, 0x00 }, { ZYD_CR86, 0x0C }, \ { ZYD_CR87, 0x12 }, { ZYD_CR88, 0x0C }, { ZYD_CR89, 0x00 }, \ { ZYD_CR90, 0x10 }, { ZYD_CR91, 0x08 }, { ZYD_CR93, 0x00 }, \ { ZYD_CR94, 0x01 }, { ZYD_CR95, 0x00 }, { ZYD_CR96, 0x50 }, \ { ZYD_CR97, 0x37 }, { ZYD_CR98, 0x35 }, { ZYD_CR101, 0x13 }, \ { ZYD_CR102, 0x27 }, { ZYD_CR103, 0x27 }, { ZYD_CR104, 0x18 }, \ { ZYD_CR105, 0x12 }, { ZYD_CR109, 0x27 }, { ZYD_CR110, 0x27 }, \ { ZYD_CR111, 0x27 }, { ZYD_CR112, 0x27 }, { ZYD_CR113, 0x27 }, \ { ZYD_CR114, 0x27 }, { ZYD_CR115, 0x26 }, { ZYD_CR116, 0x24 }, \ { ZYD_CR117, 0xfc }, { ZYD_CR118, 0xfa }, { ZYD_CR120, 0x4f }, \ { ZYD_CR125, 0xaa }, { ZYD_CR127, 0x03 }, { ZYD_CR128, 0x14 }, \ { ZYD_CR129, 0x12 }, { ZYD_CR130, 0x10 }, { ZYD_CR131, 0x0C }, \ { ZYD_CR136, 0xdf }, { ZYD_CR137, 0x40 }, { ZYD_CR138, 0xa0 }, \ { ZYD_CR139, 0xb0 }, { ZYD_CR140, 0x99 }, { ZYD_CR141, 0x82 }, \ { ZYD_CR142, 0x54 }, { ZYD_CR143, 0x1c }, { ZYD_CR144, 0x6c }, \ { ZYD_CR147, 0x07 }, { ZYD_CR148, 0x4c }, { ZYD_CR149, 0x50 }, \ { ZYD_CR150, 0x0e }, { ZYD_CR151, 0x18 }, { ZYD_CR160, 0xfe }, \ { ZYD_CR161, 0xee }, { ZYD_CR162, 0xaa }, { ZYD_CR163, 0xfa }, \ { ZYD_CR164, 0xfa }, { ZYD_CR165, 0xea }, { ZYD_CR166, 0xbe }, \ { ZYD_CR167, 0xbe }, { ZYD_CR168, 0x6a }, { ZYD_CR169, 0xba }, \ { ZYD_CR170, 0xba }, { ZYD_CR171, 0xba }, { ZYD_CR204, 0x7d }, \ { ZYD_CR203, 0x30 }, { 0, 0} \ } #define ZYD_DEF_PHYB \ { \ { ZYD_CR0, 0x14 }, { ZYD_CR1, 0x06 }, { ZYD_CR2, 0x26 }, \ { ZYD_CR3, 0x38 }, { ZYD_CR4, 0x80 }, { ZYD_CR9, 0xe0 }, \ { ZYD_CR10, 0x81 }, { ZYD_CR11, 0x00 }, { ZYD_CR12, 0xf0 }, \ { ZYD_CR13, 0x8c }, { ZYD_CR14, 0x80 }, { ZYD_CR15, 0x3d }, \ { ZYD_CR16, 0x20 }, { ZYD_CR17, 0x1e }, { ZYD_CR18, 0x0a }, \ { ZYD_CR19, 0x48 }, { ZYD_CR20, 0x10 }, { ZYD_CR21, 0x0e }, \ { ZYD_CR22, 0x23 }, { ZYD_CR23, 0x90 }, { ZYD_CR24, 0x14 }, \ { ZYD_CR25, 0x40 }, { ZYD_CR26, 0x10 }, { ZYD_CR27, 0x10 }, \ { ZYD_CR28, 0x7f }, { ZYD_CR29, 0x80 }, { ZYD_CR30, 0x4b }, \ { ZYD_CR31, 0x60 }, { ZYD_CR32, 0x43 }, { ZYD_CR33, 0x08 }, \ { ZYD_CR34, 0x06 }, { ZYD_CR35, 0x0a }, { ZYD_CR36, 0x00 }, \ { ZYD_CR37, 0x00 }, { ZYD_CR38, 0x38 }, { ZYD_CR39, 0x0c }, \ { ZYD_CR40, 0x84 }, { ZYD_CR41, 0x2a }, { ZYD_CR42, 0x80 }, \ { ZYD_CR43, 0x10 }, { ZYD_CR44, 0x33 }, { ZYD_CR46, 0xff }, \ { ZYD_CR47, 0x1E }, { ZYD_CR48, 0x26 }, { ZYD_CR49, 0x5b }, \ { ZYD_CR64, 0xd0 }, { ZYD_CR65, 0x04 }, { ZYD_CR66, 0x58 }, \ { ZYD_CR67, 0xc9 }, { ZYD_CR68, 0x88 }, { ZYD_CR69, 0x41 }, \ { ZYD_CR70, 0x23 }, { ZYD_CR71, 0x10 }, { ZYD_CR72, 0xff }, \ { ZYD_CR73, 0x32 }, { ZYD_CR74, 0x30 }, { ZYD_CR75, 0x65 }, \ { ZYD_CR76, 0x41 }, { ZYD_CR77, 0x1b }, { ZYD_CR78, 0x30 }, \ { ZYD_CR79, 0xf0 }, { ZYD_CR80, 0x64 }, { ZYD_CR81, 0x64 }, \ { ZYD_CR82, 0x00 }, { ZYD_CR83, 0x24 }, { ZYD_CR84, 0x04 }, \ { ZYD_CR85, 0x00 }, { ZYD_CR86, 0x0c }, { ZYD_CR87, 0x12 }, \ { ZYD_CR88, 0x0c }, { ZYD_CR89, 0x00 }, { ZYD_CR90, 0x58 }, \ { ZYD_CR91, 0x04 }, { ZYD_CR92, 0x00 }, { ZYD_CR93, 0x00 }, \ { ZYD_CR94, 0x01 }, { ZYD_CR95, 0x20 }, { ZYD_CR96, 0x50 }, \ { ZYD_CR97, 0x37 }, { ZYD_CR98, 0x35 }, { ZYD_CR99, 0x00 }, \ { ZYD_CR100, 0x01 }, { ZYD_CR101, 0x13 }, { ZYD_CR102, 0x27 }, \ { ZYD_CR103, 0x27 }, { ZYD_CR104, 0x18 }, { ZYD_CR105, 0x12 }, \ { ZYD_CR106, 0x04 }, { ZYD_CR107, 0x00 }, { ZYD_CR108, 0x0a }, \ { ZYD_CR109, 0x27 }, { ZYD_CR110, 0x27 }, { ZYD_CR111, 0x27 }, \ { ZYD_CR112, 0x27 }, { ZYD_CR113, 0x27 }, { ZYD_CR114, 0x27 }, \ { ZYD_CR115, 0x26 }, { ZYD_CR116, 0x24 }, { ZYD_CR117, 0xfc }, \ { ZYD_CR118, 0xfa }, { ZYD_CR119, 0x1e }, { ZYD_CR125, 0x90 }, \ { ZYD_CR126, 0x00 }, { ZYD_CR127, 0x00 }, { ZYD_CR128, 0x14 }, \ { ZYD_CR129, 0x12 }, { ZYD_CR130, 0x10 }, { ZYD_CR131, 0x0c }, \ { ZYD_CR136, 0xdf }, { ZYD_CR137, 0xa0 }, { ZYD_CR138, 0xa8 }, \ { ZYD_CR139, 0xb4 }, { ZYD_CR140, 0x98 }, { ZYD_CR141, 0x82 }, \ { ZYD_CR142, 0x53 }, { ZYD_CR143, 0x1c }, { ZYD_CR144, 0x6c }, \ { ZYD_CR147, 0x07 }, { ZYD_CR148, 0x40 }, { ZYD_CR149, 0x40 }, \ { ZYD_CR150, 0x14 }, { ZYD_CR151, 0x18 }, { ZYD_CR159, 0x70 }, \ { ZYD_CR160, 0xfe }, { ZYD_CR161, 0xee }, { ZYD_CR162, 0xaa }, \ { ZYD_CR163, 0xfa }, { ZYD_CR164, 0xfa }, { ZYD_CR165, 0xea }, \ { ZYD_CR166, 0xbe }, { ZYD_CR167, 0xbe }, { ZYD_CR168, 0x6a }, \ { ZYD_CR169, 0xba }, { ZYD_CR170, 0xba }, { ZYD_CR171, 0xba }, \ { ZYD_CR204, 0x7d }, { ZYD_CR203, 0x30 }, \ { 0, 0 } \ } #define ZYD_RFMD_PHY \ { \ { ZYD_CR2, 0x1e }, { ZYD_CR9, 0x20 }, { ZYD_CR10, 0x89 }, \ { ZYD_CR11, 0x00 }, { ZYD_CR15, 0xd0 }, { ZYD_CR17, 0x68 }, \ { ZYD_CR19, 0x4a }, { ZYD_CR20, 0x0c }, { ZYD_CR21, 0x0e }, \ { ZYD_CR23, 0x48 }, { ZYD_CR24, 0x14 }, { ZYD_CR26, 0x90 }, \ { ZYD_CR27, 0x30 }, { ZYD_CR29, 0x20 }, { ZYD_CR31, 0xb2 }, \ { ZYD_CR32, 0x43 }, { ZYD_CR33, 0x28 }, { ZYD_CR38, 0x30 }, \ { ZYD_CR34, 0x0f }, { ZYD_CR35, 0xf0 }, { ZYD_CR41, 0x2a }, \ { ZYD_CR46, 0x7f }, { ZYD_CR47, 0x1e }, { ZYD_CR51, 0xc5 }, \ { ZYD_CR52, 0xc5 }, { ZYD_CR53, 0xc5 }, { ZYD_CR79, 0x58 }, \ { ZYD_CR80, 0x30 }, { ZYD_CR81, 0x30 }, { ZYD_CR82, 0x00 }, \ { ZYD_CR83, 0x24 }, { ZYD_CR84, 0x04 }, { ZYD_CR85, 0x00 }, \ { ZYD_CR86, 0x10 }, { ZYD_CR87, 0x2a }, { ZYD_CR88, 0x10 }, \ { ZYD_CR89, 0x24 }, { ZYD_CR90, 0x18 }, { ZYD_CR91, 0x00 }, \ { ZYD_CR92, 0x0a }, { ZYD_CR93, 0x00 }, { ZYD_CR94, 0x01 }, \ { ZYD_CR95, 0x00 }, { ZYD_CR96, 0x40 }, { ZYD_CR97, 0x37 }, \ { ZYD_CR98, 0x05 }, { ZYD_CR99, 0x28 }, { ZYD_CR100, 0x00 }, \ { ZYD_CR101, 0x13 }, { ZYD_CR102, 0x27 }, { ZYD_CR103, 0x27 }, \ { ZYD_CR104, 0x18 }, { ZYD_CR105, 0x12 }, { ZYD_CR106, 0x1a }, \ { ZYD_CR107, 0x24 }, { ZYD_CR108, 0x0a }, { ZYD_CR109, 0x13 }, \ { ZYD_CR110, 0x2f }, { ZYD_CR111, 0x27 }, { ZYD_CR112, 0x27 }, \ { ZYD_CR113, 0x27 }, { ZYD_CR114, 0x27 }, { ZYD_CR115, 0x40 }, \ { ZYD_CR116, 0x40 }, { ZYD_CR117, 0xf0 }, { ZYD_CR118, 0xf0 }, \ { ZYD_CR119, 0x16 }, { ZYD_CR122, 0x00 }, { ZYD_CR127, 0x03 }, \ { ZYD_CR131, 0x08 }, { ZYD_CR138, 0x28 }, { ZYD_CR148, 0x44 }, \ { ZYD_CR150, 0x10 }, { ZYD_CR169, 0xbb }, { ZYD_CR170, 0xbb } \ } #define ZYD_RFMD_RF \ { \ 0x000007, 0x07dd43, 0x080959, 0x0e6666, 0x116a57, 0x17dd43, \ 0x1819f9, 0x1e6666, 0x214554, 0x25e7fa, 0x27fffa, 0x294128, \ 0x2c0000, 0x300000, 0x340000, 0x381e0f, 0x6c180f \ } #define ZYD_RFMD_CHANTABLE \ { \ { 0x181979, 0x1e6666 }, \ { 0x181989, 0x1e6666 }, \ { 0x181999, 0x1e6666 }, \ { 0x1819a9, 0x1e6666 }, \ { 0x1819b9, 0x1e6666 }, \ { 0x1819c9, 0x1e6666 }, \ { 0x1819d9, 0x1e6666 }, \ { 0x1819e9, 0x1e6666 }, \ { 0x1819f9, 0x1e6666 }, \ { 0x181a09, 0x1e6666 }, \ { 0x181a19, 0x1e6666 }, \ { 0x181a29, 0x1e6666 }, \ { 0x181a39, 0x1e6666 }, \ { 0x181a60, 0x1c0000 } \ } #define ZYD_AL2230_PHY \ { \ { ZYD_CR15, 0x20 }, { ZYD_CR23, 0x40 }, { ZYD_CR24, 0x20 }, \ { ZYD_CR26, 0x11 }, { ZYD_CR28, 0x3e }, { ZYD_CR29, 0x00 }, \ { ZYD_CR44, 0x33 }, { ZYD_CR106, 0x2a }, { ZYD_CR107, 0x1a }, \ { ZYD_CR109, 0x09 }, { ZYD_CR110, 0x27 }, { ZYD_CR111, 0x2b }, \ { ZYD_CR112, 0x2b }, { ZYD_CR119, 0x0a }, { ZYD_CR10, 0x89 }, \ { ZYD_CR17, 0x28 }, { ZYD_CR26, 0x93 }, { ZYD_CR34, 0x30 }, \ { ZYD_CR35, 0x3e }, { ZYD_CR41, 0x24 }, { ZYD_CR44, 0x32 }, \ { ZYD_CR46, 0x96 }, { ZYD_CR47, 0x1e }, { ZYD_CR79, 0x58 }, \ { ZYD_CR80, 0x30 }, { ZYD_CR81, 0x30 }, { ZYD_CR87, 0x0a }, \ { ZYD_CR89, 0x04 }, { ZYD_CR92, 0x0a }, { ZYD_CR99, 0x28 }, \ { ZYD_CR100, 0x00 }, { ZYD_CR101, 0x13 }, { ZYD_CR102, 0x27 }, \ { ZYD_CR106, 0x24 }, { ZYD_CR107, 0x2a }, { ZYD_CR109, 0x09 }, \ { ZYD_CR110, 0x13 }, { ZYD_CR111, 0x1f }, { ZYD_CR112, 0x1f }, \ { ZYD_CR113, 0x27 }, { ZYD_CR114, 0x27 }, { ZYD_CR115, 0x24 }, \ { ZYD_CR116, 0x24 }, { ZYD_CR117, 0xf4 }, { ZYD_CR118, 0xfc }, \ { ZYD_CR119, 0x10 }, { ZYD_CR120, 0x4f }, { ZYD_CR121, 0x77 }, \ { ZYD_CR122, 0xe0 }, { ZYD_CR137, 0x88 }, { ZYD_CR252, 0xff }, \ { ZYD_CR253, 0xff }, { ZYD_CR251, 0x2f }, { ZYD_CR251, 0x3f }, \ { ZYD_CR138, 0x28 }, { ZYD_CR203, 0x06 } \ } #define ZYD_AL2230_PHY_B \ { \ { ZYD_CR10, 0x89 }, { ZYD_CR15, 0x20 }, { ZYD_CR17, 0x2B }, \ { ZYD_CR23, 0x40 }, { ZYD_CR24, 0x20 }, { ZYD_CR26, 0x93 }, \ { ZYD_CR28, 0x3e }, { ZYD_CR29, 0x00 }, { ZYD_CR33, 0x28 }, \ { ZYD_CR34, 0x30 }, { ZYD_CR35, 0x3e }, { ZYD_CR41, 0x24 }, \ { ZYD_CR44, 0x32 }, { ZYD_CR46, 0x99 }, { ZYD_CR47, 0x1e }, \ { ZYD_CR48, 0x06 }, { ZYD_CR49, 0xf9 }, { ZYD_CR51, 0x01 }, \ { ZYD_CR52, 0x80 }, { ZYD_CR53, 0x7e }, { ZYD_CR65, 0x00 }, \ { ZYD_CR66, 0x00 }, { ZYD_CR67, 0x00 }, { ZYD_CR68, 0x00 }, \ { ZYD_CR69, 0x28 }, { ZYD_CR79, 0x58 }, { ZYD_CR80, 0x30 }, \ { ZYD_CR81, 0x30 }, { ZYD_CR87, 0x0a }, { ZYD_CR89, 0x04 }, \ { ZYD_CR91, 0x00 }, { ZYD_CR92, 0x0a }, { ZYD_CR98, 0x8d }, \ { ZYD_CR99, 0x00 }, { ZYD_CR101, 0x13 }, { ZYD_CR102, 0x27 }, \ { ZYD_CR106, 0x24 }, { ZYD_CR107, 0x2a }, { ZYD_CR109, 0x13 }, \ { ZYD_CR110, 0x1f }, { ZYD_CR111, 0x1f }, { ZYD_CR112, 0x1f }, \ { ZYD_CR113, 0x27 }, { ZYD_CR114, 0x27 }, { ZYD_CR115, 0x26 }, \ { ZYD_CR116, 0x24 }, { ZYD_CR117, 0xfa }, { ZYD_CR118, 0xfa }, \ { ZYD_CR119, 0x10 }, { ZYD_CR120, 0x4f }, { ZYD_CR121, 0x6c }, \ { ZYD_CR122, 0xfc }, { ZYD_CR123, 0x57 }, { ZYD_CR125, 0xad }, \ { ZYD_CR126, 0x6c }, { ZYD_CR127, 0x03 }, { ZYD_CR137, 0x50 }, \ { ZYD_CR138, 0xa8 }, { ZYD_CR144, 0xac }, { ZYD_CR150, 0x0d }, \ { ZYD_CR252, 0x34 }, { ZYD_CR253, 0x34 } \ } #define ZYD_AL2230_PHY_PART1 \ { \ { ZYD_CR240, 0x57 }, { ZYD_CR9, 0xe0 } \ } #define ZYD_AL2230_PHY_PART2 \ { \ { ZYD_CR251, 0x2f }, { ZYD_CR251, 0x7f }, \ } #define ZYD_AL2230_PHY_PART3 \ { \ { ZYD_CR128, 0x14 }, { ZYD_CR129, 0x12 }, { ZYD_CR130, 0x10 }, \ } #define ZYD_AL2230S_PHY_INIT \ { \ { ZYD_CR47, 0x1e }, { ZYD_CR106, 0x22 }, { ZYD_CR107, 0x2a }, \ { ZYD_CR109, 0x13 }, { ZYD_CR118, 0xf8 }, { ZYD_CR119, 0x12 }, \ { ZYD_CR122, 0xe0 }, { ZYD_CR128, 0x10 }, { ZYD_CR129, 0x0e }, \ { ZYD_CR130, 0x10 } \ } #define ZYD_AL2230_PHY_FINI_PART1 \ { \ { ZYD_CR80, 0x30 }, { ZYD_CR81, 0x30 }, { ZYD_CR79, 0x58 }, \ { ZYD_CR12, 0xf0 }, { ZYD_CR77, 0x1b }, { ZYD_CR78, 0x58 }, \ { ZYD_CR203, 0x06 }, { ZYD_CR240, 0x80 }, \ } #define ZYD_AL2230_RF_PART1 \ { \ 0x03f790, 0x033331, 0x00000d, 0x0b3331, 0x03b812, 0x00fff3 \ } #define ZYD_AL2230_RF_PART2 \ { \ 0x000da4, 0x0f4dc5, 0x0805b6, 0x011687, 0x000688, 0x0403b9, \ 0x00dbba, 0x00099b, 0x0bdffc, 0x00000d, 0x00500f \ } #define ZYD_AL2230_RF_PART3 \ { \ 0x00d00f, 0x004c0f, 0x00540f, 0x00700f, 0x00500f \ } #define ZYD_AL2230_RF_B \ { \ 0x03f790, 0x033331, 0x00000d, 0x0b3331, 0x03b812, 0x00fff3, \ 0x0005a4, 0x0f4dc5, 0x0805b6, 0x0146c7, 0x000688, 0x0403b9, \ 0x00dbba, 0x00099b, 0x0bdffc, 0x00000d, 0x00580f \ } #define ZYD_AL2230_RF_B_PART1 \ { \ 0x8cccd0, 0x481dc0, 0xcfff00, 0x25a000 \ } #define ZYD_AL2230_RF_B_PART2 \ { \ 0x25a000, 0xa3b2f0, 0x6da010, 0xe36280, 0x116000, 0x9dc020, \ 0x5ddb00, 0xd99000, 0x3ffbd0, 0xb00000, 0xf01a00 \ } #define ZYD_AL2230_RF_B_PART3 \ { \ 0xf01b00, 0xf01e00, 0xf01a00 \ } #define ZYD_AL2230_CHANTABLE \ { \ { 0x03f790, 0x033331, 0x00000d }, \ { 0x03f790, 0x0b3331, 0x00000d }, \ { 0x03e790, 0x033331, 0x00000d }, \ { 0x03e790, 0x0b3331, 0x00000d }, \ { 0x03f7a0, 0x033331, 0x00000d }, \ { 0x03f7a0, 0x0b3331, 0x00000d }, \ { 0x03e7a0, 0x033331, 0x00000d }, \ { 0x03e7a0, 0x0b3331, 0x00000d }, \ { 0x03f7b0, 0x033331, 0x00000d }, \ { 0x03f7b0, 0x0b3331, 0x00000d }, \ { 0x03e7b0, 0x033331, 0x00000d }, \ { 0x03e7b0, 0x0b3331, 0x00000d }, \ { 0x03f7c0, 0x033331, 0x00000d }, \ { 0x03e7c0, 0x066661, 0x00000d } \ } #define ZYD_AL2230_CHANTABLE_B \ { \ { 0x09efc0, 0x8cccc0, 0xb00000 }, \ { 0x09efc0, 0x8cccd0, 0xb00000 }, \ { 0x09e7c0, 0x8cccc0, 0xb00000 }, \ { 0x09e7c0, 0x8cccd0, 0xb00000 }, \ { 0x05efc0, 0x8cccc0, 0xb00000 }, \ { 0x05efc0, 0x8cccd0, 0xb00000 }, \ { 0x05e7c0, 0x8cccc0, 0xb00000 }, \ { 0x05e7c0, 0x8cccd0, 0xb00000 }, \ { 0x0defc0, 0x8cccc0, 0xb00000 }, \ { 0x0defc0, 0x8cccd0, 0xb00000 }, \ { 0x0de7c0, 0x8cccc0, 0xb00000 }, \ { 0x0de7c0, 0x8cccd0, 0xb00000 }, \ { 0x03efc0, 0x8cccc0, 0xb00000 }, \ { 0x03e7c0, 0x866660, 0xb00000 } \ } #define ZYD_AL7230B_PHY_1 \ { \ { ZYD_CR240, 0x57 }, { ZYD_CR15, 0x20 }, { ZYD_CR23, 0x40 }, \ { ZYD_CR24, 0x20 }, { ZYD_CR26, 0x11 }, { ZYD_CR28, 0x3e }, \ { ZYD_CR29, 0x00 }, { ZYD_CR44, 0x33 }, { ZYD_CR106, 0x22 }, \ { ZYD_CR107, 0x1a }, { ZYD_CR109, 0x09 }, { ZYD_CR110, 0x27 }, \ { ZYD_CR111, 0x2b }, { ZYD_CR112, 0x2b }, { ZYD_CR119, 0x0a }, \ { ZYD_CR122, 0xfc }, { ZYD_CR10, 0x89 }, { ZYD_CR17, 0x28 }, \ { ZYD_CR26, 0x93 }, { ZYD_CR34, 0x30 }, { ZYD_CR35, 0x3e }, \ { ZYD_CR41, 0x24 }, { ZYD_CR44, 0x32 }, { ZYD_CR46, 0x96 }, \ { ZYD_CR47, 0x1e }, { ZYD_CR79, 0x58 }, { ZYD_CR80, 0x30 }, \ { ZYD_CR81, 0x30 }, { ZYD_CR87, 0x0a }, { ZYD_CR89, 0x04 }, \ { ZYD_CR92, 0x0a }, { ZYD_CR99, 0x28 }, { ZYD_CR100, 0x02 }, \ { ZYD_CR101, 0x13 }, { ZYD_CR102, 0x27 }, { ZYD_CR106, 0x22 }, \ { ZYD_CR107, 0x3f }, { ZYD_CR109, 0x09 }, { ZYD_CR110, 0x1f }, \ { ZYD_CR111, 0x1f }, { ZYD_CR112, 0x1f }, { ZYD_CR113, 0x27 }, \ { ZYD_CR114, 0x27 }, { ZYD_CR115, 0x24 }, { ZYD_CR116, 0x3f }, \ { ZYD_CR117, 0xfa }, { ZYD_CR118, 0xfc }, { ZYD_CR119, 0x10 }, \ { ZYD_CR120, 0x4f }, { ZYD_CR121, 0x77 }, { ZYD_CR137, 0x88 }, \ { ZYD_CR138, 0xa8 }, { ZYD_CR252, 0x34 }, { ZYD_CR253, 0x34 }, \ { ZYD_CR251, 0x2f } \ } #define ZYD_AL7230B_PHY_2 \ { \ { ZYD_CR251, 0x3f }, { ZYD_CR128, 0x14 }, { ZYD_CR129, 0x12 }, \ { ZYD_CR130, 0x10 }, { ZYD_CR38, 0x38 }, { ZYD_CR136, 0xdf } \ } #define ZYD_AL7230B_PHY_3 \ { \ { ZYD_CR203, 0x06 }, { ZYD_CR240, 0x80 } \ } #define ZYD_AL7230B_RF_1 \ { \ 0x09ec04, 0x8cccc8, 0x4ff821, 0xc5fbfc, 0x21ebfe, 0xafd401, \ 0x6cf56a, 0xe04073, 0x193d76, 0x9dd844, 0x500007, 0xd8c010, \ 0x3c9000, 0xbfffff, 0x700000, 0xf15d58 \ } #define ZYD_AL7230B_RF_2 \ { \ 0xf15d59, 0xf15d5c, 0xf15d58 \ } #define ZYD_AL7230B_RF_SETCHANNEL \ { \ 0x4ff821, 0xc5fbfc, 0x21ebfe, 0xafd401, 0x6cf56a, 0xe04073, \ 0x193d76, 0x9dd844, 0x500007, 0xd8c010, 0x3c9000, 0xf15d58 \ } #define ZYD_AL7230B_CHANTABLE \ { \ { 0x09ec00, 0x8cccc8 }, \ { 0x09ec00, 0x8cccd8 }, \ { 0x09ec00, 0x8cccc0 }, \ { 0x09ec00, 0x8cccd0 }, \ { 0x05ec00, 0x8cccc8 }, \ { 0x05ec00, 0x8cccd8 }, \ { 0x05ec00, 0x8cccc0 }, \ { 0x05ec00, 0x8cccd0 }, \ { 0x0dec00, 0x8cccc8 }, \ { 0x0dec00, 0x8cccd8 }, \ { 0x0dec00, 0x8cccc0 }, \ { 0x0dec00, 0x8cccd0 }, \ { 0x03ec00, 0x8cccc8 }, \ { 0x03ec00, 0x866660 } \ } #define ZYD_AL2210_PHY \ { \ { ZYD_CR9, 0xe0 }, { ZYD_CR10, 0x91 }, { ZYD_CR12, 0x90 }, \ { ZYD_CR15, 0xd0 }, { ZYD_CR16, 0x40 }, { ZYD_CR17, 0x58 }, \ { ZYD_CR18, 0x04 }, { ZYD_CR23, 0x66 }, { ZYD_CR24, 0x14 }, \ { ZYD_CR26, 0x90 }, { ZYD_CR31, 0x80 }, { ZYD_CR34, 0x06 }, \ { ZYD_CR35, 0x3e }, { ZYD_CR38, 0x38 }, { ZYD_CR46, 0x90 }, \ { ZYD_CR47, 0x1e }, { ZYD_CR64, 0x64 }, { ZYD_CR79, 0xb5 }, \ { ZYD_CR80, 0x38 }, { ZYD_CR81, 0x30 }, { ZYD_CR113, 0xc0 }, \ { ZYD_CR127, 0x03 } \ } #define ZYD_AL2210_RF \ { \ 0x2396c0, 0x00fcb1, 0x358132, 0x0108b3, 0xc77804, 0x456415, \ 0xff2226, 0x806667, 0x7860f8, 0xbb01c9, 0x00000a, 0x00000b \ } #define ZYD_AL2210_CHANTABLE \ { \ 0x0196c0, 0x019710, 0x019760, 0x0197b0, 0x019800, 0x019850, \ 0x0198a0, 0x0198f0, 0x019940, 0x019990, 0x0199e0, 0x019a30, \ 0x019a80, 0x019b40 \ } #define ZYD_GCT_PHY \ { \ { ZYD_CR10, 0x89 }, { ZYD_CR15, 0x20 }, { ZYD_CR17, 0x28 }, \ { ZYD_CR23, 0x38 }, { ZYD_CR24, 0x20 }, { ZYD_CR26, 0x93 }, \ { ZYD_CR27, 0x15 }, { ZYD_CR28, 0x3e }, { ZYD_CR29, 0x00 }, \ { ZYD_CR33, 0x28 }, { ZYD_CR34, 0x30 }, { ZYD_CR35, 0x43 }, \ { ZYD_CR41, 0x24 }, { ZYD_CR44, 0x32 }, { ZYD_CR46, 0x92 }, \ { ZYD_CR47, 0x1e }, { ZYD_CR48, 0x04 }, { ZYD_CR49, 0xfa }, \ { ZYD_CR79, 0x58 }, { ZYD_CR80, 0x30 }, { ZYD_CR81, 0x30 }, \ { ZYD_CR87, 0x0a }, { ZYD_CR89, 0x04 }, { ZYD_CR91, 0x00 }, \ { ZYD_CR92, 0x0a }, { ZYD_CR98, 0x8d }, { ZYD_CR99, 0x28 }, \ { ZYD_CR100, 0x02 }, { ZYD_CR101, 0x09 }, { ZYD_CR102, 0x27 }, \ { ZYD_CR106, 0x1c }, { ZYD_CR107, 0x1c }, { ZYD_CR109, 0x13 }, \ { ZYD_CR110, 0x1f }, { ZYD_CR111, 0x13 }, { ZYD_CR112, 0x1f }, \ { ZYD_CR113, 0x27 }, { ZYD_CR114, 0x23 }, { ZYD_CR115, 0x24 }, \ { ZYD_CR116, 0x24 }, { ZYD_CR117, 0xfa }, { ZYD_CR118, 0xf0 }, \ { ZYD_CR119, 0x1a }, { ZYD_CR120, 0x4f }, { ZYD_CR121, 0x1f }, \ { ZYD_CR122, 0xf0 }, { ZYD_CR123, 0x57 }, { ZYD_CR125, 0xad }, \ { ZYD_CR126, 0x6c }, { ZYD_CR127, 0x03 }, { ZYD_CR128, 0x14 }, \ { ZYD_CR129, 0x12 }, { ZYD_CR130, 0x10 }, { ZYD_CR137, 0x50 }, \ { ZYD_CR138, 0xa8 }, { ZYD_CR144, 0xac }, { ZYD_CR146, 0x20 }, \ { ZYD_CR252, 0xff }, { ZYD_CR253, 0xff } \ } #define ZYD_GCT_RF \ { \ 0x40002b, 0x519e4f, 0x6f81ad, 0x73fffe, 0x25f9c, 0x100047, \ 0x200999, 0x307602, 0x346063, \ } #define ZYD_GCT_VCO \ { \ { 0x664d, 0x604d, 0x6675, 0x6475, 0x6655, 0x6455, 0x6665 }, \ { 0x666d, 0x606d, 0x664d, 0x644d, 0x6675, 0x6475, 0x6655 }, \ { 0x665d, 0x605d, 0x666d, 0x646d, 0x664d, 0x644d, 0x6675 }, \ { 0x667d, 0x607d, 0x665d, 0x645d, 0x666d, 0x646d, 0x664d }, \ { 0x6643, 0x6043, 0x667d, 0x647d, 0x665d, 0x645d, 0x666d }, \ { 0x6663, 0x6063, 0x6643, 0x6443, 0x667d, 0x647d, 0x665d }, \ { 0x6653, 0x6053, 0x6663, 0x6463, 0x6643, 0x6443, 0x667d }, \ { 0x6673, 0x6073, 0x6653, 0x6453, 0x6663, 0x6463, 0x6643 }, \ { 0x664b, 0x604b, 0x6673, 0x6473, 0x6653, 0x6453, 0x6663 }, \ { 0x666b, 0x606b, 0x664b, 0x644b, 0x6673, 0x6473, 0x6653 }, \ { 0x665b, 0x605b, 0x666b, 0x646b, 0x664b, 0x644b, 0x6673 } \ } #define ZYD_GCT_TXGAIN \ { \ 0x0e313, 0x0fb13, 0x0e093, 0x0f893, 0x0ea93, 0x1f093, 0x1f493, \ 0x1f693, 0x1f393, 0x1f35b, 0x1e6db, 0x1ff3f, 0x1ffff, 0x361d7, \ 0x37fbf, 0x3ff8b, 0x3ff33, 0x3fb3f, 0x3ffff \ } #define ZYD_GCT_CHANNEL_ACAL \ { \ 0x106847, 0x106847, 0x106867, 0x106867, 0x106867, 0x106867, \ 0x106857, 0x106857, 0x106857, 0x106857, 0x106877, 0x106877, \ 0x106877, 0x10684f \ } #define ZYD_GCT_CHANNEL_STD \ { \ 0x100047, 0x100047, 0x100067, 0x100067, 0x100067, 0x100067, \ 0x100057, 0x100057, 0x100057, 0x100057, 0x100077, 0x100077, \ 0x100077, 0x10004f \ } #define ZYD_GCT_CHANNEL_DIV \ { \ 0x200999, 0x20099b, 0x200998, 0x20099a, 0x200999, 0x20099b, \ 0x200998, 0x20099a, 0x200999, 0x20099b, 0x200998, 0x20099a, \ 0x200999, 0x200ccc \ } #define ZYD_MAXIM2_PHY \ { \ { ZYD_CR23, 0x40 }, { ZYD_CR15, 0x20 }, { ZYD_CR28, 0x3e }, \ { ZYD_CR29, 0x00 }, { ZYD_CR26, 0x11 }, { ZYD_CR44, 0x33 }, \ { ZYD_CR106, 0x2a }, { ZYD_CR107, 0x1a }, { ZYD_CR109, 0x2b }, \ { ZYD_CR110, 0x2b }, { ZYD_CR111, 0x2b }, { ZYD_CR112, 0x2b }, \ { ZYD_CR10, 0x89 }, { ZYD_CR17, 0x20 }, { ZYD_CR26, 0x93 }, \ { ZYD_CR34, 0x30 }, { ZYD_CR35, 0x40 }, { ZYD_CR41, 0x24 }, \ { ZYD_CR44, 0x32 }, { ZYD_CR46, 0x90 }, { ZYD_CR89, 0x18 }, \ { ZYD_CR92, 0x0a }, { ZYD_CR101, 0x13 }, { ZYD_CR102, 0x27 }, \ { ZYD_CR106, 0x20 }, { ZYD_CR107, 0x24 }, { ZYD_CR109, 0x09 }, \ { ZYD_CR110, 0x13 }, { ZYD_CR111, 0x13 }, { ZYD_CR112, 0x13 }, \ { ZYD_CR113, 0x27 }, { ZYD_CR114, 0x27 }, { ZYD_CR115, 0x24 }, \ { ZYD_CR116, 0x24 }, { ZYD_CR117, 0xf4 }, { ZYD_CR118, 0xfa }, \ { ZYD_CR120, 0x4f }, { ZYD_CR121, 0x77 }, { ZYD_CR122, 0xfe }, \ { ZYD_CR10, 0x89 }, { ZYD_CR17, 0x20 }, { ZYD_CR26, 0x93 }, \ { ZYD_CR34, 0x30 }, { ZYD_CR35, 0x40 }, { ZYD_CR41, 0x24 }, \ { ZYD_CR44, 0x32 }, { ZYD_CR46, 0x90 }, { ZYD_CR79, 0x58 }, \ { ZYD_CR80, 0x30 }, { ZYD_CR81, 0x30 }, { ZYD_CR89, 0x18 }, \ { ZYD_CR92, 0x0a }, { ZYD_CR101, 0x13 }, { ZYD_CR102, 0x27 }, \ { ZYD_CR106, 0x20 }, { ZYD_CR107, 0x24 }, { ZYD_CR109, 0x09 }, \ { ZYD_CR110, 0x13 }, { ZYD_CR111, 0x13 }, { ZYD_CR112, 0x13 }, \ { ZYD_CR113, 0x27 }, { ZYD_CR114, 0x27 }, { ZYD_CR115, 0x24 }, \ { ZYD_CR116, 0x24 }, { ZYD_CR117, 0xf4 }, { ZYD_CR118, 0x00 }, \ { ZYD_CR120, 0x4f }, { ZYD_CR121, 0x06 }, { ZYD_CR122, 0xfe } \ } #define ZYD_MAXIM2_RF \ { \ 0x33334, 0x10a03, 0x00400, 0x00ca1, 0x10072, 0x18645, 0x04006, \ 0x000a7, 0x08258, 0x03fc9, 0x0040a, 0x0000b, 0x0026c \ } #define ZYD_MAXIM2_CHANTABLE_F \ { \ 0x33334, 0x08884, 0x1ddd4, 0x33334, 0x08884, 0x1ddd4, 0x33334, \ 0x08884, 0x1ddd4, 0x33334, 0x08884, 0x1ddd4, 0x33334, 0x26664 \ } #define ZYD_MAXIM2_CHANTABLE \ { \ { 0x33334, 0x10a03 }, \ { 0x08884, 0x20a13 }, \ { 0x1ddd4, 0x30a13 }, \ { 0x33334, 0x10a13 }, \ { 0x08884, 0x20a23 }, \ { 0x1ddd4, 0x30a23 }, \ { 0x33334, 0x10a23 }, \ { 0x08884, 0x20a33 }, \ { 0x1ddd4, 0x30a33 }, \ { 0x33334, 0x10a33 }, \ { 0x08884, 0x20a43 }, \ { 0x1ddd4, 0x30a43 }, \ { 0x33334, 0x10a43 }, \ { 0x26664, 0x20a53 } \ } #define ZYD_TX_RATEDIV \ { \ 0x1, 0x2, 0xb, 0xb, 0x1, 0x1, 0x1, 0x1, 0x30, 0x18, 0xc, 0x6, \ 0x36, 0x24, 0x12, 0x9 \ } /* * Control pipe requests. */ #define ZYD_DOWNLOADREQ 0x30 #define ZYD_DOWNLOADSTS 0x31 #define ZYD_READFWDATAREQ 0x32 /* possible values for register ZYD_CR_INTERRUPT */ #define ZYD_HWINT_MASK 0x004f0000 /* possible values for register ZYD_MAC_MISC */ #define ZYD_UNLOCK_PHY_REGS 0x80 /* possible values for register ZYD_MAC_ENCRYPTION_TYPE */ #define ZYD_ENC_SNIFFER 8 /* flags for register ZYD_MAC_RXFILTER */ #define ZYD_FILTER_ASS_REQ (1 << 0) #define ZYD_FILTER_ASS_RSP (1 << 1) #define ZYD_FILTER_REASS_REQ (1 << 2) #define ZYD_FILTER_REASS_RSP (1 << 3) #define ZYD_FILTER_PRB_REQ (1 << 4) #define ZYD_FILTER_PRB_RSP (1 << 5) #define ZYD_FILTER_BCN (1 << 8) #define ZYD_FILTER_ATIM (1 << 9) #define ZYD_FILTER_DEASS (1 << 10) #define ZYD_FILTER_AUTH (1 << 11) #define ZYD_FILTER_DEAUTH (1 << 12) #define ZYD_FILTER_PS_POLL (1 << 26) #define ZYD_FILTER_RTS (1 << 27) #define ZYD_FILTER_CTS (1 << 28) #define ZYD_FILTER_ACK (1 << 29) #define ZYD_FILTER_CFE (1 << 30) #define ZYD_FILTER_CFE_A (1U << 31) /* helpers for register ZYD_MAC_RXFILTER */ #define ZYD_FILTER_MONITOR 0xffffffff #define ZYD_FILTER_BSS \ (ZYD_FILTER_ASS_REQ | ZYD_FILTER_ASS_RSP | \ ZYD_FILTER_REASS_REQ | ZYD_FILTER_REASS_RSP | \ ZYD_FILTER_PRB_REQ | ZYD_FILTER_PRB_RSP | \ (0x3 << 6) | \ ZYD_FILTER_BCN | ZYD_FILTER_ATIM | ZYD_FILTER_DEASS | \ ZYD_FILTER_AUTH | ZYD_FILTER_DEAUTH | \ (0x7 << 13) | \ ZYD_FILTER_PS_POLL | ZYD_FILTER_ACK) #define ZYD_FILTER_HOSTAP \ (ZYD_FILTER_ASS_REQ | ZYD_FILTER_REASS_REQ | \ ZYD_FILTER_PRB_REQ | ZYD_FILTER_DEASS | ZYD_FILTER_AUTH | \ ZYD_FILTER_DEAUTH | ZYD_FILTER_PS_POLL) struct zyd_tx_desc { uint8_t phy; #define ZYD_TX_PHY_SIGNAL(x) ((x) & 0xf) #define ZYD_TX_PHY_OFDM (1 << 4) #define ZYD_TX_PHY_SHPREAMBLE (1 << 5) /* CCK */ #define ZYD_TX_PHY_5GHZ (1 << 5) /* OFDM */ uint16_t len; uint8_t flags; #define ZYD_TX_FLAG_BACKOFF (1 << 0) #define ZYD_TX_FLAG_MULTICAST (1 << 1) #define ZYD_TX_FLAG_TYPE(x) (((x) & 0x3) << 2) #define ZYD_TX_TYPE_DATA 0 #define ZYD_TX_TYPE_PS_POLL 1 #define ZYD_TX_TYPE_MGMT 2 #define ZYD_TX_TYPE_CTL 3 #define ZYD_TX_FLAG_WAKEUP (1 << 4) #define ZYD_TX_FLAG_RTS (1 << 5) #define ZYD_TX_FLAG_ENCRYPT (1 << 6) #define ZYD_TX_FLAG_CTS_TO_SELF (1 << 7) uint16_t pktlen; uint16_t plcp_length; uint8_t plcp_service; #define ZYD_PLCP_LENGEXT 0x80 uint16_t nextlen; } __packed; struct zyd_plcphdr { uint8_t signal; uint8_t reserved[2]; uint16_t service; /* unaligned! */ } __packed; struct zyd_rx_stat { uint8_t signal_cck; uint8_t rssi; uint8_t signal_ofdm; uint8_t cipher; #define ZYD_RX_CIPHER_WEP64 1 #define ZYD_RX_CIPHER_TKIP 2 #define ZYD_RX_CIPHER_AES 4 #define ZYD_RX_CIPHER_WEP128 5 #define ZYD_RX_CIPHER_WEP256 6 #define ZYD_RX_CIPHER_WEP \ (ZYD_RX_CIPHER_WEP64 | ZYD_RX_CIPHER_WEP128 | ZYD_RX_CIPHER_WEP256) uint8_t flags; #define ZYD_RX_OFDM (1 << 0) #define ZYD_RX_TIMEOUT (1 << 1) #define ZYD_RX_OVERRUN (1 << 2) #define ZYD_RX_DECRYPTERR (1 << 3) #define ZYD_RX_BADCRC32 (1 << 4) #define ZYD_RX_NOT2ME (1 << 5) #define ZYD_RX_BADCRC16 (1 << 6) #define ZYD_RX_ERROR (1 << 7) } __packed; /* this structure may be unaligned */ struct zyd_rx_desc { #define ZYD_MAX_RXFRAMECNT 3 uWord len[ZYD_MAX_RXFRAMECNT]; uWord tag; #define ZYD_TAG_MULTIFRAME 0x697e } __packed; /* I2C bus alike */ struct zyd_rfwrite_cmd { uint16_t code; uint16_t width; uint16_t bit[32]; #define ZYD_RF_IF_LE (1 << 1) #define ZYD_RF_CLK (1 << 2) #define ZYD_RF_DATA (1 << 3) } __packed; struct zyd_cmd { uint16_t code; #define ZYD_CMD_IOWR 0x0021 /* write HMAC or PHY register */ #define ZYD_CMD_IORD 0x0022 /* read HMAC or PHY register */ #define ZYD_CMD_RFCFG 0x0023 /* write RF register */ #define ZYD_NOTIF_IORD 0x9001 /* response for ZYD_CMD_IORD */ #define ZYD_NOTIF_MACINTR 0x9001 /* interrupt notification */ #define ZYD_NOTIF_RETRYSTATUS 0xa001 /* Tx retry notification */ uint8_t data[64]; } __packed; /* structure for command ZYD_CMD_IOWR */ struct zyd_pair { uint16_t reg; /* helpers macros to read/write 32-bit registers */ #define ZYD_REG32_LO(reg) (reg) #define ZYD_REG32_HI(reg) \ ((reg) + ((((reg) & 0xf000) == 0x9000) ? 2 : 1)) uint16_t val; } __packed; /* structure for notification ZYD_NOTIF_RETRYSTATUS */ struct zyd_notif_retry { uint16_t rate; uint8_t macaddr[IEEE80211_ADDR_LEN]; uint16_t count; } __packed; #define ZYD_CONFIG_INDEX 0 #define ZYD_IFACE_INDEX 0 #define ZYD_INTR_TIMEOUT 1000 #define ZYD_TX_TIMEOUT 10000 #define ZYD_MAX_TXBUFSZ \ (sizeof(struct zyd_tx_desc) + MCLBYTES) #define ZYD_MIN_FRAGSZ \ (sizeof(struct zyd_plcphdr) + IEEE80211_MIN_LEN + \ sizeof(struct zyd_rx_stat)) #define ZYD_MIN_RXBUFSZ ZYD_MIN_FRAGSZ #define ZYX_MAX_RXBUFSZ \ ((sizeof (struct zyd_plcphdr) + IEEE80211_MAX_LEN + \ sizeof (struct zyd_rx_stat)) * ZYD_MAX_RXFRAMECNT + \ sizeof (struct zyd_rx_desc)) #define ZYD_TX_DESC_SIZE (sizeof (struct zyd_tx_desc)) #define ZYD_RX_LIST_CNT 1 #define ZYD_TX_LIST_CNT 5 #define ZYD_CMD_FLAG_READ (1 << 0) #define ZYD_CMD_FLAG_SENT (1 << 1) /* quickly determine if a given rate is CCK or OFDM */ #define ZYD_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) struct zyd_phy_pair { uint16_t reg; uint8_t val; }; struct zyd_mac_pair { uint16_t reg; uint32_t val; }; struct zyd_tx_data { STAILQ_ENTRY(zyd_tx_data) next; struct zyd_softc *sc; struct zyd_tx_desc desc; struct mbuf *m; struct ieee80211_node *ni; int rate; }; typedef STAILQ_HEAD(, zyd_tx_data) zyd_txdhead; struct zyd_rx_data { struct mbuf *m; int rssi; }; struct zyd_rx_radiotap_header { struct ieee80211_radiotap_header wr_ihdr; uint8_t wr_flags; uint8_t wr_rate; uint16_t wr_chan_freq; uint16_t wr_chan_flags; int8_t wr_antsignal; int8_t wr_antnoise; } __packed __aligned(8); #define ZYD_RX_RADIOTAP_PRESENT \ ((1 << IEEE80211_RADIOTAP_FLAGS) | \ (1 << IEEE80211_RADIOTAP_RATE) | \ (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \ (1 << IEEE80211_RADIOTAP_CHANNEL)) struct zyd_tx_radiotap_header { struct ieee80211_radiotap_header wt_ihdr; uint8_t wt_flags; uint8_t wt_rate; uint16_t wt_chan_freq; uint16_t wt_chan_flags; } __packed __aligned(8); #define ZYD_TX_RADIOTAP_PRESENT \ ((1 << IEEE80211_RADIOTAP_FLAGS) | \ (1 << IEEE80211_RADIOTAP_RATE) | \ (1 << IEEE80211_RADIOTAP_CHANNEL)) struct zyd_softc; /* forward declaration */ struct zyd_rf { /* RF methods */ int (*init)(struct zyd_rf *); int (*switch_radio)(struct zyd_rf *, int); int (*set_channel)(struct zyd_rf *, uint8_t); int (*bandedge6)(struct zyd_rf *, struct ieee80211_channel *); /* RF attributes */ struct zyd_softc *rf_sc; /* back-pointer */ int width; int idx; /* for GIT RF */ int update_pwr; }; struct zyd_rq { struct zyd_cmd *cmd; const uint16_t *idata; struct zyd_pair *odata; int ilen; int olen; int flags; STAILQ_ENTRY(zyd_rq) rq; }; struct zyd_vap { struct ieee80211vap vap; int (*newstate)(struct ieee80211vap *, enum ieee80211_state, int); }; #define ZYD_VAP(vap) ((struct zyd_vap *)(vap)) enum { ZYD_BULK_WR, ZYD_BULK_RD, ZYD_INTR_WR, ZYD_INTR_RD, ZYD_N_TRANSFER = 4, }; struct zyd_softc { struct ieee80211com sc_ic; struct mbufq sc_snd; device_t sc_dev; struct usb_device *sc_udev; struct usb_xfer *sc_xfer[ZYD_N_TRANSFER]; int sc_flags; #define ZYD_FLAG_FWLOADED (1 << 0) #define ZYD_FLAG_INITONCE (1 << 1) #define ZYD_FLAG_INITDONE (1 << 2) #define ZYD_FLAG_DETACHED (1 << 3) #define ZYD_FLAG_RUNNING (1 << 4) struct zyd_rf sc_rf; STAILQ_HEAD(, zyd_rq) sc_rtx; STAILQ_HEAD(, zyd_rq) sc_rqh; uint16_t sc_fwbase; uint8_t sc_regdomain; uint8_t sc_macrev; uint16_t sc_fwrev; uint8_t sc_rfrev; uint8_t sc_parev; uint8_t sc_al2230s; uint8_t sc_bandedge6; uint8_t sc_newphy; uint8_t sc_cckgain; uint8_t sc_fix_cr157; uint8_t sc_ledtype; uint8_t sc_txled; uint32_t sc_atim_wnd; uint32_t sc_pre_tbtt; uint32_t sc_bcn_int; uint8_t sc_pwrcal[14]; uint8_t sc_pwrint[14]; uint8_t sc_ofdm36_cal[14]; uint8_t sc_ofdm48_cal[14]; uint8_t sc_ofdm54_cal[14]; struct mtx sc_mtx; struct zyd_tx_data tx_data[ZYD_TX_LIST_CNT]; zyd_txdhead tx_q; zyd_txdhead tx_free; int tx_nfree; struct zyd_rx_desc sc_rx_desc; struct zyd_rx_data sc_rx_data[ZYD_MAX_RXFRAMECNT]; int sc_rx_count; struct zyd_cmd sc_ibuf; struct zyd_rx_radiotap_header sc_rxtap; - int sc_rxtap_len; struct zyd_tx_radiotap_header sc_txtap; - int sc_txtap_len; }; #define ZYD_LOCK(sc) mtx_lock(&(sc)->sc_mtx) #define ZYD_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) #define ZYD_LOCK_ASSERT(sc, t) mtx_assert(&(sc)->sc_mtx, t)