Index: head/sys/dev/drm2/i915/intel_drv.h =================================================================== --- head/sys/dev/drm2/i915/intel_drv.h (revision 287495) +++ head/sys/dev/drm2/i915/intel_drv.h (revision 287496) @@ -1,508 +1,513 @@ /* * Copyright (c) 2006 Dave Airlie * Copyright (c) 2007-2008 Intel Corporation * Jesse Barnes * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * $FreeBSD$ */ #ifndef DRM_INTEL_DRV_H #define DRM_INTEL_DRV_H #include #include #include #include #include #define _intel_wait_for(DEV, COND, MS, W, WMSG) \ ({ \ int end, ret; \ \ end = ticks + (MS) * hz / 1000; \ ret = 0; \ \ while (!(COND)) { \ if (time_after(ticks, end)) { \ ret = -ETIMEDOUT; \ break; \ } \ if (W) \ pause((WMSG), 1); \ else \ DELAY(1000); \ } \ \ ret; \ }) #define wait_for_atomic_us(COND, US) ({ \ int i, ret__ = -ETIMEDOUT; \ for (i = 0; i < (US); i++) { \ if ((COND)) { \ ret__ = 0; \ break; \ } \ DELAY(1); \ } \ ret__; \ }) #define wait_for(COND, MS) _intel_wait_for(NULL, COND, MS, 1, "915wfi") #define wait_for_atomic(COND, MS) _intel_wait_for(NULL, COND, MS, 0, "915wfa") #define KHz(x) (1000*x) #define MHz(x) KHz(1000*x) +/* + * Display related stuff + */ + /* store information about an Ixxx DVO */ /* The i830->i865 use multiple DVOs with multiple i2cs */ /* the i915, i945 have a single sDVO i2c bus - which is different */ #define MAX_OUTPUTS 6 /* maximum connectors per crtcs in the mode set */ #define INTELFB_CONN_LIMIT 4 #define INTEL_I2C_BUS_DVO 1 #define INTEL_I2C_BUS_SDVO 2 /* these are outputs from the chip - integrated only external chips are via DVO or SDVO output */ #define INTEL_OUTPUT_UNUSED 0 #define INTEL_OUTPUT_ANALOG 1 #define INTEL_OUTPUT_DVO 2 #define INTEL_OUTPUT_SDVO 3 #define INTEL_OUTPUT_LVDS 4 #define INTEL_OUTPUT_TVOUT 5 #define INTEL_OUTPUT_HDMI 6 #define INTEL_OUTPUT_DISPLAYPORT 7 #define INTEL_OUTPUT_EDP 8 +#define INTEL_OUTPUT_UNKNOWN 9 /* Intel Pipe Clone Bit */ #define INTEL_HDMIB_CLONE_BIT 1 #define INTEL_HDMIC_CLONE_BIT 2 #define INTEL_HDMID_CLONE_BIT 3 #define INTEL_HDMIE_CLONE_BIT 4 #define INTEL_HDMIF_CLONE_BIT 5 #define INTEL_SDVO_NON_TV_CLONE_BIT 6 #define INTEL_SDVO_TV_CLONE_BIT 7 #define INTEL_SDVO_LVDS_CLONE_BIT 8 #define INTEL_ANALOG_CLONE_BIT 9 #define INTEL_TV_CLONE_BIT 10 #define INTEL_DP_B_CLONE_BIT 11 #define INTEL_DP_C_CLONE_BIT 12 #define INTEL_DP_D_CLONE_BIT 13 #define INTEL_LVDS_CLONE_BIT 14 #define INTEL_DVO_TMDS_CLONE_BIT 15 #define INTEL_DVO_LVDS_CLONE_BIT 16 #define INTEL_EDP_CLONE_BIT 17 #define INTEL_DVO_CHIP_NONE 0 #define INTEL_DVO_CHIP_LVDS 1 #define INTEL_DVO_CHIP_TMDS 2 #define INTEL_DVO_CHIP_TVOUT 4 /* drm_display_mode->private_flags */ #define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0) #define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT) #define INTEL_MODE_DP_FORCE_6BPC (0x10) /* This flag must be set by the encoder's mode_fixup if it changes the crtc * timings in the mode to prevent the crtc fixup from overwriting them. * Currently only lvds needs that. */ #define INTEL_MODE_CRTC_TIMINGS_SET (0x20) static inline void intel_mode_set_pixel_multiplier(struct drm_display_mode *mode, int multiplier) { mode->clock *= multiplier; mode->private_flags |= multiplier; } static inline int intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode) { return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT; } struct intel_framebuffer { struct drm_framebuffer base; struct drm_i915_gem_object *obj; }; struct intel_fbdev { struct drm_fb_helper helper; struct intel_framebuffer ifb; struct list_head fbdev_list; struct drm_display_mode *our_mode; }; struct intel_encoder { struct drm_encoder base; int type; bool needs_tv_clock; void (*hot_plug)(struct intel_encoder *); int crtc_mask; int clone_mask; }; struct intel_connector { struct drm_connector base; struct intel_encoder *encoder; }; struct intel_crtc { struct drm_crtc base; enum pipe pipe; enum plane plane; u8 lut_r[256], lut_g[256], lut_b[256]; int dpms_mode; bool active; /* is the crtc on? independent of the dpms mode */ bool busy; /* is scanout buffer being updated frequently? */ struct callout idle_callout; bool lowfreq_avail; struct intel_overlay *overlay; struct intel_unpin_work *unpin_work; int fdi_lanes; struct drm_i915_gem_object *cursor_bo; uint32_t cursor_addr; int16_t cursor_x, cursor_y; int16_t cursor_width, cursor_height; bool cursor_visible; unsigned int bpp; /* We can share PLLs across outputs if the timings match */ struct intel_pch_pll *pch_pll; }; struct intel_plane { struct drm_plane base; enum pipe pipe; struct drm_i915_gem_object *obj; bool primary_disabled; int max_downscale; u32 lut_r[1024], lut_g[1024], lut_b[1024]; void (*update_plane)(struct drm_plane *plane, struct drm_framebuffer *fb, struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, unsigned int crtc_w, unsigned int crtc_h, uint32_t x, uint32_t y, uint32_t src_w, uint32_t src_h); void (*disable_plane)(struct drm_plane *plane); int (*update_colorkey)(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key); void (*get_colorkey)(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key); }; struct intel_watermark_params { unsigned long fifo_size; unsigned long max_wm; unsigned long default_wm; unsigned long guard_size; unsigned long cacheline_size; }; struct cxsr_latency { int is_desktop; int is_ddr3; unsigned long fsb_freq; unsigned long mem_freq; unsigned long display_sr; unsigned long display_hpll_disable; unsigned long cursor_sr; unsigned long cursor_hpll_disable; }; #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) #define to_intel_connector(x) container_of(x, struct intel_connector, base) #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) #define to_intel_plane(x) container_of(x, struct intel_plane, base) #define DIP_HEADER_SIZE 5 #define DIP_TYPE_AVI 0x82 #define DIP_VERSION_AVI 0x2 #define DIP_LEN_AVI 13 #define DIP_AVI_PR_1 0 #define DIP_AVI_PR_2 1 #define DIP_TYPE_SPD 0x83 #define DIP_VERSION_SPD 0x1 #define DIP_LEN_SPD 25 #define DIP_SPD_UNKNOWN 0 #define DIP_SPD_DSTB 0x1 #define DIP_SPD_DVDP 0x2 #define DIP_SPD_DVHS 0x3 #define DIP_SPD_HDDVR 0x4 #define DIP_SPD_DVC 0x5 #define DIP_SPD_DSC 0x6 #define DIP_SPD_VCD 0x7 #define DIP_SPD_GAME 0x8 #define DIP_SPD_PC 0x9 #define DIP_SPD_BD 0xa #define DIP_SPD_SCD 0xb struct dip_infoframe { uint8_t type; /* HB0 */ uint8_t ver; /* HB1 */ uint8_t len; /* HB2 - body len, not including checksum */ uint8_t ecc; /* Header ECC */ uint8_t checksum; /* PB0 */ union { struct { /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */ uint8_t Y_A_B_S; /* PB2 - C 7:6, M 5:4, R 3:0 */ uint8_t C_M_R; /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */ uint8_t ITC_EC_Q_SC; /* PB4 - VIC 6:0 */ uint8_t VIC; /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */ uint8_t YQ_CN_PR; /* PB6 to PB13 */ uint16_t top_bar_end; uint16_t bottom_bar_start; uint16_t left_bar_end; uint16_t right_bar_start; } __attribute__ ((packed)) avi; struct { uint8_t vn[8]; uint8_t pd[16]; uint8_t sdi; } __attribute__ ((packed)) spd; uint8_t payload[27]; } __attribute__ ((packed)) body; } __attribute__((packed)); struct intel_hdmi { struct intel_encoder base; u32 sdvox_reg; int ddc_bus; int ddi_port; uint32_t color_range; bool has_hdmi_sink; bool has_audio; enum hdmi_force_audio force_audio; void (*write_infoframe)(struct drm_encoder *encoder, struct dip_infoframe *frame); }; static inline struct drm_crtc * intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) { struct drm_i915_private *dev_priv = dev->dev_private; return dev_priv->pipe_to_crtc_mapping[pipe]; } static inline struct drm_crtc * intel_get_crtc_for_plane(struct drm_device *dev, int plane) { struct drm_i915_private *dev_priv = dev->dev_private; return dev_priv->plane_to_crtc_mapping[plane]; } struct intel_unpin_work { struct task task; struct drm_device *dev; struct drm_i915_gem_object *old_fb_obj; struct drm_i915_gem_object *pending_flip_obj; struct drm_pending_vblank_event *event; int pending; bool enable_stall_check; }; struct intel_fbc_work { struct timeout_task task; struct drm_crtc *crtc; struct drm_framebuffer *fb; int interval; }; int intel_ddc_get_modes(struct drm_connector *c, device_t adapter); extern bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus); extern void intel_attach_force_audio_property(struct drm_connector *connector); extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector); extern void intel_crt_init(struct drm_device *dev); extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg); extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); extern void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, struct drm_display_mode *adjusted_mode); extern void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder); extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if); extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); extern void intel_dvo_init(struct drm_device *dev); extern void intel_tv_init(struct drm_device *dev); extern void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj); extern bool intel_lvds_init(struct drm_device *dev); extern void intel_dp_init(struct drm_device *dev, int dp_reg); void intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode); extern bool intel_dpd_is_edp(struct drm_device *dev); extern void intel_edp_link_config(struct intel_encoder *, int *, int *); extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder); extern int intel_plane_init(struct drm_device *dev, enum pipe pipe); extern void intel_flush_display_plane(struct drm_i915_private *dev_priv, enum plane plane); void intel_sanitize_pm(struct drm_device *dev); /* intel_panel.c */ extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, struct drm_display_mode *adjusted_mode); extern void intel_pch_panel_fitting(struct drm_device *dev, int fitting_mode, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode); extern u32 intel_panel_get_max_backlight(struct drm_device *dev); extern u32 intel_panel_get_backlight(struct drm_device *dev); extern void intel_panel_set_backlight(struct drm_device *dev, u32 level); extern int intel_panel_setup_backlight(struct drm_device *dev); extern void intel_panel_enable_backlight(struct drm_device *dev); extern void intel_panel_disable_backlight(struct drm_device *dev); extern void intel_panel_destroy_backlight(struct drm_device *dev); extern enum drm_connector_status intel_panel_detect(struct drm_device *dev); extern void intel_crtc_load_lut(struct drm_crtc *crtc); extern void intel_encoder_prepare(struct drm_encoder *encoder); extern void intel_encoder_commit(struct drm_encoder *encoder); extern void intel_encoder_destroy(struct drm_encoder *encoder); static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) { return to_intel_connector(connector)->encoder; } extern void intel_connector_attach_encoder(struct intel_connector *connector, struct intel_encoder *encoder); extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector); extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, struct drm_crtc *crtc); int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, struct drm_file *file_priv); extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); struct intel_load_detect_pipe { struct drm_framebuffer *release_fb; bool load_detect_temp; int dpms_mode; }; extern bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, struct drm_connector *connector, struct drm_display_mode *mode, struct intel_load_detect_pipe *old); extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, struct drm_connector *connector, struct intel_load_detect_pipe *old); extern void intelfb_restore(void); extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, u16 blue, int regno); extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, int regno); extern void intel_enable_clock_gating(struct drm_device *dev); extern void ironlake_disable_rc6(struct drm_device *dev); extern void ironlake_enable_drps(struct drm_device *dev); extern void ironlake_disable_drps(struct drm_device *dev); extern void gen6_enable_rps(struct drm_i915_private *dev_priv); extern void gen6_update_ring_freq(struct drm_i915_private *dev_priv); extern void gen6_disable_rps(struct drm_device *dev); extern void intel_init_emon(struct drm_device *dev); extern int intel_enable_rc6(const struct drm_device *dev); extern void intel_ddi_dpms(struct drm_encoder *encoder, int mode); extern void intel_ddi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode); extern int intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_i915_gem_object *obj, struct intel_ring_buffer *pipelined); extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); extern int intel_framebuffer_init(struct drm_device *dev, struct intel_framebuffer *ifb, struct drm_mode_fb_cmd2 *mode_cmd, struct drm_i915_gem_object *obj); extern int intel_fbdev_init(struct drm_device *dev); extern void intel_fbdev_fini(struct drm_device *dev); extern void intel_prepare_page_flip(struct drm_device *dev, int plane); extern void intel_finish_page_flip(struct drm_device *dev, int pipe); extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane); extern void intel_setup_overlay(struct drm_device *dev); extern void intel_cleanup_overlay(struct drm_device *dev); extern int intel_overlay_switch_off(struct intel_overlay *overlay); extern int intel_overlay_put_image(struct drm_device *dev, void *data, struct drm_file *file_priv); extern int intel_overlay_attrs(struct drm_device *dev, void *data, struct drm_file *file_priv); extern void intel_fb_output_poll_changed(struct drm_device *dev); extern void intel_fb_restore_mode(struct drm_device *dev); extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) extern void intel_init_clock_gating(struct drm_device *dev); extern void intel_write_eld(struct drm_encoder *encoder, struct drm_display_mode *mode); extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); extern void intel_prepare_ddi(struct drm_device *dev); extern void hsw_fdi_link_train(struct drm_crtc *crtc); extern void intel_ddi_init(struct drm_device *dev, enum port port); /* For use by IVB LP watermark workaround in intel_sprite.c */ extern void intel_update_watermarks(struct drm_device *dev); extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, uint32_t sprite_width, int pixel_size); extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe, struct drm_display_mode *mode); extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data, struct drm_file *file_priv); extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data, struct drm_file *file_priv); extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg); /* Power-related functions, located in intel_pm.c */ extern void intel_init_pm(struct drm_device *dev); /* FBC */ extern bool intel_fbc_enabled(struct drm_device *dev); extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); extern void intel_update_fbc(struct drm_device *dev); #endif /* __INTEL_DRV_H__ */ Index: head/sys/dev/drm2/i915/intel_ringbuffer.h =================================================================== --- head/sys/dev/drm2/i915/intel_ringbuffer.h (revision 287495) +++ head/sys/dev/drm2/i915/intel_ringbuffer.h (revision 287496) @@ -1,215 +1,227 @@ /* * $FreeBSD$ */ #ifndef _INTEL_RINGBUFFER_H_ #define _INTEL_RINGBUFFER_H_ +/* + * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use" + * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use" + * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use" + * + * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same + * cacheline, the Head Pointer must not be greater than the Tail + * Pointer." + */ +#define I915_RING_FREE_SPACE 64 + struct intel_hw_status_page { u32 *page_addr; unsigned int gfx_addr; struct drm_i915_gem_object *obj; }; #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) #define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base)) #define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base)) #define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base)) struct intel_ring_buffer { const char *name; enum intel_ring_id { RCS = 0x0, VCS, BCS, } id; #define I915_NUM_RINGS 3 u32 mmio_base; void *virtual_start; struct drm_device *dev; struct drm_i915_gem_object *obj; u32 head; u32 tail; int space; int size; int effective_size; struct intel_hw_status_page status_page; /** We track the position of the requests in the ring buffer, and * when each is retired we increment last_retired_head as the GPU * must have finished processing the request and so we know we * can advance the ringbuffer up to that position. * * last_retired_head is set to -1 after the value is consumed so * we can detect new retirements. */ u32 last_retired_head; - u32 irq_refcount; + u32 irq_refcount; /* protected by dev_priv->irq_lock */ u32 irq_enable_mask; /* bitmask to enable ring interrupt */ u32 trace_irq_seqno; u32 sync_seqno[I915_NUM_RINGS-1]; bool (*irq_get)(struct intel_ring_buffer *ring); void (*irq_put)(struct intel_ring_buffer *ring); int (*init)(struct intel_ring_buffer *ring); void (*write_tail)(struct intel_ring_buffer *ring, uint32_t value); int (*flush)(struct intel_ring_buffer *ring, uint32_t invalidate_domains, uint32_t flush_domains); int (*add_request)(struct intel_ring_buffer *ring, uint32_t *seqno); uint32_t (*get_seqno)(struct intel_ring_buffer *ring); int (*dispatch_execbuffer)(struct intel_ring_buffer *ring, uint32_t offset, uint32_t length); +#define I915_DISPATCH_SECURE 0x1 +#define I915_DISPATCH_PINNED 0x2 void (*cleanup)(struct intel_ring_buffer *ring); int (*sync_to)(struct intel_ring_buffer *ring, struct intel_ring_buffer *to, u32 seqno); - + u32 semaphore_register[3]; /*our mbox written by others */ u32 signal_mbox[2]; /* mboxes this ring signals to */ - /** * List of objects currently involved in rendering from the * ringbuffer. * * Includes buffers having the contents of their GPU caches * flushed, not necessarily primitives. last_rendering_seqno * represents when the rendering involved will be completed. * * A reference is held on the buffer while on this list. */ struct list_head active_list; /** * List of breadcrumbs associated with GPU requests currently * outstanding. */ struct list_head request_list; /** * List of objects currently pending a GPU write flush. * * All elements on this list will belong to either the * active_list or flushing_list, last_rendering_seqno can * be used to differentiate between the two elements. */ struct list_head gpu_write_list; /** * Do we have some not yet emitted requests outstanding? */ u32 outstanding_lazy_request; /** * Do an explicit TLB flush before MI_SET_CONTEXT */ bool itlb_before_ctx_switch; struct i915_hw_context *default_context; struct drm_i915_gem_object *last_context_obj; drm_local_map_t map; void *private; }; static inline bool intel_ring_initialized(struct intel_ring_buffer *ring) { return ring->obj != NULL; } static inline unsigned intel_ring_flag(struct intel_ring_buffer *ring) { return 1 << ring->id; } static inline uint32_t intel_ring_sync_index(struct intel_ring_buffer *ring, struct intel_ring_buffer *other) { int idx; /* * cs -> 0 = vcs, 1 = bcs * vcs -> 0 = bcs, 1 = cs, * bcs -> 0 = cs, 1 = vcs. */ idx = (other - ring) - 1; if (idx < 0) idx += I915_NUM_RINGS; return idx; } -static inline uint32_t -intel_read_status_page(struct intel_ring_buffer *ring, int reg) +static inline u32 +intel_read_status_page(struct intel_ring_buffer *ring, + int reg) { - /* Ensure that the compiler doesn't optimize away the load. */ __compiler_membar(); return (atomic_load_acq_32(ring->status_page.page_addr + reg)); } void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n); static inline int intel_wait_ring_idle(struct intel_ring_buffer *ring) { return (intel_wait_ring_buffer(ring, ring->size - 8)); } int intel_ring_begin(struct intel_ring_buffer *ring, int n); static inline void intel_ring_emit(struct intel_ring_buffer *ring, - uint32_t data) + u32 data) { *(volatile uint32_t *)((char *)ring->virtual_start + ring->tail) = data; ring->tail += 4; } void intel_ring_advance(struct intel_ring_buffer *ring); uint32_t intel_ring_get_seqno(struct intel_ring_buffer *ring); int intel_init_render_ring_buffer(struct drm_device *dev); int intel_init_bsd_ring_buffer(struct drm_device *dev); int intel_init_blt_ring_buffer(struct drm_device *dev); u32 intel_ring_get_active_head(struct intel_ring_buffer *ring); void intel_ring_setup_status_page(struct intel_ring_buffer *ring); static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring) { return ring->tail; } void i915_trace_irq_get(struct intel_ring_buffer *ring, uint32_t seqno); /* DRI warts */ int intel_render_ring_init_dri(struct drm_device *dev, uint64_t start, uint32_t size); #endif /* _INTEL_RINGBUFFER_H_ */ Index: head/sys/dev/drm2/i915/intel_sdvo_regs.h =================================================================== --- head/sys/dev/drm2/i915/intel_sdvo_regs.h (revision 287495) +++ head/sys/dev/drm2/i915/intel_sdvo_regs.h (revision 287496) @@ -1,725 +1,732 @@ /* * Copyright © 2006-2007 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * Authors: * Eric Anholt * * $FreeBSD$ */ /** * @file SDVO command definitions and structures. */ #define SDVO_OUTPUT_FIRST (0) #define SDVO_OUTPUT_TMDS0 (1 << 0) #define SDVO_OUTPUT_RGB0 (1 << 1) #define SDVO_OUTPUT_CVBS0 (1 << 2) #define SDVO_OUTPUT_SVID0 (1 << 3) #define SDVO_OUTPUT_YPRPB0 (1 << 4) #define SDVO_OUTPUT_SCART0 (1 << 5) #define SDVO_OUTPUT_LVDS0 (1 << 6) #define SDVO_OUTPUT_TMDS1 (1 << 8) #define SDVO_OUTPUT_RGB1 (1 << 9) #define SDVO_OUTPUT_CVBS1 (1 << 10) #define SDVO_OUTPUT_SVID1 (1 << 11) #define SDVO_OUTPUT_YPRPB1 (1 << 12) #define SDVO_OUTPUT_SCART1 (1 << 13) #define SDVO_OUTPUT_LVDS1 (1 << 14) #define SDVO_OUTPUT_LAST (14) struct intel_sdvo_caps { u8 vendor_id; u8 device_id; u8 device_rev_id; u8 sdvo_version_major; u8 sdvo_version_minor; unsigned int sdvo_inputs_mask:2; unsigned int smooth_scaling:1; unsigned int sharp_scaling:1; unsigned int up_scaling:1; unsigned int down_scaling:1; unsigned int stall_support:1; unsigned int pad:1; u16 output_flags; } __attribute__((packed)); +/* Note: SDVO detailed timing flags match EDID misc flags. */ +#define DTD_FLAG_HSYNC_POSITIVE (1 << 1) +#define DTD_FLAG_VSYNC_POSITIVE (1 << 2) +#define DTD_FLAG_INTERLACE (1 << 7) + /** This matches the EDID DTD structure, more or less */ struct intel_sdvo_dtd { struct { u16 clock; /**< pixel clock, in 10kHz units */ u8 h_active; /**< lower 8 bits (pixels) */ u8 h_blank; /**< lower 8 bits (pixels) */ u8 h_high; /**< upper 4 bits each h_active, h_blank */ u8 v_active; /**< lower 8 bits (lines) */ u8 v_blank; /**< lower 8 bits (lines) */ u8 v_high; /**< upper 4 bits each v_active, v_blank */ } part1; struct { u8 h_sync_off; /**< lower 8 bits, from hblank start */ u8 h_sync_width; /**< lower 8 bits (pixels) */ /** lower 4 bits each vsync offset, vsync width */ u8 v_sync_off_width; /** * 2 high bits of hsync offset, 2 high bits of hsync width, * bits 4-5 of vsync offset, and 2 high bits of vsync width. */ u8 sync_off_width_high; u8 dtd_flags; u8 sdvo_flags; /** bits 6-7 of vsync offset at bits 6-7 */ u8 v_sync_off_high; u8 reserved; } part2; } __attribute__((packed)); struct intel_sdvo_pixel_clock_range { u16 min; /**< pixel clock, in 10kHz units */ u16 max; /**< pixel clock, in 10kHz units */ } __attribute__((packed)); struct intel_sdvo_preferred_input_timing_args { u16 clock; u16 width; u16 height; u8 interlace:1; u8 scaled:1; u8 pad:6; } __attribute__((packed)); /* I2C registers for SDVO */ #define SDVO_I2C_ARG_0 0x07 #define SDVO_I2C_ARG_1 0x06 #define SDVO_I2C_ARG_2 0x05 #define SDVO_I2C_ARG_3 0x04 #define SDVO_I2C_ARG_4 0x03 #define SDVO_I2C_ARG_5 0x02 #define SDVO_I2C_ARG_6 0x01 #define SDVO_I2C_ARG_7 0x00 #define SDVO_I2C_OPCODE 0x08 #define SDVO_I2C_CMD_STATUS 0x09 #define SDVO_I2C_RETURN_0 0x0a #define SDVO_I2C_RETURN_1 0x0b #define SDVO_I2C_RETURN_2 0x0c #define SDVO_I2C_RETURN_3 0x0d #define SDVO_I2C_RETURN_4 0x0e #define SDVO_I2C_RETURN_5 0x0f #define SDVO_I2C_RETURN_6 0x10 #define SDVO_I2C_RETURN_7 0x11 #define SDVO_I2C_VENDOR_BEGIN 0x20 /* Status results */ #define SDVO_CMD_STATUS_POWER_ON 0x0 #define SDVO_CMD_STATUS_SUCCESS 0x1 #define SDVO_CMD_STATUS_NOTSUPP 0x2 #define SDVO_CMD_STATUS_INVALID_ARG 0x3 #define SDVO_CMD_STATUS_PENDING 0x4 #define SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED 0x5 #define SDVO_CMD_STATUS_SCALING_NOT_SUPP 0x6 /* SDVO commands, argument/result registers */ #define SDVO_CMD_RESET 0x01 /** Returns a struct intel_sdvo_caps */ #define SDVO_CMD_GET_DEVICE_CAPS 0x02 #define SDVO_CMD_GET_FIRMWARE_REV 0x86 # define SDVO_DEVICE_FIRMWARE_MINOR SDVO_I2C_RETURN_0 # define SDVO_DEVICE_FIRMWARE_MAJOR SDVO_I2C_RETURN_1 # define SDVO_DEVICE_FIRMWARE_PATCH SDVO_I2C_RETURN_2 /** * Reports which inputs are trained (managed to sync). * * Devices must have trained within 2 vsyncs of a mode change. */ #define SDVO_CMD_GET_TRAINED_INPUTS 0x03 struct intel_sdvo_get_trained_inputs_response { unsigned int input0_trained:1; unsigned int input1_trained:1; unsigned int pad:6; } __attribute__((packed)); /** Returns a struct intel_sdvo_output_flags of active outputs. */ #define SDVO_CMD_GET_ACTIVE_OUTPUTS 0x04 /** * Sets the current set of active outputs. * * Takes a struct intel_sdvo_output_flags. Must be preceded by a SET_IN_OUT_MAP * on multi-output devices. */ #define SDVO_CMD_SET_ACTIVE_OUTPUTS 0x05 /** * Returns the current mapping of SDVO inputs to outputs on the device. * * Returns two struct intel_sdvo_output_flags structures. */ #define SDVO_CMD_GET_IN_OUT_MAP 0x06 struct intel_sdvo_in_out_map { u16 in0, in1; }; /** * Sets the current mapping of SDVO inputs to outputs on the device. * * Takes two struct i380_sdvo_output_flags structures. */ #define SDVO_CMD_SET_IN_OUT_MAP 0x07 /** * Returns a struct intel_sdvo_output_flags of attached displays. */ #define SDVO_CMD_GET_ATTACHED_DISPLAYS 0x0b /** * Returns a struct intel_sdvo_ouptut_flags of displays supporting hot plugging. */ #define SDVO_CMD_GET_HOT_PLUG_SUPPORT 0x0c /** * Takes a struct intel_sdvo_output_flags. */ #define SDVO_CMD_SET_ACTIVE_HOT_PLUG 0x0d /** * Returns a struct intel_sdvo_output_flags of displays with hot plug * interrupts enabled. */ #define SDVO_CMD_GET_ACTIVE_HOT_PLUG 0x0e #define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE 0x0f struct intel_sdvo_get_interrupt_event_source_response { u16 interrupt_status; unsigned int ambient_light_interrupt:1; unsigned int hdmi_audio_encrypt_change:1; unsigned int pad:6; } __attribute__((packed)); /** * Selects which input is affected by future input commands. * * Commands affected include SET_INPUT_TIMINGS_PART[12], * GET_INPUT_TIMINGS_PART[12], GET_PREFERRED_INPUT_TIMINGS_PART[12], * GET_INPUT_PIXEL_CLOCK_RANGE, and CREATE_PREFERRED_INPUT_TIMINGS. */ #define SDVO_CMD_SET_TARGET_INPUT 0x10 struct intel_sdvo_set_target_input_args { unsigned int target_1:1; unsigned int pad:7; } __attribute__((packed)); /** * Takes a struct intel_sdvo_output_flags of which outputs are targeted by * future output commands. * * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12], * GET_OUTPUT_TIMINGS_PART[12], and GET_OUTPUT_PIXEL_CLOCK_RANGE. */ #define SDVO_CMD_SET_TARGET_OUTPUT 0x11 #define SDVO_CMD_GET_INPUT_TIMINGS_PART1 0x12 #define SDVO_CMD_GET_INPUT_TIMINGS_PART2 0x13 #define SDVO_CMD_SET_INPUT_TIMINGS_PART1 0x14 #define SDVO_CMD_SET_INPUT_TIMINGS_PART2 0x15 #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART1 0x16 #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART2 0x17 #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART1 0x18 #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART2 0x19 /* Part 1 */ # define SDVO_DTD_CLOCK_LOW SDVO_I2C_ARG_0 # define SDVO_DTD_CLOCK_HIGH SDVO_I2C_ARG_1 # define SDVO_DTD_H_ACTIVE SDVO_I2C_ARG_2 # define SDVO_DTD_H_BLANK SDVO_I2C_ARG_3 # define SDVO_DTD_H_HIGH SDVO_I2C_ARG_4 # define SDVO_DTD_V_ACTIVE SDVO_I2C_ARG_5 # define SDVO_DTD_V_BLANK SDVO_I2C_ARG_6 # define SDVO_DTD_V_HIGH SDVO_I2C_ARG_7 /* Part 2 */ # define SDVO_DTD_HSYNC_OFF SDVO_I2C_ARG_0 # define SDVO_DTD_HSYNC_WIDTH SDVO_I2C_ARG_1 # define SDVO_DTD_VSYNC_OFF_WIDTH SDVO_I2C_ARG_2 # define SDVO_DTD_SYNC_OFF_WIDTH_HIGH SDVO_I2C_ARG_3 # define SDVO_DTD_DTD_FLAGS SDVO_I2C_ARG_4 # define SDVO_DTD_DTD_FLAG_INTERLACED (1 << 7) # define SDVO_DTD_DTD_FLAG_STEREO_MASK (3 << 5) # define SDVO_DTD_DTD_FLAG_INPUT_MASK (3 << 3) # define SDVO_DTD_DTD_FLAG_SYNC_MASK (3 << 1) # define SDVO_DTD_SDVO_FLAS SDVO_I2C_ARG_5 # define SDVO_DTD_SDVO_FLAG_STALL (1 << 7) # define SDVO_DTD_SDVO_FLAG_CENTERED (0 << 6) # define SDVO_DTD_SDVO_FLAG_UPPER_LEFT (1 << 6) # define SDVO_DTD_SDVO_FLAG_SCALING_MASK (3 << 4) # define SDVO_DTD_SDVO_FLAG_SCALING_NONE (0 << 4) # define SDVO_DTD_SDVO_FLAG_SCALING_SHARP (1 << 4) # define SDVO_DTD_SDVO_FLAG_SCALING_SMOOTH (2 << 4) # define SDVO_DTD_VSYNC_OFF_HIGH SDVO_I2C_ARG_6 /** * Generates a DTD based on the given width, height, and flags. * * This will be supported by any device supporting scaling or interlaced * modes. */ #define SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING 0x1a # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_LOW SDVO_I2C_ARG_0 # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_HIGH SDVO_I2C_ARG_1 # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_LOW SDVO_I2C_ARG_2 # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_HIGH SDVO_I2C_ARG_3 # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_LOW SDVO_I2C_ARG_4 # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_HIGH SDVO_I2C_ARG_5 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS SDVO_I2C_ARG_6 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_INTERLACED (1 << 0) # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_SCALED (1 << 1) #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1 0x1b #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2 0x1c /** Returns a struct intel_sdvo_pixel_clock_range */ #define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE 0x1d /** Returns a struct intel_sdvo_pixel_clock_range */ #define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE 0x1e /** Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */ #define SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS 0x1f /** Returns a byte containing a SDVO_CLOCK_RATE_MULT_* flag */ #define SDVO_CMD_GET_CLOCK_RATE_MULT 0x20 /** Takes a byte containing a SDVO_CLOCK_RATE_MULT_* flag */ #define SDVO_CMD_SET_CLOCK_RATE_MULT 0x21 # define SDVO_CLOCK_RATE_MULT_1X (1 << 0) # define SDVO_CLOCK_RATE_MULT_2X (1 << 1) # define SDVO_CLOCK_RATE_MULT_4X (1 << 3) #define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27 /** 6 bytes of bit flags for TV formats shared by all TV format functions */ struct intel_sdvo_tv_format { unsigned int ntsc_m:1; unsigned int ntsc_j:1; unsigned int ntsc_443:1; unsigned int pal_b:1; unsigned int pal_d:1; unsigned int pal_g:1; unsigned int pal_h:1; unsigned int pal_i:1; unsigned int pal_m:1; unsigned int pal_n:1; unsigned int pal_nc:1; unsigned int pal_60:1; unsigned int secam_b:1; unsigned int secam_d:1; unsigned int secam_g:1; unsigned int secam_k:1; unsigned int secam_k1:1; unsigned int secam_l:1; unsigned int secam_60:1; unsigned int hdtv_std_smpte_240m_1080i_59:1; unsigned int hdtv_std_smpte_240m_1080i_60:1; unsigned int hdtv_std_smpte_260m_1080i_59:1; unsigned int hdtv_std_smpte_260m_1080i_60:1; unsigned int hdtv_std_smpte_274m_1080i_50:1; unsigned int hdtv_std_smpte_274m_1080i_59:1; unsigned int hdtv_std_smpte_274m_1080i_60:1; unsigned int hdtv_std_smpte_274m_1080p_23:1; unsigned int hdtv_std_smpte_274m_1080p_24:1; unsigned int hdtv_std_smpte_274m_1080p_25:1; unsigned int hdtv_std_smpte_274m_1080p_29:1; unsigned int hdtv_std_smpte_274m_1080p_30:1; unsigned int hdtv_std_smpte_274m_1080p_50:1; unsigned int hdtv_std_smpte_274m_1080p_59:1; unsigned int hdtv_std_smpte_274m_1080p_60:1; unsigned int hdtv_std_smpte_295m_1080i_50:1; unsigned int hdtv_std_smpte_295m_1080p_50:1; unsigned int hdtv_std_smpte_296m_720p_59:1; unsigned int hdtv_std_smpte_296m_720p_60:1; unsigned int hdtv_std_smpte_296m_720p_50:1; unsigned int hdtv_std_smpte_293m_480p_59:1; unsigned int hdtv_std_smpte_170m_480i_59:1; unsigned int hdtv_std_iturbt601_576i_50:1; unsigned int hdtv_std_iturbt601_576p_50:1; unsigned int hdtv_std_eia_7702a_480i_60:1; unsigned int hdtv_std_eia_7702a_480p_60:1; unsigned int pad:3; } __attribute__((packed)); #define SDVO_CMD_GET_TV_FORMAT 0x28 #define SDVO_CMD_SET_TV_FORMAT 0x29 /** Returns the resolutiosn that can be used with the given TV format */ #define SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT 0x83 struct intel_sdvo_sdtv_resolution_request { unsigned int ntsc_m:1; unsigned int ntsc_j:1; unsigned int ntsc_443:1; unsigned int pal_b:1; unsigned int pal_d:1; unsigned int pal_g:1; unsigned int pal_h:1; unsigned int pal_i:1; unsigned int pal_m:1; unsigned int pal_n:1; unsigned int pal_nc:1; unsigned int pal_60:1; unsigned int secam_b:1; unsigned int secam_d:1; unsigned int secam_g:1; unsigned int secam_k:1; unsigned int secam_k1:1; unsigned int secam_l:1; unsigned int secam_60:1; unsigned int pad:5; } __attribute__((packed)); struct intel_sdvo_sdtv_resolution_reply { unsigned int res_320x200:1; unsigned int res_320x240:1; unsigned int res_400x300:1; unsigned int res_640x350:1; unsigned int res_640x400:1; unsigned int res_640x480:1; unsigned int res_704x480:1; unsigned int res_704x576:1; unsigned int res_720x350:1; unsigned int res_720x400:1; unsigned int res_720x480:1; unsigned int res_720x540:1; unsigned int res_720x576:1; unsigned int res_768x576:1; unsigned int res_800x600:1; unsigned int res_832x624:1; unsigned int res_920x766:1; unsigned int res_1024x768:1; unsigned int res_1280x1024:1; unsigned int pad:5; } __attribute__((packed)); /* Get supported resolution with squire pixel aspect ratio that can be scaled for the requested HDTV format */ #define SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT 0x85 struct intel_sdvo_hdtv_resolution_request { unsigned int hdtv_std_smpte_240m_1080i_59:1; unsigned int hdtv_std_smpte_240m_1080i_60:1; unsigned int hdtv_std_smpte_260m_1080i_59:1; unsigned int hdtv_std_smpte_260m_1080i_60:1; unsigned int hdtv_std_smpte_274m_1080i_50:1; unsigned int hdtv_std_smpte_274m_1080i_59:1; unsigned int hdtv_std_smpte_274m_1080i_60:1; unsigned int hdtv_std_smpte_274m_1080p_23:1; unsigned int hdtv_std_smpte_274m_1080p_24:1; unsigned int hdtv_std_smpte_274m_1080p_25:1; unsigned int hdtv_std_smpte_274m_1080p_29:1; unsigned int hdtv_std_smpte_274m_1080p_30:1; unsigned int hdtv_std_smpte_274m_1080p_50:1; unsigned int hdtv_std_smpte_274m_1080p_59:1; unsigned int hdtv_std_smpte_274m_1080p_60:1; unsigned int hdtv_std_smpte_295m_1080i_50:1; unsigned int hdtv_std_smpte_295m_1080p_50:1; unsigned int hdtv_std_smpte_296m_720p_59:1; unsigned int hdtv_std_smpte_296m_720p_60:1; unsigned int hdtv_std_smpte_296m_720p_50:1; unsigned int hdtv_std_smpte_293m_480p_59:1; unsigned int hdtv_std_smpte_170m_480i_59:1; unsigned int hdtv_std_iturbt601_576i_50:1; unsigned int hdtv_std_iturbt601_576p_50:1; unsigned int hdtv_std_eia_7702a_480i_60:1; unsigned int hdtv_std_eia_7702a_480p_60:1; unsigned int pad:6; } __attribute__((packed)); struct intel_sdvo_hdtv_resolution_reply { unsigned int res_640x480:1; unsigned int res_800x600:1; unsigned int res_1024x768:1; unsigned int res_1280x960:1; unsigned int res_1400x1050:1; unsigned int res_1600x1200:1; unsigned int res_1920x1440:1; unsigned int res_2048x1536:1; unsigned int res_2560x1920:1; unsigned int res_3200x2400:1; unsigned int res_3840x2880:1; unsigned int pad1:5; unsigned int res_848x480:1; unsigned int res_1064x600:1; unsigned int res_1280x720:1; unsigned int res_1360x768:1; unsigned int res_1704x960:1; unsigned int res_1864x1050:1; unsigned int res_1920x1080:1; unsigned int res_2128x1200:1; unsigned int res_2560x1400:1; unsigned int res_2728x1536:1; unsigned int res_3408x1920:1; unsigned int res_4264x2400:1; unsigned int res_5120x2880:1; unsigned int pad2:3; unsigned int res_768x480:1; unsigned int res_960x600:1; unsigned int res_1152x720:1; unsigned int res_1124x768:1; unsigned int res_1536x960:1; unsigned int res_1680x1050:1; unsigned int res_1728x1080:1; unsigned int res_1920x1200:1; unsigned int res_2304x1440:1; unsigned int res_2456x1536:1; unsigned int res_3072x1920:1; unsigned int res_3840x2400:1; unsigned int res_4608x2880:1; unsigned int pad3:3; unsigned int res_1280x1024:1; unsigned int pad4:7; unsigned int res_1280x768:1; unsigned int pad5:7; } __attribute__((packed)); /* Get supported power state returns info for encoder and monitor, rely on last SetTargetInput and SetTargetOutput calls */ #define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a /* Get power state returns info for encoder and monitor, rely on last SetTargetInput and SetTargetOutput calls */ #define SDVO_CMD_GET_POWER_STATE 0x2b #define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b #define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c # define SDVO_ENCODER_STATE_ON (1 << 0) # define SDVO_ENCODER_STATE_STANDBY (1 << 1) # define SDVO_ENCODER_STATE_SUSPEND (1 << 2) # define SDVO_ENCODER_STATE_OFF (1 << 3) # define SDVO_MONITOR_STATE_ON (1 << 4) # define SDVO_MONITOR_STATE_STANDBY (1 << 5) # define SDVO_MONITOR_STATE_SUSPEND (1 << 6) # define SDVO_MONITOR_STATE_OFF (1 << 7) #define SDVO_CMD_GET_MAX_PANEL_POWER_SEQUENCING 0x2d #define SDVO_CMD_GET_PANEL_POWER_SEQUENCING 0x2e #define SDVO_CMD_SET_PANEL_POWER_SEQUENCING 0x2f /** * The panel power sequencing parameters are in units of milliseconds. * The high fields are bits 8:9 of the 10-bit values. */ struct sdvo_panel_power_sequencing { u8 t0; u8 t1; u8 t2; u8 t3; u8 t4; unsigned int t0_high:2; unsigned int t1_high:2; unsigned int t2_high:2; unsigned int t3_high:2; unsigned int t4_high:2; unsigned int pad:6; } __attribute__((packed)); #define SDVO_CMD_GET_MAX_BACKLIGHT_LEVEL 0x30 struct sdvo_max_backlight_reply { u8 max_value; u8 default_value; } __attribute__((packed)); #define SDVO_CMD_GET_BACKLIGHT_LEVEL 0x31 #define SDVO_CMD_SET_BACKLIGHT_LEVEL 0x32 #define SDVO_CMD_GET_AMBIENT_LIGHT 0x33 struct sdvo_get_ambient_light_reply { u16 trip_low; u16 trip_high; u16 value; } __attribute__((packed)); #define SDVO_CMD_SET_AMBIENT_LIGHT 0x34 struct sdvo_set_ambient_light_reply { u16 trip_low; u16 trip_high; unsigned int enable:1; unsigned int pad:7; } __attribute__((packed)); /* Set display power state */ #define SDVO_CMD_SET_DISPLAY_POWER_STATE 0x7d # define SDVO_DISPLAY_STATE_ON (1 << 0) # define SDVO_DISPLAY_STATE_STANDBY (1 << 1) # define SDVO_DISPLAY_STATE_SUSPEND (1 << 2) # define SDVO_DISPLAY_STATE_OFF (1 << 3) #define SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS 0x84 struct intel_sdvo_enhancements_reply { unsigned int flicker_filter:1; unsigned int flicker_filter_adaptive:1; unsigned int flicker_filter_2d:1; unsigned int saturation:1; unsigned int hue:1; unsigned int brightness:1; unsigned int contrast:1; unsigned int overscan_h:1; unsigned int overscan_v:1; unsigned int hpos:1; unsigned int vpos:1; unsigned int sharpness:1; unsigned int dot_crawl:1; unsigned int dither:1; unsigned int tv_chroma_filter:1; unsigned int tv_luma_filter:1; } __attribute__((packed)); /* Picture enhancement limits below are dependent on the current TV format, * and thus need to be queried and set after it. */ #define SDVO_CMD_GET_MAX_FLICKER_FILTER 0x4d #define SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE 0x7b #define SDVO_CMD_GET_MAX_FLICKER_FILTER_2D 0x52 #define SDVO_CMD_GET_MAX_SATURATION 0x55 #define SDVO_CMD_GET_MAX_HUE 0x58 #define SDVO_CMD_GET_MAX_BRIGHTNESS 0x5b #define SDVO_CMD_GET_MAX_CONTRAST 0x5e #define SDVO_CMD_GET_MAX_OVERSCAN_H 0x61 #define SDVO_CMD_GET_MAX_OVERSCAN_V 0x64 #define SDVO_CMD_GET_MAX_HPOS 0x67 #define SDVO_CMD_GET_MAX_VPOS 0x6a #define SDVO_CMD_GET_MAX_SHARPNESS 0x6d #define SDVO_CMD_GET_MAX_TV_CHROMA_FILTER 0x74 #define SDVO_CMD_GET_MAX_TV_LUMA_FILTER 0x77 struct intel_sdvo_enhancement_limits_reply { u16 max_value; u16 default_value; } __attribute__((packed)); #define SDVO_CMD_GET_LVDS_PANEL_INFORMATION 0x7f #define SDVO_CMD_SET_LVDS_PANEL_INFORMATION 0x80 # define SDVO_LVDS_COLOR_DEPTH_18 (0 << 0) # define SDVO_LVDS_COLOR_DEPTH_24 (1 << 0) # define SDVO_LVDS_CONNECTOR_SPWG (0 << 2) # define SDVO_LVDS_CONNECTOR_OPENLDI (1 << 2) # define SDVO_LVDS_SINGLE_CHANNEL (0 << 4) # define SDVO_LVDS_DUAL_CHANNEL (1 << 4) #define SDVO_CMD_GET_FLICKER_FILTER 0x4e #define SDVO_CMD_SET_FLICKER_FILTER 0x4f #define SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE 0x50 #define SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE 0x51 #define SDVO_CMD_GET_FLICKER_FILTER_2D 0x53 #define SDVO_CMD_SET_FLICKER_FILTER_2D 0x54 #define SDVO_CMD_GET_SATURATION 0x56 #define SDVO_CMD_SET_SATURATION 0x57 #define SDVO_CMD_GET_HUE 0x59 #define SDVO_CMD_SET_HUE 0x5a #define SDVO_CMD_GET_BRIGHTNESS 0x5c #define SDVO_CMD_SET_BRIGHTNESS 0x5d #define SDVO_CMD_GET_CONTRAST 0x5f #define SDVO_CMD_SET_CONTRAST 0x60 #define SDVO_CMD_GET_OVERSCAN_H 0x62 #define SDVO_CMD_SET_OVERSCAN_H 0x63 #define SDVO_CMD_GET_OVERSCAN_V 0x65 #define SDVO_CMD_SET_OVERSCAN_V 0x66 #define SDVO_CMD_GET_HPOS 0x68 #define SDVO_CMD_SET_HPOS 0x69 #define SDVO_CMD_GET_VPOS 0x6b #define SDVO_CMD_SET_VPOS 0x6c #define SDVO_CMD_GET_SHARPNESS 0x6e #define SDVO_CMD_SET_SHARPNESS 0x6f #define SDVO_CMD_GET_TV_CHROMA_FILTER 0x75 #define SDVO_CMD_SET_TV_CHROMA_FILTER 0x76 #define SDVO_CMD_GET_TV_LUMA_FILTER 0x78 #define SDVO_CMD_SET_TV_LUMA_FILTER 0x79 struct intel_sdvo_enhancements_arg { u16 value; } __attribute__((packed)); #define SDVO_CMD_GET_DOT_CRAWL 0x70 #define SDVO_CMD_SET_DOT_CRAWL 0x71 # define SDVO_DOT_CRAWL_ON (1 << 0) # define SDVO_DOT_CRAWL_DEFAULT_ON (1 << 1) #define SDVO_CMD_GET_DITHER 0x72 #define SDVO_CMD_SET_DITHER 0x73 # define SDVO_DITHER_ON (1 << 0) # define SDVO_DITHER_DEFAULT_ON (1 << 1) #define SDVO_CMD_SET_CONTROL_BUS_SWITCH 0x7a # define SDVO_CONTROL_BUS_PROM (1 << 0) # define SDVO_CONTROL_BUS_DDC1 (1 << 1) # define SDVO_CONTROL_BUS_DDC2 (1 << 2) # define SDVO_CONTROL_BUS_DDC3 (1 << 3) /* HDMI op codes */ #define SDVO_CMD_GET_SUPP_ENCODE 0x9d #define SDVO_CMD_GET_ENCODE 0x9e #define SDVO_CMD_SET_ENCODE 0x9f #define SDVO_ENCODE_DVI 0x0 #define SDVO_ENCODE_HDMI 0x1 #define SDVO_CMD_SET_PIXEL_REPLI 0x8b #define SDVO_CMD_GET_PIXEL_REPLI 0x8c #define SDVO_CMD_GET_COLORIMETRY_CAP 0x8d #define SDVO_CMD_SET_COLORIMETRY 0x8e #define SDVO_COLORIMETRY_RGB256 0x0 #define SDVO_COLORIMETRY_RGB220 0x1 #define SDVO_COLORIMETRY_YCrCb422 0x3 #define SDVO_COLORIMETRY_YCrCb444 0x4 #define SDVO_CMD_GET_COLORIMETRY 0x8f #define SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER 0x90 #define SDVO_CMD_SET_AUDIO_STAT 0x91 #define SDVO_CMD_GET_AUDIO_STAT 0x92 #define SDVO_CMD_SET_HBUF_INDEX 0x93 + #define SDVO_HBUF_INDEX_ELD 0 + #define SDVO_HBUF_INDEX_AVI_IF 1 #define SDVO_CMD_GET_HBUF_INDEX 0x94 #define SDVO_CMD_GET_HBUF_INFO 0x95 #define SDVO_CMD_SET_HBUF_AV_SPLIT 0x96 #define SDVO_CMD_GET_HBUF_AV_SPLIT 0x97 #define SDVO_CMD_SET_HBUF_DATA 0x98 #define SDVO_CMD_GET_HBUF_DATA 0x99 #define SDVO_CMD_SET_HBUF_TXRATE 0x9a #define SDVO_CMD_GET_HBUF_TXRATE 0x9b #define SDVO_HBUF_TX_DISABLED (0 << 6) #define SDVO_HBUF_TX_ONCE (2 << 6) #define SDVO_HBUF_TX_VSYNC (3 << 6) #define SDVO_CMD_GET_AUDIO_TX_INFO 0x9c #define SDVO_NEED_TO_STALL (1 << 7) struct intel_sdvo_encode { u8 dvi_rev; u8 hdmi_rev; } __attribute__ ((packed));