Index: head/sys/arm/allwinner/a10_clk.c =================================================================== --- head/sys/arm/allwinner/a10_clk.c (revision 285102) +++ head/sys/arm/allwinner/a10_clk.c (revision 285103) @@ -1,326 +1,317 @@ /*- * Copyright (c) 2013 Ganbold Tsagaankhuu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* Simple clock driver for Allwinner A10 */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include -#include -#include -#include #include -#include -#include -#include #include -#include #include - -#include #include "a10_clk.h" struct a10_ccm_softc { struct resource *res; bus_space_tag_t bst; bus_space_handle_t bsh; int pll6_enabled; }; static struct a10_ccm_softc *a10_ccm_sc = NULL; #define ccm_read_4(sc, reg) \ bus_space_read_4((sc)->bst, (sc)->bsh, (reg)) #define ccm_write_4(sc, reg, val) \ bus_space_write_4((sc)->bst, (sc)->bsh, (reg), (val)) static int a10_ccm_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "allwinner,sun4i-ccm")) { device_set_desc(dev, "Allwinner Clock Control Module"); return(BUS_PROBE_DEFAULT); } return (ENXIO); } static int a10_ccm_attach(device_t dev) { struct a10_ccm_softc *sc = device_get_softc(dev); int rid = 0; if (a10_ccm_sc) return (ENXIO); sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->res) { device_printf(dev, "could not allocate resource\n"); return (ENXIO); } sc->bst = rman_get_bustag(sc->res); sc->bsh = rman_get_bushandle(sc->res); a10_ccm_sc = sc; return (0); } static device_method_t a10_ccm_methods[] = { DEVMETHOD(device_probe, a10_ccm_probe), DEVMETHOD(device_attach, a10_ccm_attach), { 0, 0 } }; static driver_t a10_ccm_driver = { "a10_ccm", a10_ccm_methods, sizeof(struct a10_ccm_softc), }; static devclass_t a10_ccm_devclass; DRIVER_MODULE(a10_ccm, simplebus, a10_ccm_driver, a10_ccm_devclass, 0, 0); int a10_clk_usb_activate(void) { struct a10_ccm_softc *sc = a10_ccm_sc; uint32_t reg_value; if (sc == NULL) return (ENXIO); /* Gating AHB clock for USB */ reg_value = ccm_read_4(sc, CCM_AHB_GATING0); reg_value |= CCM_AHB_GATING_USB0; /* AHB clock gate usb0 */ reg_value |= CCM_AHB_GATING_EHCI0; /* AHB clock gate ehci0 */ reg_value |= CCM_AHB_GATING_EHCI1; /* AHB clock gate ehci1 */ ccm_write_4(sc, CCM_AHB_GATING0, reg_value); /* Enable clock for USB */ reg_value = ccm_read_4(sc, CCM_USB_CLK); reg_value |= CCM_USB_PHY; /* USBPHY */ reg_value |= CCM_USB0_RESET; /* disable reset for USB0 */ reg_value |= CCM_USB1_RESET; /* disable reset for USB1 */ reg_value |= CCM_USB2_RESET; /* disable reset for USB2 */ ccm_write_4(sc, CCM_USB_CLK, reg_value); return (0); } int a10_clk_usb_deactivate(void) { struct a10_ccm_softc *sc = a10_ccm_sc; uint32_t reg_value; if (sc == NULL) return (ENXIO); /* Disable clock for USB */ reg_value = ccm_read_4(sc, CCM_USB_CLK); reg_value &= ~CCM_USB_PHY; /* USBPHY */ reg_value &= ~CCM_USB0_RESET; /* reset for USB0 */ reg_value &= ~CCM_USB1_RESET; /* reset for USB1 */ reg_value &= ~CCM_USB2_RESET; /* reset for USB2 */ ccm_write_4(sc, CCM_USB_CLK, reg_value); /* Disable gating AHB clock for USB */ reg_value = ccm_read_4(sc, CCM_AHB_GATING0); reg_value &= ~CCM_AHB_GATING_USB0; /* disable AHB clock gate usb0 */ reg_value &= ~CCM_AHB_GATING_EHCI0; /* disable AHB clock gate ehci0 */ reg_value &= ~CCM_AHB_GATING_EHCI1; /* disable AHB clock gate ehci1 */ ccm_write_4(sc, CCM_AHB_GATING0, reg_value); return (0); } int a10_clk_emac_activate(void) { struct a10_ccm_softc *sc = a10_ccm_sc; uint32_t reg_value; if (sc == NULL) return (ENXIO); /* Gating AHB clock for EMAC */ reg_value = ccm_read_4(sc, CCM_AHB_GATING0); reg_value |= CCM_AHB_GATING_EMAC; ccm_write_4(sc, CCM_AHB_GATING0, reg_value); return (0); } static void a10_clk_pll6_enable(void) { struct a10_ccm_softc *sc; uint32_t reg_value; /* * SATA needs PLL6 to be a 100MHz clock. * The SATA output frequency is 24MHz * n * k / m / 6. * To get to 100MHz, k & m must be equal and n must be 25. * For other uses the output frequency is 24MHz * n * k / 2. */ sc = a10_ccm_sc; if (sc->pll6_enabled) return; reg_value = ccm_read_4(sc, CCM_PLL6_CFG); reg_value &= ~CCM_PLL_CFG_BYPASS; reg_value &= ~(CCM_PLL_CFG_FACTOR_K | CCM_PLL_CFG_FACTOR_M | CCM_PLL_CFG_FACTOR_N); reg_value |= (25 << CCM_PLL_CFG_FACTOR_N_SHIFT); reg_value |= CCM_PLL6_CFG_SATA_CLKEN; reg_value |= CCM_PLL_CFG_ENABLE; ccm_write_4(sc, CCM_PLL6_CFG, reg_value); sc->pll6_enabled = 1; } static unsigned int a10_clk_pll6_get_rate(void) { struct a10_ccm_softc *sc; uint32_t k, n, reg_value; sc = a10_ccm_sc; reg_value = ccm_read_4(sc, CCM_PLL6_CFG); n = ((reg_value & CCM_PLL_CFG_FACTOR_N) >> CCM_PLL_CFG_FACTOR_N_SHIFT); k = ((reg_value & CCM_PLL_CFG_FACTOR_K) >> CCM_PLL_CFG_FACTOR_K_SHIFT) + 1; return ((CCM_CLK_REF_FREQ * n * k) / 2); } int a10_clk_ahci_activate(void) { struct a10_ccm_softc *sc; uint32_t reg_value; sc = a10_ccm_sc; if (sc == NULL) return (ENXIO); a10_clk_pll6_enable(); /* Gating AHB clock for SATA */ reg_value = ccm_read_4(sc, CCM_AHB_GATING0); reg_value |= CCM_AHB_GATING_SATA; ccm_write_4(sc, CCM_AHB_GATING0, reg_value); DELAY(1000); ccm_write_4(sc, CCM_SATA_CLK, CCM_PLL_CFG_ENABLE); return (0); } int a10_clk_mmc_activate(int devid) { struct a10_ccm_softc *sc; uint32_t reg_value; sc = a10_ccm_sc; if (sc == NULL) return (ENXIO); a10_clk_pll6_enable(); /* Gating AHB clock for SD/MMC */ reg_value = ccm_read_4(sc, CCM_AHB_GATING0); reg_value |= CCM_AHB_GATING_SDMMC0 << devid; ccm_write_4(sc, CCM_AHB_GATING0, reg_value); return (0); } int a10_clk_mmc_cfg(int devid, int freq) { struct a10_ccm_softc *sc; uint32_t clksrc, m, n, ophase, phase, reg_value; unsigned int pll_freq; sc = a10_ccm_sc; if (sc == NULL) return (ENXIO); freq /= 1000; if (freq <= 400) { pll_freq = CCM_CLK_REF_FREQ / 1000; clksrc = CCM_SD_CLK_SRC_SEL_OSC24M; ophase = 0; phase = 0; n = 2; } else if (freq <= 25000) { pll_freq = a10_clk_pll6_get_rate() / 1000; clksrc = CCM_SD_CLK_SRC_SEL_PLL6; ophase = 0; phase = 5; n = 2; } else if (freq <= 50000) { pll_freq = a10_clk_pll6_get_rate() / 1000; clksrc = CCM_SD_CLK_SRC_SEL_PLL6; ophase = 3; phase = 5; n = 0; } else return (EINVAL); m = ((pll_freq / (1 << n)) / (freq)) - 1; reg_value = ccm_read_4(sc, CCM_MMC0_SCLK_CFG + (devid * 4)); reg_value &= ~CCM_SD_CLK_SRC_SEL; reg_value |= (clksrc << CCM_SD_CLK_SRC_SEL_SHIFT); reg_value &= ~CCM_SD_CLK_PHASE_CTR; reg_value |= (phase << CCM_SD_CLK_PHASE_CTR_SHIFT); reg_value &= ~CCM_SD_CLK_DIV_RATIO_N; reg_value |= (n << CCM_SD_CLK_DIV_RATIO_N_SHIFT); reg_value &= ~CCM_SD_CLK_OPHASE_CTR; reg_value |= (ophase << CCM_SD_CLK_OPHASE_CTR_SHIFT); reg_value &= ~CCM_SD_CLK_DIV_RATIO_M; reg_value |= m; reg_value |= CCM_PLL_CFG_ENABLE; ccm_write_4(sc, CCM_MMC0_SCLK_CFG + (devid * 4), reg_value); return (0); } Index: head/sys/arm/allwinner/a10_clk.h =================================================================== --- head/sys/arm/allwinner/a10_clk.h (revision 285102) +++ head/sys/arm/allwinner/a10_clk.h (revision 285103) @@ -1,148 +1,146 @@ /*- * Copyright (c) 2013 Ganbold Tsagaankhuu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _A10_CLK_H_ #define _A10_CLK_H_ -#define CCMU_BASE 0xe1c20000 - #define CCM_PLL1_CFG 0x0000 #define CCM_PLL1_TUN 0x0004 #define CCM_PLL2_CFG 0x0008 #define CCM_PLL2_TUN 0x000c #define CCM_PLL3_CFG 0x0010 #define CCM_PLL3_TUN 0x0014 #define CCM_PLL4_CFG 0x0018 #define CCM_PLL4_TUN 0x001c #define CCM_PLL5_CFG 0x0020 #define CCM_PLL5_TUN 0x0024 #define CCM_PLL6_CFG 0x0028 #define CCM_PLL6_TUN 0x002c #define CCM_PLL7_CFG 0x0030 #define CCM_PLL7_TUN 0x0034 #define CCM_PLL1_TUN2 0x0038 #define CCM_PLL5_TUN2 0x003c #define CCM_PLL_LOCK_DBG 0x004c #define CCM_OSC24M_CFG 0x0050 #define CCM_CPU_AHB_APB0_CFG 0x0054 #define CCM_APB1_CLK_DIV 0x0058 #define CCM_AXI_GATING 0x005c #define CCM_AHB_GATING0 0x0060 #define CCM_AHB_GATING1 0x0064 #define CCM_APB0_GATING 0x0068 #define CCM_APB1_GATING 0x006c #define CCM_NAND_SCLK_CFG 0x0080 #define CCM_MS_SCLK_CFG 0x0084 #define CCM_MMC0_SCLK_CFG 0x0088 #define CCM_MMC1_SCLK_CFG 0x008c #define CCM_MMC2_SCLK_CFG 0x0090 #define CCM_MMC3_SCLK_CFG 0x0094 #define CCM_TS_CLK 0x0098 #define CCM_SS_CLK 0x009c #define CCM_SPI0_CLK 0x00a0 #define CCM_SPI1_CLK 0x00a4 #define CCM_SPI2_CLK 0x00a8 #define CCM_PATA_CLK 0x00ac #define CCM_IR0_CLK 0x00b0 #define CCM_IR1_CLK 0x00b4 #define CCM_IIS_CLK 0x00b8 #define CCM_AC97_CLK 0x00bc #define CCM_SPDIF_CLK 0x00c0 #define CCM_KEYPAD_CLK 0x00c4 #define CCM_SATA_CLK 0x00c8 #define CCM_USB_CLK 0x00cc #define CCM_GPS_CLK 0x00d0 #define CCM_SPI3_CLK 0x00d4 #define CCM_DRAM_CLK 0x0100 #define CCM_BE0_SCLK 0x0104 #define CCM_BE1_SCLK 0x0108 #define CCM_FE0_CLK 0x010c #define CCM_FE1_CLK 0x0110 #define CCM_MP_CLK 0x0114 #define CCM_LCD0_CH0_CLK 0x0118 #define CCM_LCD1_CH0_CLK 0x011c #define CCM_CSI_ISP_CLK 0x0120 #define CCM_TVD_CLK 0x0128 #define CCM_LCD0_CH1_CLK 0x012c #define CCM_LCD1_CH1_CLK 0x0130 #define CCM_CS0_CLK 0x0134 #define CCM_CS1_CLK 0x0138 #define CCM_VE_CLK 0x013c #define CCM_AUDIO_CODEC_CLK 0x0140 #define CCM_AVS_CLK 0x0144 #define CCM_ACE_CLK 0x0148 #define CCM_LVDS_CLK 0x014c #define CCM_HDMI_CLK 0x0150 #define CCM_MALI400_CLK 0x0154 #define CCM_AHB_GATING_USB0 (1 << 0) #define CCM_AHB_GATING_EHCI0 (1 << 1) #define CCM_AHB_GATING_EHCI1 (1 << 3) #define CCM_AHB_GATING_SDMMC0 (1 << 8) #define CCM_AHB_GATING_EMAC (1 << 17) #define CCM_AHB_GATING_SATA (1 << 25) #define CCM_USB_PHY (1 << 8) #define CCM_USB0_RESET (1 << 0) #define CCM_USB1_RESET (1 << 1) #define CCM_USB2_RESET (1 << 2) #define CCM_PLL_CFG_ENABLE (1U << 31) #define CCM_PLL_CFG_BYPASS (1U << 30) #define CCM_PLL_CFG_PLL5 (1U << 25) #define CCM_PLL_CFG_PLL6 (1U << 24) #define CCM_PLL_CFG_FACTOR_N 0x1f00 #define CCM_PLL_CFG_FACTOR_N_SHIFT 8 #define CCM_PLL_CFG_FACTOR_K 0x30 #define CCM_PLL_CFG_FACTOR_K_SHIFT 4 #define CCM_PLL_CFG_FACTOR_M 0x3 #define CCM_PLL6_CFG_SATA_CLKEN (1U << 14) #define CCM_SD_CLK_SRC_SEL 0x3000000 #define CCM_SD_CLK_SRC_SEL_SHIFT 24 #define CCM_SD_CLK_SRC_SEL_OSC24M 0 #define CCM_SD_CLK_SRC_SEL_PLL6 1 #define CCM_SD_CLK_PHASE_CTR 0x700000 #define CCM_SD_CLK_PHASE_CTR_SHIFT 20 #define CCM_SD_CLK_DIV_RATIO_N 0x30000 #define CCM_SD_CLK_DIV_RATIO_N_SHIFT 16 #define CCM_SD_CLK_OPHASE_CTR 0x700 #define CCM_SD_CLK_OPHASE_CTR_SHIFT 8 #define CCM_SD_CLK_DIV_RATIO_M 0xf #define CCM_CLK_REF_FREQ 24000000U int a10_clk_usb_activate(void); int a10_clk_usb_deactivate(void); int a10_clk_emac_activate(void); int a10_clk_ahci_activate(void); int a10_clk_mmc_activate(int); int a10_clk_mmc_cfg(int, int); #endif /* _A10_CLK_H_ */