Index: head/share/man/man4/sfxge.4 =================================================================== --- head/share/man/man4/sfxge.4 (revision 283513) +++ head/share/man/man4/sfxge.4 (revision 283514) @@ -1,162 +1,169 @@ -.\" Copyright (c) 2011 Solarflare Communications, Inc. +.\" Copyright (c) 2011-2015 Solarflare Communications Inc. .\" All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without -.\" modification, are permitted provided that the following conditions -.\" are met: -.\" 1. Redistributions of source code must retain the above copyright -.\" notice, this list of conditions and the following disclaimer. -.\" 2. Redistributions in binary form must reproduce the above copyright -.\" notice, this list of conditions and the following disclaimer in the -.\" documentation and/or other materials provided with the distribution. +.\" modification, are permitted provided that the following conditions are met: .\" -.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -.\" SUCH DAMAGE. +.\" 1. Redistributions of source code must retain the above copyright notice, +.\" this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright notice, +.\" this list of conditions and the following disclaimer in the documentation +.\" and/or other materials provided with the distribution. .\" +.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +.\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +.\" THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +.\" PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +.\" CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +.\" EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +.\" PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +.\" OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +.\" WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +.\" OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +.\" EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +.\" +.\" The views and conclusions contained in the software and documentation are +.\" those of the authors and should not be interpreted as representing official +.\" policies, either expressed or implied, of the FreeBSD Project. +.\" .\" $FreeBSD$ .\" .Dd February 22, 2015 .Dt SFXGE 4 .Os .Sh NAME .Nm sfxge .Nd "Solarflare 10Gb Ethernet adapter driver" .Sh SYNOPSIS To compile this driver into the kernel, place the following lines in your kernel configuration file: .Bd -ragged -offset indent .Cd "device sfxge" .Ed .Pp To load the driver as a module at boot time, place the following line in .Xr loader.conf 5 : .Bd -literal -offset indent sfxge_load="YES" .Ed .Sh DESCRIPTION The .Nm driver provides support for 10Gb Ethernet adapters based on Solarflare SFC9000 family controllers. The driver supports jumbo frames, transmit/receive checksum offload, TCP Segmentation Offload (TSO), Large Receive Offload (LRO), VLAN checksum offload, VLAN TSO, and Receive Side Scaling (RSS) using MSI-X interrupts. .Pp The driver allocates 1 receive queue, transmit queue, event queue and IRQ per CPU up to a maximum of 64. IRQ affinities should be spread out using .Xr cpuset 1 . Interrupt moderation may be controlled through the sysctl .Va dev.sfxge.%d.int_mod (units are microseconds). .Pp For more information on configuring this device, see .Xr ifconfig 8 . .Pp A large number of MAC, PHY and data path statistics are available under the sysctl .Va dev.sfxge.%d.stats . The adapter's VPD fields including its serial number are available under the sysctl .Va dev.sfxge.%d.vpd . .Sh HARDWARE The .Nm driver supports all 10Gb Ethernet adapters based on Solarflare SFC9000 family controllers. .Sh LOADER TUNABLES Tunables can be set at the .Xr loader 8 prompt before booting the kernel or stored in .Xr loader.conf 5 . Actual values can be obtained using .Xr sysctl 8 . .Bl -tag -width indent .It Va hw.sfxge.rx_ring The maximum number of descriptors in a receive queue ring. Supported values are: 512, 1024, 2048 and 4096. .It Va hw.sfxge.tx_ring The maximum number of descriptors in a transmit queue ring. Supported values are: 512, 1024, 2048 and 4096. .It Va hw.sfxge.tx_dpl_get_max The maximum length of the deferred packet .Dq get-list for queued transmit packets (TCP and non-TCP), used only if the transmit queue lock can be acquired. If a packet is dropped, the .Va tx_get_overflow counter is incremented and the local sender receives ENOBUFS. The value must be greater than 0. .It Va hw.sfxge.tx_dpl_get_non_tcp_max The maximum number of non-TCP packets in the deferred packet .Dq get-list , used only if the transmit queue lock can be acquired. If a packet is dropped, the .Va tx_get_non_tcp_overflow counter is incremented and the local sender receives ENOBUFS. The value must be greater than 0. .It Va hw.sfxge.tx_dpl_put_max The maximum length of the deferred packet .Dq put-list for queued transmit packets, used if the transmit queue lock cannot be acquired. If a packet is dropped, the .Va tx_put_overflow counter is incremented and the local sender receives ENOBUFS. The value must be greater than or equal to 0. +.It Va hw.sfxge.tso_fw_assisted +Enable/disable usage of FW-assisted TSO if supported by NIC firmware. +Enabled by default. .It Va hw.sfxge.N.max_rss_channels The maximum number of allocated RSS channels for the Nth adapter. If set to 0 or unset, the number of channels is determined by the number of CPU cores. .It Va hw.sfxge.lro.table_size Size of the LRO hash table. Must be a power of 2. A larger table means we can accelerate a larger number of streams. .It Va hw.sfxge.lro.chain_max The maximum length of a hash chain. If chains get too long then the lookup time increases and may exceed the benefit of LRO. .It Va hw.sfxge.lro.idle_ticks The maximum time (in ticks) that a connection can be idle before it's LRO state is discarded. .It Va hw.sfxge.lro.slow_start_packets Number of packets with payload that must arrive in-order before a connection is eligible for LRO. The idea is we should avoid coalescing segments when the sender is in slow-start because reducing the ACK rate can damage performance. .It Va hw.sfxge.lro.loss_packets Number of packets with payload that must arrive in-order following loss before a connection is eligible for LRO. The idea is we should avoid coalescing segments when the sender is recovering from loss, because reducing the ACK rate can damage performance. .El .Sh SUPPORT For general information and support, go to the Solarflare support website at: .Pa https://support.solarflare.com . .Sh SEE ALSO .Xr cpuset 1 , .Xr arp 4 , .Xr netintro 4 , .Xr ng_ether 4 , .Xr vlan 4 , .Xr ifconfig 8 .Sh AUTHORS The .Nm driver was written by .An Philip Paeps and .An Solarflare Communications, Inc. Property changes on: head/share/man/man4/sfxge.4 ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/conf/files =================================================================== --- head/sys/conf/files (revision 283513) +++ head/sys/conf/files (revision 283514) @@ -1,4061 +1,4030 @@ # $FreeBSD$ # # The long compile-with and dependency lines are required because of # limitations in config: backslash-newline doesn't work in strings, and # dependency lines other than the first are silently ignored. # acpi_quirks.h optional acpi \ dependency "$S/tools/acpi_quirks2h.awk $S/dev/acpica/acpi_quirks" \ compile-with "${AWK} -f $S/tools/acpi_quirks2h.awk $S/dev/acpica/acpi_quirks" \ no-obj no-implicit-rule before-depend \ clean "acpi_quirks.h" # # The 'fdt_dtb_file' target covers an actual DTB file name, which is derived # from the specified source (DTS) file: .dts -> .dtb # fdt_dtb_file optional fdt fdt_dtb_static \ compile-with "sh -c 'MACHINE=${MACHINE} $S/tools/fdt/make_dtb.sh $S ${FDT_DTS_FILE} ${.CURDIR}'" \ no-obj no-implicit-rule before-depend \ clean "${FDT_DTS_FILE:R}.dtb" fdt_static_dtb.h optional fdt fdt_dtb_static \ compile-with "sh -c 'MACHINE=${MACHINE} $S/tools/fdt/make_dtbh.sh ${FDT_DTS_FILE} ${.CURDIR}'" \ dependency "fdt_dtb_file" \ no-obj no-implicit-rule before-depend \ clean "fdt_static_dtb.h" feeder_eq_gen.h optional sound \ dependency "$S/tools/sound/feeder_eq_mkfilter.awk" \ compile-with "${AWK} -f $S/tools/sound/feeder_eq_mkfilter.awk -- ${FEEDER_EQ_PRESETS} > feeder_eq_gen.h" \ no-obj no-implicit-rule before-depend \ clean "feeder_eq_gen.h" feeder_rate_gen.h optional sound \ dependency "$S/tools/sound/feeder_rate_mkfilter.awk" \ compile-with "${AWK} -f $S/tools/sound/feeder_rate_mkfilter.awk -- ${FEEDER_RATE_PRESETS} > feeder_rate_gen.h" \ no-obj no-implicit-rule before-depend \ clean "feeder_rate_gen.h" snd_fxdiv_gen.h optional sound \ dependency "$S/tools/sound/snd_fxdiv_gen.awk" \ compile-with "${AWK} -f $S/tools/sound/snd_fxdiv_gen.awk -- > snd_fxdiv_gen.h" \ no-obj no-implicit-rule before-depend \ clean "snd_fxdiv_gen.h" miidevs.h optional miibus | mii \ dependency "$S/tools/miidevs2h.awk $S/dev/mii/miidevs" \ compile-with "${AWK} -f $S/tools/miidevs2h.awk $S/dev/mii/miidevs" \ no-obj no-implicit-rule before-depend \ clean "miidevs.h" pccarddevs.h standard \ dependency "$S/tools/pccarddevs2h.awk $S/dev/pccard/pccarddevs" \ compile-with "${AWK} -f $S/tools/pccarddevs2h.awk $S/dev/pccard/pccarddevs" \ no-obj no-implicit-rule before-depend \ clean "pccarddevs.h" teken_state.h optional sc | vt \ dependency "$S/teken/gensequences $S/teken/sequences" \ compile-with "${AWK} -f $S/teken/gensequences $S/teken/sequences > teken_state.h" \ no-obj no-implicit-rule before-depend \ clean "teken_state.h" usbdevs.h optional usb \ dependency "$S/tools/usbdevs2h.awk $S/dev/usb/usbdevs" \ compile-with "${AWK} -f $S/tools/usbdevs2h.awk $S/dev/usb/usbdevs -h" \ no-obj no-implicit-rule before-depend \ clean "usbdevs.h" usbdevs_data.h optional usb \ dependency "$S/tools/usbdevs2h.awk $S/dev/usb/usbdevs" \ compile-with "${AWK} -f $S/tools/usbdevs2h.awk $S/dev/usb/usbdevs -d" \ no-obj no-implicit-rule before-depend \ clean "usbdevs_data.h" cam/cam.c optional scbus cam/cam_compat.c optional scbus cam/cam_periph.c optional scbus cam/cam_queue.c optional scbus cam/cam_sim.c optional scbus cam/cam_xpt.c optional scbus cam/ata/ata_all.c optional scbus cam/ata/ata_xpt.c optional scbus cam/ata/ata_pmp.c optional scbus cam/scsi/scsi_xpt.c optional scbus cam/scsi/scsi_all.c optional scbus cam/scsi/scsi_cd.c optional cd cam/scsi/scsi_ch.c optional ch cam/ata/ata_da.c optional ada | da cam/ctl/ctl.c optional ctl cam/ctl/ctl_backend.c optional ctl cam/ctl/ctl_backend_block.c optional ctl cam/ctl/ctl_backend_ramdisk.c optional ctl cam/ctl/ctl_cmd_table.c optional ctl cam/ctl/ctl_frontend.c optional ctl cam/ctl/ctl_frontend_cam_sim.c optional ctl cam/ctl/ctl_frontend_internal.c optional ctl cam/ctl/ctl_frontend_iscsi.c optional ctl cam/ctl/ctl_scsi_all.c optional ctl cam/ctl/ctl_tpc.c optional ctl cam/ctl/ctl_tpc_local.c optional ctl cam/ctl/ctl_error.c optional ctl cam/ctl/ctl_util.c optional ctl cam/ctl/scsi_ctl.c optional ctl cam/scsi/scsi_da.c optional da cam/scsi/scsi_low.c optional ct | ncv | nsp | stg cam/scsi/scsi_pass.c optional pass cam/scsi/scsi_pt.c optional pt cam/scsi/scsi_sa.c optional sa cam/scsi/scsi_enc.c optional ses cam/scsi/scsi_enc_ses.c optional ses cam/scsi/scsi_enc_safte.c optional ses cam/scsi/scsi_sg.c optional sg cam/scsi/scsi_targ_bh.c optional targbh cam/scsi/scsi_target.c optional targ cam/scsi/smp_all.c optional scbus # shared between zfs and dtrace cddl/compat/opensolaris/kern/opensolaris.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_cmn_err.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_kmem.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_misc.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_sunddi.c optional zfs compile-with "${ZFS_C}" # zfs specific cddl/compat/opensolaris/kern/opensolaris_acl.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_dtrace.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_kobj.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_kstat.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_lookup.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_policy.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_string.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_sysevent.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_taskq.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_uio.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_vfs.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_vm.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_zone.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/acl/acl_common.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/avl/avl.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/nvpair/fnvpair.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/nvpair/nvpair.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/nvpair/nvpair_alloc_fixed.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/unicode/u8_textprep.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zfeature_common.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zfs_comutil.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zfs_deleg.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zfs_fletcher.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zfs_ioctl_compat.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zfs_namecheck.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zfs_prop.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zpool_prop.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zprop_common.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/gfs.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/vnode.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/blkptr.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/bplist.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/bpobj.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/bptree.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dbuf.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/ddt.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/ddt_zap.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_diff.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_object.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_objset.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_send.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_traverse.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_tx.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_zfetch.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dnode.c optional zfs compile-with "${ZFS_C}" \ warning "kernel contains CDDL licensed ZFS filesystem" cddl/contrib/opensolaris/uts/common/fs/zfs/dnode_sync.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_bookmark.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_dataset.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_deadlist.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_deleg.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_destroy.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_dir.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_pool.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_prop.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_scan.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_userhold.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_synctask.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/gzip.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lz4.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lzjb.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/metaslab.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/range_tree.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/refcount.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/rrwlock.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/sa.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/sha256.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/spa.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/spa_config.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/spa_errlog.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/spa_history.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/spa_misc.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/space_map.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/space_reftree.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/trim_map.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/txg.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/uberblock.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/unique.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_cache.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_file.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_geom.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_label.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_mirror.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_missing.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_queue.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_raidz.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_root.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zap.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zap_leaf.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zap_micro.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfeature.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_acl.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_byteswap.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ctldir.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_debug.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_dir.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_fm.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_fuid.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_log.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_onexit.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_replay.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_rlock.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_sa.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vfsops.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_znode.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zil.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zio.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zio_checksum.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zio_compress.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zio_inject.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zle.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zrlock.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zvol.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/os/callb.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/os/fm.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/os/list.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/os/nvpair_alloc_system.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/adler32.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/deflate.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/inffast.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/inflate.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/inftrees.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/opensolaris_crc32.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/trees.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/zmod.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/zmod_subr.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/zutil.c optional zfs compile-with "${ZFS_C}" compat/freebsd32/freebsd32_capability.c optional compat_freebsd32 compat/freebsd32/freebsd32_ioctl.c optional compat_freebsd32 compat/freebsd32/freebsd32_misc.c optional compat_freebsd32 compat/freebsd32/freebsd32_syscalls.c optional compat_freebsd32 compat/freebsd32/freebsd32_sysent.c optional compat_freebsd32 contrib/dev/acpica/common/ahids.c optional acpi acpi_debug contrib/dev/acpica/common/ahuuids.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbcmds.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbconvert.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbdisply.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbexec.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbfileio.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbhistry.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbinput.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbmethod.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbnames.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbstats.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbtest.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbutils.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbxface.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmbuffer.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmcstyle.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmdeferred.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmnames.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmopcode.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmobject.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmresrc.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmresrcl.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmresrcl2.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmresrcs.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmutils.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmwalk.c optional acpi acpi_debug contrib/dev/acpica/components/dispatcher/dsargs.c optional acpi contrib/dev/acpica/components/dispatcher/dscontrol.c optional acpi contrib/dev/acpica/components/dispatcher/dsfield.c optional acpi contrib/dev/acpica/components/dispatcher/dsinit.c optional acpi contrib/dev/acpica/components/dispatcher/dsmethod.c optional acpi contrib/dev/acpica/components/dispatcher/dsmthdat.c optional acpi contrib/dev/acpica/components/dispatcher/dsobject.c optional acpi contrib/dev/acpica/components/dispatcher/dsopcode.c optional acpi contrib/dev/acpica/components/dispatcher/dsutils.c optional acpi contrib/dev/acpica/components/dispatcher/dswexec.c optional acpi contrib/dev/acpica/components/dispatcher/dswload.c optional acpi contrib/dev/acpica/components/dispatcher/dswload2.c optional acpi contrib/dev/acpica/components/dispatcher/dswscope.c optional acpi contrib/dev/acpica/components/dispatcher/dswstate.c optional acpi contrib/dev/acpica/components/events/evevent.c optional acpi contrib/dev/acpica/components/events/evglock.c optional acpi contrib/dev/acpica/components/events/evgpe.c optional acpi contrib/dev/acpica/components/events/evgpeblk.c optional acpi contrib/dev/acpica/components/events/evgpeinit.c optional acpi contrib/dev/acpica/components/events/evgpeutil.c optional acpi contrib/dev/acpica/components/events/evhandler.c optional acpi contrib/dev/acpica/components/events/evmisc.c optional acpi contrib/dev/acpica/components/events/evregion.c optional acpi contrib/dev/acpica/components/events/evrgnini.c optional acpi contrib/dev/acpica/components/events/evsci.c optional acpi contrib/dev/acpica/components/events/evxface.c optional acpi contrib/dev/acpica/components/events/evxfevnt.c optional acpi contrib/dev/acpica/components/events/evxfgpe.c optional acpi contrib/dev/acpica/components/events/evxfregn.c optional acpi contrib/dev/acpica/components/executer/exconfig.c optional acpi contrib/dev/acpica/components/executer/exconvrt.c optional acpi contrib/dev/acpica/components/executer/excreate.c optional acpi contrib/dev/acpica/components/executer/exdebug.c optional acpi contrib/dev/acpica/components/executer/exdump.c optional acpi contrib/dev/acpica/components/executer/exfield.c optional acpi contrib/dev/acpica/components/executer/exfldio.c optional acpi contrib/dev/acpica/components/executer/exmisc.c optional acpi contrib/dev/acpica/components/executer/exmutex.c optional acpi contrib/dev/acpica/components/executer/exnames.c optional acpi contrib/dev/acpica/components/executer/exoparg1.c optional acpi contrib/dev/acpica/components/executer/exoparg2.c optional acpi contrib/dev/acpica/components/executer/exoparg3.c optional acpi contrib/dev/acpica/components/executer/exoparg6.c optional acpi contrib/dev/acpica/components/executer/exprep.c optional acpi contrib/dev/acpica/components/executer/exregion.c optional acpi contrib/dev/acpica/components/executer/exresnte.c optional acpi contrib/dev/acpica/components/executer/exresolv.c optional acpi contrib/dev/acpica/components/executer/exresop.c optional acpi contrib/dev/acpica/components/executer/exstore.c optional acpi contrib/dev/acpica/components/executer/exstoren.c optional acpi contrib/dev/acpica/components/executer/exstorob.c optional acpi contrib/dev/acpica/components/executer/exsystem.c optional acpi contrib/dev/acpica/components/executer/exutils.c optional acpi contrib/dev/acpica/components/hardware/hwacpi.c optional acpi contrib/dev/acpica/components/hardware/hwesleep.c optional acpi contrib/dev/acpica/components/hardware/hwgpe.c optional acpi contrib/dev/acpica/components/hardware/hwpci.c optional acpi contrib/dev/acpica/components/hardware/hwregs.c optional acpi contrib/dev/acpica/components/hardware/hwsleep.c optional acpi contrib/dev/acpica/components/hardware/hwtimer.c optional acpi contrib/dev/acpica/components/hardware/hwvalid.c optional acpi contrib/dev/acpica/components/hardware/hwxface.c optional acpi contrib/dev/acpica/components/hardware/hwxfsleep.c optional acpi contrib/dev/acpica/components/namespace/nsaccess.c optional acpi contrib/dev/acpica/components/namespace/nsalloc.c optional acpi contrib/dev/acpica/components/namespace/nsarguments.c optional acpi contrib/dev/acpica/components/namespace/nsconvert.c optional acpi contrib/dev/acpica/components/namespace/nsdump.c optional acpi contrib/dev/acpica/components/namespace/nseval.c optional acpi contrib/dev/acpica/components/namespace/nsinit.c optional acpi contrib/dev/acpica/components/namespace/nsload.c optional acpi contrib/dev/acpica/components/namespace/nsnames.c optional acpi contrib/dev/acpica/components/namespace/nsobject.c optional acpi contrib/dev/acpica/components/namespace/nsparse.c optional acpi contrib/dev/acpica/components/namespace/nspredef.c optional acpi contrib/dev/acpica/components/namespace/nsprepkg.c optional acpi contrib/dev/acpica/components/namespace/nsrepair.c optional acpi contrib/dev/acpica/components/namespace/nsrepair2.c optional acpi contrib/dev/acpica/components/namespace/nssearch.c optional acpi contrib/dev/acpica/components/namespace/nsutils.c optional acpi contrib/dev/acpica/components/namespace/nswalk.c optional acpi contrib/dev/acpica/components/namespace/nsxfeval.c optional acpi contrib/dev/acpica/components/namespace/nsxfname.c optional acpi contrib/dev/acpica/components/namespace/nsxfobj.c optional acpi contrib/dev/acpica/components/parser/psargs.c optional acpi contrib/dev/acpica/components/parser/psloop.c optional acpi contrib/dev/acpica/components/parser/psobject.c optional acpi contrib/dev/acpica/components/parser/psopcode.c optional acpi contrib/dev/acpica/components/parser/psopinfo.c optional acpi contrib/dev/acpica/components/parser/psparse.c optional acpi contrib/dev/acpica/components/parser/psscope.c optional acpi contrib/dev/acpica/components/parser/pstree.c optional acpi contrib/dev/acpica/components/parser/psutils.c optional acpi contrib/dev/acpica/components/parser/pswalk.c optional acpi contrib/dev/acpica/components/parser/psxface.c optional acpi contrib/dev/acpica/components/resources/rsaddr.c optional acpi contrib/dev/acpica/components/resources/rscalc.c optional acpi contrib/dev/acpica/components/resources/rscreate.c optional acpi contrib/dev/acpica/components/resources/rsdump.c optional acpi contrib/dev/acpica/components/resources/rsdumpinfo.c optional acpi contrib/dev/acpica/components/resources/rsinfo.c optional acpi contrib/dev/acpica/components/resources/rsio.c optional acpi contrib/dev/acpica/components/resources/rsirq.c optional acpi contrib/dev/acpica/components/resources/rslist.c optional acpi contrib/dev/acpica/components/resources/rsmemory.c optional acpi contrib/dev/acpica/components/resources/rsmisc.c optional acpi contrib/dev/acpica/components/resources/rsserial.c optional acpi contrib/dev/acpica/components/resources/rsutils.c optional acpi contrib/dev/acpica/components/resources/rsxface.c optional acpi contrib/dev/acpica/components/tables/tbdata.c optional acpi contrib/dev/acpica/components/tables/tbfadt.c optional acpi contrib/dev/acpica/components/tables/tbfind.c optional acpi contrib/dev/acpica/components/tables/tbinstal.c optional acpi contrib/dev/acpica/components/tables/tbprint.c optional acpi contrib/dev/acpica/components/tables/tbutils.c optional acpi contrib/dev/acpica/components/tables/tbxface.c optional acpi contrib/dev/acpica/components/tables/tbxfload.c optional acpi contrib/dev/acpica/components/tables/tbxfroot.c optional acpi contrib/dev/acpica/components/utilities/utaddress.c optional acpi contrib/dev/acpica/components/utilities/utalloc.c optional acpi contrib/dev/acpica/components/utilities/utbuffer.c optional acpi contrib/dev/acpica/components/utilities/utcache.c optional acpi contrib/dev/acpica/components/utilities/utcopy.c optional acpi contrib/dev/acpica/components/utilities/utdebug.c optional acpi contrib/dev/acpica/components/utilities/utdecode.c optional acpi contrib/dev/acpica/components/utilities/utdelete.c optional acpi contrib/dev/acpica/components/utilities/uterror.c optional acpi contrib/dev/acpica/components/utilities/uteval.c optional acpi contrib/dev/acpica/components/utilities/utexcep.c optional acpi contrib/dev/acpica/components/utilities/utglobal.c optional acpi contrib/dev/acpica/components/utilities/uthex.c optional acpi contrib/dev/acpica/components/utilities/utids.c optional acpi contrib/dev/acpica/components/utilities/utinit.c optional acpi contrib/dev/acpica/components/utilities/utlock.c optional acpi contrib/dev/acpica/components/utilities/utmath.c optional acpi contrib/dev/acpica/components/utilities/utmisc.c optional acpi contrib/dev/acpica/components/utilities/utmutex.c optional acpi contrib/dev/acpica/components/utilities/utobject.c optional acpi contrib/dev/acpica/components/utilities/utosi.c optional acpi contrib/dev/acpica/components/utilities/utownerid.c optional acpi contrib/dev/acpica/components/utilities/utpredef.c optional acpi contrib/dev/acpica/components/utilities/utresrc.c optional acpi contrib/dev/acpica/components/utilities/utstate.c optional acpi contrib/dev/acpica/components/utilities/utstring.c optional acpi contrib/dev/acpica/components/utilities/utuuid.c optional acpi acpi_debug contrib/dev/acpica/components/utilities/utxface.c optional acpi contrib/dev/acpica/components/utilities/utxferror.c optional acpi contrib/dev/acpica/components/utilities/utxfinit.c optional acpi #contrib/dev/acpica/components/utilities/utxfmutex.c optional acpi contrib/ipfilter/netinet/fil.c optional ipfilter inet \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_auth.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_fil_freebsd.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_frag.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_log.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_nat.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_proxy.c optional ipfilter inet \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_state.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_lookup.c optional ipfilter inet \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN} -Wno-unused -Wno-error -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_pool.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_htable.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_sync.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/mlfk_ipl.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_nat6.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_rules.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_scan.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_dstlist.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/radix_ipf.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/libfdt/fdt.c optional fdt contrib/libfdt/fdt_ro.c optional fdt contrib/libfdt/fdt_rw.c optional fdt contrib/libfdt/fdt_strerror.c optional fdt contrib/libfdt/fdt_sw.c optional fdt contrib/libfdt/fdt_wip.c optional fdt contrib/ngatm/netnatm/api/cc_conn.c optional ngatm_ccatm \ compile-with "${NORMAL_C_NOWERROR} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/cc_data.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/cc_dump.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/cc_port.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/cc_sig.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/cc_user.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/unisap.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/misc/straddr.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/misc/unimsg_common.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/msg/traffic.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/msg/uni_ie.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/msg/uni_msg.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/saal/saal_sscfu.c optional ngatm_sscfu \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/saal/saal_sscop.c optional ngatm_sscop \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_call.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_coord.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_party.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_print.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_reset.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_uni.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_unimsgcpy.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_verify.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" crypto/blowfish/bf_ecb.c optional ipsec crypto/blowfish/bf_skey.c optional crypto | ipsec crypto/camellia/camellia.c optional crypto | ipsec crypto/camellia/camellia-api.c optional crypto | ipsec crypto/des/des_ecb.c optional crypto | ipsec | netsmb crypto/des/des_setkey.c optional crypto | ipsec | netsmb crypto/rc4/rc4.c optional netgraph_mppc_encryption | kgssapi crypto/rijndael/rijndael-alg-fst.c optional crypto | geom_bde | \ ipsec | random | wlan_ccmp crypto/rijndael/rijndael-api-fst.c optional geom_bde | random crypto/rijndael/rijndael-api.c optional crypto | ipsec | wlan_ccmp crypto/sha1.c optional carp | crypto | ipsec | \ netgraph_mppc_encryption | sctp crypto/sha2/sha2.c optional crypto | geom_bde | ipsec | random | \ sctp | zfs crypto/sha2/sha256c.c optional crypto | geom_bde | ipsec | random | \ sctp | zfs crypto/siphash/siphash.c optional inet | inet6 crypto/siphash/siphash_test.c optional inet | inet6 ddb/db_access.c optional ddb ddb/db_break.c optional ddb ddb/db_capture.c optional ddb ddb/db_command.c optional ddb ddb/db_examine.c optional ddb ddb/db_expr.c optional ddb ddb/db_input.c optional ddb ddb/db_lex.c optional ddb ddb/db_main.c optional ddb ddb/db_output.c optional ddb ddb/db_print.c optional ddb ddb/db_ps.c optional ddb ddb/db_run.c optional ddb ddb/db_script.c optional ddb ddb/db_sym.c optional ddb ddb/db_thread.c optional ddb ddb/db_textdump.c optional ddb ddb/db_variables.c optional ddb ddb/db_watch.c optional ddb ddb/db_write_cmd.c optional ddb dev/aac/aac.c optional aac dev/aac/aac_cam.c optional aacp aac dev/aac/aac_debug.c optional aac dev/aac/aac_disk.c optional aac dev/aac/aac_linux.c optional aac compat_linux dev/aac/aac_pci.c optional aac pci dev/aacraid/aacraid.c optional aacraid dev/aacraid/aacraid_cam.c optional aacraid scbus dev/aacraid/aacraid_debug.c optional aacraid dev/aacraid/aacraid_linux.c optional aacraid compat_linux dev/aacraid/aacraid_pci.c optional aacraid pci dev/acpi_support/acpi_wmi.c optional acpi_wmi acpi dev/acpi_support/acpi_asus.c optional acpi_asus acpi dev/acpi_support/acpi_asus_wmi.c optional acpi_asus_wmi acpi dev/acpi_support/acpi_fujitsu.c optional acpi_fujitsu acpi dev/acpi_support/acpi_hp.c optional acpi_hp acpi dev/acpi_support/acpi_ibm.c optional acpi_ibm acpi dev/acpi_support/acpi_panasonic.c optional acpi_panasonic acpi dev/acpi_support/acpi_sony.c optional acpi_sony acpi dev/acpi_support/acpi_toshiba.c optional acpi_toshiba acpi dev/acpi_support/atk0110.c optional aibs acpi dev/acpica/Osd/OsdDebug.c optional acpi dev/acpica/Osd/OsdHardware.c optional acpi dev/acpica/Osd/OsdInterrupt.c optional acpi dev/acpica/Osd/OsdMemory.c optional acpi dev/acpica/Osd/OsdSchedule.c optional acpi dev/acpica/Osd/OsdStream.c optional acpi dev/acpica/Osd/OsdSynch.c optional acpi dev/acpica/Osd/OsdTable.c optional acpi dev/acpica/acpi.c optional acpi dev/acpica/acpi_acad.c optional acpi dev/acpica/acpi_battery.c optional acpi dev/acpica/acpi_button.c optional acpi dev/acpica/acpi_cmbat.c optional acpi dev/acpica/acpi_cpu.c optional acpi dev/acpica/acpi_ec.c optional acpi dev/acpica/acpi_isab.c optional acpi isa dev/acpica/acpi_lid.c optional acpi dev/acpica/acpi_package.c optional acpi dev/acpica/acpi_pci.c optional acpi pci dev/acpica/acpi_pci_link.c optional acpi pci dev/acpica/acpi_pcib.c optional acpi pci dev/acpica/acpi_pcib_acpi.c optional acpi pci dev/acpica/acpi_pcib_pci.c optional acpi pci dev/acpica/acpi_perf.c optional acpi dev/acpica/acpi_powerres.c optional acpi dev/acpica/acpi_quirk.c optional acpi dev/acpica/acpi_resource.c optional acpi dev/acpica/acpi_smbat.c optional acpi dev/acpica/acpi_thermal.c optional acpi dev/acpica/acpi_throttle.c optional acpi dev/acpica/acpi_timer.c optional acpi dev/acpica/acpi_video.c optional acpi_video acpi dev/acpica/acpi_dock.c optional acpi_dock acpi dev/adlink/adlink.c optional adlink dev/advansys/adv_eisa.c optional adv eisa dev/advansys/adv_pci.c optional adv pci dev/advansys/advansys.c optional adv dev/advansys/advlib.c optional adv dev/advansys/advmcode.c optional adv dev/advansys/adw_pci.c optional adw pci dev/advansys/adwcam.c optional adw dev/advansys/adwlib.c optional adw dev/advansys/adwmcode.c optional adw dev/ae/if_ae.c optional ae pci dev/age/if_age.c optional age pci dev/agp/agp.c optional agp pci dev/agp/agp_if.m optional agp pci dev/aha/aha.c optional aha dev/aha/aha_isa.c optional aha isa dev/aha/aha_mca.c optional aha mca dev/ahb/ahb.c optional ahb eisa dev/ahci/ahci.c optional ahci dev/ahci/ahciem.c optional ahci dev/ahci/ahci_pci.c optional ahci pci dev/aic/aic.c optional aic dev/aic/aic_pccard.c optional aic pccard dev/aic7xxx/ahc_eisa.c optional ahc eisa dev/aic7xxx/ahc_isa.c optional ahc isa dev/aic7xxx/ahc_pci.c optional ahc pci \ compile-with "${NORMAL_C} ${NO_WCONSTANT_CONVERSION}" dev/aic7xxx/ahd_pci.c optional ahd pci \ compile-with "${NORMAL_C} ${NO_WCONSTANT_CONVERSION}" dev/aic7xxx/aic7770.c optional ahc dev/aic7xxx/aic79xx.c optional ahd pci dev/aic7xxx/aic79xx_osm.c optional ahd pci dev/aic7xxx/aic79xx_pci.c optional ahd pci dev/aic7xxx/aic79xx_reg_print.c optional ahd pci ahd_reg_pretty_print dev/aic7xxx/aic7xxx.c optional ahc dev/aic7xxx/aic7xxx_93cx6.c optional ahc dev/aic7xxx/aic7xxx_osm.c optional ahc dev/aic7xxx/aic7xxx_pci.c optional ahc pci dev/aic7xxx/aic7xxx_reg_print.c optional ahc ahc_reg_pretty_print dev/alc/if_alc.c optional alc pci dev/ale/if_ale.c optional ale pci dev/alpm/alpm.c optional alpm pci dev/altera/avgen/altera_avgen.c optional altera_avgen dev/altera/avgen/altera_avgen_fdt.c optional altera_avgen fdt dev/altera/avgen/altera_avgen_nexus.c optional altera_avgen dev/altera/sdcard/altera_sdcard.c optional altera_sdcard dev/altera/sdcard/altera_sdcard_disk.c optional altera_sdcard dev/altera/sdcard/altera_sdcard_io.c optional altera_sdcard dev/altera/sdcard/altera_sdcard_fdt.c optional altera_sdcard fdt dev/altera/sdcard/altera_sdcard_nexus.c optional altera_sdcard dev/altera/pio/pio.c optional altera_pio dev/altera/pio/pio_if.m optional altera_pio dev/amdpm/amdpm.c optional amdpm pci | nfpm pci dev/amdsmb/amdsmb.c optional amdsmb pci dev/amr/amr.c optional amr dev/amr/amr_cam.c optional amrp amr dev/amr/amr_disk.c optional amr dev/amr/amr_linux.c optional amr compat_linux dev/amr/amr_pci.c optional amr pci dev/an/if_an.c optional an dev/an/if_an_isa.c optional an isa dev/an/if_an_pccard.c optional an pccard dev/an/if_an_pci.c optional an pci # dev/ata/ata_if.m optional ata | atacore dev/ata/ata-all.c optional ata | atacore dev/ata/ata-dma.c optional ata | atacore dev/ata/ata-lowlevel.c optional ata | atacore dev/ata/ata-sata.c optional ata | atacore dev/ata/ata-card.c optional ata pccard | atapccard dev/ata/ata-cbus.c optional ata pc98 | atapc98 dev/ata/ata-isa.c optional ata isa | ataisa dev/ata/ata-pci.c optional ata pci | atapci dev/ata/chipsets/ata-acard.c optional ata pci | ataacard dev/ata/chipsets/ata-acerlabs.c optional ata pci | ataacerlabs dev/ata/chipsets/ata-amd.c optional ata pci | ataamd dev/ata/chipsets/ata-ati.c optional ata pci | ataati dev/ata/chipsets/ata-cenatek.c optional ata pci | atacenatek dev/ata/chipsets/ata-cypress.c optional ata pci | atacypress dev/ata/chipsets/ata-cyrix.c optional ata pci | atacyrix dev/ata/chipsets/ata-highpoint.c optional ata pci | atahighpoint dev/ata/chipsets/ata-intel.c optional ata pci | ataintel dev/ata/chipsets/ata-ite.c optional ata pci | ataite dev/ata/chipsets/ata-jmicron.c optional ata pci | atajmicron dev/ata/chipsets/ata-marvell.c optional ata pci | atamarvell dev/ata/chipsets/ata-micron.c optional ata pci | atamicron dev/ata/chipsets/ata-national.c optional ata pci | atanational dev/ata/chipsets/ata-netcell.c optional ata pci | atanetcell dev/ata/chipsets/ata-nvidia.c optional ata pci | atanvidia dev/ata/chipsets/ata-promise.c optional ata pci | atapromise dev/ata/chipsets/ata-serverworks.c optional ata pci | ataserverworks dev/ata/chipsets/ata-siliconimage.c optional ata pci | atasiliconimage | ataati dev/ata/chipsets/ata-sis.c optional ata pci | atasis dev/ata/chipsets/ata-via.c optional ata pci | atavia # dev/ath/if_ath_pci.c optional ath_pci pci \ compile-with "${NORMAL_C} -I$S/dev/ath" # dev/ath/if_ath_ahb.c optional ath_ahb \ compile-with "${NORMAL_C} -I$S/dev/ath" # dev/ath/if_ath.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_alq.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_beacon.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_btcoex.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_debug.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_keycache.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_led.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_lna_div.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_tx.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_tx_edma.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_tx_ht.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_tdma.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_sysctl.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_rx.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_rx_edma.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_spectral.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ah_osdep.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" # dev/ath/ath_hal/ah.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_eeprom_v1.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_eeprom_v3.c optional ath_hal | ath_ar5211 | ath_ar5212 \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_eeprom_v14.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_eeprom_v4k.c \ optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_eeprom_9287.c \ optional ath_hal | ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_regdomain.c optional ath \ compile-with "${NORMAL_C} ${NO_WSHIFT_COUNT_NEGATIVE} ${NO_WSHIFT_COUNT_OVERFLOW} -I$S/dev/ath" # ar5210 dev/ath/ath_hal/ar5210/ar5210_attach.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_beacon.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_interrupts.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_keycache.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_misc.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_phy.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_power.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_recv.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_reset.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_xmit.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar5211 dev/ath/ath_hal/ar5211/ar5211_attach.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_beacon.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_interrupts.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_keycache.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_misc.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_phy.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_power.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_recv.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_reset.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_xmit.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar5212 dev/ath/ath_hal/ar5212/ar5212_ani.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_attach.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_beacon.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_eeprom.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_gpio.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_interrupts.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_keycache.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_misc.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_phy.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_power.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_recv.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_reset.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_rfgain.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_xmit.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar5416 (depends on ar5212) dev/ath/ath_hal/ar5416/ar5416_ani.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_attach.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_beacon.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_btcoex.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_cal.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_cal_iq.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_eeprom.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_gpio.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_interrupts.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_keycache.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_misc.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_phy.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_power.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_radar.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_recv.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_reset.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_spectral.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_xmit.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar9130 (depends upon ar5416) - also requires AH_SUPPORT_AR9130 # # Since this is an embedded MAC SoC, there's no need to compile it into the # default HAL. dev/ath/ath_hal/ar9001/ar9130_attach.c optional ath_ar9130 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9001/ar9130_phy.c optional ath_ar9130 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9001/ar9130_eeprom.c optional ath_ar9130 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar9160 (depends on ar5416) dev/ath/ath_hal/ar9001/ar9160_attach.c optional ath_hal | ath_ar9160 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar9280 (depends on ar5416) dev/ath/ath_hal/ar9002/ar9280_attach.c optional ath_hal | ath_ar9280 | \ ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9280_olc.c optional ath_hal | ath_ar9280 | \ ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar9285 (depends on ar5416 and ar9280) dev/ath/ath_hal/ar9002/ar9285_attach.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9285_btcoex.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9285_reset.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9285_cal.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9285_phy.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9285_diversity.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar9287 (depends on ar5416) dev/ath/ath_hal/ar9002/ar9287_attach.c optional ath_hal | ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9287_reset.c optional ath_hal | ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9287_cal.c optional ath_hal | ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9287_olc.c optional ath_hal | ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar9300 contrib/dev/ath/ath_hal/ar9300/ar9300_ani.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_attach.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_beacon.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_eeprom.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal ${NO_WCONSTANT_CONVERSION}" contrib/dev/ath/ath_hal/ar9300/ar9300_freebsd.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_gpio.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_interrupts.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_keycache.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_mci.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_misc.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_paprd.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_phy.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_power.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_radar.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_radio.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_recv.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_recv_ds.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_reset.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal ${NO_WSOMETIMES_UNINITIALIZED} -Wno-unused-function" contrib/dev/ath/ath_hal/ar9300/ar9300_stub.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_stub_funcs.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_timer.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_xmit.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_xmit_ds.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" # rf backends dev/ath/ath_hal/ar5212/ar2316.c optional ath_rf2316 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar2317.c optional ath_rf2317 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar2413.c optional ath_hal | ath_rf2413 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar2425.c optional ath_hal | ath_rf2425 | ath_rf2417 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5111.c optional ath_hal | ath_rf5111 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5112.c optional ath_hal | ath_rf5112 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5413.c optional ath_hal | ath_rf5413 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar2133.c optional ath_hal | ath_ar5416 | \ ath_ar9130 | ath_ar9160 | ath_ar9280 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9280.c optional ath_hal | ath_ar9280 | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9285.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9287.c optional ath_hal | ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ath rate control algorithms dev/ath/ath_rate/amrr/amrr.c optional ath_rate_amrr \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_rate/onoe/onoe.c optional ath_rate_onoe \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_rate/sample/sample.c optional ath_rate_sample \ compile-with "${NORMAL_C} -I$S/dev/ath" # ath DFS modules dev/ath/ath_dfs/null/dfs_null.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" # dev/bce/if_bce.c optional bce dev/bfe/if_bfe.c optional bfe dev/bge/if_bge.c optional bge dev/bktr/bktr_audio.c optional bktr pci dev/bktr/bktr_card.c optional bktr pci dev/bktr/bktr_core.c optional bktr pci dev/bktr/bktr_i2c.c optional bktr pci smbus dev/bktr/bktr_os.c optional bktr pci dev/bktr/bktr_tuner.c optional bktr pci dev/bktr/msp34xx.c optional bktr pci dev/buslogic/bt.c optional bt dev/buslogic/bt_eisa.c optional bt eisa dev/buslogic/bt_isa.c optional bt isa dev/buslogic/bt_mca.c optional bt mca dev/buslogic/bt_pci.c optional bt pci dev/bwi/bwimac.c optional bwi dev/bwi/bwiphy.c optional bwi dev/bwi/bwirf.c optional bwi dev/bwi/if_bwi.c optional bwi dev/bwi/if_bwi_pci.c optional bwi pci # XXX Work around clang warning, until maintainer approves fix. dev/bwn/if_bwn.c optional bwn siba_bwn \ compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}" dev/cardbus/cardbus.c optional cardbus dev/cardbus/cardbus_cis.c optional cardbus dev/cardbus/cardbus_device.c optional cardbus dev/cas/if_cas.c optional cas dev/cfi/cfi_bus_fdt.c optional cfi fdt dev/cfi/cfi_bus_nexus.c optional cfi dev/cfi/cfi_core.c optional cfi dev/cfi/cfi_dev.c optional cfi dev/cfi/cfi_disk.c optional cfid dev/ciss/ciss.c optional ciss dev/cm/smc90cx6.c optional cm dev/cmx/cmx.c optional cmx dev/cmx/cmx_pccard.c optional cmx pccard dev/cpufreq/ichss.c optional cpufreq dev/cs/if_cs.c optional cs dev/cs/if_cs_isa.c optional cs isa dev/cs/if_cs_pccard.c optional cs pccard dev/cxgb/cxgb_main.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/cxgb_sge.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_mc5.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_vsc7323.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_vsc8211.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_ael1002.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_aq100x.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_mv88e1xxx.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_xgmac.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_t3_hw.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_tn1010.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/sys/uipc_mvec.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/cxgb_t3fw.c optional cxgb cxgb_t3fw \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgbe/t4_mp_ring.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/t4_main.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/t4_netmap.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/t4_sge.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/t4_l2t.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/t4_tracer.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/common/t4_hw.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" t4fw_cfg.c optional cxgbe \ compile-with "${AWK} -f $S/tools/fw_stub.awk t4fw_cfg.fw:t4fw_cfg t4fw_cfg_uwire.fw:t4fw_cfg_uwire t4fw.fw:t4fw -mt4fw_cfg -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "t4fw_cfg.c" t4fw_cfg.fwo optional cxgbe \ dependency "t4fw_cfg.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "t4fw_cfg.fwo" t4fw_cfg.fw optional cxgbe \ dependency "$S/dev/cxgbe/firmware/t4fw_cfg.txt" \ compile-with "${CP} ${.ALLSRC} ${.TARGET}" \ no-obj no-implicit-rule \ clean "t4fw_cfg.fw" t4fw_cfg_uwire.fwo optional cxgbe \ dependency "t4fw_cfg_uwire.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "t4fw_cfg_uwire.fwo" t4fw_cfg_uwire.fw optional cxgbe \ dependency "$S/dev/cxgbe/firmware/t4fw_cfg_uwire.txt" \ compile-with "${CP} ${.ALLSRC} ${.TARGET}" \ no-obj no-implicit-rule \ clean "t4fw_cfg_uwire.fw" t4fw.fwo optional cxgbe \ dependency "t4fw.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "t4fw.fwo" t4fw.fw optional cxgbe \ dependency "$S/dev/cxgbe/firmware/t4fw-1.11.27.0.bin.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "t4fw.fw" t5fw_cfg.c optional cxgbe \ compile-with "${AWK} -f $S/tools/fw_stub.awk t5fw_cfg.fw:t5fw_cfg t5fw.fw:t5fw -mt5fw_cfg -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "t5fw_cfg.c" t5fw_cfg.fwo optional cxgbe \ dependency "t5fw_cfg.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "t5fw_cfg.fwo" t5fw_cfg.fw optional cxgbe \ dependency "$S/dev/cxgbe/firmware/t5fw_cfg.txt" \ compile-with "${CP} ${.ALLSRC} ${.TARGET}" \ no-obj no-implicit-rule \ clean "t5fw_cfg.fw" t5fw.fwo optional cxgbe \ dependency "t5fw.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "t5fw.fwo" t5fw.fw optional cxgbe \ dependency "$S/dev/cxgbe/firmware/t5fw-1.11.27.0.bin.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "t5fw.fw" dev/cy/cy.c optional cy dev/cy/cy_isa.c optional cy isa dev/cy/cy_pci.c optional cy pci dev/dc/if_dc.c optional dc pci dev/dc/dcphy.c optional dc pci dev/dc/pnphy.c optional dc pci dev/dcons/dcons.c optional dcons dev/dcons/dcons_crom.c optional dcons_crom dev/dcons/dcons_os.c optional dcons dev/de/if_de.c optional de pci dev/digi/CX.c optional digi_CX dev/digi/CX_PCI.c optional digi_CX_PCI dev/digi/EPCX.c optional digi_EPCX dev/digi/EPCX_PCI.c optional digi_EPCX_PCI dev/digi/Xe.c optional digi_Xe dev/digi/Xem.c optional digi_Xem dev/digi/Xr.c optional digi_Xr dev/digi/digi.c optional digi dev/digi/digi_isa.c optional digi isa dev/digi/digi_pci.c optional digi pci dev/dpt/dpt_eisa.c optional dpt eisa dev/dpt/dpt_pci.c optional dpt pci dev/dpt/dpt_scsi.c optional dpt dev/drm/ati_pcigart.c optional drm dev/drm/drm_agpsupport.c optional drm dev/drm/drm_auth.c optional drm dev/drm/drm_bufs.c optional drm dev/drm/drm_context.c optional drm dev/drm/drm_dma.c optional drm dev/drm/drm_drawable.c optional drm dev/drm/drm_drv.c optional drm dev/drm/drm_fops.c optional drm dev/drm/drm_hashtab.c optional drm dev/drm/drm_ioctl.c optional drm dev/drm/drm_irq.c optional drm dev/drm/drm_lock.c optional drm dev/drm/drm_memory.c optional drm dev/drm/drm_mm.c optional drm dev/drm/drm_pci.c optional drm dev/drm/drm_scatter.c optional drm dev/drm/drm_sman.c optional drm dev/drm/drm_sysctl.c optional drm dev/drm/drm_vm.c optional drm dev/drm/i915_dma.c optional i915drm dev/drm/i915_drv.c optional i915drm dev/drm/i915_irq.c optional i915drm dev/drm/i915_mem.c optional i915drm dev/drm/i915_suspend.c optional i915drm dev/drm/mach64_dma.c optional mach64drm dev/drm/mach64_drv.c optional mach64drm dev/drm/mach64_irq.c optional mach64drm dev/drm/mach64_state.c optional mach64drm dev/drm/mga_dma.c optional mgadrm dev/drm/mga_drv.c optional mgadrm dev/drm/mga_irq.c optional mgadrm dev/drm/mga_state.c optional mgadrm dev/drm/mga_warp.c optional mgadrm dev/drm/r128_cce.c optional r128drm \ compile-with "${NORMAL_C} ${NO_WCONSTANT_CONVERSION}" dev/drm/r128_drv.c optional r128drm dev/drm/r128_irq.c optional r128drm dev/drm/r128_state.c optional r128drm dev/drm/r300_cmdbuf.c optional radeondrm dev/drm/r600_blit.c optional radeondrm dev/drm/r600_cp.c optional radeondrm \ compile-with "${NORMAL_C} ${NO_WCONSTANT_CONVERSION}" dev/drm/radeon_cp.c optional radeondrm \ compile-with "${NORMAL_C} ${NO_WCONSTANT_CONVERSION}" dev/drm/radeon_cs.c optional radeondrm dev/drm/radeon_drv.c optional radeondrm dev/drm/radeon_irq.c optional radeondrm dev/drm/radeon_mem.c optional radeondrm dev/drm/radeon_state.c optional radeondrm dev/drm/savage_bci.c optional savagedrm dev/drm/savage_drv.c optional savagedrm dev/drm/savage_state.c optional savagedrm dev/drm/sis_drv.c optional sisdrm dev/drm/sis_ds.c optional sisdrm dev/drm/sis_mm.c optional sisdrm dev/drm/tdfx_drv.c optional tdfxdrm dev/drm/via_dma.c optional viadrm dev/drm/via_dmablit.c optional viadrm dev/drm/via_drv.c optional viadrm dev/drm/via_irq.c optional viadrm dev/drm/via_map.c optional viadrm dev/drm/via_mm.c optional viadrm dev/drm/via_verifier.c optional viadrm dev/drm/via_video.c optional viadrm dev/ed/if_ed.c optional ed dev/ed/if_ed_novell.c optional ed dev/ed/if_ed_rtl80x9.c optional ed dev/ed/if_ed_pccard.c optional ed pccard dev/ed/if_ed_pci.c optional ed pci dev/eisa/eisa_if.m standard dev/eisa/eisaconf.c optional eisa dev/e1000/if_em.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/if_lem.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/if_igb.c optional igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_80003es2lan.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82540.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82541.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82542.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82543.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82571.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82575.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_ich8lan.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_i210.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_api.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_mac.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_manage.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_nvm.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_phy.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_vf.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_mbx.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_osdep.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/et/if_et.c optional et dev/en/if_en_pci.c optional en pci dev/en/midway.c optional en dev/ep/if_ep.c optional ep dev/ep/if_ep_eisa.c optional ep eisa dev/ep/if_ep_isa.c optional ep isa dev/ep/if_ep_mca.c optional ep mca dev/ep/if_ep_pccard.c optional ep pccard dev/esp/esp_pci.c optional esp pci dev/esp/ncr53c9x.c optional esp dev/etherswitch/arswitch/arswitch.c optional arswitch dev/etherswitch/arswitch/arswitch_reg.c optional arswitch dev/etherswitch/arswitch/arswitch_phy.c optional arswitch dev/etherswitch/arswitch/arswitch_8216.c optional arswitch dev/etherswitch/arswitch/arswitch_8226.c optional arswitch dev/etherswitch/arswitch/arswitch_8316.c optional arswitch dev/etherswitch/arswitch/arswitch_8327.c optional arswitch dev/etherswitch/arswitch/arswitch_7240.c optional arswitch dev/etherswitch/arswitch/arswitch_9340.c optional arswitch dev/etherswitch/arswitch/arswitch_vlans.c optional arswitch dev/etherswitch/etherswitch.c optional etherswitch dev/etherswitch/etherswitch_if.m optional etherswitch dev/etherswitch/ip17x/ip17x.c optional ip17x dev/etherswitch/ip17x/ip175c.c optional ip17x dev/etherswitch/ip17x/ip175d.c optional ip17x dev/etherswitch/ip17x/ip17x_phy.c optional ip17x dev/etherswitch/ip17x/ip17x_vlans.c optional ip17x dev/etherswitch/mdio_if.m optional miiproxy dev/etherswitch/mdio.c optional miiproxy dev/etherswitch/miiproxy.c optional miiproxy dev/etherswitch/rtl8366/rtl8366rb.c optional rtl8366rb dev/etherswitch/ukswitch/ukswitch.c optional ukswitch dev/ex/if_ex.c optional ex dev/ex/if_ex_isa.c optional ex isa dev/ex/if_ex_pccard.c optional ex pccard dev/exca/exca.c optional cbb dev/fatm/if_fatm.c optional fatm pci dev/fb/fbd.c optional fbd | vt dev/fb/fb_if.m standard dev/fb/splash.c optional sc splash dev/fdt/fdt_clock.c optional fdt fdt_clock dev/fdt/fdt_clock_if.m optional fdt fdt_clock dev/fdt/fdt_common.c optional fdt dev/fdt/fdt_pinctrl.c optional fdt fdt_pinctrl dev/fdt/fdt_pinctrl_if.m optional fdt fdt_pinctrl dev/fdt/fdt_slicer.c optional fdt cfi | fdt nand dev/fdt/fdt_static_dtb.S optional fdt fdt_dtb_static \ dependency "$S/boot/fdt/dts/${MACHINE}/${FDT_DTS_FILE}" dev/fdt/simplebus.c optional fdt dev/fe/if_fe.c optional fe dev/fe/if_fe_pccard.c optional fe pccard dev/filemon/filemon.c optional filemon dev/firewire/firewire.c optional firewire dev/firewire/fwcrom.c optional firewire dev/firewire/fwdev.c optional firewire dev/firewire/fwdma.c optional firewire dev/firewire/fwmem.c optional firewire dev/firewire/fwohci.c optional firewire dev/firewire/fwohci_pci.c optional firewire pci dev/firewire/if_fwe.c optional fwe dev/firewire/if_fwip.c optional fwip dev/firewire/sbp.c optional sbp dev/firewire/sbp_targ.c optional sbp_targ dev/flash/at45d.c optional at45d dev/flash/mx25l.c optional mx25l dev/fxp/if_fxp.c optional fxp dev/fxp/inphy.c optional fxp dev/gem/if_gem.c optional gem dev/gem/if_gem_pci.c optional gem pci dev/gem/if_gem_sbus.c optional gem sbus dev/gpio/gpiobus.c optional gpio \ dependency "gpiobus_if.h" dev/gpio/gpioc.c optional gpio \ dependency "gpio_if.h" dev/gpio/gpioiic.c optional gpioiic dev/gpio/gpioled.c optional gpioled dev/gpio/gpio_if.m optional gpio dev/gpio/gpiobus_if.m optional gpio dev/gpio/ofw_gpiobus.c optional fdt gpio dev/hatm/if_hatm.c optional hatm pci dev/hatm/if_hatm_intr.c optional hatm pci dev/hatm/if_hatm_ioctl.c optional hatm pci dev/hatm/if_hatm_rx.c optional hatm pci dev/hatm/if_hatm_tx.c optional hatm pci dev/hifn/hifn7751.c optional hifn dev/hme/if_hme.c optional hme dev/hme/if_hme_pci.c optional hme pci dev/hme/if_hme_sbus.c optional hme sbus dev/hptiop/hptiop.c optional hptiop scbus dev/hwpmc/hwpmc_logging.c optional hwpmc dev/hwpmc/hwpmc_mod.c optional hwpmc dev/hwpmc/hwpmc_soft.c optional hwpmc dev/ichsmb/ichsmb.c optional ichsmb dev/ichsmb/ichsmb_pci.c optional ichsmb pci dev/ida/ida.c optional ida dev/ida/ida_disk.c optional ida dev/ida/ida_eisa.c optional ida eisa dev/ida/ida_pci.c optional ida pci dev/ie/if_ie.c optional ie isa nowerror dev/ie/if_ie_isa.c optional ie isa dev/iicbus/ad7418.c optional ad7418 dev/iicbus/ds1307.c optional ds1307 dev/iicbus/ds133x.c optional ds133x dev/iicbus/ds1374.c optional ds1374 dev/iicbus/ds1672.c optional ds1672 dev/iicbus/ds3231.c optional ds3231 dev/iicbus/icee.c optional icee dev/iicbus/if_ic.c optional ic dev/iicbus/iic.c optional iic dev/iicbus/iicbb.c optional iicbb dev/iicbus/iicbb_if.m optional iicbb dev/iicbus/iicbus.c optional iicbus dev/iicbus/iicbus_if.m optional iicbus dev/iicbus/iiconf.c optional iicbus dev/iicbus/iicsmb.c optional iicsmb \ dependency "iicbus_if.h" dev/iicbus/iicoc.c optional iicoc dev/iicbus/lm75.c optional lm75 dev/iicbus/pcf8563.c optional pcf8563 dev/iicbus/s35390a.c optional s35390a dev/iir/iir.c optional iir dev/iir/iir_ctrl.c optional iir dev/iir/iir_pci.c optional iir pci dev/intpm/intpm.c optional intpm pci # XXX Work around clang warning, until maintainer approves fix. dev/ips/ips.c optional ips \ compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}" dev/ips/ips_commands.c optional ips dev/ips/ips_disk.c optional ips dev/ips/ips_ioctl.c optional ips dev/ips/ips_pci.c optional ips pci dev/ipw/if_ipw.c optional ipw ipwbssfw.c optional ipwbssfw | ipwfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk ipw_bss.fw:ipw_bss:130 -lintel_ipw -mipw_bss -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "ipwbssfw.c" ipw_bss.fwo optional ipwbssfw | ipwfw \ dependency "ipw_bss.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "ipw_bss.fwo" ipw_bss.fw optional ipwbssfw | ipwfw \ dependency "$S/contrib/dev/ipw/ipw2100-1.3.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "ipw_bss.fw" ipwibssfw.c optional ipwibssfw | ipwfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk ipw_ibss.fw:ipw_ibss:130 -lintel_ipw -mipw_ibss -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "ipwibssfw.c" ipw_ibss.fwo optional ipwibssfw | ipwfw \ dependency "ipw_ibss.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "ipw_ibss.fwo" ipw_ibss.fw optional ipwibssfw | ipwfw \ dependency "$S/contrib/dev/ipw/ipw2100-1.3-i.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "ipw_ibss.fw" ipwmonitorfw.c optional ipwmonitorfw | ipwfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk ipw_monitor.fw:ipw_monitor:130 -lintel_ipw -mipw_monitor -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "ipwmonitorfw.c" ipw_monitor.fwo optional ipwmonitorfw | ipwfw \ dependency "ipw_monitor.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "ipw_monitor.fwo" ipw_monitor.fw optional ipwmonitorfw | ipwfw \ dependency "$S/contrib/dev/ipw/ipw2100-1.3-p.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "ipw_monitor.fw" dev/iscsi/icl.c optional iscsi | ctl dev/iscsi/icl_conn_if.m optional iscsi | ctl dev/iscsi/icl_proxy.c optional iscsi | ctl dev/iscsi/icl_soft.c optional iscsi | ctl dev/iscsi/iscsi.c optional iscsi scbus dev/iscsi_initiator/iscsi.c optional iscsi_initiator scbus dev/iscsi_initiator/iscsi_subr.c optional iscsi_initiator scbus dev/iscsi_initiator/isc_cam.c optional iscsi_initiator scbus dev/iscsi_initiator/isc_soc.c optional iscsi_initiator scbus dev/iscsi_initiator/isc_sm.c optional iscsi_initiator scbus dev/iscsi_initiator/isc_subr.c optional iscsi_initiator scbus dev/ismt/ismt.c optional ismt dev/isp/isp.c optional isp dev/isp/isp_freebsd.c optional isp dev/isp/isp_library.c optional isp dev/isp/isp_pci.c optional isp pci dev/isp/isp_sbus.c optional isp sbus dev/isp/isp_target.c optional isp dev/ispfw/ispfw.c optional ispfw dev/iwi/if_iwi.c optional iwi iwibssfw.c optional iwibssfw | iwifw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwi_bss.fw:iwi_bss:300 -lintel_iwi -miwi_bss -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwibssfw.c" iwi_bss.fwo optional iwibssfw | iwifw \ dependency "iwi_bss.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwi_bss.fwo" iwi_bss.fw optional iwibssfw | iwifw \ dependency "$S/contrib/dev/iwi/ipw2200-bss.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwi_bss.fw" iwiibssfw.c optional iwiibssfw | iwifw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwi_ibss.fw:iwi_ibss:300 -lintel_iwi -miwi_ibss -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwiibssfw.c" iwi_ibss.fwo optional iwiibssfw | iwifw \ dependency "iwi_ibss.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwi_ibss.fwo" iwi_ibss.fw optional iwiibssfw | iwifw \ dependency "$S/contrib/dev/iwi/ipw2200-ibss.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwi_ibss.fw" iwimonitorfw.c optional iwimonitorfw | iwifw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwi_monitor.fw:iwi_monitor:300 -lintel_iwi -miwi_monitor -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwimonitorfw.c" iwi_monitor.fwo optional iwimonitorfw | iwifw \ dependency "iwi_monitor.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwi_monitor.fwo" iwi_monitor.fw optional iwimonitorfw | iwifw \ dependency "$S/contrib/dev/iwi/ipw2200-sniffer.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwi_monitor.fw" dev/iwn/if_iwn.c optional iwn iwn1000fw.c optional iwn1000fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn1000.fw:iwn1000fw -miwn1000fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn1000fw.c" iwn1000fw.fwo optional iwn1000fw | iwnfw \ dependency "iwn1000.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn1000fw.fwo" iwn1000.fw optional iwn1000fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-1000-39.31.5.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn1000.fw" iwn100fw.c optional iwn100fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn100.fw:iwn100fw -miwn100fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn100fw.c" iwn100fw.fwo optional iwn100fw | iwnfw \ dependency "iwn100.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn100fw.fwo" iwn100.fw optional iwn100fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-100-39.31.5.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn100.fw" iwn105fw.c optional iwn105fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn105.fw:iwn105fw -miwn105fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn105fw.c" iwn105fw.fwo optional iwn105fw | iwnfw \ dependency "iwn105.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn105fw.fwo" iwn105.fw optional iwn105fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-105-6-18.168.6.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn105.fw" iwn135fw.c optional iwn135fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn135.fw:iwn135fw -miwn135fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn135fw.c" iwn135fw.fwo optional iwn135fw | iwnfw \ dependency "iwn135.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn135fw.fwo" iwn135.fw optional iwn135fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-135-6-18.168.6.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn135.fw" iwn2000fw.c optional iwn2000fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn2000.fw:iwn2000fw -miwn2000fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn2000fw.c" iwn2000fw.fwo optional iwn2000fw | iwnfw \ dependency "iwn2000.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn2000fw.fwo" iwn2000.fw optional iwn2000fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-2000-18.168.6.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn2000.fw" iwn2030fw.c optional iwn2030fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn2030.fw:iwn2030fw -miwn2030fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn2030fw.c" iwn2030fw.fwo optional iwn2030fw | iwnfw \ dependency "iwn2030.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn2030fw.fwo" iwn2030.fw optional iwn2030fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwnwifi-2030-18.168.6.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn2030.fw" iwn4965fw.c optional iwn4965fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn4965.fw:iwn4965fw -miwn4965fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn4965fw.c" iwn4965fw.fwo optional iwn4965fw | iwnfw \ dependency "iwn4965.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn4965fw.fwo" iwn4965.fw optional iwn4965fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-4965-228.61.2.24.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn4965.fw" iwn5000fw.c optional iwn5000fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn5000.fw:iwn5000fw -miwn5000fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn5000fw.c" iwn5000fw.fwo optional iwn5000fw | iwnfw \ dependency "iwn5000.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn5000fw.fwo" iwn5000.fw optional iwn5000fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-5000-8.83.5.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn5000.fw" iwn5150fw.c optional iwn5150fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn5150.fw:iwn5150fw -miwn5150fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn5150fw.c" iwn5150fw.fwo optional iwn5150fw | iwnfw \ dependency "iwn5150.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn5150fw.fwo" iwn5150.fw optional iwn5150fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-5150-8.24.2.2.fw.uu"\ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn5150.fw" iwn6000fw.c optional iwn6000fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn6000.fw:iwn6000fw -miwn6000fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn6000fw.c" iwn6000fw.fwo optional iwn6000fw | iwnfw \ dependency "iwn6000.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn6000fw.fwo" iwn6000.fw optional iwn6000fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-6000-9.221.4.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn6000.fw" iwn6000g2afw.c optional iwn6000g2afw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn6000g2a.fw:iwn6000g2afw -miwn6000g2afw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn6000g2afw.c" iwn6000g2afw.fwo optional iwn6000g2afw | iwnfw \ dependency "iwn6000g2a.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn6000g2afw.fwo" iwn6000g2a.fw optional iwn6000g2afw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-6000g2a-18.168.6.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn6000g2a.fw" iwn6000g2bfw.c optional iwn6000g2bfw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn6000g2b.fw:iwn6000g2bfw -miwn6000g2bfw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn6000g2bfw.c" iwn6000g2bfw.fwo optional iwn6000g2bfw | iwnfw \ dependency "iwn6000g2b.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn6000g2bfw.fwo" iwn6000g2b.fw optional iwn6000g2bfw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-6000g2b-18.168.6.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn6000g2b.fw" iwn6050fw.c optional iwn6050fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn6050.fw:iwn6050fw -miwn6050fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn6050fw.c" iwn6050fw.fwo optional iwn6050fw | iwnfw \ dependency "iwn6050.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn6050fw.fwo" iwn6050.fw optional iwn6050fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-6050-41.28.5.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn6050.fw" dev/ixgb/if_ixgb.c optional ixgb dev/ixgb/ixgb_ee.c optional ixgb dev/ixgb/ixgb_hw.c optional ixgb dev/ixgbe/if_ix.c optional ix inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe -DSMP" dev/ixgbe/if_ixv.c optional ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe -DSMP" dev/ixgbe/ix_txrx.c optional ix ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe -DSMP" dev/ixgbe/ixgbe_phy.c optional ix ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_api.c optional ix ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_common.c optional ix ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_mbx.c optional ix ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_vf.c optional ix ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_82598.c optional ix ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_82599.c optional ix ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_x540.c optional ix ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_x550.c optional ix ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_dcb.c optional ix ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_dcb_82598.c optional ix ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_dcb_82599.c optional ix ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/jme/if_jme.c optional jme pci dev/joy/joy.c optional joy dev/joy/joy_isa.c optional joy isa dev/kbdmux/kbdmux.c optional kbdmux dev/ksyms/ksyms.c optional ksyms dev/le/am7990.c optional le dev/le/am79900.c optional le dev/le/if_le_pci.c optional le pci dev/le/lance.c optional le dev/led/led.c standard dev/lge/if_lge.c optional lge dev/lmc/if_lmc.c optional lmc dev/malo/if_malo.c optional malo dev/malo/if_malohal.c optional malo dev/malo/if_malo_pci.c optional malo pci dev/mc146818/mc146818.c optional mc146818 dev/mca/mca_bus.c optional mca dev/mcd/mcd.c optional mcd isa nowerror dev/mcd/mcd_isa.c optional mcd isa nowerror dev/md/md.c optional md dev/mem/memdev.c optional mem dev/mem/memutil.c optional mem dev/mfi/mfi.c optional mfi dev/mfi/mfi_debug.c optional mfi dev/mfi/mfi_pci.c optional mfi pci dev/mfi/mfi_disk.c optional mfi dev/mfi/mfi_syspd.c optional mfi dev/mfi/mfi_tbolt.c optional mfi dev/mfi/mfi_linux.c optional mfi compat_linux dev/mfi/mfi_cam.c optional mfip scbus dev/mii/acphy.c optional miibus | acphy dev/mii/amphy.c optional miibus | amphy dev/mii/atphy.c optional miibus | atphy dev/mii/axphy.c optional miibus | axphy dev/mii/bmtphy.c optional miibus | bmtphy dev/mii/brgphy.c optional miibus | brgphy dev/mii/ciphy.c optional miibus | ciphy dev/mii/e1000phy.c optional miibus | e1000phy dev/mii/gentbi.c optional miibus | gentbi dev/mii/icsphy.c optional miibus | icsphy dev/mii/ip1000phy.c optional miibus | ip1000phy dev/mii/jmphy.c optional miibus | jmphy dev/mii/lxtphy.c optional miibus | lxtphy dev/mii/mii.c optional miibus | mii dev/mii/mii_bitbang.c optional miibus | mii_bitbang dev/mii/mii_physubr.c optional miibus | mii dev/mii/miibus_if.m optional miibus | mii dev/mii/mlphy.c optional miibus | mlphy dev/mii/nsgphy.c optional miibus | nsgphy dev/mii/nsphy.c optional miibus | nsphy dev/mii/nsphyter.c optional miibus | nsphyter dev/mii/pnaphy.c optional miibus | pnaphy dev/mii/qsphy.c optional miibus | qsphy dev/mii/rdcphy.c optional miibus | rdcphy dev/mii/rgephy.c optional miibus | rgephy dev/mii/rlphy.c optional miibus | rlphy dev/mii/rlswitch.c optional rlswitch dev/mii/smcphy.c optional miibus | smcphy dev/mii/smscphy.c optional miibus | smscphy dev/mii/tdkphy.c optional miibus | tdkphy dev/mii/tlphy.c optional miibus | tlphy dev/mii/truephy.c optional miibus | truephy dev/mii/ukphy.c optional miibus | mii dev/mii/ukphy_subr.c optional miibus | mii dev/mii/xmphy.c optional miibus | xmphy dev/mk48txx/mk48txx.c optional mk48txx dev/mlx/mlx.c optional mlx dev/mlx/mlx_disk.c optional mlx dev/mlx/mlx_pci.c optional mlx pci dev/mly/mly.c optional mly dev/mmc/mmc.c optional mmc dev/mmc/mmcbr_if.m standard dev/mmc/mmcbus_if.m standard dev/mmc/mmcsd.c optional mmcsd dev/mn/if_mn.c optional mn pci dev/mpr/mpr.c optional mpr dev/mpr/mpr_config.c optional mpr # XXX Work around clang warning, until maintainer approves fix. dev/mpr/mpr_mapping.c optional mpr \ compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}" dev/mpr/mpr_pci.c optional mpr pci dev/mpr/mpr_sas.c optional mpr \ compile-with "${NORMAL_C} ${NO_WUNNEEDED_INTERNAL_DECL}" dev/mpr/mpr_sas_lsi.c optional mpr dev/mpr/mpr_table.c optional mpr dev/mpr/mpr_user.c optional mpr dev/mps/mps.c optional mps dev/mps/mps_config.c optional mps # XXX Work around clang warning, until maintainer approves fix. dev/mps/mps_mapping.c optional mps \ compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}" dev/mps/mps_pci.c optional mps pci dev/mps/mps_sas.c optional mps \ compile-with "${NORMAL_C} ${NO_WUNNEEDED_INTERNAL_DECL}" dev/mps/mps_sas_lsi.c optional mps dev/mps/mps_table.c optional mps dev/mps/mps_user.c optional mps dev/mpt/mpt.c optional mpt dev/mpt/mpt_cam.c optional mpt dev/mpt/mpt_debug.c optional mpt dev/mpt/mpt_pci.c optional mpt pci dev/mpt/mpt_raid.c optional mpt dev/mpt/mpt_user.c optional mpt dev/mrsas/mrsas.c optional mrsas dev/mrsas/mrsas_cam.c optional mrsas dev/mrsas/mrsas_ioctl.c optional mrsas dev/mrsas/mrsas_fp.c optional mrsas dev/msk/if_msk.c optional msk dev/mvs/mvs.c optional mvs dev/mvs/mvs_if.m optional mvs dev/mvs/mvs_pci.c optional mvs pci dev/mwl/if_mwl.c optional mwl dev/mwl/if_mwl_pci.c optional mwl pci dev/mwl/mwlhal.c optional mwl mwlfw.c optional mwlfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk mw88W8363.fw:mw88W8363fw mwlboot.fw:mwlboot -mmwl -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "mwlfw.c" mw88W8363.fwo optional mwlfw \ dependency "mw88W8363.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "mw88W8363.fwo" mw88W8363.fw optional mwlfw \ dependency "$S/contrib/dev/mwl/mw88W8363.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "mw88W8363.fw" mwlboot.fwo optional mwlfw \ dependency "mwlboot.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "mwlboot.fwo" mwlboot.fw optional mwlfw \ dependency "$S/contrib/dev/mwl/mwlboot.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "mwlboot.fw" dev/mxge/if_mxge.c optional mxge pci dev/mxge/mxge_eth_z8e.c optional mxge pci dev/mxge/mxge_ethp_z8e.c optional mxge pci dev/mxge/mxge_rss_eth_z8e.c optional mxge pci dev/mxge/mxge_rss_ethp_z8e.c optional mxge pci dev/my/if_my.c optional my dev/nand/nand.c optional nand dev/nand/nand_bbt.c optional nand dev/nand/nand_cdev.c optional nand dev/nand/nand_generic.c optional nand dev/nand/nand_geom.c optional nand dev/nand/nand_id.c optional nand dev/nand/nandbus.c optional nand dev/nand/nandbus_if.m optional nand dev/nand/nand_if.m optional nand dev/nand/nandsim.c optional nandsim nand dev/nand/nandsim_chip.c optional nandsim nand dev/nand/nandsim_ctrl.c optional nandsim nand dev/nand/nandsim_log.c optional nandsim nand dev/nand/nandsim_swap.c optional nandsim nand dev/nand/nfc_if.m optional nand dev/ncr/ncr.c optional ncr pci dev/ncv/ncr53c500.c optional ncv dev/ncv/ncr53c500_pccard.c optional ncv pccard dev/netmap/netmap.c optional netmap dev/netmap/netmap_freebsd.c optional netmap dev/netmap/netmap_generic.c optional netmap dev/netmap/netmap_mbq.c optional netmap dev/netmap/netmap_mem2.c optional netmap dev/netmap/netmap_monitor.c optional netmap dev/netmap/netmap_offloadings.c optional netmap dev/netmap/netmap_pipe.c optional netmap dev/netmap/netmap_vale.c optional netmap # compile-with "${NORMAL_C} -Wconversion -Wextra" dev/nfsmb/nfsmb.c optional nfsmb pci dev/nge/if_nge.c optional nge dev/nxge/if_nxge.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nxge/xgehal/xgehal-device.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nxge/xgehal/xgehal-mm.c optional nxge dev/nxge/xgehal/xge-queue.c optional nxge dev/nxge/xgehal/xgehal-driver.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nxge/xgehal/xgehal-ring.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nxge/xgehal/xgehal-channel.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nxge/xgehal/xgehal-fifo.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nxge/xgehal/xgehal-stats.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nxge/xgehal/xgehal-config.c optional nxge dev/nxge/xgehal/xgehal-mgmt.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nmdm/nmdm.c optional nmdm dev/nsp/nsp.c optional nsp dev/nsp/nsp_pccard.c optional nsp pccard dev/null/null.c standard dev/oce/oce_hw.c optional oce pci dev/oce/oce_if.c optional oce pci dev/oce/oce_mbox.c optional oce pci dev/oce/oce_queue.c optional oce pci dev/oce/oce_sysctl.c optional oce pci dev/oce/oce_util.c optional oce pci dev/ofw/ofw_bus_if.m optional fdt dev/ofw/ofw_bus_subr.c optional fdt dev/ofw/ofw_fdt.c optional fdt dev/ofw/ofw_if.m optional fdt dev/ofw/ofw_iicbus.c optional fdt iicbus dev/ofw/ofwbus.c optional fdt dev/ofw/openfirm.c optional fdt dev/ofw/openfirmio.c optional fdt dev/patm/if_patm.c optional patm pci dev/patm/if_patm_attach.c optional patm pci dev/patm/if_patm_intr.c optional patm pci dev/patm/if_patm_ioctl.c optional patm pci dev/patm/if_patm_rtables.c optional patm pci dev/patm/if_patm_rx.c optional patm pci dev/patm/if_patm_tx.c optional patm pci dev/pbio/pbio.c optional pbio isa dev/pccard/card_if.m standard dev/pccard/pccard.c optional pccard dev/pccard/pccard_cis.c optional pccard dev/pccard/pccard_cis_quirks.c optional pccard dev/pccard/pccard_device.c optional pccard dev/pccard/power_if.m standard dev/pccbb/pccbb.c optional cbb dev/pccbb/pccbb_isa.c optional cbb isa dev/pccbb/pccbb_pci.c optional cbb pci dev/pcf/pcf.c optional pcf dev/pci/eisa_pci.c optional pci eisa dev/pci/fixup_pci.c optional pci dev/pci/hostb_pci.c optional pci dev/pci/ignore_pci.c optional pci dev/pci/isa_pci.c optional pci isa dev/pci/pci.c optional pci dev/pci/pci_if.m standard dev/pci/pci_iov.c optional pci pci_iov dev/pci/pci_iov_schema.c optional pci pci_iov dev/pci/pci_pci.c optional pci dev/pci/pci_subr.c optional pci dev/pci/pci_user.c optional pci dev/pci/pcib_if.m standard dev/pci/pcib_support.c standard dev/pci/vga_pci.c optional pci dev/pcn/if_pcn.c optional pcn pci dev/pdq/if_fea.c optional fea eisa dev/pdq/if_fpa.c optional fpa pci dev/pdq/pdq.c optional nowerror fea eisa | fpa pci dev/pdq/pdq_ifsubr.c optional nowerror fea eisa | fpa pci dev/ppbus/if_plip.c optional plip dev/ppbus/immio.c optional vpo dev/ppbus/lpbb.c optional lpbb dev/ppbus/lpt.c optional lpt dev/ppbus/pcfclock.c optional pcfclock dev/ppbus/ppb_1284.c optional ppbus dev/ppbus/ppb_base.c optional ppbus dev/ppbus/ppb_msq.c optional ppbus dev/ppbus/ppbconf.c optional ppbus dev/ppbus/ppbus_if.m optional ppbus dev/ppbus/ppi.c optional ppi dev/ppbus/pps.c optional pps dev/ppbus/vpo.c optional vpo dev/ppbus/vpoio.c optional vpo dev/ppc/ppc.c optional ppc dev/ppc/ppc_acpi.c optional ppc acpi dev/ppc/ppc_isa.c optional ppc isa dev/ppc/ppc_pci.c optional ppc pci dev/ppc/ppc_puc.c optional ppc puc dev/pst/pst-iop.c optional pst dev/pst/pst-pci.c optional pst pci dev/pst/pst-raid.c optional pst dev/pty/pty.c optional pty dev/puc/puc.c optional puc dev/puc/puc_cfg.c optional puc dev/puc/puc_pccard.c optional puc pccard dev/puc/puc_pci.c optional puc pci dev/puc/pucdata.c optional puc pci dev/quicc/quicc_core.c optional quicc dev/ral/rt2560.c optional ral dev/ral/rt2661.c optional ral dev/ral/rt2860.c optional ral dev/ral/if_ral_pci.c optional ral pci rt2561fw.c optional rt2561fw | ralfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rt2561.fw:rt2561fw -mrt2561 -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rt2561fw.c" rt2561fw.fwo optional rt2561fw | ralfw \ dependency "rt2561.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rt2561fw.fwo" rt2561.fw optional rt2561fw | ralfw \ dependency "$S/contrib/dev/ral/rt2561.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rt2561.fw" rt2561sfw.c optional rt2561sfw | ralfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rt2561s.fw:rt2561sfw -mrt2561s -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rt2561sfw.c" rt2561sfw.fwo optional rt2561sfw | ralfw \ dependency "rt2561s.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rt2561sfw.fwo" rt2561s.fw optional rt2561sfw | ralfw \ dependency "$S/contrib/dev/ral/rt2561s.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rt2561s.fw" rt2661fw.c optional rt2661fw | ralfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rt2661.fw:rt2661fw -mrt2661 -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rt2661fw.c" rt2661fw.fwo optional rt2661fw | ralfw \ dependency "rt2661.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rt2661fw.fwo" rt2661.fw optional rt2661fw | ralfw \ dependency "$S/contrib/dev/ral/rt2661.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rt2661.fw" rt2860fw.c optional rt2860fw | ralfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rt2860.fw:rt2860fw -mrt2860 -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rt2860fw.c" rt2860fw.fwo optional rt2860fw | ralfw \ dependency "rt2860.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rt2860fw.fwo" rt2860.fw optional rt2860fw | ralfw \ dependency "$S/contrib/dev/ral/rt2860.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rt2860.fw" dev/random/randomdev.c standard dev/random/random_adaptors.c standard dev/random/dummy_rng.c standard dev/random/live_entropy_sources.c standard dev/random/random_harvestq.c standard dev/random/randomdev_soft.c optional random dev/random/yarrow.c optional random dev/random/fortuna.c optional random dev/random/hash.c optional random dev/rc/rc.c optional rc dev/re/if_re.c optional re dev/rl/if_rl.c optional rl pci dev/rndtest/rndtest.c optional rndtest dev/rp/rp.c optional rp dev/rp/rp_isa.c optional rp isa dev/rp/rp_pci.c optional rp pci dev/safe/safe.c optional safe dev/scc/scc_if.m optional scc dev/scc/scc_bfe_ebus.c optional scc ebus dev/scc/scc_bfe_quicc.c optional scc quicc dev/scc/scc_bfe_sbus.c optional scc fhc | scc sbus dev/scc/scc_core.c optional scc dev/scc/scc_dev_quicc.c optional scc quicc dev/scc/scc_dev_sab82532.c optional scc dev/scc/scc_dev_z8530.c optional scc dev/scd/scd.c optional scd isa dev/scd/scd_isa.c optional scd isa dev/sdhci/sdhci.c optional sdhci dev/sdhci/sdhci_if.m optional sdhci dev/sdhci/sdhci_pci.c optional sdhci pci dev/sf/if_sf.c optional sf pci -dev/sfxge/common/efx_bootcfg.c optional sfxge pci -dev/sfxge/common/efx_ev.c optional sfxge pci -dev/sfxge/common/efx_filter.c optional sfxge pci -dev/sfxge/common/efx_intr.c optional sfxge pci -dev/sfxge/common/efx_mac.c optional sfxge pci -dev/sfxge/common/efx_mcdi.c optional sfxge pci -dev/sfxge/common/efx_mon.c optional sfxge pci -dev/sfxge/common/efx_nic.c optional sfxge pci -dev/sfxge/common/efx_nvram.c optional sfxge pci -dev/sfxge/common/efx_phy.c optional sfxge pci -dev/sfxge/common/efx_port.c optional sfxge pci -dev/sfxge/common/efx_rx.c optional sfxge pci -dev/sfxge/common/efx_sram.c optional sfxge pci -dev/sfxge/common/efx_tx.c optional sfxge pci -dev/sfxge/common/efx_vpd.c optional sfxge pci -dev/sfxge/common/efx_wol.c optional sfxge pci -dev/sfxge/common/siena_mac.c optional sfxge pci -dev/sfxge/common/siena_mon.c optional sfxge pci -dev/sfxge/common/siena_nic.c optional sfxge pci -dev/sfxge/common/siena_nvram.c optional sfxge pci -dev/sfxge/common/siena_phy.c optional sfxge pci -dev/sfxge/common/siena_sram.c optional sfxge pci -dev/sfxge/common/siena_vpd.c optional sfxge pci -dev/sfxge/sfxge.c optional sfxge pci -dev/sfxge/sfxge_dma.c optional sfxge pci -dev/sfxge/sfxge_ev.c optional sfxge pci -dev/sfxge/sfxge_intr.c optional sfxge pci -dev/sfxge/sfxge_mcdi.c optional sfxge pci -dev/sfxge/sfxge_port.c optional sfxge pci -dev/sfxge/sfxge_rx.c optional sfxge pci -dev/sfxge/sfxge_tx.c optional sfxge pci dev/sge/if_sge.c optional sge pci dev/si/si.c optional si dev/si/si2_z280.c optional si dev/si/si3_t225.c optional si dev/si/si_eisa.c optional si eisa dev/si/si_isa.c optional si isa dev/si/si_pci.c optional si pci dev/siba/siba.c optional siba dev/siba/siba_bwn.c optional siba_bwn pci dev/siba/siba_cc.c optional siba dev/siba/siba_core.c optional siba | siba_bwn pci dev/siba/siba_pcib.c optional siba pci dev/siis/siis.c optional siis pci dev/sis/if_sis.c optional sis pci dev/sk/if_sk.c optional sk pci dev/smbus/smb.c optional smb dev/smbus/smbconf.c optional smbus dev/smbus/smbus.c optional smbus dev/smbus/smbus_if.m optional smbus dev/smc/if_smc.c optional smc dev/smc/if_smc_fdt.c optional smc fdt dev/sn/if_sn.c optional sn dev/sn/if_sn_isa.c optional sn isa dev/sn/if_sn_pccard.c optional sn pccard dev/snp/snp.c optional snp dev/sound/clone.c optional sound dev/sound/unit.c optional sound dev/sound/isa/ad1816.c optional snd_ad1816 isa dev/sound/isa/ess.c optional snd_ess isa dev/sound/isa/gusc.c optional snd_gusc isa dev/sound/isa/mss.c optional snd_mss isa dev/sound/isa/sb16.c optional snd_sb16 isa dev/sound/isa/sb8.c optional snd_sb8 isa dev/sound/isa/sbc.c optional snd_sbc isa dev/sound/isa/sndbuf_dma.c optional sound isa dev/sound/pci/als4000.c optional snd_als4000 pci dev/sound/pci/atiixp.c optional snd_atiixp pci dev/sound/pci/cmi.c optional snd_cmi pci dev/sound/pci/cs4281.c optional snd_cs4281 pci dev/sound/pci/csa.c optional snd_csa pci dev/sound/pci/csapcm.c optional snd_csa pci dev/sound/pci/ds1.c optional snd_ds1 pci dev/sound/pci/emu10k1.c optional snd_emu10k1 pci dev/sound/pci/emu10kx.c optional snd_emu10kx pci dev/sound/pci/emu10kx-pcm.c optional snd_emu10kx pci dev/sound/pci/emu10kx-midi.c optional snd_emu10kx pci dev/sound/pci/envy24.c optional snd_envy24 pci dev/sound/pci/envy24ht.c optional snd_envy24ht pci dev/sound/pci/es137x.c optional snd_es137x pci dev/sound/pci/fm801.c optional snd_fm801 pci dev/sound/pci/ich.c optional snd_ich pci dev/sound/pci/maestro.c optional snd_maestro pci dev/sound/pci/maestro3.c optional snd_maestro3 pci dev/sound/pci/neomagic.c optional snd_neomagic pci dev/sound/pci/solo.c optional snd_solo pci dev/sound/pci/spicds.c optional snd_spicds pci dev/sound/pci/t4dwave.c optional snd_t4dwave pci dev/sound/pci/via8233.c optional snd_via8233 pci dev/sound/pci/via82c686.c optional snd_via82c686 pci dev/sound/pci/vibes.c optional snd_vibes pci dev/sound/pci/hda/hdaa.c optional snd_hda pci dev/sound/pci/hda/hdaa_patches.c optional snd_hda pci dev/sound/pci/hda/hdac.c optional snd_hda pci dev/sound/pci/hda/hdac_if.m optional snd_hda pci dev/sound/pci/hda/hdacc.c optional snd_hda pci dev/sound/pci/hdspe.c optional snd_hdspe pci dev/sound/pci/hdspe-pcm.c optional snd_hdspe pci dev/sound/pcm/ac97.c optional sound dev/sound/pcm/ac97_if.m optional sound dev/sound/pcm/ac97_patch.c optional sound dev/sound/pcm/buffer.c optional sound \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/channel.c optional sound dev/sound/pcm/channel_if.m optional sound dev/sound/pcm/dsp.c optional sound dev/sound/pcm/feeder.c optional sound dev/sound/pcm/feeder_chain.c optional sound dev/sound/pcm/feeder_eq.c optional sound \ dependency "feeder_eq_gen.h" \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/feeder_if.m optional sound dev/sound/pcm/feeder_format.c optional sound \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/feeder_matrix.c optional sound \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/feeder_mixer.c optional sound \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/feeder_rate.c optional sound \ dependency "feeder_rate_gen.h" \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/feeder_volume.c optional sound \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/mixer.c optional sound dev/sound/pcm/mixer_if.m optional sound dev/sound/pcm/sndstat.c optional sound dev/sound/pcm/sound.c optional sound dev/sound/pcm/vchan.c optional sound dev/sound/usb/uaudio.c optional snd_uaudio usb dev/sound/usb/uaudio_pcm.c optional snd_uaudio usb dev/sound/midi/midi.c optional sound dev/sound/midi/mpu401.c optional sound dev/sound/midi/mpu_if.m optional sound dev/sound/midi/mpufoi_if.m optional sound dev/sound/midi/sequencer.c optional sound dev/sound/midi/synth_if.m optional sound dev/spibus/ofw_spibus.c optional fdt spibus dev/spibus/spibus.c optional spibus \ dependency "spibus_if.h" dev/spibus/spibus_if.m optional spibus dev/ste/if_ste.c optional ste pci dev/stg/tmc18c30.c optional stg dev/stg/tmc18c30_isa.c optional stg isa dev/stg/tmc18c30_pccard.c optional stg pccard dev/stg/tmc18c30_pci.c optional stg pci dev/stg/tmc18c30_subr.c optional stg dev/stge/if_stge.c optional stge dev/streams/streams.c optional streams dev/sym/sym_hipd.c optional sym \ dependency "$S/dev/sym/sym_{conf,defs}.h" dev/syscons/blank/blank_saver.c optional blank_saver dev/syscons/daemon/daemon_saver.c optional daemon_saver dev/syscons/dragon/dragon_saver.c optional dragon_saver dev/syscons/fade/fade_saver.c optional fade_saver dev/syscons/fire/fire_saver.c optional fire_saver dev/syscons/green/green_saver.c optional green_saver dev/syscons/logo/logo.c optional logo_saver dev/syscons/logo/logo_saver.c optional logo_saver dev/syscons/rain/rain_saver.c optional rain_saver dev/syscons/schistory.c optional sc dev/syscons/scmouse.c optional sc dev/syscons/scterm.c optional sc dev/syscons/scvidctl.c optional sc dev/syscons/snake/snake_saver.c optional snake_saver dev/syscons/star/star_saver.c optional star_saver dev/syscons/syscons.c optional sc dev/syscons/sysmouse.c optional sc dev/syscons/warp/warp_saver.c optional warp_saver dev/tdfx/tdfx_linux.c optional tdfx_linux tdfx compat_linux dev/tdfx/tdfx_pci.c optional tdfx pci dev/ti/if_ti.c optional ti pci dev/tl/if_tl.c optional tl pci dev/trm/trm.c optional trm dev/twa/tw_cl_init.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twa/tw_cl_intr.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twa/tw_cl_io.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twa/tw_cl_misc.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twa/tw_osl_cam.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twa/tw_osl_freebsd.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twe/twe.c optional twe dev/twe/twe_freebsd.c optional twe dev/tws/tws.c optional tws dev/tws/tws_cam.c optional tws dev/tws/tws_hdm.c optional tws dev/tws/tws_services.c optional tws dev/tws/tws_user.c optional tws dev/tx/if_tx.c optional tx dev/txp/if_txp.c optional txp dev/uart/uart_bus_acpi.c optional uart acpi #dev/uart/uart_bus_cbus.c optional uart cbus dev/uart/uart_bus_ebus.c optional uart ebus dev/uart/uart_bus_fdt.c optional uart fdt dev/uart/uart_bus_isa.c optional uart isa dev/uart/uart_bus_pccard.c optional uart pccard dev/uart/uart_bus_pci.c optional uart pci dev/uart/uart_bus_puc.c optional uart puc dev/uart/uart_bus_scc.c optional uart scc dev/uart/uart_core.c optional uart dev/uart/uart_dbg.c optional uart gdb dev/uart/uart_dev_ns8250.c optional uart uart_ns8250 dev/uart/uart_dev_pl011.c optional uart pl011 dev/uart/uart_dev_quicc.c optional uart quicc dev/uart/uart_dev_sab82532.c optional uart uart_sab82532 dev/uart/uart_dev_sab82532.c optional uart scc dev/uart/uart_dev_z8530.c optional uart uart_z8530 dev/uart/uart_dev_z8530.c optional uart scc dev/uart/uart_if.m optional uart dev/uart/uart_subr.c optional uart dev/uart/uart_tty.c optional uart dev/ubsec/ubsec.c optional ubsec # # USB controller drivers # dev/usb/controller/at91dci.c optional at91dci dev/usb/controller/at91dci_atmelarm.c optional at91dci at91rm9200 dev/usb/controller/musb_otg.c optional musb dev/usb/controller/musb_otg_atmelarm.c optional musb at91rm9200 dev/usb/controller/dwc_otg.c optional dwcotg dev/usb/controller/dwc_otg_fdt.c optional dwcotg fdt dev/usb/controller/ehci.c optional ehci dev/usb/controller/ehci_pci.c optional ehci pci dev/usb/controller/ohci.c optional ohci dev/usb/controller/ohci_atmelarm.c optional ohci at91rm9200 dev/usb/controller/ohci_pci.c optional ohci pci dev/usb/controller/uhci.c optional uhci dev/usb/controller/uhci_pci.c optional uhci pci dev/usb/controller/xhci.c optional xhci dev/usb/controller/xhci_pci.c optional xhci pci dev/usb/controller/saf1761_otg.c optional saf1761otg dev/usb/controller/saf1761_otg_fdt.c optional saf1761otg fdt dev/usb/controller/uss820dci.c optional uss820dci dev/usb/controller/uss820dci_atmelarm.c optional uss820dci at91rm9200 dev/usb/controller/usb_controller.c optional usb # # USB storage drivers # dev/usb/storage/umass.c optional umass dev/usb/storage/urio.c optional urio dev/usb/storage/ustorage_fs.c optional usfs # # USB core # dev/usb/usb_busdma.c optional usb dev/usb/usb_compat_linux.c optional usb dev/usb/usb_core.c optional usb dev/usb/usb_debug.c optional usb dev/usb/usb_dev.c optional usb dev/usb/usb_device.c optional usb dev/usb/usb_dynamic.c optional usb dev/usb/usb_error.c optional usb dev/usb/usb_generic.c optional usb dev/usb/usb_handle_request.c optional usb dev/usb/usb_hid.c optional usb dev/usb/usb_hub.c optional usb dev/usb/usb_if.m optional usb dev/usb/usb_lookup.c optional usb dev/usb/usb_mbuf.c optional usb dev/usb/usb_msctest.c optional usb dev/usb/usb_parse.c optional usb dev/usb/usb_pf.c optional usb dev/usb/usb_process.c optional usb dev/usb/usb_request.c optional usb dev/usb/usb_transfer.c optional usb dev/usb/usb_util.c optional usb # # USB network drivers # dev/usb/net/if_aue.c optional aue dev/usb/net/if_axe.c optional axe dev/usb/net/if_axge.c optional axge dev/usb/net/if_cdce.c optional cdce dev/usb/net/if_cue.c optional cue dev/usb/net/if_ipheth.c optional ipheth dev/usb/net/if_kue.c optional kue dev/usb/net/if_mos.c optional mos dev/usb/net/if_rue.c optional rue dev/usb/net/if_smsc.c optional smsc dev/usb/net/if_udav.c optional udav dev/usb/net/if_usie.c optional usie dev/usb/net/if_urndis.c optional urndis dev/usb/net/ruephy.c optional rue dev/usb/net/usb_ethernet.c optional aue | axe | axge | cdce | cue | kue | \ mos | rue | smsc | udav | ipheth | \ urndis dev/usb/net/uhso.c optional uhso # # USB WLAN drivers # dev/usb/wlan/if_rsu.c optional rsu rsu-rtl8712fw.c optional rsu-rtl8712fw | rsufw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rsu-rtl8712fw.fw:rsu-rtl8712fw:120 -mrsu-rtl8712fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rsu-rtl8712fw.c" rsu-rtl8712fw.fwo optional rsu-rtl8712fw | rsufw \ dependency "rsu-rtl8712fw.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rsu-rtl8712fw.fwo" rsu-rtl8712fw.fw optional rsu-rtl8712.fw | rsufw \ dependency "$S/contrib/dev/rsu/rsu-rtl8712fw.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rsu-rtl8712fw.fw" dev/usb/wlan/if_rum.c optional rum dev/usb/wlan/if_run.c optional run runfw.c optional runfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk run.fw:runfw -mrunfw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "runfw.c" runfw.fwo optional runfw \ dependency "run.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "runfw.fwo" run.fw optional runfw \ dependency "$S/contrib/dev/run/rt2870.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "run.fw" dev/usb/wlan/if_uath.c optional uath dev/usb/wlan/if_upgt.c optional upgt dev/usb/wlan/if_ural.c optional ural dev/usb/wlan/if_urtw.c optional urtw dev/usb/wlan/if_urtwn.c optional urtwn urtwn-rtl8188eufw.c optional urtwn-rtl8188eufw | urtwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk urtwn-rtl8188eufw.fw:urtwn-rtl8188eufw:111 -murtwn-rtl8188eufw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "urtwn-rtl8188eufw.c" urtwn-rtl8188eufw.fwo optional urtwn-rtl8188eufw | urtwnfw \ dependency "urtwn-rtl8188eufw.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "urtwn-rtl8188eufw.fwo" urtwn-rtl8188eufw.fw optional urtwn-rtl8188eufw | urtwnfw \ dependency "$S/contrib/dev/urtwn/urtwn-rtl8188eufw.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "urtwn-rtl8188eufw.fw" urtwn-rtl8192cfwT.c optional urtwn-rtl8192cfwT | urtwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk urtwn-rtl8192cfwT.fw:urtwn-rtl8192cfwT:111 -murtwn-rtl8192cfwT -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "urtwn-rtl8192cfwT.c" urtwn-rtl8192cfwT.fwo optional urtwn-rtl8192cfwT | urtwnfw \ dependency "urtwn-rtl8192cfwT.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "urtwn-rtl8192cfwT.fwo" urtwn-rtl8192cfwT.fw optional urtwn-rtl8192cfwT | urtwnfw \ dependency "$S/contrib/dev/urtwn/urtwn-rtl8192cfwT.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "urtwn-rtl8192cfwT.fw" urtwn-rtl8192cfwU.c optional urtwn-rtl8192cfwU | urtwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk urtwn-rtl8192cfwU.fw:urtwn-rtl8192cfwU:111 -murtwn-rtl8192cfwU -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "urtwn-rtl8192cfwU.c" urtwn-rtl8192cfwU.fwo optional urtwn-rtl8192cfwU | urtwnfw \ dependency "urtwn-rtl8192cfwU.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "urtwn-rtl8192cfwU.fwo" urtwn-rtl8192cfwU.fw optional urtwn-rtl8192cfwU | urtwnfw \ dependency "$S/contrib/dev/urtwn/urtwn-rtl8192cfwU.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "urtwn-rtl8192cfwU.fw" dev/usb/wlan/if_zyd.c optional zyd # # USB serial and parallel port drivers # dev/usb/serial/u3g.c optional u3g dev/usb/serial/uark.c optional uark dev/usb/serial/ubsa.c optional ubsa dev/usb/serial/ubser.c optional ubser dev/usb/serial/uchcom.c optional uchcom dev/usb/serial/ucycom.c optional ucycom dev/usb/serial/ufoma.c optional ufoma dev/usb/serial/uftdi.c optional uftdi dev/usb/serial/ugensa.c optional ugensa dev/usb/serial/uipaq.c optional uipaq dev/usb/serial/ulpt.c optional ulpt dev/usb/serial/umcs.c optional umcs dev/usb/serial/umct.c optional umct dev/usb/serial/umodem.c optional umodem dev/usb/serial/umoscom.c optional umoscom dev/usb/serial/uplcom.c optional uplcom dev/usb/serial/uslcom.c optional uslcom dev/usb/serial/uvisor.c optional uvisor dev/usb/serial/uvscom.c optional uvscom dev/usb/serial/usb_serial.c optional ucom | u3g | uark | ubsa | ubser | \ uchcom | ucycom | ufoma | uftdi | \ ugensa | uipaq | umcs | umct | \ umodem | umoscom | uplcom | usie | \ uslcom | uvisor | uvscom # # USB misc drivers # dev/usb/misc/ufm.c optional ufm dev/usb/misc/udbp.c optional udbp dev/usb/misc/uled.c optional uled # # USB input drivers # dev/usb/input/atp.c optional atp dev/usb/input/uep.c optional uep dev/usb/input/uhid.c optional uhid dev/usb/input/ukbd.c optional ukbd dev/usb/input/ums.c optional ums dev/usb/input/wsp.c optional wsp # # USB quirks # dev/usb/quirk/usb_quirk.c optional usb # # USB templates # dev/usb/template/usb_template.c optional usb_template dev/usb/template/usb_template_audio.c optional usb_template dev/usb/template/usb_template_cdce.c optional usb_template dev/usb/template/usb_template_kbd.c optional usb_template dev/usb/template/usb_template_modem.c optional usb_template dev/usb/template/usb_template_mouse.c optional usb_template dev/usb/template/usb_template_msc.c optional usb_template dev/usb/template/usb_template_mtp.c optional usb_template dev/usb/template/usb_template_phone.c optional usb_template dev/usb/template/usb_template_serialnet.c optional usb_template # # USB video drivers # dev/usb/video/udl.c optional udl # # USB END # dev/videomode/videomode.c optional videomode dev/videomode/edid.c optional videomode dev/videomode/pickmode.c optional videomode dev/videomode/vesagtf.c optional videomode dev/utopia/idtphy.c optional utopia dev/utopia/suni.c optional utopia dev/utopia/utopia.c optional utopia dev/vge/if_vge.c optional vge dev/viapm/viapm.c optional viapm pci dev/virtio/virtio.c optional virtio dev/virtio/virtqueue.c optional virtio dev/virtio/virtio_bus_if.m optional virtio dev/virtio/virtio_if.m optional virtio dev/virtio/pci/virtio_pci.c optional virtio_pci dev/virtio/mmio/virtio_mmio.c optional virtio_mmio dev/virtio/mmio/virtio_mmio_if.m optional virtio_mmio dev/virtio/network/if_vtnet.c optional vtnet dev/virtio/block/virtio_blk.c optional virtio_blk dev/virtio/balloon/virtio_balloon.c optional virtio_balloon dev/virtio/scsi/virtio_scsi.c optional virtio_scsi dev/virtio/random/virtio_random.c optional virtio_random dev/virtio/console/virtio_console.c optional virtio_console dev/vkbd/vkbd.c optional vkbd dev/vr/if_vr.c optional vr pci dev/vt/colors/vt_termcolors.c optional vt dev/vt/font/vt_font_default.c optional vt dev/vt/font/vt_mouse_cursor.c optional vt dev/vt/hw/efifb/efifb.c optional vt_efifb dev/vt/hw/fb/vt_fb.c optional vt dev/vt/hw/vga/vt_vga.c optional vt vt_vga dev/vt/logo/logo_freebsd.c optional vt splash dev/vt/vt_buf.c optional vt dev/vt/vt_consolectl.c optional vt dev/vt/vt_core.c optional vt dev/vt/vt_font.c optional vt dev/vt/vt_sysmouse.c optional vt dev/vte/if_vte.c optional vte pci dev/vx/if_vx.c optional vx dev/vx/if_vx_eisa.c optional vx eisa dev/vx/if_vx_pci.c optional vx pci dev/vxge/vxge.c optional vxge dev/vxge/vxgehal/vxgehal-ifmsg.c optional vxge dev/vxge/vxgehal/vxgehal-mrpcim.c optional vxge dev/vxge/vxgehal/vxge-queue.c optional vxge dev/vxge/vxgehal/vxgehal-ring.c optional vxge dev/vxge/vxgehal/vxgehal-swapper.c optional vxge dev/vxge/vxgehal/vxgehal-mgmt.c optional vxge dev/vxge/vxgehal/vxgehal-srpcim.c optional vxge dev/vxge/vxgehal/vxgehal-config.c optional vxge dev/vxge/vxgehal/vxgehal-blockpool.c optional vxge dev/vxge/vxgehal/vxgehal-doorbells.c optional vxge dev/vxge/vxgehal/vxgehal-mgmtaux.c optional vxge dev/vxge/vxgehal/vxgehal-device.c optional vxge dev/vxge/vxgehal/vxgehal-mm.c optional vxge dev/vxge/vxgehal/vxgehal-driver.c optional vxge dev/vxge/vxgehal/vxgehal-virtualpath.c optional vxge dev/vxge/vxgehal/vxgehal-channel.c optional vxge dev/vxge/vxgehal/vxgehal-fifo.c optional vxge dev/watchdog/watchdog.c standard dev/wb/if_wb.c optional wb pci dev/wds/wd7000.c optional wds isa dev/wi/if_wi.c optional wi dev/wi/if_wi_pccard.c optional wi pccard dev/wi/if_wi_pci.c optional wi pci dev/wl/if_wl.c optional wl isa dev/wpi/if_wpi.c optional wpi pci wpifw.c optional wpifw \ compile-with "${AWK} -f $S/tools/fw_stub.awk wpi.fw:wpifw:153229 -mwpi -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "wpifw.c" wpifw.fwo optional wpifw \ dependency "wpi.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "wpifw.fwo" wpi.fw optional wpifw \ dependency "$S/contrib/dev/wpi/iwlwifi-3945-15.32.2.9.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "wpi.fw" dev/xe/if_xe.c optional xe dev/xe/if_xe_pccard.c optional xe pccard dev/xen/balloon/balloon.c optional xenhvm dev/xen/blkfront/blkfront.c optional xenhvm dev/xen/blkback/blkback.c optional xenhvm dev/xen/console/console.c optional xenhvm dev/xen/console/xencons_ring.c optional xenhvm dev/xen/control/control.c optional xenhvm dev/xen/grant_table/grant_table.c optional xenhvm dev/xen/netback/netback.c optional xenhvm dev/xen/netfront/netfront.c optional xenhvm dev/xen/xenpci/xenpci.c optional xenpci dev/xen/timer/timer.c optional xenhvm dev/xen/pvcpu/pvcpu.c optional xenhvm dev/xen/xenstore/xenstore.c optional xenhvm dev/xen/xenstore/xenstore_dev.c optional xenhvm dev/xen/xenstore/xenstored_dev.c optional xenhvm dev/xen/evtchn/evtchn_dev.c optional xenhvm dev/xen/privcmd/privcmd.c optional xenhvm dev/xen/debug/debug.c optional xenhvm dev/xl/if_xl.c optional xl pci dev/xl/xlphy.c optional xl pci fs/autofs/autofs.c optional autofs fs/autofs/autofs_vfsops.c optional autofs fs/autofs/autofs_vnops.c optional autofs fs/deadfs/dead_vnops.c standard fs/devfs/devfs_devs.c standard fs/devfs/devfs_dir.c standard fs/devfs/devfs_rule.c standard fs/devfs/devfs_vfsops.c standard fs/devfs/devfs_vnops.c standard fs/fdescfs/fdesc_vfsops.c optional fdescfs fs/fdescfs/fdesc_vnops.c optional fdescfs fs/fifofs/fifo_vnops.c standard fs/cuse/cuse.c optional cuse fs/fuse/fuse_device.c optional fuse fs/fuse/fuse_file.c optional fuse fs/fuse/fuse_internal.c optional fuse fs/fuse/fuse_io.c optional fuse fs/fuse/fuse_ipc.c optional fuse fs/fuse/fuse_main.c optional fuse fs/fuse/fuse_node.c optional fuse fs/fuse/fuse_vfsops.c optional fuse fs/fuse/fuse_vnops.c optional fuse fs/msdosfs/msdosfs_conv.c optional msdosfs fs/msdosfs/msdosfs_denode.c optional msdosfs fs/msdosfs/msdosfs_fat.c optional msdosfs fs/msdosfs/msdosfs_fileno.c optional msdosfs fs/msdosfs/msdosfs_iconv.c optional msdosfs_iconv fs/msdosfs/msdosfs_lookup.c optional msdosfs fs/msdosfs/msdosfs_vfsops.c optional msdosfs fs/msdosfs/msdosfs_vnops.c optional msdosfs fs/nandfs/bmap.c optional nandfs fs/nandfs/nandfs_alloc.c optional nandfs fs/nandfs/nandfs_bmap.c optional nandfs fs/nandfs/nandfs_buffer.c optional nandfs fs/nandfs/nandfs_cleaner.c optional nandfs fs/nandfs/nandfs_cpfile.c optional nandfs fs/nandfs/nandfs_dat.c optional nandfs fs/nandfs/nandfs_dir.c optional nandfs fs/nandfs/nandfs_ifile.c optional nandfs fs/nandfs/nandfs_segment.c optional nandfs fs/nandfs/nandfs_subr.c optional nandfs fs/nandfs/nandfs_sufile.c optional nandfs fs/nandfs/nandfs_vfsops.c optional nandfs fs/nandfs/nandfs_vnops.c optional nandfs fs/nfs/nfs_commonkrpc.c optional nfscl | nfsd fs/nfs/nfs_commonsubs.c optional nfscl | nfsd fs/nfs/nfs_commonport.c optional nfscl | nfsd fs/nfs/nfs_commonacl.c optional nfscl | nfsd fs/nfsclient/nfs_clcomsubs.c optional nfscl fs/nfsclient/nfs_clsubs.c optional nfscl fs/nfsclient/nfs_clstate.c optional nfscl fs/nfsclient/nfs_clkrpc.c optional nfscl fs/nfsclient/nfs_clrpcops.c optional nfscl fs/nfsclient/nfs_clvnops.c optional nfscl fs/nfsclient/nfs_clnode.c optional nfscl fs/nfsclient/nfs_clvfsops.c optional nfscl fs/nfsclient/nfs_clport.c optional nfscl fs/nfsclient/nfs_clbio.c optional nfscl fs/nfsclient/nfs_clnfsiod.c optional nfscl fs/nfsserver/nfs_fha_new.c optional nfsd inet fs/nfsserver/nfs_nfsdsocket.c optional nfsd inet fs/nfsserver/nfs_nfsdsubs.c optional nfsd inet fs/nfsserver/nfs_nfsdstate.c optional nfsd inet fs/nfsserver/nfs_nfsdkrpc.c optional nfsd inet fs/nfsserver/nfs_nfsdserv.c optional nfsd inet fs/nfsserver/nfs_nfsdport.c optional nfsd inet fs/nfsserver/nfs_nfsdcache.c optional nfsd inet fs/nullfs/null_subr.c optional nullfs fs/nullfs/null_vfsops.c optional nullfs fs/nullfs/null_vnops.c optional nullfs fs/procfs/procfs.c optional procfs fs/procfs/procfs_ctl.c optional procfs fs/procfs/procfs_dbregs.c optional procfs fs/procfs/procfs_fpregs.c optional procfs fs/procfs/procfs_ioctl.c optional procfs fs/procfs/procfs_map.c optional procfs fs/procfs/procfs_mem.c optional procfs fs/procfs/procfs_note.c optional procfs fs/procfs/procfs_osrel.c optional procfs fs/procfs/procfs_regs.c optional procfs fs/procfs/procfs_rlimit.c optional procfs fs/procfs/procfs_status.c optional procfs fs/procfs/procfs_type.c optional procfs fs/pseudofs/pseudofs.c optional pseudofs fs/pseudofs/pseudofs_fileno.c optional pseudofs fs/pseudofs/pseudofs_vncache.c optional pseudofs fs/pseudofs/pseudofs_vnops.c optional pseudofs fs/smbfs/smbfs_io.c optional smbfs fs/smbfs/smbfs_node.c optional smbfs fs/smbfs/smbfs_smb.c optional smbfs fs/smbfs/smbfs_subr.c optional smbfs fs/smbfs/smbfs_vfsops.c optional smbfs fs/smbfs/smbfs_vnops.c optional smbfs fs/udf/osta.c optional udf fs/udf/udf_iconv.c optional udf_iconv fs/udf/udf_vfsops.c optional udf fs/udf/udf_vnops.c optional udf fs/unionfs/union_subr.c optional unionfs fs/unionfs/union_vfsops.c optional unionfs fs/unionfs/union_vnops.c optional unionfs fs/tmpfs/tmpfs_vnops.c optional tmpfs fs/tmpfs/tmpfs_fifoops.c optional tmpfs fs/tmpfs/tmpfs_vfsops.c optional tmpfs fs/tmpfs/tmpfs_subr.c optional tmpfs gdb/gdb_cons.c optional gdb gdb/gdb_main.c optional gdb gdb/gdb_packet.c optional gdb geom/bde/g_bde.c optional geom_bde geom/bde/g_bde_crypt.c optional geom_bde geom/bde/g_bde_lock.c optional geom_bde geom/bde/g_bde_work.c optional geom_bde geom/cache/g_cache.c optional geom_cache geom/concat/g_concat.c optional geom_concat geom/eli/g_eli.c optional geom_eli geom/eli/g_eli_crypto.c optional geom_eli geom/eli/g_eli_ctl.c optional geom_eli geom/eli/g_eli_integrity.c optional geom_eli geom/eli/g_eli_key.c optional geom_eli geom/eli/g_eli_key_cache.c optional geom_eli geom/eli/g_eli_privacy.c optional geom_eli geom/eli/pkcs5v2.c optional geom_eli geom/gate/g_gate.c optional geom_gate geom/geom_aes.c optional geom_aes geom/geom_bsd.c optional geom_bsd geom/geom_bsd_enc.c optional geom_bsd | geom_part_bsd geom/geom_ccd.c optional ccd | geom_ccd geom/geom_ctl.c standard geom/geom_dev.c standard geom/geom_disk.c standard geom/geom_dump.c standard geom/geom_event.c standard geom/geom_fox.c optional geom_fox geom/geom_flashmap.c optional fdt cfi | fdt nand geom/geom_io.c standard geom/geom_kern.c standard geom/geom_map.c optional geom_map geom/geom_mbr.c optional geom_mbr geom/geom_mbr_enc.c optional geom_mbr geom/geom_pc98.c optional geom_pc98 geom/geom_pc98_enc.c optional geom_pc98 geom/geom_redboot.c optional geom_redboot geom/geom_slice.c standard geom/geom_subr.c standard geom/geom_sunlabel.c optional geom_sunlabel geom/geom_sunlabel_enc.c optional geom_sunlabel geom/geom_vfs.c standard geom/geom_vol_ffs.c optional geom_vol geom/journal/g_journal.c optional geom_journal geom/journal/g_journal_ufs.c optional geom_journal geom/label/g_label.c optional geom_label | geom_label_gpt geom/label/g_label_ext2fs.c optional geom_label geom/label/g_label_iso9660.c optional geom_label geom/label/g_label_msdosfs.c optional geom_label geom/label/g_label_ntfs.c optional geom_label geom/label/g_label_reiserfs.c optional geom_label geom/label/g_label_ufs.c optional geom_label geom/label/g_label_gpt.c optional geom_label | geom_label_gpt geom/label/g_label_disk_ident.c optional geom_label geom/linux_lvm/g_linux_lvm.c optional geom_linux_lvm geom/mirror/g_mirror.c optional geom_mirror geom/mirror/g_mirror_ctl.c optional geom_mirror geom/mountver/g_mountver.c optional geom_mountver geom/multipath/g_multipath.c optional geom_multipath geom/nop/g_nop.c optional geom_nop geom/part/g_part.c standard geom/part/g_part_if.m standard geom/part/g_part_apm.c optional geom_part_apm geom/part/g_part_bsd.c optional geom_part_bsd geom/part/g_part_bsd64.c optional geom_part_bsd64 geom/part/g_part_ebr.c optional geom_part_ebr geom/part/g_part_gpt.c optional geom_part_gpt geom/part/g_part_ldm.c optional geom_part_ldm geom/part/g_part_mbr.c optional geom_part_mbr geom/part/g_part_pc98.c optional geom_part_pc98 geom/part/g_part_vtoc8.c optional geom_part_vtoc8 geom/raid/g_raid.c optional geom_raid geom/raid/g_raid_ctl.c optional geom_raid geom/raid/g_raid_md_if.m optional geom_raid geom/raid/g_raid_tr_if.m optional geom_raid geom/raid/md_ddf.c optional geom_raid geom/raid/md_intel.c optional geom_raid geom/raid/md_jmicron.c optional geom_raid geom/raid/md_nvidia.c optional geom_raid geom/raid/md_promise.c optional geom_raid geom/raid/md_sii.c optional geom_raid geom/raid/tr_concat.c optional geom_raid geom/raid/tr_raid0.c optional geom_raid geom/raid/tr_raid1.c optional geom_raid geom/raid/tr_raid1e.c optional geom_raid geom/raid/tr_raid5.c optional geom_raid geom/raid3/g_raid3.c optional geom_raid3 geom/raid3/g_raid3_ctl.c optional geom_raid3 geom/shsec/g_shsec.c optional geom_shsec geom/stripe/g_stripe.c optional geom_stripe geom/uncompress/g_uncompress.c optional geom_uncompress contrib/xz-embedded/freebsd/xz_malloc.c \ optional xz_embedded | geom_uncompress \ compile-with "${NORMAL_C} -I$S/contrib/xz-embedded/freebsd/ -I$S/contrib/xz-embedded/linux/lib/xz/ -I$S/contrib/xz-embedded/linux/include/linux/" contrib/xz-embedded/linux/lib/xz/xz_crc32.c \ optional xz_embedded | geom_uncompress \ compile-with "${NORMAL_C} -I$S/contrib/xz-embedded/freebsd/ -I$S/contrib/xz-embedded/linux/lib/xz/ -I$S/contrib/xz-embedded/linux/include/linux/" contrib/xz-embedded/linux/lib/xz/xz_dec_bcj.c \ optional xz_embedded | geom_uncompress \ compile-with "${NORMAL_C} -I$S/contrib/xz-embedded/freebsd/ -I$S/contrib/xz-embedded/linux/lib/xz/ -I$S/contrib/xz-embedded/linux/include/linux/" contrib/xz-embedded/linux/lib/xz/xz_dec_lzma2.c \ optional xz_embedded | geom_uncompress \ compile-with "${NORMAL_C} -I$S/contrib/xz-embedded/freebsd/ -I$S/contrib/xz-embedded/linux/lib/xz/ -I$S/contrib/xz-embedded/linux/include/linux/" contrib/xz-embedded/linux/lib/xz/xz_dec_stream.c \ optional xz_embedded | geom_uncompress \ compile-with "${NORMAL_C} -I$S/contrib/xz-embedded/freebsd/ -I$S/contrib/xz-embedded/linux/lib/xz/ -I$S/contrib/xz-embedded/linux/include/linux/" geom/uzip/g_uzip.c optional geom_uzip geom/vinum/geom_vinum.c optional geom_vinum geom/vinum/geom_vinum_create.c optional geom_vinum geom/vinum/geom_vinum_drive.c optional geom_vinum geom/vinum/geom_vinum_plex.c optional geom_vinum geom/vinum/geom_vinum_volume.c optional geom_vinum geom/vinum/geom_vinum_subr.c optional geom_vinum geom/vinum/geom_vinum_raid5.c optional geom_vinum geom/vinum/geom_vinum_share.c optional geom_vinum geom/vinum/geom_vinum_list.c optional geom_vinum geom/vinum/geom_vinum_rm.c optional geom_vinum geom/vinum/geom_vinum_init.c optional geom_vinum geom/vinum/geom_vinum_state.c optional geom_vinum geom/vinum/geom_vinum_rename.c optional geom_vinum geom/vinum/geom_vinum_move.c optional geom_vinum geom/vinum/geom_vinum_events.c optional geom_vinum geom/virstor/binstream.c optional geom_virstor geom/virstor/g_virstor.c optional geom_virstor geom/virstor/g_virstor_md.c optional geom_virstor geom/zero/g_zero.c optional geom_zero fs/ext2fs/ext2_alloc.c optional ext2fs fs/ext2fs/ext2_balloc.c optional ext2fs fs/ext2fs/ext2_bmap.c optional ext2fs fs/ext2fs/ext2_extents.c optional ext2fs fs/ext2fs/ext2_inode.c optional ext2fs fs/ext2fs/ext2_inode_cnv.c optional ext2fs fs/ext2fs/ext2_lookup.c optional ext2fs fs/ext2fs/ext2_subr.c optional ext2fs fs/ext2fs/ext2_vfsops.c optional ext2fs fs/ext2fs/ext2_vnops.c optional ext2fs gnu/fs/reiserfs/reiserfs_hashes.c optional reiserfs \ warning "kernel contains GPL contaminated ReiserFS filesystem" gnu/fs/reiserfs/reiserfs_inode.c optional reiserfs gnu/fs/reiserfs/reiserfs_item_ops.c optional reiserfs gnu/fs/reiserfs/reiserfs_namei.c optional reiserfs gnu/fs/reiserfs/reiserfs_prints.c optional reiserfs gnu/fs/reiserfs/reiserfs_stree.c optional reiserfs gnu/fs/reiserfs/reiserfs_vfsops.c optional reiserfs gnu/fs/reiserfs/reiserfs_vnops.c optional reiserfs # isa/isa_if.m standard isa/isa_common.c optional isa isa/isahint.c optional isa isa/pnp.c optional isa isapnp isa/pnpparse.c optional isa isapnp fs/cd9660/cd9660_bmap.c optional cd9660 fs/cd9660/cd9660_lookup.c optional cd9660 fs/cd9660/cd9660_node.c optional cd9660 fs/cd9660/cd9660_rrip.c optional cd9660 fs/cd9660/cd9660_util.c optional cd9660 fs/cd9660/cd9660_vfsops.c optional cd9660 fs/cd9660/cd9660_vnops.c optional cd9660 fs/cd9660/cd9660_iconv.c optional cd9660_iconv kern/bus_if.m standard kern/clock_if.m standard kern/cpufreq_if.m standard kern/device_if.m standard kern/imgact_binmisc.c optional imagact_binmisc kern/imgact_elf.c standard kern/imgact_elf32.c optional compat_freebsd32 kern/imgact_shell.c standard kern/inflate.c optional gzip kern/init_main.c standard kern/init_sysent.c standard kern/ksched.c optional _kposix_priority_scheduling kern/kern_acct.c standard kern/kern_alq.c optional alq kern/kern_clock.c standard kern/kern_condvar.c standard kern/kern_conf.c standard kern/kern_cons.c standard kern/kern_cpu.c standard kern/kern_cpuset.c standard kern/kern_context.c standard kern/kern_descrip.c standard kern/kern_dtrace.c optional kdtrace_hooks kern/kern_dump.c standard kern/kern_environment.c standard kern/kern_et.c standard kern/kern_event.c standard kern/kern_exec.c standard kern/kern_exit.c standard kern/kern_fail.c standard kern/kern_ffclock.c standard kern/kern_fork.c standard kern/kern_gzio.c optional gzio kern/kern_hhook.c standard kern/kern_idle.c standard kern/kern_intr.c standard kern/kern_jail.c standard kern/kern_khelp.c standard kern/kern_kthread.c standard kern/kern_ktr.c optional ktr kern/kern_ktrace.c standard kern/kern_linker.c standard kern/kern_lock.c standard kern/kern_lockf.c standard kern/kern_lockstat.c optional kdtrace_hooks kern/kern_loginclass.c standard kern/kern_malloc.c standard kern/kern_mbuf.c standard kern/kern_mib.c standard kern/kern_module.c standard kern/kern_mtxpool.c standard kern/kern_mutex.c standard kern/kern_ntptime.c standard kern/kern_osd.c standard kern/kern_physio.c standard kern/kern_pmc.c standard kern/kern_poll.c optional device_polling kern/kern_priv.c standard kern/kern_proc.c standard kern/kern_procctl.c standard kern/kern_prot.c standard kern/kern_racct.c standard kern/kern_rangelock.c standard kern/kern_rctl.c standard kern/kern_resource.c standard kern/kern_rmlock.c standard kern/kern_rwlock.c standard kern/kern_sdt.c optional kdtrace_hooks kern/kern_sema.c standard kern/kern_sharedpage.c standard kern/kern_shutdown.c standard kern/kern_sig.c standard kern/kern_switch.c standard kern/kern_sx.c standard kern/kern_synch.c standard kern/kern_syscalls.c standard kern/kern_sysctl.c standard kern/kern_tc.c standard kern/kern_thr.c standard kern/kern_thread.c standard kern/kern_time.c standard kern/kern_timeout.c standard kern/kern_umtx.c standard kern/kern_uuid.c standard kern/kern_xxx.c standard kern/link_elf.c standard kern/linker_if.m standard kern/md4c.c optional netsmb kern/md5c.c standard kern/p1003_1b.c standard kern/posix4_mib.c standard kern/sched_4bsd.c optional sched_4bsd kern/sched_ule.c optional sched_ule kern/serdev_if.m standard kern/stack_protector.c standard \ compile-with "${NORMAL_C:N-fstack-protector*}" kern/subr_acl_nfs4.c optional ufs_acl | zfs kern/subr_acl_posix1e.c optional ufs_acl kern/subr_autoconf.c standard kern/subr_blist.c standard kern/subr_bus.c standard kern/subr_bus_dma.c standard kern/subr_bufring.c standard kern/subr_capability.c standard kern/subr_clock.c standard kern/subr_counter.c standard kern/subr_devstat.c standard kern/subr_disk.c standard kern/subr_dnvlist.c standard kern/subr_eventhandler.c standard kern/subr_fattime.c standard kern/subr_firmware.c optional firmware kern/subr_hash.c standard kern/subr_hints.c standard kern/subr_kdb.c standard kern/subr_kobj.c standard kern/subr_lock.c standard kern/subr_log.c standard kern/subr_mbpool.c optional libmbpool kern/subr_mchain.c optional libmchain kern/subr_module.c standard kern/subr_msgbuf.c standard kern/subr_nvlist.c standard kern/subr_nvpair.c standard kern/subr_param.c standard kern/subr_pcpu.c standard kern/subr_pctrie.c standard kern/subr_power.c standard kern/subr_prf.c standard kern/subr_prof.c standard kern/subr_rman.c standard kern/subr_rtc.c standard kern/subr_sbuf.c standard kern/subr_scanf.c standard kern/subr_sglist.c standard kern/subr_sleepqueue.c standard kern/subr_smp.c standard kern/subr_stack.c optional ddb | stack | ktr kern/subr_taskqueue.c standard kern/subr_terminal.c optional vt kern/subr_trap.c standard kern/subr_turnstile.c standard kern/subr_uio.c standard kern/subr_unit.c standard kern/subr_vmem.c standard kern/subr_witness.c optional witness kern/sys_capability.c standard kern/sys_generic.c standard kern/sys_pipe.c standard kern/sys_procdesc.c standard kern/sys_process.c standard kern/sys_socket.c standard kern/syscalls.c standard kern/sysv_ipc.c standard kern/sysv_msg.c optional sysvmsg kern/sysv_sem.c optional sysvsem kern/sysv_shm.c optional sysvshm kern/tty.c standard kern/tty_compat.c optional compat_43tty kern/tty_info.c standard kern/tty_inq.c standard kern/tty_outq.c standard kern/tty_pts.c standard kern/tty_tty.c standard kern/tty_ttydisc.c standard kern/uipc_accf.c standard kern/uipc_debug.c optional ddb kern/uipc_domain.c standard kern/uipc_mbuf.c standard kern/uipc_mbuf2.c standard kern/uipc_mbufhash.c standard kern/uipc_mqueue.c optional p1003_1b_mqueue kern/uipc_sem.c optional p1003_1b_semaphores kern/uipc_shm.c standard kern/uipc_sockbuf.c standard kern/uipc_socket.c standard kern/uipc_syscalls.c standard kern/uipc_usrreq.c standard kern/vfs_acl.c standard kern/vfs_aio.c optional vfs_aio kern/vfs_bio.c standard kern/vfs_cache.c standard kern/vfs_cluster.c standard kern/vfs_default.c standard kern/vfs_export.c standard kern/vfs_extattr.c standard kern/vfs_hash.c standard kern/vfs_init.c standard kern/vfs_lookup.c standard kern/vfs_mount.c standard kern/vfs_mountroot.c standard kern/vfs_subr.c standard kern/vfs_syscalls.c standard kern/vfs_vnops.c standard # # Kernel GSS-API # gssd.h optional kgssapi \ dependency "$S/kgssapi/gssd.x" \ compile-with "RPCGEN_CPP='${CPP}' rpcgen -hM $S/kgssapi/gssd.x | grep -v pthread.h > gssd.h" \ no-obj no-implicit-rule before-depend local \ clean "gssd.h" gssd_xdr.c optional kgssapi \ dependency "$S/kgssapi/gssd.x gssd.h" \ compile-with "RPCGEN_CPP='${CPP}' rpcgen -c $S/kgssapi/gssd.x -o gssd_xdr.c" \ no-implicit-rule before-depend local \ clean "gssd_xdr.c" gssd_clnt.c optional kgssapi \ dependency "$S/kgssapi/gssd.x gssd.h" \ compile-with "RPCGEN_CPP='${CPP}' rpcgen -lM $S/kgssapi/gssd.x | grep -v string.h > gssd_clnt.c" \ no-implicit-rule before-depend local \ clean "gssd_clnt.c" kgssapi/gss_accept_sec_context.c optional kgssapi kgssapi/gss_add_oid_set_member.c optional kgssapi kgssapi/gss_acquire_cred.c optional kgssapi kgssapi/gss_canonicalize_name.c optional kgssapi kgssapi/gss_create_empty_oid_set.c optional kgssapi kgssapi/gss_delete_sec_context.c optional kgssapi kgssapi/gss_display_status.c optional kgssapi kgssapi/gss_export_name.c optional kgssapi kgssapi/gss_get_mic.c optional kgssapi kgssapi/gss_init_sec_context.c optional kgssapi kgssapi/gss_impl.c optional kgssapi kgssapi/gss_import_name.c optional kgssapi kgssapi/gss_names.c optional kgssapi kgssapi/gss_pname_to_uid.c optional kgssapi kgssapi/gss_release_buffer.c optional kgssapi kgssapi/gss_release_cred.c optional kgssapi kgssapi/gss_release_name.c optional kgssapi kgssapi/gss_release_oid_set.c optional kgssapi kgssapi/gss_set_cred_option.c optional kgssapi kgssapi/gss_test_oid_set_member.c optional kgssapi kgssapi/gss_unwrap.c optional kgssapi kgssapi/gss_verify_mic.c optional kgssapi kgssapi/gss_wrap.c optional kgssapi kgssapi/gss_wrap_size_limit.c optional kgssapi kgssapi/gssd_prot.c optional kgssapi kgssapi/krb5/krb5_mech.c optional kgssapi kgssapi/krb5/kcrypto.c optional kgssapi kgssapi/krb5/kcrypto_aes.c optional kgssapi kgssapi/krb5/kcrypto_arcfour.c optional kgssapi kgssapi/krb5/kcrypto_des.c optional kgssapi kgssapi/krb5/kcrypto_des3.c optional kgssapi kgssapi/kgss_if.m optional kgssapi kgssapi/gsstest.c optional kgssapi_debug # These files in libkern/ are those needed by all architectures. Some # of the files in libkern/ are only needed on some architectures, e.g., # libkern/divdi3.c is needed by i386 but not alpha. Also, some of these # routines may be optimized for a particular platform. In either case, # the file should be moved to conf/files. from here. # libkern/arc4random.c standard libkern/asprintf.c standard libkern/bcd.c standard libkern/bsearch.c standard libkern/crc32.c standard libkern/explicit_bzero.c standard libkern/fnmatch.c standard libkern/iconv.c optional libiconv libkern/iconv_converter_if.m optional libiconv libkern/iconv_ucs.c optional libiconv libkern/iconv_xlat.c optional libiconv libkern/iconv_xlat16.c optional libiconv libkern/inet_aton.c standard libkern/inet_ntoa.c standard libkern/inet_ntop.c standard libkern/inet_pton.c standard libkern/jenkins_hash.c standard libkern/murmur3_32.c standard libkern/mcount.c optional profiling-routine libkern/memcchr.c standard libkern/memchr.c standard libkern/memcmp.c standard libkern/memmem.c optional gdb libkern/qsort.c standard libkern/qsort_r.c standard libkern/random.c standard libkern/scanc.c standard libkern/strcasecmp.c standard libkern/strcat.c standard libkern/strchr.c standard libkern/strcmp.c standard libkern/strcpy.c standard libkern/strcspn.c standard libkern/strdup.c standard libkern/strndup.c standard libkern/strlcat.c standard libkern/strlcpy.c standard libkern/strlen.c standard libkern/strncmp.c standard libkern/strncpy.c standard libkern/strnlen.c standard libkern/strrchr.c standard libkern/strsep.c standard libkern/strspn.c standard libkern/strstr.c standard libkern/strtol.c standard libkern/strtoq.c standard libkern/strtoul.c standard libkern/strtouq.c standard libkern/strvalid.c standard libkern/timingsafe_bcmp.c standard libkern/zlib.c optional crypto | geom_uzip | ipsec | \ mxge | netgraph_deflate | \ ddb_ctf | gzio | geom_uncompress net/altq/altq_cbq.c optional altq net/altq/altq_cdnr.c optional altq net/altq/altq_hfsc.c optional altq net/altq/altq_priq.c optional altq net/altq/altq_red.c optional altq net/altq/altq_rio.c optional altq net/altq/altq_rmclass.c optional altq net/altq/altq_subr.c optional altq net/bpf.c standard net/bpf_buffer.c optional bpf net/bpf_jitter.c optional bpf_jitter net/bpf_filter.c optional bpf | netgraph_bpf net/bpf_zerocopy.c optional bpf net/bridgestp.c optional bridge | if_bridge net/flowtable.c optional flowtable inet | flowtable inet6 net/ieee8023ad_lacp.c optional lagg net/if.c standard net/if_arcsubr.c optional arcnet net/if_atmsubr.c optional atm net/if_bridge.c optional bridge inet | if_bridge inet net/if_clone.c standard net/if_dead.c standard net/if_debug.c optional ddb net/if_disc.c optional disc net/if_edsc.c optional edsc net/if_enc.c optional enc ipsec inet | enc ipsec inet6 net/if_epair.c optional epair net/if_ethersubr.c optional ether net/if_fddisubr.c optional fddi net/if_fwsubr.c optional fwip net/if_gif.c optional gif inet | gif inet6 | \ netgraph_gif inet | netgraph_gif inet6 net/if_gre.c optional gre inet | gre inet6 net/if_iso88025subr.c optional token net/if_lagg.c optional lagg net/if_loop.c optional loop net/if_llatbl.c standard net/if_me.c optional me inet net/if_media.c standard net/if_mib.c standard net/if_spppfr.c optional sppp | netgraph_sppp net/if_spppsubr.c optional sppp | netgraph_sppp net/if_stf.c optional stf inet inet6 net/if_tun.c optional tun net/if_tap.c optional tap net/if_vlan.c optional vlan net/if_vxlan.c optional vxlan inet | vxlan inet6 net/mppcc.c optional netgraph_mppc_compression net/mppcd.c optional netgraph_mppc_compression net/netisr.c standard net/pfil.c optional ether | inet net/radix.c standard net/radix_mpath.c standard net/raw_cb.c standard net/raw_usrreq.c standard net/route.c standard net/rss_config.c optional inet rss | inet6 rss net/rtsock.c standard net/slcompress.c optional netgraph_vjc | sppp | \ netgraph_sppp net/toeplitz.c optional inet rss | inet6 rss net/vnet.c optional vimage net80211/ieee80211.c optional wlan net80211/ieee80211_acl.c optional wlan wlan_acl net80211/ieee80211_action.c optional wlan net80211/ieee80211_ageq.c optional wlan net80211/ieee80211_adhoc.c optional wlan \ compile-with "${NORMAL_C} -Wno-unused-function" net80211/ieee80211_ageq.c optional wlan net80211/ieee80211_amrr.c optional wlan | wlan_amrr net80211/ieee80211_crypto.c optional wlan \ compile-with "${NORMAL_C} -Wno-unused-function" net80211/ieee80211_crypto_ccmp.c optional wlan wlan_ccmp net80211/ieee80211_crypto_none.c optional wlan net80211/ieee80211_crypto_tkip.c optional wlan wlan_tkip net80211/ieee80211_crypto_wep.c optional wlan wlan_wep net80211/ieee80211_ddb.c optional wlan ddb net80211/ieee80211_dfs.c optional wlan net80211/ieee80211_freebsd.c optional wlan net80211/ieee80211_hostap.c optional wlan \ compile-with "${NORMAL_C} -Wno-unused-function" net80211/ieee80211_ht.c optional wlan net80211/ieee80211_hwmp.c optional wlan ieee80211_support_mesh net80211/ieee80211_input.c optional wlan net80211/ieee80211_ioctl.c optional wlan net80211/ieee80211_mesh.c optional wlan ieee80211_support_mesh \ compile-with "${NORMAL_C} -Wno-unused-function" net80211/ieee80211_monitor.c optional wlan net80211/ieee80211_node.c optional wlan net80211/ieee80211_output.c optional wlan net80211/ieee80211_phy.c optional wlan net80211/ieee80211_power.c optional wlan net80211/ieee80211_proto.c optional wlan net80211/ieee80211_radiotap.c optional wlan net80211/ieee80211_ratectl.c optional wlan net80211/ieee80211_ratectl_none.c optional wlan net80211/ieee80211_regdomain.c optional wlan net80211/ieee80211_rssadapt.c optional wlan wlan_rssadapt net80211/ieee80211_scan.c optional wlan net80211/ieee80211_scan_sta.c optional wlan net80211/ieee80211_sta.c optional wlan \ compile-with "${NORMAL_C} -Wno-unused-function" net80211/ieee80211_superg.c optional wlan ieee80211_support_superg net80211/ieee80211_scan_sw.c optional wlan net80211/ieee80211_tdma.c optional wlan ieee80211_support_tdma net80211/ieee80211_wds.c optional wlan net80211/ieee80211_xauth.c optional wlan wlan_xauth net80211/ieee80211_alq.c optional wlan ieee80211_alq netgraph/atm/ccatm/ng_ccatm.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" netgraph/atm/ng_atm.c optional ngatm_atm netgraph/atm/ngatmbase.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" netgraph/atm/sscfu/ng_sscfu.c optional ngatm_sscfu \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" netgraph/atm/sscop/ng_sscop.c optional ngatm_sscop \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" netgraph/atm/uni/ng_uni.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" netgraph/bluetooth/common/ng_bluetooth.c optional netgraph_bluetooth netgraph/bluetooth/drivers/bt3c/ng_bt3c_pccard.c optional netgraph_bluetooth_bt3c netgraph/bluetooth/drivers/h4/ng_h4.c optional netgraph_bluetooth_h4 netgraph/bluetooth/drivers/ubt/ng_ubt.c optional netgraph_bluetooth_ubt usb netgraph/bluetooth/drivers/ubtbcmfw/ubtbcmfw.c optional netgraph_bluetooth_ubtbcmfw usb netgraph/bluetooth/hci/ng_hci_cmds.c optional netgraph_bluetooth_hci netgraph/bluetooth/hci/ng_hci_evnt.c optional netgraph_bluetooth_hci netgraph/bluetooth/hci/ng_hci_main.c optional netgraph_bluetooth_hci netgraph/bluetooth/hci/ng_hci_misc.c optional netgraph_bluetooth_hci netgraph/bluetooth/hci/ng_hci_ulpi.c optional netgraph_bluetooth_hci netgraph/bluetooth/l2cap/ng_l2cap_cmds.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/l2cap/ng_l2cap_evnt.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/l2cap/ng_l2cap_llpi.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/l2cap/ng_l2cap_main.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/l2cap/ng_l2cap_misc.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/l2cap/ng_l2cap_ulpi.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/socket/ng_btsocket.c optional netgraph_bluetooth_socket netgraph/bluetooth/socket/ng_btsocket_hci_raw.c optional netgraph_bluetooth_socket netgraph/bluetooth/socket/ng_btsocket_l2cap.c optional netgraph_bluetooth_socket netgraph/bluetooth/socket/ng_btsocket_l2cap_raw.c optional netgraph_bluetooth_socket netgraph/bluetooth/socket/ng_btsocket_rfcomm.c optional netgraph_bluetooth_socket netgraph/bluetooth/socket/ng_btsocket_sco.c optional netgraph_bluetooth_socket netgraph/netflow/netflow.c optional netgraph_netflow netgraph/netflow/netflow_v9.c optional netgraph_netflow netgraph/netflow/ng_netflow.c optional netgraph_netflow netgraph/ng_UI.c optional netgraph_UI netgraph/ng_async.c optional netgraph_async netgraph/ng_atmllc.c optional netgraph_atmllc netgraph/ng_base.c optional netgraph netgraph/ng_bpf.c optional netgraph_bpf netgraph/ng_bridge.c optional netgraph_bridge netgraph/ng_car.c optional netgraph_car netgraph/ng_cisco.c optional netgraph_cisco netgraph/ng_deflate.c optional netgraph_deflate netgraph/ng_device.c optional netgraph_device netgraph/ng_echo.c optional netgraph_echo netgraph/ng_eiface.c optional netgraph_eiface netgraph/ng_ether.c optional netgraph_ether netgraph/ng_ether_echo.c optional netgraph_ether_echo netgraph/ng_frame_relay.c optional netgraph_frame_relay netgraph/ng_gif.c optional netgraph_gif inet6 | netgraph_gif inet netgraph/ng_gif_demux.c optional netgraph_gif_demux netgraph/ng_hole.c optional netgraph_hole netgraph/ng_iface.c optional netgraph_iface netgraph/ng_ip_input.c optional netgraph_ip_input netgraph/ng_ipfw.c optional netgraph_ipfw inet ipfirewall netgraph/ng_ksocket.c optional netgraph_ksocket netgraph/ng_l2tp.c optional netgraph_l2tp netgraph/ng_lmi.c optional netgraph_lmi netgraph/ng_mppc.c optional netgraph_mppc_compression | \ netgraph_mppc_encryption netgraph/ng_nat.c optional netgraph_nat inet libalias netgraph/ng_one2many.c optional netgraph_one2many netgraph/ng_parse.c optional netgraph netgraph/ng_patch.c optional netgraph_patch netgraph/ng_pipe.c optional netgraph_pipe netgraph/ng_ppp.c optional netgraph_ppp netgraph/ng_pppoe.c optional netgraph_pppoe netgraph/ng_pptpgre.c optional netgraph_pptpgre netgraph/ng_pred1.c optional netgraph_pred1 netgraph/ng_rfc1490.c optional netgraph_rfc1490 netgraph/ng_socket.c optional netgraph_socket netgraph/ng_split.c optional netgraph_split netgraph/ng_sppp.c optional netgraph_sppp netgraph/ng_tag.c optional netgraph_tag netgraph/ng_tcpmss.c optional netgraph_tcpmss netgraph/ng_tee.c optional netgraph_tee netgraph/ng_tty.c optional netgraph_tty netgraph/ng_vjc.c optional netgraph_vjc netgraph/ng_vlan.c optional netgraph_vlan netinet/accf_data.c optional accept_filter_data inet netinet/accf_dns.c optional accept_filter_dns inet netinet/accf_http.c optional accept_filter_http inet netinet/if_atm.c optional atm netinet/if_ether.c optional inet ether netinet/igmp.c optional inet netinet/in.c optional inet netinet/in_debug.c optional inet ddb netinet/in_kdtrace.c optional inet | inet6 netinet/ip_carp.c optional inet carp | inet6 carp netinet/in_gif.c optional gif inet | netgraph_gif inet netinet/ip_gre.c optional gre inet netinet/ip_id.c optional inet netinet/in_mcast.c optional inet netinet/in_pcb.c optional inet | inet6 netinet/in_pcbgroup.c optional inet pcbgroup | inet6 pcbgroup netinet/in_proto.c optional inet | inet6 netinet/in_rmx.c optional inet netinet/in_rss.c optional inet rss netinet/ip_divert.c optional inet ipdivert ipfirewall netinet/ip_ecn.c optional inet | inet6 netinet/ip_encap.c optional inet | inet6 netinet/ip_fastfwd.c optional inet netinet/ip_icmp.c optional inet | inet6 netinet/ip_input.c optional inet netinet/ip_ipsec.c optional inet ipsec netinet/ip_mroute.c optional mrouting inet netinet/ip_options.c optional inet netinet/ip_output.c optional inet netinet/ip_reass.c optional inet netinet/raw_ip.c optional inet | inet6 netinet/cc/cc.c optional inet | inet6 netinet/cc/cc_newreno.c optional inet | inet6 netinet/sctp_asconf.c optional inet sctp | inet6 sctp netinet/sctp_auth.c optional inet sctp | inet6 sctp netinet/sctp_bsd_addr.c optional inet sctp | inet6 sctp netinet/sctp_cc_functions.c optional inet sctp | inet6 sctp netinet/sctp_crc32.c optional inet sctp | inet6 sctp netinet/sctp_indata.c optional inet sctp | inet6 sctp netinet/sctp_input.c optional inet sctp | inet6 sctp netinet/sctp_output.c optional inet sctp | inet6 sctp netinet/sctp_pcb.c optional inet sctp | inet6 sctp netinet/sctp_peeloff.c optional inet sctp | inet6 sctp netinet/sctp_ss_functions.c optional inet sctp | inet6 sctp netinet/sctp_syscalls.c optional inet sctp | inet6 sctp netinet/sctp_sysctl.c optional inet sctp | inet6 sctp netinet/sctp_timer.c optional inet sctp | inet6 sctp netinet/sctp_usrreq.c optional inet sctp | inet6 sctp netinet/sctputil.c optional inet sctp | inet6 sctp netinet/siftr.c optional inet siftr alq | inet6 siftr alq netinet/tcp_debug.c optional tcpdebug netinet/tcp_hostcache.c optional inet | inet6 netinet/tcp_input.c optional inet | inet6 netinet/tcp_lro.c optional inet | inet6 netinet/tcp_output.c optional inet | inet6 netinet/tcp_offload.c optional tcp_offload inet | tcp_offload inet6 netinet/tcp_reass.c optional inet | inet6 netinet/tcp_sack.c optional inet | inet6 netinet/tcp_subr.c optional inet | inet6 netinet/tcp_syncache.c optional inet | inet6 netinet/tcp_timer.c optional inet | inet6 netinet/tcp_timewait.c optional inet | inet6 netinet/tcp_usrreq.c optional inet | inet6 netinet/udp_usrreq.c optional inet | inet6 netinet/libalias/alias.c optional libalias inet | netgraph_nat inet netinet/libalias/alias_db.c optional libalias inet | netgraph_nat inet netinet/libalias/alias_mod.c optional libalias | netgraph_nat netinet/libalias/alias_proxy.c optional libalias inet | netgraph_nat inet netinet/libalias/alias_util.c optional libalias inet | netgraph_nat inet netinet/libalias/alias_sctp.c optional libalias inet | netgraph_nat inet netinet6/dest6.c optional inet6 netinet6/frag6.c optional inet6 netinet6/icmp6.c optional inet6 netinet6/in6.c optional inet6 netinet6/in6_cksum.c optional inet6 netinet6/in6_gif.c optional gif inet6 | netgraph_gif inet6 netinet6/in6_ifattach.c optional inet6 netinet6/in6_mcast.c optional inet6 netinet6/in6_pcb.c optional inet6 netinet6/in6_pcbgroup.c optional inet6 pcbgroup netinet6/in6_proto.c optional inet6 netinet6/in6_rmx.c optional inet6 netinet6/in6_rss.c optional inet6 rss netinet6/in6_src.c optional inet6 netinet6/ip6_forward.c optional inet6 netinet6/ip6_gre.c optional gre inet6 netinet6/ip6_id.c optional inet6 netinet6/ip6_input.c optional inet6 netinet6/ip6_mroute.c optional mrouting inet6 netinet6/ip6_output.c optional inet6 netinet6/ip6_ipsec.c optional inet6 ipsec netinet6/mld6.c optional inet6 netinet6/nd6.c optional inet6 netinet6/nd6_nbr.c optional inet6 netinet6/nd6_rtr.c optional inet6 netinet6/raw_ip6.c optional inet6 netinet6/route6.c optional inet6 netinet6/scope6.c optional inet6 netinet6/sctp6_usrreq.c optional inet6 sctp netinet6/udp6_usrreq.c optional inet6 netipsec/ipsec.c optional ipsec inet | ipsec inet6 netipsec/ipsec_input.c optional ipsec inet | ipsec inet6 netipsec/ipsec_mbuf.c optional ipsec inet | ipsec inet6 netipsec/ipsec_output.c optional ipsec inet | ipsec inet6 netipsec/key.c optional ipsec inet | ipsec inet6 netipsec/key_debug.c optional ipsec inet | ipsec inet6 netipsec/keysock.c optional ipsec inet | ipsec inet6 netipsec/xform_ah.c optional ipsec inet | ipsec inet6 netipsec/xform_esp.c optional ipsec inet | ipsec inet6 netipsec/xform_ipcomp.c optional ipsec inet | ipsec inet6 netipsec/xform_tcp.c optional ipsec inet tcp_signature | \ ipsec inet6 tcp_signature netnatm/natm.c optional natm netnatm/natm_pcb.c optional natm netnatm/natm_proto.c optional natm netpfil/ipfw/dn_heap.c optional inet dummynet netpfil/ipfw/dn_sched_fifo.c optional inet dummynet netpfil/ipfw/dn_sched_prio.c optional inet dummynet netpfil/ipfw/dn_sched_qfq.c optional inet dummynet netpfil/ipfw/dn_sched_rr.c optional inet dummynet netpfil/ipfw/dn_sched_wf2q.c optional inet dummynet netpfil/ipfw/ip_dummynet.c optional inet dummynet netpfil/ipfw/ip_dn_io.c optional inet dummynet netpfil/ipfw/ip_dn_glue.c optional inet dummynet netpfil/ipfw/ip_fw2.c optional inet ipfirewall netpfil/ipfw/ip_fw_dynamic.c optional inet ipfirewall netpfil/ipfw/ip_fw_log.c optional inet ipfirewall netpfil/ipfw/ip_fw_pfil.c optional inet ipfirewall netpfil/ipfw/ip_fw_sockopt.c optional inet ipfirewall netpfil/ipfw/ip_fw_table.c optional inet ipfirewall netpfil/ipfw/ip_fw_table_algo.c optional inet ipfirewall netpfil/ipfw/ip_fw_table_value.c optional inet ipfirewall netpfil/ipfw/ip_fw_iface.c optional inet ipfirewall netpfil/ipfw/ip_fw_nat.c optional inet ipfirewall_nat netpfil/pf/if_pflog.c optional pflog pf inet netpfil/pf/if_pfsync.c optional pfsync pf inet netpfil/pf/pf.c optional pf inet netpfil/pf/pf_if.c optional pf inet netpfil/pf/pf_ioctl.c optional pf inet netpfil/pf/pf_lb.c optional pf inet netpfil/pf/pf_norm.c optional pf inet netpfil/pf/pf_osfp.c optional pf inet netpfil/pf/pf_ruleset.c optional pf inet netpfil/pf/pf_table.c optional pf inet netpfil/pf/in4_cksum.c optional pf inet netsmb/smb_conn.c optional netsmb netsmb/smb_crypt.c optional netsmb netsmb/smb_dev.c optional netsmb netsmb/smb_iod.c optional netsmb netsmb/smb_rq.c optional netsmb netsmb/smb_smb.c optional netsmb netsmb/smb_subr.c optional netsmb netsmb/smb_trantcp.c optional netsmb netsmb/smb_usr.c optional netsmb nfs/bootp_subr.c optional bootp nfscl nfs/krpc_subr.c optional bootp nfscl nfs/nfs_diskless.c optional nfscl nfs_root nfs/nfs_fha.c optional nfsd nfs/nfs_lock.c optional nfscl | nfslockd | nfsd nfs/nfs_nfssvc.c optional nfscl | nfsd nlm/nlm_advlock.c optional nfslockd | nfsd nlm/nlm_prot_clnt.c optional nfslockd | nfsd nlm/nlm_prot_impl.c optional nfslockd | nfsd nlm/nlm_prot_server.c optional nfslockd | nfsd nlm/nlm_prot_svc.c optional nfslockd | nfsd nlm/nlm_prot_xdr.c optional nfslockd | nfsd nlm/sm_inter_xdr.c optional nfslockd | nfsd # Linux Kernel Compatibility API ofed/include/linux/linux_kmod.c optional ofed | compat_linuxapi \ no-depend compile-with "${OFED_C}" ofed/include/linux/linux_compat.c optional ofed | compat_linuxapi \ no-depend compile-with "${OFED_C}" ofed/include/linux/linux_pci.c optional ofed | compat_linuxapi \ no-depend compile-with "${OFED_C}" ofed/include/linux/linux_idr.c optional ofed | compat_linuxapi \ no-depend compile-with "${OFED_C}" ofed/include/linux/linux_radix.c optional ofed | compat_linuxapi \ no-depend compile-with "${OFED_C}" # OpenFabrics Enterprise Distribution (Infiniband) ofed/drivers/infiniband/core/addr.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/agent.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/cache.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" # XXX Mad.c must be ordered before cm.c for sysinit sets to occur in # the correct order. ofed/drivers/infiniband/core/mad.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/cm.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/ -Wno-unused-function" ofed/drivers/infiniband/core/cma.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/device.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/fmr_pool.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/iwcm.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/mad_rmpp.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/multicast.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/packer.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/peer_mem.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/sa_query.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/smi.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/sysfs.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/ucm.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/ucma.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/ud_header.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/umem.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/user_mad.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/uverbs_cmd.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/uverbs_main.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/uverbs_marshall.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/core/verbs.c optional ofed \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/" ofed/drivers/infiniband/ulp/ipoib/ipoib_cm.c optional ipoib \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/" #ofed/drivers/infiniband/ulp/ipoib/ipoib_fs.c optional ipoib \ # no-depend \ # compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/" ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c optional ipoib \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/" ofed/drivers/infiniband/ulp/ipoib/ipoib_main.c optional ipoib \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/" ofed/drivers/infiniband/ulp/ipoib/ipoib_multicast.c optional ipoib \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/" ofed/drivers/infiniband/ulp/ipoib/ipoib_verbs.c optional ipoib \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/" #ofed/drivers/infiniband/ulp/ipoib/ipoib_vlan.c optional ipoib \ # no-depend \ # compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/" ofed/drivers/infiniband/ulp/sdp/sdp_bcopy.c optional sdp inet \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/" ofed/drivers/infiniband/ulp/sdp/sdp_main.c optional sdp inet \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/" ofed/drivers/infiniband/ulp/sdp/sdp_rx.c optional sdp inet \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/" ofed/drivers/infiniband/ulp/sdp/sdp_cma.c optional sdp inet \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/" ofed/drivers/infiniband/ulp/sdp/sdp_tx.c optional sdp inet \ no-depend \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/" ofed/drivers/infiniband/hw/mlx4/alias_GUID.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/mcg.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/sysfs.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/cm.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/ah.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/cq.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/doorbell.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/mad.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/main.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/mlx4_exp.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/mr.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/qp.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/srq.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/infiniband/hw/mlx4/wc.c optional mlx4ib \ no-depend obj-prefix "mlx4ib_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/infiniband/hw/mlx4/" ofed/drivers/net/mlx4/alloc.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/catas.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/cmd.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/cq.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/eq.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/fw.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/icm.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/intf.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/main.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/mcg.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/ -Wno-unused" ofed/drivers/net/mlx4/mr.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/pd.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/port.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/profile.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/qp.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/reset.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/sense.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/srq.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/resource_tracker.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/sys_tune.c optional mlx4ib | mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/en_cq.c optional mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/en_main.c optional mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/en_netdev.c optional mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/en_port.c optional mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/en_resources.c optional mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/en_rx.c optional mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/net/mlx4/en_tx.c optional mlxen \ no-depend obj-prefix "mlx4_" \ compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/" ofed/drivers/infiniband/hw/mthca/mthca_allocator.c optional mthca \ no-depend compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_av.c optional mthca \ no-depend compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_catas.c optional mthca \ no-depend compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_cmd.c optional mthca \ no-depend compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_cq.c optional mthca \ no-depend compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_eq.c optional mthca \ no-depend compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_mad.c optional mthca \ no-depend compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_main.c optional mthca \ no-depend compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_mcg.c optional mthca \ no-depend compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_memfree.c optional mthca \ no-depend compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_mr.c optional mthca \ no-depend compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_pd.c optional mthca \ no-depend compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_profile.c optional mthca \ no-depend compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_provider.c optional mthca \ no-depend compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_qp.c optional mthca \ no-depend compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_reset.c optional mthca \ no-depend compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_srq.c optional mthca \ no-depend compile-with "${OFED_C}" ofed/drivers/infiniband/hw/mthca/mthca_uar.c optional mthca \ no-depend compile-with "${OFED_C}" # crypto support opencrypto/cast.c optional crypto | ipsec opencrypto/criov.c optional crypto opencrypto/crypto.c optional crypto opencrypto/cryptodev.c optional cryptodev opencrypto/cryptodev_if.m optional crypto opencrypto/cryptosoft.c optional crypto opencrypto/cryptodeflate.c optional crypto opencrypto/gmac.c optional crypto opencrypto/gfmult.c optional crypto opencrypto/rmd160.c optional crypto | ipsec opencrypto/skipjack.c optional crypto opencrypto/xform.c optional crypto rpc/auth_none.c optional krpc | nfslockd | nfscl | nfsd rpc/auth_unix.c optional krpc | nfslockd | nfscl | nfsd rpc/authunix_prot.c optional krpc | nfslockd | nfscl | nfsd rpc/clnt_bck.c optional krpc | nfslockd | nfscl | nfsd rpc/clnt_dg.c optional krpc | nfslockd | nfscl | nfsd rpc/clnt_rc.c optional krpc | nfslockd | nfscl | nfsd rpc/clnt_vc.c optional krpc | nfslockd | nfscl | nfsd rpc/getnetconfig.c optional krpc | nfslockd | nfscl | nfsd rpc/replay.c optional krpc | nfslockd | nfscl | nfsd rpc/rpc_callmsg.c optional krpc | nfslockd | nfscl | nfsd rpc/rpc_generic.c optional krpc | nfslockd | nfscl | nfsd rpc/rpc_prot.c optional krpc | nfslockd | nfscl | nfsd rpc/rpcb_clnt.c optional krpc | nfslockd | nfscl | nfsd rpc/rpcb_prot.c optional krpc | nfslockd | nfscl | nfsd rpc/svc.c optional krpc | nfslockd | nfscl | nfsd rpc/svc_auth.c optional krpc | nfslockd | nfscl | nfsd rpc/svc_auth_unix.c optional krpc | nfslockd | nfscl | nfsd rpc/svc_dg.c optional krpc | nfslockd | nfscl | nfsd rpc/svc_generic.c optional krpc | nfslockd | nfscl | nfsd rpc/svc_vc.c optional krpc | nfslockd | nfscl | nfsd rpc/rpcsec_gss/rpcsec_gss.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi rpc/rpcsec_gss/rpcsec_gss_conf.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi rpc/rpcsec_gss/rpcsec_gss_misc.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi rpc/rpcsec_gss/rpcsec_gss_prot.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi rpc/rpcsec_gss/svc_rpcsec_gss.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi security/audit/audit.c optional audit security/audit/audit_arg.c optional audit security/audit/audit_bsm.c optional audit security/audit/audit_bsm_klib.c optional audit security/audit/audit_pipe.c optional audit security/audit/audit_syscalls.c standard security/audit/audit_trigger.c optional audit security/audit/audit_worker.c optional audit security/audit/bsm_domain.c optional audit security/audit/bsm_errno.c optional audit security/audit/bsm_fcntl.c optional audit security/audit/bsm_socket_type.c optional audit security/audit/bsm_token.c optional audit security/mac/mac_audit.c optional mac audit security/mac/mac_cred.c optional mac security/mac/mac_framework.c optional mac security/mac/mac_inet.c optional mac inet | mac inet6 security/mac/mac_inet6.c optional mac inet6 security/mac/mac_label.c optional mac security/mac/mac_net.c optional mac security/mac/mac_pipe.c optional mac security/mac/mac_posix_sem.c optional mac security/mac/mac_posix_shm.c optional mac security/mac/mac_priv.c optional mac security/mac/mac_process.c optional mac security/mac/mac_socket.c optional mac security/mac/mac_syscalls.c standard security/mac/mac_system.c optional mac security/mac/mac_sysv_msg.c optional mac security/mac/mac_sysv_sem.c optional mac security/mac/mac_sysv_shm.c optional mac security/mac/mac_vfs.c optional mac security/mac_biba/mac_biba.c optional mac_biba security/mac_bsdextended/mac_bsdextended.c optional mac_bsdextended security/mac_bsdextended/ugidfw_system.c optional mac_bsdextended security/mac_bsdextended/ugidfw_vnode.c optional mac_bsdextended security/mac_ifoff/mac_ifoff.c optional mac_ifoff security/mac_lomac/mac_lomac.c optional mac_lomac security/mac_mls/mac_mls.c optional mac_mls security/mac_none/mac_none.c optional mac_none security/mac_partition/mac_partition.c optional mac_partition security/mac_portacl/mac_portacl.c optional mac_portacl security/mac_seeotheruids/mac_seeotheruids.c optional mac_seeotheruids security/mac_stub/mac_stub.c optional mac_stub security/mac_test/mac_test.c optional mac_test teken/teken.c optional sc | vt ufs/ffs/ffs_alloc.c optional ffs ufs/ffs/ffs_balloc.c optional ffs ufs/ffs/ffs_inode.c optional ffs ufs/ffs/ffs_snapshot.c optional ffs ufs/ffs/ffs_softdep.c optional ffs ufs/ffs/ffs_subr.c optional ffs ufs/ffs/ffs_tables.c optional ffs ufs/ffs/ffs_vfsops.c optional ffs ufs/ffs/ffs_vnops.c optional ffs ufs/ffs/ffs_rawread.c optional ffs directio ufs/ffs/ffs_suspend.c optional ffs ufs/ufs/ufs_acl.c optional ffs ufs/ufs/ufs_bmap.c optional ffs ufs/ufs/ufs_dirhash.c optional ffs ufs/ufs/ufs_extattr.c optional ffs ufs/ufs/ufs_gjournal.c optional ffs UFS_GJOURNAL ufs/ufs/ufs_inode.c optional ffs ufs/ufs/ufs_lookup.c optional ffs ufs/ufs/ufs_quota.c optional ffs ufs/ufs/ufs_vfsops.c optional ffs ufs/ufs/ufs_vnops.c optional ffs vm/default_pager.c standard vm/device_pager.c standard vm/phys_pager.c standard vm/redzone.c optional DEBUG_REDZONE vm/sg_pager.c standard vm/swap_pager.c standard vm/uma_core.c standard vm/uma_dbg.c standard vm/memguard.c optional DEBUG_MEMGUARD vm/vm_fault.c standard vm/vm_glue.c standard vm/vm_init.c standard vm/vm_kern.c standard vm/vm_map.c standard vm/vm_meter.c standard vm/vm_mmap.c standard vm/vm_object.c standard vm/vm_page.c standard vm/vm_pageout.c standard vm/vm_pager.c standard vm/vm_phys.c standard vm/vm_radix.c standard vm/vm_reserv.c standard vm/vm_unix.c standard vm/vm_zeroidle.c standard vm/vnode_pager.c standard xen/features.c optional xenhvm xen/xenbus/xenbus_if.m optional xenhvm xen/xenbus/xenbus.c optional xenhvm xen/xenbus/xenbusb_if.m optional xenhvm xen/xenbus/xenbusb.c optional xenhvm xen/xenbus/xenbusb_front.c optional xenhvm xen/xenbus/xenbusb_back.c optional xenhvm xen/xenmem/xenmem_if.m optional xenhvm xdr/xdr.c optional krpc | nfslockd | nfscl | nfsd xdr/xdr_array.c optional krpc | nfslockd | nfscl | nfsd xdr/xdr_mbuf.c optional krpc | nfslockd | nfscl | nfsd xdr/xdr_mem.c optional krpc | nfslockd | nfscl | nfsd xdr/xdr_reference.c optional krpc | nfslockd | nfscl | nfsd xdr/xdr_sizeof.c optional krpc | nfslockd | nfscl | nfsd Index: head/sys/conf/files.amd64 =================================================================== --- head/sys/conf/files.amd64 (revision 283513) +++ head/sys/conf/files.amd64 (revision 283514) @@ -1,601 +1,616 @@ # This file tells config what files go into building a kernel, # files marked standard are always included. # # $FreeBSD$ # # The long compile-with and dependency lines are required because of # limitations in config: backslash-newline doesn't work in strings, and # dependency lines other than the first are silently ignored. # # linux32_genassym.o optional compat_linux32 \ dependency "$S/amd64/linux32/linux32_genassym.c" \ compile-with "${CC} ${CFLAGS:N-fno-common} -c ${.IMPSRC}" \ no-obj no-implicit-rule \ clean "linux32_genassym.o" # linux32_assym.h optional compat_linux32 \ dependency "$S/kern/genassym.sh linux32_genassym.o" \ compile-with "sh $S/kern/genassym.sh linux32_genassym.o > ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "linux32_assym.h" # linux32_locore.o optional compat_linux32 \ dependency "linux32_assym.h $S/amd64/linux32/linux32_locore.s" \ compile-with "${CC} -x assembler-with-cpp -DLOCORE -m32 -shared -s -pipe -I. -I$S -Werror -Wall -fno-common -nostdinc -nostdlib -Wl,-T$S/amd64/linux32/linux32_vdso.lds.s -Wl,-soname=linux32_vdso.so,--eh-frame-hdr,-fPIC,-warn-common ${.IMPSRC} -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "linux32_locore.o" # linux32_vdso.so optional compat_linux32 \ dependency "linux32_locore.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-x86-64-freebsd --binary-architecture i386 linux32_locore.o ${.TARGET}" \ no-implicit-rule \ clean "linux32_vdso.so" # ia32_genassym.o standard \ dependency "$S/compat/ia32/ia32_genassym.c" \ compile-with "${CC} ${CFLAGS:N-fno-common} -c ${.IMPSRC}" \ no-obj no-implicit-rule \ clean "ia32_genassym.o" # ia32_assym.h standard \ dependency "$S/kern/genassym.sh ia32_genassym.o" \ compile-with "env NM='${NM}' sh $S/kern/genassym.sh ia32_genassym.o > ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "ia32_assym.h" # font.h optional sc_dflt_font \ compile-with "uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x16.fnt && file2c 'static u_char dflt_font_16[16*256] = {' '};' < ${SC_DFLT_FONT}-8x16 > font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x14.fnt && file2c 'static u_char dflt_font_14[14*256] = {' '};' < ${SC_DFLT_FONT}-8x14 >> font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x8.fnt && file2c 'static u_char dflt_font_8[8*256] = {' '};' < ${SC_DFLT_FONT}-8x8 >> font.h" \ no-obj no-implicit-rule before-depend \ clean "font.h ${SC_DFLT_FONT}-8x14 ${SC_DFLT_FONT}-8x16 ${SC_DFLT_FONT}-8x8" # atkbdmap.h optional atkbd_dflt_keymap \ compile-with "/usr/sbin/kbdcontrol -L ${ATKBD_DFLT_KEYMAP} | sed -e 's/^static keymap_t.* = /static keymap_t key_map = /' -e 's/^static accentmap_t.* = /static accentmap_t accent_map = /' > atkbdmap.h" \ no-obj no-implicit-rule before-depend \ clean "atkbdmap.h" # ukbdmap.h optional ukbd_dflt_keymap \ compile-with "/usr/sbin/kbdcontrol -L ${UKBD_DFLT_KEYMAP} | sed -e 's/^static keymap_t.* = /static keymap_t key_map = /' -e 's/^static accentmap_t.* = /static accentmap_t accent_map = /' > ukbdmap.h" \ no-obj no-implicit-rule before-depend \ clean "ukbdmap.h" # hpt27xx_lib.o optional hpt27xx \ dependency "$S/dev/hpt27xx/amd64-elf.hpt27xx_lib.o.uu" \ compile-with "uudecode < $S/dev/hpt27xx/amd64-elf.hpt27xx_lib.o.uu" \ no-implicit-rule # hptmvraid.o optional hptmv \ dependency "$S/dev/hptmv/amd64-elf.raid.o.uu" \ compile-with "uudecode < $S/dev/hptmv/amd64-elf.raid.o.uu" \ no-implicit-rule # hptnr_lib.o optional hptnr \ dependency "$S/dev/hptnr/amd64-elf.hptnr_lib.o.uu" \ compile-with "uudecode < $S/dev/hptnr/amd64-elf.hptnr_lib.o.uu" \ no-implicit-rule # hptrr_lib.o optional hptrr \ dependency "$S/dev/hptrr/amd64-elf.hptrr_lib.o.uu" \ compile-with "uudecode < $S/dev/hptrr/amd64-elf.hptrr_lib.o.uu" \ no-implicit-rule # amd64/acpica/acpi_machdep.c optional acpi acpi_wakecode.o optional acpi \ dependency "$S/amd64/acpica/acpi_wakecode.S assym.s" \ compile-with "${NORMAL_S}" \ no-obj no-implicit-rule before-depend \ clean "acpi_wakecode.o" acpi_wakecode.bin optional acpi \ dependency "acpi_wakecode.o" \ compile-with "${OBJCOPY} -S -O binary acpi_wakecode.o ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "acpi_wakecode.bin" acpi_wakecode.h optional acpi \ dependency "acpi_wakecode.bin" \ compile-with "file2c -sx 'static char wakecode[] = {' '};' < acpi_wakecode.bin > ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "acpi_wakecode.h" acpi_wakedata.h optional acpi \ dependency "acpi_wakecode.o" \ compile-with '${NM} -n --defined-only acpi_wakecode.o | while read offset dummy what; do echo "#define $${what} 0x$${offset}"; done > ${.TARGET}' \ no-obj no-implicit-rule before-depend \ clean "acpi_wakedata.h" # amd64/amd64/amd64_mem.c optional mem #amd64/amd64/apic_vector.S standard amd64/amd64/atomic.c standard amd64/amd64/autoconf.c standard amd64/amd64/bios.c standard amd64/amd64/bpf_jit_machdep.c optional bpf_jitter amd64/amd64/cpu_switch.S standard amd64/amd64/db_disasm.c optional ddb amd64/amd64/db_interface.c optional ddb amd64/amd64/db_trace.c optional ddb amd64/amd64/elf_machdep.c standard amd64/amd64/exception.S standard amd64/amd64/fpu.c standard amd64/amd64/gdb_machdep.c optional gdb amd64/amd64/in_cksum.c optional inet | inet6 amd64/amd64/initcpu.c standard amd64/amd64/io.c optional io amd64/amd64/locore.S standard no-obj amd64/amd64/xen-locore.S optional xenhvm amd64/amd64/machdep.c standard amd64/amd64/mem.c optional mem amd64/amd64/minidump_machdep.c standard amd64/amd64/mp_machdep.c optional smp amd64/amd64/mp_watchdog.c optional mp_watchdog smp amd64/amd64/mpboot.S optional smp amd64/amd64/pmap.c standard amd64/amd64/prof_machdep.c optional profiling-routine amd64/amd64/ptrace_machdep.c standard amd64/amd64/sigtramp.S standard amd64/amd64/stack_machdep.c optional ddb | stack amd64/amd64/support.S standard amd64/amd64/sys_machdep.c standard amd64/amd64/trap.c standard amd64/amd64/uio_machdep.c standard amd64/amd64/uma_machdep.c standard amd64/amd64/vm_machdep.c standard amd64/pci/pci_cfgreg.c optional pci cddl/contrib/opensolaris/common/atomic/amd64/opensolaris_atomic.S optional zfs compile-with "${ZFS_S}" crypto/aesni/aeskeys_amd64.S optional aesni crypto/aesni/aesni.c optional aesni aesni_ghash.o optional aesni \ dependency "$S/crypto/aesni/aesni_ghash.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc} ${WERROR} ${NO_WCAST_QUAL} ${PROF} -mmmx -msse -msse4 -maes -mpclmul ${.IMPSRC}" \ no-implicit-rule \ clean "aesni_ghash.o" aesni_wrap.o optional aesni \ dependency "$S/crypto/aesni/aesni_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc} ${WERROR} ${NO_WCAST_QUAL} ${PROF} -mmmx -msse -msse4 -maes ${.IMPSRC}" \ no-implicit-rule \ clean "aesni_wrap.o" crypto/blowfish/bf_enc.c optional crypto | ipsec crypto/des/des_enc.c optional crypto | ipsec | netsmb crypto/via/padlock.c optional padlock crypto/via/padlock_cipher.c optional padlock crypto/via/padlock_hash.c optional padlock dev/acpica/acpi_if.m standard dev/acpica/acpi_hpet.c optional acpi dev/acpi_support/acpi_wmi_if.m standard dev/agp/agp_amd64.c optional agp dev/agp/agp_i810.c optional agp dev/agp/agp_via.c optional agp dev/amdsbwd/amdsbwd.c optional amdsbwd dev/amdtemp/amdtemp.c optional amdtemp dev/arcmsr/arcmsr.c optional arcmsr pci dev/asmc/asmc.c optional asmc isa dev/atkbdc/atkbd.c optional atkbd atkbdc dev/atkbdc/atkbd_atkbdc.c optional atkbd atkbdc dev/atkbdc/atkbdc.c optional atkbdc dev/atkbdc/atkbdc_isa.c optional atkbdc isa dev/atkbdc/atkbdc_subr.c optional atkbdc dev/atkbdc/psm.c optional psm atkbdc dev/bxe/bxe.c optional bxe pci dev/bxe/bxe_stats.c optional bxe pci dev/bxe/bxe_debug.c optional bxe pci dev/bxe/ecore_sp.c optional bxe pci dev/bxe/bxe_elink.c optional bxe pci dev/bxe/57710_init_values.c optional bxe pci dev/bxe/57711_init_values.c optional bxe pci dev/bxe/57712_init_values.c optional bxe pci dev/coretemp/coretemp.c optional coretemp dev/cpuctl/cpuctl.c optional cpuctl dev/dpms/dpms.c optional dpms # There are no systems with isa slots, so all ed isa entries should go.. dev/ed/if_ed_3c503.c optional ed isa ed_3c503 dev/ed/if_ed_isa.c optional ed isa dev/ed/if_ed_wd80x3.c optional ed isa dev/ed/if_ed_hpp.c optional ed isa ed_hpp dev/ed/if_ed_sic.c optional ed isa ed_sic dev/fb/fb.c optional fb | vga dev/fb/s3_pci.c optional s3pci dev/fb/vesa.c optional vga vesa dev/fb/vga.c optional vga dev/ichwd/ichwd.c optional ichwd dev/if_ndis/if_ndis.c optional ndis dev/if_ndis/if_ndis_pccard.c optional ndis pccard dev/if_ndis/if_ndis_pci.c optional ndis cardbus | ndis pci dev/if_ndis/if_ndis_usb.c optional ndis usb dev/io/iodev.c optional io dev/ipmi/ipmi.c optional ipmi dev/ipmi/ipmi_acpi.c optional ipmi acpi dev/ipmi/ipmi_isa.c optional ipmi isa dev/ipmi/ipmi_kcs.c optional ipmi dev/ipmi/ipmi_smic.c optional ipmi dev/ipmi/ipmi_smbus.c optional ipmi smbus dev/ipmi/ipmi_smbios.c optional ipmi dev/ipmi/ipmi_ssif.c optional ipmi smbus dev/ipmi/ipmi_pci.c optional ipmi pci dev/ipmi/ipmi_linux.c optional ipmi compat_linux32 dev/ixl/if_ixl.c optional ixl pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/if_ixlv.c optional ixlv pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/ixlvc.c optional ixlv pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/ixl_txrx.c optional ixl pci | ixlv pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/i40e_osdep.c optional ixl pci | ixlv pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/i40e_lan_hmc.c optional ixl pci | ixlv pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/i40e_hmc.c optional ixl pci | ixlv pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/i40e_common.c optional ixl pci | ixlv pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/i40e_nvm.c optional ixl pci | ixlv pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/i40e_adminq.c optional ixl pci | ixlv pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/fdc/fdc.c optional fdc dev/fdc/fdc_acpi.c optional fdc dev/fdc/fdc_isa.c optional fdc isa dev/fdc/fdc_pccard.c optional fdc pccard dev/fdt/fdt_x86.c optional fdt dev/hpt27xx/hpt27xx_os_bsd.c optional hpt27xx dev/hpt27xx/hpt27xx_osm_bsd.c optional hpt27xx dev/hpt27xx/hpt27xx_config.c optional hpt27xx dev/hptmv/entry.c optional hptmv dev/hptmv/mv.c optional hptmv dev/hptmv/gui_lib.c optional hptmv dev/hptmv/hptproc.c optional hptmv dev/hptmv/ioctl.c optional hptmv dev/hptnr/hptnr_os_bsd.c optional hptnr dev/hptnr/hptnr_osm_bsd.c optional hptnr dev/hptnr/hptnr_config.c optional hptnr dev/hptrr/hptrr_os_bsd.c optional hptrr dev/hptrr/hptrr_osm_bsd.c optional hptrr dev/hptrr/hptrr_config.c optional hptrr dev/hwpmc/hwpmc_amd.c optional hwpmc dev/hwpmc/hwpmc_intel.c optional hwpmc dev/hwpmc/hwpmc_core.c optional hwpmc dev/hwpmc/hwpmc_uncore.c optional hwpmc dev/hwpmc/hwpmc_piv.c optional hwpmc dev/hwpmc/hwpmc_tsc.c optional hwpmc dev/hwpmc/hwpmc_x86.c optional hwpmc dev/hyperv/netvsc/hv_net_vsc.c optional hyperv dev/hyperv/netvsc/hv_netvsc_drv_freebsd.c optional hyperv dev/hyperv/netvsc/hv_rndis_filter.c optional hyperv dev/hyperv/stordisengage/hv_ata_pci_disengage.c optional hyperv dev/hyperv/storvsc/hv_storvsc_drv_freebsd.c optional hyperv dev/hyperv/utilities/hv_kvp.c optional hyperv dev/hyperv/utilities/hv_util.c optional hyperv dev/hyperv/vmbus/hv_channel.c optional hyperv dev/hyperv/vmbus/hv_channel_mgmt.c optional hyperv dev/hyperv/vmbus/hv_connection.c optional hyperv dev/hyperv/vmbus/hv_hv.c optional hyperv dev/hyperv/vmbus/hv_ring_buffer.c optional hyperv dev/hyperv/vmbus/hv_vmbus_drv_freebsd.c optional hyperv dev/kbd/kbd.c optional atkbd | sc | ukbd | vt dev/nfe/if_nfe.c optional nfe pci dev/ntb/if_ntb/if_ntb.c optional if_ntb dev/ntb/ntb_hw/ntb_hw.c optional if_ntb ntb_hw dev/nvd/nvd.c optional nvd nvme dev/nvme/nvme.c optional nvme dev/nvme/nvme_ctrlr.c optional nvme dev/nvme/nvme_ctrlr_cmd.c optional nvme dev/nvme/nvme_ns.c optional nvme dev/nvme/nvme_ns_cmd.c optional nvme dev/nvme/nvme_qpair.c optional nvme dev/nvme/nvme_sysctl.c optional nvme dev/nvme/nvme_test.c optional nvme dev/nvme/nvme_util.c optional nvme dev/nvram/nvram.c optional nvram isa dev/random/ivy.c optional rdrand_rng dev/random/nehemiah.c optional padlock_rng dev/qlxge/qls_dbg.c optional qlxge pci dev/qlxge/qls_dump.c optional qlxge pci dev/qlxge/qls_hw.c optional qlxge pci dev/qlxge/qls_ioctl.c optional qlxge pci dev/qlxge/qls_isr.c optional qlxge pci dev/qlxge/qls_os.c optional qlxge pci dev/qlxgb/qla_dbg.c optional qlxgb pci dev/qlxgb/qla_hw.c optional qlxgb pci dev/qlxgb/qla_ioctl.c optional qlxgb pci dev/qlxgb/qla_isr.c optional qlxgb pci dev/qlxgb/qla_misc.c optional qlxgb pci dev/qlxgb/qla_os.c optional qlxgb pci dev/qlxgbe/ql_dbg.c optional qlxgbe pci dev/qlxgbe/ql_hw.c optional qlxgbe pci dev/qlxgbe/ql_ioctl.c optional qlxgbe pci dev/qlxgbe/ql_isr.c optional qlxgbe pci dev/qlxgbe/ql_misc.c optional qlxgbe pci dev/qlxgbe/ql_os.c optional qlxgbe pci dev/qlxgbe/ql_reset.c optional qlxgbe pci -dev/sfxge/common/efx_bootcfg.c optional sfxge inet pci -dev/sfxge/common/efx_ev.c optional sfxge inet pci -dev/sfxge/common/efx_filter.c optional sfxge inet pci -dev/sfxge/common/efx_intr.c optional sfxge inet pci -dev/sfxge/common/efx_mac.c optional sfxge inet pci -dev/sfxge/common/efx_mcdi.c optional sfxge inet pci -dev/sfxge/common/efx_mon.c optional sfxge inet pci -dev/sfxge/common/efx_nic.c optional sfxge inet pci -dev/sfxge/common/efx_nvram.c optional sfxge inet pci -dev/sfxge/common/efx_phy.c optional sfxge inet pci -dev/sfxge/common/efx_port.c optional sfxge inet pci -dev/sfxge/common/efx_rx.c optional sfxge inet pci -dev/sfxge/common/efx_sram.c optional sfxge inet pci -dev/sfxge/common/efx_tx.c optional sfxge inet pci -dev/sfxge/common/efx_vpd.c optional sfxge inet pci -dev/sfxge/common/efx_wol.c optional sfxge inet pci -dev/sfxge/common/siena_mac.c optional sfxge inet pci -dev/sfxge/common/siena_mon.c optional sfxge inet pci -dev/sfxge/common/siena_nic.c optional sfxge inet pci -dev/sfxge/common/siena_nvram.c optional sfxge inet pci -dev/sfxge/common/siena_phy.c optional sfxge inet pci -dev/sfxge/common/siena_sram.c optional sfxge inet pci -dev/sfxge/common/siena_vpd.c optional sfxge inet pci -dev/sfxge/sfxge.c optional sfxge inet pci -dev/sfxge/sfxge_dma.c optional sfxge inet pci -dev/sfxge/sfxge_ev.c optional sfxge inet pci -dev/sfxge/sfxge_intr.c optional sfxge inet pci -dev/sfxge/sfxge_mcdi.c optional sfxge inet pci -dev/sfxge/sfxge_port.c optional sfxge inet pci -dev/sfxge/sfxge_rx.c optional sfxge inet pci -dev/sfxge/sfxge_tx.c optional sfxge inet pci +dev/sfxge/common/efx_bootcfg.c optional sfxge pci +dev/sfxge/common/efx_crc32.c optional sfxge pci +dev/sfxge/common/efx_ev.c optional sfxge pci +dev/sfxge/common/efx_filter.c optional sfxge pci +dev/sfxge/common/efx_hash.c optional sfxge pci +dev/sfxge/common/efx_intr.c optional sfxge pci +dev/sfxge/common/efx_mac.c optional sfxge pci +dev/sfxge/common/efx_mcdi.c optional sfxge pci +dev/sfxge/common/efx_mon.c optional sfxge pci +dev/sfxge/common/efx_nic.c optional sfxge pci +dev/sfxge/common/efx_nvram.c optional sfxge pci +dev/sfxge/common/efx_phy.c optional sfxge pci +dev/sfxge/common/efx_port.c optional sfxge pci +dev/sfxge/common/efx_rx.c optional sfxge pci +dev/sfxge/common/efx_sram.c optional sfxge pci +dev/sfxge/common/efx_tx.c optional sfxge pci +dev/sfxge/common/efx_vpd.c optional sfxge pci +dev/sfxge/common/efx_wol.c optional sfxge pci +dev/sfxge/common/hunt_ev.c optional sfxge pci +dev/sfxge/common/hunt_filter.c optional sfxge pci +dev/sfxge/common/hunt_intr.c optional sfxge pci +dev/sfxge/common/hunt_mac.c optional sfxge pci +dev/sfxge/common/hunt_mcdi.c optional sfxge pci +dev/sfxge/common/hunt_nic.c optional sfxge pci +dev/sfxge/common/hunt_nvram.c optional sfxge pci +dev/sfxge/common/hunt_phy.c optional sfxge pci +dev/sfxge/common/hunt_rx.c optional sfxge pci +dev/sfxge/common/hunt_sram.c optional sfxge pci +dev/sfxge/common/hunt_tx.c optional sfxge pci +dev/sfxge/common/hunt_vpd.c optional sfxge pci +dev/sfxge/common/siena_mac.c optional sfxge pci +dev/sfxge/common/siena_mcdi.c optional sfxge pci +dev/sfxge/common/siena_nic.c optional sfxge pci +dev/sfxge/common/siena_nvram.c optional sfxge pci +dev/sfxge/common/siena_phy.c optional sfxge pci +dev/sfxge/common/siena_sram.c optional sfxge pci +dev/sfxge/common/siena_vpd.c optional sfxge pci +dev/sfxge/sfxge.c optional sfxge pci +dev/sfxge/sfxge_dma.c optional sfxge pci +dev/sfxge/sfxge_ev.c optional sfxge pci +dev/sfxge/sfxge_intr.c optional sfxge pci +dev/sfxge/sfxge_mcdi.c optional sfxge pci +dev/sfxge/sfxge_nvram.c optional sfxge pci +dev/sfxge/sfxge_port.c optional sfxge pci +dev/sfxge/sfxge_rx.c optional sfxge pci +dev/sfxge/sfxge_tx.c optional sfxge pci dev/sio/sio.c optional sio dev/sio/sio_isa.c optional sio isa dev/sio/sio_pccard.c optional sio pccard dev/sio/sio_pci.c optional sio pci dev/sio/sio_puc.c optional sio puc dev/speaker/spkr.c optional speaker dev/syscons/apm/apm_saver.c optional apm_saver apm dev/syscons/scterm-teken.c optional sc dev/syscons/scvesactl.c optional sc vga vesa dev/syscons/scvgarndr.c optional sc vga dev/syscons/scvtb.c optional sc dev/tpm/tpm.c optional tpm dev/tpm/tpm_acpi.c optional tpm acpi dev/tpm/tpm_isa.c optional tpm isa dev/uart/uart_cpu_x86.c optional uart dev/viawd/viawd.c optional viawd dev/vmware/vmxnet3/if_vmx.c optional vmx dev/wbwd/wbwd.c optional wbwd dev/wpi/if_wpi.c optional wpi dev/xen/pci/xen_acpi_pci.c optional xenhvm dev/xen/pci/xen_pci.c optional xenhvm dev/isci/isci.c optional isci dev/isci/isci_controller.c optional isci dev/isci/isci_domain.c optional isci dev/isci/isci_interrupt.c optional isci dev/isci/isci_io_request.c optional isci dev/isci/isci_logger.c optional isci dev/isci/isci_oem_parameters.c optional isci dev/isci/isci_remote_device.c optional isci dev/isci/isci_sysctl.c optional isci dev/isci/isci_task_request.c optional isci dev/isci/isci_timer.c optional isci dev/isci/scil/sati.c optional isci dev/isci/scil/sati_abort_task_set.c optional isci dev/isci/scil/sati_atapi.c optional isci dev/isci/scil/sati_device.c optional isci dev/isci/scil/sati_inquiry.c optional isci dev/isci/scil/sati_log_sense.c optional isci dev/isci/scil/sati_lun_reset.c optional isci dev/isci/scil/sati_mode_pages.c optional isci dev/isci/scil/sati_mode_select.c optional isci dev/isci/scil/sati_mode_sense.c optional isci dev/isci/scil/sati_mode_sense_10.c optional isci dev/isci/scil/sati_mode_sense_6.c optional isci dev/isci/scil/sati_move.c optional isci dev/isci/scil/sati_passthrough.c optional isci dev/isci/scil/sati_read.c optional isci dev/isci/scil/sati_read_buffer.c optional isci dev/isci/scil/sati_read_capacity.c optional isci dev/isci/scil/sati_reassign_blocks.c optional isci dev/isci/scil/sati_report_luns.c optional isci dev/isci/scil/sati_request_sense.c optional isci dev/isci/scil/sati_start_stop_unit.c optional isci dev/isci/scil/sati_synchronize_cache.c optional isci dev/isci/scil/sati_test_unit_ready.c optional isci dev/isci/scil/sati_unmap.c optional isci dev/isci/scil/sati_util.c optional isci dev/isci/scil/sati_verify.c optional isci dev/isci/scil/sati_write.c optional isci dev/isci/scil/sati_write_and_verify.c optional isci dev/isci/scil/sati_write_buffer.c optional isci dev/isci/scil/sati_write_long.c optional isci dev/isci/scil/sci_abstract_list.c optional isci dev/isci/scil/sci_base_controller.c optional isci dev/isci/scil/sci_base_domain.c optional isci dev/isci/scil/sci_base_iterator.c optional isci dev/isci/scil/sci_base_library.c optional isci dev/isci/scil/sci_base_logger.c optional isci dev/isci/scil/sci_base_memory_descriptor_list.c optional isci dev/isci/scil/sci_base_memory_descriptor_list_decorator.c optional isci dev/isci/scil/sci_base_object.c optional isci dev/isci/scil/sci_base_observer.c optional isci dev/isci/scil/sci_base_phy.c optional isci dev/isci/scil/sci_base_port.c optional isci dev/isci/scil/sci_base_remote_device.c optional isci dev/isci/scil/sci_base_request.c optional isci dev/isci/scil/sci_base_state_machine.c optional isci dev/isci/scil/sci_base_state_machine_logger.c optional isci dev/isci/scil/sci_base_state_machine_observer.c optional isci dev/isci/scil/sci_base_subject.c optional isci dev/isci/scil/sci_util.c optional isci dev/isci/scil/scic_sds_controller.c optional isci dev/isci/scil/scic_sds_library.c optional isci dev/isci/scil/scic_sds_pci.c optional isci dev/isci/scil/scic_sds_phy.c optional isci dev/isci/scil/scic_sds_port.c optional isci dev/isci/scil/scic_sds_port_configuration_agent.c optional isci dev/isci/scil/scic_sds_remote_device.c optional isci dev/isci/scil/scic_sds_remote_node_context.c optional isci dev/isci/scil/scic_sds_remote_node_table.c optional isci dev/isci/scil/scic_sds_request.c optional isci dev/isci/scil/scic_sds_sgpio.c optional isci dev/isci/scil/scic_sds_smp_remote_device.c optional isci dev/isci/scil/scic_sds_smp_request.c optional isci dev/isci/scil/scic_sds_ssp_request.c optional isci dev/isci/scil/scic_sds_stp_packet_request.c optional isci dev/isci/scil/scic_sds_stp_remote_device.c optional isci dev/isci/scil/scic_sds_stp_request.c optional isci dev/isci/scil/scic_sds_unsolicited_frame_control.c optional isci dev/isci/scil/scif_sas_controller.c optional isci dev/isci/scil/scif_sas_controller_state_handlers.c optional isci dev/isci/scil/scif_sas_controller_states.c optional isci dev/isci/scil/scif_sas_domain.c optional isci dev/isci/scil/scif_sas_domain_state_handlers.c optional isci dev/isci/scil/scif_sas_domain_states.c optional isci dev/isci/scil/scif_sas_high_priority_request_queue.c optional isci dev/isci/scil/scif_sas_internal_io_request.c optional isci dev/isci/scil/scif_sas_io_request.c optional isci dev/isci/scil/scif_sas_io_request_state_handlers.c optional isci dev/isci/scil/scif_sas_io_request_states.c optional isci dev/isci/scil/scif_sas_library.c optional isci dev/isci/scil/scif_sas_remote_device.c optional isci dev/isci/scil/scif_sas_remote_device_ready_substate_handlers.c optional isci dev/isci/scil/scif_sas_remote_device_ready_substates.c optional isci dev/isci/scil/scif_sas_remote_device_starting_substate_handlers.c optional isci dev/isci/scil/scif_sas_remote_device_starting_substates.c optional isci dev/isci/scil/scif_sas_remote_device_state_handlers.c optional isci dev/isci/scil/scif_sas_remote_device_states.c optional isci dev/isci/scil/scif_sas_request.c optional isci dev/isci/scil/scif_sas_smp_activity_clear_affiliation.c optional isci dev/isci/scil/scif_sas_smp_io_request.c optional isci dev/isci/scil/scif_sas_smp_phy.c optional isci dev/isci/scil/scif_sas_smp_remote_device.c optional isci dev/isci/scil/scif_sas_stp_io_request.c optional isci dev/isci/scil/scif_sas_stp_remote_device.c optional isci dev/isci/scil/scif_sas_stp_task_request.c optional isci dev/isci/scil/scif_sas_task_request.c optional isci dev/isci/scil/scif_sas_task_request_state_handlers.c optional isci dev/isci/scil/scif_sas_task_request_states.c optional isci dev/isci/scil/scif_sas_timer.c optional isci isa/syscons_isa.c optional sc isa/vga_isa.c optional vga kern/kern_clocksource.c standard kern/link_elf_obj.c standard # # IA32 binary support # #amd64/ia32/ia32_exception.S optional compat_freebsd32 amd64/ia32/ia32_reg.c optional compat_freebsd32 amd64/ia32/ia32_signal.c optional compat_freebsd32 amd64/ia32/ia32_sigtramp.S optional compat_freebsd32 amd64/ia32/ia32_syscall.c optional compat_freebsd32 amd64/ia32/ia32_misc.c optional compat_freebsd32 compat/ia32/ia32_sysvec.c optional compat_freebsd32 compat/linprocfs/linprocfs.c optional linprocfs compat/linsysfs/linsysfs.c optional linsysfs # # Linux/i386 binary support # amd64/linux32/linux32_dummy.c optional compat_linux32 amd64/linux32/linux32_machdep.c optional compat_linux32 amd64/linux32/linux32_support.s optional compat_linux32 \ dependency "linux32_assym.h" amd64/linux32/linux32_sysent.c optional compat_linux32 amd64/linux32/linux32_sysvec.c optional compat_linux32 compat/linux/linux_emul.c optional compat_linux32 compat/linux/linux_file.c optional compat_linux32 compat/linux/linux_fork.c optional compat_linux32 compat/linux/linux_futex.c optional compat_linux32 compat/linux/linux_getcwd.c optional compat_linux32 compat/linux/linux_ioctl.c optional compat_linux32 compat/linux/linux_ipc.c optional compat_linux32 compat/linux/linux_mib.c optional compat_linux32 compat/linux/linux_misc.c optional compat_linux32 compat/linux/linux_signal.c optional compat_linux32 compat/linux/linux_socket.c optional compat_linux32 compat/linux/linux_stats.c optional compat_linux32 compat/linux/linux_sysctl.c optional compat_linux32 compat/linux/linux_time.c optional compat_linux32 compat/linux/linux_timer.c optional compat_linux32 compat/linux/linux_uid16.c optional compat_linux32 compat/linux/linux_util.c optional compat_linux32 compat/linux/linux_vdso.c optional compat_linux32 compat/linux/linux_common.c optional compat_linux32 compat/linux/linux_event.c optional compat_linux32 compat/linux/linux.c optional compat_linux32 dev/amr/amr_linux.c optional compat_linux32 amr dev/mfi/mfi_linux.c optional compat_linux32 mfi # # Windows NDIS driver support # compat/ndis/kern_ndis.c optional ndisapi pci compat/ndis/kern_windrv.c optional ndisapi pci compat/ndis/subr_hal.c optional ndisapi pci compat/ndis/subr_ndis.c optional ndisapi pci compat/ndis/subr_ntoskrnl.c optional ndisapi pci compat/ndis/subr_pe.c optional ndisapi pci compat/ndis/subr_usbd.c optional ndisapi pci compat/ndis/winx64_wrap.S optional ndisapi pci # libkern/memmove.c standard libkern/memset.c standard # # x86 real mode BIOS emulator, required by dpms/pci/vesa # compat/x86bios/x86bios.c optional x86bios | dpms | pci | vesa contrib/x86emu/x86emu.c optional x86bios | dpms | pci | vesa # # bvm console # dev/bvm/bvm_console.c optional bvmconsole dev/bvm/bvm_dbg.c optional bvmdebug # # x86 shared code between IA32, AMD64 and PC98 architectures # x86/acpica/OsdEnvironment.c optional acpi x86/acpica/acpi_apm.c optional acpi x86/acpica/acpi_wakeup.c optional acpi x86/acpica/madt.c optional acpi x86/acpica/srat.c optional acpi x86/bios/smbios.c optional smbios x86/bios/vpd.c optional vpd x86/cpufreq/powernow.c optional cpufreq x86/cpufreq/est.c optional cpufreq x86/cpufreq/hwpstate.c optional cpufreq x86/cpufreq/p4tcc.c optional cpufreq x86/iommu/busdma_dmar.c optional acpi acpi_dmar pci x86/iommu/intel_ctx.c optional acpi acpi_dmar pci x86/iommu/intel_drv.c optional acpi acpi_dmar pci x86/iommu/intel_fault.c optional acpi acpi_dmar pci x86/iommu/intel_gas.c optional acpi acpi_dmar pci x86/iommu/intel_idpgtbl.c optional acpi acpi_dmar pci x86/iommu/intel_intrmap.c optional acpi acpi_dmar pci x86/iommu/intel_qi.c optional acpi acpi_dmar pci x86/iommu/intel_quirks.c optional acpi acpi_dmar pci x86/iommu/intel_utils.c optional acpi acpi_dmar pci x86/isa/atpic.c optional atpic isa x86/isa/atrtc.c standard x86/isa/clock.c standard x86/isa/elcr.c optional atpic isa | mptable x86/isa/isa.c standard x86/isa/isa_dma.c standard x86/isa/nmi.c standard x86/isa/orm.c optional isa x86/pci/pci_bus.c optional pci x86/pci/qpi.c optional pci x86/x86/busdma_bounce.c standard x86/x86/busdma_machdep.c standard x86/x86/cpu_machdep.c standard x86/x86/dump_machdep.c standard x86/x86/fdt_machdep.c optional fdt x86/x86/identcpu.c standard x86/x86/intr_machdep.c standard x86/x86/io_apic.c standard x86/x86/legacy.c standard x86/x86/local_apic.c standard x86/x86/mca.c standard x86/x86/mptable.c optional mptable x86/x86/mptable_pci.c optional mptable pci x86/x86/mp_x86.c optional smp x86/x86/msi.c optional pci x86/x86/nexus.c standard x86/x86/pvclock.c standard x86/x86/tsc.c standard x86/x86/delay.c standard x86/xen/hvm.c optional xenhvm x86/xen/xen_intr.c optional xenhvm x86/xen/pv.c optional xenhvm x86/xen/pvcpu_enum.c optional xenhvm x86/xen/xen_apic.c optional xenhvm x86/xen/xenpv.c optional xenhvm x86/xen/xen_nexus.c optional xenhvm x86/xen/xen_msi.c optional xenhvm x86/xen/xen_pci_bus.c optional xenhvm Index: head/sys/dev/sfxge/common/siena_mon.c =================================================================== --- head/sys/dev/sfxge/common/siena_mon.c (revision 283513) +++ head/sys/dev/sfxge/common/siena_mon.c (nonexistent) @@ -1,284 +0,0 @@ -/*- - * Copyright 2009 Solarflare Communications Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include "efsys.h" -#include "efx.h" -#include "efx_impl.h" - -#if EFSYS_OPT_MON_SIENA - - __checkReturn int -siena_mon_reset( - __in efx_nic_t *enp) -{ - _NOTE(ARGUNUSED(enp)) - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); - - return (0); -} - - __checkReturn int -siena_mon_reconfigure( - __in efx_nic_t *enp) -{ - _NOTE(ARGUNUSED(enp)) - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); - - return (0); -} - -#if EFSYS_OPT_MON_STATS - -#define SIENA_MON_WRONG_PORT (uint16_t)0xffff - -static __cs uint16_t __siena_mon_port0_map[] = { - EFX_MON_STAT_INT_TEMP, /* MC_CMD_SENSOR_CONTROLLER_TEMP */ - EFX_MON_STAT_EXT_TEMP, /* MC_CMD_SENSOR_PHY_COMMON_TEMP */ - EFX_MON_STAT_INT_COOLING, /* MC_CMD_SENSOR_CONTROLLER_COOLING */ - EFX_MON_STAT_EXT_TEMP, /* MC_CMD_SENSOR_PHY0_TEMP */ - EFX_MON_STAT_EXT_COOLING, /* MC_CMD_SENSOR_PHY0_COOLING */ - SIENA_MON_WRONG_PORT, /* MC_CMD_SENSOR_PHY1_TEMP */ - SIENA_MON_WRONG_PORT, /* MC_CMD_SENSOR_PHY1_COOLING */ - EFX_MON_STAT_1V, /* MC_CMD_SENSOR_IN_1V0 */ - EFX_MON_STAT_1_2V, /* MC_CMD_SENSOR_IN_1V2 */ - EFX_MON_STAT_1_8V, /* MC_CMD_SENSOR_IN_1V8 */ - EFX_MON_STAT_2_5V, /* MC_CMD_SENSOR_IN_2V5 */ - EFX_MON_STAT_3_3V, /* MC_CMD_SENSOR_IN_3V3 */ - EFX_MON_STAT_12V, /* MC_CMD_SENSOR_IN_12V0 */ - EFX_MON_STAT_1_2VA, /* MC_CMD_SENSOR_IN_1V2A */ - EFX_MON_STAT_VREF, /* MC_CMD_SENSOR_IN_VREF */ - EFX_MON_STAT_VAOE, /* MC_CMD_SENSOR_OUT_VAOE */ - EFX_MON_STAT_AOE_TEMP, /* MC_CMD_SENSOR_AOE_TEMP */ - EFX_MON_STAT_PSU_AOE_TEMP, /* MC_CMD_SENSOR_PSU_AOE_TEMP */ - EFX_MON_STAT_PSU_TEMP, /* MC_CMD_SENSOR_PSE_TEMP */ - EFX_MON_STAT_FAN0, /* MC_CMD_SENSOR_FAN_0 */ - EFX_MON_STAT_FAN1, /* MC_CMD_SENSOR_FAN_1 */ - EFX_MON_STAT_FAN2, /* MC_CMD_SENSOR_FAN_2 */ - EFX_MON_STAT_FAN3, /* MC_CMD_SENSOR_FAN_3 */ - EFX_MON_STAT_FAN4, /* MC_CMD_SENSOR_FAN_4 */ - EFX_MON_STAT_VAOE_IN, /* MC_CMD_SENSOR_IN_VAOE */ - EFX_MON_STAT_IAOE, /* MC_CMD_SENSOR_OUT_IAOE */ - EFX_MON_STAT_IAOE_IN, /* MC_CMD_SENSOR_IN_IAOE */ - -}; - -static __cs uint16_t __siena_mon_port1_map[] = { - EFX_MON_STAT_INT_TEMP, /* MC_CMD_SENSOR_CONTROLLER_TEMP */ - EFX_MON_STAT_EXT_TEMP, /* MC_CMD_SENSOR_PHY_COMMON_TEMP */ - EFX_MON_STAT_INT_COOLING, /* MC_CMD_SENSOR_CONTROLLER_COOLING */ - SIENA_MON_WRONG_PORT, /* MC_CMD_SENSOR_PHY0_TEMP */ - SIENA_MON_WRONG_PORT, /* MC_CMD_SENSOR_PHY0_COOLING */ - EFX_MON_STAT_EXT_TEMP, /* MC_CMD_SENSOR_PHY1_TEMP */ - EFX_MON_STAT_EXT_COOLING, /* MC_CMD_SENSOR_PHY1_COOLING */ - EFX_MON_STAT_1V, /* MC_CMD_SENSOR_IN_1V0 */ - EFX_MON_STAT_1_2V, /* MC_CMD_SENSOR_IN_1V2 */ - EFX_MON_STAT_1_8V, /* MC_CMD_SENSOR_IN_1V8 */ - EFX_MON_STAT_2_5V, /* MC_CMD_SENSOR_IN_2V5 */ - EFX_MON_STAT_3_3V, /* MC_CMD_SENSOR_IN_3V3 */ - EFX_MON_STAT_12V, /* MC_CMD_SENSOR_IN_12V0 */ - EFX_MON_STAT_1_2VA, /* MC_CMD_SENSOR_IN_1V2A */ - EFX_MON_STAT_VREF, /* MC_CMD_SENSOR_IN_VREF */ - EFX_MON_STAT_VAOE, /* MC_CMD_SENSOR_OUT_VAOE */ - EFX_MON_STAT_AOE_TEMP, /* MC_CMD_SENSOR_AOE_TEMP */ - EFX_MON_STAT_PSU_AOE_TEMP, /* MC_CMD_SENSOR_PSU_AOE_TEMP */ - EFX_MON_STAT_PSU_TEMP, /* MC_CMD_SENSOR_PSE_TEMP */ - EFX_MON_STAT_FAN0, /* MC_CMD_SENSOR_FAN_0 */ - EFX_MON_STAT_FAN1, /* MC_CMD_SENSOR_FAN_1 */ - EFX_MON_STAT_FAN2, /* MC_CMD_SENSOR_FAN_2 */ - EFX_MON_STAT_FAN3, /* MC_CMD_SENSOR_FAN_3 */ - EFX_MON_STAT_FAN4, /* MC_CMD_SENSOR_FAN_4 */ - EFX_MON_STAT_VAOE_IN, /* MC_CMD_SENSOR_IN_VAOE */ - EFX_MON_STAT_IAOE, /* MC_CMD_SENSOR_OUT_IAOE */ - EFX_MON_STAT_IAOE_IN, /* MC_CMD_SENSOR_IN_IAOE */ - -}; - -#define SIENA_STATIC_SENSOR_ASSERT(_field) \ - EFX_STATIC_ASSERT(MC_CMD_SENSOR_STATE_ ## _field \ - == EFX_MON_STAT_STATE_ ## _field) - - void -siena_mon_decode_stats( - __in efx_nic_t *enp, - __in uint32_t dmask, - __in_opt efsys_mem_t *esmp, - __out_opt uint32_t *vmaskp, - __out_ecount_opt(EFX_MON_NSTATS) efx_mon_stat_value_t *value) -{ - efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip); - uint16_t *sensor_map; - uint16_t mc_sensor; - size_t mc_sensor_max; - uint32_t vmask = 0; - uint32_t idx = 0; - - /* Assert the MC_CMD_SENSOR and EFX_MON_STATE namespaces agree */ - SIENA_STATIC_SENSOR_ASSERT(OK); - SIENA_STATIC_SENSOR_ASSERT(WARNING); - SIENA_STATIC_SENSOR_ASSERT(FATAL); - SIENA_STATIC_SENSOR_ASSERT(BROKEN); - - EFX_STATIC_ASSERT(sizeof (__siena_mon_port1_map) - == sizeof (__siena_mon_port0_map)); - mc_sensor_max = EFX_ARRAY_SIZE(__siena_mon_port0_map); - sensor_map = (emip->emi_port == 1) - ? __siena_mon_port0_map - : __siena_mon_port1_map; - - /* - * dmask may legitimately contain sensors not understood by the driver - */ - for (mc_sensor = 0; mc_sensor < mc_sensor_max; ++mc_sensor) { - uint16_t efx_sensor = sensor_map[mc_sensor]; - - if (~dmask & (1 << mc_sensor)) - continue; - idx++; - - if (efx_sensor == SIENA_MON_WRONG_PORT) - continue; - EFSYS_ASSERT(efx_sensor < EFX_MON_NSTATS); - - vmask |= (1 << efx_sensor); - if (value != NULL && esmp != NULL && !EFSYS_MEM_IS_NULL(esmp)) { - efx_mon_stat_value_t *emsvp = value + efx_sensor; - efx_dword_t dword; - EFSYS_MEM_READD(esmp, 4 * (idx - 1), &dword); - emsvp->emsv_value = - (uint16_t)EFX_DWORD_FIELD( - dword, - MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE); - emsvp->emsv_state = - (uint16_t)EFX_DWORD_FIELD( - dword, - MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE); - } - } - - if (vmaskp != NULL) - *vmaskp = vmask; -} - - __checkReturn int -siena_mon_ev( - __in efx_nic_t *enp, - __in efx_qword_t *eqp, - __out efx_mon_stat_t *idp, - __out efx_mon_stat_value_t *valuep) -{ - efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip); - efx_nic_cfg_t *encp = &(enp->en_nic_cfg); - uint16_t ev_monitor; - uint16_t ev_state; - uint16_t ev_value; - uint16_t *sensor_map; - efx_mon_stat_t id; - int rc; - - sensor_map = (emip->emi_port == 1) - ? __siena_mon_port0_map - : __siena_mon_port1_map; - - ev_monitor = (uint16_t)MCDI_EV_FIELD(eqp, SENSOREVT_MONITOR); - ev_state = (uint16_t)MCDI_EV_FIELD(eqp, SENSOREVT_STATE); - ev_value = (uint16_t)MCDI_EV_FIELD(eqp, SENSOREVT_VALUE); - - /* Hardware must support this statistic */ - EFSYS_ASSERT((1 << ev_monitor) & encp->enc_siena_mon_stat_mask); - - /* But we don't have to understand it */ - if (ev_monitor >= EFX_ARRAY_SIZE(__siena_mon_port0_map)) { - rc = ENOTSUP; - goto fail1; - } - - id = sensor_map[ev_monitor]; - if (id == SIENA_MON_WRONG_PORT) - return (ENODEV); - EFSYS_ASSERT(id < EFX_MON_NSTATS); - - *idp = id; - valuep->emsv_value = ev_value; - valuep->emsv_state = ev_state; - - return (0); - -fail1: - EFSYS_PROBE1(fail1, int, rc); - - return (rc); -} - - __checkReturn int -siena_mon_stats_update( - __in efx_nic_t *enp, - __in efsys_mem_t *esmp, - __out_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values) -{ - efx_nic_cfg_t *encp = &(enp->en_nic_cfg); - uint32_t dmask = encp->enc_siena_mon_stat_mask; - uint32_t vmask; - uint8_t payload[MC_CMD_READ_SENSORS_IN_LEN]; - efx_mcdi_req_t req; - int rc; - - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); - - req.emr_cmd = MC_CMD_READ_SENSORS; - req.emr_in_buf = payload; - req.emr_in_length = sizeof (payload); - EFX_STATIC_ASSERT(MC_CMD_READ_SENSORS_OUT_LEN == 0); - req.emr_out_buf = NULL; - req.emr_out_length = 0; - - MCDI_IN_SET_DWORD(req, READ_SENSORS_IN_DMA_ADDR_LO, - EFSYS_MEM_ADDR(esmp) & 0xffffffff); - MCDI_IN_SET_DWORD(req, READ_SENSORS_IN_DMA_ADDR_HI, - EFSYS_MEM_ADDR(esmp) >> 32); - - efx_mcdi_execute(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; - goto fail1; - } - - siena_mon_decode_stats(enp, dmask, esmp, &vmask, values); - EFSYS_ASSERT(vmask == encp->enc_mon_stat_mask); - - return (0); - -fail1: - EFSYS_PROBE1(fail1, int, rc); - - return (rc); -} - -#endif /* EFSYS_OPT_MON_STATS */ - -#endif /* EFSYS_OPT_MON_SIENA */ Property changes on: head/sys/dev/sfxge/common/siena_mon.c ___________________________________________________________________ Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Index: head/sys/dev/sfxge/common/ef10_tlv_layout.h =================================================================== --- head/sys/dev/sfxge/common/ef10_tlv_layout.h (nonexistent) +++ head/sys/dev/sfxge/common/ef10_tlv_layout.h (revision 283514) @@ -0,0 +1,691 @@ +/*- + * Copyright (c) 2012-2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + * + * $FreeBSD$ + */ + +/* These structures define the layouts for the TLV items stored in static and + * dynamic configuration partitions in NVRAM for EF10 (Huntington etc.). + * + * They contain the same sort of information that was kept in the + * siena_mc_static_config_hdr_t and siena_mc_dynamic_config_hdr_t structures + * (defined in and ) for + * Siena. + * + * These are used directly by the MC and should also be usable directly on host + * systems which are little-endian and do not do strange things with structure + * padding. (Big-endian host systems will require some byte-swapping.) + * + * ----- + * + * Please refer to SF-108797-SW for a general overview of the TLV partition + * format. + * + * ----- + * + * The current tag IDs have a general structure: with the exception of the + * special values defined in the document, they are of the form 0xLTTTNNNN, + * where: + * + * - L is a location, indicating where this tag is expected to be found: + * 0 for static configuration, or 1 for dynamic configuration. Other + * values are reserved. + * + * - TTT is a type, which is just a unique value. The same type value + * might appear in both locations, indicating a relationship between + * the items (e.g. static and dynamic VPD below). + * + * - NNNN is an index of some form. Some item types are per-port, some + * are per-PF, some are per-partition-type. + * + * ----- + * + * As with the previous Siena structures, each structure here is laid out + * carefully: values are aligned to their natural boundary, with explicit + * padding fields added where necessary. (No, technically this does not + * absolutely guarantee portability. But, in practice, compilers are generally + * sensible enough not to introduce completely pointless padding, and it works + * well enough.) + */ + + +#ifndef CI_MGMT_TLV_LAYOUT_H +#define CI_MGMT_TLV_LAYOUT_H + + +/* ---------------------------------------------------------------------------- + * General structure (defined by SF-108797-SW) + * ---------------------------------------------------------------------------- + */ + + +/* The "end" tag. + * + * (Note that this is *not* followed by length or value fields: anything after + * the tag itself is irrelevant.) + */ + +#define TLV_TAG_END (0xEEEEEEEE) + + +/* Other special reserved tag values. + */ + +#define TLV_TAG_SKIP (0x00000000) +#define TLV_TAG_INVALID (0xFFFFFFFF) + + +/* TLV partition header. + * + * In a TLV partition, this must be the first item in the sequence, at offset + * 0. + */ + +#define TLV_TAG_PARTITION_HEADER (0xEF10DA7A) + +struct tlv_partition_header { + uint32_t tag; + uint32_t length; + uint16_t type_id; + uint16_t reserved; + uint32_t generation; + uint32_t total_length; +}; + + +/* TLV partition trailer. + * + * In a TLV partition, this must be the last item in the sequence, immediately + * preceding the TLV_TAG_END word. + */ + +#define TLV_TAG_PARTITION_TRAILER (0xEF101A57) + +struct tlv_partition_trailer { + uint32_t tag; + uint32_t length; + uint32_t generation; + uint32_t checksum; +}; + + +/* Appendable TLV partition header. + * + * In an appendable TLV partition, this must be the first item in the sequence, + * at offset 0. (Note that, unlike the configuration partitions, there is no + * trailer before the TLV_TAG_END word.) + */ + +#define TLV_TAG_APPENDABLE_PARTITION_HEADER (0xEF10ADA7) + +struct tlv_appendable_partition_header { + uint32_t tag; + uint32_t length; + uint16_t type_id; + uint16_t reserved; +}; + + +/* ---------------------------------------------------------------------------- + * Configuration items + * ---------------------------------------------------------------------------- + */ + + +/* NIC global capabilities. + */ + +#define TLV_TAG_GLOBAL_CAPABILITIES (0x00010000) + +struct tlv_global_capabilities { + uint32_t tag; + uint32_t length; + uint32_t flags; +}; + + +/* Siena-style per-port MAC address allocation. + * + * There are addresses, starting at and incrementing + * by adding to the low-order byte(s). + * + * (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool + * of contiguous MAC addresses for the firmware to allocate as it sees fit.) + */ + +#define TLV_TAG_PORT_MAC(port) (0x00020000 + (port)) + +struct tlv_port_mac { + uint32_t tag; + uint32_t length; + uint8_t base_address[6]; + uint16_t reserved; + uint16_t count; + uint16_t stride; +}; + + +/* Static VPD. + * + * This is the portion of VPD which is set at manufacturing time and not + * expected to change. It is formatted as a standard PCI VPD block. + */ + +#define TLV_TAG_PF_STATIC_VPD(pf) (0x00030000 + (pf)) + +struct tlv_pf_static_vpd { + uint32_t tag; + uint32_t length; + uint8_t bytes[]; +}; + + +/* Dynamic VPD. + * + * This is the portion of VPD which may be changed (e.g. by firmware updates). + * It is formatted as a standard PCI VPD block. + */ + +#define TLV_TAG_PF_DYNAMIC_VPD(pf) (0x10030000 + (pf)) + +struct tlv_pf_dynamic_vpd { + uint32_t tag; + uint32_t length; + uint8_t bytes[]; +}; + + +/* "DBI" PCI config space changes. + * + * This is a set of edits made to the default PCI config space values before + * the device is allowed to enumerate. + */ + +#define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf)) + +struct tlv_pf_dbi { + uint32_t tag; + uint32_t length; + struct { + uint16_t addr; + uint16_t byte_enables; + uint32_t value; + } items[]; +}; + + +/* Partition subtype codes. + * + * A subtype may optionally be stored for each type of partition present in + * the NVRAM. For example, this may be used to allow a generic firmware update + * utility to select a specific variant of firmware for a specific variant of + * board. + * + * The description[] field is an optional string which is returned in the + * MC_CMD_NVRAM_METADATA response if present. + */ + +#define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type)) + +struct tlv_partition_subtype { + uint32_t tag; + uint32_t length; + uint32_t subtype; + uint8_t description[]; +}; + + +/* Partition version codes. + * + * A version may optionally be stored for each type of partition present in + * the NVRAM. This provides a standard way of tracking the currently stored + * version of each of the various component images. + */ + +#define TLV_TAG_PARTITION_VERSION(type) (0x10060000 + (type)) + +struct tlv_partition_version { + uint32_t tag; + uint32_t length; + uint16_t version_w; + uint16_t version_x; + uint16_t version_y; + uint16_t version_z; +}; + +/* Global PCIe configuration */ + +#define TLV_TAG_GLOBAL_PCIE_CONFIG (0x10070000) + +struct tlv_pcie_config { + uint32_t tag; + uint32_t length; + int16_t max_pf_number; /**< Largest PF RID (lower PFs may be hidden) */ + uint16_t pf_aper; /**< BIU aperture for PF BAR2 */ + uint16_t vf_aper; /**< BIU aperture for VF BAR0 */ + uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */ +#define TLV_MAX_PF_DEFAULT (-1) /* Use FW default for largest PF RID */ +#define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */ +}; + +/* Per-PF configuration. Note that not all these fields are necessarily useful + * as the apertures are constrained by the BIU settings (the one case we do + * use is to make BAR2 bigger than the BIU thinks to reserve space), but we can + * tidy things up later */ + +#define TLV_TAG_PF_PCIE_CONFIG(pf) (0x10080000 + (pf)) + +struct tlv_per_pf_pcie_config { + uint32_t tag; + uint32_t length; + uint8_t vfs_total; + uint8_t port_allocation; + uint16_t vectors_per_pf; + uint16_t vectors_per_vf; + uint8_t pf_bar0_aperture; + uint8_t pf_bar2_aperture; + uint8_t vf_bar0_aperture; + uint8_t vf_base; + uint16_t supp_pagesz; + uint16_t msix_vec_base; +}; + + +/* Development ONLY. This is a single TLV tag for all the gubbins + * that can be set through the MC command-line other than the PCIe + * settings. This is a temporary measure. */ +#define TLV_TAG_TMP_GUBBINS (0x10090000) + +struct tlv_tmp_gubbins { + uint32_t tag; + uint32_t length; + /* Consumed by dpcpu.c */ + uint64_t tx0_tags; /* Bitmap */ + uint64_t tx1_tags; /* Bitmap */ + uint64_t dl_tags; /* Bitmap */ + uint32_t flags; +#define TLV_DPCPU_TX_STRIPE (1) /* TX striping is on */ +#define TLV_DPCPU_BIU_TAGS (2) /* Use BIU tag manager */ +#define TLV_DPCPU_TX0_TAGS (4) /* tx0_tags is valid */ +#define TLV_DPCPU_TX1_TAGS (8) /* tx1_tags is valid */ +#define TLV_DPCPU_DL_TAGS (16) /* dl_tags is valid */ + /* Consumed by features.c */ + uint32_t dut_features; /* All 1s -> leave alone */ + int8_t with_rmon; /* 0 -> off, 1 -> on, -1 -> leave alone */ + /* Consumed by clocks_hunt.c */ + int8_t clk_mode; /* 0 -> off, 1 -> on, -1 -> leave alone */ + /* Consumed by sram.c */ + int8_t rx_dc_size; /* -1 -> leave alone */ + int8_t tx_dc_size; + int16_t num_q_allocs; +}; + +/* Global port configuration + * + * This is now deprecated in favour of a platform-provided default + * and dynamic config override via tlv_global_port_options. + */ +#define TLV_TAG_GLOBAL_PORT_CONFIG (0x000a0000) + +struct tlv_global_port_config { + uint32_t tag; + uint32_t length; + uint32_t ports_per_core; + uint32_t max_port_speed; +}; + + +/* Firmware options. + * + * This is intended for user-configurable selection of optional firmware + * features and variants. + * + * Initially, this consists only of the satellite CPU firmware variant + * selection, but this tag could be extended in the future (using the + * tag length to determine whether additional fields are present). + */ + +#define TLV_TAG_FIRMWARE_OPTIONS (0x100b0000) + +struct tlv_firmware_options { + uint32_t tag; + uint32_t length; + uint32_t firmware_variant; +#define TLV_FIRMWARE_VARIANT_DRIVER_SELECTED (0xffffffff) + +/* These are the values for overriding the driver's choice; the definitions + * are taken from MCDI so that they don't get out of step. Include + * or the equivalent from your driver's tree if + * you need to use these constants. + */ +#define TLV_FIRMWARE_VARIANT_FULL_FEATURED MC_CMD_FW_FULL_FEATURED +#define TLV_FIRMWARE_VARIANT_LOW_LATENCY MC_CMD_FW_LOW_LATENCY +#define TLV_FIRMWARE_VARIANT_PACKED_STREAM MC_CMD_FW_PACKED_STREAM +#define TLV_FIRMWARE_VARIANT_HIGH_TX_RATE MC_CMD_FW_HIGH_TX_RATE +#define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \ + MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 +}; + +/* Voltage settings + * + * Intended for boards with A0 silicon where the core voltage may + * need tweaking. Most likely set once when the pass voltage is + * determined. */ + +#define TLV_TAG_0V9_SETTINGS (0x000c0000) + +struct tlv_0v9_settings { + uint32_t tag; + uint32_t length; + uint16_t flags; /* Boards with high 0v9 settings may need active cooling */ +#define TLV_TAG_0V9_REQUIRES_FAN (1) + uint16_t target_voltage; /* In millivolts */ + /* Since the limits are meant to be centred to the target (and must at least + * contain it) they need setting as well. */ + uint16_t warn_low; /* In millivolts */ + uint16_t warn_high; /* In millivolts */ + uint16_t panic_low; /* In millivolts */ + uint16_t panic_high; /* In millivolts */ +}; + + +/* Clock configuration */ + +#define TLV_TAG_CLOCK_CONFIG (0x000d0000) + +struct tlv_clock_config { + uint32_t tag; + uint32_t length; + uint16_t clk_sys; /* MHz */ + uint16_t clk_dpcpu; /* MHz */ + uint16_t clk_icore; /* MHz */ + uint16_t clk_pcs; /* MHz */ +}; + +#define TLV_TAG_CLOCK_CONFIG_MEDFORD (0x00100000) + +struct tlv_clock_config_medford { + uint32_t tag; + uint32_t length; + uint16_t clk_sys; /* MHz */ + uint16_t clk_mc; /* MHz */ + uint16_t clk_rmon; /* MHz */ + uint16_t clk_vswitch; /* MHz */ + uint16_t clk_dpcpu; /* MHz */ + uint16_t clk_pcs; /* MHz */ +}; + + +/* EF10-style global pool of MAC addresses. + * + * There are addresses, starting at , which are + * contiguous. Firmware is responsible for allocating addresses from this + * pool to ports / PFs as appropriate. + */ + +#define TLV_TAG_GLOBAL_MAC (0x000e0000) + +struct tlv_global_mac { + uint32_t tag; + uint32_t length; + uint8_t base_address[6]; + uint16_t reserved1; + uint16_t count; + uint16_t reserved2; +}; + +#define TLV_TAG_ATB_0V9_TARGET (0x000f0000) + +/* The target value for the 0v9 power rail measured on-chip at the + * analogue test bus */ +struct tlv_0v9_atb_target { + uint32_t tag; + uint32_t length; + uint16_t millivolts; + uint16_t reserved; +}; + +/* Global PCIe configuration, second revision. This represents the visible PFs + * by a bitmap rather than having the number of the highest visible one. As such + * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG + * can and it should be used in place of that tag in future (but compatibility with + * the old tag will be left in the firmware indefinitely). */ + +#define TLV_TAG_GLOBAL_PCIE_CONFIG_R2 (0x10100000) + +struct tlv_pcie_config_r2 { + uint32_t tag; + uint32_t length; + uint16_t visible_pfs; /**< Bitmap of visible PFs */ + uint16_t pf_aper; /**< BIU aperture for PF BAR2 */ + uint16_t vf_aper; /**< BIU aperture for VF BAR0 */ + uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */ +}; + +/* Dynamic port mode. + * + * Allows selecting alternate port configuration for platforms that support it + * (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the + * number of externally visible ports (and, hence, PF to port mapping), so must + * be done at boot time. + * + * This tag supercedes tlv_global_port_config. + */ + +#define TLV_TAG_GLOBAL_PORT_MODE (0x10110000) + +struct tlv_global_port_mode { + uint32_t tag; + uint32_t length; + uint32_t port_mode; +#define TLV_PORT_MODE_DEFAULT (0xffffffff) /* Default for given platform */ +#define TLV_PORT_MODE_10G (0) /* 10G, single SFP/10G-KR */ +#define TLV_PORT_MODE_40G (1) /* 40G, single QSFP/40G-KR */ +#define TLV_PORT_MODE_10G_10G (2) /* 2x10G, dual SFP/10G-KR or single QSFP */ +#define TLV_PORT_MODE_40G_40G (3) /* 40G + 40G, dual QSFP/40G-KR (Greenport, Medford) */ +#define TLV_PORT_MODE_10G_10G_10G_10G (4) /* 2x10G + 2x10G, quad SFP/10G-KR or dual QSFP (Greenport, Medford) */ +#define TLV_PORT_MODE_10G_10G_10G_10G_Q (5) /* 4x10G, single QSFP, cage 0 (Medford) */ +#define TLV_PORT_MODE_40G_10G_10G (6) /* 1x40G + 2x10G, dual QSFP (Greenport, Medford) */ +#define TLV_PORT_MODE_10G_10G_40G (7) /* 2x10G + 1x40G, dual QSFP (Greenport, Medford) */ +#define TLV_PORT_MODE_10G_10G_10G_10G_Q2 (8) /* 4x10G, single QSFP, cage 1 (Medford) */ +#define TLV_PORT_MODE_MAX TLV_PORT_MODE_10G_10G_10G_10G_Q2 +}; + +/* Type of the v-switch created implicitly by the firmware */ + +#define TLV_TAG_VSWITCH_TYPE(port) (0x10120000 + (port)) + +struct tlv_vswitch_type { + uint32_t tag; + uint32_t length; + uint32_t vswitch_type; +#define TLV_VSWITCH_TYPE_DEFAULT (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */ +#define TLV_VSWITCH_TYPE_NONE (0) +#define TLV_VSWITCH_TYPE_VLAN (1) +#define TLV_VSWITCH_TYPE_VEB (2) +#define TLV_VSWITCH_TYPE_VEPA (3) +#define TLV_VSWITCH_TYPE_MUX (4) +#define TLV_VSWITCH_TYPE_TEST (5) +}; + +/* A VLAN tag for the v-port created implicitly by the firmware */ + +#define TLV_TAG_VPORT_VLAN_TAG(pf) (0x10130000 + (pf)) + +struct tlv_vport_vlan_tag { + uint32_t tag; + uint32_t length; + uint32_t vlan_tag; +#define TLV_VPORT_NO_VLAN_TAG (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */ +}; + +/* Offset to be applied to the 0v9 setting, wherever it came from */ + +#define TLV_TAG_ATB_0V9_OFFSET (0x10140000) + +struct tlv_0v9_atb_offset { + uint32_t tag; + uint32_t length; + int16_t offset_millivolts; + uint16_t reserved; +}; + +/* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per-port). + * The meaning of particular bits is defined in mcdi_ef10.yml under MC_CMD_PRIVILEGE_MASK, see also bug 44583. + * TLV_TAG_PRIVILEGE_MASK_ADD specifies bits that should be added (ORed) to firmware default while + * TLV_TAG_PRIVILEGE_MASK_REM specifies bits that should be removed (ANDed) from firmware default: + * Initial_privilege_mask = (firmware_default_mask | privilege_mask_add) & ~privilege_mask_rem */ + +#define TLV_TAG_PRIVILEGE_MASK (0x10150000) /* legacy symbol - do not use */ + +struct tlv_privilege_mask { /* legacy structure - do not use */ + uint32_t tag; + uint32_t length; + uint32_t privilege_mask; +}; + +#define TLV_TAG_PRIVILEGE_MASK_ADD (0x10150000) + +struct tlv_privilege_mask_add { + uint32_t tag; + uint32_t length; + uint32_t privilege_mask_add; +}; + +#define TLV_TAG_PRIVILEGE_MASK_REM (0x10160000) + +struct tlv_privilege_mask_rem { + uint32_t tag; + uint32_t length; + uint32_t privilege_mask_rem; +}; + +/* Additional privileges given to all PFs. + * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */ + +#define TLV_TAG_PRIVILEGE_MASK_ADD_ALL_PFS (0x10190000) + +struct tlv_privilege_mask_add_all_pfs { + uint32_t tag; + uint32_t length; + uint32_t privilege_mask_add; +}; + +/* Additional privileges given to a selected PF. + * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */ + +#define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf) (0x101A0000 + (pf)) + +struct tlv_privilege_mask_add_single_pf { + uint32_t tag; + uint32_t length; + uint32_t privilege_mask_add; +}; + +/* Turning on/off the PFIOV mode. + * This tag only takes effect if TLV_TAG_VSWITCH_TYPE is missing or set to DEFAULT. */ + +#define TLV_TAG_PFIOV(port) (0x10170000 + (port)) + +struct tlv_pfiov { + uint32_t tag; + uint32_t length; + uint32_t pfiov; +#define TLV_PFIOV_OFF (0) /* Default */ +#define TLV_PFIOV_ON (1) +}; + +/* Multicast filter chaining mode selection. + * + * When enabled, multicast packets are delivered to all recipients of all + * matching multicast filters, with the exception that IP multicast filters + * will steal traffic from MAC multicast filters on a per-function basis. + * (New behaviour.) + * + * When disabled, multicast packets will always be delivered only to the + * recipients of the highest priority matching multicast filter. + * (Legacy behaviour.) + * + * The DEFAULT mode (which is the same as the tag not being present at all) + * is equivalent to ENABLED in production builds, and DISABLED in eftest + * builds. + * + * This option is intended to provide run-time control over this feature + * while it is being stabilised and may be withdrawn at some point in the + * future; the new behaviour is intended to become the standard behaviour. + */ + +#define TLV_TAG_MCAST_FILTER_CHAINING (0x10180000) + +struct tlv_mcast_filter_chaining { + uint32_t tag; + uint32_t length; + uint32_t mode; +#define TLV_MCAST_FILTER_CHAINING_DEFAULT (0xffffffff) +#define TLV_MCAST_FILTER_CHAINING_DISABLED (0) +#define TLV_MCAST_FILTER_CHAINING_ENABLED (1) +}; + + +/* Pacer rate limit per PF */ +#define TLV_TAG_RATE_LIMIT(pf) (0x101b0000 + (pf)) + +struct tlv_rate_limit { + uint32_t tag; + uint32_t length; + uint32_t rate_mbps; +}; + + +/* OCSD Enable/Disable + * + * This setting allows OCSD to be disabled. This is a requirement for HP + * servers to support PCI passthrough for virtualization. + * + * The DEFAULT mode (which is the same as the tag not being present) is + * equivalent to ENABLED. + * + * This option is not used by the MCFW, and is entirely handled by the various + * drivers that support OCSD, by reading the setting before they attempt + * to enable OCSD. + * + * bit0: OCSD Disabled/Enabled + */ + +#define TLV_TAG_OCSD (0x101C0000) + +struct tlv_ocsd { + uint32_t tag; + uint32_t length; + uint32_t mode; +#define TLV_OCSD_DISABLED 0 +#define TLV_OCSD_ENABLED 1 /* Default */ +}; + +#endif /* CI_MGMT_TLV_LAYOUT_H */ Property changes on: head/sys/dev/sfxge/common/ef10_tlv_layout.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efsys.h =================================================================== --- head/sys/dev/sfxge/common/efsys.h (revision 283513) +++ head/sys/dev/sfxge/common/efsys.h (revision 283514) @@ -1,1171 +1,1227 @@ /*- - * Copyright (c) 2010-2011 Solarflare Communications, Inc. + * Copyright (c) 2010-2015 Solarflare Communications Inc. * All rights reserved. * * This software was developed in part by Philip Paeps under contract for * Solarflare Communications, Inc. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + * * $FreeBSD$ */ #ifndef _SYS_EFSYS_H #define _SYS_EFSYS_H #ifdef __cplusplus extern "C" { #endif #include #include #include #include #include #include #include #include #include #include #include #include #define EFSYS_HAS_UINT64 1 #if defined(__x86_64__) #define EFSYS_USE_UINT64 1 #else #define EFSYS_USE_UINT64 0 #endif +#define EFSYS_HAS_SSE2_M128 0 #if _BYTE_ORDER == _BIG_ENDIAN #define EFSYS_IS_BIG_ENDIAN 1 #define EFSYS_IS_LITTLE_ENDIAN 0 #elif _BYTE_ORDER == _LITTLE_ENDIAN #define EFSYS_IS_BIG_ENDIAN 0 #define EFSYS_IS_LITTLE_ENDIAN 1 #endif #include "efx_types.h" /* Common code requires this */ #if __FreeBSD_version < 800068 #define memmove(d, s, l) bcopy(s, d, l) #endif /* FreeBSD equivalents of Solaris things */ #ifndef _NOTE #define _NOTE(s) #endif #ifndef B_FALSE #define B_FALSE FALSE #endif #ifndef B_TRUE #define B_TRUE TRUE #endif #ifndef IS_P2ALIGNED #define IS_P2ALIGNED(v, a) ((((uintptr_t)(v)) & ((uintptr_t)(a) - 1)) == 0) #endif #ifndef P2ROUNDUP #define P2ROUNDUP(x, align) (-(-(x) & -(align))) #endif +#ifndef P2ALIGN +#define P2ALIGN(_x, _a) ((_x) & -(_a)) +#endif + #ifndef IS2P #define ISP2(x) (((x) & ((x) - 1)) == 0) #endif #if defined(__x86_64__) && __FreeBSD_version >= 1000000 #define SFXGE_USE_BUS_SPACE_8 1 #if !defined(bus_space_read_stream_8) #define bus_space_read_stream_8(t, h, o) \ bus_space_read_8((t), (h), (o)) #define bus_space_write_stream_8(t, h, o, v) \ bus_space_write_8((t), (h), (o), (v)) #endif #endif #define ENOTACTIVE EINVAL /* Memory type to use on FreeBSD */ MALLOC_DECLARE(M_SFXGE); /* Machine dependend prefetch wrappers */ #if defined(__i386__) || defined(__amd64__) static __inline void prefetch_read_many(void *addr) { __asm__( "prefetcht0 (%0)" : : "r" (addr)); } static __inline void prefetch_read_once(void *addr) { __asm__( "prefetchnta (%0)" : : "r" (addr)); } #elif defined(__sparc64__) static __inline void prefetch_read_many(void *addr) { __asm__( "prefetch [%0], 0" : : "r" (addr)); } static __inline void prefetch_read_once(void *addr) { __asm__( "prefetch [%0], 1" : : "r" (addr)); } #else static __inline void prefetch_read_many(void *addr) { } static __inline void prefetch_read_once(void *addr) { } #endif #if defined(__i386__) || defined(__amd64__) #include #include #endif static __inline void sfxge_map_mbuf_fast(bus_dma_tag_t tag, bus_dmamap_t map, - struct mbuf *m, bus_dma_segment_t *seg) + struct mbuf *m, bus_dma_segment_t *seg) { #if defined(__i386__) || defined(__amd64__) seg->ds_addr = pmap_kextract(mtod(m, vm_offset_t)); seg->ds_len = m->m_len; #else int nsegstmp; bus_dmamap_load_mbuf_sg(tag, map, m, seg, &nsegstmp, 0); #endif } -/* Modifiers used for DOS builds */ -#define __cs -#define __far - /* Modifiers used for Windows builds */ #define __in #define __in_opt #define __in_ecount(_n) #define __in_ecount_opt(_n) #define __in_bcount(_n) #define __in_bcount_opt(_n) #define __out #define __out_opt #define __out_ecount(_n) #define __out_ecount_opt(_n) #define __out_bcount(_n) #define __out_bcount_opt(_n) #define __deref_out #define __inout #define __inout_opt #define __inout_ecount(_n) #define __inout_ecount_opt(_n) #define __inout_bcount(_n) #define __inout_bcount_opt(_n) #define __inout_bcount_full_opt(_n) #define __deref_out_bcount_opt(n) #define __checkReturn #define __drv_when(_p, _c) /* Code inclusion options */ #define EFSYS_OPT_NAMES 1 #define EFSYS_OPT_FALCON 0 #define EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE 0 #define EFSYS_OPT_SIENA 1 +#define EFSYS_OPT_HUNTINGTON 1 #ifdef DEBUG #define EFSYS_OPT_CHECK_REG 1 #else #define EFSYS_OPT_CHECK_REG 0 #endif #define EFSYS_OPT_MCDI 1 #define EFSYS_OPT_MAC_FALCON_GMAC 0 #define EFSYS_OPT_MAC_FALCON_XMAC 0 #define EFSYS_OPT_MAC_STATS 1 #define EFSYS_OPT_LOOPBACK 0 #define EFSYS_OPT_MON_NULL 0 #define EFSYS_OPT_MON_LM87 0 #define EFSYS_OPT_MON_MAX6647 0 -#define EFSYS_OPT_MON_SIENA 0 +#define EFSYS_OPT_MON_MCDI 0 #define EFSYS_OPT_MON_STATS 0 #define EFSYS_OPT_PHY_NULL 0 #define EFSYS_OPT_PHY_QT2022C2 0 #define EFSYS_OPT_PHY_SFX7101 0 #define EFSYS_OPT_PHY_TXC43128 0 -#define EFSYS_OPT_PHY_PM8358 0 #define EFSYS_OPT_PHY_SFT9001 0 #define EFSYS_OPT_PHY_QT2025C 0 #define EFSYS_OPT_PHY_STATS 1 #define EFSYS_OPT_PHY_PROPS 0 -#define EFSYS_OPT_PHY_BIST 1 +#define EFSYS_OPT_PHY_BIST 0 +#define EFSYS_OPT_BIST 1 #define EFSYS_OPT_PHY_LED_CONTROL 1 #define EFSYS_OPT_PHY_FLAGS 0 #define EFSYS_OPT_VPD 1 #define EFSYS_OPT_NVRAM 1 #define EFSYS_OPT_NVRAM_FALCON_BOOTROM 0 #define EFSYS_OPT_NVRAM_SFT9001 0 #define EFSYS_OPT_NVRAM_SFX7101 0 #define EFSYS_OPT_BOOTCFG 0 #define EFSYS_OPT_PCIE_TUNE 0 #define EFSYS_OPT_DIAG 0 #define EFSYS_OPT_WOL 1 #define EFSYS_OPT_RX_SCALE 1 #define EFSYS_OPT_QSTATS 1 -#define EFSYS_OPT_FILTER 0 +#define EFSYS_OPT_FILTER 1 +#define EFSYS_OPT_MCAST_FILTER_LIST 1 #define EFSYS_OPT_RX_SCATTER 0 #define EFSYS_OPT_RX_HDR_SPLIT 0 #define EFSYS_OPT_EV_PREFETCH 0 #define EFSYS_OPT_DECODE_INTR_FATAL 1 /* ID */ typedef struct __efsys_identifier_s efsys_identifier_t; /* PROBE */ #ifndef DTRACE_PROBE #define EFSYS_PROBE(_name) #define EFSYS_PROBE1(_name, _type1, _arg1) #define EFSYS_PROBE2(_name, _type1, _arg1, _type2, _arg2) #define EFSYS_PROBE3(_name, _type1, _arg1, _type2, _arg2, \ _type3, _arg3) #define EFSYS_PROBE4(_name, _type1, _arg1, _type2, _arg2, \ _type3, _arg3, _type4, _arg4) #define EFSYS_PROBE5(_name, _type1, _arg1, _type2, _arg2, \ _type3, _arg3, _type4, _arg4, _type5, _arg5) #define EFSYS_PROBE6(_name, _type1, _arg1, _type2, _arg2, \ _type3, _arg3, _type4, _arg4, _type5, _arg5, \ _type6, _arg6) #define EFSYS_PROBE7(_name, _type1, _arg1, _type2, _arg2, \ _type3, _arg3, _type4, _arg4, _type5, _arg5, \ _type6, _arg6, _type7, _arg7) #else /* DTRACE_PROBE */ #define EFSYS_PROBE(_name) \ DTRACE_PROBE(_name) #define EFSYS_PROBE1(_name, _type1, _arg1) \ DTRACE_PROBE1(_name, _type1, _arg1) #define EFSYS_PROBE2(_name, _type1, _arg1, _type2, _arg2) \ DTRACE_PROBE2(_name, _type1, _arg1, _type2, _arg2) #define EFSYS_PROBE3(_name, _type1, _arg1, _type2, _arg2, \ _type3, _arg3) \ DTRACE_PROBE3(_name, _type1, _arg1, _type2, _arg2, \ _type3, _arg3) #define EFSYS_PROBE4(_name, _type1, _arg1, _type2, _arg2, \ _type3, _arg3, _type4, _arg4) \ DTRACE_PROBE4(_name, _type1, _arg1, _type2, _arg2, \ _type3, _arg3, _type4, _arg4) #ifdef DTRACE_PROBE5 #define EFSYS_PROBE5(_name, _type1, _arg1, _type2, _arg2, \ _type3, _arg3, _type4, _arg4, _type5, _arg5) \ DTRACE_PROBE5(_name, _type1, _arg1, _type2, _arg2, \ _type3, _arg3, _type4, _arg4, _type5, _arg5) #else #define EFSYS_PROBE5(_name, _type1, _arg1, _type2, _arg2, \ _type3, _arg3, _type4, _arg4, _type5, _arg5) \ DTRACE_PROBE4(_name, _type1, _arg1, _type2, _arg2, \ _type3, _arg3, _type4, _arg4) #endif #ifdef DTRACE_PROBE6 #define EFSYS_PROBE6(_name, _type1, _arg1, _type2, _arg2, \ _type3, _arg3, _type4, _arg4, _type5, _arg5, \ _type6, _arg6) \ DTRACE_PROBE6(_name, _type1, _arg1, _type2, _arg2, \ _type3, _arg3, _type4, _arg4, _type5, _arg5, \ _type6, _arg6) #else #define EFSYS_PROBE6(_name, _type1, _arg1, _type2, _arg2, \ _type3, _arg3, _type4, _arg4, _type5, _arg5, \ _type6, _arg6) \ EFSYS_PROBE5(_name, _type1, _arg1, _type2, _arg2, \ _type3, _arg3, _type4, _arg4, _type5, _arg5) #endif #ifdef DTRACE_PROBE7 #define EFSYS_PROBE7(_name, _type1, _arg1, _type2, _arg2, \ _type3, _arg3, _type4, _arg4, _type5, _arg5, \ _type6, _arg6, _type7, _arg7) \ DTRACE_PROBE7(_name, _type1, _arg1, _type2, _arg2, \ _type3, _arg3, _type4, _arg4, _type5, _arg5, \ _type6, _arg6, _type7, _arg7) #else #define EFSYS_PROBE7(_name, _type1, _arg1, _type2, _arg2, \ _type3, _arg3, _type4, _arg4, _type5, _arg5, \ _type6, _arg6, _type7, _arg7) \ EFSYS_PROBE6(_name, _type1, _arg1, _type2, _arg2, \ _type3, _arg3, _type4, _arg4, _type5, _arg5, \ _type6, _arg6) #endif #endif /* DTRACE_PROBE */ /* DMA */ typedef uint64_t efsys_dma_addr_t; typedef struct efsys_mem_s { bus_dma_tag_t esm_tag; bus_dmamap_t esm_map; caddr_t esm_base; efsys_dma_addr_t esm_addr; } efsys_mem_t; #define EFSYS_MEM_ZERO(_esmp, _size) \ do { \ (void) memset((_esmp)->esm_base, 0, (_size)); \ \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFSYS_MEM_READD(_esmp, _offset, _edp) \ do { \ uint32_t *addr; \ \ _NOTE(CONSTANTCONDITION) \ KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_dword_t)), \ ("not power of 2 aligned")); \ \ addr = (void *)((_esmp)->esm_base + (_offset)); \ \ (_edp)->ed_u32[0] = *addr; \ \ EFSYS_PROBE2(mem_readd, unsigned int, (_offset), \ uint32_t, (_edp)->ed_u32[0]); \ \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #if defined(__x86_64__) #define EFSYS_MEM_READQ(_esmp, _offset, _eqp) \ do { \ uint64_t *addr; \ \ _NOTE(CONSTANTCONDITION) \ KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_qword_t)), \ ("not power of 2 aligned")); \ \ addr = (void *)((_esmp)->esm_base + (_offset)); \ \ (_eqp)->eq_u64[0] = *addr; \ \ EFSYS_PROBE3(mem_readq, unsigned int, (_offset), \ uint32_t, (_eqp)->eq_u32[1], \ uint32_t, (_eqp)->eq_u32[0]); \ \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #else #define EFSYS_MEM_READQ(_esmp, _offset, _eqp) \ do { \ uint32_t *addr; \ \ _NOTE(CONSTANTCONDITION) \ KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_qword_t)), \ ("not power of 2 aligned")); \ \ addr = (void *)((_esmp)->esm_base + (_offset)); \ \ (_eqp)->eq_u32[0] = *addr++; \ (_eqp)->eq_u32[1] = *addr; \ \ EFSYS_PROBE3(mem_readq, unsigned int, (_offset), \ uint32_t, (_eqp)->eq_u32[1], \ uint32_t, (_eqp)->eq_u32[0]); \ \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #endif #if defined(__x86_64__) #define EFSYS_MEM_READO(_esmp, _offset, _eop) \ do { \ uint64_t *addr; \ \ _NOTE(CONSTANTCONDITION) \ KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_oword_t)), \ ("not power of 2 aligned")); \ \ addr = (void *)((_esmp)->esm_base + (_offset)); \ \ (_eop)->eo_u64[0] = *addr++; \ (_eop)->eo_u64[1] = *addr; \ \ EFSYS_PROBE5(mem_reado, unsigned int, (_offset), \ uint32_t, (_eop)->eo_u32[3], \ uint32_t, (_eop)->eo_u32[2], \ uint32_t, (_eop)->eo_u32[1], \ uint32_t, (_eop)->eo_u32[0]); \ \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #else #define EFSYS_MEM_READO(_esmp, _offset, _eop) \ do { \ uint32_t *addr; \ \ _NOTE(CONSTANTCONDITION) \ KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_oword_t)), \ ("not power of 2 aligned")); \ \ addr = (void *)((_esmp)->esm_base + (_offset)); \ \ (_eop)->eo_u32[0] = *addr++; \ (_eop)->eo_u32[1] = *addr++; \ (_eop)->eo_u32[2] = *addr++; \ (_eop)->eo_u32[3] = *addr; \ \ EFSYS_PROBE5(mem_reado, unsigned int, (_offset), \ uint32_t, (_eop)->eo_u32[3], \ uint32_t, (_eop)->eo_u32[2], \ uint32_t, (_eop)->eo_u32[1], \ uint32_t, (_eop)->eo_u32[0]); \ \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #endif #define EFSYS_MEM_WRITED(_esmp, _offset, _edp) \ do { \ uint32_t *addr; \ \ _NOTE(CONSTANTCONDITION) \ KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_dword_t)), \ ("not power of 2 aligned")); \ \ EFSYS_PROBE2(mem_writed, unsigned int, (_offset), \ uint32_t, (_edp)->ed_u32[0]); \ \ addr = (void *)((_esmp)->esm_base + (_offset)); \ \ *addr = (_edp)->ed_u32[0]; \ \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #if defined(__x86_64__) #define EFSYS_MEM_WRITEQ(_esmp, _offset, _eqp) \ do { \ uint64_t *addr; \ \ _NOTE(CONSTANTCONDITION) \ KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_qword_t)), \ ("not power of 2 aligned")); \ \ EFSYS_PROBE3(mem_writeq, unsigned int, (_offset), \ uint32_t, (_eqp)->eq_u32[1], \ uint32_t, (_eqp)->eq_u32[0]); \ \ addr = (void *)((_esmp)->esm_base + (_offset)); \ \ *addr = (_eqp)->eq_u64[0]; \ \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #else #define EFSYS_MEM_WRITEQ(_esmp, _offset, _eqp) \ do { \ uint32_t *addr; \ \ _NOTE(CONSTANTCONDITION) \ KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_qword_t)), \ ("not power of 2 aligned")); \ \ EFSYS_PROBE3(mem_writeq, unsigned int, (_offset), \ uint32_t, (_eqp)->eq_u32[1], \ uint32_t, (_eqp)->eq_u32[0]); \ \ addr = (void *)((_esmp)->esm_base + (_offset)); \ \ *addr++ = (_eqp)->eq_u32[0]; \ *addr = (_eqp)->eq_u32[1]; \ \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #endif #if defined(__x86_64__) #define EFSYS_MEM_WRITEO(_esmp, _offset, _eop) \ do { \ uint64_t *addr; \ \ _NOTE(CONSTANTCONDITION) \ KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_oword_t)), \ ("not power of 2 aligned")); \ \ EFSYS_PROBE5(mem_writeo, unsigned int, (_offset), \ uint32_t, (_eop)->eo_u32[3], \ uint32_t, (_eop)->eo_u32[2], \ uint32_t, (_eop)->eo_u32[1], \ uint32_t, (_eop)->eo_u32[0]); \ \ addr = (void *)((_esmp)->esm_base + (_offset)); \ \ *addr++ = (_eop)->eo_u64[0]; \ *addr = (_eop)->eo_u64[1]; \ \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #else #define EFSYS_MEM_WRITEO(_esmp, _offset, _eop) \ do { \ uint32_t *addr; \ \ _NOTE(CONSTANTCONDITION) \ KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_oword_t)), \ ("not power of 2 aligned")); \ \ EFSYS_PROBE5(mem_writeo, unsigned int, (_offset), \ uint32_t, (_eop)->eo_u32[3], \ uint32_t, (_eop)->eo_u32[2], \ uint32_t, (_eop)->eo_u32[1], \ uint32_t, (_eop)->eo_u32[0]); \ \ addr = (void *)((_esmp)->esm_base + (_offset)); \ \ *addr++ = (_eop)->eo_u32[0]; \ *addr++ = (_eop)->eo_u32[1]; \ *addr++ = (_eop)->eo_u32[2]; \ *addr = (_eop)->eo_u32[3]; \ \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #endif #define EFSYS_MEM_ADDR(_esmp) \ ((_esmp)->esm_addr) +#define EFSYS_MEM_IS_NULL(_esmp) \ + ((_esmp)->esm_base == NULL) + /* BAR */ #define SFXGE_LOCK_NAME_MAX 16 typedef struct efsys_bar_s { struct mtx esb_lock; char esb_lock_name[SFXGE_LOCK_NAME_MAX]; bus_space_tag_t esb_tag; bus_space_handle_t esb_handle; int esb_rid; struct resource *esb_res; } efsys_bar_t; #define SFXGE_BAR_LOCK_INIT(_esbp, _ifname) \ do { \ snprintf((_esbp)->esb_lock_name, \ sizeof((_esbp)->esb_lock_name), \ "%s:bar", (_ifname)); \ mtx_init(&(_esbp)->esb_lock, (_esbp)->esb_lock_name, \ NULL, MTX_DEF); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define SFXGE_BAR_LOCK_DESTROY(_esbp) \ mtx_destroy(&(_esbp)->esb_lock) #define SFXGE_BAR_LOCK(_esbp) \ mtx_lock(&(_esbp)->esb_lock) #define SFXGE_BAR_UNLOCK(_esbp) \ mtx_unlock(&(_esbp)->esb_lock) #define EFSYS_BAR_READD(_esbp, _offset, _edp, _lock) \ do { \ _NOTE(CONSTANTCONDITION) \ KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_dword_t)), \ ("not power of 2 aligned")); \ \ _NOTE(CONSTANTCONDITION) \ if (_lock) \ SFXGE_BAR_LOCK(_esbp); \ \ (_edp)->ed_u32[0] = bus_space_read_stream_4( \ (_esbp)->esb_tag, (_esbp)->esb_handle, \ (_offset)); \ \ EFSYS_PROBE2(bar_readd, unsigned int, (_offset), \ uint32_t, (_edp)->ed_u32[0]); \ \ _NOTE(CONSTANTCONDITION) \ if (_lock) \ SFXGE_BAR_UNLOCK(_esbp); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #if defined(SFXGE_USE_BUS_SPACE_8) #define EFSYS_BAR_READQ(_esbp, _offset, _eqp) \ do { \ _NOTE(CONSTANTCONDITION) \ KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_qword_t)), \ ("not power of 2 aligned")); \ \ SFXGE_BAR_LOCK(_esbp); \ \ (_eqp)->eq_u64[0] = bus_space_read_stream_8( \ (_esbp)->esb_tag, (_esbp)->esb_handle, \ (_offset)); \ \ EFSYS_PROBE3(bar_readq, unsigned int, (_offset), \ uint32_t, (_eqp)->eq_u32[1], \ uint32_t, (_eqp)->eq_u32[0]); \ \ SFXGE_BAR_UNLOCK(_esbp); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFSYS_BAR_READO(_esbp, _offset, _eop, _lock) \ do { \ _NOTE(CONSTANTCONDITION) \ KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_oword_t)), \ ("not power of 2 aligned")); \ \ _NOTE(CONSTANTCONDITION) \ if (_lock) \ SFXGE_BAR_LOCK(_esbp); \ \ (_eop)->eo_u64[0] = bus_space_read_stream_8( \ (_esbp)->esb_tag, (_esbp)->esb_handle, \ (_offset)); \ (_eop)->eo_u64[1] = bus_space_read_stream_8( \ (_esbp)->esb_tag, (_esbp)->esb_handle, \ (_offset) + 8); \ \ EFSYS_PROBE5(bar_reado, unsigned int, (_offset), \ uint32_t, (_eop)->eo_u32[3], \ uint32_t, (_eop)->eo_u32[2], \ uint32_t, (_eop)->eo_u32[1], \ uint32_t, (_eop)->eo_u32[0]); \ \ _NOTE(CONSTANTCONDITION) \ if (_lock) \ SFXGE_BAR_UNLOCK(_esbp); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #else #define EFSYS_BAR_READQ(_esbp, _offset, _eqp) \ do { \ _NOTE(CONSTANTCONDITION) \ KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_qword_t)), \ ("not power of 2 aligned")); \ \ SFXGE_BAR_LOCK(_esbp); \ \ (_eqp)->eq_u32[0] = bus_space_read_stream_4( \ (_esbp)->esb_tag, (_esbp)->esb_handle, \ (_offset)); \ (_eqp)->eq_u32[1] = bus_space_read_stream_4( \ (_esbp)->esb_tag, (_esbp)->esb_handle, \ (_offset) + 4); \ \ EFSYS_PROBE3(bar_readq, unsigned int, (_offset), \ uint32_t, (_eqp)->eq_u32[1], \ uint32_t, (_eqp)->eq_u32[0]); \ \ SFXGE_BAR_UNLOCK(_esbp); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFSYS_BAR_READO(_esbp, _offset, _eop, _lock) \ do { \ _NOTE(CONSTANTCONDITION) \ KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_oword_t)), \ ("not power of 2 aligned")); \ \ _NOTE(CONSTANTCONDITION) \ if (_lock) \ SFXGE_BAR_LOCK(_esbp); \ \ (_eop)->eo_u32[0] = bus_space_read_stream_4( \ (_esbp)->esb_tag, (_esbp)->esb_handle, \ (_offset)); \ (_eop)->eo_u32[1] = bus_space_read_stream_4( \ (_esbp)->esb_tag, (_esbp)->esb_handle, \ (_offset) + 4); \ (_eop)->eo_u32[2] = bus_space_read_stream_4( \ (_esbp)->esb_tag, (_esbp)->esb_handle, \ (_offset) + 8); \ (_eop)->eo_u32[3] = bus_space_read_stream_4( \ (_esbp)->esb_tag, (_esbp)->esb_handle, \ (_offset) + 12); \ \ EFSYS_PROBE5(bar_reado, unsigned int, (_offset), \ uint32_t, (_eop)->eo_u32[3], \ uint32_t, (_eop)->eo_u32[2], \ uint32_t, (_eop)->eo_u32[1], \ uint32_t, (_eop)->eo_u32[0]); \ \ _NOTE(CONSTANTCONDITION) \ if (_lock) \ SFXGE_BAR_UNLOCK(_esbp); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #endif #define EFSYS_BAR_WRITED(_esbp, _offset, _edp, _lock) \ do { \ _NOTE(CONSTANTCONDITION) \ KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_dword_t)), \ ("not power of 2 aligned")); \ \ _NOTE(CONSTANTCONDITION) \ if (_lock) \ SFXGE_BAR_LOCK(_esbp); \ \ EFSYS_PROBE2(bar_writed, unsigned int, (_offset), \ uint32_t, (_edp)->ed_u32[0]); \ \ /* \ * Make sure that previous writes to the dword have \ * been done. It should be cheaper than barrier just \ * after the write below. \ */ \ bus_space_barrier((_esbp)->esb_tag, (_esbp)->esb_handle,\ (_offset), sizeof (efx_dword_t), \ BUS_SPACE_BARRIER_WRITE); \ bus_space_write_stream_4((_esbp)->esb_tag, \ (_esbp)->esb_handle, \ (_offset), (_edp)->ed_u32[0]); \ \ _NOTE(CONSTANTCONDITION) \ if (_lock) \ SFXGE_BAR_UNLOCK(_esbp); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #if defined(SFXGE_USE_BUS_SPACE_8) #define EFSYS_BAR_WRITEQ(_esbp, _offset, _eqp) \ do { \ _NOTE(CONSTANTCONDITION) \ KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_qword_t)), \ ("not power of 2 aligned")); \ \ SFXGE_BAR_LOCK(_esbp); \ \ EFSYS_PROBE3(bar_writeq, unsigned int, (_offset), \ uint32_t, (_eqp)->eq_u32[1], \ uint32_t, (_eqp)->eq_u32[0]); \ \ /* \ * Make sure that previous writes to the qword have \ * been done. It should be cheaper than barrier just \ * after the write below. \ */ \ bus_space_barrier((_esbp)->esb_tag, (_esbp)->esb_handle,\ (_offset), sizeof (efx_qword_t), \ BUS_SPACE_BARRIER_WRITE); \ bus_space_write_stream_8((_esbp)->esb_tag, \ (_esbp)->esb_handle, \ (_offset), (_eqp)->eq_u64[0]); \ \ SFXGE_BAR_UNLOCK(_esbp); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #else #define EFSYS_BAR_WRITEQ(_esbp, _offset, _eqp) \ do { \ _NOTE(CONSTANTCONDITION) \ KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_qword_t)), \ ("not power of 2 aligned")); \ \ SFXGE_BAR_LOCK(_esbp); \ \ EFSYS_PROBE3(bar_writeq, unsigned int, (_offset), \ uint32_t, (_eqp)->eq_u32[1], \ uint32_t, (_eqp)->eq_u32[0]); \ \ /* \ * Make sure that previous writes to the qword have \ * been done. It should be cheaper than barrier just \ * after the last write below. \ */ \ bus_space_barrier((_esbp)->esb_tag, (_esbp)->esb_handle,\ (_offset), sizeof (efx_qword_t), \ BUS_SPACE_BARRIER_WRITE); \ bus_space_write_stream_4((_esbp)->esb_tag, \ (_esbp)->esb_handle, \ (_offset), (_eqp)->eq_u32[0]); \ /* \ * It should be guaranteed that the last dword comes \ * the last, so barrier entire qword to be sure that \ * neither above nor below writes are reordered. \ */ \ bus_space_barrier((_esbp)->esb_tag, (_esbp)->esb_handle,\ (_offset), sizeof (efx_qword_t), \ BUS_SPACE_BARRIER_WRITE); \ bus_space_write_stream_4((_esbp)->esb_tag, \ (_esbp)->esb_handle, \ (_offset) + 4, (_eqp)->eq_u32[1]); \ \ SFXGE_BAR_UNLOCK(_esbp); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #endif +/* + * Guarantees 64bit aligned 64bit writes to write combined BAR mapping + * (required by PIO hardware) + */ +#define EFSYS_BAR_WC_WRITEQ(_esbp, _offset, _eqp) \ + do { \ + _NOTE(CONSTANTCONDITION) \ + KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_qword_t)), \ + ("not power of 2 aligned")); \ + \ + (void) (_esbp); \ + \ + /* FIXME: Perform a 64-bit write */ \ + KASSERT(0, ("not implemented")); \ + \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + #if defined(SFXGE_USE_BUS_SPACE_8) #define EFSYS_BAR_WRITEO(_esbp, _offset, _eop, _lock) \ do { \ _NOTE(CONSTANTCONDITION) \ KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_oword_t)), \ ("not power of 2 aligned")); \ \ _NOTE(CONSTANTCONDITION) \ if (_lock) \ SFXGE_BAR_LOCK(_esbp); \ \ EFSYS_PROBE5(bar_writeo, unsigned int, (_offset), \ uint32_t, (_eop)->eo_u32[3], \ uint32_t, (_eop)->eo_u32[2], \ uint32_t, (_eop)->eo_u32[1], \ uint32_t, (_eop)->eo_u32[0]); \ \ /* \ * Make sure that previous writes to the oword have \ * been done. It should be cheaper than barrier just \ * after the last write below. \ */ \ bus_space_barrier((_esbp)->esb_tag, (_esbp)->esb_handle,\ (_offset), sizeof (efx_oword_t), \ BUS_SPACE_BARRIER_WRITE); \ bus_space_write_stream_8((_esbp)->esb_tag, \ (_esbp)->esb_handle, \ (_offset), (_eop)->eo_u64[0]); \ /* \ * It should be guaranteed that the last qword comes \ * the last, so barrier entire oword to be sure that \ * neither above nor below writes are reordered. \ */ \ bus_space_barrier((_esbp)->esb_tag, (_esbp)->esb_handle,\ (_offset), sizeof (efx_oword_t), \ BUS_SPACE_BARRIER_WRITE); \ bus_space_write_stream_8((_esbp)->esb_tag, \ (_esbp)->esb_handle, \ (_offset) + 8, (_eop)->eo_u64[1]); \ \ _NOTE(CONSTANTCONDITION) \ if (_lock) \ SFXGE_BAR_UNLOCK(_esbp); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #else #define EFSYS_BAR_WRITEO(_esbp, _offset, _eop, _lock) \ do { \ _NOTE(CONSTANTCONDITION) \ KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_oword_t)), \ ("not power of 2 aligned")); \ \ _NOTE(CONSTANTCONDITION) \ if (_lock) \ SFXGE_BAR_LOCK(_esbp); \ \ EFSYS_PROBE5(bar_writeo, unsigned int, (_offset), \ uint32_t, (_eop)->eo_u32[3], \ uint32_t, (_eop)->eo_u32[2], \ uint32_t, (_eop)->eo_u32[1], \ uint32_t, (_eop)->eo_u32[0]); \ \ /* \ * Make sure that previous writes to the oword have \ * been done. It should be cheaper than barrier just \ * after the last write below. \ */ \ bus_space_barrier((_esbp)->esb_tag, (_esbp)->esb_handle,\ (_offset), sizeof (efx_oword_t), \ BUS_SPACE_BARRIER_WRITE); \ bus_space_write_stream_4((_esbp)->esb_tag, \ (_esbp)->esb_handle, \ (_offset), (_eop)->eo_u32[0]); \ bus_space_write_stream_4((_esbp)->esb_tag, \ (_esbp)->esb_handle, \ (_offset) + 4, (_eop)->eo_u32[1]); \ bus_space_write_stream_4((_esbp)->esb_tag, \ (_esbp)->esb_handle, \ (_offset) + 8, (_eop)->eo_u32[2]); \ /* \ * It should be guaranteed that the last dword comes \ * the last, so barrier entire oword to be sure that \ * neither above nor below writes are reordered. \ */ \ bus_space_barrier((_esbp)->esb_tag, (_esbp)->esb_handle,\ (_offset), sizeof (efx_oword_t), \ BUS_SPACE_BARRIER_WRITE); \ bus_space_write_stream_4((_esbp)->esb_tag, \ (_esbp)->esb_handle, \ (_offset) + 12, (_eop)->eo_u32[3]); \ \ _NOTE(CONSTANTCONDITION) \ if (_lock) \ SFXGE_BAR_UNLOCK(_esbp); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #endif +/* Use the standard octo-word write for doorbell writes */ +#define EFSYS_BAR_DOORBELL_WRITEO(_esbp, _offset, _eop) \ + do { \ + EFSYS_BAR_WRITEO((_esbp), (_offset), (_eop), B_FALSE); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + /* SPIN */ #define EFSYS_SPIN(_us) \ do { \ DELAY(_us); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFSYS_SLEEP EFSYS_SPIN /* BARRIERS */ #define EFSYS_MEM_READ_BARRIER() rmb() #define EFSYS_PIO_WRITE_BARRIER() +/* DMA SYNC */ +#define EFSYS_DMA_SYNC_FOR_KERNEL(_esmp, _offset, _size) \ + do { \ + bus_dmamap_sync((_esmp)->esm_tag, \ + (_esmp)->esm_map, \ + BUS_DMASYNC_POSTREAD); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_DMA_SYNC_FOR_DEVICE(_esmp, _offset, _size) \ + do { \ + bus_dmamap_sync((_esmp)->esm_tag, \ + (_esmp)->esm_map, \ + BUS_DMASYNC_PREWRITE); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + /* TIMESTAMP */ typedef clock_t efsys_timestamp_t; #define EFSYS_TIMESTAMP(_usp) \ do { \ clock_t now; \ \ now = ticks; \ *(_usp) = now * hz / 1000000; \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) /* KMEM */ #define EFSYS_KMEM_ALLOC(_esip, _size, _p) \ do { \ (_esip) = (_esip); \ /* \ * The macro is used in non-sleepable contexts, for \ * example, holding a mutex. \ */ \ (_p) = malloc((_size), M_SFXGE, M_NOWAIT|M_ZERO); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFSYS_KMEM_FREE(_esip, _size, _p) \ do { \ (void) (_esip); \ (void) (_size); \ free((_p), M_SFXGE); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) /* LOCK */ typedef struct efsys_lock_s { struct mtx lock; char lock_name[SFXGE_LOCK_NAME_MAX]; } efsys_lock_t; #define SFXGE_EFSYS_LOCK_INIT(_eslp, _ifname, _label) \ do { \ efsys_lock_t *__eslp = (_eslp); \ \ snprintf((__eslp)->lock_name, \ sizeof((__eslp)->lock_name), \ "%s:%s", (_ifname), (_label)); \ mtx_init(&(__eslp)->lock, (__eslp)->lock_name, \ NULL, MTX_DEF); \ } while (B_FALSE) #define SFXGE_EFSYS_LOCK_DESTROY(_eslp) \ mtx_destroy(&(_eslp)->lock) #define SFXGE_EFSYS_LOCK(_eslp) \ mtx_lock(&(_eslp)->lock) #define SFXGE_EFSYS_UNLOCK(_eslp) \ mtx_unlock(&(_eslp)->lock) #define SFXGE_EFSYS_LOCK_ASSERT_OWNED(_eslp) \ mtx_assert(&(_eslp)->lock, MA_OWNED) #define EFSYS_LOCK_MAGIC 0x000010c4 #define EFSYS_LOCK(_lockp, _state) \ do { \ SFXGE_EFSYS_LOCK(_lockp); \ (_state) = EFSYS_LOCK_MAGIC; \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFSYS_UNLOCK(_lockp, _state) \ do { \ if ((_state) != EFSYS_LOCK_MAGIC) \ KASSERT(B_FALSE, ("not locked")); \ SFXGE_EFSYS_UNLOCK(_lockp); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) /* PREEMPT */ #define EFSYS_PREEMPT_DISABLE(_state) \ do { \ (_state) = (_state); \ critical_enter(); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFSYS_PREEMPT_ENABLE(_state) \ do { \ (_state) = (_state); \ critical_exit(_state); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) /* STAT */ typedef uint64_t efsys_stat_t; #define EFSYS_STAT_INCR(_knp, _delta) \ do { \ *(_knp) += (_delta); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFSYS_STAT_DECR(_knp, _delta) \ do { \ *(_knp) -= (_delta); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFSYS_STAT_SET(_knp, _val) \ do { \ *(_knp) = (_val); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFSYS_STAT_SET_QWORD(_knp, _valp) \ do { \ *(_knp) = le64toh((_valp)->eq_u64[0]); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFSYS_STAT_SET_DWORD(_knp, _valp) \ do { \ *(_knp) = le32toh((_valp)->ed_u32[0]); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFSYS_STAT_INCR_QWORD(_knp, _valp) \ do { \ *(_knp) += le64toh((_valp)->eq_u64[0]); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFSYS_STAT_SUBR_QWORD(_knp, _valp) \ do { \ *(_knp) -= le64toh((_valp)->eq_u64[0]); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) /* ERR */ extern void sfxge_err(efsys_identifier_t *, unsigned int, uint32_t, uint32_t); #if EFSYS_OPT_DECODE_INTR_FATAL #define EFSYS_ERR(_esip, _code, _dword0, _dword1) \ do { \ sfxge_err((_esip), (_code), (_dword0), (_dword1)); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #endif /* ASSERT */ #define EFSYS_ASSERT(_exp) do { \ if (!(_exp)) \ - panic(#_exp); \ + panic("%s", #_exp); \ } while (0) #define EFSYS_ASSERT3(_x, _op, _y, _t) do { \ const _t __x = (_t)(_x); \ const _t __y = (_t)(_y); \ if (!(__x _op __y)) \ panic("assertion failed at %s:%u", __FILE__, __LINE__); \ } while(0) #define EFSYS_ASSERT3U(_x, _op, _y) EFSYS_ASSERT3(_x, _op, _y, uint64_t) #define EFSYS_ASSERT3S(_x, _op, _y) EFSYS_ASSERT3(_x, _op, _y, int64_t) #define EFSYS_ASSERT3P(_x, _op, _y) EFSYS_ASSERT3(_x, _op, _y, uintptr_t) + +/* ROTATE */ + +#define EFSYS_HAS_ROTL_DWORD 0 #ifdef __cplusplus } #endif #endif /* _SYS_EFSYS_H */ Property changes on: head/sys/dev/sfxge/common/efsys.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx.h =================================================================== --- head/sys/dev/sfxge/common/efx.h (revision 283513) +++ head/sys/dev/sfxge/common/efx.h (revision 283514) @@ -1,1923 +1,2300 @@ /*- - * Copyright 2006-2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2006-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + * * $FreeBSD$ */ #ifndef _SYS_EFX_H #define _SYS_EFX_H #include "efsys.h" +#include "efx_phy_ids.h" #ifdef __cplusplus extern "C" { #endif #define EFX_STATIC_ASSERT(_cond) ((void)sizeof(char[(_cond) ? 1 : -1])) #define EFX_ARRAY_SIZE(_array) (sizeof(_array) / sizeof((_array)[0])) -#ifndef EFSYS_MEM_IS_NULL -#define EFSYS_MEM_IS_NULL(_esmp) ((_esmp)->esm_base == NULL) -#endif +#define EFX_FIELD_OFFSET(_type, _field) ((size_t) &(((_type *)0)->_field)) typedef enum efx_family_e { EFX_FAMILY_INVALID, EFX_FAMILY_FALCON, EFX_FAMILY_SIENA, + EFX_FAMILY_HUNTINGTON, EFX_FAMILY_NTYPES } efx_family_t; extern __checkReturn int efx_family( __in uint16_t venid, __in uint16_t devid, __out efx_family_t *efp); extern __checkReturn int efx_infer_family( __in efsys_bar_t *esbp, __out efx_family_t *efp); -#define EFX_PCI_VENID_SFC 0x1924 -#define EFX_PCI_DEVID_FALCON 0x0710 -#define EFX_PCI_DEVID_BETHPAGE 0x0803 -#define EFX_PCI_DEVID_SIENA 0x0813 -#define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 +#define EFX_PCI_VENID_SFC 0x1924 +#define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */ + +#define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */ +#define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */ +#define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 + +#define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901 +#define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */ +#define EFX_PCI_DEVID_HUNTINGTON 0x0913 /* SFL9122 PF */ +#define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */ + +#define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */ +#define EFX_PCI_DEVID_HUNTINGTON_VF 0x1913 /* SFL9122 VF */ +#define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */ + + #define EFX_MEM_BAR 2 /* Error codes */ enum { EFX_ERR_INVALID, EFX_ERR_SRAM_OOB, EFX_ERR_BUFID_DC_OOB, EFX_ERR_MEM_PERR, EFX_ERR_RBUF_OWN, EFX_ERR_TBUF_OWN, EFX_ERR_RDESQ_OWN, EFX_ERR_TDESQ_OWN, EFX_ERR_EVQ_OWN, EFX_ERR_EVFF_OFLO, EFX_ERR_ILL_ADDR, EFX_ERR_SRAM_PERR, EFX_ERR_NCODES }; +/* Calculate the IEEE 802.3 CRC32 of a MAC addr */ +extern __checkReturn uint32_t +efx_crc32_calculate( + __in uint32_t crc_init, + __in_ecount(length) uint8_t const *input, + __in int length); + + +/* Type prototypes */ + +typedef struct efx_rxq_s efx_rxq_t; + /* NIC */ typedef struct efx_nic_s efx_nic_t; +#define EFX_NIC_FUNC_PRIMARY 0x00000001 +#define EFX_NIC_FUNC_LINKCTRL 0x00000002 +#define EFX_NIC_FUNC_TRUSTED 0x00000004 + + extern __checkReturn int efx_nic_create( __in efx_family_t family, __in efsys_identifier_t *esip, __in efsys_bar_t *esbp, __in efsys_lock_t *eslp, __deref_out efx_nic_t **enpp); extern __checkReturn int efx_nic_probe( __in efx_nic_t *enp); #if EFSYS_OPT_PCIE_TUNE extern __checkReturn int efx_nic_pcie_tune( __in efx_nic_t *enp, unsigned int nlanes); extern __checkReturn int efx_nic_pcie_extended_sync( __in efx_nic_t *enp); #endif /* EFSYS_OPT_PCIE_TUNE */ extern __checkReturn int efx_nic_init( __in efx_nic_t *enp); extern __checkReturn int efx_nic_reset( __in efx_nic_t *enp); #if EFSYS_OPT_DIAG extern __checkReturn int efx_nic_register_test( __in efx_nic_t *enp); #endif /* EFSYS_OPT_DIAG */ extern void efx_nic_fini( __in efx_nic_t *enp); extern void efx_nic_unprobe( __in efx_nic_t *enp); extern void efx_nic_destroy( __in efx_nic_t *enp); #if EFSYS_OPT_MCDI +#if EFSYS_OPT_HUNTINGTON +/* Huntington requires MCDIv2 commands */ +#define WITH_MCDI_V2 1 +#endif + typedef struct efx_mcdi_req_s efx_mcdi_req_t; typedef enum efx_mcdi_exception_e { EFX_MCDI_EXCEPTION_MC_REBOOT, EFX_MCDI_EXCEPTION_MC_BADASSERT, } efx_mcdi_exception_t; typedef struct efx_mcdi_transport_s { void *emt_context; + efsys_mem_t *emt_dma_mem; void (*emt_execute)(void *, efx_mcdi_req_t *); void (*emt_ev_cpl)(void *); void (*emt_exception)(void *, efx_mcdi_exception_t); } efx_mcdi_transport_t; extern __checkReturn int efx_mcdi_init( __in efx_nic_t *enp, __in const efx_mcdi_transport_t *mtp); extern __checkReturn int efx_mcdi_reboot( __in efx_nic_t *enp); + void +efx_mcdi_new_epoch( + __in efx_nic_t *enp); + extern void efx_mcdi_request_start( __in efx_nic_t *enp, __in efx_mcdi_req_t *emrp, __in boolean_t ev_cpl); extern __checkReturn boolean_t efx_mcdi_request_poll( __in efx_nic_t *enp); extern __checkReturn boolean_t efx_mcdi_request_abort( __in efx_nic_t *enp); extern void efx_mcdi_fini( __in efx_nic_t *enp); #endif /* EFSYS_OPT_MCDI */ /* INTR */ #define EFX_NINTR_FALCON 64 #define EFX_NINTR_SIENA 1024 typedef enum efx_intr_type_e { EFX_INTR_INVALID = 0, EFX_INTR_LINE, EFX_INTR_MESSAGE, EFX_INTR_NTYPES } efx_intr_type_t; #define EFX_INTR_SIZE (sizeof (efx_oword_t)) extern __checkReturn int efx_intr_init( __in efx_nic_t *enp, __in efx_intr_type_t type, __in efsys_mem_t *esmp); extern void efx_intr_enable( __in efx_nic_t *enp); extern void efx_intr_disable( __in efx_nic_t *enp); extern void efx_intr_disable_unlocked( __in efx_nic_t *enp); #define EFX_INTR_NEVQS 32 extern __checkReturn int efx_intr_trigger( __in efx_nic_t *enp, __in unsigned int level); extern void efx_intr_status_line( __in efx_nic_t *enp, __out boolean_t *fatalp, __out uint32_t *maskp); extern void efx_intr_status_message( __in efx_nic_t *enp, __in unsigned int message, __out boolean_t *fatalp); extern void efx_intr_fatal( __in efx_nic_t *enp); extern void efx_intr_fini( __in efx_nic_t *enp); /* MAC */ #if EFSYS_OPT_MAC_STATS -/* START MKCONFIG GENERATED EfxHeaderMacBlock bb8d39428b6fdcf5 */ +/* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */ typedef enum efx_mac_stat_e { EFX_MAC_RX_OCTETS, EFX_MAC_RX_PKTS, EFX_MAC_RX_UNICST_PKTS, EFX_MAC_RX_MULTICST_PKTS, EFX_MAC_RX_BRDCST_PKTS, EFX_MAC_RX_PAUSE_PKTS, EFX_MAC_RX_LE_64_PKTS, EFX_MAC_RX_65_TO_127_PKTS, EFX_MAC_RX_128_TO_255_PKTS, EFX_MAC_RX_256_TO_511_PKTS, EFX_MAC_RX_512_TO_1023_PKTS, EFX_MAC_RX_1024_TO_15XX_PKTS, EFX_MAC_RX_GE_15XX_PKTS, EFX_MAC_RX_ERRORS, EFX_MAC_RX_FCS_ERRORS, EFX_MAC_RX_DROP_EVENTS, EFX_MAC_RX_FALSE_CARRIER_ERRORS, EFX_MAC_RX_SYMBOL_ERRORS, EFX_MAC_RX_ALIGN_ERRORS, EFX_MAC_RX_INTERNAL_ERRORS, EFX_MAC_RX_JABBER_PKTS, EFX_MAC_RX_LANE0_CHAR_ERR, EFX_MAC_RX_LANE1_CHAR_ERR, EFX_MAC_RX_LANE2_CHAR_ERR, EFX_MAC_RX_LANE3_CHAR_ERR, EFX_MAC_RX_LANE0_DISP_ERR, EFX_MAC_RX_LANE1_DISP_ERR, EFX_MAC_RX_LANE2_DISP_ERR, EFX_MAC_RX_LANE3_DISP_ERR, EFX_MAC_RX_MATCH_FAULT, EFX_MAC_RX_NODESC_DROP_CNT, EFX_MAC_TX_OCTETS, EFX_MAC_TX_PKTS, EFX_MAC_TX_UNICST_PKTS, EFX_MAC_TX_MULTICST_PKTS, EFX_MAC_TX_BRDCST_PKTS, EFX_MAC_TX_PAUSE_PKTS, EFX_MAC_TX_LE_64_PKTS, EFX_MAC_TX_65_TO_127_PKTS, EFX_MAC_TX_128_TO_255_PKTS, EFX_MAC_TX_256_TO_511_PKTS, EFX_MAC_TX_512_TO_1023_PKTS, EFX_MAC_TX_1024_TO_15XX_PKTS, EFX_MAC_TX_GE_15XX_PKTS, EFX_MAC_TX_ERRORS, EFX_MAC_TX_SGL_COL_PKTS, EFX_MAC_TX_MULT_COL_PKTS, EFX_MAC_TX_EX_COL_PKTS, EFX_MAC_TX_LATE_COL_PKTS, EFX_MAC_TX_DEF_PKTS, EFX_MAC_TX_EX_DEF_PKTS, + EFX_MAC_PM_TRUNC_BB_OVERFLOW, + EFX_MAC_PM_DISCARD_BB_OVERFLOW, + EFX_MAC_PM_TRUNC_VFIFO_FULL, + EFX_MAC_PM_DISCARD_VFIFO_FULL, + EFX_MAC_PM_TRUNC_QBB, + EFX_MAC_PM_DISCARD_QBB, + EFX_MAC_PM_DISCARD_MAPPING, + EFX_MAC_RXDP_Q_DISABLED_PKTS, + EFX_MAC_RXDP_DI_DROPPED_PKTS, + EFX_MAC_RXDP_STREAMING_PKTS, + EFX_MAC_RXDP_HLB_FETCH, + EFX_MAC_RXDP_HLB_WAIT, + EFX_MAC_VADAPTER_RX_UNICAST_PACKETS, + EFX_MAC_VADAPTER_RX_UNICAST_BYTES, + EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS, + EFX_MAC_VADAPTER_RX_MULTICAST_BYTES, + EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS, + EFX_MAC_VADAPTER_RX_BROADCAST_BYTES, + EFX_MAC_VADAPTER_RX_BAD_PACKETS, + EFX_MAC_VADAPTER_RX_BAD_BYTES, + EFX_MAC_VADAPTER_RX_OVERFLOW, + EFX_MAC_VADAPTER_TX_UNICAST_PACKETS, + EFX_MAC_VADAPTER_TX_UNICAST_BYTES, + EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS, + EFX_MAC_VADAPTER_TX_MULTICAST_BYTES, + EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS, + EFX_MAC_VADAPTER_TX_BROADCAST_BYTES, + EFX_MAC_VADAPTER_TX_BAD_PACKETS, + EFX_MAC_VADAPTER_TX_BAD_BYTES, + EFX_MAC_VADAPTER_TX_OVERFLOW, EFX_MAC_NSTATS } efx_mac_stat_t; /* END MKCONFIG GENERATED EfxHeaderMacBlock */ #endif /* EFSYS_OPT_MAC_STATS */ typedef enum efx_link_mode_e { EFX_LINK_UNKNOWN = 0, EFX_LINK_DOWN, EFX_LINK_10HDX, EFX_LINK_10FDX, EFX_LINK_100HDX, EFX_LINK_100FDX, EFX_LINK_1000HDX, EFX_LINK_1000FDX, EFX_LINK_10000FDX, + EFX_LINK_40000FDX, EFX_LINK_NMODES } efx_link_mode_t; +#define EFX_MAC_ADDR_LEN 6 + +#define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t*)_address)[0] & 0x01) + +#define EFX_MAC_MULTICAST_LIST_MAX 256 + #define EFX_MAC_SDU_MAX 9202 #define EFX_MAC_PDU(_sdu) \ P2ROUNDUP(((_sdu) \ + /* EtherII */ 14 \ + /* VLAN */ 4 \ + /* CRC */ 4 \ + /* bug16011 */ 16), \ (1 << 3)) #define EFX_MAC_PDU_MIN 60 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) extern __checkReturn int efx_mac_pdu_set( __in efx_nic_t *enp, __in size_t pdu); extern __checkReturn int efx_mac_addr_set( __in efx_nic_t *enp, __in uint8_t *addr); -extern __checkReturn int +extern __checkReturn int efx_mac_filter_set( + __in efx_nic_t *enp, + __in boolean_t all_unicst, + __in boolean_t mulcst, + __in boolean_t all_mulcst, + __in boolean_t brdcst); + +extern __checkReturn int +efx_mac_multicast_list_set( + __in efx_nic_t *enp, + __in_ecount(6*count) uint8_t const *addrs, + __in int count); + +extern __checkReturn int +efx_mac_filter_default_rxq_set( __in efx_nic_t *enp, - __in boolean_t unicst, - __in boolean_t brdcst); + __in efx_rxq_t *erp, + __in boolean_t using_rss); +extern void +efx_mac_filter_default_rxq_clear( + __in efx_nic_t *enp); + extern __checkReturn int efx_mac_drain( __in efx_nic_t *enp, __in boolean_t enabled); extern __checkReturn int efx_mac_up( __in efx_nic_t *enp, __out boolean_t *mac_upp); #define EFX_FCNTL_RESPOND 0x00000001 #define EFX_FCNTL_GENERATE 0x00000002 extern __checkReturn int efx_mac_fcntl_set( __in efx_nic_t *enp, __in unsigned int fcntl, __in boolean_t autoneg); extern void efx_mac_fcntl_get( __in efx_nic_t *enp, __out unsigned int *fcntl_wantedp, __out unsigned int *fcntl_linkp); #define EFX_MAC_HASH_BITS (1 << 8) extern __checkReturn int +efx_pktfilter_init( + __in efx_nic_t *enp); + +extern void +efx_pktfilter_fini( + __in efx_nic_t *enp); + +extern __checkReturn int +efx_pktfilter_set( + __in efx_nic_t *enp, + __in boolean_t unicst, + __in boolean_t brdcst); + +extern __checkReturn int efx_mac_hash_set( __in efx_nic_t *enp, __in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket); +#if EFSYS_OPT_MCAST_FILTER_LIST +extern __checkReturn int +efx_pktfilter_mcast_list_set( + __in efx_nic_t *enp, + __in uint8_t const *addrs, + __in int count); +#endif /* EFSYS_OPT_MCAST_FILTER_LIST */ + +extern __checkReturn int +efx_pktfilter_mcast_all( + __in efx_nic_t *enp); + #if EFSYS_OPT_MAC_STATS #if EFSYS_OPT_NAMES -extern __checkReturn const char __cs * +extern __checkReturn const char * efx_mac_stat_name( __in efx_nic_t *enp, __in unsigned int id); #endif /* EFSYS_OPT_NAMES */ #define EFX_MAC_STATS_SIZE 0x400 /* * Upload mac statistics supported by the hardware into the given buffer. * * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes, * and page aligned. * * The hardware will only DMA statistics that it understands (of course). * Drivers should not make any assumptions about which statistics are * supported, especially when the statistics are generated by firmware. * * Thus, drivers should zero this buffer before use, so that not-understood * statistics read back as zero. */ extern __checkReturn int efx_mac_stats_upload( __in efx_nic_t *enp, __in efsys_mem_t *esmp); extern __checkReturn int efx_mac_stats_periodic( __in efx_nic_t *enp, __in efsys_mem_t *esmp, __in uint16_t period_ms, __in boolean_t events); extern __checkReturn int efx_mac_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, __out_opt uint32_t *generationp); #endif /* EFSYS_OPT_MAC_STATS */ /* MON */ typedef enum efx_mon_type_e { EFX_MON_INVALID = 0, EFX_MON_NULL, EFX_MON_LM87, EFX_MON_MAX6647, EFX_MON_SFC90X0, + EFX_MON_SFC91X0, EFX_MON_NTYPES } efx_mon_type_t; #if EFSYS_OPT_NAMES -extern const char __cs * +extern const char * efx_mon_name( __in efx_nic_t *enp); #endif /* EFSYS_OPT_NAMES */ extern __checkReturn int efx_mon_init( __in efx_nic_t *enp); #if EFSYS_OPT_MON_STATS -#define EFX_MON_STATS_SIZE 0x100 +#define EFX_MON_STATS_PAGE_SIZE 0x100 +#define EFX_MON_MASK_ELEMENT_SIZE 32 -/* START MKCONFIG GENERATED MonitorHeaderStatsBlock 58706a378332aeee */ +/* START MKCONFIG GENERATED MonitorHeaderStatsBlock c79c86b62a144846 */ typedef enum efx_mon_stat_e { EFX_MON_STAT_2_5V, EFX_MON_STAT_VCCP1, EFX_MON_STAT_VCC, EFX_MON_STAT_5V, EFX_MON_STAT_12V, EFX_MON_STAT_VCCP2, EFX_MON_STAT_EXT_TEMP, EFX_MON_STAT_INT_TEMP, EFX_MON_STAT_AIN1, EFX_MON_STAT_AIN2, EFX_MON_STAT_INT_COOLING, EFX_MON_STAT_EXT_COOLING, EFX_MON_STAT_1V, EFX_MON_STAT_1_2V, EFX_MON_STAT_1_8V, EFX_MON_STAT_3_3V, EFX_MON_STAT_1_2VA, EFX_MON_STAT_VREF, EFX_MON_STAT_VAOE, EFX_MON_STAT_AOE_TEMP, EFX_MON_STAT_PSU_AOE_TEMP, EFX_MON_STAT_PSU_TEMP, EFX_MON_STAT_FAN0, EFX_MON_STAT_FAN1, EFX_MON_STAT_FAN2, EFX_MON_STAT_FAN3, EFX_MON_STAT_FAN4, EFX_MON_STAT_VAOE_IN, EFX_MON_STAT_IAOE, EFX_MON_STAT_IAOE_IN, + EFX_MON_STAT_NIC_POWER, + EFX_MON_STAT_0_9V, + EFX_MON_STAT_I0_9V, + EFX_MON_STAT_I1_2V, + EFX_MON_STAT_0_9V_ADC, + EFX_MON_STAT_INT_TEMP2, + EFX_MON_STAT_VREG_TEMP, + EFX_MON_STAT_VREG_0_9V_TEMP, + EFX_MON_STAT_VREG_1_2V_TEMP, + EFX_MON_STAT_INT_VPTAT, + EFX_MON_STAT_INT_ADC_TEMP, + EFX_MON_STAT_EXT_VPTAT, + EFX_MON_STAT_EXT_ADC_TEMP, + EFX_MON_STAT_AMBIENT_TEMP, + EFX_MON_STAT_AIRFLOW, + EFX_MON_STAT_VDD08D_VSS08D_CSR, + EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC, + EFX_MON_STAT_HOTPOINT_TEMP, + EFX_MON_STAT_PHY_POWER_SWITCH_PORT0, + EFX_MON_STAT_PHY_POWER_SWITCH_PORT1, + EFX_MON_STAT_MUM_VCC, + EFX_MON_STAT_0V9_A, + EFX_MON_STAT_I0V9_A, + EFX_MON_STAT_0V9_A_TEMP, + EFX_MON_STAT_0V9_B, + EFX_MON_STAT_I0V9_B, + EFX_MON_STAT_0V9_B_TEMP, + EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY, + EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC, + EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY, + EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC, + EFX_MON_STAT_CONTROLLER_MASTER_VPTAT, + EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP, + EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC, + EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC, + EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT, + EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP, + EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC, + EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC, EFX_MON_NSTATS } efx_mon_stat_t; /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */ typedef enum efx_mon_stat_state_e { EFX_MON_STAT_STATE_OK = 0, EFX_MON_STAT_STATE_WARNING = 1, EFX_MON_STAT_STATE_FATAL = 2, EFX_MON_STAT_STATE_BROKEN = 3, + EFX_MON_STAT_STATE_NO_READING = 4, } efx_mon_stat_state_t; -typedef struct efx_mon_stat_value_t { +typedef struct efx_mon_stat_value_s { uint16_t emsv_value; uint16_t emsv_state; } efx_mon_stat_value_t; #if EFSYS_OPT_NAMES -extern const char __cs * +extern const char * efx_mon_stat_name( __in efx_nic_t *enp, __in efx_mon_stat_t id); #endif /* EFSYS_OPT_NAMES */ extern __checkReturn int efx_mon_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, __out_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); #endif /* EFSYS_OPT_MON_STATS */ extern void efx_mon_fini( __in efx_nic_t *enp); /* PHY */ #define PMA_PMD_MMD 1 #define PCS_MMD 3 #define PHY_XS_MMD 4 #define DTE_XS_MMD 5 #define AN_MMD 7 #define CL22EXT_MMD 29 #define MAXMMD ((1 << 5) - 1) -/* PHY types */ -#define EFX_PHY_NULL 0x0 -#define EFX_PHY_TXC43128 0x1 -#define EFX_PHY_SFX7101 0x3 -#define EFX_PHY_QT2022C2 0x4 -#define EFX_PHY_SFT9001A 0x8 -#define EFX_PHY_QT2025C 0x9 -#define EFX_PHY_SFT9001B 0xa -#define EFX_PHY_QLX111V 0xc - extern __checkReturn int efx_phy_verify( __in efx_nic_t *enp); #if EFSYS_OPT_PHY_LED_CONTROL typedef enum efx_phy_led_mode_e { EFX_PHY_LED_DEFAULT = 0, EFX_PHY_LED_OFF, EFX_PHY_LED_ON, EFX_PHY_LED_FLASH, EFX_PHY_LED_NMODES } efx_phy_led_mode_t; extern __checkReturn int efx_phy_led_set( __in efx_nic_t *enp, __in efx_phy_led_mode_t mode); #endif /* EFSYS_OPT_PHY_LED_CONTROL */ extern __checkReturn int efx_port_init( __in efx_nic_t *enp); #if EFSYS_OPT_LOOPBACK typedef enum efx_loopback_type_e { EFX_LOOPBACK_OFF = 0, EFX_LOOPBACK_DATA = 1, EFX_LOOPBACK_GMAC = 2, EFX_LOOPBACK_XGMII = 3, EFX_LOOPBACK_XGXS = 4, EFX_LOOPBACK_XAUI = 5, EFX_LOOPBACK_GMII = 6, EFX_LOOPBACK_SGMII = 7, EFX_LOOPBACK_XGBR = 8, EFX_LOOPBACK_XFI = 9, EFX_LOOPBACK_XAUI_FAR = 10, EFX_LOOPBACK_GMII_FAR = 11, EFX_LOOPBACK_SGMII_FAR = 12, EFX_LOOPBACK_XFI_FAR = 13, EFX_LOOPBACK_GPHY = 14, EFX_LOOPBACK_PHY_XS = 15, EFX_LOOPBACK_PCS = 16, EFX_LOOPBACK_PMA_PMD = 17, + EFX_LOOPBACK_XPORT = 18, + EFX_LOOPBACK_XGMII_WS = 19, + EFX_LOOPBACK_XAUI_WS = 20, + EFX_LOOPBACK_XAUI_WS_FAR = 21, + EFX_LOOPBACK_XAUI_WS_NEAR = 22, + EFX_LOOPBACK_GMII_WS = 23, + EFX_LOOPBACK_XFI_WS = 24, + EFX_LOOPBACK_XFI_WS_FAR = 25, + EFX_LOOPBACK_PHYXS_WS = 26, + EFX_LOOPBACK_PMA_INT = 27, + EFX_LOOPBACK_SD_NEAR = 28, + EFX_LOOPBACK_SD_FAR = 29, + EFX_LOOPBACK_PMA_INT_WS = 30, + EFX_LOOPBACK_SD_FEP2_WS = 31, + EFX_LOOPBACK_SD_FEP1_5_WS = 32, + EFX_LOOPBACK_SD_FEP_WS = 33, + EFX_LOOPBACK_SD_FES_WS = 34, EFX_LOOPBACK_NTYPES } efx_loopback_type_t; -#define EFX_LOOPBACK_MAC_MASK \ - ((1 << EFX_LOOPBACK_DATA) | \ - (1 << EFX_LOOPBACK_GMAC) | \ - (1 << EFX_LOOPBACK_XGMII) | \ - (1 << EFX_LOOPBACK_XGXS) | \ - (1 << EFX_LOOPBACK_XAUI) | \ - (1 << EFX_LOOPBACK_GMII) | \ - (1 << EFX_LOOPBACK_SGMII) | \ - (1 << EFX_LOOPBACK_XGBR) | \ - (1 << EFX_LOOPBACK_XFI) | \ - (1 << EFX_LOOPBACK_XAUI_FAR) | \ - (1 << EFX_LOOPBACK_GMII_FAR) | \ - (1 << EFX_LOOPBACK_SGMII_FAR) | \ - (1 << EFX_LOOPBACK_XFI_FAR)) +typedef enum efx_loopback_kind_e { + EFX_LOOPBACK_KIND_OFF = 0, + EFX_LOOPBACK_KIND_ALL, + EFX_LOOPBACK_KIND_MAC, + EFX_LOOPBACK_KIND_PHY, + EFX_LOOPBACK_NKINDS +} efx_loopback_kind_t; -#define EFX_LOOPBACK_MASK \ - ((1 << EFX_LOOPBACK_NTYPES) - 1) +extern void +efx_loopback_mask( + __in efx_loopback_kind_t loopback_kind, + __out efx_qword_t *maskp); extern __checkReturn int efx_port_loopback_set( __in efx_nic_t *enp, __in efx_link_mode_t link_mode, __in efx_loopback_type_t type); #if EFSYS_OPT_NAMES -extern __checkReturn const char __cs * +extern __checkReturn const char * efx_loopback_type_name( __in efx_nic_t *enp, __in efx_loopback_type_t type); #endif /* EFSYS_OPT_NAMES */ #endif /* EFSYS_OPT_LOOPBACK */ extern __checkReturn int efx_port_poll( __in efx_nic_t *enp, - __out efx_link_mode_t *link_modep); + __out_opt efx_link_mode_t *link_modep); extern void efx_port_fini( __in efx_nic_t *enp); typedef enum efx_phy_cap_type_e { EFX_PHY_CAP_INVALID = 0, EFX_PHY_CAP_10HDX, EFX_PHY_CAP_10FDX, EFX_PHY_CAP_100HDX, EFX_PHY_CAP_100FDX, EFX_PHY_CAP_1000HDX, EFX_PHY_CAP_1000FDX, EFX_PHY_CAP_10000FDX, EFX_PHY_CAP_PAUSE, EFX_PHY_CAP_ASYM, EFX_PHY_CAP_AN, + EFX_PHY_CAP_40000FDX, EFX_PHY_CAP_NTYPES } efx_phy_cap_type_t; #define EFX_PHY_CAP_CURRENT 0x00000000 #define EFX_PHY_CAP_DEFAULT 0x00000001 #define EFX_PHY_CAP_PERM 0x00000002 extern void efx_phy_adv_cap_get( __in efx_nic_t *enp, __in uint32_t flag, __out uint32_t *maskp); extern __checkReturn int efx_phy_adv_cap_set( __in efx_nic_t *enp, __in uint32_t mask); extern void efx_phy_lp_cap_get( __in efx_nic_t *enp, __out uint32_t *maskp); extern __checkReturn int efx_phy_oui_get( __in efx_nic_t *enp, __out uint32_t *ouip); typedef enum efx_phy_media_type_e { EFX_PHY_MEDIA_INVALID = 0, EFX_PHY_MEDIA_XAUI, EFX_PHY_MEDIA_CX4, EFX_PHY_MEDIA_KX4, EFX_PHY_MEDIA_XFP, EFX_PHY_MEDIA_SFP_PLUS, EFX_PHY_MEDIA_BASE_T, + EFX_PHY_MEDIA_QSFP_PLUS, EFX_PHY_MEDIA_NTYPES } efx_phy_media_type_t; /* Get the type of medium currently used. If the board has ports for * modules, a module is present, and we recognise the media type of * the module, then this will be the media type of the module. * Otherwise it will be the media type of the port. */ extern void efx_phy_media_type_get( __in efx_nic_t *enp, __out efx_phy_media_type_t *typep); #if EFSYS_OPT_PHY_STATS /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */ typedef enum efx_phy_stat_e { EFX_PHY_STAT_OUI, EFX_PHY_STAT_PMA_PMD_LINK_UP, EFX_PHY_STAT_PMA_PMD_RX_FAULT, EFX_PHY_STAT_PMA_PMD_TX_FAULT, EFX_PHY_STAT_PMA_PMD_REV_A, EFX_PHY_STAT_PMA_PMD_REV_B, EFX_PHY_STAT_PMA_PMD_REV_C, EFX_PHY_STAT_PMA_PMD_REV_D, EFX_PHY_STAT_PCS_LINK_UP, EFX_PHY_STAT_PCS_RX_FAULT, EFX_PHY_STAT_PCS_TX_FAULT, EFX_PHY_STAT_PCS_BER, EFX_PHY_STAT_PCS_BLOCK_ERRORS, EFX_PHY_STAT_PHY_XS_LINK_UP, EFX_PHY_STAT_PHY_XS_RX_FAULT, EFX_PHY_STAT_PHY_XS_TX_FAULT, EFX_PHY_STAT_PHY_XS_ALIGN, EFX_PHY_STAT_PHY_XS_SYNC_A, EFX_PHY_STAT_PHY_XS_SYNC_B, EFX_PHY_STAT_PHY_XS_SYNC_C, EFX_PHY_STAT_PHY_XS_SYNC_D, EFX_PHY_STAT_AN_LINK_UP, EFX_PHY_STAT_AN_MASTER, EFX_PHY_STAT_AN_LOCAL_RX_OK, EFX_PHY_STAT_AN_REMOTE_RX_OK, EFX_PHY_STAT_CL22EXT_LINK_UP, EFX_PHY_STAT_SNR_A, EFX_PHY_STAT_SNR_B, EFX_PHY_STAT_SNR_C, EFX_PHY_STAT_SNR_D, EFX_PHY_STAT_PMA_PMD_SIGNAL_A, EFX_PHY_STAT_PMA_PMD_SIGNAL_B, EFX_PHY_STAT_PMA_PMD_SIGNAL_C, EFX_PHY_STAT_PMA_PMD_SIGNAL_D, EFX_PHY_STAT_AN_COMPLETE, EFX_PHY_STAT_PMA_PMD_REV_MAJOR, EFX_PHY_STAT_PMA_PMD_REV_MINOR, EFX_PHY_STAT_PMA_PMD_REV_MICRO, EFX_PHY_STAT_PCS_FW_VERSION_0, EFX_PHY_STAT_PCS_FW_VERSION_1, EFX_PHY_STAT_PCS_FW_VERSION_2, EFX_PHY_STAT_PCS_FW_VERSION_3, EFX_PHY_STAT_PCS_FW_BUILD_YY, EFX_PHY_STAT_PCS_FW_BUILD_MM, EFX_PHY_STAT_PCS_FW_BUILD_DD, EFX_PHY_STAT_PCS_OP_MODE, EFX_PHY_NSTATS } efx_phy_stat_t; /* END MKCONFIG GENERATED PhyHeaderStatsBlock */ #if EFSYS_OPT_NAMES -extern const char __cs * +extern const char * efx_phy_stat_name( __in efx_nic_t *enp, __in efx_phy_stat_t stat); #endif /* EFSYS_OPT_NAMES */ #define EFX_PHY_STATS_SIZE 0x100 extern __checkReturn int efx_phy_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, __out_ecount(EFX_PHY_NSTATS) uint32_t *stat); #endif /* EFSYS_OPT_PHY_STATS */ #if EFSYS_OPT_PHY_PROPS #if EFSYS_OPT_NAMES -extern const char __cs * +extern const char * efx_phy_prop_name( __in efx_nic_t *enp, __in unsigned int id); #endif /* EFSYS_OPT_NAMES */ #define EFX_PHY_PROP_DEFAULT 0x00000001 extern __checkReturn int efx_phy_prop_get( __in efx_nic_t *enp, __in unsigned int id, __in uint32_t flags, __out uint32_t *valp); extern __checkReturn int efx_phy_prop_set( __in efx_nic_t *enp, __in unsigned int id, __in uint32_t val); #endif /* EFSYS_OPT_PHY_PROPS */ -#if EFSYS_OPT_PHY_BIST +#if EFSYS_OPT_BIST -typedef enum efx_phy_bist_type_e { - EFX_PHY_BIST_TYPE_UNKNOWN, - EFX_PHY_BIST_TYPE_NORMAL, - EFX_PHY_BIST_TYPE_CABLE_SHORT, - EFX_PHY_BIST_TYPE_CABLE_LONG, - EFX_PHY_BIST_TYPE_NTYPES, -} efx_phy_bist_type_t; +typedef enum efx_bist_type_e { + EFX_BIST_TYPE_UNKNOWN, + EFX_BIST_TYPE_PHY_NORMAL, + EFX_BIST_TYPE_PHY_CABLE_SHORT, + EFX_BIST_TYPE_PHY_CABLE_LONG, + EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */ + EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/ + EFX_BIST_TYPE_REG, /* Test the register memories */ + EFX_BIST_TYPE_NTYPES, +} efx_bist_type_t; -typedef enum efx_phy_bist_result_e { - EFX_PHY_BIST_RESULT_UNKNOWN, - EFX_PHY_BIST_RESULT_RUNNING, - EFX_PHY_BIST_RESULT_PASSED, - EFX_PHY_BIST_RESULT_FAILED, -} efx_phy_bist_result_t; +typedef enum efx_bist_result_e { + EFX_BIST_RESULT_UNKNOWN, + EFX_BIST_RESULT_RUNNING, + EFX_BIST_RESULT_PASSED, + EFX_BIST_RESULT_FAILED, +} efx_bist_result_t; typedef enum efx_phy_cable_status_e { EFX_PHY_CABLE_STATUS_OK, EFX_PHY_CABLE_STATUS_INVALID, EFX_PHY_CABLE_STATUS_OPEN, EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT, EFX_PHY_CABLE_STATUS_INTERPAIRSHORT, EFX_PHY_CABLE_STATUS_BUSY, } efx_phy_cable_status_t; -typedef enum efx_phy_bist_value_e { - EFX_PHY_BIST_CABLE_LENGTH_A, - EFX_PHY_BIST_CABLE_LENGTH_B, - EFX_PHY_BIST_CABLE_LENGTH_C, - EFX_PHY_BIST_CABLE_LENGTH_D, - EFX_PHY_BIST_CABLE_STATUS_A, - EFX_PHY_BIST_CABLE_STATUS_B, - EFX_PHY_BIST_CABLE_STATUS_C, - EFX_PHY_BIST_CABLE_STATUS_D, - EFX_PHY_BIST_FAULT_CODE, - EFX_PHY_BIST_NVALUES, -} efx_phy_bist_value_t; +typedef enum efx_bist_value_e { + EFX_BIST_PHY_CABLE_LENGTH_A, + EFX_BIST_PHY_CABLE_LENGTH_B, + EFX_BIST_PHY_CABLE_LENGTH_C, + EFX_BIST_PHY_CABLE_LENGTH_D, + EFX_BIST_PHY_CABLE_STATUS_A, + EFX_BIST_PHY_CABLE_STATUS_B, + EFX_BIST_PHY_CABLE_STATUS_C, + EFX_BIST_PHY_CABLE_STATUS_D, + EFX_BIST_FAULT_CODE, + /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL + * response. */ + EFX_BIST_MEM_TEST, + EFX_BIST_MEM_ADDR, + EFX_BIST_MEM_BUS, + EFX_BIST_MEM_EXPECT, + EFX_BIST_MEM_ACTUAL, + EFX_BIST_MEM_ECC, + EFX_BIST_MEM_ECC_PARITY, + EFX_BIST_MEM_ECC_FATAL, + EFX_BIST_NVALUES, +} efx_bist_value_t; extern __checkReturn int -efx_phy_bist_start( +efx_bist_enable_offline( + __in efx_nic_t *enp); + +extern __checkReturn int +efx_bist_start( __in efx_nic_t *enp, - __in efx_phy_bist_type_t type); + __in efx_bist_type_t type); extern __checkReturn int -efx_phy_bist_poll( +efx_bist_poll( __in efx_nic_t *enp, - __in efx_phy_bist_type_t type, - __out efx_phy_bist_result_t *resultp, + __in efx_bist_type_t type, + __out efx_bist_result_t *resultp, __out_opt uint32_t *value_maskp, __out_ecount_opt(count) unsigned long *valuesp, __in size_t count); extern void -efx_phy_bist_stop( +efx_bist_stop( __in efx_nic_t *enp, - __in efx_phy_bist_type_t type); + __in efx_bist_type_t type); -#endif /* EFSYS_OPT_PHY_BIST */ +#endif /* EFSYS_OPT_BIST */ #define EFX_FEATURE_IPV6 0x00000001 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002 #define EFX_FEATURE_LINK_EVENTS 0x00000004 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008 #define EFX_FEATURE_WOL 0x00000010 #define EFX_FEATURE_MCDI 0x00000020 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080 #define EFX_FEATURE_TURBO 0x00000100 +#define EFX_FEATURE_MCDI_DMA 0x00000200 +#define EFX_FEATURE_TX_SRC_FILTERS 0x00000400 +#define EFX_FEATURE_PIO_BUFFERS 0x00000800 +#define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000 typedef struct efx_nic_cfg_s { uint32_t enc_board_type; uint32_t enc_phy_type; #if EFSYS_OPT_NAMES char enc_phy_name[21]; #endif char enc_phy_revision[21]; efx_mon_type_t enc_mon_type; #if EFSYS_OPT_MON_STATS - uint32_t enc_mon_stat_mask; + uint32_t enc_mon_stat_dma_buf_size; + uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32]; #endif unsigned int enc_features; uint8_t enc_mac_addr[6]; - uint8_t enc_port; + uint8_t enc_port; /* PHY port number */ + uint32_t enc_func_flags; + uint32_t enc_intr_vec_base; + uint32_t enc_intr_limit; uint32_t enc_evq_limit; uint32_t enc_txq_limit; uint32_t enc_rxq_limit; uint32_t enc_buftbl_limit; + uint32_t enc_piobuf_limit; + uint32_t enc_piobuf_size; uint32_t enc_evq_timer_quantum_ns; uint32_t enc_evq_timer_max_us; uint32_t enc_clk_mult; + uint32_t enc_rx_prefix_size; + uint32_t enc_rx_buf_align_start; + uint32_t enc_rx_buf_align_end; #if EFSYS_OPT_LOOPBACK - uint32_t enc_loopback_types[EFX_LINK_NMODES]; + efx_qword_t enc_loopback_types[EFX_LINK_NMODES]; #endif /* EFSYS_OPT_LOOPBACK */ #if EFSYS_OPT_PHY_FLAGS uint32_t enc_phy_flags_mask; #endif /* EFSYS_OPT_PHY_FLAGS */ #if EFSYS_OPT_PHY_LED_CONTROL uint32_t enc_led_mask; #endif /* EFSYS_OPT_PHY_LED_CONTROL */ #if EFSYS_OPT_PHY_STATS uint64_t enc_phy_stat_mask; #endif /* EFSYS_OPT_PHY_STATS */ #if EFSYS_OPT_PHY_PROPS unsigned int enc_phy_nprops; #endif /* EFSYS_OPT_PHY_PROPS */ #if EFSYS_OPT_SIENA - uint8_t enc_siena_channel; + uint8_t enc_mcdi_mdio_channel; #if EFSYS_OPT_PHY_STATS - uint32_t enc_siena_phy_stat_mask; + uint32_t enc_mcdi_phy_stat_mask; #endif /* EFSYS_OPT_PHY_STATS */ +#endif /* EFSYS_OPT_SIENA */ +#if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) #if EFSYS_OPT_MON_STATS - uint32_t enc_siena_mon_stat_mask; + uint32_t *enc_mcdi_sensor_maskp; + uint32_t enc_mcdi_sensor_mask_size; #endif /* EFSYS_OPT_MON_STATS */ -#endif /* EFSYS_OPT_SIENA */ -#if EFSYS_OPT_PHY_BIST +#endif /* (EFSYS_OPT_SIENA | EFSYS_OPT_HUNTINGTON) */ +#if EFSYS_OPT_BIST uint32_t enc_bist_mask; -#endif /* EFSYS_OPT_PHY_BIST */ +#endif /* EFSYS_OPT_BIST */ +#if EFSYS_OPT_HUNTINGTON + uint32_t enc_pf; + uint32_t enc_vf; + uint32_t enc_privilege_mask; +#endif /* EFSYS_OPT_HUNTINGTON */ + boolean_t enc_bug26807_workaround; + boolean_t enc_bug35388_workaround; + boolean_t enc_bug41750_workaround; + boolean_t enc_rx_batching_enabled; + /* Maximum number of descriptors completed in an rx event. */ + uint32_t enc_rx_batch_max; + /* Number of rx descriptors the hardware requires for a push. */ + uint32_t enc_rx_push_align; + /* + * Maximum number of bytes into the packet the TCP header can start for + * the hardware to apply TSO packet edits. + */ + uint32_t enc_tx_tso_tcp_header_offset_limit; + boolean_t enc_fw_assisted_tso_enabled; + boolean_t enc_hw_tx_insert_vlan_enabled; + /* Datapath firmware vadapter/vport/vswitch support */ + boolean_t enc_datapath_cap_evb; + /* External port identifier */ + uint8_t enc_external_port; } efx_nic_cfg_t; +#define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff) +#define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff) + +#define EFX_PCI_FUNCTION(_encp) \ + (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf) + +#define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf) + extern const efx_nic_cfg_t * efx_nic_cfg_get( __in efx_nic_t *enp); +/* Driver resource limits (minimum required/maximum usable). */ +typedef struct efx_drv_limits_s +{ + uint32_t edl_min_evq_count; + uint32_t edl_max_evq_count; + + uint32_t edl_min_rxq_count; + uint32_t edl_max_rxq_count; + + uint32_t edl_min_txq_count; + uint32_t edl_max_txq_count; + + /* PIO blocks (sub-allocated from piobuf) */ + uint32_t edl_min_pio_alloc_size; + uint32_t edl_max_pio_alloc_count; +} efx_drv_limits_t; + +extern __checkReturn int +efx_nic_set_drv_limits( + __inout efx_nic_t *enp, + __in efx_drv_limits_t *edlp); + +typedef enum efx_nic_region_e { + EFX_REGION_VI, /* Memory BAR UC mapping */ + EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */ +} efx_nic_region_t; + +extern __checkReturn int +efx_nic_get_bar_region( + __in efx_nic_t *enp, + __in efx_nic_region_t region, + __out uint32_t *offsetp, + __out size_t *sizep); + +extern __checkReturn int +efx_nic_get_vi_pool( + __in efx_nic_t *enp, + __out uint32_t *evq_countp, + __out uint32_t *rxq_countp, + __out uint32_t *txq_countp); + + #if EFSYS_OPT_VPD typedef enum efx_vpd_tag_e { EFX_VPD_ID = 0x02, EFX_VPD_END = 0x0f, EFX_VPD_RO = 0x10, EFX_VPD_RW = 0x11, } efx_vpd_tag_t; typedef uint16_t efx_vpd_keyword_t; typedef struct efx_vpd_value_s { efx_vpd_tag_t evv_tag; efx_vpd_keyword_t evv_keyword; uint8_t evv_length; uint8_t evv_value[0x100]; } efx_vpd_value_t; #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) extern __checkReturn int efx_vpd_init( __in efx_nic_t *enp); extern __checkReturn int efx_vpd_size( __in efx_nic_t *enp, __out size_t *sizep); extern __checkReturn int efx_vpd_read( __in efx_nic_t *enp, __out_bcount(size) caddr_t data, __in size_t size); extern __checkReturn int efx_vpd_verify( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size); extern __checkReturn int efx_vpd_reinit( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size); extern __checkReturn int efx_vpd_get( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size, __inout efx_vpd_value_t *evvp); extern __checkReturn int efx_vpd_set( __in efx_nic_t *enp, __inout_bcount(size) caddr_t data, __in size_t size, __in efx_vpd_value_t *evvp); extern __checkReturn int efx_vpd_next( __in efx_nic_t *enp, __inout_bcount(size) caddr_t data, __in size_t size, __out efx_vpd_value_t *evvp, __inout unsigned int *contp); extern __checkReturn int efx_vpd_write( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size); extern void efx_vpd_fini( __in efx_nic_t *enp); #endif /* EFSYS_OPT_VPD */ /* NVRAM */ #if EFSYS_OPT_NVRAM typedef enum efx_nvram_type_e { EFX_NVRAM_INVALID = 0, EFX_NVRAM_BOOTROM, EFX_NVRAM_BOOTROM_CFG, EFX_NVRAM_MC_FIRMWARE, EFX_NVRAM_MC_GOLDEN, EFX_NVRAM_PHY, EFX_NVRAM_NULLPHY, EFX_NVRAM_FPGA, EFX_NVRAM_FCFW, EFX_NVRAM_CPLD, EFX_NVRAM_FPGA_BACKUP, + EFX_NVRAM_DYNAMIC_CFG, EFX_NVRAM_NTYPES, } efx_nvram_type_t; extern __checkReturn int efx_nvram_init( __in efx_nic_t *enp); #if EFSYS_OPT_DIAG extern __checkReturn int efx_nvram_test( __in efx_nic_t *enp); #endif /* EFSYS_OPT_DIAG */ extern __checkReturn int efx_nvram_size( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out size_t *sizep); extern __checkReturn int efx_nvram_rw_start( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out_opt size_t *pref_chunkp); extern void efx_nvram_rw_finish( __in efx_nic_t *enp, __in efx_nvram_type_t type); extern __checkReturn int efx_nvram_get_version( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out uint32_t *subtypep, __out_ecount(4) uint16_t version[4]); extern __checkReturn int efx_nvram_read_chunk( __in efx_nic_t *enp, __in efx_nvram_type_t type, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size); extern __checkReturn int efx_nvram_set_version( __in efx_nic_t *enp, __in efx_nvram_type_t type, - __out uint16_t version[4]); + __in_ecount(4) uint16_t version[4]); +/* Validate contents of TLV formatted partition */ +extern __checkReturn int +efx_nvram_tlv_validate( + __in efx_nic_t *enp, + __in uint32_t partn, + __in_bcount(partn_size) caddr_t partn_data, + __in size_t partn_size); + extern __checkReturn int efx_nvram_erase( __in efx_nic_t *enp, __in efx_nvram_type_t type); extern __checkReturn int efx_nvram_write_chunk( __in efx_nic_t *enp, __in efx_nvram_type_t type, __in unsigned int offset, __in_bcount(size) caddr_t data, __in size_t size); extern void efx_nvram_fini( __in efx_nic_t *enp); #endif /* EFSYS_OPT_NVRAM */ #if EFSYS_OPT_BOOTCFG extern int efx_bootcfg_read( __in efx_nic_t *enp, __out_bcount(size) caddr_t data, __in size_t size); extern int efx_bootcfg_write( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size); #endif /* EFSYS_OPT_BOOTCFG */ #if EFSYS_OPT_WOL typedef enum efx_wol_type_e { EFX_WOL_TYPE_INVALID, EFX_WOL_TYPE_MAGIC, EFX_WOL_TYPE_BITMAP, EFX_WOL_TYPE_LINK, EFX_WOL_NTYPES, } efx_wol_type_t; typedef enum efx_lightsout_offload_type_e { EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID, EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP, EFX_LIGHTSOUT_OFFLOAD_TYPE_NS, } efx_lightsout_offload_type_t; #define EFX_WOL_BITMAP_MASK_SIZE (48) #define EFX_WOL_BITMAP_VALUE_SIZE (128) typedef union efx_wol_param_u { struct { uint8_t mac_addr[6]; } ewp_magic; struct { uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */ uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */ uint8_t value_len; } ewp_bitmap; } efx_wol_param_t; typedef union efx_lightsout_offload_param_u { struct { uint8_t mac_addr[6]; uint32_t ip; } elop_arp; struct { uint8_t mac_addr[6]; uint32_t solicited_node[4]; uint32_t ip[4]; } elop_ns; } efx_lightsout_offload_param_t; extern __checkReturn int efx_wol_init( __in efx_nic_t *enp); extern __checkReturn int efx_wol_filter_clear( __in efx_nic_t *enp); extern __checkReturn int efx_wol_filter_add( __in efx_nic_t *enp, __in efx_wol_type_t type, __in efx_wol_param_t *paramp, __out uint32_t *filter_idp); extern __checkReturn int efx_wol_filter_remove( __in efx_nic_t *enp, __in uint32_t filter_id); extern __checkReturn int efx_lightsout_offload_add( __in efx_nic_t *enp, __in efx_lightsout_offload_type_t type, __in efx_lightsout_offload_param_t *paramp, __out uint32_t *filter_idp); extern __checkReturn int efx_lightsout_offload_remove( __in efx_nic_t *enp, __in efx_lightsout_offload_type_t type, __in uint32_t filter_id); extern void efx_wol_fini( __in efx_nic_t *enp); #endif /* EFSYS_OPT_WOL */ #if EFSYS_OPT_DIAG typedef enum efx_pattern_type_t { EFX_PATTERN_BYTE_INCREMENT = 0, EFX_PATTERN_ALL_THE_SAME, EFX_PATTERN_BIT_ALTERNATE, EFX_PATTERN_BYTE_ALTERNATE, EFX_PATTERN_BYTE_CHANGING, EFX_PATTERN_BIT_SWEEP, EFX_PATTERN_NTYPES } efx_pattern_type_t; typedef void (*efx_sram_pattern_fn_t)( __in size_t row, __in boolean_t negate, __out efx_qword_t *eqp); extern __checkReturn int efx_sram_test( __in efx_nic_t *enp, __in efx_pattern_type_t type); #endif /* EFSYS_OPT_DIAG */ extern __checkReturn int efx_sram_buf_tbl_set( __in efx_nic_t *enp, __in uint32_t id, __in efsys_mem_t *esmp, __in size_t n); extern void efx_sram_buf_tbl_clear( __in efx_nic_t *enp, __in uint32_t id, __in size_t n); #define EFX_BUF_TBL_SIZE 0x20000 #define EFX_BUF_SIZE 4096 /* EV */ typedef struct efx_evq_s efx_evq_t; #if EFSYS_OPT_QSTATS -/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock d5614a5d669c8ca3 */ +/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */ typedef enum efx_ev_qstat_e { EV_ALL, EV_RX, EV_RX_OK, - EV_RX_RECOVERY, EV_RX_FRM_TRUNC, EV_RX_TOBE_DISC, EV_RX_PAUSE_FRM_ERR, EV_RX_BUF_OWNER_ID_ERR, EV_RX_IPV4_HDR_CHKSUM_ERR, EV_RX_TCP_UDP_CHKSUM_ERR, EV_RX_ETH_CRC_ERR, EV_RX_IP_FRAG_ERR, EV_RX_MCAST_PKT, EV_RX_MCAST_HASH_MATCH, EV_RX_TCP_IPV4, EV_RX_TCP_IPV6, EV_RX_UDP_IPV4, EV_RX_UDP_IPV6, EV_RX_OTHER_IPV4, EV_RX_OTHER_IPV6, EV_RX_NON_IP, - EV_RX_OVERRUN, + EV_RX_BATCH, EV_TX, EV_TX_WQ_FF_FULL, EV_TX_PKT_ERR, EV_TX_PKT_TOO_BIG, EV_TX_UNEXPECTED, EV_GLOBAL, - EV_GLOBAL_PHY, EV_GLOBAL_MNT, - EV_GLOBAL_RX_RECOVERY, EV_DRIVER, EV_DRIVER_SRM_UPD_DONE, EV_DRIVER_TX_DESCQ_FLS_DONE, EV_DRIVER_RX_DESCQ_FLS_DONE, EV_DRIVER_RX_DESCQ_FLS_FAILED, EV_DRIVER_RX_DSC_ERROR, EV_DRIVER_TX_DSC_ERROR, EV_DRV_GEN, EV_MCDI_RESPONSE, EV_NQSTATS } efx_ev_qstat_t; /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */ #endif /* EFSYS_OPT_QSTATS */ extern __checkReturn int efx_ev_init( __in efx_nic_t *enp); extern void efx_ev_fini( __in efx_nic_t *enp); -#define EFX_MASK(_max, _min) (-((_max) << 1) ^ -(_min)) - #define EFX_EVQ_MAXNEVS 32768 #define EFX_EVQ_MINNEVS 512 -#define EFX_EVQ_NEVS_MASK EFX_MASK(EFX_EVQ_MAXNEVS, EFX_EVQ_MINNEVS) - #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t)) #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE) extern __checkReturn int efx_ev_qcreate( __in efx_nic_t *enp, __in unsigned int index, __in efsys_mem_t *esmp, __in size_t n, __in uint32_t id, __deref_out efx_evq_t **eepp); extern void efx_ev_qpost( __in efx_evq_t *eep, __in uint16_t data); typedef __checkReturn boolean_t (*efx_initialized_ev_t)( __in_opt void *arg); #define EFX_PKT_UNICAST 0x0004 #define EFX_PKT_START 0x0008 #define EFX_PKT_VLAN_TAGGED 0x0010 #define EFX_CKSUM_TCPUDP 0x0020 #define EFX_CKSUM_IPV4 0x0040 #define EFX_PKT_CONT 0x0080 #define EFX_CHECK_VLAN 0x0100 #define EFX_PKT_TCP 0x0200 #define EFX_PKT_UDP 0x0400 #define EFX_PKT_IPV4 0x0800 #define EFX_PKT_IPV6 0x1000 +#define EFX_PKT_PREFIX_LEN 0x2000 #define EFX_ADDR_MISMATCH 0x4000 #define EFX_DISCARD 0x8000 #define EFX_EV_RX_NLABELS 32 #define EFX_EV_TX_NLABELS 32 typedef __checkReturn boolean_t (*efx_rx_ev_t)( __in_opt void *arg, __in uint32_t label, __in uint32_t id, __in uint32_t size, __in uint16_t flags); typedef __checkReturn boolean_t (*efx_tx_ev_t)( __in_opt void *arg, __in uint32_t label, __in uint32_t id); #define EFX_EXCEPTION_RX_RECOVERY 0x00000001 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006 +#define EFX_EXCEPTION_RX_ERROR 0x00000007 +#define EFX_EXCEPTION_TX_ERROR 0x00000008 +#define EFX_EXCEPTION_EV_ERROR 0x00000009 typedef __checkReturn boolean_t (*efx_exception_ev_t)( __in_opt void *arg, __in uint32_t label, __in uint32_t data); typedef __checkReturn boolean_t (*efx_rxq_flush_done_ev_t)( __in_opt void *arg, __in uint32_t rxq_index); typedef __checkReturn boolean_t (*efx_rxq_flush_failed_ev_t)( __in_opt void *arg, __in uint32_t rxq_index); typedef __checkReturn boolean_t (*efx_txq_flush_done_ev_t)( __in_opt void *arg, __in uint32_t txq_index); typedef __checkReturn boolean_t (*efx_software_ev_t)( __in_opt void *arg, __in uint16_t magic); typedef __checkReturn boolean_t (*efx_sram_ev_t)( __in_opt void *arg, __in uint32_t code); #define EFX_SRAM_CLEAR 0 #define EFX_SRAM_UPDATE 1 #define EFX_SRAM_ILLEGAL_CLEAR 2 typedef __checkReturn boolean_t (*efx_wake_up_ev_t)( __in_opt void *arg, __in uint32_t label); typedef __checkReturn boolean_t (*efx_timer_ev_t)( __in_opt void *arg, __in uint32_t label); typedef __checkReturn boolean_t (*efx_link_change_ev_t)( __in_opt void *arg, __in efx_link_mode_t link_mode); #if EFSYS_OPT_MON_STATS typedef __checkReturn boolean_t (*efx_monitor_ev_t)( __in_opt void *arg, __in efx_mon_stat_t id, __in efx_mon_stat_value_t value); #endif /* EFSYS_OPT_MON_STATS */ #if EFSYS_OPT_MAC_STATS typedef __checkReturn boolean_t (*efx_mac_stats_ev_t)( __in_opt void *arg, __in uint32_t generation ); #endif /* EFSYS_OPT_MAC_STATS */ typedef struct efx_ev_callbacks_s { efx_initialized_ev_t eec_initialized; efx_rx_ev_t eec_rx; efx_tx_ev_t eec_tx; efx_exception_ev_t eec_exception; efx_rxq_flush_done_ev_t eec_rxq_flush_done; efx_rxq_flush_failed_ev_t eec_rxq_flush_failed; efx_txq_flush_done_ev_t eec_txq_flush_done; efx_software_ev_t eec_software; efx_sram_ev_t eec_sram; efx_wake_up_ev_t eec_wake_up; efx_timer_ev_t eec_timer; efx_link_change_ev_t eec_link_change; #if EFSYS_OPT_MON_STATS efx_monitor_ev_t eec_monitor; #endif /* EFSYS_OPT_MON_STATS */ #if EFSYS_OPT_MAC_STATS efx_mac_stats_ev_t eec_mac_stats; -#endif /* EFSYS_OPT_MON_STATS */ +#endif /* EFSYS_OPT_MAC_STATS */ } efx_ev_callbacks_t; extern __checkReturn boolean_t efx_ev_qpending( __in efx_evq_t *eep, __in unsigned int count); #if EFSYS_OPT_EV_PREFETCH extern void efx_ev_qprefetch( __in efx_evq_t *eep, __in unsigned int count); #endif /* EFSYS_OPT_EV_PREFETCH */ extern void efx_ev_qpoll( __in efx_evq_t *eep, __inout unsigned int *countp, __in const efx_ev_callbacks_t *eecp, __in_opt void *arg); extern __checkReturn int efx_ev_qmoderate( __in efx_evq_t *eep, __in unsigned int us); extern __checkReturn int efx_ev_qprime( __in efx_evq_t *eep, __in unsigned int count); #if EFSYS_OPT_QSTATS #if EFSYS_OPT_NAMES -extern const char __cs * +extern const char * efx_ev_qstat_name( __in efx_nic_t *enp, __in unsigned int id); #endif /* EFSYS_OPT_NAMES */ extern void efx_ev_qstats_update( __in efx_evq_t *eep, __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); #endif /* EFSYS_OPT_QSTATS */ extern void efx_ev_qdestroy( __in efx_evq_t *eep); /* RX */ -typedef struct efx_rxq_s efx_rxq_t; - extern __checkReturn int efx_rx_init( - __in efx_nic_t *enp); + __inout efx_nic_t *enp); extern void efx_rx_fini( __in efx_nic_t *enp); #if EFSYS_OPT_RX_HDR_SPLIT __checkReturn int efx_rx_hdr_split_enable( __in efx_nic_t *enp, __in unsigned int hdr_buf_size, __in unsigned int pld_buf_size); #endif /* EFSYS_OPT_RX_HDR_SPLIT */ #if EFSYS_OPT_RX_SCATTER __checkReturn int efx_rx_scatter_enable( __in efx_nic_t *enp, __in unsigned int buf_size); #endif /* EFSYS_OPT_RX_SCATTER */ #if EFSYS_OPT_RX_SCALE typedef enum efx_rx_hash_alg_e { EFX_RX_HASHALG_LFSR = 0, EFX_RX_HASHALG_TOEPLITZ } efx_rx_hash_alg_t; typedef enum efx_rx_hash_type_e { EFX_RX_HASH_IPV4 = 0, EFX_RX_HASH_TCPIPV4, EFX_RX_HASH_IPV6, EFX_RX_HASH_TCPIPV6, } efx_rx_hash_type_t; +typedef enum efx_rx_hash_support_e { + EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */ + EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */ +} efx_rx_hash_support_t; + #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */ #define EFX_MAXRSS 64 /* RX indirection entry range */ #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */ +typedef enum efx_rx_scale_support_e { + EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */ + EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */ + EFX_RX_SCALE_SHARED /* Read-only key/indirection table */ +} efx_rx_scale_support_t; + + extern __checkReturn int +efx_rx_hash_support_get( + __in efx_nic_t *enp, + __out efx_rx_hash_support_t *supportp); + + extern __checkReturn int +efx_rx_scale_support_get( + __in efx_nic_t *enp, + __out efx_rx_scale_support_t *supportp); + +extern __checkReturn int efx_rx_scale_mode_set( __in efx_nic_t *enp, __in efx_rx_hash_alg_t alg, __in efx_rx_hash_type_t type, __in boolean_t insert); extern __checkReturn int efx_rx_scale_tbl_set( __in efx_nic_t *enp, __in_ecount(n) unsigned int *table, __in size_t n); extern __checkReturn int -efx_rx_scale_toeplitz_ipv4_key_set( +efx_rx_scale_key_set( __in efx_nic_t *enp, __in_ecount(n) uint8_t *key, __in size_t n); -extern __checkReturn int -efx_rx_scale_toeplitz_ipv6_key_set( +extern uint32_t +efx_psuedo_hdr_hash_get( __in efx_nic_t *enp, - __in_ecount(n) uint8_t *key, - __in size_t n); + __in efx_rx_hash_alg_t func, + __in uint8_t *buffer); -/* - * The prefix is a byte array of one of the forms: - * - * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - * XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.TT.TT.TT.TT - * XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.LL.LL - * - * where: - * - * TT.TT.TT.TT is a 32-bit Toeplitz hash - * LL.LL is a 16-bit LFSR hash - * - * Hash values are in network (big-endian) byte order. - */ - -#define EFX_RX_PREFIX_SIZE 16 - -#define EFX_RX_HASH_VALUE(_func, _buffer) \ - (((_func) == EFX_RX_HASHALG_LFSR) ? \ - ((uint16_t)(((_buffer)[14] << 8) | (_buffer)[15])) : \ - ((uint32_t)(((_buffer)[12] << 24) | \ - ((_buffer)[13] << 16) | \ - ((_buffer)[14] << 8) | \ - (_buffer)[15]))) - -#define EFX_RX_HASH_SIZE(_func) \ - (((_func) == EFX_RX_HASHALG_LFSR) ? \ - sizeof (uint16_t) : \ - sizeof (uint32_t)) - #endif /* EFSYS_OPT_RX_SCALE */ +extern __checkReturn int +efx_psuedo_hdr_pkt_length_get( + __in efx_nic_t *enp, + __in uint8_t *buffer, + __out uint16_t *pkt_lengthp); + #define EFX_RXQ_MAXNDESCS 4096 #define EFX_RXQ_MINNDESCS 512 -#define EFX_RXQ_NDESCS_MASK EFX_MASK(EFX_RXQ_MAXNDESCS, EFX_RXQ_MINNDESCS) - #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE) #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize) typedef enum efx_rxq_type_e { EFX_RXQ_TYPE_DEFAULT, EFX_RXQ_TYPE_SPLIT_HEADER, EFX_RXQ_TYPE_SPLIT_PAYLOAD, EFX_RXQ_TYPE_SCATTER, EFX_RXQ_NTYPES } efx_rxq_type_t; extern __checkReturn int efx_rx_qcreate( __in efx_nic_t *enp, __in unsigned int index, __in unsigned int label, __in efx_rxq_type_t type, __in efsys_mem_t *esmp, __in size_t n, __in uint32_t id, __in efx_evq_t *eep, __deref_out efx_rxq_t **erpp); typedef struct efx_buffer_s { efsys_dma_addr_t eb_addr; size_t eb_size; boolean_t eb_eop; } efx_buffer_t; +typedef struct efx_desc_s { + efx_qword_t ed_eq; +} efx_desc_t; + extern void efx_rx_qpost( __in efx_rxq_t *erp, __in_ecount(n) efsys_dma_addr_t *addrp, __in size_t size, __in unsigned int n, __in unsigned int completed, __in unsigned int added); extern void efx_rx_qpush( __in efx_rxq_t *erp, - __in unsigned int added); + __in unsigned int added, + __inout unsigned int *pushedp); -extern void +extern __checkReturn int efx_rx_qflush( __in efx_rxq_t *erp); extern void efx_rx_qenable( __in efx_rxq_t *erp); extern void efx_rx_qdestroy( __in efx_rxq_t *erp); /* TX */ typedef struct efx_txq_s efx_txq_t; #if EFSYS_OPT_QSTATS -/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 536c5fa5014944bf */ +/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */ typedef enum efx_tx_qstat_e { TX_POST, - TX_UNALIGNED_SPLIT, + TX_POST_PIO, TX_NQSTATS } efx_tx_qstat_t; /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */ #endif /* EFSYS_OPT_QSTATS */ extern __checkReturn int efx_tx_init( __in efx_nic_t *enp); extern void efx_tx_fini( __in efx_nic_t *enp); -#define EFX_TXQ_MAXNDESCS 4096 -#define EFX_TXQ_MINNDESCS 512 +#define EFX_BUG35388_WORKAROUND(_encp) \ + (((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0)) -#define EFX_TXQ_NDESCS_MASK EFX_MASK(EFX_TXQ_MAXNDESCS, EFX_TXQ_MINNDESCS) +#define EFX_TXQ_MAXNDESCS(_encp) \ + ((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096) +#define EFX_TXQ_MINNDESCS 512 + #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE) #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize) +#define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */ + extern __checkReturn int efx_tx_qcreate( __in efx_nic_t *enp, __in unsigned int index, __in unsigned int label, __in efsys_mem_t *esmp, __in size_t n, __in uint32_t id, __in uint16_t flags, __in efx_evq_t *eep, - __deref_out efx_txq_t **etpp); + __deref_out efx_txq_t **etpp, + __out unsigned int *addedp); extern __checkReturn int efx_tx_qpost( __in efx_txq_t *etp, __in_ecount(n) efx_buffer_t *eb, __in unsigned int n, __in unsigned int completed, __inout unsigned int *addedp); extern __checkReturn int efx_tx_qpace( __in efx_txq_t *etp, __in unsigned int ns); -extern void +extern void efx_tx_qpush( - __in efx_txq_t *etp, - __in unsigned int added); + __in efx_txq_t *etp, + __in unsigned int added, + __in unsigned int pushed); -extern void +extern __checkReturn int efx_tx_qflush( - __in efx_txq_t *etp); + __in efx_txq_t *etp); -extern void +extern void efx_tx_qenable( - __in efx_txq_t *etp); + __in efx_txq_t *etp); +extern __checkReturn int +efx_tx_qpio_enable( + __in efx_txq_t *etp); + +extern void +efx_tx_qpio_disable( + __in efx_txq_t *etp); + +extern __checkReturn int +efx_tx_qpio_write( + __in efx_txq_t *etp, + __in_ecount(buf_length) uint8_t *buffer, + __in size_t buf_length, + __in size_t pio_buf_offset); + +extern __checkReturn int +efx_tx_qpio_post( + __in efx_txq_t *etp, + __in size_t pkt_length, + __in unsigned int completed, + __inout unsigned int *addedp); + +extern __checkReturn int +efx_tx_qdesc_post( + __in efx_txq_t *etp, + __in_ecount(n) efx_desc_t *ed, + __in unsigned int n, + __in unsigned int completed, + __inout unsigned int *addedp); + +extern void +efx_tx_qdesc_dma_create( + __in efx_txq_t *etp, + __in efsys_dma_addr_t addr, + __in size_t size, + __in boolean_t eop, + __out efx_desc_t *edp); + +extern void +efx_tx_qdesc_tso_create( + __in efx_txq_t *etp, + __in uint16_t ipv4_id, + __in uint32_t tcp_seq, + __in uint8_t tcp_flags, + __out efx_desc_t *edp); + +extern void +efx_tx_qdesc_vlantci_create( + __in efx_txq_t *etp, + __in uint16_t tci, + __out efx_desc_t *edp); + #if EFSYS_OPT_QSTATS #if EFSYS_OPT_NAMES -extern const char __cs * +extern const char * efx_tx_qstat_name( __in efx_nic_t *etp, __in unsigned int id); #endif /* EFSYS_OPT_NAMES */ extern void efx_tx_qstats_update( __in efx_txq_t *etp, __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); #endif /* EFSYS_OPT_QSTATS */ extern void efx_tx_qdestroy( __in efx_txq_t *etp); /* FILTER */ #if EFSYS_OPT_FILTER +#define EFX_ETHER_TYPE_IPV4 0x0800 +#define EFX_ETHER_TYPE_IPV6 0x86DD + +#define EFX_IPPROTO_TCP 6 +#define EFX_IPPROTO_UDP 17 + typedef enum efx_filter_flag_e { EFX_FILTER_FLAG_RX_RSS = 0x01, /* use RSS to spread across * multiple queues */ EFX_FILTER_FLAG_RX_SCATTER = 0x02, /* enable RX scatter */ - EFX_FILTER_FLAG_RX_OVERRIDE_IP = 0x04, /* MAC filter overrides - * any matching IP filter */ + EFX_FILTER_FLAG_RX_OVER_AUTO = 0x04, /* Override an automatic filter + * (priority EFX_FILTER_PRI_AUTO). + * May only be set by the filter + * implementation for each type. + * A removal request will + * restore the automatic filter + * in its place. */ + EFX_FILTER_FLAG_RX = 0x08, /* Filter is for RX */ + EFX_FILTER_FLAG_TX = 0x10, /* Filter is for TX */ } efx_filter_flag_t; +typedef enum efx_filter_match_flags_e { + EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host + * address */ + EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host + * address */ + EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */ + EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */ + EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */ + EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */ + EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */ + EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */ + EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */ + EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport + * protocol */ + EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address + * I/G bit. Used for RX default + * unicast and multicast/ + * broadcast filters. */ +} efx_filter_match_flags_t; + +typedef enum efx_filter_priority_s { + EFX_FILTER_PRI_HINT = 0, /* Performance hint */ + EFX_FILTER_PRI_AUTO, /* Automatic filter based on device + * address list or hardware + * requirements. This may only be used + * by the filter implementation for + * each NIC type. */ + EFX_FILTER_PRI_MANUAL, /* Manually configured filter */ + EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the + * client (e.g. SR-IOV, HyperV VMQ etc.) + */ +} efx_filter_priority_t; + +/* + * FIXME: All these fields are assumed to be in little-endian byte order. + * It may be better for some to be big-endian. See bug42804. + */ + typedef struct efx_filter_spec_s { - uint8_t efs_type; - uint8_t efs_flags; - uint16_t efs_dmaq_id; - uint32_t efs_dword[3]; + uint32_t efs_match_flags:12; + uint32_t efs_priority:2; + uint32_t efs_flags:6; + uint32_t efs_dmaq_id:12; + uint32_t efs_rss_context; + uint16_t efs_outer_vid; + uint16_t efs_inner_vid; + uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN]; + uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN]; + uint16_t efs_ether_type; + uint8_t efs_ip_proto; + uint16_t efs_loc_port; + uint16_t efs_rem_port; + efx_oword_t efs_rem_host; + efx_oword_t efs_loc_host; } efx_filter_spec_t; + +/* Default values for use in filter specifications */ +#define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff +#define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff +#define EFX_FILTER_SPEC_VID_UNSPEC 0xffff + extern __checkReturn int efx_filter_init( __in efx_nic_t *enp); extern void efx_filter_fini( __in efx_nic_t *enp); extern __checkReturn int -efx_rx_filter_insert( - __in efx_rxq_t *erp, +efx_filter_insert( + __in efx_nic_t *enp, __inout efx_filter_spec_t *spec); extern __checkReturn int -efx_rx_filter_remove( - __in efx_rxq_t *erp, +efx_filter_remove( + __in efx_nic_t *enp, __inout efx_filter_spec_t *spec); - void +extern __checkReturn int efx_filter_restore( __in efx_nic_t *enp); -extern void -efx_filter_spec_rx_ipv4_tcp_full( - __inout efx_filter_spec_t *spec, - __in unsigned int flags, - __in uint32_t src_ip, - __in uint16_t src_tcp, - __in uint32_t dest_ip, - __in uint16_t dest_tcp); +extern __checkReturn int +efx_filter_supported_filters( + __in efx_nic_t *enp, + __out uint32_t *list, + __out size_t *length); extern void -efx_filter_spec_rx_ipv4_tcp_wild( +efx_filter_spec_init_rx( __inout efx_filter_spec_t *spec, - __in unsigned int flags, - __in uint32_t dest_ip, - __in uint16_t dest_tcp); + __in efx_filter_priority_t priority, + __in efx_filter_flag_t flags, + __in efx_rxq_t *erp); extern void -efx_filter_spec_rx_ipv4_udp_full( +efx_filter_spec_init_tx( __inout efx_filter_spec_t *spec, - __in unsigned int flags, - __in uint32_t src_ip, - __in uint16_t src_udp, - __in uint32_t dest_ip, - __in uint16_t dest_udp); + __in efx_txq_t *etp); -extern void -efx_filter_spec_rx_ipv4_udp_wild( +extern __checkReturn int +efx_filter_spec_set_ipv4_local( __inout efx_filter_spec_t *spec, - __in unsigned int flags, - __in uint32_t dest_ip, - __in uint16_t dest_udp); + __in uint8_t proto, + __in uint32_t host, + __in uint16_t port); -extern void -efx_filter_spec_rx_mac_full( +extern __checkReturn int +efx_filter_spec_set_ipv4_full( __inout efx_filter_spec_t *spec, - __in unsigned int flags, - __in uint16_t vlan_id, - __in uint8_t *dest_mac); + __in uint8_t proto, + __in uint32_t lhost, + __in uint16_t lport, + __in uint32_t rhost, + __in uint16_t rport); -extern void -efx_filter_spec_rx_mac_wild( +extern __checkReturn int +efx_filter_spec_set_eth_local( __inout efx_filter_spec_t *spec, - __in unsigned int flags, - __in uint8_t *dest_mac); + __in uint16_t vid, + __in const uint8_t *addr); - extern __checkReturn int -efx_tx_filter_insert( - __in efx_txq_t *etp, +efx_filter_spec_set_uc_def( __inout efx_filter_spec_t *spec); extern __checkReturn int -efx_tx_filter_remove( - __in efx_txq_t *etp, +efx_filter_spec_set_mc_def( __inout efx_filter_spec_t *spec); -extern void -efx_filter_spec_tx_ipv4_tcp_full( - __inout efx_filter_spec_t *spec, - __in uint32_t src_ip, - __in uint16_t src_tcp, - __in uint32_t dest_ip, - __in uint16_t dest_tcp); +#endif /* EFSYS_OPT_FILTER */ -extern void -efx_filter_spec_tx_ipv4_tcp_wild( - __inout efx_filter_spec_t *spec, - __in uint32_t src_ip, - __in uint16_t src_tcp); +/* HASH */ -extern void -efx_filter_spec_tx_ipv4_udp_full( - __inout efx_filter_spec_t *spec, - __in uint32_t src_ip, - __in uint16_t src_udp, - __in uint32_t dest_ip, - __in uint16_t dest_udp); +extern __checkReturn uint32_t +efx_hash_dwords( + __in_ecount(count) uint32_t const *input, + __in size_t count, + __in uint32_t init); -extern void -efx_filter_spec_tx_ipv4_udp_wild( - __inout efx_filter_spec_t *spec, - __in uint32_t src_ip, - __in uint16_t src_udp); - -extern void -efx_filter_spec_tx_mac_full( - __inout efx_filter_spec_t *spec, - __in uint16_t vlan_id, - __in uint8_t *src_mac); - -extern void -efx_filter_spec_tx_mac_wild( - __inout efx_filter_spec_t *spec, - __in uint8_t *src_mac); - -#endif /* EFSYS_OPT_FILTER */ +extern __checkReturn uint32_t +efx_hash_bytes( + __in_ecount(length) uint8_t const *input, + __in size_t length, + __in uint32_t init); #ifdef __cplusplus } #endif #endif /* _SYS_EFX_H */ Property changes on: head/sys/dev/sfxge/common/efx.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_bootcfg.c =================================================================== --- head/sys/dev/sfxge/common/efx_bootcfg.c (revision 283513) +++ head/sys/dev/sfxge/common/efx_bootcfg.c (revision 283514) @@ -1,345 +1,350 @@ /*- - * Copyright 2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2009-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include "efsys.h" #include "efx.h" #include "efx_types.h" #include "efx_impl.h" #if EFSYS_OPT_BOOTCFG /* * Maximum size of BOOTCFG block across all nics as understood by SFCgPXE. * A multiple of 0x100 so trailing 0xff characters don't contrinbute to the * checksum. */ #define BOOTCFG_MAX_SIZE 0x1000 #define DHCP_END (uint8_t)0xff #define DHCP_PAD (uint8_t)0 static __checkReturn uint8_t efx_bootcfg_csum( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size) { _NOTE(ARGUNUSED(enp)) unsigned int pos; uint8_t checksum = 0; for (pos = 0; pos < size; pos++) checksum += data[pos]; return (checksum); } static __checkReturn int efx_bootcfg_verify( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size, - __out size_t *usedp) + __out_opt size_t *usedp) { size_t offset = 0; size_t used = 0; int rc; /* Start parsing tags immediatly after the checksum */ for (offset = 1; offset < size; ) { uint8_t tag; uint8_t length; /* Consume tag */ tag = data[offset]; if (tag == DHCP_END) { offset++; used = offset; break; } if (tag == DHCP_PAD) { offset++; continue; } /* Consume length */ if (offset + 1 >= size) { rc = ENOSPC; goto fail1; } length = data[offset + 1]; /* Consume *length */ if (offset + 1 + length >= size) { rc = ENOSPC; goto fail2; } offset += 2 + length; used = offset; } /* Checksum the entire sector, including bytes after any DHCP_END */ if (efx_bootcfg_csum(enp, data, size) != 0) { rc = EINVAL; goto fail3; } if (usedp != NULL) *usedp = used; return (0); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } int efx_bootcfg_read( __in efx_nic_t *enp, __out_bcount(size) caddr_t data, __in size_t size) { uint8_t *payload = NULL; size_t used_bytes; size_t sector_length; int rc; rc = efx_nvram_size(enp, EFX_NVRAM_BOOTROM_CFG, §or_length); if (rc != 0) goto fail1; /* * We need to read the entire BOOTCFG area to ensure we read all the * tags, because legacy bootcfg sectors are not guaranteed to end with * a DHCP_END character. If the user hasn't supplied a sufficiently * large buffer then use our own buffer. */ if (sector_length > BOOTCFG_MAX_SIZE) sector_length = BOOTCFG_MAX_SIZE; if (sector_length > size) { EFSYS_KMEM_ALLOC(enp->en_esip, sector_length, payload); if (payload == NULL) { rc = ENOMEM; goto fail2; } } else payload = (uint8_t *)data; if ((rc = efx_nvram_rw_start(enp, EFX_NVRAM_BOOTROM_CFG, NULL)) != 0) goto fail3; rc = efx_nvram_read_chunk(enp, EFX_NVRAM_BOOTROM_CFG, 0, (caddr_t)payload, sector_length); efx_nvram_rw_finish(enp, EFX_NVRAM_BOOTROM_CFG); if (rc != 0) goto fail4; /* Verify that the area is correctly formatted and checksummed */ rc = efx_bootcfg_verify(enp, (caddr_t)payload, sector_length, &used_bytes); if (rc != 0 || used_bytes == 0) { payload[0] = (uint8_t)~DHCP_END; payload[1] = DHCP_END; used_bytes = 2; } EFSYS_ASSERT(used_bytes >= 2); /* checksum and DHCP_END */ EFSYS_ASSERT(used_bytes <= sector_length); /* * Legacy bootcfg sectors don't terminate with a DHCP_END character. * Modify the returned payload so it does. BOOTCFG_MAX_SIZE is by * definition large enough for any valid (per-port) bootcfg sector, * so reinitialise the sector if there isn't room for the character. */ if (payload[used_bytes - 1] != DHCP_END) { if (used_bytes + 1 > sector_length) { payload[0] = 0; used_bytes = 1; } payload[used_bytes] = DHCP_END; ++used_bytes; } /* * Verify that the user supplied buffer is large enough for the * entire used bootcfg area, then copy into the user supplied buffer. */ if (used_bytes > size) { rc = ENOSPC; goto fail5; } if (sector_length > size) { memcpy(data, payload, used_bytes); EFSYS_KMEM_FREE(enp->en_esip, sector_length, payload); } /* Zero out the unused portion of the user buffer */ if (used_bytes < size) (void) memset(data + used_bytes, 0, size - used_bytes); /* * The checksum includes trailing data after any DHCP_END character, * which we've just modified (by truncation or appending DHCP_END). */ data[0] -= efx_bootcfg_csum(enp, data, size); return (0); fail5: EFSYS_PROBE(fail5); fail4: EFSYS_PROBE(fail4); fail3: EFSYS_PROBE(fail3); if (sector_length > size) EFSYS_KMEM_FREE(enp->en_esip, sector_length, payload); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } int efx_bootcfg_write( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size) { uint8_t *chunk; uint8_t checksum; size_t sector_length; size_t chunk_length; size_t used_bytes; size_t offset; size_t remaining; int rc; rc = efx_nvram_size(enp, EFX_NVRAM_BOOTROM_CFG, §or_length); if (rc != 0) goto fail1; if (sector_length > BOOTCFG_MAX_SIZE) sector_length = BOOTCFG_MAX_SIZE; if ((rc = efx_bootcfg_verify(enp, data, size, &used_bytes)) != 0) goto fail2; /* The caller *must* terminate their block with a DHCP_END character */ EFSYS_ASSERT(used_bytes >= 2); /* checksum and DHCP_END */ if ((uint8_t)data[used_bytes - 1] != DHCP_END) { rc = ENOENT; goto fail3; } /* Check that the hardware has support for this much data */ if (used_bytes > MIN(sector_length, BOOTCFG_MAX_SIZE)) { rc = ENOSPC; goto fail4; } rc = efx_nvram_rw_start(enp, EFX_NVRAM_BOOTROM_CFG, &chunk_length); if (rc != 0) goto fail5; EFSYS_KMEM_ALLOC(enp->en_esip, chunk_length, chunk); if (chunk == NULL) { rc = ENOMEM; goto fail6; } if ((rc = efx_nvram_erase(enp, EFX_NVRAM_BOOTROM_CFG)) != 0) goto fail7; /* * Write the entire sector_length bytes of data in chunks. Zero out * all data following the DHCP_END, and adjust the checksum */ checksum = efx_bootcfg_csum(enp, data, used_bytes); for (offset = 0; offset < sector_length; offset += remaining) { remaining = MIN(chunk_length, sector_length - offset); /* Fill chunk */ (void) memset(chunk, 0x0, chunk_length); if (offset < used_bytes) memcpy(chunk, data + offset, MIN(remaining, used_bytes - offset)); /* Adjust checksum */ if (offset == 0) chunk[0] -= checksum; if ((rc = efx_nvram_write_chunk(enp, EFX_NVRAM_BOOTROM_CFG, offset, (caddr_t)chunk, remaining)) != 0) goto fail8; } efx_nvram_rw_finish(enp, EFX_NVRAM_BOOTROM_CFG); EFSYS_KMEM_FREE(enp->en_esip, chunk_length, chunk); return (0); fail8: EFSYS_PROBE(fail8); fail7: EFSYS_PROBE(fail7); EFSYS_KMEM_FREE(enp->en_esip, chunk_length, chunk); fail6: EFSYS_PROBE(fail6); efx_nvram_rw_finish(enp, EFX_NVRAM_BOOTROM_CFG); fail5: EFSYS_PROBE(fail5); fail4: EFSYS_PROBE(fail4); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } #endif /* EFSYS_OPT_BOOTCFG */ Property changes on: head/sys/dev/sfxge/common/efx_bootcfg.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_check.h =================================================================== --- head/sys/dev/sfxge/common/efx_check.h (nonexistent) +++ head/sys/dev/sfxge/common/efx_check.h (revision 283514) @@ -0,0 +1,388 @@ +/*- + * Copyright (c) 2012-2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + * + * $FreeBSD$ + */ + +#ifndef _SYS_EFX_CHECK_H +#define _SYS_EFX_CHECK_H + +#include "efsys.h" + +/* + * Check that the efsys.h header in client code has a valid combination of + * EFSYS_OPT_xxx options. + * + * NOTE: Keep checks for obsolete options here to ensure that they are removed + * from client code (and do not reappear in merges from other branches). + */ + +/* Support NVRAM based boot config */ +#if EFSYS_OPT_BOOTCFG +# if !EFSYS_OPT_NVRAM +# error "BOOTCFG requires NVRAM" +# endif +#endif /* EFSYS_OPT_BOOTCFG */ + +/* Verify chip implements accessed registers */ +#if EFSYS_OPT_CHECK_REG +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) +# error "CHECK_REG requires FALCON or SIENA or HUNTINGTON" +# endif +#endif /* EFSYS_OPT_CHECK_REG */ + +/* Decode fatal errors */ +#if EFSYS_OPT_DECODE_INTR_FATAL +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA) +# if EFSYS_OPT_HUNTINGTON +# error "INTR_FATAL not supported on HUNTINGTON" +# endif +# error "INTR_FATAL requires FALCON or SIENA" +# endif +#endif /* EFSYS_OPT_DECODE_INTR_FATAL */ + +/* Support diagnostic hardware tests */ +#if EFSYS_OPT_DIAG +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) +# error "DIAG requires FALCON or SIENA or HUNTINGTON" +# endif +#endif /* EFSYS_OPT_DIAG */ + +/* Support optimized EVQ data access */ +#if EFSYS_OPT_EV_PREFETCH +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) +# error "EV_PREFETCH requires FALCON or SIENA or HUNTINGTON" +# endif +#endif /* EFSYS_OPT_EV_PREFETCH */ + +/* Support overriding the NVRAM and VPD configuration */ +#if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE +# if !EFSYS_OPT_FALCON +# error "FALCON_NIC_CFG_OVERRIDE requires FALCON" +# endif +#endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */ + +/* Support hardware packet filters */ +#if EFSYS_OPT_FILTER +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) +# error "FILTER requires FALCON or SIENA or HUNTINGTON" +# endif +#endif /* EFSYS_OPT_FILTER */ + +#if EFSYS_OPT_HUNTINGTON +# if !EFSYS_OPT_FILTER +# error "HUNTINGTON requires FILTER" +# endif +#endif /* EFSYS_OPT_HUNTINGTON */ + +/* Support hardware loopback modes */ +#if EFSYS_OPT_LOOPBACK +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) +# error "LOOPBACK requires FALCON or SIENA or HUNTINGTON" +# endif +#endif /* EFSYS_OPT_LOOPBACK */ + +/* Support Falcon GMAC */ +#if EFSYS_OPT_MAC_FALCON_GMAC +# if !EFSYS_OPT_FALCON +# error "MAC_FALCON_GMAC requires FALCON" +# endif +#endif /* EFSYS_OPT_MAC_FALCON_GMAC */ + +/* Support Falcon XMAC */ +#if EFSYS_OPT_MAC_FALCON_XMAC +# if !EFSYS_OPT_FALCON +# error "MAC_FALCON_XMAC requires FALCON" +# endif +#endif /* EFSYS_OPT_MAC_FALCON_XMAC */ + +/* Support MAC statistics */ +#if EFSYS_OPT_MAC_STATS +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) +# error "MAC_STATS requires FALCON or SIENA or HUNTINGTON" +# endif +#endif /* EFSYS_OPT_MAC_STATS */ + +/* Support management controller messages */ +#if EFSYS_OPT_MCDI +# if !(EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) +# if EFSYS_OPT_FALCON +# error "MCDI not supported on FALCON" +# endif +# error "MCDI requires SIENA or HUNTINGTON" +# endif +#endif /* EFSYS_OPT_MCDI */ + +#if EFSYS_OPT_SIENA && !EFSYS_OPT_MCDI +# error "SIENA requires MCDI" +#endif +#if EFSYS_OPT_HUNTINGTON && !EFSYS_OPT_MCDI +# error "HUNTINGTON requires MCDI" +#endif + +/* Support LM87 monitor */ +#if EFSYS_OPT_MON_LM87 +# if !EFSYS_OPT_FALCON +# error "MON_LM87 requires FALCON" +# endif +#endif /* EFSYS_OPT_MON_LM87 */ + +/* Support MAX6647 monitor */ +#if EFSYS_OPT_MON_MAX6647 +# if !EFSYS_OPT_FALCON +# error "MON_MAX6647 requires FALCON" +# endif +#endif /* EFSYS_OPT_MON_MAX6647 */ + +/* Support null monitor */ +#if EFSYS_OPT_MON_NULL +# if !EFSYS_OPT_FALCON +# error "MON_NULL requires FALCON" +# endif +#endif /* EFSYS_OPT_MON_NULL */ + +/* Support Siena monitor */ +#ifdef EFSYS_OPT_MON_SIENA +# error "MON_SIENA is obsolete use MON_MCDI" +#endif /* EFSYS_OPT_MON_SIENA*/ + +/* Support Huntington monitor */ +#ifdef EFSYS_OPT_MON_HUNTINGTON +# error "MON_HUNTINGTON is obsolete use MON_MCDI" +#endif /* EFSYS_OPT_MON_HUNTINGTON*/ + +/* Support monitor statistics (voltage/temperature) */ +#if EFSYS_OPT_MON_STATS +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) +# error "MON_STATS requires FALCON or SIENA or HUNTINGTON" +# endif +#endif /* EFSYS_OPT_MON_STATS */ + +/* Support Monitor via mcdi */ +#if EFSYS_OPT_MON_MCDI +# if !(EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) +# error "MON_MCDI requires SIENA or HUNTINGTON" +# endif +#endif /* EFSYS_OPT_MON_MCDI*/ + +/* Support printable names for statistics */ +#if EFSYS_OPT_NAMES +# if !(EFSYS_OPT_LOOPBACK || EFSYS_OPT_MAC_STATS || EFSYS_OPT_MCDI || \ + EFSYS_MON_STATS || EFSYS_OPT_PHY_PROPS || EFSYS_OPT_PHY_STATS || \ + EFSYS_OPT_QSTATS) +# error "NAMES requires LOOPBACK or xxxSTATS or MCDI or PHY_PROPS" +# endif +#endif /* EFSYS_OPT_NAMES */ + +/* Support non volatile configuration */ +#if EFSYS_OPT_NVRAM +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) +# error "NVRAM requires FALCON or SIENA or HUNTINGTON" +# endif +#endif /* EFSYS_OPT_NVRAM */ + +/* Support Falcon bootrom */ +#if EFSYS_OPT_NVRAM_FALCON_BOOTROM +# if !EFSYS_OPT_NVRAM +# error "NVRAM_FALCON_BOOTROM requires NVRAM" +# endif +# if !EFSYS_OPT_FALCON +# error "NVRAM_FALCON_BOOTROM requires FALCON" +# endif +#endif /* EFSYS_OPT_NVRAM_FALCON_BOOTROM */ + +/* Support NVRAM config for SFT9001 */ +#if EFSYS_OPT_NVRAM_SFT9001 +# if !EFSYS_OPT_NVRAM +# error "NVRAM_SFT9001 requires NVRAM" +# endif +# if !EFSYS_OPT_FALCON +# error "NVRAM_SFT9001 requires FALCON" +# endif +#endif /* EFSYS_OPT_NVRAM_SFT9001 */ + +/* Support NVRAM config for SFX7101 */ +#if EFSYS_OPT_NVRAM_SFX7101 +# if !EFSYS_OPT_NVRAM +# error "NVRAM_SFX7101 requires NVRAM" +# endif +# if !EFSYS_OPT_FALCON +# error "NVRAM_SFX7101 requires FALCON" +# endif +#endif /* EFSYS_OPT_NVRAM_SFX7101 */ + +/* Support PCIe interface tuning */ +#if EFSYS_OPT_PCIE_TUNE +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA) +# error "PCIE_TUNE requires FALCON or SIENA" +# endif +#endif /* EFSYS_OPT_PCIE_TUNE */ + +/* Support PHY BIST diagnostics */ +#if EFSYS_OPT_PHY_BIST +# error "PHY_BIST is obsolete. It has been replaced by the BIST option." +#endif /* EFSYS_OPT_PHY_BIST */ + +/* Support PHY flags */ +#if EFSYS_OPT_PHY_FLAGS +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA) +# error "PHY_FLAGS requires FALCON or SIENA" +# endif +#endif /* EFSYS_OPT_PHY_FLAGS */ + +/* Support for PHY LED control */ +#if EFSYS_OPT_PHY_LED_CONTROL +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA) +# error "PHY_LED_CONTROL requires FALCON or SIENA" +# endif +#endif /* EFSYS_OPT_PHY_LED_CONTROL */ + +/* Support NULL PHY */ +#if EFSYS_OPT_PHY_NULL +# if !EFSYS_OPT_FALCON +# error "PHY_NULL requires FALCON" +# endif +#endif /* EFSYS_OPT_PHY_NULL */ + +/* Obsolete option */ +#ifdef EFSYS_OPT_PHY_PM8358 +# error "EFSYS_OPT_PHY_PM8358 is obsolete and is not supported." +#endif + +/* Support PHY properties */ +#if EFSYS_OPT_PHY_PROPS +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA) +# error "PHY_PROPS requires FALCON or SIENA" +# endif +#endif /* EFSYS_OPT_PHY_PROPS */ + +/* Support QT2022C2 PHY */ +#if EFSYS_OPT_PHY_QT2022C2 +# if !EFSYS_OPT_FALCON +# error "PHY_QT2022C2 requires FALCON" +# endif +#endif /* EFSYS_OPT_PHY_QT2022C2 */ + +/* Support QT2025C PHY (Wakefield NIC) */ +#if EFSYS_OPT_PHY_QT2025C +# if !EFSYS_OPT_FALCON +# error "PHY_QT2025C requires FALCON" +# endif +#endif /* EFSYS_OPT_PHY_QT2025C */ + +/* Support SFT9001 PHY (Starbolt NIC) */ +#if EFSYS_OPT_PHY_SFT9001 +# if !EFSYS_OPT_FALCON +# error "PHY_SFT9001 requires FALCON" +# endif +#endif /* EFSYS_OPT_PHY_SFT9001 */ + +/* Support SFX7101 PHY (SFE4001 NIC) */ +#if EFSYS_OPT_PHY_SFX7101 +# if !EFSYS_OPT_FALCON +# error "PHY_SFX7101 requires FALCON" +# endif +#endif /* EFSYS_OPT_PHY_SFX7101 */ + +/* Support PHY statistics */ +#if EFSYS_OPT_PHY_STATS +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA) +# error "PHY_STATS requires FALCON or SIENA" +# endif +#endif /* EFSYS_OPT_PHY_STATS */ + +/* Support TXC43128 PHY (SFE4003 NIC) */ +#if EFSYS_OPT_PHY_TXC43128 +# if !EFSYS_OPT_FALCON +# error "PHY_TXC43128 requires FALCON" +# endif +#endif /* EFSYS_OPT_PHY_TXC43128 */ + +/* Support EVQ/RXQ/TXQ statistics */ +#if EFSYS_OPT_QSTATS +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) +# error "QSTATS requires FALCON or SIENA or HUNTINGTON" +# endif +#endif /* EFSYS_OPT_QSTATS */ + +/* Support receive header split */ +#if EFSYS_OPT_RX_HDR_SPLIT +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) +# error "RX_HDR_SPLIT requires FALCON or SIENA or HUNTINGTON" +# endif +#endif /* EFSYS_OPT_RX_HDR_SPLIT */ + +/* Support receive scaling (RSS) */ +#if EFSYS_OPT_RX_SCALE +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) +# error "RX_SCALE requires FALCON or SIENA or HUNTINGTON" +# endif +#endif /* EFSYS_OPT_RX_SCALE */ + +/* Support receive scatter DMA */ +#if EFSYS_OPT_RX_SCATTER +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) +# error "RX_SCATTER requires FALCON or SIENA or HUNTINGTON" +# endif +#endif /* EFSYS_OPT_RX_SCATTER */ + +/* Obsolete option */ +#ifdef EFSYS_OPT_STAT_NAME +# error "EFSYS_OPT_STAT_NAME is obsolete (replaced by EFSYS_OPT_NAMES)." +#endif + +/* Support PCI Vital Product Data (VPD) */ +#if EFSYS_OPT_VPD +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) +# error "VPD requires FALCON or SIENA or HUNTINGTON" +# endif +#endif /* EFSYS_OPT_VPD */ + +/* Support Wake on LAN */ +#if EFSYS_OPT_WOL +# if !EFSYS_OPT_SIENA +# error "WOL requires SIENA" +# endif +#endif /* EFSYS_OPT_WOL */ + +/* Support calculating multicast pktfilter in common code */ +#if EFSYS_OPT_MCAST_FILTER_LIST +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) +# error "MCAST_FILTER_LIST requires FALCON or SIENA or HUNTINGTON" +# endif +#endif /* EFSYS_OPT_MCAST_FILTER_LIST */ + +/* Support BIST */ +#if EFSYS_OPT_BIST +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) +# error "BIST requires FALCON or SIENA or HUNTINGTON" +# endif +#endif /* EFSYS_OPT_BIST */ + +#endif /* _SYS_EFX_CHECK_H */ Property changes on: head/sys/dev/sfxge/common/efx_check.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_crc32.c =================================================================== --- head/sys/dev/sfxge/common/efx_crc32.c (nonexistent) +++ head/sys/dev/sfxge/common/efx_crc32.c (revision 283514) @@ -0,0 +1,127 @@ +/*- + * Copyright (c) 2013-2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "efsys.h" +#include "efx.h" +#include "efx_types.h" +#include "efx_impl.h" + +/* + * Precomputed table for computing IEEE 802.3 CRC32 + * with polynomial 0x04c11db7 (bit-reversed 0xedb88320) + */ + +static const uint32_t crc32_table[256] = { + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, + 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, + 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, + 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, + 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, + 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, + 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, + 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, + 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, + 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, + 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, + 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, + 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, + 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, + 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, + 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, + 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, + 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, + 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, + 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, + 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, + 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, + 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, + 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, + 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, + 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, + 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, + 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, + 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, + 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, + 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, + 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, + 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, + 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, + 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, + 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, + 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, + 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, + 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, + 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, + 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, + 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, + 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, + 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, + 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, + 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, + 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, + 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, + 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, + 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, + 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, + 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, + 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, + 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, + 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, + 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, + 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, + 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, + 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d +}; + +/* Calculate the IEEE 802.3 CRC32 of a MAC addr */ + __checkReturn uint32_t +efx_crc32_calculate( + __in uint32_t crc_init, + __in_ecount(length) uint8_t const *input, + __in int length) +{ + int index; + uint32_t crc = crc_init; + + for (index = 0; index < length; index++) { + uint32_t data = *(input++); + crc = (crc >> 8) ^ crc32_table[(crc ^ data) & 0xff]; + } + + return (crc); +} Property changes on: head/sys/dev/sfxge/common/efx_crc32.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_ev.c =================================================================== --- head/sys/dev/sfxge/common/efx_ev.c (revision 283513) +++ head/sys/dev/sfxge/common/efx_ev.c (revision 283514) @@ -1,1125 +1,1465 @@ /*- - * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2007-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include "efsys.h" #include "efx.h" #include "efx_types.h" #include "efx_regs.h" #include "efx_impl.h" +#include "mcdi_mon.h" #if EFSYS_OPT_QSTATS #define EFX_EV_QSTAT_INCR(_eep, _stat) \ do { \ (_eep)->ee_stat[_stat]++; \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #else #define EFX_EV_QSTAT_INCR(_eep, _stat) #endif +#define EFX_EV_PRESENT(_qword) \ + (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \ + EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff) + + + +#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA + +static __checkReturn int +falconsiena_ev_init( + __in efx_nic_t *enp); + +static void +falconsiena_ev_fini( + __in efx_nic_t *enp); + +static __checkReturn int +falconsiena_ev_qcreate( + __in efx_nic_t *enp, + __in unsigned int index, + __in efsys_mem_t *esmp, + __in size_t n, + __in uint32_t id, + __in efx_evq_t *eep); + +static void +falconsiena_ev_qdestroy( + __in efx_evq_t *eep); + +static __checkReturn int +falconsiena_ev_qprime( + __in efx_evq_t *eep, + __in unsigned int count); + +static void +falconsiena_ev_qpoll( + __in efx_evq_t *eep, + __inout unsigned int *countp, + __in const efx_ev_callbacks_t *eecp, + __in_opt void *arg); + +static void +falconsiena_ev_qpost( + __in efx_evq_t *eep, + __in uint16_t data); + +static __checkReturn int +falconsiena_ev_qmoderate( + __in efx_evq_t *eep, + __in unsigned int us); + +#if EFSYS_OPT_QSTATS +static void +falconsiena_ev_qstats_update( + __in efx_evq_t *eep, + __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); + +#endif + +#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ + +#if EFSYS_OPT_FALCON +static efx_ev_ops_t __efx_ev_falcon_ops = { + falconsiena_ev_init, /* eevo_init */ + falconsiena_ev_fini, /* eevo_fini */ + falconsiena_ev_qcreate, /* eevo_qcreate */ + falconsiena_ev_qdestroy, /* eevo_qdestroy */ + falconsiena_ev_qprime, /* eevo_qprime */ + falconsiena_ev_qpost, /* eevo_qpost */ + falconsiena_ev_qmoderate, /* eevo_qmoderate */ +#if EFSYS_OPT_QSTATS + falconsiena_ev_qstats_update, /* eevo_qstats_update */ +#endif +}; +#endif /* EFSYS_OPT_FALCON */ + +#if EFSYS_OPT_SIENA +static efx_ev_ops_t __efx_ev_siena_ops = { + falconsiena_ev_init, /* eevo_init */ + falconsiena_ev_fini, /* eevo_fini */ + falconsiena_ev_qcreate, /* eevo_qcreate */ + falconsiena_ev_qdestroy, /* eevo_qdestroy */ + falconsiena_ev_qprime, /* eevo_qprime */ + falconsiena_ev_qpost, /* eevo_qpost */ + falconsiena_ev_qmoderate, /* eevo_qmoderate */ +#if EFSYS_OPT_QSTATS + falconsiena_ev_qstats_update, /* eevo_qstats_update */ +#endif +}; +#endif /* EFSYS_OPT_SIENA */ + +#if EFSYS_OPT_HUNTINGTON +static efx_ev_ops_t __efx_ev_hunt_ops = { + hunt_ev_init, /* eevo_init */ + hunt_ev_fini, /* eevo_fini */ + hunt_ev_qcreate, /* eevo_qcreate */ + hunt_ev_qdestroy, /* eevo_qdestroy */ + hunt_ev_qprime, /* eevo_qprime */ + hunt_ev_qpost, /* eevo_qpost */ + hunt_ev_qmoderate, /* eevo_qmoderate */ +#if EFSYS_OPT_QSTATS + hunt_ev_qstats_update, /* eevo_qstats_update */ +#endif +}; +#endif /* EFSYS_OPT_HUNTINGTON */ + + __checkReturn int efx_ev_init( __in efx_nic_t *enp) { - efx_oword_t oword; + efx_ev_ops_t *eevop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); if (enp->en_mod_flags & EFX_MOD_EV) { rc = EINVAL; goto fail1; } + switch (enp->en_family) { +#if EFSYS_OPT_FALCON + case EFX_FAMILY_FALCON: + eevop = (efx_ev_ops_t *)&__efx_ev_falcon_ops; + break; +#endif /* EFSYS_OPT_FALCON */ + +#if EFSYS_OPT_SIENA + case EFX_FAMILY_SIENA: + eevop = (efx_ev_ops_t *)&__efx_ev_siena_ops; + break; +#endif /* EFSYS_OPT_SIENA */ + +#if EFSYS_OPT_HUNTINGTON + case EFX_FAMILY_HUNTINGTON: + eevop = (efx_ev_ops_t *)&__efx_ev_hunt_ops; + break; +#endif /* EFSYS_OPT_HUNTINGTON */ + + default: + EFSYS_ASSERT(0); + rc = ENOTSUP; + goto fail1; + } + EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0); + if ((rc = eevop->eevo_init(enp)) != 0) + goto fail2; + + enp->en_eevop = eevop; + enp->en_mod_flags |= EFX_MOD_EV; + return (0); + +fail2: + EFSYS_PROBE(fail2); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + enp->en_eevop = NULL; + enp->en_mod_flags &= ~EFX_MOD_EV; + return (rc); +} + + void +efx_ev_fini( + __in efx_nic_t *enp) +{ + efx_ev_ops_t *eevop = enp->en_eevop; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV); + EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX)); + EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX)); + EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0); + + eevop->eevo_fini(enp); + + enp->en_eevop = NULL; + enp->en_mod_flags &= ~EFX_MOD_EV; +} + + + __checkReturn int +efx_ev_qcreate( + __in efx_nic_t *enp, + __in unsigned int index, + __in efsys_mem_t *esmp, + __in size_t n, + __in uint32_t id, + __deref_out efx_evq_t **eepp) +{ + efx_ev_ops_t *eevop = enp->en_eevop; + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + efx_evq_t *eep; + int rc; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV); + + EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit); + + /* Allocate an EVQ object */ + EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep); + if (eep == NULL) { + rc = ENOMEM; + goto fail1; + } + + eep->ee_magic = EFX_EVQ_MAGIC; + eep->ee_enp = enp; + eep->ee_index = index; + eep->ee_mask = n - 1; + eep->ee_esmp = esmp; + + if ((rc = eevop->eevo_qcreate(enp, index, esmp, n, id, eep)) != 0) + goto fail2; + + enp->en_ev_qcount++; + *eepp = eep; + + return (0); + +fail2: + EFSYS_PROBE(fail2); + EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep); +fail1: + EFSYS_PROBE1(fail1, int, rc); + return (rc); +} + + void +efx_ev_qdestroy( + __in efx_evq_t *eep) +{ + efx_nic_t *enp = eep->ee_enp; + efx_ev_ops_t *eevop = enp->en_eevop; + + EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); + + EFSYS_ASSERT(enp->en_ev_qcount != 0); + --enp->en_ev_qcount; + + eevop->eevo_qdestroy(eep); + + /* Free the EVQ object */ + EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep); +} + + __checkReturn int +efx_ev_qprime( + __in efx_evq_t *eep, + __in unsigned int count) +{ + efx_nic_t *enp = eep->ee_enp; + efx_ev_ops_t *eevop = enp->en_eevop; + int rc; + + EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); + + if (!(enp->en_mod_flags & EFX_MOD_INTR)) { + rc = EINVAL; + goto fail1; + } + + if ((rc = eevop->eevo_qprime(eep, count)) != 0) + goto fail2; + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + return (rc); +} + + __checkReturn boolean_t +efx_ev_qpending( + __in efx_evq_t *eep, + __in unsigned int count) +{ + size_t offset; + efx_qword_t qword; + + EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); + + offset = (count & eep->ee_mask) * sizeof (efx_qword_t); + EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword); + + return (EFX_EV_PRESENT(qword)); +} + +#if EFSYS_OPT_EV_PREFETCH + + void +efx_ev_qprefetch( + __in efx_evq_t *eep, + __in unsigned int count) +{ + efx_nic_t *enp = eep->ee_enp; + unsigned int offset; + + EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); + + offset = (count & eep->ee_mask) * sizeof (efx_qword_t); + EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); +} + +#endif /* EFSYS_OPT_EV_PREFETCH */ + + void +efx_ev_qpoll( + __in efx_evq_t *eep, + __inout unsigned int *countp, + __in const efx_ev_callbacks_t *eecp, + __in_opt void *arg) +{ + EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); + /* + * FIXME: Huntington will require support for hardware event batching + * and merging, which will need a different ev_qpoll implementation. + * + * Without those features the Falcon/Siena code can be used unchanged. + */ + EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN); + EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH); + + EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV); + EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV); + EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV); + EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV == + FSE_AZ_EV_CODE_DRV_GEN_EV); +#if EFSYS_OPT_MCDI + EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV == + FSE_AZ_EV_CODE_MCDI_EVRESPONSE); +#endif + falconsiena_ev_qpoll(eep, countp, eecp, arg); +} + + void +efx_ev_qpost( + __in efx_evq_t *eep, + __in uint16_t data) +{ + efx_nic_t *enp = eep->ee_enp; + efx_ev_ops_t *eevop = enp->en_eevop; + + EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); + + EFSYS_ASSERT(eevop != NULL && + eevop->eevo_qpost != NULL); + + eevop->eevo_qpost(eep, data); +} + + __checkReturn int +efx_ev_qmoderate( + __in efx_evq_t *eep, + __in unsigned int us) +{ + efx_nic_t *enp = eep->ee_enp; + efx_ev_ops_t *eevop = enp->en_eevop; + int rc; + + EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); + + if ((rc = eevop->eevo_qmoderate(eep, us)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + return (rc); +} + +#if EFSYS_OPT_QSTATS + void +efx_ev_qstats_update( + __in efx_evq_t *eep, + __inout_ecount(EV_NQSTATS) efsys_stat_t *stat) + +{ efx_nic_t *enp = eep->ee_enp; + efx_ev_ops_t *eevop = enp->en_eevop; + + EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); + + eevop->eevo_qstats_update(eep, stat); +} + +#endif /* EFSYS_OPT_QSTATS */ + +#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA + +static __checkReturn int +falconsiena_ev_init( + __in efx_nic_t *enp) +{ + efx_oword_t oword; + + /* * Program the event queue for receive and transmit queue * flush events. */ EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword); EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0); EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword); - enp->en_mod_flags |= EFX_MOD_EV; return (0); -fail1: - EFSYS_PROBE1(fail1, int, rc); - - return (rc); } static __checkReturn boolean_t -efx_ev_rx_not_ok( +falconsiena_ev_rx_not_ok( __in efx_evq_t *eep, __in efx_qword_t *eqp, __in uint32_t label, __in uint32_t id, __inout uint16_t *flagsp) { boolean_t ignore = B_FALSE; if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) { EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC); EFSYS_PROBE(tobe_disc); /* * Assume this is a unicast address mismatch, unless below * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or * EV_RX_PAUSE_FRM_ERR is set. */ (*flagsp) |= EFX_ADDR_MISMATCH; } if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) { EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id); EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC); (*flagsp) |= EFX_DISCARD; #if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER) /* * Lookout for payload queue ran dry errors and ignore them. * * Sadly for the header/data split cases, the descriptor * pointer in this event refers to the header queue and * therefore cannot be easily detected as duplicate. * So we drop these and rely on the receive processing seeing * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard * the partially received packet. */ if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) && (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) && (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0)) ignore = B_TRUE; #endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */ } if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) { EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR); EFSYS_PROBE(crc_err); (*flagsp) &= ~EFX_ADDR_MISMATCH; (*flagsp) |= EFX_DISCARD; } if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) { EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR); EFSYS_PROBE(pause_frm_err); (*flagsp) &= ~EFX_ADDR_MISMATCH; (*flagsp) |= EFX_DISCARD; } if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) { EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR); EFSYS_PROBE(owner_id_err); (*flagsp) |= EFX_DISCARD; } if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) { EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR); EFSYS_PROBE(ipv4_err); (*flagsp) &= ~EFX_CKSUM_IPV4; } if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) { EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR); EFSYS_PROBE(udp_chk_err); (*flagsp) &= ~EFX_CKSUM_TCPUDP; } if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) { EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR); /* * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error * condition. */ (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP); } return (ignore); } static __checkReturn boolean_t -efx_ev_rx( +falconsiena_ev_rx( __in efx_evq_t *eep, __in efx_qword_t *eqp, __in const efx_ev_callbacks_t *eecp, __in_opt void *arg) { efx_nic_t *enp = eep->ee_enp; uint32_t id; uint32_t size; uint32_t label; boolean_t ok; #if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER) boolean_t sop; boolean_t jumbo_cont; #endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */ uint32_t hdr_type; boolean_t is_v6; uint16_t flags; boolean_t ignore; boolean_t should_abort; EFX_EV_QSTAT_INCR(eep, EV_RX); /* Basic packet information */ id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR); size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT); label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL); ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0); #if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER) sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0); jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0); #endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */ hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE); is_v6 = (enp->en_family != EFX_FAMILY_FALCON && EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0); /* * If packet is marked as OK and packet type is TCP/IP or * UDP/IP or other IP, then we can rely on the hardware checksums. */ switch (hdr_type) { case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP: flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP; if (is_v6) { EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6); flags |= EFX_PKT_IPV6; } else { EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4); flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4; } break; case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP: flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP; if (is_v6) { EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6); flags |= EFX_PKT_IPV6; } else { EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4); flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4; } break; case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER: if (is_v6) { EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6); flags = EFX_PKT_IPV6; } else { EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4); flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4; } break; case FSE_AZ_RX_EV_HDR_TYPE_OTHER: EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP); flags = 0; break; default: EFSYS_ASSERT(B_FALSE); flags = 0; break; } #if EFSYS_OPT_RX_SCATTER || EFSYS_OPT_RX_HDR_SPLIT /* Report scatter and header/lookahead split buffer flags */ if (sop) flags |= EFX_PKT_START; if (jumbo_cont) flags |= EFX_PKT_CONT; #endif /* EFSYS_OPT_RX_SCATTER || EFSYS_OPT_RX_HDR_SPLIT */ /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */ if (!ok) { - ignore = efx_ev_rx_not_ok(eep, eqp, label, id, &flags); + ignore = falconsiena_ev_rx_not_ok(eep, eqp, label, id, &flags); if (ignore) { EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id, uint32_t, size, uint16_t, flags); return (B_FALSE); } } /* If we're not discarding the packet then it is ok */ if (~flags & EFX_DISCARD) EFX_EV_QSTAT_INCR(eep, EV_RX_OK); /* Detect multicast packets that didn't match the filter */ if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) { EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT); if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) { EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH); } else { EFSYS_PROBE(mcast_mismatch); flags |= EFX_ADDR_MISMATCH; } } else { flags |= EFX_PKT_UNICAST; } /* * The packet parser in Siena can abort parsing packets under * certain error conditions, setting the PKT_NOT_PARSED bit * (which clears PKT_OK). If this is set, then don't trust * the PKT_TYPE field. */ if (enp->en_family != EFX_FAMILY_FALCON && !ok) { uint32_t parse_err; parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED); if (parse_err != 0) flags |= EFX_CHECK_VLAN; } if (~flags & EFX_CHECK_VLAN) { uint32_t pkt_type; pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE); if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN) flags |= EFX_PKT_VLAN_TAGGED; } EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id, uint32_t, size, uint16_t, flags); EFSYS_ASSERT(eecp->eec_rx != NULL); should_abort = eecp->eec_rx(arg, label, id, size, flags); return (should_abort); } static __checkReturn boolean_t -efx_ev_tx( +falconsiena_ev_tx( __in efx_evq_t *eep, __in efx_qword_t *eqp, __in const efx_ev_callbacks_t *eecp, __in_opt void *arg) { uint32_t id; uint32_t label; boolean_t should_abort; EFX_EV_QSTAT_INCR(eep, EV_TX); if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 && EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 && EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 && EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) { id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR); label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL); EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id); EFSYS_ASSERT(eecp->eec_tx != NULL); should_abort = eecp->eec_tx(arg, label, id); return (should_abort); } if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0) EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index, uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1), uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0)); if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0) EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR); if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0) EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG); if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0) EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL); EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED); return (B_FALSE); } static __checkReturn boolean_t -efx_ev_global( +falconsiena_ev_global( __in efx_evq_t *eep, __in efx_qword_t *eqp, __in const efx_ev_callbacks_t *eecp, __in_opt void *arg) { efx_nic_t *enp = eep->ee_enp; efx_port_t *epp = &(enp->en_port); boolean_t should_abort; EFX_EV_QSTAT_INCR(eep, EV_GLOBAL); should_abort = B_FALSE; /* Check for a link management event */ if (EFX_QWORD_FIELD(*eqp, FSF_BZ_GLB_EV_XG_MNT_INTR) != 0) { EFX_EV_QSTAT_INCR(eep, EV_GLOBAL_MNT); EFSYS_PROBE(xg_mgt); epp->ep_mac_poll_needed = B_TRUE; } return (should_abort); } static __checkReturn boolean_t -efx_ev_driver( +falconsiena_ev_driver( __in efx_evq_t *eep, __in efx_qword_t *eqp, __in const efx_ev_callbacks_t *eecp, __in_opt void *arg) { boolean_t should_abort; EFX_EV_QSTAT_INCR(eep, EV_DRIVER); should_abort = B_FALSE; switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) { case FSE_AZ_TX_DESCQ_FLS_DONE_EV: { uint32_t txq_index; EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE); txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index); EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL); should_abort = eecp->eec_txq_flush_done(arg, txq_index); break; } case FSE_AZ_RX_DESCQ_FLS_DONE_EV: { uint32_t rxq_index; uint32_t failed; rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID); failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL); EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL); EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL); if (failed) { EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED); EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index); - should_abort = eecp->eec_rxq_flush_failed(arg, rxq_index); + should_abort = eecp->eec_rxq_flush_failed(arg, + rxq_index); } else { EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE); EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index); should_abort = eecp->eec_rxq_flush_done(arg, rxq_index); } break; } case FSE_AZ_EVQ_INIT_DONE_EV: EFSYS_ASSERT(eecp->eec_initialized != NULL); should_abort = eecp->eec_initialized(arg); break; case FSE_AZ_EVQ_NOT_EN_EV: EFSYS_PROBE(evq_not_en); break; case FSE_AZ_SRM_UPD_DONE_EV: { uint32_t code; EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE); code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); EFSYS_ASSERT(eecp->eec_sram != NULL); should_abort = eecp->eec_sram(arg, code); break; } case FSE_AZ_WAKE_UP_EV: { uint32_t id; id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); EFSYS_ASSERT(eecp->eec_wake_up != NULL); should_abort = eecp->eec_wake_up(arg, id); break; } case FSE_AZ_TX_PKT_NON_TCP_UDP: EFSYS_PROBE(tx_pkt_non_tcp_udp); break; case FSE_AZ_TIMER_EV: { uint32_t id; id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); EFSYS_ASSERT(eecp->eec_timer != NULL); should_abort = eecp->eec_timer(arg, id); break; } case FSE_AZ_RX_DSC_ERROR_EV: EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR); EFSYS_PROBE(rx_dsc_error); EFSYS_ASSERT(eecp->eec_exception != NULL); should_abort = eecp->eec_exception(arg, EFX_EXCEPTION_RX_DSC_ERROR, 0); break; case FSE_AZ_TX_DSC_ERROR_EV: EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR); EFSYS_PROBE(tx_dsc_error); EFSYS_ASSERT(eecp->eec_exception != NULL); should_abort = eecp->eec_exception(arg, EFX_EXCEPTION_TX_DSC_ERROR, 0); break; default: break; } return (should_abort); } static __checkReturn boolean_t -efx_ev_drv_gen( +falconsiena_ev_drv_gen( __in efx_evq_t *eep, __in efx_qword_t *eqp, __in const efx_ev_callbacks_t *eecp, __in_opt void *arg) { uint32_t data; boolean_t should_abort; EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN); data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0); if (data >= ((uint32_t)1 << 16)) { EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index, uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1), uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0)); return (B_TRUE); } EFSYS_ASSERT(eecp->eec_software != NULL); should_abort = eecp->eec_software(arg, (uint16_t)data); return (should_abort); } #if EFSYS_OPT_MCDI static __checkReturn boolean_t -efx_ev_mcdi( +falconsiena_ev_mcdi( __in efx_evq_t *eep, __in efx_qword_t *eqp, __in const efx_ev_callbacks_t *eecp, __in_opt void *arg) { efx_nic_t *enp = eep->ee_enp; unsigned code; boolean_t should_abort = B_FALSE; EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); if (enp->en_family != EFX_FAMILY_SIENA) goto out; EFSYS_ASSERT(eecp->eec_link_change != NULL); EFSYS_ASSERT(eecp->eec_exception != NULL); #if EFSYS_OPT_MON_STATS EFSYS_ASSERT(eecp->eec_monitor != NULL); #endif EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE); code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE); switch (code) { case MCDI_EVENT_CODE_BADSSERT: efx_mcdi_ev_death(enp, EINTR); break; case MCDI_EVENT_CODE_CMDDONE: efx_mcdi_ev_cpl(enp, - MCDI_EV_FIELD(eqp, CMDDONE_SEQ), - MCDI_EV_FIELD(eqp, CMDDONE_DATALEN), - MCDI_EV_FIELD(eqp, CMDDONE_ERRNO)); + MCDI_EV_FIELD(eqp, CMDDONE_SEQ), + MCDI_EV_FIELD(eqp, CMDDONE_DATALEN), + MCDI_EV_FIELD(eqp, CMDDONE_ERRNO)); break; case MCDI_EVENT_CODE_LINKCHANGE: { efx_link_mode_t link_mode; siena_phy_link_ev(enp, eqp, &link_mode); should_abort = eecp->eec_link_change(arg, link_mode); break; } case MCDI_EVENT_CODE_SENSOREVT: { #if EFSYS_OPT_MON_STATS efx_mon_stat_t id; efx_mon_stat_value_t value; int rc; - if ((rc = siena_mon_ev(enp, eqp, &id, &value)) == 0) + if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) should_abort = eecp->eec_monitor(arg, id, value); else if (rc == ENOTSUP) { should_abort = eecp->eec_exception(arg, EFX_EXCEPTION_UNKNOWN_SENSOREVT, MCDI_EV_FIELD(eqp, DATA)); } else EFSYS_ASSERT(rc == ENODEV); /* Wrong port */ #else should_abort = B_FALSE; #endif break; } case MCDI_EVENT_CODE_SCHEDERR: /* Informational only */ break; case MCDI_EVENT_CODE_REBOOT: efx_mcdi_ev_death(enp, EIO); break; case MCDI_EVENT_CODE_MAC_STATS_DMA: #if EFSYS_OPT_MAC_STATS if (eecp->eec_mac_stats != NULL) { eecp->eec_mac_stats(arg, MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION)); } #endif break; case MCDI_EVENT_CODE_FWALERT: { uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON); if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS) should_abort = eecp->eec_exception(arg, EFX_EXCEPTION_FWALERT_SRAM, MCDI_EV_FIELD(eqp, FWALERT_DATA)); else should_abort = eecp->eec_exception(arg, EFX_EXCEPTION_UNKNOWN_FWALERT, MCDI_EV_FIELD(eqp, DATA)); break; } default: EFSYS_PROBE1(mc_pcol_error, int, code); break; } out: return (should_abort); } #endif /* EFSYS_OPT_MCDI */ - __checkReturn int -efx_ev_qprime( +static __checkReturn int +falconsiena_ev_qprime( __in efx_evq_t *eep, __in unsigned int count) { efx_nic_t *enp = eep->ee_enp; uint32_t rptr; efx_dword_t dword; - int rc; - EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); - - if (!(enp->en_mod_flags & EFX_MOD_INTR)) { - rc = EINVAL; - goto fail1; - } - rptr = count & eep->ee_mask; EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr); EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index, &dword, B_FALSE); return (0); - -fail1: - EFSYS_PROBE1(fail1, int, rc); - - return (rc); } - __checkReturn boolean_t -efx_ev_qpending( - __in efx_evq_t *eep, - __in unsigned int count) -{ - size_t offset; - efx_qword_t qword; - - EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); - - offset = (count & eep->ee_mask) * sizeof (efx_qword_t); - EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword); - - return (EFX_QWORD_FIELD(qword, EFX_DWORD_0) != 0xffffffff && - EFX_QWORD_FIELD(qword, EFX_DWORD_1) != 0xffffffff); -} - -#if EFSYS_OPT_EV_PREFETCH - - void -efx_ev_qprefetch( - __in efx_evq_t *eep, - __in unsigned int count) -{ - unsigned int offset; - - EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); - - offset = (count & eep->ee_mask) * sizeof (efx_qword_t); - EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); -} - -#endif /* EFSYS_OPT_EV_PREFETCH */ - #define EFX_EV_BATCH 8 -#define EFX_EV_PRESENT(_qword) \ - (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \ - EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff) - - void -efx_ev_qpoll( +static void +falconsiena_ev_qpoll( __in efx_evq_t *eep, __inout unsigned int *countp, __in const efx_ev_callbacks_t *eecp, __in_opt void *arg) { efx_qword_t ev[EFX_EV_BATCH]; unsigned int batch; unsigned int total; unsigned int count; unsigned int index; size_t offset; - EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); EFSYS_ASSERT(countp != NULL); EFSYS_ASSERT(eecp != NULL); count = *countp; do { /* Read up until the end of the batch period */ batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1)); offset = (count & eep->ee_mask) * sizeof (efx_qword_t); for (total = 0; total < batch; ++total) { EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total])); if (!EFX_EV_PRESENT(ev[total])) break; EFSYS_PROBE3(event, unsigned int, eep->ee_index, uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1), uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0)); offset += sizeof (efx_qword_t); } #if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1) /* * Prefetch the next batch when we get within PREFETCH_PERIOD * of a completed batch. If the batch is smaller, then prefetch * immediately. */ if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD) EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); #endif /* EFSYS_OPT_EV_PREFETCH */ /* Process the batch of events */ for (index = 0; index < total; ++index) { boolean_t should_abort; uint32_t code; - efx_ev_handler_t handler; #if EFSYS_OPT_EV_PREFETCH /* Prefetch if we've now reached the batch period */ if (total == batch && index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) { offset = (count + batch) & eep->ee_mask; offset *= sizeof (efx_qword_t); EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); } #endif /* EFSYS_OPT_EV_PREFETCH */ EFX_EV_QSTAT_INCR(eep, EV_ALL); code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE); - handler = eep->ee_handler[code]; - EFSYS_ASSERT(handler != NULL); - should_abort = handler(eep, &(ev[index]), eecp, arg); + switch (code) { + case FSE_AZ_EV_CODE_RX_EV: + should_abort = eep->ee_rx(eep, + &(ev[index]), eecp, arg); + break; + case FSE_AZ_EV_CODE_TX_EV: + should_abort = eep->ee_tx(eep, + &(ev[index]), eecp, arg); + break; + case FSE_AZ_EV_CODE_DRIVER_EV: + should_abort = eep->ee_driver(eep, + &(ev[index]), eecp, arg); + break; + case FSE_AZ_EV_CODE_DRV_GEN_EV: + should_abort = eep->ee_drv_gen(eep, + &(ev[index]), eecp, arg); + break; +#if EFSYS_OPT_MCDI + case FSE_AZ_EV_CODE_MCDI_EVRESPONSE: + should_abort = eep->ee_mcdi(eep, + &(ev[index]), eecp, arg); + break; +#endif + case FSE_AZ_EV_CODE_GLOBAL_EV: + if (eep->ee_global) { + should_abort = eep->ee_global(eep, + &(ev[index]), eecp, arg); + break; + } + /* else fallthrough */ + default: + EFSYS_PROBE3(bad_event, + unsigned int, eep->ee_index, + uint32_t, + EFX_QWORD_FIELD(ev[index], EFX_DWORD_1), + uint32_t, + EFX_QWORD_FIELD(ev[index], EFX_DWORD_0)); + + EFSYS_ASSERT(eecp->eec_exception != NULL); + (void) eecp->eec_exception(arg, + EFX_EXCEPTION_EV_ERROR, code); + should_abort = B_TRUE; + } if (should_abort) { /* Ignore subsequent events */ total = index + 1; break; } } /* * Now that the hardware has most likely moved onto dma'ing * into the next cache line, clear the processed events. Take * care to only clear out events that we've processed */ EFX_SET_QWORD(ev[0]); offset = (count & eep->ee_mask) * sizeof (efx_qword_t); for (index = 0; index < total; ++index) { EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0])); offset += sizeof (efx_qword_t); } count += total; } while (total == batch); *countp = count; } - void -efx_ev_qpost( +static void +falconsiena_ev_qpost( __in efx_evq_t *eep, __in uint16_t data) { efx_nic_t *enp = eep->ee_enp; efx_qword_t ev; efx_oword_t oword; - EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); - EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV, FSF_AZ_EV_DATA_DW0, (uint32_t)data); EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index, EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0), EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1)); EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword); } - __checkReturn int -efx_ev_qmoderate( +static __checkReturn int +falconsiena_ev_qmoderate( __in efx_evq_t *eep, __in unsigned int us) { efx_nic_t *enp = eep->ee_enp; efx_nic_cfg_t *encp = &(enp->en_nic_cfg); unsigned int locked; efx_dword_t dword; int rc; - EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); - if (us > encp->enc_evq_timer_max_us) { rc = EINVAL; goto fail1; } /* If the value is zero then disable the timer */ if (us == 0) { if (enp->en_family == EFX_FAMILY_FALCON) EFX_POPULATE_DWORD_2(dword, FRF_AB_TC_TIMER_MODE, FFE_AB_TIMER_MODE_DIS, FRF_AB_TC_TIMER_VAL, 0); else EFX_POPULATE_DWORD_2(dword, FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS, FRF_CZ_TC_TIMER_VAL, 0); } else { uint32_t timer_val; /* Calculate the timer value in quanta */ timer_val = us * 1000 / encp->enc_evq_timer_quantum_ns; /* Moderation value is base 0 so we need to deduct 1 */ if (timer_val > 0) timer_val--; if (enp->en_family == EFX_FAMILY_FALCON) EFX_POPULATE_DWORD_2(dword, FRF_AB_TC_TIMER_MODE, FFE_AB_TIMER_MODE_INT_HLDOFF, FRF_AB_TIMER_VAL, timer_val); else EFX_POPULATE_DWORD_2(dword, FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF, FRF_CZ_TC_TIMER_VAL, timer_val); } locked = (eep->ee_index == 0) ? 1 : 0; EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0, eep->ee_index, &dword, locked); return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } - __checkReturn int -efx_ev_qcreate( +static __checkReturn int +falconsiena_ev_qcreate( __in efx_nic_t *enp, __in unsigned int index, __in efsys_mem_t *esmp, __in size_t n, __in uint32_t id, - __deref_out efx_evq_t **eepp) + __in efx_evq_t *eep) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); uint32_t size; - efx_evq_t *eep; efx_oword_t oword; int rc; - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV); + EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS)); + EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS)); - EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit); - - if (!ISP2(n) || !(n & EFX_EVQ_NEVS_MASK)) { + if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) { rc = EINVAL; goto fail1; } if (index >= encp->enc_evq_limit) { rc = EINVAL; goto fail2; } #if EFSYS_OPT_RX_SCALE if (enp->en_intr.ei_type == EFX_INTR_LINE && index >= EFX_MAXRSS_LEGACY) { rc = EINVAL; goto fail3; } #endif for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS); size++) if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS)) break; if (id + (1 << size) >= encp->enc_buftbl_limit) { rc = EINVAL; goto fail4; } - /* Allocate an EVQ object */ - EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep); - if (eep == NULL) { - rc = ENOMEM; - goto fail5; - } - - eep->ee_magic = EFX_EVQ_MAGIC; - eep->ee_enp = enp; - eep->ee_index = index; - eep->ee_mask = n - 1; - eep->ee_esmp = esmp; - /* Set up the handler table */ - eep->ee_handler[FSE_AZ_EV_CODE_RX_EV] = efx_ev_rx; - eep->ee_handler[FSE_AZ_EV_CODE_TX_EV] = efx_ev_tx; - eep->ee_handler[FSE_AZ_EV_CODE_DRIVER_EV] = efx_ev_driver; - eep->ee_handler[FSE_AZ_EV_CODE_GLOBAL_EV] = efx_ev_global; - eep->ee_handler[FSE_AZ_EV_CODE_DRV_GEN_EV] = efx_ev_drv_gen; + eep->ee_rx = falconsiena_ev_rx; + eep->ee_tx = falconsiena_ev_tx; + eep->ee_driver = falconsiena_ev_driver; + eep->ee_global = falconsiena_ev_global; + eep->ee_drv_gen = falconsiena_ev_drv_gen; #if EFSYS_OPT_MCDI - eep->ee_handler[FSE_AZ_EV_CODE_MCDI_EVRESPONSE] = efx_ev_mcdi; + eep->ee_mcdi = falconsiena_ev_mcdi; #endif /* EFSYS_OPT_MCDI */ /* Set up the new event queue */ if (enp->en_family != EFX_FAMILY_FALCON) { EFX_POPULATE_OWORD_1(oword, FRF_CZ_TIMER_Q_EN, 1); - EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword); + EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE); } EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size, FRF_AZ_EVQ_BUF_BASE_ID, id); - EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword); + EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE); - enp->en_ev_qcount++; - *eepp = eep; return (0); -fail5: - EFSYS_PROBE(fail5); fail4: EFSYS_PROBE(fail4); #if EFSYS_OPT_RX_SCALE fail3: EFSYS_PROBE(fail3); #endif fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } +#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ + #if EFSYS_OPT_QSTATS #if EFSYS_OPT_NAMES -/* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock 67e9bdcd920059bd */ -static const char __cs * __cs __efx_ev_qstat_name[] = { +/* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock b693ddf85aee1bfd */ +static const char *__efx_ev_qstat_name[] = { "all", "rx", "rx_ok", - "rx_recovery", "rx_frm_trunc", "rx_tobe_disc", "rx_pause_frm_err", "rx_buf_owner_id_err", "rx_ipv4_hdr_chksum_err", "rx_tcp_udp_chksum_err", "rx_eth_crc_err", "rx_ip_frag_err", "rx_mcast_pkt", "rx_mcast_hash_match", "rx_tcp_ipv4", "rx_tcp_ipv6", "rx_udp_ipv4", "rx_udp_ipv6", "rx_other_ipv4", "rx_other_ipv6", "rx_non_ip", - "rx_overrun", + "rx_batch", "tx", "tx_wq_ff_full", "tx_pkt_err", "tx_pkt_too_big", "tx_unexpected", "global", - "global_phy", "global_mnt", - "global_rx_recovery", "driver", "driver_srm_upd_done", "driver_tx_descq_fls_done", "driver_rx_descq_fls_done", "driver_rx_descq_fls_failed", "driver_rx_dsc_error", "driver_tx_dsc_error", "drv_gen", "mcdi_response", }; /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */ - const char __cs * + const char * efx_ev_qstat_name( __in efx_nic_t *enp, __in unsigned int id) { EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(id, <, EV_NQSTATS); return (__efx_ev_qstat_name[id]); } #endif /* EFSYS_OPT_NAMES */ #endif /* EFSYS_OPT_QSTATS */ +#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA + #if EFSYS_OPT_QSTATS - void -efx_ev_qstats_update( +static void +falconsiena_ev_qstats_update( __in efx_evq_t *eep, __inout_ecount(EV_NQSTATS) efsys_stat_t *stat) { unsigned int id; - EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); - for (id = 0; id < EV_NQSTATS; id++) { efsys_stat_t *essp = &stat[id]; EFSYS_STAT_INCR(essp, eep->ee_stat[id]); eep->ee_stat[id] = 0; } } #endif /* EFSYS_OPT_QSTATS */ - void -efx_ev_qdestroy( +static void +falconsiena_ev_qdestroy( __in efx_evq_t *eep) { efx_nic_t *enp = eep->ee_enp; efx_oword_t oword; - EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); - - EFSYS_ASSERT(enp->en_ev_qcount != 0); - --enp->en_ev_qcount; - /* Purge event queue */ EFX_ZERO_OWORD(oword); EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, - eep->ee_index, &oword); + eep->ee_index, &oword, B_TRUE); if (enp->en_family != EFX_FAMILY_FALCON) { EFX_ZERO_OWORD(oword); EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, - eep->ee_index, &oword); + eep->ee_index, &oword, B_TRUE); } - - /* Free the EVQ object */ - EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep); } - void -efx_ev_fini( +static void +falconsiena_ev_fini( __in efx_nic_t *enp) { - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV); - EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX)); - EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX)); - EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0); - - enp->en_mod_flags &= ~EFX_MOD_EV; + _NOTE(ARGUNUSED(enp)) } + +#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ Property changes on: head/sys/dev/sfxge/common/efx_ev.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_filter.c =================================================================== --- head/sys/dev/sfxge/common/efx_filter.c (revision 283513) +++ head/sys/dev/sfxge/common/efx_filter.c (revision 283514) @@ -1,1029 +1,1439 @@ /*- - * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2007-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include "efsys.h" #include "efx.h" #include "efx_types.h" #include "efx_regs.h" #include "efx_impl.h" #if EFSYS_OPT_FILTER -/* "Fudge factors" - difference between programmed value and actual depth. +#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA + +static __checkReturn int +falconsiena_filter_init( + __in efx_nic_t *enp); + +static void +falconsiena_filter_fini( + __in efx_nic_t *enp); + +static __checkReturn int +falconsiena_filter_restore( + __in efx_nic_t *enp); + +static __checkReturn int +falconsiena_filter_add( + __in efx_nic_t *enp, + __inout efx_filter_spec_t *spec, + __in boolean_t may_replace); + +static __checkReturn int +falconsiena_filter_delete( + __in efx_nic_t *enp, + __inout efx_filter_spec_t *spec); + +static __checkReturn int +falconsiena_filter_supported_filters( + __in efx_nic_t *enp, + __out uint32_t *list, + __out size_t *length); + +#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ + +#if EFSYS_OPT_FALCON +static efx_filter_ops_t __efx_filter_falcon_ops = { + falconsiena_filter_init, /* efo_init */ + falconsiena_filter_fini, /* efo_fini */ + falconsiena_filter_restore, /* efo_restore */ + falconsiena_filter_add, /* efo_add */ + falconsiena_filter_delete, /* efo_delete */ + falconsiena_filter_supported_filters, /* efo_supported_filters */ + NULL, /* efo_reconfigure */ +}; +#endif /* EFSYS_OPT_FALCON */ + +#if EFSYS_OPT_SIENA +static efx_filter_ops_t __efx_filter_siena_ops = { + falconsiena_filter_init, /* efo_init */ + falconsiena_filter_fini, /* efo_fini */ + falconsiena_filter_restore, /* efo_restore */ + falconsiena_filter_add, /* efo_add */ + falconsiena_filter_delete, /* efo_delete */ + falconsiena_filter_supported_filters, /* efo_supported_filters */ + NULL, /* efo_reconfigure */ +}; +#endif /* EFSYS_OPT_SIENA */ + +#if EFSYS_OPT_HUNTINGTON +static efx_filter_ops_t __efx_filter_hunt_ops = { + hunt_filter_init, /* efo_init */ + hunt_filter_fini, /* efo_fini */ + hunt_filter_restore, /* efo_restore */ + hunt_filter_add, /* efo_add */ + hunt_filter_delete, /* efo_delete */ + hunt_filter_supported_filters, /* efo_supported_filters */ + hunt_filter_reconfigure, /* efo_reconfigure */ +}; +#endif /* EFSYS_OPT_HUNTINGTON */ + + __checkReturn int +efx_filter_insert( + __in efx_nic_t *enp, + __inout efx_filter_spec_t *spec) +{ + efx_filter_ops_t *efop = enp->en_efop; + + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER); + EFSYS_ASSERT3P(spec, !=, NULL); + EFSYS_ASSERT3U(spec->efs_flags, &, EFX_FILTER_FLAG_RX); + + return (efop->efo_add(enp, spec, B_FALSE)); +} + + __checkReturn int +efx_filter_remove( + __in efx_nic_t *enp, + __inout efx_filter_spec_t *spec) +{ + efx_filter_ops_t *efop = enp->en_efop; + + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER); + EFSYS_ASSERT3P(spec, !=, NULL); + EFSYS_ASSERT3U(spec->efs_flags, &, EFX_FILTER_FLAG_RX); + +#if EFSYS_OPT_RX_SCALE + spec->efs_rss_context = enp->en_rss_context; +#endif + + return (efop->efo_delete(enp, spec)); +} + + __checkReturn int +efx_filter_restore( + __in efx_nic_t *enp) +{ + int rc; + + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER); + + if ((rc = enp->en_efop->efo_restore(enp)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +efx_filter_init( + __in efx_nic_t *enp) +{ + efx_filter_ops_t *efop; + int rc; + + /* Check that efx_filter_spec_t is 64 bytes. */ + EFX_STATIC_ASSERT(sizeof (efx_filter_spec_t) == 64); + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); + EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_FILTER)); + + switch (enp->en_family) { +#if EFSYS_OPT_FALCON + case EFX_FAMILY_FALCON: + efop = (efx_filter_ops_t *)&__efx_filter_falcon_ops; + break; +#endif /* EFSYS_OPT_FALCON */ + +#if EFSYS_OPT_SIENA + case EFX_FAMILY_SIENA: + efop = (efx_filter_ops_t *)&__efx_filter_siena_ops; + break; +#endif /* EFSYS_OPT_SIENA */ + +#if EFSYS_OPT_HUNTINGTON + case EFX_FAMILY_HUNTINGTON: + efop = (efx_filter_ops_t *)&__efx_filter_hunt_ops; + break; +#endif /* EFSYS_OPT_HUNTINGTON */ + + default: + EFSYS_ASSERT(0); + rc = ENOTSUP; + goto fail1; + } + + if ((rc = efop->efo_init(enp)) != 0) + goto fail2; + + enp->en_efop = efop; + enp->en_mod_flags |= EFX_MOD_FILTER; + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + enp->en_efop = NULL; + enp->en_mod_flags &= ~EFX_MOD_FILTER; + return (rc); +} + + void +efx_filter_fini( + __in efx_nic_t *enp) +{ + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER); + + enp->en_efop->efo_fini(enp); + + enp->en_efop = NULL; + enp->en_mod_flags &= ~EFX_MOD_FILTER; +} + + __checkReturn int +efx_filter_supported_filters( + __in efx_nic_t *enp, + __out uint32_t *list, + __out size_t *length) +{ + int rc; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER); + EFSYS_ASSERT(enp->en_efop->efo_supported_filters != NULL); + + if ((rc = enp->en_efop->efo_supported_filters(enp, list, length)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +efx_filter_reconfigure( + __in efx_nic_t *enp, + __in_ecount(6) uint8_t const *mac_addr, + __in boolean_t all_unicst, + __in boolean_t mulcst, + __in boolean_t all_mulcst, + __in boolean_t brdcst, + __in_ecount(6*count) uint8_t const *addrs, + __in int count) +{ + int rc; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER); + + if (enp->en_efop->efo_reconfigure != NULL) { + if ((rc = enp->en_efop->efo_reconfigure(enp, mac_addr, + all_unicst, mulcst, + all_mulcst, brdcst, + addrs, count)) != 0) + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + void +efx_filter_spec_init_rx( + __inout efx_filter_spec_t *spec, + __in efx_filter_priority_t priority, + __in efx_filter_flag_t flags, + __in efx_rxq_t *erp) +{ + EFSYS_ASSERT3P(spec, !=, NULL); + EFSYS_ASSERT3P(erp, !=, NULL); + EFSYS_ASSERT((flags & ~(EFX_FILTER_FLAG_RX_RSS | + EFX_FILTER_FLAG_RX_SCATTER)) == 0); + + memset(spec, 0, sizeof (*spec)); + spec->efs_priority = priority; + spec->efs_flags = EFX_FILTER_FLAG_RX | flags; + spec->efs_rss_context = EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT; + spec->efs_dmaq_id = (uint16_t)erp->er_index; +} + + void +efx_filter_spec_init_tx( + __inout efx_filter_spec_t *spec, + __in efx_txq_t *etp) +{ + EFSYS_ASSERT3P(spec, !=, NULL); + EFSYS_ASSERT3P(etp, !=, NULL); + + memset(spec, 0, sizeof (*spec)); + spec->efs_priority = EFX_FILTER_PRI_REQUIRED; + spec->efs_flags = EFX_FILTER_FLAG_TX; + spec->efs_dmaq_id = (uint16_t)etp->et_index; +} + + +/* + * Specify IPv4 host, transport protocol and port in a filter specification + */ +__checkReturn int +efx_filter_spec_set_ipv4_local( + __inout efx_filter_spec_t *spec, + __in uint8_t proto, + __in uint32_t host, + __in uint16_t port) +{ + EFSYS_ASSERT3P(spec, !=, NULL); + + spec->efs_match_flags |= + EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO | + EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT; + spec->efs_ether_type = EFX_ETHER_TYPE_IPV4; + spec->efs_ip_proto = proto; + spec->efs_loc_host.eo_u32[0] = host; + spec->efs_loc_port = port; + return (0); +} + +/* + * Specify IPv4 hosts, transport protocol and ports in a filter specification + */ +__checkReturn int +efx_filter_spec_set_ipv4_full( + __inout efx_filter_spec_t *spec, + __in uint8_t proto, + __in uint32_t lhost, + __in uint16_t lport, + __in uint32_t rhost, + __in uint16_t rport) +{ + EFSYS_ASSERT3P(spec, !=, NULL); + + spec->efs_match_flags |= + EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO | + EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT | + EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT; + spec->efs_ether_type = EFX_ETHER_TYPE_IPV4; + spec->efs_ip_proto = proto; + spec->efs_loc_host.eo_u32[0] = lhost; + spec->efs_loc_port = lport; + spec->efs_rem_host.eo_u32[0] = rhost; + spec->efs_rem_port = rport; + return (0); +} + +/* + * Specify local Ethernet address and/or VID in filter specification + */ +__checkReturn int +efx_filter_spec_set_eth_local( + __inout efx_filter_spec_t *spec, + __in uint16_t vid, + __in const uint8_t *addr) +{ + EFSYS_ASSERT3P(spec, !=, NULL); + EFSYS_ASSERT3P(addr, !=, NULL); + + if (vid == EFX_FILTER_SPEC_VID_UNSPEC && addr == NULL) + return (EINVAL); + + if (vid != EFX_FILTER_SPEC_VID_UNSPEC) { + spec->efs_match_flags |= EFX_FILTER_MATCH_OUTER_VID; + spec->efs_outer_vid = vid; + } + if (addr != NULL) { + spec->efs_match_flags |= EFX_FILTER_MATCH_LOC_MAC; + memcpy(spec->efs_loc_mac, addr, EFX_MAC_ADDR_LEN); + } + return (0); +} + +/* + * Specify matching otherwise-unmatched unicast in a filter specification + */ +__checkReturn int +efx_filter_spec_set_uc_def( + __inout efx_filter_spec_t *spec) +{ + EFSYS_ASSERT3P(spec, !=, NULL); + + spec->efs_match_flags |= EFX_FILTER_MATCH_LOC_MAC_IG; + return (0); +} + +/* + * Specify matching otherwise-unmatched multicast in a filter specification + */ +__checkReturn int +efx_filter_spec_set_mc_def( + __inout efx_filter_spec_t *spec) +{ + EFSYS_ASSERT3P(spec, !=, NULL); + + spec->efs_match_flags |= EFX_FILTER_MATCH_LOC_MAC_IG; + spec->efs_loc_mac[0] = 1; + return (0); +} + + + +#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA + +/* + * "Fudge factors" - difference between programmed value and actual depth. * Due to pipelined implementation we need to program H/W with a value that * is larger than the hop limit we want. */ -#define FILTER_CTL_SRCH_FUDGE_WILD 3 -#define FILTER_CTL_SRCH_FUDGE_FULL 1 +#define FILTER_CTL_SRCH_FUDGE_WILD 3 +#define FILTER_CTL_SRCH_FUDGE_FULL 1 -/* Hard maximum hop limit. Hardware will time-out beyond 200-something. +/* + * Hard maximum hop limit. Hardware will time-out beyond 200-something. * We also need to avoid infinite loops in efx_filter_search() when the * table is full. */ -#define FILTER_CTL_SRCH_MAX 200 +#define FILTER_CTL_SRCH_MAX 200 -/* The filter hash function is LFSR polynomial x^16 + x^3 + 1 of a 32-bit - * key derived from the n-tuple. */ +static __checkReturn int +falconsiena_filter_spec_from_gen_spec( + __out falconsiena_filter_spec_t *fs_spec, + __in efx_filter_spec_t *gen_spec) +{ + int rc; + boolean_t is_full = B_FALSE; + + if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) + EFSYS_ASSERT3U(gen_spec->efs_flags, ==, EFX_FILTER_FLAG_TX); + else + EFSYS_ASSERT3U(gen_spec->efs_flags, &, EFX_FILTER_FLAG_RX); + + /* Falconsiena only has one RSS context */ + if ((gen_spec->efs_flags & EFX_FILTER_FLAG_RX_RSS) && + gen_spec->efs_rss_context != 0) { + rc = EINVAL; + goto fail1; + } + + fs_spec->fsfs_flags = gen_spec->efs_flags; + fs_spec->fsfs_dmaq_id = gen_spec->efs_dmaq_id; + + switch (gen_spec->efs_match_flags) { + case EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO | + EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT | + EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT: + is_full = B_TRUE; + /* Fall through */ + case EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO | + EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT: { + uint32_t rhost, host1, host2; + uint16_t rport, port1, port2; + + if (gen_spec->efs_ether_type != EFX_ETHER_TYPE_IPV4) { + rc = ENOTSUP; + goto fail2; + } + if (gen_spec->efs_loc_port == 0 || + (is_full && gen_spec->efs_rem_port == 0)) { + rc = EINVAL; + goto fail3; + } + switch (gen_spec->efs_ip_proto) { + case EFX_IPPROTO_TCP: + if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) { + fs_spec->fsfs_type = (is_full ? + EFX_FS_FILTER_TX_TCP_FULL : + EFX_FS_FILTER_TX_TCP_WILD); + } else { + fs_spec->fsfs_type = (is_full ? + EFX_FS_FILTER_RX_TCP_FULL : + EFX_FS_FILTER_RX_TCP_WILD); + } + break; + case EFX_IPPROTO_UDP: + if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) { + fs_spec->fsfs_type = (is_full ? + EFX_FS_FILTER_TX_UDP_FULL : + EFX_FS_FILTER_TX_UDP_WILD); + } else { + fs_spec->fsfs_type = (is_full ? + EFX_FS_FILTER_RX_UDP_FULL : + EFX_FS_FILTER_RX_UDP_WILD); + } + break; + default: + rc = ENOTSUP; + goto fail4; + } + /* + * The filter is constructed in terms of source and destination, + * with the odd wrinkle that the ports are swapped in a UDP + * wildcard filter. We need to convert from local and remote + * addresses (zero for a wildcard). + */ + rhost = is_full ? gen_spec->efs_rem_host.eo_u32[0] : 0; + rport = is_full ? gen_spec->efs_rem_port : 0; + if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) { + host1 = gen_spec->efs_loc_host.eo_u32[0]; + host2 = rhost; + } else { + host1 = rhost; + host2 = gen_spec->efs_loc_host.eo_u32[0]; + } + if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) { + if (fs_spec->fsfs_type == EFX_FS_FILTER_TX_UDP_WILD) { + port1 = rport; + port2 = gen_spec->efs_loc_port; + } else { + port1 = gen_spec->efs_loc_port; + port2 = rport; + } + } else { + if (fs_spec->fsfs_type == EFX_FS_FILTER_RX_UDP_WILD) { + port1 = gen_spec->efs_loc_port; + port2 = rport; + } else { + port1 = rport; + port2 = gen_spec->efs_loc_port; + } + } + fs_spec->fsfs_dword[0] = (host1 << 16) | port1; + fs_spec->fsfs_dword[1] = (port2 << 16) | (host1 >> 16); + fs_spec->fsfs_dword[2] = host2; + break; + } + + case EFX_FILTER_MATCH_LOC_MAC | EFX_FILTER_MATCH_OUTER_VID: + is_full = B_TRUE; + /* Fall through */ + case EFX_FILTER_MATCH_LOC_MAC: + if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) { + fs_spec->fsfs_type = (is_full ? + EFX_FS_FILTER_TX_MAC_FULL : + EFX_FS_FILTER_TX_MAC_WILD); + } else { + fs_spec->fsfs_type = (is_full ? + EFX_FS_FILTER_RX_MAC_FULL : + EFX_FS_FILTER_RX_MAC_WILD); + } + fs_spec->fsfs_dword[0] = is_full ? gen_spec->efs_outer_vid : 0; + fs_spec->fsfs_dword[1] = + gen_spec->efs_loc_mac[2] << 24 | + gen_spec->efs_loc_mac[3] << 16 | + gen_spec->efs_loc_mac[4] << 8 | + gen_spec->efs_loc_mac[5]; + fs_spec->fsfs_dword[2] = + gen_spec->efs_loc_mac[0] << 8 | + gen_spec->efs_loc_mac[1]; + break; + + default: + EFSYS_ASSERT(B_FALSE); + rc = ENOTSUP; + goto fail5; + } + + return (0); + +fail5: + EFSYS_PROBE(fail5); +fail4: + EFSYS_PROBE(fail4); +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +/* + * The filter hash function is LFSR polynomial x^16 + x^3 + 1 of a 32-bit + * key derived from the n-tuple. + */ static uint16_t -efx_filter_tbl_hash( - __in uint32_t key) +falconsiena_filter_tbl_hash( + __in uint32_t key) { uint16_t tmp; /* First 16 rounds */ tmp = 0x1fff ^ (uint16_t)(key >> 16); tmp = tmp ^ tmp >> 3 ^ tmp >> 6; tmp = tmp ^ tmp >> 9; /* Last 16 rounds */ tmp = tmp ^ tmp << 13 ^ (uint16_t)(key & 0xffff); tmp = tmp ^ tmp >> 3 ^ tmp >> 6; tmp = tmp ^ tmp >> 9; return (tmp); } - -/* To allow for hash collisions, filter search continues at these - * increments from the first possible entry selected by the hash. */ +/* + * To allow for hash collisions, filter search continues at these + * increments from the first possible entry selected by the hash. + */ static uint16_t -efx_filter_tbl_increment( +falconsiena_filter_tbl_increment( __in uint32_t key) { return ((uint16_t)(key * 2 - 1)); } static __checkReturn boolean_t -efx_filter_test_used( - __in efx_filter_tbl_t *eftp, +falconsiena_filter_test_used( + __in falconsiena_filter_tbl_t *fsftp, __in unsigned int index) { - EFSYS_ASSERT3P(eftp->eft_bitmap, !=, NULL); - return ((eftp->eft_bitmap[index / 32] & (1 << (index % 32))) != 0); + EFSYS_ASSERT3P(fsftp->fsft_bitmap, !=, NULL); + return ((fsftp->fsft_bitmap[index / 32] & (1 << (index % 32))) != 0); } static void -efx_filter_set_used( - __in efx_filter_tbl_t *eftp, +falconsiena_filter_set_used( + __in falconsiena_filter_tbl_t *fsftp, __in unsigned int index) { - EFSYS_ASSERT3P(eftp->eft_bitmap, !=, NULL); - eftp->eft_bitmap[index / 32] |= (1 << (index % 32)); - ++eftp->eft_used; + EFSYS_ASSERT3P(fsftp->fsft_bitmap, !=, NULL); + fsftp->fsft_bitmap[index / 32] |= (1 << (index % 32)); + ++fsftp->fsft_used; } static void -efx_filter_clear_used( - __in efx_filter_tbl_t *eftp, +falconsiena_filter_clear_used( + __in falconsiena_filter_tbl_t *fsftp, __in unsigned int index) { - EFSYS_ASSERT3P(eftp->eft_bitmap, !=, NULL); - eftp->eft_bitmap[index / 32] &= ~(1 << (index % 32)); + EFSYS_ASSERT3P(fsftp->fsft_bitmap, !=, NULL); + fsftp->fsft_bitmap[index / 32] &= ~(1 << (index % 32)); - --eftp->eft_used; - EFSYS_ASSERT3U(eftp->eft_used, >=, 0); + --fsftp->fsft_used; + EFSYS_ASSERT3U(fsftp->fsft_used, >=, 0); } -static efx_filter_tbl_id_t -efx_filter_tbl_id( - __in efx_filter_type_t type) +static falconsiena_filter_tbl_id_t +falconsiena_filter_tbl_id( + __in falconsiena_filter_type_t type) { - efx_filter_tbl_id_t tbl_id; + falconsiena_filter_tbl_id_t tbl_id; - switch (type) - { - case EFX_FILTER_RX_TCP_FULL: - case EFX_FILTER_RX_TCP_WILD: - case EFX_FILTER_RX_UDP_FULL: - case EFX_FILTER_RX_UDP_WILD: - tbl_id = EFX_FILTER_TBL_RX_IP; + switch (type) { + case EFX_FS_FILTER_RX_TCP_FULL: + case EFX_FS_FILTER_RX_TCP_WILD: + case EFX_FS_FILTER_RX_UDP_FULL: + case EFX_FS_FILTER_RX_UDP_WILD: + tbl_id = EFX_FS_FILTER_TBL_RX_IP; break; #if EFSYS_OPT_SIENA - case EFX_FILTER_RX_MAC_FULL: - case EFX_FILTER_RX_MAC_WILD: - tbl_id = EFX_FILTER_TBL_RX_MAC; + case EFX_FS_FILTER_RX_MAC_FULL: + case EFX_FS_FILTER_RX_MAC_WILD: + tbl_id = EFX_FS_FILTER_TBL_RX_MAC; break; - case EFX_FILTER_TX_TCP_FULL: - case EFX_FILTER_TX_TCP_WILD: - case EFX_FILTER_TX_UDP_FULL: - case EFX_FILTER_TX_UDP_WILD: - tbl_id = EFX_FILTER_TBL_TX_IP; + case EFX_FS_FILTER_TX_TCP_FULL: + case EFX_FS_FILTER_TX_TCP_WILD: + case EFX_FS_FILTER_TX_UDP_FULL: + case EFX_FS_FILTER_TX_UDP_WILD: + tbl_id = EFX_FS_FILTER_TBL_TX_IP; break; - case EFX_FILTER_TX_MAC_FULL: - case EFX_FILTER_TX_MAC_WILD: - tbl_id = EFX_FILTER_TBL_RX_MAC; + case EFX_FS_FILTER_TX_MAC_FULL: + case EFX_FS_FILTER_TX_MAC_WILD: + tbl_id = EFX_FS_FILTER_TBL_TX_MAC; break; #endif /* EFSYS_OPT_SIENA */ default: EFSYS_ASSERT(B_FALSE); + tbl_id = EFX_FS_FILTER_NTBLS; break; } return (tbl_id); } static void -efx_filter_reset_search_depth( - __inout efx_filter_t *efp, - __in efx_filter_tbl_id_t tbl_id) +falconsiena_filter_reset_search_depth( + __inout falconsiena_filter_t *fsfp, + __in falconsiena_filter_tbl_id_t tbl_id) { - switch (tbl_id) - { - case EFX_FILTER_TBL_RX_IP: - efp->ef_depth[EFX_FILTER_RX_TCP_FULL] = 0; - efp->ef_depth[EFX_FILTER_RX_TCP_WILD] = 0; - efp->ef_depth[EFX_FILTER_RX_UDP_FULL] = 0; - efp->ef_depth[EFX_FILTER_RX_UDP_WILD] = 0; + switch (tbl_id) { + case EFX_FS_FILTER_TBL_RX_IP: + fsfp->fsf_depth[EFX_FS_FILTER_RX_TCP_FULL] = 0; + fsfp->fsf_depth[EFX_FS_FILTER_RX_TCP_WILD] = 0; + fsfp->fsf_depth[EFX_FS_FILTER_RX_UDP_FULL] = 0; + fsfp->fsf_depth[EFX_FS_FILTER_RX_UDP_WILD] = 0; break; #if EFSYS_OPT_SIENA - case EFX_FILTER_TBL_RX_MAC: - efp->ef_depth[EFX_FILTER_RX_MAC_FULL] = 0; - efp->ef_depth[EFX_FILTER_RX_MAC_WILD] = 0; + case EFX_FS_FILTER_TBL_RX_MAC: + fsfp->fsf_depth[EFX_FS_FILTER_RX_MAC_FULL] = 0; + fsfp->fsf_depth[EFX_FS_FILTER_RX_MAC_WILD] = 0; break; - case EFX_FILTER_TBL_TX_IP: - efp->ef_depth[EFX_FILTER_TX_TCP_FULL] = 0; - efp->ef_depth[EFX_FILTER_TX_TCP_WILD] = 0; - efp->ef_depth[EFX_FILTER_TX_UDP_FULL] = 0; - efp->ef_depth[EFX_FILTER_TX_UDP_WILD] = 0; + case EFX_FS_FILTER_TBL_TX_IP: + fsfp->fsf_depth[EFX_FS_FILTER_TX_TCP_FULL] = 0; + fsfp->fsf_depth[EFX_FS_FILTER_TX_TCP_WILD] = 0; + fsfp->fsf_depth[EFX_FS_FILTER_TX_UDP_FULL] = 0; + fsfp->fsf_depth[EFX_FS_FILTER_TX_UDP_WILD] = 0; break; - case EFX_FILTER_TBL_TX_MAC: - efp->ef_depth[EFX_FILTER_TX_MAC_FULL] = 0; - efp->ef_depth[EFX_FILTER_TX_MAC_WILD] = 0; + case EFX_FS_FILTER_TBL_TX_MAC: + fsfp->fsf_depth[EFX_FS_FILTER_TX_MAC_FULL] = 0; + fsfp->fsf_depth[EFX_FS_FILTER_TX_MAC_WILD] = 0; break; #endif /* EFSYS_OPT_SIENA */ default: EFSYS_ASSERT(B_FALSE); break; } } static void -efx_filter_push_rx_limits( +falconsiena_filter_push_rx_limits( __in efx_nic_t *enp) { - efx_filter_t *efp = &enp->en_filter; + falconsiena_filter_t *fsfp = enp->en_filter.ef_falconsiena_filter; efx_oword_t oword; EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword); EFX_SET_OWORD_FIELD(oword, FRF_AZ_TCP_FULL_SRCH_LIMIT, - efp->ef_depth[EFX_FILTER_RX_TCP_FULL] + + fsfp->fsf_depth[EFX_FS_FILTER_RX_TCP_FULL] + FILTER_CTL_SRCH_FUDGE_FULL); EFX_SET_OWORD_FIELD(oword, FRF_AZ_TCP_WILD_SRCH_LIMIT, - efp->ef_depth[EFX_FILTER_RX_TCP_WILD] + + fsfp->fsf_depth[EFX_FS_FILTER_RX_TCP_WILD] + FILTER_CTL_SRCH_FUDGE_WILD); EFX_SET_OWORD_FIELD(oword, FRF_AZ_UDP_FULL_SRCH_LIMIT, - efp->ef_depth[EFX_FILTER_RX_UDP_FULL] + + fsfp->fsf_depth[EFX_FS_FILTER_RX_UDP_FULL] + FILTER_CTL_SRCH_FUDGE_FULL); EFX_SET_OWORD_FIELD(oword, FRF_AZ_UDP_WILD_SRCH_LIMIT, - efp->ef_depth[EFX_FILTER_RX_UDP_WILD] + + fsfp->fsf_depth[EFX_FS_FILTER_RX_UDP_WILD] + FILTER_CTL_SRCH_FUDGE_WILD); #if EFSYS_OPT_SIENA - if (efp->ef_tbl[EFX_FILTER_TBL_RX_MAC].eft_size) { + if (fsfp->fsf_tbl[EFX_FS_FILTER_TBL_RX_MAC].fsft_size) { EFX_SET_OWORD_FIELD(oword, FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT, - efp->ef_depth[EFX_FILTER_RX_MAC_FULL] + + fsfp->fsf_depth[EFX_FS_FILTER_RX_MAC_FULL] + FILTER_CTL_SRCH_FUDGE_FULL); EFX_SET_OWORD_FIELD(oword, FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT, - efp->ef_depth[EFX_FILTER_RX_MAC_WILD] + + fsfp->fsf_depth[EFX_FS_FILTER_RX_MAC_WILD] + FILTER_CTL_SRCH_FUDGE_WILD); } #endif /* EFSYS_OPT_SIENA */ EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword); } static void -efx_filter_push_tx_limits( +falconsiena_filter_push_tx_limits( __in efx_nic_t *enp) { - efx_filter_t *efp = &enp->en_filter; + falconsiena_filter_t *fsfp = enp->en_filter.ef_falconsiena_filter; efx_oword_t oword; - if (efp->ef_tbl[EFX_FILTER_TBL_TX_IP].eft_size == 0) - return; - EFX_BAR_READO(enp, FR_AZ_TX_CFG_REG, &oword); - EFX_SET_OWORD_FIELD(oword, FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE, - efp->ef_depth[EFX_FILTER_TX_TCP_FULL] + - FILTER_CTL_SRCH_FUDGE_FULL); - EFX_SET_OWORD_FIELD(oword, FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE, - efp->ef_depth[EFX_FILTER_TX_TCP_WILD] + - FILTER_CTL_SRCH_FUDGE_WILD); - EFX_SET_OWORD_FIELD(oword, FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE, - efp->ef_depth[EFX_FILTER_TX_UDP_FULL] + - FILTER_CTL_SRCH_FUDGE_FULL); - EFX_SET_OWORD_FIELD(oword, FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE, - efp->ef_depth[EFX_FILTER_TX_UDP_WILD] + - FILTER_CTL_SRCH_FUDGE_WILD); + if (fsfp->fsf_tbl[EFX_FS_FILTER_TBL_TX_IP].fsft_size != 0) { + EFX_SET_OWORD_FIELD(oword, + FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE, + fsfp->fsf_depth[EFX_FS_FILTER_TX_TCP_FULL] + + FILTER_CTL_SRCH_FUDGE_FULL); + EFX_SET_OWORD_FIELD(oword, + FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE, + fsfp->fsf_depth[EFX_FS_FILTER_TX_TCP_WILD] + + FILTER_CTL_SRCH_FUDGE_WILD); + EFX_SET_OWORD_FIELD(oword, + FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE, + fsfp->fsf_depth[EFX_FS_FILTER_TX_UDP_FULL] + + FILTER_CTL_SRCH_FUDGE_FULL); + EFX_SET_OWORD_FIELD(oword, + FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE, + fsfp->fsf_depth[EFX_FS_FILTER_TX_UDP_WILD] + + FILTER_CTL_SRCH_FUDGE_WILD); + } + if (fsfp->fsf_tbl[EFX_FS_FILTER_TBL_TX_MAC].fsft_size != 0) { + EFX_SET_OWORD_FIELD( + oword, FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE, + fsfp->fsf_depth[EFX_FS_FILTER_TX_MAC_FULL] + + FILTER_CTL_SRCH_FUDGE_FULL); + EFX_SET_OWORD_FIELD( + oword, FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE, + fsfp->fsf_depth[EFX_FS_FILTER_TX_MAC_WILD] + + FILTER_CTL_SRCH_FUDGE_WILD); + } + EFX_BAR_WRITEO(enp, FR_AZ_TX_CFG_REG, &oword); } /* Build a filter entry and return its n-tuple key. */ static __checkReturn uint32_t -efx_filter_build( +falconsiena_filter_build( __out efx_oword_t *filter, - __in efx_filter_spec_t *spec) + __in falconsiena_filter_spec_t *spec) { uint32_t dword3; uint32_t key; - uint8_t type = spec->efs_type; - uint8_t flags = spec->efs_flags; + uint8_t type = spec->fsfs_type; + uint32_t flags = spec->fsfs_flags; - switch (efx_filter_tbl_id(type)) { - case EFX_FILTER_TBL_RX_IP: { - boolean_t is_udp = (type == EFX_FILTER_RX_UDP_FULL || - type == EFX_FILTER_RX_UDP_WILD); + switch (falconsiena_filter_tbl_id(type)) { + case EFX_FS_FILTER_TBL_RX_IP: { + boolean_t is_udp = (type == EFX_FS_FILTER_RX_UDP_FULL || + type == EFX_FS_FILTER_RX_UDP_WILD); EFX_POPULATE_OWORD_7(*filter, - FRF_BZ_RSS_EN, (flags & EFX_FILTER_FLAG_RX_RSS) ? 1 : 0, - FRF_BZ_SCATTER_EN, (flags & EFX_FILTER_FLAG_RX_SCATTER) ? 1 : 0, + FRF_BZ_RSS_EN, + (flags & EFX_FILTER_FLAG_RX_RSS) ? 1 : 0, + FRF_BZ_SCATTER_EN, + (flags & EFX_FILTER_FLAG_RX_SCATTER) ? 1 : 0, FRF_AZ_TCP_UDP, is_udp, - FRF_AZ_RXQ_ID, spec->efs_dmaq_id, - EFX_DWORD_2, spec->efs_dword[2], - EFX_DWORD_1, spec->efs_dword[1], - EFX_DWORD_0, spec->efs_dword[0]); + FRF_AZ_RXQ_ID, spec->fsfs_dmaq_id, + EFX_DWORD_2, spec->fsfs_dword[2], + EFX_DWORD_1, spec->fsfs_dword[1], + EFX_DWORD_0, spec->fsfs_dword[0]); dword3 = is_udp; break; } #if EFSYS_OPT_SIENA - case EFX_FILTER_TBL_RX_MAC: { - boolean_t is_wild = (type == EFX_FILTER_RX_MAC_WILD); - EFX_POPULATE_OWORD_8(*filter, - FRF_CZ_RMFT_RSS_EN, (flags & EFX_FILTER_FLAG_RX_RSS) ? 1 : 0, - FRF_CZ_RMFT_SCATTER_EN, (flags & EFX_FILTER_FLAG_RX_SCATTER) ? 1 : 0, - FRF_CZ_RMFT_IP_OVERRIDE, (flags & EFX_FILTER_FLAG_RX_OVERRIDE_IP) ? 1 : 0, - FRF_CZ_RMFT_RXQ_ID, spec->efs_dmaq_id, + case EFX_FS_FILTER_TBL_RX_MAC: { + boolean_t is_wild = (type == EFX_FS_FILTER_RX_MAC_WILD); + EFX_POPULATE_OWORD_7(*filter, + FRF_CZ_RMFT_RSS_EN, + (flags & EFX_FILTER_FLAG_RX_RSS) ? 1 : 0, + FRF_CZ_RMFT_SCATTER_EN, + (flags & EFX_FILTER_FLAG_RX_SCATTER) ? 1 : 0, + FRF_CZ_RMFT_RXQ_ID, spec->fsfs_dmaq_id, FRF_CZ_RMFT_WILDCARD_MATCH, is_wild, - FRF_CZ_RMFT_DEST_MAC_DW1, spec->efs_dword[2], - FRF_CZ_RMFT_DEST_MAC_DW0, spec->efs_dword[1], - FRF_CZ_RMFT_VLAN_ID, spec->efs_dword[0]); + FRF_CZ_RMFT_DEST_MAC_DW1, spec->fsfs_dword[2], + FRF_CZ_RMFT_DEST_MAC_DW0, spec->fsfs_dword[1], + FRF_CZ_RMFT_VLAN_ID, spec->fsfs_dword[0]); dword3 = is_wild; break; } #endif /* EFSYS_OPT_SIENA */ - case EFX_FILTER_TBL_TX_IP: { - boolean_t is_udp = (type == EFX_FILTER_TX_UDP_FULL || - type == EFX_FILTER_TX_UDP_WILD); + case EFX_FS_FILTER_TBL_TX_IP: { + boolean_t is_udp = (type == EFX_FS_FILTER_TX_UDP_FULL || + type == EFX_FS_FILTER_TX_UDP_WILD); EFX_POPULATE_OWORD_5(*filter, FRF_CZ_TIFT_TCP_UDP, is_udp, - FRF_CZ_TIFT_TXQ_ID, spec->efs_dmaq_id, - EFX_DWORD_2, spec->efs_dword[2], - EFX_DWORD_1, spec->efs_dword[1], - EFX_DWORD_0, spec->efs_dword[0]); - dword3 = is_udp | spec->efs_dmaq_id << 1; + FRF_CZ_TIFT_TXQ_ID, spec->fsfs_dmaq_id, + EFX_DWORD_2, spec->fsfs_dword[2], + EFX_DWORD_1, spec->fsfs_dword[1], + EFX_DWORD_0, spec->fsfs_dword[0]); + dword3 = is_udp | spec->fsfs_dmaq_id << 1; break; } #if EFSYS_OPT_SIENA - case EFX_FILTER_TBL_TX_MAC: { - boolean_t is_wild = (type == EFX_FILTER_TX_MAC_WILD); + case EFX_FS_FILTER_TBL_TX_MAC: { + boolean_t is_wild = (type == EFX_FS_FILTER_TX_MAC_WILD); EFX_POPULATE_OWORD_5(*filter, - FRF_CZ_TMFT_TXQ_ID, spec->efs_dmaq_id, + FRF_CZ_TMFT_TXQ_ID, spec->fsfs_dmaq_id, FRF_CZ_TMFT_WILDCARD_MATCH, is_wild, - FRF_CZ_TMFT_SRC_MAC_DW1, spec->efs_dword[2], - FRF_CZ_TMFT_SRC_MAC_DW0, spec->efs_dword[1], - FRF_CZ_TMFT_VLAN_ID, spec->efs_dword[0]); - dword3 = is_wild | spec->efs_dmaq_id << 1; + FRF_CZ_TMFT_SRC_MAC_DW1, spec->fsfs_dword[2], + FRF_CZ_TMFT_SRC_MAC_DW0, spec->fsfs_dword[1], + FRF_CZ_TMFT_VLAN_ID, spec->fsfs_dword[0]); + dword3 = is_wild | spec->fsfs_dmaq_id << 1; break; } #endif /* EFSYS_OPT_SIENA */ default: EFSYS_ASSERT(B_FALSE); + return (0); } - key = spec->efs_dword[0] ^ spec->efs_dword[1] ^ spec->efs_dword[2] ^ dword3; + key = + spec->fsfs_dword[0] ^ + spec->fsfs_dword[1] ^ + spec->fsfs_dword[2] ^ + dword3; + return (key); } static __checkReturn int -efx_filter_push_entry( +falconsiena_filter_push_entry( __inout efx_nic_t *enp, - __in efx_filter_type_t type, + __in falconsiena_filter_type_t type, __in int index, __in efx_oword_t *eop) { int rc; - switch (type) - { - case EFX_FILTER_RX_TCP_FULL: - case EFX_FILTER_RX_TCP_WILD: - case EFX_FILTER_RX_UDP_FULL: - case EFX_FILTER_RX_UDP_WILD: - EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_FILTER_TBL0, index, eop); + switch (type) { + case EFX_FS_FILTER_RX_TCP_FULL: + case EFX_FS_FILTER_RX_TCP_WILD: + case EFX_FS_FILTER_RX_UDP_FULL: + case EFX_FS_FILTER_RX_UDP_WILD: + EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_FILTER_TBL0, index, + eop, B_TRUE); break; #if EFSYS_OPT_SIENA - case EFX_FILTER_RX_MAC_FULL: - case EFX_FILTER_RX_MAC_WILD: - EFX_BAR_TBL_WRITEO(enp, FR_CZ_RX_MAC_FILTER_TBL0, index, eop); + case EFX_FS_FILTER_RX_MAC_FULL: + case EFX_FS_FILTER_RX_MAC_WILD: + EFX_BAR_TBL_WRITEO(enp, FR_CZ_RX_MAC_FILTER_TBL0, index, + eop, B_TRUE); break; - case EFX_FILTER_TX_TCP_FULL: - case EFX_FILTER_TX_TCP_WILD: - case EFX_FILTER_TX_UDP_FULL: - case EFX_FILTER_TX_UDP_WILD: - EFX_BAR_TBL_WRITEO(enp, FR_CZ_TX_FILTER_TBL0, index, eop); + case EFX_FS_FILTER_TX_TCP_FULL: + case EFX_FS_FILTER_TX_TCP_WILD: + case EFX_FS_FILTER_TX_UDP_FULL: + case EFX_FS_FILTER_TX_UDP_WILD: + EFX_BAR_TBL_WRITEO(enp, FR_CZ_TX_FILTER_TBL0, index, + eop, B_TRUE); break; - case EFX_FILTER_TX_MAC_FULL: - case EFX_FILTER_TX_MAC_WILD: - EFX_BAR_TBL_WRITEO(enp, FR_CZ_TX_MAC_FILTER_TBL0, index, eop); + case EFX_FS_FILTER_TX_MAC_FULL: + case EFX_FS_FILTER_TX_MAC_WILD: + EFX_BAR_TBL_WRITEO(enp, FR_CZ_TX_MAC_FILTER_TBL0, index, + eop, B_TRUE); break; #endif /* EFSYS_OPT_SIENA */ default: + EFSYS_ASSERT(B_FALSE); rc = ENOTSUP; goto fail1; } return (0); fail1: return (rc); } static __checkReturn boolean_t -efx_filter_equal( - __in const efx_filter_spec_t *left, - __in const efx_filter_spec_t *right) +falconsiena_filter_equal( + __in const falconsiena_filter_spec_t *left, + __in const falconsiena_filter_spec_t *right) { - efx_filter_tbl_id_t tbl_id = efx_filter_tbl_id(left->efs_type); + falconsiena_filter_tbl_id_t tbl_id; - if (left->efs_type != right->efs_type) + tbl_id = falconsiena_filter_tbl_id(left->fsfs_type); + + + if (left->fsfs_type != right->fsfs_type) return (B_FALSE); - if (memcmp(left->efs_dword, right->efs_dword, sizeof(left->efs_dword))) + if (memcmp(left->fsfs_dword, right->fsfs_dword, + sizeof (left->fsfs_dword))) return (B_FALSE); - if ((tbl_id == EFX_FILTER_TBL_TX_IP || - tbl_id == EFX_FILTER_TBL_TX_MAC) && - left->efs_dmaq_id != right->efs_dmaq_id) + if ((tbl_id == EFX_FS_FILTER_TBL_TX_IP || + tbl_id == EFX_FS_FILTER_TBL_TX_MAC) && + left->fsfs_dmaq_id != right->fsfs_dmaq_id) return (B_FALSE); return (B_TRUE); } static __checkReturn int -efx_filter_search( - __in efx_filter_tbl_t *eftp, - __in efx_filter_spec_t *spec, +falconsiena_filter_search( + __in falconsiena_filter_tbl_t *fsftp, + __in falconsiena_filter_spec_t *spec, __in uint32_t key, __in boolean_t for_insert, __out int *filter_index, __out unsigned int *depth_required) { unsigned hash, incr, filter_idx, depth; - hash = efx_filter_tbl_hash(key); - incr = efx_filter_tbl_increment(key); + hash = falconsiena_filter_tbl_hash(key); + incr = falconsiena_filter_tbl_increment(key); - filter_idx = hash & (eftp->eft_size - 1); + filter_idx = hash & (fsftp->fsft_size - 1); depth = 1; for (;;) { - /* Return success if entry is used and matches this spec + /* + * Return success if entry is used and matches this spec * or entry is unused and we are trying to insert. */ - if (efx_filter_test_used(eftp, filter_idx) ? - efx_filter_equal(spec, &eftp->eft_spec[filter_idx]) : + if (falconsiena_filter_test_used(fsftp, filter_idx) ? + falconsiena_filter_equal(spec, + &fsftp->fsft_spec[filter_idx]) : for_insert) { *filter_index = filter_idx; *depth_required = depth; return (0); } /* Return failure if we reached the maximum search depth */ if (depth == FILTER_CTL_SRCH_MAX) - return for_insert ? EBUSY : ENOENT; + return (for_insert ? EBUSY : ENOENT); - filter_idx = (filter_idx + incr) & (eftp->eft_size - 1); + filter_idx = (filter_idx + incr) & (fsftp->fsft_size - 1); ++depth; } } - __checkReturn int -efx_filter_insert_filter( - __in efx_nic_t *enp, - __in efx_filter_spec_t *spec, - __in boolean_t replace) -{ - efx_filter_t *efp = &enp->en_filter; - efx_filter_tbl_id_t tbl_id = efx_filter_tbl_id(spec->efs_type); - efx_filter_tbl_t *eftp = &efp->ef_tbl[tbl_id]; - efx_filter_spec_t *saved_spec; - efx_oword_t filter; - int filter_idx; - unsigned int depth; - int state; - uint32_t key; - int rc; - - if (eftp->eft_size == 0) - return (EINVAL); - - key = efx_filter_build(&filter, spec); - - EFSYS_LOCK(enp->en_eslp, state); - - rc = efx_filter_search(eftp, spec, key, B_TRUE, &filter_idx, &depth); - if (rc != 0) - goto done; - - EFSYS_ASSERT3U(filter_idx, <, eftp->eft_size); - saved_spec = &eftp->eft_spec[filter_idx]; - - if (efx_filter_test_used(eftp, filter_idx)) { - if (replace == B_FALSE) { - rc = EEXIST; - goto done; - } - } - efx_filter_set_used(eftp, filter_idx); - *saved_spec = *spec; - - if (efp->ef_depth[spec->efs_type] < depth) { - efp->ef_depth[spec->efs_type] = depth; - if (tbl_id == EFX_FILTER_TBL_TX_IP || - tbl_id == EFX_FILTER_TBL_TX_MAC) - efx_filter_push_tx_limits(enp); - else - efx_filter_push_rx_limits(enp); - } - - efx_filter_push_entry(enp, spec->efs_type, filter_idx, &filter); - -done: - EFSYS_UNLOCK(enp->en_eslp, state); - return (rc); -} - static void -efx_filter_clear_entry( +falconsiena_filter_clear_entry( __in efx_nic_t *enp, - __in efx_filter_tbl_t *eftp, + __in falconsiena_filter_tbl_t *fsftp, __in int index) { efx_oword_t filter; - if (efx_filter_test_used(eftp, index)) { - efx_filter_clear_used(eftp, index); + if (falconsiena_filter_test_used(fsftp, index)) { + falconsiena_filter_clear_used(fsftp, index); EFX_ZERO_OWORD(filter); - efx_filter_push_entry(enp, eftp->eft_spec[index].efs_type, + falconsiena_filter_push_entry(enp, + fsftp->fsft_spec[index].fsfs_type, index, &filter); - memset(&eftp->eft_spec[index], 0, sizeof(eftp->eft_spec[0])); + memset(&fsftp->fsft_spec[index], + 0, sizeof (fsftp->fsft_spec[0])); } } - __checkReturn int -efx_filter_remove_filter( + void +falconsiena_filter_tbl_clear( __in efx_nic_t *enp, - __in efx_filter_spec_t *spec) + __in falconsiena_filter_tbl_id_t tbl_id) { - efx_filter_t *efp = &enp->en_filter; - efx_filter_tbl_id_t tbl_id = efx_filter_tbl_id(spec->efs_type); - efx_filter_tbl_t *eftp = &efp->ef_tbl[tbl_id]; - efx_filter_spec_t *saved_spec; - efx_oword_t filter; - int filter_idx; - unsigned int depth; - int state; - uint32_t key; - int rc; - - key = efx_filter_build(&filter, spec); - - EFSYS_LOCK(enp->en_eslp, state); - - rc = efx_filter_search(eftp, spec, key, B_FALSE, &filter_idx, &depth); - if (rc != 0) - goto out; - - saved_spec = &eftp->eft_spec[filter_idx]; - - efx_filter_clear_entry(enp, eftp, filter_idx); - if (eftp->eft_used == 0) - efx_filter_reset_search_depth(efp, tbl_id); - - rc = 0; - -out: - EFSYS_UNLOCK(enp->en_eslp, state); - return (rc); -} - - void -efx_filter_remove_index( - __inout efx_nic_t *enp, - __in efx_filter_type_t type, - __in int index) -{ - efx_filter_t *efp = &enp->en_filter; - efx_filter_tbl_id_t tbl_id = efx_filter_tbl_id(type); - efx_filter_tbl_t *eftp = &efp->ef_tbl[tbl_id]; - int state; - - if (index < 0) - return; - - EFSYS_LOCK(enp->en_eslp, state); - - efx_filter_clear_entry(enp, eftp, index); - if (eftp->eft_used == 0) - efx_filter_reset_search_depth(efp, tbl_id); - - EFSYS_UNLOCK(enp->en_eslp, state); -} - - void -efx_filter_tbl_clear( - __inout efx_nic_t *enp, - __in efx_filter_tbl_id_t tbl_id) -{ - efx_filter_t *efp = &enp->en_filter; - efx_filter_tbl_t *eftp = &efp->ef_tbl[tbl_id]; + falconsiena_filter_t *fsfp = enp->en_filter.ef_falconsiena_filter; + falconsiena_filter_tbl_t *fsftp = &fsfp->fsf_tbl[tbl_id]; int index; int state; EFSYS_LOCK(enp->en_eslp, state); - for (index = 0; index < eftp->eft_size; ++index) { - efx_filter_clear_entry(enp, eftp, index); + for (index = 0; index < fsftp->fsft_size; ++index) { + falconsiena_filter_clear_entry(enp, fsftp, index); } - if (eftp->eft_used == 0) - efx_filter_reset_search_depth(efp, tbl_id); + if (fsftp->fsft_used == 0) + falconsiena_filter_reset_search_depth(fsfp, tbl_id); EFSYS_UNLOCK(enp->en_eslp, state); } -/* Restore filter state after a reset */ - void -efx_filter_restore( +static __checkReturn int +falconsiena_filter_init( __in efx_nic_t *enp) { - efx_filter_t *efp = &enp->en_filter; - efx_filter_tbl_id_t tbl_id; - efx_filter_tbl_t *eftp; - efx_filter_spec_t *spec; - efx_oword_t filter; - int filter_idx; - int state; + falconsiena_filter_t *fsfp; + falconsiena_filter_tbl_t *fsftp; + int tbl_id; + int rc; - EFSYS_LOCK(enp->en_eslp, state); + EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (falconsiena_filter_t), fsfp); - for (tbl_id = 0; tbl_id < EFX_FILTER_NTBLS; tbl_id++) { - eftp = &efp->ef_tbl[tbl_id]; - for (filter_idx = 0; filter_idx < eftp->eft_size; filter_idx++) { - if (!efx_filter_test_used(eftp, filter_idx)) - continue; - - spec = &eftp->eft_spec[filter_idx]; - efx_filter_build(&filter, spec); - efx_filter_push_entry(enp, spec->efs_type, - filter_idx, &filter); - } + if (!fsfp) { + rc = ENOMEM; + goto fail1; } - efx_filter_push_rx_limits(enp); - efx_filter_push_tx_limits(enp); + enp->en_filter.ef_falconsiena_filter = fsfp; - EFSYS_UNLOCK(enp->en_eslp, state); -} - - void -efx_filter_redirect_index( - __inout efx_nic_t *enp, - __in efx_filter_type_t type, - __in int filter_index, - __in int rxq_index) -{ - efx_filter_t *efp = &enp->en_filter; - efx_filter_tbl_t *eftp = - &efp->ef_tbl[efx_filter_tbl_id(type)]; - efx_filter_spec_t *spec; - efx_oword_t filter; - int state; - - EFSYS_LOCK(enp->en_eslp, state); - - spec = &eftp->eft_spec[filter_index]; - spec->efs_dmaq_id = (uint16_t)rxq_index; - - efx_filter_build(&filter, spec); - efx_filter_push_entry(enp, spec->efs_type, filter_index, &filter); - - EFSYS_UNLOCK(enp->en_eslp, state); -} - - __checkReturn int -efx_filter_init( - __in efx_nic_t *enp) -{ - efx_filter_t *efp = &enp->en_filter; - efx_filter_tbl_t *eftp; - int tbl_id; - int rc; - - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); - EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_FILTER)); - - switch (enp->en_family) - { + switch (enp->en_family) { #if EFSYS_OPT_FALCON case EFX_FAMILY_FALCON: - eftp = &efp->ef_tbl[EFX_FILTER_TBL_RX_IP]; - eftp->eft_size = FR_AZ_RX_FILTER_TBL0_ROWS; + fsftp = &fsfp->fsf_tbl[EFX_FS_FILTER_TBL_RX_IP]; + fsftp->fsft_size = FR_AZ_RX_FILTER_TBL0_ROWS; break; #endif /* EFSYS_OPT_FALCON */ #if EFSYS_OPT_SIENA case EFX_FAMILY_SIENA: - eftp = &efp->ef_tbl[EFX_FILTER_TBL_RX_IP]; - eftp->eft_size = FR_AZ_RX_FILTER_TBL0_ROWS; + fsftp = &fsfp->fsf_tbl[EFX_FS_FILTER_TBL_RX_IP]; + fsftp->fsft_size = FR_AZ_RX_FILTER_TBL0_ROWS; - eftp = &efp->ef_tbl[EFX_FILTER_TBL_RX_MAC]; - eftp->eft_size = FR_CZ_RX_MAC_FILTER_TBL0_ROWS; + fsftp = &fsfp->fsf_tbl[EFX_FS_FILTER_TBL_RX_MAC]; + fsftp->fsft_size = FR_CZ_RX_MAC_FILTER_TBL0_ROWS; - eftp = &efp->ef_tbl[EFX_FILTER_TBL_TX_IP]; - eftp->eft_size = FR_CZ_TX_FILTER_TBL0_ROWS; + fsftp = &fsfp->fsf_tbl[EFX_FS_FILTER_TBL_TX_IP]; + fsftp->fsft_size = FR_CZ_TX_FILTER_TBL0_ROWS; - eftp = &efp->ef_tbl[EFX_FILTER_TBL_TX_MAC]; - eftp->eft_size = FR_CZ_TX_MAC_FILTER_TBL0_ROWS; + fsftp = &fsfp->fsf_tbl[EFX_FS_FILTER_TBL_TX_MAC]; + fsftp->fsft_size = FR_CZ_TX_MAC_FILTER_TBL0_ROWS; break; #endif /* EFSYS_OPT_SIENA */ default: rc = ENOTSUP; - goto fail1; + goto fail2; } - for (tbl_id = 0; tbl_id < EFX_FILTER_NTBLS; tbl_id++) { + for (tbl_id = 0; tbl_id < EFX_FS_FILTER_NTBLS; tbl_id++) { unsigned int bitmap_size; - eftp = &efp->ef_tbl[tbl_id]; - if (eftp->eft_size == 0) + fsftp = &fsfp->fsf_tbl[tbl_id]; + if (fsftp->fsft_size == 0) continue; - EFX_STATIC_ASSERT(sizeof(eftp->eft_bitmap[0]) == sizeof(uint32_t)); - bitmap_size = (eftp->eft_size + (sizeof(uint32_t) * 8) - 1) / 8; + EFX_STATIC_ASSERT(sizeof (fsftp->fsft_bitmap[0]) == + sizeof (uint32_t)); + bitmap_size = + (fsftp->fsft_size + (sizeof (uint32_t) * 8) - 1) / 8; - EFSYS_KMEM_ALLOC(enp->en_esip, bitmap_size, eftp->eft_bitmap); - if (!eftp->eft_bitmap) { + EFSYS_KMEM_ALLOC(enp->en_esip, bitmap_size, fsftp->fsft_bitmap); + if (!fsftp->fsft_bitmap) { rc = ENOMEM; - goto fail2; + goto fail3; } - EFSYS_KMEM_ALLOC(enp->en_esip, eftp->eft_size * sizeof(*eftp->eft_spec), - eftp->eft_spec); - if (!eftp->eft_spec) { + EFSYS_KMEM_ALLOC(enp->en_esip, + fsftp->fsft_size * sizeof (*fsftp->fsft_spec), + fsftp->fsft_spec); + if (!fsftp->fsft_spec) { rc = ENOMEM; - goto fail3; + goto fail4; } - memset(eftp->eft_spec, 0, eftp->eft_size * sizeof(*eftp->eft_spec)); + memset(fsftp->fsft_spec, 0, + fsftp->fsft_size * sizeof (*fsftp->fsft_spec)); } - enp->en_mod_flags |= EFX_MOD_FILTER; return (0); +fail4: + EFSYS_PROBE(fail4); + fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); - efx_filter_fini(enp); + falconsiena_filter_fini(enp); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } - void -efx_filter_fini( +static void +falconsiena_filter_fini( __in efx_nic_t *enp) { - efx_filter_t *efp = &enp->en_filter; - efx_filter_tbl_id_t tbl_id; + falconsiena_filter_t *fsfp = enp->en_filter.ef_falconsiena_filter; + falconsiena_filter_tbl_id_t tbl_id; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); - for (tbl_id = 0; tbl_id < EFX_FILTER_NTBLS; tbl_id++) { - efx_filter_tbl_t *eftp = &efp->ef_tbl[tbl_id]; + if (fsfp == NULL) + return; + + for (tbl_id = 0; tbl_id < EFX_FS_FILTER_NTBLS; tbl_id++) { + falconsiena_filter_tbl_t *fsftp = &fsfp->fsf_tbl[tbl_id]; unsigned int bitmap_size; - EFX_STATIC_ASSERT(sizeof(eftp->eft_bitmap[0]) == sizeof(uint32_t)); - bitmap_size = (eftp->eft_size + (sizeof(uint32_t) * 8) - 1) / 8; + EFX_STATIC_ASSERT(sizeof (fsftp->fsft_bitmap[0]) == + sizeof (uint32_t)); + bitmap_size = + (fsftp->fsft_size + (sizeof (uint32_t) * 8) - 1) / 8; - if (eftp->eft_bitmap != NULL) { + if (fsftp->fsft_bitmap != NULL) { EFSYS_KMEM_FREE(enp->en_esip, bitmap_size, - eftp->eft_bitmap); - eftp->eft_bitmap = NULL; + fsftp->fsft_bitmap); + fsftp->fsft_bitmap = NULL; } - if (eftp->eft_spec != NULL) { - EFSYS_KMEM_FREE(enp->en_esip, eftp->eft_size * - sizeof(*eftp->eft_spec), eftp->eft_spec); - eftp->eft_spec = NULL; + if (fsftp->fsft_spec != NULL) { + EFSYS_KMEM_FREE(enp->en_esip, fsftp->fsft_size * + sizeof (*fsftp->fsft_spec), fsftp->fsft_spec); + fsftp->fsft_spec = NULL; } } - enp->en_mod_flags &= ~EFX_MOD_FILTER; + EFSYS_KMEM_FREE(enp->en_esip, sizeof (falconsiena_filter_t), + enp->en_filter.ef_falconsiena_filter); } -extern void -efx_filter_spec_rx_ipv4_tcp_full( - __inout efx_filter_spec_t *spec, - __in unsigned int flags, - __in uint32_t src_ip, - __in uint16_t src_tcp, - __in uint32_t dest_ip, - __in uint16_t dest_tcp) +/* Restore filter state after a reset */ +static __checkReturn int +falconsiena_filter_restore( + __in efx_nic_t *enp) { - EFSYS_ASSERT3P(spec, !=, NULL); - EFSYS_ASSERT((flags & ~(EFX_FILTER_FLAG_RX_RSS | - EFX_FILTER_FLAG_RX_SCATTER)) == 0); + falconsiena_filter_t *fsfp = enp->en_filter.ef_falconsiena_filter; + falconsiena_filter_tbl_id_t tbl_id; + falconsiena_filter_tbl_t *fsftp; + falconsiena_filter_spec_t *spec; + efx_oword_t filter; + int filter_idx; + int state; + int rc; - spec->efs_type = EFX_FILTER_RX_TCP_FULL; - spec->efs_flags = (uint8_t)flags; - spec->efs_dword[0] = src_tcp | src_ip << 16; - spec->efs_dword[1] = dest_tcp << 16 | src_ip >> 16; - spec->efs_dword[2] = dest_ip; -} + EFSYS_LOCK(enp->en_eslp, state); -extern void -efx_filter_spec_rx_ipv4_tcp_wild( - __inout efx_filter_spec_t *spec, - __in unsigned int flags, - __in uint32_t dest_ip, - __in uint16_t dest_tcp) -{ - EFSYS_ASSERT3P(spec, !=, NULL); - EFSYS_ASSERT((flags & ~(EFX_FILTER_FLAG_RX_RSS | - EFX_FILTER_FLAG_RX_SCATTER)) == 0); + for (tbl_id = 0; tbl_id < EFX_FS_FILTER_NTBLS; tbl_id++) { + fsftp = &fsfp->fsf_tbl[tbl_id]; + for (filter_idx = 0; + filter_idx < fsftp->fsft_size; + filter_idx++) { + if (!falconsiena_filter_test_used(fsftp, filter_idx)) + continue; - spec->efs_type = EFX_FILTER_RX_TCP_WILD; - spec->efs_flags = (uint8_t)flags; - spec->efs_dword[0] = 0; - spec->efs_dword[1] = dest_tcp << 16; - spec->efs_dword[2] = dest_ip; -} + spec = &fsftp->fsft_spec[filter_idx]; + if ((rc = falconsiena_filter_build(&filter, spec)) != 0) + goto fail1; + if ((rc = falconsiena_filter_push_entry(enp, + spec->fsfs_type, filter_idx, &filter)) != 0) + goto fail2; + } + } -extern void -efx_filter_spec_rx_ipv4_udp_full( - __inout efx_filter_spec_t *spec, - __in unsigned int flags, - __in uint32_t src_ip, - __in uint16_t src_udp, - __in uint32_t dest_ip, - __in uint16_t dest_udp) -{ - EFSYS_ASSERT3P(spec, !=, NULL); - EFSYS_ASSERT((flags & ~(EFX_FILTER_FLAG_RX_RSS | - EFX_FILTER_FLAG_RX_SCATTER)) == 0); + falconsiena_filter_push_rx_limits(enp); + falconsiena_filter_push_tx_limits(enp); - spec->efs_type = EFX_FILTER_RX_UDP_FULL; - spec->efs_flags = (uint8_t)flags; - spec->efs_dword[0] = src_udp | src_ip << 16; - spec->efs_dword[1] = dest_udp << 16 | src_ip >> 16; - spec->efs_dword[2] = dest_ip; -} + EFSYS_UNLOCK(enp->en_eslp, state); -extern void -efx_filter_spec_rx_ipv4_udp_wild( - __inout efx_filter_spec_t *spec, - __in unsigned int flags, - __in uint32_t dest_ip, - __in uint16_t dest_udp) -{ - EFSYS_ASSERT3P(spec, !=, NULL); - EFSYS_ASSERT((flags & ~(EFX_FILTER_FLAG_RX_RSS | - EFX_FILTER_FLAG_RX_SCATTER)) == 0); + return (0); - spec->efs_type = EFX_FILTER_RX_UDP_WILD; - spec->efs_flags = (uint8_t)flags; - spec->efs_dword[0] = dest_udp; - spec->efs_dword[1] = 0; - spec->efs_dword[2] = dest_ip; -} +fail2: + EFSYS_PROBE(fail2); -#if EFSYS_OPT_SIENA -extern void -efx_filter_spec_rx_mac_full( - __inout efx_filter_spec_t *spec, - __in unsigned int flags, - __in uint16_t vlan_id, - __in uint8_t *dest_mac) -{ - EFSYS_ASSERT3P(spec, !=, NULL); - EFSYS_ASSERT3P(dest_mac, !=, NULL); - EFSYS_ASSERT((flags & ~(EFX_FILTER_FLAG_RX_RSS | - EFX_FILTER_FLAG_RX_SCATTER | - EFX_FILTER_FLAG_RX_OVERRIDE_IP)) == 0); +fail1: + EFSYS_PROBE1(fail1, int, rc); - spec->efs_type = EFX_FILTER_RX_MAC_FULL; - spec->efs_flags = (uint8_t)flags; - spec->efs_dword[0] = vlan_id; - spec->efs_dword[1] = - dest_mac[2] << 24 | - dest_mac[3] << 16 | - dest_mac[4] << 8 | - dest_mac[5]; - spec->efs_dword[2] = - dest_mac[0] << 8 | - dest_mac[1]; + EFSYS_UNLOCK(enp->en_eslp, state); + + return (rc); } -#endif /* EFSYS_OPT_SIENA */ -#if EFSYS_OPT_SIENA -extern void -efx_filter_spec_rx_mac_wild( +static __checkReturn int +falconsiena_filter_add( + __in efx_nic_t *enp, __inout efx_filter_spec_t *spec, - __in unsigned int flags, - __in uint8_t *dest_mac) + __in boolean_t may_replace) { - EFSYS_ASSERT3P(spec, !=, NULL); - EFSYS_ASSERT3P(dest_mac, !=, NULL); - EFSYS_ASSERT((flags & ~(EFX_FILTER_FLAG_RX_RSS | - EFX_FILTER_FLAG_RX_SCATTER | - EFX_FILTER_FLAG_RX_OVERRIDE_IP)) == 0); + int rc; + falconsiena_filter_spec_t fs_spec; + falconsiena_filter_t *fsfp = enp->en_filter.ef_falconsiena_filter; + falconsiena_filter_tbl_id_t tbl_id; + falconsiena_filter_tbl_t *fsftp; + falconsiena_filter_spec_t *saved_fs_spec; + efx_oword_t filter; + int filter_idx; + unsigned int depth; + int state; + uint32_t key; - spec->efs_type = EFX_FILTER_RX_MAC_WILD; - spec->efs_flags = (uint8_t)flags; - spec->efs_dword[0] = 0; - spec->efs_dword[1] = - dest_mac[2] << 24 | - dest_mac[3] << 16 | - dest_mac[4] << 8 | - dest_mac[5]; - spec->efs_dword[2] = - dest_mac[0] << 8 | - dest_mac[1]; -} -#endif /* EFSYS_OPT_SIENA */ -#if EFSYS_OPT_SIENA -extern void -efx_filter_spec_tx_ipv4_tcp_full( - __inout efx_filter_spec_t *spec, - __in uint32_t src_ip, - __in uint16_t src_tcp, - __in uint32_t dest_ip, - __in uint16_t dest_tcp) -{ EFSYS_ASSERT3P(spec, !=, NULL); - spec->efs_type = EFX_FILTER_TX_TCP_FULL; - spec->efs_flags = 0; - spec->efs_dword[0] = src_tcp | src_ip << 16; - spec->efs_dword[1] = dest_tcp << 16 | src_ip >> 16; - spec->efs_dword[2] = dest_ip; -} -#endif /* EFSYS_OPT_SIENA */ + if ((rc = falconsiena_filter_spec_from_gen_spec(&fs_spec, spec)) != 0) + goto fail1; -#if EFSYS_OPT_SIENA -extern void -efx_filter_spec_tx_ipv4_tcp_wild( - __inout efx_filter_spec_t *spec, - __in uint32_t src_ip, - __in uint16_t src_tcp) -{ - EFSYS_ASSERT3P(spec, !=, NULL); + tbl_id = falconsiena_filter_tbl_id(fs_spec.fsfs_type); + fsftp = &fsfp->fsf_tbl[tbl_id]; - spec->efs_type = EFX_FILTER_TX_TCP_WILD; - spec->efs_flags = 0; - spec->efs_dword[0] = 0; - spec->efs_dword[1] = src_tcp << 16; - spec->efs_dword[2] = src_ip; -} -#endif /* EFSYS_OPT_SIENA */ + if (fsftp->fsft_size == 0) { + rc = EINVAL; + goto fail2; + } -#if EFSYS_OPT_SIENA -extern void -efx_filter_spec_tx_ipv4_udp_full( - __inout efx_filter_spec_t *spec, - __in uint32_t src_ip, - __in uint16_t src_udp, - __in uint32_t dest_ip, - __in uint16_t dest_udp) -{ - EFSYS_ASSERT3P(spec, !=, NULL); + key = falconsiena_filter_build(&filter, &fs_spec); - spec->efs_type = EFX_FILTER_TX_UDP_FULL; - spec->efs_flags = 0; - spec->efs_dword[0] = src_udp | src_ip << 16; - spec->efs_dword[1] = dest_udp << 16 | src_ip >> 16; - spec->efs_dword[2] = dest_ip; -} -#endif /* EFSYS_OPT_SIENA */ + EFSYS_LOCK(enp->en_eslp, state); -#if EFSYS_OPT_SIENA -extern void -efx_filter_spec_tx_ipv4_udp_wild( - __inout efx_filter_spec_t *spec, - __in uint32_t src_ip, - __in uint16_t src_udp) -{ - EFSYS_ASSERT3P(spec, !=, NULL); + rc = falconsiena_filter_search(fsftp, &fs_spec, key, B_TRUE, + &filter_idx, &depth); + if (rc != 0) + goto fail3; - spec->efs_type = EFX_FILTER_TX_UDP_WILD; - spec->efs_flags = 0; - spec->efs_dword[0] = src_udp; - spec->efs_dword[1] = 0; - spec->efs_dword[2] = src_ip; + EFSYS_ASSERT3U(filter_idx, <, fsftp->fsft_size); + saved_fs_spec = &fsftp->fsft_spec[filter_idx]; + + if (falconsiena_filter_test_used(fsftp, filter_idx)) { + if (may_replace == B_FALSE) { + rc = EEXIST; + goto fail4; + } + } + falconsiena_filter_set_used(fsftp, filter_idx); + *saved_fs_spec = fs_spec; + + if (fsfp->fsf_depth[fs_spec.fsfs_type] < depth) { + fsfp->fsf_depth[fs_spec.fsfs_type] = depth; + if (tbl_id == EFX_FS_FILTER_TBL_TX_IP || + tbl_id == EFX_FS_FILTER_TBL_TX_MAC) + falconsiena_filter_push_tx_limits(enp); + else + falconsiena_filter_push_rx_limits(enp); + } + + falconsiena_filter_push_entry(enp, fs_spec.fsfs_type, + filter_idx, &filter); + + EFSYS_UNLOCK(enp->en_eslp, state); + return (0); + +fail4: + EFSYS_PROBE(fail4); + +fail3: + EFSYS_UNLOCK(enp->en_eslp, state); + EFSYS_PROBE(fail3); + +fail2: + EFSYS_PROBE(fail2); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + return (rc); } -#endif /* EFSYS_OPT_SIENA */ -#if EFSYS_OPT_SIENA -extern void -efx_filter_spec_tx_mac_full( - __inout efx_filter_spec_t *spec, - __in uint16_t vlan_id, - __in uint8_t *src_mac) +static __checkReturn int +falconsiena_filter_delete( + __in efx_nic_t *enp, + __inout efx_filter_spec_t *spec) { + int rc; + falconsiena_filter_spec_t fs_spec; + falconsiena_filter_t *fsfp = enp->en_filter.ef_falconsiena_filter; + falconsiena_filter_tbl_id_t tbl_id; + falconsiena_filter_tbl_t *fsftp; + falconsiena_filter_spec_t *saved_spec; + efx_oword_t filter; + int filter_idx; + unsigned int depth; + int state; + uint32_t key; + EFSYS_ASSERT3P(spec, !=, NULL); - EFSYS_ASSERT3P(src_mac, !=, NULL); - spec->efs_type = EFX_FILTER_TX_MAC_FULL; - spec->efs_flags = 0; - spec->efs_dword[0] = vlan_id; - spec->efs_dword[1] = - src_mac[2] << 24 | - src_mac[3] << 16 | - src_mac[4] << 8 | - src_mac[5]; - spec->efs_dword[2] = - src_mac[0] << 8 | - src_mac[1]; + if ((rc = falconsiena_filter_spec_from_gen_spec(&fs_spec, spec)) != 0) + goto fail1; + + tbl_id = falconsiena_filter_tbl_id(fs_spec.fsfs_type); + fsftp = &fsfp->fsf_tbl[tbl_id]; + + key = falconsiena_filter_build(&filter, &fs_spec); + + EFSYS_LOCK(enp->en_eslp, state); + + rc = falconsiena_filter_search(fsftp, &fs_spec, key, B_FALSE, + &filter_idx, &depth); + if (rc != 0) + goto fail2; + + saved_spec = &fsftp->fsft_spec[filter_idx]; + + falconsiena_filter_clear_entry(enp, fsftp, filter_idx); + if (fsftp->fsft_used == 0) + falconsiena_filter_reset_search_depth(fsfp, tbl_id); + + EFSYS_UNLOCK(enp->en_eslp, state); + return (0); + +fail2: + EFSYS_UNLOCK(enp->en_eslp, state); + EFSYS_PROBE(fail2); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + return (rc); } -#endif /* EFSYS_OPT_SIENA */ -#if EFSYS_OPT_SIENA -extern void -efx_filter_spec_tx_mac_wild( - __inout efx_filter_spec_t *spec, - __in uint8_t *src_mac) +#define MAX_SUPPORTED 4 + +static __checkReturn int +falconsiena_filter_supported_filters( + __in efx_nic_t *enp, + __out uint32_t *list, + __out size_t *length) { - EFSYS_ASSERT3P(spec, !=, NULL); - EFSYS_ASSERT3P(src_mac, !=, NULL); + int index = 0; + uint32_t rx_matches[MAX_SUPPORTED]; + int rc; - spec->efs_type = EFX_FILTER_TX_MAC_WILD; - spec->efs_flags = 0; - spec->efs_dword[0] = 0; - spec->efs_dword[1] = - src_mac[2] << 24 | - src_mac[3] << 16 | - src_mac[4] << 8 | - src_mac[5]; - spec->efs_dword[2] = - src_mac[0] << 8 | - src_mac[1]; + if (list == NULL) { + rc = EINVAL; + goto fail1; + } + + rx_matches[index++] = + EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO | + EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT | + EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT; + + rx_matches[index++] = + EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO | + EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT; + + if (enp->en_features & EFX_FEATURE_MAC_HEADER_FILTERS) { + rx_matches[index++] = + EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC; + + rx_matches[index++] = EFX_FILTER_MATCH_LOC_MAC; + } + + EFSYS_ASSERT3U(index, <=, MAX_SUPPORTED); + + *length = index; + memcpy(list, rx_matches, *length); + + return (0); + +fail1: + + return (rc); } -#endif /* EFSYS_OPT_SIENA */ +#undef MAX_SUPPORTED + +#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ #endif /* EFSYS_OPT_FILTER */ Property changes on: head/sys/dev/sfxge/common/efx_filter.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_hash.c =================================================================== --- head/sys/dev/sfxge/common/efx_hash.c (nonexistent) +++ head/sys/dev/sfxge/common/efx_hash.c (revision 283514) @@ -0,0 +1,333 @@ +/*- + * Copyright 2006 Bob Jenkins + * + * Derived from public domain source, see + * : + * + * "lookup3.c, by Bob Jenkins, May 2006, Public Domain. + * + * These are functions for producing 32-bit hashes for hash table lookup... + * ...You can use this free for any purpose. It's in the public domain. + * It has no warranty." + * + * Copyright (c) 2014-2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "efsys.h" +#include "efx.h" +#include "efx_types.h" +#include "efx_impl.h" + +/* Hash initial value */ +#define EFX_HASH_INITIAL_VALUE 0xdeadbeef + +/* + * Rotate a 32-bit value left + * + * Allow platform to provide an intrinsic or optimised routine and + * fall-back to a simple shift based implementation. + */ +#if EFSYS_HAS_ROTL_DWORD + +#define EFX_HASH_ROTATE(_value, _shift) \ + EFSYS_ROTL_DWORD(_value, _shift) + +#else + +#define EFX_HASH_ROTATE(_value, _shift) \ + (((_value) << (_shift)) | ((_value) >> (32 - (_shift)))) + +#endif + +/* Mix three 32-bit values reversibly */ +#define EFX_HASH_MIX(_a, _b, _c) \ + do { \ + _a -= _c; \ + _a ^= EFX_HASH_ROTATE(_c, 4); \ + _c += _b; \ + _b -= _a; \ + _b ^= EFX_HASH_ROTATE(_a, 6); \ + _a += _c; \ + _c -= _b; \ + _c ^= EFX_HASH_ROTATE(_b, 8); \ + _b += _a; \ + _a -= _c; \ + _a ^= EFX_HASH_ROTATE(_c, 16); \ + _c += _b; \ + _b -= _a; \ + _b ^= EFX_HASH_ROTATE(_a, 19); \ + _a += _c; \ + _c -= _b; \ + _c ^= EFX_HASH_ROTATE(_b, 4); \ + _b += _a; \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +/* Final mixing of three 32-bit values into one (_c) */ +#define EFX_HASH_FINALISE(_a, _b, _c) \ + do { \ + _c ^= _b; \ + _c -= EFX_HASH_ROTATE(_b, 14); \ + _a ^= _c; \ + _a -= EFX_HASH_ROTATE(_c, 11); \ + _b ^= _a; \ + _b -= EFX_HASH_ROTATE(_a, 25); \ + _c ^= _b; \ + _c -= EFX_HASH_ROTATE(_b, 16); \ + _a ^= _c; \ + _a -= EFX_HASH_ROTATE(_c, 4); \ + _b ^= _a; \ + _b -= EFX_HASH_ROTATE(_a, 14); \ + _c ^= _b; \ + _c -= EFX_HASH_ROTATE(_b, 24); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + + +/* Produce a 32-bit hash from 32-bit aligned input */ + __checkReturn uint32_t +efx_hash_dwords( + __in_ecount(count) uint32_t const *input, + __in size_t count, + __in uint32_t init) +{ + uint32_t a; + uint32_t b; + uint32_t c; + + /* Set up the initial internal state */ + a = b = c = EFX_HASH_INITIAL_VALUE + + (((uint32_t)count) * sizeof (uint32_t)) + init; + + /* Handle all but the last three dwords of the input */ + while (count > 3) { + a += input[0]; + b += input[1]; + c += input[2]; + EFX_HASH_MIX(a, b, c); + + count -= 3; + input += 3; + } + + /* Handle the left-overs */ + switch (count) { + case 3: + c += input[2]; + /* Fall-through */ + case 2: + b += input[1]; + /* Fall-through */ + case 1: + a += input[0]; + EFX_HASH_FINALISE(a, b, c); + break; + + case 0: + /* Should only get here if count parameter was zero */ + break; + } + + return (c); +} + +#if EFSYS_IS_BIG_ENDIAN + +/* Produce a 32-bit hash from arbitrarily aligned input */ + __checkReturn uint32_t +efx_hash_bytes( + __in_ecount(length) uint8_t const *input, + __in size_t length, + __in uint32_t init) +{ + uint32_t a; + uint32_t b; + uint32_t c; + + /* Set up the initial internal state */ + a = b = c = EFX_HASH_INITIAL_VALUE + (uint32_t)length + init; + + /* Handle all but the last twelve bytes of the input */ + while (length > 12) { + a += ((uint32_t)input[0]) << 24; + a += ((uint32_t)input[1]) << 16; + a += ((uint32_t)input[2]) << 8; + a += ((uint32_t)input[3]); + b += ((uint32_t)input[4]) << 24; + b += ((uint32_t)input[5]) << 16; + b += ((uint32_t)input[6]) << 8; + b += ((uint32_t)input[7]); + c += ((uint32_t)input[8]) << 24; + c += ((uint32_t)input[9]) << 16; + c += ((uint32_t)input[10]) << 8; + c += ((uint32_t)input[11]); + EFX_HASH_MIX(a, b, c); + length -= 12; + input += 12; + } + + /* Handle the left-overs */ + switch (length) { + case 12: + c += ((uint32_t)input[11]); + /* Fall-through */ + case 11: + c += ((uint32_t)input[10]) << 8; + /* Fall-through */ + case 10: + c += ((uint32_t)input[9]) << 16; + /* Fall-through */ + case 9: + c += ((uint32_t)input[8]) << 24; + /* Fall-through */ + case 8: + b += ((uint32_t)input[7]); + /* Fall-through */ + case 7: + b += ((uint32_t)input[6]) << 8; + /* Fall-through */ + case 6: + b += ((uint32_t)input[5]) << 16; + /* Fall-through */ + case 5: + b += ((uint32_t)input[4]) << 24; + /* Fall-through */ + case 4: + a += ((uint32_t)input[3]); + /* Fall-through */ + case 3: + a += ((uint32_t)input[2]) << 8; + /* Fall-through */ + case 2: + a += ((uint32_t)input[1]) << 16; + /* Fall-through */ + case 1: + a += ((uint32_t)input[0]) << 24; + EFX_HASH_FINALISE(a, b, c); + break; + + case 0: + /* Should only get here if length parameter was zero */ + break; + } + + return (c); +} + +#elif EFSYS_IS_LITTLE_ENDIAN + +/* Produce a 32-bit hash from arbitrarily aligned input */ + __checkReturn uint32_t +efx_hash_bytes( + __in_ecount(length) uint8_t const *input, + __in size_t length, + __in uint32_t init) +{ + uint32_t a; + uint32_t b; + uint32_t c; + + /* Set up the initial internal state */ + a = b = c = EFX_HASH_INITIAL_VALUE + (uint32_t)length + init; + + /* Handle all but the last twelve bytes of the input */ + while (length > 12) { + a += ((uint32_t)input[0]); + a += ((uint32_t)input[1]) << 8; + a += ((uint32_t)input[2]) << 16; + a += ((uint32_t)input[3]) << 24; + b += ((uint32_t)input[4]); + b += ((uint32_t)input[5]) << 8; + b += ((uint32_t)input[6]) << 16; + b += ((uint32_t)input[7]) << 24; + c += ((uint32_t)input[8]); + c += ((uint32_t)input[9]) << 8; + c += ((uint32_t)input[10]) << 16; + c += ((uint32_t)input[11]) << 24; + EFX_HASH_MIX(a, b, c); + length -= 12; + input += 12; + } + + /* Handle the left-overs */ + switch (length) { + case 12: + c += ((uint32_t)input[11]) << 24; + /* Fall-through */ + case 11: + c += ((uint32_t)input[10]) << 16; + /* Fall-through */ + case 10: + c += ((uint32_t)input[9]) << 8; + /* Fall-through */ + case 9: + c += ((uint32_t)input[8]); + /* Fall-through */ + case 8: + b += ((uint32_t)input[7]) << 24; + /* Fall-through */ + case 7: + b += ((uint32_t)input[6]) << 16; + /* Fall-through */ + case 6: + b += ((uint32_t)input[5]) << 8; + /* Fall-through */ + case 5: + b += ((uint32_t)input[4]); + /* Fall-through */ + case 4: + a += ((uint32_t)input[3]) << 24; + /* Fall-through */ + case 3: + a += ((uint32_t)input[2]) << 16; + /* Fall-through */ + case 2: + a += ((uint32_t)input[1]) << 8; + /* Fall-through */ + case 1: + a += ((uint32_t)input[0]); + EFX_HASH_FINALISE(a, b, c); + break; + + case 0: + /* Should only get here if length parameter was zero */ + break; + } + + return (c); +} + +#else + +#error "Neither of EFSYS_IS_{BIG,LITTLE}_ENDIAN is set" + +#endif Property changes on: head/sys/dev/sfxge/common/efx_hash.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_impl.h =================================================================== --- head/sys/dev/sfxge/common/efx_impl.h (revision 283513) +++ head/sys/dev/sfxge/common/efx_impl.h (revision 283514) @@ -1,747 +1,1166 @@ /*- - * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2007-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + * * $FreeBSD$ */ #ifndef _SYS_EFX_IMPL_H #define _SYS_EFX_IMPL_H #include "efsys.h" #include "efx.h" #include "efx_regs.h" +#include "efx_regs_ef10.h" +/* FIXME: Add definition for driver generated software events */ +#ifndef ESE_DZ_EV_CODE_DRV_GEN_EV +#define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV +#endif + +#include "efx_check.h" + + #if EFSYS_OPT_FALCON #include "falcon_impl.h" #endif /* EFSYS_OPT_FALCON */ #if EFSYS_OPT_SIENA #include "siena_impl.h" #endif /* EFSYS_OPT_SIENA */ +#if EFSYS_OPT_HUNTINGTON +#include "hunt_impl.h" +#endif /* EFSYS_OPT_HUNTINGTON */ + #ifdef __cplusplus extern "C" { #endif -#define EFX_MOD_MCDI 0x00000001 -#define EFX_MOD_PROBE 0x00000002 -#define EFX_MOD_NVRAM 0x00000004 -#define EFX_MOD_VPD 0x00000008 -#define EFX_MOD_NIC 0x00000010 -#define EFX_MOD_INTR 0x00000020 -#define EFX_MOD_EV 0x00000040 -#define EFX_MOD_RX 0x00000080 -#define EFX_MOD_TX 0x00000100 -#define EFX_MOD_PORT 0x00000200 -#define EFX_MOD_MON 0x00000400 -#define EFX_MOD_WOL 0x00000800 -#define EFX_MOD_FILTER 0x00001000 +#define EFX_MOD_MCDI 0x00000001 +#define EFX_MOD_PROBE 0x00000002 +#define EFX_MOD_NVRAM 0x00000004 +#define EFX_MOD_VPD 0x00000008 +#define EFX_MOD_NIC 0x00000010 +#define EFX_MOD_INTR 0x00000020 +#define EFX_MOD_EV 0x00000040 +#define EFX_MOD_RX 0x00000080 +#define EFX_MOD_TX 0x00000100 +#define EFX_MOD_PORT 0x00000200 +#define EFX_MOD_MON 0x00000400 +#define EFX_MOD_WOL 0x00000800 +#define EFX_MOD_FILTER 0x00001000 +#define EFX_MOD_PKTFILTER 0x00002000 -#define EFX_RESET_MAC 0x00000001 -#define EFX_RESET_PHY 0x00000002 +#define EFX_RESET_MAC 0x00000001 +#define EFX_RESET_PHY 0x00000002 +#define EFX_RESET_RXQ_ERR 0x00000004 +#define EFX_RESET_TXQ_ERR 0x00000008 typedef enum efx_mac_type_e { EFX_MAC_INVALID = 0, EFX_MAC_FALCON_GMAC, EFX_MAC_FALCON_XMAC, EFX_MAC_SIENA, + EFX_MAC_HUNTINGTON, EFX_MAC_NTYPES } efx_mac_type_t; +typedef struct efx_ev_ops_s { + int (*eevo_init)(efx_nic_t *); + void (*eevo_fini)(efx_nic_t *); + int (*eevo_qcreate)(efx_nic_t *, unsigned int, + efsys_mem_t *, size_t, uint32_t, + efx_evq_t *); + void (*eevo_qdestroy)(efx_evq_t *); + int (*eevo_qprime)(efx_evq_t *, unsigned int); + void (*eevo_qpost)(efx_evq_t *, uint16_t); + int (*eevo_qmoderate)(efx_evq_t *, unsigned int); +#if EFSYS_OPT_QSTATS + void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *); +#endif +} efx_ev_ops_t; + +typedef struct efx_tx_ops_s { + int (*etxo_init)(efx_nic_t *); + void (*etxo_fini)(efx_nic_t *); + int (*etxo_qcreate)(efx_nic_t *, + unsigned int, unsigned int, + efsys_mem_t *, size_t, + uint32_t, uint16_t, + efx_evq_t *, efx_txq_t *, + unsigned int *); + void (*etxo_qdestroy)(efx_txq_t *); + int (*etxo_qpost)(efx_txq_t *, efx_buffer_t *, + unsigned int, unsigned int, + unsigned int *); + void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int); + int (*etxo_qpace)(efx_txq_t *, unsigned int); + int (*etxo_qflush)(efx_txq_t *); + void (*etxo_qenable)(efx_txq_t *); + int (*etxo_qpio_enable)(efx_txq_t *); + void (*etxo_qpio_disable)(efx_txq_t *); + int (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t, + size_t); + int (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int, + unsigned int *); + int (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *, + unsigned int, unsigned int, + unsigned int *); + void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t, + size_t, boolean_t, + efx_desc_t *); + void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t, + uint32_t, uint8_t, + efx_desc_t *); + void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t, + efx_desc_t *); +#if EFSYS_OPT_QSTATS + void (*etxo_qstats_update)(efx_txq_t *, + efsys_stat_t *); +#endif +} efx_tx_ops_t; + +typedef struct efx_rx_ops_s { + int (*erxo_init)(efx_nic_t *); + void (*erxo_fini)(efx_nic_t *); +#if EFSYS_OPT_RX_HDR_SPLIT + int (*erxo_hdr_split_enable)(efx_nic_t *, unsigned int, + unsigned int); +#endif +#if EFSYS_OPT_RX_SCATTER + int (*erxo_scatter_enable)(efx_nic_t *, unsigned int); +#endif +#if EFSYS_OPT_RX_SCALE + int (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t, + efx_rx_hash_type_t, boolean_t); + int (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t); + int (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *, + size_t); +#endif + void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t, + unsigned int, unsigned int, + unsigned int); + void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *); + int (*erxo_qflush)(efx_rxq_t *); + void (*erxo_qenable)(efx_rxq_t *); + int (*erxo_qcreate)(efx_nic_t *enp, unsigned int, + unsigned int, efx_rxq_type_t, + efsys_mem_t *, size_t, uint32_t, + efx_evq_t *, efx_rxq_t *); + void (*erxo_qdestroy)(efx_rxq_t *); +} efx_rx_ops_t; + typedef struct efx_mac_ops_s { int (*emo_reset)(efx_nic_t *); /* optional */ int (*emo_poll)(efx_nic_t *, efx_link_mode_t *); int (*emo_up)(efx_nic_t *, boolean_t *); + int (*emo_addr_set)(efx_nic_t *); int (*emo_reconfigure)(efx_nic_t *); + int (*emo_multicast_list_set)(efx_nic_t *); + int (*emo_filter_default_rxq_set)(efx_nic_t *, + efx_rxq_t *, boolean_t); + void (*emo_filter_default_rxq_clear)(efx_nic_t *); #if EFSYS_OPT_LOOPBACK int (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t, efx_loopback_type_t); #endif /* EFSYS_OPT_LOOPBACK */ #if EFSYS_OPT_MAC_STATS int (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *); int (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *, uint16_t, boolean_t); int (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, efsys_stat_t *, uint32_t *); #endif /* EFSYS_OPT_MAC_STATS */ } efx_mac_ops_t; typedef struct efx_phy_ops_s { int (*epo_power)(efx_nic_t *, boolean_t); /* optional */ int (*epo_reset)(efx_nic_t *); int (*epo_reconfigure)(efx_nic_t *); int (*epo_verify)(efx_nic_t *); int (*epo_uplink_check)(efx_nic_t *, boolean_t *); /* optional */ int (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *, unsigned int *, uint32_t *); int (*epo_oui_get)(efx_nic_t *, uint32_t *); #if EFSYS_OPT_PHY_STATS int (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, uint32_t *); #endif /* EFSYS_OPT_PHY_STATS */ #if EFSYS_OPT_PHY_PROPS #if EFSYS_OPT_NAMES - const char __cs *(*epo_prop_name)(efx_nic_t *, unsigned int); + const char *(*epo_prop_name)(efx_nic_t *, unsigned int); #endif /* EFSYS_OPT_PHY_PROPS */ int (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t, uint32_t *); int (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t); #endif /* EFSYS_OPT_PHY_PROPS */ -#if EFSYS_OPT_PHY_BIST - int (*epo_bist_start)(efx_nic_t *, efx_phy_bist_type_t); - int (*epo_bist_poll)(efx_nic_t *, efx_phy_bist_type_t, - efx_phy_bist_result_t *, uint32_t *, +#if EFSYS_OPT_BIST + int (*epo_bist_enable_offline)(efx_nic_t *); + int (*epo_bist_start)(efx_nic_t *, efx_bist_type_t); + int (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t, + efx_bist_result_t *, uint32_t *, unsigned long *, size_t); - void (*epo_bist_stop)(efx_nic_t *, efx_phy_bist_type_t); -#endif /* EFSYS_OPT_PHY_BIST */ + void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t); +#endif /* EFSYS_OPT_BIST */ } efx_phy_ops_t; +#if EFSYS_OPT_FILTER +typedef struct efx_filter_ops_s { + int (*efo_init)(efx_nic_t *); + void (*efo_fini)(efx_nic_t *); + int (*efo_restore)(efx_nic_t *); + int (*efo_add)(efx_nic_t *, efx_filter_spec_t *, + boolean_t may_replace); + int (*efo_delete)(efx_nic_t *, efx_filter_spec_t *); + int (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *); + int (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t, + boolean_t, boolean_t, boolean_t, + uint8_t const *, int); +} efx_filter_ops_t; + +extern __checkReturn int +efx_filter_reconfigure( + __in efx_nic_t *enp, + __in_ecount(6) uint8_t const *mac_addr, + __in boolean_t all_unicst, + __in boolean_t mulcst, + __in boolean_t all_mulcst, + __in boolean_t brdcst, + __in_ecount(6*count) uint8_t const *addrs, + __in int count); + +#endif /* EFSYS_OPT_FILTER */ + +typedef struct efx_pktfilter_ops_s { + int (*epfo_set)(efx_nic_t *, + boolean_t unicst, + boolean_t brdcast); +#if EFSYS_OPT_MCAST_FILTER_LIST + int (*epfo_mcast_list_set)(efx_nic_t *, uint8_t const *addrs, int count); +#endif /* EFSYS_OPT_MCAST_FILTER_LIST */ + int (*epfo_mcast_all)(efx_nic_t *); +} efx_pktfilter_ops_t; + typedef struct efx_port_s { efx_mac_type_t ep_mac_type; uint32_t ep_phy_type; uint8_t ep_port; uint32_t ep_mac_pdu; uint8_t ep_mac_addr[6]; efx_link_mode_t ep_link_mode; - boolean_t ep_unicst; + boolean_t ep_all_unicst; + boolean_t ep_mulcst; + boolean_t ep_all_mulcst; boolean_t ep_brdcst; unsigned int ep_fcntl; boolean_t ep_fcntl_autoneg; efx_oword_t ep_multicst_hash[2]; + uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN * + EFX_MAC_MULTICAST_LIST_MAX]; + uint32_t ep_mulcst_addr_count; #if EFSYS_OPT_LOOPBACK efx_loopback_type_t ep_loopback_type; efx_link_mode_t ep_loopback_link_mode; #endif /* EFSYS_OPT_LOOPBACK */ #if EFSYS_OPT_PHY_FLAGS uint32_t ep_phy_flags; #endif /* EFSYS_OPT_PHY_FLAGS */ #if EFSYS_OPT_PHY_LED_CONTROL efx_phy_led_mode_t ep_phy_led_mode; #endif /* EFSYS_OPT_PHY_LED_CONTROL */ efx_phy_media_type_t ep_fixed_port_type; efx_phy_media_type_t ep_module_type; uint32_t ep_adv_cap_mask; uint32_t ep_lp_cap_mask; uint32_t ep_default_adv_cap_mask; uint32_t ep_phy_cap_mask; #if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C union { struct { unsigned int bug10934_count; } ep_txc43128; struct { unsigned int bug17190_count; } ep_qt2025c; }; #endif boolean_t ep_mac_poll_needed; /* falcon only */ boolean_t ep_mac_up; /* falcon only */ uint32_t ep_fwver; /* falcon only */ boolean_t ep_mac_drain; boolean_t ep_mac_stats_pending; -#if EFSYS_OPT_PHY_BIST - efx_phy_bist_type_t ep_current_bist; +#if EFSYS_OPT_BIST + efx_bist_type_t ep_current_bist; #endif efx_mac_ops_t *ep_emop; efx_phy_ops_t *ep_epop; } efx_port_t; typedef struct efx_mon_ops_s { int (*emo_reset)(efx_nic_t *); int (*emo_reconfigure)(efx_nic_t *); #if EFSYS_OPT_MON_STATS int (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, efx_mon_stat_value_t *); #endif /* EFSYS_OPT_MON_STATS */ } efx_mon_ops_t; typedef struct efx_mon_s { efx_mon_type_t em_type; efx_mon_ops_t *em_emop; } efx_mon_t; +typedef struct efx_intr_ops_s { + int (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *); + void (*eio_enable)(efx_nic_t *); + void (*eio_disable)(efx_nic_t *); + void (*eio_disable_unlocked)(efx_nic_t *); + int (*eio_trigger)(efx_nic_t *, unsigned int); + void (*eio_fini)(efx_nic_t *); +} efx_intr_ops_t; + typedef struct efx_intr_s { - efx_intr_type_t ei_type; + efx_intr_ops_t *ei_eiop; efsys_mem_t *ei_esmp; + efx_intr_type_t ei_type; unsigned int ei_level; } efx_intr_t; typedef struct efx_nic_ops_s { int (*eno_probe)(efx_nic_t *); + int (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*); int (*eno_reset)(efx_nic_t *); int (*eno_init)(efx_nic_t *); + int (*eno_get_vi_pool)(efx_nic_t *, uint32_t *); + int (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, + uint32_t *, size_t *); #if EFSYS_OPT_DIAG int (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t); int (*eno_register_test)(efx_nic_t *); #endif /* EFSYS_OPT_DIAG */ void (*eno_fini)(efx_nic_t *); void (*eno_unprobe)(efx_nic_t *); } efx_nic_ops_t; #ifndef EFX_TXQ_LIMIT_TARGET -# define EFX_TXQ_LIMIT_TARGET 259 +#define EFX_TXQ_LIMIT_TARGET 259 #endif #ifndef EFX_RXQ_LIMIT_TARGET -# define EFX_RXQ_LIMIT_TARGET 512 +#define EFX_RXQ_LIMIT_TARGET 512 #endif #ifndef EFX_TXQ_DC_SIZE -#define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */ +#define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */ #endif #ifndef EFX_RXQ_DC_SIZE -#define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */ +#define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */ #endif #if EFSYS_OPT_FILTER -typedef enum efx_filter_type_e { - EFX_FILTER_RX_TCP_FULL, /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */ - EFX_FILTER_RX_TCP_WILD, /* TCP/IPv4 dest {dIP,dTCP, -, -} */ - EFX_FILTER_RX_UDP_FULL, /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */ - EFX_FILTER_RX_UDP_WILD, /* UDP/IPv4 dest {dIP,dUDP, -, -} */ +typedef struct falconsiena_filter_spec_s { + uint8_t fsfs_type; + uint32_t fsfs_flags; + uint32_t fsfs_dmaq_id; + uint32_t fsfs_dword[3]; +} falconsiena_filter_spec_t; +typedef enum falconsiena_filter_type_e { + EFX_FS_FILTER_RX_TCP_FULL, /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */ + EFX_FS_FILTER_RX_TCP_WILD, /* TCP/IPv4 dest {dIP,dTCP, -, -} */ + EFX_FS_FILTER_RX_UDP_FULL, /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */ + EFX_FS_FILTER_RX_UDP_WILD, /* UDP/IPv4 dest {dIP,dUDP, -, -} */ + #if EFSYS_OPT_SIENA - EFX_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */ - EFX_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */ + EFX_FS_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */ + EFX_FS_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */ - EFX_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ - EFX_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */ - EFX_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */ - EFX_FILTER_TX_UDP_WILD, /* UDP/IPv4 source (host, port) */ + EFX_FS_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ + EFX_FS_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */ + EFX_FS_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */ + EFX_FS_FILTER_TX_UDP_WILD, /* UDP/IPv4 source (host, port) */ - EFX_FILTER_TX_MAC_FULL, /* Ethernet source (MAC address, VLAN ID) */ - EFX_FILTER_TX_MAC_WILD, /* Ethernet source (MAC address) */ + EFX_FS_FILTER_TX_MAC_FULL, /* Ethernet source (MAC address, VLAN ID) */ + EFX_FS_FILTER_TX_MAC_WILD, /* Ethernet source (MAC address) */ #endif /* EFSYS_OPT_SIENA */ - EFX_FILTER_NTYPES -} efx_filter_type_t; + EFX_FS_FILTER_NTYPES +} falconsiena_filter_type_t; -typedef enum efx_filter_tbl_id_e { - EFX_FILTER_TBL_RX_IP = 0, - EFX_FILTER_TBL_RX_MAC, - EFX_FILTER_TBL_TX_IP, - EFX_FILTER_TBL_TX_MAC, - EFX_FILTER_NTBLS -} efx_filter_tbl_id_t; +typedef enum falconsiena_filter_tbl_id_e { + EFX_FS_FILTER_TBL_RX_IP = 0, + EFX_FS_FILTER_TBL_RX_MAC, + EFX_FS_FILTER_TBL_TX_IP, + EFX_FS_FILTER_TBL_TX_MAC, + EFX_FS_FILTER_NTBLS +} falconsiena_filter_tbl_id_t; -typedef struct efx_filter_tbl_s { - int eft_size; /* number of entries */ - int eft_used; /* active count */ - uint32_t *eft_bitmap; /* active bitmap */ - efx_filter_spec_t *eft_spec; /* array of saved specs */ -} efx_filter_tbl_t; +typedef struct falconsiena_filter_tbl_s { + int fsft_size; /* number of entries */ + int fsft_used; /* active count */ + uint32_t *fsft_bitmap; /* active bitmap */ + falconsiena_filter_spec_t *fsft_spec; /* array of saved specs */ +} falconsiena_filter_tbl_t; +typedef struct falconsiena_filter_s { + falconsiena_filter_tbl_t fsf_tbl[EFX_FS_FILTER_NTBLS]; + unsigned int fsf_depth[EFX_FS_FILTER_NTYPES]; +} falconsiena_filter_t; + typedef struct efx_filter_s { - efx_filter_tbl_t ef_tbl[EFX_FILTER_NTBLS]; - unsigned int ef_depth[EFX_FILTER_NTYPES]; +#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA + falconsiena_filter_t *ef_falconsiena_filter; +#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ +#if EFSYS_OPT_HUNTINGTON + hunt_filter_table_t *ef_hunt_filter_table; +#endif /* EFSYS_OPT_HUNTINGTON */ } efx_filter_t; - -extern __checkReturn int -efx_filter_insert_filter( +extern void +falconsiena_filter_tbl_clear( __in efx_nic_t *enp, - __in efx_filter_spec_t *spec, - __in boolean_t replace); + __in falconsiena_filter_tbl_id_t tbl); -extern __checkReturn int -efx_filter_remove_filter( - __in efx_nic_t *enp, - __in efx_filter_spec_t *spec); +#endif /* EFSYS_OPT_FILTER */ -extern void -efx_filter_remove_index( - __inout efx_nic_t *enp, - __in efx_filter_type_t type, - __in int filter_idx); +#if EFSYS_OPT_MCDI -extern void -efx_filter_redirect_index( - __inout efx_nic_t *enp, - __in efx_filter_type_t type, - __in int filter_index, - __in int rxq_index); +typedef struct efx_mcdi_ops_s { + int (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *); + void (*emco_request_copyin)(efx_nic_t *, efx_mcdi_req_t *, + unsigned int, boolean_t, boolean_t); + boolean_t (*emco_request_poll)(efx_nic_t *); + void (*emco_request_copyout)(efx_nic_t *, efx_mcdi_req_t *); + int (*emco_poll_reboot)(efx_nic_t *); + void (*emco_fini)(efx_nic_t *); + int (*emco_fw_update_supported)(efx_nic_t *, boolean_t *); + int (*emco_macaddr_change_supported)(efx_nic_t *, boolean_t *); +} efx_mcdi_ops_t; -extern __checkReturn int -efx_filter_clear_tbl( - __in efx_nic_t *enp, - __in efx_filter_tbl_id_t tbl); +typedef struct efx_mcdi_s { + efx_mcdi_ops_t *em_emcop; + const efx_mcdi_transport_t *em_emtp; + efx_mcdi_iface_t em_emip; +} efx_mcdi_t; -#endif /* EFSYS_OPT_FILTER */ +#endif /* EFSYS_OPT_MCDI */ #if EFSYS_OPT_NVRAM typedef struct efx_nvram_ops_s { #if EFSYS_OPT_DIAG int (*envo_test)(efx_nic_t *); #endif /* EFSYS_OPT_DIAG */ int (*envo_size)(efx_nic_t *, efx_nvram_type_t, size_t *); int (*envo_get_version)(efx_nic_t *, efx_nvram_type_t, uint32_t *, uint16_t *); int (*envo_rw_start)(efx_nic_t *, efx_nvram_type_t, size_t *); int (*envo_read_chunk)(efx_nic_t *, efx_nvram_type_t, unsigned int, caddr_t, size_t); int (*envo_erase)(efx_nic_t *, efx_nvram_type_t); int (*envo_write_chunk)(efx_nic_t *, efx_nvram_type_t, unsigned int, caddr_t, size_t); void (*envo_rw_finish)(efx_nic_t *, efx_nvram_type_t); int (*envo_set_version)(efx_nic_t *, efx_nvram_type_t, uint16_t *); } efx_nvram_ops_t; #endif /* EFSYS_OPT_NVRAM */ #if EFSYS_OPT_VPD typedef struct efx_vpd_ops_s { int (*evpdo_init)(efx_nic_t *); int (*evpdo_size)(efx_nic_t *, size_t *); int (*evpdo_read)(efx_nic_t *, caddr_t, size_t); int (*evpdo_verify)(efx_nic_t *, caddr_t, size_t); int (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t); int (*evpdo_get)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *); int (*evpdo_set)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *); int (*evpdo_next)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *, unsigned int *); int (*evpdo_write)(efx_nic_t *, caddr_t, size_t); void (*evpdo_fini)(efx_nic_t *); } efx_vpd_ops_t; #endif /* EFSYS_OPT_VPD */ +#if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM + + __checkReturn int +efx_mcdi_nvram_partitions( + __in efx_nic_t *enp, + __out_bcount(size) caddr_t data, + __in size_t size, + __out unsigned int *npartnp); + + __checkReturn int +efx_mcdi_nvram_metadata( + __in efx_nic_t *enp, + __in uint32_t partn, + __out uint32_t *subtypep, + __out_ecount(4) uint16_t version[4], + __out_bcount_opt(size) char *descp, + __in size_t size); + + __checkReturn int +efx_mcdi_nvram_info( + __in efx_nic_t *enp, + __in uint32_t partn, + __out_opt size_t *sizep, + __out_opt uint32_t *addressp, + __out_opt uint32_t *erase_sizep); + + __checkReturn int +efx_mcdi_nvram_update_start( + __in efx_nic_t *enp, + __in uint32_t partn); + + __checkReturn int +efx_mcdi_nvram_read( + __in efx_nic_t *enp, + __in uint32_t partn, + __in uint32_t offset, + __out_bcount(size) caddr_t data, + __in size_t size); + + __checkReturn int +efx_mcdi_nvram_erase( + __in efx_nic_t *enp, + __in uint32_t partn, + __in uint32_t offset, + __in size_t size); + + __checkReturn int +efx_mcdi_nvram_write( + __in efx_nic_t *enp, + __in uint32_t partn, + __in uint32_t offset, + __out_bcount(size) caddr_t data, + __in size_t size); + + __checkReturn int +efx_mcdi_nvram_update_finish( + __in efx_nic_t *enp, + __in uint32_t partn, + __in boolean_t reboot); + +#if EFSYS_OPT_DIAG + + __checkReturn int +efx_mcdi_nvram_test( + __in efx_nic_t *enp, + __in uint32_t partn); + +#endif /* EFSYS_OPT_DIAG */ + +#endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ + +typedef struct efx_drv_cfg_s { + uint32_t edc_min_vi_count; + uint32_t edc_max_vi_count; + + uint32_t edc_max_piobuf_count; + uint32_t edc_pio_alloc_size; +} efx_drv_cfg_t; + struct efx_nic_s { uint32_t en_magic; efx_family_t en_family; uint32_t en_features; efsys_identifier_t *en_esip; efsys_lock_t *en_eslp; efsys_bar_t *en_esbp; unsigned int en_mod_flags; unsigned int en_reset_flags; efx_nic_cfg_t en_nic_cfg; + efx_drv_cfg_t en_drv_cfg; efx_port_t en_port; efx_mon_t en_mon; efx_intr_t en_intr; uint32_t en_ev_qcount; uint32_t en_rx_qcount; uint32_t en_tx_qcount; efx_nic_ops_t *en_enop; + efx_ev_ops_t *en_eevop; + efx_tx_ops_t *en_etxop; + efx_rx_ops_t *en_erxop; #if EFSYS_OPT_FILTER efx_filter_t en_filter; + efx_filter_ops_t *en_efop; #endif /* EFSYS_OPT_FILTER */ + efx_pktfilter_ops_t *en_epfop; +#if EFSYS_OPT_MCDI + efx_mcdi_t en_mcdi; +#endif /* EFSYS_OPT_MCDI */ #if EFSYS_OPT_NVRAM efx_nvram_type_t en_nvram_locked; efx_nvram_ops_t *en_envop; #endif /* EFSYS_OPT_NVRAM */ #if EFSYS_OPT_VPD efx_vpd_ops_t *en_evpdop; #endif /* EFSYS_OPT_VPD */ +#if EFSYS_OPT_RX_SCALE + efx_rx_hash_support_t en_hash_support; + efx_rx_scale_support_t en_rss_support; + uint32_t en_rss_context; +#endif /* EFSYS_OPT_RX_SCALE */ + uint32_t en_vport_id; union { #if EFSYS_OPT_FALCON struct { falcon_spi_dev_t enu_fsd[FALCON_SPI_NTYPES]; falcon_i2c_t enu_fip; boolean_t enu_i2c_locked; #if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE const uint8_t *enu_forced_cfg; #endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */ uint8_t enu_mon_devid; #if EFSYS_OPT_PCIE_TUNE unsigned int enu_nlanes; #endif /* EFSYS_OPT_PCIE_TUNE */ uint16_t enu_board_rev; boolean_t enu_internal_sram; uint8_t enu_sram_num_bank; uint8_t enu_sram_bank_size; } falcon; #endif /* EFSYS_OPT_FALCON */ #if EFSYS_OPT_SIENA struct { -#if EFSYS_OPT_MCDI - efx_mcdi_iface_t enu_mip; -#endif /* EFSYS_OPT_MCDI */ #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD unsigned int enu_partn_mask; #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ #if EFSYS_OPT_VPD caddr_t enu_svpd; size_t enu_svpd_length; #endif /* EFSYS_OPT_VPD */ + int enu_unused; } siena; #endif /* EFSYS_OPT_SIENA */ +#if EFSYS_OPT_HUNTINGTON + struct { + int enu_vi_base; + int enu_vi_count; +#if EFSYS_OPT_VPD + caddr_t enu_svpd; + size_t enu_svpd_length; +#endif /* EFSYS_OPT_VPD */ + efx_piobuf_handle_t enu_piobuf_handle[HUNT_PIOBUF_NBUFS]; + uint32_t enu_piobuf_count; + uint32_t enu_pio_alloc_map[HUNT_PIOBUF_NBUFS]; + uint32_t enu_pio_write_vi_base; + /* Memory BAR mapping regions */ + uint32_t enu_uc_mem_map_offset; + size_t enu_uc_mem_map_size; + uint32_t enu_wc_mem_map_offset; + size_t enu_wc_mem_map_size; + } hunt; +#endif /* EFSYS_OPT_HUNTINGTON */ } en_u; }; #define EFX_NIC_MAGIC 0x02121996 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *, const efx_ev_callbacks_t *, void *); +typedef struct efx_evq_rxq_state_s { + unsigned int eers_rx_read_ptr; + unsigned int eers_rx_mask; +} efx_evq_rxq_state_t; + struct efx_evq_s { uint32_t ee_magic; efx_nic_t *ee_enp; unsigned int ee_index; unsigned int ee_mask; efsys_mem_t *ee_esmp; #if EFSYS_OPT_QSTATS uint32_t ee_stat[EV_NQSTATS]; #endif /* EFSYS_OPT_QSTATS */ - efx_ev_handler_t ee_handler[1 << FSF_AZ_EV_CODE_WIDTH]; + + efx_ev_handler_t ee_rx; + efx_ev_handler_t ee_tx; + efx_ev_handler_t ee_driver; + efx_ev_handler_t ee_global; + efx_ev_handler_t ee_drv_gen; +#if EFSYS_OPT_MCDI + efx_ev_handler_t ee_mcdi; +#endif /* EFSYS_OPT_MCDI */ + + efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS]; }; #define EFX_EVQ_MAGIC 0x08081997 #define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */ #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */ struct efx_rxq_s { uint32_t er_magic; efx_nic_t *er_enp; + efx_evq_t *er_eep; unsigned int er_index; + unsigned int er_label; unsigned int er_mask; efsys_mem_t *er_esmp; }; #define EFX_RXQ_MAGIC 0x15022005 struct efx_txq_s { uint32_t et_magic; efx_nic_t *et_enp; unsigned int et_index; unsigned int et_mask; efsys_mem_t *et_esmp; +#if EFSYS_OPT_HUNTINGTON + uint32_t et_pio_bufnum; + uint32_t et_pio_blknum; + uint32_t et_pio_write_offset; + uint32_t et_pio_offset; + size_t et_pio_size; +#endif #if EFSYS_OPT_QSTATS uint32_t et_stat[TX_NQSTATS]; #endif /* EFSYS_OPT_QSTATS */ }; #define EFX_TXQ_MAGIC 0x05092005 #define EFX_MAC_ADDR_COPY(_dst, _src) \ do { \ (_dst)[0] = (_src)[0]; \ (_dst)[1] = (_src)[1]; \ (_dst)[2] = (_src)[2]; \ (_dst)[3] = (_src)[3]; \ (_dst)[4] = (_src)[4]; \ (_dst)[5] = (_src)[5]; \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) +#define EFX_MAC_BROADCAST_ADDR_SET(_dst) \ + do { \ + uint16_t *_d = (uint16_t *)(_dst); \ + _d[0] = 0xffff; \ + _d[1] = 0xffff; \ + _d[2] = 0xffff; \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + #if EFSYS_OPT_CHECK_REG #define EFX_CHECK_REG(_enp, _reg) \ do { \ - const char __cs *name = #_reg; \ + const char *name = #_reg; \ char min = name[4]; \ char max = name[5]; \ char rev; \ \ switch ((_enp)->en_family) { \ case EFX_FAMILY_FALCON: \ rev = 'B'; \ break; \ \ case EFX_FAMILY_SIENA: \ rev = 'C'; \ break; \ \ + case EFX_FAMILY_HUNTINGTON: \ + rev = 'D'; \ + break; \ + \ default: \ rev = '?'; \ break; \ } \ \ EFSYS_ASSERT3S(rev, >=, min); \ EFSYS_ASSERT3S(rev, <=, max); \ \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #else #define EFX_CHECK_REG(_enp, _reg) do { \ _NOTE(CONSTANTCONDITION) \ } while(B_FALSE) #endif #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \ do { \ EFX_CHECK_REG((_enp), (_reg)); \ EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \ (_edp), (_lock)); \ EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \ uint32_t, _reg ## _OFST, \ uint32_t, (_edp)->ed_u32[0]); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \ do { \ EFX_CHECK_REG((_enp), (_reg)); \ EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \ uint32_t, _reg ## _OFST, \ uint32_t, (_edp)->ed_u32[0]); \ EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \ (_edp), (_lock)); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_BAR_READQ(_enp, _reg, _eqp) \ do { \ EFX_CHECK_REG((_enp), (_reg)); \ EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \ (_eqp)); \ EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \ uint32_t, _reg ## _OFST, \ uint32_t, (_eqp)->eq_u32[1], \ uint32_t, (_eqp)->eq_u32[0]); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \ do { \ EFX_CHECK_REG((_enp), (_reg)); \ EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \ uint32_t, _reg ## _OFST, \ uint32_t, (_eqp)->eq_u32[1], \ uint32_t, (_eqp)->eq_u32[0]); \ EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \ (_eqp)); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_BAR_READO(_enp, _reg, _eop) \ do { \ EFX_CHECK_REG((_enp), (_reg)); \ EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \ (_eop), B_TRUE); \ EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \ uint32_t, _reg ## _OFST, \ uint32_t, (_eop)->eo_u32[3], \ uint32_t, (_eop)->eo_u32[2], \ uint32_t, (_eop)->eo_u32[1], \ uint32_t, (_eop)->eo_u32[0]); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_BAR_WRITEO(_enp, _reg, _eop) \ do { \ EFX_CHECK_REG((_enp), (_reg)); \ EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \ uint32_t, _reg ## _OFST, \ uint32_t, (_eop)->eo_u32[3], \ uint32_t, (_eop)->eo_u32[2], \ uint32_t, (_eop)->eo_u32[1], \ uint32_t, (_eop)->eo_u32[0]); \ EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \ (_eop), B_TRUE); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \ do { \ EFX_CHECK_REG((_enp), (_reg)); \ EFSYS_BAR_READD((_enp)->en_esbp, \ (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ (_edp), (_lock)); \ EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \ uint32_t, (_index), \ uint32_t, _reg ## _OFST, \ uint32_t, (_edp)->ed_u32[0]); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \ do { \ EFX_CHECK_REG((_enp), (_reg)); \ EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ uint32_t, (_index), \ uint32_t, _reg ## _OFST, \ uint32_t, (_edp)->ed_u32[0]); \ EFSYS_BAR_WRITED((_enp)->en_esbp, \ (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ (_edp), (_lock)); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) +#define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \ + do { \ + EFX_CHECK_REG((_enp), (_reg)); \ + EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ + uint32_t, (_index), \ + uint32_t, _reg ## _OFST, \ + uint32_t, (_edp)->ed_u32[0]); \ + EFSYS_BAR_WRITED((_enp)->en_esbp, \ + (_reg ## _OFST + \ + (2 * sizeof (efx_dword_t)) + \ + ((_index) * _reg ## _STEP)), \ + (_edp), (_lock)); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \ do { \ EFX_CHECK_REG((_enp), (_reg)); \ EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ uint32_t, (_index), \ uint32_t, _reg ## _OFST, \ uint32_t, (_edp)->ed_u32[0]); \ EFSYS_BAR_WRITED((_enp)->en_esbp, \ (_reg ## _OFST + \ (3 * sizeof (efx_dword_t)) + \ ((_index) * _reg ## _STEP)), \ (_edp), (_lock)); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \ do { \ EFX_CHECK_REG((_enp), (_reg)); \ EFSYS_BAR_READQ((_enp)->en_esbp, \ (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ (_eqp)); \ EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \ uint32_t, (_index), \ uint32_t, _reg ## _OFST, \ uint32_t, (_eqp)->eq_u32[1], \ uint32_t, (_eqp)->eq_u32[0]); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \ do { \ EFX_CHECK_REG((_enp), (_reg)); \ EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \ uint32_t, (_index), \ uint32_t, _reg ## _OFST, \ uint32_t, (_eqp)->eq_u32[1], \ uint32_t, (_eqp)->eq_u32[0]); \ EFSYS_BAR_WRITEQ((_enp)->en_esbp, \ (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ (_eqp)); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) -#define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop) \ +#define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \ do { \ EFX_CHECK_REG((_enp), (_reg)); \ EFSYS_BAR_READO((_enp)->en_esbp, \ (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ - (_eop), B_TRUE); \ + (_eop), (_lock)); \ EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \ uint32_t, (_index), \ uint32_t, _reg ## _OFST, \ uint32_t, (_eop)->eo_u32[3], \ uint32_t, (_eop)->eo_u32[2], \ uint32_t, (_eop)->eo_u32[1], \ uint32_t, (_eop)->eo_u32[0]); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) -#define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop) \ +#define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \ do { \ EFX_CHECK_REG((_enp), (_reg)); \ EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \ uint32_t, (_index), \ uint32_t, _reg ## _OFST, \ uint32_t, (_eop)->eo_u32[3], \ uint32_t, (_eop)->eo_u32[2], \ uint32_t, (_eop)->eo_u32[1], \ uint32_t, (_eop)->eo_u32[0]); \ EFSYS_BAR_WRITEO((_enp)->en_esbp, \ (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ - (_eop), B_TRUE); \ + (_eop), (_lock)); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) +/* + * Allow drivers to perform optimised 128-bit doorbell writes. + * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are + * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid + * the need for locking in the host, and are the only ones known to be safe to + * use 128-bites write with. + */ +#define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \ + do { \ + EFX_CHECK_REG((_enp), (_reg)); \ + EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \ + const char *, \ + #_reg, \ + uint32_t, (_index), \ + uint32_t, _reg ## _OFST, \ + uint32_t, (_eop)->eo_u32[3], \ + uint32_t, (_eop)->eo_u32[2], \ + uint32_t, (_eop)->eo_u32[1], \ + uint32_t, (_eop)->eo_u32[0]); \ + EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \ + (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ + (_eop)); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \ + do { \ + unsigned int _new = (_wptr); \ + unsigned int _old = (_owptr); \ + \ + if ((_new) >= (_old)) \ + EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ + (_old) * sizeof (efx_desc_t), \ + ((_new) - (_old)) * sizeof (efx_desc_t)); \ + else \ + /* \ + * It is cheaper to sync entire map than sync \ + * two parts especially when offset/size are \ + * ignored and entire map is synced in any case.\ + */ \ + EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ + 0, \ + (_entries) * sizeof (efx_desc_t)); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + extern __checkReturn int +efx_nic_biu_test( + __in efx_nic_t *enp); + +extern __checkReturn int efx_mac_select( __in efx_nic_t *enp); +extern void +efx_mac_multicast_hash_compute( + __in_ecount(6*count) uint8_t const *addrs, + __in int count, + __out efx_oword_t *hash_low, + __out efx_oword_t *hash_high); + extern __checkReturn int efx_phy_probe( __in efx_nic_t *enp); extern void efx_phy_unprobe( __in efx_nic_t *enp); #if EFSYS_OPT_VPD /* VPD utility functions */ extern __checkReturn int efx_vpd_hunk_length( __in_bcount(size) caddr_t data, __in size_t size, __out size_t *lengthp); extern __checkReturn int efx_vpd_hunk_verify( __in_bcount(size) caddr_t data, __in size_t size, __out_opt boolean_t *cksummedp); extern __checkReturn int efx_vpd_hunk_reinit( - __in caddr_t data, + __in_bcount(size) caddr_t data, __in size_t size, __in boolean_t wantpid); extern __checkReturn int efx_vpd_hunk_get( __in_bcount(size) caddr_t data, __in size_t size, __in efx_vpd_tag_t tag, __in efx_vpd_keyword_t keyword, __out unsigned int *payloadp, __out uint8_t *paylenp); extern __checkReturn int efx_vpd_hunk_next( __in_bcount(size) caddr_t data, __in size_t size, __out efx_vpd_tag_t *tagp, __out efx_vpd_keyword_t *keyword, __out_bcount_opt(*paylenp) unsigned int *payloadp, __out_opt uint8_t *paylenp, __inout unsigned int *contp); extern __checkReturn int efx_vpd_hunk_set( __in_bcount(size) caddr_t data, __in size_t size, __in efx_vpd_value_t *evvp); #endif /* EFSYS_OPT_VPD */ #if EFSYS_OPT_DIAG -extern efx_sram_pattern_fn_t __cs __efx_sram_pattern_fns[]; +extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[]; typedef struct efx_register_set_s { unsigned int address; unsigned int step; unsigned int rows; efx_oword_t mask; } efx_register_set_t; extern __checkReturn int efx_nic_test_registers( __in efx_nic_t *enp, __in efx_register_set_t *rsp, __in size_t count); extern __checkReturn int efx_nic_test_tables( __in efx_nic_t *enp, __in efx_register_set_t *rsp, __in efx_pattern_type_t pattern, __in size_t count); #endif /* EFSYS_OPT_DIAG */ + +#if EFSYS_OPT_MCDI + +extern __checkReturn int +efx_mcdi_set_workaround( + __in efx_nic_t *enp, + __in uint32_t type, + __in boolean_t enabled, + __out_opt uint32_t *flagsp); + +extern __checkReturn int +efx_mcdi_get_workarounds( + __in efx_nic_t *enp, + __out_opt uint32_t *implementedp, + __out_opt uint32_t *enabledp); + +#endif /* EFSYS_OPT_MCDI */ #ifdef __cplusplus } #endif #endif /* _SYS_EFX_IMPL_H */ Property changes on: head/sys/dev/sfxge/common/efx_impl.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_intr.c =================================================================== --- head/sys/dev/sfxge/common/efx_intr.c (revision 283513) +++ head/sys/dev/sfxge/common/efx_intr.c (revision 283514) @@ -1,357 +1,579 @@ /*- - * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2007-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include "efsys.h" #include "efx.h" #include "efx_types.h" #include "efx_regs.h" #include "efx_impl.h" + +#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA + +static __checkReturn int +falconsiena_intr_init( + __in efx_nic_t *enp, + __in efx_intr_type_t type, + __in efsys_mem_t *esmp); + +static void +falconsiena_intr_enable( + __in efx_nic_t *enp); + +static void +falconsiena_intr_disable( + __in efx_nic_t *enp); + +static void +falconsiena_intr_disable_unlocked( + __in efx_nic_t *enp); + +static __checkReturn int +falconsiena_intr_trigger( + __in efx_nic_t *enp, + __in unsigned int level); + +static void +falconsiena_intr_fini( + __in efx_nic_t *enp); + + +static __checkReturn boolean_t +falconsiena_intr_check_fatal( + __in efx_nic_t *enp); + +static void +falconsiena_intr_fatal( + __in efx_nic_t *enp); + +#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ + + +#if EFSYS_OPT_FALCON +static efx_intr_ops_t __efx_intr_falcon_ops = { + falconsiena_intr_init, /* eio_init */ + falconsiena_intr_enable, /* eio_enable */ + falconsiena_intr_disable, /* eio_disable */ + falconsiena_intr_disable_unlocked, /* eio_disable_unlocked */ + falconsiena_intr_trigger, /* eio_trigger */ + falconsiena_intr_fini, /* eio_fini */ +}; +#endif /* EFSYS_OPT_FALCON */ + +#if EFSYS_OPT_SIENA +static efx_intr_ops_t __efx_intr_siena_ops = { + falconsiena_intr_init, /* eio_init */ + falconsiena_intr_enable, /* eio_enable */ + falconsiena_intr_disable, /* eio_disable */ + falconsiena_intr_disable_unlocked, /* eio_disable_unlocked */ + falconsiena_intr_trigger, /* eio_trigger */ + falconsiena_intr_fini, /* eio_fini */ +}; +#endif /* EFSYS_OPT_SIENA */ + +#if EFSYS_OPT_HUNTINGTON +static efx_intr_ops_t __efx_intr_hunt_ops = { + hunt_intr_init, /* eio_init */ + hunt_intr_enable, /* eio_enable */ + hunt_intr_disable, /* eio_disable */ + hunt_intr_disable_unlocked, /* eio_disable_unlocked */ + hunt_intr_trigger, /* eio_trigger */ + hunt_intr_fini, /* eio_fini */ +}; +#endif /* EFSYS_OPT_HUNTINGTON */ + + __checkReturn int efx_intr_init( __in efx_nic_t *enp, __in efx_intr_type_t type, __in efsys_mem_t *esmp) { efx_intr_t *eip = &(enp->en_intr); - efx_oword_t oword; + efx_intr_ops_t *eiop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); if (enp->en_mod_flags & EFX_MOD_INTR) { rc = EINVAL; goto fail1; } + eip->ei_esmp = esmp; + eip->ei_type = type; + eip->ei_level = 0; + enp->en_mod_flags |= EFX_MOD_INTR; - eip->ei_type = type; - eip->ei_esmp = esmp; + switch (enp->en_family) { +#if EFSYS_OPT_FALCON + case EFX_FAMILY_FALCON: + eiop = (efx_intr_ops_t *)&__efx_intr_falcon_ops; + break; +#endif /* EFSYS_OPT_FALCON */ +#if EFSYS_OPT_SIENA + case EFX_FAMILY_SIENA: + eiop = (efx_intr_ops_t *)&__efx_intr_siena_ops; + break; +#endif /* EFSYS_OPT_SIENA */ + +#if EFSYS_OPT_HUNTINGTON + case EFX_FAMILY_HUNTINGTON: + eiop = (efx_intr_ops_t *)&__efx_intr_hunt_ops; + break; +#endif /* EFSYS_OPT_HUNTINGTON */ + + default: + EFSYS_ASSERT(B_FALSE); + rc = ENOTSUP; + goto fail2; + } + + if ((rc = eiop->eio_init(enp, type, esmp)) != 0) + goto fail3; + + eip->ei_eiop = eiop; + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + void +efx_intr_fini( + __in efx_nic_t *enp) +{ + efx_intr_t *eip = &(enp->en_intr); + efx_intr_ops_t *eiop = eip->ei_eiop; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); + + eiop->eio_fini(enp); + + enp->en_mod_flags &= ~EFX_MOD_INTR; +} + + void +efx_intr_enable( + __in efx_nic_t *enp) +{ + efx_intr_t *eip = &(enp->en_intr); + efx_intr_ops_t *eiop = eip->ei_eiop; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); + + eiop->eio_enable(enp); +} + + void +efx_intr_disable( + __in efx_nic_t *enp) +{ + efx_intr_t *eip = &(enp->en_intr); + efx_intr_ops_t *eiop = eip->ei_eiop; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); + + eiop->eio_disable(enp); +} + + void +efx_intr_disable_unlocked( + __in efx_nic_t *enp) +{ + efx_intr_t *eip = &(enp->en_intr); + efx_intr_ops_t *eiop = eip->ei_eiop; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); + + eiop->eio_disable_unlocked(enp); +} + + + __checkReturn int +efx_intr_trigger( + __in efx_nic_t *enp, + __in unsigned int level) +{ + efx_intr_t *eip = &(enp->en_intr); + efx_intr_ops_t *eiop = eip->ei_eiop; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); + + return (eiop->eio_trigger(enp, level)); +} + + void +efx_intr_status_line( + __in efx_nic_t *enp, + __out boolean_t *fatalp, + __out uint32_t *qmaskp) +{ + efx_intr_t *eip = &(enp->en_intr); + efx_dword_t dword; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); + + /* Ensure Huntington and Falcon/Siena ISR at same location */ + EFX_STATIC_ASSERT(FR_BZ_INT_ISR0_REG_OFST == + ER_DZ_BIU_INT_ISR_REG_OFST); + /* + * Read the queue mask and implicitly acknowledge the + * interrupt. + */ + EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE); + *qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0); + + EFSYS_PROBE1(qmask, uint32_t, *qmaskp); + +#if EFSYS_OPT_HUNTINGTON + if (enp->en_family == EFX_FAMILY_HUNTINGTON) { + /* Huntington reports fatal errors via events */ + *fatalp = B_FALSE; + return; + } +#endif + if (*qmaskp & (1U << eip->ei_level)) + *fatalp = falconsiena_intr_check_fatal(enp); + else + *fatalp = B_FALSE; +} + + void +efx_intr_status_message( + __in efx_nic_t *enp, + __in unsigned int message, + __out boolean_t *fatalp) +{ + efx_intr_t *eip = &(enp->en_intr); + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); + +#if EFSYS_OPT_HUNTINGTON + if (enp->en_family == EFX_FAMILY_HUNTINGTON) { + /* Huntington reports fatal errors via events */ + *fatalp = B_FALSE; + return; + } +#endif + if (message == eip->ei_level) + *fatalp = falconsiena_intr_check_fatal(enp); + else + *fatalp = B_FALSE; +} + + void +efx_intr_fatal( + __in efx_nic_t *enp) +{ + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); + +#if EFSYS_OPT_HUNTINGTON + if (enp->en_family == EFX_FAMILY_HUNTINGTON) { + /* Huntington reports fatal errors via events */ + return; + } +#endif +#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA + falconsiena_intr_fatal(enp); +#endif +} + + +/* ************************************************************************* */ +/* ************************************************************************* */ +/* ************************************************************************* */ + +#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA + +static __checkReturn int +falconsiena_intr_init( + __in efx_nic_t *enp, + __in efx_intr_type_t type, + __in efsys_mem_t *esmp) +{ + efx_intr_t *eip = &(enp->en_intr); + efx_oword_t oword; + + /* * bug17213 workaround. * * Under legacy interrupts, don't share a level between fatal * interrupts and event queue interrupts. Under MSI-X, they * must share, or we won't get an interrupt. */ if (enp->en_family == EFX_FAMILY_SIENA && eip->ei_type == EFX_INTR_LINE) eip->ei_level = 0x1f; else eip->ei_level = 0; /* Enable all the genuinely fatal interrupts */ EFX_SET_OWORD(oword); EFX_SET_OWORD_FIELD(oword, FRF_AZ_ILL_ADR_INT_KER_EN, 0); EFX_SET_OWORD_FIELD(oword, FRF_AZ_RBUF_OWN_INT_KER_EN, 0); EFX_SET_OWORD_FIELD(oword, FRF_AZ_TBUF_OWN_INT_KER_EN, 0); if (enp->en_family >= EFX_FAMILY_SIENA) EFX_SET_OWORD_FIELD(oword, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 0); EFX_BAR_WRITEO(enp, FR_AZ_FATAL_INTR_REG_KER, &oword); /* Set up the interrupt address register */ EFX_POPULATE_OWORD_3(oword, FRF_AZ_NORM_INT_VEC_DIS_KER, (type == EFX_INTR_MESSAGE) ? 1 : 0, FRF_AZ_INT_ADR_KER_DW0, EFSYS_MEM_ADDR(esmp) & 0xffffffff, FRF_AZ_INT_ADR_KER_DW1, EFSYS_MEM_ADDR(esmp) >> 32); EFX_BAR_WRITEO(enp, FR_AZ_INT_ADR_REG_KER, &oword); return (0); - -fail1: - EFSYS_PROBE1(fail1, int, rc); - - return (rc); } - void -efx_intr_enable( +static void +falconsiena_intr_enable( __in efx_nic_t *enp) { efx_intr_t *eip = &(enp->en_intr); efx_oword_t oword; - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); - EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword); EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, eip->ei_level); EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 1); EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword); } - void -efx_intr_disable( +static void +falconsiena_intr_disable( __in efx_nic_t *enp) { efx_oword_t oword; - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); - EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword); EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0); EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword); EFSYS_SPIN(10); } - void -efx_intr_disable_unlocked( +static void +falconsiena_intr_disable_unlocked( __in efx_nic_t *enp) { efx_oword_t oword; - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); - EFSYS_BAR_READO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST, &oword, B_FALSE); EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0); EFSYS_BAR_WRITEO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST, &oword, B_FALSE); } - __checkReturn int -efx_intr_trigger( +static __checkReturn int +falconsiena_intr_trigger( __in efx_nic_t *enp, __in unsigned int level) { efx_intr_t *eip = &(enp->en_intr); efx_oword_t oword; unsigned int count; uint32_t sel; int rc; - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); - /* bug16757: No event queues can be initialized */ EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV)); switch (enp->en_family) { case EFX_FAMILY_FALCON: - if (level > EFX_NINTR_FALCON) { + if (level >= EFX_NINTR_FALCON) { rc = EINVAL; goto fail1; } break; case EFX_FAMILY_SIENA: - if (level > EFX_NINTR_SIENA) { + if (level >= EFX_NINTR_SIENA) { rc = EINVAL; goto fail1; } break; default: EFSYS_ASSERT(B_FALSE); break; } if (level > EFX_MASK32(FRF_AZ_KER_INT_LEVE_SEL)) return (ENOTSUP); /* avoid EFSYS_PROBE() */ sel = level; /* Trigger a test interrupt */ EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword); EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, sel); EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_KER, 1); EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword); /* * Wait up to 100ms for the interrupt to be raised before restoring * KER_INT_LEVE_SEL. Ignore a failure to raise (the caller will * observe this soon enough anyway), but always reset KER_INT_LEVE_SEL */ count = 0; do { EFSYS_SPIN(100); /* 100us */ EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword); } while (EFX_OWORD_FIELD(oword, FRF_AZ_KER_INT_KER) && ++count < 1000); EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, eip->ei_level); EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword); return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } static __checkReturn boolean_t -efx_intr_check_fatal( +falconsiena_intr_check_fatal( __in efx_nic_t *enp) { efx_intr_t *eip = &(enp->en_intr); efsys_mem_t *esmp = eip->ei_esmp; efx_oword_t oword; /* Read the syndrome */ EFSYS_MEM_READO(esmp, 0, &oword); if (EFX_OWORD_FIELD(oword, FSF_AZ_NET_IVEC_FATAL_INT) != 0) { EFSYS_PROBE(fatal); /* Clear the fatal interrupt condition */ EFX_SET_OWORD_FIELD(oword, FSF_AZ_NET_IVEC_FATAL_INT, 0); EFSYS_MEM_WRITEO(esmp, 0, &oword); return (B_TRUE); } return (B_FALSE); } - void -efx_intr_status_line( - __in efx_nic_t *enp, - __out boolean_t *fatalp, - __out uint32_t *qmaskp) -{ - efx_intr_t *eip = &(enp->en_intr); - efx_dword_t dword; - - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); - - /* - * Read the queue mask and implicitly acknowledge the - * interrupt. - */ - EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE); - *qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0); - - EFSYS_PROBE1(qmask, uint32_t, *qmaskp); - - if (*qmaskp & (1U << eip->ei_level)) - *fatalp = efx_intr_check_fatal(enp); - else - *fatalp = B_FALSE; -} - - void -efx_intr_status_message( - __in efx_nic_t *enp, - __in unsigned int message, - __out boolean_t *fatalp) -{ - efx_intr_t *eip = &(enp->en_intr); - - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); - - if (message == eip->ei_level) - *fatalp = efx_intr_check_fatal(enp); - else - *fatalp = B_FALSE; -} - - void -efx_intr_fatal( +static void +falconsiena_intr_fatal( __in efx_nic_t *enp) { #if EFSYS_OPT_DECODE_INTR_FATAL efx_oword_t fatal; efx_oword_t mem_per; - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); - EFX_BAR_READO(enp, FR_AZ_FATAL_INTR_REG_KER, &fatal); EFX_ZERO_OWORD(mem_per); if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRM_PERR_INT_KER) != 0 || EFX_OWORD_FIELD(fatal, FRF_AZ_MEM_PERR_INT_KER) != 0) EFX_BAR_READO(enp, FR_AZ_MEM_STAT_REG, &mem_per); if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRAM_OOB_INT_KER) != 0) EFSYS_ERR(enp->en_esip, EFX_ERR_SRAM_OOB, 0, 0); if (EFX_OWORD_FIELD(fatal, FRF_AZ_BUFID_DC_OOB_INT_KER) != 0) EFSYS_ERR(enp->en_esip, EFX_ERR_BUFID_DC_OOB, 0, 0); if (EFX_OWORD_FIELD(fatal, FRF_AZ_MEM_PERR_INT_KER) != 0) EFSYS_ERR(enp->en_esip, EFX_ERR_MEM_PERR, EFX_OWORD_FIELD(mem_per, EFX_DWORD_0), EFX_OWORD_FIELD(mem_per, EFX_DWORD_1)); if (EFX_OWORD_FIELD(fatal, FRF_AZ_RBUF_OWN_INT_KER) != 0) EFSYS_ERR(enp->en_esip, EFX_ERR_RBUF_OWN, 0, 0); if (EFX_OWORD_FIELD(fatal, FRF_AZ_TBUF_OWN_INT_KER) != 0) EFSYS_ERR(enp->en_esip, EFX_ERR_TBUF_OWN, 0, 0); if (EFX_OWORD_FIELD(fatal, FRF_AZ_RDESCQ_OWN_INT_KER) != 0) EFSYS_ERR(enp->en_esip, EFX_ERR_RDESQ_OWN, 0, 0); if (EFX_OWORD_FIELD(fatal, FRF_AZ_TDESCQ_OWN_INT_KER) != 0) EFSYS_ERR(enp->en_esip, EFX_ERR_TDESQ_OWN, 0, 0); if (EFX_OWORD_FIELD(fatal, FRF_AZ_EVQ_OWN_INT_KER) != 0) EFSYS_ERR(enp->en_esip, EFX_ERR_EVQ_OWN, 0, 0); if (EFX_OWORD_FIELD(fatal, FRF_AZ_EVF_OFLO_INT_KER) != 0) EFSYS_ERR(enp->en_esip, EFX_ERR_EVFF_OFLO, 0, 0); if (EFX_OWORD_FIELD(fatal, FRF_AZ_ILL_ADR_INT_KER) != 0) EFSYS_ERR(enp->en_esip, EFX_ERR_ILL_ADDR, 0, 0); if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRM_PERR_INT_KER) != 0) EFSYS_ERR(enp->en_esip, EFX_ERR_SRAM_PERR, EFX_OWORD_FIELD(mem_per, EFX_DWORD_0), EFX_OWORD_FIELD(mem_per, EFX_DWORD_1)); #else EFSYS_ASSERT(0); #endif } - void -efx_intr_fini( +static void +falconsiena_intr_fini( __in efx_nic_t *enp) { efx_oword_t oword; - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); - /* Clear the interrupt address register */ EFX_ZERO_OWORD(oword); EFX_BAR_WRITEO(enp, FR_AZ_INT_ADR_REG_KER, &oword); - - enp->en_mod_flags &= ~EFX_MOD_INTR; } + +#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ Property changes on: head/sys/dev/sfxge/common/efx_intr.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_mac.c =================================================================== --- head/sys/dev/sfxge/common/efx_mac.c (revision 283513) +++ head/sys/dev/sfxge/common/efx_mac.c (revision 283514) @@ -1,687 +1,978 @@ /*- - * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2007-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include "efsys.h" #include "efx.h" #include "efx_types.h" #include "efx_impl.h" #if EFSYS_OPT_MAC_FALCON_GMAC #include "falcon_gmac.h" #endif #if EFSYS_OPT_MAC_FALCON_XMAC #include "falcon_xmac.h" #endif +#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA + +static __checkReturn int +falconsiena_mac_multicast_list_set( + __in efx_nic_t *enp); + +#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ + #if EFSYS_OPT_MAC_FALCON_GMAC -static efx_mac_ops_t __cs __efx_falcon_gmac_ops = { - falcon_gmac_reset, /* emo_reset */ - falcon_mac_poll, /* emo_poll */ - falcon_mac_up, /* emo_up */ - falcon_gmac_reconfigure, /* emo_reconfigure */ +static efx_mac_ops_t __efx_falcon_gmac_ops = { + falcon_gmac_reset, /* emo_reset */ + falcon_mac_poll, /* emo_poll */ + falcon_mac_up, /* emo_up */ + falcon_gmac_reconfigure, /* emo_addr_set */ + falcon_gmac_reconfigure, /* emo_reconfigure */ + falconsiena_mac_multicast_list_set, /* emo_multicast_list_set */ + NULL, /* emo_filter_set_default_rxq */ + NULL, /* emo_filter_default_rxq_clear */ #if EFSYS_OPT_LOOPBACK - falcon_mac_loopback_set, /* emo_loopback_set */ + falcon_mac_loopback_set, /* emo_loopback_set */ #endif /* EFSYS_OPT_LOOPBACK */ #if EFSYS_OPT_MAC_STATS - falcon_mac_stats_upload, /* emo_stats_upload */ - NULL, /* emo_stats_periodic */ - falcon_gmac_stats_update /* emo_stats_update */ + falcon_mac_stats_upload, /* emo_stats_upload */ + NULL, /* emo_stats_periodic */ + falcon_gmac_stats_update /* emo_stats_update */ #endif /* EFSYS_OPT_MAC_STATS */ }; #endif /* EFSYS_OPT_MAC_FALCON_GMAC */ #if EFSYS_OPT_MAC_FALCON_XMAC -static efx_mac_ops_t __cs __efx_falcon_xmac_ops = { - falcon_xmac_reset, /* emo_reset */ - falcon_mac_poll, /* emo_poll */ - falcon_mac_up, /* emo_up */ - falcon_xmac_reconfigure, /* emo_reconfigure */ +static efx_mac_ops_t __efx_falcon_xmac_ops = { + falcon_xmac_reset, /* emo_reset */ + falcon_mac_poll, /* emo_poll */ + falcon_mac_up, /* emo_up */ + falcon_xmac_reconfigure, /* emo_addr_set */ + falcon_xmac_reconfigure, /* emo_reconfigure */ + falconsiena_mac_multicast_list_set, /* emo_multicast_list_set */ + NULL, /* emo_filter_set_default_rxq */ + NULL, /* emo_filter_default_rxq_clear */ #if EFSYS_OPT_LOOPBACK - falcon_mac_loopback_set, /* emo_loopback_set */ + falcon_mac_loopback_set, /* emo_loopback_set */ #endif /* EFSYS_OPT_LOOPBACK */ #if EFSYS_OPT_MAC_STATS - falcon_mac_stats_upload, /* emo_stats_upload */ - NULL, /* emo_stats_periodic */ - falcon_xmac_stats_update /* emo_stats_update */ + falcon_mac_stats_upload, /* emo_stats_upload */ + NULL, /* emo_stats_periodic */ + falcon_xmac_stats_update /* emo_stats_update */ #endif /* EFSYS_OPT_MAC_STATS */ }; #endif /* EFSYS_OPT_MAC_FALCON_XMAC */ #if EFSYS_OPT_SIENA -static efx_mac_ops_t __cs __efx_siena_mac_ops = { - NULL, /* emo_reset */ - siena_mac_poll, /* emo_poll */ - siena_mac_up, /* emo_up */ - siena_mac_reconfigure, /* emo_reconfigure */ +static efx_mac_ops_t __efx_siena_mac_ops = { + NULL, /* emo_reset */ + siena_mac_poll, /* emo_poll */ + siena_mac_up, /* emo_up */ + siena_mac_reconfigure, /* emo_addr_set */ + siena_mac_reconfigure, /* emo_reconfigure */ + falconsiena_mac_multicast_list_set, /* emo_multicast_list_set */ + NULL, /* emo_filter_set_default_rxq */ + NULL, /* emo_filter_default_rxq_clear */ #if EFSYS_OPT_LOOPBACK - siena_mac_loopback_set, /* emo_loopback_set */ + siena_mac_loopback_set, /* emo_loopback_set */ #endif /* EFSYS_OPT_LOOPBACK */ #if EFSYS_OPT_MAC_STATS - siena_mac_stats_upload, /* emo_stats_upload */ - siena_mac_stats_periodic, /* emo_stats_periodic */ - siena_mac_stats_update /* emo_stats_update */ + efx_mcdi_mac_stats_upload, /* emo_stats_upload */ + efx_mcdi_mac_stats_periodic, /* emo_stats_periodic */ + siena_mac_stats_update /* emo_stats_update */ #endif /* EFSYS_OPT_MAC_STATS */ }; #endif /* EFSYS_OPT_SIENA */ -static efx_mac_ops_t __cs * __cs __efx_mac_ops[] = { +#if EFSYS_OPT_HUNTINGTON +static efx_mac_ops_t __efx_hunt_mac_ops = { + NULL, /* emo_reset */ + hunt_mac_poll, /* emo_poll */ + hunt_mac_up, /* emo_up */ + hunt_mac_addr_set, /* emo_addr_set */ + hunt_mac_reconfigure, /* emo_reconfigure */ + hunt_mac_multicast_list_set, /* emo_multicast_list_set */ + hunt_mac_filter_default_rxq_set, /* emo_filter_default_rxq_set */ + hunt_mac_filter_default_rxq_clear, + /* emo_filter_default_rxq_clear */ +#if EFSYS_OPT_LOOPBACK + hunt_mac_loopback_set, /* emo_loopback_set */ +#endif /* EFSYS_OPT_LOOPBACK */ +#if EFSYS_OPT_MAC_STATS + efx_mcdi_mac_stats_upload, /* emo_stats_upload */ + efx_mcdi_mac_stats_periodic, /* emo_stats_periodic */ + hunt_mac_stats_update /* emo_stats_update */ +#endif /* EFSYS_OPT_MAC_STATS */ +}; +#endif /* EFSYS_OPT_HUNTINGTON */ + +static efx_mac_ops_t *__efx_mac_ops[] = { + /* [EFX_MAC_INVALID] */ NULL, + /* [EFX_MAC_FALCON_GMAC] */ #if EFSYS_OPT_MAC_FALCON_GMAC &__efx_falcon_gmac_ops, #else NULL, -#endif /* EFSYS_OPT_MAC_FALCON_GMAC */ +#endif + /* [EFX_MAC_FALCON_XMAC] */ #if EFSYS_OPT_MAC_FALCON_XMAC &__efx_falcon_xmac_ops, #else NULL, -#endif /* EFSYS_OPT_MAC_FALCON_XMAC */ +#endif + /* [EFX_MAC_SIENA] */ #if EFSYS_OPT_SIENA &__efx_siena_mac_ops, #else NULL, -#endif /* EFSYS_OPT_SIENA */ +#endif + /* [EFX_MAC_HUNTINGTON] */ +#if EFSYS_OPT_HUNTINGTON + &__efx_hunt_mac_ops, +#else + NULL, +#endif }; __checkReturn int efx_mac_pdu_set( __in efx_nic_t *enp, __in size_t pdu) { efx_port_t *epp = &(enp->en_port); efx_mac_ops_t *emop = epp->ep_emop; uint32_t old_pdu; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); EFSYS_ASSERT(emop != NULL); if (pdu < EFX_MAC_PDU_MIN) { rc = EINVAL; goto fail1; } if (pdu > EFX_MAC_PDU_MAX) { rc = EINVAL; goto fail2; } old_pdu = epp->ep_mac_pdu; epp->ep_mac_pdu = (uint32_t)pdu; if ((rc = emop->emo_reconfigure(enp)) != 0) goto fail3; return (0); fail3: EFSYS_PROBE(fail3); epp->ep_mac_pdu = old_pdu; fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_mac_addr_set( __in efx_nic_t *enp, __in uint8_t *addr) { efx_port_t *epp = &(enp->en_port); efx_mac_ops_t *emop = epp->ep_emop; uint8_t old_addr[6]; uint32_t oui; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); - if (addr[0] & 0x01) { + if (EFX_MAC_ADDR_IS_MULTICAST(addr)) { rc = EINVAL; goto fail1; } oui = addr[0] << 16 | addr[1] << 8 | addr[2]; if (oui == 0x000000) { rc = EINVAL; goto fail2; } EFX_MAC_ADDR_COPY(old_addr, epp->ep_mac_addr); EFX_MAC_ADDR_COPY(epp->ep_mac_addr, addr); - if ((rc = emop->emo_reconfigure(enp)) != 0) + if ((rc = emop->emo_addr_set(enp)) != 0) goto fail3; return (0); fail3: EFSYS_PROBE(fail3); EFX_MAC_ADDR_COPY(epp->ep_mac_addr, old_addr); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_mac_filter_set( __in efx_nic_t *enp, - __in boolean_t unicst, + __in boolean_t all_unicst, + __in boolean_t mulcst, + __in boolean_t all_mulcst, __in boolean_t brdcst) { efx_port_t *epp = &(enp->en_port); efx_mac_ops_t *emop = epp->ep_emop; - boolean_t old_unicst; + boolean_t old_all_unicst; + boolean_t old_mulcst; + boolean_t old_all_mulcst; boolean_t old_brdcst; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); - old_unicst = unicst; - old_brdcst = brdcst; + old_all_unicst = epp->ep_all_unicst; + old_mulcst = epp->ep_mulcst; + old_all_mulcst = epp->ep_all_mulcst; + old_brdcst = epp->ep_brdcst; - epp->ep_unicst = unicst; + epp->ep_all_unicst = all_unicst; + epp->ep_mulcst = mulcst; + epp->ep_all_mulcst = all_mulcst; epp->ep_brdcst = brdcst; if ((rc = emop->emo_reconfigure(enp)) != 0) goto fail1; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); - epp->ep_unicst = old_unicst; + epp->ep_all_unicst = old_all_unicst; + epp->ep_mulcst = old_mulcst; + epp->ep_all_mulcst = old_all_mulcst; epp->ep_brdcst = old_brdcst; return (rc); } __checkReturn int efx_mac_drain( __in efx_nic_t *enp, __in boolean_t enabled) { efx_port_t *epp = &(enp->en_port); efx_mac_ops_t *emop = epp->ep_emop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); EFSYS_ASSERT(emop != NULL); if (epp->ep_mac_drain == enabled) return (0); epp->ep_mac_drain = enabled; if (enabled && emop->emo_reset != NULL) { if ((rc = emop->emo_reset(enp)) != 0) goto fail1; EFSYS_ASSERT(enp->en_reset_flags & EFX_RESET_MAC); enp->en_reset_flags &= ~EFX_RESET_PHY; } if ((rc = emop->emo_reconfigure(enp)) != 0) goto fail2; return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_mac_up( __in efx_nic_t *enp, __out boolean_t *mac_upp) { efx_port_t *epp = &(enp->en_port); efx_mac_ops_t *emop = epp->ep_emop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); if ((rc = emop->emo_up(enp, mac_upp)) != 0) goto fail1; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_mac_fcntl_set( __in efx_nic_t *enp, __in unsigned int fcntl, __in boolean_t autoneg) { efx_port_t *epp = &(enp->en_port); efx_mac_ops_t *emop = epp->ep_emop; efx_phy_ops_t *epop = epp->ep_epop; unsigned int old_fcntl; boolean_t old_autoneg; unsigned int old_adv_cap; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); if ((fcntl & ~(EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE)) != 0) { rc = EINVAL; goto fail1; } /* - * Ignore a request to set flow control autonegotiation + * Ignore a request to set flow control auto-negotiation * if the PHY doesn't support it. */ if (~epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN)) autoneg = B_FALSE; old_fcntl = epp->ep_fcntl; - old_autoneg = autoneg; + old_autoneg = epp->ep_fcntl_autoneg; old_adv_cap = epp->ep_adv_cap_mask; epp->ep_fcntl = fcntl; epp->ep_fcntl_autoneg = autoneg; /* - * If the PHY supports autonegotiation, then encode the flow control - * settings in the advertised capabilities, and restart AN. Otherwise, - * just push the new settings directly to the MAC. + * Always encode the flow control settings in the advertised + * capabilities even if we are not trying to auto-negotiate + * them and reconfigure both the PHY and the MAC. */ - if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN)) { - if (fcntl & EFX_FCNTL_RESPOND) - epp->ep_adv_cap_mask |= (1 << EFX_PHY_CAP_PAUSE | - 1 << EFX_PHY_CAP_ASYM); - else - epp->ep_adv_cap_mask &= ~(1 << EFX_PHY_CAP_PAUSE | - 1 << EFX_PHY_CAP_ASYM); + if (fcntl & EFX_FCNTL_RESPOND) + epp->ep_adv_cap_mask |= (1 << EFX_PHY_CAP_PAUSE | + 1 << EFX_PHY_CAP_ASYM); + else + epp->ep_adv_cap_mask &= ~(1 << EFX_PHY_CAP_PAUSE | + 1 << EFX_PHY_CAP_ASYM); - if (fcntl & EFX_FCNTL_GENERATE) - epp->ep_adv_cap_mask ^= (1 << EFX_PHY_CAP_ASYM); + if (fcntl & EFX_FCNTL_GENERATE) + epp->ep_adv_cap_mask ^= (1 << EFX_PHY_CAP_ASYM); - if ((rc = epop->epo_reconfigure(enp)) != 0) - goto fail2; + if ((rc = epop->epo_reconfigure(enp)) != 0) + goto fail2; - } else { - if ((rc = emop->emo_reconfigure(enp)) != 0) - goto fail2; - } + if ((rc = emop->emo_reconfigure(enp)) != 0) + goto fail3; return (0); +fail3: + EFSYS_PROBE(fail3); + fail2: EFSYS_PROBE(fail2); epp->ep_fcntl = old_fcntl; epp->ep_fcntl_autoneg = old_autoneg; epp->ep_adv_cap_mask = old_adv_cap; fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } void efx_mac_fcntl_get( __in efx_nic_t *enp, __out unsigned int *fcntl_wantedp, __out unsigned int *fcntl_linkp) { efx_port_t *epp = &(enp->en_port); - unsigned int wanted; + unsigned int wanted = 0; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); /* - * If the PHY supports auto negotiation, then the requested flow - * control settings are encoded in the advertised capabilities. + * Decode the requested flow control settings from the PHY + * advertised capabilities. */ - if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN)) { - wanted = 0; + if (epp->ep_adv_cap_mask & (1 << EFX_PHY_CAP_PAUSE)) + wanted = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE; + if (epp->ep_adv_cap_mask & (1 << EFX_PHY_CAP_ASYM)) + wanted ^= EFX_FCNTL_GENERATE; - if (epp->ep_adv_cap_mask & (1 << EFX_PHY_CAP_PAUSE)) - wanted = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE; - if (epp->ep_adv_cap_mask & (1 << EFX_PHY_CAP_ASYM)) - wanted ^= EFX_FCNTL_GENERATE; - } else - wanted = epp->ep_fcntl; - *fcntl_linkp = epp->ep_fcntl; *fcntl_wantedp = wanted; } +/* + * FIXME: efx_mac_hash_set() should be deleted once all its callers have been + * updated to use efx_mac_multicast_list_set(). + * Then efx_port_t.ep_multicst_hash could be made Falcon/Siena specific as + * well. + */ __checkReturn int efx_mac_hash_set( __in efx_nic_t *enp, __in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket) { efx_port_t *epp = &(enp->en_port); efx_mac_ops_t *emop = epp->ep_emop; efx_oword_t old_hash[2]; unsigned int index; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); memcpy(old_hash, epp->ep_multicst_hash, sizeof (old_hash)); /* Set the lower 128 bits of the hash */ EFX_ZERO_OWORD(epp->ep_multicst_hash[0]); for (index = 0; index < 128; index++) { if (bucket[index] != 0) EFX_SET_OWORD_BIT(epp->ep_multicst_hash[0], index); } /* Set the upper 128 bits of the hash */ EFX_ZERO_OWORD(epp->ep_multicst_hash[1]); for (index = 0; index < 128; index++) { if (bucket[index + 128] != 0) EFX_SET_OWORD_BIT(epp->ep_multicst_hash[1], index); } if ((rc = emop->emo_reconfigure(enp)) != 0) goto fail1; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); memcpy(epp->ep_multicst_hash, old_hash, sizeof (old_hash)); return (rc); } + __checkReturn int +efx_mac_multicast_list_set( + __in efx_nic_t *enp, + __in_ecount(6*count) uint8_t const *addrs, + __in int count) +{ + efx_port_t *epp = &(enp->en_port); + efx_mac_ops_t *emop = epp->ep_emop; + uint8_t *old_mulcst_addr_list = NULL; + uint32_t old_mulcst_addr_count; + int rc; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); + + if (count > EFX_MAC_MULTICAST_LIST_MAX) { + rc = EINVAL; + goto fail1; + } + + old_mulcst_addr_count = epp->ep_mulcst_addr_count; + if (old_mulcst_addr_count > 0) { + /* Allocate memory to store old list (instead of using stack) */ + EFSYS_KMEM_ALLOC(enp->en_esip, + old_mulcst_addr_count * EFX_MAC_ADDR_LEN, + old_mulcst_addr_list); + if (old_mulcst_addr_list == NULL) { + rc = ENOMEM; + goto fail2; + } + + /* Save the old list in case we need to rollback */ + memcpy(old_mulcst_addr_list, epp->ep_mulcst_addr_list, + old_mulcst_addr_count * EFX_MAC_ADDR_LEN); + } + + /* Store the new list */ + memcpy(epp->ep_mulcst_addr_list, addrs, + count * EFX_MAC_ADDR_LEN); + epp->ep_mulcst_addr_count = count; + + if ((rc = emop->emo_multicast_list_set(enp)) != 0) + goto fail3; + + if (old_mulcst_addr_count > 0) { + EFSYS_KMEM_FREE(enp->en_esip, + old_mulcst_addr_count * EFX_MAC_ADDR_LEN, + old_mulcst_addr_list); + } + + return (0); + +fail3: + EFSYS_PROBE(fail3); + + /* Restore original list on failure */ + epp->ep_mulcst_addr_count = old_mulcst_addr_count; + if (old_mulcst_addr_count > 0) { + memcpy(epp->ep_mulcst_addr_list, old_mulcst_addr_list, + old_mulcst_addr_count * EFX_MAC_ADDR_LEN); + + EFSYS_KMEM_FREE(enp->en_esip, + old_mulcst_addr_count * EFX_MAC_ADDR_LEN, + old_mulcst_addr_list); + } + +fail2: + EFSYS_PROBE(fail2); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); + +} + + __checkReturn int +efx_mac_filter_default_rxq_set( + __in efx_nic_t *enp, + __in efx_rxq_t *erp, + __in boolean_t using_rss) +{ + efx_port_t *epp = &(enp->en_port); + efx_mac_ops_t *emop = epp->ep_emop; + int rc; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); + + if (emop->emo_filter_default_rxq_set != NULL) { + rc = emop->emo_filter_default_rxq_set(enp, erp, using_rss); + if (rc != 0) + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + void +efx_mac_filter_default_rxq_clear( + __in efx_nic_t *enp) +{ + efx_port_t *epp = &(enp->en_port); + efx_mac_ops_t *emop = epp->ep_emop; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); + + if (emop->emo_filter_default_rxq_clear != NULL) + emop->emo_filter_default_rxq_clear(enp); +} + + #if EFSYS_OPT_MAC_STATS #if EFSYS_OPT_NAMES -/* START MKCONFIG GENERATED EfxMacStatNamesBlock adf707adba80813e */ -static const char __cs * __cs __efx_mac_stat_name[] = { +/* START MKCONFIG GENERATED EfxMacStatNamesBlock 054d43a31d2d7a45 */ +static const char *__efx_mac_stat_name[] = { "rx_octets", "rx_pkts", "rx_unicst_pkts", "rx_multicst_pkts", "rx_brdcst_pkts", "rx_pause_pkts", "rx_le_64_pkts", "rx_65_to_127_pkts", "rx_128_to_255_pkts", "rx_256_to_511_pkts", "rx_512_to_1023_pkts", "rx_1024_to_15xx_pkts", "rx_ge_15xx_pkts", "rx_errors", "rx_fcs_errors", "rx_drop_events", "rx_false_carrier_errors", "rx_symbol_errors", "rx_align_errors", "rx_internal_errors", "rx_jabber_pkts", "rx_lane0_char_err", "rx_lane1_char_err", "rx_lane2_char_err", "rx_lane3_char_err", "rx_lane0_disp_err", "rx_lane1_disp_err", "rx_lane2_disp_err", "rx_lane3_disp_err", "rx_match_fault", "rx_nodesc_drop_cnt", "tx_octets", "tx_pkts", "tx_unicst_pkts", "tx_multicst_pkts", "tx_brdcst_pkts", "tx_pause_pkts", "tx_le_64_pkts", "tx_65_to_127_pkts", "tx_128_to_255_pkts", "tx_256_to_511_pkts", "tx_512_to_1023_pkts", "tx_1024_to_15xx_pkts", "tx_ge_15xx_pkts", "tx_errors", "tx_sgl_col_pkts", "tx_mult_col_pkts", "tx_ex_col_pkts", "tx_late_col_pkts", "tx_def_pkts", "tx_ex_def_pkts", + "pm_trunc_bb_overflow", + "pm_discard_bb_overflow", + "pm_trunc_vfifo_full", + "pm_discard_vfifo_full", + "pm_trunc_qbb", + "pm_discard_qbb", + "pm_discard_mapping", + "rxdp_q_disabled_pkts", + "rxdp_di_dropped_pkts", + "rxdp_streaming_pkts", + "rxdp_hlb_fetch", + "rxdp_hlb_wait", + "vadapter_rx_unicast_packets", + "vadapter_rx_unicast_bytes", + "vadapter_rx_multicast_packets", + "vadapter_rx_multicast_bytes", + "vadapter_rx_broadcast_packets", + "vadapter_rx_broadcast_bytes", + "vadapter_rx_bad_packets", + "vadapter_rx_bad_bytes", + "vadapter_rx_overflow", + "vadapter_tx_unicast_packets", + "vadapter_tx_unicast_bytes", + "vadapter_tx_multicast_packets", + "vadapter_tx_multicast_bytes", + "vadapter_tx_broadcast_packets", + "vadapter_tx_broadcast_bytes", + "vadapter_tx_bad_packets", + "vadapter_tx_bad_bytes", + "vadapter_tx_overflow", }; /* END MKCONFIG GENERATED EfxMacStatNamesBlock */ - __checkReturn const char __cs * + __checkReturn const char * efx_mac_stat_name( __in efx_nic_t *enp, __in unsigned int id) { _NOTE(ARGUNUSED(enp)) EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(id, <, EFX_MAC_NSTATS); return (__efx_mac_stat_name[id]); } -#endif /* EFSYS_OPT_STAT_NAME */ +#endif /* EFSYS_OPT_NAMES */ __checkReturn int efx_mac_stats_upload( __in efx_nic_t *enp, __in efsys_mem_t *esmp) { efx_port_t *epp = &(enp->en_port); efx_mac_ops_t *emop = epp->ep_emop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); EFSYS_ASSERT(emop != NULL); /* * Don't assert !ep_mac_stats_pending, because the client might * have failed to finalise statistics when previously stopping * the port. */ if ((rc = emop->emo_stats_upload(enp, esmp)) != 0) goto fail1; epp->ep_mac_stats_pending = B_TRUE; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_mac_stats_periodic( __in efx_nic_t *enp, __in efsys_mem_t *esmp, __in uint16_t period_ms, __in boolean_t events) { efx_port_t *epp = &(enp->en_port); efx_mac_ops_t *emop = epp->ep_emop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); EFSYS_ASSERT(emop != NULL); if (emop->emo_stats_periodic == NULL) { rc = EINVAL; goto fail1; } if ((rc = emop->emo_stats_periodic(enp, esmp, period_ms, events)) != 0) goto fail2; return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_mac_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *essp, - __in uint32_t *generationp) + __out_opt uint32_t *generationp) { efx_port_t *epp = &(enp->en_port); efx_mac_ops_t *emop = epp->ep_emop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); EFSYS_ASSERT(emop != NULL); rc = emop->emo_stats_update(enp, esmp, essp, generationp); if (rc == 0) epp->ep_mac_stats_pending = B_FALSE; return (rc); } #endif /* EFSYS_OPT_MAC_STATS */ __checkReturn int efx_mac_select( __in efx_nic_t *enp) { efx_port_t *epp = &(enp->en_port); efx_mac_type_t type = EFX_MAC_INVALID; efx_mac_ops_t *emop; int rc = EINVAL; +#if EFSYS_OPT_HUNTINGTON + if (enp->en_family == EFX_FAMILY_HUNTINGTON) { + type = EFX_MAC_HUNTINGTON; + goto chosen; + } +#endif + #if EFSYS_OPT_SIENA if (enp->en_family == EFX_FAMILY_SIENA) { type = EFX_MAC_SIENA; goto chosen; } #endif #if EFSYS_OPT_FALCON switch (epp->ep_link_mode) { #if EFSYS_OPT_MAC_FALCON_GMAC case EFX_LINK_100HDX: case EFX_LINK_100FDX: case EFX_LINK_1000HDX: case EFX_LINK_1000FDX: type = EFX_MAC_FALCON_GMAC; goto chosen; #endif /* EFSYS_OPT_FALCON_GMAC */ #if EFSYS_OPT_MAC_FALCON_XMAC case EFX_LINK_10000FDX: type = EFX_MAC_FALCON_XMAC; goto chosen; #endif /* EFSYS_OPT_FALCON_XMAC */ default: #if EFSYS_OPT_MAC_FALCON_GMAC && EFSYS_OPT_MAC_FALCON_XMAC /* Only initialise a MAC supported by the PHY */ if (epp->ep_phy_cap_mask & ((1 << EFX_PHY_CAP_1000FDX) | (1 << EFX_PHY_CAP_1000HDX) | (1 << EFX_PHY_CAP_100FDX) | (1 << EFX_PHY_CAP_100HDX) | (1 << EFX_PHY_CAP_10FDX) | (1 << EFX_PHY_CAP_10FDX))) type = EFX_MAC_FALCON_GMAC; else type = EFX_MAC_FALCON_XMAC; #elif EFSYS_OPT_MAC_FALCON_GMAC type = EFX_MAC_FALCON_GMAC; #else type = EFX_MAC_FALCON_XMAC; #endif goto chosen; } #endif /* EFSYS_OPT_FALCON */ chosen: EFSYS_ASSERT(type != EFX_MAC_INVALID); EFSYS_ASSERT3U(type, <, EFX_MAC_NTYPES); emop = epp->ep_emop = (efx_mac_ops_t *)__efx_mac_ops[type]; EFSYS_ASSERT(emop != NULL); epp->ep_mac_type = type; if (emop->emo_reset != NULL) { if ((rc = emop->emo_reset(enp)) != 0) goto fail1; EFSYS_ASSERT(enp->en_reset_flags & EFX_RESET_MAC); enp->en_reset_flags &= ~EFX_RESET_MAC; } return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } + + +#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA + +/* Compute the multicast hash as used on Falcon and Siena. */ +static void +falconsiena_mac_multicast_hash_compute( + __in_ecount(6*count) uint8_t const *addrs, + __in int count, + __out efx_oword_t *hash_low, + __out efx_oword_t *hash_high) +{ + uint32_t crc, index; + int i; + + EFSYS_ASSERT(hash_low != NULL); + EFSYS_ASSERT(hash_high != NULL); + + EFX_ZERO_OWORD(*hash_low); + EFX_ZERO_OWORD(*hash_high); + + for (i = 0; i < count; i++) { + /* Calculate hash bucket (IEEE 802.3 CRC32 of the MAC addr) */ + crc = efx_crc32_calculate(0xffffffff, addrs, EFX_MAC_ADDR_LEN); + index = crc % EFX_MAC_HASH_BITS; + if (index < 128) { + EFX_SET_OWORD_BIT(*hash_low, index); + } else { + EFX_SET_OWORD_BIT(*hash_high, index - 128); + } + + addrs += EFX_MAC_ADDR_LEN; + } +} + +static __checkReturn int +falconsiena_mac_multicast_list_set( + __in efx_nic_t *enp) +{ + efx_port_t *epp = &(enp->en_port); + efx_mac_ops_t *emop = epp->ep_emop; + efx_oword_t old_hash[2]; + int rc; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); + + memcpy(old_hash, epp->ep_multicst_hash, sizeof (old_hash)); + + falconsiena_mac_multicast_hash_compute(epp->ep_mulcst_addr_list, + epp->ep_mulcst_addr_count, + &epp->ep_multicst_hash[0], + &epp->ep_multicst_hash[1]); + + if ((rc = emop->emo_reconfigure(enp)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + memcpy(epp->ep_multicst_hash, old_hash, sizeof (old_hash)); + + return (rc); +} + +#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ Property changes on: head/sys/dev/sfxge/common/efx_mac.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_mcdi.c =================================================================== --- head/sys/dev/sfxge/common/efx_mcdi.c (revision 283513) +++ head/sys/dev/sfxge/common/efx_mcdi.c (revision 283514) @@ -1,742 +1,1659 @@ /*- - * Copyright 2008-2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2008-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include "efsys.h" #include "efx.h" #include "efx_types.h" #include "efx_regs.h" #include "efx_regs_mcdi.h" #include "efx_impl.h" #if EFSYS_OPT_MCDI -/* - * A reboot/assertion causes the MCDI status word to be set after the - * command word is set or a REBOOT event is sent. If we notice a reboot - * via these mechanisms then wait 10ms for the status word to be set. - */ -#define MCDI_STATUS_SLEEP_US 10000 +#if EFSYS_OPT_SIENA + +static efx_mcdi_ops_t __efx_mcdi_siena_ops = { + siena_mcdi_init, /* emco_init */ + siena_mcdi_request_copyin, /* emco_request_copyin */ + siena_mcdi_request_poll, /* emco_request_poll */ + siena_mcdi_request_copyout, /* emco_request_copyout */ + siena_mcdi_poll_reboot, /* emco_poll_reboot */ + siena_mcdi_fini, /* emco_fini */ + siena_mcdi_fw_update_supported, /* emco_fw_update_supported */ + siena_mcdi_macaddr_change_supported, + /* emco_macaddr_change_supported */ +}; + +#endif /* EFSYS_OPT_SIENA */ + +#if EFSYS_OPT_HUNTINGTON + +static efx_mcdi_ops_t __efx_mcdi_hunt_ops = { + hunt_mcdi_init, /* emco_init */ + hunt_mcdi_request_copyin, /* emco_request_copyin */ + hunt_mcdi_request_poll, /* emco_request_poll */ + hunt_mcdi_request_copyout, /* emco_request_copyout */ + hunt_mcdi_poll_reboot, /* emco_poll_reboot */ + hunt_mcdi_fini, /* emco_fini */ + hunt_mcdi_fw_update_supported, /* emco_fw_update_supported */ + hunt_mcdi_macaddr_change_supported, + /* emco_macaddr_change_supported */ +}; + +#endif /* EFSYS_OPT_HUNTINGTON */ + + + + __checkReturn int +efx_mcdi_init( + __in efx_nic_t *enp, + __in const efx_mcdi_transport_t *emtp) +{ + efx_mcdi_ops_t *emcop; + int rc; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0); + + switch (enp->en_family) { +#if EFSYS_OPT_FALCON + case EFX_FAMILY_FALCON: + emcop = NULL; + emtp = NULL; + break; +#endif /* EFSYS_OPT_FALCON */ + +#if EFSYS_OPT_SIENA + case EFX_FAMILY_SIENA: + emcop = (efx_mcdi_ops_t *)&__efx_mcdi_siena_ops; + break; +#endif /* EFSYS_OPT_SIENA */ + +#if EFSYS_OPT_HUNTINGTON + case EFX_FAMILY_HUNTINGTON: + emcop = (efx_mcdi_ops_t *)&__efx_mcdi_hunt_ops; + break; +#endif /* EFSYS_OPT_HUNTINGTON */ + + default: + EFSYS_ASSERT(0); + rc = ENOTSUP; + goto fail1; + } + + if (enp->en_features & EFX_FEATURE_MCDI_DMA) { + /* MCDI requires a DMA buffer in host memory */ + if ((emtp == NULL) || (emtp->emt_dma_mem) == NULL) { + rc = EINVAL; + goto fail2; + } + } + enp->en_mcdi.em_emtp = emtp; + + if (emcop != NULL && emcop->emco_init != NULL) { + if ((rc = emcop->emco_init(enp, emtp)) != 0) + goto fail3; + } + + enp->en_mcdi.em_emcop = emcop; + enp->en_mod_flags |= EFX_MOD_MCDI; + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + enp->en_mcdi.em_emcop = NULL; + enp->en_mcdi.em_emtp = NULL; + enp->en_mod_flags &= ~EFX_MOD_MCDI; + + return (rc); +} + void +efx_mcdi_fini( + __in efx_nic_t *enp) +{ + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, ==, EFX_MOD_MCDI); + + if (emcop != NULL && emcop->emco_fini != NULL) + emcop->emco_fini(enp); + + emip->emi_port = 0; + emip->emi_aborted = 0; + + enp->en_mcdi.em_emcop = NULL; + enp->en_mod_flags &= ~EFX_MOD_MCDI; +} + + void +efx_mcdi_new_epoch( + __in efx_nic_t *enp) +{ + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + int state; + + /* Start a new epoch (allow fresh MCDI requests to succeed) */ + EFSYS_LOCK(enp->en_eslp, state); + emip->emi_new_epoch = B_TRUE; + EFSYS_UNLOCK(enp->en_eslp, state); +} + + + void efx_mcdi_request_start( __in efx_nic_t *enp, __in efx_mcdi_req_t *emrp, __in boolean_t ev_cpl) { - efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip); - efx_dword_t dword; + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; unsigned int seq; - unsigned int xflags; - unsigned int pdur; - unsigned int dbr; - unsigned int pos; + boolean_t new_epoch; int state; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI); - switch (emip->emi_port) { - case 1: - pdur = MC_SMEM_P0_PDU_OFST >> 2; - dbr = MC_SMEM_P0_DOORBELL_OFST >> 2; - break; - case 2: - pdur = MC_SMEM_P1_PDU_OFST >> 2; - dbr = MC_SMEM_P1_DOORBELL_OFST >> 2; - break; - default: - EFSYS_ASSERT(0); - pdur = dbr = 0; - }; + if (emcop == NULL || emcop->emco_request_copyin == NULL) + return; /* * efx_mcdi_request_start() is naturally serialised against both * efx_mcdi_request_poll() and efx_mcdi_ev_cpl()/efx_mcdi_ev_death(), * by virtue of there only being one outstanding MCDI request. * Unfortunately, upper layers may also call efx_mcdi_request_abort() * at any time, to timeout a pending mcdi request, That request may * then subsequently complete, meaning efx_mcdi_ev_cpl() or * efx_mcdi_ev_death() may end up running in parallel with * efx_mcdi_request_start(). This race is handled by ensuring that * %emi_pending_req, %emi_ev_cpl and %emi_seq are protected by the * en_eslp lock. */ EFSYS_LOCK(enp->en_eslp, state); EFSYS_ASSERT(emip->emi_pending_req == NULL); emip->emi_pending_req = emrp; emip->emi_ev_cpl = ev_cpl; emip->emi_poll_cnt = 0; - seq = emip->emi_seq++ & 0xf; + seq = emip->emi_seq++ & EFX_MASK32(MCDI_HEADER_SEQ); + new_epoch = emip->emi_new_epoch; EFSYS_UNLOCK(enp->en_eslp, state); - xflags = 0; - if (ev_cpl) - xflags |= MCDI_HEADER_XFLAGS_EVREQ; + emcop->emco_request_copyin(enp, emrp, seq, ev_cpl, new_epoch); +} - /* Construct the header in shared memory */ - EFX_POPULATE_DWORD_6(dword, - MCDI_HEADER_CODE, emrp->emr_cmd, - MCDI_HEADER_RESYNC, 1, - MCDI_HEADER_DATALEN, emrp->emr_in_length, - MCDI_HEADER_SEQ, seq, - MCDI_HEADER_RESPONSE, 0, - MCDI_HEADER_XFLAGS, xflags); - EFX_BAR_TBL_WRITED(enp, FR_CZ_MC_TREG_SMEM, pdur, &dword, B_TRUE); + __checkReturn boolean_t +efx_mcdi_request_poll( + __in efx_nic_t *enp) +{ + efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; + boolean_t completed; - for (pos = 0; pos < emrp->emr_in_length; pos += sizeof (efx_dword_t)) { - memcpy(&dword, MCDI_IN(*emrp, efx_dword_t, pos), - MIN(sizeof (dword), emrp->emr_in_length - pos)); - EFX_BAR_TBL_WRITED(enp, FR_CZ_MC_TREG_SMEM, - pdur + 1 + (pos >> 2), &dword, B_FALSE); - } + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); + EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI); - /* Ring the doorbell */ - EFX_POPULATE_DWORD_1(dword, EFX_DWORD_0, 0xd004be11); - EFX_BAR_TBL_WRITED(enp, FR_CZ_MC_TREG_SMEM, dbr, &dword, B_FALSE); + completed = B_FALSE; + + if (emcop != NULL && emcop->emco_request_poll != NULL) + completed = emcop->emco_request_poll(enp); + + return (completed); } -static void -efx_mcdi_request_copyout( - __in efx_nic_t *enp, - __in efx_mcdi_req_t *emrp) + __checkReturn boolean_t +efx_mcdi_request_abort( + __in efx_nic_t *enp) { - efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip); - unsigned int pos; - unsigned int pdur; - efx_dword_t data; + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + efx_mcdi_req_t *emrp; + boolean_t aborted; + int state; - pdur = (emip->emi_port == 1) - ? MC_SMEM_P0_PDU_OFST >> 2 - : MC_SMEM_P1_PDU_OFST >> 2; + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); + EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI); - /* Copy payload out if caller supplied buffer */ - if (emrp->emr_out_buf != NULL) { - size_t bytes = MIN(emrp->emr_out_length_used, - emrp->emr_out_length); - for (pos = 0; pos < bytes; pos += sizeof (efx_dword_t)) { - EFX_BAR_TBL_READD(enp, FR_CZ_MC_TREG_SMEM, - pdur + 1 + (pos >> 2), &data, B_FALSE); - memcpy(MCDI_OUT(*emrp, efx_dword_t, pos), &data, - MIN(sizeof (data), bytes - pos)); - } + /* + * efx_mcdi_ev_* may have already completed this event, and be + * spinning/blocked on the upper layer lock. So it *is* legitimate + * to for emi_pending_req to be NULL. If there is a pending event + * completed request, then provide a "credit" to allow + * efx_mcdi_ev_cpl() to accept a single spurious completion. + */ + EFSYS_LOCK(enp->en_eslp, state); + emrp = emip->emi_pending_req; + aborted = (emrp != NULL); + if (aborted) { + emip->emi_pending_req = NULL; + + /* Error the request */ + emrp->emr_out_length_used = 0; + emrp->emr_rc = ETIMEDOUT; + + /* Provide a credit for seqno/emr_pending_req mismatches */ + if (emip->emi_ev_cpl) + ++emip->emi_aborted; + + /* + * The upper layer has called us, so we don't + * need to complete the request. + */ } + EFSYS_UNLOCK(enp->en_eslp, state); + + return (aborted); } -static int + __checkReturn int efx_mcdi_request_errcode( __in unsigned int err) { switch (err) { + /* MCDI v1 */ + case MC_CMD_ERR_EPERM: + return (EACCES); case MC_CMD_ERR_ENOENT: return (ENOENT); case MC_CMD_ERR_EINTR: return (EINTR); case MC_CMD_ERR_EACCES: return (EACCES); case MC_CMD_ERR_EBUSY: return (EBUSY); case MC_CMD_ERR_EINVAL: return (EINVAL); case MC_CMD_ERR_EDEADLK: return (EDEADLK); case MC_CMD_ERR_ENOSYS: return (ENOTSUP); case MC_CMD_ERR_ETIME: return (ETIMEDOUT); -#ifdef WITH_MCDI_V2 + case MC_CMD_ERR_ENOTSUP: + return (ENOTSUP); + case MC_CMD_ERR_EALREADY: + return (EALREADY); + + /* MCDI v2 */ +#ifdef MC_CMD_ERR_EAGAIN case MC_CMD_ERR_EAGAIN: return (EAGAIN); +#endif +#ifdef MC_CMD_ERR_ENOSPC case MC_CMD_ERR_ENOSPC: return (ENOSPC); #endif + + case MC_CMD_ERR_ALLOC_FAIL: + return (ENOMEM); + case MC_CMD_ERR_NO_VADAPTOR: + return (ENOENT); + case MC_CMD_ERR_NO_EVB_PORT: + return (ENOENT); + case MC_CMD_ERR_NO_VSWITCH: + return (ENODEV); + case MC_CMD_ERR_VLAN_LIMIT: + return (EINVAL); + case MC_CMD_ERR_BAD_PCI_FUNC: + return (ENODEV); + case MC_CMD_ERR_BAD_VLAN_MODE: + return (EINVAL); + case MC_CMD_ERR_BAD_VSWITCH_TYPE: + return (EINVAL); + case MC_CMD_ERR_BAD_VPORT_TYPE: + return (EINVAL); + case MC_CMD_ERR_MAC_EXIST: + return (EEXIST); + default: EFSYS_PROBE1(mc_pcol_error, int, err); return (EIO); } } -static void + void efx_mcdi_raise_exception( __in efx_nic_t *enp, __in_opt efx_mcdi_req_t *emrp, __in int rc) { - efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip); - const efx_mcdi_transport_t *emtp = emip->emi_mtp; + const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; efx_mcdi_exception_t exception; /* Reboot or Assertion failure only */ EFSYS_ASSERT(rc == EIO || rc == EINTR); /* * If MC_CMD_REBOOT causes a reboot (dependent on parameters), * then the EIO is not worthy of an exception. */ if (emrp != NULL && emrp->emr_cmd == MC_CMD_REBOOT && rc == EIO) return; exception = (rc == EIO) ? EFX_MCDI_EXCEPTION_MC_REBOOT : EFX_MCDI_EXCEPTION_MC_BADASSERT; emtp->emt_exception(emtp->emt_context, exception); } static int efx_mcdi_poll_reboot( __in efx_nic_t *enp) { -#ifndef EFX_GRACEFUL_MC_REBOOT - /* - * This function is not being used properly. - * Until its callers are fixed, it should always return 0. - */ - _NOTE(ARGUNUSED(enp)) - return (0); -#else - efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip); - unsigned int rebootr; - efx_dword_t dword; - uint32_t value; + efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; - EFSYS_ASSERT(emip->emi_port == 1 || emip->emi_port == 2); - rebootr = ((emip->emi_port == 1) - ? MC_SMEM_P0_STATUS_OFST >> 2 - : MC_SMEM_P1_STATUS_OFST >> 2); - - EFX_BAR_TBL_READD(enp, FR_CZ_MC_TREG_SMEM, rebootr, &dword, B_FALSE); - value = EFX_DWORD_FIELD(dword, EFX_DWORD_0); - - if (value == 0) - return (0); - - EFX_ZERO_DWORD(dword); - EFX_BAR_TBL_WRITED(enp, FR_CZ_MC_TREG_SMEM, rebootr, &dword, B_FALSE); - - if (value == MC_STATUS_DWORD_ASSERT) - return (EINTR); - else - return (EIO); -#endif + return (emcop->emco_poll_reboot(enp)); } - __checkReturn boolean_t -efx_mcdi_request_poll( - __in efx_nic_t *enp) + + void +efx_mcdi_execute( + __in efx_nic_t *enp, + __inout efx_mcdi_req_t *emrp) { - efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip); - efx_mcdi_req_t *emrp; - efx_dword_t dword; - unsigned int pdur; - unsigned int seq; - unsigned int length; - int state; - int rc; + const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); - EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI); - /* Serialise against post-watchdog efx_mcdi_ev* */ - EFSYS_LOCK(enp->en_eslp, state); - - EFSYS_ASSERT(emip->emi_pending_req != NULL); - EFSYS_ASSERT(!emip->emi_ev_cpl); - emrp = emip->emi_pending_req; - - /* Check for reboot atomically w.r.t efx_mcdi_request_start */ - if (emip->emi_poll_cnt++ == 0) { - if ((rc = efx_mcdi_poll_reboot(enp)) != 0) { - emip->emi_pending_req = NULL; - EFSYS_UNLOCK(enp->en_eslp, state); - - goto fail1; - } - } - - EFSYS_ASSERT(emip->emi_port == 1 || emip->emi_port == 2); - pdur = (emip->emi_port == 1) - ? MC_SMEM_P0_PDU_OFST >> 2 - : MC_SMEM_P1_PDU_OFST >> 2; - - /* Read the command header */ - EFX_BAR_TBL_READD(enp, FR_CZ_MC_TREG_SMEM, pdur, &dword, B_FALSE); - if (EFX_DWORD_FIELD(dword, MCDI_HEADER_RESPONSE) == 0) { - EFSYS_UNLOCK(enp->en_eslp, state); - return (B_FALSE); - } - - /* Request complete */ - emip->emi_pending_req = NULL; - seq = (emip->emi_seq - 1) & 0xf; - - /* Check for synchronous reboot */ - if (EFX_DWORD_FIELD(dword, MCDI_HEADER_ERROR) != 0 && - EFX_DWORD_FIELD(dword, MCDI_HEADER_DATALEN) == 0) { - /* Consume status word */ - EFSYS_SPIN(MCDI_STATUS_SLEEP_US); - efx_mcdi_poll_reboot(enp); - EFSYS_UNLOCK(enp->en_eslp, state); - rc = EIO; - goto fail2; - } - - EFSYS_UNLOCK(enp->en_eslp, state); - - /* Check that the returned data is consistent */ - if (EFX_DWORD_FIELD(dword, MCDI_HEADER_CODE) != emrp->emr_cmd || - EFX_DWORD_FIELD(dword, MCDI_HEADER_SEQ) != seq) { - /* Response is for a different request */ - rc = EIO; - goto fail3; - } - - length = EFX_DWORD_FIELD(dword, MCDI_HEADER_DATALEN); - if (EFX_DWORD_FIELD(dword, MCDI_HEADER_ERROR)) { - efx_dword_t errdword; - int errcode; - - EFSYS_ASSERT3U(length, ==, 4); - EFX_BAR_TBL_READD(enp, FR_CZ_MC_TREG_SMEM, - pdur + 1 + (MC_CMD_ERR_CODE_OFST >> 2), - &errdword, B_FALSE); - errcode = EFX_DWORD_FIELD(errdword, EFX_DWORD_0); - rc = efx_mcdi_request_errcode(errcode); - EFSYS_PROBE2(mcdi_err, int, emrp->emr_cmd, int, errcode); - goto fail4; - - } else { - emrp->emr_out_length_used = length; - emrp->emr_rc = 0; - efx_mcdi_request_copyout(enp, emrp); - } - - goto out; - -fail4: - EFSYS_PROBE(fail4); -fail3: - EFSYS_PROBE(fail3); -fail2: - EFSYS_PROBE(fail2); -fail1: - EFSYS_PROBE1(fail1, int, rc); - - /* Fill out error state */ - emrp->emr_rc = rc; - emrp->emr_out_length_used = 0; - - /* Reboot/Assertion */ - if (rc == EIO || rc == EINTR) - efx_mcdi_raise_exception(enp, emrp, rc); - -out: - return (B_TRUE); + emrp->emr_quiet = B_FALSE; + emtp->emt_execute(emtp->emt_context, emrp); } void -efx_mcdi_execute( +efx_mcdi_execute_quiet( __in efx_nic_t *enp, - __in efx_mcdi_req_t *emrp) + __inout efx_mcdi_req_t *emrp) { - efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip); - const efx_mcdi_transport_t *emtp = emip->emi_mtp; + const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); - EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI); + emrp->emr_quiet = B_TRUE; emtp->emt_execute(emtp->emt_context, emrp); } void efx_mcdi_ev_cpl( __in efx_nic_t *enp, __in unsigned int seq, __in unsigned int outlen, __in int errcode) { - efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip); - const efx_mcdi_transport_t *emtp = emip->emi_mtp; + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; + efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; efx_mcdi_req_t *emrp; int state; EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); - EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI); /* * Serialise against efx_mcdi_request_poll()/efx_mcdi_request_start() * when we're completing an aborted request. */ EFSYS_LOCK(enp->en_eslp, state); if (emip->emi_pending_req == NULL || !emip->emi_ev_cpl || - (seq != ((emip->emi_seq - 1) & 0xf))) { + (seq != ((emip->emi_seq - 1) & EFX_MASK32(MCDI_HEADER_SEQ)))) { EFSYS_ASSERT(emip->emi_aborted > 0); if (emip->emi_aborted > 0) --emip->emi_aborted; EFSYS_UNLOCK(enp->en_eslp, state); return; } emrp = emip->emi_pending_req; emip->emi_pending_req = NULL; EFSYS_UNLOCK(enp->en_eslp, state); /* * Fill out the remaining hdr fields, and copyout the payload * if the user supplied an output buffer. */ if (errcode != 0) { - EFSYS_PROBE2(mcdi_err, int, emrp->emr_cmd, - int, errcode); + if (!emrp->emr_quiet) { + EFSYS_PROBE2(mcdi_err, int, emrp->emr_cmd, + int, errcode); + } emrp->emr_out_length_used = 0; emrp->emr_rc = efx_mcdi_request_errcode(errcode); } else { emrp->emr_out_length_used = outlen; emrp->emr_rc = 0; - efx_mcdi_request_copyout(enp, emrp); + + emcop->emco_request_copyout(enp, emrp); } emtp->emt_ev_cpl(emtp->emt_context); } void efx_mcdi_ev_death( __in efx_nic_t *enp, __in int rc) { - efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip); - const efx_mcdi_transport_t *emtp = emip->emi_mtp; + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; efx_mcdi_req_t *emrp = NULL; boolean_t ev_cpl; int state; /* * The MCDI request (if there is one) has been terminated, either * by a BADASSERT or REBOOT event. * * If there is an outstanding event-completed MCDI operation, then we * will never receive the completion event (because both MCDI * completions and BADASSERT events are sent to the same evq). So * complete this MCDI op. * * This function might run in parallel with efx_mcdi_request_poll() * for poll completed mcdi requests, and also with * efx_mcdi_request_start() for post-watchdog completions. */ EFSYS_LOCK(enp->en_eslp, state); emrp = emip->emi_pending_req; ev_cpl = emip->emi_ev_cpl; if (emrp != NULL && emip->emi_ev_cpl) { emip->emi_pending_req = NULL; emrp->emr_out_length_used = 0; emrp->emr_rc = rc; ++emip->emi_aborted; } /* * Since we're running in parallel with a request, consume the * status word before dropping the lock. */ if (rc == EIO || rc == EINTR) { - EFSYS_SPIN(MCDI_STATUS_SLEEP_US); + EFSYS_SPIN(EFX_MCDI_STATUS_SLEEP_US); (void) efx_mcdi_poll_reboot(enp); + emip->emi_new_epoch = B_TRUE; } EFSYS_UNLOCK(enp->en_eslp, state); efx_mcdi_raise_exception(enp, emrp, rc); if (emrp != NULL && ev_cpl) emtp->emt_ev_cpl(emtp->emt_context); } __checkReturn int efx_mcdi_version( __in efx_nic_t *enp, __out_ecount_opt(4) uint16_t versionp[4], __out_opt uint32_t *buildp, __out_opt efx_mcdi_boot_t *statusp) { - uint8_t outbuf[MAX(MC_CMD_GET_VERSION_OUT_LEN, - MC_CMD_GET_BOOT_STATUS_OUT_LEN)]; efx_mcdi_req_t req; + uint8_t payload[MAX(MAX(MC_CMD_GET_VERSION_IN_LEN, + MC_CMD_GET_VERSION_OUT_LEN), + MAX(MC_CMD_GET_BOOT_STATUS_IN_LEN, + MC_CMD_GET_BOOT_STATUS_OUT_LEN))]; efx_word_t *ver_words; uint16_t version[4]; uint32_t build; efx_mcdi_boot_t status; int rc; - EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI); - EFX_STATIC_ASSERT(MC_CMD_GET_VERSION_IN_LEN == 0); + (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_GET_VERSION; - req.emr_in_buf = NULL; - req.emr_in_length = 0; - req.emr_out_buf = outbuf; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_GET_VERSION_IN_LEN; + req.emr_out_buf = payload; req.emr_out_length = MC_CMD_GET_VERSION_OUT_LEN; efx_mcdi_execute(enp, &req); if (req.emr_rc != 0) { rc = req.emr_rc; goto fail1; } /* bootrom support */ if (req.emr_out_length_used == MC_CMD_GET_VERSION_V0_OUT_LEN) { version[0] = version[1] = version[2] = version[3] = 0; build = MCDI_OUT_DWORD(req, GET_VERSION_OUT_FIRMWARE); goto version; } if (req.emr_out_length_used < MC_CMD_GET_VERSION_OUT_LEN) { rc = EMSGSIZE; goto fail2; } ver_words = MCDI_OUT2(req, efx_word_t, GET_VERSION_OUT_VERSION); version[0] = EFX_WORD_FIELD(ver_words[0], EFX_WORD_0); version[1] = EFX_WORD_FIELD(ver_words[1], EFX_WORD_0); version[2] = EFX_WORD_FIELD(ver_words[2], EFX_WORD_0); version[3] = EFX_WORD_FIELD(ver_words[3], EFX_WORD_0); build = MCDI_OUT_DWORD(req, GET_VERSION_OUT_FIRMWARE); version: /* The bootrom doesn't understand BOOT_STATUS */ - if (build == MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM) { + if (MC_FW_VERSION_IS_BOOTLOADER(build)) { status = EFX_MCDI_BOOT_ROM; goto out; } + (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_GET_BOOT_STATUS; - EFX_STATIC_ASSERT(MC_CMD_GET_BOOT_STATUS_IN_LEN == 0); - req.emr_in_buf = NULL; - req.emr_in_length = 0; - req.emr_out_buf = outbuf; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_GET_BOOT_STATUS_IN_LEN; + req.emr_out_buf = payload; req.emr_out_length = MC_CMD_GET_BOOT_STATUS_OUT_LEN; - efx_mcdi_execute(enp, &req); + efx_mcdi_execute_quiet(enp, &req); + if (req.emr_rc == EACCES) { + /* Unprivileged functions cannot access BOOT_STATUS */ + status = EFX_MCDI_BOOT_PRIMARY; + version[0] = version[1] = version[2] = version[3] = 0; + build = 0; + goto out; + } + if (req.emr_rc != 0) { rc = req.emr_rc; goto fail3; } if (req.emr_out_length_used < MC_CMD_GET_BOOT_STATUS_OUT_LEN) { rc = EMSGSIZE; goto fail4; } if (MCDI_OUT_DWORD_FIELD(req, GET_BOOT_STATUS_OUT_FLAGS, GET_BOOT_STATUS_OUT_FLAGS_PRIMARY)) status = EFX_MCDI_BOOT_PRIMARY; else status = EFX_MCDI_BOOT_SECONDARY; out: if (versionp != NULL) memcpy(versionp, version, sizeof (version)); if (buildp != NULL) *buildp = build; if (statusp != NULL) *statusp = status; return (0); fail4: EFSYS_PROBE(fail4); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } - __checkReturn int -efx_mcdi_init( +static __checkReturn int +efx_mcdi_do_reboot( __in efx_nic_t *enp, - __in const efx_mcdi_transport_t *mtp) + __in boolean_t after_assertion) { - efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip); - efx_oword_t oword; - unsigned int portnum; + uint8_t payload[MAX(MC_CMD_REBOOT_IN_LEN, MC_CMD_REBOOT_OUT_LEN)]; + efx_mcdi_req_t req; int rc; - EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0); - enp->en_mod_flags |= EFX_MOD_MCDI; + /* + * We could require the caller to have caused en_mod_flags=0 to + * call this function. This doesn't help the other port though, + * who's about to get the MC ripped out from underneath them. + * Since they have to cope with the subsequent fallout of MCDI + * failures, we should as well. + */ + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - if (enp->en_family == EFX_FAMILY_FALCON) - return (0); + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_REBOOT; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_REBOOT_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_REBOOT_OUT_LEN; - emip->emi_mtp = mtp; + MCDI_IN_SET_DWORD(req, REBOOT_IN_FLAGS, + (after_assertion ? MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION : 0)); - /* Determine the port number to use for MCDI */ - EFX_BAR_READO(enp, FR_AZ_CS_DEBUG_REG, &oword); - portnum = EFX_OWORD_FIELD(oword, FRF_CZ_CS_PORT_NUM); + efx_mcdi_execute_quiet(enp, &req); - if (portnum == 0) { - /* Presumably booted from ROM; only MCDI port 1 will work */ - emip->emi_port = 1; - } else if (portnum <= 2) { - emip->emi_port = portnum; - } else { - rc = EINVAL; + if (req.emr_rc == EACCES) { + /* Unprivileged functions cannot reboot the MC. */ + goto out; + } + + /* A successful reboot request returns EIO. */ + if (req.emr_rc != 0 && req.emr_rc != EIO) { + rc = req.emr_rc; goto fail1; } +out: + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +efx_mcdi_reboot( + __in efx_nic_t *enp) +{ + return (efx_mcdi_do_reboot(enp, B_FALSE)); +} + + __checkReturn int +efx_mcdi_exit_assertion_handler( + __in efx_nic_t *enp) +{ + return (efx_mcdi_do_reboot(enp, B_TRUE)); +} + + __checkReturn int +efx_mcdi_read_assertion( + __in efx_nic_t *enp) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_GET_ASSERTS_IN_LEN, + MC_CMD_GET_ASSERTS_OUT_LEN)]; + const char *reason; + unsigned int flags; + unsigned int index; + unsigned int ofst; + int retry; + int rc; + /* - * Wipe the atomic reboot status so subsequent MCDI requests succeed. - * BOOT_STATUS is preserved so eno_nic_probe() can boot out of the - * assertion handler. + * Before we attempt to chat to the MC, we should verify that the MC + * isn't in it's assertion handler, either due to a previous reboot, + * or because we're reinitializing due to an eec_exception(). + * + * Use GET_ASSERTS to read any assertion state that may be present. + * Retry this command twice. Once because a boot-time assertion failure + * might cause the 1st MCDI request to fail. And once again because + * we might race with efx_mcdi_exit_assertion_handler() running on + * partner port(s) on the same NIC. */ - (void) efx_mcdi_poll_reboot(enp); + retry = 2; + do { + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_GET_ASSERTS; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_GET_ASSERTS_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_GET_ASSERTS_OUT_LEN; + MCDI_IN_SET_DWORD(req, GET_ASSERTS_IN_CLEAR, 1); + efx_mcdi_execute_quiet(enp, &req); + + } while ((req.emr_rc == EINTR || req.emr_rc == EIO) && retry-- > 0); + + if (req.emr_rc != 0) { + if (req.emr_rc == EACCES) { + /* Unprivileged functions cannot clear assertions. */ + goto out; + } + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < MC_CMD_GET_ASSERTS_OUT_LEN) { + rc = EMSGSIZE; + goto fail2; + } + + /* Print out any assertion state recorded */ + flags = MCDI_OUT_DWORD(req, GET_ASSERTS_OUT_GLOBAL_FLAGS); + if (flags == MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS) + return (0); + + reason = (flags == MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL) + ? "system-level assertion" + : (flags == MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL) + ? "thread-level assertion" + : (flags == MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED) + ? "watchdog reset" + : (flags == MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP) + ? "illegal address trap" + : "unknown assertion"; + EFSYS_PROBE3(mcpu_assertion, + const char *, reason, unsigned int, + MCDI_OUT_DWORD(req, GET_ASSERTS_OUT_SAVED_PC_OFFS), + unsigned int, + MCDI_OUT_DWORD(req, GET_ASSERTS_OUT_THREAD_OFFS)); + + /* Print out the registers (r1 ... r31) */ + ofst = MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST; + for (index = 1; + index < 1 + MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM; + index++) { + EFSYS_PROBE2(mcpu_register, unsigned int, index, unsigned int, + EFX_DWORD_FIELD(*MCDI_OUT(req, efx_dword_t, ofst), + EFX_DWORD_0)); + ofst += sizeof (efx_dword_t); + } + EFSYS_ASSERT(ofst <= MC_CMD_GET_ASSERTS_OUT_LEN); + +out: return (0); +fail2: + EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); - enp->en_mod_flags &= ~EFX_MOD_MCDI; - return (rc); } +/* + * Internal routines for for specific MCDI requests. + */ + __checkReturn int -efx_mcdi_reboot( - __in efx_nic_t *enp) +efx_mcdi_drv_attach( + __in efx_nic_t *enp, + __in boolean_t attach) { - uint8_t payload[MC_CMD_REBOOT_IN_LEN]; + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_DRV_ATTACH_IN_LEN, + MC_CMD_DRV_ATTACH_EXT_OUT_LEN)]; + uint32_t flags; int rc; + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_DRV_ATTACH; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_DRV_ATTACH_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_DRV_ATTACH_EXT_OUT_LEN; + /* - * We could require the caller to have caused en_mod_flags=0 to - * call this function. This doesn't help the other port though, - * who's about to get the MC ripped out from underneath them. - * Since they have to cope with the subsequent fallout of MCDI - * failures, we should as well. + * Use DONT_CARE for the datapath firmware type to ensure that the + * driver can attach to an unprivileged function. The datapath firmware + * type to use is controlled by the 'sfboot' utility. */ - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + MCDI_IN_SET_DWORD(req, DRV_ATTACH_IN_NEW_STATE, attach ? 1 : 0); + MCDI_IN_SET_DWORD(req, DRV_ATTACH_IN_UPDATE, 1); + MCDI_IN_SET_DWORD(req, DRV_ATTACH_IN_FIRMWARE_ID, MC_CMD_FW_DONT_CARE); - req.emr_cmd = MC_CMD_REBOOT; + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < MC_CMD_DRV_ATTACH_OUT_LEN) { + rc = EMSGSIZE; + goto fail2; + } + + if (attach == B_FALSE) { + flags = 0; + } else if (enp->en_family == EFX_FAMILY_SIENA) { + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + + /* Create synthetic privileges for Siena functions */ + flags = EFX_NIC_FUNC_LINKCTRL | EFX_NIC_FUNC_TRUSTED; + if (emip->emi_port == 1) + flags |= EFX_NIC_FUNC_PRIMARY; + } else { + EFX_STATIC_ASSERT(EFX_NIC_FUNC_PRIMARY == + (1u << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY)); + EFX_STATIC_ASSERT(EFX_NIC_FUNC_LINKCTRL == + (1u << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)); + EFX_STATIC_ASSERT(EFX_NIC_FUNC_TRUSTED == + (1u << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED)); + + /* Save function privilege flags (EF10 and later) */ + if (req.emr_out_length_used < MC_CMD_DRV_ATTACH_EXT_OUT_LEN) { + rc = EMSGSIZE; + goto fail3; + } + flags = MCDI_OUT_DWORD(req, DRV_ATTACH_EXT_OUT_FUNC_FLAGS); + } + encp->enc_func_flags = flags; + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +efx_mcdi_get_board_cfg( + __in efx_nic_t *enp, + __out_opt uint32_t *board_typep, + __out_opt efx_dword_t *capabilitiesp, + __out_ecount_opt(6) uint8_t mac_addrp[6]) +{ + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_GET_BOARD_CFG_IN_LEN, + MC_CMD_GET_BOARD_CFG_OUT_LENMIN)]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_GET_BOARD_CFG; req.emr_in_buf = payload; - req.emr_in_length = MC_CMD_REBOOT_IN_LEN; + req.emr_in_length = MC_CMD_GET_BOARD_CFG_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_GET_BOARD_CFG_OUT_LENMIN; + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < MC_CMD_GET_BOARD_CFG_OUT_LENMIN) { + rc = EMSGSIZE; + goto fail2; + } + + if (mac_addrp != NULL) { + uint8_t *addrp; + + if (emip->emi_port == 1) { + addrp = MCDI_OUT2(req, uint8_t, + GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0); + } else if (emip->emi_port == 2) { + addrp = MCDI_OUT2(req, uint8_t, + GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1); + } else { + rc = EINVAL; + goto fail3; + } + + EFX_MAC_ADDR_COPY(mac_addrp, addrp); + } + + if (capabilitiesp != NULL) { + if (emip->emi_port == 1) { + *capabilitiesp = *MCDI_OUT2(req, efx_dword_t, + GET_BOARD_CFG_OUT_CAPABILITIES_PORT0); + } else if (emip->emi_port == 2) { + *capabilitiesp = *MCDI_OUT2(req, efx_dword_t, + GET_BOARD_CFG_OUT_CAPABILITIES_PORT1); + } else { + rc = EINVAL; + goto fail4; + } + } + + if (board_typep != NULL) { + *board_typep = MCDI_OUT_DWORD(req, + GET_BOARD_CFG_OUT_BOARD_TYPE); + } + + return (0); + +fail4: + EFSYS_PROBE(fail4); +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +efx_mcdi_get_resource_limits( + __in efx_nic_t *enp, + __out_opt uint32_t *nevqp, + __out_opt uint32_t *nrxqp, + __out_opt uint32_t *ntxqp) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_GET_RESOURCE_LIMITS_IN_LEN, + MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN)]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_GET_RESOURCE_LIMITS; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_GET_RESOURCE_LIMITS_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN; + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN) { + rc = EMSGSIZE; + goto fail2; + } + + if (nevqp != NULL) + *nevqp = MCDI_OUT_DWORD(req, GET_RESOURCE_LIMITS_OUT_EVQ); + if (nrxqp != NULL) + *nrxqp = MCDI_OUT_DWORD(req, GET_RESOURCE_LIMITS_OUT_RXQ); + if (ntxqp != NULL) + *ntxqp = MCDI_OUT_DWORD(req, GET_RESOURCE_LIMITS_OUT_TXQ); + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +efx_mcdi_get_phy_cfg( + __in efx_nic_t *enp) +{ + efx_port_t *epp = &(enp->en_port); + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_GET_PHY_CFG_IN_LEN, + MC_CMD_GET_PHY_CFG_OUT_LEN)]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_GET_PHY_CFG; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_GET_PHY_CFG_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_GET_PHY_CFG_OUT_LEN; + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < MC_CMD_GET_PHY_CFG_OUT_LEN) { + rc = EMSGSIZE; + goto fail2; + } + + encp->enc_phy_type = MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_TYPE); +#if EFSYS_OPT_NAMES + (void) strncpy(encp->enc_phy_name, + MCDI_OUT2(req, char, GET_PHY_CFG_OUT_NAME), + MIN(sizeof (encp->enc_phy_name) - 1, + MC_CMD_GET_PHY_CFG_OUT_NAME_LEN)); +#endif /* EFSYS_OPT_NAMES */ + (void) memset(encp->enc_phy_revision, 0, + sizeof (encp->enc_phy_revision)); + memcpy(encp->enc_phy_revision, + MCDI_OUT2(req, char, GET_PHY_CFG_OUT_REVISION), + MIN(sizeof (encp->enc_phy_revision) - 1, + MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN)); +#if EFSYS_OPT_PHY_LED_CONTROL + encp->enc_led_mask = ((1 << EFX_PHY_LED_DEFAULT) | + (1 << EFX_PHY_LED_OFF) | + (1 << EFX_PHY_LED_ON)); +#endif /* EFSYS_OPT_PHY_LED_CONTROL */ + +#if EFSYS_OPT_PHY_PROPS + encp->enc_phy_nprops = 0; +#endif /* EFSYS_OPT_PHY_PROPS */ + + /* Get the media type of the fixed port, if recognised. */ + EFX_STATIC_ASSERT(MC_CMD_MEDIA_XAUI == EFX_PHY_MEDIA_XAUI); + EFX_STATIC_ASSERT(MC_CMD_MEDIA_CX4 == EFX_PHY_MEDIA_CX4); + EFX_STATIC_ASSERT(MC_CMD_MEDIA_KX4 == EFX_PHY_MEDIA_KX4); + EFX_STATIC_ASSERT(MC_CMD_MEDIA_XFP == EFX_PHY_MEDIA_XFP); + EFX_STATIC_ASSERT(MC_CMD_MEDIA_SFP_PLUS == EFX_PHY_MEDIA_SFP_PLUS); + EFX_STATIC_ASSERT(MC_CMD_MEDIA_BASE_T == EFX_PHY_MEDIA_BASE_T); + EFX_STATIC_ASSERT(MC_CMD_MEDIA_QSFP_PLUS == EFX_PHY_MEDIA_QSFP_PLUS); + epp->ep_fixed_port_type = + MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_MEDIA_TYPE); + if (epp->ep_fixed_port_type >= EFX_PHY_MEDIA_NTYPES) + epp->ep_fixed_port_type = EFX_PHY_MEDIA_INVALID; + + epp->ep_phy_cap_mask = + MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_SUPPORTED_CAP); +#if EFSYS_OPT_PHY_FLAGS + encp->enc_phy_flags_mask = MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_FLAGS); +#endif /* EFSYS_OPT_PHY_FLAGS */ + + encp->enc_port = (uint8_t)MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_PRT); + + /* Populate internal state */ + encp->enc_mcdi_mdio_channel = + (uint8_t)MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_CHANNEL); + +#if EFSYS_OPT_PHY_STATS + encp->enc_mcdi_phy_stat_mask = + MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_STATS_MASK); +#endif /* EFSYS_OPT_PHY_STATS */ + +#if EFSYS_OPT_BIST + encp->enc_bist_mask = 0; + if (MCDI_OUT_DWORD_FIELD(req, GET_PHY_CFG_OUT_FLAGS, + GET_PHY_CFG_OUT_BIST_CABLE_SHORT)) + encp->enc_bist_mask |= (1 << EFX_BIST_TYPE_PHY_CABLE_SHORT); + if (MCDI_OUT_DWORD_FIELD(req, GET_PHY_CFG_OUT_FLAGS, + GET_PHY_CFG_OUT_BIST_CABLE_LONG)) + encp->enc_bist_mask |= (1 << EFX_BIST_TYPE_PHY_CABLE_LONG); + if (MCDI_OUT_DWORD_FIELD(req, GET_PHY_CFG_OUT_FLAGS, + GET_PHY_CFG_OUT_BIST)) + encp->enc_bist_mask |= (1 << EFX_BIST_TYPE_PHY_NORMAL); +#endif /* EFSYS_OPT_BIST */ + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + + __checkReturn int +efx_mcdi_firmware_update_supported( + __in efx_nic_t *enp, + __out boolean_t *supportedp) +{ + efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; + int rc; + + if (emcop != NULL && emcop->emco_fw_update_supported != NULL) { + if ((rc = emcop->emco_fw_update_supported(enp, supportedp)) + != 0) + goto fail1; + } else { + /* Earlier devices always supported updates */ + *supportedp = B_TRUE; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +efx_mcdi_macaddr_change_supported( + __in efx_nic_t *enp, + __out boolean_t *supportedp) +{ + efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; + int rc; + + if (emcop != NULL && emcop->emco_macaddr_change_supported != NULL) { + if ((rc = emcop->emco_macaddr_change_supported(enp, supportedp)) + != 0) + goto fail1; + } else { + /* Earlier devices always supported MAC changes */ + *supportedp = B_TRUE; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +#if EFSYS_OPT_BIST + +#if EFSYS_OPT_HUNTINGTON +/* + * Enter bist offline mode. This is a fw mode which puts the NIC into a state + * where memory BIST tests can be run and not much else can interfere or happen. + * A reboot is required to exit this mode. + */ + __checkReturn int +efx_mcdi_bist_enable_offline( + __in efx_nic_t *enp) +{ + efx_mcdi_req_t req; + int rc; + + EFX_STATIC_ASSERT(MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN == 0); + EFX_STATIC_ASSERT(MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN == 0); + + req.emr_cmd = MC_CMD_ENABLE_OFFLINE_BIST; + req.emr_in_buf = NULL; + req.emr_in_length = 0; req.emr_out_buf = NULL; req.emr_out_length = 0; - MCDI_IN_SET_DWORD(req, REBOOT_IN_FLAGS, 0); + efx_mcdi_execute(enp, &req); + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} +#endif /* EFSYS_OPT_HUNTINGTON */ + + __checkReturn int +efx_mcdi_bist_start( + __in efx_nic_t *enp, + __in efx_bist_type_t type) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_START_BIST_IN_LEN, + MC_CMD_START_BIST_OUT_LEN)]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_START_BIST; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_START_BIST_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_START_BIST_OUT_LEN; + + switch (type) { + case EFX_BIST_TYPE_PHY_NORMAL: + MCDI_IN_SET_DWORD(req, START_BIST_IN_TYPE, MC_CMD_PHY_BIST); + break; + case EFX_BIST_TYPE_PHY_CABLE_SHORT: + MCDI_IN_SET_DWORD(req, START_BIST_IN_TYPE, + MC_CMD_PHY_BIST_CABLE_SHORT); + break; + case EFX_BIST_TYPE_PHY_CABLE_LONG: + MCDI_IN_SET_DWORD(req, START_BIST_IN_TYPE, + MC_CMD_PHY_BIST_CABLE_LONG); + break; + case EFX_BIST_TYPE_MC_MEM: + MCDI_IN_SET_DWORD(req, START_BIST_IN_TYPE, + MC_CMD_MC_MEM_BIST); + break; + case EFX_BIST_TYPE_SAT_MEM: + MCDI_IN_SET_DWORD(req, START_BIST_IN_TYPE, + MC_CMD_PORT_MEM_BIST); + break; + case EFX_BIST_TYPE_REG: + MCDI_IN_SET_DWORD(req, START_BIST_IN_TYPE, + MC_CMD_REG_BIST); + break; + default: + EFSYS_ASSERT(0); + } + efx_mcdi_execute(enp, &req); - /* Invert EIO */ - if (req.emr_rc != EIO) { - rc = EIO; + if (req.emr_rc != 0) { + rc = req.emr_rc; goto fail1; } return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } - __checkReturn boolean_t -efx_mcdi_request_abort( +#endif /* EFSYS_OPT_BIST */ + + +/* Enable logging of some events (e.g. link state changes) */ + __checkReturn int +efx_mcdi_log_ctrl( __in efx_nic_t *enp) { - efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip); - efx_mcdi_req_t *emrp; - boolean_t aborted; - int state; + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_LOG_CTRL_IN_LEN, + MC_CMD_LOG_CTRL_OUT_LEN)]; + int rc; - EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); - EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI); + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_LOG_CTRL; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_LOG_CTRL_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_LOG_CTRL_OUT_LEN; + MCDI_IN_SET_DWORD(req, LOG_CTRL_IN_LOG_DEST, + MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ); + MCDI_IN_SET_DWORD(req, LOG_CTRL_IN_LOG_DEST_EVQ, 0); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + +#if EFSYS_OPT_MAC_STATS + +typedef enum efx_stats_action_e +{ + EFX_STATS_CLEAR, + EFX_STATS_UPLOAD, + EFX_STATS_ENABLE_NOEVENTS, + EFX_STATS_ENABLE_EVENTS, + EFX_STATS_DISABLE, +} efx_stats_action_t; + +static __checkReturn int +efx_mcdi_mac_stats( + __in efx_nic_t *enp, + __in_opt efsys_mem_t *esmp, + __in efx_stats_action_t action) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_MAC_STATS_IN_LEN, + MC_CMD_MAC_STATS_OUT_DMA_LEN)]; + int clear = (action == EFX_STATS_CLEAR); + int upload = (action == EFX_STATS_UPLOAD); + int enable = (action == EFX_STATS_ENABLE_NOEVENTS); + int events = (action == EFX_STATS_ENABLE_EVENTS); + int disable = (action == EFX_STATS_DISABLE); + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_MAC_STATS; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_MAC_STATS_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_MAC_STATS_OUT_DMA_LEN; + + MCDI_IN_POPULATE_DWORD_6(req, MAC_STATS_IN_CMD, + MAC_STATS_IN_DMA, upload, + MAC_STATS_IN_CLEAR, clear, + MAC_STATS_IN_PERIODIC_CHANGE, enable | events | disable, + MAC_STATS_IN_PERIODIC_ENABLE, enable | events, + MAC_STATS_IN_PERIODIC_NOEVENT, !events, + MAC_STATS_IN_PERIOD_MS, (enable | events) ? 1000: 0); + + if (esmp != NULL) { + int bytes = MC_CMD_MAC_NSTATS * sizeof (uint64_t); + + EFX_STATIC_ASSERT(MC_CMD_MAC_NSTATS * sizeof (uint64_t) <= + EFX_MAC_STATS_SIZE); + + MCDI_IN_SET_DWORD(req, MAC_STATS_IN_DMA_ADDR_LO, + EFSYS_MEM_ADDR(esmp) & 0xffffffff); + MCDI_IN_SET_DWORD(req, MAC_STATS_IN_DMA_ADDR_HI, + EFSYS_MEM_ADDR(esmp) >> 32); + MCDI_IN_SET_DWORD(req, MAC_STATS_IN_DMA_LEN, bytes); + } else { + EFSYS_ASSERT(!upload && !enable && !events); + } + /* - * efx_mcdi_ev_* may have already completed this event, and be - * spinning/blocked on the upper layer lock. So it *is* legitimate - * to for emi_pending_req to be NULL. If there is a pending event - * completed request, then provide a "credit" to allow - * efx_mcdi_ev_cpl() to accept a single spurious completion. + * NOTE: Do not use EVB_PORT_ID_ASSIGNED when disabling periodic stats, + * as this may fail (and leave periodic DMA enabled) if the + * vadapter has already been deleted. */ - EFSYS_LOCK(enp->en_eslp, state); - emrp = emip->emi_pending_req; - aborted = (emrp != NULL); - if (aborted) { - emip->emi_pending_req = NULL; + MCDI_IN_SET_DWORD(req, MAC_STATS_IN_PORT_ID, + (disable ? EVB_PORT_ID_NULL : enp->en_vport_id)); - /* Error the request */ - emrp->emr_out_length_used = 0; - emrp->emr_rc = ETIMEDOUT; + efx_mcdi_execute(enp, &req); - /* Provide a credit for seqno/emr_pending_req mismatches */ - if (emip->emi_ev_cpl) - ++emip->emi_aborted; - - /* - * The upper layer has called us, so we don't - * need to complete the request. - */ + if (req.emr_rc != 0) { + /* EF10: Expect ENOENT if no DMA queues are initialised */ + if ((req.emr_rc != ENOENT) || + (enp->en_rx_qcount + enp->en_tx_qcount != 0)) { + rc = req.emr_rc; + goto fail1; + } } - EFSYS_UNLOCK(enp->en_eslp, state); - return (aborted); + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); } - void -efx_mcdi_fini( + __checkReturn int +efx_mcdi_mac_stats_clear( __in efx_nic_t *enp) { - efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip); + int rc; - EFSYS_ASSERT3U(enp->en_mod_flags, ==, EFX_MOD_MCDI); - enp->en_mod_flags &= ~EFX_MOD_MCDI; + if ((rc = efx_mcdi_mac_stats(enp, NULL, EFX_STATS_CLEAR)) != 0) + goto fail1; - if (~(enp->en_features) & EFX_FEATURE_MCDI) - return; + return (0); - emip->emi_mtp = NULL; - emip->emi_port = 0; - emip->emi_aborted = 0; +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); } + + __checkReturn int +efx_mcdi_mac_stats_upload( + __in efx_nic_t *enp, + __in efsys_mem_t *esmp) +{ + int rc; + + /* + * The MC DMAs aggregate statistics for our convenience, so we can + * avoid having to pull the statistics buffer into the cache to + * maintain cumulative statistics. + */ + if ((rc = efx_mcdi_mac_stats(enp, esmp, EFX_STATS_UPLOAD)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +efx_mcdi_mac_stats_periodic( + __in efx_nic_t *enp, + __in efsys_mem_t *esmp, + __in uint16_t period, + __in boolean_t events) +{ + int rc; + + /* + * The MC DMAs aggregate statistics for our convenience, so we can + * avoid having to pull the statistics buffer into the cache to + * maintain cumulative statistics. + * Huntington uses a fixed 1sec period, so use that on Siena too. + */ + if (period == 0) + rc = efx_mcdi_mac_stats(enp, NULL, EFX_STATS_DISABLE); + else if (events) + rc = efx_mcdi_mac_stats(enp, esmp, EFX_STATS_ENABLE_EVENTS); + else + rc = efx_mcdi_mac_stats(enp, esmp, EFX_STATS_ENABLE_NOEVENTS); + + if (rc != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +#endif /* EFSYS_OPT_MAC_STATS */ + +#if EFSYS_OPT_HUNTINGTON + +/* + * This function returns the pf and vf number of a function. If it is a pf the + * vf number is 0xffff. The vf number is the index of the vf on that + * function. So if you have 3 vfs on pf 0 the 3 vfs will return (pf=0,vf=0), + * (pf=0,vf=1), (pf=0,vf=2) aand the pf will return (pf=0, vf=0xffff). + */ + __checkReturn int +efx_mcdi_get_function_info( + __in efx_nic_t *enp, + __out uint32_t *pfp, + __out_opt uint32_t *vfp) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_GET_FUNCTION_INFO_IN_LEN, + MC_CMD_GET_FUNCTION_INFO_OUT_LEN)]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_GET_FUNCTION_INFO; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_GET_FUNCTION_INFO_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_GET_FUNCTION_INFO_OUT_LEN; + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < MC_CMD_GET_FUNCTION_INFO_OUT_LEN) { + rc = EMSGSIZE; + goto fail2; + } + + *pfp = MCDI_OUT_DWORD(req, GET_FUNCTION_INFO_OUT_PF); + if (vfp != NULL) + *vfp = MCDI_OUT_DWORD(req, GET_FUNCTION_INFO_OUT_VF); + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +efx_mcdi_privilege_mask( + __in efx_nic_t *enp, + __in uint32_t pf, + __in uint32_t vf, + __out uint32_t *maskp) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_PRIVILEGE_MASK_IN_LEN, + MC_CMD_PRIVILEGE_MASK_OUT_LEN)]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_PRIVILEGE_MASK; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_PRIVILEGE_MASK_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_PRIVILEGE_MASK_OUT_LEN; + + MCDI_IN_POPULATE_DWORD_2(req, PRIVILEGE_MASK_IN_FUNCTION, + PRIVILEGE_MASK_IN_FUNCTION_PF, pf, + PRIVILEGE_MASK_IN_FUNCTION_VF, vf); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < MC_CMD_PRIVILEGE_MASK_OUT_LEN) { + rc = EMSGSIZE; + goto fail2; + } + + *maskp = MCDI_OUT_DWORD(req, PRIVILEGE_MASK_OUT_OLD_MASK); + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +#endif /* EFSYS_OPT_HUNTINGTON */ + + __checkReturn int +efx_mcdi_set_workaround( + __in efx_nic_t *enp, + __in uint32_t type, + __in boolean_t enabled, + __out_opt uint32_t *flagsp) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_WORKAROUND_IN_LEN, + MC_CMD_WORKAROUND_EXT_OUT_LEN)]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_WORKAROUND; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_WORKAROUND_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_WORKAROUND_OUT_LEN; + + MCDI_IN_SET_DWORD(req, WORKAROUND_IN_TYPE, type); + MCDI_IN_SET_DWORD(req, WORKAROUND_IN_ENABLED, enabled ? 1 : 0); + + efx_mcdi_execute_quiet(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (flagsp != NULL) { + if (req.emr_out_length_used >= MC_CMD_WORKAROUND_EXT_OUT_LEN) + *flagsp = MCDI_OUT_DWORD(req, WORKAROUND_EXT_OUT_FLAGS); + else + *flagsp = 0; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + + __checkReturn int +efx_mcdi_get_workarounds( + __in efx_nic_t *enp, + __out_opt uint32_t *implementedp, + __out_opt uint32_t *enabledp) +{ + efx_mcdi_req_t req; + uint8_t payload[MC_CMD_GET_WORKAROUNDS_OUT_LEN]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_GET_WORKAROUNDS; + req.emr_in_buf = NULL; + req.emr_in_length = 0; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_GET_WORKAROUNDS_OUT_LEN; + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (implementedp != NULL) { + *implementedp = + MCDI_OUT_DWORD(req, GET_WORKAROUNDS_OUT_IMPLEMENTED); + } + + if (enabledp != NULL) { + *enabledp = MCDI_OUT_DWORD(req, GET_WORKAROUNDS_OUT_ENABLED); + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + #endif /* EFSYS_OPT_MCDI */ Property changes on: head/sys/dev/sfxge/common/efx_mcdi.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_mcdi.h =================================================================== --- head/sys/dev/sfxge/common/efx_mcdi.h (revision 283513) +++ head/sys/dev/sfxge/common/efx_mcdi.h (revision 283514) @@ -1,243 +1,357 @@ /*- - * Copyright 2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2009-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + * * $FreeBSD$ */ #ifndef _SYS_EFX_MCDI_H #define _SYS_EFX_MCDI_H #include "efx.h" #include "efx_regs.h" #include "efx_regs_mcdi.h" #ifdef __cplusplus extern "C" { #endif -/* Number of retries attempted for init code */ -#define EFX_MCDI_REQ_RETRY_INIT 2 +/* + * A reboot/assertion causes the MCDI status word to be set after the + * command word is set or a REBOOT event is sent. If we notice a reboot + * via these mechanisms then wait 10ms for the status word to be set. + */ +#define EFX_MCDI_STATUS_SLEEP_US 10000 struct efx_mcdi_req_s { + boolean_t emr_quiet; /* Inputs: Command #, input buffer and length */ unsigned int emr_cmd; uint8_t *emr_in_buf; size_t emr_in_length; /* Outputs: retcode, buffer, length, and length used*/ int emr_rc; uint8_t *emr_out_buf; size_t emr_out_length; size_t emr_out_length_used; }; typedef struct efx_mcdi_iface_s { - const efx_mcdi_transport_t *emi_mtp; unsigned int emi_port; unsigned int emi_seq; efx_mcdi_req_t *emi_pending_req; boolean_t emi_ev_cpl; + boolean_t emi_new_epoch; int emi_aborted; uint32_t emi_poll_cnt; + uint32_t emi_mc_reboot_status; } efx_mcdi_iface_t; extern void efx_mcdi_execute( __in efx_nic_t *enp, - __in efx_mcdi_req_t *emrp); + __inout efx_mcdi_req_t *emrp); extern void +efx_mcdi_execute_quiet( + __in efx_nic_t *enp, + __inout efx_mcdi_req_t *emrp); + +extern void efx_mcdi_ev_cpl( __in efx_nic_t *enp, __in unsigned int seq, __in unsigned int outlen, __in int errcode); extern void efx_mcdi_ev_death( __in efx_nic_t *enp, __in int rc); +extern __checkReturn int +efx_mcdi_request_errcode( + __in unsigned int err); + +extern void +efx_mcdi_raise_exception( + __in efx_nic_t *enp, + __in_opt efx_mcdi_req_t *emrp, + __in int rc); + typedef enum efx_mcdi_boot_e { EFX_MCDI_BOOT_PRIMARY, EFX_MCDI_BOOT_SECONDARY, EFX_MCDI_BOOT_ROM, } efx_mcdi_boot_t; extern __checkReturn int efx_mcdi_version( __in efx_nic_t *enp, __out_ecount_opt(4) uint16_t versionp[4], __out_opt uint32_t *buildp, __out_opt efx_mcdi_boot_t *statusp); +extern __checkReturn int +efx_mcdi_read_assertion( + __in efx_nic_t *enp); + +extern __checkReturn int +efx_mcdi_exit_assertion_handler( + __in efx_nic_t *enp); + +extern __checkReturn int +efx_mcdi_drv_attach( + __in efx_nic_t *enp, + __in boolean_t attach); + +extern __checkReturn int +efx_mcdi_get_board_cfg( + __in efx_nic_t *enp, + __out_opt uint32_t *board_typep, + __out_opt efx_dword_t *capabilitiesp, + __out_ecount_opt(6) uint8_t mac_addrp[6]); + +extern __checkReturn int +efx_mcdi_get_phy_cfg( + __in efx_nic_t *enp); + +extern __checkReturn int +efx_mcdi_firmware_update_supported( + __in efx_nic_t *enp, + __out boolean_t *supportedp); + +extern __checkReturn int +efx_mcdi_macaddr_change_supported( + __in efx_nic_t *enp, + __out boolean_t *supportedp); + +#if EFSYS_OPT_BIST +#if EFSYS_OPT_HUNTINGTON +extern __checkReturn int +efx_mcdi_bist_enable_offline( + __in efx_nic_t *enp); +#endif /* EFSYS_OPT_HUNTINGTON */ +extern __checkReturn int +efx_mcdi_bist_start( + __in efx_nic_t *enp, + __in efx_bist_type_t type); +#endif /* EFSYS_OPT_BIST */ + +extern __checkReturn int +efx_mcdi_get_resource_limits( + __in efx_nic_t *enp, + __out_opt uint32_t *nevqp, + __out_opt uint32_t *nrxqp, + __out_opt uint32_t *ntxqp); + +extern __checkReturn int +efx_mcdi_log_ctrl( + __in efx_nic_t *enp); + +extern __checkReturn int +efx_mcdi_mac_stats_clear( + __in efx_nic_t *enp); + +extern __checkReturn int +efx_mcdi_mac_stats_upload( + __in efx_nic_t *enp, + __in efsys_mem_t *esmp); + +extern __checkReturn int +efx_mcdi_mac_stats_periodic( + __in efx_nic_t *enp, + __in efsys_mem_t *esmp, + __in uint16_t period, + __in boolean_t events); + + +#if EFSYS_OPT_LOOPBACK +extern __checkReturn int +efx_mcdi_get_loopback_modes( + __in efx_nic_t *enp); +#endif /* EFSYS_OPT_LOOPBACK */ + #define MCDI_IN(_emr, _type, _ofst) \ ((_type *)((_emr).emr_in_buf + (_ofst))) #define MCDI_IN2(_emr, _type, _ofst) \ MCDI_IN(_emr, _type, MC_CMD_ ## _ofst ## _OFST) #define MCDI_IN_SET_BYTE(_emr, _ofst, _value) \ EFX_POPULATE_BYTE_1(*MCDI_IN2(_emr, efx_byte_t, _ofst), \ EFX_BYTE_0, _value) +#define MCDI_IN_SET_WORD(_emr, _ofst, _value) \ + EFX_POPULATE_WORD_1(*MCDI_IN2(_emr, efx_word_t, _ofst), \ + EFX_WORD_0, _value) + #define MCDI_IN_SET_DWORD(_emr, _ofst, _value) \ EFX_POPULATE_DWORD_1(*MCDI_IN2(_emr, efx_dword_t, _ofst), \ EFX_DWORD_0, _value) +#define MCDI_IN_SET_DWORD_FIELD(_emr, _ofst, _field, _value) \ + EFX_SET_DWORD_FIELD(*MCDI_IN2(_emr, efx_dword_t, _ofst), \ + MC_CMD_ ## _field, _value) + #define MCDI_IN_POPULATE_DWORD_1(_emr, _ofst, _field1, _value1) \ EFX_POPULATE_DWORD_1(*MCDI_IN2(_emr, efx_dword_t, _ofst), \ MC_CMD_ ## _field1, _value1) #define MCDI_IN_POPULATE_DWORD_2(_emr, _ofst, _field1, _value1, \ _field2, _value2) \ EFX_POPULATE_DWORD_2(*MCDI_IN2(_emr, efx_dword_t, _ofst), \ MC_CMD_ ## _field1, _value1, \ MC_CMD_ ## _field2, _value2) #define MCDI_IN_POPULATE_DWORD_3(_emr, _ofst, _field1, _value1, \ _field2, _value2, _field3, _value3) \ EFX_POPULATE_DWORD_3(*MCDI_IN2(_emr, efx_dword_t, _ofst), \ MC_CMD_ ## _field1, _value1, \ MC_CMD_ ## _field2, _value2, \ MC_CMD_ ## _field3, _value3) #define MCDI_IN_POPULATE_DWORD_4(_emr, _ofst, _field1, _value1, \ _field2, _value2, _field3, _value3, _field4, _value4) \ EFX_POPULATE_DWORD_4(*MCDI_IN2(_emr, efx_dword_t, _ofst), \ MC_CMD_ ## _field1, _value1, \ MC_CMD_ ## _field2, _value2, \ MC_CMD_ ## _field3, _value3, \ MC_CMD_ ## _field4, _value4) #define MCDI_IN_POPULATE_DWORD_5(_emr, _ofst, _field1, _value1, \ _field2, _value2, _field3, _value3, _field4, _value4, \ _field5, _value5) \ EFX_POPULATE_DWORD_5(*MCDI_IN2(_emr, efx_dword_t, _ofst), \ MC_CMD_ ## _field1, _value1, \ MC_CMD_ ## _field2, _value2, \ MC_CMD_ ## _field3, _value3, \ MC_CMD_ ## _field4, _value4, \ MC_CMD_ ## _field5, _value5) #define MCDI_IN_POPULATE_DWORD_6(_emr, _ofst, _field1, _value1, \ _field2, _value2, _field3, _value3, _field4, _value4, \ _field5, _value5, _field6, _value6) \ EFX_POPULATE_DWORD_6(*MCDI_IN2(_emr, efx_dword_t, _ofst), \ MC_CMD_ ## _field1, _value1, \ MC_CMD_ ## _field2, _value2, \ MC_CMD_ ## _field3, _value3, \ MC_CMD_ ## _field4, _value4, \ MC_CMD_ ## _field5, _value5, \ MC_CMD_ ## _field6, _value6) #define MCDI_IN_POPULATE_DWORD_7(_emr, _ofst, _field1, _value1, \ _field2, _value2, _field3, _value3, _field4, _value4, \ _field5, _value5, _field6, _value6, _field7, _value7) \ - EFX_POPULATE_DWORD_7(MCDI_IN2(_emr, efx_dword_t, _ofst), \ + EFX_POPULATE_DWORD_7(*MCDI_IN2(_emr, efx_dword_t, _ofst), \ MC_CMD_ ## _field1, _value1, \ MC_CMD_ ## _field2, _value2, \ MC_CMD_ ## _field3, _value3, \ MC_CMD_ ## _field4, _value4, \ MC_CMD_ ## _field5, _value5, \ MC_CMD_ ## _field6, _value6, \ MC_CMD_ ## _field7, _value7) #define MCDI_IN_POPULATE_DWORD_8(_emr, _ofst, _field1, _value1, \ _field2, _value2, _field3, _value3, _field4, _value4, \ _field5, _value5, _field6, _value6, _field7, _value7, \ _field8, _value8) \ EFX_POPULATE_DWORD_8(*MCDI_IN2(_emr, efx_dword_t, _ofst), \ MC_CMD_ ## _field1, _value1, \ MC_CMD_ ## _field2, _value2, \ MC_CMD_ ## _field3, _value3, \ MC_CMD_ ## _field4, _value4, \ MC_CMD_ ## _field5, _value5, \ MC_CMD_ ## _field6, _value6, \ MC_CMD_ ## _field7, _value7, \ MC_CMD_ ## _field8, _value8) #define MCDI_IN_POPULATE_DWORD_9(_emr, _ofst, _field1, _value1, \ _field2, _value2, _field3, _value3, _field4, _value4, \ _field5, _value5, _field6, _value6, _field7, _value7, \ _field8, _value8, _field9, _value9) \ EFX_POPULATE_DWORD_9(*MCDI_IN2(_emr, efx_dword_t, _ofst), \ MC_CMD_ ## _field1, _value1, \ MC_CMD_ ## _field2, _value2, \ MC_CMD_ ## _field3, _value3, \ MC_CMD_ ## _field4, _value4, \ MC_CMD_ ## _field5, _value5, \ MC_CMD_ ## _field6, _value6, \ MC_CMD_ ## _field7, _value7, \ MC_CMD_ ## _field8, _value8, \ MC_CMD_ ## _field9, _value9) #define MCDI_IN_POPULATE_DWORD_10(_emr, _ofst, _field1, _value1, \ _field2, _value2, _field3, _value3, _field4, _value4, \ _field5, _value5, _field6, _value6, _field7, _value7, \ _field8, _value8, _field9, _value9, _field10, _value10) \ EFX_POPULATE_DWORD_10(*MCDI_IN2(_emr, efx_dword_t, _ofst), \ MC_CMD_ ## _field1, _value1, \ MC_CMD_ ## _field2, _value2, \ MC_CMD_ ## _field3, _value3, \ MC_CMD_ ## _field4, _value4, \ MC_CMD_ ## _field5, _value5, \ MC_CMD_ ## _field6, _value6, \ MC_CMD_ ## _field7, _value7, \ MC_CMD_ ## _field8, _value8, \ MC_CMD_ ## _field9, _value9, \ MC_CMD_ ## _field10, _value10) #define MCDI_OUT(_emr, _type, _ofst) \ ((_type *)((_emr).emr_out_buf + (_ofst))) #define MCDI_OUT2(_emr, _type, _ofst) \ MCDI_OUT(_emr, _type, MC_CMD_ ## _ofst ## _OFST) #define MCDI_OUT_BYTE(_emr, _ofst) \ EFX_BYTE_FIELD(*MCDI_OUT2(_emr, efx_byte_t, _ofst), \ EFX_BYTE_0) #define MCDI_OUT_WORD(_emr, _ofst) \ EFX_WORD_FIELD(*MCDI_OUT2(_emr, efx_word_t, _ofst), \ EFX_WORD_0) #define MCDI_OUT_DWORD(_emr, _ofst) \ EFX_DWORD_FIELD(*MCDI_OUT2(_emr, efx_dword_t, _ofst), \ EFX_DWORD_0) #define MCDI_OUT_DWORD_FIELD(_emr, _ofst, _field) \ EFX_DWORD_FIELD(*MCDI_OUT2(_emr, efx_dword_t, _ofst), \ MC_CMD_ ## _field) #define MCDI_EV_FIELD(_eqp, _field) \ EFX_QWORD_FIELD(*_eqp, MCDI_EVENT_ ## _field) -#define MCDI_CMD_DWORD_FIELD(_edp, _field) \ +#define MCDI_CMD_DWORD_FIELD(_edp, _field) \ EFX_DWORD_FIELD(*_edp, MC_CMD_ ## _field) #ifdef __cplusplus } #endif #endif /* _SYS_EFX_MCDI_H */ Property changes on: head/sys/dev/sfxge/common/efx_mcdi.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_mon.c =================================================================== --- head/sys/dev/sfxge/common/efx_mon.c (revision 283513) +++ head/sys/dev/sfxge/common/efx_mon.c (revision 283514) @@ -1,286 +1,346 @@ /*- - * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2007-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include "efsys.h" #include "efx.h" #include "efx_types.h" #include "efx_regs.h" #include "efx_impl.h" #if EFSYS_OPT_MON_NULL #include "nullmon.h" #endif #if EFSYS_OPT_MON_LM87 #include "lm87.h" #endif #if EFSYS_OPT_MON_MAX6647 #include "max6647.h" #endif +#if EFSYS_OPT_MON_MCDI +#include "mcdi_mon.h" +#endif + #if EFSYS_OPT_NAMES -static const char __cs * __cs __efx_mon_name[] = { +static const char *__efx_mon_name[] = { "", "nullmon", "lm87", "max6647", - "sfx90x0" + "sfx90x0", + "sfx91x0" }; - const char __cs * + const char * efx_mon_name( __in efx_nic_t *enp) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT(encp->enc_mon_type != EFX_MON_INVALID); EFSYS_ASSERT3U(encp->enc_mon_type, <, EFX_MON_NTYPES); return (__efx_mon_name[encp->enc_mon_type]); } #endif /* EFSYS_OPT_NAMES */ #if EFSYS_OPT_MON_NULL -static efx_mon_ops_t __cs __efx_mon_null_ops = { +static efx_mon_ops_t __efx_mon_null_ops = { nullmon_reset, /* emo_reset */ nullmon_reconfigure, /* emo_reconfigure */ #if EFSYS_OPT_MON_STATS - nullmon_stats_update /* emo_stat_update */ + nullmon_stats_update /* emo_stats_update */ #endif /* EFSYS_OPT_MON_STATS */ }; #endif #if EFSYS_OPT_MON_LM87 -static efx_mon_ops_t __cs __efx_mon_lm87_ops = { +static efx_mon_ops_t __efx_mon_lm87_ops = { lm87_reset, /* emo_reset */ lm87_reconfigure, /* emo_reconfigure */ #if EFSYS_OPT_MON_STATS - lm87_stats_update /* emo_stat_update */ + lm87_stats_update /* emo_stats_update */ #endif /* EFSYS_OPT_MON_STATS */ }; #endif #if EFSYS_OPT_MON_MAX6647 -static efx_mon_ops_t __cs __efx_mon_max6647_ops = { +static efx_mon_ops_t __efx_mon_max6647_ops = { max6647_reset, /* emo_reset */ max6647_reconfigure, /* emo_reconfigure */ #if EFSYS_OPT_MON_STATS - max6647_stats_update /* emo_stat_update */ + max6647_stats_update /* emo_stats_update */ #endif /* EFSYS_OPT_MON_STATS */ }; #endif -#if EFSYS_OPT_MON_SIENA -static efx_mon_ops_t __cs __efx_mon_siena_ops = { - siena_mon_reset, /* emo_reset */ - siena_mon_reconfigure, /* emo_reconfigure */ +#if EFSYS_OPT_MON_MCDI +static efx_mon_ops_t __efx_mon_mcdi_ops = { + NULL, /* emo_reset */ + NULL, /* emo_reconfigure */ #if EFSYS_OPT_MON_STATS - siena_mon_stats_update /* emo_stat_update */ + mcdi_mon_stats_update /* emo_stats_update */ #endif /* EFSYS_OPT_MON_STATS */ }; #endif - -static efx_mon_ops_t __cs * __cs __efx_mon_ops[] = { +static efx_mon_ops_t *__efx_mon_ops[] = { NULL, #if EFSYS_OPT_MON_NULL &__efx_mon_null_ops, #else NULL, #endif #if EFSYS_OPT_MON_LM87 &__efx_mon_lm87_ops, #else NULL, #endif #if EFSYS_OPT_MON_MAX6647 &__efx_mon_max6647_ops, #else NULL, #endif -#if EFSYS_OPT_MON_SIENA - &__efx_mon_siena_ops +#if EFSYS_OPT_MON_MCDI + &__efx_mon_mcdi_ops, #else + NULL, +#endif +#if EFSYS_OPT_MON_MCDI + &__efx_mon_mcdi_ops +#else NULL #endif }; __checkReturn int efx_mon_init( __in efx_nic_t *enp) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); efx_mon_t *emp = &(enp->en_mon); efx_mon_ops_t *emop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); if (enp->en_mod_flags & EFX_MOD_MON) { rc = EINVAL; goto fail1; } enp->en_mod_flags |= EFX_MOD_MON; emp->em_type = encp->enc_mon_type; EFSYS_ASSERT(encp->enc_mon_type != EFX_MON_INVALID); EFSYS_ASSERT3U(emp->em_type, <, EFX_MON_NTYPES); if ((emop = (efx_mon_ops_t *)__efx_mon_ops[emp->em_type]) == NULL) { rc = ENOTSUP; goto fail2; } - if ((rc = emop->emo_reset(enp)) != 0) - goto fail3; + if (emop->emo_reset != NULL) { + if ((rc = emop->emo_reset(enp)) != 0) + goto fail3; + } - if ((rc = emop->emo_reconfigure(enp)) != 0) - goto fail4; + if (emop->emo_reconfigure != NULL) { + if ((rc = emop->emo_reconfigure(enp)) != 0) + goto fail4; + } emp->em_emop = emop; return (0); fail4: EFSYS_PROBE(fail5); - (void) emop->emo_reset(enp); + if (emop->emo_reset != NULL) + (void) emop->emo_reset(enp); fail3: EFSYS_PROBE(fail4); fail2: EFSYS_PROBE(fail3); emp->em_type = EFX_MON_INVALID; enp->en_mod_flags &= ~EFX_MOD_MON; fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } #if EFSYS_OPT_MON_STATS #if EFSYS_OPT_NAMES -/* START MKCONFIG GENERATED MonitorStatNamesBlock 89ff37f1d74ad8b3 */ -static const char __cs * __cs __mon_stat_name[] = { +/* START MKCONFIG GENERATED MonitorStatNamesBlock b9328f15438c4d01 */ +static const char *__mon_stat_name[] = { "value_2_5v", "value_vccp1", "value_vcc", "value_5v", "value_12v", "value_vccp2", "value_ext_temp", "value_int_temp", "value_ain1", "value_ain2", "controller_cooling", "ext_cooling", "1v", "1_2v", "1_8v", "3_3v", "1_2va", "vref", "vaoe", "aoe_temperature", "psu_aoe_temperature", "psu_temperature", "fan0", "fan1", "fan2", "fan3", "fan4", "vaoe_in", "iaoe", "iaoe_in", + "nic_power", + "0_9v", + "i0_9v", + "i1_2v", + "0_9v_adc", + "controller_temperature2", + "vreg_temperature", + "vreg_0_9v_temperature", + "vreg_1_2v_temperature", + "int_vptat", + "controller_internal_adc_temperature", + "ext_vptat", + "controller_external_adc_temperature", + "ambient_temperature", + "airflow", + "vdd08d_vss08d_csr", + "vdd08d_vss08d_csr_extadc", + "hotpoint_temperature", + "phy_power_switch_port0", + "phy_power_switch_port1", + "mum_vcc", + "0v9_a", + "i0v9_a", + "0v9_a_temp", + "0v9_b", + "i0v9_b", + "0v9_b_temp", + "ccom_avreg_1v2_supply", + "ccom_avreg_1v2_supply_ext_adc", + "ccom_avreg_1v8_supply", + "ccom_avreg_1v8_supply_ext_adc", + "controller_master_vptat", + "controller_master_internal_temp", + "controller_master_vptat_ext_adc", + "controller_master_internal_temp_ext_adc", + "controller_slave_vptat", + "controller_slave_internal_temp", + "controller_slave_vptat_ext_adc", + "controller_slave_internal_temp_ext_adc", }; /* END MKCONFIG GENERATED MonitorStatNamesBlock */ -extern const char __cs * +extern const char * efx_mon_stat_name( __in efx_nic_t *enp, __in efx_mon_stat_t id) { _NOTE(ARGUNUSED(enp)) EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(id, <, EFX_MON_NSTATS); return (__mon_stat_name[id]); } #endif /* EFSYS_OPT_NAMES */ __checkReturn int efx_mon_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, __out_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values) { efx_mon_t *emp = &(enp->en_mon); efx_mon_ops_t *emop = emp->em_emop; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MON); return (emop->emo_stats_update(enp, esmp, values)); } #endif /* EFSYS_OPT_MON_STATS */ void efx_mon_fini( __in efx_nic_t *enp) { efx_mon_t *emp = &(enp->en_mon); efx_mon_ops_t *emop = emp->em_emop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MON); emp->em_emop = NULL; - rc = emop->emo_reset(enp); - if (rc != 0) - EFSYS_PROBE1(fail1, int, rc); + if (emop->emo_reset != NULL) { + rc = emop->emo_reset(enp); + if (rc != 0) + EFSYS_PROBE1(fail1, int, rc); + } emp->em_type = EFX_MON_INVALID; enp->en_mod_flags &= ~EFX_MOD_MON; } Property changes on: head/sys/dev/sfxge/common/efx_mon.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_nic.c =================================================================== --- head/sys/dev/sfxge/common/efx_nic.c (revision 283513) +++ head/sys/dev/sfxge/common/efx_nic.c (revision 283514) @@ -1,681 +1,1040 @@ /*- - * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2007-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include "efsys.h" #include "efx.h" #include "efx_types.h" #include "efx_regs.h" #include "efx_impl.h" __checkReturn int efx_family( __in uint16_t venid, __in uint16_t devid, __out efx_family_t *efp) { + if (venid == EFX_PCI_VENID_SFC) { + switch (devid) { #if EFSYS_OPT_FALCON - if (venid == EFX_PCI_VENID_SFC && devid == EFX_PCI_DEVID_FALCON) { - *efp = EFX_FAMILY_FALCON; - return (0); - } + case EFX_PCI_DEVID_FALCON: + *efp = EFX_FAMILY_FALCON; + return (0); #endif #if EFSYS_OPT_SIENA - if (venid == EFX_PCI_VENID_SFC && devid == EFX_PCI_DEVID_BETHPAGE) { - *efp = EFX_FAMILY_SIENA; - return (0); - } - if (venid == EFX_PCI_VENID_SFC && devid == EFX_PCI_DEVID_SIENA) { - *efp = EFX_FAMILY_SIENA; - return (0); - } - if (venid == EFX_PCI_VENID_SFC && - devid == EFX_PCI_DEVID_SIENA_F1_UNINIT) { - *efp = EFX_FAMILY_SIENA; - return (0); - } + case EFX_PCI_DEVID_SIENA_F1_UNINIT: + /* + * Hardware default for PF0 of uninitialised Siena. + * manftest must be able to cope with this device id. + */ + *efp = EFX_FAMILY_SIENA; + return (0); + + case EFX_PCI_DEVID_BETHPAGE: + case EFX_PCI_DEVID_SIENA: + *efp = EFX_FAMILY_SIENA; + return (0); #endif + +#if EFSYS_OPT_HUNTINGTON + case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT: + /* + * Hardware default for PF0 of uninitialised Huntington. + * manftest must be able to cope with this device id. + */ + *efp = EFX_FAMILY_HUNTINGTON; + return (0); + + case EFX_PCI_DEVID_FARMINGDALE: + case EFX_PCI_DEVID_GREENPORT: + case EFX_PCI_DEVID_HUNTINGTON: + *efp = EFX_FAMILY_HUNTINGTON; + return (0); + + case EFX_PCI_DEVID_FARMINGDALE_VF: + case EFX_PCI_DEVID_GREENPORT_VF: + case EFX_PCI_DEVID_HUNTINGTON_VF: + *efp = EFX_FAMILY_HUNTINGTON; + return (0); +#endif + default: + break; + } + } + + *efp = EFX_FAMILY_INVALID; return (ENOTSUP); } /* * To support clients which aren't provided with any PCI context infer * the hardware family by inspecting the hardware. Obviously the caller * must be damn sure they're really talking to a supported device. */ __checkReturn int efx_infer_family( __in efsys_bar_t *esbp, __out efx_family_t *efp) { efx_family_t family; efx_oword_t oword; unsigned int portnum; int rc; EFSYS_BAR_READO(esbp, FR_AZ_CS_DEBUG_REG_OFST, &oword, B_TRUE); portnum = EFX_OWORD_FIELD(oword, FRF_CZ_CS_PORT_NUM); switch (portnum) { + case 0: { + efx_dword_t dword; + uint32_t hw_rev; + + EFSYS_BAR_READD(esbp, ER_DZ_BIU_HW_REV_ID_REG_OFST, &dword, + B_TRUE); + hw_rev = EFX_DWORD_FIELD(dword, ERF_DZ_HW_REV_ID); + if (hw_rev == ER_DZ_BIU_HW_REV_ID_REG_RESET) { +#if EFSYS_OPT_HUNTINGTON + family = EFX_FAMILY_HUNTINGTON; + break; +#endif + } else { #if EFSYS_OPT_FALCON - case 0: - family = EFX_FAMILY_FALCON; - break; + family = EFX_FAMILY_FALCON; + break; #endif + } + rc = ENOTSUP; + goto fail1; + } + #if EFSYS_OPT_SIENA case 1: case 2: family = EFX_FAMILY_SIENA; break; #endif default: rc = ENOTSUP; goto fail1; } if (efp != NULL) *efp = family; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } -/* - * The built-in default value device id for port 1 of Siena is 0x0810. - * manftest needs to be able to cope with that. - */ - #define EFX_BIU_MAGIC0 0x01234567 #define EFX_BIU_MAGIC1 0xfedcba98 -static __checkReturn int + __checkReturn int efx_nic_biu_test( __in efx_nic_t *enp) { efx_oword_t oword; int rc; /* * Write magic values to scratch registers 0 and 1, then * verify that the values were written correctly. Interleave * the accesses to ensure that the BIU is not just reading * back the cached value that was last written. */ EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0); - EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword); + EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE); EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1); - EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword); + EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE); - EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword); + EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE); if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) { rc = EIO; goto fail1; } - EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword); + EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE); if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) { rc = EIO; goto fail2; } /* * Perform the same test, with the values swapped. This * ensures that subsequent tests don't start with the correct * values already written into the scratch registers. */ EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1); - EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword); + EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE); EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0); - EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword); + EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE); - EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword); + EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE); if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) { rc = EIO; goto fail3; } - EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword); + EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE); if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) { rc = EIO; goto fail4; } return (0); fail4: EFSYS_PROBE(fail4); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } #if EFSYS_OPT_FALCON -static efx_nic_ops_t __cs __efx_nic_falcon_ops = { +static efx_nic_ops_t __efx_nic_falcon_ops = { falcon_nic_probe, /* eno_probe */ + NULL, /* eno_set_drv_limits */ falcon_nic_reset, /* eno_reset */ falcon_nic_init, /* eno_init */ + NULL, /* eno_get_vi_pool */ + NULL, /* eno_get_bar_region */ #if EFSYS_OPT_DIAG falcon_sram_test, /* eno_sram_test */ falcon_nic_register_test, /* eno_register_test */ #endif /* EFSYS_OPT_DIAG */ falcon_nic_fini, /* eno_fini */ falcon_nic_unprobe, /* eno_unprobe */ }; #endif /* EFSYS_OPT_FALCON */ #if EFSYS_OPT_SIENA -static efx_nic_ops_t __cs __efx_nic_siena_ops = { +static efx_nic_ops_t __efx_nic_siena_ops = { siena_nic_probe, /* eno_probe */ + NULL, /* eno_set_drv_limits */ siena_nic_reset, /* eno_reset */ siena_nic_init, /* eno_init */ + NULL, /* eno_get_vi_pool */ + NULL, /* eno_get_bar_region */ #if EFSYS_OPT_DIAG siena_sram_test, /* eno_sram_test */ siena_nic_register_test, /* eno_register_test */ #endif /* EFSYS_OPT_DIAG */ siena_nic_fini, /* eno_fini */ siena_nic_unprobe, /* eno_unprobe */ }; #endif /* EFSYS_OPT_SIENA */ +#if EFSYS_OPT_HUNTINGTON + +static efx_nic_ops_t __efx_nic_hunt_ops = { + hunt_nic_probe, /* eno_probe */ + hunt_nic_set_drv_limits, /* eno_set_drv_limits */ + hunt_nic_reset, /* eno_reset */ + hunt_nic_init, /* eno_init */ + hunt_nic_get_vi_pool, /* eno_get_vi_pool */ + hunt_nic_get_bar_region, /* eno_get_bar_region */ +#if EFSYS_OPT_DIAG + hunt_sram_test, /* eno_sram_test */ + hunt_nic_register_test, /* eno_register_test */ +#endif /* EFSYS_OPT_DIAG */ + hunt_nic_fini, /* eno_fini */ + hunt_nic_unprobe, /* eno_unprobe */ +}; + +#endif /* EFSYS_OPT_HUNTINGTON */ + __checkReturn int efx_nic_create( __in efx_family_t family, __in efsys_identifier_t *esip, __in efsys_bar_t *esbp, __in efsys_lock_t *eslp, __deref_out efx_nic_t **enpp) { efx_nic_t *enp; int rc; EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID); EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES); /* Allocate a NIC object */ EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp); if (enp == NULL) { rc = ENOMEM; goto fail1; } enp->en_magic = EFX_NIC_MAGIC; switch (family) { #if EFSYS_OPT_FALCON case EFX_FAMILY_FALCON: enp->en_enop = (efx_nic_ops_t *)&__efx_nic_falcon_ops; enp->en_features = 0; break; #endif /* EFSYS_OPT_FALCON */ #if EFSYS_OPT_SIENA case EFX_FAMILY_SIENA: enp->en_enop = (efx_nic_ops_t *)&__efx_nic_siena_ops; enp->en_features = EFX_FEATURE_IPV6 | EFX_FEATURE_LFSR_HASH_INSERT | EFX_FEATURE_LINK_EVENTS | EFX_FEATURE_PERIODIC_MAC_STATS | EFX_FEATURE_WOL | EFX_FEATURE_MCDI | EFX_FEATURE_LOOKAHEAD_SPLIT | - EFX_FEATURE_MAC_HEADER_FILTERS; + EFX_FEATURE_MAC_HEADER_FILTERS | + EFX_FEATURE_TX_SRC_FILTERS; break; #endif /* EFSYS_OPT_SIENA */ +#if EFSYS_OPT_HUNTINGTON + case EFX_FAMILY_HUNTINGTON: + enp->en_enop = (efx_nic_ops_t *)&__efx_nic_hunt_ops; + /* FIXME: Add WOL support */ + enp->en_features = + EFX_FEATURE_IPV6 | + EFX_FEATURE_LINK_EVENTS | + EFX_FEATURE_PERIODIC_MAC_STATS | + EFX_FEATURE_MCDI | + EFX_FEATURE_MAC_HEADER_FILTERS | + EFX_FEATURE_MCDI_DMA | + EFX_FEATURE_PIO_BUFFERS | + EFX_FEATURE_FW_ASSISTED_TSO; + break; +#endif /* EFSYS_OPT_HUNTINGTON */ + default: rc = ENOTSUP; goto fail2; } enp->en_family = family; enp->en_esip = esip; enp->en_esbp = esbp; enp->en_eslp = eslp; *enpp = enp; return (0); fail2: - EFSYS_PROBE(fail3); + EFSYS_PROBE(fail2); enp->en_magic = 0; /* Free the NIC object */ EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_nic_probe( __in efx_nic_t *enp) { efx_nic_ops_t *enop; - efx_oword_t oword; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); #if EFSYS_OPT_MCDI EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); #endif /* EFSYS_OPT_MCDI */ EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE)); - /* Test BIU */ - if ((rc = efx_nic_biu_test(enp)) != 0) - goto fail1; - - /* Clear the region register */ - EFX_POPULATE_OWORD_4(oword, - FRF_AZ_ADR_REGION0, 0, - FRF_AZ_ADR_REGION1, (1 << 16), - FRF_AZ_ADR_REGION2, (2 << 16), - FRF_AZ_ADR_REGION3, (3 << 16)); - EFX_BAR_WRITEO(enp, FR_AZ_ADR_REGION_REG, &oword); - enop = enp->en_enop; if ((rc = enop->eno_probe(enp)) != 0) - goto fail2; + goto fail1; if ((rc = efx_phy_probe(enp)) != 0) - goto fail3; + goto fail2; enp->en_mod_flags |= EFX_MOD_PROBE; return (0); -fail3: - EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); enop->eno_unprobe(enp); -fail2: - EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } #if EFSYS_OPT_PCIE_TUNE __checkReturn int efx_nic_pcie_tune( __in efx_nic_t *enp, unsigned int nlanes) { EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC)); #if EFSYS_OPT_FALCON if (enp->en_family == EFX_FAMILY_FALCON) return (falcon_nic_pcie_tune(enp, nlanes)); #endif return (ENOTSUP); } __checkReturn int efx_nic_pcie_extended_sync( __in efx_nic_t *enp) { EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC)); #if EFSYS_OPT_SIENA if (enp->en_family == EFX_FAMILY_SIENA) return (siena_nic_pcie_extended_sync(enp)); #endif return (ENOTSUP); } #endif /* EFSYS_OPT_PCIE_TUNE */ __checkReturn int +efx_nic_set_drv_limits( + __inout efx_nic_t *enp, + __in efx_drv_limits_t *edlp) +{ + efx_nic_ops_t *enop = enp->en_enop; + int rc; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); + + if (enop->eno_set_drv_limits != NULL) { + if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0) + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +efx_nic_get_bar_region( + __in efx_nic_t *enp, + __in efx_nic_region_t region, + __out uint32_t *offsetp, + __out size_t *sizep) +{ + efx_nic_ops_t *enop = enp->en_enop; + int rc; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); + + if (enop->eno_get_bar_region == NULL) { + rc = ENOTSUP; + goto fail1; + } + if ((rc = (enop->eno_get_bar_region)(enp, + region, offsetp, sizep)) != 0) { + goto fail2; + } + + return (0); + +fail2: + EFSYS_PROBE(fail2); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + + __checkReturn int +efx_nic_get_vi_pool( + __in efx_nic_t *enp, + __out uint32_t *evq_countp, + __out uint32_t *rxq_countp, + __out uint32_t *txq_countp) +{ + efx_nic_ops_t *enop = enp->en_enop; + efx_nic_cfg_t *encp = &enp->en_nic_cfg; + int rc; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); + + if (enop->eno_get_vi_pool != NULL) { + uint32_t vi_count = 0; + + if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0) + goto fail1; + + *evq_countp = vi_count; + *rxq_countp = vi_count; + *txq_countp = vi_count; + } else { + /* Use NIC limits as default value */ + *evq_countp = encp->enc_evq_limit; + *rxq_countp = encp->enc_rxq_limit; + *txq_countp = encp->enc_txq_limit; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + + __checkReturn int efx_nic_init( __in efx_nic_t *enp) { efx_nic_ops_t *enop = enp->en_enop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); if (enp->en_mod_flags & EFX_MOD_NIC) { rc = EINVAL; goto fail1; } if ((rc = enop->eno_init(enp)) != 0) goto fail2; enp->en_mod_flags |= EFX_MOD_NIC; return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } void efx_nic_fini( __in efx_nic_t *enp) { efx_nic_ops_t *enop = enp->en_enop; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE); EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC); EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR)); EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV)); EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX)); EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX)); enop->eno_fini(enp); enp->en_mod_flags &= ~EFX_MOD_NIC; } void efx_nic_unprobe( __in efx_nic_t *enp) { efx_nic_ops_t *enop = enp->en_enop; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); #if EFSYS_OPT_MCDI EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); #endif /* EFSYS_OPT_MCDI */ EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC)); EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR)); EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV)); EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX)); EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX)); efx_phy_unprobe(enp); enop->eno_unprobe(enp); enp->en_mod_flags &= ~EFX_MOD_PROBE; } void efx_nic_destroy( __in efx_nic_t *enp) { efsys_identifier_t *esip = enp->en_esip; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0); enp->en_family = 0; enp->en_esip = NULL; enp->en_esbp = NULL; enp->en_eslp = NULL; enp->en_enop = NULL; enp->en_magic = 0; /* Free the NIC object */ EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp); } __checkReturn int efx_nic_reset( __in efx_nic_t *enp) { efx_nic_ops_t *enop = enp->en_enop; unsigned int mod_flags; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE); /* * All modules except the MCDI, PROBE, NVRAM, VPD, MON (which we * do not reset here) must have been shut down or never initialized. * * A rule of thumb here is: If the controller or MC reboots, is *any* * state lost. If it's lost and needs reapplying, then the module * *must* not be initialised during the reset. */ mod_flags = enp->en_mod_flags; mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM | EFX_MOD_VPD | EFX_MOD_MON); EFSYS_ASSERT3U(mod_flags, ==, 0); if (mod_flags != 0) { rc = EINVAL; goto fail1; } if ((rc = enop->eno_reset(enp)) != 0) goto fail2; enp->en_reset_flags |= EFX_RESET_MAC; return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } const efx_nic_cfg_t * efx_nic_cfg_get( __in efx_nic_t *enp) { EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); return (&(enp->en_nic_cfg)); } #if EFSYS_OPT_DIAG __checkReturn int efx_nic_register_test( __in efx_nic_t *enp) { efx_nic_ops_t *enop = enp->en_enop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC)); if ((rc = enop->eno_register_test(enp)) != 0) goto fail1; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_nic_test_registers( __in efx_nic_t *enp, __in efx_register_set_t *rsp, __in size_t count) { unsigned int bit; efx_oword_t original; efx_oword_t reg; efx_oword_t buf; int rc; while (count > 0) { /* This function is only suitable for registers */ EFSYS_ASSERT(rsp->rows == 1); /* bit sweep on and off */ EFSYS_BAR_READO(enp->en_esbp, rsp->address, &original, B_TRUE); for (bit = 0; bit < 128; bit++) { /* Is this bit in the mask? */ if (~(rsp->mask.eo_u32[bit >> 5]) & (1 << bit)) continue; /* Test this bit can be set in isolation */ reg = original; EFX_AND_OWORD(reg, rsp->mask); EFX_SET_OWORD_BIT(reg, bit); EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®, B_TRUE); EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf, B_TRUE); EFX_AND_OWORD(buf, rsp->mask); if (memcmp(®, &buf, sizeof (reg))) { rc = EIO; goto fail1; } /* Test this bit can be cleared in isolation */ EFX_OR_OWORD(reg, rsp->mask); EFX_CLEAR_OWORD_BIT(reg, bit); EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®, B_TRUE); EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf, B_TRUE); EFX_AND_OWORD(buf, rsp->mask); if (memcmp(®, &buf, sizeof (reg))) { rc = EIO; goto fail2; } } /* Restore the old value */ EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original, B_TRUE); --count; ++rsp; } return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); /* Restore the old value */ EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original, B_TRUE); return (rc); } __checkReturn int efx_nic_test_tables( __in efx_nic_t *enp, __in efx_register_set_t *rsp, __in efx_pattern_type_t pattern, __in size_t count) { efx_sram_pattern_fn_t func; unsigned int index; unsigned int address; efx_oword_t reg; efx_oword_t buf; int rc; EFSYS_ASSERT(pattern < EFX_PATTERN_NTYPES); func = __efx_sram_pattern_fns[pattern]; while (count > 0) { /* Write */ address = rsp->address; for (index = 0; index < rsp->rows; ++index) { func(2 * index + 0, B_FALSE, ®.eo_qword[0]); func(2 * index + 1, B_FALSE, ®.eo_qword[1]); EFX_AND_OWORD(reg, rsp->mask); EFSYS_BAR_WRITEO(enp->en_esbp, address, ®, B_TRUE); address += rsp->step; } /* Read */ address = rsp->address; for (index = 0; index < rsp->rows; ++index) { func(2 * index + 0, B_FALSE, ®.eo_qword[0]); func(2 * index + 1, B_FALSE, ®.eo_qword[1]); EFX_AND_OWORD(reg, rsp->mask); EFSYS_BAR_READO(enp->en_esbp, address, &buf, B_TRUE); if (memcmp(®, &buf, sizeof (reg))) { rc = EIO; goto fail1; } address += rsp->step; } ++rsp; --count; } return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } #endif /* EFSYS_OPT_DIAG */ + +#if EFSYS_OPT_LOOPBACK + +extern void +efx_loopback_mask( + __in efx_loopback_kind_t loopback_kind, + __out efx_qword_t *maskp) +{ + efx_qword_t mask; + + EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS); + EFSYS_ASSERT(maskp != NULL); + + /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespace agree */ + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_NONE == EFX_LOOPBACK_OFF); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_DATA == EFX_LOOPBACK_DATA); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMAC == EFX_LOOPBACK_GMAC); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII == EFX_LOOPBACK_XGMII); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGXS == EFX_LOOPBACK_XGXS); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI == EFX_LOOPBACK_XAUI); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII == EFX_LOOPBACK_GMII); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII == EFX_LOOPBACK_SGMII); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGBR == EFX_LOOPBACK_XGBR); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI == EFX_LOOPBACK_XFI); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_FAR == EFX_LOOPBACK_XAUI_FAR); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_FAR == EFX_LOOPBACK_GMII_FAR); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII_FAR == EFX_LOOPBACK_SGMII_FAR); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_FAR == EFX_LOOPBACK_XFI_FAR); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GPHY == EFX_LOOPBACK_GPHY); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS == EFX_LOOPBACK_PHY_XS); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PCS == EFX_LOOPBACK_PCS); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMAPMD == EFX_LOOPBACK_PMA_PMD); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XPORT == EFX_LOOPBACK_XPORT); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII_WS == EFX_LOOPBACK_XGMII_WS); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_WS == EFX_LOOPBACK_XAUI_WS); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_WS_FAR == + EFX_LOOPBACK_XAUI_WS_FAR); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_WS_NEAR == + EFX_LOOPBACK_XAUI_WS_NEAR); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_WS == EFX_LOOPBACK_GMII_WS); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_WS == EFX_LOOPBACK_XFI_WS); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_WS_FAR == + EFX_LOOPBACK_XFI_WS_FAR); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS_WS == EFX_LOOPBACK_PHYXS_WS); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMA_INT == EFX_LOOPBACK_PMA_INT); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_NEAR == EFX_LOOPBACK_SD_NEAR); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FAR == EFX_LOOPBACK_SD_FAR); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMA_INT_WS == + EFX_LOOPBACK_PMA_INT_WS); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FEP2_WS == + EFX_LOOPBACK_SD_FEP2_WS); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FEP1_5_WS == + EFX_LOOPBACK_SD_FEP1_5_WS); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FEP_WS == EFX_LOOPBACK_SD_FEP_WS); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FES_WS == EFX_LOOPBACK_SD_FES_WS); + + /* Build bitmask of possible loopback types */ + EFX_ZERO_QWORD(mask); + + if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) || + (loopback_kind == EFX_LOOPBACK_KIND_ALL)) { + EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF); + } + + if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) || + (loopback_kind == EFX_LOOPBACK_KIND_ALL)) { + /* + * The "MAC" grouping has historically been used by drivers to + * mean loopbacks supported by on-chip hardware. Keep that + * meaning here, and include on-chip PHY layer loopbacks. + */ + EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA); + EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC); + EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII); + EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS); + EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI); + EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII); + EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII); + EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR); + EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI); + EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR); + EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR); + EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR); + EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR); + EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT); + EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR); + EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR); + } + + if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) || + (loopback_kind == EFX_LOOPBACK_KIND_ALL)) { + /* + * The "PHY" grouping has historically been used by drivers to + * mean loopbacks supported by off-chip hardware. Keep that + * meaning here. + */ + EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY); + EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PHY_XS); + EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS); + EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD); + } + + *maskp = mask; +} + +__checkReturn int +efx_mcdi_get_loopback_modes( + __in efx_nic_t *enp) +{ + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_GET_LOOPBACK_MODES_IN_LEN, + MC_CMD_GET_LOOPBACK_MODES_OUT_LEN)]; + efx_qword_t mask; + efx_qword_t modes; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_LEN; + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < + MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST + + MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) { + rc = EMSGSIZE; + goto fail2; + } + + /* + * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree + * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link(). + */ + efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask); + + EFX_AND_QWORD(mask, + *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED)); + + modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M); + EFX_AND_QWORD(modes, mask); + encp->enc_loopback_types[EFX_LINK_100FDX] = modes; + + modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G); + EFX_AND_QWORD(modes, mask); + encp->enc_loopback_types[EFX_LINK_1000FDX] = modes; + + modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G); + EFX_AND_QWORD(modes, mask); + encp->enc_loopback_types[EFX_LINK_10000FDX] = modes; + + if (req.emr_out_length_used >= + MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST + + MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) { + /* Response includes 40G loopback modes */ + modes = + *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_40G); + EFX_AND_QWORD(modes, mask); + encp->enc_loopback_types[EFX_LINK_40000FDX] = modes; + } + + EFX_ZERO_QWORD(modes); + EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF); + EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]); + EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]); + EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]); + EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]); + encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes; + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +#endif /* EFSYS_OPT_LOOPBACK */ Property changes on: head/sys/dev/sfxge/common/efx_nic.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_nvram.c =================================================================== --- head/sys/dev/sfxge/common/efx_nvram.c (revision 283513) +++ head/sys/dev/sfxge/common/efx_nvram.c (revision 283514) @@ -1,375 +1,887 @@ /*- - * Copyright 2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2009-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include "efsys.h" #include "efx.h" #include "efx_types.h" #include "efx_regs.h" #include "efx_impl.h" #if EFSYS_OPT_NVRAM #if EFSYS_OPT_FALCON -static efx_nvram_ops_t __cs __efx_nvram_falcon_ops = { +static efx_nvram_ops_t __efx_nvram_falcon_ops = { #if EFSYS_OPT_DIAG falcon_nvram_test, /* envo_test */ #endif /* EFSYS_OPT_DIAG */ falcon_nvram_size, /* envo_size */ falcon_nvram_get_version, /* envo_get_version */ falcon_nvram_rw_start, /* envo_rw_start */ falcon_nvram_read_chunk, /* envo_read_chunk */ falcon_nvram_erase, /* envo_erase */ falcon_nvram_write_chunk, /* envo_write_chunk */ falcon_nvram_rw_finish, /* envo_rw_finish */ falcon_nvram_set_version, /* envo_set_version */ }; #endif /* EFSYS_OPT_FALCON */ #if EFSYS_OPT_SIENA -static efx_nvram_ops_t __cs __efx_nvram_siena_ops = { +static efx_nvram_ops_t __efx_nvram_siena_ops = { #if EFSYS_OPT_DIAG siena_nvram_test, /* envo_test */ #endif /* EFSYS_OPT_DIAG */ siena_nvram_size, /* envo_size */ siena_nvram_get_version, /* envo_get_version */ siena_nvram_rw_start, /* envo_rw_start */ siena_nvram_read_chunk, /* envo_read_chunk */ siena_nvram_erase, /* envo_erase */ siena_nvram_write_chunk, /* envo_write_chunk */ siena_nvram_rw_finish, /* envo_rw_finish */ siena_nvram_set_version, /* envo_set_version */ }; #endif /* EFSYS_OPT_SIENA */ +#if EFSYS_OPT_HUNTINGTON + +static efx_nvram_ops_t __efx_nvram_hunt_ops = { +#if EFSYS_OPT_DIAG + hunt_nvram_test, /* envo_test */ +#endif /* EFSYS_OPT_DIAG */ + hunt_nvram_size, /* envo_size */ + hunt_nvram_get_version, /* envo_get_version */ + hunt_nvram_rw_start, /* envo_rw_start */ + hunt_nvram_read_chunk, /* envo_read_chunk */ + hunt_nvram_erase, /* envo_erase */ + hunt_nvram_write_chunk, /* envo_write_chunk */ + hunt_nvram_rw_finish, /* envo_rw_finish */ + hunt_nvram_set_version, /* envo_set_version */ +}; + +#endif /* EFSYS_OPT_HUNTINGTON */ + __checkReturn int efx_nvram_init( __in efx_nic_t *enp) { efx_nvram_ops_t *envop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NVRAM)); switch (enp->en_family) { #if EFSYS_OPT_FALCON case EFX_FAMILY_FALCON: envop = (efx_nvram_ops_t *)&__efx_nvram_falcon_ops; break; #endif /* EFSYS_OPT_FALCON */ #if EFSYS_OPT_SIENA case EFX_FAMILY_SIENA: envop = (efx_nvram_ops_t *)&__efx_nvram_siena_ops; break; #endif /* EFSYS_OPT_SIENA */ +#if EFSYS_OPT_HUNTINGTON + case EFX_FAMILY_HUNTINGTON: + envop = (efx_nvram_ops_t *)&__efx_nvram_hunt_ops; + break; +#endif /* EFSYS_OPT_HUNTINGTON */ + default: EFSYS_ASSERT(0); rc = ENOTSUP; goto fail1; } enp->en_envop = envop; enp->en_mod_flags |= EFX_MOD_NVRAM; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } #if EFSYS_OPT_DIAG __checkReturn int efx_nvram_test( __in efx_nic_t *enp) { efx_nvram_ops_t *envop = enp->en_envop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NVRAM); if ((rc = envop->envo_test(enp)) != 0) goto fail1; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } #endif /* EFSYS_OPT_DIAG */ __checkReturn int efx_nvram_size( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out size_t *sizep) { efx_nvram_ops_t *envop = enp->en_envop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NVRAM); EFSYS_ASSERT3U(type, <, EFX_NVRAM_NTYPES); if ((rc = envop->envo_size(enp, type, sizep)) != 0) goto fail1; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_nvram_get_version( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out uint32_t *subtypep, __out_ecount(4) uint16_t version[4]) { efx_nvram_ops_t *envop = enp->en_envop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NVRAM); EFSYS_ASSERT3U(type, <, EFX_NVRAM_NTYPES); if ((rc = envop->envo_get_version(enp, type, subtypep, version)) != 0) goto fail1; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_nvram_rw_start( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out_opt size_t *chunk_sizep) { efx_nvram_ops_t *envop = enp->en_envop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NVRAM); EFSYS_ASSERT3U(type, <, EFX_NVRAM_NTYPES); EFSYS_ASSERT3U(type, !=, EFX_NVRAM_INVALID); EFSYS_ASSERT3U(enp->en_nvram_locked, ==, EFX_NVRAM_INVALID); if ((rc = envop->envo_rw_start(enp, type, chunk_sizep)) != 0) goto fail1; enp->en_nvram_locked = type; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_nvram_read_chunk( __in efx_nic_t *enp, __in efx_nvram_type_t type, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size) { efx_nvram_ops_t *envop = enp->en_envop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NVRAM); EFSYS_ASSERT3U(type, <, EFX_NVRAM_NTYPES); EFSYS_ASSERT3U(type, !=, EFX_NVRAM_INVALID); EFSYS_ASSERT3U(enp->en_nvram_locked, ==, type); if ((rc = envop->envo_read_chunk(enp, type, offset, data, size)) != 0) goto fail1; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_nvram_erase( __in efx_nic_t *enp, __in efx_nvram_type_t type) { efx_nvram_ops_t *envop = enp->en_envop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NVRAM); EFSYS_ASSERT3U(type, <, EFX_NVRAM_NTYPES); EFSYS_ASSERT3U(type, !=, EFX_NVRAM_INVALID); EFSYS_ASSERT3U(enp->en_nvram_locked, ==, type); if ((rc = envop->envo_erase(enp, type)) != 0) goto fail1; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_nvram_write_chunk( __in efx_nic_t *enp, __in efx_nvram_type_t type, __in unsigned int offset, __in_bcount(size) caddr_t data, __in size_t size) { efx_nvram_ops_t *envop = enp->en_envop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NVRAM); EFSYS_ASSERT3U(type, <, EFX_NVRAM_NTYPES); EFSYS_ASSERT3U(type, !=, EFX_NVRAM_INVALID); EFSYS_ASSERT3U(enp->en_nvram_locked, ==, type); if ((rc = envop->envo_write_chunk(enp, type, offset, data, size)) != 0) goto fail1; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } void efx_nvram_rw_finish( __in efx_nic_t *enp, __in efx_nvram_type_t type) { efx_nvram_ops_t *envop = enp->en_envop; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NVRAM); EFSYS_ASSERT3U(type, <, EFX_NVRAM_NTYPES); EFSYS_ASSERT3U(type, !=, EFX_NVRAM_INVALID); EFSYS_ASSERT3U(enp->en_nvram_locked, ==, type); envop->envo_rw_finish(enp, type); enp->en_nvram_locked = EFX_NVRAM_INVALID; } __checkReturn int efx_nvram_set_version( __in efx_nic_t *enp, __in efx_nvram_type_t type, - __out uint16_t version[4]) + __in_ecount(4) uint16_t version[4]) { efx_nvram_ops_t *envop = enp->en_envop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NVRAM); EFSYS_ASSERT3U(type, <, EFX_NVRAM_NTYPES); /* * The Siena implementation of envo_set_version() will attempt to * acquire the NVRAM_UPDATE lock for the DYNAMIC_CONFIG sector. * Therefore, you can't have already acquired the NVRAM_UPDATE lock. */ EFSYS_ASSERT3U(enp->en_nvram_locked, ==, EFX_NVRAM_INVALID); if ((rc = envop->envo_set_version(enp, type, version)) != 0) goto fail1; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } void efx_nvram_fini( __in efx_nic_t *enp) { EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NVRAM); EFSYS_ASSERT3U(enp->en_nvram_locked, ==, EFX_NVRAM_INVALID); enp->en_envop = NULL; enp->en_mod_flags &= ~EFX_MOD_NVRAM; } #endif /* EFSYS_OPT_NVRAM */ + +#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD + +/* + * Internal MCDI request handling + */ + + __checkReturn int +efx_mcdi_nvram_partitions( + __in efx_nic_t *enp, + __out_bcount(size) caddr_t data, + __in size_t size, + __out unsigned int *npartnp) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_NVRAM_PARTITIONS_IN_LEN, + MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX)]; + unsigned int npartn; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_NVRAM_PARTITIONS; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_NVRAM_PARTITIONS_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX; + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN) { + rc = EMSGSIZE; + goto fail2; + } + npartn = MCDI_OUT_DWORD(req, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS); + + if (req.emr_out_length_used < MC_CMD_NVRAM_PARTITIONS_OUT_LEN(npartn)) { + rc = ENOENT; + goto fail3; + } + + if (size < npartn * sizeof (uint32_t)) { + rc = ENOSPC; + goto fail3; + } + + *npartnp = npartn; + + memcpy(data, + MCDI_OUT2(req, uint32_t, NVRAM_PARTITIONS_OUT_TYPE_ID), + (npartn * sizeof (uint32_t))); + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +efx_mcdi_nvram_metadata( + __in efx_nic_t *enp, + __in uint32_t partn, + __out uint32_t *subtypep, + __out_ecount(4) uint16_t version[4], + __out_bcount_opt(size) char *descp, + __in size_t size) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_NVRAM_METADATA_IN_LEN, + MC_CMD_NVRAM_METADATA_OUT_LENMAX)]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_NVRAM_METADATA; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_NVRAM_METADATA_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_NVRAM_METADATA_OUT_LENMAX; + + MCDI_IN_SET_DWORD(req, NVRAM_METADATA_IN_TYPE, partn); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < MC_CMD_NVRAM_METADATA_OUT_LENMIN) { + rc = EMSGSIZE; + goto fail2; + } + + if (MCDI_OUT_DWORD_FIELD(req, NVRAM_METADATA_OUT_FLAGS, + NVRAM_METADATA_OUT_SUBTYPE_VALID)) { + *subtypep = MCDI_OUT_DWORD(req, NVRAM_METADATA_OUT_SUBTYPE); + } else { + *subtypep = 0; + } + + if (MCDI_OUT_DWORD_FIELD(req, NVRAM_METADATA_OUT_FLAGS, + NVRAM_METADATA_OUT_VERSION_VALID)) { + version[0] = MCDI_OUT_WORD(req, NVRAM_METADATA_OUT_VERSION_W); + version[1] = MCDI_OUT_WORD(req, NVRAM_METADATA_OUT_VERSION_X); + version[2] = MCDI_OUT_WORD(req, NVRAM_METADATA_OUT_VERSION_Y); + version[3] = MCDI_OUT_WORD(req, NVRAM_METADATA_OUT_VERSION_Z); + } else { + version[0] = version[1] = version[2] = version[3] = 0; + } + + if (MCDI_OUT_DWORD_FIELD(req, NVRAM_METADATA_OUT_FLAGS, + NVRAM_METADATA_OUT_DESCRIPTION_VALID)) { + /* Return optional descrition string */ + if ((descp != NULL) && (size > 0)) { + size_t desclen; + + descp[0] = '\0'; + desclen = (req.emr_out_length_used + - MC_CMD_NVRAM_METADATA_OUT_LEN(0)); + + EFSYS_ASSERT3U(desclen, <=, + MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM); + + if (size < desclen) { + rc = ENOSPC; + goto fail3; + } + + memcpy(descp, MCDI_OUT2(req, char, + NVRAM_METADATA_OUT_DESCRIPTION), + desclen); + + /* Ensure string is NUL terminated */ + descp[desclen] = '\0'; + } + } + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +efx_mcdi_nvram_info( + __in efx_nic_t *enp, + __in uint32_t partn, + __out_opt size_t *sizep, + __out_opt uint32_t *addressp, + __out_opt uint32_t *erase_sizep) +{ + uint8_t payload[MAX(MC_CMD_NVRAM_INFO_IN_LEN, + MC_CMD_NVRAM_INFO_OUT_LEN)]; + efx_mcdi_req_t req; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_NVRAM_INFO; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_NVRAM_INFO_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_NVRAM_INFO_OUT_LEN; + + MCDI_IN_SET_DWORD(req, NVRAM_INFO_IN_TYPE, partn); + + efx_mcdi_execute_quiet(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < MC_CMD_NVRAM_INFO_OUT_LEN) { + rc = EMSGSIZE; + goto fail2; + } + + if (sizep) + *sizep = MCDI_OUT_DWORD(req, NVRAM_INFO_OUT_SIZE); + + if (addressp) + *addressp = MCDI_OUT_DWORD(req, NVRAM_INFO_OUT_PHYSADDR); + + if (erase_sizep) + *erase_sizep = MCDI_OUT_DWORD(req, NVRAM_INFO_OUT_ERASESIZE); + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +efx_mcdi_nvram_update_start( + __in efx_nic_t *enp, + __in uint32_t partn) +{ + uint8_t payload[MAX(MC_CMD_NVRAM_UPDATE_START_IN_LEN, + MC_CMD_NVRAM_UPDATE_START_OUT_LEN)]; + efx_mcdi_req_t req; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_NVRAM_UPDATE_START; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_NVRAM_UPDATE_START_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_NVRAM_UPDATE_START_OUT_LEN; + + MCDI_IN_SET_DWORD(req, NVRAM_UPDATE_START_IN_TYPE, partn); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +efx_mcdi_nvram_read( + __in efx_nic_t *enp, + __in uint32_t partn, + __in uint32_t offset, + __out_bcount(size) caddr_t data, + __in size_t size) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_NVRAM_READ_IN_LEN, + MC_CMD_NVRAM_READ_OUT_LENMAX)]; + int rc; + + if (size > MC_CMD_NVRAM_READ_OUT_LENMAX) { + rc = EINVAL; + goto fail1; + } + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_NVRAM_READ; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_NVRAM_READ_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_NVRAM_READ_OUT_LENMAX; + + MCDI_IN_SET_DWORD(req, NVRAM_READ_IN_TYPE, partn); + MCDI_IN_SET_DWORD(req, NVRAM_READ_IN_OFFSET, offset); + MCDI_IN_SET_DWORD(req, NVRAM_READ_IN_LENGTH, size); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < MC_CMD_NVRAM_READ_OUT_LEN(size)) { + rc = EMSGSIZE; + goto fail2; + } + + memcpy(data, + MCDI_OUT2(req, uint8_t, NVRAM_READ_OUT_READ_BUFFER), + size); + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +efx_mcdi_nvram_erase( + __in efx_nic_t *enp, + __in uint32_t partn, + __in uint32_t offset, + __in size_t size) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_NVRAM_ERASE_IN_LEN, + MC_CMD_NVRAM_ERASE_OUT_LEN)]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_NVRAM_ERASE; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_NVRAM_ERASE_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_NVRAM_ERASE_OUT_LEN; + + MCDI_IN_SET_DWORD(req, NVRAM_ERASE_IN_TYPE, partn); + MCDI_IN_SET_DWORD(req, NVRAM_ERASE_IN_OFFSET, offset); + MCDI_IN_SET_DWORD(req, NVRAM_ERASE_IN_LENGTH, size); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +efx_mcdi_nvram_write( + __in efx_nic_t *enp, + __in uint32_t partn, + __in uint32_t offset, + __out_bcount(size) caddr_t data, + __in size_t size) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_NVRAM_WRITE_IN_LENMAX, + MC_CMD_NVRAM_WRITE_OUT_LEN)]; + int rc; + + if (size > MC_CMD_NVRAM_WRITE_IN_LENMAX) { + rc = EINVAL; + goto fail1; + } + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_NVRAM_WRITE; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_NVRAM_WRITE_IN_LEN(size); + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_NVRAM_WRITE_OUT_LEN; + + MCDI_IN_SET_DWORD(req, NVRAM_WRITE_IN_TYPE, partn); + MCDI_IN_SET_DWORD(req, NVRAM_WRITE_IN_OFFSET, offset); + MCDI_IN_SET_DWORD(req, NVRAM_WRITE_IN_LENGTH, size); + + memcpy(MCDI_IN2(req, uint8_t, NVRAM_WRITE_IN_WRITE_BUFFER), + data, size); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail2; + } + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +efx_mcdi_nvram_update_finish( + __in efx_nic_t *enp, + __in uint32_t partn, + __in boolean_t reboot) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN, + MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN)]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_NVRAM_UPDATE_FINISH; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN; + + MCDI_IN_SET_DWORD(req, NVRAM_UPDATE_FINISH_IN_TYPE, partn); + MCDI_IN_SET_DWORD(req, NVRAM_UPDATE_FINISH_IN_REBOOT, reboot); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +#if EFSYS_OPT_DIAG + + __checkReturn int +efx_mcdi_nvram_test( + __in efx_nic_t *enp, + __in uint32_t partn) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_NVRAM_TEST_IN_LEN, + MC_CMD_NVRAM_TEST_OUT_LEN)]; + int result; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_NVRAM_TEST; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_NVRAM_TEST_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_NVRAM_TEST_OUT_LEN; + + MCDI_IN_SET_DWORD(req, NVRAM_TEST_IN_TYPE, partn); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < MC_CMD_NVRAM_TEST_OUT_LEN) { + rc = EMSGSIZE; + goto fail2; + } + + result = MCDI_OUT_DWORD(req, NVRAM_TEST_OUT_RESULT); + if (result == MC_CMD_NVRAM_TEST_FAIL) { + + EFSYS_PROBE1(nvram_test_failure, int, partn); + + rc = (EINVAL); + goto fail3; + } + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +#endif /* EFSYS_OPT_DIAG */ + + +#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ Property changes on: head/sys/dev/sfxge/common/efx_nvram.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_phy.c =================================================================== --- head/sys/dev/sfxge/common/efx_phy.c (revision 283513) +++ head/sys/dev/sfxge/common/efx_phy.c (revision 283514) @@ -1,768 +1,839 @@ /*- - * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2007-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include "efsys.h" #include "efx.h" #include "efx_types.h" #include "efx_regs.h" #include "efx_impl.h" #if EFSYS_OPT_FALCON #include "falcon_nvram.h" #endif #if EFSYS_OPT_MAC_FALCON_XMAC #include "falcon_xmac.h" #endif #if EFSYS_OPT_MAC_FALCON_GMAC #include "falcon_gmac.h" #endif #if EFSYS_OPT_PHY_NULL #include "nullphy.h" #endif #if EFSYS_OPT_PHY_QT2022C2 #include "qt2022c2.h" #endif #if EFSYS_OPT_PHY_SFX7101 #include "sfx7101.h" #endif #if EFSYS_OPT_PHY_TXC43128 #include "txc43128.h" #endif #if EFSYS_OPT_PHY_SFT9001 #include "sft9001.h" #endif #if EFSYS_OPT_PHY_QT2025C #include "qt2025c.h" #endif #if EFSYS_OPT_PHY_NULL -static efx_phy_ops_t __cs __efx_phy_null_ops = { +static efx_phy_ops_t __efx_phy_null_ops = { NULL, /* epo_power */ nullphy_reset, /* epo_reset */ nullphy_reconfigure, /* epo_reconfigure */ nullphy_verify, /* epo_verify */ NULL, /* epo_uplink_check */ nullphy_downlink_check, /* epo_downlink_check */ nullphy_oui_get, /* epo_oui_get */ #if EFSYS_OPT_PHY_STATS nullphy_stats_update, /* epo_stats_update */ #endif /* EFSYS_OPT_PHY_STATS */ #if EFSYS_OPT_PHY_PROPS #if EFSYS_OPT_NAMES nullphy_prop_name, /* epo_prop_name */ #endif nullphy_prop_get, /* epo_prop_get */ nullphy_prop_set, /* epo_prop_set */ #endif /* EFSYS_OPT_PHY_PROPS */ -#if EFSYS_OPT_PHY_BIST +#if EFSYS_OPT_BIST + NULL, /* epo_bist_enable_offline */ NULL, /* epo_bist_start */ NULL, /* epo_bist_poll */ NULL, /* epo_bist_stop */ -#endif /* EFSYS_OPT_PHY_BIST */ +#endif /* EFSYS_OPT_BIST */ }; #endif /* EFSYS_OPT_PHY_NULL */ #if EFSYS_OPT_PHY_QT2022C2 -static efx_phy_ops_t __cs __efx_phy_qt2022c2_ops = { +static efx_phy_ops_t __efx_phy_qt2022c2_ops = { NULL, /* epo_power */ qt2022c2_reset, /* epo_reset */ qt2022c2_reconfigure, /* epo_reconfigure */ qt2022c2_verify, /* epo_verify */ qt2022c2_uplink_check, /* epo_uplink_check */ qt2022c2_downlink_check, /* epo_downlink_check */ qt2022c2_oui_get, /* epo_oui_get */ #if EFSYS_OPT_PHY_STATS qt2022c2_stats_update, /* epo_stats_update */ #endif /* EFSYS_OPT_PHY_STATS */ #if EFSYS_OPT_PHY_PROPS #if EFSYS_OPT_NAMES qt2022c2_prop_name, /* epo_prop_name */ #endif qt2022c2_prop_get, /* epo_prop_get */ qt2022c2_prop_set, /* epo_prop_set */ #endif /* EFSYS_OPT_PHY_PROPS */ -#if EFSYS_OPT_PHY_BIST +#if EFSYS_OPT_BIST + NULL, /* epo_bist_enable_offline */ NULL, /* epo_bist_start */ NULL, /* epo_bist_poll */ NULL, /* epo_bist_stop */ -#endif /* EFSYS_OPT_PHY_BIST */ +#endif /* EFSYS_OPT_BIST */ }; #endif /* EFSYS_OPT_PHY_QT2022C2 */ #if EFSYS_OPT_PHY_SFX7101 -static efx_phy_ops_t __cs __efx_phy_sfx7101_ops = { +static efx_phy_ops_t __efx_phy_sfx7101_ops = { sfx7101_power, /* epo_power */ sfx7101_reset, /* epo_reset */ sfx7101_reconfigure, /* epo_reconfigure */ sfx7101_verify, /* epo_verify */ sfx7101_uplink_check, /* epo_uplink_check */ sfx7101_downlink_check, /* epo_downlink_check */ sfx7101_oui_get, /* epo_oui_get */ #if EFSYS_OPT_PHY_STATS sfx7101_stats_update, /* epo_stats_update */ #endif /* EFSYS_OPT_PHY_STATS */ #if EFSYS_OPT_PHY_PROPS #if EFSYS_OPT_NAMES sfx7101_prop_name, /* epo_prop_name */ #endif sfx7101_prop_get, /* epo_prop_get */ sfx7101_prop_set, /* epo_prop_set */ #endif /* EFSYS_OPT_PHY_PROPS */ -#if EFSYS_OPT_PHY_BIST +#if EFSYS_OPT_BIST + NULL, /* epo_bist_enable_offline */ NULL, /* epo_bist_start */ NULL, /* epo_bist_poll */ NULL, /* epo_bist_stop */ -#endif /* EFSYS_OPT_PHY_BIST */ +#endif /* EFSYS_OPT_BIST */ }; #endif /* EFSYS_OPT_PHY_SFX7101 */ #if EFSYS_OPT_PHY_TXC43128 -static efx_phy_ops_t __cs __efx_phy_txc43128_ops = { +static efx_phy_ops_t __efx_phy_txc43128_ops = { NULL, /* epo_power */ txc43128_reset, /* epo_reset */ txc43128_reconfigure, /* epo_reconfigure */ txc43128_verify, /* epo_verify */ txc43128_uplink_check, /* epo_uplink_check */ txc43128_downlink_check, /* epo_downlink_check */ txc43128_oui_get, /* epo_oui_get */ #if EFSYS_OPT_PHY_STATS txc43128_stats_update, /* epo_stats_update */ #endif /* EFSYS_OPT_PHY_STATS */ #if EFSYS_OPT_PHY_PROPS #if EFSYS_OPT_NAMES txc43128_prop_name, /* epo_prop_name */ #endif txc43128_prop_get, /* epo_prop_get */ txc43128_prop_set, /* epo_prop_set */ #endif /* EFSYS_OPT_PHY_PROPS */ -#if EFSYS_OPT_PHY_BIST +#if EFSYS_OPT_BIST + NULL, /* epo_bist_enable_offline */ NULL, /* epo_bist_start */ NULL, /* epo_bist_poll */ NULL, /* epo_bist_stop */ -#endif /* EFSYS_OPT_PHY_BIST */ +#endif /* EFSYS_OPT_BIST */ }; #endif /* EFSYS_OPT_PHY_TXC43128 */ #if EFSYS_OPT_PHY_SFT9001 -static efx_phy_ops_t __cs __efx_phy_sft9001_ops = { +static efx_phy_ops_t __efx_phy_sft9001_ops = { NULL, /* epo_power */ sft9001_reset, /* epo_reset */ sft9001_reconfigure, /* epo_reconfigure */ sft9001_verify, /* epo_verify */ sft9001_uplink_check, /* epo_uplink_check */ sft9001_downlink_check, /* epo_downlink_check */ sft9001_oui_get, /* epo_oui_get */ #if EFSYS_OPT_PHY_STATS sft9001_stats_update, /* epo_stats_update */ #endif /* EFSYS_OPT_PHY_STATS */ #if EFSYS_OPT_PHY_PROPS #if EFSYS_OPT_NAMES sft9001_prop_name, /* epo_prop_name */ #endif sft9001_prop_get, /* epo_prop_get */ sft9001_prop_set, /* epo_prop_set */ #endif /* EFSYS_OPT_PHY_PROPS */ -#if EFSYS_OPT_PHY_BIST +#if EFSYS_OPT_BIST + NULL, /* epo_bist_enable_offline */ sft9001_bist_start, /* epo_bist_start */ sft9001_bist_poll, /* epo_bist_poll */ sft9001_bist_stop, /* epo_bist_stop */ -#endif /* EFSYS_OPT_PHY_BIST */ +#endif /* EFSYS_OPT_BIST */ }; #endif /* EFSYS_OPT_PHY_SFT9001 */ #if EFSYS_OPT_PHY_QT2025C -static efx_phy_ops_t __cs __efx_phy_qt2025c_ops = { +static efx_phy_ops_t __efx_phy_qt2025c_ops = { NULL, /* epo_power */ qt2025c_reset, /* epo_reset */ qt2025c_reconfigure, /* epo_reconfigure */ qt2025c_verify, /* epo_verify */ qt2025c_uplink_check, /* epo_uplink_check */ qt2025c_downlink_check, /* epo_downlink_check */ qt2025c_oui_get, /* epo_oui_get */ #if EFSYS_OPT_PHY_STATS qt2025c_stats_update, /* epo_stats_update */ #endif /* EFSYS_OPT_PHY_STATS */ #if EFSYS_OPT_PHY_PROPS #if EFSYS_OPT_NAMES qt2025c_prop_name, /* epo_prop_name */ #endif qt2025c_prop_get, /* epo_prop_get */ qt2025c_prop_set, /* epo_prop_set */ #endif /* EFSYS_OPT_PHY_PROPS */ -#if EFSYS_OPT_PHY_BIST +#if EFSYS_OPT_BIST + NULL, /* epo_bist_enable_offline */ NULL, /* epo_bist_start */ NULL, /* epo_bist_poll */ NULL, /* epo_bist_stop */ -#endif /* EFSYS_OPT_PHY_BIST */ +#endif /* EFSYS_OPT_BIST */ }; #endif /* EFSYS_OPT_PHY_QT2025C */ #if EFSYS_OPT_SIENA -static efx_phy_ops_t __cs __efx_phy_siena_ops = { +static efx_phy_ops_t __efx_phy_siena_ops = { siena_phy_power, /* epo_power */ NULL, /* epo_reset */ siena_phy_reconfigure, /* epo_reconfigure */ siena_phy_verify, /* epo_verify */ NULL, /* epo_uplink_check */ NULL, /* epo_downlink_check */ siena_phy_oui_get, /* epo_oui_get */ #if EFSYS_OPT_PHY_STATS siena_phy_stats_update, /* epo_stats_update */ #endif /* EFSYS_OPT_PHY_STATS */ #if EFSYS_OPT_PHY_PROPS #if EFSYS_OPT_NAMES siena_phy_prop_name, /* epo_prop_name */ #endif siena_phy_prop_get, /* epo_prop_get */ siena_phy_prop_set, /* epo_prop_set */ #endif /* EFSYS_OPT_PHY_PROPS */ -#if EFSYS_OPT_PHY_BIST +#if EFSYS_OPT_BIST + NULL, /* epo_bist_enable_offline */ siena_phy_bist_start, /* epo_bist_start */ siena_phy_bist_poll, /* epo_bist_poll */ siena_phy_bist_stop, /* epo_bist_stop */ -#endif /* EFSYS_OPT_PHY_BIST */ +#endif /* EFSYS_OPT_BIST */ }; #endif /* EFSYS_OPT_SIENA */ +#if EFSYS_OPT_HUNTINGTON +static efx_phy_ops_t __efx_phy_hunt_ops = { + hunt_phy_power, /* epo_power */ + NULL, /* epo_reset */ + hunt_phy_reconfigure, /* epo_reconfigure */ + hunt_phy_verify, /* epo_verify */ + NULL, /* epo_uplink_check */ + NULL, /* epo_downlink_check */ + hunt_phy_oui_get, /* epo_oui_get */ +#if EFSYS_OPT_PHY_STATS + hunt_phy_stats_update, /* epo_stats_update */ +#endif /* EFSYS_OPT_PHY_STATS */ +#if EFSYS_OPT_PHY_PROPS +#if EFSYS_OPT_NAMES + hunt_phy_prop_name, /* epo_prop_name */ +#endif + hunt_phy_prop_get, /* epo_prop_get */ + hunt_phy_prop_set, /* epo_prop_set */ +#endif /* EFSYS_OPT_PHY_PROPS */ +#if EFSYS_OPT_BIST + hunt_bist_enable_offline, /* epo_bist_enable_offline */ + hunt_bist_start, /* epo_bist_start */ + hunt_bist_poll, /* epo_bist_poll */ + hunt_bist_stop, /* epo_bist_stop */ +#endif /* EFSYS_OPT_BIST */ +}; +#endif /* EFSYS_OPT_HUNTINGTON */ + __checkReturn int efx_phy_probe( __in efx_nic_t *enp) { efx_port_t *epp = &(enp->en_port); efx_nic_cfg_t *encp = &(enp->en_nic_cfg); efx_phy_ops_t *epop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); epp->ep_port = encp->enc_port; epp->ep_phy_type = encp->enc_phy_type; /* Hook in operations structure */ switch (enp->en_family) { #if EFSYS_OPT_FALCON case EFX_FAMILY_FALCON: switch (epp->ep_phy_type) { #if EFSYS_OPT_PHY_NULL case PHY_TYPE_NONE_DECODE: epop = (efx_phy_ops_t *)&__efx_phy_null_ops; break; #endif #if EFSYS_OPT_PHY_QT2022C2 case PHY_TYPE_QT2022C2_DECODE: epop = (efx_phy_ops_t *)&__efx_phy_qt2022c2_ops; break; #endif #if EFSYS_OPT_PHY_SFX7101 case PHY_TYPE_SFX7101_DECODE: epop = (efx_phy_ops_t *)&__efx_phy_sfx7101_ops; break; #endif #if EFSYS_OPT_PHY_TXC43128 case PHY_TYPE_TXC43128_DECODE: epop = (efx_phy_ops_t *)&__efx_phy_txc43128_ops; break; #endif #if EFSYS_OPT_PHY_SFT9001 case PHY_TYPE_SFT9001A_DECODE: case PHY_TYPE_SFT9001B_DECODE: epop = (efx_phy_ops_t *)&__efx_phy_sft9001_ops; break; #endif #if EFSYS_OPT_PHY_QT2025C case EFX_PHY_QT2025C: epop = (efx_phy_ops_t *)&__efx_phy_qt2025c_ops; break; #endif default: rc = ENOTSUP; goto fail1; } break; #endif /* EFSYS_OPT_FALCON */ #if EFSYS_OPT_SIENA case EFX_FAMILY_SIENA: epop = (efx_phy_ops_t *)&__efx_phy_siena_ops; break; #endif /* EFSYS_OPT_SIENA */ +#if EFSYS_OPT_HUNTINGTON + case EFX_FAMILY_HUNTINGTON: + epop = (efx_phy_ops_t *)&__efx_phy_hunt_ops; + break; +#endif /* EFSYS_OPT_HUNTINGTON */ default: rc = ENOTSUP; goto fail1; } epp->ep_epop = epop; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); epp->ep_port = 0; epp->ep_phy_type = 0; return (rc); } __checkReturn int efx_phy_verify( __in efx_nic_t *enp) { efx_port_t *epp = &(enp->en_port); efx_phy_ops_t *epop = epp->ep_epop; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); return (epop->epo_verify(enp)); } #if EFSYS_OPT_PHY_LED_CONTROL __checkReturn int efx_phy_led_set( __in efx_nic_t *enp, __in efx_phy_led_mode_t mode) { efx_nic_cfg_t *encp = (&enp->en_nic_cfg); efx_port_t *epp = &(enp->en_port); efx_phy_ops_t *epop = epp->ep_epop; uint32_t mask; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); if (epp->ep_phy_led_mode == mode) goto done; mask = (1 << EFX_PHY_LED_DEFAULT); mask |= encp->enc_led_mask; if (!((1 << mode) & mask)) { rc = ENOTSUP; goto fail1; } EFSYS_ASSERT3U(mode, <, EFX_PHY_LED_NMODES); epp->ep_phy_led_mode = mode; if ((rc = epop->epo_reconfigure(enp)) != 0) goto fail2; done: return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } #endif /* EFSYS_OPT_PHY_LED_CONTROL */ void efx_phy_adv_cap_get( __in efx_nic_t *enp, __in uint32_t flag, __out uint32_t *maskp) { efx_port_t *epp = &(enp->en_port); EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); switch (flag) { case EFX_PHY_CAP_CURRENT: *maskp = epp->ep_adv_cap_mask; break; case EFX_PHY_CAP_DEFAULT: *maskp = epp->ep_default_adv_cap_mask; break; case EFX_PHY_CAP_PERM: *maskp = epp->ep_phy_cap_mask; break; default: EFSYS_ASSERT(B_FALSE); break; } } __checkReturn int efx_phy_adv_cap_set( __in efx_nic_t *enp, __in uint32_t mask) { efx_port_t *epp = &(enp->en_port); efx_phy_ops_t *epop = epp->ep_epop; uint32_t old_mask; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); if ((mask & ~epp->ep_phy_cap_mask) != 0) { rc = ENOTSUP; goto fail1; } if (epp->ep_adv_cap_mask == mask) goto done; old_mask = epp->ep_adv_cap_mask; epp->ep_adv_cap_mask = mask; if ((rc = epop->epo_reconfigure(enp)) != 0) goto fail2; done: return (0); fail2: EFSYS_PROBE(fail2); epp->ep_adv_cap_mask = old_mask; /* Reconfigure for robustness */ if (epop->epo_reconfigure(enp) != 0) { /* * We may have an inconsistent view of our advertised speed * capabilities. */ EFSYS_ASSERT(0); } fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } void efx_phy_lp_cap_get( __in efx_nic_t *enp, __out uint32_t *maskp) { efx_port_t *epp = &(enp->en_port); EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); *maskp = epp->ep_lp_cap_mask; } __checkReturn int efx_phy_oui_get( __in efx_nic_t *enp, __out uint32_t *ouip) { efx_port_t *epp = &(enp->en_port); efx_phy_ops_t *epop = epp->ep_epop; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); return (epop->epo_oui_get(enp, ouip)); } void efx_phy_media_type_get( __in efx_nic_t *enp, __out efx_phy_media_type_t *typep) { efx_port_t *epp = &(enp->en_port); EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); if (epp->ep_module_type != EFX_PHY_MEDIA_INVALID) *typep = epp->ep_module_type; else *typep = epp->ep_fixed_port_type; } #if EFSYS_OPT_PHY_STATS #if EFSYS_OPT_NAMES -/* START MKCONFIG GENERATED PhyStatNamesBlock 271268f3da0e804f */ -static const char __cs * __cs __efx_phy_stat_name[] = { +/* START MKCONFIG GENERATED PhyStatNamesBlock d5f79b4bc2c050fe */ +static const char *__efx_phy_stat_name[] = { "oui", "pma_pmd_link_up", "pma_pmd_rx_fault", "pma_pmd_tx_fault", "pma_pmd_rev_a", "pma_pmd_rev_b", "pma_pmd_rev_c", "pma_pmd_rev_d", "pcs_link_up", "pcs_rx_fault", "pcs_tx_fault", "pcs_ber", "pcs_block_errors", "phy_xs_link_up", "phy_xs_rx_fault", "phy_xs_tx_fault", "phy_xs_align", "phy_xs_sync_a", "phy_xs_sync_b", "phy_xs_sync_c", "phy_xs_sync_d", "an_link_up", "an_master", "an_local_rx_ok", "an_remote_rx_ok", "cl22ext_link_up", "snr_a", "snr_b", "snr_c", "snr_d", "pma_pmd_signal_a", "pma_pmd_signal_b", "pma_pmd_signal_c", "pma_pmd_signal_d", "an_complete", "pma_pmd_rev_major", "pma_pmd_rev_minor", "pma_pmd_rev_micro", "pcs_fw_version_0", "pcs_fw_version_1", "pcs_fw_version_2", "pcs_fw_version_3", "pcs_fw_build_yy", "pcs_fw_build_mm", "pcs_fw_build_dd", "pcs_op_mode", }; /* END MKCONFIG GENERATED PhyStatNamesBlock */ - const char __cs * + const char * efx_phy_stat_name( __in efx_nic_t *enp, __in efx_phy_stat_t type) { _NOTE(ARGUNUSED(enp)) EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(type, <, EFX_PHY_NSTATS); return (__efx_phy_stat_name[type]); } #endif /* EFSYS_OPT_NAMES */ __checkReturn int efx_phy_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, __out_ecount(EFX_PHY_NSTATS) uint32_t *stat) { efx_port_t *epp = &(enp->en_port); efx_phy_ops_t *epop = epp->ep_epop; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); return (epop->epo_stats_update(enp, esmp, stat)); } #endif /* EFSYS_OPT_PHY_STATS */ #if EFSYS_OPT_PHY_PROPS #if EFSYS_OPT_NAMES - const char __cs * + const char * efx_phy_prop_name( __in efx_nic_t *enp, __in unsigned int id) { efx_port_t *epp = &(enp->en_port); efx_phy_ops_t *epop = epp->ep_epop; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); return (epop->epo_prop_name(enp, id)); } #endif /* EFSYS_OPT_NAMES */ __checkReturn int efx_phy_prop_get( __in efx_nic_t *enp, __in unsigned int id, __in uint32_t flags, __out uint32_t *valp) { efx_port_t *epp = &(enp->en_port); efx_phy_ops_t *epop = epp->ep_epop; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); return (epop->epo_prop_get(enp, id, flags, valp)); } __checkReturn int efx_phy_prop_set( __in efx_nic_t *enp, __in unsigned int id, __in uint32_t val) { efx_port_t *epp = &(enp->en_port); efx_phy_ops_t *epop = epp->ep_epop; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); return (epop->epo_prop_set(enp, id, val)); } #endif /* EFSYS_OPT_PHY_STATS */ -#if EFSYS_OPT_PHY_BIST +#if EFSYS_OPT_BIST __checkReturn int -efx_phy_bist_start( +efx_bist_enable_offline( + __in efx_nic_t *enp) +{ + efx_port_t *epp = &(enp->en_port); + efx_phy_ops_t *epop = epp->ep_epop; + int rc; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + + if (epop->epo_bist_enable_offline == NULL) { + rc = ENOTSUP; + goto fail1; + } + + if ((rc = epop->epo_bist_enable_offline(enp)) != 0) + goto fail2; + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); + +} + + __checkReturn int +efx_bist_start( __in efx_nic_t *enp, - __in efx_phy_bist_type_t type) + __in efx_bist_type_t type) { efx_port_t *epp = &(enp->en_port); efx_phy_ops_t *epop = epp->ep_epop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); - EFSYS_ASSERT3U(type, !=, EFX_PHY_BIST_TYPE_UNKNOWN); - EFSYS_ASSERT3U(type, <, EFX_PHY_BIST_TYPE_NTYPES); - EFSYS_ASSERT3U(epp->ep_current_bist, ==, EFX_PHY_BIST_TYPE_UNKNOWN); + EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN); + EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES); + EFSYS_ASSERT3U(epp->ep_current_bist, ==, EFX_BIST_TYPE_UNKNOWN); if (epop->epo_bist_start == NULL) { rc = ENOTSUP; goto fail1; } if ((rc = epop->epo_bist_start(enp, type)) != 0) goto fail2; epp->ep_current_bist = type; return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int -efx_phy_bist_poll( +efx_bist_poll( __in efx_nic_t *enp, - __in efx_phy_bist_type_t type, - __out efx_phy_bist_result_t *resultp, + __in efx_bist_type_t type, + __out efx_bist_result_t *resultp, __out_opt uint32_t *value_maskp, __out_ecount_opt(count) unsigned long *valuesp, __in size_t count) { efx_port_t *epp = &(enp->en_port); efx_phy_ops_t *epop = epp->ep_epop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); - EFSYS_ASSERT3U(type, !=, EFX_PHY_BIST_TYPE_UNKNOWN); - EFSYS_ASSERT3U(type, <, EFX_PHY_BIST_TYPE_NTYPES); + EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN); + EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES); EFSYS_ASSERT3U(epp->ep_current_bist, ==, type); EFSYS_ASSERT(epop->epo_bist_poll != NULL); if (epop->epo_bist_poll == NULL) { rc = ENOTSUP; goto fail1; } if ((rc = epop->epo_bist_poll(enp, type, resultp, value_maskp, valuesp, count)) != 0) goto fail2; return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } void -efx_phy_bist_stop( +efx_bist_stop( __in efx_nic_t *enp, - __in efx_phy_bist_type_t type) + __in efx_bist_type_t type) { efx_port_t *epp = &(enp->en_port); efx_phy_ops_t *epop = epp->ep_epop; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); - EFSYS_ASSERT3U(type, !=, EFX_PHY_BIST_TYPE_UNKNOWN); - EFSYS_ASSERT3U(type, <, EFX_PHY_BIST_TYPE_NTYPES); + EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN); + EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES); EFSYS_ASSERT3U(epp->ep_current_bist, ==, type); EFSYS_ASSERT(epop->epo_bist_stop != NULL); if (epop->epo_bist_stop != NULL) epop->epo_bist_stop(enp, type); - epp->ep_current_bist = EFX_PHY_BIST_TYPE_UNKNOWN; + epp->ep_current_bist = EFX_BIST_TYPE_UNKNOWN; } -#endif /* EFSYS_OPT_PHY_BIST */ +#endif /* EFSYS_OPT_BIST */ void efx_phy_unprobe( __in efx_nic_t *enp) { efx_port_t *epp = &(enp->en_port); EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); epp->ep_epop = NULL; epp->ep_adv_cap_mask = 0; epp->ep_port = 0; epp->ep_phy_type = 0; } Property changes on: head/sys/dev/sfxge/common/efx_phy.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_phy_ids.h =================================================================== --- head/sys/dev/sfxge/common/efx_phy_ids.h (nonexistent) +++ head/sys/dev/sfxge/common/efx_phy_ids.h (revision 283514) @@ -0,0 +1,53 @@ +/*- + * Copyright (c) 2013-2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + * + * $FreeBSD$ + */ + +#ifndef _SYS_EFX_PHY_IDS_H +#define _SYS_EFX_PHY_IDS_H + +#define EFX_PHY_NULL 0 + +typedef enum efx_phy_type_e { /* GENERATED BY scripts/genfwdef */ + EFX_PHY_TXC43128 = 1, + EFX_PHY_SFX7101 = 3, + EFX_PHY_QT2022C2 = 4, + EFX_PHY_PM8358 = 6, + EFX_PHY_SFT9001A = 8, + EFX_PHY_QT2025C = 9, + EFX_PHY_SFT9001B = 10, + EFX_PHY_QLX111V = 12, + EFX_PHY_QT2025_KR = 17, + EFX_PHY_AEL3020 = 18, + EFX_PHY_XFI_FARMI = 19, +} efx_phy_type_t; + + +#endif /* _SYS_EFX_PHY_IDS_H */ Property changes on: head/sys/dev/sfxge/common/efx_phy_ids.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_port.c =================================================================== --- head/sys/dev/sfxge/common/efx_port.c (revision 283513) +++ head/sys/dev/sfxge/common/efx_port.c (revision 283514) @@ -1,229 +1,259 @@ /*- - * Copyright 2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2009-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include "efsys.h" #include "efx.h" #include "efx_types.h" #include "efx_impl.h" __checkReturn int efx_port_init( __in efx_nic_t *enp) { efx_port_t *epp = &(enp->en_port); efx_phy_ops_t *epop = epp->ep_epop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); if (enp->en_mod_flags & EFX_MOD_PORT) { rc = EINVAL; goto fail1; } enp->en_mod_flags |= EFX_MOD_PORT; epp->ep_mac_type = EFX_MAC_INVALID; epp->ep_link_mode = EFX_LINK_UNKNOWN; epp->ep_mac_poll_needed = B_TRUE; epp->ep_mac_drain = B_TRUE; /* Configure the MAC */ if ((rc = efx_mac_select(enp)) != 0) goto fail1; epp->ep_emop->emo_reconfigure(enp); + /* Pick up current phy capababilities */ + efx_port_poll(enp, NULL); + /* * Turn on the PHY if available, otherwise reset it, and * reconfigure it with the current configuration. */ if (epop->epo_power != NULL) { if ((rc = epop->epo_power(enp, B_TRUE)) != 0) goto fail2; } else { if ((rc = epop->epo_reset(enp)) != 0) goto fail2; } EFSYS_ASSERT(enp->en_reset_flags & EFX_RESET_PHY); enp->en_reset_flags &= ~EFX_RESET_PHY; if ((rc = epop->epo_reconfigure(enp)) != 0) goto fail3; return (0); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); enp->en_mod_flags &= ~EFX_MOD_PORT; return (rc); } __checkReturn int efx_port_poll( __in efx_nic_t *enp, - __out efx_link_mode_t *link_modep) + __out_opt efx_link_mode_t *link_modep) { efx_port_t *epp = &(enp->en_port); efx_mac_ops_t *emop = epp->ep_emop; efx_link_mode_t ignore_link_mode; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); EFSYS_ASSERT(emop != NULL); EFSYS_ASSERT(!epp->ep_mac_stats_pending); if (link_modep == NULL) link_modep = &ignore_link_mode; if ((rc = emop->emo_poll(enp, link_modep)) != 0) goto fail1; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } #if EFSYS_OPT_LOOPBACK __checkReturn int efx_port_loopback_set( __in efx_nic_t *enp, __in efx_link_mode_t link_mode, __in efx_loopback_type_t loopback_type) { efx_port_t *epp = &(enp->en_port); efx_nic_cfg_t *encp = &(enp->en_nic_cfg); efx_mac_ops_t *emop = epp->ep_emop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); EFSYS_ASSERT(emop != NULL); EFSYS_ASSERT(link_mode < EFX_LINK_NMODES); - if ((1 << loopback_type) & ~encp->enc_loopback_types[link_mode]) { + + if (EFX_TEST_QWORD_BIT(encp->enc_loopback_types[link_mode], + loopback_type) == 0) { rc = ENOTSUP; goto fail1; } if (epp->ep_loopback_type == loopback_type && epp->ep_loopback_link_mode == link_mode) return (0); if ((rc = emop->emo_loopback_set(enp, link_mode, loopback_type)) != 0) goto fail2; return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } #if EFSYS_OPT_NAMES -static const char __cs * __cs __efx_loopback_type_name[] = { +static const char *__efx_loopback_type_name[] = { "OFF", "DATA", "GMAC", "XGMII", "XGXS", "XAUI", "GMII", "SGMII", "XGBR", "XFI", "XAUI_FAR", "GMII_FAR", "SGMII_FAR", "XFI_FAR", "GPHY", "PHY_XS", "PCS", "PMA_PMD", + "XPORT", + "XGMII_WS", + "XAUI_WS", + "XAUI_WS_FAR", + "XAUI_WS_NEAR", + "GMII_WS", + "XFI_WS", + "XFI_WS_FAR", + "PHYXS_WS", + "PMA_INT", + "SD_NEAR", + "SD_FAR", + "PMA_INT_WS", + "SD_FEP2_WS", + "SD_FEP1_5_WS", + "SD_FEP_WS", + "SD_FES_WS", }; - __checkReturn const char __cs * + __checkReturn const char * efx_loopback_type_name( __in efx_nic_t *enp, __in efx_loopback_type_t type) { + EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__efx_loopback_type_name) == + EFX_LOOPBACK_NTYPES); + _NOTE(ARGUNUSED(enp)) EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(type, <, EFX_LOOPBACK_NTYPES); return (__efx_loopback_type_name[type]); } #endif /* EFSYS_OPT_NAMES */ #endif /* EFSYS_OPT_LOOPBACK */ void efx_port_fini( __in efx_nic_t *enp) { efx_port_t *epp = &(enp->en_port); efx_phy_ops_t *epop = epp->ep_epop; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); EFSYS_ASSERT(epp->ep_mac_drain); epp->ep_emop = NULL; epp->ep_mac_type = EFX_MAC_INVALID; epp->ep_mac_drain = B_FALSE; epp->ep_mac_poll_needed = B_FALSE; /* Turn off the PHY */ if (epop->epo_power != NULL) (void) epop->epo_power(enp, B_FALSE); enp->en_mod_flags &= ~EFX_MOD_PORT; } Property changes on: head/sys/dev/sfxge/common/efx_port.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_regs.h =================================================================== --- head/sys/dev/sfxge/common/efx_regs.h (revision 283513) +++ head/sys/dev/sfxge/common/efx_regs.h (revision 283514) @@ -1,3867 +1,3872 @@ /*- - * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2007-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + * * $FreeBSD$ */ #ifndef _SYS_EFX_REGS_H #define _SYS_EFX_REGS_H #ifdef __cplusplus extern "C" { #endif /************************************************************************** * * Falcon/Siena registers and descriptors * ************************************************************************** */ /* * FR_AB_EE_VPD_CFG0_REG_SF(128bit): * SPI/VPD configuration register 0 */ #define FR_AB_EE_VPD_CFG0_REG_SF_OFST 0x00000300 /* falcona0,falconb0=eeprom_flash */ /* * FR_AB_EE_VPD_CFG0_REG(128bit): * SPI/VPD configuration register 0 */ #define FR_AB_EE_VPD_CFG0_REG_OFST 0x00000140 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_EE_SF_FASTRD_EN_LBN 127 #define FRF_AB_EE_SF_FASTRD_EN_WIDTH 1 #define FRF_AB_EE_SF_CLOCK_DIV_LBN 120 #define FRF_AB_EE_SF_CLOCK_DIV_WIDTH 7 #define FRF_AB_EE_VPD_WIP_POLL_LBN 119 #define FRF_AB_EE_VPD_WIP_POLL_WIDTH 1 #define FRF_AB_EE_EE_CLOCK_DIV_LBN 112 #define FRF_AB_EE_EE_CLOCK_DIV_WIDTH 7 #define FRF_AB_EE_EE_WR_TMR_VALUE_LBN 96 #define FRF_AB_EE_EE_WR_TMR_VALUE_WIDTH 16 #define FRF_AB_EE_VPDW_LENGTH_LBN 80 #define FRF_AB_EE_VPDW_LENGTH_WIDTH 15 #define FRF_AB_EE_VPDW_BASE_LBN 64 #define FRF_AB_EE_VPDW_BASE_WIDTH 15 #define FRF_AB_EE_VPD_WR_CMD_EN_LBN 56 #define FRF_AB_EE_VPD_WR_CMD_EN_WIDTH 8 #define FRF_AB_EE_VPD_BASE_LBN 32 #define FRF_AB_EE_VPD_BASE_WIDTH 24 #define FRF_AB_EE_VPD_LENGTH_LBN 16 #define FRF_AB_EE_VPD_LENGTH_WIDTH 15 #define FRF_AB_EE_VPD_AD_SIZE_LBN 8 #define FRF_AB_EE_VPD_AD_SIZE_WIDTH 5 #define FRF_AB_EE_VPD_ACCESS_ON_LBN 5 #define FRF_AB_EE_VPD_ACCESS_ON_WIDTH 1 #define FRF_AB_EE_VPD_ACCESS_BLOCK_LBN 4 #define FRF_AB_EE_VPD_ACCESS_BLOCK_WIDTH 1 #define FRF_AB_EE_VPD_DEV_SF_SEL_LBN 2 #define FRF_AB_EE_VPD_DEV_SF_SEL_WIDTH 1 #define FRF_AB_EE_VPD_EN_AD9_MODE_LBN 1 #define FRF_AB_EE_VPD_EN_AD9_MODE_WIDTH 1 #define FRF_AB_EE_VPD_EN_LBN 0 #define FRF_AB_EE_VPD_EN_WIDTH 1 /* * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit): * PCIE SerDes control register 0 to 3 */ #define FR_AB_PCIE_SD_CTL0123_REG_SF_OFST 0x00000320 /* falcona0,falconb0=eeprom_flash */ /* * FR_AB_PCIE_SD_CTL0123_REG(128bit): * PCIE SerDes control register 0 to 3 */ #define FR_AB_PCIE_SD_CTL0123_REG_OFST 0x00000320 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_PCIE_TESTSIG_H_LBN 96 #define FRF_AB_PCIE_TESTSIG_H_WIDTH 19 #define FRF_AB_PCIE_TESTSIG_L_LBN 64 #define FRF_AB_PCIE_TESTSIG_L_WIDTH 19 #define FRF_AB_PCIE_OFFSET_LBN 56 #define FRF_AB_PCIE_OFFSET_WIDTH 8 #define FRF_AB_PCIE_OFFSETEN_H_LBN 55 #define FRF_AB_PCIE_OFFSETEN_H_WIDTH 1 #define FRF_AB_PCIE_OFFSETEN_L_LBN 54 #define FRF_AB_PCIE_OFFSETEN_L_WIDTH 1 #define FRF_AB_PCIE_HIVMODE_H_LBN 53 #define FRF_AB_PCIE_HIVMODE_H_WIDTH 1 #define FRF_AB_PCIE_HIVMODE_L_LBN 52 #define FRF_AB_PCIE_HIVMODE_L_WIDTH 1 #define FRF_AB_PCIE_PARRESET_H_LBN 51 #define FRF_AB_PCIE_PARRESET_H_WIDTH 1 #define FRF_AB_PCIE_PARRESET_L_LBN 50 #define FRF_AB_PCIE_PARRESET_L_WIDTH 1 #define FRF_AB_PCIE_LPBKWDRV_H_LBN 49 #define FRF_AB_PCIE_LPBKWDRV_H_WIDTH 1 #define FRF_AB_PCIE_LPBKWDRV_L_LBN 48 #define FRF_AB_PCIE_LPBKWDRV_L_WIDTH 1 #define FRF_AB_PCIE_LPBK_LBN 40 #define FRF_AB_PCIE_LPBK_WIDTH 8 #define FRF_AB_PCIE_PARLPBK_LBN 32 #define FRF_AB_PCIE_PARLPBK_WIDTH 8 #define FRF_AB_PCIE_RXTERMADJ_H_LBN 30 #define FRF_AB_PCIE_RXTERMADJ_H_WIDTH 2 #define FRF_AB_PCIE_RXTERMADJ_L_LBN 28 #define FRF_AB_PCIE_RXTERMADJ_L_WIDTH 2 #define FFE_AB_PCIE_RXTERMADJ_MIN15PCNT 3 #define FFE_AB_PCIE_RXTERMADJ_PL10PCNT 2 #define FFE_AB_PCIE_RXTERMADJ_MIN17PCNT 1 #define FFE_AB_PCIE_RXTERMADJ_NOMNL 0 #define FRF_AB_PCIE_TXTERMADJ_H_LBN 26 #define FRF_AB_PCIE_TXTERMADJ_H_WIDTH 2 #define FRF_AB_PCIE_TXTERMADJ_L_LBN 24 #define FRF_AB_PCIE_TXTERMADJ_L_WIDTH 2 #define FFE_AB_PCIE_TXTERMADJ_MIN15PCNT 3 #define FFE_AB_PCIE_TXTERMADJ_PL10PCNT 2 #define FFE_AB_PCIE_TXTERMADJ_MIN17PCNT 1 #define FFE_AB_PCIE_TXTERMADJ_NOMNL 0 #define FRF_AB_PCIE_RXEQCTL_H_LBN 18 #define FRF_AB_PCIE_RXEQCTL_H_WIDTH 2 #define FRF_AB_PCIE_RXEQCTL_L_LBN 16 #define FRF_AB_PCIE_RXEQCTL_L_WIDTH 2 #define FFE_AB_PCIE_RXEQCTL_OFF_ALT 3 #define FFE_AB_PCIE_RXEQCTL_OFF 2 #define FFE_AB_PCIE_RXEQCTL_MIN 1 #define FFE_AB_PCIE_RXEQCTL_MAX 0 #define FRF_AB_PCIE_HIDRV_LBN 8 #define FRF_AB_PCIE_HIDRV_WIDTH 8 #define FRF_AB_PCIE_LODRV_LBN 0 #define FRF_AB_PCIE_LODRV_WIDTH 8 /* * FR_AB_PCIE_SD_CTL45_REG_SF(128bit): * PCIE SerDes control register 4 and 5 */ #define FR_AB_PCIE_SD_CTL45_REG_SF_OFST 0x00000330 /* falcona0,falconb0=eeprom_flash */ /* * FR_AB_PCIE_SD_CTL45_REG(128bit): * PCIE SerDes control register 4 and 5 */ #define FR_AB_PCIE_SD_CTL45_REG_OFST 0x00000330 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_PCIE_DTX7_LBN 60 #define FRF_AB_PCIE_DTX7_WIDTH 4 #define FRF_AB_PCIE_DTX6_LBN 56 #define FRF_AB_PCIE_DTX6_WIDTH 4 #define FRF_AB_PCIE_DTX5_LBN 52 #define FRF_AB_PCIE_DTX5_WIDTH 4 #define FRF_AB_PCIE_DTX4_LBN 48 #define FRF_AB_PCIE_DTX4_WIDTH 4 #define FRF_AB_PCIE_DTX3_LBN 44 #define FRF_AB_PCIE_DTX3_WIDTH 4 #define FRF_AB_PCIE_DTX2_LBN 40 #define FRF_AB_PCIE_DTX2_WIDTH 4 #define FRF_AB_PCIE_DTX1_LBN 36 #define FRF_AB_PCIE_DTX1_WIDTH 4 #define FRF_AB_PCIE_DTX0_LBN 32 #define FRF_AB_PCIE_DTX0_WIDTH 4 #define FRF_AB_PCIE_DEQ7_LBN 28 #define FRF_AB_PCIE_DEQ7_WIDTH 4 #define FRF_AB_PCIE_DEQ6_LBN 24 #define FRF_AB_PCIE_DEQ6_WIDTH 4 #define FRF_AB_PCIE_DEQ5_LBN 20 #define FRF_AB_PCIE_DEQ5_WIDTH 4 #define FRF_AB_PCIE_DEQ4_LBN 16 #define FRF_AB_PCIE_DEQ4_WIDTH 4 #define FRF_AB_PCIE_DEQ3_LBN 12 #define FRF_AB_PCIE_DEQ3_WIDTH 4 #define FRF_AB_PCIE_DEQ2_LBN 8 #define FRF_AB_PCIE_DEQ2_WIDTH 4 #define FRF_AB_PCIE_DEQ1_LBN 4 #define FRF_AB_PCIE_DEQ1_WIDTH 4 #define FRF_AB_PCIE_DEQ0_LBN 0 #define FRF_AB_PCIE_DEQ0_WIDTH 4 /* * FR_AB_PCIE_PCS_CTL_STAT_REG_SF(128bit): * PCIE PCS control and status register */ #define FR_AB_PCIE_PCS_CTL_STAT_REG_SF_OFST 0x00000340 /* falcona0,falconb0=eeprom_flash */ /* * FR_AB_PCIE_PCS_CTL_STAT_REG(128bit): * PCIE PCS control and status register */ #define FR_AB_PCIE_PCS_CTL_STAT_REG_OFST 0x00000340 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_PCIE_PRBSERRCOUNT0_H_LBN 52 #define FRF_AB_PCIE_PRBSERRCOUNT0_H_WIDTH 4 #define FRF_AB_PCIE_PRBSERRCOUNT0_L_LBN 48 #define FRF_AB_PCIE_PRBSERRCOUNT0_L_WIDTH 4 #define FRF_AB_PCIE_PRBSERR_LBN 40 #define FRF_AB_PCIE_PRBSERR_WIDTH 8 #define FRF_AB_PCIE_PRBSERRH0_LBN 32 #define FRF_AB_PCIE_PRBSERRH0_WIDTH 8 #define FRF_AB_PCIE_FASTINIT_H_LBN 15 #define FRF_AB_PCIE_FASTINIT_H_WIDTH 1 #define FRF_AB_PCIE_FASTINIT_L_LBN 14 #define FRF_AB_PCIE_FASTINIT_L_WIDTH 1 #define FRF_AB_PCIE_CTCDISABLE_H_LBN 13 #define FRF_AB_PCIE_CTCDISABLE_H_WIDTH 1 #define FRF_AB_PCIE_CTCDISABLE_L_LBN 12 #define FRF_AB_PCIE_CTCDISABLE_L_WIDTH 1 #define FRF_AB_PCIE_PRBSSYNC_H_LBN 11 #define FRF_AB_PCIE_PRBSSYNC_H_WIDTH 1 #define FRF_AB_PCIE_PRBSSYNC_L_LBN 10 #define FRF_AB_PCIE_PRBSSYNC_L_WIDTH 1 #define FRF_AB_PCIE_PRBSERRACK_H_LBN 9 #define FRF_AB_PCIE_PRBSERRACK_H_WIDTH 1 #define FRF_AB_PCIE_PRBSERRACK_L_LBN 8 #define FRF_AB_PCIE_PRBSERRACK_L_WIDTH 1 #define FRF_AB_PCIE_PRBSSEL_LBN 0 #define FRF_AB_PCIE_PRBSSEL_WIDTH 8 /* * FR_AB_HW_INIT_REG_SF(128bit): * Hardware initialization register */ #define FR_AB_HW_INIT_REG_SF_OFST 0x00000350 /* falcona0,falconb0=eeprom_flash */ /* * FR_AZ_HW_INIT_REG(128bit): * Hardware initialization register */ #define FR_AZ_HW_INIT_REG_OFST 0x000000c0 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_BB_BDMRD_CPLF_FULL_LBN 124 #define FRF_BB_BDMRD_CPLF_FULL_WIDTH 1 #define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_LBN 121 #define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_WIDTH 3 #define FRF_CZ_TX_MRG_TAGS_LBN 120 #define FRF_CZ_TX_MRG_TAGS_WIDTH 1 #define FRF_AZ_TRGT_MASK_ALL_LBN 100 #define FRF_AZ_TRGT_MASK_ALL_WIDTH 1 #define FRF_AZ_DOORBELL_DROP_LBN 92 #define FRF_AZ_DOORBELL_DROP_WIDTH 8 #define FRF_AB_TX_RREQ_MASK_EN_LBN 76 #define FRF_AB_TX_RREQ_MASK_EN_WIDTH 1 #define FRF_AB_PE_EIDLE_DIS_LBN 75 #define FRF_AB_PE_EIDLE_DIS_WIDTH 1 #define FRF_AZ_FC_BLOCKING_EN_LBN 45 #define FRF_AZ_FC_BLOCKING_EN_WIDTH 1 #define FRF_AZ_B2B_REQ_EN_LBN 44 #define FRF_AZ_B2B_REQ_EN_WIDTH 1 #define FRF_AZ_POST_WR_MASK_LBN 40 #define FRF_AZ_POST_WR_MASK_WIDTH 4 #define FRF_AZ_TLP_TC_LBN 34 #define FRF_AZ_TLP_TC_WIDTH 3 #define FRF_AZ_TLP_ATTR_LBN 32 #define FRF_AZ_TLP_ATTR_WIDTH 2 #define FRF_AB_INTB_VEC_LBN 24 #define FRF_AB_INTB_VEC_WIDTH 5 #define FRF_AB_INTA_VEC_LBN 16 #define FRF_AB_INTA_VEC_WIDTH 5 #define FRF_AZ_WD_TIMER_LBN 8 #define FRF_AZ_WD_TIMER_WIDTH 8 #define FRF_AZ_US_DISABLE_LBN 5 #define FRF_AZ_US_DISABLE_WIDTH 1 #define FRF_AZ_TLP_EP_LBN 4 #define FRF_AZ_TLP_EP_WIDTH 1 #define FRF_AZ_ATTR_SEL_LBN 3 #define FRF_AZ_ATTR_SEL_WIDTH 1 #define FRF_AZ_TD_SEL_LBN 1 #define FRF_AZ_TD_SEL_WIDTH 1 #define FRF_AZ_TLP_TD_LBN 0 #define FRF_AZ_TLP_TD_WIDTH 1 /* * FR_AB_NIC_STAT_REG_SF(128bit): * NIC status register */ #define FR_AB_NIC_STAT_REG_SF_OFST 0x00000360 /* falcona0,falconb0=eeprom_flash */ /* * FR_AB_NIC_STAT_REG(128bit): * NIC status register */ #define FR_AB_NIC_STAT_REG_OFST 0x00000200 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_BB_AER_DIS_LBN 34 #define FRF_BB_AER_DIS_WIDTH 1 #define FRF_BB_EE_STRAP_EN_LBN 31 #define FRF_BB_EE_STRAP_EN_WIDTH 1 #define FRF_BB_EE_STRAP_LBN 24 #define FRF_BB_EE_STRAP_WIDTH 4 #define FRF_BB_REVISION_ID_LBN 17 #define FRF_BB_REVISION_ID_WIDTH 7 #define FRF_AB_ONCHIP_SRAM_LBN 16 #define FRF_AB_ONCHIP_SRAM_WIDTH 1 #define FRF_AB_SF_PRST_LBN 9 #define FRF_AB_SF_PRST_WIDTH 1 #define FRF_AB_EE_PRST_LBN 8 #define FRF_AB_EE_PRST_WIDTH 1 #define FRF_AB_ATE_MODE_LBN 3 #define FRF_AB_ATE_MODE_WIDTH 1 #define FRF_AB_STRAP_PINS_LBN 0 #define FRF_AB_STRAP_PINS_WIDTH 3 /* * FR_AB_GLB_CTL_REG_SF(128bit): * Global control register */ #define FR_AB_GLB_CTL_REG_SF_OFST 0x00000370 /* falcona0,falconb0=eeprom_flash */ /* * FR_AB_GLB_CTL_REG(128bit): * Global control register */ #define FR_AB_GLB_CTL_REG_OFST 0x00000220 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_EXT_PHY_RST_CTL_LBN 63 #define FRF_AB_EXT_PHY_RST_CTL_WIDTH 1 #define FRF_AB_XAUI_SD_RST_CTL_LBN 62 #define FRF_AB_XAUI_SD_RST_CTL_WIDTH 1 #define FRF_AB_PCIE_SD_RST_CTL_LBN 61 #define FRF_AB_PCIE_SD_RST_CTL_WIDTH 1 #define FRF_AA_PCIX_RST_CTL_LBN 60 #define FRF_AA_PCIX_RST_CTL_WIDTH 1 #define FRF_BB_BIU_RST_CTL_LBN 60 #define FRF_BB_BIU_RST_CTL_WIDTH 1 #define FRF_AB_PCIE_STKY_RST_CTL_LBN 59 #define FRF_AB_PCIE_STKY_RST_CTL_WIDTH 1 #define FRF_AB_PCIE_NSTKY_RST_CTL_LBN 58 #define FRF_AB_PCIE_NSTKY_RST_CTL_WIDTH 1 #define FRF_AB_PCIE_CORE_RST_CTL_LBN 57 #define FRF_AB_PCIE_CORE_RST_CTL_WIDTH 1 #define FRF_AB_XGRX_RST_CTL_LBN 56 #define FRF_AB_XGRX_RST_CTL_WIDTH 1 #define FRF_AB_XGTX_RST_CTL_LBN 55 #define FRF_AB_XGTX_RST_CTL_WIDTH 1 #define FRF_AB_EM_RST_CTL_LBN 54 #define FRF_AB_EM_RST_CTL_WIDTH 1 #define FRF_AB_EV_RST_CTL_LBN 53 #define FRF_AB_EV_RST_CTL_WIDTH 1 #define FRF_AB_SR_RST_CTL_LBN 52 #define FRF_AB_SR_RST_CTL_WIDTH 1 #define FRF_AB_RX_RST_CTL_LBN 51 #define FRF_AB_RX_RST_CTL_WIDTH 1 #define FRF_AB_TX_RST_CTL_LBN 50 #define FRF_AB_TX_RST_CTL_WIDTH 1 #define FRF_AB_EE_RST_CTL_LBN 49 #define FRF_AB_EE_RST_CTL_WIDTH 1 #define FRF_AB_CS_RST_CTL_LBN 48 #define FRF_AB_CS_RST_CTL_WIDTH 1 #define FRF_AB_HOT_RST_CTL_LBN 40 #define FRF_AB_HOT_RST_CTL_WIDTH 2 #define FRF_AB_RST_EXT_PHY_LBN 31 #define FRF_AB_RST_EXT_PHY_WIDTH 1 #define FRF_AB_RST_XAUI_SD_LBN 30 #define FRF_AB_RST_XAUI_SD_WIDTH 1 #define FRF_AB_RST_PCIE_SD_LBN 29 #define FRF_AB_RST_PCIE_SD_WIDTH 1 #define FRF_AA_RST_PCIX_LBN 28 #define FRF_AA_RST_PCIX_WIDTH 1 #define FRF_BB_RST_BIU_LBN 28 #define FRF_BB_RST_BIU_WIDTH 1 #define FRF_AB_RST_PCIE_STKY_LBN 27 #define FRF_AB_RST_PCIE_STKY_WIDTH 1 #define FRF_AB_RST_PCIE_NSTKY_LBN 26 #define FRF_AB_RST_PCIE_NSTKY_WIDTH 1 #define FRF_AB_RST_PCIE_CORE_LBN 25 #define FRF_AB_RST_PCIE_CORE_WIDTH 1 #define FRF_AB_RST_XGRX_LBN 24 #define FRF_AB_RST_XGRX_WIDTH 1 #define FRF_AB_RST_XGTX_LBN 23 #define FRF_AB_RST_XGTX_WIDTH 1 #define FRF_AB_RST_EM_LBN 22 #define FRF_AB_RST_EM_WIDTH 1 #define FRF_AB_RST_EV_LBN 21 #define FRF_AB_RST_EV_WIDTH 1 #define FRF_AB_RST_SR_LBN 20 #define FRF_AB_RST_SR_WIDTH 1 #define FRF_AB_RST_RX_LBN 19 #define FRF_AB_RST_RX_WIDTH 1 #define FRF_AB_RST_TX_LBN 18 #define FRF_AB_RST_TX_WIDTH 1 #define FRF_AB_RST_SF_LBN 17 #define FRF_AB_RST_SF_WIDTH 1 #define FRF_AB_RST_CS_LBN 16 #define FRF_AB_RST_CS_WIDTH 1 #define FRF_AB_INT_RST_DUR_LBN 4 #define FRF_AB_INT_RST_DUR_WIDTH 3 #define FRF_AB_EXT_PHY_RST_DUR_LBN 1 #define FRF_AB_EXT_PHY_RST_DUR_WIDTH 3 #define FFE_AB_EXT_PHY_RST_DUR_10240US 7 #define FFE_AB_EXT_PHY_RST_DUR_5120US 6 #define FFE_AB_EXT_PHY_RST_DUR_2560US 5 #define FFE_AB_EXT_PHY_RST_DUR_1280US 4 #define FFE_AB_EXT_PHY_RST_DUR_640US 3 #define FFE_AB_EXT_PHY_RST_DUR_320US 2 #define FFE_AB_EXT_PHY_RST_DUR_160US 1 #define FFE_AB_EXT_PHY_RST_DUR_80US 0 #define FRF_AB_SWRST_LBN 0 #define FRF_AB_SWRST_WIDTH 1 /* * FR_AZ_IOM_IND_ADR_REG(32bit): * IO-mapped indirect access address register */ #define FR_AZ_IOM_IND_ADR_REG_OFST 0x00000000 /* falcona0,falconb0,sienaa0=net_func_bar0 */ #define FRF_AZ_IOM_AUTO_ADR_INC_EN_LBN 24 #define FRF_AZ_IOM_AUTO_ADR_INC_EN_WIDTH 1 #define FRF_AZ_IOM_IND_ADR_LBN 0 #define FRF_AZ_IOM_IND_ADR_WIDTH 24 /* * FR_AZ_IOM_IND_DAT_REG(32bit): * IO-mapped indirect access data register */ #define FR_AZ_IOM_IND_DAT_REG_OFST 0x00000004 /* falcona0,falconb0,sienaa0=net_func_bar0 */ #define FRF_AZ_IOM_IND_DAT_LBN 0 #define FRF_AZ_IOM_IND_DAT_WIDTH 32 /* * FR_AZ_ADR_REGION_REG(128bit): * Address region register */ #define FR_AZ_ADR_REGION_REG_OFST 0x00000000 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_ADR_REGION3_LBN 96 #define FRF_AZ_ADR_REGION3_WIDTH 18 #define FRF_AZ_ADR_REGION2_LBN 64 #define FRF_AZ_ADR_REGION2_WIDTH 18 #define FRF_AZ_ADR_REGION1_LBN 32 #define FRF_AZ_ADR_REGION1_WIDTH 18 #define FRF_AZ_ADR_REGION0_LBN 0 #define FRF_AZ_ADR_REGION0_WIDTH 18 /* * FR_AZ_INT_EN_REG_KER(128bit): * Kernel driver Interrupt enable register */ #define FR_AZ_INT_EN_REG_KER_OFST 0x00000010 /* falcona0,falconb0,sienaa0=net_func_bar2 */ #define FRF_AZ_KER_INT_LEVE_SEL_LBN 8 #define FRF_AZ_KER_INT_LEVE_SEL_WIDTH 6 #define FRF_AZ_KER_INT_CHAR_LBN 4 #define FRF_AZ_KER_INT_CHAR_WIDTH 1 #define FRF_AZ_KER_INT_KER_LBN 3 #define FRF_AZ_KER_INT_KER_WIDTH 1 #define FRF_AZ_DRV_INT_EN_KER_LBN 0 #define FRF_AZ_DRV_INT_EN_KER_WIDTH 1 /* * FR_AZ_INT_EN_REG_CHAR(128bit): * Char Driver interrupt enable register */ #define FR_AZ_INT_EN_REG_CHAR_OFST 0x00000020 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_CHAR_INT_LEVE_SEL_LBN 8 #define FRF_AZ_CHAR_INT_LEVE_SEL_WIDTH 6 #define FRF_AZ_CHAR_INT_CHAR_LBN 4 #define FRF_AZ_CHAR_INT_CHAR_WIDTH 1 #define FRF_AZ_CHAR_INT_KER_LBN 3 #define FRF_AZ_CHAR_INT_KER_WIDTH 1 #define FRF_AZ_DRV_INT_EN_CHAR_LBN 0 #define FRF_AZ_DRV_INT_EN_CHAR_WIDTH 1 /* * FR_AZ_INT_ADR_REG_KER(128bit): * Interrupt host address for Kernel driver */ #define FR_AZ_INT_ADR_REG_KER_OFST 0x00000030 /* falcona0,falconb0,sienaa0=net_func_bar2 */ #define FRF_AZ_NORM_INT_VEC_DIS_KER_LBN 64 #define FRF_AZ_NORM_INT_VEC_DIS_KER_WIDTH 1 #define FRF_AZ_INT_ADR_KER_LBN 0 #define FRF_AZ_INT_ADR_KER_WIDTH 64 #define FRF_AZ_INT_ADR_KER_DW0_LBN 0 #define FRF_AZ_INT_ADR_KER_DW0_WIDTH 32 #define FRF_AZ_INT_ADR_KER_DW1_LBN 32 #define FRF_AZ_INT_ADR_KER_DW1_WIDTH 32 /* * FR_AZ_INT_ADR_REG_CHAR(128bit): * Interrupt host address for Char driver */ #define FR_AZ_INT_ADR_REG_CHAR_OFST 0x00000040 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_NORM_INT_VEC_DIS_CHAR_LBN 64 #define FRF_AZ_NORM_INT_VEC_DIS_CHAR_WIDTH 1 #define FRF_AZ_INT_ADR_CHAR_LBN 0 #define FRF_AZ_INT_ADR_CHAR_WIDTH 64 #define FRF_AZ_INT_ADR_CHAR_DW0_LBN 0 #define FRF_AZ_INT_ADR_CHAR_DW0_WIDTH 32 #define FRF_AZ_INT_ADR_CHAR_DW1_LBN 32 #define FRF_AZ_INT_ADR_CHAR_DW1_WIDTH 32 /* * FR_AA_INT_ACK_KER(32bit): * Kernel interrupt acknowledge register */ #define FR_AA_INT_ACK_KER_OFST 0x00000050 /* falcona0=net_func_bar2 */ #define FRF_AA_INT_ACK_KER_FIELD_LBN 0 #define FRF_AA_INT_ACK_KER_FIELD_WIDTH 32 /* * FR_BZ_INT_ISR0_REG(128bit): * Function 0 Interrupt Acknowlege Status register */ #define FR_BZ_INT_ISR0_REG_OFST 0x00000090 /* falconb0,sienaa0=net_func_bar2 */ #define FRF_BZ_INT_ISR_REG_LBN 0 #define FRF_BZ_INT_ISR_REG_WIDTH 64 #define FRF_BZ_INT_ISR_REG_DW0_LBN 0 #define FRF_BZ_INT_ISR_REG_DW0_WIDTH 32 #define FRF_BZ_INT_ISR_REG_DW1_LBN 32 #define FRF_BZ_INT_ISR_REG_DW1_WIDTH 32 /* * FR_AB_EE_SPI_HCMD_REG(128bit): * SPI host command register */ #define FR_AB_EE_SPI_HCMD_REG_OFST 0x00000100 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_EE_SPI_HCMD_CMD_EN_LBN 31 #define FRF_AB_EE_SPI_HCMD_CMD_EN_WIDTH 1 #define FRF_AB_EE_WR_TIMER_ACTIVE_LBN 28 #define FRF_AB_EE_WR_TIMER_ACTIVE_WIDTH 1 #define FRF_AB_EE_SPI_HCMD_SF_SEL_LBN 24 #define FRF_AB_EE_SPI_HCMD_SF_SEL_WIDTH 1 #define FRF_AB_EE_SPI_HCMD_DABCNT_LBN 16 #define FRF_AB_EE_SPI_HCMD_DABCNT_WIDTH 5 #define FRF_AB_EE_SPI_HCMD_READ_LBN 15 #define FRF_AB_EE_SPI_HCMD_READ_WIDTH 1 #define FRF_AB_EE_SPI_HCMD_DUBCNT_LBN 12 #define FRF_AB_EE_SPI_HCMD_DUBCNT_WIDTH 2 #define FRF_AB_EE_SPI_HCMD_ADBCNT_LBN 8 #define FRF_AB_EE_SPI_HCMD_ADBCNT_WIDTH 2 #define FRF_AB_EE_SPI_HCMD_ENC_LBN 0 #define FRF_AB_EE_SPI_HCMD_ENC_WIDTH 8 /* * FR_CZ_USR_EV_CFG(32bit): * User Level Event Configuration register */ #define FR_CZ_USR_EV_CFG_OFST 0x00000100 /* sienaa0=net_func_bar2 */ #define FRF_CZ_USREV_DIS_LBN 16 #define FRF_CZ_USREV_DIS_WIDTH 1 #define FRF_CZ_DFLT_EVQ_LBN 0 #define FRF_CZ_DFLT_EVQ_WIDTH 10 /* * FR_AB_EE_SPI_HADR_REG(128bit): * SPI host address register */ #define FR_AB_EE_SPI_HADR_REG_OFST 0x00000110 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_EE_SPI_HADR_DUBYTE_LBN 24 #define FRF_AB_EE_SPI_HADR_DUBYTE_WIDTH 8 #define FRF_AB_EE_SPI_HADR_ADR_LBN 0 #define FRF_AB_EE_SPI_HADR_ADR_WIDTH 24 /* * FR_AB_EE_SPI_HDATA_REG(128bit): * SPI host data register */ #define FR_AB_EE_SPI_HDATA_REG_OFST 0x00000120 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_EE_SPI_HDATA3_LBN 96 #define FRF_AB_EE_SPI_HDATA3_WIDTH 32 #define FRF_AB_EE_SPI_HDATA2_LBN 64 #define FRF_AB_EE_SPI_HDATA2_WIDTH 32 #define FRF_AB_EE_SPI_HDATA1_LBN 32 #define FRF_AB_EE_SPI_HDATA1_WIDTH 32 #define FRF_AB_EE_SPI_HDATA0_LBN 0 #define FRF_AB_EE_SPI_HDATA0_WIDTH 32 /* * FR_AB_EE_BASE_PAGE_REG(128bit): * Expansion ROM base mirror register */ #define FR_AB_EE_BASE_PAGE_REG_OFST 0x00000130 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_EE_EXPROM_MASK_LBN 16 #define FRF_AB_EE_EXPROM_MASK_WIDTH 13 #define FRF_AB_EE_EXP_ROM_WINDOW_BASE_LBN 0 #define FRF_AB_EE_EXP_ROM_WINDOW_BASE_WIDTH 13 /* * FR_AB_EE_VPD_SW_CNTL_REG(128bit): * VPD access SW control register */ #define FR_AB_EE_VPD_SW_CNTL_REG_OFST 0x00000150 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_EE_VPD_CYCLE_PENDING_LBN 31 #define FRF_AB_EE_VPD_CYCLE_PENDING_WIDTH 1 #define FRF_AB_EE_VPD_CYC_WRITE_LBN 28 #define FRF_AB_EE_VPD_CYC_WRITE_WIDTH 1 #define FRF_AB_EE_VPD_CYC_ADR_LBN 0 #define FRF_AB_EE_VPD_CYC_ADR_WIDTH 15 /* * FR_AB_EE_VPD_SW_DATA_REG(128bit): * VPD access SW data register */ #define FR_AB_EE_VPD_SW_DATA_REG_OFST 0x00000160 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_EE_VPD_CYC_DAT_LBN 0 #define FRF_AB_EE_VPD_CYC_DAT_WIDTH 32 /* * FR_BB_PCIE_CORE_INDIRECT_REG(64bit): * Indirect Access to PCIE Core registers */ #define FR_BB_PCIE_CORE_INDIRECT_REG_OFST 0x000001f0 /* falconb0=net_func_bar2 */ #define FRF_BB_PCIE_CORE_TARGET_DATA_LBN 32 #define FRF_BB_PCIE_CORE_TARGET_DATA_WIDTH 32 #define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_LBN 15 #define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_WIDTH 1 #define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_LBN 0 #define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_WIDTH 12 /* * FR_AB_GPIO_CTL_REG(128bit): * GPIO control register */ #define FR_AB_GPIO_CTL_REG_OFST 0x00000210 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_GPIO15_OEN_LBN 63 #define FRF_AB_GPIO15_OEN_WIDTH 1 #define FRF_AB_GPIO14_OEN_LBN 62 #define FRF_AB_GPIO14_OEN_WIDTH 1 #define FRF_AB_GPIO13_OEN_LBN 61 #define FRF_AB_GPIO13_OEN_WIDTH 1 #define FRF_AB_GPIO12_OEN_LBN 60 #define FRF_AB_GPIO12_OEN_WIDTH 1 #define FRF_AB_GPIO11_OEN_LBN 59 #define FRF_AB_GPIO11_OEN_WIDTH 1 #define FRF_AB_GPIO10_OEN_LBN 58 #define FRF_AB_GPIO10_OEN_WIDTH 1 #define FRF_AB_GPIO9_OEN_LBN 57 #define FRF_AB_GPIO9_OEN_WIDTH 1 #define FRF_AB_GPIO8_OEN_LBN 56 #define FRF_AB_GPIO8_OEN_WIDTH 1 #define FRF_AB_GPIO15_OUT_LBN 55 #define FRF_AB_GPIO15_OUT_WIDTH 1 #define FRF_AB_GPIO14_OUT_LBN 54 #define FRF_AB_GPIO14_OUT_WIDTH 1 #define FRF_AB_GPIO13_OUT_LBN 53 #define FRF_AB_GPIO13_OUT_WIDTH 1 #define FRF_AB_GPIO12_OUT_LBN 52 #define FRF_AB_GPIO12_OUT_WIDTH 1 #define FRF_AB_GPIO11_OUT_LBN 51 #define FRF_AB_GPIO11_OUT_WIDTH 1 #define FRF_AB_GPIO10_OUT_LBN 50 #define FRF_AB_GPIO10_OUT_WIDTH 1 #define FRF_AB_GPIO9_OUT_LBN 49 #define FRF_AB_GPIO9_OUT_WIDTH 1 #define FRF_AB_GPIO8_OUT_LBN 48 #define FRF_AB_GPIO8_OUT_WIDTH 1 #define FRF_AB_GPIO15_IN_LBN 47 #define FRF_AB_GPIO15_IN_WIDTH 1 #define FRF_AB_GPIO14_IN_LBN 46 #define FRF_AB_GPIO14_IN_WIDTH 1 #define FRF_AB_GPIO13_IN_LBN 45 #define FRF_AB_GPIO13_IN_WIDTH 1 #define FRF_AB_GPIO12_IN_LBN 44 #define FRF_AB_GPIO12_IN_WIDTH 1 #define FRF_AB_GPIO11_IN_LBN 43 #define FRF_AB_GPIO11_IN_WIDTH 1 #define FRF_AB_GPIO10_IN_LBN 42 #define FRF_AB_GPIO10_IN_WIDTH 1 #define FRF_AB_GPIO9_IN_LBN 41 #define FRF_AB_GPIO9_IN_WIDTH 1 #define FRF_AB_GPIO8_IN_LBN 40 #define FRF_AB_GPIO8_IN_WIDTH 1 #define FRF_AB_GPIO15_PWRUP_VALUE_LBN 39 #define FRF_AB_GPIO15_PWRUP_VALUE_WIDTH 1 #define FRF_AB_GPIO14_PWRUP_VALUE_LBN 38 #define FRF_AB_GPIO14_PWRUP_VALUE_WIDTH 1 #define FRF_AB_GPIO13_PWRUP_VALUE_LBN 37 #define FRF_AB_GPIO13_PWRUP_VALUE_WIDTH 1 #define FRF_AB_GPIO12_PWRUP_VALUE_LBN 36 #define FRF_AB_GPIO12_PWRUP_VALUE_WIDTH 1 #define FRF_AB_GPIO11_PWRUP_VALUE_LBN 35 #define FRF_AB_GPIO11_PWRUP_VALUE_WIDTH 1 #define FRF_AB_GPIO10_PWRUP_VALUE_LBN 34 #define FRF_AB_GPIO10_PWRUP_VALUE_WIDTH 1 #define FRF_AB_GPIO9_PWRUP_VALUE_LBN 33 #define FRF_AB_GPIO9_PWRUP_VALUE_WIDTH 1 #define FRF_AB_GPIO8_PWRUP_VALUE_LBN 32 #define FRF_AB_GPIO8_PWRUP_VALUE_WIDTH 1 #define FRF_BB_CLK156_OUT_EN_LBN 31 #define FRF_BB_CLK156_OUT_EN_WIDTH 1 #define FRF_BB_USE_NIC_CLK_LBN 30 #define FRF_BB_USE_NIC_CLK_WIDTH 1 #define FRF_AB_GPIO5_OEN_LBN 29 #define FRF_AB_GPIO5_OEN_WIDTH 1 #define FRF_AB_GPIO4_OEN_LBN 28 #define FRF_AB_GPIO4_OEN_WIDTH 1 #define FRF_AB_GPIO3_OEN_LBN 27 #define FRF_AB_GPIO3_OEN_WIDTH 1 #define FRF_AB_GPIO2_OEN_LBN 26 #define FRF_AB_GPIO2_OEN_WIDTH 1 #define FRF_AB_GPIO1_OEN_LBN 25 #define FRF_AB_GPIO1_OEN_WIDTH 1 #define FRF_AB_GPIO0_OEN_LBN 24 #define FRF_AB_GPIO0_OEN_WIDTH 1 #define FRF_AB_GPIO5_OUT_LBN 21 #define FRF_AB_GPIO5_OUT_WIDTH 1 #define FRF_AB_GPIO4_OUT_LBN 20 #define FRF_AB_GPIO4_OUT_WIDTH 1 #define FRF_AB_GPIO3_OUT_LBN 19 #define FRF_AB_GPIO3_OUT_WIDTH 1 #define FRF_AB_GPIO2_OUT_LBN 18 #define FRF_AB_GPIO2_OUT_WIDTH 1 #define FRF_AB_GPIO1_OUT_LBN 17 #define FRF_AB_GPIO1_OUT_WIDTH 1 #define FRF_AB_GPIO0_OUT_LBN 16 #define FRF_AB_GPIO0_OUT_WIDTH 1 #define FRF_AB_GPIO5_IN_LBN 13 #define FRF_AB_GPIO5_IN_WIDTH 1 #define FRF_AB_GPIO4_IN_LBN 12 #define FRF_AB_GPIO4_IN_WIDTH 1 #define FRF_AB_GPIO3_IN_LBN 11 #define FRF_AB_GPIO3_IN_WIDTH 1 #define FRF_AB_GPIO2_IN_LBN 10 #define FRF_AB_GPIO2_IN_WIDTH 1 #define FRF_AB_GPIO1_IN_LBN 9 #define FRF_AB_GPIO1_IN_WIDTH 1 #define FRF_AB_GPIO0_IN_LBN 8 #define FRF_AB_GPIO0_IN_WIDTH 1 #define FRF_AB_GPIO5_PWRUP_VALUE_LBN 5 #define FRF_AB_GPIO5_PWRUP_VALUE_WIDTH 1 #define FRF_AB_GPIO4_PWRUP_VALUE_LBN 4 #define FRF_AB_GPIO4_PWRUP_VALUE_WIDTH 1 #define FRF_AB_GPIO3_PWRUP_VALUE_LBN 3 #define FRF_AB_GPIO3_PWRUP_VALUE_WIDTH 1 #define FRF_AB_GPIO2_PWRUP_VALUE_LBN 2 #define FRF_AB_GPIO2_PWRUP_VALUE_WIDTH 1 #define FRF_AB_GPIO1_PWRUP_VALUE_LBN 1 #define FRF_AB_GPIO1_PWRUP_VALUE_WIDTH 1 #define FRF_AB_GPIO0_PWRUP_VALUE_LBN 0 #define FRF_AB_GPIO0_PWRUP_VALUE_WIDTH 1 /* * FR_AZ_FATAL_INTR_REG_KER(128bit): * Fatal interrupt register for Kernel */ #define FR_AZ_FATAL_INTR_REG_KER_OFST 0x00000230 /* falcona0,falconb0,sienaa0=net_func_bar2 */ #define FRF_CZ_SRAM_PERR_INT_P_KER_EN_LBN 44 #define FRF_CZ_SRAM_PERR_INT_P_KER_EN_WIDTH 1 #define FRF_AB_PCI_BUSERR_INT_KER_EN_LBN 43 #define FRF_AB_PCI_BUSERR_INT_KER_EN_WIDTH 1 #define FRF_CZ_MBU_PERR_INT_KER_EN_LBN 43 #define FRF_CZ_MBU_PERR_INT_KER_EN_WIDTH 1 #define FRF_AZ_SRAM_OOB_INT_KER_EN_LBN 42 #define FRF_AZ_SRAM_OOB_INT_KER_EN_WIDTH 1 #define FRF_AZ_BUFID_OOB_INT_KER_EN_LBN 41 #define FRF_AZ_BUFID_OOB_INT_KER_EN_WIDTH 1 #define FRF_AZ_MEM_PERR_INT_KER_EN_LBN 40 #define FRF_AZ_MEM_PERR_INT_KER_EN_WIDTH 1 #define FRF_AZ_RBUF_OWN_INT_KER_EN_LBN 39 #define FRF_AZ_RBUF_OWN_INT_KER_EN_WIDTH 1 #define FRF_AZ_TBUF_OWN_INT_KER_EN_LBN 38 #define FRF_AZ_TBUF_OWN_INT_KER_EN_WIDTH 1 #define FRF_AZ_RDESCQ_OWN_INT_KER_EN_LBN 37 #define FRF_AZ_RDESCQ_OWN_INT_KER_EN_WIDTH 1 #define FRF_AZ_TDESCQ_OWN_INT_KER_EN_LBN 36 #define FRF_AZ_TDESCQ_OWN_INT_KER_EN_WIDTH 1 #define FRF_AZ_EVQ_OWN_INT_KER_EN_LBN 35 #define FRF_AZ_EVQ_OWN_INT_KER_EN_WIDTH 1 #define FRF_AZ_EVF_OFLO_INT_KER_EN_LBN 34 #define FRF_AZ_EVF_OFLO_INT_KER_EN_WIDTH 1 #define FRF_AZ_ILL_ADR_INT_KER_EN_LBN 33 #define FRF_AZ_ILL_ADR_INT_KER_EN_WIDTH 1 #define FRF_AZ_SRM_PERR_INT_KER_EN_LBN 32 #define FRF_AZ_SRM_PERR_INT_KER_EN_WIDTH 1 #define FRF_CZ_SRAM_PERR_INT_P_KER_LBN 12 #define FRF_CZ_SRAM_PERR_INT_P_KER_WIDTH 1 #define FRF_AB_PCI_BUSERR_INT_KER_LBN 11 #define FRF_AB_PCI_BUSERR_INT_KER_WIDTH 1 #define FRF_CZ_MBU_PERR_INT_KER_LBN 11 #define FRF_CZ_MBU_PERR_INT_KER_WIDTH 1 #define FRF_AZ_SRAM_OOB_INT_KER_LBN 10 #define FRF_AZ_SRAM_OOB_INT_KER_WIDTH 1 #define FRF_AZ_BUFID_DC_OOB_INT_KER_LBN 9 #define FRF_AZ_BUFID_DC_OOB_INT_KER_WIDTH 1 #define FRF_AZ_MEM_PERR_INT_KER_LBN 8 #define FRF_AZ_MEM_PERR_INT_KER_WIDTH 1 #define FRF_AZ_RBUF_OWN_INT_KER_LBN 7 #define FRF_AZ_RBUF_OWN_INT_KER_WIDTH 1 #define FRF_AZ_TBUF_OWN_INT_KER_LBN 6 #define FRF_AZ_TBUF_OWN_INT_KER_WIDTH 1 #define FRF_AZ_RDESCQ_OWN_INT_KER_LBN 5 #define FRF_AZ_RDESCQ_OWN_INT_KER_WIDTH 1 #define FRF_AZ_TDESCQ_OWN_INT_KER_LBN 4 #define FRF_AZ_TDESCQ_OWN_INT_KER_WIDTH 1 #define FRF_AZ_EVQ_OWN_INT_KER_LBN 3 #define FRF_AZ_EVQ_OWN_INT_KER_WIDTH 1 #define FRF_AZ_EVF_OFLO_INT_KER_LBN 2 #define FRF_AZ_EVF_OFLO_INT_KER_WIDTH 1 #define FRF_AZ_ILL_ADR_INT_KER_LBN 1 #define FRF_AZ_ILL_ADR_INT_KER_WIDTH 1 #define FRF_AZ_SRM_PERR_INT_KER_LBN 0 #define FRF_AZ_SRM_PERR_INT_KER_WIDTH 1 /* * FR_AZ_FATAL_INTR_REG_CHAR(128bit): * Fatal interrupt register for Char */ #define FR_AZ_FATAL_INTR_REG_CHAR_OFST 0x00000240 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_LBN 44 #define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_WIDTH 1 #define FRF_AB_PCI_BUSERR_INT_CHAR_EN_LBN 43 #define FRF_AB_PCI_BUSERR_INT_CHAR_EN_WIDTH 1 #define FRF_CZ_MBU_PERR_INT_CHAR_EN_LBN 43 #define FRF_CZ_MBU_PERR_INT_CHAR_EN_WIDTH 1 #define FRF_AZ_SRAM_OOB_INT_CHAR_EN_LBN 42 #define FRF_AZ_SRAM_OOB_INT_CHAR_EN_WIDTH 1 #define FRF_AZ_BUFID_OOB_INT_CHAR_EN_LBN 41 #define FRF_AZ_BUFID_OOB_INT_CHAR_EN_WIDTH 1 #define FRF_AZ_MEM_PERR_INT_CHAR_EN_LBN 40 #define FRF_AZ_MEM_PERR_INT_CHAR_EN_WIDTH 1 #define FRF_AZ_RBUF_OWN_INT_CHAR_EN_LBN 39 #define FRF_AZ_RBUF_OWN_INT_CHAR_EN_WIDTH 1 #define FRF_AZ_TBUF_OWN_INT_CHAR_EN_LBN 38 #define FRF_AZ_TBUF_OWN_INT_CHAR_EN_WIDTH 1 #define FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_LBN 37 #define FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_WIDTH 1 #define FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_LBN 36 #define FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_WIDTH 1 #define FRF_AZ_EVQ_OWN_INT_CHAR_EN_LBN 35 #define FRF_AZ_EVQ_OWN_INT_CHAR_EN_WIDTH 1 #define FRF_AZ_EVF_OFLO_INT_CHAR_EN_LBN 34 #define FRF_AZ_EVF_OFLO_INT_CHAR_EN_WIDTH 1 #define FRF_AZ_ILL_ADR_INT_CHAR_EN_LBN 33 #define FRF_AZ_ILL_ADR_INT_CHAR_EN_WIDTH 1 #define FRF_AZ_SRM_PERR_INT_CHAR_EN_LBN 32 #define FRF_AZ_SRM_PERR_INT_CHAR_EN_WIDTH 1 #define FRF_CZ_SRAM_PERR_INT_P_CHAR_LBN 12 #define FRF_CZ_SRAM_PERR_INT_P_CHAR_WIDTH 1 #define FRF_AB_PCI_BUSERR_INT_CHAR_LBN 11 #define FRF_AB_PCI_BUSERR_INT_CHAR_WIDTH 1 #define FRF_CZ_MBU_PERR_INT_CHAR_LBN 11 #define FRF_CZ_MBU_PERR_INT_CHAR_WIDTH 1 #define FRF_AZ_SRAM_OOB_INT_CHAR_LBN 10 #define FRF_AZ_SRAM_OOB_INT_CHAR_WIDTH 1 #define FRF_AZ_BUFID_DC_OOB_INT_CHAR_LBN 9 #define FRF_AZ_BUFID_DC_OOB_INT_CHAR_WIDTH 1 #define FRF_AZ_MEM_PERR_INT_CHAR_LBN 8 #define FRF_AZ_MEM_PERR_INT_CHAR_WIDTH 1 #define FRF_AZ_RBUF_OWN_INT_CHAR_LBN 7 #define FRF_AZ_RBUF_OWN_INT_CHAR_WIDTH 1 #define FRF_AZ_TBUF_OWN_INT_CHAR_LBN 6 #define FRF_AZ_TBUF_OWN_INT_CHAR_WIDTH 1 #define FRF_AZ_RDESCQ_OWN_INT_CHAR_LBN 5 #define FRF_AZ_RDESCQ_OWN_INT_CHAR_WIDTH 1 #define FRF_AZ_TDESCQ_OWN_INT_CHAR_LBN 4 #define FRF_AZ_TDESCQ_OWN_INT_CHAR_WIDTH 1 #define FRF_AZ_EVQ_OWN_INT_CHAR_LBN 3 #define FRF_AZ_EVQ_OWN_INT_CHAR_WIDTH 1 #define FRF_AZ_EVF_OFLO_INT_CHAR_LBN 2 #define FRF_AZ_EVF_OFLO_INT_CHAR_WIDTH 1 #define FRF_AZ_ILL_ADR_INT_CHAR_LBN 1 #define FRF_AZ_ILL_ADR_INT_CHAR_WIDTH 1 #define FRF_AZ_SRM_PERR_INT_CHAR_LBN 0 #define FRF_AZ_SRM_PERR_INT_CHAR_WIDTH 1 /* * FR_AZ_DP_CTRL_REG(128bit): * Datapath control register */ #define FR_AZ_DP_CTRL_REG_OFST 0x00000250 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_FLS_EVQ_ID_LBN 0 #define FRF_AZ_FLS_EVQ_ID_WIDTH 12 /* * FR_AZ_MEM_STAT_REG(128bit): * Memory status register */ #define FR_AZ_MEM_STAT_REG_OFST 0x00000260 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_MEM_PERR_VEC_LBN 53 #define FRF_AB_MEM_PERR_VEC_WIDTH 40 #define FRF_AB_MEM_PERR_VEC_DW0_LBN 53 #define FRF_AB_MEM_PERR_VEC_DW0_WIDTH 32 #define FRF_AB_MEM_PERR_VEC_DW1_LBN 85 #define FRF_AB_MEM_PERR_VEC_DW1_WIDTH 6 #define FRF_AB_MBIST_CORR_LBN 38 #define FRF_AB_MBIST_CORR_WIDTH 15 #define FRF_AB_MBIST_ERR_LBN 0 #define FRF_AB_MBIST_ERR_WIDTH 40 #define FRF_AB_MBIST_ERR_DW0_LBN 0 #define FRF_AB_MBIST_ERR_DW0_WIDTH 32 #define FRF_AB_MBIST_ERR_DW1_LBN 32 #define FRF_AB_MBIST_ERR_DW1_WIDTH 6 #define FRF_CZ_MEM_PERR_VEC_LBN 0 #define FRF_CZ_MEM_PERR_VEC_WIDTH 35 #define FRF_CZ_MEM_PERR_VEC_DW0_LBN 0 #define FRF_CZ_MEM_PERR_VEC_DW0_WIDTH 32 #define FRF_CZ_MEM_PERR_VEC_DW1_LBN 32 #define FRF_CZ_MEM_PERR_VEC_DW1_WIDTH 3 /* * FR_PORT0_CS_DEBUG_REG(128bit): * Debug register */ #define FR_AZ_CS_DEBUG_REG_OFST 0x00000270 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_GLB_DEBUG2_SEL_LBN 50 #define FRF_AB_GLB_DEBUG2_SEL_WIDTH 3 #define FRF_AB_DEBUG_BLK_SEL2_LBN 47 #define FRF_AB_DEBUG_BLK_SEL2_WIDTH 3 #define FRF_AB_DEBUG_BLK_SEL1_LBN 44 #define FRF_AB_DEBUG_BLK_SEL1_WIDTH 3 #define FRF_AB_DEBUG_BLK_SEL0_LBN 41 #define FRF_AB_DEBUG_BLK_SEL0_WIDTH 3 #define FRF_CZ_CS_PORT_NUM_LBN 40 #define FRF_CZ_CS_PORT_NUM_WIDTH 2 #define FRF_AB_MISC_DEBUG_ADDR_LBN 36 #define FRF_AB_MISC_DEBUG_ADDR_WIDTH 5 #define FRF_CZ_CS_RESERVED_LBN 36 #define FRF_CZ_CS_RESERVED_WIDTH 4 #define FRF_AB_SERDES_DEBUG_ADDR_LBN 31 #define FRF_AB_SERDES_DEBUG_ADDR_WIDTH 5 #define FRF_CZ_CS_PORT_FPE_DW0_LBN 1 #define FRF_CZ_CS_PORT_FPE_DW0_WIDTH 32 #define FRF_CZ_CS_PORT_FPE_DW1_LBN 33 #define FRF_CZ_CS_PORT_FPE_DW1_WIDTH 3 #define FRF_CZ_CS_PORT_FPE_LBN 1 #define FRF_CZ_CS_PORT_FPE_WIDTH 35 #define FRF_AB_EM_DEBUG_ADDR_LBN 26 #define FRF_AB_EM_DEBUG_ADDR_WIDTH 5 #define FRF_AB_SR_DEBUG_ADDR_LBN 21 #define FRF_AB_SR_DEBUG_ADDR_WIDTH 5 #define FRF_AB_EV_DEBUG_ADDR_LBN 16 #define FRF_AB_EV_DEBUG_ADDR_WIDTH 5 #define FRF_AB_RX_DEBUG_ADDR_LBN 11 #define FRF_AB_RX_DEBUG_ADDR_WIDTH 5 #define FRF_AB_TX_DEBUG_ADDR_LBN 6 #define FRF_AB_TX_DEBUG_ADDR_WIDTH 5 #define FRF_AB_CS_BIU_DEBUG_ADDR_LBN 1 #define FRF_AB_CS_BIU_DEBUG_ADDR_WIDTH 5 #define FRF_AZ_CS_DEBUG_EN_LBN 0 #define FRF_AZ_CS_DEBUG_EN_WIDTH 1 /* * FR_AZ_DRIVER_REG(128bit): * Driver scratch register [0-7] */ #define FR_AZ_DRIVER_REG_OFST 0x00000280 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FR_AZ_DRIVER_REG_STEP 16 #define FR_AZ_DRIVER_REG_ROWS 8 #define FRF_AZ_DRIVER_DW0_LBN 0 #define FRF_AZ_DRIVER_DW0_WIDTH 32 /* * FR_AZ_ALTERA_BUILD_REG(128bit): * Altera build register */ #define FR_AZ_ALTERA_BUILD_REG_OFST 0x00000300 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_ALTERA_BUILD_VER_LBN 0 #define FRF_AZ_ALTERA_BUILD_VER_WIDTH 32 /* * FR_AZ_CSR_SPARE_REG(128bit): * Spare register */ #define FR_AZ_CSR_SPARE_REG_OFST 0x00000310 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_MEM_PERR_EN_TX_DATA_LBN 72 #define FRF_AZ_MEM_PERR_EN_TX_DATA_WIDTH 2 #define FRF_AZ_MEM_PERR_EN_LBN 64 #define FRF_AZ_MEM_PERR_EN_WIDTH 38 #define FRF_AZ_MEM_PERR_EN_DW0_LBN 64 #define FRF_AZ_MEM_PERR_EN_DW0_WIDTH 32 #define FRF_AZ_MEM_PERR_EN_DW1_LBN 96 #define FRF_AZ_MEM_PERR_EN_DW1_WIDTH 6 #define FRF_AZ_CSR_SPARE_BITS_LBN 0 #define FRF_AZ_CSR_SPARE_BITS_WIDTH 32 /* * FR_BZ_DEBUG_DATA_OUT_REG(128bit): * Live Debug and Debug 2 out ports */ #define FR_BZ_DEBUG_DATA_OUT_REG_OFST 0x00000350 /* falconb0,sienaa0=net_func_bar2 */ #define FRF_BZ_DEBUG2_PORT_LBN 25 #define FRF_BZ_DEBUG2_PORT_WIDTH 15 #define FRF_BZ_DEBUG1_PORT_LBN 0 #define FRF_BZ_DEBUG1_PORT_WIDTH 25 /* * FR_BZ_EVQ_RPTR_REGP0(32bit): * Event queue read pointer register */ #define FR_BZ_EVQ_RPTR_REGP0_OFST 0x00000400 /* falconb0,sienaa0=net_func_bar2 */ #define FR_BZ_EVQ_RPTR_REGP0_STEP 8192 #define FR_BZ_EVQ_RPTR_REGP0_ROWS 1024 /* * FR_AA_EVQ_RPTR_REG_KER(32bit): * Event queue read pointer register */ #define FR_AA_EVQ_RPTR_REG_KER_OFST 0x00011b00 /* falcona0=net_func_bar2 */ #define FR_AA_EVQ_RPTR_REG_KER_STEP 4 #define FR_AA_EVQ_RPTR_REG_KER_ROWS 4 /* * FR_AZ_EVQ_RPTR_REG(32bit): * Event queue read pointer register */ #define FR_AZ_EVQ_RPTR_REG_OFST 0x00fa0000 /* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FR_AZ_EVQ_RPTR_REG_STEP 16 #define FR_AB_EVQ_RPTR_REG_ROWS 4096 #define FR_CZ_EVQ_RPTR_REG_ROWS 1024 /* * FR_BB_EVQ_RPTR_REGP123(32bit): * Event queue read pointer register */ #define FR_BB_EVQ_RPTR_REGP123_OFST 0x01000400 /* falconb0=net_func_bar2 */ #define FR_BB_EVQ_RPTR_REGP123_STEP 8192 #define FR_BB_EVQ_RPTR_REGP123_ROWS 3072 #define FRF_AZ_EVQ_RPTR_VLD_LBN 15 #define FRF_AZ_EVQ_RPTR_VLD_WIDTH 1 #define FRF_AZ_EVQ_RPTR_LBN 0 #define FRF_AZ_EVQ_RPTR_WIDTH 15 /* * FR_BZ_TIMER_COMMAND_REGP0(128bit): * Timer Command Registers */ #define FR_BZ_TIMER_COMMAND_REGP0_OFST 0x00000420 /* falconb0,sienaa0=net_func_bar2 */ #define FR_BZ_TIMER_COMMAND_REGP0_STEP 8192 #define FR_BZ_TIMER_COMMAND_REGP0_ROWS 1024 /* * FR_AA_TIMER_COMMAND_REG_KER(128bit): * Timer Command Registers */ #define FR_AA_TIMER_COMMAND_REG_KER_OFST 0x00000420 /* falcona0=net_func_bar2 */ #define FR_AA_TIMER_COMMAND_REG_KER_STEP 8192 #define FR_AA_TIMER_COMMAND_REG_KER_ROWS 4 /* * FR_AB_TIMER_COMMAND_REGP123(128bit): * Timer Command Registers */ #define FR_AB_TIMER_COMMAND_REGP123_OFST 0x01000420 /* falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FR_AB_TIMER_COMMAND_REGP123_STEP 8192 #define FR_AB_TIMER_COMMAND_REGP123_ROWS 3072 /* * FR_AA_TIMER_COMMAND_REGP0(128bit): * Timer Command Registers */ #define FR_AA_TIMER_COMMAND_REGP0_OFST 0x00008420 /* falcona0=char_func_bar0 */ #define FR_AA_TIMER_COMMAND_REGP0_STEP 8192 #define FR_AA_TIMER_COMMAND_REGP0_ROWS 1020 #define FRF_CZ_TC_TIMER_MODE_LBN 14 #define FRF_CZ_TC_TIMER_MODE_WIDTH 2 #define FRF_AB_TC_TIMER_MODE_LBN 12 #define FRF_AB_TC_TIMER_MODE_WIDTH 2 #define FRF_CZ_TC_TIMER_VAL_LBN 0 #define FRF_CZ_TC_TIMER_VAL_WIDTH 14 #define FRF_AB_TC_TIMER_VAL_LBN 0 #define FRF_AB_TC_TIMER_VAL_WIDTH 12 /* * FR_AZ_DRV_EV_REG(128bit): * Driver generated event register */ #define FR_AZ_DRV_EV_REG_OFST 0x00000440 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_DRV_EV_QID_LBN 64 #define FRF_AZ_DRV_EV_QID_WIDTH 12 #define FRF_AZ_DRV_EV_DATA_LBN 0 #define FRF_AZ_DRV_EV_DATA_WIDTH 64 #define FRF_AZ_DRV_EV_DATA_DW0_LBN 0 #define FRF_AZ_DRV_EV_DATA_DW0_WIDTH 32 #define FRF_AZ_DRV_EV_DATA_DW1_LBN 32 #define FRF_AZ_DRV_EV_DATA_DW1_WIDTH 32 /* * FR_AZ_EVQ_CTL_REG(128bit): * Event queue control register */ #define FR_AZ_EVQ_CTL_REG_OFST 0x00000450 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_CZ_RX_EVQ_WAKEUP_MASK_LBN 15 #define FRF_CZ_RX_EVQ_WAKEUP_MASK_WIDTH 10 #define FRF_BB_RX_EVQ_WAKEUP_MASK_LBN 15 #define FRF_BB_RX_EVQ_WAKEUP_MASK_WIDTH 6 #define FRF_AZ_EVQ_OWNERR_CTL_LBN 14 #define FRF_AZ_EVQ_OWNERR_CTL_WIDTH 1 #define FRF_AZ_EVQ_FIFO_AF_TH_LBN 7 #define FRF_AZ_EVQ_FIFO_AF_TH_WIDTH 7 #define FRF_AZ_EVQ_FIFO_NOTAF_TH_LBN 0 #define FRF_AZ_EVQ_FIFO_NOTAF_TH_WIDTH 7 /* * FR_AZ_EVQ_CNT1_REG(128bit): * Event counter 1 register */ #define FR_AZ_EVQ_CNT1_REG_OFST 0x00000460 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_EVQ_CNT_PRE_FIFO_LBN 120 #define FRF_AZ_EVQ_CNT_PRE_FIFO_WIDTH 7 #define FRF_AZ_EVQ_CNT_TOBIU_LBN 100 #define FRF_AZ_EVQ_CNT_TOBIU_WIDTH 20 #define FRF_AZ_EVQ_TX_REQ_CNT_LBN 80 #define FRF_AZ_EVQ_TX_REQ_CNT_WIDTH 20 #define FRF_AZ_EVQ_RX_REQ_CNT_LBN 60 #define FRF_AZ_EVQ_RX_REQ_CNT_WIDTH 20 #define FRF_AZ_EVQ_EM_REQ_CNT_LBN 40 #define FRF_AZ_EVQ_EM_REQ_CNT_WIDTH 20 #define FRF_AZ_EVQ_CSR_REQ_CNT_LBN 20 #define FRF_AZ_EVQ_CSR_REQ_CNT_WIDTH 20 #define FRF_AZ_EVQ_ERR_REQ_CNT_LBN 0 #define FRF_AZ_EVQ_ERR_REQ_CNT_WIDTH 20 /* * FR_AZ_EVQ_CNT2_REG(128bit): * Event counter 2 register */ #define FR_AZ_EVQ_CNT2_REG_OFST 0x00000470 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_EVQ_UPD_REQ_CNT_LBN 104 #define FRF_AZ_EVQ_UPD_REQ_CNT_WIDTH 20 #define FRF_AZ_EVQ_CLR_REQ_CNT_LBN 84 #define FRF_AZ_EVQ_CLR_REQ_CNT_WIDTH 20 #define FRF_AZ_EVQ_RDY_CNT_LBN 80 #define FRF_AZ_EVQ_RDY_CNT_WIDTH 4 #define FRF_AZ_EVQ_WU_REQ_CNT_LBN 60 #define FRF_AZ_EVQ_WU_REQ_CNT_WIDTH 20 #define FRF_AZ_EVQ_WET_REQ_CNT_LBN 40 #define FRF_AZ_EVQ_WET_REQ_CNT_WIDTH 20 #define FRF_AZ_EVQ_INIT_REQ_CNT_LBN 20 #define FRF_AZ_EVQ_INIT_REQ_CNT_WIDTH 20 #define FRF_AZ_EVQ_TM_REQ_CNT_LBN 0 #define FRF_AZ_EVQ_TM_REQ_CNT_WIDTH 20 /* * FR_CZ_USR_EV_REG(32bit): * Event mailbox register */ #define FR_CZ_USR_EV_REG_OFST 0x00000540 /* sienaa0=net_func_bar2 */ #define FR_CZ_USR_EV_REG_STEP 8192 #define FR_CZ_USR_EV_REG_ROWS 1024 #define FRF_CZ_USR_EV_DATA_LBN 0 #define FRF_CZ_USR_EV_DATA_WIDTH 32 /* * FR_AZ_BUF_TBL_CFG_REG(128bit): * Buffer table configuration register */ #define FR_AZ_BUF_TBL_CFG_REG_OFST 0x00000600 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_BUF_TBL_MODE_LBN 3 #define FRF_AZ_BUF_TBL_MODE_WIDTH 1 /* * FR_AZ_SRM_RX_DC_CFG_REG(128bit): * SRAM receive descriptor cache configuration register */ #define FR_AZ_SRM_RX_DC_CFG_REG_OFST 0x00000610 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_SRM_CLK_TMP_EN_LBN 21 #define FRF_AZ_SRM_CLK_TMP_EN_WIDTH 1 #define FRF_AZ_SRM_RX_DC_BASE_ADR_LBN 0 #define FRF_AZ_SRM_RX_DC_BASE_ADR_WIDTH 21 /* * FR_AZ_SRM_TX_DC_CFG_REG(128bit): * SRAM transmit descriptor cache configuration register */ #define FR_AZ_SRM_TX_DC_CFG_REG_OFST 0x00000620 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_SRM_TX_DC_BASE_ADR_LBN 0 #define FRF_AZ_SRM_TX_DC_BASE_ADR_WIDTH 21 /* * FR_AZ_SRM_CFG_REG(128bit): * SRAM configuration register */ #define FR_AZ_SRM_CFG_REG_SF_OFST 0x00000380 /* falcona0,falconb0=eeprom_flash */ /* * FR_AZ_SRM_CFG_REG(128bit): * SRAM configuration register */ #define FR_AZ_SRM_CFG_REG_OFST 0x00000630 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_SRM_OOB_ADR_INTEN_LBN 5 #define FRF_AZ_SRM_OOB_ADR_INTEN_WIDTH 1 #define FRF_AZ_SRM_OOB_BUF_INTEN_LBN 4 #define FRF_AZ_SRM_OOB_BUF_INTEN_WIDTH 1 #define FRF_AZ_SRM_INIT_EN_LBN 3 #define FRF_AZ_SRM_INIT_EN_WIDTH 1 #define FRF_AZ_SRM_NUM_BANK_LBN 2 #define FRF_AZ_SRM_NUM_BANK_WIDTH 1 #define FRF_AZ_SRM_BANK_SIZE_LBN 0 #define FRF_AZ_SRM_BANK_SIZE_WIDTH 2 /* * FR_AZ_BUF_TBL_UPD_REG(128bit): * Buffer table update register */ #define FR_AZ_BUF_TBL_UPD_REG_OFST 0x00000650 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_BUF_UPD_CMD_LBN 63 #define FRF_AZ_BUF_UPD_CMD_WIDTH 1 #define FRF_AZ_BUF_CLR_CMD_LBN 62 #define FRF_AZ_BUF_CLR_CMD_WIDTH 1 #define FRF_AZ_BUF_CLR_END_ID_LBN 32 #define FRF_AZ_BUF_CLR_END_ID_WIDTH 20 #define FRF_AZ_BUF_CLR_START_ID_LBN 0 #define FRF_AZ_BUF_CLR_START_ID_WIDTH 20 /* * FR_AZ_SRM_UPD_EVQ_REG(128bit): * Buffer table update register */ #define FR_AZ_SRM_UPD_EVQ_REG_OFST 0x00000660 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_SRM_UPD_EVQ_ID_LBN 0 #define FRF_AZ_SRM_UPD_EVQ_ID_WIDTH 12 /* * FR_AZ_SRAM_PARITY_REG(128bit): * SRAM parity register. */ #define FR_AZ_SRAM_PARITY_REG_OFST 0x00000670 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_CZ_BYPASS_ECC_LBN 3 #define FRF_CZ_BYPASS_ECC_WIDTH 1 #define FRF_CZ_SEC_INT_LBN 2 #define FRF_CZ_SEC_INT_WIDTH 1 #define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_LBN 1 #define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_WIDTH 1 #define FRF_CZ_FORCE_SRAM_SINGLE_ERR_LBN 0 #define FRF_CZ_FORCE_SRAM_SINGLE_ERR_WIDTH 1 #define FRF_AB_FORCE_SRAM_PERR_LBN 0 #define FRF_AB_FORCE_SRAM_PERR_WIDTH 1 /* * FR_AZ_RX_CFG_REG(128bit): * Receive configuration register */ #define FR_AZ_RX_CFG_REG_OFST 0x00000800 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_CZ_RX_HDR_SPLIT_EN_LBN 71 #define FRF_CZ_RX_HDR_SPLIT_EN_WIDTH 1 #define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_LBN 62 #define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_WIDTH 9 #define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_LBN 53 #define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_WIDTH 9 #define FRF_CZ_RX_PRE_RFF_IPG_LBN 49 #define FRF_CZ_RX_PRE_RFF_IPG_WIDTH 4 #define FRF_BZ_RX_TCP_SUP_LBN 48 #define FRF_BZ_RX_TCP_SUP_WIDTH 1 #define FRF_BZ_RX_INGR_EN_LBN 47 #define FRF_BZ_RX_INGR_EN_WIDTH 1 #define FRF_BZ_RX_IP_HASH_LBN 46 #define FRF_BZ_RX_IP_HASH_WIDTH 1 #define FRF_BZ_RX_HASH_ALG_LBN 45 #define FRF_BZ_RX_HASH_ALG_WIDTH 1 #define FRF_BZ_RX_HASH_INSRT_HDR_LBN 44 #define FRF_BZ_RX_HASH_INSRT_HDR_WIDTH 1 #define FRF_BZ_RX_DESC_PUSH_EN_LBN 43 #define FRF_BZ_RX_DESC_PUSH_EN_WIDTH 1 #define FRF_BZ_RX_RDW_PATCH_EN_LBN 42 #define FRF_BZ_RX_RDW_PATCH_EN_WIDTH 1 #define FRF_BB_RX_PCI_BURST_SIZE_LBN 39 #define FRF_BB_RX_PCI_BURST_SIZE_WIDTH 3 #define FRF_BZ_RX_OWNERR_CTL_LBN 38 #define FRF_BZ_RX_OWNERR_CTL_WIDTH 1 #define FRF_BZ_RX_XON_TX_TH_LBN 33 #define FRF_BZ_RX_XON_TX_TH_WIDTH 5 #define FRF_AA_RX_DESC_PUSH_EN_LBN 35 #define FRF_AA_RX_DESC_PUSH_EN_WIDTH 1 #define FRF_AA_RX_RDW_PATCH_EN_LBN 34 #define FRF_AA_RX_RDW_PATCH_EN_WIDTH 1 #define FRF_AA_RX_PCI_BURST_SIZE_LBN 31 #define FRF_AA_RX_PCI_BURST_SIZE_WIDTH 3 #define FRF_BZ_RX_XOFF_TX_TH_LBN 28 #define FRF_BZ_RX_XOFF_TX_TH_WIDTH 5 #define FRF_AA_RX_OWNERR_CTL_LBN 30 #define FRF_AA_RX_OWNERR_CTL_WIDTH 1 #define FRF_AA_RX_XON_TX_TH_LBN 25 #define FRF_AA_RX_XON_TX_TH_WIDTH 5 #define FRF_BZ_RX_USR_BUF_SIZE_LBN 19 #define FRF_BZ_RX_USR_BUF_SIZE_WIDTH 9 #define FRF_AA_RX_XOFF_TX_TH_LBN 20 #define FRF_AA_RX_XOFF_TX_TH_WIDTH 5 #define FRF_AA_RX_USR_BUF_SIZE_LBN 11 #define FRF_AA_RX_USR_BUF_SIZE_WIDTH 9 #define FRF_BZ_RX_XON_MAC_TH_LBN 10 #define FRF_BZ_RX_XON_MAC_TH_WIDTH 9 #define FRF_AA_RX_XON_MAC_TH_LBN 6 #define FRF_AA_RX_XON_MAC_TH_WIDTH 5 #define FRF_BZ_RX_XOFF_MAC_TH_LBN 1 #define FRF_BZ_RX_XOFF_MAC_TH_WIDTH 9 #define FRF_AA_RX_XOFF_MAC_TH_LBN 1 #define FRF_AA_RX_XOFF_MAC_TH_WIDTH 5 #define FRF_AZ_RX_XOFF_MAC_EN_LBN 0 #define FRF_AZ_RX_XOFF_MAC_EN_WIDTH 1 /* * FR_AZ_RX_FILTER_CTL_REG(128bit): * Receive filter control registers */ #define FR_AZ_RX_FILTER_CTL_REG_OFST 0x00000810 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_LBN 94 #define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_WIDTH 8 #define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_LBN 86 #define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_WIDTH 8 #define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_LBN 85 #define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_WIDTH 1 #define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_LBN 69 #define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_WIDTH 16 #define FRF_CZ_MULTICAST_NOMATCH_Q_ID_LBN 57 #define FRF_CZ_MULTICAST_NOMATCH_Q_ID_WIDTH 12 #define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_LBN 56 #define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_WIDTH 1 #define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_LBN 55 #define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_WIDTH 1 #define FRF_CZ_UNICAST_NOMATCH_Q_ID_LBN 43 #define FRF_CZ_UNICAST_NOMATCH_Q_ID_WIDTH 12 #define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_LBN 42 #define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_WIDTH 1 #define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_LBN 41 #define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_WIDTH 1 #define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_LBN 40 #define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_WIDTH 1 #define FRF_AZ_UDP_FULL_SRCH_LIMIT_LBN 32 #define FRF_AZ_UDP_FULL_SRCH_LIMIT_WIDTH 8 #define FRF_AZ_NUM_KER_LBN 24 #define FRF_AZ_NUM_KER_WIDTH 2 #define FRF_AZ_UDP_WILD_SRCH_LIMIT_LBN 16 #define FRF_AZ_UDP_WILD_SRCH_LIMIT_WIDTH 8 #define FRF_AZ_TCP_WILD_SRCH_LIMIT_LBN 8 #define FRF_AZ_TCP_WILD_SRCH_LIMIT_WIDTH 8 #define FRF_AZ_TCP_FULL_SRCH_LIMIT_LBN 0 #define FRF_AZ_TCP_FULL_SRCH_LIMIT_WIDTH 8 /* * FR_AZ_RX_FLUSH_DESCQ_REG(128bit): * Receive flush descriptor queue register */ #define FR_AZ_RX_FLUSH_DESCQ_REG_OFST 0x00000820 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_RX_FLUSH_DESCQ_CMD_LBN 24 #define FRF_AZ_RX_FLUSH_DESCQ_CMD_WIDTH 1 #define FRF_AZ_RX_FLUSH_DESCQ_LBN 0 #define FRF_AZ_RX_FLUSH_DESCQ_WIDTH 12 /* * FR_BZ_RX_DESC_UPD_REGP0(128bit): * Receive descriptor update register. */ #define FR_BZ_RX_DESC_UPD_REGP0_OFST 0x00000830 /* falconb0,sienaa0=net_func_bar2 */ #define FR_BZ_RX_DESC_UPD_REGP0_STEP 8192 #define FR_BZ_RX_DESC_UPD_REGP0_ROWS 1024 /* * FR_AA_RX_DESC_UPD_REG_KER(128bit): * Receive descriptor update register. */ #define FR_AA_RX_DESC_UPD_REG_KER_OFST 0x00000830 /* falcona0=net_func_bar2 */ #define FR_AA_RX_DESC_UPD_REG_KER_STEP 8192 #define FR_AA_RX_DESC_UPD_REG_KER_ROWS 4 /* * FR_AB_RX_DESC_UPD_REGP123(128bit): * Receive descriptor update register. */ #define FR_AB_RX_DESC_UPD_REGP123_OFST 0x01000830 /* falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FR_AB_RX_DESC_UPD_REGP123_STEP 8192 #define FR_AB_RX_DESC_UPD_REGP123_ROWS 3072 /* * FR_AA_RX_DESC_UPD_REGP0(128bit): * Receive descriptor update register. */ #define FR_AA_RX_DESC_UPD_REGP0_OFST 0x00008830 /* falcona0=char_func_bar0 */ #define FR_AA_RX_DESC_UPD_REGP0_STEP 8192 #define FR_AA_RX_DESC_UPD_REGP0_ROWS 1020 #define FRF_AZ_RX_DESC_WPTR_LBN 96 #define FRF_AZ_RX_DESC_WPTR_WIDTH 12 #define FRF_AZ_RX_DESC_PUSH_CMD_LBN 95 #define FRF_AZ_RX_DESC_PUSH_CMD_WIDTH 1 #define FRF_AZ_RX_DESC_LBN 0 #define FRF_AZ_RX_DESC_WIDTH 64 #define FRF_AZ_RX_DESC_DW0_LBN 0 #define FRF_AZ_RX_DESC_DW0_WIDTH 32 #define FRF_AZ_RX_DESC_DW1_LBN 32 #define FRF_AZ_RX_DESC_DW1_WIDTH 32 /* * FR_AZ_RX_DC_CFG_REG(128bit): * Receive descriptor cache configuration register */ #define FR_AZ_RX_DC_CFG_REG_OFST 0x00000840 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_RX_MAX_PF_LBN 2 #define FRF_AZ_RX_MAX_PF_WIDTH 2 #define FRF_AZ_RX_DC_SIZE_LBN 0 #define FRF_AZ_RX_DC_SIZE_WIDTH 2 #define FFE_AZ_RX_DC_SIZE_64 3 #define FFE_AZ_RX_DC_SIZE_32 2 #define FFE_AZ_RX_DC_SIZE_16 1 #define FFE_AZ_RX_DC_SIZE_8 0 /* * FR_AZ_RX_DC_PF_WM_REG(128bit): * Receive descriptor cache pre-fetch watermark register */ #define FR_AZ_RX_DC_PF_WM_REG_OFST 0x00000850 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_RX_DC_PF_HWM_LBN 6 #define FRF_AZ_RX_DC_PF_HWM_WIDTH 6 #define FRF_AZ_RX_DC_PF_LWM_LBN 0 #define FRF_AZ_RX_DC_PF_LWM_WIDTH 6 /* * FR_BZ_RX_RSS_TKEY_REG(128bit): * RSS Toeplitz hash key */ #define FR_BZ_RX_RSS_TKEY_REG_OFST 0x00000860 /* falconb0,sienaa0=net_func_bar2 */ #define FRF_BZ_RX_RSS_TKEY_LBN 96 #define FRF_BZ_RX_RSS_TKEY_WIDTH 32 #define FRF_BZ_RX_RSS_TKEY_DW3_LBN 96 #define FRF_BZ_RX_RSS_TKEY_DW3_WIDTH 32 #define FRF_BZ_RX_RSS_TKEY_DW2_LBN 64 #define FRF_BZ_RX_RSS_TKEY_DW2_WIDTH 32 #define FRF_BZ_RX_RSS_TKEY_DW1_LBN 32 #define FRF_BZ_RX_RSS_TKEY_DW1_WIDTH 32 #define FRF_BZ_RX_RSS_TKEY_DW0_LBN 0 #define FRF_BZ_RX_RSS_TKEY_DW0_WIDTH 32 /* * FR_AZ_RX_NODESC_DROP_REG(128bit): * Receive dropped packet counter register */ #define FR_AZ_RX_NODESC_DROP_REG_OFST 0x00000880 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_RX_NODESC_DROP_CNT_LBN 0 #define FRF_AZ_RX_NODESC_DROP_CNT_WIDTH 16 /* * FR_AZ_RX_SELF_RST_REG(128bit): * Receive self reset register */ #define FR_AZ_RX_SELF_RST_REG_OFST 0x00000890 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_RX_ISCSI_DIS_LBN 17 #define FRF_AZ_RX_ISCSI_DIS_WIDTH 1 #define FRF_AB_RX_SW_RST_REG_LBN 16 #define FRF_AB_RX_SW_RST_REG_WIDTH 1 #define FRF_AB_RX_SELF_RST_EN_LBN 8 #define FRF_AB_RX_SELF_RST_EN_WIDTH 1 #define FRF_AZ_RX_MAX_PF_LAT_LBN 4 #define FRF_AZ_RX_MAX_PF_LAT_WIDTH 4 #define FRF_AZ_RX_MAX_LU_LAT_LBN 0 #define FRF_AZ_RX_MAX_LU_LAT_WIDTH 4 /* * FR_AZ_RX_DEBUG_REG(128bit): * undocumented register */ #define FR_AZ_RX_DEBUG_REG_OFST 0x000008a0 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_RX_DEBUG_LBN 0 #define FRF_AZ_RX_DEBUG_WIDTH 64 #define FRF_AZ_RX_DEBUG_DW0_LBN 0 #define FRF_AZ_RX_DEBUG_DW0_WIDTH 32 #define FRF_AZ_RX_DEBUG_DW1_LBN 32 #define FRF_AZ_RX_DEBUG_DW1_WIDTH 32 /* * FR_AZ_RX_PUSH_DROP_REG(128bit): * Receive descriptor push dropped counter register */ #define FR_AZ_RX_PUSH_DROP_REG_OFST 0x000008b0 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_RX_PUSH_DROP_CNT_LBN 0 #define FRF_AZ_RX_PUSH_DROP_CNT_WIDTH 32 /* * FR_CZ_RX_RSS_IPV6_REG1(128bit): * IPv6 RSS Toeplitz hash key low bytes */ #define FR_CZ_RX_RSS_IPV6_REG1_OFST 0x000008d0 /* sienaa0=net_func_bar2 */ #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN 0 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH 128 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_LBN 0 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_WIDTH 32 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_LBN 32 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_WIDTH 32 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_LBN 64 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_WIDTH 32 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_LBN 96 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_WIDTH 32 /* * FR_CZ_RX_RSS_IPV6_REG2(128bit): * IPv6 RSS Toeplitz hash key middle bytes */ #define FR_CZ_RX_RSS_IPV6_REG2_OFST 0x000008e0 /* sienaa0=net_func_bar2 */ #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN 0 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH 128 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_LBN 0 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_WIDTH 32 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_LBN 32 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_WIDTH 32 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_LBN 64 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_WIDTH 32 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_LBN 96 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_WIDTH 32 /* * FR_CZ_RX_RSS_IPV6_REG3(128bit): * IPv6 RSS Toeplitz hash key upper bytes and IPv6 RSS settings */ #define FR_CZ_RX_RSS_IPV6_REG3_OFST 0x000008f0 /* sienaa0=net_func_bar2 */ #define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_LBN 66 #define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_WIDTH 1 #define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_LBN 65 #define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_WIDTH 1 #define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_LBN 64 #define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_WIDTH 1 #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN 0 #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH 64 #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_LBN 0 #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_WIDTH 32 #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_LBN 32 #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_WIDTH 32 /* * FR_AZ_TX_FLUSH_DESCQ_REG(128bit): * Transmit flush descriptor queue register */ #define FR_AZ_TX_FLUSH_DESCQ_REG_OFST 0x00000a00 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_TX_FLUSH_DESCQ_CMD_LBN 12 #define FRF_AZ_TX_FLUSH_DESCQ_CMD_WIDTH 1 #define FRF_AZ_TX_FLUSH_DESCQ_LBN 0 #define FRF_AZ_TX_FLUSH_DESCQ_WIDTH 12 /* * FR_BZ_TX_DESC_UPD_REGP0(128bit): * Transmit descriptor update register. */ #define FR_BZ_TX_DESC_UPD_REGP0_OFST 0x00000a10 /* falconb0,sienaa0=net_func_bar2 */ #define FR_BZ_TX_DESC_UPD_REGP0_STEP 8192 #define FR_BZ_TX_DESC_UPD_REGP0_ROWS 1024 /* * FR_AA_TX_DESC_UPD_REG_KER(128bit): * Transmit descriptor update register. */ #define FR_AA_TX_DESC_UPD_REG_KER_OFST 0x00000a10 /* falcona0=net_func_bar2 */ #define FR_AA_TX_DESC_UPD_REG_KER_STEP 8192 #define FR_AA_TX_DESC_UPD_REG_KER_ROWS 8 /* * FR_AB_TX_DESC_UPD_REGP123(128bit): * Transmit descriptor update register. */ #define FR_AB_TX_DESC_UPD_REGP123_OFST 0x01000a10 /* falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FR_AB_TX_DESC_UPD_REGP123_STEP 8192 #define FR_AB_TX_DESC_UPD_REGP123_ROWS 3072 /* * FR_AA_TX_DESC_UPD_REGP0(128bit): * Transmit descriptor update register. */ #define FR_AA_TX_DESC_UPD_REGP0_OFST 0x00008a10 /* falcona0=char_func_bar0 */ #define FR_AA_TX_DESC_UPD_REGP0_STEP 8192 #define FR_AA_TX_DESC_UPD_REGP0_ROWS 1020 #define FRF_AZ_TX_DESC_WPTR_LBN 96 #define FRF_AZ_TX_DESC_WPTR_WIDTH 12 #define FRF_AZ_TX_DESC_PUSH_CMD_LBN 95 #define FRF_AZ_TX_DESC_PUSH_CMD_WIDTH 1 #define FRF_AZ_TX_DESC_LBN 0 #define FRF_AZ_TX_DESC_WIDTH 95 #define FRF_AZ_TX_DESC_DW0_LBN 0 #define FRF_AZ_TX_DESC_DW0_WIDTH 32 #define FRF_AZ_TX_DESC_DW1_LBN 32 #define FRF_AZ_TX_DESC_DW1_WIDTH 32 #define FRF_AZ_TX_DESC_DW2_LBN 64 #define FRF_AZ_TX_DESC_DW2_WIDTH 31 /* * FR_AZ_TX_DC_CFG_REG(128bit): * Transmit descriptor cache configuration register */ #define FR_AZ_TX_DC_CFG_REG_OFST 0x00000a20 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_TX_DC_SIZE_LBN 0 #define FRF_AZ_TX_DC_SIZE_WIDTH 2 #define FFE_AZ_TX_DC_SIZE_32 2 #define FFE_AZ_TX_DC_SIZE_16 1 #define FFE_AZ_TX_DC_SIZE_8 0 /* * FR_AA_TX_CHKSM_CFG_REG(128bit): * Transmit checksum configuration register */ #define FR_AA_TX_CHKSM_CFG_REG_OFST 0x00000a30 /* falcona0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AA_TX_Q_CHKSM_DIS_96_127_LBN 96 #define FRF_AA_TX_Q_CHKSM_DIS_96_127_WIDTH 32 #define FRF_AA_TX_Q_CHKSM_DIS_64_95_LBN 64 #define FRF_AA_TX_Q_CHKSM_DIS_64_95_WIDTH 32 #define FRF_AA_TX_Q_CHKSM_DIS_32_63_LBN 32 #define FRF_AA_TX_Q_CHKSM_DIS_32_63_WIDTH 32 #define FRF_AA_TX_Q_CHKSM_DIS_0_31_LBN 0 #define FRF_AA_TX_Q_CHKSM_DIS_0_31_WIDTH 32 /* * FR_AZ_TX_CFG_REG(128bit): * Transmit configuration register */ #define FR_AZ_TX_CFG_REG_OFST 0x00000a50 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_LBN 114 #define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_WIDTH 8 #define FRF_CZ_TX_FILTER_TEST_MODE_BIT_LBN 113 #define FRF_CZ_TX_FILTER_TEST_MODE_BIT_WIDTH 1 #define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_LBN 105 #define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_WIDTH 8 #define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_LBN 97 #define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_WIDTH 8 #define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_LBN 89 #define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8 #define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_LBN 81 #define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8 #define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_LBN 73 #define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8 #define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_LBN 65 #define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8 #define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_LBN 64 #define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_WIDTH 1 #define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_LBN 48 #define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_WIDTH 16 #define FRF_CZ_TX_FILTER_EN_BIT_LBN 47 #define FRF_CZ_TX_FILTER_EN_BIT_WIDTH 1 #define FRF_AZ_TX_IP_ID_P0_OFS_LBN 16 #define FRF_AZ_TX_IP_ID_P0_OFS_WIDTH 15 #define FRF_AZ_TX_NO_EOP_DISC_EN_LBN 5 #define FRF_AZ_TX_NO_EOP_DISC_EN_WIDTH 1 #define FRF_AZ_TX_P1_PRI_EN_LBN 4 #define FRF_AZ_TX_P1_PRI_EN_WIDTH 1 #define FRF_AZ_TX_OWNERR_CTL_LBN 2 #define FRF_AZ_TX_OWNERR_CTL_WIDTH 1 #define FRF_AA_TX_NON_IP_DROP_DIS_LBN 1 #define FRF_AA_TX_NON_IP_DROP_DIS_WIDTH 1 #define FRF_AZ_TX_IP_ID_REP_EN_LBN 0 #define FRF_AZ_TX_IP_ID_REP_EN_WIDTH 1 /* * FR_AZ_TX_PUSH_DROP_REG(128bit): * Transmit push dropped register */ #define FR_AZ_TX_PUSH_DROP_REG_OFST 0x00000a60 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_TX_PUSH_DROP_CNT_LBN 0 #define FRF_AZ_TX_PUSH_DROP_CNT_WIDTH 32 /* * FR_AZ_TX_RESERVED_REG(128bit): * Transmit configuration register */ #define FR_AZ_TX_RESERVED_REG_OFST 0x00000a80 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_TX_EVT_CNT_LBN 121 #define FRF_AZ_TX_EVT_CNT_WIDTH 7 #define FRF_AZ_TX_PREF_AGE_CNT_LBN 119 #define FRF_AZ_TX_PREF_AGE_CNT_WIDTH 2 #define FRF_AZ_TX_RD_COMP_TMR_LBN 96 #define FRF_AZ_TX_RD_COMP_TMR_WIDTH 23 #define FRF_AZ_TX_PUSH_EN_LBN 89 #define FRF_AZ_TX_PUSH_EN_WIDTH 1 #define FRF_AZ_TX_PUSH_CHK_DIS_LBN 88 #define FRF_AZ_TX_PUSH_CHK_DIS_WIDTH 1 #define FRF_AZ_TX_D_FF_FULL_P0_LBN 85 #define FRF_AZ_TX_D_FF_FULL_P0_WIDTH 1 #define FRF_AZ_TX_DMAR_ST_P0_LBN 81 #define FRF_AZ_TX_DMAR_ST_P0_WIDTH 1 #define FRF_AZ_TX_DMAQ_ST_LBN 78 #define FRF_AZ_TX_DMAQ_ST_WIDTH 1 #define FRF_AZ_TX_RX_SPACER_LBN 64 #define FRF_AZ_TX_RX_SPACER_WIDTH 8 #define FRF_AZ_TX_DROP_ABORT_EN_LBN 60 #define FRF_AZ_TX_DROP_ABORT_EN_WIDTH 1 #define FRF_AZ_TX_SOFT_EVT_EN_LBN 59 #define FRF_AZ_TX_SOFT_EVT_EN_WIDTH 1 #define FRF_AZ_TX_PS_EVT_DIS_LBN 58 #define FRF_AZ_TX_PS_EVT_DIS_WIDTH 1 #define FRF_AZ_TX_RX_SPACER_EN_LBN 57 #define FRF_AZ_TX_RX_SPACER_EN_WIDTH 1 #define FRF_AZ_TX_XP_TIMER_LBN 52 #define FRF_AZ_TX_XP_TIMER_WIDTH 5 #define FRF_AZ_TX_PREF_SPACER_LBN 44 #define FRF_AZ_TX_PREF_SPACER_WIDTH 8 #define FRF_AZ_TX_PREF_WD_TMR_LBN 22 #define FRF_AZ_TX_PREF_WD_TMR_WIDTH 22 #define FRF_AZ_TX_ONLY1TAG_LBN 21 #define FRF_AZ_TX_ONLY1TAG_WIDTH 1 #define FRF_AZ_TX_PREF_THRESHOLD_LBN 19 #define FRF_AZ_TX_PREF_THRESHOLD_WIDTH 2 #define FRF_AZ_TX_ONE_PKT_PER_Q_LBN 18 #define FRF_AZ_TX_ONE_PKT_PER_Q_WIDTH 1 #define FRF_AZ_TX_DIS_NON_IP_EV_LBN 17 #define FRF_AZ_TX_DIS_NON_IP_EV_WIDTH 1 #define FRF_AA_TX_DMA_FF_THR_LBN 16 #define FRF_AA_TX_DMA_FF_THR_WIDTH 1 #define FRF_AZ_TX_DMA_SPACER_LBN 8 #define FRF_AZ_TX_DMA_SPACER_WIDTH 8 #define FRF_AA_TX_TCP_DIS_LBN 7 #define FRF_AA_TX_TCP_DIS_WIDTH 1 #define FRF_BZ_TX_FLUSH_MIN_LEN_EN_LBN 7 #define FRF_BZ_TX_FLUSH_MIN_LEN_EN_WIDTH 1 #define FRF_AA_TX_IP_DIS_LBN 6 #define FRF_AA_TX_IP_DIS_WIDTH 1 #define FRF_AZ_TX_MAX_CPL_LBN 2 #define FRF_AZ_TX_MAX_CPL_WIDTH 2 #define FFE_AZ_TX_MAX_CPL_16 3 #define FFE_AZ_TX_MAX_CPL_8 2 #define FFE_AZ_TX_MAX_CPL_4 1 #define FFE_AZ_TX_MAX_CPL_NOLIMIT 0 #define FRF_AZ_TX_MAX_PREF_LBN 0 #define FRF_AZ_TX_MAX_PREF_WIDTH 2 #define FFE_AZ_TX_MAX_PREF_32 3 #define FFE_AZ_TX_MAX_PREF_16 2 #define FFE_AZ_TX_MAX_PREF_8 1 #define FFE_AZ_TX_MAX_PREF_OFF 0 /* * FR_BZ_TX_PACE_REG(128bit): * Transmit pace control register */ #define FR_BZ_TX_PACE_REG_OFST 0x00000a90 /* falconb0,sienaa0=net_func_bar2 */ /* * FR_AA_TX_PACE_REG(128bit): * Transmit pace control register */ #define FR_AA_TX_PACE_REG_OFST 0x00f80000 /* falcona0=char_func_bar0 */ #define FRF_AZ_TX_PACE_SB_NOT_AF_LBN 19 #define FRF_AZ_TX_PACE_SB_NOT_AF_WIDTH 10 #define FRF_AZ_TX_PACE_SB_AF_LBN 9 #define FRF_AZ_TX_PACE_SB_AF_WIDTH 10 #define FRF_AZ_TX_PACE_FB_BASE_LBN 5 #define FRF_AZ_TX_PACE_FB_BASE_WIDTH 4 #define FRF_AZ_TX_PACE_BIN_TH_LBN 0 #define FRF_AZ_TX_PACE_BIN_TH_WIDTH 5 /* * FR_AZ_TX_PACE_DROP_QID_REG(128bit): * PACE Drop QID Counter */ #define FR_AZ_TX_PACE_DROP_QID_REG_OFST 0x00000aa0 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_TX_PACE_QID_DRP_CNT_LBN 0 #define FRF_AZ_TX_PACE_QID_DRP_CNT_WIDTH 16 /* * FR_AB_TX_VLAN_REG(128bit): * Transmit VLAN tag register */ #define FR_AB_TX_VLAN_REG_OFST 0x00000ae0 /* falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_TX_VLAN_EN_LBN 127 #define FRF_AB_TX_VLAN_EN_WIDTH 1 #define FRF_AB_TX_VLAN7_PORT1_EN_LBN 125 #define FRF_AB_TX_VLAN7_PORT1_EN_WIDTH 1 #define FRF_AB_TX_VLAN7_PORT0_EN_LBN 124 #define FRF_AB_TX_VLAN7_PORT0_EN_WIDTH 1 #define FRF_AB_TX_VLAN7_LBN 112 #define FRF_AB_TX_VLAN7_WIDTH 12 #define FRF_AB_TX_VLAN6_PORT1_EN_LBN 109 #define FRF_AB_TX_VLAN6_PORT1_EN_WIDTH 1 #define FRF_AB_TX_VLAN6_PORT0_EN_LBN 108 #define FRF_AB_TX_VLAN6_PORT0_EN_WIDTH 1 #define FRF_AB_TX_VLAN6_LBN 96 #define FRF_AB_TX_VLAN6_WIDTH 12 #define FRF_AB_TX_VLAN5_PORT1_EN_LBN 93 #define FRF_AB_TX_VLAN5_PORT1_EN_WIDTH 1 #define FRF_AB_TX_VLAN5_PORT0_EN_LBN 92 #define FRF_AB_TX_VLAN5_PORT0_EN_WIDTH 1 #define FRF_AB_TX_VLAN5_LBN 80 #define FRF_AB_TX_VLAN5_WIDTH 12 #define FRF_AB_TX_VLAN4_PORT1_EN_LBN 77 #define FRF_AB_TX_VLAN4_PORT1_EN_WIDTH 1 #define FRF_AB_TX_VLAN4_PORT0_EN_LBN 76 #define FRF_AB_TX_VLAN4_PORT0_EN_WIDTH 1 #define FRF_AB_TX_VLAN4_LBN 64 #define FRF_AB_TX_VLAN4_WIDTH 12 #define FRF_AB_TX_VLAN3_PORT1_EN_LBN 61 #define FRF_AB_TX_VLAN3_PORT1_EN_WIDTH 1 #define FRF_AB_TX_VLAN3_PORT0_EN_LBN 60 #define FRF_AB_TX_VLAN3_PORT0_EN_WIDTH 1 #define FRF_AB_TX_VLAN3_LBN 48 #define FRF_AB_TX_VLAN3_WIDTH 12 #define FRF_AB_TX_VLAN2_PORT1_EN_LBN 45 #define FRF_AB_TX_VLAN2_PORT1_EN_WIDTH 1 #define FRF_AB_TX_VLAN2_PORT0_EN_LBN 44 #define FRF_AB_TX_VLAN2_PORT0_EN_WIDTH 1 #define FRF_AB_TX_VLAN2_LBN 32 #define FRF_AB_TX_VLAN2_WIDTH 12 #define FRF_AB_TX_VLAN1_PORT1_EN_LBN 29 #define FRF_AB_TX_VLAN1_PORT1_EN_WIDTH 1 #define FRF_AB_TX_VLAN1_PORT0_EN_LBN 28 #define FRF_AB_TX_VLAN1_PORT0_EN_WIDTH 1 #define FRF_AB_TX_VLAN1_LBN 16 #define FRF_AB_TX_VLAN1_WIDTH 12 #define FRF_AB_TX_VLAN0_PORT1_EN_LBN 13 #define FRF_AB_TX_VLAN0_PORT1_EN_WIDTH 1 #define FRF_AB_TX_VLAN0_PORT0_EN_LBN 12 #define FRF_AB_TX_VLAN0_PORT0_EN_WIDTH 1 #define FRF_AB_TX_VLAN0_LBN 0 #define FRF_AB_TX_VLAN0_WIDTH 12 /* * FR_AZ_TX_IPFIL_PORTEN_REG(128bit): * Transmit filter control register */ #define FR_AZ_TX_IPFIL_PORTEN_REG_OFST 0x00000af0 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AZ_TX_MADR0_FIL_EN_LBN 64 #define FRF_AZ_TX_MADR0_FIL_EN_WIDTH 1 #define FRF_AB_TX_IPFIL31_PORT_EN_LBN 62 #define FRF_AB_TX_IPFIL31_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL30_PORT_EN_LBN 60 #define FRF_AB_TX_IPFIL30_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL29_PORT_EN_LBN 58 #define FRF_AB_TX_IPFIL29_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL28_PORT_EN_LBN 56 #define FRF_AB_TX_IPFIL28_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL27_PORT_EN_LBN 54 #define FRF_AB_TX_IPFIL27_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL26_PORT_EN_LBN 52 #define FRF_AB_TX_IPFIL26_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL25_PORT_EN_LBN 50 #define FRF_AB_TX_IPFIL25_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL24_PORT_EN_LBN 48 #define FRF_AB_TX_IPFIL24_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL23_PORT_EN_LBN 46 #define FRF_AB_TX_IPFIL23_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL22_PORT_EN_LBN 44 #define FRF_AB_TX_IPFIL22_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL21_PORT_EN_LBN 42 #define FRF_AB_TX_IPFIL21_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL20_PORT_EN_LBN 40 #define FRF_AB_TX_IPFIL20_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL19_PORT_EN_LBN 38 #define FRF_AB_TX_IPFIL19_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL18_PORT_EN_LBN 36 #define FRF_AB_TX_IPFIL18_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL17_PORT_EN_LBN 34 #define FRF_AB_TX_IPFIL17_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL16_PORT_EN_LBN 32 #define FRF_AB_TX_IPFIL16_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL15_PORT_EN_LBN 30 #define FRF_AB_TX_IPFIL15_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL14_PORT_EN_LBN 28 #define FRF_AB_TX_IPFIL14_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL13_PORT_EN_LBN 26 #define FRF_AB_TX_IPFIL13_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL12_PORT_EN_LBN 24 #define FRF_AB_TX_IPFIL12_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL11_PORT_EN_LBN 22 #define FRF_AB_TX_IPFIL11_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL10_PORT_EN_LBN 20 #define FRF_AB_TX_IPFIL10_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL9_PORT_EN_LBN 18 #define FRF_AB_TX_IPFIL9_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL8_PORT_EN_LBN 16 #define FRF_AB_TX_IPFIL8_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL7_PORT_EN_LBN 14 #define FRF_AB_TX_IPFIL7_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL6_PORT_EN_LBN 12 #define FRF_AB_TX_IPFIL6_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL5_PORT_EN_LBN 10 #define FRF_AB_TX_IPFIL5_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL4_PORT_EN_LBN 8 #define FRF_AB_TX_IPFIL4_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL3_PORT_EN_LBN 6 #define FRF_AB_TX_IPFIL3_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL2_PORT_EN_LBN 4 #define FRF_AB_TX_IPFIL2_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL1_PORT_EN_LBN 2 #define FRF_AB_TX_IPFIL1_PORT_EN_WIDTH 1 #define FRF_AB_TX_IPFIL0_PORT_EN_LBN 0 #define FRF_AB_TX_IPFIL0_PORT_EN_WIDTH 1 /* * FR_AB_TX_IPFIL_TBL(128bit): * Transmit IP source address filter table */ #define FR_AB_TX_IPFIL_TBL_OFST 0x00000b00 /* falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FR_AB_TX_IPFIL_TBL_STEP 16 #define FR_AB_TX_IPFIL_TBL_ROWS 16 #define FRF_AB_TX_IPFIL_MASK_1_LBN 96 #define FRF_AB_TX_IPFIL_MASK_1_WIDTH 32 #define FRF_AB_TX_IP_SRC_ADR_1_LBN 64 #define FRF_AB_TX_IP_SRC_ADR_1_WIDTH 32 #define FRF_AB_TX_IPFIL_MASK_0_LBN 32 #define FRF_AB_TX_IPFIL_MASK_0_WIDTH 32 #define FRF_AB_TX_IP_SRC_ADR_0_LBN 0 #define FRF_AB_TX_IP_SRC_ADR_0_WIDTH 32 /* * FR_AB_MD_TXD_REG(128bit): * PHY management transmit data register */ #define FR_AB_MD_TXD_REG_OFST 0x00000c00 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_MD_TXD_LBN 0 #define FRF_AB_MD_TXD_WIDTH 16 /* * FR_AB_MD_RXD_REG(128bit): * PHY management receive data register */ #define FR_AB_MD_RXD_REG_OFST 0x00000c10 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_MD_RXD_LBN 0 #define FRF_AB_MD_RXD_WIDTH 16 /* * FR_AB_MD_CS_REG(128bit): * PHY management configuration & status register */ #define FR_AB_MD_CS_REG_OFST 0x00000c20 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_MD_RD_EN_LBN 15 #define FRF_AB_MD_RD_EN_WIDTH 1 #define FRF_AB_MD_WR_EN_LBN 14 #define FRF_AB_MD_WR_EN_WIDTH 1 #define FRF_AB_MD_ADDR_CMD_LBN 13 #define FRF_AB_MD_ADDR_CMD_WIDTH 1 #define FRF_AB_MD_PT_LBN 7 #define FRF_AB_MD_PT_WIDTH 3 #define FRF_AB_MD_PL_LBN 6 #define FRF_AB_MD_PL_WIDTH 1 #define FRF_AB_MD_INT_CLR_LBN 5 #define FRF_AB_MD_INT_CLR_WIDTH 1 #define FRF_AB_MD_GC_LBN 4 #define FRF_AB_MD_GC_WIDTH 1 #define FRF_AB_MD_PRSP_LBN 3 #define FRF_AB_MD_PRSP_WIDTH 1 #define FRF_AB_MD_RIC_LBN 2 #define FRF_AB_MD_RIC_WIDTH 1 #define FRF_AB_MD_RDC_LBN 1 #define FRF_AB_MD_RDC_WIDTH 1 #define FRF_AB_MD_WRC_LBN 0 #define FRF_AB_MD_WRC_WIDTH 1 /* * FR_AB_MD_PHY_ADR_REG(128bit): * PHY management PHY address register */ #define FR_AB_MD_PHY_ADR_REG_OFST 0x00000c30 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_MD_PHY_ADR_LBN 0 #define FRF_AB_MD_PHY_ADR_WIDTH 16 /* * FR_AB_MD_ID_REG(128bit): * PHY management ID register */ #define FR_AB_MD_ID_REG_OFST 0x00000c40 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_MD_PRT_ADR_LBN 11 #define FRF_AB_MD_PRT_ADR_WIDTH 5 #define FRF_AB_MD_DEV_ADR_LBN 6 #define FRF_AB_MD_DEV_ADR_WIDTH 5 /* * FR_AB_MD_STAT_REG(128bit): * PHY management status & mask register */ #define FR_AB_MD_STAT_REG_OFST 0x00000c50 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_MD_PINT_LBN 4 #define FRF_AB_MD_PINT_WIDTH 1 #define FRF_AB_MD_DONE_LBN 3 #define FRF_AB_MD_DONE_WIDTH 1 #define FRF_AB_MD_BSERR_LBN 2 #define FRF_AB_MD_BSERR_WIDTH 1 #define FRF_AB_MD_LNFL_LBN 1 #define FRF_AB_MD_LNFL_WIDTH 1 #define FRF_AB_MD_BSY_LBN 0 #define FRF_AB_MD_BSY_WIDTH 1 /* * FR_AB_MAC_STAT_DMA_REG(128bit): * Port MAC statistical counter DMA register */ #define FR_AB_MAC_STAT_DMA_REG_OFST 0x00000c60 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_MAC_STAT_DMA_CMD_LBN 48 #define FRF_AB_MAC_STAT_DMA_CMD_WIDTH 1 #define FRF_AB_MAC_STAT_DMA_ADR_LBN 0 #define FRF_AB_MAC_STAT_DMA_ADR_WIDTH 48 #define FRF_AB_MAC_STAT_DMA_ADR_DW0_LBN 0 #define FRF_AB_MAC_STAT_DMA_ADR_DW0_WIDTH 32 #define FRF_AB_MAC_STAT_DMA_ADR_DW1_LBN 32 #define FRF_AB_MAC_STAT_DMA_ADR_DW1_WIDTH 16 /* * FR_AB_MAC_CTRL_REG(128bit): * Port MAC control register */ #define FR_AB_MAC_CTRL_REG_OFST 0x00000c80 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_MAC_XOFF_VAL_LBN 16 #define FRF_AB_MAC_XOFF_VAL_WIDTH 16 #define FRF_BB_TXFIFO_DRAIN_EN_LBN 7 #define FRF_BB_TXFIFO_DRAIN_EN_WIDTH 1 #define FRF_AB_MAC_XG_DISTXCRC_LBN 5 #define FRF_AB_MAC_XG_DISTXCRC_WIDTH 1 #define FRF_AB_MAC_BCAD_ACPT_LBN 4 #define FRF_AB_MAC_BCAD_ACPT_WIDTH 1 #define FRF_AB_MAC_UC_PROM_LBN 3 #define FRF_AB_MAC_UC_PROM_WIDTH 1 #define FRF_AB_MAC_LINK_STATUS_LBN 2 #define FRF_AB_MAC_LINK_STATUS_WIDTH 1 #define FRF_AB_MAC_SPEED_LBN 0 #define FRF_AB_MAC_SPEED_WIDTH 2 #define FRF_AB_MAC_SPEED_10M 0 #define FRF_AB_MAC_SPEED_100M 1 #define FRF_AB_MAC_SPEED_1G 2 #define FRF_AB_MAC_SPEED_10G 3 /* * FR_BB_GEN_MODE_REG(128bit): * General Purpose mode register (external interrupt mask) */ #define FR_BB_GEN_MODE_REG_OFST 0x00000c90 /* falconb0=net_func_bar2 */ #define FRF_BB_XFP_PHY_INT_POL_SEL_LBN 3 #define FRF_BB_XFP_PHY_INT_POL_SEL_WIDTH 1 #define FRF_BB_XG_PHY_INT_POL_SEL_LBN 2 #define FRF_BB_XG_PHY_INT_POL_SEL_WIDTH 1 #define FRF_BB_XFP_PHY_INT_MASK_LBN 1 #define FRF_BB_XFP_PHY_INT_MASK_WIDTH 1 #define FRF_BB_XG_PHY_INT_MASK_LBN 0 #define FRF_BB_XG_PHY_INT_MASK_WIDTH 1 /* * FR_AB_MAC_MC_HASH_REG0(128bit): * Multicast address hash table */ #define FR_AB_MAC_MC_HASH0_REG_OFST 0x00000ca0 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_MAC_MCAST_HASH0_LBN 0 #define FRF_AB_MAC_MCAST_HASH0_WIDTH 128 #define FRF_AB_MAC_MCAST_HASH0_DW0_LBN 0 #define FRF_AB_MAC_MCAST_HASH0_DW0_WIDTH 32 #define FRF_AB_MAC_MCAST_HASH0_DW1_LBN 32 #define FRF_AB_MAC_MCAST_HASH0_DW1_WIDTH 32 #define FRF_AB_MAC_MCAST_HASH0_DW2_LBN 64 #define FRF_AB_MAC_MCAST_HASH0_DW2_WIDTH 32 #define FRF_AB_MAC_MCAST_HASH0_DW3_LBN 96 #define FRF_AB_MAC_MCAST_HASH0_DW3_WIDTH 32 /* * FR_AB_MAC_MC_HASH_REG1(128bit): * Multicast address hash table */ #define FR_AB_MAC_MC_HASH1_REG_OFST 0x00000cb0 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_MAC_MCAST_HASH1_LBN 0 #define FRF_AB_MAC_MCAST_HASH1_WIDTH 128 #define FRF_AB_MAC_MCAST_HASH1_DW0_LBN 0 #define FRF_AB_MAC_MCAST_HASH1_DW0_WIDTH 32 #define FRF_AB_MAC_MCAST_HASH1_DW1_LBN 32 #define FRF_AB_MAC_MCAST_HASH1_DW1_WIDTH 32 #define FRF_AB_MAC_MCAST_HASH1_DW2_LBN 64 #define FRF_AB_MAC_MCAST_HASH1_DW2_WIDTH 32 #define FRF_AB_MAC_MCAST_HASH1_DW3_LBN 96 #define FRF_AB_MAC_MCAST_HASH1_DW3_WIDTH 32 /* * FR_AB_GM_CFG1_REG(32bit): * GMAC configuration register 1 */ #define FR_AB_GM_CFG1_REG_OFST 0x00000e00 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_GM_SW_RST_LBN 31 #define FRF_AB_GM_SW_RST_WIDTH 1 #define FRF_AB_GM_SIM_RST_LBN 30 #define FRF_AB_GM_SIM_RST_WIDTH 1 #define FRF_AB_GM_RST_RX_MAC_CTL_LBN 19 #define FRF_AB_GM_RST_RX_MAC_CTL_WIDTH 1 #define FRF_AB_GM_RST_TX_MAC_CTL_LBN 18 #define FRF_AB_GM_RST_TX_MAC_CTL_WIDTH 1 #define FRF_AB_GM_RST_RX_FUNC_LBN 17 #define FRF_AB_GM_RST_RX_FUNC_WIDTH 1 #define FRF_AB_GM_RST_TX_FUNC_LBN 16 #define FRF_AB_GM_RST_TX_FUNC_WIDTH 1 #define FRF_AB_GM_LOOP_LBN 8 #define FRF_AB_GM_LOOP_WIDTH 1 #define FRF_AB_GM_RX_FC_EN_LBN 5 #define FRF_AB_GM_RX_FC_EN_WIDTH 1 #define FRF_AB_GM_TX_FC_EN_LBN 4 #define FRF_AB_GM_TX_FC_EN_WIDTH 1 #define FRF_AB_GM_SYNC_RXEN_LBN 3 #define FRF_AB_GM_SYNC_RXEN_WIDTH 1 #define FRF_AB_GM_RX_EN_LBN 2 #define FRF_AB_GM_RX_EN_WIDTH 1 #define FRF_AB_GM_SYNC_TXEN_LBN 1 #define FRF_AB_GM_SYNC_TXEN_WIDTH 1 #define FRF_AB_GM_TX_EN_LBN 0 #define FRF_AB_GM_TX_EN_WIDTH 1 /* * FR_AB_GM_CFG2_REG(32bit): * GMAC configuration register 2 */ #define FR_AB_GM_CFG2_REG_OFST 0x00000e10 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_GM_PAMBL_LEN_LBN 12 #define FRF_AB_GM_PAMBL_LEN_WIDTH 4 #define FRF_AB_GM_IF_MODE_LBN 8 #define FRF_AB_GM_IF_MODE_WIDTH 2 #define FRF_AB_GM_IF_MODE_BYTE_MODE 2 #define FRF_AB_GM_IF_MODE_NIBBLE_MODE 1 #define FRF_AB_GM_HUGE_FRM_EN_LBN 5 #define FRF_AB_GM_HUGE_FRM_EN_WIDTH 1 #define FRF_AB_GM_LEN_CHK_LBN 4 #define FRF_AB_GM_LEN_CHK_WIDTH 1 #define FRF_AB_GM_PAD_CRC_EN_LBN 2 #define FRF_AB_GM_PAD_CRC_EN_WIDTH 1 #define FRF_AB_GM_CRC_EN_LBN 1 #define FRF_AB_GM_CRC_EN_WIDTH 1 #define FRF_AB_GM_FD_LBN 0 #define FRF_AB_GM_FD_WIDTH 1 /* * FR_AB_GM_IPG_REG(32bit): * GMAC IPG register */ #define FR_AB_GM_IPG_REG_OFST 0x00000e20 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_GM_NONB2B_IPG1_LBN 24 #define FRF_AB_GM_NONB2B_IPG1_WIDTH 7 #define FRF_AB_GM_NONB2B_IPG2_LBN 16 #define FRF_AB_GM_NONB2B_IPG2_WIDTH 7 #define FRF_AB_GM_MIN_IPG_ENF_LBN 8 #define FRF_AB_GM_MIN_IPG_ENF_WIDTH 8 #define FRF_AB_GM_B2B_IPG_LBN 0 #define FRF_AB_GM_B2B_IPG_WIDTH 7 /* * FR_AB_GM_HD_REG(32bit): * GMAC half duplex register */ #define FR_AB_GM_HD_REG_OFST 0x00000e30 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_GM_ALT_BOFF_VAL_LBN 20 #define FRF_AB_GM_ALT_BOFF_VAL_WIDTH 4 #define FRF_AB_GM_ALT_BOFF_EN_LBN 19 #define FRF_AB_GM_ALT_BOFF_EN_WIDTH 1 #define FRF_AB_GM_BP_NO_BOFF_LBN 18 #define FRF_AB_GM_BP_NO_BOFF_WIDTH 1 #define FRF_AB_GM_DIS_BOFF_LBN 17 #define FRF_AB_GM_DIS_BOFF_WIDTH 1 #define FRF_AB_GM_EXDEF_TX_EN_LBN 16 #define FRF_AB_GM_EXDEF_TX_EN_WIDTH 1 #define FRF_AB_GM_RTRY_LIMIT_LBN 12 #define FRF_AB_GM_RTRY_LIMIT_WIDTH 4 #define FRF_AB_GM_COL_WIN_LBN 0 #define FRF_AB_GM_COL_WIN_WIDTH 10 /* * FR_AB_GM_MAX_FLEN_REG(32bit): * GMAC maximum frame length register */ #define FR_AB_GM_MAX_FLEN_REG_OFST 0x00000e40 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_GM_MAX_FLEN_LBN 0 #define FRF_AB_GM_MAX_FLEN_WIDTH 16 /* * FR_AB_GM_TEST_REG(32bit): * GMAC test register */ #define FR_AB_GM_TEST_REG_OFST 0x00000e70 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_GM_MAX_BOFF_LBN 3 #define FRF_AB_GM_MAX_BOFF_WIDTH 1 #define FRF_AB_GM_REG_TX_FLOW_EN_LBN 2 #define FRF_AB_GM_REG_TX_FLOW_EN_WIDTH 1 #define FRF_AB_GM_TEST_PAUSE_LBN 1 #define FRF_AB_GM_TEST_PAUSE_WIDTH 1 #define FRF_AB_GM_SHORT_SLOT_LBN 0 #define FRF_AB_GM_SHORT_SLOT_WIDTH 1 /* * FR_AB_GM_ADR1_REG(32bit): * GMAC station address register 1 */ #define FR_AB_GM_ADR1_REG_OFST 0x00000f00 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_GM_ADR_B0_LBN 24 #define FRF_AB_GM_ADR_B0_WIDTH 8 #define FRF_AB_GM_ADR_B1_LBN 16 #define FRF_AB_GM_ADR_B1_WIDTH 8 #define FRF_AB_GM_ADR_B2_LBN 8 #define FRF_AB_GM_ADR_B2_WIDTH 8 #define FRF_AB_GM_ADR_B3_LBN 0 #define FRF_AB_GM_ADR_B3_WIDTH 8 /* * FR_AB_GM_ADR2_REG(32bit): * GMAC station address register 2 */ #define FR_AB_GM_ADR2_REG_OFST 0x00000f10 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_GM_ADR_B4_LBN 24 #define FRF_AB_GM_ADR_B4_WIDTH 8 #define FRF_AB_GM_ADR_B5_LBN 16 #define FRF_AB_GM_ADR_B5_WIDTH 8 /* * FR_AB_GMF_CFG0_REG(32bit): * GMAC FIFO configuration register 0 */ #define FR_AB_GMF_CFG0_REG_OFST 0x00000f20 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_GMF_FTFENRPLY_LBN 20 #define FRF_AB_GMF_FTFENRPLY_WIDTH 1 #define FRF_AB_GMF_STFENRPLY_LBN 19 #define FRF_AB_GMF_STFENRPLY_WIDTH 1 #define FRF_AB_GMF_FRFENRPLY_LBN 18 #define FRF_AB_GMF_FRFENRPLY_WIDTH 1 #define FRF_AB_GMF_SRFENRPLY_LBN 17 #define FRF_AB_GMF_SRFENRPLY_WIDTH 1 #define FRF_AB_GMF_WTMENRPLY_LBN 16 #define FRF_AB_GMF_WTMENRPLY_WIDTH 1 #define FRF_AB_GMF_FTFENREQ_LBN 12 #define FRF_AB_GMF_FTFENREQ_WIDTH 1 #define FRF_AB_GMF_STFENREQ_LBN 11 #define FRF_AB_GMF_STFENREQ_WIDTH 1 #define FRF_AB_GMF_FRFENREQ_LBN 10 #define FRF_AB_GMF_FRFENREQ_WIDTH 1 #define FRF_AB_GMF_SRFENREQ_LBN 9 #define FRF_AB_GMF_SRFENREQ_WIDTH 1 #define FRF_AB_GMF_WTMENREQ_LBN 8 #define FRF_AB_GMF_WTMENREQ_WIDTH 1 #define FRF_AB_GMF_HSTRSTFT_LBN 4 #define FRF_AB_GMF_HSTRSTFT_WIDTH 1 #define FRF_AB_GMF_HSTRSTST_LBN 3 #define FRF_AB_GMF_HSTRSTST_WIDTH 1 #define FRF_AB_GMF_HSTRSTFR_LBN 2 #define FRF_AB_GMF_HSTRSTFR_WIDTH 1 #define FRF_AB_GMF_HSTRSTSR_LBN 1 #define FRF_AB_GMF_HSTRSTSR_WIDTH 1 #define FRF_AB_GMF_HSTRSTWT_LBN 0 #define FRF_AB_GMF_HSTRSTWT_WIDTH 1 /* * FR_AB_GMF_CFG1_REG(32bit): * GMAC FIFO configuration register 1 */ #define FR_AB_GMF_CFG1_REG_OFST 0x00000f30 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_GMF_CFGFRTH_LBN 16 #define FRF_AB_GMF_CFGFRTH_WIDTH 5 #define FRF_AB_GMF_CFGXOFFRTX_LBN 0 #define FRF_AB_GMF_CFGXOFFRTX_WIDTH 16 /* * FR_AB_GMF_CFG2_REG(32bit): * GMAC FIFO configuration register 2 */ #define FR_AB_GMF_CFG2_REG_OFST 0x00000f40 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_GMF_CFGHWM_LBN 16 #define FRF_AB_GMF_CFGHWM_WIDTH 6 #define FRF_AB_GMF_CFGLWM_LBN 0 #define FRF_AB_GMF_CFGLWM_WIDTH 6 /* * FR_AB_GMF_CFG3_REG(32bit): * GMAC FIFO configuration register 3 */ #define FR_AB_GMF_CFG3_REG_OFST 0x00000f50 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_GMF_CFGHWMFT_LBN 16 #define FRF_AB_GMF_CFGHWMFT_WIDTH 6 #define FRF_AB_GMF_CFGFTTH_LBN 0 #define FRF_AB_GMF_CFGFTTH_WIDTH 6 /* * FR_AB_GMF_CFG4_REG(32bit): * GMAC FIFO configuration register 4 */ #define FR_AB_GMF_CFG4_REG_OFST 0x00000f60 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_GMF_HSTFLTRFRM_LBN 0 #define FRF_AB_GMF_HSTFLTRFRM_WIDTH 18 /* * FR_AB_GMF_CFG5_REG(32bit): * GMAC FIFO configuration register 5 */ #define FR_AB_GMF_CFG5_REG_OFST 0x00000f70 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_GMF_CFGHDPLX_LBN 22 #define FRF_AB_GMF_CFGHDPLX_WIDTH 1 #define FRF_AB_GMF_SRFULL_LBN 21 #define FRF_AB_GMF_SRFULL_WIDTH 1 #define FRF_AB_GMF_HSTSRFULLCLR_LBN 20 #define FRF_AB_GMF_HSTSRFULLCLR_WIDTH 1 #define FRF_AB_GMF_CFGBYTMODE_LBN 19 #define FRF_AB_GMF_CFGBYTMODE_WIDTH 1 #define FRF_AB_GMF_HSTDRPLT64_LBN 18 #define FRF_AB_GMF_HSTDRPLT64_WIDTH 1 #define FRF_AB_GMF_HSTFLTRFRMDC_LBN 0 #define FRF_AB_GMF_HSTFLTRFRMDC_WIDTH 18 /* * FR_BB_TX_SRC_MAC_TBL(128bit): * Transmit IP source address filter table */ #define FR_BB_TX_SRC_MAC_TBL_OFST 0x00001000 /* falconb0=net_func_bar2 */ #define FR_BB_TX_SRC_MAC_TBL_STEP 16 #define FR_BB_TX_SRC_MAC_TBL_ROWS 16 #define FRF_BB_TX_SRC_MAC_ADR_1_LBN 64 #define FRF_BB_TX_SRC_MAC_ADR_1_WIDTH 48 #define FRF_BB_TX_SRC_MAC_ADR_1_DW0_LBN 64 #define FRF_BB_TX_SRC_MAC_ADR_1_DW0_WIDTH 32 #define FRF_BB_TX_SRC_MAC_ADR_1_DW1_LBN 96 #define FRF_BB_TX_SRC_MAC_ADR_1_DW1_WIDTH 16 #define FRF_BB_TX_SRC_MAC_ADR_0_LBN 0 #define FRF_BB_TX_SRC_MAC_ADR_0_WIDTH 48 #define FRF_BB_TX_SRC_MAC_ADR_0_DW0_LBN 0 #define FRF_BB_TX_SRC_MAC_ADR_0_DW0_WIDTH 32 #define FRF_BB_TX_SRC_MAC_ADR_0_DW1_LBN 32 #define FRF_BB_TX_SRC_MAC_ADR_0_DW1_WIDTH 16 /* * FR_BB_TX_SRC_MAC_CTL_REG(128bit): * Transmit MAC source address filter control */ #define FR_BB_TX_SRC_MAC_CTL_REG_OFST 0x00001100 /* falconb0=net_func_bar2 */ #define FRF_BB_TX_SRC_DROP_CTR_LBN 16 #define FRF_BB_TX_SRC_DROP_CTR_WIDTH 16 #define FRF_BB_TX_SRC_FLTR_EN_LBN 15 #define FRF_BB_TX_SRC_FLTR_EN_WIDTH 1 #define FRF_BB_TX_DROP_CTR_CLR_LBN 12 #define FRF_BB_TX_DROP_CTR_CLR_WIDTH 1 #define FRF_BB_TX_MAC_QID_SEL_LBN 0 #define FRF_BB_TX_MAC_QID_SEL_WIDTH 3 /* * FR_AB_XM_ADR_LO_REG(128bit): * XGMAC address register low */ #define FR_AB_XM_ADR_LO_REG_OFST 0x00001200 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_XM_ADR_LO_LBN 0 #define FRF_AB_XM_ADR_LO_WIDTH 32 /* * FR_AB_XM_ADR_HI_REG(128bit): * XGMAC address register high */ #define FR_AB_XM_ADR_HI_REG_OFST 0x00001210 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_XM_ADR_HI_LBN 0 #define FRF_AB_XM_ADR_HI_WIDTH 16 /* * FR_AB_XM_GLB_CFG_REG(128bit): * XGMAC global configuration */ #define FR_AB_XM_GLB_CFG_REG_OFST 0x00001220 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_XM_RMTFLT_GEN_LBN 17 #define FRF_AB_XM_RMTFLT_GEN_WIDTH 1 #define FRF_AB_XM_DEBUG_MODE_LBN 16 #define FRF_AB_XM_DEBUG_MODE_WIDTH 1 #define FRF_AB_XM_RX_STAT_EN_LBN 11 #define FRF_AB_XM_RX_STAT_EN_WIDTH 1 #define FRF_AB_XM_TX_STAT_EN_LBN 10 #define FRF_AB_XM_TX_STAT_EN_WIDTH 1 #define FRF_AB_XM_RX_JUMBO_MODE_LBN 6 #define FRF_AB_XM_RX_JUMBO_MODE_WIDTH 1 #define FRF_AB_XM_WAN_MODE_LBN 5 #define FRF_AB_XM_WAN_MODE_WIDTH 1 #define FRF_AB_XM_INTCLR_MODE_LBN 3 #define FRF_AB_XM_INTCLR_MODE_WIDTH 1 #define FRF_AB_XM_CORE_RST_LBN 0 #define FRF_AB_XM_CORE_RST_WIDTH 1 /* * FR_AB_XM_TX_CFG_REG(128bit): * XGMAC transmit configuration */ #define FR_AB_XM_TX_CFG_REG_OFST 0x00001230 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_XM_TX_PROG_LBN 24 #define FRF_AB_XM_TX_PROG_WIDTH 1 #define FRF_AB_XM_IPG_LBN 16 #define FRF_AB_XM_IPG_WIDTH 4 #define FRF_AB_XM_FCNTL_LBN 10 #define FRF_AB_XM_FCNTL_WIDTH 1 #define FRF_AB_XM_TXCRC_LBN 8 #define FRF_AB_XM_TXCRC_WIDTH 1 #define FRF_AB_XM_EDRC_LBN 6 #define FRF_AB_XM_EDRC_WIDTH 1 #define FRF_AB_XM_AUTO_PAD_LBN 5 #define FRF_AB_XM_AUTO_PAD_WIDTH 1 #define FRF_AB_XM_TX_PRMBL_LBN 2 #define FRF_AB_XM_TX_PRMBL_WIDTH 1 #define FRF_AB_XM_TXEN_LBN 1 #define FRF_AB_XM_TXEN_WIDTH 1 #define FRF_AB_XM_TX_RST_LBN 0 #define FRF_AB_XM_TX_RST_WIDTH 1 /* * FR_AB_XM_RX_CFG_REG(128bit): * XGMAC receive configuration */ #define FR_AB_XM_RX_CFG_REG_OFST 0x00001240 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_XM_PASS_LENERR_LBN 26 #define FRF_AB_XM_PASS_LENERR_WIDTH 1 #define FRF_AB_XM_PASS_CRC_ERR_LBN 25 #define FRF_AB_XM_PASS_CRC_ERR_WIDTH 1 #define FRF_AB_XM_PASS_PRMBLE_ERR_LBN 24 #define FRF_AB_XM_PASS_PRMBLE_ERR_WIDTH 1 #define FRF_AB_XM_REJ_BCAST_LBN 20 #define FRF_AB_XM_REJ_BCAST_WIDTH 1 #define FRF_AB_XM_ACPT_ALL_MCAST_LBN 11 #define FRF_AB_XM_ACPT_ALL_MCAST_WIDTH 1 #define FRF_AB_XM_ACPT_ALL_UCAST_LBN 9 #define FRF_AB_XM_ACPT_ALL_UCAST_WIDTH 1 #define FRF_AB_XM_AUTO_DEPAD_LBN 8 #define FRF_AB_XM_AUTO_DEPAD_WIDTH 1 #define FRF_AB_XM_RXCRC_LBN 3 #define FRF_AB_XM_RXCRC_WIDTH 1 #define FRF_AB_XM_RX_PRMBL_LBN 2 #define FRF_AB_XM_RX_PRMBL_WIDTH 1 #define FRF_AB_XM_RXEN_LBN 1 #define FRF_AB_XM_RXEN_WIDTH 1 #define FRF_AB_XM_RX_RST_LBN 0 #define FRF_AB_XM_RX_RST_WIDTH 1 /* * FR_AB_XM_MGT_INT_MASK(128bit): * documentation to be written for sum_XM_MGT_INT_MASK */ #define FR_AB_XM_MGT_INT_MASK_OFST 0x00001250 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_XM_MSK_STA_INTR_LBN 16 #define FRF_AB_XM_MSK_STA_INTR_WIDTH 1 #define FRF_AB_XM_MSK_STAT_CNTR_HF_LBN 9 #define FRF_AB_XM_MSK_STAT_CNTR_HF_WIDTH 1 #define FRF_AB_XM_MSK_STAT_CNTR_OF_LBN 8 #define FRF_AB_XM_MSK_STAT_CNTR_OF_WIDTH 1 #define FRF_AB_XM_MSK_PRMBLE_ERR_LBN 2 #define FRF_AB_XM_MSK_PRMBLE_ERR_WIDTH 1 #define FRF_AB_XM_MSK_RMTFLT_LBN 1 #define FRF_AB_XM_MSK_RMTFLT_WIDTH 1 #define FRF_AB_XM_MSK_LCLFLT_LBN 0 #define FRF_AB_XM_MSK_LCLFLT_WIDTH 1 /* * FR_AB_XM_FC_REG(128bit): * XGMAC flow control register */ #define FR_AB_XM_FC_REG_OFST 0x00001270 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_XM_PAUSE_TIME_LBN 16 #define FRF_AB_XM_PAUSE_TIME_WIDTH 16 #define FRF_AB_XM_RX_MAC_STAT_LBN 11 #define FRF_AB_XM_RX_MAC_STAT_WIDTH 1 #define FRF_AB_XM_TX_MAC_STAT_LBN 10 #define FRF_AB_XM_TX_MAC_STAT_WIDTH 1 #define FRF_AB_XM_MCNTL_PASS_LBN 8 #define FRF_AB_XM_MCNTL_PASS_WIDTH 2 #define FRF_AB_XM_REJ_CNTL_UCAST_LBN 6 #define FRF_AB_XM_REJ_CNTL_UCAST_WIDTH 1 #define FRF_AB_XM_REJ_CNTL_MCAST_LBN 5 #define FRF_AB_XM_REJ_CNTL_MCAST_WIDTH 1 #define FRF_AB_XM_ZPAUSE_LBN 2 #define FRF_AB_XM_ZPAUSE_WIDTH 1 #define FRF_AB_XM_XMIT_PAUSE_LBN 1 #define FRF_AB_XM_XMIT_PAUSE_WIDTH 1 #define FRF_AB_XM_DIS_FCNTL_LBN 0 #define FRF_AB_XM_DIS_FCNTL_WIDTH 1 /* * FR_AB_XM_PAUSE_TIME_REG(128bit): * XGMAC pause time register */ #define FR_AB_XM_PAUSE_TIME_REG_OFST 0x00001290 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_XM_TX_PAUSE_CNT_LBN 16 #define FRF_AB_XM_TX_PAUSE_CNT_WIDTH 16 #define FRF_AB_XM_RX_PAUSE_CNT_LBN 0 #define FRF_AB_XM_RX_PAUSE_CNT_WIDTH 16 /* * FR_AB_XM_TX_PARAM_REG(128bit): * XGMAC transmit parameter register */ #define FR_AB_XM_TX_PARAM_REG_OFST 0x000012d0 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_XM_TX_JUMBO_MODE_LBN 31 #define FRF_AB_XM_TX_JUMBO_MODE_WIDTH 1 #define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_LBN 19 #define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH 11 #define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN 16 #define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH 3 #define FRF_AB_XM_PAD_CHAR_LBN 0 #define FRF_AB_XM_PAD_CHAR_WIDTH 8 /* * FR_AB_XM_RX_PARAM_REG(128bit): * XGMAC receive parameter register */ #define FR_AB_XM_RX_PARAM_REG_OFST 0x000012e0 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_LBN 3 #define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH 11 #define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN 0 #define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH 3 /* * FR_AB_XM_MGT_INT_MSK_REG(128bit): * XGMAC management interrupt mask register */ #define FR_AB_XM_MGT_INT_REG_OFST 0x000012f0 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_XM_STAT_CNTR_OF_LBN 9 #define FRF_AB_XM_STAT_CNTR_OF_WIDTH 1 #define FRF_AB_XM_STAT_CNTR_HF_LBN 8 #define FRF_AB_XM_STAT_CNTR_HF_WIDTH 1 #define FRF_AB_XM_PRMBLE_ERR_LBN 2 #define FRF_AB_XM_PRMBLE_ERR_WIDTH 1 #define FRF_AB_XM_RMTFLT_LBN 1 #define FRF_AB_XM_RMTFLT_WIDTH 1 #define FRF_AB_XM_LCLFLT_LBN 0 #define FRF_AB_XM_LCLFLT_WIDTH 1 /* * FR_AB_XX_PWR_RST_REG(128bit): * XGXS/XAUI powerdown/reset register */ #define FR_AB_XX_PWR_RST_REG_OFST 0x00001300 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_XX_PWRDND_SIG_LBN 31 #define FRF_AB_XX_PWRDND_SIG_WIDTH 1 #define FRF_AB_XX_PWRDNC_SIG_LBN 30 #define FRF_AB_XX_PWRDNC_SIG_WIDTH 1 #define FRF_AB_XX_PWRDNB_SIG_LBN 29 #define FRF_AB_XX_PWRDNB_SIG_WIDTH 1 #define FRF_AB_XX_PWRDNA_SIG_LBN 28 #define FRF_AB_XX_PWRDNA_SIG_WIDTH 1 #define FRF_AB_XX_SIM_MODE_LBN 27 #define FRF_AB_XX_SIM_MODE_WIDTH 1 #define FRF_AB_XX_RSTPLLCD_SIG_LBN 25 #define FRF_AB_XX_RSTPLLCD_SIG_WIDTH 1 #define FRF_AB_XX_RSTPLLAB_SIG_LBN 24 #define FRF_AB_XX_RSTPLLAB_SIG_WIDTH 1 #define FRF_AB_XX_RESETD_SIG_LBN 23 #define FRF_AB_XX_RESETD_SIG_WIDTH 1 #define FRF_AB_XX_RESETC_SIG_LBN 22 #define FRF_AB_XX_RESETC_SIG_WIDTH 1 #define FRF_AB_XX_RESETB_SIG_LBN 21 #define FRF_AB_XX_RESETB_SIG_WIDTH 1 #define FRF_AB_XX_RESETA_SIG_LBN 20 #define FRF_AB_XX_RESETA_SIG_WIDTH 1 #define FRF_AB_XX_RSTXGXSRX_SIG_LBN 18 #define FRF_AB_XX_RSTXGXSRX_SIG_WIDTH 1 #define FRF_AB_XX_RSTXGXSTX_SIG_LBN 17 #define FRF_AB_XX_RSTXGXSTX_SIG_WIDTH 1 #define FRF_AB_XX_SD_RST_ACT_LBN 16 #define FRF_AB_XX_SD_RST_ACT_WIDTH 1 #define FRF_AB_XX_PWRDND_EN_LBN 15 #define FRF_AB_XX_PWRDND_EN_WIDTH 1 #define FRF_AB_XX_PWRDNC_EN_LBN 14 #define FRF_AB_XX_PWRDNC_EN_WIDTH 1 #define FRF_AB_XX_PWRDNB_EN_LBN 13 #define FRF_AB_XX_PWRDNB_EN_WIDTH 1 #define FRF_AB_XX_PWRDNA_EN_LBN 12 #define FRF_AB_XX_PWRDNA_EN_WIDTH 1 #define FRF_AB_XX_RSTPLLCD_EN_LBN 9 #define FRF_AB_XX_RSTPLLCD_EN_WIDTH 1 #define FRF_AB_XX_RSTPLLAB_EN_LBN 8 #define FRF_AB_XX_RSTPLLAB_EN_WIDTH 1 #define FRF_AB_XX_RESETD_EN_LBN 7 #define FRF_AB_XX_RESETD_EN_WIDTH 1 #define FRF_AB_XX_RESETC_EN_LBN 6 #define FRF_AB_XX_RESETC_EN_WIDTH 1 #define FRF_AB_XX_RESETB_EN_LBN 5 #define FRF_AB_XX_RESETB_EN_WIDTH 1 #define FRF_AB_XX_RESETA_EN_LBN 4 #define FRF_AB_XX_RESETA_EN_WIDTH 1 #define FRF_AB_XX_RSTXGXSRX_EN_LBN 2 #define FRF_AB_XX_RSTXGXSRX_EN_WIDTH 1 #define FRF_AB_XX_RSTXGXSTX_EN_LBN 1 #define FRF_AB_XX_RSTXGXSTX_EN_WIDTH 1 #define FRF_AB_XX_RST_XX_EN_LBN 0 #define FRF_AB_XX_RST_XX_EN_WIDTH 1 /* * FR_AB_XX_SD_CTL_REG(128bit): * XGXS/XAUI powerdown/reset control register */ #define FR_AB_XX_SD_CTL_REG_OFST 0x00001310 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_XX_TERMADJ1_LBN 17 #define FRF_AB_XX_TERMADJ1_WIDTH 1 #define FRF_AB_XX_TERMADJ0_LBN 16 #define FRF_AB_XX_TERMADJ0_WIDTH 1 #define FRF_AB_XX_HIDRVD_LBN 15 #define FRF_AB_XX_HIDRVD_WIDTH 1 #define FRF_AB_XX_LODRVD_LBN 14 #define FRF_AB_XX_LODRVD_WIDTH 1 #define FRF_AB_XX_HIDRVC_LBN 13 #define FRF_AB_XX_HIDRVC_WIDTH 1 #define FRF_AB_XX_LODRVC_LBN 12 #define FRF_AB_XX_LODRVC_WIDTH 1 #define FRF_AB_XX_HIDRVB_LBN 11 #define FRF_AB_XX_HIDRVB_WIDTH 1 #define FRF_AB_XX_LODRVB_LBN 10 #define FRF_AB_XX_LODRVB_WIDTH 1 #define FRF_AB_XX_HIDRVA_LBN 9 #define FRF_AB_XX_HIDRVA_WIDTH 1 #define FRF_AB_XX_LODRVA_LBN 8 #define FRF_AB_XX_LODRVA_WIDTH 1 #define FRF_AB_XX_LPBKD_LBN 3 #define FRF_AB_XX_LPBKD_WIDTH 1 #define FRF_AB_XX_LPBKC_LBN 2 #define FRF_AB_XX_LPBKC_WIDTH 1 #define FRF_AB_XX_LPBKB_LBN 1 #define FRF_AB_XX_LPBKB_WIDTH 1 #define FRF_AB_XX_LPBKA_LBN 0 #define FRF_AB_XX_LPBKA_WIDTH 1 /* * FR_AB_XX_TXDRV_CTL_REG(128bit): * XAUI SerDes transmit drive control register */ #define FR_AB_XX_TXDRV_CTL_REG_OFST 0x00001320 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_XX_DEQD_LBN 28 #define FRF_AB_XX_DEQD_WIDTH 4 #define FRF_AB_XX_DEQC_LBN 24 #define FRF_AB_XX_DEQC_WIDTH 4 #define FRF_AB_XX_DEQB_LBN 20 #define FRF_AB_XX_DEQB_WIDTH 4 #define FRF_AB_XX_DEQA_LBN 16 #define FRF_AB_XX_DEQA_WIDTH 4 #define FRF_AB_XX_DTXD_LBN 12 #define FRF_AB_XX_DTXD_WIDTH 4 #define FRF_AB_XX_DTXC_LBN 8 #define FRF_AB_XX_DTXC_WIDTH 4 #define FRF_AB_XX_DTXB_LBN 4 #define FRF_AB_XX_DTXB_WIDTH 4 #define FRF_AB_XX_DTXA_LBN 0 #define FRF_AB_XX_DTXA_WIDTH 4 /* * FR_AB_XX_PRBS_CTL_REG(128bit): * documentation to be written for sum_XX_PRBS_CTL_REG */ #define FR_AB_XX_PRBS_CTL_REG_OFST 0x00001330 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_XX_CH3_RX_PRBS_SEL_LBN 30 #define FRF_AB_XX_CH3_RX_PRBS_SEL_WIDTH 2 #define FRF_AB_XX_CH3_RX_PRBS_INV_LBN 29 #define FRF_AB_XX_CH3_RX_PRBS_INV_WIDTH 1 #define FRF_AB_XX_CH3_RX_PRBS_CHKEN_LBN 28 #define FRF_AB_XX_CH3_RX_PRBS_CHKEN_WIDTH 1 #define FRF_AB_XX_CH2_RX_PRBS_SEL_LBN 26 #define FRF_AB_XX_CH2_RX_PRBS_SEL_WIDTH 2 #define FRF_AB_XX_CH2_RX_PRBS_INV_LBN 25 #define FRF_AB_XX_CH2_RX_PRBS_INV_WIDTH 1 #define FRF_AB_XX_CH2_RX_PRBS_CHKEN_LBN 24 #define FRF_AB_XX_CH2_RX_PRBS_CHKEN_WIDTH 1 #define FRF_AB_XX_CH1_RX_PRBS_SEL_LBN 22 #define FRF_AB_XX_CH1_RX_PRBS_SEL_WIDTH 2 #define FRF_AB_XX_CH1_RX_PRBS_INV_LBN 21 #define FRF_AB_XX_CH1_RX_PRBS_INV_WIDTH 1 #define FRF_AB_XX_CH1_RX_PRBS_CHKEN_LBN 20 #define FRF_AB_XX_CH1_RX_PRBS_CHKEN_WIDTH 1 #define FRF_AB_XX_CH0_RX_PRBS_SEL_LBN 18 #define FRF_AB_XX_CH0_RX_PRBS_SEL_WIDTH 2 #define FRF_AB_XX_CH0_RX_PRBS_INV_LBN 17 #define FRF_AB_XX_CH0_RX_PRBS_INV_WIDTH 1 #define FRF_AB_XX_CH0_RX_PRBS_CHKEN_LBN 16 #define FRF_AB_XX_CH0_RX_PRBS_CHKEN_WIDTH 1 #define FRF_AB_XX_CH3_TX_PRBS_SEL_LBN 14 #define FRF_AB_XX_CH3_TX_PRBS_SEL_WIDTH 2 #define FRF_AB_XX_CH3_TX_PRBS_INV_LBN 13 #define FRF_AB_XX_CH3_TX_PRBS_INV_WIDTH 1 #define FRF_AB_XX_CH3_TX_PRBS_CHKEN_LBN 12 #define FRF_AB_XX_CH3_TX_PRBS_CHKEN_WIDTH 1 #define FRF_AB_XX_CH2_TX_PRBS_SEL_LBN 10 #define FRF_AB_XX_CH2_TX_PRBS_SEL_WIDTH 2 #define FRF_AB_XX_CH2_TX_PRBS_INV_LBN 9 #define FRF_AB_XX_CH2_TX_PRBS_INV_WIDTH 1 #define FRF_AB_XX_CH2_TX_PRBS_CHKEN_LBN 8 #define FRF_AB_XX_CH2_TX_PRBS_CHKEN_WIDTH 1 #define FRF_AB_XX_CH1_TX_PRBS_SEL_LBN 6 #define FRF_AB_XX_CH1_TX_PRBS_SEL_WIDTH 2 #define FRF_AB_XX_CH1_TX_PRBS_INV_LBN 5 #define FRF_AB_XX_CH1_TX_PRBS_INV_WIDTH 1 #define FRF_AB_XX_CH1_TX_PRBS_CHKEN_LBN 4 #define FRF_AB_XX_CH1_TX_PRBS_CHKEN_WIDTH 1 #define FRF_AB_XX_CH0_TX_PRBS_SEL_LBN 2 #define FRF_AB_XX_CH0_TX_PRBS_SEL_WIDTH 2 #define FRF_AB_XX_CH0_TX_PRBS_INV_LBN 1 #define FRF_AB_XX_CH0_TX_PRBS_INV_WIDTH 1 #define FRF_AB_XX_CH0_TX_PRBS_CHKEN_LBN 0 #define FRF_AB_XX_CH0_TX_PRBS_CHKEN_WIDTH 1 /* * FR_AB_XX_PRBS_CHK_REG(128bit): * documentation to be written for sum_XX_PRBS_CHK_REG */ #define FR_AB_XX_PRBS_CHK_REG_OFST 0x00001340 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_XX_REV_LB_EN_LBN 16 #define FRF_AB_XX_REV_LB_EN_WIDTH 1 #define FRF_AB_XX_CH3_DEG_DET_LBN 15 #define FRF_AB_XX_CH3_DEG_DET_WIDTH 1 #define FRF_AB_XX_CH3_LFSR_LOCK_IND_LBN 14 #define FRF_AB_XX_CH3_LFSR_LOCK_IND_WIDTH 1 #define FRF_AB_XX_CH3_PRBS_FRUN_LBN 13 #define FRF_AB_XX_CH3_PRBS_FRUN_WIDTH 1 #define FRF_AB_XX_CH3_ERR_CHK_LBN 12 #define FRF_AB_XX_CH3_ERR_CHK_WIDTH 1 #define FRF_AB_XX_CH2_DEG_DET_LBN 11 #define FRF_AB_XX_CH2_DEG_DET_WIDTH 1 #define FRF_AB_XX_CH2_LFSR_LOCK_IND_LBN 10 #define FRF_AB_XX_CH2_LFSR_LOCK_IND_WIDTH 1 #define FRF_AB_XX_CH2_PRBS_FRUN_LBN 9 #define FRF_AB_XX_CH2_PRBS_FRUN_WIDTH 1 #define FRF_AB_XX_CH2_ERR_CHK_LBN 8 #define FRF_AB_XX_CH2_ERR_CHK_WIDTH 1 #define FRF_AB_XX_CH1_DEG_DET_LBN 7 #define FRF_AB_XX_CH1_DEG_DET_WIDTH 1 #define FRF_AB_XX_CH1_LFSR_LOCK_IND_LBN 6 #define FRF_AB_XX_CH1_LFSR_LOCK_IND_WIDTH 1 #define FRF_AB_XX_CH1_PRBS_FRUN_LBN 5 #define FRF_AB_XX_CH1_PRBS_FRUN_WIDTH 1 #define FRF_AB_XX_CH1_ERR_CHK_LBN 4 #define FRF_AB_XX_CH1_ERR_CHK_WIDTH 1 #define FRF_AB_XX_CH0_DEG_DET_LBN 3 #define FRF_AB_XX_CH0_DEG_DET_WIDTH 1 #define FRF_AB_XX_CH0_LFSR_LOCK_IND_LBN 2 #define FRF_AB_XX_CH0_LFSR_LOCK_IND_WIDTH 1 #define FRF_AB_XX_CH0_PRBS_FRUN_LBN 1 #define FRF_AB_XX_CH0_PRBS_FRUN_WIDTH 1 #define FRF_AB_XX_CH0_ERR_CHK_LBN 0 #define FRF_AB_XX_CH0_ERR_CHK_WIDTH 1 /* * FR_AB_XX_PRBS_ERR_REG(128bit): * documentation to be written for sum_XX_PRBS_ERR_REG */ #define FR_AB_XX_PRBS_ERR_REG_OFST 0x00001350 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_XX_CH3_PRBS_ERR_CNT_LBN 24 #define FRF_AB_XX_CH3_PRBS_ERR_CNT_WIDTH 8 #define FRF_AB_XX_CH2_PRBS_ERR_CNT_LBN 16 #define FRF_AB_XX_CH2_PRBS_ERR_CNT_WIDTH 8 #define FRF_AB_XX_CH1_PRBS_ERR_CNT_LBN 8 #define FRF_AB_XX_CH1_PRBS_ERR_CNT_WIDTH 8 #define FRF_AB_XX_CH0_PRBS_ERR_CNT_LBN 0 #define FRF_AB_XX_CH0_PRBS_ERR_CNT_WIDTH 8 /* * FR_AB_XX_CORE_STAT_REG(128bit): * XAUI XGXS core status register */ #define FR_AB_XX_CORE_STAT_REG_OFST 0x00001360 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FRF_AB_XX_FORCE_SIG3_LBN 31 #define FRF_AB_XX_FORCE_SIG3_WIDTH 1 #define FRF_AB_XX_FORCE_SIG3_VAL_LBN 30 #define FRF_AB_XX_FORCE_SIG3_VAL_WIDTH 1 #define FRF_AB_XX_FORCE_SIG2_LBN 29 #define FRF_AB_XX_FORCE_SIG2_WIDTH 1 #define FRF_AB_XX_FORCE_SIG2_VAL_LBN 28 #define FRF_AB_XX_FORCE_SIG2_VAL_WIDTH 1 #define FRF_AB_XX_FORCE_SIG1_LBN 27 #define FRF_AB_XX_FORCE_SIG1_WIDTH 1 #define FRF_AB_XX_FORCE_SIG1_VAL_LBN 26 #define FRF_AB_XX_FORCE_SIG1_VAL_WIDTH 1 #define FRF_AB_XX_FORCE_SIG0_LBN 25 #define FRF_AB_XX_FORCE_SIG0_WIDTH 1 #define FRF_AB_XX_FORCE_SIG0_VAL_LBN 24 #define FRF_AB_XX_FORCE_SIG0_VAL_WIDTH 1 #define FRF_AB_XX_XGXS_LB_EN_LBN 23 #define FRF_AB_XX_XGXS_LB_EN_WIDTH 1 #define FRF_AB_XX_XGMII_LB_EN_LBN 22 #define FRF_AB_XX_XGMII_LB_EN_WIDTH 1 #define FRF_AB_XX_MATCH_FAULT_LBN 21 #define FRF_AB_XX_MATCH_FAULT_WIDTH 1 #define FRF_AB_XX_ALIGN_DONE_LBN 20 #define FRF_AB_XX_ALIGN_DONE_WIDTH 1 #define FRF_AB_XX_SYNC_STAT3_LBN 19 #define FRF_AB_XX_SYNC_STAT3_WIDTH 1 #define FRF_AB_XX_SYNC_STAT2_LBN 18 #define FRF_AB_XX_SYNC_STAT2_WIDTH 1 #define FRF_AB_XX_SYNC_STAT1_LBN 17 #define FRF_AB_XX_SYNC_STAT1_WIDTH 1 #define FRF_AB_XX_SYNC_STAT0_LBN 16 #define FRF_AB_XX_SYNC_STAT0_WIDTH 1 #define FRF_AB_XX_COMMA_DET_CH3_LBN 15 #define FRF_AB_XX_COMMA_DET_CH3_WIDTH 1 #define FRF_AB_XX_COMMA_DET_CH2_LBN 14 #define FRF_AB_XX_COMMA_DET_CH2_WIDTH 1 #define FRF_AB_XX_COMMA_DET_CH1_LBN 13 #define FRF_AB_XX_COMMA_DET_CH1_WIDTH 1 #define FRF_AB_XX_COMMA_DET_CH0_LBN 12 #define FRF_AB_XX_COMMA_DET_CH0_WIDTH 1 #define FRF_AB_XX_CGRP_ALIGN_CH3_LBN 11 #define FRF_AB_XX_CGRP_ALIGN_CH3_WIDTH 1 #define FRF_AB_XX_CGRP_ALIGN_CH2_LBN 10 #define FRF_AB_XX_CGRP_ALIGN_CH2_WIDTH 1 #define FRF_AB_XX_CGRP_ALIGN_CH1_LBN 9 #define FRF_AB_XX_CGRP_ALIGN_CH1_WIDTH 1 #define FRF_AB_XX_CGRP_ALIGN_CH0_LBN 8 #define FRF_AB_XX_CGRP_ALIGN_CH0_WIDTH 1 #define FRF_AB_XX_CHAR_ERR_CH3_LBN 7 #define FRF_AB_XX_CHAR_ERR_CH3_WIDTH 1 #define FRF_AB_XX_CHAR_ERR_CH2_LBN 6 #define FRF_AB_XX_CHAR_ERR_CH2_WIDTH 1 #define FRF_AB_XX_CHAR_ERR_CH1_LBN 5 #define FRF_AB_XX_CHAR_ERR_CH1_WIDTH 1 #define FRF_AB_XX_CHAR_ERR_CH0_LBN 4 #define FRF_AB_XX_CHAR_ERR_CH0_WIDTH 1 #define FRF_AB_XX_DISPERR_CH3_LBN 3 #define FRF_AB_XX_DISPERR_CH3_WIDTH 1 #define FRF_AB_XX_DISPERR_CH2_LBN 2 #define FRF_AB_XX_DISPERR_CH2_WIDTH 1 #define FRF_AB_XX_DISPERR_CH1_LBN 1 #define FRF_AB_XX_DISPERR_CH1_WIDTH 1 #define FRF_AB_XX_DISPERR_CH0_LBN 0 #define FRF_AB_XX_DISPERR_CH0_WIDTH 1 /* * FR_AA_RX_DESC_PTR_TBL_KER(128bit): * Receive descriptor pointer table */ #define FR_AA_RX_DESC_PTR_TBL_KER_OFST 0x00011800 /* falcona0=net_func_bar2 */ #define FR_AA_RX_DESC_PTR_TBL_KER_STEP 16 #define FR_AA_RX_DESC_PTR_TBL_KER_ROWS 4 /* * FR_AZ_RX_DESC_PTR_TBL(128bit): * Receive descriptor pointer table */ #define FR_AZ_RX_DESC_PTR_TBL_OFST 0x00f40000 /* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FR_AZ_RX_DESC_PTR_TBL_STEP 16 #define FR_CZ_RX_DESC_PTR_TBL_ROWS 1024 #define FR_AB_RX_DESC_PTR_TBL_ROWS 4096 #define FRF_CZ_RX_HDR_SPLIT_LBN 90 #define FRF_CZ_RX_HDR_SPLIT_WIDTH 1 #define FRF_AZ_RX_RESET_LBN 89 #define FRF_AZ_RX_RESET_WIDTH 1 #define FRF_AZ_RX_ISCSI_DDIG_EN_LBN 88 #define FRF_AZ_RX_ISCSI_DDIG_EN_WIDTH 1 #define FRF_AZ_RX_ISCSI_HDIG_EN_LBN 87 #define FRF_AZ_RX_ISCSI_HDIG_EN_WIDTH 1 #define FRF_AZ_RX_DESC_PREF_ACT_LBN 86 #define FRF_AZ_RX_DESC_PREF_ACT_WIDTH 1 #define FRF_AZ_RX_DC_HW_RPTR_LBN 80 #define FRF_AZ_RX_DC_HW_RPTR_WIDTH 6 #define FRF_AZ_RX_DESCQ_HW_RPTR_LBN 68 #define FRF_AZ_RX_DESCQ_HW_RPTR_WIDTH 12 #define FRF_AZ_RX_DESCQ_SW_WPTR_LBN 56 #define FRF_AZ_RX_DESCQ_SW_WPTR_WIDTH 12 #define FRF_AZ_RX_DESCQ_BUF_BASE_ID_LBN 36 #define FRF_AZ_RX_DESCQ_BUF_BASE_ID_WIDTH 20 #define FRF_AZ_RX_DESCQ_EVQ_ID_LBN 24 #define FRF_AZ_RX_DESCQ_EVQ_ID_WIDTH 12 #define FRF_AZ_RX_DESCQ_OWNER_ID_LBN 10 #define FRF_AZ_RX_DESCQ_OWNER_ID_WIDTH 14 #define FRF_AZ_RX_DESCQ_LABEL_LBN 5 #define FRF_AZ_RX_DESCQ_LABEL_WIDTH 5 #define FRF_AZ_RX_DESCQ_SIZE_LBN 3 #define FRF_AZ_RX_DESCQ_SIZE_WIDTH 2 #define FFE_AZ_RX_DESCQ_SIZE_4K 3 #define FFE_AZ_RX_DESCQ_SIZE_2K 2 #define FFE_AZ_RX_DESCQ_SIZE_1K 1 #define FFE_AZ_RX_DESCQ_SIZE_512 0 #define FRF_AZ_RX_DESCQ_TYPE_LBN 2 #define FRF_AZ_RX_DESCQ_TYPE_WIDTH 1 #define FRF_AZ_RX_DESCQ_JUMBO_LBN 1 #define FRF_AZ_RX_DESCQ_JUMBO_WIDTH 1 #define FRF_AZ_RX_DESCQ_EN_LBN 0 #define FRF_AZ_RX_DESCQ_EN_WIDTH 1 /* * FR_AA_TX_DESC_PTR_TBL_KER(128bit): * Transmit descriptor pointer */ #define FR_AA_TX_DESC_PTR_TBL_KER_OFST 0x00011900 /* falcona0=net_func_bar2 */ #define FR_AA_TX_DESC_PTR_TBL_KER_STEP 16 #define FR_AA_TX_DESC_PTR_TBL_KER_ROWS 8 /* * FR_AZ_TX_DESC_PTR_TBL(128bit): * Transmit descriptor pointer */ #define FR_AZ_TX_DESC_PTR_TBL_OFST 0x00f50000 /* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FR_AZ_TX_DESC_PTR_TBL_STEP 16 #define FR_AB_TX_DESC_PTR_TBL_ROWS 4096 #define FR_CZ_TX_DESC_PTR_TBL_ROWS 1024 #define FRF_CZ_TX_DPT_Q_MASK_WIDTH_LBN 94 #define FRF_CZ_TX_DPT_Q_MASK_WIDTH_WIDTH 2 #define FRF_CZ_TX_DPT_ETH_FILT_EN_LBN 93 #define FRF_CZ_TX_DPT_ETH_FILT_EN_WIDTH 1 #define FRF_CZ_TX_DPT_IP_FILT_EN_LBN 92 #define FRF_CZ_TX_DPT_IP_FILT_EN_WIDTH 1 #define FRF_BZ_TX_NON_IP_DROP_DIS_LBN 91 #define FRF_BZ_TX_NON_IP_DROP_DIS_WIDTH 1 #define FRF_BZ_TX_IP_CHKSM_DIS_LBN 90 #define FRF_BZ_TX_IP_CHKSM_DIS_WIDTH 1 #define FRF_BZ_TX_TCP_CHKSM_DIS_LBN 89 #define FRF_BZ_TX_TCP_CHKSM_DIS_WIDTH 1 #define FRF_AZ_TX_DESCQ_EN_LBN 88 #define FRF_AZ_TX_DESCQ_EN_WIDTH 1 #define FRF_AZ_TX_ISCSI_DDIG_EN_LBN 87 #define FRF_AZ_TX_ISCSI_DDIG_EN_WIDTH 1 #define FRF_AZ_TX_ISCSI_HDIG_EN_LBN 86 #define FRF_AZ_TX_ISCSI_HDIG_EN_WIDTH 1 #define FRF_AZ_TX_DC_HW_RPTR_LBN 80 #define FRF_AZ_TX_DC_HW_RPTR_WIDTH 6 #define FRF_AZ_TX_DESCQ_HW_RPTR_LBN 68 #define FRF_AZ_TX_DESCQ_HW_RPTR_WIDTH 12 #define FRF_AZ_TX_DESCQ_SW_WPTR_LBN 56 #define FRF_AZ_TX_DESCQ_SW_WPTR_WIDTH 12 #define FRF_AZ_TX_DESCQ_BUF_BASE_ID_LBN 36 #define FRF_AZ_TX_DESCQ_BUF_BASE_ID_WIDTH 20 #define FRF_AZ_TX_DESCQ_EVQ_ID_LBN 24 #define FRF_AZ_TX_DESCQ_EVQ_ID_WIDTH 12 #define FRF_AZ_TX_DESCQ_OWNER_ID_LBN 10 #define FRF_AZ_TX_DESCQ_OWNER_ID_WIDTH 14 #define FRF_AZ_TX_DESCQ_LABEL_LBN 5 #define FRF_AZ_TX_DESCQ_LABEL_WIDTH 5 #define FRF_AZ_TX_DESCQ_SIZE_LBN 3 #define FRF_AZ_TX_DESCQ_SIZE_WIDTH 2 #define FFE_AZ_TX_DESCQ_SIZE_4K 3 #define FFE_AZ_TX_DESCQ_SIZE_2K 2 #define FFE_AZ_TX_DESCQ_SIZE_1K 1 #define FFE_AZ_TX_DESCQ_SIZE_512 0 #define FRF_AZ_TX_DESCQ_TYPE_LBN 1 #define FRF_AZ_TX_DESCQ_TYPE_WIDTH 2 #define FRF_AZ_TX_DESCQ_FLUSH_LBN 0 #define FRF_AZ_TX_DESCQ_FLUSH_WIDTH 1 /* * FR_AA_EVQ_PTR_TBL_KER(128bit): * Event queue pointer table */ #define FR_AA_EVQ_PTR_TBL_KER_OFST 0x00011a00 /* falcona0=net_func_bar2 */ #define FR_AA_EVQ_PTR_TBL_KER_STEP 16 #define FR_AA_EVQ_PTR_TBL_KER_ROWS 4 /* * FR_AZ_EVQ_PTR_TBL(128bit): * Event queue pointer table */ #define FR_AZ_EVQ_PTR_TBL_OFST 0x00f60000 /* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FR_AZ_EVQ_PTR_TBL_STEP 16 #define FR_CZ_EVQ_PTR_TBL_ROWS 1024 #define FR_AB_EVQ_PTR_TBL_ROWS 4096 #define FRF_BZ_EVQ_RPTR_IGN_LBN 40 #define FRF_BZ_EVQ_RPTR_IGN_WIDTH 1 #define FRF_AZ_EVQ_WKUP_OR_INT_EN_LBN 39 #define FRF_AZ_EVQ_WKUP_OR_INT_EN_WIDTH 1 #define FRF_AZ_EVQ_NXT_WPTR_LBN 24 #define FRF_AZ_EVQ_NXT_WPTR_WIDTH 15 #define FRF_AZ_EVQ_EN_LBN 23 #define FRF_AZ_EVQ_EN_WIDTH 1 #define FRF_AZ_EVQ_SIZE_LBN 20 #define FRF_AZ_EVQ_SIZE_WIDTH 3 #define FFE_AZ_EVQ_SIZE_32K 6 #define FFE_AZ_EVQ_SIZE_16K 5 #define FFE_AZ_EVQ_SIZE_8K 4 #define FFE_AZ_EVQ_SIZE_4K 3 #define FFE_AZ_EVQ_SIZE_2K 2 #define FFE_AZ_EVQ_SIZE_1K 1 #define FFE_AZ_EVQ_SIZE_512 0 #define FRF_AZ_EVQ_BUF_BASE_ID_LBN 0 #define FRF_AZ_EVQ_BUF_BASE_ID_WIDTH 20 /* * FR_AA_BUF_HALF_TBL_KER(64bit): * Buffer table in half buffer table mode direct access by driver */ #define FR_AA_BUF_HALF_TBL_KER_OFST 0x00018000 /* falcona0=net_func_bar2 */ #define FR_AA_BUF_HALF_TBL_KER_STEP 8 #define FR_AA_BUF_HALF_TBL_KER_ROWS 4096 /* * FR_AZ_BUF_HALF_TBL(64bit): * Buffer table in half buffer table mode direct access by driver */ #define FR_AZ_BUF_HALF_TBL_OFST 0x00800000 /* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FR_AZ_BUF_HALF_TBL_STEP 8 #define FR_CZ_BUF_HALF_TBL_ROWS 147456 #define FR_AB_BUF_HALF_TBL_ROWS 524288 #define FRF_AZ_BUF_ADR_HBUF_ODD_LBN 44 #define FRF_AZ_BUF_ADR_HBUF_ODD_WIDTH 20 #define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN 32 #define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_WIDTH 12 #define FRF_AZ_BUF_ADR_HBUF_EVEN_LBN 12 #define FRF_AZ_BUF_ADR_HBUF_EVEN_WIDTH 20 #define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN 0 #define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH 12 /* * FR_AA_BUF_FULL_TBL_KER(64bit): * Buffer table in full buffer table mode direct access by driver */ #define FR_AA_BUF_FULL_TBL_KER_OFST 0x00018000 /* falcona0=net_func_bar2 */ #define FR_AA_BUF_FULL_TBL_KER_STEP 8 #define FR_AA_BUF_FULL_TBL_KER_ROWS 4096 /* * FR_AZ_BUF_FULL_TBL(64bit): * Buffer table in full buffer table mode direct access by driver */ #define FR_AZ_BUF_FULL_TBL_OFST 0x00800000 /* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FR_AZ_BUF_FULL_TBL_STEP 8 #define FR_CZ_BUF_FULL_TBL_ROWS 147456 #define FR_AB_BUF_FULL_TBL_ROWS 917504 #define FRF_AZ_BUF_FULL_UNUSED_LBN 51 #define FRF_AZ_BUF_FULL_UNUSED_WIDTH 13 #define FRF_AZ_IP_DAT_BUF_SIZE_LBN 50 #define FRF_AZ_IP_DAT_BUF_SIZE_WIDTH 1 #define FRF_AZ_BUF_ADR_REGION_LBN 48 #define FRF_AZ_BUF_ADR_REGION_WIDTH 2 #define FFE_AZ_BUF_ADR_REGN3 3 #define FFE_AZ_BUF_ADR_REGN2 2 #define FFE_AZ_BUF_ADR_REGN1 1 #define FFE_AZ_BUF_ADR_REGN0 0 #define FRF_AZ_BUF_ADR_FBUF_LBN 14 #define FRF_AZ_BUF_ADR_FBUF_WIDTH 34 #define FRF_AZ_BUF_ADR_FBUF_DW0_LBN 14 #define FRF_AZ_BUF_ADR_FBUF_DW0_WIDTH 32 #define FRF_AZ_BUF_ADR_FBUF_DW1_LBN 46 #define FRF_AZ_BUF_ADR_FBUF_DW1_WIDTH 2 #define FRF_AZ_BUF_OWNER_ID_FBUF_LBN 0 #define FRF_AZ_BUF_OWNER_ID_FBUF_WIDTH 14 /* * FR_AZ_RX_FILTER_TBL0(128bit): * TCP/IPv4 Receive filter table */ #define FR_AZ_RX_FILTER_TBL0_OFST 0x00f00000 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ #define FR_AZ_RX_FILTER_TBL0_STEP 32 #define FR_AZ_RX_FILTER_TBL0_ROWS 8192 /* * FR_AB_RX_FILTER_TBL1(128bit): * TCP/IPv4 Receive filter table */ #define FR_AB_RX_FILTER_TBL1_OFST 0x00f00010 /* falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FR_AB_RX_FILTER_TBL1_STEP 32 #define FR_AB_RX_FILTER_TBL1_ROWS 8192 #define FRF_BZ_RSS_EN_LBN 110 #define FRF_BZ_RSS_EN_WIDTH 1 #define FRF_BZ_SCATTER_EN_LBN 109 #define FRF_BZ_SCATTER_EN_WIDTH 1 #define FRF_AZ_TCP_UDP_LBN 108 #define FRF_AZ_TCP_UDP_WIDTH 1 #define FRF_AZ_RXQ_ID_LBN 96 #define FRF_AZ_RXQ_ID_WIDTH 12 #define FRF_AZ_DEST_IP_LBN 64 #define FRF_AZ_DEST_IP_WIDTH 32 #define FRF_AZ_DEST_PORT_TCP_LBN 48 #define FRF_AZ_DEST_PORT_TCP_WIDTH 16 #define FRF_AZ_SRC_IP_LBN 16 #define FRF_AZ_SRC_IP_WIDTH 32 #define FRF_AZ_SRC_TCP_DEST_UDP_LBN 0 #define FRF_AZ_SRC_TCP_DEST_UDP_WIDTH 16 /* * FR_CZ_RX_MAC_FILTER_TBL0(128bit): * Receive Ethernet filter table */ #define FR_CZ_RX_MAC_FILTER_TBL0_OFST 0x00f00010 /* sienaa0=net_func_bar2 */ #define FR_CZ_RX_MAC_FILTER_TBL0_STEP 32 #define FR_CZ_RX_MAC_FILTER_TBL0_ROWS 512 #define FRF_CZ_RMFT_RSS_EN_LBN 75 #define FRF_CZ_RMFT_RSS_EN_WIDTH 1 #define FRF_CZ_RMFT_SCATTER_EN_LBN 74 #define FRF_CZ_RMFT_SCATTER_EN_WIDTH 1 #define FRF_CZ_RMFT_IP_OVERRIDE_LBN 73 #define FRF_CZ_RMFT_IP_OVERRIDE_WIDTH 1 #define FRF_CZ_RMFT_RXQ_ID_LBN 61 #define FRF_CZ_RMFT_RXQ_ID_WIDTH 12 #define FRF_CZ_RMFT_WILDCARD_MATCH_LBN 60 #define FRF_CZ_RMFT_WILDCARD_MATCH_WIDTH 1 #define FRF_CZ_RMFT_DEST_MAC_LBN 12 #define FRF_CZ_RMFT_DEST_MAC_WIDTH 48 #define FRF_CZ_RMFT_DEST_MAC_DW0_LBN 12 #define FRF_CZ_RMFT_DEST_MAC_DW0_WIDTH 32 #define FRF_CZ_RMFT_DEST_MAC_DW1_LBN 44 #define FRF_CZ_RMFT_DEST_MAC_DW1_WIDTH 16 #define FRF_CZ_RMFT_VLAN_ID_LBN 0 #define FRF_CZ_RMFT_VLAN_ID_WIDTH 12 /* * FR_AZ_TIMER_TBL(128bit): * Timer table */ #define FR_AZ_TIMER_TBL_OFST 0x00f70000 /* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FR_AZ_TIMER_TBL_STEP 16 #define FR_CZ_TIMER_TBL_ROWS 1024 #define FR_AB_TIMER_TBL_ROWS 4096 #define FRF_CZ_TIMER_Q_EN_LBN 33 #define FRF_CZ_TIMER_Q_EN_WIDTH 1 #define FRF_CZ_INT_ARMD_LBN 32 #define FRF_CZ_INT_ARMD_WIDTH 1 #define FRF_CZ_INT_PEND_LBN 31 #define FRF_CZ_INT_PEND_WIDTH 1 #define FRF_CZ_HOST_NOTIFY_MODE_LBN 30 #define FRF_CZ_HOST_NOTIFY_MODE_WIDTH 1 #define FRF_CZ_RELOAD_TIMER_VAL_LBN 16 #define FRF_CZ_RELOAD_TIMER_VAL_WIDTH 14 #define FRF_CZ_TIMER_MODE_LBN 14 #define FRF_CZ_TIMER_MODE_WIDTH 2 #define FFE_CZ_TIMER_MODE_INT_HLDOFF 3 #define FFE_CZ_TIMER_MODE_TRIG_START 2 #define FFE_CZ_TIMER_MODE_IMMED_START 1 #define FFE_CZ_TIMER_MODE_DIS 0 #define FRF_AB_TIMER_MODE_LBN 12 #define FRF_AB_TIMER_MODE_WIDTH 2 #define FFE_AB_TIMER_MODE_INT_HLDOFF 2 #define FFE_AB_TIMER_MODE_TRIG_START 2 #define FFE_AB_TIMER_MODE_IMMED_START 1 #define FFE_AB_TIMER_MODE_DIS 0 #define FRF_CZ_TIMER_VAL_LBN 0 #define FRF_CZ_TIMER_VAL_WIDTH 14 #define FRF_AB_TIMER_VAL_LBN 0 #define FRF_AB_TIMER_VAL_WIDTH 12 /* * FR_BZ_TX_PACE_TBL(128bit): * Transmit pacing table */ #define FR_BZ_TX_PACE_TBL_OFST 0x00f80000 /* sienaa0=net_func_bar2,falconb0=net_func_bar2 */ #define FR_AZ_TX_PACE_TBL_STEP 16 #define FR_CZ_TX_PACE_TBL_ROWS 1024 #define FR_BB_TX_PACE_TBL_ROWS 4096 /* * FR_AA_TX_PACE_TBL(128bit): * Transmit pacing table */ #define FR_AA_TX_PACE_TBL_OFST 0x00f80040 /* falcona0=char_func_bar0 */ /* FR_AZ_TX_PACE_TBL_STEP 16 */ #define FR_AA_TX_PACE_TBL_ROWS 4092 #define FRF_AZ_TX_PACE_LBN 0 #define FRF_AZ_TX_PACE_WIDTH 5 /* * FR_BZ_RX_INDIRECTION_TBL(7bit): * RX Indirection Table */ #define FR_BZ_RX_INDIRECTION_TBL_OFST 0x00fb0000 /* falconb0,sienaa0=net_func_bar2 */ #define FR_BZ_RX_INDIRECTION_TBL_STEP 16 #define FR_BZ_RX_INDIRECTION_TBL_ROWS 128 #define FRF_BZ_IT_QUEUE_LBN 0 #define FRF_BZ_IT_QUEUE_WIDTH 6 /* * FR_CZ_TX_FILTER_TBL0(128bit): * TCP/IPv4 Transmit filter table */ #define FR_CZ_TX_FILTER_TBL0_OFST 0x00fc0000 /* sienaa0=net_func_bar2 */ #define FR_CZ_TX_FILTER_TBL0_STEP 16 #define FR_CZ_TX_FILTER_TBL0_ROWS 8192 #define FRF_CZ_TIFT_TCP_UDP_LBN 108 #define FRF_CZ_TIFT_TCP_UDP_WIDTH 1 #define FRF_CZ_TIFT_TXQ_ID_LBN 96 #define FRF_CZ_TIFT_TXQ_ID_WIDTH 12 #define FRF_CZ_TIFT_DEST_IP_LBN 64 #define FRF_CZ_TIFT_DEST_IP_WIDTH 32 #define FRF_CZ_TIFT_DEST_PORT_TCP_LBN 48 #define FRF_CZ_TIFT_DEST_PORT_TCP_WIDTH 16 #define FRF_CZ_TIFT_SRC_IP_LBN 16 #define FRF_CZ_TIFT_SRC_IP_WIDTH 32 #define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_LBN 0 #define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_WIDTH 16 /* * FR_CZ_TX_MAC_FILTER_TBL0(128bit): * Transmit Ethernet filter table */ #define FR_CZ_TX_MAC_FILTER_TBL0_OFST 0x00fe0000 /* sienaa0=net_func_bar2 */ #define FR_CZ_TX_MAC_FILTER_TBL0_STEP 16 #define FR_CZ_TX_MAC_FILTER_TBL0_ROWS 512 #define FRF_CZ_TMFT_TXQ_ID_LBN 61 #define FRF_CZ_TMFT_TXQ_ID_WIDTH 12 #define FRF_CZ_TMFT_WILDCARD_MATCH_LBN 60 #define FRF_CZ_TMFT_WILDCARD_MATCH_WIDTH 1 #define FRF_CZ_TMFT_SRC_MAC_LBN 12 #define FRF_CZ_TMFT_SRC_MAC_WIDTH 48 #define FRF_CZ_TMFT_SRC_MAC_DW0_LBN 12 #define FRF_CZ_TMFT_SRC_MAC_DW0_WIDTH 32 #define FRF_CZ_TMFT_SRC_MAC_DW1_LBN 44 #define FRF_CZ_TMFT_SRC_MAC_DW1_WIDTH 16 #define FRF_CZ_TMFT_VLAN_ID_LBN 0 #define FRF_CZ_TMFT_VLAN_ID_WIDTH 12 /* * FR_CZ_MC_TREG_SMEM(32bit): * MC Shared Memory */ #define FR_CZ_MC_TREG_SMEM_OFST 0x00ff0000 /* sienaa0=net_func_bar2 */ #define FR_CZ_MC_TREG_SMEM_STEP 4 #define FR_CZ_MC_TREG_SMEM_ROWS 512 #define FRF_CZ_MC_TREG_SMEM_ROW_LBN 0 #define FRF_CZ_MC_TREG_SMEM_ROW_WIDTH 32 /* * FR_BB_MSIX_VECTOR_TABLE(128bit): * MSIX Vector Table */ #define FR_BB_MSIX_VECTOR_TABLE_OFST 0x00ff0000 /* falconb0=net_func_bar2 */ #define FR_BZ_MSIX_VECTOR_TABLE_STEP 16 #define FR_BB_MSIX_VECTOR_TABLE_ROWS 64 /* * FR_CZ_MSIX_VECTOR_TABLE(128bit): * MSIX Vector Table */ #define FR_CZ_MSIX_VECTOR_TABLE_OFST 0x00000000 /* sienaa0=pci_f0_bar4 */ /* FR_BZ_MSIX_VECTOR_TABLE_STEP 16 */ #define FR_CZ_MSIX_VECTOR_TABLE_ROWS 1024 #define FRF_BZ_MSIX_VECTOR_RESERVED_LBN 97 #define FRF_BZ_MSIX_VECTOR_RESERVED_WIDTH 31 #define FRF_BZ_MSIX_VECTOR_MASK_LBN 96 #define FRF_BZ_MSIX_VECTOR_MASK_WIDTH 1 #define FRF_BZ_MSIX_MESSAGE_DATA_LBN 64 #define FRF_BZ_MSIX_MESSAGE_DATA_WIDTH 32 #define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_LBN 32 #define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_WIDTH 32 #define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_LBN 0 #define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_WIDTH 32 /* * FR_BB_MSIX_PBA_TABLE(32bit): * MSIX Pending Bit Array */ #define FR_BB_MSIX_PBA_TABLE_OFST 0x00ff2000 /* falconb0=net_func_bar2 */ #define FR_BZ_MSIX_PBA_TABLE_STEP 4 #define FR_BB_MSIX_PBA_TABLE_ROWS 2 /* * FR_CZ_MSIX_PBA_TABLE(32bit): * MSIX Pending Bit Array */ #define FR_CZ_MSIX_PBA_TABLE_OFST 0x00008000 /* sienaa0=pci_f0_bar4 */ /* FR_BZ_MSIX_PBA_TABLE_STEP 4 */ #define FR_CZ_MSIX_PBA_TABLE_ROWS 32 #define FRF_BZ_MSIX_PBA_PEND_DWORD_LBN 0 #define FRF_BZ_MSIX_PBA_PEND_DWORD_WIDTH 32 /* * FR_AZ_SRM_DBG_REG(64bit): * SRAM debug access */ #define FR_AZ_SRM_DBG_REG_OFST 0x03000000 /* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ #define FR_AZ_SRM_DBG_REG_STEP 8 #define FR_CZ_SRM_DBG_REG_ROWS 262144 #define FR_AB_SRM_DBG_REG_ROWS 2097152 #define FRF_AZ_SRM_DBG_LBN 0 #define FRF_AZ_SRM_DBG_WIDTH 64 #define FRF_AZ_SRM_DBG_DW0_LBN 0 #define FRF_AZ_SRM_DBG_DW0_WIDTH 32 #define FRF_AZ_SRM_DBG_DW1_LBN 32 #define FRF_AZ_SRM_DBG_DW1_WIDTH 32 /* * FR_AA_INT_ACK_CHAR(32bit): * CHAR interrupt acknowledge register */ #define FR_AA_INT_ACK_CHAR_OFST 0x00000060 /* falcona0=char_func_bar0 */ #define FRF_AA_INT_ACK_CHAR_FIELD_LBN 0 #define FRF_AA_INT_ACK_CHAR_FIELD_WIDTH 32 /* FS_DRIVER_EV */ #define FSF_AZ_DRIVER_EV_SUBCODE_LBN 56 #define FSF_AZ_DRIVER_EV_SUBCODE_WIDTH 4 #define FSE_AZ_TX_DSC_ERROR_EV 15 #define FSE_AZ_RX_DSC_ERROR_EV 14 #define FSE_AZ_RX_RECOVER_EV 11 #define FSE_AZ_TIMER_EV 10 #define FSE_AZ_TX_PKT_NON_TCP_UDP 9 #define FSE_AZ_WAKE_UP_EV 6 #define FSE_AZ_SRM_UPD_DONE_EV 5 #define FSE_AZ_EVQ_NOT_EN_EV 3 #define FSE_AZ_EVQ_INIT_DONE_EV 2 #define FSE_AZ_RX_DESCQ_FLS_DONE_EV 1 #define FSE_AZ_TX_DESCQ_FLS_DONE_EV 0 #define FSF_AZ_DRIVER_EV_SUBDATA_LBN 0 #define FSF_AZ_DRIVER_EV_SUBDATA_WIDTH 14 /* FS_EVENT_ENTRY */ #define FSF_AZ_EV_CODE_LBN 60 #define FSF_AZ_EV_CODE_WIDTH 4 #define FSE_AZ_EV_CODE_USER_EV 8 #define FSE_AZ_EV_CODE_DRV_GEN_EV 7 #define FSE_AZ_EV_CODE_GLOBAL_EV 6 #define FSE_AZ_EV_CODE_DRIVER_EV 5 #define FSE_AZ_EV_CODE_TX_EV 2 #define FSE_AZ_EV_CODE_RX_EV 0 #define FSF_AZ_EV_DATA_LBN 0 #define FSF_AZ_EV_DATA_WIDTH 60 #define FSF_AZ_EV_DATA_DW0_LBN 0 #define FSF_AZ_EV_DATA_DW0_WIDTH 32 #define FSF_AZ_EV_DATA_DW1_LBN 32 #define FSF_AZ_EV_DATA_DW1_WIDTH 28 /* FS_GLOBAL_EV */ #define FSF_AA_GLB_EV_RX_RECOVERY_LBN 12 #define FSF_AA_GLB_EV_RX_RECOVERY_WIDTH 1 #define FSF_BZ_GLB_EV_XG_MNT_INTR_LBN 11 #define FSF_BZ_GLB_EV_XG_MNT_INTR_WIDTH 1 #define FSF_AZ_GLB_EV_XFP_PHY0_INTR_LBN 10 #define FSF_AZ_GLB_EV_XFP_PHY0_INTR_WIDTH 1 #define FSF_AZ_GLB_EV_XG_PHY0_INTR_LBN 9 #define FSF_AZ_GLB_EV_XG_PHY0_INTR_WIDTH 1 #define FSF_AZ_GLB_EV_G_PHY0_INTR_LBN 7 #define FSF_AZ_GLB_EV_G_PHY0_INTR_WIDTH 1 /* FS_RX_EV */ #define FSF_CZ_RX_EV_PKT_NOT_PARSED_LBN 58 #define FSF_CZ_RX_EV_PKT_NOT_PARSED_WIDTH 1 #define FSF_CZ_RX_EV_IPV6_PKT_LBN 57 #define FSF_CZ_RX_EV_IPV6_PKT_WIDTH 1 #define FSF_AZ_RX_EV_PKT_OK_LBN 56 #define FSF_AZ_RX_EV_PKT_OK_WIDTH 1 #define FSF_AZ_RX_EV_PAUSE_FRM_ERR_LBN 55 #define FSF_AZ_RX_EV_PAUSE_FRM_ERR_WIDTH 1 #define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_LBN 54 #define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_WIDTH 1 #define FSF_AZ_RX_EV_IP_FRAG_ERR_LBN 53 #define FSF_AZ_RX_EV_IP_FRAG_ERR_WIDTH 1 #define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_LBN 52 #define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 1 #define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_LBN 51 #define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 1 #define FSF_AZ_RX_EV_ETH_CRC_ERR_LBN 50 #define FSF_AZ_RX_EV_ETH_CRC_ERR_WIDTH 1 #define FSF_AZ_RX_EV_FRM_TRUNC_LBN 49 #define FSF_AZ_RX_EV_FRM_TRUNC_WIDTH 1 #define FSF_AZ_RX_EV_TOBE_DISC_LBN 47 #define FSF_AZ_RX_EV_TOBE_DISC_WIDTH 1 #define FSF_AZ_RX_EV_PKT_TYPE_LBN 44 #define FSF_AZ_RX_EV_PKT_TYPE_WIDTH 3 #define FSE_AZ_RX_EV_PKT_TYPE_VLAN_JUMBO 5 #define FSE_AZ_RX_EV_PKT_TYPE_VLAN_LLC 4 #define FSE_AZ_RX_EV_PKT_TYPE_VLAN 3 #define FSE_AZ_RX_EV_PKT_TYPE_JUMBO 2 #define FSE_AZ_RX_EV_PKT_TYPE_LLC 1 #define FSE_AZ_RX_EV_PKT_TYPE_ETH 0 #define FSF_AZ_RX_EV_HDR_TYPE_LBN 42 #define FSF_AZ_RX_EV_HDR_TYPE_WIDTH 2 #define FSE_AZ_RX_EV_HDR_TYPE_OTHER 3 #define FSE_AZ_RX_EV_HDR_TYPE_IPV4_OTHER 2 #define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER 2 #define FSE_AZ_RX_EV_HDR_TYPE_IPV4_UDP 1 #define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP 1 #define FSE_AZ_RX_EV_HDR_TYPE_IPV4_TCP 0 #define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP 0 #define FSF_AZ_RX_EV_DESC_Q_EMPTY_LBN 41 #define FSF_AZ_RX_EV_DESC_Q_EMPTY_WIDTH 1 #define FSF_AZ_RX_EV_MCAST_HASH_MATCH_LBN 40 #define FSF_AZ_RX_EV_MCAST_HASH_MATCH_WIDTH 1 #define FSF_AZ_RX_EV_MCAST_PKT_LBN 39 #define FSF_AZ_RX_EV_MCAST_PKT_WIDTH 1 #define FSF_AA_RX_EV_RECOVERY_FLAG_LBN 37 #define FSF_AA_RX_EV_RECOVERY_FLAG_WIDTH 1 #define FSF_AZ_RX_EV_Q_LABEL_LBN 32 #define FSF_AZ_RX_EV_Q_LABEL_WIDTH 5 #define FSF_AZ_RX_EV_JUMBO_CONT_LBN 31 #define FSF_AZ_RX_EV_JUMBO_CONT_WIDTH 1 #define FSF_AZ_RX_EV_PORT_LBN 30 #define FSF_AZ_RX_EV_PORT_WIDTH 1 #define FSF_AZ_RX_EV_BYTE_CNT_LBN 16 #define FSF_AZ_RX_EV_BYTE_CNT_WIDTH 14 #define FSF_AZ_RX_EV_SOP_LBN 15 #define FSF_AZ_RX_EV_SOP_WIDTH 1 #define FSF_AZ_RX_EV_ISCSI_PKT_OK_LBN 14 #define FSF_AZ_RX_EV_ISCSI_PKT_OK_WIDTH 1 #define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_LBN 13 #define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_WIDTH 1 #define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_LBN 12 #define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_WIDTH 1 #define FSF_AZ_RX_EV_DESC_PTR_LBN 0 #define FSF_AZ_RX_EV_DESC_PTR_WIDTH 12 /* FS_RX_KER_DESC */ #define FSF_AZ_RX_KER_BUF_SIZE_LBN 48 #define FSF_AZ_RX_KER_BUF_SIZE_WIDTH 14 #define FSF_AZ_RX_KER_BUF_REGION_LBN 46 #define FSF_AZ_RX_KER_BUF_REGION_WIDTH 2 #define FSF_AZ_RX_KER_BUF_ADDR_LBN 0 #define FSF_AZ_RX_KER_BUF_ADDR_WIDTH 46 #define FSF_AZ_RX_KER_BUF_ADDR_DW0_LBN 0 #define FSF_AZ_RX_KER_BUF_ADDR_DW0_WIDTH 32 #define FSF_AZ_RX_KER_BUF_ADDR_DW1_LBN 32 #define FSF_AZ_RX_KER_BUF_ADDR_DW1_WIDTH 14 /* FS_RX_USER_DESC */ #define FSF_AZ_RX_USER_2BYTE_OFFSET_LBN 20 #define FSF_AZ_RX_USER_2BYTE_OFFSET_WIDTH 12 #define FSF_AZ_RX_USER_BUF_ID_LBN 0 #define FSF_AZ_RX_USER_BUF_ID_WIDTH 20 /* FS_TX_EV */ #define FSF_AZ_TX_EV_PKT_ERR_LBN 38 #define FSF_AZ_TX_EV_PKT_ERR_WIDTH 1 #define FSF_AZ_TX_EV_PKT_TOO_BIG_LBN 37 #define FSF_AZ_TX_EV_PKT_TOO_BIG_WIDTH 1 #define FSF_AZ_TX_EV_Q_LABEL_LBN 32 #define FSF_AZ_TX_EV_Q_LABEL_WIDTH 5 #define FSF_AZ_TX_EV_PORT_LBN 16 #define FSF_AZ_TX_EV_PORT_WIDTH 1 #define FSF_AZ_TX_EV_WQ_FF_FULL_LBN 15 #define FSF_AZ_TX_EV_WQ_FF_FULL_WIDTH 1 #define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_LBN 14 #define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_WIDTH 1 #define FSF_AZ_TX_EV_COMP_LBN 12 #define FSF_AZ_TX_EV_COMP_WIDTH 1 #define FSF_AZ_TX_EV_DESC_PTR_LBN 0 #define FSF_AZ_TX_EV_DESC_PTR_WIDTH 12 /* FS_TX_KER_DESC */ #define FSF_AZ_TX_KER_CONT_LBN 62 #define FSF_AZ_TX_KER_CONT_WIDTH 1 #define FSF_AZ_TX_KER_BYTE_COUNT_LBN 48 #define FSF_AZ_TX_KER_BYTE_COUNT_WIDTH 14 #define FSF_AZ_TX_KER_BUF_REGION_LBN 46 #define FSF_AZ_TX_KER_BUF_REGION_WIDTH 2 #define FSF_AZ_TX_KER_BUF_ADDR_LBN 0 #define FSF_AZ_TX_KER_BUF_ADDR_WIDTH 46 #define FSF_AZ_TX_KER_BUF_ADDR_DW0_LBN 0 #define FSF_AZ_TX_KER_BUF_ADDR_DW0_WIDTH 32 #define FSF_AZ_TX_KER_BUF_ADDR_DW1_LBN 32 #define FSF_AZ_TX_KER_BUF_ADDR_DW1_WIDTH 14 /* FS_TX_USER_DESC */ #define FSF_AZ_TX_USER_SW_EV_EN_LBN 48 #define FSF_AZ_TX_USER_SW_EV_EN_WIDTH 1 #define FSF_AZ_TX_USER_CONT_LBN 46 #define FSF_AZ_TX_USER_CONT_WIDTH 1 #define FSF_AZ_TX_USER_BYTE_CNT_LBN 33 #define FSF_AZ_TX_USER_BYTE_CNT_WIDTH 13 #define FSF_AZ_TX_USER_BUF_ID_LBN 13 #define FSF_AZ_TX_USER_BUF_ID_WIDTH 20 #define FSF_AZ_TX_USER_BYTE_OFS_LBN 0 #define FSF_AZ_TX_USER_BYTE_OFS_WIDTH 13 /* FS_USER_EV */ #define FSF_CZ_USER_QID_LBN 32 #define FSF_CZ_USER_QID_WIDTH 10 #define FSF_CZ_USER_EV_REG_VALUE_LBN 0 #define FSF_CZ_USER_EV_REG_VALUE_WIDTH 32 /* FS_NET_IVEC */ #define FSF_AZ_NET_IVEC_FATAL_INT_LBN 64 #define FSF_AZ_NET_IVEC_FATAL_INT_WIDTH 1 #define FSF_AZ_NET_IVEC_INT_Q_LBN 40 #define FSF_AZ_NET_IVEC_INT_Q_WIDTH 4 #define FSF_AZ_NET_IVEC_INT_FLAG_LBN 32 #define FSF_AZ_NET_IVEC_INT_FLAG_WIDTH 1 #define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_LBN 1 #define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_WIDTH 1 #define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_LBN 0 #define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_WIDTH 1 /* DRIVER_EV */ /* Sub-fields of an RX flush completion event */ #define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_LBN 12 #define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_WIDTH 1 #define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_LBN 0 #define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_WIDTH 12 /************************************************************************** * * Falcon non-volatile configuration * ************************************************************************** */ -#define FR_AZ_TX_PACE_TBL_OFST FR_BZ_TX_PACE_TBL_OFST +#define FR_AZ_TX_PACE_TBL_OFST FR_BZ_TX_PACE_TBL_OFST #ifdef __cplusplus } #endif #endif /* _SYS_EFX_REGS_H */ Property changes on: head/sys/dev/sfxge/common/efx_regs.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_regs_ef10.h =================================================================== --- head/sys/dev/sfxge/common/efx_regs_ef10.h (revision 283513) +++ head/sys/dev/sfxge/common/efx_regs_ef10.h (revision 283514) @@ -1,2816 +1,2942 @@ /*- - * Copyright 2007-2010 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2007-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + * * $FreeBSD$ */ #ifndef _SYS_EFX_EF10_REGS_H #define _SYS_EFX_EF10_REGS_H #ifdef __cplusplus extern "C" { #endif /* * BIU_HW_REV_ID_REG(32bit): - * + * */ -#define ER_DZ_BIU_HW_REV_ID_REG 0x00000000 +#define ER_DZ_BIU_HW_REV_ID_REG_OFST 0x00000000 /* hunta0=pcie_pf_bar2 */ +#define ER_DZ_BIU_HW_REV_ID_REG_RESET 0xeb14face + #define ERF_DZ_HW_REV_ID_LBN 0 #define ERF_DZ_HW_REV_ID_WIDTH 32 /* * BIU_MC_SFT_STATUS_REG(32bit): - * + * */ -#define ER_DZ_BIU_MC_SFT_STATUS_REG 0x00000010 +#define ER_DZ_BIU_MC_SFT_STATUS_REG_OFST 0x00000010 /* hunta0=pcie_pf_bar2 */ #define ER_DZ_BIU_MC_SFT_STATUS_REG_STEP 4 #define ER_DZ_BIU_MC_SFT_STATUS_REG_ROWS 8 +#define ER_DZ_BIU_MC_SFT_STATUS_REG_RESET 0x1111face + #define ERF_DZ_MC_SFT_STATUS_LBN 0 #define ERF_DZ_MC_SFT_STATUS_WIDTH 32 /* * BIU_INT_ISR_REG(32bit): - * + * */ -#define ER_DZ_BIU_INT_ISR_REG 0x00000090 +#define ER_DZ_BIU_INT_ISR_REG_OFST 0x00000090 /* hunta0=pcie_pf_bar2 */ +#define ER_DZ_BIU_INT_ISR_REG_RESET 0x0 + #define ERF_DZ_ISR_REG_LBN 0 #define ERF_DZ_ISR_REG_WIDTH 32 /* * MC_DB_LWRD_REG(32bit): - * + * */ -#define ER_DZ_MC_DB_LWRD_REG 0x00000200 +#define ER_DZ_MC_DB_LWRD_REG_OFST 0x00000200 /* hunta0=pcie_pf_bar2 */ +#define ER_DZ_MC_DB_LWRD_REG_RESET 0x0 + #define ERF_DZ_MC_DOORBELL_L_LBN 0 #define ERF_DZ_MC_DOORBELL_L_WIDTH 32 /* * MC_DB_HWRD_REG(32bit): - * + * */ -#define ER_DZ_MC_DB_HWRD_REG 0x00000204 +#define ER_DZ_MC_DB_HWRD_REG_OFST 0x00000204 /* hunta0=pcie_pf_bar2 */ +#define ER_DZ_MC_DB_HWRD_REG_RESET 0x0 + #define ERF_DZ_MC_DOORBELL_H_LBN 0 #define ERF_DZ_MC_DOORBELL_H_WIDTH 32 /* * EVQ_RPTR_REG(32bit): - * + * */ -#define ER_DZ_EVQ_RPTR_REG 0x00000400 +#define ER_DZ_EVQ_RPTR_REG_OFST 0x00000400 /* hunta0=pcie_pf_bar2 */ -#define ER_DZ_EVQ_RPTR_REG_STEP 4096 +#define ER_DZ_EVQ_RPTR_REG_STEP 8192 #define ER_DZ_EVQ_RPTR_REG_ROWS 2048 +#define ER_DZ_EVQ_RPTR_REG_RESET 0x0 + #define ERF_DZ_EVQ_RPTR_VLD_LBN 15 #define ERF_DZ_EVQ_RPTR_VLD_WIDTH 1 #define ERF_DZ_EVQ_RPTR_LBN 0 #define ERF_DZ_EVQ_RPTR_WIDTH 15 /* * EVQ_TMR_REG(32bit): - * + * */ -#define ER_DZ_EVQ_TMR_REG 0x00000420 +#define ER_DZ_EVQ_TMR_REG_OFST 0x00000420 /* hunta0=pcie_pf_bar2 */ -#define ER_DZ_EVQ_TMR_REG_STEP 4096 +#define ER_DZ_EVQ_TMR_REG_STEP 8192 #define ER_DZ_EVQ_TMR_REG_ROWS 2048 +#define ER_DZ_EVQ_TMR_REG_RESET 0x0 + #define ERF_DZ_TC_TIMER_MODE_LBN 14 #define ERF_DZ_TC_TIMER_MODE_WIDTH 2 #define ERF_DZ_TC_TIMER_VAL_LBN 0 #define ERF_DZ_TC_TIMER_VAL_WIDTH 14 /* * RX_DESC_UPD_REG(32bit): - * + * */ -#define ER_DZ_RX_DESC_UPD_REG 0x00000830 +#define ER_DZ_RX_DESC_UPD_REG_OFST 0x00000830 /* hunta0=pcie_pf_bar2 */ -#define ER_DZ_RX_DESC_UPD_REG_STEP 4096 +#define ER_DZ_RX_DESC_UPD_REG_STEP 8192 #define ER_DZ_RX_DESC_UPD_REG_ROWS 2048 +#define ER_DZ_RX_DESC_UPD_REG_RESET 0x0 + #define ERF_DZ_RX_DESC_WPTR_LBN 0 #define ERF_DZ_RX_DESC_WPTR_WIDTH 12 /* - * TX_DESC_UPD_REG(76bit): - * + * TX_DESC_UPD_REG(96bit): + * */ -#define ER_DZ_TX_DESC_UPD_REG 0x00000a10 +#define ER_DZ_TX_DESC_UPD_REG_OFST 0x00000a10 /* hunta0=pcie_pf_bar2 */ -#define ER_DZ_TX_DESC_UPD_REG_STEP 4096 +#define ER_DZ_TX_DESC_UPD_REG_STEP 8192 #define ER_DZ_TX_DESC_UPD_REG_ROWS 2048 +#define ER_DZ_TX_DESC_UPD_REG_RESET 0x0 + +#define ERF_DZ_RSVD_LBN 76 +#define ERF_DZ_RSVD_WIDTH 20 #define ERF_DZ_TX_DESC_WPTR_LBN 64 #define ERF_DZ_TX_DESC_WPTR_WIDTH 12 #define ERF_DZ_TX_DESC_HWORD_LBN 32 #define ERF_DZ_TX_DESC_HWORD_WIDTH 32 #define ERF_DZ_TX_DESC_LWORD_LBN 0 #define ERF_DZ_TX_DESC_LWORD_WIDTH 32 +/* + * The workaround for bug 35388 requires multiplexing writes through + * the ERF_DZ_TX_DESC_WPTR address. + * TX_DESC_UPD: 0ppppppppppp (bit 11 lost) + * EVQ_RPTR: 1000hhhhhhhh, 1001llllllll (split into high and low bits) + * EVQ_TMR: 11mmvvvvvvvv (bits 8:13 of value lost) + */ +#define ER_DD_EVQ_INDIRECT_OFST (ER_DZ_TX_DESC_UPD_REG_OFST + 2 * 4) +#define ER_DD_EVQ_INDIRECT_STEP ER_DZ_TX_DESC_UPD_REG_STEP +#define ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8 +#define ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4 +#define EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8 +#define EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9 +#define ERF_DD_EVQ_IND_RPTR_LBN 0 +#define ERF_DD_EVQ_IND_RPTR_WIDTH 8 +#define ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10 +#define ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2 +#define EFE_DD_EVQ_IND_TIMER_FLAGS 3 +#define ERF_DD_EVQ_IND_TIMER_MODE_LBN 8 +#define ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2 +#define ERF_DD_EVQ_IND_TIMER_VAL_LBN 0 +#define ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8 + /* ES_DRIVER_EV */ #define ESF_DZ_DRV_CODE_LBN 60 #define ESF_DZ_DRV_CODE_WIDTH 4 #define ESF_DZ_DRV_SUB_CODE_LBN 56 #define ESF_DZ_DRV_SUB_CODE_WIDTH 4 -#define ESE_DZ_DRV_TIMER_EV 10 -#define ESE_DZ_DRV_WAKE_UP_EV 6 +#define ESE_DZ_DRV_TIMER_EV 3 +#define ESE_DZ_DRV_START_UP_EV 2 +#define ESE_DZ_DRV_WAKE_UP_EV 1 #define ESF_DZ_DRV_SUB_DATA_DW0_LBN 0 #define ESF_DZ_DRV_SUB_DATA_DW0_WIDTH 32 #define ESF_DZ_DRV_SUB_DATA_DW1_LBN 32 #define ESF_DZ_DRV_SUB_DATA_DW1_WIDTH 24 #define ESF_DZ_DRV_SUB_DATA_LBN 0 #define ESF_DZ_DRV_SUB_DATA_WIDTH 56 #define ESF_DZ_DRV_EVQ_ID_LBN 0 #define ESF_DZ_DRV_EVQ_ID_WIDTH 14 #define ESF_DZ_DRV_TMR_ID_LBN 0 #define ESF_DZ_DRV_TMR_ID_WIDTH 14 /* ES_EVENT_ENTRY */ #define ESF_DZ_EV_CODE_LBN 60 #define ESF_DZ_EV_CODE_WIDTH 4 #define ESE_DZ_EV_CODE_MCDI_EV 12 #define ESE_DZ_EV_CODE_DRIVER_EV 5 #define ESE_DZ_EV_CODE_TX_EV 2 #define ESE_DZ_EV_CODE_RX_EV 0 #define ESE_DZ_OTHER other #define ESF_DZ_EV_DATA_DW0_LBN 0 #define ESF_DZ_EV_DATA_DW0_WIDTH 32 #define ESF_DZ_EV_DATA_DW1_LBN 32 #define ESF_DZ_EV_DATA_DW1_WIDTH 28 #define ESF_DZ_EV_DATA_LBN 0 #define ESF_DZ_EV_DATA_WIDTH 60 /* ES_FF_UMSG_CPU2DL_DESC_FETCH */ -#define ESF_DZ_C2DDF_DSCR_CACHE_RPTR_LBN 112 +#define ESF_DZ_C2DDF_DSCR_CACHE_RPTR_LBN 208 #define ESF_DZ_C2DDF_DSCR_CACHE_RPTR_WIDTH 6 -#define ESF_DZ_C2DDF_QID_LBN 96 +#define ESF_DZ_C2DDF_QID_LBN 160 #define ESF_DZ_C2DDF_QID_WIDTH 11 #define ESF_DZ_C2DDF_DSCR_BASE_PAGE_ID_LBN 64 #define ESF_DZ_C2DDF_DSCR_BASE_PAGE_ID_WIDTH 18 #define ESF_DZ_C2DDF_DSCR_HW_RPTR_LBN 48 #define ESF_DZ_C2DDF_DSCR_HW_RPTR_WIDTH 12 #define ESF_DZ_C2DDF_DSCR_HW_WPTR_LBN 32 #define ESF_DZ_C2DDF_DSCR_HW_WPTR_WIDTH 12 #define ESF_DZ_C2DDF_OID_LBN 16 #define ESF_DZ_C2DDF_OID_WIDTH 12 #define ESF_DZ_C2DDF_DSCR_SIZE_LBN 13 #define ESF_DZ_C2DDF_DSCR_SIZE_WIDTH 3 #define ESE_DZ_C2DDF_DSCR_SIZE_512 7 #define ESE_DZ_C2DDF_DSCR_SIZE_1K 6 #define ESE_DZ_C2DDF_DSCR_SIZE_2K 5 #define ESE_DZ_C2DDF_DSCR_SIZE_4K 4 #define ESF_DZ_C2DDF_BIU_ARGS_LBN 0 #define ESF_DZ_C2DDF_BIU_ARGS_WIDTH 13 /* ES_FF_UMSG_CPU2DL_DESC_PUSH */ +#define ESF_DZ_C2DDP_DSCR_HW_RPTR_LBN 224 +#define ESF_DZ_C2DDP_DSCR_HW_RPTR_WIDTH 12 #define ESF_DZ_C2DDP_DESC_DW0_LBN 128 #define ESF_DZ_C2DDP_DESC_DW0_WIDTH 32 #define ESF_DZ_C2DDP_DESC_DW1_LBN 160 #define ESF_DZ_C2DDP_DESC_DW1_WIDTH 32 #define ESF_DZ_C2DDP_DESC_LBN 128 #define ESF_DZ_C2DDP_DESC_WIDTH 64 -#define ESF_DZ_C2DDP_QID_LBN 96 +#define ESF_DZ_C2DDP_QID_LBN 64 #define ESF_DZ_C2DDP_QID_WIDTH 11 -#define ESF_DZ_C2DDP_DSCR_HW_RPTR_LBN 48 -#define ESF_DZ_C2DDP_DSCR_HW_RPTR_WIDTH 12 #define ESF_DZ_C2DDP_DSCR_HW_WPTR_LBN 32 #define ESF_DZ_C2DDP_DSCR_HW_WPTR_WIDTH 12 #define ESF_DZ_C2DDP_OID_LBN 16 #define ESF_DZ_C2DDP_OID_WIDTH 12 #define ESF_DZ_C2DDP_DSCR_SIZE_LBN 0 #define ESF_DZ_C2DDP_DSCR_SIZE_WIDTH 3 #define ESE_DZ_C2DDF_DSCR_SIZE_512 7 #define ESE_DZ_C2DDF_DSCR_SIZE_1K 6 #define ESE_DZ_C2DDF_DSCR_SIZE_2K 5 #define ESE_DZ_C2DDF_DSCR_SIZE_4K 4 /* ES_FF_UMSG_CPU2DL_GPRD */ #define ESF_DZ_C2DG_ENCODED_HOST_ADDR_DW0_LBN 64 #define ESF_DZ_C2DG_ENCODED_HOST_ADDR_DW0_WIDTH 32 #define ESF_DZ_C2DG_ENCODED_HOST_ADDR_DW1_LBN 96 #define ESF_DZ_C2DG_ENCODED_HOST_ADDR_DW1_WIDTH 16 #define ESF_DZ_C2DG_ENCODED_HOST_ADDR_LBN 64 #define ESF_DZ_C2DG_ENCODED_HOST_ADDR_WIDTH 48 #define ESF_DZ_C2DG_SMC_ADDR_LBN 16 #define ESF_DZ_C2DG_SMC_ADDR_WIDTH 16 #define ESF_DZ_C2DG_BIU_ARGS_LBN 0 #define ESF_DZ_C2DG_BIU_ARGS_WIDTH 14 /* ES_FF_UMSG_CPU2EV_SOFT */ #define ESF_DZ_C2ES_TBD_LBN 0 #define ESF_DZ_C2ES_TBD_WIDTH 1 /* ES_FF_UMSG_CPU2EV_TXCMPLT */ -#define ESF_DZ_C2ET_EV_SOFT0_LBN 32 -#define ESF_DZ_C2ET_EV_SOFT0_WIDTH 16 +#define ESF_DZ_C2ET_EV_SOFT2_LBN 48 +#define ESF_DZ_C2ET_EV_SOFT2_WIDTH 16 +#define ESF_DZ_C2ET_EV_CODE_LBN 42 +#define ESF_DZ_C2ET_EV_CODE_WIDTH 4 +#define ESF_DZ_C2ET_EV_OVERRIDE_HOLDOFF_LBN 41 +#define ESF_DZ_C2ET_EV_OVERRIDE_HOLDOFF_WIDTH 1 +#define ESF_DZ_C2ET_EV_DROP_EVENT_LBN 40 +#define ESF_DZ_C2ET_EV_DROP_EVENT_WIDTH 1 +#define ESF_DZ_C2ET_EV_CAN_MERGE_LBN 39 +#define ESF_DZ_C2ET_EV_CAN_MERGE_WIDTH 1 +#define ESF_DZ_C2ET_EV_SOFT1_LBN 32 +#define ESF_DZ_C2ET_EV_SOFT1_WIDTH 7 #define ESF_DZ_C2ET_DSCR_IDX_LBN 16 #define ESF_DZ_C2ET_DSCR_IDX_WIDTH 16 #define ESF_DZ_C2ET_EV_QID_LBN 5 #define ESF_DZ_C2ET_EV_QID_WIDTH 11 #define ESF_DZ_C2ET_EV_QLABEL_LBN 0 #define ESF_DZ_C2ET_EV_QLABEL_WIDTH 5 /* ES_FF_UMSG_CPU2RXDP_INGR_BUFOP */ #define ESF_DZ_C2RIB_EV_DISABLE_LBN 191 #define ESF_DZ_C2RIB_EV_DISABLE_WIDTH 1 #define ESF_DZ_C2RIB_EV_SOFT_LBN 188 #define ESF_DZ_C2RIB_EV_SOFT_WIDTH 3 #define ESF_DZ_C2RIB_EV_DESC_PTR_LBN 176 #define ESF_DZ_C2RIB_EV_DESC_PTR_WIDTH 12 #define ESF_DZ_C2RIB_EV_ARG1_LBN 160 #define ESF_DZ_C2RIB_EV_ARG1_WIDTH 16 #define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_DW0_LBN 64 #define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_DW0_WIDTH 32 #define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_DW1_LBN 96 #define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_DW1_WIDTH 16 #define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_LBN 64 #define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_WIDTH 48 #define ESF_DZ_C2RIB_BIU_ARGS_LBN 16 #define ESF_DZ_C2RIB_BIU_ARGS_WIDTH 13 #define ESF_DZ_C2RIB_EV_QID_LBN 5 #define ESF_DZ_C2RIB_EV_QID_WIDTH 11 #define ESF_DZ_C2RIB_EV_QLABEL_LBN 0 #define ESF_DZ_C2RIB_EV_QLABEL_WIDTH 5 /* ES_FF_UMSG_CPU2RXDP_INGR_PDISP */ #define ESF_DZ_C2RIP_BUF_LEN_LBN 240 #define ESF_DZ_C2RIP_BUF_LEN_WIDTH 16 #define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_DW0_LBN 192 #define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_DW0_WIDTH 32 #define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_DW1_LBN 224 #define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_DW1_WIDTH 16 #define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_LBN 192 #define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_WIDTH 48 #define ESF_DZ_C2RIP_EV_DISABLE_LBN 191 #define ESF_DZ_C2RIP_EV_DISABLE_WIDTH 1 #define ESF_DZ_C2RIP_EV_SOFT_LBN 188 #define ESF_DZ_C2RIP_EV_SOFT_WIDTH 3 #define ESF_DZ_C2RIP_EV_DESC_PTR_LBN 176 #define ESF_DZ_C2RIP_EV_DESC_PTR_WIDTH 12 #define ESF_DZ_C2RIP_EV_ARG1_LBN 160 #define ESF_DZ_C2RIP_EV_ARG1_WIDTH 16 #define ESF_DZ_C2RIP_UPD_CRC_MODE_LBN 157 #define ESF_DZ_C2RIP_UPD_CRC_MODE_WIDTH 3 -#define ESE_DZ_C2RIP_FCOIP_MPA 5 #define ESE_DZ_C2RIP_FCOIP_FCOE 4 #define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 #define ESE_DZ_C2RIP_ISCSI_HDR 2 #define ESE_DZ_C2RIP_FCOE 1 #define ESE_DZ_C2RIP_OFF 0 #define ESF_DZ_C2RIP_BIU_ARGS_LBN 144 #define ESF_DZ_C2RIP_BIU_ARGS_WIDTH 13 #define ESF_DZ_C2RIP_EV_QID_LBN 133 #define ESF_DZ_C2RIP_EV_QID_WIDTH 11 #define ESF_DZ_C2RIP_EV_QLABEL_LBN 128 #define ESF_DZ_C2RIP_EV_QLABEL_WIDTH 5 #define ESF_DZ_C2RIP_PEDIT_DELTA_LBN 104 #define ESF_DZ_C2RIP_PEDIT_DELTA_WIDTH 8 #define ESF_DZ_C2RIP_PYLOAD_OFST_LBN 96 #define ESF_DZ_C2RIP_PYLOAD_OFST_WIDTH 8 #define ESF_DZ_C2RIP_L4_HDR_OFST_LBN 88 #define ESF_DZ_C2RIP_L4_HDR_OFST_WIDTH 8 #define ESF_DZ_C2RIP_L3_HDR_OFST_LBN 80 #define ESF_DZ_C2RIP_L3_HDR_OFST_WIDTH 8 #define ESF_DZ_C2RIP_IS_UDP_LBN 69 #define ESF_DZ_C2RIP_IS_UDP_WIDTH 1 #define ESF_DZ_C2RIP_IS_TCP_LBN 68 #define ESF_DZ_C2RIP_IS_TCP_WIDTH 1 #define ESF_DZ_C2RIP_IS_IPV6_LBN 67 #define ESF_DZ_C2RIP_IS_IPV6_WIDTH 1 #define ESF_DZ_C2RIP_IS_IPV4_LBN 66 #define ESF_DZ_C2RIP_IS_IPV4_WIDTH 1 #define ESF_DZ_C2RIP_IS_FCOE_LBN 65 #define ESF_DZ_C2RIP_IS_FCOE_WIDTH 1 #define ESF_DZ_C2RIP_PARSE_INCOMP_LBN 64 #define ESF_DZ_C2RIP_PARSE_INCOMP_WIDTH 1 #define ESF_DZ_C2RIP_FINFO_WRD3_LBN 48 #define ESF_DZ_C2RIP_FINFO_WRD3_WIDTH 16 #define ESF_DZ_C2RIP_FINFO_WRD2_LBN 32 #define ESF_DZ_C2RIP_FINFO_WRD2_WIDTH 16 #define ESF_DZ_C2RIP_FINFO_WRD1_LBN 16 #define ESF_DZ_C2RIP_FINFO_WRD1_WIDTH 16 #define ESF_DZ_C2RIP_FINFO_SRCDST_LBN 0 #define ESF_DZ_C2RIP_FINFO_SRCDST_WIDTH 16 /* ES_FF_UMSG_CPU2RXDP_INGR_SOFT */ #define ESF_DZ_C2RIS_SOFT3_LBN 48 #define ESF_DZ_C2RIS_SOFT3_WIDTH 16 #define ESF_DZ_C2RIS_SOFT2_LBN 32 #define ESF_DZ_C2RIS_SOFT2_WIDTH 16 #define ESF_DZ_C2RIS_SOFT1_LBN 16 #define ESF_DZ_C2RIS_SOFT1_WIDTH 16 #define ESF_DZ_C2RIS_SOFT0_LBN 0 #define ESF_DZ_C2RIS_SOFT0_WIDTH 16 /* ES_FF_UMSG_CPU2SMC_BUFLKUP */ #define ESF_DZ_C2SB_PAGE_ID_LBN 16 #define ESF_DZ_C2SB_PAGE_ID_WIDTH 18 #define ESF_DZ_C2SB_EXP_PAGE_ID_LBN 0 #define ESF_DZ_C2SB_EXP_PAGE_ID_WIDTH 12 /* ES_FF_UMSG_CPU2SMC_DESCOP */ #define ESF_DZ_C2SD_LEN_LBN 112 #define ESF_DZ_C2SD_LEN_WIDTH 14 #define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW0_LBN 64 #define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW0_WIDTH 32 #define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW1_LBN 96 #define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW1_WIDTH 16 #define ESF_DZ_C2SD_ENCODED_HOST_ADDR_LBN 64 #define ESF_DZ_C2SD_ENCODED_HOST_ADDR_WIDTH 48 -#define ESF_DZ_C2SD_OFFSET_LBN 48 +#define ESF_DZ_C2SD_OFFSET_LBN 80 #define ESF_DZ_C2SD_OFFSET_WIDTH 8 #define ESF_DZ_C2SD_QID_LBN 32 #define ESF_DZ_C2SD_QID_WIDTH 11 #define ESF_DZ_C2SD_CONT_LBN 16 #define ESF_DZ_C2SD_CONT_WIDTH 1 #define ESF_DZ_C2SD_TYPE_LBN 0 #define ESF_DZ_C2SD_TYPE_WIDTH 1 /* ES_FF_UMSG_CPU2SMC_GPOP */ #define ESF_DZ_C2SG_DATA_DW0_LBN 64 #define ESF_DZ_C2SG_DATA_DW0_WIDTH 32 #define ESF_DZ_C2SG_DATA_DW1_LBN 96 #define ESF_DZ_C2SG_DATA_DW1_WIDTH 32 #define ESF_DZ_C2SG_DATA_LBN 64 #define ESF_DZ_C2SG_DATA_WIDTH 64 #define ESF_DZ_C2SG_SOFT_LBN 48 #define ESF_DZ_C2SG_SOFT_WIDTH 4 #define ESF_DZ_C2SG_REFLECT_LBN 32 #define ESF_DZ_C2SG_REFLECT_WIDTH 1 #define ESF_DZ_C2SG_ADDR_LBN 0 #define ESF_DZ_C2SG_ADDR_WIDTH 16 /* ES_FF_UMSG_CPU2TXDP_DMA_BUFREQ */ #define ESF_DZ_C2TDB_BUF_LEN_LBN 176 #define ESF_DZ_C2TDB_BUF_LEN_WIDTH 16 #define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_DW0_LBN 128 #define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_DW0_WIDTH 32 #define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_DW1_LBN 160 #define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_DW1_WIDTH 16 #define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_LBN 128 #define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_WIDTH 48 #define ESF_DZ_C2TDB_SOFT_LBN 112 #define ESF_DZ_C2TDB_SOFT_WIDTH 14 #define ESF_DZ_C2TDB_DESC_IDX_LBN 96 #define ESF_DZ_C2TDB_DESC_IDX_WIDTH 16 #define ESF_DZ_C2TDB_UPD_CRC_MODE_LBN 93 #define ESF_DZ_C2TDB_UPD_CRC_MODE_WIDTH 3 -#define ESE_DZ_C2RIP_FCOIP_MPA 5 #define ESE_DZ_C2RIP_FCOIP_FCOE 4 #define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 #define ESE_DZ_C2RIP_ISCSI_HDR 2 #define ESE_DZ_C2RIP_FCOE 1 #define ESE_DZ_C2RIP_OFF 0 #define ESF_DZ_C2TDB_BIU_ARGS_LBN 80 #define ESF_DZ_C2TDB_BIU_ARGS_WIDTH 13 #define ESF_DZ_C2TDB_CONT_LBN 64 #define ESF_DZ_C2TDB_CONT_WIDTH 1 #define ESF_DZ_C2TDB_FINFO_WRD3_LBN 48 #define ESF_DZ_C2TDB_FINFO_WRD3_WIDTH 16 #define ESF_DZ_C2TDB_FINFO_WRD2_LBN 32 #define ESF_DZ_C2TDB_FINFO_WRD2_WIDTH 16 #define ESF_DZ_C2TDB_FINFO_WRD1_LBN 16 #define ESF_DZ_C2TDB_FINFO_WRD1_WIDTH 16 #define ESF_DZ_C2TDB_FINFO_SRCDST_LBN 0 #define ESF_DZ_C2TDB_FINFO_SRCDST_WIDTH 16 /* ES_FF_UMSG_CPU2TXDP_DMA_PKTABORT */ #define ESF_DZ_C2TDP_SOFT_LBN 48 #define ESF_DZ_C2TDP_SOFT_WIDTH 14 #define ESF_DZ_C2TDP_DESC_IDX_LBN 32 #define ESF_DZ_C2TDP_DESC_IDX_WIDTH 16 #define ESF_DZ_C2TDP_BIU_ARGS_LBN 16 #define ESF_DZ_C2TDP_BIU_ARGS_WIDTH 14 /* ES_FF_UMSG_CPU2TXDP_DMA_SOFT */ #define ESF_DZ_C2TDS_SOFT3_LBN 48 #define ESF_DZ_C2TDS_SOFT3_WIDTH 16 #define ESF_DZ_C2TDS_SOFT2_LBN 32 #define ESF_DZ_C2TDS_SOFT2_WIDTH 16 #define ESF_DZ_C2TDS_SOFT1_LBN 16 #define ESF_DZ_C2TDS_SOFT1_WIDTH 16 #define ESF_DZ_C2TDS_SOFT0_LBN 0 #define ESF_DZ_C2TDS_SOFT0_WIDTH 16 /* ES_FF_UMSG_CPU2TXDP_EGR */ +#define ESF_DZ_C2TE_RMON_SOFT_LBN 240 +#define ESF_DZ_C2TE_RMON_SOFT_WIDTH 1 +#define ESF_DZ_C2TE_VLAN_PRIO_LBN 224 +#define ESF_DZ_C2TE_VLAN_PRIO_WIDTH 3 +#define ESF_DZ_C2TE_VLAN_LBN 208 +#define ESF_DZ_C2TE_VLAN_WIDTH 1 +#define ESF_DZ_C2TE_QID_LBN 192 +#define ESF_DZ_C2TE_QID_WIDTH 11 #define ESF_DZ_C2TE_PEDIT_DELTA_LBN 168 #define ESF_DZ_C2TE_PEDIT_DELTA_WIDTH 8 #define ESF_DZ_C2TE_PYLOAD_OFST_LBN 160 #define ESF_DZ_C2TE_PYLOAD_OFST_WIDTH 8 #define ESF_DZ_C2TE_L4_HDR_OFST_LBN 152 #define ESF_DZ_C2TE_L4_HDR_OFST_WIDTH 8 #define ESF_DZ_C2TE_L3_HDR_OFST_LBN 144 #define ESF_DZ_C2TE_L3_HDR_OFST_WIDTH 8 #define ESF_DZ_C2TE_IS_UDP_LBN 133 #define ESF_DZ_C2TE_IS_UDP_WIDTH 1 #define ESF_DZ_C2TE_IS_TCP_LBN 132 #define ESF_DZ_C2TE_IS_TCP_WIDTH 1 #define ESF_DZ_C2TE_IS_IPV6_LBN 131 #define ESF_DZ_C2TE_IS_IPV6_WIDTH 1 #define ESF_DZ_C2TE_IS_IPV4_LBN 130 #define ESF_DZ_C2TE_IS_IPV4_WIDTH 1 #define ESF_DZ_C2TE_IS_FCOE_LBN 129 #define ESF_DZ_C2TE_IS_FCOE_WIDTH 1 #define ESF_DZ_C2TE_PARSE_INCOMP_LBN 128 #define ESF_DZ_C2TE_PARSE_INCOMP_WIDTH 1 -#define ESF_DZ_C2TE_PKT_LEN_LBN 112 -#define ESF_DZ_C2TE_PKT_LEN_WIDTH 16 -#define ESF_DZ_C2TE_UPD_TCPUDPCSUM_MODE_LBN 97 -#define ESF_DZ_C2TE_UPD_TCPUDPCSUM_MODE_WIDTH 1 -#define ESF_DZ_C2TE_UPD_IPCSUM_MODE_LBN 96 -#define ESF_DZ_C2TE_UPD_IPCSUM_MODE_WIDTH 1 -#define ESF_DZ_C2TE_UPD_CRC_MODE_LBN 93 +#define ESF_DZ_C2TE_UPD_CRC_MODE_LBN 98 #define ESF_DZ_C2TE_UPD_CRC_MODE_WIDTH 3 -#define ESE_DZ_C2RIP_FCOIP_MPA 5 #define ESE_DZ_C2RIP_FCOIP_FCOE 4 #define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 #define ESE_DZ_C2RIP_ISCSI_HDR 2 #define ESE_DZ_C2RIP_FCOE 1 #define ESE_DZ_C2RIP_OFF 0 +#define ESF_DZ_C2TE_UPD_TCPUDPCSUM_MODE_LBN 97 +#define ESF_DZ_C2TE_UPD_TCPUDPCSUM_MODE_WIDTH 1 +#define ESF_DZ_C2TE_UPD_IPCSUM_MODE_LBN 96 +#define ESF_DZ_C2TE_UPD_IPCSUM_MODE_WIDTH 1 +#define ESF_DZ_C2TE_PKT_LEN_LBN 64 +#define ESF_DZ_C2TE_PKT_LEN_WIDTH 16 #define ESF_DZ_C2TE_FINFO_WRD3_LBN 48 #define ESF_DZ_C2TE_FINFO_WRD3_WIDTH 16 #define ESF_DZ_C2TE_FINFO_WRD2_LBN 32 #define ESF_DZ_C2TE_FINFO_WRD2_WIDTH 16 #define ESF_DZ_C2TE_FINFO_WRD1_LBN 16 #define ESF_DZ_C2TE_FINFO_WRD1_WIDTH 16 #define ESF_DZ_C2TE_FINFO_SRCDST_LBN 0 #define ESF_DZ_C2TE_FINFO_SRCDST_WIDTH 16 /* ES_FF_UMSG_CPU2TXDP_EGR_SOFT */ #define ESF_DZ_C2TES_SOFT3_LBN 48 #define ESF_DZ_C2TES_SOFT3_WIDTH 16 #define ESF_DZ_C2TES_SOFT2_LBN 32 #define ESF_DZ_C2TES_SOFT2_WIDTH 16 #define ESF_DZ_C2TES_SOFT1_LBN 16 #define ESF_DZ_C2TES_SOFT1_WIDTH 16 #define ESF_DZ_C2TES_SOFT0_LBN 0 #define ESF_DZ_C2TES_SOFT0_WIDTH 16 /* ES_FF_UMSG_DL2CPU_DESC_FETCH */ #define ESF_DZ_D2CDF_REFL_DSCR_HW_WPTR_LBN 64 #define ESF_DZ_D2CDF_REFL_DSCR_HW_WPTR_WIDTH 12 #define ESF_DZ_D2CDF_FAIL_LBN 48 #define ESF_DZ_D2CDF_FAIL_WIDTH 1 #define ESF_DZ_D2CDF_QID_LBN 32 #define ESF_DZ_D2CDF_QID_WIDTH 11 #define ESF_DZ_D2CDF_NUM_DESC_LBN 16 #define ESF_DZ_D2CDF_NUM_DESC_WIDTH 7 #define ESF_DZ_D2CDF_NEW_DSCR_HW_RPTR_LBN 0 #define ESF_DZ_D2CDF_NEW_DSCR_HW_RPTR_WIDTH 12 /* ES_FF_UMSG_DL2CPU_GPRD */ #define ESF_DZ_D2CG_BIU_ARGS_LBN 0 #define ESF_DZ_D2CG_BIU_ARGS_WIDTH 14 /* ES_FF_UMSG_DPCPU_PACER_TXQ_D_R_I_REQ */ #define ESF_DZ_FRM_LEN_LBN 16 #define ESF_DZ_FRM_LEN_WIDTH 15 #define ESF_DZ_TXQ_ID_LBN 0 #define ESF_DZ_TXQ_ID_WIDTH 10 /* ES_FF_UMSG_PACER_BKT_TBL_RD_REQ */ #define ESF_DZ_BKT_ID_LBN 0 -#define ESF_DZ_BKT_ID_WIDTH 9 +#define ESF_DZ_BKT_ID_WIDTH 10 /* ES_FF_UMSG_PACER_BKT_TBL_RD_RSP */ #define ESF_DZ_DUE_TIME_LBN 80 #define ESF_DZ_DUE_TIME_WIDTH 16 #define ESF_DZ_LAST_FILL_TIME_LBN 64 #define ESF_DZ_LAST_FILL_TIME_WIDTH 16 #define ESF_DZ_RATE_REC_LBN 48 #define ESF_DZ_RATE_REC_WIDTH 16 #define ESF_DZ_RATE_LBN 32 #define ESF_DZ_RATE_WIDTH 16 #define ESF_DZ_FILL_LEVEL_LBN 16 #define ESF_DZ_FILL_LEVEL_WIDTH 16 #define ESF_DZ_IDLE_LBN 15 #define ESF_DZ_IDLE_WIDTH 1 #define ESF_DZ_USED_LBN 14 #define ESF_DZ_USED_WIDTH 1 #define ESF_DZ_MAX_FILL_REG_LBN 12 #define ESF_DZ_MAX_FILL_REG_WIDTH 2 #define ESF_DZ_BKT_ID_LBN 0 -#define ESF_DZ_BKT_ID_WIDTH 9 +#define ESF_DZ_BKT_ID_WIDTH 10 /* ES_FF_UMSG_PACER_BKT_TBL_WR_REQ */ #define ESF_DZ_RATE_REC_LBN 48 #define ESF_DZ_RATE_REC_WIDTH 16 #define ESF_DZ_RATE_LBN 32 #define ESF_DZ_RATE_WIDTH 16 #define ESF_DZ_FILL_LEVEL_LBN 16 #define ESF_DZ_FILL_LEVEL_WIDTH 16 #define ESF_DZ_IDLE_LBN 15 #define ESF_DZ_IDLE_WIDTH 1 #define ESF_DZ_USED_LBN 14 #define ESF_DZ_USED_WIDTH 1 #define ESF_DZ_MAX_FILL_REG_LBN 12 #define ESF_DZ_MAX_FILL_REG_WIDTH 2 #define ESF_DZ_BKT_ID_LBN 0 -#define ESF_DZ_BKT_ID_WIDTH 9 +#define ESF_DZ_BKT_ID_WIDTH 10 /* ES_FF_UMSG_PACER_TXQ_TBL_RD_REQ */ #define ESF_DZ_TXQ_ID_LBN 0 #define ESF_DZ_TXQ_ID_WIDTH 10 /* ES_FF_UMSG_PACER_TXQ_TBL_RD_RSP */ #define ESF_DZ_MAX_BKT2_LBN 112 -#define ESF_DZ_MAX_BKT2_WIDTH 9 +#define ESF_DZ_MAX_BKT2_WIDTH 10 #define ESF_DZ_MAX_BKT1_LBN 96 -#define ESF_DZ_MAX_BKT1_WIDTH 9 +#define ESF_DZ_MAX_BKT1_WIDTH 10 #define ESF_DZ_MAX_BKT0_LBN 80 -#define ESF_DZ_MAX_BKT0_WIDTH 9 +#define ESF_DZ_MAX_BKT0_WIDTH 10 #define ESF_DZ_MIN_BKT_LBN 64 -#define ESF_DZ_MIN_BKT_WIDTH 9 +#define ESF_DZ_MIN_BKT_WIDTH 10 #define ESF_DZ_LABEL_LBN 48 #define ESF_DZ_LABEL_WIDTH 4 #define ESF_DZ_PQ_FLAGS_LBN 32 #define ESF_DZ_PQ_FLAGS_WIDTH 3 #define ESF_DZ_DSBL_LBN 16 #define ESF_DZ_DSBL_WIDTH 1 #define ESF_DZ_TXQ_ID_LBN 0 #define ESF_DZ_TXQ_ID_WIDTH 10 /* ES_FF_UMSG_PACER_TXQ_TBL_WR_REQ */ #define ESF_DZ_MAX_BKT2_LBN 112 -#define ESF_DZ_MAX_BKT2_WIDTH 9 +#define ESF_DZ_MAX_BKT2_WIDTH 10 #define ESF_DZ_MAX_BKT1_LBN 96 -#define ESF_DZ_MAX_BKT1_WIDTH 9 +#define ESF_DZ_MAX_BKT1_WIDTH 10 #define ESF_DZ_MAX_BKT0_LBN 80 -#define ESF_DZ_MAX_BKT0_WIDTH 9 +#define ESF_DZ_MAX_BKT0_WIDTH 10 #define ESF_DZ_MIN_BKT_LBN 64 -#define ESF_DZ_MIN_BKT_WIDTH 9 +#define ESF_DZ_MIN_BKT_WIDTH 10 #define ESF_DZ_LABEL_LBN 48 #define ESF_DZ_LABEL_WIDTH 4 #define ESF_DZ_PQ_FLAGS_LBN 32 #define ESF_DZ_PQ_FLAGS_WIDTH 3 #define ESF_DZ_DSBL_LBN 16 #define ESF_DZ_DSBL_WIDTH 1 #define ESF_DZ_TXQ_ID_LBN 0 #define ESF_DZ_TXQ_ID_WIDTH 10 /* ES_FF_UMSG_PE */ #define ESF_DZ_PE_PKT_OFST_LBN 47 #define ESF_DZ_PE_PKT_OFST_WIDTH 17 #define ESF_DZ_PE_PEDIT_DELTA_LBN 40 #define ESF_DZ_PE_PEDIT_DELTA_WIDTH 8 #define ESF_DZ_PE_PYLOAD_OFST_LBN 32 #define ESF_DZ_PE_PYLOAD_OFST_WIDTH 8 #define ESF_DZ_PE_L4_HDR_OFST_LBN 24 #define ESF_DZ_PE_L4_HDR_OFST_WIDTH 8 #define ESF_DZ_PE_L3_HDR_OFST_LBN 16 #define ESF_DZ_PE_L3_HDR_OFST_WIDTH 8 #define ESF_DZ_PE_HAVE_UDP_HDR_LBN 5 #define ESF_DZ_PE_HAVE_UDP_HDR_WIDTH 1 #define ESF_DZ_PE_HAVE_TCP_HDR_LBN 4 #define ESF_DZ_PE_HAVE_TCP_HDR_WIDTH 1 #define ESF_DZ_PE_HAVE_IPV6_HDR_LBN 3 #define ESF_DZ_PE_HAVE_IPV6_HDR_WIDTH 1 #define ESF_DZ_PE_HAVE_IPV4_HDR_LBN 2 #define ESF_DZ_PE_HAVE_IPV4_HDR_WIDTH 1 #define ESF_DZ_PE_HAVE_FCOE_LBN 1 #define ESF_DZ_PE_HAVE_FCOE_WIDTH 1 #define ESF_DZ_PE_PARSE_INCOMP_LBN 0 #define ESF_DZ_PE_PARSE_INCOMP_WIDTH 1 /* ES_FF_UMSG_RXDP_EGR2CPU_SOFT */ #define ESF_DZ_RE2CS_SOFT3_LBN 48 #define ESF_DZ_RE2CS_SOFT3_WIDTH 16 #define ESF_DZ_RE2CS_SOFT2_LBN 32 #define ESF_DZ_RE2CS_SOFT2_WIDTH 16 #define ESF_DZ_RE2CS_SOFT1_LBN 16 #define ESF_DZ_RE2CS_SOFT1_WIDTH 16 #define ESF_DZ_RE2CS_SOFT0_LBN 0 #define ESF_DZ_RE2CS_SOFT0_WIDTH 16 /* ES_FF_UMSG_RXDP_INGR2CPU */ +#define ESF_DZ_RI2C_QUEUE_ID_LBN 224 +#define ESF_DZ_RI2C_QUEUE_ID_WIDTH 11 #define ESF_DZ_RI2C_LEN_LBN 208 #define ESF_DZ_RI2C_LEN_WIDTH 16 -#define ESF_DZ_RI2C_L4_CLASS_LBN 202 +#define ESF_DZ_RI2C_L4_CLASS_LBN 205 #define ESF_DZ_RI2C_L4_CLASS_WIDTH 3 -#define ESF_DZ_RI2C_L3_CLASS_LBN 199 +#define ESF_DZ_RI2C_L3_CLASS_LBN 202 #define ESF_DZ_RI2C_L3_CLASS_WIDTH 3 -#define ESF_DZ_RI2C_ETHTAG_CLASS_LBN 196 +#define ESF_DZ_RI2C_ETHTAG_CLASS_LBN 199 #define ESF_DZ_RI2C_ETHTAG_CLASS_WIDTH 3 -#define ESF_DZ_RI2C_ETHBASE_CLASS_LBN 193 +#define ESF_DZ_RI2C_ETHBASE_CLASS_LBN 196 #define ESF_DZ_RI2C_ETHBASE_CLASS_WIDTH 3 -#define ESF_DZ_RI2C_MAC_CLASS_LBN 192 +#define ESF_DZ_RI2C_MAC_CLASS_LBN 195 #define ESF_DZ_RI2C_MAC_CLASS_WIDTH 1 #define ESF_DZ_RI2C_PKT_OFST_LBN 176 #define ESF_DZ_RI2C_PKT_OFST_WIDTH 16 #define ESF_DZ_RI2C_PEDIT_DELTA_LBN 168 #define ESF_DZ_RI2C_PEDIT_DELTA_WIDTH 8 #define ESF_DZ_RI2C_PYLOAD_OFST_LBN 160 #define ESF_DZ_RI2C_PYLOAD_OFST_WIDTH 8 #define ESF_DZ_RI2C_L4_HDR_OFST_LBN 152 #define ESF_DZ_RI2C_L4_HDR_OFST_WIDTH 8 #define ESF_DZ_RI2C_L3_HDR_OFST_LBN 144 #define ESF_DZ_RI2C_L3_HDR_OFST_WIDTH 8 #define ESF_DZ_RI2C_HAVE_UDP_HDR_LBN 133 #define ESF_DZ_RI2C_HAVE_UDP_HDR_WIDTH 1 #define ESF_DZ_RI2C_HAVE_TCP_HDR_LBN 132 #define ESF_DZ_RI2C_HAVE_TCP_HDR_WIDTH 1 #define ESF_DZ_RI2C_HAVE_IPV6_HDR_LBN 131 #define ESF_DZ_RI2C_HAVE_IPV6_HDR_WIDTH 1 #define ESF_DZ_RI2C_HAVE_IPV4_HDR_LBN 130 #define ESF_DZ_RI2C_HAVE_IPV4_HDR_WIDTH 1 #define ESF_DZ_RI2C_HAVE_FCOE_LBN 129 #define ESF_DZ_RI2C_HAVE_FCOE_WIDTH 1 #define ESF_DZ_RI2C_PARSE_INCOMP_LBN 128 #define ESF_DZ_RI2C_PARSE_INCOMP_WIDTH 1 #define ESF_DZ_RI2C_EFINFO_WRD3_LBN 112 #define ESF_DZ_RI2C_EFINFO_WRD3_WIDTH 16 #define ESF_DZ_RI2C_EFINFO_WRD2_LBN 96 #define ESF_DZ_RI2C_EFINFO_WRD2_WIDTH 16 #define ESF_DZ_RI2C_EFINFO_WRD1_LBN 80 #define ESF_DZ_RI2C_EFINFO_WRD1_WIDTH 16 #define ESF_DZ_RI2C_EFINFO_WRD0_LBN 64 #define ESF_DZ_RI2C_EFINFO_WRD0_WIDTH 16 #define ESF_DZ_RI2C_FINFO_WRD3_LBN 48 #define ESF_DZ_RI2C_FINFO_WRD3_WIDTH 16 #define ESF_DZ_RI2C_FINFO_WRD2_LBN 32 #define ESF_DZ_RI2C_FINFO_WRD2_WIDTH 16 #define ESF_DZ_RI2C_FINFO_WRD1_LBN 16 #define ESF_DZ_RI2C_FINFO_WRD1_WIDTH 16 #define ESF_DZ_RI2C_FINFO_SRCDST_LBN 0 #define ESF_DZ_RI2C_FINFO_SRCDST_WIDTH 16 /* ES_FF_UMSG_SMC2CPU_BUFLKUP */ #define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_DW0_LBN 0 #define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_DW0_WIDTH 32 #define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_DW1_LBN 32 #define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_DW1_WIDTH 16 #define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_LBN 0 #define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_WIDTH 48 #define ESF_DZ_S2CB_FAIL_LBN 32 #define ESF_DZ_S2CB_FAIL_WIDTH 1 /* ES_FF_UMSG_SMC2CPU_DESCRD */ #define ESF_DZ_S2CD_BUF_LEN_LBN 112 #define ESF_DZ_S2CD_BUF_LEN_WIDTH 14 #define ESF_DZ_S2CD_ENCODED_HOST_ADDR_DW0_LBN 64 #define ESF_DZ_S2CD_ENCODED_HOST_ADDR_DW0_WIDTH 32 #define ESF_DZ_S2CD_ENCODED_HOST_ADDR_DW1_LBN 96 #define ESF_DZ_S2CD_ENCODED_HOST_ADDR_DW1_WIDTH 16 #define ESF_DZ_S2CD_ENCODED_HOST_ADDR_LBN 64 #define ESF_DZ_S2CD_ENCODED_HOST_ADDR_WIDTH 48 #define ESF_DZ_S2CD_CONT_LBN 16 #define ESF_DZ_S2CD_CONT_WIDTH 1 #define ESF_DZ_S2CD_TYPE_LBN 0 #define ESF_DZ_S2CD_TYPE_WIDTH 1 /* ES_FF_UMSG_SMC2CPU_GPRD */ #define ESF_DZ_S2CG_DATA_DW0_LBN 64 #define ESF_DZ_S2CG_DATA_DW0_WIDTH 32 #define ESF_DZ_S2CG_DATA_DW1_LBN 96 #define ESF_DZ_S2CG_DATA_DW1_WIDTH 32 #define ESF_DZ_S2CG_DATA_LBN 64 #define ESF_DZ_S2CG_DATA_WIDTH 64 #define ESF_DZ_S2CG_SOFT_LBN 48 #define ESF_DZ_S2CG_SOFT_WIDTH 4 #define ESF_DZ_S2CG_FAIL_LBN 32 #define ESF_DZ_S2CG_FAIL_WIDTH 1 /* ES_FF_UMSG_TXDP_DMA2CPU_PKTRDY */ #define ESF_DZ_TD2CP_L4_CLASS_LBN 250 #define ESF_DZ_TD2CP_L4_CLASS_WIDTH 3 #define ESF_DZ_TD2CP_L3_CLASS_LBN 247 #define ESF_DZ_TD2CP_L3_CLASS_WIDTH 3 #define ESF_DZ_TD2CP_ETHTAG_CLASS_LBN 244 #define ESF_DZ_TD2CP_ETHTAG_CLASS_WIDTH 3 #define ESF_DZ_TD2CP_ETHBASE_CLASS_LBN 241 #define ESF_DZ_TD2CP_ETHBASE_CLASS_WIDTH 3 #define ESF_DZ_TD2CP_MAC_CLASS_LBN 240 #define ESF_DZ_TD2CP_MAC_CLASS_WIDTH 1 -#define ESF_DZ_TD2CP_SOFT_LBN 226 -#define ESF_DZ_TD2CP_SOFT_WIDTH 14 -#define ESF_DZ_TD2CP_PKT_ABORT_LBN 225 +#define ESF_DZ_TD2CP_PCIE_ERR_OR_ABORT_LBN 239 +#define ESF_DZ_TD2CP_PCIE_ERR_OR_ABORT_WIDTH 1 +#define ESF_DZ_TD2CP_PKT_ABORT_LBN 238 #define ESF_DZ_TD2CP_PKT_ABORT_WIDTH 1 -#define ESF_DZ_TD2CP_PCIE_ERR_LBN 224 -#define ESF_DZ_TD2CP_PCIE_ERR_WIDTH 1 +#define ESF_DZ_TD2CP_SOFT_LBN 224 +#define ESF_DZ_TD2CP_SOFT_WIDTH 14 #define ESF_DZ_TD2CP_DESC_IDX_LBN 208 #define ESF_DZ_TD2CP_DESC_IDX_WIDTH 16 #define ESF_DZ_TD2CP_PKT_LEN_LBN 192 #define ESF_DZ_TD2CP_PKT_LEN_WIDTH 16 #define ESF_DZ_TD2CP_PKT_OFFST_OR_FIRST_DESC_IDX_LBN 176 #define ESF_DZ_TD2CP_PKT_OFFST_OR_FIRST_DESC_IDX_WIDTH 7 #define ESF_DZ_TD2CP_PEDIT_DELTA_LBN 168 #define ESF_DZ_TD2CP_PEDIT_DELTA_WIDTH 8 #define ESF_DZ_TD2CP_PYLOAD_OFST_LBN 160 #define ESF_DZ_TD2CP_PYLOAD_OFST_WIDTH 8 #define ESF_DZ_TD2CP_L4_HDR_OFST_LBN 152 #define ESF_DZ_TD2CP_L4_HDR_OFST_WIDTH 8 #define ESF_DZ_TD2CP_L3_HDR_OFST_LBN 144 #define ESF_DZ_TD2CP_L3_HDR_OFST_WIDTH 8 #define ESF_DZ_TD2CP_IS_UDP_LBN 133 #define ESF_DZ_TD2CP_IS_UDP_WIDTH 1 #define ESF_DZ_TD2CP_IS_TCP_LBN 132 #define ESF_DZ_TD2CP_IS_TCP_WIDTH 1 #define ESF_DZ_TD2CP_IS_IPV6_LBN 131 #define ESF_DZ_TD2CP_IS_IPV6_WIDTH 1 #define ESF_DZ_TD2CP_IS_IPV4_LBN 130 #define ESF_DZ_TD2CP_IS_IPV4_WIDTH 1 #define ESF_DZ_TD2CP_IS_FCOE_LBN 129 #define ESF_DZ_TD2CP_IS_FCOE_WIDTH 1 #define ESF_DZ_TD2CP_PARSE_INCOMP_LBN 128 #define ESF_DZ_TD2CP_PARSE_INCOMP_WIDTH 1 #define ESF_DZ_TD2CP_EFINFO_WRD3_LBN 112 #define ESF_DZ_TD2CP_EFINFO_WRD3_WIDTH 16 #define ESF_DZ_TD2CP_EFINFO_WRD2_LBN 96 #define ESF_DZ_TD2CP_EFINFO_WRD2_WIDTH 16 #define ESF_DZ_TD2CP_EFINFO_WRD1_LBN 80 #define ESF_DZ_TD2CP_EFINFO_WRD1_WIDTH 16 #define ESF_DZ_TD2CP_EFINFO_WRD0_LBN 64 #define ESF_DZ_TD2CP_EFINFO_WRD0_WIDTH 16 #define ESF_DZ_TD2CP_FINFO_WRD3_LBN 48 #define ESF_DZ_TD2CP_FINFO_WRD3_WIDTH 16 #define ESF_DZ_TD2CP_FINFO_WRD2_LBN 32 #define ESF_DZ_TD2CP_FINFO_WRD2_WIDTH 16 #define ESF_DZ_TD2CP_FINFO_WRD1_LBN 16 #define ESF_DZ_TD2CP_FINFO_WRD1_WIDTH 16 #define ESF_DZ_TD2CP_FINFO_SRCDST_LBN 0 #define ESF_DZ_TD2CP_FINFO_SRCDST_WIDTH 16 /* ES_FF_UMSG_TXDP_DMA2CPU_SOFT */ #define ESF_DZ_TD2CS_SOFT3_LBN 48 #define ESF_DZ_TD2CS_SOFT3_WIDTH 16 #define ESF_DZ_TD2CS_SOFT2_LBN 32 #define ESF_DZ_TD2CS_SOFT2_WIDTH 16 #define ESF_DZ_TD2CS_SOFT1_LBN 16 #define ESF_DZ_TD2CS_SOFT1_WIDTH 16 #define ESF_DZ_TD2CS_SOFT0_LBN 0 #define ESF_DZ_TD2CS_SOFT0_WIDTH 16 /* ES_FF_UMSG_TXDP_EGR2CPU_SOFT */ #define ESF_DZ_TE2CS_SOFT3_LBN 48 #define ESF_DZ_TE2CS_SOFT3_WIDTH 16 #define ESF_DZ_TE2CS_SOFT2_LBN 32 #define ESF_DZ_TE2CS_SOFT2_WIDTH 16 #define ESF_DZ_TE2CS_SOFT1_LBN 16 #define ESF_DZ_TE2CS_SOFT1_WIDTH 16 #define ESF_DZ_TE2CS_SOFT0_LBN 0 #define ESF_DZ_TE2CS_SOFT0_WIDTH 16 /* ES_FF_UMSG_VICTL2CPU */ #define ESF_DZ_V2C_DESC_WORD3_LBN 112 #define ESF_DZ_V2C_DESC_WORD3_WIDTH 17 #define ESF_DZ_V2C_DESC_WORD2_LBN 96 #define ESF_DZ_V2C_DESC_WORD2_WIDTH 16 #define ESF_DZ_V2C_DESC_WORD1_LBN 80 #define ESF_DZ_V2C_DESC_WORD1_WIDTH 16 #define ESF_DZ_V2C_DESC_WORD0_LBN 64 #define ESF_DZ_V2C_DESC_WORD0_WIDTH 16 #define ESF_DZ_V2C_NEW_DSCR_WPTR_LBN 32 #define ESF_DZ_V2C_NEW_DSCR_WPTR_WIDTH 12 #define ESF_DZ_V2C_DESC_PUSH_LBN 16 #define ESF_DZ_V2C_DESC_PUSH_WIDTH 1 /* ES_LUE_DB_MATCH_ENTRY */ #define ESF_DZ_LUE_DSCRMNTR_LBN 140 -#define ESF_DZ_LUE_DSCRMNTR_WIDTH 4 +#define ESF_DZ_LUE_DSCRMNTR_WIDTH 6 #define ESF_DZ_LUE_MATCH_VAL_DW0_LBN 44 #define ESF_DZ_LUE_MATCH_VAL_DW0_WIDTH 32 #define ESF_DZ_LUE_MATCH_VAL_DW1_LBN 76 #define ESF_DZ_LUE_MATCH_VAL_DW1_WIDTH 32 #define ESF_DZ_LUE_MATCH_VAL_DW2_LBN 108 #define ESF_DZ_LUE_MATCH_VAL_DW2_WIDTH 32 #define ESF_DZ_LUE_MATCH_VAL_LBN 44 #define ESF_DZ_LUE_MATCH_VAL_WIDTH 96 #define ESF_DZ_LUE_ME_SOFT_LBN 35 #define ESF_DZ_LUE_ME_SOFT_WIDTH 9 #define ESF_DZ_LUE_TX_MCAST_LBN 33 #define ESF_DZ_LUE_TX_MCAST_WIDTH 2 #define ESF_DZ_LUE_TX_DOMAIN_LBN 25 #define ESF_DZ_LUE_TX_DOMAIN_WIDTH 8 #define ESF_DZ_LUE_RX_MCAST_LBN 24 #define ESF_DZ_LUE_RX_MCAST_WIDTH 1 #define ESE_DZ_LUE_MULTI 1 #define ESE_DZ_LUE_SINGLE 0 #define ESF_DZ_LUE_RCPNTR_LBN 0 #define ESF_DZ_LUE_RCPNTR_WIDTH 24 -#define ESF_DZ_LUE_RCPNTR_ME_PTR_LBN 0 -#define ESF_DZ_LUE_RCPNTR_ME_PTR_WIDTH 14 /* ES_LUE_DB_NONMATCH_ENTRY */ #define ESF_DZ_LUE_DSCRMNTR_LBN 140 -#define ESF_DZ_LUE_DSCRMNTR_WIDTH 4 +#define ESF_DZ_LUE_DSCRMNTR_WIDTH 6 #define ESF_DZ_LUE_TERMINAL_LBN 139 #define ESF_DZ_LUE_TERMINAL_WIDTH 1 #define ESF_DZ_LUE_LAST_LBN 138 #define ESF_DZ_LUE_LAST_WIDTH 1 #define ESF_DZ_LUE_NE_SOFT_LBN 137 #define ESF_DZ_LUE_NE_SOFT_WIDTH 1 #define ESF_DZ_LUE_RCPNTR_NUM_LBN 134 #define ESF_DZ_LUE_RCPNTR_NUM_WIDTH 3 #define ESF_DZ_LUE_RCPNTR0_LBN 110 #define ESF_DZ_LUE_RCPNTR0_WIDTH 24 #define ESF_DZ_LUE_RCPNTR1_LBN 86 #define ESF_DZ_LUE_RCPNTR1_WIDTH 24 #define ESF_DZ_LUE_RCPNTR2_LBN 62 #define ESF_DZ_LUE_RCPNTR2_WIDTH 24 #define ESF_DZ_LUE_RCPNTR3_LBN 38 #define ESF_DZ_LUE_RCPNTR3_WIDTH 24 #define ESF_DZ_LUE_RCPNTR4_LBN 14 #define ESF_DZ_LUE_RCPNTR4_WIDTH 24 #define ESF_DZ_LUE_RCPNTR_NE_PTR_LBN 0 #define ESF_DZ_LUE_RCPNTR_NE_PTR_WIDTH 14 /* ES_LUE_MC_DIRECT_REQUEST_MSG */ #define ESF_DZ_MC2L_DR_PAD_DW0_LBN 22 #define ESF_DZ_MC2L_DR_PAD_DW0_WIDTH 32 #define ESF_DZ_MC2L_DR_PAD_DW1_LBN 54 #define ESF_DZ_MC2L_DR_PAD_DW1_WIDTH 32 #define ESF_DZ_MC2L_DR_PAD_DW2_LBN 86 #define ESF_DZ_MC2L_DR_PAD_DW2_WIDTH 32 #define ESF_DZ_MC2L_DR_PAD_DW3_LBN 118 #define ESF_DZ_MC2L_DR_PAD_DW3_WIDTH 32 #define ESF_DZ_MC2L_DR_PAD_DW4_LBN 150 -#define ESF_DZ_MC2L_DR_PAD_DW4_WIDTH 16 +#define ESF_DZ_MC2L_DR_PAD_DW4_WIDTH 18 #define ESF_DZ_MC2L_DR_PAD_LBN 22 -#define ESF_DZ_MC2L_DR_PAD_WIDTH 144 +#define ESF_DZ_MC2L_DR_PAD_WIDTH 146 #define ESF_DZ_MC2L_DR_ADDR_LBN 8 #define ESF_DZ_MC2L_DR_ADDR_WIDTH 14 #define ESF_DZ_MC2L_DR_THREAD_ID_LBN 5 #define ESF_DZ_MC2L_DR_THREAD_ID_WIDTH 3 #define ESF_DZ_MC2L_DR_CLIENT_ID_LBN 2 #define ESF_DZ_MC2L_DR_CLIENT_ID_WIDTH 3 #define ESF_DZ_MC2L_DR_OP_LBN 0 #define ESF_DZ_MC2L_DR_OP_WIDTH 2 #define ESE_DZ_LUE_GP_WR 3 #define ESE_DZ_LUE_GP_RD 2 #define ESE_DZ_LUE_DIR_REQ 1 #define ESE_DZ_LUE_MATCH_REQ 0 /* ES_LUE_MC_DIRECT_RESPONSE_MSG */ #define ESF_DZ_L2MC_DR_PAD_LBN 146 -#define ESF_DZ_L2MC_DR_PAD_WIDTH 6 +#define ESF_DZ_L2MC_DR_PAD_WIDTH 8 #define ESF_DZ_L2MC_DR_RCPNT_PTR_LBN 132 #define ESF_DZ_L2MC_DR_RCPNT_PTR_WIDTH 14 #define ESF_DZ_L2MC_DR_RCPNT4_LBN 108 #define ESF_DZ_L2MC_DR_RCPNT4_WIDTH 24 #define ESF_DZ_L2MC_DR_RCPNT3_LBN 84 #define ESF_DZ_L2MC_DR_RCPNT3_WIDTH 24 #define ESF_DZ_L2MC_DR_RCPNT2_LBN 60 #define ESF_DZ_L2MC_DR_RCPNT2_WIDTH 24 #define ESF_DZ_L2MC_DR_RCPNT1_LBN 36 #define ESF_DZ_L2MC_DR_RCPNT1_WIDTH 24 #define ESF_DZ_L2MC_DR_RCPNT0_LBN 12 #define ESF_DZ_L2MC_DR_RCPNT0_WIDTH 24 #define ESF_DZ_L2MC_DR_RCPNT_NUM_LBN 9 #define ESF_DZ_L2MC_DR_RCPNT_NUM_WIDTH 3 #define ESF_DZ_L2MC_DR_LAST_LBN 8 #define ESF_DZ_L2MC_DR_LAST_WIDTH 1 #define ESF_DZ_L2MC_DR_THREAD_ID_LBN 5 #define ESF_DZ_L2MC_DR_THREAD_ID_WIDTH 3 #define ESF_DZ_L2MC_DR_CLIENT_ID_LBN 2 #define ESF_DZ_L2MC_DR_CLIENT_ID_WIDTH 3 #define ESF_DZ_L2MC_DR_OP_LBN 0 #define ESF_DZ_L2MC_DR_OP_WIDTH 2 #define ESE_DZ_LUE_GP_WR 3 #define ESE_DZ_LUE_GP_RD 2 #define ESE_DZ_LUE_DIR_REQ 1 #define ESE_DZ_LUE_MATCH_REQ 0 /* ES_LUE_MC_GP_RD_REQUEST_MSG */ #define ESF_DZ_MC2L_GPR_PAD_DW0_LBN 22 #define ESF_DZ_MC2L_GPR_PAD_DW0_WIDTH 32 #define ESF_DZ_MC2L_GPR_PAD_DW1_LBN 54 #define ESF_DZ_MC2L_GPR_PAD_DW1_WIDTH 32 #define ESF_DZ_MC2L_GPR_PAD_DW2_LBN 86 #define ESF_DZ_MC2L_GPR_PAD_DW2_WIDTH 32 #define ESF_DZ_MC2L_GPR_PAD_DW3_LBN 118 #define ESF_DZ_MC2L_GPR_PAD_DW3_WIDTH 32 #define ESF_DZ_MC2L_GPR_PAD_DW4_LBN 150 -#define ESF_DZ_MC2L_GPR_PAD_DW4_WIDTH 16 +#define ESF_DZ_MC2L_GPR_PAD_DW4_WIDTH 18 #define ESF_DZ_MC2L_GPR_PAD_LBN 22 -#define ESF_DZ_MC2L_GPR_PAD_WIDTH 144 +#define ESF_DZ_MC2L_GPR_PAD_WIDTH 146 #define ESF_DZ_MC2L_GPR_ADDR_LBN 8 #define ESF_DZ_MC2L_GPR_ADDR_WIDTH 14 #define ESF_DZ_MC2L_GPR_THREAD_ID_LBN 5 #define ESF_DZ_MC2L_GPR_THREAD_ID_WIDTH 3 #define ESF_DZ_MC2L_GPR_CLIENT_ID_LBN 2 #define ESF_DZ_MC2L_GPR_CLIENT_ID_WIDTH 3 #define ESF_DZ_MC2L_GPR_OP_LBN 0 #define ESF_DZ_MC2L_GPR_OP_WIDTH 2 #define ESE_DZ_LUE_GP_WR 3 #define ESE_DZ_LUE_GP_RD 2 #define ESE_DZ_LUE_DIR_REQ 1 #define ESE_DZ_LUE_MATCH_REQ 0 /* ES_LUE_MC_GP_RD_RESPONSE_MSG */ #define ESF_DZ_L2MC_GPR_DATA_DW0_LBN 8 #define ESF_DZ_L2MC_GPR_DATA_DW0_WIDTH 32 #define ESF_DZ_L2MC_GPR_DATA_DW1_LBN 40 #define ESF_DZ_L2MC_GPR_DATA_DW1_WIDTH 32 #define ESF_DZ_L2MC_GPR_DATA_DW2_LBN 72 #define ESF_DZ_L2MC_GPR_DATA_DW2_WIDTH 32 #define ESF_DZ_L2MC_GPR_DATA_DW3_LBN 104 #define ESF_DZ_L2MC_GPR_DATA_DW3_WIDTH 32 #define ESF_DZ_L2MC_GPR_DATA_DW4_LBN 136 -#define ESF_DZ_L2MC_GPR_DATA_DW4_WIDTH 16 +#define ESF_DZ_L2MC_GPR_DATA_DW4_WIDTH 18 #define ESF_DZ_L2MC_GPR_DATA_LBN 8 -#define ESF_DZ_L2MC_GPR_DATA_WIDTH 144 +#define ESF_DZ_L2MC_GPR_DATA_WIDTH 146 #define ESF_DZ_L2MC_GPR_THREAD_ID_LBN 5 #define ESF_DZ_L2MC_GPR_THREAD_ID_WIDTH 3 #define ESF_DZ_L2MC_GPR_CLIENT_ID_LBN 2 #define ESF_DZ_L2MC_GPR_CLIENT_ID_WIDTH 3 #define ESF_DZ_L2MC_GPR_OP_LBN 0 #define ESF_DZ_L2MC_GPR_OP_WIDTH 2 #define ESE_DZ_LUE_GP_WR 3 #define ESE_DZ_LUE_GP_RD 2 #define ESE_DZ_LUE_DIR_REQ 1 #define ESE_DZ_LUE_MATCH_REQ 0 /* ES_LUE_MC_GP_WR_REQUEST_MSG */ #define ESF_DZ_MC2L_GPW_DATA_DW0_LBN 22 #define ESF_DZ_MC2L_GPW_DATA_DW0_WIDTH 32 #define ESF_DZ_MC2L_GPW_DATA_DW1_LBN 54 #define ESF_DZ_MC2L_GPW_DATA_DW1_WIDTH 32 #define ESF_DZ_MC2L_GPW_DATA_DW2_LBN 86 #define ESF_DZ_MC2L_GPW_DATA_DW2_WIDTH 32 #define ESF_DZ_MC2L_GPW_DATA_DW3_LBN 118 #define ESF_DZ_MC2L_GPW_DATA_DW3_WIDTH 32 #define ESF_DZ_MC2L_GPW_DATA_DW4_LBN 150 -#define ESF_DZ_MC2L_GPW_DATA_DW4_WIDTH 16 +#define ESF_DZ_MC2L_GPW_DATA_DW4_WIDTH 18 #define ESF_DZ_MC2L_GPW_DATA_LBN 22 -#define ESF_DZ_MC2L_GPW_DATA_WIDTH 144 +#define ESF_DZ_MC2L_GPW_DATA_WIDTH 146 #define ESF_DZ_MC2L_GPW_ADDR_LBN 8 #define ESF_DZ_MC2L_GPW_ADDR_WIDTH 14 #define ESF_DZ_MC2L_GPW_THREAD_ID_LBN 5 #define ESF_DZ_MC2L_GPW_THREAD_ID_WIDTH 3 #define ESF_DZ_MC2L_GPW_CLIENT_ID_LBN 2 #define ESF_DZ_MC2L_GPW_CLIENT_ID_WIDTH 3 #define ESF_DZ_MC2L_GPW_OP_LBN 0 #define ESF_DZ_MC2L_GPW_OP_WIDTH 2 #define ESE_DZ_LUE_GP_WR 3 #define ESE_DZ_LUE_GP_RD 2 #define ESE_DZ_LUE_DIR_REQ 1 #define ESE_DZ_LUE_MATCH_REQ 0 /* ES_LUE_MC_MATCH_REQUEST_MSG */ -#define ESF_DZ_MC2L_MR_PAD_LBN 135 +#define ESF_DZ_MC2L_MR_PAD_LBN 137 #define ESF_DZ_MC2L_MR_PAD_WIDTH 31 -#define ESF_DZ_MC2L_MR_HASH2_LBN 122 +#define ESF_DZ_MC2L_MR_HASH2_LBN 124 #define ESF_DZ_MC2L_MR_HASH2_WIDTH 13 -#define ESF_DZ_MC2L_MR_HASH1_LBN 108 +#define ESF_DZ_MC2L_MR_HASH1_LBN 110 #define ESF_DZ_MC2L_MR_HASH1_WIDTH 14 -#define ESF_DZ_MC2L_MR_MATCH_BITS_DW0_LBN 12 +#define ESF_DZ_MC2L_MR_MATCH_BITS_DW0_LBN 14 #define ESF_DZ_MC2L_MR_MATCH_BITS_DW0_WIDTH 32 -#define ESF_DZ_MC2L_MR_MATCH_BITS_DW1_LBN 44 +#define ESF_DZ_MC2L_MR_MATCH_BITS_DW1_LBN 46 #define ESF_DZ_MC2L_MR_MATCH_BITS_DW1_WIDTH 32 -#define ESF_DZ_MC2L_MR_MATCH_BITS_DW2_LBN 76 +#define ESF_DZ_MC2L_MR_MATCH_BITS_DW2_LBN 78 #define ESF_DZ_MC2L_MR_MATCH_BITS_DW2_WIDTH 32 -#define ESF_DZ_MC2L_MR_MATCH_BITS_LBN 12 +#define ESF_DZ_MC2L_MR_MATCH_BITS_LBN 14 #define ESF_DZ_MC2L_MR_MATCH_BITS_WIDTH 96 #define ESF_DZ_MC2L_MR_DSCRMNTR_LBN 8 -#define ESF_DZ_MC2L_MR_DSCRMNTR_WIDTH 4 +#define ESF_DZ_MC2L_MR_DSCRMNTR_WIDTH 6 #define ESF_DZ_MC2L_MR_THREAD_ID_LBN 5 #define ESF_DZ_MC2L_MR_THREAD_ID_WIDTH 3 #define ESF_DZ_MC2L_MR_CLIENT_ID_LBN 2 #define ESF_DZ_MC2L_MR_CLIENT_ID_WIDTH 3 #define ESF_DZ_MC2L_MR_OP_LBN 0 #define ESF_DZ_MC2L_MR_OP_WIDTH 2 #define ESE_DZ_LUE_GP_WR 3 #define ESE_DZ_LUE_GP_RD 2 #define ESE_DZ_LUE_DIR_REQ 1 #define ESE_DZ_LUE_MATCH_REQ 0 /* ES_LUE_MC_MATCH_RESPONSE_MSG */ #define ESF_DZ_L2MC_MR_PAD_DW0_LBN 53 #define ESF_DZ_L2MC_MR_PAD_DW0_WIDTH 32 #define ESF_DZ_L2MC_MR_PAD_DW1_LBN 85 #define ESF_DZ_L2MC_MR_PAD_DW1_WIDTH 32 #define ESF_DZ_L2MC_MR_PAD_DW2_LBN 117 #define ESF_DZ_L2MC_MR_PAD_DW2_WIDTH 32 #define ESF_DZ_L2MC_MR_PAD_DW3_LBN 149 -#define ESF_DZ_L2MC_MR_PAD_DW3_WIDTH 3 +#define ESF_DZ_L2MC_MR_PAD_DW3_WIDTH 5 #define ESF_DZ_L2MC_MR_PAD_LBN 53 -#define ESF_DZ_L2MC_MR_PAD_WIDTH 99 +#define ESF_DZ_L2MC_MR_PAD_WIDTH 101 #define ESF_DZ_L2MC_MR_LUE_RCPNT_LBN 29 #define ESF_DZ_L2MC_MR_LUE_RCPNT_WIDTH 24 #define ESF_DZ_L2MC_MR_RX_MCAST_LBN 28 #define ESF_DZ_L2MC_MR_RX_MCAST_WIDTH 1 #define ESF_DZ_L2MC_MR_TX_DOMAIN_LBN 20 #define ESF_DZ_L2MC_MR_TX_DOMAIN_WIDTH 8 #define ESF_DZ_L2MC_MR_TX_MCAST_LBN 18 #define ESF_DZ_L2MC_MR_TX_MCAST_WIDTH 2 #define ESF_DZ_L2MC_MR_SOFT_LBN 9 #define ESF_DZ_L2MC_MR_SOFT_WIDTH 9 #define ESF_DZ_L2MC_MR_MATCH_LBN 8 #define ESF_DZ_L2MC_MR_MATCH_WIDTH 1 #define ESF_DZ_L2MC_MR_THREAD_ID_LBN 5 #define ESF_DZ_L2MC_MR_THREAD_ID_WIDTH 3 #define ESF_DZ_L2MC_MR_CLIENT_ID_LBN 2 #define ESF_DZ_L2MC_MR_CLIENT_ID_WIDTH 3 #define ESF_DZ_L2MC_MR_OP_LBN 0 #define ESF_DZ_L2MC_MR_OP_WIDTH 2 #define ESE_DZ_LUE_GP_WR 3 #define ESE_DZ_LUE_GP_RD 2 #define ESE_DZ_LUE_DIR_REQ 1 #define ESE_DZ_LUE_MATCH_REQ 0 /* ES_LUE_MSG_BASE_REQ */ #define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW0_LBN 8 #define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW0_WIDTH 32 #define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW1_LBN 40 #define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW1_WIDTH 32 #define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW2_LBN 72 #define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW2_WIDTH 32 #define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW3_LBN 104 #define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW3_WIDTH 32 #define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW4_LBN 136 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW4_WIDTH 30 +#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW4_WIDTH 32 #define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_LBN 8 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_WIDTH 158 +#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_WIDTH 160 #define ESF_DZ_LUE_HW_REQ_BASE_THREAD_ID_LBN 5 #define ESF_DZ_LUE_HW_REQ_BASE_THREAD_ID_WIDTH 3 #define ESF_DZ_LUE_HW_REQ_BASE_CLIENT_ID_LBN 2 #define ESF_DZ_LUE_HW_REQ_BASE_CLIENT_ID_WIDTH 3 #define ESE_DZ_LUE_MC_ID 7 #define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 #define ESE_DZ_LUE_TX_DICPU_ID 1 #define ESE_DZ_LUE_RX_DICPU_ID 0 #define ESF_DZ_LUE_HW_REQ_BASE_OP_LBN 0 #define ESF_DZ_LUE_HW_REQ_BASE_OP_WIDTH 2 #define ESE_DZ_LUE_GP_WR 3 #define ESE_DZ_LUE_GP_RD 2 #define ESE_DZ_LUE_DIR_REQ 1 #define ESE_DZ_LUE_MATCH_REQ 0 /* ES_LUE_MSG_BASE_RESP */ #define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW0_LBN 8 #define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW0_WIDTH 32 #define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW1_LBN 40 #define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW1_WIDTH 32 #define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW2_LBN 72 #define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW2_WIDTH 32 #define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW3_LBN 104 #define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW3_WIDTH 32 #define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW4_LBN 136 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW4_WIDTH 16 +#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW4_WIDTH 18 #define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_LBN 8 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_WIDTH 144 +#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_WIDTH 146 #define ESF_DZ_LUE_HW_RSP_BASE_THREAD_ID_LBN 5 #define ESF_DZ_LUE_HW_RSP_BASE_THREAD_ID_WIDTH 3 #define ESF_DZ_LUE_HW_RSP_BASE_CLIENT_ID_LBN 2 #define ESF_DZ_LUE_HW_RSP_BASE_CLIENT_ID_WIDTH 3 #define ESE_DZ_LUE_MC_ID 7 #define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 #define ESE_DZ_LUE_TX_DICPU_ID 1 #define ESE_DZ_LUE_RX_DICPU_ID 0 #define ESF_DZ_LUE_HW_RSP_BASE_OP_LBN 0 #define ESF_DZ_LUE_HW_RSP_BASE_OP_WIDTH 2 #define ESE_DZ_LUE_GP_WR 3 #define ESE_DZ_LUE_GP_RD 2 #define ESE_DZ_LUE_DIR_REQ 1 #define ESE_DZ_LUE_MATCH_REQ 0 /* ES_LUE_MSG_DIRECT_REQ */ #define ESF_DZ_LUE_HW_REQ_DIR_ADDR_LBN 8 #define ESF_DZ_LUE_HW_REQ_DIR_ADDR_WIDTH 14 #define ESF_DZ_LUE_HW_REQ_DIR_THREAD_ID_LBN 5 #define ESF_DZ_LUE_HW_REQ_DIR_THREAD_ID_WIDTH 3 #define ESF_DZ_LUE_HW_REQ_DIR_CLIENT_ID_LBN 2 #define ESF_DZ_LUE_HW_REQ_DIR_CLIENT_ID_WIDTH 3 #define ESE_DZ_LUE_MC_ID 7 #define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 #define ESE_DZ_LUE_TX_DICPU_ID 1 #define ESE_DZ_LUE_RX_DICPU_ID 0 #define ESF_DZ_LUE_HW_REQ_DIR_OP_LBN 0 #define ESF_DZ_LUE_HW_REQ_DIR_OP_WIDTH 2 #define ESE_DZ_LUE_GP_WR 3 #define ESE_DZ_LUE_GP_RD 2 #define ESE_DZ_LUE_DIR_REQ 1 #define ESE_DZ_LUE_MATCH_REQ 0 /* ES_LUE_MSG_DIRECT_RESP */ #define ESF_DZ_LUE_HW_RSP_DIR_RCPNT_PTR_LBN 132 #define ESF_DZ_LUE_HW_RSP_DIR_RCPNT_PTR_WIDTH 14 #define ESF_DZ_LUE_HW_RSP_DIR_RCPNT4_LBN 108 #define ESF_DZ_LUE_HW_RSP_DIR_RCPNT4_WIDTH 24 #define ESF_DZ_LUE_HW_RSP_DIR_RCPNT3_LBN 84 #define ESF_DZ_LUE_HW_RSP_DIR_RCPNT3_WIDTH 24 #define ESF_DZ_LUE_HW_RSP_DIR_RCPNT2_LBN 60 #define ESF_DZ_LUE_HW_RSP_DIR_RCPNT2_WIDTH 24 #define ESF_DZ_LUE_HW_RSP_DIR_RCPNT1_LBN 36 #define ESF_DZ_LUE_HW_RSP_DIR_RCPNT1_WIDTH 24 #define ESF_DZ_LUE_HW_RSP_DIR_RCPNT0_LBN 12 #define ESF_DZ_LUE_HW_RSP_DIR_RCPNT0_WIDTH 24 #define ESF_DZ_LUE_HW_RSP_DIR_RCPNT_NUM_LBN 9 #define ESF_DZ_LUE_HW_RSP_DIR_RCPNT_NUM_WIDTH 3 #define ESF_DZ_LUE_HW_RSP_DIR_LAST_LBN 8 #define ESF_DZ_LUE_HW_RSP_DIR_LAST_WIDTH 1 #define ESF_DZ_LUE_HW_RSP_DIR_THREAD_ID_LBN 5 #define ESF_DZ_LUE_HW_RSP_DIR_THREAD_ID_WIDTH 3 #define ESF_DZ_LUE_HW_RSP_DIR_CLIENT_ID_LBN 2 #define ESF_DZ_LUE_HW_RSP_DIR_CLIENT_ID_WIDTH 3 #define ESE_DZ_LUE_MC_ID 7 #define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 #define ESE_DZ_LUE_TX_DICPU_ID 1 #define ESE_DZ_LUE_RX_DICPU_ID 0 #define ESF_DZ_LUE_HW_RSP_DIR_OP_LBN 0 #define ESF_DZ_LUE_HW_RSP_DIR_OP_WIDTH 2 #define ESE_DZ_LUE_GP_WR 3 #define ESE_DZ_LUE_GP_RD 2 #define ESE_DZ_LUE_DIR_REQ 1 #define ESE_DZ_LUE_MATCH_REQ 0 /* ES_LUE_MSG_GP_RD_REQ */ #define ESF_DZ_LUE_HW_REQ_GPRD_ADDR_LBN 8 #define ESF_DZ_LUE_HW_REQ_GPRD_ADDR_WIDTH 14 #define ESF_DZ_LUE_HW_REQ_GPRD_THREAD_ID_LBN 5 #define ESF_DZ_LUE_HW_REQ_GPRD_THREAD_ID_WIDTH 3 #define ESF_DZ_LUE_HW_REQ_GPRD_CLIENT_ID_LBN 2 #define ESF_DZ_LUE_HW_REQ_GPRD_CLIENT_ID_WIDTH 3 #define ESE_DZ_LUE_MC_ID 7 #define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 #define ESE_DZ_LUE_TX_DICPU_ID 1 #define ESE_DZ_LUE_RX_DICPU_ID 0 #define ESF_DZ_LUE_HW_REQ_GPRD_OP_LBN 0 #define ESF_DZ_LUE_HW_REQ_GPRD_OP_WIDTH 2 #define ESE_DZ_LUE_GP_WR 3 #define ESE_DZ_LUE_GP_RD 2 #define ESE_DZ_LUE_DIR_REQ 1 #define ESE_DZ_LUE_MATCH_REQ 0 /* ES_LUE_MSG_GP_RD_RESP */ #define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW0_LBN 8 #define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW0_WIDTH 32 #define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW1_LBN 40 #define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW1_WIDTH 32 #define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW2_LBN 72 #define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW2_WIDTH 32 #define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW3_LBN 104 #define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW3_WIDTH 32 #define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW4_LBN 136 -#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW4_WIDTH 16 +#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW4_WIDTH 18 #define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_LBN 8 -#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_WIDTH 144 +#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_WIDTH 146 #define ESF_DZ_LUE_HW_RSP_GPRD_THREAD_ID_LBN 5 #define ESF_DZ_LUE_HW_RSP_GPRD_THREAD_ID_WIDTH 3 #define ESF_DZ_LUE_HW_RSP_GPRD_CLIENT_ID_LBN 2 #define ESF_DZ_LUE_HW_RSP_GPRD_CLIENT_ID_WIDTH 3 #define ESE_DZ_LUE_MC_ID 7 #define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 #define ESE_DZ_LUE_TX_DICPU_ID 1 #define ESE_DZ_LUE_RX_DICPU_ID 0 #define ESF_DZ_LUE_HW_RSP_GPRD_OP_LBN 0 #define ESF_DZ_LUE_HW_RSP_GPRD_OP_WIDTH 2 #define ESE_DZ_LUE_GP_WR 3 #define ESE_DZ_LUE_GP_RD 2 #define ESE_DZ_LUE_DIR_REQ 1 #define ESE_DZ_LUE_MATCH_REQ 0 /* ES_LUE_MSG_GP_WR_REQ */ #define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW0_LBN 22 #define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW0_WIDTH 32 #define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW1_LBN 54 #define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW1_WIDTH 32 #define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW2_LBN 86 #define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW2_WIDTH 32 #define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW3_LBN 118 #define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW3_WIDTH 32 #define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW4_LBN 150 -#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW4_WIDTH 16 +#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW4_WIDTH 18 #define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_LBN 22 -#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_WIDTH 144 +#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_WIDTH 146 #define ESF_DZ_LUE_HW_REQ_GPWR_ADDR_LBN 8 #define ESF_DZ_LUE_HW_REQ_GPWR_ADDR_WIDTH 14 #define ESF_DZ_LUE_HW_REQ_GPWR_THREAD_ID_LBN 5 #define ESF_DZ_LUE_HW_REQ_GPWR_THREAD_ID_WIDTH 3 #define ESF_DZ_LUE_HW_REQ_GPWR_CLIENT_ID_LBN 2 #define ESF_DZ_LUE_HW_REQ_GPWR_CLIENT_ID_WIDTH 3 #define ESE_DZ_LUE_MC_ID 7 #define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 #define ESE_DZ_LUE_TX_DICPU_ID 1 #define ESE_DZ_LUE_RX_DICPU_ID 0 #define ESF_DZ_LUE_HW_REQ_GPWR_OP_LBN 0 #define ESF_DZ_LUE_HW_REQ_GPWR_OP_WIDTH 2 #define ESE_DZ_LUE_GP_WR 3 #define ESE_DZ_LUE_GP_RD 2 #define ESE_DZ_LUE_DIR_REQ 1 #define ESE_DZ_LUE_MATCH_REQ 0 /* ES_LUE_MSG_MATCH_REQ */ -#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_REQ_COUNT_LBN 135 -#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_REQ_COUNT_WIDTH 6 -#define ESF_DZ_LUE_HW_REQ_MATCH_HASH2_LBN 122 +#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_REQ_COUNT_LBN 137 +#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_REQ_COUNT_WIDTH 8 +#define ESF_DZ_LUE_HW_REQ_MATCH_HASH2_LBN 124 #define ESF_DZ_LUE_HW_REQ_MATCH_HASH2_WIDTH 13 -#define ESF_DZ_LUE_HW_REQ_MATCH_HASH1_LBN 108 +#define ESF_DZ_LUE_HW_REQ_MATCH_HASH1_LBN 110 #define ESF_DZ_LUE_HW_REQ_MATCH_HASH1_WIDTH 14 -#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW0_LBN 12 +#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW0_LBN 14 #define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW0_WIDTH 32 -#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW1_LBN 44 +#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW1_LBN 46 #define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW1_WIDTH 32 -#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW2_LBN 76 +#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW2_LBN 78 #define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW2_WIDTH 32 -#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_LBN 12 +#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_LBN 14 #define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_WIDTH 96 #define ESF_DZ_LUE_HW_REQ_MATCH_DSCRMNTR_LBN 8 -#define ESF_DZ_LUE_HW_REQ_MATCH_DSCRMNTR_WIDTH 4 +#define ESF_DZ_LUE_HW_REQ_MATCH_DSCRMNTR_WIDTH 6 #define ESF_DZ_LUE_HW_REQ_MATCH_THREAD_ID_LBN 5 #define ESF_DZ_LUE_HW_REQ_MATCH_THREAD_ID_WIDTH 3 #define ESF_DZ_LUE_HW_REQ_MATCH_CLIENT_ID_LBN 2 #define ESF_DZ_LUE_HW_REQ_MATCH_CLIENT_ID_WIDTH 3 #define ESE_DZ_LUE_MC_ID 7 #define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 #define ESE_DZ_LUE_TX_DICPU_ID 1 #define ESE_DZ_LUE_RX_DICPU_ID 0 #define ESF_DZ_LUE_HW_REQ_MATCH_OP_LBN 0 #define ESF_DZ_LUE_HW_REQ_MATCH_OP_WIDTH 2 #define ESE_DZ_LUE_GP_WR 3 #define ESE_DZ_LUE_GP_RD 2 #define ESE_DZ_LUE_DIR_REQ 1 #define ESE_DZ_LUE_MATCH_REQ 0 /* ES_LUE_MSG_MATCH_RESP */ #define ESF_DZ_LUE_HW_RSP_MATCH_LUE_RCPNT_LBN 29 #define ESF_DZ_LUE_HW_RSP_MATCH_LUE_RCPNT_WIDTH 24 #define ESF_DZ_LUE_HW_RSP_MATCH_RX_MCAST_LBN 28 #define ESF_DZ_LUE_HW_RSP_MATCH_RX_MCAST_WIDTH 1 #define ESF_DZ_LUE_HW_RSP_MATCH_TX_DOMAIN_LBN 20 #define ESF_DZ_LUE_HW_RSP_MATCH_TX_DOMAIN_WIDTH 8 #define ESF_DZ_LUE_HW_RSP_MATCH_TX_MCAST_LBN 18 #define ESF_DZ_LUE_HW_RSP_MATCH_TX_MCAST_WIDTH 2 #define ESF_DZ_LUE_HW_RSP_MATCH_SOFT_LBN 9 #define ESF_DZ_LUE_HW_RSP_MATCH_SOFT_WIDTH 9 #define ESF_DZ_LUE_HW_RSP_MATCH_MATCH_LBN 8 #define ESF_DZ_LUE_HW_RSP_MATCH_MATCH_WIDTH 1 #define ESF_DZ_LUE_HW_RSP_MATCH_THREAD_ID_LBN 5 #define ESF_DZ_LUE_HW_RSP_MATCH_THREAD_ID_WIDTH 3 #define ESF_DZ_LUE_HW_RSP_MATCH_CLIENT_ID_LBN 2 #define ESF_DZ_LUE_HW_RSP_MATCH_CLIENT_ID_WIDTH 3 #define ESE_DZ_LUE_MC_ID 7 #define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 #define ESE_DZ_LUE_TX_DICPU_ID 1 #define ESE_DZ_LUE_RX_DICPU_ID 0 #define ESF_DZ_LUE_HW_RSP_MATCH_OP_LBN 0 #define ESF_DZ_LUE_HW_RSP_MATCH_OP_WIDTH 2 #define ESE_DZ_LUE_GP_WR 3 #define ESE_DZ_LUE_GP_RD 2 #define ESE_DZ_LUE_DIR_REQ 1 #define ESE_DZ_LUE_MATCH_REQ 0 /* ES_LUE_RCPNTR_TYPE */ #define ESF_DZ_LUE_RXQ_LBN 14 #define ESF_DZ_LUE_RXQ_WIDTH 10 #define ESF_DZ_LUE_RSS_INFO_LBN 8 #define ESF_DZ_LUE_RSS_INFO_WIDTH 6 #define ESF_DZ_LUE_DEST_LBN 5 #define ESF_DZ_LUE_DEST_WIDTH 3 #define ESF_DZ_LUE_SOFT_LBN 0 #define ESF_DZ_LUE_SOFT_WIDTH 5 /* ES_LUE_UMSG_LU2DI_HASH_RESP */ #define ESF_DZ_L2DHR_LASTREC_ENTRY_STATUS_LBN 50 #define ESF_DZ_L2DHR_LASTREC_ENTRY_STATUS_WIDTH 1 #define ESF_DZ_L2DHR_MULTITYPE_STATUS_LBN 50 #define ESF_DZ_L2DHR_MULTITYPE_STATUS_WIDTH 1 #define ESF_DZ_L2DHR_LASTREC_STATUS_LBN 49 #define ESF_DZ_L2DHR_LASTREC_STATUS_WIDTH 1 #define ESF_DZ_L2DHR_MATCH_STATUS_LBN 48 #define ESF_DZ_L2DHR_MATCH_STATUS_WIDTH 1 #define ESF_DZ_L2DHR_HASH_LBN 0 #define ESF_DZ_L2DHR_HASH_WIDTH 32 /* ES_LUE_UMSG_LU2DI_RXLU_MULTI_MATCH_RESP */ #define ESF_DZ_L2DRMMR_SOFT_LBN 112 #define ESF_DZ_L2DRMMR_SOFT_WIDTH 9 #define ESF_DZ_L2DRMMR_RCPNTR_PTR_LBN 96 #define ESF_DZ_L2DRMMR_RCPNTR_PTR_WIDTH 14 #define ESF_DZ_L2DRMMR_TX_MCAST_LBN 80 #define ESF_DZ_L2DRMMR_TX_MCAST_WIDTH 2 #define ESF_DZ_L2DRMMR_MULTITYPE_STATUS_LBN 67 #define ESF_DZ_L2DRMMR_MULTITYPE_STATUS_WIDTH 1 #define ESF_DZ_L2DRMMR_LASTREC_ENTRY_STATUS_LBN 66 #define ESF_DZ_L2DRMMR_LASTREC_ENTRY_STATUS_WIDTH 1 #define ESF_DZ_L2DRMMR_LASTREC_STATUS_LBN 65 #define ESF_DZ_L2DRMMR_LASTREC_STATUS_WIDTH 1 #define ESF_DZ_L2DRMMR_MATCH_STATUS_LBN 64 #define ESF_DZ_L2DRMMR_MATCH_STATUS_WIDTH 1 /* ES_LUE_UMSG_LU2DI_RXLU_MULTI_RECORD_RESP */ #define ESF_DZ_L2DRMRR_SOFT_LBN 112 #define ESF_DZ_L2DRMRR_SOFT_WIDTH 9 #define ESF_DZ_L2DRMRR_RCPNTR_PTR_LBN 96 #define ESF_DZ_L2DRMRR_RCPNTR_PTR_WIDTH 14 #define ESF_DZ_L2DRMRR_RCPNTR_NUM_LBN 80 #define ESF_DZ_L2DRMRR_RCPNTR_NUM_WIDTH 3 #define ESF_DZ_L2DRMRR_MULTITYPE_STATUS_LBN 67 #define ESF_DZ_L2DRMRR_MULTITYPE_STATUS_WIDTH 1 #define ESF_DZ_L2DRMRR_LASTREC_ENTRY_STATUS_LBN 66 #define ESF_DZ_L2DRMRR_LASTREC_ENTRY_STATUS_WIDTH 1 #define ESF_DZ_L2DRMRR_LASTREC_STATUS_LBN 65 #define ESF_DZ_L2DRMRR_LASTREC_STATUS_WIDTH 1 #define ESF_DZ_L2DRMRR_MATCH_STATUS_LBN 64 #define ESF_DZ_L2DRMRR_MATCH_STATUS_WIDTH 1 #define ESF_DZ_L2DRMRR_RCPNTR_SOFT_LBN 48 #define ESF_DZ_L2DRMRR_RCPNTR_SOFT_WIDTH 6 #define ESF_DZ_L2DRMRR_RCPNTR_RSS_INFO_LBN 32 #define ESF_DZ_L2DRMRR_RCPNTR_RSS_INFO_WIDTH 5 #define ESF_DZ_L2DRMRR_RCPNTR_RXQ_LBN 16 #define ESF_DZ_L2DRMRR_RCPNTR_RXQ_WIDTH 10 #define ESF_DZ_L2DRMRR_HOST_LBN 7 #define ESF_DZ_L2DRMRR_HOST_WIDTH 1 #define ESF_DZ_L2DRMRR_MC_LBN 6 #define ESF_DZ_L2DRMRR_MC_WIDTH 1 #define ESF_DZ_L2DRMRR_PORT0_MAC_LBN 5 #define ESF_DZ_L2DRMRR_PORT0_MAC_WIDTH 1 #define ESF_DZ_L2DRMRR_PORT1_MAC_LBN 4 #define ESF_DZ_L2DRMRR_PORT1_MAC_WIDTH 1 /* ES_LUE_UMSG_LU2DI_RXLU_SINGLE_MATCH_RESP */ #define ESF_DZ_L2DRSMR_MULTITYPE_STATUS_LBN 67 #define ESF_DZ_L2DRSMR_MULTITYPE_STATUS_WIDTH 1 #define ESF_DZ_L2DRSMR_LASTREC_ENTRY_STATUS_LBN 66 #define ESF_DZ_L2DRSMR_LASTREC_ENTRY_STATUS_WIDTH 1 #define ESF_DZ_L2DRSMR_LASTREC_STATUS_LBN 65 #define ESF_DZ_L2DRSMR_LASTREC_STATUS_WIDTH 1 #define ESF_DZ_L2DRSMR_MATCH_STATUS_LBN 64 #define ESF_DZ_L2DRSMR_MATCH_STATUS_WIDTH 1 #define ESF_DZ_L2DRSMR_RCPNTR_SOFT_LBN 48 #define ESF_DZ_L2DRSMR_RCPNTR_SOFT_WIDTH 6 #define ESF_DZ_L2DRSMR_RCPNTR_RSS_INFO_LBN 32 #define ESF_DZ_L2DRSMR_RCPNTR_RSS_INFO_WIDTH 5 #define ESF_DZ_L2DRSMR_RCPNTR_RXQ_LBN 16 #define ESF_DZ_L2DRSMR_RCPNTR_RXQ_WIDTH 10 #define ESF_DZ_L2DRSMR_HOST_LBN 7 #define ESF_DZ_L2DRSMR_HOST_WIDTH 1 #define ESF_DZ_L2DRSMR_MC_LBN 6 #define ESF_DZ_L2DRSMR_MC_WIDTH 1 #define ESF_DZ_L2DRSMR_PORT0_MAC_LBN 5 #define ESF_DZ_L2DRSMR_PORT0_MAC_WIDTH 1 #define ESF_DZ_L2DRSMR_PORT1_MAC_LBN 4 #define ESF_DZ_L2DRSMR_PORT1_MAC_WIDTH 1 /* ES_LUE_UMSG_LU2DI_TXLU_MATCH_RESP */ #define ESF_DZ_L2DTMR_RCPNTR_SOFT_LBN 112 #define ESF_DZ_L2DTMR_RCPNTR_SOFT_WIDTH 6 #define ESF_DZ_L2DTMR_RCPNTR_RSS_INFO_LBN 96 #define ESF_DZ_L2DTMR_RCPNTR_RSS_INFO_WIDTH 5 #define ESF_DZ_L2DTMR_RCPNTR__RXQ_LBN 80 #define ESF_DZ_L2DTMR_RCPNTR__RXQ_WIDTH 10 #define ESF_DZ_L2DTMR_MULTITYPE_STATUS_LBN 67 #define ESF_DZ_L2DTMR_MULTITYPE_STATUS_WIDTH 1 #define ESF_DZ_L2DTMR_LASTREC_ENTRY_STATUS_LBN 66 #define ESF_DZ_L2DTMR_LASTREC_ENTRY_STATUS_WIDTH 1 #define ESF_DZ_L2DTMR_LASTREC_STATUS_LBN 65 #define ESF_DZ_L2DTMR_LASTREC_STATUS_WIDTH 1 #define ESF_DZ_L2DTMR_MATCH_STATUS_LBN 64 #define ESF_DZ_L2DTMR_MATCH_STATUS_WIDTH 1 #define ESF_DZ_L2DTMR_ME_SOFT_LBN 48 #define ESF_DZ_L2DTMR_ME_SOFT_WIDTH 9 #define ESF_DZ_L2DTMR_TX_MCAST_LBN 32 #define ESF_DZ_L2DTMR_TX_MCAST_WIDTH 2 #define ESF_DZ_L2DTMR_TX_DOMAIN_LBN 16 #define ESF_DZ_L2DTMR_TX_DOMAIN_WIDTH 8 #define ESF_DZ_L2DTMR_PORT1_MAC_LBN 6 #define ESF_DZ_L2DTMR_PORT1_MAC_WIDTH 1 #define ESF_DZ_L2DTMR_PMEM_LBN 6 #define ESF_DZ_L2DTMR_PMEM_WIDTH 1 #define ESF_DZ_L2DTMR_PORT0_MAC_LBN 5 #define ESF_DZ_L2DTMR_PORT0_MAC_WIDTH 1 /* ES_MC_EVENT */ #define ESF_DZ_MC_CODE_LBN 60 #define ESF_DZ_MC_CODE_WIDTH 4 #define ESF_DZ_MC_OVERRIDE_HOLDOFF_LBN 59 #define ESF_DZ_MC_OVERRIDE_HOLDOFF_WIDTH 1 #define ESF_DZ_MC_DROP_EVENT_LBN 58 #define ESF_DZ_MC_DROP_EVENT_WIDTH 1 #define ESF_DZ_MC_SOFT_DW0_LBN 0 #define ESF_DZ_MC_SOFT_DW0_WIDTH 32 #define ESF_DZ_MC_SOFT_DW1_LBN 32 #define ESF_DZ_MC_SOFT_DW1_WIDTH 26 #define ESF_DZ_MC_SOFT_LBN 0 #define ESF_DZ_MC_SOFT_WIDTH 58 /* ES_MC_XGMAC_FLTR_RULE_DEF */ #define ESF_DZ_MC_XFRC_MODE_LBN 416 #define ESF_DZ_MC_XFRC_MODE_WIDTH 1 #define ESE_DZ_MC_XFRC_MODE_LAYERED 1 #define ESE_DZ_MC_XFRC_MODE_SIMPLE 0 #define ESF_DZ_MC_XFRC_HASH_LBN 384 #define ESF_DZ_MC_XFRC_HASH_WIDTH 32 #define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW0_LBN 256 #define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW0_WIDTH 32 #define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW1_LBN 288 #define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW1_WIDTH 32 #define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW2_LBN 320 #define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW2_WIDTH 32 #define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW3_LBN 352 #define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW3_WIDTH 32 #define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_LBN 256 #define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_WIDTH 128 #define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW0_LBN 128 #define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW0_WIDTH 32 #define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW1_LBN 160 #define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW1_WIDTH 32 #define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW2_LBN 192 #define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW2_WIDTH 32 #define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW3_LBN 224 #define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW3_WIDTH 32 #define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_LBN 128 #define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_WIDTH 128 #define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW0_LBN 0 #define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW0_WIDTH 32 #define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW1_LBN 32 #define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW1_WIDTH 32 #define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW2_LBN 64 #define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW2_WIDTH 32 #define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW3_LBN 96 #define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW3_WIDTH 32 #define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_LBN 0 #define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_WIDTH 128 /* ES_RX_EVENT */ #define ESF_DZ_RX_CODE_LBN 60 #define ESF_DZ_RX_CODE_WIDTH 4 #define ESF_DZ_RX_OVERRIDE_HOLDOFF_LBN 59 #define ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1 #define ESF_DZ_RX_DROP_EVENT_LBN 58 #define ESF_DZ_RX_DROP_EVENT_WIDTH 1 -#define ESF_DZ_RX_EV_RSVD2_LBN 55 -#define ESF_DZ_RX_EV_RSVD2_WIDTH 3 +#define ESF_DZ_RX_EV_RSVD2_LBN 54 +#define ESF_DZ_RX_EV_RSVD2_WIDTH 4 #define ESF_DZ_RX_EV_SOFT2_LBN 52 -#define ESF_DZ_RX_EV_SOFT2_WIDTH 3 +#define ESF_DZ_RX_EV_SOFT2_WIDTH 2 #define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48 #define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4 #define ESF_DZ_RX_L4_CLASS_LBN 45 #define ESF_DZ_RX_L4_CLASS_WIDTH 3 #define ESE_DZ_L4_CLASS_RSVD7 7 #define ESE_DZ_L4_CLASS_RSVD6 6 #define ESE_DZ_L4_CLASS_RSVD5 5 #define ESE_DZ_L4_CLASS_RSVD4 4 #define ESE_DZ_L4_CLASS_RSVD3 3 #define ESE_DZ_L4_CLASS_UDP 2 #define ESE_DZ_L4_CLASS_TCP 1 #define ESE_DZ_L4_CLASS_UNKNOWN 0 #define ESF_DZ_RX_L3_CLASS_LBN 42 #define ESF_DZ_RX_L3_CLASS_WIDTH 3 #define ESE_DZ_L3_CLASS_RSVD7 7 #define ESE_DZ_L3_CLASS_IP6_FRAG 6 #define ESE_DZ_L3_CLASS_ARP 5 #define ESE_DZ_L3_CLASS_IP4_FRAG 4 #define ESE_DZ_L3_CLASS_FCOE 3 #define ESE_DZ_L3_CLASS_IP6 2 #define ESE_DZ_L3_CLASS_IP4 1 #define ESE_DZ_L3_CLASS_UNKNOWN 0 #define ESF_DZ_RX_ETH_TAG_CLASS_LBN 39 #define ESF_DZ_RX_ETH_TAG_CLASS_WIDTH 3 #define ESE_DZ_ETH_TAG_CLASS_RSVD7 7 #define ESE_DZ_ETH_TAG_CLASS_RSVD6 6 #define ESE_DZ_ETH_TAG_CLASS_RSVD5 5 #define ESE_DZ_ETH_TAG_CLASS_RSVD4 4 #define ESE_DZ_ETH_TAG_CLASS_RSVD3 3 #define ESE_DZ_ETH_TAG_CLASS_VLAN2 2 #define ESE_DZ_ETH_TAG_CLASS_VLAN1 1 #define ESE_DZ_ETH_TAG_CLASS_NONE 0 #define ESF_DZ_RX_ETH_BASE_CLASS_LBN 36 #define ESF_DZ_RX_ETH_BASE_CLASS_WIDTH 3 #define ESE_DZ_ETH_BASE_CLASS_LLC_SNAP 2 #define ESE_DZ_ETH_BASE_CLASS_LLC 1 #define ESE_DZ_ETH_BASE_CLASS_ETH2 0 #define ESF_DZ_RX_MAC_CLASS_LBN 35 #define ESF_DZ_RX_MAC_CLASS_WIDTH 1 #define ESE_DZ_MAC_CLASS_MCAST 1 #define ESE_DZ_MAC_CLASS_UCAST 0 #define ESF_DZ_RX_EV_SOFT1_LBN 32 #define ESF_DZ_RX_EV_SOFT1_WIDTH 3 -#define ESF_DZ_RX_EV_RSVD1_LBN 30 -#define ESF_DZ_RX_EV_RSVD1_WIDTH 2 +#define ESF_DZ_RX_EV_RSVD1_LBN 31 +#define ESF_DZ_RX_EV_RSVD1_WIDTH 1 +#define ESF_DZ_RX_ABORT_LBN 30 +#define ESF_DZ_RX_ABORT_WIDTH 1 #define ESF_DZ_RX_ECC_ERR_LBN 29 #define ESF_DZ_RX_ECC_ERR_WIDTH 1 #define ESF_DZ_RX_CRC1_ERR_LBN 28 #define ESF_DZ_RX_CRC1_ERR_WIDTH 1 #define ESF_DZ_RX_CRC0_ERR_LBN 27 #define ESF_DZ_RX_CRC0_ERR_WIDTH 1 #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN 26 #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_WIDTH 1 #define ESF_DZ_RX_IPCKSUM_ERR_LBN 25 #define ESF_DZ_RX_IPCKSUM_ERR_WIDTH 1 #define ESF_DZ_RX_ECRC_ERR_LBN 24 #define ESF_DZ_RX_ECRC_ERR_WIDTH 1 #define ESF_DZ_RX_QLABEL_LBN 16 -#define ESF_DZ_RX_QLABEL_WIDTH 8 +#define ESF_DZ_RX_QLABEL_WIDTH 5 #define ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15 #define ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1 #define ESF_DZ_RX_CONT_LBN 14 #define ESF_DZ_RX_CONT_WIDTH 1 #define ESF_DZ_RX_BYTES_LBN 0 #define ESF_DZ_RX_BYTES_WIDTH 14 /* ES_RX_KER_DESC */ #define ESF_DZ_RX_KER_RESERVED_LBN 62 #define ESF_DZ_RX_KER_RESERVED_WIDTH 2 #define ESF_DZ_RX_KER_BYTE_CNT_LBN 48 #define ESF_DZ_RX_KER_BYTE_CNT_WIDTH 14 #define ESF_DZ_RX_KER_BUF_ADDR_DW0_LBN 0 #define ESF_DZ_RX_KER_BUF_ADDR_DW0_WIDTH 32 #define ESF_DZ_RX_KER_BUF_ADDR_DW1_LBN 32 #define ESF_DZ_RX_KER_BUF_ADDR_DW1_WIDTH 16 #define ESF_DZ_RX_KER_BUF_ADDR_LBN 0 #define ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48 /* ES_RX_USER_DESC */ #define ESF_DZ_RX_USR_RESERVED_LBN 62 #define ESF_DZ_RX_USR_RESERVED_WIDTH 2 #define ESF_DZ_RX_USR_BYTE_CNT_LBN 48 #define ESF_DZ_RX_USR_BYTE_CNT_WIDTH 14 #define ESF_DZ_RX_USR_BUF_PAGE_SIZE_LBN 44 #define ESF_DZ_RX_USR_BUF_PAGE_SIZE_WIDTH 4 #define ESE_DZ_USR_BUF_PAGE_SZ_4MB 10 #define ESE_DZ_USR_BUF_PAGE_SZ_1MB 8 #define ESE_DZ_USR_BUF_PAGE_SZ_64KB 4 #define ESE_DZ_USR_BUF_PAGE_SZ_4KB 0 #define ESF_DZ_RX_USR_BUF_ID_OFFSET_DW0_LBN 0 #define ESF_DZ_RX_USR_BUF_ID_OFFSET_DW0_WIDTH 32 #define ESF_DZ_RX_USR_BUF_ID_OFFSET_DW1_LBN 32 #define ESF_DZ_RX_USR_BUF_ID_OFFSET_DW1_WIDTH 12 #define ESF_DZ_RX_USR_BUF_ID_OFFSET_LBN 0 #define ESF_DZ_RX_USR_BUF_ID_OFFSET_WIDTH 44 #define ESF_DZ_RX_USR_4KBPS_BUF_ID_LBN 12 #define ESF_DZ_RX_USR_4KBPS_BUF_ID_WIDTH 32 #define ESF_DZ_RX_USR_64KBPS_BUF_ID_LBN 16 #define ESF_DZ_RX_USR_64KBPS_BUF_ID_WIDTH 28 #define ESF_DZ_RX_USR_1MBPS_BUF_ID_LBN 20 #define ESF_DZ_RX_USR_1MBPS_BUF_ID_WIDTH 24 #define ESF_DZ_RX_USR_4MBPS_BUF_ID_LBN 22 #define ESF_DZ_RX_USR_4MBPS_BUF_ID_WIDTH 22 #define ESF_DZ_RX_USR_4MBPS_BYTE_OFFSET_LBN 0 #define ESF_DZ_RX_USR_4MBPS_BYTE_OFFSET_WIDTH 22 #define ESF_DZ_RX_USR_1MBPS_BYTE_OFFSET_LBN 0 #define ESF_DZ_RX_USR_1MBPS_BYTE_OFFSET_WIDTH 20 #define ESF_DZ_RX_USR_64KBPS_BYTE_OFFSET_LBN 0 #define ESF_DZ_RX_USR_64KBPS_BYTE_OFFSET_WIDTH 16 #define ESF_DZ_RX_USR_4KBPS_BYTE_OFFSET_LBN 0 #define ESF_DZ_RX_USR_4KBPS_BYTE_OFFSET_WIDTH 12 /* ES_RX_U_QSTATE_TBL0_ENTRY */ #define ESF_DZ_RX_U_DC_FILL_LBN 112 #define ESF_DZ_RX_U_DC_FILL_WIDTH 7 #define ESF_DZ_RX_U_SOFT7_B1R1_0_LBN 112 #define ESF_DZ_RX_U_SOFT7_B1R1_0_WIDTH 7 #define ESF_DZ_RX_U_DSCR_HW_RPTR_LBN 96 #define ESF_DZ_RX_U_DSCR_HW_RPTR_WIDTH 12 #define ESF_DZ_RX_U_SOFT12_B1R2_0_LBN 96 #define ESF_DZ_RX_U_SOFT12_B1R2_0_WIDTH 12 #define ESF_DZ_RX_U_DC_RPTR_LBN 80 #define ESF_DZ_RX_U_DC_RPTR_WIDTH 6 #define ESF_DZ_RX_U_SOFT6_B1R1_0_LBN 80 #define ESF_DZ_RX_U_SOFT6_B1R1_0_WIDTH 6 #define ESF_DZ_RX_U_NOTIFY_PENDING_LBN 70 #define ESF_DZ_RX_U_NOTIFY_PENDING_WIDTH 1 #define ESF_DZ_RX_U_SOFT1_B1R0_6_LBN 70 #define ESF_DZ_RX_U_SOFT1_B1R0_6_WIDTH 1 #define ESF_DZ_RX_U_DATA_ACTIVE_LBN 69 #define ESF_DZ_RX_U_DATA_ACTIVE_WIDTH 1 #define ESF_DZ_RX_U_SOFT1_B1R0_5_LBN 69 #define ESF_DZ_RX_U_SOFT1_B1R0_5_WIDTH 1 #define ESF_DZ_RX_U_FAST_PATH_LBN 68 #define ESF_DZ_RX_U_FAST_PATH_WIDTH 1 #define ESF_DZ_RX_U_SOFT1_B1R0_4_LBN 68 #define ESF_DZ_RX_U_SOFT1_B1R0_4_WIDTH 1 -#define ESF_DZ_RX_U_NO_FLUSH_LBN 67 -#define ESF_DZ_RX_U_NO_FLUSH_WIDTH 1 +#define ESF_DZ_RX_U_CHAIN_LBN 67 +#define ESF_DZ_RX_U_CHAIN_WIDTH 1 #define ESF_DZ_RX_U_SOFT1_B1R0_3_LBN 67 #define ESF_DZ_RX_U_SOFT1_B1R0_3_WIDTH 1 #define ESF_DZ_RX_U_DESC_ACTIVE_LBN 66 #define ESF_DZ_RX_U_DESC_ACTIVE_WIDTH 1 #define ESF_DZ_RX_U_SOFT1_B1R0_2_LBN 66 #define ESF_DZ_RX_U_SOFT1_B1R0_2_WIDTH 1 -#define ESF_DZ_RX_U_HDR_SPLIT_LBN 65 -#define ESF_DZ_RX_U_HDR_SPLIT_WIDTH 1 +#define ESF_DZ_RX_U_TIMESTAMP_LBN 65 +#define ESF_DZ_RX_U_TIMESTAMP_WIDTH 1 #define ESF_DZ_RX_U_SOFT1_B1R0_1_LBN 65 #define ESF_DZ_RX_U_SOFT1_B1R0_1_WIDTH 1 #define ESF_DZ_RX_U_Q_ENABLE_LBN 64 #define ESF_DZ_RX_U_Q_ENABLE_WIDTH 1 #define ESF_DZ_RX_U_SOFT1_B1R0_0_LBN 64 #define ESF_DZ_RX_U_SOFT1_B1R0_0_WIDTH 1 #define ESF_DZ_RX_U_UPD_CRC_MODE_LBN 29 #define ESF_DZ_RX_U_UPD_CRC_MODE_WIDTH 3 #define ESE_DZ_C2RIP_FCOIP_MPA 5 #define ESE_DZ_C2RIP_FCOIP_FCOE 4 #define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 #define ESE_DZ_C2RIP_ISCSI_HDR 2 #define ESE_DZ_C2RIP_FCOE 1 #define ESE_DZ_C2RIP_OFF 0 #define ESF_DZ_RX_U_SOFT16_B0R1_LBN 16 #define ESF_DZ_RX_U_SOFT16_B0R1_WIDTH 16 #define ESF_DZ_RX_U_BIU_ARGS_LBN 16 #define ESF_DZ_RX_U_BIU_ARGS_WIDTH 13 #define ESF_DZ_RX_U_EV_QID_LBN 5 #define ESF_DZ_RX_U_EV_QID_WIDTH 11 #define ESF_DZ_RX_U_SOFT16_B0R0_LBN 0 #define ESF_DZ_RX_U_SOFT16_B0R0_WIDTH 16 #define ESF_DZ_RX_U_EV_QLABEL_LBN 0 #define ESF_DZ_RX_U_EV_QLABEL_WIDTH 5 /* ES_RX_U_QSTATE_TBL1_ENTRY */ #define ESF_DZ_RX_U_DSCR_BASE_PAGE_ID_LBN 64 #define ESF_DZ_RX_U_DSCR_BASE_PAGE_ID_WIDTH 18 #define ESF_DZ_RX_U_SOFT18_B1R0_0_LBN 64 #define ESF_DZ_RX_U_SOFT18_B1R0_0_WIDTH 18 -#define ESF_DZ_RX_U_QST1_SPARE_LBN 52 -#define ESF_DZ_RX_U_QST1_SPARE_WIDTH 12 +#define ESF_DZ_RX_U_QST1_SPARE_LBN 53 +#define ESF_DZ_RX_U_QST1_SPARE_WIDTH 11 #define ESF_DZ_RX_U_SOFT16_B0R3_0_LBN 48 #define ESF_DZ_RX_U_SOFT16_B0R3_0_WIDTH 16 -#define ESF_DZ_RX_U_TIMESTAMP_LBN 51 -#define ESF_DZ_RX_U_TIMESTAMP_WIDTH 1 +#define ESF_DZ_RX_U_NO_FLUSH_LBN 52 +#define ESF_DZ_RX_U_NO_FLUSH_WIDTH 1 +#define ESF_DZ_RX_U_HDR_SPLIT_LBN 51 +#define ESF_DZ_RX_U_HDR_SPLIT_WIDTH 1 #define ESF_DZ_RX_U_DOORBELL_ENABLED_LBN 50 #define ESF_DZ_RX_U_DOORBELL_ENABLED_WIDTH 1 #define ESF_DZ_RX_U_WORK_PENDING_LBN 49 #define ESF_DZ_RX_U_WORK_PENDING_WIDTH 1 #define ESF_DZ_RX_U_ERROR_LBN 48 #define ESF_DZ_RX_U_ERROR_WIDTH 1 #define ESF_DZ_RX_U_DSCR_SW_WPTR_LBN 32 #define ESF_DZ_RX_U_DSCR_SW_WPTR_WIDTH 12 #define ESF_DZ_RX_U_SOFT12_B0R2_0_LBN 32 #define ESF_DZ_RX_U_SOFT12_B0R2_0_WIDTH 12 #define ESF_DZ_RX_U_OWNER_ID_LBN 16 #define ESF_DZ_RX_U_OWNER_ID_WIDTH 12 #define ESF_DZ_RX_U_SOFT12_B0R1_0_LBN 16 #define ESF_DZ_RX_U_SOFT12_B0R1_0_WIDTH 12 #define ESF_DZ_RX_U_DSCR_SIZE_LBN 0 #define ESF_DZ_RX_U_DSCR_SIZE_WIDTH 3 #define ESE_DZ_RX_DSCR_SIZE_512 7 #define ESE_DZ_RX_DSCR_SIZE_1K 6 #define ESE_DZ_RX_DSCR_SIZE_2K 5 #define ESE_DZ_RX_DSCR_SIZE_4K 4 #define ESF_DZ_RX_U_SOFT3_B0R0_0_LBN 0 #define ESF_DZ_RX_U_SOFT3_B0R0_0_WIDTH 3 +/* ES_SGMII_DEV_PTNR_ABILITY_1000BX_MD */ +#define ESF_DZ_SGMII_DPA_NXT_PG_LBN 15 +#define ESF_DZ_SGMII_DPA_NXT_PG_WIDTH 1 +#define ESF_DZ_SGMII_DPA_ACK_LBN 14 +#define ESF_DZ_SGMII_DPA_ACK_WIDTH 1 +#define ESF_DZ_SGMII_DPA_REMOTE_FLT_LBN 12 +#define ESF_DZ_SGMII_DPA_REMOTE_FLT_WIDTH 2 +#define ESE_DZ_SGMII_DPA_RF_AN_ERR 3 +#define ESE_DZ_SGMII_DPA_RF_OFFLINE 2 +#define ESE_DZ_SGMII_DPA_RF_LINK_FAIL 1 +#define ESE_DZ_SGMII_DPA_RF_NONE 0 +#define ESF_DZ_SGMII_DPA_PS_LBN 7 +#define ESF_DZ_SGMII_DPA_PS_WIDTH 2 +#define ESF_DZ_SGMII_DPA_HD_LBN 6 +#define ESF_DZ_SGMII_DPA_HD_WIDTH 1 +#define ESF_DZ_SGMII_DPA_FD_LBN 5 +#define ESF_DZ_SGMII_DPA_FD_WIDTH 1 + + +/* ES_SGMII_DEV_PTNR_ABILITY_SGMII_MD */ +#define ESF_DZ_SGMII_DPA_CPR_LINK_STATE_LBN 15 +#define ESF_DZ_SGMII_DPA_CPR_LINK_STATE_WIDTH 1 +#define ESF_DZ_SGMII_DPA_ACK_LBN 14 +#define ESF_DZ_SGMII_DPA_ACK_WIDTH 1 +#define ESF_DZ_SGMII_CPR_BPLX_STS_LBN 12 +#define ESF_DZ_SGMII_CPR_BPLX_STS_WIDTH 1 +#define ESF_DZ_SGMII_DPA_COPPER_SPEED_LBN 10 +#define ESF_DZ_SGMII_DPA_COPPER_SPEED_WIDTH 2 +#define ESE_DZ_SGMII_DPA_CPR_1GBS 2 +#define ESE_DZ_SGMII_DPA_CPR_100MBS 1 +#define ESE_DZ_SGMII_DPA_CPR_10MBS 0 + + /* ES_SMC_BUFTBL_CNTRL_ENTRY */ #define ESF_DZ_SMC_SW_CNTXT_DW0_LBN 16 #define ESF_DZ_SMC_SW_CNTXT_DW0_WIDTH 32 #define ESF_DZ_SMC_SW_CNTXT_DW1_LBN 48 #define ESF_DZ_SMC_SW_CNTXT_DW1_WIDTH 24 #define ESF_DZ_SMC_SW_CNTXT_LBN 16 #define ESF_DZ_SMC_SW_CNTXT_WIDTH 56 #define ESF_DZ_SMC_PAGE_SIZE_LBN 12 #define ESF_DZ_SMC_PAGE_SIZE_WIDTH 4 #define ESF_DZ_SMC_OWNER_ID_LBN 0 #define ESF_DZ_SMC_OWNER_ID_WIDTH 12 /* ES_SMC_BUFTBL_TRANSL_ENTRY */ #define ESF_DZ_SMC_PAGE_INDEX0_DW0_LBN 36 #define ESF_DZ_SMC_PAGE_INDEX0_DW0_WIDTH 32 #define ESF_DZ_SMC_PAGE_INDEX0_DW1_LBN 68 #define ESF_DZ_SMC_PAGE_INDEX0_DW1_WIDTH 4 #define ESF_DZ_SMC_PAGE_INDEX0_LBN 36 #define ESF_DZ_SMC_PAGE_INDEX0_WIDTH 36 #define ESF_DZ_SMC_PAGE_INDEX1_DW0_LBN 0 #define ESF_DZ_SMC_PAGE_INDEX1_DW0_WIDTH 32 #define ESF_DZ_SMC_PAGE_INDEX1_DW1_LBN 32 #define ESF_DZ_SMC_PAGE_INDEX1_DW1_WIDTH 4 #define ESF_DZ_SMC_PAGE_INDEX1_LBN 0 #define ESF_DZ_SMC_PAGE_INDEX1_WIDTH 36 /* ES_SMC_DSCR_CACHE_ENTRY */ #define ESF_DZ_SMC_BTE_PAD_LBN 64 #define ESF_DZ_SMC_BTE_PAD_WIDTH 8 #define ESF_DZ_SMC_DSCR_DW0_LBN 0 #define ESF_DZ_SMC_DSCR_DW0_WIDTH 32 #define ESF_DZ_SMC_DSCR_DW1_LBN 32 #define ESF_DZ_SMC_DSCR_DW1_WIDTH 32 #define ESF_DZ_SMC_DSCR_LBN 0 #define ESF_DZ_SMC_DSCR_WIDTH 64 /* ES_SMC_GEN_STORAGE_ENTRY */ #define ESF_DZ_SMC_DATA_DW0_LBN 0 #define ESF_DZ_SMC_DATA_DW0_WIDTH 32 #define ESF_DZ_SMC_DATA_DW1_LBN 32 #define ESF_DZ_SMC_DATA_DW1_WIDTH 32 #define ESF_DZ_SMC_DATA_DW2_LBN 64 #define ESF_DZ_SMC_DATA_DW2_WIDTH 8 #define ESF_DZ_SMC_DATA_LBN 0 #define ESF_DZ_SMC_DATA_WIDTH 72 /* ES_SMC_MSG_BASE_REQ */ #define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_DW0_LBN 11 #define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_DW0_WIDTH 32 #define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_DW1_LBN 43 #define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_DW1_WIDTH 32 #define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_DW2_LBN 75 #define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_DW2_WIDTH 26 #define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_LBN 11 #define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_WIDTH 90 #define ESF_DZ_MC2S_BASE_SOFT_LBN 7 #define ESF_DZ_MC2S_BASE_SOFT_WIDTH 4 #define ESF_DZ_MC2S_BASE_CLIENT_ID_LBN 3 #define ESF_DZ_MC2S_BASE_CLIENT_ID_WIDTH 4 #define ESE_DZ_SMC_MACRO_ENGINE_ID 15 #define ESE_DZ_SMC_TX_DICPU_ID 14 #define ESE_DZ_SMC_RX_DICPU_ID 13 #define ESE_DZ_SMC_MC_ID 12 #define ESE_DZ_SMC_DL_ID 10 #define ESE_DZ_SMC_EV_ID 8 #define ESE_DZ_SMC_TX_DPCPU1_ID 5 #define ESE_DZ_SMC_TX_DPCPU0_ID 4 #define ESE_DZ_SMC_RX_DPCPU_ID 0 #define ESF_DZ_MC2S_BASE_OP_LBN 0 #define ESF_DZ_MC2S_BASE_OP_WIDTH 3 #define ESE_DZ_SMC_REQ_WR 4 #define ESE_DZ_SMC_RESP_WR 4 #define ESE_DZ_SMC_REQ_RD 3 #define ESE_DZ_SMC_RESP_RD 3 #define ESE_DZ_SMC_REQ_DSCR_WRITE 2 #define ESE_DZ_SMC_RESP_DSCR_WRITE 2 #define ESE_DZ_SMC_REQ_DSCR_READ 1 #define ESE_DZ_SMC_RESP_DSCR_READ 1 #define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 #define ESE_DZ_SMC_RESP_BUFTBL_LOOKUP 0 /* ES_SMC_MSG_BUFTBL_LOOKUP_REQ */ #define ESF_DZ_MC2S_BL_BUF_ID_LBN 28 #define ESF_DZ_MC2S_BL_BUF_ID_WIDTH 18 #define ESF_DZ_MC2S_BL_EXP_PAGE_SIZE_LBN 24 #define ESF_DZ_MC2S_BL_EXP_PAGE_SIZE_WIDTH 4 #define ESE_DZ_SMC_PAGE_SIZE_4M 10 #define ESE_DZ_SMC_PAGE_SIZE_1M 8 #define ESE_DZ_SMC_PAGE_SIZE_64K 4 #define ESE_DZ_SMC_PAGE_SIZE_4K 0 #define ESF_DZ_MC2S_BL_EXP_OWNER_ID_LBN 12 #define ESF_DZ_MC2S_BL_EXP_OWNER_ID_WIDTH 12 #define ESF_DZ_MC2S_BL_REFLECT_LBN 11 #define ESF_DZ_MC2S_BL_REFLECT_WIDTH 1 #define ESF_DZ_MC2S_BL_SOFT_LBN 7 #define ESF_DZ_MC2S_BL_SOFT_WIDTH 4 #define ESF_DZ_MC2S_BL_CLIENT_ID_LBN 3 #define ESF_DZ_MC2S_BL_CLIENT_ID_WIDTH 4 #define ESE_DZ_SMC_MACRO_ENGINE_ID 15 #define ESE_DZ_SMC_TX_DICPU_ID 14 #define ESE_DZ_SMC_RX_DICPU_ID 13 #define ESE_DZ_SMC_MC_ID 12 #define ESE_DZ_SMC_DL_ID 10 #define ESE_DZ_SMC_EV_ID 8 #define ESE_DZ_SMC_TX_DPCPU1_ID 5 #define ESE_DZ_SMC_TX_DPCPU0_ID 4 #define ESE_DZ_SMC_RX_DPCPU_ID 0 #define ESF_DZ_MC2S_BL_OP_LBN 0 #define ESF_DZ_MC2S_BL_OP_WIDTH 3 #define ESE_DZ_SMC_REQ_WR 4 #define ESE_DZ_SMC_REQ_RD 3 #define ESE_DZ_SMC_REQ_DSCR_WRITE 2 #define ESE_DZ_SMC_REQ_DSCR_READ 1 #define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 /* ES_SMC_MSG_BUFTBL_LOOKUP_RESP */ #define ESF_DZ_S2MC_BL_BUFTBL_ENTRY_DW0_LBN 12 #define ESF_DZ_S2MC_BL_BUFTBL_ENTRY_DW0_WIDTH 32 #define ESF_DZ_S2MC_BL_BUFTBL_ENTRY_DW1_LBN 44 #define ESF_DZ_S2MC_BL_BUFTBL_ENTRY_DW1_WIDTH 4 #define ESF_DZ_S2MC_BL_BUFTBL_ENTRY_LBN 12 #define ESF_DZ_S2MC_BL_BUFTBL_ENTRY_WIDTH 36 #define ESF_DZ_S2MC_BL_FAIL_LBN 11 #define ESF_DZ_S2MC_BL_FAIL_WIDTH 1 #define ESF_DZ_S2MC_BL_SOFT_LBN 7 #define ESF_DZ_S2MC_BL_SOFT_WIDTH 4 #define ESF_DZ_S2MC_BL_CLIENT_ID_LBN 3 #define ESF_DZ_S2MC_BL_CLIENT_ID_WIDTH 4 #define ESE_DZ_SMC_MACRO_ENGINE_ID 15 #define ESE_DZ_SMC_TX_DICPU_ID 14 #define ESE_DZ_SMC_RX_DICPU_ID 13 #define ESE_DZ_SMC_MC_ID 12 #define ESE_DZ_SMC_DL_ID 10 #define ESE_DZ_SMC_EV_ID 8 #define ESE_DZ_SMC_TX_DPCPU1_ID 5 #define ESE_DZ_SMC_TX_DPCPU0_ID 4 #define ESE_DZ_SMC_RX_DPCPU_ID 0 #define ESF_DZ_S2MC_BL_OP_LBN 0 #define ESF_DZ_S2MC_BL_OP_WIDTH 3 #define ESE_DZ_SMC_REQ_WR 4 #define ESE_DZ_SMC_REQ_RD 3 #define ESE_DZ_SMC_REQ_DSCR_WRITE 2 #define ESE_DZ_SMC_REQ_DSCR_READ 1 #define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 /* ES_SMC_MSG_DSCR_RD_REQ */ #define ESF_DZ_MC2S_DR_DSCR_OFST_LBN 24 #define ESF_DZ_MC2S_DR_DSCR_OFST_WIDTH 6 #define ESF_DZ_MC2S_DR_QID_LBN 13 #define ESF_DZ_MC2S_DR_QID_WIDTH 11 #define ESF_DZ_MC2S_DR_IS_TX_LBN 12 #define ESF_DZ_MC2S_DR_IS_TX_WIDTH 1 #define ESF_DZ_MC2S_DR_REFLECT_LBN 11 #define ESF_DZ_MC2S_DR_REFLECT_WIDTH 1 #define ESF_DZ_MC2S_DR_SOFT_LBN 7 #define ESF_DZ_MC2S_DR_SOFT_WIDTH 4 #define ESF_DZ_MC2S_DR_CLIENT_ID_LBN 3 #define ESF_DZ_MC2S_DR_CLIENT_ID_WIDTH 4 #define ESE_DZ_SMC_MACRO_ENGINE_ID 15 #define ESE_DZ_SMC_TX_DICPU_ID 14 #define ESE_DZ_SMC_RX_DICPU_ID 13 #define ESE_DZ_SMC_MC_ID 12 #define ESE_DZ_SMC_DL_ID 10 #define ESE_DZ_SMC_EV_ID 8 #define ESE_DZ_SMC_TX_DPCPU1_ID 5 #define ESE_DZ_SMC_TX_DPCPU0_ID 4 #define ESE_DZ_SMC_RX_DPCPU_ID 0 #define ESF_DZ_MC2S_DR_OP_LBN 0 #define ESF_DZ_MC2S_DR_OP_WIDTH 3 #define ESE_DZ_SMC_REQ_WR 4 #define ESE_DZ_SMC_REQ_RD 3 #define ESE_DZ_SMC_REQ_DSCR_WRITE 2 #define ESE_DZ_SMC_REQ_DSCR_READ 1 #define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 /* ES_SMC_MSG_DSCR_RD_RESP */ #define ESF_DZ_S2MC_DR_DSCR_DW0_LBN 12 #define ESF_DZ_S2MC_DR_DSCR_DW0_WIDTH 32 #define ESF_DZ_S2MC_DR_DSCR_DW1_LBN 44 #define ESF_DZ_S2MC_DR_DSCR_DW1_WIDTH 32 #define ESF_DZ_S2MC_DR_DSCR_LBN 12 #define ESF_DZ_S2MC_DR_DSCR_WIDTH 64 #define ESF_DZ_S2MC_DR_FAIL_LBN 11 #define ESF_DZ_S2MC_DR_FAIL_WIDTH 1 #define ESF_DZ_S2MC_DR_SOFT_LBN 7 #define ESF_DZ_S2MC_DR_SOFT_WIDTH 4 #define ESF_DZ_S2MC_DR_CLIENT_ID_LBN 3 #define ESF_DZ_S2MC_DR_CLIENT_ID_WIDTH 4 #define ESE_DZ_SMC_MACRO_ENGINE_ID 15 #define ESE_DZ_SMC_TX_DICPU_ID 14 #define ESE_DZ_SMC_RX_DICPU_ID 13 #define ESE_DZ_SMC_MC_ID 12 #define ESE_DZ_SMC_DL_ID 10 #define ESE_DZ_SMC_EV_ID 8 #define ESE_DZ_SMC_TX_DPCPU1_ID 5 #define ESE_DZ_SMC_TX_DPCPU0_ID 4 #define ESE_DZ_SMC_RX_DPCPU_ID 0 #define ESF_DZ_S2MC_DR_OP_LBN 0 #define ESF_DZ_S2MC_DR_OP_WIDTH 3 #define ESE_DZ_SMC_REQ_WR 4 #define ESE_DZ_SMC_REQ_RD 3 #define ESE_DZ_SMC_REQ_DSCR_WRITE 2 #define ESE_DZ_SMC_REQ_DSCR_READ 1 #define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 /* ES_SMC_MSG_DSCR_WR_REQ */ #define ESF_DZ_MC2S_DW_DSCR_DW0_LBN 30 #define ESF_DZ_MC2S_DW_DSCR_DW0_WIDTH 32 #define ESF_DZ_MC2S_DW_DSCR_DW1_LBN 62 #define ESF_DZ_MC2S_DW_DSCR_DW1_WIDTH 32 #define ESF_DZ_MC2S_DW_DSCR_LBN 30 #define ESF_DZ_MC2S_DW_DSCR_WIDTH 64 #define ESF_DZ_MC2S_DW_DSCR_OFST_LBN 24 #define ESF_DZ_MC2S_DW_DSCR_OFST_WIDTH 6 #define ESF_DZ_MC2S_DW_QID_LBN 13 #define ESF_DZ_MC2S_DW_QID_WIDTH 11 #define ESF_DZ_MC2S_DW_IS_TX_LBN 12 #define ESF_DZ_MC2S_DW_IS_TX_WIDTH 1 #define ESF_DZ_MC2S_DW_REFLECT_LBN 11 #define ESF_DZ_MC2S_DW_REFLECT_WIDTH 1 #define ESF_DZ_MC2S_DW_SOFT_LBN 7 #define ESF_DZ_MC2S_DW_SOFT_WIDTH 4 #define ESF_DZ_MC2S_DW_CLIENT_ID_LBN 3 #define ESF_DZ_MC2S_DW_CLIENT_ID_WIDTH 4 #define ESE_DZ_SMC_MACRO_ENGINE_ID 15 #define ESE_DZ_SMC_TX_DICPU_ID 14 #define ESE_DZ_SMC_RX_DICPU_ID 13 #define ESE_DZ_SMC_MC_ID 12 #define ESE_DZ_SMC_DL_ID 10 #define ESE_DZ_SMC_EV_ID 8 #define ESE_DZ_SMC_TX_DPCPU1_ID 5 #define ESE_DZ_SMC_TX_DPCPU0_ID 4 #define ESE_DZ_SMC_RX_DPCPU_ID 0 #define ESF_DZ_MC2S_DW_OP_LBN 0 #define ESF_DZ_MC2S_DW_OP_WIDTH 3 #define ESE_DZ_SMC_REQ_WR 4 #define ESE_DZ_SMC_REQ_RD 3 #define ESE_DZ_SMC_REQ_DSCR_WRITE 2 #define ESE_DZ_SMC_REQ_DSCR_READ 1 #define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 /* ES_SMC_MSG_DSCR_WR_RESP */ #define ESF_DZ_S2MC_DW_FAIL_LBN 11 #define ESF_DZ_S2MC_DW_FAIL_WIDTH 1 #define ESF_DZ_S2MC_DW_SOFT_LBN 7 #define ESF_DZ_S2MC_DW_SOFT_WIDTH 4 #define ESF_DZ_S2MC_DW_CLIENT_ID_LBN 3 #define ESF_DZ_S2MC_DW_CLIENT_ID_WIDTH 4 #define ESE_DZ_SMC_MACRO_ENGINE_ID 15 #define ESE_DZ_SMC_TX_DICPU_ID 14 #define ESE_DZ_SMC_RX_DICPU_ID 13 #define ESE_DZ_SMC_MC_ID 12 #define ESE_DZ_SMC_DL_ID 10 #define ESE_DZ_SMC_EV_ID 8 #define ESE_DZ_SMC_TX_DPCPU1_ID 5 #define ESE_DZ_SMC_TX_DPCPU0_ID 4 #define ESE_DZ_SMC_RX_DPCPU_ID 0 #define ESF_DZ_S2MC_DW_OP_LBN 0 #define ESF_DZ_S2MC_DW_OP_WIDTH 3 #define ESE_DZ_SMC_REQ_WR 4 #define ESE_DZ_SMC_REQ_RD 3 #define ESE_DZ_SMC_REQ_DSCR_WRITE 2 #define ESE_DZ_SMC_REQ_DSCR_READ 1 #define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 /* ES_SMC_MSG_RD_REQ */ #define ESF_DZ_MC2S_RD_ADDR_LBN 12 #define ESF_DZ_MC2S_RD_ADDR_WIDTH 17 #define ESF_DZ_MC2S_RD_REFLECT_LBN 11 #define ESF_DZ_MC2S_RD_REFLECT_WIDTH 1 #define ESF_DZ_MC2S_RD_SOFT_LBN 7 #define ESF_DZ_MC2S_RD_SOFT_WIDTH 4 #define ESF_DZ_MC2S_RD_CLIENT_ID_LBN 3 #define ESF_DZ_MC2S_RD_CLIENT_ID_WIDTH 4 #define ESE_DZ_SMC_MACRO_ENGINE_ID 15 #define ESE_DZ_SMC_TX_DICPU_ID 14 #define ESE_DZ_SMC_RX_DICPU_ID 13 #define ESE_DZ_SMC_MC_ID 12 #define ESE_DZ_SMC_DL_ID 10 #define ESE_DZ_SMC_EV_ID 8 #define ESE_DZ_SMC_TX_DPCPU1_ID 5 #define ESE_DZ_SMC_TX_DPCPU0_ID 4 #define ESE_DZ_SMC_RX_DPCPU_ID 0 #define ESF_DZ_MC2S_RD_OP_LBN 0 #define ESF_DZ_MC2S_RD_OP_WIDTH 3 #define ESE_DZ_SMC_REQ_WR 4 #define ESE_DZ_SMC_REQ_RD 3 #define ESE_DZ_SMC_REQ_DSCR_WRITE 2 #define ESE_DZ_SMC_REQ_DSCR_READ 1 #define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 /* ES_SMC_MSG_RD_RESP */ #define ESF_DZ_S2MC_RD_DATA_DW0_LBN 12 #define ESF_DZ_S2MC_RD_DATA_DW0_WIDTH 32 #define ESF_DZ_S2MC_RD_DATA_DW1_LBN 44 #define ESF_DZ_S2MC_RD_DATA_DW1_WIDTH 32 #define ESF_DZ_S2MC_RD_DATA_DW2_LBN 76 #define ESF_DZ_S2MC_RD_DATA_DW2_WIDTH 8 #define ESF_DZ_S2MC_RD_DATA_LBN 12 #define ESF_DZ_S2MC_RD_DATA_WIDTH 72 #define ESF_DZ_S2MC_RD_FAIL_LBN 11 #define ESF_DZ_S2MC_RD_FAIL_WIDTH 1 #define ESF_DZ_S2MC_RD_SOFT_LBN 7 #define ESF_DZ_S2MC_RD_SOFT_WIDTH 4 #define ESF_DZ_S2MC_RD_CLIENT_ID_LBN 3 #define ESF_DZ_S2MC_RD_CLIENT_ID_WIDTH 4 #define ESE_DZ_SMC_MACRO_ENGINE_ID 15 #define ESE_DZ_SMC_TX_DICPU_ID 14 #define ESE_DZ_SMC_RX_DICPU_ID 13 #define ESE_DZ_SMC_MC_ID 12 #define ESE_DZ_SMC_DL_ID 10 #define ESE_DZ_SMC_EV_ID 8 #define ESE_DZ_SMC_TX_DPCPU1_ID 5 #define ESE_DZ_SMC_TX_DPCPU0_ID 4 #define ESE_DZ_SMC_RX_DPCPU_ID 0 #define ESF_DZ_S2MC_RD_OP_LBN 0 #define ESF_DZ_S2MC_RD_OP_WIDTH 3 #define ESE_DZ_SMC_REQ_WR 4 #define ESE_DZ_SMC_REQ_RD 3 #define ESE_DZ_SMC_REQ_DSCR_WRITE 2 #define ESE_DZ_SMC_REQ_DSCR_READ 1 #define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 /* ES_SMC_MSG_RESP */ #define ESF_DZ_S2MC_BASE_RSP_DATA_DW0_LBN 12 #define ESF_DZ_S2MC_BASE_RSP_DATA_DW0_WIDTH 32 #define ESF_DZ_S2MC_BASE_RSP_DATA_DW1_LBN 44 #define ESF_DZ_S2MC_BASE_RSP_DATA_DW1_WIDTH 32 #define ESF_DZ_S2MC_BASE_RSP_DATA_DW2_LBN 76 #define ESF_DZ_S2MC_BASE_RSP_DATA_DW2_WIDTH 8 #define ESF_DZ_S2MC_BASE_RSP_DATA_LBN 12 #define ESF_DZ_S2MC_BASE_RSP_DATA_WIDTH 72 #define ESF_DZ_S2MC_BASE_FAIL_LBN 11 #define ESF_DZ_S2MC_BASE_FAIL_WIDTH 1 #define ESF_DZ_S2MC_BASE_SOFT_LBN 7 #define ESF_DZ_S2MC_BASE_SOFT_WIDTH 4 #define ESF_DZ_S2MC_BASE_CLIENT_ID_LBN 3 #define ESF_DZ_S2MC_BASE_CLIENT_ID_WIDTH 4 #define ESE_DZ_SMC_MACRO_ENGINE_ID 15 #define ESE_DZ_SMC_TX_DICPU_ID 14 #define ESE_DZ_SMC_RX_DICPU_ID 13 #define ESE_DZ_SMC_MC_ID 12 #define ESE_DZ_SMC_DL_ID 10 #define ESE_DZ_SMC_EV_ID 8 #define ESE_DZ_SMC_TX_DPCPU1_ID 5 #define ESE_DZ_SMC_TX_DPCPU0_ID 4 #define ESE_DZ_SMC_RX_DPCPU_ID 0 #define ESF_DZ_S2MC_BASE_OP_LBN 0 #define ESF_DZ_S2MC_BASE_OP_WIDTH 3 #define ESE_DZ_SMC_REQ_WR 4 #define ESE_DZ_SMC_REQ_RD 3 #define ESE_DZ_SMC_REQ_DSCR_WRITE 2 #define ESE_DZ_SMC_REQ_DSCR_READ 1 #define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 /* ES_SMC_MSG_WR_REQ */ #define ESF_DZ_MC2S_WR_DATA_DW0_LBN 29 #define ESF_DZ_MC2S_WR_DATA_DW0_WIDTH 32 #define ESF_DZ_MC2S_WR_DATA_DW1_LBN 61 #define ESF_DZ_MC2S_WR_DATA_DW1_WIDTH 32 #define ESF_DZ_MC2S_WR_DATA_DW2_LBN 93 #define ESF_DZ_MC2S_WR_DATA_DW2_WIDTH 8 #define ESF_DZ_MC2S_WR_DATA_LBN 29 #define ESF_DZ_MC2S_WR_DATA_WIDTH 72 #define ESF_DZ_MC2S_WR_ADDR_LBN 12 #define ESF_DZ_MC2S_WR_ADDR_WIDTH 17 #define ESF_DZ_MC2S_WR_REFLECT_LBN 11 #define ESF_DZ_MC2S_WR_REFLECT_WIDTH 1 #define ESF_DZ_MC2S_WR_SOFT_LBN 7 #define ESF_DZ_MC2S_WR_SOFT_WIDTH 4 #define ESF_DZ_MC2S_WR_CLIENT_ID_LBN 3 #define ESF_DZ_MC2S_WR_CLIENT_ID_WIDTH 4 #define ESE_DZ_SMC_MACRO_ENGINE_ID 15 #define ESE_DZ_SMC_TX_DICPU_ID 14 #define ESE_DZ_SMC_RX_DICPU_ID 13 #define ESE_DZ_SMC_MC_ID 12 #define ESE_DZ_SMC_DL_ID 10 #define ESE_DZ_SMC_EV_ID 8 #define ESE_DZ_SMC_TX_DPCPU1_ID 5 #define ESE_DZ_SMC_TX_DPCPU0_ID 4 #define ESE_DZ_SMC_RX_DPCPU_ID 0 #define ESF_DZ_MC2S_WR_OP_LBN 0 #define ESF_DZ_MC2S_WR_OP_WIDTH 3 #define ESE_DZ_SMC_REQ_WR 4 #define ESE_DZ_SMC_REQ_RD 3 #define ESE_DZ_SMC_REQ_DSCR_WRITE 2 #define ESE_DZ_SMC_REQ_DSCR_READ 1 #define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 /* ES_SMC_MSG_WR_RESP */ #define ESF_DZ_S2MC_WR_FAIL_LBN 11 #define ESF_DZ_S2MC_WR_FAIL_WIDTH 1 #define ESF_DZ_S2MC_WR_SOFT_LBN 7 #define ESF_DZ_S2MC_WR_SOFT_WIDTH 4 #define ESF_DZ_S2MC_WR_CLIENT_ID_LBN 3 #define ESF_DZ_S2MC_WR_CLIENT_ID_WIDTH 4 #define ESE_DZ_SMC_MACRO_ENGINE_ID 15 #define ESE_DZ_SMC_TX_DICPU_ID 14 #define ESE_DZ_SMC_RX_DICPU_ID 13 #define ESE_DZ_SMC_MC_ID 12 #define ESE_DZ_SMC_DL_ID 10 #define ESE_DZ_SMC_EV_ID 8 #define ESE_DZ_SMC_TX_DPCPU1_ID 5 #define ESE_DZ_SMC_TX_DPCPU0_ID 4 #define ESE_DZ_SMC_RX_DPCPU_ID 0 #define ESF_DZ_S2MC_WR_OP_LBN 0 #define ESF_DZ_S2MC_WR_OP_WIDTH 3 #define ESE_DZ_SMC_REQ_WR 4 #define ESE_DZ_SMC_REQ_RD 3 #define ESE_DZ_SMC_REQ_DSCR_WRITE 2 #define ESE_DZ_SMC_REQ_DSCR_READ 1 #define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 +/* ES_TX_CSUM_TSTAMP_DESC */ +#define ESF_DZ_TX_DESC_IS_OPT_LBN 63 +#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 +#define ESF_DZ_TX_OPTION_TYPE_LBN 60 +#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 +#define ESE_DZ_TX_OPTION_DESC_TSO 7 +#define ESE_DZ_TX_OPTION_DESC_VLAN 6 +#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 +#define ESF_DZ_TX_TIMESTAMP_LBN 5 +#define ESF_DZ_TX_TIMESTAMP_WIDTH 1 +#define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2 +#define ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3 +#define ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5 +#define ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4 +#define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3 +#define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2 +#define ESE_DZ_TX_OPTION_CRC_FCOE 1 +#define ESE_DZ_TX_OPTION_CRC_OFF 0 +#define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1 +#define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1 +#define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0 +#define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1 + + /* ES_TX_EVENT */ #define ESF_DZ_TX_CODE_LBN 60 #define ESF_DZ_TX_CODE_WIDTH 4 #define ESF_DZ_TX_OVERRIDE_HOLDOFF_LBN 59 #define ESF_DZ_TX_OVERRIDE_HOLDOFF_WIDTH 1 #define ESF_DZ_TX_DROP_EVENT_LBN 58 #define ESF_DZ_TX_DROP_EVENT_WIDTH 1 #define ESF_DZ_TX_EV_RSVD_LBN 48 #define ESF_DZ_TX_EV_RSVD_WIDTH 10 #define ESF_DZ_TX_SOFT2_LBN 32 #define ESF_DZ_TX_SOFT2_WIDTH 16 +#define ESF_DZ_TX_CAN_MERGE_LBN 31 +#define ESF_DZ_TX_CAN_MERGE_WIDTH 1 #define ESF_DZ_TX_SOFT1_LBN 24 -#define ESF_DZ_TX_SOFT1_WIDTH 8 +#define ESF_DZ_TX_SOFT1_WIDTH 7 #define ESF_DZ_TX_QLABEL_LBN 16 -#define ESF_DZ_TX_QLABEL_WIDTH 8 +#define ESF_DZ_TX_QLABEL_WIDTH 5 #define ESF_DZ_TX_DESCR_INDX_LBN 0 #define ESF_DZ_TX_DESCR_INDX_WIDTH 16 /* ES_TX_KER_DESC */ #define ESF_DZ_TX_KER_TYPE_LBN 63 #define ESF_DZ_TX_KER_TYPE_WIDTH 1 #define ESF_DZ_TX_KER_CONT_LBN 62 #define ESF_DZ_TX_KER_CONT_WIDTH 1 #define ESF_DZ_TX_KER_BYTE_CNT_LBN 48 #define ESF_DZ_TX_KER_BYTE_CNT_WIDTH 14 #define ESF_DZ_TX_KER_BUF_ADDR_DW0_LBN 0 #define ESF_DZ_TX_KER_BUF_ADDR_DW0_WIDTH 32 #define ESF_DZ_TX_KER_BUF_ADDR_DW1_LBN 32 #define ESF_DZ_TX_KER_BUF_ADDR_DW1_WIDTH 16 #define ESF_DZ_TX_KER_BUF_ADDR_LBN 0 #define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48 -/* ES_TX_OPTION_DESC */ +/* ES_TX_PIO_DESC */ +#define ESF_DZ_TX_PIO_TYPE_LBN 63 +#define ESF_DZ_TX_PIO_TYPE_WIDTH 1 +#define ESF_DZ_TX_PIO_OPT_LBN 60 +#define ESF_DZ_TX_PIO_OPT_WIDTH 3 +#define ESF_DZ_TX_PIO_CONT_LBN 59 +#define ESF_DZ_TX_PIO_CONT_WIDTH 1 +#define ESF_DZ_TX_PIO_BYTE_CNT_LBN 32 +#define ESF_DZ_TX_PIO_BYTE_CNT_WIDTH 12 +#define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0 +#define ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12 + + +/* ES_TX_TSO_DESC */ #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 -#define ESE_DZ_TX_OPTION_DESC_TSO 4 +#define ESE_DZ_TX_OPTION_DESC_TSO 7 +#define ESE_DZ_TX_OPTION_DESC_VLAN 6 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 #define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48 #define ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8 -#define ESF_DZ_TX_TSO_TCP_MSS_LBN 32 -#define ESF_DZ_TX_TSO_TCP_MSS_WIDTH 16 +#define ESF_DZ_TX_TSO_IP_ID_LBN 32 +#define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 -#define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2 -#define ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3 -#define ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5 -#define ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4 -#define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3 -#define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2 -#define ESE_DZ_TX_OPTION_CRC_FCOE 1 -#define ESE_DZ_TX_OPTION_CRC_OFF 0 -#define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1 -#define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1 -#define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0 -#define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1 -/* ES_TX_PACER_BASE_MSG */ -#define ESF_DZ_TXP_BASE_REQ_MSG_DATA_DW0_LBN 11 -#define ESF_DZ_TXP_BASE_REQ_MSG_DATA_DW0_WIDTH 32 -#define ESF_DZ_TXP_BASE_REQ_MSG_DATA_DW1_LBN 43 -#define ESF_DZ_TXP_BASE_REQ_MSG_DATA_DW1_WIDTH 32 -#define ESF_DZ_TXP_BASE_REQ_MSG_DATA_DW2_LBN 75 -#define ESF_DZ_TXP_BASE_REQ_MSG_DATA_DW2_WIDTH 23 -#define ESF_DZ_TXP_BASE_REQ_MSG_DATA_LBN 11 -#define ESF_DZ_TXP_BASE_REQ_MSG_DATA_WIDTH 87 -#define ESF_DZ_TXP_BASE_OP_LBN 2 -#define ESF_DZ_TXP_BASE_OP_WIDTH 3 -#define ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7 -#define ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6 -#define ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5 -#define ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4 -#define ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3 -#define ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2 -#define ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1 -#define ESE_DZ_DPCPU_PACER_BKT_D_RD 0 -#define ESF_DZ_TXP_BASE_CLIENT_ID_LBN 0 -#define ESF_DZ_TXP_BASE_CLIENT_ID_WIDTH 2 -#define ESE_DZ_DPCPU_PACER_CPU_CLIENT 2 -#define ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1 -#define ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0 - - -/* ES_TX_PACER_BKT_D_R_REQ */ -#define ESF_DZ_TXP_BKT_D_R_REQ_FRM_LEN_LBN 45 -#define ESF_DZ_TXP_BKT_D_R_REQ_FRM_LEN_WIDTH 14 -#define ESF_DZ_TXP_BKT_D_R_REQ_MAX_BKT2_LBN 35 -#define ESF_DZ_TXP_BKT_D_R_REQ_MAX_BKT2_WIDTH 10 -#define ESF_DZ_TXP_BKT_D_R_REQ_MAX_BKT1_LBN 25 -#define ESF_DZ_TXP_BKT_D_R_REQ_MAX_BKT1_WIDTH 10 -#define ESF_DZ_TXP_BKT_D_R_REQ_MAX_BKT0_LBN 15 -#define ESF_DZ_TXP_BKT_D_R_REQ_MAX_BKT0_WIDTH 10 -#define ESF_DZ_TXP_BKT_D_R_REQ_MIN_BKT_LBN 5 -#define ESF_DZ_TXP_BKT_D_R_REQ_MIN_BKT_WIDTH 10 -#define ESF_DZ_TXP_BKT_D_R_REQ_OP_LBN 2 -#define ESF_DZ_TXP_BKT_D_R_REQ_OP_WIDTH 3 -#define ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7 -#define ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6 -#define ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5 -#define ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4 -#define ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3 -#define ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2 -#define ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1 -#define ESE_DZ_DPCPU_PACER_BKT_D_RD 0 -#define ESF_DZ_TXP_BKT_D_R_REQ_CLIENT_ID_LBN 0 -#define ESF_DZ_TXP_BKT_D_R_REQ_CLIENT_ID_WIDTH 2 -#define ESE_DZ_DPCPU_PACER_CPU_CLIENT 2 -#define ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1 -#define ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0 - - -/* ES_TX_PACER_BKT_TBL_D_R_RSP */ -#define ESF_DZ_TXP_BKT_TBL_D_R_RSP_DUE_TIME_WITH_MIN_BKT_LBN 21 -#define ESF_DZ_TXP_BKT_TBL_D_R_RSP_DUE_TIME_WITH_MIN_BKT_WIDTH 26 -#define ESF_DZ_TXP_BKT_TBL_D_R_RSP_DUE_TIME_LBN 5 -#define ESF_DZ_TXP_BKT_TBL_D_R_RSP_DUE_TIME_WIDTH 16 -#define ESF_DZ_TXP_BKT_TBL_D_R_RSP_OP_LBN 2 -#define ESF_DZ_TXP_BKT_TBL_D_R_RSP_OP_WIDTH 3 -#define ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7 -#define ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6 -#define ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5 -#define ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4 -#define ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3 -#define ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2 -#define ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1 -#define ESE_DZ_DPCPU_PACER_BKT_D_RD 0 -#define ESF_DZ_TXP_BKT_TBL_D_R_RSP_CLIENT_ID_LBN 0 -#define ESF_DZ_TXP_BKT_TBL_D_R_RSP_CLIENT_ID_WIDTH 2 -#define ESE_DZ_DPCPU_PACER_CPU_CLIENT 2 -#define ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1 -#define ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0 - - -/* ES_TX_PACER_BKT_TBL_RD_REQ */ -#define ESF_DZ_TXP_BKT_TBL_RD_REQ_BKT_ID_LBN 5 -#define ESF_DZ_TXP_BKT_TBL_RD_REQ_BKT_ID_WIDTH 10 -#define ESF_DZ_TXP_BKT_TBL_RD_REQ_OP_LBN 2 -#define ESF_DZ_TXP_BKT_TBL_RD_REQ_OP_WIDTH 3 -#define ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7 -#define ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6 -#define ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5 -#define ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4 -#define ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3 -#define ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2 -#define ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1 -#define ESE_DZ_DPCPU_PACER_BKT_D_RD 0 -#define ESF_DZ_TXP_BKT_TBL_RD_REQ_CLIENT_ID_LBN 0 -#define ESF_DZ_TXP_BKT_TBL_RD_REQ_CLIENT_ID_WIDTH 2 -#define ESE_DZ_DPCPU_PACER_CPU_CLIENT 2 -#define ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1 -#define ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0 - - -/* ES_TX_PACER_BKT_TBL_RD_RSP */ -#define ESF_DZ_TXP_BKT_TBL_RD_RSP_IDLE_LBN 97 -#define ESF_DZ_TXP_BKT_TBL_RD_RSP_IDLE_WIDTH 1 -#define ESF_DZ_TXP_BKT_TBL_RD_RSP_USED_LBN 96 -#define ESF_DZ_TXP_BKT_TBL_RD_RSP_USED_WIDTH 1 -#define ESF_DZ_TXP_BKT_TBL_RD_RSP_MAX_FILL_REG_LBN 94 -#define ESF_DZ_TXP_BKT_TBL_RD_RSP_MAX_FILL_REG_WIDTH 2 -#define ESF_DZ_TXP_BKT_TBL_RD_RSP_RATE_REC_LBN 78 -#define ESF_DZ_TXP_BKT_TBL_RD_RSP_RATE_REC_WIDTH 16 -#define ESF_DZ_TXP_BKT_TBL_RD_RSP_RATE_LBN 62 -#define ESF_DZ_TXP_BKT_TBL_RD_RSP_RATE_WIDTH 16 -#define ESF_DZ_TXP_BKT_TBL_RD_RSP_FILL_LEVEL_LBN 47 -#define ESF_DZ_TXP_BKT_TBL_RD_RSP_FILL_LEVEL_WIDTH 15 -#define ESF_DZ_TXP_BKT_TBL_RD_RSP_DUE_TIME_LBN 31 -#define ESF_DZ_TXP_BKT_TBL_RD_RSP_DUE_TIME_WIDTH 16 -#define ESF_DZ_TXP_BKT_TBL_RD_RSP_LAST_FILL_TIME_LBN 15 -#define ESF_DZ_TXP_BKT_TBL_RD_RSP_LAST_FILL_TIME_WIDTH 16 -#define ESF_DZ_TXP_BKT_TBL_RD_RSP_BKT_ID_LBN 5 -#define ESF_DZ_TXP_BKT_TBL_RD_RSP_BKT_ID_WIDTH 10 -#define ESF_DZ_TXP_BKT_TBL_RD_RSP_OP_LBN 2 -#define ESF_DZ_TXP_BKT_TBL_RD_RSP_OP_WIDTH 3 -#define ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7 -#define ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6 -#define ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5 -#define ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4 -#define ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3 -#define ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2 -#define ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1 -#define ESE_DZ_DPCPU_PACER_BKT_D_RD 0 -#define ESF_DZ_TXP_BKT_TBL_RD_RSP_CLIENT_ID_LBN 0 -#define ESF_DZ_TXP_BKT_TBL_RD_RSP_CLIENT_ID_WIDTH 2 -#define ESE_DZ_DPCPU_PACER_CPU_CLIENT 2 -#define ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1 -#define ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0 - - -/* ES_TX_PACER_BKT_TBL_WR_REQ */ -#define ESF_DZ_TXP_BKT_TBL_WR_REQ_IDLE_LBN 65 -#define ESF_DZ_TXP_BKT_TBL_WR_REQ_IDLE_WIDTH 1 -#define ESF_DZ_TXP_BKT_TBL_WR_REQ_USED_LBN 64 -#define ESF_DZ_TXP_BKT_TBL_WR_REQ_USED_WIDTH 1 -#define ESF_DZ_TXP_BKT_TBL_WR_REQ_MAX_FILL_REG_LBN 62 -#define ESF_DZ_TXP_BKT_TBL_WR_REQ_MAX_FILL_REG_WIDTH 2 -#define ESF_DZ_TXP_BKT_TBL_WR_REQ_RATE_REC_LBN 46 -#define ESF_DZ_TXP_BKT_TBL_WR_REQ_RATE_REC_WIDTH 16 -#define ESF_DZ_TXP_BKT_TBL_WR_REQ_RATE_LBN 30 -#define ESF_DZ_TXP_BKT_TBL_WR_REQ_RATE_WIDTH 16 -#define ESF_DZ_TXP_BKT_TBL_WR_REQ_FILL_LEVEL_LBN 15 -#define ESF_DZ_TXP_BKT_TBL_WR_REQ_FILL_LEVEL_WIDTH 15 -#define ESF_DZ_TXP_BKT_TBL_WR_REQ_BKT_ID_LBN 5 -#define ESF_DZ_TXP_BKT_TBL_WR_REQ_BKT_ID_WIDTH 10 -#define ESF_DZ_TXP_BKT_TBL_WR_REQ_OP_LBN 2 -#define ESF_DZ_TXP_BKT_TBL_WR_REQ_OP_WIDTH 3 -#define ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7 -#define ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6 -#define ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5 -#define ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4 -#define ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3 -#define ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2 -#define ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1 -#define ESE_DZ_DPCPU_PACER_BKT_D_RD 0 -#define ESF_DZ_TXP_BKT_TBL_WR_REQ_CLIENT_ID_LBN 0 -#define ESF_DZ_TXP_BKT_TBL_WR_REQ_CLIENT_ID_WIDTH 2 -#define ESE_DZ_DPCPU_PACER_CPU_CLIENT 2 -#define ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1 -#define ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0 - - -/* ES_TX_PACER_TXQ_D_R_I_REQ */ -#define ESF_DZ_TXP_TXQ_D_R_I_REQ_FRM_LEN_LBN 15 -#define ESF_DZ_TXP_TXQ_D_R_I_REQ_FRM_LEN_WIDTH 14 -#define ESF_DZ_TXP_TXQ_D_R_I_REQ_TXQ_ID_LBN 5 -#define ESF_DZ_TXP_TXQ_D_R_I_REQ_TXQ_ID_WIDTH 10 -#define ESF_DZ_TXP_TXQ_D_R_I_REQ_OP_LBN 2 -#define ESF_DZ_TXP_TXQ_D_R_I_REQ_OP_WIDTH 3 -#define ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7 -#define ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6 -#define ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5 -#define ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4 -#define ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3 -#define ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2 -#define ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1 -#define ESE_DZ_DPCPU_PACER_BKT_D_RD 0 -#define ESF_DZ_TXP_TXQ_D_R_I_REQ_CLIENT_ID_LBN 0 -#define ESF_DZ_TXP_TXQ_D_R_I_REQ_CLIENT_ID_WIDTH 2 -#define ESE_DZ_DPCPU_PACER_CPU_CLIENT 2 -#define ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1 -#define ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0 - - -/* ES_TX_PACER_TXQ_TBL_RD_REQ */ -#define ESF_DZ_TXP_TXQ_TBL_RD_REQ_TXQ_ID_LBN 5 -#define ESF_DZ_TXP_TXQ_TBL_RD_REQ_TXQ_ID_WIDTH 10 -#define ESF_DZ_TXP_TXQ_TBL_RD_REQ_OP_LBN 2 -#define ESF_DZ_TXP_TXQ_TBL_RD_REQ_OP_WIDTH 3 -#define ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7 -#define ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6 -#define ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5 -#define ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4 -#define ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3 -#define ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2 -#define ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1 -#define ESE_DZ_DPCPU_PACER_BKT_D_RD 0 -#define ESF_DZ_TXP_TXQ_TBL_RD_REQ_CLIENT_ID_LBN 0 -#define ESF_DZ_TXP_TXQ_TBL_RD_REQ_CLIENT_ID_WIDTH 2 -#define ESE_DZ_DPCPU_PACER_CPU_CLIENT 2 -#define ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1 -#define ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0 - - -/* ES_TX_PACER_TXQ_TBL_RD_RSP */ -#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_MAX_BKT2_LBN 53 -#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_MAX_BKT2_WIDTH 10 -#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_MAX_BKT1_LBN 43 -#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_MAX_BKT1_WIDTH 10 -#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_MAX_BKT0_LBN 33 -#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_MAX_BKT0_WIDTH 10 -#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_MIN_BKT_LBN 23 -#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_MIN_BKT_WIDTH 10 -#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_LABEL_LBN 19 -#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_LABEL_WIDTH 4 -#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_PQ_FLAGS_LBN 16 -#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_PQ_FLAGS_WIDTH 3 -#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_DSBL_LBN 15 -#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_DSBL_WIDTH 1 -#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_TXQ_ID_LBN 5 -#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_TXQ_ID_WIDTH 10 -#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_OP_LBN 2 -#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_OP_WIDTH 3 -#define ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7 -#define ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6 -#define ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5 -#define ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4 -#define ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3 -#define ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2 -#define ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1 -#define ESE_DZ_DPCPU_PACER_BKT_D_RD 0 -#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_CLIENT_ID_LBN 0 -#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_CLIENT_ID_WIDTH 2 -#define ESE_DZ_DPCPU_PACER_CPU_CLIENT 2 -#define ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1 -#define ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0 - - -/* ES_TX_PACER_TXQ_TBL_WR_REQ */ -#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_MAX_BKT2_LBN 53 -#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_MAX_BKT2_WIDTH 10 -#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_MAX_BKT1_LBN 43 -#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_MAX_BKT1_WIDTH 10 -#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_MAX_BKT0_LBN 33 -#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_MAX_BKT0_WIDTH 10 -#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_MIN_BKT_LBN 23 -#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_MIN_BKT_WIDTH 10 -#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_LABEL_LBN 19 -#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_LABEL_WIDTH 4 -#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_PQ_FLAGS_LBN 16 -#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_PQ_FLAGS_WIDTH 3 -#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_DSBL_LBN 15 -#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_DSBL_WIDTH 1 -#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_TXQ_ID_LBN 5 -#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_TXQ_ID_WIDTH 10 -#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_OP_LBN 2 -#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_OP_WIDTH 3 -#define ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7 -#define ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6 -#define ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5 -#define ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4 -#define ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3 -#define ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2 -#define ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1 -#define ESE_DZ_DPCPU_PACER_BKT_D_RD 0 -#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_CLIENT_ID_LBN 0 -#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_CLIENT_ID_WIDTH 2 -#define ESE_DZ_DPCPU_PACER_CPU_CLIENT 2 -#define ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1 -#define ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0 - - /* ES_TX_USER_DESC */ #define ESF_DZ_TX_USR_TYPE_LBN 63 #define ESF_DZ_TX_USR_TYPE_WIDTH 1 #define ESF_DZ_TX_USR_CONT_LBN 62 #define ESF_DZ_TX_USR_CONT_WIDTH 1 #define ESF_DZ_TX_USR_BYTE_CNT_LBN 48 #define ESF_DZ_TX_USR_BYTE_CNT_WIDTH 14 #define ESF_DZ_TX_USR_BUF_PAGE_SIZE_LBN 44 #define ESF_DZ_TX_USR_BUF_PAGE_SIZE_WIDTH 4 #define ESE_DZ_USR_BUF_PAGE_SZ_4MB 10 #define ESE_DZ_USR_BUF_PAGE_SZ_1MB 8 #define ESE_DZ_USR_BUF_PAGE_SZ_64KB 4 #define ESE_DZ_USR_BUF_PAGE_SZ_4KB 0 #define ESF_DZ_TX_USR_BUF_ID_OFFSET_DW0_LBN 0 #define ESF_DZ_TX_USR_BUF_ID_OFFSET_DW0_WIDTH 32 #define ESF_DZ_TX_USR_BUF_ID_OFFSET_DW1_LBN 32 #define ESF_DZ_TX_USR_BUF_ID_OFFSET_DW1_WIDTH 12 #define ESF_DZ_TX_USR_BUF_ID_OFFSET_LBN 0 #define ESF_DZ_TX_USR_BUF_ID_OFFSET_WIDTH 44 #define ESF_DZ_TX_USR_4KBPS_BUF_ID_LBN 12 #define ESF_DZ_TX_USR_4KBPS_BUF_ID_WIDTH 32 #define ESF_DZ_TX_USR_64KBPS_BUF_ID_LBN 16 #define ESF_DZ_TX_USR_64KBPS_BUF_ID_WIDTH 28 #define ESF_DZ_TX_USR_1MBPS_BUF_ID_LBN 20 #define ESF_DZ_TX_USR_1MBPS_BUF_ID_WIDTH 24 #define ESF_DZ_TX_USR_4MBPS_BUF_ID_LBN 22 #define ESF_DZ_TX_USR_4MBPS_BUF_ID_WIDTH 22 #define ESF_DZ_TX_USR_4MBPS_BYTE_OFFSET_LBN 0 #define ESF_DZ_TX_USR_4MBPS_BYTE_OFFSET_WIDTH 22 #define ESF_DZ_TX_USR_1MBPS_BYTE_OFFSET_LBN 0 #define ESF_DZ_TX_USR_1MBPS_BYTE_OFFSET_WIDTH 20 #define ESF_DZ_TX_USR_64KBPS_BYTE_OFFSET_LBN 0 #define ESF_DZ_TX_USR_64KBPS_BYTE_OFFSET_WIDTH 16 #define ESF_DZ_TX_USR_4KBPS_BYTE_OFFSET_LBN 0 #define ESF_DZ_TX_USR_4KBPS_BYTE_OFFSET_WIDTH 12 /* ES_TX_U_QSTATE_TBL0_ENTRY */ #define ESF_DZ_TX_U_DC_FILL_LBN 112 #define ESF_DZ_TX_U_DC_FILL_WIDTH 7 #define ESF_DZ_TX_U_SOFT7_B1R3_LBN 112 #define ESF_DZ_TX_U_SOFT7_B1R3_WIDTH 7 #define ESF_DZ_TX_U_DSCR_HW_RPTR_LBN 96 #define ESF_DZ_TX_U_DSCR_HW_RPTR_WIDTH 12 #define ESF_DZ_TX_U_SOFT12_B1R2_LBN 96 #define ESF_DZ_TX_U_SOFT12_B1R2_WIDTH 12 #define ESF_DZ_TX_U_DC_RPTR_LBN 80 #define ESF_DZ_TX_U_DC_RPTR_WIDTH 6 #define ESF_DZ_TX_U_SOFT6_B1R1_LBN 80 #define ESF_DZ_TX_U_SOFT6_B1R1_WIDTH 6 +#define ESF_DZ_TX_U_CNTAG_LBN 68 +#define ESF_DZ_TX_U_CNTAG_WIDTH 1 #define ESF_DZ_TX_U_SOFT5_B1R0_LBN 64 #define ESF_DZ_TX_U_SOFT5_B1R0_WIDTH 5 +#define ESF_DZ_TX_U_TIMESTAMP_LBN 67 +#define ESF_DZ_TX_U_TIMESTAMP_WIDTH 1 #define ESF_DZ_TX_U_PREFETCH_ACTIVE_LBN 66 #define ESF_DZ_TX_U_PREFETCH_ACTIVE_WIDTH 1 #define ESF_DZ_TX_U_PREFETCH_PENDING_LBN 65 #define ESF_DZ_TX_U_PREFETCH_PENDING_WIDTH 1 #define ESF_DZ_TX_U_DOORBELL_ENABLED_LBN 64 #define ESF_DZ_TX_U_DOORBELL_ENABLED_WIDTH 1 #define ESF_DZ_TX_U_UPD_UDPTCP_CSUM_MODE_LBN 33 #define ESF_DZ_TX_U_UPD_UDPTCP_CSUM_MODE_WIDTH 1 #define ESF_DZ_TX_U_SOFT2_B0R2_LBN 32 #define ESF_DZ_TX_U_SOFT2_B0R2_WIDTH 2 #define ESF_DZ_TX_U_UPD_IP_CSUM_MODE_LBN 32 #define ESF_DZ_TX_U_UPD_IP_CSUM_MODE_WIDTH 1 #define ESF_DZ_TX_U_UPD_CRC_MODE_LBN 29 #define ESF_DZ_TX_U_UPD_CRC_MODE_WIDTH 3 #define ESE_DZ_C2RIP_FCOIP_MPA 5 #define ESE_DZ_C2RIP_FCOIP_FCOE 4 #define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 #define ESE_DZ_C2RIP_ISCSI_HDR 2 #define ESE_DZ_C2RIP_FCOE 1 #define ESE_DZ_C2RIP_OFF 0 #define ESF_DZ_TX_U_SOFT16_B0R1_LBN 16 #define ESF_DZ_TX_U_SOFT16_B0R1_WIDTH 16 #define ESF_DZ_TX_U_BIU_ARGS_LBN 16 #define ESF_DZ_TX_U_BIU_ARGS_WIDTH 13 #define ESF_DZ_TX_U_EV_QID_LBN 5 #define ESF_DZ_TX_U_EV_QID_WIDTH 11 #define ESF_DZ_TX_U_SOFT16_B0R0_LBN 0 #define ESF_DZ_TX_U_SOFT16_B0R0_WIDTH 16 #define ESF_DZ_TX_U_EV_QLABEL_LBN 0 #define ESF_DZ_TX_U_EV_QLABEL_WIDTH 5 /* ES_TX_U_QSTATE_TBL1_ENTRY */ #define ESF_DZ_TX_U_DSCR_BASE_PAGE_ID_LBN 64 #define ESF_DZ_TX_U_DSCR_BASE_PAGE_ID_WIDTH 18 #define ESF_DZ_TX_U_SOFT18_B1R0_LBN 64 #define ESF_DZ_TX_U_SOFT18_B1R0_WIDTH 18 #define ESF_DZ_TX_U_SOFT16_B0R3_LBN 48 #define ESF_DZ_TX_U_SOFT16_B0R3_WIDTH 16 +#define ESF_DZ_TX_U_EMERGENCY_FETCH_FAILED_LBN 56 +#define ESF_DZ_TX_U_EMERGENCY_FETCH_FAILED_WIDTH 1 +#define ESF_DZ_TX_U_PACER_BYPASS_OK_LBN 55 +#define ESF_DZ_TX_U_PACER_BYPASS_OK_WIDTH 1 +#define ESF_DZ_TX_U_STALE_DL_FETCH_LBN 54 +#define ESF_DZ_TX_U_STALE_DL_FETCH_WIDTH 1 +#define ESF_DZ_TX_U_ROLLBACK_IDX_REACHED_LBN 52 +#define ESF_DZ_TX_U_ROLLBACK_IDX_REACHED_WIDTH 1 +#define ESF_DZ_TX_U_ROLLBACK_ACTIVE_LBN 51 +#define ESF_DZ_TX_U_ROLLBACK_ACTIVE_WIDTH 1 +#define ESF_DZ_TX_U_QUEUE_PAUSED_LBN 50 +#define ESF_DZ_TX_U_QUEUE_PAUSED_WIDTH 1 #define ESF_DZ_TX_U_QUEUE_ENABLED_LBN 49 #define ESF_DZ_TX_U_QUEUE_ENABLED_WIDTH 1 #define ESF_DZ_TX_U_FLUSH_PENDING_LBN 48 #define ESF_DZ_TX_U_FLUSH_PENDING_WIDTH 1 #define ESF_DZ_TX_U_DSCR_HW_WPTR_LBN 32 #define ESF_DZ_TX_U_DSCR_HW_WPTR_WIDTH 12 #define ESF_DZ_TX_U_SOFT12_B0R2_LBN 32 #define ESF_DZ_TX_U_SOFT12_B0R2_WIDTH 12 #define ESF_DZ_TX_U_OWNER_ID_LBN 16 #define ESF_DZ_TX_U_OWNER_ID_WIDTH 12 #define ESF_DZ_TX_U_SOFT12_B0R1_LBN 16 #define ESF_DZ_TX_U_SOFT12_B0R1_WIDTH 12 -#define ESF_DZ_TX_U_DSCR_SIZE_LBN 0 +#define ESF_DZ_TX_U_DSCR_SIZE_LBN 13 #define ESF_DZ_TX_U_DSCR_SIZE_WIDTH 3 #define ESF_DZ_TX_U_SOFT3_B0R0_LBN 0 #define ESF_DZ_TX_U_SOFT3_B0R0_WIDTH 3 /* ES_TX_U_QSTATE_TBL2_ENTRY */ #define ESF_DZ_TX_FINFO_WRD3_LBN 48 #define ESF_DZ_TX_FINFO_WRD3_WIDTH 16 #define ESF_DZ_TX_FINFO_WRD2_LBN 32 #define ESF_DZ_TX_FINFO_WRD2_WIDTH 16 #define ESF_DZ_TX_FINFO_WRD1_LBN 16 #define ESF_DZ_TX_FINFO_WRD1_WIDTH 16 #define ESF_DZ_TX_FINFO_SRCDST_LBN 0 #define ESF_DZ_TX_FINFO_SRCDST_WIDTH 16 +/* ES_TX_VLAN_DESC */ +#define ESF_DZ_TX_DESC_IS_OPT_LBN 63 +#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 +#define ESF_DZ_TX_OPTION_TYPE_LBN 60 +#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 +#define ESE_DZ_TX_OPTION_DESC_TSO 7 +#define ESE_DZ_TX_OPTION_DESC_VLAN 6 +#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 +#define ESF_DZ_TX_VLAN_OP_LBN 32 +#define ESF_DZ_TX_VLAN_OP_WIDTH 2 +#define ESF_DZ_TX_VLAN_TAG2_LBN 16 +#define ESF_DZ_TX_VLAN_TAG2_WIDTH 16 +#define ESF_DZ_TX_VLAN_TAG1_LBN 0 +#define ESF_DZ_TX_VLAN_TAG1_WIDTH 16 + + /* ES_b2t_cpl_rsp */ -#define ESF_DZ_B2T_CPL_RSP_CPL_ECC_LBN 268 +#define ESF_DZ_B2T_CPL_RSP_CPL_ECC_LBN 284 #define ESF_DZ_B2T_CPL_RSP_CPL_ECC_WIDTH 32 +#define ESF_DZ_B2T_CPL_RSP_CPL_EOT_LBN 283 +#define ESF_DZ_B2T_CPL_RSP_CPL_EOT_WIDTH 1 #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW0_LBN 27 #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW0_WIDTH 32 #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW1_LBN 59 #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW1_WIDTH 32 #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW2_LBN 91 #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW2_WIDTH 32 #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW3_LBN 123 #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW3_WIDTH 32 #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW4_LBN 155 #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW4_WIDTH 32 #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW5_LBN 187 #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW5_WIDTH 32 #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW6_LBN 219 #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW6_WIDTH 32 #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW7_LBN 251 #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW7_WIDTH 32 #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_LBN 27 #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_WIDTH 256 -#define ESF_DZ_B2T_CPL_RSP_CPL_EOT_LBN 283 -#define ESF_DZ_B2T_CPL_RSP_CPL_EOT_WIDTH -15 #define ESF_DZ_B2T_CPL_RSP_CPL_ERROR_LBN 26 #define ESF_DZ_B2T_CPL_RSP_CPL_ERROR_WIDTH 1 #define ESF_DZ_B2T_CPL_RSP_CPL_LAST_LBN 25 #define ESF_DZ_B2T_CPL_RSP_CPL_LAST_WIDTH 1 #define ESF_DZ_B2T_CPL_RSP_CPL_TAG_LBN 19 #define ESF_DZ_B2T_CPL_RSP_CPL_TAG_WIDTH 6 #define ESF_DZ_B2T_CPL_RSP_CPL_LEN_LBN 7 #define ESF_DZ_B2T_CPL_RSP_CPL_LEN_WIDTH 12 #define ESF_DZ_B2T_CPL_RSP_CPL_ADRS_LBN 0 #define ESF_DZ_B2T_CPL_RSP_CPL_ADRS_WIDTH 7 +/* ES_fltr_info_wrd_mac_to_rx */ +#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED2_LBN 112 +#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED2_WIDTH 16 +#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP2_LBN 96 +#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP2_WIDTH 16 +#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP1_LBN 80 +#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP1_WIDTH 16 +#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP0_LBN 64 +#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP0_WIDTH 16 +#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED1_LBN 48 +#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED1_WIDTH 16 +#define ESF_DZ_FLTR_INFO_MAC_TO_RX_IPSEC_SA_LBN 32 +#define ESF_DZ_FLTR_INFO_MAC_TO_RX_IPSEC_SA_WIDTH 16 +#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED0_LBN 8 +#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED0_WIDTH 24 +#define ESF_DZ_FLTR_INFO_MAC_TO_RX_IPSEC_LBN 7 +#define ESF_DZ_FLTR_INFO_MAC_TO_RX_IPSEC_WIDTH 1 +#define ESF_DZ_FLTR_INFO_MAC_TO_RX_PRIORITY_LBN 4 +#define ESF_DZ_FLTR_INFO_MAC_TO_RX_PRIORITY_WIDTH 3 +#define ESF_DZ_FLTR_INFO_MAC_TO_RX_SRC_LBN 0 +#define ESF_DZ_FLTR_INFO_MAC_TO_RX_SRC_WIDTH 4 -/* Enum DPCPU_INSTR_BRTYPE */ -#define ESE_DZ_BNEZAL 19 -#define ESE_DZ_BEQZAL 18 -#define ESE_DZ_BGEZAL 17 -#define ESE_DZ_BLTZAL 16 -#define ESE_DZ_BNEZ 3 -#define ESE_DZ_BEQZ 2 -#define ESE_DZ_BGEZ 1 -#define ESE_DZ_BLTZ 0 -/* Enum DPCPU_INSTR_FUNCT */ -#define ESE_DZ_MASKMOD 44 -#define ESE_DZ_SLTU 43 -#define ESE_DZ_SLT 42 -#define ESE_DZ_INCMOD 40 -#define ESE_DZ_NOR 39 -#define ESE_DZ_XOR 38 -#define ESE_DZ_OR 37 -#define ESE_DZ_AND 36 -#define ESE_DZ_SUBU 35 -#define ESE_DZ_SUB 34 -#define ESE_DZ_ADDU 33 -#define ESE_DZ_ADD 32 -#define ESE_DZ_MULT 25 -#define ESE_DZ_MFLO 18 -#define ESE_DZ_MFHI 16 -#define ESE_DZ_JALR 9 -#define ESE_DZ_JR 8 -#define ESE_DZ_SRAV 7 -#define ESE_DZ_SRLV 6 -#define ESE_DZ_SLLV 4 -#define ESE_DZ_SRA 3 -#define ESE_DZ_SRL 2 -#define ESE_DZ_SLL 0 +/* ES_fltr_info_wrd_mc_pdma */ +#define ESF_DZ_FLTR_INFO_MC_PDMA_FLTR_OUT_LBN 64 +#define ESF_DZ_FLTR_INFO_MC_PDMA_FLTR_OUT_WIDTH 16 +#define ESE_DZ_FLTR_MULTICAST_VLAN 512 +#define ESE_DZ_FLTR_MAC_VLAN 256 +#define ESE_DZ_FLTR_STRUCTURED7 128 +#define ESE_DZ_FLTR_STRUCTURED6 64 +#define ESE_DZ_FLTR_STRUCTURED5 32 +#define ESE_DZ_FLTR_STRUCTURED4 16 +#define ESE_DZ_FLTR_STRUCTURED3 8 +#define ESE_DZ_FLTR_STRUCTURED2 4 +#define ESE_DZ_FLTR_STRUCTURED1 2 +#define ESE_DZ_FLTR_STRUCTURED0 1 +#define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_DW0_LBN 16 +#define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_DW0_WIDTH 32 +#define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_DW1_LBN 48 +#define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_DW1_WIDTH 16 +#define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_LBN 16 +#define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_WIDTH 48 +#define ESF_DZ_FLTR_INFO_MC_PDMA_DST_LBN 8 +#define ESF_DZ_FLTR_INFO_MC_PDMA_DST_WIDTH 8 +#define ESE_DZ_DST_NCSI 64 +#define ESE_DZ_DST_PORT0 32 +#define ESE_DZ_DST_PORT1 16 +#define ESE_DZ_DST_PORT0_IPSEC 8 +#define ESE_DZ_DST_PORT1_IPSEC 4 +#define ESE_DZ_DST_PM 2 +#define ESE_DZ_DST_TIMESTAMP 1 +#define ESF_DZ_FLTR_INFO_MC_PDMA_PRIORITY_LBN 4 +#define ESF_DZ_FLTR_INFO_MC_PDMA_PRIORITY_WIDTH 4 +#define ESF_DZ_FLTR_INFO_MC_PDMA_SRC_LBN 0 +#define ESF_DZ_FLTR_INFO_MC_PDMA_SRC_WIDTH 4 -/* Enum DPCPU_INSTR_OP */ -#define ESE_DZ_LM_MSG 49 -#define ESE_DZ_MSG 48 -#define ESE_DZ_SHA 43 -#define ESE_DZ_SBA 42 -#define ESE_DZ_SH 41 -#define ESE_DZ_SB 40 -#define ESE_DZ_LHUA 39 -#define ESE_DZ_LBUA 38 -#define ESE_DZ_LHU 37 -#define ESE_DZ_LBU 36 -#define ESE_DZ_LHA 35 -#define ESE_DZ_LBA 34 -#define ESE_DZ_LH 33 -#define ESE_DZ_LB 32 -#define ESE_DZ_BGTU 31 -#define ESE_DZ_BLEU 30 -#define ESE_DZ_MODI 28 -#define ESE_DZ_NEGU 27 -#define ESE_DZ_NEG 26 -#define ESE_DZ_LI 25 -#define ESE_DZ_INCMODI 24 -#define ESE_DZ_BGT 23 -#define ESE_DZ_BLE 22 -#define ESE_DZ_BBS 21 -#define ESE_DZ_BBC 20 -#define ESE_DZ_JAL_EVT 19 -#define ESE_DZ_J_EVT 18 -#define ESE_DZ_HALT 16 -#define ESE_DZ_NORI 15 -#define ESE_DZ_XORI 14 -#define ESE_DZ_ORI 13 -#define ESE_DZ_ANDI 12 -#define ESE_DZ_SLTIU 11 -#define ESE_DZ_SLTI 10 -#define ESE_DZ_ADDIU 9 -#define ESE_DZ_ADDI 8 -#define ESE_DZ_BGTZ 7 -#define ESE_DZ_BLEZ 6 -#define ESE_DZ_BNE 5 -#define ESE_DZ_BEQ 4 -#define ESE_DZ_JAL 3 -#define ESE_DZ_J 2 -#define ESE_DZ_BRANCH 1 -#define ESE_DZ_REG2REG 0 -/* Enum DPCPU_MSG_DIR */ -#define ESE_DPCPU_MSG_DZ_OUTB 0x1 -#define ESE_DPCPU_MSG_DZ_INB 0x0 +/* ES_fltr_info_wrd_rxdi_to_rxdp */ +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_INNER_VLAN_LBN 112 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_INNER_VLAN_WIDTH 16 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_OUTER_VLAN_LBN 96 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_OUTER_VLAN_WIDTH 16 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_THASH1_LBN 80 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_THASH1_WIDTH 16 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_THASH0_LBN 64 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_THASH0_WIDTH 16 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_TIMESTAMP1_LBN 48 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_TIMESTAMP1_WIDTH 16 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_TIMESTAMP0_LBN 32 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_TIMESTAMP0_WIDTH 16 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_CNP_LBN 31 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_CNP_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_IVP_LBN 30 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_IVP_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_OVP_LBN 29 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_OVP_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST2_LBN 28 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST2_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST1_LBN 27 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST1_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST0_LBN 26 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST0_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RX_QID_LBN 16 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RX_QID_WIDTH 10 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_HOST_LBN 15 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_HOST_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_MC_LBN 14 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_MC_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_P0_LBN 13 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_P0_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_P1_LBN 12 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_P1_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RESERVED1_LBN 11 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RESERVED1_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_CRF_LBN 10 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_CRF_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RESERVED0_LBN 9 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RESERVED0_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_REPLAY_LBN 8 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_REPLAY_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_IPSEC_LBN 7 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_IPSEC_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_PRIORITY_LBN 4 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_PRIORITY_WIDTH 3 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_SRC_LBN 0 +#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_SRC_WIDTH 4 -/* Enum DPCPU_PDBUS_OP */ -#define ESE_DPCPU_PDBUS_DZ_RD 0x1 -#define ESE_DPCPU_PDBUS_DZ_WR 0x0 +/* ES_fltr_info_wrd_rxdp_to_host */ +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED3_LBN 33 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED3_WIDTH 31 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RMON_SOFT_LBN 32 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RMON_SOFT_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED2_LBN 27 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED2_WIDTH 5 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RX_QID_LBN 16 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RX_QID_WIDTH 11 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_HOST_LBN 15 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_HOST_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_MC_LBN 14 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_MC_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_P0_LBN 13 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_P0_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_P1_LBN 12 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_P1_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED1_LBN 11 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED1_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_CRF_LBN 10 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_CRF_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED0_LBN 9 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED0_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_REPLAY_LBN 8 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_REPLAY_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_IPSEC_LBN 7 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_IPSEC_WIDTH 1 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_PRIORITY_LBN 4 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_PRIORITY_WIDTH 3 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_SRC_LBN 0 +#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_SRC_WIDTH 4 + + +/* ES_fltr_info_wrd_tx_to_mac */ +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_PRV_LBN 63 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_PRV_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_LB_LBN 62 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_LB_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_MS0_LBN 61 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_MS0_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_MS1_LBN 60 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_MS1_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_NDI_LBN 59 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_NDI_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED2_LBN 48 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED2_WIDTH 11 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_IPSEC_SA_LBN 32 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_IPSEC_SA_WIDTH 16 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_TX_STACK_ID_LBN 24 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_TX_STACK_ID_WIDTH 8 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_TX_DOMAIN_LBN 16 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_TX_DOMAIN_WIDTH 8 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED1_LBN 14 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED1_WIDTH 2 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_P0_LBN 13 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_P0_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_P1_LBN 12 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_P1_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_IP0_LBN 11 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_IP0_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_IP1_LBN 10 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_IP1_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_PM_LBN 9 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_PM_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED0_LBN 8 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED0_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_IPSEC_LBN 7 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_IPSEC_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_PRIORITY_LBN 4 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_PRIORITY_WIDTH 3 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_SRC_LBN 0 +#define ESF_DZ_FLTR_INFO_TX_TO_MAC_SRC_WIDTH 4 + + +/* ES_fltr_info_wrd_txdi_to_txdp */ +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_INNER_VLAN_LBN 112 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_INNER_VLAN_WIDTH 16 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_OUTER_VLAN_LBN 96 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_OUTER_VLAN_WIDTH 16 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_CNP_LBN 95 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_CNP_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IVP_LBN 94 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IVP_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_OVP_LBN 93 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_OVP_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED4_LBN 90 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED4_WIDTH 3 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_QID_LBN 80 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_QID_WIDTH 10 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_VRI_LBN 79 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_VRI_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED3_LBN 78 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED3_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MTU_DIV4_LBN 66 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MTU_DIV4_WIDTH 12 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_VRI_OP_LBN 64 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_VRI_OP_WIDTH 2 +#define ESE_DZ_VRI_OP_INSERT_REPLACE 3 +#define ESE_DZ_VRI_OP_INSERT_INSERT 2 +#define ESE_DZ_VRI_OP_REPLACE 1 +#define ESE_DZ_VRI_OP_INSERT 0 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_PRV_LBN 63 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_PRV_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_LB_LBN 62 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_LB_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MS0_LBN 61 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MS0_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MS1_LBN 60 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MS1_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_NDI_LBN 59 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_NDI_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TXDP_CONTEXT_OUT_LBN 48 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TXDP_CONTEXT_OUT_WIDTH 11 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IPSEC_SA_LBN 32 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IPSEC_SA_WIDTH 16 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TX_STACK_ID_LBN 24 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TX_STACK_ID_WIDTH 8 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TX_DOMAIN_LBN 16 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TX_DOMAIN_WIDTH 8 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED1_LBN 14 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED1_WIDTH 2 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_P0_LBN 13 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_P0_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_P1_LBN 12 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_P1_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_IP0_LBN 11 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_IP0_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_IP1_LBN 10 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_IP1_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_PM_LBN 9 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_PM_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED0_LBN 8 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED0_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IPSEC_LBN 7 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IPSEC_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_PRIORITY_LBN 4 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_PRIORITY_WIDTH 3 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_SRC_LBN 0 +#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_SRC_WIDTH 4 + + +/* ES_fltr_info_wrd_txdp_to_txdi */ +#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_VLAN_OP_LBN 62 +#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_VLAN_OP_WIDTH 2 +#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_RESERVED1_LBN 58 +#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_RESERVED1_WIDTH 4 +#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_TX_QID_LBN 48 +#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_TX_QID_WIDTH 10 +#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_INNER_VLAN_LBN 32 +#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_INNER_VLAN_WIDTH 16 +#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_OUTER_VLAN_LBN 16 +#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_OUTER_VLAN_WIDTH 16 +#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_TXDP_CONTEXT_IN_LBN 5 +#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_TXDP_CONTEXT_IN_WIDTH 11 +#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_RESERVED0_LBN 4 +#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_RESERVED0_WIDTH 1 +#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_SRC_LBN 0 +#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_SRC_WIDTH 4 + + +/* ES_nwk_ev_merge_blk_cmd */ +#define ESF_DZ_EV_MERGE_BLK_COMMAND_OP_LBN 28 +#define ESF_DZ_EV_MERGE_BLK_COMMAND_OP_WIDTH 4 +#define ESE_DZ_EV_MERGE_BLK_COMMAND_OP_FLUSH 2 +#define ESE_DZ_EV_MERGE_BLK_COMMAND_OP_ENABLE 1 +#define ESE_DZ_EV_MERGE_BLK_COMMAND_OP_DISABLE 0 +#define ESF_DZ_EV_MERGE_BLK_COMMAND_BUSY_LBN 31 +#define ESF_DZ_EV_MERGE_BLK_COMMAND_BUSY_WIDTH 1 +#define ESF_DZ_EV_MERGE_BLK_COMMAND_EVQ_IDX_LBN 0 +#define ESF_DZ_EV_MERGE_BLK_COMMAND_EVQ_IDX_WIDTH 11 + + +/* ES_txpm2ini_cpl_rsp */ +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ECC_LBN 284 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ECC_WIDTH 32 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_EOT_LBN 283 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_EOT_WIDTH 1 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW0_LBN 27 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW0_WIDTH 32 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW1_LBN 59 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW1_WIDTH 32 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW2_LBN 91 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW2_WIDTH 32 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW3_LBN 123 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW3_WIDTH 32 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW4_LBN 155 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW4_WIDTH 32 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW5_LBN 187 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW5_WIDTH 32 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW6_LBN 219 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW6_WIDTH 32 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW7_LBN 251 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW7_WIDTH 32 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_LBN 27 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_WIDTH 256 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ERROR_LBN 26 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ERROR_WIDTH 1 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_LAST_LBN 25 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_LAST_WIDTH 1 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_TAG_LBN 19 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_TAG_WIDTH 6 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_LEN_LBN 7 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_LEN_WIDTH 12 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ADRS_LBN 0 +#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ADRS_WIDTH 7 + + + /* Enum INI_OP */ #define ESE_DZ_RD_COMPL 0x3 #define ESE_DZ_NOP 0x2 #define ESE_DZ_WR 0x1 #define ESE_DZ_RD 0x0 /* Enum INT_OP */ #define ESE_DZ_LEGACY 0x2 #define ESE_DZ_MSI 0x1 #define ESE_DZ_MSIX 0x0 + +/* Enum MC_PDMA_BUFFER_ID */ +#define ESE_DZ_MC_PDMA_BUFFER_ALL 4 +#define ESE_DZ_MC_PDMA_BUFFER_RXDP 3 +#define ESE_DZ_MC_PDMA_BUFFER_NCSI 2 +#define ESE_DZ_MC_PDMA_BUFFER_NWPORT1 1 +#define ESE_DZ_MC_PDMA_BUFFER_NWPORT0 0 + +/* Enum MC_PDMA_INTERFACE_ID */ +#define ESE_DZ_MC_PDMA_INTERFACE_RXDP 3 +#define ESE_DZ_MC_PDMA_INTERFACE_NCSI 2 +#define ESE_DZ_MC_PDMA_INTERFACE_NWPORT1 1 +#define ESE_DZ_MC_PDMA_INTERFACE_NWPORT0 0 /* Enum PKT_STRM_CTL */ #define ESE_DZ_EOP_TRUNC 0x3 #define ESE_DZ_EOP_CRC_ERR 0x2 #define ESE_DZ_EOP 0x1 #define ESE_DZ_NOOP 0x0 /* Enum PM_EPI_PKT_MARKER */ #define ESE_DZ_PM_EPI_LST 0x3 #define ESE_DZ_PM_EPI_OBL 0x2 #define ESE_DZ_PM_EPI_TBL 0x1 #define ESE_DZ_PM_EPI_MDL 0x0 /* Enum PM_IPI_TO_PM_MM_COMMAND */ #define ESE_DZ_FREE_CHAIN 0x3 #define ESE_DZ_FREE_BUFFER 0x2 #define ESE_DZ_ADD_BUFFER 0x1 #define ESE_DZ_PM_MM_NOOP 0x0 /* Enum PM_MA_TO_PM_EPI_COMMAND */ #define ESE_DZ_FROM_PORT_D 0x4 #define ESE_DZ_FROM_PORT_C 0x3 #define ESE_DZ_FROM_PORT_B 0x2 #define ESE_DZ_FROM_PORT_A 0x1 #define ESE_DZ_PM_EPI_NOOP 0x0 /* Enum PM_MA_TO_PM_IPI_COMMAND */ #define ESE_DZ_TO_PORT_D 0x4 #define ESE_DZ_TO_PORT_C 0x3 #define ESE_DZ_TO_PORT_B 0x2 #define ESE_DZ_TO_PORT_A 0x1 #define ESE_DZ_PM_IPI_NOOP 0x0 #ifdef __cplusplus } #endif #endif /* _SYS_EFX_EF10_REGS_H */ Property changes on: head/sys/dev/sfxge/common/efx_regs_ef10.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_regs_mcdi.h =================================================================== --- head/sys/dev/sfxge/common/efx_regs_mcdi.h (revision 283513) +++ head/sys/dev/sfxge/common/efx_regs_mcdi.h (revision 283514) @@ -1,5095 +1,12519 @@ /*- - * Copyright 2008-2011 Solarflare Communications Inc. All rights reserved. + * Copyright 2008-2013 Solarflare Communications Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _SIENA_MC_DRIVER_PCOL_H #define _SIENA_MC_DRIVER_PCOL_H /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ /* Power-on reset state */ #define MC_FW_STATE_POR (1) /* If this is set in MC_RESET_STATE_REG then it should be * possible to jump into IMEM without loading code from flash. */ #define MC_FW_WARM_BOOT_OK (2) /* The MC main image has started to boot. */ #define MC_FW_STATE_BOOTING (4) /* The Scheduler has started. */ #define MC_FW_STATE_SCHED (8) +/* If this is set in MC_RESET_STATE_REG then it should be + * possible to jump into IMEM without loading code from flash. + * Unlike a warm boot, assume DMEM has been reloaded, so that + * the MC persistent data must be reinitialised. */ +#define MC_FW_TEPID_BOOT_OK (16) +/* We have entered the main firmware via recovery mode. This + * means that MC persistent data must be reinitialised, but that + * we shouldn't touch PCIe config. */ +#define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32) +/* BIST state has been initialized */ +#define MC_FW_BIST_INIT_OK (128) /* Siena MC shared memmory offsets */ /* The 'doorbell' addresses are hard-wired to alert the MC when written */ #define MC_SMEM_P0_DOORBELL_OFST 0x000 #define MC_SMEM_P1_DOORBELL_OFST 0x004 /* The rest of these are firmware-defined */ #define MC_SMEM_P0_PDU_OFST 0x008 #define MC_SMEM_P1_PDU_OFST 0x108 #define MC_SMEM_PDU_LEN 0x100 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 #define MC_SMEM_P0_STATUS_OFST 0x7f8 #define MC_SMEM_P1_STATUS_OFST 0x7fc /* Values to be written to the per-port status dword in shared * memory on reboot and assert */ #define MC_STATUS_DWORD_REBOOT (0xb007b007) #define MC_STATUS_DWORD_ASSERT (0xdeaddead) +/* Check whether an mcfw version (in host order) belongs to a bootloader */ +#define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007) + /* The current version of the MCDI protocol. * * Note that the ROM burnt into the card only talks V0, so at the very * least every driver must support version 0 and MCDI_PCOL_VERSION */ #ifdef WITH_MCDI_V2 #define MCDI_PCOL_VERSION 2 #else #define MCDI_PCOL_VERSION 1 #endif /* Unused commands: 0x23, 0x27, 0x30, 0x31 */ /* MCDI version 1 * - * Each MCDI request starts with an MCDI_HEADER, which is a 32byte + * Each MCDI request starts with an MCDI_HEADER, which is a 32bit * structure, filled in by the client. * * 0 7 8 16 20 22 23 24 31 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | * | | | * | | \--- Response * | \------- Error * \------------------------------ Resync (always set) * * The client writes it's request into MC shared memory, and rings the * doorbell. Each request is completed by either by the MC writting * back into shared memory, or by writting out an event. * * All MCDI commands support completion by shared memory response. Each * request may also contain additional data (accounted for by HEADER.LEN), * and some response's may also contain additional data (again, accounted * for by HEADER.LEN). * * Some MCDI commands support completion by event, in which any associated * response data is included in the event. * * The protocol requires one response to be delivered for every request, a * request should not be sent unless the response for the previous request * has been received (either by polling shared memory, or by receiving * an event). */ /** Request/Response structure */ #define MCDI_HEADER_OFST 0 #define MCDI_HEADER_CODE_LBN 0 #define MCDI_HEADER_CODE_WIDTH 7 #define MCDI_HEADER_RESYNC_LBN 7 #define MCDI_HEADER_RESYNC_WIDTH 1 #define MCDI_HEADER_DATALEN_LBN 8 #define MCDI_HEADER_DATALEN_WIDTH 8 #define MCDI_HEADER_SEQ_LBN 16 -#define MCDI_HEADER_RSVD_LBN 20 -#define MCDI_HEADER_RSVD_WIDTH 2 #define MCDI_HEADER_SEQ_WIDTH 4 +#define MCDI_HEADER_RSVD_LBN 20 +#define MCDI_HEADER_RSVD_WIDTH 1 +#define MCDI_HEADER_NOT_EPOCH_LBN 21 +#define MCDI_HEADER_NOT_EPOCH_WIDTH 1 #define MCDI_HEADER_ERROR_LBN 22 #define MCDI_HEADER_ERROR_WIDTH 1 #define MCDI_HEADER_RESPONSE_LBN 23 #define MCDI_HEADER_RESPONSE_WIDTH 1 #define MCDI_HEADER_XFLAGS_LBN 24 #define MCDI_HEADER_XFLAGS_WIDTH 8 /* Request response using event */ #define MCDI_HEADER_XFLAGS_EVREQ 0x01 /* Maximum number of payload bytes */ +#define MCDI_CTL_SDU_LEN_MAX_V1 0xfc +#define MCDI_CTL_SDU_LEN_MAX_V2 0x400 + #ifdef WITH_MCDI_V2 -#define MCDI_CTL_SDU_LEN_MAX 0x400 +#define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2 #else -#define MCDI_CTL_SDU_LEN_MAX 0xfc +#define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V1 #endif + /* The MC can generate events for two reasons: * - To complete a shared memory request if XFLAGS_EVREQ was set * - As a notification (link state, i2c event), controlled * via MC_CMD_LOG_CTRL * * Both events share a common structure: * * 0 32 33 36 44 52 60 * | Data | Cont | Level | Src | Code | Rsvd | * | * \ There is another event pending in this notification * * If Code==CMDDONE, then the fields are further interpreted as: * * - LEVEL==INFO Command succeeded * - LEVEL==ERR Command failed * * 0 8 16 24 32 * | Seq | Datalen | Errno | Rsvd | * * These fields are taken directly out of the standard MCDI header, i.e., * LEVEL==ERR, Datalen == 0 => Reboot * * Events can be squirted out of the UART (using LOG_CTRL) without a * MCDI header. An event can be distinguished from a MCDI response by * examining the first byte which is 0xc0. This corresponds to the * non-existent MCDI command MC_CMD_DEBUG_LOG. * * 0 7 8 * | command | Resync | = 0xc0 * * Since the event is written in big-endian byte order, this works * providing bits 56-63 of the event are 0xc0. * * 56 60 63 * | Rsvd | Code | = 0xc0 * * Which means for convenience the event code is 0xc for all MC * generated events. */ #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc +/* Operation not permitted. */ +#define MC_CMD_ERR_EPERM 1 /* Non-existent command target */ #define MC_CMD_ERR_ENOENT 2 /* assert() has killed the MC */ #define MC_CMD_ERR_EINTR 4 +/* I/O failure */ +#define MC_CMD_ERR_EIO 5 +/* Already exists */ +#define MC_CMD_ERR_EEXIST 6 +/* Try again */ +#define MC_CMD_ERR_EAGAIN 11 +/* Out of memory */ +#define MC_CMD_ERR_ENOMEM 12 /* Caller does not hold required locks */ #define MC_CMD_ERR_EACCES 13 /* Resource is currently unavailable (e.g. lock contention) */ #define MC_CMD_ERR_EBUSY 16 +/* No such device */ +#define MC_CMD_ERR_ENODEV 19 /* Invalid argument to target */ #define MC_CMD_ERR_EINVAL 22 +/* Broken pipe */ +#define MC_CMD_ERR_EPIPE 32 +/* Read-only */ +#define MC_CMD_ERR_EROFS 30 +/* Out of range */ +#define MC_CMD_ERR_ERANGE 34 /* Non-recursive resource is already acquired */ #define MC_CMD_ERR_EDEADLK 35 /* Operation not implemented */ #define MC_CMD_ERR_ENOSYS 38 /* Operation timed out */ #define MC_CMD_ERR_ETIME 62 +/* Link has been severed */ +#define MC_CMD_ERR_ENOLINK 67 +/* Protocol error */ +#define MC_CMD_ERR_EPROTO 71 +/* Operation not supported */ +#define MC_CMD_ERR_ENOTSUP 95 +/* Address not available */ +#define MC_CMD_ERR_EADDRNOTAVAIL 99 +/* Not connected */ +#define MC_CMD_ERR_ENOTCONN 107 +/* Operation already in progress */ +#define MC_CMD_ERR_EALREADY 114 +/* Resource allocation failed. */ +#define MC_CMD_ERR_ALLOC_FAIL 0x1000 +/* V-adaptor not found. */ +#define MC_CMD_ERR_NO_VADAPTOR 0x1001 +/* EVB port not found. */ +#define MC_CMD_ERR_NO_EVB_PORT 0x1002 +/* V-switch not found. */ +#define MC_CMD_ERR_NO_VSWITCH 0x1003 +/* Too many VLAN tags. */ +#define MC_CMD_ERR_VLAN_LIMIT 0x1004 +/* Bad PCI function number. */ +#define MC_CMD_ERR_BAD_PCI_FUNC 0x1005 +/* Invalid VLAN mode. */ +#define MC_CMD_ERR_BAD_VLAN_MODE 0x1006 +/* Invalid v-switch type. */ +#define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007 +/* Invalid v-port type. */ +#define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008 +/* MAC address exists. */ +#define MC_CMD_ERR_MAC_EXIST 0x1009 +/* Slave core not present */ +#define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a +/* The datapath is disabled. */ +#define MC_CMD_ERR_DATAPATH_DISABLED 0x100b +/* The requesting client is not a function */ +#define MC_CMD_ERR_CLIENT_NOT_FN 0x100c +/* The requested operation might require the + command to be passed between MCs, and the + transport doesn't support that. Should + only ever been seen over the UART. */ +#define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d +/* VLAN tag(s) exists */ +#define MC_CMD_ERR_VLAN_EXIST 0x100e +/* No MAC address assigned to an EVB port */ +#define MC_CMD_ERR_NO_MAC_ADDR 0x100f +/* Notifies the driver that the request has been relayed + * to an admin function for authorization. The driver should + * wait for a PROXY_RESPONSE event and then resend its request. + * This error code is followed by a 32-bit handle that + * helps matching it with the respective PROXY_RESPONSE event. */ +#define MC_CMD_ERR_PROXY_PENDING 0x1010 +#define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4 +/* The request cannot be passed for authorization because + * another request from the same function is currently being + * authorized. The drvier should try again later. */ +#define MC_CMD_ERR_PROXY_INPROGRESS 0x1011 +/* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function + * that has enabled proxying or BLOCK_INDEX points to a function that + * doesn't await an authorization. */ +#define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012 +/* This code is currently only used internally in FW. Its meaning is that + * an operation failed due to lack of SR-IOV privilege. + * Normally it is translated to EPERM by send_cmd_err(), + * but it may also be used to trigger some special mechanism + * for handling such case, e.g. to relay the failed request + * to a designated admin function for authorization. */ +#define MC_CMD_ERR_NO_PRIVILEGE 0x1013 +/* Workaround 26807 could not be turned on/off because some functions + * have already installed filters. See the comment at + * MC_CMD_WORKAROUND_BUG26807. */ +#define MC_CMD_ERR_FILTERS_PRESENT 0x1014 + #define MC_CMD_ERR_CODE_OFST 0 /* We define 8 "escape" commands to allow for command number space extension */ #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F /* Vectors in the boot ROM */ /* Point to the copycode entry point. */ -#define MC_BOOTROM_COPYCODE_VEC (0x7f4) +#define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) +#define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) /* Points to the recovery mode entry point. */ -#define MC_BOOTROM_NOFLASH_VEC (0x7f8) +#define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) +#define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) /* The command set exported by the boot ROM (MCDI v0) */ #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ (1 << MC_CMD_READ32) | \ (1 << MC_CMD_WRITE32) | \ (1 << MC_CMD_COPYCODE) | \ (1 << MC_CMD_GET_VERSION), \ 0, 0, 0 } -#define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ +#define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ (MC_CMD_SENSOR_ENTRY_OFST + (_x)) -#define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) ( \ - (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST+ \ - MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST)+ \ - ((n)*MC_CMD_DBIWROP_TYPEDEF_LEN)) +#define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ + (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ + MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \ + (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) -#define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) ( \ - (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST+ \ - MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST)+ \ - ((n)*MC_CMD_DBIWROP_TYPEDEF_LEN)) +#define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ + (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ + MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \ + (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) -#define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) ( \ - (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST+ \ - MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST)+ \ - ((n)*MC_CMD_DBIWROP_TYPEDEF_LEN)) +#define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ + (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ + MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \ + (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) +/* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default + * stack ID (which must be in the range 1-255) along with an EVB port ID. + */ +#define EVB_STACK_ID(n) (((n) & 0xff) << 16) + #ifdef WITH_MCDI_V2 /* Version 2 adds an optional argument to error returns: the errno value * may be followed by the (0-based) number of the first argument that * could not be processed. */ #define MC_CMD_ERR_ARG_OFST 4 -/* Try again */ -#define MC_CMD_ERR_EAGAIN 11 /* No space */ #define MC_CMD_ERR_ENOSPC 28 #endif /* MCDI_EVENT structuredef */ #define MCDI_EVENT_LEN 8 #define MCDI_EVENT_CONT_LBN 32 #define MCDI_EVENT_CONT_WIDTH 1 #define MCDI_EVENT_LEVEL_LBN 33 #define MCDI_EVENT_LEVEL_WIDTH 3 -#define MCDI_EVENT_LEVEL_INFO 0x0 /* enum */ -#define MCDI_EVENT_LEVEL_WARN 0x1 /* enum */ -#define MCDI_EVENT_LEVEL_ERR 0x2 /* enum */ -#define MCDI_EVENT_LEVEL_FATAL 0x3 /* enum */ +/* enum: Info. */ +#define MCDI_EVENT_LEVEL_INFO 0x0 +/* enum: Warning. */ +#define MCDI_EVENT_LEVEL_WARN 0x1 +/* enum: Error. */ +#define MCDI_EVENT_LEVEL_ERR 0x2 +/* enum: Fatal. */ +#define MCDI_EVENT_LEVEL_FATAL 0x3 #define MCDI_EVENT_DATA_OFST 0 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 -#define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 /* enum */ -#define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 /* enum */ -#define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 /* enum */ +/* enum: 100Mbs */ +#define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 +/* enum: 1Gbs */ +#define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 +/* enum: 10Gbs */ +#define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 +/* enum: 40Gbs */ +#define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 #define MCDI_EVENT_FWALERT_DATA_LBN 8 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24 #define MCDI_EVENT_FWALERT_REASON_LBN 0 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8 -#define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 /* enum */ +/* enum: SRAM Access. */ +#define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 #define MCDI_EVENT_FLR_VF_LBN 0 #define MCDI_EVENT_FLR_VF_WIDTH 8 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 -#define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 /* enum */ -#define MCDI_EVENT_TX_ERR_NO_EOP 0x2 /* enum */ -#define MCDI_EVENT_TX_ERR_2BIG 0x3 /* enum */ +/* enum: Descriptor loader reported failure */ +#define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 +/* enum: Descriptor ring empty and no EOP seen for packet */ +#define MCDI_EVENT_TX_ERR_NO_EOP 0x2 +/* enum: Overlength packet */ +#define MCDI_EVENT_TX_ERR_2BIG 0x3 +/* enum: Malformed option descriptor */ +#define MCDI_EVENT_TX_BAD_OPTDESC 0x5 +/* enum: Option descriptor part way through a packet */ +#define MCDI_EVENT_TX_OPT_IN_PKT 0x8 +/* enum: DMA or PIO data access error */ +#define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9 #define MCDI_EVENT_TX_ERR_INFO_LBN 16 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 +#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12 +#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 -#define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 /* enum */ -#define MCDI_EVENT_PTP_ERR_FILTER 0x2 /* enum */ -#define MCDI_EVENT_PTP_ERR_FIFO 0x3 /* enum */ -#define MCDI_EVENT_PTP_ERR_QUEUE 0x4 /* enum */ +/* enum: PLL lost lock */ +#define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 +/* enum: Filter overflow (PDMA) */ +#define MCDI_EVENT_PTP_ERR_FILTER 0x2 +/* enum: FIFO overflow (FPGA) */ +#define MCDI_EVENT_PTP_ERR_FIFO 0x3 +/* enum: Merge queue overflow */ +#define MCDI_EVENT_PTP_ERR_QUEUE 0x4 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0 #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8 -#define MCDI_EVENT_AOE_NO_LOAD 0x1 /* enum */ -#define MCDI_EVENT_AOE_FC_ASSERT 0x2 /* enum */ -#define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 /* enum */ -#define MCDI_EVENT_AOE_FC_NO_START 0x4 /* enum */ -#define MCDI_EVENT_AOE_FAULT 0x5 /* enum */ -#define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 /* enum */ -#define MCDI_EVENT_AOE_LOAD 0x7 /* enum */ -#define MCDI_EVENT_AOE_DMA 0x8 /* enum */ -#define MCDI_EVENT_AOE_BYTEBLASTER 0x9 /* enum */ -#define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa /* enum */ -#define MCDI_EVENT_AOE_PTP_STATUS 0xb /* enum */ +/* enum: AOE failed to load - no valid image? */ +#define MCDI_EVENT_AOE_NO_LOAD 0x1 +/* enum: AOE FC reported an exception */ +#define MCDI_EVENT_AOE_FC_ASSERT 0x2 +/* enum: AOE FC watchdogged */ +#define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 +/* enum: AOE FC failed to start */ +#define MCDI_EVENT_AOE_FC_NO_START 0x4 +/* enum: Generic AOE fault - likely to have been reported via other means too + * but intended for use by aoex driver. + */ +#define MCDI_EVENT_AOE_FAULT 0x5 +/* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */ +#define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 +/* enum: AOE loaded successfully */ +#define MCDI_EVENT_AOE_LOAD 0x7 +/* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */ +#define MCDI_EVENT_AOE_DMA 0x8 +/* enum: AOE byteblaster connected/disconnected (Connection status in + * AOE_ERR_DATA) + */ +#define MCDI_EVENT_AOE_BYTEBLASTER 0x9 +/* enum: DDR ECC status update */ +#define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa +/* enum: PTP status update */ +#define MCDI_EVENT_AOE_PTP_STATUS 0xb #define MCDI_EVENT_AOE_ERR_DATA_LBN 8 #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8 +#define MCDI_EVENT_RX_ERR_RXQ_LBN 0 +#define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12 +#define MCDI_EVENT_RX_ERR_TYPE_LBN 12 +#define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4 +#define MCDI_EVENT_RX_ERR_INFO_LBN 16 +#define MCDI_EVENT_RX_ERR_INFO_WIDTH 16 +#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12 +#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1 +#define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0 +#define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12 +#define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0 +#define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16 +#define MCDI_EVENT_MUM_ERR_TYPE_LBN 0 +#define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8 +/* enum: MUM failed to load - no valid image? */ +#define MCDI_EVENT_MUM_NO_LOAD 0x1 +/* enum: MUM f/w reported an exception */ +#define MCDI_EVENT_MUM_ASSERT 0x2 +/* enum: MUM not kicking watchdog */ +#define MCDI_EVENT_MUM_WATCHDOG 0x3 +#define MCDI_EVENT_MUM_ERR_DATA_LBN 8 +#define MCDI_EVENT_MUM_ERR_DATA_WIDTH 8 #define MCDI_EVENT_DATA_LBN 0 #define MCDI_EVENT_DATA_WIDTH 32 #define MCDI_EVENT_SRC_LBN 36 #define MCDI_EVENT_SRC_WIDTH 8 #define MCDI_EVENT_EV_CODE_LBN 60 #define MCDI_EVENT_EV_CODE_WIDTH 4 #define MCDI_EVENT_CODE_LBN 44 #define MCDI_EVENT_CODE_WIDTH 8 -#define MCDI_EVENT_CODE_BADSSERT 0x1 /* enum */ -#define MCDI_EVENT_CODE_PMNOTICE 0x2 /* enum */ -#define MCDI_EVENT_CODE_CMDDONE 0x3 /* enum */ -#define MCDI_EVENT_CODE_LINKCHANGE 0x4 /* enum */ -#define MCDI_EVENT_CODE_SENSOREVT 0x5 /* enum */ -#define MCDI_EVENT_CODE_SCHEDERR 0x6 /* enum */ -#define MCDI_EVENT_CODE_REBOOT 0x7 /* enum */ -#define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 /* enum */ -#define MCDI_EVENT_CODE_FWALERT 0x9 /* enum */ -#define MCDI_EVENT_CODE_FLR 0xa /* enum */ -#define MCDI_EVENT_CODE_TX_ERR 0xb /* enum */ -#define MCDI_EVENT_CODE_TX_FLUSH 0xc /* enum */ -#define MCDI_EVENT_CODE_PTP_RX 0xd /* enum */ -#define MCDI_EVENT_CODE_PTP_FAULT 0xe /* enum */ -#define MCDI_EVENT_CODE_PTP_PPS 0xf /* enum */ -#define MCDI_EVENT_CODE_AOE 0x12 /* enum */ -#define MCDI_EVENT_CODE_VCAL_FAIL 0x13 /* enum */ -#define MCDI_EVENT_CODE_HW_PPS 0x14 /* enum */ +/* enum: Event generated by host software */ +#define MCDI_EVENT_SW_EVENT 0x0 +/* enum: Bad assert. */ +#define MCDI_EVENT_CODE_BADSSERT 0x1 +/* enum: PM Notice. */ +#define MCDI_EVENT_CODE_PMNOTICE 0x2 +/* enum: Command done. */ +#define MCDI_EVENT_CODE_CMDDONE 0x3 +/* enum: Link change. */ +#define MCDI_EVENT_CODE_LINKCHANGE 0x4 +/* enum: Sensor Event. */ +#define MCDI_EVENT_CODE_SENSOREVT 0x5 +/* enum: Schedule error. */ +#define MCDI_EVENT_CODE_SCHEDERR 0x6 +/* enum: Reboot. */ +#define MCDI_EVENT_CODE_REBOOT 0x7 +/* enum: Mac stats DMA. */ +#define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 +/* enum: Firmware alert. */ +#define MCDI_EVENT_CODE_FWALERT 0x9 +/* enum: Function level reset. */ +#define MCDI_EVENT_CODE_FLR 0xa +/* enum: Transmit error */ +#define MCDI_EVENT_CODE_TX_ERR 0xb +/* enum: Tx flush has completed */ +#define MCDI_EVENT_CODE_TX_FLUSH 0xc +/* enum: PTP packet received timestamp */ +#define MCDI_EVENT_CODE_PTP_RX 0xd +/* enum: PTP NIC failure */ +#define MCDI_EVENT_CODE_PTP_FAULT 0xe +/* enum: PTP PPS event */ +#define MCDI_EVENT_CODE_PTP_PPS 0xf +/* enum: Rx flush has completed */ +#define MCDI_EVENT_CODE_RX_FLUSH 0x10 +/* enum: Receive error */ +#define MCDI_EVENT_CODE_RX_ERR 0x11 +/* enum: AOE fault */ +#define MCDI_EVENT_CODE_AOE 0x12 +/* enum: Network port calibration failed (VCAL). */ +#define MCDI_EVENT_CODE_VCAL_FAIL 0x13 +/* enum: HW PPS event */ +#define MCDI_EVENT_CODE_HW_PPS 0x14 +/* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and + * a different format) + */ +#define MCDI_EVENT_CODE_MC_REBOOT 0x15 +/* enum: the MC has detected a parity error */ +#define MCDI_EVENT_CODE_PAR_ERR 0x16 +/* enum: the MC has detected a correctable error */ +#define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17 +/* enum: the MC has detected an uncorrectable error */ +#define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18 +/* enum: The MC has entered offline BIST mode */ +#define MCDI_EVENT_CODE_MC_BIST 0x19 +/* enum: PTP tick event providing current NIC time */ +#define MCDI_EVENT_CODE_PTP_TIME 0x1a +/* enum: MUM fault */ +#define MCDI_EVENT_CODE_MUM 0x1b +/* enum: notify the designated PF of a new authorization request */ +#define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c +/* enum: notify a function that awaits an authorization that its request has + * been processed and it may now resend the command + */ +#define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d +/* enum: Artificial event generated by host and posted via MC for test + * purposes. + */ +#define MCDI_EVENT_CODE_TESTGEN 0xfa #define MCDI_EVENT_CMDDONE_DATA_OFST 0 #define MCDI_EVENT_CMDDONE_DATA_LBN 0 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 #define MCDI_EVENT_TX_ERR_DATA_OFST 0 #define MCDI_EVENT_TX_ERR_DATA_LBN 0 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 +/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of + * timestamp + */ #define MCDI_EVENT_PTP_SECONDS_OFST 0 #define MCDI_EVENT_PTP_SECONDS_LBN 0 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32 +/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of + * timestamp + */ +#define MCDI_EVENT_PTP_MAJOR_OFST 0 +#define MCDI_EVENT_PTP_MAJOR_LBN 0 +#define MCDI_EVENT_PTP_MAJOR_WIDTH 32 +/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field + * of timestamp + */ #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 +/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of + * timestamp + */ +#define MCDI_EVENT_PTP_MINOR_OFST 0 +#define MCDI_EVENT_PTP_MINOR_LBN 0 +#define MCDI_EVENT_PTP_MINOR_WIDTH 32 +/* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet + */ #define MCDI_EVENT_PTP_UUID_OFST 0 #define MCDI_EVENT_PTP_UUID_LBN 0 #define MCDI_EVENT_PTP_UUID_WIDTH 32 +#define MCDI_EVENT_RX_ERR_DATA_OFST 0 +#define MCDI_EVENT_RX_ERR_DATA_LBN 0 +#define MCDI_EVENT_RX_ERR_DATA_WIDTH 32 +#define MCDI_EVENT_PAR_ERR_DATA_OFST 0 +#define MCDI_EVENT_PAR_ERR_DATA_LBN 0 +#define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32 +#define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0 +#define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0 +#define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32 +#define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0 +#define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0 +#define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32 +/* For CODE_PTP_TIME events, the major value of the PTP clock */ +#define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0 +#define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0 +#define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32 +/* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */ +#define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36 +#define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8 +/* For CODE_PTP_TIME events where report sync status is enabled, indicates + * whether the NIC clock has ever been set + */ +#define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36 +#define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1 +/* For CODE_PTP_TIME events where report sync status is enabled, indicates + * whether the NIC and System clocks are in sync + */ +#define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37 +#define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1 +/* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of + * the minor value of the PTP clock + */ +#define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38 +#define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6 +#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0 +#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0 +#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32 +#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0 +#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0 +#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32 +/* Zero means that the request has been completed or authorized, and the driver + * should resend it. A non-zero value means that the authorization has been + * denied, and gives the reason. Typically it will be EPERM. + */ +#define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36 +#define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8 /* FCDI_EVENT structuredef */ #define FCDI_EVENT_LEN 8 #define FCDI_EVENT_CONT_LBN 32 #define FCDI_EVENT_CONT_WIDTH 1 #define FCDI_EVENT_LEVEL_LBN 33 #define FCDI_EVENT_LEVEL_WIDTH 3 -#define FCDI_EVENT_LEVEL_INFO 0x0 /* enum */ -#define FCDI_EVENT_LEVEL_WARN 0x1 /* enum */ -#define FCDI_EVENT_LEVEL_ERR 0x2 /* enum */ -#define FCDI_EVENT_LEVEL_FATAL 0x3 /* enum */ +/* enum: Info. */ +#define FCDI_EVENT_LEVEL_INFO 0x0 +/* enum: Warning. */ +#define FCDI_EVENT_LEVEL_WARN 0x1 +/* enum: Error. */ +#define FCDI_EVENT_LEVEL_ERR 0x2 +/* enum: Fatal. */ +#define FCDI_EVENT_LEVEL_FATAL 0x3 #define FCDI_EVENT_DATA_OFST 0 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ #define FCDI_EVENT_LINK_UP 0x1 /* enum */ #define FCDI_EVENT_DATA_LBN 0 #define FCDI_EVENT_DATA_WIDTH 32 #define FCDI_EVENT_SRC_LBN 36 #define FCDI_EVENT_SRC_WIDTH 8 #define FCDI_EVENT_EV_CODE_LBN 60 #define FCDI_EVENT_EV_CODE_WIDTH 4 #define FCDI_EVENT_CODE_LBN 44 #define FCDI_EVENT_CODE_WIDTH 8 -#define FCDI_EVENT_CODE_REBOOT 0x1 /* enum */ -#define FCDI_EVENT_CODE_ASSERT 0x2 /* enum */ -#define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 /* enum */ -#define FCDI_EVENT_CODE_LINK_STATE 0x4 /* enum */ -#define FCDI_EVENT_CODE_TIMED_READ 0x5 /* enum */ -#define FCDI_EVENT_CODE_PPS_IN 0x6 /* enum */ -#define FCDI_EVENT_CODE_PTP_TICK 0x7 /* enum */ -#define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 /* enum */ -#define FCDI_EVENT_CODE_PTP_STATUS 0x9 /* enum */ +/* enum: The FC was rebooted. */ +#define FCDI_EVENT_CODE_REBOOT 0x1 +/* enum: Bad assert. */ +#define FCDI_EVENT_CODE_ASSERT 0x2 +/* enum: DDR3 test result. */ +#define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 +/* enum: Link status. */ +#define FCDI_EVENT_CODE_LINK_STATE 0x4 +/* enum: A timed read is ready to be serviced. */ +#define FCDI_EVENT_CODE_TIMED_READ 0x5 +/* enum: One or more PPS IN events */ +#define FCDI_EVENT_CODE_PPS_IN 0x6 +/* enum: Tick event from PTP clock */ +#define FCDI_EVENT_CODE_PTP_TICK 0x7 +/* enum: ECC error counters */ +#define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 +/* enum: Current status of PTP */ +#define FCDI_EVENT_CODE_PTP_STATUS 0x9 +/* enum: Port id config to map MC-FC port idx */ +#define FCDI_EVENT_CODE_PORT_CONFIG 0xa #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 #define FCDI_EVENT_ASSERT_TYPE_LBN 36 #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0 #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 #define FCDI_EVENT_PTP_STATE_OFST 0 #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */ #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */ #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */ #define FCDI_EVENT_PTP_STATE_LBN 0 #define FCDI_EVENT_PTP_STATE_WIDTH 32 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32 +/* Index of MC port being referred to */ +#define FCDI_EVENT_PORT_CONFIG_SRC_LBN 36 +#define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8 +/* FC Port index that matches the MC port index in SRC */ +#define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0 +#define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0 +#define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32 -/* FCDI_EXTENDED_EVENT_PPS structuredef */ +/* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events + * to the MC. Note that this structure | is overlayed over a normal FCDI event + * such that bits 32-63 containing | event code, level, source etc remain the + * same. In this case the data | field of the header is defined to be the + * number of timestamps + */ #define FCDI_EXTENDED_EVENT_PPS_LENMIN 16 #define FCDI_EXTENDED_EVENT_PPS_LENMAX 248 #define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num)) +/* Number of timestamps following */ #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 +/* Seconds field of a timestamp record */ #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 +/* Nanoseconds field of a timestamp record */ #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 +/* Timestamp records comprising the event */ #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64 +/* MUM_EVENT structuredef */ +#define MUM_EVENT_LEN 8 +#define MUM_EVENT_CONT_LBN 32 +#define MUM_EVENT_CONT_WIDTH 1 +#define MUM_EVENT_LEVEL_LBN 33 +#define MUM_EVENT_LEVEL_WIDTH 3 +/* enum: Info. */ +#define MUM_EVENT_LEVEL_INFO 0x0 +/* enum: Warning. */ +#define MUM_EVENT_LEVEL_WARN 0x1 +/* enum: Error. */ +#define MUM_EVENT_LEVEL_ERR 0x2 +/* enum: Fatal. */ +#define MUM_EVENT_LEVEL_FATAL 0x3 +#define MUM_EVENT_DATA_OFST 0 +#define MUM_EVENT_SENSOR_ID_LBN 0 +#define MUM_EVENT_SENSOR_ID_WIDTH 8 +/* Enum values, see field(s): */ +/* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ +#define MUM_EVENT_SENSOR_STATE_LBN 8 +#define MUM_EVENT_SENSOR_STATE_WIDTH 8 +#define MUM_EVENT_PORT_PHY_READY_LBN 0 +#define MUM_EVENT_PORT_PHY_READY_WIDTH 1 +#define MUM_EVENT_PORT_PHY_LINK_UP_LBN 1 +#define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1 +#define MUM_EVENT_PORT_PHY_TX_LOL_LBN 2 +#define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1 +#define MUM_EVENT_PORT_PHY_RX_LOL_LBN 3 +#define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1 +#define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4 +#define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1 +#define MUM_EVENT_PORT_PHY_RX_LOS_LBN 5 +#define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1 +#define MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6 +#define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1 +#define MUM_EVENT_DATA_LBN 0 +#define MUM_EVENT_DATA_WIDTH 32 +#define MUM_EVENT_SRC_LBN 36 +#define MUM_EVENT_SRC_WIDTH 8 +#define MUM_EVENT_EV_CODE_LBN 60 +#define MUM_EVENT_EV_CODE_WIDTH 4 +#define MUM_EVENT_CODE_LBN 44 +#define MUM_EVENT_CODE_WIDTH 8 +/* enum: The MUM was rebooted. */ +#define MUM_EVENT_CODE_REBOOT 0x1 +/* enum: Bad assert. */ +#define MUM_EVENT_CODE_ASSERT 0x2 +/* enum: Sensor failure. */ +#define MUM_EVENT_CODE_SENSOR 0x3 +/* enum: Link fault has been asserted, or has cleared. */ +#define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4 +#define MUM_EVENT_SENSOR_DATA_OFST 0 +#define MUM_EVENT_SENSOR_DATA_LBN 0 +#define MUM_EVENT_SENSOR_DATA_WIDTH 32 +#define MUM_EVENT_PORT_PHY_FLAGS_OFST 0 +#define MUM_EVENT_PORT_PHY_FLAGS_LBN 0 +#define MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32 +#define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0 +#define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0 +#define MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32 +#define MUM_EVENT_PORT_PHY_CAPS_OFST 0 +#define MUM_EVENT_PORT_PHY_CAPS_LBN 0 +#define MUM_EVENT_PORT_PHY_CAPS_WIDTH 32 +#define MUM_EVENT_PORT_PHY_TECH_OFST 0 +#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */ +#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */ +#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */ +#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */ +#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */ +#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */ +#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */ +#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */ +#define MUM_EVENT_PORT_PHY_TECH_LBN 0 +#define MUM_EVENT_PORT_PHY_TECH_WIDTH 32 +#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36 +#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4 +#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */ +#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */ +#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */ +#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */ +#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */ +#define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40 +#define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4 + /***********************************/ /* MC_CMD_READ32 * Read multiple 32byte words from MC memory. */ #define MC_CMD_READ32 0x1 +#undef MC_CMD_0x1_PRIVILEGE_CTG +#define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_READ32_IN msgrequest */ #define MC_CMD_READ32_IN_LEN 8 #define MC_CMD_READ32_IN_ADDR_OFST 0 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4 /* MC_CMD_READ32_OUT msgresponse */ #define MC_CMD_READ32_OUT_LENMIN 4 #define MC_CMD_READ32_OUT_LENMAX 252 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) #define MC_CMD_READ32_OUT_BUFFER_OFST 0 #define MC_CMD_READ32_OUT_BUFFER_LEN 4 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 /***********************************/ /* MC_CMD_WRITE32 * Write multiple 32byte words to MC memory. */ #define MC_CMD_WRITE32 0x2 +#undef MC_CMD_0x2_PRIVILEGE_CTG +#define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_WRITE32_IN msgrequest */ #define MC_CMD_WRITE32_IN_LENMIN 8 #define MC_CMD_WRITE32_IN_LENMAX 252 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) #define MC_CMD_WRITE32_IN_ADDR_OFST 0 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 /* MC_CMD_WRITE32_OUT msgresponse */ #define MC_CMD_WRITE32_OUT_LEN 0 /***********************************/ /* MC_CMD_COPYCODE * Copy MC code between two locations and jump. */ #define MC_CMD_COPYCODE 0x3 +#undef MC_CMD_0x3_PRIVILEGE_CTG +#define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_COPYCODE_IN msgrequest */ #define MC_CMD_COPYCODE_IN_LEN 16 +/* Source address + * + * The main image should be entered via a copy of a single word from and to a + * magic address, which controls various aspects of the boot. The magic address + * is a bitfield, with each bit as documented below. + */ #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 +/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */ +#define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000 +/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and + * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below) + */ +#define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0 +/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT, + * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see + * below) + */ +#define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc +#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17 +#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1 +#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2 +#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1 +#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3 +#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1 +#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4 +#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1 +#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5 +#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1 +/* Destination address */ #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 +/* Address of where to jump after copy. */ #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 -#define MC_CMD_COPYCODE_JUMP_NONE 0x1 /* enum */ +/* enum: Control should return to the caller rather than jumping */ +#define MC_CMD_COPYCODE_JUMP_NONE 0x1 /* MC_CMD_COPYCODE_OUT msgresponse */ #define MC_CMD_COPYCODE_OUT_LEN 0 /***********************************/ -/* MC_CMD_SET_FUNC +/* MC_CMD_SET_FUNC + * Select function for function-specific commands. */ -#define MC_CMD_SET_FUNC 0x4 +#define MC_CMD_SET_FUNC 0x4 +#undef MC_CMD_0x4_PRIVILEGE_CTG +#define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_SET_FUNC_IN msgrequest */ #define MC_CMD_SET_FUNC_IN_LEN 4 +/* Set function */ #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 /* MC_CMD_SET_FUNC_OUT msgresponse */ #define MC_CMD_SET_FUNC_OUT_LEN 0 /***********************************/ /* MC_CMD_GET_BOOT_STATUS + * Get the instruction address from which the MC booted. */ #define MC_CMD_GET_BOOT_STATUS 0x5 +#undef MC_CMD_0x5_PRIVILEGE_CTG +#define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 +/* ?? */ #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 +/* enum: indicates that the MC wasn't flash booted */ +#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 /***********************************/ -/* MC_CMD_GET_ASSERTS - * Get and clear any assertion status. +/* MC_CMD_GET_ASSERTS + * Get (and optionally clear) the current assertion status. Only + * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other + * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS */ -#define MC_CMD_GET_ASSERTS 0x6 +#define MC_CMD_GET_ASSERTS 0x6 +#undef MC_CMD_0x6_PRIVILEGE_CTG +#define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_GET_ASSERTS_IN msgrequest */ #define MC_CMD_GET_ASSERTS_IN_LEN 4 +/* Set to clear assertion */ #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 /* MC_CMD_GET_ASSERTS_OUT msgresponse */ #define MC_CMD_GET_ASSERTS_OUT_LEN 140 +/* Assertion status flag. */ #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 -#define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 /* enum */ -#define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 /* enum */ -#define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 /* enum */ -#define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 /* enum */ +/* enum: No assertions have failed. */ +#define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 +/* enum: A system-level assertion has failed. */ +#define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 +/* enum: A thread-level assertion has failed. */ +#define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 +/* enum: The system was reset by the watchdog. */ +#define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 +/* enum: An illegal address trap stopped the system (huntington and later) */ +#define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 +/* Failing PC value */ #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 +/* Saved GP regs */ #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 +/* enum: A magic value hinting that the value in this register at the time of + * the failure has likely been lost. + */ +#define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 +/* Failing thread address */ #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 /***********************************/ -/* MC_CMD_LOG_CTRL - * Configure the output stream for various events and messages. +/* MC_CMD_LOG_CTRL + * Configure the output stream for log events such as link state changes, + * sensor notifications and MCDI completions */ -#define MC_CMD_LOG_CTRL 0x7 +#define MC_CMD_LOG_CTRL 0x7 +#undef MC_CMD_0x7_PRIVILEGE_CTG +#define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_LOG_CTRL_IN msgrequest */ #define MC_CMD_LOG_CTRL_IN_LEN 8 +/* Log destination */ #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 -#define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 /* enum */ -#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 /* enum */ +/* enum: UART. */ +#define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 +/* enum: Event queue. */ +#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 +/* Legacy argument. Must be zero. */ #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 /* MC_CMD_LOG_CTRL_OUT msgresponse */ #define MC_CMD_LOG_CTRL_OUT_LEN 0 /***********************************/ -/* MC_CMD_GET_VERSION +/* MC_CMD_GET_VERSION * Get version information about the MC firmware. */ -#define MC_CMD_GET_VERSION 0x8 +#define MC_CMD_GET_VERSION 0x8 +#undef MC_CMD_0x8_PRIVILEGE_CTG +#define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_GET_VERSION_IN msgrequest */ #define MC_CMD_GET_VERSION_IN_LEN 0 -/* MC_CMD_GET_VERSION_V0_OUT msgresponse */ +/* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */ +#define MC_CMD_GET_VERSION_EXT_IN_LEN 4 +/* placeholder, set to 0 */ +#define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0 + +/* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */ #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 -#define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff /* enum */ -#define MC_CMD_GET_VERSION_OUT_FIRMWARE_BOOTROM 0xb0070000 /* enum */ -#define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 /* enum */ -#define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 /* enum */ +/* enum: Reserved version number to indicate "any" version. */ +#define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff +/* enum: Bootrom version value for Siena. */ +#define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 +/* enum: Bootrom version value for Huntington. */ +#define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 /* MC_CMD_GET_VERSION_OUT msgresponse */ #define MC_CMD_GET_VERSION_OUT_LEN 32 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ /* Enum values, see field(s): */ /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 +/* 128bit mask of functions supported by the current firmware */ #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 +/* MC_CMD_GET_VERSION_EXT_OUT msgresponse */ +#define MC_CMD_GET_VERSION_EXT_OUT_LEN 48 +/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ +/* Enum values, see field(s): */ +/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ +#define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4 +/* 128bit mask of functions supported by the current firmware */ +#define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8 +#define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16 +#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24 +#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8 +#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24 +#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28 +/* extra info */ +#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32 +#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16 + /***********************************/ -/* MC_CMD_FC +/* MC_CMD_FC * Perform an FC operation */ -#define MC_CMD_FC 0x9 +#define MC_CMD_FC 0x9 /* MC_CMD_FC_IN msgrequest */ #define MC_CMD_FC_IN_LEN 4 #define MC_CMD_FC_IN_OP_HDR_OFST 0 #define MC_CMD_FC_IN_OP_LBN 0 #define MC_CMD_FC_IN_OP_WIDTH 8 -#define MC_CMD_FC_OP_NULL 0x1 /* enum */ -#define MC_CMD_FC_OP_UNUSED 0x2 /* enum */ -#define MC_CMD_FC_OP_MAC 0x3 /* enum */ -#define MC_CMD_FC_OP_READ32 0x4 /* enum */ -#define MC_CMD_FC_OP_WRITE32 0x5 /* enum */ -#define MC_CMD_FC_OP_TRC_READ 0x6 /* enum */ -#define MC_CMD_FC_OP_TRC_WRITE 0x7 /* enum */ -#define MC_CMD_FC_OP_GET_VERSION 0x8 /* enum */ -#define MC_CMD_FC_OP_TRC_RX_READ 0x9 /* enum */ -#define MC_CMD_FC_OP_TRC_RX_WRITE 0xa /* enum */ -#define MC_CMD_FC_OP_SFP 0xb /* enum */ -#define MC_CMD_FC_OP_DDR_TEST 0xc /* enum */ -#define MC_CMD_FC_OP_GET_ASSERT 0xd /* enum */ -#define MC_CMD_FC_OP_FPGA_BUILD 0xe /* enum */ -#define MC_CMD_FC_OP_READ_MAP 0xf /* enum */ -#define MC_CMD_FC_OP_CAPABILITIES 0x10 /* enum */ -#define MC_CMD_FC_OP_GLOBAL_FLAGS 0x11 /* enum */ -#define MC_CMD_FC_OP_IO_REL 0x12 /* enum */ -#define MC_CMD_FC_OP_UHLINK 0x13 /* enum */ -#define MC_CMD_FC_OP_SET_LINK 0x14 /* enum */ -#define MC_CMD_FC_OP_LICENSE 0x15 /* enum */ -#define MC_CMD_FC_OP_STARTUP 0x16 /* enum */ -#define MC_CMD_FC_OP_DMA 0x17 /* enum */ -#define MC_CMD_FC_OP_TIMED_READ 0x18 /* enum */ -#define MC_CMD_FC_OP_LOG 0x19 /* enum */ -#define MC_CMD_FC_OP_CLOCK 0x1a /* enum */ -#define MC_CMD_FC_OP_DDR 0x1b /* enum */ -#define MC_CMD_FC_OP_TIMESTAMP 0x1c /* enum */ -#define MC_CMD_FC_OP_SPI 0x1d /* enum */ -#define MC_CMD_FC_OP_DIAG 0x1e /* enum */ -#define MC_CMD_FC_IN_PORT_EXT_OFST 0x0 /* enum */ -#define MC_CMD_FC_IN_PORT_INT_OFST 0x40 /* enum */ +/* enum: NULL MCDI command to FC. */ +#define MC_CMD_FC_OP_NULL 0x1 +/* enum: Unused opcode */ +#define MC_CMD_FC_OP_UNUSED 0x2 +/* enum: MAC driver commands */ +#define MC_CMD_FC_OP_MAC 0x3 +/* enum: Read FC memory */ +#define MC_CMD_FC_OP_READ32 0x4 +/* enum: Write to FC memory */ +#define MC_CMD_FC_OP_WRITE32 0x5 +/* enum: Read FC memory */ +#define MC_CMD_FC_OP_TRC_READ 0x6 +/* enum: Write to FC memory */ +#define MC_CMD_FC_OP_TRC_WRITE 0x7 +/* enum: FC firmware Version */ +#define MC_CMD_FC_OP_GET_VERSION 0x8 +/* enum: Read FC memory */ +#define MC_CMD_FC_OP_TRC_RX_READ 0x9 +/* enum: Write to FC memory */ +#define MC_CMD_FC_OP_TRC_RX_WRITE 0xa +/* enum: SFP parameters */ +#define MC_CMD_FC_OP_SFP 0xb +/* enum: DDR3 test */ +#define MC_CMD_FC_OP_DDR_TEST 0xc +/* enum: Get Crash context from FC */ +#define MC_CMD_FC_OP_GET_ASSERT 0xd +/* enum: Get FPGA Build registers */ +#define MC_CMD_FC_OP_FPGA_BUILD 0xe +/* enum: Read map support commands */ +#define MC_CMD_FC_OP_READ_MAP 0xf +/* enum: FC Capabilities */ +#define MC_CMD_FC_OP_CAPABILITIES 0x10 +/* enum: FC Global flags */ +#define MC_CMD_FC_OP_GLOBAL_FLAGS 0x11 +/* enum: FC IO using relative addressing modes */ +#define MC_CMD_FC_OP_IO_REL 0x12 +/* enum: FPGA link information */ +#define MC_CMD_FC_OP_UHLINK 0x13 +/* enum: Configure loopbacks and link on FPGA ports */ +#define MC_CMD_FC_OP_SET_LINK 0x14 +/* enum: Licensing operations relating to AOE */ +#define MC_CMD_FC_OP_LICENSE 0x15 +/* enum: Startup information to the FC */ +#define MC_CMD_FC_OP_STARTUP 0x16 +/* enum: Configure a DMA read */ +#define MC_CMD_FC_OP_DMA 0x17 +/* enum: Configure a timed read */ +#define MC_CMD_FC_OP_TIMED_READ 0x18 +/* enum: Control UART logging */ +#define MC_CMD_FC_OP_LOG 0x19 +/* enum: Get the value of a given clock_id */ +#define MC_CMD_FC_OP_CLOCK 0x1a +/* enum: DDR3/QDR3 parameters */ +#define MC_CMD_FC_OP_DDR 0x1b +/* enum: PTP and timestamp control */ +#define MC_CMD_FC_OP_TIMESTAMP 0x1c +/* enum: Commands for SPI Flash interface */ +#define MC_CMD_FC_OP_SPI 0x1d +/* enum: Commands for diagnostic components */ +#define MC_CMD_FC_OP_DIAG 0x1e +/* enum: External AOE port. */ +#define MC_CMD_FC_IN_PORT_EXT_OFST 0x0 +/* enum: Internal AOE port. */ +#define MC_CMD_FC_IN_PORT_INT_OFST 0x40 /* MC_CMD_FC_IN_NULL msgrequest */ #define MC_CMD_FC_IN_NULL_LEN 4 #define MC_CMD_FC_IN_CMD_OFST 0 +/* MC_CMD_FC_IN_PHY msgrequest */ +#define MC_CMD_FC_IN_PHY_LEN 5 +/* MC_CMD_FC_IN_CMD_OFST 0 */ +/* FC PHY driver operation code */ +#define MC_CMD_FC_IN_PHY_OP_OFST 4 +#define MC_CMD_FC_IN_PHY_OP_LEN 1 +/* enum: PHY init handler */ +#define MC_CMD_FC_OP_PHY_OP_INIT 0x1 +/* enum: PHY reconfigure handler */ +#define MC_CMD_FC_OP_PHY_OP_RECONFIGURE 0x2 +/* enum: PHY reboot handler */ +#define MC_CMD_FC_OP_PHY_OP_REBOOT 0x3 +/* enum: PHY get_supported_cap handler */ +#define MC_CMD_FC_OP_PHY_OP_GET_SUPPORTED_CAP 0x4 +/* enum: PHY get_config handler */ +#define MC_CMD_FC_OP_PHY_OP_GET_CONFIG 0x5 +/* enum: PHY get_media_info handler */ +#define MC_CMD_FC_OP_PHY_OP_GET_MEDIA_INFO 0x6 +/* enum: PHY set_led handler */ +#define MC_CMD_FC_OP_PHY_OP_SET_LED 0x7 +/* enum: PHY lasi_interrupt handler */ +#define MC_CMD_FC_OP_PHY_OP_LASI_INTERRUPT 0x8 +/* enum: PHY check_link handler */ +#define MC_CMD_FC_OP_PHY_OP_CHECK_LINK 0x9 +/* enum: PHY fill_stats handler */ +#define MC_CMD_FC_OP_PHY_OP_FILL_STATS 0xa +/* enum: PHY bpx_link_state_changed handler */ +#define MC_CMD_FC_OP_PHY_OP_BPX_LINK_STATE_CHANGED 0xb +/* enum: PHY get_state handler */ +#define MC_CMD_FC_OP_PHY_OP_GET_STATE 0xc +/* enum: PHY start_bist handler */ +#define MC_CMD_FC_OP_PHY_OP_START_BIST 0xd +/* enum: PHY poll_bist handler */ +#define MC_CMD_FC_OP_PHY_OP_POLL_BIST 0xe +/* enum: PHY nvram_test handler */ +#define MC_CMD_FC_OP_PHY_OP_NVRAM_TEST 0xf +/* enum: PHY relinquish handler */ +#define MC_CMD_FC_OP_PHY_OP_RELINQUISH_SPI 0x10 +/* enum: PHY read connection from FC - may be not required */ +#define MC_CMD_FC_OP_PHY_OP_GET_CONNECTION 0x11 +/* enum: PHY read flags from FC - may be not required */ +#define MC_CMD_FC_OP_PHY_OP_GET_FLAGS 0x12 + +/* MC_CMD_FC_IN_PHY_INIT msgrequest */ +#define MC_CMD_FC_IN_PHY_INIT_LEN 4 +#define MC_CMD_FC_IN_PHY_CMD_OFST 0 + /* MC_CMD_FC_IN_MAC msgrequest */ #define MC_CMD_FC_IN_MAC_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_MAC_HEADER_OFST 4 #define MC_CMD_FC_IN_MAC_OP_LBN 0 #define MC_CMD_FC_IN_MAC_OP_WIDTH 8 -#define MC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1 /* enum */ -#define MC_CMD_FC_OP_MAC_OP_SET_LINK 0x2 /* enum */ -#define MC_CMD_FC_OP_MAC_OP_GET_STATS 0x3 /* enum */ -#define MC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6 /* enum */ -#define MC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7 /* enum */ -#define MC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8 /* enum */ +/* enum: MAC reconfigure handler */ +#define MC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1 +/* enum: MAC Set command - same as MC_CMD_SET_MAC */ +#define MC_CMD_FC_OP_MAC_OP_SET_LINK 0x2 +/* enum: MAC statistics */ +#define MC_CMD_FC_OP_MAC_OP_GET_STATS 0x3 +/* enum: MAC RX statistics */ +#define MC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6 +/* enum: MAC TX statistics */ +#define MC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7 +/* enum: MAC Read status */ +#define MC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8 #define MC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8 #define MC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8 -#define MC_CMD_FC_PORT_EXT 0x0 /* enum */ -#define MC_CMD_FC_PORT_INT 0x1 /* enum */ +/* enum: External FPGA port. */ +#define MC_CMD_FC_PORT_EXT 0x0 +/* enum: Internal Siena-facing FPGA ports. */ +#define MC_CMD_FC_PORT_INT 0x1 #define MC_CMD_FC_IN_MAC_PORT_IDX_LBN 16 #define MC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8 -#define MC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0 /* enum */ -#define MC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1 /* enum */ +/* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are + * irrelevant. Port number is derived from pci_fn; passed in FC header. + */ +#define MC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0 +/* enum: Override default port number. Port number determined by fields + * PORT_TYPE and PORT_IDX. + */ +#define MC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1 /* MC_CMD_FC_IN_MAC_RECONFIGURE msgrequest */ #define MC_CMD_FC_IN_MAC_RECONFIGURE_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ /* MC_CMD_FC_IN_MAC_SET_LINK msgrequest */ #define MC_CMD_FC_IN_MAC_SET_LINK_LEN 32 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ +/* MTU size */ #define MC_CMD_FC_IN_MAC_SET_LINK_MTU_OFST 8 +/* Drain Tx FIFO */ #define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_OFST 12 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_LBN 0 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_WIDTH 1 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_LBN 1 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_WIDTH 1 #define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_OFST 28 /* MC_CMD_FC_IN_MAC_READ_STATUS msgrequest */ #define MC_CMD_FC_IN_MAC_READ_STATUS_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ /* MC_CMD_FC_IN_MAC_GET_RX_STATS msgrequest */ #define MC_CMD_FC_IN_MAC_GET_RX_STATS_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ /* MC_CMD_FC_IN_MAC_GET_TX_STATS msgrequest */ #define MC_CMD_FC_IN_MAC_GET_TX_STATS_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ /* MC_CMD_FC_IN_MAC_GET_STATS msgrequest */ #define MC_CMD_FC_IN_MAC_GET_STATS_LEN 20 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ +/* MC Statistics index */ #define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_OFST 8 #define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_WIDTH 1 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_LBN 1 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1 +/* Number of statistics to read */ #define MC_CMD_FC_IN_MAC_GET_STATS_NUM_OFST 16 #define MC_CMD_FC_MAC_NSTATS_PER_BLOCK 0x1e /* enum */ #define MC_CMD_FC_MAC_NBYTES_PER_STAT 0x8 /* enum */ /* MC_CMD_FC_IN_READ32 msgrequest */ #define MC_CMD_FC_IN_READ32_LEN 16 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_READ32_ADDR_HI_OFST 4 #define MC_CMD_FC_IN_READ32_ADDR_LO_OFST 8 #define MC_CMD_FC_IN_READ32_NUMWORDS_OFST 12 /* MC_CMD_FC_IN_WRITE32 msgrequest */ #define MC_CMD_FC_IN_WRITE32_LENMIN 16 #define MC_CMD_FC_IN_WRITE32_LENMAX 252 #define MC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num)) /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4 #define MC_CMD_FC_IN_WRITE32_ADDR_LO_OFST 8 #define MC_CMD_FC_IN_WRITE32_BUFFER_OFST 12 #define MC_CMD_FC_IN_WRITE32_BUFFER_LEN 4 #define MC_CMD_FC_IN_WRITE32_BUFFER_MINNUM 1 #define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM 60 /* MC_CMD_FC_IN_TRC_READ msgrequest */ #define MC_CMD_FC_IN_TRC_READ_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_TRC_READ_TRC_OFST 4 #define MC_CMD_FC_IN_TRC_READ_CHANNEL_OFST 8 /* MC_CMD_FC_IN_TRC_WRITE msgrequest */ #define MC_CMD_FC_IN_TRC_WRITE_LEN 28 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_TRC_WRITE_TRC_OFST 4 #define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_OFST 8 #define MC_CMD_FC_IN_TRC_WRITE_DATA_OFST 12 #define MC_CMD_FC_IN_TRC_WRITE_DATA_LEN 4 #define MC_CMD_FC_IN_TRC_WRITE_DATA_NUM 4 /* MC_CMD_FC_IN_GET_VERSION msgrequest */ #define MC_CMD_FC_IN_GET_VERSION_LEN 4 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_TRC_RX_READ msgrequest */ #define MC_CMD_FC_IN_TRC_RX_READ_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_TRC_RX_READ_TRC_OFST 4 #define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_OFST 8 /* MC_CMD_FC_IN_TRC_RX_WRITE msgrequest */ #define MC_CMD_FC_IN_TRC_RX_WRITE_LEN 20 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_OFST 4 #define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_OFST 8 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_OFST 12 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_LEN 4 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_NUM 2 /* MC_CMD_FC_IN_SFP msgrequest */ -#define MC_CMD_FC_IN_SFP_LEN 24 +#define MC_CMD_FC_IN_SFP_LEN 28 /* MC_CMD_FC_IN_CMD_OFST 0 */ +/* Link speed is 100, 1000, 10000, 40000 */ #define MC_CMD_FC_IN_SFP_SPEED_OFST 4 +/* Length of copper cable - zero when not relevant (e.g. if cable is fibre) */ #define MC_CMD_FC_IN_SFP_COPPER_LEN_OFST 8 +/* Not relevant for cards with QSFP modules. For older cards, true if module is + * a dual speed SFP+ module. + */ #define MC_CMD_FC_IN_SFP_DUAL_SPEED_OFST 12 +/* True if an SFP Module is present (other fields valid when true) */ #define MC_CMD_FC_IN_SFP_PRESENT_OFST 16 +/* The type of the SFP+ Module. For later cards with QSFP modules, this field + * is unused and the type is communicated by other means. + */ #define MC_CMD_FC_IN_SFP_TYPE_OFST 20 +/* Capabilities corresponding to 1 bits. */ +#define MC_CMD_FC_IN_SFP_CAPS_OFST 24 /* MC_CMD_FC_IN_DDR_TEST msgrequest */ #define MC_CMD_FC_IN_DDR_TEST_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 #define MC_CMD_FC_IN_DDR_TEST_OP_LBN 0 #define MC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8 -#define MC_CMD_FC_OP_DDR_TEST_START 0x1 /* enum */ -#define MC_CMD_FC_OP_DDR_TEST_POLL 0x2 /* enum */ +/* enum: DRAM Test Start */ +#define MC_CMD_FC_OP_DDR_TEST_START 0x1 +/* enum: DRAM Test Poll */ +#define MC_CMD_FC_OP_DDR_TEST_POLL 0x2 /* MC_CMD_FC_IN_DDR_TEST_START msgrequest */ #define MC_CMD_FC_IN_DDR_TEST_START_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ #define MC_CMD_FC_IN_DDR_TEST_START_MASK_OFST 8 #define MC_CMD_FC_IN_DDR_TEST_START_T0_LBN 0 #define MC_CMD_FC_IN_DDR_TEST_START_T0_WIDTH 1 #define MC_CMD_FC_IN_DDR_TEST_START_T1_LBN 1 #define MC_CMD_FC_IN_DDR_TEST_START_T1_WIDTH 1 #define MC_CMD_FC_IN_DDR_TEST_START_B0_LBN 2 #define MC_CMD_FC_IN_DDR_TEST_START_B0_WIDTH 1 #define MC_CMD_FC_IN_DDR_TEST_START_B1_LBN 3 #define MC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1 /* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */ #define MC_CMD_FC_IN_DDR_TEST_POLL_LEN 8 #define MC_CMD_FC_IN_DDR_TEST_CMD_OFST 0 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ /* MC_CMD_FC_IN_GET_ASSERT msgrequest */ #define MC_CMD_FC_IN_GET_ASSERT_LEN 4 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_FPGA_BUILD msgrequest */ #define MC_CMD_FC_IN_FPGA_BUILD_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ +/* FPGA build info operation code */ #define MC_CMD_FC_IN_FPGA_BUILD_OP_OFST 4 -#define MC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1 /* enum */ -#define MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2 /* enum */ -#define MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3 /* enum */ +/* enum: Get the build registers */ +#define MC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1 +/* enum: Get the services registers */ +#define MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2 +/* enum: Get the BSP version */ +#define MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3 /* MC_CMD_FC_IN_READ_MAP msgrequest */ #define MC_CMD_FC_IN_READ_MAP_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 #define MC_CMD_FC_IN_READ_MAP_OP_LBN 0 #define MC_CMD_FC_IN_READ_MAP_OP_WIDTH 8 -#define MC_CMD_FC_OP_READ_MAP_COUNT 0x1 /* enum */ -#define MC_CMD_FC_OP_READ_MAP_INDEX 0x2 /* enum */ +/* enum: Get the number of map regions */ +#define MC_CMD_FC_OP_READ_MAP_COUNT 0x1 +/* enum: Get the specified map */ +#define MC_CMD_FC_OP_READ_MAP_INDEX 0x2 /* MC_CMD_FC_IN_READ_MAP_COUNT msgrequest */ #define MC_CMD_FC_IN_READ_MAP_COUNT_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ /* MC_CMD_FC_IN_READ_MAP_INDEX msgrequest */ #define MC_CMD_FC_IN_READ_MAP_INDEX_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ #define MC_CMD_FC_IN_MAP_INDEX_OFST 8 /* MC_CMD_FC_IN_CAPABILITIES msgrequest */ #define MC_CMD_FC_IN_CAPABILITIES_LEN 4 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_GLOBAL_FLAGS msgrequest */ #define MC_CMD_FC_IN_GLOBAL_FLAGS_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_OFST 4 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_LBN 0 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_WIDTH 1 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_LBN 1 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_WIDTH 1 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_LBN 2 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_WIDTH 1 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_LBN 3 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_WIDTH 1 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_LBN 4 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_WIDTH 1 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_LBN 5 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_WIDTH 1 /* MC_CMD_FC_IN_IO_REL msgrequest */ #define MC_CMD_FC_IN_IO_REL_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 #define MC_CMD_FC_IN_IO_REL_OP_LBN 0 #define MC_CMD_FC_IN_IO_REL_OP_WIDTH 8 -#define MC_CMD_FC_IN_IO_REL_GET_ADDR 0x1 /* enum */ -#define MC_CMD_FC_IN_IO_REL_READ32 0x2 /* enum */ -#define MC_CMD_FC_IN_IO_REL_WRITE32 0x3 /* enum */ +/* enum: Get the base address that the FC applies to relative commands */ +#define MC_CMD_FC_IN_IO_REL_GET_ADDR 0x1 +/* enum: Read data */ +#define MC_CMD_FC_IN_IO_REL_READ32 0x2 +/* enum: Write data */ +#define MC_CMD_FC_IN_IO_REL_WRITE32 0x3 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8 -#define MC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1 /* enum */ -#define MC_CMD_FC_COMP_TYPE_FLASH 0x2 /* enum */ +/* enum: Application address space */ +#define MC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1 +/* enum: Flash address space */ +#define MC_CMD_FC_COMP_TYPE_FLASH 0x2 /* MC_CMD_FC_IN_IO_REL_GET_ADDR msgrequest */ #define MC_CMD_FC_IN_IO_REL_GET_ADDR_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ /* MC_CMD_FC_IN_IO_REL_READ32 msgrequest */ #define MC_CMD_FC_IN_IO_REL_READ32_LEN 20 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_OFST 8 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_OFST 12 #define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_OFST 16 /* MC_CMD_FC_IN_IO_REL_WRITE32 msgrequest */ #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMIN 20 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252 #define MC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num)) /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_OFST 8 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_OFST 12 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_OFST 16 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_LEN 4 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MINNUM 1 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM 59 /* MC_CMD_FC_IN_UHLINK msgrequest */ #define MC_CMD_FC_IN_UHLINK_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 #define MC_CMD_FC_IN_UHLINK_OP_LBN 0 #define MC_CMD_FC_IN_UHLINK_OP_WIDTH 8 -#define MC_CMD_FC_OP_UHLINK_PHY 0x1 /* enum */ -#define MC_CMD_FC_OP_UHLINK_MAC 0x2 /* enum */ -#define MC_CMD_FC_OP_UHLINK_RX_EYE 0x3 /* enum */ -#define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4 /* enum */ -#define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5 /* enum */ -#define MC_CMD_FC_OP_UHLINK_RX_TUNE 0x6 /* enum */ -#define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7 /* enum */ -#define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8 /* enum */ +/* enum: Get PHY configuration info */ +#define MC_CMD_FC_OP_UHLINK_PHY 0x1 +/* enum: Get MAC configuration info */ +#define MC_CMD_FC_OP_UHLINK_MAC 0x2 +/* enum: Get Rx eye table */ +#define MC_CMD_FC_OP_UHLINK_RX_EYE 0x3 +/* enum: Get Rx eye plot */ +#define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4 +/* enum: Get Rx eye plot */ +#define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5 +/* enum: Retune Rx settings */ +#define MC_CMD_FC_OP_UHLINK_RX_TUNE 0x6 +/* enum: Set loopback mode on fpga port */ +#define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7 +/* enum: Get loopback mode config state on fpga port */ +#define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8 -#define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0 /* enum */ -#define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1 /* enum */ +/* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are + * irrelevant. Port number is derived from pci_fn; passed in FC header. + */ +#define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0 +/* enum: Override default port number. Port number determined by fields + * PORT_TYPE and PORT_IDX. + */ +#define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1 /* MC_CMD_FC_OP_UHLINK_PHY msgrequest */ #define MC_CMD_FC_OP_UHLINK_PHY_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ /* MC_CMD_FC_OP_UHLINK_MAC msgrequest */ #define MC_CMD_FC_OP_UHLINK_MAC_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ /* MC_CMD_FC_OP_UHLINK_RX_EYE msgrequest */ #define MC_CMD_FC_OP_UHLINK_RX_EYE_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ #define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_OFST 8 #define MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 0x30 /* enum */ /* MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT msgrequest */ #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ /* MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT msgrequest */ #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_LEN 20 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_OFST 8 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_OFST 12 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_OFST 16 #define MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 0x1e /* enum */ /* MC_CMD_FC_OP_UHLINK_RX_TUNE msgrequest */ #define MC_CMD_FC_OP_UHLINK_RX_TUNE_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ /* MC_CMD_FC_OP_UHLINK_LOOPBACK_SET msgrequest */ #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_LEN 16 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_OFST 8 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PCS_SERIAL 0x0 /* enum */ #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_PRE_CDR 0x1 /* enum */ #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_POST_CDR 0x2 /* enum */ #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_OFST 12 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_OFF 0x0 /* enum */ #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_ON 0x1 /* enum */ /* MC_CMD_FC_OP_UHLINK_LOOPBACK_GET msgrequest */ #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_OFST 8 /* MC_CMD_FC_IN_SET_LINK msgrequest */ #define MC_CMD_FC_IN_SET_LINK_LEN 16 /* MC_CMD_FC_IN_CMD_OFST 0 */ +/* See MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ #define MC_CMD_FC_IN_SET_LINK_MODE_OFST 4 #define MC_CMD_FC_IN_SET_LINK_SPEED_OFST 8 #define MC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_LBN 0 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_WIDTH 1 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_LBN 1 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_WIDTH 1 #define MC_CMD_FC_IN_SET_LINK_TXDIS_LBN 2 #define MC_CMD_FC_IN_SET_LINK_TXDIS_WIDTH 1 /* MC_CMD_FC_IN_LICENSE msgrequest */ #define MC_CMD_FC_IN_LICENSE_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_LICENSE_OP_OFST 4 #define MC_CMD_FC_IN_LICENSE_UPDATE_LICENSE 0x0 /* enum */ #define MC_CMD_FC_IN_LICENSE_GET_KEY_STATS 0x1 /* enum */ /* MC_CMD_FC_IN_STARTUP msgrequest */ #define MC_CMD_FC_IN_STARTUP_LEN 40 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_STARTUP_BASE_OFST 4 #define MC_CMD_FC_IN_STARTUP_LENGTH_OFST 8 +/* Length of identifier */ #define MC_CMD_FC_IN_STARTUP_IDLENGTH_OFST 12 +/* Identifier for AOE FPGA */ #define MC_CMD_FC_IN_STARTUP_ID_OFST 16 #define MC_CMD_FC_IN_STARTUP_ID_LEN 1 #define MC_CMD_FC_IN_STARTUP_ID_NUM 24 /* MC_CMD_FC_IN_DMA msgrequest */ #define MC_CMD_FC_IN_DMA_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DMA_OP_OFST 4 #define MC_CMD_FC_IN_DMA_STOP 0x0 /* enum */ #define MC_CMD_FC_IN_DMA_READ 0x1 /* enum */ /* MC_CMD_FC_IN_DMA_STOP msgrequest */ #define MC_CMD_FC_IN_DMA_STOP_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ +/* FC supplied handle */ #define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_OFST 8 /* MC_CMD_FC_IN_DMA_READ msgrequest */ #define MC_CMD_FC_IN_DMA_READ_LEN 16 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ #define MC_CMD_FC_IN_DMA_READ_OFFSET_OFST 8 #define MC_CMD_FC_IN_DMA_READ_LENGTH_OFST 12 /* MC_CMD_FC_IN_TIMED_READ msgrequest */ #define MC_CMD_FC_IN_TIMED_READ_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 #define MC_CMD_FC_IN_TIMED_READ_SET 0x0 /* enum */ #define MC_CMD_FC_IN_TIMED_READ_GET 0x1 /* enum */ #define MC_CMD_FC_IN_TIMED_READ_CLEAR 0x2 /* enum */ /* MC_CMD_FC_IN_TIMED_READ_SET msgrequest */ #define MC_CMD_FC_IN_TIMED_READ_SET_LEN 52 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ +/* Host supplied handle (unique) */ #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_OFST 8 +/* Address into which to transfer data in host */ #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16 +/* AOE address from which to transfer data */ #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24 +/* Length of AOE transfer (total) */ #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28 +/* Length of host transfer (total) */ #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_OFST 32 +/* Offset back from aoe_address to apply operation to */ #define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_OFST 36 +/* Data to apply at offset */ #define MC_CMD_FC_IN_TIMED_READ_SET_DATA_OFST 40 #define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_WIDTH 1 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_LBN 1 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_WIDTH 1 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_LBN 2 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2 #define MC_CMD_FC_IN_TIMED_READ_SET_NONE 0x0 /* enum */ #define MC_CMD_FC_IN_TIMED_READ_SET_READ 0x1 /* enum */ #define MC_CMD_FC_IN_TIMED_READ_SET_WRITE 0x2 /* enum */ #define MC_CMD_FC_IN_TIMED_READ_SET_READWRITE 0x3 /* enum */ +/* Period at which reads are performed (100ms units) */ #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48 /* MC_CMD_FC_IN_TIMED_READ_GET msgrequest */ #define MC_CMD_FC_IN_TIMED_READ_GET_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ +/* FC supplied handle */ #define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_OFST 8 /* MC_CMD_FC_IN_TIMED_READ_CLEAR msgrequest */ #define MC_CMD_FC_IN_TIMED_READ_CLEAR_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ +/* FC supplied handle */ #define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_OFST 8 /* MC_CMD_FC_IN_LOG msgrequest */ #define MC_CMD_FC_IN_LOG_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_LOG_OP_OFST 4 #define MC_CMD_FC_IN_LOG_ADDR_RANGE 0x0 /* enum */ #define MC_CMD_FC_IN_LOG_JTAG_UART 0x1 /* enum */ /* MC_CMD_FC_IN_LOG_ADDR_RANGE msgrequest */ #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ +/* Partition offset into flash */ #define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_OFST 8 +/* Partition length */ #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_OFST 12 +/* Partition erase size */ #define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_OFST 16 /* MC_CMD_FC_IN_LOG_JTAG_UART msgrequest */ #define MC_CMD_FC_IN_LOG_JTAG_UART_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ +/* Enable/disable printing to JTAG UART */ #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8 /* MC_CMD_FC_IN_CLOCK msgrequest */ #define MC_CMD_FC_IN_CLOCK_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_CLOCK_OP_OFST 4 #define MC_CMD_FC_IN_CLOCK_GET_TIME 0x0 /* enum */ #define MC_CMD_FC_IN_CLOCK_SET_TIME 0x1 /* enum */ +/* Perform a clock operation */ #define MC_CMD_FC_IN_CLOCK_ID_OFST 8 #define MC_CMD_FC_IN_CLOCK_STATS 0x0 /* enum */ #define MC_CMD_FC_IN_CLOCK_MAC 0x1 /* enum */ /* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest */ #define MC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ +/* Retrieve the clock value of the specified clock */ /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ /* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest */ #define MC_CMD_FC_IN_CLOCK_SET_TIME_LEN 24 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16 +/* Set the clock value of the specified clock */ #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20 /* MC_CMD_FC_IN_DDR msgrequest */ #define MC_CMD_FC_IN_DDR_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DDR_OP_OFST 4 #define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */ #define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */ #define MC_CMD_FC_IN_DDR_BANK_OFST 8 #define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */ #define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */ #define MC_CMD_FC_IN_DDR_BANK_T0 0x2 /* enum */ #define MC_CMD_FC_IN_DDR_BANK_T1 0x3 /* enum */ #define MC_CMD_FC_IN_DDR_NUM_BANKS 0x4 /* enum */ /* MC_CMD_FC_IN_DDR_SET_SPD msgrequest */ #define MC_CMD_FC_IN_DDR_SET_SPD_LEN 148 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ +/* Affected bank */ /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ +/* Flags */ #define MC_CMD_FC_IN_DDR_FLAGS_OFST 12 #define MC_CMD_FC_IN_DDR_SET_SPD_ACTIVE 0x1 /* enum */ +/* 128-byte page of serial presence detect data read from module's EEPROM */ #define MC_CMD_FC_IN_DDR_SPD_OFST 16 #define MC_CMD_FC_IN_DDR_SPD_LEN 1 #define MC_CMD_FC_IN_DDR_SPD_NUM 128 +/* Page index of the spd data copied into MC_CMD_FC_IN_DDR_SPD */ #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144 /* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */ #define MC_CMD_FC_IN_DDR_GET_STATUS_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ +/* Affected bank */ /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ /* MC_CMD_FC_IN_TIMESTAMP msgrequest */ #define MC_CMD_FC_IN_TIMESTAMP_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ +/* FC timestamp operation code */ #define MC_CMD_FC_IN_TIMESTAMP_OP_OFST 4 -#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0 /* enum */ -#define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1 /* enum */ -#define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2 /* enum */ +/* enum: Read transmit timestamp(s) */ +#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0 +/* enum: Read snapshot timestamps */ +#define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1 +/* enum: Clear all transmit timestamps */ +#define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2 /* MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT msgrequest */ #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LEN 28 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_OFST 4 +/* Control filtering of the returned timestamp and sequence number specified + * here + */ #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_OFST 8 -#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0 /* enum */ -#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1 /* enum */ +/* enum: Return most recent timestamp. No filtering */ +#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0 +/* enum: Match timestamp against the PTP clock ID, port number and sequence + * number specified + */ +#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1 +/* Clock identity of PTP packet for which timestamp required */ #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16 +/* Port number of PTP packet for which timestamp required */ #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20 +/* Sequence number of PTP packet for which timestamp required */ #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_OFST 24 /* MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT msgrequest */ #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_OFST 4 /* MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT msgrequest */ #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_OFST 4 /* MC_CMD_FC_IN_SPI msgrequest */ #define MC_CMD_FC_IN_SPI_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ +/* Basic commands for SPI Flash. */ #define MC_CMD_FC_IN_SPI_OP_OFST 4 -#define MC_CMD_FC_IN_SPI_READ 0x0 /* enum */ -#define MC_CMD_FC_IN_SPI_WRITE 0x1 /* enum */ -#define MC_CMD_FC_IN_SPI_ERASE 0x2 /* enum */ +/* enum: SPI Flash read */ +#define MC_CMD_FC_IN_SPI_READ 0x0 +/* enum: SPI Flash write */ +#define MC_CMD_FC_IN_SPI_WRITE 0x1 +/* enum: SPI Flash erase */ +#define MC_CMD_FC_IN_SPI_ERASE 0x2 /* MC_CMD_FC_IN_SPI_READ msgrequest */ #define MC_CMD_FC_IN_SPI_READ_LEN 16 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_SPI_READ_OP_OFST 4 #define MC_CMD_FC_IN_SPI_READ_ADDR_OFST 8 #define MC_CMD_FC_IN_SPI_READ_NUMBYTES_OFST 12 /* MC_CMD_FC_IN_SPI_WRITE msgrequest */ #define MC_CMD_FC_IN_SPI_WRITE_LENMIN 16 #define MC_CMD_FC_IN_SPI_WRITE_LENMAX 252 #define MC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num)) /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_SPI_WRITE_OP_OFST 4 #define MC_CMD_FC_IN_SPI_WRITE_ADDR_OFST 8 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_OFST 12 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_LEN 4 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MINNUM 1 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM 60 /* MC_CMD_FC_IN_SPI_ERASE msgrequest */ #define MC_CMD_FC_IN_SPI_ERASE_LEN 16 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_SPI_ERASE_OP_OFST 4 #define MC_CMD_FC_IN_SPI_ERASE_ADDR_OFST 8 #define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_OFST 12 /* MC_CMD_FC_IN_DIAG msgrequest */ #define MC_CMD_FC_IN_DIAG_LEN 8 /* MC_CMD_FC_IN_CMD_OFST 0 */ +/* Operation code indicating component type */ #define MC_CMD_FC_IN_DIAG_OP_OFST 4 -#define MC_CMD_FC_IN_DIAG_POWER_NOISE 0x0 /* enum */ -#define MC_CMD_FC_IN_DIAG_DDR_SOAK 0x1 /* enum */ -#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2 /* enum */ +/* enum: Power noise generator. */ +#define MC_CMD_FC_IN_DIAG_POWER_NOISE 0x0 +/* enum: DDR soak test component. */ +#define MC_CMD_FC_IN_DIAG_DDR_SOAK 0x1 +/* enum: Diagnostics datapath control component. */ +#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2 /* MC_CMD_FC_IN_DIAG_POWER_NOISE msgrequest */ #define MC_CMD_FC_IN_DIAG_POWER_NOISE_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_OFST 4 +/* Sub-opcode describing the operation to be carried out */ #define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_OFST 8 -#define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0 /* enum */ -#define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1 /* enum */ +/* enum: Read the configuration (the 32-bit values in each of the clock enable + * count and toggle count registers) + */ +#define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0 +/* enum: Write a new configuration to the clock enable count and toggle count + * registers + */ +#define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG msgrequest */ #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_OFST 4 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_OFST 8 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG msgrequest */ #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 20 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_OFST 4 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_OFST 8 +/* The 32-bit value to be written to the toggle count register */ #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_OFST 12 +/* The 32-bit value to be written to the clock enable count register */ #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_OFST 16 /* MC_CMD_FC_IN_DIAG_DDR_SOAK msgrequest */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_OFST 4 +/* Sub-opcode describing the operation to be carried out */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_OFST 8 -#define MC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0 /* enum */ -#define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1 /* enum */ -#define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2 /* enum */ -#define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3 /* enum */ +/* enum: Starts DDR soak test on selected banks */ +#define MC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0 +/* enum: Read status of DDR soak test */ +#define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1 +/* enum: Stop test */ +#define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2 +/* enum: Set or clear bit that triggers fake errors. These cause subsequent + * tests to fail until the bit is cleared. + */ +#define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_START msgrequest */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_LEN 24 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_OFST 4 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_OFST 8 +/* Mask of DDR banks to be tested */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_OFST 12 +/* Pattern to use in the soak test */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_OFST 16 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ZEROS 0x0 /* enum */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONES 0x1 /* enum */ +/* Either multiple automatic tests until a STOP command is issued, or one + * single test + */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_OFST 20 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONGOING_TEST 0x0 /* enum */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SINGLE_TEST 0x1 /* enum */ /* MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT msgrequest */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_LEN 16 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_OFST 4 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_OFST 8 +/* DDR bank to read status from */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_OFST 12 #define MC_CMD_FC_DDR_BANK0 0x0 /* enum */ #define MC_CMD_FC_DDR_BANK1 0x1 /* enum */ #define MC_CMD_FC_DDR_BANK2 0x2 /* enum */ #define MC_CMD_FC_DDR_BANK3 0x3 /* enum */ #define MC_CMD_FC_DDR_AOEMEM_MAX_BANKS 0x4 /* enum */ /* MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP msgrequest */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_LEN 16 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_OFST 4 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_OFST 8 +/* Mask of DDR banks to be tested */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_OFST 12 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR msgrequest */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_LEN 20 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_OFST 4 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_OFST 8 +/* Mask of DDR banks to set/clear error flag on */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_OFST 12 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_OFST 16 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_CLEAR 0x0 /* enum */ #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SET 0x1 /* enum */ /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL msgrequest */ #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_OFST 4 +/* Sub-opcode describing the operation to be carried out */ #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_OFST 8 -#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0 /* enum */ -#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1 /* enum */ +/* enum: Set a known datapath configuration */ +#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0 +/* enum: Apply raw config to datapath control registers */ +#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE msgrequest */ #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_LEN 16 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_OFST 4 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_OFST 8 +/* Datapath configuration identifier */ #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_OFST 12 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_PASSTHROUGH 0x0 /* enum */ #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SNAKE 0x1 /* enum */ /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG msgrequest */ #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 24 /* MC_CMD_FC_IN_CMD_OFST 0 */ #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_OFST 4 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_OFST 8 +/* Value to write into control register 1 */ #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_OFST 12 +/* Value to write into control register 2 */ #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_OFST 16 +/* Value to write into control register 3 */ #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_OFST 20 /* MC_CMD_FC_OUT msgresponse */ #define MC_CMD_FC_OUT_LEN 0 /* MC_CMD_FC_OUT_NULL msgresponse */ #define MC_CMD_FC_OUT_NULL_LEN 0 /* MC_CMD_FC_OUT_READ32 msgresponse */ #define MC_CMD_FC_OUT_READ32_LENMIN 4 #define MC_CMD_FC_OUT_READ32_LENMAX 252 #define MC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num)) #define MC_CMD_FC_OUT_READ32_BUFFER_OFST 0 #define MC_CMD_FC_OUT_READ32_BUFFER_LEN 4 #define MC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1 #define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM 63 /* MC_CMD_FC_OUT_WRITE32 msgresponse */ #define MC_CMD_FC_OUT_WRITE32_LEN 0 /* MC_CMD_FC_OUT_TRC_READ msgresponse */ #define MC_CMD_FC_OUT_TRC_READ_LEN 16 #define MC_CMD_FC_OUT_TRC_READ_DATA_OFST 0 #define MC_CMD_FC_OUT_TRC_READ_DATA_LEN 4 #define MC_CMD_FC_OUT_TRC_READ_DATA_NUM 4 /* MC_CMD_FC_OUT_TRC_WRITE msgresponse */ #define MC_CMD_FC_OUT_TRC_WRITE_LEN 0 /* MC_CMD_FC_OUT_GET_VERSION msgresponse */ #define MC_CMD_FC_OUT_GET_VERSION_LEN 12 #define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_OFST 0 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8 /* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */ #define MC_CMD_FC_OUT_TRC_RX_READ_LEN 8 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_OFST 0 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_LEN 4 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_NUM 2 /* MC_CMD_FC_OUT_TRC_RX_WRITE msgresponse */ #define MC_CMD_FC_OUT_TRC_RX_WRITE_LEN 0 /* MC_CMD_FC_OUT_MAC_RECONFIGURE msgresponse */ #define MC_CMD_FC_OUT_MAC_RECONFIGURE_LEN 0 /* MC_CMD_FC_OUT_MAC_SET_LINK msgresponse */ #define MC_CMD_FC_OUT_MAC_SET_LINK_LEN 0 /* MC_CMD_FC_OUT_MAC_READ_STATUS msgresponse */ #define MC_CMD_FC_OUT_MAC_READ_STATUS_LEN 4 #define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_OFST 0 /* MC_CMD_FC_OUT_MAC_GET_RX_STATS msgresponse */ #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_RX_NSTATS))+1))>>3) #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS #define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */ #define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */ #define MC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS 0x2 /* enum */ #define MC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ #define MC_CMD_FC_MAC_RX_FRAMES_OK 0x4 /* enum */ #define MC_CMD_FC_MAC_RX_CRC_ERRORS 0x5 /* enum */ #define MC_CMD_FC_MAC_RX_VLAN_OK 0x6 /* enum */ #define MC_CMD_FC_MAC_RX_ERRORS 0x7 /* enum */ #define MC_CMD_FC_MAC_RX_UCAST_PKTS 0x8 /* enum */ #define MC_CMD_FC_MAC_RX_MULTICAST_PKTS 0x9 /* enum */ #define MC_CMD_FC_MAC_RX_BROADCAST_PKTS 0xa /* enum */ #define MC_CMD_FC_MAC_RX_STATS_DROP_EVENTS 0xb /* enum */ #define MC_CMD_FC_MAC_RX_STATS_PKTS 0xc /* enum */ #define MC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS 0xd /* enum */ #define MC_CMD_FC_MAC_RX_STATS_PKTS_64 0xe /* enum */ #define MC_CMD_FC_MAC_RX_STATS_PKTS_65_127 0xf /* enum */ #define MC_CMD_FC_MAC_RX_STATS_PKTS_128_255 0x10 /* enum */ #define MC_CMD_FC_MAC_RX_STATS_PKTS_256_511 0x11 /* enum */ #define MC_CMD_FC_MAC_RX_STATS_PKTS_512_1023 0x12 /* enum */ #define MC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518 0x13 /* enum */ #define MC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX 0x14 /* enum */ #define MC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS 0x15 /* enum */ #define MC_CMD_FC_MAC_RX_STATS_JABBERS 0x16 /* enum */ #define MC_CMD_FC_MAC_RX_STATS_FRAGMENTS 0x17 /* enum */ #define MC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES 0x18 /* enum */ -#define MC_CMD_FC_MAC_RX_NSTATS 0x19 /* enum */ +/* enum: (Last entry) */ +#define MC_CMD_FC_MAC_RX_NSTATS 0x19 /* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */ #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3) #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS #define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */ #define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */ #define MC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS 0x2 /* enum */ #define MC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ #define MC_CMD_FC_MAC_TX_FRAMES_OK 0x4 /* enum */ #define MC_CMD_FC_MAC_TX_CRC_ERRORS 0x5 /* enum */ #define MC_CMD_FC_MAC_TX_VLAN_OK 0x6 /* enum */ #define MC_CMD_FC_MAC_TX_ERRORS 0x7 /* enum */ #define MC_CMD_FC_MAC_TX_UCAST_PKTS 0x8 /* enum */ #define MC_CMD_FC_MAC_TX_MULTICAST_PKTS 0x9 /* enum */ #define MC_CMD_FC_MAC_TX_BROADCAST_PKTS 0xa /* enum */ #define MC_CMD_FC_MAC_TX_STATS_DROP_EVENTS 0xb /* enum */ #define MC_CMD_FC_MAC_TX_STATS_PKTS 0xc /* enum */ #define MC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS 0xd /* enum */ #define MC_CMD_FC_MAC_TX_STATS_PKTS_64 0xe /* enum */ #define MC_CMD_FC_MAC_TX_STATS_PKTS_65_127 0xf /* enum */ #define MC_CMD_FC_MAC_TX_STATS_PKTS_128_255 0x10 /* enum */ #define MC_CMD_FC_MAC_TX_STATS_PKTS_256_511 0x11 /* enum */ #define MC_CMD_FC_MAC_TX_STATS_PKTS_512_1023 0x12 /* enum */ #define MC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518 0x13 /* enum */ #define MC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU 0x14 /* enum */ #define MC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES 0x15 /* enum */ -#define MC_CMD_FC_MAC_TX_NSTATS 0x16 /* enum */ +/* enum: (Last entry) */ +#define MC_CMD_FC_MAC_TX_NSTATS 0x16 /* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */ #define MC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3) +/* MAC Statistics */ #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK /* MC_CMD_FC_OUT_MAC msgresponse */ #define MC_CMD_FC_OUT_MAC_LEN 0 /* MC_CMD_FC_OUT_SFP msgresponse */ #define MC_CMD_FC_OUT_SFP_LEN 0 /* MC_CMD_FC_OUT_DDR_TEST_START msgresponse */ #define MC_CMD_FC_OUT_DDR_TEST_START_LEN 0 /* MC_CMD_FC_OUT_DDR_TEST_POLL msgresponse */ #define MC_CMD_FC_OUT_DDR_TEST_POLL_LEN 8 #define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8 -#define MC_CMD_FC_OP_DDR_TEST_NONE 0x0 /* enum */ -#define MC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1 /* enum */ -#define MC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2 /* enum */ -#define MC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3 /* enum */ +/* enum: Test not yet initiated */ +#define MC_CMD_FC_OP_DDR_TEST_NONE 0x0 +/* enum: Test is in progress */ +#define MC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1 +/* enum: Timed completed */ +#define MC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2 +/* enum: Test did not complete in specified time */ +#define MC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_WIDTH 1 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_LBN 9 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1 +/* Test result from FPGA */ #define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_LBN 30 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_WIDTH 1 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_LBN 29 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_WIDTH 1 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_LBN 28 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_WIDTH 1 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_LBN 15 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_WIDTH 5 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_LBN 10 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_WIDTH 5 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_LBN 5 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_WIDTH 5 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_LBN 0 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_WIDTH 5 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_COMPLETE 0x0 /* enum */ #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_FAIL 0x1 /* enum */ #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_PASS 0x2 /* enum */ #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_FAIL 0x3 /* enum */ #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_SUCCESS 0x4 /* enum */ /* MC_CMD_FC_OUT_DDR_TEST msgresponse */ #define MC_CMD_FC_OUT_DDR_TEST_LEN 0 /* MC_CMD_FC_OUT_GET_ASSERT msgresponse */ #define MC_CMD_FC_OUT_GET_ASSERT_LEN 144 +/* Assertion status flag. */ #define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8 -#define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 /* enum */ -#define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 /* enum */ -#define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 /* enum */ +/* enum: No crash data available */ +#define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 +/* enum: New crash data available */ +#define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 +/* enum: Crash data has been sent */ +#define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8 -#define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 /* enum */ -#define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 /* enum */ -#define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 /* enum */ +/* enum: No crash has been recorded. */ +#define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 +/* enum: Crash due to exception. */ +#define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 +/* enum: Crash due to assertion. */ +#define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 +/* Failing PC value */ #define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_OFST 4 +/* Saved GP regs */ #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_OFST 8 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_LEN 4 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_NUM 31 +/* Exception Type */ #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_OFST 132 +/* Instruction at which exception occurred */ #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_OFST 136 +/* BAD Address that triggered address-based exception */ #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_OFST 140 /* MC_CMD_FC_OUT_FPGA_BUILD msgresponse */ #define MC_CMD_FC_OUT_FPGA_BUILD_LEN 32 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_OFST 0 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_LBN 31 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_LBN 30 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_LBN 16 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_WIDTH 14 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_LBN 12 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_WIDTH 4 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_LBN 4 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4 +/* Build timestamp (seconds since epoch) */ #define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_OFST 4 #define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_WIDTH 8 #define MC_CMD_FC_FPGA_TYPE_A7 0xa7 /* enum */ #define MC_CMD_FC_FPGA_TYPE_A5 0xa5 /* enum */ #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_LBN 8 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_WIDTH 10 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_LBN 18 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_LBN 19 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_LBN 20 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_LBN 21 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_LBN 22 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_LBN 23 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_LBN 24 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_LBN 25 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_LBN 26 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_LBN 27 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_LBN 28 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_LBN 29 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_WIDTH 2 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_LBN 31 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_OFST 12 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_LBN 0 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_WIDTH 16 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_LBN 16 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_WIDTH 1 #define MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 /* enum */ #define MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 /* enum */ #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_LBN 17 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_WIDTH 15 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_OFST 16 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_LBN 0 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_WIDTH 16 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_LBN 16 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_OFST 20 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_LBN 0 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_WIDTH 16 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_LBN 16 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_WIDTH 16 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16 /* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */ #define MC_CMD_FC_OUT_FPGA_SERVICES_LEN 32 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_LBN 31 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_LBN 30 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_LBN 16 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_WIDTH 14 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_LBN 12 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_WIDTH 4 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_LBN 4 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4 +/* Build timestamp (seconds since epoch) */ #define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_OFST 4 #define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_LBN 27 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_LBN 28 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_LBN 29 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_LBN 30 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_LBN 31 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_OFST 12 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_LBN 0 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_WIDTH 16 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_LBN 16 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_WIDTH 1 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_OFST 16 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_LBN 0 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_WIDTH 16 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_LBN 16 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_WIDTH 16 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_OFST 20 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_LBN 0 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_WIDTH 16 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_LBN 16 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_WIDTH 16 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_OFST 24 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_OFST 28 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16 /* MC_CMD_FC_OUT_BSP_VERSION msgresponse */ #define MC_CMD_FC_OUT_BSP_VERSION_LEN 4 +/* Qsys system ID */ #define MC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_LBN 4 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_WIDTH 8 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_LBN 0 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_WIDTH 4 /* MC_CMD_FC_OUT_READ_MAP_COUNT msgresponse */ #define MC_CMD_FC_OUT_READ_MAP_COUNT_LEN 4 +/* Number of maps */ #define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_OFST 0 /* MC_CMD_FC_OUT_READ_MAP_INDEX msgresponse */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN 164 +/* Index of the map */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_OFST 0 +/* Options for the map */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8 0x0 /* enum */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16 0x1 /* enum */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32 0x2 /* enum */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64 0x3 /* enum */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK 0x3 /* enum */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC 0x4 /* enum */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM 0x8 /* enum */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ 0x10 /* enum */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE 0x20 /* enum */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE 0x0 /* enum */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED 0x40 /* enum */ +/* Address of start of map */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12 +/* Length of address map */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20 +/* Component information field */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24 +/* License expiry data for map */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32 +/* Name of the component */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_NUM 128 /* MC_CMD_FC_OUT_READ_MAP msgresponse */ #define MC_CMD_FC_OUT_READ_MAP_LEN 0 /* MC_CMD_FC_OUT_CAPABILITIES msgresponse */ #define MC_CMD_FC_OUT_CAPABILITIES_LEN 8 +/* Number of internal ports */ #define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_OFST 0 +/* Number of external ports */ #define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_OFST 4 /* MC_CMD_FC_OUT_GLOBAL_FLAGS msgresponse */ #define MC_CMD_FC_OUT_GLOBAL_FLAGS_LEN 4 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_OFST 0 /* MC_CMD_FC_OUT_IO_REL msgresponse */ #define MC_CMD_FC_OUT_IO_REL_LEN 0 /* MC_CMD_FC_OUT_IO_REL_GET_ADDR msgresponse */ #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_LEN 8 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_OFST 0 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_OFST 4 /* MC_CMD_FC_OUT_IO_REL_READ32 msgresponse */ #define MC_CMD_FC_OUT_IO_REL_READ32_LENMIN 4 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252 #define MC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num)) #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM 63 /* MC_CMD_FC_OUT_IO_REL_WRITE32 msgresponse */ #define MC_CMD_FC_OUT_IO_REL_WRITE32_LEN 0 /* MC_CMD_FC_OUT_UHLINK_PHY msgresponse */ #define MC_CMD_FC_OUT_UHLINK_PHY_LEN 48 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_OFST 0 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_LBN 0 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16 +/* Transceiver Transmit settings */ #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16 +/* Transceiver Receive settings */ #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16 +/* Rx eye opening */ #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16 +/* PCS status word */ #define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_OFST 16 +/* Link status word */ #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1 +/* Current SFp parameters applied */ #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_OFST 24 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_LEN 20 +/* Link speed is 100, 1000, 10000 */ #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_OFST 24 +/* Length of copper cable - zero when not relevant */ #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_OFST 28 +/* True if a dual speed SFP+ module */ #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_OFST 32 +/* True if an SFP Module is present (other fields valid when true) */ #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_OFST 36 +/* The type of the SFP+ Module */ #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_OFST 40 +/* PHY config flags */ #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_LBN 1 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_WIDTH 1 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_LBN 2 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_WIDTH 1 /* MC_CMD_FC_OUT_UHLINK_MAC msgresponse */ #define MC_CMD_FC_OUT_UHLINK_MAC_LEN 20 +/* MAC configuration applied */ #define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_OFST 0 +/* MTU size */ #define MC_CMD_FC_OUT_UHLINK_MAC_MTU_OFST 4 +/* IF Mode status */ #define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_OFST 8 +/* MAC address configured */ #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16 /* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */ #define MC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3) +/* Rx Eye measurements */ #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_OFST 0 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_LEN 4 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_NUM MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK /* MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT msgresponse */ #define MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT_LEN 0 /* MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT msgresponse */ #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_LEN ((((32-1+(64*MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK))+1))>>3) +/* Has the eye plot dump completed and data returned is valid? */ #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_OFST 0 +/* Rx Eye binary plot */ #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK /* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */ #define MC_CMD_FC_OUT_UHLINK_RX_TUNE_LEN 0 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET msgresponse */ #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET_LEN 0 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET msgresponse */ #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_LEN 4 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_OFST 0 /* MC_CMD_FC_OUT_UHLINK msgresponse */ #define MC_CMD_FC_OUT_UHLINK_LEN 0 /* MC_CMD_FC_OUT_SET_LINK msgresponse */ #define MC_CMD_FC_OUT_SET_LINK_LEN 0 /* MC_CMD_FC_OUT_LICENSE msgresponse */ #define MC_CMD_FC_OUT_LICENSE_LEN 12 +/* Count of valid keys */ #define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_OFST 0 +/* Count of invalid keys */ #define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_OFST 4 +/* Count of blacklisted keys */ #define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_OFST 8 /* MC_CMD_FC_OUT_STARTUP msgresponse */ #define MC_CMD_FC_OUT_STARTUP_LEN 4 +/* Capabilities of the FPGA/FC */ #define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1 /* MC_CMD_FC_OUT_DMA_READ msgresponse */ #define MC_CMD_FC_OUT_DMA_READ_LENMIN 1 #define MC_CMD_FC_OUT_DMA_READ_LENMAX 252 #define MC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num)) +/* The data read */ #define MC_CMD_FC_OUT_DMA_READ_DATA_OFST 0 #define MC_CMD_FC_OUT_DMA_READ_DATA_LEN 1 #define MC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1 #define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM 252 /* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */ #define MC_CMD_FC_OUT_TIMED_READ_SET_LEN 4 +/* Timer handle */ #define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_OFST 0 /* MC_CMD_FC_OUT_TIMED_READ_GET msgresponse */ #define MC_CMD_FC_OUT_TIMED_READ_GET_LEN 52 +/* Host supplied handle (unique) */ #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_OFST 0 +/* Address into which to transfer data in host */ #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8 +/* AOE address from which to transfer data */ #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16 +/* Length of AOE transfer (total) */ #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20 +/* Length of host transfer (total) */ #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_OFST 24 +/* See FLAGS entry for MC_CMD_FC_IN_TIMED_READ_SET */ #define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_OFST 28 #define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_OFST 32 +/* When active, start read time */ #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40 +/* When active, end read time */ #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48 /* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */ #define MC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0 /* MC_CMD_FC_OUT_LOG msgresponse */ #define MC_CMD_FC_OUT_LOG_LEN 0 /* MC_CMD_FC_OUT_CLOCK_GET_TIME msgresponse */ #define MC_CMD_FC_OUT_CLOCK_GET_TIME_LEN 24 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_OFST 0 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_OFST 20 /* MC_CMD_FC_OUT_CLOCK_SET_TIME msgresponse */ #define MC_CMD_FC_OUT_CLOCK_SET_TIME_LEN 0 /* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */ #define MC_CMD_FC_OUT_DDR_SET_SPD_LEN 0 /* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */ #define MC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_LBN 0 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_WIDTH 1 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_LBN 1 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_WIDTH 1 /* MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT msgresponse */ #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_LEN 8 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_OFST 0 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_OFST 4 /* MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT msgresponse */ #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMIN 8 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num)) #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31 /* MC_CMD_FC_OUT_SPI_READ msgresponse */ #define MC_CMD_FC_OUT_SPI_READ_LENMIN 4 #define MC_CMD_FC_OUT_SPI_READ_LENMAX 252 #define MC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num)) #define MC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM 63 /* MC_CMD_FC_OUT_SPI_WRITE msgresponse */ #define MC_CMD_FC_OUT_SPI_WRITE_LEN 0 /* MC_CMD_FC_OUT_SPI_ERASE msgresponse */ #define MC_CMD_FC_OUT_SPI_ERASE_LEN 0 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG msgresponse */ #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_LEN 8 +/* The 32-bit value read from the toggle count register */ #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_OFST 0 +/* The 32-bit value read from the clock enable count register */ #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_OFST 4 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG msgresponse */ #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 0 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_START msgresponse */ #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_START_LEN 0 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT msgresponse */ #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_LEN 8 +/* DDR soak test status word; bits [4:0] are relevant. */ #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_LBN 1 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_WIDTH 1 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_LBN 2 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_WIDTH 1 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_LBN 3 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1 +/* DDR soak test error count */ #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_OFST 4 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP msgresponse */ #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP_LEN 0 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR msgresponse */ #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR_LEN 0 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE msgresponse */ #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE_LEN 0 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG msgresponse */ #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 0 /***********************************/ -/* MC_CMD_AOE - * AOE operations (on MC rather than FC) +/* MC_CMD_AOE + * AOE operations on MC */ -#define MC_CMD_AOE 0xa +#define MC_CMD_AOE 0xa /* MC_CMD_AOE_IN msgrequest */ #define MC_CMD_AOE_IN_LEN 4 #define MC_CMD_AOE_IN_OP_HDR_OFST 0 #define MC_CMD_AOE_IN_OP_LBN 0 #define MC_CMD_AOE_IN_OP_WIDTH 8 -#define MC_CMD_AOE_OP_INFO 0x1 /* enum */ -#define MC_CMD_AOE_OP_CURRENTS 0x2 /* enum */ -#define MC_CMD_AOE_OP_TEMPERATURES 0x3 /* enum */ -#define MC_CMD_AOE_OP_CPLD_IDLE 0x4 /* enum */ -#define MC_CMD_AOE_OP_CPLD_READ 0x5 /* enum */ -#define MC_CMD_AOE_OP_CPLD_WRITE 0x6 /* enum */ -#define MC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7 /* enum */ -#define MC_CMD_AOE_OP_CPLD_REPROGRAM 0x8 /* enum */ -#define MC_CMD_AOE_OP_POWER 0x9 /* enum */ -#define MC_CMD_AOE_OP_LOAD 0xa /* enum */ -#define MC_CMD_AOE_OP_FAN_CONTROL 0xb /* enum */ -#define MC_CMD_AOE_OP_FAN_FAILURES 0xc /* enum */ -#define MC_CMD_AOE_OP_MAC_STATS 0xd /* enum */ -#define MC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe /* enum */ -#define MC_CMD_AOE_OP_JTAG_WRITE 0xf /* enum */ -#define MC_CMD_AOE_OP_FPGA_ACCESS 0x10 /* enum */ -#define MC_CMD_AOE_OP_SET_MTU_OFFSET 0x11 /* enum */ -#define MC_CMD_AOE_OP_LINK_STATE 0x12 /* enum */ -#define MC_CMD_AOE_OP_SIENA_STATS 0x13 /* enum */ -#define MC_CMD_AOE_OP_DDR 0x14 /* enum */ -#define MC_CMD_AOE_OP_FC 0x15 /* enum */ -#define MC_CMD_AOE_OP_DDR_ECC_STATUS 0x16 /* enum */ -#define MC_CMD_AOE_OP_MC_SPI_MASTER 0x17 /* enum */ +/* enum: FPGA and CPLD information */ +#define MC_CMD_AOE_OP_INFO 0x1 +/* enum: Currents and voltages read from MCP3424s; DEBUG */ +#define MC_CMD_AOE_OP_CURRENTS 0x2 +/* enum: Temperatures at locations around the PCB; DEBUG */ +#define MC_CMD_AOE_OP_TEMPERATURES 0x3 +/* enum: Set CPLD to idle */ +#define MC_CMD_AOE_OP_CPLD_IDLE 0x4 +/* enum: Read from CPLD register */ +#define MC_CMD_AOE_OP_CPLD_READ 0x5 +/* enum: Write to CPLD register */ +#define MC_CMD_AOE_OP_CPLD_WRITE 0x6 +/* enum: Execute CPLD instruction */ +#define MC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7 +/* enum: Reprogram the CPLD on the AOE device */ +#define MC_CMD_AOE_OP_CPLD_REPROGRAM 0x8 +/* enum: AOE power control */ +#define MC_CMD_AOE_OP_POWER 0x9 +/* enum: AOE image loading */ +#define MC_CMD_AOE_OP_LOAD 0xa +/* enum: Fan monitoring */ +#define MC_CMD_AOE_OP_FAN_CONTROL 0xb +/* enum: Fan failures since last reset */ +#define MC_CMD_AOE_OP_FAN_FAILURES 0xc +/* enum: Get generic AOE MAC statistics */ +#define MC_CMD_AOE_OP_MAC_STATS 0xd +/* enum: Retrieve PHY specific information */ +#define MC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe +/* enum: Write a number of JTAG primitive commands, return will give data */ +#define MC_CMD_AOE_OP_JTAG_WRITE 0xf +/* enum: Control access to the FPGA via the Siena JTAG Chain */ +#define MC_CMD_AOE_OP_FPGA_ACCESS 0x10 +/* enum: Set the MTU offset between Siena and AOE MACs */ +#define MC_CMD_AOE_OP_SET_MTU_OFFSET 0x11 +/* enum: How link state is handled */ +#define MC_CMD_AOE_OP_LINK_STATE 0x12 +/* enum: How Siena MAC statistics are reported (deprecated - use + * MC_CMD_AOE_OP_ASIC_STATS) + */ +#define MC_CMD_AOE_OP_SIENA_STATS 0x13 +/* enum: How native ASIC MAC statistics are reported - replaces the deprecated + * command MC_CMD_AOE_OP_SIENA_STATS + */ +#define MC_CMD_AOE_OP_ASIC_STATS 0x13 +/* enum: DDR memory information */ +#define MC_CMD_AOE_OP_DDR 0x14 +/* enum: FC control */ +#define MC_CMD_AOE_OP_FC 0x15 +/* enum: DDR ECC status reads */ +#define MC_CMD_AOE_OP_DDR_ECC_STATUS 0x16 +/* enum: Commands for MC-SPI Master emulation */ +#define MC_CMD_AOE_OP_MC_SPI_MASTER 0x17 +/* enum: Commands for FC boot control */ +#define MC_CMD_AOE_OP_FC_BOOT 0x18 /* MC_CMD_AOE_OUT msgresponse */ #define MC_CMD_AOE_OUT_LEN 0 /* MC_CMD_AOE_IN_INFO msgrequest */ #define MC_CMD_AOE_IN_INFO_LEN 4 #define MC_CMD_AOE_IN_CMD_OFST 0 /* MC_CMD_AOE_IN_CURRENTS msgrequest */ #define MC_CMD_AOE_IN_CURRENTS_LEN 4 /* MC_CMD_AOE_IN_CMD_OFST 0 */ /* MC_CMD_AOE_IN_TEMPERATURES msgrequest */ #define MC_CMD_AOE_IN_TEMPERATURES_LEN 4 /* MC_CMD_AOE_IN_CMD_OFST 0 */ /* MC_CMD_AOE_IN_CPLD_IDLE msgrequest */ #define MC_CMD_AOE_IN_CPLD_IDLE_LEN 4 /* MC_CMD_AOE_IN_CMD_OFST 0 */ /* MC_CMD_AOE_IN_CPLD_READ msgrequest */ #define MC_CMD_AOE_IN_CPLD_READ_LEN 12 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_CPLD_READ_REGISTER_OFST 4 #define MC_CMD_AOE_IN_CPLD_READ_WIDTH_OFST 8 /* MC_CMD_AOE_IN_CPLD_WRITE msgrequest */ #define MC_CMD_AOE_IN_CPLD_WRITE_LEN 16 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_OFST 4 #define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_OFST 8 #define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_OFST 12 /* MC_CMD_AOE_IN_CPLD_INSTRUCTION msgrequest */ #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_LEN 8 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_OFST 4 /* MC_CMD_AOE_IN_CPLD_REPROGRAM msgrequest */ #define MC_CMD_AOE_IN_CPLD_REPROGRAM_LEN 8 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_OFST 4 -#define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1 /* enum */ -#define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3 /* enum */ -#define MC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4 /* enum */ +/* enum: Reprogram CPLD, poll for completion */ +#define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1 +/* enum: Reprogram CPLD, send event on completion */ +#define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3 +/* enum: Get status of reprogramming operation */ +#define MC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4 /* MC_CMD_AOE_IN_POWER msgrequest */ #define MC_CMD_AOE_IN_POWER_LEN 8 /* MC_CMD_AOE_IN_CMD_OFST 0 */ +/* Turn on or off AOE power */ #define MC_CMD_AOE_IN_POWER_OP_OFST 4 -#define MC_CMD_AOE_IN_POWER_OFF 0x0 /* enum */ -#define MC_CMD_AOE_IN_POWER_ON 0x1 /* enum */ -#define MC_CMD_AOE_IN_POWER_CLEAR 0x2 /* enum */ -#define MC_CMD_AOE_IN_POWER_SHOW_CURRENT 0x3 /* enum */ -#define MC_CMD_AOE_IN_POWER_SHOW_PEAK 0x4 /* enum */ -#define MC_CMD_AOE_IN_POWER_DDR_LAST 0x5 /* enum */ -#define MC_CMD_AOE_IN_POWER_DDR_PEAK 0x6 /* enum */ -#define MC_CMD_AOE_IN_POWER_DDR_CLEAR 0x7 /* enum */ +/* enum: Turn off FPGA power */ +#define MC_CMD_AOE_IN_POWER_OFF 0x0 +/* enum: Turn on FPGA power */ +#define MC_CMD_AOE_IN_POWER_ON 0x1 +/* enum: Clear peak power measurement */ +#define MC_CMD_AOE_IN_POWER_CLEAR 0x2 +/* enum: Show current power in sensors output */ +#define MC_CMD_AOE_IN_POWER_SHOW_CURRENT 0x3 +/* enum: Show peak power in sensors output */ +#define MC_CMD_AOE_IN_POWER_SHOW_PEAK 0x4 +/* enum: Show current DDR current */ +#define MC_CMD_AOE_IN_POWER_DDR_LAST 0x5 +/* enum: Show peak DDR current */ +#define MC_CMD_AOE_IN_POWER_DDR_PEAK 0x6 +/* enum: Clear peak DDR current */ +#define MC_CMD_AOE_IN_POWER_DDR_CLEAR 0x7 /* MC_CMD_AOE_IN_LOAD msgrequest */ #define MC_CMD_AOE_IN_LOAD_LEN 8 /* MC_CMD_AOE_IN_CMD_OFST 0 */ +/* Image to be loaded (0 - main or 1 - diagnostic) to load in normal sequence + */ #define MC_CMD_AOE_IN_LOAD_IMAGE_OFST 4 /* MC_CMD_AOE_IN_FAN_CONTROL msgrequest */ #define MC_CMD_AOE_IN_FAN_CONTROL_LEN 8 /* MC_CMD_AOE_IN_CMD_OFST 0 */ +/* If non zero report measured fan RPM rather than nominal */ #define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_OFST 4 /* MC_CMD_AOE_IN_FAN_FAILURES msgrequest */ #define MC_CMD_AOE_IN_FAN_FAILURES_LEN 4 /* MC_CMD_AOE_IN_CMD_OFST 0 */ /* MC_CMD_AOE_IN_MAC_STATS msgrequest */ #define MC_CMD_AOE_IN_MAC_STATS_LEN 24 /* MC_CMD_AOE_IN_CMD_OFST 0 */ +/* AOE port */ #define MC_CMD_AOE_IN_MAC_STATS_PORT_OFST 4 +/* Host memory address for statistics */ #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12 #define MC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LBN 0 #define MC_CMD_AOE_IN_MAC_STATS_DMA_WIDTH 1 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_LBN 1 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_WIDTH 1 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_LBN 2 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_WIDTH 1 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_LBN 3 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_WIDTH 1 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_LBN 4 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_WIDTH 1 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_LBN 5 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16 +/* Length of DMA data (optional) */ #define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_OFST 20 /* MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO msgrequest */ #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_LEN 12 /* MC_CMD_AOE_IN_CMD_OFST 0 */ +/* AOE port */ #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_OFST 4 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_OFST 8 /* MC_CMD_AOE_IN_JTAG_WRITE msgrequest */ #define MC_CMD_AOE_IN_JTAG_WRITE_LENMIN 12 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252 #define MC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num)) /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_OFST 8 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_LEN 4 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MINNUM 1 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM 61 /* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */ #define MC_CMD_AOE_IN_FPGA_ACCESS_LEN 8 /* MC_CMD_AOE_IN_CMD_OFST 0 */ +/* Enable or disable access */ #define MC_CMD_AOE_IN_FPGA_ACCESS_OP_OFST 4 -#define MC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1 /* enum */ -#define MC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2 /* enum */ +/* enum: Enable access */ +#define MC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1 +/* enum: Disable access */ +#define MC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2 /* MC_CMD_AOE_IN_SET_MTU_OFFSET msgrequest */ #define MC_CMD_AOE_IN_SET_MTU_OFFSET_LEN 12 /* MC_CMD_AOE_IN_CMD_OFST 0 */ +/* AOE port - when not ALL_EXTERNAL or ALL_INTERNAL specifies port number */ #define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_OFST 4 -#define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000 /* enum */ -#define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000 /* enum */ +/* enum: Apply to all external ports */ +#define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000 +/* enum: Apply to all internal ports */ +#define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000 +/* The MTU offset to be applied to the external ports */ #define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_OFST 8 /* MC_CMD_AOE_IN_LINK_STATE msgrequest */ #define MC_CMD_AOE_IN_LINK_STATE_LEN 8 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8 -#define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE 0x0 /* enum */ -#define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED 0x1 /* enum */ -#define MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2 /* enum */ -#define MC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3 /* enum */ +/* enum: AOE and associated external port */ +#define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE 0x0 +/* enum: AOE and OR of all external ports */ +#define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED 0x1 +/* enum: Individual ports */ +#define MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2 +/* enum: Configure link state mode on given AOE port */ +#define MC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8 -#define MC_CMD_AOE_IN_LINK_STATE_OP_NONE 0x0 /* enum */ -#define MC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1 /* enum */ -#define MC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2 /* enum */ +/* enum: No-op */ +#define MC_CMD_AOE_IN_LINK_STATE_OP_NONE 0x0 +/* enum: logical OR of all SFP ports link status */ +#define MC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1 +/* enum: logical AND of all SFP ports link status */ +#define MC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16 /* MC_CMD_AOE_IN_SIENA_STATS msgrequest */ #define MC_CMD_AOE_IN_SIENA_STATS_LEN 8 /* MC_CMD_AOE_IN_CMD_OFST 0 */ +/* How MAC statistics are reported */ #define MC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4 -#define MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA 0x0 /* enum */ -#define MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE 0x1 /* enum */ +/* enum: Statistics from Siena (default) */ +#define MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA 0x0 +/* enum: Statistics from AOE external ports */ +#define MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE 0x1 +/* MC_CMD_AOE_IN_ASIC_STATS msgrequest */ +#define MC_CMD_AOE_IN_ASIC_STATS_LEN 8 +/* MC_CMD_AOE_IN_CMD_OFST 0 */ +/* How MAC statistics are reported */ +#define MC_CMD_AOE_IN_ASIC_STATS_MODE_OFST 4 +/* enum: Statistics from the ASIC (default) */ +#define MC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC 0x0 +/* enum: Statistics from AOE external ports */ +#define MC_CMD_AOE_IN_ASIC_STATS_STATS_AOE 0x1 + /* MC_CMD_AOE_IN_DDR msgrequest */ #define MC_CMD_AOE_IN_DDR_LEN 12 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_DDR_BANK_OFST 4 /* Enum values, see field(s): */ -/* MC_CMD_FC_IN_DDR_BANK */ +/* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ +/* Page index of SPD data */ #define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_OFST 8 /* MC_CMD_AOE_IN_FC msgrequest */ #define MC_CMD_AOE_IN_FC_LEN 4 /* MC_CMD_AOE_IN_CMD_OFST 0 */ /* MC_CMD_AOE_IN_DDR_ECC_STATUS msgrequest */ #define MC_CMD_AOE_IN_DDR_ECC_STATUS_LEN 8 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_OFST 4 /* Enum values, see field(s): */ -/* MC_CMD_FC_IN_DDR_BANK */ +/* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ /* MC_CMD_AOE_IN_MC_SPI_MASTER msgrequest */ #define MC_CMD_AOE_IN_MC_SPI_MASTER_LEN 8 /* MC_CMD_AOE_IN_CMD_OFST 0 */ +/* Basic commands for MC SPI Master emulation. */ #define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_OFST 4 -#define MC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0 /* enum */ -#define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1 /* enum */ +/* enum: MC SPI read */ +#define MC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0 +/* enum: MC SPI write */ +#define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1 /* MC_CMD_AOE_IN_MC_SPI_MASTER_READ msgrequest */ #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_LEN 12 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_OFST 4 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_OFST 8 /* MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE msgrequest */ #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_LEN 16 /* MC_CMD_AOE_IN_CMD_OFST 0 */ #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_OFST 4 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_OFST 8 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_OFST 12 +/* MC_CMD_AOE_IN_FC_BOOT msgrequest */ +#define MC_CMD_AOE_IN_FC_BOOT_LEN 8 +/* MC_CMD_AOE_IN_CMD_OFST 0 */ +/* FC boot control flags */ +#define MC_CMD_AOE_IN_FC_BOOT_CONTROL_OFST 4 +#define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0 +#define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1 + /* MC_CMD_AOE_OUT_INFO msgresponse */ #define MC_CMD_AOE_OUT_INFO_LEN 44 +/* JTAG IDCODE of CPLD */ #define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_OFST 0 +/* Version of CPLD */ #define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_OFST 4 +/* JTAG IDCODE of FPGA */ #define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_OFST 8 +/* JTAG USERCODE of FPGA */ #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12 +/* FPGA type - read from CPLD straps */ #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16 +/* FPGA state (debug) */ #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20 +/* FPGA image - partition from which loaded */ #define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_OFST 24 +/* FC state */ #define MC_CMD_AOE_OUT_INFO_FC_STATE_OFST 28 -#define MC_CMD_AOE_OUT_INFO_WATCHDOG 0x1 /* enum */ -#define MC_CMD_AOE_OUT_INFO_COMMS 0x2 /* enum */ +/* enum: Set if watchdog working */ +#define MC_CMD_AOE_OUT_INFO_WATCHDOG 0x1 +/* enum: Set if MC-FC communications working */ +#define MC_CMD_AOE_OUT_INFO_COMMS 0x2 +/* Random pieces of information */ #define MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32 -#define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 /* enum */ -#define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 /* enum */ -#define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 /* enum */ -#define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 /* enum */ -#define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 /* enum */ -#define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 /* enum */ +/* enum: Power to FPGA supplied by PEG connector, not PCIe bus */ +#define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 +/* enum: CPLD apparently good */ +#define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 +/* enum: FPGA working normally */ +#define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 +/* enum: FPGA is powered */ +#define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 +/* enum: Board has incompatible SODIMMs fitted */ +#define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 +/* enum: Board has ByteBlaster connected */ +#define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 +/* Revision of Modena board */ #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36 #define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */ #define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */ #define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */ #define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */ +/* Result of FC booting - not valid while a ByteBlaster is connected. */ #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40 -#define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0 /* enum */ -#define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1 /* enum */ -#define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2 /* enum */ -#define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3 /* enum */ -#define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4 /* enum */ -#define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5 /* enum */ -#define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80 /* enum */ -#define MC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff /* enum */ +/* enum: No error */ +#define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0 +/* enum: Bad address set in CPLD */ +#define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1 +/* enum: Bad header */ +#define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2 +/* enum: Bad text section details */ +#define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3 +/* enum: Bad checksum */ +#define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4 +/* enum: Bad BSP */ +#define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5 +/* enum: FC application loaded and execution attempted */ +#define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80 +/* enum: FC application Started */ +#define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_STARTED 0x81 +/* enum: No bootrom in FPGA */ +#define MC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff /* MC_CMD_AOE_OUT_CURRENTS msgresponse */ #define MC_CMD_AOE_OUT_CURRENTS_LEN 68 +/* Set of currents and voltages (mA or mV as appropriate) */ #define MC_CMD_AOE_OUT_CURRENTS_VALUES_OFST 0 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_LEN 4 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_NUM 17 #define MC_CMD_AOE_OUT_CURRENTS_I_2V5 0x0 /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_I_1V8 0x1 /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_I_GXB 0x2 /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_I_PGM 0x3 /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_I_XCVR 0x4 /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_I_1V5 0x5 /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_V_3V3 0x6 /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_V_1V5 0x7 /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_I_IN 0x8 /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_I_OUT 0x9 /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_V_IN 0xa /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR1 0xb /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR1 0xc /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR2 0xd /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR2 0xe /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR3 0xf /* enum */ #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR3 0x10 /* enum */ /* MC_CMD_AOE_OUT_TEMPERATURES msgresponse */ #define MC_CMD_AOE_OUT_TEMPERATURES_LEN 40 +/* Set of temperatures */ #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_OFST 0 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_LEN 4 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_NUM 10 -#define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0 /* enum */ +/* enum: The first set of enum values are for Modena code. */ +#define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_1 0x1 /* enum */ #define MC_CMD_AOE_OUT_TEMPERATURES_IND_0 0x2 /* enum */ #define MC_CMD_AOE_OUT_TEMPERATURES_IND_1 0x3 /* enum */ #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO1 0x4 /* enum */ #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO2 0x5 /* enum */ #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO3 0x6 /* enum */ #define MC_CMD_AOE_OUT_TEMPERATURES_PSU 0x7 /* enum */ #define MC_CMD_AOE_OUT_TEMPERATURES_FPGA 0x8 /* enum */ #define MC_CMD_AOE_OUT_TEMPERATURES_SIENA 0x9 /* enum */ +/* enum: The second set of enum values are for Sorrento code. */ +#define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_0 0x0 +#define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_1 0x1 /* enum */ +#define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_0 0x2 /* enum */ +#define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_1 0x3 /* enum */ +#define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_0 0x4 /* enum */ +#define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_1 0x5 /* enum */ +#define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_FPGA 0x6 /* enum */ +#define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY0 0x7 /* enum */ +#define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY1 0x8 /* enum */ /* MC_CMD_AOE_OUT_CPLD_READ msgresponse */ #define MC_CMD_AOE_OUT_CPLD_READ_LEN 4 +/* The value read from the CPLD */ #define MC_CMD_AOE_OUT_CPLD_READ_VALUE_OFST 0 /* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */ #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252 #define MC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num)) +/* Failure counts for each fan */ #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM 63 /* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */ #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4 +/* Results of status command (only) */ #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_OFST 0 +/* MC_CMD_AOE_OUT_POWER_OFF msgresponse */ +#define MC_CMD_AOE_OUT_POWER_OFF_LEN 0 + +/* MC_CMD_AOE_OUT_POWER_ON msgresponse */ +#define MC_CMD_AOE_OUT_POWER_ON_LEN 0 + +/* MC_CMD_AOE_OUT_LOAD msgresponse */ +#define MC_CMD_AOE_OUT_LOAD_LEN 0 + /* MC_CMD_AOE_OUT_MAC_STATS_DMA msgresponse */ #define MC_CMD_AOE_OUT_MAC_STATS_DMA_LEN 0 -/* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse */ +/* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse: See MC_CMD_MAC_STATS_OUT_NO_DMA + * for details + */ #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS /* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */ #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num)) +/* in bytes */ #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_OFST 4 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MINNUM 1 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM 248 /* MC_CMD_AOE_OUT_JTAG_WRITE msgresponse */ #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252 #define MC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num)) +/* Used to align the in and out data blocks so the MC can re-use the cmd */ #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0 +/* out bytes */ #define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_OFST 4 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_OFST 8 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MINNUM 1 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM 61 /* MC_CMD_AOE_OUT_FPGA_ACCESS msgresponse */ #define MC_CMD_AOE_OUT_FPGA_ACCESS_LEN 0 /* MC_CMD_AOE_OUT_DDR msgresponse */ #define MC_CMD_AOE_OUT_DDR_LENMIN 17 #define MC_CMD_AOE_OUT_DDR_LENMAX 252 #define MC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num)) +/* Information on the module. */ #define MC_CMD_AOE_OUT_DDR_FLAGS_OFST 0 #define MC_CMD_AOE_OUT_DDR_PRESENT_LBN 0 #define MC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1 #define MC_CMD_AOE_OUT_DDR_POWERED_LBN 1 #define MC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1 +#define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_LBN 3 +#define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_WIDTH 1 +/* Memory size, in MB. */ #define MC_CMD_AOE_OUT_DDR_CAPACITY_OFST 4 +/* The memory type, as reported from SPD information */ #define MC_CMD_AOE_OUT_DDR_TYPE_OFST 8 +/* Nominal voltage of the module (as applied) */ #define MC_CMD_AOE_OUT_DDR_VOLTAGE_OFST 12 +/* SPD data read from the module */ #define MC_CMD_AOE_OUT_DDR_SPD_OFST 16 #define MC_CMD_AOE_OUT_DDR_SPD_LEN 1 #define MC_CMD_AOE_OUT_DDR_SPD_MINNUM 1 #define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236 +/* MC_CMD_AOE_OUT_SET_MTU_OFFSET msgresponse */ +#define MC_CMD_AOE_OUT_SET_MTU_OFFSET_LEN 0 + /* MC_CMD_AOE_OUT_LINK_STATE msgresponse */ #define MC_CMD_AOE_OUT_LINK_STATE_LEN 0 +/* MC_CMD_AOE_OUT_SIENA_STATS msgresponse */ +#define MC_CMD_AOE_OUT_SIENA_STATS_LEN 0 + +/* MC_CMD_AOE_OUT_ASIC_STATS msgresponse */ +#define MC_CMD_AOE_OUT_ASIC_STATS_LEN 0 + /* MC_CMD_AOE_OUT_FC msgresponse */ #define MC_CMD_AOE_OUT_FC_LEN 0 /* MC_CMD_AOE_OUT_DDR_ECC_STATUS msgresponse */ #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_LEN 8 +/* Flags describing status info on the module. */ #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1 +/* DDR ECC status on the module. */ #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_LBN 1 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_WIDTH 1 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_LBN 2 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_WIDTH 1 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_LBN 8 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_WIDTH 8 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_LBN 16 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_WIDTH 8 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_LBN 24 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_WIDTH 8 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_READ msgresponse */ #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_LEN 4 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_OFST 0 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE msgresponse */ #define MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE_LEN 0 /* MC_CMD_AOE_OUT_MC_SPI_MASTER msgresponse */ #define MC_CMD_AOE_OUT_MC_SPI_MASTER_LEN 0 +/* MC_CMD_AOE_OUT_FC_BOOT msgresponse */ +#define MC_CMD_AOE_OUT_FC_BOOT_LEN 0 + /***********************************/ -/* MC_CMD_PTP +/* MC_CMD_PTP * Perform PTP operation */ -#define MC_CMD_PTP 0xb +#define MC_CMD_PTP 0xb +#undef MC_CMD_0xb_PRIVILEGE_CTG +#define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_PTP_IN msgrequest */ #define MC_CMD_PTP_IN_LEN 1 +/* PTP operation code */ #define MC_CMD_PTP_IN_OP_OFST 0 #define MC_CMD_PTP_IN_OP_LEN 1 -#define MC_CMD_PTP_OP_ENABLE 0x1 /* enum */ -#define MC_CMD_PTP_OP_DISABLE 0x2 /* enum */ -#define MC_CMD_PTP_OP_TRANSMIT 0x3 /* enum */ -#define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 /* enum */ -#define MC_CMD_PTP_OP_STATUS 0x5 /* enum */ -#define MC_CMD_PTP_OP_ADJUST 0x6 /* enum */ -#define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 /* enum */ -#define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 /* enum */ -#define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 /* enum */ -#define MC_CMD_PTP_OP_RESET_STATS 0xa /* enum */ -#define MC_CMD_PTP_OP_DEBUG 0xb /* enum */ -#define MC_CMD_PTP_OP_FPGAREAD 0xc /* enum */ -#define MC_CMD_PTP_OP_FPGAWRITE 0xd /* enum */ -#define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe /* enum */ -#define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf /* enum */ -#define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 /* enum */ -#define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 /* enum */ -#define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 /* enum */ -#define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 /* enum */ -#define MC_CMD_PTP_OP_RST_CLK 0x14 /* enum */ -#define MC_CMD_PTP_OP_PPS_ENABLE 0x15 /* enum */ -#define MC_CMD_PTP_OP_MAX 0x16 /* enum */ +/* enum: Enable PTP packet timestamping operation. */ +#define MC_CMD_PTP_OP_ENABLE 0x1 +/* enum: Disable PTP packet timestamping operation. */ +#define MC_CMD_PTP_OP_DISABLE 0x2 +/* enum: Send a PTP packet. */ +#define MC_CMD_PTP_OP_TRANSMIT 0x3 +/* enum: Read the current NIC time. */ +#define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 +/* enum: Get the current PTP status. */ +#define MC_CMD_PTP_OP_STATUS 0x5 +/* enum: Adjust the PTP NIC's time. */ +#define MC_CMD_PTP_OP_ADJUST 0x6 +/* enum: Synchronize host and NIC time. */ +#define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 +/* enum: Basic manufacturing tests. */ +#define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 +/* enum: Packet based manufacturing tests. */ +#define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 +/* enum: Reset some of the PTP related statistics */ +#define MC_CMD_PTP_OP_RESET_STATS 0xa +/* enum: Debug operations to MC. */ +#define MC_CMD_PTP_OP_DEBUG 0xb +/* enum: Read an FPGA register */ +#define MC_CMD_PTP_OP_FPGAREAD 0xc +/* enum: Write an FPGA register */ +#define MC_CMD_PTP_OP_FPGAWRITE 0xd +/* enum: Apply an offset to the NIC clock */ +#define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe +/* enum: Change Apply an offset to the NIC clock */ +#define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf +/* enum: Set the MC packet filter VLAN tags for received PTP packets */ +#define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 +/* enum: Set the MC packet filter UUID for received PTP packets */ +#define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 +/* enum: Set the MC packet filter Domain for received PTP packets */ +#define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 +/* enum: Set the clock source */ +#define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 +/* enum: Reset value of Timer Reg. */ +#define MC_CMD_PTP_OP_RST_CLK 0x14 +/* enum: Enable the forwarding of PPS events to the host */ +#define MC_CMD_PTP_OP_PPS_ENABLE 0x15 +/* enum: Get the time format used by this NIC for PTP operations */ +#define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16 +/* enum: Get the clock attributes. NOTE- extended version of + * MC_CMD_PTP_OP_GET_TIME_FORMAT + */ +#define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16 +/* enum: Get corrections that should be applied to the various different + * timestamps + */ +#define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17 +/* enum: Subscribe to receive periodic time events indicating the current NIC + * time + */ +#define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18 +/* enum: Unsubscribe to stop receiving time events */ +#define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19 +/* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS + * input on the same NIC. + */ +#define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a +/* enum: Set the PTP sync status. Status is used by firmware to report to event + * subscribers. + */ +#define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b +/* enum: Above this for future use. */ +#define MC_CMD_PTP_OP_MAX 0x1c /* MC_CMD_PTP_IN_ENABLE msgrequest */ #define MC_CMD_PTP_IN_ENABLE_LEN 16 #define MC_CMD_PTP_IN_CMD_OFST 0 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 +/* Event queue for PTP events */ #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 +/* PTP timestamping mode */ #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 -#define MC_CMD_PTP_MODE_V1 0x0 /* enum */ -#define MC_CMD_PTP_MODE_V1_VLAN 0x1 /* enum */ -#define MC_CMD_PTP_MODE_V2 0x2 /* enum */ -#define MC_CMD_PTP_MODE_V2_VLAN 0x3 /* enum */ -#define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 /* enum */ +/* enum: PTP, version 1 */ +#define MC_CMD_PTP_MODE_V1 0x0 +/* enum: PTP, version 1, with VLAN headers - deprecated */ +#define MC_CMD_PTP_MODE_V1_VLAN 0x1 +/* enum: PTP, version 2 */ +#define MC_CMD_PTP_MODE_V2 0x2 +/* enum: PTP, version 2, with VLAN headers - deprecated */ +#define MC_CMD_PTP_MODE_V2_VLAN 0x3 +/* enum: PTP, version 2, with improved UUID filtering */ +#define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 +/* enum: FCoE (seconds and microseconds) */ +#define MC_CMD_PTP_MODE_FCOE 0x5 /* MC_CMD_PTP_IN_DISABLE msgrequest */ #define MC_CMD_PTP_IN_DISABLE_LEN 8 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ /* MC_CMD_PTP_IN_TRANSMIT msgrequest */ #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ +/* Transmit packet length */ #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 +/* Transmit packet data */ #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ /* MC_CMD_PTP_IN_STATUS msgrequest */ #define MC_CMD_PTP_IN_STATUS_LEN 8 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ /* MC_CMD_PTP_IN_ADJUST msgrequest */ #define MC_CMD_PTP_IN_ADJUST_LEN 24 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ +/* Frequency adjustment 40 bit fixed point ns */ #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 -#define MC_CMD_PTP_IN_ADJUST_BITS 0x28 /* enum */ +/* enum: Number of fractional bits in frequency adjustment */ +#define MC_CMD_PTP_IN_ADJUST_BITS 0x28 +/* Time adjustment in seconds */ #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 +/* Time adjustment major value */ +#define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16 +/* Time adjustment in nanoseconds */ #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 +/* Time adjustment minor value */ +#define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ +/* Number of time readings to capture */ #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 +/* Host address in which to write "synchronization started" indication (64 + * bits) + */ #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ +/* Enable or disable packet testing */ #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 /* MC_CMD_PTP_IN_RESET_STATS msgrequest */ #define MC_CMD_PTP_IN_RESET_STATS_LEN 8 /* MC_CMD_PTP_IN_CMD_OFST 0 */ +/* Reset PTP statistics */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ /* MC_CMD_PTP_IN_DEBUG msgrequest */ #define MC_CMD_PTP_IN_DEBUG_LEN 12 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ +/* Debug operations */ #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 /* MC_CMD_PTP_IN_FPGAREAD msgrequest */ #define MC_CMD_PTP_IN_FPGAREAD_LEN 16 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ #define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12 /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */ #define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13 #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252 #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num)) /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */ #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ +/* Time adjustment in seconds */ #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8 +/* Time adjustment major value */ +#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8 +/* Time adjustment in nanoseconds */ #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12 +/* Time adjustment minor value */ +#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12 /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */ #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ +/* Frequency adjustment 40 bit fixed point ns */ #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12 +/* enum: Number of fractional bits in frequency adjustment */ /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */ /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */ #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ +/* Number of VLAN tags, 0 if not VLAN */ #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8 +/* Set of VLAN tags to filter against */ #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3 /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */ #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ +/* 1 to enable UUID filtering, 0 to disable */ #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8 +/* UUID to filter against */ #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16 /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */ #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ +/* 1 to enable Domain filtering, 0 to disable */ #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8 +/* Domain number to filter against */ #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12 +/* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */ +#define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12 +/* MC_CMD_PTP_IN_CMD_OFST 0 */ +/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ +/* Set the clock source. */ +#define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8 +/* enum: Internal. */ +#define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0 +/* enum: External. */ +#define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1 + +/* MC_CMD_PTP_IN_RST_CLK msgrequest */ +#define MC_CMD_PTP_IN_RST_CLK_LEN 8 +/* MC_CMD_PTP_IN_CMD_OFST 0 */ +/* Reset value of Timer Reg. */ +/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ + /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */ #define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12 /* MC_CMD_PTP_IN_CMD_OFST 0 */ +/* Enable or disable */ #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4 -#define MC_CMD_PTP_ENABLE_PPS 0x0 /* enum */ -#define MC_CMD_PTP_DISABLE_PPS 0x1 /* enum */ +/* enum: Enable */ +#define MC_CMD_PTP_ENABLE_PPS 0x0 +/* enum: Disable */ +#define MC_CMD_PTP_DISABLE_PPS 0x1 +/* Queue id to send events back */ #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8 +/* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */ +#define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8 +/* MC_CMD_PTP_IN_CMD_OFST 0 */ +/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ + +/* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */ +#define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8 +/* MC_CMD_PTP_IN_CMD_OFST 0 */ +/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ + +/* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */ +#define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8 +/* MC_CMD_PTP_IN_CMD_OFST 0 */ +/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ + +/* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */ +#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12 +/* MC_CMD_PTP_IN_CMD_OFST 0 */ +/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ +/* Original field containing queue ID. Now extended to include flags. */ +#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8 +#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0 +#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16 +#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31 +#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1 + +/* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */ +#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16 +/* MC_CMD_PTP_IN_CMD_OFST 0 */ +/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ +/* Unsubscribe options */ +#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8 +/* enum: Unsubscribe a single queue */ +#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0 +/* enum: Unsubscribe all queues */ +#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1 +/* Event queue ID */ +#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12 + +/* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */ +#define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12 +/* MC_CMD_PTP_IN_CMD_OFST 0 */ +/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ +/* 1 to enable PPS test mode, 0 to disable and return result. */ +#define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8 + +/* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */ +#define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24 +/* MC_CMD_PTP_IN_CMD_OFST 0 */ +/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ +/* NIC - Host System Clock Synchronization status */ +#define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8 +/* enum: Host System clock and NIC clock are not in sync */ +#define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0 +/* enum: Host System clock and NIC clock are synchronized */ +#define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1 +/* If synchronized, number of seconds until clocks should be considered to be + * no longer in sync. + */ +#define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12 +#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16 +#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20 + /* MC_CMD_PTP_OUT msgresponse */ #define MC_CMD_PTP_OUT_LEN 0 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 +/* Value of seconds timestamp */ #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 +/* Timestamp major value */ +#define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0 +/* Value of nanoseconds timestamp */ #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 +/* Timestamp minor value */ +#define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4 +/* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */ +#define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0 + +/* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */ +#define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0 + /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 +/* Value of seconds timestamp */ #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 +/* Timestamp major value */ +#define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0 +/* Value of nanoseconds timestamp */ #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 +/* Timestamp minor value */ +#define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4 /* MC_CMD_PTP_OUT_STATUS msgresponse */ #define MC_CMD_PTP_OUT_STATUS_LEN 64 +/* Frequency of NIC's hardware clock */ #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 +/* Number of packets transmitted and timestamped */ #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 +/* Number of packets received and timestamped */ #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 +/* Number of packets timestamped by the FPGA */ #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 +/* Number of packets filter matched */ #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 +/* Number of packets not filter matched */ #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 +/* Number of PPS overflows (noise on input?) */ #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 +/* Number of PPS bad periods */ #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 +/* Minimum period of PPS pulse in nanoseconds */ #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 +/* Maximum period of PPS pulse in nanoseconds */ #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 +/* Last period of PPS pulse in nanoseconds */ #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 +/* Mean period of PPS pulse in nanoseconds */ #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 +/* Minimum offset of PPS pulse in nanoseconds (signed) */ #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 +/* Maximum offset of PPS pulse in nanoseconds (signed) */ #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 +/* Last offset of PPS pulse in nanoseconds (signed) */ #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 +/* Mean offset of PPS pulse in nanoseconds (signed) */ #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) +/* A set of host and NIC times */ #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 +/* Host time immediately before NIC's hardware clock read */ #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 +/* Value of seconds timestamp */ #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 +/* Timestamp major value */ +#define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4 +/* Value of nanoseconds timestamp */ #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 +/* Timestamp minor value */ +#define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8 +/* Host time immediately after NIC's hardware clock read */ #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 +/* Number of nanoseconds waited after reading NIC's hardware clock */ #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 +/* Results of testing */ #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 -#define MC_CMD_PTP_MANF_SUCCESS 0x0 /* enum */ -#define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 /* enum */ -#define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 /* enum */ -#define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 /* enum */ -#define MC_CMD_PTP_MANF_OSCILLATOR 0x4 /* enum */ -#define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 /* enum */ -#define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 /* enum */ -#define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 /* enum */ -#define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 /* enum */ -#define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 /* enum */ +/* enum: Successful test */ +#define MC_CMD_PTP_MANF_SUCCESS 0x0 +/* enum: FPGA load failed */ +#define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 +/* enum: FPGA version invalid */ +#define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 +/* enum: FPGA registers incorrect */ +#define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 +/* enum: Oscillator possibly not working? */ +#define MC_CMD_PTP_MANF_OSCILLATOR 0x4 +/* enum: Timestamps not increasing */ +#define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 +/* enum: Mismatched packet count */ +#define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 +/* enum: Mismatched packet count (Siena filter and FPGA) */ +#define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 +/* enum: Not enough packets to perform timestamp check */ +#define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 +/* enum: Timestamp trigger GPIO not working */ +#define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 +/* enum: Insufficient PPS events to perform checks */ +#define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa +/* enum: PPS time event period not sufficiently close to 1s. */ +#define MC_CMD_PTP_MANF_PPS_PERIOD 0xb +/* enum: PPS time event nS reading not sufficiently close to zero. */ +#define MC_CMD_PTP_MANF_PPS_NS 0xc +/* enum: PTP peripheral registers incorrect */ +#define MC_CMD_PTP_MANF_REGISTERS 0xd +/* enum: Failed to read time from PTP peripheral */ +#define MC_CMD_PTP_MANF_CLOCK_READ 0xe +/* Presence of external oscillator */ #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 +/* Results of testing */ #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 +/* Number of packets received by FPGA */ #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 +/* Number of packets received by Siena filters */ #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */ #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1 #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num)) #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252 +/* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */ +#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4 +/* Time format required/used by for this NIC. Applies to all PTP MCDI + * operations that pass times between the host and firmware. If this operation + * is not supported (older firmware) a format of seconds and nanoseconds should + * be assumed. + */ +#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0 +/* enum: Times are in seconds and nanoseconds */ +#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0 +/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ +#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1 +/* enum: Major register has units of seconds, minor 2^-27s per tick */ +#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2 +/* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */ +#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24 +/* Time format required/used by for this NIC. Applies to all PTP MCDI + * operations that pass times between the host and firmware. If this operation + * is not supported (older firmware) a format of seconds and nanoseconds should + * be assumed. + */ +#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0 +/* enum: Times are in seconds and nanoseconds */ +#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0 +/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ +#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1 +/* enum: Major register has units of seconds, minor 2^-27s per tick */ +#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2 +/* Minimum acceptable value for a corrected synchronization timeset. When + * comparing host and NIC clock times, the MC returns a set of samples that + * contain the host start and end time, the MC time when the host start was + * detected and the time the MC waited between reading the time and detecting + * the host end. The corrected sync window is the difference between the host + * end and start times minus the time that the MC waited for host end. + */ +#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4 +/* Various PTP capabilities */ +#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8 +#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0 +#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1 +#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12 +#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16 +#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20 + +/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16 +/* Uncorrected error on transmit timestamps in NIC clock format */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0 +/* Uncorrected error on receive timestamps in NIC clock format */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4 +/* Uncorrected error on PPS output in NIC clock format */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8 +/* Uncorrected error on PPS input in NIC clock format */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12 + +/* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */ +#define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4 +/* Results of testing */ +#define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0 +/* Enum values, see field(s): */ +/* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */ + +/* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */ +#define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0 + + /***********************************/ -/* MC_CMD_CSR_READ32 +/* MC_CMD_CSR_READ32 * Read 32bit words from the indirect memory map. */ -#define MC_CMD_CSR_READ32 0xc +#define MC_CMD_CSR_READ32 0xc +#undef MC_CMD_0xc_PRIVILEGE_CTG +#define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_CSR_READ32_IN msgrequest */ #define MC_CMD_CSR_READ32_IN_LEN 12 +/* Address */ #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 /* MC_CMD_CSR_READ32_OUT msgresponse */ #define MC_CMD_CSR_READ32_OUT_LENMIN 4 #define MC_CMD_CSR_READ32_OUT_LENMAX 252 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) +/* The last dword is the status, not a value read */ #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 /***********************************/ -/* MC_CMD_CSR_WRITE32 +/* MC_CMD_CSR_WRITE32 * Write 32bit dwords to the indirect memory map. */ -#define MC_CMD_CSR_WRITE32 0xd +#define MC_CMD_CSR_WRITE32 0xd +#undef MC_CMD_0xd_PRIVILEGE_CTG +#define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_CSR_WRITE32_IN msgrequest */ #define MC_CMD_CSR_WRITE32_IN_LENMIN 12 #define MC_CMD_CSR_WRITE32_IN_LENMAX 252 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) +/* Address */ #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 /* MC_CMD_CSR_WRITE32_OUT msgresponse */ #define MC_CMD_CSR_WRITE32_OUT_LEN 4 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 /***********************************/ -/* MC_CMD_HP - * HP specific commands. +/* MC_CMD_HP + * These commands are used for HP related features. They are grouped under one + * MCDI command to avoid creating too many MCDI commands. */ -#define MC_CMD_HP 0x54 +#define MC_CMD_HP 0x54 +#undef MC_CMD_0x54_PRIVILEGE_CTG +#define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_HP_IN msgrequest */ #define MC_CMD_HP_IN_LEN 16 +/* HP OCSD sub-command. When address is not NULL, request activation of OCSD at + * the specified address with the specified interval.When address is NULL, + * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current + * state / 2: (debug) Show temperature reported by one of the supported + * sensors. + */ #define MC_CMD_HP_IN_SUBCMD_OFST 0 -#define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 /* enum */ -#define MC_CMD_HP_IN_LAST_SUBCMD 0x0 /* enum */ +/* enum: OCSD (Option Card Sensor Data) sub-command. */ +#define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 +/* enum: Last known valid HP sub-command. */ +#define MC_CMD_HP_IN_LAST_SUBCMD 0x0 +/* The address to the array of sensor fields. (Or NULL to use a sub-command.) + */ #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 +/* The requested update interval, in seconds. (Or the sub-command if ADDR is + * NULL.) + */ #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 /* MC_CMD_HP_OUT msgresponse */ #define MC_CMD_HP_OUT_LEN 4 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 -#define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 /* enum */ -#define MC_CMD_HP_OUT_OCSD_STARTED 0x2 /* enum */ -#define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 /* enum */ +/* enum: OCSD stopped for this card. */ +#define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 +/* enum: OCSD was successfully started with the address provided. */ +#define MC_CMD_HP_OUT_OCSD_STARTED 0x2 +/* enum: OCSD was already started for this card. */ +#define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 /***********************************/ -/* MC_CMD_STACKINFO +/* MC_CMD_STACKINFO * Get stack information. */ -#define MC_CMD_STACKINFO 0xf +#define MC_CMD_STACKINFO 0xf +#undef MC_CMD_0xf_PRIVILEGE_CTG +#define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_STACKINFO_IN msgrequest */ #define MC_CMD_STACKINFO_IN_LEN 0 /* MC_CMD_STACKINFO_OUT msgresponse */ #define MC_CMD_STACKINFO_OUT_LENMIN 12 #define MC_CMD_STACKINFO_OUT_LENMAX 252 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) +/* (thread ptr, stack size, free space) for each thread in system */ #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 /***********************************/ -/* MC_CMD_MDIO_READ +/* MC_CMD_MDIO_READ * MDIO register read. */ -#define MC_CMD_MDIO_READ 0x10 +#define MC_CMD_MDIO_READ 0x10 +#undef MC_CMD_0x10_PRIVILEGE_CTG +#define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_MDIO_READ_IN msgrequest */ #define MC_CMD_MDIO_READ_IN_LEN 16 +/* Bus number; there are two MDIO buses: one for the internal PHY, and one for + * external devices. + */ #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 -#define MC_CMD_MDIO_BUS_INTERNAL 0x0 /* enum */ -#define MC_CMD_MDIO_BUS_EXTERNAL 0x1 /* enum */ +/* enum: Internal. */ +#define MC_CMD_MDIO_BUS_INTERNAL 0x0 +/* enum: External. */ +#define MC_CMD_MDIO_BUS_EXTERNAL 0x1 +/* Port address */ #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 +/* Device Address or clause 22. */ #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 -#define MC_CMD_MDIO_CLAUSE22 0x20 /* enum */ +/* enum: By default all the MCDI MDIO operations perform clause45 mode. If you + * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. + */ +#define MC_CMD_MDIO_CLAUSE22 0x20 +/* Address */ #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 /* MC_CMD_MDIO_READ_OUT msgresponse */ #define MC_CMD_MDIO_READ_OUT_LEN 8 +/* Value */ #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 +/* Status the MDIO commands return the raw status bits from the MDIO block. A + * "good" transaction should have the DONE bit set and all other bits clear. + */ #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 -#define MC_CMD_MDIO_STATUS_GOOD 0x8 /* enum */ +/* enum: Good. */ +#define MC_CMD_MDIO_STATUS_GOOD 0x8 /***********************************/ -/* MC_CMD_MDIO_WRITE +/* MC_CMD_MDIO_WRITE * MDIO register write. */ -#define MC_CMD_MDIO_WRITE 0x11 +#define MC_CMD_MDIO_WRITE 0x11 +#undef MC_CMD_0x11_PRIVILEGE_CTG +#define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_MDIO_WRITE_IN msgrequest */ #define MC_CMD_MDIO_WRITE_IN_LEN 20 +/* Bus number; there are two MDIO buses: one for the internal PHY, and one for + * external devices. + */ #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 +/* enum: Internal. */ /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ +/* enum: External. */ /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ +/* Port address */ #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 +/* Device Address or clause 22. */ #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 +/* enum: By default all the MCDI MDIO operations perform clause45 mode. If you + * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. + */ /* MC_CMD_MDIO_CLAUSE22 0x20 */ +/* Address */ #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 +/* Value */ #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 /* MC_CMD_MDIO_WRITE_OUT msgresponse */ #define MC_CMD_MDIO_WRITE_OUT_LEN 4 +/* Status; the MDIO commands return the raw status bits from the MDIO block. A + * "good" transaction should have the DONE bit set and all other bits clear. + */ #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 +/* enum: Good. */ /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ /***********************************/ -/* MC_CMD_DBI_WRITE +/* MC_CMD_DBI_WRITE * Write DBI register(s). */ -#define MC_CMD_DBI_WRITE 0x12 +#define MC_CMD_DBI_WRITE 0x12 +#undef MC_CMD_0x12_PRIVILEGE_CTG +#define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_DBI_WRITE_IN msgrequest */ #define MC_CMD_DBI_WRITE_IN_LENMIN 12 #define MC_CMD_DBI_WRITE_IN_LENMAX 252 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) +/* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset + * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF. + */ #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 /* MC_CMD_DBI_WRITE_OUT msgresponse */ #define MC_CMD_DBI_WRITE_OUT_LEN 0 /* MC_CMD_DBIWROP_TYPEDEF structuredef */ #define MC_CMD_DBIWROP_TYPEDEF_LEN 12 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 -#define MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST 4 -#define MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_LBN 32 -#define MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_WIDTH 32 +#define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4 +#define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16 +#define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16 +#define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15 +#define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1 +#define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14 +#define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1 +#define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32 +#define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 /***********************************/ -/* MC_CMD_PORT_READ32 - * Read a 32-bit register from the indirect port register map. +/* MC_CMD_PORT_READ32 + * Read a 32-bit register from the indirect port register map. The port to + * access is implied by the Shared memory channel used. */ -#define MC_CMD_PORT_READ32 0x14 +#define MC_CMD_PORT_READ32 0x14 /* MC_CMD_PORT_READ32_IN msgrequest */ #define MC_CMD_PORT_READ32_IN_LEN 4 +/* Address */ #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 /* MC_CMD_PORT_READ32_OUT msgresponse */ #define MC_CMD_PORT_READ32_OUT_LEN 8 +/* Value */ #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 +/* Status */ #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 /***********************************/ -/* MC_CMD_PORT_WRITE32 - * Write a 32-bit register to the indirect port register map. +/* MC_CMD_PORT_WRITE32 + * Write a 32-bit register to the indirect port register map. The port to + * access is implied by the Shared memory channel used. */ -#define MC_CMD_PORT_WRITE32 0x15 +#define MC_CMD_PORT_WRITE32 0x15 /* MC_CMD_PORT_WRITE32_IN msgrequest */ #define MC_CMD_PORT_WRITE32_IN_LEN 8 +/* Address */ #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 +/* Value */ #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 /* MC_CMD_PORT_WRITE32_OUT msgresponse */ #define MC_CMD_PORT_WRITE32_OUT_LEN 4 +/* Status */ #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 /***********************************/ -/* MC_CMD_PORT_READ128 - * Read a 128-bit register from the indirect port register map. +/* MC_CMD_PORT_READ128 + * Read a 128-bit register from the indirect port register map. The port to + * access is implied by the Shared memory channel used. */ -#define MC_CMD_PORT_READ128 0x16 +#define MC_CMD_PORT_READ128 0x16 /* MC_CMD_PORT_READ128_IN msgrequest */ #define MC_CMD_PORT_READ128_IN_LEN 4 +/* Address */ #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 /* MC_CMD_PORT_READ128_OUT msgresponse */ #define MC_CMD_PORT_READ128_OUT_LEN 20 +/* Value */ #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 +/* Status */ #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 /***********************************/ -/* MC_CMD_PORT_WRITE128 - * Write a 128-bit register to the indirect port register map. +/* MC_CMD_PORT_WRITE128 + * Write a 128-bit register to the indirect port register map. The port to + * access is implied by the Shared memory channel used. */ -#define MC_CMD_PORT_WRITE128 0x17 +#define MC_CMD_PORT_WRITE128 0x17 /* MC_CMD_PORT_WRITE128_IN msgrequest */ #define MC_CMD_PORT_WRITE128_IN_LEN 20 +/* Address */ #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 +/* Value */ #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 /* MC_CMD_PORT_WRITE128_OUT msgresponse */ #define MC_CMD_PORT_WRITE128_OUT_LEN 4 +/* Status */ #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 +/* MC_CMD_CAPABILITIES structuredef */ +#define MC_CMD_CAPABILITIES_LEN 4 +/* Small buf table. */ +#define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0 +#define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1 +/* Turbo mode (for Maranello). */ +#define MC_CMD_CAPABILITIES_TURBO_LBN 1 +#define MC_CMD_CAPABILITIES_TURBO_WIDTH 1 +/* Turbo mode active (for Maranello). */ +#define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2 +#define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1 +/* PTP offload. */ +#define MC_CMD_CAPABILITIES_PTP_LBN 3 +#define MC_CMD_CAPABILITIES_PTP_WIDTH 1 +/* AOE mode. */ +#define MC_CMD_CAPABILITIES_AOE_LBN 4 +#define MC_CMD_CAPABILITIES_AOE_WIDTH 1 +/* AOE mode active. */ +#define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5 +#define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1 +/* AOE mode active. */ +#define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6 +#define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1 +#define MC_CMD_CAPABILITIES_RESERVED_LBN 7 +#define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25 + /***********************************/ -/* MC_CMD_GET_BOARD_CFG +/* MC_CMD_GET_BOARD_CFG * Returns the MC firmware configuration structure. */ -#define MC_CMD_GET_BOARD_CFG 0x18 +#define MC_CMD_GET_BOARD_CFG 0x18 +#undef MC_CMD_0x18_PRIVILEGE_CTG +#define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_GET_BOARD_CFG_IN msgrequest */ #define MC_CMD_GET_BOARD_CFG_IN_LEN 0 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 +/* See MC_CMD_CAPABILITIES */ #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 -#define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0x0 /* enum */ -#define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 0x1 /* enum */ -#define MC_CMD_CAPABILITIES_TURBO_LBN 0x1 /* enum */ -#define MC_CMD_CAPABILITIES_TURBO_WIDTH 0x1 /* enum */ -#define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 0x2 /* enum */ -#define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 0x1 /* enum */ -#define MC_CMD_CAPABILITIES_PTP_LBN 0x3 /* enum */ -#define MC_CMD_CAPABILITIES_PTP_WIDTH 0x1 /* enum */ -#define MC_CMD_CAPABILITIES_AOE_LBN 0x4 /* enum */ -#define MC_CMD_CAPABILITIES_AOE_WIDTH 0x1 /* enum */ -#define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 0x5 /* enum */ -#define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 0x1 /* enum */ -#define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 0x6 /* enum */ -#define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 0x1 /* enum */ +/* See MC_CMD_CAPABILITIES */ #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 -/* Enum values, see field(s): */ -/* CAPABILITIES_PORT0 */ #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 +/* This field contains a 16-bit value for each of the types of NVRAM area. The + * values are defined in the firmware/mc/platform/.c file for a specific board + * type, but otherwise have no meaning to the MC; they are used by the driver + * to manage selection of appropriate firmware updates. + */ #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 /***********************************/ -/* MC_CMD_DBI_READX - * Read DBI register(s). +/* MC_CMD_DBI_READX + * Read DBI register(s) -- extended functionality */ -#define MC_CMD_DBI_READX 0x19 +#define MC_CMD_DBI_READX 0x19 +#undef MC_CMD_0x19_PRIVILEGE_CTG +#define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_DBI_READX_IN msgrequest */ #define MC_CMD_DBI_READX_IN_LENMIN 8 #define MC_CMD_DBI_READX_IN_LENMAX 248 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) +/* Each Read op consists of an address (offset 0), VF/CS2) */ #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 /* MC_CMD_DBI_READX_OUT msgresponse */ #define MC_CMD_DBI_READX_OUT_LENMIN 4 #define MC_CMD_DBI_READX_OUT_LENMAX 252 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) +/* Value */ #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 +/* MC_CMD_DBIRDOP_TYPEDEF structuredef */ +#define MC_CMD_DBIRDOP_TYPEDEF_LEN 8 +#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0 +#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0 +#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32 +#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4 +#define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16 +#define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16 +#define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15 +#define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1 +#define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14 +#define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1 +#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32 +#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32 + /***********************************/ -/* MC_CMD_SET_RAND_SEED +/* MC_CMD_SET_RAND_SEED * Set the 16byte seed for the MC pseudo-random generator. */ -#define MC_CMD_SET_RAND_SEED 0x1a +#define MC_CMD_SET_RAND_SEED 0x1a +#undef MC_CMD_0x1a_PRIVILEGE_CTG +#define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_SET_RAND_SEED_IN msgrequest */ #define MC_CMD_SET_RAND_SEED_IN_LEN 16 +/* Seed value. */ #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 /***********************************/ -/* MC_CMD_LTSSM_HIST - * Retrieve the history of the PCIE LTSSM. +/* MC_CMD_LTSSM_HIST + * Retrieve the history of the LTSSM, if the build supports it. */ -#define MC_CMD_LTSSM_HIST 0x1b +#define MC_CMD_LTSSM_HIST 0x1b /* MC_CMD_LTSSM_HIST_IN msgrequest */ #define MC_CMD_LTSSM_HIST_IN_LEN 0 /* MC_CMD_LTSSM_HIST_OUT msgresponse */ #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) +/* variable number of LTSSM values, as bytes. The history is read-to-clear. */ #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 /***********************************/ -/* MC_CMD_DRV_ATTACH - * Inform MCPU that this port is managed on the host. +/* MC_CMD_DRV_ATTACH + * Inform MCPU that this port is managed on the host (i.e. driver active). For + * Huntington, also request the preferred datapath firmware to use if possible + * (it may not be possible for this request to be fulfilled; the driver must + * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which + * features are actually available). The FIRMWARE_ID field is ignored by older + * platforms. */ -#define MC_CMD_DRV_ATTACH 0x1c +#define MC_CMD_DRV_ATTACH 0x1c +#undef MC_CMD_0x1c_PRIVILEGE_CTG +#define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_DRV_ATTACH_IN msgrequest */ -#define MC_CMD_DRV_ATTACH_IN_LEN 8 +#define MC_CMD_DRV_ATTACH_IN_LEN 12 +/* new state (0=detached, 1=attached) to set if UPDATE=1 */ #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 +/* 1 to set new state, or 0 to just report the existing state */ #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 +/* preferred datapath firmware (for Huntington; ignored for Siena) */ +#define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8 +/* enum: Prefer to use full featured firmware */ +#define MC_CMD_FW_FULL_FEATURED 0x0 +/* enum: Prefer to use firmware with fewer features but lower latency */ +#define MC_CMD_FW_LOW_LATENCY 0x1 +/* enum: Prefer to use firmware for SolarCapture packed stream mode */ +#define MC_CMD_FW_PACKED_STREAM 0x2 +/* enum: Prefer to use firmware with fewer features and simpler TX event + * batching but higher TX packet rate + */ +#define MC_CMD_FW_HIGH_TX_RATE 0x3 +/* enum: Reserved value */ +#define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 +/* enum: Only this option is allowed for non-admin functions */ +#define MC_CMD_FW_DONT_CARE 0xffffffff /* MC_CMD_DRV_ATTACH_OUT msgresponse */ #define MC_CMD_DRV_ATTACH_OUT_LEN 4 +/* previous or existing state (0=detached, 1=attached) */ #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 +/* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */ +#define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8 +/* previous or existing state (0=detached, 1=attached) */ +#define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0 +/* Flags associated with this function */ +#define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 +/* enum: Labels the lowest-numbered function visible to the OS */ +#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0 +/* enum: The function can control the link state of the physical port it is + * bound to. + */ +#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1 +/* enum: The function can perform privileged operations */ +#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2 + /***********************************/ -/* MC_CMD_SHMUART +/* MC_CMD_SHMUART * Route UART output to circular buffer in shared memory instead. */ -#define MC_CMD_SHMUART 0x1f +#define MC_CMD_SHMUART 0x1f /* MC_CMD_SHMUART_IN msgrequest */ #define MC_CMD_SHMUART_IN_LEN 4 +/* ??? */ #define MC_CMD_SHMUART_IN_FLAG_OFST 0 /* MC_CMD_SHMUART_OUT msgresponse */ #define MC_CMD_SHMUART_OUT_LEN 0 /***********************************/ -/* MC_CMD_PORT_RESET - * Generic per-port reset. +/* MC_CMD_PORT_RESET + * Generic per-port reset. There is no equivalent for per-board reset. Locks + * required: None; Return code: 0, ETIME. NOTE: This command is deprecated - + * use MC_CMD_ENTITY_RESET instead. */ -#define MC_CMD_PORT_RESET 0x20 +#define MC_CMD_PORT_RESET 0x20 +#undef MC_CMD_0x20_PRIVILEGE_CTG +#define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_PORT_RESET_IN msgrequest */ #define MC_CMD_PORT_RESET_IN_LEN 0 /* MC_CMD_PORT_RESET_OUT msgresponse */ #define MC_CMD_PORT_RESET_OUT_LEN 0 /***********************************/ -/* MC_CMD_PCIE_CREDITS +/* MC_CMD_ENTITY_RESET + * Generic per-resource reset. There is no equivalent for per-board reset. + * Locks required: None; Return code: 0, ETIME. NOTE: This command is an + * extended version of the deprecated MC_CMD_PORT_RESET with added fields. + */ +#define MC_CMD_ENTITY_RESET 0x20 +/* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */ + +/* MC_CMD_ENTITY_RESET_IN msgrequest */ +#define MC_CMD_ENTITY_RESET_IN_LEN 4 +/* Optional flags field. Omitting this will perform a "legacy" reset action + * (TBD). + */ +#define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0 +#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0 +#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1 + +/* MC_CMD_ENTITY_RESET_OUT msgresponse */ +#define MC_CMD_ENTITY_RESET_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_PCIE_CREDITS * Read instantaneous and minimum flow control thresholds. */ -#define MC_CMD_PCIE_CREDITS 0x21 +#define MC_CMD_PCIE_CREDITS 0x21 /* MC_CMD_PCIE_CREDITS_IN msgrequest */ #define MC_CMD_PCIE_CREDITS_IN_LEN 8 +/* poll period. 0 is disabled */ #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 +/* wipe statistics */ #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */ #define MC_CMD_PCIE_CREDITS_OUT_LEN 16 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 /***********************************/ -/* MC_CMD_RXD_MONITOR +/* MC_CMD_RXD_MONITOR * Get histogram of RX queue fill level. */ -#define MC_CMD_RXD_MONITOR 0x22 +#define MC_CMD_RXD_MONITOR 0x22 /* MC_CMD_RXD_MONITOR_IN msgrequest */ #define MC_CMD_RXD_MONITOR_IN_LEN 12 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 /* MC_CMD_RXD_MONITOR_OUT msgresponse */ #define MC_CMD_RXD_MONITOR_OUT_LEN 80 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 /***********************************/ -/* MC_CMD_PUTS - * puts(3) implementation over MCDI +/* MC_CMD_PUTS + * Copy the given ASCII string out onto UART and/or out of the network port. */ -#define MC_CMD_PUTS 0x23 +#define MC_CMD_PUTS 0x23 +#undef MC_CMD_0x23_PRIVILEGE_CTG +#define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_PUTS_IN msgrequest */ #define MC_CMD_PUTS_IN_LENMIN 13 #define MC_CMD_PUTS_IN_LENMAX 252 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) #define MC_CMD_PUTS_IN_DEST_OFST 0 #define MC_CMD_PUTS_IN_UART_LBN 0 #define MC_CMD_PUTS_IN_UART_WIDTH 1 #define MC_CMD_PUTS_IN_PORT_LBN 1 #define MC_CMD_PUTS_IN_PORT_WIDTH 1 #define MC_CMD_PUTS_IN_DHOST_OFST 4 #define MC_CMD_PUTS_IN_DHOST_LEN 6 #define MC_CMD_PUTS_IN_STRING_OFST 12 #define MC_CMD_PUTS_IN_STRING_LEN 1 #define MC_CMD_PUTS_IN_STRING_MINNUM 1 #define MC_CMD_PUTS_IN_STRING_MAXNUM 240 /* MC_CMD_PUTS_OUT msgresponse */ #define MC_CMD_PUTS_OUT_LEN 0 /***********************************/ -/* MC_CMD_GET_PHY_CFG - * Report PHY configuration. +/* MC_CMD_GET_PHY_CFG + * Report PHY configuration. This guarantees to succeed even if the PHY is in a + * 'zombie' state. Locks required: None */ -#define MC_CMD_GET_PHY_CFG 0x24 +#define MC_CMD_GET_PHY_CFG 0x24 +#undef MC_CMD_0x24_PRIVILEGE_CTG +#define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_GET_PHY_CFG_IN msgrequest */ #define MC_CMD_GET_PHY_CFG_IN_LEN 0 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */ #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 +/* flags */ #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 +/* ?? */ #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 +/* Bitmask of supported capabilities */ #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 #define MC_CMD_PHY_CAP_10HDX_LBN 1 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1 #define MC_CMD_PHY_CAP_10FDX_LBN 2 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1 #define MC_CMD_PHY_CAP_100HDX_LBN 3 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1 #define MC_CMD_PHY_CAP_100FDX_LBN 4 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1 #define MC_CMD_PHY_CAP_1000HDX_LBN 5 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 #define MC_CMD_PHY_CAP_1000FDX_LBN 6 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 #define MC_CMD_PHY_CAP_10000FDX_LBN 7 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 #define MC_CMD_PHY_CAP_PAUSE_LBN 8 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 #define MC_CMD_PHY_CAP_ASYM_LBN 9 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1 #define MC_CMD_PHY_CAP_AN_LBN 10 #define MC_CMD_PHY_CAP_AN_WIDTH 1 +#define MC_CMD_PHY_CAP_40000FDX_LBN 11 +#define MC_CMD_PHY_CAP_40000FDX_WIDTH 1 #define MC_CMD_PHY_CAP_DDM_LBN 12 #define MC_CMD_PHY_CAP_DDM_WIDTH 1 +/* ?? */ #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 +/* ?? */ #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 +/* ?? */ #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 +/* ?? */ #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 +/* ?? */ #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 -#define MC_CMD_MEDIA_XAUI 0x1 /* enum */ -#define MC_CMD_MEDIA_CX4 0x2 /* enum */ -#define MC_CMD_MEDIA_KX4 0x3 /* enum */ -#define MC_CMD_MEDIA_XFP 0x4 /* enum */ -#define MC_CMD_MEDIA_SFP_PLUS 0x5 /* enum */ -#define MC_CMD_MEDIA_BASE_T 0x6 /* enum */ +/* enum: Xaui. */ +#define MC_CMD_MEDIA_XAUI 0x1 +/* enum: CX4. */ +#define MC_CMD_MEDIA_CX4 0x2 +/* enum: KX4. */ +#define MC_CMD_MEDIA_KX4 0x3 +/* enum: XFP Far. */ +#define MC_CMD_MEDIA_XFP 0x4 +/* enum: SFP+. */ +#define MC_CMD_MEDIA_SFP_PLUS 0x5 +/* enum: 10GBaseT. */ +#define MC_CMD_MEDIA_BASE_T 0x6 +/* enum: QSFP+. */ +#define MC_CMD_MEDIA_QSFP_PLUS 0x7 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 -#define MC_CMD_MMD_CLAUSE22 0x0 /* enum */ +/* enum: Native clause 22 */ +#define MC_CMD_MMD_CLAUSE22 0x0 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ -#define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d /* enum */ +/* enum: Clause22 proxied over clause45 by PHY. */ +#define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 /***********************************/ -/* MC_CMD_START_BIST - * Start a BIST test on the PHY. +/* MC_CMD_START_BIST + * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST + * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held) */ -#define MC_CMD_START_BIST 0x25 +#define MC_CMD_START_BIST 0x25 +#undef MC_CMD_0x25_PRIVILEGE_CTG +#define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_START_BIST_IN msgrequest */ #define MC_CMD_START_BIST_IN_LEN 4 +/* Type of test. */ #define MC_CMD_START_BIST_IN_TYPE_OFST 0 -#define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 /* enum */ -#define MC_CMD_PHY_BIST_CABLE_LONG 0x2 /* enum */ -#define MC_CMD_BPX_SERDES_BIST 0x3 /* enum */ -#define MC_CMD_MC_LOOPBACK_BIST 0x4 /* enum */ -#define MC_CMD_PHY_BIST 0x5 /* enum */ +/* enum: Run the PHY's short cable BIST. */ +#define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 +/* enum: Run the PHY's long cable BIST. */ +#define MC_CMD_PHY_BIST_CABLE_LONG 0x2 +/* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */ +#define MC_CMD_BPX_SERDES_BIST 0x3 +/* enum: Run the MC loopback tests. */ +#define MC_CMD_MC_LOOPBACK_BIST 0x4 +/* enum: Run the PHY's standard BIST. */ +#define MC_CMD_PHY_BIST 0x5 +/* enum: Run MC RAM test. */ +#define MC_CMD_MC_MEM_BIST 0x6 +/* enum: Run Port RAM test. */ +#define MC_CMD_PORT_MEM_BIST 0x7 +/* enum: Run register test. */ +#define MC_CMD_REG_BIST 0x8 /* MC_CMD_START_BIST_OUT msgresponse */ #define MC_CMD_START_BIST_OUT_LEN 0 /***********************************/ -/* MC_CMD_POLL_BIST - * Poll for BIST completion. +/* MC_CMD_POLL_BIST + * Poll for BIST completion. Returns a single status code, and optionally some + * PHY specific bist output. The driver should only consume the BIST output + * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't + * successfully parse the BIST output, it should still respect the pass/Fail in + * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0, + * EACCES (if PHY_LOCK is not held). */ -#define MC_CMD_POLL_BIST 0x26 +#define MC_CMD_POLL_BIST 0x26 +#undef MC_CMD_0x26_PRIVILEGE_CTG +#define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_POLL_BIST_IN msgrequest */ #define MC_CMD_POLL_BIST_IN_LEN 0 /* MC_CMD_POLL_BIST_OUT msgresponse */ #define MC_CMD_POLL_BIST_OUT_LEN 8 +/* result */ #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 -#define MC_CMD_POLL_BIST_RUNNING 0x1 /* enum */ -#define MC_CMD_POLL_BIST_PASSED 0x2 /* enum */ -#define MC_CMD_POLL_BIST_FAILED 0x3 /* enum */ -#define MC_CMD_POLL_BIST_TIMEOUT 0x4 /* enum */ +/* enum: Running. */ +#define MC_CMD_POLL_BIST_RUNNING 0x1 +/* enum: Passed. */ +#define MC_CMD_POLL_BIST_PASSED 0x2 +/* enum: Failed. */ +#define MC_CMD_POLL_BIST_FAILED 0x3 +/* enum: Timed-out. */ +#define MC_CMD_POLL_BIST_TIMEOUT 0x4 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 +/* result */ /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ /* Enum values, see field(s): */ /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 +/* Status of each channel A */ #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 -#define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 /* enum */ -#define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 /* enum */ -#define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 /* enum */ -#define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 /* enum */ -#define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 /* enum */ +/* enum: Ok. */ +#define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 +/* enum: Open. */ +#define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 +/* enum: Intra-pair short. */ +#define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 +/* enum: Inter-pair short. */ +#define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 +/* enum: Busy. */ +#define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 +/* Status of each channel B */ #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 /* Enum values, see field(s): */ /* CABLE_STATUS_A */ +/* Status of each channel C */ #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 /* Enum values, see field(s): */ /* CABLE_STATUS_A */ +/* Status of each channel D */ #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 /* Enum values, see field(s): */ /* CABLE_STATUS_A */ /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 +/* result */ /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ /* Enum values, see field(s): */ /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 -#define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 /* enum */ -#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 /* enum */ -#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 /* enum */ -#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 /* enum */ -#define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 /* enum */ -#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 /* enum */ -#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 /* enum */ -#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 /* enum */ -#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 /* enum */ +/* enum: Complete. */ +#define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 +/* enum: Bus switch off I2C write. */ +#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 +/* enum: Bus switch off I2C no access IO exp. */ +#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 +/* enum: Bus switch off I2C no access module. */ +#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 +/* enum: IO exp I2C configure. */ +#define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 +/* enum: Bus switch I2C no cross talk. */ +#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 +/* enum: Module presence. */ +#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 +/* enum: Module ID I2C access. */ +#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 +/* enum: Module ID sane value. */ +#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 +/* MC_CMD_POLL_BIST_OUT_MEM msgresponse */ +#define MC_CMD_POLL_BIST_OUT_MEM_LEN 36 +/* result */ +/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ +/* Enum values, see field(s): */ +/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ +#define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4 +/* enum: Test has completed. */ +#define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0 +/* enum: RAM test - walk ones. */ +#define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1 +/* enum: RAM test - walk zeros. */ +#define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2 +/* enum: RAM test - walking inversions zeros/ones. */ +#define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3 +/* enum: RAM test - walking inversions checkerboard. */ +#define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4 +/* enum: Register test - set / clear individual bits. */ +#define MC_CMD_POLL_BIST_MEM_REG 0x5 +/* enum: ECC error detected. */ +#define MC_CMD_POLL_BIST_MEM_ECC 0x6 +/* Failure address, only valid if result is POLL_BIST_FAILED */ +#define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8 +/* Bus or address space to which the failure address corresponds */ +#define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12 +/* enum: MC MIPS bus. */ +#define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0 +/* enum: CSR IREG bus. */ +#define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1 +/* enum: RX DPCPU bus. */ +#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2 +/* enum: TX0 DPCPU bus. */ +#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3 +/* enum: TX1 DPCPU bus. */ +#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4 +/* enum: RX DICPU bus. */ +#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5 +/* enum: TX DICPU bus. */ +#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6 +/* Pattern written to RAM / register */ +#define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16 +/* Actual value read from RAM / register */ +#define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20 +/* ECC error mask */ +#define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24 +/* ECC parity error mask */ +#define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28 +/* ECC fatal error mask */ +#define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32 + /***********************************/ -/* MC_CMD_FLUSH_RX_QUEUES - * Flush receive queue(s). +/* MC_CMD_FLUSH_RX_QUEUES + * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ + * flushes should be initiated via this MCDI operation, rather than via + * directly writing FLUSH_CMD. + * + * The flush is completed (either done/fail) asynchronously (after this command + * returns). The driver must still wait for flush done/failure events as usual. */ -#define MC_CMD_FLUSH_RX_QUEUES 0x27 +#define MC_CMD_FLUSH_RX_QUEUES 0x27 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 /***********************************/ -/* MC_CMD_GET_LOOPBACK_MODES - * Get port's loopback modes. +/* MC_CMD_GET_LOOPBACK_MODES + * Returns a bitmask of loopback modes available at each speed. */ -#define MC_CMD_GET_LOOPBACK_MODES 0x28 +#define MC_CMD_GET_LOOPBACK_MODES 0x28 +#undef MC_CMD_0x28_PRIVILEGE_CTG +#define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ -#define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 32 +#define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40 +/* Supported loopbacks. */ #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 -#define MC_CMD_LOOPBACK_NONE 0x0 /* enum */ -#define MC_CMD_LOOPBACK_DATA 0x1 /* enum */ -#define MC_CMD_LOOPBACK_GMAC 0x2 /* enum */ -#define MC_CMD_LOOPBACK_XGMII 0x3 /* enum */ -#define MC_CMD_LOOPBACK_XGXS 0x4 /* enum */ -#define MC_CMD_LOOPBACK_XAUI 0x5 /* enum */ -#define MC_CMD_LOOPBACK_GMII 0x6 /* enum */ -#define MC_CMD_LOOPBACK_SGMII 0x7 /* enum */ -#define MC_CMD_LOOPBACK_XGBR 0x8 /* enum */ -#define MC_CMD_LOOPBACK_XFI 0x9 /* enum */ -#define MC_CMD_LOOPBACK_XAUI_FAR 0xa /* enum */ -#define MC_CMD_LOOPBACK_GMII_FAR 0xb /* enum */ -#define MC_CMD_LOOPBACK_SGMII_FAR 0xc /* enum */ -#define MC_CMD_LOOPBACK_XFI_FAR 0xd /* enum */ -#define MC_CMD_LOOPBACK_GPHY 0xe /* enum */ -#define MC_CMD_LOOPBACK_PHYXS 0xf /* enum */ -#define MC_CMD_LOOPBACK_PCS 0x10 /* enum */ -#define MC_CMD_LOOPBACK_PMAPMD 0x11 /* enum */ -#define MC_CMD_LOOPBACK_XPORT 0x12 /* enum */ -#define MC_CMD_LOOPBACK_XGMII_WS 0x13 /* enum */ -#define MC_CMD_LOOPBACK_XAUI_WS 0x14 /* enum */ -#define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 /* enum */ -#define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 /* enum */ -#define MC_CMD_LOOPBACK_GMII_WS 0x17 /* enum */ -#define MC_CMD_LOOPBACK_XFI_WS 0x18 /* enum */ -#define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 /* enum */ -#define MC_CMD_LOOPBACK_PHYXS_WS 0x1a /* enum */ -#define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 /* enum */ +/* enum: None. */ +#define MC_CMD_LOOPBACK_NONE 0x0 +/* enum: Data. */ +#define MC_CMD_LOOPBACK_DATA 0x1 +/* enum: GMAC. */ +#define MC_CMD_LOOPBACK_GMAC 0x2 +/* enum: XGMII. */ +#define MC_CMD_LOOPBACK_XGMII 0x3 +/* enum: XGXS. */ +#define MC_CMD_LOOPBACK_XGXS 0x4 +/* enum: XAUI. */ +#define MC_CMD_LOOPBACK_XAUI 0x5 +/* enum: GMII. */ +#define MC_CMD_LOOPBACK_GMII 0x6 +/* enum: SGMII. */ +#define MC_CMD_LOOPBACK_SGMII 0x7 +/* enum: XGBR. */ +#define MC_CMD_LOOPBACK_XGBR 0x8 +/* enum: XFI. */ +#define MC_CMD_LOOPBACK_XFI 0x9 +/* enum: XAUI Far. */ +#define MC_CMD_LOOPBACK_XAUI_FAR 0xa +/* enum: GMII Far. */ +#define MC_CMD_LOOPBACK_GMII_FAR 0xb +/* enum: SGMII Far. */ +#define MC_CMD_LOOPBACK_SGMII_FAR 0xc +/* enum: XFI Far. */ +#define MC_CMD_LOOPBACK_XFI_FAR 0xd +/* enum: GPhy. */ +#define MC_CMD_LOOPBACK_GPHY 0xe +/* enum: PhyXS. */ +#define MC_CMD_LOOPBACK_PHYXS 0xf +/* enum: PCS. */ +#define MC_CMD_LOOPBACK_PCS 0x10 +/* enum: PMA-PMD. */ +#define MC_CMD_LOOPBACK_PMAPMD 0x11 +/* enum: Cross-Port. */ +#define MC_CMD_LOOPBACK_XPORT 0x12 +/* enum: XGMII-Wireside. */ +#define MC_CMD_LOOPBACK_XGMII_WS 0x13 +/* enum: XAUI Wireside. */ +#define MC_CMD_LOOPBACK_XAUI_WS 0x14 +/* enum: XAUI Wireside Far. */ +#define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 +/* enum: XAUI Wireside near. */ +#define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 +/* enum: GMII Wireside. */ +#define MC_CMD_LOOPBACK_GMII_WS 0x17 +/* enum: XFI Wireside. */ +#define MC_CMD_LOOPBACK_XFI_WS 0x18 +/* enum: XFI Wireside Far. */ +#define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 +/* enum: PhyXS Wireside. */ +#define MC_CMD_LOOPBACK_PHYXS_WS 0x1a +/* enum: PMA lanes MAC-Serdes. */ +#define MC_CMD_LOOPBACK_PMA_INT 0x1b +/* enum: KR Serdes Parallel (Encoder). */ +#define MC_CMD_LOOPBACK_SD_NEAR 0x1c +/* enum: KR Serdes Serial. */ +#define MC_CMD_LOOPBACK_SD_FAR 0x1d +/* enum: PMA lanes MAC-Serdes Wireside. */ +#define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e +/* enum: KR Serdes Parallel Wireside (Full PCS). */ +#define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f +/* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ +#define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 +/* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ +#define MC_CMD_LOOPBACK_SD_FEP_WS 0x21 +/* enum: KR Serdes Serial Wireside. */ +#define MC_CMD_LOOPBACK_SD_FES_WS 0x22 +/* enum: Near side of AOE Siena side port */ +#define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 +/* enum: Medford Wireside datapath loopback */ +#define MC_CMD_LOOPBACK_DATA_WS 0x24 +/* enum: Force link up without setting up any physical loopback (snapper use + * only) + */ +#define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 +/* Supported loopbacks. */ #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 /* Enum values, see field(s): */ /* 100M */ +/* Supported loopbacks. */ #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 /* Enum values, see field(s): */ /* 100M */ +/* Supported loopbacks. */ #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 /* Enum values, see field(s): */ /* 100M */ +/* Supported loopbacks. */ +#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32 +#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8 +#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32 +#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36 +/* Enum values, see field(s): */ +/* 100M */ /***********************************/ -/* MC_CMD_GET_LINK - * Read the unified MAC/PHY link state. +/* MC_CMD_GET_LINK + * Read the unified MAC/PHY link state. Locks required: None Return code: 0, + * ETIME. */ -#define MC_CMD_GET_LINK 0x29 +#define MC_CMD_GET_LINK 0x29 +#undef MC_CMD_0x29_PRIVILEGE_CTG +#define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_GET_LINK_IN msgrequest */ #define MC_CMD_GET_LINK_IN_LEN 0 /* MC_CMD_GET_LINK_OUT msgresponse */ #define MC_CMD_GET_LINK_OUT_LEN 28 +/* near-side advertised capabilities */ #define MC_CMD_GET_LINK_OUT_CAP_OFST 0 +/* link-partner advertised capabilities */ #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 +/* Autonegotiated speed in mbit/s. The link may still be down even if this + * reads non-zero. + */ #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 +/* Current loopback setting. */ #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 /* Enum values, see field(s): */ /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1 +/* This returns the negotiated flow control value. */ #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 -#define MC_CMD_FCNTL_OFF 0x0 /* enum */ -#define MC_CMD_FCNTL_RESPOND 0x1 /* enum */ -#define MC_CMD_FCNTL_BIDIR 0x2 /* enum */ +/* Enum values, see field(s): */ +/* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */ #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 /***********************************/ -/* MC_CMD_SET_LINK - * Write the unified MAC/PHY link configuration. +/* MC_CMD_SET_LINK + * Write the unified MAC/PHY link configuration. Locks required: None. Return + * code: 0, EINVAL, ETIME */ -#define MC_CMD_SET_LINK 0x2a +#define MC_CMD_SET_LINK 0x2a +#undef MC_CMD_0x2a_PRIVILEGE_CTG +#define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK + /* MC_CMD_SET_LINK_IN msgrequest */ #define MC_CMD_SET_LINK_IN_LEN 16 +/* ??? */ #define MC_CMD_SET_LINK_IN_CAP_OFST 0 +/* Flags */ #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 +/* Loopback mode. */ #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 /* Enum values, see field(s): */ /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ +/* A loopback speed of "0" is supported, and means (choose any available + * speed). + */ #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 /* MC_CMD_SET_LINK_OUT msgresponse */ #define MC_CMD_SET_LINK_OUT_LEN 0 /***********************************/ -/* MC_CMD_SET_ID_LED - * Set indentification LED state. +/* MC_CMD_SET_ID_LED + * Set identification LED state. Locks required: None. Return code: 0, EINVAL */ -#define MC_CMD_SET_ID_LED 0x2b +#define MC_CMD_SET_ID_LED 0x2b +#undef MC_CMD_0x2b_PRIVILEGE_CTG +#define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK + /* MC_CMD_SET_ID_LED_IN msgrequest */ #define MC_CMD_SET_ID_LED_IN_LEN 4 +/* Set LED state. */ #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 #define MC_CMD_LED_OFF 0x0 /* enum */ #define MC_CMD_LED_ON 0x1 /* enum */ #define MC_CMD_LED_DEFAULT 0x2 /* enum */ /* MC_CMD_SET_ID_LED_OUT msgresponse */ #define MC_CMD_SET_ID_LED_OUT_LEN 0 /***********************************/ -/* MC_CMD_SET_MAC - * Set MAC configuration. +/* MC_CMD_SET_MAC + * Set MAC configuration. Locks required: None. Return code: 0, EINVAL */ -#define MC_CMD_SET_MAC 0x2c +#define MC_CMD_SET_MAC 0x2c +#undef MC_CMD_0x2c_PRIVILEGE_CTG +#define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_LINK + /* MC_CMD_SET_MAC_IN msgrequest */ -#define MC_CMD_SET_MAC_IN_LEN 24 +#define MC_CMD_SET_MAC_IN_LEN 28 +/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of + * EtherII, VLAN, bug16011 padding). + */ #define MC_CMD_SET_MAC_IN_MTU_OFST 0 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 #define MC_CMD_SET_MAC_IN_ADDR_OFST 8 #define MC_CMD_SET_MAC_IN_ADDR_LEN 8 #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 #define MC_CMD_SET_MAC_IN_REJECT_OFST 16 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 -/* MC_CMD_FCNTL_OFF 0x0 */ -/* MC_CMD_FCNTL_RESPOND 0x1 */ -/* MC_CMD_FCNTL_BIDIR 0x2 */ -#define MC_CMD_FCNTL_AUTO 0x3 /* enum */ +/* enum: Flow control is off. */ +#define MC_CMD_FCNTL_OFF 0x0 +/* enum: Respond to flow control. */ +#define MC_CMD_FCNTL_RESPOND 0x1 +/* enum: Respond to and Issue flow control. */ +#define MC_CMD_FCNTL_BIDIR 0x2 +/* enum: Auto neg flow control. */ +#define MC_CMD_FCNTL_AUTO 0x3 +/* enum: Priority flow control (eftest builds only). */ +#define MC_CMD_FCNTL_QBB 0x4 +/* enum: Issue flow control. */ +#define MC_CMD_FCNTL_GENERATE 0x5 +#define MC_CMD_SET_MAC_IN_FLAGS_OFST 24 +#define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0 +#define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1 /* MC_CMD_SET_MAC_OUT msgresponse */ #define MC_CMD_SET_MAC_OUT_LEN 0 /***********************************/ -/* MC_CMD_PHY_STATS - * Get generic PHY statistics. +/* MC_CMD_PHY_STATS + * Get generic PHY statistics. This call returns the statistics for a generic + * PHY in a sparse array (indexed by the enumerate). Each value is represented + * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the + * statistics may be read from the message response. If DMA_ADDR != 0, then the + * statistics are dmad to that (page-aligned location). Locks required: None. + * Returns: 0, ETIME */ -#define MC_CMD_PHY_STATS 0x2d +#define MC_CMD_PHY_STATS 0x2d +#undef MC_CMD_0x2d_PRIVILEGE_CTG +#define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK + /* MC_CMD_PHY_STATS_IN msgrequest */ #define MC_CMD_PHY_STATS_IN_LEN 8 +/* ??? */ #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS -#define MC_CMD_OUI 0x0 /* enum */ -#define MC_CMD_PMA_PMD_LINK_UP 0x1 /* enum */ -#define MC_CMD_PMA_PMD_RX_FAULT 0x2 /* enum */ -#define MC_CMD_PMA_PMD_TX_FAULT 0x3 /* enum */ -#define MC_CMD_PMA_PMD_SIGNAL 0x4 /* enum */ -#define MC_CMD_PMA_PMD_SNR_A 0x5 /* enum */ -#define MC_CMD_PMA_PMD_SNR_B 0x6 /* enum */ -#define MC_CMD_PMA_PMD_SNR_C 0x7 /* enum */ -#define MC_CMD_PMA_PMD_SNR_D 0x8 /* enum */ -#define MC_CMD_PCS_LINK_UP 0x9 /* enum */ -#define MC_CMD_PCS_RX_FAULT 0xa /* enum */ -#define MC_CMD_PCS_TX_FAULT 0xb /* enum */ -#define MC_CMD_PCS_BER 0xc /* enum */ -#define MC_CMD_PCS_BLOCK_ERRORS 0xd /* enum */ -#define MC_CMD_PHYXS_LINK_UP 0xe /* enum */ -#define MC_CMD_PHYXS_RX_FAULT 0xf /* enum */ -#define MC_CMD_PHYXS_TX_FAULT 0x10 /* enum */ -#define MC_CMD_PHYXS_ALIGN 0x11 /* enum */ -#define MC_CMD_PHYXS_SYNC 0x12 /* enum */ -#define MC_CMD_AN_LINK_UP 0x13 /* enum */ -#define MC_CMD_AN_COMPLETE 0x14 /* enum */ -#define MC_CMD_AN_10GBT_STATUS 0x15 /* enum */ -#define MC_CMD_CL22_LINK_UP 0x16 /* enum */ -#define MC_CMD_PHY_NSTATS 0x17 /* enum */ +/* enum: OUI. */ +#define MC_CMD_OUI 0x0 +/* enum: PMA-PMD Link Up. */ +#define MC_CMD_PMA_PMD_LINK_UP 0x1 +/* enum: PMA-PMD RX Fault. */ +#define MC_CMD_PMA_PMD_RX_FAULT 0x2 +/* enum: PMA-PMD TX Fault. */ +#define MC_CMD_PMA_PMD_TX_FAULT 0x3 +/* enum: PMA-PMD Signal */ +#define MC_CMD_PMA_PMD_SIGNAL 0x4 +/* enum: PMA-PMD SNR A. */ +#define MC_CMD_PMA_PMD_SNR_A 0x5 +/* enum: PMA-PMD SNR B. */ +#define MC_CMD_PMA_PMD_SNR_B 0x6 +/* enum: PMA-PMD SNR C. */ +#define MC_CMD_PMA_PMD_SNR_C 0x7 +/* enum: PMA-PMD SNR D. */ +#define MC_CMD_PMA_PMD_SNR_D 0x8 +/* enum: PCS Link Up. */ +#define MC_CMD_PCS_LINK_UP 0x9 +/* enum: PCS RX Fault. */ +#define MC_CMD_PCS_RX_FAULT 0xa +/* enum: PCS TX Fault. */ +#define MC_CMD_PCS_TX_FAULT 0xb +/* enum: PCS BER. */ +#define MC_CMD_PCS_BER 0xc +/* enum: PCS Block Errors. */ +#define MC_CMD_PCS_BLOCK_ERRORS 0xd +/* enum: PhyXS Link Up. */ +#define MC_CMD_PHYXS_LINK_UP 0xe +/* enum: PhyXS RX Fault. */ +#define MC_CMD_PHYXS_RX_FAULT 0xf +/* enum: PhyXS TX Fault. */ +#define MC_CMD_PHYXS_TX_FAULT 0x10 +/* enum: PhyXS Align. */ +#define MC_CMD_PHYXS_ALIGN 0x11 +/* enum: PhyXS Sync. */ +#define MC_CMD_PHYXS_SYNC 0x12 +/* enum: AN link-up. */ +#define MC_CMD_AN_LINK_UP 0x13 +/* enum: AN Complete. */ +#define MC_CMD_AN_COMPLETE 0x14 +/* enum: AN 10GBaseT Status. */ +#define MC_CMD_AN_10GBT_STATUS 0x15 +/* enum: Clause 22 Link-Up. */ +#define MC_CMD_CL22_LINK_UP 0x16 +/* enum: (Last entry) */ +#define MC_CMD_PHY_NSTATS 0x17 /***********************************/ -/* MC_CMD_MAC_STATS - * Get generic MAC statistics. +/* MC_CMD_MAC_STATS + * Get generic MAC statistics. This call returns unified statistics maintained + * by the MC as it switches between the GMAC and XMAC. The MC will write out + * all supported stats. The driver should zero initialise the buffer to + * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is + * performed, and the statistics may be read from the message response. If + * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location). + * Locks required: None. The PERIODIC_CLEAR option is not used and now has no + * effect. Returns: 0, ETIME */ -#define MC_CMD_MAC_STATS 0x2e +#define MC_CMD_MAC_STATS 0x2e +#undef MC_CMD_0x2e_PRIVILEGE_CTG +#define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_MAC_STATS_IN msgrequest */ -#define MC_CMD_MAC_STATS_IN_LEN 16 +#define MC_CMD_MAC_STATS_IN_LEN 20 +/* ??? */ #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 #define MC_CMD_MAC_STATS_IN_CMD_OFST 8 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 +/* port id so vadapter stats can be provided */ +#define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ +#define MC_CMD_MAC_DMABUF_START 0x1 /* enum */ #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ -#define MC_CMD_GMAC_DMABUF_START 0x40 /* enum */ -#define MC_CMD_GMAC_DMABUF_END 0x5f /* enum */ +/* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS + * capability only. + */ +#define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c +/* enum: PM discard_bb_overflow counter. Valid for EF10 with + * PM_AND_RXDP_COUNTERS capability only. + */ +#define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d +/* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS + * capability only. + */ +#define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e +/* enum: PM discard_vfifo_full counter. Valid for EF10 with + * PM_AND_RXDP_COUNTERS capability only. + */ +#define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f +/* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS + * capability only. + */ +#define MC_CMD_MAC_PM_TRUNC_QBB 0x40 +/* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS + * capability only. + */ +#define MC_CMD_MAC_PM_DISCARD_QBB 0x41 +/* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS + * capability only. + */ +#define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42 +/* enum: RXDP counter: Number of packets dropped due to the queue being + * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. + */ +#define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43 +/* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10 + * with PM_AND_RXDP_COUNTERS capability only. + */ +#define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45 +/* enum: RXDP counter: Number of non-host packets. Valid for EF10 with + * PM_AND_RXDP_COUNTERS capability only. + */ +#define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46 +/* enum: RXDP counter: Number of times an hlb descriptor fetch was performed. + * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. + */ +#define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47 +/* enum: RXDP counter: Number of times the DPCPU waited for an existing + * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. + */ +#define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48 +#define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */ +#define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */ +#define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */ +#define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */ +#define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */ +#define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */ +#define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */ +#define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */ +#define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */ +#define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */ +#define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */ +#define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */ +#define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */ +#define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */ +#define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */ +#define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */ +#define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */ +#define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */ +#define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */ +#define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */ +/* enum: Start of GMAC stats buffer space, for Siena only. */ +#define MC_CMD_GMAC_DMABUF_START 0x40 +/* enum: End of GMAC stats buffer space, for Siena only. */ +#define MC_CMD_GMAC_DMABUF_END 0x5f #define MC_CMD_MAC_GENERATION_END 0x60 /* enum */ #define MC_CMD_MAC_NSTATS 0x61 /* enum */ /***********************************/ -/* MC_CMD_SRIOV +/* MC_CMD_SRIOV * to be documented */ -#define MC_CMD_SRIOV 0x30 +#define MC_CMD_SRIOV 0x30 /* MC_CMD_SRIOV_IN msgrequest */ #define MC_CMD_SRIOV_IN_LEN 12 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 /* MC_CMD_SRIOV_OUT msgresponse */ #define MC_CMD_SRIOV_OUT_LEN 8 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 +/* this is only used for the first record */ #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 /***********************************/ -/* MC_CMD_MEMCPY - * Perform memory copy operation. +/* MC_CMD_MEMCPY + * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data + * embedded directly in the command. + * + * A common pattern is for a client to use generation counts to signal a dma + * update of a datastructure. To facilitate this, this MCDI operation can + * contain multiple requests which are executed in strict order. Requests take + * the form of duplicating the entire MCDI request continuously (including the + * requests record, which is ignored in all but the first structure) + * + * The source data can either come from a DMA from the host, or it can be + * embedded within the request directly, thereby eliminating a DMA read. To + * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and + * ADDR_LO=offset, and inserts the data at %offset from the start of the + * payload. It's the callers responsibility to ensure that the embedded data + * doesn't overlap the records. + * + * Returns: 0, EINVAL (invalid RID) */ -#define MC_CMD_MEMCPY 0x31 +#define MC_CMD_MEMCPY 0x31 /* MC_CMD_MEMCPY_IN msgrequest */ #define MC_CMD_MEMCPY_IN_LENMIN 32 #define MC_CMD_MEMCPY_IN_LENMAX 224 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) +/* see MC_CMD_MEMCPY_RECORD_TYPEDEF */ #define MC_CMD_MEMCPY_IN_RECORD_OFST 0 #define MC_CMD_MEMCPY_IN_RECORD_LEN 32 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 /* MC_CMD_MEMCPY_OUT msgresponse */ #define MC_CMD_MEMCPY_OUT_LEN 0 /***********************************/ -/* MC_CMD_WOL_FILTER_SET +/* MC_CMD_WOL_FILTER_SET * Set a WoL filter. */ -#define MC_CMD_WOL_FILTER_SET 0x32 +#define MC_CMD_WOL_FILTER_SET 0x32 +#undef MC_CMD_0x32_PRIVILEGE_CTG +#define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK + /* MC_CMD_WOL_FILTER_SET_IN msgrequest */ #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ +/* A type value of 1 is unused. */ #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 -#define MC_CMD_WOL_TYPE_MAGIC 0x0 /* enum */ -#define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 /* enum */ -#define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 /* enum */ -#define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 /* enum */ -#define MC_CMD_WOL_TYPE_BITMAP 0x5 /* enum */ -#define MC_CMD_WOL_TYPE_LINK 0x6 /* enum */ -#define MC_CMD_WOL_TYPE_MAX 0x7 /* enum */ +/* enum: Magic */ +#define MC_CMD_WOL_TYPE_MAGIC 0x0 +/* enum: MS Windows Magic */ +#define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 +/* enum: IPv4 Syn */ +#define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 +/* enum: IPv6 Syn */ +#define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 +/* enum: Bitmap */ +#define MC_CMD_WOL_TYPE_BITMAP 0x5 +/* enum: Link */ +#define MC_CMD_WOL_TYPE_LINK 0x6 +/* enum: (Above this for future use) */ +#define MC_CMD_WOL_TYPE_MAX 0x7 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 /***********************************/ -/* MC_CMD_WOL_FILTER_REMOVE - * Remove a WoL filter. +/* MC_CMD_WOL_FILTER_REMOVE + * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS */ -#define MC_CMD_WOL_FILTER_REMOVE 0x33 +#define MC_CMD_WOL_FILTER_REMOVE 0x33 +#undef MC_CMD_0x33_PRIVILEGE_CTG +#define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK + /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 /***********************************/ -/* MC_CMD_WOL_FILTER_RESET - * Reset (i.e. remove all) WoL filters. +/* MC_CMD_WOL_FILTER_RESET + * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0, + * ENOSYS */ -#define MC_CMD_WOL_FILTER_RESET 0x34 +#define MC_CMD_WOL_FILTER_RESET 0x34 +#undef MC_CMD_0x34_PRIVILEGE_CTG +#define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK + /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 /***********************************/ -/* MC_CMD_SET_MCAST_HASH - * Set the MCASH hash value. +/* MC_CMD_SET_MCAST_HASH + * Set the MCAST hash value without otherwise reconfiguring the MAC */ -#define MC_CMD_SET_MCAST_HASH 0x35 +#define MC_CMD_SET_MCAST_HASH 0x35 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */ #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 /***********************************/ -/* MC_CMD_NVRAM_TYPES - * Get virtual NVRAM partitions information. +/* MC_CMD_NVRAM_TYPES + * Return bitfield indicating available types of virtual NVRAM partitions. + * Locks required: none. Returns: 0 */ -#define MC_CMD_NVRAM_TYPES 0x36 +#define MC_CMD_NVRAM_TYPES 0x36 +#undef MC_CMD_0x36_PRIVILEGE_CTG +#define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_NVRAM_TYPES_IN msgrequest */ #define MC_CMD_NVRAM_TYPES_IN_LEN 0 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */ #define MC_CMD_NVRAM_TYPES_OUT_LEN 4 +/* Bit mask of supported types. */ #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 -#define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 /* enum */ -#define MC_CMD_NVRAM_TYPE_MC_FW 0x1 /* enum */ -#define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 /* enum */ -#define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 /* enum */ -#define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 /* enum */ -#define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 /* enum */ -#define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 /* enum */ -#define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 /* enum */ -#define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 /* enum */ -#define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 /* enum */ -#define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa /* enum */ -#define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb /* enum */ -#define MC_CMD_NVRAM_TYPE_LOG 0xc /* enum */ -#define MC_CMD_NVRAM_TYPE_FPGA 0xd /* enum */ -#define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe /* enum */ -#define MC_CMD_NVRAM_TYPE_FC_FW 0xf /* enum */ -#define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 /* enum */ -#define MC_CMD_NVRAM_TYPE_CPLD 0x11 /* enum */ -#define MC_CMD_NVRAM_TYPE_LICENSE 0x12 /* enum */ -#define MC_CMD_NVRAM_TYPE_FC_LOG 0x13 /* enum */ -#define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14 /* enum */ +/* enum: Disabled callisto. */ +#define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 +/* enum: MC firmware. */ +#define MC_CMD_NVRAM_TYPE_MC_FW 0x1 +/* enum: MC backup firmware. */ +#define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 +/* enum: Static configuration Port0. */ +#define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 +/* enum: Static configuration Port1. */ +#define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 +/* enum: Dynamic configuration Port0. */ +#define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 +/* enum: Dynamic configuration Port1. */ +#define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 +/* enum: Expansion Rom. */ +#define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 +/* enum: Expansion Rom Configuration Port0. */ +#define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 +/* enum: Expansion Rom Configuration Port1. */ +#define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 +/* enum: Phy Configuration Port0. */ +#define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa +/* enum: Phy Configuration Port1. */ +#define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb +/* enum: Log. */ +#define MC_CMD_NVRAM_TYPE_LOG 0xc +/* enum: FPGA image. */ +#define MC_CMD_NVRAM_TYPE_FPGA 0xd +/* enum: FPGA backup image */ +#define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe +/* enum: FC firmware. */ +#define MC_CMD_NVRAM_TYPE_FC_FW 0xf +/* enum: FC backup firmware. */ +#define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 +/* enum: CPLD image. */ +#define MC_CMD_NVRAM_TYPE_CPLD 0x11 +/* enum: Licensing information. */ +#define MC_CMD_NVRAM_TYPE_LICENSE 0x12 +/* enum: FC Log. */ +#define MC_CMD_NVRAM_TYPE_FC_LOG 0x13 +/* enum: Additional flash on FPGA. */ +#define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14 /***********************************/ -/* MC_CMD_NVRAM_INFO - * Read info about a virtual NVRAM partition. +/* MC_CMD_NVRAM_INFO + * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0, + * EINVAL (bad type). */ -#define MC_CMD_NVRAM_INFO 0x37 +#define MC_CMD_NVRAM_INFO 0x37 +#undef MC_CMD_0x37_PRIVILEGE_CTG +#define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_NVRAM_INFO_IN msgrequest */ #define MC_CMD_NVRAM_INFO_IN_LEN 4 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 /* Enum values, see field(s): */ /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ /* MC_CMD_NVRAM_INFO_OUT msgresponse */ #define MC_CMD_NVRAM_INFO_OUT_LEN 24 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 /* Enum values, see field(s): */ /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 +#define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1 +#define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1 +#define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7 +#define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 /***********************************/ -/* MC_CMD_NVRAM_UPDATE_START - * Start a group of update operations on a virtual NVRAM partition. +/* MC_CMD_NVRAM_UPDATE_START + * Start a group of update operations on a virtual NVRAM partition. Locks + * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if + * PHY_LOCK required and not held). */ -#define MC_CMD_NVRAM_UPDATE_START 0x38 +#define MC_CMD_NVRAM_UPDATE_START 0x38 +#undef MC_CMD_0x38_PRIVILEGE_CTG +#define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest */ #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 /* Enum values, see field(s): */ /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 /***********************************/ -/* MC_CMD_NVRAM_READ - * Read data from a virtual NVRAM partition. +/* MC_CMD_NVRAM_READ + * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if + * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if + * PHY_LOCK required and not held) */ -#define MC_CMD_NVRAM_READ 0x39 +#define MC_CMD_NVRAM_READ 0x39 +#undef MC_CMD_0x39_PRIVILEGE_CTG +#define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_NVRAM_READ_IN msgrequest */ #define MC_CMD_NVRAM_READ_IN_LEN 12 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 /* Enum values, see field(s): */ /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 +/* amount to read in bytes */ #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 /* MC_CMD_NVRAM_READ_OUT msgresponse */ #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 /***********************************/ -/* MC_CMD_NVRAM_WRITE - * Write data to a virtual NVRAM partition. +/* MC_CMD_NVRAM_WRITE + * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if + * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if + * PHY_LOCK required and not held) */ -#define MC_CMD_NVRAM_WRITE 0x3a +#define MC_CMD_NVRAM_WRITE 0x3a +#undef MC_CMD_0x3a_PRIVILEGE_CTG +#define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_NVRAM_WRITE_IN msgrequest */ #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 /* Enum values, see field(s): */ /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */ #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 /***********************************/ -/* MC_CMD_NVRAM_ERASE - * Erase sector(s) from a virtual NVRAM partition. +/* MC_CMD_NVRAM_ERASE + * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if + * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if + * PHY_LOCK required and not held) */ -#define MC_CMD_NVRAM_ERASE 0x3b +#define MC_CMD_NVRAM_ERASE 0x3b +#undef MC_CMD_0x3b_PRIVILEGE_CTG +#define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_NVRAM_ERASE_IN msgrequest */ #define MC_CMD_NVRAM_ERASE_IN_LEN 12 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 /* Enum values, see field(s): */ /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */ #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 /***********************************/ -/* MC_CMD_NVRAM_UPDATE_FINISH - * Finish a group of update operations on a virtual NVRAM partition. +/* MC_CMD_NVRAM_UPDATE_FINISH + * Finish a group of update operations on a virtual NVRAM partition. Locks + * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad + * type/offset/length), EACCES (if PHY_LOCK required and not held) */ -#define MC_CMD_NVRAM_UPDATE_FINISH 0x3c +#define MC_CMD_NVRAM_UPDATE_FINISH 0x3c +#undef MC_CMD_0x3c_PRIVILEGE_CTG +#define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest */ #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 /* Enum values, see field(s): */ /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse */ #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 /***********************************/ -/* MC_CMD_REBOOT +/* MC_CMD_REBOOT * Reboot the MC. + * + * The AFTER_ASSERTION flag is intended to be used when the driver notices an + * assertion failure (at which point it is expected to perform a complete tear + * down and reinitialise), to allow both ports to reset the MC once in an + * atomic fashion. + * + * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, + * which means that they will automatically reboot out of the assertion + * handler, so this is in practise an optional operation. It is still + * recommended that drivers execute this to support custom firmwares with + * REBOOT_ON_ASSERT=0. + * + * Locks required: NONE Returns: Nothing. You get back a response with ERR=1, + * DATALEN=0 */ -#define MC_CMD_REBOOT 0x3d +#define MC_CMD_REBOOT 0x3d +#undef MC_CMD_0x3d_PRIVILEGE_CTG +#define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_REBOOT_IN msgrequest */ #define MC_CMD_REBOOT_IN_LEN 4 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ /* MC_CMD_REBOOT_OUT msgresponse */ #define MC_CMD_REBOOT_OUT_LEN 0 /***********************************/ -/* MC_CMD_SCHEDINFO - * Request scheduler info. +/* MC_CMD_SCHEDINFO + * Request scheduler info. Locks required: NONE. Returns: An array of + * (timeslice,maximum overrun), one for each thread, in ascending order of + * thread address. */ -#define MC_CMD_SCHEDINFO 0x3e +#define MC_CMD_SCHEDINFO 0x3e +#undef MC_CMD_0x3e_PRIVILEGE_CTG +#define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_SCHEDINFO_IN msgrequest */ #define MC_CMD_SCHEDINFO_IN_LEN 0 /* MC_CMD_SCHEDINFO_OUT msgresponse */ #define MC_CMD_SCHEDINFO_OUT_LENMIN 4 #define MC_CMD_SCHEDINFO_OUT_LENMAX 252 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 /***********************************/ -/* MC_CMD_REBOOT_MODE +/* MC_CMD_REBOOT_MODE + * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot + * mode to the specified value. Returns the old mode. */ -#define MC_CMD_REBOOT_MODE 0x3f +#define MC_CMD_REBOOT_MODE 0x3f +#undef MC_CMD_0x3f_PRIVILEGE_CTG +#define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_REBOOT_MODE_IN msgrequest */ #define MC_CMD_REBOOT_MODE_IN_LEN 4 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 -#define MC_CMD_REBOOT_MODE_NORMAL 0x0 /* enum */ -#define MC_CMD_REBOOT_MODE_SNAPPER 0x3 /* enum */ +/* enum: Normal. */ +#define MC_CMD_REBOOT_MODE_NORMAL 0x0 +/* enum: Power-on Reset. */ +#define MC_CMD_REBOOT_MODE_POR 0x2 +/* enum: Snapper. */ +#define MC_CMD_REBOOT_MODE_SNAPPER 0x3 +/* enum: snapper fake POR */ +#define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4 +#define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7 +#define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1 /* MC_CMD_REBOOT_MODE_OUT msgresponse */ #define MC_CMD_REBOOT_MODE_OUT_LEN 4 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 /***********************************/ -/* MC_CMD_SENSOR_INFO +/* MC_CMD_SENSOR_INFO * Returns information about every available sensor. + * + * Each sensor has a single (16bit) value, and a corresponding state. The + * mapping between value and state is nominally determined by the MC, but may + * be implemented using up to 2 ranges per sensor. + * + * This call returns a mask (32bit) of the sensors that are supported by this + * platform, then an array of sensor information structures, in order of sensor + * type (but without gaps for unimplemented sensors). Each structure defines + * the ranges for the corresponding sensor. An unused range is indicated by + * equal limit values. If one range is used, a value outside that range results + * in STATE_FATAL. If two ranges are used, a value outside the second range + * results in STATE_FATAL while a value outside the first and inside the second + * range results in STATE_WARNING. + * + * Sensor masks and sensor information arrays are organised into pages. For + * backward compatibility, older host software can only use sensors in page 0. + * Bit 32 in the sensor mask was previously unused, and is no reserved for use + * as the next page flag. + * + * If the request does not contain a PAGE value then firmware will only return + * page 0 of sensor information, with bit 31 in the sensor mask cleared. + * + * If the request contains a PAGE value then firmware responds with the sensor + * mask and sensor information array for that page of sensors. In this case bit + * 31 in the mask is set if another page exists. + * + * Locks required: None Returns: 0 */ -#define MC_CMD_SENSOR_INFO 0x41 +#define MC_CMD_SENSOR_INFO 0x41 +#undef MC_CMD_0x41_PRIVILEGE_CTG +#define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_SENSOR_INFO_IN msgrequest */ #define MC_CMD_SENSOR_INFO_IN_LEN 0 +/* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */ +#define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4 +/* Which page of sensors to report. + * + * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). + * + * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc. + */ +#define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0 + /* MC_CMD_SENSOR_INFO_OUT msgresponse */ -#define MC_CMD_SENSOR_INFO_OUT_LENMIN 12 +#define MC_CMD_SENSOR_INFO_OUT_LENMIN 4 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 -#define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 /* enum */ -#define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 /* enum */ -#define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 /* enum */ -#define MC_CMD_SENSOR_PHY0_TEMP 0x3 /* enum */ -#define MC_CMD_SENSOR_PHY0_COOLING 0x4 /* enum */ -#define MC_CMD_SENSOR_PHY1_TEMP 0x5 /* enum */ -#define MC_CMD_SENSOR_PHY1_COOLING 0x6 /* enum */ -#define MC_CMD_SENSOR_IN_1V0 0x7 /* enum */ -#define MC_CMD_SENSOR_IN_1V2 0x8 /* enum */ -#define MC_CMD_SENSOR_IN_1V8 0x9 /* enum */ -#define MC_CMD_SENSOR_IN_2V5 0xa /* enum */ -#define MC_CMD_SENSOR_IN_3V3 0xb /* enum */ -#define MC_CMD_SENSOR_IN_12V0 0xc /* enum */ -#define MC_CMD_SENSOR_IN_1V2A 0xd /* enum */ -#define MC_CMD_SENSOR_IN_VREF 0xe /* enum */ -#define MC_CMD_SENSOR_OUT_VAOE 0xf /* enum */ -#define MC_CMD_SENSOR_AOE_TEMP 0x10 /* enum */ -#define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 /* enum */ -#define MC_CMD_SENSOR_PSU_TEMP 0x12 /* enum */ -#define MC_CMD_SENSOR_FAN_0 0x13 /* enum */ -#define MC_CMD_SENSOR_FAN_1 0x14 /* enum */ -#define MC_CMD_SENSOR_FAN_2 0x15 /* enum */ -#define MC_CMD_SENSOR_FAN_3 0x16 /* enum */ -#define MC_CMD_SENSOR_FAN_4 0x17 /* enum */ -#define MC_CMD_SENSOR_IN_VAOE 0x18 /* enum */ -#define MC_CMD_SENSOR_OUT_IAOE 0x19 /* enum */ -#define MC_CMD_SENSOR_IN_IAOE 0x1a /* enum */ -#define MC_CMD_SENSOR_NIC_POWER 0x1b /* enum */ +/* enum: Controller temperature: degC */ +#define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 +/* enum: Phy common temperature: degC */ +#define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 +/* enum: Controller cooling: bool */ +#define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 +/* enum: Phy 0 temperature: degC */ +#define MC_CMD_SENSOR_PHY0_TEMP 0x3 +/* enum: Phy 0 cooling: bool */ +#define MC_CMD_SENSOR_PHY0_COOLING 0x4 +/* enum: Phy 1 temperature: degC */ +#define MC_CMD_SENSOR_PHY1_TEMP 0x5 +/* enum: Phy 1 cooling: bool */ +#define MC_CMD_SENSOR_PHY1_COOLING 0x6 +/* enum: 1.0v power: mV */ +#define MC_CMD_SENSOR_IN_1V0 0x7 +/* enum: 1.2v power: mV */ +#define MC_CMD_SENSOR_IN_1V2 0x8 +/* enum: 1.8v power: mV */ +#define MC_CMD_SENSOR_IN_1V8 0x9 +/* enum: 2.5v power: mV */ +#define MC_CMD_SENSOR_IN_2V5 0xa +/* enum: 3.3v power: mV */ +#define MC_CMD_SENSOR_IN_3V3 0xb +/* enum: 12v power: mV */ +#define MC_CMD_SENSOR_IN_12V0 0xc +/* enum: 1.2v analogue power: mV */ +#define MC_CMD_SENSOR_IN_1V2A 0xd +/* enum: reference voltage: mV */ +#define MC_CMD_SENSOR_IN_VREF 0xe +/* enum: AOE FPGA power: mV */ +#define MC_CMD_SENSOR_OUT_VAOE 0xf +/* enum: AOE FPGA temperature: degC */ +#define MC_CMD_SENSOR_AOE_TEMP 0x10 +/* enum: AOE FPGA PSU temperature: degC */ +#define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 +/* enum: AOE PSU temperature: degC */ +#define MC_CMD_SENSOR_PSU_TEMP 0x12 +/* enum: Fan 0 speed: RPM */ +#define MC_CMD_SENSOR_FAN_0 0x13 +/* enum: Fan 1 speed: RPM */ +#define MC_CMD_SENSOR_FAN_1 0x14 +/* enum: Fan 2 speed: RPM */ +#define MC_CMD_SENSOR_FAN_2 0x15 +/* enum: Fan 3 speed: RPM */ +#define MC_CMD_SENSOR_FAN_3 0x16 +/* enum: Fan 4 speed: RPM */ +#define MC_CMD_SENSOR_FAN_4 0x17 +/* enum: AOE FPGA input power: mV */ +#define MC_CMD_SENSOR_IN_VAOE 0x18 +/* enum: AOE FPGA current: mA */ +#define MC_CMD_SENSOR_OUT_IAOE 0x19 +/* enum: AOE FPGA input current: mA */ +#define MC_CMD_SENSOR_IN_IAOE 0x1a +/* enum: NIC power consumption: W */ +#define MC_CMD_SENSOR_NIC_POWER 0x1b +/* enum: 0.9v power voltage: mV */ +#define MC_CMD_SENSOR_IN_0V9 0x1c +/* enum: 0.9v power current: mA */ +#define MC_CMD_SENSOR_IN_I0V9 0x1d +/* enum: 1.2v power current: mA */ +#define MC_CMD_SENSOR_IN_I1V2 0x1e +/* enum: Not a sensor: reserved for the next page flag */ +#define MC_CMD_SENSOR_PAGE0_NEXT 0x1f +/* enum: 0.9v power voltage (at ADC): mV */ +#define MC_CMD_SENSOR_IN_0V9_ADC 0x20 +/* enum: Controller temperature 2: degC */ +#define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21 +/* enum: Voltage regulator internal temperature: degC */ +#define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22 +/* enum: 0.9V voltage regulator temperature: degC */ +#define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23 +/* enum: 1.2V voltage regulator temperature: degC */ +#define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24 +/* enum: controller internal temperature sensor voltage (internal ADC): mV */ +#define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25 +/* enum: controller internal temperature (internal ADC): degC */ +#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26 +/* enum: controller internal temperature sensor voltage (external ADC): mV */ +#define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27 +/* enum: controller internal temperature (external ADC): degC */ +#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28 +/* enum: ambient temperature: degC */ +#define MC_CMD_SENSOR_AMBIENT_TEMP 0x29 +/* enum: air flow: bool */ +#define MC_CMD_SENSOR_AIRFLOW 0x2a +/* enum: voltage between VSS08D and VSS08D at CSR: mV */ +#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b +/* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */ +#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c +/* enum: Hotpoint temperature: degC */ +#define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d +/* enum: Port 0 PHY power switch over-current: bool */ +#define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e +/* enum: Port 1 PHY power switch over-current: bool */ +#define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f +/* enum: Mop-up microcontroller reference voltage (millivolts) */ +#define MC_CMD_SENSOR_MUM_VCC 0x30 +/* enum: 0.9v power phase A voltage: mV */ +#define MC_CMD_SENSOR_IN_0V9_A 0x31 +/* enum: 0.9v power phase A current: mA */ +#define MC_CMD_SENSOR_IN_I0V9_A 0x32 +/* enum: 0.9V voltage regulator phase A temperature: degC */ +#define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33 +/* enum: 0.9v power phase B voltage: mV */ +#define MC_CMD_SENSOR_IN_0V9_B 0x34 +/* enum: 0.9v power phase B current: mA */ +#define MC_CMD_SENSOR_IN_I0V9_B 0x35 +/* enum: 0.9V voltage regulator phase B temperature: degC */ +#define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36 +/* enum: CCOM AVREG 1v2 supply (interval ADC): mV */ +#define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37 +/* enum: CCOM AVREG 1v2 supply (external ADC): mV */ +#define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38 +/* enum: CCOM AVREG 1v8 supply (interval ADC): mV */ +#define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39 +/* enum: CCOM AVREG 1v8 supply (external ADC): mV */ +#define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a +/* enum: Not a sensor: reserved for the next page flag */ +#define MC_CMD_SENSOR_PAGE1_NEXT 0x3f +/* enum: controller internal temperature sensor voltage on master core + * (internal ADC): mV + */ +#define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40 +/* enum: controller internal temperature on master core (internal ADC): degC */ +#define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41 +/* enum: controller internal temperature sensor voltage on master core + * (external ADC): mV + */ +#define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42 +/* enum: controller internal temperature on master core (external ADC): degC */ +#define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43 +/* enum: controller internal temperature on slave core sensor voltage (internal + * ADC): mV + */ +#define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44 +/* enum: controller internal temperature on slave core (internal ADC): degC */ +#define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45 +/* enum: controller internal temperature on slave core sensor voltage (external + * ADC): mV + */ +#define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46 +/* enum: controller internal temperature on slave core (external ADC): degC */ +#define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47 +/* enum: Voltage supplied to the SODIMMs from their power supply: mV */ +#define MC_CMD_SENSOR_SODIMM_VOUT 0x49 +/* enum: Temperature of SODIMM 0 (if installed): degC */ +#define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a +/* enum: Temperature of SODIMM 1 (if installed): degC */ +#define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b +/* enum: Voltage supplied to the QSFP #0 from their power supply: mV */ +#define MC_CMD_SENSOR_PHY0_VCC 0x4c +/* enum: Voltage supplied to the QSFP #1 from their power supply: mV */ +#define MC_CMD_SENSOR_PHY1_VCC 0x4d +/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ #define MC_CMD_SENSOR_ENTRY_OFST 4 #define MC_CMD_SENSOR_ENTRY_LEN 8 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8 -#define MC_CMD_SENSOR_ENTRY_MINNUM 1 +#define MC_CMD_SENSOR_ENTRY_MINNUM 0 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31 +/* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */ +#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4 +#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252 +#define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num)) +#define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0 +/* Enum values, see field(s): */ +/* MC_CMD_SENSOR_INFO_OUT */ +#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31 +#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1 +/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ +/* MC_CMD_SENSOR_ENTRY_OFST 4 */ +/* MC_CMD_SENSOR_ENTRY_LEN 8 */ +/* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */ +/* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */ +/* MC_CMD_SENSOR_ENTRY_MINNUM 0 */ +/* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */ + /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 /***********************************/ -/* MC_CMD_READ_SENSORS - * Returns the current reading from each sensor. +/* MC_CMD_READ_SENSORS + * Returns the current reading from each sensor. DMAs an array of sensor + * readings, in order of sensor type (but without gaps for unimplemented + * sensors), into host memory. Each array element is a + * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword. + * + * If the request does not contain the LENGTH field then only sensors 0 to 30 + * are reported, to avoid DMA buffer overflow in older host software. If the + * sensor reading require more space than the LENGTH allows, then return + * EINVAL. + * + * The MC will send a SENSOREVT event every time any sensor changes state. The + * driver is responsible for ensuring that it doesn't miss any events. The + * board will function normally if all sensors are in STATE_OK or + * STATE_WARNING. Otherwise the board should not be expected to function. */ -#define MC_CMD_READ_SENSORS 0x42 +#define MC_CMD_READ_SENSORS 0x42 +#undef MC_CMD_0x42_PRIVILEGE_CTG +#define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_READ_SENSORS_IN msgrequest */ #define MC_CMD_READ_SENSORS_IN_LEN 8 +/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 +/* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ +#define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 +/* DMA address of host buffer for sensor readings */ +#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 +#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 +#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 +#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4 +/* Size in bytes of host buffer. */ +#define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8 + /* MC_CMD_READ_SENSORS_OUT msgresponse */ #define MC_CMD_READ_SENSORS_OUT_LEN 0 +/* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */ +#define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0 + /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ -#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 3 +#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 -#define MC_CMD_SENSOR_STATE_OK 0x0 /* enum */ -#define MC_CMD_SENSOR_STATE_WARNING 0x1 /* enum */ -#define MC_CMD_SENSOR_STATE_FATAL 0x2 /* enum */ -#define MC_CMD_SENSOR_STATE_BROKEN 0x3 /* enum */ +/* enum: Ok. */ +#define MC_CMD_SENSOR_STATE_OK 0x0 +/* enum: Breached warning threshold. */ +#define MC_CMD_SENSOR_STATE_WARNING 0x1 +/* enum: Breached fatal threshold. */ +#define MC_CMD_SENSOR_STATE_FATAL 0x2 +/* enum: Fault with sensor. */ +#define MC_CMD_SENSOR_STATE_BROKEN 0x3 +/* enum: Sensor is working but does not currently have a reading. */ +#define MC_CMD_SENSOR_STATE_NO_READING 0x4 +/* enum: Sensor initialisation failed. */ +#define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 +#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3 +#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1 +/* Enum values, see field(s): */ +/* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ +#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24 +#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8 /***********************************/ -/* MC_CMD_GET_PHY_STATE - * Report current state of PHY. +/* MC_CMD_GET_PHY_STATE + * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot + * (e.g. due to missing or corrupted firmware). Locks required: None. Return + * code: 0 */ -#define MC_CMD_GET_PHY_STATE 0x43 +#define MC_CMD_GET_PHY_STATE 0x43 +#undef MC_CMD_0x43_PRIVILEGE_CTG +#define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_GET_PHY_STATE_IN msgrequest */ #define MC_CMD_GET_PHY_STATE_IN_LEN 0 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */ #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 -#define MC_CMD_PHY_STATE_OK 0x1 /* enum */ -#define MC_CMD_PHY_STATE_ZOMBIE 0x2 /* enum */ +/* enum: Ok. */ +#define MC_CMD_PHY_STATE_OK 0x1 +/* enum: Faulty. */ +#define MC_CMD_PHY_STATE_ZOMBIE 0x2 /***********************************/ -/* MC_CMD_SETUP_8021QBB - * 802.1Qbb control. +/* MC_CMD_SETUP_8021QBB + * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to + * disable 802.Qbb for a given priority. */ -#define MC_CMD_SETUP_8021QBB 0x44 +#define MC_CMD_SETUP_8021QBB 0x44 /* MC_CMD_SETUP_8021QBB_IN msgrequest */ #define MC_CMD_SETUP_8021QBB_IN_LEN 32 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 /***********************************/ -/* MC_CMD_WOL_FILTER_GET - * Retrieve ID of any WoL filters. +/* MC_CMD_WOL_FILTER_GET + * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS */ -#define MC_CMD_WOL_FILTER_GET 0x45 +#define MC_CMD_WOL_FILTER_GET 0x45 +#undef MC_CMD_0x45_PRIVILEGE_CTG +#define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK + /* MC_CMD_WOL_FILTER_GET_IN msgrequest */ #define MC_CMD_WOL_FILTER_GET_IN_LEN 0 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 /***********************************/ -/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD - * Add a protocol offload to NIC for lights-out state. +/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD + * Add a protocol offload to NIC for lights-out state. Locks required: None. + * Returns: 0, ENOSYS */ -#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 +#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 +#undef MC_CMD_0x46_PRIVILEGE_CTG +#define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK + /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 /***********************************/ -/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD - * Remove a protocol offload from NIC for lights-out state. +/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD + * Remove a protocol offload from NIC for lights-out state. Locks required: + * None. Returns: 0, ENOSYS */ -#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 +#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 +#undef MC_CMD_0x47_PRIVILEGE_CTG +#define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK + /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 /***********************************/ -/* MC_CMD_MAC_RESET_RESTORE - * Restore MAC after block reset. +/* MC_CMD_MAC_RESET_RESTORE + * Restore MAC after block reset. Locks required: None. Returns: 0. */ -#define MC_CMD_MAC_RESET_RESTORE 0x48 +#define MC_CMD_MAC_RESET_RESTORE 0x48 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 /***********************************/ -/* MC_CMD_TESTASSERT +/* MC_CMD_TESTASSERT + * Deliberately trigger an assert-detonation in the firmware for testing + * purposes (i.e. to allow tests that the driver copes gracefully). Locks + * required: None Returns: 0 */ -#define MC_CMD_TESTASSERT 0x49 +#define MC_CMD_TESTASSERT 0x49 +#undef MC_CMD_0x49_PRIVILEGE_CTG +#define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_TESTASSERT_IN msgrequest */ #define MC_CMD_TESTASSERT_IN_LEN 0 /* MC_CMD_TESTASSERT_OUT msgresponse */ #define MC_CMD_TESTASSERT_OUT_LEN 0 /***********************************/ -/* MC_CMD_WORKAROUND - * Enable/Disable a given workaround. +/* MC_CMD_WORKAROUND + * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't + * understand the given workaround number - which should not be treated as a + * hard error by client code. This op does not imply any semantics about each + * workaround, that's between the driver and the mcfw on a per-workaround + * basis. Locks required: None. Returns: 0, EINVAL . */ -#define MC_CMD_WORKAROUND 0x4a +#define MC_CMD_WORKAROUND 0x4a +#undef MC_CMD_0x4a_PRIVILEGE_CTG +#define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_WORKAROUND_IN msgrequest */ #define MC_CMD_WORKAROUND_IN_LEN 8 +/* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */ #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 -#define MC_CMD_WORKAROUND_BUG17230 0x1 /* enum */ +/* enum: Bug 17230 work around. */ +#define MC_CMD_WORKAROUND_BUG17230 0x1 +/* enum: Bug 35388 work around (unsafe EVQ writes). */ +#define MC_CMD_WORKAROUND_BUG35388 0x2 +/* enum: Bug35017 workaround (A64 tables must be identity map) */ +#define MC_CMD_WORKAROUND_BUG35017 0x3 +/* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ +#define MC_CMD_WORKAROUND_BUG41750 0x4 +/* enum: Bug 42008 present (Interrupts can overtake associated events). Caution + * - before adding code that queries this workaround, remember that there's + * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, + * and will hence (incorrectly) report that the bug doesn't exist. + */ +#define MC_CMD_WORKAROUND_BUG42008 0x5 +/* enum: Bug 26807 features present in firmware (multicast filter chaining) + * This feature cannot be turned on/off while there are any filters already + * present. The behaviour in such case depends on the acting client's privilege + * level. If the client has the admin privilege, then all functions that have + * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise + * the command will fail with MC_CMD_ERR_FILTERS_PRESENT. + */ +#define MC_CMD_WORKAROUND_BUG26807 0x6 +/* 0 = disable the workaround indicated by TYPE; any non-zero value = enable + * the workaround + */ #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 /* MC_CMD_WORKAROUND_OUT msgresponse */ #define MC_CMD_WORKAROUND_OUT_LEN 0 +/* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used + * when (TYPE == MC_CMD_WORKAROUND_BUG26807) + */ +#define MC_CMD_WORKAROUND_EXT_OUT_LEN 4 +#define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0 +#define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0 +#define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1 + /***********************************/ -/* MC_CMD_GET_PHY_MEDIA_INFO - * Read media-specific data from PHY. +/* MC_CMD_GET_PHY_MEDIA_INFO + * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for + * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG + * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the + * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1 + * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80. + * Anything else: currently undefined. Locks required: None. Return code: 0. */ -#define MC_CMD_GET_PHY_MEDIA_INFO 0x4b +#define MC_CMD_GET_PHY_MEDIA_INFO 0x4b +#undef MC_CMD_0x4b_PRIVILEGE_CTG +#define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */ #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num)) +/* in bytes */ #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248 /***********************************/ -/* MC_CMD_NVRAM_TEST - * Test a particular NVRAM partition. +/* MC_CMD_NVRAM_TEST + * Test a particular NVRAM partition for valid contents (where "valid" depends + * on the type of partition). */ -#define MC_CMD_NVRAM_TEST 0x4c +#define MC_CMD_NVRAM_TEST 0x4c +#undef MC_CMD_0x4c_PRIVILEGE_CTG +#define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_NVRAM_TEST_IN msgrequest */ #define MC_CMD_NVRAM_TEST_IN_LEN 4 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 /* Enum values, see field(s): */ /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ /* MC_CMD_NVRAM_TEST_OUT msgresponse */ #define MC_CMD_NVRAM_TEST_OUT_LEN 4 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 -#define MC_CMD_NVRAM_TEST_PASS 0x0 /* enum */ -#define MC_CMD_NVRAM_TEST_FAIL 0x1 /* enum */ -#define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 /* enum */ +/* enum: Passed. */ +#define MC_CMD_NVRAM_TEST_PASS 0x0 +/* enum: Failed. */ +#define MC_CMD_NVRAM_TEST_FAIL 0x1 +/* enum: Not supported. */ +#define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 /***********************************/ -/* MC_CMD_MRSFP_TWEAK - * Read status and/or set parameters for the 'mrsfp' driver. +/* MC_CMD_MRSFP_TWEAK + * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds. + * I2C I/O expander bits are always read; if equaliser parameters are supplied, + * they are configured first. Locks required: None. Return code: 0, EINVAL. */ -#define MC_CMD_MRSFP_TWEAK 0x4d +#define MC_CMD_MRSFP_TWEAK 0x4d /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 +/* 0-6 low->high de-emph. */ #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 +/* 0-8 low->high ref.V */ #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 +/* 0-8 0-8 low->high boost */ #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 +/* 0-8 low->high ref.V */ #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 +/* input bits */ #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 +/* output bits */ #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 +/* direction */ #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 -#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 /* enum */ -#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 /* enum */ +/* enum: Out. */ +#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 +/* enum: In. */ +#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 /***********************************/ -/* MC_CMD_SENSOR_SET_LIMS - * Adjusts the sensor limits. +/* MC_CMD_SENSOR_SET_LIMS + * Adjusts the sensor limits. This is a warranty-voiding operation. Returns: + * ENOENT if the sensor specified does not exist, EINVAL if the limits are out + * of range. */ -#define MC_CMD_SENSOR_SET_LIMS 0x4e +#define MC_CMD_SENSOR_SET_LIMS 0x4e +#undef MC_CMD_0x4e_PRIVILEGE_CTG +#define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 /* Enum values, see field(s): */ /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ +/* interpretation is is sensor-specific. */ #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 +/* interpretation is is sensor-specific. */ #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 +/* interpretation is is sensor-specific. */ #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 +/* interpretation is is sensor-specific. */ #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 /***********************************/ -/* MC_CMD_GET_RESOURCE_LIMITS +/* MC_CMD_GET_RESOURCE_LIMITS */ -#define MC_CMD_GET_RESOURCE_LIMITS 0x4f +#define MC_CMD_GET_RESOURCE_LIMITS 0x4f /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 /***********************************/ -/* MC_CMD_CLP - * CLP support operations +/* MC_CMD_NVRAM_PARTITIONS + * Reads the list of available virtual NVRAM partition types. Locks required: + * none. Returns: 0, EINVAL (bad type). */ -#define MC_CMD_CLP 0x56 +#define MC_CMD_NVRAM_PARTITIONS 0x51 +#undef MC_CMD_0x51_PRIVILEGE_CTG +#define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */ +#define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0 + +/* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */ +#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4 +#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252 +#define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num)) +/* total number of partitions */ +#define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0 +/* type ID code for each of NUM_PARTITIONS partitions */ +#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4 +#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4 +#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0 +#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62 + + +/***********************************/ +/* MC_CMD_NVRAM_METADATA + * Reads soft metadata for a virtual NVRAM partition type. Locks required: + * none. Returns: 0, EINVAL (bad type). + */ +#define MC_CMD_NVRAM_METADATA 0x52 +#undef MC_CMD_0x52_PRIVILEGE_CTG + +#define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_NVRAM_METADATA_IN msgrequest */ +#define MC_CMD_NVRAM_METADATA_IN_LEN 4 +/* Partition type ID code */ +#define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0 + +/* MC_CMD_NVRAM_METADATA_OUT msgresponse */ +#define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20 +#define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252 +#define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num)) +/* Partition type ID code */ +#define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0 +#define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4 +#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0 +#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1 +#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1 +#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1 +#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2 +#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1 +/* Subtype ID code for content of this partition */ +#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8 +/* 1st component of W.X.Y.Z version number for content of this partition */ +#define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12 +#define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2 +/* 2nd component of W.X.Y.Z version number for content of this partition */ +#define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14 +#define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2 +/* 3rd component of W.X.Y.Z version number for content of this partition */ +#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16 +#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2 +/* 4th component of W.X.Y.Z version number for content of this partition */ +#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18 +#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2 +/* Zero-terminated string describing the content of this partition */ +#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20 +#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1 +#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0 +#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232 + + +/***********************************/ +/* MC_CMD_GET_MAC_ADDRESSES + * Returns the base MAC, count and stride for the requesting function + */ +#define MC_CMD_GET_MAC_ADDRESSES 0x55 +#undef MC_CMD_0x55_PRIVILEGE_CTG + +#define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */ +#define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0 + +/* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */ +#define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16 +/* Base MAC address */ +#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0 +#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6 +/* Padding */ +#define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6 +#define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2 +/* Number of allocated MAC addresses */ +#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8 +/* Spacing of allocated MAC addresses */ +#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12 + + +/***********************************/ +/* MC_CMD_CLP + * Perform a CLP related operation + */ +#define MC_CMD_CLP 0x56 +#undef MC_CMD_0x56_PRIVILEGE_CTG + +#define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_CLP_IN msgrequest */ #define MC_CMD_CLP_IN_LEN 4 +/* Sub operation */ #define MC_CMD_CLP_IN_OP_OFST 0 -#define MC_CMD_CLP_OP_DEFAULT 0x1 /* enum */ -#define MC_CMD_CLP_OP_SET_MAC 0x2 /* enum */ -#define MC_CMD_CLP_OP_GET_MAC 0x3 /* enum */ -#define MC_CMD_CLP_OP_SET_BOOT 0x4 /* enum */ -#define MC_CMD_CLP_OP_GET_BOOT 0x5 /* enum */ +/* enum: Return to factory default settings */ +#define MC_CMD_CLP_OP_DEFAULT 0x1 +/* enum: Set MAC address */ +#define MC_CMD_CLP_OP_SET_MAC 0x2 +/* enum: Get MAC address */ +#define MC_CMD_CLP_OP_GET_MAC 0x3 +/* enum: Set UEFI/GPXE boot mode */ +#define MC_CMD_CLP_OP_SET_BOOT 0x4 +/* enum: Get UEFI/GPXE boot mode */ +#define MC_CMD_CLP_OP_GET_BOOT 0x5 /* MC_CMD_CLP_OUT msgresponse */ #define MC_CMD_CLP_OUT_LEN 0 /* MC_CMD_CLP_IN_DEFAULT msgrequest */ #define MC_CMD_CLP_IN_DEFAULT_LEN 4 /* MC_CMD_CLP_IN_OP_OFST 0 */ /* MC_CMD_CLP_OUT_DEFAULT msgresponse */ #define MC_CMD_CLP_OUT_DEFAULT_LEN 0 /* MC_CMD_CLP_IN_SET_MAC msgrequest */ #define MC_CMD_CLP_IN_SET_MAC_LEN 12 /* MC_CMD_CLP_IN_OP_OFST 0 */ +/* MAC address assigned to port */ #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4 #define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6 +/* Padding */ #define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2 /* MC_CMD_CLP_OUT_SET_MAC msgresponse */ #define MC_CMD_CLP_OUT_SET_MAC_LEN 0 /* MC_CMD_CLP_IN_GET_MAC msgrequest */ #define MC_CMD_CLP_IN_GET_MAC_LEN 4 /* MC_CMD_CLP_IN_OP_OFST 0 */ /* MC_CMD_CLP_OUT_GET_MAC msgresponse */ #define MC_CMD_CLP_OUT_GET_MAC_LEN 8 +/* MAC address assigned to port */ #define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6 +/* Padding */ #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2 /* MC_CMD_CLP_IN_SET_BOOT msgrequest */ #define MC_CMD_CLP_IN_SET_BOOT_LEN 5 /* MC_CMD_CLP_IN_OP_OFST 0 */ +/* Boot flag */ #define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1 /* MC_CMD_CLP_OUT_SET_BOOT msgresponse */ #define MC_CMD_CLP_OUT_SET_BOOT_LEN 0 /* MC_CMD_CLP_IN_GET_BOOT msgrequest */ #define MC_CMD_CLP_IN_GET_BOOT_LEN 4 /* MC_CMD_CLP_IN_OP_OFST 0 */ /* MC_CMD_CLP_OUT_GET_BOOT msgresponse */ #define MC_CMD_CLP_OUT_GET_BOOT_LEN 4 +/* Boot flag */ #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1 +/* Padding */ #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3 + +/***********************************/ +/* MC_CMD_MUM + * Perform a MUM operation + */ +#define MC_CMD_MUM 0x57 +#undef MC_CMD_0x57_PRIVILEGE_CTG + +#define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_MUM_IN msgrequest */ +#define MC_CMD_MUM_IN_LEN 4 +#define MC_CMD_MUM_IN_OP_HDR_OFST 0 +#define MC_CMD_MUM_IN_OP_LBN 0 +#define MC_CMD_MUM_IN_OP_WIDTH 8 +/* enum: NULL MCDI command to MUM */ +#define MC_CMD_MUM_OP_NULL 0x1 +/* enum: Get MUM version */ +#define MC_CMD_MUM_OP_GET_VERSION 0x2 +/* enum: Issue raw I2C command to MUM */ +#define MC_CMD_MUM_OP_RAW_CMD 0x3 +/* enum: Read from registers on devices connected to MUM. */ +#define MC_CMD_MUM_OP_READ 0x4 +/* enum: Write to registers on devices connected to MUM. */ +#define MC_CMD_MUM_OP_WRITE 0x5 +/* enum: Control UART logging. */ +#define MC_CMD_MUM_OP_LOG 0x6 +/* enum: Operations on MUM GPIO lines */ +#define MC_CMD_MUM_OP_GPIO 0x7 +/* enum: Get sensor readings from MUM */ +#define MC_CMD_MUM_OP_READ_SENSORS 0x8 +/* enum: Initiate clock programming on the MUM */ +#define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9 +/* enum: Initiate FPGA load from flash on the MUM */ +#define MC_CMD_MUM_OP_FPGA_LOAD 0xa +/* enum: Request sensor reading from MUM ADC resulting from earlier request via + * MUM ATB + */ +#define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb +/* enum: Send commands relating to the QSFP ports via the MUM for PHY + * operations + */ +#define MC_CMD_MUM_OP_QSFP 0xc + +/* MC_CMD_MUM_IN_NULL msgrequest */ +#define MC_CMD_MUM_IN_NULL_LEN 4 +/* MUM cmd header */ +#define MC_CMD_MUM_IN_CMD_OFST 0 + +/* MC_CMD_MUM_IN_GET_VERSION msgrequest */ +#define MC_CMD_MUM_IN_GET_VERSION_LEN 4 +/* MUM cmd header */ +/* MC_CMD_MUM_IN_CMD_OFST 0 */ + +/* MC_CMD_MUM_IN_READ msgrequest */ +#define MC_CMD_MUM_IN_READ_LEN 16 +/* MUM cmd header */ +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +/* ID of (device connected to MUM) to read from registers of */ +#define MC_CMD_MUM_IN_READ_DEVICE_OFST 4 +/* enum: Hittite HMC1035 clock generator on Sorrento board */ +#define MC_CMD_MUM_DEV_HITTITE 0x1 +/* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */ +#define MC_CMD_MUM_DEV_HITTITE_NIC 0x2 +/* 32-bit address to read from */ +#define MC_CMD_MUM_IN_READ_ADDR_OFST 8 +/* Number of words to read. */ +#define MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12 + +/* MC_CMD_MUM_IN_WRITE msgrequest */ +#define MC_CMD_MUM_IN_WRITE_LENMIN 16 +#define MC_CMD_MUM_IN_WRITE_LENMAX 252 +#define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num)) +/* MUM cmd header */ +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +/* ID of (device connected to MUM) to write to registers of */ +#define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4 +/* enum: Hittite HMC1035 clock generator on Sorrento board */ +/* MC_CMD_MUM_DEV_HITTITE 0x1 */ +/* 32-bit address to write to */ +#define MC_CMD_MUM_IN_WRITE_ADDR_OFST 8 +/* Words to write */ +#define MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12 +#define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4 +#define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1 +#define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60 + +/* MC_CMD_MUM_IN_RAW_CMD msgrequest */ +#define MC_CMD_MUM_IN_RAW_CMD_LENMIN 17 +#define MC_CMD_MUM_IN_RAW_CMD_LENMAX 252 +#define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num)) +/* MUM cmd header */ +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +/* MUM I2C cmd code */ +#define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4 +/* Number of bytes to write */ +#define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8 +/* Number of bytes to read */ +#define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12 +/* Bytes to write */ +#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16 +#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1 +#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1 +#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236 + +/* MC_CMD_MUM_IN_LOG msgrequest */ +#define MC_CMD_MUM_IN_LOG_LEN 8 +/* MUM cmd header */ +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +#define MC_CMD_MUM_IN_LOG_OP_OFST 4 +#define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */ + +/* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */ +#define MC_CMD_MUM_IN_LOG_OP_UART_LEN 12 +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +/* MC_CMD_MUM_IN_LOG_OP_OFST 4 */ +/* Enable/disable debug output to UART */ +#define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8 + +/* MC_CMD_MUM_IN_GPIO msgrequest */ +#define MC_CMD_MUM_IN_GPIO_LEN 8 +/* MUM cmd header */ +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +#define MC_CMD_MUM_IN_GPIO_HDR_OFST 4 +#define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0 +#define MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8 +#define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */ +#define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */ +#define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */ +#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */ +#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */ +#define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */ + +/* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */ +#define MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8 +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +#define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4 + +/* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */ +#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16 +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4 +/* The first 32-bit word to be written to the GPIO OUT register. */ +#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8 +/* The second 32-bit word to be written to the GPIO OUT register. */ +#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12 + +/* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */ +#define MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8 +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +#define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4 + +/* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */ +#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16 +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4 +/* The first 32-bit word to be written to the GPIO OUT ENABLE register. */ +#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8 +/* The second 32-bit word to be written to the GPIO OUT ENABLE register. */ +#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12 + +/* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */ +#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8 +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4 + +/* MC_CMD_MUM_IN_GPIO_OP msgrequest */ +#define MC_CMD_MUM_IN_GPIO_OP_LEN 8 +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +#define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4 +#define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8 +#define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8 +#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */ +#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */ +#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */ +#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */ +#define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16 +#define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8 + +/* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */ +#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8 +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4 + +/* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */ +#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8 +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4 +#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24 +#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8 + +/* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */ +#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8 +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4 +#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24 +#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8 + +/* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */ +#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8 +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4 +#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24 +#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8 + +/* MC_CMD_MUM_IN_READ_SENSORS msgrequest */ +#define MC_CMD_MUM_IN_READ_SENSORS_LEN 8 +/* MUM cmd header */ +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +#define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4 +#define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0 +#define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8 +#define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8 +#define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8 + +/* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */ +#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12 +/* MUM cmd header */ +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +/* Bit-mask of clocks to be programmed */ +#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4 +#define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */ +#define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */ +#define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */ +/* Control flags for clock programming */ +#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8 +#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0 +#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1 + +/* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */ +#define MC_CMD_MUM_IN_FPGA_LOAD_LEN 8 +/* MUM cmd header */ +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +/* Enable/Disable FPGA config from flash */ +#define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4 + +/* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */ +#define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4 +/* MUM cmd header */ +/* MC_CMD_MUM_IN_CMD_OFST 0 */ + +/* MC_CMD_MUM_IN_QSFP msgrequest */ +#define MC_CMD_MUM_IN_QSFP_LEN 12 +/* MUM cmd header */ +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +#define MC_CMD_MUM_IN_QSFP_HDR_OFST 4 +#define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0 +#define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4 +#define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */ +#define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */ +#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */ +#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */ +#define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */ +#define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */ +#define MC_CMD_MUM_IN_QSFP_IDX_OFST 8 + +/* MC_CMD_MUM_IN_QSFP_INIT msgrequest */ +#define MC_CMD_MUM_IN_QSFP_INIT_LEN 16 +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +#define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4 +#define MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8 +#define MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12 + +/* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */ +#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24 +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4 +#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8 +#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12 +#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16 +#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20 + +/* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */ +#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12 +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4 +#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8 + +/* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */ +#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16 +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4 +#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8 +#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12 + +/* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */ +#define MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12 +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +#define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4 +#define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8 + +/* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */ +#define MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12 +/* MC_CMD_MUM_IN_CMD_OFST 0 */ +#define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4 +#define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8 + +/* MC_CMD_MUM_OUT msgresponse */ +#define MC_CMD_MUM_OUT_LEN 0 + +/* MC_CMD_MUM_OUT_NULL msgresponse */ +#define MC_CMD_MUM_OUT_NULL_LEN 0 + +/* MC_CMD_MUM_OUT_GET_VERSION msgresponse */ +#define MC_CMD_MUM_OUT_GET_VERSION_LEN 12 +#define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0 +#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4 +#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8 +#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4 +#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8 + +/* MC_CMD_MUM_OUT_RAW_CMD msgresponse */ +#define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1 +#define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252 +#define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num)) +/* returned data */ +#define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0 +#define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1 +#define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1 +#define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252 + +/* MC_CMD_MUM_OUT_READ msgresponse */ +#define MC_CMD_MUM_OUT_READ_LENMIN 4 +#define MC_CMD_MUM_OUT_READ_LENMAX 252 +#define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num)) +#define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0 +#define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4 +#define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1 +#define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63 + +/* MC_CMD_MUM_OUT_WRITE msgresponse */ +#define MC_CMD_MUM_OUT_WRITE_LEN 0 + +/* MC_CMD_MUM_OUT_LOG msgresponse */ +#define MC_CMD_MUM_OUT_LOG_LEN 0 + +/* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */ +#define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0 + +/* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */ +#define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8 +/* The first 32-bit word read from the GPIO IN register. */ +#define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0 +/* The second 32-bit word read from the GPIO IN register. */ +#define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4 + +/* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */ +#define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0 + +/* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */ +#define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8 +/* The first 32-bit word read from the GPIO OUT register. */ +#define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0 +/* The second 32-bit word read from the GPIO OUT register. */ +#define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4 + +/* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */ +#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0 + +/* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */ +#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8 +#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0 +#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4 + +/* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */ +#define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4 +#define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0 + +/* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */ +#define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0 + +/* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */ +#define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0 + +/* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */ +#define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0 + +/* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */ +#define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4 +#define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252 +#define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num)) +#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0 +#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4 +#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1 +#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63 +#define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0 +#define MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16 +#define MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16 +#define MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8 +#define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24 +#define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8 + +/* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */ +#define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4 +#define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0 + +/* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */ +#define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0 + +/* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */ +#define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4 +#define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0 + +/* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */ +#define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0 + +/* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */ +#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8 +#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0 +#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4 +#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0 +#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1 +#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1 +#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1 + +/* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */ +#define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4 +#define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0 + +/* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */ +#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5 +#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252 +#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num)) +/* in bytes */ +#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0 +#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4 +#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1 +#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1 +#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248 + +/* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */ +#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8 +#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0 +#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4 + +/* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */ +#define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4 +#define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0 + /* MC_CMD_RESOURCE_SPECIFIER enum */ -#define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff /* enum */ -#define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe /* enum */ +/* enum: Any */ +#define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff +/* enum: None */ +#define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe +/* EVB_PORT_ID structuredef */ +#define EVB_PORT_ID_LEN 4 +#define EVB_PORT_ID_PORT_ID_OFST 0 +/* enum: An invalid port handle. */ +#define EVB_PORT_ID_NULL 0x0 +/* enum: The port assigned to this function.. */ +#define EVB_PORT_ID_ASSIGNED 0x1000000 +/* enum: External network port 0 */ +#define EVB_PORT_ID_MAC0 0x2000000 +/* enum: External network port 1 */ +#define EVB_PORT_ID_MAC1 0x2000001 +/* enum: External network port 2 */ +#define EVB_PORT_ID_MAC2 0x2000002 +/* enum: External network port 3 */ +#define EVB_PORT_ID_MAC3 0x2000003 +#define EVB_PORT_ID_PORT_ID_LBN 0 +#define EVB_PORT_ID_PORT_ID_WIDTH 32 +/* EVB_VLAN_TAG structuredef */ +#define EVB_VLAN_TAG_LEN 2 +/* The VLAN tag value */ +#define EVB_VLAN_TAG_VLAN_ID_LBN 0 +#define EVB_VLAN_TAG_VLAN_ID_WIDTH 12 +#define EVB_VLAN_TAG_MODE_LBN 12 +#define EVB_VLAN_TAG_MODE_WIDTH 4 +/* enum: Insert the VLAN. */ +#define EVB_VLAN_TAG_INSERT 0x0 +/* enum: Replace the VLAN if already present. */ +#define EVB_VLAN_TAG_REPLACE 0x1 + +/* BUFTBL_ENTRY structuredef */ +#define BUFTBL_ENTRY_LEN 12 +/* the owner ID */ +#define BUFTBL_ENTRY_OID_OFST 0 +#define BUFTBL_ENTRY_OID_LEN 2 +#define BUFTBL_ENTRY_OID_LBN 0 +#define BUFTBL_ENTRY_OID_WIDTH 16 +/* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */ +#define BUFTBL_ENTRY_PGSZ_OFST 2 +#define BUFTBL_ENTRY_PGSZ_LEN 2 +#define BUFTBL_ENTRY_PGSZ_LBN 16 +#define BUFTBL_ENTRY_PGSZ_WIDTH 16 +/* the raw 64-bit address field from the SMC, not adjusted for page size */ +#define BUFTBL_ENTRY_RAWADDR_OFST 4 +#define BUFTBL_ENTRY_RAWADDR_LEN 8 +#define BUFTBL_ENTRY_RAWADDR_LO_OFST 4 +#define BUFTBL_ENTRY_RAWADDR_HI_OFST 8 +#define BUFTBL_ENTRY_RAWADDR_LBN 32 +#define BUFTBL_ENTRY_RAWADDR_WIDTH 64 + +/* NVRAM_PARTITION_TYPE structuredef */ +#define NVRAM_PARTITION_TYPE_LEN 2 +#define NVRAM_PARTITION_TYPE_ID_OFST 0 +#define NVRAM_PARTITION_TYPE_ID_LEN 2 +/* enum: Primary MC firmware partition */ +#define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100 +/* enum: Secondary MC firmware partition */ +#define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200 +/* enum: Expansion ROM partition */ +#define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300 +/* enum: Static configuration TLV partition */ +#define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400 +/* enum: Dynamic configuration TLV partition */ +#define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500 +/* enum: Expansion ROM configuration data for port 0 */ +#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600 +/* enum: Expansion ROM configuration data for port 1 */ +#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601 +/* enum: Expansion ROM configuration data for port 2 */ +#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602 +/* enum: Expansion ROM configuration data for port 3 */ +#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603 +/* enum: Non-volatile log output partition */ +#define NVRAM_PARTITION_TYPE_LOG 0x700 +/* enum: Device state dump output partition */ +#define NVRAM_PARTITION_TYPE_DUMP 0x800 +/* enum: Application license key storage partition */ +#define NVRAM_PARTITION_TYPE_LICENSE 0x900 +/* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */ +#define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00 +/* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */ +#define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff +/* enum: Primary FPGA partition */ +#define NVRAM_PARTITION_TYPE_FPGA 0xb00 +/* enum: Secondary FPGA partition */ +#define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01 +/* enum: FC firmware partition */ +#define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02 +/* enum: FC License partition */ +#define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03 +/* enum: Non-volatile log output partition for FC */ +#define NVRAM_PARTITION_TYPE_FC_LOG 0xb04 +/* enum: MUM firmware partition */ +#define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00 +/* enum: MUM Non-volatile log output partition. */ +#define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01 +/* enum: MUM Application table partition. */ +#define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02 +/* enum: MUM boot rom partition. */ +#define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03 +/* enum: MUM production signatures & calibration rom partition. */ +#define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04 +/* enum: MUM user signatures & calibration rom partition. */ +#define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05 +/* enum: MUM fuses and lockbits partition. */ +#define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06 +/* enum: Start of reserved value range (firmware may use for any purpose) */ +#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00 +/* enum: End of reserved value range (firmware may use for any purpose) */ +#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd +/* enum: Recovery partition map (provided if real map is missing or corrupt) */ +#define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe +/* enum: Partition map (real map as stored in flash) */ +#define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff +#define NVRAM_PARTITION_TYPE_ID_LBN 0 +#define NVRAM_PARTITION_TYPE_ID_WIDTH 16 + +/* LICENSED_APP_ID structuredef */ +#define LICENSED_APP_ID_LEN 4 +#define LICENSED_APP_ID_ID_OFST 0 +/* enum: OpenOnload */ +#define LICENSED_APP_ID_ONLOAD 0x1 +/* enum: PTP timestamping */ +#define LICENSED_APP_ID_PTP 0x2 +/* enum: SolarCapture Pro */ +#define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4 +/* enum: SolarSecure filter engine */ +#define LICENSED_APP_ID_SOLARSECURE 0x8 +/* enum: Performance monitor */ +#define LICENSED_APP_ID_PERF_MONITOR 0x10 +/* enum: SolarCapture Live */ +#define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20 +/* enum: Capture SolarSystem */ +#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40 +/* enum: Network Access Control */ +#define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80 +#define LICENSED_APP_ID_ID_LBN 0 +#define LICENSED_APP_ID_ID_WIDTH 32 + +/* TX_TIMESTAMP_EVENT structuredef */ +#define TX_TIMESTAMP_EVENT_LEN 6 +/* lower 16 bits of timestamp data */ +#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0 +#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2 +#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0 +#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16 +/* Type of TX event, ordinary TX completion, low or high part of TX timestamp + */ +#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3 +#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1 +/* enum: This is a TX completion event, not a timestamp */ +#define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0 +/* enum: This is the low part of a TX timestamp event */ +#define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51 +/* enum: This is the high part of a TX timestamp event */ +#define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52 +#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24 +#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8 +/* upper 16 bits of timestamp data */ +#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4 +#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2 +#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32 +#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16 + +/* RSS_MODE structuredef */ +#define RSS_MODE_LEN 1 +/* The RSS mode for a particular packet type is a value from 0 - 15 which can + * be considered as 4 bits selecting which fields are included in the hash. (A + * value 0 effectively disables RSS spreading for the packet type.) The YAML + * generation tools require this structure to be a whole number of bytes wide, + * but only 4 bits are relevant. + */ +#define RSS_MODE_HASH_SELECTOR_OFST 0 +#define RSS_MODE_HASH_SELECTOR_LEN 1 +#define RSS_MODE_HASH_SRC_ADDR_LBN 0 +#define RSS_MODE_HASH_SRC_ADDR_WIDTH 1 +#define RSS_MODE_HASH_DST_ADDR_LBN 1 +#define RSS_MODE_HASH_DST_ADDR_WIDTH 1 +#define RSS_MODE_HASH_SRC_PORT_LBN 2 +#define RSS_MODE_HASH_SRC_PORT_WIDTH 1 +#define RSS_MODE_HASH_DST_PORT_LBN 3 +#define RSS_MODE_HASH_DST_PORT_WIDTH 1 +#define RSS_MODE_HASH_SELECTOR_LBN 0 +#define RSS_MODE_HASH_SELECTOR_WIDTH 8 + + /***********************************/ -/* MC_CMD_INIT_EVQ +/* MC_CMD_READ_REGS + * Get a dump of the MCPU registers */ -#define MC_CMD_INIT_EVQ 0x50 +#define MC_CMD_READ_REGS 0x50 +#undef MC_CMD_0x50_PRIVILEGE_CTG +#define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_READ_REGS_IN msgrequest */ +#define MC_CMD_READ_REGS_IN_LEN 0 + +/* MC_CMD_READ_REGS_OUT msgresponse */ +#define MC_CMD_READ_REGS_OUT_LEN 308 +/* Whether the corresponding register entry contains a valid value */ +#define MC_CMD_READ_REGS_OUT_MASK_OFST 0 +#define MC_CMD_READ_REGS_OUT_MASK_LEN 16 +/* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr, + * fir, fp) + */ +#define MC_CMD_READ_REGS_OUT_REGS_OFST 16 +#define MC_CMD_READ_REGS_OUT_REGS_LEN 4 +#define MC_CMD_READ_REGS_OUT_REGS_NUM 73 + + +/***********************************/ +/* MC_CMD_INIT_EVQ + * Set up an event queue according to the supplied parameters. The IN arguments + * end with an address for each 4k of host memory required to back the EVQ. + */ +#define MC_CMD_INIT_EVQ 0x80 +#undef MC_CMD_0x80_PRIVILEGE_CTG + +#define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_INIT_EVQ_IN msgrequest */ -#define MC_CMD_INIT_EVQ_IN_LENMIN 36 -#define MC_CMD_INIT_EVQ_IN_LENMAX 540 -#define MC_CMD_INIT_EVQ_IN_LEN(num) (28+8*(num)) +#define MC_CMD_INIT_EVQ_IN_LENMIN 44 +#define MC_CMD_INIT_EVQ_IN_LENMAX 548 +#define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num)) +/* Size, in entries */ #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0 +/* Desired instance. Must be set to a specific instance, which is a function + * local queue index. + */ #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4 +/* The initial timer value. The load value is ignored if the timer mode is DIS. + */ #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8 +/* The reload value is ignored in one-shot modes */ #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12 +/* tbd */ #define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1 +#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2 +#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1 +#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3 +#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1 +#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4 +#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1 +#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5 +#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20 -#define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 /* enum */ -#define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 /* enum */ -#define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 /* enum */ -#define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 /* enum */ +/* enum: Disabled */ +#define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 +/* enum: Immediate */ +#define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 +/* enum: Triggered */ +#define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 +/* enum: Hold-off */ +#define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 +/* Target EVQ for wakeups if in wakeup mode. */ #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24 +/* Target interrupt if in interrupting mode (note union with target EVQ). Use + * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test + * purposes. + */ #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24 -#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 28 +/* Event Counter Mode. */ +#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28 +/* enum: Disabled */ +#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0 +/* enum: Disabled */ +#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1 +/* enum: Disabled */ +#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2 +/* enum: Disabled */ +#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3 +/* Event queue packet count threshold. */ +#define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32 +/* 64-bit address of 4k of 4k-aligned host memory buffer */ +#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8 -#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 28 -#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 32 +#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36 +#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64 /* MC_CMD_INIT_EVQ_OUT msgresponse */ #define MC_CMD_INIT_EVQ_OUT_LEN 4 +/* Only valid if INTRFLAG was true */ #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0 /* QUEUE_CRC_MODE structuredef */ #define QUEUE_CRC_MODE_LEN 1 #define QUEUE_CRC_MODE_MODE_LBN 0 #define QUEUE_CRC_MODE_MODE_WIDTH 4 -#define QUEUE_CRC_MODE_NONE 0x0 /* enum */ -#define QUEUE_CRC_MODE_FCOE 0x1 /* enum */ -#define QUEUE_CRC_MODE_ISCSI_HDR 0x2 /* enum */ -#define QUEUE_CRC_MODE_ISCSI 0x3 /* enum */ -#define QUEUE_CRC_MODE_FCOIPOE 0x4 /* enum */ -#define QUEUE_CRC_MODE_MPA 0x5 /* enum */ +/* enum: No CRC. */ +#define QUEUE_CRC_MODE_NONE 0x0 +/* enum: CRC Fiber channel over ethernet. */ +#define QUEUE_CRC_MODE_FCOE 0x1 +/* enum: CRC (digest) iSCSI header only. */ +#define QUEUE_CRC_MODE_ISCSI_HDR 0x2 +/* enum: CRC (digest) iSCSI header and payload. */ +#define QUEUE_CRC_MODE_ISCSI 0x3 +/* enum: CRC Fiber channel over IP over ethernet. */ +#define QUEUE_CRC_MODE_FCOIPOE 0x4 +/* enum: CRC MPA. */ +#define QUEUE_CRC_MODE_MPA 0x5 #define QUEUE_CRC_MODE_SPARE_LBN 4 #define QUEUE_CRC_MODE_SPARE_WIDTH 4 /***********************************/ -/* MC_CMD_INIT_RXQ +/* MC_CMD_INIT_RXQ + * set up a receive queue according to the supplied parameters. The IN + * arguments end with an address for each 4k of host memory required to back + * the RXQ. */ -#define MC_CMD_INIT_RXQ 0x51 +#define MC_CMD_INIT_RXQ 0x81 +#undef MC_CMD_0x81_PRIVILEGE_CTG -/* MC_CMD_INIT_RXQ_IN msgrequest */ -#define MC_CMD_INIT_RXQ_IN_LENMIN 32 -#define MC_CMD_INIT_RXQ_IN_LENMAX 248 -#define MC_CMD_INIT_RXQ_IN_LEN(num) (24+8*(num)) +#define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version + * in new code. + */ +#define MC_CMD_INIT_RXQ_IN_LENMIN 36 +#define MC_CMD_INIT_RXQ_IN_LENMAX 252 +#define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num)) +/* Size, in entries */ #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0 +/* The EVQ to send events to. This is an index originally specified to INIT_EVQ + */ #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4 +/* The value to put in the event data. Check hardware spec. for valid range. */ #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8 +/* Desired instance. Must be set to a specific instance, which is a function + * local queue index. + */ #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12 +/* There will be more flags here. */ #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1 -#define MC_CMD_INIT_RXQ_IN_FLAG_PKT_EDIT_LBN 2 -#define MC_CMD_INIT_RXQ_IN_FLAG_PKT_EDIT_WIDTH 1 +#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2 +#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4 +#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7 +#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1 +#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8 +#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1 +#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9 +#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1 +/* Owner ID to use if in buffer mode (zero if physical) */ #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20 -#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 24 +/* The port ID associated with the v-adaptor which should contain this DMAQ. */ +#define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24 +/* 64-bit address of 4k of 4k-aligned host memory buffer */ +#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8 -#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 24 -#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 28 +#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28 +#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28 +/* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode + * flags + */ +#define MC_CMD_INIT_RXQ_EXT_IN_LEN 544 +/* Size, in entries */ +#define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0 +/* The EVQ to send events to. This is an index originally specified to INIT_EVQ + */ +#define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4 +/* The value to put in the event data. Check hardware spec. for valid range. */ +#define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8 +/* Desired instance. Must be set to a specific instance, which is a function + * local queue index. + */ +#define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12 +/* There will be more flags here. */ +#define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16 +#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 +#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 +#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1 +#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1 +#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2 +#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 +#define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3 +#define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4 +#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7 +#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1 +#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8 +#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1 +#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9 +#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1 +#define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10 +#define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4 +/* enum: One packet per descriptor (for normal networking) */ +#define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0 +/* enum: Pack multiple packets into large descriptors (for SolarCapture) */ +#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1 +#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14 +#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 +#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 +#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 +#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */ +#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */ +#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */ +#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */ +#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */ +#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 +#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 +/* Owner ID to use if in buffer mode (zero if physical) */ +#define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20 +/* The port ID associated with the v-adaptor which should contain this DMAQ. */ +#define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24 +/* 64-bit address of 4k of 4k-aligned host memory buffer */ +#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28 +#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8 +#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28 +#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32 +#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64 +/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ +#define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540 + /* MC_CMD_INIT_RXQ_OUT msgresponse */ #define MC_CMD_INIT_RXQ_OUT_LEN 0 +/* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */ +#define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0 + /***********************************/ -/* MC_CMD_INIT_TXQ +/* MC_CMD_INIT_TXQ */ -#define MC_CMD_INIT_TXQ 0x52 +#define MC_CMD_INIT_TXQ 0x82 +#undef MC_CMD_0x82_PRIVILEGE_CTG -/* MC_CMD_INIT_TXQ_IN msgrequest */ -#define MC_CMD_INIT_TXQ_IN_LENMIN 32 -#define MC_CMD_INIT_TXQ_IN_LENMAX 248 -#define MC_CMD_INIT_TXQ_IN_LEN(num) (24+8*(num)) +#define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version + * in new code. + */ +#define MC_CMD_INIT_TXQ_IN_LENMIN 36 +#define MC_CMD_INIT_TXQ_IN_LENMAX 252 +#define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num)) +/* Size, in entries */ #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0 +/* The EVQ to send events to. This is an index originally specified to + * INIT_EVQ. + */ #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4 +/* The value to put in the event data. Check hardware spec. for valid range. */ #define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8 +/* Desired instance. Must be set to a specific instance, which is a function + * local queue index. + */ #define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12 +/* There will be more flags here. */ #define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4 +#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8 +#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1 +#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9 +#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1 +#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 +#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 +#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 +#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 +/* Owner ID to use if in buffer mode (zero if physical) */ #define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20 -#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 24 +/* The port ID associated with the v-adaptor which should contain this DMAQ. */ +#define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24 +/* 64-bit address of 4k of 4k-aligned host memory buffer */ +#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8 -#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 24 -#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 28 +#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28 +#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28 +/* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode + * flags + */ +#define MC_CMD_INIT_TXQ_EXT_IN_LEN 544 +/* Size, in entries */ +#define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0 +/* The EVQ to send events to. This is an index originally specified to + * INIT_EVQ. + */ +#define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4 +/* The value to put in the event data. Check hardware spec. for valid range. */ +#define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8 +/* Desired instance. Must be set to a specific instance, which is a function + * local queue index. + */ +#define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12 +/* There will be more flags here. */ +#define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16 +#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 +#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 +#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1 +#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1 +#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2 +#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 +#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3 +#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 +#define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4 +#define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4 +#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8 +#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 +#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9 +#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1 +#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 +#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 +#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 +#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 +/* Owner ID to use if in buffer mode (zero if physical) */ +#define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20 +/* The port ID associated with the v-adaptor which should contain this DMAQ. */ +#define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24 +/* 64-bit address of 4k of 4k-aligned host memory buffer */ +#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28 +#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8 +#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28 +#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32 +#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1 +#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64 +/* Flags related to Qbb flow control mode. */ +#define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540 +#define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0 +#define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1 +#define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1 +#define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3 + /* MC_CMD_INIT_TXQ_OUT msgresponse */ #define MC_CMD_INIT_TXQ_OUT_LEN 0 /***********************************/ -/* MC_CMD_FINI_EVQ +/* MC_CMD_FINI_EVQ + * Teardown an EVQ. + * + * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first + * or the operation will fail with EBUSY */ -#define MC_CMD_FINI_EVQ 0x55 +#define MC_CMD_FINI_EVQ 0x83 +#undef MC_CMD_0x83_PRIVILEGE_CTG +#define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_FINI_EVQ_IN msgrequest */ #define MC_CMD_FINI_EVQ_IN_LEN 4 +/* Instance of EVQ to destroy. Should be the same instance as that previously + * passed to INIT_EVQ + */ #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0 /* MC_CMD_FINI_EVQ_OUT msgresponse */ #define MC_CMD_FINI_EVQ_OUT_LEN 0 /***********************************/ -/* MC_CMD_FINI_RXQ +/* MC_CMD_FINI_RXQ + * Teardown a RXQ. */ -#define MC_CMD_FINI_RXQ 0x56 +#define MC_CMD_FINI_RXQ 0x84 +#undef MC_CMD_0x84_PRIVILEGE_CTG +#define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_FINI_RXQ_IN msgrequest */ #define MC_CMD_FINI_RXQ_IN_LEN 4 +/* Instance of RXQ to destroy */ #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0 /* MC_CMD_FINI_RXQ_OUT msgresponse */ #define MC_CMD_FINI_RXQ_OUT_LEN 0 /***********************************/ -/* MC_CMD_FINI_TXQ +/* MC_CMD_FINI_TXQ + * Teardown a TXQ. */ -#define MC_CMD_FINI_TXQ 0x57 +#define MC_CMD_FINI_TXQ 0x85 +#undef MC_CMD_0x85_PRIVILEGE_CTG +#define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_FINI_TXQ_IN msgrequest */ #define MC_CMD_FINI_TXQ_IN_LEN 4 +/* Instance of TXQ to destroy */ #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0 /* MC_CMD_FINI_TXQ_OUT msgresponse */ #define MC_CMD_FINI_TXQ_OUT_LEN 0 /***********************************/ -/* MC_CMD_DRIVER_EVENT +/* MC_CMD_DRIVER_EVENT + * Generate an event on an EVQ belonging to the function issuing the command. */ -#define MC_CMD_DRIVER_EVENT 0x5a +#define MC_CMD_DRIVER_EVENT 0x86 +#undef MC_CMD_0x86_PRIVILEGE_CTG +#define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_DRIVER_EVENT_IN msgrequest */ #define MC_CMD_DRIVER_EVENT_IN_LEN 12 +/* Handle of target EVQ */ #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0 +/* Bits 0 - 63 of event */ #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4 #define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4 #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8 +/* MC_CMD_DRIVER_EVENT_OUT msgresponse */ +#define MC_CMD_DRIVER_EVENT_OUT_LEN 0 + /***********************************/ -/* MC_CMD_PROXY_CMD +/* MC_CMD_PROXY_CMD + * Execute an arbitrary MCDI command on behalf of a different function, subject + * to security restrictions. The command to be proxied follows immediately + * afterward in the host buffer (or on the UART). This command supercedes + * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated. */ -#define MC_CMD_PROXY_CMD 0x5b +#define MC_CMD_PROXY_CMD 0x5b +#undef MC_CMD_0x5b_PRIVILEGE_CTG +#define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_PROXY_CMD_IN msgrequest */ #define MC_CMD_PROXY_CMD_IN_LEN 4 +/* The handle of the target function. */ #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0 +#define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0 +#define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16 +#define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16 +#define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16 +#define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */ +/* MC_CMD_PROXY_CMD_OUT msgresponse */ +#define MC_CMD_PROXY_CMD_OUT_LEN 0 +/* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to + * manage proxied requests + */ +#define MC_PROXY_STATUS_BUFFER_LEN 16 +/* Handle allocated by the firmware for this proxy transaction */ +#define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0 +/* enum: An invalid handle. */ +#define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0 +#define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0 +#define MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32 +/* The requesting physical function number */ +#define MC_PROXY_STATUS_BUFFER_PF_OFST 4 +#define MC_PROXY_STATUS_BUFFER_PF_LEN 2 +#define MC_PROXY_STATUS_BUFFER_PF_LBN 32 +#define MC_PROXY_STATUS_BUFFER_PF_WIDTH 16 +/* The requesting virtual function number. Set to VF_NULL if the target is a + * PF. + */ +#define MC_PROXY_STATUS_BUFFER_VF_OFST 6 +#define MC_PROXY_STATUS_BUFFER_VF_LEN 2 +#define MC_PROXY_STATUS_BUFFER_VF_LBN 48 +#define MC_PROXY_STATUS_BUFFER_VF_WIDTH 16 +/* The target function RID. */ +#define MC_PROXY_STATUS_BUFFER_RID_OFST 8 +#define MC_PROXY_STATUS_BUFFER_RID_LEN 2 +#define MC_PROXY_STATUS_BUFFER_RID_LBN 64 +#define MC_PROXY_STATUS_BUFFER_RID_WIDTH 16 +/* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */ +#define MC_PROXY_STATUS_BUFFER_STATUS_OFST 10 +#define MC_PROXY_STATUS_BUFFER_STATUS_LEN 2 +#define MC_PROXY_STATUS_BUFFER_STATUS_LBN 80 +#define MC_PROXY_STATUS_BUFFER_STATUS_WIDTH 16 +/* If a request is authorized rather than carried out by the host, this is the + * elevated privilege mask granted to the requesting function. + */ +#define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12 +#define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96 +#define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32 + + /***********************************/ -/* MC_CMD_ALLOC_OWNER_IDS +/* MC_CMD_PROXY_CONFIGURE + * Enable/disable authorization of MCDI requests from unprivileged functions by + * a designated admin function */ -#define MC_CMD_ALLOC_OWNER_IDS 0x54 +#define MC_CMD_PROXY_CONFIGURE 0x58 +#undef MC_CMD_0x58_PRIVILEGE_CTG -/* MC_CMD_ALLOC_OWNER_IDS_IN msgrequest */ -#define MC_CMD_ALLOC_OWNER_IDS_IN_LEN 4 -#define MC_CMD_ALLOC_OWNER_IDS_IN_NIDS_OFST 0 +#define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN -/* MC_CMD_ALLOC_OWNER_IDS_OUT msgresponse */ -#define MC_CMD_ALLOC_OWNER_IDS_OUT_LEN 12 -#define MC_CMD_ALLOC_OWNER_IDS_OUT_HANDLE_OFST 0 -#define MC_CMD_ALLOC_OWNER_IDS_OUT_NIDS_OFST 4 -#define MC_CMD_ALLOC_OWNER_IDS_OUT_BASE_OFST 8 +/* MC_CMD_PROXY_CONFIGURE_IN msgrequest */ +#define MC_CMD_PROXY_CONFIGURE_IN_LEN 108 +#define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0 +#define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0 +#define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1 +/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS + * of blocks, each of the size REQUEST_BLOCK_SIZE. + */ +#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4 +#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8 +#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4 +#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8 +/* Must be a power of 2 */ +#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12 +/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS + * of blocks, each of the size REPLY_BLOCK_SIZE. + */ +#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16 +#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8 +#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16 +#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20 +/* Must be a power of 2 */ +#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24 +/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS + * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if + * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. + */ +#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28 +#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8 +#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28 +#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32 +/* Must be a power of 2, or zero if this buffer is not provided */ +#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36 +/* Applies to all three buffers */ +#define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40 +/* A bit mask defining which MCDI operations may be proxied */ +#define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44 +#define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64 +/* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */ +#define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0 + /***********************************/ -/* MC_CMD_FREE_OWNER_IDS +/* MC_CMD_PROXY_COMPLETE + * Tells FW that a requested proxy operation has either been completed (by + * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the + * function that enabled proxying/authorization (by using + * MC_CMD_PROXY_CONFIGURE). */ -#define MC_CMD_FREE_OWNER_IDS 0x59 +#define MC_CMD_PROXY_COMPLETE 0x5f +#undef MC_CMD_0x5f_PRIVILEGE_CTG -/* MC_CMD_FREE_OWNER_IDS_IN msgrequest */ -#define MC_CMD_FREE_OWNER_IDS_IN_LEN 4 -#define MC_CMD_FREE_OWNER_IDS_IN_HANDLE_OFST 0 +#define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN -/* MC_CMD_FREE_OWNER_IDS_OUT msgresponse */ -#define MC_CMD_FREE_OWNER_IDS_OUT_LEN 0 +/* MC_CMD_PROXY_COMPLETE_IN msgrequest */ +#define MC_CMD_PROXY_COMPLETE_IN_LEN 12 +#define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0 +#define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4 +/* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply + * is stored in the REPLY_BUFF. + */ +#define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0 +/* enum: The operation has been authorized. The originating function may now + * try again. + */ +#define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1 +/* enum: The operation has been declined. */ +#define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2 +/* enum: The authorization failed because the relevant application did not + * respond in time. + */ +#define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3 +#define MC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8 +/* MC_CMD_PROXY_COMPLETE_OUT msgresponse */ +#define MC_CMD_PROXY_COMPLETE_OUT_LEN 0 + /***********************************/ -/* MC_CMD_ALLOC_BUFTBL_CHUNK +/* MC_CMD_ALLOC_BUFTBL_CHUNK + * Allocate a set of buffer table entries using the specified owner ID. This + * operation allocates the required buffer table entries (and fails if it + * cannot do so). The buffer table entries will initially be zeroed. */ -#define MC_CMD_ALLOC_BUFTBL_CHUNK 0x5c +#define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87 +#undef MC_CMD_0x87_PRIVILEGE_CTG +#define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD + /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */ #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8 +/* Owner ID to use */ #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0 +/* Size of buffer table pages to use, in bytes (note that only a few values are + * legal on any specific hardware). + */ #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4 /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */ #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4 +/* Buffer table IDs for use in DMA descriptors. */ #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8 /***********************************/ -/* MC_CMD_PROGRAM_BUFTBL_ENTRIES +/* MC_CMD_PROGRAM_BUFTBL_ENTRIES + * Reprogram a set of buffer table entries in the specified chunk. */ -#define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x5d +#define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88 +#undef MC_CMD_0x88_PRIVILEGE_CTG +#define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD + /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */ #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20 -#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 252 +#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num)) #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0 +/* ID */ #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4 +/* Num entries */ #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8 +/* Buffer table entry address */ #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1 -#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 30 +#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */ #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0 /***********************************/ -/* MC_CMD_FREE_BUFTBL_CHUNK +/* MC_CMD_FREE_BUFTBL_CHUNK */ -#define MC_CMD_FREE_BUFTBL_CHUNK 0x5e +#define MC_CMD_FREE_BUFTBL_CHUNK 0x89 +#undef MC_CMD_0x89_PRIVILEGE_CTG +#define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD + /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */ #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0 /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */ #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0 +/* PORT_CONFIG_ENTRY structuredef */ +#define PORT_CONFIG_ENTRY_LEN 16 +/* External port number (label) */ +#define PORT_CONFIG_ENTRY_EXT_NUMBER_OFST 0 +#define PORT_CONFIG_ENTRY_EXT_NUMBER_LEN 1 +#define PORT_CONFIG_ENTRY_EXT_NUMBER_LBN 0 +#define PORT_CONFIG_ENTRY_EXT_NUMBER_WIDTH 8 +/* Port core location */ +#define PORT_CONFIG_ENTRY_CORE_OFST 1 +#define PORT_CONFIG_ENTRY_CORE_LEN 1 +#define PORT_CONFIG_ENTRY_STANDALONE 0x0 /* enum */ +#define PORT_CONFIG_ENTRY_MASTER 0x1 /* enum */ +#define PORT_CONFIG_ENTRY_SLAVE 0x2 /* enum */ +#define PORT_CONFIG_ENTRY_CORE_LBN 8 +#define PORT_CONFIG_ENTRY_CORE_WIDTH 8 +/* Internal number (HW resource) relative to the core */ +#define PORT_CONFIG_ENTRY_INT_NUMBER_OFST 2 +#define PORT_CONFIG_ENTRY_INT_NUMBER_LEN 1 +#define PORT_CONFIG_ENTRY_INT_NUMBER_LBN 16 +#define PORT_CONFIG_ENTRY_INT_NUMBER_WIDTH 8 +/* Reserved */ +#define PORT_CONFIG_ENTRY_RSVD_OFST 3 +#define PORT_CONFIG_ENTRY_RSVD_LEN 1 +#define PORT_CONFIG_ENTRY_RSVD_LBN 24 +#define PORT_CONFIG_ENTRY_RSVD_WIDTH 8 +/* Bitmask of KR lanes used by the port */ +#define PORT_CONFIG_ENTRY_LANES_OFST 4 +#define PORT_CONFIG_ENTRY_LANES_LBN 32 +#define PORT_CONFIG_ENTRY_LANES_WIDTH 32 +/* Port capabilities (MC_CMD_PHY_CAP_*) */ +#define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_OFST 8 +#define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_LBN 64 +#define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_WIDTH 32 +/* Reserved (align to 16 bytes) */ +#define PORT_CONFIG_ENTRY_RSVD2_OFST 12 +#define PORT_CONFIG_ENTRY_RSVD2_LBN 96 +#define PORT_CONFIG_ENTRY_RSVD2_WIDTH 32 -/***********************************/ -/* MC_CMD_GET_PF_COUNT - */ -#define MC_CMD_GET_PF_COUNT 0x60 -/* MC_CMD_GET_PF_COUNT_IN msgrequest */ -#define MC_CMD_GET_PF_COUNT_IN_LEN 0 - -/* MC_CMD_GET_PF_COUNT_OUT msgresponse */ -#define MC_CMD_GET_PF_COUNT_OUT_LEN 1 -#define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 -#define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 - - /***********************************/ -/* MC_CMD_FILTER_OP +/* MC_CMD_FILTER_OP + * Multiplexed MCDI call for filter operations */ -#define MC_CMD_FILTER_OP 0x61 +#define MC_CMD_FILTER_OP 0x8a +#undef MC_CMD_0x8a_PRIVILEGE_CTG +#define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_FILTER_OP_IN msgrequest */ -#define MC_CMD_FILTER_OP_IN_LEN 100 +#define MC_CMD_FILTER_OP_IN_LEN 108 +/* identifies the type of operation requested */ #define MC_CMD_FILTER_OP_IN_OP_OFST 0 -#define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 /* enum */ -#define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 /* enum */ -#define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 /* enum */ -#define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 /* enum */ +/* enum: single-recipient filter insert */ +#define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 +/* enum: single-recipient filter remove */ +#define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 +/* enum: multi-recipient filter subscribe */ +#define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 +/* enum: multi-recipient filter unsubscribe */ +#define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 +/* enum: replace one recipient with another (warning - the filter handle may + * change) + */ +#define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4 +/* filter handle (for remove / unsubscribe operations) */ #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4 -#define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 8 +#define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8 +#define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4 +#define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8 +/* The port ID associated with the v-adaptor which should contain this filter. + */ +#define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12 +/* fields to include in match criteria */ +#define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1 -#define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 12 -#define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 /* enum */ -#define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 /* enum */ -#define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 /* enum */ -#define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 /* enum */ -#define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 /* enum */ -#define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 16 -#define MC_CMD_FILTER_OP_IN_RX_FLAGS_OFST 20 -#define MC_CMD_FILTER_OP_IN_RX_FLAG_RSS_LBN 0 -#define MC_CMD_FILTER_OP_IN_RX_FLAG_RSS_WIDTH 1 -#define MC_CMD_FILTER_OP_IN_RSS_CONTEXT_OFST 24 -#define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 28 -#define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 32 +#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 +#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 +#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 +#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 +/* receive destination */ +#define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20 +/* enum: drop packets */ +#define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 +/* enum: receive to host */ +#define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 +/* enum: receive to MC */ +#define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 +/* enum: loop back to TXDP 0 */ +#define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 +/* enum: loop back to TXDP 1 */ +#define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 +/* receive queue handle (for multiple queue modes, this is the base queue) */ +#define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24 +/* receive mode */ +#define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28 +/* enum: receive to just the specified queue */ +#define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0 +/* enum: receive to multiple queues using RSS context */ +#define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1 +/* enum: receive to multiple queues using .1p mapping */ +#define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2 +/* enum: install a filter entry that will never match; for test purposes only + */ +#define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 +/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for + * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or + * MC_CMD_DOT1P_MAPPING_ALLOC. + */ +#define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32 +/* transmit domain (reserved; set to 0) */ +#define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36 +/* transmit destination (either set the MAC and/or PM bits for explicit + * control, or set this field to TX_DEST_DEFAULT for sensible default + * behaviour) + */ +#define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40 +/* enum: request default behaviour (based on filter type) */ +#define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1 -#define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 36 +/* source MAC address to match (as bytes in network order) */ +#define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44 #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6 -#define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 42 +/* source port to match (as bytes in network order) */ +#define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50 #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2 -#define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 44 +/* destination MAC address to match (as bytes in network order) */ +#define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52 #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6 -#define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 50 +/* destination port to match (as bytes in network order) */ +#define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58 #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2 -#define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 52 +/* Ethernet type to match (as bytes in network order) */ +#define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2 -#define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 54 +/* Inner VLAN tag to match (as bytes in network order) */ +#define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2 -#define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 56 +/* Outer VLAN tag to match (as bytes in network order) */ +#define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2 -#define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 58 +/* IP protocol to match (in low byte; set high byte to 0) */ +#define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66 #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2 -#define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 60 -#define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 64 -#define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 68 +/* Firmware defined register 0 to match (reserved; set to 0) */ +#define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68 +/* Firmware defined register 1 to match (reserved; set to 0) */ +#define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72 +/* source IP address to match (as bytes in network order; set last 12 bytes to + * 0 for IPv4 address) + */ +#define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76 #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16 -#define MC_CMD_FILTER_OP_IN_DST_IP_OFST 84 +/* destination IP address to match (as bytes in network order; set last 12 + * bytes to 0 for IPv4 address) + */ +#define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92 #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16 +/* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to + * include handling of VXLAN/NVGRE encapsulated frame filtering (which is + * supported on Medford only). + */ +#define MC_CMD_FILTER_OP_EXT_IN_LEN 172 +/* identifies the type of operation requested */ +#define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0 +/* Enum values, see field(s): */ +/* MC_CMD_FILTER_OP_IN/OP */ +/* filter handle (for remove / unsubscribe operations) */ +#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4 +#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8 +#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4 +#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8 +/* The port ID associated with the v-adaptor which should contain this filter. + */ +#define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12 +/* fields to include in match criteria */ +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 +#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 +/* receive destination */ +#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20 +/* enum: drop packets */ +#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0 +/* enum: receive to host */ +#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1 +/* enum: receive to MC */ +#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2 +/* enum: loop back to TXDP 0 */ +#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3 +/* enum: loop back to TXDP 1 */ +#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4 +/* receive queue handle (for multiple queue modes, this is the base queue) */ +#define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24 +/* receive mode */ +#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28 +/* enum: receive to just the specified queue */ +#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0 +/* enum: receive to multiple queues using RSS context */ +#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1 +/* enum: receive to multiple queues using .1p mapping */ +#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2 +/* enum: install a filter entry that will never match; for test purposes only + */ +#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 +/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for + * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or + * MC_CMD_DOT1P_MAPPING_ALLOC. + */ +#define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32 +/* transmit domain (reserved; set to 0) */ +#define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36 +/* transmit destination (either set the MAC and/or PM bits for explicit + * control, or set this field to TX_DEST_DEFAULT for sensible default + * behaviour) + */ +#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40 +/* enum: request default behaviour (based on filter type) */ +#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff +#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0 +#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1 +#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1 +#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1 +/* source MAC address to match (as bytes in network order) */ +#define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44 +#define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6 +/* source port to match (as bytes in network order) */ +#define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50 +#define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2 +/* destination MAC address to match (as bytes in network order) */ +#define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52 +#define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6 +/* destination port to match (as bytes in network order) */ +#define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58 +#define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2 +/* Ethernet type to match (as bytes in network order) */ +#define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60 +#define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2 +/* Inner VLAN tag to match (as bytes in network order) */ +#define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62 +#define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2 +/* Outer VLAN tag to match (as bytes in network order) */ +#define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64 +#define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2 +/* IP protocol to match (in low byte; set high byte to 0) */ +#define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66 +#define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2 +/* Firmware defined register 0 to match (reserved; set to 0) */ +#define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68 +/* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP + * protocol is GRE) to match (as bytes in network order; set last byte to 0 for + * VXLAN/NVGRE, or 1 for Geneve) + */ +#define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72 +#define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0 +#define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24 +#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24 +#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8 +/* enum: Match VXLAN traffic with this VNI */ +#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0 +/* enum: Match Geneve traffic with this VNI */ +#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1 +/* enum: Reserved for experimental development use */ +#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe +#define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0 +#define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24 +#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24 +#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8 +/* enum: Match NVGRE traffic with this VSID */ +#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0 +/* source IP address to match (as bytes in network order; set last 12 bytes to + * 0 for IPv4 address) + */ +#define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76 +#define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16 +/* destination IP address to match (as bytes in network order; set last 12 + * bytes to 0 for IPv4 address) + */ +#define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92 +#define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16 +/* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network + * order) + */ +#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108 +#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6 +/* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */ +#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114 +#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2 +/* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in + * network order) + */ +#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116 +#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6 +/* VXLAN/NVGRE inner frame destination port to match (as bytes in network + * order) + */ +#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122 +#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2 +/* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order) + */ +#define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124 +#define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2 +/* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order) + */ +#define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126 +#define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2 +/* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order) + */ +#define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128 +#define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2 +/* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to + * 0) + */ +#define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130 +#define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2 +/* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set + * to 0) + */ +#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132 +/* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set + * to 0) + */ +#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136 +/* VXLAN/NVGRE inner frame source IP address to match (as bytes in network + * order; set last 12 bytes to 0 for IPv4 address) + */ +#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140 +#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16 +/* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network + * order; set last 12 bytes to 0 for IPv4 address) + */ +#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156 +#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16 + /* MC_CMD_FILTER_OP_OUT msgresponse */ -#define MC_CMD_FILTER_OP_OUT_LEN 8 +#define MC_CMD_FILTER_OP_OUT_LEN 12 +/* identifies the type of operation requested */ #define MC_CMD_FILTER_OP_OUT_OP_OFST 0 -#define MC_CMD_FILTER_OP_OUT_OP_INSERT 0x0 /* enum */ -#define MC_CMD_FILTER_OP_OUT_OP_REMOVE 0x1 /* enum */ -#define MC_CMD_FILTER_OP_OUT_OP_SUBSCRIBE 0x2 /* enum */ -#define MC_CMD_FILTER_OP_OUT_OP_UNSUBSCRIBE 0x3 /* enum */ +/* Enum values, see field(s): */ +/* MC_CMD_FILTER_OP_IN/OP */ +/* Returned filter handle (for insert / subscribe operations). Note that these + * handles should be considered opaque to the host, although a value of + * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. + */ #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4 +#define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8 +#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4 +#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8 +/* enum: guaranteed invalid filter handle (low 32 bits) */ +#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff +/* enum: guaranteed invalid filter handle (high 32 bits) */ +#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff +/* MC_CMD_FILTER_OP_EXT_OUT msgresponse */ +#define MC_CMD_FILTER_OP_EXT_OUT_LEN 12 +/* identifies the type of operation requested */ +#define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0 +/* Enum values, see field(s): */ +/* MC_CMD_FILTER_OP_EXT_IN/OP */ +/* Returned filter handle (for insert / subscribe operations). Note that these + * handles should be considered opaque to the host, although a value of + * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. + */ +#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4 +#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8 +#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4 +#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8 +/* Enum values, see field(s): */ +/* MC_CMD_FILTER_OP_OUT/HANDLE */ + /***********************************/ -/* MC_CMD_SET_PF_COUNT +/* MC_CMD_GET_PARSER_DISP_INFO + * Get information related to the parser-dispatcher subsystem */ -#define MC_CMD_SET_PF_COUNT 0x62 +#define MC_CMD_GET_PARSER_DISP_INFO 0xe4 +#undef MC_CMD_0xe4_PRIVILEGE_CTG +#define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */ +#define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4 +/* identifies the type of operation requested */ +#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0 +/* enum: read the list of supported RX filter matches */ +#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1 +/* enum: read flags indicating restrictions on filter insertion for the calling + * client + */ +#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2 + +/* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */ +#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8 +#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252 +#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num)) +/* identifies the type of operation requested */ +#define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0 +/* Enum values, see field(s): */ +/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ +/* number of supported match types */ +#define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4 +/* array of supported match types (valid MATCH_FIELDS values for + * MC_CMD_FILTER_OP) sorted in decreasing priority order + */ +#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8 +#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4 +#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0 +#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61 + +/* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */ +#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8 +/* identifies the type of operation requested */ +#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0 +/* Enum values, see field(s): */ +/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ +/* bitfield of filter insertion restrictions */ +#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4 +#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0 +#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1 + + +/***********************************/ +/* MC_CMD_PARSER_DISP_RW + * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging + */ +#define MC_CMD_PARSER_DISP_RW 0xe5 +#undef MC_CMD_0xe5_PRIVILEGE_CTG + +#define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_PARSER_DISP_RW_IN msgrequest */ +#define MC_CMD_PARSER_DISP_RW_IN_LEN 32 +/* identifies the target of the operation */ +#define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0 +/* enum: RX dispatcher CPU */ +#define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0 +/* enum: TX dispatcher CPU */ +#define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1 +/* enum: Lookup engine (with original metadata format) */ +#define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2 +/* enum: Lookup engine (with requested metadata format) */ +#define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3 +/* identifies the type of operation requested */ +#define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4 +/* enum: read a word of DICPU DMEM or a LUE entry */ +#define MC_CMD_PARSER_DISP_RW_IN_READ 0x0 +/* enum: write a word of DICPU DMEM or a LUE entry */ +#define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1 +/* enum: read-modify-write a word of DICPU DMEM (not valid for LUE) */ +#define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2 +/* data memory address or LUE index */ +#define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8 +/* value to write (for DMEM writes) */ +#define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12 +/* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */ +#define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12 +/* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */ +#define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16 +/* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */ +#define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12 +/* value to write (for LUE writes) */ +#define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12 +#define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20 + +/* MC_CMD_PARSER_DISP_RW_OUT msgresponse */ +#define MC_CMD_PARSER_DISP_RW_OUT_LEN 52 +/* value read (for DMEM reads) */ +#define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0 +/* value read (for LUE reads) */ +#define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0 +#define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20 +/* up to 8 32-bit words of additional soft state from the LUE manager (the + * exact content is firmware-dependent and intended only for debug use) + */ +#define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20 +#define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32 + + +/***********************************/ +/* MC_CMD_GET_PF_COUNT + * Get number of PFs on the device. + */ +#define MC_CMD_GET_PF_COUNT 0xb6 +#undef MC_CMD_0xb6_PRIVILEGE_CTG + +#define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_GET_PF_COUNT_IN msgrequest */ +#define MC_CMD_GET_PF_COUNT_IN_LEN 0 + +/* MC_CMD_GET_PF_COUNT_OUT msgresponse */ +#define MC_CMD_GET_PF_COUNT_OUT_LEN 1 +/* Identifies the number of PFs on the device. */ +#define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 +#define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 + + +/***********************************/ +/* MC_CMD_SET_PF_COUNT + * Set number of PFs on the device. + */ +#define MC_CMD_SET_PF_COUNT 0xb7 + /* MC_CMD_SET_PF_COUNT_IN msgrequest */ #define MC_CMD_SET_PF_COUNT_IN_LEN 4 +/* New number of PFs on the device. */ #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0 /* MC_CMD_SET_PF_COUNT_OUT msgresponse */ #define MC_CMD_SET_PF_COUNT_OUT_LEN 0 /***********************************/ -/* MC_CMD_GET_PORT_ASSIGNMENT +/* MC_CMD_GET_PORT_ASSIGNMENT + * Get port assignment for current PCI function. */ -#define MC_CMD_GET_PORT_ASSIGNMENT 0x63 +#define MC_CMD_GET_PORT_ASSIGNMENT 0xb8 +#undef MC_CMD_0xb8_PRIVILEGE_CTG +#define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */ #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */ #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4 +/* Identifies the port assignment for this function. */ #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0 /***********************************/ -/* MC_CMD_SET_PORT_ASSIGNMENT +/* MC_CMD_SET_PORT_ASSIGNMENT + * Set port assignment for current PCI function. */ -#define MC_CMD_SET_PORT_ASSIGNMENT 0x64 +#define MC_CMD_SET_PORT_ASSIGNMENT 0xb9 +#undef MC_CMD_0xb9_PRIVILEGE_CTG +#define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */ #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4 +/* Identifies the port assignment for this function. */ #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0 /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */ #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0 /***********************************/ -/* MC_CMD_ALLOC_VIS +/* MC_CMD_ALLOC_VIS + * Allocate VIs for current PCI function. */ -#define MC_CMD_ALLOC_VIS 0x65 +#define MC_CMD_ALLOC_VIS 0x8b +#undef MC_CMD_0x8b_PRIVILEGE_CTG +#define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_ALLOC_VIS_IN msgrequest */ -#define MC_CMD_ALLOC_VIS_IN_LEN 4 -#define MC_CMD_ALLOC_VIS_IN_VI_COUNT_OFST 0 +#define MC_CMD_ALLOC_VIS_IN_LEN 8 +/* The minimum number of VIs that is acceptable */ +#define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0 +/* The maximum number of VIs that would be useful */ +#define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4 -/* MC_CMD_ALLOC_VIS_OUT msgresponse */ -#define MC_CMD_ALLOC_VIS_OUT_LEN 0 +/* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request. + * Use extended version in new code. + */ +#define MC_CMD_ALLOC_VIS_OUT_LEN 8 +/* The number of VIs allocated on this function */ +#define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0 +/* The base absolute VI number allocated to this function. Required to + * correctly interpret wakeup events. + */ +#define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4 +/* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */ +#define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12 +/* The number of VIs allocated on this function */ +#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0 +/* The base absolute VI number allocated to this function. Required to + * correctly interpret wakeup events. + */ +#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4 +/* Function's port vi_shift value (always 0 on Huntington) */ +#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8 + /***********************************/ -/* MC_CMD_FREE_VIS +/* MC_CMD_FREE_VIS + * Free VIs for current PCI function. Any linked PIO buffers will be unlinked, + * but not freed. */ -#define MC_CMD_FREE_VIS 0x66 +#define MC_CMD_FREE_VIS 0x8c +#undef MC_CMD_0x8c_PRIVILEGE_CTG +#define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_FREE_VIS_IN msgrequest */ #define MC_CMD_FREE_VIS_IN_LEN 0 /* MC_CMD_FREE_VIS_OUT msgresponse */ #define MC_CMD_FREE_VIS_OUT_LEN 0 /***********************************/ -/* MC_CMD_GET_SRIOV_CFG +/* MC_CMD_GET_SRIOV_CFG + * Get SRIOV config for this PF. */ -#define MC_CMD_GET_SRIOV_CFG 0x67 +#define MC_CMD_GET_SRIOV_CFG 0xba +#undef MC_CMD_0xba_PRIVILEGE_CTG +#define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */ #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0 /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */ #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20 +/* Number of VFs currently enabled. */ #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0 +/* Max number of VFs before sriov stride and offset may need to be changed. */ #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1 +/* RID offset of first VF from PF. */ #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12 +/* RID offset of each subsequent VF from the previous. */ #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16 /***********************************/ -/* MC_CMD_SET_SRIOV_CFG +/* MC_CMD_SET_SRIOV_CFG + * Set SRIOV config for this PF. */ -#define MC_CMD_SET_SRIOV_CFG 0x68 +#define MC_CMD_SET_SRIOV_CFG 0xbb +#undef MC_CMD_0xbb_PRIVILEGE_CTG +#define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN + /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */ #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20 +/* Number of VFs currently enabled. */ #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0 +/* Max number of VFs before sriov stride and offset may need to be changed. */ #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1 +/* RID offset of first VF from PF, or 0 for no change, or + * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset. + */ #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12 +/* RID offset of each subsequent VF from the previous, 0 for no change, or + * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride. + */ #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16 /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */ #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0 /***********************************/ -/* MC_CMD_GET_VI_COUNT +/* MC_CMD_GET_VI_ALLOC_INFO + * Get information about number of VI's and base VI number allocated to this + * function. */ -#define MC_CMD_GET_VI_COUNT 0x69 +#define MC_CMD_GET_VI_ALLOC_INFO 0x8d +#undef MC_CMD_0x8d_PRIVILEGE_CTG -/* MC_CMD_GET_VI_COUNT_IN msgrequest */ -#define MC_CMD_GET_VI_COUNT_IN_LEN 0 +#define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL -/* MC_CMD_GET_VI_COUNT_OUT msgresponse */ -#define MC_CMD_GET_VI_COUNT_OUT_LEN 4 -#define MC_CMD_GET_VI_COUNT_OUT_VI_COUNT_OFST 0 +/* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */ +#define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0 - -/***********************************/ -/* MC_CMD_GET_VECTOR_CFG +/* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */ +#define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12 +/* The number of VIs allocated on this function */ +#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0 +/* The base absolute VI number allocated to this function. Required to + * correctly interpret wakeup events. */ -#define MC_CMD_GET_VECTOR_CFG 0x70 +#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4 +/* Function's port vi_shift value (always 0 on Huntington) */ +#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8 -/* MC_CMD_GET_VECTOR_CFG_IN msgrequest */ -#define MC_CMD_GET_VECTOR_CFG_IN_LEN 0 -/* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */ -#define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12 -#define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0 -#define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4 -#define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 - - /***********************************/ -/* MC_CMD_SET_VECTOR_CFG +/* MC_CMD_DUMP_VI_STATE + * For CmdClient use. Dump pertinent information on a specific absolute VI. */ -#define MC_CMD_SET_VECTOR_CFG 0x71 +#define MC_CMD_DUMP_VI_STATE 0x8e +#undef MC_CMD_0x8e_PRIVILEGE_CTG -/* MC_CMD_SET_VECTOR_CFG_IN msgrequest */ -#define MC_CMD_SET_VECTOR_CFG_IN_LEN 12 -#define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0 -#define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4 -#define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8 +#define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL -/* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ -#define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 +/* MC_CMD_DUMP_VI_STATE_IN msgrequest */ +#define MC_CMD_DUMP_VI_STATE_IN_LEN 4 +/* The VI number to query. */ +#define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0 +/* MC_CMD_DUMP_VI_STATE_OUT msgresponse */ +#define MC_CMD_DUMP_VI_STATE_OUT_LEN 96 +/* The PF part of the function owning this VI. */ +#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0 +#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2 +/* The VF part of the function owning this VI. */ +#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2 +#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2 +/* Base of VIs allocated to this function. */ +#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4 +#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2 +/* Count of VIs allocated to the owner function. */ +#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6 +#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2 +/* Base interrupt vector allocated to this function. */ +#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8 +#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2 +/* Number of interrupt vectors allocated to this function. */ +#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10 +#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2 +/* Raw evq ptr table data. */ +#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16 +/* Raw evq timer table data. */ +#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24 +/* Combined metadata field. */ +#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8 +/* TXDPCPU raw table data for queue. */ +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36 +/* TXDPCPU raw table data for queue. */ +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44 +/* TXDPCPU raw table data for queue. */ +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52 +/* Combined metadata field. */ +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24 +/* RXDPCPU raw table data for queue. */ +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68 +/* RXDPCPU raw table data for queue. */ +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76 +/* Reserved, currently 0. */ +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84 +/* Combined metadata field. */ +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32 +#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8 + /***********************************/ -/* MC_CMD_ALLOC_PIOBUF +/* MC_CMD_ALLOC_PIOBUF + * Allocate a push I/O buffer for later use with a tx queue. */ -#define MC_CMD_ALLOC_PIOBUF 0x72 +#define MC_CMD_ALLOC_PIOBUF 0x8f +#undef MC_CMD_0x8f_PRIVILEGE_CTG +#define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD + /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */ #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0 /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */ #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4 +/* Handle for allocated push I/O buffer. */ #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0 /***********************************/ -/* MC_CMD_FREE_PIOBUF +/* MC_CMD_FREE_PIOBUF + * Free a push I/O buffer. */ -#define MC_CMD_FREE_PIOBUF 0x73 +#define MC_CMD_FREE_PIOBUF 0x90 +#undef MC_CMD_0x90_PRIVILEGE_CTG +#define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD + /* MC_CMD_FREE_PIOBUF_IN msgrequest */ #define MC_CMD_FREE_PIOBUF_IN_LEN 4 +/* Handle for allocated push I/O buffer. */ #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 /* MC_CMD_FREE_PIOBUF_OUT msgresponse */ #define MC_CMD_FREE_PIOBUF_OUT_LEN 0 /***********************************/ -/* MC_CMD_V2_EXTN +/* MC_CMD_GET_VI_TLP_PROCESSING + * Get TLP steering and ordering information for a VI. */ -#define MC_CMD_V2_EXTN 0x7f +#define MC_CMD_GET_VI_TLP_PROCESSING 0xb0 +#undef MC_CMD_0xb0_PRIVILEGE_CTG +#define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */ +#define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4 +/* VI number to get information for. */ +#define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 + +/* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */ +#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4 +/* Transaction processing steering hint 1 for use with the Rx Queue. */ +#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0 +#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1 +/* Transaction processing steering hint 2 for use with the Ev Queue. */ +#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1 +#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1 +/* Use Relaxed ordering model for TLPs on this VI. */ +#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16 +#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1 +/* Use ID based ordering for TLPs on this VI. */ +#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17 +#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1 +/* Set no snoop bit for TLPs on this VI. */ +#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18 +#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1 +/* Enable TPH for TLPs on this VI. */ +#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19 +#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1 +#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0 + + +/***********************************/ +/* MC_CMD_SET_VI_TLP_PROCESSING + * Set TLP steering and ordering information for a VI. + */ +#define MC_CMD_SET_VI_TLP_PROCESSING 0xb1 +#undef MC_CMD_0xb1_PRIVILEGE_CTG + +#define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */ +#define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8 +/* VI number to set information for. */ +#define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 +/* Transaction processing steering hint 1 for use with the Rx Queue. */ +#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4 +#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1 +/* Transaction processing steering hint 2 for use with the Ev Queue. */ +#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5 +#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1 +/* Use Relaxed ordering model for TLPs on this VI. */ +#define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48 +#define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1 +/* Use ID based ordering for TLPs on this VI. */ +#define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49 +#define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1 +/* Set the no snoop bit for TLPs on this VI. */ +#define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50 +#define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1 +/* Enable TPH for TLPs on this VI. */ +#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51 +#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1 +#define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4 + +/* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */ +#define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_GET_TLP_PROCESSING_GLOBALS + * Get global PCIe steering and transaction processing configuration. + */ +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc +#undef MC_CMD_0xbc_PRIVILEGE_CTG + +#define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */ +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 +/* enum: MISC. */ +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0 +/* enum: IDO. */ +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1 +/* enum: RO. */ +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2 +/* enum: TPH Type. */ +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3 + +/* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0 +/* Enum values, see field(s): */ +/* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ +/* Amalgamated TLP info word. */ +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9 +#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23 + + +/***********************************/ +/* MC_CMD_SET_TLP_PROCESSING_GLOBALS + * Set global PCIe steering and transaction processing configuration. + */ +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd +#undef MC_CMD_0xbd_PRIVILEGE_CTG + +#define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */ +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 +/* Enum values, see field(s): */ +/* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ +/* Amalgamated TLP info word. */ +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10 +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22 + +/* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ +#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_SATELLITE_DOWNLOAD + * Download a new set of images to the satellite CPUs from the host. + */ +#define MC_CMD_SATELLITE_DOWNLOAD 0x91 +#undef MC_CMD_0x91_PRIVILEGE_CTG + +#define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs + * are subtle, and so downloads must proceed in a number of phases. + * + * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0. + * + * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download + * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should + * be a checksum (a simple 32-bit sum) of the transferred data. An individual + * download may be aborted using CHUNK_ID_ABORT. + * + * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15), + * similar to PHASE_IMEMS. + * + * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0. + * + * After any error (a requested abort is not considered to be an error) the + * sequence must be restarted from PHASE_RESET. + */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20 +#define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252 +#define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num)) +/* Download phase. (Note: the IDLE phase is used internally and is never valid + * in a command from the host.) + */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0 +#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */ +/* Target for download. (These match the blob numbers defined in + * mc_flash_layout.h.) + */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4 +/* enum: Valid in phase 2 (PHASE_IMEMS) only */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0 +/* enum: Valid in phase 2 (PHASE_IMEMS) only */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1 +/* enum: Valid in phase 2 (PHASE_IMEMS) only */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2 +/* enum: Valid in phase 2 (PHASE_IMEMS) only */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3 +/* enum: Valid in phase 2 (PHASE_IMEMS) only */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4 +/* enum: Valid in phase 2 (PHASE_IMEMS) only */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5 +/* enum: Valid in phase 2 (PHASE_IMEMS) only */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6 +/* enum: Valid in phase 2 (PHASE_IMEMS) only */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7 +/* enum: Valid in phase 2 (PHASE_IMEMS) only */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8 +/* enum: Valid in phase 2 (PHASE_IMEMS) only */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9 +/* enum: Valid in phase 2 (PHASE_IMEMS) only */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa +/* enum: Valid in phase 2 (PHASE_IMEMS) only */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb +/* enum: Valid in phase 3 (PHASE_VECTORS) only */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc +/* enum: Valid in phase 3 (PHASE_VECTORS) only */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd +/* enum: Valid in phase 3 (PHASE_VECTORS) only */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe +/* enum: Valid in phase 3 (PHASE_VECTORS) only */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf +/* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff +/* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8 +/* enum: Last chunk, containing checksum rather than data */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff +/* enum: Abort download of this item */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe +/* Length of this chunk in bytes */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12 +/* Data for this chunk */ +#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16 +#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4 +#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1 +#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59 + +/* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */ +#define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8 +/* Same as MC_CMD_ERR field, but included as 0 in success cases */ +#define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0 +/* Extra status information */ +#define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4 +/* enum: Code download OK, completed. */ +#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0 +/* enum: Code download aborted as requested. */ +#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1 +/* enum: Code download OK so far, send next chunk. */ +#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2 +/* enum: Download phases out of sequence */ +#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100 +/* enum: Bad target for this phase */ +#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101 +/* enum: Chunk ID out of sequence */ +#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200 +/* enum: Chunk length zero or too large */ +#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201 +/* enum: Checksum was incorrect */ +#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300 + + +/***********************************/ +/* MC_CMD_GET_CAPABILITIES + * Get device capabilities. + * + * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to + * reference inherent device capabilities as opposed to current NVRAM config. + */ +#define MC_CMD_GET_CAPABILITIES 0xbe +#undef MC_CMD_0xbe_PRIVILEGE_CTG + +#define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_GET_CAPABILITIES_IN msgrequest */ +#define MC_CMD_GET_CAPABILITIES_IN_LEN 0 + +/* MC_CMD_GET_CAPABILITIES_OUT msgresponse */ +#define MC_CMD_GET_CAPABILITIES_OUT_LEN 20 +/* First word of flags. */ +#define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0 +#define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 +#define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13 +#define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14 +#define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19 +#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21 +#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26 +#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27 +#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 +#define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30 +#define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31 +#define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1 +/* RxDPCPU firmware id. */ +#define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2 +/* enum: Standard RXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0 +/* enum: Low latency RXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1 +/* enum: Packed stream RXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2 +/* enum: BIST RXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a +/* enum: RXDP Test firmware image 1 */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 +/* enum: RXDP Test firmware image 2 */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 +/* enum: RXDP Test firmware image 3 */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 +/* enum: RXDP Test firmware image 4 */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 +/* enum: RXDP Test firmware image 5 */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105 +/* enum: RXDP Test firmware image 6 */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 +/* enum: RXDP Test firmware image 7 */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 +/* enum: RXDP Test firmware image 8 */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 +/* TxDPCPU firmware id. */ +#define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6 +#define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2 +/* enum: Standard TXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0 +/* enum: Low latency TXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1 +/* enum: High packet rate TXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3 +/* enum: BIST TXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d +/* enum: TXDP Test firmware image 1 */ +#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 +/* enum: TXDP Test firmware image 2 */ +#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 +#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8 +#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2 +#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0 +#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12 +#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12 +#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 +/* enum: reserved value - do not use (may indicate alternative interpretation + * of REV field in future) + */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0 +/* enum: Trivial RX PD firmware for early Huntington development (Huntington + * development only) + */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 +/* enum: RX PD firmware with approximately Siena-compatible behaviour + * (Huntington development only) + */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 +/* enum: Virtual switching (full feature) RX PD production firmware */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3 +/* enum: siena_compat variant RX PD firmware using PM rather than MAC + * (Huntington development only) + */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 +/* enum: Low latency RX PD production firmware */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 +/* enum: Packed stream RX PD production firmware */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 +/* enum: RX PD firmware handling layer 2 only for high packet rate performance + * tests (Medford development only) + */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 +/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe +/* enum: RX PD firmware parsing but not filtering network overlay tunnel + * encapsulations (Medford development only) + */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf +#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10 +#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2 +#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0 +#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12 +#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12 +#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 +/* enum: reserved value - do not use (may indicate alternative interpretation + * of REV field in future) + */ +#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0 +/* enum: Trivial TX PD firmware for early Huntington development (Huntington + * development only) + */ +#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 +/* enum: TX PD firmware with approximately Siena-compatible behaviour + * (Huntington development only) + */ +#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 +/* enum: Virtual switching (full feature) TX PD production firmware */ +#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3 +/* enum: siena_compat variant TX PD firmware using PM rather than MAC + * (Huntington development only) + */ +#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 +#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ +/* enum: TX PD firmware handling layer 2 only for high packet rate performance + * tests (Medford development only) + */ +#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 +/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ +#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe +/* Hardware capabilities of NIC */ +#define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12 +/* Licensed capabilities */ +#define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16 + + +/***********************************/ +/* MC_CMD_V2_EXTN + * Encapsulation for a v2 extended command + */ +#define MC_CMD_V2_EXTN 0x7f + /* MC_CMD_V2_EXTN_IN msgrequest */ #define MC_CMD_V2_EXTN_IN_LEN 4 +/* the extended command number */ #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15 #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15 #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1 +/* the actual length of the encapsulated command (which is not in the v1 + * header) + */ #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10 #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26 #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6 /***********************************/ -/* MC_CMD_TCM_BUCKET_ALLOC +/* MC_CMD_TCM_BUCKET_ALLOC + * Allocate a pacer bucket (for qau rp or a snapper test) */ -#define MC_CMD_TCM_BUCKET_ALLOC 0x80 +#define MC_CMD_TCM_BUCKET_ALLOC 0xb2 +#undef MC_CMD_0xb2_PRIVILEGE_CTG +#define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */ #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0 /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */ #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4 +/* the bucket id */ #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0 /***********************************/ -/* MC_CMD_TCM_BUCKET_FREE +/* MC_CMD_TCM_BUCKET_FREE + * Free a pacer bucket */ -#define MC_CMD_TCM_BUCKET_FREE 0x81 +#define MC_CMD_TCM_BUCKET_FREE 0xb3 +#undef MC_CMD_0xb3_PRIVILEGE_CTG +#define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */ #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4 +/* the bucket id */ #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0 /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */ #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0 /***********************************/ -/* MC_CMD_TCM_BUCKET_INIT +/* MC_CMD_TCM_BUCKET_INIT + * Initialise pacer bucket with a given rate */ -#define MC_CMD_TCM_BUCKET_INIT 0x82 +#define MC_CMD_TCM_BUCKET_INIT 0xb4 +#undef MC_CMD_0xb4_PRIVILEGE_CTG +#define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */ #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8 +/* the bucket id */ #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0 +/* the rate in mbps */ #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4 +/* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */ +#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12 +/* the bucket id */ +#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0 +/* the rate in mbps */ +#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4 +/* the desired maximum fill level */ +#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8 + /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */ #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0 /***********************************/ -/* MC_CMD_TCM_TXQ_INIT +/* MC_CMD_TCM_TXQ_INIT + * Initialise txq in pacer with given options or set options */ -#define MC_CMD_TCM_TXQ_INIT 0x83 +#define MC_CMD_TCM_TXQ_INIT 0xb5 +#undef MC_CMD_0xb5_PRIVILEGE_CTG +#define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL + /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */ #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28 +/* the txq id */ #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0 +/* the static priority associated with the txq */ #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4 +/* bitmask of the priority queues this txq is inserted into when inserted. */ #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8 +#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0 +#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 +#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1 +#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1 +#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2 +#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1 +/* the reaction point (RP) bucket */ #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12 +/* an already reserved bucket (typically set to bucket associated with outer + * vswitch) + */ #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16 +/* an already reserved bucket (typically set to bucket associated with inner + * vswitch) + */ #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20 +/* the min bucket (typically for ETS/minimum bandwidth) */ #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24 +/* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */ +#define MC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32 +/* the txq id */ +#define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0 +/* the static priority associated with the txq */ +#define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4 +/* bitmask of the priority queues this txq is inserted into when inserted. */ +#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8 +#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0 +#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 +#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1 +#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1 +#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2 +#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1 +/* the reaction point (RP) bucket */ +#define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12 +/* an already reserved bucket (typically set to bucket associated with outer + * vswitch) + */ +#define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16 +/* an already reserved bucket (typically set to bucket associated with inner + * vswitch) + */ +#define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20 +/* the min bucket (typically for ETS/minimum bandwidth) */ +#define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24 +/* the static priority associated with the txq */ +#define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28 + /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */ #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_LINK_PIOBUF + * Link a push I/O buffer to a TxQ + */ +#define MC_CMD_LINK_PIOBUF 0x92 +#undef MC_CMD_0x92_PRIVILEGE_CTG + +#define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD + +/* MC_CMD_LINK_PIOBUF_IN msgrequest */ +#define MC_CMD_LINK_PIOBUF_IN_LEN 8 +/* Handle for allocated push I/O buffer. */ +#define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 +/* Function Local Instance (VI) number. */ +#define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4 + +/* MC_CMD_LINK_PIOBUF_OUT msgresponse */ +#define MC_CMD_LINK_PIOBUF_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_UNLINK_PIOBUF + * Unlink a push I/O buffer from a TxQ + */ +#define MC_CMD_UNLINK_PIOBUF 0x93 +#undef MC_CMD_0x93_PRIVILEGE_CTG + +#define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD + +/* MC_CMD_UNLINK_PIOBUF_IN msgrequest */ +#define MC_CMD_UNLINK_PIOBUF_IN_LEN 4 +/* Function Local Instance (VI) number. */ +#define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0 + +/* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */ +#define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_VSWITCH_ALLOC + * allocate and initialise a v-switch. + */ +#define MC_CMD_VSWITCH_ALLOC 0x94 +#undef MC_CMD_0x94_PRIVILEGE_CTG + +#define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_VSWITCH_ALLOC_IN msgrequest */ +#define MC_CMD_VSWITCH_ALLOC_IN_LEN 16 +/* The port to connect to the v-switch's upstream port. */ +#define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 +/* The type of v-switch to create. */ +#define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4 +/* enum: VLAN */ +#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1 +/* enum: VEB */ +#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2 +/* enum: VEPA (obsolete) */ +#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3 +/* enum: MUX */ +#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4 +/* enum: Snapper specific; semantics TBD */ +#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5 +/* Flags controlling v-port creation */ +#define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8 +#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 +#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 +/* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators, + * this must be one or greated, and the attached v-ports must have exactly this + * number of tags. For other v-switch types, this must be zero of greater, and + * is an upper limit on the number of VLAN tags for attached v-ports. An error + * will be returned if existing configuration means we can't support attached + * v-ports with this number of tags. + */ +#define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 + +/* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */ +#define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_VSWITCH_FREE + * de-allocate a v-switch. + */ +#define MC_CMD_VSWITCH_FREE 0x95 +#undef MC_CMD_0x95_PRIVILEGE_CTG + +#define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_VSWITCH_FREE_IN msgrequest */ +#define MC_CMD_VSWITCH_FREE_IN_LEN 4 +/* The port to which the v-switch is connected. */ +#define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0 + +/* MC_CMD_VSWITCH_FREE_OUT msgresponse */ +#define MC_CMD_VSWITCH_FREE_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_VPORT_ALLOC + * allocate a v-port. + */ +#define MC_CMD_VPORT_ALLOC 0x96 +#undef MC_CMD_0x96_PRIVILEGE_CTG + +#define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_VPORT_ALLOC_IN msgrequest */ +#define MC_CMD_VPORT_ALLOC_IN_LEN 20 +/* The port to which the v-switch is connected. */ +#define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 +/* The type of the new v-port. */ +#define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4 +/* enum: VLAN (obsolete) */ +#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1 +/* enum: VEB (obsolete) */ +#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2 +/* enum: VEPA (obsolete) */ +#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3 +/* enum: A normal v-port receives packets which match a specified MAC and/or + * VLAN. + */ +#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4 +/* enum: An expansion v-port packets traffic which don't match any other + * v-port. + */ +#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5 +/* enum: An test v-port receives packets which match any filters installed by + * its downstream components. + */ +#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6 +/* Flags controlling v-port creation */ +#define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8 +#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 +#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 +/* The number of VLAN tags to insert/remove. An error will be returned if + * incompatible with the number of VLAN tags specified for the upstream + * v-switch. + */ +#define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 +/* The actual VLAN tags to insert/remove */ +#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16 +#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0 +#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16 +#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16 +#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16 + +/* MC_CMD_VPORT_ALLOC_OUT msgresponse */ +#define MC_CMD_VPORT_ALLOC_OUT_LEN 4 +/* The handle of the new v-port */ +#define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0 + + +/***********************************/ +/* MC_CMD_VPORT_FREE + * de-allocate a v-port. + */ +#define MC_CMD_VPORT_FREE 0x97 +#undef MC_CMD_0x97_PRIVILEGE_CTG + +#define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_VPORT_FREE_IN msgrequest */ +#define MC_CMD_VPORT_FREE_IN_LEN 4 +/* The handle of the v-port */ +#define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0 + +/* MC_CMD_VPORT_FREE_OUT msgresponse */ +#define MC_CMD_VPORT_FREE_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_VADAPTOR_ALLOC + * allocate a v-adaptor. + */ +#define MC_CMD_VADAPTOR_ALLOC 0x98 +#undef MC_CMD_0x98_PRIVILEGE_CTG + +#define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */ +#define MC_CMD_VADAPTOR_ALLOC_IN_LEN 30 +/* The port to connect to the v-adaptor's port. */ +#define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 +/* Flags controlling v-adaptor creation */ +#define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8 +#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0 +#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1 +/* The number of VLAN tags to strip on receive */ +#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12 +/* The number of VLAN tags to transparently insert/remove. */ +#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16 +/* The actual VLAN tags to insert/remove */ +#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20 +#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0 +#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16 +#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16 +#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16 +/* The MAC address to assign to this v-adaptor */ +#define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24 +#define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6 +/* enum: Derive the MAC address from the upstream port */ +#define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0 + +/* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */ +#define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_VADAPTOR_FREE + * de-allocate a v-adaptor. + */ +#define MC_CMD_VADAPTOR_FREE 0x99 +#undef MC_CMD_0x99_PRIVILEGE_CTG + +#define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_VADAPTOR_FREE_IN msgrequest */ +#define MC_CMD_VADAPTOR_FREE_IN_LEN 4 +/* The port to which the v-adaptor is connected. */ +#define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0 + +/* MC_CMD_VADAPTOR_FREE_OUT msgresponse */ +#define MC_CMD_VADAPTOR_FREE_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_VADAPTOR_SET_MAC + * assign a new MAC address to a v-adaptor. + */ +#define MC_CMD_VADAPTOR_SET_MAC 0x5d +#undef MC_CMD_0x5d_PRIVILEGE_CTG + +#define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */ +#define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10 +/* The port to which the v-adaptor is connected. */ +#define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 +/* The new MAC address to assign to this v-adaptor */ +#define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4 +#define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6 + +/* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */ +#define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_VADAPTOR_GET_MAC + * read the MAC address assigned to a v-adaptor. + */ +#define MC_CMD_VADAPTOR_GET_MAC 0x5e +#undef MC_CMD_0x5e_PRIVILEGE_CTG + +#define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */ +#define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4 +/* The port to which the v-adaptor is connected. */ +#define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 + +/* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */ +#define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6 +/* The MAC address assigned to this v-adaptor */ +#define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0 +#define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6 + + +/***********************************/ +/* MC_CMD_EVB_PORT_ASSIGN + * assign a port to a PCI function. + */ +#define MC_CMD_EVB_PORT_ASSIGN 0x9a +#undef MC_CMD_0x9a_PRIVILEGE_CTG + +#define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */ +#define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8 +/* The port to assign. */ +#define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0 +/* The target function to modify. */ +#define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4 +#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0 +#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16 +#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16 +#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16 + +/* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */ +#define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_RDWR_A64_REGIONS + * Assign the 64 bit region addresses. + */ +#define MC_CMD_RDWR_A64_REGIONS 0x9b +#undef MC_CMD_0x9b_PRIVILEGE_CTG + +#define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */ +#define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17 +#define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0 +#define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4 +#define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8 +#define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12 +/* Write enable bits 0-3, set to write, clear to read. */ +#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128 +#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4 +#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16 +#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1 + +/* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included + * regardless of state of write bits in the request. + */ +#define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16 +#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0 +#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4 +#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8 +#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12 + + +/***********************************/ +/* MC_CMD_ONLOAD_STACK_ALLOC + * Allocate an Onload stack ID. + */ +#define MC_CMD_ONLOAD_STACK_ALLOC 0x9c +#undef MC_CMD_0x9c_PRIVILEGE_CTG + +#define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD + +/* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */ +#define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4 +/* The handle of the owning upstream port */ +#define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 + +/* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */ +#define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4 +/* The handle of the new Onload stack */ +#define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0 + + +/***********************************/ +/* MC_CMD_ONLOAD_STACK_FREE + * Free an Onload stack ID. + */ +#define MC_CMD_ONLOAD_STACK_FREE 0x9d +#undef MC_CMD_0x9d_PRIVILEGE_CTG + +#define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD + +/* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */ +#define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4 +/* The handle of the Onload stack */ +#define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0 + +/* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */ +#define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_RSS_CONTEXT_ALLOC + * Allocate an RSS context. + */ +#define MC_CMD_RSS_CONTEXT_ALLOC 0x9e +#undef MC_CMD_0x9e_PRIVILEGE_CTG + +#define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */ +#define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12 +/* The handle of the owning upstream port */ +#define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 +/* The type of context to allocate */ +#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4 +/* enum: Allocate a context for exclusive use. The key and indirection table + * must be explicitly configured. + */ +#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0 +/* enum: Allocate a context for shared use; this will spread across a range of + * queues, but the key and indirection table are pre-configured and may not be + * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64. + */ +#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1 +/* Number of queues spanned by this context, in the range 1-64; valid offsets + * in the indirection table will be in the range 0 to NUM_QUEUES-1. + */ +#define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8 + +/* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */ +#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4 +/* The handle of the new RSS context. This should be considered opaque to the + * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid + * handle. + */ +#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0 +/* enum: guaranteed invalid RSS context handle value */ +#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff + + +/***********************************/ +/* MC_CMD_RSS_CONTEXT_FREE + * Free an RSS context. + */ +#define MC_CMD_RSS_CONTEXT_FREE 0x9f +#undef MC_CMD_0x9f_PRIVILEGE_CTG + +#define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */ +#define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4 +/* The handle of the RSS context */ +#define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0 + +/* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */ +#define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_RSS_CONTEXT_SET_KEY + * Set the Toeplitz hash key for an RSS context. + */ +#define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0 +#undef MC_CMD_0xa0_PRIVILEGE_CTG + +#define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */ +#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44 +/* The handle of the RSS context */ +#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0 +/* The 40-byte Toeplitz hash key (TBD endianness issues?) */ +#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4 +#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40 + +/* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */ +#define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_RSS_CONTEXT_GET_KEY + * Get the Toeplitz hash key for an RSS context. + */ +#define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1 +#undef MC_CMD_0xa1_PRIVILEGE_CTG + +#define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */ +#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4 +/* The handle of the RSS context */ +#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0 + +/* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */ +#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44 +/* The 40-byte Toeplitz hash key (TBD endianness issues?) */ +#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4 +#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40 + + +/***********************************/ +/* MC_CMD_RSS_CONTEXT_SET_TABLE + * Set the indirection table for an RSS context. + */ +#define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2 +#undef MC_CMD_0xa2_PRIVILEGE_CTG + +#define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */ +#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132 +/* The handle of the RSS context */ +#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 +/* The 128-byte indirection table (1 byte per entry) */ +#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4 +#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128 + +/* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */ +#define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_RSS_CONTEXT_GET_TABLE + * Get the indirection table for an RSS context. + */ +#define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3 +#undef MC_CMD_0xa3_PRIVILEGE_CTG + +#define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */ +#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4 +/* The handle of the RSS context */ +#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 + +/* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */ +#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132 +/* The 128-byte indirection table (1 byte per entry) */ +#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4 +#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128 + + +/***********************************/ +/* MC_CMD_RSS_CONTEXT_SET_FLAGS + * Set various control flags for an RSS context. + */ +#define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1 +#undef MC_CMD_0xe1_PRIVILEGE_CTG + +#define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */ +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8 +/* The handle of the RSS context */ +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 +/* Hash control flags. The _EN bits are always supported. The _MODE bits only + * work when the firmware reports ADDITIONAL_RSS_MODES in + * MC_CMD_GET_CAPABILITIES and override the _EN bits if any of them are not 0. + * See the RSS_MODE structure for the meaning of the mode bits. + */ +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4 +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0 +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1 +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1 +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1 +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2 +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1 +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3 +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1 +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4 +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4 +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8 +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4 +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12 +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4 +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16 +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4 +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20 +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4 +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24 +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4 +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28 +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4 + +/* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */ +#define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_RSS_CONTEXT_GET_FLAGS + * Get various control flags for an RSS context. + */ +#define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2 +#undef MC_CMD_0xe2_PRIVILEGE_CTG + +#define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */ +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4 +/* The handle of the RSS context */ +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 + +/* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */ +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8 +/* Hash control flags. If any _MODE bits are non-zero (which will only be true + * when the firmware reports ADDITIONAL_RSS_MODES) then the _EN bits should be + * disregarded (but are guaranteed to be consistent with the _MODE bits if + * RSS_CONTEXT_SET_FLAGS has never been called for this context since it was + * allocated). + */ +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4 +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0 +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1 +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1 +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1 +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2 +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1 +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3 +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1 +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4 +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4 +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8 +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4 +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12 +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4 +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16 +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4 +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20 +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4 +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24 +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4 +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28 +#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4 + + +/***********************************/ +/* MC_CMD_DOT1P_MAPPING_ALLOC + * Allocate a .1p mapping. + */ +#define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4 +#undef MC_CMD_0xa4_PRIVILEGE_CTG + +#define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */ +#define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8 +/* The handle of the owning upstream port */ +#define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 +/* Number of queues spanned by this mapping, in the range 1-64; valid fixed + * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and + * referenced RSS contexts must span no more than this number. + */ +#define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4 + +/* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */ +#define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4 +/* The handle of the new .1p mapping. This should be considered opaque to the + * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid + * handle. + */ +#define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0 +/* enum: guaranteed invalid .1p mapping handle value */ +#define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff + + +/***********************************/ +/* MC_CMD_DOT1P_MAPPING_FREE + * Free a .1p mapping. + */ +#define MC_CMD_DOT1P_MAPPING_FREE 0xa5 +#undef MC_CMD_0xa5_PRIVILEGE_CTG + +#define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */ +#define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4 +/* The handle of the .1p mapping */ +#define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0 + +/* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */ +#define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_DOT1P_MAPPING_SET_TABLE + * Set the mapping table for a .1p mapping. + */ +#define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6 +#undef MC_CMD_0xa6_PRIVILEGE_CTG + +#define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */ +#define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36 +/* The handle of the .1p mapping */ +#define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 +/* Per-priority mappings (1 32-bit word per entry - an offset or RSS context + * handle) + */ +#define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4 +#define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32 + +/* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */ +#define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_DOT1P_MAPPING_GET_TABLE + * Get the mapping table for a .1p mapping. + */ +#define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7 +#undef MC_CMD_0xa7_PRIVILEGE_CTG + +#define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */ +#define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4 +/* The handle of the .1p mapping */ +#define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 + +/* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */ +#define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36 +/* Per-priority mappings (1 32-bit word per entry - an offset or RSS context + * handle) + */ +#define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4 +#define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32 + + +/***********************************/ +/* MC_CMD_GET_VECTOR_CFG + * Get Interrupt Vector config for this PF. + */ +#define MC_CMD_GET_VECTOR_CFG 0xbf +#undef MC_CMD_0xbf_PRIVILEGE_CTG + +#define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_GET_VECTOR_CFG_IN msgrequest */ +#define MC_CMD_GET_VECTOR_CFG_IN_LEN 0 + +/* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */ +#define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12 +/* Base absolute interrupt vector number. */ +#define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0 +/* Number of interrupt vectors allocate to this PF. */ +#define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4 +/* Number of interrupt vectors to allocate per VF. */ +#define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 + + +/***********************************/ +/* MC_CMD_SET_VECTOR_CFG + * Set Interrupt Vector config for this PF. + */ +#define MC_CMD_SET_VECTOR_CFG 0xc0 +#undef MC_CMD_0xc0_PRIVILEGE_CTG + +#define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_SET_VECTOR_CFG_IN msgrequest */ +#define MC_CMD_SET_VECTOR_CFG_IN_LEN 12 +/* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to + * let the system find a suitable base. + */ +#define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0 +/* Number of interrupt vectors allocate to this PF. */ +#define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4 +/* Number of interrupt vectors to allocate per VF. */ +#define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8 + +/* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ +#define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_VPORT_ADD_MAC_ADDRESS + * Add a MAC address to a v-port + */ +#define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8 +#undef MC_CMD_0xa8_PRIVILEGE_CTG + +#define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */ +#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10 +/* The handle of the v-port */ +#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0 +/* MAC address to add */ +#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4 +#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6 + +/* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */ +#define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_VPORT_DEL_MAC_ADDRESS + * Delete a MAC address from a v-port + */ +#define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9 +#undef MC_CMD_0xa9_PRIVILEGE_CTG + +#define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */ +#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10 +/* The handle of the v-port */ +#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0 +/* MAC address to add */ +#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4 +#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6 + +/* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */ +#define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_VPORT_GET_MAC_ADDRESSES + * Delete a MAC address from a v-port + */ +#define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa +#undef MC_CMD_0xaa_PRIVILEGE_CTG + +#define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */ +#define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4 +/* The handle of the v-port */ +#define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0 + +/* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */ +#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4 +#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250 +#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num)) +/* The number of MAC addresses returned */ +#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0 +/* Array of MAC addresses */ +#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4 +#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6 +#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0 +#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41 + + +/***********************************/ +/* MC_CMD_DUMP_BUFTBL_ENTRIES + * Dump buffer table entries, mainly for command client debug use. Dumps + * absolute entries, and does not use chunk handles. All entries must be in + * range, and used for q page mapping, Although the latter restriction may be + * lifted in future. + */ +#define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab +#undef MC_CMD_0xab_PRIVILEGE_CTG + +#define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */ +#define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8 +/* Index of the first buffer table entry. */ +#define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0 +/* Number of buffer table entries to dump. */ +#define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4 + +/* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */ +#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12 +#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252 +#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num)) +/* Raw buffer table entries, layed out as BUFTBL_ENTRY. */ +#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0 +#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12 +#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1 +#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21 + + +/***********************************/ +/* MC_CMD_SET_RXDP_CONFIG + * Set global RXDP configuration settings + */ +#define MC_CMD_SET_RXDP_CONFIG 0xc1 +#undef MC_CMD_0xc1_PRIVILEGE_CTG + +#define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */ +#define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4 +#define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0 +#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0 +#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1 + +/* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */ +#define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_GET_RXDP_CONFIG + * Get global RXDP configuration settings + */ +#define MC_CMD_GET_RXDP_CONFIG 0xc2 +#undef MC_CMD_0xc2_PRIVILEGE_CTG + +#define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */ +#define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0 + +/* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */ +#define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4 +#define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0 +#define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0 +#define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1 + + +/***********************************/ +/* MC_CMD_GET_CLOCK + * Return the system and PDCPU clock frequencies. + */ +#define MC_CMD_GET_CLOCK 0xac +#undef MC_CMD_0xac_PRIVILEGE_CTG + +#define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_GET_CLOCK_IN msgrequest */ +#define MC_CMD_GET_CLOCK_IN_LEN 0 + +/* MC_CMD_GET_CLOCK_OUT msgresponse */ +#define MC_CMD_GET_CLOCK_OUT_LEN 8 +/* System frequency, MHz */ +#define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0 +/* DPCPU frequency, MHz */ +#define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4 + + +/***********************************/ +/* MC_CMD_SET_CLOCK + * Control the system and DPCPU clock frequencies. Changes are lost reboot. + */ +#define MC_CMD_SET_CLOCK 0xad +#undef MC_CMD_0xad_PRIVILEGE_CTG + +#define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_SET_CLOCK_IN msgrequest */ +#define MC_CMD_SET_CLOCK_IN_LEN 28 +/* Requested frequency in MHz for system clock domain */ +#define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0 +/* enum: Leave the system clock domain frequency unchanged */ +#define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0 +/* Requested frequency in MHz for inter-core clock domain */ +#define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4 +/* enum: Leave the inter-core clock domain frequency unchanged */ +#define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0 +/* Requested frequency in MHz for DPCPU clock domain */ +#define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8 +/* enum: Leave the DPCPU clock domain frequency unchanged */ +#define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0 +/* Requested frequency in MHz for PCS clock domain */ +#define MC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12 +/* enum: Leave the PCS clock domain frequency unchanged */ +#define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0 +/* Requested frequency in MHz for MC clock domain */ +#define MC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16 +/* enum: Leave the MC clock domain frequency unchanged */ +#define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0 +/* Requested frequency in MHz for rmon clock domain */ +#define MC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20 +/* enum: Leave the rmon clock domain frequency unchanged */ +#define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0 +/* Requested frequency in MHz for vswitch clock domain */ +#define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24 +/* enum: Leave the vswitch clock domain frequency unchanged */ +#define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0 + +/* MC_CMD_SET_CLOCK_OUT msgresponse */ +#define MC_CMD_SET_CLOCK_OUT_LEN 28 +/* Resulting system frequency in MHz */ +#define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0 +/* enum: The system clock domain doesn't exist */ +#define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0 +/* Resulting inter-core frequency in MHz */ +#define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4 +/* enum: The inter-core clock domain doesn't exist / isn't used */ +#define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0 +/* Resulting DPCPU frequency in MHz */ +#define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8 +/* enum: The dpcpu clock domain doesn't exist */ +#define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0 +/* Resulting PCS frequency in MHz */ +#define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12 +/* enum: The PCS clock domain doesn't exist / isn't controlled */ +#define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0 +/* Resulting MC frequency in MHz */ +#define MC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16 +/* enum: The MC clock domain doesn't exist / isn't controlled */ +#define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0 +/* Resulting rmon frequency in MHz */ +#define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20 +/* enum: The rmon clock domain doesn't exist / isn't controlled */ +#define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0 +/* Resulting vswitch frequency in MHz */ +#define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24 +/* enum: The vswitch clock domain doesn't exist / isn't controlled */ +#define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0 + + +/***********************************/ +/* MC_CMD_DPCPU_RPC + * Send an arbitrary DPCPU message. + */ +#define MC_CMD_DPCPU_RPC 0xae +#undef MC_CMD_0xae_PRIVILEGE_CTG + +#define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_DPCPU_RPC_IN msgrequest */ +#define MC_CMD_DPCPU_RPC_IN_LEN 36 +#define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0 +/* enum: RxDPCPU0 */ +#define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0 +/* enum: TxDPCPU0 */ +#define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1 +/* enum: TxDPCPU1 */ +#define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2 +/* enum: RxDPCPU1 (Medford only) */ +#define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3 +/* enum: RxDPCPU (will be for the calling function; for now, just an alias of + * DPCPU_RX0) + */ +#define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80 +/* enum: TxDPCPU (will be for the calling function; for now, just an alias of + * DPCPU_TX0) + */ +#define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81 +/* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be + * initialised to zero + */ +#define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4 +#define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32 +#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8 +#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8 +#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */ +#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */ +#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */ +#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */ +#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */ +#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */ +#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */ +#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */ +#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */ +#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16 +#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16 +#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16 +#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16 +#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48 +#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16 +#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16 +#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240 +#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16 +#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16 +#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */ +#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */ +#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */ +#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */ +#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */ +#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48 +#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16 +#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64 +#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16 +#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80 +#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16 +#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16 +#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16 +#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */ +#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */ +#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */ +#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64 +#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16 +#define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12 +#define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24 +/* Register data to write. Only valid in write/write-read. */ +#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16 +/* Register address. */ +#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20 + +/* MC_CMD_DPCPU_RPC_OUT msgresponse */ +#define MC_CMD_DPCPU_RPC_OUT_LEN 36 +#define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0 +/* DATA */ +#define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4 +#define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32 +#define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32 +#define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16 +#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48 +#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16 +#define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12 +#define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24 +#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12 +#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16 +#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20 +#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24 + + +/***********************************/ +/* MC_CMD_TRIGGER_INTERRUPT + * Trigger an interrupt by prodding the BIU. + */ +#define MC_CMD_TRIGGER_INTERRUPT 0xe3 +#undef MC_CMD_0xe3_PRIVILEGE_CTG + +#define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */ +#define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4 +/* Interrupt level relative to base for function. */ +#define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0 + +/* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */ +#define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_SHMBOOT_OP + * Special operations to support (for now) shmboot. + */ +#define MC_CMD_SHMBOOT_OP 0xe6 +#undef MC_CMD_0xe6_PRIVILEGE_CTG + +#define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_SHMBOOT_OP_IN msgrequest */ +#define MC_CMD_SHMBOOT_OP_IN_LEN 4 +/* Identifies the operation to perform */ +#define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0 +/* enum: Copy slave_data section to the slave core. (Greenport only) */ +#define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0 + +/* MC_CMD_SHMBOOT_OP_OUT msgresponse */ +#define MC_CMD_SHMBOOT_OP_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_CAP_BLK_READ + * Read multiple 64bit words from capture block memory + */ +#define MC_CMD_CAP_BLK_READ 0xe7 +#undef MC_CMD_0xe7_PRIVILEGE_CTG + +#define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_CAP_BLK_READ_IN msgrequest */ +#define MC_CMD_CAP_BLK_READ_IN_LEN 12 +#define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0 +#define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4 +#define MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8 + +/* MC_CMD_CAP_BLK_READ_OUT msgresponse */ +#define MC_CMD_CAP_BLK_READ_OUT_LENMIN 8 +#define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248 +#define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num)) +#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0 +#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8 +#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0 +#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4 +#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1 +#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31 + + +/***********************************/ +/* MC_CMD_DUMP_DO + * Take a dump of the DUT state + */ +#define MC_CMD_DUMP_DO 0xe8 +#undef MC_CMD_0xe8_PRIVILEGE_CTG + +#define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_DUMP_DO_IN msgrequest */ +#define MC_CMD_DUMP_DO_IN_LEN 52 +#define MC_CMD_DUMP_DO_IN_PADDING_OFST 0 +#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4 +#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */ +#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */ +#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 +#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */ +#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */ +#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */ +#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */ +#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 +#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 +#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 +#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 +#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 +#define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */ +#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 +#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 +#define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */ +#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 +/* enum: The uart port this command was received over (if using a uart + * transport) + */ +#define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff +#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 +#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28 +#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */ +#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */ +#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 +/* Enum values, see field(s): */ +/* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ +#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 +#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 +#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 +#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 +#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 +#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 +#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 +#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 +#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 + +/* MC_CMD_DUMP_DO_OUT msgresponse */ +#define MC_CMD_DUMP_DO_OUT_LEN 4 +#define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0 + + +/***********************************/ +/* MC_CMD_DUMP_CONFIGURE_UNSOLICITED + * Configure unsolicited dumps + */ +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9 +#undef MC_CMD_0xe9_PRIVILEGE_CTG + +#define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */ +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52 +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0 +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4 +/* Enum values, see field(s): */ +/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */ +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 +/* Enum values, see field(s): */ +/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28 +/* Enum values, see field(s): */ +/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */ +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 +/* Enum values, see field(s): */ +/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 +#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 + + +/***********************************/ +/* MC_CMD_SET_PSU + * Adjusts power supply parameters. This is a warranty-voiding operation. + * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if + * the parameter is out of range. + */ +#define MC_CMD_SET_PSU 0xea +#undef MC_CMD_0xea_PRIVILEGE_CTG + +#define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_SET_PSU_IN msgrequest */ +#define MC_CMD_SET_PSU_IN_LEN 12 +#define MC_CMD_SET_PSU_IN_PARAM_OFST 0 +#define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */ +#define MC_CMD_SET_PSU_IN_RAIL_OFST 4 +#define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */ +#define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */ +/* desired value, eg voltage in mV */ +#define MC_CMD_SET_PSU_IN_VALUE_OFST 8 + +/* MC_CMD_SET_PSU_OUT msgresponse */ +#define MC_CMD_SET_PSU_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_GET_FUNCTION_INFO + * Get function information. PF and VF number. + */ +#define MC_CMD_GET_FUNCTION_INFO 0xec +#undef MC_CMD_0xec_PRIVILEGE_CTG + +#define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */ +#define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0 + +/* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */ +#define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8 +#define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0 +#define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4 + + +/***********************************/ +/* MC_CMD_ENABLE_OFFLINE_BIST + * Enters offline BIST mode. All queues are torn down, chip enters quiescent + * mode, calling function gets exclusive MCDI ownership. The only way out is + * reboot. + */ +#define MC_CMD_ENABLE_OFFLINE_BIST 0xed +#undef MC_CMD_0xed_PRIVILEGE_CTG + +#define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */ +#define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0 + +/* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */ +#define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_UART_SEND_DATA + * Send checksummed[sic] block of data over the uart. Response is a placeholder + * should we wish to make this reliable; currently requests are fire-and- + * forget. + */ +#define MC_CMD_UART_SEND_DATA 0xee +#undef MC_CMD_0xee_PRIVILEGE_CTG + +#define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_UART_SEND_DATA_OUT msgrequest */ +#define MC_CMD_UART_SEND_DATA_OUT_LENMIN 16 +#define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252 +#define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num)) +/* CRC32 over OFFSET, LENGTH, RESERVED, DATA */ +#define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0 +/* Offset at which to write the data */ +#define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4 +/* Length of data */ +#define MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8 +/* Reserved for future use */ +#define MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12 +#define MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16 +#define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1 +#define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0 +#define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236 + +/* MC_CMD_UART_SEND_DATA_IN msgresponse */ +#define MC_CMD_UART_SEND_DATA_IN_LEN 0 + + +/***********************************/ +/* MC_CMD_UART_RECV_DATA + * Request checksummed[sic] block of data over the uart. Only a placeholder, + * subject to change and not currently implemented. + */ +#define MC_CMD_UART_RECV_DATA 0xef +#undef MC_CMD_0xef_PRIVILEGE_CTG + +#define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_UART_RECV_DATA_OUT msgrequest */ +#define MC_CMD_UART_RECV_DATA_OUT_LEN 16 +/* CRC32 over OFFSET, LENGTH, RESERVED */ +#define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0 +/* Offset from which to read the data */ +#define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4 +/* Length of data */ +#define MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8 +/* Reserved for future use */ +#define MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12 + +/* MC_CMD_UART_RECV_DATA_IN msgresponse */ +#define MC_CMD_UART_RECV_DATA_IN_LENMIN 16 +#define MC_CMD_UART_RECV_DATA_IN_LENMAX 252 +#define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num)) +/* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */ +#define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0 +/* Offset at which to write the data */ +#define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4 +/* Length of data */ +#define MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8 +/* Reserved for future use */ +#define MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12 +#define MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16 +#define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1 +#define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0 +#define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236 + + +/***********************************/ +/* MC_CMD_READ_FUSES + * Read data programmed into the device One-Time-Programmable (OTP) Fuses + */ +#define MC_CMD_READ_FUSES 0xf0 +#undef MC_CMD_0xf0_PRIVILEGE_CTG + +#define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_READ_FUSES_IN msgrequest */ +#define MC_CMD_READ_FUSES_IN_LEN 8 +/* Offset in OTP to read */ +#define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0 +/* Length of data to read in bytes */ +#define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4 + +/* MC_CMD_READ_FUSES_OUT msgresponse */ +#define MC_CMD_READ_FUSES_OUT_LENMIN 4 +#define MC_CMD_READ_FUSES_OUT_LENMAX 252 +#define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num)) +/* Length of returned OTP data in bytes */ +#define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0 +/* Returned data */ +#define MC_CMD_READ_FUSES_OUT_DATA_OFST 4 +#define MC_CMD_READ_FUSES_OUT_DATA_LEN 1 +#define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0 +#define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248 + + +/***********************************/ +/* MC_CMD_KR_TUNE + * Get or set KR Serdes RXEQ and TX Driver settings + */ +#define MC_CMD_KR_TUNE 0xf1 +#undef MC_CMD_0xf1_PRIVILEGE_CTG + +#define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_KR_TUNE_IN msgrequest */ +#define MC_CMD_KR_TUNE_IN_LENMIN 4 +#define MC_CMD_KR_TUNE_IN_LENMAX 252 +#define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num)) +/* Requested operation */ +#define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0 +#define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1 +/* enum: Get current RXEQ settings */ +#define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0 +/* enum: Override RXEQ settings */ +#define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1 +/* enum: Get current TX Driver settings */ +#define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2 +/* enum: Override TX Driver settings */ +#define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3 +/* enum: Force KR Serdes reset / recalibration */ +#define MC_CMD_KR_TUNE_IN_RECAL 0x4 +/* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid + * signal. + */ +#define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5 +/* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The + * caller should call this command repeatedly after starting eye plot, until no + * more data is returned. + */ +#define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6 +/* enum: Read Figure Of Merit (eye quality, higher is better). */ +#define MC_CMD_KR_TUNE_IN_READ_FOM 0x7 +/* Align the arguments to 32 bits */ +#define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1 +#define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3 +/* Arguments specific to the operation */ +#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4 +#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4 +#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0 +#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62 + +/* MC_CMD_KR_TUNE_OUT msgresponse */ +#define MC_CMD_KR_TUNE_OUT_LEN 0 + +/* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */ +#define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4 +/* Requested operation */ +#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0 +#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1 +/* Align the arguments to 32 bits */ +#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 +#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 + +/* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */ +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4 +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252 +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) +/* RXEQ Parameter */ +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 +/* enum: Attenuation (0-15, TBD for Medford) */ +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0 +/* enum: CTLE Boost (0-15, TBD for Medford) */ +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1 +/* enum: Edge DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive, TBD + * for Medford) + */ +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2 +/* enum: Edge DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive, TBD for + * Medford) + */ +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3 +/* enum: Edge DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive, TBD for + * Medford) + */ +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4 +/* enum: Edge DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive, TBD for + * Medford) + */ +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5 +/* enum: Edge DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive, TBD for + * Medford) + */ +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6 +/* enum: Edge DFE DLEV (TBD for Medford) */ +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7 +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3 +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11 +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4 +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16 +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 + +/* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */ +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8 +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252 +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) +/* Requested operation */ +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0 +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1 +/* Align the arguments to 32 bits */ +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 +/* RXEQ Parameter */ +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4 +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4 +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 +/* Enum values, see field(s): */ +/* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */ +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3 +/* Enum values, see field(s): */ +/* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */ +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11 +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12 +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4 +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 +#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 + +/* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */ +#define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0 + +/* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */ +#define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4 +/* Requested operation */ +#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0 +#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1 +/* Align the arguments to 32 bits */ +#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 +#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 + +/* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4 +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252 +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) +/* TXEQ Parameter */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 +/* enum: TX Amplitude */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0 +/* enum: De-Emphasis Tap1 Magnitude (0-7) */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1 +/* enum: De-Emphasis Tap1 Fine */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2 +/* enum: De-Emphasis Tap2 Magnitude (0-6) */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3 +/* enum: De-Emphasis Tap2 Fine */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4 +/* enum: Pre-Emphasis Magnitude */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5 +/* enum: Pre-Emphasis Fine */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6 +/* enum: TX Slew Rate Coarse control */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7 +/* enum: TX Slew Rate Fine control */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8 +/* enum: TX Termination Impedance control */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9 +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3 +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11 +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5 +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16 +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24 +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8 + +/* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */ +#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8 +#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252 +#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num)) +/* Requested operation */ +#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0 +#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1 +/* Align the arguments to 32 bits */ +#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 +#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 +/* TXEQ Parameter */ +#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4 +#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4 +#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1 +#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62 +#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0 +#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8 +/* Enum values, see field(s): */ +/* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */ +#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8 +#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3 +/* Enum values, see field(s): */ +/* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */ +#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11 +#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5 +#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16 +#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 +#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24 +#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8 + +/* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */ +#define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0 + +/* MC_CMD_KR_TUNE_RECAL_IN msgrequest */ +#define MC_CMD_KR_TUNE_RECAL_IN_LEN 4 +/* Requested operation */ +#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0 +#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1 +/* Align the arguments to 32 bits */ +#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1 +#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3 + +/* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */ +#define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0 + +/* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */ +#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8 +/* Requested operation */ +#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 +#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 +/* Align the arguments to 32 bits */ +#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 +#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 +#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 + +/* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */ +#define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0 + +/* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */ +#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4 +/* Requested operation */ +#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 +#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 +/* Align the arguments to 32 bits */ +#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 +#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 + +/* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */ +#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 +#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 +#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) +#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 +#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 +#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 +#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 + +/* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */ +#define MC_CMD_KR_TUNE_READ_FOM_IN_LEN 8 +/* Requested operation */ +#define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0 +#define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1 +/* Align the arguments to 32 bits */ +#define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1 +#define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3 +#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4 + +/* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */ +#define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4 +#define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0 + + +/***********************************/ +/* MC_CMD_PCIE_TUNE + * Get or set PCIE Serdes RXEQ and TX Driver settings + */ +#define MC_CMD_PCIE_TUNE 0xf2 +#undef MC_CMD_0xf2_PRIVILEGE_CTG + +#define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_PCIE_TUNE_IN msgrequest */ +#define MC_CMD_PCIE_TUNE_IN_LENMIN 4 +#define MC_CMD_PCIE_TUNE_IN_LENMAX 252 +#define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num)) +/* Requested operation */ +#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0 +#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1 +/* enum: Get current RXEQ settings */ +#define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0 +/* enum: Override RXEQ settings */ +#define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1 +/* enum: Get current TX Driver settings */ +#define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2 +/* enum: Override TX Driver settings */ +#define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3 +/* enum: Start PCIe Serdes Eye diagram plot on a given lane. */ +#define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5 +/* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The + * caller should call this command repeatedly after starting eye plot, until no + * more data is returned. + */ +#define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6 +/* Align the arguments to 32 bits */ +#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1 +#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3 +/* Arguments specific to the operation */ +#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4 +#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4 +#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0 +#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62 + +/* MC_CMD_PCIE_TUNE_OUT msgresponse */ +#define MC_CMD_PCIE_TUNE_OUT_LEN 0 + +/* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4 +/* Requested operation */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 +/* Align the arguments to 32 bits */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 + +/* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) +/* RXEQ Parameter */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 +/* enum: Attenuation (0-15) */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0 +/* enum: CTLE Boost (0-15) */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1 +/* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2 +/* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3 +/* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4 +/* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5 +/* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 4 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x8 /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 12 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 + +/* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */ +#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4 +/* Requested operation */ +#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 +#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 +/* Align the arguments to 32 bits */ +#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 +#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 + +/* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */ +#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4 +#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252 +#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) +/* RXEQ Parameter */ +#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 +#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 +#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 +#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 +#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 +#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 +/* enum: TxMargin (PIPE) */ +#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0 +/* enum: TxSwing (PIPE) */ +#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1 +/* enum: De-emphasis coefficient C(-1) (PIPE) */ +#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2 +/* enum: De-emphasis coefficient C(0) (PIPE) */ +#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3 +/* enum: De-emphasis coefficient C(+1) (PIPE) */ +#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4 +#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 +#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4 +/* Enum values, see field(s): */ +/* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ +#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12 +#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12 +#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24 +#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 + +/* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */ +#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8 +/* Requested operation */ +#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 +#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 +/* Align the arguments to 32 bits */ +#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 +#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 +#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 + +/* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */ +#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0 + +/* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */ +#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4 +/* Requested operation */ +#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 +#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 +/* Align the arguments to 32 bits */ +#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 +#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 + +/* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */ +#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 +#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 +#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) +#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 +#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 +#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 +#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 + + +/***********************************/ +/* MC_CMD_LICENSING + * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition + */ +#define MC_CMD_LICENSING 0xf3 +#undef MC_CMD_0xf3_PRIVILEGE_CTG + +#define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_LICENSING_IN msgrequest */ +#define MC_CMD_LICENSING_IN_LEN 4 +/* identifies the type of operation requested */ +#define MC_CMD_LICENSING_IN_OP_OFST 0 +/* enum: re-read and apply licenses after a license key partition update; note + * that this operation returns a zero-length response + */ +#define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0 +/* enum: report counts of installed licenses */ +#define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1 + +/* MC_CMD_LICENSING_OUT msgresponse */ +#define MC_CMD_LICENSING_OUT_LEN 28 +/* count of application keys which are valid */ +#define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0 +/* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with + * MC_CMD_FC_OP_LICENSE) + */ +#define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4 +/* count of application keys which are invalid due to being blacklisted */ +#define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8 +/* count of application keys which are invalid due to being unverifiable */ +#define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12 +/* count of application keys which are invalid due to being for the wrong node + */ +#define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16 +/* licensing state (for diagnostics; the exact meaning of the bits in this + * field are private to the firmware) + */ +#define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20 +/* licensing subsystem self-test report (for manftest) */ +#define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24 +/* enum: licensing subsystem self-test failed */ +#define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0 +/* enum: licensing subsystem self-test passed */ +#define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1 + + +/***********************************/ +/* MC_CMD_MC2MC_PROXY + * Execute an arbitrary MCDI command on the slave MC of a dual-core device. + * This will fail on a single-core system. + */ +#define MC_CMD_MC2MC_PROXY 0xf4 +#undef MC_CMD_0xf4_PRIVILEGE_CTG + +#define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_MC2MC_PROXY_IN msgrequest */ +#define MC_CMD_MC2MC_PROXY_IN_LEN 0 + +/* MC_CMD_MC2MC_PROXY_OUT msgresponse */ +#define MC_CMD_MC2MC_PROXY_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_GET_LICENSED_APP_STATE + * Query the state of an individual licensed application. (Note that the actual + * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation + * or a reboot of the MC.) + */ +#define MC_CMD_GET_LICENSED_APP_STATE 0xf5 +#undef MC_CMD_0xf5_PRIVILEGE_CTG + +#define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */ +#define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4 +/* application ID to query (LICENSED_APP_ID_xxx) */ +#define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0 + +/* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */ +#define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4 +/* state of this application */ +#define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0 +/* enum: no (or invalid) license is present for the application */ +#define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0 +/* enum: a valid license is present for the application */ +#define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1 + + +/***********************************/ +/* MC_CMD_LICENSED_APP_OP + * Perform an action for an individual licensed application. + */ +#define MC_CMD_LICENSED_APP_OP 0xf6 +#undef MC_CMD_0xf6_PRIVILEGE_CTG + +#define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_LICENSED_APP_OP_IN msgrequest */ +#define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8 +#define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252 +#define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num)) +/* application ID */ +#define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0 +/* the type of operation requested */ +#define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4 +/* enum: validate application */ +#define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0 +/* enum: mask application */ +#define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1 +/* arguments specific to this particular operation */ +#define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8 +#define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4 +#define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0 +#define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61 + +/* MC_CMD_LICENSED_APP_OP_OUT msgresponse */ +#define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0 +#define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252 +#define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num)) +/* result specific to this particular operation */ +#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0 +#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4 +#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0 +#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63 + +/* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */ +#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72 +/* application ID */ +#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0 +/* the type of operation requested */ +#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4 +/* validation challenge */ +#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8 +#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64 + +/* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */ +#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68 +/* feature expiry (time_t) */ +#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0 +/* validation response */ +#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4 +#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64 + +/* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */ +#define MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12 +/* application ID */ +#define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0 +/* the type of operation requested */ +#define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4 +/* flag */ +#define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8 + +/* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */ +#define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_SET_PORT_SNIFF_CONFIG + * Configure RX port sniffing for the physical port associated with the calling + * function. Only a privileged function may change the port sniffing + * configuration. A copy of all traffic delivered to the host (non-promiscuous + * mode) or all traffic arriving at the port (promiscuous mode) may be + * delivered to a specific queue, or a set of queues with RSS. + */ +#define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7 +#undef MC_CMD_0xf7_PRIVILEGE_CTG + +#define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */ +#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16 +/* configuration flags */ +#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 +#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 +#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 +#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1 +#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1 +/* receive queue handle (for RSS mode, this is the base queue) */ +#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 +/* receive mode */ +#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 +/* enum: receive to just the specified queue */ +#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 +/* enum: receive to multiple queues using RSS context */ +#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 +/* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note + * that these handles should be considered opaque to the host, although a value + * of 0xFFFFFFFF is guaranteed never to be a valid handle. + */ +#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 + +/* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */ +#define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_GET_PORT_SNIFF_CONFIG + * Obtain the current RX port sniffing configuration for the physical port + * associated with the calling function. Only a privileged function may read + * the configuration. + */ +#define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8 +#undef MC_CMD_0xf8_PRIVILEGE_CTG + +#define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */ +#define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0 + +/* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */ +#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16 +/* configuration flags */ +#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 +#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 +#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 +#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1 +#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1 +/* receiving queue handle (for RSS mode, this is the base queue) */ +#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 +/* receive mode */ +#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 +/* enum: receiving to just the specified queue */ +#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 +/* enum: receiving to multiple queues using RSS context */ +#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 +/* RSS context (for RX_MODE_RSS) */ +#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 + + +/***********************************/ +/* MC_CMD_SET_PARSER_DISP_CONFIG + * Change configuration related to the parser-dispatcher subsystem. + */ +#define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9 +#undef MC_CMD_0xf9_PRIVILEGE_CTG + +#define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */ +#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12 +#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252 +#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num)) +/* the type of configuration setting to change */ +#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 +/* enum: Per-TXQ enable for multicast UDP destination lookup for possible + * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.) + */ +#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0 +/* enum: Per-v-adaptor enable for suppression of self-transmissions on the + * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single + * boolean.) + */ +#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1 +/* handle for the entity to update: queue handle, EVB port ID, etc. depending + * on the type of configuration setting being changed + */ +#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 +/* new value: the details depend on the type of configuration setting being + * changed + */ +#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8 +#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4 +#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1 +#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61 + +/* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */ +#define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_GET_PARSER_DISP_CONFIG + * Read configuration related to the parser-dispatcher subsystem. + */ +#define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa +#undef MC_CMD_0xfa_PRIVILEGE_CTG + +#define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */ +#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8 +/* the type of configuration setting to read */ +#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 +/* Enum values, see field(s): */ +/* MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */ +/* handle for the entity to query: queue handle, EVB port ID, etc. depending on + * the type of configuration setting being read + */ +#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 + +/* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */ +#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4 +#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252 +#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num)) +/* current value: the details depend on the type of configuration setting being + * read + */ +#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0 +#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4 +#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1 +#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63 + + +/***********************************/ +/* MC_CMD_SET_TX_PORT_SNIFF_CONFIG + * Configure TX port sniffing for the physical port associated with the calling + * function. Only a privileged function may change the port sniffing + * configuration. A copy of all traffic transmitted through the port may be + * delivered to a specific queue, or a set of queues with RSS. Note that these + * packets are delivered with transmit timestamps in the packet prefix, not + * receive timestamps, so it is likely that the queue(s) will need to be + * dedicated as TX sniff receivers. + */ +#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb +#undef MC_CMD_0xfb_PRIVILEGE_CTG + +#define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ +#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16 +/* configuration flags */ +#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 +#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 +#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 +/* receive queue handle (for RSS mode, this is the base queue) */ +#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 +/* receive mode */ +#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 +/* enum: receive to just the specified queue */ +#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 +/* enum: receive to multiple queues using RSS context */ +#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 +/* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note + * that these handles should be considered opaque to the host, although a value + * of 0xFFFFFFFF is guaranteed never to be a valid handle. + */ +#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 + +/* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ +#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_GET_TX_PORT_SNIFF_CONFIG + * Obtain the current TX port sniffing configuration for the physical port + * associated with the calling function. Only a privileged function may read + * the configuration. + */ +#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc +#undef MC_CMD_0xfc_PRIVILEGE_CTG + +#define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ +#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0 + +/* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ +#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16 +/* configuration flags */ +#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 +#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 +#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 +/* receiving queue handle (for RSS mode, this is the base queue) */ +#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 +/* receive mode */ +#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 +/* enum: receiving to just the specified queue */ +#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 +/* enum: receiving to multiple queues using RSS context */ +#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 +/* RSS context (for RX_MODE_RSS) */ +#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 + + +/***********************************/ +/* MC_CMD_RMON_STATS_RX_ERRORS + * Per queue rx error stats. + */ +#define MC_CMD_RMON_STATS_RX_ERRORS 0xfe +#undef MC_CMD_0xfe_PRIVILEGE_CTG + +#define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_RMON_STATS_RX_ERRORS_IN msgrequest */ +#define MC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8 +/* The rx queue to get stats for. */ +#define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0 +#define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4 +#define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0 +#define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1 + +/* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */ +#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16 +#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0 +#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4 +#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8 +#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12 + + +/***********************************/ +/* MC_CMD_GET_PCIE_RESOURCE_INFO + * Find out about available PCIE resources + */ +#define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd + +/* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */ +#define MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0 + +/* MC_CMD_GET_PCIE_RESOURCE_INFO_OUT msgresponse */ +#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28 +/* The maximum number of PFs the device can expose */ +#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0 +/* The maximum number of VFs the device can expose in total */ +#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4 +/* The maximum number of MSI-X vectors the device can provide in total */ +#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8 +/* the number of MSI-X vectors the device will allocate by default to each PF + */ +#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12 +/* the number of MSI-X vectors the device will allocate by default to each VF + */ +#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16 +/* the maximum number of MSI-X vectors the device can allocate to any one PF */ +#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20 +/* the maximum number of MSI-X vectors the device can allocate to any one VF */ +#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24 + + +/***********************************/ +/* MC_CMD_GET_PORT_MODES + * Find out about available port modes + */ +#define MC_CMD_GET_PORT_MODES 0xff +#undef MC_CMD_0xff_PRIVILEGE_CTG + +#define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_GET_PORT_MODES_IN msgrequest */ +#define MC_CMD_GET_PORT_MODES_IN_LEN 0 + +/* MC_CMD_GET_PORT_MODES_OUT msgresponse */ +#define MC_CMD_GET_PORT_MODES_OUT_LEN 12 +/* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) */ +#define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0 +/* Default (canonical) board mode */ +#define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4 +/* Current board mode */ +#define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8 + + +/***********************************/ +/* MC_CMD_READ_ATB + * Sample voltages on the ATB + */ +#define MC_CMD_READ_ATB 0x100 +#undef MC_CMD_0x100_PRIVILEGE_CTG + +#define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_READ_ATB_IN msgrequest */ +#define MC_CMD_READ_ATB_IN_LEN 16 +#define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0 +#define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */ +#define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */ +#define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */ +#define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4 +#define MC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8 +#define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12 + +/* MC_CMD_READ_ATB_OUT msgresponse */ +#define MC_CMD_READ_ATB_OUT_LEN 4 +#define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0 + + +/***********************************/ +/* MC_CMD_GET_WORKAROUNDS + * Read the list of all implemented and all currently enabled workarounds. The + * enums here must correspond with those in MC_CMD_WORKAROUND. + */ +#define MC_CMD_GET_WORKAROUNDS 0x59 +#undef MC_CMD_0x59_PRIVILEGE_CTG + +#define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */ +#define MC_CMD_GET_WORKAROUNDS_OUT_LEN 8 +/* Each workaround is represented by a single bit according to the enums below. + */ +#define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0 +#define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4 +/* enum: Bug 17230 work around. */ +#define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2 +/* enum: Bug 35388 work around (unsafe EVQ writes). */ +#define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4 +/* enum: Bug35017 workaround (A64 tables must be identity map) */ +#define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8 +/* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ +#define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10 +/* enum: Bug 42008 present (Interrupts can overtake associated events). Caution + * - before adding code that queries this workaround, remember that there's + * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, + * and will hence (incorrectly) report that the bug doesn't exist. + */ +#define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20 +/* enum: Bug 26807 features present in firmware (multicast filter chaining) */ +#define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40 + + +/***********************************/ +/* MC_CMD_PRIVILEGE_MASK + * Read/set privileges of an arbitrary PCIe function + */ +#define MC_CMD_PRIVILEGE_MASK 0x5a +#undef MC_CMD_0x5a_PRIVILEGE_CTG + +#define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_PRIVILEGE_MASK_IN msgrequest */ +#define MC_CMD_PRIVILEGE_MASK_IN_LEN 8 +/* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF + * 1,3 = 0x00030001 + */ +#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0 +#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0 +#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16 +#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16 +#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16 +#define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */ +/* New privilege mask to be set. The mask will only be changed if the MSB is + * set to 1. + */ +#define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4 +#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */ +#define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */ +#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */ +#define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */ +#define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */ +#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20 /* enum */ +#define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */ +#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */ +#define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */ +#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */ +#define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */ +/* enum: Set this bit to indicate that a new privilege mask is to be set, + * otherwise the command will only read the existing mask. + */ +#define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000 + +/* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */ +#define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4 +/* For an admin function, always all the privileges are reported. */ +#define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0 + + +/***********************************/ +/* MC_CMD_LINK_STATE_MODE + * Read/set link state mode of a VF + */ +#define MC_CMD_LINK_STATE_MODE 0x5c +#undef MC_CMD_0x5c_PRIVILEGE_CTG + +#define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_LINK_STATE_MODE_IN msgrequest */ +#define MC_CMD_LINK_STATE_MODE_IN_LEN 8 +/* The target function to have its link state mode read or set, must be a VF + * e.g. VF 1,3 = 0x00030001 + */ +#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0 +#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0 +#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16 +#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16 +#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16 +/* New link state mode to be set */ +#define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4 +#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */ +#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */ +#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */ +/* enum: Use this value to just read the existing setting without modifying it. + */ +#define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff + +/* MC_CMD_LINK_STATE_MODE_OUT msgresponse */ +#define MC_CMD_LINK_STATE_MODE_OUT_LEN 4 +#define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0 + + +/***********************************/ +/* MC_CMD_GET_SNAPSHOT_LENGTH + * Obtain the curent range of allowable values for the SNAPSHOT_LENGTH + * parameter to MC_CMD_INIT_RXQ. + */ +#define MC_CMD_GET_SNAPSHOT_LENGTH 0x101 +#undef MC_CMD_0x101_PRIVILEGE_CTG + +#define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_GET_SNAPSHOT_LENGTH_IN msgrequest */ +#define MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0 + +/* MC_CMD_GET_SNAPSHOT_LENGTH_OUT msgresponse */ +#define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8 +/* Minimum acceptable snapshot length. */ +#define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0 +/* Maximum acceptable snapshot length. */ +#define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4 + + +/***********************************/ +/* MC_CMD_FUSE_DIAGS + * Additional fuse diagnostics + */ +#define MC_CMD_FUSE_DIAGS 0x102 +#undef MC_CMD_0x102_PRIVILEGE_CTG + +#define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_FUSE_DIAGS_IN msgrequest */ +#define MC_CMD_FUSE_DIAGS_IN_LEN 0 + +/* MC_CMD_FUSE_DIAGS_OUT msgresponse */ +#define MC_CMD_FUSE_DIAGS_OUT_LEN 48 +/* Total number of mismatched bits between pairs in area 0 */ +#define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0 +/* Total number of unexpectedly clear (set in B but not A) bits in area 0 */ +#define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4 +/* Total number of unexpectedly clear (set in A but not B) bits in area 0 */ +#define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8 +/* Checksum of data after logical OR of pairs in area 0 */ +#define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12 +/* Total number of mismatched bits between pairs in area 1 */ +#define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16 +/* Total number of unexpectedly clear (set in B but not A) bits in area 1 */ +#define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20 +/* Total number of unexpectedly clear (set in A but not B) bits in area 1 */ +#define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24 +/* Checksum of data after logical OR of pairs in area 1 */ +#define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28 +/* Total number of mismatched bits between pairs in area 2 */ +#define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32 +/* Total number of unexpectedly clear (set in B but not A) bits in area 2 */ +#define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36 +/* Total number of unexpectedly clear (set in A but not B) bits in area 2 */ +#define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40 +/* Checksum of data after logical OR of pairs in area 2 */ +#define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44 + + +/***********************************/ +/* MC_CMD_PRIVILEGE_MODIFY + * Modify the privileges of a set of PCIe functions. Note that this operation + * only effects non-admin functions unless the admin privilege itself is + * included in one of the masks provided. + */ +#define MC_CMD_PRIVILEGE_MODIFY 0x60 +#undef MC_CMD_0x60_PRIVILEGE_CTG + +#define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */ +#define MC_CMD_PRIVILEGE_MODIFY_IN_LEN 16 +/* The groups of functions to have their privilege masks modified. */ +#define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0 +#define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */ +#define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */ +#define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */ +#define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */ +#define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */ +#define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */ +/* For VFS_OF_PF specify the PF, for ONE specify the target function */ +#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4 +#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0 +#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16 +#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16 +#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16 +/* Privileges to be added to the target functions. For privilege definitions + * refer to the command MC_CMD_PRIVILEGE_MASK + */ +#define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8 +/* Privileges to be removed from the target functions. For privilege + * definitions refer to the command MC_CMD_PRIVILEGE_MASK + */ +#define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12 + +/* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */ +#define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_XPM_READ_BYTES + * Read XPM memory + */ +#define MC_CMD_XPM_READ_BYTES 0x103 +#undef MC_CMD_0x103_PRIVILEGE_CTG + +#define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_XPM_READ_BYTES_IN msgrequest */ +#define MC_CMD_XPM_READ_BYTES_IN_LEN 8 +/* Start address (byte) */ +#define MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0 +/* Count (bytes) */ +#define MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4 + +/* MC_CMD_XPM_READ_BYTES_OUT msgresponse */ +#define MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0 +#define MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252 +#define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num)) +/* Data */ +#define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0 +#define MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1 +#define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0 +#define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252 + + +/***********************************/ +/* MC_CMD_XPM_WRITE_BYTES + * Write XPM memory + */ +#define MC_CMD_XPM_WRITE_BYTES 0x104 +#undef MC_CMD_0x104_PRIVILEGE_CTG + +#define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */ +#define MC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8 +#define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252 +#define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num)) +/* Start address (byte) */ +#define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0 +/* Count (bytes) */ +#define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4 +/* Data */ +#define MC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8 +#define MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1 +#define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0 +#define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244 + +/* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */ +#define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_XPM_READ_SECTOR + * Read XPM sector + */ +#define MC_CMD_XPM_READ_SECTOR 0x105 +#undef MC_CMD_0x105_PRIVILEGE_CTG + +#define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_XPM_READ_SECTOR_IN msgrequest */ +#define MC_CMD_XPM_READ_SECTOR_IN_LEN 8 +/* Sector index */ +#define MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0 +/* Sector size */ +#define MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4 + +/* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */ +#define MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4 +#define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36 +#define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num)) +/* Sector type */ +#define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0 +#define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */ +#define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */ +#define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */ +#define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */ +/* Sector data */ +#define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4 +#define MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1 +#define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0 +#define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32 + + +/***********************************/ +/* MC_CMD_XPM_WRITE_SECTOR + * Write XPM sector + */ +#define MC_CMD_XPM_WRITE_SECTOR 0x106 +#undef MC_CMD_0x106_PRIVILEGE_CTG + +#define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */ +#define MC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12 +#define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44 +#define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num)) +/* If writing fails due to an uncorrectable error, try up to RETRIES following + * sectors (or until no more space available). If 0, only one write attempt is + * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair + * mechanism. + */ +#define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0 +#define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1 +#define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1 +#define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3 +/* Sector type */ +#define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4 +/* Enum values, see field(s): */ +/* MC_CMD_XPM_READ_SECTOR_OUT/TYPE */ +/* Sector size */ +#define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8 +/* Sector data */ +#define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12 +#define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1 +#define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0 +#define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32 + +/* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */ +#define MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4 +/* New sector index */ +#define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0 + + +/***********************************/ +/* MC_CMD_XPM_INVALIDATE_SECTOR + * Invalidate XPM sector + */ +#define MC_CMD_XPM_INVALIDATE_SECTOR 0x107 +#undef MC_CMD_0x107_PRIVILEGE_CTG + +#define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */ +#define MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4 +/* Sector index */ +#define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0 + +/* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */ +#define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_XPM_BLANK_CHECK + * Blank-check XPM memory and report bad locations + */ +#define MC_CMD_XPM_BLANK_CHECK 0x108 +#undef MC_CMD_0x108_PRIVILEGE_CTG + +#define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */ +#define MC_CMD_XPM_BLANK_CHECK_IN_LEN 8 +/* Start address (byte) */ +#define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0 +/* Count (bytes) */ +#define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4 + +/* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */ +#define MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4 +#define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252 +#define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num)) +/* Total number of bad (non-blank) locations */ +#define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0 +/* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit + * into MCDI response) + */ +#define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4 +#define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2 +#define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0 +#define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124 + + +/***********************************/ +/* MC_CMD_XPM_REPAIR + * Blank-check and repair XPM memory + */ +#define MC_CMD_XPM_REPAIR 0x109 +#undef MC_CMD_0x109_PRIVILEGE_CTG + +#define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_XPM_REPAIR_IN msgrequest */ +#define MC_CMD_XPM_REPAIR_IN_LEN 8 +/* Start address (byte) */ +#define MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0 +/* Count (bytes) */ +#define MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4 + +/* MC_CMD_XPM_REPAIR_OUT msgresponse */ +#define MC_CMD_XPM_REPAIR_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_XPM_DECODER_TEST + * Test XPM memory address decoders for gross manufacturing defects. Can only + * be performed on an unprogrammed part. + */ +#define MC_CMD_XPM_DECODER_TEST 0x10a +#undef MC_CMD_0x10a_PRIVILEGE_CTG + +#define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_XPM_DECODER_TEST_IN msgrequest */ +#define MC_CMD_XPM_DECODER_TEST_IN_LEN 0 + +/* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */ +#define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_XPM_WRITE_TEST + * XPM memory write test. Test XPM write logic for gross manufacturing defects + * by writing to a dedicated test row. There are 16 locations in the test row + * and the test can only be performed on locations that have not been + * previously used (i.e. can be run at most 16 times). The test will pick the + * first available location to use, or fail with ENOSPC if none left. + */ +#define MC_CMD_XPM_WRITE_TEST 0x10b +#undef MC_CMD_0x10b_PRIVILEGE_CTG + +#define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_XPM_WRITE_TEST_IN msgrequest */ +#define MC_CMD_XPM_WRITE_TEST_IN_LEN 0 + +/* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */ +#define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0 #endif /* _SIENA_MC_DRIVER_PCOL_H */ Property changes on: head/sys/dev/sfxge/common/efx_regs_mcdi.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_regs_pci.h =================================================================== --- head/sys/dev/sfxge/common/efx_regs_pci.h (revision 283513) +++ head/sys/dev/sfxge/common/efx_regs_pci.h (revision 283514) @@ -1,2378 +1,2358 @@ /*- - * Copyright 2007-2010 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2007-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + * * $FreeBSD$ */ #ifndef _SYS_EFX_REGS_PCI_H #define _SYS_EFX_REGS_PCI_H #ifdef __cplusplus extern "C" { #endif /* * PC_VEND_ID_REG(16bit): * Vendor ID register */ #define PCR_AZ_VEND_ID_REG 0x00000000 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_VEND_ID_LBN 0 #define PCRF_AZ_VEND_ID_WIDTH 16 /* * PC_DEV_ID_REG(16bit): * Device ID register */ #define PCR_AZ_DEV_ID_REG 0x00000002 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_DEV_ID_LBN 0 #define PCRF_AZ_DEV_ID_WIDTH 16 /* * PC_CMD_REG(16bit): * Command register */ #define PCR_AZ_CMD_REG 0x00000004 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_INTX_DIS_LBN 10 #define PCRF_AZ_INTX_DIS_WIDTH 1 #define PCRF_AZ_FB2B_EN_LBN 9 #define PCRF_AZ_FB2B_EN_WIDTH 1 #define PCRF_AZ_SERR_EN_LBN 8 #define PCRF_AZ_SERR_EN_WIDTH 1 #define PCRF_AZ_IDSEL_CTL_LBN 7 #define PCRF_AZ_IDSEL_CTL_WIDTH 1 #define PCRF_AZ_PERR_EN_LBN 6 #define PCRF_AZ_PERR_EN_WIDTH 1 #define PCRF_AZ_VGA_PAL_SNP_LBN 5 #define PCRF_AZ_VGA_PAL_SNP_WIDTH 1 #define PCRF_AZ_MWI_EN_LBN 4 #define PCRF_AZ_MWI_EN_WIDTH 1 #define PCRF_AZ_SPEC_CYC_LBN 3 #define PCRF_AZ_SPEC_CYC_WIDTH 1 #define PCRF_AZ_MST_EN_LBN 2 #define PCRF_AZ_MST_EN_WIDTH 1 #define PCRF_AZ_MEM_EN_LBN 1 #define PCRF_AZ_MEM_EN_WIDTH 1 #define PCRF_AZ_IO_EN_LBN 0 #define PCRF_AZ_IO_EN_WIDTH 1 /* * PC_STAT_REG(16bit): * Status register */ #define PCR_AZ_STAT_REG 0x00000006 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_DET_PERR_LBN 15 #define PCRF_AZ_DET_PERR_WIDTH 1 #define PCRF_AZ_SIG_SERR_LBN 14 #define PCRF_AZ_SIG_SERR_WIDTH 1 #define PCRF_AZ_GOT_MABRT_LBN 13 #define PCRF_AZ_GOT_MABRT_WIDTH 1 #define PCRF_AZ_GOT_TABRT_LBN 12 #define PCRF_AZ_GOT_TABRT_WIDTH 1 #define PCRF_AZ_SIG_TABRT_LBN 11 #define PCRF_AZ_SIG_TABRT_WIDTH 1 #define PCRF_AZ_DEVSEL_TIM_LBN 9 #define PCRF_AZ_DEVSEL_TIM_WIDTH 2 #define PCRF_AZ_MDAT_PERR_LBN 8 #define PCRF_AZ_MDAT_PERR_WIDTH 1 #define PCRF_AZ_FB2B_CAP_LBN 7 #define PCRF_AZ_FB2B_CAP_WIDTH 1 #define PCRF_AZ_66MHZ_CAP_LBN 5 #define PCRF_AZ_66MHZ_CAP_WIDTH 1 #define PCRF_AZ_CAP_LIST_LBN 4 #define PCRF_AZ_CAP_LIST_WIDTH 1 #define PCRF_AZ_INTX_STAT_LBN 3 #define PCRF_AZ_INTX_STAT_WIDTH 1 /* * PC_REV_ID_REG(8bit): * Class code & revision ID register */ #define PCR_AZ_REV_ID_REG 0x00000008 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_REV_ID_LBN 0 #define PCRF_AZ_REV_ID_WIDTH 8 /* * PC_CC_REG(24bit): * Class code register */ #define PCR_AZ_CC_REG 0x00000009 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_BASE_CC_LBN 16 #define PCRF_AZ_BASE_CC_WIDTH 8 #define PCRF_AZ_SUB_CC_LBN 8 #define PCRF_AZ_SUB_CC_WIDTH 8 #define PCRF_AZ_PROG_IF_LBN 0 #define PCRF_AZ_PROG_IF_WIDTH 8 /* * PC_CACHE_LSIZE_REG(8bit): * Cache line size */ #define PCR_AZ_CACHE_LSIZE_REG 0x0000000c /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_CACHE_LSIZE_LBN 0 #define PCRF_AZ_CACHE_LSIZE_WIDTH 8 /* * PC_MST_LAT_REG(8bit): * Master latency timer register */ #define PCR_AZ_MST_LAT_REG 0x0000000d /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_MST_LAT_LBN 0 #define PCRF_AZ_MST_LAT_WIDTH 8 /* * PC_HDR_TYPE_REG(8bit): * Header type register */ #define PCR_AZ_HDR_TYPE_REG 0x0000000e /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_MULT_FUNC_LBN 7 #define PCRF_AZ_MULT_FUNC_WIDTH 1 #define PCRF_AZ_TYPE_LBN 0 #define PCRF_AZ_TYPE_WIDTH 7 /* * PC_BIST_REG(8bit): * BIST register */ #define PCR_AZ_BIST_REG 0x0000000f /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_BIST_LBN 0 #define PCRF_AZ_BIST_WIDTH 8 /* * PC_BAR0_REG(32bit): * Primary function base address register 0 */ #define PCR_AZ_BAR0_REG 0x00000010 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_BAR0_LBN 4 #define PCRF_AZ_BAR0_WIDTH 28 #define PCRF_AZ_BAR0_PREF_LBN 3 #define PCRF_AZ_BAR0_PREF_WIDTH 1 #define PCRF_AZ_BAR0_TYPE_LBN 1 #define PCRF_AZ_BAR0_TYPE_WIDTH 2 #define PCRF_AZ_BAR0_IOM_LBN 0 #define PCRF_AZ_BAR0_IOM_WIDTH 1 /* * PC_BAR1_REG(32bit): * Primary function base address register 1, BAR1 is not implemented so read only. */ #define PCR_DZ_BAR1_REG 0x00000014 /* hunta0=pci_f0_config */ #define PCRF_DZ_BAR1_LBN 0 #define PCRF_DZ_BAR1_WIDTH 32 /* * PC_BAR2_LO_REG(32bit): * Primary function base address register 2 low bits */ #define PCR_AZ_BAR2_LO_REG 0x00000018 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_BAR2_LO_LBN 4 #define PCRF_AZ_BAR2_LO_WIDTH 28 #define PCRF_AZ_BAR2_PREF_LBN 3 #define PCRF_AZ_BAR2_PREF_WIDTH 1 #define PCRF_AZ_BAR2_TYPE_LBN 1 #define PCRF_AZ_BAR2_TYPE_WIDTH 2 #define PCRF_AZ_BAR2_IOM_LBN 0 #define PCRF_AZ_BAR2_IOM_WIDTH 1 /* * PC_BAR2_HI_REG(32bit): * Primary function base address register 2 high bits */ #define PCR_AZ_BAR2_HI_REG 0x0000001c /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_BAR2_HI_LBN 0 #define PCRF_AZ_BAR2_HI_WIDTH 32 /* * PC_BAR4_LO_REG(32bit): * Primary function base address register 2 low bits */ #define PCR_CZ_BAR4_LO_REG 0x00000020 /* sienaa0,hunta0=pci_f0_config */ #define PCRF_CZ_BAR4_LO_LBN 4 #define PCRF_CZ_BAR4_LO_WIDTH 28 #define PCRF_CZ_BAR4_PREF_LBN 3 #define PCRF_CZ_BAR4_PREF_WIDTH 1 #define PCRF_CZ_BAR4_TYPE_LBN 1 #define PCRF_CZ_BAR4_TYPE_WIDTH 2 #define PCRF_CZ_BAR4_IOM_LBN 0 #define PCRF_CZ_BAR4_IOM_WIDTH 1 /* * PC_BAR4_HI_REG(32bit): * Primary function base address register 2 high bits */ #define PCR_CZ_BAR4_HI_REG 0x00000024 /* sienaa0,hunta0=pci_f0_config */ #define PCRF_CZ_BAR4_HI_LBN 0 #define PCRF_CZ_BAR4_HI_WIDTH 32 /* * PC_SS_VEND_ID_REG(16bit): * Sub-system vendor ID register */ #define PCR_AZ_SS_VEND_ID_REG 0x0000002c /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_SS_VEND_ID_LBN 0 #define PCRF_AZ_SS_VEND_ID_WIDTH 16 /* * PC_SS_ID_REG(16bit): * Sub-system ID register */ #define PCR_AZ_SS_ID_REG 0x0000002e /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_SS_ID_LBN 0 #define PCRF_AZ_SS_ID_WIDTH 16 /* * PC_EXPROM_BAR_REG(32bit): * Expansion ROM base address register */ #define PCR_AZ_EXPROM_BAR_REG 0x00000030 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_EXPROM_BAR_LBN 11 #define PCRF_AZ_EXPROM_BAR_WIDTH 21 #define PCRF_AB_EXPROM_MIN_SIZE_LBN 2 #define PCRF_AB_EXPROM_MIN_SIZE_WIDTH 9 #define PCRF_CZ_EXPROM_MIN_SIZE_LBN 1 #define PCRF_CZ_EXPROM_MIN_SIZE_WIDTH 10 #define PCRF_AB_EXPROM_FEATURE_ENABLE_LBN 1 #define PCRF_AB_EXPROM_FEATURE_ENABLE_WIDTH 1 #define PCRF_AZ_EXPROM_EN_LBN 0 #define PCRF_AZ_EXPROM_EN_WIDTH 1 /* * PC_CAP_PTR_REG(8bit): * Capability pointer register */ #define PCR_AZ_CAP_PTR_REG 0x00000034 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_CAP_PTR_LBN 0 #define PCRF_AZ_CAP_PTR_WIDTH 8 /* * PC_INT_LINE_REG(8bit): * Interrupt line register */ #define PCR_AZ_INT_LINE_REG 0x0000003c /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_INT_LINE_LBN 0 #define PCRF_AZ_INT_LINE_WIDTH 8 /* * PC_INT_PIN_REG(8bit): * Interrupt pin register */ #define PCR_AZ_INT_PIN_REG 0x0000003d /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_INT_PIN_LBN 0 #define PCRF_AZ_INT_PIN_WIDTH 8 +#define PCFE_DZ_INTPIN_INTD 4 +#define PCFE_DZ_INTPIN_INTC 3 +#define PCFE_DZ_INTPIN_INTB 2 +#define PCFE_DZ_INTPIN_INTA 1 /* * PC_PM_CAP_ID_REG(8bit): * Power management capability ID */ -#define PCR_AC_PM_CAP_ID_REG 0x00000040 -/* falcona0,falconb0,sienaa0=pci_f0_config */ +#define PCR_AZ_PM_CAP_ID_REG 0x00000040 +/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ -#define PCR_DZ_PM_CAP_ID_REG 0x00000080 -/* hunta0=pci_f0_config */ - #define PCRF_AZ_PM_CAP_ID_LBN 0 #define PCRF_AZ_PM_CAP_ID_WIDTH 8 /* * PC_PM_NXT_PTR_REG(8bit): * Power management next item pointer */ -#define PCR_AC_PM_NXT_PTR_REG 0x00000041 -/* falcona0,falconb0,sienaa0=pci_f0_config */ +#define PCR_AZ_PM_NXT_PTR_REG 0x00000041 +/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ -#define PCR_DZ_PM_NXT_PTR_REG 0x00000081 -/* hunta0=pci_f0_config */ - #define PCRF_AZ_PM_NXT_PTR_LBN 0 #define PCRF_AZ_PM_NXT_PTR_WIDTH 8 /* * PC_PM_CAP_REG(16bit): * Power management capabilities register */ -#define PCR_AC_PM_CAP_REG 0x00000042 -/* falcona0,falconb0,sienaa0=pci_f0_config */ +#define PCR_AZ_PM_CAP_REG 0x00000042 +/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ -#define PCR_DZ_PM_CAP_REG 0x00000082 -/* hunta0=pci_f0_config */ - #define PCRF_AZ_PM_PME_SUPT_LBN 11 #define PCRF_AZ_PM_PME_SUPT_WIDTH 5 #define PCRF_AZ_PM_D2_SUPT_LBN 10 #define PCRF_AZ_PM_D2_SUPT_WIDTH 1 #define PCRF_AZ_PM_D1_SUPT_LBN 9 #define PCRF_AZ_PM_D1_SUPT_WIDTH 1 #define PCRF_AZ_PM_AUX_CURR_LBN 6 #define PCRF_AZ_PM_AUX_CURR_WIDTH 3 #define PCRF_AZ_PM_DSI_LBN 5 #define PCRF_AZ_PM_DSI_WIDTH 1 #define PCRF_AZ_PM_PME_CLK_LBN 3 #define PCRF_AZ_PM_PME_CLK_WIDTH 1 #define PCRF_AZ_PM_PME_VER_LBN 0 #define PCRF_AZ_PM_PME_VER_WIDTH 3 /* * PC_PM_CS_REG(16bit): * Power management control & status register */ -#define PCR_AC_PM_CS_REG 0x00000044 -/* falcona0,falconb0,sienaa0=pci_f0_config */ +#define PCR_AZ_PM_CS_REG 0x00000044 +/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ -#define PCR_DZ_PM_CS_REG 0x00000084 -/* hunta0=pci_f0_config */ - #define PCRF_AZ_PM_PME_STAT_LBN 15 #define PCRF_AZ_PM_PME_STAT_WIDTH 1 #define PCRF_AZ_PM_DAT_SCALE_LBN 13 #define PCRF_AZ_PM_DAT_SCALE_WIDTH 2 #define PCRF_AZ_PM_DAT_SEL_LBN 9 #define PCRF_AZ_PM_DAT_SEL_WIDTH 4 #define PCRF_AZ_PM_PME_EN_LBN 8 #define PCRF_AZ_PM_PME_EN_WIDTH 1 #define PCRF_CZ_NO_SOFT_RESET_LBN 3 #define PCRF_CZ_NO_SOFT_RESET_WIDTH 1 #define PCRF_AZ_PM_PWR_ST_LBN 0 #define PCRF_AZ_PM_PWR_ST_WIDTH 2 /* * PC_MSI_CAP_ID_REG(8bit): * MSI capability ID */ -#define PCR_AC_MSI_CAP_ID_REG 0x00000050 -/* falcona0,falconb0,sienaa0=pci_f0_config */ +#define PCR_AZ_MSI_CAP_ID_REG 0x00000050 +/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ -#define PCR_DZ_MSI_CAP_ID_REG 0x00000090 -/* hunta0=pci_f0_config */ - #define PCRF_AZ_MSI_CAP_ID_LBN 0 #define PCRF_AZ_MSI_CAP_ID_WIDTH 8 /* * PC_MSI_NXT_PTR_REG(8bit): * MSI next item pointer */ -#define PCR_AC_MSI_NXT_PTR_REG 0x00000051 -/* falcona0,falconb0,sienaa0=pci_f0_config */ +#define PCR_AZ_MSI_NXT_PTR_REG 0x00000051 +/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ -#define PCR_DZ_MSI_NXT_PTR_REG 0x00000091 -/* hunta0=pci_f0_config */ - #define PCRF_AZ_MSI_NXT_PTR_LBN 0 #define PCRF_AZ_MSI_NXT_PTR_WIDTH 8 /* * PC_MSI_CTL_REG(16bit): * MSI control register */ -#define PCR_AC_MSI_CTL_REG 0x00000052 -/* falcona0,falconb0,sienaa0=pci_f0_config */ +#define PCR_AZ_MSI_CTL_REG 0x00000052 +/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ -#define PCR_DZ_MSI_CTL_REG 0x00000092 -/* hunta0=pci_f0_config */ - #define PCRF_AZ_MSI_64_EN_LBN 7 #define PCRF_AZ_MSI_64_EN_WIDTH 1 #define PCRF_AZ_MSI_MULT_MSG_EN_LBN 4 #define PCRF_AZ_MSI_MULT_MSG_EN_WIDTH 3 #define PCRF_AZ_MSI_MULT_MSG_CAP_LBN 1 #define PCRF_AZ_MSI_MULT_MSG_CAP_WIDTH 3 #define PCRF_AZ_MSI_EN_LBN 0 #define PCRF_AZ_MSI_EN_WIDTH 1 /* * PC_MSI_ADR_LO_REG(32bit): * MSI low 32 bits address register */ -#define PCR_AC_MSI_ADR_LO_REG 0x00000054 -/* falcona0,falconb0,sienaa0=pci_f0_config */ +#define PCR_AZ_MSI_ADR_LO_REG 0x00000054 +/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ -#define PCR_DZ_MSI_ADR_LO_REG 0x00000094 -/* hunta0=pci_f0_config */ - #define PCRF_AZ_MSI_ADR_LO_LBN 2 #define PCRF_AZ_MSI_ADR_LO_WIDTH 30 /* - * PC_VPD_CAP_CTL_REG(8bit): - * VPD control and capabilities register - */ - -#define PCR_DZ_VPD_CAP_CTL_REG 0x00000054 -/* hunta0=pci_f0_config */ - -#define PCR_CC_VPD_CAP_CTL_REG 0x000000d0 -/* sienaa0=pci_f0_config */ - -#define PCRF_CZ_VPD_FLAG_LBN 31 -#define PCRF_CZ_VPD_FLAG_WIDTH 1 -#define PCRF_CZ_VPD_ADDR_LBN 16 -#define PCRF_CZ_VPD_ADDR_WIDTH 15 -#define PCRF_CZ_VPD_NXT_PTR_LBN 8 -#define PCRF_CZ_VPD_NXT_PTR_WIDTH 8 -#define PCRF_CZ_VPD_CAP_ID_LBN 0 -#define PCRF_CZ_VPD_CAP_ID_WIDTH 8 - - -/* - * PC_VPD_CAP_DATA_REG(32bit): - * documentation to be written for sum_PC_VPD_CAP_DATA_REG - */ - -#define PCR_DZ_VPD_CAP_DATA_REG 0x00000058 -/* hunta0=pci_f0_config */ - -#define PCR_AB_VPD_CAP_DATA_REG 0x000000b4 -/* falcona0,falconb0=pci_f0_config */ - -#define PCR_CC_VPD_CAP_DATA_REG 0x000000d4 -/* sienaa0=pci_f0_config */ - -#define PCRF_AZ_VPD_DATA_LBN 0 -#define PCRF_AZ_VPD_DATA_WIDTH 32 - - -/* * PC_MSI_ADR_HI_REG(32bit): * MSI high 32 bits address register */ -#define PCR_AC_MSI_ADR_HI_REG 0x00000058 -/* falcona0,falconb0,sienaa0=pci_f0_config */ +#define PCR_AZ_MSI_ADR_HI_REG 0x00000058 +/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ -#define PCR_DZ_MSI_ADR_HI_REG 0x00000098 -/* hunta0=pci_f0_config */ - #define PCRF_AZ_MSI_ADR_HI_LBN 0 #define PCRF_AZ_MSI_ADR_HI_WIDTH 32 /* * PC_MSI_DAT_REG(16bit): * MSI data register */ -#define PCR_AC_MSI_DAT_REG 0x0000005c -/* falcona0,falconb0,sienaa0=pci_f0_config */ +#define PCR_AZ_MSI_DAT_REG 0x0000005c +/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ -#define PCR_DZ_MSI_DAT_REG 0x0000009c -/* hunta0=pci_f0_config */ - #define PCRF_AZ_MSI_DAT_LBN 0 #define PCRF_AZ_MSI_DAT_WIDTH 16 /* * PC_PCIE_CAP_LIST_REG(16bit): * PCIe capability list register */ #define PCR_AB_PCIE_CAP_LIST_REG 0x00000060 /* falcona0,falconb0=pci_f0_config */ -#define PCR_CC_PCIE_CAP_LIST_REG 0x00000070 -/* sienaa0=pci_f0_config */ +#define PCR_CZ_PCIE_CAP_LIST_REG 0x00000070 +/* sienaa0,hunta0=pci_f0_config */ -#define PCR_DZ_PCIE_CAP_LIST_REG 0x000000c0 -/* hunta0=pci_f0_config */ - #define PCRF_AZ_PCIE_NXT_PTR_LBN 8 #define PCRF_AZ_PCIE_NXT_PTR_WIDTH 8 #define PCRF_AZ_PCIE_CAP_ID_LBN 0 #define PCRF_AZ_PCIE_CAP_ID_WIDTH 8 /* * PC_PCIE_CAP_REG(16bit): * PCIe capability register */ #define PCR_AB_PCIE_CAP_REG 0x00000062 /* falcona0,falconb0=pci_f0_config */ -#define PCR_CC_PCIE_CAP_REG 0x00000072 -/* sienaa0=pci_f0_config */ +#define PCR_CZ_PCIE_CAP_REG 0x00000072 +/* sienaa0,hunta0=pci_f0_config */ -#define PCR_DZ_PCIE_CAP_REG 0x000000c2 -/* hunta0=pci_f0_config */ - #define PCRF_AZ_PCIE_INT_MSG_NUM_LBN 9 #define PCRF_AZ_PCIE_INT_MSG_NUM_WIDTH 5 #define PCRF_AZ_PCIE_SLOT_IMP_LBN 8 #define PCRF_AZ_PCIE_SLOT_IMP_WIDTH 1 #define PCRF_AZ_PCIE_DEV_PORT_TYPE_LBN 4 #define PCRF_AZ_PCIE_DEV_PORT_TYPE_WIDTH 4 #define PCRF_AZ_PCIE_CAP_VER_LBN 0 #define PCRF_AZ_PCIE_CAP_VER_WIDTH 4 /* * PC_DEV_CAP_REG(32bit): * PCIe device capabilities register */ #define PCR_AB_DEV_CAP_REG 0x00000064 /* falcona0,falconb0=pci_f0_config */ -#define PCR_CC_DEV_CAP_REG 0x00000074 -/* sienaa0=pci_f0_config */ +#define PCR_CZ_DEV_CAP_REG 0x00000074 +/* sienaa0=pci_f0_config,hunta0=pci_f0_config */ -#define PCR_DZ_DEV_CAP_REG 0x000000c4 -/* hunta0=pci_f0_config */ - #define PCRF_CZ_CAP_FN_LEVEL_RESET_LBN 28 #define PCRF_CZ_CAP_FN_LEVEL_RESET_WIDTH 1 #define PCRF_AZ_CAP_SLOT_PWR_SCL_LBN 26 #define PCRF_AZ_CAP_SLOT_PWR_SCL_WIDTH 2 #define PCRF_AZ_CAP_SLOT_PWR_VAL_LBN 18 #define PCRF_AZ_CAP_SLOT_PWR_VAL_WIDTH 8 #define PCRF_CZ_ROLE_BASE_ERR_REPORTING_LBN 15 #define PCRF_CZ_ROLE_BASE_ERR_REPORTING_WIDTH 1 #define PCRF_AB_PWR_IND_LBN 14 #define PCRF_AB_PWR_IND_WIDTH 1 #define PCRF_AB_ATTN_IND_LBN 13 #define PCRF_AB_ATTN_IND_WIDTH 1 #define PCRF_AB_ATTN_BUTTON_LBN 12 #define PCRF_AB_ATTN_BUTTON_WIDTH 1 #define PCRF_AZ_ENDPT_L1_LAT_LBN 9 #define PCRF_AZ_ENDPT_L1_LAT_WIDTH 3 #define PCRF_AZ_ENDPT_L0_LAT_LBN 6 #define PCRF_AZ_ENDPT_L0_LAT_WIDTH 3 #define PCRF_AZ_TAG_FIELD_LBN 5 #define PCRF_AZ_TAG_FIELD_WIDTH 1 #define PCRF_AZ_PHAN_FUNC_LBN 3 #define PCRF_AZ_PHAN_FUNC_WIDTH 2 #define PCRF_AZ_MAX_PAYL_SIZE_SUPT_LBN 0 #define PCRF_AZ_MAX_PAYL_SIZE_SUPT_WIDTH 3 /* * PC_DEV_CTL_REG(16bit): * PCIe device control register */ #define PCR_AB_DEV_CTL_REG 0x00000068 /* falcona0,falconb0=pci_f0_config */ -#define PCR_CC_DEV_CTL_REG 0x00000078 -/* sienaa0=pci_f0_config */ +#define PCR_CZ_DEV_CTL_REG 0x00000078 +/* sienaa0,hunta0=pci_f0_config */ -#define PCR_DZ_DEV_CTL_REG 0x000000c8 -/* hunta0=pci_f0_config */ - #define PCRF_CZ_FN_LEVEL_RESET_LBN 15 #define PCRF_CZ_FN_LEVEL_RESET_WIDTH 1 #define PCRF_AZ_MAX_RD_REQ_SIZE_LBN 12 #define PCRF_AZ_MAX_RD_REQ_SIZE_WIDTH 3 #define PCFE_AZ_MAX_RD_REQ_SIZE_4096 5 #define PCFE_AZ_MAX_RD_REQ_SIZE_2048 4 #define PCFE_AZ_MAX_RD_REQ_SIZE_1024 3 #define PCFE_AZ_MAX_RD_REQ_SIZE_512 2 #define PCFE_AZ_MAX_RD_REQ_SIZE_256 1 #define PCFE_AZ_MAX_RD_REQ_SIZE_128 0 -#define PCFE_DZ_OTHER other #define PCRF_AZ_EN_NO_SNOOP_LBN 11 #define PCRF_AZ_EN_NO_SNOOP_WIDTH 1 #define PCRF_AZ_AUX_PWR_PM_EN_LBN 10 #define PCRF_AZ_AUX_PWR_PM_EN_WIDTH 1 #define PCRF_AZ_PHAN_FUNC_EN_LBN 9 #define PCRF_AZ_PHAN_FUNC_EN_WIDTH 1 #define PCRF_AB_DEV_CAP_REG_RSVD0_LBN 8 #define PCRF_AB_DEV_CAP_REG_RSVD0_WIDTH 1 #define PCRF_CZ_EXTENDED_TAG_EN_LBN 8 #define PCRF_CZ_EXTENDED_TAG_EN_WIDTH 1 #define PCRF_AZ_MAX_PAYL_SIZE_LBN 5 #define PCRF_AZ_MAX_PAYL_SIZE_WIDTH 3 #define PCFE_AZ_MAX_PAYL_SIZE_4096 5 #define PCFE_AZ_MAX_PAYL_SIZE_2048 4 #define PCFE_AZ_MAX_PAYL_SIZE_1024 3 #define PCFE_AZ_MAX_PAYL_SIZE_512 2 #define PCFE_AZ_MAX_PAYL_SIZE_256 1 #define PCFE_AZ_MAX_PAYL_SIZE_128 0 -#define PCFE_DZ_OTHER other #define PCRF_AZ_EN_RELAX_ORDER_LBN 4 #define PCRF_AZ_EN_RELAX_ORDER_WIDTH 1 #define PCRF_AZ_UNSUP_REQ_RPT_EN_LBN 3 #define PCRF_AZ_UNSUP_REQ_RPT_EN_WIDTH 1 #define PCRF_AZ_FATAL_ERR_RPT_EN_LBN 2 #define PCRF_AZ_FATAL_ERR_RPT_EN_WIDTH 1 #define PCRF_AZ_NONFATAL_ERR_RPT_EN_LBN 1 #define PCRF_AZ_NONFATAL_ERR_RPT_EN_WIDTH 1 #define PCRF_AZ_CORR_ERR_RPT_EN_LBN 0 #define PCRF_AZ_CORR_ERR_RPT_EN_WIDTH 1 /* * PC_DEV_STAT_REG(16bit): * PCIe device status register */ #define PCR_AB_DEV_STAT_REG 0x0000006a /* falcona0,falconb0=pci_f0_config */ -#define PCR_CC_DEV_STAT_REG 0x0000007a -/* sienaa0=pci_f0_config */ +#define PCR_CZ_DEV_STAT_REG 0x0000007a +/* sienaa0,hunta0=pci_f0_config */ -#define PCR_DZ_DEV_STAT_REG 0x000000ca -/* hunta0=pci_f0_config */ - #define PCRF_AZ_TRNS_PEND_LBN 5 #define PCRF_AZ_TRNS_PEND_WIDTH 1 #define PCRF_AZ_AUX_PWR_DET_LBN 4 #define PCRF_AZ_AUX_PWR_DET_WIDTH 1 #define PCRF_AZ_UNSUP_REQ_DET_LBN 3 #define PCRF_AZ_UNSUP_REQ_DET_WIDTH 1 #define PCRF_AZ_FATAL_ERR_DET_LBN 2 #define PCRF_AZ_FATAL_ERR_DET_WIDTH 1 #define PCRF_AZ_NONFATAL_ERR_DET_LBN 1 #define PCRF_AZ_NONFATAL_ERR_DET_WIDTH 1 #define PCRF_AZ_CORR_ERR_DET_LBN 0 #define PCRF_AZ_CORR_ERR_DET_WIDTH 1 /* * PC_LNK_CAP_REG(32bit): * PCIe link capabilities register */ #define PCR_AB_LNK_CAP_REG 0x0000006c /* falcona0,falconb0=pci_f0_config */ -#define PCR_CC_LNK_CAP_REG 0x0000007c -/* sienaa0=pci_f0_config */ +#define PCR_CZ_LNK_CAP_REG 0x0000007c +/* sienaa0,hunta0=pci_f0_config */ -#define PCR_DZ_LNK_CAP_REG 0x000000cc -/* hunta0=pci_f0_config */ - #define PCRF_AZ_PORT_NUM_LBN 24 #define PCRF_AZ_PORT_NUM_WIDTH 8 +#define PCRF_DZ_ASPM_OPTIONALITY_CAP_LBN 22 +#define PCRF_DZ_ASPM_OPTIONALITY_CAP_WIDTH 1 #define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_LBN 21 #define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_WIDTH 1 #define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_LBN 20 #define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_WIDTH 1 #define PCRF_CZ_SURPISE_DOWN_RPT_CAP_LBN 19 #define PCRF_CZ_SURPISE_DOWN_RPT_CAP_WIDTH 1 #define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_LBN 18 #define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_WIDTH 1 #define PCRF_AZ_DEF_L1_EXIT_LAT_LBN 15 #define PCRF_AZ_DEF_L1_EXIT_LAT_WIDTH 3 #define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_LBN 12 #define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_WIDTH 3 #define PCRF_AZ_AS_LNK_PM_SUPT_LBN 10 #define PCRF_AZ_AS_LNK_PM_SUPT_WIDTH 2 #define PCRF_AZ_MAX_LNK_WIDTH_LBN 4 #define PCRF_AZ_MAX_LNK_WIDTH_WIDTH 6 #define PCRF_AZ_MAX_LNK_SP_LBN 0 #define PCRF_AZ_MAX_LNK_SP_WIDTH 4 /* * PC_LNK_CTL_REG(16bit): * PCIe link control register */ #define PCR_AB_LNK_CTL_REG 0x00000070 /* falcona0,falconb0=pci_f0_config */ -#define PCR_CC_LNK_CTL_REG 0x00000080 -/* sienaa0=pci_f0_config */ +#define PCR_CZ_LNK_CTL_REG 0x00000080 +/* sienaa0,hunta0=pci_f0_config */ -#define PCR_DZ_LNK_CTL_REG 0x000000d0 -/* hunta0=pci_f0_config */ - #define PCRF_AZ_EXT_SYNC_LBN 7 #define PCRF_AZ_EXT_SYNC_WIDTH 1 #define PCRF_AZ_COMM_CLK_CFG_LBN 6 #define PCRF_AZ_COMM_CLK_CFG_WIDTH 1 #define PCRF_AB_LNK_CTL_REG_RSVD0_LBN 5 #define PCRF_AB_LNK_CTL_REG_RSVD0_WIDTH 1 #define PCRF_CZ_LNK_RETRAIN_LBN 5 #define PCRF_CZ_LNK_RETRAIN_WIDTH 1 #define PCRF_AZ_LNK_DIS_LBN 4 #define PCRF_AZ_LNK_DIS_WIDTH 1 #define PCRF_AZ_RD_COM_BDRY_LBN 3 #define PCRF_AZ_RD_COM_BDRY_WIDTH 1 #define PCRF_AZ_ACT_ST_LNK_PM_CTL_LBN 0 #define PCRF_AZ_ACT_ST_LNK_PM_CTL_WIDTH 2 /* * PC_LNK_STAT_REG(16bit): * PCIe link status register */ #define PCR_AB_LNK_STAT_REG 0x00000072 /* falcona0,falconb0=pci_f0_config */ -#define PCR_CC_LNK_STAT_REG 0x00000082 -/* sienaa0=pci_f0_config */ +#define PCR_CZ_LNK_STAT_REG 0x00000082 +/* sienaa0,hunta0=pci_f0_config */ -#define PCR_DZ_LNK_STAT_REG 0x000000d2 -/* hunta0=pci_f0_config */ - #define PCRF_AZ_SLOT_CLK_CFG_LBN 12 #define PCRF_AZ_SLOT_CLK_CFG_WIDTH 1 #define PCRF_AZ_LNK_TRAIN_LBN 11 #define PCRF_AZ_LNK_TRAIN_WIDTH 1 #define PCRF_AB_TRAIN_ERR_LBN 10 #define PCRF_AB_TRAIN_ERR_WIDTH 1 #define PCRF_AZ_LNK_WIDTH_LBN 4 #define PCRF_AZ_LNK_WIDTH_WIDTH 6 #define PCRF_AZ_LNK_SP_LBN 0 #define PCRF_AZ_LNK_SP_WIDTH 4 /* * PC_SLOT_CAP_REG(32bit): * PCIe slot capabilities register */ #define PCR_AB_SLOT_CAP_REG 0x00000074 /* falcona0,falconb0=pci_f0_config */ #define PCRF_AB_SLOT_NUM_LBN 19 #define PCRF_AB_SLOT_NUM_WIDTH 13 #define PCRF_AB_SLOT_PWR_LIM_SCL_LBN 15 #define PCRF_AB_SLOT_PWR_LIM_SCL_WIDTH 2 #define PCRF_AB_SLOT_PWR_LIM_VAL_LBN 7 #define PCRF_AB_SLOT_PWR_LIM_VAL_WIDTH 8 #define PCRF_AB_SLOT_HP_CAP_LBN 6 #define PCRF_AB_SLOT_HP_CAP_WIDTH 1 #define PCRF_AB_SLOT_HP_SURP_LBN 5 #define PCRF_AB_SLOT_HP_SURP_WIDTH 1 #define PCRF_AB_SLOT_PWR_IND_PRST_LBN 4 #define PCRF_AB_SLOT_PWR_IND_PRST_WIDTH 1 #define PCRF_AB_SLOT_ATTN_IND_PRST_LBN 3 #define PCRF_AB_SLOT_ATTN_IND_PRST_WIDTH 1 #define PCRF_AB_SLOT_MRL_SENS_PRST_LBN 2 #define PCRF_AB_SLOT_MRL_SENS_PRST_WIDTH 1 #define PCRF_AB_SLOT_PWR_CTL_PRST_LBN 1 #define PCRF_AB_SLOT_PWR_CTL_PRST_WIDTH 1 #define PCRF_AB_SLOT_ATTN_BUT_PRST_LBN 0 #define PCRF_AB_SLOT_ATTN_BUT_PRST_WIDTH 1 /* * PC_SLOT_CTL_REG(16bit): * PCIe slot control register */ #define PCR_AB_SLOT_CTL_REG 0x00000078 /* falcona0,falconb0=pci_f0_config */ #define PCRF_AB_SLOT_PWR_CTLR_CTL_LBN 10 #define PCRF_AB_SLOT_PWR_CTLR_CTL_WIDTH 1 #define PCRF_AB_SLOT_PWR_IND_CTL_LBN 8 #define PCRF_AB_SLOT_PWR_IND_CTL_WIDTH 2 #define PCRF_AB_SLOT_ATT_IND_CTL_LBN 6 #define PCRF_AB_SLOT_ATT_IND_CTL_WIDTH 2 #define PCRF_AB_SLOT_HP_INT_EN_LBN 5 #define PCRF_AB_SLOT_HP_INT_EN_WIDTH 1 #define PCRF_AB_SLOT_CMD_COMP_INT_EN_LBN 4 #define PCRF_AB_SLOT_CMD_COMP_INT_EN_WIDTH 1 #define PCRF_AB_SLOT_PRES_DET_CHG_EN_LBN 3 #define PCRF_AB_SLOT_PRES_DET_CHG_EN_WIDTH 1 #define PCRF_AB_SLOT_MRL_SENS_CHG_EN_LBN 2 #define PCRF_AB_SLOT_MRL_SENS_CHG_EN_WIDTH 1 #define PCRF_AB_SLOT_PWR_FLTDET_EN_LBN 1 #define PCRF_AB_SLOT_PWR_FLTDET_EN_WIDTH 1 #define PCRF_AB_SLOT_ATTN_BUT_EN_LBN 0 #define PCRF_AB_SLOT_ATTN_BUT_EN_WIDTH 1 /* * PC_SLOT_STAT_REG(16bit): * PCIe slot status register */ #define PCR_AB_SLOT_STAT_REG 0x0000007a /* falcona0,falconb0=pci_f0_config */ #define PCRF_AB_PRES_DET_ST_LBN 6 #define PCRF_AB_PRES_DET_ST_WIDTH 1 #define PCRF_AB_MRL_SENS_ST_LBN 5 #define PCRF_AB_MRL_SENS_ST_WIDTH 1 #define PCRF_AB_SLOT_PWR_IND_LBN 4 #define PCRF_AB_SLOT_PWR_IND_WIDTH 1 #define PCRF_AB_SLOT_ATTN_IND_LBN 3 #define PCRF_AB_SLOT_ATTN_IND_WIDTH 1 #define PCRF_AB_SLOT_MRL_SENS_LBN 2 #define PCRF_AB_SLOT_MRL_SENS_WIDTH 1 #define PCRF_AB_PWR_FLTDET_LBN 1 #define PCRF_AB_PWR_FLTDET_WIDTH 1 #define PCRF_AB_ATTN_BUTDET_LBN 0 #define PCRF_AB_ATTN_BUTDET_WIDTH 1 /* * PC_MSIX_CAP_ID_REG(8bit): * MSIX Capability ID */ #define PCR_BB_MSIX_CAP_ID_REG 0x00000090 /* falconb0=pci_f0_config */ #define PCR_CZ_MSIX_CAP_ID_REG 0x000000b0 /* sienaa0,hunta0=pci_f0_config */ #define PCRF_BZ_MSIX_CAP_ID_LBN 0 #define PCRF_BZ_MSIX_CAP_ID_WIDTH 8 /* * PC_MSIX_NXT_PTR_REG(8bit): * MSIX Capability Next Capability Ptr */ #define PCR_BB_MSIX_NXT_PTR_REG 0x00000091 /* falconb0=pci_f0_config */ #define PCR_CZ_MSIX_NXT_PTR_REG 0x000000b1 /* sienaa0,hunta0=pci_f0_config */ #define PCRF_BZ_MSIX_NXT_PTR_LBN 0 #define PCRF_BZ_MSIX_NXT_PTR_WIDTH 8 /* * PC_MSIX_CTL_REG(16bit): * MSIX control register */ #define PCR_BB_MSIX_CTL_REG 0x00000092 /* falconb0=pci_f0_config */ #define PCR_CZ_MSIX_CTL_REG 0x000000b2 /* sienaa0,hunta0=pci_f0_config */ #define PCRF_BZ_MSIX_EN_LBN 15 #define PCRF_BZ_MSIX_EN_WIDTH 1 #define PCRF_BZ_MSIX_FUNC_MASK_LBN 14 #define PCRF_BZ_MSIX_FUNC_MASK_WIDTH 1 #define PCRF_BZ_MSIX_TBL_SIZE_LBN 0 #define PCRF_BZ_MSIX_TBL_SIZE_WIDTH 11 /* - * PC_DEV_CAP2_REG(16bit): - * PCIe Device Capabilities 2 + * PC_MSIX_TBL_BASE_REG(32bit): + * MSIX Capability Vector Table Base */ -#define PCR_CC_DEV_CAP2_REG 0x00000094 -/* sienaa0=pci_f0_config */ +#define PCR_BB_MSIX_TBL_BASE_REG 0x00000094 +/* falconb0=pci_f0_config */ -#define PCR_DZ_DEV_CAP2_REG 0x000000e4 -/* hunta0=pci_f0_config */ +#define PCR_CZ_MSIX_TBL_BASE_REG 0x000000b4 +/* sienaa0,hunta0=pci_f0_config */ -#define PCRF_CZ_CMPL_TIMEOUT_DIS_LBN 4 -#define PCRF_CZ_CMPL_TIMEOUT_DIS_WIDTH 1 +#define PCRF_BZ_MSIX_TBL_OFF_LBN 3 +#define PCRF_BZ_MSIX_TBL_OFF_WIDTH 29 +#define PCRF_BZ_MSIX_TBL_BIR_LBN 0 +#define PCRF_BZ_MSIX_TBL_BIR_WIDTH 3 + + +/* + * PC_DEV_CAP2_REG(32bit): + * PCIe Device Capabilities 2 + */ + +#define PCR_CZ_DEV_CAP2_REG 0x00000094 +/* sienaa0=pci_f0_config,hunta0=pci_f0_config */ + +#define PCRF_DZ_OBFF_SUPPORTED_LBN 18 +#define PCRF_DZ_OBFF_SUPPORTED_WIDTH 2 +#define PCRF_DZ_TPH_CMPL_SUPPORTED_LBN 12 +#define PCRF_DZ_TPH_CMPL_SUPPORTED_WIDTH 2 +#define PCRF_DZ_LTR_M_SUPPORTED_LBN 11 +#define PCRF_DZ_LTR_M_SUPPORTED_WIDTH 1 +#define PCRF_CC_CMPL_TIMEOUT_DIS_LBN 4 +#define PCRF_CC_CMPL_TIMEOUT_DIS_WIDTH 1 +#define PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_LBN 4 +#define PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_WIDTH 1 #define PCRF_CZ_CMPL_TIMEOUT_LBN 0 #define PCRF_CZ_CMPL_TIMEOUT_WIDTH 4 #define PCFE_CZ_CMPL_TIMEOUT_17000_TO_6400MS 14 #define PCFE_CZ_CMPL_TIMEOUT_4000_TO_1300MS 13 #define PCFE_CZ_CMPL_TIMEOUT_1000_TO_3500MS 10 #define PCFE_CZ_CMPL_TIMEOUT_260_TO_900MS 9 #define PCFE_CZ_CMPL_TIMEOUT_65_TO_210MS 6 #define PCFE_CZ_CMPL_TIMEOUT_16_TO_55MS 5 #define PCFE_CZ_CMPL_TIMEOUT_1_TO_10MS 2 #define PCFE_CZ_CMPL_TIMEOUT_50_TO_100US 1 #define PCFE_CZ_CMPL_TIMEOUT_DEFAULT 0 /* - * PC_MSIX_TBL_BASE_REG(32bit): - * MSIX Capability Vector Table Base - */ - -#define PCR_BB_MSIX_TBL_BASE_REG 0x00000094 -/* falconb0=pci_f0_config */ - -#define PCR_CZ_MSIX_TBL_BASE_REG 0x000000b4 -/* sienaa0,hunta0=pci_f0_config */ - -#define PCRF_BZ_MSIX_TBL_OFF_LBN 3 -#define PCRF_BZ_MSIX_TBL_OFF_WIDTH 29 -#define PCRF_BZ_MSIX_TBL_BIR_LBN 0 -#define PCRF_BZ_MSIX_TBL_BIR_WIDTH 3 - - -/* * PC_DEV_CTL2_REG(16bit): * PCIe Device Control 2 */ -#define PCR_CC_DEV_CTL2_REG 0x00000098 -/* sienaa0=pci_f0_config */ +#define PCR_CZ_DEV_CTL2_REG 0x00000098 +/* sienaa0,hunta0=pci_f0_config */ -#define PCR_DZ_DEV_CTL2_REG 0x000000e8 -/* hunta0=pci_f0_config */ - +#define PCRF_DZ_OBFF_ENABLE_LBN 13 +#define PCRF_DZ_OBFF_ENABLE_WIDTH 2 +#define PCRF_DZ_LTR_ENABLE_LBN 10 +#define PCRF_DZ_LTR_ENABLE_WIDTH 1 +#define PCRF_DZ_IDO_COMPLETION_ENABLE_LBN 9 +#define PCRF_DZ_IDO_COMPLETION_ENABLE_WIDTH 1 +#define PCRF_DZ_IDO_REQUEST_ENABLE_LBN 8 +#define PCRF_DZ_IDO_REQUEST_ENABLE_WIDTH 1 #define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_LBN 4 #define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_WIDTH 1 #define PCRF_CZ_CMPL_TIMEOUT_CTL_LBN 0 #define PCRF_CZ_CMPL_TIMEOUT_CTL_WIDTH 4 /* * PC_MSIX_PBA_BASE_REG(32bit): * MSIX Capability PBA Base */ #define PCR_BB_MSIX_PBA_BASE_REG 0x00000098 /* falconb0=pci_f0_config */ #define PCR_CZ_MSIX_PBA_BASE_REG 0x000000b8 /* sienaa0,hunta0=pci_f0_config */ #define PCRF_BZ_MSIX_PBA_OFF_LBN 3 #define PCRF_BZ_MSIX_PBA_OFF_WIDTH 29 #define PCRF_BZ_MSIX_PBA_BIR_LBN 0 #define PCRF_BZ_MSIX_PBA_BIR_WIDTH 3 /* + * PC_LNK_CAP2_REG(32bit): + * PCIe Link Capability 2 + */ + +#define PCR_DZ_LNK_CAP2_REG 0x0000009c +/* hunta0=pci_f0_config */ + +#define PCRF_DZ_LNK_SPEED_SUP_LBN 1 +#define PCRF_DZ_LNK_SPEED_SUP_WIDTH 7 + + +/* * PC_LNK_CTL2_REG(16bit): * PCIe Link Control 2 */ -#define PCR_CC_LNK_CTL2_REG 0x000000a0 -/* sienaa0=pci_f0_config */ +#define PCR_CZ_LNK_CTL2_REG 0x000000a0 +/* sienaa0,hunta0=pci_f0_config */ -#define PCR_DZ_LNK_CTL2_REG 0x000000f0 -/* hunta0=pci_f0_config */ - #define PCRF_CZ_POLLING_DEEMPH_LVL_LBN 12 #define PCRF_CZ_POLLING_DEEMPH_LVL_WIDTH 1 #define PCRF_CZ_COMPLIANCE_SOS_CTL_LBN 11 #define PCRF_CZ_COMPLIANCE_SOS_CTL_WIDTH 1 #define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_LBN 10 #define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_WIDTH 1 #define PCRF_CZ_TRANSMIT_MARGIN_LBN 7 #define PCRF_CZ_TRANSMIT_MARGIN_WIDTH 3 #define PCRF_CZ_SELECT_DEEMPH_LBN 6 #define PCRF_CZ_SELECT_DEEMPH_WIDTH 1 #define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_LBN 5 #define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_WIDTH 1 #define PCRF_CZ_ENTER_COMPLIANCE_CTL_LBN 4 #define PCRF_CZ_ENTER_COMPLIANCE_CTL_WIDTH 1 #define PCRF_CZ_TGT_LNK_SPEED_CTL_LBN 0 #define PCRF_CZ_TGT_LNK_SPEED_CTL_WIDTH 4 +#define PCFE_DZ_LCTL2_TGT_SPEED_GEN3 3 +#define PCFE_DZ_LCTL2_TGT_SPEED_GEN2 2 +#define PCFE_DZ_LCTL2_TGT_SPEED_GEN1 1 /* * PC_LNK_STAT2_REG(16bit): * PCIe Link Status 2 */ -#define PCR_CC_LNK_STAT2_REG 0x000000a2 -/* sienaa0=pci_f0_config */ +#define PCR_CZ_LNK_STAT2_REG 0x000000a2 +/* sienaa0,hunta0=pci_f0_config */ -#define PCR_DZ_LNK_STAT2_REG 0x000000f2 -/* hunta0=pci_f0_config */ - #define PCRF_CZ_CURRENT_DEEMPH_LBN 0 #define PCRF_CZ_CURRENT_DEEMPH_WIDTH 1 /* * PC_VPD_CAP_ID_REG(8bit): * VPD data register */ #define PCR_AB_VPD_CAP_ID_REG 0x000000b0 /* falcona0,falconb0=pci_f0_config */ #define PCRF_AB_VPD_CAP_ID_LBN 0 #define PCRF_AB_VPD_CAP_ID_WIDTH 8 /* * PC_VPD_NXT_PTR_REG(8bit): * VPD next item pointer */ #define PCR_AB_VPD_NXT_PTR_REG 0x000000b1 /* falcona0,falconb0=pci_f0_config */ #define PCRF_AB_VPD_NXT_PTR_LBN 0 #define PCRF_AB_VPD_NXT_PTR_WIDTH 8 /* * PC_VPD_ADDR_REG(16bit): * VPD address register */ #define PCR_AB_VPD_ADDR_REG 0x000000b2 /* falcona0,falconb0=pci_f0_config */ #define PCRF_AB_VPD_FLAG_LBN 15 #define PCRF_AB_VPD_FLAG_WIDTH 1 #define PCRF_AB_VPD_ADDR_LBN 0 #define PCRF_AB_VPD_ADDR_WIDTH 15 /* + * PC_VPD_CAP_DATA_REG(32bit): + * documentation to be written for sum_PC_VPD_CAP_DATA_REG + */ + +#define PCR_AB_VPD_CAP_DATA_REG 0x000000b4 +/* falcona0,falconb0=pci_f0_config */ + +#define PCR_CZ_VPD_CAP_DATA_REG 0x000000d4 +/* sienaa0,hunta0=pci_f0_config */ + +#define PCRF_AZ_VPD_DATA_LBN 0 +#define PCRF_AZ_VPD_DATA_WIDTH 32 + + +/* + * PC_VPD_CAP_CTL_REG(8bit): + * VPD control and capabilities register + */ + +#define PCR_CZ_VPD_CAP_CTL_REG 0x000000d0 +/* sienaa0,hunta0=pci_f0_config */ + +#define PCRF_CZ_VPD_FLAG_LBN 31 +#define PCRF_CZ_VPD_FLAG_WIDTH 1 +#define PCRF_CZ_VPD_ADDR_LBN 16 +#define PCRF_CZ_VPD_ADDR_WIDTH 15 +#define PCRF_CZ_VPD_NXT_PTR_LBN 8 +#define PCRF_CZ_VPD_NXT_PTR_WIDTH 8 +#define PCRF_CZ_VPD_CAP_ID_LBN 0 +#define PCRF_CZ_VPD_CAP_ID_WIDTH 8 + + +/* * PC_AER_CAP_HDR_REG(32bit): * AER capability header register */ #define PCR_AZ_AER_CAP_HDR_REG 0x00000100 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_AERCAPHDR_NXT_PTR_LBN 20 #define PCRF_AZ_AERCAPHDR_NXT_PTR_WIDTH 12 #define PCRF_AZ_AERCAPHDR_VER_LBN 16 #define PCRF_AZ_AERCAPHDR_VER_WIDTH 4 #define PCRF_AZ_AERCAPHDR_ID_LBN 0 #define PCRF_AZ_AERCAPHDR_ID_WIDTH 16 /* * PC_AER_UNCORR_ERR_STAT_REG(32bit): * AER Uncorrectable error status register */ #define PCR_AZ_AER_UNCORR_ERR_STAT_REG 0x00000104 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_UNSUPT_REQ_ERR_STAT_LBN 20 #define PCRF_AZ_UNSUPT_REQ_ERR_STAT_WIDTH 1 #define PCRF_AZ_ECRC_ERR_STAT_LBN 19 #define PCRF_AZ_ECRC_ERR_STAT_WIDTH 1 #define PCRF_AZ_MALF_TLP_STAT_LBN 18 #define PCRF_AZ_MALF_TLP_STAT_WIDTH 1 #define PCRF_AZ_RX_OVF_STAT_LBN 17 #define PCRF_AZ_RX_OVF_STAT_WIDTH 1 #define PCRF_AZ_UNEXP_COMP_STAT_LBN 16 #define PCRF_AZ_UNEXP_COMP_STAT_WIDTH 1 #define PCRF_AZ_COMP_ABRT_STAT_LBN 15 #define PCRF_AZ_COMP_ABRT_STAT_WIDTH 1 #define PCRF_AZ_COMP_TIMEOUT_STAT_LBN 14 #define PCRF_AZ_COMP_TIMEOUT_STAT_WIDTH 1 #define PCRF_AZ_FC_PROTO_ERR_STAT_LBN 13 #define PCRF_AZ_FC_PROTO_ERR_STAT_WIDTH 1 #define PCRF_AZ_PSON_TLP_STAT_LBN 12 #define PCRF_AZ_PSON_TLP_STAT_WIDTH 1 #define PCRF_AZ_DL_PROTO_ERR_STAT_LBN 4 #define PCRF_AZ_DL_PROTO_ERR_STAT_WIDTH 1 #define PCRF_AB_TRAIN_ERR_STAT_LBN 0 #define PCRF_AB_TRAIN_ERR_STAT_WIDTH 1 /* * PC_AER_UNCORR_ERR_MASK_REG(32bit): * AER Uncorrectable error mask register */ #define PCR_AZ_AER_UNCORR_ERR_MASK_REG 0x00000108 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ +#define PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_LBN 24 +#define PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_WIDTH 1 +#define PCRF_DZ_UNCORR_INT_ERR_MASK_LBN 22 +#define PCRF_DZ_UNCORR_INT_ERR_MASK_WIDTH 1 #define PCRF_AZ_UNSUPT_REQ_ERR_MASK_LBN 20 #define PCRF_AZ_UNSUPT_REQ_ERR_MASK_WIDTH 1 #define PCRF_AZ_ECRC_ERR_MASK_LBN 19 #define PCRF_AZ_ECRC_ERR_MASK_WIDTH 1 #define PCRF_AZ_MALF_TLP_MASK_LBN 18 #define PCRF_AZ_MALF_TLP_MASK_WIDTH 1 #define PCRF_AZ_RX_OVF_MASK_LBN 17 #define PCRF_AZ_RX_OVF_MASK_WIDTH 1 #define PCRF_AZ_UNEXP_COMP_MASK_LBN 16 #define PCRF_AZ_UNEXP_COMP_MASK_WIDTH 1 #define PCRF_AZ_COMP_ABRT_MASK_LBN 15 #define PCRF_AZ_COMP_ABRT_MASK_WIDTH 1 #define PCRF_AZ_COMP_TIMEOUT_MASK_LBN 14 #define PCRF_AZ_COMP_TIMEOUT_MASK_WIDTH 1 #define PCRF_AZ_FC_PROTO_ERR_MASK_LBN 13 #define PCRF_AZ_FC_PROTO_ERR_MASK_WIDTH 1 #define PCRF_AZ_PSON_TLP_MASK_LBN 12 #define PCRF_AZ_PSON_TLP_MASK_WIDTH 1 #define PCRF_AZ_DL_PROTO_ERR_MASK_LBN 4 #define PCRF_AZ_DL_PROTO_ERR_MASK_WIDTH 1 #define PCRF_AB_TRAIN_ERR_MASK_LBN 0 #define PCRF_AB_TRAIN_ERR_MASK_WIDTH 1 /* * PC_AER_UNCORR_ERR_SEV_REG(32bit): * AER Uncorrectable error severity register */ #define PCR_AZ_AER_UNCORR_ERR_SEV_REG 0x0000010c /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_UNSUPT_REQ_ERR_SEV_LBN 20 #define PCRF_AZ_UNSUPT_REQ_ERR_SEV_WIDTH 1 #define PCRF_AZ_ECRC_ERR_SEV_LBN 19 #define PCRF_AZ_ECRC_ERR_SEV_WIDTH 1 #define PCRF_AZ_MALF_TLP_SEV_LBN 18 #define PCRF_AZ_MALF_TLP_SEV_WIDTH 1 #define PCRF_AZ_RX_OVF_SEV_LBN 17 #define PCRF_AZ_RX_OVF_SEV_WIDTH 1 #define PCRF_AZ_UNEXP_COMP_SEV_LBN 16 #define PCRF_AZ_UNEXP_COMP_SEV_WIDTH 1 #define PCRF_AZ_COMP_ABRT_SEV_LBN 15 #define PCRF_AZ_COMP_ABRT_SEV_WIDTH 1 #define PCRF_AZ_COMP_TIMEOUT_SEV_LBN 14 #define PCRF_AZ_COMP_TIMEOUT_SEV_WIDTH 1 #define PCRF_AZ_FC_PROTO_ERR_SEV_LBN 13 #define PCRF_AZ_FC_PROTO_ERR_SEV_WIDTH 1 #define PCRF_AZ_PSON_TLP_SEV_LBN 12 #define PCRF_AZ_PSON_TLP_SEV_WIDTH 1 #define PCRF_AZ_DL_PROTO_ERR_SEV_LBN 4 #define PCRF_AZ_DL_PROTO_ERR_SEV_WIDTH 1 #define PCRF_AB_TRAIN_ERR_SEV_LBN 0 #define PCRF_AB_TRAIN_ERR_SEV_WIDTH 1 /* * PC_AER_CORR_ERR_STAT_REG(32bit): * AER Correctable error status register */ #define PCR_AZ_AER_CORR_ERR_STAT_REG 0x00000110 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_CZ_ADVSY_NON_FATAL_STAT_LBN 13 #define PCRF_CZ_ADVSY_NON_FATAL_STAT_WIDTH 1 #define PCRF_AZ_RPLY_TMR_TOUT_STAT_LBN 12 #define PCRF_AZ_RPLY_TMR_TOUT_STAT_WIDTH 1 #define PCRF_AZ_RPLAY_NUM_RO_STAT_LBN 8 #define PCRF_AZ_RPLAY_NUM_RO_STAT_WIDTH 1 #define PCRF_AZ_BAD_DLLP_STAT_LBN 7 #define PCRF_AZ_BAD_DLLP_STAT_WIDTH 1 #define PCRF_AZ_BAD_TLP_STAT_LBN 6 #define PCRF_AZ_BAD_TLP_STAT_WIDTH 1 #define PCRF_AZ_RX_ERR_STAT_LBN 0 #define PCRF_AZ_RX_ERR_STAT_WIDTH 1 /* * PC_AER_CORR_ERR_MASK_REG(32bit): * AER Correctable error status register */ #define PCR_AZ_AER_CORR_ERR_MASK_REG 0x00000114 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_CZ_ADVSY_NON_FATAL_MASK_LBN 13 #define PCRF_CZ_ADVSY_NON_FATAL_MASK_WIDTH 1 #define PCRF_AZ_RPLY_TMR_TOUT_MASK_LBN 12 #define PCRF_AZ_RPLY_TMR_TOUT_MASK_WIDTH 1 #define PCRF_AZ_RPLAY_NUM_RO_MASK_LBN 8 #define PCRF_AZ_RPLAY_NUM_RO_MASK_WIDTH 1 #define PCRF_AZ_BAD_DLLP_MASK_LBN 7 #define PCRF_AZ_BAD_DLLP_MASK_WIDTH 1 #define PCRF_AZ_BAD_TLP_MASK_LBN 6 #define PCRF_AZ_BAD_TLP_MASK_WIDTH 1 #define PCRF_AZ_RX_ERR_MASK_LBN 0 #define PCRF_AZ_RX_ERR_MASK_WIDTH 1 /* * PC_AER_CAP_CTL_REG(32bit): * AER capability and control register */ #define PCR_AZ_AER_CAP_CTL_REG 0x00000118 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_ECRC_CHK_EN_LBN 8 #define PCRF_AZ_ECRC_CHK_EN_WIDTH 1 #define PCRF_AZ_ECRC_CHK_CAP_LBN 7 #define PCRF_AZ_ECRC_CHK_CAP_WIDTH 1 #define PCRF_AZ_ECRC_GEN_EN_LBN 6 #define PCRF_AZ_ECRC_GEN_EN_WIDTH 1 #define PCRF_AZ_ECRC_GEN_CAP_LBN 5 #define PCRF_AZ_ECRC_GEN_CAP_WIDTH 1 #define PCRF_AZ_1ST_ERR_PTR_LBN 0 #define PCRF_AZ_1ST_ERR_PTR_WIDTH 5 /* * PC_AER_HDR_LOG_REG(128bit): * AER Header log register */ #define PCR_AZ_AER_HDR_LOG_REG 0x0000011c /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ #define PCRF_AZ_HDR_LOG_LBN 0 #define PCRF_AZ_HDR_LOG_WIDTH 128 /* * PC_DEVSN_CAP_HDR_REG(32bit): * Device serial number capability header register */ -#define PCR_DZ_DEVSN_CAP_HDR_REG 0x00000130 -/* hunta0=pci_f0_config */ +#define PCR_CZ_DEVSN_CAP_HDR_REG 0x00000140 +/* sienaa0,hunta0=pci_f0_config */ -#define PCR_CC_DEVSN_CAP_HDR_REG 0x00000140 -/* sienaa0=pci_f0_config */ - #define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_LBN 20 #define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_WIDTH 12 #define PCRF_CZ_DEVSNCAPHDR_VER_LBN 16 #define PCRF_CZ_DEVSNCAPHDR_VER_WIDTH 4 #define PCRF_CZ_DEVSNCAPHDR_ID_LBN 0 #define PCRF_CZ_DEVSNCAPHDR_ID_WIDTH 16 /* * PC_DEVSN_DWORD0_REG(32bit): * Device serial number DWORD0 */ -#define PCR_DZ_DEVSN_DWORD0_REG 0x00000134 -/* hunta0=pci_f0_config */ +#define PCR_CZ_DEVSN_DWORD0_REG 0x00000144 +/* sienaa0,hunta0=pci_f0_config */ -#define PCR_CC_DEVSN_DWORD0_REG 0x00000144 -/* sienaa0=pci_f0_config */ - #define PCRF_CZ_DEVSN_DWORD0_LBN 0 #define PCRF_CZ_DEVSN_DWORD0_WIDTH 32 /* * PC_DEVSN_DWORD1_REG(32bit): * Device serial number DWORD0 */ -#define PCR_DZ_DEVSN_DWORD1_REG 0x00000138 -/* hunta0=pci_f0_config */ +#define PCR_CZ_DEVSN_DWORD1_REG 0x00000148 +/* sienaa0,hunta0=pci_f0_config */ -#define PCR_CC_DEVSN_DWORD1_REG 0x00000148 -/* sienaa0=pci_f0_config */ - #define PCRF_CZ_DEVSN_DWORD1_LBN 0 #define PCRF_CZ_DEVSN_DWORD1_WIDTH 32 /* * PC_ARI_CAP_HDR_REG(32bit): * ARI capability header register */ -#define PCR_DZ_ARI_CAP_HDR_REG 0x00000140 -/* hunta0=pci_f0_config */ +#define PCR_CZ_ARI_CAP_HDR_REG 0x00000150 +/* sienaa0,hunta0=pci_f0_config */ -#define PCR_CC_ARI_CAP_HDR_REG 0x00000150 -/* sienaa0=pci_f0_config */ - #define PCRF_CZ_ARICAPHDR_NXT_PTR_LBN 20 #define PCRF_CZ_ARICAPHDR_NXT_PTR_WIDTH 12 #define PCRF_CZ_ARICAPHDR_VER_LBN 16 #define PCRF_CZ_ARICAPHDR_VER_WIDTH 4 #define PCRF_CZ_ARICAPHDR_ID_LBN 0 #define PCRF_CZ_ARICAPHDR_ID_WIDTH 16 /* * PC_ARI_CAP_REG(16bit): * ARI Capabilities */ -#define PCR_DZ_ARI_CAP_REG 0x00000144 -/* hunta0=pci_f0_config */ +#define PCR_CZ_ARI_CAP_REG 0x00000154 +/* sienaa0,hunta0=pci_f0_config */ -#define PCR_CC_ARI_CAP_REG 0x00000154 -/* sienaa0=pci_f0_config */ - #define PCRF_CZ_ARI_NXT_FN_NUM_LBN 8 #define PCRF_CZ_ARI_NXT_FN_NUM_WIDTH 8 #define PCRF_CZ_ARI_ACS_FNGRP_CAP_LBN 1 #define PCRF_CZ_ARI_ACS_FNGRP_CAP_WIDTH 1 #define PCRF_CZ_ARI_MFVC_FNGRP_CAP_LBN 0 #define PCRF_CZ_ARI_MFVC_FNGRP_CAP_WIDTH 1 /* * PC_ARI_CTL_REG(16bit): * ARI Control */ -#define PCR_DZ_ARI_CTL_REG 0x00000146 -/* hunta0=pci_f0_config */ +#define PCR_CZ_ARI_CTL_REG 0x00000156 +/* sienaa0,hunta0=pci_f0_config */ -#define PCR_CC_ARI_CTL_REG 0x00000156 -/* sienaa0=pci_f0_config */ - #define PCRF_CZ_ARI_FN_GRP_LBN 4 #define PCRF_CZ_ARI_FN_GRP_WIDTH 3 #define PCRF_CZ_ARI_ACS_FNGRP_EN_LBN 1 #define PCRF_CZ_ARI_ACS_FNGRP_EN_WIDTH 1 #define PCRF_CZ_ARI_MFVC_FNGRP_EN_LBN 0 #define PCRF_CZ_ARI_MFVC_FNGRP_EN_WIDTH 1 /* + * PC_SEC_PCIE_CAP_REG(32bit): + * Secondary PCIE Capability Register + */ + +#define PCR_DZ_SEC_PCIE_CAP_REG 0x00000160 +/* hunta0=pci_f0_config */ + +#define PCRF_DZ_SEC_NXT_PTR_LBN 20 +#define PCRF_DZ_SEC_NXT_PTR_WIDTH 12 +#define PCRF_DZ_SEC_VERSION_LBN 16 +#define PCRF_DZ_SEC_VERSION_WIDTH 4 +#define PCRF_DZ_SEC_EXT_CAP_ID_LBN 0 +#define PCRF_DZ_SEC_EXT_CAP_ID_WIDTH 16 + + +/* * PC_SRIOV_CAP_HDR_REG(32bit): * SRIOV capability header register */ #define PCR_CC_SRIOV_CAP_HDR_REG 0x00000160 /* sienaa0=pci_f0_config */ -#define PCR_DZ_SRIOV_CAP_HDR_REG 0x00000200 +#define PCR_DZ_SRIOV_CAP_HDR_REG 0x00000180 /* hunta0=pci_f0_config */ #define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_LBN 20 #define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_WIDTH 12 #define PCRF_CZ_SRIOVCAPHDR_VER_LBN 16 #define PCRF_CZ_SRIOVCAPHDR_VER_WIDTH 4 #define PCRF_CZ_SRIOVCAPHDR_ID_LBN 0 #define PCRF_CZ_SRIOVCAPHDR_ID_WIDTH 16 /* * PC_SRIOV_CAP_REG(32bit): * SRIOV Capabilities */ #define PCR_CC_SRIOV_CAP_REG 0x00000164 /* sienaa0=pci_f0_config */ -#define PCR_DZ_SRIOV_CAP_REG 0x00000204 +#define PCR_DZ_SRIOV_CAP_REG 0x00000184 /* hunta0=pci_f0_config */ #define PCRF_CZ_VF_MIGR_INT_MSG_NUM_LBN 21 #define PCRF_CZ_VF_MIGR_INT_MSG_NUM_WIDTH 11 +#define PCRF_DZ_VF_ARI_CAP_PRESV_LBN 1 +#define PCRF_DZ_VF_ARI_CAP_PRESV_WIDTH 1 #define PCRF_CZ_VF_MIGR_CAP_LBN 0 #define PCRF_CZ_VF_MIGR_CAP_WIDTH 1 /* + * PC_LINK_CONTROL3_REG(32bit): + * Link Control 3. + */ + +#define PCR_DZ_LINK_CONTROL3_REG 0x00000164 +/* hunta0=pci_f0_config */ + +#define PCRF_DZ_LINK_EQ_INT_EN_LBN 1 +#define PCRF_DZ_LINK_EQ_INT_EN_WIDTH 1 +#define PCRF_DZ_PERFORM_EQL_LBN 0 +#define PCRF_DZ_PERFORM_EQL_WIDTH 1 + + +/* + * PC_LANE_ERROR_STAT_REG(32bit): + * Lane Error Status Register. + */ + +#define PCR_DZ_LANE_ERROR_STAT_REG 0x00000168 +/* hunta0=pci_f0_config */ + +#define PCRF_DZ_LANE_STATUS_LBN 0 +#define PCRF_DZ_LANE_STATUS_WIDTH 8 + + +/* * PC_SRIOV_CTL_REG(16bit): * SRIOV Control */ #define PCR_CC_SRIOV_CTL_REG 0x00000168 /* sienaa0=pci_f0_config */ -#define PCR_DZ_SRIOV_CTL_REG 0x00000208 +#define PCR_DZ_SRIOV_CTL_REG 0x00000188 /* hunta0=pci_f0_config */ #define PCRF_CZ_VF_ARI_CAP_HRCHY_LBN 4 #define PCRF_CZ_VF_ARI_CAP_HRCHY_WIDTH 1 #define PCRF_CZ_VF_MSE_LBN 3 #define PCRF_CZ_VF_MSE_WIDTH 1 #define PCRF_CZ_VF_MIGR_INT_EN_LBN 2 #define PCRF_CZ_VF_MIGR_INT_EN_WIDTH 1 #define PCRF_CZ_VF_MIGR_EN_LBN 1 #define PCRF_CZ_VF_MIGR_EN_WIDTH 1 #define PCRF_CZ_VF_EN_LBN 0 #define PCRF_CZ_VF_EN_WIDTH 1 /* * PC_SRIOV_STAT_REG(16bit): * SRIOV Status */ #define PCR_CC_SRIOV_STAT_REG 0x0000016a /* sienaa0=pci_f0_config */ -#define PCR_DZ_SRIOV_STAT_REG 0x0000020a +#define PCR_DZ_SRIOV_STAT_REG 0x0000018a /* hunta0=pci_f0_config */ #define PCRF_CZ_VF_MIGR_STAT_LBN 0 #define PCRF_CZ_VF_MIGR_STAT_WIDTH 1 /* + * PC_LANE01_EQU_CONTROL_REG(32bit): + * Lanes 0,1 Equalization Control Register. + */ + +#define PCR_DZ_LANE01_EQU_CONTROL_REG 0x0000016c +/* hunta0=pci_f0_config */ + +#define PCRF_DZ_LANE1_EQ_CTRL_LBN 16 +#define PCRF_DZ_LANE1_EQ_CTRL_WIDTH 16 +#define PCRF_DZ_LANE0_EQ_CTRL_LBN 0 +#define PCRF_DZ_LANE0_EQ_CTRL_WIDTH 16 + + +/* * PC_SRIOV_INITIALVFS_REG(16bit): * SRIOV Initial VFs */ #define PCR_CC_SRIOV_INITIALVFS_REG 0x0000016c /* sienaa0=pci_f0_config */ -#define PCR_DZ_SRIOV_INITIALVFS_REG 0x0000020c +#define PCR_DZ_SRIOV_INITIALVFS_REG 0x0000018c /* hunta0=pci_f0_config */ #define PCRF_CZ_VF_INITIALVFS_LBN 0 #define PCRF_CZ_VF_INITIALVFS_WIDTH 16 /* * PC_SRIOV_TOTALVFS_REG(10bit): * SRIOV Total VFs */ #define PCR_CC_SRIOV_TOTALVFS_REG 0x0000016e /* sienaa0=pci_f0_config */ -#define PCR_DZ_SRIOV_TOTALVFS_REG 0x0000020e +#define PCR_DZ_SRIOV_TOTALVFS_REG 0x0000018e /* hunta0=pci_f0_config */ #define PCRF_CZ_VF_TOTALVFS_LBN 0 #define PCRF_CZ_VF_TOTALVFS_WIDTH 16 /* * PC_SRIOV_NUMVFS_REG(16bit): * SRIOV Number of VFs */ #define PCR_CC_SRIOV_NUMVFS_REG 0x00000170 /* sienaa0=pci_f0_config */ -#define PCR_DZ_SRIOV_NUMVFS_REG 0x00000210 +#define PCR_DZ_SRIOV_NUMVFS_REG 0x00000190 /* hunta0=pci_f0_config */ #define PCRF_CZ_VF_NUMVFS_LBN 0 #define PCRF_CZ_VF_NUMVFS_WIDTH 16 /* + * PC_LANE23_EQU_CONTROL_REG(32bit): + * Lanes 2,3 Equalization Control Register. + */ + +#define PCR_DZ_LANE23_EQU_CONTROL_REG 0x00000170 +/* hunta0=pci_f0_config */ + +#define PCRF_DZ_LANE3_EQ_CTRL_LBN 16 +#define PCRF_DZ_LANE3_EQ_CTRL_WIDTH 16 +#define PCRF_DZ_LANE2_EQ_CTRL_LBN 0 +#define PCRF_DZ_LANE2_EQ_CTRL_WIDTH 16 + + +/* * PC_SRIOV_FN_DPND_LNK_REG(16bit): * SRIOV Function dependency link */ #define PCR_CC_SRIOV_FN_DPND_LNK_REG 0x00000172 /* sienaa0=pci_f0_config */ -#define PCR_DZ_SRIOV_FN_DPND_LNK_REG 0x00000212 +#define PCR_DZ_SRIOV_FN_DPND_LNK_REG 0x00000192 /* hunta0=pci_f0_config */ #define PCRF_CZ_SRIOV_FN_DPND_LNK_LBN 0 #define PCRF_CZ_SRIOV_FN_DPND_LNK_WIDTH 8 /* * PC_SRIOV_1STVF_OFFSET_REG(16bit): * SRIOV First VF Offset */ #define PCR_CC_SRIOV_1STVF_OFFSET_REG 0x00000174 /* sienaa0=pci_f0_config */ -#define PCR_DZ_SRIOV_1STVF_OFFSET_REG 0x00000214 +#define PCR_DZ_SRIOV_1STVF_OFFSET_REG 0x00000194 /* hunta0=pci_f0_config */ #define PCRF_CZ_VF_1STVF_OFFSET_LBN 0 #define PCRF_CZ_VF_1STVF_OFFSET_WIDTH 16 /* + * PC_LANE45_EQU_CONTROL_REG(32bit): + * Lanes 4,5 Equalization Control Register. + */ + +#define PCR_DZ_LANE45_EQU_CONTROL_REG 0x00000174 +/* hunta0=pci_f0_config */ + +#define PCRF_DZ_LANE5_EQ_CTRL_LBN 16 +#define PCRF_DZ_LANE5_EQ_CTRL_WIDTH 16 +#define PCRF_DZ_LANE4_EQ_CTRL_LBN 0 +#define PCRF_DZ_LANE4_EQ_CTRL_WIDTH 16 + + +/* * PC_SRIOV_VFSTRIDE_REG(16bit): * SRIOV VF Stride */ #define PCR_CC_SRIOV_VFSTRIDE_REG 0x00000176 /* sienaa0=pci_f0_config */ -#define PCR_DZ_SRIOV_VFSTRIDE_REG 0x00000216 +#define PCR_DZ_SRIOV_VFSTRIDE_REG 0x00000196 /* hunta0=pci_f0_config */ #define PCRF_CZ_VF_VFSTRIDE_LBN 0 #define PCRF_CZ_VF_VFSTRIDE_WIDTH 16 /* + * PC_LANE67_EQU_CONTROL_REG(32bit): + * Lanes 6,7 Equalization Control Register. + */ + +#define PCR_DZ_LANE67_EQU_CONTROL_REG 0x00000178 +/* hunta0=pci_f0_config */ + +#define PCRF_DZ_LANE7_EQ_CTRL_LBN 16 +#define PCRF_DZ_LANE7_EQ_CTRL_WIDTH 16 +#define PCRF_DZ_LANE6_EQ_CTRL_LBN 0 +#define PCRF_DZ_LANE6_EQ_CTRL_WIDTH 16 + + +/* * PC_SRIOV_DEVID_REG(16bit): * SRIOV VF Device ID */ #define PCR_CC_SRIOV_DEVID_REG 0x0000017a /* sienaa0=pci_f0_config */ -#define PCR_DZ_SRIOV_DEVID_REG 0x0000021a +#define PCR_DZ_SRIOV_DEVID_REG 0x0000019a /* hunta0=pci_f0_config */ #define PCRF_CZ_VF_DEVID_LBN 0 #define PCRF_CZ_VF_DEVID_WIDTH 16 /* * PC_SRIOV_SUP_PAGESZ_REG(16bit): * SRIOV Supported Page Sizes */ #define PCR_CC_SRIOV_SUP_PAGESZ_REG 0x0000017c /* sienaa0=pci_f0_config */ -#define PCR_DZ_SRIOV_SUP_PAGESZ_REG 0x0000021c +#define PCR_DZ_SRIOV_SUP_PAGESZ_REG 0x0000019c /* hunta0=pci_f0_config */ #define PCRF_CZ_VF_SUP_PAGESZ_LBN 0 #define PCRF_CZ_VF_SUP_PAGESZ_WIDTH 16 /* * PC_SRIOV_SYS_PAGESZ_REG(32bit): * SRIOV System Page Size */ #define PCR_CC_SRIOV_SYS_PAGESZ_REG 0x00000180 /* sienaa0=pci_f0_config */ -#define PCR_DZ_SRIOV_SYS_PAGESZ_REG 0x00000220 +#define PCR_DZ_SRIOV_SYS_PAGESZ_REG 0x000001a0 /* hunta0=pci_f0_config */ #define PCRF_CZ_VF_SYS_PAGESZ_LBN 0 #define PCRF_CZ_VF_SYS_PAGESZ_WIDTH 16 /* * PC_SRIOV_BAR0_REG(32bit): * SRIOV VF Bar0 */ #define PCR_CC_SRIOV_BAR0_REG 0x00000184 /* sienaa0=pci_f0_config */ -#define PCR_DZ_SRIOV_BAR0_REG 0x00000224 +#define PCR_DZ_SRIOV_BAR0_REG 0x000001a4 /* hunta0=pci_f0_config */ #define PCRF_CC_VF_BAR_ADDRESS_LBN 0 #define PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 -#define PCRF_DZ_VF_BAR0_ADDRESS_LBN 0 -#define PCRF_DZ_VF_BAR0_ADDRESS_WIDTH 32 +#define PCRF_DZ_VF_BAR0_ADDRESS_LBN 4 +#define PCRF_DZ_VF_BAR0_ADDRESS_WIDTH 28 +#define PCRF_DZ_VF_BAR0_PREF_LBN 3 +#define PCRF_DZ_VF_BAR0_PREF_WIDTH 1 +#define PCRF_DZ_VF_BAR0_TYPE_LBN 1 +#define PCRF_DZ_VF_BAR0_TYPE_WIDTH 2 +#define PCRF_DZ_VF_BAR0_IOM_LBN 0 +#define PCRF_DZ_VF_BAR0_IOM_WIDTH 1 /* * PC_SRIOV_BAR1_REG(32bit): * SRIOV Bar1 */ #define PCR_CC_SRIOV_BAR1_REG 0x00000188 /* sienaa0=pci_f0_config */ -#define PCR_DZ_SRIOV_BAR1_REG 0x00000228 +#define PCR_DZ_SRIOV_BAR1_REG 0x000001a8 /* hunta0=pci_f0_config */ /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ #define PCRF_DZ_VF_BAR1_ADDRESS_LBN 0 #define PCRF_DZ_VF_BAR1_ADDRESS_WIDTH 32 /* * PC_SRIOV_BAR2_REG(32bit): * SRIOV Bar2 */ #define PCR_CC_SRIOV_BAR2_REG 0x0000018c /* sienaa0=pci_f0_config */ -#define PCR_DZ_SRIOV_BAR2_REG 0x0000022c +#define PCR_DZ_SRIOV_BAR2_REG 0x000001ac /* hunta0=pci_f0_config */ /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ -#define PCRF_DZ_VF_BAR2_ADDRESS_LBN 0 -#define PCRF_DZ_VF_BAR2_ADDRESS_WIDTH 32 +#define PCRF_DZ_VF_BAR2_ADDRESS_LBN 4 +#define PCRF_DZ_VF_BAR2_ADDRESS_WIDTH 28 +#define PCRF_DZ_VF_BAR2_PREF_LBN 3 +#define PCRF_DZ_VF_BAR2_PREF_WIDTH 1 +#define PCRF_DZ_VF_BAR2_TYPE_LBN 1 +#define PCRF_DZ_VF_BAR2_TYPE_WIDTH 2 +#define PCRF_DZ_VF_BAR2_IOM_LBN 0 +#define PCRF_DZ_VF_BAR2_IOM_WIDTH 1 /* * PC_SRIOV_BAR3_REG(32bit): * SRIOV Bar3 */ #define PCR_CC_SRIOV_BAR3_REG 0x00000190 /* sienaa0=pci_f0_config */ -#define PCR_DZ_SRIOV_BAR3_REG 0x00000230 +#define PCR_DZ_SRIOV_BAR3_REG 0x000001b0 /* hunta0=pci_f0_config */ /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ #define PCRF_DZ_VF_BAR3_ADDRESS_LBN 0 #define PCRF_DZ_VF_BAR3_ADDRESS_WIDTH 32 /* * PC_SRIOV_BAR4_REG(32bit): * SRIOV Bar4 */ #define PCR_CC_SRIOV_BAR4_REG 0x00000194 /* sienaa0=pci_f0_config */ -#define PCR_DZ_SRIOV_BAR4_REG 0x00000234 +#define PCR_DZ_SRIOV_BAR4_REG 0x000001b4 /* hunta0=pci_f0_config */ /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ #define PCRF_DZ_VF_BAR4_ADDRESS_LBN 0 #define PCRF_DZ_VF_BAR4_ADDRESS_WIDTH 32 /* * PC_SRIOV_BAR5_REG(32bit): * SRIOV Bar5 */ #define PCR_CC_SRIOV_BAR5_REG 0x00000198 /* sienaa0=pci_f0_config */ -#define PCR_DZ_SRIOV_BAR5_REG 0x00000238 +#define PCR_DZ_SRIOV_BAR5_REG 0x000001b8 /* hunta0=pci_f0_config */ /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ #define PCRF_DZ_VF_BAR5_ADDRESS_LBN 0 #define PCRF_DZ_VF_BAR5_ADDRESS_WIDTH 32 /* + * PC_SRIOV_RSVD_REG(16bit): + * Reserved register + */ + +#define PCR_DZ_SRIOV_RSVD_REG 0x00000198 +/* hunta0=pci_f0_config */ + +#define PCRF_DZ_VF_RSVD_LBN 0 +#define PCRF_DZ_VF_RSVD_WIDTH 16 + + +/* * PC_SRIOV_MIBR_SARRAY_OFFSET_REG(32bit): * SRIOV VF Migration State Array Offset */ #define PCR_CC_SRIOV_MIBR_SARRAY_OFFSET_REG 0x0000019c /* sienaa0=pci_f0_config */ -#define PCR_DZ_SRIOV_MIBR_SARRAY_OFFSET_REG 0x0000023c +#define PCR_DZ_SRIOV_MIBR_SARRAY_OFFSET_REG 0x000001bc /* hunta0=pci_f0_config */ #define PCRF_CZ_VF_MIGR_OFFSET_LBN 3 #define PCRF_CZ_VF_MIGR_OFFSET_WIDTH 29 #define PCRF_CZ_VF_MIGR_BIR_LBN 0 #define PCRF_CZ_VF_MIGR_BIR_WIDTH 3 /* - * PC_LTR_CAP_HDR_REG(32bit): - * Latency Tolerance Reporting Cap Header Reg - */ - -#define PCR_DZ_LTR_CAP_HDR_REG 0x00000240 -/* hunta0=pci_f0_config */ - -#define PCRF_DZ_LTR_NXT_PTR_LBN 20 -#define PCRF_DZ_LTR_NXT_PTR_WIDTH 12 -#define PCRF_DZ_LTR_VERSION_LBN 16 -#define PCRF_DZ_LTR_VERSION_WIDTH 4 -#define PCRF_DZ_LTR_EXT_CAP_ID_LBN 0 -#define PCRF_DZ_LTR_EXT_CAP_ID_WIDTH 16 - - -/* - * PC_LTR_MAX_SNOOP_REG(32bit): - * LTR Maximum Snoop/No Snoop Register - */ - -#define PCR_DZ_LTR_MAX_SNOOP_REG 0x00000244 -/* hunta0=pci_f0_config */ - -#define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_LBN 26 -#define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_WIDTH 3 -#define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_LBN 16 -#define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_WIDTH 10 -#define PCRF_DZ_LTR_MAX_SNOOP_SCALE_LBN 10 -#define PCRF_DZ_LTR_MAX_SNOOP_SCALE_WIDTH 3 -#define PCRF_DZ_LTR_MAX_SNOOP_LAT_LBN 0 -#define PCRF_DZ_LTR_MAX_SNOOP_LAT_WIDTH 10 - - -/* * PC_TPH_CAP_HDR_REG(32bit): * TPH Capability Header Register */ -#define PCR_DZ_TPH_CAP_HDR_REG 0x00000274 +#define PCR_DZ_TPH_CAP_HDR_REG 0x000001c0 /* hunta0=pci_f0_config */ #define PCRF_DZ_TPH_NXT_PTR_LBN 20 #define PCRF_DZ_TPH_NXT_PTR_WIDTH 12 #define PCRF_DZ_TPH_VERSION_LBN 16 #define PCRF_DZ_TPH_VERSION_WIDTH 4 #define PCRF_DZ_TPH_EXT_CAP_ID_LBN 0 #define PCRF_DZ_TPH_EXT_CAP_ID_WIDTH 16 /* * PC_TPH_REQ_CAP_REG(32bit): * TPH Requester Capability Register */ -#define PCR_DZ_TPH_REQ_CAP_REG 0x00000278 +#define PCR_DZ_TPH_REQ_CAP_REG 0x000001c4 /* hunta0=pci_f0_config */ #define PCRF_DZ_ST_TBLE_SIZE_LBN 16 #define PCRF_DZ_ST_TBLE_SIZE_WIDTH 11 #define PCRF_DZ_ST_TBLE_LOC_LBN 9 #define PCRF_DZ_ST_TBLE_LOC_WIDTH 2 #define PCRF_DZ_EXT_TPH_MODE_SUP_LBN 8 #define PCRF_DZ_EXT_TPH_MODE_SUP_WIDTH 1 #define PCRF_DZ_TPH_DEV_MODE_SUP_LBN 2 #define PCRF_DZ_TPH_DEV_MODE_SUP_WIDTH 1 #define PCRF_DZ_TPH_INT_MODE_SUP_LBN 1 #define PCRF_DZ_TPH_INT_MODE_SUP_WIDTH 1 #define PCRF_DZ_TPH_NOST_MODE_SUP_LBN 0 #define PCRF_DZ_TPH_NOST_MODE_SUP_WIDTH 1 /* * PC_TPH_REQ_CTL_REG(32bit): * TPH Requester Control Register */ -#define PCR_DZ_TPH_REQ_CTL_REG 0x0000027c +#define PCR_DZ_TPH_REQ_CTL_REG 0x000001c8 /* hunta0=pci_f0_config */ #define PCRF_DZ_TPH_REQ_ENABLE_LBN 8 #define PCRF_DZ_TPH_REQ_ENABLE_WIDTH 2 #define PCRF_DZ_TPH_ST_MODE_LBN 0 #define PCRF_DZ_TPH_ST_MODE_WIDTH 3 /* - * PC_SEC_PCIE_CAP_REG(32bit): - * Secondary PCIE Capability Register + * PC_LTR_CAP_HDR_REG(32bit): + * Latency Tolerance Reporting Cap Header Reg */ -#define PCR_DZ_SEC_PCIE_CAP_REG 0x00000300 +#define PCR_DZ_LTR_CAP_HDR_REG 0x00000290 /* hunta0=pci_f0_config */ -#define PCRF_DZ_SEC_NXT_PTR_LBN 20 -#define PCRF_DZ_SEC_NXT_PTR_WIDTH 12 -#define PCRF_DZ_SEC_VERSION_LBN 16 -#define PCRF_DZ_SEC_VERSION_WIDTH 4 -#define PCRF_DZ_SEC_EXT_CAP_ID_LBN 0 -#define PCRF_DZ_SEC_EXT_CAP_ID_WIDTH 16 +#define PCRF_DZ_LTR_NXT_PTR_LBN 20 +#define PCRF_DZ_LTR_NXT_PTR_WIDTH 12 +#define PCRF_DZ_LTR_VERSION_LBN 16 +#define PCRF_DZ_LTR_VERSION_WIDTH 4 +#define PCRF_DZ_LTR_EXT_CAP_ID_LBN 0 +#define PCRF_DZ_LTR_EXT_CAP_ID_WIDTH 16 /* - * PC_LINK_CONTROL3_REG(32bit): - * Link Control 3. + * PC_LTR_MAX_SNOOP_REG(32bit): + * LTR Maximum Snoop/No Snoop Register */ -#define PCR_DZ_LINK_CONTROL3_REG 0x00000304 +#define PCR_DZ_LTR_MAX_SNOOP_REG 0x00000294 /* hunta0=pci_f0_config */ -#define PCRF_DZ_LINK_EQ_INT_EN_LBN 1 -#define PCRF_DZ_LINK_EQ_INT_EN_WIDTH 1 -#define PCRF_DZ_PERFORM_EQL_LBN 0 -#define PCRF_DZ_PERFORM_EQL_WIDTH 1 +#define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_LBN 26 +#define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_WIDTH 3 +#define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_LBN 16 +#define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_WIDTH 10 +#define PCRF_DZ_LTR_MAX_SNOOP_SCALE_LBN 10 +#define PCRF_DZ_LTR_MAX_SNOOP_SCALE_WIDTH 3 +#define PCRF_DZ_LTR_MAX_SNOOP_LAT_LBN 0 +#define PCRF_DZ_LTR_MAX_SNOOP_LAT_WIDTH 10 /* - * PC_LANE_ERROR_STAT_REG(32bit): - * Lane Error Status Register. - */ - -#define PCR_DZ_LANE_ERROR_STAT_REG 0x00000308 -/* hunta0=pci_f0_config */ - -#define PCRF_DZ_LANE_STATUS_LBN 0 -#define PCRF_DZ_LANE_STATUS_WIDTH 8 - - -/* - * PC_LANE01_EQU_CONTROL_REG(32bit): - * Lanes 0,1 Equalization Control Register. - */ - -#define PCR_DZ_LANE01_EQU_CONTROL_REG 0x0000030c -/* hunta0=pci_f0_config */ - -#define PCRF_DZ_LANE1_EQ_CTRL_LBN 16 -#define PCRF_DZ_LANE1_EQ_CTRL_WIDTH 16 -#define PCRF_DZ_LANE0_EQ_CTRL_LBN 0 -#define PCRF_DZ_LANE0_EQ_CTRL_WIDTH 16 - - -/* - * PC_LANE23_EQU_CONTROL_REG(32bit): - * Lanes 2,3 Equalization Control Register. - */ - -#define PCR_DZ_LANE23_EQU_CONTROL_REG 0x00000310 -/* hunta0=pci_f0_config */ - -#define PCRF_DZ_LANE3_EQ_CTRL_LBN 16 -#define PCRF_DZ_LANE3_EQ_CTRL_WIDTH 16 -#define PCRF_DZ_LANE2_EQ_CTRL_LBN 0 -#define PCRF_DZ_LANE2_EQ_CTRL_WIDTH 16 - - -/* - * PC_LANE45_EQU_CONTROL_REG(32bit): - * Lanes 4,5 Equalization Control Register. - */ - -#define PCR_DZ_LANE45_EQU_CONTROL_REG 0x00000314 -/* hunta0=pci_f0_config */ - -#define PCRF_DZ_LANE5_EQ_CTRL_LBN 16 -#define PCRF_DZ_LANE5_EQ_CTRL_WIDTH 16 -#define PCRF_DZ_LANE4_EQ_CTRL_LBN 0 -#define PCRF_DZ_LANE4_EQ_CTRL_WIDTH 16 - - -/* - * PC_LANE67_EQU_CONTROL_REG(32bit): - * Lanes 6,7 Equalization Control Register. - */ - -#define PCR_DZ_LANE67_EQU_CONTROL_REG 0x00000318 -/* hunta0=pci_f0_config */ - -#define PCRF_DZ_LANE7_EQ_CTRL_LBN 16 -#define PCRF_DZ_LANE7_EQ_CTRL_WIDTH 16 -#define PCRF_DZ_LANE6_EQ_CTRL_LBN 0 -#define PCRF_DZ_LANE6_EQ_CTRL_WIDTH 16 - - -/* * PC_ACK_LAT_TMR_REG(32bit): * ACK latency timer & replay timer register */ #define PCR_AC_ACK_LAT_TMR_REG 0x00000700 /* falcona0,falconb0,sienaa0=pci_f0_config */ #define PCRF_AC_RT_LBN 16 #define PCRF_AC_RT_WIDTH 16 #define PCRF_AC_ALT_LBN 0 #define PCRF_AC_ALT_WIDTH 16 /* * PC_OTHER_MSG_REG(32bit): * Other message register */ #define PCR_AC_OTHER_MSG_REG 0x00000704 /* falcona0,falconb0,sienaa0=pci_f0_config */ #define PCRF_AC_OM_CRPT3_LBN 24 #define PCRF_AC_OM_CRPT3_WIDTH 8 #define PCRF_AC_OM_CRPT2_LBN 16 #define PCRF_AC_OM_CRPT2_WIDTH 8 #define PCRF_AC_OM_CRPT1_LBN 8 #define PCRF_AC_OM_CRPT1_WIDTH 8 #define PCRF_AC_OM_CRPT0_LBN 0 #define PCRF_AC_OM_CRPT0_WIDTH 8 /* * PC_FORCE_LNK_REG(24bit): * Port force link register */ #define PCR_AC_FORCE_LNK_REG 0x00000708 /* falcona0,falconb0,sienaa0=pci_f0_config */ #define PCRF_AC_LFS_LBN 16 #define PCRF_AC_LFS_WIDTH 6 #define PCRF_AC_FL_LBN 15 #define PCRF_AC_FL_WIDTH 1 #define PCRF_AC_LN_LBN 0 #define PCRF_AC_LN_WIDTH 8 /* * PC_ACK_FREQ_REG(32bit): * ACK frequency register */ #define PCR_AC_ACK_FREQ_REG 0x0000070c /* falcona0,falconb0,sienaa0=pci_f0_config */ #define PCRF_CC_ALLOW_L1_WITHOUT_L0S_LBN 30 #define PCRF_CC_ALLOW_L1_WITHOUT_L0S_WIDTH 1 #define PCRF_AC_L1_ENTR_LAT_LBN 27 #define PCRF_AC_L1_ENTR_LAT_WIDTH 3 #define PCRF_AC_L0_ENTR_LAT_LBN 24 #define PCRF_AC_L0_ENTR_LAT_WIDTH 3 #define PCRF_CC_COMM_NFTS_LBN 16 #define PCRF_CC_COMM_NFTS_WIDTH 8 #define PCRF_AB_ACK_FREQ_REG_RSVD0_LBN 16 #define PCRF_AB_ACK_FREQ_REG_RSVD0_WIDTH 3 #define PCRF_AC_MAX_FTS_LBN 8 #define PCRF_AC_MAX_FTS_WIDTH 8 #define PCRF_AC_ACK_FREQ_LBN 0 #define PCRF_AC_ACK_FREQ_WIDTH 8 /* * PC_PORT_LNK_CTL_REG(32bit): * Port link control register */ #define PCR_AC_PORT_LNK_CTL_REG 0x00000710 /* falcona0,falconb0,sienaa0=pci_f0_config */ #define PCRF_AB_LRE_LBN 27 #define PCRF_AB_LRE_WIDTH 1 #define PCRF_AB_ESYNC_LBN 26 #define PCRF_AB_ESYNC_WIDTH 1 #define PCRF_AB_CRPT_LBN 25 #define PCRF_AB_CRPT_WIDTH 1 #define PCRF_AB_XB_LBN 24 #define PCRF_AB_XB_WIDTH 1 #define PCRF_AC_LC_LBN 16 #define PCRF_AC_LC_WIDTH 6 #define PCRF_AC_LDR_LBN 8 #define PCRF_AC_LDR_WIDTH 4 #define PCRF_AC_FLM_LBN 7 #define PCRF_AC_FLM_WIDTH 1 #define PCRF_AC_LKD_LBN 6 #define PCRF_AC_LKD_WIDTH 1 #define PCRF_AC_DLE_LBN 5 #define PCRF_AC_DLE_WIDTH 1 #define PCRF_AB_PORT_LNK_CTL_REG_RSVD0_LBN 4 #define PCRF_AB_PORT_LNK_CTL_REG_RSVD0_WIDTH 1 #define PCRF_AC_RA_LBN 3 #define PCRF_AC_RA_WIDTH 1 #define PCRF_AC_LE_LBN 2 #define PCRF_AC_LE_WIDTH 1 #define PCRF_AC_SD_LBN 1 #define PCRF_AC_SD_WIDTH 1 #define PCRF_AC_OMR_LBN 0 #define PCRF_AC_OMR_WIDTH 1 /* * PC_LN_SKEW_REG(32bit): * Lane skew register */ #define PCR_AC_LN_SKEW_REG 0x00000714 /* falcona0,falconb0,sienaa0=pci_f0_config */ #define PCRF_AC_DIS_LBN 31 #define PCRF_AC_DIS_WIDTH 1 #define PCRF_AB_RST_LBN 30 #define PCRF_AB_RST_WIDTH 1 #define PCRF_AC_AD_LBN 25 #define PCRF_AC_AD_WIDTH 1 #define PCRF_AC_FCD_LBN 24 #define PCRF_AC_FCD_WIDTH 1 #define PCRF_AC_LS2_LBN 16 #define PCRF_AC_LS2_WIDTH 8 #define PCRF_AC_LS1_LBN 8 #define PCRF_AC_LS1_WIDTH 8 #define PCRF_AC_LS0_LBN 0 #define PCRF_AC_LS0_WIDTH 8 /* * PC_SYM_NUM_REG(16bit): * Symbol number register */ #define PCR_AC_SYM_NUM_REG 0x00000718 /* falcona0,falconb0,sienaa0=pci_f0_config */ #define PCRF_CC_MAX_FUNCTIONS_LBN 29 #define PCRF_CC_MAX_FUNCTIONS_WIDTH 3 #define PCRF_CC_FC_WATCHDOG_TMR_LBN 24 #define PCRF_CC_FC_WATCHDOG_TMR_WIDTH 5 #define PCRF_CC_ACK_NAK_TMR_MOD_LBN 19 #define PCRF_CC_ACK_NAK_TMR_MOD_WIDTH 5 #define PCRF_CC_REPLAY_TMR_MOD_LBN 14 #define PCRF_CC_REPLAY_TMR_MOD_WIDTH 5 #define PCRF_AB_ES_LBN 12 #define PCRF_AB_ES_WIDTH 3 #define PCRF_AB_SYM_NUM_REG_RSVD0_LBN 11 #define PCRF_AB_SYM_NUM_REG_RSVD0_WIDTH 1 #define PCRF_CC_NUM_SKP_SYMS_LBN 8 #define PCRF_CC_NUM_SKP_SYMS_WIDTH 3 #define PCRF_AB_TS2_LBN 4 #define PCRF_AB_TS2_WIDTH 4 #define PCRF_AC_TS1_LBN 0 #define PCRF_AC_TS1_WIDTH 4 /* * PC_SYM_TMR_FLT_MSK_REG(16bit): * Symbol timer and Filter Mask Register */ #define PCR_CC_SYM_TMR_FLT_MSK_REG 0x0000071c /* sienaa0=pci_f0_config */ #define PCRF_CC_DEFAULT_FLT_MSK1_LBN 16 #define PCRF_CC_DEFAULT_FLT_MSK1_WIDTH 16 #define PCRF_CC_FC_WDOG_TMR_DIS_LBN 15 #define PCRF_CC_FC_WDOG_TMR_DIS_WIDTH 1 #define PCRF_CC_SI1_LBN 8 #define PCRF_CC_SI1_WIDTH 3 #define PCRF_CC_SKIP_INT_VAL_LBN 0 #define PCRF_CC_SKIP_INT_VAL_WIDTH 11 #define PCRF_CC_SI0_LBN 0 #define PCRF_CC_SI0_WIDTH 8 /* * PC_SYM_TMR_REG(16bit): * Symbol timer register */ #define PCR_AB_SYM_TMR_REG 0x0000071c /* falcona0,falconb0=pci_f0_config */ #define PCRF_AB_ET_LBN 11 #define PCRF_AB_ET_WIDTH 4 #define PCRF_AB_SI1_LBN 8 #define PCRF_AB_SI1_WIDTH 3 #define PCRF_AB_SI0_LBN 0 #define PCRF_AB_SI0_WIDTH 8 /* + * PC_FLT_MSK_REG(32bit): + * Filter Mask Register 2 + */ + +#define PCR_CC_FLT_MSK_REG 0x00000720 +/* sienaa0=pci_f0_config */ + +#define PCRF_CC_DEFAULT_FLT_MSK2_LBN 0 +#define PCRF_CC_DEFAULT_FLT_MSK2_WIDTH 32 + + +/* * PC_PHY_STAT_REG(32bit): * PHY status register */ #define PCR_AB_PHY_STAT_REG 0x00000720 /* falcona0,falconb0=pci_f0_config */ #define PCR_CC_PHY_STAT_REG 0x00000810 /* sienaa0=pci_f0_config */ #define PCRF_AC_SSL_LBN 3 #define PCRF_AC_SSL_WIDTH 1 #define PCRF_AC_SSR_LBN 2 #define PCRF_AC_SSR_WIDTH 1 #define PCRF_AC_SSCL_LBN 1 #define PCRF_AC_SSCL_WIDTH 1 #define PCRF_AC_SSCD_LBN 0 #define PCRF_AC_SSCD_WIDTH 1 - - -/* - * PC_FLT_MSK_REG(32bit): - * Filter Mask Register 2 - */ - -#define PCR_CC_FLT_MSK_REG 0x00000720 -/* sienaa0=pci_f0_config */ - -#define PCRF_CC_DEFAULT_FLT_MSK2_LBN 0 -#define PCRF_CC_DEFAULT_FLT_MSK2_WIDTH 32 /* * PC_PHY_CTL_REG(32bit): * PHY control register */ #define PCR_AB_PHY_CTL_REG 0x00000724 /* falcona0,falconb0=pci_f0_config */ #define PCR_CC_PHY_CTL_REG 0x00000814 /* sienaa0=pci_f0_config */ #define PCRF_AC_BD_LBN 31 #define PCRF_AC_BD_WIDTH 1 #define PCRF_AC_CDS_LBN 30 #define PCRF_AC_CDS_WIDTH 1 #define PCRF_AC_DWRAP_LB_LBN 29 #define PCRF_AC_DWRAP_LB_WIDTH 1 #define PCRF_AC_EBD_LBN 28 #define PCRF_AC_EBD_WIDTH 1 #define PCRF_AC_SNR_LBN 27 #define PCRF_AC_SNR_WIDTH 1 #define PCRF_AC_RX_NOT_DET_LBN 2 #define PCRF_AC_RX_NOT_DET_WIDTH 1 #define PCRF_AC_FORCE_LOS_VAL_LBN 1 #define PCRF_AC_FORCE_LOS_VAL_WIDTH 1 #define PCRF_AC_FORCE_LOS_EN_LBN 0 #define PCRF_AC_FORCE_LOS_EN_WIDTH 1 /* * PC_DEBUG0_REG(32bit): * Debug register 0 */ #define PCR_AC_DEBUG0_REG 0x00000728 /* falcona0,falconb0,sienaa0=pci_f0_config */ #define PCRF_AC_CDI03_LBN 24 #define PCRF_AC_CDI03_WIDTH 8 #define PCRF_AC_CDI0_LBN 0 #define PCRF_AC_CDI0_WIDTH 32 #define PCRF_AC_CDI02_LBN 16 #define PCRF_AC_CDI02_WIDTH 8 #define PCRF_AC_CDI01_LBN 8 #define PCRF_AC_CDI01_WIDTH 8 #define PCRF_AC_CDI00_LBN 0 #define PCRF_AC_CDI00_WIDTH 8 /* * PC_DEBUG1_REG(32bit): * Debug register 1 */ #define PCR_AC_DEBUG1_REG 0x0000072c /* falcona0,falconb0,sienaa0=pci_f0_config */ #define PCRF_AC_CDI13_LBN 24 #define PCRF_AC_CDI13_WIDTH 8 #define PCRF_AC_CDI1_LBN 0 #define PCRF_AC_CDI1_WIDTH 32 #define PCRF_AC_CDI12_LBN 16 #define PCRF_AC_CDI12_WIDTH 8 #define PCRF_AC_CDI11_LBN 8 #define PCRF_AC_CDI11_WIDTH 8 #define PCRF_AC_CDI10_LBN 0 #define PCRF_AC_CDI10_WIDTH 8 /* * PC_XPFCC_STAT_REG(24bit): * documentation to be written for sum_PC_XPFCC_STAT_REG */ #define PCR_AC_XPFCC_STAT_REG 0x00000730 /* falcona0,falconb0,sienaa0=pci_f0_config */ #define PCRF_AC_XPDC_LBN 12 #define PCRF_AC_XPDC_WIDTH 8 #define PCRF_AC_XPHC_LBN 0 #define PCRF_AC_XPHC_WIDTH 12 /* * PC_XNPFCC_STAT_REG(24bit): * documentation to be written for sum_PC_XNPFCC_STAT_REG */ #define PCR_AC_XNPFCC_STAT_REG 0x00000734 /* falcona0,falconb0,sienaa0=pci_f0_config */ #define PCRF_AC_XNPDC_LBN 12 #define PCRF_AC_XNPDC_WIDTH 8 #define PCRF_AC_XNPHC_LBN 0 #define PCRF_AC_XNPHC_WIDTH 12 /* * PC_XCFCC_STAT_REG(24bit): * documentation to be written for sum_PC_XCFCC_STAT_REG */ #define PCR_AC_XCFCC_STAT_REG 0x00000738 /* falcona0,falconb0,sienaa0=pci_f0_config */ #define PCRF_AC_XCDC_LBN 12 #define PCRF_AC_XCDC_WIDTH 8 #define PCRF_AC_XCHC_LBN 0 #define PCRF_AC_XCHC_WIDTH 12 /* * PC_Q_STAT_REG(8bit): * documentation to be written for sum_PC_Q_STAT_REG */ #define PCR_AC_Q_STAT_REG 0x0000073c /* falcona0,falconb0,sienaa0=pci_f0_config */ #define PCRF_AC_RQNE_LBN 2 #define PCRF_AC_RQNE_WIDTH 1 #define PCRF_AC_XRNE_LBN 1 #define PCRF_AC_XRNE_WIDTH 1 #define PCRF_AC_RCNR_LBN 0 #define PCRF_AC_RCNR_WIDTH 1 /* * PC_VC_XMIT_ARB1_REG(32bit): * VC Transmit Arbitration Register 1 */ #define PCR_CC_VC_XMIT_ARB1_REG 0x00000740 /* sienaa0=pci_f0_config */ /* * PC_VC_XMIT_ARB2_REG(32bit): * VC Transmit Arbitration Register 2 */ #define PCR_CC_VC_XMIT_ARB2_REG 0x00000744 /* sienaa0=pci_f0_config */ /* * PC_VC0_P_RQ_CTL_REG(32bit): * VC0 Posted Receive Queue Control */ #define PCR_CC_VC0_P_RQ_CTL_REG 0x00000748 /* sienaa0=pci_f0_config */ /* * PC_VC0_NP_RQ_CTL_REG(32bit): * VC0 Non-Posted Receive Queue Control */ #define PCR_CC_VC0_NP_RQ_CTL_REG 0x0000074c /* sienaa0=pci_f0_config */ /* * PC_VC0_C_RQ_CTL_REG(32bit): * VC0 Completion Receive Queue Control */ #define PCR_CC_VC0_C_RQ_CTL_REG 0x00000750 /* sienaa0=pci_f0_config */ /* * PC_GEN2_REG(32bit): * Gen2 Register */ #define PCR_CC_GEN2_REG 0x0000080c /* sienaa0=pci_f0_config */ #define PCRF_CC_SET_DE_EMPHASIS_LBN 20 #define PCRF_CC_SET_DE_EMPHASIS_WIDTH 1 #define PCRF_CC_CFG_TX_COMPLIANCE_LBN 19 #define PCRF_CC_CFG_TX_COMPLIANCE_WIDTH 1 #define PCRF_CC_CFG_TX_SWING_LBN 18 #define PCRF_CC_CFG_TX_SWING_WIDTH 1 #define PCRF_CC_DIR_SPEED_CHANGE_LBN 17 #define PCRF_CC_DIR_SPEED_CHANGE_WIDTH 1 #define PCRF_CC_LANE_ENABLE_LBN 8 #define PCRF_CC_LANE_ENABLE_WIDTH 9 #define PCRF_CC_NUM_FTS_LBN 0 #define PCRF_CC_NUM_FTS_WIDTH 8 #ifdef __cplusplus } #endif #endif /* _SYS_EFX_REGS_PCI_H */ Property changes on: head/sys/dev/sfxge/common/efx_regs_pci.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_rx.c =================================================================== --- head/sys/dev/sfxge/common/efx_rx.c (revision 283513) +++ head/sys/dev/sfxge/common/efx_rx.c (revision 283514) @@ -1,820 +1,1369 @@ /*- - * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2007-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include "efsys.h" #include "efx.h" #include "efx_types.h" #include "efx_regs.h" #include "efx_impl.h" + +#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA + +static __checkReturn int +falconsiena_rx_init( + __in efx_nic_t *enp); + +static void +falconsiena_rx_fini( + __in efx_nic_t *enp); + +#if EFSYS_OPT_RX_HDR_SPLIT +static __checkReturn int +falconsiena_rx_hdr_split_enable( + __in efx_nic_t *enp, + __in unsigned int hdr_buf_size, + __in unsigned int pld_buf_size); +#endif /* EFSYS_OPT_RX_HDR_SPLIT */ + +#if EFSYS_OPT_RX_SCATTER +static __checkReturn int +falconsiena_rx_scatter_enable( + __in efx_nic_t *enp, + __in unsigned int buf_size); +#endif /* EFSYS_OPT_RX_SCATTER */ + +#if EFSYS_OPT_RX_SCALE +static __checkReturn int +falconsiena_rx_scale_mode_set( + __in efx_nic_t *enp, + __in efx_rx_hash_alg_t alg, + __in efx_rx_hash_type_t type, + __in boolean_t insert); + +static __checkReturn int +falconsiena_rx_scale_key_set( + __in efx_nic_t *enp, + __in_ecount(n) uint8_t *key, + __in size_t n); + +static __checkReturn int +falconsiena_rx_scale_tbl_set( + __in efx_nic_t *enp, + __in_ecount(n) unsigned int *table, + __in size_t n); + +#endif /* EFSYS_OPT_RX_SCALE */ + +static void +falconsiena_rx_qpost( + __in efx_rxq_t *erp, + __in_ecount(n) efsys_dma_addr_t *addrp, + __in size_t size, + __in unsigned int n, + __in unsigned int completed, + __in unsigned int added); + +static void +falconsiena_rx_qpush( + __in efx_rxq_t *erp, + __in unsigned int added, + __inout unsigned int *pushedp); + +static __checkReturn int +falconsiena_rx_qflush( + __in efx_rxq_t *erp); + +static void +falconsiena_rx_qenable( + __in efx_rxq_t *erp); + +static __checkReturn int +falconsiena_rx_qcreate( + __in efx_nic_t *enp, + __in unsigned int index, + __in unsigned int label, + __in efx_rxq_type_t type, + __in efsys_mem_t *esmp, + __in size_t n, + __in uint32_t id, + __in efx_evq_t *eep, + __in efx_rxq_t *erp); + +static void +falconsiena_rx_qdestroy( + __in efx_rxq_t *erp); + +#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ + + +#if EFSYS_OPT_FALCON +static efx_rx_ops_t __efx_rx_falcon_ops = { + falconsiena_rx_init, /* erxo_init */ + falconsiena_rx_fini, /* erxo_fini */ +#if EFSYS_OPT_RX_HDR_SPLIT + falconsiena_rx_hdr_split_enable, /* erxo_hdr_split_enable */ +#endif +#if EFSYS_OPT_RX_SCATTER + falconsiena_rx_scatter_enable, /* erxo_scatter_enable */ +#endif +#if EFSYS_OPT_RX_SCALE + falconsiena_rx_scale_mode_set, /* erxo_scale_mode_set */ + falconsiena_rx_scale_key_set, /* erxo_scale_key_set */ + falconsiena_rx_scale_tbl_set, /* erxo_scale_tbl_set */ +#endif + falconsiena_rx_qpost, /* erxo_qpost */ + falconsiena_rx_qpush, /* erxo_qpush */ + falconsiena_rx_qflush, /* erxo_qflush */ + falconsiena_rx_qenable, /* erxo_qenable */ + falconsiena_rx_qcreate, /* erxo_qcreate */ + falconsiena_rx_qdestroy, /* erxo_qdestroy */ +}; +#endif /* EFSYS_OPT_FALCON */ + +#if EFSYS_OPT_SIENA +static efx_rx_ops_t __efx_rx_siena_ops = { + falconsiena_rx_init, /* erxo_init */ + falconsiena_rx_fini, /* erxo_fini */ +#if EFSYS_OPT_RX_HDR_SPLIT + falconsiena_rx_hdr_split_enable, /* erxo_hdr_split_enable */ +#endif +#if EFSYS_OPT_RX_SCATTER + falconsiena_rx_scatter_enable, /* erxo_scatter_enable */ +#endif +#if EFSYS_OPT_RX_SCALE + falconsiena_rx_scale_mode_set, /* erxo_scale_mode_set */ + falconsiena_rx_scale_key_set, /* erxo_scale_key_set */ + falconsiena_rx_scale_tbl_set, /* erxo_scale_tbl_set */ +#endif + falconsiena_rx_qpost, /* erxo_qpost */ + falconsiena_rx_qpush, /* erxo_qpush */ + falconsiena_rx_qflush, /* erxo_qflush */ + falconsiena_rx_qenable, /* erxo_qenable */ + falconsiena_rx_qcreate, /* erxo_qcreate */ + falconsiena_rx_qdestroy, /* erxo_qdestroy */ +}; +#endif /* EFSYS_OPT_SIENA */ + +#if EFSYS_OPT_HUNTINGTON +static efx_rx_ops_t __efx_rx_hunt_ops = { + hunt_rx_init, /* erxo_init */ + hunt_rx_fini, /* erxo_fini */ +#if EFSYS_OPT_RX_HDR_SPLIT + hunt_rx_hdr_split_enable, /* erxo_hdr_split_enable */ +#endif +#if EFSYS_OPT_RX_SCATTER + hunt_rx_scatter_enable, /* erxo_scatter_enable */ +#endif +#if EFSYS_OPT_RX_SCALE + hunt_rx_scale_mode_set, /* erxo_scale_mode_set */ + hunt_rx_scale_key_set, /* erxo_scale_key_set */ + hunt_rx_scale_tbl_set, /* erxo_scale_tbl_set */ +#endif + hunt_rx_qpost, /* erxo_qpost */ + hunt_rx_qpush, /* erxo_qpush */ + hunt_rx_qflush, /* erxo_qflush */ + hunt_rx_qenable, /* erxo_qenable */ + hunt_rx_qcreate, /* erxo_qcreate */ + hunt_rx_qdestroy, /* erxo_qdestroy */ +}; +#endif /* EFSYS_OPT_HUNTINGTON */ + + __checkReturn int efx_rx_init( - __in efx_nic_t *enp) + __inout efx_nic_t *enp) { - efx_oword_t oword; - unsigned int index; + efx_rx_ops_t *erxop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); if (!(enp->en_mod_flags & EFX_MOD_EV)) { rc = EINVAL; goto fail1; } if (enp->en_mod_flags & EFX_MOD_RX) { rc = EINVAL; goto fail2; } + switch (enp->en_family) { +#if EFSYS_OPT_FALCON + case EFX_FAMILY_FALCON: + erxop = (efx_rx_ops_t *)&__efx_rx_falcon_ops; + break; +#endif /* EFSYS_OPT_FALCON */ + +#if EFSYS_OPT_SIENA + case EFX_FAMILY_SIENA: + erxop = (efx_rx_ops_t *)&__efx_rx_siena_ops; + break; +#endif /* EFSYS_OPT_SIENA */ + +#if EFSYS_OPT_HUNTINGTON + case EFX_FAMILY_HUNTINGTON: + erxop = (efx_rx_ops_t *)&__efx_rx_hunt_ops; + break; +#endif /* EFSYS_OPT_HUNTINGTON */ + + default: + EFSYS_ASSERT(0); + rc = ENOTSUP; + goto fail3; + } + + if ((rc = erxop->erxo_init(enp)) != 0) + goto fail4; + + enp->en_erxop = erxop; + enp->en_mod_flags |= EFX_MOD_RX; + return (0); + +fail4: + EFSYS_PROBE(fail4); +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + enp->en_erxop = NULL; + enp->en_mod_flags &= ~EFX_MOD_RX; + return (rc); +} + + void +efx_rx_fini( + __in efx_nic_t *enp) +{ + efx_rx_ops_t *erxop = enp->en_erxop; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); + EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0); + + erxop->erxo_fini(enp); + + enp->en_erxop = NULL; + enp->en_mod_flags &= ~EFX_MOD_RX; +} + +#if EFSYS_OPT_RX_HDR_SPLIT + __checkReturn int +efx_rx_hdr_split_enable( + __in efx_nic_t *enp, + __in unsigned int hdr_buf_size, + __in unsigned int pld_buf_size) +{ + efx_rx_ops_t *erxop = enp->en_erxop; + int rc; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); + EFSYS_ASSERT3U(enp->en_family, >=, EFX_FAMILY_SIENA); + + if ((rc = erxop->erxo_hdr_split_enable(enp, hdr_buf_size, + pld_buf_size)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + return (rc); +} +#endif /* EFSYS_OPT_RX_HDR_SPLIT */ + +#if EFSYS_OPT_RX_SCATTER + __checkReturn int +efx_rx_scatter_enable( + __in efx_nic_t *enp, + __in unsigned int buf_size) +{ + efx_rx_ops_t *erxop = enp->en_erxop; + int rc; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); + + if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + return (rc); +} +#endif /* EFSYS_OPT_RX_SCATTER */ + +#if EFSYS_OPT_RX_SCALE + __checkReturn int +efx_rx_hash_support_get( + __in efx_nic_t *enp, + __out efx_rx_hash_support_t *supportp) +{ + int rc; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); + + if (supportp == NULL) { + rc = EINVAL; + goto fail1; + } + + /* Report if resources are available to insert RX hash value */ + *supportp = enp->en_hash_support; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +efx_rx_scale_support_get( + __in efx_nic_t *enp, + __out efx_rx_scale_support_t *supportp) +{ + int rc; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); + + if (supportp == NULL) { + rc = EINVAL; + goto fail1; + } + + /* Report if resources are available to support RSS */ + *supportp = enp->en_rss_support; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +efx_rx_scale_mode_set( + __in efx_nic_t *enp, + __in efx_rx_hash_alg_t alg, + __in efx_rx_hash_type_t type, + __in boolean_t insert) +{ + efx_rx_ops_t *erxop = enp->en_erxop; + int rc; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); + + if (erxop->erxo_scale_mode_set != NULL) { + if ((rc = erxop->erxo_scale_mode_set(enp, alg, + type, insert)) != 0) + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + return (rc); +} +#endif /* EFSYS_OPT_RX_SCALE */ + +#if EFSYS_OPT_RX_SCALE + __checkReturn int +efx_rx_scale_key_set( + __in efx_nic_t *enp, + __in_ecount(n) uint8_t *key, + __in size_t n) +{ + efx_rx_ops_t *erxop = enp->en_erxop; + int rc; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); + + if ((rc = erxop->erxo_scale_key_set(enp, key, n)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} +#endif /* EFSYS_OPT_RX_SCALE */ + +#if EFSYS_OPT_RX_SCALE + __checkReturn int +efx_rx_scale_tbl_set( + __in efx_nic_t *enp, + __in_ecount(n) unsigned int *table, + __in size_t n) +{ + efx_rx_ops_t *erxop = enp->en_erxop; + int rc; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); + + if ((rc = erxop->erxo_scale_tbl_set(enp, table, n)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} +#endif /* EFSYS_OPT_RX_SCALE */ + + void +efx_rx_qpost( + __in efx_rxq_t *erp, + __in_ecount(n) efsys_dma_addr_t *addrp, + __in size_t size, + __in unsigned int n, + __in unsigned int completed, + __in unsigned int added) +{ + efx_nic_t *enp = erp->er_enp; + efx_rx_ops_t *erxop = enp->en_erxop; + + EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); + + erxop->erxo_qpost(erp, addrp, size, n, completed, added); +} + + void +efx_rx_qpush( + __in efx_rxq_t *erp, + __in unsigned int added, + __inout unsigned int *pushedp) +{ + efx_nic_t *enp = erp->er_enp; + efx_rx_ops_t *erxop = enp->en_erxop; + + EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); + + erxop->erxo_qpush(erp, added, pushedp); +} + + __checkReturn int +efx_rx_qflush( + __in efx_rxq_t *erp) +{ + efx_nic_t *enp = erp->er_enp; + efx_rx_ops_t *erxop = enp->en_erxop; + int rc; + + EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); + + if ((rc = erxop->erxo_qflush(erp)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + void +efx_rx_qenable( + __in efx_rxq_t *erp) +{ + efx_nic_t *enp = erp->er_enp; + efx_rx_ops_t *erxop = enp->en_erxop; + + EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); + + erxop->erxo_qenable(erp); +} + + __checkReturn int +efx_rx_qcreate( + __in efx_nic_t *enp, + __in unsigned int index, + __in unsigned int label, + __in efx_rxq_type_t type, + __in efsys_mem_t *esmp, + __in size_t n, + __in uint32_t id, + __in efx_evq_t *eep, + __deref_out efx_rxq_t **erpp) +{ + efx_rx_ops_t *erxop = enp->en_erxop; + efx_rxq_t *erp; + int rc; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); + + /* Allocate an RXQ object */ + EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp); + + if (erp == NULL) { + rc = ENOMEM; + goto fail1; + } + + erp->er_magic = EFX_RXQ_MAGIC; + erp->er_enp = enp; + erp->er_index = index; + erp->er_mask = n - 1; + erp->er_esmp = esmp; + + if ((rc = erxop->erxo_qcreate(enp, index, label, type, esmp, n, id, + eep, erp)) != 0) + goto fail2; + + enp->en_rx_qcount++; + *erpp = erp; + + return (0); + +fail2: + EFSYS_PROBE(fail2); + + EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + void +efx_rx_qdestroy( + __in efx_rxq_t *erp) +{ + efx_nic_t *enp = erp->er_enp; + efx_rx_ops_t *erxop = enp->en_erxop; + + EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); + + erxop->erxo_qdestroy(erp); +} + +/* + * Psuedo-header info for Siena/Falcon. + * + * The psuedo-header is a byte array of one of the forms: + * + * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + * XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.TT.TT.TT.TT + * XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.LL.LL + * + * where: + * + * TT.TT.TT.TT is a 32-bit Toeplitz hash + * LL.LL is a 16-bit LFSR hash + * + * Hash values are in network (big-endian) byte order. + * + * + * On Huntington the pseudo-header is laid out as: + * (See also SF-109306-TC section 9) + * + * Toeplitz hash (32 bits, little-endian) + * Out-of-band outer VLAN tag + * (16 bits, big-endian, 0 if the packet did not have an outer VLAN tag) + * Out-of-band inner VLAN tag + * (16 bits, big-endian, 0 if the packet did not have an inner VLAN tag) + * Packet length (16 bits, little-endian, may be 0) + * MAC timestamp (32 bits, little-endian, may be 0) + * VLAN tag + * (16 bits, big-endian, 0 if the packet did not have an outer VLAN tag) + * VLAN tag + * (16 bits, big-endian, 0 if the packet did not have an inner VLAN tag) + */ + + __checkReturn int +efx_psuedo_hdr_pkt_length_get( + __in efx_nic_t *enp, + __in uint8_t *buffer, + __out uint16_t *pkt_lengthp) +{ + if (enp->en_family != EFX_FAMILY_HUNTINGTON) { + EFSYS_ASSERT(0); + return (ENOTSUP); + } + + *pkt_lengthp = buffer[8] | (buffer[9] << 8); + + return (0); +} + +#if EFSYS_OPT_RX_SCALE + +uint32_t +efx_psuedo_hdr_hash_get( + __in efx_nic_t *enp, + __in efx_rx_hash_alg_t func, + __in uint8_t *buffer) +{ + if (func == EFX_RX_HASHALG_TOEPLITZ) { + switch (enp->en_family) { + case EFX_FAMILY_FALCON: + case EFX_FAMILY_SIENA: + return ((buffer[12] << 24) | + (buffer[13] << 16) | + (buffer[14] << 8) | + buffer[15]); + case EFX_FAMILY_HUNTINGTON: + return (buffer[0] | + (buffer[1] << 8) | + (buffer[2] << 16) | + (buffer[3] << 24)); + default: + EFSYS_ASSERT(0); + return (0); + } + } else if (func == EFX_RX_HASHALG_LFSR) { + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_FALCON || + enp->en_family == EFX_FAMILY_SIENA); + return ((buffer[14] << 8) | buffer[15]); + } else { + EFSYS_ASSERT(0); + return (0); + } +} + +#endif /* EFSYS_OPT_RX_SCALE */ + +#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA + +static __checkReturn int +falconsiena_rx_init( + __in efx_nic_t *enp) +{ + efx_oword_t oword; + unsigned int index; + EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword); EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0); EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0); EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32); EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword); /* Zero the RSS table */ for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) { EFX_ZERO_OWORD(oword); EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL, - index, &oword); + index, &oword, B_TRUE); } - enp->en_mod_flags |= EFX_MOD_RX; - return (0); +#if EFSYS_OPT_RX_SCALE + /* The RSS key and indirection table are writable. */ + enp->en_rss_support = EFX_RX_SCALE_EXCLUSIVE; -fail2: - EFSYS_PROBE(fail2); -fail1: - EFSYS_PROBE1(fail1, int, rc); + /* Hardware can insert RX hash with/without RSS */ + enp->en_hash_support = EFX_RX_HASH_AVAILABLE; +#endif /* EFSYS_OPT_RX_SCALE */ - return (rc); + return (0); } #if EFSYS_OPT_RX_HDR_SPLIT - __checkReturn int -efx_rx_hdr_split_enable( +static __checkReturn int +falconsiena_rx_hdr_split_enable( __in efx_nic_t *enp, __in unsigned int hdr_buf_size, __in unsigned int pld_buf_size) { unsigned int nhdr32; unsigned int npld32; efx_oword_t oword; int rc; - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); - EFSYS_ASSERT3U(enp->en_family, >=, EFX_FAMILY_SIENA); - nhdr32 = hdr_buf_size / 32; if ((nhdr32 == 0) || (nhdr32 >= (1 << FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_WIDTH)) || ((hdr_buf_size % 32) != 0)) { rc = EINVAL; goto fail1; } npld32 = pld_buf_size / 32; if ((npld32 == 0) || (npld32 >= (1 << FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_WIDTH)) || ((pld_buf_size % 32) != 0)) { rc = EINVAL; goto fail2; } if (enp->en_rx_qcount > 0) { rc = EBUSY; goto fail3; } EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword); EFX_SET_OWORD_FIELD(oword, FRF_CZ_RX_HDR_SPLIT_EN, 1); EFX_SET_OWORD_FIELD(oword, FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE, nhdr32); EFX_SET_OWORD_FIELD(oword, FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE, npld32); EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword); return (0); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } #endif /* EFSYS_OPT_RX_HDR_SPLIT */ - #if EFSYS_OPT_RX_SCATTER - __checkReturn int -efx_rx_scatter_enable( +static __checkReturn int +falconsiena_rx_scatter_enable( __in efx_nic_t *enp, __in unsigned int buf_size) { unsigned int nbuf32; efx_oword_t oword; int rc; - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); - EFSYS_ASSERT3U(enp->en_family, >=, EFX_FAMILY_FALCON); - nbuf32 = buf_size / 32; if ((nbuf32 == 0) || (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) || ((buf_size % 32) != 0)) { rc = EINVAL; goto fail1; } if (enp->en_rx_qcount > 0) { rc = EBUSY; goto fail2; } /* Set scatter buffer size */ EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword); EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32); EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword); /* Enable scatter for packets not matching a filter */ EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword); EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1); EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword); return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } #endif /* EFSYS_OPT_RX_SCATTER */ #define EFX_RX_LFSR_HASH(_enp, _insert) \ - do { \ + do { \ efx_oword_t oword; \ \ EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \ EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \ EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \ EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \ EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \ (_insert) ? 1 : 0); \ EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \ \ if ((_enp)->en_family == EFX_FAMILY_SIENA) { \ EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \ &oword); \ EFX_SET_OWORD_FIELD(oword, \ FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \ EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \ &oword); \ } \ \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \ - do { \ + do { \ efx_oword_t oword; \ \ EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \ EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \ EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \ (_ip) ? 1 : 0); \ EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \ (_tcp) ? 0 : 1); \ EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \ (_insert) ? 1 : 0); \ EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \ \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \ - do { \ + do { \ efx_oword_t oword; \ \ if ((_enp)->en_family == EFX_FAMILY_FALCON) { \ (_rc) = ((_ip) || (_tcp)) ? ENOTSUP : 0; \ break; \ } \ \ EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \ EFX_SET_OWORD_FIELD(oword, \ FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \ EFX_SET_OWORD_FIELD(oword, \ FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \ EFX_SET_OWORD_FIELD(oword, \ FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \ EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \ \ (_rc) = 0; \ \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #if EFSYS_OPT_RX_SCALE - __checkReturn int -efx_rx_scale_mode_set( + +static __checkReturn int +falconsiena_rx_scale_mode_set( __in efx_nic_t *enp, __in efx_rx_hash_alg_t alg, __in efx_rx_hash_type_t type, __in boolean_t insert) { int rc; - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); - EFSYS_ASSERT3U(enp->en_family, >=, EFX_FAMILY_FALCON); - switch (alg) { case EFX_RX_HASHALG_LFSR: EFX_RX_LFSR_HASH(enp, insert); break; case EFX_RX_HASHALG_TOEPLITZ: EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert, type & (1 << EFX_RX_HASH_IPV4), type & (1 << EFX_RX_HASH_TCPIPV4)); EFX_RX_TOEPLITZ_IPV6_HASH(enp, type & (1 << EFX_RX_HASH_IPV6), type & (1 << EFX_RX_HASH_TCPIPV6), rc); if (rc != 0) goto fail1; break; default: rc = EINVAL; goto fail2; } return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); EFX_RX_LFSR_HASH(enp, B_FALSE); return (rc); } #endif #if EFSYS_OPT_RX_SCALE - __checkReturn int -efx_rx_scale_toeplitz_ipv4_key_set( +static __checkReturn int +falconsiena_rx_scale_key_set( __in efx_nic_t *enp, __in_ecount(n) uint8_t *key, __in size_t n) { efx_oword_t oword; unsigned int byte; unsigned int offset; int rc; - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); - byte = 0; - /* Write toeplitz hash key */ + /* Write Toeplitz IPv4 hash key */ EFX_ZERO_OWORD(oword); for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8; offset > 0 && byte < n; --offset) oword.eo_u8[offset - 1] = key[byte++]; EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword); byte = 0; - /* Verify toeplitz hash key */ + /* Verify Toeplitz IPv4 hash key */ EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword); for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8; offset > 0 && byte < n; --offset) { if (oword.eo_u8[offset - 1] != key[byte++]) { rc = EFAULT; goto fail1; } } - return (0); + if ((enp->en_features & EFX_FEATURE_IPV6) == 0) + goto done; -fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_ASSERT3U(enp->en_family, !=, EFX_FAMILY_FALCON); - return (rc); -} -#endif - -#if EFSYS_OPT_RX_SCALE - __checkReturn int -efx_rx_scale_toeplitz_ipv6_key_set( - __in efx_nic_t *enp, - __in_ecount(n) uint8_t *key, - __in size_t n) -{ - efx_oword_t oword; - unsigned int byte; - int offset; - int rc; - - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); - byte = 0; - /* Write toeplitz hash key 3 */ + /* Write Toeplitz IPv6 hash key 3 */ EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword); for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8; offset > 0 && byte < n; --offset) oword.eo_u8[offset - 1] = key[byte++]; EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword); - /* Write toeplitz hash key 2 */ + /* Write Toeplitz IPv6 hash key 2 */ EFX_ZERO_OWORD(oword); for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN + FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8; offset > 0 && byte < n; --offset) oword.eo_u8[offset - 1] = key[byte++]; EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword); - /* Write toeplitz hash key 1 */ + /* Write Toeplitz IPv6 hash key 1 */ EFX_ZERO_OWORD(oword); for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN + FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8; offset > 0 && byte < n; --offset) oword.eo_u8[offset - 1] = key[byte++]; EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword); byte = 0; - /* Verify toeplitz hash key 3 */ + /* Verify Toeplitz IPv6 hash key 3 */ EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword); for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8; offset > 0 && byte < n; --offset) { if (oword.eo_u8[offset - 1] != key[byte++]) { rc = EFAULT; - goto fail1; + goto fail2; } } - /* Verify toeplitz hash key 2 */ + /* Verify Toeplitz IPv6 hash key 2 */ EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword); for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN + FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8; offset > 0 && byte < n; --offset) { if (oword.eo_u8[offset - 1] != key[byte++]) { rc = EFAULT; - goto fail2; + goto fail3; } } - /* Verify toeplitz hash key 1 */ + /* Verify Toeplitz IPv6 hash key 1 */ EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword); for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN + FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8; offset > 0 && byte < n; --offset) { if (oword.eo_u8[offset - 1] != key[byte++]) { rc = EFAULT; - goto fail3; + goto fail4; } } +done: return (0); +fail4: + EFSYS_PROBE(fail4); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } #endif #if EFSYS_OPT_RX_SCALE - __checkReturn int -efx_rx_scale_tbl_set( +static __checkReturn int +falconsiena_rx_scale_tbl_set( __in efx_nic_t *enp, __in_ecount(n) unsigned int *table, __in size_t n) { efx_oword_t oword; int index; int rc; - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); - EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS); EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH)); if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) { rc = EINVAL; goto fail1; } for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) { uint32_t byte; /* Calculate the entry to place in the table */ - byte = (uint32_t)table[index % n]; + byte = (n > 0) ? (uint32_t)table[index % n] : 0; EFSYS_PROBE2(table, int, index, uint32_t, byte); EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte); /* Write the table */ EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL, - index, &oword); + index, &oword, B_TRUE); } for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) { uint32_t byte; /* Determine if we're starting a new batch */ - byte = (uint32_t)table[index % n]; + byte = (n > 0) ? (uint32_t)table[index % n] : 0; /* Read the table */ EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL, - index, &oword); + index, &oword, B_TRUE); /* Verify the entry */ if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) { rc = EFAULT; goto fail2; } } return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } #endif -#if EFSYS_OPT_FILTER -extern __checkReturn int -efx_rx_filter_insert( +static void +falconsiena_rx_qpost( __in efx_rxq_t *erp, - __inout efx_filter_spec_t *spec) -{ - EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); - EFSYS_ASSERT3P(spec, !=, NULL); - - spec->efs_dmaq_id = (uint16_t)erp->er_index; - return (efx_filter_insert_filter(erp->er_enp, spec, B_FALSE)); -} -#endif - -#if EFSYS_OPT_FILTER -extern __checkReturn int -efx_rx_filter_remove( - __in efx_rxq_t *erp, - __inout efx_filter_spec_t *spec) -{ - EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); - EFSYS_ASSERT3P(spec, !=, NULL); - - spec->efs_dmaq_id = (uint16_t)erp->er_index; - return (efx_filter_remove_filter(erp->er_enp, spec)); -} -#endif - -extern void -efx_rx_qpost( - __in efx_rxq_t *erp, __in_ecount(n) efsys_dma_addr_t *addrp, __in size_t size, __in unsigned int n, __in unsigned int completed, __in unsigned int added) { efx_qword_t qword; unsigned int i; unsigned int offset; unsigned int id; - EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); - /* The client driver must not overfill the queue */ EFSYS_ASSERT3U(added - completed + n, <=, EFX_RXQ_LIMIT(erp->er_mask + 1)); id = added & (erp->er_mask); for (i = 0; i < n; i++) { EFSYS_PROBE4(rx_post, unsigned int, erp->er_index, unsigned int, id, efsys_dma_addr_t, addrp[i], size_t, size); EFX_POPULATE_QWORD_3(qword, FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size), FSF_AZ_RX_KER_BUF_ADDR_DW0, (uint32_t)(addrp[i] & 0xffffffff), FSF_AZ_RX_KER_BUF_ADDR_DW1, (uint32_t)(addrp[i] >> 32)); offset = id * sizeof (efx_qword_t); EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword); id = (id + 1) & (erp->er_mask); } } - void -efx_rx_qpush( +static void +falconsiena_rx_qpush( __in efx_rxq_t *erp, - __in unsigned int added) + __in unsigned int added, + __inout unsigned int *pushedp) { efx_nic_t *enp = erp->er_enp; + unsigned int pushed = *pushedp; uint32_t wptr; efx_oword_t oword; efx_dword_t dword; - EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); + /* All descriptors are pushed */ + *pushedp = added; - /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */ - EFSYS_PIO_WRITE_BARRIER(); - /* Push the populated descriptors out */ wptr = added & erp->er_mask; EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr); /* Only write the third DWORD */ EFX_POPULATE_DWORD_1(dword, EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3)); + + /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */ + EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1, + wptr, pushed & erp->er_mask); + EFSYS_PIO_WRITE_BARRIER(); EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0, erp->er_index, &dword, B_FALSE); } - void -efx_rx_qflush( +static __checkReturn int +falconsiena_rx_qflush( __in efx_rxq_t *erp) { efx_nic_t *enp = erp->er_enp; efx_oword_t oword; uint32_t label; - EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); - label = erp->er_index; /* Flush the queue */ EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1, FRF_AZ_RX_FLUSH_DESCQ, label); EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword); + + return (0); } - void -efx_rx_qenable( +static void +falconsiena_rx_qenable( __in efx_rxq_t *erp) { efx_nic_t *enp = erp->er_enp; efx_oword_t oword; EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL, - erp->er_index, &oword); + erp->er_index, &oword, B_TRUE); EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0); EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0); EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1); EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL, - erp->er_index, &oword); + erp->er_index, &oword, B_TRUE); } - __checkReturn int -efx_rx_qcreate( +static __checkReturn int +falconsiena_rx_qcreate( __in efx_nic_t *enp, __in unsigned int index, __in unsigned int label, __in efx_rxq_type_t type, __in efsys_mem_t *esmp, __in size_t n, __in uint32_t id, __in efx_evq_t *eep, - __deref_out efx_rxq_t **erpp) + __in efx_rxq_t *erp) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); - efx_rxq_t *erp; efx_oword_t oword; uint32_t size; boolean_t split; boolean_t jumbo; int rc; - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); - EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS == (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH)); EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS); EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit); - if (!ISP2(n) || !(n & EFX_RXQ_NDESCS_MASK)) { + EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS)); + EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS)); + + if (!ISP2(n) || (n < EFX_RXQ_MINNDESCS) || (n > EFX_RXQ_MAXNDESCS)) { rc = EINVAL; goto fail1; } if (index >= encp->enc_rxq_limit) { rc = EINVAL; goto fail2; } for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS); size++) if ((1 << size) == (int)(n / EFX_RXQ_MINNDESCS)) break; if (id + (1 << size) >= encp->enc_buftbl_limit) { rc = EINVAL; goto fail3; } switch (type) { case EFX_RXQ_TYPE_DEFAULT: split = B_FALSE; jumbo = B_FALSE; break; #if EFSYS_OPT_RX_HDR_SPLIT case EFX_RXQ_TYPE_SPLIT_HEADER: if ((enp->en_family < EFX_FAMILY_SIENA) || ((index & 1) != 0)) { rc = EINVAL; goto fail4; } split = B_TRUE; jumbo = B_TRUE; break; case EFX_RXQ_TYPE_SPLIT_PAYLOAD: if ((enp->en_family < EFX_FAMILY_SIENA) || ((index & 1) == 0)) { rc = EINVAL; goto fail4; } split = B_FALSE; jumbo = B_TRUE; break; #endif /* EFSYS_OPT_RX_HDR_SPLIT */ #if EFSYS_OPT_RX_SCATTER case EFX_RXQ_TYPE_SCATTER: if (enp->en_family < EFX_FAMILY_SIENA) { rc = EINVAL; goto fail4; } split = B_FALSE; jumbo = B_TRUE; break; #endif /* EFSYS_OPT_RX_SCATTER */ default: rc = EINVAL; goto fail4; } - /* Allocate an RXQ object */ - EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp); - - if (erp == NULL) { - rc = ENOMEM; - goto fail5; - } - - erp->er_magic = EFX_RXQ_MAGIC; - erp->er_enp = enp; - erp->er_index = index; - erp->er_mask = n - 1; - erp->er_esmp = esmp; - /* Set up the new descriptor queue */ EFX_POPULATE_OWORD_10(oword, FRF_CZ_RX_HDR_SPLIT, split, FRF_AZ_RX_ISCSI_DDIG_EN, 0, FRF_AZ_RX_ISCSI_HDIG_EN, 0, FRF_AZ_RX_DESCQ_BUF_BASE_ID, id, FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index, FRF_AZ_RX_DESCQ_OWNER_ID, 0, FRF_AZ_RX_DESCQ_LABEL, label, FRF_AZ_RX_DESCQ_SIZE, size, FRF_AZ_RX_DESCQ_TYPE, 0, FRF_AZ_RX_DESCQ_JUMBO, jumbo); EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL, - erp->er_index, &oword); + erp->er_index, &oword, B_TRUE); - enp->en_rx_qcount++; - *erpp = erp; return (0); -fail5: - EFSYS_PROBE(fail5); fail4: EFSYS_PROBE(fail4); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } - void -efx_rx_qdestroy( +static void +falconsiena_rx_qdestroy( __in efx_rxq_t *erp) { efx_nic_t *enp = erp->er_enp; efx_oword_t oword; - EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); - EFSYS_ASSERT(enp->en_rx_qcount != 0); --enp->en_rx_qcount; /* Purge descriptor queue */ EFX_ZERO_OWORD(oword); EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL, - erp->er_index, &oword); + erp->er_index, &oword, B_TRUE); /* Free the RXQ object */ EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp); } - void -efx_rx_fini( +static void +falconsiena_rx_fini( __in efx_nic_t *enp) { - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); - EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0); - - enp->en_mod_flags &= ~EFX_MOD_RX; + _NOTE(ARGUNUSED(enp)) } + +#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ Property changes on: head/sys/dev/sfxge/common/efx_rx.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_sram.c =================================================================== --- head/sys/dev/sfxge/common/efx_sram.c (revision 283513) +++ head/sys/dev/sfxge/common/efx_sram.c (revision 283514) @@ -1,297 +1,332 @@ /*- - * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2007-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include "efsys.h" #include "efx.h" #include "efx_types.h" #include "efx_regs.h" #include "efx_impl.h" __checkReturn int efx_sram_buf_tbl_set( __in efx_nic_t *enp, __in uint32_t id, __in efsys_mem_t *esmp, __in size_t n) { efx_qword_t qword; uint32_t start = id; uint32_t stop = start + n; efsys_dma_addr_t addr; efx_oword_t oword; unsigned int count; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); +#if EFSYS_OPT_HUNTINGTON + if (enp->en_family == EFX_FAMILY_HUNTINGTON) { + /* + * FIXME: the efx_sram_buf_tbl_*() functionality needs to be + * pulled inside the Falcon/Siena queue create/destroy code, + * and then the original functions can be removed (see bug30834 + * comment #1). But, for now, we just ensure that they are + * no-ops for Huntington, to allow bringing up existing drivers + * without modification. + */ + + return (0); + } +#endif /* EFSYS_OPT_HUNTINGTON */ + if (stop >= EFX_BUF_TBL_SIZE) { rc = EFBIG; goto fail1; } /* Add the entries into the buffer table */ addr = EFSYS_MEM_ADDR(esmp); for (id = start; id != stop; id++) { EFX_POPULATE_QWORD_5(qword, FRF_AZ_IP_DAT_BUF_SIZE, 0, FRF_AZ_BUF_ADR_REGION, 0, FRF_AZ_BUF_ADR_FBUF_DW0, (uint32_t)((addr >> 12) & 0xffffffff), FRF_AZ_BUF_ADR_FBUF_DW1, (uint32_t)((addr >> 12) >> 32), FRF_AZ_BUF_OWNER_ID_FBUF, 0); EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_FULL_TBL, id, &qword); addr += EFX_BUF_SIZE; } EFSYS_PROBE2(buf, uint32_t, start, uint32_t, stop - 1); /* Flush the write buffer */ EFX_POPULATE_OWORD_2(oword, FRF_AZ_BUF_UPD_CMD, 1, FRF_AZ_BUF_CLR_CMD, 0); EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_UPD_REG, &oword); /* Poll for the last entry being written to the buffer table */ EFSYS_ASSERT3U(id, ==, stop); addr -= EFX_BUF_SIZE; count = 0; do { EFSYS_PROBE1(wait, unsigned int, count); /* Spin for 1 ms */ EFSYS_SPIN(1000); EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_FULL_TBL, id - 1, &qword); if (EFX_QWORD_FIELD(qword, FRF_AZ_BUF_ADR_FBUF_DW0) == (uint32_t)((addr >> 12) & 0xffffffff) && EFX_QWORD_FIELD(qword, FRF_AZ_BUF_ADR_FBUF_DW1) == (uint32_t)((addr >> 12) >> 32)) goto verify; } while (++count < 100); rc = ETIMEDOUT; goto fail2; verify: /* Verify the rest of the entries in the buffer table */ while (--id != start) { addr -= EFX_BUF_SIZE; /* Read the buffer table entry */ EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_FULL_TBL, id - 1, &qword); if (EFX_QWORD_FIELD(qword, FRF_AZ_BUF_ADR_FBUF_DW0) != (uint32_t)((addr >> 12) & 0xffffffff) || EFX_QWORD_FIELD(qword, FRF_AZ_BUF_ADR_FBUF_DW1) != (uint32_t)((addr >> 12) >> 32)) { rc = EFAULT; goto fail3; } } return (0); fail3: EFSYS_PROBE(fail3); id = stop; fail2: EFSYS_PROBE(fail2); EFX_POPULATE_OWORD_4(oword, FRF_AZ_BUF_UPD_CMD, 0, FRF_AZ_BUF_CLR_CMD, 1, FRF_AZ_BUF_CLR_END_ID, id - 1, FRF_AZ_BUF_CLR_START_ID, start); EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_UPD_REG, &oword); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } void efx_sram_buf_tbl_clear( __in efx_nic_t *enp, __in uint32_t id, __in size_t n) { efx_oword_t oword; uint32_t start = id; uint32_t stop = start + n; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); +#if EFSYS_OPT_HUNTINGTON + if (enp->en_family == EFX_FAMILY_HUNTINGTON) { + /* + * FIXME: the efx_sram_buf_tbl_*() functionality needs to be + * pulled inside the Falcon/Siena queue create/destroy code, + * and then the original functions can be removed (see bug30834 + * comment #1). But, for now, we just ensure that they are + * no-ops for Huntington, to allow bringing up existing drivers + * without modification. + */ + + return; + } +#endif /* EFSYS_OPT_HUNTINGTON */ + EFSYS_ASSERT3U(stop, <, EFX_BUF_TBL_SIZE); EFSYS_PROBE2(buf, uint32_t, start, uint32_t, stop - 1); EFX_POPULATE_OWORD_4(oword, FRF_AZ_BUF_UPD_CMD, 0, FRF_AZ_BUF_CLR_CMD, 1, FRF_AZ_BUF_CLR_END_ID, stop - 1, FRF_AZ_BUF_CLR_START_ID, start); EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_UPD_REG, &oword); } #if EFSYS_OPT_DIAG static void efx_sram_byte_increment_set( __in size_t row, __in boolean_t negate, __out efx_qword_t *eqp) { size_t offset = row * FR_AZ_SRM_DBG_REG_STEP; unsigned int index; _NOTE(ARGUNUSED(negate)) for (index = 0; index < sizeof (efx_qword_t); index++) eqp->eq_u8[index] = offset + index; } static void efx_sram_all_the_same_set( __in size_t row, __in boolean_t negate, __out efx_qword_t *eqp) { _NOTE(ARGUNUSED(row)) if (negate) EFX_SET_QWORD(*eqp); else EFX_ZERO_QWORD(*eqp); } static void efx_sram_bit_alternate_set( __in size_t row, __in boolean_t negate, __out efx_qword_t *eqp) { _NOTE(ARGUNUSED(row)) EFX_POPULATE_QWORD_2(*eqp, EFX_DWORD_0, (negate) ? 0x55555555 : 0xaaaaaaaa, EFX_DWORD_1, (negate) ? 0x55555555 : 0xaaaaaaaa); } static void efx_sram_byte_alternate_set( __in size_t row, __in boolean_t negate, __out efx_qword_t *eqp) { _NOTE(ARGUNUSED(row)) EFX_POPULATE_QWORD_2(*eqp, EFX_DWORD_0, (negate) ? 0x00ff00ff : 0xff00ff00, EFX_DWORD_1, (negate) ? 0x00ff00ff : 0xff00ff00); } static void efx_sram_byte_changing_set( __in size_t row, __in boolean_t negate, __out efx_qword_t *eqp) { size_t offset = row * FR_AZ_SRM_DBG_REG_STEP; unsigned int index; for (index = 0; index < sizeof (efx_qword_t); index++) { uint8_t byte; if (offset / 256 == 0) byte = (uint8_t)((offset % 257) % 256); else byte = (uint8_t)(~((offset - 8) % 257) % 256); eqp->eq_u8[index] = (negate) ? ~byte : byte; } } static void efx_sram_bit_sweep_set( __in size_t row, __in boolean_t negate, __out efx_qword_t *eqp) { size_t offset = row * FR_AZ_SRM_DBG_REG_STEP; if (negate) { EFX_SET_QWORD(*eqp); EFX_CLEAR_QWORD_BIT(*eqp, (offset / sizeof (efx_qword_t)) % 64); } else { EFX_ZERO_QWORD(*eqp); EFX_SET_QWORD_BIT(*eqp, (offset / sizeof (efx_qword_t)) % 64); } } -efx_sram_pattern_fn_t __cs __efx_sram_pattern_fns[] = { +efx_sram_pattern_fn_t __efx_sram_pattern_fns[] = { efx_sram_byte_increment_set, efx_sram_all_the_same_set, efx_sram_bit_alternate_set, efx_sram_byte_alternate_set, efx_sram_byte_changing_set, efx_sram_bit_sweep_set }; __checkReturn int efx_sram_test( __in efx_nic_t *enp, __in efx_pattern_type_t type) { efx_nic_ops_t *enop = enp->en_enop; efx_sram_pattern_fn_t func; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX)); EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX)); EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV)); /* Select pattern generator */ EFSYS_ASSERT3U(type, <, EFX_PATTERN_NTYPES); func = __efx_sram_pattern_fns[type]; return (enop->eno_sram_test(enp, func)); } #endif /* EFSYS_OPT_DIAG */ Property changes on: head/sys/dev/sfxge/common/efx_sram.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_tx.c =================================================================== --- head/sys/dev/sfxge/common/efx_tx.c (revision 283513) +++ head/sys/dev/sfxge/common/efx_tx.c (revision 283514) @@ -1,485 +1,1071 @@ /*- - * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2007-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include "efsys.h" #include "efx.h" #include "efx_types.h" #include "efx_regs.h" #include "efx_impl.h" #if EFSYS_OPT_QSTATS #define EFX_TX_QSTAT_INCR(_etp, _stat) \ do { \ (_etp)->et_stat[_stat]++; \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #else #define EFX_TX_QSTAT_INCR(_etp, _stat) #endif +#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA + +static __checkReturn int +falconsiena_tx_init( + __in efx_nic_t *enp); + +static void +falconsiena_tx_fini( + __in efx_nic_t *enp); + +static __checkReturn int +falconsiena_tx_qcreate( + __in efx_nic_t *enp, + __in unsigned int index, + __in unsigned int label, + __in efsys_mem_t *esmp, + __in size_t n, + __in uint32_t id, + __in uint16_t flags, + __in efx_evq_t *eep, + __in efx_txq_t *etp, + __out unsigned int *addedp); + +static void +falconsiena_tx_qdestroy( + __in efx_txq_t *etp); + +static __checkReturn int +falconsiena_tx_qpost( + __in efx_txq_t *etp, + __in_ecount(n) efx_buffer_t *eb, + __in unsigned int n, + __in unsigned int completed, + __inout unsigned int *addedp); + +static void +falconsiena_tx_qpush( + __in efx_txq_t *etp, + __in unsigned int added, + __in unsigned int pushed); + +static __checkReturn int +falconsiena_tx_qpace( + __in efx_txq_t *etp, + __in unsigned int ns); + +static __checkReturn int +falconsiena_tx_qflush( + __in efx_txq_t *etp); + +static void +falconsiena_tx_qenable( + __in efx_txq_t *etp); + __checkReturn int +falconsiena_tx_qdesc_post( + __in efx_txq_t *etp, + __in_ecount(n) efx_desc_t *ed, + __in unsigned int n, + __in unsigned int completed, + __inout unsigned int *addedp); + + void +falconsiena_tx_qdesc_dma_create( + __in efx_txq_t *etp, + __in efsys_dma_addr_t addr, + __in size_t size, + __in boolean_t eop, + __out efx_desc_t *edp); + +#if EFSYS_OPT_QSTATS +static void +falconsiena_tx_qstats_update( + __in efx_txq_t *etp, + __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); +#endif + +#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ + + +#if EFSYS_OPT_FALCON +static efx_tx_ops_t __efx_tx_falcon_ops = { + falconsiena_tx_init, /* etxo_init */ + falconsiena_tx_fini, /* etxo_fini */ + falconsiena_tx_qcreate, /* etxo_qcreate */ + falconsiena_tx_qdestroy, /* etxo_qdestroy */ + falconsiena_tx_qpost, /* etxo_qpost */ + falconsiena_tx_qpush, /* etxo_qpush */ + falconsiena_tx_qpace, /* etxo_qpace */ + falconsiena_tx_qflush, /* etxo_qflush */ + falconsiena_tx_qenable, /* etxo_qenable */ + NULL, /* etxo_qpio_enable */ + NULL, /* etxo_qpio_disable */ + NULL, /* etxo_qpio_write */ + NULL, /* etxo_qpio_post */ + falconsiena_tx_qdesc_post, /* etxo_qdesc_post */ + falconsiena_tx_qdesc_dma_create, /* etxo_qdesc_dma_create */ + NULL, /* etxo_qdesc_tso_create */ + NULL, /* etxo_qdesc_vlantci_create */ +#if EFSYS_OPT_QSTATS + falconsiena_tx_qstats_update, /* etxo_qstats_update */ +#endif +}; +#endif /* EFSYS_OPT_FALCON */ + +#if EFSYS_OPT_SIENA +static efx_tx_ops_t __efx_tx_siena_ops = { + falconsiena_tx_init, /* etxo_init */ + falconsiena_tx_fini, /* etxo_fini */ + falconsiena_tx_qcreate, /* etxo_qcreate */ + falconsiena_tx_qdestroy, /* etxo_qdestroy */ + falconsiena_tx_qpost, /* etxo_qpost */ + falconsiena_tx_qpush, /* etxo_qpush */ + falconsiena_tx_qpace, /* etxo_qpace */ + falconsiena_tx_qflush, /* etxo_qflush */ + falconsiena_tx_qenable, /* etxo_qenable */ + NULL, /* etxo_qpio_enable */ + NULL, /* etxo_qpio_disable */ + NULL, /* etxo_qpio_write */ + NULL, /* etxo_qpio_post */ + falconsiena_tx_qdesc_post, /* etxo_qdesc_post */ + falconsiena_tx_qdesc_dma_create, /* etxo_qdesc_dma_create */ + NULL, /* etxo_qdesc_tso_create */ + NULL, /* etxo_qdesc_vlantci_create */ +#if EFSYS_OPT_QSTATS + falconsiena_tx_qstats_update, /* etxo_qstats_update */ +#endif +}; +#endif /* EFSYS_OPT_SIENA */ + +#if EFSYS_OPT_HUNTINGTON +static efx_tx_ops_t __efx_tx_hunt_ops = { + hunt_tx_init, /* etxo_init */ + hunt_tx_fini, /* etxo_fini */ + hunt_tx_qcreate, /* etxo_qcreate */ + hunt_tx_qdestroy, /* etxo_qdestroy */ + hunt_tx_qpost, /* etxo_qpost */ + hunt_tx_qpush, /* etxo_qpush */ + hunt_tx_qpace, /* etxo_qpace */ + hunt_tx_qflush, /* etxo_qflush */ + hunt_tx_qenable, /* etxo_qenable */ + hunt_tx_qpio_enable, /* etxo_qpio_enable */ + hunt_tx_qpio_disable, /* etxo_qpio_disable */ + hunt_tx_qpio_write, /* etxo_qpio_write */ + hunt_tx_qpio_post, /* etxo_qpio_post */ + hunt_tx_qdesc_post, /* etxo_qdesc_post */ + hunt_tx_qdesc_dma_create, /* etxo_qdesc_dma_create */ + hunt_tx_qdesc_tso_create, /* etxo_qdesc_tso_create */ + hunt_tx_qdesc_vlantci_create, /* etxo_qdesc_vlantci_create */ +#if EFSYS_OPT_QSTATS + hunt_tx_qstats_update, /* etxo_qstats_update */ +#endif +}; +#endif /* EFSYS_OPT_HUNTINGTON */ + + __checkReturn int efx_tx_init( __in efx_nic_t *enp) { - efx_oword_t oword; + efx_tx_ops_t *etxop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); if (!(enp->en_mod_flags & EFX_MOD_EV)) { rc = EINVAL; goto fail1; } if (enp->en_mod_flags & EFX_MOD_TX) { rc = EINVAL; goto fail2; } + switch (enp->en_family) { +#if EFSYS_OPT_FALCON + case EFX_FAMILY_FALCON: + etxop = (efx_tx_ops_t *)&__efx_tx_falcon_ops; + break; +#endif /* EFSYS_OPT_FALCON */ + +#if EFSYS_OPT_SIENA + case EFX_FAMILY_SIENA: + etxop = (efx_tx_ops_t *)&__efx_tx_siena_ops; + break; +#endif /* EFSYS_OPT_SIENA */ + +#if EFSYS_OPT_HUNTINGTON + case EFX_FAMILY_HUNTINGTON: + etxop = (efx_tx_ops_t *)&__efx_tx_hunt_ops; + break; +#endif /* EFSYS_OPT_HUNTINGTON */ + + default: + EFSYS_ASSERT(0); + rc = ENOTSUP; + goto fail3; + } + EFSYS_ASSERT3U(enp->en_tx_qcount, ==, 0); + if ((rc = etxop->etxo_init(enp)) != 0) + goto fail4; + + enp->en_etxop = etxop; + enp->en_mod_flags |= EFX_MOD_TX; + return (0); + +fail4: + EFSYS_PROBE(fail4); +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + enp->en_etxop = NULL; + enp->en_mod_flags &= ~EFX_MOD_TX; + return (rc); +} + + void +efx_tx_fini( + __in efx_nic_t *enp) +{ + efx_tx_ops_t *etxop = enp->en_etxop; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_TX); + EFSYS_ASSERT3U(enp->en_tx_qcount, ==, 0); + + etxop->etxo_fini(enp); + + enp->en_etxop = NULL; + enp->en_mod_flags &= ~EFX_MOD_TX; +} + + __checkReturn int +efx_tx_qcreate( + __in efx_nic_t *enp, + __in unsigned int index, + __in unsigned int label, + __in efsys_mem_t *esmp, + __in size_t n, + __in uint32_t id, + __in uint16_t flags, + __in efx_evq_t *eep, + __deref_out efx_txq_t **etpp, + __out unsigned int *addedp) +{ + efx_tx_ops_t *etxop = enp->en_etxop; + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + efx_txq_t *etp; + int rc; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_TX); + + EFSYS_ASSERT3U(enp->en_tx_qcount + 1, <, encp->enc_txq_limit); + + /* Allocate an TXQ object */ + EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_txq_t), etp); + + if (etp == NULL) { + rc = ENOMEM; + goto fail1; + } + + etp->et_magic = EFX_TXQ_MAGIC; + etp->et_enp = enp; + etp->et_index = index; + etp->et_mask = n - 1; + etp->et_esmp = esmp; + + /* Initial descriptor index may be modified by etxo_qcreate */ + *addedp = 0; + + if ((rc = etxop->etxo_qcreate(enp, index, label, esmp, + n, id, flags, eep, etp, addedp)) != 0) + goto fail2; + + enp->en_tx_qcount++; + *etpp = etp; + + return (0); + +fail2: + EFSYS_PROBE(fail2); + EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_txq_t), etp); +fail1: + EFSYS_PROBE1(fail1, int, rc); + return (rc); +} + + void +efx_tx_qdestroy( + __in efx_txq_t *etp) +{ + efx_nic_t *enp = etp->et_enp; + efx_tx_ops_t *etxop = enp->en_etxop; + + EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); + + EFSYS_ASSERT(enp->en_tx_qcount != 0); + --enp->en_tx_qcount; + + etxop->etxo_qdestroy(etp); + + /* Free the TXQ object */ + EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_txq_t), etp); +} + + __checkReturn int +efx_tx_qpost( + __in efx_txq_t *etp, + __in_ecount(n) efx_buffer_t *eb, + __in unsigned int n, + __in unsigned int completed, + __inout unsigned int *addedp) +{ + efx_nic_t *enp = etp->et_enp; + efx_tx_ops_t *etxop = enp->en_etxop; + int rc; + + EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); + + if ((rc = etxop->etxo_qpost(etp, eb, + n, completed, addedp)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + return (rc); +} + + void +efx_tx_qpush( + __in efx_txq_t *etp, + __in unsigned int added, + __in unsigned int pushed) +{ + efx_nic_t *enp = etp->et_enp; + efx_tx_ops_t *etxop = enp->en_etxop; + + EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); + + etxop->etxo_qpush(etp, added, pushed); +} + + __checkReturn int +efx_tx_qpace( + __in efx_txq_t *etp, + __in unsigned int ns) +{ + efx_nic_t *enp = etp->et_enp; + efx_tx_ops_t *etxop = enp->en_etxop; + int rc; + + EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); + + if ((rc = etxop->etxo_qpace(etp, ns)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + return (rc); +} + + __checkReturn int +efx_tx_qflush( + __in efx_txq_t *etp) +{ + efx_nic_t *enp = etp->et_enp; + efx_tx_ops_t *etxop = enp->en_etxop; + int rc; + + EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); + + if ((rc = etxop->etxo_qflush(etp)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + return (rc); +} + + void +efx_tx_qenable( + __in efx_txq_t *etp) +{ + efx_nic_t *enp = etp->et_enp; + efx_tx_ops_t *etxop = enp->en_etxop; + + EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); + + etxop->etxo_qenable(etp); +} + + __checkReturn int +efx_tx_qpio_enable( + __in efx_txq_t *etp) +{ + efx_nic_t *enp = etp->et_enp; + efx_tx_ops_t *etxop = enp->en_etxop; + int rc; + + EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); + + if (~enp->en_features & EFX_FEATURE_PIO_BUFFERS) { + rc = ENOTSUP; + goto fail1; + } + if (etxop->etxo_qpio_enable == NULL) { + rc = ENOTSUP; + goto fail2; + } + if ((rc = etxop->etxo_qpio_enable(etp)) != 0) + goto fail3; + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + return (rc); +} + + void +efx_tx_qpio_disable( + __in efx_txq_t *etp) +{ + efx_nic_t *enp = etp->et_enp; + efx_tx_ops_t *etxop = enp->en_etxop; + + EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); + + if (etxop->etxo_qpio_disable != NULL) + etxop->etxo_qpio_disable(etp); +} + + __checkReturn int +efx_tx_qpio_write( + __in efx_txq_t *etp, + __in_ecount(buf_length) uint8_t *buffer, + __in size_t buf_length, + __in size_t pio_buf_offset) +{ + efx_nic_t *enp = etp->et_enp; + efx_tx_ops_t *etxop = enp->en_etxop; + int rc; + + EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); + + if (etxop->etxo_qpio_write != NULL) { + if ((rc = etxop->etxo_qpio_write(etp, buffer, buf_length, + pio_buf_offset)) != 0) + goto fail1; + return (0); + } + + return (ENOTSUP); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + return (rc); +} + + __checkReturn int +efx_tx_qpio_post( + __in efx_txq_t *etp, + __in size_t pkt_length, + __in unsigned int completed, + __inout unsigned int *addedp) +{ + efx_nic_t *enp = etp->et_enp; + efx_tx_ops_t *etxop = enp->en_etxop; + int rc; + + EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); + + if (etxop->etxo_qpio_post != NULL) { + if ((rc = etxop->etxo_qpio_post(etp, pkt_length, completed, + addedp)) != 0) + goto fail1; + return (0); + } + + return (ENOTSUP); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + return (rc); +} + + __checkReturn int +efx_tx_qdesc_post( + __in efx_txq_t *etp, + __in_ecount(n) efx_desc_t *ed, + __in unsigned int n, + __in unsigned int completed, + __inout unsigned int *addedp) +{ + efx_nic_t *enp = etp->et_enp; + efx_tx_ops_t *etxop = enp->en_etxop; + int rc; + + EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); + + if ((rc = etxop->etxo_qdesc_post(etp, ed, + n, completed, addedp)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + return (rc); +} + + void +efx_tx_qdesc_dma_create( + __in efx_txq_t *etp, + __in efsys_dma_addr_t addr, + __in size_t size, + __in boolean_t eop, + __out efx_desc_t *edp) +{ + efx_nic_t *enp = etp->et_enp; + efx_tx_ops_t *etxop = enp->en_etxop; + + EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); + EFSYS_ASSERT(etxop->etxo_qdesc_dma_create != NULL); + + etxop->etxo_qdesc_dma_create(etp, addr, size, eop, edp); +} + + void +efx_tx_qdesc_tso_create( + __in efx_txq_t *etp, + __in uint16_t ipv4_id, + __in uint32_t tcp_seq, + __in uint8_t tcp_flags, + __out efx_desc_t *edp) +{ + efx_nic_t *enp = etp->et_enp; + efx_tx_ops_t *etxop = enp->en_etxop; + + EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); + EFSYS_ASSERT(etxop->etxo_qdesc_tso_create != NULL); + + etxop->etxo_qdesc_tso_create(etp, ipv4_id, tcp_seq, tcp_flags, edp); +} + + void +efx_tx_qdesc_vlantci_create( + __in efx_txq_t *etp, + __in uint16_t tci, + __out efx_desc_t *edp) +{ + efx_nic_t *enp = etp->et_enp; + efx_tx_ops_t *etxop = enp->en_etxop; + + EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); + EFSYS_ASSERT(etxop->etxo_qdesc_vlantci_create != NULL); + + etxop->etxo_qdesc_vlantci_create(etp, tci, edp); +} + + +#if EFSYS_OPT_QSTATS + void +efx_tx_qstats_update( + __in efx_txq_t *etp, + __inout_ecount(TX_NQSTATS) efsys_stat_t *stat) +{ + efx_nic_t *enp = etp->et_enp; + efx_tx_ops_t *etxop = enp->en_etxop; + + EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); + + etxop->etxo_qstats_update(etp, stat); +} +#endif + + +#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA + +static __checkReturn int +falconsiena_tx_init( + __in efx_nic_t *enp) +{ + efx_oword_t oword; + /* * Disable the timer-based TX DMA backoff and allow TX DMA to be * controlled by the RX FIFO fill level (although always allow a * minimal trickle). */ EFX_BAR_READO(enp, FR_AZ_TX_RESERVED_REG, &oword); EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_RX_SPACER, 0xfe); EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_RX_SPACER_EN, 1); EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_ONE_PKT_PER_Q, 1); EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_PUSH_EN, 0); EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_DIS_NON_IP_EV, 1); EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_PREF_THRESHOLD, 2); EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_PREF_WD_TMR, 0x3fffff); /* * Filter all packets less than 14 bytes to avoid parsing * errors. */ EFX_SET_OWORD_FIELD(oword, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1); EFX_BAR_WRITEO(enp, FR_AZ_TX_RESERVED_REG, &oword); /* * Do not set TX_NO_EOP_DISC_EN, since it limits packets to 16 * descriptors (which is bad). */ EFX_BAR_READO(enp, FR_AZ_TX_CFG_REG, &oword); EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_NO_EOP_DISC_EN, 0); EFX_BAR_WRITEO(enp, FR_AZ_TX_CFG_REG, &oword); - enp->en_mod_flags |= EFX_MOD_TX; return (0); - -fail2: - EFSYS_PROBE(fail2); -fail1: - EFSYS_PROBE1(fail1, int, rc); - - return (rc); } -#if EFSYS_OPT_FILTER -extern __checkReturn int -efx_tx_filter_insert( - __in efx_txq_t *etp, - __inout efx_filter_spec_t *spec) -{ - EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); - EFSYS_ASSERT3P(spec, !=, NULL); - - spec->efs_dmaq_id = (uint16_t)etp->et_index; - return (efx_filter_insert_filter(etp->et_enp, spec, B_FALSE)); -} -#endif - -#if EFSYS_OPT_FILTER -extern __checkReturn int -efx_tx_filter_remove( - __in efx_txq_t *etp, - __inout efx_filter_spec_t *spec) -{ - EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); - EFSYS_ASSERT3P(spec, !=, NULL); - - spec->efs_dmaq_id = (uint16_t)etp->et_index; - return (efx_filter_remove_filter(etp->et_enp, spec)); -} -#endif - #define EFX_TX_DESC(_etp, _addr, _size, _eop, _added) \ do { \ unsigned int id; \ size_t offset; \ efx_qword_t qword; \ \ id = (_added)++ & (_etp)->et_mask; \ offset = id * sizeof (efx_qword_t); \ \ EFSYS_PROBE5(tx_post, unsigned int, (_etp)->et_index, \ unsigned int, id, efsys_dma_addr_t, (_addr), \ size_t, (_size), boolean_t, (_eop)); \ \ EFX_POPULATE_QWORD_4(qword, \ FSF_AZ_TX_KER_CONT, (_eop) ? 0 : 1, \ FSF_AZ_TX_KER_BYTE_COUNT, (uint32_t)(_size), \ FSF_AZ_TX_KER_BUF_ADDR_DW0, \ (uint32_t)((_addr) & 0xffffffff), \ FSF_AZ_TX_KER_BUF_ADDR_DW1, \ (uint32_t)((_addr) >> 32)); \ EFSYS_MEM_WRITEQ((_etp)->et_esmp, offset, &qword); \ \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) - __checkReturn int -efx_tx_qpost( +static __checkReturn int +falconsiena_tx_qpost( __in efx_txq_t *etp, __in_ecount(n) efx_buffer_t *eb, __in unsigned int n, __in unsigned int completed, __inout unsigned int *addedp) { unsigned int added = *addedp; unsigned int i; int rc = ENOSPC; - EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); - if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) goto fail1; for (i = 0; i < n; i++) { efx_buffer_t *ebp = &eb[i]; efsys_dma_addr_t start = ebp->eb_addr; size_t size = ebp->eb_size; efsys_dma_addr_t end = start + size; /* Fragments must not span 4k boundaries. */ EFSYS_ASSERT(P2ROUNDUP(start + 1, 4096) >= end); EFX_TX_DESC(etp, start, size, ebp->eb_eop, added); } EFX_TX_QSTAT_INCR(etp, TX_POST); *addedp = added; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } - void -efx_tx_qpush( +static void +falconsiena_tx_qpush( __in efx_txq_t *etp, - __in unsigned int added) + __in unsigned int added, + __in unsigned int pushed) { efx_nic_t *enp = etp->et_enp; uint32_t wptr; efx_dword_t dword; efx_oword_t oword; - EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); - - /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */ - EFSYS_PIO_WRITE_BARRIER(); - /* Push the populated descriptors out */ wptr = added & etp->et_mask; EFX_POPULATE_OWORD_1(oword, FRF_AZ_TX_DESC_WPTR, wptr); /* Only write the third DWORD */ EFX_POPULATE_DWORD_1(dword, EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3)); + + /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */ + EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1, + wptr, pushed & etp->et_mask); + EFSYS_PIO_WRITE_BARRIER(); EFX_BAR_TBL_WRITED3(enp, FR_BZ_TX_DESC_UPD_REGP0, etp->et_index, &dword, B_FALSE); } #define EFX_MAX_PACE_VALUE 20 #define EFX_TX_PACE_CLOCK_BASE 104 - __checkReturn int -efx_tx_qpace( +static __checkReturn int +falconsiena_tx_qpace( __in efx_txq_t *etp, __in unsigned int ns) { efx_nic_t *enp = etp->et_enp; efx_nic_cfg_t *encp = &(enp->en_nic_cfg); efx_oword_t oword; unsigned int pace_val; unsigned int timer_period; int rc; - EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); - if (ns == 0) { pace_val = 0; } else { /* * The pace_val to write into the table is s.t * ns <= timer_period * (2 ^ pace_val) */ timer_period = EFX_TX_PACE_CLOCK_BASE / encp->enc_clk_mult; for (pace_val = 1; pace_val <= EFX_MAX_PACE_VALUE; pace_val++) { if ((timer_period << pace_val) >= ns) break; } } if (pace_val > EFX_MAX_PACE_VALUE) { rc = EINVAL; goto fail1; } /* Update the pacing table */ EFX_POPULATE_OWORD_1(oword, FRF_AZ_TX_PACE, pace_val); - EFX_BAR_TBL_WRITEO(enp, FR_AZ_TX_PACE_TBL, etp->et_index, &oword); + EFX_BAR_TBL_WRITEO(enp, FR_AZ_TX_PACE_TBL, etp->et_index, + &oword, B_TRUE); return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } - void -efx_tx_qflush( - __in efx_txq_t *etp) +static __checkReturn int +falconsiena_tx_qflush( + __in efx_txq_t *etp) { efx_nic_t *enp = etp->et_enp; efx_oword_t oword; uint32_t label; - EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); - efx_tx_qpace(etp, 0); label = etp->et_index; /* Flush the queue */ EFX_POPULATE_OWORD_2(oword, FRF_AZ_TX_FLUSH_DESCQ_CMD, 1, FRF_AZ_TX_FLUSH_DESCQ, label); EFX_BAR_WRITEO(enp, FR_AZ_TX_FLUSH_DESCQ_REG, &oword); + + return (0); } - void -efx_tx_qenable( +static void +falconsiena_tx_qenable( __in efx_txq_t *etp) { efx_nic_t *enp = etp->et_enp; efx_oword_t oword; - EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); - EFX_BAR_TBL_READO(enp, FR_AZ_TX_DESC_PTR_TBL, - etp->et_index, &oword); + etp->et_index, &oword, B_TRUE); EFSYS_PROBE5(tx_descq_ptr, unsigned int, etp->et_index, uint32_t, EFX_OWORD_FIELD(oword, EFX_DWORD_3), uint32_t, EFX_OWORD_FIELD(oword, EFX_DWORD_2), uint32_t, EFX_OWORD_FIELD(oword, EFX_DWORD_1), uint32_t, EFX_OWORD_FIELD(oword, EFX_DWORD_0)); EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_DC_HW_RPTR, 0); EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_DESCQ_HW_RPTR, 0); EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_DESCQ_EN, 1); EFX_BAR_TBL_WRITEO(enp, FR_AZ_TX_DESC_PTR_TBL, - etp->et_index, &oword); + etp->et_index, &oword, B_TRUE); } - __checkReturn int -efx_tx_qcreate( +static __checkReturn int +falconsiena_tx_qcreate( __in efx_nic_t *enp, __in unsigned int index, __in unsigned int label, __in efsys_mem_t *esmp, __in size_t n, __in uint32_t id, __in uint16_t flags, __in efx_evq_t *eep, - __deref_out efx_txq_t **etpp) + __in efx_txq_t *etp, + __out unsigned int *addedp) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); - efx_txq_t *etp; efx_oword_t oword; uint32_t size; int rc; - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_TX); - EFX_STATIC_ASSERT(EFX_EV_TX_NLABELS == (1 << FRF_AZ_TX_DESCQ_LABEL_WIDTH)); EFSYS_ASSERT3U(label, <, EFX_EV_TX_NLABELS); - EFSYS_ASSERT3U(enp->en_tx_qcount + 1, <, encp->enc_txq_limit); - if (!ISP2(n) || !(n & EFX_TXQ_NDESCS_MASK)) { + EFSYS_ASSERT(ISP2(EFX_TXQ_MAXNDESCS(encp))); + EFX_STATIC_ASSERT(ISP2(EFX_TXQ_MINNDESCS)); + + if (!ISP2(n) || (n < EFX_TXQ_MINNDESCS) || (n > EFX_EVQ_MAXNEVS)) { rc = EINVAL; goto fail1; } if (index >= encp->enc_txq_limit) { rc = EINVAL; goto fail2; } - for (size = 0; (1 << size) <= (EFX_TXQ_MAXNDESCS / EFX_TXQ_MINNDESCS); + for (size = 0; + (1 << size) <= (EFX_TXQ_MAXNDESCS(encp) / EFX_TXQ_MINNDESCS); size++) if ((1 << size) == (int)(n / EFX_TXQ_MINNDESCS)) break; if (id + (1 << size) >= encp->enc_buftbl_limit) { rc = EINVAL; goto fail3; } - /* Allocate an TXQ object */ - EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_txq_t), etp); - - if (etp == NULL) { - rc = ENOMEM; - goto fail4; - } - - etp->et_magic = EFX_TXQ_MAGIC; - etp->et_enp = enp; - etp->et_index = index; - etp->et_mask = n - 1; - etp->et_esmp = esmp; - /* Set up the new descriptor queue */ EFX_POPULATE_OWORD_6(oword, FRF_AZ_TX_DESCQ_BUF_BASE_ID, id, FRF_AZ_TX_DESCQ_EVQ_ID, eep->ee_index, FRF_AZ_TX_DESCQ_OWNER_ID, 0, FRF_AZ_TX_DESCQ_LABEL, label, FRF_AZ_TX_DESCQ_SIZE, size, FRF_AZ_TX_DESCQ_TYPE, 0); EFX_SET_OWORD_FIELD(oword, FRF_BZ_TX_NON_IP_DROP_DIS, 1); EFX_SET_OWORD_FIELD(oword, FRF_BZ_TX_IP_CHKSM_DIS, (flags & EFX_CKSUM_IPV4) ? 0 : 1); EFX_SET_OWORD_FIELD(oword, FRF_BZ_TX_TCP_CHKSM_DIS, (flags & EFX_CKSUM_TCPUDP) ? 0 : 1); EFX_BAR_TBL_WRITEO(enp, FR_AZ_TX_DESC_PTR_TBL, - etp->et_index, &oword); + etp->et_index, &oword, B_TRUE); - enp->en_tx_qcount++; - *etpp = etp; return (0); -fail4: - EFSYS_PROBE(fail4); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } + __checkReturn int +falconsiena_tx_qdesc_post( + __in efx_txq_t *etp, + __in_ecount(n) efx_desc_t *ed, + __in unsigned int n, + __in unsigned int completed, + __inout unsigned int *addedp) +{ + unsigned int added = *addedp; + unsigned int i; + int rc; + + if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) { + rc = ENOSPC; + goto fail1; + } + + for (i = 0; i < n; i++) { + efx_desc_t *edp = &ed[i]; + unsigned int id; + size_t offset; + + id = added++ & etp->et_mask; + offset = id * sizeof (efx_desc_t); + + EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &edp->ed_eq); + } + + EFSYS_PROBE3(tx_desc_post, unsigned int, etp->et_index, + unsigned int, added, unsigned int, n); + + EFX_TX_QSTAT_INCR(etp, TX_POST); + + *addedp = added; + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + return (rc); +} + + void +falconsiena_tx_qdesc_dma_create( + __in efx_txq_t *etp, + __in efsys_dma_addr_t addr, + __in size_t size, + __in boolean_t eop, + __out efx_desc_t *edp) +{ + /* Fragments must not span 4k boundaries. */ + EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= addr + size); + + EFSYS_PROBE4(tx_desc_dma_create, unsigned int, etp->et_index, + efsys_dma_addr_t, addr, + size_t, size, boolean_t, eop); + + EFX_POPULATE_QWORD_4(edp->ed_eq, + FSF_AZ_TX_KER_CONT, eop ? 0 : 1, + FSF_AZ_TX_KER_BYTE_COUNT, (uint32_t)size, + FSF_AZ_TX_KER_BUF_ADDR_DW0, + (uint32_t)(addr & 0xffffffff), + FSF_AZ_TX_KER_BUF_ADDR_DW1, + (uint32_t)(addr >> 32)); +} + +#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ + #if EFSYS_OPT_QSTATS #if EFSYS_OPT_NAMES -/* START MKCONFIG GENERATED EfxTransmitQueueStatNamesBlock 78ca9ab00287fffb */ -static const char __cs * __cs __efx_tx_qstat_name[] = { +/* START MKCONFIG GENERATED EfxTransmitQueueStatNamesBlock 9d8d26a0a5e2c453 */ +static const char *__efx_tx_qstat_name[] = { "post", - "unaligned_split", + "post_pio", }; /* END MKCONFIG GENERATED EfxTransmitQueueStatNamesBlock */ - const char __cs * + const char * efx_tx_qstat_name( __in efx_nic_t *enp, __in unsigned int id) { _NOTE(ARGUNUSED(enp)) EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(id, <, TX_NQSTATS); return (__efx_tx_qstat_name[id]); } #endif /* EFSYS_OPT_NAMES */ -#endif /* EFSYS_OPT_QSTATS */ +#endif /* EFSYS_OPT_QSTATS */ +#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA + #if EFSYS_OPT_QSTATS - void -efx_tx_qstats_update( +static void +falconsiena_tx_qstats_update( __in efx_txq_t *etp, __inout_ecount(TX_NQSTATS) efsys_stat_t *stat) { unsigned int id; - EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); - for (id = 0; id < TX_NQSTATS; id++) { efsys_stat_t *essp = &stat[id]; EFSYS_STAT_INCR(essp, etp->et_stat[id]); etp->et_stat[id] = 0; } } #endif /* EFSYS_OPT_QSTATS */ - void -efx_tx_qdestroy( +static void +falconsiena_tx_qdestroy( __in efx_txq_t *etp) { efx_nic_t *enp = etp->et_enp; efx_oword_t oword; - EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); - - EFSYS_ASSERT(enp->en_tx_qcount != 0); - --enp->en_tx_qcount; - /* Purge descriptor queue */ EFX_ZERO_OWORD(oword); EFX_BAR_TBL_WRITEO(enp, FR_AZ_TX_DESC_PTR_TBL, - etp->et_index, &oword); - - /* Free the TXQ object */ - EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_txq_t), etp); + etp->et_index, &oword, B_TRUE); } - void -efx_tx_fini( +static void +falconsiena_tx_fini( __in efx_nic_t *enp) { - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_TX); - EFSYS_ASSERT3U(enp->en_tx_qcount, ==, 0); - - enp->en_mod_flags &= ~EFX_MOD_TX; + _NOTE(ARGUNUSED(enp)) } + +#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ Property changes on: head/sys/dev/sfxge/common/efx_tx.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_types.h =================================================================== --- head/sys/dev/sfxge/common/efx_types.h (revision 283513) +++ head/sys/dev/sfxge/common/efx_types.h (revision 283514) @@ -1,1607 +1,1649 @@ /*- - * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2007-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + * * Ackowledgement to Fen Systems Ltd. * * $FreeBSD$ */ #ifndef _SYS_EFX_TYPES_H #define _SYS_EFX_TYPES_H #include "efsys.h" #ifdef __cplusplus extern "C" { #endif /* * Bitfield access * * Solarflare NICs make extensive use of bitfields up to 128 bits * wide. Since there is no native 128-bit datatype on most systems, * and since 64-bit datatypes are inefficient on 32-bit systems and * vice versa, we wrap accesses in a way that uses the most efficient * datatype. * * The NICs are PCI devices and therefore little-endian. Since most * of the quantities that we deal with are DMAed to/from host memory, * we define our datatypes (efx_oword_t, efx_qword_t and efx_dword_t) * to be little-endian. * * In the less common case of using PIO for individual register * writes, we construct the little-endian datatype in host memory and * then use non-swapping register access primitives, rather than * constructing a native-endian datatype and relying on implicit * byte-swapping. (We use a similar strategy for register reads.) */ /* * NOTE: Field definitions here and elsewhere are done in terms of a lowest * bit number (LBN) and a width. */ #define EFX_DUMMY_FIELD_LBN 0 #define EFX_DUMMY_FIELD_WIDTH 0 #define EFX_BYTE_0_LBN 0 #define EFX_BYTE_0_WIDTH 8 #define EFX_BYTE_1_LBN 8 #define EFX_BYTE_1_WIDTH 8 #define EFX_BYTE_2_LBN 16 #define EFX_BYTE_2_WIDTH 8 #define EFX_BYTE_3_LBN 24 #define EFX_BYTE_3_WIDTH 8 #define EFX_BYTE_4_LBN 32 #define EFX_BYTE_4_WIDTH 8 #define EFX_BYTE_5_LBN 40 #define EFX_BYTE_5_WIDTH 8 #define EFX_BYTE_6_LBN 48 #define EFX_BYTE_6_WIDTH 8 #define EFX_BYTE_7_LBN 56 #define EFX_BYTE_7_WIDTH 8 #define EFX_WORD_0_LBN 0 #define EFX_WORD_0_WIDTH 16 #define EFX_WORD_1_LBN 16 #define EFX_WORD_1_WIDTH 16 #define EFX_WORD_2_LBN 32 #define EFX_WORD_2_WIDTH 16 #define EFX_WORD_3_LBN 48 #define EFX_WORD_3_WIDTH 16 #define EFX_DWORD_0_LBN 0 #define EFX_DWORD_0_WIDTH 32 #define EFX_DWORD_1_LBN 32 #define EFX_DWORD_1_WIDTH 32 #define EFX_DWORD_2_LBN 64 #define EFX_DWORD_2_WIDTH 32 #define EFX_DWORD_3_LBN 96 #define EFX_DWORD_3_WIDTH 32 -#define EFX_QWORD_0_LBN 0 -#define EFX_QWORD_0_WIDTH 64 +/* There are intentionally no EFX_QWORD_0 or EFX_QWORD_1 field definitions + * here as the implementaion of EFX_QWORD_FIELD and EFX_OWORD_FIELD do not + * support field widths larger than 32 bits. + */ -#define EFX_QWORD_1_LBN 64 -#define EFX_QWORD_1_WIDTH 64 - /* Specified attribute (i.e. LBN ow WIDTH) of the specified field */ #define EFX_VAL(_field, _attribute) \ _field ## _ ## _attribute /* Lowest bit number of the specified field */ #define EFX_LOW_BIT(_field) \ EFX_VAL(_field, LBN) /* Width of the specified field */ #define EFX_WIDTH(_field) \ EFX_VAL(_field, WIDTH) /* Highest bit number of the specified field */ #define EFX_HIGH_BIT(_field) \ (EFX_LOW_BIT(_field) + EFX_WIDTH(_field) - 1) /* * 64-bit mask equal in width to the specified field. * * For example, a field with width 5 would have a mask of 0x000000000000001f. */ #define EFX_MASK64(_field) \ ((EFX_WIDTH(_field) == 64) ? ~((uint64_t)0) : \ (((((uint64_t)1) << EFX_WIDTH(_field))) - 1)) /* * 32-bit mask equal in width to the specified field. * * For example, a field with width 5 would have a mask of 0x0000001f. */ #define EFX_MASK32(_field) \ ((EFX_WIDTH(_field) == 32) ? ~((uint32_t)0) : \ (((((uint32_t)1) << EFX_WIDTH(_field))) - 1)) /* * 16-bit mask equal in width to the specified field. * * For example, a field with width 5 would have a mask of 0x001f. */ #define EFX_MASK16(_field) \ ((EFX_WIDTH(_field) == 16) ? 0xffffu : \ (uint16_t)((1 << EFX_WIDTH(_field)) - 1)) /* * 8-bit mask equal in width to the specified field. * * For example, a field with width 5 would have a mask of 0x1f. */ #define EFX_MASK8(_field) \ ((uint8_t)((1 << EFX_WIDTH(_field)) - 1)) #pragma pack(1) /* * A byte (i.e. 8-bit) datatype */ typedef union efx_byte_u { uint8_t eb_u8[1]; } efx_byte_t; /* * A word (i.e. 16-bit) datatype * * This datatype is defined to be little-endian. */ typedef union efx_word_u { efx_byte_t ew_byte[2]; uint16_t ew_u16[1]; uint8_t ew_u8[2]; } efx_word_t; /* * A doubleword (i.e. 32-bit) datatype * * This datatype is defined to be little-endian. */ typedef union efx_dword_u { efx_byte_t ed_byte[4]; efx_word_t ed_word[2]; uint32_t ed_u32[1]; uint16_t ed_u16[2]; uint8_t ed_u8[4]; } efx_dword_t; /* * A quadword (i.e. 64-bit) datatype * * This datatype is defined to be little-endian. */ typedef union efx_qword_u { efx_byte_t eq_byte[8]; efx_word_t eq_word[4]; efx_dword_t eq_dword[2]; #if EFSYS_HAS_UINT64 uint64_t eq_u64[1]; #endif uint32_t eq_u32[2]; uint16_t eq_u16[4]; uint8_t eq_u8[8]; } efx_qword_t; /* * An octword (i.e. 128-bit) datatype * * This datatype is defined to be little-endian. */ typedef union efx_oword_u { efx_byte_t eo_byte[16]; efx_word_t eo_word[8]; efx_dword_t eo_dword[4]; efx_qword_t eo_qword[2]; +#if EFSYS_HAS_SSE2_M128 + __m128i eo_u128[1]; +#endif #if EFSYS_HAS_UINT64 uint64_t eo_u64[2]; #endif uint32_t eo_u32[4]; uint16_t eo_u16[8]; uint8_t eo_u8[16]; } efx_oword_t; #pragma pack() #define __SWAP16(_x) \ ((((_x) & 0xff) << 8) | \ (((_x) >> 8) & 0xff)) #define __SWAP32(_x) \ ((__SWAP16((_x) & 0xffff) << 16) | \ __SWAP16(((_x) >> 16) & 0xffff)) #define __SWAP64(_x) \ ((__SWAP32((_x) & 0xffffffff) << 32) | \ __SWAP32(((_x) >> 32) & 0xffffffff)) #define __NOSWAP16(_x) (_x) #define __NOSWAP32(_x) (_x) #define __NOSWAP64(_x) (_x) #if EFSYS_IS_BIG_ENDIAN #define __CPU_TO_LE_16(_x) (uint16_t)__SWAP16(_x) #define __LE_TO_CPU_16(_x) (uint16_t)__SWAP16(_x) #define __CPU_TO_BE_16(_x) (uint16_t)__NOSWAP16(_x) #define __BE_TO_CPU_16(_x) (uint16_t)__NOSWAP16(_x) #define __CPU_TO_LE_32(_x) (uint32_t)__SWAP32(_x) #define __LE_TO_CPU_32(_x) (uint32_t)__SWAP32(_x) #define __CPU_TO_BE_32(_x) (uint32_t)__NOSWAP32(_x) #define __BE_TO_CPU_32(_x) (uint32_t)__NOSWAP32(_x) #define __CPU_TO_LE_64(_x) (uint64_t)__SWAP64(_x) #define __LE_TO_CPU_64(_x) (uint64_t)__SWAP64(_x) #define __CPU_TO_BE_64(_x) (uint64_t)__NOSWAP64(_x) #define __BE_TO_CPU_64(_x) (uint64_t)__NOSWAP64(_x) #elif EFSYS_IS_LITTLE_ENDIAN #define __CPU_TO_LE_16(_x) (uint16_t)__NOSWAP16(_x) #define __LE_TO_CPU_16(_x) (uint16_t)__NOSWAP16(_x) #define __CPU_TO_BE_16(_x) (uint16_t)__SWAP16(_x) #define __BE_TO_CPU_16(_x) (uint16_t)__SWAP16(_x) #define __CPU_TO_LE_32(_x) (uint32_t)__NOSWAP32(_x) #define __LE_TO_CPU_32(_x) (uint32_t)__NOSWAP32(_x) #define __CPU_TO_BE_32(_x) (uint32_t)__SWAP32(_x) #define __BE_TO_CPU_32(_x) (uint32_t)__SWAP32(_x) #define __CPU_TO_LE_64(_x) (uint64_t)__NOSWAP64(_x) #define __LE_TO_CPU_64(_x) (uint64_t)__NOSWAP64(_x) #define __CPU_TO_BE_64(_x) (uint64_t)__SWAP64(_x) #define __BE_TO_CPU_64(_x) (uint64_t)__SWAP64(_x) #else #error "Neither of EFSYS_IS_{BIG,LITTLE}_ENDIAN is set" #endif #define __NATIVE_8(_x) (uint8_t)(_x) /* Format string for printing an efx_byte_t */ #define EFX_BYTE_FMT "0x%02x" /* Format string for printing an efx_word_t */ #define EFX_WORD_FMT "0x%04x" /* Format string for printing an efx_dword_t */ #define EFX_DWORD_FMT "0x%08x" /* Format string for printing an efx_qword_t */ #define EFX_QWORD_FMT "0x%08x:%08x" /* Format string for printing an efx_oword_t */ #define EFX_OWORD_FMT "0x%08x:%08x:%08x:%08x" /* Parameters for printing an efx_byte_t */ #define EFX_BYTE_VAL(_byte) \ ((unsigned int)__NATIVE_8((_byte).eb_u8[0])) /* Parameters for printing an efx_word_t */ #define EFX_WORD_VAL(_word) \ ((unsigned int)__LE_TO_CPU_16((_word).ew_u16[0])) /* Parameters for printing an efx_dword_t */ #define EFX_DWORD_VAL(_dword) \ ((unsigned int)__LE_TO_CPU_32((_dword).ed_u32[0])) /* Parameters for printing an efx_qword_t */ #define EFX_QWORD_VAL(_qword) \ ((unsigned int)__LE_TO_CPU_32((_qword).eq_u32[1])), \ ((unsigned int)__LE_TO_CPU_32((_qword).eq_u32[0])) /* Parameters for printing an efx_oword_t */ #define EFX_OWORD_VAL(_oword) \ ((unsigned int)__LE_TO_CPU_32((_oword).eo_u32[3])), \ ((unsigned int)__LE_TO_CPU_32((_oword).eo_u32[2])), \ ((unsigned int)__LE_TO_CPU_32((_oword).eo_u32[1])), \ ((unsigned int)__LE_TO_CPU_32((_oword).eo_u32[0])) /* * Stop lint complaining about some shifts. */ #ifdef __lint extern int fix_lint; #define FIX_LINT(_x) (_x + fix_lint) #else #define FIX_LINT(_x) (_x) #endif /* * Extract bit field portion [low,high) from the native-endian element * which contains bits [min,max). * * For example, suppose "element" represents the high 32 bits of a * 64-bit value, and we wish to extract the bits belonging to the bit * field occupying bits 28-45 of this 64-bit value. * * Then EFX_EXTRACT(_element, 32, 63, 28, 45) would give * * (_element) << 4 * * The result will contain the relevant bits filled in in the range * [0,high-low), with garbage in bits [high-low+1,...). */ #define EFX_EXTRACT_NATIVE(_element, _min, _max, _low, _high) \ ((FIX_LINT(_low > _max) || FIX_LINT(_high < _min)) ? \ 0U : \ ((_low > _min) ? \ ((_element) >> (_low - _min)) : \ ((_element) << (_min - _low)))) /* * Extract bit field portion [low,high) from the 64-bit little-endian * element which contains bits [min,max) */ #define EFX_EXTRACT64(_element, _min, _max, _low, _high) \ EFX_EXTRACT_NATIVE(__LE_TO_CPU_64(_element), _min, _max, _low, _high) /* * Extract bit field portion [low,high) from the 32-bit little-endian * element which contains bits [min,max) */ #define EFX_EXTRACT32(_element, _min, _max, _low, _high) \ EFX_EXTRACT_NATIVE(__LE_TO_CPU_32(_element), _min, _max, _low, _high) /* * Extract bit field portion [low,high) from the 16-bit little-endian * element which contains bits [min,max) */ #define EFX_EXTRACT16(_element, _min, _max, _low, _high) \ EFX_EXTRACT_NATIVE(__LE_TO_CPU_16(_element), _min, _max, _low, _high) /* * Extract bit field portion [low,high) from the 8-bit * element which contains bits [min,max) */ #define EFX_EXTRACT8(_element, _min, _max, _low, _high) \ EFX_EXTRACT_NATIVE(__NATIVE_8(_element), _min, _max, _low, _high) #define EFX_EXTRACT_OWORD64(_oword, _low, _high) \ (EFX_EXTRACT64((_oword).eo_u64[0], FIX_LINT(0), FIX_LINT(63), \ _low, _high) | \ EFX_EXTRACT64((_oword).eo_u64[1], FIX_LINT(64), FIX_LINT(127), \ _low, _high)) #define EFX_EXTRACT_OWORD32(_oword, _low, _high) \ (EFX_EXTRACT32((_oword).eo_u32[0], FIX_LINT(0), FIX_LINT(31), \ _low, _high) | \ EFX_EXTRACT32((_oword).eo_u32[1], FIX_LINT(32), FIX_LINT(63), \ _low, _high) | \ EFX_EXTRACT32((_oword).eo_u32[2], FIX_LINT(64), FIX_LINT(95), \ _low, _high) | \ EFX_EXTRACT32((_oword).eo_u32[3], FIX_LINT(96), FIX_LINT(127), \ _low, _high)) #define EFX_EXTRACT_QWORD64(_qword, _low, _high) \ (EFX_EXTRACT64((_qword).eq_u64[0], FIX_LINT(0), FIX_LINT(63), \ _low, _high)) #define EFX_EXTRACT_QWORD32(_qword, _low, _high) \ (EFX_EXTRACT32((_qword).eq_u32[0], FIX_LINT(0), FIX_LINT(31), \ _low, _high) | \ EFX_EXTRACT32((_qword).eq_u32[1], FIX_LINT(32), FIX_LINT(63), \ _low, _high)) #define EFX_EXTRACT_DWORD(_dword, _low, _high) \ (EFX_EXTRACT32((_dword).ed_u32[0], FIX_LINT(0), FIX_LINT(31), \ _low, _high)) #define EFX_EXTRACT_WORD(_word, _low, _high) \ (EFX_EXTRACT16((_word).ew_u16[0], FIX_LINT(0), FIX_LINT(15), \ _low, _high)) #define EFX_EXTRACT_BYTE(_byte, _low, _high) \ (EFX_EXTRACT8((_byte).eb_u8[0], FIX_LINT(0), FIX_LINT(7), \ _low, _high)) #define EFX_OWORD_FIELD64(_oword, _field) \ ((uint32_t)EFX_EXTRACT_OWORD64(_oword, EFX_LOW_BIT(_field), \ EFX_HIGH_BIT(_field)) & EFX_MASK32(_field)) #define EFX_OWORD_FIELD32(_oword, _field) \ (EFX_EXTRACT_OWORD32(_oword, EFX_LOW_BIT(_field), \ EFX_HIGH_BIT(_field)) & EFX_MASK32(_field)) #define EFX_QWORD_FIELD64(_qword, _field) \ ((uint32_t)EFX_EXTRACT_QWORD64(_qword, EFX_LOW_BIT(_field), \ EFX_HIGH_BIT(_field)) & EFX_MASK32(_field)) #define EFX_QWORD_FIELD32(_qword, _field) \ (EFX_EXTRACT_QWORD32(_qword, EFX_LOW_BIT(_field), \ EFX_HIGH_BIT(_field)) & EFX_MASK32(_field)) #define EFX_DWORD_FIELD(_dword, _field) \ (EFX_EXTRACT_DWORD(_dword, EFX_LOW_BIT(_field), \ EFX_HIGH_BIT(_field)) & EFX_MASK32(_field)) #define EFX_WORD_FIELD(_word, _field) \ (EFX_EXTRACT_WORD(_word, EFX_LOW_BIT(_field), \ EFX_HIGH_BIT(_field)) & EFX_MASK16(_field)) #define EFX_BYTE_FIELD(_byte, _field) \ (EFX_EXTRACT_BYTE(_byte, EFX_LOW_BIT(_field), \ EFX_HIGH_BIT(_field)) & EFX_MASK8(_field)) #define EFX_OWORD_IS_EQUAL64(_oword_a, _oword_b) \ ((_oword_a).eo_u64[0] == (_oword_b).eo_u64[0] && \ (_oword_a).eo_u64[1] == (_oword_b).eo_u64[1]) #define EFX_OWORD_IS_EQUAL32(_oword_a, _oword_b) \ ((_oword_a).eo_u32[0] == (_oword_b).eo_u32[0] && \ (_oword_a).eo_u32[1] == (_oword_b).eo_u32[1] && \ (_oword_a).eo_u32[2] == (_oword_b).eo_u32[2] && \ (_oword_a).eo_u32[3] == (_oword_b).eo_u32[3]) #define EFX_QWORD_IS_EQUAL64(_qword_a, _qword_b) \ ((_qword_a).eq_u64[0] == (_qword_b).eq_u64[0]) #define EFX_QWORD_IS_EQUAL32(_qword_a, _qword_b) \ ((_qword_a).eq_u32[0] == (_qword_b).eq_u32[0] && \ (_qword_a).eq_u32[1] == (_qword_b).eq_u32[1]) #define EFX_DWORD_IS_EQUAL(_dword_a, _dword_b) \ ((_dword_a).ed_u32[0] == (_dword_b).ed_u32[0]) #define EFX_WORD_IS_EQUAL(_word_a, _word_b) \ ((_word_a).ew_u16[0] == (_word_b).ew_u16[0]) #define EFX_BYTE_IS_EQUAL(_byte_a, _byte_b) \ ((_byte_a).eb_u8[0] == (_byte_b).eb_u8[0]) #define EFX_OWORD_IS_ZERO64(_oword) \ (((_oword).eo_u64[0] | \ (_oword).eo_u64[1]) == 0) #define EFX_OWORD_IS_ZERO32(_oword) \ (((_oword).eo_u32[0] | \ (_oword).eo_u32[1] | \ (_oword).eo_u32[2] | \ (_oword).eo_u32[3]) == 0) #define EFX_QWORD_IS_ZERO64(_qword) \ (((_qword).eq_u64[0]) == 0) #define EFX_QWORD_IS_ZERO32(_qword) \ (((_qword).eq_u32[0] | \ (_qword).eq_u32[1]) == 0) #define EFX_DWORD_IS_ZERO(_dword) \ (((_dword).ed_u32[0]) == 0) #define EFX_WORD_IS_ZERO(_word) \ (((_word).ew_u16[0]) == 0) #define EFX_BYTE_IS_ZERO(_byte) \ (((_byte).eb_u8[0]) == 0) #define EFX_OWORD_IS_SET64(_oword) \ (((_oword).eo_u64[0] & \ (_oword).eo_u64[1]) == ~((uint64_t)0)) #define EFX_OWORD_IS_SET32(_oword) \ (((_oword).eo_u32[0] & \ (_oword).eo_u32[1] & \ (_oword).eo_u32[2] & \ (_oword).eo_u32[3]) == ~((uint32_t)0)) #define EFX_QWORD_IS_SET64(_qword) \ (((_qword).eq_u64[0]) == ~((uint32_t)0)) #define EFX_QWORD_IS_SET32(_qword) \ (((_qword).eq_u32[0] & \ (_qword).eq_u32[1]) == ~((uint32_t)0)) #define EFX_DWORD_IS_SET(_dword) \ ((_dword).ed_u32[0] == ~((uint32_t)0)) #define EFX_WORD_IS_SET(_word) \ ((_word).ew_u16[0] == ~((uint16_t)0)) #define EFX_BYTE_IS_SET(_byte) \ ((_byte).eb_u8[0] == ~((uint8_t)0)) /* * Construct bit field portion * * Creates the portion of the bit field [low,high) that lies within * the range [min,max). */ #define EFX_INSERT_NATIVE64(_min, _max, _low, _high, _value) \ (((_low > _max) || (_high < _min)) ? \ 0U : \ ((_low > _min) ? \ (((uint64_t)(_value)) << (_low - _min)) : \ (((uint64_t)(_value)) >> (_min - _low)))) #define EFX_INSERT_NATIVE32(_min, _max, _low, _high, _value) \ (((_low > _max) || (_high < _min)) ? \ 0U : \ ((_low > _min) ? \ (((uint32_t)(_value)) << (_low - _min)) : \ (((uint32_t)(_value)) >> (_min - _low)))) #define EFX_INSERT_NATIVE16(_min, _max, _low, _high, _value) \ (((_low > _max) || (_high < _min)) ? \ 0U : \ (uint16_t)((_low > _min) ? \ ((_value) << (_low - _min)) : \ ((_value) >> (_min - _low)))) #define EFX_INSERT_NATIVE8(_min, _max, _low, _high, _value) \ (((_low > _max) || (_high < _min)) ? \ 0U : \ (uint8_t)((_low > _min) ? \ ((_value) << (_low - _min)) : \ ((_value) >> (_min - _low)))) /* * Construct bit field portion * * Creates the portion of the named bit field that lies within the * range [min,max). */ #define EFX_INSERT_FIELD_NATIVE64(_min, _max, _field, _value) \ EFX_INSERT_NATIVE64(_min, _max, EFX_LOW_BIT(_field), \ EFX_HIGH_BIT(_field), _value) #define EFX_INSERT_FIELD_NATIVE32(_min, _max, _field, _value) \ EFX_INSERT_NATIVE32(_min, _max, EFX_LOW_BIT(_field), \ EFX_HIGH_BIT(_field), _value) #define EFX_INSERT_FIELD_NATIVE16(_min, _max, _field, _value) \ EFX_INSERT_NATIVE16(_min, _max, EFX_LOW_BIT(_field), \ EFX_HIGH_BIT(_field), _value) #define EFX_INSERT_FIELD_NATIVE8(_min, _max, _field, _value) \ EFX_INSERT_NATIVE8(_min, _max, EFX_LOW_BIT(_field), \ EFX_HIGH_BIT(_field), _value) /* * Construct bit field * * Creates the portion of the named bit fields that lie within the * range [min,max). */ #define EFX_INSERT_FIELDS64(_min, _max, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, _field9, _value9, \ _field10, _value10) \ __CPU_TO_LE_64( \ EFX_INSERT_FIELD_NATIVE64(_min, _max, _field1, _value1) | \ EFX_INSERT_FIELD_NATIVE64(_min, _max, _field2, _value2) | \ EFX_INSERT_FIELD_NATIVE64(_min, _max, _field3, _value3) | \ EFX_INSERT_FIELD_NATIVE64(_min, _max, _field4, _value4) | \ EFX_INSERT_FIELD_NATIVE64(_min, _max, _field5, _value5) | \ EFX_INSERT_FIELD_NATIVE64(_min, _max, _field6, _value6) | \ EFX_INSERT_FIELD_NATIVE64(_min, _max, _field7, _value7) | \ EFX_INSERT_FIELD_NATIVE64(_min, _max, _field8, _value8) | \ EFX_INSERT_FIELD_NATIVE64(_min, _max, _field9, _value9) | \ EFX_INSERT_FIELD_NATIVE64(_min, _max, _field10, _value10)) #define EFX_INSERT_FIELDS32(_min, _max, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, _field9, _value9, \ _field10, _value10) \ __CPU_TO_LE_32( \ EFX_INSERT_FIELD_NATIVE32(_min, _max, _field1, _value1) | \ EFX_INSERT_FIELD_NATIVE32(_min, _max, _field2, _value2) | \ EFX_INSERT_FIELD_NATIVE32(_min, _max, _field3, _value3) | \ EFX_INSERT_FIELD_NATIVE32(_min, _max, _field4, _value4) | \ EFX_INSERT_FIELD_NATIVE32(_min, _max, _field5, _value5) | \ EFX_INSERT_FIELD_NATIVE32(_min, _max, _field6, _value6) | \ EFX_INSERT_FIELD_NATIVE32(_min, _max, _field7, _value7) | \ EFX_INSERT_FIELD_NATIVE32(_min, _max, _field8, _value8) | \ EFX_INSERT_FIELD_NATIVE32(_min, _max, _field9, _value9) | \ EFX_INSERT_FIELD_NATIVE32(_min, _max, _field10, _value10)) #define EFX_INSERT_FIELDS16(_min, _max, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, _field9, _value9, \ _field10, _value10) \ __CPU_TO_LE_16( \ EFX_INSERT_FIELD_NATIVE16(_min, _max, _field1, _value1) | \ EFX_INSERT_FIELD_NATIVE16(_min, _max, _field2, _value2) | \ EFX_INSERT_FIELD_NATIVE16(_min, _max, _field3, _value3) | \ EFX_INSERT_FIELD_NATIVE16(_min, _max, _field4, _value4) | \ EFX_INSERT_FIELD_NATIVE16(_min, _max, _field5, _value5) | \ EFX_INSERT_FIELD_NATIVE16(_min, _max, _field6, _value6) | \ EFX_INSERT_FIELD_NATIVE16(_min, _max, _field7, _value7) | \ EFX_INSERT_FIELD_NATIVE16(_min, _max, _field8, _value8) | \ EFX_INSERT_FIELD_NATIVE16(_min, _max, _field9, _value9) | \ EFX_INSERT_FIELD_NATIVE16(_min, _max, _field10, _value10)) #define EFX_INSERT_FIELDS8(_min, _max, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, _field9, _value9, \ _field10, _value10) \ __NATIVE_8( \ EFX_INSERT_FIELD_NATIVE8(_min, _max, _field1, _value1) | \ EFX_INSERT_FIELD_NATIVE8(_min, _max, _field2, _value2) | \ EFX_INSERT_FIELD_NATIVE8(_min, _max, _field3, _value3) | \ EFX_INSERT_FIELD_NATIVE8(_min, _max, _field4, _value4) | \ EFX_INSERT_FIELD_NATIVE8(_min, _max, _field5, _value5) | \ EFX_INSERT_FIELD_NATIVE8(_min, _max, _field6, _value6) | \ EFX_INSERT_FIELD_NATIVE8(_min, _max, _field7, _value7) | \ EFX_INSERT_FIELD_NATIVE8(_min, _max, _field8, _value8) | \ EFX_INSERT_FIELD_NATIVE8(_min, _max, _field9, _value9) | \ EFX_INSERT_FIELD_NATIVE8(_min, _max, _field10, _value10)) #define EFX_POPULATE_OWORD64(_oword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, _field9, _value9, \ _field10, _value10) \ do { \ _NOTE(CONSTANTCONDITION) \ (_oword).eo_u64[0] = EFX_INSERT_FIELDS64(0, 63, \ _field1, _value1, _field2, _value2, \ _field3, _value3, _field4, _value4, \ _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, \ _field9, _value9, _field10, _value10); \ _NOTE(CONSTANTCONDITION) \ (_oword).eo_u64[1] = EFX_INSERT_FIELDS64(64, 127, \ _field1, _value1, _field2, _value2, \ _field3, _value3, _field4, _value4, \ _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, \ _field9, _value9, _field10, _value10); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_POPULATE_OWORD32(_oword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, _field9, _value9, \ _field10, _value10) \ do { \ _NOTE(CONSTANTCONDITION) \ (_oword).eo_u32[0] = EFX_INSERT_FIELDS32(0, 31, \ _field1, _value1, _field2, _value2, \ _field3, _value3, _field4, _value4, \ _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, \ _field9, _value9, _field10, _value10); \ _NOTE(CONSTANTCONDITION) \ (_oword).eo_u32[1] = EFX_INSERT_FIELDS32(32, 63, \ _field1, _value1, _field2, _value2, \ _field3, _value3, _field4, _value4, \ _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, \ _field9, _value9, _field10, _value10); \ _NOTE(CONSTANTCONDITION) \ (_oword).eo_u32[2] = EFX_INSERT_FIELDS32(64, 95, \ _field1, _value1, _field2, _value2, \ _field3, _value3, _field4, _value4, \ _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, \ _field9, _value9, _field10, _value10); \ _NOTE(CONSTANTCONDITION) \ (_oword).eo_u32[3] = EFX_INSERT_FIELDS32(96, 127, \ _field1, _value1, _field2, _value2, \ _field3, _value3, _field4, _value4, \ _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, \ _field9, _value9, _field10, _value10); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_POPULATE_QWORD64(_qword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, _field9, _value9, \ _field10, _value10) \ do { \ _NOTE(CONSTANTCONDITION) \ (_qword).eq_u64[0] = EFX_INSERT_FIELDS64(0, 63, \ _field1, _value1, _field2, _value2, \ _field3, _value3, _field4, _value4, \ _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, \ _field9, _value9, _field10, _value10); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_POPULATE_QWORD32(_qword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, _field9, _value9, \ _field10, _value10) \ do { \ _NOTE(CONSTANTCONDITION) \ (_qword).eq_u32[0] = EFX_INSERT_FIELDS32(0, 31, \ _field1, _value1, _field2, _value2, \ _field3, _value3, _field4, _value4, \ _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, \ _field9, _value9, _field10, _value10); \ _NOTE(CONSTANTCONDITION) \ (_qword).eq_u32[1] = EFX_INSERT_FIELDS32(32, 63, \ _field1, _value1, _field2, _value2, \ _field3, _value3, _field4, _value4, \ _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, \ _field9, _value9, _field10, _value10); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_POPULATE_DWORD(_dword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, _field9, _value9, \ _field10, _value10) \ do { \ _NOTE(CONSTANTCONDITION) \ (_dword).ed_u32[0] = EFX_INSERT_FIELDS32(0, 31, \ _field1, _value1, _field2, _value2, \ _field3, _value3, _field4, _value4, \ _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, \ _field9, _value9, _field10, _value10); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_POPULATE_WORD(_word, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, _field9, _value9, \ _field10, _value10) \ do { \ _NOTE(CONSTANTCONDITION) \ (_word).ew_u16[0] = EFX_INSERT_FIELDS16(0, 15, \ _field1, _value1, _field2, _value2, \ _field3, _value3, _field4, _value4, \ _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, \ _field9, _value9, _field10, _value10); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_POPULATE_BYTE(_byte, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, _field9, _value9, \ _field10, _value10) \ do { \ _NOTE(CONSTANTCONDITION) \ (_byte).eb_u8[0] = EFX_INSERT_FIELDS8(0, 7, \ _field1, _value1, _field2, _value2, \ _field3, _value3, _field4, _value4, \ _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, \ _field9, _value9, _field10, _value10); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) /* Populate an octword field with various numbers of arguments */ #define EFX_POPULATE_OWORD_10 EFX_POPULATE_OWORD #define EFX_POPULATE_OWORD_9(_oword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, _field9, _value9) \ EFX_POPULATE_OWORD_10(_oword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, _field9, _value9) #define EFX_POPULATE_OWORD_8(_oword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8) \ EFX_POPULATE_OWORD_9(_oword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8) #define EFX_POPULATE_OWORD_7(_oword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7) \ EFX_POPULATE_OWORD_8(_oword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7) #define EFX_POPULATE_OWORD_6(_oword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6) \ EFX_POPULATE_OWORD_7(_oword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6) #define EFX_POPULATE_OWORD_5(_oword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5) \ EFX_POPULATE_OWORD_6(_oword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5) #define EFX_POPULATE_OWORD_4(_oword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4) \ EFX_POPULATE_OWORD_5(_oword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4) #define EFX_POPULATE_OWORD_3(_oword, \ _field1, _value1, _field2, _value2, _field3, _value3) \ EFX_POPULATE_OWORD_4(_oword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3) #define EFX_POPULATE_OWORD_2(_oword, \ _field1, _value1, _field2, _value2) \ EFX_POPULATE_OWORD_3(_oword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2) #define EFX_POPULATE_OWORD_1(_oword, \ _field1, _value1) \ EFX_POPULATE_OWORD_2(_oword, EFX_DUMMY_FIELD, 0, \ _field1, _value1) #define EFX_ZERO_OWORD(_oword) \ EFX_POPULATE_OWORD_1(_oword, EFX_DUMMY_FIELD, 0) -#define EFX_SET_OWORD64(_oword) \ - EFX_POPULATE_OWORD_2(_oword, \ - EFX_QWORD_0, (uint64_t)-1, EFX_QWORD_1, (uint64_t)-1) - -#define EFX_SET_OWORD32(_oword) \ +#define EFX_SET_OWORD(_oword) \ EFX_POPULATE_OWORD_4(_oword, \ EFX_DWORD_0, 0xffffffff, EFX_DWORD_1, 0xffffffff, \ EFX_DWORD_2, 0xffffffff, EFX_DWORD_3, 0xffffffff) /* Populate a quadword field with various numbers of arguments */ #define EFX_POPULATE_QWORD_10 EFX_POPULATE_QWORD #define EFX_POPULATE_QWORD_9(_qword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, _field9, _value9) \ EFX_POPULATE_QWORD_10(_qword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, _field9, _value9) #define EFX_POPULATE_QWORD_8(_qword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8) \ EFX_POPULATE_QWORD_9(_qword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8) #define EFX_POPULATE_QWORD_7(_qword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7) \ EFX_POPULATE_QWORD_8(_qword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7) #define EFX_POPULATE_QWORD_6(_qword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6) \ EFX_POPULATE_QWORD_7(_qword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6) #define EFX_POPULATE_QWORD_5(_qword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5) \ EFX_POPULATE_QWORD_6(_qword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5) #define EFX_POPULATE_QWORD_4(_qword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4) \ EFX_POPULATE_QWORD_5(_qword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4) #define EFX_POPULATE_QWORD_3(_qword, \ _field1, _value1, _field2, _value2, _field3, _value3) \ EFX_POPULATE_QWORD_4(_qword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3) #define EFX_POPULATE_QWORD_2(_qword, \ _field1, _value1, _field2, _value2) \ EFX_POPULATE_QWORD_3(_qword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2) #define EFX_POPULATE_QWORD_1(_qword, \ _field1, _value1) \ EFX_POPULATE_QWORD_2(_qword, EFX_DUMMY_FIELD, 0, \ _field1, _value1) #define EFX_ZERO_QWORD(_qword) \ EFX_POPULATE_QWORD_1(_qword, EFX_DUMMY_FIELD, 0) -#define EFX_SET_QWORD64(_qword) \ - EFX_POPULATE_QWORD_1(_qword, \ - EFX_QWORD_0, (uint64_t)-1) - -#define EFX_SET_QWORD32(_qword) \ +#define EFX_SET_QWORD(_qword) \ EFX_POPULATE_QWORD_2(_qword, \ EFX_DWORD_0, 0xffffffff, EFX_DWORD_1, 0xffffffff) /* Populate a dword field with various numbers of arguments */ #define EFX_POPULATE_DWORD_10 EFX_POPULATE_DWORD #define EFX_POPULATE_DWORD_9(_dword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, _field9, _value9) \ EFX_POPULATE_DWORD_10(_dword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, _field9, _value9) #define EFX_POPULATE_DWORD_8(_dword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8) \ EFX_POPULATE_DWORD_9(_dword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8) #define EFX_POPULATE_DWORD_7(_dword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7) \ EFX_POPULATE_DWORD_8(_dword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7) #define EFX_POPULATE_DWORD_6(_dword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6) \ EFX_POPULATE_DWORD_7(_dword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6) #define EFX_POPULATE_DWORD_5(_dword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5) \ EFX_POPULATE_DWORD_6(_dword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5) #define EFX_POPULATE_DWORD_4(_dword, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4) \ EFX_POPULATE_DWORD_5(_dword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4) #define EFX_POPULATE_DWORD_3(_dword, \ _field1, _value1, _field2, _value2, _field3, _value3) \ EFX_POPULATE_DWORD_4(_dword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3) #define EFX_POPULATE_DWORD_2(_dword, \ _field1, _value1, _field2, _value2) \ EFX_POPULATE_DWORD_3(_dword, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2) #define EFX_POPULATE_DWORD_1(_dword, \ _field1, _value1) \ EFX_POPULATE_DWORD_2(_dword, EFX_DUMMY_FIELD, 0, \ _field1, _value1) #define EFX_ZERO_DWORD(_dword) \ EFX_POPULATE_DWORD_1(_dword, EFX_DUMMY_FIELD, 0) #define EFX_SET_DWORD(_dword) \ EFX_POPULATE_DWORD_1(_dword, \ EFX_DWORD_0, 0xffffffff) /* Populate a word field with various numbers of arguments */ #define EFX_POPULATE_WORD_10 EFX_POPULATE_WORD #define EFX_POPULATE_WORD_9(_word, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, _field9, _value9) \ EFX_POPULATE_WORD_10(_word, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, _field9, _value9) #define EFX_POPULATE_WORD_8(_word, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8) \ EFX_POPULATE_WORD_9(_word, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8) #define EFX_POPULATE_WORD_7(_word, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7) \ EFX_POPULATE_WORD_8(_word, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7) #define EFX_POPULATE_WORD_6(_word, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6) \ EFX_POPULATE_WORD_7(_word, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6) #define EFX_POPULATE_WORD_5(_word, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5) \ EFX_POPULATE_WORD_6(_word, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5) #define EFX_POPULATE_WORD_4(_word, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4) \ EFX_POPULATE_WORD_5(_word, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4) #define EFX_POPULATE_WORD_3(_word, \ _field1, _value1, _field2, _value2, _field3, _value3) \ EFX_POPULATE_WORD_4(_word, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3) #define EFX_POPULATE_WORD_2(_word, \ _field1, _value1, _field2, _value2) \ EFX_POPULATE_WORD_3(_word, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2) #define EFX_POPULATE_WORD_1(_word, \ _field1, _value1) \ EFX_POPULATE_WORD_2(_word, EFX_DUMMY_FIELD, 0, \ _field1, _value1) #define EFX_ZERO_WORD(_word) \ EFX_POPULATE_WORD_1(_word, EFX_DUMMY_FIELD, 0) #define EFX_SET_WORD(_word) \ EFX_POPULATE_WORD_1(_word, \ EFX_WORD_0, 0xffff) /* Populate a byte field with various numbers of arguments */ #define EFX_POPULATE_BYTE_10 EFX_POPULATE_BYTE #define EFX_POPULATE_BYTE_9(_byte, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, _field9, _value9) \ EFX_POPULATE_BYTE_10(_byte, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8, _field9, _value9) #define EFX_POPULATE_BYTE_8(_byte, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8) \ EFX_POPULATE_BYTE_9(_byte, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7, _field8, _value8) #define EFX_POPULATE_BYTE_7(_byte, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7) \ EFX_POPULATE_BYTE_8(_byte, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6, \ _field7, _value7) #define EFX_POPULATE_BYTE_6(_byte, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6) \ EFX_POPULATE_BYTE_7(_byte, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5, _field6, _value6) #define EFX_POPULATE_BYTE_5(_byte, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5) \ EFX_POPULATE_BYTE_6(_byte, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4, _field5, _value5) #define EFX_POPULATE_BYTE_4(_byte, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4) \ EFX_POPULATE_BYTE_5(_byte, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3, \ _field4, _value4) #define EFX_POPULATE_BYTE_3(_byte, \ _field1, _value1, _field2, _value2, _field3, _value3) \ EFX_POPULATE_BYTE_4(_byte, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2, _field3, _value3) #define EFX_POPULATE_BYTE_2(_byte, \ _field1, _value1, _field2, _value2) \ EFX_POPULATE_BYTE_3(_byte, EFX_DUMMY_FIELD, 0, \ _field1, _value1, _field2, _value2) #define EFX_POPULATE_BYTE_1(_byte, \ _field1, _value1) \ EFX_POPULATE_BYTE_2(_byte, EFX_DUMMY_FIELD, 0, \ _field1, _value1) #define EFX_ZERO_BYTE(_byte) \ EFX_POPULATE_BYTE_1(_byte, EFX_DUMMY_FIELD, 0) #define EFX_SET_BYTE(_byte) \ EFX_POPULATE_BYTE_1(_byte, \ EFX_BYTE_0, 0xff) /* * Modify a named field within an already-populated structure. Used * for read-modify-write operations. */ #define EFX_INSERT_FIELD64(_min, _max, _field, _value) \ __CPU_TO_LE_64(EFX_INSERT_FIELD_NATIVE64(_min, _max, _field, _value)) #define EFX_INSERT_FIELD32(_min, _max, _field, _value) \ __CPU_TO_LE_32(EFX_INSERT_FIELD_NATIVE32(_min, _max, _field, _value)) #define EFX_INSERT_FIELD16(_min, _max, _field, _value) \ __CPU_TO_LE_16(EFX_INSERT_FIELD_NATIVE16(_min, _max, _field, _value)) #define EFX_INSERT_FIELD8(_min, _max, _field, _value) \ __NATIVE_8(EFX_INSERT_FIELD_NATIVE8(_min, _max, _field, _value)) #define EFX_INPLACE_MASK64(_min, _max, _field) \ EFX_INSERT_FIELD64(_min, _max, _field, EFX_MASK64(_field)) #define EFX_INPLACE_MASK32(_min, _max, _field) \ EFX_INSERT_FIELD32(_min, _max, _field, EFX_MASK32(_field)) #define EFX_INPLACE_MASK16(_min, _max, _field) \ EFX_INSERT_FIELD16(_min, _max, _field, EFX_MASK16(_field)) #define EFX_INPLACE_MASK8(_min, _max, _field) \ EFX_INSERT_FIELD8(_min, _max, _field, EFX_MASK8(_field)) #define EFX_SET_OWORD_FIELD64(_oword, _field, _value) \ do { \ _NOTE(CONSTANTCONDITION) \ (_oword).eo_u64[0] = (((_oword).eo_u64[0] & \ ~EFX_INPLACE_MASK64(0, 63, _field)) | \ EFX_INSERT_FIELD64(0, 63, _field, _value)); \ _NOTE(CONSTANTCONDITION) \ (_oword).eo_u64[1] = (((_oword).eo_u64[1] & \ ~EFX_INPLACE_MASK64(64, 127, _field)) | \ EFX_INSERT_FIELD64(64, 127, _field, _value)); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_SET_OWORD_FIELD32(_oword, _field, _value) \ do { \ _NOTE(CONSTANTCONDITION) \ (_oword).eo_u32[0] = (((_oword).eo_u32[0] & \ ~EFX_INPLACE_MASK32(0, 31, _field)) | \ EFX_INSERT_FIELD32(0, 31, _field, _value)); \ _NOTE(CONSTANTCONDITION) \ (_oword).eo_u32[1] = (((_oword).eo_u32[1] & \ ~EFX_INPLACE_MASK32(32, 63, _field)) | \ EFX_INSERT_FIELD32(32, 63, _field, _value)); \ _NOTE(CONSTANTCONDITION) \ (_oword).eo_u32[2] = (((_oword).eo_u32[2] & \ ~EFX_INPLACE_MASK32(64, 95, _field)) | \ EFX_INSERT_FIELD32(64, 95, _field, _value)); \ _NOTE(CONSTANTCONDITION) \ (_oword).eo_u32[3] = (((_oword).eo_u32[3] & \ ~EFX_INPLACE_MASK32(96, 127, _field)) | \ EFX_INSERT_FIELD32(96, 127, _field, _value)); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_SET_QWORD_FIELD64(_qword, _field, _value) \ do { \ _NOTE(CONSTANTCONDITION) \ (_qword).eq_u64[0] = (((_qword).eq_u64[0] & \ ~EFX_INPLACE_MASK64(0, 63, _field)) | \ EFX_INSERT_FIELD64(0, 63, _field, _value)); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_SET_QWORD_FIELD32(_qword, _field, _value) \ do { \ _NOTE(CONSTANTCONDITION) \ (_qword).eq_u32[0] = (((_qword).eq_u32[0] & \ ~EFX_INPLACE_MASK32(0, 31, _field)) | \ EFX_INSERT_FIELD32(0, 31, _field, _value)); \ _NOTE(CONSTANTCONDITION) \ (_qword).eq_u32[1] = (((_qword).eq_u32[1] & \ ~EFX_INPLACE_MASK32(32, 63, _field)) | \ EFX_INSERT_FIELD32(32, 63, _field, _value)); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_SET_DWORD_FIELD(_dword, _field, _value) \ do { \ _NOTE(CONSTANTCONDITION) \ (_dword).ed_u32[0] = (((_dword).ed_u32[0] & \ ~EFX_INPLACE_MASK32(0, 31, _field)) | \ EFX_INSERT_FIELD32(0, 31, _field, _value)); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_SET_WORD_FIELD(_word, _field, _value) \ do { \ _NOTE(CONSTANTCONDITION) \ (_word).ew_u16[0] = (((_word).ew_u16[0] & \ ~EFX_INPLACE_MASK16(0, 15, _field)) | \ EFX_INSERT_FIELD16(0, 15, _field, _value)); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_SET_BYTE_FIELD(_byte, _field, _value) \ do { \ _NOTE(CONSTANTCONDITION) \ (_byte).eb_u8[0] = (((_byte).eb_u8[0] & \ ~EFX_INPLACE_MASK8(0, 7, _field)) | \ EFX_INSERT_FIELD8(0, 7, _field, _value)); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) /* * Set or clear a numbered bit within an octword. */ #define EFX_SHIFT64(_bit, _base) \ (((_bit) >= (_base) && (_bit) < (_base) + 64) ? \ ((uint64_t)1 << ((_bit) - (_base))) : \ 0U) #define EFX_SHIFT32(_bit, _base) \ (((_bit) >= (_base) && (_bit) < (_base) + 32) ? \ ((uint32_t)1 << ((_bit) - (_base))) : \ 0U) #define EFX_SHIFT16(_bit, _base) \ (((_bit) >= (_base) && (_bit) < (_base) + 16) ? \ (uint16_t)(1 << ((_bit) - (_base))) : \ 0U) #define EFX_SHIFT8(_bit, _base) \ (((_bit) >= (_base) && (_bit) < (_base) + 8) ? \ (uint8_t)(1 << ((_bit) - (_base))) : \ 0U) #define EFX_SET_OWORD_BIT64(_oword, _bit) \ do { \ _NOTE(CONSTANTCONDITION) \ (_oword).eo_u64[0] |= \ __CPU_TO_LE_64(EFX_SHIFT64(_bit, FIX_LINT(0))); \ (_oword).eo_u64[1] |= \ __CPU_TO_LE_64(EFX_SHIFT64(_bit, FIX_LINT(64))); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_SET_OWORD_BIT32(_oword, _bit) \ do { \ _NOTE(CONSTANTCONDITION) \ (_oword).eo_u32[0] |= \ __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(0))); \ (_oword).eo_u32[1] |= \ __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(32))); \ (_oword).eo_u32[2] |= \ __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(64))); \ (_oword).eo_u32[3] |= \ __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(96))); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_CLEAR_OWORD_BIT64(_oword, _bit) \ do { \ _NOTE(CONSTANTCONDITION) \ (_oword).eo_u64[0] &= \ __CPU_TO_LE_64(~EFX_SHIFT64(_bit, FIX_LINT(0))); \ (_oword).eo_u64[1] &= \ __CPU_TO_LE_64(~EFX_SHIFT64(_bit, FIX_LINT(64))); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_CLEAR_OWORD_BIT32(_oword, _bit) \ do { \ _NOTE(CONSTANTCONDITION) \ (_oword).eo_u32[0] &= \ __CPU_TO_LE_32(~EFX_SHIFT32(_bit, FIX_LINT(0))); \ (_oword).eo_u32[1] &= \ __CPU_TO_LE_32(~EFX_SHIFT32(_bit, FIX_LINT(32))); \ (_oword).eo_u32[2] &= \ __CPU_TO_LE_32(~EFX_SHIFT32(_bit, FIX_LINT(64))); \ (_oword).eo_u32[3] &= \ __CPU_TO_LE_32(~EFX_SHIFT32(_bit, FIX_LINT(96))); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) +#define EFX_TEST_OWORD_BIT64(_oword, _bit) \ + (((_oword).eo_u64[0] & \ + __CPU_TO_LE_64(EFX_SHIFT64(_bit, FIX_LINT(0)))) || \ + ((_oword).eo_u64[1] & \ + __CPU_TO_LE_64(EFX_SHIFT64(_bit, FIX_LINT(64))))) + +#define EFX_TEST_OWORD_BIT32(_oword, _bit) \ + (((_oword).eo_u32[0] & \ + __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(0)))) || \ + ((_oword).eo_u32[1] & \ + __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(32)))) || \ + ((_oword).eo_u32[2] & \ + __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(64)))) || \ + ((_oword).eo_u32[3] & \ + __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(96))))) + + #define EFX_SET_QWORD_BIT64(_qword, _bit) \ do { \ _NOTE(CONSTANTCONDITION) \ (_qword).eq_u64[0] |= \ __CPU_TO_LE_64(EFX_SHIFT64(_bit, FIX_LINT(0))); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_SET_QWORD_BIT32(_qword, _bit) \ do { \ _NOTE(CONSTANTCONDITION) \ (_qword).eq_u32[0] |= \ __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(0))); \ (_qword).eq_u32[1] |= \ __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(32))); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_CLEAR_QWORD_BIT64(_qword, _bit) \ do { \ _NOTE(CONSTANTCONDITION) \ (_qword).eq_u64[0] &= \ __CPU_TO_LE_64(~EFX_SHIFT64(_bit, FIX_LINT(0))); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_CLEAR_QWORD_BIT32(_qword, _bit) \ do { \ _NOTE(CONSTANTCONDITION) \ (_qword).eq_u32[0] &= \ __CPU_TO_LE_32(~EFX_SHIFT32(_bit, FIX_LINT(0))); \ (_qword).eq_u32[1] &= \ __CPU_TO_LE_32(~EFX_SHIFT32(_bit, FIX_LINT(32))); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) +#define EFX_TEST_QWORD_BIT64(_qword, _bit) \ + (((_qword).eq_u64[0] & \ + __CPU_TO_LE_64(EFX_SHIFT64(_bit, FIX_LINT(0)))) != 0) + +#define EFX_TEST_QWORD_BIT32(_qword, _bit) \ + (((_qword).eq_u32[0] & \ + __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(0)))) || \ + ((_qword).eq_u32[1] & \ + __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(32))))) + + #define EFX_SET_DWORD_BIT(_dword, _bit) \ do { \ (_dword).ed_u32[0] |= \ __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(0))); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_CLEAR_DWORD_BIT(_dword, _bit) \ do { \ (_dword).ed_u32[0] &= \ __CPU_TO_LE_32(~EFX_SHIFT32(_bit, FIX_LINT(0))); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) +#define EFX_TEST_DWORD_BIT(_dword, _bit) \ + (((_dword).ed_u32[0] & \ + __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(0)))) != 0) + + #define EFX_SET_WORD_BIT(_word, _bit) \ do { \ (_word).ew_u16[0] |= \ __CPU_TO_LE_16(EFX_SHIFT16(_bit, FIX_LINT(0))); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_CLEAR_WORD_BIT(_word, _bit) \ do { \ (_word).ew_u32[0] &= \ __CPU_TO_LE_16(~EFX_SHIFT16(_bit, FIX_LINT(0))); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) +#define EFX_TEST_WORD_BIT(_word, _bit) \ + (((_word).ew_u16[0] & \ + __CPU_TO_LE_16(EFX_SHIFT16(_bit, FIX_LINT(0)))) != 0) + + #define EFX_SET_BYTE_BIT(_byte, _bit) \ do { \ (_byte).eb_u8[0] |= \ __NATIVE_8(EFX_SHIFT8(_bit, FIX_LINT(0))); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_CLEAR_BYTE_BIT(_byte, _bit) \ do { \ (_byte).eb_u8[0] &= \ __NATIVE_8(~EFX_SHIFT8(_bit, FIX_LINT(0))); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) +#define EFX_TEST_BYTE_BIT(_byte, _bit) \ + (((_byte).eb_u8[0] & \ + __NATIVE_8(EFX_SHIFT8(_bit, FIX_LINT(0)))) != 0) + + #define EFX_OR_OWORD64(_oword1, _oword2) \ do { \ (_oword1).eo_u64[0] |= (_oword2).eo_u64[0]; \ (_oword1).eo_u64[1] |= (_oword2).eo_u64[1]; \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_OR_OWORD32(_oword1, _oword2) \ do { \ (_oword1).eo_u32[0] |= (_oword2).eo_u32[0]; \ (_oword1).eo_u32[1] |= (_oword2).eo_u32[1]; \ (_oword1).eo_u32[2] |= (_oword2).eo_u32[2]; \ (_oword1).eo_u32[3] |= (_oword2).eo_u32[3]; \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_AND_OWORD64(_oword1, _oword2) \ do { \ (_oword1).eo_u64[0] &= (_oword2).eo_u64[0]; \ (_oword1).eo_u64[1] &= (_oword2).eo_u64[1]; \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_AND_OWORD32(_oword1, _oword2) \ do { \ (_oword1).eo_u32[0] &= (_oword2).eo_u32[0]; \ (_oword1).eo_u32[1] &= (_oword2).eo_u32[1]; \ (_oword1).eo_u32[2] &= (_oword2).eo_u32[2]; \ (_oword1).eo_u32[3] &= (_oword2).eo_u32[3]; \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_OR_QWORD64(_qword1, _qword2) \ do { \ (_qword1).eq_u64[0] |= (_qword2).eq_u64[0]; \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_OR_QWORD32(_qword1, _qword2) \ do { \ (_qword1).eq_u32[0] |= (_qword2).eq_u32[0]; \ (_qword1).eq_u32[1] |= (_qword2).eq_u32[1]; \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_AND_QWORD64(_qword1, _qword2) \ do { \ (_qword1).eq_u64[0] &= (_qword2).eq_u64[0]; \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_AND_QWORD32(_qword1, _qword2) \ do { \ (_qword1).eq_u32[0] &= (_qword2).eq_u32[0]; \ (_qword1).eq_u32[1] &= (_qword2).eq_u32[1]; \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_OR_DWORD(_dword1, _dword2) \ do { \ (_dword1).ed_u32[0] |= (_dword2).ed_u32[0]; \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_AND_DWORD(_dword1, _dword2) \ do { \ (_dword1).ed_u32[0] &= (_dword2).ed_u32[0]; \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_OR_WORD(_word1, _word2) \ do { \ (_word1).ew_u16[0] |= (_word2).ew_u16[0]; \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_AND_WORD(_word1, _word2) \ do { \ (_word1).ew_u16[0] &= (_word2).ew_u16[0]; \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_OR_BYTE(_byte1, _byte2) \ do { \ (_byte1).eb_u8[0] &= (_byte2).eb_u8[0]; \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #define EFX_AND_BYTE(_byte1, _byte2) \ do { \ (_byte1).eb_u8[0] &= (_byte2).eb_u8[0]; \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) #if EFSYS_USE_UINT64 #define EFX_OWORD_FIELD EFX_OWORD_FIELD64 #define EFX_QWORD_FIELD EFX_QWORD_FIELD64 #define EFX_OWORD_IS_EQUAL EFX_OWORD_IS_EQUAL64 #define EFX_QWORD_IS_EQUAL EFX_QWORD_IS_EQUAL64 #define EFX_OWORD_IS_ZERO EFX_OWORD_IS_ZERO64 #define EFX_QWORD_IS_ZERO EFX_QWORD_IS_ZERO64 #define EFX_OWORD_IS_SET EFX_OWORD_IS_SET64 #define EFX_QWORD_IS_SET EFX_QWORD_IS_SET64 #define EFX_POPULATE_OWORD EFX_POPULATE_OWORD64 #define EFX_POPULATE_QWORD EFX_POPULATE_QWORD64 -#define EFX_SET_OWORD EFX_SET_OWORD64 -#define EFX_SET_QWORD EFX_SET_QWORD64 #define EFX_SET_OWORD_FIELD EFX_SET_OWORD_FIELD64 #define EFX_SET_QWORD_FIELD EFX_SET_QWORD_FIELD64 #define EFX_SET_OWORD_BIT EFX_SET_OWORD_BIT64 #define EFX_CLEAR_OWORD_BIT EFX_CLEAR_OWORD_BIT64 +#define EFX_TEST_OWORD_BIT EFX_TEST_OWORD_BIT64 #define EFX_SET_QWORD_BIT EFX_SET_QWORD_BIT64 #define EFX_CLEAR_QWORD_BIT EFX_CLEAR_QWORD_BIT64 +#define EFX_TEST_QWORD_BIT EFX_TEST_QWORD_BIT64 #define EFX_OR_OWORD EFX_OR_OWORD64 #define EFX_AND_OWORD EFX_AND_OWORD64 #define EFX_OR_QWORD EFX_OR_QWORD64 -#define EFX_AND_QWORD EFX_OR_QWORD64 +#define EFX_AND_QWORD EFX_AND_QWORD64 #else #define EFX_OWORD_FIELD EFX_OWORD_FIELD32 #define EFX_QWORD_FIELD EFX_QWORD_FIELD32 #define EFX_OWORD_IS_EQUAL EFX_OWORD_IS_EQUAL32 #define EFX_QWORD_IS_EQUAL EFX_QWORD_IS_EQUAL32 #define EFX_OWORD_IS_ZERO EFX_OWORD_IS_ZERO32 #define EFX_QWORD_IS_ZERO EFX_QWORD_IS_ZERO32 #define EFX_OWORD_IS_SET EFX_OWORD_IS_SET32 #define EFX_QWORD_IS_SET EFX_QWORD_IS_SET32 #define EFX_POPULATE_OWORD EFX_POPULATE_OWORD32 #define EFX_POPULATE_QWORD EFX_POPULATE_QWORD32 -#define EFX_SET_OWORD EFX_SET_OWORD32 -#define EFX_SET_QWORD EFX_SET_QWORD32 #define EFX_SET_OWORD_FIELD EFX_SET_OWORD_FIELD32 #define EFX_SET_QWORD_FIELD EFX_SET_QWORD_FIELD32 #define EFX_SET_OWORD_BIT EFX_SET_OWORD_BIT32 #define EFX_CLEAR_OWORD_BIT EFX_CLEAR_OWORD_BIT32 +#define EFX_TEST_OWORD_BIT EFX_TEST_OWORD_BIT32 #define EFX_SET_QWORD_BIT EFX_SET_QWORD_BIT32 #define EFX_CLEAR_QWORD_BIT EFX_CLEAR_QWORD_BIT32 +#define EFX_TEST_QWORD_BIT EFX_TEST_QWORD_BIT32 #define EFX_OR_OWORD EFX_OR_OWORD32 #define EFX_AND_OWORD EFX_AND_OWORD32 #define EFX_OR_QWORD EFX_OR_QWORD32 -#define EFX_AND_QWORD EFX_OR_QWORD32 +#define EFX_AND_QWORD EFX_AND_QWORD32 #endif #ifdef __cplusplus } #endif #endif /* _SYS_EFX_TYPES_H */ Property changes on: head/sys/dev/sfxge/common/efx_types.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_vpd.c =================================================================== --- head/sys/dev/sfxge/common/efx_vpd.c (revision 283513) +++ head/sys/dev/sfxge/common/efx_vpd.c (revision 283514) @@ -1,1002 +1,1030 @@ /*- - * Copyright 2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2009-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include "efsys.h" #include "efx.h" #include "efx_types.h" #include "efx_regs.h" #include "efx_impl.h" #if EFSYS_OPT_VPD #define TAG_TYPE_LBN 7 #define TAG_TYPE_WIDTH 1 #define TAG_TYPE_LARGE_ITEM_DECODE 1 #define TAG_TYPE_SMALL_ITEM_DECODE 0 #define TAG_SMALL_ITEM_NAME_LBN 3 #define TAG_SMALL_ITEM_NAME_WIDTH 4 #define TAG_SMALL_ITEM_SIZE_LBN 0 #define TAG_SMALL_ITEM_SIZE_WIDTH 3 #define TAG_LARGE_ITEM_NAME_LBN 0 #define TAG_LARGE_ITEM_NAME_WIDTH 7 #define TAG_NAME_END_DECODE 0x0f #define TAG_NAME_ID_STRING_DECODE 0x02 #define TAG_NAME_VPD_R_DECODE 0x10 #define TAG_NAME_VPD_W_DECODE 0x11 #if EFSYS_OPT_FALCON -static efx_vpd_ops_t __cs __efx_vpd_falcon_ops = { +static efx_vpd_ops_t __efx_vpd_falcon_ops = { NULL, /* evpdo_init */ falcon_vpd_size, /* evpdo_size */ falcon_vpd_read, /* evpdo_read */ falcon_vpd_verify, /* evpdo_verify */ NULL, /* evpdo_reinit */ falcon_vpd_get, /* evpdo_get */ falcon_vpd_set, /* evpdo_set */ falcon_vpd_next, /* evpdo_next */ falcon_vpd_write, /* evpdo_write */ NULL, /* evpdo_fini */ }; #endif /* EFSYS_OPT_FALCON */ #if EFSYS_OPT_SIENA -static efx_vpd_ops_t __cs __efx_vpd_siena_ops = { +static efx_vpd_ops_t __efx_vpd_siena_ops = { siena_vpd_init, /* evpdo_init */ siena_vpd_size, /* evpdo_size */ siena_vpd_read, /* evpdo_read */ siena_vpd_verify, /* evpdo_verify */ siena_vpd_reinit, /* evpdo_reinit */ siena_vpd_get, /* evpdo_get */ siena_vpd_set, /* evpdo_set */ siena_vpd_next, /* evpdo_next */ siena_vpd_write, /* evpdo_write */ siena_vpd_fini, /* evpdo_fini */ }; #endif /* EFSYS_OPT_SIENA */ +#if EFSYS_OPT_HUNTINGTON + +static efx_vpd_ops_t __efx_vpd_hunt_ops = { + hunt_vpd_init, /* evpdo_init */ + hunt_vpd_size, /* evpdo_size */ + hunt_vpd_read, /* evpdo_read */ + hunt_vpd_verify, /* evpdo_verify */ + hunt_vpd_reinit, /* evpdo_reinit */ + hunt_vpd_get, /* evpdo_get */ + hunt_vpd_set, /* evpdo_set */ + hunt_vpd_next, /* evpdo_next */ + hunt_vpd_write, /* evpdo_write */ + hunt_vpd_fini, /* evpdo_fini */ +}; + +#endif /* EFSYS_OPT_HUNTINGTON */ + __checkReturn int efx_vpd_init( __in efx_nic_t *enp) { efx_vpd_ops_t *evpdop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_VPD)); switch (enp->en_family) { #if EFSYS_OPT_FALCON case EFX_FAMILY_FALCON: evpdop = (efx_vpd_ops_t *)&__efx_vpd_falcon_ops; break; #endif /* EFSYS_OPT_FALCON */ #if EFSYS_OPT_SIENA case EFX_FAMILY_SIENA: evpdop = (efx_vpd_ops_t *)&__efx_vpd_siena_ops; break; #endif /* EFSYS_OPT_SIENA */ +#if EFSYS_OPT_HUNTINGTON + case EFX_FAMILY_HUNTINGTON: + evpdop = (efx_vpd_ops_t *)&__efx_vpd_hunt_ops; + break; +#endif /* EFSYS_OPT_HUNTINGTON */ + default: EFSYS_ASSERT(0); rc = ENOTSUP; goto fail1; } if (evpdop->evpdo_init != NULL) { if ((rc = evpdop->evpdo_init(enp)) != 0) goto fail2; } enp->en_evpdop = evpdop; enp->en_mod_flags |= EFX_MOD_VPD; return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_vpd_size( __in efx_nic_t *enp, __out size_t *sizep) { efx_vpd_ops_t *evpdop = enp->en_evpdop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_VPD); if ((rc = evpdop->evpdo_size(enp, sizep)) != 0) goto fail1; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_vpd_read( __in efx_nic_t *enp, __out_bcount(size) caddr_t data, __in size_t size) { efx_vpd_ops_t *evpdop = enp->en_evpdop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_VPD); if ((rc = evpdop->evpdo_read(enp, data, size)) != 0) goto fail1; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_vpd_verify( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size) { efx_vpd_ops_t *evpdop = enp->en_evpdop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_VPD); if ((rc = evpdop->evpdo_verify(enp, data, size)) != 0) goto fail1; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_vpd_reinit( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size) { efx_vpd_ops_t *evpdop = enp->en_evpdop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_VPD); if (evpdop->evpdo_reinit == NULL) { rc = ENOTSUP; goto fail1; } if ((rc = evpdop->evpdo_reinit(enp, data, size)) != 0) goto fail2; return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_vpd_get( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size, __inout efx_vpd_value_t *evvp) { efx_vpd_ops_t *evpdop = enp->en_evpdop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_VPD); if ((rc = evpdop->evpdo_get(enp, data, size, evvp)) != 0) goto fail1; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_vpd_set( __in efx_nic_t *enp, __inout_bcount(size) caddr_t data, __in size_t size, __in efx_vpd_value_t *evvp) { efx_vpd_ops_t *evpdop = enp->en_evpdop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_VPD); if ((rc = evpdop->evpdo_set(enp, data, size, evvp)) != 0) goto fail1; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_vpd_next( __in efx_nic_t *enp, __inout_bcount(size) caddr_t data, __in size_t size, __out efx_vpd_value_t *evvp, __inout unsigned int *contp) { efx_vpd_ops_t *evpdop = enp->en_evpdop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_VPD); if ((rc = evpdop->evpdo_next(enp, data, size, evvp, contp)) != 0) goto fail1; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_vpd_write( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size) { efx_vpd_ops_t *evpdop = enp->en_evpdop; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_VPD); if ((rc = evpdop->evpdo_write(enp, data, size)) != 0) goto fail1; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } static __checkReturn int efx_vpd_next_tag( __in caddr_t data, __in size_t size, __inout unsigned int *offsetp, __out efx_vpd_tag_t *tagp, __out uint16_t *lengthp) { efx_byte_t byte; efx_word_t word; uint8_t name; uint16_t length; size_t headlen; int rc; if (*offsetp >= size) { rc = EFAULT; goto fail1; } EFX_POPULATE_BYTE_1(byte, EFX_BYTE_0, data[*offsetp]); switch (EFX_BYTE_FIELD(byte, TAG_TYPE)) { case TAG_TYPE_SMALL_ITEM_DECODE: headlen = 1; name = EFX_BYTE_FIELD(byte, TAG_SMALL_ITEM_NAME); length = (uint16_t)EFX_BYTE_FIELD(byte, TAG_SMALL_ITEM_SIZE); break; case TAG_TYPE_LARGE_ITEM_DECODE: headlen = 3; if (*offsetp + headlen > size) { rc = EFAULT; goto fail2; } name = EFX_BYTE_FIELD(byte, TAG_LARGE_ITEM_NAME); EFX_POPULATE_WORD_2(word, EFX_BYTE_0, data[*offsetp + 1], EFX_BYTE_1, data[*offsetp + 2]); length = EFX_WORD_FIELD(word, EFX_WORD_0); break; default: rc = EFAULT; goto fail2; } if (*offsetp + headlen + length > size) { rc = EFAULT; goto fail3; } EFX_STATIC_ASSERT(TAG_NAME_END_DECODE == EFX_VPD_END); EFX_STATIC_ASSERT(TAG_NAME_ID_STRING_DECODE == EFX_VPD_ID); EFX_STATIC_ASSERT(TAG_NAME_VPD_R_DECODE == EFX_VPD_RO); EFX_STATIC_ASSERT(TAG_NAME_VPD_W_DECODE == EFX_VPD_RW); if (name != EFX_VPD_END && name != EFX_VPD_ID && name != EFX_VPD_RO) { rc = EFAULT; goto fail4; } *tagp = name; *lengthp = length; *offsetp += headlen; return (0); fail4: EFSYS_PROBE(fail4); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } static __checkReturn int efx_vpd_next_keyword( __in_bcount(size) caddr_t tag, __in size_t size, __in unsigned int pos, __out efx_vpd_keyword_t *keywordp, __out uint8_t *lengthp) { efx_vpd_keyword_t keyword; uint8_t length; int rc; if (pos + 3U > size) { rc = EFAULT; goto fail1; } keyword = EFX_VPD_KEYWORD(tag[pos], tag[pos + 1]); length = tag[pos + 2]; if (length == 0 || pos + 3U + length > size) { rc = EFAULT; goto fail2; } *keywordp = keyword; *lengthp = length; return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_vpd_hunk_length( __in_bcount(size) caddr_t data, __in size_t size, __out size_t *lengthp) { efx_vpd_tag_t tag; unsigned int offset; uint16_t taglen; int rc; offset = 0; _NOTE(CONSTANTCONDITION) while (1) { if ((rc = efx_vpd_next_tag(data, size, &offset, &tag, &taglen)) != 0) goto fail1; offset += taglen; if (tag == EFX_VPD_END) break; } *lengthp = offset; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_vpd_hunk_verify( __in_bcount(size) caddr_t data, __in size_t size, __out_opt boolean_t *cksummedp) { efx_vpd_tag_t tag; efx_vpd_keyword_t keyword; unsigned int offset; unsigned int pos; unsigned int i; uint16_t taglen; uint8_t keylen; uint8_t cksum; boolean_t cksummed = B_FALSE; int rc; /* * Parse every tag,keyword in the existing VPD. If the csum is present, * the assert it is correct, and is the final keyword in the RO block. */ offset = 0; _NOTE(CONSTANTCONDITION) while (1) { if ((rc = efx_vpd_next_tag(data, size, &offset, &tag, &taglen)) != 0) goto fail1; if (tag == EFX_VPD_END) break; else if (tag == EFX_VPD_ID) goto done; for (pos = 0; pos != taglen; pos += 3 + keylen) { /* RV keyword must be the last in the block */ if (cksummed) goto fail2; if ((rc = efx_vpd_next_keyword(data + offset, taglen, pos, &keyword, &keylen)) != 0) goto fail3; if (keyword == EFX_VPD_KEYWORD('R', 'V')) { cksum = 0; for (i = 0; i < offset + pos + 4; i++) cksum += data[i]; if (cksum != 0) { rc = EFAULT; goto fail4; } cksummed = B_TRUE; } } done: offset += taglen; } if (!cksummed) { rc = EFAULT; goto fail5; } if (cksummedp != NULL) *cksummedp = cksummed; return (0); fail5: EFSYS_PROBE(fail5); fail4: EFSYS_PROBE(fail4); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } -static uint8_t __cs __efx_vpd_blank_pid[] = { +static uint8_t __efx_vpd_blank_pid[] = { /* Large resource type ID length 1 */ 0x82, 0x01, 0x00, /* Product name ' ' */ 0x32, }; -static uint8_t __cs __efx_vpd_blank_r[] = { +static uint8_t __efx_vpd_blank_r[] = { /* Large resource type VPD-R length 4 */ 0x90, 0x04, 0x00, /* RV keyword length 1 */ 'R', 'V', 0x01, /* RV payload checksum */ 0x00, }; __checkReturn int efx_vpd_hunk_reinit( - __in caddr_t data, + __in_bcount(size) caddr_t data, __in size_t size, __in boolean_t wantpid) { unsigned int offset = 0; unsigned int pos; efx_byte_t byte; uint8_t cksum; int rc; if (size < 0x100) { rc = ENOSPC; goto fail1; } if (wantpid) { memcpy(data + offset, __efx_vpd_blank_pid, sizeof (__efx_vpd_blank_pid)); offset += sizeof (__efx_vpd_blank_pid); } memcpy(data + offset, __efx_vpd_blank_r, sizeof (__efx_vpd_blank_r)); offset += sizeof (__efx_vpd_blank_r); /* Update checksum */ cksum = 0; for (pos = 0; pos < offset; pos++) cksum += data[pos]; data[offset - 1] -= cksum; /* Append trailing tag */ EFX_POPULATE_BYTE_3(byte, TAG_TYPE, TAG_TYPE_SMALL_ITEM_DECODE, TAG_SMALL_ITEM_NAME, TAG_NAME_END_DECODE, TAG_SMALL_ITEM_SIZE, 0); data[offset] = EFX_BYTE_FIELD(byte, EFX_BYTE_0); offset++; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_vpd_hunk_next( __in_bcount(size) caddr_t data, __in size_t size, __out efx_vpd_tag_t *tagp, __out efx_vpd_keyword_t *keywordp, __out_bcount_opt(*paylenp) unsigned int *payloadp, __out_opt uint8_t *paylenp, __inout unsigned int *contp) { efx_vpd_tag_t tag; efx_vpd_keyword_t keyword = 0; unsigned int offset; unsigned int pos; unsigned int index; uint16_t taglen; uint8_t keylen; uint8_t paylen; int rc; offset = index = 0; _NOTE(CONSTANTCONDITION) while (1) { if ((rc = efx_vpd_next_tag(data, size, &offset, &tag, &taglen)) != 0) goto fail1; if (tag == EFX_VPD_END) break; if (tag == EFX_VPD_ID) { if (index == *contp) { EFSYS_ASSERT3U(taglen, <, 0x100); paylen = (uint8_t)MIN(taglen, 0xff); goto done; } } else { for (pos = 0; pos != taglen; pos += 3 + keylen) { if ((rc = efx_vpd_next_keyword(data + offset, taglen, pos, &keyword, &keylen)) != 0) goto fail2; if (index == *contp) { offset += pos + 3; paylen = keylen; goto done; } } } offset += taglen; } *contp = 0; return (0); done: *tagp = tag; *keywordp = keyword; if (payloadp != NULL) *payloadp = offset; if (paylenp != NULL) *paylenp = paylen; ++(*contp); return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_vpd_hunk_get( __in_bcount(size) caddr_t data, __in size_t size, __in efx_vpd_tag_t tag, __in efx_vpd_keyword_t keyword, __out unsigned int *payloadp, __out uint8_t *paylenp) { efx_vpd_tag_t itag; efx_vpd_keyword_t ikeyword; unsigned int offset; unsigned int pos; uint16_t taglen; uint8_t keylen; int rc; offset = 0; _NOTE(CONSTANTCONDITION) while (1) { if ((rc = efx_vpd_next_tag(data, size, &offset, &itag, &taglen)) != 0) goto fail1; if (itag == EFX_VPD_END) break; if (itag == tag) { if (itag == EFX_VPD_ID) { EFSYS_ASSERT3U(taglen, <, 0x100); *paylenp = (uint8_t)MIN(taglen, 0xff); *payloadp = offset; return (0); } for (pos = 0; pos != taglen; pos += 3 + keylen) { if ((rc = efx_vpd_next_keyword(data + offset, taglen, pos, &ikeyword, &keylen)) != 0) goto fail2; if (ikeyword == keyword) { *paylenp = keylen; *payloadp = offset + pos + 3; return (0); } } } offset += taglen; } /* Not an error */ return (ENOENT); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_vpd_hunk_set( __in_bcount(size) caddr_t data, __in size_t size, __in efx_vpd_value_t *evvp) { efx_word_t word; efx_vpd_tag_t tag; efx_vpd_keyword_t keyword; unsigned int offset; unsigned int pos; unsigned int taghead; unsigned int source; unsigned int dest; unsigned int i; uint16_t taglen; uint8_t keylen; uint8_t cksum; size_t used; int rc; switch (evvp->evv_tag) { case EFX_VPD_ID: if (evvp->evv_keyword != 0) { rc = EINVAL; goto fail1; } /* Can't delete the ID keyword */ if (evvp->evv_length == 0) { rc = EINVAL; goto fail1; } break; case EFX_VPD_RO: if (evvp->evv_keyword == EFX_VPD_KEYWORD('R', 'V')) { rc = EINVAL; goto fail1; } break; default: rc = EINVAL; goto fail1; } /* Determine total size of all current tags */ if ((rc = efx_vpd_hunk_length(data, size, &used)) != 0) goto fail2; offset = 0; _NOTE(CONSTANTCONDITION) while (1) { taghead = offset; if ((rc = efx_vpd_next_tag(data, size, &offset, &tag, &taglen)) != 0) goto fail3; if (tag == EFX_VPD_END) break; else if (tag != evvp->evv_tag) { offset += taglen; continue; } /* We only support modifying large resource tags */ if (offset - taghead != 3) { rc = EINVAL; goto fail4; } /* * Work out the offset of the byte immediately after the * old (=source) and new (=dest) new keyword/tag */ pos = 0; if (tag == EFX_VPD_ID) { source = offset + taglen; dest = offset + evvp->evv_length; goto check_space; } EFSYS_ASSERT3U(tag, ==, EFX_VPD_RO); source = dest = 0; for (pos = 0; pos != taglen; pos += 3 + keylen) { if ((rc = efx_vpd_next_keyword(data + offset, taglen, pos, &keyword, &keylen)) != 0) goto fail5; if (keyword == evvp->evv_keyword && evvp->evv_length == 0) { /* Deleting this keyword */ source = offset + pos + 3 + keylen; dest = offset + pos; break; } else if (keyword == evvp->evv_keyword) { /* Adjusting this keyword */ source = offset + pos + 3 + keylen; dest = offset + pos + 3 + evvp->evv_length; break; } else if (keyword == EFX_VPD_KEYWORD('R', 'V')) { /* The RV keyword must be at the end */ EFSYS_ASSERT3U(pos + 3 + keylen, ==, taglen); /* * The keyword doesn't already exist. If the * user deleting a non-existant keyword then * this is a no-op. */ if (evvp->evv_length == 0) return (0); /* Insert this keyword before the RV keyword */ source = offset + pos; dest = offset + pos + 3 + evvp->evv_length; break; } } check_space: if (used + dest > size + source) { rc = ENOSPC; goto fail6; } /* Move trailing data */ (void) memmove(data + dest, data + source, used - source); /* Copy contents */ memcpy(data + dest - evvp->evv_length, evvp->evv_value, evvp->evv_length); /* Insert new keyword header if required */ if (tag != EFX_VPD_ID && evvp->evv_length > 0) { EFX_POPULATE_WORD_1(word, EFX_WORD_0, evvp->evv_keyword); data[offset + pos + 0] = EFX_WORD_FIELD(word, EFX_BYTE_0); data[offset + pos + 1] = EFX_WORD_FIELD(word, EFX_BYTE_1); data[offset + pos + 2] = evvp->evv_length; } /* Modify tag length (large resource type) */ taglen += (dest - source); EFX_POPULATE_WORD_1(word, EFX_WORD_0, taglen); data[offset - 2] = EFX_WORD_FIELD(word, EFX_BYTE_0); data[offset - 1] = EFX_WORD_FIELD(word, EFX_BYTE_1); goto checksum; } /* Unable to find the matching tag */ rc = ENOENT; goto fail7; checksum: /* Find the RV tag, and update the checksum */ offset = 0; _NOTE(CONSTANTCONDITION) while (1) { if ((rc = efx_vpd_next_tag(data, size, &offset, &tag, &taglen)) != 0) goto fail8; if (tag == EFX_VPD_END) break; if (tag == EFX_VPD_RO) { for (pos = 0; pos != taglen; pos += 3 + keylen) { if ((rc = efx_vpd_next_keyword(data + offset, taglen, pos, &keyword, &keylen)) != 0) goto fail9; if (keyword == EFX_VPD_KEYWORD('R', 'V')) { cksum = 0; for (i = 0; i < offset + pos + 3; i++) cksum += data[i]; data[i] = -cksum; break; } } } offset += taglen; } /* Zero out the unused portion */ (void) memset(data + offset + taglen, 0xff, size - offset - taglen); return (0); fail9: EFSYS_PROBE(fail9); fail8: EFSYS_PROBE(fail8); fail7: EFSYS_PROBE(fail7); fail6: EFSYS_PROBE(fail6); fail5: EFSYS_PROBE(fail5); fail4: EFSYS_PROBE(fail4); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } void efx_vpd_fini( __in efx_nic_t *enp) { efx_vpd_ops_t *evpdop = enp->en_evpdop; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_VPD); if (evpdop->evpdo_fini != NULL) evpdop->evpdo_fini(enp); enp->en_evpdop = NULL; enp->en_mod_flags &= ~EFX_MOD_VPD; } #endif /* EFSYS_OPT_VPD */ Property changes on: head/sys/dev/sfxge/common/efx_vpd.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/efx_wol.c =================================================================== --- head/sys/dev/sfxge/common/efx_wol.c (revision 283513) +++ head/sys/dev/sfxge/common/efx_wol.c (revision 283514) @@ -1,399 +1,417 @@ /*- - * Copyright 2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2009-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include "efsys.h" #include "efx.h" #include "efx_types.h" #include "efx_impl.h" #if EFSYS_OPT_WOL __checkReturn int efx_wol_init( __in efx_nic_t *enp) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_WOL)); if (~(encp->enc_features) & EFX_FEATURE_WOL) { rc = ENOTSUP; goto fail1; } /* Current implementation is Siena specific */ EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); enp->en_mod_flags |= EFX_MOD_WOL; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_wol_filter_clear( __in efx_nic_t *enp) { efx_mcdi_req_t req; - uint8_t payload[MC_CMD_WOL_FILTER_RESET_IN_LEN]; + uint8_t payload[MAX(MC_CMD_WOL_FILTER_RESET_IN_LEN, + MC_CMD_WOL_FILTER_RESET_OUT_LEN)]; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_WOL); + (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_WOL_FILTER_RESET; req.emr_in_buf = payload; req.emr_in_length = MC_CMD_WOL_FILTER_RESET_IN_LEN; - req.emr_out_buf = NULL; - req.emr_out_length = 0; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_WOL_FILTER_RESET_OUT_LEN; MCDI_IN_SET_DWORD(req, WOL_FILTER_RESET_IN_MASK, MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS | MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS); efx_mcdi_execute(enp, &req); if (req.emr_rc != 0) { rc = req.emr_rc; goto fail1; } return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_wol_filter_add( __in efx_nic_t *enp, __in efx_wol_type_t type, __in efx_wol_param_t *paramp, __out uint32_t *filter_idp) { efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_WOL_FILTER_SET_IN_LEN, MC_CMD_WOL_FILTER_SET_OUT_LEN)]; efx_byte_t link_mask; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_WOL); + (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_WOL_FILTER_SET; - (void) memset(payload, '\0', sizeof (payload)); req.emr_in_buf = payload; req.emr_in_length = MC_CMD_WOL_FILTER_SET_IN_LEN; req.emr_out_buf = payload; req.emr_out_length = MC_CMD_WOL_FILTER_SET_OUT_LEN; switch (type) { case EFX_WOL_TYPE_MAGIC: MCDI_IN_SET_DWORD(req, WOL_FILTER_SET_IN_FILTER_MODE, MC_CMD_FILTER_MODE_SIMPLE); MCDI_IN_SET_DWORD(req, WOL_FILTER_SET_IN_WOL_TYPE, MC_CMD_WOL_TYPE_MAGIC); EFX_MAC_ADDR_COPY( MCDI_IN2(req, uint8_t, WOL_FILTER_SET_IN_MAGIC_MAC), paramp->ewp_magic.mac_addr); break; case EFX_WOL_TYPE_BITMAP: { uint32_t swapped = 0; efx_dword_t *dwordp; unsigned int pos, bit; MCDI_IN_SET_DWORD(req, WOL_FILTER_SET_IN_FILTER_MODE, MC_CMD_FILTER_MODE_SIMPLE); MCDI_IN_SET_DWORD(req, WOL_FILTER_SET_IN_WOL_TYPE, MC_CMD_WOL_TYPE_BITMAP); /* * MC bitmask is supposed to be bit swapped * amongst 32 bit words(!) */ dwordp = MCDI_IN2(req, efx_dword_t, WOL_FILTER_SET_IN_BITMAP_MASK); EFSYS_ASSERT3U(EFX_WOL_BITMAP_MASK_SIZE % 4, ==, 0); for (pos = 0; pos < EFX_WOL_BITMAP_MASK_SIZE; ++pos) { uint8_t native = paramp->ewp_bitmap.mask[pos]; for (bit = 0; bit < 8; ++bit) { swapped <<= 1; swapped |= (native & 0x1); native >>= 1; } if ((pos & 3) == 3) { EFX_POPULATE_DWORD_1(dwordp[pos >> 2], EFX_DWORD_0, swapped); swapped = 0; } } memcpy(MCDI_IN2(req, uint8_t, WOL_FILTER_SET_IN_BITMAP_BITMAP), paramp->ewp_bitmap.value, sizeof (paramp->ewp_bitmap.value)); EFSYS_ASSERT3U(paramp->ewp_bitmap.value_len, <=, sizeof (paramp->ewp_bitmap.value)); MCDI_IN_SET_DWORD(req, WOL_FILTER_SET_IN_BITMAP_LEN, paramp->ewp_bitmap.value_len); } break; case EFX_WOL_TYPE_LINK: MCDI_IN_SET_DWORD(req, WOL_FILTER_SET_IN_FILTER_MODE, MC_CMD_FILTER_MODE_SIMPLE); MCDI_IN_SET_DWORD(req, WOL_FILTER_SET_IN_WOL_TYPE, MC_CMD_WOL_TYPE_LINK); EFX_ZERO_BYTE(link_mask); EFX_SET_BYTE_FIELD(link_mask, MC_CMD_WOL_FILTER_SET_IN_LINK_UP, 1); MCDI_IN_SET_BYTE(req, WOL_FILTER_SET_IN_LINK_MASK, link_mask.eb_u8[0]); break; default: EFSYS_ASSERT3U(type, !=, type); } efx_mcdi_execute(enp, &req); if (req.emr_rc != 0) { rc = req.emr_rc; goto fail1; } if (req.emr_out_length_used < MC_CMD_WOL_FILTER_SET_OUT_LEN) { rc = EMSGSIZE; goto fail2; } *filter_idp = MCDI_OUT_DWORD(req, WOL_FILTER_SET_OUT_FILTER_ID); return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_wol_filter_remove( __in efx_nic_t *enp, __in uint32_t filter_id) { efx_mcdi_req_t req; - uint8_t payload[MC_CMD_WOL_FILTER_REMOVE_IN_LEN]; + uint8_t payload[MAX(MC_CMD_WOL_FILTER_REMOVE_IN_LEN, + MC_CMD_WOL_FILTER_REMOVE_OUT_LEN)]; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_WOL); + (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_WOL_FILTER_REMOVE; req.emr_in_buf = payload; req.emr_in_length = MC_CMD_WOL_FILTER_REMOVE_IN_LEN; - EFX_STATIC_ASSERT(MC_CMD_WOL_FILTER_REMOVE_OUT_LEN == 0); - req.emr_out_buf = NULL; - req.emr_out_length = 0; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_WOL_FILTER_REMOVE_OUT_LEN; MCDI_IN_SET_DWORD(req, WOL_FILTER_REMOVE_IN_FILTER_ID, filter_id); efx_mcdi_execute(enp, &req); if (req.emr_rc != 0) { rc = req.emr_rc; goto fail1; } return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_lightsout_offload_add( __in efx_nic_t *enp, __in efx_lightsout_offload_type_t type, __in efx_lightsout_offload_param_t *paramp, __out uint32_t *filter_idp) { efx_mcdi_req_t req; uint8_t payload[MAX(MAX(MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN, MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN), MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN)]; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_WOL); + (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_ADD_LIGHTSOUT_OFFLOAD; req.emr_in_buf = payload; req.emr_in_length = sizeof (type); req.emr_out_buf = payload; req.emr_out_length = MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN; switch (type) { case EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP: req.emr_in_length = MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN; + MCDI_IN_SET_DWORD(req, ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL, MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP); EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t, ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC), paramp->elop_arp.mac_addr); MCDI_IN_SET_DWORD(req, ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP, paramp->elop_arp.ip); break; case EFX_LIGHTSOUT_OFFLOAD_TYPE_NS: req.emr_in_length = MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN; + MCDI_IN_SET_DWORD(req, ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL, MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS); EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t, ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC), paramp->elop_ns.mac_addr); memcpy(MCDI_IN2(req, uint8_t, ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6), paramp->elop_ns.solicited_node, sizeof (paramp->elop_ns.solicited_node)); memcpy(MCDI_IN2(req, uint8_t, ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6), paramp->elop_ns.ip, sizeof (paramp->elop_ns.ip)); break; default: - EFSYS_ASSERT3U(type, !=, type); + rc = EINVAL; + goto fail1; } efx_mcdi_execute(enp, &req); if (req.emr_rc != 0) { rc = req.emr_rc; - goto fail1; + goto fail2; } if (req.emr_out_length_used < MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN) { rc = EMSGSIZE; - goto fail2; + goto fail3; } *filter_idp = MCDI_OUT_DWORD(req, ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID); return (0); +fail3: + EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int efx_lightsout_offload_remove( __in efx_nic_t *enp, __in efx_lightsout_offload_type_t type, __in uint32_t filter_id) { efx_mcdi_req_t req; - uint8_t payload[MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN]; + uint8_t payload[MAX(MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN, + MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN)]; int rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_WOL); + (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD; req.emr_in_buf = payload; - req.emr_in_length = sizeof (payload); - EFX_STATIC_ASSERT(MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN == 0); - req.emr_out_buf = NULL; - req.emr_out_length = 0; + req.emr_in_length = MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN; switch (type) { case EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP: MCDI_IN_SET_DWORD(req, REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL, MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP); break; case EFX_LIGHTSOUT_OFFLOAD_TYPE_NS: MCDI_IN_SET_DWORD(req, REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL, MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS); break; default: - EFSYS_ASSERT3U(type, !=, type); + rc = EINVAL; + goto fail1; } MCDI_IN_SET_DWORD(req, REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID, filter_id); efx_mcdi_execute(enp, &req); if (req.emr_rc != 0) { rc = req.emr_rc; - goto fail1; + goto fail2; } return (0); +fail2: + EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } void efx_wol_fini( __in efx_nic_t *enp) { EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_WOL); enp->en_mod_flags &= ~EFX_MOD_WOL; } #endif /* EFSYS_OPT_WOL */ Property changes on: head/sys/dev/sfxge/common/efx_wol.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/hunt_ev.c =================================================================== --- head/sys/dev/sfxge/common/hunt_ev.c (nonexistent) +++ head/sys/dev/sfxge/common/hunt_ev.c (revision 283514) @@ -0,0 +1,1010 @@ +/*- + * Copyright (c) 2012-2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "efsys.h" +#include "efx.h" +#include "efx_types.h" +#include "efx_regs.h" +#include "efx_impl.h" +#if EFSYS_OPT_MON_STATS +#include "mcdi_mon.h" +#endif + +#if EFSYS_OPT_HUNTINGTON + +#if EFSYS_OPT_QSTATS +#define EFX_EV_QSTAT_INCR(_eep, _stat) \ + do { \ + (_eep)->ee_stat[_stat]++; \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) +#else +#define EFX_EV_QSTAT_INCR(_eep, _stat) +#endif + + +static __checkReturn boolean_t +hunt_ev_rx( + __in efx_evq_t *eep, + __in efx_qword_t *eqp, + __in const efx_ev_callbacks_t *eecp, + __in_opt void *arg); + +static __checkReturn boolean_t +hunt_ev_tx( + __in efx_evq_t *eep, + __in efx_qword_t *eqp, + __in const efx_ev_callbacks_t *eecp, + __in_opt void *arg); + +static __checkReturn boolean_t +hunt_ev_driver( + __in efx_evq_t *eep, + __in efx_qword_t *eqp, + __in const efx_ev_callbacks_t *eecp, + __in_opt void *arg); + +static __checkReturn boolean_t +hunt_ev_drv_gen( + __in efx_evq_t *eep, + __in efx_qword_t *eqp, + __in const efx_ev_callbacks_t *eecp, + __in_opt void *arg); + +static __checkReturn boolean_t +hunt_ev_mcdi( + __in efx_evq_t *eep, + __in efx_qword_t *eqp, + __in const efx_ev_callbacks_t *eecp, + __in_opt void *arg); + + +static __checkReturn int +efx_mcdi_init_evq( + __in efx_nic_t *enp, + __in unsigned int instance, + __in efsys_mem_t *esmp, + __in size_t nevs, + __in uint32_t irq, + __out_opt uint32_t *irqp) +{ + efx_mcdi_req_t req; + uint8_t payload[ + MAX(MC_CMD_INIT_EVQ_IN_LEN(EFX_EVQ_NBUFS(EFX_EVQ_MAXNEVS)), + MC_CMD_INIT_EVQ_OUT_LEN)]; + efx_qword_t *dma_addr; + uint64_t addr; + int npages; + int i; + int supports_rx_batching; + int rc; + + npages = EFX_EVQ_NBUFS(nevs); + if (MC_CMD_INIT_EVQ_IN_LEN(npages) > MC_CMD_INIT_EVQ_IN_LENMAX) { + rc = EINVAL; + goto fail1; + } + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_INIT_EVQ; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_INIT_EVQ_IN_LEN(npages); + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_INIT_EVQ_OUT_LEN; + + MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_SIZE, nevs); + MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_INSTANCE, instance); + MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_IRQ_NUM, irq); + + /* + * On Huntington RX and TX event batching can only be requested + * together (even if the datapath firmware doesn't actually support RX + * batching). + * Cut through is incompatible with RX batching and so enabling cut + * through disables RX batching (but it does not affect TX batching). + * + * So always enable RX and TX event batching, and enable cut through + * if RX event batching isn't supported (i.e. on low latency firmware). + */ + supports_rx_batching = enp->en_nic_cfg.enc_rx_batching_enabled ? 1 : 0; + MCDI_IN_POPULATE_DWORD_6(req, INIT_EVQ_IN_FLAGS, + INIT_EVQ_IN_FLAG_INTERRUPTING, 1, + INIT_EVQ_IN_FLAG_RPTR_DOS, 0, + INIT_EVQ_IN_FLAG_INT_ARMD, 0, + INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_batching, + INIT_EVQ_IN_FLAG_RX_MERGE, 1, + INIT_EVQ_IN_FLAG_TX_MERGE, 1); + + MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE, + MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS); + MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, 0); + MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, 0); + + MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_MODE, + MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS); + MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_THRSHLD, 0); + + dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_IN_DMA_ADDR); + addr = EFSYS_MEM_ADDR(esmp); + + for (i = 0; i < npages; i++) { + EFX_POPULATE_QWORD_2(*dma_addr, + EFX_DWORD_1, (uint32_t)(addr >> 32), + EFX_DWORD_0, (uint32_t)(addr & 0xffffffff)); + + dma_addr++; + addr += EFX_BUF_SIZE; + } + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail2; + } + + if (req.emr_out_length_used < MC_CMD_INIT_EVQ_OUT_LEN) { + rc = EMSGSIZE; + goto fail3; + } + + if (irqp != NULL) + *irqp = MCDI_OUT_DWORD(req, INIT_EVQ_OUT_IRQ); + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static __checkReturn int +efx_mcdi_fini_evq( + __in efx_nic_t *enp, + __in uint32_t instance) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_FINI_EVQ_IN_LEN, + MC_CMD_FINI_EVQ_OUT_LEN)]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_FINI_EVQ; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_FINI_EVQ_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_FINI_EVQ_OUT_LEN; + + MCDI_IN_SET_DWORD(req, FINI_EVQ_IN_INSTANCE, instance); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + + + __checkReturn int +hunt_ev_init( + __in efx_nic_t *enp) +{ + _NOTE(ARGUNUSED(enp)) + return (0); +} + + void +hunt_ev_fini( + __in efx_nic_t *enp) +{ + _NOTE(ARGUNUSED(enp)) +} + + __checkReturn int +hunt_ev_qcreate( + __in efx_nic_t *enp, + __in unsigned int index, + __in efsys_mem_t *esmp, + __in size_t n, + __in uint32_t id, + __in efx_evq_t *eep) +{ + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + uint32_t irq; + int rc; + + _NOTE(ARGUNUSED(id)) /* buftbl id managed by MC */ + EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS)); + EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS)); + + if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) { + rc = EINVAL; + goto fail1; + } + + if (index >= encp->enc_evq_limit) { + rc = EINVAL; + goto fail2; + } + + /* Set up the handler table */ + eep->ee_rx = hunt_ev_rx; + eep->ee_tx = hunt_ev_tx; + eep->ee_driver = hunt_ev_driver; + eep->ee_drv_gen = hunt_ev_drv_gen; + eep->ee_mcdi = hunt_ev_mcdi; + + /* + * Set up the event queue + * NOTE: ignore the returned IRQ param as firmware does not set it. + */ + irq = index; /* INIT_EVQ expects function-relative vector number */ + if ((rc = efx_mcdi_init_evq(enp, index, esmp, n, irq, NULL)) != 0) + goto fail3; + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + void +hunt_ev_qdestroy( + __in efx_evq_t *eep) +{ + efx_nic_t *enp = eep->ee_enp; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + + (void) efx_mcdi_fini_evq(eep->ee_enp, eep->ee_index); +} + + __checkReturn int +hunt_ev_qprime( + __in efx_evq_t *eep, + __in unsigned int count) +{ + efx_nic_t *enp = eep->ee_enp; + uint32_t rptr; + efx_dword_t dword; + + rptr = count & eep->ee_mask; + + if (enp->en_nic_cfg.enc_bug35388_workaround) { + EFX_STATIC_ASSERT(EFX_EVQ_MINNEVS > + (1 << ERF_DD_EVQ_IND_RPTR_WIDTH)); + EFX_STATIC_ASSERT(EFX_EVQ_MAXNEVS < + (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH)); + + EFX_POPULATE_DWORD_2(dword, + ERF_DD_EVQ_IND_RPTR_FLAGS, + EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH, + ERF_DD_EVQ_IND_RPTR, + (rptr >> ERF_DD_EVQ_IND_RPTR_WIDTH)); + EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index, + &dword, B_FALSE); + + EFX_POPULATE_DWORD_2(dword, + ERF_DD_EVQ_IND_RPTR_FLAGS, + EFE_DD_EVQ_IND_RPTR_FLAGS_LOW, + ERF_DD_EVQ_IND_RPTR, + rptr & ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1)); + EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index, + &dword, B_FALSE); + } else { + EFX_POPULATE_DWORD_1(dword, ERF_DZ_EVQ_RPTR, rptr); + EFX_BAR_TBL_WRITED(enp, ER_DZ_EVQ_RPTR_REG, eep->ee_index, + &dword, B_FALSE); + } + + return (0); +} + +static __checkReturn int +efx_mcdi_driver_event( + __in efx_nic_t *enp, + __in uint32_t evq, + __in efx_qword_t data) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_DRIVER_EVENT_IN_LEN, + MC_CMD_DRIVER_EVENT_OUT_LEN)]; + int rc; + + req.emr_cmd = MC_CMD_DRIVER_EVENT; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_DRIVER_EVENT_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_DRIVER_EVENT_OUT_LEN; + + MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_EVQ, evq); + + MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_LO, + EFX_QWORD_FIELD(data, EFX_DWORD_0)); + MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_HI, + EFX_QWORD_FIELD(data, EFX_DWORD_1)); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + void +hunt_ev_qpost( + __in efx_evq_t *eep, + __in uint16_t data) +{ + efx_nic_t *enp = eep->ee_enp; + efx_qword_t event; + + EFX_POPULATE_QWORD_3(event, + ESF_DZ_DRV_CODE, ESE_DZ_EV_CODE_DRV_GEN_EV, + ESF_DZ_DRV_SUB_CODE, 0, + ESF_DZ_DRV_SUB_DATA_DW0, (uint32_t)data); + + (void) efx_mcdi_driver_event(enp, eep->ee_index, event); +} + + __checkReturn int +hunt_ev_qmoderate( + __in efx_evq_t *eep, + __in unsigned int us) +{ + efx_nic_t *enp = eep->ee_enp; + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + efx_dword_t dword; + uint32_t timer_val, mode; + int rc; + + if (us > encp->enc_evq_timer_max_us) { + rc = EINVAL; + goto fail1; + } + + /* If the value is zero then disable the timer */ + if (us == 0) { + timer_val = 0; + mode = FFE_CZ_TIMER_MODE_DIS; + } else { + /* Calculate the timer value in quanta */ + timer_val = us * 1000 / encp->enc_evq_timer_quantum_ns; + + /* Moderation value is base 0 so we need to deduct 1 */ + if (timer_val > 0) + timer_val--; + + mode = FFE_CZ_TIMER_MODE_INT_HLDOFF; + } + + if (encp->enc_bug35388_workaround) { + EFX_POPULATE_DWORD_3(dword, + ERF_DD_EVQ_IND_TIMER_FLAGS, + EFE_DD_EVQ_IND_TIMER_FLAGS, + ERF_DD_EVQ_IND_TIMER_MODE, mode, + ERF_DD_EVQ_IND_TIMER_VAL, timer_val); + EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT, + eep->ee_index, &dword, 0); + } else { + EFX_POPULATE_DWORD_2(dword, + FRF_CZ_TC_TIMER_MODE, mode, + FRF_CZ_TC_TIMER_VAL, timer_val); + EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0, + eep->ee_index, &dword, 0); + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + +#if EFSYS_OPT_QSTATS + void +hunt_ev_qstats_update( + __in efx_evq_t *eep, + __inout_ecount(EV_NQSTATS) efsys_stat_t *stat) +{ + /* + * TBD: Consider a common Siena/Huntington function. The code is + * essentially identical. + */ + unsigned int id; + + for (id = 0; id < EV_NQSTATS; id++) { + efsys_stat_t *essp = &stat[id]; + + EFSYS_STAT_INCR(essp, eep->ee_stat[id]); + eep->ee_stat[id] = 0; + } +} +#endif /* EFSYS_OPT_QSTATS */ + + +static __checkReturn boolean_t +hunt_ev_rx( + __in efx_evq_t *eep, + __in efx_qword_t *eqp, + __in const efx_ev_callbacks_t *eecp, + __in_opt void *arg) +{ + efx_nic_t *enp = eep->ee_enp; + uint32_t size; + boolean_t parse_err; + uint32_t label; + uint32_t mcast; + uint32_t eth_base_class; + uint32_t eth_tag_class; + uint32_t l3_class; + uint32_t l4_class; + uint32_t next_read_lbits; + boolean_t soft1, soft2; + uint16_t flags; + boolean_t should_abort; + efx_evq_rxq_state_t *eersp; + unsigned int desc_count; + unsigned int last_used_id; + + EFX_EV_QSTAT_INCR(eep, EV_RX); + + /* Discard events after RXQ/TXQ errors */ + if (enp->en_reset_flags & (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR)) + return (B_FALSE); + + /* + * FIXME: likely to be incomplete, incorrect and inefficient. + * Improvements in all three areas are required. + */ + + if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DROP_EVENT) != 0) { + /* Drop this event */ + return (B_FALSE); + } + flags = 0; + + size = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_BYTES); + + if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT) != 0) { + /* + * FIXME: There is not yet any driver that supports scatter on + * Huntington. Scatter support is required for OSX. + */ + EFSYS_ASSERT(0); + flags |= EFX_PKT_CONT; + } + + parse_err = (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE) != 0); + label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL); + + if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) { + /* Ethernet frame CRC bad */ + flags |= EFX_DISCARD; + } + if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CRC0_ERR) != 0) { + /* IP+TCP, bad CRC in iSCSI header */ + flags |= EFX_DISCARD; + } + if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CRC1_ERR) != 0) { + /* IP+TCP, bad CRC in iSCSI payload or FCoE or FCoIP */ + flags |= EFX_DISCARD; + } + if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECC_ERR) != 0) { + /* ECC memory error */ + flags |= EFX_DISCARD; + } + + /* FIXME: do we need soft bits from RXDP firmware ? */ + soft1 = (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_EV_SOFT1) != 0); + soft2 = (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_EV_SOFT2) != 0); + + mcast = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_MAC_CLASS); + if (mcast == ESE_DZ_MAC_CLASS_UCAST) + flags |= EFX_PKT_UNICAST; + + eth_base_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ETH_BASE_CLASS); + eth_tag_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ETH_TAG_CLASS); + l3_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L3_CLASS); + l4_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L4_CLASS); + + /* bottom 4 bits of incremented index (not last desc consumed) */ + next_read_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS); + + /* Increment the count of descriptors read */ + eersp = &eep->ee_rxq_state[label]; + desc_count = (next_read_lbits - eersp->eers_rx_read_ptr) & + EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS); + eersp->eers_rx_read_ptr += desc_count; + + /* + * FIXME: add error checking to make sure this a batched event. + * This could also be an aborted scatter, see Bug36629. + */ + if (desc_count > 1) { + EFX_EV_QSTAT_INCR(eep, EV_RX_BATCH); + flags |= EFX_PKT_PREFIX_LEN; + } + + /* Calculate the index of the the last descriptor consumed */ + last_used_id = (eersp->eers_rx_read_ptr - 1) & eersp->eers_rx_mask; + + /* EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_OVERRIDE_HOLDOFF); */ + + switch (eth_base_class) { + case ESE_DZ_ETH_BASE_CLASS_LLC_SNAP: + case ESE_DZ_ETH_BASE_CLASS_LLC: + case ESE_DZ_ETH_BASE_CLASS_ETH2: + default: + break; + } + + switch (eth_tag_class) { + case ESE_DZ_ETH_TAG_CLASS_RSVD7: + case ESE_DZ_ETH_TAG_CLASS_RSVD6: + case ESE_DZ_ETH_TAG_CLASS_RSVD5: + case ESE_DZ_ETH_TAG_CLASS_RSVD4: + break; + + case ESE_DZ_ETH_TAG_CLASS_RSVD3: /* Triple tagged */ + case ESE_DZ_ETH_TAG_CLASS_VLAN2: /* Double tagged */ + case ESE_DZ_ETH_TAG_CLASS_VLAN1: /* VLAN tagged */ + flags |= EFX_PKT_VLAN_TAGGED; + break; + + case ESE_DZ_ETH_TAG_CLASS_NONE: + default: + break; + } + + switch (l3_class) { + case ESE_DZ_L3_CLASS_RSVD7: /* Used by firmware for packet overrun */ + parse_err = B_TRUE; + flags |= EFX_DISCARD; + break; + + case ESE_DZ_L3_CLASS_ARP: + case ESE_DZ_L3_CLASS_FCOE: + break; + + case ESE_DZ_L3_CLASS_IP6_FRAG: + case ESE_DZ_L3_CLASS_IP6: + flags |= EFX_PKT_IPV6; + break; + + case ESE_DZ_L3_CLASS_IP4_FRAG: + case ESE_DZ_L3_CLASS_IP4: + flags |= EFX_PKT_IPV4; + if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR) == 0) + flags |= EFX_CKSUM_IPV4; + break; + + case ESE_DZ_L3_CLASS_UNKNOWN: + default: + break; + } + + switch (l4_class) { + case ESE_DZ_L4_CLASS_RSVD7: + case ESE_DZ_L4_CLASS_RSVD6: + case ESE_DZ_L4_CLASS_RSVD5: + case ESE_DZ_L4_CLASS_RSVD4: + case ESE_DZ_L4_CLASS_RSVD3: + break; + + case ESE_DZ_L4_CLASS_UDP: + flags |= EFX_PKT_UDP; + if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR) == 0) + flags |= EFX_CKSUM_TCPUDP; + break; + + case ESE_DZ_L4_CLASS_TCP: + flags |= EFX_PKT_TCP; + if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR) == 0) + flags |= EFX_CKSUM_TCPUDP; + break; + + case ESE_DZ_L4_CLASS_UNKNOWN: + default: + break; + } + + /* If we're not discarding the packet then it is ok */ + if (~flags & EFX_DISCARD) + EFX_EV_QSTAT_INCR(eep, EV_RX_OK); + + EFSYS_ASSERT(eecp->eec_rx != NULL); + should_abort = eecp->eec_rx(arg, label, last_used_id, size, flags); + + return (should_abort); +} + +static __checkReturn boolean_t +hunt_ev_tx( + __in efx_evq_t *eep, + __in efx_qword_t *eqp, + __in const efx_ev_callbacks_t *eecp, + __in_opt void *arg) +{ + efx_nic_t *enp = eep->ee_enp; + uint32_t id; + uint32_t label; + boolean_t should_abort; + + EFX_EV_QSTAT_INCR(eep, EV_TX); + + /* Discard events after RXQ/TXQ errors */ + if (enp->en_reset_flags & (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR)) + return (B_FALSE); + + if (EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DROP_EVENT) != 0) { + /* Drop this event */ + return (B_FALSE); + } + + /* Per-packet TX completion (was per-descriptor for Falcon/Siena) */ + id = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DESCR_INDX); + label = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_QLABEL); + + EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id); + + EFSYS_ASSERT(eecp->eec_tx != NULL); + should_abort = eecp->eec_tx(arg, label, id); + + return (should_abort); +} + +static __checkReturn boolean_t +hunt_ev_driver( + __in efx_evq_t *eep, + __in efx_qword_t *eqp, + __in const efx_ev_callbacks_t *eecp, + __in_opt void *arg) +{ + unsigned int code; + boolean_t should_abort; + + EFX_EV_QSTAT_INCR(eep, EV_DRIVER); + should_abort = B_FALSE; + + code = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_CODE); + switch (code) { + case ESE_DZ_DRV_TIMER_EV: { + uint32_t id; + + id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_TMR_ID); + + EFSYS_ASSERT(eecp->eec_timer != NULL); + should_abort = eecp->eec_timer(arg, id); + break; + } + + case ESE_DZ_DRV_WAKE_UP_EV: { + uint32_t id; + + id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_EVQ_ID); + + EFSYS_ASSERT(eecp->eec_wake_up != NULL); + should_abort = eecp->eec_wake_up(arg, id); + break; + } + + case ESE_DZ_DRV_START_UP_EV: + EFSYS_ASSERT(eecp->eec_initialized != NULL); + should_abort = eecp->eec_initialized(arg); + break; + + default: + EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index, + uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1), + uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0)); + break; + } + + return (should_abort); +} + +static __checkReturn boolean_t +hunt_ev_drv_gen( + __in efx_evq_t *eep, + __in efx_qword_t *eqp, + __in const efx_ev_callbacks_t *eecp, + __in_opt void *arg) +{ + uint32_t data; + boolean_t should_abort; + + EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN); + should_abort = B_FALSE; + + data = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_DATA_DW0); + if (data >= ((uint32_t)1 << 16)) { + EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index, + uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1), + uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0)); + + return (B_TRUE); + } + + EFSYS_ASSERT(eecp->eec_software != NULL); + should_abort = eecp->eec_software(arg, (uint16_t)data); + + return (should_abort); +} + +static __checkReturn boolean_t +hunt_ev_mcdi( + __in efx_evq_t *eep, + __in efx_qword_t *eqp, + __in const efx_ev_callbacks_t *eecp, + __in_opt void *arg) +{ + efx_nic_t *enp = eep->ee_enp; + unsigned code; + boolean_t should_abort = B_FALSE; + + EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE); + + code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE); + switch (code) { + case MCDI_EVENT_CODE_BADSSERT: + efx_mcdi_ev_death(enp, EINTR); + break; + + case MCDI_EVENT_CODE_CMDDONE: + efx_mcdi_ev_cpl(enp, + MCDI_EV_FIELD(eqp, CMDDONE_SEQ), + MCDI_EV_FIELD(eqp, CMDDONE_DATALEN), + MCDI_EV_FIELD(eqp, CMDDONE_ERRNO)); + break; + + case MCDI_EVENT_CODE_LINKCHANGE: { + efx_link_mode_t link_mode; + + hunt_phy_link_ev(enp, eqp, &link_mode); + should_abort = eecp->eec_link_change(arg, link_mode); + break; + } + + case MCDI_EVENT_CODE_SENSOREVT: { +#if EFSYS_OPT_MON_STATS + efx_mon_stat_t id; + efx_mon_stat_value_t value; + int rc; + + /* Decode monitor stat for MCDI sensor (if supported) */ + if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) { + /* Report monitor stat change */ + should_abort = eecp->eec_monitor(arg, id, value); + } else if (rc == ENOTSUP) { + should_abort = eecp->eec_exception(arg, + EFX_EXCEPTION_UNKNOWN_SENSOREVT, + MCDI_EV_FIELD(eqp, DATA)); + } else { + EFSYS_ASSERT(rc == ENODEV); /* Wrong port */ + } +#endif + break; + } + + case MCDI_EVENT_CODE_SCHEDERR: + /* Informational only */ + break; + + case MCDI_EVENT_CODE_REBOOT: + /* Falcon/Siena only (should not been seen with Huntington). */ + efx_mcdi_ev_death(enp, EIO); + break; + + case MCDI_EVENT_CODE_MC_REBOOT: + /* MC_REBOOT event is used for Huntington (EF10) and later. */ + efx_mcdi_ev_death(enp, EIO); + break; + + case MCDI_EVENT_CODE_MAC_STATS_DMA: +#if EFSYS_OPT_MAC_STATS + if (eecp->eec_mac_stats != NULL) { + eecp->eec_mac_stats(arg, + MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION)); + } +#endif + break; + + case MCDI_EVENT_CODE_FWALERT: { + uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON); + + if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS) + should_abort = eecp->eec_exception(arg, + EFX_EXCEPTION_FWALERT_SRAM, + MCDI_EV_FIELD(eqp, FWALERT_DATA)); + else + should_abort = eecp->eec_exception(arg, + EFX_EXCEPTION_UNKNOWN_FWALERT, + MCDI_EV_FIELD(eqp, DATA)); + break; + } + + case MCDI_EVENT_CODE_TX_ERR: { + /* + * After a TXQ error is detected, firmware sends a TX_ERR event. + * This may be followed by TX completions (which we discard), + * and then finally by a TX_FLUSH event. Firmware destroys the + * TXQ automatically after sending the TX_FLUSH event. + */ + enp->en_reset_flags |= EFX_RESET_TXQ_ERR; + + EFSYS_PROBE1(tx_descq_err, uint32_t, MCDI_EV_FIELD(eqp, DATA)); + + /* Inform the driver that a reset is required. */ + eecp->eec_exception(arg, EFX_EXCEPTION_TX_ERROR, + MCDI_EV_FIELD(eqp, TX_ERR_DATA)); + break; + } + + case MCDI_EVENT_CODE_TX_FLUSH: { + uint32_t txq_index = MCDI_EV_FIELD(eqp, TX_FLUSH_TXQ); + + /* + * EF10 firmware sends two TX_FLUSH events: one to the txq's + * event queue, and one to evq 0 (with TX_FLUSH_TO_DRIVER set). + * We want to wait for all completions, so ignore the events + * with TX_FLUSH_TO_DRIVER. + */ + if (MCDI_EV_FIELD(eqp, TX_FLUSH_TO_DRIVER) != 0) { + should_abort = B_FALSE; + break; + } + + EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE); + + EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index); + + EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL); + should_abort = eecp->eec_txq_flush_done(arg, txq_index); + break; + } + + case MCDI_EVENT_CODE_RX_ERR: { + /* + * After an RXQ error is detected, firmware sends an RX_ERR + * event. This may be followed by RX events (which we discard), + * and then finally by an RX_FLUSH event. Firmware destroys the + * RXQ automatically after sending the RX_FLUSH event. + */ + enp->en_reset_flags |= EFX_RESET_RXQ_ERR; + + EFSYS_PROBE1(rx_descq_err, uint32_t, MCDI_EV_FIELD(eqp, DATA)); + + /* Inform the driver that a reset is required. */ + eecp->eec_exception(arg, EFX_EXCEPTION_RX_ERROR, + MCDI_EV_FIELD(eqp, RX_ERR_DATA)); + break; + } + + case MCDI_EVENT_CODE_RX_FLUSH: { + uint32_t rxq_index = MCDI_EV_FIELD(eqp, RX_FLUSH_RXQ); + + /* + * EF10 firmware sends two RX_FLUSH events: one to the rxq's + * event queue, and one to evq 0 (with RX_FLUSH_TO_DRIVER set). + * We want to wait for all completions, so ignore the events + * with RX_FLUSH_TO_DRIVER. + */ + if (MCDI_EV_FIELD(eqp, RX_FLUSH_TO_DRIVER) != 0) { + should_abort = B_FALSE; + break; + } + + EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE); + + EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index); + + EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL); + should_abort = eecp->eec_rxq_flush_done(arg, rxq_index); + break; + } + + default: + EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index, + uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1), + uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0)); + break; + } + + return (should_abort); +} + + void +hunt_ev_rxlabel_init( + __in efx_evq_t *eep, + __in efx_rxq_t *erp, + __in unsigned int label) +{ + efx_evq_rxq_state_t *eersp; + + EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state)); + eersp = &eep->ee_rxq_state[label]; + + EFSYS_ASSERT3U(eersp->eers_rx_mask, ==, 0); + + eersp->eers_rx_read_ptr = 0; + eersp->eers_rx_mask = erp->er_mask; +} + + void +hunt_ev_rxlabel_fini( + __in efx_evq_t *eep, + __in unsigned int label) +{ + efx_evq_rxq_state_t *eersp; + + EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state)); + eersp = &eep->ee_rxq_state[label]; + + EFSYS_ASSERT3U(eersp->eers_rx_mask, !=, 0); + + eersp->eers_rx_read_ptr = 0; + eersp->eers_rx_mask = 0; +} + +#endif /* EFSYS_OPT_HUNTINGTON */ Property changes on: head/sys/dev/sfxge/common/hunt_ev.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/hunt_filter.c =================================================================== --- head/sys/dev/sfxge/common/hunt_filter.c (nonexistent) +++ head/sys/dev/sfxge/common/hunt_filter.c (revision 283514) @@ -0,0 +1,1376 @@ +/*- + * Copyright (c) 2007-2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "efsys.h" +#include "efx.h" +#include "efx_types.h" +#include "efx_regs_mcdi.h" +#include "efx_impl.h" + +#if EFSYS_OPT_HUNTINGTON + +#if EFSYS_OPT_FILTER + +#define HFE_SPEC(hftp, index) ((hftp)->hft_entry[(index)].hfe_spec) + +static efx_filter_spec_t * +hunt_filter_entry_spec( + __in const hunt_filter_table_t *hftp, + __in unsigned int index) +{ + return ((efx_filter_spec_t *)(HFE_SPEC(hftp, index) & + ~(uintptr_t)EFX_HUNT_FILTER_FLAGS)); +} + +static boolean_t +hunt_filter_entry_is_busy( + __in const hunt_filter_table_t *hftp, + __in unsigned int index) +{ + if (HFE_SPEC(hftp, index) & EFX_HUNT_FILTER_FLAG_BUSY) + return (B_TRUE); + else + return (B_FALSE); +} + +static boolean_t +hunt_filter_entry_is_auto_old( + __in const hunt_filter_table_t *hftp, + __in unsigned int index) +{ + if (HFE_SPEC(hftp, index) & EFX_HUNT_FILTER_FLAG_AUTO_OLD) + return (B_TRUE); + else + return (B_FALSE); +} + +static void +hunt_filter_set_entry( + __inout hunt_filter_table_t *hftp, + __in unsigned int index, + __in_opt const efx_filter_spec_t *efsp) +{ + HFE_SPEC(hftp, index) = (uintptr_t)efsp; +} + +static void +hunt_filter_set_entry_busy( + __inout hunt_filter_table_t *hftp, + __in unsigned int index) +{ + HFE_SPEC(hftp, index) |= (uintptr_t)EFX_HUNT_FILTER_FLAG_BUSY; +} + +static void +hunt_filter_set_entry_not_busy( + __inout hunt_filter_table_t *hftp, + __in unsigned int index) +{ + HFE_SPEC(hftp, index) &= ~(uintptr_t)EFX_HUNT_FILTER_FLAG_BUSY; +} + +static void +hunt_filter_set_entry_auto_old( + __inout hunt_filter_table_t *hftp, + __in unsigned int index) +{ + EFSYS_ASSERT(hunt_filter_entry_spec(hftp, index) != NULL); + HFE_SPEC(hftp, index) |= (uintptr_t)EFX_HUNT_FILTER_FLAG_AUTO_OLD; +} + +static void +hunt_filter_set_entry_not_auto_old( + __inout hunt_filter_table_t *hftp, + __in unsigned int index) +{ + HFE_SPEC(hftp, index) &= ~(uintptr_t)EFX_HUNT_FILTER_FLAG_AUTO_OLD; + EFSYS_ASSERT(hunt_filter_entry_spec(hftp, index) != NULL); +} + + __checkReturn int +hunt_filter_init( + __in efx_nic_t *enp) +{ + int rc; + hunt_filter_table_t *hftp; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + +#define MATCH_MASK(match) (EFX_MASK32(match) << EFX_LOW_BIT(match)) + EFX_STATIC_ASSERT(EFX_FILTER_MATCH_REM_HOST == + MATCH_MASK(MC_CMD_FILTER_OP_IN_MATCH_SRC_IP)); + EFX_STATIC_ASSERT(EFX_FILTER_MATCH_LOC_HOST == + MATCH_MASK(MC_CMD_FILTER_OP_IN_MATCH_DST_IP)); + EFX_STATIC_ASSERT(EFX_FILTER_MATCH_REM_MAC == + MATCH_MASK(MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC)); + EFX_STATIC_ASSERT(EFX_FILTER_MATCH_REM_PORT == + MATCH_MASK(MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT)); + EFX_STATIC_ASSERT(EFX_FILTER_MATCH_LOC_MAC == + MATCH_MASK(MC_CMD_FILTER_OP_IN_MATCH_DST_MAC)); + EFX_STATIC_ASSERT(EFX_FILTER_MATCH_LOC_PORT == + MATCH_MASK(MC_CMD_FILTER_OP_IN_MATCH_DST_PORT)); + EFX_STATIC_ASSERT(EFX_FILTER_MATCH_ETHER_TYPE == + MATCH_MASK(MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE)); + EFX_STATIC_ASSERT(EFX_FILTER_MATCH_INNER_VID == + MATCH_MASK(MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN)); + EFX_STATIC_ASSERT(EFX_FILTER_MATCH_OUTER_VID == + MATCH_MASK(MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN)); + EFX_STATIC_ASSERT(EFX_FILTER_MATCH_IP_PROTO == + MATCH_MASK(MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO)); +#undef MATCH_MASK + + EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (hunt_filter_table_t), hftp); + + if (!hftp) { + rc = ENOMEM; + goto fail1; + } + + enp->en_filter.ef_hunt_filter_table = hftp; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + void +hunt_filter_fini( + __in efx_nic_t *enp) +{ + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + + if (enp->en_filter.ef_hunt_filter_table != NULL) { + EFSYS_KMEM_FREE(enp->en_esip, sizeof (hunt_filter_table_t), + enp->en_filter.ef_hunt_filter_table); + } +} + +static __checkReturn int +efx_mcdi_filter_op_add( + __in efx_nic_t *enp, + __in efx_filter_spec_t *spec, + __in unsigned int filter_op, + __inout hunt_filter_handle_t *handle) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_FILTER_OP_IN_LEN, + MC_CMD_FILTER_OP_OUT_LEN)]; + uint32_t match_fields = 0; + int rc; + + memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_FILTER_OP; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_FILTER_OP_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_FILTER_OP_OUT_LEN; + + switch (filter_op) { + case MC_CMD_FILTER_OP_IN_OP_REPLACE: + MCDI_IN_SET_DWORD(req, FILTER_OP_IN_HANDLE_LO, + handle->hfh_lo); + MCDI_IN_SET_DWORD(req, FILTER_OP_IN_HANDLE_HI, + handle->hfh_hi); + /* Fall through */ + case MC_CMD_FILTER_OP_IN_OP_INSERT: + case MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE: + MCDI_IN_SET_DWORD(req, FILTER_OP_IN_OP, filter_op); + break; + default: + EFSYS_ASSERT(0); + rc = EINVAL; + goto fail1; + } + + if (spec->efs_match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) { + /* + * The LOC_MAC_IG match flag can represent unknown unicast + * or multicast filters - use the MAC address to distinguish + * them. + */ + if (EFX_MAC_ADDR_IS_MULTICAST(spec->efs_loc_mac)) + match_fields |= 1U << + MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN; + else + match_fields |= 1U << + MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN; + } + + match_fields |= spec->efs_match_flags & (~EFX_FILTER_MATCH_LOC_MAC_IG); + + MCDI_IN_SET_DWORD(req, FILTER_OP_IN_PORT_ID, + EVB_PORT_ID_ASSIGNED); + MCDI_IN_SET_DWORD(req, FILTER_OP_IN_MATCH_FIELDS, + match_fields); + MCDI_IN_SET_DWORD(req, FILTER_OP_IN_RX_DEST, + MC_CMD_FILTER_OP_IN_RX_DEST_HOST); + MCDI_IN_SET_DWORD(req, FILTER_OP_IN_RX_QUEUE, + spec->efs_dmaq_id); + if (spec->efs_flags & EFX_FILTER_FLAG_RX_RSS) { + MCDI_IN_SET_DWORD(req, FILTER_OP_IN_RX_CONTEXT, + spec->efs_rss_context); + } + MCDI_IN_SET_DWORD(req, FILTER_OP_IN_RX_MODE, + spec->efs_flags & EFX_FILTER_FLAG_RX_RSS ? + MC_CMD_FILTER_OP_IN_RX_MODE_RSS : + MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE); + MCDI_IN_SET_DWORD(req, FILTER_OP_IN_TX_DEST, + MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT); + + if (filter_op != MC_CMD_FILTER_OP_IN_OP_REPLACE) { + /* + * NOTE: Unlike most MCDI requests, the filter fields + * are presented in network (big endian) byte order. + */ + memcpy(MCDI_IN2(req, uint8_t, FILTER_OP_IN_SRC_MAC), + spec->efs_rem_mac, EFX_MAC_ADDR_LEN); + memcpy(MCDI_IN2(req, uint8_t, FILTER_OP_IN_DST_MAC), + spec->efs_loc_mac, EFX_MAC_ADDR_LEN); + + MCDI_IN_SET_WORD(req, FILTER_OP_IN_SRC_PORT, + __CPU_TO_BE_16(spec->efs_rem_port)); + MCDI_IN_SET_WORD(req, FILTER_OP_IN_DST_PORT, + __CPU_TO_BE_16(spec->efs_loc_port)); + + MCDI_IN_SET_WORD(req, FILTER_OP_IN_ETHER_TYPE, + __CPU_TO_BE_16(spec->efs_ether_type)); + + MCDI_IN_SET_WORD(req, FILTER_OP_IN_INNER_VLAN, + __CPU_TO_BE_16(spec->efs_inner_vid)); + MCDI_IN_SET_WORD(req, FILTER_OP_IN_OUTER_VLAN, + __CPU_TO_BE_16(spec->efs_outer_vid)); + + /* IP protocol (in low byte, high byte is zero) */ + MCDI_IN_SET_BYTE(req, FILTER_OP_IN_IP_PROTO, + spec->efs_ip_proto); + + EFX_STATIC_ASSERT(sizeof (spec->efs_rem_host) == + MC_CMD_FILTER_OP_IN_SRC_IP_LEN); + EFX_STATIC_ASSERT(sizeof (spec->efs_loc_host) == + MC_CMD_FILTER_OP_IN_DST_IP_LEN); + + memcpy(MCDI_IN2(req, uint8_t, FILTER_OP_IN_SRC_IP), + &spec->efs_rem_host.eo_byte[0], + MC_CMD_FILTER_OP_IN_SRC_IP_LEN); + memcpy(MCDI_IN2(req, uint8_t, FILTER_OP_IN_DST_IP), + &spec->efs_loc_host.eo_byte[0], + MC_CMD_FILTER_OP_IN_DST_IP_LEN); + } + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail2; + } + + if (req.emr_out_length_used < MC_CMD_FILTER_OP_OUT_LEN) { + rc = EMSGSIZE; + goto fail3; + } + + handle->hfh_lo = MCDI_OUT_DWORD(req, FILTER_OP_OUT_HANDLE_LO); + handle->hfh_hi = MCDI_OUT_DWORD(req, FILTER_OP_OUT_HANDLE_HI); + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); + +} + +static __checkReturn int +efx_mcdi_filter_op_delete( + __in efx_nic_t *enp, + __in unsigned int filter_op, + __inout hunt_filter_handle_t *handle) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_FILTER_OP_IN_LEN, + MC_CMD_FILTER_OP_OUT_LEN)]; + int rc; + + memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_FILTER_OP; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_FILTER_OP_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_FILTER_OP_OUT_LEN; + + switch (filter_op) { + case MC_CMD_FILTER_OP_IN_OP_REMOVE: + MCDI_IN_SET_DWORD(req, FILTER_OP_IN_OP, + MC_CMD_FILTER_OP_IN_OP_REMOVE); + break; + case MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE: + MCDI_IN_SET_DWORD(req, FILTER_OP_IN_OP, + MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); + break; + default: + EFSYS_ASSERT(0); + rc = EINVAL; + goto fail1; + } + + MCDI_IN_SET_DWORD(req, FILTER_OP_IN_HANDLE_LO, handle->hfh_lo); + MCDI_IN_SET_DWORD(req, FILTER_OP_IN_HANDLE_HI, handle->hfh_hi); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail2; + } + + if (req.emr_out_length_used < MC_CMD_FILTER_OP_OUT_LEN) { + rc = EMSGSIZE; + goto fail3; + } + + return (0); + +fail3: + EFSYS_PROBE(fail3); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static __checkReturn boolean_t +hunt_filter_equal( + __in const efx_filter_spec_t *left, + __in const efx_filter_spec_t *right) +{ + /* FIXME: Consider rx vs tx filters (look at efs_flags) */ + if (left->efs_match_flags != right->efs_match_flags) + return (B_FALSE); + if (!EFX_OWORD_IS_EQUAL(left->efs_rem_host, right->efs_rem_host)) + return (B_FALSE); + if (!EFX_OWORD_IS_EQUAL(left->efs_loc_host, right->efs_loc_host)) + return (B_FALSE); + if (memcmp(left->efs_rem_mac, right->efs_rem_mac, EFX_MAC_ADDR_LEN)) + return (B_FALSE); + if (memcmp(left->efs_loc_mac, right->efs_loc_mac, EFX_MAC_ADDR_LEN)) + return (B_FALSE); + if (left->efs_rem_port != right->efs_rem_port) + return (B_FALSE); + if (left->efs_loc_port != right->efs_loc_port) + return (B_FALSE); + if (left->efs_inner_vid != right->efs_inner_vid) + return (B_FALSE); + if (left->efs_outer_vid != right->efs_outer_vid) + return (B_FALSE); + if (left->efs_ether_type != right->efs_ether_type) + return (B_FALSE); + if (left->efs_ip_proto != right->efs_ip_proto) + return (B_FALSE); + + return (B_TRUE); + +} + +static __checkReturn boolean_t +hunt_filter_same_dest( + __in const efx_filter_spec_t *left, + __in const efx_filter_spec_t *right) +{ + if ((left->efs_flags & EFX_FILTER_FLAG_RX_RSS) && + (right->efs_flags & EFX_FILTER_FLAG_RX_RSS)) { + if (left->efs_rss_context == right->efs_rss_context) + return (B_TRUE); + } else if ((~(left->efs_flags) & EFX_FILTER_FLAG_RX_RSS) && + (~(right->efs_flags) & EFX_FILTER_FLAG_RX_RSS)) { + if (left->efs_dmaq_id == right->efs_dmaq_id) + return (B_TRUE); + } + return (B_FALSE); +} + +static __checkReturn uint32_t +hunt_filter_hash( + __in efx_filter_spec_t *spec) +{ + EFX_STATIC_ASSERT((sizeof (efx_filter_spec_t) % sizeof (uint32_t)) + == 0); + EFX_STATIC_ASSERT((EFX_FIELD_OFFSET(efx_filter_spec_t, efs_outer_vid) % + sizeof (uint32_t)) == 0); + + /* + * As the area of the efx_filter_spec_t we need to hash is DWORD + * aligned and an exact number of DWORDs in size we can use the + * optimised efx_hash_dwords() rather than efx_hash_bytes() + */ + return (efx_hash_dwords((const uint32_t *)&spec->efs_outer_vid, + (sizeof (efx_filter_spec_t) - + EFX_FIELD_OFFSET(efx_filter_spec_t, efs_outer_vid)) / + sizeof (uint32_t), 0)); +} + +/* + * Decide whether a filter should be exclusive or else should allow + * delivery to additional recipients. Currently we decide that + * filters for specific local unicast MAC and IP addresses are + * exclusive. + */ +static __checkReturn boolean_t +hunt_filter_is_exclusive( + __in efx_filter_spec_t *spec) +{ + if ((spec->efs_match_flags & EFX_FILTER_MATCH_LOC_MAC) && + !EFX_MAC_ADDR_IS_MULTICAST(spec->efs_loc_mac)) + return (B_TRUE); + + if ((spec->efs_match_flags & + (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) == + (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) { + if ((spec->efs_ether_type == EFX_ETHER_TYPE_IPV4) && + ((spec->efs_loc_host.eo_u8[0] & 0xf) != 0xe)) + return (B_TRUE); + if ((spec->efs_ether_type == EFX_ETHER_TYPE_IPV6) && + (spec->efs_loc_host.eo_u8[0] != 0xff)) + return (B_TRUE); + } + + return (B_FALSE); +} + + __checkReturn int +hunt_filter_restore( + __in efx_nic_t *enp) +{ + int tbl_id; + efx_filter_spec_t *spec; + hunt_filter_table_t *hftp = enp->en_filter.ef_hunt_filter_table; + boolean_t restoring; + int state; + int rc; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + + for (tbl_id = 0; tbl_id < EFX_HUNT_FILTER_TBL_ROWS; tbl_id++) { + + EFSYS_LOCK(enp->en_eslp, state); + + spec = hunt_filter_entry_spec(hftp, tbl_id); + if (spec == NULL) { + restoring = B_FALSE; + } else if (hunt_filter_entry_is_busy(hftp, tbl_id)) { + /* Ignore busy entries. */ + restoring = B_FALSE; + } else { + hunt_filter_set_entry_busy(hftp, tbl_id); + restoring = B_TRUE; + } + + EFSYS_UNLOCK(enp->en_eslp, state); + + if (restoring == B_FALSE) + continue; + + if (hunt_filter_is_exclusive(spec)) { + rc = efx_mcdi_filter_op_add(enp, spec, + MC_CMD_FILTER_OP_IN_OP_INSERT, + &hftp->hft_entry[tbl_id].hfe_handle); + } else { + rc = efx_mcdi_filter_op_add(enp, spec, + MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE, + &hftp->hft_entry[tbl_id].hfe_handle); + } + + if (rc != 0) + goto fail1; + + EFSYS_LOCK(enp->en_eslp, state); + + hunt_filter_set_entry_not_busy(hftp, tbl_id); + + EFSYS_UNLOCK(enp->en_eslp, state); + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +/* + * An arbitrary search limit for the software hash table. As per the linux net + * driver. + */ +#define EFX_HUNT_FILTER_SEARCH_LIMIT 200 + +static __checkReturn int +hunt_filter_add_internal( + __in efx_nic_t *enp, + __inout efx_filter_spec_t *spec, + __in boolean_t may_replace, + __out_opt uint32_t *filter_id) +{ + int rc; + hunt_filter_table_t *hftp = enp->en_filter.ef_hunt_filter_table; + efx_filter_spec_t *saved_spec; + uint32_t hash; + unsigned int depth; + int ins_index; + boolean_t replacing = B_FALSE; + unsigned int i; + int state; + boolean_t locked = B_FALSE; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + +#if EFSYS_OPT_RX_SCALE + spec->efs_rss_context = enp->en_rss_context; +#endif + + hash = hunt_filter_hash(spec); + + /* + * FIXME: Add support for inserting filters of different priorities + * and removing lower priority multicast filters (bug 42378) + */ + + /* + * Find any existing filters with the same match tuple or + * else a free slot to insert at. If any of them are busy, + * we have to wait and retry. + */ + for (;;) { + ins_index = -1; + depth = 1; + EFSYS_LOCK(enp->en_eslp, state); + locked = B_TRUE; + + for (;;) { + i = (hash + depth) & (EFX_HUNT_FILTER_TBL_ROWS - 1); + saved_spec = hunt_filter_entry_spec(hftp, i); + + if (!saved_spec) { + if (ins_index < 0) { + ins_index = i; + } + } else if (hunt_filter_equal(spec, saved_spec)) { + if (hunt_filter_entry_is_busy(hftp, i)) + break; + if (saved_spec->efs_priority + == EFX_FILTER_PRI_AUTO) { + ins_index = i; + goto found; + } else if (hunt_filter_is_exclusive(spec)) { + if (may_replace) { + ins_index = i; + goto found; + } else { + rc = EEXIST; + goto fail1; + } + } + + /* Leave existing */ + } + + /* + * Once we reach the maximum search depth, use + * the first suitable slot or return EBUSY if + * there was none. + */ + if (depth == EFX_HUNT_FILTER_SEARCH_LIMIT) { + if (ins_index < 0) { + rc = EBUSY; + goto fail2; + } + goto found; + } + depth++; + } + EFSYS_UNLOCK(enp->en_eslp, state); + locked = B_FALSE; + } + +found: + /* + * Create a software table entry if necessary, and mark it + * busy. We might yet fail to insert, but any attempt to + * insert a conflicting filter while we're waiting for the + * firmware must find the busy entry. + */ + saved_spec = hunt_filter_entry_spec(hftp, ins_index); + if (saved_spec) { + if (saved_spec->efs_priority == EFX_FILTER_PRI_AUTO) { + /* This is a filter we are refreshing */ + hunt_filter_set_entry_not_auto_old(hftp, ins_index); + goto out_unlock; + + } + replacing = B_TRUE; + } else { + EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), saved_spec); + if (!saved_spec) { + rc = ENOMEM; + goto fail3; + } + *saved_spec = *spec; + hunt_filter_set_entry(hftp, ins_index, saved_spec); + } + hunt_filter_set_entry_busy(hftp, ins_index); + + EFSYS_UNLOCK(enp->en_eslp, state); + locked = B_FALSE; + + /* + * On replacing the filter handle may change after after a successful + * replace operation. + */ + if (replacing) { + rc = efx_mcdi_filter_op_add(enp, spec, + MC_CMD_FILTER_OP_IN_OP_REPLACE, + &hftp->hft_entry[ins_index].hfe_handle); + } else if (hunt_filter_is_exclusive(spec)) { + rc = efx_mcdi_filter_op_add(enp, spec, + MC_CMD_FILTER_OP_IN_OP_INSERT, + &hftp->hft_entry[ins_index].hfe_handle); + } else { + rc = efx_mcdi_filter_op_add(enp, spec, + MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE, + &hftp->hft_entry[ins_index].hfe_handle); + } + + if (rc != 0) + goto fail4; + + EFSYS_LOCK(enp->en_eslp, state); + locked = B_TRUE; + + if (replacing) { + /* Update the fields that may differ */ + saved_spec->efs_priority = spec->efs_priority; + saved_spec->efs_flags = spec->efs_flags; + saved_spec->efs_rss_context = spec->efs_rss_context; + saved_spec->efs_dmaq_id = spec->efs_dmaq_id; + } + + hunt_filter_set_entry_not_busy(hftp, ins_index); + +out_unlock: + + EFSYS_UNLOCK(enp->en_eslp, state); + locked = B_FALSE; + + if (filter_id) + *filter_id = ins_index; + + return (0); + +fail4: + EFSYS_PROBE(fail4); + + if (!replacing) { + EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), saved_spec); + saved_spec = NULL; + } + hunt_filter_set_entry_not_busy(hftp, ins_index); + hunt_filter_set_entry(hftp, ins_index, NULL); + +fail3: + EFSYS_PROBE(fail3); + +fail2: + EFSYS_PROBE(fail2); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + if (locked) + EFSYS_UNLOCK(enp->en_eslp, state); + + return (rc); +} + + __checkReturn int +hunt_filter_add( + __in efx_nic_t *enp, + __inout efx_filter_spec_t *spec, + __in boolean_t may_replace) +{ + int rc; + + rc = hunt_filter_add_internal(enp, spec, may_replace, NULL); + if (rc != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + +static __checkReturn int +hunt_filter_delete_internal( + __in efx_nic_t *enp, + __in uint32_t filter_id) +{ + int rc; + hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table; + efx_filter_spec_t *spec; + int state; + uint32_t filter_idx = filter_id % EFX_HUNT_FILTER_TBL_ROWS; + + /* + * Find the software table entry and mark it busy. Don't + * remove it yet; any attempt to update while we're waiting + * for the firmware must find the busy entry. + * + * FIXME: What if the busy flag is never cleared? + */ + EFSYS_LOCK(enp->en_eslp, state); + while (hunt_filter_entry_is_busy(table, filter_idx)) { + EFSYS_UNLOCK(enp->en_eslp, state); + EFSYS_SPIN(1); + EFSYS_LOCK(enp->en_eslp, state); + } + if ((spec = hunt_filter_entry_spec(table, filter_idx)) != NULL) { + hunt_filter_set_entry_busy(table, filter_idx); + } + EFSYS_UNLOCK(enp->en_eslp, state); + + if (spec == NULL) { + rc = ENOENT; + goto fail1; + } + + /* + * Try to remove the hardware filter. This may fail if the MC has + * rebooted (which frees all hardware filter resources). + */ + if (hunt_filter_is_exclusive(spec)) { + rc = efx_mcdi_filter_op_delete(enp, + MC_CMD_FILTER_OP_IN_OP_REMOVE, + &table->hft_entry[filter_idx].hfe_handle); + } else { + rc = efx_mcdi_filter_op_delete(enp, + MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE, + &table->hft_entry[filter_idx].hfe_handle); + } + + /* Free the software table entry */ + EFSYS_LOCK(enp->en_eslp, state); + hunt_filter_set_entry_not_busy(table, filter_idx); + hunt_filter_set_entry(table, filter_idx, NULL); + EFSYS_UNLOCK(enp->en_eslp, state); + + EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec); + + /* Check result of hardware filter removal */ + if (rc != 0) + goto fail2; + + return (0); + +fail2: + EFSYS_PROBE(fail2); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_filter_delete( + __in efx_nic_t *enp, + __inout efx_filter_spec_t *spec) +{ + int rc; + hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table; + efx_filter_spec_t *saved_spec; + unsigned int hash; + unsigned int depth; + unsigned int i; + int state; + boolean_t locked = B_FALSE; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + + hash = hunt_filter_hash(spec); + + EFSYS_LOCK(enp->en_eslp, state); + locked = B_TRUE; + + depth = 1; + for (;;) { + i = (hash + depth) & (EFX_HUNT_FILTER_TBL_ROWS - 1); + saved_spec = hunt_filter_entry_spec(table, i); + if (saved_spec && hunt_filter_equal(spec, saved_spec) && + hunt_filter_same_dest(spec, saved_spec)) { + break; + } + if (depth == EFX_HUNT_FILTER_SEARCH_LIMIT) { + rc = ENOENT; + goto fail1; + } + depth++; + } + + EFSYS_UNLOCK(enp->en_eslp, state); + locked = B_FALSE; + + rc = hunt_filter_delete_internal(enp, i); + if (rc != 0) + goto fail2; + + return (0); + +fail2: + EFSYS_PROBE(fail2); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + if (locked) + EFSYS_UNLOCK(enp->en_eslp, state); + + return (rc); +} + +static __checkReturn int +efx_mcdi_get_parser_disp_info( + __in efx_nic_t *enp, + __out uint32_t *list, + __out size_t *length) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_GET_PARSER_DISP_INFO_IN_LEN, + MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX)]; + int rc; + uint32_t i; + boolean_t support_unknown_ucast = B_FALSE; + boolean_t support_unknown_mcast = B_FALSE; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_GET_PARSER_DISP_INFO; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_GET_PARSER_DISP_INFO_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX; + + MCDI_IN_SET_DWORD(req, GET_PARSER_DISP_INFO_OUT_OP, + MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + *length = MCDI_OUT_DWORD(req, + GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES); + + if (req.emr_out_length_used < + MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(*length)) { + rc = EMSGSIZE; + goto fail2; + } + + memcpy(list, + MCDI_OUT2(req, + uint32_t, + GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES), + (*length) * sizeof (uint32_t)); + EFX_STATIC_ASSERT(sizeof (uint32_t) == + MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN); + + /* + * Remove UNKNOWN UCAST and MCAST flags, and if both are present, change + * the lower priority one to LOC_MAC_IG. + */ + for (i = 0; i < *length; i++) { + if (list[i] & MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN) { + list[i] &= + (~MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN); + support_unknown_ucast = B_TRUE; + } + if (list[i] & MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN) { + list[i] &= + (~MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN); + support_unknown_mcast = B_TRUE; + } + + if (support_unknown_ucast && support_unknown_mcast) { + list[i] &= EFX_FILTER_MATCH_LOC_MAC_IG; + break; + } + } + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_filter_supported_filters( + __in efx_nic_t *enp, + __out uint32_t *list, + __out size_t *length) +{ + int rc; + + if ((rc = efx_mcdi_get_parser_disp_info(enp, list, length) != 0)) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static __checkReturn int +hunt_filter_unicast_refresh( + __in efx_nic_t *enp, + __in_ecount(6) uint8_t const *addr, + __in boolean_t all_unicst, + __in efx_filter_flag_t filter_flags) +{ + hunt_filter_table_t *hftp = enp->en_filter.ef_hunt_filter_table; + efx_filter_spec_t spec; + int rc; + + if (all_unicst == B_TRUE) + goto use_uc_def; + + /* Insert the filter for the local station address */ + efx_filter_spec_init_rx(&spec, EFX_FILTER_PRI_AUTO, + filter_flags, + hftp->hft_default_rxq); + efx_filter_spec_set_eth_local(&spec, EFX_FILTER_SPEC_VID_UNSPEC, addr); + + rc = hunt_filter_add_internal(enp, &spec, B_TRUE, + &hftp->hft_unicst_filter_index); + if (rc != 0) { + /* + * Fall back to an unknown filter. We may be able to subscribe + * to it even if we couldn't insert the unicast filter. + */ + goto use_uc_def; + } + hftp->hft_unicst_filter_set = B_TRUE; + + return (0); + +use_uc_def: + /* Insert the unknown unicast filter */ + efx_filter_spec_init_rx(&spec, EFX_FILTER_PRI_AUTO, + filter_flags, + hftp->hft_default_rxq); + efx_filter_spec_set_uc_def(&spec); + rc = hunt_filter_add_internal(enp, &spec, B_TRUE, + &hftp->hft_unicst_filter_index); + if (rc != 0) + goto fail1; + + hftp->hft_unicst_filter_set = B_TRUE; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + if (hftp->hft_unicst_filter_set != B_FALSE) { + (void) hunt_filter_delete_internal(enp, + hftp->hft_unicst_filter_index); + + hftp->hft_unicst_filter_set = B_FALSE; + } + + return (rc); +} + +static __checkReturn int +hunt_filter_multicast_refresh( + __in efx_nic_t *enp, + __in boolean_t mulcst, + __in boolean_t all_mulcst, + __in boolean_t brdcst, + __in_ecount(6*count) uint8_t const *addrs, + __in int count, + __in efx_filter_flag_t filter_flags) +{ + hunt_filter_table_t *hftp = enp->en_filter.ef_hunt_filter_table; + efx_filter_spec_t spec; + uint8_t addr[6]; + unsigned i; + int rc; + + if (all_mulcst == B_TRUE) + goto use_mc_def; + + if (mulcst == B_FALSE) + count = 0; + + if (count + (brdcst ? 1 : 0) > + EFX_ARRAY_SIZE(hftp->hft_mulcst_filter_indexes)) { + /* Too many MAC addresses; use unknown multicast filter */ + goto use_mc_def; + } + + /* Insert/renew multicast address list filters */ + hftp->hft_mulcst_filter_count = count; + for (i = 0; i < hftp->hft_mulcst_filter_count; i++) { + efx_filter_spec_init_rx(&spec, + EFX_FILTER_PRI_AUTO, + filter_flags, + hftp->hft_default_rxq); + + efx_filter_spec_set_eth_local(&spec, + EFX_FILTER_SPEC_VID_UNSPEC, + &addrs[i * EFX_MAC_ADDR_LEN]); + + rc = hunt_filter_add_internal(enp, &spec, B_TRUE, + &hftp->hft_mulcst_filter_indexes[i]); + if (rc != 0) { + /* Rollback, then use unknown multicast filter */ + goto rollback; + } + } + + if (brdcst == B_TRUE) { + /* Insert/renew broadcast address filter */ + hftp->hft_mulcst_filter_count++; + efx_filter_spec_init_rx(&spec, EFX_FILTER_PRI_AUTO, + filter_flags, + hftp->hft_default_rxq); + + EFX_MAC_BROADCAST_ADDR_SET(addr); + efx_filter_spec_set_eth_local(&spec, EFX_FILTER_SPEC_VID_UNSPEC, + addr); + + rc = hunt_filter_add_internal(enp, &spec, B_TRUE, + &hftp->hft_mulcst_filter_indexes[ + hftp->hft_mulcst_filter_count - 1]); + if (rc != 0) { + /* Rollback, then use unknown multicast filter */ + goto rollback; + } + } + + return (0); + +rollback: + /* + * Rollback by removing any filters we have inserted + * before inserting the unknown multicast filter. + */ + while (i--) { + (void) hunt_filter_delete_internal(enp, + hftp->hft_mulcst_filter_indexes[i]); + } + hftp->hft_mulcst_filter_count = 0; + +use_mc_def: + /* Insert the unknown multicast filter */ + efx_filter_spec_init_rx(&spec, EFX_FILTER_PRI_AUTO, + filter_flags, + hftp->hft_default_rxq); + efx_filter_spec_set_mc_def(&spec); + + rc = hunt_filter_add_internal(enp, &spec, B_TRUE, + &hftp->hft_mulcst_filter_indexes[0]); + if (rc != 0) + goto fail1; + + hftp->hft_mulcst_filter_count = 1; + + /* + * FIXME: If brdcst == B_FALSE, add a filter to drop broadcast traffic. + */ + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); + +} + + +static __checkReturn int +hunt_filter_get_workarounds( + __in efx_nic_t *enp) +{ + efx_nic_cfg_t *encp = &enp->en_nic_cfg; + uint32_t implemented = 0; + uint32_t enabled = 0; + int rc; + + rc = efx_mcdi_get_workarounds(enp, &implemented, &enabled); + if (rc == 0) { + /* Check if chained multicast filter support is enabled */ + if (implemented & enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807) + encp->enc_bug26807_workaround = B_TRUE; + else + encp->enc_bug26807_workaround = B_FALSE; + } else if (rc == ENOTSUP) { + /* + * Firmware is too old to support GET_WORKAROUNDS, and support + * for this workaround was implemented later. + */ + encp->enc_bug26807_workaround = B_FALSE; + } else { + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); + +} + + +/* + * Reconfigure all filters. + * If all_unicst and/or all mulcst filters cannot be applied then + * return ENOTSUP (Note the filters for the specified addresses are + * still applied in this case). + */ + __checkReturn int +hunt_filter_reconfigure( + __in efx_nic_t *enp, + __in_ecount(6) uint8_t const *mac_addr, + __in boolean_t all_unicst, + __in boolean_t mulcst, + __in boolean_t all_mulcst, + __in boolean_t brdcst, + __in_ecount(6*count) uint8_t const *addrs, + __in int count) +{ + hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table; + efx_filter_flag_t filter_flags; + unsigned i; + int all_unicst_rc; + int all_mulcst_rc; + int rc; + + if (table->hft_default_rxq == NULL) { + /* + * Filters direct traffic to the default RXQ, and so cannot be + * inserted until it is available. Any currently configured + * filters must be removed (ignore errors in case the MC + * has rebooted, which removes hardware filters). + */ + if (table->hft_unicst_filter_set != B_FALSE) { + (void) hunt_filter_delete_internal(enp, + table->hft_unicst_filter_index); + table->hft_unicst_filter_set = B_FALSE; + } + for (i = 0; i < table->hft_mulcst_filter_count; i++) { + (void) hunt_filter_delete_internal(enp, + table->hft_mulcst_filter_indexes[i]); + } + table->hft_mulcst_filter_count = 0; + + return (0); + } + + if (table->hft_using_rss) + filter_flags = EFX_FILTER_FLAG_RX_RSS; + else + filter_flags = 0; + + /* Mark old filters which may need to be removed */ + if (table->hft_unicst_filter_set != B_FALSE) { + hunt_filter_set_entry_auto_old(table, + table->hft_unicst_filter_index); + } + for (i = 0; i < table->hft_mulcst_filter_count; i++) { + hunt_filter_set_entry_auto_old(table, + table->hft_mulcst_filter_indexes[i]); + } + + /* Insert or renew unicast filters */ + if ((all_unicst_rc = hunt_filter_unicast_refresh(enp, mac_addr, + all_unicst, filter_flags)) != 0) { + if (all_unicst == B_FALSE) { + rc = all_unicst_rc; + goto fail1; + } + /* Retry without all_unicast flag */ + rc = hunt_filter_unicast_refresh(enp, mac_addr, + B_FALSE, filter_flags); + if (rc != 0) + goto fail2; + } + + /* + * WORKAROUND_BUG26807 controls firmware support for chained multicast + * filters, and can only be enabled or disabled when the hardware filter + * table is empty. + * + * Firmware will reset (FLR) functions which have inserted filters in + * the hardware filter table when the workaround is enabled/disabled. + * Functions without any hardware filters are not reset. + * + * Re-check if the workaround is enabled after adding unicast hardware + * filters. This ensures that encp->enc_workaround_bug26807 matches the + * firmware state, and that later changes to enable/disable the + * workaround will result in this function seeing a reset (FLR). + */ + if ((rc = hunt_filter_get_workarounds(enp)) != 0) + goto fail3; + + /* Insert or renew multicast filters */ + if ((all_mulcst_rc = hunt_filter_multicast_refresh(enp, mulcst, + all_mulcst, brdcst, + addrs, count, filter_flags)) != 0) { + if (all_mulcst == B_FALSE) { + rc = all_mulcst_rc; + goto fail4; + } + /* Retry without all_mulcast flag */ + rc = hunt_filter_multicast_refresh(enp, mulcst, + B_FALSE, brdcst, + addrs, count, filter_flags); + if (rc != 0) + goto fail5; + } + + /* Remove old filters which were not renewed */ + for (i = 0; i < EFX_ARRAY_SIZE(table->hft_entry); i++) { + if (hunt_filter_entry_is_auto_old(table, i)) { + (void) hunt_filter_delete_internal(enp, i); + } + } + + /* report if any optional flags were rejected */ + if (((all_unicst != B_FALSE) && (all_unicst_rc != 0)) || + ((all_mulcst != B_FALSE) && (all_mulcst_rc != 0))) { + rc = ENOTSUP; + } + + return (rc); + +fail5: + EFSYS_PROBE(fail5); +fail4: + EFSYS_PROBE(fail4); +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + /* Clear auto old flags */ + for (i = 0; i < EFX_ARRAY_SIZE(table->hft_entry); i++) { + if (hunt_filter_entry_is_auto_old(table, i)) { + hunt_filter_set_entry_not_auto_old(table, i); + } + } + + return (rc); +} + + void +hunt_filter_get_default_rxq( + __in efx_nic_t *enp, + __out efx_rxq_t **erpp, + __out boolean_t *using_rss) +{ + hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table; + + *erpp = table->hft_default_rxq; + *using_rss = table->hft_using_rss; +} + + + void +hunt_filter_default_rxq_set( + __in efx_nic_t *enp, + __in efx_rxq_t *erp, + __in boolean_t using_rss) +{ + hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table; + +#if EFSYS_OPT_RX_SCALE + EFSYS_ASSERT((using_rss == B_FALSE) || + (enp->en_rss_context != HUNTINGTON_RSS_CONTEXT_INVALID)); + table->hft_using_rss = using_rss; +#else + EFSYS_ASSERT(using_rss == B_FALSE); + table->hft_using_rss = B_FALSE; +#endif + table->hft_default_rxq = erp; +} + + void +hunt_filter_default_rxq_clear( + __in efx_nic_t *enp) +{ + hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table; + + table->hft_default_rxq = NULL; + table->hft_using_rss = B_FALSE; +} + + +#endif /* EFSYS_OPT_FILTER */ + +#endif /* EFSYS_OPT_HUNTINGTON */ Property changes on: head/sys/dev/sfxge/common/hunt_filter.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/hunt_impl.h =================================================================== --- head/sys/dev/sfxge/common/hunt_impl.h (nonexistent) +++ head/sys/dev/sfxge/common/hunt_impl.h (revision 283514) @@ -0,0 +1,1015 @@ +/*- + * Copyright (c) 2012-2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + * + * $FreeBSD$ + */ + +#ifndef _SYS_HUNT_IMPL_H +#define _SYS_HUNT_IMPL_H + +#include "efx.h" +#include "efx_regs.h" +#include "efx_regs_ef10.h" +#include "efx_mcdi.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HUNTINGTON_NVRAM_CHUNK 0x80 + +/* Alignment requirement for value written to RX WPTR: + * the WPTR must be aligned to an 8 descriptor boundary + */ +#define HUNTINGTON_RX_WPTR_ALIGN 8 + +/* Invalid RSS context handle */ +#define HUNTINGTON_RSS_CONTEXT_INVALID (0xffffffff) + + +/* EV */ + + __checkReturn int +hunt_ev_init( + __in efx_nic_t *enp); + + void +hunt_ev_fini( + __in efx_nic_t *enp); + + __checkReturn int +hunt_ev_qcreate( + __in efx_nic_t *enp, + __in unsigned int index, + __in efsys_mem_t *esmp, + __in size_t n, + __in uint32_t id, + __in efx_evq_t *eep); + + void +hunt_ev_qdestroy( + __in efx_evq_t *eep); + + __checkReturn int +hunt_ev_qprime( + __in efx_evq_t *eep, + __in unsigned int count); + + void +hunt_ev_qpost( + __in efx_evq_t *eep, + __in uint16_t data); + + __checkReturn int +hunt_ev_qmoderate( + __in efx_evq_t *eep, + __in unsigned int us); + +#if EFSYS_OPT_QSTATS + void +hunt_ev_qstats_update( + __in efx_evq_t *eep, + __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); +#endif /* EFSYS_OPT_QSTATS */ + + void +hunt_ev_rxlabel_init( + __in efx_evq_t *eep, + __in efx_rxq_t *erp, + __in unsigned int label); + + void +hunt_ev_rxlabel_fini( + __in efx_evq_t *eep, + __in unsigned int label); + +/* INTR */ + + __checkReturn int +hunt_intr_init( + __in efx_nic_t *enp, + __in efx_intr_type_t type, + __in efsys_mem_t *esmp); + + void +hunt_intr_enable( + __in efx_nic_t *enp); + + void +hunt_intr_disable( + __in efx_nic_t *enp); + + void +hunt_intr_disable_unlocked( + __in efx_nic_t *enp); + + __checkReturn int +hunt_intr_trigger( + __in efx_nic_t *enp, + __in unsigned int level); + + void +hunt_intr_fini( + __in efx_nic_t *enp); + +/* NIC */ + +extern __checkReturn int +hunt_nic_probe( + __in efx_nic_t *enp); + +extern __checkReturn int +hunt_nic_set_drv_limits( + __inout efx_nic_t *enp, + __in efx_drv_limits_t *edlp); + +extern __checkReturn int +hunt_nic_get_vi_pool( + __in efx_nic_t *enp, + __out uint32_t *vi_countp); + +extern __checkReturn int +hunt_nic_get_bar_region( + __in efx_nic_t *enp, + __in efx_nic_region_t region, + __out uint32_t *offsetp, + __out size_t *sizep); + +extern __checkReturn int +hunt_nic_reset( + __in efx_nic_t *enp); + +extern __checkReturn int +hunt_nic_init( + __in efx_nic_t *enp); + +#if EFSYS_OPT_DIAG + +extern __checkReturn int +hunt_nic_register_test( + __in efx_nic_t *enp); + +#endif /* EFSYS_OPT_DIAG */ + +extern void +hunt_nic_fini( + __in efx_nic_t *enp); + +extern void +hunt_nic_unprobe( + __in efx_nic_t *enp); + + +/* MAC */ + +extern __checkReturn int +hunt_mac_poll( + __in efx_nic_t *enp, + __out efx_link_mode_t *link_modep); + +extern __checkReturn int +hunt_mac_up( + __in efx_nic_t *enp, + __out boolean_t *mac_upp); + +extern __checkReturn int +hunt_mac_addr_set( + __in efx_nic_t *enp); + +extern __checkReturn int +hunt_mac_reconfigure( + __in efx_nic_t *enp); + +extern __checkReturn int +hunt_mac_multicast_list_set( + __in efx_nic_t *enp); + +extern __checkReturn int +hunt_mac_filter_default_rxq_set( + __in efx_nic_t *enp, + __in efx_rxq_t *erp, + __in boolean_t using_rss); + +extern void +hunt_mac_filter_default_rxq_clear( + __in efx_nic_t *enp); + +#if EFSYS_OPT_LOOPBACK + +extern __checkReturn int +hunt_mac_loopback_set( + __in efx_nic_t *enp, + __in efx_link_mode_t link_mode, + __in efx_loopback_type_t loopback_type); + +#endif /* EFSYS_OPT_LOOPBACK */ + +#if EFSYS_OPT_MAC_STATS + +extern __checkReturn int +hunt_mac_stats_update( + __in efx_nic_t *enp, + __in efsys_mem_t *esmp, + __out_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, + __out_opt uint32_t *generationp); + +#endif /* EFSYS_OPT_MAC_STATS */ + + +/* MCDI */ + +#if EFSYS_OPT_MCDI + +extern __checkReturn int +hunt_mcdi_init( + __in efx_nic_t *enp, + __in const efx_mcdi_transport_t *mtp); + +extern void +hunt_mcdi_fini( + __in efx_nic_t *enp); + +extern void +hunt_mcdi_request_copyin( + __in efx_nic_t *enp, + __in efx_mcdi_req_t *emrp, + __in unsigned int seq, + __in boolean_t ev_cpl, + __in boolean_t new_epoch); + +extern __checkReturn boolean_t +hunt_mcdi_request_poll( + __in efx_nic_t *enp); + +extern void +hunt_mcdi_request_copyout( + __in efx_nic_t *enp, + __in efx_mcdi_req_t *emrp); + +extern int +hunt_mcdi_poll_reboot( + __in efx_nic_t *enp); + +extern __checkReturn int +hunt_mcdi_fw_update_supported( + __in efx_nic_t *enp, + __out boolean_t *supportedp); + +extern __checkReturn int +hunt_mcdi_macaddr_change_supported( + __in efx_nic_t *enp, + __out boolean_t *supportedp); + +#endif /* EFSYS_OPT_MCDI */ + +/* NVRAM */ + +#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD + +extern __checkReturn int +hunt_nvram_buf_read_tlv( + __in efx_nic_t *enp, + __in_bcount(partn_size) caddr_t partn_data, + __in size_t partn_size, + __in uint32_t tag, + __deref_out_bcount_opt(*sizep) caddr_t *datap, + __out size_t *sizep); + +extern __checkReturn int +hunt_nvram_buf_write_tlv( + __inout_bcount(partn_size) caddr_t partn_data, + __in size_t partn_size, + __in uint32_t tag, + __in_bcount(tag_size) caddr_t tag_data, + __in size_t tag_size, + __out size_t *total_lengthp); + +extern __checkReturn int +hunt_nvram_partn_read_tlv( + __in efx_nic_t *enp, + __in uint32_t partn, + __in uint32_t tag, + __deref_out_bcount_opt(*sizep) caddr_t *datap, + __out size_t *sizep); + +extern __checkReturn int +hunt_nvram_partn_write_tlv( + __in efx_nic_t *enp, + __in uint32_t partn, + __in uint32_t tag, + __in_bcount(size) caddr_t data, + __in size_t size); + +extern __checkReturn int +hunt_nvram_partn_size( + __in efx_nic_t *enp, + __in unsigned int partn, + __out size_t *sizep); + +extern __checkReturn int +hunt_nvram_partn_lock( + __in efx_nic_t *enp, + __in unsigned int partn); + +extern __checkReturn int +hunt_nvram_partn_read( + __in efx_nic_t *enp, + __in unsigned int partn, + __in unsigned int offset, + __out_bcount(size) caddr_t data, + __in size_t size); + +extern __checkReturn int +hunt_nvram_partn_erase( + __in efx_nic_t *enp, + __in unsigned int partn, + __in unsigned int offset, + __in size_t size); + +extern __checkReturn int +hunt_nvram_partn_write( + __in efx_nic_t *enp, + __in unsigned int partn, + __in unsigned int offset, + __out_bcount(size) caddr_t data, + __in size_t size); + +extern void +hunt_nvram_partn_unlock( + __in efx_nic_t *enp, + __in unsigned int partn); + +#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ + +#if EFSYS_OPT_NVRAM + +#if EFSYS_OPT_DIAG + +extern __checkReturn int +hunt_nvram_test( + __in efx_nic_t *enp); + +#endif /* EFSYS_OPT_DIAG */ + +extern __checkReturn int +hunt_nvram_size( + __in efx_nic_t *enp, + __in efx_nvram_type_t type, + __out size_t *sizep); + +extern __checkReturn int +hunt_nvram_get_version( + __in efx_nic_t *enp, + __in efx_nvram_type_t type, + __out uint32_t *subtypep, + __out_ecount(4) uint16_t version[4]); + +extern __checkReturn int +hunt_nvram_rw_start( + __in efx_nic_t *enp, + __in efx_nvram_type_t type, + __out size_t *pref_chunkp); + +extern __checkReturn int +hunt_nvram_read_chunk( + __in efx_nic_t *enp, + __in efx_nvram_type_t type, + __in unsigned int offset, + __out_bcount(size) caddr_t data, + __in size_t size); + +extern __checkReturn int +hunt_nvram_erase( + __in efx_nic_t *enp, + __in efx_nvram_type_t type); + +extern __checkReturn int +hunt_nvram_write_chunk( + __in efx_nic_t *enp, + __in efx_nvram_type_t type, + __in unsigned int offset, + __in_bcount(size) caddr_t data, + __in size_t size); + +extern void +hunt_nvram_rw_finish( + __in efx_nic_t *enp, + __in efx_nvram_type_t type); + +extern __checkReturn int +hunt_nvram_partn_set_version( + __in efx_nic_t *enp, + __in unsigned int partn, + __in_ecount(4) uint16_t version[4]); + +extern __checkReturn int +hunt_nvram_set_version( + __in efx_nic_t *enp, + __in efx_nvram_type_t type, + __in_ecount(4) uint16_t version[4]); + +#endif /* EFSYS_OPT_NVRAM */ + + +/* PHY */ + +typedef struct hunt_link_state_s { + uint32_t hls_adv_cap_mask; + uint32_t hls_lp_cap_mask; + unsigned int hls_fcntl; + efx_link_mode_t hls_link_mode; +#if EFSYS_OPT_LOOPBACK + efx_loopback_type_t hls_loopback; +#endif + boolean_t hls_mac_up; +} hunt_link_state_t; + +extern void +hunt_phy_link_ev( + __in efx_nic_t *enp, + __in efx_qword_t *eqp, + __out efx_link_mode_t *link_modep); + +extern __checkReturn int +hunt_phy_get_link( + __in efx_nic_t *enp, + __out hunt_link_state_t *hlsp); + +extern __checkReturn int +hunt_phy_power( + __in efx_nic_t *enp, + __in boolean_t on); + +extern __checkReturn int +hunt_phy_reconfigure( + __in efx_nic_t *enp); + +extern __checkReturn int +hunt_phy_verify( + __in efx_nic_t *enp); + +extern __checkReturn int +hunt_phy_oui_get( + __in efx_nic_t *enp, + __out uint32_t *ouip); + +#if EFSYS_OPT_PHY_STATS + +extern __checkReturn int +hunt_phy_stats_update( + __in efx_nic_t *enp, + __in efsys_mem_t *esmp, + __out_ecount(EFX_PHY_NSTATS) uint32_t *stat); + +#endif /* EFSYS_OPT_PHY_STATS */ + +#if EFSYS_OPT_PHY_PROPS + +#if EFSYS_OPT_NAMES + +extern const char * +hunt_phy_prop_name( + __in efx_nic_t *enp, + __in unsigned int id); + +#endif /* EFSYS_OPT_NAMES */ + +extern __checkReturn int +hunt_phy_prop_get( + __in efx_nic_t *enp, + __in unsigned int id, + __in uint32_t flags, + __out uint32_t *valp); + +extern __checkReturn int +hunt_phy_prop_set( + __in efx_nic_t *enp, + __in unsigned int id, + __in uint32_t val); + +#endif /* EFSYS_OPT_PHY_PROPS */ + +#if EFSYS_OPT_BIST + +extern __checkReturn int +hunt_bist_enable_offline( + __in efx_nic_t *enp); + +extern __checkReturn int +hunt_bist_start( + __in efx_nic_t *enp, + __in efx_bist_type_t type); + +extern __checkReturn int +hunt_bist_poll( + __in efx_nic_t *enp, + __in efx_bist_type_t type, + __out efx_bist_result_t *resultp, + __out_opt __drv_when(count > 0, __notnull) + uint32_t *value_maskp, + __out_ecount_opt(count) __drv_when(count > 0, __notnull) + unsigned long *valuesp, + __in size_t count); + +extern void +hunt_bist_stop( + __in efx_nic_t *enp, + __in efx_bist_type_t type); + +#endif /* EFSYS_OPT_BIST */ + + +/* SRAM */ + +#if EFSYS_OPT_DIAG + +extern __checkReturn int +hunt_sram_test( + __in efx_nic_t *enp, + __in efx_sram_pattern_fn_t func); + +#endif /* EFSYS_OPT_DIAG */ + + +/* TX */ + +extern __checkReturn int +hunt_tx_init( + __in efx_nic_t *enp); + +extern void +hunt_tx_fini( + __in efx_nic_t *enp); + +extern __checkReturn int +hunt_tx_qcreate( + __in efx_nic_t *enp, + __in unsigned int index, + __in unsigned int label, + __in efsys_mem_t *esmp, + __in size_t n, + __in uint32_t id, + __in uint16_t flags, + __in efx_evq_t *eep, + __in efx_txq_t *etp, + __out unsigned int *addedp); + +extern void +hunt_tx_qdestroy( + __in efx_txq_t *etp); + +extern __checkReturn int +hunt_tx_qpost( + __in efx_txq_t *etp, + __in_ecount(n) efx_buffer_t *eb, + __in unsigned int n, + __in unsigned int completed, + __inout unsigned int *addedp); + +extern void +hunt_tx_qpush( + __in efx_txq_t *etp, + __in unsigned int added, + __in unsigned int pushed); + +extern __checkReturn int +hunt_tx_qpace( + __in efx_txq_t *etp, + __in unsigned int ns); + +extern __checkReturn int +hunt_tx_qflush( + __in efx_txq_t *etp); + +extern void +hunt_tx_qenable( + __in efx_txq_t *etp); + +extern __checkReturn int +hunt_tx_qpio_enable( + __in efx_txq_t *etp); + +extern void +hunt_tx_qpio_disable( + __in efx_txq_t *etp); + +extern __checkReturn int +hunt_tx_qpio_write( + __in efx_txq_t *etp, + __in_ecount(buf_length) uint8_t *buffer, + __in size_t buf_length, + __in size_t pio_buf_offset); + +extern __checkReturn int +hunt_tx_qpio_post( + __in efx_txq_t *etp, + __in size_t pkt_length, + __in unsigned int completed, + __inout unsigned int *addedp); + +extern __checkReturn int +hunt_tx_qdesc_post( + __in efx_txq_t *etp, + __in_ecount(n) efx_desc_t *ed, + __in unsigned int n, + __in unsigned int completed, + __inout unsigned int *addedp); + +extern void +hunt_tx_qdesc_dma_create( + __in efx_txq_t *etp, + __in efsys_dma_addr_t addr, + __in size_t size, + __in boolean_t eop, + __out efx_desc_t *edp); + +extern void +hunt_tx_qdesc_tso_create( + __in efx_txq_t *etp, + __in uint16_t ipv4_id, + __in uint32_t tcp_seq, + __in uint8_t tcp_flags, + __out efx_desc_t *edp); + +extern void +hunt_tx_qdesc_vlantci_create( + __in efx_txq_t *etp, + __in uint16_t vlan_tci, + __out efx_desc_t *edp); + + +#if EFSYS_OPT_QSTATS + +extern void +hunt_tx_qstats_update( + __in efx_txq_t *etp, + __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); + +#endif /* EFSYS_OPT_QSTATS */ + +/* PIO */ + +/* Missing register definitions */ +#ifndef ER_DZ_TX_PIOBUF_OFST +#define ER_DZ_TX_PIOBUF_OFST 0x00001000 +#endif +#ifndef ER_DZ_TX_PIOBUF_STEP +#define ER_DZ_TX_PIOBUF_STEP 8192 +#endif +#ifndef ER_DZ_TX_PIOBUF_ROWS +#define ER_DZ_TX_PIOBUF_ROWS 2048 +#endif + +#ifndef ER_DZ_TX_PIOBUF_SIZE +#define ER_DZ_TX_PIOBUF_SIZE 2048 +#endif + +#define HUNT_PIOBUF_NBUFS (16) +#define HUNT_PIOBUF_SIZE (ER_DZ_TX_PIOBUF_SIZE) + +#define HUNT_MIN_PIO_ALLOC_SIZE (HUNT_PIOBUF_SIZE / 32) + +typedef uint32_t efx_piobuf_handle_t; + +#define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1) + +extern __checkReturn int +hunt_nic_pio_alloc( + __inout efx_nic_t *enp, + __out uint32_t *bufnump, + __out efx_piobuf_handle_t *handlep, + __out uint32_t *blknump, + __out uint32_t *offsetp, + __out size_t *sizep); + +extern __checkReturn int +hunt_nic_pio_free( + __inout efx_nic_t *enp, + __in uint32_t bufnum, + __in uint32_t blknum); + +extern __checkReturn int +hunt_nic_pio_link( + __inout efx_nic_t *enp, + __in uint32_t vi_index, + __in efx_piobuf_handle_t handle); + +extern __checkReturn int +hunt_nic_pio_unlink( + __inout efx_nic_t *enp, + __in uint32_t vi_index); + + +/* VPD */ + +#if EFSYS_OPT_VPD + +extern __checkReturn int +hunt_vpd_init( + __in efx_nic_t *enp); + +extern __checkReturn int +hunt_vpd_size( + __in efx_nic_t *enp, + __out size_t *sizep); + +extern __checkReturn int +hunt_vpd_read( + __in efx_nic_t *enp, + __out_bcount(size) caddr_t data, + __in size_t size); + +extern __checkReturn int +hunt_vpd_verify( + __in efx_nic_t *enp, + __in_bcount(size) caddr_t data, + __in size_t size); + +extern __checkReturn int +hunt_vpd_reinit( + __in efx_nic_t *enp, + __in_bcount(size) caddr_t data, + __in size_t size); + +extern __checkReturn int +hunt_vpd_get( + __in efx_nic_t *enp, + __in_bcount(size) caddr_t data, + __in size_t size, + __inout efx_vpd_value_t *evvp); + +extern __checkReturn int +hunt_vpd_set( + __in efx_nic_t *enp, + __in_bcount(size) caddr_t data, + __in size_t size, + __in efx_vpd_value_t *evvp); + +extern __checkReturn int +hunt_vpd_next( + __in efx_nic_t *enp, + __in_bcount(size) caddr_t data, + __in size_t size, + __out efx_vpd_value_t *evvp, + __inout unsigned int *contp); + +extern __checkReturn int +hunt_vpd_write( + __in efx_nic_t *enp, + __in_bcount(size) caddr_t data, + __in size_t size); + +extern void +hunt_vpd_fini( + __in efx_nic_t *enp); + +#endif /* EFSYS_OPT_VPD */ + + +/* RX */ + +extern __checkReturn int +hunt_rx_init( + __in efx_nic_t *enp); + +#if EFSYS_OPT_RX_HDR_SPLIT +extern __checkReturn int +hunt_rx_hdr_split_enable( + __in efx_nic_t *enp, + __in unsigned int hdr_buf_size, + __in unsigned int pld_buf_size); +#endif /* EFSYS_OPT_RX_HDR_SPLIT */ + +#if EFSYS_OPT_RX_SCATTER +extern __checkReturn int +hunt_rx_scatter_enable( + __in efx_nic_t *enp, + __in unsigned int buf_size); +#endif /* EFSYS_OPT_RX_SCATTER */ + + +#if EFSYS_OPT_RX_SCALE + +extern __checkReturn int +hunt_rx_scale_mode_set( + __in efx_nic_t *enp, + __in efx_rx_hash_alg_t alg, + __in efx_rx_hash_type_t type, + __in boolean_t insert); + +extern __checkReturn int +hunt_rx_scale_key_set( + __in efx_nic_t *enp, + __in_ecount(n) uint8_t *key, + __in size_t n); + +extern __checkReturn int +hunt_rx_scale_tbl_set( + __in efx_nic_t *enp, + __in_ecount(n) unsigned int *table, + __in size_t n); + +#endif /* EFSYS_OPT_RX_SCALE */ + +extern void +hunt_rx_qpost( + __in efx_rxq_t *erp, + __in_ecount(n) efsys_dma_addr_t *addrp, + __in size_t size, + __in unsigned int n, + __in unsigned int completed, + __in unsigned int added); + +extern void +hunt_rx_qpush( + __in efx_rxq_t *erp, + __in unsigned int added, + __inout unsigned int *pushedp); + +extern __checkReturn int +hunt_rx_qflush( + __in efx_rxq_t *erp); + +extern void +hunt_rx_qenable( + __in efx_rxq_t *erp); + +extern __checkReturn int +hunt_rx_qcreate( + __in efx_nic_t *enp, + __in unsigned int index, + __in unsigned int label, + __in efx_rxq_type_t type, + __in efsys_mem_t *esmp, + __in size_t n, + __in uint32_t id, + __in efx_evq_t *eep, + __in efx_rxq_t *erp); + +extern void +hunt_rx_qdestroy( + __in efx_rxq_t *erp); + +extern void +hunt_rx_fini( + __in efx_nic_t *enp); + +#if EFSYS_OPT_FILTER + +typedef struct hunt_filter_handle_s { + uint32_t hfh_lo; + uint32_t hfh_hi; +} hunt_filter_handle_t; + +typedef struct hunt_filter_entry_s { + uintptr_t hfe_spec; /* pointer to filter spec plus busy bit */ + hunt_filter_handle_t hfe_handle; +} hunt_filter_entry_t; + +/* + * BUSY flag indicates that an update is in progress. + * AUTO_OLD flag is used to mark and sweep MAC packet filters. + */ +#define EFX_HUNT_FILTER_FLAG_BUSY 1U +#define EFX_HUNT_FILTER_FLAG_AUTO_OLD 2U +#define EFX_HUNT_FILTER_FLAGS 3U + +#define EFX_HUNT_FILTER_TBL_ROWS 8192 + +/* Allow for the broadcast address to be added to the multicast list */ +#define EFX_HUNT_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1) + +typedef struct hunt_filter_table_s { + hunt_filter_entry_t hft_entry[EFX_HUNT_FILTER_TBL_ROWS]; + efx_rxq_t * hft_default_rxq; + boolean_t hft_using_rss; + uint32_t hft_unicst_filter_index; + boolean_t hft_unicst_filter_set; + uint32_t hft_mulcst_filter_indexes[ + EFX_HUNT_FILTER_MULTICAST_FILTERS_MAX]; + uint32_t hft_mulcst_filter_count; +} hunt_filter_table_t; + + __checkReturn int +hunt_filter_init( + __in efx_nic_t *enp); + + void +hunt_filter_fini( + __in efx_nic_t *enp); + + __checkReturn int +hunt_filter_restore( + __in efx_nic_t *enp); + + __checkReturn int +hunt_filter_add( + __in efx_nic_t *enp, + __inout efx_filter_spec_t *spec, + __in boolean_t may_replace); + + __checkReturn int +hunt_filter_delete( + __in efx_nic_t *enp, + __inout efx_filter_spec_t *spec); + +extern __checkReturn int +hunt_filter_supported_filters( + __in efx_nic_t *enp, + __out uint32_t *list, + __out size_t *length); + +extern __checkReturn int +hunt_filter_reconfigure( + __in efx_nic_t *enp, + __in_ecount(6) uint8_t const *mac_addr, + __in boolean_t all_unicst, + __in boolean_t mulcst, + __in boolean_t all_mulcst, + __in boolean_t brdcst, + __in_ecount(6*count) uint8_t const *addrs, + __in int count); + +extern void +hunt_filter_get_default_rxq( + __in efx_nic_t *enp, + __out efx_rxq_t **erpp, + __out boolean_t *using_rss); + +extern void +hunt_filter_default_rxq_set( + __in efx_nic_t *enp, + __in efx_rxq_t *erp, + __in boolean_t using_rss); + +extern void +hunt_filter_default_rxq_clear( + __in efx_nic_t *enp); + + +#endif /* EFSYS_OPT_FILTER */ + +extern __checkReturn int +hunt_pktfilter_set( + __in efx_nic_t *enp, + __in boolean_t unicst, + __in boolean_t brdcst); + +#if EFSYS_OPT_MCAST_FILTER_LIST + +extern __checkReturn int +hunt_pktfilter_mcast_set( + __in efx_nic_t *enp, + __in uint8_t const *addrs, + __in int count); + +#endif /* EFSYS_OPT_MCAST_FILTER_LIST */ + +extern __checkReturn int +hunt_pktfilter_mcast_all( + __in efx_nic_t *enp); + +extern __checkReturn int +efx_mcdi_get_function_info( + __in efx_nic_t *enp, + __out uint32_t *pfp, + __out_opt uint32_t *vfp); + +extern __checkReturn int +efx_mcdi_privilege_mask( + __in efx_nic_t *enp, + __in uint32_t pf, + __in uint32_t vf, + __out uint32_t *maskp); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_HUNT_IMPL_H */ Property changes on: head/sys/dev/sfxge/common/hunt_impl.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/hunt_intr.c =================================================================== --- head/sys/dev/sfxge/common/hunt_intr.c (nonexistent) +++ head/sys/dev/sfxge/common/hunt_intr.c (revision 283514) @@ -0,0 +1,155 @@ +/*- + * Copyright (c) 2012-2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "efsys.h" +#include "efx.h" +#include "efx_impl.h" + + +#if EFSYS_OPT_HUNTINGTON + + __checkReturn int +hunt_intr_init( + __in efx_nic_t *enp, + __in efx_intr_type_t type, + __in efsys_mem_t *esmp) +{ + _NOTE(ARGUNUSED(enp, type, esmp)) + return (0); +} + + + void +hunt_intr_enable( + __in efx_nic_t *enp) +{ + _NOTE(ARGUNUSED(enp)) +} + + + void +hunt_intr_disable( + __in efx_nic_t *enp) +{ + _NOTE(ARGUNUSED(enp)) +} + + + void +hunt_intr_disable_unlocked( + __in efx_nic_t *enp) +{ + _NOTE(ARGUNUSED(enp)) +} + + +static __checkReturn int +efx_mcdi_trigger_interrupt( + __in efx_nic_t *enp, + __in unsigned int level) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_TRIGGER_INTERRUPT_IN_LEN, + MC_CMD_TRIGGER_INTERRUPT_OUT_LEN)]; + int rc; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + + if (level >= enp->en_nic_cfg.enc_intr_limit) { + rc = EINVAL; + goto fail1; + } + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_TRIGGER_INTERRUPT; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_TRIGGER_INTERRUPT_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_TRIGGER_INTERRUPT_OUT_LEN; + + MCDI_IN_SET_DWORD(req, TRIGGER_INTERRUPT_IN_INTR_LEVEL, level); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail2; + } + + return (0); + +fail2: + EFSYS_PROBE(fail2); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_intr_trigger( + __in efx_nic_t *enp, + __in unsigned int level) +{ + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + int rc; + + if (encp->enc_bug41750_workaround) { + /* bug 41750: Test interrupts don't work on Greenport */ + rc = ENOTSUP; + goto fail1; + } + + if ((rc = efx_mcdi_trigger_interrupt(enp, level)) != 0) + goto fail2; + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + + void +hunt_intr_fini( + __in efx_nic_t *enp) +{ + _NOTE(ARGUNUSED(enp)) +} + +#endif /* EFSYS_OPT_HUNTINGTON */ Property changes on: head/sys/dev/sfxge/common/hunt_intr.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/hunt_mac.c =================================================================== --- head/sys/dev/sfxge/common/hunt_mac.c (nonexistent) +++ head/sys/dev/sfxge/common/hunt_mac.c (revision 283514) @@ -0,0 +1,685 @@ +/*- + * Copyright (c) 2012-2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "efsys.h" +#include "efx.h" +#include "efx_impl.h" + + +#if EFSYS_OPT_HUNTINGTON + + __checkReturn int +hunt_mac_poll( + __in efx_nic_t *enp, + __out efx_link_mode_t *link_modep) +{ + /* + * TBD: Consider a common Siena/Huntington function. The code is + * essentially identical. + */ + + efx_port_t *epp = &(enp->en_port); + hunt_link_state_t hls; + int rc; + + if ((rc = hunt_phy_get_link(enp, &hls)) != 0) + goto fail1; + + epp->ep_adv_cap_mask = hls.hls_adv_cap_mask; + epp->ep_fcntl = hls.hls_fcntl; + + *link_modep = hls.hls_link_mode; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + *link_modep = EFX_LINK_UNKNOWN; + + return (rc); +} + + __checkReturn int +hunt_mac_up( + __in efx_nic_t *enp, + __out boolean_t *mac_upp) +{ + /* + * TBD: Consider a common Siena/Huntington function. The code is + * essentially identical. + */ + + hunt_link_state_t hls; + int rc; + + /* + * Because Huntington doesn't *require* polling, we can't rely on + * hunt_mac_poll() being executed to populate epp->ep_mac_up. + */ + if ((rc = hunt_phy_get_link(enp, &hls)) != 0) + goto fail1; + + *mac_upp = hls.hls_mac_up; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +/* + * Huntington uses MC_CMD_VADAPTOR_SET_MAC to set the + * MAC address; the address field in MC_CMD_SET_MAC has no + * effect. + * MC_CMD_VADAPTOR_SET_MAC requires mac-spoofing privilege and + * the port to have no filters or queues active. + */ +static __checkReturn int +efx_mcdi_vadapter_set_mac( + __in efx_nic_t *enp) +{ + efx_port_t *epp = &(enp->en_port); + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_VADAPTOR_SET_MAC_IN_LEN, + MC_CMD_VADAPTOR_SET_MAC_OUT_LEN)]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_VADAPTOR_SET_MAC; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_VADAPTOR_SET_MAC_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_VADAPTOR_SET_MAC_OUT_LEN; + + MCDI_IN_SET_DWORD(req, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID, + enp->en_vport_id); + EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t, VADAPTOR_SET_MAC_IN_MACADDR), + epp->ep_mac_addr); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_mac_addr_set( + __in efx_nic_t *enp) +{ + int rc; + + if ((rc = efx_mcdi_vadapter_set_mac(enp)) != 0) + goto fail1; + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +__checkReturn int +hunt_mac_reconfigure( + __in efx_nic_t *enp) +{ + efx_port_t *epp = &(enp->en_port); + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_SET_MAC_IN_LEN, + MC_CMD_SET_MAC_OUT_LEN)]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_SET_MAC; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_SET_MAC_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_SET_MAC_OUT_LEN; + + MCDI_IN_SET_DWORD(req, SET_MAC_IN_MTU, epp->ep_mac_pdu); + MCDI_IN_SET_DWORD(req, SET_MAC_IN_DRAIN, epp->ep_mac_drain ? 1 : 0); + EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t, SET_MAC_IN_ADDR), + epp->ep_mac_addr); + + /* + * Note: The Huntington MAC does not support REJECT_BRDCST. + * The REJECT_UNCST flag will also prevent multicast traffic + * from reaching the filters. As Huntington filters drop any + * traffic that does not match a filter it is ok to leave the + * MAC running in promiscuous mode. See bug41141. + */ + MCDI_IN_POPULATE_DWORD_2(req, SET_MAC_IN_REJECT, + SET_MAC_IN_REJECT_UNCST, 0, + SET_MAC_IN_REJECT_BRDCST, 0); + + /* + * Flow control, whether it is auto-negotiated or not, + * is set via the PHY advertised capabilities. When set to + * automatic the MAC will use the PHY settings to determine + * the flow control settings. + */ + MCDI_IN_SET_DWORD(req, SET_MAC_IN_FCNTL, MC_CMD_FCNTL_AUTO); + + /* Do not include the Ethernet frame checksum in RX packets */ + MCDI_IN_POPULATE_DWORD_1(req, SET_MAC_IN_FLAGS, + SET_MAC_IN_FLAG_INCLUDE_FCS, 0); + + efx_mcdi_execute_quiet(enp, &req); + + if (req.emr_rc != 0) { + /* + * Unprivileged functions cannot control link state, + * but still need to configure filters. + */ + if (req.emr_rc != EACCES) { + rc = req.emr_rc; + goto fail1; + } + } + + /* + * Apply the filters for the MAC configuration. + * If the NIC isn't ready to accept filters this may + * return success without setting anything. + */ + rc = efx_filter_reconfigure(enp, epp->ep_mac_addr, + epp->ep_all_unicst, epp->ep_mulcst, + epp->ep_all_mulcst, epp->ep_brdcst, + epp->ep_mulcst_addr_list, + epp->ep_mulcst_addr_count); + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_mac_multicast_list_set( + __in efx_nic_t *enp) +{ + efx_port_t *epp = &(enp->en_port); + efx_mac_ops_t *emop = epp->ep_emop; + int rc; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + + /* FIXME: Insert filters for multicast list */ + + if ((rc = emop->emo_reconfigure(enp)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_mac_filter_default_rxq_set( + __in efx_nic_t *enp, + __in efx_rxq_t *erp, + __in boolean_t using_rss) +{ + efx_port_t *epp = &(enp->en_port); + efx_rxq_t *old_rxq; + boolean_t old_using_rss; + int rc; + + hunt_filter_get_default_rxq(enp, &old_rxq, &old_using_rss); + + hunt_filter_default_rxq_set(enp, erp, using_rss); + + rc = efx_filter_reconfigure(enp, epp->ep_mac_addr, + epp->ep_all_unicst, epp->ep_mulcst, + epp->ep_all_mulcst, epp->ep_brdcst, + epp->ep_mulcst_addr_list, + epp->ep_mulcst_addr_count); + + if (rc != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + hunt_filter_default_rxq_set(enp, old_rxq, old_using_rss); + + return (rc); +} + + void +hunt_mac_filter_default_rxq_clear( + __in efx_nic_t *enp) +{ + efx_port_t *epp = &(enp->en_port); + + hunt_filter_default_rxq_clear(enp); + + efx_filter_reconfigure(enp, epp->ep_mac_addr, + epp->ep_all_unicst, epp->ep_mulcst, + epp->ep_all_mulcst, epp->ep_brdcst, + epp->ep_mulcst_addr_list, + epp->ep_mulcst_addr_count); +} + + +#if EFSYS_OPT_LOOPBACK + + __checkReturn int +hunt_mac_loopback_set( + __in efx_nic_t *enp, + __in efx_link_mode_t link_mode, + __in efx_loopback_type_t loopback_type) +{ + /* + * TBD: Consider a common Siena/Huntington function. The code is + * essentially identical. + */ + + efx_port_t *epp = &(enp->en_port); + efx_phy_ops_t *epop = epp->ep_epop; + efx_loopback_type_t old_loopback_type; + efx_link_mode_t old_loopback_link_mode; + int rc; + + /* The PHY object handles this on Huntington */ + old_loopback_type = epp->ep_loopback_type; + old_loopback_link_mode = epp->ep_loopback_link_mode; + epp->ep_loopback_type = loopback_type; + epp->ep_loopback_link_mode = link_mode; + + if ((rc = epop->epo_reconfigure(enp)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE(fail2); + + epp->ep_loopback_type = old_loopback_type; + epp->ep_loopback_link_mode = old_loopback_link_mode; + + return (rc); +} + +#endif /* EFSYS_OPT_LOOPBACK */ + +#if EFSYS_OPT_MAC_STATS + +#define HUNT_MAC_STAT_READ(_esmp, _field, _eqp) \ + EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp) + + + __checkReturn int +hunt_mac_stats_update( + __in efx_nic_t *enp, + __in efsys_mem_t *esmp, + __out_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, + __out_opt uint32_t *generationp) +{ + efx_qword_t value; + efx_qword_t generation_start; + efx_qword_t generation_end; + + _NOTE(ARGUNUSED(enp)) + + /* Read END first so we don't race with the MC */ + EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFX_MAC_STATS_SIZE); + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_END, + &generation_end); + EFSYS_MEM_READ_BARRIER(); + + /* TX */ + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_CONTROL_PKTS, &value); + EFSYS_STAT_SUBR_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PAUSE_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PAUSE_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_UNICAST_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_UNICST_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTICAST_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULTICST_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BROADCAST_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_BRDCST_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BYTES, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_OCTETS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LT64_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value); + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_64_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_65_TO_127_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_65_TO_127_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_128_TO_255_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_128_TO_255_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_256_TO_511_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_256_TO_511_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_512_TO_1023_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_512_TO_1023_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_1024_TO_15XX_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_1024_TO_15XX_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value); + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_GTJUMBO_PKTS, &value); + EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BAD_FCS_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_ERRORS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_SGL_COL_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS, + &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULT_COL_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS, + &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_COL_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LATE_COLLISION_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LATE_COL_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_DEFERRED_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_DEF_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS, + &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_DEF_PKTS]), &value); + + /* RX */ + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BYTES, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_OCTETS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNICAST_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_UNICST_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MULTICAST_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MULTICST_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BROADCAST_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_BRDCST_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PAUSE_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PAUSE_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNDERSIZE_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value); + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_64_PKTS, &value); + EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_65_TO_127_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_65_TO_127_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_128_TO_255_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_128_TO_255_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_256_TO_511_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_256_TO_511_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_512_TO_1023_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_512_TO_1023_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_1024_TO_15XX_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_1024_TO_15XX_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value); + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_GTJUMBO_PKTS, &value); + EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BAD_FCS_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FCS_ERRORS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_OVERFLOW_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_DROP_EVENTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_FALSE_CARRIER_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FALSE_CARRIER_ERRORS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_SYMBOL_ERRORS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_ALIGN_ERROR_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_ALIGN_ERRORS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_INTERNAL_ERRORS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_JABBER_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_JABBER_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_CHAR_ERR, &value); + EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_CHAR_ERR]), + &(value.eq_dword[0])); + EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_CHAR_ERR]), + &(value.eq_dword[1])); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_CHAR_ERR, &value); + EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_CHAR_ERR]), + &(value.eq_dword[0])); + EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_CHAR_ERR]), + &(value.eq_dword[1])); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_DISP_ERR, &value); + EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_DISP_ERR]), + &(value.eq_dword[0])); + EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_DISP_ERR]), + &(value.eq_dword[1])); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_DISP_ERR, &value); + EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_DISP_ERR]), + &(value.eq_dword[0])); + EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_DISP_ERR]), + &(value.eq_dword[1])); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MATCH_FAULT, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MATCH_FAULT]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_NODESC_DROPS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_NODESC_DROP_CNT]), &value); + + /* Packet memory (EF10 only) */ + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_TRUNC_BB_OVERFLOW]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_BB_OVERFLOW]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_TRUNC_VFIFO_FULL, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_TRUNC_VFIFO_FULL]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_VFIFO_FULL, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_VFIFO_FULL]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_TRUNC_QBB, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_TRUNC_QBB]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_QBB, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_QBB]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_MAPPING, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_MAPPING]), &value); + + /* RX datapath */ + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_Q_DISABLED_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_Q_DISABLED_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_DI_DROPPED_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_DI_DROPPED_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_STREAMING_PKTS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_STREAMING_PKTS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_HLB_FETCH]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_HLB_WAIT]), &value); + + + /* VADAPTER RX */ + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS, + &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_UNICAST_PACKETS]), + &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES, + &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_UNICAST_BYTES]), + &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS, + &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS]), + &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES, + &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_MULTICAST_BYTES]), + &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS, + &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS]), + &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES, + &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BROADCAST_BYTES]), + &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS, + &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BAD_PACKETS]), + &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BAD_BYTES, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BAD_BYTES]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_OVERFLOW, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_OVERFLOW]), &value); + + /* VADAPTER TX */ + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS, + &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_UNICAST_PACKETS]), + &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES, + &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_UNICAST_BYTES]), + &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS, + &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS]), + &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES, + &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_MULTICAST_BYTES]), + &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS, + &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS]), + &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES, + &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BROADCAST_BYTES]), + &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BAD_PACKETS]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BAD_BYTES, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BAD_BYTES]), &value); + + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_OVERFLOW, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_OVERFLOW]), &value); + + + EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFX_MAC_STATS_SIZE); + EFSYS_MEM_READ_BARRIER(); + HUNT_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_START, + &generation_start); + + /* Check that we didn't read the stats in the middle of a DMA */ + /* Not a good enough check ? */ + if (memcmp(&generation_start, &generation_end, + sizeof (generation_start))) + return (EAGAIN); + + if (generationp) + *generationp = EFX_QWORD_FIELD(generation_start, EFX_DWORD_0); + + return (0); +} + +#endif /* EFSYS_OPT_MAC_STATS */ + +#endif /* EFSYS_OPT_HUNTINGTON */ Property changes on: head/sys/dev/sfxge/common/hunt_mac.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/hunt_mcdi.c =================================================================== --- head/sys/dev/sfxge/common/hunt_mcdi.c (nonexistent) +++ head/sys/dev/sfxge/common/hunt_mcdi.c (revision 283514) @@ -0,0 +1,465 @@ +/*- + * Copyright (c) 2012-2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "efsys.h" +#include "efx.h" +#include "efx_impl.h" + + +#if EFSYS_OPT_HUNTINGTON + +#if EFSYS_OPT_MCDI + +#ifndef WITH_MCDI_V2 +#error "WITH_MCDI_V2 required for Huntington MCDIv2 commands." +#endif + +typedef enum efx_mcdi_header_type_e { + EFX_MCDI_HEADER_TYPE_V1, /* MCDIv0 (BootROM), MCDIv1 commands */ + EFX_MCDI_HEADER_TYPE_V2, /* MCDIv2 commands */ +} efx_mcdi_header_type_t; + +/* + * Return the header format to use for sending an MCDI request. + * + * An MCDIv1 (Siena compatible) command should use MCDIv2 encapsulation if the + * request input buffer or response output buffer are too large for the MCDIv1 + * format. An MCDIv2 command must always be sent using MCDIv2 encapsulation. + */ +#define EFX_MCDI_HEADER_TYPE(_cmd, _length) \ + ((((_cmd) & ~EFX_MASK32(MCDI_HEADER_CODE)) || \ + ((_length) & ~EFX_MASK32(MCDI_HEADER_DATALEN))) ? \ + EFX_MCDI_HEADER_TYPE_V2 : EFX_MCDI_HEADER_TYPE_V1) + + +/* + * MCDI Header NOT_EPOCH flag + * ========================== + * A new epoch begins at initial startup or after an MC reboot, and defines when + * the MC should reject stale MCDI requests. + * + * The first MCDI request sent by the host should contain NOT_EPOCH=0, and all + * subsequent requests (until the next MC reboot) should contain NOT_EPOCH=1. + * + * After rebooting the MC will fail all requests with NOT_EPOCH=1 by writing a + * response with ERROR=1 and DATALEN=0 until a request is seen with NOT_EPOCH=0. + */ + + + __checkReturn int +hunt_mcdi_init( + __in efx_nic_t *enp, + __in const efx_mcdi_transport_t *emtp) +{ + efsys_mem_t *esmp = emtp->emt_dma_mem; + efx_dword_t dword; + int rc; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_features & EFX_FEATURE_MCDI_DMA); + + /* A host DMA buffer is required for Huntington MCDI */ + if (esmp == NULL) { + rc = EINVAL; + goto fail1; + } + + /* + * Ensure that the MC doorbell is in a known state before issuing MCDI + * commands. The recovery algorithm requires that the MC command buffer + * must be 256 byte aligned. See bug24769. + */ + if ((EFSYS_MEM_ADDR(esmp) & 0xFF) != 0) { + rc = EINVAL; + goto fail2; + } + EFX_POPULATE_DWORD_1(dword, EFX_DWORD_0, 1); + EFX_BAR_WRITED(enp, ER_DZ_MC_DB_HWRD_REG, &dword, B_FALSE); + + /* Save initial MC reboot status */ + (void) hunt_mcdi_poll_reboot(enp); + + /* Start a new epoch (allow fresh MCDI requests to succeed) */ + efx_mcdi_new_epoch(enp); + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + void +hunt_mcdi_fini( + __in efx_nic_t *enp) +{ + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + + emip->emi_new_epoch = B_FALSE; +} + + void +hunt_mcdi_request_copyin( + __in efx_nic_t *enp, + __in efx_mcdi_req_t *emrp, + __in unsigned int seq, + __in boolean_t ev_cpl, + __in boolean_t new_epoch) +{ + const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; + efsys_mem_t *esmp = emtp->emt_dma_mem; + efx_mcdi_header_type_t hdr_type; + efx_dword_t dword; + unsigned int xflags; + unsigned int pos; + size_t offset; + + EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON); + + xflags = 0; + if (ev_cpl) + xflags |= MCDI_HEADER_XFLAGS_EVREQ; + + offset = 0; + + hdr_type = EFX_MCDI_HEADER_TYPE(emrp->emr_cmd, + MAX(emrp->emr_in_length, emrp->emr_out_length)); + + if (hdr_type == EFX_MCDI_HEADER_TYPE_V2) { + /* Construct MCDI v2 header */ + EFX_POPULATE_DWORD_8(dword, + MCDI_HEADER_CODE, MC_CMD_V2_EXTN, + MCDI_HEADER_RESYNC, 1, + MCDI_HEADER_DATALEN, 0, + MCDI_HEADER_SEQ, seq, + MCDI_HEADER_NOT_EPOCH, new_epoch ? 0 : 1, + MCDI_HEADER_ERROR, 0, + MCDI_HEADER_RESPONSE, 0, + MCDI_HEADER_XFLAGS, xflags); + EFSYS_MEM_WRITED(esmp, offset, &dword); + offset += sizeof (dword); + + EFX_POPULATE_DWORD_2(dword, + MC_CMD_V2_EXTN_IN_EXTENDED_CMD, emrp->emr_cmd, + MC_CMD_V2_EXTN_IN_ACTUAL_LEN, emrp->emr_in_length); + EFSYS_MEM_WRITED(esmp, offset, &dword); + offset += sizeof (dword); + } else { + /* Construct MCDI v1 header */ + EFX_POPULATE_DWORD_8(dword, + MCDI_HEADER_CODE, emrp->emr_cmd, + MCDI_HEADER_RESYNC, 1, + MCDI_HEADER_DATALEN, emrp->emr_in_length, + MCDI_HEADER_SEQ, seq, + MCDI_HEADER_NOT_EPOCH, new_epoch ? 0 : 1, + MCDI_HEADER_ERROR, 0, + MCDI_HEADER_RESPONSE, 0, + MCDI_HEADER_XFLAGS, xflags); + EFSYS_MEM_WRITED(esmp, offset, &dword); + offset += sizeof (dword); + } + + /* Construct the payload */ + for (pos = 0; pos < emrp->emr_in_length; pos += sizeof (efx_dword_t)) { + memcpy(&dword, MCDI_IN(*emrp, efx_dword_t, pos), + MIN(sizeof (dword), emrp->emr_in_length - pos)); + EFSYS_MEM_WRITED(esmp, offset + pos, &dword); + } + + /* Ring the doorbell to post the command DMA address to the MC */ + EFSYS_ASSERT((EFSYS_MEM_ADDR(esmp) & 0xFF) == 0); + + /* Guarantee ordering of memory (MCDI request) and PIO (MC doorbell) */ + EFSYS_DMA_SYNC_FOR_DEVICE(esmp, 0, offset + emrp->emr_in_length); + EFSYS_PIO_WRITE_BARRIER(); + + EFX_POPULATE_DWORD_1(dword, + EFX_DWORD_0, EFSYS_MEM_ADDR(esmp) >> 32); + EFX_BAR_WRITED(enp, ER_DZ_MC_DB_LWRD_REG, &dword, B_FALSE); + + EFX_POPULATE_DWORD_1(dword, + EFX_DWORD_0, EFSYS_MEM_ADDR(esmp) & 0xffffffff); + EFX_BAR_WRITED(enp, ER_DZ_MC_DB_HWRD_REG, &dword, B_FALSE); +} + + void +hunt_mcdi_request_copyout( + __in efx_nic_t *enp, + __in efx_mcdi_req_t *emrp) +{ + const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; + efsys_mem_t *esmp = emtp->emt_dma_mem; + unsigned int pos; + unsigned int offset; + efx_dword_t hdr; + efx_dword_t hdr2; + efx_dword_t data; + size_t bytes; + + if (emrp->emr_out_buf == NULL) + return; + + /* Read the command header to detect MCDI response format */ + EFSYS_MEM_READD(esmp, 0, &hdr); + if (EFX_DWORD_FIELD(hdr, MCDI_HEADER_CODE) == MC_CMD_V2_EXTN) { + offset = 2 * sizeof (efx_dword_t); + + /* + * Read the actual payload length. The length given in the event + * is only correct for responses with the V1 format. + */ + EFSYS_MEM_READD(esmp, sizeof (efx_dword_t), &hdr2); + emrp->emr_out_length_used = EFX_DWORD_FIELD(hdr2, + MC_CMD_V2_EXTN_IN_ACTUAL_LEN); + } else { + offset = sizeof (efx_dword_t); + } + + /* Copy payload out into caller supplied buffer */ + bytes = MIN(emrp->emr_out_length_used, emrp->emr_out_length); + for (pos = 0; pos < bytes; pos += sizeof (efx_dword_t)) { + EFSYS_MEM_READD(esmp, offset + pos, &data); + memcpy(MCDI_OUT(*emrp, efx_dword_t, pos), &data, + MIN(sizeof (data), bytes - pos)); + } +} + + __checkReturn boolean_t +hunt_mcdi_request_poll( + __in efx_nic_t *enp) +{ + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; + efsys_mem_t *esmp = emtp->emt_dma_mem; + efx_mcdi_req_t *emrp; + efx_dword_t dword; + unsigned int seq; + unsigned int cmd; + unsigned int length; + size_t offset; + int state; + int rc; + + EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON); + + /* Serialise against post-watchdog efx_mcdi_ev* */ + EFSYS_LOCK(enp->en_eslp, state); + + EFSYS_ASSERT(emip->emi_pending_req != NULL); + EFSYS_ASSERT(!emip->emi_ev_cpl); + emrp = emip->emi_pending_req; + + offset = 0; + + /* Read the command header */ + EFSYS_MEM_READD(esmp, offset, &dword); + offset += sizeof (efx_dword_t); + if (EFX_DWORD_FIELD(dword, MCDI_HEADER_RESPONSE) == 0) { + EFSYS_UNLOCK(enp->en_eslp, state); + return (B_FALSE); + } + if (EFX_DWORD_FIELD(dword, MCDI_HEADER_CODE) == MC_CMD_V2_EXTN) { + efx_dword_t dword2; + + EFSYS_MEM_READD(esmp, offset, &dword2); + offset += sizeof (efx_dword_t); + + cmd = EFX_DWORD_FIELD(dword2, MC_CMD_V2_EXTN_IN_EXTENDED_CMD); + length = EFX_DWORD_FIELD(dword2, MC_CMD_V2_EXTN_IN_ACTUAL_LEN); + } else { + cmd = EFX_DWORD_FIELD(dword, MCDI_HEADER_CODE); + length = EFX_DWORD_FIELD(dword, MCDI_HEADER_DATALEN); + } + + /* Request complete */ + emip->emi_pending_req = NULL; + seq = (emip->emi_seq - 1) & EFX_MASK32(MCDI_HEADER_SEQ); + + /* Check for synchronous reboot */ + if (EFX_DWORD_FIELD(dword, MCDI_HEADER_ERROR) != 0 && length == 0) { + /* The MC has rebooted since the request was sent. */ + EFSYS_SPIN(EFX_MCDI_STATUS_SLEEP_US); + hunt_mcdi_poll_reboot(enp); + + EFSYS_UNLOCK(enp->en_eslp, state); + rc = EIO; + goto fail1; + } + + /* Ensure stale MCDI requests fail after an MC reboot. */ + emip->emi_new_epoch = B_FALSE; + + EFSYS_UNLOCK(enp->en_eslp, state); + + /* Check that the returned data is consistent */ + if (cmd != emrp->emr_cmd || + EFX_DWORD_FIELD(dword, MCDI_HEADER_SEQ) != seq) { + /* Response is for a different request */ + rc = EIO; + goto fail2; + } + if (EFX_DWORD_FIELD(dword, MCDI_HEADER_ERROR)) { + efx_dword_t errdword; + int errcode; + int argnum; + + /* Read error code (and arg num for MCDI v2 commands) */ + EFSYS_MEM_READD(esmp, offset + MC_CMD_ERR_CODE_OFST, &errdword); + errcode = EFX_DWORD_FIELD(errdword, EFX_DWORD_0); + + EFSYS_MEM_READD(esmp, offset + MC_CMD_ERR_ARG_OFST, &errdword); + argnum = EFX_DWORD_FIELD(errdword, EFX_DWORD_0); + + rc = efx_mcdi_request_errcode(errcode); + if (!emrp->emr_quiet) { + EFSYS_PROBE3(mcdi_err_arg, int, emrp->emr_cmd, + int, errcode, int, argnum); + } + goto fail3; + + } else { + emrp->emr_out_length_used = length; + emrp->emr_rc = 0; + hunt_mcdi_request_copyout(enp, emrp); + } + + goto out; + +fail3: + if (!emrp->emr_quiet) + EFSYS_PROBE(fail3); +fail2: + if (!emrp->emr_quiet) + EFSYS_PROBE(fail2); +fail1: + if (!emrp->emr_quiet) + EFSYS_PROBE1(fail1, int, rc); + + /* Fill out error state */ + emrp->emr_rc = rc; + emrp->emr_out_length_used = 0; + + /* Reboot/Assertion */ + if (rc == EIO || rc == EINTR) + efx_mcdi_raise_exception(enp, emrp, rc); + +out: + return (B_TRUE); +} + + int +hunt_mcdi_poll_reboot( + __in efx_nic_t *enp) +{ + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + efx_dword_t dword; + uint32_t old_status; + uint32_t new_status; + int rc; + + old_status = emip->emi_mc_reboot_status; + + /* Update MC reboot status word */ + EFX_BAR_TBL_READD(enp, ER_DZ_BIU_MC_SFT_STATUS_REG, 0, &dword, B_FALSE); + new_status = dword.ed_u32[0]; + + /* MC has rebooted if the value has changed */ + if (new_status != old_status) { + emip->emi_mc_reboot_status = new_status; + + /* + * FIXME: Ignore detected MC REBOOT for now. + * + * The Siena support for checking for MC reboot from status + * flags is broken - see comments in siena_mcdi_poll_reboot(). + * As the generic MCDI code is shared the Huntington reboot + * detection suffers similar problems. + * + * Do not report an error when the boot status changes until + * this can be handled by common code drivers (and reworked to + * support Siena too). + */ + if (B_FALSE) { + rc = EIO; + goto fail1; + } + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_mcdi_fw_update_supported( + __in efx_nic_t *enp, + __out boolean_t *supportedp) +{ + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + + EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON); + + /* use privilege mask state at MCDI attach */ + *supportedp = (encp->enc_privilege_mask & + MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN) + == MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN; + + return (0); +} + + __checkReturn int +hunt_mcdi_macaddr_change_supported( + __in efx_nic_t *enp, + __out boolean_t *supportedp) +{ + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + + EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON); + + /* use privilege mask state at MCDI attach */ + *supportedp = (encp->enc_privilege_mask & + MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING) + == MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING; + + return (0); +} + +#endif /* EFSYS_OPT_MCDI */ + +#endif /* EFSYS_OPT_HUNTINGTON */ Property changes on: head/sys/dev/sfxge/common/hunt_mcdi.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/hunt_nic.c =================================================================== --- head/sys/dev/sfxge/common/hunt_nic.c (nonexistent) +++ head/sys/dev/sfxge/common/hunt_nic.c (revision 283514) @@ -0,0 +1,1741 @@ +/*- + * Copyright (c) 2012-2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "efsys.h" +#include "efx.h" +#include "efx_impl.h" +#include "mcdi_mon.h" + +#if EFSYS_OPT_HUNTINGTON + +#include "ef10_tlv_layout.h" + +static __checkReturn int +efx_mcdi_get_port_assignment( + __in efx_nic_t *enp, + __out uint32_t *portp) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN, + MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN)]; + int rc; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN; + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) { + rc = EMSGSIZE; + goto fail2; + } + + *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT); + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static __checkReturn int +efx_mcdi_get_port_modes( + __in efx_nic_t *enp, + __out uint32_t *modesp) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_GET_PORT_MODES_IN_LEN, + MC_CMD_GET_PORT_MODES_OUT_LEN)]; + int rc; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_GET_PORT_MODES; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN; + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + /* Accept pre-Medford size (8 bytes - no CurrentMode field) */ + if (req.emr_out_length_used < + MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) { + rc = EMSGSIZE; + goto fail2; + } + + *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES); + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + +static __checkReturn int +efx_mcdi_vadaptor_alloc( + __in efx_nic_t *enp, + __in uint32_t port_id) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_VADAPTOR_ALLOC_IN_LEN, + MC_CMD_VADAPTOR_ALLOC_OUT_LEN)]; + int rc; + + EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL); + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_VADAPTOR_ALLOC; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN; + + MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static __checkReturn int +efx_mcdi_vadaptor_free( + __in efx_nic_t *enp, + __in uint32_t port_id) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_VADAPTOR_FREE_IN_LEN, + MC_CMD_VADAPTOR_FREE_OUT_LEN)]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_VADAPTOR_FREE; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN; + + MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static __checkReturn int +efx_mcdi_get_mac_address_pf( + __in efx_nic_t *enp, + __out_ecount_opt(6) uint8_t mac_addrp[6]) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_GET_MAC_ADDRESSES_IN_LEN, + MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)]; + int rc; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN; + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) { + rc = EMSGSIZE; + goto fail2; + } + + if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) { + rc = ENOENT; + goto fail3; + } + + if (mac_addrp != NULL) { + uint8_t *addrp; + + addrp = MCDI_OUT2(req, uint8_t, + GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE); + + EFX_MAC_ADDR_COPY(mac_addrp, addrp); + } + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static __checkReturn int +efx_mcdi_get_mac_address_vf( + __in efx_nic_t *enp, + __out_ecount_opt(6) uint8_t mac_addrp[6]) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN, + MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX)]; + int rc; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX; + + MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID, + EVB_PORT_ID_ASSIGNED); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < + MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) { + rc = EMSGSIZE; + goto fail2; + } + + if (MCDI_OUT_DWORD(req, + VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) { + rc = ENOENT; + goto fail3; + } + + if (mac_addrp != NULL) { + uint8_t *addrp; + + addrp = MCDI_OUT2(req, uint8_t, + VPORT_GET_MAC_ADDRESSES_OUT_MACADDR); + + EFX_MAC_ADDR_COPY(mac_addrp, addrp); + } + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static __checkReturn int +efx_mcdi_get_clock( + __in efx_nic_t *enp, + __out uint32_t *sys_freqp) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_GET_CLOCK_IN_LEN, + MC_CMD_GET_CLOCK_OUT_LEN)]; + int rc; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_GET_CLOCK; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN; + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) { + rc = EMSGSIZE; + goto fail2; + } + + *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ); + if (*sys_freqp == 0) { + rc = EINVAL; + goto fail3; + } + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static __checkReturn int +efx_mcdi_get_vector_cfg( + __in efx_nic_t *enp, + __out_opt uint32_t *vec_basep, + __out_opt uint32_t *pf_nvecp, + __out_opt uint32_t *vf_nvecp) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_GET_VECTOR_CFG_IN_LEN, + MC_CMD_GET_VECTOR_CFG_OUT_LEN)]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_GET_VECTOR_CFG; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN; + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) { + rc = EMSGSIZE; + goto fail2; + } + + if (vec_basep != NULL) + *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE); + if (pf_nvecp != NULL) + *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF); + if (vf_nvecp != NULL) + *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF); + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static __checkReturn int +efx_mcdi_get_capabilities( + __in efx_nic_t *enp, + __out efx_dword_t *flagsp) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_GET_CAPABILITIES_IN_LEN, + MC_CMD_GET_CAPABILITIES_OUT_LEN)]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_GET_CAPABILITIES; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_GET_CAPABILITIES_OUT_LEN; + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) { + rc = EMSGSIZE; + goto fail2; + } + + *flagsp = *MCDI_OUT2(req, efx_dword_t, GET_CAPABILITIES_OUT_FLAGS1); + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + +static __checkReturn int +efx_mcdi_alloc_vis( + __in efx_nic_t *enp, + __in uint32_t min_vi_count, + __in uint32_t max_vi_count, + __out_opt uint32_t *vi_basep, + __out uint32_t *vi_countp) + +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_ALLOC_VIS_IN_LEN, + MC_CMD_ALLOC_VIS_OUT_LEN)]; + int rc; + + if (vi_countp == NULL) { + rc = EINVAL; + goto fail1; + } + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_ALLOC_VIS; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_ALLOC_VIS_OUT_LEN; + + MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count); + MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail2; + } + + if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) { + rc = EMSGSIZE; + goto fail3; + } + + if (vi_basep != NULL) + *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE); + + if (vi_countp != NULL) + *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT); + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + +static __checkReturn int +efx_mcdi_free_vis( + __in efx_nic_t *enp) +{ + efx_mcdi_req_t req; + int rc; + + EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0); + EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0); + + req.emr_cmd = MC_CMD_FREE_VIS; + req.emr_in_buf = NULL; + req.emr_in_length = 0; + req.emr_out_buf = NULL; + req.emr_out_length = 0; + + efx_mcdi_execute_quiet(enp, &req); + + /* Ignore ELREADY (no allocated VIs, so nothing to free) */ + if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) { + rc = req.emr_rc; + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + +static __checkReturn int +efx_mcdi_alloc_piobuf( + __in efx_nic_t *enp, + __out efx_piobuf_handle_t *handlep) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_ALLOC_PIOBUF_IN_LEN, + MC_CMD_ALLOC_PIOBUF_OUT_LEN)]; + int rc; + + if (handlep == NULL) { + rc = EINVAL; + goto fail1; + } + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_ALLOC_PIOBUF; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN; + + efx_mcdi_execute_quiet(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail2; + } + + if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) { + rc = EMSGSIZE; + goto fail3; + } + + *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE); + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static __checkReturn int +efx_mcdi_free_piobuf( + __in efx_nic_t *enp, + __out efx_piobuf_handle_t handle) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_FREE_PIOBUF_IN_LEN, + MC_CMD_FREE_PIOBUF_OUT_LEN)]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_FREE_PIOBUF; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN; + + MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle); + + efx_mcdi_execute_quiet(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static __checkReturn int +efx_mcdi_link_piobuf( + __in efx_nic_t *enp, + __in uint32_t vi_index, + __in efx_piobuf_handle_t handle) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_LINK_PIOBUF_IN_LEN, + MC_CMD_LINK_PIOBUF_OUT_LEN)]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_LINK_PIOBUF; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN; + + MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle); + MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static __checkReturn int +efx_mcdi_unlink_piobuf( + __in efx_nic_t *enp, + __in uint32_t vi_index) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_UNLINK_PIOBUF_IN_LEN, + MC_CMD_UNLINK_PIOBUF_OUT_LEN)]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_UNLINK_PIOBUF; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN; + + MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static void +hunt_nic_alloc_piobufs( + __in efx_nic_t *enp, + __in uint32_t max_piobuf_count) +{ + efx_piobuf_handle_t *handlep; + unsigned int i; + int rc; + + EFSYS_ASSERT3U(max_piobuf_count, <=, + EFX_ARRAY_SIZE(enp->en_u.hunt.enu_piobuf_handle)); + + enp->en_u.hunt.enu_piobuf_count = 0; + + for (i = 0; i < max_piobuf_count; i++) { + handlep = &enp->en_u.hunt.enu_piobuf_handle[i]; + + if ((rc = efx_mcdi_alloc_piobuf(enp, handlep)) != 0) + goto fail1; + + enp->en_u.hunt.enu_pio_alloc_map[i] = 0; + enp->en_u.hunt.enu_piobuf_count++; + } + + return; + +fail1: + for (i = 0; i < enp->en_u.hunt.enu_piobuf_count; i++) { + handlep = &enp->en_u.hunt.enu_piobuf_handle[i]; + + efx_mcdi_free_piobuf(enp, *handlep); + *handlep = EFX_PIOBUF_HANDLE_INVALID; + } + enp->en_u.hunt.enu_piobuf_count = 0; +} + + +static void +hunt_nic_free_piobufs( + __in efx_nic_t *enp) +{ + efx_piobuf_handle_t *handlep; + unsigned int i; + + for (i = 0; i < enp->en_u.hunt.enu_piobuf_count; i++) { + handlep = &enp->en_u.hunt.enu_piobuf_handle[i]; + + efx_mcdi_free_piobuf(enp, *handlep); + *handlep = EFX_PIOBUF_HANDLE_INVALID; + } + enp->en_u.hunt.enu_piobuf_count = 0; +} + +/* Sub-allocate a block from a piobuf */ + __checkReturn int +hunt_nic_pio_alloc( + __inout efx_nic_t *enp, + __out uint32_t *bufnump, + __out efx_piobuf_handle_t *handlep, + __out uint32_t *blknump, + __out uint32_t *offsetp, + __out size_t *sizep) +{ + efx_drv_cfg_t *edcp = &enp->en_drv_cfg; + uint32_t blk_per_buf; + uint32_t buf, blk; + int rc; + + EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(bufnump); + EFSYS_ASSERT(handlep); + EFSYS_ASSERT(blknump); + EFSYS_ASSERT(offsetp); + EFSYS_ASSERT(sizep); + + if ((edcp->edc_pio_alloc_size == 0) || + (enp->en_u.hunt.enu_piobuf_count == 0)) { + rc = ENOMEM; + goto fail1; + } + blk_per_buf = HUNT_PIOBUF_SIZE / edcp->edc_pio_alloc_size; + + for (buf = 0; buf < enp->en_u.hunt.enu_piobuf_count; buf++) { + uint32_t *map = &enp->en_u.hunt.enu_pio_alloc_map[buf]; + + if (~(*map) == 0) + continue; + + EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map))); + for (blk = 0; blk < blk_per_buf; blk++) { + if ((*map & (1u << blk)) == 0) { + *map |= (1u << blk); + goto done; + } + } + } + rc = ENOMEM; + goto fail2; + +done: + *handlep = enp->en_u.hunt.enu_piobuf_handle[buf]; + *bufnump = buf; + *blknump = blk; + *sizep = edcp->edc_pio_alloc_size; + *offsetp = blk * (*sizep); + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +/* Free a piobuf sub-allocated block */ + __checkReturn int +hunt_nic_pio_free( + __inout efx_nic_t *enp, + __in uint32_t bufnum, + __in uint32_t blknum) +{ + uint32_t *map; + int rc; + + if ((bufnum >= enp->en_u.hunt.enu_piobuf_count) || + (blknum >= (8 * sizeof (*map)))) { + rc = EINVAL; + goto fail1; + } + + map = &enp->en_u.hunt.enu_pio_alloc_map[bufnum]; + if ((*map & (1u << blknum)) == 0) { + rc = ENOENT; + goto fail2; + } + *map &= ~(1u << blknum); + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_nic_pio_link( + __inout efx_nic_t *enp, + __in uint32_t vi_index, + __in efx_piobuf_handle_t handle) +{ + return (efx_mcdi_link_piobuf(enp, vi_index, handle)); +} + + __checkReturn int +hunt_nic_pio_unlink( + __inout efx_nic_t *enp, + __in uint32_t vi_index) +{ + return (efx_mcdi_unlink_piobuf(enp, vi_index)); +} + +static __checkReturn int +hunt_get_datapath_caps( + __in efx_nic_t *enp) +{ + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + efx_dword_t datapath_capabilities; + int rc; + + if ((rc = efx_mcdi_get_capabilities(enp, &datapath_capabilities)) != 0) + goto fail1; + + /* + * Huntington RXDP firmware inserts a 0 or 14 byte prefix. + * We only support the 14 byte prefix here. + */ + if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities, + GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14) != 1) { + rc = ENOTSUP; + goto fail2; + } + encp->enc_rx_prefix_size = 14; + + /* Check if the firmware supports TSO */ + if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities, + GET_CAPABILITIES_OUT_TX_TSO) == 1) + encp->enc_fw_assisted_tso_enabled = B_TRUE; + else + encp->enc_fw_assisted_tso_enabled = B_FALSE; + + /* Check if the firmware has vadapter/vport/vswitch support */ + if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities, + GET_CAPABILITIES_OUT_EVB) == 1) + encp->enc_datapath_cap_evb = B_TRUE; + else + encp->enc_datapath_cap_evb = B_FALSE; + + /* Check if the firmware supports VLAN insertion */ + if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities, + GET_CAPABILITIES_OUT_TX_VLAN_INSERTION) == 1) + encp->enc_hw_tx_insert_vlan_enabled = B_TRUE; + else + encp->enc_hw_tx_insert_vlan_enabled = B_FALSE; + + /* Check if the firmware supports RX event batching */ + if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities, + GET_CAPABILITIES_OUT_RX_BATCHING) == 1) { + encp->enc_rx_batching_enabled = B_TRUE; + encp->enc_rx_batch_max = 16; + } else { + encp->enc_rx_batching_enabled = B_FALSE; + } + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +/* + * The external port mapping is a one-based numbering of the external + * connectors on the board. It does not distinguish off-board separated + * outputs such as multi-headed cables. + * The number of ports that map to each external port connector + * on the board is determined by the chip family and the port modes to + * which the NIC can be configured. The mapping table lists modes with + * port numbering requirements in increasing order. + */ +static struct { + efx_family_t family; + uint32_t modes_mask; + uint32_t stride; +} __hunt_external_port_mappings[] = { + /* Supported modes requiring 1 output per port */ + { + EFX_FAMILY_HUNTINGTON, + (1 << TLV_PORT_MODE_10G) | + (1 << TLV_PORT_MODE_40G) | + (1 << TLV_PORT_MODE_10G_10G) | + (1 << TLV_PORT_MODE_40G_40G), + 1 + }, + /* Supported modes requiring 2 outputs per port */ + { + EFX_FAMILY_HUNTINGTON, + (1 << TLV_PORT_MODE_10G_10G_10G_10G) | + (1 << TLV_PORT_MODE_40G_10G_10G) | + (1 << TLV_PORT_MODE_10G_10G_40G), + 2 + } +}; + +static __checkReturn int +hunt_external_port_mapping( + __in efx_nic_t *enp, + __in uint32_t port, + __out uint8_t *external_portp) +{ + int rc; + int i; + uint32_t port_modes; + uint32_t matches; + uint32_t stride = 1; /* default 1-1 mapping */ + + if ((rc = efx_mcdi_get_port_modes(enp, &port_modes)) != 0) { + /* No port mode information available - use default mapping */ + goto out; + } + + /* + * Infer the internal port -> external port mapping from + * the possible port modes for this NIC. + */ + for (i = 0; i < EFX_ARRAY_SIZE(__hunt_external_port_mappings); ++i) { + if (__hunt_external_port_mappings[i].family != + enp->en_family) + continue; + matches = (__hunt_external_port_mappings[i].modes_mask & + port_modes); + if (matches != 0) { + stride = __hunt_external_port_mappings[i].stride; + port_modes &= ~matches; + } + } + + if (port_modes != 0) { + /* Some advertised modes are not supported */ + rc = ENOTSUP; + goto fail1; + } + +out: + /* + * Scale as required by last matched mode and then convert to + * one-based numbering + */ + *external_portp = (uint8_t)(port / stride) + 1; + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static __checkReturn int +hunt_board_cfg( + __in efx_nic_t *enp) +{ + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + uint8_t mac_addr[6]; + uint32_t board_type = 0; + hunt_link_state_t hls; + efx_port_t *epp = &(enp->en_port); + uint32_t port; + uint32_t pf; + uint32_t vf; + uint32_t mask; + uint32_t flags; + uint32_t sysclk; + uint32_t base, nvec; + int rc; + + if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0) + goto fail1; + + /* + * NOTE: The MCDI protocol numbers ports from zero. + * The common code MCDI interface numbers ports from one. + */ + emip->emi_port = port + 1; + + if ((rc = hunt_external_port_mapping(enp, port, + &encp->enc_external_port)) != 0) + goto fail2; + + /* + * Get PCIe function number from firmware (used for + * per-function privilege and dynamic config info). + * - PCIe PF: pf = PF number, vf = 0xffff. + * - PCIe VF: pf = parent PF, vf = VF number. + */ + if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0) + goto fail3; + + encp->enc_pf = pf; + encp->enc_vf = vf; + + /* MAC address for this function */ + if (EFX_PCI_FUNCTION_IS_PF(encp)) { + rc = efx_mcdi_get_mac_address_pf(enp, mac_addr); + } else { + rc = efx_mcdi_get_mac_address_vf(enp, mac_addr); + } + if ((rc == 0) && (mac_addr[0] & 0x02)) { + /* + * If the static config does not include a global MAC address + * pool then the board may return a locally administered MAC + * address (this should only happen on incorrectly programmed + * boards). + */ + rc = EINVAL; + } + if (rc != 0) + goto fail4; + + EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr); + + /* Board configuration */ + rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL); + if (rc != 0) { + /* Unprivileged functions may not be able to read board cfg */ + if (rc == EACCES) + board_type = 0; + else + goto fail5; + } + + encp->enc_board_type = board_type; + encp->enc_clk_mult = 1; /* not used for Huntington */ + + /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ + if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) + goto fail6; + + /* Obtain the default PHY advertised capabilities */ + if ((rc = hunt_phy_get_link(enp, &hls)) != 0) + goto fail7; + epp->ep_default_adv_cap_mask = hls.hls_adv_cap_mask; + epp->ep_adv_cap_mask = hls.hls_adv_cap_mask; + + /* + * Enable firmware workarounds for hardware errata. + * Expected responses are: + * - 0 (zero): + * Success: workaround enabled or disabled as requested. + * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP): + * Firmware does not support the MC_CMD_WORKAROUND request. + * (assume that the workaround is not supported). + * - MC_CMD_ERR_ENOENT (reported as ENOENT): + * Firmware does not support the requested workaround. + * - MC_CMD_ERR_EPERM (reported as EACCES): + * Unprivileged function cannot enable/disable workarounds. + * + * See efx_mcdi_request_errcode() for MCDI error translations. + */ + + /* + * If the bug35388 workaround is enabled, then use an indirect access + * method to avoid unsafe EVQ writes. + */ + rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE, + NULL); + if ((rc == 0) || (rc == EACCES)) + encp->enc_bug35388_workaround = B_TRUE; + else if ((rc == ENOTSUP) || (rc == ENOENT)) + encp->enc_bug35388_workaround = B_FALSE; + else + goto fail8; + + /* + * If the bug41750 workaround is enabled, then do not test interrupts, + * as the test will fail (seen with Greenport controllers). + */ + rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE, + NULL); + if (rc == 0) { + encp->enc_bug41750_workaround = B_TRUE; + } else if (rc == EACCES) { + /* Assume a controller with 40G ports needs the workaround. */ + if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX) + encp->enc_bug41750_workaround = B_TRUE; + else + encp->enc_bug41750_workaround = B_FALSE; + } else if ((rc == ENOTSUP) || (rc == ENOENT)) { + encp->enc_bug41750_workaround = B_FALSE; + } else { + goto fail9; + } + if (EFX_PCI_FUNCTION_IS_VF(encp)) { + /* Interrupt testing does not work for VFs. See bug50084. */ + encp->enc_bug41750_workaround = B_TRUE; + } + + /* + * If the bug26807 workaround is enabled, then firmware has enabled + * support for chained multicast filters. Firmware will reset (FLR) + * functions which have filters in the hardware filter table when the + * workaround is enabled/disabled. + * + * We must recheck if the workaround is enabled after inserting the + * first hardware filter, in case it has been changed since this check. + */ + rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807, + B_TRUE, &flags); + if (rc == 0) { + encp->enc_bug26807_workaround = B_TRUE; + if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) { + /* + * Other functions had installed filters before the + * workaround was enabled, and they have been reset + * by firmware. + */ + EFSYS_PROBE(bug26807_workaround_flr_done); + /* FIXME: bump MC warm boot count ? */ + } + } else if (rc == EACCES) { + /* + * Unprivileged functions cannot enable the workaround in older + * firmware. + */ + encp->enc_bug26807_workaround = B_FALSE; + } else if ((rc == ENOTSUP) || (rc == ENOENT)) { + encp->enc_bug26807_workaround = B_FALSE; + } else { + goto fail10; + } + + /* Get sysclk frequency (in MHz). */ + if ((rc = efx_mcdi_get_clock(enp, &sysclk)) != 0) + goto fail11; + + /* + * The timer quantum is 1536 sysclk cycles, documented for the + * EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units. + */ + encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */ + if (encp->enc_bug35388_workaround) { + encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << + ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000; + } else { + encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << + FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000; + } + + /* Check capabilities of running datapath firmware */ + if ((rc = hunt_get_datapath_caps(enp)) != 0) + goto fail12; + + /* Alignment for receive packet DMA buffers */ + encp->enc_rx_buf_align_start = 1; + encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */ + + /* Alignment for WPTR updates */ + encp->enc_rx_push_align = HUNTINGTON_RX_WPTR_ALIGN; + + /* + * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use + * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available + * resources (allocated to this PCIe function), which is zero until + * after we have allocated VIs. + */ + encp->enc_evq_limit = 1024; + encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET; + encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET; + + encp->enc_buftbl_limit = 0xFFFFFFFF; + + encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS; + encp->enc_piobuf_size = HUNT_PIOBUF_SIZE; + + /* + * Get the current privilege mask. Note that this may be modified + * dynamically, so this value is informational only. DO NOT use + * the privilege mask to check for sufficient privileges, as that + * can result in time-of-check/time-of-use bugs. + */ + if ((rc = efx_mcdi_privilege_mask(enp, pf, vf, &mask)) != 0) + goto fail13; + + encp->enc_privilege_mask = mask; + + /* Get interrupt vector limits */ + if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) { + if (EFX_PCI_FUNCTION_IS_PF(encp)) + goto fail14; + + /* Ignore error (cannot query vector limits from a VF). */ + base = 0; + nvec = 1024; + } + encp->enc_intr_vec_base = base; + encp->enc_intr_limit = nvec; + + /* + * Maximum number of bytes into the frame the TCP header can start for + * firmware assisted TSO to work. + */ + encp->enc_tx_tso_tcp_header_offset_limit = 208; + + return (0); + +fail14: + EFSYS_PROBE(fail14); +fail13: + EFSYS_PROBE(fail13); +fail12: + EFSYS_PROBE(fail12); +fail11: + EFSYS_PROBE(fail11); +fail10: + EFSYS_PROBE(fail10); +fail9: + EFSYS_PROBE(fail9); +fail8: + EFSYS_PROBE(fail8); +fail7: + EFSYS_PROBE(fail7); +fail6: + EFSYS_PROBE(fail6); +fail5: + EFSYS_PROBE(fail5); +fail4: + EFSYS_PROBE(fail4); +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + + __checkReturn int +hunt_nic_probe( + __in efx_nic_t *enp) +{ + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + efx_drv_cfg_t *edcp = &(enp->en_drv_cfg); + int rc; + + EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON); + + /* Read and clear any assertion state */ + if ((rc = efx_mcdi_read_assertion(enp)) != 0) + goto fail1; + + /* Exit the assertion handler */ + if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0) + if (rc != EACCES) + goto fail2; + + if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0) + goto fail3; + + if ((rc = hunt_board_cfg(enp)) != 0) + if (rc != EACCES) + goto fail4; + + /* + * Set default driver config limits (based on board config). + * + * FIXME: For now allocate a fixed number of VIs which is likely to be + * sufficient and small enough to allow multiple functions on the same + * port. + */ + edcp->edc_min_vi_count = edcp->edc_max_vi_count = + MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit)); + + /* The client driver must configure and enable PIO buffer support */ + edcp->edc_max_piobuf_count = 0; + edcp->edc_pio_alloc_size = 0; + +#if EFSYS_OPT_MAC_STATS + /* Wipe the MAC statistics */ + if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0) + goto fail5; +#endif + +#if EFSYS_OPT_LOOPBACK + if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0) + goto fail6; +#endif + +#if EFSYS_OPT_MON_STATS + if ((rc = mcdi_mon_cfg_build(enp)) != 0) { + /* Unprivileged functions do not have access to sensors */ + if (rc != EACCES) + goto fail7; + } +#endif + + encp->enc_features = enp->en_features; + + return (0); + +#if EFSYS_OPT_MON_STATS +fail7: + EFSYS_PROBE(fail7); +#endif +#if EFSYS_OPT_LOOPBACK +fail6: + EFSYS_PROBE(fail6); +#endif +#if EFSYS_OPT_MAC_STATS +fail5: + EFSYS_PROBE(fail5); +#endif +fail4: + EFSYS_PROBE(fail4); +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_nic_set_drv_limits( + __inout efx_nic_t *enp, + __in efx_drv_limits_t *edlp) +{ + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + efx_drv_cfg_t *edcp = &(enp->en_drv_cfg); + uint32_t min_evq_count, max_evq_count; + uint32_t min_rxq_count, max_rxq_count; + uint32_t min_txq_count, max_txq_count; + int rc; + + if (edlp == NULL) { + rc = EINVAL; + goto fail1; + } + + /* Get minimum required and maximum usable VI limits */ + min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit); + min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit); + min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit); + + edcp->edc_min_vi_count = + MAX(min_evq_count, MAX(min_rxq_count, min_txq_count)); + + max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit); + max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit); + max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit); + + edcp->edc_max_vi_count = + MAX(max_evq_count, MAX(max_rxq_count, max_txq_count)); + + /* + * Check limits for sub-allocated piobuf blocks. + * PIO is optional, so don't fail if the limits are incorrect. + */ + if ((encp->enc_piobuf_size == 0) || + (encp->enc_piobuf_limit == 0) || + (edlp->edl_min_pio_alloc_size == 0) || + (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) { + /* Disable PIO */ + edcp->edc_max_piobuf_count = 0; + edcp->edc_pio_alloc_size = 0; + } else { + uint32_t blk_size, blk_count, blks_per_piobuf; + + blk_size = + MAX(edlp->edl_min_pio_alloc_size, HUNT_MIN_PIO_ALLOC_SIZE); + + blks_per_piobuf = encp->enc_piobuf_size / blk_size; + EFSYS_ASSERT3U(blks_per_piobuf, <=, 32); + + blk_count = (encp->enc_piobuf_limit * blks_per_piobuf); + + /* A zero max pio alloc count means unlimited */ + if ((edlp->edl_max_pio_alloc_count > 0) && + (edlp->edl_max_pio_alloc_count < blk_count)) { + blk_count = edlp->edl_max_pio_alloc_count; + } + + edcp->edc_pio_alloc_size = blk_size; + edcp->edc_max_piobuf_count = + (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + + __checkReturn int +hunt_nic_reset( + __in efx_nic_t *enp) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_ENTITY_RESET_IN_LEN, + MC_CMD_ENTITY_RESET_OUT_LEN)]; + int rc; + + /* hunt_nic_reset() is called to recover from BADASSERT failures. */ + if ((rc = efx_mcdi_read_assertion(enp)) != 0) + goto fail1; + if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0) + goto fail2; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_ENTITY_RESET; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN; + + MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG, + ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail3; + } + + /* Clear RX/TX DMA queue errors */ + enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR); + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_nic_init( + __in efx_nic_t *enp) +{ + efx_drv_cfg_t *edcp = &(enp->en_drv_cfg); + uint32_t min_vi_count, max_vi_count; + uint32_t vi_count, vi_base; + uint32_t i; + int rc; + + EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON); + + /* Enable reporting of some events (e.g. link change) */ + if ((rc = efx_mcdi_log_ctrl(enp)) != 0) + goto fail1; + + /* Allocate (optional) on-chip PIO buffers */ + hunt_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count); + + /* + * For best performance, PIO writes should use a write-combined + * (WC) memory mapping. Using a separate WC mapping for the PIO + * aperture of each VI would be a burden to drivers (and not + * possible if the host page size is >4Kbyte). + * + * To avoid this we use a single uncached (UC) mapping for VI + * register access, and a single WC mapping for extra VIs used + * for PIO writes. + * + * Each piobuf must be linked to a VI in the WC mapping, and to + * each VI that is using a sub-allocated block from the piobuf. + */ + min_vi_count = edcp->edc_min_vi_count; + max_vi_count = edcp->edc_max_vi_count + enp->en_u.hunt.enu_piobuf_count; + + /* Ensure that the previously attached driver's VIs are freed */ + if ((rc = efx_mcdi_free_vis(enp)) != 0) + goto fail2; + + /* + * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this + * fails then retrying the request for fewer VI resources may succeed. + */ + vi_count = 0; + if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count, + &vi_base, &vi_count)) != 0) + goto fail3; + + EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count); + + if (vi_count < min_vi_count) { + rc = ENOMEM; + goto fail4; + } + + enp->en_u.hunt.enu_vi_base = vi_base; + enp->en_u.hunt.enu_vi_count = vi_count; + + if (vi_count < min_vi_count + enp->en_u.hunt.enu_piobuf_count) { + /* Not enough extra VIs to map piobufs */ + hunt_nic_free_piobufs(enp); + } + + enp->en_u.hunt.enu_pio_write_vi_base = + vi_count - enp->en_u.hunt.enu_piobuf_count; + + /* Save UC memory mapping details */ + enp->en_u.hunt.enu_uc_mem_map_offset = 0; + if (enp->en_u.hunt.enu_piobuf_count > 0) { + enp->en_u.hunt.enu_uc_mem_map_size = + (ER_DZ_TX_PIOBUF_STEP * + enp->en_u.hunt.enu_pio_write_vi_base); + } else { + enp->en_u.hunt.enu_uc_mem_map_size = + (ER_DZ_TX_PIOBUF_STEP * + enp->en_u.hunt.enu_vi_count); + } + + /* Save WC memory mapping details */ + enp->en_u.hunt.enu_wc_mem_map_offset = + enp->en_u.hunt.enu_uc_mem_map_offset + + enp->en_u.hunt.enu_uc_mem_map_size; + + enp->en_u.hunt.enu_wc_mem_map_size = + (ER_DZ_TX_PIOBUF_STEP * + enp->en_u.hunt.enu_piobuf_count); + + /* Link piobufs to extra VIs in WC mapping */ + if (enp->en_u.hunt.enu_piobuf_count > 0) { + for (i = 0; i < enp->en_u.hunt.enu_piobuf_count; i++) { + rc = efx_mcdi_link_piobuf(enp, + enp->en_u.hunt.enu_pio_write_vi_base + i, + enp->en_u.hunt.enu_piobuf_handle[i]); + if (rc != 0) + break; + } + } + + /* Allocate a vAdapter attached to our upstream vPort/pPort */ + if ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) + goto fail5; + + enp->en_vport_id = EVB_PORT_ID_ASSIGNED; + + return (0); + +fail5: + EFSYS_PROBE(fail5); +fail4: + EFSYS_PROBE(fail4); +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); + + hunt_nic_free_piobufs(enp); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_nic_get_vi_pool( + __in efx_nic_t *enp, + __out uint32_t *vi_countp) +{ + EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON); + + /* + * Report VIs that the client driver can use. + * Do not include VIs used for PIO buffer writes. + */ + *vi_countp = enp->en_u.hunt.enu_pio_write_vi_base; + + return (0); +} + + __checkReturn int +hunt_nic_get_bar_region( + __in efx_nic_t *enp, + __in efx_nic_region_t region, + __out uint32_t *offsetp, + __out size_t *sizep) +{ + int rc; + + EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON); + + /* + * TODO: Specify host memory mapping alignment and granularity + * in efx_drv_limits_t so that they can be taken into account + * when allocating extra VIs for PIO writes. + */ + switch (region) { + case EFX_REGION_VI: + /* UC mapped memory BAR region for VI registers */ + *offsetp = enp->en_u.hunt.enu_uc_mem_map_offset; + *sizep = enp->en_u.hunt.enu_uc_mem_map_size; + break; + + case EFX_REGION_PIO_WRITE_VI: + /* WC mapped memory BAR region for piobuf writes */ + *offsetp = enp->en_u.hunt.enu_wc_mem_map_offset; + *sizep = enp->en_u.hunt.enu_wc_mem_map_size; + break; + + default: + rc = EINVAL; + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + void +hunt_nic_fini( + __in efx_nic_t *enp) +{ + (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id); + enp->en_vport_id = 0; + + /* FIXME: do we need to unlink piobufs ? */ + hunt_nic_free_piobufs(enp); + + (void) efx_mcdi_free_vis(enp); + enp->en_u.hunt.enu_vi_count = 0; +} + + void +hunt_nic_unprobe( + __in efx_nic_t *enp) +{ +#if EFSYS_OPT_MON_STATS + mcdi_mon_cfg_free(enp); +#endif /* EFSYS_OPT_MON_STATS */ + (void) efx_mcdi_drv_attach(enp, B_FALSE); +} + +#if EFSYS_OPT_DIAG + + __checkReturn int +hunt_nic_register_test( + __in efx_nic_t *enp) +{ + int rc; + + /* FIXME */ + _NOTE(ARGUNUSED(enp)) + if (B_FALSE) { + rc = ENOTSUP; + goto fail1; + } + /* FIXME */ + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +#endif /* EFSYS_OPT_DIAG */ + + + +#endif /* EFSYS_OPT_HUNTINGTON */ Property changes on: head/sys/dev/sfxge/common/hunt_nic.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/hunt_nvram.c =================================================================== --- head/sys/dev/sfxge/common/hunt_nvram.c (nonexistent) +++ head/sys/dev/sfxge/common/hunt_nvram.c (revision 283514) @@ -0,0 +1,1538 @@ +/*- + * Copyright (c) 2012-2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "efsys.h" +#include "efx.h" +#include "efx_types.h" +#include "efx_regs.h" +#include "efx_impl.h" + +#if EFSYS_OPT_HUNTINGTON + +#if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM + +#include "ef10_tlv_layout.h" + +/* Cursor for TLV partition format */ +typedef struct tlv_cursor_s { + uint32_t *block; /* Base of data block */ + uint32_t *current; /* Cursor position */ + uint32_t *end; /* End tag position */ + uint32_t *limit; /* Last dword of data block */ +} tlv_cursor_t; + +static __checkReturn int +tlv_validate_state( + __in tlv_cursor_t *cursor); + + +/* + * Operations on TLV formatted partition data. + */ +static uint32_t +tlv_tag( + __in tlv_cursor_t *cursor) +{ + uint32_t dword, tag; + + dword = cursor->current[0]; + tag = __LE_TO_CPU_32(dword); + + return (tag); +} + +static size_t +tlv_length( + __in tlv_cursor_t *cursor) +{ + uint32_t dword, length; + + if (tlv_tag(cursor) == TLV_TAG_END) + return (0); + + dword = cursor->current[1]; + length = __LE_TO_CPU_32(dword); + + return ((size_t)length); +} + +static uint8_t * +tlv_value( + __in tlv_cursor_t *cursor) +{ + if (tlv_tag(cursor) == TLV_TAG_END) + return (NULL); + + return ((uint8_t *)(&cursor->current[2])); +} + +static uint8_t * +tlv_item( + __in tlv_cursor_t *cursor) +{ + if (tlv_tag(cursor) == TLV_TAG_END) + return (NULL); + + return ((uint8_t *)cursor->current); +} + +/* + * TLV item DWORD length is tag + length + value (rounded up to DWORD) + * equivalent to tlv_n_words_for_len in mc-comms tlv.c + */ +#define TLV_DWORD_COUNT(length) \ + (1 + 1 + (((length) + sizeof (uint32_t) - 1) / sizeof (uint32_t))) + + +static uint32_t * +tlv_next_item_ptr( + __in tlv_cursor_t *cursor) +{ + uint32_t length; + + length = tlv_length(cursor); + + return (cursor->current + TLV_DWORD_COUNT(length)); +} + +static int +tlv_advance( + __in tlv_cursor_t *cursor) +{ + int rc; + + if ((rc = tlv_validate_state(cursor)) != 0) + goto fail1; + + if (cursor->current == cursor->end) { + /* No more tags after END tag */ + cursor->current = NULL; + rc = ENOENT; + goto fail2; + } + + /* Advance to next item and validate */ + cursor->current = tlv_next_item_ptr(cursor); + + if ((rc = tlv_validate_state(cursor)) != 0) + goto fail3; + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static int +tlv_rewind( + __in tlv_cursor_t *cursor) +{ + int rc; + + cursor->current = cursor->block; + + if ((rc = tlv_validate_state(cursor)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static int +tlv_find( + __in tlv_cursor_t *cursor, + __in uint32_t tag) +{ + int rc; + + rc = tlv_rewind(cursor); + while (rc == 0) { + if (tlv_tag(cursor) == tag) + break; + + rc = tlv_advance(cursor); + } + return (rc); +} + +static __checkReturn int +tlv_validate_state( + __in tlv_cursor_t *cursor) +{ + int rc; + + /* Check cursor position */ + if (cursor->current < cursor->block) { + rc = EINVAL; + goto fail1; + } + if (cursor->current > cursor->limit) { + rc = EINVAL; + goto fail2; + } + + if (tlv_tag(cursor) != TLV_TAG_END) { + /* Check current item has space for tag and length */ + if (cursor->current > (cursor->limit - 2)) { + cursor->current = NULL; + rc = EFAULT; + goto fail3; + } + + /* Check we have value data for current item and another tag */ + if (tlv_next_item_ptr(cursor) > (cursor->limit - 1)) { + cursor->current = NULL; + rc = EFAULT; + goto fail4; + } + } + + return (0); + +fail4: + EFSYS_PROBE(fail4); +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static int +tlv_init_cursor( + __in tlv_cursor_t *cursor, + __in uint32_t *block, + __in uint32_t *limit) +{ + cursor->block = block; + cursor->limit = limit; + + cursor->current = cursor->block; + cursor->end = NULL; + + return (tlv_validate_state(cursor)); +} + +static int +tlv_init_cursor_from_size( + __in tlv_cursor_t *cursor, + __in uint8_t *block, + __in size_t size) +{ + uint32_t *limit; + limit = (uint32_t *)(block + size - sizeof (uint32_t)); + return (tlv_init_cursor(cursor, (uint32_t *)block, limit)); +} + +static int +tlv_require_end( + __in tlv_cursor_t *cursor) +{ + uint32_t *pos; + int rc; + + if (cursor->end == NULL) { + pos = cursor->current; + if ((rc = tlv_find(cursor, TLV_TAG_END)) != 0) + goto fail1; + + cursor->end = cursor->current; + cursor->current = pos; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static size_t +tlv_block_length_used( + __in tlv_cursor_t *cursor) +{ + int rc; + + if ((rc = tlv_validate_state(cursor)) != 0) + goto fail1; + + if ((rc = tlv_require_end(cursor)) != 0) + goto fail2; + + /* Return space used (including the END tag) */ + return (cursor->end + 1 - cursor->block) * sizeof (uint32_t); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (0); +} + + +static __checkReturn uint32_t * +tlv_write( + __in tlv_cursor_t *cursor, + __in uint32_t tag, + __in_bcount(size) uint8_t *data, + __in size_t size) +{ + uint32_t len = size; + uint32_t *ptr; + + ptr = cursor->current; + + *ptr++ = __CPU_TO_LE_32(tag); + *ptr++ = __CPU_TO_LE_32(len); + + if (len > 0) { + ptr[(len - 1) / sizeof (uint32_t)] = 0; + memcpy(ptr, data, len); + ptr += P2ROUNDUP(len, sizeof (uint32_t)) / sizeof (*ptr); + } + + return (ptr); +} + +static __checkReturn int +tlv_insert( + __in tlv_cursor_t *cursor, + __in uint32_t tag, + __in uint8_t *data, + __in size_t size) +{ + unsigned int delta; + int rc; + + if ((rc = tlv_validate_state(cursor)) != 0) + goto fail1; + + if ((rc = tlv_require_end(cursor)) != 0) + goto fail2; + + if (tag == TLV_TAG_END) { + rc = EINVAL; + goto fail3; + } + + delta = TLV_DWORD_COUNT(size); + if (cursor->end + 1 + delta > cursor->limit) { + rc = ENOSPC; + goto fail4; + } + + /* Move data up: new space at cursor->current */ + memmove(cursor->current + delta, cursor->current, + (cursor->end + 1 - cursor->current) * sizeof (uint32_t)); + + /* Adjust the end pointer */ + cursor->end += delta; + + /* Write new TLV item */ + tlv_write(cursor, tag, data, size); + + return (0); + +fail4: + EFSYS_PROBE(fail4); +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static __checkReturn int +tlv_modify( + __in tlv_cursor_t *cursor, + __in uint32_t tag, + __in uint8_t *data, + __in size_t size) +{ + uint32_t *pos; + unsigned int old_ndwords; + unsigned int new_ndwords; + unsigned int delta; + int rc; + + if ((rc = tlv_validate_state(cursor)) != 0) + goto fail1; + + if (tlv_tag(cursor) == TLV_TAG_END) { + rc = EINVAL; + goto fail2; + } + if (tlv_tag(cursor) != tag) { + rc = EINVAL; + goto fail3; + } + + old_ndwords = TLV_DWORD_COUNT(tlv_length(cursor)); + new_ndwords = TLV_DWORD_COUNT(size); + + if ((rc = tlv_require_end(cursor)) != 0) + goto fail4; + + if (new_ndwords > old_ndwords) { + /* Expand space used for TLV item */ + delta = new_ndwords - old_ndwords; + pos = cursor->current + old_ndwords; + + if (cursor->end + 1 + delta > cursor->limit) { + rc = ENOSPC; + goto fail5; + } + + /* Move up: new space at (cursor->current + old_ndwords) */ + memmove(pos + delta, pos, + (cursor->end + 1 - pos) * sizeof (uint32_t)); + + /* Adjust the end pointer */ + cursor->end += delta; + + } else if (new_ndwords < old_ndwords) { + /* Shrink space used for TLV item */ + delta = old_ndwords - new_ndwords; + pos = cursor->current + new_ndwords; + + /* Move down: remove words at (cursor->current + new_ndwords) */ + memmove(pos, pos + delta, + (cursor->end + 1 - pos) * sizeof (uint32_t)); + + /* Zero the new space at the end of the TLV chain */ + memset(cursor->end + 1 - delta, 0, delta * sizeof (uint32_t)); + + /* Adjust the end pointer */ + cursor->end -= delta; + } + + /* Write new data */ + tlv_write(cursor, tag, data, size); + + return (0); + +fail5: + EFSYS_PROBE(fail5); +fail4: + EFSYS_PROBE(fail4); +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +/* Validate TLV formatted partition contents (before writing to flash) */ + __checkReturn int +efx_nvram_tlv_validate( + __in efx_nic_t *enp, + __in uint32_t partn, + __in_bcount(partn_size) caddr_t partn_data, + __in size_t partn_size) +{ + tlv_cursor_t cursor; + struct tlv_partition_header *header; + struct tlv_partition_trailer *trailer; + size_t total_length; + uint32_t cksum; + int pos; + int rc; + + EFX_STATIC_ASSERT(sizeof (*header) <= HUNTINGTON_NVRAM_CHUNK); + + if ((partn_data == NULL) || (partn_size == 0)) { + rc = EINVAL; + goto fail1; + } + + /* The partition header must be the first item (at offset zero) */ + if ((rc = tlv_init_cursor_from_size(&cursor, partn_data, + partn_size)) != 0) { + rc = EFAULT; + goto fail2; + } + if (tlv_tag(&cursor) != TLV_TAG_PARTITION_HEADER) { + rc = EINVAL; + goto fail3; + } + header = (struct tlv_partition_header *)tlv_item(&cursor); + + /* Check TLV partition length (includes the END tag) */ + total_length = __LE_TO_CPU_32(header->total_length); + if (total_length > partn_size) { + rc = EFBIG; + goto fail4; + } + + /* Check partition ends with PARTITION_TRAILER and END tags */ + if ((rc = tlv_find(&cursor, TLV_TAG_PARTITION_TRAILER)) != 0) { + rc = EINVAL; + goto fail5; + } + trailer = (struct tlv_partition_trailer *)tlv_item(&cursor); + + if ((rc = tlv_advance(&cursor)) != 0) { + rc = EINVAL; + goto fail6; + } + if (tlv_tag(&cursor) != TLV_TAG_END) { + rc = EINVAL; + goto fail7; + } + + /* Check generation counts are consistent */ + if (trailer->generation != header->generation) { + rc = EINVAL; + goto fail8; + } + + /* Verify partition checksum */ + cksum = 0; + for (pos = 0; (size_t)pos < total_length; pos += sizeof (uint32_t)) { + cksum += *((uint32_t *)(partn_data + pos)); + } + if (cksum != 0) { + rc = EINVAL; + goto fail9; + } + + return (0); + +fail9: + EFSYS_PROBE(fail9); +fail8: + EFSYS_PROBE(fail8); +fail7: + EFSYS_PROBE(fail7); +fail6: + EFSYS_PROBE(fail6); +fail5: + EFSYS_PROBE(fail5); +fail4: + EFSYS_PROBE(fail4); +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +/* Read and validate an entire TLV formatted partition */ +static __checkReturn int +hunt_nvram_read_tlv_partition( + __in efx_nic_t *enp, + __in uint32_t partn, + __in_bcount(partn_size) caddr_t partn_data, + __in size_t partn_size) +{ + tlv_cursor_t cursor; + struct tlv_partition_header *header; + struct tlv_partition_trailer *trailer; + size_t total_length; + uint32_t cksum; + int pos; + int rc; + + EFX_STATIC_ASSERT(sizeof (*header) <= HUNTINGTON_NVRAM_CHUNK); + + if ((partn_data == NULL) || (partn_size == 0)) { + rc = EINVAL; + goto fail1; + } + + /* Read initial chunk of partition */ + if ((rc = hunt_nvram_partn_read(enp, partn, 0, partn_data, + HUNTINGTON_NVRAM_CHUNK)) != 0) { + goto fail2; + } + + /* The partition header must be the first item (at offset zero) */ + if ((rc = tlv_init_cursor_from_size(&cursor, partn_data, + partn_size)) != 0) { + rc = EFAULT; + goto fail3; + } + if (tlv_tag(&cursor) != TLV_TAG_PARTITION_HEADER) { + rc = EINVAL; + goto fail4; + } + header = (struct tlv_partition_header *)tlv_item(&cursor); + + /* Check TLV partition length (includes the END tag) */ + total_length = __LE_TO_CPU_32(header->total_length); + if (total_length > partn_size) { + rc = EFBIG; + goto fail5; + } + + /* Read the remaining partition content */ + if (total_length > HUNTINGTON_NVRAM_CHUNK) { + if ((rc = hunt_nvram_partn_read(enp, partn, + HUNTINGTON_NVRAM_CHUNK, + partn_data + HUNTINGTON_NVRAM_CHUNK, + total_length - HUNTINGTON_NVRAM_CHUNK)) != 0) + goto fail6; + } + + /* Check partition ends with PARTITION_TRAILER and END tags */ + if ((rc = tlv_find(&cursor, TLV_TAG_PARTITION_TRAILER)) != 0) { + rc = EINVAL; + goto fail7; + } + trailer = (struct tlv_partition_trailer *)tlv_item(&cursor); + + if ((rc = tlv_advance(&cursor)) != 0) { + rc = EINVAL; + goto fail8; + } + if (tlv_tag(&cursor) != TLV_TAG_END) { + rc = EINVAL; + goto fail9; + } + + /* Check data read from partition is consistent */ + if (trailer->generation != header->generation) { + /* + * The partition data may have been modified between successive + * MCDI NVRAM_READ requests by the MC or another PCI function. + * + * The caller must retry to obtain consistent partition data. + */ + rc = EAGAIN; + goto fail10; + } + + /* Verify partition checksum */ + cksum = 0; + for (pos = 0; (size_t)pos < total_length; pos += sizeof (uint32_t)) { + cksum += *((uint32_t *)(partn_data + pos)); + } + if (cksum != 0) { + rc = EINVAL; + goto fail11; + } + + return (0); + +fail11: + EFSYS_PROBE(fail11); +fail10: + EFSYS_PROBE(fail10); +fail9: + EFSYS_PROBE(fail9); +fail8: + EFSYS_PROBE(fail8); +fail7: + EFSYS_PROBE(fail7); +fail6: + EFSYS_PROBE(fail6); +fail5: + EFSYS_PROBE(fail5); +fail4: + EFSYS_PROBE(fail4); +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +/* + * Read a single TLV item from a host memory + * buffer containing a TLV formatted partition. + */ + __checkReturn int +hunt_nvram_buf_read_tlv( + __in efx_nic_t *enp, + __in_bcount(partn_size) caddr_t partn_data, + __in size_t partn_size, + __in uint32_t tag, + __deref_out_bcount_opt(*sizep) caddr_t *datap, + __out size_t *sizep) +{ + tlv_cursor_t cursor; + caddr_t data; + size_t length; + caddr_t value; + int rc; + + if ((partn_data == NULL) || (partn_size == 0)) { + rc = EINVAL; + goto fail1; + } + + /* Find requested TLV tag in partition data */ + if ((rc = tlv_init_cursor_from_size(&cursor, partn_data, + partn_size)) != 0) { + rc = EFAULT; + goto fail2; + } + if ((rc = tlv_find(&cursor, tag)) != 0) { + rc = ENOENT; + goto fail3; + } + value = tlv_value(&cursor); + length = tlv_length(&cursor); + + if (length == 0) + data = NULL; + else { + /* Copy out data from TLV item */ + EFSYS_KMEM_ALLOC(enp->en_esip, length, data); + if (data == NULL) { + rc = ENOMEM; + goto fail4; + } + memcpy(data, value, length); + } + + *datap = data; + *sizep = length; + + return (0); + +fail4: + EFSYS_PROBE(fail4); +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + + +/* Read a single TLV item from a TLV formatted partition */ + __checkReturn int +hunt_nvram_partn_read_tlv( + __in efx_nic_t *enp, + __in uint32_t partn, + __in uint32_t tag, + __deref_out_bcount_opt(*sizep) caddr_t *datap, + __out size_t *sizep) +{ + caddr_t partn_data = NULL; + size_t partn_size = 0; + size_t length; + caddr_t data; + int retry; + int rc; + + /* Allocate sufficient memory for the entire partition */ + if ((rc = hunt_nvram_partn_size(enp, partn, &partn_size)) != 0) + goto fail1; + + if (partn_size == 0) { + rc = ENOENT; + goto fail2; + } + + EFSYS_KMEM_ALLOC(enp->en_esip, partn_size, partn_data); + if (partn_data == NULL) { + rc = ENOMEM; + goto fail3; + } + + /* + * Read the entire TLV partition. Retry until consistent partition + * contents are returned. Inconsistent data may be read if: + * a) the partition contents are invalid + * b) the MC has rebooted while we were reading the partition + * c) the partition has been modified while we were reading it + * Limit retry attempts to ensure forward progress. + */ + retry = 10; + do { + rc = hunt_nvram_read_tlv_partition(enp, partn, + partn_data, partn_size); + } while ((rc == EAGAIN) && (--retry > 0)); + + if (rc != 0) { + /* Failed to obtain consistent partition data */ + goto fail4; + } + + if ((rc = hunt_nvram_buf_read_tlv(enp, partn_data, partn_size, + tag, &data, &length)) != 0) + goto fail5; + + EFSYS_KMEM_FREE(enp->en_esip, partn_size, partn_data); + + *datap = data; + *sizep = length; + + return (0); + +fail5: + EFSYS_PROBE(fail5); +fail4: + EFSYS_PROBE(fail4); + + EFSYS_KMEM_FREE(enp->en_esip, partn_size, partn_data); +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +/* + * Add or update a single TLV item in a host memory buffer containing a TLV + * formatted partition. + */ + __checkReturn int +hunt_nvram_buf_write_tlv( + __inout_bcount(partn_size) caddr_t partn_data, + __in size_t partn_size, + __in uint32_t tag, + __in_bcount(tag_size) caddr_t tag_data, + __in size_t tag_size, + __out size_t *total_lengthp) +{ + tlv_cursor_t cursor; + struct tlv_partition_header *header; + struct tlv_partition_trailer *trailer; + uint32_t generation; + uint32_t cksum; + int pos; + int rc; + + /* The partition header must be the first item (at offset zero) */ + if ((rc = tlv_init_cursor_from_size(&cursor, partn_data, + partn_size)) != 0) { + rc = EFAULT; + goto fail1; + } + if (tlv_tag(&cursor) != TLV_TAG_PARTITION_HEADER) { + rc = EINVAL; + goto fail2; + } + header = (struct tlv_partition_header *)tlv_item(&cursor); + + /* Update the TLV chain to contain the new data */ + if ((rc = tlv_find(&cursor, tag)) == 0) { + /* Modify existing TLV item */ + if ((rc = tlv_modify(&cursor, tag, + tag_data, tag_size)) != 0) + goto fail3; + } else { + /* Insert a new TLV item before the PARTITION_TRAILER */ + rc = tlv_find(&cursor, TLV_TAG_PARTITION_TRAILER); + if (rc != 0) { + rc = EINVAL; + goto fail4; + } + if ((rc = tlv_insert(&cursor, tag, + tag_data, tag_size)) != 0) { + rc = EINVAL; + goto fail5; + } + } + + /* Find the trailer tag */ + if ((rc = tlv_find(&cursor, TLV_TAG_PARTITION_TRAILER)) != 0) { + rc = EINVAL; + goto fail6; + } + trailer = (struct tlv_partition_trailer *)tlv_item(&cursor); + + /* Update PARTITION_HEADER and PARTITION_TRAILER fields */ + *total_lengthp = tlv_block_length_used(&cursor); + EFSYS_ASSERT3U(*total_lengthp, <=, partn_size); + generation = __LE_TO_CPU_32(header->generation) + 1; + + header->total_length = __CPU_TO_LE_32(*total_lengthp); + header->generation = __CPU_TO_LE_32(generation); + trailer->generation = __CPU_TO_LE_32(generation); + + /* Recompute PARTITION_TRAILER checksum */ + trailer->checksum = 0; + cksum = 0; + for (pos = 0; (size_t)pos < *total_lengthp; pos += sizeof (uint32_t)) { + cksum += *((uint32_t *)(partn_data + pos)); + } + trailer->checksum = ~cksum + 1; + + return (0); + +fail6: + EFSYS_PROBE(fail6); +fail5: + EFSYS_PROBE(fail5); +fail4: + EFSYS_PROBE(fail4); +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +/* Add or update a single TLV item in a TLV formatted partition */ + __checkReturn int +hunt_nvram_partn_write_tlv( + __in efx_nic_t *enp, + __in uint32_t partn, + __in uint32_t tag, + __in_bcount(size) caddr_t data, + __in size_t size) +{ + size_t partn_size; + caddr_t partn_data; + size_t total_length; + int rc; + + EFSYS_ASSERT3U(partn, ==, NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG); + + /* Allocate sufficient memory for the entire partition */ + if ((rc = hunt_nvram_partn_size(enp, partn, &partn_size)) != 0) + goto fail1; + + EFSYS_KMEM_ALLOC(enp->en_esip, partn_size, partn_data); + if (partn_data == NULL) { + rc = ENOMEM; + goto fail2; + } + + /* Lock the partition */ + if ((rc = hunt_nvram_partn_lock(enp, partn)) != 0) + goto fail3; + + /* Read the partition contents (no need to retry when locked). */ + if ((rc = hunt_nvram_read_tlv_partition(enp, partn, + partn_data, partn_size)) != 0) { + /* Failed to obtain consistent partition data */ + goto fail4; + } + + /* Update the contents in memory */ + if ((rc = hunt_nvram_buf_write_tlv(partn_data, partn_size, + tag, data, size, &total_length)) != 0) + goto fail5; + + /* Erase the whole partition */ + if ((rc = hunt_nvram_partn_erase(enp, partn, 0, partn_size)) != 0) + goto fail6; + + /* Write new partition contents to NVRAM */ + if ((rc = hunt_nvram_partn_write(enp, partn, 0, partn_data, + total_length)) != 0) + goto fail7; + + /* Unlock the partition */ + hunt_nvram_partn_unlock(enp, partn); + + EFSYS_KMEM_FREE(enp->en_esip, partn_size, partn_data); + + return (0); + +fail7: + EFSYS_PROBE(fail7); +fail6: + EFSYS_PROBE(fail6); +fail5: + EFSYS_PROBE(fail5); +fail4: + EFSYS_PROBE(fail4); + + hunt_nvram_partn_unlock(enp, partn); +fail3: + EFSYS_PROBE(fail3); + + EFSYS_KMEM_FREE(enp->en_esip, partn_size, partn_data); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_nvram_partn_size( + __in efx_nic_t *enp, + __in unsigned int partn, + __out size_t *sizep) +{ + int rc; + + if ((rc = efx_mcdi_nvram_info(enp, partn, sizep, NULL, NULL)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_nvram_partn_lock( + __in efx_nic_t *enp, + __in unsigned int partn) +{ + int rc; + + if ((rc = efx_mcdi_nvram_update_start(enp, partn)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_nvram_partn_read( + __in efx_nic_t *enp, + __in unsigned int partn, + __in unsigned int offset, + __out_bcount(size) caddr_t data, + __in size_t size) +{ + size_t chunk; + int rc; + + while (size > 0) { + chunk = MIN(size, HUNTINGTON_NVRAM_CHUNK); + + if ((rc = efx_mcdi_nvram_read(enp, partn, offset, + data, chunk)) != 0) { + goto fail1; + } + + size -= chunk; + data += chunk; + offset += chunk; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_nvram_partn_erase( + __in efx_nic_t *enp, + __in unsigned int partn, + __in unsigned int offset, + __in size_t size) +{ + int rc; + + if ((rc = efx_mcdi_nvram_erase(enp, partn, offset, size)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_nvram_partn_write( + __in efx_nic_t *enp, + __in unsigned int partn, + __in unsigned int offset, + __out_bcount(size) caddr_t data, + __in size_t size) +{ + size_t chunk; + int rc; + + while (size > 0) { + chunk = MIN(size, HUNTINGTON_NVRAM_CHUNK); + + if ((rc = efx_mcdi_nvram_write(enp, partn, offset, + data, chunk)) != 0) { + goto fail1; + } + + size -= chunk; + data += chunk; + offset += chunk; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + void +hunt_nvram_partn_unlock( + __in efx_nic_t *enp, + __in unsigned int partn) +{ + boolean_t reboot; + int rc; + + reboot = B_FALSE; + if ((rc = efx_mcdi_nvram_update_finish(enp, partn, reboot)) != 0) + goto fail1; + + return; + +fail1: + EFSYS_PROBE1(fail1, int, rc); +} + + __checkReturn int +hunt_nvram_partn_set_version( + __in efx_nic_t *enp, + __in unsigned int partn, + __in_ecount(4) uint16_t version[4]) +{ + struct tlv_partition_version partn_version; + size_t size; + int rc; + + /* Add or modify partition version TLV item */ + partn_version.version_w = __CPU_TO_LE_16(version[0]); + partn_version.version_x = __CPU_TO_LE_16(version[1]); + partn_version.version_y = __CPU_TO_LE_16(version[2]); + partn_version.version_z = __CPU_TO_LE_16(version[3]); + + size = sizeof (partn_version) - (2 * sizeof (uint32_t)); + + if ((rc = hunt_nvram_partn_write_tlv(enp, + NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, + TLV_TAG_PARTITION_VERSION(partn), + (caddr_t)&partn_version.version_w, size)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +#endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ + +#if EFSYS_OPT_NVRAM + +typedef struct hunt_parttbl_entry_s { + unsigned int partn; + unsigned int port; + efx_nvram_type_t nvtype; +} hunt_parttbl_entry_t; + +/* Translate EFX NVRAM types to firmware partition types */ +static hunt_parttbl_entry_t hunt_parttbl[] = { + {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 1, EFX_NVRAM_MC_FIRMWARE}, + {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 2, EFX_NVRAM_MC_FIRMWARE}, + {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 3, EFX_NVRAM_MC_FIRMWARE}, + {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 4, EFX_NVRAM_MC_FIRMWARE}, + {NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 1, EFX_NVRAM_MC_GOLDEN}, + {NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 2, EFX_NVRAM_MC_GOLDEN}, + {NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 3, EFX_NVRAM_MC_GOLDEN}, + {NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 4, EFX_NVRAM_MC_GOLDEN}, + {NVRAM_PARTITION_TYPE_EXPANSION_ROM, 1, EFX_NVRAM_BOOTROM}, + {NVRAM_PARTITION_TYPE_EXPANSION_ROM, 2, EFX_NVRAM_BOOTROM}, + {NVRAM_PARTITION_TYPE_EXPANSION_ROM, 3, EFX_NVRAM_BOOTROM}, + {NVRAM_PARTITION_TYPE_EXPANSION_ROM, 4, EFX_NVRAM_BOOTROM}, + {NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 1, EFX_NVRAM_BOOTROM_CFG}, + {NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 2, EFX_NVRAM_BOOTROM_CFG}, + {NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 3, EFX_NVRAM_BOOTROM_CFG}, + {NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 4, EFX_NVRAM_BOOTROM_CFG}, + {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 1, EFX_NVRAM_DYNAMIC_CFG}, + {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 2, EFX_NVRAM_DYNAMIC_CFG}, + {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 3, EFX_NVRAM_DYNAMIC_CFG}, + {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 4, EFX_NVRAM_DYNAMIC_CFG} +}; + +static __checkReturn hunt_parttbl_entry_t * +hunt_parttbl_entry( + __in efx_nic_t *enp, + __in efx_nvram_type_t type) +{ + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + hunt_parttbl_entry_t *entry; + int i; + + EFSYS_ASSERT3U(type, <, EFX_NVRAM_NTYPES); + + for (i = 0; i < EFX_ARRAY_SIZE(hunt_parttbl); i++) { + entry = &hunt_parttbl[i]; + + if (entry->port == emip->emi_port && entry->nvtype == type) + return (entry); + } + + return (NULL); +} + + +#if EFSYS_OPT_DIAG + + __checkReturn int +hunt_nvram_test( + __in efx_nic_t *enp) +{ + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + hunt_parttbl_entry_t *entry; + unsigned int npartns = 0; + uint32_t *partns = NULL; + size_t size; + int i; + unsigned int j; + int rc; + + /* Find supported partitions */ + size = MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM * sizeof (uint32_t); + EFSYS_KMEM_ALLOC(enp->en_esip, size, partns); + if (partns == NULL) { + rc = ENOMEM; + goto fail1; + } + + if ((rc = efx_mcdi_nvram_partitions(enp, (caddr_t)partns, size, + &npartns)) != 0) { + goto fail2; + } + + /* + * Iterate over the list of supported partition types + * applicable to *this* port + */ + for (i = 0; i < EFX_ARRAY_SIZE(hunt_parttbl); i++) { + entry = &hunt_parttbl[i]; + + if (entry->port != emip->emi_port) + continue; + + for (j = 0; j < npartns; j++) { + if (entry->partn == partns[j]) { + rc = efx_mcdi_nvram_test(enp, entry->partn); + if (rc != 0) + goto fail3; + } + } + } + + EFSYS_KMEM_FREE(enp->en_esip, size, partns); + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); + EFSYS_KMEM_FREE(enp->en_esip, size, partns); +fail1: + EFSYS_PROBE1(fail1, int, rc); + return (rc); +} + +#endif /* EFSYS_OPT_DIAG */ + + __checkReturn int +hunt_nvram_size( + __in efx_nic_t *enp, + __in efx_nvram_type_t type, + __out size_t *sizep) +{ + hunt_parttbl_entry_t *entry; + uint32_t partn; + int rc; + + if ((entry = hunt_parttbl_entry(enp, type)) == NULL) { + rc = ENOTSUP; + goto fail1; + } + partn = entry->partn; + + if ((rc = hunt_nvram_partn_size(enp, partn, sizep)) != 0) + goto fail2; + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + *sizep = 0; + + return (rc); +} + + __checkReturn int +hunt_nvram_get_version( + __in efx_nic_t *enp, + __in efx_nvram_type_t type, + __out uint32_t *subtypep, + __out_ecount(4) uint16_t version[4]) +{ + hunt_parttbl_entry_t *entry; + uint32_t partn; + int rc; + + if ((entry = hunt_parttbl_entry(enp, type)) == NULL) { + rc = ENOTSUP; + goto fail1; + } + partn = entry->partn; + + /* FIXME: get highest partn version from all ports */ + /* FIXME: return partn description if available */ + + if ((rc = efx_mcdi_nvram_metadata(enp, partn, subtypep, + version, NULL, 0)) != 0) + goto fail2; + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_nvram_rw_start( + __in efx_nic_t *enp, + __in efx_nvram_type_t type, + __out size_t *chunk_sizep) +{ + hunt_parttbl_entry_t *entry; + uint32_t partn; + int rc; + + if ((entry = hunt_parttbl_entry(enp, type)) == NULL) { + rc = ENOTSUP; + goto fail1; + } + partn = entry->partn; + + if ((rc = hunt_nvram_partn_lock(enp, partn)) != 0) + goto fail2; + + if (chunk_sizep != NULL) + *chunk_sizep = HUNTINGTON_NVRAM_CHUNK; + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_nvram_read_chunk( + __in efx_nic_t *enp, + __in efx_nvram_type_t type, + __in unsigned int offset, + __out_bcount(size) caddr_t data, + __in size_t size) +{ + hunt_parttbl_entry_t *entry; + int rc; + + if ((entry = hunt_parttbl_entry(enp, type)) == NULL) { + rc = ENOTSUP; + goto fail1; + } + + if ((rc = hunt_nvram_partn_read(enp, entry->partn, + offset, data, size)) != 0) + goto fail2; + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_nvram_erase( + __in efx_nic_t *enp, + __in efx_nvram_type_t type) +{ + hunt_parttbl_entry_t *entry; + size_t size; + int rc; + + if ((entry = hunt_parttbl_entry(enp, type)) == NULL) { + rc = ENOTSUP; + goto fail1; + } + + if ((rc = hunt_nvram_partn_size(enp, entry->partn, &size)) != 0) + goto fail2; + + if ((rc = hunt_nvram_partn_erase(enp, entry->partn, 0, size)) != 0) + goto fail3; + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_nvram_write_chunk( + __in efx_nic_t *enp, + __in efx_nvram_type_t type, + __in unsigned int offset, + __in_bcount(size) caddr_t data, + __in size_t size) +{ + hunt_parttbl_entry_t *entry; + int rc; + + if ((entry = hunt_parttbl_entry(enp, type)) == NULL) { + rc = ENOTSUP; + goto fail1; + } + + if ((rc = hunt_nvram_partn_write(enp, entry->partn, + offset, data, size)) != 0) + goto fail2; + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + void +hunt_nvram_rw_finish( + __in efx_nic_t *enp, + __in efx_nvram_type_t type) +{ + hunt_parttbl_entry_t *entry; + + if ((entry = hunt_parttbl_entry(enp, type)) != NULL) + hunt_nvram_partn_unlock(enp, entry->partn); +} + + __checkReturn int +hunt_nvram_set_version( + __in efx_nic_t *enp, + __in efx_nvram_type_t type, + __in_ecount(4) uint16_t version[4]) +{ + hunt_parttbl_entry_t *entry; + unsigned int partn; + int rc; + + if ((entry = hunt_parttbl_entry(enp, type)) == NULL) { + rc = ENOTSUP; + goto fail1; + } + partn = entry->partn; + + if ((rc = hunt_nvram_partn_set_version(enp, partn, version)) != 0) + goto fail2; + + return (0); + +fail2: + EFSYS_PROBE(fail2); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +#endif /* EFSYS_OPT_NVRAM */ + +#endif /* EFSYS_OPT_HUNTINGTON */ Property changes on: head/sys/dev/sfxge/common/hunt_nvram.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/hunt_phy.c =================================================================== --- head/sys/dev/sfxge/common/hunt_phy.c (nonexistent) +++ head/sys/dev/sfxge/common/hunt_phy.c (revision 283514) @@ -0,0 +1,701 @@ +/*- + * Copyright (c) 2012-2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "efsys.h" +#include "efx.h" +#include "efx_impl.h" + +#if EFSYS_OPT_HUNTINGTON + +static void +hunt_phy_decode_cap( + __in uint32_t mcdi_cap, + __out uint32_t *maskp) +{ + /* + * TBD: consider common Siena/Hunt function: Hunt is a superset of + * Siena here (adds 40G) + */ + + uint32_t mask; + + mask = 0; + if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10HDX_LBN)) + mask |= (1 << EFX_PHY_CAP_10HDX); + if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10FDX_LBN)) + mask |= (1 << EFX_PHY_CAP_10FDX); + if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100HDX_LBN)) + mask |= (1 << EFX_PHY_CAP_100HDX); + if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100FDX_LBN)) + mask |= (1 << EFX_PHY_CAP_100FDX); + if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000HDX_LBN)) + mask |= (1 << EFX_PHY_CAP_1000HDX); + if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000FDX_LBN)) + mask |= (1 << EFX_PHY_CAP_1000FDX); + if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10000FDX_LBN)) + mask |= (1 << EFX_PHY_CAP_10000FDX); + if (mcdi_cap & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) + mask |= (1 << EFX_PHY_CAP_40000FDX); + if (mcdi_cap & (1 << MC_CMD_PHY_CAP_PAUSE_LBN)) + mask |= (1 << EFX_PHY_CAP_PAUSE); + if (mcdi_cap & (1 << MC_CMD_PHY_CAP_ASYM_LBN)) + mask |= (1 << EFX_PHY_CAP_ASYM); + if (mcdi_cap & (1 << MC_CMD_PHY_CAP_AN_LBN)) + mask |= (1 << EFX_PHY_CAP_AN); + + *maskp = mask; +} + +static void +hunt_phy_decode_link_mode( + __in efx_nic_t *enp, + __in uint32_t link_flags, + __in unsigned int speed, + __in unsigned int fcntl, + __out efx_link_mode_t *link_modep, + __out unsigned int *fcntlp) +{ + /* + * TBD: consider common Siena/Hunt function: Hunt is a superset of + * Siena here (adds 40G and generate-only flow control) + */ + + boolean_t fd = !!(link_flags & + (1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN)); + boolean_t up = !!(link_flags & + (1 << MC_CMD_GET_LINK_OUT_LINK_UP_LBN)); + + _NOTE(ARGUNUSED(enp)) + + if (!up) + *link_modep = EFX_LINK_DOWN; + else if (speed == 40000 && fd) + *link_modep = EFX_LINK_40000FDX; + else if (speed == 10000 && fd) + *link_modep = EFX_LINK_10000FDX; + else if (speed == 1000) + *link_modep = fd ? EFX_LINK_1000FDX : EFX_LINK_1000HDX; + else if (speed == 100) + *link_modep = fd ? EFX_LINK_100FDX : EFX_LINK_100HDX; + else if (speed == 10) + *link_modep = fd ? EFX_LINK_10FDX : EFX_LINK_10HDX; + else + *link_modep = EFX_LINK_UNKNOWN; + + if (fcntl == MC_CMD_FCNTL_OFF) + *fcntlp = 0; + else if (fcntl == MC_CMD_FCNTL_RESPOND) + *fcntlp = EFX_FCNTL_RESPOND; + else if (fcntl == MC_CMD_FCNTL_GENERATE) + *fcntlp = EFX_FCNTL_GENERATE; + else if (fcntl == MC_CMD_FCNTL_BIDIR) + *fcntlp = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE; + else { + EFSYS_PROBE1(mc_pcol_error, int, fcntl); + *fcntlp = 0; + } +} + + + void +hunt_phy_link_ev( + __in efx_nic_t *enp, + __in efx_qword_t *eqp, + __out efx_link_mode_t *link_modep) +{ + /* + * TBD: consider common Siena/Hunt function: Hunt is a superset of + * Siena here (adds 40G) + */ + + efx_port_t *epp = &(enp->en_port); + unsigned int link_flags; + unsigned int speed; + unsigned int fcntl; + efx_link_mode_t link_mode; + uint32_t lp_cap_mask; + + /* + * Convert the LINKCHANGE speed enumeration into mbit/s, in the + * same way as GET_LINK encodes the speed + */ + switch (MCDI_EV_FIELD(eqp, LINKCHANGE_SPEED)) { + case MCDI_EVENT_LINKCHANGE_SPEED_100M: + speed = 100; + break; + case MCDI_EVENT_LINKCHANGE_SPEED_1G: + speed = 1000; + break; + case MCDI_EVENT_LINKCHANGE_SPEED_10G: + speed = 10000; + break; + case MCDI_EVENT_LINKCHANGE_SPEED_40G: + speed = 40000; + break; + default: + speed = 0; + break; + } + + link_flags = MCDI_EV_FIELD(eqp, LINKCHANGE_LINK_FLAGS); + hunt_phy_decode_link_mode(enp, link_flags, speed, + MCDI_EV_FIELD(eqp, LINKCHANGE_FCNTL), + &link_mode, &fcntl); + hunt_phy_decode_cap(MCDI_EV_FIELD(eqp, LINKCHANGE_LP_CAP), + &lp_cap_mask); + + /* + * It's safe to update ep_lp_cap_mask without the driver's port lock + * because presumably any concurrently running efx_port_poll() is + * only going to arrive at the same value. + * + * ep_fcntl has two meanings. It's either the link common fcntl + * (if the PHY supports AN), or it's the forced link state. If + * the former, it's safe to update the value for the same reason as + * for ep_lp_cap_mask. If the latter, then just ignore the value, + * because we can race with efx_mac_fcntl_set(). + */ + epp->ep_lp_cap_mask = lp_cap_mask; + epp->ep_fcntl = fcntl; + + *link_modep = link_mode; +} + + __checkReturn int +hunt_phy_power( + __in efx_nic_t *enp, + __in boolean_t power) +{ + /* TBD: consider common Siena/Hunt function: essentially identical */ + + int rc; + + if (!power) + return (0); + + /* Check if the PHY is a zombie */ + if ((rc = hunt_phy_verify(enp)) != 0) + goto fail1; + + enp->en_reset_flags |= EFX_RESET_PHY; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_phy_get_link( + __in efx_nic_t *enp, + __out hunt_link_state_t *hlsp) +{ + /* + * TBD: consider common Siena/Hunt function: Hunt is very similar + * (at least for now; not clear that the loopbacks should necessarily + * be quite the same...) + */ + + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_GET_LINK_IN_LEN, + MC_CMD_GET_LINK_OUT_LEN)]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_GET_LINK; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_GET_LINK_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_GET_LINK_OUT_LEN; + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_LEN) { + rc = EMSGSIZE; + goto fail2; + } + + hunt_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_CAP), + &hlsp->hls_adv_cap_mask); + hunt_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_LP_CAP), + &hlsp->hls_lp_cap_mask); + + hunt_phy_decode_link_mode(enp, MCDI_OUT_DWORD(req, GET_LINK_OUT_FLAGS), + MCDI_OUT_DWORD(req, GET_LINK_OUT_LINK_SPEED), + MCDI_OUT_DWORD(req, GET_LINK_OUT_FCNTL), + &hlsp->hls_link_mode, &hlsp->hls_fcntl); + +#if EFSYS_OPT_LOOPBACK + /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespace agree */ + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_NONE == EFX_LOOPBACK_OFF); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_DATA == EFX_LOOPBACK_DATA); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMAC == EFX_LOOPBACK_GMAC); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII == EFX_LOOPBACK_XGMII); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGXS == EFX_LOOPBACK_XGXS); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI == EFX_LOOPBACK_XAUI); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII == EFX_LOOPBACK_GMII); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII == EFX_LOOPBACK_SGMII); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGBR == EFX_LOOPBACK_XGBR); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI == EFX_LOOPBACK_XFI); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_FAR == EFX_LOOPBACK_XAUI_FAR); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_FAR == EFX_LOOPBACK_GMII_FAR); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII_FAR == EFX_LOOPBACK_SGMII_FAR); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_FAR == EFX_LOOPBACK_XFI_FAR); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GPHY == EFX_LOOPBACK_GPHY); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS == EFX_LOOPBACK_PHY_XS); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PCS == EFX_LOOPBACK_PCS); + EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMAPMD == EFX_LOOPBACK_PMA_PMD); + + hlsp->hls_loopback = MCDI_OUT_DWORD(req, GET_LINK_OUT_LOOPBACK_MODE); +#endif /* EFSYS_OPT_LOOPBACK */ + + hlsp->hls_mac_up = MCDI_OUT_DWORD(req, GET_LINK_OUT_MAC_FAULT) == 0; + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_phy_reconfigure( + __in efx_nic_t *enp) +{ + /* + * TBD: this is a little different for now (no LED support for Hunt + * yet), but ultimately should consider common Siena/Hunt function: + * Hunt should be a superset of Siena here (adds 40G) + */ + + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + efx_port_t *epp = &(enp->en_port); + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_SET_LINK_IN_LEN, + MC_CMD_SET_LINK_OUT_LEN)]; + uint32_t cap_mask; + unsigned int led_mode; + unsigned int speed; + int rc; + + if (~encp->enc_func_flags & EFX_NIC_FUNC_LINKCTRL) + goto out; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_SET_LINK; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_SET_LINK_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_SET_LINK_OUT_LEN; + + cap_mask = epp->ep_adv_cap_mask; + MCDI_IN_POPULATE_DWORD_10(req, SET_LINK_IN_CAP, + PHY_CAP_10HDX, (cap_mask >> EFX_PHY_CAP_10HDX) & 0x1, + PHY_CAP_10FDX, (cap_mask >> EFX_PHY_CAP_10FDX) & 0x1, + PHY_CAP_100HDX, (cap_mask >> EFX_PHY_CAP_100HDX) & 0x1, + PHY_CAP_100FDX, (cap_mask >> EFX_PHY_CAP_100FDX) & 0x1, + PHY_CAP_1000HDX, (cap_mask >> EFX_PHY_CAP_1000HDX) & 0x1, + PHY_CAP_1000FDX, (cap_mask >> EFX_PHY_CAP_1000FDX) & 0x1, + PHY_CAP_10000FDX, (cap_mask >> EFX_PHY_CAP_10000FDX) & 0x1, + PHY_CAP_PAUSE, (cap_mask >> EFX_PHY_CAP_PAUSE) & 0x1, + PHY_CAP_ASYM, (cap_mask >> EFX_PHY_CAP_ASYM) & 0x1, + PHY_CAP_AN, (cap_mask >> EFX_PHY_CAP_AN) & 0x1); + /* Too many fields for for POPULATE macros, so insert this afterwards */ + MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP, + PHY_CAP_40000FDX, (cap_mask >> EFX_PHY_CAP_40000FDX) & 0x1); + +#if EFSYS_OPT_LOOPBACK + MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, + epp->ep_loopback_type); + switch (epp->ep_loopback_link_mode) { + case EFX_LINK_100FDX: + speed = 100; + break; + case EFX_LINK_1000FDX: + speed = 1000; + break; + case EFX_LINK_10000FDX: + speed = 10000; + break; + case EFX_LINK_40000FDX: + speed = 40000; + break; + default: + speed = 0; + } +#else + MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, MC_CMD_LOOPBACK_NONE); + speed = 0; +#endif /* EFSYS_OPT_LOOPBACK */ + MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_SPEED, speed); + +#if EFSYS_OPT_PHY_FLAGS + MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, epp->ep_phy_flags); +#else + MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, 0); +#endif /* EFSYS_OPT_PHY_FLAGS */ + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + /* And set the blink mode */ + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_SET_ID_LED; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_SET_ID_LED_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_SET_ID_LED_OUT_LEN; + +#if EFSYS_OPT_PHY_LED_CONTROL + switch (epp->ep_phy_led_mode) { + case EFX_PHY_LED_DEFAULT: + led_mode = MC_CMD_LED_DEFAULT; + break; + case EFX_PHY_LED_OFF: + led_mode = MC_CMD_LED_OFF; + break; + case EFX_PHY_LED_ON: + led_mode = MC_CMD_LED_ON; + break; + default: + EFSYS_ASSERT(0); + led_mode = MC_CMD_LED_DEFAULT; + } + + MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, led_mode); +#else + MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, MC_CMD_LED_DEFAULT); +#endif /* EFSYS_OPT_PHY_LED_CONTROL */ + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail2; + } +out: + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_phy_verify( + __in efx_nic_t *enp) +{ + /* TBD: consider common Siena/Hunt function: essentially identical */ + + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_GET_PHY_STATE_IN_LEN, + MC_CMD_GET_PHY_STATE_OUT_LEN)]; + uint32_t state; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_GET_PHY_STATE; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_GET_PHY_STATE_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_GET_PHY_STATE_OUT_LEN; + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < MC_CMD_GET_PHY_STATE_OUT_LEN) { + rc = EMSGSIZE; + goto fail2; + } + + state = MCDI_OUT_DWORD(req, GET_PHY_STATE_OUT_STATE); + if (state != MC_CMD_PHY_STATE_OK) { + if (state != MC_CMD_PHY_STATE_ZOMBIE) + EFSYS_PROBE1(mc_pcol_error, int, state); + rc = ENOTACTIVE; + goto fail3; + } + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_phy_oui_get( + __in efx_nic_t *enp, + __out uint32_t *ouip) +{ + _NOTE(ARGUNUSED(enp, ouip)) + + return (ENOTSUP); +} + +#if EFSYS_OPT_PHY_STATS + + __checkReturn int +hunt_phy_stats_update( + __in efx_nic_t *enp, + __in efsys_mem_t *esmp, + __out_ecount(EFX_PHY_NSTATS) uint32_t *stat) +{ + /* TBD: no stats support in firmware yet */ + _NOTE(ARGUNUSED(enp, esmp)) + memset(stat, 0, EFX_PHY_NSTATS * sizeof (*stat)); + + return (0); +} + +#endif /* EFSYS_OPT_PHY_STATS */ + +#if EFSYS_OPT_PHY_PROPS + +#if EFSYS_OPT_NAMES + +extern const char * +hunt_phy_prop_name( + __in efx_nic_t *enp, + __in unsigned int id) +{ + _NOTE(ARGUNUSED(enp, id)) + + return (NULL); +} + +#endif /* EFSYS_OPT_NAMES */ + +extern __checkReturn int +hunt_phy_prop_get( + __in efx_nic_t *enp, + __in unsigned int id, + __in uint32_t flags, + __out uint32_t *valp) +{ + _NOTE(ARGUNUSED(enp, id, flags, valp)) + + return (ENOTSUP); +} + +extern __checkReturn int +hunt_phy_prop_set( + __in efx_nic_t *enp, + __in unsigned int id, + __in uint32_t val) +{ + _NOTE(ARGUNUSED(enp, id, val)) + + return (ENOTSUP); +} + +#endif /* EFSYS_OPT_PHY_PROPS */ + +#if EFSYS_OPT_BIST + + __checkReturn int +hunt_bist_enable_offline( + __in efx_nic_t *enp) +{ + int rc; + + if ((rc = efx_mcdi_bist_enable_offline(enp)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_bist_start( + __in efx_nic_t *enp, + __in efx_bist_type_t type) +{ + int rc; + + if ((rc = efx_mcdi_bist_start(enp, type)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_bist_poll( + __in efx_nic_t *enp, + __in efx_bist_type_t type, + __out efx_bist_result_t *resultp, + __out_opt __drv_when(count > 0, __notnull) + uint32_t *value_maskp, + __out_ecount_opt(count) __drv_when(count > 0, __notnull) + unsigned long *valuesp, + __in size_t count) +{ + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_POLL_BIST_IN_LEN, + MCDI_CTL_SDU_LEN_MAX)]; + uint32_t value_mask = 0; + uint32_t result; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_POLL_BIST; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_POLL_BIST_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MCDI_CTL_SDU_LEN_MAX; + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < MC_CMD_POLL_BIST_OUT_RESULT_OFST + 4) { + rc = EMSGSIZE; + goto fail2; + } + + if (count > 0) + (void) memset(valuesp, '\0', count * sizeof (unsigned long)); + + result = MCDI_OUT_DWORD(req, POLL_BIST_OUT_RESULT); + + if (result == MC_CMD_POLL_BIST_FAILED && + req.emr_out_length >= MC_CMD_POLL_BIST_OUT_MEM_LEN && + count > EFX_BIST_MEM_ECC_FATAL) { + if (valuesp != NULL) { + valuesp[EFX_BIST_MEM_TEST] = + MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_TEST); + valuesp[EFX_BIST_MEM_ADDR] = + MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_ADDR); + valuesp[EFX_BIST_MEM_BUS] = + MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_BUS); + valuesp[EFX_BIST_MEM_EXPECT] = + MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_EXPECT); + valuesp[EFX_BIST_MEM_ACTUAL] = + MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_ACTUAL); + valuesp[EFX_BIST_MEM_ECC] = + MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_ECC); + valuesp[EFX_BIST_MEM_ECC_PARITY] = + MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_ECC_PARITY); + valuesp[EFX_BIST_MEM_ECC_FATAL] = + MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_ECC_FATAL); + } + value_mask |= (1 << EFX_BIST_MEM_TEST) | + (1 << EFX_BIST_MEM_ADDR) | + (1 << EFX_BIST_MEM_BUS) | + (1 << EFX_BIST_MEM_EXPECT) | + (1 << EFX_BIST_MEM_ACTUAL) | + (1 << EFX_BIST_MEM_ECC) | + (1 << EFX_BIST_MEM_ECC_PARITY) | + (1 << EFX_BIST_MEM_ECC_FATAL); + } else if (result == MC_CMD_POLL_BIST_FAILED && + encp->enc_phy_type == EFX_PHY_XFI_FARMI && + req.emr_out_length >= MC_CMD_POLL_BIST_OUT_MRSFP_LEN && + count > EFX_BIST_FAULT_CODE) { + if (valuesp != NULL) + valuesp[EFX_BIST_FAULT_CODE] = + MCDI_OUT_DWORD(req, POLL_BIST_OUT_MRSFP_TEST); + value_mask |= 1 << EFX_BIST_FAULT_CODE; + } + + if (value_maskp != NULL) + *value_maskp = value_mask; + + EFSYS_ASSERT(resultp != NULL); + if (result == MC_CMD_POLL_BIST_RUNNING) + *resultp = EFX_BIST_RESULT_RUNNING; + else if (result == MC_CMD_POLL_BIST_PASSED) + *resultp = EFX_BIST_RESULT_PASSED; + else + *resultp = EFX_BIST_RESULT_FAILED; + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + void +hunt_bist_stop( + __in efx_nic_t *enp, + __in efx_bist_type_t type) +{ + /* There is no way to stop BIST on Huntinton. */ + _NOTE(ARGUNUSED(enp, type)) +} + +#endif /* EFSYS_OPT_BIST */ + +#endif /* EFSYS_OPT_HUNTINGTON */ Property changes on: head/sys/dev/sfxge/common/hunt_phy.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/hunt_rx.c =================================================================== --- head/sys/dev/sfxge/common/hunt_rx.c (nonexistent) +++ head/sys/dev/sfxge/common/hunt_rx.c (revision 283514) @@ -0,0 +1,765 @@ +/*- + * Copyright (c) 2012-2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "efsys.h" +#include "efx.h" +#include "efx_impl.h" + + +#if EFSYS_OPT_HUNTINGTON + + +static __checkReturn int +efx_mcdi_init_rxq( + __in efx_nic_t *enp, + __in uint32_t size, + __in uint32_t target_evq, + __in uint32_t label, + __in uint32_t instance, + __in efsys_mem_t *esmp) +{ + efx_mcdi_req_t req; + uint8_t payload[ + MAX(MC_CMD_INIT_RXQ_IN_LEN(EFX_RXQ_NBUFS(EFX_RXQ_MAXNDESCS)), + MC_CMD_INIT_RXQ_OUT_LEN)]; + int npages = EFX_RXQ_NBUFS(size); + int i; + efx_qword_t *dma_addr; + uint64_t addr; + int rc; + + EFSYS_ASSERT3U(size, <=, EFX_RXQ_MAXNDESCS); + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_INIT_RXQ; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_INIT_RXQ_IN_LEN(npages); + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_INIT_RXQ_OUT_LEN; + + MCDI_IN_SET_DWORD(req, INIT_RXQ_IN_SIZE, size); + MCDI_IN_SET_DWORD(req, INIT_RXQ_IN_TARGET_EVQ, target_evq); + MCDI_IN_SET_DWORD(req, INIT_RXQ_IN_LABEL, label); + MCDI_IN_SET_DWORD(req, INIT_RXQ_IN_INSTANCE, instance); + MCDI_IN_POPULATE_DWORD_5(req, INIT_RXQ_IN_FLAGS, + INIT_RXQ_IN_FLAG_BUFF_MODE, 0, + INIT_RXQ_IN_FLAG_HDR_SPLIT, 0, + INIT_RXQ_IN_FLAG_TIMESTAMP, 0, + INIT_RXQ_IN_CRC_MODE, 0, + INIT_RXQ_IN_FLAG_PREFIX, 1); + MCDI_IN_SET_DWORD(req, INIT_RXQ_IN_OWNER_ID, 0); + MCDI_IN_SET_DWORD(req, INIT_RXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); + + dma_addr = MCDI_IN2(req, efx_qword_t, INIT_RXQ_IN_DMA_ADDR); + addr = EFSYS_MEM_ADDR(esmp); + + for (i = 0; i < npages; i++) { + EFX_POPULATE_QWORD_2(*dma_addr, + EFX_DWORD_1, (uint32_t)(addr >> 32), + EFX_DWORD_0, (uint32_t)(addr & 0xffffffff)); + + dma_addr++; + addr += EFX_BUF_SIZE; + } + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static __checkReturn int +efx_mcdi_fini_rxq( + __in efx_nic_t *enp, + __in uint32_t instance) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_FINI_RXQ_IN_LEN, + MC_CMD_FINI_RXQ_OUT_LEN)]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_FINI_RXQ; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_FINI_RXQ_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_FINI_RXQ_OUT_LEN; + + MCDI_IN_SET_DWORD(req, FINI_RXQ_IN_INSTANCE, instance); + + efx_mcdi_execute(enp, &req); + + if ((req.emr_rc != 0) && (req.emr_rc != MC_CMD_ERR_EALREADY)) { + rc = req.emr_rc; + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +#if EFSYS_OPT_RX_SCALE +static __checkReturn int +efx_mcdi_rss_context_alloc( + __in efx_nic_t *enp, + __out uint32_t *rss_contextp) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN, + MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)]; + uint32_t rss_context; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_RSS_CONTEXT_ALLOC; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN; + + MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID, + EVB_PORT_ID_ASSIGNED); + MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_TYPE, + MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE); + /* NUM_QUEUES is only used to validate indirection table offsets */ + MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, 64); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + if (req.emr_out_length_used < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) { + rc = EMSGSIZE; + goto fail2; + } + + rss_context = MCDI_OUT_DWORD(req, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID); + if (rss_context == HUNTINGTON_RSS_CONTEXT_INVALID) { + rc = ENOENT; + goto fail3; + } + + *rss_contextp = rss_context; + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} +#endif /* EFSYS_OPT_RX_SCALE */ + +#if EFSYS_OPT_RX_SCALE +static int +efx_mcdi_rss_context_free( + __in efx_nic_t *enp, + __in uint32_t rss_context) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_RSS_CONTEXT_FREE_IN_LEN, + MC_CMD_RSS_CONTEXT_FREE_OUT_LEN)]; + int rc; + + if (rss_context == HUNTINGTON_RSS_CONTEXT_INVALID) { + rc = EINVAL; + goto fail1; + } + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_RSS_CONTEXT_FREE; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_RSS_CONTEXT_FREE_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_RSS_CONTEXT_FREE_OUT_LEN; + + MCDI_IN_SET_DWORD(req, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID, rss_context); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail2; + } + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} +#endif /* EFSYS_OPT_RX_SCALE */ + +#if EFSYS_OPT_RX_SCALE +static int +efx_mcdi_rss_context_set_flags( + __in efx_nic_t *enp, + __in uint32_t rss_context, + __in efx_rx_hash_type_t type) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN, + MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN)]; + int rc; + + if (rss_context == HUNTINGTON_RSS_CONTEXT_INVALID) { + rc = EINVAL; + goto fail1; + } + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_FLAGS; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN; + + MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID, + rss_context); + + MCDI_IN_POPULATE_DWORD_4(req, RSS_CONTEXT_SET_FLAGS_IN_FLAGS, + RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN, + (type & (1U << EFX_RX_HASH_IPV4)) ? 1 : 0, + RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN, + (type & (1U << EFX_RX_HASH_TCPIPV4)) ? 1 : 0, + RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN, + (type & (1U << EFX_RX_HASH_IPV6)) ? 1 : 0, + RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN, + (type & (1U << EFX_RX_HASH_TCPIPV6)) ? 1 : 0); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail2; + } + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} +#endif /* EFSYS_OPT_RX_SCALE */ + +#if EFSYS_OPT_RX_SCALE +static int +efx_mcdi_rss_context_set_key( + __in efx_nic_t *enp, + __in uint32_t rss_context, + __in_ecount(n) uint8_t *key, + __in size_t n) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN, + MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN)]; + int rc; + + if (rss_context == HUNTINGTON_RSS_CONTEXT_INVALID) { + rc = EINVAL; + goto fail1; + } + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_KEY; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN; + + MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID, + rss_context); + + EFSYS_ASSERT3U(n, ==, MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN); + if (n != MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN) { + rc = EINVAL; + goto fail2; + } + + memcpy(MCDI_IN2(req, uint8_t, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY), + key, n); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail3; + } + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} +#endif /* EFSYS_OPT_RX_SCALE */ + +#if EFSYS_OPT_RX_SCALE +static int +efx_mcdi_rss_context_set_table( + __in efx_nic_t *enp, + __in uint32_t rss_context, + __in_ecount(n) unsigned int *table, + __in size_t n) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN, + MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN)]; + uint8_t *req_table; + int i, rc; + + if (rss_context == HUNTINGTON_RSS_CONTEXT_INVALID) { + rc = EINVAL; + goto fail1; + } + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_TABLE; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN; + + MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID, + rss_context); + + req_table = + MCDI_IN2(req, uint8_t, RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE); + + for (i = 0; + i < MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN; + i++) { + req_table[i] = (n > 0) ? (uint8_t)table[i % n] : 0; + } + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail2; + } + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} +#endif /* EFSYS_OPT_RX_SCALE */ + + + __checkReturn int +hunt_rx_init( + __in efx_nic_t *enp) +{ +#if EFSYS_OPT_RX_SCALE + + if (efx_mcdi_rss_context_alloc(enp, &enp->en_rss_context) == 0) { + /* + * Allocated an exclusive RSS context, which allows both the + * indirection table and key to be modified. + */ + enp->en_rss_support = EFX_RX_SCALE_EXCLUSIVE; + enp->en_hash_support = EFX_RX_HASH_AVAILABLE; + } else { + /* + * Failed to allocate an exclusive RSS context. Continue + * operation without support for RSS. The pseudo-header in + * received packets will not contain a Toeplitz hash value. + */ + enp->en_rss_support = EFX_RX_SCALE_UNAVAILABLE; + enp->en_hash_support = EFX_RX_HASH_UNAVAILABLE; + } + +#endif /* EFSYS_OPT_RX_SCALE */ + + return (0); +} + +#if EFSYS_OPT_RX_HDR_SPLIT + __checkReturn int +hunt_rx_hdr_split_enable( + __in efx_nic_t *enp, + __in unsigned int hdr_buf_size, + __in unsigned int pld_buf_size) +{ + int rc; + + /* FIXME */ + _NOTE(ARGUNUSED(enp, hdr_buf_size, pld_buf_size)) + if (B_FALSE) { + rc = ENOTSUP; + goto fail1; + } + /* FIXME */ + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} +#endif /* EFSYS_OPT_RX_HDR_SPLIT */ + +#if EFSYS_OPT_RX_SCATTER + __checkReturn int +hunt_rx_scatter_enable( + __in efx_nic_t *enp, + __in unsigned int buf_size) +{ + _NOTE(ARGUNUSED(enp, buf_size)) + return (0); +} +#endif /* EFSYS_OPT_RX_SCATTER */ + +#if EFSYS_OPT_RX_SCALE + __checkReturn int +hunt_rx_scale_mode_set( + __in efx_nic_t *enp, + __in efx_rx_hash_alg_t alg, + __in efx_rx_hash_type_t type, + __in boolean_t insert) +{ + int rc; + + EFSYS_ASSERT3U(alg, ==, EFX_RX_HASHALG_TOEPLITZ); + EFSYS_ASSERT3U(insert, ==, B_TRUE); + + if ((alg != EFX_RX_HASHALG_TOEPLITZ) || (insert == B_FALSE)) { + rc = EINVAL; + goto fail1; + } + + if (enp->en_rss_support == EFX_RX_SCALE_UNAVAILABLE) { + rc = ENOTSUP; + goto fail2; + } + + if ((rc = efx_mcdi_rss_context_set_flags(enp, + enp->en_rss_context, type)) != 0) + goto fail3; + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} +#endif /* EFSYS_OPT_RX_SCALE */ + +#if EFSYS_OPT_RX_SCALE + __checkReturn int +hunt_rx_scale_key_set( + __in efx_nic_t *enp, + __in_ecount(n) uint8_t *key, + __in size_t n) +{ + int rc; + + if (enp->en_rss_support == EFX_RX_SCALE_UNAVAILABLE) { + rc = ENOTSUP; + goto fail1; + } + + if ((rc = efx_mcdi_rss_context_set_key(enp, + enp->en_rss_context, key, n)) != 0) + goto fail2; + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} +#endif /* EFSYS_OPT_RX_SCALE */ + +#if EFSYS_OPT_RX_SCALE + __checkReturn int +hunt_rx_scale_tbl_set( + __in efx_nic_t *enp, + __in_ecount(n) unsigned int *table, + __in size_t n) +{ + int rc; + + if (enp->en_rss_support == EFX_RX_SCALE_UNAVAILABLE) { + rc = ENOTSUP; + goto fail1; + } + + if ((rc = efx_mcdi_rss_context_set_table(enp, + enp->en_rss_context, table, n)) != 0) + goto fail2; + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} +#endif /* EFSYS_OPT_RX_SCALE */ + + void +hunt_rx_qpost( + __in efx_rxq_t *erp, + __in_ecount(n) efsys_dma_addr_t *addrp, + __in size_t size, + __in unsigned int n, + __in unsigned int completed, + __in unsigned int added) +{ + efx_qword_t qword; + unsigned int i; + unsigned int offset; + unsigned int id; + + /* The client driver must not overfill the queue */ + EFSYS_ASSERT3U(added - completed + n, <=, + EFX_RXQ_LIMIT(erp->er_mask + 1)); + + id = added & (erp->er_mask); + for (i = 0; i < n; i++) { + EFSYS_PROBE4(rx_post, unsigned int, erp->er_index, + unsigned int, id, efsys_dma_addr_t, addrp[i], + size_t, size); + + EFX_POPULATE_QWORD_3(qword, + ESF_DZ_RX_KER_BYTE_CNT, (uint32_t)(size), + ESF_DZ_RX_KER_BUF_ADDR_DW0, + (uint32_t)(addrp[i] & 0xffffffff), + ESF_DZ_RX_KER_BUF_ADDR_DW1, + (uint32_t)(addrp[i] >> 32)); + + offset = id * sizeof (efx_qword_t); + EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword); + + id = (id + 1) & (erp->er_mask); + } +} + + void +hunt_rx_qpush( + __in efx_rxq_t *erp, + __in unsigned int added, + __inout unsigned int *pushedp) +{ + efx_nic_t *enp = erp->er_enp; + unsigned int pushed = *pushedp; + uint32_t wptr; + efx_dword_t dword; + + /* Hardware has alignment restriction for WPTR */ + wptr = P2ALIGN(added, HUNTINGTON_RX_WPTR_ALIGN); + if (pushed == wptr) + return; + + *pushedp = wptr; + + /* Push the populated descriptors out */ + wptr &= erp->er_mask; + + EFX_POPULATE_DWORD_1(dword, ERF_DZ_RX_DESC_WPTR, wptr); + + /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */ + EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1, + wptr, pushed & erp->er_mask); + EFSYS_PIO_WRITE_BARRIER(); + EFX_BAR_TBL_WRITED(enp, ER_DZ_RX_DESC_UPD_REG, + erp->er_index, &dword, B_FALSE); +} + + __checkReturn int +hunt_rx_qflush( + __in efx_rxq_t *erp) +{ + efx_nic_t *enp = erp->er_enp; + int rc; + + if ((rc = efx_mcdi_fini_rxq(enp, erp->er_index)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + void +hunt_rx_qenable( + __in efx_rxq_t *erp) +{ + /* FIXME */ + _NOTE(ARGUNUSED(erp)) + /* FIXME */ +} + + __checkReturn int +hunt_rx_qcreate( + __in efx_nic_t *enp, + __in unsigned int index, + __in unsigned int label, + __in efx_rxq_type_t type, + __in efsys_mem_t *esmp, + __in size_t n, + __in uint32_t id, + __in efx_evq_t *eep, + __in efx_rxq_t *erp) +{ + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + int rc; + + _NOTE(ARGUNUSED(erp)) + + EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS == (1 << ESF_DZ_RX_QLABEL_WIDTH)); + EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS); + EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit); + + EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS)); + EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS)); + + if (!ISP2(n) || (n < EFX_RXQ_MINNDESCS) || (n > EFX_RXQ_MAXNDESCS)) { + rc = EINVAL; + goto fail1; + } + if (index >= encp->enc_rxq_limit) { + rc = EINVAL; + goto fail2; + } + + /* + * FIXME: Siena code handles different queue types (default, header + * split, scatter); we'll need to do something more here later, but + * all that stuff is TBD for now. + */ + + if ((rc = efx_mcdi_init_rxq(enp, n, eep->ee_index, label, index, + esmp)) != 0) + goto fail3; + + erp->er_eep = eep; + erp->er_label = label; + + hunt_ev_rxlabel_init(eep, erp, label); + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + void +hunt_rx_qdestroy( + __in efx_rxq_t *erp) +{ + efx_nic_t *enp = erp->er_enp; + efx_evq_t *eep = erp->er_eep; + unsigned int label = erp->er_label; + + hunt_ev_rxlabel_fini(eep, label); + + EFSYS_ASSERT(enp->en_rx_qcount != 0); + --enp->en_rx_qcount; + + EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp); +} + + void +hunt_rx_fini( + __in efx_nic_t *enp) +{ +#if EFSYS_OPT_RX_SCALE + if (enp->en_rss_support != EFX_RX_SCALE_UNAVAILABLE) { + (void) efx_mcdi_rss_context_free(enp, enp->en_rss_context); + } + enp->en_rss_context = 0; + enp->en_rss_support = EFX_RX_SCALE_UNAVAILABLE; +#else + _NOTE(ARGUNUSED(enp)) +#endif /* EFSYS_OPT_RX_SCALE */ +} + +#endif /* EFSYS_OPT_HUNTINGTON */ Property changes on: head/sys/dev/sfxge/common/hunt_rx.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/hunt_sram.c =================================================================== --- head/sys/dev/sfxge/common/hunt_sram.c (nonexistent) +++ head/sys/dev/sfxge/common/hunt_sram.c (revision 283514) @@ -0,0 +1,69 @@ +/*- + * Copyright (c) 2012-2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "efsys.h" +#include "efx.h" +#include "efx_impl.h" + +#if EFSYS_OPT_HUNTINGTON + + +#if EFSYS_OPT_DIAG + + __checkReturn int +hunt_sram_test( + __in efx_nic_t *enp, + __in efx_sram_pattern_fn_t func) +{ + int rc; + + /* FIXME */ + _NOTE(ARGUNUSED(enp)) + _NOTE(ARGUNUSED(func)) + if (B_FALSE) { + rc = ENOTSUP; + goto fail1; + } + /* FIXME */ + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +#endif /* EFSYS_OPT_DIAG */ + +#endif /* EFSYS_OPT_HUNTINGTON */ Property changes on: head/sys/dev/sfxge/common/hunt_sram.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/hunt_tx.c =================================================================== --- head/sys/dev/sfxge/common/hunt_tx.c (nonexistent) +++ head/sys/dev/sfxge/common/hunt_tx.c (revision 283514) @@ -0,0 +1,679 @@ +/*- + * Copyright (c) 2012-2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "efsys.h" +#include "efx.h" +#include "efx_impl.h" + + +#if EFSYS_OPT_HUNTINGTON + +#if EFSYS_OPT_QSTATS +#define EFX_TX_QSTAT_INCR(_etp, _stat) \ + do { \ + (_etp)->et_stat[_stat]++; \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) +#else +#define EFX_TX_QSTAT_INCR(_etp, _stat) +#endif + +static __checkReturn int +efx_mcdi_init_txq( + __in efx_nic_t *enp, + __in uint32_t size, + __in uint32_t target_evq, + __in uint32_t label, + __in uint32_t instance, + __in uint16_t flags, + __in efsys_mem_t *esmp) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_INIT_TXQ_IN_LEN(EFX_TXQ_MAX_BUFS), + MC_CMD_INIT_TXQ_OUT_LEN)]; + efx_qword_t *dma_addr; + uint64_t addr; + int npages; + int i; + int rc; + + EFSYS_ASSERT(EFX_TXQ_MAX_BUFS >= + EFX_TXQ_NBUFS(EFX_TXQ_MAXNDESCS(&enp->en_nic_cfg))); + + npages = EFX_TXQ_NBUFS(size); + if (npages > MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM) { + rc = EINVAL; + goto fail1; + } + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_INIT_TXQ; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_INIT_TXQ_IN_LEN(npages); + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_INIT_TXQ_OUT_LEN; + + MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_SIZE, size); + MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_TARGET_EVQ, target_evq); + MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_LABEL, label); + MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_INSTANCE, instance); + + MCDI_IN_POPULATE_DWORD_6(req, INIT_TXQ_IN_FLAGS, + INIT_TXQ_IN_FLAG_BUFF_MODE, 0, + INIT_TXQ_IN_FLAG_IP_CSUM_DIS, (flags & EFX_CKSUM_IPV4) ? 0 : 1, + INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, (flags & EFX_CKSUM_TCPUDP) ? 0 : 1, + INIT_TXQ_IN_FLAG_TCP_UDP_ONLY, 0, + INIT_TXQ_IN_CRC_MODE, 0, + INIT_TXQ_IN_FLAG_TIMESTAMP, 0); + + MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_OWNER_ID, 0); + MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); + + dma_addr = MCDI_IN2(req, efx_qword_t, INIT_TXQ_IN_DMA_ADDR); + addr = EFSYS_MEM_ADDR(esmp); + + for (i = 0; i < npages; i++) { + EFX_POPULATE_QWORD_2(*dma_addr, + EFX_DWORD_1, (uint32_t)(addr >> 32), + EFX_DWORD_0, (uint32_t)(addr & 0xffffffff)); + + dma_addr++; + addr += EFX_BUF_SIZE; + } + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail2; + } + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static __checkReturn int +efx_mcdi_fini_txq( + __in efx_nic_t *enp, + __in uint32_t instance) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_FINI_TXQ_IN_LEN, + MC_CMD_FINI_TXQ_OUT_LEN)]; + int rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_FINI_TXQ; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_FINI_TXQ_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_FINI_TXQ_OUT_LEN; + + MCDI_IN_SET_DWORD(req, FINI_TXQ_IN_INSTANCE, instance); + + efx_mcdi_execute(enp, &req); + + if ((req.emr_rc != 0) && (req.emr_rc != MC_CMD_ERR_EALREADY)) { + rc = req.emr_rc; + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_tx_init( + __in efx_nic_t *enp) +{ + _NOTE(ARGUNUSED(enp)) + return (0); +} + + void +hunt_tx_fini( + __in efx_nic_t *enp) +{ + _NOTE(ARGUNUSED(enp)) +} + + __checkReturn int +hunt_tx_qcreate( + __in efx_nic_t *enp, + __in unsigned int index, + __in unsigned int label, + __in efsys_mem_t *esmp, + __in size_t n, + __in uint32_t id, + __in uint16_t flags, + __in efx_evq_t *eep, + __in efx_txq_t *etp, + __out unsigned int *addedp) +{ + efx_qword_t desc; + int rc; + + + if ((rc = efx_mcdi_init_txq(enp, n, eep->ee_index, label, index, flags, + esmp)) != 0) + goto fail1; + + /* + * A previous user of this TX queue may have written a descriptor to the + * TX push collector, but not pushed the doorbell (e.g. after a crash). + * The next doorbell write would then push the stale descriptor. + * + * Ensure the (per network port) TX push collector is cleared by writing + * a no-op TX option descriptor. See bug29981 for details. + */ + *addedp = 1; + EFX_POPULATE_QWORD_4(desc, + ESF_DZ_TX_DESC_IS_OPT, 1, + ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_CRC_CSUM, + ESF_DZ_TX_OPTION_UDP_TCP_CSUM, (flags & EFX_CKSUM_TCPUDP) ? 1 : 0, + ESF_DZ_TX_OPTION_IP_CSUM, (flags & EFX_CKSUM_IPV4) ? 1 : 0); + + EFSYS_MEM_WRITEQ(etp->et_esmp, 0, &desc); + hunt_tx_qpush(etp, *addedp, 0); + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + void +hunt_tx_qdestroy( + __in efx_txq_t *etp) +{ + /* FIXME */ + _NOTE(ARGUNUSED(etp)) + /* FIXME */ +} + + __checkReturn int +hunt_tx_qpio_enable( + __in efx_txq_t *etp) +{ + efx_nic_t *enp = etp->et_enp; + efx_piobuf_handle_t handle; + int rc; + + if (etp->et_pio_size != 0) { + rc = EALREADY; + goto fail1; + } + + /* Sub-allocate a PIO block from a piobuf */ + if ((rc = hunt_nic_pio_alloc(enp, + &etp->et_pio_bufnum, + &handle, + &etp->et_pio_blknum, + &etp->et_pio_offset, + &etp->et_pio_size)) != 0) { + goto fail2; + } + EFSYS_ASSERT3U(etp->et_pio_size, !=, 0); + + /* Link the piobuf to this TXQ */ + if ((rc = hunt_nic_pio_link(enp, etp->et_index, handle)) != 0) { + goto fail3; + } + + /* + * et_pio_offset is the offset of the sub-allocated block within the + * hardware PIO buffer. It is used as the buffer address in the PIO + * option descriptor. + * + * et_pio_write_offset is the offset of the sub-allocated block from the + * start of the write-combined memory mapping, and is used for writing + * data into the PIO buffer. + */ + etp->et_pio_write_offset = + (etp->et_pio_bufnum * ER_DZ_TX_PIOBUF_STEP) + + ER_DZ_TX_PIOBUF_OFST + etp->et_pio_offset; + + return (0); + +fail3: + EFSYS_PROBE(fail3); + hunt_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum); + etp->et_pio_size = 0; +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + void +hunt_tx_qpio_disable( + __in efx_txq_t *etp) +{ + efx_nic_t *enp = etp->et_enp; + + if (etp->et_pio_size != 0) { + /* Unlink the piobuf from this TXQ */ + hunt_nic_pio_unlink(enp, etp->et_index); + + /* Free the sub-allocated PIO block */ + hunt_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum); + etp->et_pio_size = 0; + etp->et_pio_write_offset = 0; + } +} + + __checkReturn int +hunt_tx_qpio_write( + __in efx_txq_t *etp, + __in_ecount(length) uint8_t *buffer, + __in size_t length, + __in size_t offset) +{ + efx_nic_t *enp = etp->et_enp; + efsys_bar_t *esbp = enp->en_esbp; + uint32_t write_offset; + uint32_t write_offset_limit; + efx_qword_t *eqp; + int rc; + + EFSYS_ASSERT(length % sizeof (efx_qword_t) == 0); + + if (etp->et_pio_size == 0) { + rc = ENOENT; + goto fail1; + } + if (offset + length > etp->et_pio_size) { + rc = ENOSPC; + goto fail2; + } + + /* + * Writes to PIO buffers must be 64 bit aligned, and multiples of + * 64 bits. + */ + write_offset = etp->et_pio_write_offset + offset; + write_offset_limit = write_offset + length; + eqp = (efx_qword_t *)buffer; + while (write_offset < write_offset_limit) { + EFSYS_BAR_WC_WRITEQ(esbp, write_offset, eqp); + eqp++; + write_offset += sizeof (efx_qword_t); + } + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_tx_qpio_post( + __in efx_txq_t *etp, + __in size_t pkt_length, + __in unsigned int completed, + __inout unsigned int *addedp) +{ + efx_qword_t pio_desc; + unsigned int id; + size_t offset; + unsigned int added = *addedp; + int rc; + + + if (added - completed + 1 > EFX_TXQ_LIMIT(etp->et_mask + 1)) { + rc = ENOSPC; + goto fail1; + } + + if (etp->et_pio_size == 0) { + rc = ENOENT; + goto fail2; + } + + id = added++ & etp->et_mask; + offset = id * sizeof (efx_qword_t); + + EFSYS_PROBE4(tx_pio_post, unsigned int, etp->et_index, + unsigned int, id, uint32_t, etp->et_pio_offset, + size_t, pkt_length); + + EFX_POPULATE_QWORD_5(pio_desc, + ESF_DZ_TX_DESC_IS_OPT, 1, + ESF_DZ_TX_OPTION_TYPE, 1, + ESF_DZ_TX_PIO_CONT, 0, + ESF_DZ_TX_PIO_BYTE_CNT, pkt_length, + ESF_DZ_TX_PIO_BUF_ADDR, etp->et_pio_offset); + + EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &pio_desc); + + EFX_TX_QSTAT_INCR(etp, TX_POST_PIO); + + *addedp = added; + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_tx_qpost( + __in efx_txq_t *etp, + __in_ecount(n) efx_buffer_t *eb, + __in unsigned int n, + __in unsigned int completed, + __inout unsigned int *addedp) +{ + unsigned int added = *addedp; + unsigned int i; + int rc; + + if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) { + rc = ENOSPC; + goto fail1; + } + + for (i = 0; i < n; i++) { + efx_buffer_t *ebp = &eb[i]; + efsys_dma_addr_t addr = ebp->eb_addr; + size_t size = ebp->eb_size; + boolean_t eop = ebp->eb_eop; + unsigned int id; + size_t offset; + efx_qword_t qword; + + /* Fragments must not span 4k boundaries. */ + EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= (addr + size)); + + id = added++ & etp->et_mask; + offset = id * sizeof (efx_qword_t); + + EFSYS_PROBE5(tx_post, unsigned int, etp->et_index, + unsigned int, id, efsys_dma_addr_t, addr, + size_t, size, boolean_t, eop); + + EFX_POPULATE_QWORD_5(qword, + ESF_DZ_TX_KER_TYPE, 0, + ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1, + ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size), + ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff), + ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32)); + + EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &qword); + } + + EFX_TX_QSTAT_INCR(etp, TX_POST); + + *addedp = added; + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +/* + * This improves performance by pushing a TX descriptor at the same time as the + * doorbell. The descriptor must be added to the TXQ, so that can be used if the + * hardware decides not to use the pushed descriptor. + */ + void +hunt_tx_qpush( + __in efx_txq_t *etp, + __in unsigned int added, + __in unsigned int pushed) +{ + efx_nic_t *enp = etp->et_enp; + unsigned int wptr; + unsigned int id; + size_t offset; + efx_qword_t desc; + efx_oword_t oword; + + wptr = added & etp->et_mask; + id = pushed & etp->et_mask; + offset = id * sizeof (efx_qword_t); + + EFSYS_MEM_READQ(etp->et_esmp, offset, &desc); + EFX_POPULATE_OWORD_3(oword, + ERF_DZ_TX_DESC_WPTR, wptr, + ERF_DZ_TX_DESC_HWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_1), + ERF_DZ_TX_DESC_LWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_0)); + + /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */ + EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1, wptr, id); + EFSYS_PIO_WRITE_BARRIER(); + EFX_BAR_TBL_DOORBELL_WRITEO(enp, ER_DZ_TX_DESC_UPD_REG, etp->et_index, + &oword); +} + + __checkReturn int +hunt_tx_qdesc_post( + __in efx_txq_t *etp, + __in_ecount(n) efx_desc_t *ed, + __in unsigned int n, + __in unsigned int completed, + __inout unsigned int *addedp) +{ + unsigned int added = *addedp; + unsigned int i; + int rc; + + if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) { + rc = ENOSPC; + goto fail1; + } + + for (i = 0; i < n; i++) { + efx_desc_t *edp = &ed[i]; + unsigned int id; + size_t offset; + + id = added++ & etp->et_mask; + offset = id * sizeof (efx_desc_t); + + EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &edp->ed_eq); + } + + EFSYS_PROBE3(tx_desc_post, unsigned int, etp->et_index, + unsigned int, added, unsigned int, n); + + EFX_TX_QSTAT_INCR(etp, TX_POST); + + *addedp = added; + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + void +hunt_tx_qdesc_dma_create( + __in efx_txq_t *etp, + __in efsys_dma_addr_t addr, + __in size_t size, + __in boolean_t eop, + __out efx_desc_t *edp) +{ + /* Fragments must not span 4k boundaries. */ + EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= addr + size); + + EFSYS_PROBE4(tx_desc_dma_create, unsigned int, etp->et_index, + efsys_dma_addr_t, addr, + size_t, size, boolean_t, eop); + + EFX_POPULATE_QWORD_5(edp->ed_eq, + ESF_DZ_TX_KER_TYPE, 0, + ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1, + ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size), + ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff), + ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32)); +} + + void +hunt_tx_qdesc_tso_create( + __in efx_txq_t *etp, + __in uint16_t ipv4_id, + __in uint32_t tcp_seq, + __in uint8_t tcp_flags, + __out efx_desc_t *edp) +{ + EFSYS_PROBE4(tx_desc_tso_create, unsigned int, etp->et_index, + uint16_t, ipv4_id, uint32_t, tcp_seq, + uint8_t, tcp_flags); + + EFX_POPULATE_QWORD_5(edp->ed_eq, + ESF_DZ_TX_DESC_IS_OPT, 1, + ESF_DZ_TX_OPTION_TYPE, + ESE_DZ_TX_OPTION_DESC_TSO, + ESF_DZ_TX_TSO_TCP_FLAGS, tcp_flags, + ESF_DZ_TX_TSO_IP_ID, ipv4_id, + ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq); +} + + void +hunt_tx_qdesc_vlantci_create( + __in efx_txq_t *etp, + __in uint16_t tci, + __out efx_desc_t *edp) +{ + EFSYS_PROBE2(tx_desc_vlantci_create, unsigned int, etp->et_index, + uint16_t, tci); + + EFX_POPULATE_QWORD_4(edp->ed_eq, + ESF_DZ_TX_DESC_IS_OPT, 1, + ESF_DZ_TX_OPTION_TYPE, + ESE_DZ_TX_OPTION_DESC_VLAN, + ESF_DZ_TX_VLAN_OP, tci ? 1 : 0, + ESF_DZ_TX_VLAN_TAG1, tci); +} + + + __checkReturn int +hunt_tx_qpace( + __in efx_txq_t *etp, + __in unsigned int ns) +{ + int rc; + + /* FIXME */ + _NOTE(ARGUNUSED(etp, ns)) + if (B_FALSE) { + rc = ENOTSUP; + goto fail1; + } + /* FIXME */ + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_tx_qflush( + __in efx_txq_t *etp) +{ + efx_nic_t *enp = etp->et_enp; + int rc; + + if ((rc = efx_mcdi_fini_txq(enp, etp->et_index)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + void +hunt_tx_qenable( + __in efx_txq_t *etp) +{ + /* FIXME */ + _NOTE(ARGUNUSED(etp)) + /* FIXME */ +} + +#if EFSYS_OPT_QSTATS + void +hunt_tx_qstats_update( + __in efx_txq_t *etp, + __inout_ecount(TX_NQSTATS) efsys_stat_t *stat) +{ + /* + * TBD: Consider a common Siena/Huntington function. The code is + * essentially identical. + */ + + unsigned int id; + + for (id = 0; id < TX_NQSTATS; id++) { + efsys_stat_t *essp = &stat[id]; + + EFSYS_STAT_INCR(essp, etp->et_stat[id]); + etp->et_stat[id] = 0; + } +} + +#endif /* EFSYS_OPT_QSTATS */ + +#endif /* EFSYS_OPT_HUNTINGTON */ Property changes on: head/sys/dev/sfxge/common/hunt_tx.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/hunt_vpd.c =================================================================== --- head/sys/dev/sfxge/common/hunt_vpd.c (nonexistent) +++ head/sys/dev/sfxge/common/hunt_vpd.c (revision 283514) @@ -0,0 +1,435 @@ +/*- + * Copyright (c) 2009-2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "efsys.h" +#include "efx.h" +#include "efx_types.h" +#include "efx_regs.h" +#include "efx_impl.h" + + +#if EFSYS_OPT_VPD + +#if EFSYS_OPT_HUNTINGTON + +#include "ef10_tlv_layout.h" + + __checkReturn int +hunt_vpd_init( + __in efx_nic_t *enp) +{ + caddr_t svpd; + size_t svpd_size; + uint32_t pci_pf; + int rc; + + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + + pci_pf = enp->en_nic_cfg.enc_pf; + /* + * The VPD interface exposes VPD resources from the combined static and + * dynamic VPD storage. As the static VPD configuration should *never* + * change, we can cache it. + */ + svpd = NULL; + svpd_size = 0; + rc = hunt_nvram_partn_read_tlv(enp, + NVRAM_PARTITION_TYPE_STATIC_CONFIG, + TLV_TAG_PF_STATIC_VPD(pci_pf), + &svpd, &svpd_size); + if (rc != 0) { + if (rc == EACCES) { + /* Unpriviledged functions cannot access VPD */ + goto out; + } + goto fail1; + } + + if (svpd != NULL && svpd_size > 0) { + if ((rc = efx_vpd_hunk_verify(svpd, svpd_size, NULL)) != 0) + goto fail2; + } + + enp->en_u.hunt.enu_svpd = svpd; + enp->en_u.hunt.enu_svpd_length = svpd_size; + +out: + return (0); + +fail2: + EFSYS_PROBE(fail2); + + EFSYS_KMEM_FREE(enp->en_esip, svpd_size, svpd); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_vpd_size( + __in efx_nic_t *enp, + __out size_t *sizep) +{ + int rc; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + + /* + * This function returns the total size the user should allocate + * for all VPD operations. We've already cached the static vpd, + * so we just need to return an upper bound on the dynamic vpd, + * which is the size of the DYNAMIC_CONFIG partition. + */ + if ((rc = efx_mcdi_nvram_info(enp, NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, + sizep, NULL, NULL)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_vpd_read( + __in efx_nic_t *enp, + __out_bcount(size) caddr_t data, + __in size_t size) +{ + caddr_t dvpd; + size_t dvpd_size; + uint32_t pci_pf; + int rc; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + + pci_pf = enp->en_nic_cfg.enc_pf; + + if ((rc = hunt_nvram_partn_read_tlv(enp, + NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, + TLV_TAG_PF_DYNAMIC_VPD(pci_pf), + &dvpd, &dvpd_size)) != 0) + goto fail1; + + if (dvpd_size > size) { + rc = ENOSPC; + goto fail2; + } + memcpy(data, dvpd, dvpd_size); + + /* Pad data with all-1s, consistent with update operations */ + memset(data + dvpd_size, 0xff, size - dvpd_size); + + EFSYS_KMEM_FREE(enp->en_esip, dvpd_size, dvpd); + + return (0); + +fail2: + EFSYS_PROBE(fail2); + + EFSYS_KMEM_FREE(enp->en_esip, dvpd_size, dvpd); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_vpd_verify( + __in efx_nic_t *enp, + __in_bcount(size) caddr_t data, + __in size_t size) +{ + efx_vpd_tag_t stag; + efx_vpd_tag_t dtag; + efx_vpd_keyword_t skey; + efx_vpd_keyword_t dkey; + unsigned int scont; + unsigned int dcont; + int rc; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + + /* + * Strictly you could take the view that dynamic vpd is optional. + * Instead, to conform more closely to the read/verify/reinit() + * paradigm, we require dynamic vpd. hunt_vpd_reinit() will + * reinitialize it as required. + */ + if ((rc = efx_vpd_hunk_verify(data, size, NULL)) != 0) + goto fail1; + + /* + * Verify that there is no duplication between the static and + * dynamic cfg sectors. + */ + if (enp->en_u.hunt.enu_svpd_length == 0) + goto done; + + dcont = 0; + _NOTE(CONSTANTCONDITION) + while (1) { + if ((rc = efx_vpd_hunk_next(data, size, &dtag, + &dkey, NULL, NULL, &dcont)) != 0) + goto fail2; + if (dcont == 0) + break; + + scont = 0; + _NOTE(CONSTANTCONDITION) + while (1) { + if ((rc = efx_vpd_hunk_next( + enp->en_u.hunt.enu_svpd, + enp->en_u.hunt.enu_svpd_length, &stag, &skey, + NULL, NULL, &scont)) != 0) + goto fail3; + if (scont == 0) + break; + + if (stag == dtag && skey == dkey) { + rc = EEXIST; + goto fail4; + } + } + } + +done: + return (0); + +fail4: + EFSYS_PROBE(fail4); +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_vpd_reinit( + __in efx_nic_t *enp, + __in_bcount(size) caddr_t data, + __in size_t size) +{ + boolean_t wantpid; + int rc; + + /* + * Only create an ID string if the dynamic cfg doesn't have one + */ + if (enp->en_u.hunt.enu_svpd_length == 0) + wantpid = B_TRUE; + else { + unsigned int offset; + uint8_t length; + + rc = efx_vpd_hunk_get(enp->en_u.hunt.enu_svpd, + enp->en_u.hunt.enu_svpd_length, + EFX_VPD_ID, 0, &offset, &length); + if (rc == 0) + wantpid = B_FALSE; + else if (rc == ENOENT) + wantpid = B_TRUE; + else + goto fail1; + } + + if ((rc = efx_vpd_hunk_reinit(data, size, wantpid)) != 0) + goto fail2; + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_vpd_get( + __in efx_nic_t *enp, + __in_bcount(size) caddr_t data, + __in size_t size, + __inout efx_vpd_value_t *evvp) +{ + unsigned int offset; + uint8_t length; + int rc; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + + /* Attempt to satisfy the request from svpd first */ + if (enp->en_u.hunt.enu_svpd_length > 0) { + if ((rc = efx_vpd_hunk_get(enp->en_u.hunt.enu_svpd, + enp->en_u.hunt.enu_svpd_length, evvp->evv_tag, + evvp->evv_keyword, &offset, &length)) == 0) { + evvp->evv_length = length; + memcpy(evvp->evv_value, + enp->en_u.hunt.enu_svpd + offset, length); + return (0); + } else if (rc != ENOENT) + goto fail1; + } + + /* And then from the provided data buffer */ + if ((rc = efx_vpd_hunk_get(data, size, evvp->evv_tag, + evvp->evv_keyword, &offset, &length)) != 0) + goto fail2; + + evvp->evv_length = length; + memcpy(evvp->evv_value, data + offset, length); + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_vpd_set( + __in efx_nic_t *enp, + __in_bcount(size) caddr_t data, + __in size_t size, + __in efx_vpd_value_t *evvp) +{ + int rc; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + + /* If the provided (tag,keyword) exists in svpd, then it is readonly */ + if (enp->en_u.hunt.enu_svpd_length > 0) { + unsigned int offset; + uint8_t length; + + if ((rc = efx_vpd_hunk_get(enp->en_u.hunt.enu_svpd, + enp->en_u.hunt.enu_svpd_length, evvp->evv_tag, + evvp->evv_keyword, &offset, &length)) == 0) { + rc = EACCES; + goto fail1; + } + } + + if ((rc = efx_vpd_hunk_set(data, size, evvp)) != 0) + goto fail2; + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +hunt_vpd_next( + __in efx_nic_t *enp, + __in_bcount(size) caddr_t data, + __in size_t size, + __out efx_vpd_value_t *evvp, + __inout unsigned int *contp) +{ + _NOTE(ARGUNUSED(enp, data, size, evvp, contp)) + + return (ENOTSUP); +} + + __checkReturn int +hunt_vpd_write( + __in efx_nic_t *enp, + __in_bcount(size) caddr_t data, + __in size_t size) +{ + size_t vpd_length; + uint32_t pci_pf; + int rc; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + + pci_pf = enp->en_nic_cfg.enc_pf; + + /* Determine total length of new dynamic VPD */ + if ((rc = efx_vpd_hunk_length(data, size, &vpd_length)) != 0) + goto fail1; + + /* Store new dynamic VPD in DYNAMIC_CONFIG partition */ + if ((rc = hunt_nvram_partn_write_tlv(enp, + NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, + TLV_TAG_PF_DYNAMIC_VPD(pci_pf), + data, vpd_length)) != 0) { + goto fail2; + } + + return (0); + +fail2: + EFSYS_PROBE(fail2); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + void +hunt_vpd_fini( + __in efx_nic_t *enp) +{ + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + + if (enp->en_u.hunt.enu_svpd_length > 0) { + EFSYS_KMEM_FREE(enp->en_esip, enp->en_u.hunt.enu_svpd_length, + enp->en_u.hunt.enu_svpd); + + enp->en_u.hunt.enu_svpd = NULL; + enp->en_u.hunt.enu_svpd_length = 0; + } +} + +#endif /* EFSYS_OPT_HUNTINGTON */ + +#endif /* EFSYS_OPT_VPD */ Property changes on: head/sys/dev/sfxge/common/hunt_vpd.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/mcdi_mon.c =================================================================== --- head/sys/dev/sfxge/common/mcdi_mon.c (nonexistent) +++ head/sys/dev/sfxge/common/mcdi_mon.c (revision 283514) @@ -0,0 +1,552 @@ +/*- + * Copyright (c) 2009-2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "efsys.h" +#include "efx.h" +#include "efx_impl.h" + +#if EFSYS_OPT_MON_MCDI + +#if EFSYS_OPT_MON_STATS + +#define MCDI_MON_NEXT_PAGE (uint16_t)0xfffe +#define MCDI_MON_INVALID_SENSOR (uint16_t)0xfffd +#define MCDI_MON_PAGE_SIZE 0x20 + +/* Bitmasks of valid port(s) for each sensor */ +#define MCDI_MON_PORT_NONE (0x00) +#define MCDI_MON_PORT_P1 (0x01) +#define MCDI_MON_PORT_P2 (0x02) +#define MCDI_MON_PORT_P3 (0x04) +#define MCDI_MON_PORT_P4 (0x08) +#define MCDI_MON_PORT_Px (0xFFFF) + +/* Entry for MCDI sensor in sensor map */ +#define STAT(portmask, stat) \ + { (MCDI_MON_PORT_##portmask), (EFX_MON_STAT_##stat) } + +/* Entry for sensor next page flag in sensor map */ +#define STAT_NEXT_PAGE() \ + { MCDI_MON_PORT_NONE, MCDI_MON_NEXT_PAGE } + +/* Placeholder for gaps in the array */ +#define STAT_NO_SENSOR() \ + { MCDI_MON_PORT_NONE, MCDI_MON_INVALID_SENSOR } + +/* Map from MC sensors to monitor statistics */ +static const struct mcdi_sensor_map_s { + uint16_t msm_port_mask; + uint16_t msm_stat; +} mcdi_sensor_map[] = { + /* Sensor page 0 MC_CMD_SENSOR_xxx */ + STAT(Px, INT_TEMP), /* 0x00 CONTROLLER_TEMP */ + STAT(Px, EXT_TEMP), /* 0x01 PHY_COMMON_TEMP */ + STAT(Px, INT_COOLING), /* 0x02 CONTROLLER_COOLING */ + STAT(P1, EXT_TEMP), /* 0x03 PHY0_TEMP */ + STAT(P1, EXT_COOLING), /* 0x04 PHY0_COOLING */ + STAT(P2, EXT_TEMP), /* 0x05 PHY1_TEMP */ + STAT(P2, EXT_COOLING), /* 0x06 PHY1_COOLING */ + STAT(Px, 1V), /* 0x07 IN_1V0 */ + STAT(Px, 1_2V), /* 0x08 IN_1V2 */ + STAT(Px, 1_8V), /* 0x09 IN_1V8 */ + STAT(Px, 2_5V), /* 0x0a IN_2V5 */ + STAT(Px, 3_3V), /* 0x0b IN_3V3 */ + STAT(Px, 12V), /* 0x0c IN_12V0 */ + STAT(Px, 1_2VA), /* 0x0d IN_1V2A */ + STAT(Px, VREF), /* 0x0e IN_VREF */ + STAT(Px, VAOE), /* 0x0f OUT_VAOE */ + STAT(Px, AOE_TEMP), /* 0x10 AOE_TEMP */ + STAT(Px, PSU_AOE_TEMP), /* 0x11 PSU_AOE_TEMP */ + STAT(Px, PSU_TEMP), /* 0x12 PSU_TEMP */ + STAT(Px, FAN0), /* 0x13 FAN_0 */ + STAT(Px, FAN1), /* 0x14 FAN_1 */ + STAT(Px, FAN2), /* 0x15 FAN_2 */ + STAT(Px, FAN3), /* 0x16 FAN_3 */ + STAT(Px, FAN4), /* 0x17 FAN_4 */ + STAT(Px, VAOE_IN), /* 0x18 IN_VAOE */ + STAT(Px, IAOE), /* 0x19 OUT_IAOE */ + STAT(Px, IAOE_IN), /* 0x1a IN_IAOE */ + STAT(Px, NIC_POWER), /* 0x1b NIC_POWER */ + STAT(Px, 0_9V), /* 0x1c IN_0V9 */ + STAT(Px, I0_9V), /* 0x1d IN_I0V9 */ + STAT(Px, I1_2V), /* 0x1e IN_I1V2 */ + STAT_NEXT_PAGE(), /* 0x1f Next page flag (not a sensor) */ + + /* Sensor page 1 MC_CMD_SENSOR_xxx */ + STAT(Px, 0_9V_ADC), /* 0x20 IN_0V9_ADC */ + STAT(Px, INT_TEMP2), /* 0x21 CONTROLLER_2_TEMP */ + STAT(Px, VREG_TEMP), /* 0x22 VREG_INTERNAL_TEMP */ + STAT(Px, VREG_0_9V_TEMP), /* 0x23 VREG_0V9_TEMP */ + STAT(Px, VREG_1_2V_TEMP), /* 0x24 VREG_1V2_TEMP */ + STAT(Px, INT_VPTAT), /* 0x25 CTRLR. VPTAT */ + STAT(Px, INT_ADC_TEMP), /* 0x26 CTRLR. INTERNAL_TEMP */ + STAT(Px, EXT_VPTAT), /* 0x27 CTRLR. VPTAT_EXTADC */ + STAT(Px, EXT_ADC_TEMP), /* 0x28 CTRLR. INTERNAL_TEMP_EXTADC */ + STAT(Px, AMBIENT_TEMP), /* 0x29 AMBIENT_TEMP */ + STAT(Px, AIRFLOW), /* 0x2a AIRFLOW */ + STAT(Px, VDD08D_VSS08D_CSR), /* 0x2b VDD08D_VSS08D_CSR */ + STAT(Px, VDD08D_VSS08D_CSR_EXTADC), /* 0x2c VDD08D_VSS08D_CSR_EXTADC */ + STAT(Px, HOTPOINT_TEMP), /* 0x2d HOTPOINT_TEMP */ + STAT(P1, PHY_POWER_SWITCH_PORT0), /* 0x2e PHY_POWER_SWITCH_PORT0 */ + STAT(P2, PHY_POWER_SWITCH_PORT1), /* 0x2f PHY_POWER_SWITCH_PORT1 */ + STAT(Px, MUM_VCC), /* 0x30 MUM_VCC */ + STAT(Px, 0V9_A), /* 0x31 0V9_A */ + STAT(Px, I0V9_A), /* 0x32 I0V9_A */ + STAT(Px, 0V9_A_TEMP), /* 0x33 0V9_A_TEMP */ + STAT(Px, 0V9_B), /* 0x34 0V9_B */ + STAT(Px, I0V9_B), /* 0x35 I0V9_B */ + STAT(Px, 0V9_B_TEMP), /* 0x36 0V9_B_TEMP */ + STAT(Px, CCOM_AVREG_1V2_SUPPLY), /* 0x37 CCOM_AVREG_1V2_SUPPLY */ + STAT(Px, CCOM_AVREG_1V2_SUPPLY_EXT_ADC), + /* 0x38 CCOM_AVREG_1V2_SUPPLY_EXT_ADC */ + STAT(Px, CCOM_AVREG_1V8_SUPPLY), /* 0x39 CCOM_AVREG_1V8_SUPPLY */ + STAT(Px, CCOM_AVREG_1V8_SUPPLY_EXT_ADC), + /* 0x3a CCOM_AVREG_1V8_SUPPLY_EXT_ADC */ + STAT_NO_SENSOR(), /* 0x3b (no sensor) */ + STAT_NO_SENSOR(), /* 0x3c (no sensor) */ + STAT_NO_SENSOR(), /* 0x3d (no sensor) */ + STAT_NO_SENSOR(), /* 0x3e (no sensor) */ + STAT_NEXT_PAGE(), /* 0x3f Next page flag (not a sensor) */ + + /* Sensor page 2 MC_CMD_SENSOR_xxx */ + STAT(Px, CONTROLLER_MASTER_VPTAT), /* 0x40 MASTER_VPTAT */ + STAT(Px, CONTROLLER_MASTER_INTERNAL_TEMP), /* 0x41 MASTER_INT_TEMP */ + STAT(Px, CONTROLLER_MASTER_VPTAT_EXT_ADC), /* 0x42 MAST_VPTAT_EXT_ADC */ + STAT(Px, CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC), + /* 0x43 MASTER_INTERNAL_TEMP_EXT_ADC */ + STAT(Px, CONTROLLER_SLAVE_VPTAT), /* 0x44 SLAVE_VPTAT */ + STAT(Px, CONTROLLER_SLAVE_INTERNAL_TEMP), /* 0x45 SLAVE_INTERNAL_TEMP */ + STAT(Px, CONTROLLER_SLAVE_VPTAT_EXT_ADC), /* 0x46 SLAVE_VPTAT_EXT_ADC */ + STAT(Px, CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC), + /* 0x47 SLAVE_INTERNAL_TEMP_EXT_ADC */ +}; + +#define MCDI_STATIC_SENSOR_ASSERT(_field) \ + EFX_STATIC_ASSERT(MC_CMD_SENSOR_STATE_ ## _field \ + == EFX_MON_STAT_STATE_ ## _field) + +static void +mcdi_mon_decode_stats( + __in efx_nic_t *enp, + __in_ecount(sensor_mask_size) uint32_t *sensor_mask, + __in size_t sensor_mask_size, + __in_opt efsys_mem_t *esmp, + __out_ecount_opt(sensor_mask_size) uint32_t *stat_maskp, + __out_ecount_opt(EFX_MON_NSTATS) efx_mon_stat_value_t *stat) +{ + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + uint16_t port_mask; + uint16_t sensor; + size_t sensor_max; + uint32_t stat_mask[(EFX_ARRAY_SIZE(mcdi_sensor_map) + 31) / 32]; + uint32_t idx = 0; + uint32_t page = 0; + + /* Assert the MC_CMD_SENSOR and EFX_MON_STATE namespaces agree */ + MCDI_STATIC_SENSOR_ASSERT(OK); + MCDI_STATIC_SENSOR_ASSERT(WARNING); + MCDI_STATIC_SENSOR_ASSERT(FATAL); + MCDI_STATIC_SENSOR_ASSERT(BROKEN); + MCDI_STATIC_SENSOR_ASSERT(NO_READING); + + EFX_STATIC_ASSERT(sizeof (stat_mask[0]) * 8 == + EFX_MON_MASK_ELEMENT_SIZE); + sensor_max = + MIN((8 * sensor_mask_size), EFX_ARRAY_SIZE(mcdi_sensor_map)); + + port_mask = 1U << emip->emi_port; + + memset(stat_mask, 0, sizeof (stat_mask)); + + /* + * The MCDI sensor readings in the DMA buffer are a packed array of + * MC_CMD_SENSOR_VALUE_ENTRY structures, which only includes entries for + * supported sensors (bit set in sensor_mask). The sensor_mask and + * sensor readings do not include entries for the per-page NEXT_PAGE + * flag. + * + * sensor_mask may legitimately contain MCDI sensors that the driver + * does not understand. + */ + for (sensor = 0; sensor < sensor_max; ++sensor) { + efx_mon_stat_t id = mcdi_sensor_map[sensor].msm_stat; + + if ((sensor % MCDI_MON_PAGE_SIZE) == MC_CMD_SENSOR_PAGE0_NEXT) { + EFSYS_ASSERT3U(id, ==, MCDI_MON_NEXT_PAGE); + page++; + continue; + } + if (~(sensor_mask[page]) & (1U << sensor)) + continue; + idx++; + + if ((port_mask & mcdi_sensor_map[sensor].msm_port_mask) == 0) + continue; + EFSYS_ASSERT(id < EFX_MON_NSTATS); + + /* + * stat_mask is a bitmask indexed by EFX_MON_* monitor statistic + * identifiers from efx_mon_stat_t (without NEXT_PAGE bits). + * + * If there is an entry in the MCDI sensor to monitor statistic + * map then the sensor reading is used for the value of the + * monitor statistic. + */ + stat_mask[id / EFX_MON_MASK_ELEMENT_SIZE] |= + (1U << (id % EFX_MON_MASK_ELEMENT_SIZE)); + + if (stat != NULL && esmp != NULL && !EFSYS_MEM_IS_NULL(esmp)) { + efx_dword_t dword; + + /* Get MCDI sensor reading from DMA buffer */ + EFSYS_MEM_READD(esmp, 4 * (idx - 1), &dword); + + /* Update EFX monitor stat from MCDI sensor reading */ + stat[id].emsv_value = (uint16_t)EFX_DWORD_FIELD(dword, + MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE); + + stat[id].emsv_state = (uint16_t)EFX_DWORD_FIELD(dword, + MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE); + } + } + + if (stat_maskp != NULL) { + memcpy(stat_maskp, stat_mask, sizeof (stat_mask)); + } +} + + __checkReturn int +mcdi_mon_ev( + __in efx_nic_t *enp, + __in efx_qword_t *eqp, + __out efx_mon_stat_t *idp, + __out efx_mon_stat_value_t *valuep) +{ + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + uint16_t port_mask; + uint16_t sensor; + uint16_t state; + uint16_t value; + efx_mon_stat_t id; + int rc; + + port_mask = (emip->emi_port == 1) + ? MCDI_MON_PORT_P1 + : MCDI_MON_PORT_P2; + + sensor = (uint16_t)MCDI_EV_FIELD(eqp, SENSOREVT_MONITOR); + state = (uint16_t)MCDI_EV_FIELD(eqp, SENSOREVT_STATE); + value = (uint16_t)MCDI_EV_FIELD(eqp, SENSOREVT_VALUE); + + /* Hardware must support this MCDI sensor */ + EFSYS_ASSERT3U(sensor, <, (8 * encp->enc_mcdi_sensor_mask_size)); + EFSYS_ASSERT((sensor % MCDI_MON_PAGE_SIZE) != MC_CMD_SENSOR_PAGE0_NEXT); + EFSYS_ASSERT(encp->enc_mcdi_sensor_maskp != NULL); + EFSYS_ASSERT((encp->enc_mcdi_sensor_maskp[sensor / MCDI_MON_PAGE_SIZE] & + (1U << (sensor % MCDI_MON_PAGE_SIZE))) != 0); + + /* But we don't have to understand it */ + if (sensor >= EFX_ARRAY_SIZE(mcdi_sensor_map)) { + rc = ENOTSUP; + goto fail1; + } + id = mcdi_sensor_map[sensor].msm_stat; + if ((port_mask & mcdi_sensor_map[sensor].msm_port_mask) == 0) + return (ENODEV); + EFSYS_ASSERT(id < EFX_MON_NSTATS); + + *idp = id; + valuep->emsv_value = value; + valuep->emsv_state = state; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + +static __checkReturn int +efx_mcdi_read_sensors( + __in efx_nic_t *enp, + __in efsys_mem_t *esmp, + __in uint32_t size) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_READ_SENSORS_EXT_IN_LEN, + MC_CMD_READ_SENSORS_EXT_OUT_LEN)]; + uint32_t addr_lo, addr_hi; + + req.emr_cmd = MC_CMD_READ_SENSORS; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_READ_SENSORS_EXT_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_READ_SENSORS_EXT_OUT_LEN; + + addr_lo = (uint32_t)(EFSYS_MEM_ADDR(esmp) & 0xffffffff); + addr_hi = (uint32_t)(EFSYS_MEM_ADDR(esmp) >> 32); + + MCDI_IN_SET_DWORD(req, READ_SENSORS_EXT_IN_DMA_ADDR_LO, addr_lo); + MCDI_IN_SET_DWORD(req, READ_SENSORS_EXT_IN_DMA_ADDR_HI, addr_hi); + MCDI_IN_SET_DWORD(req, READ_SENSORS_EXT_IN_LENGTH, size); + + efx_mcdi_execute(enp, &req); + + return (req.emr_rc); +} + +static __checkReturn int +efx_mcdi_sensor_info_npages( + __in efx_nic_t *enp, + __out uint32_t *npagesp) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_SENSOR_INFO_EXT_IN_LEN, + MC_CMD_SENSOR_INFO_OUT_LENMAX)]; + int page; + int rc; + + EFSYS_ASSERT(npagesp != NULL); + + page = 0; + do { + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_SENSOR_INFO; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_SENSOR_INFO_EXT_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_SENSOR_INFO_OUT_LENMAX; + + MCDI_IN_SET_DWORD(req, SENSOR_INFO_EXT_IN_PAGE, page++); + + efx_mcdi_execute_quiet(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + } while (MCDI_OUT_DWORD(req, SENSOR_INFO_OUT_MASK) & + (1 << MC_CMD_SENSOR_PAGE0_NEXT)); + + *npagesp = page; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + +static __checkReturn int +efx_mcdi_sensor_info( + __in efx_nic_t *enp, + __out_ecount(npages) uint32_t *sensor_maskp, + __in size_t npages) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_SENSOR_INFO_EXT_IN_LEN, + MC_CMD_SENSOR_INFO_OUT_LENMAX)]; + uint32_t page; + int rc; + + EFSYS_ASSERT(sensor_maskp != NULL); + + for (page = 0; page < npages; page++) { + uint32_t mask; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_SENSOR_INFO; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_SENSOR_INFO_EXT_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_SENSOR_INFO_OUT_LENMAX; + + MCDI_IN_SET_DWORD(req, SENSOR_INFO_EXT_IN_PAGE, page); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + mask = MCDI_OUT_DWORD(req, SENSOR_INFO_OUT_MASK); + + if ((page != (npages - 1)) && + ((mask & (1U << MC_CMD_SENSOR_PAGE0_NEXT)) == 0)) { + rc = EINVAL; + goto fail2; + } + sensor_maskp[page] = mask; + } + + if (sensor_maskp[npages - 1] & (1U << MC_CMD_SENSOR_PAGE0_NEXT)) { + rc = EINVAL; + goto fail3; + } + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +mcdi_mon_stats_update( + __in efx_nic_t *enp, + __in efsys_mem_t *esmp, + __out_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values) +{ + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + uint32_t size = encp->enc_mon_stat_dma_buf_size; + int rc; + + if ((rc = efx_mcdi_read_sensors(enp, esmp, size)) != 0) + goto fail1; + + EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, size); + + mcdi_mon_decode_stats(enp, + encp->enc_mcdi_sensor_maskp, + encp->enc_mcdi_sensor_mask_size, + esmp, NULL, values); + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + __checkReturn int +mcdi_mon_cfg_build( + __in efx_nic_t *enp) +{ + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + uint32_t npages; + int rc; + + switch (enp->en_family) { +#if EFSYS_OPT_SIENA + case EFX_FAMILY_SIENA: + encp->enc_mon_type = EFX_MON_SFC90X0; + break; +#endif +#if EFSYS_OPT_HUNTINGTON + case EFX_FAMILY_HUNTINGTON: + encp->enc_mon_type = EFX_MON_SFC91X0; + break; +#endif + default: + rc = EINVAL; + goto fail1; + } + + /* Get mc sensor mask size */ + npages = 0; + if ((rc = efx_mcdi_sensor_info_npages(enp, &npages)) != 0) + goto fail2; + + encp->enc_mon_stat_dma_buf_size = npages * EFX_MON_STATS_PAGE_SIZE; + encp->enc_mcdi_sensor_mask_size = npages * sizeof (uint32_t); + + /* Allocate mc sensor mask */ + EFSYS_KMEM_ALLOC(enp->en_esip, + encp->enc_mcdi_sensor_mask_size, + encp->enc_mcdi_sensor_maskp); + + if (encp->enc_mcdi_sensor_maskp == NULL) { + rc = ENOMEM; + goto fail3; + } + + /* Read mc sensor mask */ + if ((rc = efx_mcdi_sensor_info(enp, + encp->enc_mcdi_sensor_maskp, + npages)) != 0) + goto fail4; + + /* Build monitor statistics mask */ + mcdi_mon_decode_stats(enp, + encp->enc_mcdi_sensor_maskp, + encp->enc_mcdi_sensor_mask_size, + NULL, encp->enc_mon_stat_mask, NULL); + + return (0); + +fail4: + EFSYS_PROBE(fail4); + EFSYS_KMEM_FREE(enp->en_esip, + encp->enc_mcdi_sensor_mask_size, + encp->enc_mcdi_sensor_maskp); + +fail3: + EFSYS_PROBE(fail3); + +fail2: + EFSYS_PROBE(fail2); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + void +mcdi_mon_cfg_free( + __in efx_nic_t *enp) +{ + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + + if (encp->enc_mcdi_sensor_maskp != NULL) { + EFSYS_KMEM_FREE(enp->en_esip, + encp->enc_mcdi_sensor_mask_size, + encp->enc_mcdi_sensor_maskp); + } +} + + +#endif /* EFSYS_OPT_MON_STATS */ + +#endif /* EFSYS_OPT_MON_MCDI */ Property changes on: head/sys/dev/sfxge/common/mcdi_mon.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/mcdi_mon.h =================================================================== --- head/sys/dev/sfxge/common/mcdi_mon.h (nonexistent) +++ head/sys/dev/sfxge/common/mcdi_mon.h (revision 283514) @@ -0,0 +1,76 @@ +/*- + * Copyright (c) 2009-2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + * + * $FreeBSD$ + */ + +#ifndef _SYS_MCDI_MON_H +#define _SYS_MCDI_MON_H + +#include "efx.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if EFSYS_OPT_MON_MCDI + +#if EFSYS_OPT_MON_STATS + + __checkReturn int +mcdi_mon_cfg_build( + __in efx_nic_t *enp); + + void +mcdi_mon_cfg_free( + __in efx_nic_t *enp); + + +extern __checkReturn int +mcdi_mon_ev( + __in efx_nic_t *enp, + __in efx_qword_t *eqp, + __out efx_mon_stat_t *idp, + __out efx_mon_stat_value_t *valuep); + +extern __checkReturn int +mcdi_mon_stats_update( + __in efx_nic_t *enp, + __in efsys_mem_t *esmp, + __out_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); + +#endif /* EFSYS_OPT_MON_STATS */ + +#endif /* EFSYS_OPT_MON_MCDI */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_MCDI_MON_H */ Property changes on: head/sys/dev/sfxge/common/mcdi_mon.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/siena_flash.h =================================================================== --- head/sys/dev/sfxge/common/siena_flash.h (revision 283513) +++ head/sys/dev/sfxge/common/siena_flash.h (revision 283514) @@ -1,135 +1,201 @@ /*- - * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2007-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + * * $FreeBSD$ */ #ifndef _SYS_SIENA_FLASH_H #define _SYS_SIENA_FLASH_H #pragma pack(1) /* Fixed locations near the start of flash (which may be in the internal PHY * firmware header) point to the boot header. * * - parsed by MC boot ROM and firmware * - reserved (but not parsed) by PHY firmware * - opaque to driver */ #define SIENA_MC_BOOT_PHY_FW_HDR_LEN (0x20) #define SIENA_MC_BOOT_PTR_LOCATION (0x18) /* First thing we try to boot */ #define SIENA_MC_BOOT_ALT_PTR_LOCATION (0x1c) /* Alternative if that fails */ #define SIENA_MC_BOOT_HDR_LEN (0x200) #define SIENA_MC_BOOT_MAGIC (0x51E4A001) #define SIENA_MC_BOOT_VERSION (1) + +/*Structures supporting an arbitrary number of binary blobs in the flash image + intended to house code and tables for the satellite cpus*/ +/*thanks to random.org for:*/ +#define BLOBS_HEADER_MAGIC (0xBDA3BBD4) +#define BLOB_HEADER_MAGIC (0xA1478A91) + +typedef struct blobs_hdr_s { /* GENERATED BY scripts/genfwdef */ + efx_dword_t magic; + efx_dword_t no_of_blobs; +} blobs_hdr_t; + +typedef struct blob_hdr_s { /* GENERATED BY scripts/genfwdef */ + efx_dword_t magic; + efx_dword_t cpu_type; + efx_dword_t build_variant; + efx_dword_t offset; + efx_dword_t length; + efx_dword_t checksum; +} blob_hdr_t; + +#define BLOB_CPU_TYPE_TXDI_TEXT (0) +#define BLOB_CPU_TYPE_RXDI_TEXT (1) +#define BLOB_CPU_TYPE_TXDP_TEXT (2) +#define BLOB_CPU_TYPE_RXDP_TEXT (3) +#define BLOB_CPU_TYPE_RXHRSL_HR_LUT (4) +#define BLOB_CPU_TYPE_RXHRSL_HR_LUT_CFG (5) +#define BLOB_CPU_TYPE_TXHRSL_HR_LUT (6) +#define BLOB_CPU_TYPE_TXHRSL_HR_LUT_CFG (7) +#define BLOB_CPU_TYPE_RXHRSL_HR_PGM (8) +#define BLOB_CPU_TYPE_RXHRSL_SL_PGM (9) +#define BLOB_CPU_TYPE_TXHRSL_HR_PGM (10) +#define BLOB_CPU_TYPE_TXHRSL_SL_PGM (11) +#define BLOB_CPU_TYPE_RXDI_VTBL0 (12) +#define BLOB_CPU_TYPE_TXDI_VTBL0 (13) +#define BLOB_CPU_TYPE_RXDI_VTBL1 (14) +#define BLOB_CPU_TYPE_TXDI_VTBL1 (15) +#define BLOB_CPU_TYPE_DUMPSPEC (32) + typedef struct siena_mc_boot_hdr_s { /* GENERATED BY scripts/genfwdef */ efx_dword_t magic; /* = SIENA_MC_BOOT_MAGIC */ efx_word_t hdr_version; /* this structure definition is version 1 */ efx_byte_t board_type; efx_byte_t firmware_version_a; efx_byte_t firmware_version_b; efx_byte_t firmware_version_c; efx_word_t checksum; /* of whole header area + firmware image */ efx_word_t firmware_version_d; - efx_word_t reserved_a[1]; /* (set to 0) */ + efx_byte_t mcfw_subtype; + efx_byte_t reserved_a[1]; /* (set to 0) */ efx_dword_t firmware_text_offset; /* offset to firmware .text */ efx_dword_t firmware_text_size; /* length of firmware .text, in bytes */ efx_dword_t firmware_data_offset; /* offset to firmware .data */ efx_dword_t firmware_data_size; /* length of firmware .data, in bytes */ - efx_dword_t reserved_b[8]; /* (set to 0) */ + efx_byte_t spi_rate; /* SPI rate for reading image, 0 is BootROM default */ + efx_byte_t spi_phase_adj; /* SPI SDO/SCL phase adjustment, 0 is default (no adj) */ + efx_word_t reserved_b[1]; /* (set to 0) */ + efx_dword_t reserved_c[7]; /* (set to 0) */ } siena_mc_boot_hdr_t; +#define SIENA_MC_BOOT_HDR_PADDING \ + (SIENA_MC_BOOT_HDR_LEN - sizeof(siena_mc_boot_hdr_t)) + #define SIENA_MC_STATIC_CONFIG_MAGIC (0xBDCF5555) #define SIENA_MC_STATIC_CONFIG_VERSION (0) typedef struct siena_mc_static_config_hdr_s { /* GENERATED BY scripts/genfwdef */ efx_dword_t magic; /* = SIENA_MC_STATIC_CONFIG_MAGIC */ efx_word_t length; /* of header area (i.e. not including VPD) */ efx_byte_t version; efx_byte_t csum; /* over header area (i.e. not including VPD) */ efx_dword_t static_vpd_offset; efx_dword_t static_vpd_length; efx_dword_t capabilities; efx_byte_t mac_addr_base[6]; efx_byte_t green_mode_cal; /* Green mode calibration result */ efx_byte_t green_mode_valid; /* Whether cal holds a valid value */ efx_word_t mac_addr_count; efx_word_t mac_addr_stride; - efx_word_t calibrated_vref; - efx_word_t adc_vref; + efx_word_t calibrated_vref; /* Vref as measured during production */ + efx_word_t adc_vref; /* Vref as read by ADC */ efx_dword_t reserved2[1]; /* (write as zero) */ efx_dword_t num_dbi_items; struct { efx_word_t addr; efx_word_t byte_enables; efx_dword_t value; } dbi[]; } siena_mc_static_config_hdr_t; #define SIENA_MC_DYNAMIC_CONFIG_MAGIC (0xBDCFDDDD) #define SIENA_MC_DYNAMIC_CONFIG_VERSION (0) typedef struct siena_mc_fw_version_s { /* GENERATED BY scripts/genfwdef */ efx_dword_t fw_subtype; efx_word_t version_w; efx_word_t version_x; efx_word_t version_y; efx_word_t version_z; } siena_mc_fw_version_t; typedef struct siena_mc_dynamic_config_hdr_s { /* GENERATED BY scripts/genfwdef */ efx_dword_t magic; /* = SIENA_MC_DYNAMIC_CONFIG_MAGIC */ efx_word_t length; /* of header area (i.e. not including VPD) */ efx_byte_t version; efx_byte_t csum; /* over header area (i.e. not including VPD) */ efx_dword_t dynamic_vpd_offset; efx_dword_t dynamic_vpd_length; efx_dword_t num_fw_version_items; siena_mc_fw_version_t fw_version[]; } siena_mc_dynamic_config_hdr_t; #define SIENA_MC_EXPROM_SINGLE_MAGIC (0xAA55) /* little-endian uint16_t */ #define SIENA_MC_EXPROM_COMBO_MAGIC (0xB0070102) /* little-endian uint32_t */ +#define SIENA_MC_EXPROM_COMBO_V2_MAGIC (0xB0070103) /* little-endian uint32_t */ typedef struct siena_mc_combo_rom_hdr_s { /* GENERATED BY scripts/genfwdef */ - efx_dword_t magic; /* = SIENA_MC_EXPROM_COMBO_MAGIC */ - efx_dword_t len1; /* length of first image */ - efx_dword_t len2; /* length of second image */ - efx_dword_t off1; /* offset of first byte to edit to combine images */ - efx_dword_t off2; /* offset of second byte to edit to combine images */ - efx_word_t infoblk0_off; /* infoblk offset */ - efx_word_t infoblk1_off; /* infoblk offset */ - efx_byte_t infoblk_len; /* length of space reserved for infoblk structures */ - efx_byte_t reserved[7]; /* (set to 0) */ + efx_dword_t magic; /* = SIENA_MC_EXPROM_COMBO_MAGIC or SIENA_MC_EXPROM_COMBO_V2_MAGIC */ + union { + struct { + efx_dword_t len1; /* length of first image */ + efx_dword_t len2; /* length of second image */ + efx_dword_t off1; /* offset of first byte to edit to combine images */ + efx_dword_t off2; /* offset of second byte to edit to combine images */ + efx_word_t infoblk0_off;/* infoblk offset */ + efx_word_t infoblk1_off;/* infoblk offset */ + efx_byte_t infoblk_len;/* length of space reserved for one infoblk structure */ + efx_byte_t reserved[7];/* (set to 0) */ + } v1; + struct { + efx_dword_t len1; /* length of first image */ + efx_dword_t len2; /* length of second image */ + efx_dword_t off1; /* offset of first byte to edit to combine images */ + efx_dword_t off2; /* offset of second byte to edit to combine images */ + efx_word_t infoblk_off;/* infoblk start offset */ + efx_word_t infoblk_count;/* infoblk count */ + efx_byte_t infoblk_len;/* length of space reserved for one infoblk structure */ + efx_byte_t reserved[7];/* (set to 0) */ + } v2; + }; } siena_mc_combo_rom_hdr_t; #pragma pack() #endif /* _SYS_SIENA_FLASH_H */ Property changes on: head/sys/dev/sfxge/common/siena_flash.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/siena_impl.h =================================================================== --- head/sys/dev/sfxge/common/siena_impl.h (revision 283513) +++ head/sys/dev/sfxge/common/siena_impl.h (revision 283514) @@ -1,479 +1,484 @@ /*- - * Copyright 2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2009-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + * * $FreeBSD$ */ #ifndef _SYS_SIENA_IMPL_H #define _SYS_SIENA_IMPL_H #include "efx.h" #include "efx_regs.h" #include "efx_mcdi.h" #include "siena_flash.h" #ifdef __cplusplus extern "C" { #endif #if EFSYS_OPT_PHY_PROPS /* START MKCONFIG GENERATED SienaPhyHeaderPropsBlock a8db1f8eb5106efd */ typedef enum siena_phy_prop_e { SIENA_PHY_NPROPS } siena_phy_prop_t; /* END MKCONFIG GENERATED SienaPhyHeaderPropsBlock */ #endif /* EFSYS_OPT_PHY_PROPS */ #define SIENA_NVRAM_CHUNK 0x80 extern __checkReturn int siena_nic_probe( __in efx_nic_t *enp); #if EFSYS_OPT_PCIE_TUNE extern __checkReturn int siena_nic_pcie_extended_sync( __in efx_nic_t *enp); #endif extern __checkReturn int siena_nic_reset( __in efx_nic_t *enp); extern __checkReturn int siena_nic_init( __in efx_nic_t *enp); #if EFSYS_OPT_DIAG extern __checkReturn int siena_nic_register_test( __in efx_nic_t *enp); #endif /* EFSYS_OPT_DIAG */ extern void siena_nic_fini( __in efx_nic_t *enp); extern void siena_nic_unprobe( __in efx_nic_t *enp); #define SIENA_SRAM_ROWS 0x12000 extern void siena_sram_init( __in efx_nic_t *enp); #if EFSYS_OPT_DIAG extern __checkReturn int siena_sram_test( __in efx_nic_t *enp, __in efx_sram_pattern_fn_t func); #endif /* EFSYS_OPT_DIAG */ +#if EFSYS_OPT_MCDI +extern __checkReturn int +siena_mcdi_init( + __in efx_nic_t *enp, + __in const efx_mcdi_transport_t *mtp); + +extern void +siena_mcdi_request_copyin( + __in efx_nic_t *enp, + __in efx_mcdi_req_t *emrp, + __in unsigned int seq, + __in boolean_t ev_cpl, + __in boolean_t new_epoch); + +extern __checkReturn boolean_t +siena_mcdi_request_poll( + __in efx_nic_t *enp); + +extern void +siena_mcdi_request_copyout( + __in efx_nic_t *enp, + __in efx_mcdi_req_t *emrp); + +extern int +siena_mcdi_poll_reboot( + __in efx_nic_t *enp); + +extern void +siena_mcdi_fini( + __in efx_nic_t *enp); + +extern __checkReturn int +siena_mcdi_fw_update_supported( + __in efx_nic_t *enp, + __out boolean_t *supportedp); + +extern __checkReturn int +siena_mcdi_macaddr_change_supported( + __in efx_nic_t *enp, + __out boolean_t *supportedp); + +#endif /* EFSYS_OPT_MCDI */ + #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD extern __checkReturn int siena_nvram_partn_size( __in efx_nic_t *enp, __in unsigned int partn, __out size_t *sizep); extern __checkReturn int siena_nvram_partn_lock( __in efx_nic_t *enp, __in unsigned int partn); extern __checkReturn int siena_nvram_partn_read( __in efx_nic_t *enp, __in unsigned int partn, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size); extern __checkReturn int siena_nvram_partn_erase( __in efx_nic_t *enp, __in unsigned int partn, __in unsigned int offset, __in size_t size); extern __checkReturn int siena_nvram_partn_write( __in efx_nic_t *enp, __in unsigned int partn, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size); extern void siena_nvram_partn_unlock( __in efx_nic_t *enp, __in unsigned int partn); extern __checkReturn int siena_nvram_get_dynamic_cfg( __in efx_nic_t *enp, __in unsigned int index, __in boolean_t vpd, __out siena_mc_dynamic_config_hdr_t **dcfgp, __out size_t *sizep); #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ #if EFSYS_OPT_NVRAM #if EFSYS_OPT_DIAG extern __checkReturn int siena_nvram_test( __in efx_nic_t *enp); #endif /* EFSYS_OPT_DIAG */ extern __checkReturn int siena_nvram_size( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out size_t *sizep); extern __checkReturn int +siena_nvram_get_subtype( + __in efx_nic_t *enp, + __in unsigned int partn, + __out uint32_t *subtypep); + +extern __checkReturn int siena_nvram_get_version( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out uint32_t *subtypep, __out_ecount(4) uint16_t version[4]); extern __checkReturn int siena_nvram_rw_start( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out size_t *pref_chunkp); extern __checkReturn int siena_nvram_read_chunk( __in efx_nic_t *enp, __in efx_nvram_type_t type, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size); extern __checkReturn int siena_nvram_erase( __in efx_nic_t *enp, __in efx_nvram_type_t type); extern __checkReturn int siena_nvram_write_chunk( __in efx_nic_t *enp, __in efx_nvram_type_t type, __in unsigned int offset, __in_bcount(size) caddr_t data, __in size_t size); extern void siena_nvram_rw_finish( __in efx_nic_t *enp, __in efx_nvram_type_t type); extern __checkReturn int siena_nvram_set_version( __in efx_nic_t *enp, __in efx_nvram_type_t type, - __out uint16_t version[4]); + __in_ecount(4) uint16_t version[4]); #endif /* EFSYS_OPT_NVRAM */ #if EFSYS_OPT_VPD extern __checkReturn int siena_vpd_init( __in efx_nic_t *enp); extern __checkReturn int siena_vpd_size( __in efx_nic_t *enp, __out size_t *sizep); extern __checkReturn int siena_vpd_read( __in efx_nic_t *enp, __out_bcount(size) caddr_t data, __in size_t size); extern __checkReturn int siena_vpd_verify( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size); extern __checkReturn int siena_vpd_reinit( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size); extern __checkReturn int siena_vpd_get( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size, __inout efx_vpd_value_t *evvp); extern __checkReturn int siena_vpd_set( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size, __in efx_vpd_value_t *evvp); extern __checkReturn int siena_vpd_next( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size, __out efx_vpd_value_t *evvp, __inout unsigned int *contp); extern __checkReturn int siena_vpd_write( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size); extern void siena_vpd_fini( __in efx_nic_t *enp); #endif /* EFSYS_OPT_VPD */ typedef struct siena_link_state_s { uint32_t sls_adv_cap_mask; uint32_t sls_lp_cap_mask; unsigned int sls_fcntl; efx_link_mode_t sls_link_mode; #if EFSYS_OPT_LOOPBACK efx_loopback_type_t sls_loopback; #endif boolean_t sls_mac_up; } siena_link_state_t; extern void siena_phy_link_ev( __in efx_nic_t *enp, __in efx_qword_t *eqp, __out efx_link_mode_t *link_modep); extern __checkReturn int siena_phy_get_link( __in efx_nic_t *enp, __out siena_link_state_t *slsp); extern __checkReturn int siena_phy_power( __in efx_nic_t *enp, __in boolean_t on); extern __checkReturn int siena_phy_reconfigure( __in efx_nic_t *enp); extern __checkReturn int siena_phy_verify( __in efx_nic_t *enp); extern __checkReturn int siena_phy_oui_get( __in efx_nic_t *enp, __out uint32_t *ouip); #if EFSYS_OPT_PHY_STATS extern void siena_phy_decode_stats( __in efx_nic_t *enp, __in uint32_t vmask, __in_opt efsys_mem_t *esmp, __out_opt uint64_t *smaskp, __out_ecount_opt(EFX_PHY_NSTATS) uint32_t *stat); extern __checkReturn int siena_phy_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, __out_ecount(EFX_PHY_NSTATS) uint32_t *stat); #endif /* EFSYS_OPT_PHY_STATS */ #if EFSYS_OPT_PHY_PROPS #if EFSYS_OPT_NAMES -extern const char __cs * +extern const char * siena_phy_prop_name( __in efx_nic_t *enp, __in unsigned int id); #endif /* EFSYS_OPT_NAMES */ extern __checkReturn int siena_phy_prop_get( __in efx_nic_t *enp, __in unsigned int id, __in uint32_t flags, __out uint32_t *valp); extern __checkReturn int siena_phy_prop_set( __in efx_nic_t *enp, __in unsigned int id, __in uint32_t val); #endif /* EFSYS_OPT_PHY_PROPS */ -#if EFSYS_OPT_PHY_BIST +#if EFSYS_OPT_BIST extern __checkReturn int siena_phy_bist_start( __in efx_nic_t *enp, - __in efx_phy_bist_type_t type); + __in efx_bist_type_t type); extern __checkReturn int siena_phy_bist_poll( __in efx_nic_t *enp, - __in efx_phy_bist_type_t type, - __out efx_phy_bist_result_t *resultp, + __in efx_bist_type_t type, + __out efx_bist_result_t *resultp, __out_opt __drv_when(count > 0, __notnull) uint32_t *value_maskp, __out_ecount_opt(count) __drv_when(count > 0, __notnull) unsigned long *valuesp, __in size_t count); extern void siena_phy_bist_stop( __in efx_nic_t *enp, - __in efx_phy_bist_type_t type); + __in efx_bist_type_t type); -#endif /* EFSYS_OPT_PHY_BIST */ +#endif /* EFSYS_OPT_BIST */ extern __checkReturn int siena_mac_poll( __in efx_nic_t *enp, __out efx_link_mode_t *link_modep); extern __checkReturn int siena_mac_up( __in efx_nic_t *enp, __out boolean_t *mac_upp); extern __checkReturn int siena_mac_reconfigure( __in efx_nic_t *enp); #if EFSYS_OPT_LOOPBACK extern __checkReturn int siena_mac_loopback_set( __in efx_nic_t *enp, __in efx_link_mode_t link_mode, __in efx_loopback_type_t loopback_type); #endif /* EFSYS_OPT_LOOPBACK */ #if EFSYS_OPT_MAC_STATS extern __checkReturn int -siena_mac_stats_clear( - __in efx_nic_t *enp); - -extern __checkReturn int -siena_mac_stats_upload( - __in efx_nic_t *enp, - __in efsys_mem_t *esmp); - -extern __checkReturn int -siena_mac_stats_periodic( - __in efx_nic_t *enp, - __in efsys_mem_t *esmp, - __in uint16_t period_ms, - __in boolean_t events); - -extern __checkReturn int siena_mac_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, __out_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, __out_opt uint32_t *generationp); #endif /* EFSYS_OPT_MAC_STATS */ - -extern __checkReturn int -siena_mon_reset( - __in efx_nic_t *enp); - -extern __checkReturn int -siena_mon_reconfigure( - __in efx_nic_t *enp); - -#if EFSYS_OPT_MON_STATS - -extern void -siena_mon_decode_stats( - __in efx_nic_t *enp, - __in uint32_t dmask, - __in_opt efsys_mem_t *esmp, - __out_opt uint32_t *vmaskp, - __out_ecount_opt(EFX_MON_NSTATS) efx_mon_stat_value_t *value); - -extern __checkReturn int -siena_mon_ev( - __in efx_nic_t *enp, - __in efx_qword_t *eqp, - __out efx_mon_stat_t *idp, - __out efx_mon_stat_value_t *valuep); - -extern __checkReturn int -siena_mon_stats_update( - __in efx_nic_t *enp, - __in efsys_mem_t *esmp, - __out_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); - -#endif /* EFSYS_OPT_MON_STATS */ #ifdef __cplusplus } #endif #endif /* _SYS_SIENA_IMPL_H */ Property changes on: head/sys/dev/sfxge/common/siena_impl.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/siena_mac.c =================================================================== --- head/sys/dev/sfxge/common/siena_mac.c (revision 283513) +++ head/sys/dev/sfxge/common/siena_mac.c (revision 283514) @@ -1,550 +1,436 @@ /*- - * Copyright 2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2009-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include "efsys.h" #include "efx.h" #include "efx_impl.h" #if EFSYS_OPT_SIENA __checkReturn int siena_mac_poll( __in efx_nic_t *enp, __out efx_link_mode_t *link_modep) { efx_port_t *epp = &(enp->en_port); siena_link_state_t sls; int rc; if ((rc = siena_phy_get_link(enp, &sls)) != 0) goto fail1; epp->ep_adv_cap_mask = sls.sls_adv_cap_mask; epp->ep_fcntl = sls.sls_fcntl; *link_modep = sls.sls_link_mode; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); *link_modep = EFX_LINK_UNKNOWN; return (rc); } __checkReturn int siena_mac_up( __in efx_nic_t *enp, __out boolean_t *mac_upp) { siena_link_state_t sls; int rc; /* * Because Siena doesn't *require* polling, we can't rely on * siena_mac_poll() being executed to populate epp->ep_mac_up. */ if ((rc = siena_phy_get_link(enp, &sls)) != 0) goto fail1; *mac_upp = sls.sls_mac_up; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_mac_reconfigure( __in efx_nic_t *enp) { efx_port_t *epp = &(enp->en_port); - uint8_t payload[MAX(MC_CMD_SET_MAC_IN_LEN, - MC_CMD_SET_MCAST_HASH_IN_LEN)]; + efx_oword_t multicast_hash[2]; efx_mcdi_req_t req; + uint8_t payload[MAX(MAX(MC_CMD_SET_MAC_IN_LEN, + MC_CMD_SET_MAC_OUT_LEN), + MAX(MC_CMD_SET_MCAST_HASH_IN_LEN, + MC_CMD_SET_MCAST_HASH_OUT_LEN))]; unsigned int fcntl; int rc; + (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_SET_MAC; req.emr_in_buf = payload; req.emr_in_length = MC_CMD_SET_MAC_IN_LEN; - EFX_STATIC_ASSERT(MC_CMD_SET_MAC_OUT_LEN == 0); - req.emr_out_buf = NULL; - req.emr_out_length = 0; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_SET_MAC_OUT_LEN; MCDI_IN_SET_DWORD(req, SET_MAC_IN_MTU, epp->ep_mac_pdu); MCDI_IN_SET_DWORD(req, SET_MAC_IN_DRAIN, epp->ep_mac_drain ? 1 : 0); EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t, SET_MAC_IN_ADDR), epp->ep_mac_addr); MCDI_IN_POPULATE_DWORD_2(req, SET_MAC_IN_REJECT, - SET_MAC_IN_REJECT_UNCST, !epp->ep_unicst, - SET_MAC_IN_REJECT_BRDCST, !epp->ep_brdcst); + SET_MAC_IN_REJECT_UNCST, !epp->ep_all_unicst, + SET_MAC_IN_REJECT_BRDCST, !epp->ep_brdcst); if (epp->ep_fcntl_autoneg) /* efx_fcntl_set() has already set the phy capabilities */ fcntl = MC_CMD_FCNTL_AUTO; else if (epp->ep_fcntl & EFX_FCNTL_RESPOND) fcntl = (epp->ep_fcntl & EFX_FCNTL_GENERATE) ? MC_CMD_FCNTL_BIDIR : MC_CMD_FCNTL_RESPOND; else fcntl = MC_CMD_FCNTL_OFF; MCDI_IN_SET_DWORD(req, SET_MAC_IN_FCNTL, fcntl); efx_mcdi_execute(enp, &req); if (req.emr_rc != 0) { rc = req.emr_rc; goto fail1; } - /* Push multicast hash. Set the broadcast bit (0xff) appropriately */ + /* Push multicast hash */ + + if (epp->ep_all_mulcst) { + /* A hash matching all multicast is all 1s */ + EFX_SET_OWORD(multicast_hash[0]); + EFX_SET_OWORD(multicast_hash[1]); + } else if (epp->ep_mulcst) { + /* Use the hash set by the multicast list */ + multicast_hash[0] = epp->ep_multicst_hash[0]; + multicast_hash[1] = epp->ep_multicst_hash[1]; + } else { + /* A hash matching no traffic is simply 0 */ + EFX_ZERO_OWORD(multicast_hash[0]); + EFX_ZERO_OWORD(multicast_hash[1]); + } + + /* + * Broadcast packets go through the multicast hash filter. + * The IEEE 802.3 CRC32 of the broadcast address is 0xbe2612ff + * so we always add bit 0xff to the mask (bit 0x7f in the + * second octword). + */ + if (epp->ep_brdcst) + EFX_SET_OWORD_BIT(multicast_hash[1], 0x7f); + + (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_SET_MCAST_HASH; req.emr_in_buf = payload; req.emr_in_length = MC_CMD_SET_MCAST_HASH_IN_LEN; - EFX_STATIC_ASSERT(MC_CMD_SET_MCAST_HASH_OUT_LEN == 0); - req.emr_out_buf = NULL; - req.emr_out_length = 0; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_SET_MCAST_HASH_OUT_LEN; memcpy(MCDI_IN2(req, uint8_t, SET_MCAST_HASH_IN_HASH0), - epp->ep_multicst_hash, sizeof (epp->ep_multicst_hash)); - if (epp->ep_brdcst) - EFX_SET_OWORD_BIT(*MCDI_IN2(req, efx_oword_t, - SET_MCAST_HASH_IN_HASH1), 0x7f); + multicast_hash, sizeof (multicast_hash)); efx_mcdi_execute(enp, &req); if (req.emr_rc != 0) { rc = req.emr_rc; goto fail2; } return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } #if EFSYS_OPT_LOOPBACK __checkReturn int siena_mac_loopback_set( __in efx_nic_t *enp, __in efx_link_mode_t link_mode, __in efx_loopback_type_t loopback_type) { efx_port_t *epp = &(enp->en_port); efx_phy_ops_t *epop = epp->ep_epop; efx_loopback_type_t old_loopback_type; efx_link_mode_t old_loopback_link_mode; int rc; /* The PHY object handles this on Siena */ old_loopback_type = epp->ep_loopback_type; old_loopback_link_mode = epp->ep_loopback_link_mode; epp->ep_loopback_type = loopback_type; epp->ep_loopback_link_mode = link_mode; if ((rc = epop->epo_reconfigure(enp)) != 0) goto fail1; return (0); fail1: EFSYS_PROBE(fail2); epp->ep_loopback_type = old_loopback_type; epp->ep_loopback_link_mode = old_loopback_link_mode; return (rc); } #endif /* EFSYS_OPT_LOOPBACK */ #if EFSYS_OPT_MAC_STATS - __checkReturn int -siena_mac_stats_clear( - __in efx_nic_t *enp) -{ - uint8_t payload[MC_CMD_MAC_STATS_IN_LEN]; - efx_mcdi_req_t req; - int rc; - - req.emr_cmd = MC_CMD_MAC_STATS; - req.emr_in_buf = payload; - req.emr_in_length = sizeof (payload); - EFX_STATIC_ASSERT(MC_CMD_MAC_STATS_OUT_DMA_LEN == 0); - req.emr_out_buf = NULL; - req.emr_out_length = 0; - - MCDI_IN_POPULATE_DWORD_3(req, MAC_STATS_IN_CMD, - MAC_STATS_IN_DMA, 0, - MAC_STATS_IN_CLEAR, 1, - MAC_STATS_IN_PERIODIC_CHANGE, 0); - - efx_mcdi_execute(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; - goto fail1; - } - - return (0); - -fail1: - EFSYS_PROBE1(fail1, int, rc); - - return (rc); -} - - __checkReturn int -siena_mac_stats_upload( - __in efx_nic_t *enp, - __in efsys_mem_t *esmp) -{ - uint8_t payload[MC_CMD_MAC_STATS_IN_LEN]; - efx_mcdi_req_t req; - size_t bytes; - int rc; - - EFX_STATIC_ASSERT(MC_CMD_MAC_NSTATS * sizeof (uint64_t) <= - EFX_MAC_STATS_SIZE); - - bytes = MC_CMD_MAC_NSTATS * sizeof (uint64_t); - - req.emr_cmd = MC_CMD_MAC_STATS; - req.emr_in_buf = payload; - req.emr_in_length = sizeof (payload); - EFX_STATIC_ASSERT(MC_CMD_MAC_STATS_OUT_DMA_LEN == 0); - req.emr_out_buf = NULL; - req.emr_out_length = 0; - - MCDI_IN_SET_DWORD(req, MAC_STATS_IN_DMA_ADDR_LO, - EFSYS_MEM_ADDR(esmp) & 0xffffffff); - MCDI_IN_SET_DWORD(req, MAC_STATS_IN_DMA_ADDR_HI, - EFSYS_MEM_ADDR(esmp) >> 32); - MCDI_IN_SET_DWORD(req, MAC_STATS_IN_DMA_LEN, bytes); - - /* - * The MC DMAs aggregate statistics for our convinience, so we can - * avoid having to pull the statistics buffer into the cache to - * maintain cumulative statistics. - */ - MCDI_IN_POPULATE_DWORD_3(req, MAC_STATS_IN_CMD, - MAC_STATS_IN_DMA, 1, - MAC_STATS_IN_CLEAR, 0, - MAC_STATS_IN_PERIODIC_CHANGE, 0); - - efx_mcdi_execute(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; - goto fail1; - } - - return (0); - -fail1: - EFSYS_PROBE1(fail1, int, rc); - - return (rc); -} - - __checkReturn int -siena_mac_stats_periodic( - __in efx_nic_t *enp, - __in efsys_mem_t *esmp, - __in uint16_t period, - __in boolean_t events) -{ - uint8_t payload[MC_CMD_MAC_STATS_IN_LEN]; - efx_mcdi_req_t req; - size_t bytes; - int rc; - - bytes = MC_CMD_MAC_NSTATS * sizeof (uint64_t); - - req.emr_cmd = MC_CMD_MAC_STATS; - req.emr_in_buf = payload; - req.emr_in_length = sizeof (payload); - EFX_STATIC_ASSERT(MC_CMD_MAC_STATS_OUT_DMA_LEN == 0); - req.emr_out_buf = NULL; - req.emr_out_length = 0; - - MCDI_IN_SET_DWORD(req, MAC_STATS_IN_DMA_ADDR_LO, - EFSYS_MEM_ADDR(esmp) & 0xffffffff); - MCDI_IN_SET_DWORD(req, MAC_STATS_IN_DMA_ADDR_HI, - EFSYS_MEM_ADDR(esmp) >> 32); - MCDI_IN_SET_DWORD(req, MAC_STATS_IN_DMA_LEN, bytes); - - /* - * The MC DMAs aggregate statistics for our convinience, so we can - * avoid having to pull the statistics buffer into the cache to - * maintain cumulative statistics. - */ - MCDI_IN_POPULATE_DWORD_6(req, MAC_STATS_IN_CMD, - MAC_STATS_IN_DMA, 0, - MAC_STATS_IN_CLEAR, 0, - MAC_STATS_IN_PERIODIC_CHANGE, 1, - MAC_STATS_IN_PERIODIC_ENABLE, period ? 1 : 0, - MAC_STATS_IN_PERIODIC_NOEVENT, events ? 0 : 1, - MAC_STATS_IN_PERIOD_MS, period); - - efx_mcdi_execute(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; - goto fail1; - } - - return (0); - -fail1: - EFSYS_PROBE1(fail1, int, rc); - - return (rc); -} - - #define SIENA_MAC_STAT_READ(_esmp, _field, _eqp) \ EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp) __checkReturn int siena_mac_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, __out_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, __out_opt uint32_t *generationp) { - efx_qword_t rx_pkts; efx_qword_t value; efx_qword_t generation_start; efx_qword_t generation_end; _NOTE(ARGUNUSED(enp)) /* Read END first so we don't race with the MC */ + EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFX_MAC_STATS_SIZE); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_END, &generation_end); EFSYS_MEM_READ_BARRIER(); /* TX */ SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_CONTROL_PKTS, &value); EFSYS_STAT_SUBR_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PAUSE_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PAUSE_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_UNICAST_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_UNICST_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTICAST_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULTICST_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BROADCAST_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_BRDCST_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BYTES, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_OCTETS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LT64_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_64_PKTS, &value); - EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value); + EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_65_TO_127_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_65_TO_127_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_128_TO_255_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_128_TO_255_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_256_TO_511_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_256_TO_511_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_512_TO_1023_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_512_TO_1023_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_1024_TO_15XX_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_1024_TO_15XX_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_GTJUMBO_PKTS, &value); EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BAD_FCS_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_ERRORS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_SGL_COL_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULT_COL_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_COL_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LATE_COLLISION_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LATE_COL_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_DEFERRED_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_DEF_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_DEF_PKTS]), &value); /* RX */ - SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BYTES, &rx_pkts); - EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_OCTETS]), &rx_pkts); + SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BYTES, &value); + EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_OCTETS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNICAST_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_UNICST_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MULTICAST_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MULTICST_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BROADCAST_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_BRDCST_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PAUSE_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PAUSE_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNDERSIZE_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_64_PKTS, &value); EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_65_TO_127_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_65_TO_127_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_128_TO_255_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_128_TO_255_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_256_TO_511_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_256_TO_511_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_512_TO_1023_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_512_TO_1023_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_1024_TO_15XX_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_1024_TO_15XX_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_GTJUMBO_PKTS, &value); EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BAD_FCS_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FCS_ERRORS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_OVERFLOW_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_DROP_EVENTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_FALSE_CARRIER_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FALSE_CARRIER_ERRORS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_SYMBOL_ERRORS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_ALIGN_ERROR_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_ALIGN_ERRORS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_INTERNAL_ERRORS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_JABBER_PKTS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_JABBER_PKTS]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_CHAR_ERR, &value); EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_CHAR_ERR]), &(value.eq_dword[0])); EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_CHAR_ERR]), &(value.eq_dword[1])); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_CHAR_ERR, &value); EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_CHAR_ERR]), &(value.eq_dword[0])); EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_CHAR_ERR]), &(value.eq_dword[1])); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_DISP_ERR, &value); EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_DISP_ERR]), &(value.eq_dword[0])); EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_DISP_ERR]), &(value.eq_dword[1])); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_DISP_ERR, &value); EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_DISP_ERR]), &(value.eq_dword[0])); EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_DISP_ERR]), &(value.eq_dword[1])); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MATCH_FAULT, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MATCH_FAULT]), &value); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_NODESC_DROPS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_NODESC_DROP_CNT]), &value); + EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFX_MAC_STATS_SIZE); EFSYS_MEM_READ_BARRIER(); SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_START, &generation_start); /* Check that we didn't read the stats in the middle of a DMA */ /* Not a good enough check ? */ if (memcmp(&generation_start, &generation_end, sizeof (generation_start))) return (EAGAIN); if (generationp) *generationp = EFX_QWORD_FIELD(generation_start, EFX_DWORD_0); return (0); } #endif /* EFSYS_OPT_MAC_STATS */ #endif /* EFSYS_OPT_SIENA */ Property changes on: head/sys/dev/sfxge/common/siena_mac.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/siena_mcdi.c =================================================================== --- head/sys/dev/sfxge/common/siena_mcdi.c (nonexistent) +++ head/sys/dev/sfxge/common/siena_mcdi.c (revision 283514) @@ -0,0 +1,354 @@ +/*- + * Copyright (c) 2012-2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "efsys.h" +#include "efx.h" +#include "efx_impl.h" + +#if EFSYS_OPT_SIENA && EFSYS_OPT_MCDI + +#define SIENA_MCDI_PDU(_emip) \ + (((emip)->emi_port == 1) \ + ? MC_SMEM_P0_PDU_OFST >> 2 \ + : MC_SMEM_P1_PDU_OFST >> 2) + +#define SIENA_MCDI_DOORBELL(_emip) \ + (((emip)->emi_port == 1) \ + ? MC_SMEM_P0_DOORBELL_OFST >> 2 \ + : MC_SMEM_P1_DOORBELL_OFST >> 2) + +#define SIENA_MCDI_STATUS(_emip) \ + (((emip)->emi_port == 1) \ + ? MC_SMEM_P0_STATUS_OFST >> 2 \ + : MC_SMEM_P1_STATUS_OFST >> 2) + + + void +siena_mcdi_request_copyin( + __in efx_nic_t *enp, + __in efx_mcdi_req_t *emrp, + __in unsigned int seq, + __in boolean_t ev_cpl, + __in boolean_t new_epoch) +{ + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + efx_dword_t dword; + unsigned int xflags; + unsigned int pdur; + unsigned int dbr; + unsigned int pos; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); + _NOTE(ARGUNUSED(new_epoch)) + + EFSYS_ASSERT(emip->emi_port == 1 || emip->emi_port == 2); + pdur = SIENA_MCDI_PDU(emip); + dbr = SIENA_MCDI_DOORBELL(emip); + + xflags = 0; + if (ev_cpl) + xflags |= MCDI_HEADER_XFLAGS_EVREQ; + + /* Construct the header in shared memory */ + EFX_POPULATE_DWORD_6(dword, + MCDI_HEADER_CODE, emrp->emr_cmd, + MCDI_HEADER_RESYNC, 1, + MCDI_HEADER_DATALEN, emrp->emr_in_length, + MCDI_HEADER_SEQ, seq, + MCDI_HEADER_RESPONSE, 0, + MCDI_HEADER_XFLAGS, xflags); + EFX_BAR_TBL_WRITED(enp, FR_CZ_MC_TREG_SMEM, pdur, &dword, B_TRUE); + + for (pos = 0; pos < emrp->emr_in_length; pos += sizeof (efx_dword_t)) { + memcpy(&dword, MCDI_IN(*emrp, efx_dword_t, pos), + MIN(sizeof (dword), emrp->emr_in_length - pos)); + EFX_BAR_TBL_WRITED(enp, FR_CZ_MC_TREG_SMEM, + pdur + 1 + (pos >> 2), &dword, B_FALSE); + } + + /* Ring the doorbell */ + EFX_POPULATE_DWORD_1(dword, EFX_DWORD_0, 0xd004be11); + EFX_BAR_TBL_WRITED(enp, FR_CZ_MC_TREG_SMEM, dbr, &dword, B_FALSE); +} + + void +siena_mcdi_request_copyout( + __in efx_nic_t *enp, + __in efx_mcdi_req_t *emrp) +{ + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + unsigned int pos; + unsigned int pdur; + efx_dword_t data; + + pdur = SIENA_MCDI_PDU(emip); + + /* Copy payload out if caller supplied buffer */ + if (emrp->emr_out_buf != NULL) { + size_t bytes = MIN(emrp->emr_out_length_used, + emrp->emr_out_length); + for (pos = 0; pos < bytes; pos += sizeof (efx_dword_t)) { + EFX_BAR_TBL_READD(enp, FR_CZ_MC_TREG_SMEM, + pdur + 1 + (pos >> 2), &data, B_FALSE); + memcpy(MCDI_OUT(*emrp, efx_dword_t, pos), &data, + MIN(sizeof (data), bytes - pos)); + } + } +} + + int +siena_mcdi_poll_reboot( + __in efx_nic_t *enp) +{ +#ifndef EFX_GRACEFUL_MC_REBOOT + /* + * This function is not being used properly. + * Until its callers are fixed, it should always return 0. + */ + _NOTE(ARGUNUSED(enp)) + return (0); +#else + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + unsigned int rebootr; + efx_dword_t dword; + uint32_t value; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); + EFSYS_ASSERT(emip->emi_port == 1 || emip->emi_port == 2); + rebootr = SIENA_MCDI_STATUS(emip); + + EFX_BAR_TBL_READD(enp, FR_CZ_MC_TREG_SMEM, rebootr, &dword, B_FALSE); + value = EFX_DWORD_FIELD(dword, EFX_DWORD_0); + + if (value == 0) + return (0); + + EFX_ZERO_DWORD(dword); + EFX_BAR_TBL_WRITED(enp, FR_CZ_MC_TREG_SMEM, rebootr, &dword, B_FALSE); + + if (value == MC_STATUS_DWORD_ASSERT) + return (EINTR); + else + return (EIO); +#endif +} + + __checkReturn boolean_t +siena_mcdi_request_poll( + __in efx_nic_t *enp) +{ + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + efx_mcdi_req_t *emrp; + efx_dword_t dword; + unsigned int pdur; + unsigned int seq; + unsigned int length; + int state; + int rc; + + EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); + + /* Serialise against post-watchdog efx_mcdi_ev* */ + EFSYS_LOCK(enp->en_eslp, state); + + EFSYS_ASSERT(emip->emi_pending_req != NULL); + EFSYS_ASSERT(!emip->emi_ev_cpl); + emrp = emip->emi_pending_req; + + /* Check for reboot atomically w.r.t efx_mcdi_request_start */ + if (emip->emi_poll_cnt++ == 0) { + if ((rc = siena_mcdi_poll_reboot(enp)) != 0) { + emip->emi_pending_req = NULL; + EFSYS_UNLOCK(enp->en_eslp, state); + + goto fail1; + } + } + + EFSYS_ASSERT(emip->emi_port == 1 || emip->emi_port == 2); + pdur = SIENA_MCDI_PDU(emip); + + /* Read the command header */ + EFX_BAR_TBL_READD(enp, FR_CZ_MC_TREG_SMEM, pdur, &dword, B_FALSE); + if (EFX_DWORD_FIELD(dword, MCDI_HEADER_RESPONSE) == 0) { + EFSYS_UNLOCK(enp->en_eslp, state); + return (B_FALSE); + } + + /* Request complete */ + emip->emi_pending_req = NULL; + seq = (emip->emi_seq - 1) & EFX_MASK32(MCDI_HEADER_SEQ); + + /* Check for synchronous reboot */ + if (EFX_DWORD_FIELD(dword, MCDI_HEADER_ERROR) != 0 && + EFX_DWORD_FIELD(dword, MCDI_HEADER_DATALEN) == 0) { + /* Consume status word */ + EFSYS_SPIN(EFX_MCDI_STATUS_SLEEP_US); + siena_mcdi_poll_reboot(enp); + EFSYS_UNLOCK(enp->en_eslp, state); + rc = EIO; + goto fail2; + } + + EFSYS_UNLOCK(enp->en_eslp, state); + + /* Check that the returned data is consistent */ + if (EFX_DWORD_FIELD(dword, MCDI_HEADER_CODE) != emrp->emr_cmd || + EFX_DWORD_FIELD(dword, MCDI_HEADER_SEQ) != seq) { + /* Response is for a different request */ + rc = EIO; + goto fail3; + } + + length = EFX_DWORD_FIELD(dword, MCDI_HEADER_DATALEN); + if (EFX_DWORD_FIELD(dword, MCDI_HEADER_ERROR)) { + efx_dword_t errdword; + int errcode; + + EFSYS_ASSERT3U(length, ==, 4); + EFX_BAR_TBL_READD(enp, FR_CZ_MC_TREG_SMEM, + pdur + 1 + (MC_CMD_ERR_CODE_OFST >> 2), + &errdword, B_FALSE); + errcode = EFX_DWORD_FIELD(errdword, EFX_DWORD_0); + rc = efx_mcdi_request_errcode(errcode); + if (!emrp->emr_quiet) { + EFSYS_PROBE2(mcdi_err, int, emrp->emr_cmd, + int, errcode); + } + goto fail4; + + } else { + emrp->emr_out_length_used = length; + emrp->emr_rc = 0; + siena_mcdi_request_copyout(enp, emrp); + } + + goto out; + +fail4: + if (!emrp->emr_quiet) + EFSYS_PROBE(fail4); +fail3: + if (!emrp->emr_quiet) + EFSYS_PROBE(fail3); +fail2: + if (!emrp->emr_quiet) + EFSYS_PROBE(fail2); +fail1: + if (!emrp->emr_quiet) + EFSYS_PROBE1(fail1, int, rc); + + /* Fill out error state */ + emrp->emr_rc = rc; + emrp->emr_out_length_used = 0; + + /* Reboot/Assertion */ + if (rc == EIO || rc == EINTR) + efx_mcdi_raise_exception(enp, emrp, rc); + +out: + return (B_TRUE); +} + + __checkReturn int +siena_mcdi_init( + __in efx_nic_t *enp, + __in const efx_mcdi_transport_t *mtp) +{ + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + efx_oword_t oword; + unsigned int portnum; + int rc; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); + + /* Determine the port number to use for MCDI */ + EFX_BAR_READO(enp, FR_AZ_CS_DEBUG_REG, &oword); + portnum = EFX_OWORD_FIELD(oword, FRF_CZ_CS_PORT_NUM); + + if (portnum == 0) { + /* Presumably booted from ROM; only MCDI port 1 will work */ + emip->emi_port = 1; + } else if (portnum <= 2) { + emip->emi_port = portnum; + } else { + rc = EINVAL; + goto fail1; + } + + /* + * Wipe the atomic reboot status so subsequent MCDI requests succeed. + * BOOT_STATUS is preserved so eno_nic_probe() can boot out of the + * assertion handler. + */ + (void) siena_mcdi_poll_reboot(enp); + + return (0); + +fail1: + EFSYS_PROBE1(fail1, int, rc); + + return (rc); +} + + void +siena_mcdi_fini( + __in efx_nic_t *enp) +{ +} + + __checkReturn int +siena_mcdi_fw_update_supported( + __in efx_nic_t *enp, + __out boolean_t *supportedp) +{ + EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); + + *supportedp = B_TRUE; + + return (0); +} + + __checkReturn int +siena_mcdi_macaddr_change_supported( + __in efx_nic_t *enp, + __out boolean_t *supportedp) +{ + EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); + + *supportedp = B_TRUE; + + return (0); +} + +#endif /* EFSYS_OPT_SIENA && EFSYS_OPT_MCDI */ Property changes on: head/sys/dev/sfxge/common/siena_mcdi.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/siena_nic.c =================================================================== --- head/sys/dev/sfxge/common/siena_nic.c (revision 283513) +++ head/sys/dev/sfxge/common/siena_nic.c (revision 283514) @@ -1,988 +1,581 @@ /*- - * Copyright 2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2009-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include "efsys.h" #include "efx.h" #include "efx_impl.h" +#include "mcdi_mon.h" #if EFSYS_OPT_SIENA static __checkReturn int siena_nic_get_partn_mask( __in efx_nic_t *enp, __out unsigned int *maskp) { efx_mcdi_req_t req; - uint8_t outbuf[MC_CMD_NVRAM_TYPES_OUT_LEN]; + uint8_t payload[MAX(MC_CMD_NVRAM_TYPES_IN_LEN, + MC_CMD_NVRAM_TYPES_OUT_LEN)]; int rc; + (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_NVRAM_TYPES; - EFX_STATIC_ASSERT(MC_CMD_NVRAM_TYPES_IN_LEN == 0); - req.emr_in_buf = NULL; - req.emr_in_length = 0; - req.emr_out_buf = outbuf; - req.emr_out_length = sizeof (outbuf); + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_NVRAM_TYPES_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_NVRAM_TYPES_OUT_LEN; efx_mcdi_execute(enp, &req); if (req.emr_rc != 0) { rc = req.emr_rc; goto fail1; } if (req.emr_out_length_used < MC_CMD_NVRAM_TYPES_OUT_LEN) { rc = EMSGSIZE; goto fail2; } *maskp = MCDI_OUT_DWORD(req, NVRAM_TYPES_OUT_TYPES); return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } -static __checkReturn int -siena_nic_exit_assertion_handler( - __in efx_nic_t *enp) -{ - efx_mcdi_req_t req; - uint8_t payload[MC_CMD_REBOOT_IN_LEN]; - int rc; - - req.emr_cmd = MC_CMD_REBOOT; - req.emr_in_buf = payload; - req.emr_in_length = MC_CMD_REBOOT_IN_LEN; - EFX_STATIC_ASSERT(MC_CMD_REBOOT_OUT_LEN == 0); - req.emr_out_buf = NULL; - req.emr_out_length = 0; - - MCDI_IN_SET_DWORD(req, REBOOT_IN_FLAGS, - MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION); - - efx_mcdi_execute(enp, &req); - - if (req.emr_rc != 0 && req.emr_rc != EIO) { - rc = req.emr_rc; - goto fail1; - } - - return (0); - -fail1: - EFSYS_PROBE1(fail1, int, rc); - - return (rc); -} - -static __checkReturn int -siena_nic_read_assertion( - __in efx_nic_t *enp) -{ - efx_mcdi_req_t req; - uint8_t payload[MAX(MC_CMD_GET_ASSERTS_IN_LEN, - MC_CMD_GET_ASSERTS_OUT_LEN)]; - const char *reason; - unsigned int flags; - unsigned int index; - unsigned int ofst; - int retry; - int rc; - - /* - * Before we attempt to chat to the MC, we should verify that the MC - * isn't in it's assertion handler, either due to a previous reboot, - * or because we're reinitializing due to an eec_exception(). - * - * Use GET_ASSERTS to read any assertion state that may be present. - * Retry this command twice. Once because a boot-time assertion failure - * might cause the 1st MCDI request to fail. And once again because - * we might race with siena_nic_exit_assertion_handler() running on the - * other port. - */ - retry = 2; - do { - req.emr_cmd = MC_CMD_GET_ASSERTS; - req.emr_in_buf = payload; - req.emr_in_length = MC_CMD_GET_ASSERTS_IN_LEN; - req.emr_out_buf = payload; - req.emr_out_length = MC_CMD_GET_ASSERTS_OUT_LEN; - - MCDI_IN_SET_DWORD(req, GET_ASSERTS_IN_CLEAR, 1); - efx_mcdi_execute(enp, &req); - - } while ((req.emr_rc == EINTR || req.emr_rc == EIO) && retry-- > 0); - - if (req.emr_rc != 0) { - rc = req.emr_rc; - goto fail1; - } - - if (req.emr_out_length_used < MC_CMD_GET_ASSERTS_OUT_LEN) { - rc = EMSGSIZE; - goto fail2; - } - - /* Print out any assertion state recorded */ - flags = MCDI_OUT_DWORD(req, GET_ASSERTS_OUT_GLOBAL_FLAGS); - if (flags == MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS) - return (0); - - reason = (flags == MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL) - ? "system-level assertion" - : (flags == MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL) - ? "thread-level assertion" - : (flags == MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED) - ? "watchdog reset" - : "unknown assertion"; - EFSYS_PROBE3(mcpu_assertion, - const char *, reason, unsigned int, - MCDI_OUT_DWORD(req, GET_ASSERTS_OUT_SAVED_PC_OFFS), - unsigned int, - MCDI_OUT_DWORD(req, GET_ASSERTS_OUT_THREAD_OFFS)); - - /* Print out the registers */ - ofst = MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST; - for (index = 1; index < 32; index++) { - EFSYS_PROBE2(mcpu_register, unsigned int, index, unsigned int, - EFX_DWORD_FIELD(*MCDI_OUT(req, efx_dword_t, ofst), - EFX_DWORD_0)); - ofst += sizeof (efx_dword_t); - } - EFSYS_ASSERT(ofst <= MC_CMD_GET_ASSERTS_OUT_LEN); - - return (0); - -fail2: - EFSYS_PROBE(fail2); -fail1: - EFSYS_PROBE1(fail1, int, rc); - - return (rc); -} - -static __checkReturn int -siena_nic_attach( - __in efx_nic_t *enp, - __in boolean_t attach) -{ - efx_mcdi_req_t req; - uint8_t payload[MC_CMD_DRV_ATTACH_IN_LEN]; - int rc; - - req.emr_cmd = MC_CMD_DRV_ATTACH; - req.emr_in_buf = payload; - req.emr_in_length = MC_CMD_DRV_ATTACH_IN_LEN; - req.emr_out_buf = NULL; - req.emr_out_length = 0; - - MCDI_IN_SET_DWORD(req, DRV_ATTACH_IN_NEW_STATE, attach ? 1 : 0); - MCDI_IN_SET_DWORD(req, DRV_ATTACH_IN_UPDATE, 1); - - efx_mcdi_execute(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; - goto fail1; - } - - if (req.emr_out_length_used < MC_CMD_DRV_ATTACH_OUT_LEN) { - rc = EMSGSIZE; - goto fail2; - } - - return (0); - -fail2: - EFSYS_PROBE(fail2); -fail1: - EFSYS_PROBE1(fail1, int, rc); - - return (rc); -} - #if EFSYS_OPT_PCIE_TUNE __checkReturn int siena_nic_pcie_extended_sync( __in efx_nic_t *enp) { - uint8_t inbuf[MC_CMD_WORKAROUND_IN_LEN]; - efx_mcdi_req_t req; int rc; - EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); - - req.emr_cmd = MC_CMD_WORKAROUND; - req.emr_in_buf = inbuf; - req.emr_in_length = sizeof (inbuf); - EFX_STATIC_ASSERT(MC_CMD_WORKAROUND_OUT_LEN == 0); - req.emr_out_buf = NULL; - req.emr_out_length = 0; - - MCDI_IN_SET_DWORD(req, WORKAROUND_IN_TYPE, MC_CMD_WORKAROUND_BUG17230); - MCDI_IN_SET_DWORD(req, WORKAROUND_IN_ENABLED, 1); - - efx_mcdi_execute(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; + if ((rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG17230, + B_TRUE, NULL) != 0)) goto fail1; - } return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } #endif /* EFSYS_OPT_PCIE_TUNE */ static __checkReturn int siena_board_cfg( __in efx_nic_t *enp) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); - efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip); - uint8_t outbuf[MAX(MC_CMD_GET_BOARD_CFG_OUT_LENMIN, - MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN)]; - efx_mcdi_req_t req; - uint8_t *mac_addr; - efx_dword_t *capabilities; + uint8_t mac_addr[6]; + efx_dword_t capabilities; + uint32_t board_type; + uint32_t nevq, nrxq, ntxq; int rc; - /* Board configuration */ - req.emr_cmd = MC_CMD_GET_BOARD_CFG; - EFX_STATIC_ASSERT(MC_CMD_GET_BOARD_CFG_IN_LEN == 0); - req.emr_in_buf = NULL; - req.emr_in_length = 0; - req.emr_out_buf = outbuf; - req.emr_out_length = MC_CMD_GET_BOARD_CFG_OUT_LENMIN; + /* External port identifier using one-based port numbering */ + encp->enc_external_port = (uint8_t)enp->en_mcdi.em_emip.emi_port; - efx_mcdi_execute(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; + /* Board configuration */ + if ((rc = efx_mcdi_get_board_cfg(enp, &board_type, + &capabilities, mac_addr)) != 0) goto fail1; - } - if (req.emr_out_length_used < MC_CMD_GET_BOARD_CFG_OUT_LENMIN) { - rc = EMSGSIZE; - goto fail2; - } - - if (emip->emi_port == 1) { - mac_addr = MCDI_OUT2(req, uint8_t, - GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0); - capabilities = MCDI_OUT2(req, efx_dword_t, - GET_BOARD_CFG_OUT_CAPABILITIES_PORT0); - } else { - mac_addr = MCDI_OUT2(req, uint8_t, - GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1); - capabilities = MCDI_OUT2(req, efx_dword_t, - GET_BOARD_CFG_OUT_CAPABILITIES_PORT1); - } EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr); - encp->enc_board_type = MCDI_OUT_DWORD(req, - GET_BOARD_CFG_OUT_BOARD_TYPE); + encp->enc_board_type = board_type; /* Additional capabilities */ encp->enc_clk_mult = 1; - if (MCDI_CMD_DWORD_FIELD(capabilities, CAPABILITIES_TURBO)) { + if (EFX_DWORD_FIELD(capabilities, MC_CMD_CAPABILITIES_TURBO)) { enp->en_features |= EFX_FEATURE_TURBO; - if (MCDI_CMD_DWORD_FIELD(capabilities, - CAPABILITIES_TURBO_ACTIVE)) + if (EFX_DWORD_FIELD(capabilities, + MC_CMD_CAPABILITIES_TURBO_ACTIVE)) { encp->enc_clk_mult = 2; + } } encp->enc_evq_timer_quantum_ns = EFX_EVQ_SIENA_TIMER_QUANTUM_NS / encp->enc_clk_mult; encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000; - /* Resource limits */ - req.emr_cmd = MC_CMD_GET_RESOURCE_LIMITS; - EFX_STATIC_ASSERT(MC_CMD_GET_RESOURCE_LIMITS_IN_LEN == 0); - req.emr_in_buf = NULL; - req.emr_in_length = 0; - req.emr_out_buf = outbuf; - req.emr_out_length = MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN; + /* When hash header insertion is enabled, Siena inserts 16 bytes */ + encp->enc_rx_prefix_size = 16; - efx_mcdi_execute(enp, &req); + /* Alignment for receive packet DMA buffers */ + encp->enc_rx_buf_align_start = 1; + encp->enc_rx_buf_align_end = 1; - if (req.emr_rc == 0) { - if (req.emr_out_length_used < - MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN) { - rc = EMSGSIZE; - goto fail3; - } + /* Alignment for WPTR updates */ + encp->enc_rx_push_align = 1; - encp->enc_evq_limit = MCDI_OUT_DWORD(req, - GET_RESOURCE_LIMITS_OUT_EVQ); - encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, - MCDI_OUT_DWORD(req, GET_RESOURCE_LIMITS_OUT_TXQ)); - encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, - MCDI_OUT_DWORD(req, GET_RESOURCE_LIMITS_OUT_RXQ)); - } else if (req.emr_rc == ENOTSUP) { - encp->enc_evq_limit = 1024; - encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET; - encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET; - } else { - rc = req.emr_rc; - goto fail4; + /* Resource limits */ + rc = efx_mcdi_get_resource_limits(enp, &nevq, &nrxq, &ntxq); + if (rc != 0) { + if (rc != ENOTSUP) + goto fail2; + + nevq = 1024; + nrxq = EFX_RXQ_LIMIT_TARGET; + ntxq = EFX_TXQ_LIMIT_TARGET; } + encp->enc_evq_limit = nevq; + encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq); + encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq); encp->enc_buftbl_limit = SIENA_SRAM_ROWS - (encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) - (encp->enc_rxq_limit * EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE)); + encp->enc_hw_tx_insert_vlan_enabled = B_FALSE; + encp->enc_fw_assisted_tso_enabled = B_FALSE; + return (0); -fail4: - EFSYS_PROBE(fail4); -fail3: - EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } static __checkReturn int siena_phy_cfg( __in efx_nic_t *enp) { - efx_port_t *epp = &(enp->en_port); efx_nic_cfg_t *encp = &(enp->en_nic_cfg); - efx_mcdi_req_t req; - uint8_t outbuf[MC_CMD_GET_PHY_CFG_OUT_LEN]; int rc; - req.emr_cmd = MC_CMD_GET_PHY_CFG; - EFX_STATIC_ASSERT(MC_CMD_GET_PHY_CFG_IN_LEN == 0); - req.emr_in_buf = NULL; - req.emr_in_length = 0; - req.emr_out_buf = outbuf; - req.emr_out_length = sizeof (outbuf); - - efx_mcdi_execute(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; + /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ + if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) goto fail1; - } - if (req.emr_out_length_used < MC_CMD_GET_PHY_CFG_OUT_LEN) { - rc = EMSGSIZE; - goto fail2; - } - - encp->enc_phy_type = MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_TYPE); -#if EFSYS_OPT_NAMES - (void) strncpy(encp->enc_phy_name, - MCDI_OUT2(req, char, GET_PHY_CFG_OUT_NAME), - MIN(sizeof (encp->enc_phy_name) - 1, - MC_CMD_GET_PHY_CFG_OUT_NAME_LEN)); -#endif /* EFSYS_OPT_NAMES */ - (void) memset(encp->enc_phy_revision, 0, - sizeof (encp->enc_phy_revision)); - memcpy(encp->enc_phy_revision, - MCDI_OUT2(req, char, GET_PHY_CFG_OUT_REVISION), - MIN(sizeof (encp->enc_phy_revision) - 1, - MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN)); -#if EFSYS_OPT_PHY_LED_CONTROL - encp->enc_led_mask = ((1 << EFX_PHY_LED_DEFAULT) | - (1 << EFX_PHY_LED_OFF) | - (1 << EFX_PHY_LED_ON)); -#endif /* EFSYS_OPT_PHY_LED_CONTROL */ - -#if EFSYS_OPT_PHY_PROPS - encp->enc_phy_nprops = 0; -#endif /* EFSYS_OPT_PHY_PROPS */ - - /* Get the media type of the fixed port, if recognised. */ - EFX_STATIC_ASSERT(MC_CMD_MEDIA_XAUI == EFX_PHY_MEDIA_XAUI); - EFX_STATIC_ASSERT(MC_CMD_MEDIA_CX4 == EFX_PHY_MEDIA_CX4); - EFX_STATIC_ASSERT(MC_CMD_MEDIA_KX4 == EFX_PHY_MEDIA_KX4); - EFX_STATIC_ASSERT(MC_CMD_MEDIA_XFP == EFX_PHY_MEDIA_XFP); - EFX_STATIC_ASSERT(MC_CMD_MEDIA_SFP_PLUS == EFX_PHY_MEDIA_SFP_PLUS); - EFX_STATIC_ASSERT(MC_CMD_MEDIA_BASE_T == EFX_PHY_MEDIA_BASE_T); - epp->ep_fixed_port_type = - MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_MEDIA_TYPE); - if (epp->ep_fixed_port_type >= EFX_PHY_MEDIA_NTYPES) - epp->ep_fixed_port_type = EFX_PHY_MEDIA_INVALID; - - epp->ep_phy_cap_mask = - MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_SUPPORTED_CAP); -#if EFSYS_OPT_PHY_FLAGS - encp->enc_phy_flags_mask = MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_FLAGS); -#endif /* EFSYS_OPT_PHY_FLAGS */ - - encp->enc_port = (uint8_t)MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_PRT); - - /* Populate internal state */ - encp->enc_siena_channel = - (uint8_t)MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_CHANNEL); - #if EFSYS_OPT_PHY_STATS - encp->enc_siena_phy_stat_mask = - MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_STATS_MASK); - /* Convert the MCDI statistic mask into the EFX_PHY_STAT mask */ - siena_phy_decode_stats(enp, encp->enc_siena_phy_stat_mask, + siena_phy_decode_stats(enp, encp->enc_mcdi_phy_stat_mask, NULL, &encp->enc_phy_stat_mask, NULL); #endif /* EFSYS_OPT_PHY_STATS */ -#if EFSYS_OPT_PHY_BIST - encp->enc_bist_mask = 0; - if (MCDI_OUT_DWORD_FIELD(req, GET_PHY_CFG_OUT_FLAGS, - GET_PHY_CFG_OUT_BIST_CABLE_SHORT)) - encp->enc_bist_mask |= (1 << EFX_PHY_BIST_TYPE_CABLE_SHORT); - if (MCDI_OUT_DWORD_FIELD(req, GET_PHY_CFG_OUT_FLAGS, - GET_PHY_CFG_OUT_BIST_CABLE_LONG)) - encp->enc_bist_mask |= (1 << EFX_PHY_BIST_TYPE_CABLE_LONG); - if (MCDI_OUT_DWORD_FIELD(req, GET_PHY_CFG_OUT_FLAGS, - GET_PHY_CFG_OUT_BIST)) - encp->enc_bist_mask |= (1 << EFX_PHY_BIST_TYPE_NORMAL); -#endif /* EFSYS_OPT_PHY_BIST */ - return (0); -fail2: - EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } -#if EFSYS_OPT_LOOPBACK - -static __checkReturn int -siena_loopback_cfg( - __in efx_nic_t *enp) -{ - efx_nic_cfg_t *encp = &(enp->en_nic_cfg); - efx_mcdi_req_t req; - uint8_t outbuf[MC_CMD_GET_LOOPBACK_MODES_OUT_LEN]; - int rc; - - req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES; - EFX_STATIC_ASSERT(MC_CMD_GET_LOOPBACK_MODES_IN_LEN == 0); - req.emr_in_buf = NULL; - req.emr_in_length = 0; - req.emr_out_buf = outbuf; - req.emr_out_length = sizeof (outbuf); - - efx_mcdi_execute(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; - goto fail1; - } - - if (req.emr_out_length_used < MC_CMD_GET_LOOPBACK_MODES_OUT_LEN) { - rc = EMSGSIZE; - goto fail2; - } - - /* - * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree - * in siena_phy.c:siena_phy_get_link() - */ - encp->enc_loopback_types[EFX_LINK_100FDX] = EFX_LOOPBACK_MASK & - MCDI_OUT_DWORD(req, GET_LOOPBACK_MODES_OUT_100M) & - MCDI_OUT_DWORD(req, GET_LOOPBACK_MODES_OUT_SUGGESTED); - encp->enc_loopback_types[EFX_LINK_1000FDX] = EFX_LOOPBACK_MASK & - MCDI_OUT_DWORD(req, GET_LOOPBACK_MODES_OUT_1G) & - MCDI_OUT_DWORD(req, GET_LOOPBACK_MODES_OUT_SUGGESTED); - encp->enc_loopback_types[EFX_LINK_10000FDX] = EFX_LOOPBACK_MASK & - MCDI_OUT_DWORD(req, GET_LOOPBACK_MODES_OUT_10G) & - MCDI_OUT_DWORD(req, GET_LOOPBACK_MODES_OUT_SUGGESTED); - encp->enc_loopback_types[EFX_LINK_UNKNOWN] = - (1 << EFX_LOOPBACK_OFF) | - encp->enc_loopback_types[EFX_LINK_100FDX] | - encp->enc_loopback_types[EFX_LINK_1000FDX] | - encp->enc_loopback_types[EFX_LINK_10000FDX]; - - return (0); - -fail2: - EFSYS_PROBE(fail2); -fail1: - EFSYS_PROBE1(fail1, int, rc); - - return (rc); -} - -#endif /* EFSYS_OPT_LOOPBACK */ - -#if EFSYS_OPT_MON_STATS - -static __checkReturn int -siena_monitor_cfg( - __in efx_nic_t *enp) -{ - efx_nic_cfg_t *encp = &(enp->en_nic_cfg); - efx_mcdi_req_t req; - uint8_t outbuf[MCDI_CTL_SDU_LEN_MAX]; - int rc; - - req.emr_cmd = MC_CMD_SENSOR_INFO; - EFX_STATIC_ASSERT(MC_CMD_SENSOR_INFO_IN_LEN == 0); - req.emr_in_buf = NULL; - req.emr_in_length = 0; - req.emr_out_buf = outbuf; - req.emr_out_length = sizeof (outbuf); - - efx_mcdi_execute(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; - goto fail1; - } - - if (req.emr_out_length_used < MC_CMD_SENSOR_INFO_OUT_MASK_OFST + 4) { - rc = EMSGSIZE; - goto fail2; - } - - encp->enc_siena_mon_stat_mask = - MCDI_OUT_DWORD(req, SENSOR_INFO_OUT_MASK); - encp->enc_mon_type = EFX_MON_SFC90X0; - - siena_mon_decode_stats(enp, encp->enc_siena_mon_stat_mask, - NULL, &(encp->enc_mon_stat_mask), NULL); - - return (0); - -fail2: - EFSYS_PROBE(fail2); -fail1: - EFSYS_PROBE1(fail1, int, rc); - - return (rc); -} - -#endif /* EFSYS_OPT_MON_STATS */ - __checkReturn int siena_nic_probe( __in efx_nic_t *enp) { efx_port_t *epp = &(enp->en_port); efx_nic_cfg_t *encp = &(enp->en_nic_cfg); siena_link_state_t sls; unsigned int mask; + efx_oword_t oword; int rc; EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); - /* Read clear any assertion state */ - if ((rc = siena_nic_read_assertion(enp)) != 0) + /* Test BIU */ + if ((rc = efx_nic_biu_test(enp)) != 0) goto fail1; - /* Exit the assertion handler */ - if ((rc = siena_nic_exit_assertion_handler(enp)) != 0) + /* Clear the region register */ + EFX_POPULATE_OWORD_4(oword, + FRF_AZ_ADR_REGION0, 0, + FRF_AZ_ADR_REGION1, (1 << 16), + FRF_AZ_ADR_REGION2, (2 << 16), + FRF_AZ_ADR_REGION3, (3 << 16)); + EFX_BAR_WRITEO(enp, FR_AZ_ADR_REGION_REG, &oword); + + /* Read clear any assertion state */ + if ((rc = efx_mcdi_read_assertion(enp)) != 0) goto fail2; - /* Wrestle control from the BMC */ - if ((rc = siena_nic_attach(enp, B_TRUE)) != 0) + /* Exit the assertion handler */ + if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0) goto fail3; - if ((rc = siena_board_cfg(enp)) != 0) + /* Wrestle control from the BMC */ + if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0) goto fail4; - if ((rc = siena_phy_cfg(enp)) != 0) + if ((rc = siena_board_cfg(enp)) != 0) goto fail5; + if ((rc = siena_phy_cfg(enp)) != 0) + goto fail6; + /* Obtain the default PHY advertised capabilities */ if ((rc = siena_nic_reset(enp)) != 0) - goto fail6; - if ((rc = siena_phy_get_link(enp, &sls)) != 0) goto fail7; + if ((rc = siena_phy_get_link(enp, &sls)) != 0) + goto fail8; epp->ep_default_adv_cap_mask = sls.sls_adv_cap_mask; epp->ep_adv_cap_mask = sls.sls_adv_cap_mask; #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM if ((rc = siena_nic_get_partn_mask(enp, &mask)) != 0) - goto fail8; + goto fail9; enp->en_u.siena.enu_partn_mask = mask; #endif #if EFSYS_OPT_MAC_STATS /* Wipe the MAC statistics */ - if ((rc = siena_mac_stats_clear(enp)) != 0) - goto fail9; + if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0) + goto fail10; #endif #if EFSYS_OPT_LOOPBACK - if ((rc = siena_loopback_cfg(enp)) != 0) - goto fail10; + if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0) + goto fail11; #endif #if EFSYS_OPT_MON_STATS - if ((rc = siena_monitor_cfg(enp)) != 0) - goto fail11; + if ((rc = mcdi_mon_cfg_build(enp)) != 0) + goto fail12; #endif encp->enc_features = enp->en_features; return (0); #if EFSYS_OPT_MON_STATS +fail12: + EFSYS_PROBE(fail12); +#endif +#if EFSYS_OPT_LOOPBACK fail11: EFSYS_PROBE(fail11); #endif -#if EFSYS_OPT_LOOPBACK +#if EFSYS_OPT_MAC_STATS fail10: EFSYS_PROBE(fail10); #endif -#if EFSYS_OPT_MAC_STATS +#if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM fail9: EFSYS_PROBE(fail9); #endif -#if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM fail8: EFSYS_PROBE(fail8); -#endif fail7: EFSYS_PROBE(fail7); fail6: EFSYS_PROBE(fail6); fail5: EFSYS_PROBE(fail5); fail4: EFSYS_PROBE(fail4); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_nic_reset( __in efx_nic_t *enp) { efx_mcdi_req_t req; int rc; EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); /* siena_nic_reset() is called to recover from BADASSERT failures. */ - if ((rc = siena_nic_read_assertion(enp)) != 0) + if ((rc = efx_mcdi_read_assertion(enp)) != 0) goto fail1; - if ((rc = siena_nic_exit_assertion_handler(enp)) != 0) + if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0) goto fail2; - req.emr_cmd = MC_CMD_PORT_RESET; - EFX_STATIC_ASSERT(MC_CMD_PORT_RESET_IN_LEN == 0); + /* + * Bug24908: ENTITY_RESET_IN_LEN is non zero but zero may be supplied + * for backwards compatibility with PORT_RESET_IN_LEN. + */ + EFX_STATIC_ASSERT(MC_CMD_ENTITY_RESET_OUT_LEN == 0); + + req.emr_cmd = MC_CMD_ENTITY_RESET; req.emr_in_buf = NULL; req.emr_in_length = 0; - EFX_STATIC_ASSERT(MC_CMD_PORT_RESET_OUT_LEN == 0); req.emr_out_buf = NULL; req.emr_out_length = 0; efx_mcdi_execute(enp, &req); if (req.emr_rc != 0) { rc = req.emr_rc; goto fail3; } return (0); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (0); } -static __checkReturn int -siena_nic_logging( - __in efx_nic_t *enp) -{ - efx_mcdi_req_t req; - uint8_t payload[MC_CMD_LOG_CTRL_IN_LEN]; - int rc; - - req.emr_cmd = MC_CMD_LOG_CTRL; - req.emr_in_buf = payload; - req.emr_in_length = MC_CMD_LOG_CTRL_IN_LEN; - EFX_STATIC_ASSERT(MC_CMD_LOG_CTRL_OUT_LEN == 0); - req.emr_out_buf = NULL; - req.emr_out_length = 0; - - MCDI_IN_SET_DWORD(req, LOG_CTRL_IN_LOG_DEST, - MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ); - MCDI_IN_SET_DWORD(req, LOG_CTRL_IN_LOG_DEST_EVQ, 0); - - efx_mcdi_execute(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; - goto fail1; - } - - return (0); - -fail1: - EFSYS_PROBE1(fail1, int, rc); - - return (rc); -} - static void siena_nic_rx_cfg( __in efx_nic_t *enp) { efx_oword_t oword; /* * RX_INGR_EN is always enabled on Siena, because we rely on * the RX parser to be resiliant to missing SOP/EOP. */ EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword); EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_INGR_EN, 1); EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword); /* Disable parsing of additional 802.1Q in Q packets */ EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword); EFX_SET_OWORD_FIELD(oword, FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES, 0); EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword); } static void siena_nic_usrev_dis( __in efx_nic_t *enp) { efx_oword_t oword; EFX_POPULATE_OWORD_1(oword, FRF_CZ_USREV_DIS, 1); EFX_BAR_WRITEO(enp, FR_CZ_USR_EV_CFG, &oword); } __checkReturn int siena_nic_init( __in efx_nic_t *enp) { int rc; EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); - if ((rc = siena_nic_logging(enp)) != 0) + /* Enable reporting of some events (e.g. link change) */ + if ((rc = efx_mcdi_log_ctrl(enp)) != 0) goto fail1; siena_sram_init(enp); /* Configure Siena's RX block */ siena_nic_rx_cfg(enp); /* Disable USR_EVents for now */ siena_nic_usrev_dis(enp); /* bug17057: Ensure set_link is called */ if ((rc = siena_phy_reconfigure(enp)) != 0) goto fail2; return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } void siena_nic_fini( __in efx_nic_t *enp) { _NOTE(ARGUNUSED(enp)) } void siena_nic_unprobe( __in efx_nic_t *enp) { - (void) siena_nic_attach(enp, B_FALSE); +#if EFSYS_OPT_MON_STATS + mcdi_mon_cfg_free(enp); +#endif /* EFSYS_OPT_MON_STATS */ + (void) efx_mcdi_drv_attach(enp, B_FALSE); } #if EFSYS_OPT_DIAG -static efx_register_set_t __cs __siena_registers[] = { +static efx_register_set_t __siena_registers[] = { { FR_AZ_ADR_REGION_REG_OFST, 0, 1 }, { FR_CZ_USR_EV_CFG_OFST, 0, 1 }, { FR_AZ_RX_CFG_REG_OFST, 0, 1 }, { FR_AZ_TX_CFG_REG_OFST, 0, 1 }, { FR_AZ_TX_RESERVED_REG_OFST, 0, 1 }, { FR_AZ_SRM_TX_DC_CFG_REG_OFST, 0, 1 }, { FR_AZ_RX_DC_CFG_REG_OFST, 0, 1 }, { FR_AZ_RX_DC_PF_WM_REG_OFST, 0, 1 }, { FR_AZ_DP_CTRL_REG_OFST, 0, 1 }, { FR_BZ_RX_RSS_TKEY_REG_OFST, 0, 1}, { FR_CZ_RX_RSS_IPV6_REG1_OFST, 0, 1}, { FR_CZ_RX_RSS_IPV6_REG2_OFST, 0, 1}, { FR_CZ_RX_RSS_IPV6_REG3_OFST, 0, 1} }; -static const uint32_t __cs __siena_register_masks[] = { +static const uint32_t __siena_register_masks[] = { 0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x000103FF, 0x00000000, 0x00000000, 0x00000000, 0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000, 0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF, 0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF, 0x001FFFFF, 0x00000000, 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x000003FF, 0x00000000, 0x00000000, 0x00000000, 0x00000FFF, 0x00000000, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000 }; -static efx_register_set_t __cs __siena_tables[] = { +static efx_register_set_t __siena_tables[] = { { FR_AZ_RX_FILTER_TBL0_OFST, FR_AZ_RX_FILTER_TBL0_STEP, FR_AZ_RX_FILTER_TBL0_ROWS }, { FR_CZ_RX_MAC_FILTER_TBL0_OFST, FR_CZ_RX_MAC_FILTER_TBL0_STEP, FR_CZ_RX_MAC_FILTER_TBL0_ROWS }, { FR_AZ_RX_DESC_PTR_TBL_OFST, FR_AZ_RX_DESC_PTR_TBL_STEP, FR_CZ_RX_DESC_PTR_TBL_ROWS }, { FR_AZ_TX_DESC_PTR_TBL_OFST, FR_AZ_TX_DESC_PTR_TBL_STEP, FR_CZ_TX_DESC_PTR_TBL_ROWS }, { FR_AZ_TIMER_TBL_OFST, FR_AZ_TIMER_TBL_STEP, FR_CZ_TIMER_TBL_ROWS }, { FR_CZ_TX_FILTER_TBL0_OFST, FR_CZ_TX_FILTER_TBL0_STEP, FR_CZ_TX_FILTER_TBL0_ROWS }, { FR_CZ_TX_MAC_FILTER_TBL0_OFST, FR_CZ_TX_MAC_FILTER_TBL0_STEP, FR_CZ_TX_MAC_FILTER_TBL0_ROWS } }; -static const uint32_t __cs __siena_table_masks[] = { +static const uint32_t __siena_table_masks[] = { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000003FF, 0xFFFF0FFF, 0xFFFFFFFF, 0x00000E7F, 0x00000000, 0xFFFFFFFE, 0x0FFFFFFF, 0x01800000, 0x00000000, 0xFFFFFFFE, 0x0FFFFFFF, 0x0C000000, 0x00000000, 0x3FFFFFFF, 0x00000000, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000013FF, 0xFFFF07FF, 0xFFFFFFFF, 0x0000007F, 0x00000000, }; __checkReturn int siena_nic_register_test( __in efx_nic_t *enp) { efx_register_set_t *rsp; const uint32_t *dwordp; unsigned int nitems; unsigned int count; int rc; /* Fill out the register mask entries */ EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_register_masks) == EFX_ARRAY_SIZE(__siena_registers) * 4); nitems = EFX_ARRAY_SIZE(__siena_registers); dwordp = __siena_register_masks; for (count = 0; count < nitems; ++count) { rsp = __siena_registers + count; rsp->mask.eo_u32[0] = *dwordp++; rsp->mask.eo_u32[1] = *dwordp++; rsp->mask.eo_u32[2] = *dwordp++; rsp->mask.eo_u32[3] = *dwordp++; } /* Fill out the register table entries */ EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_table_masks) == EFX_ARRAY_SIZE(__siena_tables) * 4); nitems = EFX_ARRAY_SIZE(__siena_tables); dwordp = __siena_table_masks; for (count = 0; count < nitems; ++count) { rsp = __siena_tables + count; rsp->mask.eo_u32[0] = *dwordp++; rsp->mask.eo_u32[1] = *dwordp++; rsp->mask.eo_u32[2] = *dwordp++; rsp->mask.eo_u32[3] = *dwordp++; } if ((rc = efx_nic_test_registers(enp, __siena_registers, EFX_ARRAY_SIZE(__siena_registers))) != 0) goto fail1; if ((rc = efx_nic_test_tables(enp, __siena_tables, EFX_PATTERN_BYTE_ALTERNATE, EFX_ARRAY_SIZE(__siena_tables))) != 0) goto fail2; if ((rc = efx_nic_test_tables(enp, __siena_tables, EFX_PATTERN_BYTE_CHANGING, EFX_ARRAY_SIZE(__siena_tables))) != 0) goto fail3; if ((rc = efx_nic_test_tables(enp, __siena_tables, EFX_PATTERN_BIT_SWEEP, EFX_ARRAY_SIZE(__siena_tables))) != 0) goto fail4; return (0); fail4: EFSYS_PROBE(fail4); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } #endif /* EFSYS_OPT_DIAG */ #endif /* EFSYS_OPT_SIENA */ Property changes on: head/sys/dev/sfxge/common/siena_nic.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/siena_nvram.c =================================================================== --- head/sys/dev/sfxge/common/siena_nvram.c (revision 283513) +++ head/sys/dev/sfxge/common/siena_nvram.c (revision 283514) @@ -1,1005 +1,871 @@ /*- - * Copyright 2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2009-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include "efsys.h" #include "efx.h" #include "efx_types.h" #include "efx_regs.h" #include "efx_impl.h" #if EFSYS_OPT_SIENA #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM __checkReturn int siena_nvram_partn_size( __in efx_nic_t *enp, __in unsigned int partn, __out size_t *sizep) { - efx_mcdi_req_t req; - uint8_t payload[MAX(MC_CMD_NVRAM_INFO_IN_LEN, - MC_CMD_NVRAM_INFO_OUT_LEN)]; int rc; if ((1 << partn) & ~enp->en_u.siena.enu_partn_mask) { rc = ENOTSUP; goto fail1; } - req.emr_cmd = MC_CMD_NVRAM_INFO; - req.emr_in_buf = payload; - req.emr_in_length = MC_CMD_NVRAM_INFO_IN_LEN; - req.emr_out_buf = payload; - req.emr_out_length = MC_CMD_NVRAM_INFO_OUT_LEN; - - MCDI_IN_SET_DWORD(req, NVRAM_INFO_IN_TYPE, partn); - - efx_mcdi_execute(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; + if ((rc = efx_mcdi_nvram_info(enp, partn, sizep, NULL, NULL)) != 0) { goto fail2; } - if (req.emr_out_length_used < MC_CMD_NVRAM_INFO_OUT_LEN) { - rc = EMSGSIZE; - goto fail3; - } - - *sizep = MCDI_OUT_DWORD(req, NVRAM_INFO_OUT_SIZE); - return (0); -fail3: - EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_nvram_partn_lock( __in efx_nic_t *enp, __in unsigned int partn) { - efx_mcdi_req_t req; - uint8_t payload[MC_CMD_NVRAM_UPDATE_START_IN_LEN]; int rc; - req.emr_cmd = MC_CMD_NVRAM_UPDATE_START; - req.emr_in_buf = payload; - req.emr_in_length = MC_CMD_NVRAM_UPDATE_START_IN_LEN; - EFX_STATIC_ASSERT(MC_CMD_NVRAM_UPDATE_START_OUT_LEN == 0); - req.emr_out_buf = NULL; - req.emr_out_length = 0; - - MCDI_IN_SET_DWORD(req, NVRAM_UPDATE_START_IN_TYPE, partn); - - efx_mcdi_execute(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; + if ((rc = efx_mcdi_nvram_update_start(enp, partn)) != 0) { goto fail1; } return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_nvram_partn_read( __in efx_nic_t *enp, __in unsigned int partn, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size) { - efx_mcdi_req_t req; - uint8_t payload[MAX(MC_CMD_NVRAM_READ_IN_LEN, - MC_CMD_NVRAM_READ_OUT_LEN(SIENA_NVRAM_CHUNK))]; size_t chunk; int rc; while (size > 0) { chunk = MIN(size, SIENA_NVRAM_CHUNK); - req.emr_cmd = MC_CMD_NVRAM_READ; - req.emr_in_buf = payload; - req.emr_in_length = MC_CMD_NVRAM_READ_IN_LEN; - req.emr_out_buf = payload; - req.emr_out_length = - MC_CMD_NVRAM_READ_OUT_LEN(SIENA_NVRAM_CHUNK); - - MCDI_IN_SET_DWORD(req, NVRAM_READ_IN_TYPE, partn); - MCDI_IN_SET_DWORD(req, NVRAM_READ_IN_OFFSET, offset); - MCDI_IN_SET_DWORD(req, NVRAM_READ_IN_LENGTH, chunk); - - efx_mcdi_execute(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; + if ((rc = efx_mcdi_nvram_read(enp, partn, offset, + data, chunk)) != 0) { goto fail1; } - if (req.emr_out_length_used < - MC_CMD_NVRAM_READ_OUT_LEN(chunk)) { - rc = EMSGSIZE; - goto fail2; - } - - memcpy(data, - MCDI_OUT2(req, uint8_t, NVRAM_READ_OUT_READ_BUFFER), - chunk); - size -= chunk; data += chunk; offset += chunk; } return (0); -fail2: - EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_nvram_partn_erase( __in efx_nic_t *enp, __in unsigned int partn, __in unsigned int offset, __in size_t size) { - efx_mcdi_req_t req; - uint8_t payload[MC_CMD_NVRAM_ERASE_IN_LEN]; int rc; - req.emr_cmd = MC_CMD_NVRAM_ERASE; - req.emr_in_buf = payload; - req.emr_in_length = MC_CMD_NVRAM_ERASE_IN_LEN; - EFX_STATIC_ASSERT(MC_CMD_NVRAM_ERASE_OUT_LEN == 0); - req.emr_out_buf = NULL; - req.emr_out_length = 0; - - MCDI_IN_SET_DWORD(req, NVRAM_ERASE_IN_TYPE, partn); - MCDI_IN_SET_DWORD(req, NVRAM_ERASE_IN_OFFSET, offset); - MCDI_IN_SET_DWORD(req, NVRAM_ERASE_IN_LENGTH, size); - - efx_mcdi_execute(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; + if ((rc = efx_mcdi_nvram_erase(enp, partn, offset, size)) != 0) { goto fail1; } return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_nvram_partn_write( __in efx_nic_t *enp, __in unsigned int partn, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size) { - efx_mcdi_req_t req; - uint8_t payload[MC_CMD_NVRAM_WRITE_IN_LEN(SIENA_NVRAM_CHUNK)]; size_t chunk; int rc; while (size > 0) { chunk = MIN(size, SIENA_NVRAM_CHUNK); - req.emr_cmd = MC_CMD_NVRAM_WRITE; - req.emr_in_buf = payload; - req.emr_in_length = MC_CMD_NVRAM_WRITE_IN_LEN(chunk); - EFX_STATIC_ASSERT(MC_CMD_NVRAM_WRITE_OUT_LEN == 0); - req.emr_out_buf = NULL; - req.emr_out_length = 0; - - MCDI_IN_SET_DWORD(req, NVRAM_WRITE_IN_TYPE, partn); - MCDI_IN_SET_DWORD(req, NVRAM_WRITE_IN_OFFSET, offset); - MCDI_IN_SET_DWORD(req, NVRAM_WRITE_IN_LENGTH, chunk); - - memcpy(MCDI_IN2(req, uint8_t, NVRAM_WRITE_IN_WRITE_BUFFER), - data, chunk); - - efx_mcdi_execute(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; + if ((rc = efx_mcdi_nvram_write(enp, partn, offset, + data, chunk)) != 0) { goto fail1; } size -= chunk; data += chunk; offset += chunk; } return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } void siena_nvram_partn_unlock( __in efx_nic_t *enp, __in unsigned int partn) { - efx_mcdi_req_t req; - uint8_t payload[MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN]; - uint32_t reboot; + boolean_t reboot; int rc; - req.emr_cmd = MC_CMD_NVRAM_UPDATE_FINISH; - req.emr_in_buf = payload; - req.emr_in_length = MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN; - EFX_STATIC_ASSERT(MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN == 0); - req.emr_out_buf = NULL; - req.emr_out_length = 0; - /* * Reboot into the new image only for PHYs. The driver has to * explicitly cope with an MC reboot after a firmware update. */ reboot = (partn == MC_CMD_NVRAM_TYPE_PHY_PORT0 || partn == MC_CMD_NVRAM_TYPE_PHY_PORT1 || partn == MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO); - MCDI_IN_SET_DWORD(req, NVRAM_UPDATE_FINISH_IN_TYPE, partn); - MCDI_IN_SET_DWORD(req, NVRAM_UPDATE_FINISH_IN_REBOOT, reboot); - - efx_mcdi_execute(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; + if ((rc = efx_mcdi_nvram_update_finish(enp, partn, reboot)) != 0) { goto fail1; } return; fail1: EFSYS_PROBE1(fail1, int, rc); } #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ #if EFSYS_OPT_NVRAM typedef struct siena_parttbl_entry_s { unsigned int partn; unsigned int port; efx_nvram_type_t nvtype; } siena_parttbl_entry_t; static siena_parttbl_entry_t siena_parttbl[] = { {MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO, 1, EFX_NVRAM_NULLPHY}, {MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO, 2, EFX_NVRAM_NULLPHY}, {MC_CMD_NVRAM_TYPE_MC_FW, 1, EFX_NVRAM_MC_FIRMWARE}, {MC_CMD_NVRAM_TYPE_MC_FW, 2, EFX_NVRAM_MC_FIRMWARE}, {MC_CMD_NVRAM_TYPE_MC_FW_BACKUP, 1, EFX_NVRAM_MC_GOLDEN}, {MC_CMD_NVRAM_TYPE_MC_FW_BACKUP, 2, EFX_NVRAM_MC_GOLDEN}, {MC_CMD_NVRAM_TYPE_EXP_ROM, 1, EFX_NVRAM_BOOTROM}, {MC_CMD_NVRAM_TYPE_EXP_ROM, 2, EFX_NVRAM_BOOTROM}, {MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0, 1, EFX_NVRAM_BOOTROM_CFG}, {MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1, 2, EFX_NVRAM_BOOTROM_CFG}, {MC_CMD_NVRAM_TYPE_PHY_PORT0, 1, EFX_NVRAM_PHY}, {MC_CMD_NVRAM_TYPE_PHY_PORT1, 2, EFX_NVRAM_PHY}, {MC_CMD_NVRAM_TYPE_FPGA, 1, EFX_NVRAM_FPGA}, {MC_CMD_NVRAM_TYPE_FPGA, 2, EFX_NVRAM_FPGA}, {MC_CMD_NVRAM_TYPE_FPGA_BACKUP, 1, EFX_NVRAM_FPGA_BACKUP}, {MC_CMD_NVRAM_TYPE_FPGA_BACKUP, 2, EFX_NVRAM_FPGA_BACKUP}, {MC_CMD_NVRAM_TYPE_FC_FW, 1, EFX_NVRAM_FCFW}, {MC_CMD_NVRAM_TYPE_FC_FW, 2, EFX_NVRAM_FCFW}, {MC_CMD_NVRAM_TYPE_CPLD, 1, EFX_NVRAM_CPLD}, {MC_CMD_NVRAM_TYPE_CPLD, 2, EFX_NVRAM_CPLD}, - {0, 0, 0}, }; static __checkReturn siena_parttbl_entry_t * siena_parttbl_entry( __in efx_nic_t *enp, __in efx_nvram_type_t type) { - efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip); + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); siena_parttbl_entry_t *entry; + unsigned int i; EFSYS_ASSERT3U(type, <, EFX_NVRAM_NTYPES); - for (entry = siena_parttbl; entry->port > 0; ++entry) { + for (i = 0; i < EFX_ARRAY_SIZE(siena_parttbl); i++) { + entry = &siena_parttbl[i]; + if (entry->port == emip->emi_port && entry->nvtype == type) return (entry); } return (NULL); } #if EFSYS_OPT_DIAG __checkReturn int siena_nvram_test( __in efx_nic_t *enp) { - efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip); + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); siena_parttbl_entry_t *entry; - efx_mcdi_req_t req; - uint8_t payload[MAX(MC_CMD_NVRAM_TEST_IN_LEN, - MC_CMD_NVRAM_TEST_OUT_LEN)]; - int result; + unsigned int i; int rc; - req.emr_cmd = MC_CMD_NVRAM_TEST; - req.emr_in_buf = payload; - req.emr_in_length = MC_CMD_NVRAM_TEST_IN_LEN; - req.emr_out_buf = payload; - req.emr_out_length = MC_CMD_NVRAM_TEST_OUT_LEN; - /* * Iterate over the list of supported partition types * applicable to *this* port */ - for (entry = siena_parttbl; entry->port > 0; ++entry) { + for (i = 0; i < EFX_ARRAY_SIZE(siena_parttbl); i++) { + entry = &siena_parttbl[i]; + if (entry->port != emip->emi_port || !(enp->en_u.siena.enu_partn_mask & (1 << entry->partn))) continue; - MCDI_IN_SET_DWORD(req, NVRAM_TEST_IN_TYPE, entry->partn); - - efx_mcdi_execute(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; + if ((rc = efx_mcdi_nvram_test(enp, entry->partn)) != 0) { goto fail1; } - - if (req.emr_out_length_used < MC_CMD_NVRAM_TEST_OUT_LEN) { - rc = EMSGSIZE; - goto fail2; - } - - result = MCDI_OUT_DWORD(req, NVRAM_TEST_OUT_RESULT); - if (result == MC_CMD_NVRAM_TEST_FAIL) { - - EFSYS_PROBE1(nvram_test_failure, int, entry->partn); - - rc = (EINVAL); - goto fail3; - } } return (0); -fail3: - EFSYS_PROBE(fail3); -fail2: - EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } #endif /* EFSYS_OPT_DIAG */ __checkReturn int siena_nvram_size( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out size_t *sizep) { siena_parttbl_entry_t *entry; int rc; if ((entry = siena_parttbl_entry(enp, type)) == NULL) { rc = ENOTSUP; goto fail1; } if ((rc = siena_nvram_partn_size(enp, entry->partn, sizep)) != 0) goto fail2; return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); *sizep = 0; return (rc); } #define SIENA_DYNAMIC_CFG_SIZE(_nitems) \ (sizeof (siena_mc_dynamic_config_hdr_t) + ((_nitems) * \ sizeof (((siena_mc_dynamic_config_hdr_t *)NULL)->fw_version[0]))) __checkReturn int siena_nvram_get_dynamic_cfg( __in efx_nic_t *enp, __in unsigned int partn, __in boolean_t vpd, __out siena_mc_dynamic_config_hdr_t **dcfgp, __out size_t *sizep) { - siena_mc_dynamic_config_hdr_t *dcfg; + siena_mc_dynamic_config_hdr_t *dcfg = NULL; size_t size; uint8_t cksum; unsigned int vpd_offset; unsigned int vpd_length; unsigned int hdr_length; unsigned int nversions; unsigned int pos; unsigned int region; int rc; EFSYS_ASSERT(partn == MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 || partn == MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1); /* * Allocate sufficient memory for the entire dynamiccfg area, even * if we're not actually going to read in the VPD. */ if ((rc = siena_nvram_partn_size(enp, partn, &size)) != 0) goto fail1; EFSYS_KMEM_ALLOC(enp->en_esip, size, dcfg); if (dcfg == NULL) { rc = ENOMEM; goto fail2; } if ((rc = siena_nvram_partn_read(enp, partn, 0, (caddr_t)dcfg, SIENA_NVRAM_CHUNK)) != 0) goto fail3; /* Verify the magic */ if (EFX_DWORD_FIELD(dcfg->magic, EFX_DWORD_0) != SIENA_MC_DYNAMIC_CONFIG_MAGIC) goto invalid1; /* All future versions of the structure must be backwards compatable */ EFX_STATIC_ASSERT(SIENA_MC_DYNAMIC_CONFIG_VERSION == 0); hdr_length = EFX_WORD_FIELD(dcfg->length, EFX_WORD_0); nversions = EFX_DWORD_FIELD(dcfg->num_fw_version_items, EFX_DWORD_0); vpd_offset = EFX_DWORD_FIELD(dcfg->dynamic_vpd_offset, EFX_DWORD_0); vpd_length = EFX_DWORD_FIELD(dcfg->dynamic_vpd_length, EFX_DWORD_0); /* Verify the hdr doesn't overflow the partn size */ if (hdr_length > size || vpd_offset > size || vpd_length > size || vpd_length + vpd_offset > size) goto invalid2; /* Verify the header has room for all it's versions */ if (hdr_length < SIENA_DYNAMIC_CFG_SIZE(0) || hdr_length < SIENA_DYNAMIC_CFG_SIZE(nversions)) goto invalid3; /* * Read the remaining portion of the dcfg, either including * the whole of VPD (there is no vpd length in this structure, * so we have to parse each tag), or just the dcfg header itself */ region = vpd ? vpd_offset + vpd_length : hdr_length; if (region > SIENA_NVRAM_CHUNK) { if ((rc = siena_nvram_partn_read(enp, partn, SIENA_NVRAM_CHUNK, (caddr_t)dcfg + SIENA_NVRAM_CHUNK, region - SIENA_NVRAM_CHUNK)) != 0) goto fail4; } /* Verify checksum */ cksum = 0; for (pos = 0; pos < hdr_length; pos++) cksum += ((uint8_t *)dcfg)[pos]; if (cksum != 0) goto invalid4; goto done; invalid4: EFSYS_PROBE(invalid4); invalid3: EFSYS_PROBE(invalid3); invalid2: EFSYS_PROBE(invalid2); invalid1: EFSYS_PROBE(invalid1); /* * Construct a new "null" dcfg, with an empty version vector, * and an empty VPD chunk trailing. This has the neat side effect * of testing the exception paths in the write path. */ EFX_POPULATE_DWORD_1(dcfg->magic, EFX_DWORD_0, SIENA_MC_DYNAMIC_CONFIG_MAGIC); EFX_POPULATE_WORD_1(dcfg->length, EFX_WORD_0, sizeof (*dcfg)); EFX_POPULATE_BYTE_1(dcfg->version, EFX_BYTE_0, SIENA_MC_DYNAMIC_CONFIG_VERSION); EFX_POPULATE_DWORD_1(dcfg->dynamic_vpd_offset, EFX_DWORD_0, sizeof (*dcfg)); EFX_POPULATE_DWORD_1(dcfg->dynamic_vpd_length, EFX_DWORD_0, 0); EFX_POPULATE_DWORD_1(dcfg->num_fw_version_items, EFX_DWORD_0, 0); done: *dcfgp = dcfg; *sizep = size; return (0); fail4: EFSYS_PROBE(fail4); fail3: EFSYS_PROBE(fail3); -fail2: - EFSYS_PROBE(fail2); EFSYS_KMEM_FREE(enp->en_esip, size, dcfg); +fail2: + EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } -static __checkReturn int + __checkReturn int siena_nvram_get_subtype( __in efx_nic_t *enp, __in unsigned int partn, __out uint32_t *subtypep) { efx_mcdi_req_t req; - uint8_t outbuf[MC_CMD_GET_BOARD_CFG_OUT_LENMAX]; + uint8_t payload[MAX(MC_CMD_GET_BOARD_CFG_IN_LEN, + MC_CMD_GET_BOARD_CFG_OUT_LENMAX)]; efx_word_t *fw_list; int rc; + (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_GET_BOARD_CFG; - EFX_STATIC_ASSERT(MC_CMD_GET_BOARD_CFG_IN_LEN == 0); - req.emr_in_buf = NULL; - req.emr_in_length = 0; - req.emr_out_buf = outbuf; - req.emr_out_length = sizeof (outbuf); + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_GET_BOARD_CFG_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_GET_BOARD_CFG_OUT_LENMAX; efx_mcdi_execute(enp, &req); if (req.emr_rc != 0) { rc = req.emr_rc; goto fail1; } if (req.emr_out_length_used < MC_CMD_GET_BOARD_CFG_OUT_LENMIN) { rc = EMSGSIZE; goto fail2; } if (req.emr_out_length_used < MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST + (partn + 1) * sizeof (efx_word_t)) { rc = ENOENT; goto fail3; } fw_list = MCDI_OUT2(req, efx_word_t, GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST); *subtypep = EFX_WORD_FIELD(fw_list[partn], EFX_WORD_0); return (0); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_nvram_get_version( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out uint32_t *subtypep, __out_ecount(4) uint16_t version[4]) { siena_mc_dynamic_config_hdr_t *dcfg; siena_parttbl_entry_t *entry; unsigned int dcfg_partn; unsigned int partn; + unsigned int i; int rc; if ((entry = siena_parttbl_entry(enp, type)) == NULL) { rc = ENOTSUP; goto fail1; } partn = entry->partn; if ((1 << partn) & ~enp->en_u.siena.enu_partn_mask) { rc = ENOTSUP; goto fail2; } if ((rc = siena_nvram_get_subtype(enp, partn, subtypep)) != 0) goto fail3; /* * Some partitions are accessible from both ports (for instance BOOTROM) * Find the highest version reported by all dcfg structures on ports * that have access to this partition. */ version[0] = version[1] = version[2] = version[3] = 0; - for (entry = siena_parttbl; entry->port > 0; ++entry) { + for (i = 0; i < EFX_ARRAY_SIZE(siena_parttbl); i++) { unsigned int nitems; uint16_t temp[4]; size_t length; + entry = &siena_parttbl[i]; if (entry->partn != partn) continue; dcfg_partn = (entry->port == 1) ? MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 : MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1; /* * Ingore missing partitions on port 2, assuming they're due * to to running on a single port part. */ if ((1 << dcfg_partn) & ~enp->en_u.siena.enu_partn_mask) { if (entry->port == 2) continue; } if ((rc = siena_nvram_get_dynamic_cfg(enp, dcfg_partn, B_FALSE, &dcfg, &length)) != 0) goto fail4; nitems = EFX_DWORD_FIELD(dcfg->num_fw_version_items, EFX_DWORD_0); if (nitems < entry->partn) goto done; temp[0] = EFX_WORD_FIELD(dcfg->fw_version[partn].version_w, EFX_WORD_0); temp[1] = EFX_WORD_FIELD(dcfg->fw_version[partn].version_x, EFX_WORD_0); temp[2] = EFX_WORD_FIELD(dcfg->fw_version[partn].version_y, EFX_WORD_0); temp[3] = EFX_WORD_FIELD(dcfg->fw_version[partn].version_z, EFX_WORD_0); if (memcmp(version, temp, sizeof (temp)) < 0) memcpy(version, temp, sizeof (temp)); done: EFSYS_KMEM_FREE(enp->en_esip, length, dcfg); } return (0); fail4: EFSYS_PROBE(fail4); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_nvram_rw_start( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out size_t *chunk_sizep) { siena_parttbl_entry_t *entry; int rc; if ((entry = siena_parttbl_entry(enp, type)) == NULL) { rc = ENOTSUP; goto fail1; } if ((rc = siena_nvram_partn_lock(enp, entry->partn)) != 0) goto fail2; if (chunk_sizep != NULL) *chunk_sizep = SIENA_NVRAM_CHUNK; return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_nvram_read_chunk( __in efx_nic_t *enp, __in efx_nvram_type_t type, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size) { siena_parttbl_entry_t *entry; int rc; if ((entry = siena_parttbl_entry(enp, type)) == NULL) { rc = ENOTSUP; goto fail1; } if ((rc = siena_nvram_partn_read(enp, entry->partn, offset, data, size)) != 0) goto fail2; return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_nvram_erase( __in efx_nic_t *enp, __in efx_nvram_type_t type) { siena_parttbl_entry_t *entry; size_t size; int rc; if ((entry = siena_parttbl_entry(enp, type)) == NULL) { rc = ENOTSUP; goto fail1; } if ((rc = siena_nvram_partn_size(enp, entry->partn, &size)) != 0) goto fail2; if ((rc = siena_nvram_partn_erase(enp, entry->partn, 0, size)) != 0) goto fail3; return (0); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_nvram_write_chunk( __in efx_nic_t *enp, __in efx_nvram_type_t type, __in unsigned int offset, __in_bcount(size) caddr_t data, __in size_t size) { siena_parttbl_entry_t *entry; int rc; if ((entry = siena_parttbl_entry(enp, type)) == NULL) { rc = ENOTSUP; goto fail1; } if ((rc = siena_nvram_partn_write(enp, entry->partn, offset, data, size)) != 0) goto fail2; return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } void siena_nvram_rw_finish( __in efx_nic_t *enp, __in efx_nvram_type_t type) { siena_parttbl_entry_t *entry; if ((entry = siena_parttbl_entry(enp, type)) != NULL) siena_nvram_partn_unlock(enp, entry->partn); } __checkReturn int siena_nvram_set_version( __in efx_nic_t *enp, __in efx_nvram_type_t type, - __out uint16_t version[4]) + __in_ecount(4) uint16_t version[4]) { siena_mc_dynamic_config_hdr_t *dcfg = NULL; siena_parttbl_entry_t *entry; unsigned int dcfg_partn; size_t partn_size; unsigned int hdr_length; unsigned int vpd_length; unsigned int vpd_offset; unsigned int nitems; unsigned int required_hdr_length; unsigned int pos; uint8_t cksum; uint32_t subtype; size_t length; int rc; if ((entry = siena_parttbl_entry(enp, type)) == NULL) { rc = ENOTSUP; goto fail1; } dcfg_partn = (entry->port == 1) ? MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 : MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1; if ((rc = siena_nvram_partn_size(enp, dcfg_partn, &partn_size)) != 0) goto fail2; if ((rc = siena_nvram_partn_lock(enp, dcfg_partn)) != 0) goto fail2; if ((rc = siena_nvram_get_dynamic_cfg(enp, dcfg_partn, B_TRUE, &dcfg, &length)) != 0) goto fail3; hdr_length = EFX_WORD_FIELD(dcfg->length, EFX_WORD_0); nitems = EFX_DWORD_FIELD(dcfg->num_fw_version_items, EFX_DWORD_0); vpd_length = EFX_DWORD_FIELD(dcfg->dynamic_vpd_length, EFX_DWORD_0); vpd_offset = EFX_DWORD_FIELD(dcfg->dynamic_vpd_offset, EFX_DWORD_0); /* * NOTE: This function will blatt any fields trailing the version * vector, or the VPD chunk. */ required_hdr_length = SIENA_DYNAMIC_CFG_SIZE(entry->partn + 1); if (required_hdr_length + vpd_length > length) { rc = ENOSPC; goto fail4; } if (vpd_offset < required_hdr_length) { (void) memmove((caddr_t)dcfg + required_hdr_length, (caddr_t)dcfg + vpd_offset, vpd_length); vpd_offset = required_hdr_length; EFX_POPULATE_DWORD_1(dcfg->dynamic_vpd_offset, EFX_DWORD_0, vpd_offset); } if (hdr_length < required_hdr_length) { (void) memset((caddr_t)dcfg + hdr_length, 0, required_hdr_length - hdr_length); hdr_length = required_hdr_length; EFX_POPULATE_WORD_1(dcfg->length, EFX_WORD_0, hdr_length); } /* Get the subtype to insert into the fw_subtype array */ if ((rc = siena_nvram_get_subtype(enp, entry->partn, &subtype)) != 0) goto fail5; /* Fill out the new version */ EFX_POPULATE_DWORD_1(dcfg->fw_version[entry->partn].fw_subtype, EFX_DWORD_0, subtype); EFX_POPULATE_WORD_1(dcfg->fw_version[entry->partn].version_w, EFX_WORD_0, version[0]); EFX_POPULATE_WORD_1(dcfg->fw_version[entry->partn].version_x, EFX_WORD_0, version[1]); EFX_POPULATE_WORD_1(dcfg->fw_version[entry->partn].version_y, EFX_WORD_0, version[2]); EFX_POPULATE_WORD_1(dcfg->fw_version[entry->partn].version_z, EFX_WORD_0, version[3]); /* Update the version count */ if (nitems < entry->partn + 1) { nitems = entry->partn + 1; EFX_POPULATE_DWORD_1(dcfg->num_fw_version_items, EFX_DWORD_0, nitems); } /* Update the checksum */ cksum = 0; for (pos = 0; pos < hdr_length; pos++) cksum += ((uint8_t *)dcfg)[pos]; dcfg->csum.eb_u8[0] -= cksum; /* Erase and write the new partition */ if ((rc = siena_nvram_partn_erase(enp, dcfg_partn, 0, partn_size)) != 0) goto fail6; /* Write out the new structure to nvram */ if ((rc = siena_nvram_partn_write(enp, dcfg_partn, 0, (caddr_t)dcfg, vpd_offset + vpd_length)) != 0) goto fail7; EFSYS_KMEM_FREE(enp->en_esip, length, dcfg); siena_nvram_partn_unlock(enp, dcfg_partn); return (0); fail7: EFSYS_PROBE(fail7); fail6: EFSYS_PROBE(fail6); fail5: EFSYS_PROBE(fail5); fail4: EFSYS_PROBE(fail4); EFSYS_KMEM_FREE(enp->en_esip, length, dcfg); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } #endif /* EFSYS_OPT_NVRAM */ #endif /* EFSYS_OPT_SIENA */ Property changes on: head/sys/dev/sfxge/common/siena_nvram.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/siena_phy.c =================================================================== --- head/sys/dev/sfxge/common/siena_phy.c (revision 283513) +++ head/sys/dev/sfxge/common/siena_phy.c (revision 283514) @@ -1,861 +1,842 @@ /*- - * Copyright 2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2009-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include "efsys.h" #include "efx.h" #include "efx_impl.h" #if EFSYS_OPT_SIENA static void siena_phy_decode_cap( __in uint32_t mcdi_cap, __out uint32_t *maskp) { uint32_t mask; mask = 0; if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10HDX_LBN)) mask |= (1 << EFX_PHY_CAP_10HDX); if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10FDX_LBN)) mask |= (1 << EFX_PHY_CAP_10FDX); if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100HDX_LBN)) mask |= (1 << EFX_PHY_CAP_100HDX); if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100FDX_LBN)) mask |= (1 << EFX_PHY_CAP_100FDX); if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000HDX_LBN)) mask |= (1 << EFX_PHY_CAP_1000HDX); if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000FDX_LBN)) mask |= (1 << EFX_PHY_CAP_1000FDX); if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10000FDX_LBN)) mask |= (1 << EFX_PHY_CAP_10000FDX); if (mcdi_cap & (1 << MC_CMD_PHY_CAP_PAUSE_LBN)) mask |= (1 << EFX_PHY_CAP_PAUSE); if (mcdi_cap & (1 << MC_CMD_PHY_CAP_ASYM_LBN)) mask |= (1 << EFX_PHY_CAP_ASYM); if (mcdi_cap & (1 << MC_CMD_PHY_CAP_AN_LBN)) mask |= (1 << EFX_PHY_CAP_AN); *maskp = mask; } static void siena_phy_decode_link_mode( __in efx_nic_t *enp, __in uint32_t link_flags, __in unsigned int speed, __in unsigned int fcntl, __out efx_link_mode_t *link_modep, __out unsigned int *fcntlp) { boolean_t fd = !!(link_flags & (1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN)); boolean_t up = !!(link_flags & (1 << MC_CMD_GET_LINK_OUT_LINK_UP_LBN)); _NOTE(ARGUNUSED(enp)) if (!up) *link_modep = EFX_LINK_DOWN; else if (speed == 10000 && fd) *link_modep = EFX_LINK_10000FDX; else if (speed == 1000) *link_modep = fd ? EFX_LINK_1000FDX : EFX_LINK_1000HDX; else if (speed == 100) *link_modep = fd ? EFX_LINK_100FDX : EFX_LINK_100HDX; else if (speed == 10) *link_modep = fd ? EFX_LINK_10FDX : EFX_LINK_10HDX; else *link_modep = EFX_LINK_UNKNOWN; if (fcntl == MC_CMD_FCNTL_OFF) *fcntlp = 0; else if (fcntl == MC_CMD_FCNTL_RESPOND) *fcntlp = EFX_FCNTL_RESPOND; else if (fcntl == MC_CMD_FCNTL_BIDIR) *fcntlp = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE; else { EFSYS_PROBE1(mc_pcol_error, int, fcntl); *fcntlp = 0; } } void siena_phy_link_ev( __in efx_nic_t *enp, __in efx_qword_t *eqp, __out efx_link_mode_t *link_modep) { efx_port_t *epp = &(enp->en_port); unsigned int link_flags; unsigned int speed; unsigned int fcntl; efx_link_mode_t link_mode; uint32_t lp_cap_mask; /* * Convert the LINKCHANGE speed enumeration into mbit/s, in the * same way as GET_LINK encodes the speed */ switch (MCDI_EV_FIELD(eqp, LINKCHANGE_SPEED)) { case MCDI_EVENT_LINKCHANGE_SPEED_100M: speed = 100; break; case MCDI_EVENT_LINKCHANGE_SPEED_1G: speed = 1000; break; case MCDI_EVENT_LINKCHANGE_SPEED_10G: speed = 10000; break; default: speed = 0; break; } link_flags = MCDI_EV_FIELD(eqp, LINKCHANGE_LINK_FLAGS); siena_phy_decode_link_mode(enp, link_flags, speed, MCDI_EV_FIELD(eqp, LINKCHANGE_FCNTL), &link_mode, &fcntl); siena_phy_decode_cap(MCDI_EV_FIELD(eqp, LINKCHANGE_LP_CAP), &lp_cap_mask); /* * It's safe to update ep_lp_cap_mask without the driver's port lock * because presumably any concurrently running efx_port_poll() is * only going to arrive at the same value. * * ep_fcntl has two meanings. It's either the link common fcntl * (if the PHY supports AN), or it's the forced link state. If * the former, it's safe to update the value for the same reason as * for ep_lp_cap_mask. If the latter, then just ignore the value, * because we can race with efx_mac_fcntl_set(). */ epp->ep_lp_cap_mask = lp_cap_mask; if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN)) epp->ep_fcntl = fcntl; *link_modep = link_mode; } __checkReturn int siena_phy_power( __in efx_nic_t *enp, __in boolean_t power) { int rc; if (!power) return (0); /* Check if the PHY is a zombie */ if ((rc = siena_phy_verify(enp)) != 0) goto fail1; enp->en_reset_flags |= EFX_RESET_PHY; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_phy_get_link( __in efx_nic_t *enp, __out siena_link_state_t *slsp) { efx_mcdi_req_t req; - uint8_t outbuf[MC_CMD_GET_LINK_OUT_LEN]; + uint8_t payload[MAX(MC_CMD_GET_LINK_IN_LEN, + MC_CMD_GET_LINK_OUT_LEN)]; int rc; + (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_GET_LINK; - EFX_STATIC_ASSERT(MC_CMD_GET_LINK_IN_LEN == 0); - req.emr_in_buf = NULL; - req.emr_in_length = 0; - req.emr_out_buf = outbuf; - req.emr_out_length = sizeof (outbuf); + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_GET_LINK_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_GET_LINK_OUT_LEN; efx_mcdi_execute(enp, &req); if (req.emr_rc != 0) { rc = req.emr_rc; goto fail1; } if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_LEN) { rc = EMSGSIZE; goto fail2; } siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_CAP), &slsp->sls_adv_cap_mask); siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_LP_CAP), &slsp->sls_lp_cap_mask); siena_phy_decode_link_mode(enp, MCDI_OUT_DWORD(req, GET_LINK_OUT_FLAGS), MCDI_OUT_DWORD(req, GET_LINK_OUT_LINK_SPEED), MCDI_OUT_DWORD(req, GET_LINK_OUT_FCNTL), &slsp->sls_link_mode, &slsp->sls_fcntl); #if EFSYS_OPT_LOOPBACK /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespace agree */ EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_NONE == EFX_LOOPBACK_OFF); EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_DATA == EFX_LOOPBACK_DATA); EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMAC == EFX_LOOPBACK_GMAC); EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII == EFX_LOOPBACK_XGMII); EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGXS == EFX_LOOPBACK_XGXS); EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI == EFX_LOOPBACK_XAUI); EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII == EFX_LOOPBACK_GMII); EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII == EFX_LOOPBACK_SGMII); EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGBR == EFX_LOOPBACK_XGBR); EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI == EFX_LOOPBACK_XFI); EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_FAR == EFX_LOOPBACK_XAUI_FAR); EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_FAR == EFX_LOOPBACK_GMII_FAR); EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII_FAR == EFX_LOOPBACK_SGMII_FAR); EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_FAR == EFX_LOOPBACK_XFI_FAR); EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GPHY == EFX_LOOPBACK_GPHY); EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS == EFX_LOOPBACK_PHY_XS); EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PCS == EFX_LOOPBACK_PCS); EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMAPMD == EFX_LOOPBACK_PMA_PMD); slsp->sls_loopback = MCDI_OUT_DWORD(req, GET_LINK_OUT_LOOPBACK_MODE); #endif /* EFSYS_OPT_LOOPBACK */ slsp->sls_mac_up = MCDI_OUT_DWORD(req, GET_LINK_OUT_MAC_FAULT) == 0; return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_phy_reconfigure( __in efx_nic_t *enp) { efx_port_t *epp = &(enp->en_port); efx_mcdi_req_t req; - uint8_t payload[MAX(MC_CMD_SET_ID_LED_IN_LEN, - MC_CMD_SET_LINK_IN_LEN)]; + uint8_t payload[MAX(MAX(MC_CMD_SET_ID_LED_IN_LEN, + MC_CMD_SET_ID_LED_OUT_LEN), + MAX(MC_CMD_SET_LINK_IN_LEN, + MC_CMD_SET_LINK_OUT_LEN))]; uint32_t cap_mask; unsigned int led_mode; unsigned int speed; int rc; + (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_SET_LINK; req.emr_in_buf = payload; req.emr_in_length = MC_CMD_SET_LINK_IN_LEN; - EFX_STATIC_ASSERT(MC_CMD_SET_LINK_OUT_LEN == 0); - req.emr_out_buf = NULL; - req.emr_out_length = 0; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_SET_LINK_OUT_LEN; cap_mask = epp->ep_adv_cap_mask; MCDI_IN_POPULATE_DWORD_10(req, SET_LINK_IN_CAP, PHY_CAP_10HDX, (cap_mask >> EFX_PHY_CAP_10HDX) & 0x1, PHY_CAP_10FDX, (cap_mask >> EFX_PHY_CAP_10FDX) & 0x1, PHY_CAP_100HDX, (cap_mask >> EFX_PHY_CAP_100HDX) & 0x1, PHY_CAP_100FDX, (cap_mask >> EFX_PHY_CAP_100FDX) & 0x1, PHY_CAP_1000HDX, (cap_mask >> EFX_PHY_CAP_1000HDX) & 0x1, PHY_CAP_1000FDX, (cap_mask >> EFX_PHY_CAP_1000FDX) & 0x1, PHY_CAP_10000FDX, (cap_mask >> EFX_PHY_CAP_10000FDX) & 0x1, PHY_CAP_PAUSE, (cap_mask >> EFX_PHY_CAP_PAUSE) & 0x1, PHY_CAP_ASYM, (cap_mask >> EFX_PHY_CAP_ASYM) & 0x1, PHY_CAP_AN, (cap_mask >> EFX_PHY_CAP_AN) & 0x1); #if EFSYS_OPT_LOOPBACK MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, epp->ep_loopback_type); switch (epp->ep_loopback_link_mode) { case EFX_LINK_100FDX: speed = 100; break; case EFX_LINK_1000FDX: speed = 1000; break; case EFX_LINK_10000FDX: speed = 10000; break; default: speed = 0; } #else MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, MC_CMD_LOOPBACK_NONE); speed = 0; #endif /* EFSYS_OPT_LOOPBACK */ MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_SPEED, speed); #if EFSYS_OPT_PHY_FLAGS MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, epp->ep_phy_flags); #else MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, 0); #endif /* EFSYS_OPT_PHY_FLAGS */ efx_mcdi_execute(enp, &req); if (req.emr_rc != 0) { rc = req.emr_rc; goto fail1; } /* And set the blink mode */ + (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_SET_ID_LED; req.emr_in_buf = payload; req.emr_in_length = MC_CMD_SET_ID_LED_IN_LEN; - EFX_STATIC_ASSERT(MC_CMD_SET_ID_LED_OUT_LEN == 0); - req.emr_out_buf = NULL; - req.emr_out_length = 0; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_SET_ID_LED_OUT_LEN; #if EFSYS_OPT_PHY_LED_CONTROL switch (epp->ep_phy_led_mode) { case EFX_PHY_LED_DEFAULT: led_mode = MC_CMD_LED_DEFAULT; break; case EFX_PHY_LED_OFF: led_mode = MC_CMD_LED_OFF; break; case EFX_PHY_LED_ON: led_mode = MC_CMD_LED_ON; break; default: EFSYS_ASSERT(0); led_mode = MC_CMD_LED_DEFAULT; } MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, led_mode); #else MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, MC_CMD_LED_DEFAULT); #endif /* EFSYS_OPT_PHY_LED_CONTROL */ efx_mcdi_execute(enp, &req); if (req.emr_rc != 0) { rc = req.emr_rc; goto fail2; } return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_phy_verify( __in efx_nic_t *enp) { efx_mcdi_req_t req; - uint8_t outbuf[MC_CMD_GET_PHY_STATE_OUT_LEN]; + uint8_t payload[MAX(MC_CMD_GET_PHY_STATE_IN_LEN, + MC_CMD_GET_PHY_STATE_OUT_LEN)]; uint32_t state; int rc; + (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_GET_PHY_STATE; - EFX_STATIC_ASSERT(MC_CMD_GET_PHY_STATE_IN_LEN == 0); - req.emr_in_buf = NULL; - req.emr_in_length = 0; - req.emr_out_buf = outbuf; - req.emr_out_length = sizeof (outbuf); + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_GET_PHY_STATE_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_GET_PHY_STATE_OUT_LEN; efx_mcdi_execute(enp, &req); if (req.emr_rc != 0) { rc = req.emr_rc; goto fail1; } if (req.emr_out_length_used < MC_CMD_GET_PHY_STATE_OUT_LEN) { rc = EMSGSIZE; goto fail2; } state = MCDI_OUT_DWORD(req, GET_PHY_STATE_OUT_STATE); if (state != MC_CMD_PHY_STATE_OK) { if (state != MC_CMD_PHY_STATE_ZOMBIE) EFSYS_PROBE1(mc_pcol_error, int, state); rc = ENOTACTIVE; goto fail3; } return (0); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_phy_oui_get( __in efx_nic_t *enp, __out uint32_t *ouip) { _NOTE(ARGUNUSED(enp, ouip)) return (ENOTSUP); } #if EFSYS_OPT_PHY_STATS #define SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \ _mc_record, _efx_record) \ if ((_vmask) & (1ULL << (_mc_record))) { \ (_smask) |= (1ULL << (_efx_record)); \ if ((_stat) != NULL && !EFSYS_MEM_IS_NULL(_esmp)) { \ efx_dword_t dword; \ EFSYS_MEM_READD(_esmp, (_mc_record) * 4, &dword);\ (_stat)[_efx_record] = \ EFX_DWORD_FIELD(dword, EFX_DWORD_0); \ } \ } #define SIENA_SIMPLE_STAT_SET2(_vmask, _esmp, _smask, _stat, _record) \ SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \ MC_CMD_ ## _record, \ EFX_PHY_STAT_ ## _record) void siena_phy_decode_stats( __in efx_nic_t *enp, __in uint32_t vmask, __in_opt efsys_mem_t *esmp, __out_opt uint64_t *smaskp, __out_ecount_opt(EFX_PHY_NSTATS) uint32_t *stat) { uint64_t smask = 0; _NOTE(ARGUNUSED(enp)) SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, OUI); SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_LINK_UP); SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_RX_FAULT); SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_TX_FAULT); if (vmask & (1 << MC_CMD_PMA_PMD_SIGNAL)) { smask |= ((1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_A) | (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_B) | (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_C) | (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_D)); if (stat != NULL && esmp != NULL && !EFSYS_MEM_IS_NULL(esmp)) { efx_dword_t dword; uint32_t sig; EFSYS_MEM_READD(esmp, 4 * MC_CMD_PMA_PMD_SIGNAL, &dword); sig = EFX_DWORD_FIELD(dword, EFX_DWORD_0); stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_A] = (sig >> 1) & 1; stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_B] = (sig >> 2) & 1; stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_C] = (sig >> 3) & 1; stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_D] = (sig >> 4) & 1; } } SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_A, EFX_PHY_STAT_SNR_A); SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_B, EFX_PHY_STAT_SNR_B); SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_C, EFX_PHY_STAT_SNR_C); SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_D, EFX_PHY_STAT_SNR_D); SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_LINK_UP); SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_RX_FAULT); SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_TX_FAULT); SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BER); SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BLOCK_ERRORS); SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_LINK_UP, EFX_PHY_STAT_PHY_XS_LINK_UP); SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_RX_FAULT, EFX_PHY_STAT_PHY_XS_RX_FAULT); SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_TX_FAULT, EFX_PHY_STAT_PHY_XS_TX_FAULT); SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_ALIGN, EFX_PHY_STAT_PHY_XS_ALIGN); if (vmask & (1 << MC_CMD_PHYXS_SYNC)) { smask |= ((1 << EFX_PHY_STAT_PHY_XS_SYNC_A) | (1 << EFX_PHY_STAT_PHY_XS_SYNC_B) | (1 << EFX_PHY_STAT_PHY_XS_SYNC_C) | (1 << EFX_PHY_STAT_PHY_XS_SYNC_D)); if (stat != NULL && !EFSYS_MEM_IS_NULL(esmp)) { efx_dword_t dword; uint32_t sync; EFSYS_MEM_READD(esmp, 4 * MC_CMD_PHYXS_SYNC, &dword); sync = EFX_DWORD_FIELD(dword, EFX_DWORD_0); stat[EFX_PHY_STAT_PHY_XS_SYNC_A] = (sync >> 0) & 1; stat[EFX_PHY_STAT_PHY_XS_SYNC_B] = (sync >> 1) & 1; stat[EFX_PHY_STAT_PHY_XS_SYNC_C] = (sync >> 2) & 1; stat[EFX_PHY_STAT_PHY_XS_SYNC_D] = (sync >> 3) & 1; } } SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_LINK_UP); SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_COMPLETE); SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_CL22_LINK_UP, EFX_PHY_STAT_CL22EXT_LINK_UP); if (smaskp != NULL) *smaskp = smask; } __checkReturn int siena_phy_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, __out_ecount(EFX_PHY_NSTATS) uint32_t *stat) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); - uint32_t vmask = encp->enc_siena_phy_stat_mask; - uint8_t payload[MC_CMD_PHY_STATS_IN_LEN]; + uint32_t vmask = encp->enc_mcdi_phy_stat_mask; uint64_t smask; efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_PHY_STATS_IN_LEN, + MC_CMD_PHY_STATS_OUT_DMA_LEN)]; int rc; + (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_PHY_STATS; req.emr_in_buf = payload; - req.emr_in_length = sizeof (payload); - EFX_STATIC_ASSERT(MC_CMD_PHY_STATS_OUT_DMA_LEN == 0); - req.emr_out_buf = NULL; - req.emr_out_length = 0; + req.emr_in_length = MC_CMD_PHY_STATS_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_PHY_STATS_OUT_DMA_LEN; MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_LO, EFSYS_MEM_ADDR(esmp) & 0xffffffff); MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_HI, EFSYS_MEM_ADDR(esmp) >> 32); efx_mcdi_execute(enp, &req); if (req.emr_rc != 0) { rc = req.emr_rc; goto fail1; } EFSYS_ASSERT3U(req.emr_out_length, ==, MC_CMD_PHY_STATS_OUT_DMA_LEN); siena_phy_decode_stats(enp, vmask, esmp, &smask, stat); EFSYS_ASSERT(smask == encp->enc_phy_stat_mask); return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (0); } #endif /* EFSYS_OPT_PHY_STATS */ #if EFSYS_OPT_PHY_PROPS #if EFSYS_OPT_NAMES -extern const char __cs * +extern const char * siena_phy_prop_name( __in efx_nic_t *enp, __in unsigned int id) { _NOTE(ARGUNUSED(enp, id)) return (NULL); } #endif /* EFSYS_OPT_NAMES */ extern __checkReturn int siena_phy_prop_get( __in efx_nic_t *enp, __in unsigned int id, __in uint32_t flags, __out uint32_t *valp) { _NOTE(ARGUNUSED(enp, id, flags, valp)) return (ENOTSUP); } extern __checkReturn int siena_phy_prop_set( __in efx_nic_t *enp, __in unsigned int id, __in uint32_t val) { _NOTE(ARGUNUSED(enp, id, val)) return (ENOTSUP); } #endif /* EFSYS_OPT_PHY_PROPS */ -#if EFSYS_OPT_PHY_BIST +#if EFSYS_OPT_BIST __checkReturn int siena_phy_bist_start( __in efx_nic_t *enp, - __in efx_phy_bist_type_t type) + __in efx_bist_type_t type) { - uint8_t payload[MC_CMD_START_BIST_IN_LEN]; - efx_mcdi_req_t req; int rc; - req.emr_cmd = MC_CMD_START_BIST; - req.emr_in_buf = payload; - req.emr_in_length = sizeof (payload); - EFX_STATIC_ASSERT(MC_CMD_START_BIST_OUT_LEN == 0); - req.emr_out_buf = NULL; - req.emr_out_length = 0; - - switch (type) { - case EFX_PHY_BIST_TYPE_NORMAL: - MCDI_IN_SET_DWORD(req, START_BIST_IN_TYPE, MC_CMD_PHY_BIST); - break; - case EFX_PHY_BIST_TYPE_CABLE_SHORT: - MCDI_IN_SET_DWORD(req, START_BIST_IN_TYPE, - MC_CMD_PHY_BIST_CABLE_SHORT); - break; - case EFX_PHY_BIST_TYPE_CABLE_LONG: - MCDI_IN_SET_DWORD(req, START_BIST_IN_TYPE, - MC_CMD_PHY_BIST_CABLE_LONG); - break; - default: - EFSYS_ASSERT(0); - } - - efx_mcdi_execute(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; + if ((rc = efx_mcdi_bist_start(enp, type)) != 0) goto fail1; - } return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } static __checkReturn unsigned long siena_phy_sft9001_bist_status( __in uint16_t code) { switch (code) { case MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY: return (EFX_PHY_CABLE_STATUS_BUSY); case MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT: return (EFX_PHY_CABLE_STATUS_INTERPAIRSHORT); case MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT: return (EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT); case MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN: return (EFX_PHY_CABLE_STATUS_OPEN); case MC_CMD_POLL_BIST_SFT9001_PAIR_OK: return (EFX_PHY_CABLE_STATUS_OK); default: return (EFX_PHY_CABLE_STATUS_INVALID); } } __checkReturn int siena_phy_bist_poll( __in efx_nic_t *enp, - __in efx_phy_bist_type_t type, - __out efx_phy_bist_result_t *resultp, + __in efx_bist_type_t type, + __out efx_bist_result_t *resultp, __out_opt __drv_when(count > 0, __notnull) uint32_t *value_maskp, __out_ecount_opt(count) __drv_when(count > 0, __notnull) unsigned long *valuesp, __in size_t count) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); - uint8_t payload[MCDI_CTL_SDU_LEN_MAX]; + uint8_t payload[MAX(MC_CMD_POLL_BIST_IN_LEN, + MCDI_CTL_SDU_LEN_MAX)]; uint32_t value_mask = 0; efx_mcdi_req_t req; uint32_t result; int rc; + (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_POLL_BIST; - _NOTE(CONSTANTCONDITION) - EFSYS_ASSERT(MC_CMD_POLL_BIST_IN_LEN == 0); - req.emr_in_buf = NULL; - req.emr_in_length = 0; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_POLL_BIST_IN_LEN; req.emr_out_buf = payload; - req.emr_out_length = sizeof (payload); + req.emr_out_length = MCDI_CTL_SDU_LEN_MAX; efx_mcdi_execute(enp, &req); if (req.emr_rc != 0) { rc = req.emr_rc; goto fail1; } if (req.emr_out_length_used < MC_CMD_POLL_BIST_OUT_RESULT_OFST + 4) { rc = EMSGSIZE; goto fail2; } if (count > 0) (void) memset(valuesp, '\0', count * sizeof (unsigned long)); result = MCDI_OUT_DWORD(req, POLL_BIST_OUT_RESULT); /* Extract PHY specific results */ if (result == MC_CMD_POLL_BIST_PASSED && encp->enc_phy_type == EFX_PHY_SFT9001B && req.emr_out_length_used >= MC_CMD_POLL_BIST_OUT_SFT9001_LEN && - (type == EFX_PHY_BIST_TYPE_CABLE_SHORT || - type == EFX_PHY_BIST_TYPE_CABLE_LONG)) { + (type == EFX_BIST_TYPE_PHY_CABLE_SHORT || + type == EFX_BIST_TYPE_PHY_CABLE_LONG)) { uint16_t word; - if (count > EFX_PHY_BIST_CABLE_LENGTH_A) { + if (count > EFX_BIST_PHY_CABLE_LENGTH_A) { if (valuesp != NULL) - valuesp[EFX_PHY_BIST_CABLE_LENGTH_A] = + valuesp[EFX_BIST_PHY_CABLE_LENGTH_A] = MCDI_OUT_DWORD(req, POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A); - value_mask |= (1 << EFX_PHY_BIST_CABLE_LENGTH_A); + value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_A); } - if (count > EFX_PHY_BIST_CABLE_LENGTH_B) { + if (count > EFX_BIST_PHY_CABLE_LENGTH_B) { if (valuesp != NULL) - valuesp[EFX_PHY_BIST_CABLE_LENGTH_B] = + valuesp[EFX_BIST_PHY_CABLE_LENGTH_B] = MCDI_OUT_DWORD(req, POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B); - value_mask |= (1 << EFX_PHY_BIST_CABLE_LENGTH_B); + value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_B); } - if (count > EFX_PHY_BIST_CABLE_LENGTH_C) { + if (count > EFX_BIST_PHY_CABLE_LENGTH_C) { if (valuesp != NULL) - valuesp[EFX_PHY_BIST_CABLE_LENGTH_C] = + valuesp[EFX_BIST_PHY_CABLE_LENGTH_C] = MCDI_OUT_DWORD(req, POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C); - value_mask |= (1 << EFX_PHY_BIST_CABLE_LENGTH_C); + value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_C); } - if (count > EFX_PHY_BIST_CABLE_LENGTH_D) { + if (count > EFX_BIST_PHY_CABLE_LENGTH_D) { if (valuesp != NULL) - valuesp[EFX_PHY_BIST_CABLE_LENGTH_D] = + valuesp[EFX_BIST_PHY_CABLE_LENGTH_D] = MCDI_OUT_DWORD(req, POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D); - value_mask |= (1 << EFX_PHY_BIST_CABLE_LENGTH_D); + value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_D); } - if (count > EFX_PHY_BIST_CABLE_STATUS_A) { + if (count > EFX_BIST_PHY_CABLE_STATUS_A) { if (valuesp != NULL) { word = MCDI_OUT_WORD(req, POLL_BIST_OUT_SFT9001_CABLE_STATUS_A); - valuesp[EFX_PHY_BIST_CABLE_STATUS_A] = + valuesp[EFX_BIST_PHY_CABLE_STATUS_A] = siena_phy_sft9001_bist_status(word); } - value_mask |= (1 << EFX_PHY_BIST_CABLE_STATUS_A); + value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_A); } - if (count > EFX_PHY_BIST_CABLE_STATUS_B) { + if (count > EFX_BIST_PHY_CABLE_STATUS_B) { if (valuesp != NULL) { word = MCDI_OUT_WORD(req, POLL_BIST_OUT_SFT9001_CABLE_STATUS_B); - valuesp[EFX_PHY_BIST_CABLE_STATUS_B] = + valuesp[EFX_BIST_PHY_CABLE_STATUS_B] = siena_phy_sft9001_bist_status(word); } - value_mask |= (1 << EFX_PHY_BIST_CABLE_STATUS_B); + value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_B); } - if (count > EFX_PHY_BIST_CABLE_STATUS_C) { + if (count > EFX_BIST_PHY_CABLE_STATUS_C) { if (valuesp != NULL) { word = MCDI_OUT_WORD(req, POLL_BIST_OUT_SFT9001_CABLE_STATUS_C); - valuesp[EFX_PHY_BIST_CABLE_STATUS_C] = + valuesp[EFX_BIST_PHY_CABLE_STATUS_C] = siena_phy_sft9001_bist_status(word); } - value_mask |= (1 << EFX_PHY_BIST_CABLE_STATUS_C); + value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_C); } - if (count > EFX_PHY_BIST_CABLE_STATUS_D) { + if (count > EFX_BIST_PHY_CABLE_STATUS_D) { if (valuesp != NULL) { word = MCDI_OUT_WORD(req, POLL_BIST_OUT_SFT9001_CABLE_STATUS_D); - valuesp[EFX_PHY_BIST_CABLE_STATUS_D] = + valuesp[EFX_BIST_PHY_CABLE_STATUS_D] = siena_phy_sft9001_bist_status(word); } - value_mask |= (1 << EFX_PHY_BIST_CABLE_STATUS_D); + value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_D); } } else if (result == MC_CMD_POLL_BIST_FAILED && encp->enc_phy_type == EFX_PHY_QLX111V && req.emr_out_length >= MC_CMD_POLL_BIST_OUT_MRSFP_LEN && - count > EFX_PHY_BIST_FAULT_CODE) { + count > EFX_BIST_FAULT_CODE) { if (valuesp != NULL) - valuesp[EFX_PHY_BIST_FAULT_CODE] = + valuesp[EFX_BIST_FAULT_CODE] = MCDI_OUT_DWORD(req, POLL_BIST_OUT_MRSFP_TEST); - value_mask |= 1 << EFX_PHY_BIST_FAULT_CODE; + value_mask |= 1 << EFX_BIST_FAULT_CODE; } if (value_maskp != NULL) *value_maskp = value_mask; EFSYS_ASSERT(resultp != NULL); if (result == MC_CMD_POLL_BIST_RUNNING) - *resultp = EFX_PHY_BIST_RESULT_RUNNING; + *resultp = EFX_BIST_RESULT_RUNNING; else if (result == MC_CMD_POLL_BIST_PASSED) - *resultp = EFX_PHY_BIST_RESULT_PASSED; + *resultp = EFX_BIST_RESULT_PASSED; else - *resultp = EFX_PHY_BIST_RESULT_FAILED; + *resultp = EFX_BIST_RESULT_FAILED; return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } void siena_phy_bist_stop( __in efx_nic_t *enp, - __in efx_phy_bist_type_t type) + __in efx_bist_type_t type) { /* There is no way to stop BIST on Siena */ _NOTE(ARGUNUSED(enp, type)) } -#endif /* EFSYS_OPT_PHY_BIST */ +#endif /* EFSYS_OPT_BIST */ #endif /* EFSYS_OPT_SIENA */ Property changes on: head/sys/dev/sfxge/common/siena_phy.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/siena_sram.c =================================================================== --- head/sys/dev/sfxge/common/siena_sram.c (revision 283513) +++ head/sys/dev/sfxge/common/siena_sram.c (revision 283514) @@ -1,177 +1,182 @@ /*- - * Copyright 2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2009-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include "efsys.h" #include "efx.h" #include "efx_impl.h" #if EFSYS_OPT_SIENA void siena_sram_init( __in efx_nic_t *enp) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); efx_oword_t oword; uint32_t rx_base, tx_base; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); rx_base = encp->enc_buftbl_limit; tx_base = rx_base + (encp->enc_rxq_limit * EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE)); /* Initialize the transmit descriptor cache */ EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, tx_base); EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword); EFX_POPULATE_OWORD_1(oword, FRF_AZ_TX_DC_SIZE, EFX_TXQ_DC_SIZE); EFX_BAR_WRITEO(enp, FR_AZ_TX_DC_CFG_REG, &oword); /* Initialize the receive descriptor cache */ EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rx_base); EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword); EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_SIZE, EFX_RXQ_DC_SIZE); EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_CFG_REG, &oword); /* Set receive descriptor pre-fetch low water mark */ EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_PF_LWM, 56); EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_PF_WM_REG, &oword); /* Set the event queue to use for SRAM updates */ EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_UPD_EVQ_ID, 0); EFX_BAR_WRITEO(enp, FR_AZ_SRM_UPD_EVQ_REG, &oword); } #if EFSYS_OPT_DIAG __checkReturn int siena_sram_test( __in efx_nic_t *enp, __in efx_sram_pattern_fn_t func) { efx_oword_t oword; efx_qword_t qword; efx_qword_t verify; size_t rows; unsigned int wptr; unsigned int rptr; int rc; EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); /* Reconfigure into HALF buffer table mode */ EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 0); EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword); /* * Move the descriptor caches up to the top of SRAM, and test * all of SRAM below them. We only miss out one row here. */ rows = SIENA_SRAM_ROWS - 1; EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rows); EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword); EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, rows + 1); EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword); /* * Write the pattern through BUF_HALF_TBL. Write * in 64 entry batches, waiting 1us in between each batch * to guarantee not to overflow the SRAM fifo */ for (wptr = 0, rptr = 0; wptr < rows; ++wptr) { func(wptr, B_FALSE, &qword); EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_HALF_TBL, wptr, &qword); if ((wptr - rptr) < 64 && wptr < rows - 1) continue; EFSYS_SPIN(1); for (; rptr <= wptr; ++rptr) { func(rptr, B_FALSE, &qword); EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_HALF_TBL, rptr, &verify); if (!EFX_QWORD_IS_EQUAL(verify, qword)) { rc = EFAULT; goto fail1; } } } /* And do the same negated */ for (wptr = 0, rptr = 0; wptr < rows; ++wptr) { func(wptr, B_TRUE, &qword); EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_HALF_TBL, wptr, &qword); if ((wptr - rptr) < 64 && wptr < rows - 1) continue; EFSYS_SPIN(1); for (; rptr <= wptr; ++rptr) { func(rptr, B_TRUE, &qword); EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_HALF_TBL, rptr, &verify); if (!EFX_QWORD_IS_EQUAL(verify, qword)) { rc = EFAULT; goto fail2; } } } /* Restore back to FULL buffer table mode */ EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1); EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword); /* * We don't need to reconfigure SRAM again because the API * requires efx_nic_fini() to be called after an sram test. */ return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); /* Restore back to FULL buffer table mode */ EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1); EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword); return (rc); } #endif /* EFSYS_OPT_DIAG */ #endif /* EFSYS_OPT_SIENA */ Property changes on: head/sys/dev/sfxge/common/siena_sram.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/common/siena_vpd.c =================================================================== --- head/sys/dev/sfxge/common/siena_vpd.c (revision 283513) +++ head/sys/dev/sfxge/common/siena_vpd.c (revision 283514) @@ -1,604 +1,613 @@ /*- - * Copyright 2009 Solarflare Communications Inc. All rights reserved. + * Copyright (c) 2009-2015 Solarflare Communications Inc. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include "efsys.h" #include "efx.h" #include "efx_types.h" #include "efx_regs.h" #include "efx_impl.h" #if EFSYS_OPT_VPD #if EFSYS_OPT_SIENA static __checkReturn int siena_vpd_get_static( __in efx_nic_t *enp, __in unsigned int partn, __deref_out_bcount_opt(*sizep) caddr_t *svpdp, __out size_t *sizep) { siena_mc_static_config_hdr_t *scfg; caddr_t svpd; size_t size; uint8_t cksum; unsigned int vpd_offset; unsigned int vpd_length; unsigned int hdr_length; unsigned int pos; unsigned int region; int rc; EFSYS_ASSERT(partn == MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 || partn == MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1); /* Allocate sufficient memory for the entire static cfg area */ if ((rc = siena_nvram_partn_size(enp, partn, &size)) != 0) goto fail1; EFSYS_KMEM_ALLOC(enp->en_esip, size, scfg); if (scfg == NULL) { rc = ENOMEM; goto fail2; } if ((rc = siena_nvram_partn_read(enp, partn, 0, (caddr_t)scfg, SIENA_NVRAM_CHUNK)) != 0) goto fail3; /* Verify the magic number */ if (EFX_DWORD_FIELD(scfg->magic, EFX_DWORD_0) != SIENA_MC_STATIC_CONFIG_MAGIC) { rc = EINVAL; goto fail4; } /* All future versions of the structure must be backwards compatable */ EFX_STATIC_ASSERT(SIENA_MC_STATIC_CONFIG_VERSION == 0); hdr_length = EFX_WORD_FIELD(scfg->length, EFX_WORD_0); vpd_offset = EFX_DWORD_FIELD(scfg->static_vpd_offset, EFX_DWORD_0); vpd_length = EFX_DWORD_FIELD(scfg->static_vpd_length, EFX_DWORD_0); /* Verify the hdr doesn't overflow the sector size */ if (hdr_length > size || vpd_offset > size || vpd_length > size || vpd_length + vpd_offset > size) { rc = EINVAL; goto fail5; } /* Read the remainder of scfg + static vpd */ region = vpd_offset + vpd_length; if (region > SIENA_NVRAM_CHUNK) { if ((rc = siena_nvram_partn_read(enp, partn, SIENA_NVRAM_CHUNK, (caddr_t)scfg + SIENA_NVRAM_CHUNK, region - SIENA_NVRAM_CHUNK)) != 0) goto fail6; } /* Verify checksum */ cksum = 0; for (pos = 0; pos < hdr_length; pos++) cksum += ((uint8_t *)scfg)[pos]; if (cksum != 0) { rc = EINVAL; goto fail7; } if (vpd_length == 0) svpd = NULL; else { /* Copy the vpd data out */ EFSYS_KMEM_ALLOC(enp->en_esip, vpd_length, svpd); if (svpd == NULL) { rc = ENOMEM; goto fail8; } memcpy(svpd, (caddr_t)scfg + vpd_offset, vpd_length); } EFSYS_KMEM_FREE(enp->en_esip, size, scfg); *svpdp = svpd; *sizep = vpd_length; return (0); fail8: EFSYS_PROBE(fail8); fail7: EFSYS_PROBE(fail7); fail6: EFSYS_PROBE(fail6); fail5: EFSYS_PROBE(fail5); fail4: EFSYS_PROBE(fail4); fail3: EFSYS_PROBE(fail3); -fail2: - EFSYS_PROBE(fail2); EFSYS_KMEM_FREE(enp->en_esip, size, scfg); +fail2: + EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_vpd_init( __in efx_nic_t *enp) { - efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip); + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); caddr_t svpd = NULL; unsigned partn; size_t size = 0; int rc; EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); partn = (emip->emi_port == 1) ? MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 : MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1; /* * We need the static VPD sector to present a unified static+dynamic * VPD, that is, basically on every read, write, verify cycle. Since * it should *never* change we can just cache it here. */ if ((rc = siena_vpd_get_static(enp, partn, &svpd, &size)) != 0) goto fail1; if (svpd != NULL && size > 0) { if ((rc = efx_vpd_hunk_verify(svpd, size, NULL)) != 0) goto fail2; } enp->en_u.siena.enu_svpd = svpd; enp->en_u.siena.enu_svpd_length = size; return (0); fail2: EFSYS_PROBE(fail2); EFSYS_KMEM_FREE(enp->en_esip, size, svpd); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_vpd_size( __in efx_nic_t *enp, __out size_t *sizep) { - efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip); + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); unsigned int partn; int rc; EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); /* * This function returns the total size the user should allocate * for all VPD operations. We've already cached the static vpd, * so we just need to return an upper bound on the dynamic vpd. * Since the dynamic_config structure can change under our feet, * (as version numbers are inserted), just be safe and return the * total size of the dynamic_config *sector* */ partn = (emip->emi_port == 1) ? MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 : MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1; if ((rc = siena_nvram_partn_size(enp, partn, sizep)) != 0) goto fail1; return (0); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_vpd_read( __in efx_nic_t *enp, __out_bcount(size) caddr_t data, __in size_t size) { - efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip); - siena_mc_dynamic_config_hdr_t *dcfg; + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + siena_mc_dynamic_config_hdr_t *dcfg = NULL; unsigned int vpd_length; unsigned int vpd_offset; unsigned int dcfg_partn; size_t dcfg_size; int rc; EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); dcfg_partn = (emip->emi_port == 1) ? MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 : MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1; if ((rc = siena_nvram_get_dynamic_cfg(enp, dcfg_partn, B_TRUE, &dcfg, &dcfg_size)) != 0) goto fail1; vpd_length = EFX_DWORD_FIELD(dcfg->dynamic_vpd_length, EFX_DWORD_0); vpd_offset = EFX_DWORD_FIELD(dcfg->dynamic_vpd_offset, EFX_DWORD_0); if (vpd_length > size) { rc = EFAULT; /* Invalid dcfg: header bigger than sector */ goto fail2; } EFSYS_ASSERT3U(vpd_length, <=, size); memcpy(data, (caddr_t)dcfg + vpd_offset, vpd_length); /* Pad data with all-1s, consistent with update operations */ memset(data + vpd_length, 0xff, size - vpd_length); EFSYS_KMEM_FREE(enp->en_esip, dcfg_size, dcfg); return (0); fail2: EFSYS_PROBE(fail2); EFSYS_KMEM_FREE(enp->en_esip, dcfg_size, dcfg); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_vpd_verify( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size) { efx_vpd_tag_t stag; efx_vpd_tag_t dtag; efx_vpd_keyword_t skey; efx_vpd_keyword_t dkey; unsigned int scont; unsigned int dcont; int rc; EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); /* * Strictly you could take the view that dynamic vpd is optional. * Instead, to conform more closely to the read/verify/reinit() * paradigm, we require dynamic vpd. siena_vpd_reinit() will * reinitialize it as required. */ if ((rc = efx_vpd_hunk_verify(data, size, NULL)) != 0) goto fail1; /* * Verify that there is no duplication between the static and * dynamic cfg sectors. */ if (enp->en_u.siena.enu_svpd_length == 0) goto done; dcont = 0; _NOTE(CONSTANTCONDITION) while (1) { if ((rc = efx_vpd_hunk_next(data, size, &dtag, &dkey, NULL, NULL, &dcont)) != 0) goto fail2; if (dcont == 0) break; scont = 0; _NOTE(CONSTANTCONDITION) while (1) { if ((rc = efx_vpd_hunk_next( enp->en_u.siena.enu_svpd, enp->en_u.siena.enu_svpd_length, &stag, &skey, NULL, NULL, &scont)) != 0) goto fail3; if (scont == 0) break; if (stag == dtag && skey == dkey) { rc = EEXIST; goto fail4; } } } done: return (0); fail4: EFSYS_PROBE(fail4); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_vpd_reinit( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size) { boolean_t wantpid; int rc; /* * Only create a PID if the dynamic cfg doesn't have one */ if (enp->en_u.siena.enu_svpd_length == 0) wantpid = B_TRUE; else { unsigned int offset; uint8_t length; rc = efx_vpd_hunk_get(enp->en_u.siena.enu_svpd, enp->en_u.siena.enu_svpd_length, EFX_VPD_ID, 0, &offset, &length); if (rc == 0) wantpid = B_FALSE; else if (rc == ENOENT) wantpid = B_TRUE; else goto fail1; } if ((rc = efx_vpd_hunk_reinit(data, size, wantpid)) != 0) goto fail2; return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_vpd_get( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size, __inout efx_vpd_value_t *evvp) { unsigned int offset; uint8_t length; int rc; EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); /* Attempt to satisfy the request from svpd first */ if (enp->en_u.siena.enu_svpd_length > 0) { if ((rc = efx_vpd_hunk_get(enp->en_u.siena.enu_svpd, enp->en_u.siena.enu_svpd_length, evvp->evv_tag, evvp->evv_keyword, &offset, &length)) == 0) { evvp->evv_length = length; memcpy(evvp->evv_value, enp->en_u.siena.enu_svpd + offset, length); return (0); } else if (rc != ENOENT) goto fail1; } /* And then from the provided data buffer */ if ((rc = efx_vpd_hunk_get(data, size, evvp->evv_tag, evvp->evv_keyword, &offset, &length)) != 0) goto fail2; evvp->evv_length = length; memcpy(evvp->evv_value, data + offset, length); return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_vpd_set( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size, __in efx_vpd_value_t *evvp) { int rc; EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); /* If the provided (tag,keyword) exists in svpd, then it is readonly */ if (enp->en_u.siena.enu_svpd_length > 0) { unsigned int offset; uint8_t length; if ((rc = efx_vpd_hunk_get(enp->en_u.siena.enu_svpd, enp->en_u.siena.enu_svpd_length, evvp->evv_tag, evvp->evv_keyword, &offset, &length)) == 0) { rc = EACCES; goto fail1; } } if ((rc = efx_vpd_hunk_set(data, size, evvp)) != 0) goto fail2; return (0); fail2: EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } __checkReturn int siena_vpd_next( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size, __out efx_vpd_value_t *evvp, __inout unsigned int *contp) { _NOTE(ARGUNUSED(enp, data, size, evvp, contp)) return (ENOTSUP); } __checkReturn int siena_vpd_write( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size) { - efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip); - siena_mc_dynamic_config_hdr_t *dcfg; + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + siena_mc_dynamic_config_hdr_t *dcfg = NULL; unsigned int vpd_offset; unsigned int dcfg_partn; unsigned int hdr_length; unsigned int pos; uint8_t cksum; size_t partn_size, dcfg_size; size_t vpd_length; int rc; EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); /* Determine total length of all tags */ if ((rc = efx_vpd_hunk_length(data, size, &vpd_length)) != 0) goto fail1; /* Lock dynamic config sector for write, and read structure only */ dcfg_partn = (emip->emi_port == 1) ? MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 : MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1; if ((rc = siena_nvram_partn_size(enp, dcfg_partn, &partn_size)) != 0) goto fail2; if ((rc = siena_nvram_partn_lock(enp, dcfg_partn)) != 0) - goto fail2; + goto fail3; if ((rc = siena_nvram_get_dynamic_cfg(enp, dcfg_partn, B_FALSE, &dcfg, &dcfg_size)) != 0) - goto fail3; + goto fail4; hdr_length = EFX_WORD_FIELD(dcfg->length, EFX_WORD_0); /* Allocated memory should have room for the new VPD */ if (hdr_length + vpd_length > dcfg_size) { rc = ENOSPC; - goto fail3; + goto fail5; } /* Copy in new vpd and update header */ vpd_offset = dcfg_size - vpd_length; EFX_POPULATE_DWORD_1(dcfg->dynamic_vpd_offset, EFX_DWORD_0, vpd_offset); memcpy((caddr_t)dcfg + vpd_offset, data, vpd_length); EFX_POPULATE_DWORD_1(dcfg->dynamic_vpd_length, EFX_DWORD_0, vpd_length); /* Update the checksum */ cksum = 0; for (pos = 0; pos < hdr_length; pos++) cksum += ((uint8_t *)dcfg)[pos]; dcfg->csum.eb_u8[0] -= cksum; /* Erase and write the new sector */ if ((rc = siena_nvram_partn_erase(enp, dcfg_partn, 0, partn_size)) != 0) - goto fail4; + goto fail6; /* Write out the new structure to nvram */ if ((rc = siena_nvram_partn_write(enp, dcfg_partn, 0, (caddr_t)dcfg, vpd_offset + vpd_length)) != 0) - goto fail5; + goto fail7; EFSYS_KMEM_FREE(enp->en_esip, dcfg_size, dcfg); siena_nvram_partn_unlock(enp, dcfg_partn); return (0); +fail7: + EFSYS_PROBE(fail7); +fail6: + EFSYS_PROBE(fail6); fail5: EFSYS_PROBE(fail5); + + EFSYS_KMEM_FREE(enp->en_esip, dcfg_size, dcfg); fail4: EFSYS_PROBE(fail4); + + siena_nvram_partn_unlock(enp, dcfg_partn); fail3: EFSYS_PROBE(fail3); - - EFSYS_KMEM_FREE(enp->en_esip, dcfg_size, dcfg); fail2: EFSYS_PROBE(fail2); - - siena_nvram_partn_unlock(enp, dcfg_partn); fail1: EFSYS_PROBE1(fail1, int, rc); return (rc); } void siena_vpd_fini( __in efx_nic_t *enp) { EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); if (enp->en_u.siena.enu_svpd_length > 0) { EFSYS_KMEM_FREE(enp->en_esip, enp->en_u.siena.enu_svpd_length, enp->en_u.siena.enu_svpd); enp->en_u.siena.enu_svpd = NULL; enp->en_u.siena.enu_svpd_length = 0; } } #endif /* EFSYS_OPT_SIENA */ #endif /* EFSYS_OPT_VPD */ Property changes on: head/sys/dev/sfxge/common/siena_vpd.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/sfxge.c =================================================================== --- head/sys/dev/sfxge/sfxge.c (revision 283513) +++ head/sys/dev/sfxge/sfxge.c (revision 283514) @@ -1,880 +1,1115 @@ /*- - * Copyright (c) 2010-2011 Solarflare Communications, Inc. + * Copyright (c) 2010-2015 Solarflare Communications Inc. * All rights reserved. * * This software was developed in part by Philip Paeps under contract for * Solarflare Communications, Inc. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include +#include #include #include #include #include #include #include #include #include #include "common/efx.h" #include "sfxge.h" #include "sfxge_rx.h" +#include "sfxge_ioc.h" #include "sfxge_version.h" #define SFXGE_CAP (IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM | \ IFCAP_RXCSUM | IFCAP_TXCSUM | \ IFCAP_RXCSUM_IPV6 | IFCAP_TXCSUM_IPV6 | \ IFCAP_TSO4 | IFCAP_TSO6 | \ IFCAP_JUMBO_MTU | \ IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWSTATS) #define SFXGE_CAP_ENABLE SFXGE_CAP #define SFXGE_CAP_FIXED (IFCAP_VLAN_MTU | \ IFCAP_JUMBO_MTU | IFCAP_LINKSTATE | IFCAP_HWSTATS) MALLOC_DEFINE(M_SFXGE, "sfxge", "Solarflare 10GigE driver"); SYSCTL_NODE(_hw, OID_AUTO, sfxge, CTLFLAG_RD, 0, "SFXGE driver parameters"); #define SFXGE_PARAM_RX_RING SFXGE_PARAM(rx_ring) static int sfxge_rx_ring_entries = SFXGE_NDESCS; TUNABLE_INT(SFXGE_PARAM_RX_RING, &sfxge_rx_ring_entries); SYSCTL_INT(_hw_sfxge, OID_AUTO, rx_ring, CTLFLAG_RDTUN, &sfxge_rx_ring_entries, 0, "Maximum number of descriptors in a receive ring"); #define SFXGE_PARAM_TX_RING SFXGE_PARAM(tx_ring) static int sfxge_tx_ring_entries = SFXGE_NDESCS; TUNABLE_INT(SFXGE_PARAM_TX_RING, &sfxge_tx_ring_entries); SYSCTL_INT(_hw_sfxge, OID_AUTO, tx_ring, CTLFLAG_RDTUN, &sfxge_tx_ring_entries, 0, "Maximum number of descriptors in a transmit ring"); static void sfxge_reset(void *arg, int npending); static int +sfxge_estimate_rsrc_limits(struct sfxge_softc *sc) +{ + efx_drv_limits_t limits; + int rc; + unsigned int evq_max; + uint32_t evq_allocated; + uint32_t rxq_allocated; + uint32_t txq_allocated; + + /* + * Limit the number of event queues to: + * - number of CPUs + * - hardwire maximum RSS channels + * - administratively specified maximum RSS channels + */ + evq_max = MIN(mp_ncpus, EFX_MAXRSS); + if (sc->max_rss_channels > 0) + evq_max = MIN(evq_max, sc->max_rss_channels); + + memset(&limits, 0, sizeof(limits)); + + limits.edl_min_evq_count = 1; + limits.edl_max_evq_count = evq_max; + limits.edl_min_txq_count = SFXGE_TXQ_NTYPES; + limits.edl_max_txq_count = evq_max + SFXGE_TXQ_NTYPES - 1; + limits.edl_min_rxq_count = 1; + limits.edl_max_rxq_count = evq_max; + + efx_nic_set_drv_limits(sc->enp, &limits); + + if ((rc = efx_nic_init(sc->enp)) != 0) + return (rc); + + rc = efx_nic_get_vi_pool(sc->enp, &evq_allocated, &rxq_allocated, + &txq_allocated); + if (rc != 0) { + efx_nic_fini(sc->enp); + return (rc); + } + + KASSERT(txq_allocated >= SFXGE_TXQ_NTYPES, + ("txq_allocated < SFXGE_TXQ_NTYPES")); + + sc->evq_max = MIN(evq_allocated, evq_max); + sc->evq_max = MIN(rxq_allocated, sc->evq_max); + sc->evq_max = MIN(txq_allocated - (SFXGE_TXQ_NTYPES - 1), + sc->evq_max); + + KASSERT(sc->evq_max <= evq_max, + ("allocated more than maximum requested")); + + /* + * NIC is kept initialized in the case of success to be able to + * initialize port to find out media types. + */ + return (0); +} + +static int +sfxge_set_drv_limits(struct sfxge_softc *sc) +{ + efx_drv_limits_t limits; + + memset(&limits, 0, sizeof(limits)); + + /* Limits are strict since take into account initial estimation */ + limits.edl_min_evq_count = limits.edl_max_evq_count = + sc->intr.n_alloc; + limits.edl_min_txq_count = limits.edl_max_txq_count = + sc->intr.n_alloc + SFXGE_TXQ_NTYPES - 1; + limits.edl_min_rxq_count = limits.edl_max_rxq_count = + sc->intr.n_alloc; + + return (efx_nic_set_drv_limits(sc->enp, &limits)); +} + +static int sfxge_start(struct sfxge_softc *sc) { int rc; SFXGE_ADAPTER_LOCK_ASSERT_OWNED(sc); if (sc->init_state == SFXGE_STARTED) return (0); if (sc->init_state != SFXGE_REGISTERED) { rc = EINVAL; goto fail; } + /* Set required resource limits */ + if ((rc = sfxge_set_drv_limits(sc)) != 0) + goto fail; + if ((rc = efx_nic_init(sc->enp)) != 0) goto fail; /* Start processing interrupts. */ if ((rc = sfxge_intr_start(sc)) != 0) goto fail2; /* Start processing events. */ if ((rc = sfxge_ev_start(sc)) != 0) goto fail3; + /* Fire up the port. */ + if ((rc = sfxge_port_start(sc)) != 0) + goto fail4; + /* Start the receiver side. */ if ((rc = sfxge_rx_start(sc)) != 0) - goto fail4; + goto fail5; /* Start the transmitter side. */ if ((rc = sfxge_tx_start(sc)) != 0) - goto fail5; - - /* Fire up the port. */ - if ((rc = sfxge_port_start(sc)) != 0) goto fail6; sc->init_state = SFXGE_STARTED; /* Tell the stack we're running. */ sc->ifnet->if_drv_flags |= IFF_DRV_RUNNING; sc->ifnet->if_drv_flags &= ~IFF_DRV_OACTIVE; return (0); fail6: - sfxge_tx_stop(sc); + sfxge_rx_stop(sc); fail5: - sfxge_rx_stop(sc); + sfxge_port_stop(sc); fail4: sfxge_ev_stop(sc); fail3: sfxge_intr_stop(sc); fail2: efx_nic_fini(sc->enp); fail: device_printf(sc->dev, "sfxge_start: %d\n", rc); return (rc); } static void sfxge_if_init(void *arg) { struct sfxge_softc *sc; sc = (struct sfxge_softc *)arg; SFXGE_ADAPTER_LOCK(sc); (void)sfxge_start(sc); SFXGE_ADAPTER_UNLOCK(sc); } static void sfxge_stop(struct sfxge_softc *sc) { SFXGE_ADAPTER_LOCK_ASSERT_OWNED(sc); if (sc->init_state != SFXGE_STARTED) return; sc->init_state = SFXGE_REGISTERED; - /* Stop the port. */ - sfxge_port_stop(sc); - /* Stop the transmitter. */ sfxge_tx_stop(sc); /* Stop the receiver. */ sfxge_rx_stop(sc); + /* Stop the port. */ + sfxge_port_stop(sc); + /* Stop processing events. */ sfxge_ev_stop(sc); /* Stop processing interrupts. */ sfxge_intr_stop(sc); efx_nic_fini(sc->enp); sc->ifnet->if_drv_flags &= ~IFF_DRV_RUNNING; } + static int +sfxge_vpd_ioctl(struct sfxge_softc *sc, sfxge_ioc_t *ioc) +{ + efx_vpd_value_t value; + int rc = 0; + + switch (ioc->u.vpd.op) { + case SFXGE_VPD_OP_GET_KEYWORD: + value.evv_tag = ioc->u.vpd.tag; + value.evv_keyword = ioc->u.vpd.keyword; + rc = efx_vpd_get(sc->enp, sc->vpd_data, sc->vpd_size, &value); + if (rc != 0) + break; + ioc->u.vpd.len = MIN(ioc->u.vpd.len, value.evv_length); + if (ioc->u.vpd.payload != 0) { + rc = copyout(value.evv_value, ioc->u.vpd.payload, + ioc->u.vpd.len); + } + break; + case SFXGE_VPD_OP_SET_KEYWORD: + if (ioc->u.vpd.len > sizeof(value.evv_value)) + return (EINVAL); + value.evv_tag = ioc->u.vpd.tag; + value.evv_keyword = ioc->u.vpd.keyword; + value.evv_length = ioc->u.vpd.len; + rc = copyin(ioc->u.vpd.payload, value.evv_value, value.evv_length); + if (rc != 0) + break; + rc = efx_vpd_set(sc->enp, sc->vpd_data, sc->vpd_size, &value); + if (rc != 0) + break; + rc = efx_vpd_verify(sc->enp, sc->vpd_data, sc->vpd_size); + if (rc != 0) + break; + rc = efx_vpd_write(sc->enp, sc->vpd_data, sc->vpd_size); + break; + default: + rc = EOPNOTSUPP; + break; + } + + return (rc); +} + +static int +sfxge_private_ioctl(struct sfxge_softc *sc, sfxge_ioc_t *ioc) +{ + switch (ioc->op) { + case SFXGE_MCDI_IOC: + return (sfxge_mcdi_ioctl(sc, ioc)); + case SFXGE_NVRAM_IOC: + return (sfxge_nvram_ioctl(sc, ioc)); + case SFXGE_VPD_IOC: + return (sfxge_vpd_ioctl(sc, ioc)); + default: + return (EOPNOTSUPP); + } +} + + +static int sfxge_if_ioctl(struct ifnet *ifp, unsigned long command, caddr_t data) { struct sfxge_softc *sc; struct ifreq *ifr; + sfxge_ioc_t ioc; int error; ifr = (struct ifreq *)data; sc = ifp->if_softc; error = 0; switch (command) { case SIOCSIFFLAGS: SFXGE_ADAPTER_LOCK(sc); if (ifp->if_flags & IFF_UP) { if (ifp->if_drv_flags & IFF_DRV_RUNNING) { if ((ifp->if_flags ^ sc->if_flags) & (IFF_PROMISC | IFF_ALLMULTI)) { sfxge_mac_filter_set(sc); } } else sfxge_start(sc); } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) sfxge_stop(sc); sc->if_flags = ifp->if_flags; SFXGE_ADAPTER_UNLOCK(sc); break; case SIOCSIFMTU: if (ifr->ifr_mtu == ifp->if_mtu) { /* Nothing to do */ error = 0; } else if (ifr->ifr_mtu > SFXGE_MAX_MTU) { error = EINVAL; } else if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { ifp->if_mtu = ifr->ifr_mtu; error = 0; } else { /* Restart required */ SFXGE_ADAPTER_LOCK(sc); sfxge_stop(sc); ifp->if_mtu = ifr->ifr_mtu; error = sfxge_start(sc); SFXGE_ADAPTER_UNLOCK(sc); if (error != 0) { ifp->if_flags &= ~IFF_UP; ifp->if_drv_flags &= ~IFF_DRV_RUNNING; if_down(ifp); } } break; case SIOCADDMULTI: case SIOCDELMULTI: if (ifp->if_drv_flags & IFF_DRV_RUNNING) sfxge_mac_filter_set(sc); break; case SIOCSIFCAP: { int reqcap = ifr->ifr_reqcap; int capchg_mask; SFXGE_ADAPTER_LOCK(sc); /* Capabilities to be changed in accordance with request */ capchg_mask = ifp->if_capenable ^ reqcap; /* * The networking core already rejects attempts to * enable capabilities we don't have. We still have * to reject attempts to disable capabilities that we * can't (yet) disable. */ KASSERT((reqcap & ~ifp->if_capabilities) == 0, - ("Unsupported capabilities %x requested %x vs %x", + ("Unsupported capabilities 0x%x requested 0x%x vs " + "supported 0x%x", reqcap & ~ifp->if_capabilities, reqcap , ifp->if_capabilities)); if (capchg_mask & SFXGE_CAP_FIXED) { error = EINVAL; SFXGE_ADAPTER_UNLOCK(sc); break; } /* Check request before any changes */ if ((capchg_mask & IFCAP_TSO4) && (reqcap & (IFCAP_TSO4 | IFCAP_TXCSUM)) == IFCAP_TSO4) { error = EAGAIN; SFXGE_ADAPTER_UNLOCK(sc); if_printf(ifp, "enable txcsum before tso4\n"); break; } if ((capchg_mask & IFCAP_TSO6) && (reqcap & (IFCAP_TSO6 | IFCAP_TXCSUM_IPV6)) == IFCAP_TSO6) { error = EAGAIN; SFXGE_ADAPTER_UNLOCK(sc); if_printf(ifp, "enable txcsum6 before tso6\n"); break; } if (reqcap & IFCAP_TXCSUM) { ifp->if_hwassist |= (CSUM_IP | CSUM_TCP | CSUM_UDP); } else { ifp->if_hwassist &= ~(CSUM_IP | CSUM_TCP | CSUM_UDP); if (reqcap & IFCAP_TSO4) { reqcap &= ~IFCAP_TSO4; if_printf(ifp, "tso4 disabled due to -txcsum\n"); } } if (reqcap & IFCAP_TXCSUM_IPV6) { ifp->if_hwassist |= (CSUM_TCP_IPV6 | CSUM_UDP_IPV6); } else { ifp->if_hwassist &= ~(CSUM_TCP_IPV6 | CSUM_UDP_IPV6); if (reqcap & IFCAP_TSO6) { reqcap &= ~IFCAP_TSO6; if_printf(ifp, "tso6 disabled due to -txcsum6\n"); } } /* * The kernel takes both IFCAP_TSOx and CSUM_TSO into * account before using TSO. So, we do not touch * checksum flags when IFCAP_TSOx is modified. * Note that CSUM_TSO is (CSUM_IP_TSO|CSUM_IP6_TSO), * but both bits are set in IPv4 and IPv6 mbufs. */ ifp->if_capenable = reqcap; SFXGE_ADAPTER_UNLOCK(sc); break; } case SIOCSIFMEDIA: case SIOCGIFMEDIA: error = ifmedia_ioctl(ifp, ifr, &sc->media, command); break; + case SIOCGPRIVATE_0: + error = priv_check(curthread, PRIV_DRIVER); + if (error != 0) + break; + error = copyin(ifr->ifr_data, &ioc, sizeof(ioc)); + if (error != 0) + return (error); + error = sfxge_private_ioctl(sc, &ioc); + if (error == 0) { + error = copyout(&ioc, ifr->ifr_data, sizeof(ioc)); + } + break; default: error = ether_ioctl(ifp, command, data); } return (error); } static void sfxge_ifnet_fini(struct ifnet *ifp) { struct sfxge_softc *sc = ifp->if_softc; SFXGE_ADAPTER_LOCK(sc); sfxge_stop(sc); SFXGE_ADAPTER_UNLOCK(sc); ifmedia_removeall(&sc->media); ether_ifdetach(ifp); if_free(ifp); } static int sfxge_ifnet_init(struct ifnet *ifp, struct sfxge_softc *sc) { const efx_nic_cfg_t *encp = efx_nic_cfg_get(sc->enp); device_t dev; int rc; dev = sc->dev; sc->ifnet = ifp; if_initname(ifp, device_get_name(dev), device_get_unit(dev)); ifp->if_init = sfxge_if_init; ifp->if_softc = sc; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_ioctl = sfxge_if_ioctl; ifp->if_capabilities = SFXGE_CAP; ifp->if_capenable = SFXGE_CAP_ENABLE; #ifdef SFXGE_LRO ifp->if_capabilities |= IFCAP_LRO; ifp->if_capenable |= IFCAP_LRO; #endif + if (encp->enc_hw_tx_insert_vlan_enabled) { + ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; + ifp->if_capenable |= IFCAP_VLAN_HWTAGGING; + } ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | CSUM_TCP_IPV6 | CSUM_UDP_IPV6; ether_ifattach(ifp, encp->enc_mac_addr); ifp->if_transmit = sfxge_if_transmit; ifp->if_qflush = sfxge_if_qflush; ifp->if_get_counter = sfxge_get_counter; + DBGPRINT(sc->dev, "ifmedia_init"); if ((rc = sfxge_port_ifmedia_init(sc)) != 0) goto fail; return (0); fail: ether_ifdetach(sc->ifnet); return (rc); } void sfxge_sram_buf_tbl_alloc(struct sfxge_softc *sc, size_t n, uint32_t *idp) { KASSERT(sc->buffer_table_next + n <= efx_nic_cfg_get(sc->enp)->enc_buftbl_limit, ("buffer table full")); *idp = sc->buffer_table_next; sc->buffer_table_next += n; } static int sfxge_bar_init(struct sfxge_softc *sc) { efsys_bar_t *esbp = &sc->bar; esbp->esb_rid = PCIR_BAR(EFX_MEM_BAR); if ((esbp->esb_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &esbp->esb_rid, RF_ACTIVE)) == NULL) { device_printf(sc->dev, "Cannot allocate BAR region %d\n", EFX_MEM_BAR); return (ENXIO); } esbp->esb_tag = rman_get_bustag(esbp->esb_res); esbp->esb_handle = rman_get_bushandle(esbp->esb_res); SFXGE_BAR_LOCK_INIT(esbp, device_get_nameunit(sc->dev)); return (0); } static void sfxge_bar_fini(struct sfxge_softc *sc) { efsys_bar_t *esbp = &sc->bar; bus_release_resource(sc->dev, SYS_RES_MEMORY, esbp->esb_rid, esbp->esb_res); SFXGE_BAR_LOCK_DESTROY(esbp); } static int sfxge_create(struct sfxge_softc *sc) { device_t dev; efx_nic_t *enp; int error; char rss_param_name[sizeof(SFXGE_PARAM(%d.max_rss_channels))]; dev = sc->dev; SFXGE_ADAPTER_LOCK_INIT(sc, device_get_nameunit(sc->dev)); sc->max_rss_channels = 0; snprintf(rss_param_name, sizeof(rss_param_name), SFXGE_PARAM(%d.max_rss_channels), (int)device_get_unit(dev)); TUNABLE_INT_FETCH(rss_param_name, &sc->max_rss_channels); sc->stats_node = SYSCTL_ADD_NODE( device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "stats", CTLFLAG_RD, NULL, "Statistics"); if (sc->stats_node == NULL) { error = ENOMEM; goto fail; } TASK_INIT(&sc->task_reset, 0, sfxge_reset, sc); (void) pci_enable_busmaster(dev); /* Initialize DMA mappings. */ + DBGPRINT(sc->dev, "dma_init..."); if ((error = sfxge_dma_init(sc)) != 0) goto fail; /* Map the device registers. */ + DBGPRINT(sc->dev, "bar_init..."); if ((error = sfxge_bar_init(sc)) != 0) goto fail; error = efx_family(pci_get_vendor(dev), pci_get_device(dev), &sc->family); KASSERT(error == 0, ("Family should be filtered by sfxge_probe()")); + DBGPRINT(sc->dev, "nic_create..."); + /* Create the common code nic object. */ SFXGE_EFSYS_LOCK_INIT(&sc->enp_lock, device_get_nameunit(sc->dev), "nic"); if ((error = efx_nic_create(sc->family, (efsys_identifier_t *)sc, &sc->bar, &sc->enp_lock, &enp)) != 0) goto fail3; sc->enp = enp; if (!ISP2(sfxge_rx_ring_entries) || - !(sfxge_rx_ring_entries & EFX_RXQ_NDESCS_MASK)) { + (sfxge_rx_ring_entries < EFX_RXQ_MINNDESCS) || + (sfxge_rx_ring_entries > EFX_RXQ_MAXNDESCS)) { log(LOG_ERR, "%s=%d must be power of 2 from %u to %u", SFXGE_PARAM_RX_RING, sfxge_rx_ring_entries, EFX_RXQ_MINNDESCS, EFX_RXQ_MAXNDESCS); error = EINVAL; goto fail_rx_ring_entries; } sc->rxq_entries = sfxge_rx_ring_entries; if (!ISP2(sfxge_tx_ring_entries) || - !(sfxge_tx_ring_entries & EFX_TXQ_NDESCS_MASK)) { + (sfxge_tx_ring_entries < EFX_TXQ_MINNDESCS) || + (sfxge_tx_ring_entries > EFX_TXQ_MAXNDESCS(efx_nic_cfg_get(enp)))) { log(LOG_ERR, "%s=%d must be power of 2 from %u to %u", SFXGE_PARAM_TX_RING, sfxge_tx_ring_entries, - EFX_TXQ_MINNDESCS, EFX_TXQ_MAXNDESCS); + EFX_TXQ_MINNDESCS, EFX_TXQ_MAXNDESCS(efx_nic_cfg_get(enp))); error = EINVAL; goto fail_tx_ring_entries; } sc->txq_entries = sfxge_tx_ring_entries; /* Initialize MCDI to talk to the microcontroller. */ + DBGPRINT(sc->dev, "mcdi_init..."); if ((error = sfxge_mcdi_init(sc)) != 0) goto fail4; /* Probe the NIC and build the configuration data area. */ + DBGPRINT(sc->dev, "nic_probe..."); if ((error = efx_nic_probe(enp)) != 0) goto fail5; SYSCTL_ADD_STRING(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "version", CTLFLAG_RD, SFXGE_VERSION_STRING, 0, "Driver version"); + SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), + OID_AUTO, "phy_type", CTLFLAG_RD, + NULL, efx_nic_cfg_get(enp)->enc_phy_type, + "PHY type"); + /* Initialize the NVRAM. */ + DBGPRINT(sc->dev, "nvram_init..."); if ((error = efx_nvram_init(enp)) != 0) goto fail6; /* Initialize the VPD. */ + DBGPRINT(sc->dev, "vpd_init..."); if ((error = efx_vpd_init(enp)) != 0) goto fail7; + efx_mcdi_new_epoch(enp); + /* Reset the NIC. */ + DBGPRINT(sc->dev, "nic_reset..."); if ((error = efx_nic_reset(enp)) != 0) goto fail8; /* Initialize buffer table allocation. */ sc->buffer_table_next = 0; + /* + * Guarantee minimum and estimate maximum number of event queues + * to take it into account when MSI-X interrupts are allocated. + * It initializes NIC and keeps it initialized on success. + */ + if ((error = sfxge_estimate_rsrc_limits(sc)) != 0) + goto fail8; + /* Set up interrupts. */ + DBGPRINT(sc->dev, "intr_init..."); if ((error = sfxge_intr_init(sc)) != 0) - goto fail8; + goto fail9; /* Initialize event processing state. */ + DBGPRINT(sc->dev, "ev_init..."); if ((error = sfxge_ev_init(sc)) != 0) goto fail11; + /* Initialize port state. */ + DBGPRINT(sc->dev, "port_init..."); + if ((error = sfxge_port_init(sc)) != 0) + goto fail12; + /* Initialize receive state. */ + DBGPRINT(sc->dev, "rx_init..."); if ((error = sfxge_rx_init(sc)) != 0) - goto fail12; + goto fail13; /* Initialize transmit state. */ + DBGPRINT(sc->dev, "tx_init..."); if ((error = sfxge_tx_init(sc)) != 0) - goto fail13; - - /* Initialize port state. */ - if ((error = sfxge_port_init(sc)) != 0) goto fail14; sc->init_state = SFXGE_INITIALIZED; + DBGPRINT(sc->dev, "success"); return (0); fail14: - sfxge_tx_fini(sc); + sfxge_rx_fini(sc); fail13: - sfxge_rx_fini(sc); + sfxge_port_fini(sc); fail12: sfxge_ev_fini(sc); fail11: sfxge_intr_fini(sc); +fail9: + efx_nic_fini(sc->enp); + fail8: efx_vpd_fini(enp); fail7: efx_nvram_fini(enp); fail6: efx_nic_unprobe(enp); fail5: sfxge_mcdi_fini(sc); fail4: fail_tx_ring_entries: fail_rx_ring_entries: sc->enp = NULL; efx_nic_destroy(enp); SFXGE_EFSYS_LOCK_DESTROY(&sc->enp_lock); fail3: sfxge_bar_fini(sc); (void) pci_disable_busmaster(sc->dev); fail: + DBGPRINT(sc->dev, "failed %d", error); sc->dev = NULL; SFXGE_ADAPTER_LOCK_DESTROY(sc); return (error); } static void sfxge_destroy(struct sfxge_softc *sc) { efx_nic_t *enp; - /* Clean up port state. */ - sfxge_port_fini(sc); - /* Clean up transmit state. */ sfxge_tx_fini(sc); /* Clean up receive state. */ sfxge_rx_fini(sc); + /* Clean up port state. */ + sfxge_port_fini(sc); + /* Clean up event processing state. */ sfxge_ev_fini(sc); /* Clean up interrupts. */ sfxge_intr_fini(sc); /* Tear down common code subsystems. */ efx_nic_reset(sc->enp); efx_vpd_fini(sc->enp); efx_nvram_fini(sc->enp); efx_nic_unprobe(sc->enp); /* Tear down MCDI. */ sfxge_mcdi_fini(sc); /* Destroy common code context. */ enp = sc->enp; sc->enp = NULL; efx_nic_destroy(enp); /* Free DMA memory. */ sfxge_dma_fini(sc); /* Free mapped BARs. */ sfxge_bar_fini(sc); (void) pci_disable_busmaster(sc->dev); taskqueue_drain(taskqueue_thread, &sc->task_reset); /* Destroy the softc lock. */ SFXGE_ADAPTER_LOCK_DESTROY(sc); } static int sfxge_vpd_handler(SYSCTL_HANDLER_ARGS) { struct sfxge_softc *sc = arg1; efx_vpd_value_t value; int rc; value.evv_tag = arg2 >> 16; value.evv_keyword = arg2 & 0xffff; if ((rc = efx_vpd_get(sc->enp, sc->vpd_data, sc->vpd_size, &value)) != 0) return (rc); return (SYSCTL_OUT(req, value.evv_value, value.evv_length)); } static void sfxge_vpd_try_add(struct sfxge_softc *sc, struct sysctl_oid_list *list, efx_vpd_tag_t tag, const char *keyword) { struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev); efx_vpd_value_t value; /* Check whether VPD tag/keyword is present */ value.evv_tag = tag; value.evv_keyword = EFX_VPD_KEYWORD(keyword[0], keyword[1]); if (efx_vpd_get(sc->enp, sc->vpd_data, sc->vpd_size, &value) != 0) return; SYSCTL_ADD_PROC( ctx, list, OID_AUTO, keyword, CTLTYPE_STRING|CTLFLAG_RD, sc, tag << 16 | EFX_VPD_KEYWORD(keyword[0], keyword[1]), sfxge_vpd_handler, "A", ""); } static int sfxge_vpd_init(struct sfxge_softc *sc) { struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev); struct sysctl_oid *vpd_node; struct sysctl_oid_list *vpd_list; char keyword[3]; efx_vpd_value_t value; int rc; if ((rc = efx_vpd_size(sc->enp, &sc->vpd_size)) != 0) goto fail; sc->vpd_data = malloc(sc->vpd_size, M_SFXGE, M_WAITOK); if ((rc = efx_vpd_read(sc->enp, sc->vpd_data, sc->vpd_size)) != 0) goto fail2; /* Copy ID (product name) into device description, and log it. */ value.evv_tag = EFX_VPD_ID; if (efx_vpd_get(sc->enp, sc->vpd_data, sc->vpd_size, &value) == 0) { value.evv_value[value.evv_length] = 0; device_set_desc_copy(sc->dev, value.evv_value); device_printf(sc->dev, "%s\n", value.evv_value); } vpd_node = SYSCTL_ADD_NODE( ctx, SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "vpd", CTLFLAG_RD, NULL, "Vital Product Data"); vpd_list = SYSCTL_CHILDREN(vpd_node); /* Add sysctls for all expected and any vendor-defined keywords. */ sfxge_vpd_try_add(sc, vpd_list, EFX_VPD_RO, "PN"); sfxge_vpd_try_add(sc, vpd_list, EFX_VPD_RO, "EC"); sfxge_vpd_try_add(sc, vpd_list, EFX_VPD_RO, "SN"); keyword[0] = 'V'; keyword[2] = 0; for (keyword[1] = '0'; keyword[1] <= '9'; keyword[1]++) sfxge_vpd_try_add(sc, vpd_list, EFX_VPD_RO, keyword); for (keyword[1] = 'A'; keyword[1] <= 'Z'; keyword[1]++) sfxge_vpd_try_add(sc, vpd_list, EFX_VPD_RO, keyword); return (0); fail2: free(sc->vpd_data, M_SFXGE); fail: return (rc); } static void sfxge_vpd_fini(struct sfxge_softc *sc) { free(sc->vpd_data, M_SFXGE); } static void sfxge_reset(void *arg, int npending) { struct sfxge_softc *sc; int rc; + unsigned attempt; (void)npending; sc = (struct sfxge_softc *)arg; SFXGE_ADAPTER_LOCK(sc); if (sc->init_state != SFXGE_STARTED) goto done; sfxge_stop(sc); efx_nic_reset(sc->enp); - if ((rc = sfxge_start(sc)) != 0) - device_printf(sc->dev, - "reset failed (%d); interface is now stopped\n", - rc); + for (attempt = 0; attempt < 3; ++attempt) { + if ((rc = sfxge_start(sc)) == 0) + goto done; + device_printf(sc->dev, "start on reset failed (%d)\n", rc); + DELAY(100000); + } + + device_printf(sc->dev, "reset failed; interface is now stopped\n"); + done: SFXGE_ADAPTER_UNLOCK(sc); } void sfxge_schedule_reset(struct sfxge_softc *sc) { taskqueue_enqueue(taskqueue_thread, &sc->task_reset); } static int sfxge_attach(device_t dev) { struct sfxge_softc *sc; struct ifnet *ifp; int error; sc = device_get_softc(dev); sc->dev = dev; /* Allocate ifnet. */ ifp = if_alloc(IFT_ETHER); if (ifp == NULL) { device_printf(dev, "Couldn't allocate ifnet\n"); error = ENOMEM; goto fail; } sc->ifnet = ifp; /* Initialize hardware. */ + DBGPRINT(sc->dev, "create nic"); if ((error = sfxge_create(sc)) != 0) goto fail2; /* Create the ifnet for the port. */ + DBGPRINT(sc->dev, "init ifnet"); if ((error = sfxge_ifnet_init(ifp, sc)) != 0) goto fail3; + DBGPRINT(sc->dev, "init vpd"); if ((error = sfxge_vpd_init(sc)) != 0) goto fail4; + /* + * NIC is initialized inside sfxge_create() and kept inialized + * to be able to initialize port to discover media types in + * sfxge_ifnet_init(). + */ + efx_nic_fini(sc->enp); + sc->init_state = SFXGE_REGISTERED; + DBGPRINT(sc->dev, "success"); return (0); fail4: sfxge_ifnet_fini(ifp); fail3: + efx_nic_fini(sc->enp); sfxge_destroy(sc); fail2: if_free(sc->ifnet); fail: + DBGPRINT(sc->dev, "failed %d", error); return (error); } static int sfxge_detach(device_t dev) { struct sfxge_softc *sc; sc = device_get_softc(dev); sfxge_vpd_fini(sc); /* Destroy the ifnet. */ sfxge_ifnet_fini(sc->ifnet); /* Tear down hardware. */ sfxge_destroy(sc); return (0); } static int sfxge_probe(device_t dev) { uint16_t pci_vendor_id; uint16_t pci_device_id; efx_family_t family; int rc; pci_vendor_id = pci_get_vendor(dev); pci_device_id = pci_get_device(dev); + DBGPRINT(dev, "PCI ID %04x:%04x", pci_vendor_id, pci_device_id); rc = efx_family(pci_vendor_id, pci_device_id, &family); - if (rc != 0) + if (rc != 0) { + DBGPRINT(dev, "efx_family fail %d", rc); return (ENXIO); + } - KASSERT(family == EFX_FAMILY_SIENA, ("impossible controller family")); - device_set_desc(dev, "Solarflare SFC9000 family"); - return (0); + if (family == EFX_FAMILY_SIENA) { + device_set_desc(dev, "Solarflare SFC9000 family"); + return (0); + } + + if (family == EFX_FAMILY_HUNTINGTON) { + device_set_desc(dev, "Solarflare SFC9100 family"); + return (0); + } + + DBGPRINT(dev, "impossible controller family %d", family); + return (ENXIO); } static device_method_t sfxge_methods[] = { DEVMETHOD(device_probe, sfxge_probe), DEVMETHOD(device_attach, sfxge_attach), DEVMETHOD(device_detach, sfxge_detach), DEVMETHOD_END }; static devclass_t sfxge_devclass; static driver_t sfxge_driver = { "sfxge", sfxge_methods, sizeof(struct sfxge_softc) }; DRIVER_MODULE(sfxge, pci, sfxge_driver, sfxge_devclass, 0, 0); Property changes on: head/sys/dev/sfxge/sfxge.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/sfxge.h =================================================================== --- head/sys/dev/sfxge/sfxge.h (revision 283513) +++ head/sys/dev/sfxge/sfxge.h (revision 283514) @@ -1,398 +1,432 @@ /*- - * Copyright (c) 2010-2011 Solarflare Communications, Inc. + * Copyright (c) 2010-2015 Solarflare Communications Inc. * All rights reserved. * * This software was developed in part by Philip Paeps under contract for * Solarflare Communications, Inc. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + * * $FreeBSD$ */ #ifndef _SFXGE_H #define _SFXGE_H #include #include -#include #include #include #include #include #include #include #include #include #include +#include "sfxge_ioc.h" + /* + * Debugging + */ +#if 0 +#define DBGPRINT(dev, fmt, args...) \ + device_printf(dev, "%s: " fmt "\n", __func__, ## args) +#else +#define DBGPRINT(dev, fmt, args...) +#endif + +/* * Backward-compatibility */ #ifndef CACHE_LINE_SIZE /* This should be right on most machines the driver will be used on, and * we needn't care too much about wasting a few KB per interface. */ #define CACHE_LINE_SIZE 128 #endif #ifndef IFCAP_LINKSTATE #define IFCAP_LINKSTATE 0 #endif #ifndef IFCAP_VLAN_HWTSO #define IFCAP_VLAN_HWTSO 0 #endif #ifndef IFM_10G_T #define IFM_10G_T IFM_UNKNOWN #endif #ifndef IFM_10G_KX4 #define IFM_10G_KX4 IFM_10G_CX4 #endif +#ifndef IFM_40G_CR4 +#define IFM_40G_CR4 IFM_UNKNOWN +#endif + #if (__FreeBSD_version >= 800501 && __FreeBSD_version < 900000) || \ __FreeBSD_version >= 900003 #define SFXGE_HAVE_DESCRIBE_INTR #endif #ifdef IFM_ETH_RXPAUSE #define SFXGE_HAVE_PAUSE_MEDIAOPTS #endif #ifndef CTLTYPE_U64 #define CTLTYPE_U64 CTLTYPE_QUAD #endif #include "sfxge_rx.h" #include "sfxge_tx.h" #define ROUNDUP_POW_OF_TWO(_n) (1ULL << flsl((_n) - 1)) #define SFXGE_IP_ALIGN 2 #define SFXGE_ETHERTYPE_LOOPBACK 0x9000 /* Xerox loopback */ enum sfxge_evq_state { SFXGE_EVQ_UNINITIALIZED = 0, SFXGE_EVQ_INITIALIZED, SFXGE_EVQ_STARTING, SFXGE_EVQ_STARTED }; #define SFXGE_EV_BATCH 16384 struct sfxge_evq { /* Structure members below are sorted by usage order */ struct sfxge_softc *sc; struct mtx lock; unsigned int index; enum sfxge_evq_state init_state; efsys_mem_t mem; efx_evq_t *common; unsigned int read_ptr; boolean_t exception; unsigned int rx_done; unsigned int tx_done; /* Linked list of TX queues with completions to process */ struct sfxge_txq *txq; struct sfxge_txq **txqs; /* Structure members not used on event processing path */ unsigned int buf_base_id; unsigned int entries; char lock_name[SFXGE_LOCK_NAME_MAX]; } __aligned(CACHE_LINE_SIZE); #define SFXGE_NDESCS 1024 #define SFXGE_MODERATION 30 enum sfxge_intr_state { SFXGE_INTR_UNINITIALIZED = 0, SFXGE_INTR_INITIALIZED, SFXGE_INTR_TESTING, SFXGE_INTR_STARTED }; struct sfxge_intr_hdl { int eih_rid; void *eih_tag; struct resource *eih_res; }; struct sfxge_intr { enum sfxge_intr_state state; struct resource *msix_res; struct sfxge_intr_hdl *table; int n_alloc; int type; efsys_mem_t status; uint32_t zero_count; }; enum sfxge_mcdi_state { SFXGE_MCDI_UNINITIALIZED = 0, SFXGE_MCDI_INITIALIZED, SFXGE_MCDI_BUSY, SFXGE_MCDI_COMPLETED }; struct sfxge_mcdi { struct mtx lock; - struct cv cv; + efsys_mem_t mem; enum sfxge_mcdi_state state; efx_mcdi_transport_t transport; /* Only used in debugging output */ char lock_name[SFXGE_LOCK_NAME_MAX]; }; struct sfxge_hw_stats { clock_t update_time; efsys_mem_t dma_buf; void *decode_buf; }; enum sfxge_port_state { SFXGE_PORT_UNINITIALIZED = 0, SFXGE_PORT_INITIALIZED, SFXGE_PORT_STARTED }; struct sfxge_port { struct sfxge_softc *sc; struct mtx lock; enum sfxge_port_state init_state; #ifndef SFXGE_HAVE_PAUSE_MEDIAOPTS unsigned int wanted_fc; #endif struct sfxge_hw_stats phy_stats; struct sfxge_hw_stats mac_stats; efx_link_mode_t link_mode; + uint8_t mcast_addrs[EFX_MAC_MULTICAST_LIST_MAX * + EFX_MAC_ADDR_LEN]; + unsigned int mcast_count; /* Only used in debugging output */ char lock_name[SFXGE_LOCK_NAME_MAX]; }; enum sfxge_softc_state { SFXGE_UNINITIALIZED = 0, SFXGE_INITIALIZED, SFXGE_REGISTERED, SFXGE_STARTED }; struct sfxge_softc { device_t dev; struct sx softc_lock; char softc_lock_name[SFXGE_LOCK_NAME_MAX]; enum sfxge_softc_state init_state; struct ifnet *ifnet; unsigned int if_flags; struct sysctl_oid *stats_node; struct sysctl_oid *txqs_node; struct task task_reset; efx_family_t family; caddr_t vpd_data; size_t vpd_size; efx_nic_t *enp; efsys_lock_t enp_lock; unsigned int rxq_entries; unsigned int txq_entries; bus_dma_tag_t parent_dma_tag; efsys_bar_t bar; struct sfxge_intr intr; struct sfxge_mcdi mcdi; struct sfxge_port port; uint32_t buffer_table_next; struct sfxge_evq *evq[SFXGE_RX_SCALE_MAX]; unsigned int ev_moderation; #if EFSYS_OPT_QSTATS clock_t ev_stats_update_time; uint64_t ev_stats[EV_NQSTATS]; #endif unsigned int max_rss_channels; uma_zone_t rxq_cache; struct sfxge_rxq *rxq[SFXGE_RX_SCALE_MAX]; unsigned int rx_indir_table[SFXGE_RX_SCALE_MAX]; struct sfxge_txq *txq[SFXGE_TXQ_NTYPES + SFXGE_RX_SCALE_MAX]; struct ifmedia media; size_t rx_prefix_size; size_t rx_buffer_size; + size_t rx_buffer_align; uma_zone_t rx_buffer_zone; + unsigned int evq_max; unsigned int evq_count; unsigned int rxq_count; unsigned int txq_count; + + int tso_fw_assisted; }; #define SFXGE_LINK_UP(sc) ((sc)->port.link_mode != EFX_LINK_DOWN) #define SFXGE_RUNNING(sc) ((sc)->ifnet->if_drv_flags & IFF_DRV_RUNNING) #define SFXGE_PARAM(_name) "hw.sfxge." #_name SYSCTL_DECL(_hw_sfxge); /* * From sfxge.c. */ extern void sfxge_schedule_reset(struct sfxge_softc *sc); extern void sfxge_sram_buf_tbl_alloc(struct sfxge_softc *sc, size_t n, uint32_t *idp); /* * From sfxge_dma.c. */ extern int sfxge_dma_init(struct sfxge_softc *sc); extern void sfxge_dma_fini(struct sfxge_softc *sc); extern int sfxge_dma_alloc(struct sfxge_softc *sc, bus_size_t len, - efsys_mem_t *esmp); + efsys_mem_t *esmp); extern void sfxge_dma_free(efsys_mem_t *esmp); extern int sfxge_dma_map_sg_collapse(bus_dma_tag_t tag, bus_dmamap_t map, - struct mbuf **mp, bus_dma_segment_t *segs, int *nsegs, int maxsegs); + struct mbuf **mp, + bus_dma_segment_t *segs, + int *nsegs, int maxsegs); /* * From sfxge_ev.c. */ extern int sfxge_ev_init(struct sfxge_softc *sc); extern void sfxge_ev_fini(struct sfxge_softc *sc); extern int sfxge_ev_start(struct sfxge_softc *sc); extern void sfxge_ev_stop(struct sfxge_softc *sc); extern int sfxge_ev_qpoll(struct sfxge_evq *evq); /* * From sfxge_intr.c. */ extern int sfxge_intr_init(struct sfxge_softc *sc); extern void sfxge_intr_fini(struct sfxge_softc *sc); extern int sfxge_intr_start(struct sfxge_softc *sc); extern void sfxge_intr_stop(struct sfxge_softc *sc); /* * From sfxge_mcdi.c. */ extern int sfxge_mcdi_init(struct sfxge_softc *sc); extern void sfxge_mcdi_fini(struct sfxge_softc *sc); +extern int sfxge_mcdi_ioctl(struct sfxge_softc *sc, sfxge_ioc_t *ip); /* + * From sfxge_nvram.c. + */ +extern int sfxge_nvram_ioctl(struct sfxge_softc *sc, sfxge_ioc_t *ip); + +/* * From sfxge_port.c. */ extern int sfxge_port_init(struct sfxge_softc *sc); extern void sfxge_port_fini(struct sfxge_softc *sc); extern int sfxge_port_start(struct sfxge_softc *sc); extern void sfxge_port_stop(struct sfxge_softc *sc); extern void sfxge_mac_link_update(struct sfxge_softc *sc, - efx_link_mode_t mode); + efx_link_mode_t mode); extern int sfxge_mac_filter_set(struct sfxge_softc *sc); extern int sfxge_port_ifmedia_init(struct sfxge_softc *sc); extern uint64_t sfxge_get_counter(struct ifnet *ifp, ift_counter c); #define SFXGE_MAX_MTU (9 * 1024) #define SFXGE_ADAPTER_LOCK_INIT(_sc, _ifname) \ do { \ struct sfxge_softc *__sc = (_sc); \ \ snprintf((__sc)->softc_lock_name, \ sizeof((__sc)->softc_lock_name), \ "%s:softc", (_ifname)); \ sx_init(&(__sc)->softc_lock, (__sc)->softc_lock_name); \ } while (B_FALSE) #define SFXGE_ADAPTER_LOCK_DESTROY(_sc) \ sx_destroy(&(_sc)->softc_lock) #define SFXGE_ADAPTER_LOCK(_sc) \ sx_xlock(&(_sc)->softc_lock) #define SFXGE_ADAPTER_UNLOCK(_sc) \ sx_xunlock(&(_sc)->softc_lock) #define SFXGE_ADAPTER_LOCK_ASSERT_OWNED(_sc) \ sx_assert(&(_sc)->softc_lock, LA_XLOCKED) #define SFXGE_PORT_LOCK_INIT(_port, _ifname) \ do { \ struct sfxge_port *__port = (_port); \ \ snprintf((__port)->lock_name, \ sizeof((__port)->lock_name), \ "%s:port", (_ifname)); \ mtx_init(&(__port)->lock, (__port)->lock_name, \ NULL, MTX_DEF); \ } while (B_FALSE) #define SFXGE_PORT_LOCK_DESTROY(_port) \ mtx_destroy(&(_port)->lock) #define SFXGE_PORT_LOCK(_port) \ mtx_lock(&(_port)->lock) #define SFXGE_PORT_UNLOCK(_port) \ mtx_unlock(&(_port)->lock) #define SFXGE_PORT_LOCK_ASSERT_OWNED(_port) \ mtx_assert(&(_port)->lock, MA_OWNED) #define SFXGE_MCDI_LOCK_INIT(_mcdi, _ifname) \ do { \ struct sfxge_mcdi *__mcdi = (_mcdi); \ \ snprintf((__mcdi)->lock_name, \ sizeof((__mcdi)->lock_name), \ "%s:mcdi", (_ifname)); \ mtx_init(&(__mcdi)->lock, (__mcdi)->lock_name, \ NULL, MTX_DEF); \ } while (B_FALSE) #define SFXGE_MCDI_LOCK_DESTROY(_mcdi) \ mtx_destroy(&(_mcdi)->lock) #define SFXGE_MCDI_LOCK(_mcdi) \ mtx_lock(&(_mcdi)->lock) #define SFXGE_MCDI_UNLOCK(_mcdi) \ mtx_unlock(&(_mcdi)->lock) #define SFXGE_MCDI_LOCK_ASSERT_OWNED(_mcdi) \ mtx_assert(&(_mcdi)->lock, MA_OWNED) #define SFXGE_EVQ_LOCK_INIT(_evq, _ifname, _evq_index) \ do { \ struct sfxge_evq *__evq = (_evq); \ \ snprintf((__evq)->lock_name, \ sizeof((__evq)->lock_name), \ "%s:evq%u", (_ifname), (_evq_index)); \ mtx_init(&(__evq)->lock, (__evq)->lock_name, \ NULL, MTX_DEF); \ } while (B_FALSE) #define SFXGE_EVQ_LOCK_DESTROY(_evq) \ mtx_destroy(&(_evq)->lock) #define SFXGE_EVQ_LOCK(_evq) \ mtx_lock(&(_evq)->lock) #define SFXGE_EVQ_UNLOCK(_evq) \ mtx_unlock(&(_evq)->lock) #define SFXGE_EVQ_LOCK_ASSERT_OWNED(_evq) \ mtx_assert(&(_evq)->lock, MA_OWNED) #endif /* _SFXGE_H */ Property changes on: head/sys/dev/sfxge/sfxge.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/sfxge_dma.c =================================================================== --- head/sys/dev/sfxge/sfxge_dma.c (revision 283513) +++ head/sys/dev/sfxge/sfxge_dma.c (revision 283514) @@ -1,211 +1,216 @@ /*- - * Copyright (c) 2010-2011 Solarflare Communications, Inc. + * Copyright (c) 2010-2015 Solarflare Communications Inc. * All rights reserved. * * This software was developed in part by Philip Paeps under contract for * Solarflare Communications, Inc. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include "common/efx.h" #include "sfxge.h" static void sfxge_dma_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) { bus_addr_t *addr; addr = arg; if (error != 0) { *addr = 0; return; } *addr = segs[0].ds_addr; } int sfxge_dma_map_sg_collapse(bus_dma_tag_t tag, bus_dmamap_t map, - struct mbuf **mp, bus_dma_segment_t *segs, int *nsegs, int maxsegs) + struct mbuf **mp, bus_dma_segment_t *segs, + int *nsegs, int maxsegs) { bus_dma_segment_t *psegs; struct mbuf *m; int seg_count; int defragged; int err; m = *mp; defragged = err = seg_count = 0; KASSERT(m->m_pkthdr.len, ("packet has zero header length")); retry: psegs = segs; seg_count = 0; if (m->m_next == NULL) { sfxge_map_mbuf_fast(tag, map, m, segs); *nsegs = 1; return (0); } #if defined(__i386__) || defined(__amd64__) while (m != NULL && seg_count < maxsegs) { /* * firmware doesn't like empty segments */ if (m->m_len != 0) { seg_count++; sfxge_map_mbuf_fast(tag, map, m, psegs); psegs++; } m = m->m_next; } #else err = bus_dmamap_load_mbuf_sg(tag, map, *mp, segs, &seg_count, 0); #endif if (seg_count == 0) { err = EFBIG; goto err_out; } else if (err == EFBIG || seg_count >= maxsegs) { if (!defragged) { m = m_defrag(*mp, M_NOWAIT); if (m == NULL) { err = ENOBUFS; goto err_out; } *mp = m; defragged = 1; goto retry; } err = EFBIG; goto err_out; } *nsegs = seg_count; err_out: return (err); } void sfxge_dma_free(efsys_mem_t *esmp) { bus_dmamap_unload(esmp->esm_tag, esmp->esm_map); bus_dmamem_free(esmp->esm_tag, esmp->esm_base, esmp->esm_map); bus_dma_tag_destroy(esmp->esm_tag); esmp->esm_addr = 0; esmp->esm_base = NULL; } int sfxge_dma_alloc(struct sfxge_softc *sc, bus_size_t len, efsys_mem_t *esmp) { void *vaddr; /* Create the child DMA tag. */ if (bus_dma_tag_create(sc->parent_dma_tag, PAGE_SIZE, 0, MIN(0x3FFFFFFFFFFFUL, BUS_SPACE_MAXADDR), BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, &esmp->esm_tag) != 0) { device_printf(sc->dev, "Couldn't allocate txq DMA tag\n"); goto fail_tag_create; } /* Allocate kernel memory. */ if (bus_dmamem_alloc(esmp->esm_tag, (void **)&vaddr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &esmp->esm_map) != 0) { device_printf(sc->dev, "Couldn't allocate DMA memory\n"); goto fail_alloc; } /* Load map into device memory. */ if (bus_dmamap_load(esmp->esm_tag, esmp->esm_map, vaddr, len, sfxge_dma_cb, &esmp->esm_addr, 0) != 0) { device_printf(sc->dev, "Couldn't load DMA mapping\n"); goto fail_load; } /* * The callback gets error information about the mapping * and will have set esm_addr to 0 if something went * wrong. */ if (esmp->esm_addr == 0) goto fail_load_check; esmp->esm_base = vaddr; return (0); fail_load_check: fail_load: bus_dmamem_free(esmp->esm_tag, vaddr, esmp->esm_map); fail_alloc: bus_dma_tag_destroy(esmp->esm_tag); fail_tag_create: return (ENOMEM); } void sfxge_dma_fini(struct sfxge_softc *sc) { bus_dma_tag_destroy(sc->parent_dma_tag); } int sfxge_dma_init(struct sfxge_softc *sc) { /* Create the parent dma tag. */ if (bus_dma_tag_create(bus_get_dma_tag(sc->dev), /* parent */ 1, 0, /* algnmnt, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ BUS_SPACE_UNRESTRICTED, /* nsegments */ BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lock, lockarg */ &sc->parent_dma_tag) != 0) { device_printf(sc->dev, "Cannot allocate parent DMA tag\n"); return (ENOMEM); } return (0); } Property changes on: head/sys/dev/sfxge/sfxge_dma.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/sfxge_ev.c =================================================================== --- head/sys/dev/sfxge/sfxge_ev.c (revision 283513) +++ head/sys/dev/sfxge/sfxge_ev.c (revision 283514) @@ -1,927 +1,968 @@ /*- - * Copyright (c) 2010-2011 Solarflare Communications, Inc. + * Copyright (c) 2010-2015 Solarflare Communications Inc. * All rights reserved. * * This software was developed in part by Philip Paeps under contract for * Solarflare Communications, Inc. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include "common/efx.h" #include "sfxge.h" static void sfxge_ev_qcomplete(struct sfxge_evq *evq, boolean_t eop) { struct sfxge_softc *sc; unsigned int index; struct sfxge_rxq *rxq; struct sfxge_txq *txq; SFXGE_EVQ_LOCK_ASSERT_OWNED(evq); sc = evq->sc; index = evq->index; rxq = sc->rxq[index]; if ((txq = evq->txq) != NULL) { evq->txq = NULL; evq->txqs = &(evq->txq); do { struct sfxge_txq *next; next = txq->next; txq->next = NULL; KASSERT(txq->evq_index == index, ("txq->evq_index != index")); if (txq->pending != txq->completed) sfxge_tx_qcomplete(txq, evq); txq = next; } while (txq != NULL); } if (rxq->pending != rxq->completed) sfxge_rx_qcomplete(rxq, eop); } static boolean_t sfxge_ev_rx(void *arg, uint32_t label, uint32_t id, uint32_t size, - uint16_t flags) + uint16_t flags) { struct sfxge_evq *evq; struct sfxge_softc *sc; struct sfxge_rxq *rxq; - unsigned int expected; + unsigned int stop; + unsigned int delta; struct sfxge_rx_sw_desc *rx_desc; evq = arg; SFXGE_EVQ_LOCK_ASSERT_OWNED(evq); sc = evq->sc; if (evq->exception) goto done; rxq = sc->rxq[label]; KASSERT(rxq != NULL, ("rxq == NULL")); KASSERT(evq->index == rxq->index, ("evq->index != rxq->index")); if (__predict_false(rxq->init_state != SFXGE_RXQ_STARTED)) goto done; - expected = rxq->pending++ & rxq->ptr_mask; - if (id != expected) { - evq->exception = B_TRUE; + stop = (id + 1) & rxq->ptr_mask; + id = rxq->pending & rxq->ptr_mask; + delta = (stop >= id) ? (stop - id) : (rxq->entries - id + stop); + rxq->pending += delta; - device_printf(sc->dev, "RX completion out of order" - " (id=%#x expected=%#x flags=%#x); resetting\n", - id, expected, flags); - sfxge_schedule_reset(sc); + if (delta != 1) { + if ((!efx_nic_cfg_get(sc->enp)->enc_rx_batching_enabled) || + (delta <= 0) || + (delta > efx_nic_cfg_get(sc->enp)->enc_rx_batch_max)) { + evq->exception = B_TRUE; - goto done; + device_printf(sc->dev, "RX completion out of order" + " (id=%#x delta=%u flags=%#x); resetting\n", + id, delta, flags); + sfxge_schedule_reset(sc); + + goto done; + } } rx_desc = &rxq->queue[id]; - KASSERT(rx_desc->flags == EFX_DISCARD, - ("rx_desc->flags != EFX_DISCARD")); - rx_desc->flags = flags; - - KASSERT(size < (1 << 16), ("size > (1 << 16)")); - rx_desc->size = (uint16_t)size; prefetch_read_many(rx_desc->mbuf); + for (; id != stop; id = (id + 1) & rxq->ptr_mask) { + rx_desc = &rxq->queue[id]; + KASSERT(rx_desc->flags == EFX_DISCARD, + ("rx_desc->flags != EFX_DISCARD")); + rx_desc->flags = flags; + + KASSERT(size < (1 << 16), ("size > (1 << 16)")); + rx_desc->size = (uint16_t)size; + } + evq->rx_done++; if (rxq->pending - rxq->completed >= SFXGE_RX_BATCH) sfxge_ev_qcomplete(evq, B_FALSE); done: return (evq->rx_done >= SFXGE_EV_BATCH); } static boolean_t sfxge_ev_exception(void *arg, uint32_t code, uint32_t data) { struct sfxge_evq *evq; struct sfxge_softc *sc; evq = (struct sfxge_evq *)arg; SFXGE_EVQ_LOCK_ASSERT_OWNED(evq); sc = evq->sc; + DBGPRINT(sc->dev, "[%d] %s", evq->index, + (code == EFX_EXCEPTION_RX_RECOVERY) ? "RX_RECOVERY" : + (code == EFX_EXCEPTION_RX_DSC_ERROR) ? "RX_DSC_ERROR" : + (code == EFX_EXCEPTION_TX_DSC_ERROR) ? "TX_DSC_ERROR" : + (code == EFX_EXCEPTION_UNKNOWN_SENSOREVT) ? "UNKNOWN_SENSOREVT" : + (code == EFX_EXCEPTION_FWALERT_SRAM) ? "FWALERT_SRAM" : + (code == EFX_EXCEPTION_UNKNOWN_FWALERT) ? "UNKNOWN_FWALERT" : + (code == EFX_EXCEPTION_RX_ERROR) ? "RX_ERROR" : + (code == EFX_EXCEPTION_TX_ERROR) ? "TX_ERROR" : + (code == EFX_EXCEPTION_EV_ERROR) ? "EV_ERROR" : + "UNKNOWN"); + evq->exception = B_TRUE; if (code != EFX_EXCEPTION_UNKNOWN_SENSOREVT) { device_printf(sc->dev, "hardware exception (code=%u); resetting\n", code); sfxge_schedule_reset(sc); } return (B_FALSE); } static boolean_t sfxge_ev_rxq_flush_done(void *arg, uint32_t rxq_index) { struct sfxge_evq *evq; struct sfxge_softc *sc; struct sfxge_rxq *rxq; unsigned int index; unsigned int label; uint16_t magic; evq = (struct sfxge_evq *)arg; SFXGE_EVQ_LOCK_ASSERT_OWNED(evq); sc = evq->sc; rxq = sc->rxq[rxq_index]; KASSERT(rxq != NULL, ("rxq == NULL")); /* Resend a software event on the correct queue */ index = rxq->index; + if (index == evq->index) { + sfxge_rx_qflush_done(rxq); + return (B_FALSE); + } + evq = sc->evq[index]; label = rxq_index; KASSERT((label & SFXGE_MAGIC_DMAQ_LABEL_MASK) == label, ("(label & SFXGE_MAGIC_DMAQ_LABEL_MASK) != level")); magic = SFXGE_MAGIC_RX_QFLUSH_DONE | label; KASSERT(evq->init_state == SFXGE_EVQ_STARTED, ("evq not started")); efx_ev_qpost(evq->common, magic); return (B_FALSE); } static boolean_t sfxge_ev_rxq_flush_failed(void *arg, uint32_t rxq_index) { struct sfxge_evq *evq; struct sfxge_softc *sc; struct sfxge_rxq *rxq; unsigned int index; unsigned int label; uint16_t magic; evq = (struct sfxge_evq *)arg; SFXGE_EVQ_LOCK_ASSERT_OWNED(evq); sc = evq->sc; rxq = sc->rxq[rxq_index]; KASSERT(rxq != NULL, ("rxq == NULL")); /* Resend a software event on the correct queue */ index = rxq->index; evq = sc->evq[index]; label = rxq_index; KASSERT((label & SFXGE_MAGIC_DMAQ_LABEL_MASK) == label, ("(label & SFXGE_MAGIC_DMAQ_LABEL_MASK) != label")); magic = SFXGE_MAGIC_RX_QFLUSH_FAILED | label; KASSERT(evq->init_state == SFXGE_EVQ_STARTED, ("evq not started")); efx_ev_qpost(evq->common, magic); return (B_FALSE); } static struct sfxge_txq * sfxge_get_txq_by_label(struct sfxge_evq *evq, enum sfxge_txq_type label) { unsigned int index; KASSERT((evq->index == 0 && label < SFXGE_TXQ_NTYPES) || (label == SFXGE_TXQ_IP_TCP_UDP_CKSUM), ("unexpected txq label")); index = (evq->index == 0) ? label : (evq->index - 1 + SFXGE_TXQ_NTYPES); return (evq->sc->txq[index]); } static boolean_t sfxge_ev_tx(void *arg, uint32_t label, uint32_t id) { struct sfxge_evq *evq; struct sfxge_txq *txq; unsigned int stop; unsigned int delta; evq = (struct sfxge_evq *)arg; SFXGE_EVQ_LOCK_ASSERT_OWNED(evq); txq = sfxge_get_txq_by_label(evq, label); KASSERT(txq != NULL, ("txq == NULL")); KASSERT(evq->index == txq->evq_index, ("evq->index != txq->evq_index")); if (__predict_false(txq->init_state != SFXGE_TXQ_STARTED)) goto done; stop = (id + 1) & txq->ptr_mask; id = txq->pending & txq->ptr_mask; delta = (stop >= id) ? (stop - id) : (txq->entries - id + stop); txq->pending += delta; evq->tx_done++; if (txq->next == NULL && evq->txqs != &(txq->next)) { *(evq->txqs) = txq; evq->txqs = &(txq->next); } if (txq->pending - txq->completed >= SFXGE_TX_BATCH) sfxge_tx_qcomplete(txq, evq); done: return (evq->tx_done >= SFXGE_EV_BATCH); } static boolean_t sfxge_ev_txq_flush_done(void *arg, uint32_t txq_index) { struct sfxge_evq *evq; struct sfxge_softc *sc; struct sfxge_txq *txq; unsigned int label; uint16_t magic; evq = (struct sfxge_evq *)arg; SFXGE_EVQ_LOCK_ASSERT_OWNED(evq); sc = evq->sc; txq = sc->txq[txq_index]; KASSERT(txq != NULL, ("txq == NULL")); KASSERT(txq->init_state == SFXGE_TXQ_INITIALIZED, ("txq not initialized")); + if (txq->evq_index == evq->index) { + sfxge_tx_qflush_done(txq); + return (B_FALSE); + } + /* Resend a software event on the correct queue */ evq = sc->evq[txq->evq_index]; label = txq->type; KASSERT((label & SFXGE_MAGIC_DMAQ_LABEL_MASK) == label, ("(label & SFXGE_MAGIC_DMAQ_LABEL_MASK) != label")); magic = SFXGE_MAGIC_TX_QFLUSH_DONE | label; KASSERT(evq->init_state == SFXGE_EVQ_STARTED, ("evq not started")); efx_ev_qpost(evq->common, magic); return (B_FALSE); } static boolean_t sfxge_ev_software(void *arg, uint16_t magic) { struct sfxge_evq *evq; struct sfxge_softc *sc; unsigned int label; evq = (struct sfxge_evq *)arg; SFXGE_EVQ_LOCK_ASSERT_OWNED(evq); sc = evq->sc; label = magic & SFXGE_MAGIC_DMAQ_LABEL_MASK; magic &= ~SFXGE_MAGIC_DMAQ_LABEL_MASK; switch (magic) { case SFXGE_MAGIC_RX_QFLUSH_DONE: { struct sfxge_rxq *rxq = sc->rxq[label]; KASSERT(rxq != NULL, ("rxq == NULL")); KASSERT(evq->index == rxq->index, ("evq->index != rxq->index")); sfxge_rx_qflush_done(rxq); break; } case SFXGE_MAGIC_RX_QFLUSH_FAILED: { struct sfxge_rxq *rxq = sc->rxq[label]; KASSERT(rxq != NULL, ("rxq == NULL")); KASSERT(evq->index == rxq->index, ("evq->index != rxq->index")); sfxge_rx_qflush_failed(rxq); break; } case SFXGE_MAGIC_RX_QREFILL: { struct sfxge_rxq *rxq = sc->rxq[label]; KASSERT(rxq != NULL, ("rxq == NULL")); KASSERT(evq->index == rxq->index, ("evq->index != rxq->index")); sfxge_rx_qrefill(rxq); break; } case SFXGE_MAGIC_TX_QFLUSH_DONE: { struct sfxge_txq *txq = sfxge_get_txq_by_label(evq, label); KASSERT(txq != NULL, ("txq == NULL")); KASSERT(evq->index == txq->evq_index, ("evq->index != txq->evq_index")); sfxge_tx_qflush_done(txq); break; } default: break; } return (B_FALSE); } static boolean_t sfxge_ev_sram(void *arg, uint32_t code) { (void)arg; (void)code; switch (code) { case EFX_SRAM_UPDATE: EFSYS_PROBE(sram_update); break; case EFX_SRAM_CLEAR: EFSYS_PROBE(sram_clear); break; case EFX_SRAM_ILLEGAL_CLEAR: EFSYS_PROBE(sram_illegal_clear); break; default: KASSERT(B_FALSE, ("Impossible SRAM event")); break; } return (B_FALSE); } static boolean_t sfxge_ev_timer(void *arg, uint32_t index) { (void)arg; (void)index; return (B_FALSE); } static boolean_t sfxge_ev_wake_up(void *arg, uint32_t index) { (void)arg; (void)index; return (B_FALSE); } #if EFSYS_OPT_QSTATS static void sfxge_ev_stat_update(struct sfxge_softc *sc) { struct sfxge_evq *evq; unsigned int index; clock_t now; SFXGE_ADAPTER_LOCK(sc); if (__predict_false(sc->evq[0]->init_state != SFXGE_EVQ_STARTED)) goto out; now = ticks; if (now - sc->ev_stats_update_time < hz) goto out; sc->ev_stats_update_time = now; /* Add event counts from each event queue in turn */ for (index = 0; index < sc->evq_count; index++) { evq = sc->evq[index]; SFXGE_EVQ_LOCK(evq); efx_ev_qstats_update(evq->common, sc->ev_stats); SFXGE_EVQ_UNLOCK(evq); } out: SFXGE_ADAPTER_UNLOCK(sc); } static int sfxge_ev_stat_handler(SYSCTL_HANDLER_ARGS) { struct sfxge_softc *sc = arg1; unsigned int id = arg2; sfxge_ev_stat_update(sc); return (SYSCTL_OUT(req, &sc->ev_stats[id], sizeof(sc->ev_stats[id]))); } static void sfxge_ev_stat_init(struct sfxge_softc *sc) { struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev); struct sysctl_oid_list *stat_list; unsigned int id; char name[40]; stat_list = SYSCTL_CHILDREN(sc->stats_node); for (id = 0; id < EV_NQSTATS; id++) { snprintf(name, sizeof(name), "ev_%s", efx_ev_qstat_name(sc->enp, id)); SYSCTL_ADD_PROC( ctx, stat_list, OID_AUTO, name, CTLTYPE_U64|CTLFLAG_RD, sc, id, sfxge_ev_stat_handler, "Q", ""); } } #endif /* EFSYS_OPT_QSTATS */ static void sfxge_ev_qmoderate(struct sfxge_softc *sc, unsigned int idx, unsigned int us) { struct sfxge_evq *evq; efx_evq_t *eep; evq = sc->evq[idx]; eep = evq->common; KASSERT(evq->init_state == SFXGE_EVQ_STARTED, ("evq->init_state != SFXGE_EVQ_STARTED")); (void)efx_ev_qmoderate(eep, us); } static int sfxge_int_mod_handler(SYSCTL_HANDLER_ARGS) { struct sfxge_softc *sc = arg1; struct sfxge_intr *intr = &sc->intr; unsigned int moderation; int error; unsigned int index; SFXGE_ADAPTER_LOCK(sc); if (req->newptr != NULL) { if ((error = SYSCTL_IN(req, &moderation, sizeof(moderation))) != 0) goto out; /* We may not be calling efx_ev_qmoderate() now, * so we have to range-check the value ourselves. */ if (moderation > efx_nic_cfg_get(sc->enp)->enc_evq_timer_max_us) { error = EINVAL; goto out; } sc->ev_moderation = moderation; if (intr->state == SFXGE_INTR_STARTED) { for (index = 0; index < sc->evq_count; index++) sfxge_ev_qmoderate(sc, index, moderation); } } else { error = SYSCTL_OUT(req, &sc->ev_moderation, sizeof(sc->ev_moderation)); } out: SFXGE_ADAPTER_UNLOCK(sc); return (error); } static boolean_t sfxge_ev_initialized(void *arg) { struct sfxge_evq *evq; evq = (struct sfxge_evq *)arg; SFXGE_EVQ_LOCK_ASSERT_OWNED(evq); - KASSERT(evq->init_state == SFXGE_EVQ_STARTING, + /* Init done events may be duplicated on 7xxx */ + KASSERT(evq->init_state == SFXGE_EVQ_STARTING || + evq->init_state == SFXGE_EVQ_STARTED, ("evq not starting")); evq->init_state = SFXGE_EVQ_STARTED; return (0); } static boolean_t sfxge_ev_link_change(void *arg, efx_link_mode_t link_mode) { struct sfxge_evq *evq; struct sfxge_softc *sc; evq = (struct sfxge_evq *)arg; SFXGE_EVQ_LOCK_ASSERT_OWNED(evq); sc = evq->sc; sfxge_mac_link_update(sc, link_mode); return (0); } static const efx_ev_callbacks_t sfxge_ev_callbacks = { .eec_initialized = sfxge_ev_initialized, .eec_rx = sfxge_ev_rx, .eec_tx = sfxge_ev_tx, .eec_exception = sfxge_ev_exception, .eec_rxq_flush_done = sfxge_ev_rxq_flush_done, .eec_rxq_flush_failed = sfxge_ev_rxq_flush_failed, .eec_txq_flush_done = sfxge_ev_txq_flush_done, .eec_software = sfxge_ev_software, .eec_sram = sfxge_ev_sram, .eec_wake_up = sfxge_ev_wake_up, .eec_timer = sfxge_ev_timer, .eec_link_change = sfxge_ev_link_change, }; int sfxge_ev_qpoll(struct sfxge_evq *evq) { int rc; SFXGE_EVQ_LOCK(evq); if (__predict_false(evq->init_state != SFXGE_EVQ_STARTING && evq->init_state != SFXGE_EVQ_STARTED)) { rc = EINVAL; goto fail; } /* Synchronize the DMA memory for reading */ bus_dmamap_sync(evq->mem.esm_tag, evq->mem.esm_map, BUS_DMASYNC_POSTREAD); KASSERT(evq->rx_done == 0, ("evq->rx_done != 0")); KASSERT(evq->tx_done == 0, ("evq->tx_done != 0")); KASSERT(evq->txq == NULL, ("evq->txq != NULL")); KASSERT(evq->txqs == &evq->txq, ("evq->txqs != &evq->txq")); /* Poll the queue */ efx_ev_qpoll(evq->common, &evq->read_ptr, &sfxge_ev_callbacks, evq); evq->rx_done = 0; evq->tx_done = 0; /* Perform any pending completion processing */ sfxge_ev_qcomplete(evq, B_TRUE); /* Re-prime the event queue for interrupts */ if ((rc = efx_ev_qprime(evq->common, evq->read_ptr)) != 0) goto fail; SFXGE_EVQ_UNLOCK(evq); return (0); fail: SFXGE_EVQ_UNLOCK(evq); return (rc); } static void sfxge_ev_qstop(struct sfxge_softc *sc, unsigned int index) { struct sfxge_evq *evq; evq = sc->evq[index]; KASSERT(evq->init_state == SFXGE_EVQ_STARTED, ("evq->init_state != SFXGE_EVQ_STARTED")); SFXGE_EVQ_LOCK(evq); evq->init_state = SFXGE_EVQ_INITIALIZED; evq->read_ptr = 0; evq->exception = B_FALSE; #if EFSYS_OPT_QSTATS /* Add event counts before discarding the common evq state */ efx_ev_qstats_update(evq->common, sc->ev_stats); #endif efx_ev_qdestroy(evq->common); efx_sram_buf_tbl_clear(sc->enp, evq->buf_base_id, EFX_EVQ_NBUFS(evq->entries)); SFXGE_EVQ_UNLOCK(evq); } static int sfxge_ev_qstart(struct sfxge_softc *sc, unsigned int index) { struct sfxge_evq *evq; efsys_mem_t *esmp; int count; int rc; evq = sc->evq[index]; esmp = &evq->mem; KASSERT(evq->init_state == SFXGE_EVQ_INITIALIZED, ("evq->init_state != SFXGE_EVQ_INITIALIZED")); /* Clear all events. */ (void)memset(esmp->esm_base, 0xff, EFX_EVQ_SIZE(evq->entries)); /* Program the buffer table. */ if ((rc = efx_sram_buf_tbl_set(sc->enp, evq->buf_base_id, esmp, EFX_EVQ_NBUFS(evq->entries))) != 0) return (rc); /* Create the common code event queue. */ if ((rc = efx_ev_qcreate(sc->enp, index, esmp, evq->entries, evq->buf_base_id, &evq->common)) != 0) goto fail; SFXGE_EVQ_LOCK(evq); /* Set the default moderation */ (void)efx_ev_qmoderate(evq->common, sc->ev_moderation); /* Prime the event queue for interrupts */ if ((rc = efx_ev_qprime(evq->common, evq->read_ptr)) != 0) goto fail2; evq->init_state = SFXGE_EVQ_STARTING; SFXGE_EVQ_UNLOCK(evq); /* Wait for the initialization event */ count = 0; do { /* Pause for 100 ms */ pause("sfxge evq init", hz / 10); /* Check to see if the test event has been processed */ if (evq->init_state == SFXGE_EVQ_STARTED) goto done; } while (++count < 20); rc = ETIMEDOUT; goto fail3; done: return (0); fail3: SFXGE_EVQ_LOCK(evq); evq->init_state = SFXGE_EVQ_INITIALIZED; fail2: SFXGE_EVQ_UNLOCK(evq); efx_ev_qdestroy(evq->common); fail: efx_sram_buf_tbl_clear(sc->enp, evq->buf_base_id, EFX_EVQ_NBUFS(evq->entries)); return (rc); } void sfxge_ev_stop(struct sfxge_softc *sc) { struct sfxge_intr *intr; efx_nic_t *enp; int index; intr = &sc->intr; enp = sc->enp; KASSERT(intr->state == SFXGE_INTR_STARTED, ("Interrupts not started")); /* Stop the event queue(s) */ index = sc->evq_count; while (--index >= 0) sfxge_ev_qstop(sc, index); /* Tear down the event module */ efx_ev_fini(enp); } int sfxge_ev_start(struct sfxge_softc *sc) { struct sfxge_intr *intr; int index; int rc; intr = &sc->intr; KASSERT(intr->state == SFXGE_INTR_STARTED, ("intr->state != SFXGE_INTR_STARTED")); /* Initialize the event module */ if ((rc = efx_ev_init(sc->enp)) != 0) return (rc); /* Start the event queues */ for (index = 0; index < sc->evq_count; index++) { if ((rc = sfxge_ev_qstart(sc, index)) != 0) goto fail; } return (0); fail: /* Stop the event queue(s) */ while (--index >= 0) sfxge_ev_qstop(sc, index); /* Tear down the event module */ efx_ev_fini(sc->enp); return (rc); } static void sfxge_ev_qfini(struct sfxge_softc *sc, unsigned int index) { struct sfxge_evq *evq; evq = sc->evq[index]; KASSERT(evq->init_state == SFXGE_EVQ_INITIALIZED, ("evq->init_state != SFXGE_EVQ_INITIALIZED")); KASSERT(evq->txqs == &evq->txq, ("evq->txqs != &evq->txq")); sfxge_dma_free(&evq->mem); sc->evq[index] = NULL; SFXGE_EVQ_LOCK_DESTROY(evq); free(evq, M_SFXGE); } static int sfxge_ev_qinit(struct sfxge_softc *sc, unsigned int index) { struct sfxge_evq *evq; efsys_mem_t *esmp; int rc; KASSERT(index < SFXGE_RX_SCALE_MAX, ("index >= SFXGE_RX_SCALE_MAX")); evq = malloc(sizeof(struct sfxge_evq), M_SFXGE, M_ZERO | M_WAITOK); evq->sc = sc; evq->index = index; sc->evq[index] = evq; esmp = &evq->mem; /* Build an event queue with room for one event per tx and rx buffer, * plus some extra for link state events and MCDI completions. * There are three tx queues in the first event queue and one in * other. */ if (index == 0) evq->entries = ROUNDUP_POW_OF_TWO(sc->rxq_entries + 3 * sc->txq_entries + 128); else evq->entries = ROUNDUP_POW_OF_TWO(sc->rxq_entries + sc->txq_entries + 128); /* Initialise TX completion list */ evq->txqs = &evq->txq; /* Allocate DMA space. */ if ((rc = sfxge_dma_alloc(sc, EFX_EVQ_SIZE(evq->entries), esmp)) != 0) return (rc); /* Allocate buffer table entries. */ sfxge_sram_buf_tbl_alloc(sc, EFX_EVQ_NBUFS(evq->entries), &evq->buf_base_id); SFXGE_EVQ_LOCK_INIT(evq, device_get_nameunit(sc->dev), index); evq->init_state = SFXGE_EVQ_INITIALIZED; return (0); } void sfxge_ev_fini(struct sfxge_softc *sc) { struct sfxge_intr *intr; int index; intr = &sc->intr; KASSERT(intr->state == SFXGE_INTR_INITIALIZED, ("intr->state != SFXGE_INTR_INITIALIZED")); sc->ev_moderation = 0; /* Tear down the event queue(s). */ index = sc->evq_count; while (--index >= 0) sfxge_ev_qfini(sc, index); sc->evq_count = 0; } int sfxge_ev_init(struct sfxge_softc *sc) { struct sysctl_ctx_list *sysctl_ctx = device_get_sysctl_ctx(sc->dev); struct sysctl_oid *sysctl_tree = device_get_sysctl_tree(sc->dev); struct sfxge_intr *intr; int index; int rc; intr = &sc->intr; sc->evq_count = intr->n_alloc; KASSERT(intr->state == SFXGE_INTR_INITIALIZED, ("intr->state != SFXGE_INTR_INITIALIZED")); /* Set default interrupt moderation; add a sysctl to * read and change it. */ sc->ev_moderation = SFXGE_MODERATION; SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO, "int_mod", CTLTYPE_UINT|CTLFLAG_RW, sc, 0, sfxge_int_mod_handler, "IU", "sfxge interrupt moderation (us)"); /* * Initialize the event queue(s) - one per interrupt. */ for (index = 0; index < sc->evq_count; index++) { if ((rc = sfxge_ev_qinit(sc, index)) != 0) goto fail; } #if EFSYS_OPT_QSTATS sfxge_ev_stat_init(sc); #endif return (0); fail: while (--index >= 0) sfxge_ev_qfini(sc, index); sc->evq_count = 0; return (rc); } Property changes on: head/sys/dev/sfxge/sfxge_ev.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/sfxge_intr.c =================================================================== --- head/sys/dev/sfxge/sfxge_intr.c (revision 283513) +++ head/sys/dev/sfxge/sfxge_intr.c (revision 283514) @@ -1,562 +1,558 @@ /*- - * Copyright (c) 2010-2011 Solarflare Communications, Inc. + * Copyright (c) 2010-2015 Solarflare Communications Inc. * All rights reserved. * * This software was developed in part by Philip Paeps under contract for * Solarflare Communications, Inc. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include -#include #include #include #include #include #include #include #include "common/efx.h" #include "sfxge.h" static int sfxge_intr_line_filter(void *arg) { struct sfxge_evq *evq; struct sfxge_softc *sc; efx_nic_t *enp; struct sfxge_intr *intr; boolean_t fatal; uint32_t qmask; evq = (struct sfxge_evq *)arg; sc = evq->sc; enp = sc->enp; intr = &sc->intr; KASSERT(intr != NULL, ("intr == NULL")); KASSERT(intr->type == EFX_INTR_LINE, ("intr->type != EFX_INTR_LINE")); if (intr->state != SFXGE_INTR_STARTED) return (FILTER_STRAY); (void)efx_intr_status_line(enp, &fatal, &qmask); if (fatal) { (void) efx_intr_disable(enp); (void) efx_intr_fatal(enp); return (FILTER_HANDLED); } if (qmask != 0) { intr->zero_count = 0; return (FILTER_SCHEDULE_THREAD); } /* SF bug 15783: If the function is not asserting its IRQ and * we read the queue mask on the cycle before a flag is added * to the mask, this inhibits the function from asserting the * IRQ even though we don't see the flag set. To work around * this, we must re-prime all event queues and report the IRQ * as handled when we see a mask of zero. To allow for shared * IRQs, we don't repeat this if we see a mask of zero twice * or more in a row. */ if (intr->zero_count++ == 0) { if (evq->init_state == SFXGE_EVQ_STARTED) { if (efx_ev_qpending(evq->common, evq->read_ptr)) return (FILTER_SCHEDULE_THREAD); efx_ev_qprime(evq->common, evq->read_ptr); return (FILTER_HANDLED); } } return (FILTER_STRAY); } static void sfxge_intr_line(void *arg) { struct sfxge_evq *evq = arg; (void)sfxge_ev_qpoll(evq); } static void sfxge_intr_message(void *arg) { struct sfxge_evq *evq; struct sfxge_softc *sc; efx_nic_t *enp; struct sfxge_intr *intr; unsigned int index; boolean_t fatal; evq = (struct sfxge_evq *)arg; sc = evq->sc; enp = sc->enp; intr = &sc->intr; index = evq->index; KASSERT(intr != NULL, ("intr == NULL")); KASSERT(intr->type == EFX_INTR_MESSAGE, ("intr->type != EFX_INTR_MESSAGE")); if (__predict_false(intr->state != SFXGE_INTR_STARTED)) return; (void)efx_intr_status_message(enp, index, &fatal); if (fatal) { (void)efx_intr_disable(enp); (void)efx_intr_fatal(enp); return; } (void)sfxge_ev_qpoll(evq); } static int sfxge_intr_bus_enable(struct sfxge_softc *sc) { struct sfxge_intr *intr; struct sfxge_intr_hdl *table; driver_filter_t *filter; driver_intr_t *handler; int index; int err; intr = &sc->intr; table = intr->table; switch (intr->type) { case EFX_INTR_MESSAGE: filter = NULL; /* not shared */ handler = sfxge_intr_message; break; case EFX_INTR_LINE: filter = sfxge_intr_line_filter; handler = sfxge_intr_line; break; default: KASSERT(0, ("Invalid interrupt type")); return (EINVAL); } /* Try to add the handlers */ for (index = 0; index < intr->n_alloc; index++) { if ((err = bus_setup_intr(sc->dev, table[index].eih_res, INTR_MPSAFE|INTR_TYPE_NET, filter, handler, sc->evq[index], &table[index].eih_tag)) != 0) { goto fail; } #ifdef SFXGE_HAVE_DESCRIBE_INTR if (intr->n_alloc > 1) bus_describe_intr(sc->dev, table[index].eih_res, table[index].eih_tag, "%d", index); #endif bus_bind_intr(sc->dev, table[index].eih_res, index); } return (0); fail: /* Remove remaining handlers */ while (--index >= 0) bus_teardown_intr(sc->dev, table[index].eih_res, table[index].eih_tag); return (err); } static void sfxge_intr_bus_disable(struct sfxge_softc *sc) { struct sfxge_intr *intr; struct sfxge_intr_hdl *table; int i; intr = &sc->intr; table = intr->table; /* Remove all handlers */ for (i = 0; i < intr->n_alloc; i++) bus_teardown_intr(sc->dev, table[i].eih_res, table[i].eih_tag); } static int sfxge_intr_alloc(struct sfxge_softc *sc, int count) { device_t dev; struct sfxge_intr_hdl *table; struct sfxge_intr *intr; struct resource *res; int rid; int error; int i; dev = sc->dev; intr = &sc->intr; error = 0; table = malloc(count * sizeof(struct sfxge_intr_hdl), M_SFXGE, M_WAITOK); intr->table = table; for (i = 0; i < count; i++) { rid = i + 1; res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); if (res == NULL) { device_printf(dev, "Couldn't allocate interrupts for " "message %d\n", rid); error = ENOMEM; break; } table[i].eih_rid = rid; table[i].eih_res = res; } if (error != 0) { count = i - 1; for (i = 0; i < count; i++) bus_release_resource(dev, SYS_RES_IRQ, table[i].eih_rid, table[i].eih_res); } return (error); } static void sfxge_intr_teardown_msix(struct sfxge_softc *sc) { device_t dev; struct resource *resp; int rid; dev = sc->dev; resp = sc->intr.msix_res; rid = rman_get_rid(resp); bus_release_resource(dev, SYS_RES_MEMORY, rid, resp); } static int sfxge_intr_setup_msix(struct sfxge_softc *sc) { struct sfxge_intr *intr; struct resource *resp; device_t dev; int count; int rid; dev = sc->dev; intr = &sc->intr; /* Check if MSI-X is available. */ count = pci_msix_count(dev); if (count == 0) return (EINVAL); - /* Limit the number of interrupts to the number of CPUs. */ - if (count > mp_ncpus) - count = mp_ncpus; + /* Do not try to allocate more than already estimated EVQ maximum */ + KASSERT(sc->evq_max > 0, ("evq_max is zero")); + count = MIN(count, sc->evq_max); - /* Not very likely these days... */ - if (count > EFX_MAXRSS) - count = EFX_MAXRSS; - - if (sc->max_rss_channels > 0 && count > sc->max_rss_channels) - count = sc->max_rss_channels; - rid = PCIR_BAR(4); resp = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (resp == NULL) return (ENOMEM); if (pci_alloc_msix(dev, &count) != 0) { bus_release_resource(dev, SYS_RES_MEMORY, rid, resp); return (ENOMEM); } /* Allocate interrupt handlers. */ if (sfxge_intr_alloc(sc, count) != 0) { bus_release_resource(dev, SYS_RES_MEMORY, rid, resp); pci_release_msi(dev); return (ENOMEM); } intr->type = EFX_INTR_MESSAGE; intr->n_alloc = count; intr->msix_res = resp; return (0); } static int sfxge_intr_setup_msi(struct sfxge_softc *sc) { struct sfxge_intr_hdl *table; struct sfxge_intr *intr; device_t dev; int count; int error; dev = sc->dev; intr = &sc->intr; table = intr->table; /* * Check if MSI is available. All messages must be written to * the same address and on x86 this means the IRQs have the * same CPU affinity. So we only ever allocate 1. */ count = pci_msi_count(dev) ? 1 : 0; if (count == 0) return (EINVAL); if ((error = pci_alloc_msi(dev, &count)) != 0) return (ENOMEM); /* Allocate interrupt handler. */ if (sfxge_intr_alloc(sc, count) != 0) { pci_release_msi(dev); return (ENOMEM); } intr->type = EFX_INTR_MESSAGE; intr->n_alloc = count; return (0); } static int sfxge_intr_setup_fixed(struct sfxge_softc *sc) { struct sfxge_intr_hdl *table; struct sfxge_intr *intr; struct resource *res; device_t dev; int rid; dev = sc->dev; intr = &sc->intr; rid = 0; res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); if (res == NULL) return (ENOMEM); table = malloc(sizeof(struct sfxge_intr_hdl), M_SFXGE, M_WAITOK); table[0].eih_rid = rid; table[0].eih_res = res; intr->type = EFX_INTR_LINE; intr->n_alloc = 1; intr->table = table; return (0); } static const char *const __sfxge_err[] = { "", "SRAM out-of-bounds", "Buffer ID out-of-bounds", "Internal memory parity", "Receive buffer ownership", "Transmit buffer ownership", "Receive descriptor ownership", "Transmit descriptor ownership", "Event queue ownership", "Event queue FIFO overflow", "Illegal address", "SRAM parity" }; void sfxge_err(efsys_identifier_t *arg, unsigned int code, uint32_t dword0, - uint32_t dword1) + uint32_t dword1) { struct sfxge_softc *sc = (struct sfxge_softc *)arg; device_t dev = sc->dev; log(LOG_WARNING, "[%s%d] FATAL ERROR: %s (0x%08x%08x)", device_get_name(dev), device_get_unit(dev), __sfxge_err[code], dword1, dword0); } void sfxge_intr_stop(struct sfxge_softc *sc) { struct sfxge_intr *intr; intr = &sc->intr; KASSERT(intr->state == SFXGE_INTR_STARTED, ("Interrupts not started")); intr->state = SFXGE_INTR_INITIALIZED; /* Disable interrupts at the NIC */ efx_intr_disable(sc->enp); /* Disable interrupts at the bus */ sfxge_intr_bus_disable(sc); /* Tear down common code interrupt bits. */ efx_intr_fini(sc->enp); } int sfxge_intr_start(struct sfxge_softc *sc) { struct sfxge_intr *intr; efsys_mem_t *esmp; int rc; intr = &sc->intr; esmp = &intr->status; KASSERT(intr->state == SFXGE_INTR_INITIALIZED, ("Interrupts not initialized")); /* Zero the memory. */ (void)memset(esmp->esm_base, 0, EFX_INTR_SIZE); /* Initialize common code interrupt bits. */ (void)efx_intr_init(sc->enp, intr->type, esmp); /* Enable interrupts at the bus */ if ((rc = sfxge_intr_bus_enable(sc)) != 0) goto fail; intr->state = SFXGE_INTR_STARTED; /* Enable interrupts at the NIC */ efx_intr_enable(sc->enp); return (0); fail: /* Tear down common code interrupt bits. */ efx_intr_fini(sc->enp); intr->state = SFXGE_INTR_INITIALIZED; return (rc); } void sfxge_intr_fini(struct sfxge_softc *sc) { struct sfxge_intr_hdl *table; struct sfxge_intr *intr; efsys_mem_t *esmp; device_t dev; int i; dev = sc->dev; intr = &sc->intr; esmp = &intr->status; table = intr->table; KASSERT(intr->state == SFXGE_INTR_INITIALIZED, ("intr->state != SFXGE_INTR_INITIALIZED")); /* Free DMA memory. */ sfxge_dma_free(esmp); /* Free interrupt handles. */ for (i = 0; i < intr->n_alloc; i++) bus_release_resource(dev, SYS_RES_IRQ, table[i].eih_rid, table[i].eih_res); if (table[0].eih_rid != 0) pci_release_msi(dev); if (intr->msix_res != NULL) sfxge_intr_teardown_msix(sc); /* Free the handle table */ free(table, M_SFXGE); intr->table = NULL; intr->n_alloc = 0; /* Clear the interrupt type */ intr->type = EFX_INTR_INVALID; intr->state = SFXGE_INTR_UNINITIALIZED; } int sfxge_intr_init(struct sfxge_softc *sc) { device_t dev; struct sfxge_intr *intr; efsys_mem_t *esmp; int rc; dev = sc->dev; intr = &sc->intr; esmp = &intr->status; KASSERT(intr->state == SFXGE_INTR_UNINITIALIZED, ("Interrupts already initialized")); /* Try to setup MSI-X or MSI interrupts if available. */ if ((rc = sfxge_intr_setup_msix(sc)) == 0) device_printf(dev, "Using MSI-X interrupts\n"); else if ((rc = sfxge_intr_setup_msi(sc)) == 0) device_printf(dev, "Using MSI interrupts\n"); else if ((rc = sfxge_intr_setup_fixed(sc)) == 0) { device_printf(dev, "Using fixed interrupts\n"); } else { device_printf(dev, "Couldn't setup interrupts\n"); return (ENOMEM); } /* Set up DMA for interrupts. */ if ((rc = sfxge_dma_alloc(sc, EFX_INTR_SIZE, esmp)) != 0) return (ENOMEM); intr->state = SFXGE_INTR_INITIALIZED; return (0); } Property changes on: head/sys/dev/sfxge/sfxge_intr.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/sfxge_ioc.h =================================================================== --- head/sys/dev/sfxge/sfxge_ioc.h (nonexistent) +++ head/sys/dev/sfxge/sfxge_ioc.h (revision 283514) @@ -0,0 +1,112 @@ +/*- + * Copyright (c) 2014-2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + * + * $FreeBSD$ + */ + +#ifndef _SYS_SFXGE_IOC_H +#define _SYS_SFXGE_IOC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* More codes may be added if necessary */ +enum sfxge_ioc_codes { + SFXGE_MCDI_IOC, + SFXGE_NVRAM_IOC, + SFXGE_VPD_IOC +}; + +enum sfxge_nvram_ops { + SFXGE_NVRAM_OP_SIZE, + SFXGE_NVRAM_OP_READ, + SFXGE_NVRAM_OP_WRITE, + SFXGE_NVRAM_OP_ERASE, + SFXGE_NVRAM_OP_GET_VER, + SFXGE_NVRAM_OP_SET_VER +}; + +enum sfxge_nvram_types { + SFXGE_NVRAM_TYPE_BOOTROM, + SFXGE_NVRAM_TYPE_BOOTROM_CFG, + SFXGE_NVRAM_TYPE_MC, + SFXGE_NVRAM_TYPE_MC_GOLDEN, + SFXGE_NVRAM_TYPE_PHY, + SFXGE_NVRAM_TYPE_NULL_PHY, + SFXGE_NVRAM_TYPE_FPGA, + SFXGE_NVRAM_TYPE_FCFW, + SFXGE_NVRAM_TYPE_CPLD, + SFXGE_NVRAM_TYPE_FPGA_BACKUP, + SFXGE_NVRAM_TYPE_DYNAMIC_CFG +}; + +enum sfxge_vpd_ops { + SFXGE_VPD_OP_GET_KEYWORD, + SFXGE_VPD_OP_SET_KEYWORD +}; + +#define SFXGE_MCDI_MAX_PAYLOAD 0x400 +#define SFXGE_VPD_MAX_PAYLOAD 0x100 + +typedef struct sfxge_ioc_s { + uint32_t op; + union { + struct { + caddr_t payload; + uint32_t cmd; + size_t len; /* In and out */ + uint32_t rc; + } mcdi; + struct { + uint32_t op; + uint32_t type; + uint32_t offset; + uint32_t size; + uint32_t subtype; + uint16_t version[4]; /* get/set_ver */ + caddr_t data; + } nvram; + struct { + uint8_t op; + uint8_t tag; + uint16_t keyword; + uint16_t len; /* In or out */ + caddr_t payload; + } vpd; + } u; +} __packed sfxge_ioc_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_SFXGE_IOC_H */ Property changes on: head/sys/dev/sfxge/sfxge_ioc.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/sfxge_mcdi.c =================================================================== --- head/sys/dev/sfxge/sfxge_mcdi.c (revision 283513) +++ head/sys/dev/sfxge/sfxge_mcdi.c (revision 283514) @@ -1,248 +1,309 @@ /*- - * Copyright (c) 2010-2011 Solarflare Communications, Inc. + * Copyright (c) 2010-2015 Solarflare Communications Inc. * All rights reserved. * * This software was developed in part by Philip Paeps under contract for * Solarflare Communications, Inc. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include +#include #include "common/efx.h" #include "common/efx_mcdi.h" #include "common/efx_regs_mcdi.h" #include "sfxge.h" #define SFXGE_MCDI_POLL_INTERVAL_MIN 10 /* 10us in 1us units */ #define SFXGE_MCDI_POLL_INTERVAL_MAX 100000 /* 100ms in 1us units */ #define SFXGE_MCDI_WATCHDOG_INTERVAL 10000000 /* 10s in 1us units */ -/* Acquire exclusive access to MCDI for the duration of a request. */ static void -sfxge_mcdi_acquire(struct sfxge_mcdi *mcdi) -{ - SFXGE_MCDI_LOCK(mcdi); - KASSERT(mcdi->state != SFXGE_MCDI_UNINITIALIZED, - ("MCDI not initialized")); - - while (mcdi->state != SFXGE_MCDI_INITIALIZED) - (void)cv_wait_sig(&mcdi->cv, &mcdi->lock); - mcdi->state = SFXGE_MCDI_BUSY; - - SFXGE_MCDI_UNLOCK(mcdi); -} - -/* Release ownership of MCDI on request completion. */ -static void -sfxge_mcdi_release(struct sfxge_mcdi *mcdi) -{ - SFXGE_MCDI_LOCK(mcdi); - KASSERT((mcdi->state == SFXGE_MCDI_BUSY || - mcdi->state == SFXGE_MCDI_COMPLETED), - ("MCDI not busy or task not completed")); - - mcdi->state = SFXGE_MCDI_INITIALIZED; - cv_broadcast(&mcdi->cv); - - SFXGE_MCDI_UNLOCK(mcdi); -} - -static void sfxge_mcdi_timeout(struct sfxge_softc *sc) { device_t dev = sc->dev; log(LOG_WARNING, "[%s%d] MC_TIMEOUT", device_get_name(dev), device_get_unit(dev)); EFSYS_PROBE(mcdi_timeout); sfxge_schedule_reset(sc); } static void sfxge_mcdi_poll(struct sfxge_softc *sc) { efx_nic_t *enp; clock_t delay_total; clock_t delay_us; boolean_t aborted; delay_total = 0; delay_us = SFXGE_MCDI_POLL_INTERVAL_MIN; enp = sc->enp; do { if (efx_mcdi_request_poll(enp)) { EFSYS_PROBE1(mcdi_delay, clock_t, delay_total); return; } if (delay_total > SFXGE_MCDI_WATCHDOG_INTERVAL) { aborted = efx_mcdi_request_abort(enp); KASSERT(aborted, ("abort failed")); sfxge_mcdi_timeout(sc); return; } /* Spin or block depending on delay interval. */ if (delay_us < 1000000) DELAY(delay_us); else pause("mcdi wait", delay_us * hz / 1000000); delay_total += delay_us; /* Exponentially back off the poll frequency. */ delay_us = delay_us * 2; if (delay_us > SFXGE_MCDI_POLL_INTERVAL_MAX) delay_us = SFXGE_MCDI_POLL_INTERVAL_MAX; } while (1); } static void sfxge_mcdi_execute(void *arg, efx_mcdi_req_t *emrp) { struct sfxge_softc *sc; struct sfxge_mcdi *mcdi; sc = (struct sfxge_softc *)arg; mcdi = &sc->mcdi; - sfxge_mcdi_acquire(mcdi); + SFXGE_MCDI_LOCK(mcdi); + KASSERT(mcdi->state == SFXGE_MCDI_INITIALIZED, + ("MCDI not initialized")); + /* Issue request and poll for completion. */ efx_mcdi_request_start(sc->enp, emrp, B_FALSE); sfxge_mcdi_poll(sc); - sfxge_mcdi_release(mcdi); + SFXGE_MCDI_UNLOCK(mcdi); } static void sfxge_mcdi_ev_cpl(void *arg) { struct sfxge_softc *sc; struct sfxge_mcdi *mcdi; sc = (struct sfxge_softc *)arg; mcdi = &sc->mcdi; - SFXGE_MCDI_LOCK(mcdi); - KASSERT(mcdi->state == SFXGE_MCDI_BUSY, ("MCDI not busy")); - mcdi->state = SFXGE_MCDI_COMPLETED; - cv_broadcast(&mcdi->cv); - SFXGE_MCDI_UNLOCK(mcdi); + KASSERT(mcdi->state == SFXGE_MCDI_INITIALIZED, + ("MCDI not initialized")); + + /* We do not use MCDI completion, MCDI is simply polled */ } static void sfxge_mcdi_exception(void *arg, efx_mcdi_exception_t eme) { struct sfxge_softc *sc; device_t dev; sc = (struct sfxge_softc *)arg; dev = sc->dev; log(LOG_WARNING, "[%s%d] MC_%s", device_get_name(dev), device_get_unit(dev), (eme == EFX_MCDI_EXCEPTION_MC_REBOOT) ? "REBOOT" : (eme == EFX_MCDI_EXCEPTION_MC_BADASSERT) ? "BADASSERT" : "UNKNOWN"); EFSYS_PROBE(mcdi_exception); sfxge_schedule_reset(sc); } int +sfxge_mcdi_ioctl(struct sfxge_softc *sc, sfxge_ioc_t *ip) +{ + const efx_nic_cfg_t *encp = efx_nic_cfg_get(sc->enp); + struct sfxge_mcdi *mp = &(sc->mcdi); + efx_mcdi_req_t emr; + uint8_t *mcdibuf; + int rc; + + if (mp->state == SFXGE_MCDI_UNINITIALIZED) { + rc = ENODEV; + goto fail1; + } + + if (!(encp->enc_features & EFX_FEATURE_MCDI)) { + rc = ENOTSUP; + goto fail2; + } + + if (ip->u.mcdi.len > SFXGE_MCDI_MAX_PAYLOAD) { + rc = EINVAL; + goto fail3; + } + + mcdibuf = malloc(SFXGE_MCDI_MAX_PAYLOAD, M_TEMP, M_WAITOK | M_ZERO); + if (mcdibuf == NULL) { + rc = ENOMEM; + goto fail4; + } + if ((rc = copyin(ip->u.mcdi.payload, mcdibuf, ip->u.mcdi.len)) != 0) { + goto fail5; + } + + emr.emr_cmd = ip->u.mcdi.cmd; + emr.emr_in_buf = mcdibuf; + emr.emr_in_length = ip->u.mcdi.len; + + emr.emr_out_buf = mcdibuf; + emr.emr_out_length = SFXGE_MCDI_MAX_PAYLOAD; + + sfxge_mcdi_execute(sc, &emr); + + ip->u.mcdi.rc = emr.emr_rc; + ip->u.mcdi.cmd = emr.emr_cmd; + ip->u.mcdi.len = emr.emr_out_length_used; + if ((rc = copyout(mcdibuf, ip->u.mcdi.payload, ip->u.mcdi.len)) != 0) { + goto fail6; + } + + /* + * Helpfully trigger a device reset in response to an MCDI_CMD_REBOOT + * Both ports will see ->emt_exception callbacks on the next MCDI poll + */ + if (ip->u.mcdi.cmd == MC_CMD_REBOOT) { + + EFSYS_PROBE(mcdi_ioctl_mc_reboot); + /* sfxge_t->s_state_lock held */ + (void) sfxge_schedule_reset(sc); + } + + free(mcdibuf, M_TEMP); + + return (0); + +fail6: +fail5: + free(mcdibuf, M_TEMP); +fail4: +fail3: +fail2: +fail1: + return (rc); +} + + +int sfxge_mcdi_init(struct sfxge_softc *sc) { efx_nic_t *enp; struct sfxge_mcdi *mcdi; efx_mcdi_transport_t *emtp; + efsys_mem_t *esmp; + int max_msg_size; int rc; enp = sc->enp; mcdi = &sc->mcdi; emtp = &mcdi->transport; + esmp = &mcdi->mem; + max_msg_size = sizeof (uint32_t) + MCDI_CTL_SDU_LEN_MAX_V2; KASSERT(mcdi->state == SFXGE_MCDI_UNINITIALIZED, ("MCDI already initialized")); SFXGE_MCDI_LOCK_INIT(mcdi, device_get_nameunit(sc->dev)); mcdi->state = SFXGE_MCDI_INITIALIZED; + if ((rc = sfxge_dma_alloc(sc, max_msg_size, esmp)) != 0) + goto fail; + emtp->emt_context = sc; + emtp->emt_dma_mem = esmp; emtp->emt_execute = sfxge_mcdi_execute; emtp->emt_ev_cpl = sfxge_mcdi_ev_cpl; emtp->emt_exception = sfxge_mcdi_exception; - cv_init(&mcdi->cv, "sfxge_mcdi"); - if ((rc = efx_mcdi_init(enp, emtp)) != 0) goto fail; return (0); fail: SFXGE_MCDI_LOCK_DESTROY(mcdi); mcdi->state = SFXGE_MCDI_UNINITIALIZED; return (rc); } void sfxge_mcdi_fini(struct sfxge_softc *sc) { struct sfxge_mcdi *mcdi; efx_nic_t *enp; efx_mcdi_transport_t *emtp; + efsys_mem_t *esmp; enp = sc->enp; mcdi = &sc->mcdi; emtp = &mcdi->transport; + esmp = &mcdi->mem; SFXGE_MCDI_LOCK(mcdi); KASSERT(mcdi->state == SFXGE_MCDI_INITIALIZED, ("MCDI not initialized")); efx_mcdi_fini(enp); bzero(emtp, sizeof(*emtp)); - cv_destroy(&mcdi->cv); SFXGE_MCDI_UNLOCK(mcdi); + + sfxge_dma_free(esmp); SFXGE_MCDI_LOCK_DESTROY(mcdi); } Property changes on: head/sys/dev/sfxge/sfxge_mcdi.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/sfxge_nvram.c =================================================================== --- head/sys/dev/sfxge/sfxge_nvram.c (nonexistent) +++ head/sys/dev/sfxge/sfxge_nvram.c (revision 283514) @@ -0,0 +1,203 @@ +/*- + * Copyright (c) 2010-2015 Solarflare Communications, Inc. + * All rights reserved. + * + * This software was developed in part by OKTET Labs Ltd. under contract for + * Solarflare Communications, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + + +#include +#include + +#include "common/efx.h" +#include "sfxge.h" + +/* These data make no real sense, they are here just to make sfupdate happy. + * Any code that would rely on it is broken. + */ +static const uint8_t fake_dynamic_cfg_nvram[] = { + 0x7a, 0xda, 0x10, 0xef, 0x0c, 0x00, 0x00, 0x00, + 0x00, 0x05, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x10, + 0x08, 0x00, 0x00, 0x00, 0x90, 0x04, 0x00, 0x52, + 0x56, 0x01, 0xc3, 0x78, 0x01, 0x00, 0x03, 0x10, + 0x08, 0x00, 0x00, 0x00, 0x90, 0x04, 0x00, 0x52, + 0x56, 0x01, 0xc3, 0x78, 0x57, 0x1a, 0x10, 0xef, + 0x08, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x02, 0x0b, 0x64, 0x7d, 0xee, 0xee, 0xee, 0xee +}; + +static int +sfxge_nvram_rw(struct sfxge_softc *sc, sfxge_ioc_t *ip, efx_nvram_type_t type, + boolean_t write) +{ + efx_nic_t *enp = sc->enp; + size_t total_size = ip->u.nvram.size; + size_t chunk_size; + off_t off; + int rc = 0; + uint8_t *buf; + + if (type == EFX_NVRAM_DYNAMIC_CFG && sc->family == EFX_FAMILY_SIENA) { + if (write) + return (0); + rc = copyout(fake_dynamic_cfg_nvram, ip->u.nvram.data, + MIN(total_size, sizeof(fake_dynamic_cfg_nvram))); + return (rc); + } + + if ((rc = efx_nvram_rw_start(enp, type, &chunk_size)) != 0) + goto fail1; + + buf = malloc(chunk_size, M_TEMP, M_WAITOK); + if (buf == NULL) { + rc = ENOMEM; + goto fail2; + } + + off = 0; + while (total_size) { + size_t len = MIN(chunk_size, total_size); + + if (write) { + rc = copyin(ip->u.nvram.data + off, buf, len); + if (rc != 0) + goto fail3; + rc = efx_nvram_write_chunk(enp, type, + ip->u.nvram.offset + off, buf, len); + if (rc != 0) + goto fail3; + } else { + rc = efx_nvram_read_chunk(enp, type, + ip->u.nvram.offset + off, buf, len); + if (rc != 0) + goto fail3; + rc = copyout(buf, ip->u.nvram.data + off, len); + if (rc != 0) + goto fail3; + } + + total_size -= len; + off += len; + } + +fail3: + free(buf, M_TEMP); +fail2: + efx_nvram_rw_finish(enp, type); +fail1: + return (rc); +} + + +static int +sfxge_nvram_erase(struct sfxge_softc *sc, efx_nvram_type_t type) +{ + efx_nic_t *enp = sc->enp; + size_t chunk_size; + int rc = 0; + + if (type == EFX_NVRAM_DYNAMIC_CFG && sc->family == EFX_FAMILY_SIENA) + return (0); + + if ((rc = efx_nvram_rw_start(enp, type, &chunk_size)) != 0) + return (rc); + + rc = efx_nvram_erase(enp, type); + + efx_nvram_rw_finish(enp, type); + return (rc); +} + +int +sfxge_nvram_ioctl(struct sfxge_softc *sc, sfxge_ioc_t *ip) +{ + static const efx_nvram_type_t nvram_types[] = { + [SFXGE_NVRAM_TYPE_BOOTROM] = EFX_NVRAM_BOOTROM, + [SFXGE_NVRAM_TYPE_BOOTROM_CFG] = EFX_NVRAM_BOOTROM_CFG, + [SFXGE_NVRAM_TYPE_MC] = EFX_NVRAM_MC_FIRMWARE, + [SFXGE_NVRAM_TYPE_MC_GOLDEN] = EFX_NVRAM_MC_GOLDEN, + [SFXGE_NVRAM_TYPE_PHY] = EFX_NVRAM_PHY, + [SFXGE_NVRAM_TYPE_NULL_PHY] = EFX_NVRAM_NULLPHY, + [SFXGE_NVRAM_TYPE_FPGA] = EFX_NVRAM_FPGA, + [SFXGE_NVRAM_TYPE_FCFW] = EFX_NVRAM_FCFW, + [SFXGE_NVRAM_TYPE_CPLD] = EFX_NVRAM_CPLD, + [SFXGE_NVRAM_TYPE_FPGA_BACKUP] = EFX_NVRAM_FPGA_BACKUP, + [SFXGE_NVRAM_TYPE_DYNAMIC_CFG] = EFX_NVRAM_DYNAMIC_CFG, + }; + + efx_nic_t *enp = sc->enp; + efx_nvram_type_t type; + int rc = 0; + + if (ip->u.nvram.type > SFXGE_NVRAM_TYPE_DYNAMIC_CFG) + return (EINVAL); + type = nvram_types[ip->u.nvram.type]; + if (type == EFX_NVRAM_MC_GOLDEN && + (ip->u.nvram.op == SFXGE_NVRAM_OP_WRITE || + ip->u.nvram.op == SFXGE_NVRAM_OP_ERASE || + ip->u.nvram.op == SFXGE_NVRAM_OP_SET_VER)) + return (EOPNOTSUPP); + + switch (ip->u.nvram.op) { + case SFXGE_NVRAM_OP_SIZE: + { + size_t size; + + if (type == EFX_NVRAM_DYNAMIC_CFG && sc->family == EFX_FAMILY_SIENA) { + ip->u.nvram.size = sizeof(fake_dynamic_cfg_nvram); + } else { + if ((rc = efx_nvram_size(enp, type, &size)) != 0) + return (rc); + ip->u.nvram.size = size; + } + break; + } + case SFXGE_NVRAM_OP_READ: + rc = sfxge_nvram_rw(sc, ip, type, B_FALSE); + break; + case SFXGE_NVRAM_OP_WRITE: + rc = sfxge_nvram_rw(sc, ip, type, B_TRUE); + break; + case SFXGE_NVRAM_OP_ERASE: + rc = sfxge_nvram_erase(sc, type); + break; + case SFXGE_NVRAM_OP_GET_VER: + rc = efx_nvram_get_version(enp, type, &ip->u.nvram.subtype, + &ip->u.nvram.version[0]); + break; + case SFXGE_NVRAM_OP_SET_VER: + rc = efx_nvram_set_version(enp, type, &ip->u.nvram.version[0]); + break; + default: + rc = EOPNOTSUPP; + break; + } + + return (rc); +} Property changes on: head/sys/dev/sfxge/sfxge_nvram.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/sfxge_port.c =================================================================== --- head/sys/dev/sfxge/sfxge_port.c (revision 283513) +++ head/sys/dev/sfxge/sfxge_port.c (revision 283514) @@ -1,946 +1,1000 @@ /*- - * Copyright (c) 2010-2011 Solarflare Communications, Inc. + * Copyright (c) 2010-2015 Solarflare Communications Inc. * All rights reserved. * * This software was developed in part by Philip Paeps under contract for * Solarflare Communications, Inc. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include "common/efx.h" #include "sfxge.h" static int sfxge_phy_cap_mask(struct sfxge_softc *, int, uint32_t *); static int sfxge_mac_stat_update(struct sfxge_softc *sc) { struct sfxge_port *port = &sc->port; efsys_mem_t *esmp = &(port->mac_stats.dma_buf); clock_t now; unsigned int count; int rc; SFXGE_PORT_LOCK_ASSERT_OWNED(port); if (__predict_false(port->init_state != SFXGE_PORT_STARTED)) { rc = 0; goto out; } now = ticks; if (now - port->mac_stats.update_time < hz) { rc = 0; goto out; } port->mac_stats.update_time = now; /* If we're unlucky enough to read statistics wduring the DMA, wait * up to 10ms for it to finish (typically takes <500us) */ for (count = 0; count < 100; ++count) { EFSYS_PROBE1(wait, unsigned int, count); - /* Synchronize the DMA memory for reading */ - bus_dmamap_sync(esmp->esm_tag, esmp->esm_map, - BUS_DMASYNC_POSTREAD); - /* Try to update the cached counters */ if ((rc = efx_mac_stats_update(sc->enp, esmp, port->mac_stats.decode_buf, NULL)) != EAGAIN) goto out; DELAY(100); } rc = ETIMEDOUT; out: return (rc); } uint64_t sfxge_get_counter(struct ifnet *ifp, ift_counter c) { struct sfxge_softc *sc = ifp->if_softc; uint64_t *mac_stats; uint64_t val; SFXGE_PORT_LOCK(&sc->port); /* Ignore error and use old values */ (void)sfxge_mac_stat_update(sc); mac_stats = (uint64_t *)sc->port.mac_stats.decode_buf; switch (c) { case IFCOUNTER_IPACKETS: val = mac_stats[EFX_MAC_RX_PKTS]; break; case IFCOUNTER_IERRORS: val = mac_stats[EFX_MAC_RX_ERRORS]; break; case IFCOUNTER_OPACKETS: val = mac_stats[EFX_MAC_TX_PKTS]; break; case IFCOUNTER_OERRORS: val = mac_stats[EFX_MAC_TX_ERRORS]; break; case IFCOUNTER_COLLISIONS: val = mac_stats[EFX_MAC_TX_SGL_COL_PKTS] + mac_stats[EFX_MAC_TX_MULT_COL_PKTS] + mac_stats[EFX_MAC_TX_EX_COL_PKTS] + mac_stats[EFX_MAC_TX_LATE_COL_PKTS]; break; case IFCOUNTER_IBYTES: val = mac_stats[EFX_MAC_RX_OCTETS]; break; case IFCOUNTER_OBYTES: val = mac_stats[EFX_MAC_TX_OCTETS]; break; case IFCOUNTER_OMCASTS: val = mac_stats[EFX_MAC_TX_MULTICST_PKTS] + mac_stats[EFX_MAC_TX_BRDCST_PKTS]; break; case IFCOUNTER_OQDROPS: SFXGE_PORT_UNLOCK(&sc->port); return (sfxge_tx_get_drops(sc)); case IFCOUNTER_IMCASTS: /* if_imcasts is maintained in net/if_ethersubr.c */ case IFCOUNTER_IQDROPS: /* if_iqdrops is maintained in net/if_ethersubr.c */ case IFCOUNTER_NOPROTO: /* if_noproto is maintained in net/if_ethersubr.c */ default: SFXGE_PORT_UNLOCK(&sc->port); return (if_get_counter_default(ifp, c)); } SFXGE_PORT_UNLOCK(&sc->port); return (val); } static int sfxge_mac_stat_handler(SYSCTL_HANDLER_ARGS) { struct sfxge_softc *sc = arg1; unsigned int id = arg2; int rc; uint64_t val; SFXGE_PORT_LOCK(&sc->port); if ((rc = sfxge_mac_stat_update(sc)) == 0) val = ((uint64_t *)sc->port.mac_stats.decode_buf)[id]; SFXGE_PORT_UNLOCK(&sc->port); if (rc == 0) rc = SYSCTL_OUT(req, &val, sizeof(val)); return (rc); } static void sfxge_mac_stat_init(struct sfxge_softc *sc) { struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev); struct sysctl_oid_list *stat_list; unsigned int id; const char *name; stat_list = SYSCTL_CHILDREN(sc->stats_node); /* Initialise the named stats */ for (id = 0; id < EFX_MAC_NSTATS; id++) { name = efx_mac_stat_name(sc->enp, id); SYSCTL_ADD_PROC( ctx, stat_list, OID_AUTO, name, CTLTYPE_U64|CTLFLAG_RD, sc, id, sfxge_mac_stat_handler, "Q", ""); } } #ifdef SFXGE_HAVE_PAUSE_MEDIAOPTS static unsigned int sfxge_port_wanted_fc(struct sfxge_softc *sc) { struct ifmedia_entry *ifm = sc->media.ifm_cur; if (ifm->ifm_media == (IFM_ETHER | IFM_AUTO)) return (EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE); return (((ifm->ifm_media & IFM_ETH_RXPAUSE) ? EFX_FCNTL_RESPOND : 0) | ((ifm->ifm_media & IFM_ETH_TXPAUSE) ? EFX_FCNTL_GENERATE : 0)); } static unsigned int sfxge_port_link_fc_ifm(struct sfxge_softc *sc) { unsigned int wanted_fc, link_fc; efx_mac_fcntl_get(sc->enp, &wanted_fc, &link_fc); return ((link_fc & EFX_FCNTL_RESPOND) ? IFM_ETH_RXPAUSE : 0) | ((link_fc & EFX_FCNTL_GENERATE) ? IFM_ETH_TXPAUSE : 0); } #else /* !SFXGE_HAVE_PAUSE_MEDIAOPTS */ static unsigned int sfxge_port_wanted_fc(struct sfxge_softc *sc) { return (sc->port.wanted_fc); } static unsigned int sfxge_port_link_fc_ifm(struct sfxge_softc *sc) { return (0); } static int sfxge_port_wanted_fc_handler(SYSCTL_HANDLER_ARGS) { struct sfxge_softc *sc; struct sfxge_port *port; unsigned int fcntl; int error; sc = arg1; port = &sc->port; if (req->newptr != NULL) { if ((error = SYSCTL_IN(req, &fcntl, sizeof(fcntl))) != 0) return (error); SFXGE_PORT_LOCK(port); if (port->wanted_fc != fcntl) { if (port->init_state == SFXGE_PORT_STARTED) error = efx_mac_fcntl_set(sc->enp, port->wanted_fc, B_TRUE); if (error == 0) port->wanted_fc = fcntl; } SFXGE_PORT_UNLOCK(port); } else { SFXGE_PORT_LOCK(port); fcntl = port->wanted_fc; SFXGE_PORT_UNLOCK(port); error = SYSCTL_OUT(req, &fcntl, sizeof(fcntl)); } return (error); } static int sfxge_port_link_fc_handler(SYSCTL_HANDLER_ARGS) { struct sfxge_softc *sc; struct sfxge_port *port; unsigned int wanted_fc, link_fc; sc = arg1; port = &sc->port; SFXGE_PORT_LOCK(port); if (__predict_true(port->init_state == SFXGE_PORT_STARTED) && SFXGE_LINK_UP(sc)) efx_mac_fcntl_get(sc->enp, &wanted_fc, &link_fc); else link_fc = 0; SFXGE_PORT_UNLOCK(port); return (SYSCTL_OUT(req, &link_fc, sizeof(link_fc))); } #endif /* SFXGE_HAVE_PAUSE_MEDIAOPTS */ static const uint64_t sfxge_link_baudrate[EFX_LINK_NMODES] = { [EFX_LINK_10HDX] = IF_Mbps(10), [EFX_LINK_10FDX] = IF_Mbps(10), [EFX_LINK_100HDX] = IF_Mbps(100), [EFX_LINK_100FDX] = IF_Mbps(100), [EFX_LINK_1000HDX] = IF_Gbps(1), [EFX_LINK_1000FDX] = IF_Gbps(1), [EFX_LINK_10000FDX] = IF_Gbps(10), + [EFX_LINK_40000FDX] = IF_Gbps(40), }; void sfxge_mac_link_update(struct sfxge_softc *sc, efx_link_mode_t mode) { struct sfxge_port *port; int link_state; port = &sc->port; if (port->link_mode == mode) return; port->link_mode = mode; /* Push link state update to the OS */ link_state = (port->link_mode != EFX_LINK_DOWN ? LINK_STATE_UP : LINK_STATE_DOWN); sc->ifnet->if_baudrate = sfxge_link_baudrate[port->link_mode]; if_link_state_change(sc->ifnet, link_state); } static void sfxge_mac_poll_work(void *arg, int npending) { struct sfxge_softc *sc; efx_nic_t *enp; struct sfxge_port *port; efx_link_mode_t mode; sc = (struct sfxge_softc *)arg; enp = sc->enp; port = &sc->port; SFXGE_PORT_LOCK(port); if (__predict_false(port->init_state != SFXGE_PORT_STARTED)) goto done; /* This may sleep waiting for MCDI completion */ (void)efx_port_poll(enp, &mode); sfxge_mac_link_update(sc, mode); done: SFXGE_PORT_UNLOCK(port); } static int -sfxge_mac_filter_set_locked(struct sfxge_softc *sc) +sfxge_mac_multicast_list_set(struct sfxge_softc *sc) { - unsigned int bucket[EFX_MAC_HASH_BITS]; struct ifnet *ifp = sc->ifnet; + struct sfxge_port *port = &sc->port; + uint8_t *mcast_addr = port->mcast_addrs; struct ifmultiaddr *ifma; struct sockaddr_dl *sa; - efx_nic_t *enp = sc->enp; - unsigned int index; - int rc; + int rc = 0; - /* Set promisc-unicast and broadcast filter bits */ - if ((rc = efx_mac_filter_set(enp, !!(ifp->if_flags & IFF_PROMISC), - B_TRUE)) != 0) - return (rc); + mtx_assert(&port->lock, MA_OWNED); - /* Set multicast hash filter */ - if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { - for (index = 0; index < EFX_MAC_HASH_BITS; index++) - bucket[index] = 1; - } else { - /* Broadcast frames also go through the multicast - * filter, and the broadcast address hashes to - * 0xff. */ - bucket[0xff] = 1; - - if_maddr_rlock(ifp); - TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { - if (ifma->ifma_addr->sa_family == AF_LINK) { - sa = (struct sockaddr_dl *)ifma->ifma_addr; - index = ether_crc32_le(LLADDR(sa), 6) & 0xff; - bucket[index] = 1; + port->mcast_count = 0; + if_maddr_rlock(ifp); + TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { + if (ifma->ifma_addr->sa_family == AF_LINK) { + if (port->mcast_count == EFX_MAC_MULTICAST_LIST_MAX) { + device_printf(sc->dev, + "Too many multicast addresses\n"); + rc = EINVAL; + break; } + + sa = (struct sockaddr_dl *)ifma->ifma_addr; + memcpy(mcast_addr, LLADDR(sa), EFX_MAC_ADDR_LEN); + mcast_addr += EFX_MAC_ADDR_LEN; + ++port->mcast_count; } - if_maddr_runlock(ifp); } - return (efx_mac_hash_set(enp, bucket)); + if_maddr_runlock(ifp); + + if (rc == 0) { + rc = efx_mac_multicast_list_set(sc->enp, port->mcast_addrs, + port->mcast_count); + if (rc != 0) + device_printf(sc->dev, + "Cannot set multicast address list\n"); + } + + return (rc); } +static int +sfxge_mac_filter_set_locked(struct sfxge_softc *sc) +{ + struct ifnet *ifp = sc->ifnet; + struct sfxge_port *port = &sc->port; + boolean_t all_mulcst; + int rc; + + mtx_assert(&port->lock, MA_OWNED); + + all_mulcst = !!(ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)); + + rc = sfxge_mac_multicast_list_set(sc); + /* Fallback to all multicast if cannot set multicast list */ + if (rc != 0) + all_mulcst = B_TRUE; + + rc = efx_mac_filter_set(sc->enp, !!(ifp->if_flags & IFF_PROMISC), + (port->mcast_count > 0), all_mulcst, B_TRUE); + + return (rc); +} + int sfxge_mac_filter_set(struct sfxge_softc *sc) { struct sfxge_port *port = &sc->port; int rc; SFXGE_PORT_LOCK(port); /* * The function may be called without softc_lock held in the * case of SIOCADDMULTI and SIOCDELMULTI ioctls. ioctl handler * checks IFF_DRV_RUNNING flag which implies port started, but * it is not guaranteed to remain. softc_lock shared lock can't * be held in the case of these ioctls processing, since it * results in failure where kernel complains that non-sleepable * lock is held in sleeping thread. Both problems are repeatable * on LAG with LACP proto bring up. */ if (__predict_true(port->init_state == SFXGE_PORT_STARTED)) rc = sfxge_mac_filter_set_locked(sc); else rc = 0; SFXGE_PORT_UNLOCK(port); return (rc); } void sfxge_port_stop(struct sfxge_softc *sc) { struct sfxge_port *port; efx_nic_t *enp; port = &sc->port; enp = sc->enp; SFXGE_PORT_LOCK(port); KASSERT(port->init_state == SFXGE_PORT_STARTED, ("port not started")); port->init_state = SFXGE_PORT_INITIALIZED; port->mac_stats.update_time = 0; /* This may call MCDI */ (void)efx_mac_drain(enp, B_TRUE); (void)efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf, 0, B_FALSE); port->link_mode = EFX_LINK_UNKNOWN; /* Destroy the common code port object. */ - efx_port_fini(sc->enp); + efx_port_fini(enp); + efx_filter_fini(enp); + SFXGE_PORT_UNLOCK(port); } int sfxge_port_start(struct sfxge_softc *sc) { uint8_t mac_addr[ETHER_ADDR_LEN]; struct ifnet *ifp = sc->ifnet; struct sfxge_port *port; efx_nic_t *enp; size_t pdu; int rc; uint32_t phy_cap_mask; port = &sc->port; enp = sc->enp; SFXGE_PORT_LOCK(port); KASSERT(port->init_state == SFXGE_PORT_INITIALIZED, ("port not initialized")); + /* Initialise the required filtering */ + if ((rc = efx_filter_init(enp)) != 0) + goto fail_filter_init; + /* Initialize the port object in the common code. */ if ((rc = efx_port_init(sc->enp)) != 0) goto fail; /* Set the SDU */ pdu = EFX_MAC_PDU(ifp->if_mtu); if ((rc = efx_mac_pdu_set(enp, pdu)) != 0) goto fail2; if ((rc = efx_mac_fcntl_set(enp, sfxge_port_wanted_fc(sc), B_TRUE)) != 0) - goto fail2; + goto fail3; /* Set the unicast address */ if_addr_rlock(ifp); bcopy(LLADDR((struct sockaddr_dl *)ifp->if_addr->ifa_addr), mac_addr, sizeof(mac_addr)); if_addr_runlock(ifp); if ((rc = efx_mac_addr_set(enp, mac_addr)) != 0) - goto fail; + goto fail4; sfxge_mac_filter_set_locked(sc); /* Update MAC stats by DMA every second */ if ((rc = efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf, - 1000, B_FALSE)) != 0) - goto fail2; + 1000, B_FALSE)) != 0) + goto fail6; if ((rc = efx_mac_drain(enp, B_FALSE)) != 0) - goto fail3; + goto fail8; if ((rc = sfxge_phy_cap_mask(sc, sc->media.ifm_cur->ifm_media, &phy_cap_mask)) != 0) - goto fail4; + goto fail9; if ((rc = efx_phy_adv_cap_set(sc->enp, phy_cap_mask)) != 0) - goto fail5; + goto fail10; port->init_state = SFXGE_PORT_STARTED; /* Single poll in case there were missing initial events */ SFXGE_PORT_UNLOCK(port); sfxge_mac_poll_work(sc, 0); return (0); -fail5: -fail4: +fail10: +fail9: (void)efx_mac_drain(enp, B_TRUE); +fail8: + (void)efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf, 0, B_FALSE); +fail6: +fail4: fail3: - (void)efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf, - 0, B_FALSE); + fail2: - efx_port_fini(sc->enp); + efx_port_fini(enp); fail: + efx_filter_fini(enp); +fail_filter_init: SFXGE_PORT_UNLOCK(port); return (rc); } static int sfxge_phy_stat_update(struct sfxge_softc *sc) { struct sfxge_port *port = &sc->port; efsys_mem_t *esmp = &port->phy_stats.dma_buf; clock_t now; unsigned int count; int rc; SFXGE_PORT_LOCK_ASSERT_OWNED(port); if (__predict_false(port->init_state != SFXGE_PORT_STARTED)) { rc = 0; goto out; } now = ticks; if (now - port->phy_stats.update_time < hz) { rc = 0; goto out; } port->phy_stats.update_time = now; /* If we're unlucky enough to read statistics wduring the DMA, wait * up to 10ms for it to finish (typically takes <500us) */ for (count = 0; count < 100; ++count) { EFSYS_PROBE1(wait, unsigned int, count); /* Synchronize the DMA memory for reading */ bus_dmamap_sync(esmp->esm_tag, esmp->esm_map, BUS_DMASYNC_POSTREAD); /* Try to update the cached counters */ if ((rc = efx_phy_stats_update(sc->enp, esmp, port->phy_stats.decode_buf)) != EAGAIN) goto out; DELAY(100); } rc = ETIMEDOUT; out: return (rc); } static int sfxge_phy_stat_handler(SYSCTL_HANDLER_ARGS) { struct sfxge_softc *sc = arg1; unsigned int id = arg2; int rc; uint32_t val; SFXGE_PORT_LOCK(&sc->port); if ((rc = sfxge_phy_stat_update(sc)) == 0) val = ((uint32_t *)sc->port.phy_stats.decode_buf)[id]; SFXGE_PORT_UNLOCK(&sc->port); if (rc == 0) rc = SYSCTL_OUT(req, &val, sizeof(val)); return (rc); } static void sfxge_phy_stat_init(struct sfxge_softc *sc) { struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev); struct sysctl_oid_list *stat_list; unsigned int id; const char *name; uint64_t stat_mask = efx_nic_cfg_get(sc->enp)->enc_phy_stat_mask; stat_list = SYSCTL_CHILDREN(sc->stats_node); /* Initialise the named stats */ for (id = 0; id < EFX_PHY_NSTATS; id++) { if (!(stat_mask & ((uint64_t)1 << id))) continue; name = efx_phy_stat_name(sc->enp, id); SYSCTL_ADD_PROC( ctx, stat_list, OID_AUTO, name, CTLTYPE_UINT|CTLFLAG_RD, sc, id, sfxge_phy_stat_handler, id == EFX_PHY_STAT_OUI ? "IX" : "IU", ""); } } void sfxge_port_fini(struct sfxge_softc *sc) { struct sfxge_port *port; efsys_mem_t *esmp; port = &sc->port; esmp = &port->mac_stats.dma_buf; KASSERT(port->init_state == SFXGE_PORT_INITIALIZED, ("Port not initialized")); port->init_state = SFXGE_PORT_UNINITIALIZED; port->link_mode = EFX_LINK_UNKNOWN; /* Finish with PHY DMA memory */ sfxge_dma_free(&port->phy_stats.dma_buf); free(port->phy_stats.decode_buf, M_SFXGE); sfxge_dma_free(esmp); free(port->mac_stats.decode_buf, M_SFXGE); SFXGE_PORT_LOCK_DESTROY(port); port->sc = NULL; } int sfxge_port_init(struct sfxge_softc *sc) { struct sfxge_port *port; struct sysctl_ctx_list *sysctl_ctx; struct sysctl_oid *sysctl_tree; efsys_mem_t *mac_stats_buf, *phy_stats_buf; int rc; port = &sc->port; mac_stats_buf = &port->mac_stats.dma_buf; phy_stats_buf = &port->phy_stats.dma_buf; KASSERT(port->init_state == SFXGE_PORT_UNINITIALIZED, ("Port already initialized")); port->sc = sc; SFXGE_PORT_LOCK_INIT(port, device_get_nameunit(sc->dev)); + DBGPRINT(sc->dev, "alloc PHY stats"); port->phy_stats.decode_buf = malloc(EFX_PHY_NSTATS * sizeof(uint32_t), M_SFXGE, M_WAITOK | M_ZERO); if ((rc = sfxge_dma_alloc(sc, EFX_PHY_STATS_SIZE, phy_stats_buf)) != 0) goto fail; sfxge_phy_stat_init(sc); + DBGPRINT(sc->dev, "init sysctl"); sysctl_ctx = device_get_sysctl_ctx(sc->dev); sysctl_tree = device_get_sysctl_tree(sc->dev); #ifndef SFXGE_HAVE_PAUSE_MEDIAOPTS /* If flow control cannot be configured or reported through * ifmedia, provide sysctls for it. */ port->wanted_fc = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE; SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO, "wanted_fc", CTLTYPE_UINT|CTLFLAG_RW, sc, 0, sfxge_port_wanted_fc_handler, "IU", "wanted flow control mode"); SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO, "link_fc", CTLTYPE_UINT|CTLFLAG_RD, sc, 0, sfxge_port_link_fc_handler, "IU", "link flow control mode"); #endif + DBGPRINT(sc->dev, "alloc MAC stats"); port->mac_stats.decode_buf = malloc(EFX_MAC_NSTATS * sizeof(uint64_t), M_SFXGE, M_WAITOK | M_ZERO); if ((rc = sfxge_dma_alloc(sc, EFX_MAC_STATS_SIZE, mac_stats_buf)) != 0) goto fail2; sfxge_mac_stat_init(sc); port->init_state = SFXGE_PORT_INITIALIZED; + DBGPRINT(sc->dev, "success"); return (0); fail2: free(port->mac_stats.decode_buf, M_SFXGE); sfxge_dma_free(phy_stats_buf); fail: free(port->phy_stats.decode_buf, M_SFXGE); SFXGE_PORT_LOCK_DESTROY(port); port->sc = NULL; + DBGPRINT(sc->dev, "failed %d", rc); return (rc); } static const int sfxge_link_mode[EFX_PHY_MEDIA_NTYPES][EFX_LINK_NMODES] = { [EFX_PHY_MEDIA_CX4] = { [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_CX4, }, [EFX_PHY_MEDIA_KX4] = { [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_KX4, }, [EFX_PHY_MEDIA_XFP] = { /* Don't know the module type, but assume SR for now. */ [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_SR, }, + [EFX_PHY_MEDIA_QSFP_PLUS] = { + /* Don't know the module type, but assume SR for now. */ + [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_SR, + [EFX_LINK_40000FDX] = IFM_ETHER | IFM_FDX | IFM_40G_CR4, + }, [EFX_PHY_MEDIA_SFP_PLUS] = { /* Don't know the module type, but assume SX/SR for now. */ [EFX_LINK_1000FDX] = IFM_ETHER | IFM_FDX | IFM_1000_SX, [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_SR, }, [EFX_PHY_MEDIA_BASE_T] = { [EFX_LINK_10HDX] = IFM_ETHER | IFM_HDX | IFM_10_T, [EFX_LINK_10FDX] = IFM_ETHER | IFM_FDX | IFM_10_T, [EFX_LINK_100HDX] = IFM_ETHER | IFM_HDX | IFM_100_TX, [EFX_LINK_100FDX] = IFM_ETHER | IFM_FDX | IFM_100_TX, [EFX_LINK_1000HDX] = IFM_ETHER | IFM_HDX | IFM_1000_T, [EFX_LINK_1000FDX] = IFM_ETHER | IFM_FDX | IFM_1000_T, [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_T, }, }; static void sfxge_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) { struct sfxge_softc *sc; efx_phy_media_type_t medium_type; efx_link_mode_t mode; sc = ifp->if_softc; SFXGE_ADAPTER_LOCK(sc); ifmr->ifm_status = IFM_AVALID; ifmr->ifm_active = IFM_ETHER; if (SFXGE_RUNNING(sc) && SFXGE_LINK_UP(sc)) { ifmr->ifm_status |= IFM_ACTIVE; efx_phy_media_type_get(sc->enp, &medium_type); mode = sc->port.link_mode; ifmr->ifm_active |= sfxge_link_mode[medium_type][mode]; ifmr->ifm_active |= sfxge_port_link_fc_ifm(sc); } SFXGE_ADAPTER_UNLOCK(sc); } static efx_phy_cap_type_t sfxge_link_mode_to_phy_cap(efx_link_mode_t mode) { switch (mode) { case EFX_LINK_10HDX: return (EFX_PHY_CAP_10HDX); case EFX_LINK_10FDX: return (EFX_PHY_CAP_10FDX); case EFX_LINK_100HDX: return (EFX_PHY_CAP_100HDX); case EFX_LINK_100FDX: return (EFX_PHY_CAP_100FDX); case EFX_LINK_1000HDX: return (EFX_PHY_CAP_1000HDX); case EFX_LINK_1000FDX: return (EFX_PHY_CAP_1000FDX); case EFX_LINK_10000FDX: return (EFX_PHY_CAP_10000FDX); + case EFX_LINK_40000FDX: + return (EFX_PHY_CAP_40000FDX); default: EFSYS_ASSERT(B_FALSE); return (EFX_PHY_CAP_INVALID); } } static int sfxge_phy_cap_mask(struct sfxge_softc *sc, int ifmedia, uint32_t *phy_cap_mask) { efx_phy_media_type_t medium_type; boolean_t mode_found = B_FALSE; uint32_t cap_mask, mode_cap_mask; efx_link_mode_t mode; efx_phy_cap_type_t phy_cap; efx_phy_media_type_get(sc->enp, &medium_type); if (medium_type >= nitems(sfxge_link_mode)) { if_printf(sc->ifnet, "unexpected media type %d\n", medium_type); return (EINVAL); } efx_phy_adv_cap_get(sc->enp, EFX_PHY_CAP_PERM, &cap_mask); for (mode = EFX_LINK_10HDX; mode < EFX_LINK_NMODES; mode++) { if (ifmedia == sfxge_link_mode[medium_type][mode]) { mode_found = B_TRUE; break; } } if (!mode_found) { /* * If media is not in the table, it must be IFM_AUTO. */ KASSERT((cap_mask & (1 << EFX_PHY_CAP_AN)) && ifmedia == (IFM_ETHER | IFM_AUTO), ("%s: no mode for media %d", __func__, ifmedia)); *phy_cap_mask = (cap_mask & ~(1 << EFX_PHY_CAP_ASYM)); return (0); } phy_cap = sfxge_link_mode_to_phy_cap(mode); if (phy_cap == EFX_PHY_CAP_INVALID) { if_printf(sc->ifnet, "cannot map link mode %d to phy capability\n", mode); return (EINVAL); } mode_cap_mask = (1 << phy_cap); mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_AN); #ifdef SFXGE_HAVE_PAUSE_MEDIAOPTS if (ifmedia & IFM_ETH_RXPAUSE) mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_PAUSE); if (!(ifmedia & IFM_ETH_TXPAUSE)) mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_ASYM); #else mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_PAUSE); #endif *phy_cap_mask = mode_cap_mask; return (0); } static int sfxge_media_change(struct ifnet *ifp) { struct sfxge_softc *sc; struct ifmedia_entry *ifm; int rc; uint32_t phy_cap_mask; sc = ifp->if_softc; ifm = sc->media.ifm_cur; SFXGE_ADAPTER_LOCK(sc); if (!SFXGE_RUNNING(sc)) { rc = 0; goto out; } rc = efx_mac_fcntl_set(sc->enp, sfxge_port_wanted_fc(sc), B_TRUE); if (rc != 0) goto out; if ((rc = sfxge_phy_cap_mask(sc, ifm->ifm_media, &phy_cap_mask)) != 0) goto out; rc = efx_phy_adv_cap_set(sc->enp, phy_cap_mask); out: SFXGE_ADAPTER_UNLOCK(sc); return (rc); } int sfxge_port_ifmedia_init(struct sfxge_softc *sc) { efx_phy_media_type_t medium_type; uint32_t cap_mask, mode_cap_mask; efx_link_mode_t mode; efx_phy_cap_type_t phy_cap; int mode_ifm, best_mode_ifm = 0; int rc; - /* We need port state to initialise the ifmedia list. */ - if ((rc = efx_nic_init(sc->enp)) != 0) - goto out; + /* + * We need port state to initialise the ifmedia list. + * It requires initialized NIC what is already done in + * sfxge_create() when resources are estimated. + */ + if ((rc = efx_filter_init(sc->enp)) != 0) + goto out1; if ((rc = efx_port_init(sc->enp)) != 0) goto out2; /* * Register ifconfig callbacks for querying and setting the * link mode and link status. */ ifmedia_init(&sc->media, IFM_IMASK, sfxge_media_change, sfxge_media_status); /* * Map firmware medium type and capabilities to ifmedia types. * ifmedia does not distinguish between forcing the link mode * and disabling auto-negotiation. 1000BASE-T and 10GBASE-T * require AN even if only one link mode is enabled, and for * 100BASE-TX it is useful even if the link mode is forced. * Therefore we never disable auto-negotiation. * * Also enable and advertise flow control by default. */ efx_phy_media_type_get(sc->enp, &medium_type); efx_phy_adv_cap_get(sc->enp, EFX_PHY_CAP_PERM, &cap_mask); for (mode = EFX_LINK_10HDX; mode < EFX_LINK_NMODES; mode++) { phy_cap = sfxge_link_mode_to_phy_cap(mode); if (phy_cap == EFX_PHY_CAP_INVALID) continue; mode_cap_mask = (1 << phy_cap); mode_ifm = sfxge_link_mode[medium_type][mode]; if ((cap_mask & mode_cap_mask) && mode_ifm) { /* No flow-control */ ifmedia_add(&sc->media, mode_ifm, 0, NULL); #ifdef SFXGE_HAVE_PAUSE_MEDIAOPTS /* Respond-only. If using AN, we implicitly * offer symmetric as well, but that doesn't * mean we *have* to generate pause frames. */ mode_ifm |= IFM_ETH_RXPAUSE; ifmedia_add(&sc->media, mode_ifm, 0, NULL); /* Symmetric */ mode_ifm |= IFM_ETH_TXPAUSE; ifmedia_add(&sc->media, mode_ifm, 0, NULL); #endif /* Link modes are numbered in order of speed, * so assume the last one available is the best. */ best_mode_ifm = mode_ifm; } } if (cap_mask & (1 << EFX_PHY_CAP_AN)) { /* Add autoselect mode. */ mode_ifm = IFM_ETHER | IFM_AUTO; ifmedia_add(&sc->media, mode_ifm, 0, NULL); best_mode_ifm = mode_ifm; } if (best_mode_ifm != 0) ifmedia_set(&sc->media, best_mode_ifm); /* Now discard port state until interface is started. */ efx_port_fini(sc->enp); out2: - efx_nic_fini(sc->enp); -out: + efx_filter_fini(sc->enp); +out1: return (rc); } Property changes on: head/sys/dev/sfxge/sfxge_port.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/sfxge_rx.c =================================================================== --- head/sys/dev/sfxge/sfxge_rx.c (revision 283513) +++ head/sys/dev/sfxge/sfxge_rx.c (revision 283514) @@ -1,1339 +1,1420 @@ /*- - * Copyright (c) 2010-2011 Solarflare Communications, Inc. + * Copyright (c) 2010-2015 Solarflare Communications Inc. * All rights reserved. * * This software was developed in part by Philip Paeps under contract for * Solarflare Communications, Inc. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include +#include #include #include #include #include #include #include #include #include #include #include #include "common/efx.h" #include "sfxge.h" #include "sfxge_rx.h" #define RX_REFILL_THRESHOLD(_entries) (EFX_RXQ_LIMIT(_entries) * 9 / 10) #ifdef SFXGE_LRO SYSCTL_NODE(_hw_sfxge, OID_AUTO, lro, CTLFLAG_RD, NULL, "Large receive offload (LRO) parameters"); #define SFXGE_LRO_PARAM(_param) SFXGE_PARAM(lro._param) /* Size of the LRO hash table. Must be a power of 2. A larger table * means we can accelerate a larger number of streams. */ static unsigned lro_table_size = 128; TUNABLE_INT(SFXGE_LRO_PARAM(table_size), &lro_table_size); SYSCTL_UINT(_hw_sfxge_lro, OID_AUTO, table_size, CTLFLAG_RDTUN, &lro_table_size, 0, "Size of the LRO hash table (must be a power of 2)"); /* Maximum length of a hash chain. If chains get too long then the lookup * time increases and may exceed the benefit of LRO. */ static unsigned lro_chain_max = 20; TUNABLE_INT(SFXGE_LRO_PARAM(chain_max), &lro_chain_max); SYSCTL_UINT(_hw_sfxge_lro, OID_AUTO, chain_max, CTLFLAG_RDTUN, &lro_chain_max, 0, "The maximum length of a hash chain"); /* Maximum time (in ticks) that a connection can be idle before it's LRO * state is discarded. */ static unsigned lro_idle_ticks; /* initialised in sfxge_rx_init() */ TUNABLE_INT(SFXGE_LRO_PARAM(idle_ticks), &lro_idle_ticks); SYSCTL_UINT(_hw_sfxge_lro, OID_AUTO, idle_ticks, CTLFLAG_RDTUN, &lro_idle_ticks, 0, "The maximum time (in ticks) that a connection can be idle " "before it's LRO state is discarded"); /* Number of packets with payload that must arrive in-order before a * connection is eligible for LRO. The idea is we should avoid coalescing * segments when the sender is in slow-start because reducing the ACK rate * can damage performance. */ static int lro_slow_start_packets = 2000; TUNABLE_INT(SFXGE_LRO_PARAM(slow_start_packets), &lro_slow_start_packets); SYSCTL_UINT(_hw_sfxge_lro, OID_AUTO, slow_start_packets, CTLFLAG_RDTUN, &lro_slow_start_packets, 0, "Number of packets with payload that must arrive in-order before " "a connection is eligible for LRO"); /* Number of packets with payload that must arrive in-order following loss * before a connection is eligible for LRO. The idea is we should avoid * coalescing segments when the sender is recovering from loss, because * reducing the ACK rate can damage performance. */ static int lro_loss_packets = 20; TUNABLE_INT(SFXGE_LRO_PARAM(loss_packets), &lro_loss_packets); SYSCTL_UINT(_hw_sfxge_lro, OID_AUTO, loss_packets, CTLFLAG_RDTUN, &lro_loss_packets, 0, "Number of packets with payload that must arrive in-order " "following loss before a connection is eligible for LRO"); /* Flags for sfxge_lro_conn::l2_id; must not collide with EVL_VLID_MASK */ #define SFXGE_LRO_L2_ID_VLAN 0x4000 #define SFXGE_LRO_L2_ID_IPV6 0x8000 #define SFXGE_LRO_CONN_IS_VLAN_ENCAP(c) ((c)->l2_id & SFXGE_LRO_L2_ID_VLAN) #define SFXGE_LRO_CONN_IS_TCPIPV4(c) (!((c)->l2_id & SFXGE_LRO_L2_ID_IPV6)) /* Compare IPv6 addresses, avoiding conditional branches */ static unsigned long ipv6_addr_cmp(const struct in6_addr *left, const struct in6_addr *right) { #if LONG_BIT == 64 const uint64_t *left64 = (const uint64_t *)left; const uint64_t *right64 = (const uint64_t *)right; return (left64[0] - right64[0]) | (left64[1] - right64[1]); #else return (left->s6_addr32[0] - right->s6_addr32[0]) | (left->s6_addr32[1] - right->s6_addr32[1]) | (left->s6_addr32[2] - right->s6_addr32[2]) | (left->s6_addr32[3] - right->s6_addr32[3]); #endif } #endif /* SFXGE_LRO */ void sfxge_rx_qflush_done(struct sfxge_rxq *rxq) { rxq->flush_state = SFXGE_FLUSH_DONE; } void sfxge_rx_qflush_failed(struct sfxge_rxq *rxq) { rxq->flush_state = SFXGE_FLUSH_FAILED; } static uint8_t toep_key[] = { 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67, 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb, 0xae, 0x7b, 0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30, 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa }; static void sfxge_rx_post_refill(void *arg) { struct sfxge_rxq *rxq = arg; struct sfxge_softc *sc; unsigned int index; struct sfxge_evq *evq; uint16_t magic; sc = rxq->sc; index = rxq->index; evq = sc->evq[index]; magic = SFXGE_MAGIC_RX_QREFILL | index; /* This is guaranteed due to the start/stop order of rx and ev */ KASSERT(evq->init_state == SFXGE_EVQ_STARTED, ("evq not started")); KASSERT(rxq->init_state == SFXGE_RXQ_STARTED, ("rxq not started")); efx_ev_qpost(evq->common, magic); } static void sfxge_rx_schedule_refill(struct sfxge_rxq *rxq, boolean_t retrying) { /* Initially retry after 100 ms, but back off in case of * repeated failures as we probably have to wait for the * administrator to raise the pool limit. */ if (retrying) rxq->refill_delay = min(rxq->refill_delay * 2, 10 * hz); else rxq->refill_delay = hz / 10; callout_reset_curcpu(&rxq->refill_callout, rxq->refill_delay, sfxge_rx_post_refill, rxq); } static struct mbuf *sfxge_rx_alloc_mbuf(struct sfxge_softc *sc) { struct mb_args args; struct mbuf *m; /* Allocate mbuf structure */ args.flags = M_PKTHDR; args.type = MT_DATA; m = (struct mbuf *)uma_zalloc_arg(zone_mbuf, &args, M_NOWAIT); /* Allocate (and attach) packet buffer */ if (m != NULL && !uma_zalloc_arg(sc->rx_buffer_zone, m, M_NOWAIT)) { uma_zfree(zone_mbuf, m); m = NULL; } return (m); } #define SFXGE_REFILL_BATCH 64 static void sfxge_rx_qfill(struct sfxge_rxq *rxq, unsigned int target, boolean_t retrying) { struct sfxge_softc *sc; unsigned int index; struct sfxge_evq *evq; unsigned int batch; unsigned int rxfill; unsigned int mblksize; int ntodo; efsys_dma_addr_t addr[SFXGE_REFILL_BATCH]; sc = rxq->sc; index = rxq->index; evq = sc->evq[index]; prefetch_read_many(sc->enp); prefetch_read_many(rxq->common); SFXGE_EVQ_LOCK_ASSERT_OWNED(evq); if (__predict_false(rxq->init_state != SFXGE_RXQ_STARTED)) return; rxfill = rxq->added - rxq->completed; KASSERT(rxfill <= EFX_RXQ_LIMIT(rxq->entries), ("rxfill > EFX_RXQ_LIMIT(rxq->entries)")); ntodo = min(EFX_RXQ_LIMIT(rxq->entries) - rxfill, target); KASSERT(ntodo <= EFX_RXQ_LIMIT(rxq->entries), ("ntodo > EFX_RQX_LIMIT(rxq->entries)")); if (ntodo == 0) return; batch = 0; - mblksize = sc->rx_buffer_size; + mblksize = sc->rx_buffer_size - sc->rx_buffer_align; while (ntodo-- > 0) { unsigned int id; struct sfxge_rx_sw_desc *rx_desc; bus_dma_segment_t seg; struct mbuf *m; id = (rxq->added + batch) & rxq->ptr_mask; rx_desc = &rxq->queue[id]; KASSERT(rx_desc->mbuf == NULL, ("rx_desc->mbuf != NULL")); rx_desc->flags = EFX_DISCARD; m = rx_desc->mbuf = sfxge_rx_alloc_mbuf(sc); if (m == NULL) break; + + /* m_len specifies length of area to be mapped for DMA */ + m->m_len = mblksize; + m->m_data = (caddr_t)P2ROUNDUP((uintptr_t)m->m_data, CACHE_LINE_SIZE); + m->m_data += sc->rx_buffer_align; + sfxge_map_mbuf_fast(rxq->mem.esm_tag, rxq->mem.esm_map, m, &seg); addr[batch++] = seg.ds_addr; if (batch == SFXGE_REFILL_BATCH) { efx_rx_qpost(rxq->common, addr, mblksize, batch, rxq->completed, rxq->added); rxq->added += batch; batch = 0; } } if (ntodo != 0) sfxge_rx_schedule_refill(rxq, retrying); if (batch != 0) { efx_rx_qpost(rxq->common, addr, mblksize, batch, rxq->completed, rxq->added); rxq->added += batch; } /* Make the descriptors visible to the hardware */ bus_dmamap_sync(rxq->mem.esm_tag, rxq->mem.esm_map, BUS_DMASYNC_PREWRITE); - efx_rx_qpush(rxq->common, rxq->added); + efx_rx_qpush(rxq->common, rxq->added, &rxq->pushed); + + /* The queue could still be empty if no descriptors were actually + * pushed, in which case there will be no event to cause the next + * refill, so we must schedule a refill ourselves. + */ + if(rxq->pushed == rxq->completed) { + sfxge_rx_schedule_refill(rxq, retrying); + } } void sfxge_rx_qrefill(struct sfxge_rxq *rxq) { if (__predict_false(rxq->init_state != SFXGE_RXQ_STARTED)) return; /* Make sure the queue is full */ sfxge_rx_qfill(rxq, EFX_RXQ_LIMIT(rxq->entries), B_TRUE); } static void __sfxge_rx_deliver(struct sfxge_softc *sc, struct mbuf *m) { struct ifnet *ifp = sc->ifnet; m->m_pkthdr.rcvif = ifp; m->m_pkthdr.csum_data = 0xffff; ifp->if_input(ifp, m); } static void sfxge_rx_deliver(struct sfxge_softc *sc, struct sfxge_rx_sw_desc *rx_desc) { struct mbuf *m = rx_desc->mbuf; int flags = rx_desc->flags; int csum_flags; /* Convert checksum flags */ csum_flags = (flags & EFX_CKSUM_IPV4) ? (CSUM_IP_CHECKED | CSUM_IP_VALID) : 0; if (flags & EFX_CKSUM_TCPUDP) csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; if (flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) { - m->m_pkthdr.flowid = EFX_RX_HASH_VALUE(EFX_RX_HASHALG_TOEPLITZ, - mtod(m, uint8_t *)); + m->m_pkthdr.flowid = + efx_psuedo_hdr_hash_get(sc->enp, + EFX_RX_HASHALG_TOEPLITZ, + mtod(m, uint8_t *)); /* The hash covers a 4-tuple for TCP only */ M_HASHTYPE_SET(m, (flags & EFX_PKT_IPV4) ? ((flags & EFX_PKT_TCP) ? M_HASHTYPE_RSS_TCP_IPV4 : M_HASHTYPE_RSS_IPV4) : ((flags & EFX_PKT_TCP) ? M_HASHTYPE_RSS_TCP_IPV6 : M_HASHTYPE_RSS_IPV6)); } m->m_data += sc->rx_prefix_size; m->m_len = rx_desc->size - sc->rx_prefix_size; m->m_pkthdr.len = m->m_len; m->m_pkthdr.csum_flags = csum_flags; __sfxge_rx_deliver(sc, rx_desc->mbuf); rx_desc->flags = EFX_DISCARD; rx_desc->mbuf = NULL; } #ifdef SFXGE_LRO static void sfxge_lro_deliver(struct sfxge_lro_state *st, struct sfxge_lro_conn *c) { struct sfxge_softc *sc = st->sc; struct mbuf *m = c->mbuf; struct tcphdr *c_th; int csum_flags; KASSERT(m, ("no mbuf to deliver")); ++st->n_bursts; /* Finish off packet munging and recalculate IP header checksum. */ if (SFXGE_LRO_CONN_IS_TCPIPV4(c)) { struct ip *iph = c->nh; iph->ip_len = htons(iph->ip_len); iph->ip_sum = 0; iph->ip_sum = in_cksum_hdr(iph); c_th = (struct tcphdr *)(iph + 1); csum_flags = (CSUM_DATA_VALID | CSUM_PSEUDO_HDR | CSUM_IP_CHECKED | CSUM_IP_VALID); } else { struct ip6_hdr *iph = c->nh; iph->ip6_plen = htons(iph->ip6_plen); c_th = (struct tcphdr *)(iph + 1); csum_flags = CSUM_DATA_VALID | CSUM_PSEUDO_HDR; } c_th->th_win = c->th_last->th_win; c_th->th_ack = c->th_last->th_ack; if (c_th->th_off == c->th_last->th_off) { /* Copy TCP options (take care to avoid going negative). */ int optlen = ((c_th->th_off - 5) & 0xf) << 2u; memcpy(c_th + 1, c->th_last + 1, optlen); } m->m_pkthdr.flowid = c->conn_hash; M_HASHTYPE_SET(m, SFXGE_LRO_CONN_IS_TCPIPV4(c) ? M_HASHTYPE_RSS_TCP_IPV4 : M_HASHTYPE_RSS_TCP_IPV6); m->m_pkthdr.csum_flags = csum_flags; __sfxge_rx_deliver(sc, m); c->mbuf = NULL; c->delivered = 1; } /* Drop the given connection, and add it to the free list. */ static void sfxge_lro_drop(struct sfxge_rxq *rxq, struct sfxge_lro_conn *c) { unsigned bucket; KASSERT(!c->mbuf, ("found orphaned mbuf")); if (c->next_buf.mbuf != NULL) { sfxge_rx_deliver(rxq->sc, &c->next_buf); LIST_REMOVE(c, active_link); } bucket = c->conn_hash & rxq->lro.conns_mask; KASSERT(rxq->lro.conns_n[bucket] > 0, ("LRO: bucket fill level wrong")); --rxq->lro.conns_n[bucket]; TAILQ_REMOVE(&rxq->lro.conns[bucket], c, link); TAILQ_INSERT_HEAD(&rxq->lro.free_conns, c, link); } /* Stop tracking connections that have gone idle in order to keep hash * chains short. */ static void sfxge_lro_purge_idle(struct sfxge_rxq *rxq, unsigned now) { struct sfxge_lro_conn *c; unsigned i; KASSERT(LIST_EMPTY(&rxq->lro.active_conns), ("found active connections")); rxq->lro.last_purge_ticks = now; for (i = 0; i <= rxq->lro.conns_mask; ++i) { if (TAILQ_EMPTY(&rxq->lro.conns[i])) continue; c = TAILQ_LAST(&rxq->lro.conns[i], sfxge_lro_tailq); if (now - c->last_pkt_ticks > lro_idle_ticks) { ++rxq->lro.n_drop_idle; sfxge_lro_drop(rxq, c); } } } static void sfxge_lro_merge(struct sfxge_lro_state *st, struct sfxge_lro_conn *c, struct mbuf *mbuf, struct tcphdr *th) { struct tcphdr *c_th; /* Tack the new mbuf onto the chain. */ KASSERT(!mbuf->m_next, ("mbuf already chained")); c->mbuf_tail->m_next = mbuf; c->mbuf_tail = mbuf; /* Increase length appropriately */ c->mbuf->m_pkthdr.len += mbuf->m_len; /* Update the connection state flags */ if (SFXGE_LRO_CONN_IS_TCPIPV4(c)) { struct ip *iph = c->nh; iph->ip_len += mbuf->m_len; c_th = (struct tcphdr *)(iph + 1); } else { struct ip6_hdr *iph = c->nh; iph->ip6_plen += mbuf->m_len; c_th = (struct tcphdr *)(iph + 1); } c_th->th_flags |= (th->th_flags & TH_PUSH); c->th_last = th; ++st->n_merges; /* Pass packet up now if another segment could overflow the IP * length. */ if (c->mbuf->m_pkthdr.len > 65536 - 9200) sfxge_lro_deliver(st, c); } static void sfxge_lro_start(struct sfxge_lro_state *st, struct sfxge_lro_conn *c, struct mbuf *mbuf, void *nh, struct tcphdr *th) { /* Start the chain */ c->mbuf = mbuf; c->mbuf_tail = c->mbuf; c->nh = nh; c->th_last = th; mbuf->m_pkthdr.len = mbuf->m_len; /* Mangle header fields for later processing */ if (SFXGE_LRO_CONN_IS_TCPIPV4(c)) { struct ip *iph = nh; iph->ip_len = ntohs(iph->ip_len); } else { struct ip6_hdr *iph = nh; iph->ip6_plen = ntohs(iph->ip6_plen); } } /* Try to merge or otherwise hold or deliver (as appropriate) the * packet buffered for this connection (c->next_buf). Return a flag * indicating whether the connection is still active for LRO purposes. */ static int sfxge_lro_try_merge(struct sfxge_rxq *rxq, struct sfxge_lro_conn *c) { struct sfxge_rx_sw_desc *rx_buf = &c->next_buf; char *eh = c->next_eh; int data_length, hdr_length, dont_merge; unsigned th_seq, pkt_length; struct tcphdr *th; unsigned now; if (SFXGE_LRO_CONN_IS_TCPIPV4(c)) { struct ip *iph = c->next_nh; th = (struct tcphdr *)(iph + 1); pkt_length = ntohs(iph->ip_len) + (char *) iph - eh; } else { struct ip6_hdr *iph = c->next_nh; th = (struct tcphdr *)(iph + 1); pkt_length = ntohs(iph->ip6_plen) + (char *) th - eh; } hdr_length = (char *) th + th->th_off * 4 - eh; data_length = (min(pkt_length, rx_buf->size - rxq->sc->rx_prefix_size) - hdr_length); th_seq = ntohl(th->th_seq); dont_merge = ((data_length <= 0) | (th->th_flags & (TH_URG | TH_SYN | TH_RST | TH_FIN))); /* Check for options other than aligned timestamp. */ if (th->th_off != 5) { const uint32_t *opt_ptr = (const uint32_t *) (th + 1); if (th->th_off == 8 && opt_ptr[0] == ntohl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) { /* timestamp option -- okay */ } else { dont_merge = 1; } } if (__predict_false(th_seq != c->next_seq)) { /* Out-of-order, so start counting again. */ if (c->mbuf != NULL) sfxge_lro_deliver(&rxq->lro, c); c->n_in_order_pkts -= lro_loss_packets; c->next_seq = th_seq + data_length; ++rxq->lro.n_misorder; goto deliver_buf_out; } c->next_seq = th_seq + data_length; now = ticks; if (now - c->last_pkt_ticks > lro_idle_ticks) { ++rxq->lro.n_drop_idle; if (c->mbuf != NULL) sfxge_lro_deliver(&rxq->lro, c); sfxge_lro_drop(rxq, c); return (0); } c->last_pkt_ticks = ticks; if (c->n_in_order_pkts < lro_slow_start_packets) { /* May be in slow-start, so don't merge. */ ++rxq->lro.n_slow_start; ++c->n_in_order_pkts; goto deliver_buf_out; } if (__predict_false(dont_merge)) { if (c->mbuf != NULL) sfxge_lro_deliver(&rxq->lro, c); if (th->th_flags & (TH_FIN | TH_RST)) { ++rxq->lro.n_drop_closed; sfxge_lro_drop(rxq, c); return (0); } goto deliver_buf_out; } rx_buf->mbuf->m_data += rxq->sc->rx_prefix_size; if (__predict_true(c->mbuf != NULL)) { /* Remove headers and any padding */ rx_buf->mbuf->m_data += hdr_length; rx_buf->mbuf->m_len = data_length; sfxge_lro_merge(&rxq->lro, c, rx_buf->mbuf, th); } else { /* Remove any padding */ rx_buf->mbuf->m_len = pkt_length; sfxge_lro_start(&rxq->lro, c, rx_buf->mbuf, c->next_nh, th); } rx_buf->mbuf = NULL; return (1); deliver_buf_out: sfxge_rx_deliver(rxq->sc, rx_buf); return (1); } static void sfxge_lro_new_conn(struct sfxge_lro_state *st, uint32_t conn_hash, uint16_t l2_id, void *nh, struct tcphdr *th) { unsigned bucket = conn_hash & st->conns_mask; struct sfxge_lro_conn *c; if (st->conns_n[bucket] >= lro_chain_max) { ++st->n_too_many; return; } if (!TAILQ_EMPTY(&st->free_conns)) { c = TAILQ_FIRST(&st->free_conns); TAILQ_REMOVE(&st->free_conns, c, link); } else { c = malloc(sizeof(*c), M_SFXGE, M_NOWAIT); if (c == NULL) return; c->mbuf = NULL; c->next_buf.mbuf = NULL; } /* Create the connection tracking data */ ++st->conns_n[bucket]; TAILQ_INSERT_HEAD(&st->conns[bucket], c, link); c->l2_id = l2_id; c->conn_hash = conn_hash; c->source = th->th_sport; c->dest = th->th_dport; c->n_in_order_pkts = 0; c->last_pkt_ticks = *(volatile int *)&ticks; c->delivered = 0; ++st->n_new_stream; /* NB. We don't initialise c->next_seq, and it doesn't matter what * value it has. Most likely the next packet received for this * connection will not match -- no harm done. */ } /* Process mbuf and decide whether to dispatch it to the stack now or * later. */ static void sfxge_lro(struct sfxge_rxq *rxq, struct sfxge_rx_sw_desc *rx_buf) { struct sfxge_softc *sc = rxq->sc; struct mbuf *m = rx_buf->mbuf; struct ether_header *eh; struct sfxge_lro_conn *c; uint16_t l2_id; uint16_t l3_proto; void *nh; struct tcphdr *th; uint32_t conn_hash; unsigned bucket; /* Get the hardware hash */ - conn_hash = EFX_RX_HASH_VALUE(EFX_RX_HASHALG_TOEPLITZ, - mtod(m, uint8_t *)); + conn_hash = efx_psuedo_hdr_hash_get(sc->enp, + EFX_RX_HASHALG_TOEPLITZ, + mtod(m, uint8_t *)); eh = (struct ether_header *)(m->m_data + sc->rx_prefix_size); if (eh->ether_type == htons(ETHERTYPE_VLAN)) { struct ether_vlan_header *veh = (struct ether_vlan_header *)eh; l2_id = EVL_VLANOFTAG(ntohs(veh->evl_tag)) | SFXGE_LRO_L2_ID_VLAN; l3_proto = veh->evl_proto; nh = veh + 1; } else { l2_id = 0; l3_proto = eh->ether_type; nh = eh + 1; } /* Check whether this is a suitable packet (unfragmented * TCP/IPv4 or TCP/IPv6). If so, find the TCP header and * length, and compute a hash if necessary. If not, return. */ if (l3_proto == htons(ETHERTYPE_IP)) { struct ip *iph = nh; KASSERT(iph->ip_p == IPPROTO_TCP, ("IPv4 protocol is not TCP, but packet marker is set")); if ((iph->ip_hl - (sizeof(*iph) >> 2u)) | (iph->ip_off & htons(IP_MF | IP_OFFMASK))) goto deliver_now; th = (struct tcphdr *)(iph + 1); } else if (l3_proto == htons(ETHERTYPE_IPV6)) { struct ip6_hdr *iph = nh; KASSERT(iph->ip6_nxt == IPPROTO_TCP, ("IPv6 next header is not TCP, but packet marker is set")); l2_id |= SFXGE_LRO_L2_ID_IPV6; th = (struct tcphdr *)(iph + 1); } else { goto deliver_now; } bucket = conn_hash & rxq->lro.conns_mask; TAILQ_FOREACH(c, &rxq->lro.conns[bucket], link) { if ((c->l2_id - l2_id) | (c->conn_hash - conn_hash)) continue; if ((c->source - th->th_sport) | (c->dest - th->th_dport)) continue; if (c->mbuf != NULL) { if (SFXGE_LRO_CONN_IS_TCPIPV4(c)) { struct ip *c_iph, *iph = nh; c_iph = c->nh; if ((c_iph->ip_src.s_addr - iph->ip_src.s_addr) | (c_iph->ip_dst.s_addr - iph->ip_dst.s_addr)) continue; } else { struct ip6_hdr *c_iph, *iph = nh; c_iph = c->nh; if (ipv6_addr_cmp(&c_iph->ip6_src, &iph->ip6_src) | ipv6_addr_cmp(&c_iph->ip6_dst, &iph->ip6_dst)) continue; } } /* Re-insert at head of list to reduce lookup time. */ TAILQ_REMOVE(&rxq->lro.conns[bucket], c, link); TAILQ_INSERT_HEAD(&rxq->lro.conns[bucket], c, link); if (c->next_buf.mbuf != NULL) { if (!sfxge_lro_try_merge(rxq, c)) goto deliver_now; } else { LIST_INSERT_HEAD(&rxq->lro.active_conns, c, active_link); } c->next_buf = *rx_buf; c->next_eh = eh; c->next_nh = nh; rx_buf->mbuf = NULL; rx_buf->flags = EFX_DISCARD; return; } sfxge_lro_new_conn(&rxq->lro, conn_hash, l2_id, nh, th); deliver_now: sfxge_rx_deliver(sc, rx_buf); } static void sfxge_lro_end_of_burst(struct sfxge_rxq *rxq) { struct sfxge_lro_state *st = &rxq->lro; struct sfxge_lro_conn *c; unsigned t; while (!LIST_EMPTY(&st->active_conns)) { c = LIST_FIRST(&st->active_conns); if (!c->delivered && c->mbuf != NULL) sfxge_lro_deliver(st, c); if (sfxge_lro_try_merge(rxq, c)) { if (c->mbuf != NULL) sfxge_lro_deliver(st, c); LIST_REMOVE(c, active_link); } c->delivered = 0; } t = *(volatile int *)&ticks; if (__predict_false(t != st->last_purge_ticks)) sfxge_lro_purge_idle(rxq, t); } #else /* !SFXGE_LRO */ static void sfxge_lro(struct sfxge_rxq *rxq, struct sfxge_rx_sw_desc *rx_buf) { } static void sfxge_lro_end_of_burst(struct sfxge_rxq *rxq) { } #endif /* SFXGE_LRO */ void sfxge_rx_qcomplete(struct sfxge_rxq *rxq, boolean_t eop) { struct sfxge_softc *sc = rxq->sc; int if_capenable = sc->ifnet->if_capenable; int lro_enabled = if_capenable & IFCAP_LRO; unsigned int index; struct sfxge_evq *evq; unsigned int completed; unsigned int level; struct mbuf *m; struct sfxge_rx_sw_desc *prev = NULL; index = rxq->index; evq = sc->evq[index]; SFXGE_EVQ_LOCK_ASSERT_OWNED(evq); completed = rxq->completed; while (completed != rxq->pending) { unsigned int id; struct sfxge_rx_sw_desc *rx_desc; id = completed++ & rxq->ptr_mask; rx_desc = &rxq->queue[id]; m = rx_desc->mbuf; if (__predict_false(rxq->init_state != SFXGE_RXQ_STARTED)) goto discard; if (rx_desc->flags & (EFX_ADDR_MISMATCH | EFX_DISCARD)) goto discard; + /* Read the length from the psuedo header if required */ + if (rx_desc->flags & EFX_PKT_PREFIX_LEN) { + uint16_t tmp_size; + int rc; + rc = efx_psuedo_hdr_pkt_length_get(sc->enp, + mtod(m, uint8_t *), + &tmp_size); + KASSERT(rc == 0, ("cannot get packet length: %d", rc)); + rx_desc->size = (int)tmp_size + sc->rx_prefix_size; + } + prefetch_read_many(mtod(m, caddr_t)); switch (rx_desc->flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) { case EFX_PKT_IPV4: if (~if_capenable & IFCAP_RXCSUM) rx_desc->flags &= ~(EFX_CKSUM_IPV4 | EFX_CKSUM_TCPUDP); break; case EFX_PKT_IPV6: if (~if_capenable & IFCAP_RXCSUM_IPV6) rx_desc->flags &= ~EFX_CKSUM_TCPUDP; break; case 0: /* Check for loopback packets */ { struct ether_header *etherhp; /*LINTED*/ etherhp = mtod(m, struct ether_header *); if (etherhp->ether_type == htons(SFXGE_ETHERTYPE_LOOPBACK)) { EFSYS_PROBE(loopback); rxq->loopback++; goto discard; } } break; default: KASSERT(B_FALSE, ("Rx descriptor with both IPv4 and IPv6 flags")); goto discard; } /* Pass packet up the stack or into LRO (pipelined) */ if (prev != NULL) { if (lro_enabled && ((prev->flags & (EFX_PKT_TCP | EFX_CKSUM_TCPUDP)) == (EFX_PKT_TCP | EFX_CKSUM_TCPUDP))) sfxge_lro(rxq, prev); else sfxge_rx_deliver(sc, prev); } prev = rx_desc; continue; discard: /* Return the packet to the pool */ m_free(m); rx_desc->mbuf = NULL; } rxq->completed = completed; level = rxq->added - rxq->completed; /* Pass last packet up the stack or into LRO */ if (prev != NULL) { if (lro_enabled && ((prev->flags & (EFX_PKT_TCP | EFX_CKSUM_TCPUDP)) == (EFX_PKT_TCP | EFX_CKSUM_TCPUDP))) sfxge_lro(rxq, prev); else sfxge_rx_deliver(sc, prev); } /* * If there are any pending flows and this is the end of the * poll then they must be completed. */ if (eop) sfxge_lro_end_of_burst(rxq); /* Top up the queue if necessary */ if (level < rxq->refill_threshold) sfxge_rx_qfill(rxq, EFX_RXQ_LIMIT(rxq->entries), B_FALSE); } static void sfxge_rx_qstop(struct sfxge_softc *sc, unsigned int index) { struct sfxge_rxq *rxq; struct sfxge_evq *evq; unsigned int count; + unsigned int retry = 3; + SFXGE_ADAPTER_LOCK_ASSERT_OWNED(sc); + rxq = sc->rxq[index]; evq = sc->evq[index]; SFXGE_EVQ_LOCK(evq); KASSERT(rxq->init_state == SFXGE_RXQ_STARTED, ("rxq not started")); rxq->init_state = SFXGE_RXQ_INITIALIZED; callout_stop(&rxq->refill_callout); -again: - rxq->flush_state = SFXGE_FLUSH_PENDING; + while (rxq->flush_state != SFXGE_FLUSH_DONE && retry != 0) { + rxq->flush_state = SFXGE_FLUSH_PENDING; - /* Flush the receive queue */ - efx_rx_qflush(rxq->common); + SFXGE_EVQ_UNLOCK(evq); - SFXGE_EVQ_UNLOCK(evq); - - count = 0; - do { - /* Spin for 100 ms */ - DELAY(100000); - - if (rxq->flush_state != SFXGE_FLUSH_PENDING) + /* Flush the receive queue */ + if (efx_rx_qflush(rxq->common) != 0) { + SFXGE_EVQ_LOCK(evq); + rxq->flush_state = SFXGE_FLUSH_FAILED; break; + } - } while (++count < 20); + count = 0; + do { + /* Spin for 100 ms */ + DELAY(100000); - SFXGE_EVQ_LOCK(evq); + if (rxq->flush_state != SFXGE_FLUSH_PENDING) + break; - if (rxq->flush_state == SFXGE_FLUSH_FAILED) - goto again; + } while (++count < 20); - rxq->flush_state = SFXGE_FLUSH_DONE; + SFXGE_EVQ_LOCK(evq); + if (rxq->flush_state == SFXGE_FLUSH_PENDING) { + /* Flush timeout - neither done nor failed */ + log(LOG_ERR, "%s: Cannot flush Rx queue %u\n", + device_get_nameunit(sc->dev), index); + rxq->flush_state = SFXGE_FLUSH_DONE; + } + retry--; + } + if (rxq->flush_state == SFXGE_FLUSH_FAILED) { + log(LOG_ERR, "%s: Flushing Rx queue %u failed\n", + device_get_nameunit(sc->dev), index); + rxq->flush_state = SFXGE_FLUSH_DONE; + } + rxq->pending = rxq->added; sfxge_rx_qcomplete(rxq, B_TRUE); KASSERT(rxq->completed == rxq->pending, ("rxq->completed != rxq->pending")); rxq->added = 0; + rxq->pushed = 0; rxq->pending = 0; rxq->completed = 0; rxq->loopback = 0; /* Destroy the common code receive queue. */ efx_rx_qdestroy(rxq->common); efx_sram_buf_tbl_clear(sc->enp, rxq->buf_base_id, EFX_RXQ_NBUFS(sc->rxq_entries)); SFXGE_EVQ_UNLOCK(evq); } static int sfxge_rx_qstart(struct sfxge_softc *sc, unsigned int index) { struct sfxge_rxq *rxq; efsys_mem_t *esmp; struct sfxge_evq *evq; int rc; + SFXGE_ADAPTER_LOCK_ASSERT_OWNED(sc); + rxq = sc->rxq[index]; esmp = &rxq->mem; evq = sc->evq[index]; KASSERT(rxq->init_state == SFXGE_RXQ_INITIALIZED, ("rxq->init_state != SFXGE_RXQ_INITIALIZED")); KASSERT(evq->init_state == SFXGE_EVQ_STARTED, ("evq->init_state != SFXGE_EVQ_STARTED")); /* Program the buffer table. */ if ((rc = efx_sram_buf_tbl_set(sc->enp, rxq->buf_base_id, esmp, EFX_RXQ_NBUFS(sc->rxq_entries))) != 0) return (rc); /* Create the common code receive queue. */ if ((rc = efx_rx_qcreate(sc->enp, index, index, EFX_RXQ_TYPE_DEFAULT, esmp, sc->rxq_entries, rxq->buf_base_id, evq->common, &rxq->common)) != 0) goto fail; SFXGE_EVQ_LOCK(evq); /* Enable the receive queue. */ efx_rx_qenable(rxq->common); rxq->init_state = SFXGE_RXQ_STARTED; + rxq->flush_state = SFXGE_FLUSH_REQUIRED; /* Try to fill the queue from the pool. */ sfxge_rx_qfill(rxq, EFX_RXQ_LIMIT(sc->rxq_entries), B_FALSE); SFXGE_EVQ_UNLOCK(evq); return (0); fail: efx_sram_buf_tbl_clear(sc->enp, rxq->buf_base_id, EFX_RXQ_NBUFS(sc->rxq_entries)); return (rc); } void sfxge_rx_stop(struct sfxge_softc *sc) { int index; + efx_mac_filter_default_rxq_clear(sc->enp); + /* Stop the receive queue(s) */ index = sc->rxq_count; while (--index >= 0) sfxge_rx_qstop(sc, index); sc->rx_prefix_size = 0; sc->rx_buffer_size = 0; efx_rx_fini(sc->enp); } int sfxge_rx_start(struct sfxge_softc *sc) { struct sfxge_intr *intr; + const efx_nic_cfg_t *encp; + size_t hdrlen, align, reserved; int index; int rc; intr = &sc->intr; /* Initialize the common code receive module. */ if ((rc = efx_rx_init(sc->enp)) != 0) return (rc); - /* Calculate the receive packet buffer size. */ - sc->rx_prefix_size = EFX_RX_PREFIX_SIZE; - sc->rx_buffer_size = (EFX_MAC_PDU(sc->ifnet->if_mtu) + - sc->rx_prefix_size); + encp = efx_nic_cfg_get(sc->enp); + sc->rx_buffer_size = EFX_MAC_PDU(sc->ifnet->if_mtu); + /* Calculate the receive packet buffer size. */ + sc->rx_prefix_size = encp->enc_rx_prefix_size; + + /* Ensure IP headers are 32bit aligned */ + hdrlen = sc->rx_prefix_size + sizeof (struct ether_header); + sc->rx_buffer_align = P2ROUNDUP(hdrlen, 4) - hdrlen; + + sc->rx_buffer_size += sc->rx_buffer_align; + + /* Align end of packet buffer for RX DMA end padding */ + align = MAX(1, encp->enc_rx_buf_align_end); + EFSYS_ASSERT(ISP2(align)); + sc->rx_buffer_size = P2ROUNDUP(sc->rx_buffer_size, align); + + /* + * Standard mbuf zones only guarantee pointer-size alignment; + * we need extra space to align to the cache line + */ + reserved = sc->rx_buffer_size + CACHE_LINE_SIZE; + /* Select zone for packet buffers */ - if (sc->rx_buffer_size <= MCLBYTES) + if (reserved <= MCLBYTES) sc->rx_buffer_zone = zone_clust; - else if (sc->rx_buffer_size <= MJUMPAGESIZE) + else if (reserved <= MJUMPAGESIZE) sc->rx_buffer_zone = zone_jumbop; - else if (sc->rx_buffer_size <= MJUM9BYTES) + else if (reserved <= MJUM9BYTES) sc->rx_buffer_zone = zone_jumbo9; else sc->rx_buffer_zone = zone_jumbo16; /* * Set up the scale table. Enable all hash types and hash insertion. */ for (index = 0; index < SFXGE_RX_SCALE_MAX; index++) sc->rx_indir_table[index] = index % sc->rxq_count; if ((rc = efx_rx_scale_tbl_set(sc->enp, sc->rx_indir_table, SFXGE_RX_SCALE_MAX)) != 0) goto fail; (void)efx_rx_scale_mode_set(sc->enp, EFX_RX_HASHALG_TOEPLITZ, (1 << EFX_RX_HASH_IPV4) | (1 << EFX_RX_HASH_TCPIPV4) | (1 << EFX_RX_HASH_IPV6) | (1 << EFX_RX_HASH_TCPIPV6), B_TRUE); - if ((rc = efx_rx_scale_toeplitz_ipv4_key_set(sc->enp, toep_key, - sizeof(toep_key))) != 0) + if ((rc = efx_rx_scale_key_set(sc->enp, toep_key, + sizeof(toep_key))) != 0) goto fail; /* Start the receive queue(s). */ for (index = 0; index < sc->rxq_count; index++) { if ((rc = sfxge_rx_qstart(sc, index)) != 0) goto fail2; } + rc = efx_mac_filter_default_rxq_set(sc->enp, sc->rxq[0]->common, + sc->intr.n_alloc > 1); + if (rc != 0) + goto fail3; + return (0); +fail3: fail2: while (--index >= 0) sfxge_rx_qstop(sc, index); fail: efx_rx_fini(sc->enp); return (rc); } #ifdef SFXGE_LRO static void sfxge_lro_init(struct sfxge_rxq *rxq) { struct sfxge_lro_state *st = &rxq->lro; unsigned i; st->conns_mask = lro_table_size - 1; KASSERT(!((st->conns_mask + 1) & st->conns_mask), ("lro_table_size must be a power of 2")); st->sc = rxq->sc; st->conns = malloc((st->conns_mask + 1) * sizeof(st->conns[0]), M_SFXGE, M_WAITOK); st->conns_n = malloc((st->conns_mask + 1) * sizeof(st->conns_n[0]), M_SFXGE, M_WAITOK); for (i = 0; i <= st->conns_mask; ++i) { TAILQ_INIT(&st->conns[i]); st->conns_n[i] = 0; } LIST_INIT(&st->active_conns); TAILQ_INIT(&st->free_conns); } static void sfxge_lro_fini(struct sfxge_rxq *rxq) { struct sfxge_lro_state *st = &rxq->lro; struct sfxge_lro_conn *c; unsigned i; /* Return cleanly if sfxge_lro_init() has not been called. */ if (st->conns == NULL) return; KASSERT(LIST_EMPTY(&st->active_conns), ("found active connections")); for (i = 0; i <= st->conns_mask; ++i) { while (!TAILQ_EMPTY(&st->conns[i])) { c = TAILQ_LAST(&st->conns[i], sfxge_lro_tailq); sfxge_lro_drop(rxq, c); } } while (!TAILQ_EMPTY(&st->free_conns)) { c = TAILQ_FIRST(&st->free_conns); TAILQ_REMOVE(&st->free_conns, c, link); KASSERT(!c->mbuf, ("found orphaned mbuf")); free(c, M_SFXGE); } free(st->conns_n, M_SFXGE); free(st->conns, M_SFXGE); st->conns = NULL; } #else static void sfxge_lro_init(struct sfxge_rxq *rxq) { } static void sfxge_lro_fini(struct sfxge_rxq *rxq) { } #endif /* SFXGE_LRO */ static void sfxge_rx_qfini(struct sfxge_softc *sc, unsigned int index) { struct sfxge_rxq *rxq; rxq = sc->rxq[index]; KASSERT(rxq->init_state == SFXGE_RXQ_INITIALIZED, ("rxq->init_state != SFXGE_RXQ_INITIALIZED")); /* Free the context array and the flow table. */ free(rxq->queue, M_SFXGE); sfxge_lro_fini(rxq); /* Release DMA memory. */ sfxge_dma_free(&rxq->mem); sc->rxq[index] = NULL; free(rxq, M_SFXGE); } static int sfxge_rx_qinit(struct sfxge_softc *sc, unsigned int index) { struct sfxge_rxq *rxq; struct sfxge_evq *evq; efsys_mem_t *esmp; int rc; KASSERT(index < sc->rxq_count, ("index >= %d", sc->rxq_count)); rxq = malloc(sizeof(struct sfxge_rxq), M_SFXGE, M_ZERO | M_WAITOK); rxq->sc = sc; rxq->index = index; rxq->entries = sc->rxq_entries; rxq->ptr_mask = rxq->entries - 1; rxq->refill_threshold = RX_REFILL_THRESHOLD(rxq->entries); sc->rxq[index] = rxq; esmp = &rxq->mem; evq = sc->evq[index]; /* Allocate and zero DMA space. */ if ((rc = sfxge_dma_alloc(sc, EFX_RXQ_SIZE(sc->rxq_entries), esmp)) != 0) return (rc); /* Allocate buffer table entries. */ sfxge_sram_buf_tbl_alloc(sc, EFX_RXQ_NBUFS(sc->rxq_entries), &rxq->buf_base_id); /* Allocate the context array and the flow table. */ rxq->queue = malloc(sizeof(struct sfxge_rx_sw_desc) * sc->rxq_entries, M_SFXGE, M_WAITOK | M_ZERO); sfxge_lro_init(rxq); callout_init(&rxq->refill_callout, 1); rxq->init_state = SFXGE_RXQ_INITIALIZED; return (0); } static const struct { const char *name; size_t offset; } sfxge_rx_stats[] = { #define SFXGE_RX_STAT(name, member) \ { #name, offsetof(struct sfxge_rxq, member) } #ifdef SFXGE_LRO SFXGE_RX_STAT(lro_merges, lro.n_merges), SFXGE_RX_STAT(lro_bursts, lro.n_bursts), SFXGE_RX_STAT(lro_slow_start, lro.n_slow_start), SFXGE_RX_STAT(lro_misorder, lro.n_misorder), SFXGE_RX_STAT(lro_too_many, lro.n_too_many), SFXGE_RX_STAT(lro_new_stream, lro.n_new_stream), SFXGE_RX_STAT(lro_drop_idle, lro.n_drop_idle), SFXGE_RX_STAT(lro_drop_closed, lro.n_drop_closed) #endif }; static int sfxge_rx_stat_handler(SYSCTL_HANDLER_ARGS) { struct sfxge_softc *sc = arg1; unsigned int id = arg2; unsigned int sum, index; /* Sum across all RX queues */ sum = 0; for (index = 0; index < sc->rxq_count; index++) sum += *(unsigned int *)((caddr_t)sc->rxq[index] + sfxge_rx_stats[id].offset); return (SYSCTL_OUT(req, &sum, sizeof(sum))); } static void sfxge_rx_stat_init(struct sfxge_softc *sc) { struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev); struct sysctl_oid_list *stat_list; unsigned int id; stat_list = SYSCTL_CHILDREN(sc->stats_node); for (id = 0; id < nitems(sfxge_rx_stats); id++) { SYSCTL_ADD_PROC( ctx, stat_list, OID_AUTO, sfxge_rx_stats[id].name, CTLTYPE_UINT|CTLFLAG_RD, sc, id, sfxge_rx_stat_handler, "IU", ""); } } void sfxge_rx_fini(struct sfxge_softc *sc) { int index; index = sc->rxq_count; while (--index >= 0) sfxge_rx_qfini(sc, index); sc->rxq_count = 0; } int sfxge_rx_init(struct sfxge_softc *sc) { struct sfxge_intr *intr; int index; int rc; #ifdef SFXGE_LRO if (!ISP2(lro_table_size)) { log(LOG_ERR, "%s=%u must be power of 2", SFXGE_LRO_PARAM(table_size), lro_table_size); rc = EINVAL; goto fail_lro_table_size; } if (lro_idle_ticks == 0) lro_idle_ticks = hz / 10 + 1; /* 100 ms */ #endif intr = &sc->intr; sc->rxq_count = intr->n_alloc; KASSERT(intr->state == SFXGE_INTR_INITIALIZED, ("intr->state != SFXGE_INTR_INITIALIZED")); /* Initialize the receive queue(s) - one per interrupt. */ for (index = 0; index < sc->rxq_count; index++) { if ((rc = sfxge_rx_qinit(sc, index)) != 0) goto fail; } sfxge_rx_stat_init(sc); return (0); fail: /* Tear down the receive queue(s). */ while (--index >= 0) sfxge_rx_qfini(sc, index); sc->rxq_count = 0; #ifdef SFXGE_LRO fail_lro_table_size: #endif return (rc); } Property changes on: head/sys/dev/sfxge/sfxge_rx.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/sfxge_rx.h =================================================================== --- head/sys/dev/sfxge/sfxge_rx.h (revision 283513) +++ head/sys/dev/sfxge/sfxge_rx.h (revision 283514) @@ -1,205 +1,211 @@ /*- - * Copyright (c) 2010-2011 Solarflare Communications, Inc. + * Copyright (c) 2010-2015 Solarflare Communications Inc. * All rights reserved. * * This software was developed in part by Philip Paeps under contract for * Solarflare Communications, Inc. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + * * $FreeBSD$ */ #ifndef _SFXGE_RX_H #define _SFXGE_RX_H #include "opt_inet.h" #include "opt_inet6.h" #if defined(INET) || defined(INET6) #define SFXGE_LRO 1 #endif -#define SFXGE_MAGIC_RESERVED 0x8000 +#define SFXGE_MAGIC_RESERVED 0x8000 #define SFXGE_MAGIC_DMAQ_LABEL_WIDTH 6 -#define SFXGE_MAGIC_DMAQ_LABEL_MASK \ +#define SFXGE_MAGIC_DMAQ_LABEL_MASK \ ((1 << SFXGE_MAGIC_DMAQ_LABEL_WIDTH) - 1) -#define SFXGE_MAGIC_RX_QFLUSH_DONE \ +#define SFXGE_MAGIC_RX_QFLUSH_DONE \ (SFXGE_MAGIC_RESERVED | (1 << SFXGE_MAGIC_DMAQ_LABEL_WIDTH)) -#define SFXGE_MAGIC_RX_QFLUSH_FAILED \ +#define SFXGE_MAGIC_RX_QFLUSH_FAILED \ (SFXGE_MAGIC_RESERVED | (2 << SFXGE_MAGIC_DMAQ_LABEL_WIDTH)) -#define SFXGE_MAGIC_RX_QREFILL \ +#define SFXGE_MAGIC_RX_QREFILL \ (SFXGE_MAGIC_RESERVED | (3 << SFXGE_MAGIC_DMAQ_LABEL_WIDTH)) -#define SFXGE_MAGIC_TX_QFLUSH_DONE \ +#define SFXGE_MAGIC_TX_QFLUSH_DONE \ (SFXGE_MAGIC_RESERVED | (4 << SFXGE_MAGIC_DMAQ_LABEL_WIDTH)) #define SFXGE_RX_SCALE_MAX EFX_MAXRSS struct sfxge_rx_sw_desc { struct mbuf *mbuf; bus_dmamap_t map; int flags; int size; }; #ifdef SFXGE_LRO /** * struct sfxge_lro_conn - Connection state for software LRO * @link: Link for hash table and free list. * @active_link: Link for active_conns list * @l2_id: Identifying information from layer 2 * @conn_hash: Hash of connection 4-tuple * @nh: IP (v4 or v6) header of super-packet * @source: Source TCP port number * @dest: Destination TCP port number * @n_in_order_pkts: Number of in-order packets with payload. * @next_seq: Next in-order sequence number. * @last_pkt_ticks: Time we last saw a packet on this connection. * @mbuf: The mbuf we are currently holding. * If %NULL, then all following fields are undefined. * @mbuf_tail: The tail of the frag_list of mbufs we're holding. * Only valid after at least one merge. * @th_last: The TCP header of the last packet merged. * @next_buf: The next RX buffer to process. * @next_eh: Ethernet header of the next buffer. * @next_nh: IP header of the next buffer. * @delivered: True if we've delivered a payload packet up this interrupt. */ struct sfxge_lro_conn { TAILQ_ENTRY(sfxge_lro_conn) link; LIST_ENTRY(sfxge_lro_conn) active_link; uint16_t l2_id; uint32_t conn_hash; void *nh; uint16_t source, dest; int n_in_order_pkts; unsigned next_seq; unsigned last_pkt_ticks; struct mbuf *mbuf; struct mbuf *mbuf_tail; struct tcphdr *th_last; struct sfxge_rx_sw_desc next_buf; void *next_eh; void *next_nh; int delivered; }; /** * struct sfxge_lro_state - Port state for software LRO * @sc: The associated NIC. * @conns_mask: Number of hash buckets - 1. * @conns: Hash buckets for tracked connections. * @conns_n: Length of linked list for each hash bucket. * @active_conns: Connections that are holding a packet. * Connections are self-linked when not in this list. * @free_conns: Free sfxge_lro_conn instances. * @last_purge_ticks: The value of ticks last time we purged idle * connections. * @n_merges: Number of packets absorbed by LRO. * @n_bursts: Number of bursts spotted by LRO. * @n_slow_start: Number of packets not merged because connection may be in * slow-start. * @n_misorder: Number of out-of-order packets seen in tracked streams. * @n_too_many: Incremented when we're trying to track too many streams. * @n_new_stream: Number of distinct streams we've tracked. * @n_drop_idle: Number of streams discarded because they went idle. * @n_drop_closed: Number of streams that have seen a FIN or RST. */ struct sfxge_lro_state { struct sfxge_softc *sc; unsigned conns_mask; TAILQ_HEAD(sfxge_lro_tailq, sfxge_lro_conn) *conns; unsigned *conns_n; LIST_HEAD(, sfxge_lro_conn) active_conns; TAILQ_HEAD(, sfxge_lro_conn) free_conns; unsigned last_purge_ticks; unsigned n_merges; unsigned n_bursts; unsigned n_slow_start; unsigned n_misorder; unsigned n_too_many; unsigned n_new_stream; unsigned n_drop_idle; unsigned n_drop_closed; }; #endif /* SFXGE_LRO */ enum sfxge_flush_state { SFXGE_FLUSH_DONE = 0, + SFXGE_FLUSH_REQUIRED, SFXGE_FLUSH_PENDING, SFXGE_FLUSH_FAILED }; enum sfxge_rxq_state { SFXGE_RXQ_UNINITIALIZED = 0, SFXGE_RXQ_INITIALIZED, SFXGE_RXQ_STARTED }; #define SFXGE_RX_BATCH 128 struct sfxge_rxq { struct sfxge_softc *sc __aligned(CACHE_LINE_SIZE); unsigned int index; efsys_mem_t mem; unsigned int buf_base_id; enum sfxge_rxq_state init_state; unsigned int entries; unsigned int ptr_mask; struct sfxge_rx_sw_desc *queue __aligned(CACHE_LINE_SIZE); unsigned int added; + unsigned int pushed; unsigned int pending; unsigned int completed; unsigned int loopback; #ifdef SFXGE_LRO struct sfxge_lro_state lro; #endif unsigned int refill_threshold; struct callout refill_callout; unsigned int refill_delay; efx_rxq_t *common __aligned(CACHE_LINE_SIZE); volatile enum sfxge_flush_state flush_state; }; /* * From sfxge_rx.c. */ extern int sfxge_rx_init(struct sfxge_softc *sc); extern void sfxge_rx_fini(struct sfxge_softc *sc); extern int sfxge_rx_start(struct sfxge_softc *sc); extern void sfxge_rx_stop(struct sfxge_softc *sc); extern void sfxge_rx_qcomplete(struct sfxge_rxq *rxq, boolean_t eop); extern void sfxge_rx_qrefill(struct sfxge_rxq *rxq); extern void sfxge_rx_qflush_done(struct sfxge_rxq *rxq); extern void sfxge_rx_qflush_failed(struct sfxge_rxq *rxq); extern void sfxge_rx_scale_update(void *arg, int npending); #endif Property changes on: head/sys/dev/sfxge/sfxge_rx.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/sfxge_tx.c =================================================================== --- head/sys/dev/sfxge/sfxge_tx.c (revision 283513) +++ head/sys/dev/sfxge/sfxge_tx.c (revision 283514) @@ -1,1629 +1,1786 @@ /*- - * Copyright (c) 2010-2011 Solarflare Communications, Inc. + * Copyright (c) 2010-2015 Solarflare Communications Inc. * All rights reserved. * * This software was developed in part by Philip Paeps under contract for * Solarflare Communications, Inc. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. */ /* Theory of operation: * * Tx queues allocation and mapping * * One Tx queue with enabled checksum offload is allocated per Rx channel * (event queue). Also 2 Tx queues (one without checksum offload and one * with IP checksum offload only) are allocated and bound to event queue 0. * sfxge_txq_type is used as Tx queue label. * * So, event queue plus label mapping to Tx queue index is: * if event queue index is 0, TxQ-index = TxQ-label * [0..SFXGE_TXQ_NTYPES) * else TxQ-index = SFXGE_TXQ_NTYPES + EvQ-index - 1 * See sfxge_get_txq_by_label() sfxge_ev.c */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "common/efx.h" #include "sfxge.h" #include "sfxge_tx.h" -/* - * Estimate maximum number of Tx descriptors required for TSO packet. - * With minimum MSS and maximum mbuf length we might need more (even - * than a ring-ful of descriptors), but this should not happen in - * practice except due to deliberate attack. In that case we will - * truncate the output at a packet boundary. - */ -#define SFXGE_TSO_MAX_DESC \ - (SFXGE_TSO_MAX_SEGS * 2 + SFXGE_TX_MAPPING_MAX_SEG - 1) -/* - * Set the block level to ensure there is space to generate a - * large number of descriptors for TSO. - */ -#define SFXGE_TXQ_BLOCK_LEVEL(_entries) \ - (EFX_TXQ_LIMIT(_entries) - SFXGE_TSO_MAX_DESC) - - #define SFXGE_PARAM_TX_DPL_GET_MAX SFXGE_PARAM(tx_dpl_get_max) static int sfxge_tx_dpl_get_max = SFXGE_TX_DPL_GET_PKT_LIMIT_DEFAULT; TUNABLE_INT(SFXGE_PARAM_TX_DPL_GET_MAX, &sfxge_tx_dpl_get_max); SYSCTL_INT(_hw_sfxge, OID_AUTO, tx_dpl_get_max, CTLFLAG_RDTUN, &sfxge_tx_dpl_get_max, 0, "Maximum number of any packets in deferred packet get-list"); #define SFXGE_PARAM_TX_DPL_GET_NON_TCP_MAX \ SFXGE_PARAM(tx_dpl_get_non_tcp_max) static int sfxge_tx_dpl_get_non_tcp_max = SFXGE_TX_DPL_GET_NON_TCP_PKT_LIMIT_DEFAULT; TUNABLE_INT(SFXGE_PARAM_TX_DPL_GET_NON_TCP_MAX, &sfxge_tx_dpl_get_non_tcp_max); SYSCTL_INT(_hw_sfxge, OID_AUTO, tx_dpl_get_non_tcp_max, CTLFLAG_RDTUN, &sfxge_tx_dpl_get_non_tcp_max, 0, "Maximum number of non-TCP packets in deferred packet get-list"); #define SFXGE_PARAM_TX_DPL_PUT_MAX SFXGE_PARAM(tx_dpl_put_max) static int sfxge_tx_dpl_put_max = SFXGE_TX_DPL_PUT_PKT_LIMIT_DEFAULT; TUNABLE_INT(SFXGE_PARAM_TX_DPL_PUT_MAX, &sfxge_tx_dpl_put_max); SYSCTL_INT(_hw_sfxge, OID_AUTO, tx_dpl_put_max, CTLFLAG_RDTUN, &sfxge_tx_dpl_put_max, 0, "Maximum number of any packets in deferred packet put-list"); +#define SFXGE_PARAM_TSO_FW_ASSISTED SFXGE_PARAM(tso_fw_assisted) +static int sfxge_tso_fw_assisted = 1; +TUNABLE_INT(SFXGE_PARAM_TSO_FW_ASSISTED, &sfxge_tso_fw_assisted); +SYSCTL_INT(_hw_sfxge, OID_AUTO, tso_fw_assisted, CTLFLAG_RDTUN, + &sfxge_tso_fw_assisted, 0, + "Use FW-assisted TSO if supported by NIC firmware"); + static const struct { const char *name; size_t offset; } sfxge_tx_stats[] = { #define SFXGE_TX_STAT(name, member) \ { #name, offsetof(struct sfxge_txq, member) } SFXGE_TX_STAT(tso_bursts, tso_bursts), SFXGE_TX_STAT(tso_packets, tso_packets), SFXGE_TX_STAT(tso_long_headers, tso_long_headers), SFXGE_TX_STAT(tso_pdrop_too_many, tso_pdrop_too_many), SFXGE_TX_STAT(tso_pdrop_no_rsrc, tso_pdrop_no_rsrc), SFXGE_TX_STAT(tx_collapses, collapses), SFXGE_TX_STAT(tx_drops, drops), SFXGE_TX_STAT(tx_get_overflow, get_overflow), SFXGE_TX_STAT(tx_get_non_tcp_overflow, get_non_tcp_overflow), SFXGE_TX_STAT(tx_put_overflow, put_overflow), SFXGE_TX_STAT(tx_netdown_drops, netdown_drops), }; /* Forward declarations. */ static void sfxge_tx_qdpl_service(struct sfxge_txq *txq); static void sfxge_tx_qlist_post(struct sfxge_txq *txq); static void sfxge_tx_qunblock(struct sfxge_txq *txq); static int sfxge_tx_queue_tso(struct sfxge_txq *txq, struct mbuf *mbuf, - const bus_dma_segment_t *dma_seg, int n_dma_seg); + const bus_dma_segment_t *dma_seg, int n_dma_seg, + int vlan_tagged); +static int +sfxge_tx_maybe_insert_tag(struct sfxge_txq *txq, struct mbuf *mbuf) +{ + uint16_t this_tag = ((mbuf->m_flags & M_VLANTAG) ? + mbuf->m_pkthdr.ether_vtag : + 0); + + if (this_tag == txq->hw_vlan_tci) + return (0); + + efx_tx_qdesc_vlantci_create(txq->common, + bswap16(this_tag), + &txq->pend_desc[0]); + txq->n_pend_desc = 1; + txq->hw_vlan_tci = this_tag; + return (1); +} + +static inline void +sfxge_next_stmp(struct sfxge_txq *txq, struct sfxge_tx_mapping **pstmp) +{ + KASSERT((*pstmp)->flags == 0, ("stmp flags are not 0")); + if (__predict_false(*pstmp == + &txq->stmp[txq->ptr_mask])) + *pstmp = &txq->stmp[0]; + else + (*pstmp)++; +} + + void sfxge_tx_qcomplete(struct sfxge_txq *txq, struct sfxge_evq *evq) { unsigned int completed; SFXGE_EVQ_LOCK_ASSERT_OWNED(evq); completed = txq->completed; while (completed != txq->pending) { struct sfxge_tx_mapping *stmp; unsigned int id; id = completed++ & txq->ptr_mask; stmp = &txq->stmp[id]; if (stmp->flags & TX_BUF_UNMAP) { bus_dmamap_unload(txq->packet_dma_tag, stmp->map); if (stmp->flags & TX_BUF_MBUF) { struct mbuf *m = stmp->u.mbuf; do m = m_free(m); while (m != NULL); } else { free(stmp->u.heap_buf, M_SFXGE); } stmp->flags = 0; } } txq->completed = completed; /* Check whether we need to unblock the queue. */ mb(); if (txq->blocked) { unsigned int level; level = txq->added - txq->completed; if (level <= SFXGE_TXQ_UNBLOCK_LEVEL(txq->entries)) sfxge_tx_qunblock(txq); } } static unsigned int sfxge_is_mbuf_non_tcp(struct mbuf *mbuf) { /* Absense of TCP checksum flags does not mean that it is non-TCP * but it should be true if user wants to achieve high throughput. */ return (!(mbuf->m_pkthdr.csum_flags & (CSUM_IP_TCP | CSUM_IP6_TCP))); } /* * Reorder the put list and append it to the get list. */ static void sfxge_tx_qdpl_swizzle(struct sfxge_txq *txq) { struct sfxge_tx_dpl *stdp; struct mbuf *mbuf, *get_next, **get_tailp; volatile uintptr_t *putp; uintptr_t put; unsigned int count; unsigned int non_tcp_count; SFXGE_TXQ_LOCK_ASSERT_OWNED(txq); stdp = &txq->dpl; /* Acquire the put list. */ putp = &stdp->std_put; put = atomic_readandclear_ptr(putp); mbuf = (void *)put; if (mbuf == NULL) return; /* Reverse the put list. */ get_tailp = &mbuf->m_nextpkt; get_next = NULL; count = 0; non_tcp_count = 0; do { struct mbuf *put_next; non_tcp_count += sfxge_is_mbuf_non_tcp(mbuf); put_next = mbuf->m_nextpkt; mbuf->m_nextpkt = get_next; get_next = mbuf; mbuf = put_next; count++; } while (mbuf != NULL); if (count > stdp->std_put_hiwat) stdp->std_put_hiwat = count; /* Append the reversed put list to the get list. */ KASSERT(*get_tailp == NULL, ("*get_tailp != NULL")); *stdp->std_getp = get_next; stdp->std_getp = get_tailp; stdp->std_get_count += count; stdp->std_get_non_tcp_count += non_tcp_count; } static void sfxge_tx_qreap(struct sfxge_txq *txq) { SFXGE_TXQ_LOCK_ASSERT_OWNED(txq); txq->reaped = txq->completed; } static void sfxge_tx_qlist_post(struct sfxge_txq *txq) { unsigned int old_added; + unsigned int block_level; unsigned int level; int rc; SFXGE_TXQ_LOCK_ASSERT_OWNED(txq); KASSERT(txq->n_pend_desc != 0, ("txq->n_pend_desc == 0")); - KASSERT(txq->n_pend_desc <= SFXGE_TSO_MAX_DESC, + KASSERT(txq->n_pend_desc <= txq->max_pkt_desc, ("txq->n_pend_desc too large")); KASSERT(!txq->blocked, ("txq->blocked")); old_added = txq->added; /* Post the fragment list. */ - rc = efx_tx_qpost(txq->common, txq->pend_desc, txq->n_pend_desc, + rc = efx_tx_qdesc_post(txq->common, txq->pend_desc, txq->n_pend_desc, txq->reaped, &txq->added); - KASSERT(rc == 0, ("efx_tx_qpost() failed")); + KASSERT(rc == 0, ("efx_tx_qdesc_post() failed")); - /* If efx_tx_qpost() had to refragment, our information about + /* If efx_tx_qdesc_post() had to refragment, our information about * buffers to free may be associated with the wrong * descriptors. */ KASSERT(txq->added - old_added == txq->n_pend_desc, - ("efx_tx_qpost() refragmented descriptors")); + ("efx_tx_qdesc_post() refragmented descriptors")); level = txq->added - txq->reaped; KASSERT(level <= txq->entries, ("overfilled TX queue")); /* Clear the fragment list. */ txq->n_pend_desc = 0; + /* + * Set the block level to ensure there is space to generate a + * large number of descriptors for TSO. + */ + block_level = EFX_TXQ_LIMIT(txq->entries) - txq->max_pkt_desc; + /* Have we reached the block level? */ - if (level < SFXGE_TXQ_BLOCK_LEVEL(txq->entries)) + if (level < block_level) return; /* Reap, and check again */ sfxge_tx_qreap(txq); level = txq->added - txq->reaped; - if (level < SFXGE_TXQ_BLOCK_LEVEL(txq->entries)) + if (level < block_level) return; txq->blocked = 1; /* * Avoid a race with completion interrupt handling that could leave * the queue blocked. */ mb(); sfxge_tx_qreap(txq); level = txq->added - txq->reaped; - if (level < SFXGE_TXQ_BLOCK_LEVEL(txq->entries)) { + if (level < block_level) { mb(); txq->blocked = 0; } } static int sfxge_tx_queue_mbuf(struct sfxge_txq *txq, struct mbuf *mbuf) { bus_dmamap_t *used_map; bus_dmamap_t map; bus_dma_segment_t dma_seg[SFXGE_TX_MAPPING_MAX_SEG]; unsigned int id; struct sfxge_tx_mapping *stmp; - efx_buffer_t *desc; + efx_desc_t *desc; int n_dma_seg; int rc; int i; + int eop; + int vlan_tagged; KASSERT(!txq->blocked, ("txq->blocked")); if (mbuf->m_pkthdr.csum_flags & CSUM_TSO) prefetch_read_many(mbuf->m_data); if (__predict_false(txq->init_state != SFXGE_TXQ_STARTED)) { rc = EINTR; goto reject; } /* Load the packet for DMA. */ id = txq->added & txq->ptr_mask; stmp = &txq->stmp[id]; rc = bus_dmamap_load_mbuf_sg(txq->packet_dma_tag, stmp->map, mbuf, dma_seg, &n_dma_seg, 0); if (rc == EFBIG) { /* Try again. */ struct mbuf *new_mbuf = m_collapse(mbuf, M_NOWAIT, SFXGE_TX_MAPPING_MAX_SEG); if (new_mbuf == NULL) goto reject; ++txq->collapses; mbuf = new_mbuf; rc = bus_dmamap_load_mbuf_sg(txq->packet_dma_tag, stmp->map, mbuf, dma_seg, &n_dma_seg, 0); } if (rc != 0) goto reject; /* Make the packet visible to the hardware. */ bus_dmamap_sync(txq->packet_dma_tag, stmp->map, BUS_DMASYNC_PREWRITE); used_map = &stmp->map; + vlan_tagged = sfxge_tx_maybe_insert_tag(txq, mbuf); + if (vlan_tagged) { + sfxge_next_stmp(txq, &stmp); + } if (mbuf->m_pkthdr.csum_flags & CSUM_TSO) { - rc = sfxge_tx_queue_tso(txq, mbuf, dma_seg, n_dma_seg); + rc = sfxge_tx_queue_tso(txq, mbuf, dma_seg, n_dma_seg, vlan_tagged); if (rc < 0) goto reject_mapped; - stmp = &txq->stmp[rc]; + stmp = &txq->stmp[(rc - 1) & txq->ptr_mask]; } else { /* Add the mapping to the fragment list, and set flags * for the buffer. */ + i = 0; for (;;) { - desc = &txq->pend_desc[i]; - desc->eb_addr = dma_seg[i].ds_addr; - desc->eb_size = dma_seg[i].ds_len; - if (i == n_dma_seg - 1) { - desc->eb_eop = 1; + desc = &txq->pend_desc[i + vlan_tagged]; + eop = (i == n_dma_seg - 1); + efx_tx_qdesc_dma_create(txq->common, + dma_seg[i].ds_addr, + dma_seg[i].ds_len, + eop, + desc); + if (eop) break; - } - desc->eb_eop = 0; i++; - - stmp->flags = 0; - if (__predict_false(stmp == - &txq->stmp[txq->ptr_mask])) - stmp = &txq->stmp[0]; - else - stmp++; + sfxge_next_stmp(txq, &stmp); } - txq->n_pend_desc = n_dma_seg; + txq->n_pend_desc = n_dma_seg + vlan_tagged; } /* * If the mapping required more than one descriptor * then we need to associate the DMA map with the last * descriptor, not the first. */ if (used_map != &stmp->map) { map = stmp->map; stmp->map = *used_map; *used_map = map; } stmp->u.mbuf = mbuf; stmp->flags = TX_BUF_UNMAP | TX_BUF_MBUF; /* Post the fragment list. */ sfxge_tx_qlist_post(txq); return (0); reject_mapped: bus_dmamap_unload(txq->packet_dma_tag, *used_map); reject: /* Drop the packet on the floor. */ m_freem(mbuf); ++txq->drops; return (rc); } /* * Drain the deferred packet list into the transmit queue. */ static void sfxge_tx_qdpl_drain(struct sfxge_txq *txq) { struct sfxge_softc *sc; struct sfxge_tx_dpl *stdp; struct mbuf *mbuf, *next; unsigned int count; unsigned int non_tcp_count; unsigned int pushed; int rc; SFXGE_TXQ_LOCK_ASSERT_OWNED(txq); sc = txq->sc; stdp = &txq->dpl; pushed = txq->added; if (__predict_true(txq->init_state == SFXGE_TXQ_STARTED)) { prefetch_read_many(sc->enp); prefetch_read_many(txq->common); } mbuf = stdp->std_get; count = stdp->std_get_count; non_tcp_count = stdp->std_get_non_tcp_count; if (count > stdp->std_get_hiwat) stdp->std_get_hiwat = count; while (count != 0) { KASSERT(mbuf != NULL, ("mbuf == NULL")); next = mbuf->m_nextpkt; mbuf->m_nextpkt = NULL; ETHER_BPF_MTAP(sc->ifnet, mbuf); /* packet capture */ if (next != NULL) prefetch_read_many(next); rc = sfxge_tx_queue_mbuf(txq, mbuf); --count; non_tcp_count -= sfxge_is_mbuf_non_tcp(mbuf); mbuf = next; if (rc != 0) continue; if (txq->blocked) break; /* Push the fragments to the hardware in batches. */ if (txq->added - pushed >= SFXGE_TX_BATCH) { - efx_tx_qpush(txq->common, txq->added); + efx_tx_qpush(txq->common, txq->added, pushed); pushed = txq->added; } } if (count == 0) { KASSERT(mbuf == NULL, ("mbuf != NULL")); KASSERT(non_tcp_count == 0, ("inconsistent TCP/non-TCP detection")); stdp->std_get = NULL; stdp->std_get_count = 0; stdp->std_get_non_tcp_count = 0; stdp->std_getp = &stdp->std_get; } else { stdp->std_get = mbuf; stdp->std_get_count = count; stdp->std_get_non_tcp_count = non_tcp_count; } if (txq->added != pushed) - efx_tx_qpush(txq->common, txq->added); + efx_tx_qpush(txq->common, txq->added, pushed); KASSERT(txq->blocked || stdp->std_get_count == 0, ("queue unblocked but count is non-zero")); } -#define SFXGE_TX_QDPL_PENDING(_txq) \ - ((_txq)->dpl.std_put != 0) +#define SFXGE_TX_QDPL_PENDING(_txq) ((_txq)->dpl.std_put != 0) /* * Service the deferred packet list. * * NOTE: drops the txq mutex! */ static void sfxge_tx_qdpl_service(struct sfxge_txq *txq) { SFXGE_TXQ_LOCK_ASSERT_OWNED(txq); do { if (SFXGE_TX_QDPL_PENDING(txq)) sfxge_tx_qdpl_swizzle(txq); if (!txq->blocked) sfxge_tx_qdpl_drain(txq); SFXGE_TXQ_UNLOCK(txq); } while (SFXGE_TX_QDPL_PENDING(txq) && SFXGE_TXQ_TRYLOCK(txq)); } /* * Put a packet on the deferred packet get-list. */ static int sfxge_tx_qdpl_put_locked(struct sfxge_txq *txq, struct mbuf *mbuf) { struct sfxge_tx_dpl *stdp; stdp = &txq->dpl; KASSERT(mbuf->m_nextpkt == NULL, ("mbuf->m_nextpkt != NULL")); SFXGE_TXQ_LOCK_ASSERT_OWNED(txq); if (stdp->std_get_count >= stdp->std_get_max) { txq->get_overflow++; return (ENOBUFS); } if (sfxge_is_mbuf_non_tcp(mbuf)) { if (stdp->std_get_non_tcp_count >= stdp->std_get_non_tcp_max) { txq->get_non_tcp_overflow++; return (ENOBUFS); } stdp->std_get_non_tcp_count++; } *(stdp->std_getp) = mbuf; stdp->std_getp = &mbuf->m_nextpkt; stdp->std_get_count++; return (0); } /* * Put a packet on the deferred packet put-list. * * We overload the csum_data field in the mbuf to keep track of this length * because there is no cheap alternative to avoid races. */ static int sfxge_tx_qdpl_put_unlocked(struct sfxge_txq *txq, struct mbuf *mbuf) { struct sfxge_tx_dpl *stdp; volatile uintptr_t *putp; uintptr_t old; uintptr_t new; unsigned old_len; KASSERT(mbuf->m_nextpkt == NULL, ("mbuf->m_nextpkt != NULL")); SFXGE_TXQ_LOCK_ASSERT_NOTOWNED(txq); stdp = &txq->dpl; putp = &stdp->std_put; new = (uintptr_t)mbuf; do { old = *putp; if (old != 0) { struct mbuf *mp = (struct mbuf *)old; old_len = mp->m_pkthdr.csum_data; } else old_len = 0; if (old_len >= stdp->std_put_max) { atomic_add_long(&txq->put_overflow, 1); return (ENOBUFS); } mbuf->m_pkthdr.csum_data = old_len + 1; mbuf->m_nextpkt = (void *)old; } while (atomic_cmpset_ptr(putp, old, new) == 0); return (0); } /* * Called from if_transmit - will try to grab the txq lock and enqueue to the * put list if it succeeds, otherwise try to push onto the defer list if space. */ -int +static int sfxge_tx_packet_add(struct sfxge_txq *txq, struct mbuf *m) { int rc; if (!SFXGE_LINK_UP(txq->sc)) { atomic_add_long(&txq->netdown_drops, 1); return (ENETDOWN); } /* * Try to grab the txq lock. If we are able to get the lock, * the packet will be appended to the "get list" of the deferred * packet list. Otherwise, it will be pushed on the "put list". */ if (SFXGE_TXQ_TRYLOCK(txq)) { /* First swizzle put-list to get-list to keep order */ sfxge_tx_qdpl_swizzle(txq); rc = sfxge_tx_qdpl_put_locked(txq, m); /* Try to service the list. */ sfxge_tx_qdpl_service(txq); /* Lock has been dropped. */ } else { rc = sfxge_tx_qdpl_put_unlocked(txq, m); /* * Try to grab the lock again. * * If we are able to get the lock, we need to process * the deferred packet list. If we are not able to get * the lock, another thread is processing the list. */ if ((rc == 0) && SFXGE_TXQ_TRYLOCK(txq)) { sfxge_tx_qdpl_service(txq); /* Lock has been dropped. */ } } SFXGE_TXQ_LOCK_ASSERT_NOTOWNED(txq); return (rc); } static void sfxge_tx_qdpl_flush(struct sfxge_txq *txq) { struct sfxge_tx_dpl *stdp = &txq->dpl; struct mbuf *mbuf, *next; SFXGE_TXQ_LOCK(txq); sfxge_tx_qdpl_swizzle(txq); for (mbuf = stdp->std_get; mbuf != NULL; mbuf = next) { next = mbuf->m_nextpkt; m_freem(mbuf); } stdp->std_get = NULL; stdp->std_get_count = 0; stdp->std_get_non_tcp_count = 0; stdp->std_getp = &stdp->std_get; SFXGE_TXQ_UNLOCK(txq); } void sfxge_if_qflush(struct ifnet *ifp) { struct sfxge_softc *sc; unsigned int i; sc = ifp->if_softc; for (i = 0; i < sc->txq_count; i++) sfxge_tx_qdpl_flush(sc->txq[i]); } /* * TX start -- called by the stack. */ int sfxge_if_transmit(struct ifnet *ifp, struct mbuf *m) { struct sfxge_softc *sc; struct sfxge_txq *txq; int rc; sc = (struct sfxge_softc *)ifp->if_softc; /* * Transmit may be called when interface is up from the kernel * point of view, but not yet up (in progress) from the driver * point of view. I.e. link aggregation bring up. * Transmit may be called when interface is up from the driver * point of view, but already down from the kernel point of * view. I.e. Rx when interface shutdown is in progress. */ KASSERT((ifp->if_flags & IFF_UP) || (sc->if_flags & IFF_UP), ("interface not up")); /* Pick the desired transmit queue. */ if (m->m_pkthdr.csum_flags & (CSUM_DELAY_DATA | CSUM_TCP_IPV6 | CSUM_UDP_IPV6 | CSUM_TSO)) { int index = 0; /* check if flowid is set */ if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) { uint32_t hash = m->m_pkthdr.flowid; index = sc->rx_indir_table[hash % SFXGE_RX_SCALE_MAX]; } txq = sc->txq[SFXGE_TXQ_IP_TCP_UDP_CKSUM + index]; } else if (m->m_pkthdr.csum_flags & CSUM_DELAY_IP) { txq = sc->txq[SFXGE_TXQ_IP_CKSUM]; } else { txq = sc->txq[SFXGE_TXQ_NON_CKSUM]; } rc = sfxge_tx_packet_add(txq, m); if (rc != 0) m_freem(m); return (rc); } /* * Software "TSO". Not quite as good as doing it in hardware, but * still faster than segmenting in the stack. */ struct sfxge_tso_state { /* Output position */ unsigned out_len; /* Remaining length in current segment */ unsigned seqnum; /* Current sequence number */ unsigned packet_space; /* Remaining space in current packet */ /* Input position */ uint64_t dma_addr; /* DMA address of current position */ unsigned in_len; /* Remaining length in current mbuf */ const struct mbuf *mbuf; /* Input mbuf (head of chain) */ u_short protocol; /* Network protocol (after VLAN decap) */ ssize_t nh_off; /* Offset of network header */ ssize_t tcph_off; /* Offset of TCP header */ unsigned header_len; /* Number of bytes of header */ unsigned seg_size; /* TCP segment size */ + int fw_assisted; /* Use FW-assisted TSO */ + u_short packet_id; /* IPv4 packet ID from the original packet */ + efx_desc_t header_desc; /* Precomputed header descriptor for + * FW-assisted TSO */ }; static const struct ip *tso_iph(const struct sfxge_tso_state *tso) { KASSERT(tso->protocol == htons(ETHERTYPE_IP), ("tso_iph() in non-IPv4 state")); return (const struct ip *)(tso->mbuf->m_data + tso->nh_off); } static __unused const struct ip6_hdr *tso_ip6h(const struct sfxge_tso_state *tso) { KASSERT(tso->protocol == htons(ETHERTYPE_IPV6), ("tso_ip6h() in non-IPv6 state")); return (const struct ip6_hdr *)(tso->mbuf->m_data + tso->nh_off); } static const struct tcphdr *tso_tcph(const struct sfxge_tso_state *tso) { return (const struct tcphdr *)(tso->mbuf->m_data + tso->tcph_off); } /* Size of preallocated TSO header buffers. Larger blocks must be * allocated from the heap. */ #define TSOH_STD_SIZE 128 /* At most half the descriptors in the queue at any time will refer to * a TSO header buffer, since they must always be followed by a * payload descriptor referring to an mbuf. */ #define TSOH_COUNT(_txq_entries) ((_txq_entries) / 2u) #define TSOH_PER_PAGE (PAGE_SIZE / TSOH_STD_SIZE) #define TSOH_PAGE_COUNT(_txq_entries) \ ((TSOH_COUNT(_txq_entries) + TSOH_PER_PAGE - 1) / TSOH_PER_PAGE) static int tso_init(struct sfxge_txq *txq) { struct sfxge_softc *sc = txq->sc; unsigned int tsoh_page_count = TSOH_PAGE_COUNT(sc->txq_entries); int i, rc; /* Allocate TSO header buffers */ txq->tsoh_buffer = malloc(tsoh_page_count * sizeof(txq->tsoh_buffer[0]), M_SFXGE, M_WAITOK); for (i = 0; i < tsoh_page_count; i++) { rc = sfxge_dma_alloc(sc, PAGE_SIZE, &txq->tsoh_buffer[i]); if (rc != 0) goto fail; } return (0); fail: while (i-- > 0) sfxge_dma_free(&txq->tsoh_buffer[i]); free(txq->tsoh_buffer, M_SFXGE); txq->tsoh_buffer = NULL; return (rc); } static void tso_fini(struct sfxge_txq *txq) { int i; if (txq->tsoh_buffer != NULL) { for (i = 0; i < TSOH_PAGE_COUNT(txq->sc->txq_entries); i++) sfxge_dma_free(&txq->tsoh_buffer[i]); free(txq->tsoh_buffer, M_SFXGE); } } -static void tso_start(struct sfxge_tso_state *tso, struct mbuf *mbuf) +static void tso_start(struct sfxge_txq *txq, struct sfxge_tso_state *tso, + const bus_dma_segment_t *hdr_dma_seg, + struct mbuf *mbuf) { struct ether_header *eh = mtod(mbuf, struct ether_header *); + const efx_nic_cfg_t *encp = efx_nic_cfg_get(txq->sc->enp); const struct tcphdr *th; struct tcphdr th_copy; + tso->fw_assisted = txq->sc->tso_fw_assisted; tso->mbuf = mbuf; /* Find network protocol and header */ tso->protocol = eh->ether_type; if (tso->protocol == htons(ETHERTYPE_VLAN)) { struct ether_vlan_header *veh = mtod(mbuf, struct ether_vlan_header *); tso->protocol = veh->evl_proto; tso->nh_off = sizeof(*veh); } else { tso->nh_off = sizeof(*eh); } /* Find TCP header */ if (tso->protocol == htons(ETHERTYPE_IP)) { KASSERT(tso_iph(tso)->ip_p == IPPROTO_TCP, ("TSO required on non-TCP packet")); tso->tcph_off = tso->nh_off + 4 * tso_iph(tso)->ip_hl; + tso->packet_id = tso_iph(tso)->ip_id; } else { KASSERT(tso->protocol == htons(ETHERTYPE_IPV6), ("TSO required on non-IP packet")); KASSERT(tso_ip6h(tso)->ip6_nxt == IPPROTO_TCP, ("TSO required on non-TCP packet")); tso->tcph_off = tso->nh_off + sizeof(struct ip6_hdr); + tso->packet_id = 0; } + if (tso->fw_assisted && + __predict_false(tso->tcph_off > + encp->enc_tx_tso_tcp_header_offset_limit)) { + tso->fw_assisted = 0; + } KASSERT(mbuf->m_len >= tso->tcph_off, ("network header is fragmented in mbuf")); /* We need TCP header including flags (window is the next) */ if (mbuf->m_len < tso->tcph_off + offsetof(struct tcphdr, th_win)) { m_copydata(tso->mbuf, tso->tcph_off, sizeof(th_copy), (caddr_t)&th_copy); th = &th_copy; } else { th = tso_tcph(tso); } tso->header_len = tso->tcph_off + 4 * th->th_off; tso->seg_size = mbuf->m_pkthdr.tso_segsz; tso->seqnum = ntohl(th->th_seq); /* These flags must not be duplicated */ /* * RST should not be duplicated as well, but FreeBSD kernel * generates TSO packets with RST flag. So, do not assert * its absence. */ KASSERT(!(th->th_flags & (TH_URG | TH_SYN)), ("incompatible TCP flag 0x%x on TSO packet", th->th_flags & (TH_URG | TH_SYN))); tso->out_len = mbuf->m_pkthdr.len - tso->header_len; + + if (tso->fw_assisted) { + if (hdr_dma_seg->ds_len >= tso->header_len) + efx_tx_qdesc_dma_create(txq->common, + hdr_dma_seg->ds_addr, + tso->header_len, + B_FALSE, + &tso->header_desc); + else + tso->fw_assisted = 0; + } } /* * tso_fill_packet_with_fragment - form descriptors for the current fragment * * Form descriptors for the current fragment, until we reach the end * of fragment or end-of-packet. Return 0 on success, 1 if not enough * space. */ static void tso_fill_packet_with_fragment(struct sfxge_txq *txq, struct sfxge_tso_state *tso) { - efx_buffer_t *desc; + efx_desc_t *desc; int n; if (tso->in_len == 0 || tso->packet_space == 0) return; KASSERT(tso->in_len > 0, ("TSO input length went negative")); KASSERT(tso->packet_space > 0, ("TSO packet space went negative")); n = min(tso->in_len, tso->packet_space); tso->packet_space -= n; tso->out_len -= n; tso->in_len -= n; desc = &txq->pend_desc[txq->n_pend_desc++]; - desc->eb_addr = tso->dma_addr; - desc->eb_size = n; - desc->eb_eop = tso->out_len == 0 || tso->packet_space == 0; + efx_tx_qdesc_dma_create(txq->common, + tso->dma_addr, + n, + tso->out_len == 0 || tso->packet_space == 0, + desc); tso->dma_addr += n; } /* Callback from bus_dmamap_load() for long TSO headers. */ static void tso_map_long_header(void *dma_addr_ret, bus_dma_segment_t *segs, int nseg, int error) { *(uint64_t *)dma_addr_ret = ((__predict_true(error == 0) && __predict_true(nseg == 1)) ? segs->ds_addr : 0); } /* * tso_start_new_packet - generate a new header and prepare for the new packet * * Generate a new header and prepare for the new packet. Return 0 on * success, or an error code if failed to alloc header. */ static int tso_start_new_packet(struct sfxge_txq *txq, struct sfxge_tso_state *tso, - unsigned int id) + unsigned int *idp) { - struct sfxge_tx_mapping *stmp = &txq->stmp[id]; + unsigned int id = *idp; struct tcphdr *tsoh_th; unsigned ip_length; caddr_t header; uint64_t dma_addr; bus_dmamap_t map; - efx_buffer_t *desc; + efx_desc_t *desc; int rc; - /* Allocate a DMA-mapped header buffer. */ - if (__predict_true(tso->header_len <= TSOH_STD_SIZE)) { - unsigned int page_index = (id / 2) / TSOH_PER_PAGE; - unsigned int buf_index = (id / 2) % TSOH_PER_PAGE; + if (tso->fw_assisted) { + uint8_t tcp_flags = tso_tcph(tso)->th_flags; - header = (txq->tsoh_buffer[page_index].esm_base + - buf_index * TSOH_STD_SIZE); - dma_addr = (txq->tsoh_buffer[page_index].esm_addr + - buf_index * TSOH_STD_SIZE); - map = txq->tsoh_buffer[page_index].esm_map; + if (tso->out_len > tso->seg_size) + tcp_flags &= ~(TH_FIN | TH_PUSH); - stmp->flags = 0; + /* TSO option descriptor */ + desc = &txq->pend_desc[txq->n_pend_desc++]; + efx_tx_qdesc_tso_create(txq->common, + tso->packet_id, + tso->seqnum, + tcp_flags, + desc++); + KASSERT(txq->stmp[id].flags == 0, ("stmp flags are not 0")); + id = (id + 1) & txq->ptr_mask; + + /* Header DMA descriptor */ + *desc = tso->header_desc; + txq->n_pend_desc++; + KASSERT(txq->stmp[id].flags == 0, ("stmp flags are not 0")); + id = (id + 1) & txq->ptr_mask; + + tso->seqnum += tso->seg_size; } else { - /* We cannot use bus_dmamem_alloc() as that may sleep */ - header = malloc(tso->header_len, M_SFXGE, M_NOWAIT); - if (__predict_false(!header)) - return (ENOMEM); - rc = bus_dmamap_load(txq->packet_dma_tag, stmp->map, - header, tso->header_len, - tso_map_long_header, &dma_addr, - BUS_DMA_NOWAIT); - if (__predict_false(dma_addr == 0)) { - if (rc == 0) { - /* Succeeded but got >1 segment */ - bus_dmamap_unload(txq->packet_dma_tag, - stmp->map); - rc = EINVAL; + /* Allocate a DMA-mapped header buffer. */ + if (__predict_true(tso->header_len <= TSOH_STD_SIZE)) { + unsigned int page_index = (id / 2) / TSOH_PER_PAGE; + unsigned int buf_index = (id / 2) % TSOH_PER_PAGE; + + header = (txq->tsoh_buffer[page_index].esm_base + + buf_index * TSOH_STD_SIZE); + dma_addr = (txq->tsoh_buffer[page_index].esm_addr + + buf_index * TSOH_STD_SIZE); + map = txq->tsoh_buffer[page_index].esm_map; + + KASSERT(txq->stmp[id].flags == 0, + ("stmp flags are not 0")); + } else { + struct sfxge_tx_mapping *stmp = &txq->stmp[id]; + + /* We cannot use bus_dmamem_alloc() as that may sleep */ + header = malloc(tso->header_len, M_SFXGE, M_NOWAIT); + if (__predict_false(!header)) + return (ENOMEM); + rc = bus_dmamap_load(txq->packet_dma_tag, stmp->map, + header, tso->header_len, + tso_map_long_header, &dma_addr, + BUS_DMA_NOWAIT); + if (__predict_false(dma_addr == 0)) { + if (rc == 0) { + /* Succeeded but got >1 segment */ + bus_dmamap_unload(txq->packet_dma_tag, + stmp->map); + rc = EINVAL; + } + free(header, M_SFXGE); + return (rc); } - free(header, M_SFXGE); - return (rc); + map = stmp->map; + + txq->tso_long_headers++; + stmp->u.heap_buf = header; + stmp->flags = TX_BUF_UNMAP; } - map = stmp->map; - txq->tso_long_headers++; - stmp->u.heap_buf = header; - stmp->flags = TX_BUF_UNMAP; - } + tsoh_th = (struct tcphdr *)(header + tso->tcph_off); - tsoh_th = (struct tcphdr *)(header + tso->tcph_off); + /* Copy and update the headers. */ + m_copydata(tso->mbuf, 0, tso->header_len, header); - /* Copy and update the headers. */ - m_copydata(tso->mbuf, 0, tso->header_len, header); + tsoh_th->th_seq = htonl(tso->seqnum); + tso->seqnum += tso->seg_size; + if (tso->out_len > tso->seg_size) { + /* This packet will not finish the TSO burst. */ + ip_length = tso->header_len - tso->nh_off + tso->seg_size; + tsoh_th->th_flags &= ~(TH_FIN | TH_PUSH); + } else { + /* This packet will be the last in the TSO burst. */ + ip_length = tso->header_len - tso->nh_off + tso->out_len; + } - tsoh_th->th_seq = htonl(tso->seqnum); - tso->seqnum += tso->seg_size; - if (tso->out_len > tso->seg_size) { - /* This packet will not finish the TSO burst. */ - ip_length = tso->header_len - tso->nh_off + tso->seg_size; - tsoh_th->th_flags &= ~(TH_FIN | TH_PUSH); - } else { - /* This packet will be the last in the TSO burst. */ - ip_length = tso->header_len - tso->nh_off + tso->out_len; - } + if (tso->protocol == htons(ETHERTYPE_IP)) { + struct ip *tsoh_iph = (struct ip *)(header + tso->nh_off); + tsoh_iph->ip_len = htons(ip_length); + /* XXX We should increment ip_id, but FreeBSD doesn't + * currently allocate extra IDs for multiple segments. + */ + } else { + struct ip6_hdr *tsoh_iph = + (struct ip6_hdr *)(header + tso->nh_off); + tsoh_iph->ip6_plen = htons(ip_length - sizeof(*tsoh_iph)); + } - if (tso->protocol == htons(ETHERTYPE_IP)) { - struct ip *tsoh_iph = (struct ip *)(header + tso->nh_off); - tsoh_iph->ip_len = htons(ip_length); - /* XXX We should increment ip_id, but FreeBSD doesn't - * currently allocate extra IDs for multiple segments. - */ - } else { - struct ip6_hdr *tsoh_iph = - (struct ip6_hdr *)(header + tso->nh_off); - tsoh_iph->ip6_plen = htons(ip_length - sizeof(*tsoh_iph)); - } + /* Make the header visible to the hardware. */ + bus_dmamap_sync(txq->packet_dma_tag, map, BUS_DMASYNC_PREWRITE); - /* Make the header visible to the hardware. */ - bus_dmamap_sync(txq->packet_dma_tag, map, BUS_DMASYNC_PREWRITE); - + /* Form a descriptor for this header. */ + desc = &txq->pend_desc[txq->n_pend_desc++]; + efx_tx_qdesc_dma_create(txq->common, + dma_addr, + tso->header_len, + 0, + desc); + id = (id + 1) & txq->ptr_mask; + } tso->packet_space = tso->seg_size; txq->tso_packets++; + *idp = id; - /* Form a descriptor for this header. */ - desc = &txq->pend_desc[txq->n_pend_desc++]; - desc->eb_addr = dma_addr; - desc->eb_size = tso->header_len; - desc->eb_eop = 0; - return (0); } static int sfxge_tx_queue_tso(struct sfxge_txq *txq, struct mbuf *mbuf, - const bus_dma_segment_t *dma_seg, int n_dma_seg) + const bus_dma_segment_t *dma_seg, int n_dma_seg, + int vlan_tagged) { struct sfxge_tso_state tso; - unsigned int id, next_id; + unsigned int id; unsigned skipped = 0; - tso_start(&tso, mbuf); + tso_start(txq, &tso, dma_seg, mbuf); while (dma_seg->ds_len + skipped <= tso.header_len) { skipped += dma_seg->ds_len; --n_dma_seg; KASSERT(n_dma_seg, ("no payload found in TSO packet")); ++dma_seg; } tso.in_len = dma_seg->ds_len - (tso.header_len - skipped); tso.dma_addr = dma_seg->ds_addr + (tso.header_len - skipped); - id = txq->added & txq->ptr_mask; - if (__predict_false(tso_start_new_packet(txq, &tso, id))) + id = (txq->added + vlan_tagged) & txq->ptr_mask; + if (__predict_false(tso_start_new_packet(txq, &tso, &id))) return (-1); while (1) { - id = (id + 1) & txq->ptr_mask; tso_fill_packet_with_fragment(txq, &tso); + /* Exactly one DMA descriptor is added */ + KASSERT(txq->stmp[id].flags == 0, ("stmp flags are not 0")); + id = (id + 1) & txq->ptr_mask; /* Move onto the next fragment? */ if (tso.in_len == 0) { --n_dma_seg; if (n_dma_seg == 0) break; ++dma_seg; tso.in_len = dma_seg->ds_len; tso.dma_addr = dma_seg->ds_addr; } /* End of packet? */ if (tso.packet_space == 0) { /* If the queue is now full due to tiny MSS, * or we can't create another header, discard * the remainder of the input mbuf but do not * roll back the work we have done. */ - if (txq->n_pend_desc + 1 /* header */ + n_dma_seg > - SFXGE_TSO_MAX_DESC) { + if (txq->n_pend_desc + tso.fw_assisted + + 1 /* header */ + n_dma_seg > + txq->max_pkt_desc) { txq->tso_pdrop_too_many++; break; } - next_id = (id + 1) & txq->ptr_mask; if (__predict_false(tso_start_new_packet(txq, &tso, - next_id))) { + &id))) { txq->tso_pdrop_no_rsrc++; break; } - id = next_id; } } txq->tso_bursts++; return (id); } static void sfxge_tx_qunblock(struct sfxge_txq *txq) { struct sfxge_softc *sc; struct sfxge_evq *evq; sc = txq->sc; evq = sc->evq[txq->evq_index]; SFXGE_EVQ_LOCK_ASSERT_OWNED(evq); if (__predict_false(txq->init_state != SFXGE_TXQ_STARTED)) return; SFXGE_TXQ_LOCK(txq); if (txq->blocked) { unsigned int level; level = txq->added - txq->completed; if (level <= SFXGE_TXQ_UNBLOCK_LEVEL(txq->entries)) { /* reaped must be in sync with blocked */ sfxge_tx_qreap(txq); txq->blocked = 0; } } sfxge_tx_qdpl_service(txq); /* note: lock has been dropped */ } void sfxge_tx_qflush_done(struct sfxge_txq *txq) { txq->flush_state = SFXGE_FLUSH_DONE; } static void sfxge_tx_qstop(struct sfxge_softc *sc, unsigned int index) { struct sfxge_txq *txq; struct sfxge_evq *evq; unsigned int count; + SFXGE_ADAPTER_LOCK_ASSERT_OWNED(sc); + txq = sc->txq[index]; evq = sc->evq[txq->evq_index]; + SFXGE_EVQ_LOCK(evq); SFXGE_TXQ_LOCK(txq); KASSERT(txq->init_state == SFXGE_TXQ_STARTED, ("txq->init_state != SFXGE_TXQ_STARTED")); txq->init_state = SFXGE_TXQ_INITIALIZED; - txq->flush_state = SFXGE_FLUSH_PENDING; - /* Flush the transmit queue. */ - efx_tx_qflush(txq->common); + if (txq->flush_state != SFXGE_FLUSH_DONE) { + txq->flush_state = SFXGE_FLUSH_PENDING; - SFXGE_TXQ_UNLOCK(txq); + SFXGE_EVQ_UNLOCK(evq); + SFXGE_TXQ_UNLOCK(txq); - count = 0; - do { - /* Spin for 100ms. */ - DELAY(100000); + /* Flush the transmit queue. */ + if (efx_tx_qflush(txq->common) != 0) { + log(LOG_ERR, "%s: Flushing Tx queue %u failed\n", + device_get_nameunit(sc->dev), index); + txq->flush_state = SFXGE_FLUSH_DONE; + } else { + count = 0; + do { + /* Spin for 100ms. */ + DELAY(100000); + if (txq->flush_state != SFXGE_FLUSH_PENDING) + break; + } while (++count < 20); + } + SFXGE_EVQ_LOCK(evq); + SFXGE_TXQ_LOCK(txq); - if (txq->flush_state != SFXGE_FLUSH_PENDING) - break; - } while (++count < 20); + KASSERT(txq->flush_state != SFXGE_FLUSH_FAILED, + ("txq->flush_state == SFXGE_FLUSH_FAILED")); - SFXGE_EVQ_LOCK(evq); - SFXGE_TXQ_LOCK(txq); + if (txq->flush_state != SFXGE_FLUSH_DONE) { + /* Flush timeout */ + log(LOG_ERR, "%s: Cannot flush Tx queue %u\n", + device_get_nameunit(sc->dev), index); + txq->flush_state = SFXGE_FLUSH_DONE; + } + } - KASSERT(txq->flush_state != SFXGE_FLUSH_FAILED, - ("txq->flush_state == SFXGE_FLUSH_FAILED")); - - txq->flush_state = SFXGE_FLUSH_DONE; - txq->blocked = 0; txq->pending = txq->added; sfxge_tx_qcomplete(txq, evq); KASSERT(txq->completed == txq->added, ("txq->completed != txq->added")); sfxge_tx_qreap(txq); KASSERT(txq->reaped == txq->completed, ("txq->reaped != txq->completed")); txq->added = 0; txq->pending = 0; txq->completed = 0; txq->reaped = 0; /* Destroy the common code transmit queue. */ efx_tx_qdestroy(txq->common); txq->common = NULL; efx_sram_buf_tbl_clear(sc->enp, txq->buf_base_id, EFX_TXQ_NBUFS(sc->txq_entries)); SFXGE_EVQ_UNLOCK(evq); SFXGE_TXQ_UNLOCK(txq); } static int sfxge_tx_qstart(struct sfxge_softc *sc, unsigned int index) { struct sfxge_txq *txq; efsys_mem_t *esmp; uint16_t flags; struct sfxge_evq *evq; + unsigned int desc_index; int rc; + SFXGE_ADAPTER_LOCK_ASSERT_OWNED(sc); + txq = sc->txq[index]; esmp = &txq->mem; evq = sc->evq[txq->evq_index]; KASSERT(txq->init_state == SFXGE_TXQ_INITIALIZED, ("txq->init_state != SFXGE_TXQ_INITIALIZED")); KASSERT(evq->init_state == SFXGE_EVQ_STARTED, ("evq->init_state != SFXGE_EVQ_STARTED")); /* Program the buffer table. */ if ((rc = efx_sram_buf_tbl_set(sc->enp, txq->buf_base_id, esmp, EFX_TXQ_NBUFS(sc->txq_entries))) != 0) return (rc); /* Determine the kind of queue we are creating. */ switch (txq->type) { case SFXGE_TXQ_NON_CKSUM: flags = 0; break; case SFXGE_TXQ_IP_CKSUM: flags = EFX_CKSUM_IPV4; break; case SFXGE_TXQ_IP_TCP_UDP_CKSUM: flags = EFX_CKSUM_IPV4 | EFX_CKSUM_TCPUDP; break; default: KASSERT(0, ("Impossible TX queue")); flags = 0; break; } /* Create the common code transmit queue. */ if ((rc = efx_tx_qcreate(sc->enp, index, txq->type, esmp, sc->txq_entries, txq->buf_base_id, flags, evq->common, - &txq->common)) != 0) + &txq->common, &desc_index)) != 0) goto fail; + /* Initialise queue descriptor indexes */ + txq->added = txq->pending = txq->completed = txq->reaped = desc_index; + SFXGE_TXQ_LOCK(txq); /* Enable the transmit queue. */ efx_tx_qenable(txq->common); txq->init_state = SFXGE_TXQ_STARTED; + txq->flush_state = SFXGE_FLUSH_REQUIRED; SFXGE_TXQ_UNLOCK(txq); return (0); fail: efx_sram_buf_tbl_clear(sc->enp, txq->buf_base_id, EFX_TXQ_NBUFS(sc->txq_entries)); return (rc); } void sfxge_tx_stop(struct sfxge_softc *sc) { int index; index = sc->txq_count; while (--index >= 0) sfxge_tx_qstop(sc, index); /* Tear down the transmit module */ efx_tx_fini(sc->enp); } int sfxge_tx_start(struct sfxge_softc *sc) { int index; int rc; /* Initialize the common code transmit module. */ if ((rc = efx_tx_init(sc->enp)) != 0) return (rc); for (index = 0; index < sc->txq_count; index++) { if ((rc = sfxge_tx_qstart(sc, index)) != 0) goto fail; } return (0); fail: while (--index >= 0) sfxge_tx_qstop(sc, index); efx_tx_fini(sc->enp); return (rc); } static int sfxge_txq_stat_init(struct sfxge_txq *txq, struct sysctl_oid *txq_node) { struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(txq->sc->dev); struct sysctl_oid *stat_node; unsigned int id; stat_node = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(txq_node), OID_AUTO, "stats", CTLFLAG_RD, NULL, "Tx queue statistics"); if (stat_node == NULL) return (ENOMEM); for (id = 0; id < nitems(sfxge_tx_stats); id++) { SYSCTL_ADD_ULONG( ctx, SYSCTL_CHILDREN(stat_node), OID_AUTO, sfxge_tx_stats[id].name, CTLFLAG_RD | CTLFLAG_STATS, (unsigned long *)((caddr_t)txq + sfxge_tx_stats[id].offset), ""); } return (0); } /** * Destroy a transmit queue. */ static void sfxge_tx_qfini(struct sfxge_softc *sc, unsigned int index) { struct sfxge_txq *txq; unsigned int nmaps; txq = sc->txq[index]; KASSERT(txq->init_state == SFXGE_TXQ_INITIALIZED, ("txq->init_state != SFXGE_TXQ_INITIALIZED")); if (txq->type == SFXGE_TXQ_IP_TCP_UDP_CKSUM) tso_fini(txq); /* Free the context arrays. */ free(txq->pend_desc, M_SFXGE); nmaps = sc->txq_entries; while (nmaps-- != 0) bus_dmamap_destroy(txq->packet_dma_tag, txq->stmp[nmaps].map); free(txq->stmp, M_SFXGE); /* Release DMA memory mapping. */ sfxge_dma_free(&txq->mem); sc->txq[index] = NULL; SFXGE_TXQ_LOCK_DESTROY(txq); free(txq, M_SFXGE); } +/* + * Estimate maximum number of Tx descriptors required for TSO packet. + * With minimum MSS and maximum mbuf length we might need more (even + * than a ring-ful of descriptors), but this should not happen in + * practice except due to deliberate attack. In that case we will + * truncate the output at a packet boundary. + */ +static unsigned int +sfxge_tx_max_pkt_desc(const struct sfxge_softc *sc, enum sfxge_txq_type type) +{ + /* One descriptor for every input fragment */ + unsigned int max_descs = SFXGE_TX_MAPPING_MAX_SEG; + + /* VLAN tagging Tx option descriptor may be required */ + if (efx_nic_cfg_get(sc->enp)->enc_hw_tx_insert_vlan_enabled) + max_descs++; + + if (type == SFXGE_TXQ_IP_TCP_UDP_CKSUM) { + /* + * Plus header and payload descriptor for each output segment. + * Minus one since header fragment is already counted. + */ + max_descs += SFXGE_TSO_MAX_SEGS * 2 - 1; + + /* FW assisted TSO requires one more descriptor per segment */ + if (sc->tso_fw_assisted) + max_descs += SFXGE_TSO_MAX_SEGS; + } + + return (max_descs); +} + static int sfxge_tx_qinit(struct sfxge_softc *sc, unsigned int txq_index, - enum sfxge_txq_type type, unsigned int evq_index) + enum sfxge_txq_type type, unsigned int evq_index) { char name[16]; struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev); struct sysctl_oid *txq_node; struct sfxge_txq *txq; struct sfxge_evq *evq; struct sfxge_tx_dpl *stdp; struct sysctl_oid *dpl_node; efsys_mem_t *esmp; unsigned int nmaps; int rc; txq = malloc(sizeof(struct sfxge_txq), M_SFXGE, M_ZERO | M_WAITOK); txq->sc = sc; txq->entries = sc->txq_entries; txq->ptr_mask = txq->entries - 1; sc->txq[txq_index] = txq; esmp = &txq->mem; evq = sc->evq[evq_index]; /* Allocate and zero DMA space for the descriptor ring. */ if ((rc = sfxge_dma_alloc(sc, EFX_TXQ_SIZE(sc->txq_entries), esmp)) != 0) return (rc); /* Allocate buffer table entries. */ sfxge_sram_buf_tbl_alloc(sc, EFX_TXQ_NBUFS(sc->txq_entries), &txq->buf_base_id); /* Create a DMA tag for packet mappings. */ if (bus_dma_tag_create(sc->parent_dma_tag, 1, 0x1000, MIN(0x3FFFFFFFFFFFUL, BUS_SPACE_MAXADDR), BUS_SPACE_MAXADDR, NULL, NULL, 0x11000, SFXGE_TX_MAPPING_MAX_SEG, 0x1000, 0, NULL, NULL, &txq->packet_dma_tag) != 0) { device_printf(sc->dev, "Couldn't allocate txq DMA tag\n"); rc = ENOMEM; goto fail; } /* Allocate pending descriptor array for batching writes. */ - txq->pend_desc = malloc(sizeof(efx_buffer_t) * sc->txq_entries, + txq->pend_desc = malloc(sizeof(efx_desc_t) * sc->txq_entries, M_SFXGE, M_ZERO | M_WAITOK); /* Allocate and initialise mbuf DMA mapping array. */ txq->stmp = malloc(sizeof(struct sfxge_tx_mapping) * sc->txq_entries, M_SFXGE, M_ZERO | M_WAITOK); for (nmaps = 0; nmaps < sc->txq_entries; nmaps++) { rc = bus_dmamap_create(txq->packet_dma_tag, 0, &txq->stmp[nmaps].map); if (rc != 0) goto fail2; } snprintf(name, sizeof(name), "%u", txq_index); txq_node = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(sc->txqs_node), OID_AUTO, name, CTLFLAG_RD, NULL, ""); if (txq_node == NULL) { rc = ENOMEM; goto fail_txq_node; } if (type == SFXGE_TXQ_IP_TCP_UDP_CKSUM && (rc = tso_init(txq)) != 0) goto fail3; if (sfxge_tx_dpl_get_max <= 0) { log(LOG_ERR, "%s=%d must be greater than 0", SFXGE_PARAM_TX_DPL_GET_MAX, sfxge_tx_dpl_get_max); rc = EINVAL; goto fail_tx_dpl_get_max; } if (sfxge_tx_dpl_get_non_tcp_max <= 0) { log(LOG_ERR, "%s=%d must be greater than 0", SFXGE_PARAM_TX_DPL_GET_NON_TCP_MAX, sfxge_tx_dpl_get_non_tcp_max); rc = EINVAL; goto fail_tx_dpl_get_max; } if (sfxge_tx_dpl_put_max < 0) { log(LOG_ERR, "%s=%d must be greater or equal to 0", SFXGE_PARAM_TX_DPL_PUT_MAX, sfxge_tx_dpl_put_max); rc = EINVAL; goto fail_tx_dpl_put_max; } /* Initialize the deferred packet list. */ stdp = &txq->dpl; stdp->std_put_max = sfxge_tx_dpl_put_max; stdp->std_get_max = sfxge_tx_dpl_get_max; stdp->std_get_non_tcp_max = sfxge_tx_dpl_get_non_tcp_max; stdp->std_getp = &stdp->std_get; SFXGE_TXQ_LOCK_INIT(txq, device_get_nameunit(sc->dev), txq_index); dpl_node = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(txq_node), OID_AUTO, "dpl", CTLFLAG_RD, NULL, "Deferred packet list statistics"); if (dpl_node == NULL) { rc = ENOMEM; goto fail_dpl_node; } SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(dpl_node), OID_AUTO, "get_count", CTLFLAG_RD | CTLFLAG_STATS, &stdp->std_get_count, 0, ""); SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(dpl_node), OID_AUTO, "get_non_tcp_count", CTLFLAG_RD | CTLFLAG_STATS, &stdp->std_get_non_tcp_count, 0, ""); SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(dpl_node), OID_AUTO, "get_hiwat", CTLFLAG_RD | CTLFLAG_STATS, &stdp->std_get_hiwat, 0, ""); SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(dpl_node), OID_AUTO, "put_hiwat", CTLFLAG_RD | CTLFLAG_STATS, &stdp->std_put_hiwat, 0, ""); rc = sfxge_txq_stat_init(txq, txq_node); if (rc != 0) goto fail_txq_stat_init; txq->type = type; txq->evq_index = evq_index; txq->txq_index = txq_index; txq->init_state = SFXGE_TXQ_INITIALIZED; + txq->hw_vlan_tci = 0; + txq->max_pkt_desc = sfxge_tx_max_pkt_desc(sc, type); + return (0); fail_txq_stat_init: fail_dpl_node: fail_tx_dpl_put_max: fail_tx_dpl_get_max: fail3: fail_txq_node: free(txq->pend_desc, M_SFXGE); fail2: while (nmaps-- != 0) bus_dmamap_destroy(txq->packet_dma_tag, txq->stmp[nmaps].map); free(txq->stmp, M_SFXGE); bus_dma_tag_destroy(txq->packet_dma_tag); fail: sfxge_dma_free(esmp); return (rc); } static int sfxge_tx_stat_handler(SYSCTL_HANDLER_ARGS) { struct sfxge_softc *sc = arg1; unsigned int id = arg2; unsigned long sum; unsigned int index; /* Sum across all TX queues */ sum = 0; for (index = 0; index < sc->txq_count; index++) sum += *(unsigned long *)((caddr_t)sc->txq[index] + sfxge_tx_stats[id].offset); return (SYSCTL_OUT(req, &sum, sizeof(sum))); } static void sfxge_tx_stat_init(struct sfxge_softc *sc) { struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev); struct sysctl_oid_list *stat_list; unsigned int id; stat_list = SYSCTL_CHILDREN(sc->stats_node); for (id = 0; id < nitems(sfxge_tx_stats); id++) { SYSCTL_ADD_PROC( ctx, stat_list, OID_AUTO, sfxge_tx_stats[id].name, CTLTYPE_ULONG|CTLFLAG_RD, sc, id, sfxge_tx_stat_handler, "LU", ""); } } uint64_t sfxge_tx_get_drops(struct sfxge_softc *sc) { unsigned int index; uint64_t drops = 0; struct sfxge_txq *txq; /* Sum across all TX queues */ for (index = 0; index < sc->txq_count; index++) { txq = sc->txq[index]; /* * In theory, txq->put_overflow and txq->netdown_drops * should use atomic operation and other should be * obtained under txq lock, but it is just statistics. */ drops += txq->drops + txq->get_overflow + txq->get_non_tcp_overflow + txq->put_overflow + txq->netdown_drops + txq->tso_pdrop_too_many + txq->tso_pdrop_no_rsrc; } return (drops); } void sfxge_tx_fini(struct sfxge_softc *sc) { int index; index = sc->txq_count; while (--index >= 0) sfxge_tx_qfini(sc, index); sc->txq_count = 0; } int sfxge_tx_init(struct sfxge_softc *sc) { + const efx_nic_cfg_t *encp = efx_nic_cfg_get(sc->enp); struct sfxge_intr *intr; int index; int rc; intr = &sc->intr; KASSERT(intr->state == SFXGE_INTR_INITIALIZED, ("intr->state != SFXGE_INTR_INITIALIZED")); sc->txq_count = SFXGE_TXQ_NTYPES - 1 + sc->intr.n_alloc; + + sc->tso_fw_assisted = sfxge_tso_fw_assisted; + if (sc->tso_fw_assisted) + sc->tso_fw_assisted = + (encp->enc_features & EFX_FEATURE_FW_ASSISTED_TSO) && + (encp->enc_fw_assisted_tso_enabled); sc->txqs_node = SYSCTL_ADD_NODE( device_get_sysctl_ctx(sc->dev), SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "txq", CTLFLAG_RD, NULL, "Tx queues"); if (sc->txqs_node == NULL) { rc = ENOMEM; goto fail_txq_node; } /* Initialize the transmit queues */ if ((rc = sfxge_tx_qinit(sc, SFXGE_TXQ_NON_CKSUM, SFXGE_TXQ_NON_CKSUM, 0)) != 0) goto fail; if ((rc = sfxge_tx_qinit(sc, SFXGE_TXQ_IP_CKSUM, SFXGE_TXQ_IP_CKSUM, 0)) != 0) goto fail2; for (index = 0; index < sc->txq_count - SFXGE_TXQ_NTYPES + 1; index++) { if ((rc = sfxge_tx_qinit(sc, SFXGE_TXQ_NTYPES - 1 + index, SFXGE_TXQ_IP_TCP_UDP_CKSUM, index)) != 0) goto fail3; } sfxge_tx_stat_init(sc); return (0); fail3: while (--index >= 0) sfxge_tx_qfini(sc, SFXGE_TXQ_IP_TCP_UDP_CKSUM + index); sfxge_tx_qfini(sc, SFXGE_TXQ_IP_CKSUM); fail2: sfxge_tx_qfini(sc, SFXGE_TXQ_NON_CKSUM); fail: fail_txq_node: sc->txq_count = 0; return (rc); } Property changes on: head/sys/dev/sfxge/sfxge_tx.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/sfxge_tx.h =================================================================== --- head/sys/dev/sfxge/sfxge_tx.h (revision 283513) +++ head/sys/dev/sfxge/sfxge_tx.h (revision 283514) @@ -1,225 +1,234 @@ /*- - * Copyright (c) 2010-2011 Solarflare Communications, Inc. + * Copyright (c) 2010-2015 Solarflare Communications Inc. * All rights reserved. * * This software was developed in part by Philip Paeps under contract for * Solarflare Communications, Inc. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + * * $FreeBSD$ */ #ifndef _SFXGE_TX_H #define _SFXGE_TX_H #include #include #include /* Maximum size of TSO packet */ #define SFXGE_TSO_MAX_SIZE (65535) /* * Maximum number of segments to be created for a TSO packet. * Allow for a reasonable minimum MSS of 512. */ #define SFXGE_TSO_MAX_SEGS howmany(SFXGE_TSO_MAX_SIZE, 512) /* Maximum number of DMA segments needed to map an mbuf chain. With * TSO, the mbuf length may be just over 64K, divided into 2K mbuf * clusters. (The chain could be longer than this initially, but can * be shortened with m_collapse().) */ #define SFXGE_TX_MAPPING_MAX_SEG \ (1 + howmany(SFXGE_TSO_MAX_SIZE, MCLBYTES)) /* * Buffer mapping flags. * * Buffers and DMA mappings must be freed when the last descriptor * referring to them is completed. Set the TX_BUF_UNMAP and * TX_BUF_MBUF flags on the last descriptor generated for an mbuf * chain. Set only the TX_BUF_UNMAP flag on a descriptor referring to * a heap buffer. */ enum sfxge_tx_buf_flags { TX_BUF_UNMAP = 1, TX_BUF_MBUF = 2, }; /* * Buffer mapping information for descriptors in flight. */ struct sfxge_tx_mapping { union { struct mbuf *mbuf; caddr_t heap_buf; } u; bus_dmamap_t map; enum sfxge_tx_buf_flags flags; }; #define SFXGE_TX_DPL_GET_PKT_LIMIT_DEFAULT (64 * 1024) #define SFXGE_TX_DPL_GET_NON_TCP_PKT_LIMIT_DEFAULT 1024 #define SFXGE_TX_DPL_PUT_PKT_LIMIT_DEFAULT 1024 /* * Deferred packet list. */ struct sfxge_tx_dpl { unsigned int std_get_max; /* Maximum number of packets * in get list */ unsigned int std_get_non_tcp_max; /* Maximum number * of non-TCP packets * in get list */ unsigned int std_put_max; /* Maximum number of packets * in put list */ uintptr_t std_put; /* Head of put list. */ struct mbuf *std_get; /* Head of get list. */ struct mbuf **std_getp; /* Tail of get list. */ unsigned int std_get_count; /* Packets in get list. */ unsigned int std_get_non_tcp_count; /* Non-TCP packets * in get list */ unsigned int std_get_hiwat; /* Packets in get list * high watermark */ unsigned int std_put_hiwat; /* Packets in put list * high watermark */ }; #define SFXGE_TX_BUFFER_SIZE 0x400 #define SFXGE_TX_HEADER_SIZE 0x100 #define SFXGE_TX_COPY_THRESHOLD 0x200 enum sfxge_txq_state { SFXGE_TXQ_UNINITIALIZED = 0, SFXGE_TXQ_INITIALIZED, SFXGE_TXQ_STARTED }; enum sfxge_txq_type { SFXGE_TXQ_NON_CKSUM = 0, SFXGE_TXQ_IP_CKSUM, SFXGE_TXQ_IP_TCP_UDP_CKSUM, SFXGE_TXQ_NTYPES }; #define SFXGE_TXQ_UNBLOCK_LEVEL(_entries) (EFX_TXQ_LIMIT(_entries) / 4) #define SFXGE_TX_BATCH 64 #define SFXGE_TXQ_LOCK_INIT(_txq, _ifname, _txq_index) \ do { \ struct sfxge_txq *__txq = (_txq); \ \ snprintf((__txq)->lock_name, \ sizeof((__txq)->lock_name), \ "%s:txq%u", (_ifname), (_txq_index)); \ mtx_init(&(__txq)->lock, (__txq)->lock_name, \ NULL, MTX_DEF); \ } while (B_FALSE) #define SFXGE_TXQ_LOCK_DESTROY(_txq) \ mtx_destroy(&(_txq)->lock) #define SFXGE_TXQ_LOCK(_txq) \ mtx_lock(&(_txq)->lock) #define SFXGE_TXQ_TRYLOCK(_txq) \ mtx_trylock(&(_txq)->lock) #define SFXGE_TXQ_UNLOCK(_txq) \ mtx_unlock(&(_txq)->lock) #define SFXGE_TXQ_LOCK_ASSERT_OWNED(_txq) \ mtx_assert(&(_txq)->lock, MA_OWNED) #define SFXGE_TXQ_LOCK_ASSERT_NOTOWNED(_txq) \ mtx_assert(&(_txq)->lock, MA_NOTOWNED) struct sfxge_txq { /* The following fields should be written very rarely */ struct sfxge_softc *sc; enum sfxge_txq_state init_state; enum sfxge_flush_state flush_state; enum sfxge_txq_type type; unsigned int txq_index; unsigned int evq_index; efsys_mem_t mem; unsigned int buf_base_id; unsigned int entries; unsigned int ptr_mask; + unsigned int max_pkt_desc; struct sfxge_tx_mapping *stmp; /* Packets in flight. */ bus_dma_tag_t packet_dma_tag; - efx_buffer_t *pend_desc; + efx_desc_t *pend_desc; efx_txq_t *common; efsys_mem_t *tsoh_buffer; char lock_name[SFXGE_LOCK_NAME_MAX]; /* This field changes more often and is read regularly on both * the initiation and completion paths */ int blocked __aligned(CACHE_LINE_SIZE); /* The following fields change more often, and are used mostly * on the initiation path */ struct mtx lock __aligned(CACHE_LINE_SIZE); struct sfxge_tx_dpl dpl; /* Deferred packet list. */ unsigned int n_pend_desc; unsigned int added; unsigned int reaped; + + /* The last VLAN TCI seen on the queue if FW-assisted tagging is + used */ + uint16_t hw_vlan_tci; + /* Statistics */ unsigned long tso_bursts; unsigned long tso_packets; unsigned long tso_long_headers; unsigned long collapses; unsigned long drops; unsigned long get_overflow; unsigned long get_non_tcp_overflow; unsigned long put_overflow; unsigned long netdown_drops; unsigned long tso_pdrop_too_many; unsigned long tso_pdrop_no_rsrc; /* The following fields change more often, and are used mostly * on the completion path */ unsigned int pending __aligned(CACHE_LINE_SIZE); unsigned int completed; struct sfxge_txq *next; }; struct sfxge_evq; -extern int sfxge_tx_packet_add(struct sfxge_txq *, struct mbuf *); extern uint64_t sfxge_tx_get_drops(struct sfxge_softc *sc); extern int sfxge_tx_init(struct sfxge_softc *sc); extern void sfxge_tx_fini(struct sfxge_softc *sc); extern int sfxge_tx_start(struct sfxge_softc *sc); extern void sfxge_tx_stop(struct sfxge_softc *sc); extern void sfxge_tx_qcomplete(struct sfxge_txq *txq, struct sfxge_evq *evq); extern void sfxge_tx_qflush_done(struct sfxge_txq *txq); extern void sfxge_if_qflush(struct ifnet *ifp); extern int sfxge_if_transmit(struct ifnet *ifp, struct mbuf *m); #endif Property changes on: head/sys/dev/sfxge/sfxge_tx.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/sfxge/sfxge_version.h =================================================================== --- head/sys/dev/sfxge/sfxge_version.h (revision 283513) +++ head/sys/dev/sfxge/sfxge_version.h (revision 283514) @@ -1,37 +1,41 @@ /*- - * Copyright (c) 2015 Solarflare Communications, Inc. + * Copyright (c) 2015 Solarflare Communications Inc. * All rights reserved. * * This software was developed in part by OKTET Labs under contract for * Solarflare Communications, Inc. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * modification, are permitted provided that the following conditions are met: * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + * * $FreeBSD$ */ #ifndef _SFXGE_VERSION_H #define _SFXGE_VERSION_H -#define SFXGE_VERSION_STRING "v3.3.4.6365" +#define SFXGE_VERSION_STRING "v4.5.1.1018" #endif /* _SFXGE_DRIVER_VERSION_H */ Index: head/sys/modules/sfxge/Makefile =================================================================== --- head/sys/modules/sfxge/Makefile (revision 283513) +++ head/sys/modules/sfxge/Makefile (revision 283514) @@ -1,30 +1,39 @@ # $FreeBSD$ KMOD= sfxge SFXGE= ${.CURDIR}/../../dev/sfxge SRCS= device_if.h bus_if.h pci_if.h SRCS+= opt_inet.h opt_inet6.h opt_sched.h .PATH: ${.CURDIR}/../../dev/sfxge SRCS+= sfxge.c sfxge_dma.c sfxge_ev.c -SRCS+= sfxge_intr.c sfxge_mcdi.c +SRCS+= sfxge_intr.c sfxge_mcdi.c sfxge_nvram.c SRCS+= sfxge_port.c sfxge_rx.c sfxge_tx.c SRCS+= sfxge.h sfxge_rx.h sfxge_tx.h sfxge_version.h .PATH: ${.CURDIR}/../../dev/sfxge/common -SRCS+= efx_ev.c efx_intr.c efx_mac.c efx_mcdi.c efx_nic.c +SRCS+= efx_bootcfg.c efx_crc32.c efx_ev.c efx_intr.c efx_mac.c +SRCS+= efx_mcdi.c efx_mon.c efx_nic.c SRCS+= efx_nvram.c efx_phy.c efx_port.c efx_rx.c efx_sram.c efx_tx.c -SRCS+= efx_vpd.c efx_wol.c +SRCS+= efx_vpd.c efx_wol.c efx_filter.c efx_hash.c SRCS+= efsys.h -SRCS+= efx.h efx_impl.h efx_mcdi.h efx_regs.h efx_regs_ef10.h -SRCS+= efx_regs_mcdi.h efx_regs_pci.h efx_types.h +SRCS+= efx.h efx_check.h efx_impl.h efx_mcdi.h efx_regs.h efx_regs_ef10.h +SRCS+= efx_regs_mcdi.h efx_regs_pci.h efx_types.h efx_phy_ids.h +SRCS+= ef10_tlv_layout.h -SRCS+= siena_mac.c siena_nic.c siena_nvram.c siena_phy.c +SRCS+= mcdi_mon.c mcdi_mon.h + +SRCS+= siena_mac.c siena_mcdi.c siena_nic.c siena_nvram.c siena_phy.c SRCS+= siena_sram.c siena_vpd.c SRCS+= siena_flash.h siena_impl.h + +SRCS+= hunt_ev.c hunt_intr.c hunt_mac.c hunt_mcdi.c hunt_nic.c +SRCS+= hunt_nvram.c hunt_rx.c hunt_phy.c hunt_sram.c hunt_tx.c hunt_vpd.c +SRCS+= hunt_filter.c +SRCS+= hunt_impl.h DEBUG_FLAGS= -DDEBUG=1 .include Property changes on: head/sys/modules/sfxge/Makefile ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property