Index: stable/10/sys/arm/conf/APALIS-IMX6 =================================================================== --- stable/10/sys/arm/conf/APALIS-IMX6 (nonexistent) +++ stable/10/sys/arm/conf/APALIS-IMX6 (revision 283500) @@ -0,0 +1,31 @@ +# Kernel configuration for Toradex Apalis i.MX6 +# +# For more information on this file, please read the config(5) manual page, +# and/or the handbook section on Kernel Configuration Files: +# +# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html +# +# The handbook is also available locally in /usr/share/doc/handbook +# if you've installed the doc distribution, otherwise always see the +# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the +# latest information. +# +# An exhaustive list of options and more detailed explanations of the +# device lines is also present in the ../../conf/NOTES and NOTES files. +# If you are in doubt as to the purpose or necessity of a line, check first +# in NOTES. +# +# $FreeBSD$ + +#NO_UNIVERSE + +include "IMX6" +ident APALIS-IMX6 + +makeoptions MODULES_OVERRIDE="" +makeoptions WITHOUT_MODULES="ahc" + +# Flattened Device Tree +options FDT +options FDT_DTB_STATIC +makeoptions FDT_DTS_FILE=apalis-imx6.dts Property changes on: stable/10/sys/arm/conf/APALIS-IMX6 ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/10/sys/arm/freescale/imx/files.imx6 =================================================================== --- stable/10/sys/arm/freescale/imx/files.imx6 (revision 283499) +++ stable/10/sys/arm/freescale/imx/files.imx6 (revision 283500) @@ -1,54 +1,73 @@ # $FreeBSD$ # # Standard ARM support. # arm/arm/bus_space_asm_generic.S standard arm/arm/bus_space_generic.c standard arm/arm/cpufunc_asm_arm11.S standard arm/arm/cpufunc_asm_armv5.S standard arm/arm/cpufunc_asm_armv7.S standard kern/kern_clocksource.c standard # # Standard imx6 devices and support. # arm/arm/gic.c standard arm/arm/pl310.c standard arm/arm/bus_space_base.c standard arm/arm/mpcore_timer.c standard arm/freescale/fsl_ocotp.c standard arm/freescale/imx/imx6_anatop.c standard arm/freescale/imx/imx6_ccm.c standard arm/freescale/imx/imx6_machdep.c standard arm/freescale/imx/imx6_mp.c optional smp arm/freescale/imx/imx6_pl310.c standard arm/freescale/imx/imx_iomux.c standard arm/freescale/imx/imx_machdep.c standard arm/freescale/imx/imx_gpt.c standard arm/freescale/imx/imx_gpio.c optional gpio arm/freescale/imx/imx_i2c.c optional fsliic +arm/freescale/imx/imx6_sdma.c optional sdma +arm/freescale/imx/imx6_audmux.c optional sound +arm/freescale/imx/imx6_ssi.c optional sound # # Optional devices. # arm/freescale/imx/imx_sdhci.c optional sdhci arm/freescale/imx/imx_wdog.c optional imxwdt dev/ffec/if_ffec.c optional ffec dev/uart/uart_dev_imx.c optional uart dev/usb/controller/ehci_imx.c optional ehci arm/freescale/imx/imx6_usbphy.c optional ehci # # Low-level serial console for debugging early kernel startup. # #arm/freescale/imx/console.c standard # # Not ready yet... # #arm/freescale/imx/imx51_ipuv3.c optional sc + +# SDMA firmware +sdma_fw.c optional sdma_fw \ + compile-with "${AWK} -f $S/tools/fw_stub.awk sdma-imx6q-to1.bin:sdma_fw -msdma -c${.TARGET}" \ + no-implicit-rule before-depend local \ + clean "sdma_fw.c" +sdma-imx6q-to1.fwo optional sdma_fw \ + dependency "sdma-imx6q-to1.bin" \ + compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} sdma-imx6q-to1.bin" \ + no-implicit-rule \ + clean "sdma-imx6q-to1.fwo" +sdma-imx6q-to1.bin optional sdma_fw \ + dependency "$S/contrib/dev/imx/sdma-imx6q-to1.bin.uu" \ + compile-with "uudecode < $S/contrib/dev/imx/sdma-imx6q-to1.bin.uu" \ + no-obj no-implicit-rule \ + clean "sdma-imx6q-to1.bin" Index: stable/10/sys/arm/freescale/imx/imx6_anatop.c =================================================================== --- stable/10/sys/arm/freescale/imx/imx6_anatop.c (revision 283499) +++ stable/10/sys/arm/freescale/imx/imx6_anatop.c (revision 283500) @@ -1,765 +1,786 @@ /*- * Copyright (c) 2013 Ian Lepore * Copyright (c) 2014 Steven Lawrance * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * Analog PLL and power regulator driver for Freescale i.MX6 family of SoCs. * Also, temperature montoring and cpu frequency control. It was Freescale who * kitchen-sinked this device, not us. :) * * We don't really do anything with analog PLLs, but the registers for * controlling them belong to the same block as the power regulator registers. * Since the newbus hierarchy makes it hard for anyone other than us to get at * them, we just export a couple public functions to allow the imx6 CCM clock * driver to read and write those registers. * * We also don't do anything about power regulation yet, but when the need * arises, this would be the place for that code to live. * * I have no idea where the "anatop" name comes from. It's in the standard DTS * source describing i.MX6 SoCs, and in the linux and u-boot code which comes * from Freescale, but it's not in the SoC manual. * * Note that temperature values throughout this code are handled in two types of * units. Items with '_cnt' in the name use the hardware temperature count * units (higher counts are lower temperatures). Items with '_val' in the name * are deci-Celcius, which are converted to/from deci-Kelvins in the sysctl * handlers (dK is the standard unit for temperature in sysctl). */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include static SYSCTL_NODE(_hw, OID_AUTO, imx6, CTLFLAG_RW, NULL, "i.MX6 container"); static struct resource_spec imx6_anatop_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE }, { -1, 0 } }; #define MEMRES 0 #define IRQRES 1 struct imx6_anatop_softc { device_t dev; struct resource *res[2]; struct intr_config_hook intr_setup_hook; uint32_t cpu_curmhz; uint32_t cpu_curmv; uint32_t cpu_minmhz; uint32_t cpu_minmv; uint32_t cpu_maxmhz; uint32_t cpu_maxmv; uint32_t cpu_maxmhz_hw; boolean_t cpu_overclock_enable; boolean_t cpu_init_done; uint32_t refosc_mhz; void *temp_intrhand; uint32_t temp_high_val; uint32_t temp_high_cnt; uint32_t temp_last_cnt; uint32_t temp_room_cnt; struct callout temp_throttle_callout; sbintime_t temp_throttle_delay; uint32_t temp_throttle_reset_cnt; uint32_t temp_throttle_trigger_cnt; uint32_t temp_throttle_val; }; static struct imx6_anatop_softc *imx6_anatop_sc; /* * Table of "operating points". * These are combinations of frequency and voltage blessed by Freescale. */ static struct oppt { uint32_t mhz; uint32_t mv; } imx6_oppt_table[] = { /* { 396, 925}, XXX: need functional ccm code for this speed */ { 792, 1150}, { 852, 1225}, { 996, 1225}, {1200, 1275}, }; /* * Table of CPU max frequencies. This is used to translate the max frequency * value (0-3) from the ocotp CFG3 register into a mhz value that can be looked * up in the operating points table. */ static uint32_t imx6_ocotp_mhz_tab[] = {792, 852, 996, 1200}; #define TZ_ZEROC 2732 /* deci-Kelvin <-> deci-Celcius offset. */ uint32_t imx6_anatop_read_4(bus_size_t offset) { KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_read_4 sc NULL")); return (bus_read_4(imx6_anatop_sc->res[MEMRES], offset)); } void imx6_anatop_write_4(bus_size_t offset, uint32_t value) { KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_write_4 sc NULL")); bus_write_4(imx6_anatop_sc->res[MEMRES], offset, value); } static void vdd_set(struct imx6_anatop_softc *sc, int mv) { int newtarg, oldtarg; uint32_t delay, pmureg; static boolean_t init_done = false; /* * The datasheet says VDD_PU and VDD_SOC must be equal, and VDD_ARM * can't be more than 50mV above or 200mV below them. For now to keep * things simple we set all three to the same value. */ pmureg = imx6_anatop_read_4(IMX6_ANALOG_PMU_REG_CORE); oldtarg = pmureg & IMX6_ANALOG_PMU_REG0_TARG_MASK; /* Convert mV to target value. Clamp target to valid range. */ if (mv < 725) newtarg = 0x00; else if (mv > 1450) newtarg = 0x1F; else newtarg = (mv - 700) / 25; /* * The first time through the 3 voltages might not be equal so use a * long conservative delay. After that we need to delay 3uS for every * 25mV step upward. No need to delay at all when lowering. */ if (init_done) { if (newtarg == oldtarg) return; else if (newtarg > oldtarg) delay = (newtarg - oldtarg) * 3; else delay = 0; } else { delay = 700 / 25 * 3; init_done = true; } /* * Make the change and wait for it to take effect. */ pmureg &= ~(IMX6_ANALOG_PMU_REG0_TARG_MASK | IMX6_ANALOG_PMU_REG1_TARG_MASK | IMX6_ANALOG_PMU_REG2_TARG_MASK); pmureg |= newtarg << IMX6_ANALOG_PMU_REG0_TARG_SHIFT; pmureg |= newtarg << IMX6_ANALOG_PMU_REG1_TARG_SHIFT; pmureg |= newtarg << IMX6_ANALOG_PMU_REG2_TARG_SHIFT; imx6_anatop_write_4(IMX6_ANALOG_PMU_REG_CORE, pmureg); DELAY(delay); sc->cpu_curmv = newtarg * 25 + 700; } static inline uint32_t cpufreq_mhz_from_div(struct imx6_anatop_softc *sc, uint32_t div) { return (sc->refosc_mhz * (div / 2)); } static inline uint32_t cpufreq_mhz_to_div(struct imx6_anatop_softc *sc, uint32_t cpu_mhz) { return (cpu_mhz / (sc->refosc_mhz / 2)); } static inline uint32_t cpufreq_actual_mhz(struct imx6_anatop_softc *sc, uint32_t cpu_mhz) { return (cpufreq_mhz_from_div(sc, cpufreq_mhz_to_div(sc, cpu_mhz))); } static struct oppt * cpufreq_nearest_oppt(struct imx6_anatop_softc *sc, uint32_t cpu_newmhz) { int d, diff, i, nearest; if (cpu_newmhz > sc->cpu_maxmhz_hw && !sc->cpu_overclock_enable) cpu_newmhz = sc->cpu_maxmhz_hw; diff = INT_MAX; nearest = 0; for (i = 0; i < nitems(imx6_oppt_table); ++i) { d = abs((int)cpu_newmhz - (int)imx6_oppt_table[i].mhz); if (diff > d) { diff = d; nearest = i; } } return (&imx6_oppt_table[nearest]); } static void cpufreq_set_clock(struct imx6_anatop_softc * sc, struct oppt *op) { uint32_t timeout, wrk32; /* If increasing the frequency, we must first increase the voltage. */ if (op->mhz > sc->cpu_curmhz) { vdd_set(sc, op->mv); } /* * I can't find a documented procedure for changing the ARM PLL divisor, * but some trial and error came up with this: * - Set the bypass clock source to REF_CLK_24M (source #0). * - Set the PLL into bypass mode; cpu should now be running at 24mhz. * - Change the divisor. * - Wait for the LOCK bit to come on; it takes ~50 loop iterations. * - Turn off bypass mode; cpu should now be running at the new speed. */ imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR, IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK); imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_SET, IMX6_ANALOG_CCM_PLL_ARM_BYPASS); wrk32 = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM); wrk32 &= ~IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK; wrk32 |= cpufreq_mhz_to_div(sc, op->mhz); imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM, wrk32); timeout = 10000; while ((imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) & IMX6_ANALOG_CCM_PLL_ARM_LOCK) == 0) if (--timeout == 0) panic("imx6_set_cpu_clock(): PLL never locked"); imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR, IMX6_ANALOG_CCM_PLL_ARM_BYPASS); /* If lowering the frequency, it is now safe to lower the voltage. */ if (op->mhz < sc->cpu_curmhz) vdd_set(sc, op->mv); sc->cpu_curmhz = op->mhz; /* Tell the mpcore timer that its frequency has changed. */ arm_tmr_change_frequency( cpufreq_actual_mhz(sc, sc->cpu_curmhz) * 1000000 / 2); } static int cpufreq_sysctl_minmhz(SYSCTL_HANDLER_ARGS) { struct imx6_anatop_softc *sc; struct oppt * op; uint32_t temp; int err; sc = arg1; temp = sc->cpu_minmhz; err = sysctl_handle_int(oidp, &temp, 0, req); if (err != 0 || req->newptr == NULL) return (err); op = cpufreq_nearest_oppt(sc, temp); if (op->mhz > sc->cpu_maxmhz) return (ERANGE); else if (op->mhz == sc->cpu_minmhz) return (0); /* * Value changed, update softc. If the new min is higher than the * current speed, raise the current speed to match. */ sc->cpu_minmhz = op->mhz; if (sc->cpu_minmhz > sc->cpu_curmhz) { cpufreq_set_clock(sc, op); } return (err); } static int cpufreq_sysctl_maxmhz(SYSCTL_HANDLER_ARGS) { struct imx6_anatop_softc *sc; struct oppt * op; uint32_t temp; int err; sc = arg1; temp = sc->cpu_maxmhz; err = sysctl_handle_int(oidp, &temp, 0, req); if (err != 0 || req->newptr == NULL) return (err); op = cpufreq_nearest_oppt(sc, temp); if (op->mhz < sc->cpu_minmhz) return (ERANGE); else if (op->mhz == sc->cpu_maxmhz) return (0); /* * Value changed, update softc and hardware. The hardware update is * unconditional. We always try to run at max speed, so any change of * the max means we need to change the current speed too, regardless of * whether it is higher or lower than the old max. */ sc->cpu_maxmhz = op->mhz; cpufreq_set_clock(sc, op); return (err); } static void cpufreq_initialize(struct imx6_anatop_softc *sc) { uint32_t cfg3speed; struct oppt * op; SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), OID_AUTO, "cpu_mhz", CTLFLAG_RD, &sc->cpu_curmhz, 0, "CPU frequency"); SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), OID_AUTO, "cpu_minmhz", CTLTYPE_INT | CTLFLAG_RWTUN, sc, 0, cpufreq_sysctl_minmhz, "IU", "Minimum CPU frequency"); SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), OID_AUTO, "cpu_maxmhz", CTLTYPE_INT | CTLFLAG_RWTUN, sc, 0, cpufreq_sysctl_maxmhz, "IU", "Maximum CPU frequency"); SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), OID_AUTO, "cpu_maxmhz_hw", CTLFLAG_RD, &sc->cpu_maxmhz_hw, 0, "Maximum CPU frequency allowed by hardware"); SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), OID_AUTO, "cpu_overclock_enable", CTLFLAG_RWTUN, &sc->cpu_overclock_enable, 0, "Allow setting CPU frequency higher than cpu_maxmhz_hw"); /* * XXX 24mhz shouldn't be hard-coded, should get this from imx6_ccm * (even though in the real world it will always be 24mhz). Oh wait a * sec, I never wrote imx6_ccm. */ sc->refosc_mhz = 24; /* * Get the maximum speed this cpu can be set to. The values in the * OCOTP CFG3 register are not documented in the reference manual. * The following info was in an archived email found via web search: * - 2b'11: 1200000000Hz; * - 2b'10: 996000000Hz; * - 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz. * - 2b'00: 792000000Hz; * The default hardware max speed can be overridden by a tunable. */ cfg3speed = (fsl_ocotp_read_4(FSL_OCOTP_CFG3) & FSL_OCOTP_CFG3_SPEED_MASK) >> FSL_OCOTP_CFG3_SPEED_SHIFT; sc->cpu_maxmhz_hw = imx6_ocotp_mhz_tab[cfg3speed]; sc->cpu_maxmhz = sc->cpu_maxmhz_hw; TUNABLE_INT_FETCH("hw.imx6.cpu_overclock_enable", &sc->cpu_overclock_enable); TUNABLE_INT_FETCH("hw.imx6.cpu_minmhz", &sc->cpu_minmhz); op = cpufreq_nearest_oppt(sc, sc->cpu_minmhz); sc->cpu_minmhz = op->mhz; sc->cpu_minmv = op->mv; TUNABLE_INT_FETCH("hw.imx6.cpu_maxmhz", &sc->cpu_maxmhz); op = cpufreq_nearest_oppt(sc, sc->cpu_maxmhz); sc->cpu_maxmhz = op->mhz; sc->cpu_maxmv = op->mv; /* * Set the CPU to maximum speed. * * We won't have thermal throttling until interrupts are enabled, but we * want to run at full speed through all the device init stuff. This * basically assumes that a single core can't overheat before interrupts * are enabled; empirical testing shows that to be a safe assumption. */ cpufreq_set_clock(sc, op); } static inline uint32_t temp_from_count(struct imx6_anatop_softc *sc, uint32_t count) { return (((sc->temp_high_val - (count - sc->temp_high_cnt) * (sc->temp_high_val - 250) / (sc->temp_room_cnt - sc->temp_high_cnt)))); } static inline uint32_t temp_to_count(struct imx6_anatop_softc *sc, uint32_t temp) { return ((sc->temp_room_cnt - sc->temp_high_cnt) * (sc->temp_high_val - temp) / (sc->temp_high_val - 250) + sc->temp_high_cnt); } static void temp_update_count(struct imx6_anatop_softc *sc) { uint32_t val; val = imx6_anatop_read_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0); if (!(val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_VALID)) return; sc->temp_last_cnt = (val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) >> IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT; } static int temp_sysctl_handler(SYSCTL_HANDLER_ARGS) { struct imx6_anatop_softc *sc = arg1; uint32_t t; temp_update_count(sc); t = temp_from_count(sc, sc->temp_last_cnt) + TZ_ZEROC; return (sysctl_handle_int(oidp, &t, 0, req)); } static int temp_throttle_sysctl_handler(SYSCTL_HANDLER_ARGS) { struct imx6_anatop_softc *sc = arg1; int err; uint32_t temp; temp = sc->temp_throttle_val + TZ_ZEROC; err = sysctl_handle_int(oidp, &temp, 0, req); if (temp < TZ_ZEROC) return (ERANGE); temp -= TZ_ZEROC; if (err != 0 || req->newptr == NULL || temp == sc->temp_throttle_val) return (err); /* Value changed, update counts in softc and hardware. */ sc->temp_throttle_val = temp; sc->temp_throttle_trigger_cnt = temp_to_count(sc, sc->temp_throttle_val); sc->temp_throttle_reset_cnt = temp_to_count(sc, sc->temp_throttle_val - 100); imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_CLR, IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_MASK); imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_SET, (sc->temp_throttle_trigger_cnt << IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT)); return (err); } static void tempmon_gofast(struct imx6_anatop_softc *sc) { if (sc->cpu_curmhz < sc->cpu_maxmhz) { cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_maxmhz)); } } static void tempmon_goslow(struct imx6_anatop_softc *sc) { if (sc->cpu_curmhz > sc->cpu_minmhz) { cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_minmhz)); } } static int tempmon_intr(void *arg) { struct imx6_anatop_softc *sc = arg; /* * XXX Note that this code doesn't currently run (for some mysterious * reason we just never get an interrupt), so the real monitoring is * done by tempmon_throttle_check(). */ tempmon_goslow(sc); /* XXX Schedule callout to speed back up eventually. */ return (FILTER_HANDLED); } static void tempmon_throttle_check(void *arg) { struct imx6_anatop_softc *sc = arg; /* Lower counts are higher temperatures. */ if (sc->temp_last_cnt < sc->temp_throttle_trigger_cnt) tempmon_goslow(sc); else if (sc->temp_last_cnt > (sc->temp_throttle_reset_cnt)) tempmon_gofast(sc); callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay, 0, tempmon_throttle_check, sc, 0); } static void initialize_tempmon(struct imx6_anatop_softc *sc) { uint32_t cal; /* * Fetch calibration data: a sensor count at room temperature (25C), * a sensor count at a high temperature, and that temperature */ cal = fsl_ocotp_read_4(FSL_OCOTP_ANA1); sc->temp_room_cnt = (cal & 0xFFF00000) >> 20; sc->temp_high_cnt = (cal & 0x000FFF00) >> 8; sc->temp_high_val = (cal & 0x000000FF) * 10; /* * Throttle to a lower cpu freq at 10C below the "hot" temperature, and * reset back to max cpu freq at 5C below the trigger. */ sc->temp_throttle_val = sc->temp_high_val - 100; sc->temp_throttle_trigger_cnt = temp_to_count(sc, sc->temp_throttle_val); sc->temp_throttle_reset_cnt = temp_to_count(sc, sc->temp_throttle_val - 50); /* * Set the sensor to sample automatically at 16Hz (32.768KHz/0x800), set * the throttle count, and begin making measurements. */ imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE1, 0x0800); imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0, (sc->temp_throttle_trigger_cnt << IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT) | IMX6_ANALOG_TEMPMON_TEMPSENSE0_MEASURE); /* * XXX Note that the alarm-interrupt feature isn't working yet, so * we'll use a callout handler to check at 10Hz. Make sure we have an * initial temperature reading before starting up the callouts so we * don't get a bogus reading of zero. */ while (sc->temp_last_cnt == 0) temp_update_count(sc); sc->temp_throttle_delay = 100 * SBT_1MS; callout_init(&sc->temp_throttle_callout, 0); callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay, 0, tempmon_throttle_check, sc, 0); SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD, sc, 0, temp_sysctl_handler, "IK", "Current die temperature"); SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), OID_AUTO, "throttle_temperature", CTLTYPE_INT | CTLFLAG_RW, sc, 0, temp_throttle_sysctl_handler, "IK", "Throttle CPU when exceeding this temperature"); } static void intr_setup(void *arg) { struct imx6_anatop_softc *sc; sc = arg; bus_setup_intr(sc->dev, sc->res[IRQRES], INTR_TYPE_MISC | INTR_MPSAFE, tempmon_intr, NULL, sc, &sc->temp_intrhand); config_intrhook_disestablish(&sc->intr_setup_hook); } static void imx6_anatop_new_pass(device_t dev) { struct imx6_anatop_softc *sc; const int cpu_init_pass = BUS_PASS_CPU + BUS_PASS_ORDER_MIDDLE; /* * We attach during BUS_PASS_BUS (because some day we will be a * simplebus that has regulator devices as children), but some of our * init work cannot be done until BUS_PASS_CPU (we rely on other devices * that attach on the CPU pass). */ sc = device_get_softc(dev); if (!sc->cpu_init_done && bus_current_pass >= cpu_init_pass) { sc->cpu_init_done = true; cpufreq_initialize(sc); initialize_tempmon(sc); if (bootverbose) { device_printf(sc->dev, "CPU %uMHz @ %umV\n", sc->cpu_curmhz, sc->cpu_curmv); } } bus_generic_new_pass(dev); } static int imx6_anatop_detach(device_t dev) { /* This device can never detach. */ return (EBUSY); } static int imx6_anatop_attach(device_t dev) { struct imx6_anatop_softc *sc; int err; sc = device_get_softc(dev); sc->dev = dev; /* Allocate bus_space resources. */ if (bus_alloc_resources(dev, imx6_anatop_spec, sc->res)) { device_printf(dev, "Cannot allocate resources\n"); err = ENXIO; goto out; } sc->intr_setup_hook.ich_func = intr_setup; sc->intr_setup_hook.ich_arg = sc; config_intrhook_establish(&sc->intr_setup_hook); SYSCTL_ADD_UINT(device_get_sysctl_ctx(sc->dev), SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "cpu_voltage", CTLFLAG_RD, &sc->cpu_curmv, 0, "Current CPU voltage in millivolts"); imx6_anatop_sc = sc; /* * Other code seen on the net sets this SELFBIASOFF flag around the same * time the temperature sensor is set up, although it's unclear how the * two are related (if at all). */ imx6_anatop_write_4(IMX6_ANALOG_PMU_MISC0_SET, IMX6_ANALOG_PMU_MISC0_SELFBIASOFF); /* * Some day, when we're ready to deal with the actual anatop regulators * that are described in fdt data as children of this "bus", this would * be the place to invoke a simplebus helper routine to instantiate the * children from the fdt data. */ err = 0; out: if (err != 0) { bus_release_resources(dev, imx6_anatop_spec, sc->res); } return (err); } +uint32_t +pll4_configure_output(uint32_t mfi, uint32_t mfn, uint32_t mfd) +{ + int reg; + + /* + * Audio PLL (PLL4). + * PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM) + */ + + reg = (IMX6_ANALOG_CCM_PLL_AUDIO_ENABLE); + reg &= ~(IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_MASK << \ + IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT); + reg |= (mfi << IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT); + imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO, reg); + imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_NUM, mfn); + imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_DENOM, mfd); + + return (0); +} + static int imx6_anatop_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "fsl,imx6q-anatop") == 0) return (ENXIO); device_set_desc(dev, "Freescale i.MX6 Analog PLLs and Power"); return (BUS_PROBE_DEFAULT); } uint32_t imx6_get_cpu_clock() { uint32_t div; div = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) & IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK; return (cpufreq_mhz_from_div(imx6_anatop_sc, div)); } static device_method_t imx6_anatop_methods[] = { /* Device interface */ DEVMETHOD(device_probe, imx6_anatop_probe), DEVMETHOD(device_attach, imx6_anatop_attach), DEVMETHOD(device_detach, imx6_anatop_detach), /* Bus interface */ DEVMETHOD(bus_new_pass, imx6_anatop_new_pass), DEVMETHOD_END }; static driver_t imx6_anatop_driver = { "imx6_anatop", imx6_anatop_methods, sizeof(struct imx6_anatop_softc) }; static devclass_t imx6_anatop_devclass; EARLY_DRIVER_MODULE(imx6_anatop, simplebus, imx6_anatop_driver, imx6_anatop_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); EARLY_DRIVER_MODULE(imx6_anatop, ofwbus, imx6_anatop_driver, imx6_anatop_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Index: stable/10/sys/arm/freescale/imx/imx6_anatopreg.h =================================================================== --- stable/10/sys/arm/freescale/imx/imx6_anatopreg.h (revision 283499) +++ stable/10/sys/arm/freescale/imx/imx6_anatopreg.h (revision 283500) @@ -1,188 +1,191 @@ /*- * Copyright (c) 2013 Ian Lepore * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef IMX6_ANATOPREG_H #define IMX6_ANATOPREG_H #define IMX6_ANALOG_CCM_PLL_ARM 0x000 #define IMX6_ANALOG_CCM_PLL_ARM_SET 0x004 #define IMX6_ANALOG_CCM_PLL_ARM_CLR 0x008 #define IMX6_ANALOG_CCM_PLL_ARM_TOG 0x00C #define IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK 0x7F #define IMX6_ANALOG_CCM_PLL_ARM_LOCK (1U << 31) #define IMX6_ANALOG_CCM_PLL_ARM_BYPASS (1 << 16) #define IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK (0x03 << 16) #define IMX6_ANALOG_CCM_PLL_USB1 0x010 #define IMX6_ANALOG_CCM_PLL_USB1_SET 0x014 #define IMX6_ANALOG_CCM_PLL_USB1_CLR 0x018 #define IMX6_ANALOG_CCM_PLL_USB1_TOG 0x01C #define IMX6_ANALOG_CCM_PLL_USB_LOCK (1U << 31) #define IMX6_ANALOG_CCM_PLL_USB_BYPASS (1 << 16) #define IMX6_ANALOG_CCM_PLL_USB_ENABLE (1 << 13) #define IMX6_ANALOG_CCM_PLL_USB_POWER (1 << 12) #define IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS (1 << 6) #define IMX6_ANALOG_CCM_PLL_USB2 0x020 #define IMX6_ANALOG_CCM_PLL_USB2_SET 0x024 #define IMX6_ANALOG_CCM_PLL_USB2_CLR 0x028 #define IMX6_ANALOG_CCM_PLL_USB2_TOG 0x02C #define IMX6_ANALOG_CCM_PLL_SYS 0x030 #define IMX6_ANALOG_CCM_PLL_SYS_SET 0x034 #define IMX6_ANALOG_CCM_PLL_SYS_CLR 0x038 #define IMX6_ANALOG_CCM_PLL_SYS_TOG 0x03C #define IMX6_ANALOG_CCM_PLL_SYS_SS 0x040 #define IMX6_ANALOG_CCM_PLL_SYS_NUM 0x050 #define IMX6_ANALOG_CCM_PLL_SYS_DENOM 0x060 #define IMX6_ANALOG_CCM_PLL_AUDIO 0x070 +#define IMX6_ANALOG_CCM_PLL_AUDIO_ENABLE (1 << 13) +#define IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT 0 +#define IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_MASK 0x7f #define IMX6_ANALOG_CCM_PLL_AUDIO_SET 0x074 #define IMX6_ANALOG_CCM_PLL_AUDIO_CLR 0x078 #define IMX6_ANALOG_CCM_PLL_AUDIO_TOG 0x07C #define IMX6_ANALOG_CCM_PLL_AUDIO_NUM 0x080 #define IMX6_ANALOG_CCM_PLL_AUDIO_DENOM 0x090 #define IMX6_ANALOG_CCM_PLL_VIDEO 0x0A0 #define IMX6_ANALOG_CCM_PLL_VIDEO_SET 0x0A4 #define IMX6_ANALOG_CCM_PLL_VIDEO_CLR 0x0A8 #define IMX6_ANALOG_CCM_PLL_VIDEO_TOG 0x0AC #define IMX6_ANALOG_CCM_PLL_VIDEO_NUM 0x0B0 #define IMX6_ANALOG_CCM_PLL_VIDEO_DENOM 0x0C0 #define IMX6_ANALOG_CCM_PLL_MLB 0x0D0 #define IMX6_ANALOG_CCM_PLL_MLB_SET 0x0D4 #define IMX6_ANALOG_CCM_PLL_MLB_CLR 0x0D8 #define IMX6_ANALOG_CCM_PLL_MLB_TOG 0x0DC #define IMX6_ANALOG_CCM_PLL_ENET 0x0E0 #define IMX6_ANALOG_CCM_PLL_ENET_SET 0x0E4 #define IMX6_ANALOG_CCM_PLL_ENET_CLR 0x0E8 #define IMX6_ANALOG_CCM_PLL_ENET_TOG 0x0EC #define IMX6_ANALOG_CCM_PFD_480 0x0F0 #define IMX6_ANALOG_CCM_PFD_480_SET 0x0F4 #define IMX6_ANALOG_CCM_PFD_480_CLR 0x0F8 #define IMX6_ANALOG_CCM_PFD_480_TOG 0x0FC #define IMX6_ANALOG_CCM_PFD_528 0x100 #define IMX6_ANALOG_CCM_PFD_528_SET 0x104 #define IMX6_ANALOG_CCM_PFD_528_CLR 0x108 #define IMX6_ANALOG_CCM_PFD_528_TOG 0x10C #define IMX6_ANALOG_PMU_REG_CORE 0x140 #define IMX6_ANALOG_PMU_REG2_TARG_SHIFT 18 #define IMX6_ANALOG_PMU_REG2_TARG_MASK \ (0x1f << IMX6_ANALOG_PMU_REG2_TARG_SHIFT) #define IMX6_ANALOG_PMU_REG1_TARG_SHIFT 9 #define IMX6_ANALOG_PMU_REG1_TARG_MASK \ (0x1f << IMX6_ANALOG_PMU_REG1_TARG_SHIFT) #define IMX6_ANALOG_PMU_REG0_TARG_SHIFT 0 #define IMX6_ANALOG_PMU_REG0_TARG_MASK \ (0x1f << IMX6_ANALOG_PMU_REG0_TARG_SHIFT) #define IMX6_ANALOG_PMU_MISC0 0x150 #define IMX6_ANALOG_PMU_MISC0_SET 0x154 #define IMX6_ANALOG_PMU_MISC0_CLR 0x158 #define IMX6_ANALOG_PMU_MISC0_TOG 0x15C #define IMX6_ANALOG_PMU_MISC0_SELFBIASOFF (1 << 3) #define IMX6_ANALOG_PMU_MISC1 0x160 #define IMX6_ANALOG_PMU_MISC1_SET 0x164 #define IMX6_ANALOG_PMU_MISC1_CLR 0x168 #define IMX6_ANALOG_PMU_MISC1_TOG 0x16C #define IMX6_ANALOG_PMU_MISC1_IRQ_TEMPSENSE (1 << 29) #define IMX6_ANALOG_PMU_MISC2 0x170 #define IMX6_ANALOG_PMU_MISC2_SET 0x174 #define IMX6_ANALOG_PMU_MISC2_CLR 0x178 #define IMX6_ANALOG_PMU_MISC2_TOG 0x17C /* * Note that the ANALOG_CCM_MISCn registers are the same as the PMU_MISCn * registers; some bits conceptually belong to the PMU and some to the CCM. */ #define IMX6_ANALOG_CCM_MISC0 IMX6_ANALOG_PMU_MISC0 #define IMX6_ANALOG_CCM_MISC0_SET IMX6_ANALOG_PMU_MISC0_SET #define IMX6_ANALOG_CCM_MISC0_CLR IMX6_ANALOG_PMU_MISC0_CLR #define IMX6_ANALOG_CCM_MISC0_TOG IMX6_ANALOG_PMU_MISC0_TOG #define IMX6_ANALOG_CCM_MISC2 IMX6_ANALOG_PMU_MISC2 #define IMX6_ANALOG_CCM_MISC2_SET IMX6_ANALOG_PMU_MISC2_SET #define IMX6_ANALOG_CCM_MISC2_CLR IMX6_ANALOG_PMU_MISC2_CLR #define IMX6_ANALOG_CCM_MISC2_TOG IMX6_ANALOG_PMU_MISC2_TOG #define IMX6_ANALOG_TEMPMON_TEMPSENSE0 0x180 #define IMX6_ANALOG_TEMPMON_TEMPSENSE0_SET 0x184 #define IMX6_ANALOG_TEMPMON_TEMPSENSE0_CLR 0x188 #define IMX6_ANALOG_TEMPMON_TEMPSENSE0_TOG 0x18C #define IMX6_ANALOG_TEMPMON_TEMPSENSE0_TOG 0x18C #define IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT 20 #define IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_MASK \ (0xfff << IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT) #define IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT 8 #define IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_MASK \ (0xfff << IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT) #define IMX6_ANALOG_TEMPMON_TEMPSENSE0_VALID 0x4 #define IMX6_ANALOG_TEMPMON_TEMPSENSE0_MEASURE 0x2 #define IMX6_ANALOG_TEMPMON_TEMPSENSE0_POWER_DOWN 0x1 #define IMX6_ANALOG_TEMPMON_TEMPSENSE1 0x190 #define IMX6_ANALOG_TEMPMON_TEMPSENSE1_SET 0x194 #define IMX6_ANALOG_TEMPMON_TEMPSENSE1_CLR 0x198 #define IMX6_ANALOG_TEMPMON_TEMPSENSE1_TOG 0x19C #define IMX6_ANALOG_USB1_VBUS_DETECT 0x1A0 #define IMX6_ANALOG_USB1_VBUS_DETECT_SET 0x1A4 #define IMX6_ANALOG_USB1_VBUS_DETECT_CLR 0x1A8 #define IMX6_ANALOG_USB1_VBUS_DETECT_TOG 0x1AC #define IMX6_ANALOG_USB1_CHRG_DETECT 0x1B0 #define IMX6_ANALOG_USB1_CHRG_DETECT_SET 0x1B4 #define IMX6_ANALOG_USB1_CHRG_DETECT_CLR 0x1B8 #define IMX6_ANALOG_USB1_CHRG_DETECT_TOG 0x1BC #define IMX6_ANALOG_USB_CHRG_DETECT_N_ENABLE (1 << 20) /* EN_B */ #define IMX6_ANALOG_USB_CHRG_DETECT_N_CHK_CHRG (1 << 19) /* CHK_CHRG_B */ #define IMX6_ANALOG_USB_CHRG_DETECT_CHK_CONTACT (1 << 18) #define IMX6_ANALOG_USB1_VBUS_DETECT_STAT 0x1C0 #define IMX6_ANALOG_USB1_CHRG_DETECT_STAT 0x1D0 #define IMX6_ANALOG_USB1_MISC 0x1F0 #define IMX6_ANALOG_USB1_MISC_SET 0x1F4 #define IMX6_ANALOG_USB1_MISC_CLR 0x1F8 #define IMX6_ANALOG_USB1_MISC_TOG 0x1FC #define IMX6_ANALOG_USB2_VBUS_DETECT 0x200 #define IMX6_ANALOG_USB2_VBUS_DETECT_SET 0x204 #define IMX6_ANALOG_USB2_VBUS_DETECT_CLR 0x208 #define IMX6_ANALOG_USB2_VBUS_DETECT_TOG 0x20C #define IMX6_ANALOG_USB2_CHRG_DETECT 0x210 #define IMX6_ANALOG_USB2_CHRG_DETECT_SET 0x214 #define IMX6_ANALOG_USB2_CHRG_DETECT_CLR 0x218 #define IMX6_ANALOG_USB2_CHRG_DETECT_TOG 0x21C #define IMX6_ANALOG_USB2_VBUS_DETECT_STAT 0x220 #define IMX6_ANALOG_USB2_CHRG_DETECT_STAT 0x230 #define IMX6_ANALOG_USB2_MISC 0x250 #define IMX6_ANALOG_USB2_MISC_SET 0x254 #define IMX6_ANALOG_USB2_MISC_CLR 0x258 #define IMX6_ANALOG_USB2_MISC_TOG 0x25C #define IMX6_ANALOG_DIGPROG 0x260 #define IMX6_ANALOG_DIGPROG_SL 0x280 #define IMX6_ANALOG_DIGPROG_SOCTYPE_SHIFT 16 #define IMX6_ANALOG_DIGPROG_SOCTYPE_MASK \ (0xff << IMX6_ANALOG_DIGPROG_SOCTYPE_SHIFT) #endif Index: stable/10/sys/arm/freescale/imx/imx6_anatopvar.h =================================================================== --- stable/10/sys/arm/freescale/imx/imx6_anatopvar.h (revision 283499) +++ stable/10/sys/arm/freescale/imx/imx6_anatopvar.h (revision 283500) @@ -1,45 +1,47 @@ /*- * Copyright (c) 2013 Ian Lepore * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef IMX6_ANATOPVAR_H #define IMX6_ANATOPVAR_H /* * All registers controlling various analog aspects of the SoC (such as PLLs or * voltage regulators or USB VBUS detection) are gathered together under the * anatop device (because of newbus hierarchical resource management), but other * drivers such as CMM or USBPHY need access to these registers. These * functions let them have at the hardware directly. No effort is made by these * functions to mediate concurrent access. */ uint32_t imx6_anatop_read_4(bus_size_t _offset); void imx6_anatop_write_4(bus_size_t _offset, uint32_t _value); uint32_t imx6_get_cpu_clock(void); +uint32_t pll4_configure_output(uint32_t mfi, uint32_t mfn, uint32_t mfd); + #endif Index: stable/10/sys/arm/freescale/imx/imx6_audmux.c =================================================================== --- stable/10/sys/arm/freescale/imx/imx6_audmux.c (nonexistent) +++ stable/10/sys/arm/freescale/imx/imx6_audmux.c (revision 283500) @@ -0,0 +1,159 @@ +/*- + * Copyright (c) 2015 Ruslan Bukin + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * i.MX6 Digital Audio Multiplexer (AUDMUX) + * Chapter 16, i.MX 6Dual/6Quad Applications Processor Reference Manual, + * Rev. 1, 04/2013 + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#define READ4(_sc, _reg) \ + bus_space_read_4(_sc->bst, _sc->bsh, _reg) +#define WRITE4(_sc, _reg, _val) \ + bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val) + +#define AUDMUX_PTCR(n) (0x8 * (n - 1)) /* Port Timing Control Register */ +#define PTCR_TFS_DIR (1 << 31) /* Transmit Frame Sync Direction Control */ +#define PTCR_TFSEL_S 27 /* Transmit Frame Sync Select */ +#define PTCR_TFSEL_M 0xf +#define PTCR_TCLKDIR (1 << 26) /* Transmit Clock Direction Control */ +#define PTCR_TCSEL_S 22 /* Transmit Clock Select. */ +#define PTCR_TCSEL_M 0xf +#define PTCR_RFS_DIR (1 << 21) /* Receive Frame Sync Direction Control */ +#define PTCR_SYN (1 << 11) +#define AUDMUX_PDCR(n) (0x8 * (n - 1) + 0x4) /* Port Data Control Reg */ +#define PDCR_RXDSEL_S 13 /* Receive Data Select */ +#define PDCR_RXDSEL_M 0x3 +#define PDCR_RXDSEL_PORT(n) (n - 1) + +struct audmux_softc { + struct resource *res[1]; + bus_space_tag_t bst; + bus_space_handle_t bsh; + void *ih; +}; + +static struct resource_spec audmux_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { -1, 0 } +}; + +static int +audmux_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_is_compatible(dev, "fsl,imx6q-audmux")) + return (ENXIO); + + device_set_desc(dev, "i.MX6 Digital Audio Multiplexer"); + return (BUS_PROBE_DEFAULT); +} + +static int +audmux_configure(struct audmux_softc *sc, + int ssi_port, int audmux_port) +{ + uint32_t reg; + + /* Direction: output */ + reg = (PTCR_TFS_DIR | PTCR_TCLKDIR | PTCR_SYN); + WRITE4(sc, AUDMUX_PTCR(audmux_port), reg); + + /* Select source */ + reg = (PDCR_RXDSEL_PORT(ssi_port) << PDCR_RXDSEL_S); + WRITE4(sc, AUDMUX_PDCR(audmux_port), reg); + + return (0); +} + +static int +audmux_attach(device_t dev) +{ + struct audmux_softc *sc; + + sc = device_get_softc(dev); + + if (bus_alloc_resources(dev, audmux_spec, sc->res)) { + device_printf(dev, "could not allocate resources\n"); + return (ENXIO); + } + + /* Memory interface */ + sc->bst = rman_get_bustag(sc->res[0]); + sc->bsh = rman_get_bushandle(sc->res[0]); + + /* + * Direct SSI1 output to AUDMUX5 pins. + * TODO: dehardcore this. + */ + audmux_configure(sc, 1, 5); + + return (0); +}; + +static device_method_t audmux_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, audmux_probe), + DEVMETHOD(device_attach, audmux_attach), + { 0, 0 } +}; + +static driver_t audmux_driver = { + "audmux", + audmux_methods, + sizeof(struct audmux_softc), +}; + +static devclass_t audmux_devclass; + +DRIVER_MODULE(audmux, simplebus, audmux_driver, audmux_devclass, 0, 0); Property changes on: stable/10/sys/arm/freescale/imx/imx6_audmux.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/10/sys/arm/freescale/imx/imx6_ccm.c =================================================================== --- stable/10/sys/arm/freescale/imx/imx6_ccm.c (revision 283499) +++ stable/10/sys/arm/freescale/imx/imx6_ccm.c (revision 283500) @@ -1,290 +1,342 @@ /*- * Copyright (c) 2013 Ian Lepore * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * Clocks and power control driver for Freescale i.MX6 family of SoCs. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifndef CCGR_CLK_MODE_ALWAYS #define CCGR_CLK_MODE_OFF 0 #define CCGR_CLK_MODE_RUNMODE 1 #define CCGR_CLK_MODE_ALWAYS 3 #endif struct ccm_softc { device_t dev; struct resource *mem_res; }; static struct ccm_softc *ccm_sc; static inline uint32_t RD4(struct ccm_softc *sc, bus_size_t off) { return (bus_read_4(sc->mem_res, off)); } static inline void WR4(struct ccm_softc *sc, bus_size_t off, uint32_t val) { bus_write_4(sc->mem_res, off, val); } /* * Until we have a fully functional ccm driver which implements the fdt_clock * interface, use the age-old workaround of unconditionally enabling the clocks * for devices we might need to use. The SoC defaults to most clocks enabled, * but the rom boot code and u-boot disable a few of them. We turn on only * what's needed to run the chip plus devices we have drivers for, and turn off * devices we don't yet have drivers for. (Note that USB is not turned on here * because that is one we do when the driver asks for it.) */ static void ccm_init_gates(struct ccm_softc *sc) { /* Turns on... */ WR4(sc, CCM_CCGR0, 0x0000003f); /* ahpbdma, aipstz 1 & 2 busses */ WR4(sc, CCM_CCGR1, 0x00300c00); /* gpt, enet */ WR4(sc, CCM_CCGR2, 0x0fffffc0); /* ipmux & ipsync (bridges), iomux, i2c */ WR4(sc, CCM_CCGR3, 0x3ff00000); /* DDR memory controller */ WR4(sc, CCM_CCGR4, 0x0000f300); /* pl301 bus crossbar */ - WR4(sc, CCM_CCGR5, 0x0f000000); /* uarts */ + WR4(sc, CCM_CCGR5, 0x0ffc00c0); /* uarts, ssi, sdma */ WR4(sc, CCM_CCGR6, 0x000000ff); /* usdhc 1-4 */ } static int ccm_detach(device_t dev) { struct ccm_softc *sc; sc = device_get_softc(dev); if (sc->mem_res != NULL) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); return (0); } static int ccm_attach(device_t dev) { struct ccm_softc *sc; int err, rid; uint32_t reg; sc = device_get_softc(dev); err = 0; /* Allocate bus_space resources. */ rid = 0; sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->mem_res == NULL) { device_printf(dev, "Cannot allocate memory resources\n"); err = ENXIO; goto out; } ccm_sc = sc; /* * Configure the Low Power Mode setting to leave the ARM core power on * when a WFI instruction is executed. This lets the MPCore timers and * GIC continue to run, which is helpful when the only thing that can * wake you up is an MPCore Private Timer interrupt delivered via GIC. * * XXX Based on the docs, setting CCM_CGPR_INT_MEM_CLK_LPM shouldn't be * required when the LPM bits are set to LPM_RUN. But experimentally * I've experienced a fairly rare lockup when not setting it. I was * unable to prove conclusively that the lockup was related to power * management or that this definitively fixes it. Revisit this. */ reg = RD4(sc, CCM_CGPR); reg |= CCM_CGPR_INT_MEM_CLK_LPM; WR4(sc, CCM_CGPR, reg); reg = RD4(sc, CCM_CLPCR); reg = (reg & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM_RUN; WR4(sc, CCM_CLPCR, reg); ccm_init_gates(sc); err = 0; out: if (err != 0) ccm_detach(dev); return (err); } static int ccm_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "fsl,imx6q-ccm") == 0) return (ENXIO); device_set_desc(dev, "Freescale i.MX6 Clock Control Module"); return (BUS_PROBE_DEFAULT); +} + +void +imx_ccm_ssi_configure(device_t _ssidev) +{ + struct ccm_softc *sc; + uint32_t reg; + + sc = ccm_sc; + + /* + * Select PLL4 (Audio PLL) clock multiplexer as source. + * PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). + */ + + reg = RD4(sc, CCM_CSCMR1); + reg &= ~(SSI_CLK_SEL_M << SSI1_CLK_SEL_S); + reg |= (SSI_CLK_SEL_PLL4 << SSI1_CLK_SEL_S); + reg &= ~(SSI_CLK_SEL_M << SSI2_CLK_SEL_S); + reg |= (SSI_CLK_SEL_PLL4 << SSI2_CLK_SEL_S); + reg &= ~(SSI_CLK_SEL_M << SSI3_CLK_SEL_S); + reg |= (SSI_CLK_SEL_PLL4 << SSI3_CLK_SEL_S); + WR4(sc, CCM_CSCMR1, reg); + + /* + * Ensure we have set hardware-default values + * for pre and post dividers. + */ + + /* SSI1 and SSI3 */ + reg = RD4(sc, CCM_CS1CDR); + /* Divide by 2 */ + reg &= ~(SSI_CLK_PODF_MASK << SSI1_CLK_PODF_SHIFT); + reg &= ~(SSI_CLK_PODF_MASK << SSI3_CLK_PODF_SHIFT); + reg |= (0x1 << SSI1_CLK_PODF_SHIFT); + reg |= (0x1 << SSI3_CLK_PODF_SHIFT); + /* Divide by 4 */ + reg &= ~(SSI_CLK_PRED_MASK << SSI1_CLK_PRED_SHIFT); + reg &= ~(SSI_CLK_PRED_MASK << SSI3_CLK_PRED_SHIFT); + reg |= (0x3 << SSI1_CLK_PRED_SHIFT); + reg |= (0x3 << SSI3_CLK_PRED_SHIFT); + WR4(sc, CCM_CS1CDR, reg); + + /* SSI2 */ + reg = RD4(sc, CCM_CS2CDR); + /* Divide by 2 */ + reg &= ~(SSI_CLK_PODF_MASK << SSI2_CLK_PODF_SHIFT); + reg |= (0x1 << SSI2_CLK_PODF_SHIFT); + /* Divide by 4 */ + reg &= ~(SSI_CLK_PRED_MASK << SSI2_CLK_PRED_SHIFT); + reg |= (0x3 << SSI2_CLK_PRED_SHIFT); + WR4(sc, CCM_CS2CDR, reg); } void imx_ccm_usb_enable(device_t _usbdev) { /* * For imx6, the USBOH3 clock gate is bits 0-1 of CCGR6, so no need for * shifting and masking here, just set the low-order two bits to ALWAYS. */ WR4(ccm_sc, CCM_CCGR6, RD4(ccm_sc, CCM_CCGR6) | CCGR_CLK_MODE_ALWAYS); } void imx_ccm_usbphy_enable(device_t _phydev) { /* * XXX Which unit? * Right now it's not clear how to figure from fdt data which phy unit * we're supposed to operate on. Until this is worked out, just enable * both PHYs. */ #if 0 int phy_num, regoff; phy_num = 0; /* XXX */ switch (phy_num) { case 0: regoff = 0; break; case 1: regoff = 0x10; break; default: device_printf(ccm_sc->dev, "Bad PHY number %u,\n", phy_num); return; } imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + regoff, IMX6_ANALOG_CCM_PLL_USB_ENABLE | IMX6_ANALOG_CCM_PLL_USB_POWER | IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS); #else imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0, IMX6_ANALOG_CCM_PLL_USB_ENABLE | IMX6_ANALOG_CCM_PLL_USB_POWER | IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS); imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0x10, IMX6_ANALOG_CCM_PLL_USB_ENABLE | IMX6_ANALOG_CCM_PLL_USB_POWER | IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS); #endif } uint32_t imx_ccm_ipg_hz(void) { return (66000000); } uint32_t imx_ccm_perclk_hz(void) { return (66000000); } uint32_t imx_ccm_sdhci_hz(void) { return (200000000); } uint32_t imx_ccm_uart_hz(void) { return (80000000); } uint32_t imx_ccm_ahb_hz(void) { return (132000000); } static device_method_t ccm_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ccm_probe), DEVMETHOD(device_attach, ccm_attach), DEVMETHOD(device_detach, ccm_detach), DEVMETHOD_END }; static driver_t ccm_driver = { "ccm", ccm_methods, sizeof(struct ccm_softc) }; static devclass_t ccm_devclass; EARLY_DRIVER_MODULE(ccm, simplebus, ccm_driver, ccm_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY); Index: stable/10/sys/arm/freescale/imx/imx6_ccmreg.h =================================================================== --- stable/10/sys/arm/freescale/imx/imx6_ccmreg.h (revision 283499) +++ stable/10/sys/arm/freescale/imx/imx6_ccmreg.h (revision 283500) @@ -1,49 +1,69 @@ /*- * Copyright (c) 2013 Ian Lepore * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef IMX6_CCMREG_H #define IMX6_CCMREG_H +#define CCM_CSCMR1 0x01C +#define SSI1_CLK_SEL_S 10 +#define SSI2_CLK_SEL_S 12 +#define SSI3_CLK_SEL_S 14 +#define SSI_CLK_SEL_M 0x3 +#define SSI_CLK_SEL_508_PFD 0 +#define SSI_CLK_SEL_454_PFD 1 +#define SSI_CLK_SEL_PLL4 2 +#define CCM_CSCMR2 0x020 +#define CCM_CS1CDR 0x028 +#define SSI1_CLK_PODF_SHIFT 0 +#define SSI1_CLK_PRED_SHIFT 6 +#define SSI3_CLK_PODF_SHIFT 16 +#define SSI3_CLK_PRED_SHIFT 22 +#define SSI_CLK_PODF_MASK 0x3f +#define SSI_CLK_PRED_MASK 0x7 +#define CCM_CS2CDR 0x02C +#define SSI2_CLK_PODF_SHIFT 0 +#define SSI2_CLK_PRED_SHIFT 6 +#define CCM_CSCDR2 0x038 #define CCM_CLPCR 0x054 #define CCM_CLPCR_LPM_MASK 0x03 #define CCM_CLPCR_LPM_RUN 0x00 #define CCM_CLPCR_LPM_WAIT 0x01 #define CCM_CLPCR_LPM_STOP 0x02 #define CCM_CGPR 0x064 #define CCM_CGPR_INT_MEM_CLK_LPM (1 << 17) #define CCM_CCGR0 0x068 #define CCM_CCGR1 0x06C #define CCM_CCGR2 0x070 #define CCM_CCGR3 0x074 #define CCM_CCGR4 0x078 #define CCM_CCGR5 0x07C #define CCM_CCGR6 0x080 #define CCM_CMEOR 0x088 #endif Index: stable/10/sys/arm/freescale/imx/imx6_sdma.c =================================================================== --- stable/10/sys/arm/freescale/imx/imx6_sdma.c (nonexistent) +++ stable/10/sys/arm/freescale/imx/imx6_sdma.c (revision 283500) @@ -0,0 +1,518 @@ +/*- + * Copyright (c) 2015 Ruslan Bukin + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * i.MX6 Smart Direct Memory Access Controller (sDMA) + * Chapter 41, i.MX 6Dual/6Quad Applications Processor Reference Manual, + * Rev. 1, 04/2013 + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#define MAX_BD (PAGE_SIZE / sizeof(struct sdma_buffer_descriptor)) + +#define READ4(_sc, _reg) \ + bus_space_read_4(_sc->bst, _sc->bsh, _reg) +#define WRITE4(_sc, _reg, _val) \ + bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val) + +struct sdma_softc *sdma_sc; + +static struct resource_spec sdma_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { SYS_RES_IRQ, 0, RF_ACTIVE }, + { -1, 0 } +}; + +static void +sdma_intr(void *arg) +{ + struct sdma_buffer_descriptor *bd; + struct sdma_channel *channel; + struct sdma_conf *conf; + struct sdma_softc *sc; + int pending; + int i; + int j; + + sc = arg; + + pending = READ4(sc, SDMAARM_INTR); + + /* Ack intr */ + WRITE4(sc, SDMAARM_INTR, pending); + + for (i = 0; i < SDMA_N_CHANNELS; i++) { + if ((pending & (1 << i)) == 0) + continue; + channel = &sc->channel[i]; + conf = channel->conf; + if (!conf) + continue; + for (j = 0; j < conf->num_bd; j++) { + bd = &channel->bd[j]; + bd->mode.status |= BD_DONE; + if (bd->mode.status & BD_RROR) + printf("sDMA error\n"); + } + + conf->ih(conf->ih_user, 1); + + WRITE4(sc, SDMAARM_HSTART, (1 << i)); + } +} + +static int +sdma_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_is_compatible(dev, "fsl,imx6q-sdma")) + return (ENXIO); + + device_set_desc(dev, "i.MX6 Smart Direct Memory Access Controller"); + return (BUS_PROBE_DEFAULT); +} + +int +sdma_start(int chn) +{ + struct sdma_softc *sc; + + sc = sdma_sc; + + WRITE4(sc, SDMAARM_HSTART, (1 << chn)); + + return (0); +} + +int +sdma_stop(int chn) +{ + struct sdma_softc *sc; + + sc = sdma_sc; + + WRITE4(sc, SDMAARM_STOP_STAT, (1 << chn)); + + return (0); +} + +int +sdma_alloc(void) +{ + struct sdma_channel *channel; + struct sdma_softc *sc; + int found; + int chn; + int i; + + sc = sdma_sc; + found = 0; + + /* Channel 0 can't be used */ + for (i = 1; i < SDMA_N_CHANNELS; i++) { + channel = &sc->channel[i]; + if (channel->in_use == 0) { + channel->in_use = 1; + found = 1; + break; + } + } + + if (!found) + return (-1); + + chn = i; + + /* Allocate area for buffer descriptors */ + channel->bd = (void *)kmem_alloc_contig(kernel_arena, + PAGE_SIZE, M_ZERO, 0, ~0, PAGE_SIZE, 0, + VM_MEMATTR_UNCACHEABLE); + + return (chn); +} + +int +sdma_free(int chn) +{ + struct sdma_channel *channel; + struct sdma_softc *sc; + + sc = sdma_sc; + + channel = &sc->channel[chn]; + channel->in_use = 0; + + kmem_free(kernel_arena, (vm_offset_t)channel->bd, + PAGE_SIZE); + + return (0); +} + +static int +sdma_overrides(struct sdma_softc *sc, int chn, + int evt, int host, int dsp) +{ + int reg; + + /* Ignore sDMA requests */ + reg = READ4(sc, SDMAARM_EVTOVR); + if (evt) + reg |= (1 << chn); + else + reg &= ~(1 << chn); + WRITE4(sc, SDMAARM_EVTOVR, reg); + + /* Ignore enable bit (HE) */ + reg = READ4(sc, SDMAARM_HOSTOVR); + if (host) + reg |= (1 << chn); + else + reg &= ~(1 << chn); + WRITE4(sc, SDMAARM_HOSTOVR, reg); + + /* Prevent sDMA channel from starting */ + reg = READ4(sc, SDMAARM_DSPOVR); + if (!dsp) + reg |= (1 << chn); + else + reg &= ~(1 << chn); + WRITE4(sc, SDMAARM_DSPOVR, reg); + + return (0); +} + +int +sdma_configure(int chn, struct sdma_conf *conf) +{ + struct sdma_buffer_descriptor *bd0; + struct sdma_buffer_descriptor *bd; + struct sdma_context_data *context; + struct sdma_channel *channel; + struct sdma_softc *sc; +#if 0 + int timeout; + int ret; +#endif + int i; + + sc = sdma_sc; + + channel = &sc->channel[chn]; + channel->conf = conf; + + /* Ensure operation has stopped */ + sdma_stop(chn); + + /* Set priority and enable the channel */ + WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1); + WRITE4(sc, SDMAARM_CHNENBL(conf->event), (1 << chn)); + + sdma_overrides(sc, chn, 0, 0, 0); + + if (conf->num_bd > MAX_BD) { + device_printf(sc->dev, "Error: too much buffer" + " descriptors requested\n"); + return (-1); + } + + for (i = 0; i < conf->num_bd; i++) { + bd = &channel->bd[i]; + bd->mode.command = conf->command; + bd->mode.status = BD_DONE | BD_EXTD | BD_CONT | BD_INTR; + if (i == (conf->num_bd - 1)) + bd->mode.status |= BD_WRAP; + bd->mode.count = conf->period; + bd->buffer_addr = conf->saddr + (conf->period * i); + bd->ext_buffer_addr = 0; + } + + sc->ccb[chn].base_bd_ptr = vtophys(channel->bd); + sc->ccb[chn].current_bd_ptr = vtophys(channel->bd); + + /* + * Load context. + * + * i.MX6 Reference Manual: Appendix A SDMA Scripts + * A.3.1.7.1 (mcu_2_app) + */ + + /* + * TODO: allow using other scripts + */ + context = sc->context; + memset(context, 0, sizeof(*context)); + context->channel_state.pc = sc->fw_scripts->mcu_2_app_addr; + + /* + * Tx FIFO 0 address (r6) + * Event_mask (r1) + * Event2_mask (r0) + * Watermark level (r7) + */ + + if (conf->event > 32) { + context->gReg[0] = (1 << (conf->event % 32)); + context->gReg[1] = 0; + } else { + context->gReg[0] = 0; + context->gReg[1] = (1 << conf->event); + } + + context->gReg[6] = conf->daddr; + context->gReg[7] = conf->word_length; + + bd0 = sc->bd0; + bd0->mode.command = C0_SETDM; + bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; + bd0->mode.count = sizeof(*context) / 4; + bd0->buffer_addr = sc->context_phys; + bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * chn; + + WRITE4(sc, SDMAARM_HSTART, 1); + +#if 0 + /* Debug purposes */ + + timeout = 1000; + while (!(ret = READ4(sc, SDMAARM_INTR) & 1)) { + if (timeout-- <= 0) + break; + DELAY(10); + }; + + if (!ret) { + device_printf(sc->dev, "Failed to load context.\n"); + return (-1); + } + + WRITE4(sc, SDMAARM_INTR, ret); + + device_printf(sc->dev, "Context loaded successfully.\n"); +#endif + + return (0); +} + +static int +load_firmware(struct sdma_softc *sc) +{ + struct sdma_firmware_header *header; + const struct firmware *fp; + + fp = firmware_get("sdma_fw"); + if (fp == NULL) { + device_printf(sc->dev, "Can't get firmware.\n"); + return (-1); + } + + header = (struct sdma_firmware_header *)fp->data; + if (header->magic != FW_HEADER_MAGIC) { + device_printf(sc->dev, "Can't use firmware.\n"); + return (-1); + } + + sc->fw_header = header; + sc->fw_scripts = (void *)((char *)header + + header->script_addrs_start); + + return (0); +} + +static int +boot_firmware(struct sdma_softc *sc) +{ + struct sdma_buffer_descriptor *bd0; + uint32_t *ram_code; + int timeout; + int ret; + int chn; + int sz; + int i; + + ram_code = (void *)((char *)sc->fw_header + + sc->fw_header->ram_code_start); + + /* Make sure SDMA has not started yet */ + WRITE4(sc, SDMAARM_MC0PTR, 0); + + sz = SDMA_N_CHANNELS * sizeof(struct sdma_channel_control) + \ + sizeof(struct sdma_context_data); + sc->ccb = (void *)kmem_alloc_contig(kernel_arena, + sz, M_ZERO, 0, ~0, PAGE_SIZE, 0, VM_MEMATTR_UNCACHEABLE); + sc->ccb_phys = vtophys(sc->ccb); + + sc->context = (void *)((char *)sc->ccb + \ + SDMA_N_CHANNELS * sizeof(struct sdma_channel_control)); + sc->context_phys = vtophys(sc->context); + + /* Disable all the channels */ + for (i = 0; i < SDMA_N_EVENTS; i++) + WRITE4(sc, SDMAARM_CHNENBL(i), 0); + + /* All channels have priority 0 */ + for (i = 0; i < SDMA_N_CHANNELS; i++) + WRITE4(sc, SDMAARM_SDMA_CHNPRI(i), 0); + + /* Channel 0 is used for booting firmware */ + chn = 0; + + sc->bd0 = (void *)kmem_alloc_contig(kernel_arena, + PAGE_SIZE, M_ZERO, 0, ~0, PAGE_SIZE, 0, + VM_MEMATTR_UNCACHEABLE); + bd0 = sc->bd0; + sc->ccb[chn].base_bd_ptr = vtophys(bd0); + sc->ccb[chn].current_bd_ptr = vtophys(bd0); + + WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1); + + sdma_overrides(sc, chn, 1, 0, 0); + + /* XXX: not sure what is that */ + WRITE4(sc, SDMAARM_CHN0ADDR, 0x4050); + + WRITE4(sc, SDMAARM_CONFIG, 0); + WRITE4(sc, SDMAARM_MC0PTR, sc->ccb_phys); + WRITE4(sc, SDMAARM_CONFIG, CONFIG_CSM); + WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1); + + bd0->mode.command = C0_SETPM; + bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; + bd0->mode.count = sc->fw_header->ram_code_size / 2; + bd0->buffer_addr = vtophys(ram_code); + bd0->ext_buffer_addr = sc->fw_scripts->ram_code_start_addr; + + WRITE4(sc, SDMAARM_HSTART, 1); + + timeout = 100; + while (!(ret = READ4(sc, SDMAARM_INTR) & 1)) { + if (timeout-- <= 0) + break; + DELAY(10); + }; + + if (ret == 0) { + device_printf(sc->dev, "SDMA failed to boot\n"); + return (-1); + } + + WRITE4(sc, SDMAARM_INTR, ret); + +#if 0 + device_printf(sc->dev, "SDMA booted successfully.\n"); +#endif + + /* Debug is disabled */ + WRITE4(sc, SDMAARM_ONCE_ENB, 0); + + return (0); +} + +static int +sdma_attach(device_t dev) +{ + struct sdma_softc *sc; + int err; + + sc = device_get_softc(dev); + sc->dev = dev; + + if (bus_alloc_resources(dev, sdma_spec, sc->res)) { + device_printf(dev, "could not allocate resources\n"); + return (ENXIO); + } + + /* Memory interface */ + sc->bst = rman_get_bustag(sc->res[0]); + sc->bsh = rman_get_bushandle(sc->res[0]); + + sdma_sc = sc; + + /* Setup interrupt handler */ + err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE, + NULL, sdma_intr, sc, &sc->ih); + if (err) { + device_printf(dev, "Unable to alloc interrupt resource.\n"); + return (ENXIO); + } + + if (load_firmware(sc) == -1) + return (ENXIO); + + if (boot_firmware(sc) == -1) + return (ENXIO); + + return (0); +}; + +static device_method_t sdma_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, sdma_probe), + DEVMETHOD(device_attach, sdma_attach), + { 0, 0 } +}; + +static driver_t sdma_driver = { + "sdma", + sdma_methods, + sizeof(struct sdma_softc), +}; + +static devclass_t sdma_devclass; + +DRIVER_MODULE(sdma, simplebus, sdma_driver, sdma_devclass, 0, 0); Property changes on: stable/10/sys/arm/freescale/imx/imx6_sdma.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/10/sys/arm/freescale/imx/imx6_sdma.h =================================================================== --- stable/10/sys/arm/freescale/imx/imx6_sdma.h (nonexistent) +++ stable/10/sys/arm/freescale/imx/imx6_sdma.h (revision 283500) @@ -0,0 +1,245 @@ +/*- + * Copyright (c) 2015 Ruslan Bukin + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#define SDMAARM_MC0PTR 0x00 /* ARM platform Channel 0 Pointer */ +#define SDMAARM_INTR 0x04 /* Channel Interrupts */ +#define SDMAARM_STOP_STAT 0x08 /* Channel Stop/Channel Status */ +#define SDMAARM_HSTART 0x0C /* Channel Start */ +#define SDMAARM_EVTOVR 0x10 /* Channel Event Override */ +#define SDMAARM_DSPOVR 0x14 /* Channel BP Override */ +#define SDMAARM_HOSTOVR 0x18 /* Channel ARM platform Override */ +#define SDMAARM_EVTPEND 0x1C /* Channel Event Pending */ +#define SDMAARM_RESET 0x24 /* Reset Register */ +#define SDMAARM_EVTERR 0x28 /* DMA Request Error Register */ +#define SDMAARM_INTRMASK 0x2C /* Channel ARM platform Interrupt Mask */ +#define SDMAARM_PSW 0x30 /* Schedule Status */ +#define SDMAARM_EVTERRDBG 0x34 /* DMA Request Error Register */ +#define SDMAARM_CONFIG 0x38 /* Configuration Register */ +#define CONFIG_CSM 0x3 +#define SDMAARM_SDMA_LOCK 0x3C /* SDMA LOCK */ +#define SDMAARM_ONCE_ENB 0x40 /* OnCE Enable */ +#define SDMAARM_ONCE_DATA 0x44 /* OnCE Data Register */ +#define SDMAARM_ONCE_INSTR 0x48 /* OnCE Instruction Register */ +#define SDMAARM_ONCE_STAT 0x4C /* OnCE Status Register */ +#define SDMAARM_ONCE_CMD 0x50 /* OnCE Command Register */ +#define SDMAARM_ILLINSTADDR 0x58 /* Illegal Instruction Trap Address */ +#define SDMAARM_CHN0ADDR 0x5C /* Channel 0 Boot Address */ +#define SDMAARM_EVT_MIRROR 0x60 /* DMA Requests */ +#define SDMAARM_EVT_MIRROR2 0x64 /* DMA Requests 2 */ +#define SDMAARM_XTRIG_CONF1 0x70 /* Cross-Trigger Events Configuration Register 1 */ +#define SDMAARM_XTRIG_CONF2 0x74 /* Cross-Trigger Events Configuration Register 2 */ +#define SDMAARM_SDMA_CHNPRI(n) (0x100 + 0x4 * n) /* Channel Priority Registers */ +#define SDMAARM_CHNENBL(n) (0x200 + 0x4 * n) /* Channel Enable RAM */ + +/* SDMA Event Mappings */ +#define SSI1_RX_1 35 +#define SSI1_TX_1 36 +#define SSI1_RX_0 37 +#define SSI1_TX_0 38 +#define SSI2_RX_1 39 +#define SSI2_TX_1 40 +#define SSI2_RX_0 41 +#define SSI2_TX_0 42 +#define SSI3_RX_1 43 +#define SSI3_TX_1 44 +#define SSI3_RX_0 45 +#define SSI3_TX_0 46 + +#define C0_ADDR 0x01 +#define C0_LOAD 0x02 +#define C0_DUMP 0x03 +#define C0_SETCTX 0x07 +#define C0_GETCTX 0x03 +#define C0_SETDM 0x01 +#define C0_SETPM 0x04 +#define C0_GETDM 0x02 +#define C0_GETPM 0x08 + +#define BD_DONE 0x01 +#define BD_WRAP 0x02 +#define BD_CONT 0x04 +#define BD_INTR 0x08 +#define BD_RROR 0x10 +#define BD_LAST 0x20 +#define BD_EXTD 0x80 + +/* sDMA data transfer length */ +#define CMD_4BYTES 0 +#define CMD_3BYTES 3 +#define CMD_2BYTES 2 +#define CMD_1BYTES 1 + +struct sdma_firmware_header { + uint32_t magic; + uint32_t version_major; + uint32_t version_minor; + uint32_t script_addrs_start; + uint32_t num_script_addrs; + uint32_t ram_code_start; + uint32_t ram_code_size; +}; + +struct sdma_mode_count { + uint16_t count; + uint8_t status; + uint8_t command; +}; + +struct sdma_buffer_descriptor { + struct sdma_mode_count mode; + uint32_t buffer_addr; + uint32_t ext_buffer_addr; +} __packed; + +struct sdma_channel_control { + uint32_t current_bd_ptr; + uint32_t base_bd_ptr; + uint32_t unused[2]; +} __packed; + +struct sdma_state_registers { + uint32_t pc :14; + uint32_t unused1: 1; + uint32_t t : 1; + uint32_t rpc :14; + uint32_t unused0: 1; + uint32_t sf : 1; + uint32_t spc :14; + uint32_t unused2: 1; + uint32_t df : 1; + uint32_t epc :14; + uint32_t lm : 2; +} __packed; + +struct sdma_context_data { + struct sdma_state_registers channel_state; + uint32_t gReg[8]; + uint32_t mda; + uint32_t msa; + uint32_t ms; + uint32_t md; + uint32_t pda; + uint32_t psa; + uint32_t ps; + uint32_t pd; + uint32_t ca; + uint32_t cs; + uint32_t dda; + uint32_t dsa; + uint32_t ds; + uint32_t dd; + uint32_t unused[8]; +} __packed; + +/* SDMA firmware script pointers */ +struct sdma_script_start_addrs { + int32_t ap_2_ap_addr; + int32_t ap_2_bp_addr; + int32_t ap_2_ap_fixed_addr; + int32_t bp_2_ap_addr; + int32_t loopback_on_dsp_side_addr; + int32_t mcu_interrupt_only_addr; + int32_t firi_2_per_addr; + int32_t firi_2_mcu_addr; + int32_t per_2_firi_addr; + int32_t mcu_2_firi_addr; + int32_t uart_2_per_addr; + int32_t uart_2_mcu_addr; + int32_t per_2_app_addr; + int32_t mcu_2_app_addr; + int32_t per_2_per_addr; + int32_t uartsh_2_per_addr; + int32_t uartsh_2_mcu_addr; + int32_t per_2_shp_addr; + int32_t mcu_2_shp_addr; + int32_t ata_2_mcu_addr; + int32_t mcu_2_ata_addr; + int32_t app_2_per_addr; + int32_t app_2_mcu_addr; + int32_t shp_2_per_addr; + int32_t shp_2_mcu_addr; + int32_t mshc_2_mcu_addr; + int32_t mcu_2_mshc_addr; + int32_t spdif_2_mcu_addr; + int32_t mcu_2_spdif_addr; + int32_t asrc_2_mcu_addr; + int32_t ext_mem_2_ipu_addr; + int32_t descrambler_addr; + int32_t dptc_dvfs_addr; + int32_t utra_addr; + int32_t ram_code_start_addr; + int32_t mcu_2_ssish_addr; + int32_t ssish_2_mcu_addr; + int32_t hdmi_dma_addr; +}; + +#define SDMA_N_CHANNELS 32 +#define SDMA_N_EVENTS 48 +#define FW_HEADER_MAGIC 0x414d4453 + +struct sdma_channel { + struct sdma_conf *conf; + struct sdma_buffer_descriptor *bd; + uint8_t in_use; +}; + +struct sdma_softc { + struct resource *res[2]; + bus_space_tag_t bst; + bus_space_handle_t bsh; + device_t dev; + void *ih; + struct sdma_channel_control *ccb; + struct sdma_buffer_descriptor *bd0; + struct sdma_context_data *context; + struct sdma_channel channel[SDMA_N_CHANNELS]; + uint32_t num_bd; + uint32_t ccb_phys; + uint32_t context_phys; + struct sdma_firmware_header *fw_header; + struct sdma_script_start_addrs *fw_scripts; +}; + +struct sdma_conf { + bus_addr_t saddr; + bus_addr_t daddr; + uint32_t word_length; + uint32_t nbits; + uint32_t command; + uint32_t num_bd; + uint32_t event; + uint32_t period; + uint32_t (*ih)(void *, int); + void *ih_user; +}; + +int sdma_configure(int, struct sdma_conf *); +int sdma_start(int); +int sdma_stop(int); +int sdma_alloc(void); +int sdma_free(int); Property changes on: stable/10/sys/arm/freescale/imx/imx6_sdma.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/10/sys/arm/freescale/imx/imx6_ssi.c =================================================================== --- stable/10/sys/arm/freescale/imx/imx6_ssi.c (nonexistent) +++ stable/10/sys/arm/freescale/imx/imx6_ssi.c (revision 283500) @@ -0,0 +1,855 @@ +/*- + * Copyright (c) 2015 Ruslan Bukin + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * i.MX6 Synchronous Serial Interface (SSI) + * + * Chapter 61, i.MX 6Dual/6Quad Applications Processor Reference Manual, + * Rev. 1, 04/2013 + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#define READ4(_sc, _reg) \ + bus_space_read_4(_sc->bst, _sc->bsh, _reg) +#define WRITE4(_sc, _reg, _val) \ + bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val) + +#define SSI_NCHANNELS 1 + +/* i.MX6 SSI registers */ + +#define SSI_STX0 0x00 /* Transmit Data Register n */ +#define SSI_STX1 0x04 /* Transmit Data Register n */ +#define SSI_SRX0 0x08 /* Receive Data Register n */ +#define SSI_SRX1 0x0C /* Receive Data Register n */ +#define SSI_SCR 0x10 /* Control Register */ +#define SCR_I2S_MODE_S 5 /* I2S Mode Select. */ +#define SCR_I2S_MODE_M 0x3 +#define SCR_SYN (1 << 4) +#define SCR_NET (1 << 3) /* Network mode */ +#define SCR_RE (1 << 2) /* Receive Enable. */ +#define SCR_TE (1 << 1) /* Transmit Enable. */ +#define SCR_SSIEN (1 << 0) /* SSI Enable */ +#define SSI_SISR 0x14 /* Interrupt Status Register */ +#define SSI_SIER 0x18 /* Interrupt Enable Register */ +#define SIER_RDMAE (1 << 22) /* Receive DMA Enable. */ +#define SIER_RIE (1 << 21) /* Receive Interrupt Enable. */ +#define SIER_TDMAE (1 << 20) /* Transmit DMA Enable. */ +#define SIER_TIE (1 << 19) /* Transmit Interrupt Enable. */ +#define SIER_TDE0IE (1 << 12) /* Transmit Data Register Empty 0. */ +#define SIER_TUE0IE (1 << 8) /* Transmitter Underrun Error 0. */ +#define SIER_TFE0IE (1 << 0) /* Transmit FIFO Empty 0 IE. */ +#define SSI_STCR 0x1C /* Transmit Configuration Register */ +#define STCR_TXBIT0 (1 << 9) /* Transmit Bit 0 shift MSB/LSB */ +#define STCR_TFEN1 (1 << 8) /* Transmit FIFO Enable 1. */ +#define STCR_TFEN0 (1 << 7) /* Transmit FIFO Enable 0. */ +#define STCR_TFDIR (1 << 6) /* Transmit Frame Direction. */ +#define STCR_TXDIR (1 << 5) /* Transmit Clock Direction. */ +#define STCR_TSHFD (1 << 4) /* Transmit Shift Direction. */ +#define STCR_TSCKP (1 << 3) /* Transmit Clock Polarity. */ +#define STCR_TFSI (1 << 2) /* Transmit Frame Sync Invert. */ +#define STCR_TFSL (1 << 1) /* Transmit Frame Sync Length. */ +#define STCR_TEFS (1 << 0) /* Transmit Early Frame Sync. */ +#define SSI_SRCR 0x20 /* Receive Configuration Register */ +#define SSI_STCCR 0x24 /* Transmit Clock Control Register */ +#define STCCR_DIV2 (1 << 18) /* Divide By 2. */ +#define STCCR_PSR (1 << 17) /* Divide clock by 8. */ +#define WL3_WL0_S 13 +#define WL3_WL0_M 0xf +#define DC4_DC0_S 8 +#define DC4_DC0_M 0x1f +#define PM7_PM0_S 0 +#define PM7_PM0_M 0xff +#define SSI_SRCCR 0x28 /* Receive Clock Control Register */ +#define SSI_SFCSR 0x2C /* FIFO Control/Status Register */ +#define SFCSR_RFWM1_S 20 /* Receive FIFO Empty WaterMark 1 */ +#define SFCSR_RFWM1_M 0xf +#define SFCSR_TFWM1_S 16 /* Transmit FIFO Empty WaterMark 1 */ +#define SFCSR_TFWM1_M 0xf +#define SFCSR_RFWM0_S 4 /* Receive FIFO Empty WaterMark 0 */ +#define SFCSR_RFWM0_M 0xf +#define SFCSR_TFWM0_S 0 /* Transmit FIFO Empty WaterMark 0 */ +#define SFCSR_TFWM0_M 0xf +#define SSI_SACNT 0x38 /* AC97 Control Register */ +#define SSI_SACADD 0x3C /* AC97 Command Address Register */ +#define SSI_SACDAT 0x40 /* AC97 Command Data Register */ +#define SSI_SATAG 0x44 /* AC97 Tag Register */ +#define SSI_STMSK 0x48 /* Transmit Time Slot Mask Register */ +#define SSI_SRMSK 0x4C /* Receive Time Slot Mask Register */ +#define SSI_SACCST 0x50 /* AC97 Channel Status Register */ +#define SSI_SACCEN 0x54 /* AC97 Channel Enable Register */ +#define SSI_SACCDIS 0x58 /* AC97 Channel Disable Register */ + +static MALLOC_DEFINE(M_SSI, "ssi", "ssi audio"); + +uint32_t ssi_dma_intr(void *arg, int chn); + +struct ssi_rate { + uint32_t speed; + uint32_t mfi; /* PLL4 Multiplication Factor Integer */ + uint32_t mfn; /* PLL4 Multiplication Factor Numerator */ + uint32_t mfd; /* PLL4 Multiplication Factor Denominator */ + /* More dividers to configure can be added here */ +}; + +static struct ssi_rate rate_map[] = { + { 192000, 49, 152, 1000 }, /* PLL4 49.152 Mhz */ + /* TODO: add more frequences */ + { 0, 0 }, +}; + +/* + * i.MX6 example bit clock formula + * + * BCLK = 2 channels * 192000 hz * 24 bit = 9216000 hz = + * (24000000 * (49 + 152/1000.0) / 4 / 4 / 2 / 2 / 2 / 1 / 1) + * ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ + * | | | | | | | | | | | + * Fref ------/ | | | | | | | | | | + * PLL4 div select -/ | | | | | | | | | + * PLL4 num --------------/ | | | | | | | | + * PLL4 denom -------------------/ | | | | | | | + * PLL4 post div ---------------------/ | | | | | | + * CCM ssi pre div (CCM_CS1CDR) ----------/ | | | | | + * CCM ssi post div (CCM_CS1CDR) -------------/ | | | | + * SSI PM7_PM0_S ---------------------------------/ | | | + * SSI Fixed divider ---------------------------------/ | | + * SSI DIV2 ----------------------------------------------/ | + * SSI PSR (prescaler /1 or /8) ------------------------------/ + * + * MCLK (Master clock) depends on DAC, usually BCLK * 4 + */ + +struct sc_info { + struct resource *res[2]; + bus_space_tag_t bst; + bus_space_handle_t bsh; + device_t dev; + struct mtx *lock; + void *ih; + int pos; + int dma_size; + bus_dma_tag_t dma_tag; + bus_dmamap_t dma_map; + bus_addr_t buf_base_phys; + uint32_t *buf_base; + struct sdma_conf *conf; + struct ssi_rate *sr; + struct sdma_softc *sdma_sc; + int sdma_ev_rx; + int sdma_ev_tx; + int sdma_channel; +}; + +/* Channel registers */ +struct sc_chinfo { + struct snd_dbuf *buffer; + struct pcm_channel *channel; + struct sc_pcminfo *parent; + + /* Channel information */ + uint32_t dir; + uint32_t format; + + /* Flags */ + uint32_t run; +}; + +/* PCM device private data */ +struct sc_pcminfo { + device_t dev; + uint32_t (*ih)(struct sc_pcminfo *scp); + uint32_t chnum; + struct sc_chinfo chan[SSI_NCHANNELS]; + struct sc_info *sc; +}; + +static struct resource_spec ssi_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { SYS_RES_IRQ, 0, RF_ACTIVE }, + { -1, 0 } +}; + +static int setup_dma(struct sc_pcminfo *scp); +static void setup_ssi(struct sc_info *); +static void ssi_configure_clock(struct sc_info *); + +/* + * Mixer interface. + */ + +static int +ssimixer_init(struct snd_mixer *m) +{ + struct sc_pcminfo *scp; + struct sc_info *sc; + int mask; + + scp = mix_getdevinfo(m); + sc = scp->sc; + + if (sc == NULL) + return -1; + + mask = SOUND_MASK_PCM; + mask |= SOUND_MASK_VOLUME; + + snd_mtxlock(sc->lock); + pcm_setflags(scp->dev, pcm_getflags(scp->dev) | SD_F_SOFTPCMVOL); + mix_setdevs(m, mask); + snd_mtxunlock(sc->lock); + + return (0); +} + +static int +ssimixer_set(struct snd_mixer *m, unsigned dev, + unsigned left, unsigned right) +{ + struct sc_pcminfo *scp; + + scp = mix_getdevinfo(m); + + /* Here we can configure hardware volume on our DAC */ + +#if 1 + device_printf(scp->dev, "ssimixer_set() %d %d\n", + left, right); +#endif + + return (0); +} + +static kobj_method_t ssimixer_methods[] = { + KOBJMETHOD(mixer_init, ssimixer_init), + KOBJMETHOD(mixer_set, ssimixer_set), + KOBJMETHOD_END +}; +MIXER_DECLARE(ssimixer); + + +/* + * Channel interface. + */ + +static void * +ssichan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, + struct pcm_channel *c, int dir) +{ + struct sc_pcminfo *scp; + struct sc_chinfo *ch; + struct sc_info *sc; + + scp = (struct sc_pcminfo *)devinfo; + sc = scp->sc; + + snd_mtxlock(sc->lock); + ch = &scp->chan[0]; + ch->dir = dir; + ch->run = 0; + ch->buffer = b; + ch->channel = c; + ch->parent = scp; + snd_mtxunlock(sc->lock); + + if (sndbuf_setup(ch->buffer, sc->buf_base, sc->dma_size) != 0) { + device_printf(scp->dev, "Can't setup sndbuf.\n"); + return NULL; + } + + return ch; +} + +static int +ssichan_free(kobj_t obj, void *data) +{ + struct sc_chinfo *ch = data; + struct sc_pcminfo *scp = ch->parent; + struct sc_info *sc = scp->sc; + +#if 0 + device_printf(scp->dev, "ssichan_free()\n"); +#endif + + snd_mtxlock(sc->lock); + /* TODO: free channel buffer */ + snd_mtxunlock(sc->lock); + + return (0); +} + +static int +ssichan_setformat(kobj_t obj, void *data, uint32_t format) +{ + struct sc_chinfo *ch = data; + + ch->format = format; + + return (0); +} + +static uint32_t +ssichan_setspeed(kobj_t obj, void *data, uint32_t speed) +{ + struct sc_pcminfo *scp; + struct sc_chinfo *ch; + struct ssi_rate *sr; + struct sc_info *sc; + int threshold; + int i; + + ch = data; + scp = ch->parent; + sc = scp->sc; + + sr = NULL; + + /* First look for equal frequency. */ + for (i = 0; rate_map[i].speed != 0; i++) { + if (rate_map[i].speed == speed) + sr = &rate_map[i]; + } + + /* If no match, just find nearest. */ + if (sr == NULL) { + for (i = 0; rate_map[i].speed != 0; i++) { + sr = &rate_map[i]; + threshold = sr->speed + ((rate_map[i + 1].speed != 0) ? + ((rate_map[i + 1].speed - sr->speed) >> 1) : 0); + if (speed < threshold) + break; + } + } + + sc->sr = sr; + + ssi_configure_clock(sc); + + return (sr->speed); +} + +static void +ssi_configure_clock(struct sc_info *sc) +{ + struct ssi_rate *sr; + + sr = sc->sr; + + pll4_configure_output(sr->mfi, sr->mfn, sr->mfd); + + /* Configure other dividers here, if any */ +} + +static uint32_t +ssichan_setblocksize(kobj_t obj, void *data, uint32_t blocksize) +{ + struct sc_chinfo *ch = data; + struct sc_pcminfo *scp = ch->parent; + struct sc_info *sc = scp->sc; + + sndbuf_resize(ch->buffer, sc->dma_size / blocksize, blocksize); + + setup_dma(scp); + + return (sndbuf_getblksz(ch->buffer)); +} + +uint32_t +ssi_dma_intr(void *arg, int chn) +{ + struct sc_pcminfo *scp; + struct sdma_conf *conf; + struct sc_chinfo *ch; + struct sc_info *sc; + int bufsize; + + scp = arg; + ch = &scp->chan[0]; + sc = scp->sc; + conf = sc->conf; + + bufsize = sndbuf_getsize(ch->buffer); + + sc->pos += conf->period; + if (sc->pos >= bufsize) + sc->pos -= bufsize; + + if (ch->run) + chn_intr(ch->channel); + + return (0); +} + +static int +find_sdma_controller(struct sc_info *sc) +{ + struct sdma_softc *sdma_sc; + phandle_t node, sdma_node; + device_t sdma_dev; + int dts_value[8]; + int len; + + if ((node = ofw_bus_get_node(sc->dev)) == -1) + return (ENXIO); + + if ((len = OF_getproplen(node, "dmas")) <= 0) + return (ENXIO); + + OF_getprop(node, "dmas", &dts_value, len); + + sc->sdma_ev_rx = fdt32_to_cpu(dts_value[1]); + sc->sdma_ev_tx = fdt32_to_cpu(dts_value[5]); + + sdma_node = OF_node_from_xref(fdt32_to_cpu(dts_value[0])); + + sdma_sc = NULL; + + sdma_dev = devclass_get_device(devclass_find("sdma"), 0); + if (sdma_dev) + sdma_sc = device_get_softc(sdma_dev); + + if (sdma_sc == NULL) { + device_printf(sc->dev, "No sDMA found. Can't operate\n"); + return (ENXIO); + }; + + sc->sdma_sc = sdma_sc; + + return (0); +}; + +static int +setup_dma(struct sc_pcminfo *scp) +{ + struct sdma_conf *conf; + struct sc_chinfo *ch; + struct sc_info *sc; + int fmt; + + ch = &scp->chan[0]; + sc = scp->sc; + conf = sc->conf; + + conf->ih = ssi_dma_intr; + conf->ih_user = scp; + conf->saddr = sc->buf_base_phys; + conf->daddr = rman_get_start(sc->res[0]) + SSI_STX0; + conf->event = sc->sdma_ev_tx; /* SDMA TX event */ + conf->period = sndbuf_getblksz(ch->buffer); + conf->num_bd = sndbuf_getblkcnt(ch->buffer); + + /* + * Word Length + * Can be 32, 24, 16 or 8 for sDMA. + * + * SSI supports 24 at max. + */ + + fmt = sndbuf_getfmt(ch->buffer); + + if (fmt & AFMT_16BIT) { + conf->word_length = 16; + conf->command = CMD_2BYTES; + } else if (fmt & AFMT_24BIT) { + conf->word_length = 24; + conf->command = CMD_3BYTES; + } else { + device_printf(sc->dev, "Unknown format\n"); + return (-1); + } + + return (0); +} + +static int +ssi_start(struct sc_pcminfo *scp) +{ + struct sc_info *sc; + int reg; + + sc = scp->sc; + + if (sdma_configure(sc->sdma_channel, sc->conf) != 0) { + device_printf(sc->dev, "Can't configure sDMA\n"); + return (-1); + } + + /* Enable DMA interrupt */ + reg = (SIER_TDMAE); + WRITE4(sc, SSI_SIER, reg); + + sdma_start(sc->sdma_channel); + + return (0); +} + +static int +ssi_stop(struct sc_pcminfo *scp) +{ + struct sc_info *sc; + int reg; + + sc = scp->sc; + + reg = READ4(sc, SSI_SIER); + reg &= ~(SIER_TDMAE); + WRITE4(sc, SSI_SIER, reg); + + sdma_stop(sc->sdma_channel); + + bzero(sc->buf_base, sc->dma_size); + + return (0); +} + +static int +ssichan_trigger(kobj_t obj, void *data, int go) +{ + struct sc_pcminfo *scp; + struct sc_chinfo *ch; + struct sc_info *sc; + + ch = data; + scp = ch->parent; + sc = scp->sc; + + snd_mtxlock(sc->lock); + + switch (go) { + case PCMTRIG_START: +#if 0 + device_printf(scp->dev, "trigger start\n"); +#endif + ch->run = 1; + + ssi_start(scp); + + break; + + case PCMTRIG_STOP: + case PCMTRIG_ABORT: +#if 0 + device_printf(scp->dev, "trigger stop or abort\n"); +#endif + ch->run = 0; + + ssi_stop(scp); + + break; + } + + snd_mtxunlock(sc->lock); + + return (0); +} + +static uint32_t +ssichan_getptr(kobj_t obj, void *data) +{ + struct sc_pcminfo *scp; + struct sc_chinfo *ch; + struct sc_info *sc; + + ch = data; + scp = ch->parent; + sc = scp->sc; + + return (sc->pos); +} + +static uint32_t ssi_pfmt[] = { + SND_FORMAT(AFMT_S24_LE, 2, 0), + 0 +}; + +static struct pcmchan_caps ssi_pcaps = {44100, 192000, ssi_pfmt, 0}; + +static struct pcmchan_caps * +ssichan_getcaps(kobj_t obj, void *data) +{ + + return (&ssi_pcaps); +} + +static kobj_method_t ssichan_methods[] = { + KOBJMETHOD(channel_init, ssichan_init), + KOBJMETHOD(channel_free, ssichan_free), + KOBJMETHOD(channel_setformat, ssichan_setformat), + KOBJMETHOD(channel_setspeed, ssichan_setspeed), + KOBJMETHOD(channel_setblocksize, ssichan_setblocksize), + KOBJMETHOD(channel_trigger, ssichan_trigger), + KOBJMETHOD(channel_getptr, ssichan_getptr), + KOBJMETHOD(channel_getcaps, ssichan_getcaps), + KOBJMETHOD_END +}; +CHANNEL_DECLARE(ssichan); + +static int +ssi_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_is_compatible(dev, "fsl,imx6q-ssi")) + return (ENXIO); + + device_set_desc(dev, "i.MX6 Synchronous Serial Interface (SSI)"); + return (BUS_PROBE_DEFAULT); +} + +static void +ssi_intr(void *arg) +{ + struct sc_pcminfo *scp; + struct sc_chinfo *ch; + struct sc_info *sc; + + scp = arg; + sc = scp->sc; + ch = &scp->chan[0]; + + /* We don't use SSI interrupt */ +#if 0 + device_printf(sc->dev, "SSI Intr 0x%08x\n", + READ4(sc, SSI_SISR)); +#endif +} + +static void +setup_ssi(struct sc_info *sc) +{ + int reg; + + reg = READ4(sc, SSI_STCCR); + reg &= ~(WL3_WL0_M << WL3_WL0_S); + reg |= (0xb << WL3_WL0_S); /* 24 bit */ + reg &= ~(DC4_DC0_M << DC4_DC0_S); + reg |= (1 << DC4_DC0_S); /* 2 words per frame */ + reg &= ~(STCCR_DIV2); /* Divide by 1 */ + reg &= ~(STCCR_PSR); /* Divide by 1 */ + reg &= ~(PM7_PM0_M << PM7_PM0_S); + reg |= (1 << PM7_PM0_S); /* Divide by 2 */ + WRITE4(sc, SSI_STCCR, reg); + + reg = READ4(sc, SSI_SFCSR); + reg &= ~(SFCSR_TFWM0_M << SFCSR_TFWM0_S); + reg |= (8 << SFCSR_TFWM0_S); /* empty slots */ + WRITE4(sc, SSI_SFCSR, reg); + + reg = READ4(sc, SSI_STCR); + reg |= (STCR_TFEN0); + reg &= ~(STCR_TFEN1); + reg &= ~(STCR_TSHFD); /* MSB */ + reg |= (STCR_TXBIT0); + reg |= (STCR_TXDIR | STCR_TFDIR); + reg |= (STCR_TSCKP); /* falling edge */ + reg |= (STCR_TFSI); + reg &= ~(STCR_TFSI); /* active high frame sync */ + reg &= ~(STCR_TFSL); + reg |= STCR_TEFS; + WRITE4(sc, SSI_STCR, reg); + + reg = READ4(sc, SSI_SCR); + reg &= ~(SCR_I2S_MODE_M << SCR_I2S_MODE_S); /* Not master */ + reg |= (SCR_SSIEN | SCR_TE); + reg |= (SCR_NET); + reg |= (SCR_SYN); + WRITE4(sc, SSI_SCR, reg); +} + +static void +ssi_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) +{ + bus_addr_t *addr; + + if (err) + return; + + addr = (bus_addr_t*)arg; + *addr = segs[0].ds_addr; +} + +static int +ssi_attach(device_t dev) +{ + char status[SND_STATUSLEN]; + struct sc_pcminfo *scp; + struct sc_info *sc; + int err; + + sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); + sc->dev = dev; + sc->sr = &rate_map[0]; + sc->pos = 0; + sc->conf = malloc(sizeof(struct sdma_conf), M_DEVBUF, M_WAITOK | M_ZERO); + + sc->lock = snd_mtxcreate(device_get_nameunit(dev), "ssi softc"); + if (sc->lock == NULL) { + device_printf(dev, "Cant create mtx\n"); + return (ENXIO); + } + + if (bus_alloc_resources(dev, ssi_spec, sc->res)) { + device_printf(dev, "could not allocate resources\n"); + return (ENXIO); + } + + /* Memory interface */ + sc->bst = rman_get_bustag(sc->res[0]); + sc->bsh = rman_get_bushandle(sc->res[0]); + + /* SDMA */ + if (find_sdma_controller(sc)) { + device_printf(dev, "could not find active SDMA\n"); + return (ENXIO); + } + + /* Setup PCM */ + scp = malloc(sizeof(struct sc_pcminfo), M_DEVBUF, M_NOWAIT | M_ZERO); + scp->sc = sc; + scp->dev = dev; + + /* + * Maximum possible DMA buffer. + * Will be used partialy to match 24 bit word. + */ + sc->dma_size = 131072; + + /* + * Must use dma_size boundary as modulo feature required. + * Modulo feature allows setup circular buffer. + */ + + err = bus_dma_tag_create( + bus_get_dma_tag(sc->dev), + 4, sc->dma_size, /* alignment, boundary */ + BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + sc->dma_size, 1, /* maxsize, nsegments */ + sc->dma_size, 0, /* maxsegsize, flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->dma_tag); + + err = bus_dmamem_alloc(sc->dma_tag, (void **)&sc->buf_base, + BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->dma_map); + if (err) { + device_printf(dev, "cannot allocate framebuffer\n"); + return (ENXIO); + } + + err = bus_dmamap_load(sc->dma_tag, sc->dma_map, sc->buf_base, + sc->dma_size, ssi_dmamap_cb, &sc->buf_base_phys, BUS_DMA_NOWAIT); + if (err) { + device_printf(dev, "cannot load DMA map\n"); + return (ENXIO); + } + + bzero(sc->buf_base, sc->dma_size); + + /* Setup interrupt handler */ + err = bus_setup_intr(dev, sc->res[1], INTR_MPSAFE | INTR_TYPE_AV, + NULL, ssi_intr, scp, &sc->ih); + if (err) { + device_printf(dev, "Unable to alloc interrupt resource.\n"); + return (ENXIO); + } + + pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); + + err = pcm_register(dev, scp, 1, 0); + if (err) { + device_printf(dev, "Can't register pcm.\n"); + return (ENXIO); + } + + scp->chnum = 0; + pcm_addchan(dev, PCMDIR_PLAY, &ssichan_class, scp); + scp->chnum++; + + snprintf(status, SND_STATUSLEN, "at simplebus"); + pcm_setstatus(dev, status); + + mixer_init(dev, &ssimixer_class, scp); + setup_ssi(sc); + + imx_ccm_ssi_configure(dev); + + sc->sdma_channel = sdma_alloc(); + if (sc->sdma_channel < 0) { + device_printf(sc->dev, "Can't get sDMA channel\n"); + return (1); + } + + return (0); +} + +static device_method_t ssi_pcm_methods[] = { + DEVMETHOD(device_probe, ssi_probe), + DEVMETHOD(device_attach, ssi_attach), + { 0, 0 } +}; + +static driver_t ssi_pcm_driver = { + "pcm", + ssi_pcm_methods, + PCM_SOFTC_SIZE, +}; + +DRIVER_MODULE(ssi, simplebus, ssi_pcm_driver, pcm_devclass, 0, 0); +MODULE_DEPEND(ssi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); +MODULE_VERSION(ssi, 1); Property changes on: stable/10/sys/arm/freescale/imx/imx6_ssi.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/10/sys/arm/freescale/imx/imx_ccmvar.h =================================================================== --- stable/10/sys/arm/freescale/imx/imx_ccmvar.h (revision 283499) +++ stable/10/sys/arm/freescale/imx/imx_ccmvar.h (revision 283500) @@ -1,55 +1,56 @@ /*- * Copyright (c) 2014 Ian Lepore * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef IMX_CCMVAR_H #define IMX_CCMVAR_H /* * We need a clock management system that works across unrelated SoCs and * devices. For now, to keep imx development moving, define some barebones * functionality that can be shared within the imx family by having each SoC * implement functions with a common name. * * The usb enable functions are best-effort. They turn on the usb otg, host, * and phy clocks in a SoC-specific manner, but it may take a lot more than that * to make usb work on a given board. In particular, it can require specific * pinmux setup of gpio pins connected to external phy parts, voltage regulators * and overcurrent detectors, and so on. On such boards, u-boot or other early * board setup code has to handle those things. */ uint32_t imx_ccm_ipg_hz(void); uint32_t imx_ccm_perclk_hz(void); uint32_t imx_ccm_sdhci_hz(void); uint32_t imx_ccm_uart_hz(void); uint32_t imx_ccm_ahb_hz(void); void imx_ccm_usb_enable(device_t _usbdev); void imx_ccm_usbphy_enable(device_t _phydev); +void imx_ccm_ssi_configure(device_t _ssidev); #endif Index: stable/10/sys/boot/fdt/dts/arm/apalis-imx6.dts =================================================================== --- stable/10/sys/boot/fdt/dts/arm/apalis-imx6.dts (nonexistent) +++ stable/10/sys/boot/fdt/dts/arm/apalis-imx6.dts (revision 283500) @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2014-2015 Ruslan Bukin + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include "imx6q-pinfunc.h" + +/dts-v1/; +/include/ "imx6.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + + model = "Toradex Apalis i.MX6"; + compatible = "toradex,imx6q-apalis", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x40000000>; /* RAM 1GB */ + }; + + SOC: soc@00000000 { + aips@02000000 { /* AIPS1 */ + iomux@020e0000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pins_ssi>; + pins_ssi: ssi { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0 + MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x130b0 + >; + }; + }; + gpio@0209c000 { status = "okay"; }; + gpio@020a0000 { status = "okay"; }; + gpio@020a4000 { status = "okay"; }; + gpio@020a8000 { status = "okay"; }; + gpio@020ac000 { status = "okay"; }; + gpio@020b0000 { status = "okay"; }; + gpio@020b4000 { status = "okay"; }; + console:serial@02020000 { status = "okay"; }; + serial@021e8000 { status = "disabled"; }; + serial@021ec000 { status = "disabled"; }; + serial@021f0000 { status = "disabled"; }; + serial@021f4000 { status = "disabled"; }; + usbphy@020c9000 { status = "okay"; }; + usbphy@020ca000 { status = "okay"; }; + ecspi@02008000 { status = "okay"; }; + ssi@02028000 { status = "okay"; }; + sdma@020ec000 { status = "okay"; }; + }; + aips@02100000 { /* AIPS2 */ + ethernet@02188000 { + status = "okay"; + phy-mode = "rgmii"; + phy-disable-preamble; + }; + usb@02184000 { status = "okay"; }; + usb@02184200 { status = "okay"; }; + usb@02184400 { status = "disabled"; }; + usb@02184600 { status = "disabled"; }; + usdhc@02190000 { status = "disabled"; }; + usdhc@02194000 { status = "okay"; }; + usdhc@02198000 { status = "disabled"; }; + usdhc@0219c000 { status = "disabled"; }; + audmux@021d8000 { status = "okay"; }; + i2c@021a0000 { status = "okay"; }; + }; + }; + + chosen { + stdin = &console; + stdout = &console; + }; +}; Property changes on: stable/10/sys/boot/fdt/dts/arm/apalis-imx6.dts ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/10/sys/boot/fdt/dts/arm/imx6.dtsi =================================================================== --- stable/10/sys/boot/fdt/dts/arm/imx6.dtsi (revision 283499) +++ stable/10/sys/boot/fdt/dts/arm/imx6.dtsi (revision 283500) @@ -1,460 +1,464 @@ /* * Copyright (c) 2013 Ian Lepore * Copyright (c) 2012 The FreeBSD Foundation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * Freescale i.MX6 Common Device Tree Source. * There are enough differences between the Solo, Dual, Quad, and *-lite * flavors of this SoC that eventually we will need a finer-grained breakdown * of some of this stuff. For now this file works for all of them. I think. * * $FreeBSD$ */ / { cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "ARM,MCIMX6"; reg = <0x0>; d-cache-line-size = <32>; i-cache-line-size = <32>; d-cache-size = <0x8000>; i-cache-size = <0x8000>; /* TODO: describe L2 cache also */ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; }; }; aliases { soc = &SOC; }; SOC: soc@00000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&gic>; ranges = <0x00000000 0x00000000 0x10000000>; gic: generic-interrupt-controller@00a00100 { compatible = "arm,gic"; interrupt-controller; #interrupt-cells = <1>; reg = <0x00a01000 0x00001000 0x00a00100 0x00000100>; }; mp_tmr0@00a00200 { compatible = "arm,mpcore-timers"; reg = <0x00a00200 0x100 0x00a00600 0x100>; interrupts = <27 29>; interrupt-parent = <&gic>; }; l2-cache@00a02000 { compatible = "arm,pl310-cache", "arm,pl310"; reg = <0xa02000 0x1000>; interrupts = <124>; cache-level = <0x2>; interrupt-parent = < &gic >; }; aips@02000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&gic>; reg = <0x02000000 0x00100000>; ranges; /* Required by many devices, so better to stay first */ clks: ccm@020c4000 { compatible = "fsl,imx6q-ccm"; reg = <0x020c4000 0x4000>; interrupts = <119 120>; }; /* System Reset Controller */ src: src@4006E000 { compatible = "fsl,imx6-src"; reg = <0x020D8000 0x100>; }; sdma: sdma@020ec000 { compatible = "fsl,imx6q-sdma"; reg = <0x020ec000 0x4000>; interrupt-parent = <&gic>; interrupts = <34>; status = "disabled"; }; anatop: anatop@020c8000 { compatible = "fsl,imx6q-anatop"; reg = <0x020c8000 0x1000>; interrupt-parent = <&gic>; interrupts = <49>; }; gpt: timer@02098000 { compatible = "fsl,imx6q-gpt", "fsl,imx51-gpt"; reg = <0x02098000 0x4000>; - interrupt-parent = <&gic>; interrupts = <87>; + interrupt-parent = <&gic>; + interrupts = <87>; }; iomux@020e0000 { - compatible = "fsl,imx6q-iomux"; + compatible = "fsl,imx6q-iomuxc"; reg = <0x020e0000 0x4000>; interrupt-parent = <&gic>; interrupts = <32>; }; gpio1: gpio@0209c000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x0209c000 0x4000>; interrupts = < 98 99 >; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio2: gpio@020a0000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020a0000 0x4000>; interrupts = < 100 101 >; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio3: gpio@020a4000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020a4000 0x4000>; interrupts = < 102 103 >; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio4: gpio@020a8000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020a8000 0x4000>; interrupts = < 104 105 >; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio5: gpio@020ac000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020ac000 0x4000>; interrupts = < 106 107 >; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio6: gpio@020b0000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020b0000 0x4000>; interrupts = < 108 109 >; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; gpio7: gpio@020b4000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020b4000 0x4000>; interrupts = < 110 111 >; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; status = "disabled"; }; uart1: serial@02020000 { compatible = "fsl,imx6q-uart"; reg = <0x02020000 0x4000>; interrupt-parent = <&gic>; interrupts = <58>; clock-frequency = <80000000>; status = "disabled"; }; uart2: serial@021e8000 { compatible = "fsl,imx6q-uart"; reg = <0x021e8000 0x4000>; interrupt-parent = <&gic>; interrupts = <59>; clock-frequency = <80000000>; status = "disabled"; }; uart3: serial@021ec000 { compatible = "fsl,imx6q-uart"; reg = <0x021ec000 0x4000>; interrupt-parent = <&gic>; interrupts = <60>; clock-frequency = <80000000>; status = "disabled"; }; uart4: serial@021f0000 { compatible = "fsl,imx6q-uart"; reg = <0x021f0000 0x4000>; interrupt-parent = <&gic>; interrupts = <61>; clock-frequency = <80000000>; status = "disabled"; }; uart5: serial@021f4000 { compatible = "fsl,imx6q-uart"; reg = <0x021f4000 0x4000>; interrupt-parent = <&gic>; interrupts = <62>; clock-frequency = <80000000>; status = "disabled"; }; usbphy1: usbphy@020c9000 { compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = <44>; status = "disabled"; }; usbphy2: usbphy@020ca000 { compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020ca000 0x1000>; interrupts = <45>; status = "disabled"; }; ecspi1: ecspi@02008000 { compatible = "fsl,imx6q-ecspi"; reg = <0x02008000 0x4000>; interrupts = < 63 >; status = "disabled"; }; ecspi2: ecspi@0200C000 { compatible = "fsl,imx6q-ecspi"; reg = <0x0200C000 0x4000>; interrupts = < 64 >; status = "disabled"; }; ecspi3: ecspi@02010000 { compatible = "fsl,imx6q-ecspi"; reg = <0x02010000 0x4000>; interrupts = < 65 >; status = "disabled"; }; ecspi4: ecspi@02014000 { compatible = "fsl,imx6q-ecspi"; reg = <0x02014000 0x4000>; interrupts = < 66 >; status = "disabled"; }; ecspi5: ecspi@02018000 { compatible = "fsl,imx6q-ecspi"; reg = <0x02018000 0x4000>; interrupts = < 67 >; status = "disabled"; }; ssi1: ssi@02028000 { compatible = "fsl,imx6q-ssi"; reg = <0x02028000 0x4000>; interrupts = < 78 >; + dmas = <&sdma 37 1 0>, + <&sdma 38 1 0>; + dma-names = "rx", "tx"; status = "disabled"; }; ssi2: ssi@0202C000 { compatible = "fsl,imx6q-ssi"; reg = <0x0202C000 0x4000>; interrupts = < 79 >; status = "disabled"; }; ssi3: ssi@02030000 { compatible = "fsl,imx6q-ssi"; reg = <0x02030000 0x4000>; interrupts = < 80 >; status = "disabled"; }; }; aips@02100000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&gic>; reg = <0x02100000 0x00100000>; ranges; i2c1: i2c@021a0000 { compatible = "fsl,imx6q-i2c"; reg = <0x021a0000 0x4000>; interrupts = < 68 >; status = "disabled"; }; i2c2: i2c@021a4000 { compatible = "fsl,imx6q-i2c"; reg = <0x021a4000 0x4000>; interrupts = < 69 >; status = "disabled"; }; i2c3: i2c@021ac000 { compatible = "fsl,imx6q-i2c"; reg = <0x021a8000 0x4000>; interrupts = < 70 >; status = "disabled"; }; fec1: ethernet@02188000 { compatible = "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; interrupts = <150 151>; status = "disabled"; }; usbotg1: usb@02184000 { compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; interrupts = <75>; fsl,usbphy = <&usbphy1>; fsl,usbmisc = <&usbmisc 0>; status = "disabled"; }; usbh1: usb@02184200 { compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184200 0x200>; interrupts = <72>; fsl,usbphy = <&usbphy2>; fsl,usbmisc = <&usbmisc 1>; status = "disabled"; }; usbh2: usb@02184400 { compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184400 0x200>; interrupts = <73>; fsl,usbmisc = <&usbmisc 2>; status = "disabled"; }; usbh3: usb@02184600 { compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184600 0x200>; interrupts = <74>; fsl,usbmisc = <&usbmisc 3>; status = "disabled"; }; usbmisc: usbmisc@02184800 { #index-cells = <1>; compatible = "fsl,imx6q-usbmisc"; reg = <0x02184800 0x200>; // Not disabled on purpose. }; usdhc1: usdhc@02190000 { compatible = "fsl,imx6q-usdhc"; reg = <0x02190000 0x4000>; interrupt-parent = <&gic>; interrupts = <54>; cd-gpios = <&gpio1 2 0>; bus-width = <0x4>; status ="disabled"; }; usdhc2: usdhc@02194000 { compatible = "fsl,imx6q-usdhc"; reg = <0x02194000 0x4000>; interrupt-parent = <&gic>; interrupts = <55>; non-removable; bus-width = <0x4>; status ="disabled"; }; usdhc3: usdhc@02198000 { compatible = "fsl,imx6q-usdhc"; reg = <0x02198000 0x4000>; interrupt-parent = <&gic>; interrupts = <56>; cd-gpios = <&gpio3 9 0>; bus-width = <0x4>; status ="disabled"; }; usdhc4: usdhc@0219c000 { compatible = "fsl,imx6q-usdhc"; reg = <0x0219c000 0x4000>; interrupt-parent = <&gic>; interrupts = <57>; bus-width = <0x4>; status ="disabled"; }; ocotp0: ocotp@021bc000 { compatible = "fsl,imx6q-ocotp"; reg = <0x021bc000 0x4000>; }; audmux: audmux@021d8000 { compatible = "fsl,imx6q-audmux"; reg = <0x021d8000 0x4000>; status = "disabled"; }; }; }; }; Index: stable/10 =================================================================== --- stable/10 (revision 283499) +++ stable/10 (revision 283500) Property changes on: stable/10 ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head:r268838,277644