Index: stable/10/sys/arm/samsung/exynos/uart.h =================================================================== --- stable/10/sys/arm/samsung/exynos/uart.h (revision 283321) +++ stable/10/sys/arm/samsung/exynos/uart.h (nonexistent) @@ -1,126 +0,0 @@ -/* $NetBSD: s3c2xx0reg.h,v 1.4 2004/02/12 03:47:29 bsh Exp $ */ - -/*- - * Copyright (c) 2002, 2003 Fujitsu Component Limited - * Copyright (c) 2002, 2003 Genetec Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of The Fujitsu Component Limited nor the name of - * Genetec corporation may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC - * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC - * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -/* s3c2410-specific registers */ -#define UMCON_AFC (1 << 4) /* auto flow control */ -#define UMSTAT_DCTS (1 << 2) /* CTS change */ -#define ULCON_IR (1 << 6) -#define ULCON_PARITY_SHIFT 3 - -/* - * Exynos-specific - * - * UFSTAT_TXFULL register differs between Exynos and others. - * Others have UFSTAT_TXFULL (1 << 9) - */ -#define UFSTAT_TXFULL (1 << 24) - -#define SSCOM_UINTM 0x038 -#define SSCOM_UINTP 0x030 - -/* common for s3c2800 and s3c24x0 */ -#define SSCOM_ULCON 0x00 /* UART line control */ -#define ULCON_PARITY_NONE (0 << ULCON_PARITY_SHIFT) -#define ULCON_PARITY_ODD (4 << ULCON_PARITY_SHIFT) -#define ULCON_PARITY_EVEN (5 << ULCON_PARITY_SHIFT) -#define ULCON_PARITY_ONE (6 << ULCON_PARITY_SHIFT) -#define ULCON_PARITY_ZERO (7 << ULCON_PARITY_SHIFT) -#define ULCON_STOP (1 << 2) -#define ULCON_LENGTH_5 0 -#define ULCON_LENGTH_6 1 -#define ULCON_LENGTH_7 2 -#define ULCON_LENGTH_8 3 -#define SSCOM_UCON 0x04 /* UART control */ -#define UCON_TXINT_TYPE (1 << 9) /* Tx interrupt. 0=pulse,1=level */ -#define UCON_TXINT_TYPE_LEVEL UCON_TXINT_TYPE -#define UCON_TXINT_TYPE_PULSE 0 -#define UCON_RXINT_TYPE (1 << 8) /* Rx interrupt */ -#define UCON_RXINT_TYPE_LEVEL UCON_RXINT_TYPE -#define UCON_RXINT_TYPE_PULSE 0 -#define UCON_TOINT (1 << 7) /* Rx timeout interrupt */ -#define UCON_ERRINT (1 << 6) /* receive error interrupt */ -#define UCON_LOOP (1 << 5) /* loopback */ -#define UCON_SBREAK (1 << 4) /* send break */ -#define UCON_TXMODE_DISABLE (0 << 2) -#define UCON_TXMODE_INT (1 << 2) -#define UCON_TXMODE_DMA (2 << 2) -#define UCON_TXMODE_MASK (3 << 2) -#define UCON_RXMODE_DISABLE (0 << 0) -#define UCON_RXMODE_INT (1 << 0) -#define UCON_RXMODE_DMA (2 << 0) -#define UCON_RXMODE_MASK (3 << 0) -#define SSCOM_UFCON 0x08 /* FIFO control */ -#define UFCON_TXTRIGGER_0 (0 << 6) -#define UFCON_TXTRIGGER_4 (1 << 6) -#define UFCON_TXTRIGGER_8 (2 << 6) -#define UFCON_TXTRIGGER_16 (3 << 6) -#define UFCON_RXTRIGGER_4 (0 << 4) -#define UFCON_RXTRIGGER_8 (1 << 4) -#define UFCON_RXTRIGGER_12 (2 << 4) -#define UFCON_RXTRIGGER_16 (3 << 4) -#define UFCON_TXFIFO_RESET (1 << 2) -#define UFCON_RXFIFO_RESET (1 << 1) -#define UFCON_FIFO_ENABLE (1 << 0) -#define SSCOM_UMCON 0x0c /* MODEM control */ -#define UMCON_RTS (1 << 0) /* Request to send */ -#define SSCOM_UTRSTAT 0x10 /* Status register */ -#define UTRSTAT_TXSHIFTER_EMPTY ( 1<< 2) -#define UTRSTAT_TXEMPTY (1 << 1) /* TX fifo or buffer empty */ -#define UTRSTAT_RXREADY (1 << 0) /* RX fifo or buffer is not empty */ -#define SSCOM_UERSTAT 0x14 /* Error status register */ -#define UERSTAT_BREAK (1 << 3) /* Break signal, not 2410 */ -#define UERSTAT_FRAME (1 << 2) /* Frame error */ -#define UERSTAT_PARITY (1 << 1) /* Parity error, not 2410 */ -#define UERSTAT_OVERRUN (1 << 0) /* Overrun */ -#define UERSTAT_ALL_ERRORS \ - (UERSTAT_OVERRUN|UERSTAT_BREAK|UERSTAT_FRAME|UERSTAT_PARITY) -#define SSCOM_UFSTAT 0x18 /* Fifo status register */ -#define UFSTAT_RXFULL (1 <<8) /* Rx fifo full */ -#define UFSTAT_TXCOUNT_SHIFT 4 /* TX FIFO count */ -#define UFSTAT_TXCOUNT (0x0f << UFSTAT_TXCOUNT_SHIFT) -#define UFSTAT_RXCOUNT_SHIFT 0 /* RX FIFO count */ -#define UFSTAT_RXCOUNT (0x0f << UFSTAT_RXCOUNT_SHIFT) -#define SSCOM_UMSTAT 0x1c /* Modem status register */ -#define UMSTAT_CTS (1 << 0) /* Clear to send */ -#if _BYTE_ORDER == _LITTLE_ENDIAN -#define SSCOM_UTXH 0x20 /* Transmit data register */ -#define SSCOM_URXH 0x24 /* Receive data register */ -#else -#define SSCOM_UTXH 0x23 /* Transmit data register */ -#define SSCOM_URXH 0x27 /* Receive data register */ -#endif -#define SSCOM_UBRDIV 0x28 /* baud-reate divisor */ -#define SSCOM_SIZE 0x2c Property changes on: stable/10/sys/arm/samsung/exynos/uart.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: stable/10/sys/arm/samsung/exynos/uart.c =================================================================== --- stable/10/sys/arm/samsung/exynos/uart.c (revision 283321) +++ stable/10/sys/arm/samsung/exynos/uart.c (nonexistent) @@ -1,377 +0,0 @@ -/* - * Copyright (c) 2003 Marcel Moolenaar - * Copyright (c) 2007-2009 Andrew Turner - * Copyright (c) 2013 Ruslan Bukin - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include "uart_if.h" - -#define DEF_CLK 100000000 - -static int sscomspeed(long, long); -static int s3c24x0_uart_param(struct uart_bas *, int, int, int, int); - -/* - * Low-level UART interface. - */ -static int s3c2410_probe(struct uart_bas *bas); -static void s3c2410_init(struct uart_bas *bas, int, int, int, int); -static void s3c2410_term(struct uart_bas *bas); -static void s3c2410_putc(struct uart_bas *bas, int); -static int s3c2410_rxready(struct uart_bas *bas); -static int s3c2410_getc(struct uart_bas *bas, struct mtx *mtx); - -extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; - -static int -sscomspeed(long speed, long frequency) -{ - int x; - - if (speed <= 0 || frequency <= 0) - return (-1); - x = (frequency / 16) / speed; - return (x-1); -} - -static int -s3c24x0_uart_param(struct uart_bas *bas, int baudrate, int databits, - int stopbits, int parity) -{ - int brd, ulcon; - - ulcon = 0; - - switch(databits) { - case 5: - ulcon |= ULCON_LENGTH_5; - break; - case 6: - ulcon |= ULCON_LENGTH_6; - break; - case 7: - ulcon |= ULCON_LENGTH_7; - break; - case 8: - ulcon |= ULCON_LENGTH_8; - break; - default: - return (EINVAL); - } - - switch (parity) { - case UART_PARITY_NONE: - ulcon |= ULCON_PARITY_NONE; - break; - case UART_PARITY_ODD: - ulcon |= ULCON_PARITY_ODD; - break; - case UART_PARITY_EVEN: - ulcon |= ULCON_PARITY_EVEN; - break; - case UART_PARITY_MARK: - case UART_PARITY_SPACE: - default: - return (EINVAL); - } - - if (stopbits == 2) - ulcon |= ULCON_STOP; - - uart_setreg(bas, SSCOM_ULCON, ulcon); - - brd = sscomspeed(baudrate, bas->rclk); - uart_setreg(bas, SSCOM_UBRDIV, brd); - - return (0); -} - -struct uart_ops uart_s3c2410_ops = { - .probe = s3c2410_probe, - .init = s3c2410_init, - .term = s3c2410_term, - .putc = s3c2410_putc, - .rxready = s3c2410_rxready, - .getc = s3c2410_getc, -}; - -static int -s3c2410_probe(struct uart_bas *bas) -{ - - return (0); -} - -static void -s3c2410_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, - int parity) -{ - - if (bas->rclk == 0) - bas->rclk = DEF_CLK; - - KASSERT(bas->rclk != 0, ("s3c2410_init: Invalid rclk")); - - uart_setreg(bas, SSCOM_UCON, 0); - uart_setreg(bas, SSCOM_UFCON, - UFCON_TXTRIGGER_8 | UFCON_RXTRIGGER_8 | - UFCON_TXFIFO_RESET | UFCON_RXFIFO_RESET | - UFCON_FIFO_ENABLE); - s3c24x0_uart_param(bas, baudrate, databits, stopbits, parity); - - /* Enable UART. */ - uart_setreg(bas, SSCOM_UCON, UCON_TXMODE_INT | UCON_RXMODE_INT | - UCON_TOINT); - uart_setreg(bas, SSCOM_UMCON, UMCON_RTS); -} - -static void -s3c2410_term(struct uart_bas *bas) -{ - /* XXX */ -} - -static void -s3c2410_putc(struct uart_bas *bas, int c) -{ - - while ((bus_space_read_4(bas->bst, bas->bsh, SSCOM_UFSTAT) & - UFSTAT_TXFULL) == UFSTAT_TXFULL) - continue; - - uart_setreg(bas, SSCOM_UTXH, c); -} - -static int -s3c2410_rxready(struct uart_bas *bas) -{ - - return ((uart_getreg(bas, SSCOM_UTRSTAT) & UTRSTAT_RXREADY) == - UTRSTAT_RXREADY); -} - -static int -s3c2410_getc(struct uart_bas *bas, struct mtx *mtx) -{ - int utrstat; - - utrstat = bus_space_read_1(bas->bst, bas->bsh, SSCOM_UTRSTAT); - while (!(utrstat & UTRSTAT_RXREADY)) { - utrstat = bus_space_read_1(bas->bst, bas->bsh, SSCOM_UTRSTAT); - continue; - } - - return (bus_space_read_1(bas->bst, bas->bsh, SSCOM_URXH)); -} - -static int s3c2410_bus_probe(struct uart_softc *sc); -static int s3c2410_bus_attach(struct uart_softc *sc); -static int s3c2410_bus_flush(struct uart_softc *, int); -static int s3c2410_bus_getsig(struct uart_softc *); -static int s3c2410_bus_ioctl(struct uart_softc *, int, intptr_t); -static int s3c2410_bus_ipend(struct uart_softc *); -static int s3c2410_bus_param(struct uart_softc *, int, int, int, int); -static int s3c2410_bus_receive(struct uart_softc *); -static int s3c2410_bus_setsig(struct uart_softc *, int); -static int s3c2410_bus_transmit(struct uart_softc *); - -static kobj_method_t s3c2410_methods[] = { - KOBJMETHOD(uart_probe, s3c2410_bus_probe), - KOBJMETHOD(uart_attach, s3c2410_bus_attach), - KOBJMETHOD(uart_flush, s3c2410_bus_flush), - KOBJMETHOD(uart_getsig, s3c2410_bus_getsig), - KOBJMETHOD(uart_ioctl, s3c2410_bus_ioctl), - KOBJMETHOD(uart_ipend, s3c2410_bus_ipend), - KOBJMETHOD(uart_param, s3c2410_bus_param), - KOBJMETHOD(uart_receive, s3c2410_bus_receive), - KOBJMETHOD(uart_setsig, s3c2410_bus_setsig), - KOBJMETHOD(uart_transmit, s3c2410_bus_transmit), - - {0, 0 } -}; - -int -s3c2410_bus_probe(struct uart_softc *sc) -{ - - sc->sc_txfifosz = 16; - sc->sc_rxfifosz = 16; - - return (0); -} - -static int -s3c2410_bus_attach(struct uart_softc *sc) -{ - - sc->sc_hwiflow = 0; - sc->sc_hwoflow = 0; - - return (0); -} - -static int -s3c2410_bus_transmit(struct uart_softc *sc) -{ - int i; - int reg; - - uart_lock(sc->sc_hwmtx); - - for (i = 0; i < sc->sc_txdatasz; i++) { - s3c2410_putc(&sc->sc_bas, sc->sc_txbuf[i]); - uart_barrier(&sc->sc_bas); - } - - sc->sc_txbusy = 1; - - uart_unlock(sc->sc_hwmtx); - - /* unmask TX interrupt */ - reg = bus_space_read_4(sc->sc_bas.bst, sc->sc_bas.bsh, SSCOM_UINTM); - reg &= ~(1 << 2); - bus_space_write_4(sc->sc_bas.bst, sc->sc_bas.bsh, SSCOM_UINTM, reg); - - return (0); -} - -static int -s3c2410_bus_setsig(struct uart_softc *sc, int sig) -{ - - return (0); -} - -static int -s3c2410_bus_receive(struct uart_softc *sc) -{ - - uart_rx_put(sc, uart_getreg(&sc->sc_bas, SSCOM_URXH)); - return (0); -} - -static int -s3c2410_bus_param(struct uart_softc *sc, int baudrate, int databits, - int stopbits, int parity) -{ - int error; - - if (sc->sc_bas.rclk == 0) - sc->sc_bas.rclk = DEF_CLK; - - KASSERT(sc->sc_bas.rclk != 0, ("s3c2410_init: Invalid rclk")); - - uart_lock(sc->sc_hwmtx); - error = s3c24x0_uart_param(&sc->sc_bas, baudrate, databits, stopbits, - parity); - uart_unlock(sc->sc_hwmtx); - - return (error); -} - -static int -s3c2410_bus_ipend(struct uart_softc *sc) -{ - uint32_t ints; - uint32_t txempty, rxready; - int reg; - int ipend; - - uart_lock(sc->sc_hwmtx); - ints = bus_space_read_4(sc->sc_bas.bst, sc->sc_bas.bsh, SSCOM_UINTP); - bus_space_write_4(sc->sc_bas.bst, sc->sc_bas.bsh, SSCOM_UINTP, ints); - - txempty = (1 << 2); - rxready = (1 << 0); - - ipend = 0; - if ((ints & txempty) > 0) { - if (sc->sc_txbusy != 0) - ipend |= SER_INT_TXIDLE; - - /* mask TX interrupt */ - reg = bus_space_read_4(sc->sc_bas.bst, sc->sc_bas.bsh, - SSCOM_UINTM); - reg |= (1 << 2); - bus_space_write_4(sc->sc_bas.bst, sc->sc_bas.bsh, - SSCOM_UINTM, reg); - } - - if ((ints & rxready) > 0) { - ipend |= SER_INT_RXREADY; - } - - uart_unlock(sc->sc_hwmtx); - return (ipend); -} - -static int -s3c2410_bus_flush(struct uart_softc *sc, int what) -{ - - return (0); -} - -static int -s3c2410_bus_getsig(struct uart_softc *sc) -{ - - return (0); -} - -static int -s3c2410_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) -{ - - return (EINVAL); -} - -struct uart_class uart_s3c2410_class = { - "s3c2410 class", - s3c2410_methods, - 1, - .uc_ops = &uart_s3c2410_ops, - .uc_range = 8, - .uc_rclk = 0, -}; Property changes on: stable/10/sys/arm/samsung/exynos/uart.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: stable/10/sys/arm/samsung/exynos/exynos_uart.c =================================================================== --- stable/10/sys/arm/samsung/exynos/exynos_uart.c (nonexistent) +++ stable/10/sys/arm/samsung/exynos/exynos_uart.c (revision 283322) @@ -0,0 +1,382 @@ +/* + * Copyright (c) 2003 Marcel Moolenaar + * Copyright (c) 2007-2009 Andrew Turner + * Copyright (c) 2013 Ruslan Bukin + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "uart_if.h" + +#define DEF_CLK 100000000 + +static int sscomspeed(long, long); +static int s3c24x0_uart_param(struct uart_bas *, int, int, int, int); + +/* + * Low-level UART interface. + */ +static int s3c2410_probe(struct uart_bas *bas); +static void s3c2410_init(struct uart_bas *bas, int, int, int, int); +static void s3c2410_term(struct uart_bas *bas); +static void s3c2410_putc(struct uart_bas *bas, int); +static int s3c2410_rxready(struct uart_bas *bas); +static int s3c2410_getc(struct uart_bas *bas, struct mtx *mtx); + +extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; + +static int +sscomspeed(long speed, long frequency) +{ + int x; + + if (speed <= 0 || frequency <= 0) + return (-1); + x = (frequency / 16) / speed; + return (x-1); +} + +static int +s3c24x0_uart_param(struct uart_bas *bas, int baudrate, int databits, + int stopbits, int parity) +{ + int brd, ulcon; + + ulcon = 0; + + switch(databits) { + case 5: + ulcon |= ULCON_LENGTH_5; + break; + case 6: + ulcon |= ULCON_LENGTH_6; + break; + case 7: + ulcon |= ULCON_LENGTH_7; + break; + case 8: + ulcon |= ULCON_LENGTH_8; + break; + default: + return (EINVAL); + } + + switch (parity) { + case UART_PARITY_NONE: + ulcon |= ULCON_PARITY_NONE; + break; + case UART_PARITY_ODD: + ulcon |= ULCON_PARITY_ODD; + break; + case UART_PARITY_EVEN: + ulcon |= ULCON_PARITY_EVEN; + break; + case UART_PARITY_MARK: + case UART_PARITY_SPACE: + default: + return (EINVAL); + } + + if (stopbits == 2) + ulcon |= ULCON_STOP; + + uart_setreg(bas, SSCOM_ULCON, ulcon); + + brd = sscomspeed(baudrate, bas->rclk); + uart_setreg(bas, SSCOM_UBRDIV, brd); + + return (0); +} + +struct uart_ops uart_s3c2410_ops = { + .probe = s3c2410_probe, + .init = s3c2410_init, + .term = s3c2410_term, + .putc = s3c2410_putc, + .rxready = s3c2410_rxready, + .getc = s3c2410_getc, +}; + +static int +s3c2410_probe(struct uart_bas *bas) +{ + + return (0); +} + +static void +s3c2410_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, + int parity) +{ + + if (bas->rclk == 0) + bas->rclk = DEF_CLK; + + KASSERT(bas->rclk != 0, ("s3c2410_init: Invalid rclk")); + + uart_setreg(bas, SSCOM_UCON, 0); + uart_setreg(bas, SSCOM_UFCON, + UFCON_TXTRIGGER_8 | UFCON_RXTRIGGER_8 | + UFCON_TXFIFO_RESET | UFCON_RXFIFO_RESET | + UFCON_FIFO_ENABLE); + s3c24x0_uart_param(bas, baudrate, databits, stopbits, parity); + + /* Enable UART. */ + uart_setreg(bas, SSCOM_UCON, UCON_TXMODE_INT | UCON_RXMODE_INT | + UCON_TOINT); + uart_setreg(bas, SSCOM_UMCON, UMCON_RTS); +} + +static void +s3c2410_term(struct uart_bas *bas) +{ + /* XXX */ +} + +static void +s3c2410_putc(struct uart_bas *bas, int c) +{ + + while ((bus_space_read_4(bas->bst, bas->bsh, SSCOM_UFSTAT) & + UFSTAT_TXFULL) == UFSTAT_TXFULL) + continue; + + uart_setreg(bas, SSCOM_UTXH, c); +} + +static int +s3c2410_rxready(struct uart_bas *bas) +{ + + return ((uart_getreg(bas, SSCOM_UTRSTAT) & UTRSTAT_RXREADY) == + UTRSTAT_RXREADY); +} + +static int +s3c2410_getc(struct uart_bas *bas, struct mtx *mtx) +{ + int utrstat; + + utrstat = bus_space_read_1(bas->bst, bas->bsh, SSCOM_UTRSTAT); + while (!(utrstat & UTRSTAT_RXREADY)) { + utrstat = bus_space_read_1(bas->bst, bas->bsh, SSCOM_UTRSTAT); + continue; + } + + return (bus_space_read_1(bas->bst, bas->bsh, SSCOM_URXH)); +} + +static int s3c2410_bus_probe(struct uart_softc *sc); +static int s3c2410_bus_attach(struct uart_softc *sc); +static int s3c2410_bus_flush(struct uart_softc *, int); +static int s3c2410_bus_getsig(struct uart_softc *); +static int s3c2410_bus_ioctl(struct uart_softc *, int, intptr_t); +static int s3c2410_bus_ipend(struct uart_softc *); +static int s3c2410_bus_param(struct uart_softc *, int, int, int, int); +static int s3c2410_bus_receive(struct uart_softc *); +static int s3c2410_bus_setsig(struct uart_softc *, int); +static int s3c2410_bus_transmit(struct uart_softc *); + +static kobj_method_t s3c2410_methods[] = { + KOBJMETHOD(uart_probe, s3c2410_bus_probe), + KOBJMETHOD(uart_attach, s3c2410_bus_attach), + KOBJMETHOD(uart_flush, s3c2410_bus_flush), + KOBJMETHOD(uart_getsig, s3c2410_bus_getsig), + KOBJMETHOD(uart_ioctl, s3c2410_bus_ioctl), + KOBJMETHOD(uart_ipend, s3c2410_bus_ipend), + KOBJMETHOD(uart_param, s3c2410_bus_param), + KOBJMETHOD(uart_receive, s3c2410_bus_receive), + KOBJMETHOD(uart_setsig, s3c2410_bus_setsig), + KOBJMETHOD(uart_transmit, s3c2410_bus_transmit), + + {0, 0 } +}; + +int +s3c2410_bus_probe(struct uart_softc *sc) +{ + + sc->sc_txfifosz = 16; + sc->sc_rxfifosz = 16; + + return (0); +} + +static int +s3c2410_bus_attach(struct uart_softc *sc) +{ + + sc->sc_hwiflow = 0; + sc->sc_hwoflow = 0; + + return (0); +} + +static int +s3c2410_bus_transmit(struct uart_softc *sc) +{ + int i; + int reg; + + uart_lock(sc->sc_hwmtx); + + for (i = 0; i < sc->sc_txdatasz; i++) { + s3c2410_putc(&sc->sc_bas, sc->sc_txbuf[i]); + uart_barrier(&sc->sc_bas); + } + + sc->sc_txbusy = 1; + + uart_unlock(sc->sc_hwmtx); + + /* unmask TX interrupt */ + reg = bus_space_read_4(sc->sc_bas.bst, sc->sc_bas.bsh, SSCOM_UINTM); + reg &= ~(1 << 2); + bus_space_write_4(sc->sc_bas.bst, sc->sc_bas.bsh, SSCOM_UINTM, reg); + + return (0); +} + +static int +s3c2410_bus_setsig(struct uart_softc *sc, int sig) +{ + + return (0); +} + +static int +s3c2410_bus_receive(struct uart_softc *sc) +{ + struct uart_bas *bas; + + bas = &sc->sc_bas; + while (bus_space_read_4(bas->bst, bas->bsh, + SSCOM_UFSTAT) & UFSTAT_RXCOUNT) + uart_rx_put(sc, uart_getreg(&sc->sc_bas, SSCOM_URXH)); + + return (0); +} + +static int +s3c2410_bus_param(struct uart_softc *sc, int baudrate, int databits, + int stopbits, int parity) +{ + int error; + + if (sc->sc_bas.rclk == 0) + sc->sc_bas.rclk = DEF_CLK; + + KASSERT(sc->sc_bas.rclk != 0, ("s3c2410_init: Invalid rclk")); + + uart_lock(sc->sc_hwmtx); + error = s3c24x0_uart_param(&sc->sc_bas, baudrate, databits, stopbits, + parity); + uart_unlock(sc->sc_hwmtx); + + return (error); +} + +static int +s3c2410_bus_ipend(struct uart_softc *sc) +{ + uint32_t ints; + uint32_t txempty, rxready; + int reg; + int ipend; + + uart_lock(sc->sc_hwmtx); + ints = bus_space_read_4(sc->sc_bas.bst, sc->sc_bas.bsh, SSCOM_UINTP); + bus_space_write_4(sc->sc_bas.bst, sc->sc_bas.bsh, SSCOM_UINTP, ints); + + txempty = (1 << 2); + rxready = (1 << 0); + + ipend = 0; + if ((ints & txempty) > 0) { + if (sc->sc_txbusy != 0) + ipend |= SER_INT_TXIDLE; + + /* mask TX interrupt */ + reg = bus_space_read_4(sc->sc_bas.bst, sc->sc_bas.bsh, + SSCOM_UINTM); + reg |= (1 << 2); + bus_space_write_4(sc->sc_bas.bst, sc->sc_bas.bsh, + SSCOM_UINTM, reg); + } + + if ((ints & rxready) > 0) { + ipend |= SER_INT_RXREADY; + } + + uart_unlock(sc->sc_hwmtx); + return (ipend); +} + +static int +s3c2410_bus_flush(struct uart_softc *sc, int what) +{ + + return (0); +} + +static int +s3c2410_bus_getsig(struct uart_softc *sc) +{ + + return (0); +} + +static int +s3c2410_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) +{ + + return (EINVAL); +} + +struct uart_class uart_s3c2410_class = { + "s3c2410 class", + s3c2410_methods, + 1, + .uc_ops = &uart_s3c2410_ops, + .uc_range = 8, + .uc_rclk = 0, +}; Property changes on: stable/10/sys/arm/samsung/exynos/exynos_uart.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/10/sys/arm/samsung/exynos/exynos_uart.h =================================================================== --- stable/10/sys/arm/samsung/exynos/exynos_uart.h (nonexistent) +++ stable/10/sys/arm/samsung/exynos/exynos_uart.h (revision 283322) @@ -0,0 +1,126 @@ +/* $NetBSD: s3c2xx0reg.h,v 1.4 2004/02/12 03:47:29 bsh Exp $ */ + +/*- + * Copyright (c) 2002, 2003 Fujitsu Component Limited + * Copyright (c) 2002, 2003 Genetec Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of The Fujitsu Component Limited nor the name of + * Genetec corporation may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC + * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC + * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* s3c2410-specific registers */ +#define UMCON_AFC (1 << 4) /* auto flow control */ +#define UMSTAT_DCTS (1 << 2) /* CTS change */ +#define ULCON_IR (1 << 6) +#define ULCON_PARITY_SHIFT 3 + +/* + * Exynos-specific + * + * UFSTAT_TXFULL register differs between Exynos and others. + * Others have UFSTAT_TXFULL (1 << 9) + */ +#define UFSTAT_TXFULL (1 << 24) + +#define SSCOM_UINTM 0x038 +#define SSCOM_UINTP 0x030 + +/* common for s3c2800 and s3c24x0 */ +#define SSCOM_ULCON 0x00 /* UART line control */ +#define ULCON_PARITY_NONE (0 << ULCON_PARITY_SHIFT) +#define ULCON_PARITY_ODD (4 << ULCON_PARITY_SHIFT) +#define ULCON_PARITY_EVEN (5 << ULCON_PARITY_SHIFT) +#define ULCON_PARITY_ONE (6 << ULCON_PARITY_SHIFT) +#define ULCON_PARITY_ZERO (7 << ULCON_PARITY_SHIFT) +#define ULCON_STOP (1 << 2) +#define ULCON_LENGTH_5 0 +#define ULCON_LENGTH_6 1 +#define ULCON_LENGTH_7 2 +#define ULCON_LENGTH_8 3 +#define SSCOM_UCON 0x04 /* UART control */ +#define UCON_TXINT_TYPE (1 << 9) /* Tx interrupt. 0=pulse,1=level */ +#define UCON_TXINT_TYPE_LEVEL UCON_TXINT_TYPE +#define UCON_TXINT_TYPE_PULSE 0 +#define UCON_RXINT_TYPE (1 << 8) /* Rx interrupt */ +#define UCON_RXINT_TYPE_LEVEL UCON_RXINT_TYPE +#define UCON_RXINT_TYPE_PULSE 0 +#define UCON_TOINT (1 << 7) /* Rx timeout interrupt */ +#define UCON_ERRINT (1 << 6) /* receive error interrupt */ +#define UCON_LOOP (1 << 5) /* loopback */ +#define UCON_SBREAK (1 << 4) /* send break */ +#define UCON_TXMODE_DISABLE (0 << 2) +#define UCON_TXMODE_INT (1 << 2) +#define UCON_TXMODE_DMA (2 << 2) +#define UCON_TXMODE_MASK (3 << 2) +#define UCON_RXMODE_DISABLE (0 << 0) +#define UCON_RXMODE_INT (1 << 0) +#define UCON_RXMODE_DMA (2 << 0) +#define UCON_RXMODE_MASK (3 << 0) +#define SSCOM_UFCON 0x08 /* FIFO control */ +#define UFCON_TXTRIGGER_0 (0 << 6) +#define UFCON_TXTRIGGER_4 (1 << 6) +#define UFCON_TXTRIGGER_8 (2 << 6) +#define UFCON_TXTRIGGER_16 (3 << 6) +#define UFCON_RXTRIGGER_4 (0 << 4) +#define UFCON_RXTRIGGER_8 (1 << 4) +#define UFCON_RXTRIGGER_12 (2 << 4) +#define UFCON_RXTRIGGER_16 (3 << 4) +#define UFCON_TXFIFO_RESET (1 << 2) +#define UFCON_RXFIFO_RESET (1 << 1) +#define UFCON_FIFO_ENABLE (1 << 0) +#define SSCOM_UMCON 0x0c /* MODEM control */ +#define UMCON_RTS (1 << 0) /* Request to send */ +#define SSCOM_UTRSTAT 0x10 /* Status register */ +#define UTRSTAT_TXSHIFTER_EMPTY ( 1<< 2) +#define UTRSTAT_TXEMPTY (1 << 1) /* TX fifo or buffer empty */ +#define UTRSTAT_RXREADY (1 << 0) /* RX fifo or buffer is not empty */ +#define SSCOM_UERSTAT 0x14 /* Error status register */ +#define UERSTAT_BREAK (1 << 3) /* Break signal, not 2410 */ +#define UERSTAT_FRAME (1 << 2) /* Frame error */ +#define UERSTAT_PARITY (1 << 1) /* Parity error, not 2410 */ +#define UERSTAT_OVERRUN (1 << 0) /* Overrun */ +#define UERSTAT_ALL_ERRORS \ + (UERSTAT_OVERRUN|UERSTAT_BREAK|UERSTAT_FRAME|UERSTAT_PARITY) +#define SSCOM_UFSTAT 0x18 /* Fifo status register */ +#define UFSTAT_RXFULL (1 <<8) /* Rx fifo full */ +#define UFSTAT_TXCOUNT_SHIFT 4 /* TX FIFO count */ +#define UFSTAT_TXCOUNT (0x0f << UFSTAT_TXCOUNT_SHIFT) +#define UFSTAT_RXCOUNT_SHIFT 0 /* RX FIFO count */ +#define UFSTAT_RXCOUNT (0x0f << UFSTAT_RXCOUNT_SHIFT) +#define SSCOM_UMSTAT 0x1c /* Modem status register */ +#define UMSTAT_CTS (1 << 0) /* Clear to send */ +#if _BYTE_ORDER == _LITTLE_ENDIAN +#define SSCOM_UTXH 0x20 /* Transmit data register */ +#define SSCOM_URXH 0x24 /* Receive data register */ +#else +#define SSCOM_UTXH 0x23 /* Transmit data register */ +#define SSCOM_URXH 0x27 /* Receive data register */ +#endif +#define SSCOM_UBRDIV 0x28 /* baud-reate divisor */ +#define SSCOM_SIZE 0x2c Property changes on: stable/10/sys/arm/samsung/exynos/exynos_uart.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/10/sys/arm/samsung/exynos/files.exynos5 =================================================================== --- stable/10/sys/arm/samsung/exynos/files.exynos5 (revision 283321) +++ stable/10/sys/arm/samsung/exynos/files.exynos5 (revision 283322) @@ -1,31 +1,31 @@ # $FreeBSD$ kern/kern_clocksource.c standard arm/arm/bus_space_generic.c standard arm/arm/bus_space_asm_generic.S standard arm/arm/cpufunc_asm_armv5.S standard arm/arm/cpufunc_asm_arm10.S standard arm/arm/cpufunc_asm_arm11.S standard arm/arm/cpufunc_asm_armv7.S standard arm/arm/bus_space_base.c standard arm/arm/gic.c standard arm/arm/generic_timer.c standard arm/samsung/exynos/exynos5_mct.c standard arm/samsung/exynos/exynos5_mp.c optional smp arm/samsung/exynos/exynos5_common.c standard arm/samsung/exynos/exynos5_machdep.c standard arm/samsung/exynos/exynos5_combiner.c standard arm/samsung/exynos/exynos5_pad.c optional gpio -arm/samsung/exynos/uart.c optional uart +arm/samsung/exynos/exynos_uart.c optional uart arm/samsung/exynos/exynos5_ehci.c optional ehci arm/samsung/exynos/exynos5_fimd.c optional vt arm/samsung/exynos/exynos5_i2c.c optional iicbus # chromebook drivers arm/samsung/exynos/chrome_ec.c optional chrome_ec arm/samsung/exynos/chrome_kb.c optional chrome_kb #dev/sdhci/sdhci_fdt.c optional sdhci Index: stable/10 =================================================================== --- stable/10 (revision 283321) +++ stable/10 (revision 283322) Property changes on: stable/10 ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head:r266942,266944