Index: head/sys/arm/allwinner/a10_clk.c =================================================================== --- head/sys/arm/allwinner/a10_clk.c (revision 283252) +++ head/sys/arm/allwinner/a10_clk.c (revision 283253) @@ -1,191 +1,299 @@ /*- * Copyright (c) 2013 Ganbold Tsagaankhuu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* Simple clock driver for Allwinner A10 */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "a10_clk.h" struct a10_ccm_softc { struct resource *res; bus_space_tag_t bst; bus_space_handle_t bsh; }; static struct a10_ccm_softc *a10_ccm_sc = NULL; #define ccm_read_4(sc, reg) \ bus_space_read_4((sc)->bst, (sc)->bsh, (reg)) #define ccm_write_4(sc, reg, val) \ bus_space_write_4((sc)->bst, (sc)->bsh, (reg), (val)) static int a10_ccm_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "allwinner,sun4i-ccm")) { device_set_desc(dev, "Allwinner Clock Control Module"); return(BUS_PROBE_DEFAULT); } return (ENXIO); } static int a10_ccm_attach(device_t dev) { struct a10_ccm_softc *sc = device_get_softc(dev); int rid = 0; if (a10_ccm_sc) return (ENXIO); sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->res) { device_printf(dev, "could not allocate resource\n"); return (ENXIO); } sc->bst = rman_get_bustag(sc->res); sc->bsh = rman_get_bushandle(sc->res); a10_ccm_sc = sc; return (0); } static device_method_t a10_ccm_methods[] = { DEVMETHOD(device_probe, a10_ccm_probe), DEVMETHOD(device_attach, a10_ccm_attach), { 0, 0 } }; static driver_t a10_ccm_driver = { "a10_ccm", a10_ccm_methods, sizeof(struct a10_ccm_softc), }; static devclass_t a10_ccm_devclass; DRIVER_MODULE(a10_ccm, simplebus, a10_ccm_driver, a10_ccm_devclass, 0, 0); int a10_clk_usb_activate(void) { struct a10_ccm_softc *sc = a10_ccm_sc; uint32_t reg_value; if (sc == NULL) return (ENXIO); /* Gating AHB clock for USB */ reg_value = ccm_read_4(sc, CCM_AHB_GATING0); reg_value |= CCM_AHB_GATING_USB0; /* AHB clock gate usb0 */ reg_value |= CCM_AHB_GATING_EHCI0; /* AHB clock gate ehci0 */ reg_value |= CCM_AHB_GATING_EHCI1; /* AHB clock gate ehci1 */ ccm_write_4(sc, CCM_AHB_GATING0, reg_value); /* Enable clock for USB */ reg_value = ccm_read_4(sc, CCM_USB_CLK); reg_value |= CCM_USB_PHY; /* USBPHY */ reg_value |= CCM_USB0_RESET; /* disable reset for USB0 */ reg_value |= CCM_USB1_RESET; /* disable reset for USB1 */ reg_value |= CCM_USB2_RESET; /* disable reset for USB2 */ ccm_write_4(sc, CCM_USB_CLK, reg_value); return (0); } int a10_clk_usb_deactivate(void) { struct a10_ccm_softc *sc = a10_ccm_sc; uint32_t reg_value; if (sc == NULL) return (ENXIO); /* Disable clock for USB */ reg_value = ccm_read_4(sc, CCM_USB_CLK); reg_value &= ~CCM_USB_PHY; /* USBPHY */ reg_value &= ~CCM_USB0_RESET; /* reset for USB0 */ reg_value &= ~CCM_USB1_RESET; /* reset for USB1 */ reg_value &= ~CCM_USB2_RESET; /* reset for USB2 */ ccm_write_4(sc, CCM_USB_CLK, reg_value); /* Disable gating AHB clock for USB */ reg_value = ccm_read_4(sc, CCM_AHB_GATING0); reg_value &= ~CCM_AHB_GATING_USB0; /* disable AHB clock gate usb0 */ reg_value &= ~CCM_AHB_GATING_EHCI0; /* disable AHB clock gate ehci0 */ reg_value &= ~CCM_AHB_GATING_EHCI1; /* disable AHB clock gate ehci1 */ ccm_write_4(sc, CCM_AHB_GATING0, reg_value); return (0); } int -a10_clk_emac_activate(void) { +a10_clk_emac_activate(void) +{ struct a10_ccm_softc *sc = a10_ccm_sc; uint32_t reg_value; if (sc == NULL) return (ENXIO); /* Gating AHB clock for EMAC */ reg_value = ccm_read_4(sc, CCM_AHB_GATING0); reg_value |= CCM_AHB_GATING_EMAC; ccm_write_4(sc, CCM_AHB_GATING0, reg_value); return (0); } +static void +a10_clk_pll6_enable(void) +{ + struct a10_ccm_softc *sc; + uint32_t reg_value; + + /* + * SATA needs PLL6 to be a 100MHz clock. + * The SATA output frequency is 24MHz * n * k / m / 6. + * To get to 100MHz, k & m must be equal and n must be 25. + * For other uses the output frequency is 24MHz * n * k / 2. + */ + sc = a10_ccm_sc; + reg_value = ccm_read_4(sc, CCM_PLL6_CFG); + reg_value &= ~CCM_PLL_CFG_BYPASS; + reg_value &= ~(CCM_PLL_CFG_FACTOR_K | CCM_PLL_CFG_FACTOR_M | + CCM_PLL_CFG_FACTOR_N); + reg_value |= (25 << CCM_PLL_CFG_FACTOR_N_SHIFT); + reg_value |= CCM_PLL6_CFG_SATA_CLKEN; + reg_value |= CCM_PLL_CFG_ENABLE; + ccm_write_4(sc, CCM_PLL6_CFG, reg_value); +} + +static unsigned int +a10_clk_pll6_get_rate(void) +{ + struct a10_ccm_softc *sc; + uint32_t k, n, reg_value; + + sc = a10_ccm_sc; + reg_value = ccm_read_4(sc, CCM_PLL6_CFG); + n = ((reg_value & CCM_PLL_CFG_FACTOR_N) >> CCM_PLL_CFG_FACTOR_N_SHIFT); + k = ((reg_value & CCM_PLL_CFG_FACTOR_K) >> CCM_PLL_CFG_FACTOR_K_SHIFT) + + 1; + + return ((CCM_CLK_REF_FREQ * n * k) / 2); +} + +int +a10_clk_mmc_activate(int devid) +{ + struct a10_ccm_softc *sc; + uint32_t reg_value; + + sc = a10_ccm_sc; + if (sc == NULL) + return (ENXIO); + + a10_clk_pll6_enable(); + + /* Gating AHB clock for SD/MMC */ + reg_value = ccm_read_4(sc, CCM_AHB_GATING0); + reg_value |= CCM_AHB_GATING_SDMMC0 << devid; + ccm_write_4(sc, CCM_AHB_GATING0, reg_value); + + return (0); +} + +int +a10_clk_mmc_cfg(int devid, int freq) +{ + struct a10_ccm_softc *sc; + uint32_t clksrc, m, n, ophase, phase, reg_value; + unsigned int pll_freq; + + sc = a10_ccm_sc; + if (sc == NULL) + return (ENXIO); + + freq /= 1000; + if (freq <= 400) { + pll_freq = CCM_CLK_REF_FREQ / 1000; + clksrc = CCM_SD_CLK_SRC_SEL_OSC24M; + ophase = 0; + phase = 0; + n = 2; + } else if (freq <= 25000) { + pll_freq = a10_clk_pll6_get_rate() / 1000; + clksrc = CCM_SD_CLK_SRC_SEL_PLL6; + ophase = 0; + phase = 5; + n = 2; + } else if (freq <= 50000) { + pll_freq = a10_clk_pll6_get_rate() / 1000; + clksrc = CCM_SD_CLK_SRC_SEL_PLL6; + ophase = 3; + phase = 5; + n = 0; + } else + return (EINVAL); + m = ((pll_freq / (1 << n)) / (freq)) - 1; + reg_value = ccm_read_4(sc, CCM_MMC0_SCLK_CFG + (devid * 4)); + reg_value &= ~CCM_SD_CLK_SRC_SEL; + reg_value |= (clksrc << CCM_SD_CLK_SRC_SEL_SHIFT); + reg_value &= ~CCM_SD_CLK_PHASE_CTR; + reg_value |= (phase << CCM_SD_CLK_PHASE_CTR_SHIFT); + reg_value &= ~CCM_SD_CLK_DIV_RATIO_N; + reg_value |= (n << CCM_SD_CLK_DIV_RATIO_N_SHIFT); + reg_value &= ~CCM_SD_CLK_OPHASE_CTR; + reg_value |= (ophase << CCM_SD_CLK_OPHASE_CTR_SHIFT); + reg_value &= ~CCM_SD_CLK_DIV_RATIO_M; + reg_value |= m; + reg_value |= CCM_PLL_CFG_ENABLE; + ccm_write_4(sc, CCM_MMC0_SCLK_CFG + (devid * 4), reg_value); + + return (0); +} Index: head/sys/arm/allwinner/a10_clk.h =================================================================== --- head/sys/arm/allwinner/a10_clk.h (revision 283252) +++ head/sys/arm/allwinner/a10_clk.h (revision 283253) @@ -1,117 +1,146 @@ /*- * Copyright (c) 2013 Ganbold Tsagaankhuu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _A10_CLK_H_ #define _A10_CLK_H_ #define CCMU_BASE 0xe1c20000 #define CCM_PLL1_CFG 0x0000 #define CCM_PLL1_TUN 0x0004 #define CCM_PLL2_CFG 0x0008 #define CCM_PLL2_TUN 0x000c #define CCM_PLL3_CFG 0x0010 #define CCM_PLL3_TUN 0x0014 #define CCM_PLL4_CFG 0x0018 #define CCM_PLL4_TUN 0x001c #define CCM_PLL5_CFG 0x0020 #define CCM_PLL5_TUN 0x0024 #define CCM_PLL6_CFG 0x0028 #define CCM_PLL6_TUN 0x002c #define CCM_PLL7_CFG 0x0030 #define CCM_PLL7_TUN 0x0034 #define CCM_PLL1_TUN2 0x0038 #define CCM_PLL5_TUN2 0x003c #define CCM_PLL_LOCK_DBG 0x004c #define CCM_OSC24M_CFG 0x0050 #define CCM_CPU_AHB_APB0_CFG 0x0054 #define CCM_APB1_CLK_DIV 0x0058 #define CCM_AXI_GATING 0x005c #define CCM_AHB_GATING0 0x0060 #define CCM_AHB_GATING1 0x0064 #define CCM_APB0_GATING 0x0068 #define CCM_APB1_GATING 0x006c #define CCM_NAND_SCLK_CFG 0x0080 #define CCM_MS_SCLK_CFG 0x0084 #define CCM_MMC0_SCLK_CFG 0x0088 #define CCM_MMC1_SCLK_CFG 0x008c #define CCM_MMC2_SCLK_CFG 0x0090 #define CCM_MMC3_SCLK_CFG 0x0094 #define CCM_TS_CLK 0x0098 #define CCM_SS_CLK 0x009c #define CCM_SPI0_CLK 0x00a0 #define CCM_SPI1_CLK 0x00a4 #define CCM_SPI2_CLK 0x00a8 #define CCM_PATA_CLK 0x00ac #define CCM_IR0_CLK 0x00b0 #define CCM_IR1_CLK 0x00b4 #define CCM_IIS_CLK 0x00b8 #define CCM_AC97_CLK 0x00bc #define CCM_SPDIF_CLK 0x00c0 #define CCM_KEYPAD_CLK 0x00c4 #define CCM_SATA_CLK 0x00c8 #define CCM_USB_CLK 0x00cc #define CCM_GPS_CLK 0x00d0 #define CCM_SPI3_CLK 0x00d4 #define CCM_DRAM_CLK 0x0100 #define CCM_BE0_SCLK 0x0104 #define CCM_BE1_SCLK 0x0108 #define CCM_FE0_CLK 0x010c #define CCM_FE1_CLK 0x0110 #define CCM_MP_CLK 0x0114 #define CCM_LCD0_CH0_CLK 0x0118 #define CCM_LCD1_CH0_CLK 0x011c #define CCM_CSI_ISP_CLK 0x0120 #define CCM_TVD_CLK 0x0128 #define CCM_LCD0_CH1_CLK 0x012c #define CCM_LCD1_CH1_CLK 0x0130 #define CCM_CS0_CLK 0x0134 #define CCM_CS1_CLK 0x0138 #define CCM_VE_CLK 0x013c #define CCM_AUDIO_CODEC_CLK 0x0140 #define CCM_AVS_CLK 0x0144 #define CCM_ACE_CLK 0x0148 #define CCM_LVDS_CLK 0x014c #define CCM_HDMI_CLK 0x0150 #define CCM_MALI400_CLK 0x0154 #define CCM_AHB_GATING_USB0 (1 << 0) #define CCM_AHB_GATING_EHCI0 (1 << 1) #define CCM_AHB_GATING_EHCI1 (1 << 3) +#define CCM_AHB_GATING_SDMMC0 (1 << 8) #define CCM_AHB_GATING_EMAC (1 << 17) #define CCM_USB_PHY (1 << 8) #define CCM_USB0_RESET (1 << 0) #define CCM_USB1_RESET (1 << 1) #define CCM_USB2_RESET (1 << 2) +#define CCM_PLL_CFG_ENABLE (1U << 31) +#define CCM_PLL_CFG_BYPASS (1U << 30) +#define CCM_PLL_CFG_PLL5 (1U << 25) +#define CCM_PLL_CFG_PLL6 (1U << 24) +#define CCM_PLL_CFG_FACTOR_N 0x1f00 +#define CCM_PLL_CFG_FACTOR_N_SHIFT 8 +#define CCM_PLL_CFG_FACTOR_K 0x30 +#define CCM_PLL_CFG_FACTOR_K_SHIFT 4 +#define CCM_PLL_CFG_FACTOR_M 0x3 + +#define CCM_PLL6_CFG_SATA_CLKEN (1U << 14) + +#define CCM_SD_CLK_SRC_SEL 0x3000000 +#define CCM_SD_CLK_SRC_SEL_SHIFT 24 +#define CCM_SD_CLK_SRC_SEL_OSC24M 0 +#define CCM_SD_CLK_SRC_SEL_PLL6 1 +#define CCM_SD_CLK_PHASE_CTR 0x700000 +#define CCM_SD_CLK_PHASE_CTR_SHIFT 20 +#define CCM_SD_CLK_DIV_RATIO_N 0x30000 +#define CCM_SD_CLK_DIV_RATIO_N_SHIFT 16 +#define CCM_SD_CLK_OPHASE_CTR 0x700 +#define CCM_SD_CLK_OPHASE_CTR_SHIFT 8 +#define CCM_SD_CLK_DIV_RATIO_M 0xf + +#define CCM_CLK_REF_FREQ 24000000U + int a10_clk_usb_activate(void); int a10_clk_usb_deactivate(void); int a10_clk_emac_activate(void); +int a10_clk_mmc_activate(int); +int a10_clk_mmc_cfg(int, int); #endif /* _A10_CLK_H_ */ Index: head/sys/arm/allwinner/a10_mmc.c =================================================================== --- head/sys/arm/allwinner/a10_mmc.c (nonexistent) +++ head/sys/arm/allwinner/a10_mmc.c (revision 283253) @@ -0,0 +1,689 @@ +/*- + * Copyright (c) 2013 Alexander Fedorov + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include + +#include +#include + +#define A10_MMC_MEMRES 0 +#define A10_MMC_IRQRES 1 +#define A10_MMC_RESSZ 2 + +struct a10_mmc_softc { + bus_space_handle_t a10_bsh; + bus_space_tag_t a10_bst; + device_t a10_dev; + int a10_bus_busy; + int a10_id; + int a10_resid; + int a10_timeout; + struct callout a10_timeoutc; + struct mmc_host a10_host; + struct mmc_request * a10_req; + struct mtx a10_mtx; + struct resource * a10_res[A10_MMC_RESSZ]; + uint32_t a10_intr; + uint32_t a10_intr_wait; + void * a10_intrhand; +}; + +static struct resource_spec a10_mmc_res_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, + { -1, 0, 0 } +}; + +static int a10_mmc_probe(device_t); +static int a10_mmc_attach(device_t); +static int a10_mmc_detach(device_t); +static int a10_mmc_reset(struct a10_mmc_softc *); +static void a10_mmc_intr(void *); +static int a10_mmc_update_clock(struct a10_mmc_softc *); + +static int a10_mmc_update_ios(device_t, device_t); +static int a10_mmc_request(device_t, device_t, struct mmc_request *); +static int a10_mmc_get_ro(device_t, device_t); +static int a10_mmc_acquire_host(device_t, device_t); +static int a10_mmc_release_host(device_t, device_t); + +#define A10_MMC_LOCK(_sc) mtx_lock(&(_sc)->a10_mtx) +#define A10_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->a10_mtx) +#define A10_MMC_READ_4(_sc, _reg) \ + bus_space_read_4((_sc)->a10_bst, (_sc)->a10_bsh, _reg) +#define A10_MMC_WRITE_4(_sc, _reg, _value) \ + bus_space_write_4((_sc)->a10_bst, (_sc)->a10_bsh, _reg, _value) + +static int +a10_mmc_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-mmc")) + return (ENXIO); + device_set_desc(dev, "Allwinner Integrated MMC/SD controller"); + + return (BUS_PROBE_DEFAULT); +} + +static int +a10_mmc_attach(device_t dev) +{ + device_t child; + struct a10_mmc_softc *sc; + struct sysctl_ctx_list *ctx; + struct sysctl_oid_list *tree; + + sc = device_get_softc(dev); + sc->a10_dev = dev; + sc->a10_req = NULL; + sc->a10_id = device_get_unit(dev); + if (sc->a10_id > 3) { + device_printf(dev, "only 4 hosts are supported (0-3)\n"); + return (ENXIO); + } + if (bus_alloc_resources(dev, a10_mmc_res_spec, sc->a10_res) != 0) { + device_printf(dev, "cannot allocate device resources\n"); + return (ENXIO); + } + sc->a10_bst = rman_get_bustag(sc->a10_res[A10_MMC_MEMRES]); + sc->a10_bsh = rman_get_bushandle(sc->a10_res[A10_MMC_MEMRES]); + if (bus_setup_intr(dev, sc->a10_res[A10_MMC_IRQRES], + INTR_TYPE_MISC | INTR_MPSAFE, NULL, a10_mmc_intr, sc, + &sc->a10_intrhand)) { + bus_release_resources(dev, a10_mmc_res_spec, sc->a10_res); + device_printf(dev, "cannot setup interrupt handler\n"); + return (ENXIO); + } + + /* Activate the module clock. */ + if (a10_clk_mmc_activate(sc->a10_id) != 0) { + bus_teardown_intr(dev, sc->a10_res[A10_MMC_IRQRES], + sc->a10_intrhand); + bus_release_resources(dev, a10_mmc_res_spec, sc->a10_res); + device_printf(dev, "cannot activate mmc clock\n"); + return (ENXIO); + } + + sc->a10_timeout = 10; + ctx = device_get_sysctl_ctx(dev); + tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); + SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW, + &sc->a10_timeout, 0, "Request timeout in seconds"); + mtx_init(&sc->a10_mtx, device_get_nameunit(sc->a10_dev), "a10_mmc", + MTX_DEF); + callout_init_mtx(&sc->a10_timeoutc, &sc->a10_mtx, 0); + + /* Reset controller. */ + if (a10_mmc_reset(sc) != 0) { + device_printf(dev, "cannot reset the controller\n"); + goto fail; + } + + sc->a10_host.f_min = 400000; + sc->a10_host.f_max = 52000000; + sc->a10_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; + sc->a10_host.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_HSPEED; + sc->a10_host.mode = mode_sd; + + child = device_add_child(dev, "mmc", -1); + if (child == NULL) { + device_printf(dev, "attaching MMC bus failed!\n"); + goto fail; + } + if (device_probe_and_attach(child) != 0) { + device_printf(dev, "attaching MMC child failed!\n"); + device_delete_child(dev, child); + goto fail; + } + + return (0); + +fail: + callout_drain(&sc->a10_timeoutc); + mtx_destroy(&sc->a10_mtx); + bus_teardown_intr(dev, sc->a10_res[A10_MMC_IRQRES], sc->a10_intrhand); + bus_release_resources(dev, a10_mmc_res_spec, sc->a10_res); + + return (ENXIO); +} + +static int +a10_mmc_detach(device_t dev) +{ + + return (EBUSY); +} + +static int +a10_mmc_reset(struct a10_mmc_softc *sc) +{ + int timeout; + + A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, + A10_MMC_READ_4(sc, A10_MMC_GCTRL) | A10_MMC_RESET); + timeout = 1000; + while (--timeout > 0) { + if ((A10_MMC_READ_4(sc, A10_MMC_GCTRL) & A10_MMC_RESET) == 0) + break; + DELAY(100); + } + if (timeout == 0) + return (ETIMEDOUT); + + /* Set the timeout. */ + A10_MMC_WRITE_4(sc, A10_MMC_TIMEOUT, 0xffffffff); + + /* Clear pending interrupts. */ + A10_MMC_WRITE_4(sc, A10_MMC_RINTR, 0xffffffff); + /* Unmask interrupts. */ + A10_MMC_WRITE_4(sc, A10_MMC_IMASK, + A10_MMC_CMD_DONE | A10_MMC_INT_ERR_BIT | + A10_MMC_DATA_OVER | A10_MMC_AUTOCMD_DONE | + A10_MMC_RX_DATA_REQ | A10_MMC_TX_DATA_REQ); + /* Enable interrupts and AHB access. */ + A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, + A10_MMC_READ_4(sc, A10_MMC_GCTRL) | + A10_MMC_INT_ENABLE | A10_MMC_ACCESS_BY_AHB); + + return (0); +} + +static void +a10_mmc_req_done(struct a10_mmc_softc *sc) +{ + struct mmc_command *cmd; + struct mmc_request *req; + + cmd = sc->a10_req->cmd; + if (cmd->error != MMC_ERR_NONE) { + /* Reset the controller. */ + a10_mmc_reset(sc); + a10_mmc_update_clock(sc); + } + /* Reset the FIFO. */ + A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, + A10_MMC_READ_4(sc, A10_MMC_GCTRL) | A10_MMC_FIFO_RESET); + + req = sc->a10_req; + callout_stop(&sc->a10_timeoutc); + sc->a10_req = NULL; + sc->a10_intr = 0; + sc->a10_resid = 0; + sc->a10_intr_wait = 0; + req->done(req); +} + +static void +a10_mmc_req_ok(struct a10_mmc_softc *sc) +{ + int timeout; + struct mmc_command *cmd; + uint32_t status; + + timeout = 1000; + while (--timeout > 0) { + status = A10_MMC_READ_4(sc, A10_MMC_STAS); + if ((status & A10_MMC_CARD_DATA_BUSY) == 0) + break; + DELAY(1000); + } + cmd = sc->a10_req->cmd; + if (timeout == 0) { + cmd->error = MMC_ERR_FAILED; + a10_mmc_req_done(sc); + return; + } + if (cmd->flags & MMC_RSP_PRESENT) { + if (cmd->flags & MMC_RSP_136) { + cmd->resp[0] = A10_MMC_READ_4(sc, A10_MMC_RESP3); + cmd->resp[1] = A10_MMC_READ_4(sc, A10_MMC_RESP2); + cmd->resp[2] = A10_MMC_READ_4(sc, A10_MMC_RESP1); + cmd->resp[3] = A10_MMC_READ_4(sc, A10_MMC_RESP0); + } else + cmd->resp[0] = A10_MMC_READ_4(sc, A10_MMC_RESP0); + } + /* All data has been transferred ? */ + if (cmd->data != NULL && (sc->a10_resid << 2) < cmd->data->len) + cmd->error = MMC_ERR_FAILED; + a10_mmc_req_done(sc); +} + +static void +a10_mmc_timeout(void *arg) +{ + struct a10_mmc_softc *sc; + + sc = (struct a10_mmc_softc *)arg; + if (sc->a10_req != NULL) { + device_printf(sc->a10_dev, "controller timeout\n"); + sc->a10_req->cmd->error = MMC_ERR_TIMEOUT; + a10_mmc_req_done(sc); + } else + device_printf(sc->a10_dev, + "Spurious timeout - no active request\n"); +} + +static int +a10_mmc_pio_transfer(struct a10_mmc_softc *sc, struct mmc_data *data) +{ + int i, write; + uint32_t bit, *buf; + + buf = (uint32_t *)data->data; + write = (data->flags & MMC_DATA_WRITE) ? 1 : 0; + bit = write ? A10_MMC_FIFO_FULL : A10_MMC_FIFO_EMPTY; + for (i = sc->a10_resid; i < (data->len >> 2); i++) { + if ((A10_MMC_READ_4(sc, A10_MMC_STAS) & bit)) + return (1); + if (write) + A10_MMC_WRITE_4(sc, A10_MMC_FIFO, buf[i]); + else + buf[i] = A10_MMC_READ_4(sc, A10_MMC_FIFO); + sc->a10_resid = i + 1; + } + + return (0); +} + +static void +a10_mmc_intr(void *arg) +{ + struct a10_mmc_softc *sc; + struct mmc_data *data; + uint32_t imask, rint; + + sc = (struct a10_mmc_softc *)arg; + A10_MMC_LOCK(sc); + rint = A10_MMC_READ_4(sc, A10_MMC_RINTR); + imask = A10_MMC_READ_4(sc, A10_MMC_IMASK); + if (imask == 0 && rint == 0) { + A10_MMC_UNLOCK(sc); + return; + } +#ifdef DEBUG + device_printf(sc->a10_dev, "imask: %#x, rint: %#x\n", imask, rint); +#endif + if (sc->a10_req == NULL) { + device_printf(sc->a10_dev, + "Spurious interrupt - no active request, rint: 0x%08X\n", + rint); + A10_MMC_WRITE_4(sc, A10_MMC_RINTR, rint); + A10_MMC_UNLOCK(sc); + return; + } + if (rint & A10_MMC_INT_ERR_BIT) { + device_printf(sc->a10_dev, "error rint: 0x%08X\n", rint); + if (rint & A10_MMC_RESP_TIMEOUT) + sc->a10_req->cmd->error = MMC_ERR_TIMEOUT; + else + sc->a10_req->cmd->error = MMC_ERR_FAILED; + A10_MMC_WRITE_4(sc, A10_MMC_RINTR, rint); + a10_mmc_req_done(sc); + A10_MMC_UNLOCK(sc); + return; + } + + sc->a10_intr |= rint; + data = sc->a10_req->cmd->data; + if (data != NULL && (rint & (A10_MMC_DATA_OVER | + A10_MMC_RX_DATA_REQ | A10_MMC_TX_DATA_REQ)) != 0) + a10_mmc_pio_transfer(sc, data); + if ((sc->a10_intr & sc->a10_intr_wait) == sc->a10_intr_wait) + a10_mmc_req_ok(sc); + + A10_MMC_WRITE_4(sc, A10_MMC_RINTR, rint); + A10_MMC_UNLOCK(sc); +} + +static int +a10_mmc_request(device_t bus, device_t child, struct mmc_request *req) +{ + int blksz; + struct a10_mmc_softc *sc; + struct mmc_command *cmd; + uint32_t cmdreg; + + sc = device_get_softc(bus); + A10_MMC_LOCK(sc); + if (sc->a10_req) { + A10_MMC_UNLOCK(sc); + return (EBUSY); + } + sc->a10_req = req; + cmd = req->cmd; + cmdreg = A10_MMC_START; + if (cmd->opcode == MMC_GO_IDLE_STATE) + cmdreg |= A10_MMC_SEND_INIT_SEQ; + if (cmd->flags & MMC_RSP_PRESENT) + cmdreg |= A10_MMC_RESP_EXP; + if (cmd->flags & MMC_RSP_136) + cmdreg |= A10_MMC_LONG_RESP; + if (cmd->flags & MMC_RSP_CRC) + cmdreg |= A10_MMC_CHECK_RESP_CRC; + + sc->a10_intr = 0; + sc->a10_resid = 0; + sc->a10_intr_wait = A10_MMC_CMD_DONE; + cmd->error = MMC_ERR_NONE; + if (cmd->data != NULL) { + sc->a10_intr_wait |= A10_MMC_DATA_OVER; + cmdreg |= A10_MMC_DATA_EXP | A10_MMC_WAIT_PREOVER; + if (cmd->data->flags & MMC_DATA_MULTI) { + cmdreg |= A10_MMC_SEND_AUTOSTOP; + sc->a10_intr_wait |= A10_MMC_AUTOCMD_DONE; + } + if (cmd->data->flags & MMC_DATA_WRITE) + cmdreg |= A10_MMC_WRITE; + blksz = min(cmd->data->len, MMC_SECTOR_SIZE); + A10_MMC_WRITE_4(sc, A10_MMC_BLKSZ, blksz); + A10_MMC_WRITE_4(sc, A10_MMC_BCNTR, cmd->data->len); + } + + A10_MMC_WRITE_4(sc, A10_MMC_CARG, cmd->arg); + A10_MMC_WRITE_4(sc, A10_MMC_CMDR, cmdreg | cmd->opcode); + callout_reset(&sc->a10_timeoutc, sc->a10_timeout * hz, + a10_mmc_timeout, sc); + A10_MMC_UNLOCK(sc); + + return (0); +} + +static int +a10_mmc_read_ivar(device_t bus, device_t child, int which, + uintptr_t *result) +{ + struct a10_mmc_softc *sc; + + sc = device_get_softc(bus); + switch (which) { + default: + return (EINVAL); + case MMCBR_IVAR_BUS_MODE: + *(int *)result = sc->a10_host.ios.bus_mode; + break; + case MMCBR_IVAR_BUS_WIDTH: + *(int *)result = sc->a10_host.ios.bus_width; + break; + case MMCBR_IVAR_CHIP_SELECT: + *(int *)result = sc->a10_host.ios.chip_select; + break; + case MMCBR_IVAR_CLOCK: + *(int *)result = sc->a10_host.ios.clock; + break; + case MMCBR_IVAR_F_MIN: + *(int *)result = sc->a10_host.f_min; + break; + case MMCBR_IVAR_F_MAX: + *(int *)result = sc->a10_host.f_max; + break; + case MMCBR_IVAR_HOST_OCR: + *(int *)result = sc->a10_host.host_ocr; + break; + case MMCBR_IVAR_MODE: + *(int *)result = sc->a10_host.mode; + break; + case MMCBR_IVAR_OCR: + *(int *)result = sc->a10_host.ocr; + break; + case MMCBR_IVAR_POWER_MODE: + *(int *)result = sc->a10_host.ios.power_mode; + break; + case MMCBR_IVAR_VDD: + *(int *)result = sc->a10_host.ios.vdd; + break; + case MMCBR_IVAR_CAPS: + *(int *)result = sc->a10_host.caps; + break; + case MMCBR_IVAR_MAX_DATA: + *(int *)result = 65535; + break; + } + + return (0); +} + +static int +a10_mmc_write_ivar(device_t bus, device_t child, int which, + uintptr_t value) +{ + struct a10_mmc_softc *sc; + + sc = device_get_softc(bus); + switch (which) { + default: + return (EINVAL); + case MMCBR_IVAR_BUS_MODE: + sc->a10_host.ios.bus_mode = value; + break; + case MMCBR_IVAR_BUS_WIDTH: + sc->a10_host.ios.bus_width = value; + break; + case MMCBR_IVAR_CHIP_SELECT: + sc->a10_host.ios.chip_select = value; + break; + case MMCBR_IVAR_CLOCK: + sc->a10_host.ios.clock = value; + break; + case MMCBR_IVAR_MODE: + sc->a10_host.mode = value; + break; + case MMCBR_IVAR_OCR: + sc->a10_host.ocr = value; + break; + case MMCBR_IVAR_POWER_MODE: + sc->a10_host.ios.power_mode = value; + break; + case MMCBR_IVAR_VDD: + sc->a10_host.ios.vdd = value; + break; + /* These are read-only */ + case MMCBR_IVAR_CAPS: + case MMCBR_IVAR_HOST_OCR: + case MMCBR_IVAR_F_MIN: + case MMCBR_IVAR_F_MAX: + case MMCBR_IVAR_MAX_DATA: + return (EINVAL); + } + + return (0); +} + +static int +a10_mmc_update_clock(struct a10_mmc_softc *sc) +{ + uint32_t cmdreg; + int retry; + + cmdreg = A10_MMC_START | A10_MMC_UPCLK_ONLY | + A10_MMC_WAIT_PREOVER; + A10_MMC_WRITE_4(sc, A10_MMC_CMDR, cmdreg); + retry = 0xfffff; + while (--retry > 0) { + if ((A10_MMC_READ_4(sc, A10_MMC_CMDR) & A10_MMC_START) == 0) { + A10_MMC_WRITE_4(sc, A10_MMC_RINTR, 0xffffffff); + return (0); + } + DELAY(10); + } + A10_MMC_WRITE_4(sc, A10_MMC_RINTR, 0xffffffff); + device_printf(sc->a10_dev, "timeout updating clock\n"); + + return (ETIMEDOUT); +} + +static int +a10_mmc_update_ios(device_t bus, device_t child) +{ + int error; + struct a10_mmc_softc *sc; + struct mmc_ios *ios; + uint32_t clkcr; + + sc = device_get_softc(bus); + clkcr = A10_MMC_READ_4(sc, A10_MMC_CLKCR); + if (clkcr & A10_MMC_CARD_CLK_ON) { + /* Disable clock. */ + clkcr &= ~A10_MMC_CARD_CLK_ON; + A10_MMC_WRITE_4(sc, A10_MMC_CLKCR, clkcr); + error = a10_mmc_update_clock(sc); + if (error != 0) + return (error); + } + + ios = &sc->a10_host.ios; + if (ios->clock) { + /* Reset the divider. */ + clkcr &= ~A10_MMC_CLKCR_DIV; + A10_MMC_WRITE_4(sc, A10_MMC_CLKCR, clkcr); + error = a10_mmc_update_clock(sc); + if (error != 0) + return (error); + + /* Set the MMC clock. */ + error = a10_clk_mmc_cfg(sc->a10_id, ios->clock); + if (error != 0) + return (error); + + /* Enable clock. */ + clkcr |= A10_MMC_CARD_CLK_ON; + A10_MMC_WRITE_4(sc, A10_MMC_CLKCR, clkcr); + error = a10_mmc_update_clock(sc); + if (error != 0) + return (error); + } + + /* Set the bus width. */ + switch (ios->bus_width) { + case bus_width_1: + A10_MMC_WRITE_4(sc, A10_MMC_WIDTH, A10_MMC_WIDTH1); + break; + case bus_width_4: + A10_MMC_WRITE_4(sc, A10_MMC_WIDTH, A10_MMC_WIDTH4); + break; + case bus_width_8: + A10_MMC_WRITE_4(sc, A10_MMC_WIDTH, A10_MMC_WIDTH8); + break; + } + + return (0); +} + +static int +a10_mmc_get_ro(device_t bus, device_t child) +{ + + return (0); +} + +static int +a10_mmc_acquire_host(device_t bus, device_t child) +{ + struct a10_mmc_softc *sc; + int error; + + sc = device_get_softc(bus); + A10_MMC_LOCK(sc); + while (sc->a10_bus_busy) { + error = msleep(sc, &sc->a10_mtx, PCATCH, "mmchw", 0); + if (error != 0) { + A10_MMC_UNLOCK(sc); + return (error); + } + } + sc->a10_bus_busy++; + A10_MMC_UNLOCK(sc); + + return (0); +} + +static int +a10_mmc_release_host(device_t bus, device_t child) +{ + struct a10_mmc_softc *sc; + + sc = device_get_softc(bus); + A10_MMC_LOCK(sc); + sc->a10_bus_busy--; + wakeup(sc); + A10_MMC_UNLOCK(sc); + + return (0); +} + +static device_method_t a10_mmc_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, a10_mmc_probe), + DEVMETHOD(device_attach, a10_mmc_attach), + DEVMETHOD(device_detach, a10_mmc_detach), + + /* Bus interface */ + DEVMETHOD(bus_read_ivar, a10_mmc_read_ivar), + DEVMETHOD(bus_write_ivar, a10_mmc_write_ivar), + DEVMETHOD(bus_print_child, bus_generic_print_child), + + /* MMC bridge interface */ + DEVMETHOD(mmcbr_update_ios, a10_mmc_update_ios), + DEVMETHOD(mmcbr_request, a10_mmc_request), + DEVMETHOD(mmcbr_get_ro, a10_mmc_get_ro), + DEVMETHOD(mmcbr_acquire_host, a10_mmc_acquire_host), + DEVMETHOD(mmcbr_release_host, a10_mmc_release_host), + + DEVMETHOD_END +}; + +static devclass_t a10_mmc_devclass; + +static driver_t a10_mmc_driver = { + "a10_mmc", + a10_mmc_methods, + sizeof(struct a10_mmc_softc), +}; + +DRIVER_MODULE(a10_mmc, simplebus, a10_mmc_driver, a10_mmc_devclass, 0, 0); Property changes on: head/sys/arm/allwinner/a10_mmc.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/allwinner/a10_mmc.h =================================================================== --- head/sys/arm/allwinner/a10_mmc.h (nonexistent) +++ head/sys/arm/allwinner/a10_mmc.h (revision 283253) @@ -0,0 +1,179 @@ +/*- + * Copyright (c) 2013 Alexander Fedorov + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _A10_MMC_H_ +#define _A10_MMC_H_ + +#define A10_MMC_GCTRL 0x00 /* Global Control Register */ +#define A10_MMC_CLKCR 0x04 /* Clock Control Register */ +#define A10_MMC_TIMEOUT 0x08 /* Timeout Register */ +#define A10_MMC_WIDTH 0x0C /* Bus Width Register */ +#define A10_MMC_BLKSZ 0x10 /* Block Size Register */ +#define A10_MMC_BCNTR 0x14 /* Byte Count Register */ +#define A10_MMC_CMDR 0x18 /* Command Register */ +#define A10_MMC_CARG 0x1C /* Argument Register */ +#define A10_MMC_RESP0 0x20 /* Response Register 0 */ +#define A10_MMC_RESP1 0x24 /* Response Register 1 */ +#define A10_MMC_RESP2 0x28 /* Response Register 2 */ +#define A10_MMC_RESP3 0x2C /* Response Register 3 */ +#define A10_MMC_IMASK 0x30 /* Interrupt Mask Register */ +#define A10_MMC_MISTA 0x34 /* Masked Interrupt Status Register */ +#define A10_MMC_RINTR 0x38 /* Raw Interrupt Status Register */ +#define A10_MMC_STAS 0x3C /* Status Register */ +#define A10_MMC_FTRGL 0x40 /* FIFO Threshold Watermark Register */ +#define A10_MMC_FUNS 0x44 /* Function Select Register */ +#define A10_MMC_CBCR 0x48 /* CIU Byte Count Register */ +#define A10_MMC_BBCR 0x4C /* BIU Byte Count Register */ +#define A10_MMC_DBGC 0x50 /* Debug Enable Register */ +#define A10_MMC_DMAC 0x80 /* IDMAC Control Register */ +#define A10_MMC_DLBA 0x84 /* IDMAC Desc List Base Address Reg */ +#define A10_MMC_IDST 0x88 /* IDMAC Status Register */ +#define A10_MMC_IDIE 0x8C /* IDMAC Interrupt Enable Register */ +#define A10_MMC_CHDA 0x90 +#define A10_MMC_CBDA 0x94 +#define A10_MMC_FIFO 0x100 /* FIFO Access Address */ + +/* A10_MMC_GCTRL */ +#define A10_MMC_SOFT_RESET (1U << 0) +#define A10_MMC_FIFO_RESET (1U << 1) +#define A10_MMC_DMA_RESET (1U << 2) +#define A10_MMC_INT_ENABLE (1U << 4) +#define A10_MMC_DMA_ENABLE (1U << 5) +#define A10_MMC_DEBOUNCE_ENABLE (1U << 8) +#define A10_MMC_DDR_MODE (1U << 10) +#define A10_MMC_ACCESS_BY_DMA (1U << 30) +#define A10_MMC_ACCESS_BY_AHB (1U << 31) +#define A10_MMC_RESET \ + (A10_MMC_SOFT_RESET | A10_MMC_FIFO_RESET | A10_MMC_DMA_RESET) + +/* A10_MMC_CLKCR */ +#define A10_MMC_CARD_CLK_ON (1U << 16) +#define A10_MMC_LOW_POWER_ON (1U << 17) +#define A10_MMC_CLKCR_DIV 0xff + +/* A10_MMC_WIDTH */ +#define A10_MMC_WIDTH1 0 +#define A10_MMC_WIDTH4 1 +#define A10_MMC_WIDTH8 2 + +/* A10_MMC_CMDR */ +#define A10_MMC_RESP_EXP (1U << 6) +#define A10_MMC_LONG_RESP (1U << 7) +#define A10_MMC_CHECK_RESP_CRC (1U << 8) +#define A10_MMC_DATA_EXP (1U << 9) +#define A10_MMC_WRITE (1U << 10) +#define A10_MMC_SEQ_MODE (1U << 11) +#define A10_MMC_SEND_AUTOSTOP (1U << 12) +#define A10_MMC_WAIT_PREOVER (1U << 13) +#define A10_MMC_STOP_ABORT_CMD (1U << 14) +#define A10_MMC_SEND_INIT_SEQ (1U << 15) +#define A10_MMC_UPCLK_ONLY (1U << 21) +#define A10_MMC_RDCEATADEV (1U << 22) +#define A10_MMC_CCS_EXP (1U << 23) +#define A10_MMC_ENB_BOOT (1U << 24) +#define A10_MMC_ALT_BOOT_OPT (1U << 25) +#define A10_MMC_BOOT_ACK_EXP (1U << 26) +#define A10_MMC_DISABLE_BOOT (1U << 27) +#define A10_MMC_VOL_SWITCH (1U << 28) +#define A10_MMC_START (1U << 31) + +/* A10_MMC_IMASK and A10_MMC_RINTR */ +#define A10_MMC_RESP_ERR (1U << 1) +#define A10_MMC_CMD_DONE (1U << 2) +#define A10_MMC_DATA_OVER (1U << 3) +#define A10_MMC_TX_DATA_REQ (1U << 4) +#define A10_MMC_RX_DATA_REQ (1U << 5) +#define A10_MMC_RESP_CRC_ERR (1U << 6) +#define A10_MMC_DATA_CRC_ERR (1U << 7) +#define A10_MMC_RESP_TIMEOUT (1U << 8) +#define A10_MMC_ACK_RECV (1U << 8) +#define A10_MMC_DATA_TIMEOUT (1U << 9) +#define A10_MMC_BOOT_START (1U << 9) +#define A10_MMC_DATA_STARVE (1U << 10) +#define A10_MMC_VOL_CHG_DONE (1U << 10) +#define A10_MMC_FIFO_RUN_ERR (1U << 11) +#define A10_MMC_HARDW_LOCKED (1U << 12) +#define A10_MMC_START_BIT_ERR (1U << 13) +#define A10_MMC_AUTOCMD_DONE (1U << 14) +#define A10_MMC_END_BIT_ERR (1U << 15) +#define A10_MMC_SDIO_INT (1U << 16) +#define A10_MMC_CARD_INSERT (1U << 30) +#define A10_MMC_CARD_REMOVE (1U << 31) +#define A10_MMC_INT_ERR_BIT \ + (A10_MMC_RESP_ERR | A10_MMC_RESP_CRC_ERR | \ + A10_MMC_DATA_CRC_ERR | A10_MMC_RESP_TIMEOUT | \ + A10_MMC_FIFO_RUN_ERR | A10_MMC_HARDW_LOCKED | \ + A10_MMC_START_BIT_ERR | A10_MMC_END_BIT_ERR) + +/* A10_MMC_STAS */ +#define A10_MMC_RX_WLFLAG (1U << 0) +#define A10_MMC_TX_WLFLAG (1U << 1) +#define A10_MMC_FIFO_EMPTY (1U << 2) +#define A10_MMC_FIFO_FULL (1U << 3) +#define A10_MMC_CARD_PRESENT (1U << 8) +#define A10_MMC_CARD_DATA_BUSY (1U << 9) +#define A10_MMC_DATA_FSM_BUSY (1U << 10) +#define A10_MMC_DMA_REQ (1U << 31) +#define A10_MMC_FIFO_SIZE 16 + +/* A10_MMC_FUNS */ +#define A10_MMC_CE_ATA_ON (0xceaaU << 16) +#define A10_MMC_SEND_IRQ_RESP (1U << 0) +#define A10_MMC_SDIO_RD_WAIT (1U << 1) +#define A10_MMC_ABT_RD_DATA (1U << 2) +#define A10_MMC_SEND_CC_SD (1U << 8) +#define A10_MMC_SEND_AUTOSTOP_CC_SD (1U << 9) +#define A10_MMC_CE_ATA_DEV_INT_ENB (1U << 10) + +/* IDMA CONTROLLER BUS MOD BIT FIELD */ +#define A10_MMC_IDMAC_SOFT_RST (1U << 0) +#define A10_MMC_IDMAC_FIX_BURST (1U << 1) +#define A10_MMC_IDMAC_IDMA_ON (1U << 7) +#define A10_MMC_IDMAC_REFETCH_DES (1U << 31) + +/* A10_MMC_IDST */ +#define A10_MMC_IDMAC_TRANSMIT_INT (1U << 0) +#define A10_MMC_IDMAC_RECEIVE_INT (1U << 1) +#define A10_MMC_IDMAC_FATAL_BUS_ERR (1U << 2) +#define A10_MMC_IDMAC_DES_INVALID (1U << 4) +#define A10_MMC_IDMAC_CARD_ERR_SUM (1U << 5) +#define A10_MMC_IDMAC_NORMAL_INT_SUM (1U << 8) +#define A10_MMC_IDMAC_ABNORMAL_INT_SUM (1U << 9) +#define A10_MMC_IDMAC_HOST_ABT_INTX (1U << 10) +#define A10_MMC_IDMAC_HOST_ABT_INRX (1U << 10) +#define A10_MMC_IDMAC_IDLE (0U << 13) +#define A10_MMC_IDMAC_SUSPEND (1U << 13) +#define A10_MMC_IDMAC_DESC_RD (2U << 13) +#define A10_MMC_IDMAC_DESC_CHECK (3U << 13) +#define A10_MMC_IDMAC_RD_REQ_WAIT (4U << 13) +#define A10_MMC_IDMAC_WR_REQ_WAIT (5U << 13) +#define A10_MMC_IDMAC_RD (6U << 13) +#define A10_MMC_IDMAC_WR (7U << 13) +#define A10_MMC_IDMAC_DESC_CLOSE (8U << 13) + +#endif /* _A10_MMC_H_ */ Property changes on: head/sys/arm/allwinner/a10_mmc.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/allwinner/files.allwinner =================================================================== --- head/sys/arm/allwinner/files.allwinner (revision 283252) +++ head/sys/arm/allwinner/files.allwinner (revision 283253) @@ -1,18 +1,19 @@ # $FreeBSD$ kern/kern_clocksource.c standard arm/arm/bus_space_base.c standard arm/arm/bus_space_asm_generic.S standard arm/arm/bus_space_generic.c standard arm/allwinner/a10_clk.c standard arm/allwinner/a10_common.c standard arm/allwinner/a10_ehci.c optional ehci arm/allwinner/a10_gpio.c optional gpio arm/allwinner/a10_machdep.c standard +arm/allwinner/a10_mmc.c optional mmc arm/allwinner/a10_sramc.c standard arm/allwinner/a10_wdog.c standard arm/allwinner/a20/a20_cpu_cfg.c standard arm/allwinner/if_emac.c optional emac arm/allwinner/timer.c standard #arm/allwinner/console.c standard Index: head/sys/arm/conf/CUBIEBOARD =================================================================== --- head/sys/arm/conf/CUBIEBOARD (revision 283252) +++ head/sys/arm/conf/CUBIEBOARD (revision 283253) @@ -1,110 +1,110 @@ # # CUBIEBOARD -- Custom configuration for the CUBIEBOARD ARM development # platform, check out http://www.cubieboard.org # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ ident CUBIEBOARD include "std.armv6" include "../allwinner/std.a10" options HZ=100 options SCHED_4BSD # 4BSD scheduler # Debugging for use in -current makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols options BREAK_TO_DEBUGGER #options VERBOSE_SYSINIT # Enable verbose sysinit messages options KDB # Enable kernel debugger support # For minimum debugger support (stable branch) use: #options KDB_TRACE # Print a stack trace for a panic # For full debugger support use this instead: options DDB # Enable the kernel debugger options INVARIANTS # Enable calls of extra sanity checking options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS options WITNESS # Enable checks to detect deadlocks and cycles options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed #options DIAGNOSTIC # NFS root from boopt/dhcp #options BOOTP #options BOOTP_NFSROOT #options BOOTP_COMPAT #options BOOTP_NFSV3 #options BOOTP_WIRED_TO=cpsw0 # Boot device is 2nd slice on MMC/SD card options ROOTDEVNAME=\"ufs:/dev/da0s2\" # MMC/SD/SDIO Card slot support -#device mmc # mmc/sd bus -#device mmcsd # mmc/sd flash cards +device mmc # mmc/sd bus +device mmcsd # mmc/sd flash cards # ATA controllers #device ahci # AHCI-compatible SATA controllers #device ata # Legacy ATA/SATA controllers #options ATA_STATIC_ID # Static device numbering # Console and misc device uart device uart_ns8250 device pty device snp device md device random # Entropy device # I2C support #device iicbus #device iic # GPIO device gpio device scbus # SCSI bus (required for ATA/SCSI) device da # Direct Access (disks) device pass # USB support options USB_HOST_ALIGN=64 # Align usb buffers to cache line size. device usb options USB_DEBUG #options USB_REQ_DEBUG #options USB_VERBOSE #device uhci #device ohci device ehci device umass # Ethernet device loop device ether device mii device bpf device emac # USB ethernet support, requires miibus device miibus # Flattened Device Tree options FDT # Configure using FDT/DTB data options FDT_DTB_STATIC makeoptions FDT_DTS_FILE=cubieboard.dts makeoptions MODULES_EXTRA=dtb/allwinner Index: head/sys/arm/conf/CUBIEBOARD2 =================================================================== --- head/sys/arm/conf/CUBIEBOARD2 (revision 283252) +++ head/sys/arm/conf/CUBIEBOARD2 (revision 283253) @@ -1,114 +1,114 @@ # # CUBIEBOARD2 -- Custom configuration for the CUBIEBOARD2 ARM development # platform, check out http://www.cubieboard.org # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ ident CUBIEBOARD2 include "std.armv6" include "../allwinner/a20/std.a20" options HZ=100 options SCHED_ULE # ULE scheduler options SMP # Enable multiple cores # Debugging for use in -current makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols options BREAK_TO_DEBUGGER #options VERBOSE_SYSINIT # Enable verbose sysinit messages options KDB # Enable kernel debugger support # For minimum debugger support (stable branch) use: #options KDB_TRACE # Print a stack trace for a panic # For full debugger support use this instead: options DDB # Enable the kernel debugger options INVARIANTS # Enable calls of extra sanity checking options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS options WITNESS # Enable checks to detect deadlocks and cycles options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed #options DIAGNOSTIC # NFS root from boopt/dhcp #options BOOTP #options BOOTP_NFSROOT #options BOOTP_COMPAT #options BOOTP_NFSV3 #options BOOTP_WIRED_TO=cpsw0 # Boot device is 2nd slice on MMC/SD card options ROOTDEVNAME=\"ufs:/dev/da0s2\" # Interrupt controller device gic # MMC/SD/SDIO Card slot support -#device mmc # mmc/sd bus -#device mmcsd # mmc/sd flash cards +device mmc # mmc/sd bus +device mmcsd # mmc/sd flash cards # ATA controllers #device ahci # AHCI-compatible SATA controllers #device ata # Legacy ATA/SATA controllers #options ATA_STATIC_ID # Static device numbering # Console and misc device uart device uart_ns8250 device pty device snp device md device random # Entropy device # I2C support #device iicbus #device iic # GPIO device gpio device scbus # SCSI bus (required for ATA/SCSI) device da # Direct Access (disks) device pass # USB support options USB_HOST_ALIGN=64 # Align usb buffers to cache line size. device usb options USB_DEBUG #options USB_REQ_DEBUG #options USB_VERBOSE #device uhci #device ohci device ehci device umass # Ethernet device loop device ether device mii device bpf device emac # USB ethernet support, requires miibus device miibus # Flattened Device Tree options FDT # Configure using FDT/DTB data options FDT_DTB_STATIC makeoptions FDT_DTS_FILE=cubieboard2.dts makeoptions MODULES_EXTRA=dtb/allwinner Index: head/sys/boot/fdt/dts/arm/cubieboard.dts =================================================================== --- head/sys/boot/fdt/dts/arm/cubieboard.dts (revision 283252) +++ head/sys/boot/fdt/dts/arm/cubieboard.dts (revision 283253) @@ -1,71 +1,75 @@ /*- * Copyright (c) 2012 Ganbold Tsagaankhuu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /dts-v1/; /include/ "sun4i-a10.dtsi" / { model = "Cubietech Cubieboard"; memory { device_type = "memory"; reg = < 0x40000000 0x40000000 >; /* 1GB RAM */ }; aliases { soc = &SOC; UART0 = &UART0; }; SOC: a10 { usb1: usb@01c14000 { status = "okay"; }; usb2: usb@01c1c000 { status = "okay"; }; UART0: serial@01c28000 { status = "okay"; }; + mmc0: mmc@01c0f000 { + status = "okay"; + }; + emac@01c0b000 { status = "okay"; }; }; chosen { bootargs = "-v"; stdin = "UART0"; stdout = "UART0"; }; }; Index: head/sys/boot/fdt/dts/arm/cubieboard2.dts =================================================================== --- head/sys/boot/fdt/dts/arm/cubieboard2.dts (revision 283252) +++ head/sys/boot/fdt/dts/arm/cubieboard2.dts (revision 283253) @@ -1,75 +1,79 @@ /*- * Copyright (c) 2013 Ganbold Tsagaankhuu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /dts-v1/; /include/ "sun7i-a20.dtsi" / { model = "Cubietech Cubieboard2"; memory { device_type = "memory"; reg = < 0x40000000 0x40000000 >; /* 1GB RAM */ }; aliases { soc = &SOC; UART0 = &UART0; }; SOC: a20 { usb1: usb@01c14000 { status = "okay"; }; usb2: usb@01c1c000 { status = "okay"; }; UART0: serial@01c28000 { status = "okay"; }; + mmc0: mmc@01c0f000 { + status = "okay"; + }; + emac@01c0b000 { status = "okay"; }; ahci: sata@01c18000 { status = "okay"; }; }; chosen { bootargs = "-v"; stdin = "UART0"; stdout = "UART0"; }; }; Index: head/sys/boot/fdt/dts/arm/sun4i-a10.dtsi =================================================================== --- head/sys/boot/fdt/dts/arm/sun4i-a10.dtsi (revision 283252) +++ head/sys/boot/fdt/dts/arm/sun4i-a10.dtsi (revision 283253) @@ -1,133 +1,141 @@ /*- * Copyright (c) 2014 Ganbold Tsagaankhuu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ / { compatible = "allwinner,sun4i-a10"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&AINTC>; aliases { soc = &SOC; }; SOC: a10 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; ranges; bus-frequency = <0>; AINTC: interrupt-controller@01c20400 { compatible = "allwinner,sun4i-ic"; interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; reg = < 0x01c20400 0x400 >; }; sramc@01c00000 { compatible = "allwinner,sun4i-sramc"; #address-cells = <1>; #size-cells = <1>; reg = < 0x01c00000 0x1000 >; }; ccm@01c20000 { compatible = "allwinner,sun4i-ccm"; #address-cells = <1>; #size-cells = <1>; reg = < 0x01c20000 0x400 >; }; timer@01c20c00 { compatible = "allwinner,sun4i-timer"; reg = <0x01c20c00 0x90>; interrupts = < 22 >; interrupt-parent = <&AINTC>; clock-frequency = < 24000000 >; }; watchdog@01c20c90 { compatible = "allwinner,sun4i-wdt"; reg = <0x01c20c90 0x08>; }; GPIO: gpio@01c20800 { #gpio-cells = <3>; compatible = "allwinner,sun4i-gpio"; gpio-controller; reg =< 0x01c20800 0x400 >; interrupts = < 28 >; interrupt-parent = <&AINTC>; }; usb1: usb@01c14000 { compatible = "allwinner,usb-ehci", "usb-ehci"; reg = <0x01c14000 0x1000>; interrupts = < 39 >; interrupt-parent = <&AINTC>; }; usb2: usb@01c1c000 { compatible = "allwinner,usb-ehci", "usb-ehci"; reg = <0x01c1c000 0x1000>; interrupts = < 40 >; interrupt-parent = <&AINTC>; }; + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun4i-a10-mmc"; + reg = <0x01c0f000 0x1000>; + interrupts = <32>; + interrupt-parent = <&AINTC>; + status = "disabled"; + }; + sata@01c18000 { compatible = "allwinner,sun4i-ahci"; reg = <0x01c18000 0x1000>; interrupts = <56>; interrupt-parent = <&AINTC>; }; UART0: serial@01c28000 { compatible = "ns16550"; reg = <0x01c28000 0x400>; reg-shift = <2>; interrupts = <1>; interrupt-parent = <&AINTC>; current-speed = <115200>; clock-frequency = < 24000000 >; busy-detect = <1>; broken-txfifo = <1>; }; emac@01c0b000 { compatible = "allwinner,sun4i-emac"; reg = <0x01c0b000 0x1000>; interrupts = <55>; interrupt-parent = <&AINTC>; }; }; }; Index: head/sys/boot/fdt/dts/arm/sun7i-a20.dtsi =================================================================== --- head/sys/boot/fdt/dts/arm/sun7i-a20.dtsi (revision 283252) +++ head/sys/boot/fdt/dts/arm/sun7i-a20.dtsi (revision 283253) @@ -1,139 +1,147 @@ /*- * Copyright (c) 2014 Ganbold Tsagaankhuu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ / { compatible = "allwinner,sun7i-a20"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&GIC>; aliases { soc = &SOC; }; SOC: a20 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; ranges; bus-frequency = <0>; GIC: interrupt-controller@01c81000 { compatible = "arm,gic"; reg = <0x01c81000 0x1000>, /* Distributor Registers */ <0x01c82000 0x0100>; /* CPU Interface Registers */ interrupt-controller; #interrupt-cells = <1>; }; sramc@01c00000 { compatible = "allwinner,sun4i-sramc"; #address-cells = <1>; #size-cells = <1>; reg = < 0x01c00000 0x1000 >; }; cpu-cfg@01c25c00 { compatible = "allwinner,sun7i-cpu-cfg"; #address-cells = <1>; #size-cells = <1>; reg = < 0x01c25c00 0x400 >; }; ccm@01c20000 { compatible = "allwinner,sun4i-ccm"; #address-cells = <1>; #size-cells = <1>; reg = < 0x01c20000 0x400 >; }; timer@01c20c00 { compatible = "allwinner,sun7i-timer"; reg = <0x01c20c00 0x90>; interrupts = < 22 >; interrupt-parent = <&GIC>; clock-frequency = < 24000000 >; }; watchdog@01c20c90 { compatible = "allwinner,sun4i-wdt"; reg = <0x01c20c90 0x10>; }; GPIO: gpio@01c20800 { #gpio-cells = <3>; compatible = "allwinner,sun4i-gpio"; gpio-controller; reg =< 0x01c20800 0x400 >; interrupts = < 28 >; interrupt-parent = <&GIC>; }; usb1: usb@01c14000 { compatible = "allwinner,usb-ehci", "usb-ehci"; reg = <0x01c14000 0x1000>; interrupts = < 39 >; interrupt-parent = <&GIC>; }; usb2: usb@01c1c000 { compatible = "allwinner,usb-ehci", "usb-ehci"; reg = <0x01c1c000 0x1000>; interrupts = < 40 >; interrupt-parent = <&GIC>; }; + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun4i-a10-mmc"; + reg = <0x01c0f000 0x1000>; + interrupts = <32>; + interrupt-parent = <&GIC>; + status = "disabled"; + }; + sata@01c18000 { compatible = "allwinner,sun4i-a10-ahci"; reg = <0x01c18000 0x1000>; interrupts = <56>; interrupt-parent = <&GIC>; }; UART0: serial@01c28000 { compatible = "ns16550"; reg = <0x01c28000 0x400>; reg-shift = <2>; interrupts = <1>; interrupt-parent = <&GIC>; current-speed = <115200>; clock-frequency = < 24000000 >; busy-detect = <1>; broken-txfifo = <1>; }; emac@01c0b000 { compatible = "allwinner,sun4i-emac"; reg = <0x01c0b000 0x1000>; interrupts = <55>; interrupt-parent = <&GIC>; }; }; }; Index: head/sys/dev/mmc/mmc.c =================================================================== --- head/sys/dev/mmc/mmc.c (revision 283252) +++ head/sys/dev/mmc/mmc.c (revision 283253) @@ -1,1824 +1,1824 @@ /*- * Copyright (c) 2006 Bernd Walter. All rights reserved. * Copyright (c) 2006 M. Warner Losh. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Portions of this software may have been developed with reference to * the SD Simplified Specification. The following disclaimer may apply: * * The following conditions apply to the release of the simplified * specification ("Simplified Specification") by the SD Card Association and * the SD Group. The Simplified Specification is a subset of the complete SD * Specification which is owned by the SD Card Association and the SD * Group. This Simplified Specification is provided on a non-confidential * basis subject to the disclaimers below. Any implementation of the * Simplified Specification may require a license from the SD Card * Association, SD Group, SD-3C LLC or other third parties. * * Disclaimers: * * The information contained in the Simplified Specification is presented only * as a standard specification for SD Cards and SD Host/Ancillary products and * is provided "AS-IS" without any representations or warranties of any * kind. No responsibility is assumed by the SD Group, SD-3C LLC or the SD * Card Association for any damages, any infringements of patents or other * right of the SD Group, SD-3C LLC, the SD Card Association or any third * parties, which may result from its use. No license is granted by * implication, estoppel or otherwise under any patent or other rights of the * SD Group, SD-3C LLC, the SD Card Association or any third party. Nothing * herein shall be construed as an obligation by the SD Group, the SD-3C LLC * or the SD Card Association to disclose or distribute any technical * information, know-how or other confidential information to any third party. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "mmcbr_if.h" #include "mmcbus_if.h" struct mmc_softc { device_t dev; struct mtx sc_mtx; struct intr_config_hook config_intrhook; device_t owner; uint32_t last_rca; int squelched; /* suppress reporting of (expected) errors */ int log_count; struct timeval log_time; }; #define LOG_PPS 5 /* Log no more than 5 errors per second. */ /* * Per-card data */ struct mmc_ivars { uint32_t raw_cid[4]; /* Raw bits of the CID */ uint32_t raw_csd[4]; /* Raw bits of the CSD */ uint32_t raw_scr[2]; /* Raw bits of the SCR */ uint8_t raw_ext_csd[512]; /* Raw bits of the EXT_CSD */ uint32_t raw_sd_status[16]; /* Raw bits of the SD_STATUS */ uint16_t rca; enum mmc_card_mode mode; struct mmc_cid cid; /* cid decoded */ struct mmc_csd csd; /* csd decoded */ struct mmc_scr scr; /* scr decoded */ struct mmc_sd_status sd_status; /* SD_STATUS decoded */ u_char read_only; /* True when the device is read-only */ u_char bus_width; /* Bus width to use */ u_char timing; /* Bus timing support */ u_char high_cap; /* High Capacity card (block addressed) */ uint32_t sec_count; /* Card capacity in 512byte blocks */ uint32_t tran_speed; /* Max speed in normal mode */ uint32_t hs_tran_speed; /* Max speed in high speed mode */ uint32_t erase_sector; /* Card native erase sector size */ char card_id_string[64];/* Formatted CID info (serial, MFG, etc) */ char card_sn_string[16];/* Formatted serial # for disk->d_ident */ }; #define CMD_RETRIES 3 #define CARD_ID_FREQUENCY 400000 /* Spec requires 400kHz max during ID phase. */ static SYSCTL_NODE(_hw, OID_AUTO, mmc, CTLFLAG_RD, NULL, "mmc driver"); static int mmc_debug; SYSCTL_INT(_hw_mmc, OID_AUTO, debug, CTLFLAG_RW, &mmc_debug, 0, "Debug level"); /* bus entry points */ static int mmc_acquire_bus(device_t busdev, device_t dev); static int mmc_attach(device_t dev); static int mmc_child_location_str(device_t dev, device_t child, char *buf, size_t buflen); static int mmc_detach(device_t dev); static int mmc_probe(device_t dev); static int mmc_read_ivar(device_t bus, device_t child, int which, uintptr_t *result); static int mmc_release_bus(device_t busdev, device_t dev); static int mmc_resume(device_t dev); static int mmc_suspend(device_t dev); static int mmc_wait_for_request(device_t brdev, device_t reqdev, struct mmc_request *req); static int mmc_write_ivar(device_t bus, device_t child, int which, uintptr_t value); #define MMC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) #define MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) #define MMC_LOCK_INIT(_sc) \ mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ "mmc", MTX_DEF) #define MMC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); #define MMC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); #define MMC_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); static int mmc_all_send_cid(struct mmc_softc *sc, uint32_t *rawcid); static void mmc_app_decode_scr(uint32_t *raw_scr, struct mmc_scr *scr); static void mmc_app_decode_sd_status(uint32_t *raw_sd_status, struct mmc_sd_status *sd_status); static int mmc_app_sd_status(struct mmc_softc *sc, uint16_t rca, uint32_t *rawsdstatus); static int mmc_app_send_scr(struct mmc_softc *sc, uint16_t rca, uint32_t *rawscr); static int mmc_calculate_clock(struct mmc_softc *sc); static void mmc_decode_cid_mmc(uint32_t *raw_cid, struct mmc_cid *cid); static void mmc_decode_cid_sd(uint32_t *raw_cid, struct mmc_cid *cid); static void mmc_decode_csd_mmc(uint32_t *raw_csd, struct mmc_csd *csd); static void mmc_decode_csd_sd(uint32_t *raw_csd, struct mmc_csd *csd); static void mmc_delayed_attach(void *xsc); static int mmc_delete_cards(struct mmc_softc *sc); static void mmc_discover_cards(struct mmc_softc *sc); static void mmc_format_card_id_string(struct mmc_ivars *ivar); static void mmc_go_discovery(struct mmc_softc *sc); static uint32_t mmc_get_bits(uint32_t *bits, int bit_len, int start, int size); static int mmc_highest_voltage(uint32_t ocr); static void mmc_idle_cards(struct mmc_softc *sc); static void mmc_ms_delay(int ms); static void mmc_log_card(device_t dev, struct mmc_ivars *ivar, int newcard); static void mmc_power_down(struct mmc_softc *sc); static void mmc_power_up(struct mmc_softc *sc); static void mmc_rescan_cards(struct mmc_softc *sc); static void mmc_scan(struct mmc_softc *sc); static int mmc_sd_switch(struct mmc_softc *sc, uint8_t mode, uint8_t grp, uint8_t value, uint8_t *res); static int mmc_select_card(struct mmc_softc *sc, uint16_t rca); static uint32_t mmc_select_vdd(struct mmc_softc *sc, uint32_t ocr); static int mmc_send_app_op_cond(struct mmc_softc *sc, uint32_t ocr, uint32_t *rocr); static int mmc_send_csd(struct mmc_softc *sc, uint16_t rca, uint32_t *rawcsd); static int mmc_send_ext_csd(struct mmc_softc *sc, uint8_t *rawextcsd); static int mmc_send_if_cond(struct mmc_softc *sc, uint8_t vhs); static int mmc_send_op_cond(struct mmc_softc *sc, uint32_t ocr, uint32_t *rocr); static int mmc_send_relative_addr(struct mmc_softc *sc, uint32_t *resp); static int mmc_send_status(struct mmc_softc *sc, uint16_t rca, uint32_t *status); static int mmc_set_blocklen(struct mmc_softc *sc, uint32_t len); static int mmc_set_card_bus_width(struct mmc_softc *sc, uint16_t rca, int width); static int mmc_set_relative_addr(struct mmc_softc *sc, uint16_t resp); static int mmc_set_timing(struct mmc_softc *sc, int timing); static int mmc_switch(struct mmc_softc *sc, uint8_t set, uint8_t index, uint8_t value); static int mmc_test_bus_width(struct mmc_softc *sc); static int mmc_wait_for_app_cmd(struct mmc_softc *sc, uint32_t rca, struct mmc_command *cmd, int retries); static int mmc_wait_for_cmd(struct mmc_softc *sc, struct mmc_command *cmd, int retries); static int mmc_wait_for_command(struct mmc_softc *sc, uint32_t opcode, uint32_t arg, uint32_t flags, uint32_t *resp, int retries); static int mmc_wait_for_req(struct mmc_softc *sc, struct mmc_request *req); static void mmc_wakeup(struct mmc_request *req); static void mmc_ms_delay(int ms) { DELAY(1000 * ms); /* XXX BAD */ } static int mmc_probe(device_t dev) { device_set_desc(dev, "MMC/SD bus"); return (0); } static int mmc_attach(device_t dev) { struct mmc_softc *sc; sc = device_get_softc(dev); sc->dev = dev; MMC_LOCK_INIT(sc); /* We'll probe and attach our children later, but before / mount */ sc->config_intrhook.ich_func = mmc_delayed_attach; sc->config_intrhook.ich_arg = sc; if (config_intrhook_establish(&sc->config_intrhook) != 0) device_printf(dev, "config_intrhook_establish failed\n"); return (0); } static int mmc_detach(device_t dev) { struct mmc_softc *sc = device_get_softc(dev); int err; if ((err = mmc_delete_cards(sc)) != 0) return (err); mmc_power_down(sc); MMC_LOCK_DESTROY(sc); return (0); } static int mmc_suspend(device_t dev) { struct mmc_softc *sc = device_get_softc(dev); int err; err = bus_generic_suspend(dev); if (err) return (err); mmc_power_down(sc); return (0); } static int mmc_resume(device_t dev) { struct mmc_softc *sc = device_get_softc(dev); mmc_scan(sc); return (bus_generic_resume(dev)); } static int mmc_acquire_bus(device_t busdev, device_t dev) { struct mmc_softc *sc; struct mmc_ivars *ivar; int err; int rca; err = MMCBR_ACQUIRE_HOST(device_get_parent(busdev), busdev); if (err) return (err); sc = device_get_softc(busdev); MMC_LOCK(sc); if (sc->owner) panic("mmc: host bridge didn't serialize us."); sc->owner = dev; MMC_UNLOCK(sc); if (busdev != dev) { /* * Keep track of the last rca that we've selected. If * we're asked to do it again, don't. We never * unselect unless the bus code itself wants the mmc * bus, and constantly reselecting causes problems. */ rca = mmc_get_rca(dev); if (sc->last_rca != rca) { mmc_select_card(sc, rca); sc->last_rca = rca; /* Prepare bus width for the new card. */ ivar = device_get_ivars(dev); if (bootverbose || mmc_debug) { device_printf(busdev, "setting bus width to %d bits\n", (ivar->bus_width == bus_width_4) ? 4 : (ivar->bus_width == bus_width_8) ? 8 : 1); } mmc_set_card_bus_width(sc, rca, ivar->bus_width); mmcbr_set_bus_width(busdev, ivar->bus_width); mmcbr_update_ios(busdev); } } else { /* * If there's a card selected, stand down. */ if (sc->last_rca != 0) { mmc_select_card(sc, 0); sc->last_rca = 0; } } return (0); } static int mmc_release_bus(device_t busdev, device_t dev) { struct mmc_softc *sc; int err; sc = device_get_softc(busdev); MMC_LOCK(sc); if (!sc->owner) panic("mmc: releasing unowned bus."); if (sc->owner != dev) panic("mmc: you don't own the bus. game over."); MMC_UNLOCK(sc); err = MMCBR_RELEASE_HOST(device_get_parent(busdev), busdev); if (err) return (err); MMC_LOCK(sc); sc->owner = NULL; MMC_UNLOCK(sc); return (0); } static uint32_t mmc_select_vdd(struct mmc_softc *sc, uint32_t ocr) { return (ocr & MMC_OCR_VOLTAGE); } static int mmc_highest_voltage(uint32_t ocr) { int i; for (i = MMC_OCR_MAX_VOLTAGE_SHIFT; i >= MMC_OCR_MIN_VOLTAGE_SHIFT; i--) if (ocr & (1 << i)) return (i); return (-1); } static void mmc_wakeup(struct mmc_request *req) { struct mmc_softc *sc; sc = (struct mmc_softc *)req->done_data; MMC_LOCK(sc); req->flags |= MMC_REQ_DONE; MMC_UNLOCK(sc); wakeup(req); } static int mmc_wait_for_req(struct mmc_softc *sc, struct mmc_request *req) { req->done = mmc_wakeup; req->done_data = sc; if (mmc_debug > 1) { device_printf(sc->dev, "REQUEST: CMD%d arg %#x flags %#x", req->cmd->opcode, req->cmd->arg, req->cmd->flags); if (req->cmd->data) { printf(" data %d\n", (int)req->cmd->data->len); } else printf("\n"); } MMCBR_REQUEST(device_get_parent(sc->dev), sc->dev, req); MMC_LOCK(sc); while ((req->flags & MMC_REQ_DONE) == 0) msleep(req, &sc->sc_mtx, 0, "mmcreq", 0); MMC_UNLOCK(sc); if (mmc_debug > 2 || (mmc_debug > 0 && req->cmd->error != MMC_ERR_NONE)) device_printf(sc->dev, "CMD%d RESULT: %d\n", req->cmd->opcode, req->cmd->error); return (0); } static int mmc_wait_for_request(device_t brdev, device_t reqdev, struct mmc_request *req) { struct mmc_softc *sc = device_get_softc(brdev); return (mmc_wait_for_req(sc, req)); } static int mmc_wait_for_cmd(struct mmc_softc *sc, struct mmc_command *cmd, int retries) { struct mmc_request mreq; int err; do { memset(&mreq, 0, sizeof(mreq)); memset(cmd->resp, 0, sizeof(cmd->resp)); cmd->retries = 0; /* Retries done here, not in hardware. */ cmd->mrq = &mreq; mreq.cmd = cmd; if (mmc_wait_for_req(sc, &mreq) != 0) err = MMC_ERR_FAILED; else err = cmd->error; } while (err != MMC_ERR_NONE && retries-- > 0); if (err != MMC_ERR_NONE && sc->squelched == 0) { if (ppsratecheck(&sc->log_time, &sc->log_count, LOG_PPS)) { device_printf(sc->dev, "CMD%d failed, RESULT: %d\n", cmd->opcode, err); } } return (err); } static int mmc_wait_for_app_cmd(struct mmc_softc *sc, uint32_t rca, struct mmc_command *cmd, int retries) { struct mmc_command appcmd; int err; /* Squelch error reporting at lower levels, we report below. */ sc->squelched++; do { memset(&appcmd, 0, sizeof(appcmd)); appcmd.opcode = MMC_APP_CMD; appcmd.arg = rca << 16; appcmd.flags = MMC_RSP_R1 | MMC_CMD_AC; appcmd.data = NULL; if (mmc_wait_for_cmd(sc, &appcmd, 0) != 0) err = MMC_ERR_FAILED; else err = appcmd.error; if (err == MMC_ERR_NONE) { if (!(appcmd.resp[0] & R1_APP_CMD)) err = MMC_ERR_FAILED; else if (mmc_wait_for_cmd(sc, cmd, 0) != 0) err = MMC_ERR_FAILED; else err = cmd->error; } } while (err != MMC_ERR_NONE && retries-- > 0); sc->squelched--; if (err != MMC_ERR_NONE && sc->squelched == 0) { if (ppsratecheck(&sc->log_time, &sc->log_count, LOG_PPS)) { device_printf(sc->dev, "ACMD%d failed, RESULT: %d\n", cmd->opcode, err); } } return (err); } static int mmc_wait_for_command(struct mmc_softc *sc, uint32_t opcode, uint32_t arg, uint32_t flags, uint32_t *resp, int retries) { struct mmc_command cmd; int err; memset(&cmd, 0, sizeof(cmd)); cmd.opcode = opcode; cmd.arg = arg; cmd.flags = flags; cmd.data = NULL; err = mmc_wait_for_cmd(sc, &cmd, retries); if (err) return (err); if (resp) { if (flags & MMC_RSP_136) memcpy(resp, cmd.resp, 4 * sizeof(uint32_t)); else *resp = cmd.resp[0]; } return (0); } static void mmc_idle_cards(struct mmc_softc *sc) { device_t dev; struct mmc_command cmd; dev = sc->dev; mmcbr_set_chip_select(dev, cs_high); mmcbr_update_ios(dev); mmc_ms_delay(1); memset(&cmd, 0, sizeof(cmd)); cmd.opcode = MMC_GO_IDLE_STATE; cmd.arg = 0; cmd.flags = MMC_RSP_NONE | MMC_CMD_BC; cmd.data = NULL; mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); mmc_ms_delay(1); mmcbr_set_chip_select(dev, cs_dontcare); mmcbr_update_ios(dev); mmc_ms_delay(1); } static int mmc_send_app_op_cond(struct mmc_softc *sc, uint32_t ocr, uint32_t *rocr) { struct mmc_command cmd; int err = MMC_ERR_NONE, i; memset(&cmd, 0, sizeof(cmd)); cmd.opcode = ACMD_SD_SEND_OP_COND; cmd.arg = ocr; cmd.flags = MMC_RSP_R3 | MMC_CMD_BCR; cmd.data = NULL; for (i = 0; i < 1000; i++) { err = mmc_wait_for_app_cmd(sc, 0, &cmd, CMD_RETRIES); if (err != MMC_ERR_NONE) break; if ((cmd.resp[0] & MMC_OCR_CARD_BUSY) || (ocr & MMC_OCR_VOLTAGE) == 0) break; err = MMC_ERR_TIMEOUT; mmc_ms_delay(10); } if (rocr && err == MMC_ERR_NONE) *rocr = cmd.resp[0]; return (err); } static int mmc_send_op_cond(struct mmc_softc *sc, uint32_t ocr, uint32_t *rocr) { struct mmc_command cmd; int err = MMC_ERR_NONE, i; memset(&cmd, 0, sizeof(cmd)); cmd.opcode = MMC_SEND_OP_COND; cmd.arg = ocr; cmd.flags = MMC_RSP_R3 | MMC_CMD_BCR; cmd.data = NULL; for (i = 0; i < 1000; i++) { err = mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); if (err != MMC_ERR_NONE) break; if ((cmd.resp[0] & MMC_OCR_CARD_BUSY) || (ocr & MMC_OCR_VOLTAGE) == 0) break; err = MMC_ERR_TIMEOUT; mmc_ms_delay(10); } if (rocr && err == MMC_ERR_NONE) *rocr = cmd.resp[0]; return (err); } static int mmc_send_if_cond(struct mmc_softc *sc, uint8_t vhs) { struct mmc_command cmd; int err; memset(&cmd, 0, sizeof(cmd)); cmd.opcode = SD_SEND_IF_COND; cmd.arg = (vhs << 8) + 0xAA; cmd.flags = MMC_RSP_R7 | MMC_CMD_BCR; cmd.data = NULL; err = mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); return (err); } static void mmc_power_up(struct mmc_softc *sc) { device_t dev; dev = sc->dev; mmcbr_set_vdd(dev, mmc_highest_voltage(mmcbr_get_host_ocr(dev))); mmcbr_set_bus_mode(dev, opendrain); mmcbr_set_chip_select(dev, cs_dontcare); mmcbr_set_bus_width(dev, bus_width_1); mmcbr_set_power_mode(dev, power_up); mmcbr_set_clock(dev, 0); mmcbr_update_ios(dev); mmc_ms_delay(1); mmcbr_set_clock(dev, CARD_ID_FREQUENCY); mmcbr_set_timing(dev, bus_timing_normal); mmcbr_set_power_mode(dev, power_on); mmcbr_update_ios(dev); mmc_ms_delay(2); } static void mmc_power_down(struct mmc_softc *sc) { device_t dev = sc->dev; mmcbr_set_bus_mode(dev, opendrain); mmcbr_set_chip_select(dev, cs_dontcare); mmcbr_set_bus_width(dev, bus_width_1); mmcbr_set_power_mode(dev, power_off); mmcbr_set_clock(dev, 0); mmcbr_set_timing(dev, bus_timing_normal); mmcbr_update_ios(dev); } static int mmc_select_card(struct mmc_softc *sc, uint16_t rca) { int flags; flags = (rca ? MMC_RSP_R1B : MMC_RSP_NONE) | MMC_CMD_AC; return (mmc_wait_for_command(sc, MMC_SELECT_CARD, (uint32_t)rca << 16, flags, NULL, CMD_RETRIES)); } static int mmc_switch(struct mmc_softc *sc, uint8_t set, uint8_t index, uint8_t value) { struct mmc_command cmd; int err; memset(&cmd, 0, sizeof(cmd)); cmd.opcode = MMC_SWITCH_FUNC; cmd.arg = (MMC_SWITCH_FUNC_WR << 24) | (index << 16) | (value << 8) | set; cmd.flags = MMC_RSP_R1B | MMC_CMD_AC; cmd.data = NULL; err = mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); return (err); } static int mmc_sd_switch(struct mmc_softc *sc, uint8_t mode, uint8_t grp, uint8_t value, uint8_t *res) { int err; struct mmc_command cmd; struct mmc_data data; memset(&cmd, 0, sizeof(cmd)); memset(&data, 0, sizeof(data)); memset(res, 0, 64); cmd.opcode = SD_SWITCH_FUNC; cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; cmd.arg = mode << 31; /* 0 - check, 1 - set */ cmd.arg |= 0x00FFFFFF; cmd.arg &= ~(0xF << (grp * 4)); cmd.arg |= value << (grp * 4); cmd.data = &data; data.data = res; data.len = 64; data.flags = MMC_DATA_READ; err = mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); return (err); } static int mmc_set_card_bus_width(struct mmc_softc *sc, uint16_t rca, int width) { struct mmc_command cmd; int err; uint8_t value; if (mmcbr_get_mode(sc->dev) == mode_sd) { memset(&cmd, 0, sizeof(cmd)); cmd.opcode = ACMD_SET_CLR_CARD_DETECT; cmd.flags = MMC_RSP_R1 | MMC_CMD_AC; cmd.arg = SD_CLR_CARD_DETECT; err = mmc_wait_for_app_cmd(sc, rca, &cmd, CMD_RETRIES); if (err != 0) return (err); memset(&cmd, 0, sizeof(cmd)); cmd.opcode = ACMD_SET_BUS_WIDTH; cmd.flags = MMC_RSP_R1 | MMC_CMD_AC; switch (width) { case bus_width_1: cmd.arg = SD_BUS_WIDTH_1; break; case bus_width_4: cmd.arg = SD_BUS_WIDTH_4; break; default: return (MMC_ERR_INVALID); } err = mmc_wait_for_app_cmd(sc, rca, &cmd, CMD_RETRIES); } else { switch (width) { case bus_width_1: value = EXT_CSD_BUS_WIDTH_1; break; case bus_width_4: value = EXT_CSD_BUS_WIDTH_4; break; case bus_width_8: value = EXT_CSD_BUS_WIDTH_8; break; default: return (MMC_ERR_INVALID); } err = mmc_switch(sc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, value); } return (err); } static int mmc_set_timing(struct mmc_softc *sc, int timing) { int err; uint8_t value; u_char switch_res[64]; switch (timing) { case bus_timing_normal: value = 0; break; case bus_timing_hs: value = 1; break; default: return (MMC_ERR_INVALID); } if (mmcbr_get_mode(sc->dev) == mode_sd) err = mmc_sd_switch(sc, SD_SWITCH_MODE_SET, SD_SWITCH_GROUP1, value, switch_res); else err = mmc_switch(sc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, value); return (err); } static int mmc_test_bus_width(struct mmc_softc *sc) { struct mmc_command cmd; struct mmc_data data; int err; uint8_t buf[8]; uint8_t p8[8] = { 0x55, 0xAA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; uint8_t p8ok[8] = { 0xAA, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; uint8_t p4[4] = { 0x5A, 0x00, 0x00, 0x00, }; uint8_t p4ok[4] = { 0xA5, 0x00, 0x00, 0x00, }; if (mmcbr_get_caps(sc->dev) & MMC_CAP_8_BIT_DATA) { mmcbr_set_bus_width(sc->dev, bus_width_8); mmcbr_update_ios(sc->dev); sc->squelched++; /* Errors are expected, squelch reporting. */ memset(&cmd, 0, sizeof(cmd)); memset(&data, 0, sizeof(data)); cmd.opcode = MMC_BUSTEST_W; cmd.arg = 0; cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; cmd.data = &data; data.data = p8; data.len = 8; data.flags = MMC_DATA_WRITE; mmc_wait_for_cmd(sc, &cmd, 0); memset(&cmd, 0, sizeof(cmd)); memset(&data, 0, sizeof(data)); cmd.opcode = MMC_BUSTEST_R; cmd.arg = 0; cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; cmd.data = &data; data.data = buf; data.len = 8; data.flags = MMC_DATA_READ; err = mmc_wait_for_cmd(sc, &cmd, 0); sc->squelched--; mmcbr_set_bus_width(sc->dev, bus_width_1); mmcbr_update_ios(sc->dev); if (err == MMC_ERR_NONE && memcmp(buf, p8ok, 8) == 0) return (bus_width_8); } if (mmcbr_get_caps(sc->dev) & MMC_CAP_4_BIT_DATA) { mmcbr_set_bus_width(sc->dev, bus_width_4); mmcbr_update_ios(sc->dev); sc->squelched++; /* Errors are expected, squelch reporting. */ memset(&cmd, 0, sizeof(cmd)); memset(&data, 0, sizeof(data)); cmd.opcode = MMC_BUSTEST_W; cmd.arg = 0; cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; cmd.data = &data; data.data = p4; data.len = 4; data.flags = MMC_DATA_WRITE; mmc_wait_for_cmd(sc, &cmd, 0); memset(&cmd, 0, sizeof(cmd)); memset(&data, 0, sizeof(data)); cmd.opcode = MMC_BUSTEST_R; cmd.arg = 0; cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; cmd.data = &data; data.data = buf; data.len = 4; data.flags = MMC_DATA_READ; err = mmc_wait_for_cmd(sc, &cmd, 0); sc->squelched--; mmcbr_set_bus_width(sc->dev, bus_width_1); mmcbr_update_ios(sc->dev); if (err == MMC_ERR_NONE && memcmp(buf, p4ok, 4) == 0) return (bus_width_4); } return (bus_width_1); } static uint32_t mmc_get_bits(uint32_t *bits, int bit_len, int start, int size) { const int i = (bit_len / 32) - (start / 32) - 1; const int shift = start & 31; uint32_t retval = bits[i] >> shift; if (size + shift > 32) retval |= bits[i - 1] << (32 - shift); return (retval & ((1llu << size) - 1)); } static void mmc_decode_cid_sd(uint32_t *raw_cid, struct mmc_cid *cid) { int i; /* There's no version info, so we take it on faith */ memset(cid, 0, sizeof(*cid)); cid->mid = mmc_get_bits(raw_cid, 128, 120, 8); cid->oid = mmc_get_bits(raw_cid, 128, 104, 16); for (i = 0; i < 5; i++) cid->pnm[i] = mmc_get_bits(raw_cid, 128, 96 - i * 8, 8); cid->pnm[5] = 0; cid->prv = mmc_get_bits(raw_cid, 128, 56, 8); cid->psn = mmc_get_bits(raw_cid, 128, 24, 32); cid->mdt_year = mmc_get_bits(raw_cid, 128, 12, 8) + 2000; cid->mdt_month = mmc_get_bits(raw_cid, 128, 8, 4); } static void mmc_decode_cid_mmc(uint32_t *raw_cid, struct mmc_cid *cid) { int i; /* There's no version info, so we take it on faith */ memset(cid, 0, sizeof(*cid)); cid->mid = mmc_get_bits(raw_cid, 128, 120, 8); cid->oid = mmc_get_bits(raw_cid, 128, 104, 8); for (i = 0; i < 6; i++) cid->pnm[i] = mmc_get_bits(raw_cid, 128, 96 - i * 8, 8); cid->pnm[6] = 0; cid->prv = mmc_get_bits(raw_cid, 128, 48, 8); cid->psn = mmc_get_bits(raw_cid, 128, 16, 32); cid->mdt_month = mmc_get_bits(raw_cid, 128, 12, 4); cid->mdt_year = mmc_get_bits(raw_cid, 128, 8, 4) + 1997; } static void mmc_format_card_id_string(struct mmc_ivars *ivar) { char oidstr[8]; uint8_t c1; uint8_t c2; /* * Format a card ID string for use by the mmcsd driver, it's what * appears between the <> in the following: * mmcsd0: 968MB at mmc0 * 22.5MHz/4bit/128-block * * Also format just the card serial number, which the mmcsd driver will * use as the disk->d_ident string. * * The card_id_string in mmc_ivars is currently allocated as 64 bytes, * and our max formatted length is currently 55 bytes if every field * contains the largest value. * * Sometimes the oid is two printable ascii chars; when it's not, * format it as 0xnnnn instead. */ c1 = (ivar->cid.oid >> 8) & 0x0ff; c2 = ivar->cid.oid & 0x0ff; if (c1 > 0x1f && c1 < 0x7f && c2 > 0x1f && c2 < 0x7f) snprintf(oidstr, sizeof(oidstr), "%c%c", c1, c2); else snprintf(oidstr, sizeof(oidstr), "0x%04x", ivar->cid.oid); snprintf(ivar->card_sn_string, sizeof(ivar->card_sn_string), "%08X", ivar->cid.psn); snprintf(ivar->card_id_string, sizeof(ivar->card_id_string), "%s%s %s %d.%d SN %08X MFG %02d/%04d by %d %s", ivar->mode == mode_sd ? "SD" : "MMC", ivar->high_cap ? "HC" : "", ivar->cid.pnm, ivar->cid.prv >> 4, ivar->cid.prv & 0x0f, ivar->cid.psn, ivar->cid.mdt_month, ivar->cid.mdt_year, ivar->cid.mid, oidstr); } static const int exp[8] = { 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000 }; static const int mant[16] = { 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80 }; static const int cur_min[8] = { 500, 1000, 5000, 10000, 25000, 35000, 60000, 100000 }; static const int cur_max[8] = { 1000, 5000, 10000, 25000, 35000, 45000, 800000, 200000 }; static void mmc_decode_csd_sd(uint32_t *raw_csd, struct mmc_csd *csd) { int v; int m; int e; memset(csd, 0, sizeof(*csd)); csd->csd_structure = v = mmc_get_bits(raw_csd, 128, 126, 2); if (v == 0) { m = mmc_get_bits(raw_csd, 128, 115, 4); e = mmc_get_bits(raw_csd, 128, 112, 3); csd->tacc = (exp[e] * mant[m] + 9) / 10; csd->nsac = mmc_get_bits(raw_csd, 128, 104, 8) * 100; m = mmc_get_bits(raw_csd, 128, 99, 4); e = mmc_get_bits(raw_csd, 128, 96, 3); csd->tran_speed = exp[e] * 10000 * mant[m]; csd->ccc = mmc_get_bits(raw_csd, 128, 84, 12); csd->read_bl_len = 1 << mmc_get_bits(raw_csd, 128, 80, 4); csd->read_bl_partial = mmc_get_bits(raw_csd, 128, 79, 1); csd->write_blk_misalign = mmc_get_bits(raw_csd, 128, 78, 1); csd->read_blk_misalign = mmc_get_bits(raw_csd, 128, 77, 1); csd->dsr_imp = mmc_get_bits(raw_csd, 128, 76, 1); csd->vdd_r_curr_min = cur_min[mmc_get_bits(raw_csd, 128, 59, 3)]; csd->vdd_r_curr_max = cur_max[mmc_get_bits(raw_csd, 128, 56, 3)]; csd->vdd_w_curr_min = cur_min[mmc_get_bits(raw_csd, 128, 53, 3)]; csd->vdd_w_curr_max = cur_max[mmc_get_bits(raw_csd, 128, 50, 3)]; m = mmc_get_bits(raw_csd, 128, 62, 12); e = mmc_get_bits(raw_csd, 128, 47, 3); csd->capacity = ((1 + m) << (e + 2)) * csd->read_bl_len; csd->erase_blk_en = mmc_get_bits(raw_csd, 128, 46, 1); csd->erase_sector = mmc_get_bits(raw_csd, 128, 39, 7) + 1; csd->wp_grp_size = mmc_get_bits(raw_csd, 128, 32, 7); csd->wp_grp_enable = mmc_get_bits(raw_csd, 128, 31, 1); csd->r2w_factor = 1 << mmc_get_bits(raw_csd, 128, 26, 3); csd->write_bl_len = 1 << mmc_get_bits(raw_csd, 128, 22, 4); csd->write_bl_partial = mmc_get_bits(raw_csd, 128, 21, 1); } else if (v == 1) { m = mmc_get_bits(raw_csd, 128, 115, 4); e = mmc_get_bits(raw_csd, 128, 112, 3); csd->tacc = (exp[e] * mant[m] + 9) / 10; csd->nsac = mmc_get_bits(raw_csd, 128, 104, 8) * 100; m = mmc_get_bits(raw_csd, 128, 99, 4); e = mmc_get_bits(raw_csd, 128, 96, 3); csd->tran_speed = exp[e] * 10000 * mant[m]; csd->ccc = mmc_get_bits(raw_csd, 128, 84, 12); csd->read_bl_len = 1 << mmc_get_bits(raw_csd, 128, 80, 4); csd->read_bl_partial = mmc_get_bits(raw_csd, 128, 79, 1); csd->write_blk_misalign = mmc_get_bits(raw_csd, 128, 78, 1); csd->read_blk_misalign = mmc_get_bits(raw_csd, 128, 77, 1); csd->dsr_imp = mmc_get_bits(raw_csd, 128, 76, 1); csd->capacity = ((uint64_t)mmc_get_bits(raw_csd, 128, 48, 22) + 1) * 512 * 1024; csd->erase_blk_en = mmc_get_bits(raw_csd, 128, 46, 1); csd->erase_sector = mmc_get_bits(raw_csd, 128, 39, 7) + 1; csd->wp_grp_size = mmc_get_bits(raw_csd, 128, 32, 7); csd->wp_grp_enable = mmc_get_bits(raw_csd, 128, 31, 1); csd->r2w_factor = 1 << mmc_get_bits(raw_csd, 128, 26, 3); csd->write_bl_len = 1 << mmc_get_bits(raw_csd, 128, 22, 4); csd->write_bl_partial = mmc_get_bits(raw_csd, 128, 21, 1); } else panic("unknown SD CSD version"); } static void mmc_decode_csd_mmc(uint32_t *raw_csd, struct mmc_csd *csd) { int m; int e; memset(csd, 0, sizeof(*csd)); csd->csd_structure = mmc_get_bits(raw_csd, 128, 126, 2); csd->spec_vers = mmc_get_bits(raw_csd, 128, 122, 4); m = mmc_get_bits(raw_csd, 128, 115, 4); e = mmc_get_bits(raw_csd, 128, 112, 3); csd->tacc = exp[e] * mant[m] + 9 / 10; csd->nsac = mmc_get_bits(raw_csd, 128, 104, 8) * 100; m = mmc_get_bits(raw_csd, 128, 99, 4); e = mmc_get_bits(raw_csd, 128, 96, 3); csd->tran_speed = exp[e] * 10000 * mant[m]; csd->ccc = mmc_get_bits(raw_csd, 128, 84, 12); csd->read_bl_len = 1 << mmc_get_bits(raw_csd, 128, 80, 4); csd->read_bl_partial = mmc_get_bits(raw_csd, 128, 79, 1); csd->write_blk_misalign = mmc_get_bits(raw_csd, 128, 78, 1); csd->read_blk_misalign = mmc_get_bits(raw_csd, 128, 77, 1); csd->dsr_imp = mmc_get_bits(raw_csd, 128, 76, 1); csd->vdd_r_curr_min = cur_min[mmc_get_bits(raw_csd, 128, 59, 3)]; csd->vdd_r_curr_max = cur_max[mmc_get_bits(raw_csd, 128, 56, 3)]; csd->vdd_w_curr_min = cur_min[mmc_get_bits(raw_csd, 128, 53, 3)]; csd->vdd_w_curr_max = cur_max[mmc_get_bits(raw_csd, 128, 50, 3)]; m = mmc_get_bits(raw_csd, 128, 62, 12); e = mmc_get_bits(raw_csd, 128, 47, 3); csd->capacity = ((1 + m) << (e + 2)) * csd->read_bl_len; csd->erase_blk_en = 0; csd->erase_sector = (mmc_get_bits(raw_csd, 128, 42, 5) + 1) * (mmc_get_bits(raw_csd, 128, 37, 5) + 1); csd->wp_grp_size = mmc_get_bits(raw_csd, 128, 32, 5); csd->wp_grp_enable = mmc_get_bits(raw_csd, 128, 31, 1); csd->r2w_factor = 1 << mmc_get_bits(raw_csd, 128, 26, 3); csd->write_bl_len = 1 << mmc_get_bits(raw_csd, 128, 22, 4); csd->write_bl_partial = mmc_get_bits(raw_csd, 128, 21, 1); } static void mmc_app_decode_scr(uint32_t *raw_scr, struct mmc_scr *scr) { unsigned int scr_struct; memset(scr, 0, sizeof(*scr)); scr_struct = mmc_get_bits(raw_scr, 64, 60, 4); if (scr_struct != 0) { printf("Unrecognised SCR structure version %d\n", scr_struct); return; } scr->sda_vsn = mmc_get_bits(raw_scr, 64, 56, 4); scr->bus_widths = mmc_get_bits(raw_scr, 64, 48, 4); } static void mmc_app_decode_sd_status(uint32_t *raw_sd_status, struct mmc_sd_status *sd_status) { memset(sd_status, 0, sizeof(*sd_status)); sd_status->bus_width = mmc_get_bits(raw_sd_status, 512, 510, 2); sd_status->secured_mode = mmc_get_bits(raw_sd_status, 512, 509, 1); sd_status->card_type = mmc_get_bits(raw_sd_status, 512, 480, 16); sd_status->prot_area = mmc_get_bits(raw_sd_status, 512, 448, 12); sd_status->speed_class = mmc_get_bits(raw_sd_status, 512, 440, 8); sd_status->perf_move = mmc_get_bits(raw_sd_status, 512, 432, 8); sd_status->au_size = mmc_get_bits(raw_sd_status, 512, 428, 4); sd_status->erase_size = mmc_get_bits(raw_sd_status, 512, 408, 16); sd_status->erase_timeout = mmc_get_bits(raw_sd_status, 512, 402, 6); sd_status->erase_offset = mmc_get_bits(raw_sd_status, 512, 400, 2); } static int mmc_all_send_cid(struct mmc_softc *sc, uint32_t *rawcid) { struct mmc_command cmd; int err; memset(&cmd, 0, sizeof(cmd)); cmd.opcode = MMC_ALL_SEND_CID; cmd.arg = 0; cmd.flags = MMC_RSP_R2 | MMC_CMD_BCR; cmd.data = NULL; err = mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); memcpy(rawcid, cmd.resp, 4 * sizeof(uint32_t)); return (err); } static int mmc_send_csd(struct mmc_softc *sc, uint16_t rca, uint32_t *rawcsd) { struct mmc_command cmd; int err; memset(&cmd, 0, sizeof(cmd)); cmd.opcode = MMC_SEND_CSD; cmd.arg = rca << 16; cmd.flags = MMC_RSP_R2 | MMC_CMD_BCR; cmd.data = NULL; err = mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); memcpy(rawcsd, cmd.resp, 4 * sizeof(uint32_t)); return (err); } static int mmc_app_send_scr(struct mmc_softc *sc, uint16_t rca, uint32_t *rawscr) { int err; struct mmc_command cmd; struct mmc_data data; memset(&cmd, 0, sizeof(cmd)); memset(&data, 0, sizeof(data)); memset(rawscr, 0, 8); cmd.opcode = ACMD_SEND_SCR; cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; cmd.arg = 0; cmd.data = &data; data.data = rawscr; data.len = 8; data.flags = MMC_DATA_READ; err = mmc_wait_for_app_cmd(sc, rca, &cmd, CMD_RETRIES); rawscr[0] = be32toh(rawscr[0]); rawscr[1] = be32toh(rawscr[1]); return (err); } static int mmc_send_ext_csd(struct mmc_softc *sc, uint8_t *rawextcsd) { int err; struct mmc_command cmd; struct mmc_data data; memset(&cmd, 0, sizeof(cmd)); memset(&data, 0, sizeof(data)); memset(rawextcsd, 0, 512); cmd.opcode = MMC_SEND_EXT_CSD; cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; cmd.arg = 0; cmd.data = &data; data.data = rawextcsd; data.len = 512; data.flags = MMC_DATA_READ; err = mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); return (err); } static int mmc_app_sd_status(struct mmc_softc *sc, uint16_t rca, uint32_t *rawsdstatus) { int err, i; struct mmc_command cmd; struct mmc_data data; memset(&cmd, 0, sizeof(cmd)); memset(&data, 0, sizeof(data)); memset(rawsdstatus, 0, 64); cmd.opcode = ACMD_SD_STATUS; cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; cmd.arg = 0; cmd.data = &data; data.data = rawsdstatus; data.len = 64; data.flags = MMC_DATA_READ; err = mmc_wait_for_app_cmd(sc, rca, &cmd, CMD_RETRIES); for (i = 0; i < 16; i++) rawsdstatus[i] = be32toh(rawsdstatus[i]); return (err); } static int mmc_set_relative_addr(struct mmc_softc *sc, uint16_t resp) { struct mmc_command cmd; int err; memset(&cmd, 0, sizeof(cmd)); cmd.opcode = MMC_SET_RELATIVE_ADDR; cmd.arg = resp << 16; cmd.flags = MMC_RSP_R6 | MMC_CMD_BCR; cmd.data = NULL; err = mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); return (err); } static int mmc_send_relative_addr(struct mmc_softc *sc, uint32_t *resp) { struct mmc_command cmd; int err; memset(&cmd, 0, sizeof(cmd)); cmd.opcode = SD_SEND_RELATIVE_ADDR; cmd.arg = 0; cmd.flags = MMC_RSP_R6 | MMC_CMD_BCR; cmd.data = NULL; err = mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); *resp = cmd.resp[0]; return (err); } static int mmc_send_status(struct mmc_softc *sc, uint16_t rca, uint32_t *status) { struct mmc_command cmd; int err; memset(&cmd, 0, sizeof(cmd)); cmd.opcode = MMC_SEND_STATUS; cmd.arg = rca << 16; cmd.flags = MMC_RSP_R1 | MMC_CMD_AC; cmd.data = NULL; err = mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); *status = cmd.resp[0]; return (err); } static int mmc_set_blocklen(struct mmc_softc *sc, uint32_t len) { struct mmc_command cmd; int err; memset(&cmd, 0, sizeof(cmd)); cmd.opcode = MMC_SET_BLOCKLEN; cmd.arg = len; cmd.flags = MMC_RSP_R1 | MMC_CMD_AC; cmd.data = NULL; err = mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); return (err); } static void mmc_log_card(device_t dev, struct mmc_ivars *ivar, int newcard) { device_printf(dev, "Card at relative address 0x%04x%s:\n", ivar->rca, newcard ? " added" : ""); device_printf(dev, " card: %s\n", ivar->card_id_string); device_printf(dev, " bus: %ubit, %uMHz%s\n", (ivar->bus_width == bus_width_1 ? 1 : (ivar->bus_width == bus_width_4 ? 4 : 8)), (ivar->timing == bus_timing_hs ? ivar->hs_tran_speed : ivar->tran_speed) / 1000000, ivar->timing == bus_timing_hs ? ", high speed timing" : ""); device_printf(dev, " memory: %u blocks, erase sector %u blocks%s\n", ivar->sec_count, ivar->erase_sector, ivar->read_only ? ", read-only" : ""); } static void mmc_discover_cards(struct mmc_softc *sc) { struct mmc_ivars *ivar = NULL; device_t *devlist; int err, i, devcount, newcard; uint32_t raw_cid[4], resp, sec_count, status; device_t child; uint16_t rca = 2; u_char switch_res[64]; if (bootverbose || mmc_debug) device_printf(sc->dev, "Probing cards\n"); while (1) { sc->squelched++; /* Errors are expected, squelch reporting. */ err = mmc_all_send_cid(sc, raw_cid); sc->squelched--; if (err == MMC_ERR_TIMEOUT) break; if (err != MMC_ERR_NONE) { device_printf(sc->dev, "Error reading CID %d\n", err); break; } newcard = 1; if ((err = device_get_children(sc->dev, &devlist, &devcount)) != 0) return; for (i = 0; i < devcount; i++) { ivar = device_get_ivars(devlist[i]); if (memcmp(ivar->raw_cid, raw_cid, sizeof(raw_cid)) == 0) { newcard = 0; break; } } free(devlist, M_TEMP); if (bootverbose || mmc_debug) { device_printf(sc->dev, "%sard detected (CID %08x%08x%08x%08x)\n", newcard ? "New c" : "C", raw_cid[0], raw_cid[1], raw_cid[2], raw_cid[3]); } if (newcard) { ivar = malloc(sizeof(struct mmc_ivars), M_DEVBUF, M_WAITOK | M_ZERO); memcpy(ivar->raw_cid, raw_cid, sizeof(raw_cid)); } if (mmcbr_get_ro(sc->dev)) ivar->read_only = 1; ivar->bus_width = bus_width_1; ivar->timing = bus_timing_normal; ivar->mode = mmcbr_get_mode(sc->dev); if (ivar->mode == mode_sd) { mmc_decode_cid_sd(ivar->raw_cid, &ivar->cid); mmc_send_relative_addr(sc, &resp); ivar->rca = resp >> 16; /* Get card CSD. */ mmc_send_csd(sc, ivar->rca, ivar->raw_csd); if (bootverbose || mmc_debug) device_printf(sc->dev, "%sard detected (CSD %08x%08x%08x%08x)\n", newcard ? "New c" : "C", ivar->raw_csd[0], ivar->raw_csd[1], ivar->raw_csd[2], ivar->raw_csd[3]); mmc_decode_csd_sd(ivar->raw_csd, &ivar->csd); ivar->sec_count = ivar->csd.capacity / MMC_SECTOR_SIZE; if (ivar->csd.csd_structure > 0) ivar->high_cap = 1; ivar->tran_speed = ivar->csd.tran_speed; ivar->erase_sector = ivar->csd.erase_sector * ivar->csd.write_bl_len / MMC_SECTOR_SIZE; err = mmc_send_status(sc, ivar->rca, &status); if (err != MMC_ERR_NONE) { device_printf(sc->dev, "Error reading card status %d\n", err); break; } if ((status & R1_CARD_IS_LOCKED) != 0) { device_printf(sc->dev, "Card is password protected, skipping.\n"); break; } /* Get card SCR. Card must be selected to fetch it. */ mmc_select_card(sc, ivar->rca); mmc_app_send_scr(sc, ivar->rca, ivar->raw_scr); mmc_app_decode_scr(ivar->raw_scr, &ivar->scr); /* Get card switch capabilities (command class 10). */ if ((ivar->scr.sda_vsn >= 1) && (ivar->csd.ccc & (1<<10))) { mmc_sd_switch(sc, SD_SWITCH_MODE_CHECK, SD_SWITCH_GROUP1, SD_SWITCH_NOCHANGE, switch_res); if (switch_res[13] & 2) { ivar->timing = bus_timing_hs; ivar->hs_tran_speed = SD_MAX_HS; } } /* * We reselect the card here. Some cards become * unselected and timeout with the above two commands, * although the state tables / diagrams in the standard * suggest they go back to the transfer state. The only * thing we use from the sd_status is the erase sector * size, but it is still nice to get that right. It is * normally harmless for cards not misbehaving. The * Atmel bridge will complain about this command timing * out. Others seem to handle it correctly, so it may * be a combination of card and controller. */ mmc_select_card(sc, ivar->rca); mmc_app_sd_status(sc, ivar->rca, ivar->raw_sd_status); mmc_app_decode_sd_status(ivar->raw_sd_status, &ivar->sd_status); if (ivar->sd_status.au_size != 0) { ivar->erase_sector = 16 << ivar->sd_status.au_size; } /* Find max supported bus width. */ if ((mmcbr_get_caps(sc->dev) & MMC_CAP_4_BIT_DATA) && (ivar->scr.bus_widths & SD_SCR_BUS_WIDTH_4)) ivar->bus_width = bus_width_4; /* * Some cards that report maximum I/O block sizes * greater than 512 require the block length to be * set to 512, even though that is supposed to be * the default. Example: * * Transcend 2GB SDSC card, CID: * mid=0x1b oid=0x534d pnm="00000" prv=1.0 mdt=00.2000 */ if (ivar->csd.read_bl_len != MMC_SECTOR_SIZE || ivar->csd.write_bl_len != MMC_SECTOR_SIZE) mmc_set_blocklen(sc, MMC_SECTOR_SIZE); mmc_format_card_id_string(ivar); if (bootverbose || mmc_debug) mmc_log_card(sc->dev, ivar, newcard); if (newcard) { /* Add device. */ child = device_add_child(sc->dev, NULL, -1); device_set_ivars(child, ivar); } mmc_select_card(sc, 0); return; } mmc_decode_cid_mmc(ivar->raw_cid, &ivar->cid); ivar->rca = rca++; mmc_set_relative_addr(sc, ivar->rca); /* Get card CSD. */ mmc_send_csd(sc, ivar->rca, ivar->raw_csd); if (bootverbose || mmc_debug) device_printf(sc->dev, "%sard detected (CSD %08x%08x%08x%08x)\n", newcard ? "New c" : "C", ivar->raw_csd[0], ivar->raw_csd[1], ivar->raw_csd[2], ivar->raw_csd[3]); mmc_decode_csd_mmc(ivar->raw_csd, &ivar->csd); ivar->sec_count = ivar->csd.capacity / MMC_SECTOR_SIZE; ivar->tran_speed = ivar->csd.tran_speed; ivar->erase_sector = ivar->csd.erase_sector * ivar->csd.write_bl_len / MMC_SECTOR_SIZE; err = mmc_send_status(sc, ivar->rca, &status); if (err != MMC_ERR_NONE) { device_printf(sc->dev, "Error reading card status %d\n", err); break; } if ((status & R1_CARD_IS_LOCKED) != 0) { device_printf(sc->dev, "Card is password protected, skipping.\n"); break; } mmc_select_card(sc, ivar->rca); /* Only MMC >= 4.x cards support EXT_CSD. */ if (ivar->csd.spec_vers >= 4) { mmc_send_ext_csd(sc, ivar->raw_ext_csd); /* Handle extended capacity from EXT_CSD */ sec_count = ivar->raw_ext_csd[EXT_CSD_SEC_CNT] + (ivar->raw_ext_csd[EXT_CSD_SEC_CNT + 1] << 8) + (ivar->raw_ext_csd[EXT_CSD_SEC_CNT + 2] << 16) + (ivar->raw_ext_csd[EXT_CSD_SEC_CNT + 3] << 24); if (sec_count != 0) { ivar->sec_count = sec_count; ivar->high_cap = 1; } /* Get card speed in high speed mode. */ ivar->timing = bus_timing_hs; if (ivar->raw_ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_52) ivar->hs_tran_speed = MMC_TYPE_52_MAX_HS; else if (ivar->raw_ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_26) ivar->hs_tran_speed = MMC_TYPE_26_MAX_HS; else ivar->hs_tran_speed = ivar->tran_speed; /* Find max supported bus width. */ ivar->bus_width = mmc_test_bus_width(sc); /* Handle HC erase sector size. */ if (ivar->raw_ext_csd[EXT_CSD_ERASE_GRP_SIZE] != 0) { ivar->erase_sector = 1024 * ivar->raw_ext_csd[EXT_CSD_ERASE_GRP_SIZE]; mmc_switch(sc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_ERASE_GRP_DEF, 1); } } else { ivar->bus_width = bus_width_1; ivar->timing = bus_timing_normal; } /* * Some cards that report maximum I/O block sizes greater * than 512 require the block length to be set to 512, even * though that is supposed to be the default. Example: * * Transcend 2GB SDSC card, CID: * mid=0x1b oid=0x534d pnm="00000" prv=1.0 mdt=00.2000 */ if (ivar->csd.read_bl_len != MMC_SECTOR_SIZE || ivar->csd.write_bl_len != MMC_SECTOR_SIZE) mmc_set_blocklen(sc, MMC_SECTOR_SIZE); mmc_format_card_id_string(ivar); if (bootverbose || mmc_debug) mmc_log_card(sc->dev, ivar, newcard); if (newcard) { /* Add device. */ child = device_add_child(sc->dev, NULL, -1); device_set_ivars(child, ivar); } mmc_select_card(sc, 0); } } static void mmc_rescan_cards(struct mmc_softc *sc) { struct mmc_ivars *ivar = NULL; device_t *devlist; int err, i, devcount; if ((err = device_get_children(sc->dev, &devlist, &devcount)) != 0) return; for (i = 0; i < devcount; i++) { ivar = device_get_ivars(devlist[i]); if (mmc_select_card(sc, ivar->rca)) { if (bootverbose || mmc_debug) device_printf(sc->dev, "Card at relative address %d lost.\n", ivar->rca); device_delete_child(sc->dev, devlist[i]); free(ivar, M_DEVBUF); } } free(devlist, M_TEMP); mmc_select_card(sc, 0); } static int mmc_delete_cards(struct mmc_softc *sc) { struct mmc_ivars *ivar; device_t *devlist; int err, i, devcount; if ((err = device_get_children(sc->dev, &devlist, &devcount)) != 0) return (err); for (i = 0; i < devcount; i++) { ivar = device_get_ivars(devlist[i]); if (bootverbose || mmc_debug) device_printf(sc->dev, "Card at relative address %d deleted.\n", ivar->rca); device_delete_child(sc->dev, devlist[i]); free(ivar, M_DEVBUF); } free(devlist, M_TEMP); return (0); } static void mmc_go_discovery(struct mmc_softc *sc) { uint32_t ocr; device_t dev; int err; dev = sc->dev; if (mmcbr_get_power_mode(dev) != power_on) { /* * First, try SD modes */ sc->squelched++; /* Errors are expected, squelch reporting. */ mmcbr_set_mode(dev, mode_sd); mmc_power_up(sc); mmcbr_set_bus_mode(dev, pushpull); if (bootverbose || mmc_debug) device_printf(sc->dev, "Probing bus\n"); mmc_idle_cards(sc); err = mmc_send_if_cond(sc, 1); if ((bootverbose || mmc_debug) && err == 0) device_printf(sc->dev, "SD 2.0 interface conditions: OK\n"); if (mmc_send_app_op_cond(sc, 0, &ocr) != MMC_ERR_NONE) { if (bootverbose || mmc_debug) device_printf(sc->dev, "SD probe: failed\n"); /* * Failed, try MMC */ mmcbr_set_mode(dev, mode_mmc); if (mmc_send_op_cond(sc, 0, &ocr) != MMC_ERR_NONE) { if (bootverbose || mmc_debug) device_printf(sc->dev, "MMC probe: failed\n"); ocr = 0; /* Failed both, powerdown. */ } else if (bootverbose || mmc_debug) device_printf(sc->dev, "MMC probe: OK (OCR: 0x%08x)\n", ocr); } else if (bootverbose || mmc_debug) device_printf(sc->dev, "SD probe: OK (OCR: 0x%08x)\n", ocr); sc->squelched--; mmcbr_set_ocr(dev, mmc_select_vdd(sc, ocr)); if (mmcbr_get_ocr(dev) != 0) mmc_idle_cards(sc); } else { mmcbr_set_bus_mode(dev, opendrain); mmcbr_set_clock(dev, CARD_ID_FREQUENCY); mmcbr_update_ios(dev); /* XXX recompute vdd based on new cards? */ } /* * Make sure that we have a mutually agreeable voltage to at least * one card on the bus. */ if (bootverbose || mmc_debug) device_printf(sc->dev, "Current OCR: 0x%08x\n", mmcbr_get_ocr(dev)); if (mmcbr_get_ocr(dev) == 0) { device_printf(sc->dev, "No compatible cards found on bus\n"); mmc_delete_cards(sc); mmc_power_down(sc); return; } /* * Reselect the cards after we've idled them above. */ if (mmcbr_get_mode(dev) == mode_sd) { err = mmc_send_if_cond(sc, 1); mmc_send_app_op_cond(sc, (err ? 0 : MMC_OCR_CCS) | mmcbr_get_ocr(dev), NULL); } else mmc_send_op_cond(sc, MMC_OCR_CCS | mmcbr_get_ocr(dev), NULL); mmc_discover_cards(sc); mmc_rescan_cards(sc); mmcbr_set_bus_mode(dev, pushpull); mmcbr_update_ios(dev); mmc_calculate_clock(sc); bus_generic_attach(dev); /* mmc_update_children_sysctl(dev);*/ } static int mmc_calculate_clock(struct mmc_softc *sc) { int max_dtr, max_hs_dtr, max_timing; int nkid, i, f_max; device_t *kids; struct mmc_ivars *ivar; f_max = mmcbr_get_f_max(sc->dev); max_dtr = max_hs_dtr = f_max; if ((mmcbr_get_caps(sc->dev) & MMC_CAP_HSPEED)) max_timing = bus_timing_hs; else max_timing = bus_timing_normal; if (device_get_children(sc->dev, &kids, &nkid) != 0) panic("can't get children"); for (i = 0; i < nkid; i++) { ivar = device_get_ivars(kids[i]); if (ivar->timing < max_timing) max_timing = ivar->timing; if (ivar->tran_speed < max_dtr) max_dtr = ivar->tran_speed; if (ivar->hs_tran_speed < max_hs_dtr) max_hs_dtr = ivar->hs_tran_speed; } for (i = 0; i < nkid; i++) { ivar = device_get_ivars(kids[i]); if (ivar->timing == bus_timing_normal) continue; mmc_select_card(sc, ivar->rca); mmc_set_timing(sc, max_timing); } mmc_select_card(sc, 0); free(kids, M_TEMP); if (max_timing == bus_timing_hs) max_dtr = max_hs_dtr; if (bootverbose || mmc_debug) { device_printf(sc->dev, "setting transfer rate to %d.%03dMHz%s\n", max_dtr / 1000000, (max_dtr / 1000) % 1000, max_timing == bus_timing_hs ? " (high speed timing)" : ""); } mmcbr_set_timing(sc->dev, max_timing); mmcbr_set_clock(sc->dev, max_dtr); mmcbr_update_ios(sc->dev); return max_dtr; } static void mmc_scan(struct mmc_softc *sc) { device_t dev = sc->dev; mmc_acquire_bus(dev, dev); mmc_go_discovery(sc); mmc_release_bus(dev, dev); } static int mmc_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) { struct mmc_ivars *ivar = device_get_ivars(child); switch (which) { default: return (EINVAL); case MMC_IVAR_DSR_IMP: *result = ivar->csd.dsr_imp; break; case MMC_IVAR_MEDIA_SIZE: *result = ivar->sec_count; break; case MMC_IVAR_RCA: *result = ivar->rca; break; case MMC_IVAR_SECTOR_SIZE: *result = MMC_SECTOR_SIZE; break; case MMC_IVAR_TRAN_SPEED: *result = mmcbr_get_clock(bus); break; case MMC_IVAR_READ_ONLY: *result = ivar->read_only; break; case MMC_IVAR_HIGH_CAP: *result = ivar->high_cap; break; case MMC_IVAR_CARD_TYPE: *result = ivar->mode; break; case MMC_IVAR_BUS_WIDTH: *result = ivar->bus_width; break; case MMC_IVAR_ERASE_SECTOR: *result = ivar->erase_sector; break; case MMC_IVAR_MAX_DATA: *result = mmcbr_get_max_data(bus); break; case MMC_IVAR_CARD_ID_STRING: *(char **)result = ivar->card_id_string; break; case MMC_IVAR_CARD_SN_STRING: *(char **)result = ivar->card_sn_string; break; } return (0); } static int mmc_write_ivar(device_t bus, device_t child, int which, uintptr_t value) { /* * None are writable ATM */ return (EINVAL); } static void mmc_delayed_attach(void *xsc) { struct mmc_softc *sc = xsc; mmc_scan(sc); config_intrhook_disestablish(&sc->config_intrhook); } static int mmc_child_location_str(device_t dev, device_t child, char *buf, size_t buflen) { snprintf(buf, buflen, "rca=0x%04x", mmc_get_rca(child)); return (0); } static device_method_t mmc_methods[] = { /* device_if */ DEVMETHOD(device_probe, mmc_probe), DEVMETHOD(device_attach, mmc_attach), DEVMETHOD(device_detach, mmc_detach), DEVMETHOD(device_suspend, mmc_suspend), DEVMETHOD(device_resume, mmc_resume), /* Bus interface */ DEVMETHOD(bus_read_ivar, mmc_read_ivar), DEVMETHOD(bus_write_ivar, mmc_write_ivar), DEVMETHOD(bus_child_location_str, mmc_child_location_str), /* MMC Bus interface */ DEVMETHOD(mmcbus_wait_for_request, mmc_wait_for_request), DEVMETHOD(mmcbus_acquire_bus, mmc_acquire_bus), DEVMETHOD(mmcbus_release_bus, mmc_release_bus), DEVMETHOD_END }; static driver_t mmc_driver = { "mmc", mmc_methods, sizeof(struct mmc_softc), }; static devclass_t mmc_devclass; +DRIVER_MODULE(mmc, a10_mmc, mmc_driver, mmc_devclass, NULL, NULL); DRIVER_MODULE(mmc, aml8726_mmc, mmc_driver, mmc_devclass, NULL, NULL); DRIVER_MODULE(mmc, aml8726_sdxc, mmc_driver, mmc_devclass, NULL, NULL); DRIVER_MODULE(mmc, at91_mci, mmc_driver, mmc_devclass, NULL, NULL); DRIVER_MODULE(mmc, sdhci_bcm, mmc_driver, mmc_devclass, NULL, NULL); DRIVER_MODULE(mmc, sdhci_fdt, mmc_driver, mmc_devclass, NULL, NULL); DRIVER_MODULE(mmc, sdhci_imx, mmc_driver, mmc_devclass, NULL, NULL); DRIVER_MODULE(mmc, sdhci_pci, mmc_driver, mmc_devclass, NULL, NULL); DRIVER_MODULE(mmc, sdhci_ti, mmc_driver, mmc_devclass, NULL, NULL); DRIVER_MODULE(mmc, ti_mmchs, mmc_driver, mmc_devclass, NULL, NULL); DRIVER_MODULE(mmc, dwmmc, mmc_driver, mmc_devclass, NULL, NULL); -