Index: stable/9/sys/dev/mii/rgephy.c =================================================================== --- stable/9/sys/dev/mii/rgephy.c (revision 280667) +++ stable/9/sys/dev/mii/rgephy.c (revision 280668) @@ -1,517 +1,562 @@ /*- * Copyright (c) 2003 * Bill Paul . All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Bill Paul. * 4. Neither the name of the author nor the names of any co-contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * Driver for the RealTek 8169S/8110S/8211B/8211C internal 10/100/1000 PHY. */ #include #include #include #include #include #include #include #include #include #include #include #include "miidevs.h" #include #include "miibus_if.h" #include #include static int rgephy_probe(device_t); static int rgephy_attach(device_t); static device_method_t rgephy_methods[] = { /* device interface */ DEVMETHOD(device_probe, rgephy_probe), DEVMETHOD(device_attach, rgephy_attach), DEVMETHOD(device_detach, mii_phy_detach), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD_END }; static devclass_t rgephy_devclass; static driver_t rgephy_driver = { "rgephy", rgephy_methods, sizeof(struct mii_softc) }; DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0); static int rgephy_service(struct mii_softc *, struct mii_data *, int); static void rgephy_status(struct mii_softc *); static int rgephy_mii_phy_auto(struct mii_softc *, int); static void rgephy_reset(struct mii_softc *); +static int rgephy_linkup(struct mii_softc *); static void rgephy_loop(struct mii_softc *); static void rgephy_load_dspcode(struct mii_softc *); static const struct mii_phydesc rgephys[] = { MII_PHY_DESC(REALTEK, RTL8169S), MII_PHY_DESC(REALTEK, RTL8251), MII_PHY_END }; static const struct mii_phy_funcs rgephy_funcs = { rgephy_service, rgephy_status, rgephy_reset }; static int rgephy_probe(device_t dev) { return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT)); } static int rgephy_attach(device_t dev) { struct mii_softc *sc; struct mii_attach_args *ma; u_int flags; sc = device_get_softc(dev); ma = device_get_ivars(dev); flags = 0; if (strcmp(ma->mii_data->mii_ifp->if_dname, "re") == 0) flags |= MIIF_PHYPRIV0; mii_phy_dev_attach(dev, flags, &rgephy_funcs, 0); /* RTL8169S do not report auto-sense; add manually. */ sc->mii_capabilities = (PHY_READ(sc, MII_BMSR) | BMSR_ANEG) & sc->mii_capmask; if (sc->mii_capabilities & BMSR_EXTSTAT) sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); device_printf(dev, " "); mii_phy_add_media(sc); printf("\n"); /* * Allow IFM_FLAG0 to be set indicating that auto-negotiation with * manual configuration, which is used to work around issues with * certain setups by default, should not be triggered as it may in * turn cause harm in some edge cases. */ sc->mii_pdata->mii_media.ifm_mask |= IFM_FLAG0; PHY_RESET(sc); MIIBUS_MEDIAINIT(sc->mii_dev); return (0); } static int rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) { struct ifmedia_entry *ife = mii->mii_media.ifm_cur; - int reg, speed, gig, anar; + int speed, gig, anar; switch (cmd) { case MII_POLLSTAT: break; case MII_MEDIACHG: /* * If the interface is not up, don't do anything. */ if ((mii->mii_ifp->if_flags & IFF_UP) == 0) break; PHY_RESET(sc); /* XXX hardware bug work-around */ anar = PHY_READ(sc, RGEPHY_MII_ANAR); anar &= ~(RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP | RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10); switch (IFM_SUBTYPE(ife->ifm_media)) { case IFM_AUTO: #ifdef foo /* * If we're already in auto mode, just return. */ if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) return (0); #endif (void)rgephy_mii_phy_auto(sc, ife->ifm_media); break; case IFM_1000_T: speed = RGEPHY_S1000; goto setit; case IFM_100_TX: speed = RGEPHY_S100; anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX; goto setit; case IFM_10_T: speed = RGEPHY_S10; anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10; setit: if ((ife->ifm_media & IFM_FLOW) != 0 && (mii->mii_media.ifm_media & IFM_FLAG0) != 0) return (EINVAL); if ((ife->ifm_media & IFM_FDX) != 0) { speed |= RGEPHY_BMCR_FDX; gig = RGEPHY_1000CTL_AFD; anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10); if ((ife->ifm_media & IFM_FLOW) != 0 || (sc->mii_flags & MIIF_FORCEPAUSE) != 0) anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; } else { gig = RGEPHY_1000CTL_AHD; anar &= ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD); } if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { gig |= RGEPHY_1000CTL_MSE; if ((ife->ifm_media & IFM_ETH_MASTER) != 0) gig |= RGEPHY_1000CTL_MSC; } else { gig = 0; anar &= ~RGEPHY_ANAR_ASP; } if ((mii->mii_media.ifm_media & IFM_FLAG0) == 0) speed |= RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG; rgephy_loop(sc); PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig); PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); PHY_WRITE(sc, RGEPHY_MII_BMCR, speed); break; case IFM_NONE: PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN); break; default: return (EINVAL); } break; case MII_TICK: /* * Is the interface even up? */ if ((mii->mii_ifp->if_flags & IFF_UP) == 0) return (0); /* * Only used for autonegotiation. */ if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { sc->mii_ticks = 0; break; } /* * Check to see if we have link. If we do, we don't * need to restart the autonegotiation process. */ - if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && - sc->mii_mpd_rev >= 2) { - /* RTL8211B(L) */ - reg = PHY_READ(sc, RGEPHY_MII_SSR); - if (reg & RGEPHY_SSR_LINK) { - sc->mii_ticks = 0; - break; - } - } else { - reg = PHY_READ(sc, RL_GMEDIASTAT); - if (reg & RL_GMEDIASTAT_LINK) { - sc->mii_ticks = 0; - break; - } + if (rgephy_linkup(sc) != 0) { + sc->mii_ticks = 0; + break; } /* Announce link loss right after it happens. */ if (sc->mii_ticks++ == 0) break; /* Only retry autonegotiation every mii_anegticks seconds. */ if (sc->mii_ticks <= sc->mii_anegticks) return (0); sc->mii_ticks = 0; rgephy_mii_phy_auto(sc, ife->ifm_media); break; } /* Update the media status. */ PHY_STATUS(sc); /* * Callback if something changed. Note that we need to poke * the DSP on the RealTek PHYs if the media changes. * */ if (sc->mii_media_active != mii->mii_media_active || sc->mii_media_status != mii->mii_media_status || cmd == MII_MEDIACHG) { rgephy_load_dspcode(sc); } mii_phy_update(sc, cmd); return (0); } +static int +rgephy_linkup(struct mii_softc *sc) +{ + int linkup; + uint16_t reg; + + linkup = 0; + if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && + sc->mii_mpd_rev >= RGEPHY_8211B) { + if (sc->mii_mpd_rev == RGEPHY_8211F) { + reg = PHY_READ(sc, RGEPHY_F_MII_SSR); + if (reg & RGEPHY_F_SSR_LINK) + linkup++; + } else { + reg = PHY_READ(sc, RGEPHY_MII_SSR); + if (reg & RGEPHY_SSR_LINK) + linkup++; + } + } else { + reg = PHY_READ(sc, RL_GMEDIASTAT); + if (reg & RL_GMEDIASTAT_LINK) + linkup++; + } + + return (linkup); +} + static void rgephy_status(struct mii_softc *sc) { struct mii_data *mii = sc->mii_pdata; int bmsr, bmcr; uint16_t ssr; mii->mii_media_status = IFM_AVALID; mii->mii_media_active = IFM_ETHER; - if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev >= 2) { - ssr = PHY_READ(sc, RGEPHY_MII_SSR); - if (ssr & RGEPHY_SSR_LINK) - mii->mii_media_status |= IFM_ACTIVE; - } else { - bmsr = PHY_READ(sc, RL_GMEDIASTAT); - if (bmsr & RL_GMEDIASTAT_LINK) - mii->mii_media_status |= IFM_ACTIVE; - } + if (rgephy_linkup(sc) != 0) + mii->mii_media_status |= IFM_ACTIVE; bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); - bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); if (bmcr & RGEPHY_BMCR_ISO) { mii->mii_media_active |= IFM_NONE; mii->mii_media_status = 0; return; } if (bmcr & RGEPHY_BMCR_LOOP) mii->mii_media_active |= IFM_LOOP; if (bmcr & RGEPHY_BMCR_AUTOEN) { if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { /* Erg, still trying, I guess... */ mii->mii_media_active |= IFM_NONE; return; } } - if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev >= 2) { - ssr = PHY_READ(sc, RGEPHY_MII_SSR); - switch (ssr & RGEPHY_SSR_SPD_MASK) { - case RGEPHY_SSR_S1000: - mii->mii_media_active |= IFM_1000_T; - break; - case RGEPHY_SSR_S100: - mii->mii_media_active |= IFM_100_TX; - break; - case RGEPHY_SSR_S10: - mii->mii_media_active |= IFM_10_T; - break; - default: - mii->mii_media_active |= IFM_NONE; - break; + if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && + sc->mii_mpd_rev >= RGEPHY_8211B) { + if (sc->mii_mpd_rev == RGEPHY_8211F) { + ssr = PHY_READ(sc, RGEPHY_F_MII_SSR); + switch (ssr & RGEPHY_F_SSR_SPD_MASK) { + case RGEPHY_F_SSR_S1000: + mii->mii_media_active |= IFM_1000_T; + break; + case RGEPHY_F_SSR_S100: + mii->mii_media_active |= IFM_100_TX; + break; + case RGEPHY_F_SSR_S10: + mii->mii_media_active |= IFM_10_T; + break; + default: + mii->mii_media_active |= IFM_NONE; + break; + } + if (ssr & RGEPHY_F_SSR_FDX) + mii->mii_media_active |= IFM_FDX; + else + mii->mii_media_active |= IFM_HDX; + + } else { + ssr = PHY_READ(sc, RGEPHY_MII_SSR); + switch (ssr & RGEPHY_SSR_SPD_MASK) { + case RGEPHY_SSR_S1000: + mii->mii_media_active |= IFM_1000_T; + break; + case RGEPHY_SSR_S100: + mii->mii_media_active |= IFM_100_TX; + break; + case RGEPHY_SSR_S10: + mii->mii_media_active |= IFM_10_T; + break; + default: + mii->mii_media_active |= IFM_NONE; + break; + } + if (ssr & RGEPHY_SSR_FDX) + mii->mii_media_active |= IFM_FDX; + else + mii->mii_media_active |= IFM_HDX; } - if (ssr & RGEPHY_SSR_FDX) - mii->mii_media_active |= IFM_FDX; - else - mii->mii_media_active |= IFM_HDX; } else { bmsr = PHY_READ(sc, RL_GMEDIASTAT); if (bmsr & RL_GMEDIASTAT_1000MBPS) mii->mii_media_active |= IFM_1000_T; else if (bmsr & RL_GMEDIASTAT_100MBPS) mii->mii_media_active |= IFM_100_TX; else if (bmsr & RL_GMEDIASTAT_10MBPS) mii->mii_media_active |= IFM_10_T; else mii->mii_media_active |= IFM_NONE; if (bmsr & RL_GMEDIASTAT_FDX) mii->mii_media_active |= IFM_FDX; else mii->mii_media_active |= IFM_HDX; } if ((mii->mii_media_active & IFM_FDX) != 0) mii->mii_media_active |= mii_phy_flowstatus(sc); if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && (PHY_READ(sc, RGEPHY_MII_1000STS) & RGEPHY_1000STS_MSR) != 0) mii->mii_media_active |= IFM_ETH_MASTER; } static int rgephy_mii_phy_auto(struct mii_softc *sc, int media) { int anar; rgephy_loop(sc); PHY_RESET(sc); anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; if ((media & IFM_FLOW) != 0 || (sc->mii_flags & MIIF_FORCEPAUSE) != 0) anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); DELAY(1000); PHY_WRITE(sc, RGEPHY_MII_1000CTL, RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD); DELAY(1000); PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); DELAY(100); return (EJUSTRETURN); } static void rgephy_loop(struct mii_softc *sc) { int i; if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && - sc->mii_mpd_rev < 2) { + sc->mii_mpd_rev < RGEPHY_8211B) { PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); DELAY(1000); } for (i = 0; i < 15000; i++) { if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) { #if 0 device_printf(sc->mii_dev, "looped %d\n", i); #endif break; } DELAY(10); } } #define PHY_SETBIT(x, y, z) \ PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) #define PHY_CLRBIT(x, y, z) \ PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) /* * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of * existing revisions of the 8169S/8110S chips need to be tuned in * order to reliably negotiate a 1000Mbps link. This is only needed * for rev 0 and rev 1 of the PHY. Later versions work without * any fixups. */ static void rgephy_load_dspcode(struct mii_softc *sc) { int val; if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8251 || - sc->mii_mpd_rev >= 2) + sc->mii_mpd_rev >= RGEPHY_8211B) return; PHY_WRITE(sc, 31, 0x0001); PHY_WRITE(sc, 21, 0x1000); PHY_WRITE(sc, 24, 0x65C7); PHY_CLRBIT(sc, 4, 0x0800); val = PHY_READ(sc, 4) & 0xFFF; PHY_WRITE(sc, 4, val); PHY_WRITE(sc, 3, 0x00A1); PHY_WRITE(sc, 2, 0x0008); PHY_WRITE(sc, 1, 0x1020); PHY_WRITE(sc, 0, 0x1000); PHY_SETBIT(sc, 4, 0x0800); PHY_CLRBIT(sc, 4, 0x0800); val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; PHY_WRITE(sc, 4, val); PHY_WRITE(sc, 3, 0xFF41); PHY_WRITE(sc, 2, 0xDE60); PHY_WRITE(sc, 1, 0x0140); PHY_WRITE(sc, 0, 0x0077); val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; PHY_WRITE(sc, 4, val); PHY_WRITE(sc, 3, 0xDF01); PHY_WRITE(sc, 2, 0xDF20); PHY_WRITE(sc, 1, 0xFF95); PHY_WRITE(sc, 0, 0xFA00); val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; PHY_WRITE(sc, 4, val); PHY_WRITE(sc, 3, 0xFF41); PHY_WRITE(sc, 2, 0xDE20); PHY_WRITE(sc, 1, 0x0140); PHY_WRITE(sc, 0, 0x00BB); val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; PHY_WRITE(sc, 4, val); PHY_WRITE(sc, 3, 0xDF01); PHY_WRITE(sc, 2, 0xDF20); PHY_WRITE(sc, 1, 0xFF95); PHY_WRITE(sc, 0, 0xBF00); PHY_SETBIT(sc, 4, 0x0800); PHY_CLRBIT(sc, 4, 0x0800); PHY_WRITE(sc, 31, 0x0000); DELAY(40); } static void rgephy_reset(struct mii_softc *sc) { uint16_t pcr, ssr; - if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev == 3) { - /* RTL8211C(L) */ - ssr = PHY_READ(sc, RGEPHY_MII_SSR); - if ((ssr & RGEPHY_SSR_ALDPS) != 0) { - ssr &= ~RGEPHY_SSR_ALDPS; - PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); + switch (sc->mii_mpd_rev) { + case RGEPHY_8211F: + pcr = PHY_READ(sc, RGEPHY_F_MII_PCR1); + if ((pcr & RGEPHY_F_PCR1_MDI_MM) != 0) { + pcr &= ~RGEPHY_F_PCR1_MDI_MM; + PHY_WRITE(sc, RGEPHY_F_MII_PCR1, pcr); } - } - - if (sc->mii_mpd_rev >= 2) { - pcr = PHY_READ(sc, RGEPHY_MII_PCR); - if ((pcr & RGEPHY_PCR_MDIX_AUTO) == 0) { - pcr &= ~RGEPHY_PCR_MDI_MASK; - pcr |= RGEPHY_PCR_MDIX_AUTO; - PHY_WRITE(sc, RGEPHY_MII_PCR, pcr); + break; + case RGEPHY_8211C: + if ((sc->mii_flags & MIIF_PHYPRIV0) == 0) { + /* RTL8211C(L) */ + ssr = PHY_READ(sc, RGEPHY_MII_SSR); + if ((ssr & RGEPHY_SSR_ALDPS) != 0) { + ssr &= ~RGEPHY_SSR_ALDPS; + PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); + } } + /* FALLTHROUGH */ + default: + if (sc->mii_mpd_rev >= RGEPHY_8211B) { + pcr = PHY_READ(sc, RGEPHY_MII_PCR); + if ((pcr & RGEPHY_PCR_MDIX_AUTO) == 0) { + pcr &= ~RGEPHY_PCR_MDI_MASK; + pcr |= RGEPHY_PCR_MDIX_AUTO; + PHY_WRITE(sc, RGEPHY_MII_PCR, pcr); + } + } + break; } mii_phy_reset(sc); DELAY(1000); rgephy_load_dspcode(sc); } Index: stable/9/sys/dev/mii/rgephyreg.h =================================================================== --- stable/9/sys/dev/mii/rgephyreg.h (revision 280667) +++ stable/9/sys/dev/mii/rgephyreg.h (revision 280668) @@ -1,165 +1,186 @@ /*- * Copyright (c) 2003 * Bill Paul . All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Bill Paul. * 4. Neither the name of the author nor the names of any co-contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _DEV_MII_RGEPHYREG_H_ #define _DEV_MII_RGEPHYREG_H_ +#define RGEPHY_8211B 2 +#define RGEPHY_8211C 3 +#define RGEPHY_8211F 6 + /* * RealTek 8169S/8110S gigE PHY registers */ #define RGEPHY_MII_BMCR 0x00 #define RGEPHY_BMCR_RESET 0x8000 #define RGEPHY_BMCR_LOOP 0x4000 #define RGEPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */ #define RGEPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */ #define RGEPHY_BMCR_PDOWN 0x0800 /* Power down */ #define RGEPHY_BMCR_ISO 0x0400 /* Isolate */ #define RGEPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */ #define RGEPHY_BMCR_FDX 0x0100 /* Duplex mode */ #define RGEPHY_BMCR_CTEST 0x0080 /* Collision test enable */ #define RGEPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */ #define RGEPHY_S1000 RGEPHY_BMCR_SPD1 /* 1000mbps */ #define RGEPHY_S100 RGEPHY_BMCR_SPD0 /* 100mpbs */ #define RGEPHY_S10 0 /* 10mbps */ #define RGEPHY_MII_BMSR 0x01 #define RGEPHY_BMSR_100T4 0x8000 /* 100 base T4 capable */ #define RGEPHY_BMSR_100TXFDX 0x4000 /* 100 base Tx full duplex capable */ #define RGEPHY_BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */ #define RGEPHY_BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */ #define RGEPHY_BMSR_10THDX 0x0800 /* 10 base T half duplex capable */ #define RGEPHY_BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */ #define RGEPHY_BMSR_100T2HDX 0x0200 /* 100 base T2 half duplex capable */ #define RGEPHY_BMSR_EXTSTS 0x0100 /* Extended status present */ #define RGEPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */ #define RGEPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */ #define RGEPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occurred */ #define RGEPHY_BMSR_ANEG 0x0008 /* Autoneg capable */ #define RGEPHY_BMSR_LINK 0x0004 /* Link status */ #define RGEPHY_BMSR_JABBER 0x0002 /* Jabber detected */ #define RGEPHY_BMSR_EXT 0x0001 /* Extended capability */ #define RGEPHY_MII_ANAR 0x04 #define RGEPHY_ANAR_NP 0x8000 /* Next page */ #define RGEPHY_ANAR_RF 0x2000 /* Remote fault */ #define RGEPHY_ANAR_ASP 0x0800 /* Asymmetric Pause */ #define RGEPHY_ANAR_PC 0x0400 /* Pause capable */ #define RGEPHY_ANAR_T4 0x0200 /* local device supports 100bT4 */ #define RGEPHY_ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */ #define RGEPHY_ANAR_TX 0x0080 /* local device supports 100bTx */ #define RGEPHY_ANAR_10_FD 0x0040 /* local device supports 10bT FD */ #define RGEPHY_ANAR_10 0x0020 /* local device supports 10bT */ #define RGEPHY_ANAR_SEL 0x001F /* selector field, 00001=Ethernet */ #define RGEPHY_MII_ANLPAR 0x05 #define RGEPHY_ANLPAR_NP 0x8000 /* Next page */ #define RGEPHY_ANLPAR_RF 0x2000 /* Remote fault */ #define RGEPHY_ANLPAR_ASP 0x0800 /* Asymmetric Pause */ #define RGEPHY_ANLPAR_PC 0x0400 /* Pause capable */ #define RGEPHY_ANLPAR_T4 0x0200 /* link partner supports 100bT4 */ #define RGEPHY_ANLPAR_TX_FD 0x0100 /* link partner supports 100bTx FD */ #define RGEPHY_ANLPAR_TX 0x0080 /* link partner supports 100bTx */ #define RGEPHY_ANLPAR_10_FD 0x0040 /* link partner supports 10bT FD */ #define RGEPHY_ANLPAR_10 0x0020 /* link partner supports 10bT */ #define RGEPHY_ANLPAR_SEL 0x001F /* selector field, 00001=Ethernet */ #define RGEPHY_SEL_TYPE 0x0001 /* ethernet */ #define RGEPHY_MII_ANER 0x06 #define RGEPHY_ANER_PDF 0x0010 /* Parallel detection fault */ #define RGEPHY_ANER_LPNP 0x0008 /* Link partner can next page */ #define RGEPHY_ANER_NP 0x0004 /* Local PHY can next page */ #define RGEPHY_ANER_RX 0x0002 /* Next page received */ #define RGEPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */ #define RGEPHY_MII_NEXTP 0x07 /* Next page */ #define RGEPHY_MII_NEXTP_LP 0x08 /* Next page of link partner */ #define RGEPHY_MII_1000CTL 0x09 /* 1000baseT control */ #define RGEPHY_1000CTL_TST 0xE000 /* test modes */ #define RGEPHY_1000CTL_MSE 0x1000 /* Master/Slave manual enable */ #define RGEPHY_1000CTL_MSC 0x0800 /* Master/Slave select */ #define RGEPHY_1000CTL_RD 0x0400 /* Repeater/DTE */ #define RGEPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */ #define RGEPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */ #define RGEPHY_TEST_TX_JITTER 0x2000 #define RGEPHY_TEST_TX_JITTER_MASTER_MODE 0x4000 #define RGEPHY_TEST_TX_JITTER_SLAVE_MODE 0x6000 #define RGEPHY_TEST_TX_DISTORTION 0x8000 #define RGEPHY_MII_1000STS 0x0A /* 1000baseT status */ #define RGEPHY_1000STS_MSF 0x8000 /* Master/slave fault */ #define RGEPHY_1000STS_MSR 0x4000 /* Master/slave result */ #define RGEPHY_1000STS_LRS 0x2000 /* Local receiver status */ #define RGEPHY_1000STS_RRS 0x1000 /* Remote receiver status */ #define RGEPHY_1000STS_LPFD 0x0800 /* Link partner can FD */ #define RGEPHY_1000STS_LPHD 0x0400 /* Link partner can HD */ #define RGEPHY_1000STS_IEC 0x00FF /* Idle error count */ #define RGEPHY_MII_EXTSTS 0x0F /* Extended status */ #define RGEPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */ #define RGEPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */ #define RGEPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */ #define RGEPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */ /* RTL8211B(L)/RTL8211C(L) */ #define RGEPHY_MII_PCR 0x10 /* PHY Specific control register */ #define RGEPHY_PCR_ASSERT_CRS 0x0800 #define RGEPHY_PCR_FORCE_LINK 0x0400 #define RGEPHY_PCR_MDI_MASK 0x0060 #define RGEPHY_PCR_MDIX_AUTO 0x0040 #define RGEPHY_PCR_MDIX_MANUAL 0x0020 #define RGEPHY_PCR_MDI_MANUAL 0x0000 #define RGEPHY_PCR_CLK125_DIS 0x0010 #define RGEPHY_PCR_JABBER_DIS 0x0001 /* RTL8211B(L)/RTL8211C(L) */ #define RGEPHY_MII_SSR 0x11 /* PHY Specific status register */ #define RGEPHY_SSR_S1000 0x8000 /* 1000Mbps */ #define RGEPHY_SSR_S100 0x4000 /* 100Mbps */ #define RGEPHY_SSR_S10 0x0000 /* 10Mbps */ #define RGEPHY_SSR_SPD_MASK 0xc000 #define RGEPHY_SSR_FDX 0x2000 /* full duplex */ #define RGEPHY_SSR_PAGE_RECEIVED 0x1000 /* new page received */ #define RGEPHY_SSR_SPD_DPLX_RESOLVED 0x0800 /* speed/duplex resolved */ #define RGEPHY_SSR_LINK 0x0400 /* link up */ #define RGEPHY_SSR_MDI_XOVER 0x0040 /* MDI crossover */ #define RGEPHY_SSR_ALDPS 0x0008 /* RTL8211C(L) only */ #define RGEPHY_SSR_JABBER 0x0001 /* Jabber */ + +/* RTL8211F */ +#define RGEPHY_F_MII_PCR1 0x18 /* PHY Specific control register 1 */ +#define RGEPHY_F_PCR1_MDI_MM 0x0200 /* MDI / MDIX Manual Mode */ +#define RGEPHY_F_PCR1_MDI_MODE 0x0100 /* MDI Mode (0=MDIX,1=MDI) */ +#define RGEPHY_F_PCR1_ALDPS_EN 0x0004 /* Link Down Power Saving Enable */ + +/* RTL8211F */ +#define RGEPHY_F_MII_SSR 0x1A /* PHY Specific status register */ +#define RGEPHY_F_SSR_S1000 0x0020 /* 1000Mbps */ +#define RGEPHY_F_SSR_S100 0x0010 /* 100Mbps */ +#define RGEPHY_F_SSR_S10 0x0000 /* 10Mbps */ +#define RGEPHY_F_SSR_SPD_MASK 0x0030 +#define RGEPHY_F_SSR_FDX 0x0008 /* full duplex */ +#define RGEPHY_F_SSR_LINK 0x0004 /* link up */ +#define RGEPHY_F_SSR_MDI 0x0002 /* MDI/MDIX */ +#define RGEPHY_F_SSR_JABBER 0x0001 /* Jabber */ #endif /* _DEV_RGEPHY_MIIREG_H_ */ Index: stable/9/sys/dev =================================================================== --- stable/9/sys/dev (revision 280667) +++ stable/9/sys/dev (revision 280668) Property changes on: stable/9/sys/dev ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head/sys/dev:r279903,279941 Index: stable/9/sys =================================================================== --- stable/9/sys (revision 280667) +++ stable/9/sys (revision 280668) Property changes on: stable/9/sys ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head/sys:r279903,279941