Index: head/sys/mips/nlm/dev/net/mdio.c =================================================================== --- head/sys/mips/nlm/dev/net/mdio.c (revision 279387) +++ head/sys/mips/nlm/dev/net/mdio.c (revision 279388) @@ -1,333 +1,333 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include /* Internal MDIO READ/WRITE Routines */ int nlm_int_gmac_mdio_read(uint64_t nae_base, int bus, int block, int intf_type, int phyaddr, int regidx) { uint32_t mdio_ld_cmd; uint32_t ctrlval; - ctrlval = INT_MDIO_CTRL_SMP | + ctrlval = INT_MDIO_CTRL_SMP | (phyaddr << INT_MDIO_CTRL_PHYADDR_POS) | (regidx << INT_MDIO_CTRL_DEVTYPE_POS) | (2 << INT_MDIO_CTRL_OP_POS) | (1 << INT_MDIO_CTRL_ST_POS) | - (7 << INT_MDIO_CTRL_XDIV_POS) | + (7 << INT_MDIO_CTRL_XDIV_POS) | (2 << INT_MDIO_CTRL_TA_POS) | - (2 << INT_MDIO_CTRL_MIIM_POS) | + (2 << INT_MDIO_CTRL_MIIM_POS) | (1 << INT_MDIO_CTRL_MCDIV_POS); mdio_ld_cmd = nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4))); if (mdio_ld_cmd & INT_MDIO_CTRL_CMD_LOAD) { nlm_write_nae_reg(nae_base, NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus*4)), (mdio_ld_cmd & ~INT_MDIO_CTRL_CMD_LOAD)); } nlm_write_nae_reg(nae_base, NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)), ctrlval); /* Toggle Load Cmd Bit */ nlm_write_nae_reg(nae_base, NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)), ctrlval | (1 << INT_MDIO_CTRL_LOAD_POS)); /* poll master busy bit until it is not busy */ while(nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type, (INT_MDIO_RD_STAT + bus * 4))) & INT_MDIO_STAT_MBSY) { } nlm_write_nae_reg(nae_base, NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)), ctrlval); /* Read the data back */ return nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type, (INT_MDIO_RD_STAT + bus * 4))); } /* Internal MDIO WRITE Routines */ int nlm_int_gmac_mdio_write(uint64_t nae_base, int bus, int block, int intf_type, int phyaddr, int regidx, uint16_t val) { uint32_t mdio_ld_cmd; uint32_t ctrlval; ctrlval = INT_MDIO_CTRL_SMP | (phyaddr << INT_MDIO_CTRL_PHYADDR_POS) | (regidx << INT_MDIO_CTRL_DEVTYPE_POS) | (1 << INT_MDIO_CTRL_OP_POS) | (1 << INT_MDIO_CTRL_ST_POS) | (7 << INT_MDIO_CTRL_XDIV_POS) | (2 << INT_MDIO_CTRL_TA_POS) | (1 << INT_MDIO_CTRL_MIIM_POS) | (1 << INT_MDIO_CTRL_MCDIV_POS); mdio_ld_cmd = nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4))); if (mdio_ld_cmd & INT_MDIO_CTRL_CMD_LOAD) { nlm_write_nae_reg(nae_base, NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus*4)), (mdio_ld_cmd & ~INT_MDIO_CTRL_CMD_LOAD)); } /* load data into ctrl data reg */ nlm_write_nae_reg(nae_base, NAE_REG(block, intf_type, (INT_MDIO_CTRL_DATA + bus * 4)), val); nlm_write_nae_reg(nae_base, NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)), ctrlval); nlm_write_nae_reg(nae_base, NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)), ctrlval | (1 << INT_MDIO_CTRL_LOAD_POS)); /* poll master busy bit until it is not busy */ while(nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type, (INT_MDIO_RD_STAT + bus * 4))) & INT_MDIO_STAT_MBSY) { } nlm_write_nae_reg(nae_base, NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)), ctrlval); return (0); } int nlm_int_gmac_mdio_reset(uint64_t nae_base, int bus, int block, int intf_type) { uint32_t val; - val = (7 << INT_MDIO_CTRL_XDIV_POS) | + val = (7 << INT_MDIO_CTRL_XDIV_POS) | (1 << INT_MDIO_CTRL_MCDIV_POS) | (INT_MDIO_CTRL_SMP); nlm_write_nae_reg(nae_base, - NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)), + NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)), val | INT_MDIO_CTRL_RST); nlm_write_nae_reg(nae_base, - NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)), + NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)), val); return (0); } /* * nae_gmac_mdio_read - Read sgmii phy register * * Input parameters: * bus - bus number, nae has two external gmac bus: 0 and 1 * phyaddr - PHY's address * regidx - index of register to read * * Return value: * value read (16 bits), or 0xffffffff if an error occurred. */ int nlm_gmac_mdio_read(uint64_t nae_base, int bus, int block, int intf_type, int phyaddr, int regidx) { uint32_t mdio_ld_cmd; uint32_t ctrlval; mdio_ld_cmd = nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL + bus * 4))); if (mdio_ld_cmd & EXT_G_MDIO_CMD_LCD) { nlm_write_nae_reg(nae_base, - NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), + NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), (mdio_ld_cmd & ~EXT_G_MDIO_CMD_LCD)); while(nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type, (EXT_G0_MDIO_RD_STAT + bus * 4))) & EXT_G_MDIO_STAT_MBSY); } ctrlval = EXT_G_MDIO_CMD_SP | (phyaddr << EXT_G_MDIO_PHYADDR_POS) | (regidx << EXT_G_MDIO_REGADDR_POS); if (nlm_is_xlp8xx_ax() || nlm_is_xlp8xx_b0() || nlm_is_xlp3xx_ax()) - ctrlval |= EXT_G_MDIO_DIV; + ctrlval |= EXT_G_MDIO_DIV; else ctrlval |= EXT_G_MDIO_DIV_WITH_HW_DIV64; - nlm_write_nae_reg(nae_base, - NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), + nlm_write_nae_reg(nae_base, + NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), ctrlval); nlm_write_nae_reg(nae_base, - NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), + NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), ctrlval | (1<<18)); DELAY(1000); /* poll master busy bit until it is not busy */ while(nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type, (EXT_G0_MDIO_RD_STAT + bus * 4))) & EXT_G_MDIO_STAT_MBSY); nlm_write_nae_reg(nae_base, - NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), + NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), ctrlval); /* Read the data back */ return nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type, (EXT_G0_MDIO_RD_STAT + bus * 4))); } /* * nae_gmac_mdio_write -Write sgmac mii PHY register. * * Input parameters: * bus - bus number, nae has two external gmac bus: 0 and 1 * phyaddr - PHY to use * regidx - register within the PHY * val - data to write to register * * Return value: * 0 - success */ int nlm_gmac_mdio_write(uint64_t nae_base, int bus, int block, int intf_type, int phyaddr, int regidx, uint16_t val) { uint32_t mdio_ld_cmd; uint32_t ctrlval; mdio_ld_cmd = nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL + bus * 4))); if (mdio_ld_cmd & EXT_G_MDIO_CMD_LCD) { nlm_write_nae_reg(nae_base, - NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), + NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), (mdio_ld_cmd & ~EXT_G_MDIO_CMD_LCD)); while(nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type, (EXT_G0_MDIO_RD_STAT + bus * 4))) & EXT_G_MDIO_STAT_MBSY); } /* load data into ctrl data reg */ nlm_write_nae_reg(nae_base, - NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL_DATA+bus*4)), + NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL_DATA+bus*4)), val); ctrlval = EXT_G_MDIO_CMD_SP | (phyaddr << EXT_G_MDIO_PHYADDR_POS) | (regidx << EXT_G_MDIO_REGADDR_POS); if (nlm_is_xlp8xx_ax() || nlm_is_xlp8xx_b0() || nlm_is_xlp3xx_ax()) - ctrlval |= EXT_G_MDIO_DIV; + ctrlval |= EXT_G_MDIO_DIV; else ctrlval |= EXT_G_MDIO_DIV_WITH_HW_DIV64; nlm_write_nae_reg(nae_base, - NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), + NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), ctrlval); nlm_write_nae_reg(nae_base, - NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), + NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), ctrlval | EXT_G_MDIO_CMD_LCD); DELAY(1000); /* poll master busy bit until it is not busy */ while(nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type, (EXT_G0_MDIO_RD_STAT + bus * 4))) & EXT_G_MDIO_STAT_MBSY); nlm_write_nae_reg(nae_base, - NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), + NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), ctrlval); return (0); } /* * nae_gmac_mdio_reset -Reset sgmii mdio module. * * Input parameters: * bus - bus number, nae has two external gmac bus: 0 and 1 * * Return value: * 0 - success */ int nlm_gmac_mdio_reset(uint64_t nae_base, int bus, int block, int intf_type) { uint32_t ctrlval; ctrlval = nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4))); if (nlm_is_xlp8xx_ax() || nlm_is_xlp8xx_b0() || nlm_is_xlp3xx_ax()) ctrlval |= EXT_G_MDIO_DIV; else ctrlval |= EXT_G_MDIO_DIV_WITH_HW_DIV64; nlm_write_nae_reg(nae_base, - NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL + bus * 4)), + NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL + bus * 4)), EXT_G_MDIO_MMRST | ctrlval); nlm_write_nae_reg(nae_base, NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL + bus * 4)), ctrlval); return (0); } /* * nlm_mdio_reset_all : reset all internal and external MDIO */ void nlm_mdio_reset_all(uint64_t nae_base) { /* reset internal MDIO */ nlm_int_gmac_mdio_reset(nae_base, 0, BLOCK_7, LANE_CFG); /* reset external MDIO */ nlm_gmac_mdio_reset(nae_base, 0, BLOCK_7, LANE_CFG); nlm_gmac_mdio_reset(nae_base, 1, BLOCK_7, LANE_CFG); } Index: head/sys/mips/nlm/dev/net/nae.c =================================================================== --- head/sys/mips/nlm/dev/net/nae.c (revision 279387) +++ head/sys/mips/nlm/dev/net/nae.c (revision 279388) @@ -1,1454 +1,1454 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include void nlm_nae_flush_free_fifo(uint64_t nae_base, int nblocks) { uint32_t data, fifo_mask; fifo_mask = (1 << (4 * nblocks)) - 1; nlm_write_nae_reg(nae_base, NAE_RX_FREE_FIFO_POP, fifo_mask); do { data = nlm_read_nae_reg(nae_base, NAE_RX_FREE_FIFO_POP); } while (data != fifo_mask); nlm_write_nae_reg(nae_base, NAE_RX_FREE_FIFO_POP, 0); } void nlm_program_nae_parser_seq_fifo(uint64_t nae_base, int maxports, struct nae_port_config *cfg) { uint32_t val; int start = 0, size, i; for (i = 0; i < maxports; i++) { size = cfg[i].pseq_fifo_size; val = (((size & 0x1fff) << 17) | ((start & 0xfff) << 5) | (i & 0x1f)); nlm_write_nae_reg(nae_base, NAE_PARSER_SEQ_FIFO_CFG, val); start += size; } } void nlm_setup_rx_cal_cfg(uint64_t nae_base, int total_num_ports, struct nae_port_config *cfg) { int rx_slots = 0, port; int cal_len, cal = 0, last_free = 0; uint32_t val; for (port = 0; port < total_num_ports; port++) { if (cfg[port].rx_slots_reqd) rx_slots += cfg[port].rx_slots_reqd; if (rx_slots > MAX_CAL_SLOTS) { rx_slots = MAX_CAL_SLOTS; break; } } cal_len = rx_slots - 1; do { if (cal >= MAX_CAL_SLOTS) break; last_free = cal; for (port = 0; port < total_num_ports; port++) { if (cfg[port].rx_slots_reqd > 0) { val = (cal_len << 16) | (port << 8) | cal; nlm_write_nae_reg(nae_base, NAE_RX_IF_SLOT_CAL, val); cal++; cfg[port].rx_slots_reqd--; } } if (last_free == cal) break; } while (1); } void nlm_setup_tx_cal_cfg(uint64_t nae_base, int total_num_ports, struct nae_port_config *cfg) { int tx_slots = 0, port; int cal = 0, last_free = 0; uint32_t val; for (port = 0; port < total_num_ports; port++) { if (cfg[port].tx_slots_reqd) tx_slots += cfg[port].tx_slots_reqd; if (tx_slots > MAX_CAL_SLOTS) { tx_slots = MAX_CAL_SLOTS; break; } } nlm_write_nae_reg(nae_base, NAE_EGR_NIOR_CAL_LEN_REG, tx_slots - 1); do { if (cal >= MAX_CAL_SLOTS) break; last_free = cal; for (port = 0; port < total_num_ports; port++) { if (cfg[port].tx_slots_reqd > 0) { val = (port << 7) | (cal << 1) | 1; nlm_write_nae_reg(nae_base, NAE_EGR_NIOR_CRDT_CAL_PROG, val); cal++; cfg[port].tx_slots_reqd--; } } if (last_free == cal) break; } while (1); } void nlm_deflate_frin_fifo_carving(uint64_t nae_base, int total_num_ports) { const int minimum_size = 8; uint32_t value; int intf, start; for (intf = 0; intf < total_num_ports; intf++) { start = minimum_size * intf; value = (minimum_size << 20) | (start << 8) | (intf); nlm_write_nae_reg(nae_base, NAE_FREE_IN_FIFO_CFG, value); } } void nlm_reset_nae(int node) { uint64_t sysbase; uint64_t nae_base; uint64_t nae_pcibase; uint32_t rx_config; uint32_t bar0; int reset_bit; sysbase = nlm_get_sys_regbase(node); nae_base = nlm_get_nae_regbase(node); nae_pcibase = nlm_get_nae_pcibase(node); bar0 = nlm_read_pci_reg(nae_pcibase, XLP_PCI_CFGREG4); #if BYTE_ORDER == LITTLE_ENDIAN if (nlm_is_xlp8xx_ax()) { uint8_t val; /* membar fixup */ val = (bar0 >> 24) & 0xff; bar0 = (val << 24) | (val << 16) | (val << 8) | val; } #endif if (nlm_is_xlp3xx()) reset_bit = 6; else reset_bit = 9; /* Reset NAE */ nlm_write_sys_reg(sysbase, SYS_RESET, (1 << reset_bit)); /* XXXJC - 1s delay here may be too high */ DELAY(1000000); nlm_write_sys_reg(sysbase, SYS_RESET, (0 << reset_bit)); DELAY(1000000); rx_config = nlm_read_nae_reg(nae_base, NAE_RX_CONFIG); nlm_write_pci_reg(nae_pcibase, XLP_PCI_CFGREG4, bar0); } void nlm_setup_poe_class_config(uint64_t nae_base, int max_poe_classes, int num_contexts, int *poe_cl_tbl) { uint32_t val; int i, max_poe_class_ctxt_tbl_sz; max_poe_class_ctxt_tbl_sz = num_contexts/max_poe_classes; for (i = 0; i < max_poe_class_ctxt_tbl_sz; i++) { val = (poe_cl_tbl[(i/max_poe_classes) & 0x7] << 8) | i; nlm_write_nae_reg(nae_base, NAE_POE_CLASS_SETUP_CFG, val); } } void nlm_setup_vfbid_mapping(uint64_t nae_base) { uint32_t val; int dest_vc, vfbid; /* 127 is max vfbid */ for (vfbid = 127; vfbid >= 0; vfbid--) { dest_vc = nlm_get_vfbid_mapping(vfbid); if (dest_vc < 0) continue; val = (dest_vc << 16) | (vfbid << 4) | 1; nlm_write_nae_reg(nae_base, NAE_VFBID_DESTMAP_CMD, val); } } void nlm_setup_flow_crc_poly(uint64_t nae_base, uint32_t poly) { nlm_write_nae_reg(nae_base, NAE_FLOW_CRC16_POLY_CFG, poly); } void nlm_setup_iface_fifo_cfg(uint64_t nae_base, int maxports, struct nae_port_config *cfg) { uint32_t reg; int fifo_xoff_thresh = 12; int i, size; int cur_iface_start = 0; for (i = 0; i < maxports; i++) { size = cfg[i].iface_fifo_size; reg = ((fifo_xoff_thresh << 25) | ((size & 0x1ff) << 16) | ((cur_iface_start & 0xff) << 8) | (i & 0x1f)); nlm_write_nae_reg(nae_base, NAE_IFACE_FIFO_CFG, reg); cur_iface_start += size; } } void nlm_setup_rx_base_config(uint64_t nae_base, int maxports, struct nae_port_config *cfg) { int base = 0; uint32_t val; int i; int id; for (i = 0; i < (maxports/2); i++) { id = 0x12 + i; /* RX_IF_BASE_CONFIG0 */ val = (base & 0x3ff); base += cfg[(i * 2)].num_channels; val |= ((base & 0x3ff) << 16); base += cfg[(i * 2) + 1].num_channels; nlm_write_nae_reg(nae_base, NAE_REG(7, 0, id), val); } } void nlm_setup_rx_buf_config(uint64_t nae_base, int maxports, struct nae_port_config *cfg) { uint32_t val; int i, sz, k; int context = 0; int base = 0; for (i = 0; i < maxports; i++) { if (cfg[i].type == UNKNOWN) continue; for (k = 0; k < cfg[i].num_channels; k++) { /* write index (context num) */ nlm_write_nae_reg(nae_base, NAE_RXBUF_BASE_DPTH_ADDR, (context+k)); /* write value (rx buf sizes) */ sz = cfg[i].rxbuf_size; val = 0x80000000 | ((base << 2) & 0x3fff); /* base */ val |= (((sz << 2) & 0x3fff) << 16); /* size */ nlm_write_nae_reg(nae_base, NAE_RXBUF_BASE_DPTH, val); nlm_write_nae_reg(nae_base, NAE_RXBUF_BASE_DPTH, (0x7fffffff & val)); base += sz; } context += cfg[i].num_channels; } } void nlm_setup_freein_fifo_cfg(uint64_t nae_base, struct nae_port_config *cfg) { int size, i; uint32_t reg; int start = 0, maxbufpool; if (nlm_is_xlp8xx()) maxbufpool = MAX_FREE_FIFO_POOL_8XX; else maxbufpool = MAX_FREE_FIFO_POOL_3XX; for (i = 0; i < maxbufpool; i++) { /* Each entry represents 2 descs; hence division by 2 */ size = (cfg[i].num_free_descs / 2); if (size == 0) size = 8; reg = ((size & 0x3ff ) << 20) | /* fcSize */ ((start & 0x1ff) << 8) | /* fcStart */ (i & 0x1f); nlm_write_nae_reg(nae_base, NAE_FREE_IN_FIFO_CFG, reg); start += size; } } /* XXX function name */ int nlm_get_flow_mask(int num_ports) { const int max_bits = 5; /* upto 32 ports */ int i; /* Compute the number of bits to needed to * represent all the ports */ for (i = 0; i < max_bits; i++) { if (num_ports <= (2 << i)) return (i + 1); } return (max_bits); } void nlm_program_flow_cfg(uint64_t nae_base, int port, uint32_t cur_flow_base, uint32_t flow_mask) { uint32_t val; val = (cur_flow_base << 16) | port; val |= ((flow_mask & 0x1f) << 8); nlm_write_nae_reg(nae_base, NAE_FLOW_BASEMASK_CFG, val); } void xlp_ax_nae_lane_reset_txpll(uint64_t nae_base, int block, int lane_ctrl, int mode) { uint32_t val = 0, saved_data; int rext_sel = 0; val = PHY_LANE_CTRL_RST | PHY_LANE_CTRL_PWRDOWN | (mode << PHY_LANE_CTRL_PHYMODE_POS); /* set comma bypass for XAUI */ if (mode != PHYMODE_SGMII) val |= PHY_LANE_CTRL_BPC_XAUI; nlm_write_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl), val); if (lane_ctrl != 4) { rext_sel = (1 << 23); if (mode != PHYMODE_SGMII) rext_sel |= PHY_LANE_CTRL_BPC_XAUI; val = nlm_read_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl)); val &= ~PHY_LANE_CTRL_RST; val |= rext_sel; /* Resetting PMA for non-zero lanes */ nlm_write_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl), val); DELAY(20000); /* 20 ms delay, XXXJC: needed? */ val |= PHY_LANE_CTRL_RST; nlm_write_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl), val); val = 0; } /* Come out of reset for TXPLL */ saved_data = nlm_read_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl)) & 0xFFC00000; nlm_write_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl), (0x66 << PHY_LANE_CTRL_ADDR_POS) | PHY_LANE_CTRL_CMD_READ | PHY_LANE_CTRL_CMD_START | PHY_LANE_CTRL_RST | rext_sel | val ); while (((val = nlm_read_nae_reg(nae_base, - NAE_REG(block, PHY, lane_ctrl))) & + NAE_REG(block, PHY, lane_ctrl))) & PHY_LANE_CTRL_CMD_PENDING)); val &= 0xFF; /* set bit[4] to 0 */ val &= ~(1 << 4); nlm_write_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl), (0x66 << PHY_LANE_CTRL_ADDR_POS) | PHY_LANE_CTRL_CMD_WRITE | PHY_LANE_CTRL_CMD_START | (0x0 << 19) /* (0x4 << 19) */ | rext_sel | saved_data | val ); /* re-do */ nlm_write_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl), (0x66 << PHY_LANE_CTRL_ADDR_POS) | PHY_LANE_CTRL_CMD_WRITE | PHY_LANE_CTRL_CMD_START | (0x0 << 19) /* (0x4 << 19) */ | rext_sel | saved_data | val ); while (!((val = nlm_read_nae_reg(nae_base, - NAE_REG(block, PHY, (lane_ctrl - PHY_LANE_0_CTRL)))) & + NAE_REG(block, PHY, (lane_ctrl - PHY_LANE_0_CTRL)))) & PHY_LANE_STAT_PCR)); /* Clear the Power Down bit */ val = nlm_read_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl)); val &= ~((1 << 29) | (0x7ffff)); nlm_write_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl), (rext_sel | val)); } void xlp_nae_lane_reset_txpll(uint64_t nae_base, int block, int lane_ctrl, int mode) { uint32_t val = 0; int rext_sel = 0; if (lane_ctrl != 4) rext_sel = (1 << 23); val = nlm_read_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl)); /* set comma bypass for XAUI */ if (mode != PHYMODE_SGMII) val |= PHY_LANE_CTRL_BPC_XAUI; val |= 0x100000; val |= (mode << PHY_LANE_CTRL_PHYMODE_POS); val &= ~(0x20000); nlm_write_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl), val); val = nlm_read_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl)); val |= 0x40000000; nlm_write_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl), val); /* clear the power down bit */ val = nlm_read_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl)); val &= ~( (1 << 29) | (0x7ffff)); nlm_write_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl), rext_sel | val); } void xlp_nae_config_lane_gmac(uint64_t nae_base, int cplx_mask) { int block, lane_ctrl; int cplx_lane_enable; int lane_enable = 0; cplx_lane_enable = LM_SGMII | (LM_SGMII << 4) | (LM_SGMII << 8) | (LM_SGMII << 12); /* Lane mode progamming */ block = 7; /* Complexes 0, 1 */ if (cplx_mask & 0x1) lane_enable |= cplx_lane_enable; if (cplx_mask & 0x2) lane_enable |= (cplx_lane_enable << 16); if (lane_enable) { nlm_write_nae_reg(nae_base, NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_0_1), lane_enable); lane_enable = 0; } /* Complexes 2 3 */ if (cplx_mask & 0x4) lane_enable |= cplx_lane_enable; if (cplx_mask & 0x8) lane_enable |= (cplx_lane_enable << 16); nlm_write_nae_reg(nae_base, NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_2_3), lane_enable); /* complex 4 */ /* XXXJC : fix duplicate code */ if (cplx_mask & 0x10) { nlm_write_nae_reg(nae_base, NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_4), ((LM_SGMII << 4) | LM_SGMII)); for (lane_ctrl = PHY_LANE_0_CTRL; lane_ctrl <= PHY_LANE_1_CTRL; lane_ctrl++) { if (!nlm_is_xlp8xx_ax()) xlp_nae_lane_reset_txpll(nae_base, 4, lane_ctrl, PHYMODE_SGMII); else xlp_ax_nae_lane_reset_txpll(nae_base, 4, lane_ctrl, PHYMODE_SGMII); } } for (block = 0; block < 4; block++) { if ((cplx_mask & (1 << block)) == 0) continue; for (lane_ctrl = PHY_LANE_0_CTRL; lane_ctrl <= PHY_LANE_3_CTRL; lane_ctrl++) { if (!nlm_is_xlp8xx_ax()) xlp_nae_lane_reset_txpll(nae_base, block, lane_ctrl, PHYMODE_SGMII); else xlp_ax_nae_lane_reset_txpll(nae_base, block, lane_ctrl, PHYMODE_SGMII); } } } void config_egress_fifo_carvings(uint64_t nae_base, int hwport, int start_ctxt, int num_ctxts, int max_ctxts, struct nae_port_config *cfg) { static uint32_t cur_start[6] = {0, 0, 0, 0, 0, 0}; uint32_t data = 0; uint32_t start = 0, size, offset; int i, limit; limit = start_ctxt + num_ctxts; /* Stage 2 FIFO */ start = cur_start[0]; for (i = start_ctxt; i < limit; i++) { size = cfg[hwport].stg2_fifo_size / max_ctxts; if (size) offset = size - 1; else offset = size; if (offset > cfg[hwport].max_stg2_offset) offset = cfg[hwport].max_stg2_offset; - data = offset << 23 | - start << 11 | + data = offset << 23 | + start << 11 | i << 1 | 1; nlm_write_nae_reg(nae_base, NAE_STG2_PMEM_PROG, data); start += size; } cur_start[0] = start; /* EH FIFO */ - start = cur_start[1]; + start = cur_start[1]; for (i = start_ctxt; i < limit; i++) { size = cfg[hwport].eh_fifo_size / max_ctxts; if (size) offset = size - 1; else offset = size ; if (offset > cfg[hwport].max_eh_offset) offset = cfg[hwport].max_eh_offset; - data = offset << 23 | + data = offset << 23 | start << 11 | i << 1 | 1; nlm_write_nae_reg(nae_base, NAE_EH_PMEM_PROG, data); start += size; } cur_start[1] = start; /* FROUT FIFO */ - start = cur_start[2]; + start = cur_start[2]; for (i = start_ctxt; i < limit; i++) { size = cfg[hwport].frout_fifo_size / max_ctxts; if (size) offset = size - 1; else offset = size ; if (offset > cfg[hwport].max_frout_offset) offset = cfg[hwport].max_frout_offset; - data = offset << 23 | - start << 11 | + data = offset << 23 | + start << 11 | i << 1 | 1; nlm_write_nae_reg(nae_base, NAE_FREE_PMEM_PROG, data); start += size; } cur_start[2] = start; /* MS FIFO */ - start = cur_start[3]; + start = cur_start[3]; for (i = start_ctxt; i < limit; i++) { size = cfg[hwport].ms_fifo_size / max_ctxts; if (size) offset = size - 1; else offset = size ; if (offset > cfg[hwport].max_ms_offset) offset = cfg[hwport].max_ms_offset; data = offset << 22 | /* FIXME in PRM */ - start << 11 | + start << 11 | i << 1 | 1; nlm_write_nae_reg(nae_base, NAE_STR_PMEM_CMD, data); start += size; } cur_start[3] = start; /* PKT FIFO */ - start = cur_start[4]; + start = cur_start[4]; for (i = start_ctxt; i < limit; i++) { size = cfg[hwport].pkt_fifo_size / max_ctxts; if (size) offset = size - 1; else offset = size ; if (offset > cfg[hwport].max_pmem_offset) offset = cfg[hwport].max_pmem_offset; nlm_write_nae_reg(nae_base, NAE_TX_PKT_PMEM_CMD1, offset); - data = start << 11 | + data = start << 11 | i << 1 | 1; nlm_write_nae_reg(nae_base, NAE_TX_PKT_PMEM_CMD0, data); start += size; } cur_start[4] = start; /* PKT LEN FIFO */ - start = cur_start[5]; + start = cur_start[5]; for (i = start_ctxt; i < limit; i++) { size = cfg[hwport].pktlen_fifo_size / max_ctxts; if (size) offset = size - 1; else offset = size ; - data = offset << 22 | - start << 11 | + data = offset << 22 | + start << 11 | i << 1 | 1; nlm_write_nae_reg(nae_base, NAE_TX_PKTLEN_PMEM_CMD, data); start += size; } cur_start[5] = start; } void config_egress_fifo_credits(uint64_t nae_base, int hwport, int start_ctxt, int num_ctxts, int max_ctxts, struct nae_port_config *cfg) { uint32_t data, credit, max_credit; int i, limit; limit = start_ctxt + num_ctxts; /* Stage1 -> Stage2 */ max_credit = cfg[hwport].max_stg2_offset + 1; for (i = start_ctxt; i < limit; i++) { credit = cfg[hwport].stg1_2_credit / max_ctxts; if (credit > max_credit) credit = max_credit; - data = credit << 16 | + data = credit << 16 | i << 4 | 1; nlm_write_nae_reg(nae_base, NAE_STG1_STG2CRDT_CMD, data); } /* Stage2 -> EH */ max_credit = cfg[hwport].max_eh_offset + 1; for (i = start_ctxt; i < limit; i++) { credit = cfg[hwport].stg2_eh_credit / max_ctxts; if (credit > max_credit) credit = max_credit; - data = credit << 16 | + data = credit << 16 | i << 4 | 1; nlm_write_nae_reg(nae_base, NAE_STG2_EHCRDT_CMD, data); } /* Stage2 -> Frout */ max_credit = cfg[hwport].max_frout_offset + 1; for (i = start_ctxt; i < limit; i++) { credit = cfg[hwport].stg2_frout_credit / max_ctxts; if (credit > max_credit) credit = max_credit; - data = credit << 16 | + data = credit << 16 | i << 4 | 1; nlm_write_nae_reg(nae_base, NAE_EH_FREECRDT_CMD, data); } /* Stage2 -> MS */ max_credit = cfg[hwport].max_ms_offset + 1; for (i = start_ctxt; i < limit; i++) { credit = cfg[hwport].stg2_ms_credit / max_ctxts; if (credit > max_credit) credit = max_credit; - data = credit << 16 | + data = credit << 16 | i << 4 | 1; nlm_write_nae_reg(nae_base, NAE_STG2_STRCRDT_CMD, data); } } void nlm_config_freein_fifo_uniq_cfg(uint64_t nae_base, int port, int nblock_free_desc) { uint32_t val; int size_in_clines; size_in_clines = (nblock_free_desc / NAE_CACHELINE_SIZE); val = (size_in_clines << 8) | (port & 0x1f); nlm_write_nae_reg(nae_base, NAE_FREEIN_FIFO_UNIQ_SZ_CFG, val); } /* XXXJC: redundant, see ucore_spray_config() */ void nlm_config_ucore_iface_mask_cfg(uint64_t nae_base, int port, int nblock_ucore_mask) { uint32_t val; val = ( 0x1U << 31) | ((nblock_ucore_mask & 0xffff) << 8) | (port & 0x1f); nlm_write_nae_reg(nae_base, NAE_UCORE_IFACEMASK_CFG, val); } int nlm_nae_init_netior(uint64_t nae_base, int nblocks) { uint32_t ctrl1, ctrl2, ctrl3; if (nblocks == 5) ctrl3 = 0x07 << 18; else ctrl3 = 0; switch (nblocks) { case 2: ctrl1 = 0xff; ctrl2 = 0x0707; break; case 4: case 5: ctrl1 = 0xfffff; ctrl2 = 0x07070707; break; default: printf("WARNING: unsupported blocks %d\n", nblocks); return (-1); } nlm_write_nae_reg(nae_base, NAE_LANE_CFG_SOFTRESET, 0); nlm_write_nae_reg(nae_base, NAE_NETIOR_MISC_CTRL3, ctrl3); nlm_write_nae_reg(nae_base, NAE_NETIOR_MISC_CTRL2, ctrl2); nlm_write_nae_reg(nae_base, NAE_NETIOR_MISC_CTRL1, ctrl1); nlm_write_nae_reg(nae_base, NAE_NETIOR_MISC_CTRL1, 0x0); return (0); } void nlm_nae_init_ingress(uint64_t nae_base, uint32_t desc_size) { uint32_t rx_cfg; uint32_t parser_threshold = 384; rx_cfg = nlm_read_nae_reg(nae_base, NAE_RX_CONFIG); rx_cfg &= ~(0x3 << 1); /* reset max message size */ rx_cfg &= ~(0xff << 4); /* clear freein desc cluster size */ rx_cfg &= ~(0x3f << 24); /* reset rx status mask */ /*XXX: why not 7f */ rx_cfg |= 1; /* rx enable */ rx_cfg |= (0x0 << 1); /* max message size */ rx_cfg |= (0x43 & 0x7f) << 24; /* rx status mask */ rx_cfg |= ((desc_size / 64) & 0xff) << 4; /* freein desc cluster size */ nlm_write_nae_reg(nae_base, NAE_RX_CONFIG, rx_cfg); nlm_write_nae_reg(nae_base, NAE_PARSER_CONFIG, (parser_threshold & 0x3ff) | (((parser_threshold / desc_size) + 1) & 0xff) << 12 | (((parser_threshold / 64) % desc_size) & 0xff) << 20); /*nlm_write_nae_reg(nae_base, NAE_RX_FREE_FIFO_THRESH, 33);*/ } void nlm_nae_init_egress(uint64_t nae_base) { uint32_t tx_cfg; tx_cfg = nlm_read_nae_reg(nae_base, NAE_TX_CONFIG); if (!nlm_is_xlp8xx_ax()) { nlm_write_nae_reg(nae_base, NAE_TX_CONFIG, tx_cfg | 0x1 | /* tx enable */ 0x2 | /* tx ace */ 0x4 | /* tx compatible */ (1 << 3)); } else { nlm_write_nae_reg(nae_base, NAE_TX_CONFIG, tx_cfg | 0x1 | /* tx enable */ 0x2); /* tx ace */ } } uint32_t ucore_spray_config(uint32_t interface, uint32_t ucore_mask, int cmd) { return ((cmd & 0x1) << 31) | ((ucore_mask & 0xffff) << 8) | (interface & 0x1f); } void nlm_nae_init_ucore(uint64_t nae_base, int if_num, u_int ucore_mask) { uint32_t ucfg; ucfg = ucore_spray_config(if_num, ucore_mask, 1); /* 1 : write */ nlm_write_nae_reg(nae_base, NAE_UCORE_IFACEMASK_CFG, ucfg); } uint64_t nae_tx_desc(u_int type, u_int rdex, u_int fbid, u_int len, uint64_t addr) { return ((uint64_t)type << 62) | ((uint64_t)rdex << 61) | ((uint64_t)fbid << 54) | ((uint64_t)len << 40) | addr; } void nlm_setup_l2type(uint64_t nae_base, int hwport, uint32_t l2extlen, uint32_t l2extoff, uint32_t extra_hdrsize, uint32_t proto_offset, uint32_t fixed_hdroff, uint32_t l2proto) { uint32_t val; val = ((l2extlen & 0x3f) << 26) | ((l2extoff & 0x3f) << 20) | ((extra_hdrsize & 0x3f) << 14) | ((proto_offset & 0x3f) << 8) | ((fixed_hdroff & 0x3f) << 2) | (l2proto & 0x3); nlm_write_nae_reg(nae_base, (NAE_L2_TYPE_PORT0 + hwport), val); } void nlm_setup_l3ctable_mask(uint64_t nae_base, int hwport, uint32_t ptmask, uint32_t l3portmask) { uint32_t val; val = ((ptmask & 0x1) << 6) | ((l3portmask & 0x1) << 5) | (hwport & 0x1f); nlm_write_nae_reg(nae_base, NAE_L3_CTABLE_MASK0, val); } void nlm_setup_l3ctable_even(uint64_t nae_base, int entry, uint32_t l3hdroff, uint32_t ipcsum_en, uint32_t l4protooff, uint32_t l2proto, uint32_t eth_type) { uint32_t val; val = ((l3hdroff & 0x3f) << 26) | ((l4protooff & 0x3f) << 20) | ((ipcsum_en & 0x1) << 18) | ((l2proto & 0x3) << 16) | (eth_type & 0xffff); nlm_write_nae_reg(nae_base, (NAE_L3CTABLE0 + (entry * 2)), val); } void nlm_setup_l3ctable_odd(uint64_t nae_base, int entry, uint32_t l3off0, uint32_t l3len0, uint32_t l3off1, uint32_t l3len1, uint32_t l3off2, uint32_t l3len2) { uint32_t val; val = ((l3off0 & 0x3f) << 26) | ((l3len0 & 0x1f) << 21) | ((l3off1 & 0x3f) << 15) | ((l3len1 & 0x1f) << 10) | ((l3off2 & 0x3f) << 4) | (l3len2 & 0xf); nlm_write_nae_reg(nae_base, (NAE_L3CTABLE0 + ((entry * 2) + 1)), val); } void nlm_setup_l4ctable_even(uint64_t nae_base, int entry, uint32_t im, uint32_t l3cm, uint32_t l4pm, uint32_t port, uint32_t l3camaddr, uint32_t l4proto) { uint32_t val; val = ((im & 0x1) << 19) | ((l3cm & 0x1) << 18) | ((l4pm & 0x1) << 17) | ((port & 0x1f) << 12) | ((l3camaddr & 0xf) << 8) | (l4proto & 0xff); nlm_write_nae_reg(nae_base, (NAE_L4CTABLE0 + (entry * 2)), val); } void nlm_setup_l4ctable_odd(uint64_t nae_base, int entry, uint32_t l4off0, uint32_t l4len0, uint32_t l4off1, uint32_t l4len1) { uint32_t val; val = ((l4off0 & 0x3f) << 21) | ((l4len0 & 0xf) << 17) | ((l4off1 & 0x3f) << 11) | (l4len1 & 0xf); nlm_write_nae_reg(nae_base, (NAE_L4CTABLE0 + ((entry * 2) + 1)), val); } void nlm_enable_hardware_parser(uint64_t nae_base) { uint32_t val; val = nlm_read_nae_reg(nae_base, NAE_RX_CONFIG); val |= (1 << 12); /* hardware parser enable */ nlm_write_nae_reg(nae_base, NAE_RX_CONFIG, val); - /*********************************************** + /*********************************************** * program L3 CAM table ***********************************************/ /* - * entry-0 is ipv4 MPLS type 1 label + * entry-0 is ipv4 MPLS type 1 label */ /* l3hdroff = 4 bytes, ether_type = 0x8847 for MPLS_type1 */ nlm_setup_l3ctable_even(nae_base, 0, 4, 1, 9, 1, 0x8847); /* l3off0 (8 bytes) -> l3len0 (1 byte) := ip proto * l3off1 (12 bytes) -> l3len1 (4 bytes) := src ip * l3off2 (16 bytes) -> l3len2 (4 bytes) := dst ip */ nlm_setup_l3ctable_odd(nae_base, 0, 9, 1, 12, 4, 16, 4); /* * entry-1 is for ethernet IPv4 packets */ nlm_setup_l3ctable_even(nae_base, 1, 0, 1, 9, 1, 0x0800); /* l3off0 (8 bytes) -> l3len0 (1 byte) := ip proto * l3off1 (12 bytes) -> l3len1 (4 bytes) := src ip * l3off2 (16 bytes) -> l3len2 (4 bytes) := dst ip */ nlm_setup_l3ctable_odd(nae_base, 1, 9, 1, 12, 4, 16, 4); /* * entry-2 is for ethernet IPv6 packets */ nlm_setup_l3ctable_even(nae_base, 2, 0, 1, 6, 1, 0x86dd); /* l3off0 (6 bytes) -> l3len0 (1 byte) := next header (ip proto) * l3off1 (8 bytes) -> l3len1 (16 bytes) := src ip * l3off2 (24 bytes) -> l3len2 (16 bytes) := dst ip */ nlm_setup_l3ctable_odd(nae_base, 2, 6, 1, 8, 16, 24, 16); /* * entry-3 is for ethernet ARP packets */ nlm_setup_l3ctable_even(nae_base, 3, 0, 0, 9, 1, 0x0806); /* extract 30 bytes from packet start */ nlm_setup_l3ctable_odd(nae_base, 3, 0, 30, 0, 0, 0, 0); /* * entry-4 is for ethernet FCoE packets */ nlm_setup_l3ctable_even(nae_base, 4, 0, 0, 9, 1, 0x8906); /* FCoE packet consists of 4 byte start-of-frame, * and 24 bytes of frame header, followed by - * 64 bytes of optional-header (ESP, network..), + * 64 bytes of optional-header (ESP, network..), * 2048 bytes of payload, 36 bytes of optional * "fill bytes" or ESP trailer, 4 bytes of CRC, * and 4 bytes of end-of-frame - * We extract the first 4 + 24 = 28 bytes + * We extract the first 4 + 24 = 28 bytes */ nlm_setup_l3ctable_odd(nae_base, 4, 0, 28, 0, 0, 0, 0); /* * entry-5 is for vlan tagged frames (0x8100) */ nlm_setup_l3ctable_even(nae_base, 5, 0, 0, 9, 1, 0x8100); /* we extract 31 bytes from the payload */ nlm_setup_l3ctable_odd(nae_base, 5, 0, 31, 0, 0, 0, 0); /* * entry-6 is for ieee 802.1ad provider bridging * tagged frames (0x88a8) */ nlm_setup_l3ctable_even(nae_base, 6, 0, 0, 9, 1, 0x88a8); /* we extract 31 bytes from the payload */ nlm_setup_l3ctable_odd(nae_base, 6, 0, 31, 0, 0, 0, 0); /* * entry-7 is for Cisco's Q-in-Q tagged frames (0x9100) */ nlm_setup_l3ctable_even(nae_base, 7, 0, 0, 9, 1, 0x9100); /* we extract 31 bytes from the payload */ nlm_setup_l3ctable_odd(nae_base, 7, 0, 31, 0, 0, 0, 0); /* * entry-8 is for Ethernet Jumbo frames (0x8870) */ nlm_setup_l3ctable_even(nae_base, 8, 0, 0, 9, 1, 0x8870); /* we extract 31 bytes from the payload */ nlm_setup_l3ctable_odd(nae_base, 8, 0, 31, 0, 0, 0, 0); /* * entry-9 is for MPLS Multicast frames (0x8848) */ nlm_setup_l3ctable_even(nae_base, 9, 0, 0, 9, 1, 0x8848); /* we extract 31 bytes from the payload */ nlm_setup_l3ctable_odd(nae_base, 9, 0, 31, 0, 0, 0, 0); /* * entry-10 is for IEEE 802.1ae MAC Security frames (0x88e5) */ nlm_setup_l3ctable_even(nae_base, 10, 0, 0, 9, 1, 0x88e5); /* we extract 31 bytes from the payload */ nlm_setup_l3ctable_odd(nae_base, 10, 0, 31, 0, 0, 0, 0); /* * entry-11 is for PTP frames (0x88f7) */ nlm_setup_l3ctable_even(nae_base, 11, 0, 0, 9, 1, 0x88f7); /* PTP messages can be sent as UDP messages over * IPv4 or IPv6; and as a raw ethernet message * with ethertype 0x88f7. The message contents * are the same for UDP or ethernet based encapsulations * The header is 34 bytes long, and we extract * it all out. */ nlm_setup_l3ctable_odd(nae_base, 11, 0, 31, 31, 2, 0, 0); /* * entry-12 is for ethernet Link Control Protocol (LCP) * used with PPPoE */ nlm_setup_l3ctable_even(nae_base, 12, 0, 0, 9, 1, 0xc021); /* LCP packet consists of 1 byte of code, 1 byte of * identifier and two bytes of length followed by * data (upto length bytes). * We extract 4 bytes from start of packet */ nlm_setup_l3ctable_odd(nae_base, 12, 0, 4, 0, 0, 0, 0); /* * entry-13 is for ethernet Link Quality Report (0xc025) * used with PPPoE */ nlm_setup_l3ctable_even(nae_base, 13, 0, 0, 9, 1, 0xc025); /* We extract 31 bytes from packet start */ nlm_setup_l3ctable_odd(nae_base, 13, 0, 31, 0, 0, 0, 0); /* * entry-14 is for PPPoE Session (0x8864) */ nlm_setup_l3ctable_even(nae_base, 14, 0, 0, 9, 1, 0x8864); /* We extract 31 bytes from packet start */ nlm_setup_l3ctable_odd(nae_base, 14, 0, 31, 0, 0, 0, 0); /* * entry-15 - default entry */ nlm_setup_l3ctable_even(nae_base, 15, 0, 0, 0, 0, 0x0000); /* We extract 31 bytes from packet start */ nlm_setup_l3ctable_odd(nae_base, 15, 0, 31, 0, 0, 0, 0); - /*********************************************** + /*********************************************** * program L4 CAM table ***********************************************/ /* * entry-0 - tcp packets (0x6) */ nlm_setup_l4ctable_even(nae_base, 0, 0, 0, 1, 0, 0, 0x6); - /* tcp header is 20 bytes without tcp options + /* tcp header is 20 bytes without tcp options * We extract 20 bytes from tcp start */ nlm_setup_l4ctable_odd(nae_base, 0, 0, 15, 15, 5); /* * entry-1 - udp packets (0x11) */ nlm_setup_l4ctable_even(nae_base, 1, 0, 0, 1, 0, 0, 0x11); /* udp header is 8 bytes in size. * We extract 8 bytes from udp start */ nlm_setup_l4ctable_odd(nae_base, 1, 0, 8, 0, 0); /* * entry-2 - sctp packets (0x84) */ nlm_setup_l4ctable_even(nae_base, 2, 0, 0, 1, 0, 0, 0x84); /* sctp packets have a 12 byte generic header * and various chunks. * We extract 12 bytes from sctp start */ nlm_setup_l4ctable_odd(nae_base, 2, 0, 12, 0, 0); /* * entry-3 - RDP packets (0x1b) */ nlm_setup_l4ctable_even(nae_base, 3, 0, 0, 1, 0, 0, 0x1b); - /* RDP packets have 18 bytes of generic header + /* RDP packets have 18 bytes of generic header * before variable header starts. * We extract 18 bytes from rdp start */ nlm_setup_l4ctable_odd(nae_base, 3, 0, 15, 15, 3); /* * entry-4 - DCCP packets (0x21) */ nlm_setup_l4ctable_even(nae_base, 4, 0, 0, 1, 0, 0, 0x21); /* DCCP has two types of generic headers of * sizes 16 bytes and 12 bytes if X = 1. * We extract 16 bytes from dccp start */ nlm_setup_l4ctable_odd(nae_base, 4, 0, 15, 15, 1); /* * entry-5 - ipv6 encapsulated in ipv4 packets (0x29) */ nlm_setup_l4ctable_even(nae_base, 5, 0, 0, 1, 0, 0, 0x29); /* ipv4 header is 20 bytes excluding IP options. * We extract 20 bytes from IPv4 start */ nlm_setup_l4ctable_odd(nae_base, 5, 0, 15, 15, 5); /* * entry-6 - ip in ip encapsulation packets (0x04) */ nlm_setup_l4ctable_even(nae_base, 6, 0, 0, 1, 0, 0, 0x04); /* ipv4 header is 20 bytes excluding IP options. * We extract 20 bytes from ipv4 start */ nlm_setup_l4ctable_odd(nae_base, 6, 0, 15, 15, 5); /* * entry-7 - default entry (0x0) */ nlm_setup_l4ctable_even(nae_base, 7, 0, 0, 1, 0, 0, 0x0); /* We extract 20 bytes from packet start */ nlm_setup_l4ctable_odd(nae_base, 7, 0, 15, 15, 5); } void nlm_enable_hardware_parser_per_port(uint64_t nae_base, int block, int port) { int hwport = (block * 4) + (port & 0x3); /* program L2 and L3 header extraction for each port */ /* enable ethernet L2 mode on port */ nlm_setup_l2type(nae_base, hwport, 0, 0, 0, 0, 0, 1); /* l2proto and ethtype included in l3cam */ nlm_setup_l3ctable_mask(nae_base, hwport, 1, 0); } void nlm_prepad_enable(uint64_t nae_base, int size) { uint32_t val; val = nlm_read_nae_reg(nae_base, NAE_RX_CONFIG); val |= (1 << 13); /* prepad enable */ val |= ((size & 0x3) << 22); /* prepad size */ nlm_write_nae_reg(nae_base, NAE_RX_CONFIG, val); } void nlm_setup_1588_timer(uint64_t nae_base, struct nae_port_config *cfg) { uint32_t hi, lo, val; hi = cfg[0].ieee1588_userval >> 32; lo = cfg[0].ieee1588_userval & 0xffffffff; nlm_write_nae_reg(nae_base, NAE_1588_PTP_USER_VALUE_HI, hi); nlm_write_nae_reg(nae_base, NAE_1588_PTP_USER_VALUE_LO, lo); hi = cfg[0].ieee1588_ptpoff >> 32; lo = cfg[0].ieee1588_ptpoff & 0xffffffff; nlm_write_nae_reg(nae_base, NAE_1588_PTP_OFFSET_HI, hi); nlm_write_nae_reg(nae_base, NAE_1588_PTP_OFFSET_LO, lo); hi = cfg[0].ieee1588_tmr1 >> 32; lo = cfg[0].ieee1588_tmr1 & 0xffffffff; nlm_write_nae_reg(nae_base, NAE_1588_PTP_TMR1_HI, hi); nlm_write_nae_reg(nae_base, NAE_1588_PTP_TMR1_LO, lo); hi = cfg[0].ieee1588_tmr2 >> 32; lo = cfg[0].ieee1588_tmr2 & 0xffffffff; nlm_write_nae_reg(nae_base, NAE_1588_PTP_TMR2_HI, hi); nlm_write_nae_reg(nae_base, NAE_1588_PTP_TMR2_LO, lo); hi = cfg[0].ieee1588_tmr3 >> 32; lo = cfg[0].ieee1588_tmr3 & 0xffffffff; nlm_write_nae_reg(nae_base, NAE_1588_PTP_TMR3_HI, hi); nlm_write_nae_reg(nae_base, NAE_1588_PTP_TMR3_LO, lo); nlm_write_nae_reg(nae_base, NAE_1588_PTP_INC_INTG, cfg[0].ieee1588_inc_intg); nlm_write_nae_reg(nae_base, NAE_1588_PTP_INC_NUM, cfg[0].ieee1588_inc_num); nlm_write_nae_reg(nae_base, NAE_1588_PTP_INC_DEN, cfg[0].ieee1588_inc_den); val = nlm_read_nae_reg(nae_base, NAE_1588_PTP_CONTROL); /* set and clear freq_mul = 1 */ nlm_write_nae_reg(nae_base, NAE_1588_PTP_CONTROL, val | (0x1 << 1)); nlm_write_nae_reg(nae_base, NAE_1588_PTP_CONTROL, val); /* set and clear load_user_val = 1 */ nlm_write_nae_reg(nae_base, NAE_1588_PTP_CONTROL, val | (0x1 << 6)); nlm_write_nae_reg(nae_base, NAE_1588_PTP_CONTROL, val); } void nlm_mac_enable(uint64_t nae_base, int nblock, int port_type, int port) { uint32_t mac_cfg1, xaui_cfg; uint32_t netwk_inf; int iface = port & 0x3; switch(port_type) { case SGMIIC: netwk_inf = nlm_read_nae_reg(nae_base, SGMII_NET_IFACE_CTRL(nblock, iface)); nlm_write_nae_reg(nae_base, SGMII_NET_IFACE_CTRL(nblock, iface), netwk_inf | (1 << 2)); /* enable tx */ mac_cfg1 = nlm_read_nae_reg(nae_base, SGMII_MAC_CONF1(nblock, iface)); nlm_write_nae_reg(nae_base, SGMII_MAC_CONF1(nblock, iface), mac_cfg1 | (1 << 2) | /* rx enable */ 1); /* tx enable */ break; case XAUIC: xaui_cfg = nlm_read_nae_reg(nae_base, XAUI_CONFIG1(nblock)); nlm_write_nae_reg(nae_base, XAUI_CONFIG1(nblock), xaui_cfg | XAUI_CONFIG_TFEN | XAUI_CONFIG_RFEN); break; case ILC: break; } } void nlm_mac_disable(uint64_t nae_base, int nblock, int port_type, int port) { uint32_t mac_cfg1, xaui_cfg; uint32_t netwk_inf; int iface = port & 0x3; switch(port_type) { case SGMIIC: mac_cfg1 = nlm_read_nae_reg(nae_base, SGMII_MAC_CONF1(nblock, iface)); nlm_write_nae_reg(nae_base, SGMII_MAC_CONF1(nblock, iface), mac_cfg1 & ~((1 << 2) | /* rx enable */ 1)); /* tx enable */ netwk_inf = nlm_read_nae_reg(nae_base, SGMII_NET_IFACE_CTRL(nblock, iface)); nlm_write_nae_reg(nae_base, SGMII_NET_IFACE_CTRL(nblock, iface), netwk_inf & ~(1 << 2)); /* enable tx */ break; case XAUIC: xaui_cfg = nlm_read_nae_reg(nae_base, XAUI_CONFIG1(nblock)); nlm_write_nae_reg(nae_base, XAUI_CONFIG1(nblock), xaui_cfg & ~(XAUI_CONFIG_TFEN | XAUI_CONFIG_RFEN)); break; case ILC: break; } } /* * Set IOR credits for the ports in ifmask to valmask */ static void nlm_nae_set_ior_credit(uint64_t nae_base, uint32_t ifmask, uint32_t valmask) { uint32_t tx_config, tx_ior_credit; tx_ior_credit = nlm_read_nae_reg(nae_base, NAE_TX_IORCRDT_INIT); tx_ior_credit &= ~ifmask; tx_ior_credit |= valmask; nlm_write_nae_reg(nae_base, NAE_TX_IORCRDT_INIT, tx_ior_credit); tx_config = nlm_read_nae_reg(nae_base, NAE_TX_CONFIG); /* need to toggle these bits for credits to be loaded */ nlm_write_nae_reg(nae_base, NAE_TX_CONFIG, tx_config | (TXINITIORCR(ifmask))); nlm_write_nae_reg(nae_base, NAE_TX_CONFIG, tx_config & ~(TXINITIORCR(ifmask))); } int nlm_nae_open_if(uint64_t nae_base, int nblock, int port_type, int port, uint32_t desc_size) { uint32_t netwk_inf; uint32_t mac_cfg1, netior_ctrl3; int iface, iface_ctrl_reg, iface_ctrl3_reg, conf1_reg, conf2_reg; switch (port_type) { case XAUIC: netwk_inf = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock)); netwk_inf |= (1 << NETIOR_XGMAC_STATS_CLR_POS); nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock), netwk_inf); nlm_nae_set_ior_credit(nae_base, 0xf << port, 0xf << port); break; case ILC: nlm_nae_set_ior_credit(nae_base, 0xff << port, 0xff << port); break; case SGMIIC: nlm_nae_set_ior_credit(nae_base, 0x1 << port, 0); /* * XXXJC: split this and merge to sgmii.c * some of this is duplicated from there. */ /* init phy id to access internal PCS */ iface = port & 0x3; iface_ctrl_reg = SGMII_NET_IFACE_CTRL(nblock, iface); conf1_reg = SGMII_MAC_CONF1(nblock, iface); conf2_reg = SGMII_MAC_CONF2(nblock, iface); netwk_inf = nlm_read_nae_reg(nae_base, iface_ctrl_reg); netwk_inf &= 0x7ffffff; netwk_inf |= (port << 27); nlm_write_nae_reg(nae_base, iface_ctrl_reg, netwk_inf); /* Sofreset sgmii port - set bit 11 to 0 */ netwk_inf &= 0xfffff7ff; nlm_write_nae_reg(nae_base, iface_ctrl_reg, netwk_inf); /* Reset Gmac */ mac_cfg1 = nlm_read_nae_reg(nae_base, conf1_reg); nlm_write_nae_reg(nae_base, conf1_reg, mac_cfg1 | (1U << 31) | /* soft reset */ (1 << 2) | /* rx enable */ (1)); /* tx enable */ /* default to 1G */ nlm_write_nae_reg(nae_base, - conf2_reg, + conf2_reg, (0x7 << 12) | /* interface preamble length */ (0x2 << 8) | /* interface mode */ (0x1 << 2) | /* pad crc enable */ (0x1)); /* full duplex */ /* clear gmac reset */ mac_cfg1 = nlm_read_nae_reg(nae_base, conf1_reg); nlm_write_nae_reg(nae_base, conf1_reg, mac_cfg1 & ~(1U << 31)); /* clear speed debug bit */ iface_ctrl3_reg = SGMII_NET_IFACE_CTRL3(nblock, iface); netior_ctrl3 = nlm_read_nae_reg(nae_base, iface_ctrl3_reg); nlm_write_nae_reg(nae_base, iface_ctrl3_reg, netior_ctrl3 & ~(1 << 6)); /* disable TX, RX for now */ mac_cfg1 = nlm_read_nae_reg(nae_base, conf1_reg); nlm_write_nae_reg(nae_base, conf1_reg, mac_cfg1 & ~(0x5)); netwk_inf = nlm_read_nae_reg(nae_base, iface_ctrl_reg); nlm_write_nae_reg(nae_base, iface_ctrl_reg, netwk_inf & ~(0x1 << 2)); /* clear stats counters */ netwk_inf = nlm_read_nae_reg(nae_base, iface_ctrl_reg); nlm_write_nae_reg(nae_base, iface_ctrl_reg, netwk_inf | (1 << 15)); /* enable stats counters */ netwk_inf = nlm_read_nae_reg(nae_base, iface_ctrl_reg); nlm_write_nae_reg(nae_base, iface_ctrl_reg, (netwk_inf & ~(1 << 15)) | (1 << 16)); /* flow control? */ mac_cfg1 = nlm_read_nae_reg(nae_base, conf1_reg); nlm_write_nae_reg(nae_base, conf1_reg, mac_cfg1 | (0x3 << 4)); - break; + break; } nlm_nae_init_ingress(nae_base, desc_size); nlm_nae_init_egress(nae_base); return (0); } Index: head/sys/mips/nlm/dev/net/sgmii.c =================================================================== --- head/sys/mips/nlm/dev/net/sgmii.c (revision 279387) +++ head/sys/mips/nlm/dev/net/sgmii.c (revision 279388) @@ -1,209 +1,209 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include void nlm_configure_sgmii_interface(uint64_t nae_base, int block, int port, int mtu, int loopback) { uint32_t data1, data2; /* Apply a soft reset */ data1 = (0x1 << 31); /* soft reset */ if (loopback) data1 |= (0x01 << 8); data1 |= (0x01 << 2); /* Rx enable */ data1 |= 0x01; /* Tx enable */ nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF1), data1); data2 = (0x7 << 12) | /* pre-amble length=7 */ (0x2 << 8) | /* byteMode */ 0x1; /* fullDuplex */ nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF2), data2); /* Remove a soft reset */ data1 &= ~(0x01 << 31); nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF1), data1); /* setup sgmii max frame length */ nlm_write_nae_reg(nae_base, SGMII_MAX_FRAME(block, port), mtu); } void nlm_sgmii_pcs_init(uint64_t nae_base, uint32_t cplx_mask) { xlp_nae_config_lane_gmac(nae_base, cplx_mask); } void nlm_nae_setup_mac(uint64_t nae_base, int nblock, int iface, int reset, int rx_en, int tx_en, int speed, int duplex) { uint32_t mac_cfg1, mac_cfg2, netwk_inf; mac_cfg1 = nlm_read_nae_reg(nae_base, SGMII_MAC_CONF1(nblock,iface)); mac_cfg2 = nlm_read_nae_reg(nae_base, SGMII_MAC_CONF2(nblock,iface)); netwk_inf = nlm_read_nae_reg(nae_base, SGMII_NET_IFACE_CTRL(nblock, iface)); mac_cfg1 &= ~(0x1 << 31); /* remove reset */ mac_cfg1 &= ~(0x1 << 2); /* remove rx */ mac_cfg1 &= ~(0x1); /* remove tx */ mac_cfg2 &= ~(0x3 << 8); /* remove interface mode bits */ mac_cfg2 &= ~(0x1); /* remove duplex */ netwk_inf &= ~(0x1 << 2); /* remove tx */ netwk_inf &= ~(0x3); /* remove speed */ switch (speed) { case NLM_SGMII_SPEED_10: netwk_inf |= 0x0; /* 2.5 Mhz clock for 10 Mbps */ mac_cfg2 |= (0x1 << 8); /* enable 10/100 Mbps */ break; case NLM_SGMII_SPEED_100: netwk_inf |= 0x1; /* 25 Mhz clock for 100 Mbps */ mac_cfg2 |= (0x1 << 8); /* enable 10/100 Mbps */ break; default: /* make it as 1G */ netwk_inf |= 0x2; /* 125 Mhz clock for 1G */ mac_cfg2 |= (0x2 << 8); /* enable 1G */ break; } if (reset) mac_cfg1 |= (0x1 << 31); /* set reset */ if (rx_en) mac_cfg1 |= (0x1 << 2); /* set rx */ nlm_write_nae_reg(nae_base, SGMII_NET_IFACE_CTRL(nblock, iface), netwk_inf); if (tx_en) { mac_cfg1 |= 0x1; /* set tx */ netwk_inf |= (0x1 << 2); /* set tx */ } switch (duplex) { case NLM_SGMII_DUPLEX_HALF: /* duplexity is already set to half duplex */ break; default: mac_cfg2 |= 0x1; /* set full duplex */ } nlm_write_nae_reg(nae_base, SGMII_MAC_CONF1(nblock, iface), mac_cfg1); nlm_write_nae_reg(nae_base, SGMII_MAC_CONF2(nblock, iface), mac_cfg2); nlm_write_nae_reg(nae_base, SGMII_NET_IFACE_CTRL(nblock, iface), netwk_inf); } void nlm_nae_setup_rx_mode_sgmii(uint64_t base, int nblock, int iface, int port_type, int broadcast_en, int multicast_en, int pause_en, int promisc_en) { uint32_t val; /* bit[17] of vlan_typefilter - allows packet matching in MAC. * When DA filtering is disabled, this bit and bit[16] should * be zero. * bit[16] of vlan_typefilter - Allows hash matching to be used * for DA filtering. When DA filtering is disabled, this bit and * bit[17] should be zero. * Both bits have to be set only if you want to turn on both * features / modes. */ if (promisc_en == 1) { val = nlm_read_nae_reg(base, SGMII_NETIOR_VLANTYPE_FILTER(nblock, iface)); val &= (~(0x3 << 16)); nlm_write_nae_reg(base, SGMII_NETIOR_VLANTYPE_FILTER(nblock, iface), val); } else { val = nlm_read_nae_reg(base, SGMII_NETIOR_VLANTYPE_FILTER(nblock, iface)); val |= (0x1 << 17); nlm_write_nae_reg(base, SGMII_NETIOR_VLANTYPE_FILTER(nblock, iface), val); } val = ((broadcast_en & 0x1) << 10) | ((pause_en & 0x1) << 9) | ((multicast_en & 0x1) << 8) | ((promisc_en & 0x1) << 7) | /* unicast_enable - enables promisc mode */ 1; /* MAC address is always valid */ nlm_write_nae_reg(base, SGMII_MAC_FILTER_CONFIG(nblock, iface), val); } void nlm_nae_setup_mac_addr_sgmii(uint64_t base, int nblock, int iface, int port_type, uint8_t *mac_addr) { nlm_write_nae_reg(base, SGMII_MAC_ADDR0_LO(nblock, iface), (mac_addr[5] << 24) | (mac_addr[4] << 16) | (mac_addr[3] << 8) | mac_addr[2]); nlm_write_nae_reg(base, SGMII_MAC_ADDR0_HI(nblock, iface), (mac_addr[1] << 24) | (mac_addr[0] << 16)); nlm_write_nae_reg(base, SGMII_MAC_ADDR_MASK0_LO(nblock, iface), 0xffffffff); nlm_write_nae_reg(base, SGMII_MAC_ADDR_MASK0_HI(nblock, iface), 0xffffffff); nlm_nae_setup_rx_mode_sgmii(base, nblock, iface, SGMIIC, 1, /* broadcast enabled */ 1, /* multicast enabled */ 0, /* do not accept pause frames */ 0 /* promisc mode disabled */ ); } Index: head/sys/mips/nlm/dev/net/ucore/crt0_basic.S =================================================================== --- head/sys/mips/nlm/dev/net/ucore/crt0_basic.S (revision 279387) +++ head/sys/mips/nlm/dev/net/ucore/crt0_basic.S (revision 279388) @@ -1,66 +1,66 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #include .text .align 2 .globl _start .ent _start _start: .set noreorder la gp, _gp - .end _start + .end _start .globl __stack .ent zerobss zerobss: la v0, _fbss la v1, _end 3: sw zero, 0(v0) bltu v0,v1,3b addiu v0,v0,4 # executed in delay slot la sp, __stack # set stack pointer .end zerobss .ent init init: addiu a1,sp,32 # argv = sp + 32 addiu a2,sp,40 # envp = sp + 40 sw zero,(a1) # argv[argc] = 0 sw zero,(a2) # envp[0] = 0 jal main # call the program start function move a0,zero # set argc to 0 1: b 1b nop .end init Index: head/sys/mips/nlm/dev/net/ucore/ld.ucore.S =================================================================== --- head/sys/mips/nlm/dev/net/ucore/ld.ucore.S (revision 279387) +++ head/sys/mips/nlm/dev/net/ucore/ld.ucore.S (revision 279388) @@ -1,162 +1,162 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ ENTRY(_start) OUTPUT_FORMAT(elf32-tradbigmips) __DYNAMIC = 0; SECTIONS { . = 0x0; _loadaddr = . ; /* ----------------------------------------- */ .text : { _ftext = . ; PROVIDE (eprol = .); _shim_reg = . ; *(.text) *(.text.*) *(.gnu.linkonce.t*) *(.mips16.fn.*) *(.mips16.call.*) } .init : { KEEP(*(.init)) *(.init) } .fini : { *(.fini) } .rel.sdata : { PROVIDE (__runtime_reloc_start = .); *(.rel.sdata) PROVIDE (__runtime_reloc_stop = .); } PROVIDE (etext = .); .ctors : { KEEP (*crtbegin.o(.ctors)) KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } . = .; .rodata : { *(.rdata) *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) } . = . + (0x1000 - .) ; /* ----------------------------------------- */ . = 0x8000 ; magicstart = . ; .magicregs : { *(.magicregs) } magicend = . ; /* ----------------------------------------- */ - . = 0x18000 ; + . = 0x18000 ; shmemstart = . ; .sharedmem : { *(.sharedmem) } shmemend = . ; /* ----------------------------------------- */ . = 0xFF800 ; .data : { *(.data) *(.data.*) *(.gnu.linkonce.d*) } . = ALIGN(8); .lit8 : { *(.lit8) } .lit4 : { *(.lit4) } .sdata : { *(.sdata) *(.sdata.*) *(.gnu.linkonce.s*) } . = ALIGN (8); PROVIDE (edata = .); _edata = .; _fbss = .; .sbss : { *(.sbss) *(.scommon) } .bss : { _bss_start = . ; *(.bss) *(COMMON) } _bss_end = . ; _end = .; _gp = . ; __global = _gp ; . = ALIGN (8); PROVIDE(__stackmarker = .) ; - . = 0xFFA00 ; + . = 0xFFA00 ; /* 32 + 4(argc) + 4(argv), aligned to 64 */ - PROVIDE(__stack = . - 64); + PROVIDE(__stack = . - 64); /* ----------------------------------------- */ . = 0xFFE00 ; .pktbuf : { *(.pktbuf) } . = . + (0x100000 - .) ; PROVIDE(_endaddr = 0x0 + 0x100000); } Index: head/sys/mips/nlm/dev/net/ucore/ucore.h =================================================================== --- head/sys/mips/nlm/dev/net/ucore/ucore.h (revision 279387) +++ head/sys/mips/nlm/dev/net/ucore/ucore.h (revision 279388) @@ -1,352 +1,352 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef __NLM_UCORE_H__ #define __NLM_UCORE_H__ /* Microcode registers */ #define UCORE_OUTBUF_DONE 0x8000 #define UCORE_RX_PKT_RDY 0x8004 #define UCORE_RX_PKT_INFO 0x8008 #define UCORE_CAM0 0x800c #define UCORE_CAM1 0x8010 #define UCORE_CAM2 0x8014 #define UCORE_CAM3 0x8018 #define UCORE_CAM_RESULT 0x801c #define UCORE_CSUMINFO 0x8020 #define UCORE_CRCINFO 0x8024 #define UCORE_CRCPOS 0x8028 #define UCORE_FR_FIFOEMPTY 0x802c #define UCORE_PKT_DISTR 0x8030 #define PACKET_MEMORY 0xFFE00 #define PACKET_DATA_OFFSET 64 #define SHARED_SCRATCH_MEM 0x18000 /* Distribution mode */ #define VAL_PDM(x) (((x) & 0x7) << 0) /* Dest distribution or distribution list */ #define VAL_DEST(x) (((x) & 0x3ff) << 8) #define VAL_PDL(x) (((x) & 0xf) << 4) /*output buffer done*/ #define VAL_FSV(x) (x << 19) #define VAL_FFS(x) (x << 14) #define FWD_DEST_ONLY 1 #define FWD_ENQ_DIST_VEC 2 #define FWD_ENQ_DEST 3 #define FWD_DIST_VEC 4 #define FWD_ENQ_DIST_VEC_SER 6 #define FWD_ENQ_DEST_SER 7 #define USE_HASH_DST (1 << 20) static __inline unsigned int nlm_read_ucore_reg(int reg) { volatile unsigned int *addr = (volatile void *)reg; return (*addr); } static __inline void nlm_write_ucore_reg(int reg, unsigned int val) { volatile unsigned int *addr = (volatile void *)reg; *addr = val; } #define NLM_DEFINE_UCORE(name, reg) \ static __inline unsigned int \ nlm_read_ucore_##name(void) \ { \ return nlm_read_ucore_reg(reg); \ } \ \ static __inline void \ nlm_write_ucore_##name(unsigned int v) \ { \ nlm_write_ucore_reg(reg, v); \ } struct __hack NLM_DEFINE_UCORE(obufdone, UCORE_OUTBUF_DONE); NLM_DEFINE_UCORE(rxpktrdy, UCORE_RX_PKT_RDY); NLM_DEFINE_UCORE(rxpktinfo, UCORE_RX_PKT_INFO); NLM_DEFINE_UCORE(cam0, UCORE_CAM0); NLM_DEFINE_UCORE(cam1, UCORE_CAM1); NLM_DEFINE_UCORE(cam2, UCORE_CAM2); NLM_DEFINE_UCORE(cam3, UCORE_CAM3); NLM_DEFINE_UCORE(camresult, UCORE_CAM_RESULT); NLM_DEFINE_UCORE(csuminfo, UCORE_CSUMINFO); NLM_DEFINE_UCORE(crcinfo, UCORE_CRCINFO); NLM_DEFINE_UCORE(crcpos, UCORE_CRCPOS); NLM_DEFINE_UCORE(freefifo_empty, UCORE_FR_FIFOEMPTY); NLM_DEFINE_UCORE(pktdistr, UCORE_PKT_DISTR); /* * l3cachelines - number of cache lines to allocate into l3 * fsv - 0 : use interface-id for selecting the free fifo pool * 1 : use free fifo pool selected by FFS field * ffs - selects which free fifo pool to use to take a free fifo - * prepad_en - If this field is set to 1, part or all of the + * prepad_en - If this field is set to 1, part or all of the * 64 byte prepad seen by micro engines, is written * infront of every packet. - * prepad_ovride - If this field is 1, the ucore system uses + * prepad_ovride - If this field is 1, the ucore system uses * prepad configuration defined in this register, * 0 means that it uses the configuration defined * in NAE RX_CONFIG register * prepad_size - number of 16 byte words in the 64-byte prepad * seen by micro engines and dma'ed to memory as * pkt prepad. This field is meaningful only if * prepad_en and prepad_ovride is set. * 0 : 1 word * 1 : 2 words * 2 : 3 words * 3 : 4 words * prepad[0-3]: writing 0 to this means that the 1st 16 byte offset * of prepad in micro engine, gets setup as prepad0/1/2/3. * prepad word. * 1 : means 2nd 16 byte chunk in prepad0/1/2/3 * 2 : means 3rd 16 byte chunk in prepad0/1/2/3 * 3 : means 4rth 16 byte chunk in prepad0/1/2/3 * pkt_discard - packet will be discarded if this is set to 1 * rd5 - value (single bit) to be inserted in bit 5, the unclassified * pkt bit of receive descriptor. If this bit is set, HPRE bit * should also be set in ucore_rxpktready register */ static __inline__ void nlm_ucore_pkt_done(int l3cachelines, int fsv, int ffs, int prepad_en, int prepad_ovride, int prepad_size, int prepad0, int prepad1, int prepad2, int prepad3, int pkt_discard, int rd5) { unsigned int val = 0; val |= ((l3cachelines & 0xfff) << 20); val |= ((fsv & 0x1) << 19); val |= ((ffs & 0x1f) << 14); val |= ((prepad_en & 0x1) << 3); val |= ((prepad_ovride & 0x1) << 2); val |= ((prepad_size & 0x3) << 12); val |= ((prepad0 & 0x3) << 4); val |= ((prepad1 & 0x3) << 6); val |= ((prepad2 & 0x3) << 8); val |= ((prepad3 & 0x3) << 10); val |= ((pkt_discard & 0x1) << 1); val |= ((rd5 & 0x1) << 0); nlm_write_ucore_obufdone(val); } -/* Get the class full vector field from POE. +/* Get the class full vector field from POE. * The POE maintains a threshold for each class. * A bit in this field will be set corresponding to the class approaching * class full status. */ static __inline__ int nlm_ucore_get_rxpkt_poeclassfullvec(unsigned int pktrdy) { return ((pktrdy >> 24) & 0xff); } /* This function returns 1 if the hardware parser extraction process * resulted in an error. Else, returns 0. */ static __inline__ int nlm_ucore_get_rxpkt_hwparsererr(unsigned int pktrdy) { return ((pktrdy >> 23) & 0x1); } /* This function returns the context number assigned to incoming - * packet + * packet */ static __inline__ int nlm_ucore_get_rxpkt_context(unsigned int pktrdy) { return ((pktrdy >> 13) & 0x3ff); } /* this function returns the channel number of incoming packet, * and applies only to interlaken. */ static __inline__ int nlm_ucore_get_rxpkt_channel(unsigned int pktrdy) { return ((pktrdy >> 5) & 0xff); } /* This function returns the interface number on which the pkt * was received */ static __inline__ int nlm_ucore_get_rxpkt_interface(unsigned int pktrdy) { return (pktrdy & 0x1f); } -/* This function returns 1 if end of packet (EOP) is set in - * packet data. +/* This function returns 1 if end of packet (EOP) is set in + * packet data. */ static __inline__ int nlm_ucore_get_rxpkt_eop(unsigned int rxpkt_info) { return ((rxpkt_info >> 9) & 0x1); } /* This function returns packet length of received pkt */ static __inline__ int nlm_ucore_get_rxpktlen(unsigned int rxpkt_info) { return (rxpkt_info & 0x1ff); } /* this function sets up the ucore TCAM keys. */ static __inline__ void nlm_ucore_setup_camkey(unsigned int cam_key0, unsigned int cam_key1, unsigned int cam_key2, unsigned int cam_key3) { nlm_write_ucore_cam0(cam_key0); nlm_write_ucore_cam1(cam_key1); nlm_write_ucore_cam2(cam_key2); nlm_write_ucore_cam3(cam_key3); } /* This function checks if the cam result is valid or not. * If valid, it returns the result, else it returns 0. */ static __inline__ int nlm_ucore_get_cam_result(unsigned int cam_result) { if (((cam_result >> 15) & 0x1) == 1) /* valid result */ return (cam_result & 0x3fff); return 0; } /* This function sets up the csum in ucore. * iphdr_start - defines the start of ip header (to check - is this byte * position???) - * iphdr_len - This field is auto filled by h/w parser if zero, else + * iphdr_len - This field is auto filled by h/w parser if zero, else * the value defined will be used. */ static __inline__ void nlm_ucore_csum_setup(int iphdr_start, int iphdr_len) { unsigned int val = 0; val |= ((iphdr_len & 0xff) << 8); val |= (iphdr_len & 0xff); nlm_write_ucore_csuminfo(val); } /* crcpos - position of crc in pkt. If crc position is within startcrc and - * endcrc, zero out these bytes in the packet before computing crc. This + * endcrc, zero out these bytes in the packet before computing crc. This * field is not needed for FCoE. * cps - If 1, uses the polynomial in RX_CRC_POLY1 of NAE register. * if 0, uses the polynomial in RX_CRC_POLY0 of NAE register. * fcoe - If this is 1, crc calculation starts from 'startCRC' and the CRC * engine ends calculation before the last byte. * cbm - if 1, enables crc byte mirroring, where bits within a byte will get * reversed (mirrored) during calculation of crc. * cfi - If 1, performs a final inversion of crc before comarison is done during * pkt reception. * startcrc - This field is always required for both FCoE and SCTP crc. - * endcrc - This information needs to be setup only for SCTP. For FCoE this + * endcrc - This information needs to be setup only for SCTP. For FCoE this * information is provided by hardware. * valid - if set to 1, CRC status is placed into bit 2 of rx descriptor * if set to 0, TCP checksum status is placed into bit 2 of rx descriptor * keysize - defines the number of bytes in the pre-pad that contains the key */ static __inline__ void nlm_ucore_crc_setup(int crcpos, int cps, int cfi, int cbm, int fcoe, int keysize, int valid, int startcrc, int endcrc) { unsigned int val = 0; val |= ((cfi & 0x1) << 20); val |= ((cbm & 0x1) << 19); val |= ((fcoe & 0x1) << 18); val |= ((cps & 0x1) << 16); val |= (crcpos & 0xffff); nlm_write_ucore_crcpos(val); val = 0; val |= ((keysize & 0x3f) << 25); val |= ((valid & 0x1) << 24); val |= ((endcrc & 0xffff) << 8); val |= (startcrc & 0xff); nlm_write_ucore_crcinfo(val); } -/* This function returns a fifo empty vector, where each bit provides +/* This function returns a fifo empty vector, where each bit provides * the status of a fifo pool, where if the pool is empty the bit gets * set to 1. */ static __inline__ int nlm_ucore_get_fifoempty(unsigned int fifoempty) { return (fifoempty & 0xfffff); } /* This function controls how POE will distribute the packet. * pdm - is the packet distribution mode, where * 0x0 - means packet distribution mode is not used * 0x1 - means forwarding based on destination only (no enqueue) * 0x2 - means forwarding based on FID and distr vector (enqueue) * 0x3 - means forwarding based on dest and FID (enqueue) * 0x4 - means forwarding based on distr vec (no enqueue) * 0x6 - means forward based on FID (enqueue), distr vec and serial mode * 0x7 - means forward based on FID (enqueue), dest and serial mode * mc3 - If 1, then the 3 most significant bits of distribution list are taken * from context->class_table * pdl - poe distribution list * dest - fixed destination setup - * hash - if 1, use hash based destination + * hash - if 1, use hash based destination */ static __inline__ void nlm_ucore_setup_poepktdistr(int pdm, int mc3, int pdl, int dest, int hash) { unsigned int val = 0; val |= ((hash & 0x1) << 20); val |= ((dest & 0xfff) << 8); val |= ((pdl & 0xf) << 4); val |= ((mc3 & 0x1) << 3); val |= (pdm & 0x7); nlm_write_ucore_pktdistr(val); } #endif Index: head/sys/mips/nlm/dev/net/ucore/ucore_app.c =================================================================== --- head/sys/mips/nlm/dev/net/ucore/ucore_app.c (revision 279387) +++ head/sys/mips/nlm/dev/net/ucore/ucore_app.c (revision 279388) @@ -1,58 +1,48 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #include "ucore.h" int main(void) { -#if 0 - volatile unsigned int *pkt = - (volatile unsigned int *) (PACKET_MEMORY + PACKET_DATA_OFFSET); - int intf, hw_parser_error, context; -#endif unsigned int pktrdy; int num_cachelines = 1518 / 64 ; /* pktsize / L3 cacheline size */ /* Spray packets to using distribution vector */ while (1) { pktrdy = nlm_read_ucore_rxpktrdy(); -#if 0 - intf = pktrdy & 0x1f; - context = (pktrdy >> 13) & 0x3ff; - hw_parser_error = (pktrdy >> 23) & 0x1; -#endif nlm_ucore_setup_poepktdistr(FWD_DIST_VEC, 0, 0, 0, 0); nlm_ucore_pkt_done(num_cachelines, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); } return (0); } Index: head/sys/mips/nlm/dev/net/xaui.c =================================================================== --- head/sys/mips/nlm/dev/net/xaui.c (revision 279387) +++ head/sys/mips/nlm/dev/net/xaui.c (revision 279388) @@ -1,249 +1,249 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include void nlm_xaui_pcs_init(uint64_t nae_base, int xaui_cplx_mask) { int block, lane_ctrl, reg; int cplx_lane_enable; int lane_enable = 0; uint32_t regval; cplx_lane_enable = LM_XAUI | (LM_XAUI << 4) | (LM_XAUI << 8) | (LM_XAUI << 12); if (xaui_cplx_mask == 0) return; /* write 0x2 to enable SGMII for all lane */ block = 7; if (xaui_cplx_mask & 0x3) { /* Complexes 0, 1 */ lane_enable = nlm_read_nae_reg(nae_base, NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_0_1)); if (xaui_cplx_mask & 0x1) { /* Complex 0 */ lane_enable &= ~(0xFFFF); lane_enable |= cplx_lane_enable; } if (xaui_cplx_mask & 0x2) { /* Complex 1 */ lane_enable &= ~(0xFFFF<<16); lane_enable |= (cplx_lane_enable << 16); } nlm_write_nae_reg(nae_base, NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_0_1), lane_enable); } lane_enable = 0; if (xaui_cplx_mask & 0xc) { /* Complexes 2, 3 */ lane_enable = nlm_read_nae_reg(nae_base, NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_2_3)); if (xaui_cplx_mask & 0x4) { /* Complex 2 */ lane_enable &= ~(0xFFFF); lane_enable |= cplx_lane_enable; } if (xaui_cplx_mask & 0x8) { /* Complex 3 */ lane_enable &= ~(0xFFFF<<16); lane_enable |= (cplx_lane_enable << 16); } nlm_write_nae_reg(nae_base, NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_2_3), lane_enable); } /* Bring txpll out of reset */ for (block = 0; block < 4; block++) { if ((xaui_cplx_mask & (1 << block)) == 0) continue; for (lane_ctrl = PHY_LANE_0_CTRL; lane_ctrl <= PHY_LANE_3_CTRL; lane_ctrl++) { if (!nlm_is_xlp8xx_ax()) xlp_nae_lane_reset_txpll(nae_base, block, lane_ctrl, PHYMODE_XAUI); else xlp_ax_nae_lane_reset_txpll(nae_base, block, lane_ctrl, PHYMODE_XAUI); } } /* Wait for Rx & TX clock stable */ for (block = 0; block < 4; block++) { if ((xaui_cplx_mask & (1 << block)) == 0) continue; for (lane_ctrl = PHY_LANE_0_CTRL; lane_ctrl <= PHY_LANE_3_CTRL; lane_ctrl++) { reg = NAE_REG(block, PHY, lane_ctrl - 4); /* Wait for TX clock to be set */ do { regval = nlm_read_nae_reg(nae_base, reg); } while ((regval & LANE_TX_CLK) == 0); /* Wait for RX clock to be set */ do { regval = nlm_read_nae_reg(nae_base, reg); } while ((regval & LANE_RX_CLK) == 0); /* Wait for XAUI Lane fault to be cleared */ do { regval = nlm_read_nae_reg(nae_base, reg); } while ((regval & XAUI_LANE_FAULT) != 0); } } } void nlm_nae_setup_rx_mode_xaui(uint64_t base, int nblock, int iface, int port_type, int broadcast_en, int multicast_en, int pause_en, int promisc_en) { uint32_t val; val = ((broadcast_en & 0x1) << 10) | ((pause_en & 0x1) << 9) | ((multicast_en & 0x1) << 8) | ((promisc_en & 0x1) << 7) | /* unicast_enable - enables promisc mode */ 1; /* MAC address is always valid */ nlm_write_nae_reg(base, XAUI_MAC_FILTER_CFG(nblock), val); } void nlm_nae_setup_mac_addr_xaui(uint64_t base, int nblock, int iface, int port_type, unsigned char *mac_addr) { nlm_write_nae_reg(base, XAUI_MAC_ADDR0_LO(nblock), (mac_addr[5] << 24) | (mac_addr[4] << 16) | (mac_addr[3] << 8) | mac_addr[2]); nlm_write_nae_reg(base, XAUI_MAC_ADDR0_HI(nblock), (mac_addr[1] << 24) | (mac_addr[0] << 16)); nlm_write_nae_reg(base, XAUI_MAC_ADDR_MASK0_LO(nblock), 0xffffffff); nlm_write_nae_reg(base, XAUI_MAC_ADDR_MASK0_HI(nblock), 0xffffffff); nlm_nae_setup_rx_mode_xaui(base, nblock, iface, XAUIC, 1, /* broadcast enabled */ 1, /* multicast enabled */ 0, /* do not accept pause frames */ 0 /* promisc mode disabled */ ); } void nlm_config_xaui_mtu(uint64_t nae_base, int nblock, int max_tx_frame_sz, int max_rx_frame_sz) { uint32_t tx_words = max_tx_frame_sz >> 2; /* max_tx_frame_sz / 4 */ /* write max frame length */ nlm_write_nae_reg(nae_base, XAUI_MAX_FRAME_LEN(nblock), ((tx_words & 0x3ff) << 16) | (max_rx_frame_sz & 0xffff)); } void nlm_config_xaui(uint64_t nae_base, int nblock, int max_tx_frame_sz, int max_rx_frame_sz, int vlan_pri_en) { uint32_t val; val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock)); val &= ~(0x1 << 11); /* clear soft reset */ nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock), val); val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock)); val &= ~(0x3 << 11); /* clear soft reset and hard reset */ nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock), val); nlm_write_nae_reg(nae_base, XAUI_CONFIG0(nblock), 0xffffffff); nlm_write_nae_reg(nae_base, XAUI_CONFIG0(nblock), 0); /* Enable tx/rx frame */ val = 0x000010A8; val |= XAUI_CONFIG_LENCHK; val |= XAUI_CONFIG_GENFCS; val |= XAUI_CONFIG_PAD_64; nlm_write_nae_reg(nae_base, XAUI_CONFIG1(nblock), val); /* write max frame length */ nlm_config_xaui_mtu(nae_base, nblock, max_tx_frame_sz, max_rx_frame_sz); /* set stats counter */ val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock)); val |= (0x1 << NETIOR_XGMAC_VLAN_DC_POS); val |= (0x1 << NETIOR_XGMAC_STATS_EN_POS); if (vlan_pri_en) { val |= (0x1 << NETIOR_XGMAC_TX_PFC_EN_POS); val |= (0x1 << NETIOR_XGMAC_RX_PFC_EN_POS); val |= (0x1 << NETIOR_XGMAC_TX_PAUSE_POS); } else { val &= ~(0x1 << NETIOR_XGMAC_TX_PFC_EN_POS); val |= (0x1 << NETIOR_XGMAC_TX_PAUSE_POS); } nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock), val); /* configure on / off timer */ if (vlan_pri_en) val = 0xF1230000; /* PFC mode, offtimer = 0xf123, ontimer = 0 */ else val = 0x0000F123; /* link level FC mode, offtimer = 0xf123 */ nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL2(nblock), val); /* set xaui tx threshold */ val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL3(nblock)); val &= ~(0x1f << 10); val |= ~(15 << 10); nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL3(nblock), val); } Index: head/sys/mips/nlm/dev/net/xlpge.c =================================================================== --- head/sys/mips/nlm/dev/net/xlpge.c (revision 279387) +++ head/sys/mips/nlm/dev/net/xlpge.c (revision 279388) @@ -1,1542 +1,1542 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define __RMAN_RESOURCE_VISIBLE #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* for DELAY */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "miidevs.h" #include #include "miibus_if.h" #include #include /*#define XLP_DRIVER_LOOPBACK*/ static struct nae_port_config nae_port_config[64]; int poe_cl_tbl[MAX_POE_CLASSES] = { - 0x0, 0x249249, + 0x0, 0x249249, 0x492492, 0x6db6db, 0x924924, 0xb6db6d, 0xdb6db6, 0xffffff }; /* #define DUMP_PACKET */ -static uint64_t +static uint64_t nlm_paddr_ld(uint64_t paddr) { uint64_t xkaddr = 0x9800000000000000 | paddr; return (nlm_load_dword_daddr(xkaddr)); } struct nlm_xlp_portdata ifp_ports[64]; static uma_zone_t nl_tx_desc_zone; /* This implementation will register the following tree of device * registration: * pcibus * | * xlpnae (1 instance - virtual entity) * | * xlpge * (18 sgmii / 4 xaui / 2 interlaken instances) * | * miibus */ static int nlm_xlpnae_probe(device_t); static int nlm_xlpnae_attach(device_t); static int nlm_xlpnae_detach(device_t); static int nlm_xlpnae_suspend(device_t); static int nlm_xlpnae_resume(device_t); static int nlm_xlpnae_shutdown(device_t); static device_method_t nlm_xlpnae_methods[] = { /* Methods from the device interface */ DEVMETHOD(device_probe, nlm_xlpnae_probe), DEVMETHOD(device_attach, nlm_xlpnae_attach), DEVMETHOD(device_detach, nlm_xlpnae_detach), DEVMETHOD(device_suspend, nlm_xlpnae_suspend), DEVMETHOD(device_resume, nlm_xlpnae_resume), DEVMETHOD(device_shutdown, nlm_xlpnae_shutdown), DEVMETHOD(bus_driver_added, bus_generic_driver_added), DEVMETHOD_END }; static driver_t nlm_xlpnae_driver = { "xlpnae", nlm_xlpnae_methods, sizeof(struct nlm_xlpnae_softc) }; static devclass_t nlm_xlpnae_devclass; static int nlm_xlpge_probe(device_t); static int nlm_xlpge_attach(device_t); static int nlm_xlpge_detach(device_t); static int nlm_xlpge_suspend(device_t); static int nlm_xlpge_resume(device_t); static int nlm_xlpge_shutdown(device_t); /* mii override functions */ static int nlm_xlpge_mii_read(struct device *, int, int); static int nlm_xlpge_mii_write(struct device *, int, int, int); static void nlm_xlpge_mii_statchg(device_t); static device_method_t nlm_xlpge_methods[] = { /* Methods from the device interface */ DEVMETHOD(device_probe, nlm_xlpge_probe), DEVMETHOD(device_attach, nlm_xlpge_attach), DEVMETHOD(device_detach, nlm_xlpge_detach), DEVMETHOD(device_suspend, nlm_xlpge_suspend), DEVMETHOD(device_resume, nlm_xlpge_resume), DEVMETHOD(device_shutdown, nlm_xlpge_shutdown), - /* Methods from the nexus bus needed for explicitly + /* Methods from the nexus bus needed for explicitly * probing children when driver is loaded as a kernel module */ DEVMETHOD(miibus_readreg, nlm_xlpge_mii_read), DEVMETHOD(miibus_writereg, nlm_xlpge_mii_write), DEVMETHOD(miibus_statchg, nlm_xlpge_mii_statchg), /* Terminate method list */ DEVMETHOD_END }; static driver_t nlm_xlpge_driver = { "xlpge", nlm_xlpge_methods, sizeof(struct nlm_xlpge_softc) }; static devclass_t nlm_xlpge_devclass; DRIVER_MODULE(xlpnae, pci, nlm_xlpnae_driver, nlm_xlpnae_devclass, 0, 0); DRIVER_MODULE(xlpge, xlpnae, nlm_xlpge_driver, nlm_xlpge_devclass, 0, 0); DRIVER_MODULE(miibus, xlpge, miibus_driver, miibus_devclass, 0, 0); MODULE_DEPEND(pci, xlpnae, 1, 1, 1); MODULE_DEPEND(xlpnae, xlpge, 1, 1, 1); MODULE_DEPEND(xlpge, ether, 1, 1, 1); MODULE_DEPEND(xlpge, miibus, 1, 1, 1); #define SGMII_RCV_CONTEXT_WIDTH 8 /* prototypes */ static void nlm_xlpge_msgring_handler(int vc, int size, int code, int srcid, struct nlm_fmn_msg *msg, void *data); static void nlm_xlpge_submit_rx_free_desc(struct nlm_xlpge_softc *sc, int num); static void nlm_xlpge_init(void *addr); static void nlm_xlpge_port_disable(struct nlm_xlpge_softc *sc); static void nlm_xlpge_port_enable(struct nlm_xlpge_softc *sc); /* globals */ int dbg_on = 1; int cntx2port[524]; static __inline void atomic_incr_long(unsigned long *addr) { atomic_add_long(addr, 1); } /* * xlpnae driver implementation */ -static int +static int nlm_xlpnae_probe(device_t dev) { if (pci_get_vendor(dev) != PCI_VENDOR_NETLOGIC || pci_get_device(dev) != PCI_DEVICE_ID_NLM_NAE) return (ENXIO); return (BUS_PROBE_DEFAULT); } static void nlm_xlpnae_print_frin_desc_carving(struct nlm_xlpnae_softc *sc) { int intf; uint32_t value; int start, size; /* XXXJC: use max_ports instead of 20 ? */ for (intf = 0; intf < 20; intf++) { nlm_write_nae_reg(sc->base, NAE_FREE_IN_FIFO_CFG, (0x80000000 | intf)); value = nlm_read_nae_reg(sc->base, NAE_FREE_IN_FIFO_CFG); size = 2 * ((value >> 20) & 0x3ff); start = 2 * ((value >> 8) & 0x1ff); } } static void nlm_config_egress(struct nlm_xlpnae_softc *sc, int nblock, int context_base, int hwport, int max_channels) { int offset, num_channels; uint32_t data; num_channels = sc->portcfg[hwport].num_channels; data = (2048 << 12) | (hwport << 4) | 1; nlm_write_nae_reg(sc->base, NAE_TX_IF_BURSTMAX_CMD, data); data = ((context_base + num_channels - 1) << 22) | (context_base << 12) | (hwport << 4) | 1; nlm_write_nae_reg(sc->base, NAE_TX_DDR_ACTVLIST_CMD, data); config_egress_fifo_carvings(sc->base, hwport, context_base, num_channels, max_channels, sc->portcfg); config_egress_fifo_credits(sc->base, hwport, context_base, num_channels, max_channels, sc->portcfg); data = nlm_read_nae_reg(sc->base, NAE_DMA_TX_CREDIT_TH); data |= (1 << 25) | (1 << 24); nlm_write_nae_reg(sc->base, NAE_DMA_TX_CREDIT_TH, data); for (offset = 0; offset < num_channels; offset++) { nlm_write_nae_reg(sc->base, NAE_TX_SCHED_MAP_CMD1, NAE_DRR_QUANTA); data = (hwport << 15) | ((context_base + offset) << 5); if (sc->cmplx_type[nblock] == ILC) data |= (offset << 20); nlm_write_nae_reg(sc->base, NAE_TX_SCHED_MAP_CMD0, data | 1); nlm_write_nae_reg(sc->base, NAE_TX_SCHED_MAP_CMD0, data); } } static int xlpnae_get_maxchannels(struct nlm_xlpnae_softc *sc) { int maxchans = 0; int i; for (i = 0; i < sc->max_ports; i++) { if (sc->portcfg[i].type == UNKNOWN) continue; maxchans += sc->portcfg[i].num_channels; } return (maxchans); } static void nlm_setup_interface(struct nlm_xlpnae_softc *sc, int nblock, int port, uint32_t cur_flow_base, uint32_t flow_mask, int max_channels, int context) { uint64_t nae_base = sc->base; int mtu = 1536; /* XXXJC: don't hard code */ uint32_t ucore_mask; if (sc->cmplx_type[nblock] == XAUIC) nlm_config_xaui(nae_base, nblock, mtu, mtu, sc->portcfg[port].vlan_pri_en); nlm_config_freein_fifo_uniq_cfg(nae_base, port, sc->portcfg[port].free_desc_sizes); nlm_config_ucore_iface_mask_cfg(nae_base, port, sc->portcfg[port].ucore_mask); nlm_program_flow_cfg(nae_base, port, cur_flow_base, flow_mask); if (sc->cmplx_type[nblock] == SGMIIC) nlm_configure_sgmii_interface(nae_base, nblock, port, mtu, 0); nlm_config_egress(sc, nblock, context, port, max_channels); nlm_nae_init_netior(nae_base, sc->nblocks); nlm_nae_open_if(nae_base, nblock, sc->cmplx_type[nblock], port, sc->portcfg[port].free_desc_sizes); /* XXXJC: check mask calculation */ ucore_mask = (1 << sc->nucores) - 1; nlm_nae_init_ucore(nae_base, port, ucore_mask); } static void nlm_setup_interfaces(struct nlm_xlpnae_softc *sc) { uint64_t nae_base; uint32_t cur_slot, cur_slot_base; uint32_t cur_flow_base, port, flow_mask; int max_channels; int i, context; cur_slot = 0; cur_slot_base = 0; cur_flow_base = 0; nae_base = sc->base; flow_mask = nlm_get_flow_mask(sc->total_num_ports); /* calculate max_channels */ max_channels = xlpnae_get_maxchannels(sc); port = 0; context = 0; for (i = 0; i < sc->max_ports; i++) { if (sc->portcfg[i].type == UNKNOWN) continue; nlm_setup_interface(sc, sc->portcfg[i].block, i, cur_flow_base, flow_mask, max_channels, context); cur_flow_base += sc->per_port_num_flows; context += sc->portcfg[i].num_channels; } } static void nlm_xlpnae_init(int node, struct nlm_xlpnae_softc *sc) { uint64_t nae_base; uint32_t ucoremask = 0; uint32_t val; int i; nae_base = sc->base; nlm_nae_flush_free_fifo(nae_base, sc->nblocks); nlm_deflate_frin_fifo_carving(nae_base, sc->max_ports); nlm_reset_nae(node); for (i = 0; i < sc->nucores; i++) /* XXXJC: code repeated below */ ucoremask |= (0x1 << i); printf("Loading 0x%x ucores with microcode\n", ucoremask); nlm_ucore_load_all(nae_base, ucoremask, 1); val = nlm_set_device_frequency(node, DFS_DEVICE_NAE, sc->freq); printf("Setup NAE frequency to %dMHz\n", val); nlm_mdio_reset_all(nae_base); printf("Initialze SGMII PCS for blocks 0x%x\n", sc->sgmiimask); nlm_sgmii_pcs_init(nae_base, sc->sgmiimask); printf("Initialze XAUI PCS for blocks 0x%x\n", sc->xauimask); nlm_xaui_pcs_init(nae_base, sc->xauimask); /* clear NETIOR soft reset */ nlm_write_nae_reg(nae_base, NAE_LANE_CFG_SOFTRESET, 0x0); /* Disable RX enable bit in RX_CONFIG */ val = nlm_read_nae_reg(nae_base, NAE_RX_CONFIG); val &= 0xfffffffe; nlm_write_nae_reg(nae_base, NAE_RX_CONFIG, val); if (nlm_is_xlp8xx_ax() == 0) { val = nlm_read_nae_reg(nae_base, NAE_TX_CONFIG); val &= ~(1 << 3); nlm_write_nae_reg(nae_base, NAE_TX_CONFIG, val); } nlm_setup_poe_class_config(nae_base, MAX_POE_CLASSES, sc->ncontexts, poe_cl_tbl); nlm_setup_vfbid_mapping(nae_base); nlm_setup_flow_crc_poly(nae_base, sc->flow_crc_poly); nlm_setup_rx_cal_cfg(nae_base, sc->max_ports, sc->portcfg); /* note: xlp8xx Ax does not have Tx Calendering */ if (!nlm_is_xlp8xx_ax()) nlm_setup_tx_cal_cfg(nae_base, sc->max_ports, sc->portcfg); nlm_setup_interfaces(sc); nlm_config_poe(sc->poe_base, sc->poedv_base); if (sc->hw_parser_en) nlm_enable_hardware_parser(nae_base); if (sc->prepad_en) nlm_prepad_enable(nae_base, sc->prepad_size); if (sc->ieee_1588_en) nlm_setup_1588_timer(sc->base, sc->portcfg); } static void nlm_xlpnae_update_pde(void *dummy __unused) { struct nlm_xlpnae_softc *sc; uint32_t dv[NUM_WORDS_PER_DV]; device_t dev; int vec; dev = devclass_get_device(devclass_find("xlpnae"), 0); sc = device_get_softc(dev); nlm_write_poe_reg(sc->poe_base, POE_DISTR_EN, 0); for (vec = 0; vec < NUM_DIST_VEC; vec++) { if (nlm_get_poe_distvec(vec, dv) != 0) continue; nlm_write_poe_distvec(sc->poedv_base, vec, dv); } nlm_write_poe_reg(sc->poe_base, POE_DISTR_EN, 1); } SYSINIT(nlm_xlpnae_update_pde, SI_SUB_SMP, SI_ORDER_ANY, nlm_xlpnae_update_pde, NULL); /* configuration common for sgmii, xaui, ilaken goes here */ static void nlm_setup_portcfg(struct nlm_xlpnae_softc *sc, struct xlp_nae_ivars *naep, int block, int port) { int i; uint32_t ucore_mask = 0; struct xlp_block_ivars *bp; struct xlp_port_ivars *p; bp = &(naep->block_ivars[block]); p = &(bp->port_ivars[port & 0x3]); sc->portcfg[port].node = p->node; sc->portcfg[port].block = p->block; sc->portcfg[port].port = p->port; sc->portcfg[port].type = p->type; sc->portcfg[port].mdio_bus = p->mdio_bus; sc->portcfg[port].phy_addr = p->phy_addr; sc->portcfg[port].loopback_mode = p->loopback_mode; sc->portcfg[port].num_channels = p->num_channels; if (p->free_desc_sizes != MCLBYTES) { printf("[%d, %d] Error: free_desc_sizes %d != %d\n", block, port, p->free_desc_sizes, MCLBYTES); return; } sc->portcfg[port].free_desc_sizes = p->free_desc_sizes; for (i = 0; i < sc->nucores; i++) /* XXXJC: configure this */ ucore_mask |= (0x1 << i); sc->portcfg[port].ucore_mask = ucore_mask; sc->portcfg[port].vlan_pri_en = p->vlan_pri_en; sc->portcfg[port].num_free_descs = p->num_free_descs; sc->portcfg[port].iface_fifo_size = p->iface_fifo_size; sc->portcfg[port].rxbuf_size = p->rxbuf_size; sc->portcfg[port].rx_slots_reqd = p->rx_slots_reqd; sc->portcfg[port].tx_slots_reqd = p->tx_slots_reqd; sc->portcfg[port].pseq_fifo_size = p->pseq_fifo_size; sc->portcfg[port].stg2_fifo_size = p->stg2_fifo_size; sc->portcfg[port].eh_fifo_size = p->eh_fifo_size; sc->portcfg[port].frout_fifo_size = p->frout_fifo_size; sc->portcfg[port].ms_fifo_size = p->ms_fifo_size; sc->portcfg[port].pkt_fifo_size = p->pkt_fifo_size; sc->portcfg[port].pktlen_fifo_size = p->pktlen_fifo_size; sc->portcfg[port].max_stg2_offset = p->max_stg2_offset; sc->portcfg[port].max_eh_offset = p->max_eh_offset; sc->portcfg[port].max_frout_offset = p->max_frout_offset; sc->portcfg[port].max_ms_offset = p->max_ms_offset; sc->portcfg[port].max_pmem_offset = p->max_pmem_offset; sc->portcfg[port].stg1_2_credit = p->stg1_2_credit; sc->portcfg[port].stg2_eh_credit = p->stg2_eh_credit; sc->portcfg[port].stg2_frout_credit = p->stg2_frout_credit; sc->portcfg[port].stg2_ms_credit = p->stg2_ms_credit; sc->portcfg[port].ieee1588_inc_intg = p->ieee1588_inc_intg; sc->portcfg[port].ieee1588_inc_den = p->ieee1588_inc_den; sc->portcfg[port].ieee1588_inc_num = p->ieee1588_inc_num; sc->portcfg[port].ieee1588_userval = p->ieee1588_userval; sc->portcfg[port].ieee1588_ptpoff = p->ieee1588_ptpoff; sc->portcfg[port].ieee1588_tmr1 = p->ieee1588_tmr1; sc->portcfg[port].ieee1588_tmr2 = p->ieee1588_tmr2; sc->portcfg[port].ieee1588_tmr3 = p->ieee1588_tmr3; sc->total_free_desc += sc->portcfg[port].free_desc_sizes; sc->total_num_ports++; } -static int +static int nlm_xlpnae_attach(device_t dev) { struct xlp_nae_ivars *nae_ivars; struct nlm_xlpnae_softc *sc; device_t tmpd; uint32_t dv[NUM_WORDS_PER_DV]; int port, i, j, nchan, nblock, node, qstart, qnum; int offset, context, txq_base, rxvcbase; uint64_t poe_pcibase, nae_pcibase; node = pci_get_slot(dev) / 8; nae_ivars = &xlp_board_info.nodes[node].nae_ivars; sc = device_get_softc(dev); sc->xlpnae_dev = dev; sc->node = nae_ivars->node; sc->base = nlm_get_nae_regbase(sc->node); sc->poe_base = nlm_get_poe_regbase(sc->node); sc->poedv_base = nlm_get_poedv_regbase(sc->node); sc->portcfg = nae_port_config; sc->blockmask = nae_ivars->blockmask; sc->ilmask = nae_ivars->ilmask; sc->xauimask = nae_ivars->xauimask; sc->sgmiimask = nae_ivars->sgmiimask; sc->nblocks = nae_ivars->nblocks; sc->freq = nae_ivars->freq; - + /* flow table generation is done by CRC16 polynomial */ - sc->flow_crc_poly = nae_ivars->flow_crc_poly; + sc->flow_crc_poly = nae_ivars->flow_crc_poly; - sc->hw_parser_en = nae_ivars->hw_parser_en; - sc->prepad_en = nae_ivars->prepad_en; - sc->prepad_size = nae_ivars->prepad_size; - sc->ieee_1588_en = nae_ivars->ieee_1588_en; + sc->hw_parser_en = nae_ivars->hw_parser_en; + sc->prepad_en = nae_ivars->prepad_en; + sc->prepad_size = nae_ivars->prepad_size; + sc->ieee_1588_en = nae_ivars->ieee_1588_en; nae_pcibase = nlm_get_nae_pcibase(sc->node); sc->ncontexts = nlm_read_reg(nae_pcibase, XLP_PCI_DEVINFO_REG5); sc->nucores = nlm_num_uengines(nae_pcibase); for (nblock = 0; nblock < sc->nblocks; nblock++) { sc->cmplx_type[nblock] = nae_ivars->block_ivars[nblock].type; sc->portmask[nblock] = nae_ivars->block_ivars[nblock].portmask; } for (i = 0; i < sc->ncontexts; i++) cntx2port[i] = 18; /* 18 is an invalid port */ if (sc->nblocks == 5) sc->max_ports = 18; /* 8xx has a block 4 with 2 ports */ else sc->max_ports = sc->nblocks * PORTS_PER_CMPLX; for (i = 0; i < sc->max_ports; i++) sc->portcfg[i].type = UNKNOWN; /* Port Not Present */ /* * Now setup all internal fifo carvings based on * total number of ports in the system */ sc->total_free_desc = 0; sc->total_num_ports = 0; port = 0; context = 0; txq_base = nlm_qidstart(nae_pcibase); rxvcbase = txq_base + sc->ncontexts; for (i = 0; i < sc->nblocks; i++) { uint32_t portmask; if ((nae_ivars->blockmask & (1 << i)) == 0) { port += 4; continue; } portmask = nae_ivars->block_ivars[i].portmask; for (j = 0; j < PORTS_PER_CMPLX; j++, port++) { if ((portmask & (1 << j)) == 0) continue; nlm_setup_portcfg(sc, nae_ivars, i, port); nchan = sc->portcfg[port].num_channels; for (offset = 0; offset < nchan; offset++) cntx2port[context + offset] = port; sc->portcfg[port].txq = txq_base + context; sc->portcfg[port].rxfreeq = rxvcbase + port; context += nchan; } } poe_pcibase = nlm_get_poe_pcibase(sc->node); sc->per_port_num_flows = nlm_poe_max_flows(poe_pcibase) / sc->total_num_ports; /* zone for P2P descriptors */ nl_tx_desc_zone = uma_zcreate("NL Tx Desc", sizeof(struct xlpge_tx_desc), NULL, NULL, NULL, NULL, NAE_CACHELINE_SIZE, 0); /* NAE FMN messages have CMS src station id's in the * range of qstart to qnum. */ qstart = nlm_qidstart(nae_pcibase); qnum = nlm_qnum(nae_pcibase); if (register_msgring_handler(qstart, qstart + qnum - 1, nlm_xlpge_msgring_handler, sc)) { panic("Couldn't register NAE msgring handler\n"); } /* POE FMN messages have CMS src station id's in the * range of qstart to qnum. */ qstart = nlm_qidstart(poe_pcibase); qnum = nlm_qnum(poe_pcibase); if (register_msgring_handler(qstart, qstart + qnum - 1, nlm_xlpge_msgring_handler, sc)) { panic("Couldn't register POE msgring handler\n"); } nlm_xlpnae_init(node, sc); for (i = 0; i < sc->max_ports; i++) { char desc[32]; int block, port; if (sc->portcfg[i].type == UNKNOWN) continue; block = sc->portcfg[i].block; port = sc->portcfg[i].port; tmpd = device_add_child(dev, "xlpge", i); device_set_ivars(tmpd, &(nae_ivars->block_ivars[block].port_ivars[port])); sprintf(desc, "XLP NAE Port %d,%d", block, port); device_set_desc_copy(tmpd, desc); } nlm_setup_iface_fifo_cfg(sc->base, sc->max_ports, sc->portcfg); nlm_setup_rx_base_config(sc->base, sc->max_ports, sc->portcfg); nlm_setup_rx_buf_config(sc->base, sc->max_ports, sc->portcfg); nlm_setup_freein_fifo_cfg(sc->base, sc->portcfg); nlm_program_nae_parser_seq_fifo(sc->base, sc->max_ports, sc->portcfg); nlm_xlpnae_print_frin_desc_carving(sc); bus_generic_probe(dev); bus_generic_attach(dev); /* * Enable only boot cpu at this point, full distribution comes * only after SMP is started */ nlm_write_poe_reg(sc->poe_base, POE_DISTR_EN, 0); nlm_calc_poe_distvec(0x1, 0, 0, 0, 0x1 << XLPGE_RX_VC, dv); nlm_write_poe_distvec(sc->poedv_base, 0, dv); nlm_write_poe_reg(sc->poe_base, POE_DISTR_EN, 1); return (0); } -static int +static int nlm_xlpnae_detach(device_t dev) { /* TODO - free zone here */ return (0); } -static int +static int nlm_xlpnae_suspend(device_t dev) { return (0); } -static int +static int nlm_xlpnae_resume(device_t dev) { return (0); } -static int +static int nlm_xlpnae_shutdown(device_t dev) { return (0); } /* * xlpge driver implementation */ static void nlm_xlpge_mac_set_rx_mode(struct nlm_xlpge_softc *sc) { if (sc->if_flags & IFF_PROMISC) { if (sc->type == SGMIIC) nlm_nae_setup_rx_mode_sgmii(sc->base_addr, sc->block, sc->port, sc->type, 1 /* broadcast */, 1/* multicast */, 0 /* pause */, 1 /* promisc */); else nlm_nae_setup_rx_mode_xaui(sc->base_addr, sc->block, sc->port, sc->type, 1 /* broadcast */, 1/* multicast */, 0 /* pause */, 1 /* promisc */); } else { if (sc->type == SGMIIC) nlm_nae_setup_rx_mode_sgmii(sc->base_addr, sc->block, sc->port, sc->type, 1 /* broadcast */, 1/* multicast */, 0 /* pause */, 0 /* promisc */); else nlm_nae_setup_rx_mode_xaui(sc->base_addr, sc->block, sc->port, sc->type, 1 /* broadcast */, 1/* multicast */, 0 /* pause */, 0 /* promisc */); } } -static int +static int nlm_xlpge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) { struct mii_data *mii; struct nlm_xlpge_softc *sc; struct ifreq *ifr; - int error; + int error; sc = ifp->if_softc; error = 0; ifr = (struct ifreq *)data; switch (command) { case SIOCSIFFLAGS: XLPGE_LOCK(sc); sc->if_flags = ifp->if_flags; if (ifp->if_flags & IFF_UP) { if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) nlm_xlpge_init(sc); else nlm_xlpge_port_enable(sc); nlm_xlpge_mac_set_rx_mode(sc); sc->link = NLM_LINK_UP; } else { if (ifp->if_drv_flags & IFF_DRV_RUNNING) nlm_xlpge_port_disable(sc); sc->link = NLM_LINK_DOWN; } XLPGE_UNLOCK(sc); error = 0; break; case SIOCGIFMEDIA: case SIOCSIFMEDIA: if (sc->mii_bus != NULL) { mii = device_get_softc(sc->mii_bus); error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); } break; default: error = ether_ioctl(ifp, command, data); break; } return (error); } static int xlpge_tx(struct ifnet *ifp, struct mbuf *mbuf_chain) { struct nlm_fmn_msg msg; struct xlpge_tx_desc *p2p; struct nlm_xlpge_softc *sc; struct mbuf *m; vm_paddr_t paddr; int fbid, dst, pos, err; int ret = 0, tx_msgstatus, retries; err = 0; if (mbuf_chain == NULL) return (0); sc = ifp->if_softc; p2p = NULL; if (!(ifp->if_drv_flags & IFF_DRV_RUNNING) || ifp->if_drv_flags & IFF_DRV_OACTIVE) { err = ENXIO; goto fail; } /* free a few in coming messages on the fb vc */ xlp_handle_msg_vc(1 << XLPGE_FB_VC, 2); /* vfb id table is setup to map cpu to vc 3 of the cpu */ - fbid = nlm_cpuid(); + fbid = nlm_cpuid(); dst = sc->txq; pos = 0; p2p = uma_zalloc(nl_tx_desc_zone, M_NOWAIT); if (p2p == NULL) { printf("alloc fail\n"); err = ENOBUFS; goto fail; } for (m = mbuf_chain; m != NULL; m = m->m_next) { vm_offset_t buf = (vm_offset_t) m->m_data; int len = m->m_len; int frag_sz; uint64_t desc; /*printf("m_data = %p len %d\n", m->m_data, len); */ while (len) { if (pos == XLP_NTXFRAGS - 3) { device_printf(sc->xlpge_dev, "packet defrag %d\n", m_length(mbuf_chain, NULL)); err = ENOBUFS; /* TODO fix error */ goto fail; } paddr = vtophys(buf); frag_sz = PAGE_SIZE - (buf & PAGE_MASK); if (len < frag_sz) frag_sz = len; desc = nae_tx_desc(P2D_NEOP, 0, 127, frag_sz, paddr); p2p->frag[pos] = htobe64(desc); pos++; len -= frag_sz; buf += frag_sz; } } KASSERT(pos != 0, ("Zero-length mbuf chain?\n")); /* Make the last one P2D EOP */ p2p->frag[pos-1] |= htobe64((uint64_t)P2D_EOP << 62); /* stash useful pointers in the desc */ p2p->frag[XLP_NTXFRAGS-3] = 0xf00bad; p2p->frag[XLP_NTXFRAGS-2] = (uintptr_t)p2p; p2p->frag[XLP_NTXFRAGS-1] = (uintptr_t)mbuf_chain; paddr = vtophys(p2p); msg.msg[0] = nae_tx_desc(P2P, 0, fbid, pos, paddr); for (retries = 16; retries > 0; retries--) { ret = nlm_fmn_msgsend(dst, 1, FMN_SWCODE_NAE, &msg); if (ret == 0) return (0); } fail: if (ret != 0) { tx_msgstatus = nlm_read_c2_txmsgstatus(); if ((tx_msgstatus >> 24) & 0x1) device_printf(sc->xlpge_dev, "Transmit queue full - "); if ((tx_msgstatus >> 3) & 0x1) device_printf(sc->xlpge_dev, "ECC error - "); if ((tx_msgstatus >> 2) & 0x1) device_printf(sc->xlpge_dev, "Pending Sync - "); if ((tx_msgstatus >> 1) & 0x1) device_printf(sc->xlpge_dev, "Insufficient input queue credits - "); if (tx_msgstatus & 0x1) device_printf(sc->xlpge_dev, "Insufficient output queue credits - "); } device_printf(sc->xlpge_dev, "Send failed! err = %d\n", err); if (p2p) uma_zfree(nl_tx_desc_zone, p2p); m_freem(mbuf_chain); if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); return (err); } static int nlm_xlpge_gmac_config_speed(struct nlm_xlpge_softc *sc) { struct mii_data *mii; if (sc->type == XAUIC || sc->type == ILC) return (0); if (sc->mii_bus) { mii = device_get_softc(sc->mii_bus); mii_pollstat(mii); } return (0); } static void nlm_xlpge_port_disable(struct nlm_xlpge_softc *sc) { struct ifnet *ifp; ifp = sc->xlpge_if; ifp->if_drv_flags &= ~IFF_DRV_RUNNING; callout_stop(&sc->xlpge_callout); nlm_mac_disable(sc->base_addr, sc->block, sc->type, sc->port); } static void nlm_mii_pollstat(void *arg) { struct nlm_xlpge_softc *sc = (struct nlm_xlpge_softc *)arg; struct mii_data *mii = NULL; if (sc->mii_bus) { mii = device_get_softc(sc->mii_bus); KASSERT(mii != NULL, ("mii ptr is NULL")); mii_pollstat(mii); - callout_reset(&sc->xlpge_callout, hz, + callout_reset(&sc->xlpge_callout, hz, nlm_mii_pollstat, sc); } } static void nlm_xlpge_port_enable(struct nlm_xlpge_softc *sc) { if ((sc->type != SGMIIC) && (sc->type != XAUIC)) return; nlm_mac_enable(sc->base_addr, sc->block, sc->type, sc->port); nlm_mii_pollstat((void *)sc); } static void nlm_xlpge_init(void *addr) { struct nlm_xlpge_softc *sc; struct ifnet *ifp; struct mii_data *mii = NULL; sc = (struct nlm_xlpge_softc *)addr; ifp = sc->xlpge_if; if (ifp->if_drv_flags & IFF_DRV_RUNNING) return; if (sc->mii_bus) { mii = device_get_softc(sc->mii_bus); mii_mediachg(mii); } nlm_xlpge_gmac_config_speed(sc); ifp->if_drv_flags |= IFF_DRV_RUNNING; ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; nlm_xlpge_port_enable(sc); /* start the callout */ callout_reset(&sc->xlpge_callout, hz, nlm_mii_pollstat, sc); } /* * Read the MAC address from FDT or board eeprom. */ static void xlpge_read_mac_addr(struct nlm_xlpge_softc *sc) { xlpge_get_macaddr(sc->dev_addr); /* last octet is port specific */ sc->dev_addr[5] += (sc->block * 4) + sc->port; if (sc->type == SGMIIC) nlm_nae_setup_mac_addr_sgmii(sc->base_addr, sc->block, sc->port, sc->type, sc->dev_addr); else if (sc->type == XAUIC) nlm_nae_setup_mac_addr_xaui(sc->base_addr, sc->block, sc->port, sc->type, sc->dev_addr); } static int xlpge_mediachange(struct ifnet *ifp) { return (0); } static void xlpge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) { struct nlm_xlpge_softc *sc; struct mii_data *md; md = NULL; sc = ifp->if_softc; if (sc->mii_bus) md = device_get_softc(sc->mii_bus); ifmr->ifm_status = IFM_AVALID; ifmr->ifm_active = IFM_ETHER; if (sc->link == NLM_LINK_DOWN) return; if (md != NULL) ifmr->ifm_active = md->mii_media.ifm_cur->ifm_media; ifmr->ifm_status |= IFM_ACTIVE; } -static int +static int nlm_xlpge_ifinit(struct nlm_xlpge_softc *sc) { struct ifnet *ifp; device_t dev; int port = sc->block * 4 + sc->port; dev = sc->xlpge_dev; ifp = sc->xlpge_if = if_alloc(IFT_ETHER); /*(sc->network_sc)->ifp_ports[port].xlpge_if = ifp;*/ ifp_ports[port].xlpge_if = ifp; if (ifp == NULL) { device_printf(dev, "cannot if_alloc()\n"); return (ENOSPC); } ifp->if_softc = sc; if_initname(ifp, device_get_name(dev), device_get_unit(dev)); ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; sc->if_flags = ifp->if_flags; /*ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_VLAN_HWTAGGING;*/ ifp->if_capabilities = 0; ifp->if_capenable = ifp->if_capabilities; ifp->if_ioctl = nlm_xlpge_ioctl; ifp->if_init = nlm_xlpge_init ; ifp->if_hwassist = 0; ifp->if_snd.ifq_drv_maxlen = NLM_XLPGE_TXQ_SIZE; /* TODO: make this a sysint */ IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); IFQ_SET_READY(&ifp->if_snd); ifmedia_init(&sc->xlpge_mii.mii_media, 0, xlpge_mediachange, xlpge_mediastatus); ifmedia_add(&sc->xlpge_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, NULL); ifmedia_set(&sc->xlpge_mii.mii_media, IFM_ETHER | IFM_AUTO); sc->xlpge_mii.mii_media.ifm_media = sc->xlpge_mii.mii_media.ifm_cur->ifm_media; xlpge_read_mac_addr(sc); ether_ifattach(ifp, sc->dev_addr); /* override if_transmit : per ifnet(9), do it after if_attach */ ifp->if_transmit = xlpge_tx; return (0); } -static int +static int nlm_xlpge_probe(device_t dev) { return (BUS_PROBE_DEFAULT); } static void * get_buf(void) { struct mbuf *m_new; uint64_t *md; #ifdef INVARIANTS vm_paddr_t temp1, temp2; #endif if ((m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR)) == NULL) return (NULL); m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; KASSERT(((uintptr_t)m_new->m_data & (NAE_CACHELINE_SIZE - 1)) == 0, ("m_new->m_data is not cacheline aligned")); md = (uint64_t *)m_new->m_data; md[0] = (intptr_t)m_new; /* Back Ptr */ md[1] = 0xf00bad; m_adj(m_new, NAE_CACHELINE_SIZE); #ifdef INVARIANTS temp1 = vtophys((vm_offset_t) m_new->m_data); temp2 = vtophys((vm_offset_t) m_new->m_data + 1536); KASSERT((temp1 + 1536) == temp2, ("Alloced buffer is not contiguous")); #endif return ((void *)m_new->m_data); } static void nlm_xlpge_mii_init(device_t dev, struct nlm_xlpge_softc *sc) { int error; error = mii_attach(dev, &sc->mii_bus, sc->xlpge_if, xlpge_mediachange, xlpge_mediastatus, BMSR_DEFCAPMASK, sc->phy_addr, MII_OFFSET_ANY, 0); if (error) { device_printf(dev, "attaching PHYs failed\n"); sc->mii_bus = NULL; } if (sc->mii_bus != NULL) { /* enable MDIO interrupts in the PHY */ /* XXXJC: TODO */ } } static int xlpge_stats_sysctl(SYSCTL_HANDLER_ARGS) { struct nlm_xlpge_softc *sc; uint32_t val; int reg, field; sc = arg1; field = arg2; reg = SGMII_STATS_MLR(sc->block, sc->port) + field; val = nlm_read_nae_reg(sc->base_addr, reg); return (sysctl_handle_int(oidp, &val, 0, req)); } static void nlm_xlpge_setup_stats_sysctl(device_t dev, struct nlm_xlpge_softc *sc) { struct sysctl_ctx_list *ctx; struct sysctl_oid_list *child; struct sysctl_oid *tree; ctx = device_get_sysctl_ctx(dev); tree = device_get_sysctl_tree(dev); child = SYSCTL_CHILDREN(tree); #define XLPGE_STAT(name, offset, desc) \ - SYSCTL_ADD_PROC(ctx, child, OID_AUTO, name, \ + SYSCTL_ADD_PROC(ctx, child, OID_AUTO, name, \ CTLTYPE_UINT | CTLFLAG_RD, sc, offset, \ xlpge_stats_sysctl, "IU", desc) XLPGE_STAT("tr127", nlm_sgmii_stats_tr127, "TxRx 64 - 127 Bytes"); XLPGE_STAT("tr255", nlm_sgmii_stats_tr255, "TxRx 128 - 255 Bytes"); XLPGE_STAT("tr511", nlm_sgmii_stats_tr511, "TxRx 256 - 511 Bytes"); XLPGE_STAT("tr1k", nlm_sgmii_stats_tr1k, "TxRx 512 - 1023 Bytes"); XLPGE_STAT("trmax", nlm_sgmii_stats_trmax, "TxRx 1024 - 1518 Bytes"); XLPGE_STAT("trmgv", nlm_sgmii_stats_trmgv, "TxRx 1519 - 1522 Bytes"); XLPGE_STAT("rbyt", nlm_sgmii_stats_rbyt, "Rx Bytes"); XLPGE_STAT("rpkt", nlm_sgmii_stats_rpkt, "Rx Packets"); XLPGE_STAT("rfcs", nlm_sgmii_stats_rfcs, "Rx FCS Error"); XLPGE_STAT("rmca", nlm_sgmii_stats_rmca, "Rx Multicast Packets"); XLPGE_STAT("rbca", nlm_sgmii_stats_rbca, "Rx Broadcast Packets"); XLPGE_STAT("rxcf", nlm_sgmii_stats_rxcf, "Rx Control Frames"); XLPGE_STAT("rxpf", nlm_sgmii_stats_rxpf, "Rx Pause Frames"); XLPGE_STAT("rxuo", nlm_sgmii_stats_rxuo, "Rx Unknown Opcode"); XLPGE_STAT("raln", nlm_sgmii_stats_raln, "Rx Alignment Errors"); XLPGE_STAT("rflr", nlm_sgmii_stats_rflr, "Rx Framelength Errors"); XLPGE_STAT("rcde", nlm_sgmii_stats_rcde, "Rx Code Errors"); XLPGE_STAT("rcse", nlm_sgmii_stats_rcse, "Rx Carrier Sense Errors"); XLPGE_STAT("rund", nlm_sgmii_stats_rund, "Rx Undersize Packet Errors"); XLPGE_STAT("rovr", nlm_sgmii_stats_rovr, "Rx Oversize Packet Errors"); XLPGE_STAT("rfrg", nlm_sgmii_stats_rfrg, "Rx Fragments"); XLPGE_STAT("rjbr", nlm_sgmii_stats_rjbr, "Rx Jabber"); XLPGE_STAT("tbyt", nlm_sgmii_stats_tbyt, "Tx Bytes"); XLPGE_STAT("tpkt", nlm_sgmii_stats_tpkt, "Tx Packets"); XLPGE_STAT("tmca", nlm_sgmii_stats_tmca, "Tx Multicast Packets"); XLPGE_STAT("tbca", nlm_sgmii_stats_tbca, "Tx Broadcast Packets"); XLPGE_STAT("txpf", nlm_sgmii_stats_txpf, "Tx Pause Frame"); XLPGE_STAT("tdfr", nlm_sgmii_stats_tdfr, "Tx Deferral Packets"); XLPGE_STAT("tedf", nlm_sgmii_stats_tedf, "Tx Excessive Deferral Pkts"); XLPGE_STAT("tscl", nlm_sgmii_stats_tscl, "Tx Single Collisions"); XLPGE_STAT("tmcl", nlm_sgmii_stats_tmcl, "Tx Multiple Collisions"); XLPGE_STAT("tlcl", nlm_sgmii_stats_tlcl, "Tx Late Collision Pkts"); XLPGE_STAT("txcl", nlm_sgmii_stats_txcl, "Tx Excessive Collisions"); XLPGE_STAT("tncl", nlm_sgmii_stats_tncl, "Tx Total Collisions"); XLPGE_STAT("tjbr", nlm_sgmii_stats_tjbr, "Tx Jabber Frames"); XLPGE_STAT("tfcs", nlm_sgmii_stats_tfcs, "Tx FCS Errors"); XLPGE_STAT("txcf", nlm_sgmii_stats_txcf, "Tx Control Frames"); XLPGE_STAT("tovr", nlm_sgmii_stats_tovr, "Tx Oversize Frames"); XLPGE_STAT("tund", nlm_sgmii_stats_tund, "Tx Undersize Frames"); XLPGE_STAT("tfrg", nlm_sgmii_stats_tfrg, "Tx Fragments"); #undef XLPGE_STAT } -static int +static int nlm_xlpge_attach(device_t dev) { struct xlp_port_ivars *pv; struct nlm_xlpge_softc *sc; int port; pv = device_get_ivars(dev); sc = device_get_softc(dev); sc->xlpge_dev = dev; sc->mii_bus = NULL; sc->block = pv->block; sc->node = pv->node; sc->port = pv->port; sc->type = pv->type; sc->xlpge_if = NULL; sc->phy_addr = pv->phy_addr; sc->mdio_bus = pv->mdio_bus; sc->portcfg = nae_port_config; sc->hw_parser_en = pv->hw_parser_en; /* default settings */ sc->speed = NLM_SGMII_SPEED_10; sc->duplexity = NLM_SGMII_DUPLEX_FULL; sc->link = NLM_LINK_DOWN; sc->flowctrl = NLM_FLOWCTRL_DISABLED; sc->network_sc = device_get_softc(device_get_parent(dev)); sc->base_addr = sc->network_sc->base; sc->prepad_en = sc->network_sc->prepad_en; sc->prepad_size = sc->network_sc->prepad_size; callout_init(&sc->xlpge_callout, CALLOUT_MPSAFE); XLPGE_LOCK_INIT(sc, device_get_nameunit(dev)); port = (sc->block*4)+sc->port; sc->nfree_desc = nae_port_config[port].num_free_descs; sc->txq = nae_port_config[port].txq; sc->rxfreeq = nae_port_config[port].rxfreeq; nlm_xlpge_submit_rx_free_desc(sc, sc->nfree_desc); if (sc->hw_parser_en) nlm_enable_hardware_parser_per_port(sc->base_addr, sc->block, sc->port); nlm_xlpge_ifinit(sc); ifp_ports[port].xlpge_sc = sc; nlm_xlpge_mii_init(dev, sc); nlm_xlpge_setup_stats_sysctl(dev, sc); return (0); } -static int +static int nlm_xlpge_detach(device_t dev) { return (0); } -static int +static int nlm_xlpge_suspend(device_t dev) { return (0); } -static int +static int nlm_xlpge_resume(device_t dev) { return (0); } -static int +static int nlm_xlpge_shutdown(device_t dev) { return (0); } /* * miibus function with custom implementation */ -static int +static int nlm_xlpge_mii_read(struct device *dev, int phyaddr, int regidx) { struct nlm_xlpge_softc *sc; int val; sc = device_get_softc(dev); - if (sc->type == SGMIIC) + if (sc->type == SGMIIC) val = nlm_gmac_mdio_read(sc->base_addr, sc->mdio_bus, BLOCK_7, LANE_CFG, phyaddr, regidx); else val = 0xffff; return (val); } -static int +static int nlm_xlpge_mii_write(struct device *dev, int phyaddr, int regidx, int val) { struct nlm_xlpge_softc *sc; sc = device_get_softc(dev); if (sc->type == SGMIIC) nlm_gmac_mdio_write(sc->base_addr, sc->mdio_bus, BLOCK_7, LANE_CFG, phyaddr, regidx, val); return (0); } -static void +static void nlm_xlpge_mii_statchg(device_t dev) { struct nlm_xlpge_softc *sc; struct mii_data *mii; char *speed, *duplexity; sc = device_get_softc(dev); if (sc->mii_bus == NULL) return; mii = device_get_softc(sc->mii_bus); if (mii->mii_media_status & IFM_ACTIVE) { if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { sc->speed = NLM_SGMII_SPEED_10; speed = "10Mbps"; } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { sc->speed = NLM_SGMII_SPEED_100; speed = "100Mbps"; } else { /* default to 1G */ sc->speed = NLM_SGMII_SPEED_1000; speed = "1Gbps"; } if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { sc->duplexity = NLM_SGMII_DUPLEX_FULL; duplexity = "full"; } else { sc->duplexity = NLM_SGMII_DUPLEX_HALF; duplexity = "half"; } printf("Port [%d, %d] setup with speed=%s duplex=%s\n", sc->block, sc->port, speed, duplexity); nlm_nae_setup_mac(sc->base_addr, sc->block, sc->port, 0, 1, 1, sc->speed, sc->duplexity); } } /* * xlpge support function implementations */ static void nlm_xlpge_release_mbuf(uint64_t paddr) { uint64_t mag, desc, mbuf; paddr += (XLP_NTXFRAGS - 3) * sizeof(uint64_t); mag = nlm_paddr_ld(paddr); desc = nlm_paddr_ld(paddr + sizeof(uint64_t)); mbuf = nlm_paddr_ld(paddr + 2 * sizeof(uint64_t)); if (mag != 0xf00bad) { /* somebody else packet Error - FIXME in intialization */ printf("cpu %d: ERR Tx packet paddr %jx, mag %jx, desc %jx mbuf %jx\n", nlm_cpuid(), (uintmax_t)paddr, (uintmax_t)mag, (intmax_t)desc, (uintmax_t)mbuf); return; } m_freem((struct mbuf *)(uintptr_t)mbuf); uma_zfree(nl_tx_desc_zone, (void *)(uintptr_t)desc); } static void nlm_xlpge_rx(struct nlm_xlpge_softc *sc, int port, vm_paddr_t paddr, int len) { struct ifnet *ifp; struct mbuf *m; vm_offset_t temp; unsigned long mag; int prepad_size; ifp = sc->xlpge_if; temp = nlm_paddr_ld(paddr - NAE_CACHELINE_SIZE); mag = nlm_paddr_ld(paddr - NAE_CACHELINE_SIZE + sizeof(uint64_t)); m = (struct mbuf *)(intptr_t)temp; if (mag != 0xf00bad) { /* somebody else packet Error - FIXME in intialization */ printf("cpu %d: ERR Rx packet paddr %jx, temp %p, mag %lx\n", nlm_cpuid(), (uintmax_t)paddr, (void *)temp, mag); return; } m->m_pkthdr.rcvif = ifp; #ifdef DUMP_PACKET { int i = 0, j = 64; unsigned char *buf = (char *)m->m_data; printf("(cpu_%d: nlge_rx, !RX_COPY) Rx Packet: length=%d\n", nlm_cpuid(), len); if (len < j) j = len; if (sc->prepad_en) j += ((sc->prepad_size + 1) * 16); for (i = 0; i < j; i++) { if (i && (i % 16) == 0) printf("\n"); printf("%02x ", buf[i]); } printf("\n"); } #endif if (sc->prepad_en) { prepad_size = ((sc->prepad_size + 1) * 16); m->m_data += prepad_size; m->m_pkthdr.len = m->m_len = (len - prepad_size); } else m->m_pkthdr.len = m->m_len = len; if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); #ifdef XLP_DRIVER_LOOPBACK if (port == 16 || port == 17) (*ifp->if_input)(ifp, m); else xlpge_tx(ifp, m); #else (*ifp->if_input)(ifp, m); #endif } void nlm_xlpge_submit_rx_free_desc(struct nlm_xlpge_softc *sc, int num) { int i, size, ret, n; struct nlm_fmn_msg msg; void *ptr; for(i = 0; i < num; i++) { memset(&msg, 0, sizeof(msg)); ptr = get_buf(); if (!ptr) { device_printf(sc->xlpge_dev, "Cannot allocate mbuf\n"); break; } msg.msg[0] = vtophys(ptr); if (msg.msg[0] == 0) { printf("Bad ptr for %p\n", ptr); break; } size = 1; n = 0; while (1) { /* on success returns 1, else 0 */ ret = nlm_fmn_msgsend(sc->rxfreeq, size, 0, &msg); if (ret == 0) break; if (n++ > 10000) { printf("Too many credit fails for send free desc\n"); break; } } } } void nlm_xlpge_msgring_handler(int vc, int size, int code, int src_id, struct nlm_fmn_msg *msg, void *data) { uint64_t phys_addr; struct nlm_xlpnae_softc *sc; struct nlm_xlpge_softc *xlpge_sc; struct ifnet *ifp; uint32_t context; uint32_t port = 0; uint32_t length; sc = (struct nlm_xlpnae_softc *)data; KASSERT(sc != NULL, ("Null sc in msgring handler")); if (size == 1) { /* process transmit complete */ phys_addr = msg->msg[0] & 0xffffffffffULL; /* context is SGMII_RCV_CONTEXT_NUM + three bit vlan type * or vlan priority */ context = (msg->msg[0] >> 40) & 0x3fff; port = cntx2port[context]; if (port >= XLP_MAX_PORTS) { printf("%s:%d Bad port %d (context=%d)\n", __func__, __LINE__, port, context); return; } ifp = ifp_ports[port].xlpge_if; xlpge_sc = ifp_ports[port].xlpge_sc; nlm_xlpge_release_mbuf(phys_addr); if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); } else if (size > 1) { /* Recieve packet */ phys_addr = msg->msg[1] & 0xffffffffc0ULL; length = (msg->msg[1] >> 40) & 0x3fff; length -= MAC_CRC_LEN; /* context is SGMII_RCV_CONTEXT_NUM + three bit vlan type * or vlan priority */ context = (msg->msg[1] >> 54) & 0x3ff; port = cntx2port[context]; if (port >= XLP_MAX_PORTS) { printf("%s:%d Bad port %d (context=%d)\n", __func__, __LINE__, port, context); return; } ifp = ifp_ports[port].xlpge_if; xlpge_sc = ifp_ports[port].xlpge_sc; nlm_xlpge_rx(xlpge_sc, port, phys_addr, length); /* return back a free descriptor to NA */ nlm_xlpge_submit_rx_free_desc(xlpge_sc, 1); } } Index: head/sys/mips/nlm/dev/net/xlpge.h =================================================================== --- head/sys/mips/nlm/dev/net/xlpge.h (revision 279387) +++ head/sys/mips/nlm/dev/net/xlpge.h (revision 279388) @@ -1,138 +1,138 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef __XLPGE_H__ #define __XLPGE_H__ #define NLM_XLPGE_TXQ_SIZE 1024 #define MAC_CRC_LEN 4 enum xlpge_link_state { NLM_LINK_DOWN, NLM_LINK_UP }; enum xlpge_floctrl_status { NLM_FLOWCTRL_DISABLED, NLM_FLOWCTRL_ENABLED }; struct nlm_xlp_portdata { struct ifnet *xlpge_if; struct nlm_xlpge_softc *xlpge_sc; }; struct nlm_xlpnae_softc { device_t xlpnae_dev; int node; /* XLP Node id */ uint64_t base; /* NAE IO base */ uint64_t poe_base; /* POE IO base */ uint64_t poedv_base; /* POE distribution vec IO base */ int freq; /* frequency of nae block */ int flow_crc_poly; /* Flow CRC16 polynomial */ int total_free_desc; /* total for node */ int max_ports; int total_num_ports; int per_port_num_flows; u_int nucores; u_int nblocks; u_int num_complex; u_int ncontexts; /* Ingress side parameters */ u_int num_desc; /* no of descriptors in each packet */ u_int parser_threshold;/* threshold of entries above which */ /* the parser sequencer is scheduled */ /* NetIOR configs */ u_int cmplx_type[8]; /* XXXJC: redundant? */ struct nae_port_config *portcfg; u_int blockmask; u_int portmask[XLP_NAE_NBLOCKS]; u_int ilmask; u_int xauimask; u_int sgmiimask; u_int hw_parser_en; u_int prepad_en; u_int prepad_size; u_int driver_mode; u_int ieee_1588_en; }; struct nlm_xlpge_softc { struct ifnet *xlpge_if; /* should be first member */ /* see - mii.c:miibus_attach() */ device_t xlpge_dev; device_t mii_bus; struct nlm_xlpnae_softc *network_sc; uint64_t base_addr; /* NAE IO base */ int node; /* node id (quickread) */ int block; /* network block id (quickread) */ int port; /* port id - among the 18 in XLP */ int type; /* port type - see xlp_gmac_port_types */ int valid; /* boolean: valid port or not */ struct mii_data xlpge_mii; int nfree_desc; /* No of free descriptors sent to port */ int phy_addr; /* PHY id for the interface */ int speed; /* Port speed */ int duplexity; /* Port duplexity */ int link; /* Port link status */ int flowctrl; /* Port flow control setting */ - unsigned char dev_addr[ETHER_ADDR_LEN]; + unsigned char dev_addr[ETHER_ADDR_LEN]; struct mtx sc_lock; int if_flags; struct nae_port_config *portcfg; struct callout xlpge_callout; int mdio_bus; int txq; int rxfreeq; int hw_parser_en; int prepad_en; int prepad_size; }; #define XLP_NTXFRAGS 16 #define NULL_VFBID 127 struct xlpge_tx_desc { uint64_t frag[XLP_NTXFRAGS]; }; #define XLPGE_LOCK_INIT(_sc, _name) \ mtx_init(&(_sc)->sc_lock, _name, MTX_NETWORK_LOCK, MTX_DEF) #define XLPGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_lock) #define XLPGE_LOCK(_sc) mtx_lock(&(_sc)->sc_lock) #define XLPGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_lock) #define XLPGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_lock, MA_OWNED) #endif Index: head/sys/mips/nlm/dev/sec/nlmrsa.c =================================================================== --- head/sys/mips/nlm/dev/sec/nlmrsa.c (revision 279387) +++ head/sys/mips/nlm/dev/sec/nlmrsa.c (revision 279388) @@ -1,555 +1,555 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "cryptodev_if.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef NLM_RSA_DEBUG static void print_krp_params(struct cryptkop *krp); #endif static int xlp_rsa_init(struct xlp_rsa_softc *sc, int node); static int xlp_rsa_newsession(device_t , uint32_t *, struct cryptoini *); static int xlp_rsa_freesession(device_t , uint64_t); static int xlp_rsa_kprocess(device_t , struct cryptkop *, int); static int xlp_get_rsa_opsize(struct xlp_rsa_command *cmd, unsigned int bits); static void xlp_free_cmd_params(struct xlp_rsa_command *cmd); static int xlp_rsa_inp2hwformat(uint8_t *src, uint8_t *dst, uint32_t paramsize, uint8_t result); static int xlp_rsa_probe(device_t); static int xlp_rsa_attach(device_t); static int xlp_rsa_detach(device_t); static device_method_t xlp_rsa_methods[] = { /* device interface */ DEVMETHOD(device_probe, xlp_rsa_probe), DEVMETHOD(device_attach, xlp_rsa_attach), DEVMETHOD(device_detach, xlp_rsa_detach), /* bus interface */ DEVMETHOD(bus_print_child, bus_generic_print_child), DEVMETHOD(bus_driver_added, bus_generic_driver_added), /* crypto device methods */ DEVMETHOD(cryptodev_newsession, xlp_rsa_newsession), DEVMETHOD(cryptodev_freesession, xlp_rsa_freesession), DEVMETHOD(cryptodev_kprocess, xlp_rsa_kprocess), DEVMETHOD_END }; static driver_t xlp_rsa_driver = { "nlmrsa", xlp_rsa_methods, sizeof(struct xlp_rsa_softc) }; static devclass_t xlp_rsa_devclass; DRIVER_MODULE(nlmrsa, pci, xlp_rsa_driver, xlp_rsa_devclass, 0, 0); MODULE_DEPEND(nlmrsa, crypto, 1, 1, 1); #ifdef NLM_RSA_DEBUG static void print_krp_params(struct cryptkop *krp) { int i; printf("krp->krp_op :%d\n", krp->krp_op); printf("krp->krp_status :%d\n", krp->krp_status); printf("krp->krp_iparams:%d\n", krp->krp_iparams); printf("krp->krp_oparams:%d\n", krp->krp_oparams); for (i = 0; i < krp->krp_iparams + krp->krp_oparams; i++) { printf("krp->krp_param[%d].crp_p :0x%llx\n", i, (unsigned long long)krp->krp_param[i].crp_p); printf("krp->krp_param[%d].crp_nbits :%d\n", i, krp->krp_param[i].crp_nbits); printf("krp->krp_param[%d].crp_nbytes :%d\n", i, howmany(krp->krp_param[i].crp_nbits, 8)); } } #endif -static int +static int xlp_rsa_init(struct xlp_rsa_softc *sc, int node) { struct xlp_rsa_command *cmd = NULL; uint32_t fbvc, dstvc, endsel, regval; struct nlm_fmn_msg m; int err, ret, i; uint64_t base; /* Register interrupt handler for the RSA/ECC CMS messages */ if (register_msgring_handler(sc->rsaecc_vc_start, sc->rsaecc_vc_end, nlm_xlprsaecc_msgring_handler, sc) != 0) { err = -1; printf("Couldn't register rsa/ecc msgring handler\n"); goto errout; } fbvc = nlm_cpuid() * 4 + XLPGE_FB_VC; /* Do the CMS credit initialization */ /* Currently it is configured by default to 50 when kernel comes up */ #if BYTE_ORDER == LITTLE_ENDIAN for (i = 0; i < nitems(nlm_rsa_ucode_data); i++) nlm_rsa_ucode_data[i] = htobe64(nlm_rsa_ucode_data[i]); #endif for (dstvc = sc->rsaecc_vc_start; dstvc <= sc->rsaecc_vc_end; dstvc++) { cmd = malloc(sizeof(struct xlp_rsa_command), M_DEVBUF, M_NOWAIT | M_ZERO); KASSERT(cmd != NULL, ("%s:cmd is NULL\n", __func__)); cmd->rsasrc = contigmalloc(sizeof(nlm_rsa_ucode_data), M_DEVBUF, (M_WAITOK | M_ZERO), 0UL /* low address */, -1UL /* high address */, XLP_L2L3_CACHELINE_SIZE /* alignment */, 0UL /* boundary */); KASSERT(cmd->rsasrc != NULL, ("%s:cmd->rsasrc is NULL\n", __func__)); memcpy(cmd->rsasrc, nlm_rsa_ucode_data, sizeof(nlm_rsa_ucode_data)); m.msg[0] = nlm_crypto_form_rsa_ecc_fmn_entry0(1, 0x70, 0, vtophys(cmd->rsasrc)); m.msg[1] = nlm_crypto_form_rsa_ecc_fmn_entry1(0, 1, fbvc, vtophys(cmd->rsasrc)); /* Software scratch pad */ m.msg[2] = (uintptr_t)cmd; m.msg[3] = 0; ret = nlm_fmn_msgsend(dstvc, 3, FMN_SWCODE_RSA, &m); if (ret != 0) { err = -1; printf("%s: msgsnd failed (%x)\n", __func__, ret); goto errout; } } /* Configure so that all VCs send request to all RSA pipes */ base = nlm_get_rsa_regbase(node); if (nlm_is_xlp3xx()) { endsel = 1; regval = 0xFFFF; } else { endsel = 3; regval = 0x07FFFFFF; } for (i = 0; i < endsel; i++) nlm_write_rsa_reg(base, RSA_ENG_SEL_0 + i, regval); return (0); errout: xlp_free_cmd_params(cmd); return (err); } /* This function is called from an interrupt handler */ void nlm_xlprsaecc_msgring_handler(int vc, int size, int code, int src_id, struct nlm_fmn_msg *msg, void *data) { struct xlp_rsa_command *cmd; struct xlp_rsa_softc *sc; struct crparam *outparam; int ostart; KASSERT(code == FMN_SWCODE_RSA, ("%s: bad code = %d, expected code = %d\n", __func__, code, FMN_SWCODE_RSA)); sc = data; KASSERT(src_id >= sc->rsaecc_vc_start && src_id <= sc->rsaecc_vc_end, ("%s: bad src_id = %d, expect %d - %d\n", __func__, src_id, sc->rsaecc_vc_start, sc->rsaecc_vc_end)); cmd = (struct xlp_rsa_command *)(uintptr_t)msg->msg[1]; KASSERT(cmd != NULL, ("%s:cmd not received properly\n", __func__)); if (RSA_ERROR(msg->msg[0]) != 0) { printf("%s: Message rcv msg0 %llx msg1 %llx err %x \n", __func__, (unsigned long long)msg->msg[0], (unsigned long long)msg->msg[1], (int)RSA_ERROR(msg->msg[0])); cmd->krp->krp_status = EBADMSG; } if (cmd->krp != NULL) { ostart = cmd->krp->krp_iparams; outparam = &cmd->krp->krp_param[ostart]; xlp_rsa_inp2hwformat(cmd->rsasrc + cmd->rsaopsize * ostart, outparam->crp_p, howmany(outparam->crp_nbits, 8), 1); crypto_kdone(cmd->krp); } xlp_free_cmd_params(cmd); } static int xlp_rsa_probe(device_t dev) { struct xlp_rsa_softc *sc; if (pci_get_vendor(dev) == PCI_VENDOR_NETLOGIC && pci_get_device(dev) == PCI_DEVICE_ID_NLM_RSA) { sc = device_get_softc(dev); return (BUS_PROBE_DEFAULT); } return (ENXIO); } /* * Attach an interface that successfully probed. */ static int xlp_rsa_attach(device_t dev) { struct xlp_rsa_softc *sc = device_get_softc(dev); uint64_t base; int qstart, qnum; int freq, node; sc->sc_dev = dev; node = nlm_get_device_node(pci_get_slot(dev)); freq = nlm_set_device_frequency(node, DFS_DEVICE_RSA, 250); if (bootverbose) device_printf(dev, "RSA Freq: %dMHz\n", freq); if (pci_get_device(dev) == PCI_DEVICE_ID_NLM_RSA) { device_set_desc(dev, "XLP RSA/ECC Accelerator"); if ((sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE)) < 0) { printf("xlp_rsaecc-err:couldn't get the driver id\n"); goto error_exit; } if (crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0) != 0) goto error_exit; base = nlm_get_rsa_pcibase(node); qstart = nlm_qidstart(base); qnum = nlm_qnum(base); sc->rsaecc_vc_start = qstart; sc->rsaecc_vc_end = qstart + qnum - 1; } if (xlp_rsa_init(sc, node) != 0) goto error_exit; device_printf(dev, "RSA Initialization complete!\n"); return (0); error_exit: return (ENXIO); } /* * Detach an interface that successfully probed. */ static int xlp_rsa_detach(device_t dev) { return (0); } /* * Allocate a new 'session' and return an encoded session id. 'sidp' * contains our registration id, and should contain an encoded session * id on successful allocation. */ static int xlp_rsa_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) { struct xlp_rsa_softc *sc = device_get_softc(dev); struct xlp_rsa_session *ses = NULL; int sesn; if (sidp == NULL || cri == NULL || sc == NULL) return (EINVAL); if (sc->sc_sessions == NULL) { ses = sc->sc_sessions = malloc(sizeof(struct xlp_rsa_session), M_DEVBUF, M_NOWAIT); if (ses == NULL) return (ENOMEM); sesn = 0; sc->sc_nsessions = 1; } else { for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { if (!sc->sc_sessions[sesn].hs_used) { ses = &sc->sc_sessions[sesn]; break; } } if (ses == NULL) { sesn = sc->sc_nsessions; ses = malloc((sesn + 1) * sizeof(*ses), M_DEVBUF, M_NOWAIT); if (ses == NULL) return (ENOMEM); bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses)); bzero(sc->sc_sessions, sesn * sizeof(*ses)); free(sc->sc_sessions, M_DEVBUF); sc->sc_sessions = ses; ses = &sc->sc_sessions[sesn]; sc->sc_nsessions++; } } bzero(ses, sizeof(*ses)); ses->sessionid = sesn; ses->hs_used = 1; *sidp = XLP_RSA_SID(device_get_unit(sc->sc_dev), sesn); return (0); } /* * Deallocate a session. * XXX this routine should run a zero'd mac/encrypt key into context ram. * XXX to blow away any keys already stored there. */ static int xlp_rsa_freesession(device_t dev, u_int64_t tid) { struct xlp_rsa_softc *sc = device_get_softc(dev); int session; u_int32_t sid = CRYPTO_SESID2LID(tid); if (sc == NULL) return (EINVAL); session = XLP_RSA_SESSION(sid); if (session >= sc->sc_nsessions) return (EINVAL); sc->sc_sessions[session].hs_used = 0; return (0); } -static void +static void xlp_free_cmd_params(struct xlp_rsa_command *cmd) { if (cmd == NULL) return; if (cmd->rsasrc != NULL) { if (cmd->krp == NULL) /* Micro code load */ contigfree(cmd->rsasrc, sizeof(nlm_rsa_ucode_data), M_DEVBUF); else free(cmd->rsasrc, M_DEVBUF); } free(cmd, M_DEVBUF); } static int xlp_get_rsa_opsize(struct xlp_rsa_command *cmd, unsigned int bits) { if (bits == 0 || bits > 8192) return (-1); /* XLP hardware expects always a fixed size with unused bytes * zeroed out in the input data */ if (bits <= 512) { cmd->rsatype = 0x40; cmd->rsaopsize = 64; } else if (bits <= 1024) { cmd->rsatype = 0x41; cmd->rsaopsize = 128; } else if (bits <= 2048) { cmd->rsatype = 0x42; cmd->rsaopsize = 256; } else if (bits <= 4096) { cmd->rsatype = 0x43; cmd->rsaopsize = 512; } else if (bits <= 8192) { cmd->rsatype = 0x44; cmd->rsaopsize = 1024; } return (0); } static int xlp_rsa_inp2hwformat(uint8_t *src, uint8_t *dst, uint32_t paramsize, uint8_t result) { uint32_t pdwords, pbytes; int i, j, k; pdwords = paramsize / 8; pbytes = paramsize % 8; for (i = 0, k = 0; i < pdwords; i++) { /* copy dwords of inp/hw to hw/out format */ for (j = 7; j >= 0; j--, k++) dst[i * 8 + j] = src[k]; } if (pbytes) { if (result == 0) { /* copy rem bytes of input data to hw format */ for (j = 7; k < paramsize; j--, k++) dst[i * 8 + j] = src[k]; } else { /* copy rem bytes of hw data to exp output format */ for (j = 7; k < paramsize; j--, k++) dst[k] = src[i * 8 + j]; } } return (0); } static int nlm_crypto_complete_rsa_request(struct xlp_rsa_softc *sc, struct xlp_rsa_command *cmd) { unsigned int fbvc; struct nlm_fmn_msg m; int ret; fbvc = nlm_cpuid() * 4 + XLPGE_FB_VC; m.msg[0] = nlm_crypto_form_rsa_ecc_fmn_entry0(1, cmd->rsatype, cmd->rsafn, vtophys(cmd->rsasrc)); m.msg[1] = nlm_crypto_form_rsa_ecc_fmn_entry1(0, 1, fbvc, vtophys(cmd->rsasrc + cmd->rsaopsize * cmd->krp->krp_iparams)); /* Software scratch pad */ m.msg[2] = (uintptr_t)cmd; m.msg[3] = 0; /* Send the message to rsa engine vc */ ret = nlm_fmn_msgsend(sc->rsaecc_vc_start, 3, FMN_SWCODE_RSA, &m); if (ret != 0) { #ifdef NLM_SEC_DEBUG printf("%s: msgsnd failed (%x)\n", __func__, ret); #endif return (ERESTART); } return (0); } static int xlp_rsa_kprocess(device_t dev, struct cryptkop *krp, int hint) { struct xlp_rsa_softc *sc = device_get_softc(dev); struct xlp_rsa_command *cmd; struct crparam *kp; int err, i; if (krp == NULL || krp->krp_callback == NULL) return (EINVAL); cmd = malloc(sizeof(struct xlp_rsa_command), M_DEVBUF, M_NOWAIT | M_ZERO); KASSERT(cmd != NULL, ("%s:cmd is NULL\n", __func__)); cmd->krp = krp; #ifdef NLM_RSA_DEBUG print_krp_params(krp); #endif err = EOPNOTSUPP; switch (krp->krp_op) { case CRK_MOD_EXP: if (krp->krp_iparams == 3 && krp->krp_oparams == 1) break; goto errout; default: device_printf(dev, "Op:%d not yet supported\n", krp->krp_op); goto errout; } err = xlp_get_rsa_opsize(cmd, krp->krp_param[krp->krp_iparams - 1].crp_nbits); if (err != 0) { err = EINVAL; goto errout; } cmd->rsafn = 0; /* Mod Exp */ cmd->rsasrc = malloc( cmd->rsaopsize * (krp->krp_iparams + krp->krp_oparams), M_DEVBUF, M_NOWAIT | M_ZERO); if (cmd->rsasrc == NULL) { err = ENOMEM; goto errout; } for (i = 0, kp = krp->krp_param; i < krp->krp_iparams; i++, kp++) { KASSERT(kp->crp_nbits != 0, ("%s: parameter[%d]'s length is zero\n", __func__, i)); xlp_rsa_inp2hwformat(kp->crp_p, cmd->rsasrc + i * cmd->rsaopsize, howmany(kp->crp_nbits, 8), 0); } err = nlm_crypto_complete_rsa_request(sc, cmd); if (err != 0) goto errout; return (0); errout: xlp_free_cmd_params(cmd); krp->krp_status = err; crypto_kdone(krp); return (err); } Index: head/sys/mips/nlm/dev/sec/nlmrsalib.h =================================================================== --- head/sys/mips/nlm/dev/sec/nlmrsalib.h (revision 279387) +++ head/sys/mips/nlm/dev/sec/nlmrsalib.h (revision 279388) @@ -1,70 +1,70 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _NLMRSALIB_H_ #define _NLMRSALIB_H_ #define XLP_RSA_SESSION(sid) ((sid) & 0x000007ff) #define XLP_RSA_SID(crd,ses) (((crd) << 28) | ((ses) & 0x7ff)) #define RSA_ERROR(msg0) (((msg0) >> 53) & 0x1f) struct xlp_rsa_session { uint32_t sessionid; int hs_used; }; struct xlp_rsa_command { uint16_t session_num; struct xlp_rsa_session *ses; struct cryptkop *krp; uint8_t *rsasrc; uint32_t rsaopsize; uint32_t rsatype; uint32_t rsafn; }; /* * Holds data specific to nlm security accelerators */ struct xlp_rsa_softc { device_t sc_dev; /* device backpointer */ uint64_t rsa_base; int sc_cid; struct xlp_rsa_session *sc_sessions; int sc_nsessions; int rsaecc_vc_start; int rsaecc_vc_end; }; void nlm_xlprsaecc_msgring_handler(int vc, int size, int code, int src_id, struct nlm_fmn_msg *msg, void *data); #endif /* _NLMRSALIB_H_ */ Index: head/sys/mips/nlm/dev/sec/nlmsec.c =================================================================== --- head/sys/mips/nlm/dev/sec/nlmsec.c (revision 279387) +++ head/sys/mips/nlm/dev/sec/nlmsec.c (revision 279388) @@ -1,850 +1,850 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "cryptodev_if.h" #include #include #include #include #include #include #include #include #include #include #include #include unsigned int creditleft; void xlp_sec_print_data(struct cryptop *crp); static int xlp_sec_init(struct xlp_sec_softc *sc); static int xlp_sec_newsession(device_t , uint32_t *, struct cryptoini *); static int xlp_sec_freesession(device_t , uint64_t); static int xlp_sec_process(device_t , struct cryptop *, int); static int xlp_copyiv(struct xlp_sec_softc *, struct xlp_sec_command *, struct cryptodesc *enccrd); static int xlp_get_nsegs(struct cryptop *, unsigned int *); static int xlp_alloc_cmd_params(struct xlp_sec_command *, unsigned int); static void xlp_free_cmd_params(struct xlp_sec_command *); static int xlp_sec_probe(device_t); static int xlp_sec_attach(device_t); static int xlp_sec_detach(device_t); static device_method_t xlp_sec_methods[] = { /* device interface */ DEVMETHOD(device_probe, xlp_sec_probe), DEVMETHOD(device_attach, xlp_sec_attach), DEVMETHOD(device_detach, xlp_sec_detach), /* bus interface */ DEVMETHOD(bus_print_child, bus_generic_print_child), DEVMETHOD(bus_driver_added, bus_generic_driver_added), /* crypto device methods */ DEVMETHOD(cryptodev_newsession, xlp_sec_newsession), DEVMETHOD(cryptodev_freesession,xlp_sec_freesession), DEVMETHOD(cryptodev_process, xlp_sec_process), DEVMETHOD_END }; static driver_t xlp_sec_driver = { "nlmsec", xlp_sec_methods, sizeof(struct xlp_sec_softc) }; static devclass_t xlp_sec_devclass; DRIVER_MODULE(nlmsec, pci, xlp_sec_driver, xlp_sec_devclass, 0, 0); MODULE_DEPEND(nlmsec, crypto, 1, 1, 1); void -nlm_xlpsec_msgring_handler(int vc, int size, int code, int src_id, +nlm_xlpsec_msgring_handler(int vc, int size, int code, int src_id, struct nlm_fmn_msg *msg, void *data); #ifdef NLM_SEC_DEBUG -#define extract_bits(x, bitshift, bitcnt) \ +#define extract_bits(x, bitshift, bitcnt) \ (((unsigned long long)x >> bitshift) & ((1ULL << bitcnt) - 1)) void print_crypto_params(struct xlp_sec_command *cmd, struct nlm_fmn_msg m) { unsigned long long msg0,msg1,msg2,msg3,msg4,msg5,msg6,msg7,msg8; msg0 = cmd->ctrlp->desc0; msg1 = cmd->paramp->desc0; msg2 = cmd->paramp->desc1; msg3 = cmd->paramp->desc2; msg4 = cmd->paramp->desc3; msg5 = cmd->paramp->segment[0][0]; msg6 = cmd->paramp->segment[0][1]; msg7 = m.msg[0]; msg8 = m.msg[1]; printf("msg0 %llx msg1 %llx msg2 %llx msg3 %llx msg4 %llx msg5 %llx" "msg6 %llx msg7 %llx msg8 %llx\n", msg0, msg1, msg2, msg3, msg4, msg5, msg6, msg7, msg8); printf("c0: hmac %d htype %d hmode %d ctype %d cmode %d arc4 %x\n", (unsigned int)extract_bits(msg0, 61, 1), (unsigned int)extract_bits(msg0, 52, 8), (unsigned int)extract_bits(msg0, 43, 8), (unsigned int)extract_bits(msg0, 34, 8), (unsigned int)extract_bits(msg0, 25, 8), (unsigned int)extract_bits(msg0, 0, 23)); printf("p0: tls %d hsrc %d hl3 %d enc %d ivl %d hd %llx\n", (unsigned int)extract_bits(msg1, 63, 1), (unsigned int)extract_bits(msg1,62,1), (unsigned int)extract_bits(msg1,60,1), (unsigned int)extract_bits(msg1,59,1), (unsigned int)extract_bits(msg1,41,16), extract_bits(msg1,0,40)); printf("p1: clen %u hl %u\n", (unsigned int)extract_bits(msg2, 32, 32), (unsigned int)extract_bits(msg2,0,32)); printf("p2: ivoff %d cbit %d coff %d hbit %d hclb %d hoff %d\n", (unsigned int)extract_bits(msg3, 45, 17), (unsigned int)extract_bits(msg3, 42,3), (unsigned int)extract_bits(msg3, 22,16), (unsigned int)extract_bits(msg3, 19,3), (unsigned int)extract_bits(msg3, 18,1), (unsigned int)extract_bits(msg3, 0, 16)); printf("p3: desfbid %d tlen %d arc4 %x hmacpad %d\n", (unsigned int)extract_bits(msg4, 48,16), (unsigned int)extract_bits(msg4,11,16), (unsigned int)extract_bits(msg4,6,3), (unsigned int)extract_bits(msg4,5,1)); printf("p4: sflen %d sddr %llx \n", (unsigned int)extract_bits(msg5, 48, 16),extract_bits(msg5, 0, 40)); printf("p5: dflen %d cl3 %d cclob %d cdest %llx \n", (unsigned int)extract_bits(msg6, 48, 16), (unsigned int)extract_bits(msg6, 46, 1), (unsigned int)extract_bits(msg6, 41, 1), extract_bits(msg6, 0, 40)); printf("fmn0: fbid %d dfrlen %d dfrv %d cklen %d cdescaddr %llx\n", (unsigned int)extract_bits(msg7, 48, 16), (unsigned int)extract_bits(msg7,46,2), (unsigned int)extract_bits(msg7,45,1), (unsigned int)extract_bits(msg7,40,5), (extract_bits(msg7,0,34)<< 6)); printf("fmn1: arc4 %d hklen %d pdesclen %d pktdescad %llx\n", (unsigned int)extract_bits(msg8, 63, 1), (unsigned int)extract_bits(msg8,56,5), (unsigned int)extract_bits(msg8,43,12), (extract_bits(msg8,0,34) << 6)); return; } -void +void xlp_sec_print_data(struct cryptop *crp) { int i, key_len; struct cryptodesc *crp_desc; printf("session id = 0x%llx, crp_ilen = %d, crp_olen=%d \n", crp->crp_sid, crp->crp_ilen, crp->crp_olen); printf("crp_flags = 0x%x\n", crp->crp_flags); printf("crp buf:\n"); for (i = 0; i < crp->crp_ilen; i++) { printf("%c ", crp->crp_buf[i]); if (i % 10 == 0) printf("\n"); } printf("\n"); printf("****************** desc ****************\n"); crp_desc = crp->crp_desc; printf("crd_skip=%d, crd_len=%d, crd_flags=0x%x, crd_alg=%d\n", crp_desc->crd_skip, crp_desc->crd_len, crp_desc->crd_flags, crp_desc->crd_alg); key_len = crp_desc->crd_klen / 8; printf("key(%d) :\n", key_len); for (i = 0; i < key_len; i++) printf("%d", crp_desc->crd_key[i]); printf("\n"); printf(" IV : \n"); for (i = 0; i < EALG_MAX_BLOCK_LEN; i++) printf("%d", crp_desc->crd_iv[i]); printf("\n"); printf("crd_next=%p\n", crp_desc->crd_next); return; } void print_cmd(struct xlp_sec_command *cmd) { printf("session_num :%d\n",cmd->session_num); printf("crp :0x%x\n",(uint32_t)cmd->crp); printf("enccrd :0x%x\n",(uint32_t)cmd->enccrd); printf("maccrd :0x%x\n",(uint32_t)cmd->maccrd); printf("ses :%d\n",(uint32_t)cmd->ses); printf("ctrlp :0x%x\n",(uint32_t)cmd->ctrlp); printf("paramp :0x%x\n",(uint32_t)cmd->paramp); printf("hashdest :0x%x\n",(uint32_t)cmd->hashdest); printf("hashsrc :%d\n",cmd->hashsrc); printf("hmacpad :%d\n",cmd->hmacpad); printf("hashoff :%d\n",cmd->hashoff); printf("hashlen :%d\n",cmd->hashlen); printf("cipheroff :%d\n",cmd->cipheroff); printf("cipherlen :%d\n",cmd->cipherlen); printf("ivoff :%d\n",cmd->ivoff); printf("ivlen :%d\n",cmd->ivlen); printf("hashalg :%d\n",cmd->hashalg); printf("hashmode :%d\n",cmd->hashmode); printf("cipheralg :%d\n",cmd->cipheralg); printf("ciphermode :%d\n",cmd->ciphermode); printf("nsegs :%d\n",cmd->nsegs); printf("hash_dst_len :%d\n",cmd->hash_dst_len); } #endif /* NLM_SEC_DEBUG */ -static int +static int xlp_sec_init(struct xlp_sec_softc *sc) { /* Register interrupt handler for the SEC CMS messages */ if (register_msgring_handler(sc->sec_vc_start, sc->sec_vc_end, nlm_xlpsec_msgring_handler, sc) != 0) { printf("Couldn't register sec msgring handler\n"); return (-1); } /* Do the CMS credit initialization */ /* Currently it is configured by default to 50 when kernel comes up */ return (0); } /* This function is called from an interrupt handler */ void nlm_xlpsec_msgring_handler(int vc, int size, int code, int src_id, struct nlm_fmn_msg *msg, void *data) { struct xlp_sec_command *cmd = NULL; struct xlp_sec_softc *sc = NULL; struct cryptodesc *crd = NULL; unsigned int ivlen = 0; KASSERT(code == FMN_SWCODE_CRYPTO, ("%s: bad code = %d, expected code = %d\n", __FUNCTION__, code, FMN_SWCODE_CRYPTO)); sc = (struct xlp_sec_softc *)data; KASSERT(src_id >= sc->sec_vc_start && src_id <= sc->sec_vc_end, ("%s: bad src_id = %d, expect %d - %d\n", __FUNCTION__, src_id, sc->sec_vc_start, sc->sec_vc_end)); cmd = (struct xlp_sec_command *)(uintptr_t)msg->msg[0]; KASSERT(cmd != NULL && cmd->crp != NULL, ("%s :cmd not received properly\n",__FUNCTION__)); KASSERT(CRYPTO_ERROR(msg->msg[1]) == 0, ("%s: Message rcv msg0 %llx msg1 %llx err %x \n", __FUNCTION__, (unsigned long long)msg->msg[0], (unsigned long long)msg->msg[1], (int)CRYPTO_ERROR(msg->msg[1]))); crd = cmd->enccrd; /* Copy the last 8 or 16 bytes to the session iv, so that in few * cases this will be used as IV for the next request */ if (crd != NULL) { if ((crd->crd_alg == CRYPTO_DES_CBC || crd->crd_alg == CRYPTO_3DES_CBC || crd->crd_alg == CRYPTO_AES_CBC) && (crd->crd_flags & CRD_F_ENCRYPT)) { ivlen = ((crd->crd_alg == CRYPTO_AES_CBC) ? XLP_SEC_AES_IV_LENGTH : XLP_SEC_DES_IV_LENGTH); crypto_copydata(cmd->crp->crp_flags, cmd->crp->crp_buf, crd->crd_skip + crd->crd_len - ivlen, ivlen, sc->sc_sessions[cmd->session_num].ses_iv); } } /* If there are not enough credits to send, then send request * will fail with ERESTART and the driver will be blocked until it is * unblocked here after knowing that there are sufficient credits to * send the request again. */ if (sc->sc_needwakeup) { atomic_add_int(&creditleft, sc->sec_msgsz); if (creditleft >= (NLM_CRYPTO_LEFT_REQS)) { crypto_unblock(sc->sc_cid, sc->sc_needwakeup); sc->sc_needwakeup &= (~(CRYPTO_SYMQ | CRYPTO_ASYMQ)); } } if(cmd->maccrd) { crypto_copyback(cmd->crp->crp_flags, cmd->crp->crp_buf, cmd->maccrd->crd_inject, cmd->hash_dst_len, cmd->hashdest); } /* This indicates completion of the crypto operation */ crypto_done(cmd->crp); xlp_free_cmd_params(cmd); return; } static int xlp_sec_probe(device_t dev) { struct xlp_sec_softc *sc; if (pci_get_vendor(dev) == PCI_VENDOR_NETLOGIC && pci_get_device(dev) == PCI_DEVICE_ID_NLM_SAE) { sc = device_get_softc(dev); return (BUS_PROBE_DEFAULT); } return (ENXIO); } /* * Attach an interface that successfully probed. */ static int xlp_sec_attach(device_t dev) { struct xlp_sec_softc *sc = device_get_softc(dev); uint64_t base; int qstart, qnum; int freq, node; sc->sc_dev = dev; node = nlm_get_device_node(pci_get_slot(dev)); freq = nlm_set_device_frequency(node, DFS_DEVICE_SAE, 250); if (bootverbose) device_printf(dev, "SAE Freq: %dMHz\n", freq); if(pci_get_device(dev) == PCI_DEVICE_ID_NLM_SAE) { device_set_desc(dev, "XLP Security Accelerator"); sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE); if (sc->sc_cid < 0) { printf("xlp_sec - error : could not get the driver" " id\n"); goto error_exit; } if (crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0) != 0) printf("register failed for CRYPTO_DES_CBC\n"); if (crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0) != 0) printf("register failed for CRYPTO_3DES_CBC\n"); if (crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0) != 0) printf("register failed for CRYPTO_AES_CBC\n"); if (crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0) != 0) printf("register failed for CRYPTO_ARC4\n"); if (crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0) != 0) printf("register failed for CRYPTO_MD5\n"); if (crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0) != 0) printf("register failed for CRYPTO_SHA1\n"); if (crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0) != 0) printf("register failed for CRYPTO_MD5_HMAC\n"); if (crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0) != 0) printf("register failed for CRYPTO_SHA1_HMAC\n"); base = nlm_get_sec_pcibase(node); qstart = nlm_qidstart(base); qnum = nlm_qnum(base); sc->sec_vc_start = qstart; sc->sec_vc_end = qstart + qnum - 1; } if (xlp_sec_init(sc) != 0) goto error_exit; if (bootverbose) device_printf(dev, "SEC Initialization complete!\n"); return (0); error_exit: return (ENXIO); } /* * Detach an interface that successfully probed. */ static int xlp_sec_detach(device_t dev) { return (0); } /* * Allocate a new 'session' and return an encoded session id. 'sidp' * contains our registration id, and should contain an encoded session * id on successful allocation. */ static int xlp_sec_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) { struct cryptoini *c; struct xlp_sec_softc *sc = device_get_softc(dev); int mac = 0, cry = 0, sesn; struct xlp_sec_session *ses = NULL; struct xlp_sec_command *cmd = NULL; if (sidp == NULL || cri == NULL || sc == NULL) return (EINVAL); if (sc->sc_sessions == NULL) { ses = sc->sc_sessions = malloc(sizeof(struct xlp_sec_session), M_DEVBUF, M_NOWAIT); if (ses == NULL) return (ENOMEM); sesn = 0; sc->sc_nsessions = 1; } else { for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { if (!sc->sc_sessions[sesn].hs_used) { ses = &sc->sc_sessions[sesn]; break; } } if (ses == NULL) { sesn = sc->sc_nsessions; ses = malloc((sesn + 1)*sizeof(struct xlp_sec_session), M_DEVBUF, M_NOWAIT); if (ses == NULL) return (ENOMEM); bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses)); bzero(sc->sc_sessions, sesn * sizeof(*ses)); free(sc->sc_sessions, M_DEVBUF); sc->sc_sessions = ses; ses = &sc->sc_sessions[sesn]; sc->sc_nsessions++; } } bzero(ses, sizeof(*ses)); ses->sessionid = sesn; cmd = &ses->cmd; ses->hs_used = 1; for (c = cri; c != NULL; c = c->cri_next) { switch (c->cri_alg) { case CRYPTO_MD5: case CRYPTO_SHA1: case CRYPTO_MD5_HMAC: case CRYPTO_SHA1_HMAC: if (mac) return (EINVAL); mac = 1; ses->hs_mlen = c->cri_mlen; if (ses->hs_mlen == 0) { switch (c->cri_alg) { case CRYPTO_MD5: case CRYPTO_MD5_HMAC: ses->hs_mlen = 16; break; case CRYPTO_SHA1: case CRYPTO_SHA1_HMAC: ses->hs_mlen = 20; break; } } break; case CRYPTO_DES_CBC: case CRYPTO_3DES_CBC: case CRYPTO_AES_CBC: /* XXX this may read fewer, does it matter? */ read_random(ses->ses_iv, c->cri_alg == CRYPTO_AES_CBC ? XLP_SEC_AES_IV_LENGTH : XLP_SEC_DES_IV_LENGTH); /* FALLTHROUGH */ case CRYPTO_ARC4: if (cry) return (EINVAL); cry = 1; break; default: return (EINVAL); } } if (mac == 0 && cry == 0) return (EINVAL); cmd->hash_dst_len = ses->hs_mlen; *sidp = XLP_SEC_SID(device_get_unit(sc->sc_dev), sesn); return (0); } /* * Deallocate a session. * XXX this routine should run a zero'd mac/encrypt key into context ram. * XXX to blow away any keys already stored there. */ static int xlp_sec_freesession(device_t dev, u_int64_t tid) { struct xlp_sec_softc *sc = device_get_softc(dev); int session; u_int32_t sid = CRYPTO_SESID2LID(tid); if (sc == NULL) return (EINVAL); session = XLP_SEC_SESSION(sid); if (session >= sc->sc_nsessions) return (EINVAL); sc->sc_sessions[session].hs_used = 0; return (0); } static int xlp_copyiv(struct xlp_sec_softc *sc, struct xlp_sec_command *cmd, struct cryptodesc *enccrd) { unsigned int ivlen = 0; int session; struct cryptop *crp = NULL; crp = cmd->crp; session = cmd->session_num; if (enccrd->crd_alg != CRYPTO_ARC4) { ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ? XLP_SEC_AES_IV_LENGTH : XLP_SEC_DES_IV_LENGTH); if (enccrd->crd_flags & CRD_F_ENCRYPT) { if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { bcopy(enccrd->crd_iv, cmd->iv, ivlen); } else { bcopy(sc->sc_sessions[session].ses_iv, cmd->iv, ivlen); } if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { crypto_copyback(crp->crp_flags, crp->crp_buf, enccrd->crd_inject, ivlen, cmd->iv); } } else { if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { bcopy(enccrd->crd_iv, cmd->iv, ivlen); } else { crypto_copydata(crp->crp_flags, crp->crp_buf, enccrd->crd_inject, ivlen, cmd->iv); } } } return (0); } static int xlp_get_nsegs(struct cryptop *crp, unsigned int *nsegs) { if (crp->crp_flags & CRYPTO_F_IMBUF) { struct mbuf *m = NULL; m = (struct mbuf *)crp->crp_buf; while (m != NULL) { *nsegs += NLM_CRYPTO_NUM_SEGS_REQD(m->m_len); m = m->m_next; } } else if (crp->crp_flags & CRYPTO_F_IOV) { struct uio *uio = NULL; struct iovec *iov = NULL; int iol = 0; uio = (struct uio *)crp->crp_buf; iov = (struct iovec *)uio->uio_iov; iol = uio->uio_iovcnt; while (iol > 0) { *nsegs += NLM_CRYPTO_NUM_SEGS_REQD(iov->iov_len); iol--; iov++; } } else { *nsegs = NLM_CRYPTO_NUM_SEGS_REQD(crp->crp_ilen); } return (0); } static int xlp_alloc_cmd_params(struct xlp_sec_command *cmd, unsigned int nsegs) { int err = 0; if(cmd == NULL) { err = EINVAL; goto error; } if ((cmd->ctrlp = malloc(sizeof(struct nlm_crypto_pkt_ctrl), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { err = ENOMEM; goto error; } if (((uintptr_t)cmd->ctrlp & (XLP_L2L3_CACHELINE_SIZE - 1))) { err = EINVAL; goto error; } /* (nsegs - 1) because one seg is part of the structure already */ if ((cmd->paramp = malloc(sizeof(struct nlm_crypto_pkt_param) + (16 * (nsegs - 1)), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { err = ENOMEM; goto error; } if (((uintptr_t)cmd->paramp & (XLP_L2L3_CACHELINE_SIZE - 1))) { err = EINVAL; goto error; } if ((cmd->iv = malloc(EALG_MAX_BLOCK_LEN, M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { err = ENOMEM; goto error; } if ((cmd->hashdest = malloc(HASH_MAX_LEN, M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { err = ENOMEM; goto error; } error: return (err); } -static void +static void xlp_free_cmd_params(struct xlp_sec_command *cmd) { if (cmd->ctrlp != NULL) free(cmd->ctrlp, M_DEVBUF); if (cmd->paramp != NULL) free(cmd->paramp, M_DEVBUF); if (cmd->iv != NULL) free(cmd->iv, M_DEVBUF); if (cmd->hashdest != NULL) free(cmd->hashdest, M_DEVBUF); if (cmd != NULL) free(cmd, M_DEVBUF); return; } static int xlp_sec_process(device_t dev, struct cryptop *crp, int hint) { struct xlp_sec_softc *sc = device_get_softc(dev); struct xlp_sec_command *cmd = NULL; int session, err = -1, ret = 0; struct cryptodesc *crd1, *crd2; struct xlp_sec_session *ses; unsigned int nsegs = 0; if (crp == NULL || crp->crp_callback == NULL) { return (EINVAL); } session = XLP_SEC_SESSION(crp->crp_sid); if (sc == NULL || session >= sc->sc_nsessions) { err = EINVAL; goto errout; } ses = &sc->sc_sessions[session]; if ((cmd = malloc(sizeof(struct xlp_sec_command), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { err = ENOMEM; goto errout; } cmd->crp = crp; cmd->session_num = session; cmd->hash_dst_len = ses->hs_mlen; if ((crd1 = crp->crp_desc) == NULL) { err = EINVAL; goto errout; } crd2 = crd1->crd_next; if ((ret = xlp_get_nsegs(crp, &nsegs)) != 0) { err = EINVAL; goto errout; } if (((crd1 != NULL) && (crd1->crd_flags & CRD_F_IV_EXPLICIT)) || ((crd2 != NULL) && (crd2->crd_flags & CRD_F_IV_EXPLICIT))) { /* Since IV is given as separate segment to avoid copy */ nsegs += 1; } cmd->nsegs = nsegs; if ((err = xlp_alloc_cmd_params(cmd, nsegs)) != 0) goto errout; if ((crd1 != NULL) && (crd2 == NULL)) { if (crd1->crd_alg == CRYPTO_DES_CBC || crd1->crd_alg == CRYPTO_3DES_CBC || crd1->crd_alg == CRYPTO_AES_CBC || crd1->crd_alg == CRYPTO_ARC4) { cmd->enccrd = crd1; cmd->maccrd = NULL; if ((ret = nlm_get_cipher_param(cmd)) != 0) { err = EINVAL; goto errout; } if (crd1->crd_flags & CRD_F_IV_EXPLICIT) cmd->cipheroff = cmd->ivlen; - else + else cmd->cipheroff = cmd->enccrd->crd_skip; cmd->cipherlen = cmd->enccrd->crd_len; if (crd1->crd_flags & CRD_F_IV_PRESENT) cmd->ivoff = 0; else cmd->ivoff = cmd->enccrd->crd_inject; if ((err = xlp_copyiv(sc, cmd, cmd->enccrd)) != 0) goto errout; if ((err = nlm_crypto_do_cipher(sc, cmd)) != 0) goto errout; } else if (crd1->crd_alg == CRYPTO_MD5_HMAC || crd1->crd_alg == CRYPTO_SHA1_HMAC || crd1->crd_alg == CRYPTO_SHA1 || crd1->crd_alg == CRYPTO_MD5) { cmd->enccrd = NULL; cmd->maccrd = crd1; if ((ret = nlm_get_digest_param(cmd)) != 0) { err = EINVAL; goto errout; } cmd->hashoff = cmd->maccrd->crd_skip; cmd->hashlen = cmd->maccrd->crd_len; cmd->hmacpad = 0; cmd->hashsrc = 0; if ((err = nlm_crypto_do_digest(sc, cmd)) != 0) goto errout; } else { err = EINVAL; goto errout; } } else if( (crd1 != NULL) && (crd2 != NULL) ) { if ((crd1->crd_alg == CRYPTO_MD5_HMAC || crd1->crd_alg == CRYPTO_SHA1_HMAC || crd1->crd_alg == CRYPTO_MD5 || crd1->crd_alg == CRYPTO_SHA1) && (crd2->crd_alg == CRYPTO_DES_CBC || crd2->crd_alg == CRYPTO_3DES_CBC || crd2->crd_alg == CRYPTO_AES_CBC || crd2->crd_alg == CRYPTO_ARC4)) { cmd->maccrd = crd1; cmd->enccrd = crd2; } else if ((crd1->crd_alg == CRYPTO_DES_CBC || crd1->crd_alg == CRYPTO_ARC4 || crd1->crd_alg == CRYPTO_3DES_CBC || crd1->crd_alg == CRYPTO_AES_CBC) && (crd2->crd_alg == CRYPTO_MD5_HMAC || crd2->crd_alg == CRYPTO_SHA1_HMAC || crd2->crd_alg == CRYPTO_MD5 || crd2->crd_alg == CRYPTO_SHA1)) { cmd->enccrd = crd1; cmd->maccrd = crd2; } else { err = EINVAL; goto errout; } if ((ret = nlm_get_cipher_param(cmd)) != 0) { err = EINVAL; goto errout; } if ((ret = nlm_get_digest_param(cmd)) != 0) { err = EINVAL; goto errout; } cmd->ivoff = cmd->enccrd->crd_inject; cmd->hashoff = cmd->maccrd->crd_skip; cmd->hashlen = cmd->maccrd->crd_len; cmd->hmacpad = 0; if (cmd->enccrd->crd_flags & CRD_F_ENCRYPT) cmd->hashsrc = 1; else cmd->hashsrc = 0; cmd->cipheroff = cmd->enccrd->crd_skip; cmd->cipherlen = cmd->enccrd->crd_len; if ((err = xlp_copyiv(sc, cmd, cmd->enccrd)) != 0) goto errout; if ((err = nlm_crypto_do_cipher_digest(sc, cmd)) != 0) goto errout; } else { err = EINVAL; goto errout; } return (0); errout: xlp_free_cmd_params(cmd); if (err == ERESTART) { sc->sc_needwakeup |= CRYPTO_SYMQ; creditleft = 0; return (err); } crp->crp_etype = err; crypto_done(crp); return (err); } Index: head/sys/mips/nlm/dev/sec/nlmseclib.c =================================================================== --- head/sys/mips/nlm/dev/sec/nlmseclib.c (revision 279387) +++ head/sys/mips/nlm/dev/sec/nlmseclib.c (revision 279388) @@ -1,307 +1,307 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include static int nlm_crypto_complete_sec_request(struct xlp_sec_softc *sc, struct xlp_sec_command *cmd) { unsigned int fbvc; struct nlm_fmn_msg m; int ret; fbvc = nlm_cpuid() / CMS_MAX_VCPU_VC; m.msg[0] = m.msg[1] = m.msg[2] = m.msg[3] = 0; m.msg[0] = nlm_crypto_form_pkt_fmn_entry0(fbvc, 0, 0, cmd->ctrlp->cipherkeylen, vtophys(cmd->ctrlp)); m.msg[1] = nlm_crypto_form_pkt_fmn_entry1(0, cmd->ctrlp->hashkeylen, NLM_CRYPTO_PKT_DESC_SIZE(cmd->nsegs), vtophys(cmd->paramp)); /* Software scratch pad */ m.msg[2] = (uintptr_t)cmd; sc->sec_msgsz = 3; /* Send the message to sec/rsa engine vc */ ret = nlm_fmn_msgsend(sc->sec_vc_start, sc->sec_msgsz, FMN_SWCODE_CRYPTO, &m); if (ret != 0) { #ifdef NLM_SEC_DEBUG printf("%s: msgsnd failed (%x)\n", __func__, ret); #endif return (ERESTART); } return (0); } int nlm_crypto_form_srcdst_segs(struct xlp_sec_command *cmd) { unsigned int srcseg = 0, dstseg = 0; struct cryptodesc *cipdesc = NULL; struct cryptop *crp = NULL; crp = cmd->crp; cipdesc = cmd->enccrd; if (cipdesc != NULL) { /* IV is given as ONE segment to avoid copy */ if (cipdesc->crd_flags & CRD_F_IV_EXPLICIT) { srcseg = nlm_crypto_fill_src_seg(cmd->paramp, srcseg, cmd->iv, cmd->ivlen); dstseg = nlm_crypto_fill_dst_seg(cmd->paramp, dstseg, cmd->iv, cmd->ivlen); } } if (crp->crp_flags & CRYPTO_F_IMBUF) { struct mbuf *m = NULL; m = (struct mbuf *)crp->crp_buf; while (m != NULL) { srcseg = nlm_crypto_fill_src_seg(cmd->paramp, srcseg, mtod(m,caddr_t), m->m_len); if (cipdesc != NULL) { dstseg = nlm_crypto_fill_dst_seg(cmd->paramp, dstseg, mtod(m,caddr_t), m->m_len); } m = m->m_next; } } else if (crp->crp_flags & CRYPTO_F_IOV) { struct uio *uio = NULL; struct iovec *iov = NULL; int iol = 0; uio = (struct uio *)crp->crp_buf; iov = (struct iovec *)uio->uio_iov; iol = uio->uio_iovcnt; while (iol > 0) { srcseg = nlm_crypto_fill_src_seg(cmd->paramp, srcseg, (caddr_t)iov->iov_base, iov->iov_len); if (cipdesc != NULL) { dstseg = nlm_crypto_fill_dst_seg(cmd->paramp, dstseg, (caddr_t)iov->iov_base, iov->iov_len); } iov++; iol--; } } else { srcseg = nlm_crypto_fill_src_seg(cmd->paramp, srcseg, ((caddr_t)crp->crp_buf), crp->crp_ilen); if (cipdesc != NULL) { dstseg = nlm_crypto_fill_dst_seg(cmd->paramp, dstseg, ((caddr_t)crp->crp_buf), crp->crp_ilen); } } return (0); } int nlm_crypto_do_cipher(struct xlp_sec_softc *sc, struct xlp_sec_command *cmd) { struct cryptodesc *cipdesc = NULL; unsigned char *cipkey = NULL; int ret = 0; cipdesc = cmd->enccrd; cipkey = (unsigned char *)cipdesc->crd_key; if (cmd->cipheralg == NLM_CIPHER_3DES) { if (!(cipdesc->crd_flags & CRD_F_ENCRYPT)) { uint64_t *k, *tkey; k = (uint64_t *)cipdesc->crd_key; tkey = (uint64_t *)cmd->des3key; tkey[2] = k[0]; tkey[1] = k[1]; tkey[0] = k[2]; cipkey = (unsigned char *)tkey; } } nlm_crypto_fill_pkt_ctrl(cmd->ctrlp, 0, NLM_HASH_BYPASS, 0, cmd->cipheralg, cmd->ciphermode, cipkey, (cipdesc->crd_klen >> 3), NULL, 0); nlm_crypto_fill_cipher_pkt_param(cmd->ctrlp, cmd->paramp, (cipdesc->crd_flags & CRD_F_ENCRYPT) ? 1 : 0, cmd->ivoff, cmd->ivlen, cmd->cipheroff, cmd->cipherlen); nlm_crypto_form_srcdst_segs(cmd); ret = nlm_crypto_complete_sec_request(sc, cmd); return (ret); } int nlm_crypto_do_digest(struct xlp_sec_softc *sc, struct xlp_sec_command *cmd) { struct cryptodesc *digdesc = NULL; int ret=0; digdesc = cmd->maccrd; nlm_crypto_fill_pkt_ctrl(cmd->ctrlp, (digdesc->crd_klen) ? 1 : 0, cmd->hashalg, cmd->hashmode, NLM_CIPHER_BYPASS, 0, NULL, 0, digdesc->crd_key, digdesc->crd_klen >> 3); nlm_crypto_fill_auth_pkt_param(cmd->ctrlp, cmd->paramp, cmd->hashoff, cmd->hashlen, cmd->hmacpad, (unsigned char *)cmd->hashdest); nlm_crypto_form_srcdst_segs(cmd); ret = nlm_crypto_complete_sec_request(sc, cmd); return (ret); } int nlm_crypto_do_cipher_digest(struct xlp_sec_softc *sc, struct xlp_sec_command *cmd) { struct cryptodesc *cipdesc=NULL, *digdesc=NULL; unsigned char *cipkey = NULL; int ret=0; cipdesc = cmd->enccrd; digdesc = cmd->maccrd; cipkey = (unsigned char *)cipdesc->crd_key; if (cmd->cipheralg == NLM_CIPHER_3DES) { if (!(cipdesc->crd_flags & CRD_F_ENCRYPT)) { uint64_t *k, *tkey; k = (uint64_t *)cipdesc->crd_key; tkey = (uint64_t *)cmd->des3key; tkey[2] = k[0]; tkey[1] = k[1]; tkey[0] = k[2]; cipkey = (unsigned char *)tkey; } } nlm_crypto_fill_pkt_ctrl(cmd->ctrlp, (digdesc->crd_klen) ? 1 : 0, cmd->hashalg, cmd->hashmode, cmd->cipheralg, cmd->ciphermode, cipkey, (cipdesc->crd_klen >> 3), digdesc->crd_key, (digdesc->crd_klen >> 3)); nlm_crypto_fill_cipher_auth_pkt_param(cmd->ctrlp, cmd->paramp, (cipdesc->crd_flags & CRD_F_ENCRYPT) ? 1 : 0, cmd->hashsrc, cmd->ivoff, cmd->ivlen, cmd->hashoff, cmd->hashlen, cmd->hmacpad, cmd->cipheroff, cmd->cipherlen, (unsigned char *)cmd->hashdest); nlm_crypto_form_srcdst_segs(cmd); ret = nlm_crypto_complete_sec_request(sc, cmd); return (ret); } int nlm_get_digest_param(struct xlp_sec_command *cmd) { switch(cmd->maccrd->crd_alg) { case CRYPTO_MD5: cmd->hashalg = NLM_HASH_MD5; cmd->hashmode = NLM_HASH_MODE_SHA1; break; case CRYPTO_SHA1: cmd->hashalg = NLM_HASH_SHA; cmd->hashmode = NLM_HASH_MODE_SHA1; break; case CRYPTO_MD5_HMAC: cmd->hashalg = NLM_HASH_MD5; cmd->hashmode = NLM_HASH_MODE_SHA1; break; case CRYPTO_SHA1_HMAC: cmd->hashalg = NLM_HASH_SHA; cmd->hashmode = NLM_HASH_MODE_SHA1; break; default: /* Not supported */ return (-1); } return (0); } int nlm_get_cipher_param(struct xlp_sec_command *cmd) { switch(cmd->enccrd->crd_alg) { case CRYPTO_DES_CBC: cmd->cipheralg = NLM_CIPHER_DES; cmd->ciphermode = NLM_CIPHER_MODE_CBC; cmd->ivlen = XLP_SEC_DES_IV_LENGTH; break; case CRYPTO_3DES_CBC: cmd->cipheralg = NLM_CIPHER_3DES; cmd->ciphermode = NLM_CIPHER_MODE_CBC; cmd->ivlen = XLP_SEC_DES_IV_LENGTH; break; case CRYPTO_AES_CBC: cmd->cipheralg = NLM_CIPHER_AES128; cmd->ciphermode = NLM_CIPHER_MODE_CBC; cmd->ivlen = XLP_SEC_AES_IV_LENGTH; break; case CRYPTO_ARC4: cmd->cipheralg = NLM_CIPHER_ARC4; cmd->ciphermode = NLM_CIPHER_MODE_ECB; cmd->ivlen = XLP_SEC_ARC4_IV_LENGTH; break; default: /* Not supported */ return (-1); } return (0); } Index: head/sys/mips/nlm/dev/sec/nlmseclib.h =================================================================== --- head/sys/mips/nlm/dev/sec/nlmseclib.h (revision 279387) +++ head/sys/mips/nlm/dev/sec/nlmseclib.h (revision 279388) @@ -1,157 +1,157 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _NLMSECLIB_H_ #define _NLMSECLIB_H_ /* * Cryptographic parameter definitions */ #define XLP_SEC_DES_KEY_LENGTH 8 /* Bytes */ #define XLP_SEC_3DES_KEY_LENGTH 24 /* Bytes */ #define XLP_SEC_AES128_KEY_LENGTH 16 /* Bytes */ #define XLP_SEC_AES192_KEY_LENGTH 24 /* Bytes */ #define XLP_SEC_AES256_KEY_LENGTH 32 /* Bytes */ #define XLP_SEC_AES128F8_KEY_LENGTH 32 /* Bytes */ #define XLP_SEC_AES192F8_KEY_LENGTH 48 /* Bytes */ #define XLP_SEC_AES256F8_KEY_LENGTH 64 /* Bytes */ #define XLP_SEC_KASUMI_F8_KEY_LENGTH 16 /* Bytes */ #define XLP_SEC_MAX_CRYPT_KEY_LENGTH XLP_SEC_AES256F8_KEY_LENGTH #define XLP_SEC_DES_IV_LENGTH 8 /* Bytes */ #define XLP_SEC_AES_IV_LENGTH 16 /* Bytes */ #define XLP_SEC_ARC4_IV_LENGTH 0 /* Bytes */ #define XLP_SEC_KASUMI_F8_IV_LENGTH 16 /* Bytes */ #define XLP_SEC_MAX_IV_LENGTH 16 /* Bytes */ #define XLP_SEC_IV_LENGTH_BYTES 8 /* Bytes */ #define XLP_SEC_AES_BLOCK_SIZE 16 /* Bytes */ #define XLP_SEC_DES_BLOCK_SIZE 8 /* Bytes */ #define XLP_SEC_3DES_BLOCK_SIZE 8 /* Bytes */ #define XLP_SEC_MD5_BLOCK_SIZE 64 /* Bytes */ #define XLP_SEC_SHA1_BLOCK_SIZE 64 /* Bytes */ #define XLP_SEC_SHA256_BLOCK_SIZE 64 /* Bytes */ #define XLP_SEC_SHA384_BLOCK_SIZE 128 /* Bytes */ #define XLP_SEC_SHA512_BLOCK_SIZE 128 /* Bytes */ #define XLP_SEC_GCM_BLOCK_SIZE 16 /* XXX: Bytes */ #define XLP_SEC_KASUMI_F9_BLOCK_SIZE 16 /* XXX: Bytes */ #define XLP_SEC_MAX_BLOCK_SIZE 64 /* Max of MD5/SHA */ #define XLP_SEC_MD5_LENGTH 16 /* Bytes */ #define XLP_SEC_SHA1_LENGTH 20 /* Bytes */ #define XLP_SEC_SHA256_LENGTH 32 /* Bytes */ #define XLP_SEC_SHA384_LENGTH 64 /* Bytes */ #define XLP_SEC_SHA512_LENGTH 64 /* Bytes */ #define XLP_SEC_GCM_LENGTH 16 /* Bytes */ #define XLP_SEC_KASUMI_F9_LENGTH 16 /* Bytes */ #define XLP_SEC_KASUMI_F9_RESULT_LENGTH 4 /* Bytes */ #define XLP_SEC_HMAC_LENGTH 64 /* Max of MD5/SHA/SHA256 */ #define XLP_SEC_MAX_AUTH_KEY_LENGTH XLP_SEC_SHA512_BLOCK_SIZE #define XLP_SEC_MAX_RC4_STATE_SIZE 264 /* char s[256], int i, int j */ #define XLP_SEC_SESSION(sid) ((sid) & 0x000007ff) #define XLP_SEC_SID(crd,ses) (((crd) << 28) | ((ses) & 0x7ff)) #define CRYPTO_ERROR(msg1) ((unsigned int)msg1) #define NLM_CRYPTO_LEFT_REQS (CMS_DEFAULT_CREDIT/2) #define NLM_CRYPTO_NUM_SEGS_REQD(__bufsize) \ ((__bufsize + NLM_CRYPTO_MAX_SEG_LEN - 1) / NLM_CRYPTO_MAX_SEG_LEN) #define NLM_CRYPTO_PKT_DESC_SIZE(nsegs) (32 + (nsegs * 16)) extern unsigned int creditleft; struct xlp_sec_command { uint16_t session_num; struct cryptop *crp; struct cryptodesc *enccrd, *maccrd; struct xlp_sec_session *ses; struct nlm_crypto_pkt_ctrl *ctrlp; struct nlm_crypto_pkt_param *paramp; void *iv; uint8_t des3key[24]; uint8_t *hashdest; uint8_t hashsrc; uint8_t hmacpad; uint32_t hashoff; uint32_t hashlen; uint32_t cipheroff; - uint32_t cipherlen; + uint32_t cipherlen; uint32_t ivoff; uint32_t ivlen; uint32_t hashalg; uint32_t hashmode; uint32_t cipheralg; - uint32_t ciphermode; + uint32_t ciphermode; uint32_t nsegs; uint32_t hash_dst_len; /* used to store hash alg dst size */ }; struct xlp_sec_session { uint32_t sessionid; int hs_used; int hs_mlen; uint8_t ses_iv[EALG_MAX_BLOCK_LEN]; struct xlp_sec_command cmd; }; /* * Holds data specific to nlm security accelerators */ struct xlp_sec_softc { device_t sc_dev; /* device backpointer */ uint64_t sec_base; int32_t sc_cid; struct xlp_sec_session *sc_sessions; int sc_nsessions; int sc_needwakeup; uint32_t sec_vc_start; uint32_t sec_vc_end; uint32_t sec_msgsz; }; #ifdef NLM_SEC_DEBUG void print_crypto_params(struct xlp_sec_command *cmd, struct nlm_fmn_msg m); void xlp_sec_print_data(struct cryptop *crp); void print_cmd(struct xlp_sec_command *cmd); #endif int nlm_crypto_form_srcdst_segs(struct xlp_sec_command *cmd); int nlm_crypto_do_cipher(struct xlp_sec_softc *sc, struct xlp_sec_command *cmd); int nlm_crypto_do_digest(struct xlp_sec_softc *sc, struct xlp_sec_command *cmd); int nlm_crypto_do_cipher_digest(struct xlp_sec_softc *sc, struct xlp_sec_command *cmd); int nlm_get_digest_param(struct xlp_sec_command *cmd); int nlm_get_cipher_param(struct xlp_sec_command *cmd); #endif /* _NLMSECLIB_H_ */ Index: head/sys/mips/nlm/dev/sec/rsa_ucode.h =================================================================== --- head/sys/mips/nlm/dev/sec/rsa_ucode.h (revision 279387) +++ head/sys/mips/nlm/dev/sec/rsa_ucode.h (revision 279388) @@ -1,956 +1,956 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _NLM_HAL_RSA_UCODE_H #define _NLM_HAL_RSA_UCODE_H static uint64_t nlm_rsa_ucode_data [] = { 0x0000000000000000ULL, 0x00000000503840ecULL, 0x00000001903800ecULL, 0x00000002c03820ecULL, 0x0000003760000044ULL, 0x0000000000000014ULL, 0x000000071000000cULL, 0x00000007d000010cULL, 0x0000001b80000c0cULL, 0x00000000e03fc0ecULL, 0x00000001103fc1ecULL, 0x00000001403f42ecULL, 0x00000001403fc4ecULL, 0x0000003760000044ULL, 0x000000001800003cULL, 0x0000000d8000030cULL, 0x0000000630000044ULL, 0x000000002800003cULL, 0x0000000ef000030cULL, 0x0000000630000044ULL, 0x00000000503fc23cULL, 0x00000000a03fc33cULL, 0x00000001403fc43cULL, 0x00000010c000030cULL, 0x0000000630000044ULL, 0x0000000000000014ULL, 0x000000071000000cULL, 0x0000001c1000070cULL, 0x0000002500000d0cULL, 0x00000027c0000e0cULL, 0x0000002d60000f0cULL, 0x00000002603f00ecULL, 0x00000002603f82ecULL, 0x00000002803f83ecULL, 0x00000002803f04ecULL, 0x00000002a03f06ecULL, 0x00000002a03f88ecULL, 0x0000003760000044ULL, 0x000000086000010cULL, 0x00000003f0000044ULL, 0x00000008d000010cULL, 0x00000004b0000044ULL, 0x00000008d000010cULL, 0x0000000570000044ULL, 0x000000000000001cULL, 0x000000076000000cULL, 0x0000001c1000070cULL, 0x0000002690000d0cULL, 0x0000002990000e0cULL, 0x0000002e10000f0cULL, 0x00000003903f20ecULL, 0x00000003903fa2ecULL, 0x00000003b03fa3ecULL, 0x00000003b03f24ecULL, 0x00000003d03f26ecULL, 0x00000003d03fa8ecULL, 0x0000003760000044ULL, 0x000000096000010cULL, 0x00000003f0000044ULL, 0x0000000a0000010cULL, 0x00000004b0000044ULL, 0x0000000a0000010cULL, 0x0000000570000044ULL, 0x000000000800003cULL, 0x0000000af000020cULL, 0x0000000bc000030cULL, 0x000000129000040cULL, 0x000000178000050cULL, 0x000000191000060cULL, 0x0000001ff000080cULL, 0x000000205000090cULL, 0x00000022c0000a0cULL, 0x00000020b0000b0cULL, 0x0000001ac0000c0cULL, 0x0000000680000044ULL, 0x000000001000003cULL, 0x0000000b5000020cULL, 0x0000000c5000030cULL, 0x000000137000040cULL, 0x00000017e000050cULL, 0x000000197000060cULL, 0x000000200000080cULL, 0x000000206000090cULL, 0x0000002340000a0cULL, 0x0000002110000b0cULL, 0x0000001b10000c0cULL, 0x0000000680000044ULL, 0x000000001800003cULL, 0x0000000b5000020cULL, 0x0000000d8000030cULL, 0x000000154000040cULL, 0x000000187000050cULL, 0x0000001a0000060cULL, 0x000000202000080cULL, 0x000000208000090cULL, 0x0000002410000a0cULL, 0x00000021c0000b0cULL, 0x0000001b80000c0cULL, 0x0000000680000044ULL, 0x000000000000000aULL, 0x0000000000000024ULL, 0x0000002ed01f80e4ULL, 0x00000030101f81e4ULL, 0x0000003760000044ULL, 0x000000000000000aULL, 0x0000000000000024ULL, 0x00000030d01f00e4ULL, 0x00000030d01f82e4ULL, 0x00000034801f83e4ULL, 0x00000035401e04e4ULL, 0x00000037101f88e4ULL, 0x00000035401f89e4ULL, 0x0000003760000044ULL, 0x0000000000000074ULL, 0x0000000f0000008cULL, 0x00000008000000a4ULL, 0x000000080400007bULL, 0x00000000000000c4ULL, 0x0000000000000074ULL, 0x0000000c000000a4ULL, 0x0000000004004071ULL, 0x0000000b0000008cULL, 0x00000008000000a4ULL, 0x000000080400007bULL, 0x00000000000000c4ULL, 0x000000034c0b4091ULL, 0x0000000b040b0093ULL, 0x0000000000000000ULL, 0x0000000004000802ULL, 0x00000002c88b0021ULL, 0x0000000a828b0423ULL, 0x00000010000000a4ULL, 0x000000081000006cULL, 0x00000000000000c4ULL, 0x000000004c0b4091ULL, 0x00000008000000a4ULL, 0x0000000002000402ULL, 0x000000004a8b0021ULL, 0x00000010000000a4ULL, 0x000000089000006cULL, 0x00000000000000c4ULL, 0x000000034c0b4091ULL, 0x0000000b040b0093ULL, 0x00000008000000a4ULL, 0x0000000002000402ULL, 0x00000002c88b0021ULL, 0x0000000a828b0423ULL, 0x00000010000000a4ULL, 0x000000091000006cULL, 0x00000000000000c4ULL, 0x000000004c0b4091ULL, 0x00000008000000a4ULL, 0x0000000002000402ULL, 0x000000004a8b0021ULL, 0x00000010000000a4ULL, 0x0000000990000064ULL, 0x000000004a8b0021ULL, 0x0000000000898611ULL, 0x0000000c000000a4ULL, 0x00000000000000c4ULL, 0x000000034c0b4091ULL, 0x0000000b040b0093ULL, 0x00000008000000a4ULL, 0x0000000002000402ULL, 0x00000002c88b0021ULL, 0x0000000a828b0423ULL, 0x00000010000000a4ULL, 0x0000000a40000064ULL, 0x0000000088800021ULL, 0x0000000880800423ULL, 0x00000000001004a1ULL, 0x0000000c000000a4ULL, 0x00000002c88b0061ULL, 0x0000000a808b0463ULL, 0x00000000000000c4ULL, 0x00000000058f0011ULL, 0x0000000001860002ULL, 0x00000010000000a4ULL, 0x00000000000000ccULL, 0x000000004d8f0021ULL, 0x0000000b10000044ULL, 0x00000007058f0013ULL, 0x0000000001860002ULL, 0x00000010000000a4ULL, 0x00000000000000ccULL, 0x000000034c0f0021ULL, 0x0000000b058f0423ULL, 0x0000000b70000044ULL, 0x0000000000180001ULL, 0x000000000b600031ULL, 0x00000008000000a4ULL, 0x0000000004800041ULL, 0x00000008000000a4ULL, 0x0000000007c03f41ULL, 0x00000000440ac491ULL, 0x00000004000000a4ULL, 0x00000000000000c4ULL, 0x0000000010180001ULL, 0x0000000088a00031ULL, 0x00000002c3430431ULL, 0x00000004000000a4ULL, 0x0000000204938041ULL, 0x00000008000000a4ULL, 0x000000012c002b41ULL, 0x0000000117982861ULL, 0x0000000088a03631ULL, 0x00000002c3430c31ULL, 0x00000004000000a4ULL, 0x0000000204938041ULL, 0x00000008000000a4ULL, 0x000000012c002b41ULL, 0x0000000347cb2861ULL, 0x000000034c09f691ULL, 0x00000003040a8491ULL, 0x0000000000000000ULL, 0x00000000000000c4ULL, 0x0000000010180001ULL, 0x0000000088a00031ULL, 0x00000002c0830431ULL, 0x0000000283430431ULL, 0x000000080000009cULL, 0x0000000204938041ULL, 0x00000008000000a4ULL, 0x000000012c002b41ULL, 0x0000000104202861ULL, 0x0000000117d82861ULL, 0x0000000088a02f31ULL, 0x00000002c0833c31ULL, 0x0000002283430c3bULL, 0x0000000000000000ULL, 0x0000000204938041ULL, 0x00000008000000a4ULL, 0x000000012c002b41ULL, 0x00000003442b2861ULL, 0x0000000307cb2861ULL, 0x000000034c09ef91ULL, 0x000000030409bc91ULL, 0x00000003040a8491ULL, 0x00000000000000c4ULL, 0x0000000010180001ULL, 0x0000000088a00031ULL, 0x00000002c0830431ULL, 0x0000000280830431ULL, 0x0000000280c30431ULL, 0x0000000004900041ULL, 0x0000000283430531ULL, 0x0000000a00038007ULL, 0x0000000000000000ULL, 0x000000012c002b41ULL, 0x0000000344202861ULL, 0x0000001304032863ULL, 0x0000000317db2861ULL, 0x00000000b8a02b31ULL, 0x00000002c0832831ULL, 0x0000000280832831ULL, 0x0000000280c33c31ULL, 0x0000000004900041ULL, 0x0000002e83430d3bULL, 0x0000000200038000ULL, 0x0000000000000000ULL, 0x000000012c002b41ULL, 0x00000003442b2861ULL, 0x00000013040b2863ULL, 0x0000000307cb2861ULL, 0x000000037c09eb91ULL, 0x000000130409a893ULL, 0x000000030409bc91ULL, 0x00000003040a849dULL, 0x0000000010180001ULL, 0x0000000088a00031ULL, 0x00000002c0830431ULL, 0x0000000280830431ULL, 0x0000000280c30431ULL, 0x0000000004900041ULL, 0x0000000280830531ULL, 0x0000001e80830433ULL, 0x0000000283430431ULL, 0x0000000b2c03ab67ULL, 0x0000000344202861ULL, 0x0000001304032863ULL, 0x0000000317db2861ULL, 0x00000002b8a3ab31ULL, 0x00000002c0832831ULL, 0x0000000280832831ULL, 0x0000000280c32831ULL, 0x0000000004900041ULL, 0x0000000280832931ULL, 0x0000001e80832833ULL, 0x0000002e83430c3bULL, 0x000000032c03ab61ULL, 0x00000003442b2861ULL, 0x00000013040b2863ULL, 0x0000000307cb2861ULL, 0x000000037c09eb91ULL, 0x000000130409a893ULL, 0x000000030409bc91ULL, 0x00000003040a849dULL, 0x0000000000140001ULL, 0x0000004000140001ULL, 0x000000000b600061ULL, 0x000000400b600061ULL, 0x00000004000000a4ULL, 0x0000000004800041ULL, 0x0000004004800041ULL, 0x00000004000000a4ULL, 0x0000000007c03f41ULL, 0x0000004007c03f41ULL, 0x00000000440ac591ULL, 0x00000040440ac591ULL, 0x0000000000000000ULL, 0x00000000000000c4ULL, 0x0000000010140001ULL, 0x0000004010140001ULL, 0x0000000088e00061ULL, 0x0000004088e00061ULL, 0x00000002c3430561ULL, 0x00000042c3430561ULL, 0x0000000204938041ULL, 0x0000004204938041ULL, 0x00000004000000a4ULL, 0x000000012c402b41ULL, 0x000000412c402b41ULL, 0x0000000117f42961ULL, 0x0000004117f42961ULL, 0x0000000088e03f61ULL, 0x0000004088e03f61ULL, 0x00000002c3430d61ULL, 0x00000042c3430d61ULL, 0x0000000204938041ULL, 0x0000004204938041ULL, 0x00000004000000a4ULL, 0x000000012c402b41ULL, 0x000000412c402b41ULL, 0x0000000347eb2961ULL, 0x0000004347eb2961ULL, 0x000000034c7dff91ULL, 0x000000434c7dff91ULL, 0x00000003040a0591ULL, 0x00000043040a0591ULL, 0x00000000000000c4ULL, 0x0000000010140001ULL, 0x0000004010140001ULL, 0x0000000088e00061ULL, 0x0000004088e00061ULL, 0x00000002c0c30561ULL, 0x00000042c0c30561ULL, 0x0000000004900041ULL, 0x0000004004900041ULL, 0x0000000283430561ULL, 0x0000004283430561ULL, 0x0000000b2c43ab47ULL, 0x000000432c43ab41ULL, 0x0000000344602961ULL, 0x0000004344602961ULL, 0x0000000317d72961ULL, 0x0000004317d72961ULL, 0x00000002b8e3ab61ULL, 0x00000042b8e3ab61ULL, 0x00000002c0c32961ULL, 0x00000042c0c32961ULL, 0x0000000004900041ULL, 0x0000004004900041ULL, 0x0000000283430d61ULL, 0x0000007683430d6bULL, 0x000000032c43ab41ULL, 0x000000432c43ab41ULL, 0x00000003446b2961ULL, 0x00000043446b2961ULL, 0x0000000307cb2961ULL, 0x0000004307cb2961ULL, 0x000000037c7de791ULL, 0x000000437c7de791ULL, 0x0000000304499d91ULL, 0x0000004304499d91ULL, 0x00000003040a0591ULL, 0x00000043040a059dULL, 0x0000000048840011ULL, 0x00000000028b3691ULL, 0x000000000e09c691ULL, 0x000000000c09c691ULL, 0x0000000000000000ULL, 0x00000000000000c4ULL, 0x00000000c8840011ULL, 0x0000000212ab3691ULL, 0x0000000080800411ULL, 0x0000000002cb3691ULL, 0x000000034c29ef91ULL, 0x0000000006098491ULL, 0x000000034c09ef91ULL, 0x0000000004098491ULL, 0x00000000000000c4ULL, 0x00000000e8840011ULL, 0x0000000210ab3a91ULL, 0x0000000880800415ULL, 0x00000006128b3699ULL, 0x000000034c29eb91ULL, 0x0000000f0409a893ULL, 0x0000000026098891ULL, 0x000000034c09eb91ULL, 0x0000000f0409a893ULL, 0x000000000409849dULL, 0x0000000048841011ULL, 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0x0000000000000000ULL, 0x0000000000000000ULL, }; #endif /* _NLM_HAL_RSA_UCODE_H_ */